From 620742250b1386f9c5f8473c887c55502a143ce3 Mon Sep 17 00:00:00 2001
From: SEEKFREE_BUDING <2289331269@qq.com>
Date: Fri, 3 Mar 2023 15:46:47 +0800
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---
Example/E15_fft_demo/.cproject | 1198 +
Example/E15_fft_demo/.project | 40 +
.../com.infineon.aurix.buildsystem.prefs | 10 +
.../org.eclipse.core.resources.prefs | 1 +
.../E15_fft_demo/Lcf_Tasking_Tricore_Tc.lsl | 449 +
Example/E15_fft_demo/code/本文件夹作用.txt | 3 +
.../doc/GPL3_permission_statement.txt | 13 +
.../E15_fft_demo/libraries/doc/version.txt | 181 +
.../Configurations/Ifx_Cfg.h | 53 +
.../Platform/Tricore/Compilers/CompilerDcc.c | 76 +
.../Platform/Tricore/Compilers/CompilerDcc.h | 170 +
.../Platform/Tricore/Compilers/CompilerGhs.c | 113 +
.../Platform/Tricore/Compilers/CompilerGhs.h | 173 +
.../Platform/Tricore/Compilers/CompilerGnuc.c | 153 +
.../Platform/Tricore/Compilers/CompilerGnuc.h | 186 +
.../Tricore/Compilers/CompilerTasking.c | 65 +
.../Tricore/Compilers/CompilerTasking.h | 165 +
.../Platform/Tricore/Compilers/Compilers.h | 144 +
.../Infra/Sfr/TC26B/_Reg/IfxAsclin_bf.h | 1764 +
.../Infra/Sfr/TC26B/_Reg/IfxAsclin_reg.h | 468 +
.../Infra/Sfr/TC26B/_Reg/IfxAsclin_regdef.h | 699 +
.../Infra/Sfr/TC26B/_Reg/IfxCan_bf.h | 2214 +
.../Infra/Sfr/TC26B/_Reg/IfxCan_reg.h | 33560 ++++++++++++++++
.../Infra/Sfr/TC26B/_Reg/IfxCan_regdef.h | 1093 +
.../Infra/Sfr/TC26B/_Reg/IfxCbs_bf.h | 2493 ++
.../Infra/Sfr/TC26B/_Reg/IfxCbs_reg.h | 269 +
.../Infra/Sfr/TC26B/_Reg/IfxCbs_regdef.h | 957 +
.../Infra/Sfr/TC26B/_Reg/IfxCcu6_bf.h | 2394 ++
.../Infra/Sfr/TC26B/_Reg/IfxCcu6_reg.h | 329 +
.../Infra/Sfr/TC26B/_Reg/IfxCcu6_regdef.h | 1032 +
.../Infra/Sfr/TC26B/_Reg/IfxCif_bf.h | 4959 +++
.../Infra/Sfr/TC26B/_Reg/IfxCif_reg.h | 2362 ++
.../Infra/Sfr/TC26B/_Reg/IfxCif_regdef.h | 3367 ++
.../Infra/Sfr/TC26B/_Reg/IfxCpu_bf.h | 1845 +
.../Infra/Sfr/TC26B/_Reg/IfxCpu_reg.h | 2452 ++
.../Infra/Sfr/TC26B/_Reg/IfxCpu_regdef.h | 1427 +
.../Infra/Sfr/TC26B/_Reg/IfxDma_bf.h | 2700 ++
.../Infra/Sfr/TC26B/_Reg/IfxDma_reg.h | 5041 +++
.../Infra/Sfr/TC26B/_Reg/IfxDma_regdef.h | 1152 +
.../Infra/Sfr/TC26B/_Reg/IfxDsadc_bf.h | 1647 +
.../Infra/Sfr/TC26B/_Reg/IfxDsadc_reg.h | 435 +
.../Infra/Sfr/TC26B/_Reg/IfxDsadc_regdef.h | 761 +
.../Infra/Sfr/TC26B/_Reg/IfxEbcu_bf.h | 621 +
.../Infra/Sfr/TC26B/_Reg/IfxEbcu_reg.h | 123 +
.../Infra/Sfr/TC26B/_Reg/IfxEbcu_regdef.h | 264 +
.../Infra/Sfr/TC26B/_Reg/IfxEmem_bf.h | 954 +
.../Infra/Sfr/TC26B/_Reg/IfxEmem_reg.h | 78 +
.../Infra/Sfr/TC26B/_Reg/IfxEmem_regdef.h | 309 +
.../Infra/Sfr/TC26B/_Reg/IfxEray_bf.h | 10179 +++++
.../Infra/Sfr/TC26B/_Reg/IfxEray_reg.h | 2293 ++
.../Infra/Sfr/TC26B/_Reg/IfxEray_regdef.h | 2761 ++
.../Infra/Sfr/TC26B/_Reg/IfxEth_bf.h | 5224 +++
.../Infra/Sfr/TC26B/_Reg/IfxEth_reg.h | 1003 +
.../Infra/Sfr/TC26B/_Reg/IfxEth_regdef.h | 2712 ++
.../Infra/Sfr/TC26B/_Reg/IfxFce_bf.h | 702 +
.../Infra/Sfr/TC26B/_Reg/IfxFce_reg.h | 363 +
.../Infra/Sfr/TC26B/_Reg/IfxFce_regdef.h | 585 +
.../Infra/Sfr/TC26B/_Reg/IfxFft_bf.h | 360 +
.../Infra/Sfr/TC26B/_Reg/IfxFft_reg.h | 81 +
.../Infra/Sfr/TC26B/_Reg/IfxFft_regdef.h | 264 +
.../Infra/Sfr/TC26B/_Reg/IfxFlash_bf.h | 2538 ++
.../Infra/Sfr/TC26B/_Reg/IfxFlash_reg.h | 282 +
.../Infra/Sfr/TC26B/_Reg/IfxFlash_regdef.h | 901 +
.../Infra/Sfr/TC26B/_Reg/IfxGpt12_bf.h | 1071 +
.../Infra/Sfr/TC26B/_Reg/IfxGpt12_reg.h | 111 +
.../Infra/Sfr/TC26B/_Reg/IfxGpt12_regdef.h | 487 +
.../Infra/Sfr/TC26B/_Reg/IfxGtm_bf.h | 18756 +++++++++
.../Infra/Sfr/TC26B/_Reg/IfxGtm_reg.h | 9076 +++++
.../Infra/Sfr/TC26B/_Reg/IfxGtm_regdef.h | 7844 ++++
.../Infra/Sfr/TC26B/_Reg/IfxHsct_bf.h | 1179 +
.../Infra/Sfr/TC26B/_Reg/IfxHsct_reg.h | 117 +
.../Infra/Sfr/TC26B/_Reg/IfxHsct_regdef.h | 538 +
.../Infra/Sfr/TC26B/_Reg/IfxHssl_bf.h | 1521 +
.../Infra/Sfr/TC26B/_Reg/IfxHssl_reg.h | 428 +
.../Infra/Sfr/TC26B/_Reg/IfxHssl_regdef.h | 772 +
.../Infra/Sfr/TC26B/_Reg/IfxI2c_bf.h | 1359 +
.../Infra/Sfr/TC26B/_Reg/IfxI2c_reg.h | 156 +
.../Infra/Sfr/TC26B/_Reg/IfxI2c_regdef.h | 753 +
.../Infra/Sfr/TC26B/_Reg/IfxInt_bf.h | 990 +
.../Infra/Sfr/TC26B/_Reg/IfxInt_reg.h | 171 +
.../Infra/Sfr/TC26B/_Reg/IfxInt_regdef.h | 482 +
.../Infra/Sfr/TC26B/_Reg/IfxIom_bf.h | 1764 +
.../Infra/Sfr/TC26B/_Reg/IfxIom_reg.h | 331 +
.../Infra/Sfr/TC26B/_Reg/IfxIom_regdef.h | 533 +
.../Infra/Sfr/TC26B/_Reg/IfxLmu_bf.h | 477 +
.../Infra/Sfr/TC26B/_Reg/IfxLmu_reg.h | 75 +
.../Infra/Sfr/TC26B/_Reg/IfxLmu_regdef.h | 214 +
.../Infra/Sfr/TC26B/_Reg/IfxMc_bf.h | 450 +
.../Infra/Sfr/TC26B/_Reg/IfxMc_reg.h | 15000 +++++++
.../Infra/Sfr/TC26B/_Reg/IfxMc_regdef.h | 259 +
.../Infra/Sfr/TC26B/_Reg/IfxMsc_bf.h | 2583 ++
.../Infra/Sfr/TC26B/_Reg/IfxMsc_reg.h | 266 +
.../Infra/Sfr/TC26B/_Reg/IfxMsc_regdef.h | 823 +
.../Infra/Sfr/TC26B/_Reg/IfxMtu_bf.h | 1107 +
.../Infra/Sfr/TC26B/_Reg/IfxMtu_reg.h | 84 +
.../Infra/Sfr/TC26B/_Reg/IfxMtu_regdef.h | 370 +
.../Infra/Sfr/TC26B/_Reg/IfxOvc_bf.h | 378 +
.../Infra/Sfr/TC26B/_Reg/IfxOvc_reg.h | 1604 +
.../Infra/Sfr/TC26B/_Reg/IfxOvc_regdef.h | 185 +
.../Infra/Sfr/TC26B/_Reg/IfxPmu_bf.h | 63 +
.../Infra/Sfr/TC26B/_Reg/IfxPmu_reg.h | 54 +
.../Infra/Sfr/TC26B/_Reg/IfxPmu_regdef.h | 85 +
.../Infra/Sfr/TC26B/_Reg/IfxPort_bf.h | 2430 ++
.../Infra/Sfr/TC26B/_Reg/IfxPort_reg.h | 980 +
.../Infra/Sfr/TC26B/_Reg/IfxPort_regdef.h | 785 +
.../Infra/Sfr/TC26B/_Reg/IfxPsi5_bf.h | 11997 ++++++
.../Infra/Sfr/TC26B/_Reg/IfxPsi5_reg.h | 1832 +
.../Infra/Sfr/TC26B/_Reg/IfxPsi5_regdef.h | 2510 ++
.../Infra/Sfr/TC26B/_Reg/IfxPsi5s_bf.h | 3321 ++
.../Infra/Sfr/TC26B/_Reg/IfxPsi5s_reg.h | 468 +
.../Infra/Sfr/TC26B/_Reg/IfxPsi5s_regdef.h | 1168 +
.../Infra/Sfr/TC26B/_Reg/IfxQspi_bf.h | 1251 +
.../Infra/Sfr/TC26B/_Reg/IfxQspi_reg.h | 534 +
.../Infra/Sfr/TC26B/_Reg/IfxQspi_regdef.h | 565 +
.../Infra/Sfr/TC26B/_Reg/IfxSbcu_bf.h | 1143 +
.../Infra/Sfr/TC26B/_Reg/IfxSbcu_reg.h | 195 +
.../Infra/Sfr/TC26B/_Reg/IfxSbcu_regdef.h | 460 +
.../Infra/Sfr/TC26B/_Reg/IfxScu_bf.h | 4932 +++
.../Infra/Sfr/TC26B/_Reg/IfxScu_reg.h | 405 +
.../Infra/Sfr/TC26B/_Reg/IfxScu_regdef.h | 2107 +
.../Infra/Sfr/TC26B/_Reg/IfxSent_bf.h | 1674 +
.../Infra/Sfr/TC26B/_Reg/IfxSent_reg.h | 795 +
.../Infra/Sfr/TC26B/_Reg/IfxSent_regdef.h | 699 +
.../Infra/Sfr/TC26B/_Reg/IfxSmu_bf.h | 2700 ++
.../Infra/Sfr/TC26B/_Reg/IfxSmu_reg.h | 383 +
.../Infra/Sfr/TC26B/_Reg/IfxSmu_regdef.h | 758 +
.../Infra/Sfr/TC26B/_Reg/IfxSrc_bf.h | 135 +
.../Infra/Sfr/TC26B/_Reg/IfxSrc_reg.h | 3107 ++
.../Infra/Sfr/TC26B/_Reg/IfxSrc_regdef.h | 676 +
.../Infra/Sfr/TC26B/_Reg/IfxStm_bf.h | 666 +
.../Infra/Sfr/TC26B/_Reg/IfxStm_reg.h | 200 +
.../Infra/Sfr/TC26B/_Reg/IfxStm_regdef.h | 463 +
.../Infra/Sfr/TC26B/_Reg/IfxVadc_bf.h | 4194 ++
.../Infra/Sfr/TC26B/_Reg/IfxVadc_reg.h | 3341 ++
.../Infra/Sfr/TC26B/_Reg/IfxVadc_regdef.h | 1565 +
.../Infra/Sfr/TC26B/_Reg/IfxXbar_bf.h | 1251 +
.../Infra/Sfr/TC26B/_Reg/IfxXbar_reg.h | 523 +
.../Infra/Sfr/TC26B/_Reg/IfxXbar_regdef.h | 754 +
.../Infra/Sfr/TC26B/_Reg/Ifx_TypesReg.h | 74 +
.../Infra/Sfr/TC26B/_Reg/Ifx_reg.h | 90 +
.../Infra/Sfr/TC26B/_Reg/_package.xml | 630 +
.../Service/CpuGeneric/If/Ccu6If/Icu.h | 87 +
.../Service/CpuGeneric/If/Ccu6If/PwmHl.h | 95 +
.../Service/CpuGeneric/If/Ccu6If/TPwm.h | 94 +
.../Service/CpuGeneric/If/Ccu6If/Timer.h | 103 +
.../Service/CpuGeneric/If/SpiIf.c | 81 +
.../Service/CpuGeneric/If/SpiIf.h | 291 +
.../Service/CpuGeneric/If/info.dox | 6 +
.../Service/CpuGeneric/StdIf/IfxStdIf.h | 120 +
.../Service/CpuGeneric/StdIf/IfxStdIf_DPipe.c | 72 +
.../Service/CpuGeneric/StdIf/IfxStdIf_DPipe.h | 401 +
.../Service/CpuGeneric/StdIf/IfxStdIf_Pos.c | 97 +
.../Service/CpuGeneric/StdIf/IfxStdIf_Pos.h | 583 +
.../Service/CpuGeneric/StdIf/IfxStdIf_PwmHl.c | 58 +
.../Service/CpuGeneric/StdIf/IfxStdIf_PwmHl.h | 322 +
.../Service/CpuGeneric/StdIf/IfxStdIf_Timer.c | 165 +
.../Service/CpuGeneric/StdIf/IfxStdIf_Timer.h | 481 +
.../StandardInterfaceDataPipeExample.png | Bin 0 -> 13687 bytes
.../StdIf/StandardInterfaceLayers.png | Bin 0 -> 4919 bytes
.../StdIf/StandardInterfaceTimerExample.png | Bin 0 -> 12542 bytes
.../Service/CpuGeneric/StdIf/Timer.png | Bin 0 -> 7988 bytes
.../Service/CpuGeneric/SysSe/Bsp/Assert.c | 127 +
.../Service/CpuGeneric/SysSe/Bsp/Assert.h | 209 +
.../Service/CpuGeneric/SysSe/Bsp/Bsp.c | 96 +
.../Service/CpuGeneric/SysSe/Bsp/Bsp.h | 443 +
.../Service/CpuGeneric/SysSe/Bsp/info.dox | 5 +
.../CpuGeneric/SysSe/Comm/Ifx_Console.c | 130 +
.../CpuGeneric/SysSe/Comm/Ifx_Console.h | 115 +
.../Service/CpuGeneric/SysSe/Comm/Ifx_Shell.c | 1335 +
.../Service/CpuGeneric/SysSe/Comm/Ifx_Shell.h | 474 +
.../Service/CpuGeneric/SysSe/Comm/info.dox | 4 +
.../SysSe/General/Ifx_GlobalResources.c | 168 +
.../SysSe/General/Ifx_GlobalResources.h | 107 +
.../Service/CpuGeneric/SysSe/General/info.dox | 4 +
.../CpuGeneric/SysSe/Math/Ifx_AngleTrkF32.c | 464 +
.../CpuGeneric/SysSe/Math/Ifx_AngleTrkF32.h | 309 +
.../Service/CpuGeneric/SysSe/Math/Ifx_Cf32.c | 390 +
.../Service/CpuGeneric/SysSe/Math/Ifx_Cf32.h | 184 +
.../Service/CpuGeneric/SysSe/Math/Ifx_Crc.c | 656 +
.../Service/CpuGeneric/SysSe/Math/Ifx_Crc.h | 130 +
.../CpuGeneric/SysSe/Math/Ifx_FftF32.c | 185 +
.../CpuGeneric/SysSe/Math/Ifx_FftF32.h | 115 +
.../SysSe/Math/Ifx_FftF32_BitReverseTable.c | 16435 ++++++++
.../SysSe/Math/Ifx_FftF32_TwiddleTable.c | 8243 ++++
.../CpuGeneric/SysSe/Math/Ifx_IntegralF32.c | 92 +
.../CpuGeneric/SysSe/Math/Ifx_IntegralF32.h | 109 +
.../CpuGeneric/SysSe/Math/Ifx_LowPassPt1F32.c | 80 +
.../CpuGeneric/SysSe/Math/Ifx_LowPassPt1F32.h | 100 +
.../Service/CpuGeneric/SysSe/Math/Ifx_Lut.h | 97 +
.../CpuGeneric/SysSe/Math/Ifx_LutAtan2F32.c | 204 +
.../CpuGeneric/SysSe/Math/Ifx_LutAtan2F32.h | 76 +
.../SysSe/Math/Ifx_LutAtan2F32_Table.c | 1190 +
.../SysSe/Math/Ifx_LutIndexedLinearF32.h | 96 +
.../CpuGeneric/SysSe/Math/Ifx_LutLSincosF32.c | 201 +
.../CpuGeneric/SysSe/Math/Ifx_LutLSincosF32.h | 107 +
.../CpuGeneric/SysSe/Math/Ifx_LutLinearF32.c | 99 +
.../CpuGeneric/SysSe/Math/Ifx_LutLinearF32.h | 125 +
.../CpuGeneric/SysSe/Math/Ifx_LutSincosF32.c | 90 +
.../CpuGeneric/SysSe/Math/Ifx_LutSincosF32.h | 107 +
.../SysSe/Math/Ifx_LutSincosF32_Table.c | 1089 +
.../CpuGeneric/SysSe/Math/Ifx_RampF32.c | 71 +
.../CpuGeneric/SysSe/Math/Ifx_RampF32.h | 150 +
.../CpuGeneric/SysSe/Math/Ifx_WndF32.h | 74 +
.../Math/Ifx_WndF32_BlackmanHarrisTable.c | 565 +
.../SysSe/Math/Ifx_WndF32_HannTable.c | 565 +
.../Service/CpuGeneric/SysSe/Math/info.dox | 7 +
.../CpuGeneric/SysSe/Time/Ifx_DateTime.c | 73 +
.../CpuGeneric/SysSe/Time/Ifx_DateTime.h | 63 +
.../Service/CpuGeneric/SysSe/Time/info.dox | 5 +
.../Service/CpuGeneric/SysSe/info.dox | 5 +
.../CpuGeneric/_Utilities/Ifx_Assert.h | 93 +
.../Service/CpuGeneric/_Utilities/info.dox | 5 +
.../Service/CpuGeneric/info.dox | 5 +
.../TC26B/Tricore/Asclin/Asc/IfxAsclin_Asc.c | 641 +
.../TC26B/Tricore/Asclin/Asc/IfxAsclin_Asc.h | 615 +
.../TC26B/Tricore/Asclin/Lin/IfxAsclin_Lin.c | 1004 +
.../TC26B/Tricore/Asclin/Lin/IfxAsclin_Lin.h | 858 +
.../TC26B/Tricore/Asclin/Spi/IfxAsclin_Spi.c | 472 +
.../TC26B/Tricore/Asclin/Spi/IfxAsclin_Spi.h | 479 +
.../iLLD/TC26B/Tricore/Asclin/Std/IfxAsclin.c | 416 +
.../iLLD/TC26B/Tricore/Asclin/Std/IfxAsclin.h | 2465 ++
.../iLLD/TC26B/Tricore/Ccu6/Icu/IfxCcu6_Icu.c | 349 +
.../iLLD/TC26B/Tricore/Ccu6/Icu/IfxCcu6_Icu.h | 442 +
.../TC26B/Tricore/Ccu6/PwmBc/IfxCcu6_PwmBc.c | 528 +
.../TC26B/Tricore/Ccu6/PwmBc/IfxCcu6_PwmBc.h | 464 +
.../TC26B/Tricore/Ccu6/PwmHl/IfxCcu6_PwmHl.c | 520 +
.../TC26B/Tricore/Ccu6/PwmHl/IfxCcu6_PwmHl.h | 310 +
.../iLLD/TC26B/Tricore/Ccu6/Std/IfxCcu6.c | 519 +
.../iLLD/TC26B/Tricore/Ccu6/Std/IfxCcu6.h | 2176 +
.../TC26B/Tricore/Ccu6/TPwm/IfxCcu6_TPwm.c | 550 +
.../TC26B/Tricore/Ccu6/TPwm/IfxCcu6_TPwm.h | 417 +
.../TC26B/Tricore/Ccu6/Timer/IfxCcu6_Timer.c | 544 +
.../TC26B/Tricore/Ccu6/Timer/IfxCcu6_Timer.h | 417 +
.../IfxCcu6_TimerWithTrigger.c | 379 +
.../IfxCcu6_TimerWithTrigger.h | 299 +
.../iLLD/TC26B/Tricore/Cif/Cam/IfxCif_Cam.c | 848 +
.../iLLD/TC26B/Tricore/Cif/Cam/IfxCif_Cam.h | 624 +
.../iLLD/TC26B/Tricore/Cif/Std/IfxCif.c | 3964 ++
.../iLLD/TC26B/Tricore/Cif/Std/IfxCif.h | 3040 ++
.../TC26B/Tricore/Cpu/CStart/IfxCpu_CStart.h | 281 +
.../TC26B/Tricore/Cpu/CStart/IfxCpu_CStart0.c | 309 +
.../TC26B/Tricore/Cpu/CStart/IfxCpu_CStart1.c | 148 +
.../iLLD/TC26B/Tricore/Cpu/Irq/IfxCpu_Irq.c | 102 +
.../iLLD/TC26B/Tricore/Cpu/Irq/IfxCpu_Irq.h | 261 +
.../iLLD/TC26B/Tricore/Cpu/Std/IfxCpu.c | 362 +
.../iLLD/TC26B/Tricore/Cpu/Std/IfxCpu.h | 1089 +
.../TC26B/Tricore/Cpu/Std/IfxCpu_Intrinsics.h | 170 +
.../Tricore/Cpu/Std/IfxCpu_IntrinsicsDcc.h | 2123 +
.../Tricore/Cpu/Std/IfxCpu_IntrinsicsGhs.h | 1708 +
.../Tricore/Cpu/Std/IfxCpu_IntrinsicsGnuc.h | 2331 ++
.../Cpu/Std/IfxCpu_IntrinsicsTasking.h | 639 +
.../iLLD/TC26B/Tricore/Cpu/Std/Ifx_Types.h | 227 +
.../iLLD/TC26B/Tricore/Cpu/Std/Ifx_TypesDcc.h | 58 +
.../iLLD/TC26B/Tricore/Cpu/Std/Ifx_TypesGhs.h | 58 +
.../TC26B/Tricore/Cpu/Std/Ifx_TypesGnuc.h | 59 +
.../TC26B/Tricore/Cpu/Std/Ifx_TypesTasking.h | 53 +
.../TC26B/Tricore/Cpu/Std/Platform_Types.h | 187 +
.../iLLD/TC26B/Tricore/Cpu/Trap/IfxCpu_Trap.c | 483 +
.../iLLD/TC26B/Tricore/Cpu/Trap/IfxCpu_Trap.h | 436 +
.../iLLD/TC26B/Tricore/Dma/Dma/IfxDma_Dma.c | 241 +
.../iLLD/TC26B/Tricore/Dma/Dma/IfxDma_Dma.h | 774 +
.../iLLD/TC26B/Tricore/Dma/Std/IfxDma.c | 49 +
.../iLLD/TC26B/Tricore/Dma/Std/IfxDma.h | 1766 +
.../Tricore/Dsadc/Dsadc/IfxDsadc_Dsadc.c | 493 +
.../Tricore/Dsadc/Dsadc/IfxDsadc_Dsadc.h | 539 +
.../TC26B/Tricore/Dsadc/Rdc/IfxDsadc_Rdc.c | 572 +
.../TC26B/Tricore/Dsadc/Rdc/IfxDsadc_Rdc.h | 634 +
.../iLLD/TC26B/Tricore/Dsadc/Std/IfxDsadc.c | 177 +
.../iLLD/TC26B/Tricore/Dsadc/Std/IfxDsadc.h | 760 +
.../iLLD/TC26B/Tricore/Dts/Dts/IfxDts_Dts.c | 138 +
.../iLLD/TC26B/Tricore/Dts/Dts/IfxDts_Dts.h | 323 +
.../iLLD/TC26B/Tricore/Dts/Std/IfxDts.c | 58 +
.../iLLD/TC26B/Tricore/Dts/Std/IfxDts.h | 160 +
.../iLLD/TC26B/Tricore/Emem/Std/IfxEmem.c | 76 +
.../iLLD/TC26B/Tricore/Emem/Std/IfxEmem.h | 187 +
.../TC26B/Tricore/Eray/Eray/IfxEray_Eray.c | 609 +
.../TC26B/Tricore/Eray/Eray/IfxEray_Eray.h | 1324 +
.../iLLD/TC26B/Tricore/Eray/Std/IfxEray.c | 363 +
.../iLLD/TC26B/Tricore/Eray/Std/IfxEray.h | 1845 +
.../Eth/Phy_Pef7071/IfxEth_Phy_Pef7071.c | 243 +
.../Eth/Phy_Pef7071/IfxEth_Phy_Pef7071.h | 111 +
.../iLLD/TC26B/Tricore/Eth/Std/IfxEth.c | 953 +
.../iLLD/TC26B/Tricore/Eth/Std/IfxEth.h | 1684 +
.../iLLD/TC26B/Tricore/Fce/Crc/IfxFce_Crc.c | 286 +
.../iLLD/TC26B/Tricore/Fce/Crc/IfxFce_Crc.h | 565 +
.../iLLD/TC26B/Tricore/Fce/Std/IfxFce.c | 124 +
.../iLLD/TC26B/Tricore/Fce/Std/IfxFce.h | 250 +
.../iLLD/TC26B/Tricore/Fft/Fft/IfxFft_Fft.c | 744 +
.../iLLD/TC26B/Tricore/Fft/Fft/IfxFft_Fft.h | 463 +
.../iLLD/TC26B/Tricore/Fft/Std/IfxFft.c | 49 +
.../iLLD/TC26B/Tricore/Fft/Std/IfxFft.h | 346 +
.../iLLD/TC26B/Tricore/Flash/Std/IfxFlash.c | 176 +
.../iLLD/TC26B/Tricore/Flash/Std/IfxFlash.h | 790 +
.../Tricore/Gpt12/IncrEnc/IfxGpt12_IncrEnc.c | 565 +
.../Tricore/Gpt12/IncrEnc/IfxGpt12_IncrEnc.h | 423 +
.../iLLD/TC26B/Tricore/Gpt12/Std/IfxGpt12.c | 404 +
.../iLLD/TC26B/Tricore/Gpt12/Std/IfxGpt12.h | 1665 +
.../Tricore/Gtm/Atom/Pwm/IfxGtm_Atom_Pwm.c | 161 +
.../Tricore/Gtm/Atom/Pwm/IfxGtm_Atom_Pwm.h | 230 +
.../Gtm/Atom/PwmHl/IfxGtm_Atom_PwmHl.c | 746 +
.../Gtm/Atom/PwmHl/IfxGtm_Atom_PwmHl.h | 308 +
.../Gtm/Atom/Timer/IfxGtm_Atom_Timer.c | 393 +
.../Gtm/Atom/Timer/IfxGtm_Atom_Timer.h | 335 +
.../iLLD/TC26B/Tricore/Gtm/Std/IfxGtm.c | 80 +
.../iLLD/TC26B/Tricore/Gtm/Std/IfxGtm.h | 177 +
.../iLLD/TC26B/Tricore/Gtm/Std/IfxGtm_Atom.c | 567 +
.../iLLD/TC26B/Tricore/Gtm/Std/IfxGtm_Atom.h | 609 +
.../iLLD/TC26B/Tricore/Gtm/Std/IfxGtm_Cmu.c | 424 +
.../iLLD/TC26B/Tricore/Gtm/Std/IfxGtm_Cmu.h | 212 +
.../iLLD/TC26B/Tricore/Gtm/Std/IfxGtm_Dpll.c | 60 +
.../iLLD/TC26B/Tricore/Gtm/Std/IfxGtm_Dpll.h | 74 +
.../iLLD/TC26B/Tricore/Gtm/Std/IfxGtm_Tbu.c | 74 +
.../iLLD/TC26B/Tricore/Gtm/Std/IfxGtm_Tbu.h | 135 +
.../iLLD/TC26B/Tricore/Gtm/Std/IfxGtm_Tim.c | 173 +
.../iLLD/TC26B/Tricore/Gtm/Std/IfxGtm_Tim.h | 385 +
.../iLLD/TC26B/Tricore/Gtm/Std/IfxGtm_Tom.c | 558 +
.../iLLD/TC26B/Tricore/Gtm/Std/IfxGtm_Tom.h | 537 +
.../TC26B/Tricore/Gtm/Tim/In/IfxGtm_Tim_In.c | 341 +
.../TC26B/Tricore/Gtm/Tim/In/IfxGtm_Tim_In.h | 311 +
.../Tricore/Gtm/Tom/Pwm/IfxGtm_Tom_Pwm.c | 171 +
.../Tricore/Gtm/Tom/Pwm/IfxGtm_Tom_Pwm.h | 233 +
.../Tricore/Gtm/Tom/PwmHl/IfxGtm_Tom_PwmHl.c | 774 +
.../Tricore/Gtm/Tom/PwmHl/IfxGtm_Tom_PwmHl.h | 350 +
.../Tricore/Gtm/Tom/Timer/IfxGtm_Tom_Timer.c | 448 +
.../Tricore/Gtm/Tom/Timer/IfxGtm_Tom_Timer.h | 378 +
.../iLLD/TC26B/Tricore/Gtm/Trig/IfxGtm_Trig.c | 314 +
.../iLLD/TC26B/Tricore/Gtm/Trig/IfxGtm_Trig.h | 235 +
.../TC26B/Tricore/Hssl/Hssl/IfxHssl_Hssl.c | 580 +
.../TC26B/Tricore/Hssl/Hssl/IfxHssl_Hssl.h | 780 +
.../iLLD/TC26B/Tricore/Hssl/Std/IfxHssl.c | 243 +
.../iLLD/TC26B/Tricore/Hssl/Std/IfxHssl.h | 965 +
.../iLLD/TC26B/Tricore/I2c/I2c/IfxI2c_I2c.c | 457 +
.../iLLD/TC26B/Tricore/I2c/I2c/IfxI2c_I2c.h | 429 +
.../iLLD/TC26B/Tricore/I2c/Std/IfxI2c.c | 309 +
.../iLLD/TC26B/Tricore/I2c/Std/IfxI2c.h | 945 +
.../iLLD/TC26B/Tricore/IfxLldVersion.h | 10 +
.../TC26B/Tricore/Iom/Driver/IfxIom_Driver.c | 406 +
.../TC26B/Tricore/Iom/Driver/IfxIom_Driver.h | 338 +
.../iLLD/TC26B/Tricore/Iom/Std/IfxIom.c | 85 +
.../iLLD/TC26B/Tricore/Iom/Std/IfxIom.h | 252 +
.../iLLD/TC26B/Tricore/Msc/Msc/IfxMsc_Msc.c | 720 +
.../iLLD/TC26B/Tricore/Msc/Msc/IfxMsc_Msc.h | 606 +
.../iLLD/TC26B/Tricore/Msc/Std/IfxMsc.c | 252 +
.../iLLD/TC26B/Tricore/Msc/Std/IfxMsc.h | 1778 +
.../iLLD/TC26B/Tricore/Mtu/Std/IfxMtu.c | 495 +
.../iLLD/TC26B/Tricore/Mtu/Std/IfxMtu.h | 573 +
.../Tricore/Multican/Can/IfxMultican_Can.c | 1075 +
.../Tricore/Multican/Can/IfxMultican_Can.h | 1317 +
.../TC26B/Tricore/Multican/Std/IfxMultican.c | 1297 +
.../TC26B/Tricore/Multican/Std/IfxMultican.h | 1721 +
.../iLLD/TC26B/Tricore/Port/Io/IfxPort_Io.c | 67 +
.../iLLD/TC26B/Tricore/Port/Io/IfxPort_Io.h | 212 +
.../iLLD/TC26B/Tricore/Port/Std/IfxPort.c | 355 +
.../iLLD/TC26B/Tricore/Port/Std/IfxPort.h | 604 +
.../TC26B/Tricore/Psi5/Psi5/IfxPsi5_Psi5.c | 574 +
.../TC26B/Tricore/Psi5/Psi5/IfxPsi5_Psi5.h | 521 +
.../iLLD/TC26B/Tricore/Psi5/Std/IfxPsi5.c | 91 +
.../iLLD/TC26B/Tricore/Psi5/Std/IfxPsi5.h | 603 +
.../Tricore/Psi5s/Psi5s/IfxPsi5s_Psi5s.c | 657 +
.../Tricore/Psi5s/Psi5s/IfxPsi5s_Psi5s.h | 608 +
.../iLLD/TC26B/Tricore/Psi5s/Std/IfxPsi5s.c | 132 +
.../iLLD/TC26B/Tricore/Psi5s/Std/IfxPsi5s.h | 532 +
.../Qspi/SpiMaster/IfxQspi_SpiMaster.c | 1337 +
.../Qspi/SpiMaster/IfxQspi_SpiMaster.h | 946 +
.../Tricore/Qspi/SpiSlave/IfxQspi_SpiSlave.c | 672 +
.../Tricore/Qspi/SpiSlave/IfxQspi_SpiSlave.h | 555 +
.../iLLD/TC26B/Tricore/Qspi/Std/IfxQspi.c | 518 +
.../iLLD/TC26B/Tricore/Qspi/Std/IfxQspi.h | 1305 +
.../iLLD/TC26B/Tricore/Scu/Std/IfxScuCcu.c | 1364 +
.../iLLD/TC26B/Tricore/Scu/Std/IfxScuCcu.h | 1148 +
.../iLLD/TC26B/Tricore/Scu/Std/IfxScuEru.c | 415 +
.../iLLD/TC26B/Tricore/Scu/Std/IfxScuEru.h | 357 +
.../TC26B/Tricore/Scu/Std/IfxScuWdt.asm.h | 135 +
.../iLLD/TC26B/Tricore/Scu/Std/IfxScuWdt.c | 484 +
.../iLLD/TC26B/Tricore/Scu/Std/IfxScuWdt.h | 570 +
.../TC26B/Tricore/Sent/Sent/IfxSent_Sent.c | 353 +
.../TC26B/Tricore/Sent/Sent/IfxSent_Sent.h | 695 +
.../iLLD/TC26B/Tricore/Sent/Std/IfxSent.c | 164 +
.../iLLD/TC26B/Tricore/Sent/Std/IfxSent.h | 783 +
.../iLLD/TC26B/Tricore/Smu/Std/IfxSmu.c | 321 +
.../iLLD/TC26B/Tricore/Smu/Std/IfxSmu.h | 344 +
.../iLLD/TC26B/Tricore/Src/Std/IfxSrc.c | 49 +
.../iLLD/TC26B/Tricore/Src/Std/IfxSrc.h | 300 +
.../iLLD/TC26B/Tricore/Stm/Std/IfxStm.c | 291 +
.../iLLD/TC26B/Tricore/Stm/Std/IfxStm.h | 698 +
.../TC26B/Tricore/Stm/Timer/IfxStm_Timer.c | 248 +
.../TC26B/Tricore/Stm/Timer/IfxStm_Timer.h | 274 +
.../iLLD/TC26B/Tricore/Vadc/Adc/IfxVadc_Adc.c | 852 +
.../iLLD/TC26B/Tricore/Vadc/Adc/IfxVadc_Adc.h | 1313 +
.../iLLD/TC26B/Tricore/Vadc/Std/IfxVadc.c | 591 +
.../iLLD/TC26B/Tricore/Vadc/Std/IfxVadc.h | 2496 ++
.../iLLD/TC26B/Tricore/_Build/IfxAsclin.xml | 18 +
.../iLLD/TC26B/Tricore/_Build/IfxCcu6.xml | 16 +
.../iLLD/TC26B/Tricore/_Build/IfxCif.xml | 16 +
.../iLLD/TC26B/Tricore/_Build/IfxCpu.xml | 9 +
.../iLLD/TC26B/Tricore/_Build/IfxDma.xml | 8 +
.../iLLD/TC26B/Tricore/_Build/IfxDsadc.xml | 13 +
.../iLLD/TC26B/Tricore/_Build/IfxDts.xml | 11 +
.../iLLD/TC26B/Tricore/_Build/IfxEmem.xml | 9 +
.../iLLD/TC26B/Tricore/_Build/IfxEray.xml | 15 +
.../iLLD/TC26B/Tricore/_Build/IfxEth.xml | 12 +
.../iLLD/TC26B/Tricore/_Build/IfxFce.xml | 11 +
.../iLLD/TC26B/Tricore/_Build/IfxFft.xml | 12 +
.../iLLD/TC26B/Tricore/_Build/IfxFlash.xml | 9 +
.../iLLD/TC26B/Tricore/_Build/IfxGpt12.xml | 12 +
.../iLLD/TC26B/Tricore/_Build/IfxGtm.xml | 27 +
.../iLLD/TC26B/Tricore/_Build/IfxHssl.xml | 12 +
.../iLLD/TC26B/Tricore/_Build/IfxI2c.xml | 13 +
.../iLLD/TC26B/Tricore/_Build/IfxIom.xml | 10 +
.../iLLD/TC26B/Tricore/_Build/IfxMsc.xml | 14 +
.../iLLD/TC26B/Tricore/_Build/IfxMtu.xml | 10 +
.../iLLD/TC26B/Tricore/_Build/IfxMultican.xml | 13 +
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.../iLLD/TC26B/Tricore/_Build/IfxQspi.xml | 17 +
.../iLLD/TC26B/Tricore/_Build/IfxScu.xml | 11 +
.../iLLD/TC26B/Tricore/_Build/IfxSent.xml | 13 +
.../iLLD/TC26B/Tricore/_Build/IfxSmu.xml | 10 +
.../iLLD/TC26B/Tricore/_Build/IfxSrc.xml | 6 +
.../iLLD/TC26B/Tricore/_Build/IfxStm.xml | 10 +
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.../iLLD/TC26B/Tricore/_Impl/IfxAsclin_cfg.c | 60 +
.../iLLD/TC26B/Tricore/_Impl/IfxAsclin_cfg.h | 95 +
.../iLLD/TC26B/Tricore/_Impl/IfxCcu6_cfg.c | 64 +
.../iLLD/TC26B/Tricore/_Impl/IfxCcu6_cfg.h | 113 +
.../iLLD/TC26B/Tricore/_Impl/IfxCif_cfg.c | 49 +
.../iLLD/TC26B/Tricore/_Impl/IfxCif_cfg.h | 79 +
.../iLLD/TC26B/Tricore/_Impl/IfxCpu_cfg.c | 58 +
.../iLLD/TC26B/Tricore/_Impl/IfxCpu_cfg.h | 169 +
.../iLLD/TC26B/Tricore/_Impl/IfxDma_cfg.c | 49 +
.../iLLD/TC26B/Tricore/_Impl/IfxDma_cfg.h | 158 +
.../iLLD/TC26B/Tricore/_Impl/IfxDsadc_cfg.h | 71 +
.../iLLD/TC26B/Tricore/_Impl/IfxDts_cfg.h | 65 +
.../iLLD/TC26B/Tricore/_Impl/IfxEmem_cfg.c | 49 +
.../iLLD/TC26B/Tricore/_Impl/IfxEmem_cfg.h | 80 +
.../iLLD/TC26B/Tricore/_Impl/IfxEray_cfg.c | 57 +
.../iLLD/TC26B/Tricore/_Impl/IfxEray_cfg.h | 110 +
.../iLLD/TC26B/Tricore/_Impl/IfxEth_cfg.h | 67 +
.../iLLD/TC26B/Tricore/_Impl/IfxFce_cfg.h | 67 +
.../iLLD/TC26B/Tricore/_Impl/IfxFft_cfg.h | 89 +
.../iLLD/TC26B/Tricore/_Impl/IfxFlash_cfg.c | 151 +
.../iLLD/TC26B/Tricore/_Impl/IfxFlash_cfg.h | 196 +
.../iLLD/TC26B/Tricore/_Impl/IfxGlobal_cfg.h | 64 +
.../iLLD/TC26B/Tricore/_Impl/IfxGpt12_cfg.h | 65 +
.../iLLD/TC26B/Tricore/_Impl/IfxGtm_cfg.c | 49 +
.../iLLD/TC26B/Tricore/_Impl/IfxGtm_cfg.h | 340 +
.../iLLD/TC26B/Tricore/_Impl/IfxHssl_cfg.c | 61 +
.../iLLD/TC26B/Tricore/_Impl/IfxHssl_cfg.h | 112 +
.../iLLD/TC26B/Tricore/_Impl/IfxI2c_cfg.c | 57 +
.../iLLD/TC26B/Tricore/_Impl/IfxI2c_cfg.h | 97 +
.../iLLD/TC26B/Tricore/_Impl/IfxIom_cfg.h | 245 +
.../iLLD/TC26B/Tricore/_Impl/IfxMsc_cfg.c | 58 +
.../iLLD/TC26B/Tricore/_Impl/IfxMsc_cfg.h | 95 +
.../iLLD/TC26B/Tricore/_Impl/IfxMtu_cfg.c | 145 +
.../iLLD/TC26B/Tricore/_Impl/IfxMtu_cfg.h | 152 +
.../TC26B/Tricore/_Impl/IfxMultican_cfg.c | 57 +
.../TC26B/Tricore/_Impl/IfxMultican_cfg.h | 139 +
.../iLLD/TC26B/Tricore/_Impl/IfxPort_cfg.c | 88 +
.../iLLD/TC26B/Tricore/_Impl/IfxPort_cfg.h | 117 +
.../iLLD/TC26B/Tricore/_Impl/IfxPsi5_cfg.c | 49 +
.../iLLD/TC26B/Tricore/_Impl/IfxPsi5_cfg.h | 99 +
.../iLLD/TC26B/Tricore/_Impl/IfxPsi5s_cfg.h | 95 +
.../iLLD/TC26B/Tricore/_Impl/IfxQspi_cfg.c | 60 +
.../iLLD/TC26B/Tricore/_Impl/IfxQspi_cfg.h | 95 +
.../iLLD/TC26B/Tricore/_Impl/IfxScu_cfg.c | 49 +
.../iLLD/TC26B/Tricore/_Impl/IfxScu_cfg.h | 1419 +
.../iLLD/TC26B/Tricore/_Impl/IfxSent_cfg.c | 50 +
.../iLLD/TC26B/Tricore/_Impl/IfxSent_cfg.h | 97 +
.../iLLD/TC26B/Tricore/_Impl/IfxSmu_cfg.c | 49 +
.../iLLD/TC26B/Tricore/_Impl/IfxSmu_cfg.h | 247 +
.../iLLD/TC26B/Tricore/_Impl/IfxSrc_cfg.c | 49 +
.../iLLD/TC26B/Tricore/_Impl/IfxSrc_cfg.h | 78 +
.../iLLD/TC26B/Tricore/_Impl/IfxStm_cfg.c | 58 +
.../iLLD/TC26B/Tricore/_Impl/IfxStm_cfg.h | 107 +
.../iLLD/TC26B/Tricore/_Impl/IfxVadc_cfg.c | 80 +
.../iLLD/TC26B/Tricore/_Impl/IfxVadc_cfg.h | 137 +
.../DataHandling/Ifx_CircularBuffer.asm.c | 159 +
.../_Lib/DataHandling/Ifx_CircularBuffer.c | 186 +
.../_Lib/DataHandling/Ifx_CircularBuffer.h | 121 +
.../Tricore/_Lib/DataHandling/Ifx_Fifo.c | 419 +
.../Tricore/_Lib/DataHandling/Ifx_Fifo.h | 243 +
.../TC26B/Tricore/_Lib/DataHandling/info.dox | 5 +
.../_Lib/InternalMux/Ifx_InternalMux.c | 67 +
.../_Lib/InternalMux/Ifx_InternalMux.h | 94 +
.../TC26B/Tricore/_Lib/InternalMux/info.dox | 5 +
.../iLLD/TC26B/Tricore/_Lib/info.dox | 5 +
.../TC26B/Tricore/_PinMap/IfxAsclin_PinMap.c | 345 +
.../TC26B/Tricore/_PinMap/IfxAsclin_PinMap.h | 228 +
.../TC26B/Tricore/_PinMap/IfxCcu6_PinMap.c | 374 +
.../TC26B/Tricore/_PinMap/IfxCcu6_PinMap.h | 357 +
.../TC26B/Tricore/_PinMap/IfxCif_PinMap.c | 66 +
.../TC26B/Tricore/_PinMap/IfxCif_PinMap.h | 108 +
.../TC26B/Tricore/_PinMap/IfxDsadc_PinMap.c | 279 +
.../TC26B/Tricore/_PinMap/IfxDsadc_PinMap.h | 219 +
.../TC26B/Tricore/_PinMap/IfxEray_PinMap.c | 125 +
.../TC26B/Tricore/_PinMap/IfxEray_PinMap.h | 129 +
.../TC26B/Tricore/_PinMap/IfxEth_PinMap.c | 135 +
.../TC26B/Tricore/_PinMap/IfxEth_PinMap.h | 234 +
.../TC26B/Tricore/_PinMap/IfxGpt12_PinMap.c | 178 +
.../TC26B/Tricore/_PinMap/IfxGpt12_PinMap.h | 142 +
.../TC26B/Tricore/_PinMap/IfxGtm_PinMap.c | 743 +
.../TC26B/Tricore/_PinMap/IfxGtm_PinMap.h | 805 +
.../TC26B/Tricore/_PinMap/IfxI2c_PinMap.c | 70 +
.../TC26B/Tricore/_PinMap/IfxI2c_PinMap.h | 97 +
.../TC26B/Tricore/_PinMap/IfxMsc_PinMap.c | 245 +
.../TC26B/Tricore/_PinMap/IfxMsc_PinMap.h | 205 +
.../Tricore/_PinMap/IfxMultican_PinMap.c | 146 +
.../Tricore/_PinMap/IfxMultican_PinMap.h | 124 +
.../TC26B/Tricore/_PinMap/IfxPort_PinMap.c | 866 +
.../TC26B/Tricore/_PinMap/IfxPort_PinMap.h | 186 +
.../TC26B/Tricore/_PinMap/IfxPsi5_PinMap.c | 106 +
.../TC26B/Tricore/_PinMap/IfxPsi5_PinMap.h | 110 +
.../TC26B/Tricore/_PinMap/IfxPsi5s_PinMap.c | 79 +
.../TC26B/Tricore/_PinMap/IfxPsi5s_PinMap.h | 109 +
.../TC26B/Tricore/_PinMap/IfxQspi_PinMap.c | 658 +
.../TC26B/Tricore/_PinMap/IfxQspi_PinMap.h | 310 +
.../TC26B/Tricore/_PinMap/IfxScu_PinMap.c | 186 +
.../TC26B/Tricore/_PinMap/IfxScu_PinMap.h | 186 +
.../TC26B/Tricore/_PinMap/IfxSent_PinMap.c | 146 +
.../TC26B/Tricore/_PinMap/IfxSent_PinMap.h | 126 +
.../TC26B/Tricore/_PinMap/IfxSmu_PinMap.c | 55 +
.../TC26B/Tricore/_PinMap/IfxSmu_PinMap.h | 77 +
.../TC26B/Tricore/_PinMap/IfxVadc_PinMap.c | 267 +
.../TC26B/Tricore/_PinMap/IfxVadc_PinMap.h | 192 +
.../libraries/zf_common/zf_common_clock.c | 111 +
.../libraries/zf_common/zf_common_clock.h | 48 +
.../libraries/zf_common/zf_common_debug.c | 432 +
.../libraries/zf_common/zf_common_debug.h | 111 +
.../libraries/zf_common/zf_common_fifo.c | 537 +
.../libraries/zf_common/zf_common_fifo.h | 95 +
.../libraries/zf_common/zf_common_font.c | 2721 ++
.../libraries/zf_common/zf_common_font.h | 68 +
.../libraries/zf_common/zf_common_function.c | 905 +
.../libraries/zf_common/zf_common_function.h | 97 +
.../libraries/zf_common/zf_common_headfile.h | 108 +
.../libraries/zf_common/zf_common_interrupt.c | 85 +
.../libraries/zf_common/zf_common_interrupt.h | 46 +
.../libraries/zf_common/zf_common_typedef.h | 77 +
.../zf_device/zf_device_absolute_encoder.c | 229 +
.../zf_device/zf_device_absolute_encoder.h | 93 +
.../zf_device/zf_device_bluetooth_ch9141.c | 254 +
.../zf_device/zf_device_bluetooth_ch9141.h | 77 +
.../libraries/zf_device/zf_device_camera.c | 169 +
.../libraries/zf_device/zf_device_camera.h | 55 +
.../libraries/zf_device/zf_device_config.a | Bin 0 -> 38970 bytes
.../libraries/zf_device/zf_device_config.h | 49 +
.../libraries/zf_device/zf_device_dl1a.c | 752 +
.../libraries/zf_device/zf_device_dl1a.h | 199 +
.../zf_device/zf_device_gps_tau1201.c | 542 +
.../zf_device/zf_device_gps_tau1201.h | 116 +
.../libraries/zf_device/zf_device_icm20602.c | 324 +
.../libraries/zf_device/zf_device_icm20602.h | 182 +
.../libraries/zf_device/zf_device_imu660ra.c | 311 +
.../libraries/zf_device/zf_device_imu660ra.h | 132 +
.../libraries/zf_device/zf_device_imu963ra.c | 498 +
.../libraries/zf_device/zf_device_imu963ra.h | 156 +
.../libraries/zf_device/zf_device_ips114.c | 1001 +
.../libraries/zf_device/zf_device_ips114.h | 166 +
.../libraries/zf_device/zf_device_ips200.c | 1152 +
.../libraries/zf_device/zf_device_ips200.h | 227 +
.../libraries/zf_device/zf_device_key.c | 144 +
.../libraries/zf_device/zf_device_key.h | 84 +
.../libraries/zf_device/zf_device_mpu6050.c | 225 +
.../libraries/zf_device/zf_device_mpu6050.h | 112 +
.../libraries/zf_device/zf_device_mt9v03x.c | 502 +
.../libraries/zf_device/zf_device_mt9v03x.h | 144 +
.../libraries/zf_device/zf_device_oled.c | 749 +
.../libraries/zf_device/zf_device_oled.h | 161 +
.../libraries/zf_device/zf_device_ov7725.c | 544 +
.../libraries/zf_device/zf_device_ov7725.h | 272 +
.../libraries/zf_device/zf_device_scc8660.c | 576 +
.../libraries/zf_device/zf_device_scc8660.h | 133 +
.../libraries/zf_device/zf_device_tft180.c | 984 +
.../libraries/zf_device/zf_device_tft180.h | 165 +
.../libraries/zf_device/zf_device_tsl1401.c | 134 +
.../libraries/zf_device/zf_device_tsl1401.h | 82 +
.../libraries/zf_device/zf_device_type.c | 90 +
.../libraries/zf_device/zf_device_type.h | 77 +
.../zf_device_virtual_oscilloscope.c | 103 +
.../zf_device_virtual_oscilloscope.h | 47 +
.../libraries/zf_device/zf_device_wifi_uart.c | 1210 +
.../libraries/zf_device/zf_device_wifi_uart.h | 153 +
.../zf_device/zf_device_wireless_uart.c | 303 +
.../zf_device/zf_device_wireless_uart.h | 93 +
.../libraries/zf_driver/zf_driver_adc.c | 153 +
.../libraries/zf_driver/zf_driver_adc.h | 95 +
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.../libraries/zf_driver/zf_driver_dma.c | 198 +
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.../libraries/zf_driver/zf_driver_exti.c | 212 +
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.../libraries/zf_driver/zf_driver_gpio.c | 195 +
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.../libraries/zf_driver/zf_driver_soft_iic.c | 674 +
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.../libraries/zf_driver/zf_driver_soft_spi.c | 571 +
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.../libraries/zf_driver/zf_driver_timer.c | 74 +
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Example/E15_fft_demo/user/cpu0_main.c | 95 +
Example/E15_fft_demo/user/cpu0_main.h | 85 +
Example/E15_fft_demo/user/cpu1_main.c | 72 +
Example/E15_fft_demo/user/isr.c | 274 +
Example/E15_fft_demo/user/isr.h | 52 +
Example/E15_fft_demo/user/isr_config.h | 115 +
Example/E15_fft_demo/删除临时文件.bat | 6 +
Example/E15_fft_demo/尽量不要使用的引脚.txt | 14 +
Example/E15_fft_demo/推荐IO分配.txt | 47 +
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create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxCcu6_PinMap.h
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxCif_PinMap.c
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxCif_PinMap.h
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxDsadc_PinMap.c
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxDsadc_PinMap.h
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxEray_PinMap.c
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxEray_PinMap.h
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxEth_PinMap.c
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxEth_PinMap.h
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxGpt12_PinMap.c
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxGpt12_PinMap.h
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxGtm_PinMap.c
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxGtm_PinMap.h
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxI2c_PinMap.c
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxI2c_PinMap.h
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxMsc_PinMap.c
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxMsc_PinMap.h
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxMultican_PinMap.c
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxMultican_PinMap.h
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxPort_PinMap.c
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxPort_PinMap.h
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxPsi5_PinMap.c
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxPsi5_PinMap.h
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxPsi5s_PinMap.c
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxPsi5s_PinMap.h
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxQspi_PinMap.c
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxQspi_PinMap.h
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxScu_PinMap.c
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxScu_PinMap.h
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxSent_PinMap.c
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxSent_PinMap.h
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxSmu_PinMap.c
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxSmu_PinMap.h
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxVadc_PinMap.c
create mode 100644 Example/E15_fft_demo/libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/IfxVadc_PinMap.h
create mode 100644 Example/E15_fft_demo/libraries/zf_common/zf_common_clock.c
create mode 100644 Example/E15_fft_demo/libraries/zf_common/zf_common_clock.h
create mode 100644 Example/E15_fft_demo/libraries/zf_common/zf_common_debug.c
create mode 100644 Example/E15_fft_demo/libraries/zf_common/zf_common_debug.h
create mode 100644 Example/E15_fft_demo/libraries/zf_common/zf_common_fifo.c
create mode 100644 Example/E15_fft_demo/libraries/zf_common/zf_common_fifo.h
create mode 100644 Example/E15_fft_demo/libraries/zf_common/zf_common_font.c
create mode 100644 Example/E15_fft_demo/libraries/zf_common/zf_common_font.h
create mode 100644 Example/E15_fft_demo/libraries/zf_common/zf_common_function.c
create mode 100644 Example/E15_fft_demo/libraries/zf_common/zf_common_function.h
create mode 100644 Example/E15_fft_demo/libraries/zf_common/zf_common_headfile.h
create mode 100644 Example/E15_fft_demo/libraries/zf_common/zf_common_interrupt.c
create mode 100644 Example/E15_fft_demo/libraries/zf_common/zf_common_interrupt.h
create mode 100644 Example/E15_fft_demo/libraries/zf_common/zf_common_typedef.h
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_absolute_encoder.c
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_absolute_encoder.h
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_bluetooth_ch9141.c
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_bluetooth_ch9141.h
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_camera.c
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_camera.h
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_config.a
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_config.h
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_dl1a.c
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_dl1a.h
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_gps_tau1201.c
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_gps_tau1201.h
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_icm20602.c
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_icm20602.h
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_imu660ra.c
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_imu660ra.h
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_imu963ra.c
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_imu963ra.h
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_ips114.c
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_ips114.h
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_ips200.c
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_ips200.h
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_key.c
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_key.h
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_mpu6050.c
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_mpu6050.h
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_mt9v03x.c
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_mt9v03x.h
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_oled.c
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_oled.h
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_ov7725.c
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_ov7725.h
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_scc8660.c
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_scc8660.h
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_tft180.c
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_tft180.h
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_tsl1401.c
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_tsl1401.h
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_type.c
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_type.h
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_virtual_oscilloscope.c
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_virtual_oscilloscope.h
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_wifi_uart.c
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_wifi_uart.h
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_wireless_uart.c
create mode 100644 Example/E15_fft_demo/libraries/zf_device/zf_device_wireless_uart.h
create mode 100644 Example/E15_fft_demo/libraries/zf_driver/zf_driver_adc.c
create mode 100644 Example/E15_fft_demo/libraries/zf_driver/zf_driver_adc.h
create mode 100644 Example/E15_fft_demo/libraries/zf_driver/zf_driver_delay.c
create mode 100644 Example/E15_fft_demo/libraries/zf_driver/zf_driver_delay.h
create mode 100644 Example/E15_fft_demo/libraries/zf_driver/zf_driver_dma.c
create mode 100644 Example/E15_fft_demo/libraries/zf_driver/zf_driver_dma.h
create mode 100644 Example/E15_fft_demo/libraries/zf_driver/zf_driver_encoder.c
create mode 100644 Example/E15_fft_demo/libraries/zf_driver/zf_driver_encoder.h
create mode 100644 Example/E15_fft_demo/libraries/zf_driver/zf_driver_exti.c
create mode 100644 Example/E15_fft_demo/libraries/zf_driver/zf_driver_exti.h
create mode 100644 Example/E15_fft_demo/libraries/zf_driver/zf_driver_flash.c
create mode 100644 Example/E15_fft_demo/libraries/zf_driver/zf_driver_flash.h
create mode 100644 Example/E15_fft_demo/libraries/zf_driver/zf_driver_gpio.c
create mode 100644 Example/E15_fft_demo/libraries/zf_driver/zf_driver_gpio.h
create mode 100644 Example/E15_fft_demo/libraries/zf_driver/zf_driver_pit.c
create mode 100644 Example/E15_fft_demo/libraries/zf_driver/zf_driver_pit.h
create mode 100644 Example/E15_fft_demo/libraries/zf_driver/zf_driver_pwm.c
create mode 100644 Example/E15_fft_demo/libraries/zf_driver/zf_driver_pwm.h
create mode 100644 Example/E15_fft_demo/libraries/zf_driver/zf_driver_soft_iic.c
create mode 100644 Example/E15_fft_demo/libraries/zf_driver/zf_driver_soft_iic.h
create mode 100644 Example/E15_fft_demo/libraries/zf_driver/zf_driver_soft_spi.c
create mode 100644 Example/E15_fft_demo/libraries/zf_driver/zf_driver_soft_spi.h
create mode 100644 Example/E15_fft_demo/libraries/zf_driver/zf_driver_spi.c
create mode 100644 Example/E15_fft_demo/libraries/zf_driver/zf_driver_spi.h
create mode 100644 Example/E15_fft_demo/libraries/zf_driver/zf_driver_timer.c
create mode 100644 Example/E15_fft_demo/libraries/zf_driver/zf_driver_timer.h
create mode 100644 Example/E15_fft_demo/libraries/zf_driver/zf_driver_uart.c
create mode 100644 Example/E15_fft_demo/libraries/zf_driver/zf_driver_uart.h
create mode 100644 Example/E15_fft_demo/user/cpu0_main.c
create mode 100644 Example/E15_fft_demo/user/cpu0_main.h
create mode 100644 Example/E15_fft_demo/user/cpu1_main.c
create mode 100644 Example/E15_fft_demo/user/isr.c
create mode 100644 Example/E15_fft_demo/user/isr.h
create mode 100644 Example/E15_fft_demo/user/isr_config.h
create mode 100644 Example/E15_fft_demo/删除临时文件.bat
create mode 100644 Example/E15_fft_demo/尽量不要使用的引脚.txt
create mode 100644 Example/E15_fft_demo/推荐IO分配.txt
diff --git a/Example/E15_fft_demo/.cproject b/Example/E15_fft_demo/.cproject
new file mode 100644
index 0000000..526374b
--- /dev/null
+++ b/Example/E15_fft_demo/.cproject
@@ -0,0 +1,1198 @@
+
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diff --git a/Example/E15_fft_demo/.project b/Example/E15_fft_demo/.project
new file mode 100644
index 0000000..143f2d4
--- /dev/null
+++ b/Example/E15_fft_demo/.project
@@ -0,0 +1,40 @@
+
+
+ E15_fft_demo
+
+
+
+
+
+ com.infineon.aurix.buildsystem.builders.booster
+ full,incremental,
+
+
+
+
+ com.infineon.aurix.buildsystem.builders.autodiscovery
+ full,incremental,
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.genmakebuilder
+ clean,full,incremental,
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+ full,incremental,
+
+
+
+
+
+ org.eclipse.cdt.core.cnature
+ org.eclipse.cdt.managedbuilder.core.managedBuildNature
+ org.eclipse.cdt.core.ccnature
+ com.infineon.aurix.buildsystem.aurixnature
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+
+
diff --git a/Example/E15_fft_demo/.settings/com.infineon.aurix.buildsystem.prefs b/Example/E15_fft_demo/.settings/com.infineon.aurix.buildsystem.prefs
new file mode 100644
index 0000000..be61bc1
--- /dev/null
+++ b/Example/E15_fft_demo/.settings/com.infineon.aurix.buildsystem.prefs
@@ -0,0 +1,10 @@
+AURIX-LIBRARY-PATH=Libraries/iLLD\#Libraries/Infra\#Libraries/Service
+DEVICE-ID=TC26B
+DEVICE-ID-FULL=TC26xD_B-Step
+ILLD-SET=full
+IncludesAutodiscovery=true
+LIBRARIES-ROOT-PATH=Libraries
+NEVER-EXCLUDE-FROM-BUILD=/Libraries/iLLD/TC26B/Tricore/Cpu/CStart\#/Libraries/iLLD/TC26B/Tricore/Cpu/Trap\#/Configurations\#/Configurations/Debug
+PROJECT-VERSION=1.0
+aurixDevice=TC26xD_B-Step
+eclipse.preferences.version=1
diff --git a/Example/E15_fft_demo/.settings/org.eclipse.core.resources.prefs b/Example/E15_fft_demo/.settings/org.eclipse.core.resources.prefs
new file mode 100644
index 0000000..b3c7fde
--- /dev/null
+++ b/Example/E15_fft_demo/.settings/org.eclipse.core.resources.prefs
@@ -0,0 +1 @@
+eclipse.preferences.version=1
diff --git a/Example/E15_fft_demo/Lcf_Tasking_Tricore_Tc.lsl b/Example/E15_fft_demo/Lcf_Tasking_Tricore_Tc.lsl
new file mode 100644
index 0000000..e568c95
--- /dev/null
+++ b/Example/E15_fft_demo/Lcf_Tasking_Tricore_Tc.lsl
@@ -0,0 +1,449 @@
+/**********************************************************************************************************************
+ * \file Lcf_Tasking_Tricore_Tc.lsl
+ * \brief Linker command file for Tasking compiler.
+ * \copyright Copyright (C) Infineon Technologies AG 2019
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of
+ * business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
+ * are agreed, use of this file is subject to following:
+ *
+ * Boost Software License - Version 1.0 - August 17th, 2003
+ *
+ * Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and
+ * accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
+ * and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+ *
+ * The copyright notices in the Software and this entire statement, including the above license grant, this restriction
+ * and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are solely in the form of
+ * machine-executable object code generated by a source language processor.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *********************************************************************************************************************/
+
+#define LCF_CSA0_SIZE 8k
+#define LCF_USTACK0_SIZE 2k
+#define LCF_ISTACK0_SIZE 1k
+
+#define LCF_CSA1_SIZE 8k
+#define LCF_USTACK1_SIZE 2k
+#define LCF_ISTACK1_SIZE 1k
+
+#define LCF_HEAP_SIZE 2k
+
+#define LCF_CPU0 0
+#define LCF_CPU1 1
+
+/*Un comment one of the below statements to enable CpuX DMI RAM to hold global variables*/
+/*#define LCF_DEFAULT_HOST LCF_CPU0*/
+#define LCF_DEFAULT_HOST LCF_CPU1
+
+#define LCF_DSPR1_START 0x60000000
+#define LCF_DSPR1_SIZE 120k
+
+#define LCF_DSPR0_START 0x70000000
+#define LCF_DSPR0_SIZE 72k
+
+#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
+#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
+#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
+
+#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
+#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
+#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
+
+#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
+#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
+
+#define LCF_INTVEC0_START 0x800F4000
+#define LCF_TRAPVEC0_START 0x80000100
+#define LCF_TRAPVEC1_START 0x800F6000
+
+#define INTTAB0 (LCF_INTVEC0_START)
+#define TRAPTAB0 (LCF_TRAPVEC0_START)
+#define TRAPTAB1 (LCF_TRAPVEC1_START)
+
+#define RESET 0x80000020
+
+#include "tc1v1_6_x.lsl"
+
+// Specify a multi-core processor environment (mpe)
+
+processor mpe
+{
+ derivative = tc26B;
+}
+
+derivative tc26B
+{
+ core tc0
+ {
+ architecture = TC1V1.6.X;
+ space_id_offset = 100; // add 100 to all space IDs in the architecture definition
+ copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
+ }
+
+ core tc1 // core 1 TC16E
+ {
+ architecture = TC1V1.6.X;
+ space_id_offset = 200; // add 200 to all space IDs in the architecture definition
+ copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
+ }
+
+ core vtc
+ {
+ architecture = TC1V1.6.X;
+ import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
+ import tc1; // tc1
+ }
+
+ bus sri
+ {
+ mau = 8;
+ width = 32;
+
+ // map shared addresses one-to-one to real cores and virtual cores
+ map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
+ map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
+ map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
+ }
+
+ memory dsram1 // Data Scratch Pad Ram
+ {
+ mau = 8;
+ size = 120k;
+ type = ram;
+ map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
+ map (dest=bus:sri, dest_offset=0x60000000, size=120k);
+ }
+
+ memory psram1 // Program Scratch Pad Ram
+ {
+ mau = 8;
+ size = 32k;
+ type = ram;
+ map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
+ map (dest=bus:sri, dest_offset=0x60100000, size=32k);
+ }
+
+ memory dsram0 // Data Scratch Pad Ram
+ {
+ mau = 8;
+ size = 72k;
+ type = ram;
+ map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
+ map (dest=bus:sri, dest_offset=0x70000000, size=72k);
+ }
+
+ memory psram0 // Program Scratch Pad Ram
+ {
+ mau = 8;
+ size = 16k;
+ type = ram;
+ map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
+ map (dest=bus:sri, dest_offset=0x70100000, size=16k);
+ }
+
+ memory pfls0
+ {
+ mau = 8;
+ size = 1M;
+ type = rom;
+ map cached (dest=bus:sri, dest_offset=0x80000000, size=1M);
+ map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1M);
+ }
+
+ memory pfls1
+ {
+ mau = 8;
+ size = 1536K;
+ type = rom;
+ map cached (dest=bus:sri, dest_offset=0x80100000, size=1536K);
+ map not_cached (dest=bus:sri, dest_offset=0xa0100000, reserved, size=1536K);
+ }
+
+ memory dfls0
+ {
+ mau = 8;
+ size = 1m+16k;
+ type = reserved nvram;
+ map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
+ }
+
+ memory edmem
+ {
+ mau = 8;
+ size = 512K;
+ type = ram;
+ map (dest=bus:sri, dest_offset=0x9f000000, size=512K);
+ map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=512K);
+ }
+
+#if (__VERSION__ >= 6003)
+ section_setup :vtc:linear
+ {
+ heap "heap" (min_size = (1k), fixed, align = 8);
+ }
+#endif
+
+ section_setup :vtc:linear
+ {
+ start_address
+ (
+ symbol = "_START"
+ );
+ }
+
+ section_setup :vtc:linear
+ {
+ stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
+ stack "istack_tc0" (min_size = 1k, fixed, align = 8);
+ stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
+ stack "istack_tc1" (min_size = 1k, fixed, align = 8);
+ }
+
+ /*Section setup for the copy table*/
+ section_setup :vtc:linear
+ {
+ copytable
+ (
+ align = 4,
+ dest = linear,
+ table
+ {
+ symbol = "_lc_ub_table_tc0";
+ space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
+ },
+ table
+ {
+ symbol = "_lc_ub_table_tc1";
+ space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
+ }
+ );
+ }
+
+ /*Near data sections*/
+ section_layout :vtc:abs18
+ {
+ group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
+ {
+ select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
+ select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
+ }
+
+ group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
+ {
+ select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
+ select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
+ }
+# if LCF_DEFAULT_HOST == LCF_CPU1
+ group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
+# endif
+# if LCF_DEFAULT_HOST == LCF_CPU0
+ group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
+# endif
+ {
+ select "(.zdata|.zdata*)";
+ select "(.zbss|.zbss*)";
+ }
+ }
+
+ section_layout :vtc:linear
+ {
+/*Small data sections, No option given for CPU specific user sections to make generated code portable across Cpus*/
+# if LCF_DEFAULT_HOST == LCF_CPU1
+ group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
+# endif
+# if LCF_DEFAULT_HOST == LCF_CPU0
+ group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
+# endif
+ {
+ select "(.sdata |.sdata*)";
+ select "(.sbss |.sbss*)";
+ }
+ "_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
+
+ group (ordered, contiguous, align = 4, run_addr = mem:edmem)
+ {
+ select "(.data.edmemdata|.data.edmemdata*)";
+ select "(.bss.edmembss|.bss.edmembss*)";
+ }
+
+ group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
+ {
+ select "(.data.data_cpu1|.data.data_cpu1*)";
+ select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
+
+ select ".bss.cpu1_dsram|.bss.cpu1_dsram.*";
+ select ".data.cpu1_dsram|.data.cpu1_dsram.*";
+ select ".zdata.cpu1_dsram|.zdata.cpu1_dsram.*";
+ }
+
+ group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
+ {
+ select "(.data.data_cpu0|.data.data_cpu0*)";
+ select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
+
+ select ".bss.cpu0_dsram|.bss.cpu0_dsram.*";
+ select ".data.cpu0_dsram|.data.cpu0_dsram.*";
+ select ".zdata.cpu0_dsram|.zdata.cpu0_dsram.*";
+ }
+
+# if LCF_DEFAULT_HOST == LCF_CPU1
+ group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
+# endif
+# if LCF_DEFAULT_HOST == LCF_CPU0
+ group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
+# endif
+ {
+ select "(.data|.data*)";
+ select "(.bss|.bss*)";
+ }
+
+/*Heap sections*/
+# if LCF_DEFAULT_HOST == LCF_CPU1
+ group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
+# endif
+# if LCF_DEFAULT_HOST == LCF_CPU0
+ group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
+# endif
+ {
+ heap "heap" (size = LCF_HEAP_SIZE);
+ }
+
+ group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
+ {
+ stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
+ }
+ "__USTACK1":= "_lc_ue_ustack_tc1";
+ "__USTACK1_END":= "_lc_ub_ustack_tc1";
+
+ group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
+ {
+ stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
+ }
+ "__ISTACK1":= "_lc_ue_istack_tc1";
+ "__ISTACK1_END":= "_lc_ub_istack_tc1";
+
+ group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
+ reserved "csa_tc1" (size = LCF_CSA1_SIZE);
+ "__CSA1":= "_lc_ub_csa_tc1";
+ "__CSA1_END":= "_lc_ue_csa_tc1";
+
+ group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
+ {
+ stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
+ }
+ "__USTACK0":= "_lc_ue_ustack_tc0";
+ "__USTACK0_END":= "_lc_ub_ustack_tc0";
+
+ group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
+ {
+ stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
+ }
+ "__ISTACK0":= "_lc_ue_istack_tc0";
+ "__ISTACK0_END":= "_lc_ub_istack_tc0";
+
+ group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
+ reserved "csa_tc0" (size = LCF_CSA0_SIZE);
+ "__CSA0":= "_lc_ub_csa_tc0";
+ "__CSA0_END":= "_lc_ue_csa_tc0";
+ }
+
+
+ section_layout :vtc:linear
+ {
+ "_lc_u_int_tab" = (LCF_INTVEC0_START);
+ "__INTTAB_CPU0" = (LCF_INTVEC0_START);
+ "__INTTAB_CPU1" = (LCF_INTVEC0_START);
+
+ // interrupt vector tables for tc0, tc1, tc2
+ group int_tab_tc0 (ordered)
+ {
+# include "inttab0.lsl"
+ }
+
+ group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
+ {
+ select "(.text.traptab_cpu0*)";
+ }
+
+ group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
+ {
+ select "(.text.traptab_cpu1*)";
+ }
+
+ group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
+ {
+ select "(.text.psram_cpu0*)";
+ select "(.text.cpu0_psram*)";
+ }
+
+ group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
+ {
+ select "(.text.psram_cpu1*)";
+ select "(.text.cpu1_psram*)";
+ }
+ }
+
+ section_layout :vtc:abs18
+ {
+ group (ordered, run_addr=mem:pfls0)
+ {
+ select ".zrodata*";
+ }
+ }
+
+ section_layout :vtc:linear
+ {
+ group bmh_0 (ordered, run_addr=0x80000000)
+ {
+ select "*.bmhd_0";
+ }
+ group bmh_1 (ordered, run_addr=0x80020000)
+ {
+ select "*.bmhd_1";
+ }
+ group reset (ordered, run_addr=0x80000020)
+ {
+ select "*.start";
+ }
+ group interface_const (ordered, run_addr=0x80000040)
+ {
+ select "*.interface_const";
+ }
+ "__IF_CONST" := addressof(group:ainterface_const);
+ group a1 (ordered, run_addr=mem:pfls0)
+ {
+ select ".srodata*";
+ select ".ldata*";
+ }
+ "_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
+ "_A1_MEM" = "_LITERAL_DATA_";
+ "_A9_DATA_" := 0x00000000;
+ "_A9_MEM" = "_A9_DATA_";
+
+ group (ordered, run_addr=mem:pfls0)
+ {
+ select ".rodata*";
+ }
+ group (ordered, run_addr=mem:pfls0)
+ {
+ select ".text*";
+ }
+ group a8 (ordered, run_addr=mem:pfls0)
+ {
+ select "(.rodata_a8|.rodata_a8*)";
+ }
+ "_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
+ "_A8_MEM" := "_A8_DATA_";
+
+ "__TRAPTAB_CPU0" := TRAPTAB0;
+ "__TRAPTAB_CPU1" := TRAPTAB1;
+ }
+}
diff --git a/Example/E15_fft_demo/code/本文件夹作用.txt b/Example/E15_fft_demo/code/本文件夹作用.txt
new file mode 100644
index 0000000..9e40fbe
--- /dev/null
+++ b/Example/E15_fft_demo/code/本文件夹作用.txt
@@ -0,0 +1,3 @@
+ûҪԼĴļʱļCODEļ
+ҪٴļУֱӽļCODEļ
+Ȼļɱ
\ No newline at end of file
diff --git a/Example/E15_fft_demo/libraries/doc/GPL3_permission_statement.txt b/Example/E15_fft_demo/libraries/doc/GPL3_permission_statement.txt
new file mode 100644
index 0000000..b63dd8d
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/doc/GPL3_permission_statement.txt
@@ -0,0 +1,13 @@
+TC264 Opensourec Library : An open source library of third party interfaces based on the official SDK
+Copyright (C) 2022 SEEKFREE ɿƼ
+
+TC264 Opensourec Library is free software:
+you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation,
+either version 3 of the License, or (at your option) any later version.
+
+TC264 Opensourec Library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+See the GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along with TC264 Opensourec Library.
+If not, see .
\ No newline at end of file
diff --git a/Example/E15_fft_demo/libraries/doc/version.txt b/Example/E15_fft_demo/libraries/doc/version.txt
new file mode 100644
index 0000000..fc8ff9a
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/doc/version.txt
@@ -0,0 +1,181 @@
+V3.1.5
+ İ˿ ͨ
+ GPSģ˿ ڸΪUSRT3 Ļصλ
+ CCDɼλcc61_ch1
+V3.1.4
+ DL1Aģļ
+V3.1.3
+ עԼʹʾ
+V3.1.2
+ flash_checkֻһݵbug
+V3.1.1
+ ͷʼRAMռù
+V3.1.0
+ GPSȲ
+ ļעʹ
+ ûӿڵĶԻ ǿ V3 Ľ׳ ҪԿָ
+V3.0.1
+ 絥عȹ
+V3.0.0
+ Դʵ
+ ǿ˴Ŀֲ
+ ˲ֹ㹦
+V1.3.0
+ icm20602ijʼϵ˵
+V1.2.10
+ IMU963RAģļ
+V1.2.9
+ ɾSEEKFREE_IPS200_PARALLEL8ļSEEKFREE_IPS200ļԭе2Ҳµ2
+ spiײ˳ʱжcs״̬ȷspiɺ˳
+ tftips114з͵my_delayȥ
+V1.2.8
+ ײPCLK_MODEȡλ
+
+V1.2.7
+ ֮ǰ͵ײ⣬ᵼ׳ֲɼλ
+ żӴͼλԴӼԽ
+
+V1.2.6
+ ײ㣬ʹ÷ʽ
+ ײ㣬ӶV2.1汾PCLK
+ ˫ƵGPSλģĵײ
+
+V1.2.5
+ ŻӲSPISPIĻSPIĻˢٶȣIPS1.14Ļʾ188*120ɴ31֡ʾ160*120ɴ37֡TFT1.8Ļʾ160*120ɴ37֡
+
+V1.2.4
+ systick_delay_msʱʱϳʱʱʱ䲻ȷ
+
+V1.2.3
+ ͷʼнPCLKΪش
+ systickʱusʱ
+
+V1.2.2
+ ͷͼżԴλ³ʼDMAʹ´βɼͼԶָ
+ ͷʱΪش
+ ͷȥ־λżɼһͼ֡ʼ
+
+V1.2.1
+ printfرյʱ뱨
+
+V1.2.0
+ CH9141תģ
+ ͵öٱ
+ ɾʱļ.bat ִԶرմ
+ ɾʱļ.bat ɾ°汾ļ
+ ĹĿļ֧°汾
+
+V1.1.10
+ ͨ#pragma section all "cpux_dsram"ָλʧЧ
+
+V1.1.9
+ ڵķbuffӵ128ֽ
+
+V1.1.8
+ isr_config.h INT_SERVICEøΪʹöֵ
+ illdļΪinfineon_libraries
+ TC264ļУƵѡ
+ mainȴȴкijʼϲſʼ
+ CLK_FREQ궨ΪCMU_CLK_FREQ
+ DMAַָͨдݣԱڲͷʱص鲻ռRAM
+ pclkΪ½ش
+ תڵRTSòΪ
+
+V1.1.7
+ Ӵڰ汾С
+ ͷͱͨöж
+
+V1.1.6
+ printfΪͨ
+ лΪADSḶ́ADSֱӵ뼴ɱ
+
+V1.1.5
+ DMA_LINKṹlinked_listԱȡΪɶʱָ
+ dma_link_listṹ嶨Ӷ
+
+V1.1.4
+ ļһעͱĬõµһעͱԶ۵
+
+V1.1.3
+ SPI spi_mosiڽΪյʱ쳣
+
+V1.1.2
+ ATOM_PWMռձ쳣
+
+V1.1.1
+ uart_getcharյס
+
+V1.1.0
+ ISRļڵжϺȫenableInterrupts(); ʵжǶĹ
+ RDA5807ȡRSSIܺ
+ DMAӴõıERU_DMA_INT_SERVICEŵӦCPU
+
+V1.0.9
+ RDA5807ļҪ֤ϵ1SڲFMģ
+
+V1.0.8
+ CCU61 ͨ1жô
+ CCU6ߵԵʱʱԶֹͣߵʱжϵ
+ CCU6pit_closepit_startڿƶʱĿʼֹͣ
+ CCU6pit_disable_interruptpit_enable_interruptڿжϿ
+
+V1.0.7
+ ʹsystick_getvalʱʱʱ䳬4һʱ⡣
+ Բִ#pragma warningŻȼʱ־
+ 1.8TFTĻʼйĻѡֵĴ
+
+V1.0.6
+ ADCƵõĺ궨壬ADC_SAMPLE_FREQUENCYΪ10MhzĬµٶнϴ
+
+V1.0.5
+ ȡHEX
+
+V1.0.4
+ ĬϹѡHEXĹ
+ Cpu1_Main.cеcore1_mainĬ жϵĺ
+ CPU1Ӧжϵ
+ ɾеİ·Ϣ
+ Сֱֻɼһε
+ RDA5807 FMģ
+ LSLļͨ#pragma ָָ߳RAMʹοSpecifies_Variable_Or_Code_Location_Demo
+ //ʹ#pragma section all "cpu0_dsram" #pragma section all restoreԽcpu0_dsram
+ //ֻҪ仰м伴ɣʹʾ
+ #pragma section all "cpu0_dsram"
+ uint8 test_arry[5]; //cpu0_dsram
+ //cpu0_dsramΪcpu1_dsram cpu1_dsram
+ //ǽĸCPUִУʹõıĸڣĬϲָ±cpu1_dsram
+ #pragma section all restore
+
+ //ʹ#pragma section all "cpu0_psram" #pragma section all restoreԽصcpu0_psram
+ //ֻҪ仰м伴ɣʹʾ
+ #pragma section all "cpu0_psram"
+ void delay_tset(void) //صcpu0_psramִ
+ {
+ int i;
+ i = 999;
+ while(i--);
+ }
+ //cpu0_psramΪcpu1_psram صcpu1_psram
+ //ǽĸCPUִУصĸڣĬϲָ£Ǵflashزִ
+ //ͨǶҪRAMУһִеijСcacheֳִٶȽͣʱǾͿԽִRAMִУٶ
+ #pragma section all restore
+
+V1.0.3
+ spiuartpitвֱvolatileΣ
+
+V1.0.2
+ ģIICĬʱʱΪ20
+ ҪرעP20_2DzģֻĹ ע
+ ͷɼDMAΪlink䣬ԴDMAжϴ
+ ĬϵIICŶ
+ 6050 ҪõIICģ飬ڳʼĬϵģIICʼ
+ С
+
+V1.0.1
+ ͷijжϽģжϱ־λΪ0Ųɼһͼַʳͻ
+ SPIʼеĴ˹̶SPI2ַ
+ STMʹSTM1
+ gtm pwmռձֻGTM_ATOM0_PWM_DUTY_MAXЧ
+
+V1.0.0
+ ʼ汾
\ No newline at end of file
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Configurations/Ifx_Cfg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Configurations/Ifx_Cfg.h
new file mode 100644
index 0000000..28ff689
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Configurations/Ifx_Cfg.h
@@ -0,0 +1,53 @@
+/**********************************************************************************************************************
+ * \file Ifx_Cfg.h
+ * \brief Project configuration file.
+ * \copyright Copyright (C) Infineon Technologies AG 2019
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of
+ * business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
+ * are agreed, use of this file is subject to following:
+ *
+ * Boost Software License - Version 1.0 - August 17th, 2003
+ *
+ * Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and
+ * accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
+ * and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+ *
+ * The copyright notices in the Software and this entire statement, including the above license grant, this restriction
+ * and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are solely in the form of
+ * machine-executable object code generated by a source language processor.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *********************************************************************************************************************/
+
+#ifndef IFX_CFG_H
+#define IFX_CFG_H 1
+
+
+/*********************************************************************************************************************/
+/*------------------------------------------Configuration for IfxScu_cfg.h-------------------------------------------*/
+/*********************************************************************************************************************/
+/* External oscillator frequency in Hz */
+#define IFX_CFG_SCU_XTAL_FREQUENCY (20000000) /* Allowed values are: 16000000, 20000000 or 40000000 */
+/* PLL frequency in Hz */
+#define IFX_CFG_SCU_PLL_FREQUENCY (200000000) /* Allowed values are: 80000000, 133000000, 160000000
+ * or 200000000 */
+
+/*********************************************************************************************************************/
+/*-----------------------------------Configuration for Software managed interrupt------------------------------------*/
+/*********************************************************************************************************************/
+/* #define IFX_USE_SW_MANAGED_INT */ /* Decomment this line if the project needs to use Software managed interrupts */
+
+/*********************************************************************************************************************/
+/*---------------------------------Configuration for Trap Hook Functions' Extensions---------------------------------*/
+/*********************************************************************************************************************/
+/* #define IFX_CFG_EXTEND_TRAP_HOOKS */ /* Decomment this line if the project needs to extend trap hook functions */
+
+#endif /* IFX_CFG_H */
+
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Platform/Tricore/Compilers/CompilerDcc.c b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Platform/Tricore/Compilers/CompilerDcc.c
new file mode 100644
index 0000000..c34dc04
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Platform/Tricore/Compilers/CompilerDcc.c
@@ -0,0 +1,76 @@
+/**
+ * \file CompilerDcc.c
+ *
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ * $Date: 2014-02-27 20:08:39 GMT$
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ */
+
+#include "Cpu/Std/Ifx_Types.h"
+#include "Compilers.h"
+
+#if defined(__DCC__)
+/*!
+ * \brief Initializes C variables
+ *
+ * This function is called in the startup. This function initialize the all variables in .data section
+ * and clears the .bss section
+ *
+ * Parameters: Nil
+ * Return: Nil
+ */
+void Ifx_C_Init(void)
+{
+ extern void __init_main(void);
+
+ __init_main(); /* initialize data */
+}
+
+
+#ifndef IFX_CFG_USE_COMPILER_DEFAULT_LINKER
+/*Dummy main function
+ * This function is required only for the Windriver, which looks for main while linking
+ * ! DO NOT USE THIS FUNCTION !*/
+int main(void)
+{
+ return 0;
+}
+
+
+#endif /*IFX_CFG_USE_COMPILER_DEFAULT_LINKER */
+#endif
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Platform/Tricore/Compilers/CompilerDcc.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Platform/Tricore/Compilers/CompilerDcc.h
new file mode 100644
index 0000000..cb1a7a7
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Platform/Tricore/Compilers/CompilerDcc.h
@@ -0,0 +1,170 @@
+/**
+ * \file CompilerDcc.h
+ *
+ * \version iLLD_New
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ */
+
+#ifndef COMPILERDCC_H
+#define COMPILERDCC_H 1
+
+/******************************************************************************/
+
+#include
+
+/*Linker definitions which are specific to Dcc */
+/* IFX_CFG_USE_COMPILER_DEFAULT_LINKER shall be defined in Ifx_Cfg.h
+ * to use the default compiler linker varaibles and startup */
+#ifndef IFX_CFG_USE_COMPILER_DEFAULT_LINKER
+
+/*Start: Core 0 definitions ********************************************** */
+
+/*C extern defintions */
+#define IFXCOMPILER_CORE_LINKER_SYMBOLS(cpu) \
+ extern unsigned int __USTACK##cpu[]; /**< user stack end */ \
+ extern unsigned int __ISTACK##cpu[]; /**< interrupt stack end */ \
+ extern unsigned int __INTTAB_CPU##cpu[]; /**< interrupt vector table */ \
+ extern unsigned int __TRAPTAB_CPU##cpu[]; /**< trap vector table */ \
+ extern unsigned int __CSA##cpu[]; /**< context save area begin */ \
+ extern unsigned int __CSA##cpu##_END[]; /**< context save area end */
+
+#define __USTACK(cpu) __USTACK##cpu
+#define __ISTACK(cpu) __ISTACK##cpu
+#define __INTTAB_CPU(cpu) __INTTAB_CPU##cpu
+#define __TRAPTAB_CPU(cpu) __TRAPTAB_CPU##cpu
+#define __CSA(cpu) __CSA##cpu
+#define __CSA_END(cpu) __CSA##cpu##_END
+
+#define IFXCOMPILER_COMMON_LINKER_SYMBOLS() \
+ __asm("\t .weak __A8_MEM, __A9_MEM"); /**< ASM extern definitions */
+
+/*Wrapper macros for the tool specific definitions */
+#if defined(IFX_USE_SW_MANAGED_INT)
+#define __INTTAB(cpu) ((unsigned int)__INTTAB_CPU##cpu | (unsigned int)0x1FE0)
+#else
+#define __INTTAB(cpu) __INTTAB_CPU##cpu
+#endif /*defined(IFX_USE_SW_MANAGED_INT) */
+
+#define __TRAPTAB(cpu) __TRAPTAB_CPU##cpu
+
+#define __SDATA1(cpu) _SMALL_DATA_
+#define __SDATA2(cpu) _LITERAL_DATA_
+#define __SDATA3(cpu) __A8_MEM
+#define __SDATA4(cpu) __A9_MEM
+
+#endif /*IFX_CFG_USE_COMPILER_DEFAULT_LINKER*/
+
+/******************************************************************************/
+#define IFX_INLINE static __inline__
+
+/* FXIME check how to pack structure members */
+#define IFX_PACKED
+
+#define COMPILER_NAME "DCC"
+#define COMPILER_VERSION __VERSION__
+
+#define COMPILER_REVISION 0
+#define IFX_INTERRUPT_FAST IFX_INTERRUPT
+
+#if defined(IFX_USE_SW_MANAGED_INT)
+
+#ifndef IFX_INTERRUPT
+#define IFX_INTERRUPT(isr, vectabNum, prio) void isr(void)
+#endif
+
+#else
+/* *INDENT-OFF* */
+
+#ifndef IFX_INTERRUPT
+#define IFX_INTERRUPT(isr, vectabNum, prio) IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio)
+#endif
+#endif /*defined(IFX_USE_SW_MANAGED_INT)*/
+
+#ifndef IFX_INTERRUPT_INTERNAL
+#define IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio) \
+void __interrupt(prio) __vector_table(vectabNum) isr(void)
+#endif
+
+/*Macro IFX_INTERRUPT_LEGACY is to be used for compiler version pror to 5.9.3.0*/
+#define IFX_INTERRUPT_LEGACY(isr, vectabNum, prio) \
+__asm ("\t.align\t 5\n\t\
+.section .int."#prio"\n \t.sectionlink .inttab"#vectabNum".intvec."#prio"\n\
+#$$bf\n\
+__intvec_tc"#vectabNum"_"#prio":\n\
+ movh.a\t %a14,"#isr"@ha\n\
+ lea\t %a14,[%a14]"#isr"@l\n\
+ ji\t %a14\n\
+#$$ef\n\t\
+.section .intend."#prio"\n \t.sectionlink .text");\
+__interrupt__ void isr (void)
+
+/* *INDENT-ON* */
+
+/******************************************************************************/
+
+#define IFX_ALIGN(n) __attribute__ ((aligned(n)))
+
+/******************************************************************************/
+/*Memory qualifiers*/
+#ifndef IFX_FAR_ABS
+#define IFX_FAR_ABS
+#endif
+
+#ifndef IFX_NEAR_ABS
+#define IFX_NEAR_ABS
+#endif
+
+#ifndef IFX_REL_A0
+#define IFX_REL_A0
+#endif
+
+#ifndef IFX_REL_A1
+#define IFX_REL_A1
+#endif
+
+#ifndef IFX_REL_A8
+#define IFX_REL_A8
+#endif
+
+#ifndef IFX_REL_A9
+#define IFX_REL_A9
+#endif
+/******************************************************************************/
+
+#endif /* COMPILERDCC_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Platform/Tricore/Compilers/CompilerGhs.c b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Platform/Tricore/Compilers/CompilerGhs.c
new file mode 100644
index 0000000..272b257
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Platform/Tricore/Compilers/CompilerGhs.c
@@ -0,0 +1,113 @@
+/**
+ * \file CompilerGhs.c
+ *
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ * $Date: 2014-02-27 20:08:40 GMT$
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ */
+
+#include "Cpu/Std/Ifx_Types.h"
+#include "Compilers.h"
+
+#if defined(__ghs__) && !defined(WIN32)
+
+typedef int ptrdiff_t;
+typedef unsigned int syze_t;
+typedef signed int signed_size_t;
+#define size_t syze_t
+
+extern void *memcpy(void *s1, const void *s2, syze_t n);
+extern void *memset(void *s, int c, syze_t n);
+
+/* rodata is absolute */
+typedef const char rodata_ptr[];
+# define PIRBASE 0
+
+#define CONST_FUNCP *const
+
+/*!
+ * \brief Initializes C variables.
+ *
+ * This function is called in the startup. This function initialize the all variables in .data section
+ * and clears the .bss section
+ *
+ * Parameters: Nil
+ * Return: Nil
+ */
+void Ifx_C_Init(void)
+{
+ /*----------------------------------------------------------------------*/
+ /* */
+ /* Clear BSS */
+ /* */
+ /*----------------------------------------------------------------------*/
+ { /* The .secinfo section is in text; declare functions to force PIC */
+
+ #pragma ghs rodata
+ extern rodata_ptr __ghsbinfo_clear;
+ #pragma ghs rodata
+ extern rodata_ptr __ghseinfo_clear;
+
+ void **b = (void **) ((char *)__ghsbinfo_clear);
+ void **e = (void **) ((char *)__ghseinfo_clear);
+
+ while (b != e) {
+ void * t; /* target pointer */
+ ptrdiff_t v; /* value to set */
+ size_t n; /* set n bytes */
+ t = (char *)(*b++);
+ v = *((ptrdiff_t *) b); b++;
+ n = *((size_t *) b); b++;
+ memset(t, v, n);
+ }
+ }
+
+ /*----------------*/
+ /* initialize iob */
+ /*----------------*/
+ {
+ #pragma weak __gh_iob_init
+ extern void __gh_iob_init(void);
+ static void (CONST_FUNCP iob_init_funcp)(void) = __gh_iob_init;
+ /* if cciob.c is loaded, initialize _iob for stdin,stdout,stderr */
+ if (iob_init_funcp) __gh_iob_init();
+ }
+}
+
+
+#endif
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Platform/Tricore/Compilers/CompilerGhs.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Platform/Tricore/Compilers/CompilerGhs.h
new file mode 100644
index 0000000..3ed49f2
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Platform/Tricore/Compilers/CompilerGhs.h
@@ -0,0 +1,173 @@
+/**
+ * \file CompilerGhs.h
+ *
+ * \version iLLD_New
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ */
+
+#ifndef COMPILERGHS_H
+#define COMPILERGHS_H 1
+
+/******************************************************************************/
+
+// #include
+
+/*Linker definitions which are specific to Ghs */
+/* IFX_CFG_USE_COMPILER_DEFAULT_LINKER shall be defined in Ifx_Cfg.h
+ * to use the default compiler linker varaibles and startup */
+#ifndef IFX_CFG_USE_COMPILER_DEFAULT_LINKER
+
+/*Start: Common definitions ********************************************** */
+#define IFXCOMPILER_COMMON_LINKER_SYMBOLS() \
+ extern unsigned int __A0_MEM[]; /**< center of A0 addressable area */ \
+ extern unsigned int __A1_MEM[]; /**< center of A1 addressable area */ \
+ extern unsigned int __A8_MEM[]; /**< center of A8 addressable area */ \
+ extern unsigned int __A9_MEM[]; /**< center of A9 addressable area */
+
+/*End: Common definitions ************************************************ */
+
+/*Start: Core 0 definitions ********************************************** */
+
+/*C extern defintions */
+#define IFXCOMPILER_CORE_LINKER_SYMBOLS(cpu) \
+ extern unsigned int __USTACK##cpu[]; /**< user stack end */ \
+ extern unsigned int __ISTACK##cpu[]; /**< interrupt stack end */ \
+ extern unsigned int __INTTAB_CPU##cpu[]; /**< Interrupt vector table */ \
+ extern unsigned int __TRAPTAB_CPU##cpu[]; /**< trap table */ \
+ extern unsigned int __CSA##cpu[]; /**< context save area 1 begin */ \
+ extern unsigned int __CSA##cpu##_END[]; /**< context save area 1 begin */
+
+#define __USTACK(cpu) __USTACK##cpu
+#define __ISTACK(cpu) __ISTACK##cpu
+#define __INTTAB_CPU(cpu) __INTTAB_CPU##cpu
+#define __TRAPTAB_CPU(cpu) __TRAPTAB_CPU##cpu
+#define __CSA(cpu) __CSA##cpu
+#define __CSA_END(cpu) __CSA##cpu##_END
+
+/*Wrapper macros for the tool specific definitions */
+#if defined(IFX_USE_SW_MANAGED_INT)
+#define __INTTAB(cpu) ((unsigned int)__INTTAB_CPU##cpu | (unsigned int)0x1FE0)
+#else
+#define __INTTAB(cpu) __INTTAB_CPU##cpu
+#endif /*defined(IFX_USE_SW_MANAGED_INT) */
+
+#define __TRAPTAB(cpu) __TRAPTAB_CPU##cpu
+
+#define __SDATA1(cpu) __A0_MEM
+#define __SDATA2(cpu) __A1_MEM
+#define __SDATA3(cpu) __A8_MEM
+#define __SDATA4(cpu) __A9_MEM
+
+/* MHWS+
+#define __SDATA1(cpu) __A0_MEM
+#define __SDATA2(cpu) __A1_MEM
+#define __SDATA3(cpu) __A8_MEM
+#define __SDATA4(cpu) __A9_MEM
+MHWS- */
+#endif /*IFX_CFG_USE_COMPILER_DEFAULT_LINKER*/
+
+/******************************************************************************/
+#ifndef IFX_INLINE
+#define IFX_INLINE static inline __attribute__ ((always_inline)) /*Makes the function always inlined */
+#endif
+
+#define IFX_PACKED __packed
+
+#define COMPILER_NAME "GHS"
+#define COMPILER_VERSION __GHS_VERSION_NUMBER
+
+#define COMPILER_REVISION __GHS_REVISION_VALUE
+
+#if defined(IFX_USE_SW_MANAGED_INT)
+
+#ifndef IFX_INTERRUPT
+#define IFX_INTERRUPT(isr, vectabNum, prio) void isr(void)
+#endif
+
+#else
+/* *INDENT-OFF* */
+
+#ifndef IFX_INTERRUPT
+#define IFX_INTERRUPT(isr, vectabNum, prio) IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio)
+#endif
+#endif /*defined(IFX_USE_SW_MANAGED_INT)*/
+
+#define IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio) \
+__attribute__((section(".intvec_tc"#vectabNum"_"#prio))) void iVecEntry##vectabNum##_##prio(void) \
+{ \
+ __asm__("movh.a a14, %hi("#isr") \n" \
+ "lea a14, [a14]%lo("#isr")\n" \
+ "ji a14"); \
+} \
+__interrupt void isr(void)
+
+/* *INDENT-ON* */
+
+/******************************************************************************/
+
+#define IFX_ALIGN(n) __attribute__ ((aligned(n)))
+
+/******************************************************************************/
+/*Memory qualifiers*/
+#ifndef IFX_FAR_ABS
+#define IFX_FAR_ABS __attribute__((fardata))
+#endif
+
+#ifndef IFX_NEAR_ABS
+#define IFX_NEAR_ABS
+#endif
+
+#ifndef IFX_REL_A0
+#define IFX_REL_A0
+#endif
+
+#ifndef IFX_REL_A1
+#define IFX_REL_A1
+#endif
+
+#ifndef IFX_REL_A8
+#define IFX_REL_A8
+#endif
+
+#ifndef IFX_REL_A9
+#define IFX_REL_A9
+#endif
+/******************************************************************************/
+
+#endif /* COMPILERGHS_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Platform/Tricore/Compilers/CompilerGnuc.c b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Platform/Tricore/Compilers/CompilerGnuc.c
new file mode 100644
index 0000000..450b08d
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Platform/Tricore/Compilers/CompilerGnuc.c
@@ -0,0 +1,153 @@
+/**
+ * \file CompilerGnuc.c
+ *
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ * $Date: 2014-02-27 20:08:40 GMT$
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ */
+
+#include "Cpu/Std/Ifx_Types.h"
+#include "Compilers.h"
+
+#if defined(__HIGHTEC__) && !defined(WIN32)
+/*!
+ * \brief Data s C variables.
+ */
+extern uint32 __clear_table[]; /**< clear table entry */
+extern uint32 __copy_table[]; /**< copy table entry */
+
+typedef volatile union
+{
+ uint8 *ucPtr;
+ uint16 *usPtr;
+ uint32 *uiPtr;
+ unsigned long long *ullPtr;
+} IfxStart_CTablePtr;
+
+/*!
+ * \brief Initializes C variables.
+ *
+ * This function is called in the startup. This function initialize the all variables in .data section
+ * and clears the .bss section
+ *
+ * Parameters: Nil
+ * Return: Nil
+ */
+void Ifx_C_Init(void)
+{
+ IfxStart_CTablePtr pBlockDest, pBlockSrc;
+ uint32 uiLength, uiCnt;
+ uint32 *pTable;
+ /* clear table */
+ pTable = (uint32 *)&__clear_table;
+
+ while (pTable)
+ {
+ pBlockDest.uiPtr = (uint32 *)*pTable++;
+ uiLength = *pTable++;
+
+ /* we are finished when length == -1 */
+ if (uiLength == 0xFFFFFFFF)
+ {
+ break;
+ }
+
+ uiCnt = uiLength / 8;
+
+ while (uiCnt--)
+ {
+ *pBlockDest.ullPtr++ = 0;
+ }
+
+ if (uiLength & 0x4)
+ {
+ *pBlockDest.uiPtr++ = 0;
+ }
+
+ if (uiLength & 0x2)
+ {
+ *pBlockDest.usPtr++ = 0;
+ }
+
+ if (uiLength & 0x1)
+ {
+ *pBlockDest.ucPtr = 0;
+ }
+ }
+
+ /* copy table */
+ pTable = (uint32 *)&__copy_table;
+
+ while (pTable)
+ {
+ pBlockSrc.uiPtr = (uint32 *)*pTable++;
+ pBlockDest.uiPtr = (uint32 *)*pTable++;
+ uiLength = *pTable++;
+
+ /* we are finished when length == -1 */
+ if (uiLength == 0xFFFFFFFF)
+ {
+ break;
+ }
+
+ uiCnt = uiLength / 8;
+
+ while (uiCnt--)
+ {
+ *pBlockDest.ullPtr++ = *pBlockSrc.ullPtr++;
+ }
+
+ if (uiLength & 0x4)
+ {
+ *pBlockDest.uiPtr++ = *pBlockSrc.uiPtr++;
+ }
+
+ if (uiLength & 0x2)
+ {
+ *pBlockDest.usPtr++ = *pBlockSrc.usPtr++;
+ }
+
+ if (uiLength & 0x1)
+ {
+ *pBlockDest.ucPtr = *pBlockSrc.ucPtr;
+ }
+ }
+}
+
+
+#endif
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Platform/Tricore/Compilers/CompilerGnuc.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Platform/Tricore/Compilers/CompilerGnuc.h
new file mode 100644
index 0000000..e816340
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Platform/Tricore/Compilers/CompilerGnuc.h
@@ -0,0 +1,186 @@
+/**
+ * \file CompilerGnuc.h
+ *
+ * \version iLLD_New
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ */
+
+#ifndef COMPILERGNUC_H
+#define COMPILERGNUC_H 1
+
+/******************************************************************************/
+
+#include
+
+/*Linker definitions which are specific to Gnuc */
+/* IFX_CFG_USE_COMPILER_DEFAULT_LINKER shall be defined in Ifx_Cfg.h
+ * to use the default compiler linker varaibles and startup */
+#ifndef IFX_CFG_USE_COMPILER_DEFAULT_LINKER
+
+/*Start: Common definitions ********************************************** */
+#define IFXCOMPILER_COMMON_LINKER_SYMBOLS() \
+ extern unsigned int __A0_MEM[]; /**< center of A0 addressable area */ \
+ extern unsigned int __A1_MEM[]; /**< center of A1 addressable area */ \
+ extern unsigned int __A8_MEM[]; /**< center of A8 addressable area */ \
+ extern unsigned int __A9_MEM[]; /**< center of A9 addressable area */
+
+/*End: Common definitions ************************************************ */
+
+/*Start: Core 0 definitions ********************************************** */
+
+/*C extern defintions */
+#define IFXCOMPILER_CORE_LINKER_SYMBOLS(cpu) \
+ extern unsigned int __USTACK##cpu[]; /**< user stack end */ \
+ extern unsigned int __ISTACK##cpu[]; /**< interrupt stack end */ \
+ extern unsigned int __INTTAB_CPU##cpu[]; /**< Interrupt vector table */ \
+ extern unsigned int __TRAPTAB_CPU##cpu[]; /**< trap table */ \
+ extern unsigned int __CSA##cpu[]; /**< context save area 1 begin */ \
+ extern unsigned int __CSA##cpu##_END[]; /**< context save area 1 begin */
+
+#define __USTACK(cpu) __USTACK##cpu
+#define __ISTACK(cpu) __ISTACK##cpu
+#define __INTTAB_CPU(cpu) __INTTAB_CPU##cpu
+#define __TRAPTAB_CPU(cpu) __TRAPTAB_CPU##cpu
+#define __CSA(cpu) __CSA##cpu
+#define __CSA_END(cpu) __CSA##cpu##_END
+
+/*Wrapper macros for the tool specific definitions */
+#if defined(IFX_USE_SW_MANAGED_INT)
+#define __INTTAB(cpu) ((unsigned int)__INTTAB_CPU##cpu | (unsigned int)0x1FE0)
+#else
+#define __INTTAB(cpu) __INTTAB_CPU##cpu
+#endif /*defined(IFX_USE_SW_MANAGED_INT) */
+
+#define __TRAPTAB(cpu) __TRAPTAB_CPU##cpu
+
+#define __SDATA1(cpu) __A0_MEM
+#define __SDATA2(cpu) __A1_MEM
+#define __SDATA3(cpu) __A8_MEM
+#define __SDATA4(cpu) __A9_MEM
+
+#endif /*IFX_CFG_USE_COMPILER_DEFAULT_LINKER*/
+
+/******************************************************************************/
+#ifndef IFX_INLINE
+#define IFX_INLINE static inline __attribute__ ((always_inline)) /*Makes the function always inlined */
+#endif
+
+#define IFX_PACKED __attribute__ ((packed))
+
+#define COMPILER_NAME "GNUC"
+#define COMPILER_VERSION __VERSION__
+
+#define COMPILER_REVISION 0
+
+#define IFX_INTERRUPT_FAST IFX_INTERRUPT
+
+#if defined(IFX_USE_SW_MANAGED_INT)
+
+#ifndef IFX_INTERRUPT
+#define IFX_INTERRUPT(isr, vectabNum, prio) void isr(void)
+#endif
+
+#else
+/* *INDENT-OFF* */
+#ifndef IFX_INTERRUPT
+#define IFX_INTERRUPT(isr, vectabNum, prio) IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio)
+#endif
+#endif /*defined(IFX_USE_SW_MANAGED_INT)*/
+
+#ifndef IFX_INTERRUPT_INTERNAL
+#define IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio) \
+__asm__ (".ifndef .intr.entry.include \n"\
+ ".altmacro \n"\
+ ".macro .int_entry.2 intEntryLabel, name # define the section and inttab entry code \n"\
+ " .pushsection .\\intEntryLabel,\"ax\",@progbits \n"\
+ " __\\intEntryLabel : \n"\
+ " svlcx \n"\
+ " movh.a %a14, hi:\\name \n"\
+ " lea %a14, [%a14]lo:\\name \n"\
+ " ji %a14 \n"\
+ " .popsection \n"\
+ ".endm \n"\
+ ".macro .int_entry.1 prio,vectabNum,u,name \n"\
+ ".int_entry.2 intvec_tc\\vectabNum\\u\\prio,(name) # build the unique name \n"\
+ ".endm \n"\
+ " \n"\
+ ".macro .intr.entry name,vectabNum,prio \n"\
+ ".int_entry.1 %(prio),%(vectabNum),_,name # evaluate the priority and the cpu number \n"\
+ ".endm \n"\
+ ".intr.entry.include: \n"\
+ ".endif \n"\
+ ".intr.entry "#isr","#vectabNum","#prio );\
+IFX_EXTERN void __attribute__ ((interrupt_handler)) isr(); \
+void isr (void)
+#endif /* IFX_INTERRUPT_INTERNAL */
+
+/* *INDENT-ON* */
+
+/******************************************************************************/
+
+#define IFX_ALIGN(n) __attribute__ ((aligned(n)))
+
+/******************************************************************************/
+/*Memory qualifiers*/
+#ifndef IFX_FAR_ABS
+#define IFX_FAR_ABS __attribute__((fardata))
+#endif
+
+#ifndef IFX_NEAR_ABS
+#define IFX_NEAR_ABS
+#endif
+
+#ifndef IFX_REL_A0
+#define IFX_REL_A0
+#endif
+
+#ifndef IFX_REL_A1
+#define IFX_REL_A1
+#endif
+
+#ifndef IFX_REL_A8
+#define IFX_REL_A8
+#endif
+
+#ifndef IFX_REL_A9
+#define IFX_REL_A9
+#endif
+/******************************************************************************/
+
+#endif /* COMPILERGNUC_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Platform/Tricore/Compilers/CompilerTasking.c b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Platform/Tricore/Compilers/CompilerTasking.c
new file mode 100644
index 0000000..9698d75
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Platform/Tricore/Compilers/CompilerTasking.c
@@ -0,0 +1,65 @@
+/**
+ * \file CompilerTasking.c
+ *
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ * $Date: 2014-02-27 20:08:41 GMT$
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ */
+
+#include "Cpu/Std/Ifx_Types.h"
+#include "Compilers.h"
+
+#if defined(__TASKING__)
+/*!
+ * \brief Initializes C variables
+ *
+ * This function is called in the startup. This function initialize the all variables in .data section
+ * and clears the .bss section
+ *
+ * Parameters: Nil
+ * Return: Nil
+ */
+void Ifx_C_Init(void)
+{
+ extern void _c_init(void);
+
+ _c_init(); /* initialize data */
+}
+
+
+#endif
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Platform/Tricore/Compilers/CompilerTasking.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Platform/Tricore/Compilers/CompilerTasking.h
new file mode 100644
index 0000000..ec7c6e2
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Platform/Tricore/Compilers/CompilerTasking.h
@@ -0,0 +1,165 @@
+/**
+ * \file CompilerTasking.h
+ *
+ * \version iLLD_New
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ */
+
+#ifndef COMPILERTASKING_H
+#define COMPILERTASKING_H 1
+
+/******************************************************************************/
+
+#include
+
+/*Linker definitions which are specific to Tasking */
+/* IFX_CFG_USE_COMPILER_DEFAULT_LINKER shall be defined in Ifx_Cfg.h
+ * to use the default compiler linker varaibles and startup */
+#ifndef IFX_CFG_USE_COMPILER_DEFAULT_LINKER
+
+#ifndef __cplusplus
+/*Start: Common definitions ********************************************** */
+#define IFXCOMPILER_COMMON_LINKER_SYMBOLS() \
+ __asm("\t .extern _SMALL_DATA_, _LITERAL_DATA_, _A8_DATA_, _A9_DATA_");
+
+/*End: Common definitions ********************************************** */
+
+/*Start: Core 0 definitions ********************************************** */
+
+#define IFXCOMPILER_CORE_LINKER_SYMBOLS(cpu) \
+ __asm("\t .extern __USTACK"#cpu); /**< user stack end is required as asm to be used with setreg macro */ \
+ extern unsigned int __ISTACK##cpu[]; /**< interrupt stack end */ \
+ extern unsigned int __INTTAB_CPU##cpu[]; /**< interrupt vector table */ \
+ extern unsigned int __TRAPTAB_CPU##cpu[]; /**< trap vector table */ \
+ extern unsigned int __CSA##cpu[]; /**< context save area begin */ \
+ extern unsigned int __CSA##cpu##_END[]; /**< context save area end */
+#endif
+
+#define __USTACK(cpu) __USTACK##cpu
+#define __ISTACK(cpu) __ISTACK##cpu
+#define __INTTAB_CPU(cpu) __INTTAB_CPU##cpu
+#define __TRAPTAB_CPU(cpu) __TRAPTAB_CPU##cpu
+#define __CSA(cpu) __CSA##cpu
+#define __CSA_END(cpu) __CSA##cpu##_END
+
+/*Wrapper macros for the tool specific definitions */
+#if defined(IFX_USE_SW_MANAGED_INT)
+#define __INTTAB(cpu) ((unsigned int)__INTTAB_CPU##cpu | (unsigned int)0x1FE0)
+#else
+#define __INTTAB(cpu) __INTTAB_CPU##cpu
+#endif /*defined(IFX_USE_SW_MANAGED_INT) */
+
+#define __TRAPTAB(cpu) __TRAPTAB_CPU##cpu
+
+#define __SDATA1(cpu) _SMALL_DATA_
+#define __SDATA2(cpu) _LITERAL_DATA_
+#define __SDATA3(cpu) _A8_DATA_
+#define __SDATA4(cpu) _A9_DATA_
+
+#endif /*IFX_CFG_USE_COMPILER_DEFAULT_LINKER*/
+
+/******************************************************************************/
+#ifdef __cplusplus
+#define IFX_INLINE static inline
+#else
+#define IFX_INLINE inline
+#endif
+
+/* FXIME check how to pack structure members */
+#define IFX_PACKED
+
+#define COMPILER_NAME "TASKING"
+#define COMPILER_VERSION __VERSION__
+
+/* Note that __REVISION__ is only available for tasking compiler! */
+#define COMPILER_REVISION __REVISION__
+
+/******************************************************************************/
+
+#if defined(IFX_USE_SW_MANAGED_INT)
+
+#ifndef IFX_INTERRUPT
+#define IFX_INTERRUPT(isr, vectabNum, prio) void isr(void)
+#endif
+
+#else
+/* *INDENT-OFF* */
+#ifndef IFX_INTERRUPT
+#define IFX_INTERRUPT(isr, vectabNum, prio) IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio)
+#endif
+#define IFX_INTERRUPT_FAST(isr, vectabNum, prio) void __interrupt_fast(prio) __vector_table(vectabNum) isr(void)
+
+#endif /*defined(IFX_USE_SW_MANAGED_INT)*/
+
+#define IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio) void __interrupt(prio) __vector_table(vectabNum) isr(void)
+
+/* *INDENT-ON* */
+
+/******************************************************************************/
+
+#define IFX_ALIGN(n) __attribute__ ((__align(n)))
+
+/******************************************************************************/
+/*Memory qualifiers*/
+#ifndef IFX_FAR_ABS
+#define IFX_FAR_ABS __far
+#endif
+
+#ifndef IFX_NEAR_ABS
+#define IFX_NEAR_ABS __near
+#endif
+
+#ifndef IFX_REL_A0
+#define IFX_REL_A0 __a0
+#endif
+
+#ifndef IFX_REL_A1
+#define IFX_REL_A1 __a1
+#endif
+
+#ifndef IFX_REL_A8
+#define IFX_REL_A8 __a8
+#endif
+
+#ifndef IFX_REL_A9
+#define IFX_REL_A9 __a9
+#endif
+/******************************************************************************/
+
+#endif /* COMPILERTASKING_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Platform/Tricore/Compilers/Compilers.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Platform/Tricore/Compilers/Compilers.h
new file mode 100644
index 0000000..9930f14
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Platform/Tricore/Compilers/Compilers.h
@@ -0,0 +1,144 @@
+/**
+ * \file Compilers.h
+ *
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ * $Date: 2014-04-07 12:13:19 GMT$
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ */
+
+#ifndef COMPILERS_H
+#define COMPILERS_H 1
+
+/******************************************************************************/
+
+#include "Ifx_Cfg.h"
+
+/*this file shall not be modified by the user, IFX_XXXX defines shall be defined in Ifx_Cfg.h */
+#ifndef IFX_STATIC
+#define IFX_STATIC static
+#endif
+
+#ifndef IFX_CONST
+#define IFX_CONST const
+#endif
+#ifndef CONST_CFG
+#define CONST_CFG const /* configuration constants are stored in ROM */
+#endif
+
+#ifdef __cplusplus
+#define IFX_EXTERN extern "C"
+#else
+#define IFX_EXTERN extern
+#endif
+
+#ifndef NULL_PTR
+#ifdef __cplusplus
+#define NULL_PTR (0)
+#else /*#ifdef __cplusplus */
+#define NULL_PTR ((void *)0)
+#endif /*#ifdef __cplusplus */
+#endif /*#ifndef NULL_PTR */
+
+#ifndef CFG_LONG_SIZE_T
+#define CFG_LONG_SIZE_T (0)
+#endif
+
+#if defined(__DCC__)
+#include "CompilerDcc.h"
+
+#elif defined(__HIGHTEC__)
+#include "CompilerGnuc.h"
+
+#elif defined(__TASKING__)
+#include "CompilerTasking.h"
+
+#elif defined(__ghs__)
+#include "CompilerGhs.h"
+
+#elif defined(__MSVC__)
+#include "CompilerMsvc.h"
+
+#else
+
+/** \addtogroup IfxLld_Cpu_Std_Interrupt
+ * \{ */
+/** \brief Macro to define Interrupt Service Routine.
+ * This macro makes following definitions:\n
+ * 1) Define linker section as .intvec_tc_.\n
+ * 2) define compiler specific attribute for the interrupt functions.\n
+ * 3) define the Interrupt service routine as Isr function.\n
+ * To get details about usage of this macro, refer \ref IfxLld_Cpu_Irq_Usage
+ *
+ * \param isr Name of the Isr function.
+ * \param vectabNum Vector table number.
+ * \param prio Interrupt priority. Refer Usage of Interrupt Macro for more details.
+ */
+#define IFX_INTERRUPT(isr, vectabNum, prio)
+
+/** \} */
+#error "Compiler unsupported"
+#endif
+
+#if defined(__HIGHTEC__)
+#define BEGIN_DATA_SECTION(sec) DATA_SECTION(section #sec aw 4)
+#define DATA_SECTION(sec) _Pragma(#sec)
+#define END_DATA_SECTION DATA_SECTION(section)
+#elif defined(__TASKING__)
+#define BEGIN_DATA_SECTION(sec) DATA_SECTION(section farbss #sec)
+#define DATA_SECTION(sec) _Pragma(#sec)
+#define END_DATA_SECTION DATA_SECTION(section farbss align restore) \
+ DATA_SECTION(section farbss)
+#elif defined(__DCC__)
+#define BEGIN_DATA_SECTION(sec) DATA_SECTION(section #sec WX)
+#define DATA_SECTION(sec) _Pragma(#sec)
+#define END_DATA_SECTION DATA_SECTION(section DATA X)
+#elif defined(__ghs__)
+#define BEGIN_DATA_SECTION(sec) DATA_SECTION(section #sec WX)
+#define DATA_SECTION(sec) _Pragma(#sec)
+#define END_DATA_SECTION DATA_SECTION(section DATA X)
+#else
+#error "Please specify compiler."
+#endif
+
+/* Functions prototypes */
+/******************************************************************************/
+void Ifx_C_Init(void);
+/******************************************************************************/
+
+
+#endif /* COMPILERS_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxAsclin_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxAsclin_bf.h
new file mode 100644
index 0000000..a7e1a87
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxAsclin_bf.h
@@ -0,0 +1,1764 @@
+/**
+ * \file IfxAsclin_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Asclin_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Asclin
+ *
+ */
+#ifndef IFXASCLIN_BF_H
+#define IFXASCLIN_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Asclin_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN0 */
+#define IFX_ASCLIN_ACCEN0_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN0 */
+#define IFX_ASCLIN_ACCEN0_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN0 */
+#define IFX_ASCLIN_ACCEN0_EN0_OFF (0u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN10 */
+#define IFX_ASCLIN_ACCEN0_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN10 */
+#define IFX_ASCLIN_ACCEN0_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN10 */
+#define IFX_ASCLIN_ACCEN0_EN10_OFF (10u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN11 */
+#define IFX_ASCLIN_ACCEN0_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN11 */
+#define IFX_ASCLIN_ACCEN0_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN11 */
+#define IFX_ASCLIN_ACCEN0_EN11_OFF (11u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN12 */
+#define IFX_ASCLIN_ACCEN0_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN12 */
+#define IFX_ASCLIN_ACCEN0_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN12 */
+#define IFX_ASCLIN_ACCEN0_EN12_OFF (12u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN13 */
+#define IFX_ASCLIN_ACCEN0_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN13 */
+#define IFX_ASCLIN_ACCEN0_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN13 */
+#define IFX_ASCLIN_ACCEN0_EN13_OFF (13u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN14 */
+#define IFX_ASCLIN_ACCEN0_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN14 */
+#define IFX_ASCLIN_ACCEN0_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN14 */
+#define IFX_ASCLIN_ACCEN0_EN14_OFF (14u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN15 */
+#define IFX_ASCLIN_ACCEN0_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN15 */
+#define IFX_ASCLIN_ACCEN0_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN15 */
+#define IFX_ASCLIN_ACCEN0_EN15_OFF (15u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN16 */
+#define IFX_ASCLIN_ACCEN0_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN16 */
+#define IFX_ASCLIN_ACCEN0_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN16 */
+#define IFX_ASCLIN_ACCEN0_EN16_OFF (16u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN17 */
+#define IFX_ASCLIN_ACCEN0_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN17 */
+#define IFX_ASCLIN_ACCEN0_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN17 */
+#define IFX_ASCLIN_ACCEN0_EN17_OFF (17u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN18 */
+#define IFX_ASCLIN_ACCEN0_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN18 */
+#define IFX_ASCLIN_ACCEN0_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN18 */
+#define IFX_ASCLIN_ACCEN0_EN18_OFF (18u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN19 */
+#define IFX_ASCLIN_ACCEN0_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN19 */
+#define IFX_ASCLIN_ACCEN0_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN19 */
+#define IFX_ASCLIN_ACCEN0_EN19_OFF (19u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN1 */
+#define IFX_ASCLIN_ACCEN0_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN1 */
+#define IFX_ASCLIN_ACCEN0_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN1 */
+#define IFX_ASCLIN_ACCEN0_EN1_OFF (1u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN20 */
+#define IFX_ASCLIN_ACCEN0_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN20 */
+#define IFX_ASCLIN_ACCEN0_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN20 */
+#define IFX_ASCLIN_ACCEN0_EN20_OFF (20u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN21 */
+#define IFX_ASCLIN_ACCEN0_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN21 */
+#define IFX_ASCLIN_ACCEN0_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN21 */
+#define IFX_ASCLIN_ACCEN0_EN21_OFF (21u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN22 */
+#define IFX_ASCLIN_ACCEN0_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN22 */
+#define IFX_ASCLIN_ACCEN0_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN22 */
+#define IFX_ASCLIN_ACCEN0_EN22_OFF (22u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN23 */
+#define IFX_ASCLIN_ACCEN0_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN23 */
+#define IFX_ASCLIN_ACCEN0_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN23 */
+#define IFX_ASCLIN_ACCEN0_EN23_OFF (23u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN24 */
+#define IFX_ASCLIN_ACCEN0_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN24 */
+#define IFX_ASCLIN_ACCEN0_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN24 */
+#define IFX_ASCLIN_ACCEN0_EN24_OFF (24u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN25 */
+#define IFX_ASCLIN_ACCEN0_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN25 */
+#define IFX_ASCLIN_ACCEN0_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN25 */
+#define IFX_ASCLIN_ACCEN0_EN25_OFF (25u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN26 */
+#define IFX_ASCLIN_ACCEN0_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN26 */
+#define IFX_ASCLIN_ACCEN0_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN26 */
+#define IFX_ASCLIN_ACCEN0_EN26_OFF (26u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN27 */
+#define IFX_ASCLIN_ACCEN0_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN27 */
+#define IFX_ASCLIN_ACCEN0_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN27 */
+#define IFX_ASCLIN_ACCEN0_EN27_OFF (27u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN28 */
+#define IFX_ASCLIN_ACCEN0_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN28 */
+#define IFX_ASCLIN_ACCEN0_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN28 */
+#define IFX_ASCLIN_ACCEN0_EN28_OFF (28u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN29 */
+#define IFX_ASCLIN_ACCEN0_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN29 */
+#define IFX_ASCLIN_ACCEN0_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN29 */
+#define IFX_ASCLIN_ACCEN0_EN29_OFF (29u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN2 */
+#define IFX_ASCLIN_ACCEN0_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN2 */
+#define IFX_ASCLIN_ACCEN0_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN2 */
+#define IFX_ASCLIN_ACCEN0_EN2_OFF (2u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN30 */
+#define IFX_ASCLIN_ACCEN0_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN30 */
+#define IFX_ASCLIN_ACCEN0_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN30 */
+#define IFX_ASCLIN_ACCEN0_EN30_OFF (30u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN31 */
+#define IFX_ASCLIN_ACCEN0_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN31 */
+#define IFX_ASCLIN_ACCEN0_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN31 */
+#define IFX_ASCLIN_ACCEN0_EN31_OFF (31u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN3 */
+#define IFX_ASCLIN_ACCEN0_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN3 */
+#define IFX_ASCLIN_ACCEN0_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN3 */
+#define IFX_ASCLIN_ACCEN0_EN3_OFF (3u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN4 */
+#define IFX_ASCLIN_ACCEN0_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN4 */
+#define IFX_ASCLIN_ACCEN0_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN4 */
+#define IFX_ASCLIN_ACCEN0_EN4_OFF (4u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN5 */
+#define IFX_ASCLIN_ACCEN0_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN5 */
+#define IFX_ASCLIN_ACCEN0_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN5 */
+#define IFX_ASCLIN_ACCEN0_EN5_OFF (5u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN6 */
+#define IFX_ASCLIN_ACCEN0_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN6 */
+#define IFX_ASCLIN_ACCEN0_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN6 */
+#define IFX_ASCLIN_ACCEN0_EN6_OFF (6u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN7 */
+#define IFX_ASCLIN_ACCEN0_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN7 */
+#define IFX_ASCLIN_ACCEN0_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN7 */
+#define IFX_ASCLIN_ACCEN0_EN7_OFF (7u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN8 */
+#define IFX_ASCLIN_ACCEN0_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN8 */
+#define IFX_ASCLIN_ACCEN0_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN8 */
+#define IFX_ASCLIN_ACCEN0_EN8_OFF (8u)
+
+/** \brief Length for Ifx_ASCLIN_ACCEN0_Bits.EN9 */
+#define IFX_ASCLIN_ACCEN0_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_ACCEN0_Bits.EN9 */
+#define IFX_ASCLIN_ACCEN0_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_ACCEN0_Bits.EN9 */
+#define IFX_ASCLIN_ACCEN0_EN9_OFF (9u)
+
+/** \brief Length for Ifx_ASCLIN_BITCON_Bits.OVERSAMPLING */
+#define IFX_ASCLIN_BITCON_OVERSAMPLING_LEN (4u)
+
+/** \brief Mask for Ifx_ASCLIN_BITCON_Bits.OVERSAMPLING */
+#define IFX_ASCLIN_BITCON_OVERSAMPLING_MSK (0xfu)
+
+/** \brief Offset for Ifx_ASCLIN_BITCON_Bits.OVERSAMPLING */
+#define IFX_ASCLIN_BITCON_OVERSAMPLING_OFF (16u)
+
+/** \brief Length for Ifx_ASCLIN_BITCON_Bits.PRESCALER */
+#define IFX_ASCLIN_BITCON_PRESCALER_LEN (12u)
+
+/** \brief Mask for Ifx_ASCLIN_BITCON_Bits.PRESCALER */
+#define IFX_ASCLIN_BITCON_PRESCALER_MSK (0xfffu)
+
+/** \brief Offset for Ifx_ASCLIN_BITCON_Bits.PRESCALER */
+#define IFX_ASCLIN_BITCON_PRESCALER_OFF (0u)
+
+/** \brief Length for Ifx_ASCLIN_BITCON_Bits.SAMPLEPOINT */
+#define IFX_ASCLIN_BITCON_SAMPLEPOINT_LEN (4u)
+
+/** \brief Mask for Ifx_ASCLIN_BITCON_Bits.SAMPLEPOINT */
+#define IFX_ASCLIN_BITCON_SAMPLEPOINT_MSK (0xfu)
+
+/** \brief Offset for Ifx_ASCLIN_BITCON_Bits.SAMPLEPOINT */
+#define IFX_ASCLIN_BITCON_SAMPLEPOINT_OFF (24u)
+
+/** \brief Length for Ifx_ASCLIN_BITCON_Bits.SM */
+#define IFX_ASCLIN_BITCON_SM_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_BITCON_Bits.SM */
+#define IFX_ASCLIN_BITCON_SM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_BITCON_Bits.SM */
+#define IFX_ASCLIN_BITCON_SM_OFF (31u)
+
+/** \brief Length for Ifx_ASCLIN_BRD_Bits.LOWERLIMIT */
+#define IFX_ASCLIN_BRD_LOWERLIMIT_LEN (8u)
+
+/** \brief Mask for Ifx_ASCLIN_BRD_Bits.LOWERLIMIT */
+#define IFX_ASCLIN_BRD_LOWERLIMIT_MSK (0xffu)
+
+/** \brief Offset for Ifx_ASCLIN_BRD_Bits.LOWERLIMIT */
+#define IFX_ASCLIN_BRD_LOWERLIMIT_OFF (0u)
+
+/** \brief Length for Ifx_ASCLIN_BRD_Bits.MEASURED */
+#define IFX_ASCLIN_BRD_MEASURED_LEN (12u)
+
+/** \brief Mask for Ifx_ASCLIN_BRD_Bits.MEASURED */
+#define IFX_ASCLIN_BRD_MEASURED_MSK (0xfffu)
+
+/** \brief Offset for Ifx_ASCLIN_BRD_Bits.MEASURED */
+#define IFX_ASCLIN_BRD_MEASURED_OFF (16u)
+
+/** \brief Length for Ifx_ASCLIN_BRD_Bits.UPPERLIMIT */
+#define IFX_ASCLIN_BRD_UPPERLIMIT_LEN (8u)
+
+/** \brief Mask for Ifx_ASCLIN_BRD_Bits.UPPERLIMIT */
+#define IFX_ASCLIN_BRD_UPPERLIMIT_MSK (0xffu)
+
+/** \brief Offset for Ifx_ASCLIN_BRD_Bits.UPPERLIMIT */
+#define IFX_ASCLIN_BRD_UPPERLIMIT_OFF (8u)
+
+/** \brief Length for Ifx_ASCLIN_BRG_Bits.DENOMINATOR */
+#define IFX_ASCLIN_BRG_DENOMINATOR_LEN (12u)
+
+/** \brief Mask for Ifx_ASCLIN_BRG_Bits.DENOMINATOR */
+#define IFX_ASCLIN_BRG_DENOMINATOR_MSK (0xfffu)
+
+/** \brief Offset for Ifx_ASCLIN_BRG_Bits.DENOMINATOR */
+#define IFX_ASCLIN_BRG_DENOMINATOR_OFF (0u)
+
+/** \brief Length for Ifx_ASCLIN_BRG_Bits.NUMERATOR */
+#define IFX_ASCLIN_BRG_NUMERATOR_LEN (12u)
+
+/** \brief Mask for Ifx_ASCLIN_BRG_Bits.NUMERATOR */
+#define IFX_ASCLIN_BRG_NUMERATOR_MSK (0xfffu)
+
+/** \brief Offset for Ifx_ASCLIN_BRG_Bits.NUMERATOR */
+#define IFX_ASCLIN_BRG_NUMERATOR_OFF (16u)
+
+/** \brief Length for Ifx_ASCLIN_CLC_Bits.DISR */
+#define IFX_ASCLIN_CLC_DISR_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_CLC_Bits.DISR */
+#define IFX_ASCLIN_CLC_DISR_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_CLC_Bits.DISR */
+#define IFX_ASCLIN_CLC_DISR_OFF (0u)
+
+/** \brief Length for Ifx_ASCLIN_CLC_Bits.DISS */
+#define IFX_ASCLIN_CLC_DISS_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_CLC_Bits.DISS */
+#define IFX_ASCLIN_CLC_DISS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_CLC_Bits.DISS */
+#define IFX_ASCLIN_CLC_DISS_OFF (1u)
+
+/** \brief Length for Ifx_ASCLIN_CLC_Bits.EDIS */
+#define IFX_ASCLIN_CLC_EDIS_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_CLC_Bits.EDIS */
+#define IFX_ASCLIN_CLC_EDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_CLC_Bits.EDIS */
+#define IFX_ASCLIN_CLC_EDIS_OFF (3u)
+
+/** \brief Length for Ifx_ASCLIN_CSR_Bits.CLKSEL */
+#define IFX_ASCLIN_CSR_CLKSEL_LEN (5u)
+
+/** \brief Mask for Ifx_ASCLIN_CSR_Bits.CLKSEL */
+#define IFX_ASCLIN_CSR_CLKSEL_MSK (0x1fu)
+
+/** \brief Offset for Ifx_ASCLIN_CSR_Bits.CLKSEL */
+#define IFX_ASCLIN_CSR_CLKSEL_OFF (0u)
+
+/** \brief Length for Ifx_ASCLIN_CSR_Bits.CON */
+#define IFX_ASCLIN_CSR_CON_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_CSR_Bits.CON */
+#define IFX_ASCLIN_CSR_CON_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_CSR_Bits.CON */
+#define IFX_ASCLIN_CSR_CON_OFF (31u)
+
+/** \brief Length for Ifx_ASCLIN_DATCON_Bits.CSM */
+#define IFX_ASCLIN_DATCON_CSM_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_DATCON_Bits.CSM */
+#define IFX_ASCLIN_DATCON_CSM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_DATCON_Bits.CSM */
+#define IFX_ASCLIN_DATCON_CSM_OFF (15u)
+
+/** \brief Length for Ifx_ASCLIN_DATCON_Bits.DATLEN */
+#define IFX_ASCLIN_DATCON_DATLEN_LEN (4u)
+
+/** \brief Mask for Ifx_ASCLIN_DATCON_Bits.DATLEN */
+#define IFX_ASCLIN_DATCON_DATLEN_MSK (0xfu)
+
+/** \brief Offset for Ifx_ASCLIN_DATCON_Bits.DATLEN */
+#define IFX_ASCLIN_DATCON_DATLEN_OFF (0u)
+
+/** \brief Length for Ifx_ASCLIN_DATCON_Bits.HO */
+#define IFX_ASCLIN_DATCON_HO_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_DATCON_Bits.HO */
+#define IFX_ASCLIN_DATCON_HO_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_DATCON_Bits.HO */
+#define IFX_ASCLIN_DATCON_HO_OFF (13u)
+
+/** \brief Length for Ifx_ASCLIN_DATCON_Bits.RESPONSE */
+#define IFX_ASCLIN_DATCON_RESPONSE_LEN (8u)
+
+/** \brief Mask for Ifx_ASCLIN_DATCON_Bits.RESPONSE */
+#define IFX_ASCLIN_DATCON_RESPONSE_MSK (0xffu)
+
+/** \brief Offset for Ifx_ASCLIN_DATCON_Bits.RESPONSE */
+#define IFX_ASCLIN_DATCON_RESPONSE_OFF (16u)
+
+/** \brief Length for Ifx_ASCLIN_DATCON_Bits.RM */
+#define IFX_ASCLIN_DATCON_RM_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_DATCON_Bits.RM */
+#define IFX_ASCLIN_DATCON_RM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_DATCON_Bits.RM */
+#define IFX_ASCLIN_DATCON_RM_OFF (14u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGS_Bits.BD */
+#define IFX_ASCLIN_FLAGS_BD_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGS_Bits.BD */
+#define IFX_ASCLIN_FLAGS_BD_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGS_Bits.BD */
+#define IFX_ASCLIN_FLAGS_BD_OFF (21u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGS_Bits.CE */
+#define IFX_ASCLIN_FLAGS_CE_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGS_Bits.CE */
+#define IFX_ASCLIN_FLAGS_CE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGS_Bits.CE */
+#define IFX_ASCLIN_FLAGS_CE_OFF (25u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGS_Bits.FE */
+#define IFX_ASCLIN_FLAGS_FE_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGS_Bits.FE */
+#define IFX_ASCLIN_FLAGS_FE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGS_Bits.FE */
+#define IFX_ASCLIN_FLAGS_FE_OFF (18u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGS_Bits.FED */
+#define IFX_ASCLIN_FLAGS_FED_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGS_Bits.FED */
+#define IFX_ASCLIN_FLAGS_FED_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGS_Bits.FED */
+#define IFX_ASCLIN_FLAGS_FED_OFF (5u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGS_Bits.HT */
+#define IFX_ASCLIN_FLAGS_HT_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGS_Bits.HT */
+#define IFX_ASCLIN_FLAGS_HT_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGS_Bits.HT */
+#define IFX_ASCLIN_FLAGS_HT_OFF (19u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGS_Bits.LA */
+#define IFX_ASCLIN_FLAGS_LA_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGS_Bits.LA */
+#define IFX_ASCLIN_FLAGS_LA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGS_Bits.LA */
+#define IFX_ASCLIN_FLAGS_LA_OFF (23u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGS_Bits.LC */
+#define IFX_ASCLIN_FLAGS_LC_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGS_Bits.LC */
+#define IFX_ASCLIN_FLAGS_LC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGS_Bits.LC */
+#define IFX_ASCLIN_FLAGS_LC_OFF (24u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGS_Bits.LP */
+#define IFX_ASCLIN_FLAGS_LP_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGS_Bits.LP */
+#define IFX_ASCLIN_FLAGS_LP_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGS_Bits.LP */
+#define IFX_ASCLIN_FLAGS_LP_OFF (22u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGS_Bits.PE */
+#define IFX_ASCLIN_FLAGS_PE_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGS_Bits.PE */
+#define IFX_ASCLIN_FLAGS_PE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGS_Bits.PE */
+#define IFX_ASCLIN_FLAGS_PE_OFF (16u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGS_Bits.RED */
+#define IFX_ASCLIN_FLAGS_RED_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGS_Bits.RED */
+#define IFX_ASCLIN_FLAGS_RED_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGS_Bits.RED */
+#define IFX_ASCLIN_FLAGS_RED_OFF (6u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGS_Bits.RFL */
+#define IFX_ASCLIN_FLAGS_RFL_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGS_Bits.RFL */
+#define IFX_ASCLIN_FLAGS_RFL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGS_Bits.RFL */
+#define IFX_ASCLIN_FLAGS_RFL_OFF (28u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGS_Bits.RFO */
+#define IFX_ASCLIN_FLAGS_RFO_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGS_Bits.RFO */
+#define IFX_ASCLIN_FLAGS_RFO_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGS_Bits.RFO */
+#define IFX_ASCLIN_FLAGS_RFO_OFF (26u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGS_Bits.RFU */
+#define IFX_ASCLIN_FLAGS_RFU_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGS_Bits.RFU */
+#define IFX_ASCLIN_FLAGS_RFU_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGS_Bits.RFU */
+#define IFX_ASCLIN_FLAGS_RFU_OFF (27u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGS_Bits.RH */
+#define IFX_ASCLIN_FLAGS_RH_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGS_Bits.RH */
+#define IFX_ASCLIN_FLAGS_RH_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGS_Bits.RH */
+#define IFX_ASCLIN_FLAGS_RH_OFF (2u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGS_Bits.RR */
+#define IFX_ASCLIN_FLAGS_RR_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGS_Bits.RR */
+#define IFX_ASCLIN_FLAGS_RR_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGS_Bits.RR */
+#define IFX_ASCLIN_FLAGS_RR_OFF (3u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGS_Bits.RT */
+#define IFX_ASCLIN_FLAGS_RT_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGS_Bits.RT */
+#define IFX_ASCLIN_FLAGS_RT_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGS_Bits.RT */
+#define IFX_ASCLIN_FLAGS_RT_OFF (20u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGS_Bits.TC */
+#define IFX_ASCLIN_FLAGS_TC_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGS_Bits.TC */
+#define IFX_ASCLIN_FLAGS_TC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGS_Bits.TC */
+#define IFX_ASCLIN_FLAGS_TC_OFF (17u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGS_Bits.TFL */
+#define IFX_ASCLIN_FLAGS_TFL_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGS_Bits.TFL */
+#define IFX_ASCLIN_FLAGS_TFL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGS_Bits.TFL */
+#define IFX_ASCLIN_FLAGS_TFL_OFF (31u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGS_Bits.TFO */
+#define IFX_ASCLIN_FLAGS_TFO_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGS_Bits.TFO */
+#define IFX_ASCLIN_FLAGS_TFO_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGS_Bits.TFO */
+#define IFX_ASCLIN_FLAGS_TFO_OFF (30u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGS_Bits.TH */
+#define IFX_ASCLIN_FLAGS_TH_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGS_Bits.TH */
+#define IFX_ASCLIN_FLAGS_TH_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGS_Bits.TH */
+#define IFX_ASCLIN_FLAGS_TH_OFF (0u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGS_Bits.THRQ */
+#define IFX_ASCLIN_FLAGS_THRQ_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGS_Bits.THRQ */
+#define IFX_ASCLIN_FLAGS_THRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGS_Bits.THRQ */
+#define IFX_ASCLIN_FLAGS_THRQ_OFF (14u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGS_Bits.TR */
+#define IFX_ASCLIN_FLAGS_TR_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGS_Bits.TR */
+#define IFX_ASCLIN_FLAGS_TR_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGS_Bits.TR */
+#define IFX_ASCLIN_FLAGS_TR_OFF (1u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGS_Bits.TRRQ */
+#define IFX_ASCLIN_FLAGS_TRRQ_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGS_Bits.TRRQ */
+#define IFX_ASCLIN_FLAGS_TRRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGS_Bits.TRRQ */
+#define IFX_ASCLIN_FLAGS_TRRQ_OFF (15u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGS_Bits.TWRQ */
+#define IFX_ASCLIN_FLAGS_TWRQ_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGS_Bits.TWRQ */
+#define IFX_ASCLIN_FLAGS_TWRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGS_Bits.TWRQ */
+#define IFX_ASCLIN_FLAGS_TWRQ_OFF (13u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.BDC */
+#define IFX_ASCLIN_FLAGSCLEAR_BDC_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.BDC */
+#define IFX_ASCLIN_FLAGSCLEAR_BDC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.BDC */
+#define IFX_ASCLIN_FLAGSCLEAR_BDC_OFF (21u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.CEC */
+#define IFX_ASCLIN_FLAGSCLEAR_CEC_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.CEC */
+#define IFX_ASCLIN_FLAGSCLEAR_CEC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.CEC */
+#define IFX_ASCLIN_FLAGSCLEAR_CEC_OFF (25u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.FEC */
+#define IFX_ASCLIN_FLAGSCLEAR_FEC_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.FEC */
+#define IFX_ASCLIN_FLAGSCLEAR_FEC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.FEC */
+#define IFX_ASCLIN_FLAGSCLEAR_FEC_OFF (18u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.FEDC */
+#define IFX_ASCLIN_FLAGSCLEAR_FEDC_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.FEDC */
+#define IFX_ASCLIN_FLAGSCLEAR_FEDC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.FEDC */
+#define IFX_ASCLIN_FLAGSCLEAR_FEDC_OFF (5u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.HTC */
+#define IFX_ASCLIN_FLAGSCLEAR_HTC_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.HTC */
+#define IFX_ASCLIN_FLAGSCLEAR_HTC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.HTC */
+#define IFX_ASCLIN_FLAGSCLEAR_HTC_OFF (19u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.LAC */
+#define IFX_ASCLIN_FLAGSCLEAR_LAC_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.LAC */
+#define IFX_ASCLIN_FLAGSCLEAR_LAC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.LAC */
+#define IFX_ASCLIN_FLAGSCLEAR_LAC_OFF (23u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.LCC */
+#define IFX_ASCLIN_FLAGSCLEAR_LCC_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.LCC */
+#define IFX_ASCLIN_FLAGSCLEAR_LCC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.LCC */
+#define IFX_ASCLIN_FLAGSCLEAR_LCC_OFF (24u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.LPC */
+#define IFX_ASCLIN_FLAGSCLEAR_LPC_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.LPC */
+#define IFX_ASCLIN_FLAGSCLEAR_LPC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.LPC */
+#define IFX_ASCLIN_FLAGSCLEAR_LPC_OFF (22u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.PEC */
+#define IFX_ASCLIN_FLAGSCLEAR_PEC_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.PEC */
+#define IFX_ASCLIN_FLAGSCLEAR_PEC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.PEC */
+#define IFX_ASCLIN_FLAGSCLEAR_PEC_OFF (16u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.REDC */
+#define IFX_ASCLIN_FLAGSCLEAR_REDC_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.REDC */
+#define IFX_ASCLIN_FLAGSCLEAR_REDC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.REDC */
+#define IFX_ASCLIN_FLAGSCLEAR_REDC_OFF (6u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.RFLC */
+#define IFX_ASCLIN_FLAGSCLEAR_RFLC_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.RFLC */
+#define IFX_ASCLIN_FLAGSCLEAR_RFLC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.RFLC */
+#define IFX_ASCLIN_FLAGSCLEAR_RFLC_OFF (28u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.RFOC */
+#define IFX_ASCLIN_FLAGSCLEAR_RFOC_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.RFOC */
+#define IFX_ASCLIN_FLAGSCLEAR_RFOC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.RFOC */
+#define IFX_ASCLIN_FLAGSCLEAR_RFOC_OFF (26u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.RFUC */
+#define IFX_ASCLIN_FLAGSCLEAR_RFUC_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.RFUC */
+#define IFX_ASCLIN_FLAGSCLEAR_RFUC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.RFUC */
+#define IFX_ASCLIN_FLAGSCLEAR_RFUC_OFF (27u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.RHC */
+#define IFX_ASCLIN_FLAGSCLEAR_RHC_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.RHC */
+#define IFX_ASCLIN_FLAGSCLEAR_RHC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.RHC */
+#define IFX_ASCLIN_FLAGSCLEAR_RHC_OFF (2u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.RRC */
+#define IFX_ASCLIN_FLAGSCLEAR_RRC_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.RRC */
+#define IFX_ASCLIN_FLAGSCLEAR_RRC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.RRC */
+#define IFX_ASCLIN_FLAGSCLEAR_RRC_OFF (3u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.RTC */
+#define IFX_ASCLIN_FLAGSCLEAR_RTC_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.RTC */
+#define IFX_ASCLIN_FLAGSCLEAR_RTC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.RTC */
+#define IFX_ASCLIN_FLAGSCLEAR_RTC_OFF (20u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.TCC */
+#define IFX_ASCLIN_FLAGSCLEAR_TCC_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.TCC */
+#define IFX_ASCLIN_FLAGSCLEAR_TCC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.TCC */
+#define IFX_ASCLIN_FLAGSCLEAR_TCC_OFF (17u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.TFLC */
+#define IFX_ASCLIN_FLAGSCLEAR_TFLC_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.TFLC */
+#define IFX_ASCLIN_FLAGSCLEAR_TFLC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.TFLC */
+#define IFX_ASCLIN_FLAGSCLEAR_TFLC_OFF (31u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.TFOC */
+#define IFX_ASCLIN_FLAGSCLEAR_TFOC_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.TFOC */
+#define IFX_ASCLIN_FLAGSCLEAR_TFOC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.TFOC */
+#define IFX_ASCLIN_FLAGSCLEAR_TFOC_OFF (30u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.THC */
+#define IFX_ASCLIN_FLAGSCLEAR_THC_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.THC */
+#define IFX_ASCLIN_FLAGSCLEAR_THC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.THC */
+#define IFX_ASCLIN_FLAGSCLEAR_THC_OFF (0u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.THRQC */
+#define IFX_ASCLIN_FLAGSCLEAR_THRQC_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.THRQC */
+#define IFX_ASCLIN_FLAGSCLEAR_THRQC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.THRQC */
+#define IFX_ASCLIN_FLAGSCLEAR_THRQC_OFF (14u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.TRC */
+#define IFX_ASCLIN_FLAGSCLEAR_TRC_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.TRC */
+#define IFX_ASCLIN_FLAGSCLEAR_TRC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.TRC */
+#define IFX_ASCLIN_FLAGSCLEAR_TRC_OFF (1u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.TRRQC */
+#define IFX_ASCLIN_FLAGSCLEAR_TRRQC_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.TRRQC */
+#define IFX_ASCLIN_FLAGSCLEAR_TRRQC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.TRRQC */
+#define IFX_ASCLIN_FLAGSCLEAR_TRRQC_OFF (15u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.TWRQC */
+#define IFX_ASCLIN_FLAGSCLEAR_TWRQC_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.TWRQC */
+#define IFX_ASCLIN_FLAGSCLEAR_TWRQC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.TWRQC */
+#define IFX_ASCLIN_FLAGSCLEAR_TWRQC_OFF (13u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSENABLE_Bits.ABE */
+#define IFX_ASCLIN_FLAGSENABLE_ABE_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.ABE */
+#define IFX_ASCLIN_FLAGSENABLE_ABE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.ABE */
+#define IFX_ASCLIN_FLAGSENABLE_ABE_OFF (23u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSENABLE_Bits.BDE */
+#define IFX_ASCLIN_FLAGSENABLE_BDE_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.BDE */
+#define IFX_ASCLIN_FLAGSENABLE_BDE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.BDE */
+#define IFX_ASCLIN_FLAGSENABLE_BDE_OFF (21u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSENABLE_Bits.CEE */
+#define IFX_ASCLIN_FLAGSENABLE_CEE_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.CEE */
+#define IFX_ASCLIN_FLAGSENABLE_CEE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.CEE */
+#define IFX_ASCLIN_FLAGSENABLE_CEE_OFF (25u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSENABLE_Bits.FEDE */
+#define IFX_ASCLIN_FLAGSENABLE_FEDE_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.FEDE */
+#define IFX_ASCLIN_FLAGSENABLE_FEDE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.FEDE */
+#define IFX_ASCLIN_FLAGSENABLE_FEDE_OFF (5u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSENABLE_Bits.FEE */
+#define IFX_ASCLIN_FLAGSENABLE_FEE_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.FEE */
+#define IFX_ASCLIN_FLAGSENABLE_FEE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.FEE */
+#define IFX_ASCLIN_FLAGSENABLE_FEE_OFF (18u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSENABLE_Bits.HTE */
+#define IFX_ASCLIN_FLAGSENABLE_HTE_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.HTE */
+#define IFX_ASCLIN_FLAGSENABLE_HTE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.HTE */
+#define IFX_ASCLIN_FLAGSENABLE_HTE_OFF (19u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSENABLE_Bits.LCE */
+#define IFX_ASCLIN_FLAGSENABLE_LCE_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.LCE */
+#define IFX_ASCLIN_FLAGSENABLE_LCE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.LCE */
+#define IFX_ASCLIN_FLAGSENABLE_LCE_OFF (24u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSENABLE_Bits.LPE */
+#define IFX_ASCLIN_FLAGSENABLE_LPE_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.LPE */
+#define IFX_ASCLIN_FLAGSENABLE_LPE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.LPE */
+#define IFX_ASCLIN_FLAGSENABLE_LPE_OFF (22u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSENABLE_Bits.PEE */
+#define IFX_ASCLIN_FLAGSENABLE_PEE_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.PEE */
+#define IFX_ASCLIN_FLAGSENABLE_PEE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.PEE */
+#define IFX_ASCLIN_FLAGSENABLE_PEE_OFF (16u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSENABLE_Bits.REDE */
+#define IFX_ASCLIN_FLAGSENABLE_REDE_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.REDE */
+#define IFX_ASCLIN_FLAGSENABLE_REDE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.REDE */
+#define IFX_ASCLIN_FLAGSENABLE_REDE_OFF (6u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSENABLE_Bits.RFLE */
+#define IFX_ASCLIN_FLAGSENABLE_RFLE_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.RFLE */
+#define IFX_ASCLIN_FLAGSENABLE_RFLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.RFLE */
+#define IFX_ASCLIN_FLAGSENABLE_RFLE_OFF (28u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSENABLE_Bits.RFOE */
+#define IFX_ASCLIN_FLAGSENABLE_RFOE_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.RFOE */
+#define IFX_ASCLIN_FLAGSENABLE_RFOE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.RFOE */
+#define IFX_ASCLIN_FLAGSENABLE_RFOE_OFF (26u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSENABLE_Bits.RFUE */
+#define IFX_ASCLIN_FLAGSENABLE_RFUE_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.RFUE */
+#define IFX_ASCLIN_FLAGSENABLE_RFUE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.RFUE */
+#define IFX_ASCLIN_FLAGSENABLE_RFUE_OFF (27u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSENABLE_Bits.RHE */
+#define IFX_ASCLIN_FLAGSENABLE_RHE_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.RHE */
+#define IFX_ASCLIN_FLAGSENABLE_RHE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.RHE */
+#define IFX_ASCLIN_FLAGSENABLE_RHE_OFF (2u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSENABLE_Bits.RRE */
+#define IFX_ASCLIN_FLAGSENABLE_RRE_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.RRE */
+#define IFX_ASCLIN_FLAGSENABLE_RRE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.RRE */
+#define IFX_ASCLIN_FLAGSENABLE_RRE_OFF (3u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSENABLE_Bits.RTE */
+#define IFX_ASCLIN_FLAGSENABLE_RTE_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.RTE */
+#define IFX_ASCLIN_FLAGSENABLE_RTE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.RTE */
+#define IFX_ASCLIN_FLAGSENABLE_RTE_OFF (20u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSENABLE_Bits.TCE */
+#define IFX_ASCLIN_FLAGSENABLE_TCE_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.TCE */
+#define IFX_ASCLIN_FLAGSENABLE_TCE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.TCE */
+#define IFX_ASCLIN_FLAGSENABLE_TCE_OFF (17u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSENABLE_Bits.TFLE */
+#define IFX_ASCLIN_FLAGSENABLE_TFLE_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.TFLE */
+#define IFX_ASCLIN_FLAGSENABLE_TFLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.TFLE */
+#define IFX_ASCLIN_FLAGSENABLE_TFLE_OFF (31u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSENABLE_Bits.TFOE */
+#define IFX_ASCLIN_FLAGSENABLE_TFOE_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.TFOE */
+#define IFX_ASCLIN_FLAGSENABLE_TFOE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.TFOE */
+#define IFX_ASCLIN_FLAGSENABLE_TFOE_OFF (30u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSENABLE_Bits.THE */
+#define IFX_ASCLIN_FLAGSENABLE_THE_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.THE */
+#define IFX_ASCLIN_FLAGSENABLE_THE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.THE */
+#define IFX_ASCLIN_FLAGSENABLE_THE_OFF (0u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSENABLE_Bits.TRE */
+#define IFX_ASCLIN_FLAGSENABLE_TRE_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.TRE */
+#define IFX_ASCLIN_FLAGSENABLE_TRE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.TRE */
+#define IFX_ASCLIN_FLAGSENABLE_TRE_OFF (1u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSSET_Bits.BDS */
+#define IFX_ASCLIN_FLAGSSET_BDS_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSSET_Bits.BDS */
+#define IFX_ASCLIN_FLAGSSET_BDS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSSET_Bits.BDS */
+#define IFX_ASCLIN_FLAGSSET_BDS_OFF (21u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSSET_Bits.CES */
+#define IFX_ASCLIN_FLAGSSET_CES_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSSET_Bits.CES */
+#define IFX_ASCLIN_FLAGSSET_CES_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSSET_Bits.CES */
+#define IFX_ASCLIN_FLAGSSET_CES_OFF (25u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSSET_Bits.FEDS */
+#define IFX_ASCLIN_FLAGSSET_FEDS_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSSET_Bits.FEDS */
+#define IFX_ASCLIN_FLAGSSET_FEDS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSSET_Bits.FEDS */
+#define IFX_ASCLIN_FLAGSSET_FEDS_OFF (5u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSSET_Bits.FES */
+#define IFX_ASCLIN_FLAGSSET_FES_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSSET_Bits.FES */
+#define IFX_ASCLIN_FLAGSSET_FES_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSSET_Bits.FES */
+#define IFX_ASCLIN_FLAGSSET_FES_OFF (18u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSSET_Bits.HTS */
+#define IFX_ASCLIN_FLAGSSET_HTS_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSSET_Bits.HTS */
+#define IFX_ASCLIN_FLAGSSET_HTS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSSET_Bits.HTS */
+#define IFX_ASCLIN_FLAGSSET_HTS_OFF (19u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSSET_Bits.LAS */
+#define IFX_ASCLIN_FLAGSSET_LAS_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSSET_Bits.LAS */
+#define IFX_ASCLIN_FLAGSSET_LAS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSSET_Bits.LAS */
+#define IFX_ASCLIN_FLAGSSET_LAS_OFF (23u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSSET_Bits.LCS */
+#define IFX_ASCLIN_FLAGSSET_LCS_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSSET_Bits.LCS */
+#define IFX_ASCLIN_FLAGSSET_LCS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSSET_Bits.LCS */
+#define IFX_ASCLIN_FLAGSSET_LCS_OFF (24u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSSET_Bits.LPS */
+#define IFX_ASCLIN_FLAGSSET_LPS_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSSET_Bits.LPS */
+#define IFX_ASCLIN_FLAGSSET_LPS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSSET_Bits.LPS */
+#define IFX_ASCLIN_FLAGSSET_LPS_OFF (22u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSSET_Bits.PES */
+#define IFX_ASCLIN_FLAGSSET_PES_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSSET_Bits.PES */
+#define IFX_ASCLIN_FLAGSSET_PES_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSSET_Bits.PES */
+#define IFX_ASCLIN_FLAGSSET_PES_OFF (16u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSSET_Bits.REDS */
+#define IFX_ASCLIN_FLAGSSET_REDS_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSSET_Bits.REDS */
+#define IFX_ASCLIN_FLAGSSET_REDS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSSET_Bits.REDS */
+#define IFX_ASCLIN_FLAGSSET_REDS_OFF (6u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSSET_Bits.RFLS */
+#define IFX_ASCLIN_FLAGSSET_RFLS_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSSET_Bits.RFLS */
+#define IFX_ASCLIN_FLAGSSET_RFLS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSSET_Bits.RFLS */
+#define IFX_ASCLIN_FLAGSSET_RFLS_OFF (28u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSSET_Bits.RFOS */
+#define IFX_ASCLIN_FLAGSSET_RFOS_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSSET_Bits.RFOS */
+#define IFX_ASCLIN_FLAGSSET_RFOS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSSET_Bits.RFOS */
+#define IFX_ASCLIN_FLAGSSET_RFOS_OFF (26u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSSET_Bits.RFUS */
+#define IFX_ASCLIN_FLAGSSET_RFUS_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSSET_Bits.RFUS */
+#define IFX_ASCLIN_FLAGSSET_RFUS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSSET_Bits.RFUS */
+#define IFX_ASCLIN_FLAGSSET_RFUS_OFF (27u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSSET_Bits.RHS */
+#define IFX_ASCLIN_FLAGSSET_RHS_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSSET_Bits.RHS */
+#define IFX_ASCLIN_FLAGSSET_RHS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSSET_Bits.RHS */
+#define IFX_ASCLIN_FLAGSSET_RHS_OFF (2u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSSET_Bits.RRS */
+#define IFX_ASCLIN_FLAGSSET_RRS_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSSET_Bits.RRS */
+#define IFX_ASCLIN_FLAGSSET_RRS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSSET_Bits.RRS */
+#define IFX_ASCLIN_FLAGSSET_RRS_OFF (3u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSSET_Bits.RTS */
+#define IFX_ASCLIN_FLAGSSET_RTS_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSSET_Bits.RTS */
+#define IFX_ASCLIN_FLAGSSET_RTS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSSET_Bits.RTS */
+#define IFX_ASCLIN_FLAGSSET_RTS_OFF (20u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSSET_Bits.TCS */
+#define IFX_ASCLIN_FLAGSSET_TCS_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSSET_Bits.TCS */
+#define IFX_ASCLIN_FLAGSSET_TCS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSSET_Bits.TCS */
+#define IFX_ASCLIN_FLAGSSET_TCS_OFF (17u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSSET_Bits.TFLS */
+#define IFX_ASCLIN_FLAGSSET_TFLS_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSSET_Bits.TFLS */
+#define IFX_ASCLIN_FLAGSSET_TFLS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSSET_Bits.TFLS */
+#define IFX_ASCLIN_FLAGSSET_TFLS_OFF (31u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSSET_Bits.TFOS */
+#define IFX_ASCLIN_FLAGSSET_TFOS_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSSET_Bits.TFOS */
+#define IFX_ASCLIN_FLAGSSET_TFOS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSSET_Bits.TFOS */
+#define IFX_ASCLIN_FLAGSSET_TFOS_OFF (30u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSSET_Bits.THRQS */
+#define IFX_ASCLIN_FLAGSSET_THRQS_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSSET_Bits.THRQS */
+#define IFX_ASCLIN_FLAGSSET_THRQS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSSET_Bits.THRQS */
+#define IFX_ASCLIN_FLAGSSET_THRQS_OFF (14u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSSET_Bits.THS */
+#define IFX_ASCLIN_FLAGSSET_THS_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSSET_Bits.THS */
+#define IFX_ASCLIN_FLAGSSET_THS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSSET_Bits.THS */
+#define IFX_ASCLIN_FLAGSSET_THS_OFF (0u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSSET_Bits.TRRQS */
+#define IFX_ASCLIN_FLAGSSET_TRRQS_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSSET_Bits.TRRQS */
+#define IFX_ASCLIN_FLAGSSET_TRRQS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSSET_Bits.TRRQS */
+#define IFX_ASCLIN_FLAGSSET_TRRQS_OFF (15u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSSET_Bits.TRS */
+#define IFX_ASCLIN_FLAGSSET_TRS_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSSET_Bits.TRS */
+#define IFX_ASCLIN_FLAGSSET_TRS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSSET_Bits.TRS */
+#define IFX_ASCLIN_FLAGSSET_TRS_OFF (1u)
+
+/** \brief Length for Ifx_ASCLIN_FLAGSSET_Bits.TWRQS */
+#define IFX_ASCLIN_FLAGSSET_TWRQS_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FLAGSSET_Bits.TWRQS */
+#define IFX_ASCLIN_FLAGSSET_TWRQS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FLAGSSET_Bits.TWRQS */
+#define IFX_ASCLIN_FLAGSSET_TWRQS_OFF (13u)
+
+/** \brief Length for Ifx_ASCLIN_FRAMECON_Bits.CEN */
+#define IFX_ASCLIN_FRAMECON_CEN_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FRAMECON_Bits.CEN */
+#define IFX_ASCLIN_FRAMECON_CEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FRAMECON_Bits.CEN */
+#define IFX_ASCLIN_FRAMECON_CEN_OFF (29u)
+
+/** \brief Length for Ifx_ASCLIN_FRAMECON_Bits.IDLE */
+#define IFX_ASCLIN_FRAMECON_IDLE_LEN (3u)
+
+/** \brief Mask for Ifx_ASCLIN_FRAMECON_Bits.IDLE */
+#define IFX_ASCLIN_FRAMECON_IDLE_MSK (0x7u)
+
+/** \brief Offset for Ifx_ASCLIN_FRAMECON_Bits.IDLE */
+#define IFX_ASCLIN_FRAMECON_IDLE_OFF (6u)
+
+/** \brief Length for Ifx_ASCLIN_FRAMECON_Bits.LEAD */
+#define IFX_ASCLIN_FRAMECON_LEAD_LEN (3u)
+
+/** \brief Mask for Ifx_ASCLIN_FRAMECON_Bits.LEAD */
+#define IFX_ASCLIN_FRAMECON_LEAD_MSK (0x7u)
+
+/** \brief Offset for Ifx_ASCLIN_FRAMECON_Bits.LEAD */
+#define IFX_ASCLIN_FRAMECON_LEAD_OFF (12u)
+
+/** \brief Length for Ifx_ASCLIN_FRAMECON_Bits.MODE */
+#define IFX_ASCLIN_FRAMECON_MODE_LEN (2u)
+
+/** \brief Mask for Ifx_ASCLIN_FRAMECON_Bits.MODE */
+#define IFX_ASCLIN_FRAMECON_MODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_ASCLIN_FRAMECON_Bits.MODE */
+#define IFX_ASCLIN_FRAMECON_MODE_OFF (16u)
+
+/** \brief Length for Ifx_ASCLIN_FRAMECON_Bits.MSB */
+#define IFX_ASCLIN_FRAMECON_MSB_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FRAMECON_Bits.MSB */
+#define IFX_ASCLIN_FRAMECON_MSB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FRAMECON_Bits.MSB */
+#define IFX_ASCLIN_FRAMECON_MSB_OFF (28u)
+
+/** \brief Length for Ifx_ASCLIN_FRAMECON_Bits.ODD */
+#define IFX_ASCLIN_FRAMECON_ODD_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FRAMECON_Bits.ODD */
+#define IFX_ASCLIN_FRAMECON_ODD_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FRAMECON_Bits.ODD */
+#define IFX_ASCLIN_FRAMECON_ODD_OFF (31u)
+
+/** \brief Length for Ifx_ASCLIN_FRAMECON_Bits.PEN */
+#define IFX_ASCLIN_FRAMECON_PEN_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_FRAMECON_Bits.PEN */
+#define IFX_ASCLIN_FRAMECON_PEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_FRAMECON_Bits.PEN */
+#define IFX_ASCLIN_FRAMECON_PEN_OFF (30u)
+
+/** \brief Length for Ifx_ASCLIN_FRAMECON_Bits.STOP */
+#define IFX_ASCLIN_FRAMECON_STOP_LEN (3u)
+
+/** \brief Mask for Ifx_ASCLIN_FRAMECON_Bits.STOP */
+#define IFX_ASCLIN_FRAMECON_STOP_MSK (0x7u)
+
+/** \brief Offset for Ifx_ASCLIN_FRAMECON_Bits.STOP */
+#define IFX_ASCLIN_FRAMECON_STOP_OFF (9u)
+
+/** \brief Length for Ifx_ASCLIN_ID_Bits.MODNUMBER */
+#define IFX_ASCLIN_ID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_ASCLIN_ID_Bits.MODNUMBER */
+#define IFX_ASCLIN_ID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_ASCLIN_ID_Bits.MODNUMBER */
+#define IFX_ASCLIN_ID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_ASCLIN_ID_Bits.MODREV */
+#define IFX_ASCLIN_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_ASCLIN_ID_Bits.MODREV */
+#define IFX_ASCLIN_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_ASCLIN_ID_Bits.MODREV */
+#define IFX_ASCLIN_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_ASCLIN_ID_Bits.MODTYPE */
+#define IFX_ASCLIN_ID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_ASCLIN_ID_Bits.MODTYPE */
+#define IFX_ASCLIN_ID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_ASCLIN_ID_Bits.MODTYPE */
+#define IFX_ASCLIN_ID_MODTYPE_OFF (8u)
+
+/** \brief Length for Ifx_ASCLIN_IOCR_Bits.ALTI */
+#define IFX_ASCLIN_IOCR_ALTI_LEN (3u)
+
+/** \brief Mask for Ifx_ASCLIN_IOCR_Bits.ALTI */
+#define IFX_ASCLIN_IOCR_ALTI_MSK (0x7u)
+
+/** \brief Offset for Ifx_ASCLIN_IOCR_Bits.ALTI */
+#define IFX_ASCLIN_IOCR_ALTI_OFF (0u)
+
+/** \brief Length for Ifx_ASCLIN_IOCR_Bits.CPOL */
+#define IFX_ASCLIN_IOCR_CPOL_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_IOCR_Bits.CPOL */
+#define IFX_ASCLIN_IOCR_CPOL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_IOCR_Bits.CPOL */
+#define IFX_ASCLIN_IOCR_CPOL_OFF (26u)
+
+/** \brief Length for Ifx_ASCLIN_IOCR_Bits.CTS */
+#define IFX_ASCLIN_IOCR_CTS_LEN (2u)
+
+/** \brief Mask for Ifx_ASCLIN_IOCR_Bits.CTS */
+#define IFX_ASCLIN_IOCR_CTS_MSK (0x3u)
+
+/** \brief Offset for Ifx_ASCLIN_IOCR_Bits.CTS */
+#define IFX_ASCLIN_IOCR_CTS_OFF (16u)
+
+/** \brief Length for Ifx_ASCLIN_IOCR_Bits.CTSEN */
+#define IFX_ASCLIN_IOCR_CTSEN_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_IOCR_Bits.CTSEN */
+#define IFX_ASCLIN_IOCR_CTSEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_IOCR_Bits.CTSEN */
+#define IFX_ASCLIN_IOCR_CTSEN_OFF (29u)
+
+/** \brief Length for Ifx_ASCLIN_IOCR_Bits.DEPTH */
+#define IFX_ASCLIN_IOCR_DEPTH_LEN (6u)
+
+/** \brief Mask for Ifx_ASCLIN_IOCR_Bits.DEPTH */
+#define IFX_ASCLIN_IOCR_DEPTH_MSK (0x3fu)
+
+/** \brief Offset for Ifx_ASCLIN_IOCR_Bits.DEPTH */
+#define IFX_ASCLIN_IOCR_DEPTH_OFF (4u)
+
+/** \brief Length for Ifx_ASCLIN_IOCR_Bits.LB */
+#define IFX_ASCLIN_IOCR_LB_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_IOCR_Bits.LB */
+#define IFX_ASCLIN_IOCR_LB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_IOCR_Bits.LB */
+#define IFX_ASCLIN_IOCR_LB_OFF (28u)
+
+/** \brief Length for Ifx_ASCLIN_IOCR_Bits.RCPOL */
+#define IFX_ASCLIN_IOCR_RCPOL_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_IOCR_Bits.RCPOL */
+#define IFX_ASCLIN_IOCR_RCPOL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_IOCR_Bits.RCPOL */
+#define IFX_ASCLIN_IOCR_RCPOL_OFF (25u)
+
+/** \brief Length for Ifx_ASCLIN_IOCR_Bits.RXM */
+#define IFX_ASCLIN_IOCR_RXM_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_IOCR_Bits.RXM */
+#define IFX_ASCLIN_IOCR_RXM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_IOCR_Bits.RXM */
+#define IFX_ASCLIN_IOCR_RXM_OFF (30u)
+
+/** \brief Length for Ifx_ASCLIN_IOCR_Bits.SPOL */
+#define IFX_ASCLIN_IOCR_SPOL_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_IOCR_Bits.SPOL */
+#define IFX_ASCLIN_IOCR_SPOL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_IOCR_Bits.SPOL */
+#define IFX_ASCLIN_IOCR_SPOL_OFF (27u)
+
+/** \brief Length for Ifx_ASCLIN_IOCR_Bits.TXM */
+#define IFX_ASCLIN_IOCR_TXM_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_IOCR_Bits.TXM */
+#define IFX_ASCLIN_IOCR_TXM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_IOCR_Bits.TXM */
+#define IFX_ASCLIN_IOCR_TXM_OFF (31u)
+
+/** \brief Length for Ifx_ASCLIN_KRST0_Bits.RST */
+#define IFX_ASCLIN_KRST0_RST_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_KRST0_Bits.RST */
+#define IFX_ASCLIN_KRST0_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_KRST0_Bits.RST */
+#define IFX_ASCLIN_KRST0_RST_OFF (0u)
+
+/** \brief Length for Ifx_ASCLIN_KRST0_Bits.RSTSTAT */
+#define IFX_ASCLIN_KRST0_RSTSTAT_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_KRST0_Bits.RSTSTAT */
+#define IFX_ASCLIN_KRST0_RSTSTAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_KRST0_Bits.RSTSTAT */
+#define IFX_ASCLIN_KRST0_RSTSTAT_OFF (1u)
+
+/** \brief Length for Ifx_ASCLIN_KRST1_Bits.RST */
+#define IFX_ASCLIN_KRST1_RST_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_KRST1_Bits.RST */
+#define IFX_ASCLIN_KRST1_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_KRST1_Bits.RST */
+#define IFX_ASCLIN_KRST1_RST_OFF (0u)
+
+/** \brief Length for Ifx_ASCLIN_KRSTCLR_Bits.CLR */
+#define IFX_ASCLIN_KRSTCLR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_KRSTCLR_Bits.CLR */
+#define IFX_ASCLIN_KRSTCLR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_KRSTCLR_Bits.CLR */
+#define IFX_ASCLIN_KRSTCLR_CLR_OFF (0u)
+
+/** \brief Length for Ifx_ASCLIN_LIN_BTIMER_Bits.BREAK */
+#define IFX_ASCLIN_LIN_BTIMER_BREAK_LEN (6u)
+
+/** \brief Mask for Ifx_ASCLIN_LIN_BTIMER_Bits.BREAK */
+#define IFX_ASCLIN_LIN_BTIMER_BREAK_MSK (0x3fu)
+
+/** \brief Offset for Ifx_ASCLIN_LIN_BTIMER_Bits.BREAK */
+#define IFX_ASCLIN_LIN_BTIMER_BREAK_OFF (0u)
+
+/** \brief Length for Ifx_ASCLIN_LIN_CON_Bits.ABD */
+#define IFX_ASCLIN_LIN_CON_ABD_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_LIN_CON_Bits.ABD */
+#define IFX_ASCLIN_LIN_CON_ABD_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_LIN_CON_Bits.ABD */
+#define IFX_ASCLIN_LIN_CON_ABD_OFF (27u)
+
+/** \brief Length for Ifx_ASCLIN_LIN_CON_Bits.CSEN */
+#define IFX_ASCLIN_LIN_CON_CSEN_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_LIN_CON_Bits.CSEN */
+#define IFX_ASCLIN_LIN_CON_CSEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_LIN_CON_Bits.CSEN */
+#define IFX_ASCLIN_LIN_CON_CSEN_OFF (25u)
+
+/** \brief Length for Ifx_ASCLIN_LIN_CON_Bits.CSI */
+#define IFX_ASCLIN_LIN_CON_CSI_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_LIN_CON_Bits.CSI */
+#define IFX_ASCLIN_LIN_CON_CSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_LIN_CON_Bits.CSI */
+#define IFX_ASCLIN_LIN_CON_CSI_OFF (23u)
+
+/** \brief Length for Ifx_ASCLIN_LIN_CON_Bits.MS */
+#define IFX_ASCLIN_LIN_CON_MS_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_LIN_CON_Bits.MS */
+#define IFX_ASCLIN_LIN_CON_MS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_LIN_CON_Bits.MS */
+#define IFX_ASCLIN_LIN_CON_MS_OFF (26u)
+
+/** \brief Length for Ifx_ASCLIN_LIN_HTIMER_Bits.HEADER */
+#define IFX_ASCLIN_LIN_HTIMER_HEADER_LEN (8u)
+
+/** \brief Mask for Ifx_ASCLIN_LIN_HTIMER_Bits.HEADER */
+#define IFX_ASCLIN_LIN_HTIMER_HEADER_MSK (0xffu)
+
+/** \brief Offset for Ifx_ASCLIN_LIN_HTIMER_Bits.HEADER */
+#define IFX_ASCLIN_LIN_HTIMER_HEADER_OFF (0u)
+
+/** \brief Length for Ifx_ASCLIN_OCS_Bits.SUS */
+#define IFX_ASCLIN_OCS_SUS_LEN (4u)
+
+/** \brief Mask for Ifx_ASCLIN_OCS_Bits.SUS */
+#define IFX_ASCLIN_OCS_SUS_MSK (0xfu)
+
+/** \brief Offset for Ifx_ASCLIN_OCS_Bits.SUS */
+#define IFX_ASCLIN_OCS_SUS_OFF (24u)
+
+/** \brief Length for Ifx_ASCLIN_OCS_Bits.SUS_P */
+#define IFX_ASCLIN_OCS_SUS_P_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_OCS_Bits.SUS_P */
+#define IFX_ASCLIN_OCS_SUS_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_OCS_Bits.SUS_P */
+#define IFX_ASCLIN_OCS_SUS_P_OFF (28u)
+
+/** \brief Length for Ifx_ASCLIN_OCS_Bits.SUSSTA */
+#define IFX_ASCLIN_OCS_SUSSTA_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_OCS_Bits.SUSSTA */
+#define IFX_ASCLIN_OCS_SUSSTA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_OCS_Bits.SUSSTA */
+#define IFX_ASCLIN_OCS_SUSSTA_OFF (29u)
+
+/** \brief Length for Ifx_ASCLIN_RXDATA_Bits.DATA */
+#define IFX_ASCLIN_RXDATA_DATA_LEN (32u)
+
+/** \brief Mask for Ifx_ASCLIN_RXDATA_Bits.DATA */
+#define IFX_ASCLIN_RXDATA_DATA_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ASCLIN_RXDATA_Bits.DATA */
+#define IFX_ASCLIN_RXDATA_DATA_OFF (0u)
+
+/** \brief Length for Ifx_ASCLIN_RXDATAD_Bits.DATA */
+#define IFX_ASCLIN_RXDATAD_DATA_LEN (32u)
+
+/** \brief Mask for Ifx_ASCLIN_RXDATAD_Bits.DATA */
+#define IFX_ASCLIN_RXDATAD_DATA_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ASCLIN_RXDATAD_Bits.DATA */
+#define IFX_ASCLIN_RXDATAD_DATA_OFF (0u)
+
+/** \brief Length for Ifx_ASCLIN_RXFIFOCON_Bits.BUF */
+#define IFX_ASCLIN_RXFIFOCON_BUF_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_RXFIFOCON_Bits.BUF */
+#define IFX_ASCLIN_RXFIFOCON_BUF_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_RXFIFOCON_Bits.BUF */
+#define IFX_ASCLIN_RXFIFOCON_BUF_OFF (31u)
+
+/** \brief Length for Ifx_ASCLIN_RXFIFOCON_Bits.ENI */
+#define IFX_ASCLIN_RXFIFOCON_ENI_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_RXFIFOCON_Bits.ENI */
+#define IFX_ASCLIN_RXFIFOCON_ENI_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_RXFIFOCON_Bits.ENI */
+#define IFX_ASCLIN_RXFIFOCON_ENI_OFF (1u)
+
+/** \brief Length for Ifx_ASCLIN_RXFIFOCON_Bits.FILL */
+#define IFX_ASCLIN_RXFIFOCON_FILL_LEN (5u)
+
+/** \brief Mask for Ifx_ASCLIN_RXFIFOCON_Bits.FILL */
+#define IFX_ASCLIN_RXFIFOCON_FILL_MSK (0x1fu)
+
+/** \brief Offset for Ifx_ASCLIN_RXFIFOCON_Bits.FILL */
+#define IFX_ASCLIN_RXFIFOCON_FILL_OFF (16u)
+
+/** \brief Length for Ifx_ASCLIN_RXFIFOCON_Bits.FLUSH */
+#define IFX_ASCLIN_RXFIFOCON_FLUSH_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_RXFIFOCON_Bits.FLUSH */
+#define IFX_ASCLIN_RXFIFOCON_FLUSH_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_RXFIFOCON_Bits.FLUSH */
+#define IFX_ASCLIN_RXFIFOCON_FLUSH_OFF (0u)
+
+/** \brief Length for Ifx_ASCLIN_RXFIFOCON_Bits.INTLEVEL */
+#define IFX_ASCLIN_RXFIFOCON_INTLEVEL_LEN (4u)
+
+/** \brief Mask for Ifx_ASCLIN_RXFIFOCON_Bits.INTLEVEL */
+#define IFX_ASCLIN_RXFIFOCON_INTLEVEL_MSK (0xfu)
+
+/** \brief Offset for Ifx_ASCLIN_RXFIFOCON_Bits.INTLEVEL */
+#define IFX_ASCLIN_RXFIFOCON_INTLEVEL_OFF (8u)
+
+/** \brief Length for Ifx_ASCLIN_RXFIFOCON_Bits.OUTW */
+#define IFX_ASCLIN_RXFIFOCON_OUTW_LEN (2u)
+
+/** \brief Mask for Ifx_ASCLIN_RXFIFOCON_Bits.OUTW */
+#define IFX_ASCLIN_RXFIFOCON_OUTW_MSK (0x3u)
+
+/** \brief Offset for Ifx_ASCLIN_RXFIFOCON_Bits.OUTW */
+#define IFX_ASCLIN_RXFIFOCON_OUTW_OFF (6u)
+
+/** \brief Length for Ifx_ASCLIN_TXDATA_Bits.DATA */
+#define IFX_ASCLIN_TXDATA_DATA_LEN (32u)
+
+/** \brief Mask for Ifx_ASCLIN_TXDATA_Bits.DATA */
+#define IFX_ASCLIN_TXDATA_DATA_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ASCLIN_TXDATA_Bits.DATA */
+#define IFX_ASCLIN_TXDATA_DATA_OFF (0u)
+
+/** \brief Length for Ifx_ASCLIN_TXFIFOCON_Bits.ENO */
+#define IFX_ASCLIN_TXFIFOCON_ENO_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_TXFIFOCON_Bits.ENO */
+#define IFX_ASCLIN_TXFIFOCON_ENO_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_TXFIFOCON_Bits.ENO */
+#define IFX_ASCLIN_TXFIFOCON_ENO_OFF (1u)
+
+/** \brief Length for Ifx_ASCLIN_TXFIFOCON_Bits.FILL */
+#define IFX_ASCLIN_TXFIFOCON_FILL_LEN (5u)
+
+/** \brief Mask for Ifx_ASCLIN_TXFIFOCON_Bits.FILL */
+#define IFX_ASCLIN_TXFIFOCON_FILL_MSK (0x1fu)
+
+/** \brief Offset for Ifx_ASCLIN_TXFIFOCON_Bits.FILL */
+#define IFX_ASCLIN_TXFIFOCON_FILL_OFF (16u)
+
+/** \brief Length for Ifx_ASCLIN_TXFIFOCON_Bits.FLUSH */
+#define IFX_ASCLIN_TXFIFOCON_FLUSH_LEN (1u)
+
+/** \brief Mask for Ifx_ASCLIN_TXFIFOCON_Bits.FLUSH */
+#define IFX_ASCLIN_TXFIFOCON_FLUSH_MSK (0x1u)
+
+/** \brief Offset for Ifx_ASCLIN_TXFIFOCON_Bits.FLUSH */
+#define IFX_ASCLIN_TXFIFOCON_FLUSH_OFF (0u)
+
+/** \brief Length for Ifx_ASCLIN_TXFIFOCON_Bits.INTLEVEL */
+#define IFX_ASCLIN_TXFIFOCON_INTLEVEL_LEN (4u)
+
+/** \brief Mask for Ifx_ASCLIN_TXFIFOCON_Bits.INTLEVEL */
+#define IFX_ASCLIN_TXFIFOCON_INTLEVEL_MSK (0xfu)
+
+/** \brief Offset for Ifx_ASCLIN_TXFIFOCON_Bits.INTLEVEL */
+#define IFX_ASCLIN_TXFIFOCON_INTLEVEL_OFF (8u)
+
+/** \brief Length for Ifx_ASCLIN_TXFIFOCON_Bits.INW */
+#define IFX_ASCLIN_TXFIFOCON_INW_LEN (2u)
+
+/** \brief Mask for Ifx_ASCLIN_TXFIFOCON_Bits.INW */
+#define IFX_ASCLIN_TXFIFOCON_INW_MSK (0x3u)
+
+/** \brief Offset for Ifx_ASCLIN_TXFIFOCON_Bits.INW */
+#define IFX_ASCLIN_TXFIFOCON_INW_OFF (6u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXASCLIN_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxAsclin_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxAsclin_reg.h
new file mode 100644
index 0000000..14bc76a
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxAsclin_reg.h
@@ -0,0 +1,468 @@
+/**
+ * \file IfxAsclin_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Asclin_Cfg Asclin address
+ * \ingroup IfxLld_Asclin
+ *
+ * \defgroup IfxLld_Asclin_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Asclin_Cfg
+ *
+ * \defgroup IfxLld_Asclin_Cfg_Asclin0 2-ASCLIN0
+ * \ingroup IfxLld_Asclin_Cfg
+ *
+ * \defgroup IfxLld_Asclin_Cfg_Asclin1 2-ASCLIN1
+ * \ingroup IfxLld_Asclin_Cfg
+ *
+ * \defgroup IfxLld_Asclin_Cfg_Asclin2 2-ASCLIN2
+ * \ingroup IfxLld_Asclin_Cfg
+ *
+ * \defgroup IfxLld_Asclin_Cfg_Asclin3 2-ASCLIN3
+ * \ingroup IfxLld_Asclin_Cfg
+ *
+ */
+#ifndef IFXASCLIN_REG_H
+#define IFXASCLIN_REG_H 1
+/******************************************************************************/
+#include "IfxAsclin_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Asclin_Cfg_BaseAddress
+ * \{ */
+
+/** \brief ASCLIN object */
+#define MODULE_ASCLIN0 /*lint --e(923)*/ (*(Ifx_ASCLIN*)0xF0000600u)
+
+/** \brief ASCLIN object */
+#define MODULE_ASCLIN1 /*lint --e(923)*/ (*(Ifx_ASCLIN*)0xF0000700u)
+
+/** \brief ASCLIN object */
+#define MODULE_ASCLIN2 /*lint --e(923)*/ (*(Ifx_ASCLIN*)0xF0000800u)
+
+/** \brief ASCLIN object */
+#define MODULE_ASCLIN3 /*lint --e(923)*/ (*(Ifx_ASCLIN*)0xF0000900u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Asclin_Cfg_Asclin0
+ * \{ */
+
+/** \brief FC, Access Enable Register 0 */
+#define ASCLIN0_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN0*)0xF00006FCu)
+
+/** \brief F8, Access Enable Register 1 */
+#define ASCLIN0_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN1*)0xF00006F8u)
+
+/** \brief 14, Bit Configuration Register */
+#define ASCLIN0_BITCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BITCON*)0xF0000614u)
+
+/** \brief 24, Baud Rate Detection Register */
+#define ASCLIN0_BRD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRD*)0xF0000624u)
+
+/** \brief 20, Baud Rate Generation Register */
+#define ASCLIN0_BRG /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRG*)0xF0000620u)
+
+/** \brief 0, Clock Control Register */
+#define ASCLIN0_CLC /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CLC*)0xF0000600u)
+
+/** \brief 4C, Clock Selection Register */
+#define ASCLIN0_CSR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CSR*)0xF000064Cu)
+
+/** \brief 1C, Data Configuration Register */
+#define ASCLIN0_DATCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_DATCON*)0xF000061Cu)
+
+/** \brief 34, Flags Register */
+#define ASCLIN0_FLAGS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGS*)0xF0000634u)
+
+/** \brief 3C, Flags Clear Register */
+#define ASCLIN0_FLAGSCLEAR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSCLEAR*)0xF000063Cu)
+
+/** \brief 40, Flags Enable Register */
+#define ASCLIN0_FLAGSENABLE /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSENABLE*)0xF0000640u)
+
+/** \brief 38, Flags Set Register */
+#define ASCLIN0_FLAGSSET /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSSET*)0xF0000638u)
+
+/** \brief 18, Frame Control Register */
+#define ASCLIN0_FRAMECON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FRAMECON*)0xF0000618u)
+
+/** \brief 8, Module Identification Register */
+#define ASCLIN0_ID /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ID*)0xF0000608u)
+
+/** \brief 4, Input and Output Control Register */
+#define ASCLIN0_IOCR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_IOCR*)0xF0000604u)
+
+/** \brief F4, Kernel Reset Register 0 */
+#define ASCLIN0_KRST0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST0*)0xF00006F4u)
+
+/** \brief F0, Kernel Reset Register 1 */
+#define ASCLIN0_KRST1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST1*)0xF00006F0u)
+
+/** \brief EC, Kernel Reset Status Clear Register */
+#define ASCLIN0_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRSTCLR*)0xF00006ECu)
+
+/** \brief 2C, LIN Break Timer Register */
+#define ASCLIN0_LIN_BTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_BTIMER*)0xF000062Cu)
+
+/** Alias (User Manual Name) for ASCLIN0_LIN_BTIMER.
+* To use register names with standard convension, please use ASCLIN0_LIN_BTIMER.
+*/
+#define ASCLIN0_LINBTIMER (ASCLIN0_LIN_BTIMER)
+
+/** \brief 28, LIN Control Register */
+#define ASCLIN0_LIN_CON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_CON*)0xF0000628u)
+
+/** Alias (User Manual Name) for ASCLIN0_LIN_CON.
+* To use register names with standard convension, please use ASCLIN0_LIN_CON.
+*/
+#define ASCLIN0_LINCON (ASCLIN0_LIN_CON)
+
+/** \brief 30, LIN Header Timer Register */
+#define ASCLIN0_LIN_HTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_HTIMER*)0xF0000630u)
+
+/** Alias (User Manual Name) for ASCLIN0_LIN_HTIMER.
+* To use register names with standard convension, please use ASCLIN0_LIN_HTIMER.
+*/
+#define ASCLIN0_LINHTIMER (ASCLIN0_LIN_HTIMER)
+
+/** \brief E8, OCDS Control and Status */
+#define ASCLIN0_OCS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_OCS*)0xF00006E8u)
+
+/** \brief 48, Receive Data Register */
+#define ASCLIN0_RXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATA*)0xF0000648u)
+
+/** \brief 50, Receive Data Debug Register */
+#define ASCLIN0_RXDATAD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATAD*)0xF0000650u)
+
+/** \brief 10, RX FIFO Configuration Register */
+#define ASCLIN0_RXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXFIFOCON*)0xF0000610u)
+
+/** \brief 44, Transmit Data Register */
+#define ASCLIN0_TXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXDATA*)0xF0000644u)
+
+/** \brief C, TX FIFO Configuration Register */
+#define ASCLIN0_TXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXFIFOCON*)0xF000060Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Asclin_Cfg_Asclin1
+ * \{ */
+
+/** \brief FC, Access Enable Register 0 */
+#define ASCLIN1_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN0*)0xF00007FCu)
+
+/** \brief F8, Access Enable Register 1 */
+#define ASCLIN1_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN1*)0xF00007F8u)
+
+/** \brief 14, Bit Configuration Register */
+#define ASCLIN1_BITCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BITCON*)0xF0000714u)
+
+/** \brief 24, Baud Rate Detection Register */
+#define ASCLIN1_BRD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRD*)0xF0000724u)
+
+/** \brief 20, Baud Rate Generation Register */
+#define ASCLIN1_BRG /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRG*)0xF0000720u)
+
+/** \brief 0, Clock Control Register */
+#define ASCLIN1_CLC /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CLC*)0xF0000700u)
+
+/** \brief 4C, Clock Selection Register */
+#define ASCLIN1_CSR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CSR*)0xF000074Cu)
+
+/** \brief 1C, Data Configuration Register */
+#define ASCLIN1_DATCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_DATCON*)0xF000071Cu)
+
+/** \brief 34, Flags Register */
+#define ASCLIN1_FLAGS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGS*)0xF0000734u)
+
+/** \brief 3C, Flags Clear Register */
+#define ASCLIN1_FLAGSCLEAR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSCLEAR*)0xF000073Cu)
+
+/** \brief 40, Flags Enable Register */
+#define ASCLIN1_FLAGSENABLE /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSENABLE*)0xF0000740u)
+
+/** \brief 38, Flags Set Register */
+#define ASCLIN1_FLAGSSET /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSSET*)0xF0000738u)
+
+/** \brief 18, Frame Control Register */
+#define ASCLIN1_FRAMECON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FRAMECON*)0xF0000718u)
+
+/** \brief 8, Module Identification Register */
+#define ASCLIN1_ID /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ID*)0xF0000708u)
+
+/** \brief 4, Input and Output Control Register */
+#define ASCLIN1_IOCR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_IOCR*)0xF0000704u)
+
+/** \brief F4, Kernel Reset Register 0 */
+#define ASCLIN1_KRST0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST0*)0xF00007F4u)
+
+/** \brief F0, Kernel Reset Register 1 */
+#define ASCLIN1_KRST1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST1*)0xF00007F0u)
+
+/** \brief EC, Kernel Reset Status Clear Register */
+#define ASCLIN1_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRSTCLR*)0xF00007ECu)
+
+/** \brief 2C, LIN Break Timer Register */
+#define ASCLIN1_LIN_BTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_BTIMER*)0xF000072Cu)
+
+/** Alias (User Manual Name) for ASCLIN1_LIN_BTIMER.
+* To use register names with standard convension, please use ASCLIN1_LIN_BTIMER.
+*/
+#define ASCLIN1_LINBTIMER (ASCLIN1_LIN_BTIMER)
+
+/** \brief 28, LIN Control Register */
+#define ASCLIN1_LIN_CON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_CON*)0xF0000728u)
+
+/** Alias (User Manual Name) for ASCLIN1_LIN_CON.
+* To use register names with standard convension, please use ASCLIN1_LIN_CON.
+*/
+#define ASCLIN1_LINCON (ASCLIN1_LIN_CON)
+
+/** \brief 30, LIN Header Timer Register */
+#define ASCLIN1_LIN_HTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_HTIMER*)0xF0000730u)
+
+/** Alias (User Manual Name) for ASCLIN1_LIN_HTIMER.
+* To use register names with standard convension, please use ASCLIN1_LIN_HTIMER.
+*/
+#define ASCLIN1_LINHTIMER (ASCLIN1_LIN_HTIMER)
+
+/** \brief E8, OCDS Control and Status */
+#define ASCLIN1_OCS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_OCS*)0xF00007E8u)
+
+/** \brief 48, Receive Data Register */
+#define ASCLIN1_RXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATA*)0xF0000748u)
+
+/** \brief 50, Receive Data Debug Register */
+#define ASCLIN1_RXDATAD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATAD*)0xF0000750u)
+
+/** \brief 10, RX FIFO Configuration Register */
+#define ASCLIN1_RXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXFIFOCON*)0xF0000710u)
+
+/** \brief 44, Transmit Data Register */
+#define ASCLIN1_TXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXDATA*)0xF0000744u)
+
+/** \brief C, TX FIFO Configuration Register */
+#define ASCLIN1_TXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXFIFOCON*)0xF000070Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Asclin_Cfg_Asclin2
+ * \{ */
+
+/** \brief FC, Access Enable Register 0 */
+#define ASCLIN2_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN0*)0xF00008FCu)
+
+/** \brief F8, Access Enable Register 1 */
+#define ASCLIN2_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN1*)0xF00008F8u)
+
+/** \brief 14, Bit Configuration Register */
+#define ASCLIN2_BITCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BITCON*)0xF0000814u)
+
+/** \brief 24, Baud Rate Detection Register */
+#define ASCLIN2_BRD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRD*)0xF0000824u)
+
+/** \brief 20, Baud Rate Generation Register */
+#define ASCLIN2_BRG /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRG*)0xF0000820u)
+
+/** \brief 0, Clock Control Register */
+#define ASCLIN2_CLC /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CLC*)0xF0000800u)
+
+/** \brief 4C, Clock Selection Register */
+#define ASCLIN2_CSR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CSR*)0xF000084Cu)
+
+/** \brief 1C, Data Configuration Register */
+#define ASCLIN2_DATCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_DATCON*)0xF000081Cu)
+
+/** \brief 34, Flags Register */
+#define ASCLIN2_FLAGS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGS*)0xF0000834u)
+
+/** \brief 3C, Flags Clear Register */
+#define ASCLIN2_FLAGSCLEAR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSCLEAR*)0xF000083Cu)
+
+/** \brief 40, Flags Enable Register */
+#define ASCLIN2_FLAGSENABLE /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSENABLE*)0xF0000840u)
+
+/** \brief 38, Flags Set Register */
+#define ASCLIN2_FLAGSSET /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSSET*)0xF0000838u)
+
+/** \brief 18, Frame Control Register */
+#define ASCLIN2_FRAMECON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FRAMECON*)0xF0000818u)
+
+/** \brief 8, Module Identification Register */
+#define ASCLIN2_ID /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ID*)0xF0000808u)
+
+/** \brief 4, Input and Output Control Register */
+#define ASCLIN2_IOCR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_IOCR*)0xF0000804u)
+
+/** \brief F4, Kernel Reset Register 0 */
+#define ASCLIN2_KRST0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST0*)0xF00008F4u)
+
+/** \brief F0, Kernel Reset Register 1 */
+#define ASCLIN2_KRST1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST1*)0xF00008F0u)
+
+/** \brief EC, Kernel Reset Status Clear Register */
+#define ASCLIN2_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRSTCLR*)0xF00008ECu)
+
+/** \brief 2C, LIN Break Timer Register */
+#define ASCLIN2_LIN_BTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_BTIMER*)0xF000082Cu)
+
+/** Alias (User Manual Name) for ASCLIN2_LIN_BTIMER.
+* To use register names with standard convension, please use ASCLIN2_LIN_BTIMER.
+*/
+#define ASCLIN2_LINBTIMER (ASCLIN2_LIN_BTIMER)
+
+/** \brief 28, LIN Control Register */
+#define ASCLIN2_LIN_CON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_CON*)0xF0000828u)
+
+/** Alias (User Manual Name) for ASCLIN2_LIN_CON.
+* To use register names with standard convension, please use ASCLIN2_LIN_CON.
+*/
+#define ASCLIN2_LINCON (ASCLIN2_LIN_CON)
+
+/** \brief 30, LIN Header Timer Register */
+#define ASCLIN2_LIN_HTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_HTIMER*)0xF0000830u)
+
+/** Alias (User Manual Name) for ASCLIN2_LIN_HTIMER.
+* To use register names with standard convension, please use ASCLIN2_LIN_HTIMER.
+*/
+#define ASCLIN2_LINHTIMER (ASCLIN2_LIN_HTIMER)
+
+/** \brief E8, OCDS Control and Status */
+#define ASCLIN2_OCS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_OCS*)0xF00008E8u)
+
+/** \brief 48, Receive Data Register */
+#define ASCLIN2_RXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATA*)0xF0000848u)
+
+/** \brief 50, Receive Data Debug Register */
+#define ASCLIN2_RXDATAD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATAD*)0xF0000850u)
+
+/** \brief 10, RX FIFO Configuration Register */
+#define ASCLIN2_RXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXFIFOCON*)0xF0000810u)
+
+/** \brief 44, Transmit Data Register */
+#define ASCLIN2_TXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXDATA*)0xF0000844u)
+
+/** \brief C, TX FIFO Configuration Register */
+#define ASCLIN2_TXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXFIFOCON*)0xF000080Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Asclin_Cfg_Asclin3
+ * \{ */
+
+/** \brief FC, Access Enable Register 0 */
+#define ASCLIN3_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN0*)0xF00009FCu)
+
+/** \brief F8, Access Enable Register 1 */
+#define ASCLIN3_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN1*)0xF00009F8u)
+
+/** \brief 14, Bit Configuration Register */
+#define ASCLIN3_BITCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BITCON*)0xF0000914u)
+
+/** \brief 24, Baud Rate Detection Register */
+#define ASCLIN3_BRD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRD*)0xF0000924u)
+
+/** \brief 20, Baud Rate Generation Register */
+#define ASCLIN3_BRG /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRG*)0xF0000920u)
+
+/** \brief 0, Clock Control Register */
+#define ASCLIN3_CLC /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CLC*)0xF0000900u)
+
+/** \brief 4C, Clock Selection Register */
+#define ASCLIN3_CSR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CSR*)0xF000094Cu)
+
+/** \brief 1C, Data Configuration Register */
+#define ASCLIN3_DATCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_DATCON*)0xF000091Cu)
+
+/** \brief 34, Flags Register */
+#define ASCLIN3_FLAGS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGS*)0xF0000934u)
+
+/** \brief 3C, Flags Clear Register */
+#define ASCLIN3_FLAGSCLEAR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSCLEAR*)0xF000093Cu)
+
+/** \brief 40, Flags Enable Register */
+#define ASCLIN3_FLAGSENABLE /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSENABLE*)0xF0000940u)
+
+/** \brief 38, Flags Set Register */
+#define ASCLIN3_FLAGSSET /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSSET*)0xF0000938u)
+
+/** \brief 18, Frame Control Register */
+#define ASCLIN3_FRAMECON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FRAMECON*)0xF0000918u)
+
+/** \brief 8, Module Identification Register */
+#define ASCLIN3_ID /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ID*)0xF0000908u)
+
+/** \brief 4, Input and Output Control Register */
+#define ASCLIN3_IOCR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_IOCR*)0xF0000904u)
+
+/** \brief F4, Kernel Reset Register 0 */
+#define ASCLIN3_KRST0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST0*)0xF00009F4u)
+
+/** \brief F0, Kernel Reset Register 1 */
+#define ASCLIN3_KRST1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST1*)0xF00009F0u)
+
+/** \brief EC, Kernel Reset Status Clear Register */
+#define ASCLIN3_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRSTCLR*)0xF00009ECu)
+
+/** \brief 2C, LIN Break Timer Register */
+#define ASCLIN3_LIN_BTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_BTIMER*)0xF000092Cu)
+
+/** Alias (User Manual Name) for ASCLIN3_LIN_BTIMER.
+* To use register names with standard convension, please use ASCLIN3_LIN_BTIMER.
+*/
+#define ASCLIN3_LINBTIMER (ASCLIN3_LIN_BTIMER)
+
+/** \brief 28, LIN Control Register */
+#define ASCLIN3_LIN_CON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_CON*)0xF0000928u)
+
+/** Alias (User Manual Name) for ASCLIN3_LIN_CON.
+* To use register names with standard convension, please use ASCLIN3_LIN_CON.
+*/
+#define ASCLIN3_LINCON (ASCLIN3_LIN_CON)
+
+/** \brief 30, LIN Header Timer Register */
+#define ASCLIN3_LIN_HTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_HTIMER*)0xF0000930u)
+
+/** Alias (User Manual Name) for ASCLIN3_LIN_HTIMER.
+* To use register names with standard convension, please use ASCLIN3_LIN_HTIMER.
+*/
+#define ASCLIN3_LINHTIMER (ASCLIN3_LIN_HTIMER)
+
+/** \brief E8, OCDS Control and Status */
+#define ASCLIN3_OCS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_OCS*)0xF00009E8u)
+
+/** \brief 48, Receive Data Register */
+#define ASCLIN3_RXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATA*)0xF0000948u)
+
+/** \brief 50, Receive Data Debug Register */
+#define ASCLIN3_RXDATAD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATAD*)0xF0000950u)
+
+/** \brief 10, RX FIFO Configuration Register */
+#define ASCLIN3_RXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXFIFOCON*)0xF0000910u)
+
+/** \brief 44, Transmit Data Register */
+#define ASCLIN3_TXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXDATA*)0xF0000944u)
+
+/** \brief C, TX FIFO Configuration Register */
+#define ASCLIN3_TXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXFIFOCON*)0xF000090Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXASCLIN_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxAsclin_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxAsclin_regdef.h
new file mode 100644
index 0000000..916578e
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxAsclin_regdef.h
@@ -0,0 +1,699 @@
+/**
+ * \file IfxAsclin_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Asclin Asclin
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Asclin_Bitfields Bitfields
+ * \ingroup IfxLld_Asclin
+ *
+ * \defgroup IfxLld_Asclin_union Union
+ * \ingroup IfxLld_Asclin
+ *
+ * \defgroup IfxLld_Asclin_struct Struct
+ * \ingroup IfxLld_Asclin
+ *
+ */
+#ifndef IFXASCLIN_REGDEF_H
+#define IFXASCLIN_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Asclin_Bitfields
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef struct _Ifx_ASCLIN_ACCEN0_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_ASCLIN_ACCEN0_Bits;
+
+/** \brief Access Enable Register 1 */
+typedef struct _Ifx_ASCLIN_ACCEN1_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_ASCLIN_ACCEN1_Bits;
+
+/** \brief Bit Configuration Register */
+typedef struct _Ifx_ASCLIN_BITCON_Bits
+{
+ unsigned int PRESCALER:12; /**< \brief [11:0] Prescaling of the Fractional Divider (rw) */
+ unsigned int reserved_12:4; /**< \brief \internal Reserved */
+ unsigned int OVERSAMPLING:4; /**< \brief [19:16] Oversampling Factor (rw) */
+ unsigned int reserved_20:4; /**< \brief \internal Reserved */
+ unsigned int SAMPLEPOINT:4; /**< \brief [27:24] Sample Point Position (rw) */
+ unsigned int reserved_28:3; /**< \brief \internal Reserved */
+ unsigned int SM:1; /**< \brief [31:31] Sample Mode (rw) */
+} Ifx_ASCLIN_BITCON_Bits;
+
+/** \brief Baud Rate Detection Register */
+typedef struct _Ifx_ASCLIN_BRD_Bits
+{
+ unsigned int LOWERLIMIT:8; /**< \brief [7:0] Lower Limit (rw) */
+ unsigned int UPPERLIMIT:8; /**< \brief [15:8] Upper Limit (rw) */
+ unsigned int MEASURED:12; /**< \brief [27:16] Measured Value of the Denominator (rh) */
+ unsigned int reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_ASCLIN_BRD_Bits;
+
+/** \brief Baud Rate Generation Register */
+typedef struct _Ifx_ASCLIN_BRG_Bits
+{
+ unsigned int DENOMINATOR:12; /**< \brief [11:0] Denominator (rw) */
+ unsigned int reserved_12:4; /**< \brief \internal Reserved */
+ unsigned int NUMERATOR:12; /**< \brief [27:16] Numerator (rw) */
+ unsigned int reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_ASCLIN_BRG_Bits;
+
+/** \brief Clock Control Register */
+typedef struct _Ifx_ASCLIN_CLC_Bits
+{
+ unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
+ unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
+ unsigned int reserved_2:1; /**< \brief \internal Reserved */
+ unsigned int EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control (rw) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_ASCLIN_CLC_Bits;
+
+/** \brief Clock Selection Register */
+typedef struct _Ifx_ASCLIN_CSR_Bits
+{
+ unsigned int CLKSEL:5; /**< \brief [4:0] Baud Rate Logic Clock Select (rw) */
+ unsigned int reserved_5:26; /**< \brief \internal Reserved */
+ unsigned int CON:1; /**< \brief [31:31] Clock On Flag (rh) */
+} Ifx_ASCLIN_CSR_Bits;
+
+/** \brief Data Configuration Register */
+typedef struct _Ifx_ASCLIN_DATCON_Bits
+{
+ unsigned int DATLEN:4; /**< \brief [3:0] Data Length (rw) */
+ unsigned int reserved_4:9; /**< \brief \internal Reserved */
+ unsigned int HO:1; /**< \brief [13:13] Header Only (rw) */
+ unsigned int RM:1; /**< \brief [14:14] Response Mode (rw) */
+ unsigned int CSM:1; /**< \brief [15:15] Checksum Mode (rw) */
+ unsigned int RESPONSE:8; /**< \brief [23:16] Response Timeout Threshold Value (rw) */
+ unsigned int reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_ASCLIN_DATCON_Bits;
+
+/** \brief Flags Register */
+typedef struct _Ifx_ASCLIN_FLAGS_Bits
+{
+ unsigned int TH:1; /**< \brief [0:0] Transmit Header End Flag (rh) */
+ unsigned int TR:1; /**< \brief [1:1] Transmit Response End Flag (rh) */
+ unsigned int RH:1; /**< \brief [2:2] Receive Header End Flag (rh) */
+ unsigned int RR:1; /**< \brief [3:3] Receive Response End Flag (rh) */
+ unsigned int reserved_4:1; /**< \brief \internal Reserved */
+ unsigned int FED:1; /**< \brief [5:5] Falling Edge from Level 1 to Level 0 Detected (rh) */
+ unsigned int RED:1; /**< \brief [6:6] Rising Edge from Level 0 to Level 1 Detected (rh) */
+ unsigned int reserved_7:6; /**< \brief \internal Reserved */
+ unsigned int TWRQ:1; /**< \brief [13:13] Transmit Wake Request Flag (rh) */
+ unsigned int THRQ:1; /**< \brief [14:14] Transmit Header Request Flag (rh) */
+ unsigned int TRRQ:1; /**< \brief [15:15] Transmit Response Request Flag (rh) */
+ unsigned int PE:1; /**< \brief [16:16] Parity Error Flag (rh) */
+ unsigned int TC:1; /**< \brief [17:17] Transmission Completed Flag (rh) */
+ unsigned int FE:1; /**< \brief [18:18] Framing Error Flag (rh) */
+ unsigned int HT:1; /**< \brief [19:19] Header Timeout Flag (rh) */
+ unsigned int RT:1; /**< \brief [20:20] Response Timeout Flag (rh) */
+ unsigned int BD:1; /**< \brief [21:21] Break Detected Flag (rh) */
+ unsigned int LP:1; /**< \brief [22:22] LIN Parity Error Flag (rh) */
+ unsigned int LA:1; /**< \brief [23:23] LIN Autobaud Detection Error Flag (rh) */
+ unsigned int LC:1; /**< \brief [24:24] LIN Checksum Error Flag (rh) */
+ unsigned int CE:1; /**< \brief [25:25] Collision Detection Error Flag (rh) */
+ unsigned int RFO:1; /**< \brief [26:26] Receive FIFO Overflow Flag (rh) */
+ unsigned int RFU:1; /**< \brief [27:27] Receive FIFO Underflow Flag (rh) */
+ unsigned int RFL:1; /**< \brief [28:28] Receive FIFO Level Flag (rh) */
+ unsigned int reserved_29:1; /**< \brief \internal Reserved */
+ unsigned int TFO:1; /**< \brief [30:30] Transmit FIFO Overflow Flag (rh) */
+ unsigned int TFL:1; /**< \brief [31:31] Transmit FIFO Level Flag (rh) */
+} Ifx_ASCLIN_FLAGS_Bits;
+
+/** \brief Flags Clear Register */
+typedef struct _Ifx_ASCLIN_FLAGSCLEAR_Bits
+{
+ unsigned int THC:1; /**< \brief [0:0] Flag Clear Bit (w) */
+ unsigned int TRC:1; /**< \brief [1:1] Flag Clear Bit (w) */
+ unsigned int RHC:1; /**< \brief [2:2] Flag Clear Bit (w) */
+ unsigned int RRC:1; /**< \brief [3:3] Flag Clear Bit (w) */
+ unsigned int reserved_4:1; /**< \brief \internal Reserved */
+ unsigned int FEDC:1; /**< \brief [5:5] Flag Clear Bit (w) */
+ unsigned int REDC:1; /**< \brief [6:6] Flag Clear Bit (w) */
+ unsigned int reserved_7:6; /**< \brief \internal Reserved */
+ unsigned int TWRQC:1; /**< \brief [13:13] Flag Clear Bit (w) */
+ unsigned int THRQC:1; /**< \brief [14:14] Flag Clear Bit (w) */
+ unsigned int TRRQC:1; /**< \brief [15:15] Flag Clear Bit (w) */
+ unsigned int PEC:1; /**< \brief [16:16] Flag Clear Bit (w) */
+ unsigned int TCC:1; /**< \brief [17:17] Flag Clear Bit (w) */
+ unsigned int FEC:1; /**< \brief [18:18] Flag Clear Bit (w) */
+ unsigned int HTC:1; /**< \brief [19:19] Flag Clear Bit (w) */
+ unsigned int RTC:1; /**< \brief [20:20] Flag Clear Bit (w) */
+ unsigned int BDC:1; /**< \brief [21:21] Flag Clear Bit (w) */
+ unsigned int LPC:1; /**< \brief [22:22] Flag Clear Bit (w) */
+ unsigned int LAC:1; /**< \brief [23:23] Flag Clear Bit (w) */
+ unsigned int LCC:1; /**< \brief [24:24] Flag Clear Bit (w) */
+ unsigned int CEC:1; /**< \brief [25:25] Flag Clear Bit (w) */
+ unsigned int RFOC:1; /**< \brief [26:26] Flag Clear Bit (w) */
+ unsigned int RFUC:1; /**< \brief [27:27] Flag Clear Bit (w) */
+ unsigned int RFLC:1; /**< \brief [28:28] Flag Clear Bit (w) */
+ unsigned int reserved_29:1; /**< \brief \internal Reserved */
+ unsigned int TFOC:1; /**< \brief [30:30] Flag Clear Bit (w) */
+ unsigned int TFLC:1; /**< \brief [31:31] Flag Clear Bit (w) */
+} Ifx_ASCLIN_FLAGSCLEAR_Bits;
+
+/** \brief Flags Enable Register */
+typedef struct _Ifx_ASCLIN_FLAGSENABLE_Bits
+{
+ unsigned int THE:1; /**< \brief [0:0] Flag Enable Bit (rw) */
+ unsigned int TRE:1; /**< \brief [1:1] Flag Enable Bit (rw) */
+ unsigned int RHE:1; /**< \brief [2:2] Flag Enable Bit (rw) */
+ unsigned int RRE:1; /**< \brief [3:3] Flag Enable Bit (rw) */
+ unsigned int reserved_4:1; /**< \brief \internal Reserved */
+ unsigned int FEDE:1; /**< \brief [5:5] Flag Enable Bit (rw) */
+ unsigned int REDE:1; /**< \brief [6:6] Flag Enable Bit (rw) */
+ unsigned int reserved_7:9; /**< \brief \internal Reserved */
+ unsigned int PEE:1; /**< \brief [16:16] Flag Enable Bit (rw) */
+ unsigned int TCE:1; /**< \brief [17:17] Flag Enable Bit (rw) */
+ unsigned int FEE:1; /**< \brief [18:18] Flag Enable Bit (rw) */
+ unsigned int HTE:1; /**< \brief [19:19] Flag Enable Bit (rw) */
+ unsigned int RTE:1; /**< \brief [20:20] Flag Enable Bit (rw) */
+ unsigned int BDE:1; /**< \brief [21:21] Flag Enable Bit (rw) */
+ unsigned int LPE:1; /**< \brief [22:22] Flag Enable Bit (rw) */
+ unsigned int ABE:1; /**< \brief [23:23] Flag Enable Bit (rw) */
+ unsigned int LCE:1; /**< \brief [24:24] Flag Enable Bit (rw) */
+ unsigned int CEE:1; /**< \brief [25:25] Flag Enable Bit (rw) */
+ unsigned int RFOE:1; /**< \brief [26:26] Flag Enable Bit (rw) */
+ unsigned int RFUE:1; /**< \brief [27:27] Flag Enable Bit (rw) */
+ unsigned int RFLE:1; /**< \brief [28:28] Flag Enable Bit (rw) */
+ unsigned int reserved_29:1; /**< \brief \internal Reserved */
+ unsigned int TFOE:1; /**< \brief [30:30] Flag Enable Bit (rw) */
+ unsigned int TFLE:1; /**< \brief [31:31] Flag Enable Bit (rw) */
+} Ifx_ASCLIN_FLAGSENABLE_Bits;
+
+/** \brief Flags Set Register */
+typedef struct _Ifx_ASCLIN_FLAGSSET_Bits
+{
+ unsigned int THS:1; /**< \brief [0:0] Flag Set Bit (w) */
+ unsigned int TRS:1; /**< \brief [1:1] Flag Set Bit (w) */
+ unsigned int RHS:1; /**< \brief [2:2] Flag Set Bit (w) */
+ unsigned int RRS:1; /**< \brief [3:3] Flag Set Bit (w) */
+ unsigned int reserved_4:1; /**< \brief \internal Reserved */
+ unsigned int FEDS:1; /**< \brief [5:5] Flag Set Bit (w) */
+ unsigned int REDS:1; /**< \brief [6:6] Flag Set Bit (w) */
+ unsigned int reserved_7:6; /**< \brief \internal Reserved */
+ unsigned int TWRQS:1; /**< \brief [13:13] Flag Set Bit (w) */
+ unsigned int THRQS:1; /**< \brief [14:14] Flag Set Bit (w) */
+ unsigned int TRRQS:1; /**< \brief [15:15] Flag Set Bit (w) */
+ unsigned int PES:1; /**< \brief [16:16] Flag Set Bit (w) */
+ unsigned int TCS:1; /**< \brief [17:17] Flag Set Bit (w) */
+ unsigned int FES:1; /**< \brief [18:18] Flag Set Bit (w) */
+ unsigned int HTS:1; /**< \brief [19:19] Flag Set Bit (w) */
+ unsigned int RTS:1; /**< \brief [20:20] Flag Set Bit (w) */
+ unsigned int BDS:1; /**< \brief [21:21] Flag Set Bit (w) */
+ unsigned int LPS:1; /**< \brief [22:22] Flag Set Bit (w) */
+ unsigned int LAS:1; /**< \brief [23:23] Flag Set Bit (w) */
+ unsigned int LCS:1; /**< \brief [24:24] Flag Set Bit (w) */
+ unsigned int CES:1; /**< \brief [25:25] Flag Set Bit (w) */
+ unsigned int RFOS:1; /**< \brief [26:26] Flag Set Bit (w) */
+ unsigned int RFUS:1; /**< \brief [27:27] Flag Set Bit (w) */
+ unsigned int RFLS:1; /**< \brief [28:28] Flag Set Bit (w) */
+ unsigned int reserved_29:1; /**< \brief \internal Reserved */
+ unsigned int TFOS:1; /**< \brief [30:30] Flag Set Bit (w) */
+ unsigned int TFLS:1; /**< \brief [31:31] Flag Set Bit (w) */
+} Ifx_ASCLIN_FLAGSSET_Bits;
+
+/** \brief Frame Control Register */
+typedef struct _Ifx_ASCLIN_FRAMECON_Bits
+{
+ unsigned int reserved_0:6; /**< \brief \internal Reserved */
+ unsigned int IDLE:3; /**< \brief [8:6] Duration of the IDLE delay (rw) */
+ unsigned int STOP:3; /**< \brief [11:9] Number of Stop Bits (rw) */
+ unsigned int LEAD:3; /**< \brief [14:12] Duration of the Leading Delay (rw) */
+ unsigned int reserved_15:1; /**< \brief \internal Reserved */
+ unsigned int MODE:2; /**< \brief [17:16] Mode Selection (rw) */
+ unsigned int reserved_18:10; /**< \brief \internal Reserved */
+ unsigned int MSB:1; /**< \brief [28:28] Shift Direction (rw) */
+ unsigned int CEN:1; /**< \brief [29:29] Collision Detection Enable (rw) */
+ unsigned int PEN:1; /**< \brief [30:30] Parity Enable (rw) */
+ unsigned int ODD:1; /**< \brief [31:31] Parity Type (rw) */
+} Ifx_ASCLIN_FRAMECON_Bits;
+
+/** \brief Module Identification Register */
+typedef struct _Ifx_ASCLIN_ID_Bits
+{
+ unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
+ unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_ASCLIN_ID_Bits;
+
+/** \brief Input and Output Control Register */
+typedef struct _Ifx_ASCLIN_IOCR_Bits
+{
+ unsigned int ALTI:3; /**< \brief [2:0] Alternate Input Select (rw) */
+ unsigned int reserved_3:1; /**< \brief \internal Reserved */
+ unsigned int DEPTH:6; /**< \brief [9:4] Digital Glitch Filter Depth (rw) */
+ unsigned int reserved_10:6; /**< \brief \internal Reserved */
+ unsigned int CTS:2; /**< \brief [17:16] CTS Select (rw) */
+ unsigned int reserved_18:7; /**< \brief \internal Reserved */
+ unsigned int RCPOL:1; /**< \brief [25:25] RTS CTS Polarity (rw) */
+ unsigned int CPOL:1; /**< \brief [26:26] Clock Polarity in Synchronous Mode (rw) */
+ unsigned int SPOL:1; /**< \brief [27:27] Slave Polarity in Synchronous Mode (rw) */
+ unsigned int LB:1; /**< \brief [28:28] Loop Back Mode (rw) */
+ unsigned int CTSEN:1; /**< \brief [29:29] Input Signal CTS Enable (rw) */
+ unsigned int RXM:1; /**< \brief [30:30] Receive Monitor (rh) */
+ unsigned int TXM:1; /**< \brief [31:31] Transmit Monitor (rh) */
+} Ifx_ASCLIN_IOCR_Bits;
+
+/** \brief Kernel Reset Register 0 */
+typedef struct _Ifx_ASCLIN_KRST0_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rh) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_ASCLIN_KRST0_Bits;
+
+/** \brief Kernel Reset Register 1 */
+typedef struct _Ifx_ASCLIN_KRST1_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_ASCLIN_KRST1_Bits;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef struct _Ifx_ASCLIN_KRSTCLR_Bits
+{
+ unsigned int CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_ASCLIN_KRSTCLR_Bits;
+
+/** \brief LIN Break Timer Register */
+typedef struct _Ifx_ASCLIN_LIN_BTIMER_Bits
+{
+ unsigned int BREAK:6; /**< \brief [5:0] Break Pulse Generation and Detection (rw) */
+ unsigned int reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_ASCLIN_LIN_BTIMER_Bits;
+
+/** \brief LIN Control Register */
+typedef struct _Ifx_ASCLIN_LIN_CON_Bits
+{
+ unsigned int reserved_0:23; /**< \brief \internal Reserved */
+ unsigned int CSI:1; /**< \brief [23:23] Checksum Injection (rw) */
+ unsigned int reserved_24:1; /**< \brief \internal Reserved */
+ unsigned int CSEN:1; /**< \brief [25:25] Hardware Checksum Enable (rw) */
+ unsigned int MS:1; /**< \brief [26:26] Master Slave Mode (rw) */
+ unsigned int ABD:1; /**< \brief [27:27] Autobaud Detection (rw) */
+ unsigned int reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_ASCLIN_LIN_CON_Bits;
+
+/** \brief LIN Header Timer Register */
+typedef struct _Ifx_ASCLIN_LIN_HTIMER_Bits
+{
+ unsigned int HEADER:8; /**< \brief [7:0] Header Timeout Threshold Value (rw) */
+ unsigned int reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_ASCLIN_LIN_HTIMER_Bits;
+
+/** \brief OCDS Control and Status */
+typedef struct _Ifx_ASCLIN_OCS_Bits
+{
+ unsigned int reserved_0:24; /**< \brief \internal Reserved */
+ unsigned int SUS:4; /**< \brief [27:24] OCDS Suspend Control (rw) */
+ unsigned int SUS_P:1; /**< \brief [28:28] SUS Write Protection (w) */
+ unsigned int SUSSTA:1; /**< \brief [29:29] Suspend State (rh) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_ASCLIN_OCS_Bits;
+
+/** \brief Receive Data Register */
+typedef struct _Ifx_ASCLIN_RXDATA_Bits
+{
+ unsigned int DATA:32; /**< \brief [31:0] Data (rh) */
+} Ifx_ASCLIN_RXDATA_Bits;
+
+/** \brief Receive Data Debug Register */
+typedef struct _Ifx_ASCLIN_RXDATAD_Bits
+{
+ unsigned int DATA:32; /**< \brief [31:0] Data (rh) */
+} Ifx_ASCLIN_RXDATAD_Bits;
+
+/** \brief RX FIFO Configuration Register */
+typedef struct _Ifx_ASCLIN_RXFIFOCON_Bits
+{
+ unsigned int FLUSH:1; /**< \brief [0:0] Flush the receive FIFO (w) */
+ unsigned int ENI:1; /**< \brief [1:1] Receive FIFO Inlet Enable (rwh) */
+ unsigned int reserved_2:4; /**< \brief \internal Reserved */
+ unsigned int OUTW:2; /**< \brief [7:6] Receive FIFO Outlet Width (rw) */
+ unsigned int INTLEVEL:4; /**< \brief [11:8] FIFO Interrupt Level (rw) */
+ unsigned int reserved_12:4; /**< \brief \internal Reserved */
+ unsigned int FILL:5; /**< \brief [20:16] FIFO Filling Level (rh) */
+ unsigned int reserved_21:10; /**< \brief \internal Reserved */
+ unsigned int BUF:1; /**< \brief [31:31] Receive Buffer Mode (rw) */
+} Ifx_ASCLIN_RXFIFOCON_Bits;
+
+/** \brief Transmit Data Register */
+typedef struct _Ifx_ASCLIN_TXDATA_Bits
+{
+ unsigned int DATA:32; /**< \brief [31:0] Data (w) */
+} Ifx_ASCLIN_TXDATA_Bits;
+
+/** \brief TX FIFO Configuration Register */
+typedef struct _Ifx_ASCLIN_TXFIFOCON_Bits
+{
+ unsigned int FLUSH:1; /**< \brief [0:0] Flush the transmit FIFO (w) */
+ unsigned int ENO:1; /**< \brief [1:1] Transmit FIFO Outlet Enable (rw) */
+ unsigned int reserved_2:4; /**< \brief \internal Reserved */
+ unsigned int INW:2; /**< \brief [7:6] Transmit FIFO Inlet Width (rw) */
+ unsigned int INTLEVEL:4; /**< \brief [11:8] FIFO Interrupt Level (rw) */
+ unsigned int reserved_12:4; /**< \brief \internal Reserved */
+ unsigned int FILL:5; /**< \brief [20:16] FIFO Filling Level (rh) */
+ unsigned int reserved_21:11; /**< \brief \internal Reserved */
+} Ifx_ASCLIN_TXFIFOCON_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Asclin_union
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ASCLIN_ACCEN0_Bits B; /**< \brief Bitfield access */
+} Ifx_ASCLIN_ACCEN0;
+
+/** \brief Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ASCLIN_ACCEN1_Bits B; /**< \brief Bitfield access */
+} Ifx_ASCLIN_ACCEN1;
+
+/** \brief Bit Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ASCLIN_BITCON_Bits B; /**< \brief Bitfield access */
+} Ifx_ASCLIN_BITCON;
+
+/** \brief Baud Rate Detection Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ASCLIN_BRD_Bits B; /**< \brief Bitfield access */
+} Ifx_ASCLIN_BRD;
+
+/** \brief Baud Rate Generation Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ASCLIN_BRG_Bits B; /**< \brief Bitfield access */
+} Ifx_ASCLIN_BRG;
+
+/** \brief Clock Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ASCLIN_CLC_Bits B; /**< \brief Bitfield access */
+} Ifx_ASCLIN_CLC;
+
+/** \brief Clock Selection Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ASCLIN_CSR_Bits B; /**< \brief Bitfield access */
+} Ifx_ASCLIN_CSR;
+
+/** \brief Data Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ASCLIN_DATCON_Bits B; /**< \brief Bitfield access */
+} Ifx_ASCLIN_DATCON;
+
+/** \brief Flags Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ASCLIN_FLAGS_Bits B; /**< \brief Bitfield access */
+} Ifx_ASCLIN_FLAGS;
+
+/** \brief Flags Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ASCLIN_FLAGSCLEAR_Bits B; /**< \brief Bitfield access */
+} Ifx_ASCLIN_FLAGSCLEAR;
+
+/** \brief Flags Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ASCLIN_FLAGSENABLE_Bits B; /**< \brief Bitfield access */
+} Ifx_ASCLIN_FLAGSENABLE;
+
+/** \brief Flags Set Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ASCLIN_FLAGSSET_Bits B; /**< \brief Bitfield access */
+} Ifx_ASCLIN_FLAGSSET;
+
+/** \brief Frame Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ASCLIN_FRAMECON_Bits B; /**< \brief Bitfield access */
+} Ifx_ASCLIN_FRAMECON;
+
+/** \brief Module Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ASCLIN_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_ASCLIN_ID;
+
+/** \brief Input and Output Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ASCLIN_IOCR_Bits B; /**< \brief Bitfield access */
+} Ifx_ASCLIN_IOCR;
+
+/** \brief Kernel Reset Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ASCLIN_KRST0_Bits B; /**< \brief Bitfield access */
+} Ifx_ASCLIN_KRST0;
+
+/** \brief Kernel Reset Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ASCLIN_KRST1_Bits B; /**< \brief Bitfield access */
+} Ifx_ASCLIN_KRST1;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ASCLIN_KRSTCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_ASCLIN_KRSTCLR;
+
+/** \brief LIN Break Timer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ASCLIN_LIN_BTIMER_Bits B; /**< \brief Bitfield access */
+} Ifx_ASCLIN_LIN_BTIMER;
+
+/** \brief LIN Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ASCLIN_LIN_CON_Bits B; /**< \brief Bitfield access */
+} Ifx_ASCLIN_LIN_CON;
+
+/** \brief LIN Header Timer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ASCLIN_LIN_HTIMER_Bits B; /**< \brief Bitfield access */
+} Ifx_ASCLIN_LIN_HTIMER;
+
+/** \brief OCDS Control and Status */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ASCLIN_OCS_Bits B; /**< \brief Bitfield access */
+} Ifx_ASCLIN_OCS;
+
+/** \brief Receive Data Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ASCLIN_RXDATA_Bits B; /**< \brief Bitfield access */
+} Ifx_ASCLIN_RXDATA;
+
+/** \brief Receive Data Debug Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ASCLIN_RXDATAD_Bits B; /**< \brief Bitfield access */
+} Ifx_ASCLIN_RXDATAD;
+
+/** \brief RX FIFO Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ASCLIN_RXFIFOCON_Bits B; /**< \brief Bitfield access */
+} Ifx_ASCLIN_RXFIFOCON;
+
+/** \brief Transmit Data Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ASCLIN_TXDATA_Bits B; /**< \brief Bitfield access */
+} Ifx_ASCLIN_TXDATA;
+
+/** \brief TX FIFO Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ASCLIN_TXFIFOCON_Bits B; /**< \brief Bitfield access */
+} Ifx_ASCLIN_TXFIFOCON;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Asclin_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L1
+ * \{ */
+
+/** \brief LIN */
+typedef volatile struct _Ifx_ASCLIN_LIN
+{
+ Ifx_ASCLIN_LIN_CON CON; /**< \brief 0, LIN Control Register */
+ Ifx_ASCLIN_LIN_BTIMER BTIMER; /**< \brief 4, LIN Break Timer Register */
+ Ifx_ASCLIN_LIN_HTIMER HTIMER; /**< \brief 8, LIN Header Timer Register */
+} Ifx_ASCLIN_LIN;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Asclin_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief ASCLIN object */
+typedef volatile struct _Ifx_ASCLIN
+{
+ Ifx_ASCLIN_CLC CLC; /**< \brief 0, Clock Control Register */
+ Ifx_ASCLIN_IOCR IOCR; /**< \brief 4, Input and Output Control Register */
+ Ifx_ASCLIN_ID ID; /**< \brief 8, Module Identification Register */
+ Ifx_ASCLIN_TXFIFOCON TXFIFOCON; /**< \brief C, TX FIFO Configuration Register */
+ Ifx_ASCLIN_RXFIFOCON RXFIFOCON; /**< \brief 10, RX FIFO Configuration Register */
+ Ifx_ASCLIN_BITCON BITCON; /**< \brief 14, Bit Configuration Register */
+ Ifx_ASCLIN_FRAMECON FRAMECON; /**< \brief 18, Frame Control Register */
+ Ifx_ASCLIN_DATCON DATCON; /**< \brief 1C, Data Configuration Register */
+ Ifx_ASCLIN_BRG BRG; /**< \brief 20, Baud Rate Generation Register */
+ Ifx_ASCLIN_BRD BRD; /**< \brief 24, Baud Rate Detection Register */
+ Ifx_ASCLIN_LIN LIN; /**< \brief 28, LIN */
+ Ifx_ASCLIN_FLAGS FLAGS; /**< \brief 34, Flags Register */
+ Ifx_ASCLIN_FLAGSSET FLAGSSET; /**< \brief 38, Flags Set Register */
+ Ifx_ASCLIN_FLAGSCLEAR FLAGSCLEAR; /**< \brief 3C, Flags Clear Register */
+ Ifx_ASCLIN_FLAGSENABLE FLAGSENABLE; /**< \brief 40, Flags Enable Register */
+ Ifx_ASCLIN_TXDATA TXDATA; /**< \brief 44, Transmit Data Register */
+ Ifx_ASCLIN_RXDATA RXDATA; /**< \brief 48, Receive Data Register */
+ Ifx_ASCLIN_CSR CSR; /**< \brief 4C, Clock Selection Register */
+ Ifx_ASCLIN_RXDATAD RXDATAD; /**< \brief 50, Receive Data Debug Register */
+ unsigned char reserved_54[148]; /**< \brief 54, \internal Reserved */
+ Ifx_ASCLIN_OCS OCS; /**< \brief E8, OCDS Control and Status */
+ Ifx_ASCLIN_KRSTCLR KRSTCLR; /**< \brief EC, Kernel Reset Status Clear Register */
+ Ifx_ASCLIN_KRST1 KRST1; /**< \brief F0, Kernel Reset Register 1 */
+ Ifx_ASCLIN_KRST0 KRST0; /**< \brief F4, Kernel Reset Register 0 */
+ Ifx_ASCLIN_ACCEN1 ACCEN1; /**< \brief F8, Access Enable Register 1 */
+ Ifx_ASCLIN_ACCEN0 ACCEN0; /**< \brief FC, Access Enable Register 0 */
+} Ifx_ASCLIN;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXASCLIN_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCan_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCan_bf.h
new file mode 100644
index 0000000..994ba3f
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCan_bf.h
@@ -0,0 +1,2214 @@
+/**
+ * \file IfxCan_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Can_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Can
+ *
+ */
+#ifndef IFXCAN_BF_H
+#define IFXCAN_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Can_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN0 */
+#define IFX_CAN_ACCEN0_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN0 */
+#define IFX_CAN_ACCEN0_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN0 */
+#define IFX_CAN_ACCEN0_EN0_OFF (0u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN10 */
+#define IFX_CAN_ACCEN0_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN10 */
+#define IFX_CAN_ACCEN0_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN10 */
+#define IFX_CAN_ACCEN0_EN10_OFF (10u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN11 */
+#define IFX_CAN_ACCEN0_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN11 */
+#define IFX_CAN_ACCEN0_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN11 */
+#define IFX_CAN_ACCEN0_EN11_OFF (11u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN12 */
+#define IFX_CAN_ACCEN0_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN12 */
+#define IFX_CAN_ACCEN0_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN12 */
+#define IFX_CAN_ACCEN0_EN12_OFF (12u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN13 */
+#define IFX_CAN_ACCEN0_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN13 */
+#define IFX_CAN_ACCEN0_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN13 */
+#define IFX_CAN_ACCEN0_EN13_OFF (13u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN14 */
+#define IFX_CAN_ACCEN0_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN14 */
+#define IFX_CAN_ACCEN0_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN14 */
+#define IFX_CAN_ACCEN0_EN14_OFF (14u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN15 */
+#define IFX_CAN_ACCEN0_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN15 */
+#define IFX_CAN_ACCEN0_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN15 */
+#define IFX_CAN_ACCEN0_EN15_OFF (15u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN16 */
+#define IFX_CAN_ACCEN0_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN16 */
+#define IFX_CAN_ACCEN0_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN16 */
+#define IFX_CAN_ACCEN0_EN16_OFF (16u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN17 */
+#define IFX_CAN_ACCEN0_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN17 */
+#define IFX_CAN_ACCEN0_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN17 */
+#define IFX_CAN_ACCEN0_EN17_OFF (17u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN18 */
+#define IFX_CAN_ACCEN0_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN18 */
+#define IFX_CAN_ACCEN0_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN18 */
+#define IFX_CAN_ACCEN0_EN18_OFF (18u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN19 */
+#define IFX_CAN_ACCEN0_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN19 */
+#define IFX_CAN_ACCEN0_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN19 */
+#define IFX_CAN_ACCEN0_EN19_OFF (19u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN1 */
+#define IFX_CAN_ACCEN0_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN1 */
+#define IFX_CAN_ACCEN0_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN1 */
+#define IFX_CAN_ACCEN0_EN1_OFF (1u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN20 */
+#define IFX_CAN_ACCEN0_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN20 */
+#define IFX_CAN_ACCEN0_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN20 */
+#define IFX_CAN_ACCEN0_EN20_OFF (20u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN21 */
+#define IFX_CAN_ACCEN0_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN21 */
+#define IFX_CAN_ACCEN0_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN21 */
+#define IFX_CAN_ACCEN0_EN21_OFF (21u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN22 */
+#define IFX_CAN_ACCEN0_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN22 */
+#define IFX_CAN_ACCEN0_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN22 */
+#define IFX_CAN_ACCEN0_EN22_OFF (22u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN23 */
+#define IFX_CAN_ACCEN0_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN23 */
+#define IFX_CAN_ACCEN0_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN23 */
+#define IFX_CAN_ACCEN0_EN23_OFF (23u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN24 */
+#define IFX_CAN_ACCEN0_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN24 */
+#define IFX_CAN_ACCEN0_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN24 */
+#define IFX_CAN_ACCEN0_EN24_OFF (24u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN25 */
+#define IFX_CAN_ACCEN0_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN25 */
+#define IFX_CAN_ACCEN0_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN25 */
+#define IFX_CAN_ACCEN0_EN25_OFF (25u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN26 */
+#define IFX_CAN_ACCEN0_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN26 */
+#define IFX_CAN_ACCEN0_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN26 */
+#define IFX_CAN_ACCEN0_EN26_OFF (26u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN27 */
+#define IFX_CAN_ACCEN0_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN27 */
+#define IFX_CAN_ACCEN0_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN27 */
+#define IFX_CAN_ACCEN0_EN27_OFF (27u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN28 */
+#define IFX_CAN_ACCEN0_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN28 */
+#define IFX_CAN_ACCEN0_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN28 */
+#define IFX_CAN_ACCEN0_EN28_OFF (28u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN29 */
+#define IFX_CAN_ACCEN0_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN29 */
+#define IFX_CAN_ACCEN0_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN29 */
+#define IFX_CAN_ACCEN0_EN29_OFF (29u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN2 */
+#define IFX_CAN_ACCEN0_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN2 */
+#define IFX_CAN_ACCEN0_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN2 */
+#define IFX_CAN_ACCEN0_EN2_OFF (2u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN30 */
+#define IFX_CAN_ACCEN0_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN30 */
+#define IFX_CAN_ACCEN0_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN30 */
+#define IFX_CAN_ACCEN0_EN30_OFF (30u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN31 */
+#define IFX_CAN_ACCEN0_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN31 */
+#define IFX_CAN_ACCEN0_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN31 */
+#define IFX_CAN_ACCEN0_EN31_OFF (31u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN3 */
+#define IFX_CAN_ACCEN0_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN3 */
+#define IFX_CAN_ACCEN0_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN3 */
+#define IFX_CAN_ACCEN0_EN3_OFF (3u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN4 */
+#define IFX_CAN_ACCEN0_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN4 */
+#define IFX_CAN_ACCEN0_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN4 */
+#define IFX_CAN_ACCEN0_EN4_OFF (4u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN5 */
+#define IFX_CAN_ACCEN0_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN5 */
+#define IFX_CAN_ACCEN0_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN5 */
+#define IFX_CAN_ACCEN0_EN5_OFF (5u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN6 */
+#define IFX_CAN_ACCEN0_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN6 */
+#define IFX_CAN_ACCEN0_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN6 */
+#define IFX_CAN_ACCEN0_EN6_OFF (6u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN7 */
+#define IFX_CAN_ACCEN0_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN7 */
+#define IFX_CAN_ACCEN0_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN7 */
+#define IFX_CAN_ACCEN0_EN7_OFF (7u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN8 */
+#define IFX_CAN_ACCEN0_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN8 */
+#define IFX_CAN_ACCEN0_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN8 */
+#define IFX_CAN_ACCEN0_EN8_OFF (8u)
+
+/** \brief Length for Ifx_CAN_ACCEN0_Bits.EN9 */
+#define IFX_CAN_ACCEN0_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_ACCEN0_Bits.EN9 */
+#define IFX_CAN_ACCEN0_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_ACCEN0_Bits.EN9 */
+#define IFX_CAN_ACCEN0_EN9_OFF (9u)
+
+/** \brief Length for Ifx_CAN_CLC_Bits.DISR */
+#define IFX_CAN_CLC_DISR_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_CLC_Bits.DISR */
+#define IFX_CAN_CLC_DISR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_CLC_Bits.DISR */
+#define IFX_CAN_CLC_DISR_OFF (0u)
+
+/** \brief Length for Ifx_CAN_CLC_Bits.DISS */
+#define IFX_CAN_CLC_DISS_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_CLC_Bits.DISS */
+#define IFX_CAN_CLC_DISS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_CLC_Bits.DISS */
+#define IFX_CAN_CLC_DISS_OFF (1u)
+
+/** \brief Length for Ifx_CAN_CLC_Bits.EDIS */
+#define IFX_CAN_CLC_EDIS_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_CLC_Bits.EDIS */
+#define IFX_CAN_CLC_EDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_CLC_Bits.EDIS */
+#define IFX_CAN_CLC_EDIS_OFF (3u)
+
+/** \brief Length for Ifx_CAN_FDR_Bits.DM */
+#define IFX_CAN_FDR_DM_LEN (2u)
+
+/** \brief Mask for Ifx_CAN_FDR_Bits.DM */
+#define IFX_CAN_FDR_DM_MSK (0x3u)
+
+/** \brief Offset for Ifx_CAN_FDR_Bits.DM */
+#define IFX_CAN_FDR_DM_OFF (14u)
+
+/** \brief Length for Ifx_CAN_FDR_Bits.STEP */
+#define IFX_CAN_FDR_STEP_LEN (10u)
+
+/** \brief Mask for Ifx_CAN_FDR_Bits.STEP */
+#define IFX_CAN_FDR_STEP_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_CAN_FDR_Bits.STEP */
+#define IFX_CAN_FDR_STEP_OFF (0u)
+
+/** \brief Length for Ifx_CAN_ID_Bits.MODNUMBER */
+#define IFX_CAN_ID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_CAN_ID_Bits.MODNUMBER */
+#define IFX_CAN_ID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CAN_ID_Bits.MODNUMBER */
+#define IFX_CAN_ID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_CAN_ID_Bits.MODREV */
+#define IFX_CAN_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_ID_Bits.MODREV */
+#define IFX_CAN_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_ID_Bits.MODREV */
+#define IFX_CAN_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_CAN_ID_Bits.MODTYPE */
+#define IFX_CAN_ID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_ID_Bits.MODTYPE */
+#define IFX_CAN_ID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_ID_Bits.MODTYPE */
+#define IFX_CAN_ID_MODTYPE_OFF (8u)
+
+/** \brief Length for Ifx_CAN_KRST0_Bits.RST */
+#define IFX_CAN_KRST0_RST_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_KRST0_Bits.RST */
+#define IFX_CAN_KRST0_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_KRST0_Bits.RST */
+#define IFX_CAN_KRST0_RST_OFF (0u)
+
+/** \brief Length for Ifx_CAN_KRST0_Bits.RSTSTAT */
+#define IFX_CAN_KRST0_RSTSTAT_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_KRST0_Bits.RSTSTAT */
+#define IFX_CAN_KRST0_RSTSTAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_KRST0_Bits.RSTSTAT */
+#define IFX_CAN_KRST0_RSTSTAT_OFF (1u)
+
+/** \brief Length for Ifx_CAN_KRST1_Bits.RST */
+#define IFX_CAN_KRST1_RST_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_KRST1_Bits.RST */
+#define IFX_CAN_KRST1_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_KRST1_Bits.RST */
+#define IFX_CAN_KRST1_RST_OFF (0u)
+
+/** \brief Length for Ifx_CAN_KRSTCLR_Bits.CLR */
+#define IFX_CAN_KRSTCLR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_KRSTCLR_Bits.CLR */
+#define IFX_CAN_KRSTCLR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_KRSTCLR_Bits.CLR */
+#define IFX_CAN_KRSTCLR_CLR_OFF (0u)
+
+/** \brief Length for Ifx_CAN_LIST_Bits.BEGIN */
+#define IFX_CAN_LIST_BEGIN_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_LIST_Bits.BEGIN */
+#define IFX_CAN_LIST_BEGIN_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_LIST_Bits.BEGIN */
+#define IFX_CAN_LIST_BEGIN_OFF (0u)
+
+/** \brief Length for Ifx_CAN_LIST_Bits.EMPTY */
+#define IFX_CAN_LIST_EMPTY_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_LIST_Bits.EMPTY */
+#define IFX_CAN_LIST_EMPTY_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_LIST_Bits.EMPTY */
+#define IFX_CAN_LIST_EMPTY_OFF (24u)
+
+/** \brief Length for Ifx_CAN_LIST_Bits.END */
+#define IFX_CAN_LIST_END_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_LIST_Bits.END */
+#define IFX_CAN_LIST_END_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_LIST_Bits.END */
+#define IFX_CAN_LIST_END_OFF (8u)
+
+/** \brief Length for Ifx_CAN_LIST_Bits.SIZE */
+#define IFX_CAN_LIST_SIZE_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_LIST_Bits.SIZE */
+#define IFX_CAN_LIST_SIZE_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_LIST_Bits.SIZE */
+#define IFX_CAN_LIST_SIZE_OFF (16u)
+
+/** \brief Length for Ifx_CAN_MCR_Bits.CLKSEL */
+#define IFX_CAN_MCR_CLKSEL_LEN (4u)
+
+/** \brief Mask for Ifx_CAN_MCR_Bits.CLKSEL */
+#define IFX_CAN_MCR_CLKSEL_MSK (0xfu)
+
+/** \brief Offset for Ifx_CAN_MCR_Bits.CLKSEL */
+#define IFX_CAN_MCR_CLKSEL_OFF (0u)
+
+/** \brief Length for Ifx_CAN_MCR_Bits.MPSEL */
+#define IFX_CAN_MCR_MPSEL_LEN (4u)
+
+/** \brief Mask for Ifx_CAN_MCR_Bits.MPSEL */
+#define IFX_CAN_MCR_MPSEL_MSK (0xfu)
+
+/** \brief Offset for Ifx_CAN_MCR_Bits.MPSEL */
+#define IFX_CAN_MCR_MPSEL_OFF (12u)
+
+/** \brief Length for Ifx_CAN_MECR_Bits.ANYED */
+#define IFX_CAN_MECR_ANYED_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MECR_Bits.ANYED */
+#define IFX_CAN_MECR_ANYED_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MECR_Bits.ANYED */
+#define IFX_CAN_MECR_ANYED_OFF (24u)
+
+/** \brief Length for Ifx_CAN_MECR_Bits.CAPEIE */
+#define IFX_CAN_MECR_CAPEIE_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MECR_Bits.CAPEIE */
+#define IFX_CAN_MECR_CAPEIE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MECR_Bits.CAPEIE */
+#define IFX_CAN_MECR_CAPEIE_OFF (25u)
+
+/** \brief Length for Ifx_CAN_MECR_Bits.DEPTH */
+#define IFX_CAN_MECR_DEPTH_LEN (3u)
+
+/** \brief Mask for Ifx_CAN_MECR_Bits.DEPTH */
+#define IFX_CAN_MECR_DEPTH_MSK (0x7u)
+
+/** \brief Offset for Ifx_CAN_MECR_Bits.DEPTH */
+#define IFX_CAN_MECR_DEPTH_OFF (27u)
+
+/** \brief Length for Ifx_CAN_MECR_Bits.INP */
+#define IFX_CAN_MECR_INP_LEN (4u)
+
+/** \brief Mask for Ifx_CAN_MECR_Bits.INP */
+#define IFX_CAN_MECR_INP_MSK (0xfu)
+
+/** \brief Offset for Ifx_CAN_MECR_Bits.INP */
+#define IFX_CAN_MECR_INP_OFF (16u)
+
+/** \brief Length for Ifx_CAN_MECR_Bits.NODE */
+#define IFX_CAN_MECR_NODE_LEN (3u)
+
+/** \brief Mask for Ifx_CAN_MECR_Bits.NODE */
+#define IFX_CAN_MECR_NODE_MSK (0x7u)
+
+/** \brief Offset for Ifx_CAN_MECR_Bits.NODE */
+#define IFX_CAN_MECR_NODE_OFF (20u)
+
+/** \brief Length for Ifx_CAN_MECR_Bits.SOF */
+#define IFX_CAN_MECR_SOF_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MECR_Bits.SOF */
+#define IFX_CAN_MECR_SOF_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MECR_Bits.SOF */
+#define IFX_CAN_MECR_SOF_OFF (30u)
+
+/** \brief Length for Ifx_CAN_MECR_Bits.TH */
+#define IFX_CAN_MECR_TH_LEN (16u)
+
+/** \brief Mask for Ifx_CAN_MECR_Bits.TH */
+#define IFX_CAN_MECR_TH_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CAN_MECR_Bits.TH */
+#define IFX_CAN_MECR_TH_OFF (0u)
+
+/** \brief Length for Ifx_CAN_MESTAT_Bits.CAPE */
+#define IFX_CAN_MESTAT_CAPE_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MESTAT_Bits.CAPE */
+#define IFX_CAN_MESTAT_CAPE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MESTAT_Bits.CAPE */
+#define IFX_CAN_MESTAT_CAPE_OFF (17u)
+
+/** \brief Length for Ifx_CAN_MESTAT_Bits.CAPRED */
+#define IFX_CAN_MESTAT_CAPRED_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MESTAT_Bits.CAPRED */
+#define IFX_CAN_MESTAT_CAPRED_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MESTAT_Bits.CAPRED */
+#define IFX_CAN_MESTAT_CAPRED_OFF (16u)
+
+/** \brief Length for Ifx_CAN_MESTAT_Bits.CAPT */
+#define IFX_CAN_MESTAT_CAPT_LEN (16u)
+
+/** \brief Mask for Ifx_CAN_MESTAT_Bits.CAPT */
+#define IFX_CAN_MESTAT_CAPT_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CAN_MESTAT_Bits.CAPT */
+#define IFX_CAN_MESTAT_CAPT_OFF (0u)
+
+/** \brief Length for Ifx_CAN_MITR_Bits.IT */
+#define IFX_CAN_MITR_IT_LEN (16u)
+
+/** \brief Mask for Ifx_CAN_MITR_Bits.IT */
+#define IFX_CAN_MITR_IT_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CAN_MITR_Bits.IT */
+#define IFX_CAN_MITR_IT_OFF (0u)
+
+/** \brief Length for Ifx_CAN_MO_AMR_Bits.AM */
+#define IFX_CAN_MO_AMR_AM_LEN (29u)
+
+/** \brief Mask for Ifx_CAN_MO_AMR_Bits.AM */
+#define IFX_CAN_MO_AMR_AM_MSK (0x1fffffffu)
+
+/** \brief Offset for Ifx_CAN_MO_AMR_Bits.AM */
+#define IFX_CAN_MO_AMR_AM_OFF (0u)
+
+/** \brief Length for Ifx_CAN_MO_AMR_Bits.MIDE */
+#define IFX_CAN_MO_AMR_MIDE_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_AMR_Bits.MIDE */
+#define IFX_CAN_MO_AMR_MIDE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_AMR_Bits.MIDE */
+#define IFX_CAN_MO_AMR_MIDE_OFF (29u)
+
+/** \brief Length for Ifx_CAN_MO_AR_Bits.ID */
+#define IFX_CAN_MO_AR_ID_LEN (29u)
+
+/** \brief Mask for Ifx_CAN_MO_AR_Bits.ID */
+#define IFX_CAN_MO_AR_ID_MSK (0x1fffffffu)
+
+/** \brief Offset for Ifx_CAN_MO_AR_Bits.ID */
+#define IFX_CAN_MO_AR_ID_OFF (0u)
+
+/** \brief Length for Ifx_CAN_MO_AR_Bits.IDE */
+#define IFX_CAN_MO_AR_IDE_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_AR_Bits.IDE */
+#define IFX_CAN_MO_AR_IDE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_AR_Bits.IDE */
+#define IFX_CAN_MO_AR_IDE_OFF (29u)
+
+/** \brief Length for Ifx_CAN_MO_AR_Bits.PRI */
+#define IFX_CAN_MO_AR_PRI_LEN (2u)
+
+/** \brief Mask for Ifx_CAN_MO_AR_Bits.PRI */
+#define IFX_CAN_MO_AR_PRI_MSK (0x3u)
+
+/** \brief Offset for Ifx_CAN_MO_AR_Bits.PRI */
+#define IFX_CAN_MO_AR_PRI_OFF (30u)
+
+/** \brief Length for Ifx_CAN_MO_CTR_Bits.RESDIR */
+#define IFX_CAN_MO_CTR_RESDIR_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_CTR_Bits.RESDIR */
+#define IFX_CAN_MO_CTR_RESDIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_CTR_Bits.RESDIR */
+#define IFX_CAN_MO_CTR_RESDIR_OFF (11u)
+
+/** \brief Length for Ifx_CAN_MO_CTR_Bits.RESMSGLST */
+#define IFX_CAN_MO_CTR_RESMSGLST_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_CTR_Bits.RESMSGLST */
+#define IFX_CAN_MO_CTR_RESMSGLST_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_CTR_Bits.RESMSGLST */
+#define IFX_CAN_MO_CTR_RESMSGLST_OFF (4u)
+
+/** \brief Length for Ifx_CAN_MO_CTR_Bits.RESMSGVAL */
+#define IFX_CAN_MO_CTR_RESMSGVAL_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_CTR_Bits.RESMSGVAL */
+#define IFX_CAN_MO_CTR_RESMSGVAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_CTR_Bits.RESMSGVAL */
+#define IFX_CAN_MO_CTR_RESMSGVAL_OFF (5u)
+
+/** \brief Length for Ifx_CAN_MO_CTR_Bits.RESNEWDAT */
+#define IFX_CAN_MO_CTR_RESNEWDAT_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_CTR_Bits.RESNEWDAT */
+#define IFX_CAN_MO_CTR_RESNEWDAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_CTR_Bits.RESNEWDAT */
+#define IFX_CAN_MO_CTR_RESNEWDAT_OFF (3u)
+
+/** \brief Length for Ifx_CAN_MO_CTR_Bits.RESRTSEL */
+#define IFX_CAN_MO_CTR_RESRTSEL_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_CTR_Bits.RESRTSEL */
+#define IFX_CAN_MO_CTR_RESRTSEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_CTR_Bits.RESRTSEL */
+#define IFX_CAN_MO_CTR_RESRTSEL_OFF (6u)
+
+/** \brief Length for Ifx_CAN_MO_CTR_Bits.RESRXEN */
+#define IFX_CAN_MO_CTR_RESRXEN_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_CTR_Bits.RESRXEN */
+#define IFX_CAN_MO_CTR_RESRXEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_CTR_Bits.RESRXEN */
+#define IFX_CAN_MO_CTR_RESRXEN_OFF (7u)
+
+/** \brief Length for Ifx_CAN_MO_CTR_Bits.RESRXPND */
+#define IFX_CAN_MO_CTR_RESRXPND_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_CTR_Bits.RESRXPND */
+#define IFX_CAN_MO_CTR_RESRXPND_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_CTR_Bits.RESRXPND */
+#define IFX_CAN_MO_CTR_RESRXPND_OFF (0u)
+
+/** \brief Length for Ifx_CAN_MO_CTR_Bits.RESRXUPD */
+#define IFX_CAN_MO_CTR_RESRXUPD_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_CTR_Bits.RESRXUPD */
+#define IFX_CAN_MO_CTR_RESRXUPD_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_CTR_Bits.RESRXUPD */
+#define IFX_CAN_MO_CTR_RESRXUPD_OFF (2u)
+
+/** \brief Length for Ifx_CAN_MO_CTR_Bits.RESTXEN0 */
+#define IFX_CAN_MO_CTR_RESTXEN0_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_CTR_Bits.RESTXEN0 */
+#define IFX_CAN_MO_CTR_RESTXEN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_CTR_Bits.RESTXEN0 */
+#define IFX_CAN_MO_CTR_RESTXEN0_OFF (9u)
+
+/** \brief Length for Ifx_CAN_MO_CTR_Bits.RESTXEN1 */
+#define IFX_CAN_MO_CTR_RESTXEN1_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_CTR_Bits.RESTXEN1 */
+#define IFX_CAN_MO_CTR_RESTXEN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_CTR_Bits.RESTXEN1 */
+#define IFX_CAN_MO_CTR_RESTXEN1_OFF (10u)
+
+/** \brief Length for Ifx_CAN_MO_CTR_Bits.RESTXPND */
+#define IFX_CAN_MO_CTR_RESTXPND_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_CTR_Bits.RESTXPND */
+#define IFX_CAN_MO_CTR_RESTXPND_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_CTR_Bits.RESTXPND */
+#define IFX_CAN_MO_CTR_RESTXPND_OFF (1u)
+
+/** \brief Length for Ifx_CAN_MO_CTR_Bits.RESTXRQ */
+#define IFX_CAN_MO_CTR_RESTXRQ_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_CTR_Bits.RESTXRQ */
+#define IFX_CAN_MO_CTR_RESTXRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_CTR_Bits.RESTXRQ */
+#define IFX_CAN_MO_CTR_RESTXRQ_OFF (8u)
+
+/** \brief Length for Ifx_CAN_MO_CTR_Bits.SETDIR */
+#define IFX_CAN_MO_CTR_SETDIR_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_CTR_Bits.SETDIR */
+#define IFX_CAN_MO_CTR_SETDIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_CTR_Bits.SETDIR */
+#define IFX_CAN_MO_CTR_SETDIR_OFF (27u)
+
+/** \brief Length for Ifx_CAN_MO_CTR_Bits.SETMSGLST */
+#define IFX_CAN_MO_CTR_SETMSGLST_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_CTR_Bits.SETMSGLST */
+#define IFX_CAN_MO_CTR_SETMSGLST_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_CTR_Bits.SETMSGLST */
+#define IFX_CAN_MO_CTR_SETMSGLST_OFF (20u)
+
+/** \brief Length for Ifx_CAN_MO_CTR_Bits.SETMSGVAL */
+#define IFX_CAN_MO_CTR_SETMSGVAL_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_CTR_Bits.SETMSGVAL */
+#define IFX_CAN_MO_CTR_SETMSGVAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_CTR_Bits.SETMSGVAL */
+#define IFX_CAN_MO_CTR_SETMSGVAL_OFF (21u)
+
+/** \brief Length for Ifx_CAN_MO_CTR_Bits.SETNEWDAT */
+#define IFX_CAN_MO_CTR_SETNEWDAT_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_CTR_Bits.SETNEWDAT */
+#define IFX_CAN_MO_CTR_SETNEWDAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_CTR_Bits.SETNEWDAT */
+#define IFX_CAN_MO_CTR_SETNEWDAT_OFF (19u)
+
+/** \brief Length for Ifx_CAN_MO_CTR_Bits.SETRTSEL */
+#define IFX_CAN_MO_CTR_SETRTSEL_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_CTR_Bits.SETRTSEL */
+#define IFX_CAN_MO_CTR_SETRTSEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_CTR_Bits.SETRTSEL */
+#define IFX_CAN_MO_CTR_SETRTSEL_OFF (22u)
+
+/** \brief Length for Ifx_CAN_MO_CTR_Bits.SETRXEN */
+#define IFX_CAN_MO_CTR_SETRXEN_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_CTR_Bits.SETRXEN */
+#define IFX_CAN_MO_CTR_SETRXEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_CTR_Bits.SETRXEN */
+#define IFX_CAN_MO_CTR_SETRXEN_OFF (23u)
+
+/** \brief Length for Ifx_CAN_MO_CTR_Bits.SETRXPND */
+#define IFX_CAN_MO_CTR_SETRXPND_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_CTR_Bits.SETRXPND */
+#define IFX_CAN_MO_CTR_SETRXPND_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_CTR_Bits.SETRXPND */
+#define IFX_CAN_MO_CTR_SETRXPND_OFF (16u)
+
+/** \brief Length for Ifx_CAN_MO_CTR_Bits.SETRXUPD */
+#define IFX_CAN_MO_CTR_SETRXUPD_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_CTR_Bits.SETRXUPD */
+#define IFX_CAN_MO_CTR_SETRXUPD_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_CTR_Bits.SETRXUPD */
+#define IFX_CAN_MO_CTR_SETRXUPD_OFF (18u)
+
+/** \brief Length for Ifx_CAN_MO_CTR_Bits.SETTXEN0 */
+#define IFX_CAN_MO_CTR_SETTXEN0_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_CTR_Bits.SETTXEN0 */
+#define IFX_CAN_MO_CTR_SETTXEN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_CTR_Bits.SETTXEN0 */
+#define IFX_CAN_MO_CTR_SETTXEN0_OFF (25u)
+
+/** \brief Length for Ifx_CAN_MO_CTR_Bits.SETTXEN1 */
+#define IFX_CAN_MO_CTR_SETTXEN1_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_CTR_Bits.SETTXEN1 */
+#define IFX_CAN_MO_CTR_SETTXEN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_CTR_Bits.SETTXEN1 */
+#define IFX_CAN_MO_CTR_SETTXEN1_OFF (26u)
+
+/** \brief Length for Ifx_CAN_MO_CTR_Bits.SETTXPND */
+#define IFX_CAN_MO_CTR_SETTXPND_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_CTR_Bits.SETTXPND */
+#define IFX_CAN_MO_CTR_SETTXPND_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_CTR_Bits.SETTXPND */
+#define IFX_CAN_MO_CTR_SETTXPND_OFF (17u)
+
+/** \brief Length for Ifx_CAN_MO_CTR_Bits.SETTXRQ */
+#define IFX_CAN_MO_CTR_SETTXRQ_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_CTR_Bits.SETTXRQ */
+#define IFX_CAN_MO_CTR_SETTXRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_CTR_Bits.SETTXRQ */
+#define IFX_CAN_MO_CTR_SETTXRQ_OFF (24u)
+
+/** \brief Length for Ifx_CAN_MO_DATAH_Bits.DB4 */
+#define IFX_CAN_MO_DATAH_DB4_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_DATAH_Bits.DB4 */
+#define IFX_CAN_MO_DATAH_DB4_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_DATAH_Bits.DB4 */
+#define IFX_CAN_MO_DATAH_DB4_OFF (0u)
+
+/** \brief Length for Ifx_CAN_MO_DATAH_Bits.DB5 */
+#define IFX_CAN_MO_DATAH_DB5_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_DATAH_Bits.DB5 */
+#define IFX_CAN_MO_DATAH_DB5_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_DATAH_Bits.DB5 */
+#define IFX_CAN_MO_DATAH_DB5_OFF (8u)
+
+/** \brief Length for Ifx_CAN_MO_DATAH_Bits.DB6 */
+#define IFX_CAN_MO_DATAH_DB6_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_DATAH_Bits.DB6 */
+#define IFX_CAN_MO_DATAH_DB6_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_DATAH_Bits.DB6 */
+#define IFX_CAN_MO_DATAH_DB6_OFF (16u)
+
+/** \brief Length for Ifx_CAN_MO_DATAH_Bits.DB7 */
+#define IFX_CAN_MO_DATAH_DB7_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_DATAH_Bits.DB7 */
+#define IFX_CAN_MO_DATAH_DB7_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_DATAH_Bits.DB7 */
+#define IFX_CAN_MO_DATAH_DB7_OFF (24u)
+
+/** \brief Length for Ifx_CAN_MO_DATAL_Bits.DB0 */
+#define IFX_CAN_MO_DATAL_DB0_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_DATAL_Bits.DB0 */
+#define IFX_CAN_MO_DATAL_DB0_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_DATAL_Bits.DB0 */
+#define IFX_CAN_MO_DATAL_DB0_OFF (0u)
+
+/** \brief Length for Ifx_CAN_MO_DATAL_Bits.DB1 */
+#define IFX_CAN_MO_DATAL_DB1_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_DATAL_Bits.DB1 */
+#define IFX_CAN_MO_DATAL_DB1_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_DATAL_Bits.DB1 */
+#define IFX_CAN_MO_DATAL_DB1_OFF (8u)
+
+/** \brief Length for Ifx_CAN_MO_DATAL_Bits.DB2 */
+#define IFX_CAN_MO_DATAL_DB2_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_DATAL_Bits.DB2 */
+#define IFX_CAN_MO_DATAL_DB2_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_DATAL_Bits.DB2 */
+#define IFX_CAN_MO_DATAL_DB2_OFF (16u)
+
+/** \brief Length for Ifx_CAN_MO_DATAL_Bits.DB3 */
+#define IFX_CAN_MO_DATAL_DB3_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_DATAL_Bits.DB3 */
+#define IFX_CAN_MO_DATAL_DB3_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_DATAL_Bits.DB3 */
+#define IFX_CAN_MO_DATAL_DB3_OFF (24u)
+
+/** \brief Length for Ifx_CAN_MO_EDATA0_Bits.DB0 */
+#define IFX_CAN_MO_EDATA0_DB0_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_EDATA0_Bits.DB0 */
+#define IFX_CAN_MO_EDATA0_DB0_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_EDATA0_Bits.DB0 */
+#define IFX_CAN_MO_EDATA0_DB0_OFF (0u)
+
+/** \brief Length for Ifx_CAN_MO_EDATA0_Bits.DB1 */
+#define IFX_CAN_MO_EDATA0_DB1_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_EDATA0_Bits.DB1 */
+#define IFX_CAN_MO_EDATA0_DB1_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_EDATA0_Bits.DB1 */
+#define IFX_CAN_MO_EDATA0_DB1_OFF (8u)
+
+/** \brief Length for Ifx_CAN_MO_EDATA0_Bits.DB2 */
+#define IFX_CAN_MO_EDATA0_DB2_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_EDATA0_Bits.DB2 */
+#define IFX_CAN_MO_EDATA0_DB2_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_EDATA0_Bits.DB2 */
+#define IFX_CAN_MO_EDATA0_DB2_OFF (16u)
+
+/** \brief Length for Ifx_CAN_MO_EDATA0_Bits.DB3 */
+#define IFX_CAN_MO_EDATA0_DB3_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_EDATA0_Bits.DB3 */
+#define IFX_CAN_MO_EDATA0_DB3_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_EDATA0_Bits.DB3 */
+#define IFX_CAN_MO_EDATA0_DB3_OFF (24u)
+
+/** \brief Length for Ifx_CAN_MO_EDATA1_Bits.DB0 */
+#define IFX_CAN_MO_EDATA1_DB0_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_EDATA1_Bits.DB0 */
+#define IFX_CAN_MO_EDATA1_DB0_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_EDATA1_Bits.DB0 */
+#define IFX_CAN_MO_EDATA1_DB0_OFF (0u)
+
+/** \brief Length for Ifx_CAN_MO_EDATA1_Bits.DB1 */
+#define IFX_CAN_MO_EDATA1_DB1_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_EDATA1_Bits.DB1 */
+#define IFX_CAN_MO_EDATA1_DB1_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_EDATA1_Bits.DB1 */
+#define IFX_CAN_MO_EDATA1_DB1_OFF (8u)
+
+/** \brief Length for Ifx_CAN_MO_EDATA1_Bits.DB2 */
+#define IFX_CAN_MO_EDATA1_DB2_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_EDATA1_Bits.DB2 */
+#define IFX_CAN_MO_EDATA1_DB2_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_EDATA1_Bits.DB2 */
+#define IFX_CAN_MO_EDATA1_DB2_OFF (16u)
+
+/** \brief Length for Ifx_CAN_MO_EDATA1_Bits.DB3 */
+#define IFX_CAN_MO_EDATA1_DB3_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_EDATA1_Bits.DB3 */
+#define IFX_CAN_MO_EDATA1_DB3_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_EDATA1_Bits.DB3 */
+#define IFX_CAN_MO_EDATA1_DB3_OFF (24u)
+
+/** \brief Length for Ifx_CAN_MO_EDATA2_Bits.DB0 */
+#define IFX_CAN_MO_EDATA2_DB0_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_EDATA2_Bits.DB0 */
+#define IFX_CAN_MO_EDATA2_DB0_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_EDATA2_Bits.DB0 */
+#define IFX_CAN_MO_EDATA2_DB0_OFF (0u)
+
+/** \brief Length for Ifx_CAN_MO_EDATA2_Bits.DB1 */
+#define IFX_CAN_MO_EDATA2_DB1_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_EDATA2_Bits.DB1 */
+#define IFX_CAN_MO_EDATA2_DB1_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_EDATA2_Bits.DB1 */
+#define IFX_CAN_MO_EDATA2_DB1_OFF (8u)
+
+/** \brief Length for Ifx_CAN_MO_EDATA2_Bits.DB2 */
+#define IFX_CAN_MO_EDATA2_DB2_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_EDATA2_Bits.DB2 */
+#define IFX_CAN_MO_EDATA2_DB2_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_EDATA2_Bits.DB2 */
+#define IFX_CAN_MO_EDATA2_DB2_OFF (16u)
+
+/** \brief Length for Ifx_CAN_MO_EDATA2_Bits.DB3 */
+#define IFX_CAN_MO_EDATA2_DB3_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_EDATA2_Bits.DB3 */
+#define IFX_CAN_MO_EDATA2_DB3_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_EDATA2_Bits.DB3 */
+#define IFX_CAN_MO_EDATA2_DB3_OFF (24u)
+
+/** \brief Length for Ifx_CAN_MO_EDATA3_Bits.DB0 */
+#define IFX_CAN_MO_EDATA3_DB0_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_EDATA3_Bits.DB0 */
+#define IFX_CAN_MO_EDATA3_DB0_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_EDATA3_Bits.DB0 */
+#define IFX_CAN_MO_EDATA3_DB0_OFF (0u)
+
+/** \brief Length for Ifx_CAN_MO_EDATA3_Bits.DB1 */
+#define IFX_CAN_MO_EDATA3_DB1_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_EDATA3_Bits.DB1 */
+#define IFX_CAN_MO_EDATA3_DB1_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_EDATA3_Bits.DB1 */
+#define IFX_CAN_MO_EDATA3_DB1_OFF (8u)
+
+/** \brief Length for Ifx_CAN_MO_EDATA3_Bits.DB2 */
+#define IFX_CAN_MO_EDATA3_DB2_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_EDATA3_Bits.DB2 */
+#define IFX_CAN_MO_EDATA3_DB2_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_EDATA3_Bits.DB2 */
+#define IFX_CAN_MO_EDATA3_DB2_OFF (16u)
+
+/** \brief Length for Ifx_CAN_MO_EDATA3_Bits.DB3 */
+#define IFX_CAN_MO_EDATA3_DB3_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_EDATA3_Bits.DB3 */
+#define IFX_CAN_MO_EDATA3_DB3_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_EDATA3_Bits.DB3 */
+#define IFX_CAN_MO_EDATA3_DB3_OFF (24u)
+
+/** \brief Length for Ifx_CAN_MO_EDATA4_Bits.DB0 */
+#define IFX_CAN_MO_EDATA4_DB0_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_EDATA4_Bits.DB0 */
+#define IFX_CAN_MO_EDATA4_DB0_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_EDATA4_Bits.DB0 */
+#define IFX_CAN_MO_EDATA4_DB0_OFF (0u)
+
+/** \brief Length for Ifx_CAN_MO_EDATA4_Bits.DB1 */
+#define IFX_CAN_MO_EDATA4_DB1_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_EDATA4_Bits.DB1 */
+#define IFX_CAN_MO_EDATA4_DB1_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_EDATA4_Bits.DB1 */
+#define IFX_CAN_MO_EDATA4_DB1_OFF (8u)
+
+/** \brief Length for Ifx_CAN_MO_EDATA4_Bits.DB2 */
+#define IFX_CAN_MO_EDATA4_DB2_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_EDATA4_Bits.DB2 */
+#define IFX_CAN_MO_EDATA4_DB2_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_EDATA4_Bits.DB2 */
+#define IFX_CAN_MO_EDATA4_DB2_OFF (16u)
+
+/** \brief Length for Ifx_CAN_MO_EDATA4_Bits.DB3 */
+#define IFX_CAN_MO_EDATA4_DB3_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_EDATA4_Bits.DB3 */
+#define IFX_CAN_MO_EDATA4_DB3_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_EDATA4_Bits.DB3 */
+#define IFX_CAN_MO_EDATA4_DB3_OFF (24u)
+
+/** \brief Length for Ifx_CAN_MO_EDATA5_Bits.DB0 */
+#define IFX_CAN_MO_EDATA5_DB0_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_EDATA5_Bits.DB0 */
+#define IFX_CAN_MO_EDATA5_DB0_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_EDATA5_Bits.DB0 */
+#define IFX_CAN_MO_EDATA5_DB0_OFF (0u)
+
+/** \brief Length for Ifx_CAN_MO_EDATA5_Bits.DB1 */
+#define IFX_CAN_MO_EDATA5_DB1_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_EDATA5_Bits.DB1 */
+#define IFX_CAN_MO_EDATA5_DB1_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_EDATA5_Bits.DB1 */
+#define IFX_CAN_MO_EDATA5_DB1_OFF (8u)
+
+/** \brief Length for Ifx_CAN_MO_EDATA5_Bits.DB2 */
+#define IFX_CAN_MO_EDATA5_DB2_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_EDATA5_Bits.DB2 */
+#define IFX_CAN_MO_EDATA5_DB2_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_EDATA5_Bits.DB2 */
+#define IFX_CAN_MO_EDATA5_DB2_OFF (16u)
+
+/** \brief Length for Ifx_CAN_MO_EDATA5_Bits.DB3 */
+#define IFX_CAN_MO_EDATA5_DB3_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_EDATA5_Bits.DB3 */
+#define IFX_CAN_MO_EDATA5_DB3_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_EDATA5_Bits.DB3 */
+#define IFX_CAN_MO_EDATA5_DB3_OFF (24u)
+
+/** \brief Length for Ifx_CAN_MO_EDATA6_Bits.DB0 */
+#define IFX_CAN_MO_EDATA6_DB0_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_EDATA6_Bits.DB0 */
+#define IFX_CAN_MO_EDATA6_DB0_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_EDATA6_Bits.DB0 */
+#define IFX_CAN_MO_EDATA6_DB0_OFF (0u)
+
+/** \brief Length for Ifx_CAN_MO_EDATA6_Bits.DB1 */
+#define IFX_CAN_MO_EDATA6_DB1_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_EDATA6_Bits.DB1 */
+#define IFX_CAN_MO_EDATA6_DB1_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_EDATA6_Bits.DB1 */
+#define IFX_CAN_MO_EDATA6_DB1_OFF (8u)
+
+/** \brief Length for Ifx_CAN_MO_EDATA6_Bits.DB2 */
+#define IFX_CAN_MO_EDATA6_DB2_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_EDATA6_Bits.DB2 */
+#define IFX_CAN_MO_EDATA6_DB2_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_EDATA6_Bits.DB2 */
+#define IFX_CAN_MO_EDATA6_DB2_OFF (16u)
+
+/** \brief Length for Ifx_CAN_MO_EDATA6_Bits.DB3 */
+#define IFX_CAN_MO_EDATA6_DB3_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_EDATA6_Bits.DB3 */
+#define IFX_CAN_MO_EDATA6_DB3_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_EDATA6_Bits.DB3 */
+#define IFX_CAN_MO_EDATA6_DB3_OFF (24u)
+
+/** \brief Length for Ifx_CAN_MO_FCR_Bits.BRS */
+#define IFX_CAN_MO_FCR_BRS_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_FCR_Bits.BRS */
+#define IFX_CAN_MO_FCR_BRS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_FCR_Bits.BRS */
+#define IFX_CAN_MO_FCR_BRS_OFF (5u)
+
+/** \brief Length for Ifx_CAN_MO_FCR_Bits.DATC */
+#define IFX_CAN_MO_FCR_DATC_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_FCR_Bits.DATC */
+#define IFX_CAN_MO_FCR_DATC_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_FCR_Bits.DATC */
+#define IFX_CAN_MO_FCR_DATC_OFF (11u)
+
+/** \brief Length for Ifx_CAN_MO_FCR_Bits.DLC */
+#define IFX_CAN_MO_FCR_DLC_LEN (4u)
+
+/** \brief Mask for Ifx_CAN_MO_FCR_Bits.DLC */
+#define IFX_CAN_MO_FCR_DLC_MSK (0xfu)
+
+/** \brief Offset for Ifx_CAN_MO_FCR_Bits.DLC */
+#define IFX_CAN_MO_FCR_DLC_OFF (24u)
+
+/** \brief Length for Ifx_CAN_MO_FCR_Bits.DLCC */
+#define IFX_CAN_MO_FCR_DLCC_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_FCR_Bits.DLCC */
+#define IFX_CAN_MO_FCR_DLCC_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_FCR_Bits.DLCC */
+#define IFX_CAN_MO_FCR_DLCC_OFF (10u)
+
+/** \brief Length for Ifx_CAN_MO_FCR_Bits.FDF */
+#define IFX_CAN_MO_FCR_FDF_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_FCR_Bits.FDF */
+#define IFX_CAN_MO_FCR_FDF_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_FCR_Bits.FDF */
+#define IFX_CAN_MO_FCR_FDF_OFF (6u)
+
+/** \brief Length for Ifx_CAN_MO_FCR_Bits.FRREN */
+#define IFX_CAN_MO_FCR_FRREN_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_FCR_Bits.FRREN */
+#define IFX_CAN_MO_FCR_FRREN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_FCR_Bits.FRREN */
+#define IFX_CAN_MO_FCR_FRREN_OFF (20u)
+
+/** \brief Length for Ifx_CAN_MO_FCR_Bits.GDFS */
+#define IFX_CAN_MO_FCR_GDFS_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_FCR_Bits.GDFS */
+#define IFX_CAN_MO_FCR_GDFS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_FCR_Bits.GDFS */
+#define IFX_CAN_MO_FCR_GDFS_OFF (8u)
+
+/** \brief Length for Ifx_CAN_MO_FCR_Bits.IDC */
+#define IFX_CAN_MO_FCR_IDC_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_FCR_Bits.IDC */
+#define IFX_CAN_MO_FCR_IDC_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_FCR_Bits.IDC */
+#define IFX_CAN_MO_FCR_IDC_OFF (9u)
+
+/** \brief Length for Ifx_CAN_MO_FCR_Bits.MMC */
+#define IFX_CAN_MO_FCR_MMC_LEN (4u)
+
+/** \brief Mask for Ifx_CAN_MO_FCR_Bits.MMC */
+#define IFX_CAN_MO_FCR_MMC_MSK (0xfu)
+
+/** \brief Offset for Ifx_CAN_MO_FCR_Bits.MMC */
+#define IFX_CAN_MO_FCR_MMC_OFF (0u)
+
+/** \brief Length for Ifx_CAN_MO_FCR_Bits.OVIE */
+#define IFX_CAN_MO_FCR_OVIE_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_FCR_Bits.OVIE */
+#define IFX_CAN_MO_FCR_OVIE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_FCR_Bits.OVIE */
+#define IFX_CAN_MO_FCR_OVIE_OFF (18u)
+
+/** \brief Length for Ifx_CAN_MO_FCR_Bits.RMM */
+#define IFX_CAN_MO_FCR_RMM_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_FCR_Bits.RMM */
+#define IFX_CAN_MO_FCR_RMM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_FCR_Bits.RMM */
+#define IFX_CAN_MO_FCR_RMM_OFF (21u)
+
+/** \brief Length for Ifx_CAN_MO_FCR_Bits.RXIE */
+#define IFX_CAN_MO_FCR_RXIE_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_FCR_Bits.RXIE */
+#define IFX_CAN_MO_FCR_RXIE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_FCR_Bits.RXIE */
+#define IFX_CAN_MO_FCR_RXIE_OFF (16u)
+
+/** \brief Length for Ifx_CAN_MO_FCR_Bits.RXTOE */
+#define IFX_CAN_MO_FCR_RXTOE_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_FCR_Bits.RXTOE */
+#define IFX_CAN_MO_FCR_RXTOE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_FCR_Bits.RXTOE */
+#define IFX_CAN_MO_FCR_RXTOE_OFF (4u)
+
+/** \brief Length for Ifx_CAN_MO_FCR_Bits.SDT */
+#define IFX_CAN_MO_FCR_SDT_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_FCR_Bits.SDT */
+#define IFX_CAN_MO_FCR_SDT_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_FCR_Bits.SDT */
+#define IFX_CAN_MO_FCR_SDT_OFF (22u)
+
+/** \brief Length for Ifx_CAN_MO_FCR_Bits.STT */
+#define IFX_CAN_MO_FCR_STT_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_FCR_Bits.STT */
+#define IFX_CAN_MO_FCR_STT_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_FCR_Bits.STT */
+#define IFX_CAN_MO_FCR_STT_OFF (23u)
+
+/** \brief Length for Ifx_CAN_MO_FCR_Bits.TXIE */
+#define IFX_CAN_MO_FCR_TXIE_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_FCR_Bits.TXIE */
+#define IFX_CAN_MO_FCR_TXIE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_FCR_Bits.TXIE */
+#define IFX_CAN_MO_FCR_TXIE_OFF (17u)
+
+/** \brief Length for Ifx_CAN_MO_FGPR_Bits.BOT */
+#define IFX_CAN_MO_FGPR_BOT_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_FGPR_Bits.BOT */
+#define IFX_CAN_MO_FGPR_BOT_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_FGPR_Bits.BOT */
+#define IFX_CAN_MO_FGPR_BOT_OFF (0u)
+
+/** \brief Length for Ifx_CAN_MO_FGPR_Bits.CUR */
+#define IFX_CAN_MO_FGPR_CUR_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_FGPR_Bits.CUR */
+#define IFX_CAN_MO_FGPR_CUR_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_FGPR_Bits.CUR */
+#define IFX_CAN_MO_FGPR_CUR_OFF (16u)
+
+/** \brief Length for Ifx_CAN_MO_FGPR_Bits.SEL */
+#define IFX_CAN_MO_FGPR_SEL_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_FGPR_Bits.SEL */
+#define IFX_CAN_MO_FGPR_SEL_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_FGPR_Bits.SEL */
+#define IFX_CAN_MO_FGPR_SEL_OFF (24u)
+
+/** \brief Length for Ifx_CAN_MO_FGPR_Bits.TOP */
+#define IFX_CAN_MO_FGPR_TOP_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_FGPR_Bits.TOP */
+#define IFX_CAN_MO_FGPR_TOP_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_FGPR_Bits.TOP */
+#define IFX_CAN_MO_FGPR_TOP_OFF (8u)
+
+/** \brief Length for Ifx_CAN_MO_IPR_Bits.CFCVAL */
+#define IFX_CAN_MO_IPR_CFCVAL_LEN (16u)
+
+/** \brief Mask for Ifx_CAN_MO_IPR_Bits.CFCVAL */
+#define IFX_CAN_MO_IPR_CFCVAL_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CAN_MO_IPR_Bits.CFCVAL */
+#define IFX_CAN_MO_IPR_CFCVAL_OFF (16u)
+
+/** \brief Length for Ifx_CAN_MO_IPR_Bits.MPN */
+#define IFX_CAN_MO_IPR_MPN_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_IPR_Bits.MPN */
+#define IFX_CAN_MO_IPR_MPN_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_IPR_Bits.MPN */
+#define IFX_CAN_MO_IPR_MPN_OFF (8u)
+
+/** \brief Length for Ifx_CAN_MO_IPR_Bits.RXINP */
+#define IFX_CAN_MO_IPR_RXINP_LEN (4u)
+
+/** \brief Mask for Ifx_CAN_MO_IPR_Bits.RXINP */
+#define IFX_CAN_MO_IPR_RXINP_MSK (0xfu)
+
+/** \brief Offset for Ifx_CAN_MO_IPR_Bits.RXINP */
+#define IFX_CAN_MO_IPR_RXINP_OFF (0u)
+
+/** \brief Length for Ifx_CAN_MO_IPR_Bits.TXINP */
+#define IFX_CAN_MO_IPR_TXINP_LEN (4u)
+
+/** \brief Mask for Ifx_CAN_MO_IPR_Bits.TXINP */
+#define IFX_CAN_MO_IPR_TXINP_MSK (0xfu)
+
+/** \brief Offset for Ifx_CAN_MO_IPR_Bits.TXINP */
+#define IFX_CAN_MO_IPR_TXINP_OFF (4u)
+
+/** \brief Length for Ifx_CAN_MO_STAT_Bits.DIR */
+#define IFX_CAN_MO_STAT_DIR_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_STAT_Bits.DIR */
+#define IFX_CAN_MO_STAT_DIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_STAT_Bits.DIR */
+#define IFX_CAN_MO_STAT_DIR_OFF (11u)
+
+/** \brief Length for Ifx_CAN_MO_STAT_Bits.LIST */
+#define IFX_CAN_MO_STAT_LIST_LEN (4u)
+
+/** \brief Mask for Ifx_CAN_MO_STAT_Bits.LIST */
+#define IFX_CAN_MO_STAT_LIST_MSK (0xfu)
+
+/** \brief Offset for Ifx_CAN_MO_STAT_Bits.LIST */
+#define IFX_CAN_MO_STAT_LIST_OFF (12u)
+
+/** \brief Length for Ifx_CAN_MO_STAT_Bits.MSGLST */
+#define IFX_CAN_MO_STAT_MSGLST_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_STAT_Bits.MSGLST */
+#define IFX_CAN_MO_STAT_MSGLST_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_STAT_Bits.MSGLST */
+#define IFX_CAN_MO_STAT_MSGLST_OFF (4u)
+
+/** \brief Length for Ifx_CAN_MO_STAT_Bits.MSGVAL */
+#define IFX_CAN_MO_STAT_MSGVAL_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_STAT_Bits.MSGVAL */
+#define IFX_CAN_MO_STAT_MSGVAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_STAT_Bits.MSGVAL */
+#define IFX_CAN_MO_STAT_MSGVAL_OFF (5u)
+
+/** \brief Length for Ifx_CAN_MO_STAT_Bits.NEWDAT */
+#define IFX_CAN_MO_STAT_NEWDAT_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_STAT_Bits.NEWDAT */
+#define IFX_CAN_MO_STAT_NEWDAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_STAT_Bits.NEWDAT */
+#define IFX_CAN_MO_STAT_NEWDAT_OFF (3u)
+
+/** \brief Length for Ifx_CAN_MO_STAT_Bits.PNEXT */
+#define IFX_CAN_MO_STAT_PNEXT_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_STAT_Bits.PNEXT */
+#define IFX_CAN_MO_STAT_PNEXT_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_STAT_Bits.PNEXT */
+#define IFX_CAN_MO_STAT_PNEXT_OFF (24u)
+
+/** \brief Length for Ifx_CAN_MO_STAT_Bits.PPREV */
+#define IFX_CAN_MO_STAT_PPREV_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_MO_STAT_Bits.PPREV */
+#define IFX_CAN_MO_STAT_PPREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_MO_STAT_Bits.PPREV */
+#define IFX_CAN_MO_STAT_PPREV_OFF (16u)
+
+/** \brief Length for Ifx_CAN_MO_STAT_Bits.RTSEL */
+#define IFX_CAN_MO_STAT_RTSEL_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_STAT_Bits.RTSEL */
+#define IFX_CAN_MO_STAT_RTSEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_STAT_Bits.RTSEL */
+#define IFX_CAN_MO_STAT_RTSEL_OFF (6u)
+
+/** \brief Length for Ifx_CAN_MO_STAT_Bits.RXEN */
+#define IFX_CAN_MO_STAT_RXEN_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_STAT_Bits.RXEN */
+#define IFX_CAN_MO_STAT_RXEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_STAT_Bits.RXEN */
+#define IFX_CAN_MO_STAT_RXEN_OFF (7u)
+
+/** \brief Length for Ifx_CAN_MO_STAT_Bits.RXPND */
+#define IFX_CAN_MO_STAT_RXPND_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_STAT_Bits.RXPND */
+#define IFX_CAN_MO_STAT_RXPND_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_STAT_Bits.RXPND */
+#define IFX_CAN_MO_STAT_RXPND_OFF (0u)
+
+/** \brief Length for Ifx_CAN_MO_STAT_Bits.RXUPD */
+#define IFX_CAN_MO_STAT_RXUPD_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_STAT_Bits.RXUPD */
+#define IFX_CAN_MO_STAT_RXUPD_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_STAT_Bits.RXUPD */
+#define IFX_CAN_MO_STAT_RXUPD_OFF (2u)
+
+/** \brief Length for Ifx_CAN_MO_STAT_Bits.TXEN0 */
+#define IFX_CAN_MO_STAT_TXEN0_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_STAT_Bits.TXEN0 */
+#define IFX_CAN_MO_STAT_TXEN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_STAT_Bits.TXEN0 */
+#define IFX_CAN_MO_STAT_TXEN0_OFF (9u)
+
+/** \brief Length for Ifx_CAN_MO_STAT_Bits.TXEN1 */
+#define IFX_CAN_MO_STAT_TXEN1_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_STAT_Bits.TXEN1 */
+#define IFX_CAN_MO_STAT_TXEN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_STAT_Bits.TXEN1 */
+#define IFX_CAN_MO_STAT_TXEN1_OFF (10u)
+
+/** \brief Length for Ifx_CAN_MO_STAT_Bits.TXPND */
+#define IFX_CAN_MO_STAT_TXPND_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_STAT_Bits.TXPND */
+#define IFX_CAN_MO_STAT_TXPND_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_STAT_Bits.TXPND */
+#define IFX_CAN_MO_STAT_TXPND_OFF (1u)
+
+/** \brief Length for Ifx_CAN_MO_STAT_Bits.TXRQ */
+#define IFX_CAN_MO_STAT_TXRQ_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_MO_STAT_Bits.TXRQ */
+#define IFX_CAN_MO_STAT_TXRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_MO_STAT_Bits.TXRQ */
+#define IFX_CAN_MO_STAT_TXRQ_OFF (8u)
+
+/** \brief Length for Ifx_CAN_MSID_Bits.INDEX */
+#define IFX_CAN_MSID_INDEX_LEN (6u)
+
+/** \brief Mask for Ifx_CAN_MSID_Bits.INDEX */
+#define IFX_CAN_MSID_INDEX_MSK (0x3fu)
+
+/** \brief Offset for Ifx_CAN_MSID_Bits.INDEX */
+#define IFX_CAN_MSID_INDEX_OFF (0u)
+
+/** \brief Length for Ifx_CAN_MSIMASK_Bits.IM */
+#define IFX_CAN_MSIMASK_IM_LEN (32u)
+
+/** \brief Mask for Ifx_CAN_MSIMASK_Bits.IM */
+#define IFX_CAN_MSIMASK_IM_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_CAN_MSIMASK_Bits.IM */
+#define IFX_CAN_MSIMASK_IM_OFF (0u)
+
+/** \brief Length for Ifx_CAN_MSPND_Bits.PND */
+#define IFX_CAN_MSPND_PND_LEN (32u)
+
+/** \brief Mask for Ifx_CAN_MSPND_Bits.PND */
+#define IFX_CAN_MSPND_PND_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_CAN_MSPND_Bits.PND */
+#define IFX_CAN_MSPND_PND_OFF (0u)
+
+/** \brief Length for Ifx_CAN_N_BTEVR_Bits.BRP */
+#define IFX_CAN_N_BTEVR_BRP_LEN (6u)
+
+/** \brief Mask for Ifx_CAN_N_BTEVR_Bits.BRP */
+#define IFX_CAN_N_BTEVR_BRP_MSK (0x3fu)
+
+/** \brief Offset for Ifx_CAN_N_BTEVR_Bits.BRP */
+#define IFX_CAN_N_BTEVR_BRP_OFF (0u)
+
+/** \brief Length for Ifx_CAN_N_BTEVR_Bits.DIV8 */
+#define IFX_CAN_N_BTEVR_DIV8_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_N_BTEVR_Bits.DIV8 */
+#define IFX_CAN_N_BTEVR_DIV8_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_N_BTEVR_Bits.DIV8 */
+#define IFX_CAN_N_BTEVR_DIV8_OFF (15u)
+
+/** \brief Length for Ifx_CAN_N_BTEVR_Bits.SJW */
+#define IFX_CAN_N_BTEVR_SJW_LEN (4u)
+
+/** \brief Mask for Ifx_CAN_N_BTEVR_Bits.SJW */
+#define IFX_CAN_N_BTEVR_SJW_MSK (0xfu)
+
+/** \brief Offset for Ifx_CAN_N_BTEVR_Bits.SJW */
+#define IFX_CAN_N_BTEVR_SJW_OFF (8u)
+
+/** \brief Length for Ifx_CAN_N_BTEVR_Bits.TSEG1 */
+#define IFX_CAN_N_BTEVR_TSEG1_LEN (6u)
+
+/** \brief Mask for Ifx_CAN_N_BTEVR_Bits.TSEG1 */
+#define IFX_CAN_N_BTEVR_TSEG1_MSK (0x3fu)
+
+/** \brief Offset for Ifx_CAN_N_BTEVR_Bits.TSEG1 */
+#define IFX_CAN_N_BTEVR_TSEG1_OFF (22u)
+
+/** \brief Length for Ifx_CAN_N_BTEVR_Bits.TSEG2 */
+#define IFX_CAN_N_BTEVR_TSEG2_LEN (5u)
+
+/** \brief Mask for Ifx_CAN_N_BTEVR_Bits.TSEG2 */
+#define IFX_CAN_N_BTEVR_TSEG2_MSK (0x1fu)
+
+/** \brief Offset for Ifx_CAN_N_BTEVR_Bits.TSEG2 */
+#define IFX_CAN_N_BTEVR_TSEG2_OFF (16u)
+
+/** \brief Length for Ifx_CAN_N_BTR_Bits.BRP */
+#define IFX_CAN_N_BTR_BRP_LEN (6u)
+
+/** \brief Mask for Ifx_CAN_N_BTR_Bits.BRP */
+#define IFX_CAN_N_BTR_BRP_MSK (0x3fu)
+
+/** \brief Offset for Ifx_CAN_N_BTR_Bits.BRP */
+#define IFX_CAN_N_BTR_BRP_OFF (0u)
+
+/** \brief Length for Ifx_CAN_N_BTR_Bits.DIV8 */
+#define IFX_CAN_N_BTR_DIV8_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_N_BTR_Bits.DIV8 */
+#define IFX_CAN_N_BTR_DIV8_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_N_BTR_Bits.DIV8 */
+#define IFX_CAN_N_BTR_DIV8_OFF (15u)
+
+/** \brief Length for Ifx_CAN_N_BTR_Bits.SJW */
+#define IFX_CAN_N_BTR_SJW_LEN (2u)
+
+/** \brief Mask for Ifx_CAN_N_BTR_Bits.SJW */
+#define IFX_CAN_N_BTR_SJW_MSK (0x3u)
+
+/** \brief Offset for Ifx_CAN_N_BTR_Bits.SJW */
+#define IFX_CAN_N_BTR_SJW_OFF (6u)
+
+/** \brief Length for Ifx_CAN_N_BTR_Bits.TSEG1 */
+#define IFX_CAN_N_BTR_TSEG1_LEN (4u)
+
+/** \brief Mask for Ifx_CAN_N_BTR_Bits.TSEG1 */
+#define IFX_CAN_N_BTR_TSEG1_MSK (0xfu)
+
+/** \brief Offset for Ifx_CAN_N_BTR_Bits.TSEG1 */
+#define IFX_CAN_N_BTR_TSEG1_OFF (8u)
+
+/** \brief Length for Ifx_CAN_N_BTR_Bits.TSEG2 */
+#define IFX_CAN_N_BTR_TSEG2_LEN (3u)
+
+/** \brief Mask for Ifx_CAN_N_BTR_Bits.TSEG2 */
+#define IFX_CAN_N_BTR_TSEG2_MSK (0x7u)
+
+/** \brief Offset for Ifx_CAN_N_BTR_Bits.TSEG2 */
+#define IFX_CAN_N_BTR_TSEG2_OFF (12u)
+
+/** \brief Length for Ifx_CAN_N_CR_Bits.ALIE */
+#define IFX_CAN_N_CR_ALIE_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_N_CR_Bits.ALIE */
+#define IFX_CAN_N_CR_ALIE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_N_CR_Bits.ALIE */
+#define IFX_CAN_N_CR_ALIE_OFF (3u)
+
+/** \brief Length for Ifx_CAN_N_CR_Bits.CALM */
+#define IFX_CAN_N_CR_CALM_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_N_CR_Bits.CALM */
+#define IFX_CAN_N_CR_CALM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_N_CR_Bits.CALM */
+#define IFX_CAN_N_CR_CALM_OFF (7u)
+
+/** \brief Length for Ifx_CAN_N_CR_Bits.CANDIS */
+#define IFX_CAN_N_CR_CANDIS_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_N_CR_Bits.CANDIS */
+#define IFX_CAN_N_CR_CANDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_N_CR_Bits.CANDIS */
+#define IFX_CAN_N_CR_CANDIS_OFF (4u)
+
+/** \brief Length for Ifx_CAN_N_CR_Bits.CCE */
+#define IFX_CAN_N_CR_CCE_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_N_CR_Bits.CCE */
+#define IFX_CAN_N_CR_CCE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_N_CR_Bits.CCE */
+#define IFX_CAN_N_CR_CCE_OFF (6u)
+
+/** \brief Length for Ifx_CAN_N_CR_Bits.FDEN */
+#define IFX_CAN_N_CR_FDEN_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_N_CR_Bits.FDEN */
+#define IFX_CAN_N_CR_FDEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_N_CR_Bits.FDEN */
+#define IFX_CAN_N_CR_FDEN_OFF (9u)
+
+/** \brief Length for Ifx_CAN_N_CR_Bits.INIT */
+#define IFX_CAN_N_CR_INIT_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_N_CR_Bits.INIT */
+#define IFX_CAN_N_CR_INIT_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_N_CR_Bits.INIT */
+#define IFX_CAN_N_CR_INIT_OFF (0u)
+
+/** \brief Length for Ifx_CAN_N_CR_Bits.LECIE */
+#define IFX_CAN_N_CR_LECIE_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_N_CR_Bits.LECIE */
+#define IFX_CAN_N_CR_LECIE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_N_CR_Bits.LECIE */
+#define IFX_CAN_N_CR_LECIE_OFF (2u)
+
+/** \brief Length for Ifx_CAN_N_CR_Bits.SUSEN */
+#define IFX_CAN_N_CR_SUSEN_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_N_CR_Bits.SUSEN */
+#define IFX_CAN_N_CR_SUSEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_N_CR_Bits.SUSEN */
+#define IFX_CAN_N_CR_SUSEN_OFF (8u)
+
+/** \brief Length for Ifx_CAN_N_CR_Bits.TRIE */
+#define IFX_CAN_N_CR_TRIE_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_N_CR_Bits.TRIE */
+#define IFX_CAN_N_CR_TRIE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_N_CR_Bits.TRIE */
+#define IFX_CAN_N_CR_TRIE_OFF (1u)
+
+/** \brief Length for Ifx_CAN_N_CR_Bits.TXDIS */
+#define IFX_CAN_N_CR_TXDIS_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_N_CR_Bits.TXDIS */
+#define IFX_CAN_N_CR_TXDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_N_CR_Bits.TXDIS */
+#define IFX_CAN_N_CR_TXDIS_OFF (5u)
+
+/** \brief Length for Ifx_CAN_N_ECNT_Bits.EWRNLVL */
+#define IFX_CAN_N_ECNT_EWRNLVL_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_N_ECNT_Bits.EWRNLVL */
+#define IFX_CAN_N_ECNT_EWRNLVL_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_N_ECNT_Bits.EWRNLVL */
+#define IFX_CAN_N_ECNT_EWRNLVL_OFF (16u)
+
+/** \brief Length for Ifx_CAN_N_ECNT_Bits.LEINC */
+#define IFX_CAN_N_ECNT_LEINC_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_N_ECNT_Bits.LEINC */
+#define IFX_CAN_N_ECNT_LEINC_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_N_ECNT_Bits.LEINC */
+#define IFX_CAN_N_ECNT_LEINC_OFF (25u)
+
+/** \brief Length for Ifx_CAN_N_ECNT_Bits.LETD */
+#define IFX_CAN_N_ECNT_LETD_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_N_ECNT_Bits.LETD */
+#define IFX_CAN_N_ECNT_LETD_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_N_ECNT_Bits.LETD */
+#define IFX_CAN_N_ECNT_LETD_OFF (24u)
+
+/** \brief Length for Ifx_CAN_N_ECNT_Bits.REC */
+#define IFX_CAN_N_ECNT_REC_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_N_ECNT_Bits.REC */
+#define IFX_CAN_N_ECNT_REC_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_N_ECNT_Bits.REC */
+#define IFX_CAN_N_ECNT_REC_OFF (0u)
+
+/** \brief Length for Ifx_CAN_N_ECNT_Bits.TEC */
+#define IFX_CAN_N_ECNT_TEC_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_N_ECNT_Bits.TEC */
+#define IFX_CAN_N_ECNT_TEC_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_N_ECNT_Bits.TEC */
+#define IFX_CAN_N_ECNT_TEC_OFF (8u)
+
+/** \brief Length for Ifx_CAN_N_FBTR_Bits.FBRP */
+#define IFX_CAN_N_FBTR_FBRP_LEN (6u)
+
+/** \brief Mask for Ifx_CAN_N_FBTR_Bits.FBRP */
+#define IFX_CAN_N_FBTR_FBRP_MSK (0x3fu)
+
+/** \brief Offset for Ifx_CAN_N_FBTR_Bits.FBRP */
+#define IFX_CAN_N_FBTR_FBRP_OFF (0u)
+
+/** \brief Length for Ifx_CAN_N_FBTR_Bits.FSJW */
+#define IFX_CAN_N_FBTR_FSJW_LEN (2u)
+
+/** \brief Mask for Ifx_CAN_N_FBTR_Bits.FSJW */
+#define IFX_CAN_N_FBTR_FSJW_MSK (0x3u)
+
+/** \brief Offset for Ifx_CAN_N_FBTR_Bits.FSJW */
+#define IFX_CAN_N_FBTR_FSJW_OFF (6u)
+
+/** \brief Length for Ifx_CAN_N_FBTR_Bits.FTSEG1 */
+#define IFX_CAN_N_FBTR_FTSEG1_LEN (4u)
+
+/** \brief Mask for Ifx_CAN_N_FBTR_Bits.FTSEG1 */
+#define IFX_CAN_N_FBTR_FTSEG1_MSK (0xfu)
+
+/** \brief Offset for Ifx_CAN_N_FBTR_Bits.FTSEG1 */
+#define IFX_CAN_N_FBTR_FTSEG1_OFF (8u)
+
+/** \brief Length for Ifx_CAN_N_FBTR_Bits.FTSEG2 */
+#define IFX_CAN_N_FBTR_FTSEG2_LEN (3u)
+
+/** \brief Mask for Ifx_CAN_N_FBTR_Bits.FTSEG2 */
+#define IFX_CAN_N_FBTR_FTSEG2_MSK (0x7u)
+
+/** \brief Offset for Ifx_CAN_N_FBTR_Bits.FTSEG2 */
+#define IFX_CAN_N_FBTR_FTSEG2_OFF (12u)
+
+/** \brief Length for Ifx_CAN_N_FCR_Bits.CFC */
+#define IFX_CAN_N_FCR_CFC_LEN (16u)
+
+/** \brief Mask for Ifx_CAN_N_FCR_Bits.CFC */
+#define IFX_CAN_N_FCR_CFC_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CAN_N_FCR_Bits.CFC */
+#define IFX_CAN_N_FCR_CFC_OFF (0u)
+
+/** \brief Length for Ifx_CAN_N_FCR_Bits.CFCIE */
+#define IFX_CAN_N_FCR_CFCIE_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_N_FCR_Bits.CFCIE */
+#define IFX_CAN_N_FCR_CFCIE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_N_FCR_Bits.CFCIE */
+#define IFX_CAN_N_FCR_CFCIE_OFF (22u)
+
+/** \brief Length for Ifx_CAN_N_FCR_Bits.CFCOV */
+#define IFX_CAN_N_FCR_CFCOV_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_N_FCR_Bits.CFCOV */
+#define IFX_CAN_N_FCR_CFCOV_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_N_FCR_Bits.CFCOV */
+#define IFX_CAN_N_FCR_CFCOV_OFF (23u)
+
+/** \brief Length for Ifx_CAN_N_FCR_Bits.CFMOD */
+#define IFX_CAN_N_FCR_CFMOD_LEN (2u)
+
+/** \brief Mask for Ifx_CAN_N_FCR_Bits.CFMOD */
+#define IFX_CAN_N_FCR_CFMOD_MSK (0x3u)
+
+/** \brief Offset for Ifx_CAN_N_FCR_Bits.CFMOD */
+#define IFX_CAN_N_FCR_CFMOD_OFF (19u)
+
+/** \brief Length for Ifx_CAN_N_FCR_Bits.CFSEL */
+#define IFX_CAN_N_FCR_CFSEL_LEN (3u)
+
+/** \brief Mask for Ifx_CAN_N_FCR_Bits.CFSEL */
+#define IFX_CAN_N_FCR_CFSEL_MSK (0x7u)
+
+/** \brief Offset for Ifx_CAN_N_FCR_Bits.CFSEL */
+#define IFX_CAN_N_FCR_CFSEL_OFF (16u)
+
+/** \brief Length for Ifx_CAN_N_IPR_Bits.ALINP */
+#define IFX_CAN_N_IPR_ALINP_LEN (4u)
+
+/** \brief Mask for Ifx_CAN_N_IPR_Bits.ALINP */
+#define IFX_CAN_N_IPR_ALINP_MSK (0xfu)
+
+/** \brief Offset for Ifx_CAN_N_IPR_Bits.ALINP */
+#define IFX_CAN_N_IPR_ALINP_OFF (0u)
+
+/** \brief Length for Ifx_CAN_N_IPR_Bits.CFCINP */
+#define IFX_CAN_N_IPR_CFCINP_LEN (4u)
+
+/** \brief Mask for Ifx_CAN_N_IPR_Bits.CFCINP */
+#define IFX_CAN_N_IPR_CFCINP_MSK (0xfu)
+
+/** \brief Offset for Ifx_CAN_N_IPR_Bits.CFCINP */
+#define IFX_CAN_N_IPR_CFCINP_OFF (12u)
+
+/** \brief Length for Ifx_CAN_N_IPR_Bits.LECINP */
+#define IFX_CAN_N_IPR_LECINP_LEN (4u)
+
+/** \brief Mask for Ifx_CAN_N_IPR_Bits.LECINP */
+#define IFX_CAN_N_IPR_LECINP_MSK (0xfu)
+
+/** \brief Offset for Ifx_CAN_N_IPR_Bits.LECINP */
+#define IFX_CAN_N_IPR_LECINP_OFF (4u)
+
+/** \brief Length for Ifx_CAN_N_IPR_Bits.TEINP */
+#define IFX_CAN_N_IPR_TEINP_LEN (4u)
+
+/** \brief Mask for Ifx_CAN_N_IPR_Bits.TEINP */
+#define IFX_CAN_N_IPR_TEINP_MSK (0xfu)
+
+/** \brief Offset for Ifx_CAN_N_IPR_Bits.TEINP */
+#define IFX_CAN_N_IPR_TEINP_OFF (16u)
+
+/** \brief Length for Ifx_CAN_N_IPR_Bits.TRINP */
+#define IFX_CAN_N_IPR_TRINP_LEN (4u)
+
+/** \brief Mask for Ifx_CAN_N_IPR_Bits.TRINP */
+#define IFX_CAN_N_IPR_TRINP_MSK (0xfu)
+
+/** \brief Offset for Ifx_CAN_N_IPR_Bits.TRINP */
+#define IFX_CAN_N_IPR_TRINP_OFF (8u)
+
+/** \brief Length for Ifx_CAN_N_PCR_Bits.LBM */
+#define IFX_CAN_N_PCR_LBM_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_N_PCR_Bits.LBM */
+#define IFX_CAN_N_PCR_LBM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_N_PCR_Bits.LBM */
+#define IFX_CAN_N_PCR_LBM_OFF (8u)
+
+/** \brief Length for Ifx_CAN_N_PCR_Bits.RXSEL */
+#define IFX_CAN_N_PCR_RXSEL_LEN (3u)
+
+/** \brief Mask for Ifx_CAN_N_PCR_Bits.RXSEL */
+#define IFX_CAN_N_PCR_RXSEL_MSK (0x7u)
+
+/** \brief Offset for Ifx_CAN_N_PCR_Bits.RXSEL */
+#define IFX_CAN_N_PCR_RXSEL_OFF (0u)
+
+/** \brief Length for Ifx_CAN_N_SR_Bits.ALERT */
+#define IFX_CAN_N_SR_ALERT_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_N_SR_Bits.ALERT */
+#define IFX_CAN_N_SR_ALERT_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_N_SR_Bits.ALERT */
+#define IFX_CAN_N_SR_ALERT_OFF (5u)
+
+/** \brief Length for Ifx_CAN_N_SR_Bits.BOFF */
+#define IFX_CAN_N_SR_BOFF_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_N_SR_Bits.BOFF */
+#define IFX_CAN_N_SR_BOFF_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_N_SR_Bits.BOFF */
+#define IFX_CAN_N_SR_BOFF_OFF (7u)
+
+/** \brief Length for Ifx_CAN_N_SR_Bits.EWRN */
+#define IFX_CAN_N_SR_EWRN_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_N_SR_Bits.EWRN */
+#define IFX_CAN_N_SR_EWRN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_N_SR_Bits.EWRN */
+#define IFX_CAN_N_SR_EWRN_OFF (6u)
+
+/** \brief Length for Ifx_CAN_N_SR_Bits.FLEC */
+#define IFX_CAN_N_SR_FLEC_LEN (3u)
+
+/** \brief Mask for Ifx_CAN_N_SR_Bits.FLEC */
+#define IFX_CAN_N_SR_FLEC_MSK (0x7u)
+
+/** \brief Offset for Ifx_CAN_N_SR_Bits.FLEC */
+#define IFX_CAN_N_SR_FLEC_OFF (12u)
+
+/** \brief Length for Ifx_CAN_N_SR_Bits.LEC */
+#define IFX_CAN_N_SR_LEC_LEN (3u)
+
+/** \brief Mask for Ifx_CAN_N_SR_Bits.LEC */
+#define IFX_CAN_N_SR_LEC_MSK (0x7u)
+
+/** \brief Offset for Ifx_CAN_N_SR_Bits.LEC */
+#define IFX_CAN_N_SR_LEC_OFF (0u)
+
+/** \brief Length for Ifx_CAN_N_SR_Bits.LLE */
+#define IFX_CAN_N_SR_LLE_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_N_SR_Bits.LLE */
+#define IFX_CAN_N_SR_LLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_N_SR_Bits.LLE */
+#define IFX_CAN_N_SR_LLE_OFF (8u)
+
+/** \brief Length for Ifx_CAN_N_SR_Bits.LOE */
+#define IFX_CAN_N_SR_LOE_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_N_SR_Bits.LOE */
+#define IFX_CAN_N_SR_LOE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_N_SR_Bits.LOE */
+#define IFX_CAN_N_SR_LOE_OFF (9u)
+
+/** \brief Length for Ifx_CAN_N_SR_Bits.RESI */
+#define IFX_CAN_N_SR_RESI_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_N_SR_Bits.RESI */
+#define IFX_CAN_N_SR_RESI_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_N_SR_Bits.RESI */
+#define IFX_CAN_N_SR_RESI_OFF (11u)
+
+/** \brief Length for Ifx_CAN_N_SR_Bits.RXOK */
+#define IFX_CAN_N_SR_RXOK_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_N_SR_Bits.RXOK */
+#define IFX_CAN_N_SR_RXOK_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_N_SR_Bits.RXOK */
+#define IFX_CAN_N_SR_RXOK_OFF (4u)
+
+/** \brief Length for Ifx_CAN_N_SR_Bits.SUSACK */
+#define IFX_CAN_N_SR_SUSACK_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_N_SR_Bits.SUSACK */
+#define IFX_CAN_N_SR_SUSACK_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_N_SR_Bits.SUSACK */
+#define IFX_CAN_N_SR_SUSACK_OFF (10u)
+
+/** \brief Length for Ifx_CAN_N_SR_Bits.TXOK */
+#define IFX_CAN_N_SR_TXOK_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_N_SR_Bits.TXOK */
+#define IFX_CAN_N_SR_TXOK_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_N_SR_Bits.TXOK */
+#define IFX_CAN_N_SR_TXOK_OFF (3u)
+
+/** \brief Length for Ifx_CAN_N_TCCR_Bits.TPSC */
+#define IFX_CAN_N_TCCR_TPSC_LEN (4u)
+
+/** \brief Mask for Ifx_CAN_N_TCCR_Bits.TPSC */
+#define IFX_CAN_N_TCCR_TPSC_MSK (0xfu)
+
+/** \brief Offset for Ifx_CAN_N_TCCR_Bits.TPSC */
+#define IFX_CAN_N_TCCR_TPSC_OFF (8u)
+
+/** \brief Length for Ifx_CAN_N_TCCR_Bits.TRIGSRC */
+#define IFX_CAN_N_TCCR_TRIGSRC_LEN (3u)
+
+/** \brief Mask for Ifx_CAN_N_TCCR_Bits.TRIGSRC */
+#define IFX_CAN_N_TCCR_TRIGSRC_MSK (0x7u)
+
+/** \brief Offset for Ifx_CAN_N_TCCR_Bits.TRIGSRC */
+#define IFX_CAN_N_TCCR_TRIGSRC_OFF (18u)
+
+/** \brief Length for Ifx_CAN_N_TDCR_Bits.TDC */
+#define IFX_CAN_N_TDCR_TDC_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_N_TDCR_Bits.TDC */
+#define IFX_CAN_N_TDCR_TDC_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_N_TDCR_Bits.TDC */
+#define IFX_CAN_N_TDCR_TDC_OFF (15u)
+
+/** \brief Length for Ifx_CAN_N_TDCR_Bits.TDCO */
+#define IFX_CAN_N_TDCR_TDCO_LEN (4u)
+
+/** \brief Mask for Ifx_CAN_N_TDCR_Bits.TDCO */
+#define IFX_CAN_N_TDCR_TDCO_MSK (0xfu)
+
+/** \brief Offset for Ifx_CAN_N_TDCR_Bits.TDCO */
+#define IFX_CAN_N_TDCR_TDCO_OFF (8u)
+
+/** \brief Length for Ifx_CAN_N_TDCR_Bits.TDCV */
+#define IFX_CAN_N_TDCR_TDCV_LEN (5u)
+
+/** \brief Mask for Ifx_CAN_N_TDCR_Bits.TDCV */
+#define IFX_CAN_N_TDCR_TDCV_MSK (0x1fu)
+
+/** \brief Offset for Ifx_CAN_N_TDCR_Bits.TDCV */
+#define IFX_CAN_N_TDCR_TDCV_OFF (0u)
+
+/** \brief Length for Ifx_CAN_N_TRTR_Bits.RELOAD */
+#define IFX_CAN_N_TRTR_RELOAD_LEN (16u)
+
+/** \brief Mask for Ifx_CAN_N_TRTR_Bits.RELOAD */
+#define IFX_CAN_N_TRTR_RELOAD_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CAN_N_TRTR_Bits.RELOAD */
+#define IFX_CAN_N_TRTR_RELOAD_OFF (0u)
+
+/** \brief Length for Ifx_CAN_N_TRTR_Bits.TE */
+#define IFX_CAN_N_TRTR_TE_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_N_TRTR_Bits.TE */
+#define IFX_CAN_N_TRTR_TE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_N_TRTR_Bits.TE */
+#define IFX_CAN_N_TRTR_TE_OFF (23u)
+
+/** \brief Length for Ifx_CAN_N_TRTR_Bits.TEIE */
+#define IFX_CAN_N_TRTR_TEIE_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_N_TRTR_Bits.TEIE */
+#define IFX_CAN_N_TRTR_TEIE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_N_TRTR_Bits.TEIE */
+#define IFX_CAN_N_TRTR_TEIE_OFF (22u)
+
+/** \brief Length for Ifx_CAN_N_TTTR_Bits.RELOAD */
+#define IFX_CAN_N_TTTR_RELOAD_LEN (16u)
+
+/** \brief Mask for Ifx_CAN_N_TTTR_Bits.RELOAD */
+#define IFX_CAN_N_TTTR_RELOAD_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CAN_N_TTTR_Bits.RELOAD */
+#define IFX_CAN_N_TTTR_RELOAD_OFF (0u)
+
+/** \brief Length for Ifx_CAN_N_TTTR_Bits.STRT */
+#define IFX_CAN_N_TTTR_STRT_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_N_TTTR_Bits.STRT */
+#define IFX_CAN_N_TTTR_STRT_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_N_TTTR_Bits.STRT */
+#define IFX_CAN_N_TTTR_STRT_OFF (24u)
+
+/** \brief Length for Ifx_CAN_N_TTTR_Bits.TXMO */
+#define IFX_CAN_N_TTTR_TXMO_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_N_TTTR_Bits.TXMO */
+#define IFX_CAN_N_TTTR_TXMO_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_N_TTTR_Bits.TXMO */
+#define IFX_CAN_N_TTTR_TXMO_OFF (16u)
+
+/** \brief Length for Ifx_CAN_OCS_Bits.SUS */
+#define IFX_CAN_OCS_SUS_LEN (4u)
+
+/** \brief Mask for Ifx_CAN_OCS_Bits.SUS */
+#define IFX_CAN_OCS_SUS_MSK (0xfu)
+
+/** \brief Offset for Ifx_CAN_OCS_Bits.SUS */
+#define IFX_CAN_OCS_SUS_OFF (24u)
+
+/** \brief Length for Ifx_CAN_OCS_Bits.SUS_P */
+#define IFX_CAN_OCS_SUS_P_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_OCS_Bits.SUS_P */
+#define IFX_CAN_OCS_SUS_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_OCS_Bits.SUS_P */
+#define IFX_CAN_OCS_SUS_P_OFF (28u)
+
+/** \brief Length for Ifx_CAN_OCS_Bits.SUSSTA */
+#define IFX_CAN_OCS_SUSSTA_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_OCS_Bits.SUSSTA */
+#define IFX_CAN_OCS_SUSSTA_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_OCS_Bits.SUSSTA */
+#define IFX_CAN_OCS_SUSSTA_OFF (29u)
+
+/** \brief Length for Ifx_CAN_OCS_Bits.TG_P */
+#define IFX_CAN_OCS_TG_P_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_OCS_Bits.TG_P */
+#define IFX_CAN_OCS_TG_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_OCS_Bits.TG_P */
+#define IFX_CAN_OCS_TG_P_OFF (3u)
+
+/** \brief Length for Ifx_CAN_OCS_Bits.TGB */
+#define IFX_CAN_OCS_TGB_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_OCS_Bits.TGB */
+#define IFX_CAN_OCS_TGB_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_OCS_Bits.TGB */
+#define IFX_CAN_OCS_TGB_OFF (2u)
+
+/** \brief Length for Ifx_CAN_OCS_Bits.TGS */
+#define IFX_CAN_OCS_TGS_LEN (2u)
+
+/** \brief Mask for Ifx_CAN_OCS_Bits.TGS */
+#define IFX_CAN_OCS_TGS_MSK (0x3u)
+
+/** \brief Offset for Ifx_CAN_OCS_Bits.TGS */
+#define IFX_CAN_OCS_TGS_OFF (0u)
+
+/** \brief Length for Ifx_CAN_PANCTR_Bits.BUSY */
+#define IFX_CAN_PANCTR_BUSY_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_PANCTR_Bits.BUSY */
+#define IFX_CAN_PANCTR_BUSY_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_PANCTR_Bits.BUSY */
+#define IFX_CAN_PANCTR_BUSY_OFF (8u)
+
+/** \brief Length for Ifx_CAN_PANCTR_Bits.PANAR1 */
+#define IFX_CAN_PANCTR_PANAR1_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_PANCTR_Bits.PANAR1 */
+#define IFX_CAN_PANCTR_PANAR1_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_PANCTR_Bits.PANAR1 */
+#define IFX_CAN_PANCTR_PANAR1_OFF (16u)
+
+/** \brief Length for Ifx_CAN_PANCTR_Bits.PANAR2 */
+#define IFX_CAN_PANCTR_PANAR2_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_PANCTR_Bits.PANAR2 */
+#define IFX_CAN_PANCTR_PANAR2_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_PANCTR_Bits.PANAR2 */
+#define IFX_CAN_PANCTR_PANAR2_OFF (24u)
+
+/** \brief Length for Ifx_CAN_PANCTR_Bits.PANCMD */
+#define IFX_CAN_PANCTR_PANCMD_LEN (8u)
+
+/** \brief Mask for Ifx_CAN_PANCTR_Bits.PANCMD */
+#define IFX_CAN_PANCTR_PANCMD_MSK (0xffu)
+
+/** \brief Offset for Ifx_CAN_PANCTR_Bits.PANCMD */
+#define IFX_CAN_PANCTR_PANCMD_OFF (0u)
+
+/** \brief Length for Ifx_CAN_PANCTR_Bits.RBUSY */
+#define IFX_CAN_PANCTR_RBUSY_LEN (1u)
+
+/** \brief Mask for Ifx_CAN_PANCTR_Bits.RBUSY */
+#define IFX_CAN_PANCTR_RBUSY_MSK (0x1u)
+
+/** \brief Offset for Ifx_CAN_PANCTR_Bits.RBUSY */
+#define IFX_CAN_PANCTR_RBUSY_OFF (9u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXCAN_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCan_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCan_reg.h
new file mode 100644
index 0000000..65501f9
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCan_reg.h
@@ -0,0 +1,33560 @@
+/**
+ * \file IfxCan_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Can_Cfg Can address
+ * \ingroup IfxLld_Can
+ *
+ * \defgroup IfxLld_Can_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Can_Cfg
+ *
+ * \defgroup IfxLld_Can_Cfg_Can 2-CAN
+ * \ingroup IfxLld_Can_Cfg
+ *
+ */
+#ifndef IFXCAN_REG_H
+#define IFXCAN_REG_H 1
+/******************************************************************************/
+#include "IfxCan_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Can_Cfg_BaseAddress
+ * \{ */
+
+/** \brief CAN object */
+#define MODULE_CAN /*lint --e(923)*/ (*(Ifx_CAN*)0xF0018000u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Can_Cfg_Can
+ * \{ */
+
+/** \brief FC, Access Enable Register 0 */
+#define CAN_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_CAN_ACCEN0*)0xF00180FCu)
+
+/** \brief F8, Access Enable Register 1 */
+#define CAN_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_CAN_ACCEN1*)0xF00180F8u)
+
+/** \brief 0, CAN Clock Control Register */
+#define CAN_CLC /*lint --e(923)*/ (*(volatile Ifx_CAN_CLC*)0xF0018000u)
+
+/** \brief C, CAN Fractional Divider Register */
+#define CAN_FDR /*lint --e(923)*/ (*(volatile Ifx_CAN_FDR*)0xF001800Cu)
+
+/** \brief 8, Module Identification Register */
+#define CAN_ID /*lint --e(923)*/ (*(volatile Ifx_CAN_ID*)0xF0018008u)
+
+/** \brief F4, Kernel Reset Register 0 */
+#define CAN_KRST0 /*lint --e(923)*/ (*(volatile Ifx_CAN_KRST0*)0xF00180F4u)
+
+/** \brief F0, Kernel Reset Register 1 */
+#define CAN_KRST1 /*lint --e(923)*/ (*(volatile Ifx_CAN_KRST1*)0xF00180F0u)
+
+/** \brief EC, Kernel Reset Status Clear Register */
+#define CAN_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_CAN_KRSTCLR*)0xF00180ECu)
+
+/** \brief 100, List Register */
+#define CAN_LIST0 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018100u)
+
+/** \brief 104, List Register */
+#define CAN_LIST1 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018104u)
+
+/** \brief 128, List Register */
+#define CAN_LIST10 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018128u)
+
+/** \brief 12C, List Register */
+#define CAN_LIST11 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF001812Cu)
+
+/** \brief 130, List Register */
+#define CAN_LIST12 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018130u)
+
+/** \brief 134, List Register */
+#define CAN_LIST13 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018134u)
+
+/** \brief 138, List Register */
+#define CAN_LIST14 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018138u)
+
+/** \brief 13C, List Register */
+#define CAN_LIST15 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF001813Cu)
+
+/** \brief 108, List Register */
+#define CAN_LIST2 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018108u)
+
+/** \brief 10C, List Register */
+#define CAN_LIST3 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF001810Cu)
+
+/** \brief 110, List Register */
+#define CAN_LIST4 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018110u)
+
+/** \brief 114, List Register */
+#define CAN_LIST5 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018114u)
+
+/** \brief 118, List Register */
+#define CAN_LIST6 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018118u)
+
+/** \brief 11C, List Register */
+#define CAN_LIST7 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF001811Cu)
+
+/** \brief 120, List Register */
+#define CAN_LIST8 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018120u)
+
+/** \brief 124, List Register */
+#define CAN_LIST9 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018124u)
+
+/** \brief 1C8, Module Control Register */
+#define CAN_MCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MCR*)0xF00181C8u)
+
+/** \brief 1D0, Measure Control Register */
+#define CAN_MECR /*lint --e(923)*/ (*(volatile Ifx_CAN_MECR*)0xF00181D0u)
+
+/** \brief 1D4, Measure Status Register */
+#define CAN_MESTAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MESTAT*)0xF00181D4u)
+
+/** \brief 1CC, Module Interrupt Trigger Register */
+#define CAN_MITR /*lint --e(923)*/ (*(volatile Ifx_CAN_MITR*)0xF00181CCu)
+
+/** \brief 100C, Message Object Acceptance Mask Register */
+#define CAN_MO0_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001900Cu)
+
+/** Alias (User Manual Name) for CAN_MO0_AMR.
+* To use register names with standard convension, please use CAN_MO0_AMR.
+*/
+#define CAN_MOAMR0 (CAN_MO0_AMR)
+
+/** \brief 1018, Message Object Arbitration Register */
+#define CAN_MO0_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019018u)
+
+/** Alias (User Manual Name) for CAN_MO0_AR.
+* To use register names with standard convension, please use CAN_MO0_AR.
+*/
+#define CAN_MOAR0 (CAN_MO0_AR)
+
+/** \brief 101C, Message Object Control Register */
+#define CAN_MO0_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001901Cu)
+
+/** Alias (User Manual Name) for CAN_MO0_CTR.
+* To use register names with standard convension, please use CAN_MO0_CTR.
+*/
+#define CAN_MOCTR0 (CAN_MO0_CTR)
+
+/** \brief 1014, Message Object Data Register High */
+#define CAN_MO0_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019014u)
+
+/** Alias (User Manual Name) for CAN_MO0_DATAH.
+* To use register names with standard convension, please use CAN_MO0_DATAH.
+*/
+#define CAN_MODATAH0 (CAN_MO0_DATAH)
+
+/** \brief 1010, Message Object Data Register Low */
+#define CAN_MO0_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019010u)
+
+/** Alias (User Manual Name) for CAN_MO0_DATAL.
+* To use register names with standard convension, please use CAN_MO0_DATAL.
+*/
+#define CAN_MODATAL0 (CAN_MO0_DATAL)
+
+/** \brief 1000, Message Object Function Control Register */
+#define CAN_MO0_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019000u)
+
+/** Alias (User Manual Name) for CAN_MO0_EDATA0.
+* To use register names with standard convension, please use CAN_MO0_EDATA0.
+*/
+#define CAN_EMO0DATA0 (CAN_MO0_EDATA0)
+
+/** \brief 1004, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO0_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019004u)
+
+/** Alias (User Manual Name) for CAN_MO0_EDATA1.
+* To use register names with standard convension, please use CAN_MO0_EDATA1.
+*/
+#define CAN_EMO0DATA1 (CAN_MO0_EDATA1)
+
+/** \brief 1008, Message Object Interrupt Pointer Register */
+#define CAN_MO0_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019008u)
+
+/** Alias (User Manual Name) for CAN_MO0_EDATA2.
+* To use register names with standard convension, please use CAN_MO0_EDATA2.
+*/
+#define CAN_EMO0DATA2 (CAN_MO0_EDATA2)
+
+/** \brief 100C, Message Object Acceptance Mask Register */
+#define CAN_MO0_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001900Cu)
+
+/** Alias (User Manual Name) for CAN_MO0_EDATA3.
+* To use register names with standard convension, please use CAN_MO0_EDATA3.
+*/
+#define CAN_EMO0DATA3 (CAN_MO0_EDATA3)
+
+/** \brief 1010, Message Object Data Register Low */
+#define CAN_MO0_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019010u)
+
+/** Alias (User Manual Name) for CAN_MO0_EDATA4.
+* To use register names with standard convension, please use CAN_MO0_EDATA4.
+*/
+#define CAN_EMO0DATA4 (CAN_MO0_EDATA4)
+
+/** \brief 1014, Message Object Data Register High */
+#define CAN_MO0_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019014u)
+
+/** Alias (User Manual Name) for CAN_MO0_EDATA5.
+* To use register names with standard convension, please use CAN_MO0_EDATA5.
+*/
+#define CAN_EMO0DATA5 (CAN_MO0_EDATA5)
+
+/** \brief 1018, Message Object Arbitration Register */
+#define CAN_MO0_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019018u)
+
+/** Alias (User Manual Name) for CAN_MO0_EDATA6.
+* To use register names with standard convension, please use CAN_MO0_EDATA6.
+*/
+#define CAN_EMO0DATA6 (CAN_MO0_EDATA6)
+
+/** \brief 1000, Message Object Function Control Register */
+#define CAN_MO0_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019000u)
+
+/** Alias (User Manual Name) for CAN_MO0_FCR.
+* To use register names with standard convension, please use CAN_MO0_FCR.
+*/
+#define CAN_MOFCR0 (CAN_MO0_FCR)
+
+/** \brief 1004, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO0_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019004u)
+
+/** Alias (User Manual Name) for CAN_MO0_FGPR.
+* To use register names with standard convension, please use CAN_MO0_FGPR.
+*/
+#define CAN_MOFGPR0 (CAN_MO0_FGPR)
+
+/** \brief 1008, Message Object Interrupt Pointer Register */
+#define CAN_MO0_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019008u)
+
+/** Alias (User Manual Name) for CAN_MO0_IPR.
+* To use register names with standard convension, please use CAN_MO0_IPR.
+*/
+#define CAN_MOIPR0 (CAN_MO0_IPR)
+
+/** \brief 101C, Message Object Control Register */
+#define CAN_MO0_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001901Cu)
+
+/** Alias (User Manual Name) for CAN_MO0_STAT.
+* To use register names with standard convension, please use CAN_MO0_STAT.
+*/
+#define CAN_MOSTAT0 (CAN_MO0_STAT)
+
+/** \brief 1C8C, Message Object Acceptance Mask Register */
+#define CAN_MO100_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019C8Cu)
+
+/** Alias (User Manual Name) for CAN_MO100_AMR.
+* To use register names with standard convension, please use CAN_MO100_AMR.
+*/
+#define CAN_MOAMR100 (CAN_MO100_AMR)
+
+/** \brief 1C98, Message Object Arbitration Register */
+#define CAN_MO100_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019C98u)
+
+/** Alias (User Manual Name) for CAN_MO100_AR.
+* To use register names with standard convension, please use CAN_MO100_AR.
+*/
+#define CAN_MOAR100 (CAN_MO100_AR)
+
+/** \brief 1C9C, Message Object Control Register */
+#define CAN_MO100_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019C9Cu)
+
+/** Alias (User Manual Name) for CAN_MO100_CTR.
+* To use register names with standard convension, please use CAN_MO100_CTR.
+*/
+#define CAN_MOCTR100 (CAN_MO100_CTR)
+
+/** \brief 1C94, Message Object Data Register High */
+#define CAN_MO100_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019C94u)
+
+/** Alias (User Manual Name) for CAN_MO100_DATAH.
+* To use register names with standard convension, please use CAN_MO100_DATAH.
+*/
+#define CAN_MODATAH100 (CAN_MO100_DATAH)
+
+/** \brief 1C90, Message Object Data Register Low */
+#define CAN_MO100_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019C90u)
+
+/** Alias (User Manual Name) for CAN_MO100_DATAL.
+* To use register names with standard convension, please use CAN_MO100_DATAL.
+*/
+#define CAN_MODATAL100 (CAN_MO100_DATAL)
+
+/** \brief 1C80, Message Object Function Control Register */
+#define CAN_MO100_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019C80u)
+
+/** Alias (User Manual Name) for CAN_MO100_EDATA0.
+* To use register names with standard convension, please use CAN_MO100_EDATA0.
+*/
+#define CAN_EMO100DATA0 (CAN_MO100_EDATA0)
+
+/** \brief 1C84, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO100_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019C84u)
+
+/** Alias (User Manual Name) for CAN_MO100_EDATA1.
+* To use register names with standard convension, please use CAN_MO100_EDATA1.
+*/
+#define CAN_EMO100DATA1 (CAN_MO100_EDATA1)
+
+/** \brief 1C88, Message Object Interrupt Pointer Register */
+#define CAN_MO100_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019C88u)
+
+/** Alias (User Manual Name) for CAN_MO100_EDATA2.
+* To use register names with standard convension, please use CAN_MO100_EDATA2.
+*/
+#define CAN_EMO100DATA2 (CAN_MO100_EDATA2)
+
+/** \brief 1C8C, Message Object Acceptance Mask Register */
+#define CAN_MO100_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019C8Cu)
+
+/** Alias (User Manual Name) for CAN_MO100_EDATA3.
+* To use register names with standard convension, please use CAN_MO100_EDATA3.
+*/
+#define CAN_EMO100DATA3 (CAN_MO100_EDATA3)
+
+/** \brief 1C90, Message Object Data Register Low */
+#define CAN_MO100_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019C90u)
+
+/** Alias (User Manual Name) for CAN_MO100_EDATA4.
+* To use register names with standard convension, please use CAN_MO100_EDATA4.
+*/
+#define CAN_EMO100DATA4 (CAN_MO100_EDATA4)
+
+/** \brief 1C94, Message Object Data Register High */
+#define CAN_MO100_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019C94u)
+
+/** Alias (User Manual Name) for CAN_MO100_EDATA5.
+* To use register names with standard convension, please use CAN_MO100_EDATA5.
+*/
+#define CAN_EMO100DATA5 (CAN_MO100_EDATA5)
+
+/** \brief 1C98, Message Object Arbitration Register */
+#define CAN_MO100_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019C98u)
+
+/** Alias (User Manual Name) for CAN_MO100_EDATA6.
+* To use register names with standard convension, please use CAN_MO100_EDATA6.
+*/
+#define CAN_EMO100DATA6 (CAN_MO100_EDATA6)
+
+/** \brief 1C80, Message Object Function Control Register */
+#define CAN_MO100_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019C80u)
+
+/** Alias (User Manual Name) for CAN_MO100_FCR.
+* To use register names with standard convension, please use CAN_MO100_FCR.
+*/
+#define CAN_MOFCR100 (CAN_MO100_FCR)
+
+/** \brief 1C84, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO100_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019C84u)
+
+/** Alias (User Manual Name) for CAN_MO100_FGPR.
+* To use register names with standard convension, please use CAN_MO100_FGPR.
+*/
+#define CAN_MOFGPR100 (CAN_MO100_FGPR)
+
+/** \brief 1C88, Message Object Interrupt Pointer Register */
+#define CAN_MO100_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019C88u)
+
+/** Alias (User Manual Name) for CAN_MO100_IPR.
+* To use register names with standard convension, please use CAN_MO100_IPR.
+*/
+#define CAN_MOIPR100 (CAN_MO100_IPR)
+
+/** \brief 1C9C, Message Object Control Register */
+#define CAN_MO100_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019C9Cu)
+
+/** Alias (User Manual Name) for CAN_MO100_STAT.
+* To use register names with standard convension, please use CAN_MO100_STAT.
+*/
+#define CAN_MOSTAT100 (CAN_MO100_STAT)
+
+/** \brief 1CAC, Message Object Acceptance Mask Register */
+#define CAN_MO101_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019CACu)
+
+/** Alias (User Manual Name) for CAN_MO101_AMR.
+* To use register names with standard convension, please use CAN_MO101_AMR.
+*/
+#define CAN_MOAMR101 (CAN_MO101_AMR)
+
+/** \brief 1CB8, Message Object Arbitration Register */
+#define CAN_MO101_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019CB8u)
+
+/** Alias (User Manual Name) for CAN_MO101_AR.
+* To use register names with standard convension, please use CAN_MO101_AR.
+*/
+#define CAN_MOAR101 (CAN_MO101_AR)
+
+/** \brief 1CBC, Message Object Control Register */
+#define CAN_MO101_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019CBCu)
+
+/** Alias (User Manual Name) for CAN_MO101_CTR.
+* To use register names with standard convension, please use CAN_MO101_CTR.
+*/
+#define CAN_MOCTR101 (CAN_MO101_CTR)
+
+/** \brief 1CB4, Message Object Data Register High */
+#define CAN_MO101_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019CB4u)
+
+/** Alias (User Manual Name) for CAN_MO101_DATAH.
+* To use register names with standard convension, please use CAN_MO101_DATAH.
+*/
+#define CAN_MODATAH101 (CAN_MO101_DATAH)
+
+/** \brief 1CB0, Message Object Data Register Low */
+#define CAN_MO101_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019CB0u)
+
+/** Alias (User Manual Name) for CAN_MO101_DATAL.
+* To use register names with standard convension, please use CAN_MO101_DATAL.
+*/
+#define CAN_MODATAL101 (CAN_MO101_DATAL)
+
+/** \brief 1CA0, Message Object Function Control Register */
+#define CAN_MO101_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019CA0u)
+
+/** Alias (User Manual Name) for CAN_MO101_EDATA0.
+* To use register names with standard convension, please use CAN_MO101_EDATA0.
+*/
+#define CAN_EMO101DATA0 (CAN_MO101_EDATA0)
+
+/** \brief 1CA4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO101_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019CA4u)
+
+/** Alias (User Manual Name) for CAN_MO101_EDATA1.
+* To use register names with standard convension, please use CAN_MO101_EDATA1.
+*/
+#define CAN_EMO101DATA1 (CAN_MO101_EDATA1)
+
+/** \brief 1CA8, Message Object Interrupt Pointer Register */
+#define CAN_MO101_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019CA8u)
+
+/** Alias (User Manual Name) for CAN_MO101_EDATA2.
+* To use register names with standard convension, please use CAN_MO101_EDATA2.
+*/
+#define CAN_EMO101DATA2 (CAN_MO101_EDATA2)
+
+/** \brief 1CAC, Message Object Acceptance Mask Register */
+#define CAN_MO101_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019CACu)
+
+/** Alias (User Manual Name) for CAN_MO101_EDATA3.
+* To use register names with standard convension, please use CAN_MO101_EDATA3.
+*/
+#define CAN_EMO101DATA3 (CAN_MO101_EDATA3)
+
+/** \brief 1CB0, Message Object Data Register Low */
+#define CAN_MO101_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019CB0u)
+
+/** Alias (User Manual Name) for CAN_MO101_EDATA4.
+* To use register names with standard convension, please use CAN_MO101_EDATA4.
+*/
+#define CAN_EMO101DATA4 (CAN_MO101_EDATA4)
+
+/** \brief 1CB4, Message Object Data Register High */
+#define CAN_MO101_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019CB4u)
+
+/** Alias (User Manual Name) for CAN_MO101_EDATA5.
+* To use register names with standard convension, please use CAN_MO101_EDATA5.
+*/
+#define CAN_EMO101DATA5 (CAN_MO101_EDATA5)
+
+/** \brief 1CB8, Message Object Arbitration Register */
+#define CAN_MO101_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019CB8u)
+
+/** Alias (User Manual Name) for CAN_MO101_EDATA6.
+* To use register names with standard convension, please use CAN_MO101_EDATA6.
+*/
+#define CAN_EMO101DATA6 (CAN_MO101_EDATA6)
+
+/** \brief 1CA0, Message Object Function Control Register */
+#define CAN_MO101_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019CA0u)
+
+/** Alias (User Manual Name) for CAN_MO101_FCR.
+* To use register names with standard convension, please use CAN_MO101_FCR.
+*/
+#define CAN_MOFCR101 (CAN_MO101_FCR)
+
+/** \brief 1CA4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO101_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019CA4u)
+
+/** Alias (User Manual Name) for CAN_MO101_FGPR.
+* To use register names with standard convension, please use CAN_MO101_FGPR.
+*/
+#define CAN_MOFGPR101 (CAN_MO101_FGPR)
+
+/** \brief 1CA8, Message Object Interrupt Pointer Register */
+#define CAN_MO101_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019CA8u)
+
+/** Alias (User Manual Name) for CAN_MO101_IPR.
+* To use register names with standard convension, please use CAN_MO101_IPR.
+*/
+#define CAN_MOIPR101 (CAN_MO101_IPR)
+
+/** \brief 1CBC, Message Object Control Register */
+#define CAN_MO101_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019CBCu)
+
+/** Alias (User Manual Name) for CAN_MO101_STAT.
+* To use register names with standard convension, please use CAN_MO101_STAT.
+*/
+#define CAN_MOSTAT101 (CAN_MO101_STAT)
+
+/** \brief 1CCC, Message Object Acceptance Mask Register */
+#define CAN_MO102_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019CCCu)
+
+/** Alias (User Manual Name) for CAN_MO102_AMR.
+* To use register names with standard convension, please use CAN_MO102_AMR.
+*/
+#define CAN_MOAMR102 (CAN_MO102_AMR)
+
+/** \brief 1CD8, Message Object Arbitration Register */
+#define CAN_MO102_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019CD8u)
+
+/** Alias (User Manual Name) for CAN_MO102_AR.
+* To use register names with standard convension, please use CAN_MO102_AR.
+*/
+#define CAN_MOAR102 (CAN_MO102_AR)
+
+/** \brief 1CDC, Message Object Control Register */
+#define CAN_MO102_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019CDCu)
+
+/** Alias (User Manual Name) for CAN_MO102_CTR.
+* To use register names with standard convension, please use CAN_MO102_CTR.
+*/
+#define CAN_MOCTR102 (CAN_MO102_CTR)
+
+/** \brief 1CD4, Message Object Data Register High */
+#define CAN_MO102_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019CD4u)
+
+/** Alias (User Manual Name) for CAN_MO102_DATAH.
+* To use register names with standard convension, please use CAN_MO102_DATAH.
+*/
+#define CAN_MODATAH102 (CAN_MO102_DATAH)
+
+/** \brief 1CD0, Message Object Data Register Low */
+#define CAN_MO102_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019CD0u)
+
+/** Alias (User Manual Name) for CAN_MO102_DATAL.
+* To use register names with standard convension, please use CAN_MO102_DATAL.
+*/
+#define CAN_MODATAL102 (CAN_MO102_DATAL)
+
+/** \brief 1CC0, Message Object Function Control Register */
+#define CAN_MO102_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019CC0u)
+
+/** Alias (User Manual Name) for CAN_MO102_EDATA0.
+* To use register names with standard convension, please use CAN_MO102_EDATA0.
+*/
+#define CAN_EMO102DATA0 (CAN_MO102_EDATA0)
+
+/** \brief 1CC4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO102_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019CC4u)
+
+/** Alias (User Manual Name) for CAN_MO102_EDATA1.
+* To use register names with standard convension, please use CAN_MO102_EDATA1.
+*/
+#define CAN_EMO102DATA1 (CAN_MO102_EDATA1)
+
+/** \brief 1CC8, Message Object Interrupt Pointer Register */
+#define CAN_MO102_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019CC8u)
+
+/** Alias (User Manual Name) for CAN_MO102_EDATA2.
+* To use register names with standard convension, please use CAN_MO102_EDATA2.
+*/
+#define CAN_EMO102DATA2 (CAN_MO102_EDATA2)
+
+/** \brief 1CCC, Message Object Acceptance Mask Register */
+#define CAN_MO102_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019CCCu)
+
+/** Alias (User Manual Name) for CAN_MO102_EDATA3.
+* To use register names with standard convension, please use CAN_MO102_EDATA3.
+*/
+#define CAN_EMO102DATA3 (CAN_MO102_EDATA3)
+
+/** \brief 1CD0, Message Object Data Register Low */
+#define CAN_MO102_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019CD0u)
+
+/** Alias (User Manual Name) for CAN_MO102_EDATA4.
+* To use register names with standard convension, please use CAN_MO102_EDATA4.
+*/
+#define CAN_EMO102DATA4 (CAN_MO102_EDATA4)
+
+/** \brief 1CD4, Message Object Data Register High */
+#define CAN_MO102_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019CD4u)
+
+/** Alias (User Manual Name) for CAN_MO102_EDATA5.
+* To use register names with standard convension, please use CAN_MO102_EDATA5.
+*/
+#define CAN_EMO102DATA5 (CAN_MO102_EDATA5)
+
+/** \brief 1CD8, Message Object Arbitration Register */
+#define CAN_MO102_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019CD8u)
+
+/** Alias (User Manual Name) for CAN_MO102_EDATA6.
+* To use register names with standard convension, please use CAN_MO102_EDATA6.
+*/
+#define CAN_EMO102DATA6 (CAN_MO102_EDATA6)
+
+/** \brief 1CC0, Message Object Function Control Register */
+#define CAN_MO102_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019CC0u)
+
+/** Alias (User Manual Name) for CAN_MO102_FCR.
+* To use register names with standard convension, please use CAN_MO102_FCR.
+*/
+#define CAN_MOFCR102 (CAN_MO102_FCR)
+
+/** \brief 1CC4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO102_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019CC4u)
+
+/** Alias (User Manual Name) for CAN_MO102_FGPR.
+* To use register names with standard convension, please use CAN_MO102_FGPR.
+*/
+#define CAN_MOFGPR102 (CAN_MO102_FGPR)
+
+/** \brief 1CC8, Message Object Interrupt Pointer Register */
+#define CAN_MO102_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019CC8u)
+
+/** Alias (User Manual Name) for CAN_MO102_IPR.
+* To use register names with standard convension, please use CAN_MO102_IPR.
+*/
+#define CAN_MOIPR102 (CAN_MO102_IPR)
+
+/** \brief 1CDC, Message Object Control Register */
+#define CAN_MO102_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019CDCu)
+
+/** Alias (User Manual Name) for CAN_MO102_STAT.
+* To use register names with standard convension, please use CAN_MO102_STAT.
+*/
+#define CAN_MOSTAT102 (CAN_MO102_STAT)
+
+/** \brief 1CEC, Message Object Acceptance Mask Register */
+#define CAN_MO103_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019CECu)
+
+/** Alias (User Manual Name) for CAN_MO103_AMR.
+* To use register names with standard convension, please use CAN_MO103_AMR.
+*/
+#define CAN_MOAMR103 (CAN_MO103_AMR)
+
+/** \brief 1CF8, Message Object Arbitration Register */
+#define CAN_MO103_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019CF8u)
+
+/** Alias (User Manual Name) for CAN_MO103_AR.
+* To use register names with standard convension, please use CAN_MO103_AR.
+*/
+#define CAN_MOAR103 (CAN_MO103_AR)
+
+/** \brief 1CFC, Message Object Control Register */
+#define CAN_MO103_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019CFCu)
+
+/** Alias (User Manual Name) for CAN_MO103_CTR.
+* To use register names with standard convension, please use CAN_MO103_CTR.
+*/
+#define CAN_MOCTR103 (CAN_MO103_CTR)
+
+/** \brief 1CF4, Message Object Data Register High */
+#define CAN_MO103_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019CF4u)
+
+/** Alias (User Manual Name) for CAN_MO103_DATAH.
+* To use register names with standard convension, please use CAN_MO103_DATAH.
+*/
+#define CAN_MODATAH103 (CAN_MO103_DATAH)
+
+/** \brief 1CF0, Message Object Data Register Low */
+#define CAN_MO103_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019CF0u)
+
+/** Alias (User Manual Name) for CAN_MO103_DATAL.
+* To use register names with standard convension, please use CAN_MO103_DATAL.
+*/
+#define CAN_MODATAL103 (CAN_MO103_DATAL)
+
+/** \brief 1CE0, Message Object Function Control Register */
+#define CAN_MO103_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019CE0u)
+
+/** Alias (User Manual Name) for CAN_MO103_EDATA0.
+* To use register names with standard convension, please use CAN_MO103_EDATA0.
+*/
+#define CAN_EMO103DATA0 (CAN_MO103_EDATA0)
+
+/** \brief 1CE4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO103_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019CE4u)
+
+/** Alias (User Manual Name) for CAN_MO103_EDATA1.
+* To use register names with standard convension, please use CAN_MO103_EDATA1.
+*/
+#define CAN_EMO103DATA1 (CAN_MO103_EDATA1)
+
+/** \brief 1CE8, Message Object Interrupt Pointer Register */
+#define CAN_MO103_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019CE8u)
+
+/** Alias (User Manual Name) for CAN_MO103_EDATA2.
+* To use register names with standard convension, please use CAN_MO103_EDATA2.
+*/
+#define CAN_EMO103DATA2 (CAN_MO103_EDATA2)
+
+/** \brief 1CEC, Message Object Acceptance Mask Register */
+#define CAN_MO103_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019CECu)
+
+/** Alias (User Manual Name) for CAN_MO103_EDATA3.
+* To use register names with standard convension, please use CAN_MO103_EDATA3.
+*/
+#define CAN_EMO103DATA3 (CAN_MO103_EDATA3)
+
+/** \brief 1CF0, Message Object Data Register Low */
+#define CAN_MO103_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019CF0u)
+
+/** Alias (User Manual Name) for CAN_MO103_EDATA4.
+* To use register names with standard convension, please use CAN_MO103_EDATA4.
+*/
+#define CAN_EMO103DATA4 (CAN_MO103_EDATA4)
+
+/** \brief 1CF4, Message Object Data Register High */
+#define CAN_MO103_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019CF4u)
+
+/** Alias (User Manual Name) for CAN_MO103_EDATA5.
+* To use register names with standard convension, please use CAN_MO103_EDATA5.
+*/
+#define CAN_EMO103DATA5 (CAN_MO103_EDATA5)
+
+/** \brief 1CF8, Message Object Arbitration Register */
+#define CAN_MO103_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019CF8u)
+
+/** Alias (User Manual Name) for CAN_MO103_EDATA6.
+* To use register names with standard convension, please use CAN_MO103_EDATA6.
+*/
+#define CAN_EMO103DATA6 (CAN_MO103_EDATA6)
+
+/** \brief 1CE0, Message Object Function Control Register */
+#define CAN_MO103_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019CE0u)
+
+/** Alias (User Manual Name) for CAN_MO103_FCR.
+* To use register names with standard convension, please use CAN_MO103_FCR.
+*/
+#define CAN_MOFCR103 (CAN_MO103_FCR)
+
+/** \brief 1CE4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO103_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019CE4u)
+
+/** Alias (User Manual Name) for CAN_MO103_FGPR.
+* To use register names with standard convension, please use CAN_MO103_FGPR.
+*/
+#define CAN_MOFGPR103 (CAN_MO103_FGPR)
+
+/** \brief 1CE8, Message Object Interrupt Pointer Register */
+#define CAN_MO103_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019CE8u)
+
+/** Alias (User Manual Name) for CAN_MO103_IPR.
+* To use register names with standard convension, please use CAN_MO103_IPR.
+*/
+#define CAN_MOIPR103 (CAN_MO103_IPR)
+
+/** \brief 1CFC, Message Object Control Register */
+#define CAN_MO103_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019CFCu)
+
+/** Alias (User Manual Name) for CAN_MO103_STAT.
+* To use register names with standard convension, please use CAN_MO103_STAT.
+*/
+#define CAN_MOSTAT103 (CAN_MO103_STAT)
+
+/** \brief 1D0C, Message Object Acceptance Mask Register */
+#define CAN_MO104_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019D0Cu)
+
+/** Alias (User Manual Name) for CAN_MO104_AMR.
+* To use register names with standard convension, please use CAN_MO104_AMR.
+*/
+#define CAN_MOAMR104 (CAN_MO104_AMR)
+
+/** \brief 1D18, Message Object Arbitration Register */
+#define CAN_MO104_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019D18u)
+
+/** Alias (User Manual Name) for CAN_MO104_AR.
+* To use register names with standard convension, please use CAN_MO104_AR.
+*/
+#define CAN_MOAR104 (CAN_MO104_AR)
+
+/** \brief 1D1C, Message Object Control Register */
+#define CAN_MO104_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019D1Cu)
+
+/** Alias (User Manual Name) for CAN_MO104_CTR.
+* To use register names with standard convension, please use CAN_MO104_CTR.
+*/
+#define CAN_MOCTR104 (CAN_MO104_CTR)
+
+/** \brief 1D14, Message Object Data Register High */
+#define CAN_MO104_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019D14u)
+
+/** Alias (User Manual Name) for CAN_MO104_DATAH.
+* To use register names with standard convension, please use CAN_MO104_DATAH.
+*/
+#define CAN_MODATAH104 (CAN_MO104_DATAH)
+
+/** \brief 1D10, Message Object Data Register Low */
+#define CAN_MO104_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019D10u)
+
+/** Alias (User Manual Name) for CAN_MO104_DATAL.
+* To use register names with standard convension, please use CAN_MO104_DATAL.
+*/
+#define CAN_MODATAL104 (CAN_MO104_DATAL)
+
+/** \brief 1D00, Message Object Function Control Register */
+#define CAN_MO104_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019D00u)
+
+/** Alias (User Manual Name) for CAN_MO104_EDATA0.
+* To use register names with standard convension, please use CAN_MO104_EDATA0.
+*/
+#define CAN_EMO104DATA0 (CAN_MO104_EDATA0)
+
+/** \brief 1D04, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO104_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019D04u)
+
+/** Alias (User Manual Name) for CAN_MO104_EDATA1.
+* To use register names with standard convension, please use CAN_MO104_EDATA1.
+*/
+#define CAN_EMO104DATA1 (CAN_MO104_EDATA1)
+
+/** \brief 1D08, Message Object Interrupt Pointer Register */
+#define CAN_MO104_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019D08u)
+
+/** Alias (User Manual Name) for CAN_MO104_EDATA2.
+* To use register names with standard convension, please use CAN_MO104_EDATA2.
+*/
+#define CAN_EMO104DATA2 (CAN_MO104_EDATA2)
+
+/** \brief 1D0C, Message Object Acceptance Mask Register */
+#define CAN_MO104_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019D0Cu)
+
+/** Alias (User Manual Name) for CAN_MO104_EDATA3.
+* To use register names with standard convension, please use CAN_MO104_EDATA3.
+*/
+#define CAN_EMO104DATA3 (CAN_MO104_EDATA3)
+
+/** \brief 1D10, Message Object Data Register Low */
+#define CAN_MO104_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019D10u)
+
+/** Alias (User Manual Name) for CAN_MO104_EDATA4.
+* To use register names with standard convension, please use CAN_MO104_EDATA4.
+*/
+#define CAN_EMO104DATA4 (CAN_MO104_EDATA4)
+
+/** \brief 1D14, Message Object Data Register High */
+#define CAN_MO104_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019D14u)
+
+/** Alias (User Manual Name) for CAN_MO104_EDATA5.
+* To use register names with standard convension, please use CAN_MO104_EDATA5.
+*/
+#define CAN_EMO104DATA5 (CAN_MO104_EDATA5)
+
+/** \brief 1D18, Message Object Arbitration Register */
+#define CAN_MO104_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019D18u)
+
+/** Alias (User Manual Name) for CAN_MO104_EDATA6.
+* To use register names with standard convension, please use CAN_MO104_EDATA6.
+*/
+#define CAN_EMO104DATA6 (CAN_MO104_EDATA6)
+
+/** \brief 1D00, Message Object Function Control Register */
+#define CAN_MO104_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019D00u)
+
+/** Alias (User Manual Name) for CAN_MO104_FCR.
+* To use register names with standard convension, please use CAN_MO104_FCR.
+*/
+#define CAN_MOFCR104 (CAN_MO104_FCR)
+
+/** \brief 1D04, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO104_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019D04u)
+
+/** Alias (User Manual Name) for CAN_MO104_FGPR.
+* To use register names with standard convension, please use CAN_MO104_FGPR.
+*/
+#define CAN_MOFGPR104 (CAN_MO104_FGPR)
+
+/** \brief 1D08, Message Object Interrupt Pointer Register */
+#define CAN_MO104_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019D08u)
+
+/** Alias (User Manual Name) for CAN_MO104_IPR.
+* To use register names with standard convension, please use CAN_MO104_IPR.
+*/
+#define CAN_MOIPR104 (CAN_MO104_IPR)
+
+/** \brief 1D1C, Message Object Control Register */
+#define CAN_MO104_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019D1Cu)
+
+/** Alias (User Manual Name) for CAN_MO104_STAT.
+* To use register names with standard convension, please use CAN_MO104_STAT.
+*/
+#define CAN_MOSTAT104 (CAN_MO104_STAT)
+
+/** \brief 1D2C, Message Object Acceptance Mask Register */
+#define CAN_MO105_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019D2Cu)
+
+/** Alias (User Manual Name) for CAN_MO105_AMR.
+* To use register names with standard convension, please use CAN_MO105_AMR.
+*/
+#define CAN_MOAMR105 (CAN_MO105_AMR)
+
+/** \brief 1D38, Message Object Arbitration Register */
+#define CAN_MO105_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019D38u)
+
+/** Alias (User Manual Name) for CAN_MO105_AR.
+* To use register names with standard convension, please use CAN_MO105_AR.
+*/
+#define CAN_MOAR105 (CAN_MO105_AR)
+
+/** \brief 1D3C, Message Object Control Register */
+#define CAN_MO105_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019D3Cu)
+
+/** Alias (User Manual Name) for CAN_MO105_CTR.
+* To use register names with standard convension, please use CAN_MO105_CTR.
+*/
+#define CAN_MOCTR105 (CAN_MO105_CTR)
+
+/** \brief 1D34, Message Object Data Register High */
+#define CAN_MO105_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019D34u)
+
+/** Alias (User Manual Name) for CAN_MO105_DATAH.
+* To use register names with standard convension, please use CAN_MO105_DATAH.
+*/
+#define CAN_MODATAH105 (CAN_MO105_DATAH)
+
+/** \brief 1D30, Message Object Data Register Low */
+#define CAN_MO105_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019D30u)
+
+/** Alias (User Manual Name) for CAN_MO105_DATAL.
+* To use register names with standard convension, please use CAN_MO105_DATAL.
+*/
+#define CAN_MODATAL105 (CAN_MO105_DATAL)
+
+/** \brief 1D20, Message Object Function Control Register */
+#define CAN_MO105_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019D20u)
+
+/** Alias (User Manual Name) for CAN_MO105_EDATA0.
+* To use register names with standard convension, please use CAN_MO105_EDATA0.
+*/
+#define CAN_EMO105DATA0 (CAN_MO105_EDATA0)
+
+/** \brief 1D24, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO105_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019D24u)
+
+/** Alias (User Manual Name) for CAN_MO105_EDATA1.
+* To use register names with standard convension, please use CAN_MO105_EDATA1.
+*/
+#define CAN_EMO105DATA1 (CAN_MO105_EDATA1)
+
+/** \brief 1D28, Message Object Interrupt Pointer Register */
+#define CAN_MO105_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019D28u)
+
+/** Alias (User Manual Name) for CAN_MO105_EDATA2.
+* To use register names with standard convension, please use CAN_MO105_EDATA2.
+*/
+#define CAN_EMO105DATA2 (CAN_MO105_EDATA2)
+
+/** \brief 1D2C, Message Object Acceptance Mask Register */
+#define CAN_MO105_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019D2Cu)
+
+/** Alias (User Manual Name) for CAN_MO105_EDATA3.
+* To use register names with standard convension, please use CAN_MO105_EDATA3.
+*/
+#define CAN_EMO105DATA3 (CAN_MO105_EDATA3)
+
+/** \brief 1D30, Message Object Data Register Low */
+#define CAN_MO105_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019D30u)
+
+/** Alias (User Manual Name) for CAN_MO105_EDATA4.
+* To use register names with standard convension, please use CAN_MO105_EDATA4.
+*/
+#define CAN_EMO105DATA4 (CAN_MO105_EDATA4)
+
+/** \brief 1D34, Message Object Data Register High */
+#define CAN_MO105_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019D34u)
+
+/** Alias (User Manual Name) for CAN_MO105_EDATA5.
+* To use register names with standard convension, please use CAN_MO105_EDATA5.
+*/
+#define CAN_EMO105DATA5 (CAN_MO105_EDATA5)
+
+/** \brief 1D38, Message Object Arbitration Register */
+#define CAN_MO105_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019D38u)
+
+/** Alias (User Manual Name) for CAN_MO105_EDATA6.
+* To use register names with standard convension, please use CAN_MO105_EDATA6.
+*/
+#define CAN_EMO105DATA6 (CAN_MO105_EDATA6)
+
+/** \brief 1D20, Message Object Function Control Register */
+#define CAN_MO105_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019D20u)
+
+/** Alias (User Manual Name) for CAN_MO105_FCR.
+* To use register names with standard convension, please use CAN_MO105_FCR.
+*/
+#define CAN_MOFCR105 (CAN_MO105_FCR)
+
+/** \brief 1D24, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO105_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019D24u)
+
+/** Alias (User Manual Name) for CAN_MO105_FGPR.
+* To use register names with standard convension, please use CAN_MO105_FGPR.
+*/
+#define CAN_MOFGPR105 (CAN_MO105_FGPR)
+
+/** \brief 1D28, Message Object Interrupt Pointer Register */
+#define CAN_MO105_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019D28u)
+
+/** Alias (User Manual Name) for CAN_MO105_IPR.
+* To use register names with standard convension, please use CAN_MO105_IPR.
+*/
+#define CAN_MOIPR105 (CAN_MO105_IPR)
+
+/** \brief 1D3C, Message Object Control Register */
+#define CAN_MO105_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019D3Cu)
+
+/** Alias (User Manual Name) for CAN_MO105_STAT.
+* To use register names with standard convension, please use CAN_MO105_STAT.
+*/
+#define CAN_MOSTAT105 (CAN_MO105_STAT)
+
+/** \brief 1D4C, Message Object Acceptance Mask Register */
+#define CAN_MO106_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019D4Cu)
+
+/** Alias (User Manual Name) for CAN_MO106_AMR.
+* To use register names with standard convension, please use CAN_MO106_AMR.
+*/
+#define CAN_MOAMR106 (CAN_MO106_AMR)
+
+/** \brief 1D58, Message Object Arbitration Register */
+#define CAN_MO106_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019D58u)
+
+/** Alias (User Manual Name) for CAN_MO106_AR.
+* To use register names with standard convension, please use CAN_MO106_AR.
+*/
+#define CAN_MOAR106 (CAN_MO106_AR)
+
+/** \brief 1D5C, Message Object Control Register */
+#define CAN_MO106_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019D5Cu)
+
+/** Alias (User Manual Name) for CAN_MO106_CTR.
+* To use register names with standard convension, please use CAN_MO106_CTR.
+*/
+#define CAN_MOCTR106 (CAN_MO106_CTR)
+
+/** \brief 1D54, Message Object Data Register High */
+#define CAN_MO106_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019D54u)
+
+/** Alias (User Manual Name) for CAN_MO106_DATAH.
+* To use register names with standard convension, please use CAN_MO106_DATAH.
+*/
+#define CAN_MODATAH106 (CAN_MO106_DATAH)
+
+/** \brief 1D50, Message Object Data Register Low */
+#define CAN_MO106_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019D50u)
+
+/** Alias (User Manual Name) for CAN_MO106_DATAL.
+* To use register names with standard convension, please use CAN_MO106_DATAL.
+*/
+#define CAN_MODATAL106 (CAN_MO106_DATAL)
+
+/** \brief 1D40, Message Object Function Control Register */
+#define CAN_MO106_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019D40u)
+
+/** Alias (User Manual Name) for CAN_MO106_EDATA0.
+* To use register names with standard convension, please use CAN_MO106_EDATA0.
+*/
+#define CAN_EMO106DATA0 (CAN_MO106_EDATA0)
+
+/** \brief 1D44, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO106_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019D44u)
+
+/** Alias (User Manual Name) for CAN_MO106_EDATA1.
+* To use register names with standard convension, please use CAN_MO106_EDATA1.
+*/
+#define CAN_EMO106DATA1 (CAN_MO106_EDATA1)
+
+/** \brief 1D48, Message Object Interrupt Pointer Register */
+#define CAN_MO106_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019D48u)
+
+/** Alias (User Manual Name) for CAN_MO106_EDATA2.
+* To use register names with standard convension, please use CAN_MO106_EDATA2.
+*/
+#define CAN_EMO106DATA2 (CAN_MO106_EDATA2)
+
+/** \brief 1D4C, Message Object Acceptance Mask Register */
+#define CAN_MO106_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019D4Cu)
+
+/** Alias (User Manual Name) for CAN_MO106_EDATA3.
+* To use register names with standard convension, please use CAN_MO106_EDATA3.
+*/
+#define CAN_EMO106DATA3 (CAN_MO106_EDATA3)
+
+/** \brief 1D50, Message Object Data Register Low */
+#define CAN_MO106_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019D50u)
+
+/** Alias (User Manual Name) for CAN_MO106_EDATA4.
+* To use register names with standard convension, please use CAN_MO106_EDATA4.
+*/
+#define CAN_EMO106DATA4 (CAN_MO106_EDATA4)
+
+/** \brief 1D54, Message Object Data Register High */
+#define CAN_MO106_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019D54u)
+
+/** Alias (User Manual Name) for CAN_MO106_EDATA5.
+* To use register names with standard convension, please use CAN_MO106_EDATA5.
+*/
+#define CAN_EMO106DATA5 (CAN_MO106_EDATA5)
+
+/** \brief 1D58, Message Object Arbitration Register */
+#define CAN_MO106_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019D58u)
+
+/** Alias (User Manual Name) for CAN_MO106_EDATA6.
+* To use register names with standard convension, please use CAN_MO106_EDATA6.
+*/
+#define CAN_EMO106DATA6 (CAN_MO106_EDATA6)
+
+/** \brief 1D40, Message Object Function Control Register */
+#define CAN_MO106_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019D40u)
+
+/** Alias (User Manual Name) for CAN_MO106_FCR.
+* To use register names with standard convension, please use CAN_MO106_FCR.
+*/
+#define CAN_MOFCR106 (CAN_MO106_FCR)
+
+/** \brief 1D44, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO106_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019D44u)
+
+/** Alias (User Manual Name) for CAN_MO106_FGPR.
+* To use register names with standard convension, please use CAN_MO106_FGPR.
+*/
+#define CAN_MOFGPR106 (CAN_MO106_FGPR)
+
+/** \brief 1D48, Message Object Interrupt Pointer Register */
+#define CAN_MO106_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019D48u)
+
+/** Alias (User Manual Name) for CAN_MO106_IPR.
+* To use register names with standard convension, please use CAN_MO106_IPR.
+*/
+#define CAN_MOIPR106 (CAN_MO106_IPR)
+
+/** \brief 1D5C, Message Object Control Register */
+#define CAN_MO106_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019D5Cu)
+
+/** Alias (User Manual Name) for CAN_MO106_STAT.
+* To use register names with standard convension, please use CAN_MO106_STAT.
+*/
+#define CAN_MOSTAT106 (CAN_MO106_STAT)
+
+/** \brief 1D6C, Message Object Acceptance Mask Register */
+#define CAN_MO107_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019D6Cu)
+
+/** Alias (User Manual Name) for CAN_MO107_AMR.
+* To use register names with standard convension, please use CAN_MO107_AMR.
+*/
+#define CAN_MOAMR107 (CAN_MO107_AMR)
+
+/** \brief 1D78, Message Object Arbitration Register */
+#define CAN_MO107_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019D78u)
+
+/** Alias (User Manual Name) for CAN_MO107_AR.
+* To use register names with standard convension, please use CAN_MO107_AR.
+*/
+#define CAN_MOAR107 (CAN_MO107_AR)
+
+/** \brief 1D7C, Message Object Control Register */
+#define CAN_MO107_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019D7Cu)
+
+/** Alias (User Manual Name) for CAN_MO107_CTR.
+* To use register names with standard convension, please use CAN_MO107_CTR.
+*/
+#define CAN_MOCTR107 (CAN_MO107_CTR)
+
+/** \brief 1D74, Message Object Data Register High */
+#define CAN_MO107_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019D74u)
+
+/** Alias (User Manual Name) for CAN_MO107_DATAH.
+* To use register names with standard convension, please use CAN_MO107_DATAH.
+*/
+#define CAN_MODATAH107 (CAN_MO107_DATAH)
+
+/** \brief 1D70, Message Object Data Register Low */
+#define CAN_MO107_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019D70u)
+
+/** Alias (User Manual Name) for CAN_MO107_DATAL.
+* To use register names with standard convension, please use CAN_MO107_DATAL.
+*/
+#define CAN_MODATAL107 (CAN_MO107_DATAL)
+
+/** \brief 1D60, Message Object Function Control Register */
+#define CAN_MO107_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019D60u)
+
+/** Alias (User Manual Name) for CAN_MO107_EDATA0.
+* To use register names with standard convension, please use CAN_MO107_EDATA0.
+*/
+#define CAN_EMO107DATA0 (CAN_MO107_EDATA0)
+
+/** \brief 1D64, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO107_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019D64u)
+
+/** Alias (User Manual Name) for CAN_MO107_EDATA1.
+* To use register names with standard convension, please use CAN_MO107_EDATA1.
+*/
+#define CAN_EMO107DATA1 (CAN_MO107_EDATA1)
+
+/** \brief 1D68, Message Object Interrupt Pointer Register */
+#define CAN_MO107_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019D68u)
+
+/** Alias (User Manual Name) for CAN_MO107_EDATA2.
+* To use register names with standard convension, please use CAN_MO107_EDATA2.
+*/
+#define CAN_EMO107DATA2 (CAN_MO107_EDATA2)
+
+/** \brief 1D6C, Message Object Acceptance Mask Register */
+#define CAN_MO107_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019D6Cu)
+
+/** Alias (User Manual Name) for CAN_MO107_EDATA3.
+* To use register names with standard convension, please use CAN_MO107_EDATA3.
+*/
+#define CAN_EMO107DATA3 (CAN_MO107_EDATA3)
+
+/** \brief 1D70, Message Object Data Register Low */
+#define CAN_MO107_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019D70u)
+
+/** Alias (User Manual Name) for CAN_MO107_EDATA4.
+* To use register names with standard convension, please use CAN_MO107_EDATA4.
+*/
+#define CAN_EMO107DATA4 (CAN_MO107_EDATA4)
+
+/** \brief 1D74, Message Object Data Register High */
+#define CAN_MO107_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019D74u)
+
+/** Alias (User Manual Name) for CAN_MO107_EDATA5.
+* To use register names with standard convension, please use CAN_MO107_EDATA5.
+*/
+#define CAN_EMO107DATA5 (CAN_MO107_EDATA5)
+
+/** \brief 1D78, Message Object Arbitration Register */
+#define CAN_MO107_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019D78u)
+
+/** Alias (User Manual Name) for CAN_MO107_EDATA6.
+* To use register names with standard convension, please use CAN_MO107_EDATA6.
+*/
+#define CAN_EMO107DATA6 (CAN_MO107_EDATA6)
+
+/** \brief 1D60, Message Object Function Control Register */
+#define CAN_MO107_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019D60u)
+
+/** Alias (User Manual Name) for CAN_MO107_FCR.
+* To use register names with standard convension, please use CAN_MO107_FCR.
+*/
+#define CAN_MOFCR107 (CAN_MO107_FCR)
+
+/** \brief 1D64, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO107_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019D64u)
+
+/** Alias (User Manual Name) for CAN_MO107_FGPR.
+* To use register names with standard convension, please use CAN_MO107_FGPR.
+*/
+#define CAN_MOFGPR107 (CAN_MO107_FGPR)
+
+/** \brief 1D68, Message Object Interrupt Pointer Register */
+#define CAN_MO107_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019D68u)
+
+/** Alias (User Manual Name) for CAN_MO107_IPR.
+* To use register names with standard convension, please use CAN_MO107_IPR.
+*/
+#define CAN_MOIPR107 (CAN_MO107_IPR)
+
+/** \brief 1D7C, Message Object Control Register */
+#define CAN_MO107_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019D7Cu)
+
+/** Alias (User Manual Name) for CAN_MO107_STAT.
+* To use register names with standard convension, please use CAN_MO107_STAT.
+*/
+#define CAN_MOSTAT107 (CAN_MO107_STAT)
+
+/** \brief 1D8C, Message Object Acceptance Mask Register */
+#define CAN_MO108_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019D8Cu)
+
+/** Alias (User Manual Name) for CAN_MO108_AMR.
+* To use register names with standard convension, please use CAN_MO108_AMR.
+*/
+#define CAN_MOAMR108 (CAN_MO108_AMR)
+
+/** \brief 1D98, Message Object Arbitration Register */
+#define CAN_MO108_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019D98u)
+
+/** Alias (User Manual Name) for CAN_MO108_AR.
+* To use register names with standard convension, please use CAN_MO108_AR.
+*/
+#define CAN_MOAR108 (CAN_MO108_AR)
+
+/** \brief 1D9C, Message Object Control Register */
+#define CAN_MO108_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019D9Cu)
+
+/** Alias (User Manual Name) for CAN_MO108_CTR.
+* To use register names with standard convension, please use CAN_MO108_CTR.
+*/
+#define CAN_MOCTR108 (CAN_MO108_CTR)
+
+/** \brief 1D94, Message Object Data Register High */
+#define CAN_MO108_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019D94u)
+
+/** Alias (User Manual Name) for CAN_MO108_DATAH.
+* To use register names with standard convension, please use CAN_MO108_DATAH.
+*/
+#define CAN_MODATAH108 (CAN_MO108_DATAH)
+
+/** \brief 1D90, Message Object Data Register Low */
+#define CAN_MO108_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019D90u)
+
+/** Alias (User Manual Name) for CAN_MO108_DATAL.
+* To use register names with standard convension, please use CAN_MO108_DATAL.
+*/
+#define CAN_MODATAL108 (CAN_MO108_DATAL)
+
+/** \brief 1D80, Message Object Function Control Register */
+#define CAN_MO108_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019D80u)
+
+/** Alias (User Manual Name) for CAN_MO108_EDATA0.
+* To use register names with standard convension, please use CAN_MO108_EDATA0.
+*/
+#define CAN_EMO108DATA0 (CAN_MO108_EDATA0)
+
+/** \brief 1D84, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO108_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019D84u)
+
+/** Alias (User Manual Name) for CAN_MO108_EDATA1.
+* To use register names with standard convension, please use CAN_MO108_EDATA1.
+*/
+#define CAN_EMO108DATA1 (CAN_MO108_EDATA1)
+
+/** \brief 1D88, Message Object Interrupt Pointer Register */
+#define CAN_MO108_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019D88u)
+
+/** Alias (User Manual Name) for CAN_MO108_EDATA2.
+* To use register names with standard convension, please use CAN_MO108_EDATA2.
+*/
+#define CAN_EMO108DATA2 (CAN_MO108_EDATA2)
+
+/** \brief 1D8C, Message Object Acceptance Mask Register */
+#define CAN_MO108_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019D8Cu)
+
+/** Alias (User Manual Name) for CAN_MO108_EDATA3.
+* To use register names with standard convension, please use CAN_MO108_EDATA3.
+*/
+#define CAN_EMO108DATA3 (CAN_MO108_EDATA3)
+
+/** \brief 1D90, Message Object Data Register Low */
+#define CAN_MO108_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019D90u)
+
+/** Alias (User Manual Name) for CAN_MO108_EDATA4.
+* To use register names with standard convension, please use CAN_MO108_EDATA4.
+*/
+#define CAN_EMO108DATA4 (CAN_MO108_EDATA4)
+
+/** \brief 1D94, Message Object Data Register High */
+#define CAN_MO108_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019D94u)
+
+/** Alias (User Manual Name) for CAN_MO108_EDATA5.
+* To use register names with standard convension, please use CAN_MO108_EDATA5.
+*/
+#define CAN_EMO108DATA5 (CAN_MO108_EDATA5)
+
+/** \brief 1D98, Message Object Arbitration Register */
+#define CAN_MO108_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019D98u)
+
+/** Alias (User Manual Name) for CAN_MO108_EDATA6.
+* To use register names with standard convension, please use CAN_MO108_EDATA6.
+*/
+#define CAN_EMO108DATA6 (CAN_MO108_EDATA6)
+
+/** \brief 1D80, Message Object Function Control Register */
+#define CAN_MO108_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019D80u)
+
+/** Alias (User Manual Name) for CAN_MO108_FCR.
+* To use register names with standard convension, please use CAN_MO108_FCR.
+*/
+#define CAN_MOFCR108 (CAN_MO108_FCR)
+
+/** \brief 1D84, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO108_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019D84u)
+
+/** Alias (User Manual Name) for CAN_MO108_FGPR.
+* To use register names with standard convension, please use CAN_MO108_FGPR.
+*/
+#define CAN_MOFGPR108 (CAN_MO108_FGPR)
+
+/** \brief 1D88, Message Object Interrupt Pointer Register */
+#define CAN_MO108_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019D88u)
+
+/** Alias (User Manual Name) for CAN_MO108_IPR.
+* To use register names with standard convension, please use CAN_MO108_IPR.
+*/
+#define CAN_MOIPR108 (CAN_MO108_IPR)
+
+/** \brief 1D9C, Message Object Control Register */
+#define CAN_MO108_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019D9Cu)
+
+/** Alias (User Manual Name) for CAN_MO108_STAT.
+* To use register names with standard convension, please use CAN_MO108_STAT.
+*/
+#define CAN_MOSTAT108 (CAN_MO108_STAT)
+
+/** \brief 1DAC, Message Object Acceptance Mask Register */
+#define CAN_MO109_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019DACu)
+
+/** Alias (User Manual Name) for CAN_MO109_AMR.
+* To use register names with standard convension, please use CAN_MO109_AMR.
+*/
+#define CAN_MOAMR109 (CAN_MO109_AMR)
+
+/** \brief 1DB8, Message Object Arbitration Register */
+#define CAN_MO109_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019DB8u)
+
+/** Alias (User Manual Name) for CAN_MO109_AR.
+* To use register names with standard convension, please use CAN_MO109_AR.
+*/
+#define CAN_MOAR109 (CAN_MO109_AR)
+
+/** \brief 1DBC, Message Object Control Register */
+#define CAN_MO109_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019DBCu)
+
+/** Alias (User Manual Name) for CAN_MO109_CTR.
+* To use register names with standard convension, please use CAN_MO109_CTR.
+*/
+#define CAN_MOCTR109 (CAN_MO109_CTR)
+
+/** \brief 1DB4, Message Object Data Register High */
+#define CAN_MO109_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019DB4u)
+
+/** Alias (User Manual Name) for CAN_MO109_DATAH.
+* To use register names with standard convension, please use CAN_MO109_DATAH.
+*/
+#define CAN_MODATAH109 (CAN_MO109_DATAH)
+
+/** \brief 1DB0, Message Object Data Register Low */
+#define CAN_MO109_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019DB0u)
+
+/** Alias (User Manual Name) for CAN_MO109_DATAL.
+* To use register names with standard convension, please use CAN_MO109_DATAL.
+*/
+#define CAN_MODATAL109 (CAN_MO109_DATAL)
+
+/** \brief 1DA0, Message Object Function Control Register */
+#define CAN_MO109_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019DA0u)
+
+/** Alias (User Manual Name) for CAN_MO109_EDATA0.
+* To use register names with standard convension, please use CAN_MO109_EDATA0.
+*/
+#define CAN_EMO109DATA0 (CAN_MO109_EDATA0)
+
+/** \brief 1DA4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO109_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019DA4u)
+
+/** Alias (User Manual Name) for CAN_MO109_EDATA1.
+* To use register names with standard convension, please use CAN_MO109_EDATA1.
+*/
+#define CAN_EMO109DATA1 (CAN_MO109_EDATA1)
+
+/** \brief 1DA8, Message Object Interrupt Pointer Register */
+#define CAN_MO109_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019DA8u)
+
+/** Alias (User Manual Name) for CAN_MO109_EDATA2.
+* To use register names with standard convension, please use CAN_MO109_EDATA2.
+*/
+#define CAN_EMO109DATA2 (CAN_MO109_EDATA2)
+
+/** \brief 1DAC, Message Object Acceptance Mask Register */
+#define CAN_MO109_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019DACu)
+
+/** Alias (User Manual Name) for CAN_MO109_EDATA3.
+* To use register names with standard convension, please use CAN_MO109_EDATA3.
+*/
+#define CAN_EMO109DATA3 (CAN_MO109_EDATA3)
+
+/** \brief 1DB0, Message Object Data Register Low */
+#define CAN_MO109_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019DB0u)
+
+/** Alias (User Manual Name) for CAN_MO109_EDATA4.
+* To use register names with standard convension, please use CAN_MO109_EDATA4.
+*/
+#define CAN_EMO109DATA4 (CAN_MO109_EDATA4)
+
+/** \brief 1DB4, Message Object Data Register High */
+#define CAN_MO109_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019DB4u)
+
+/** Alias (User Manual Name) for CAN_MO109_EDATA5.
+* To use register names with standard convension, please use CAN_MO109_EDATA5.
+*/
+#define CAN_EMO109DATA5 (CAN_MO109_EDATA5)
+
+/** \brief 1DB8, Message Object Arbitration Register */
+#define CAN_MO109_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019DB8u)
+
+/** Alias (User Manual Name) for CAN_MO109_EDATA6.
+* To use register names with standard convension, please use CAN_MO109_EDATA6.
+*/
+#define CAN_EMO109DATA6 (CAN_MO109_EDATA6)
+
+/** \brief 1DA0, Message Object Function Control Register */
+#define CAN_MO109_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019DA0u)
+
+/** Alias (User Manual Name) for CAN_MO109_FCR.
+* To use register names with standard convension, please use CAN_MO109_FCR.
+*/
+#define CAN_MOFCR109 (CAN_MO109_FCR)
+
+/** \brief 1DA4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO109_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019DA4u)
+
+/** Alias (User Manual Name) for CAN_MO109_FGPR.
+* To use register names with standard convension, please use CAN_MO109_FGPR.
+*/
+#define CAN_MOFGPR109 (CAN_MO109_FGPR)
+
+/** \brief 1DA8, Message Object Interrupt Pointer Register */
+#define CAN_MO109_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019DA8u)
+
+/** Alias (User Manual Name) for CAN_MO109_IPR.
+* To use register names with standard convension, please use CAN_MO109_IPR.
+*/
+#define CAN_MOIPR109 (CAN_MO109_IPR)
+
+/** \brief 1DBC, Message Object Control Register */
+#define CAN_MO109_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019DBCu)
+
+/** Alias (User Manual Name) for CAN_MO109_STAT.
+* To use register names with standard convension, please use CAN_MO109_STAT.
+*/
+#define CAN_MOSTAT109 (CAN_MO109_STAT)
+
+/** \brief 114C, Message Object Acceptance Mask Register */
+#define CAN_MO10_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001914Cu)
+
+/** Alias (User Manual Name) for CAN_MO10_AMR.
+* To use register names with standard convension, please use CAN_MO10_AMR.
+*/
+#define CAN_MOAMR10 (CAN_MO10_AMR)
+
+/** \brief 1158, Message Object Arbitration Register */
+#define CAN_MO10_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019158u)
+
+/** Alias (User Manual Name) for CAN_MO10_AR.
+* To use register names with standard convension, please use CAN_MO10_AR.
+*/
+#define CAN_MOAR10 (CAN_MO10_AR)
+
+/** \brief 115C, Message Object Control Register */
+#define CAN_MO10_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001915Cu)
+
+/** Alias (User Manual Name) for CAN_MO10_CTR.
+* To use register names with standard convension, please use CAN_MO10_CTR.
+*/
+#define CAN_MOCTR10 (CAN_MO10_CTR)
+
+/** \brief 1154, Message Object Data Register High */
+#define CAN_MO10_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019154u)
+
+/** Alias (User Manual Name) for CAN_MO10_DATAH.
+* To use register names with standard convension, please use CAN_MO10_DATAH.
+*/
+#define CAN_MODATAH10 (CAN_MO10_DATAH)
+
+/** \brief 1150, Message Object Data Register Low */
+#define CAN_MO10_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019150u)
+
+/** Alias (User Manual Name) for CAN_MO10_DATAL.
+* To use register names with standard convension, please use CAN_MO10_DATAL.
+*/
+#define CAN_MODATAL10 (CAN_MO10_DATAL)
+
+/** \brief 1140, Message Object Function Control Register */
+#define CAN_MO10_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019140u)
+
+/** Alias (User Manual Name) for CAN_MO10_EDATA0.
+* To use register names with standard convension, please use CAN_MO10_EDATA0.
+*/
+#define CAN_EMO10DATA0 (CAN_MO10_EDATA0)
+
+/** \brief 1144, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO10_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019144u)
+
+/** Alias (User Manual Name) for CAN_MO10_EDATA1.
+* To use register names with standard convension, please use CAN_MO10_EDATA1.
+*/
+#define CAN_EMO10DATA1 (CAN_MO10_EDATA1)
+
+/** \brief 1148, Message Object Interrupt Pointer Register */
+#define CAN_MO10_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019148u)
+
+/** Alias (User Manual Name) for CAN_MO10_EDATA2.
+* To use register names with standard convension, please use CAN_MO10_EDATA2.
+*/
+#define CAN_EMO10DATA2 (CAN_MO10_EDATA2)
+
+/** \brief 114C, Message Object Acceptance Mask Register */
+#define CAN_MO10_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001914Cu)
+
+/** Alias (User Manual Name) for CAN_MO10_EDATA3.
+* To use register names with standard convension, please use CAN_MO10_EDATA3.
+*/
+#define CAN_EMO10DATA3 (CAN_MO10_EDATA3)
+
+/** \brief 1150, Message Object Data Register Low */
+#define CAN_MO10_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019150u)
+
+/** Alias (User Manual Name) for CAN_MO10_EDATA4.
+* To use register names with standard convension, please use CAN_MO10_EDATA4.
+*/
+#define CAN_EMO10DATA4 (CAN_MO10_EDATA4)
+
+/** \brief 1154, Message Object Data Register High */
+#define CAN_MO10_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019154u)
+
+/** Alias (User Manual Name) for CAN_MO10_EDATA5.
+* To use register names with standard convension, please use CAN_MO10_EDATA5.
+*/
+#define CAN_EMO10DATA5 (CAN_MO10_EDATA5)
+
+/** \brief 1158, Message Object Arbitration Register */
+#define CAN_MO10_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019158u)
+
+/** Alias (User Manual Name) for CAN_MO10_EDATA6.
+* To use register names with standard convension, please use CAN_MO10_EDATA6.
+*/
+#define CAN_EMO10DATA6 (CAN_MO10_EDATA6)
+
+/** \brief 1140, Message Object Function Control Register */
+#define CAN_MO10_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019140u)
+
+/** Alias (User Manual Name) for CAN_MO10_FCR.
+* To use register names with standard convension, please use CAN_MO10_FCR.
+*/
+#define CAN_MOFCR10 (CAN_MO10_FCR)
+
+/** \brief 1144, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO10_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019144u)
+
+/** Alias (User Manual Name) for CAN_MO10_FGPR.
+* To use register names with standard convension, please use CAN_MO10_FGPR.
+*/
+#define CAN_MOFGPR10 (CAN_MO10_FGPR)
+
+/** \brief 1148, Message Object Interrupt Pointer Register */
+#define CAN_MO10_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019148u)
+
+/** Alias (User Manual Name) for CAN_MO10_IPR.
+* To use register names with standard convension, please use CAN_MO10_IPR.
+*/
+#define CAN_MOIPR10 (CAN_MO10_IPR)
+
+/** \brief 115C, Message Object Control Register */
+#define CAN_MO10_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001915Cu)
+
+/** Alias (User Manual Name) for CAN_MO10_STAT.
+* To use register names with standard convension, please use CAN_MO10_STAT.
+*/
+#define CAN_MOSTAT10 (CAN_MO10_STAT)
+
+/** \brief 1DCC, Message Object Acceptance Mask Register */
+#define CAN_MO110_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019DCCu)
+
+/** Alias (User Manual Name) for CAN_MO110_AMR.
+* To use register names with standard convension, please use CAN_MO110_AMR.
+*/
+#define CAN_MOAMR110 (CAN_MO110_AMR)
+
+/** \brief 1DD8, Message Object Arbitration Register */
+#define CAN_MO110_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019DD8u)
+
+/** Alias (User Manual Name) for CAN_MO110_AR.
+* To use register names with standard convension, please use CAN_MO110_AR.
+*/
+#define CAN_MOAR110 (CAN_MO110_AR)
+
+/** \brief 1DDC, Message Object Control Register */
+#define CAN_MO110_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019DDCu)
+
+/** Alias (User Manual Name) for CAN_MO110_CTR.
+* To use register names with standard convension, please use CAN_MO110_CTR.
+*/
+#define CAN_MOCTR110 (CAN_MO110_CTR)
+
+/** \brief 1DD4, Message Object Data Register High */
+#define CAN_MO110_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019DD4u)
+
+/** Alias (User Manual Name) for CAN_MO110_DATAH.
+* To use register names with standard convension, please use CAN_MO110_DATAH.
+*/
+#define CAN_MODATAH110 (CAN_MO110_DATAH)
+
+/** \brief 1DD0, Message Object Data Register Low */
+#define CAN_MO110_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019DD0u)
+
+/** Alias (User Manual Name) for CAN_MO110_DATAL.
+* To use register names with standard convension, please use CAN_MO110_DATAL.
+*/
+#define CAN_MODATAL110 (CAN_MO110_DATAL)
+
+/** \brief 1DC0, Message Object Function Control Register */
+#define CAN_MO110_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019DC0u)
+
+/** Alias (User Manual Name) for CAN_MO110_EDATA0.
+* To use register names with standard convension, please use CAN_MO110_EDATA0.
+*/
+#define CAN_EMO110DATA0 (CAN_MO110_EDATA0)
+
+/** \brief 1DC4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO110_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019DC4u)
+
+/** Alias (User Manual Name) for CAN_MO110_EDATA1.
+* To use register names with standard convension, please use CAN_MO110_EDATA1.
+*/
+#define CAN_EMO110DATA1 (CAN_MO110_EDATA1)
+
+/** \brief 1DC8, Message Object Interrupt Pointer Register */
+#define CAN_MO110_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019DC8u)
+
+/** Alias (User Manual Name) for CAN_MO110_EDATA2.
+* To use register names with standard convension, please use CAN_MO110_EDATA2.
+*/
+#define CAN_EMO110DATA2 (CAN_MO110_EDATA2)
+
+/** \brief 1DCC, Message Object Acceptance Mask Register */
+#define CAN_MO110_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019DCCu)
+
+/** Alias (User Manual Name) for CAN_MO110_EDATA3.
+* To use register names with standard convension, please use CAN_MO110_EDATA3.
+*/
+#define CAN_EMO110DATA3 (CAN_MO110_EDATA3)
+
+/** \brief 1DD0, Message Object Data Register Low */
+#define CAN_MO110_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019DD0u)
+
+/** Alias (User Manual Name) for CAN_MO110_EDATA4.
+* To use register names with standard convension, please use CAN_MO110_EDATA4.
+*/
+#define CAN_EMO110DATA4 (CAN_MO110_EDATA4)
+
+/** \brief 1DD4, Message Object Data Register High */
+#define CAN_MO110_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019DD4u)
+
+/** Alias (User Manual Name) for CAN_MO110_EDATA5.
+* To use register names with standard convension, please use CAN_MO110_EDATA5.
+*/
+#define CAN_EMO110DATA5 (CAN_MO110_EDATA5)
+
+/** \brief 1DD8, Message Object Arbitration Register */
+#define CAN_MO110_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019DD8u)
+
+/** Alias (User Manual Name) for CAN_MO110_EDATA6.
+* To use register names with standard convension, please use CAN_MO110_EDATA6.
+*/
+#define CAN_EMO110DATA6 (CAN_MO110_EDATA6)
+
+/** \brief 1DC0, Message Object Function Control Register */
+#define CAN_MO110_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019DC0u)
+
+/** Alias (User Manual Name) for CAN_MO110_FCR.
+* To use register names with standard convension, please use CAN_MO110_FCR.
+*/
+#define CAN_MOFCR110 (CAN_MO110_FCR)
+
+/** \brief 1DC4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO110_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019DC4u)
+
+/** Alias (User Manual Name) for CAN_MO110_FGPR.
+* To use register names with standard convension, please use CAN_MO110_FGPR.
+*/
+#define CAN_MOFGPR110 (CAN_MO110_FGPR)
+
+/** \brief 1DC8, Message Object Interrupt Pointer Register */
+#define CAN_MO110_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019DC8u)
+
+/** Alias (User Manual Name) for CAN_MO110_IPR.
+* To use register names with standard convension, please use CAN_MO110_IPR.
+*/
+#define CAN_MOIPR110 (CAN_MO110_IPR)
+
+/** \brief 1DDC, Message Object Control Register */
+#define CAN_MO110_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019DDCu)
+
+/** Alias (User Manual Name) for CAN_MO110_STAT.
+* To use register names with standard convension, please use CAN_MO110_STAT.
+*/
+#define CAN_MOSTAT110 (CAN_MO110_STAT)
+
+/** \brief 1DEC, Message Object Acceptance Mask Register */
+#define CAN_MO111_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019DECu)
+
+/** Alias (User Manual Name) for CAN_MO111_AMR.
+* To use register names with standard convension, please use CAN_MO111_AMR.
+*/
+#define CAN_MOAMR111 (CAN_MO111_AMR)
+
+/** \brief 1DF8, Message Object Arbitration Register */
+#define CAN_MO111_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019DF8u)
+
+/** Alias (User Manual Name) for CAN_MO111_AR.
+* To use register names with standard convension, please use CAN_MO111_AR.
+*/
+#define CAN_MOAR111 (CAN_MO111_AR)
+
+/** \brief 1DFC, Message Object Control Register */
+#define CAN_MO111_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019DFCu)
+
+/** Alias (User Manual Name) for CAN_MO111_CTR.
+* To use register names with standard convension, please use CAN_MO111_CTR.
+*/
+#define CAN_MOCTR111 (CAN_MO111_CTR)
+
+/** \brief 1DF4, Message Object Data Register High */
+#define CAN_MO111_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019DF4u)
+
+/** Alias (User Manual Name) for CAN_MO111_DATAH.
+* To use register names with standard convension, please use CAN_MO111_DATAH.
+*/
+#define CAN_MODATAH111 (CAN_MO111_DATAH)
+
+/** \brief 1DF0, Message Object Data Register Low */
+#define CAN_MO111_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019DF0u)
+
+/** Alias (User Manual Name) for CAN_MO111_DATAL.
+* To use register names with standard convension, please use CAN_MO111_DATAL.
+*/
+#define CAN_MODATAL111 (CAN_MO111_DATAL)
+
+/** \brief 1DE0, Message Object Function Control Register */
+#define CAN_MO111_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019DE0u)
+
+/** Alias (User Manual Name) for CAN_MO111_EDATA0.
+* To use register names with standard convension, please use CAN_MO111_EDATA0.
+*/
+#define CAN_EMO111DATA0 (CAN_MO111_EDATA0)
+
+/** \brief 1DE4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO111_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019DE4u)
+
+/** Alias (User Manual Name) for CAN_MO111_EDATA1.
+* To use register names with standard convension, please use CAN_MO111_EDATA1.
+*/
+#define CAN_EMO111DATA1 (CAN_MO111_EDATA1)
+
+/** \brief 1DE8, Message Object Interrupt Pointer Register */
+#define CAN_MO111_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019DE8u)
+
+/** Alias (User Manual Name) for CAN_MO111_EDATA2.
+* To use register names with standard convension, please use CAN_MO111_EDATA2.
+*/
+#define CAN_EMO111DATA2 (CAN_MO111_EDATA2)
+
+/** \brief 1DEC, Message Object Acceptance Mask Register */
+#define CAN_MO111_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019DECu)
+
+/** Alias (User Manual Name) for CAN_MO111_EDATA3.
+* To use register names with standard convension, please use CAN_MO111_EDATA3.
+*/
+#define CAN_EMO111DATA3 (CAN_MO111_EDATA3)
+
+/** \brief 1DF0, Message Object Data Register Low */
+#define CAN_MO111_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019DF0u)
+
+/** Alias (User Manual Name) for CAN_MO111_EDATA4.
+* To use register names with standard convension, please use CAN_MO111_EDATA4.
+*/
+#define CAN_EMO111DATA4 (CAN_MO111_EDATA4)
+
+/** \brief 1DF4, Message Object Data Register High */
+#define CAN_MO111_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019DF4u)
+
+/** Alias (User Manual Name) for CAN_MO111_EDATA5.
+* To use register names with standard convension, please use CAN_MO111_EDATA5.
+*/
+#define CAN_EMO111DATA5 (CAN_MO111_EDATA5)
+
+/** \brief 1DF8, Message Object Arbitration Register */
+#define CAN_MO111_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019DF8u)
+
+/** Alias (User Manual Name) for CAN_MO111_EDATA6.
+* To use register names with standard convension, please use CAN_MO111_EDATA6.
+*/
+#define CAN_EMO111DATA6 (CAN_MO111_EDATA6)
+
+/** \brief 1DE0, Message Object Function Control Register */
+#define CAN_MO111_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019DE0u)
+
+/** Alias (User Manual Name) for CAN_MO111_FCR.
+* To use register names with standard convension, please use CAN_MO111_FCR.
+*/
+#define CAN_MOFCR111 (CAN_MO111_FCR)
+
+/** \brief 1DE4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO111_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019DE4u)
+
+/** Alias (User Manual Name) for CAN_MO111_FGPR.
+* To use register names with standard convension, please use CAN_MO111_FGPR.
+*/
+#define CAN_MOFGPR111 (CAN_MO111_FGPR)
+
+/** \brief 1DE8, Message Object Interrupt Pointer Register */
+#define CAN_MO111_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019DE8u)
+
+/** Alias (User Manual Name) for CAN_MO111_IPR.
+* To use register names with standard convension, please use CAN_MO111_IPR.
+*/
+#define CAN_MOIPR111 (CAN_MO111_IPR)
+
+/** \brief 1DFC, Message Object Control Register */
+#define CAN_MO111_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019DFCu)
+
+/** Alias (User Manual Name) for CAN_MO111_STAT.
+* To use register names with standard convension, please use CAN_MO111_STAT.
+*/
+#define CAN_MOSTAT111 (CAN_MO111_STAT)
+
+/** \brief 1E0C, Message Object Acceptance Mask Register */
+#define CAN_MO112_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019E0Cu)
+
+/** Alias (User Manual Name) for CAN_MO112_AMR.
+* To use register names with standard convension, please use CAN_MO112_AMR.
+*/
+#define CAN_MOAMR112 (CAN_MO112_AMR)
+
+/** \brief 1E18, Message Object Arbitration Register */
+#define CAN_MO112_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019E18u)
+
+/** Alias (User Manual Name) for CAN_MO112_AR.
+* To use register names with standard convension, please use CAN_MO112_AR.
+*/
+#define CAN_MOAR112 (CAN_MO112_AR)
+
+/** \brief 1E1C, Message Object Control Register */
+#define CAN_MO112_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019E1Cu)
+
+/** Alias (User Manual Name) for CAN_MO112_CTR.
+* To use register names with standard convension, please use CAN_MO112_CTR.
+*/
+#define CAN_MOCTR112 (CAN_MO112_CTR)
+
+/** \brief 1E14, Message Object Data Register High */
+#define CAN_MO112_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019E14u)
+
+/** Alias (User Manual Name) for CAN_MO112_DATAH.
+* To use register names with standard convension, please use CAN_MO112_DATAH.
+*/
+#define CAN_MODATAH112 (CAN_MO112_DATAH)
+
+/** \brief 1E10, Message Object Data Register Low */
+#define CAN_MO112_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019E10u)
+
+/** Alias (User Manual Name) for CAN_MO112_DATAL.
+* To use register names with standard convension, please use CAN_MO112_DATAL.
+*/
+#define CAN_MODATAL112 (CAN_MO112_DATAL)
+
+/** \brief 1E00, Message Object Function Control Register */
+#define CAN_MO112_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019E00u)
+
+/** Alias (User Manual Name) for CAN_MO112_EDATA0.
+* To use register names with standard convension, please use CAN_MO112_EDATA0.
+*/
+#define CAN_EMO112DATA0 (CAN_MO112_EDATA0)
+
+/** \brief 1E04, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO112_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019E04u)
+
+/** Alias (User Manual Name) for CAN_MO112_EDATA1.
+* To use register names with standard convension, please use CAN_MO112_EDATA1.
+*/
+#define CAN_EMO112DATA1 (CAN_MO112_EDATA1)
+
+/** \brief 1E08, Message Object Interrupt Pointer Register */
+#define CAN_MO112_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019E08u)
+
+/** Alias (User Manual Name) for CAN_MO112_EDATA2.
+* To use register names with standard convension, please use CAN_MO112_EDATA2.
+*/
+#define CAN_EMO112DATA2 (CAN_MO112_EDATA2)
+
+/** \brief 1E0C, Message Object Acceptance Mask Register */
+#define CAN_MO112_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019E0Cu)
+
+/** Alias (User Manual Name) for CAN_MO112_EDATA3.
+* To use register names with standard convension, please use CAN_MO112_EDATA3.
+*/
+#define CAN_EMO112DATA3 (CAN_MO112_EDATA3)
+
+/** \brief 1E10, Message Object Data Register Low */
+#define CAN_MO112_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019E10u)
+
+/** Alias (User Manual Name) for CAN_MO112_EDATA4.
+* To use register names with standard convension, please use CAN_MO112_EDATA4.
+*/
+#define CAN_EMO112DATA4 (CAN_MO112_EDATA4)
+
+/** \brief 1E14, Message Object Data Register High */
+#define CAN_MO112_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019E14u)
+
+/** Alias (User Manual Name) for CAN_MO112_EDATA5.
+* To use register names with standard convension, please use CAN_MO112_EDATA5.
+*/
+#define CAN_EMO112DATA5 (CAN_MO112_EDATA5)
+
+/** \brief 1E18, Message Object Arbitration Register */
+#define CAN_MO112_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019E18u)
+
+/** Alias (User Manual Name) for CAN_MO112_EDATA6.
+* To use register names with standard convension, please use CAN_MO112_EDATA6.
+*/
+#define CAN_EMO112DATA6 (CAN_MO112_EDATA6)
+
+/** \brief 1E00, Message Object Function Control Register */
+#define CAN_MO112_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019E00u)
+
+/** Alias (User Manual Name) for CAN_MO112_FCR.
+* To use register names with standard convension, please use CAN_MO112_FCR.
+*/
+#define CAN_MOFCR112 (CAN_MO112_FCR)
+
+/** \brief 1E04, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO112_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019E04u)
+
+/** Alias (User Manual Name) for CAN_MO112_FGPR.
+* To use register names with standard convension, please use CAN_MO112_FGPR.
+*/
+#define CAN_MOFGPR112 (CAN_MO112_FGPR)
+
+/** \brief 1E08, Message Object Interrupt Pointer Register */
+#define CAN_MO112_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019E08u)
+
+/** Alias (User Manual Name) for CAN_MO112_IPR.
+* To use register names with standard convension, please use CAN_MO112_IPR.
+*/
+#define CAN_MOIPR112 (CAN_MO112_IPR)
+
+/** \brief 1E1C, Message Object Control Register */
+#define CAN_MO112_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019E1Cu)
+
+/** Alias (User Manual Name) for CAN_MO112_STAT.
+* To use register names with standard convension, please use CAN_MO112_STAT.
+*/
+#define CAN_MOSTAT112 (CAN_MO112_STAT)
+
+/** \brief 1E2C, Message Object Acceptance Mask Register */
+#define CAN_MO113_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019E2Cu)
+
+/** Alias (User Manual Name) for CAN_MO113_AMR.
+* To use register names with standard convension, please use CAN_MO113_AMR.
+*/
+#define CAN_MOAMR113 (CAN_MO113_AMR)
+
+/** \brief 1E38, Message Object Arbitration Register */
+#define CAN_MO113_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019E38u)
+
+/** Alias (User Manual Name) for CAN_MO113_AR.
+* To use register names with standard convension, please use CAN_MO113_AR.
+*/
+#define CAN_MOAR113 (CAN_MO113_AR)
+
+/** \brief 1E3C, Message Object Control Register */
+#define CAN_MO113_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019E3Cu)
+
+/** Alias (User Manual Name) for CAN_MO113_CTR.
+* To use register names with standard convension, please use CAN_MO113_CTR.
+*/
+#define CAN_MOCTR113 (CAN_MO113_CTR)
+
+/** \brief 1E34, Message Object Data Register High */
+#define CAN_MO113_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019E34u)
+
+/** Alias (User Manual Name) for CAN_MO113_DATAH.
+* To use register names with standard convension, please use CAN_MO113_DATAH.
+*/
+#define CAN_MODATAH113 (CAN_MO113_DATAH)
+
+/** \brief 1E30, Message Object Data Register Low */
+#define CAN_MO113_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019E30u)
+
+/** Alias (User Manual Name) for CAN_MO113_DATAL.
+* To use register names with standard convension, please use CAN_MO113_DATAL.
+*/
+#define CAN_MODATAL113 (CAN_MO113_DATAL)
+
+/** \brief 1E20, Message Object Function Control Register */
+#define CAN_MO113_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019E20u)
+
+/** Alias (User Manual Name) for CAN_MO113_EDATA0.
+* To use register names with standard convension, please use CAN_MO113_EDATA0.
+*/
+#define CAN_EMO113DATA0 (CAN_MO113_EDATA0)
+
+/** \brief 1E24, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO113_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019E24u)
+
+/** Alias (User Manual Name) for CAN_MO113_EDATA1.
+* To use register names with standard convension, please use CAN_MO113_EDATA1.
+*/
+#define CAN_EMO113DATA1 (CAN_MO113_EDATA1)
+
+/** \brief 1E28, Message Object Interrupt Pointer Register */
+#define CAN_MO113_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019E28u)
+
+/** Alias (User Manual Name) for CAN_MO113_EDATA2.
+* To use register names with standard convension, please use CAN_MO113_EDATA2.
+*/
+#define CAN_EMO113DATA2 (CAN_MO113_EDATA2)
+
+/** \brief 1E2C, Message Object Acceptance Mask Register */
+#define CAN_MO113_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019E2Cu)
+
+/** Alias (User Manual Name) for CAN_MO113_EDATA3.
+* To use register names with standard convension, please use CAN_MO113_EDATA3.
+*/
+#define CAN_EMO113DATA3 (CAN_MO113_EDATA3)
+
+/** \brief 1E30, Message Object Data Register Low */
+#define CAN_MO113_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019E30u)
+
+/** Alias (User Manual Name) for CAN_MO113_EDATA4.
+* To use register names with standard convension, please use CAN_MO113_EDATA4.
+*/
+#define CAN_EMO113DATA4 (CAN_MO113_EDATA4)
+
+/** \brief 1E34, Message Object Data Register High */
+#define CAN_MO113_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019E34u)
+
+/** Alias (User Manual Name) for CAN_MO113_EDATA5.
+* To use register names with standard convension, please use CAN_MO113_EDATA5.
+*/
+#define CAN_EMO113DATA5 (CAN_MO113_EDATA5)
+
+/** \brief 1E38, Message Object Arbitration Register */
+#define CAN_MO113_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019E38u)
+
+/** Alias (User Manual Name) for CAN_MO113_EDATA6.
+* To use register names with standard convension, please use CAN_MO113_EDATA6.
+*/
+#define CAN_EMO113DATA6 (CAN_MO113_EDATA6)
+
+/** \brief 1E20, Message Object Function Control Register */
+#define CAN_MO113_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019E20u)
+
+/** Alias (User Manual Name) for CAN_MO113_FCR.
+* To use register names with standard convension, please use CAN_MO113_FCR.
+*/
+#define CAN_MOFCR113 (CAN_MO113_FCR)
+
+/** \brief 1E24, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO113_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019E24u)
+
+/** Alias (User Manual Name) for CAN_MO113_FGPR.
+* To use register names with standard convension, please use CAN_MO113_FGPR.
+*/
+#define CAN_MOFGPR113 (CAN_MO113_FGPR)
+
+/** \brief 1E28, Message Object Interrupt Pointer Register */
+#define CAN_MO113_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019E28u)
+
+/** Alias (User Manual Name) for CAN_MO113_IPR.
+* To use register names with standard convension, please use CAN_MO113_IPR.
+*/
+#define CAN_MOIPR113 (CAN_MO113_IPR)
+
+/** \brief 1E3C, Message Object Control Register */
+#define CAN_MO113_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019E3Cu)
+
+/** Alias (User Manual Name) for CAN_MO113_STAT.
+* To use register names with standard convension, please use CAN_MO113_STAT.
+*/
+#define CAN_MOSTAT113 (CAN_MO113_STAT)
+
+/** \brief 1E4C, Message Object Acceptance Mask Register */
+#define CAN_MO114_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019E4Cu)
+
+/** Alias (User Manual Name) for CAN_MO114_AMR.
+* To use register names with standard convension, please use CAN_MO114_AMR.
+*/
+#define CAN_MOAMR114 (CAN_MO114_AMR)
+
+/** \brief 1E58, Message Object Arbitration Register */
+#define CAN_MO114_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019E58u)
+
+/** Alias (User Manual Name) for CAN_MO114_AR.
+* To use register names with standard convension, please use CAN_MO114_AR.
+*/
+#define CAN_MOAR114 (CAN_MO114_AR)
+
+/** \brief 1E5C, Message Object Control Register */
+#define CAN_MO114_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019E5Cu)
+
+/** Alias (User Manual Name) for CAN_MO114_CTR.
+* To use register names with standard convension, please use CAN_MO114_CTR.
+*/
+#define CAN_MOCTR114 (CAN_MO114_CTR)
+
+/** \brief 1E54, Message Object Data Register High */
+#define CAN_MO114_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019E54u)
+
+/** Alias (User Manual Name) for CAN_MO114_DATAH.
+* To use register names with standard convension, please use CAN_MO114_DATAH.
+*/
+#define CAN_MODATAH114 (CAN_MO114_DATAH)
+
+/** \brief 1E50, Message Object Data Register Low */
+#define CAN_MO114_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019E50u)
+
+/** Alias (User Manual Name) for CAN_MO114_DATAL.
+* To use register names with standard convension, please use CAN_MO114_DATAL.
+*/
+#define CAN_MODATAL114 (CAN_MO114_DATAL)
+
+/** \brief 1E40, Message Object Function Control Register */
+#define CAN_MO114_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019E40u)
+
+/** Alias (User Manual Name) for CAN_MO114_EDATA0.
+* To use register names with standard convension, please use CAN_MO114_EDATA0.
+*/
+#define CAN_EMO114DATA0 (CAN_MO114_EDATA0)
+
+/** \brief 1E44, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO114_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019E44u)
+
+/** Alias (User Manual Name) for CAN_MO114_EDATA1.
+* To use register names with standard convension, please use CAN_MO114_EDATA1.
+*/
+#define CAN_EMO114DATA1 (CAN_MO114_EDATA1)
+
+/** \brief 1E48, Message Object Interrupt Pointer Register */
+#define CAN_MO114_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019E48u)
+
+/** Alias (User Manual Name) for CAN_MO114_EDATA2.
+* To use register names with standard convension, please use CAN_MO114_EDATA2.
+*/
+#define CAN_EMO114DATA2 (CAN_MO114_EDATA2)
+
+/** \brief 1E4C, Message Object Acceptance Mask Register */
+#define CAN_MO114_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019E4Cu)
+
+/** Alias (User Manual Name) for CAN_MO114_EDATA3.
+* To use register names with standard convension, please use CAN_MO114_EDATA3.
+*/
+#define CAN_EMO114DATA3 (CAN_MO114_EDATA3)
+
+/** \brief 1E50, Message Object Data Register Low */
+#define CAN_MO114_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019E50u)
+
+/** Alias (User Manual Name) for CAN_MO114_EDATA4.
+* To use register names with standard convension, please use CAN_MO114_EDATA4.
+*/
+#define CAN_EMO114DATA4 (CAN_MO114_EDATA4)
+
+/** \brief 1E54, Message Object Data Register High */
+#define CAN_MO114_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019E54u)
+
+/** Alias (User Manual Name) for CAN_MO114_EDATA5.
+* To use register names with standard convension, please use CAN_MO114_EDATA5.
+*/
+#define CAN_EMO114DATA5 (CAN_MO114_EDATA5)
+
+/** \brief 1E58, Message Object Arbitration Register */
+#define CAN_MO114_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019E58u)
+
+/** Alias (User Manual Name) for CAN_MO114_EDATA6.
+* To use register names with standard convension, please use CAN_MO114_EDATA6.
+*/
+#define CAN_EMO114DATA6 (CAN_MO114_EDATA6)
+
+/** \brief 1E40, Message Object Function Control Register */
+#define CAN_MO114_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019E40u)
+
+/** Alias (User Manual Name) for CAN_MO114_FCR.
+* To use register names with standard convension, please use CAN_MO114_FCR.
+*/
+#define CAN_MOFCR114 (CAN_MO114_FCR)
+
+/** \brief 1E44, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO114_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019E44u)
+
+/** Alias (User Manual Name) for CAN_MO114_FGPR.
+* To use register names with standard convension, please use CAN_MO114_FGPR.
+*/
+#define CAN_MOFGPR114 (CAN_MO114_FGPR)
+
+/** \brief 1E48, Message Object Interrupt Pointer Register */
+#define CAN_MO114_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019E48u)
+
+/** Alias (User Manual Name) for CAN_MO114_IPR.
+* To use register names with standard convension, please use CAN_MO114_IPR.
+*/
+#define CAN_MOIPR114 (CAN_MO114_IPR)
+
+/** \brief 1E5C, Message Object Control Register */
+#define CAN_MO114_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019E5Cu)
+
+/** Alias (User Manual Name) for CAN_MO114_STAT.
+* To use register names with standard convension, please use CAN_MO114_STAT.
+*/
+#define CAN_MOSTAT114 (CAN_MO114_STAT)
+
+/** \brief 1E6C, Message Object Acceptance Mask Register */
+#define CAN_MO115_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019E6Cu)
+
+/** Alias (User Manual Name) for CAN_MO115_AMR.
+* To use register names with standard convension, please use CAN_MO115_AMR.
+*/
+#define CAN_MOAMR115 (CAN_MO115_AMR)
+
+/** \brief 1E78, Message Object Arbitration Register */
+#define CAN_MO115_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019E78u)
+
+/** Alias (User Manual Name) for CAN_MO115_AR.
+* To use register names with standard convension, please use CAN_MO115_AR.
+*/
+#define CAN_MOAR115 (CAN_MO115_AR)
+
+/** \brief 1E7C, Message Object Control Register */
+#define CAN_MO115_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019E7Cu)
+
+/** Alias (User Manual Name) for CAN_MO115_CTR.
+* To use register names with standard convension, please use CAN_MO115_CTR.
+*/
+#define CAN_MOCTR115 (CAN_MO115_CTR)
+
+/** \brief 1E74, Message Object Data Register High */
+#define CAN_MO115_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019E74u)
+
+/** Alias (User Manual Name) for CAN_MO115_DATAH.
+* To use register names with standard convension, please use CAN_MO115_DATAH.
+*/
+#define CAN_MODATAH115 (CAN_MO115_DATAH)
+
+/** \brief 1E70, Message Object Data Register Low */
+#define CAN_MO115_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019E70u)
+
+/** Alias (User Manual Name) for CAN_MO115_DATAL.
+* To use register names with standard convension, please use CAN_MO115_DATAL.
+*/
+#define CAN_MODATAL115 (CAN_MO115_DATAL)
+
+/** \brief 1E60, Message Object Function Control Register */
+#define CAN_MO115_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019E60u)
+
+/** Alias (User Manual Name) for CAN_MO115_EDATA0.
+* To use register names with standard convension, please use CAN_MO115_EDATA0.
+*/
+#define CAN_EMO115DATA0 (CAN_MO115_EDATA0)
+
+/** \brief 1E64, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO115_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019E64u)
+
+/** Alias (User Manual Name) for CAN_MO115_EDATA1.
+* To use register names with standard convension, please use CAN_MO115_EDATA1.
+*/
+#define CAN_EMO115DATA1 (CAN_MO115_EDATA1)
+
+/** \brief 1E68, Message Object Interrupt Pointer Register */
+#define CAN_MO115_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019E68u)
+
+/** Alias (User Manual Name) for CAN_MO115_EDATA2.
+* To use register names with standard convension, please use CAN_MO115_EDATA2.
+*/
+#define CAN_EMO115DATA2 (CAN_MO115_EDATA2)
+
+/** \brief 1E6C, Message Object Acceptance Mask Register */
+#define CAN_MO115_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019E6Cu)
+
+/** Alias (User Manual Name) for CAN_MO115_EDATA3.
+* To use register names with standard convension, please use CAN_MO115_EDATA3.
+*/
+#define CAN_EMO115DATA3 (CAN_MO115_EDATA3)
+
+/** \brief 1E70, Message Object Data Register Low */
+#define CAN_MO115_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019E70u)
+
+/** Alias (User Manual Name) for CAN_MO115_EDATA4.
+* To use register names with standard convension, please use CAN_MO115_EDATA4.
+*/
+#define CAN_EMO115DATA4 (CAN_MO115_EDATA4)
+
+/** \brief 1E74, Message Object Data Register High */
+#define CAN_MO115_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019E74u)
+
+/** Alias (User Manual Name) for CAN_MO115_EDATA5.
+* To use register names with standard convension, please use CAN_MO115_EDATA5.
+*/
+#define CAN_EMO115DATA5 (CAN_MO115_EDATA5)
+
+/** \brief 1E78, Message Object Arbitration Register */
+#define CAN_MO115_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019E78u)
+
+/** Alias (User Manual Name) for CAN_MO115_EDATA6.
+* To use register names with standard convension, please use CAN_MO115_EDATA6.
+*/
+#define CAN_EMO115DATA6 (CAN_MO115_EDATA6)
+
+/** \brief 1E60, Message Object Function Control Register */
+#define CAN_MO115_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019E60u)
+
+/** Alias (User Manual Name) for CAN_MO115_FCR.
+* To use register names with standard convension, please use CAN_MO115_FCR.
+*/
+#define CAN_MOFCR115 (CAN_MO115_FCR)
+
+/** \brief 1E64, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO115_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019E64u)
+
+/** Alias (User Manual Name) for CAN_MO115_FGPR.
+* To use register names with standard convension, please use CAN_MO115_FGPR.
+*/
+#define CAN_MOFGPR115 (CAN_MO115_FGPR)
+
+/** \brief 1E68, Message Object Interrupt Pointer Register */
+#define CAN_MO115_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019E68u)
+
+/** Alias (User Manual Name) for CAN_MO115_IPR.
+* To use register names with standard convension, please use CAN_MO115_IPR.
+*/
+#define CAN_MOIPR115 (CAN_MO115_IPR)
+
+/** \brief 1E7C, Message Object Control Register */
+#define CAN_MO115_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019E7Cu)
+
+/** Alias (User Manual Name) for CAN_MO115_STAT.
+* To use register names with standard convension, please use CAN_MO115_STAT.
+*/
+#define CAN_MOSTAT115 (CAN_MO115_STAT)
+
+/** \brief 1E8C, Message Object Acceptance Mask Register */
+#define CAN_MO116_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019E8Cu)
+
+/** Alias (User Manual Name) for CAN_MO116_AMR.
+* To use register names with standard convension, please use CAN_MO116_AMR.
+*/
+#define CAN_MOAMR116 (CAN_MO116_AMR)
+
+/** \brief 1E98, Message Object Arbitration Register */
+#define CAN_MO116_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019E98u)
+
+/** Alias (User Manual Name) for CAN_MO116_AR.
+* To use register names with standard convension, please use CAN_MO116_AR.
+*/
+#define CAN_MOAR116 (CAN_MO116_AR)
+
+/** \brief 1E9C, Message Object Control Register */
+#define CAN_MO116_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019E9Cu)
+
+/** Alias (User Manual Name) for CAN_MO116_CTR.
+* To use register names with standard convension, please use CAN_MO116_CTR.
+*/
+#define CAN_MOCTR116 (CAN_MO116_CTR)
+
+/** \brief 1E94, Message Object Data Register High */
+#define CAN_MO116_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019E94u)
+
+/** Alias (User Manual Name) for CAN_MO116_DATAH.
+* To use register names with standard convension, please use CAN_MO116_DATAH.
+*/
+#define CAN_MODATAH116 (CAN_MO116_DATAH)
+
+/** \brief 1E90, Message Object Data Register Low */
+#define CAN_MO116_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019E90u)
+
+/** Alias (User Manual Name) for CAN_MO116_DATAL.
+* To use register names with standard convension, please use CAN_MO116_DATAL.
+*/
+#define CAN_MODATAL116 (CAN_MO116_DATAL)
+
+/** \brief 1E80, Message Object Function Control Register */
+#define CAN_MO116_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019E80u)
+
+/** Alias (User Manual Name) for CAN_MO116_EDATA0.
+* To use register names with standard convension, please use CAN_MO116_EDATA0.
+*/
+#define CAN_EMO116DATA0 (CAN_MO116_EDATA0)
+
+/** \brief 1E84, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO116_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019E84u)
+
+/** Alias (User Manual Name) for CAN_MO116_EDATA1.
+* To use register names with standard convension, please use CAN_MO116_EDATA1.
+*/
+#define CAN_EMO116DATA1 (CAN_MO116_EDATA1)
+
+/** \brief 1E88, Message Object Interrupt Pointer Register */
+#define CAN_MO116_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019E88u)
+
+/** Alias (User Manual Name) for CAN_MO116_EDATA2.
+* To use register names with standard convension, please use CAN_MO116_EDATA2.
+*/
+#define CAN_EMO116DATA2 (CAN_MO116_EDATA2)
+
+/** \brief 1E8C, Message Object Acceptance Mask Register */
+#define CAN_MO116_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019E8Cu)
+
+/** Alias (User Manual Name) for CAN_MO116_EDATA3.
+* To use register names with standard convension, please use CAN_MO116_EDATA3.
+*/
+#define CAN_EMO116DATA3 (CAN_MO116_EDATA3)
+
+/** \brief 1E90, Message Object Data Register Low */
+#define CAN_MO116_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019E90u)
+
+/** Alias (User Manual Name) for CAN_MO116_EDATA4.
+* To use register names with standard convension, please use CAN_MO116_EDATA4.
+*/
+#define CAN_EMO116DATA4 (CAN_MO116_EDATA4)
+
+/** \brief 1E94, Message Object Data Register High */
+#define CAN_MO116_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019E94u)
+
+/** Alias (User Manual Name) for CAN_MO116_EDATA5.
+* To use register names with standard convension, please use CAN_MO116_EDATA5.
+*/
+#define CAN_EMO116DATA5 (CAN_MO116_EDATA5)
+
+/** \brief 1E98, Message Object Arbitration Register */
+#define CAN_MO116_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019E98u)
+
+/** Alias (User Manual Name) for CAN_MO116_EDATA6.
+* To use register names with standard convension, please use CAN_MO116_EDATA6.
+*/
+#define CAN_EMO116DATA6 (CAN_MO116_EDATA6)
+
+/** \brief 1E80, Message Object Function Control Register */
+#define CAN_MO116_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019E80u)
+
+/** Alias (User Manual Name) for CAN_MO116_FCR.
+* To use register names with standard convension, please use CAN_MO116_FCR.
+*/
+#define CAN_MOFCR116 (CAN_MO116_FCR)
+
+/** \brief 1E84, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO116_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019E84u)
+
+/** Alias (User Manual Name) for CAN_MO116_FGPR.
+* To use register names with standard convension, please use CAN_MO116_FGPR.
+*/
+#define CAN_MOFGPR116 (CAN_MO116_FGPR)
+
+/** \brief 1E88, Message Object Interrupt Pointer Register */
+#define CAN_MO116_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019E88u)
+
+/** Alias (User Manual Name) for CAN_MO116_IPR.
+* To use register names with standard convension, please use CAN_MO116_IPR.
+*/
+#define CAN_MOIPR116 (CAN_MO116_IPR)
+
+/** \brief 1E9C, Message Object Control Register */
+#define CAN_MO116_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019E9Cu)
+
+/** Alias (User Manual Name) for CAN_MO116_STAT.
+* To use register names with standard convension, please use CAN_MO116_STAT.
+*/
+#define CAN_MOSTAT116 (CAN_MO116_STAT)
+
+/** \brief 1EAC, Message Object Acceptance Mask Register */
+#define CAN_MO117_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019EACu)
+
+/** Alias (User Manual Name) for CAN_MO117_AMR.
+* To use register names with standard convension, please use CAN_MO117_AMR.
+*/
+#define CAN_MOAMR117 (CAN_MO117_AMR)
+
+/** \brief 1EB8, Message Object Arbitration Register */
+#define CAN_MO117_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019EB8u)
+
+/** Alias (User Manual Name) for CAN_MO117_AR.
+* To use register names with standard convension, please use CAN_MO117_AR.
+*/
+#define CAN_MOAR117 (CAN_MO117_AR)
+
+/** \brief 1EBC, Message Object Control Register */
+#define CAN_MO117_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019EBCu)
+
+/** Alias (User Manual Name) for CAN_MO117_CTR.
+* To use register names with standard convension, please use CAN_MO117_CTR.
+*/
+#define CAN_MOCTR117 (CAN_MO117_CTR)
+
+/** \brief 1EB4, Message Object Data Register High */
+#define CAN_MO117_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019EB4u)
+
+/** Alias (User Manual Name) for CAN_MO117_DATAH.
+* To use register names with standard convension, please use CAN_MO117_DATAH.
+*/
+#define CAN_MODATAH117 (CAN_MO117_DATAH)
+
+/** \brief 1EB0, Message Object Data Register Low */
+#define CAN_MO117_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019EB0u)
+
+/** Alias (User Manual Name) for CAN_MO117_DATAL.
+* To use register names with standard convension, please use CAN_MO117_DATAL.
+*/
+#define CAN_MODATAL117 (CAN_MO117_DATAL)
+
+/** \brief 1EA0, Message Object Function Control Register */
+#define CAN_MO117_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019EA0u)
+
+/** Alias (User Manual Name) for CAN_MO117_EDATA0.
+* To use register names with standard convension, please use CAN_MO117_EDATA0.
+*/
+#define CAN_EMO117DATA0 (CAN_MO117_EDATA0)
+
+/** \brief 1EA4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO117_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019EA4u)
+
+/** Alias (User Manual Name) for CAN_MO117_EDATA1.
+* To use register names with standard convension, please use CAN_MO117_EDATA1.
+*/
+#define CAN_EMO117DATA1 (CAN_MO117_EDATA1)
+
+/** \brief 1EA8, Message Object Interrupt Pointer Register */
+#define CAN_MO117_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019EA8u)
+
+/** Alias (User Manual Name) for CAN_MO117_EDATA2.
+* To use register names with standard convension, please use CAN_MO117_EDATA2.
+*/
+#define CAN_EMO117DATA2 (CAN_MO117_EDATA2)
+
+/** \brief 1EAC, Message Object Acceptance Mask Register */
+#define CAN_MO117_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019EACu)
+
+/** Alias (User Manual Name) for CAN_MO117_EDATA3.
+* To use register names with standard convension, please use CAN_MO117_EDATA3.
+*/
+#define CAN_EMO117DATA3 (CAN_MO117_EDATA3)
+
+/** \brief 1EB0, Message Object Data Register Low */
+#define CAN_MO117_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019EB0u)
+
+/** Alias (User Manual Name) for CAN_MO117_EDATA4.
+* To use register names with standard convension, please use CAN_MO117_EDATA4.
+*/
+#define CAN_EMO117DATA4 (CAN_MO117_EDATA4)
+
+/** \brief 1EB4, Message Object Data Register High */
+#define CAN_MO117_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019EB4u)
+
+/** Alias (User Manual Name) for CAN_MO117_EDATA5.
+* To use register names with standard convension, please use CAN_MO117_EDATA5.
+*/
+#define CAN_EMO117DATA5 (CAN_MO117_EDATA5)
+
+/** \brief 1EB8, Message Object Arbitration Register */
+#define CAN_MO117_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019EB8u)
+
+/** Alias (User Manual Name) for CAN_MO117_EDATA6.
+* To use register names with standard convension, please use CAN_MO117_EDATA6.
+*/
+#define CAN_EMO117DATA6 (CAN_MO117_EDATA6)
+
+/** \brief 1EA0, Message Object Function Control Register */
+#define CAN_MO117_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019EA0u)
+
+/** Alias (User Manual Name) for CAN_MO117_FCR.
+* To use register names with standard convension, please use CAN_MO117_FCR.
+*/
+#define CAN_MOFCR117 (CAN_MO117_FCR)
+
+/** \brief 1EA4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO117_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019EA4u)
+
+/** Alias (User Manual Name) for CAN_MO117_FGPR.
+* To use register names with standard convension, please use CAN_MO117_FGPR.
+*/
+#define CAN_MOFGPR117 (CAN_MO117_FGPR)
+
+/** \brief 1EA8, Message Object Interrupt Pointer Register */
+#define CAN_MO117_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019EA8u)
+
+/** Alias (User Manual Name) for CAN_MO117_IPR.
+* To use register names with standard convension, please use CAN_MO117_IPR.
+*/
+#define CAN_MOIPR117 (CAN_MO117_IPR)
+
+/** \brief 1EBC, Message Object Control Register */
+#define CAN_MO117_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019EBCu)
+
+/** Alias (User Manual Name) for CAN_MO117_STAT.
+* To use register names with standard convension, please use CAN_MO117_STAT.
+*/
+#define CAN_MOSTAT117 (CAN_MO117_STAT)
+
+/** \brief 1ECC, Message Object Acceptance Mask Register */
+#define CAN_MO118_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019ECCu)
+
+/** Alias (User Manual Name) for CAN_MO118_AMR.
+* To use register names with standard convension, please use CAN_MO118_AMR.
+*/
+#define CAN_MOAMR118 (CAN_MO118_AMR)
+
+/** \brief 1ED8, Message Object Arbitration Register */
+#define CAN_MO118_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019ED8u)
+
+/** Alias (User Manual Name) for CAN_MO118_AR.
+* To use register names with standard convension, please use CAN_MO118_AR.
+*/
+#define CAN_MOAR118 (CAN_MO118_AR)
+
+/** \brief 1EDC, Message Object Control Register */
+#define CAN_MO118_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019EDCu)
+
+/** Alias (User Manual Name) for CAN_MO118_CTR.
+* To use register names with standard convension, please use CAN_MO118_CTR.
+*/
+#define CAN_MOCTR118 (CAN_MO118_CTR)
+
+/** \brief 1ED4, Message Object Data Register High */
+#define CAN_MO118_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019ED4u)
+
+/** Alias (User Manual Name) for CAN_MO118_DATAH.
+* To use register names with standard convension, please use CAN_MO118_DATAH.
+*/
+#define CAN_MODATAH118 (CAN_MO118_DATAH)
+
+/** \brief 1ED0, Message Object Data Register Low */
+#define CAN_MO118_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019ED0u)
+
+/** Alias (User Manual Name) for CAN_MO118_DATAL.
+* To use register names with standard convension, please use CAN_MO118_DATAL.
+*/
+#define CAN_MODATAL118 (CAN_MO118_DATAL)
+
+/** \brief 1EC0, Message Object Function Control Register */
+#define CAN_MO118_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019EC0u)
+
+/** Alias (User Manual Name) for CAN_MO118_EDATA0.
+* To use register names with standard convension, please use CAN_MO118_EDATA0.
+*/
+#define CAN_EMO118DATA0 (CAN_MO118_EDATA0)
+
+/** \brief 1EC4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO118_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019EC4u)
+
+/** Alias (User Manual Name) for CAN_MO118_EDATA1.
+* To use register names with standard convension, please use CAN_MO118_EDATA1.
+*/
+#define CAN_EMO118DATA1 (CAN_MO118_EDATA1)
+
+/** \brief 1EC8, Message Object Interrupt Pointer Register */
+#define CAN_MO118_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019EC8u)
+
+/** Alias (User Manual Name) for CAN_MO118_EDATA2.
+* To use register names with standard convension, please use CAN_MO118_EDATA2.
+*/
+#define CAN_EMO118DATA2 (CAN_MO118_EDATA2)
+
+/** \brief 1ECC, Message Object Acceptance Mask Register */
+#define CAN_MO118_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019ECCu)
+
+/** Alias (User Manual Name) for CAN_MO118_EDATA3.
+* To use register names with standard convension, please use CAN_MO118_EDATA3.
+*/
+#define CAN_EMO118DATA3 (CAN_MO118_EDATA3)
+
+/** \brief 1ED0, Message Object Data Register Low */
+#define CAN_MO118_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019ED0u)
+
+/** Alias (User Manual Name) for CAN_MO118_EDATA4.
+* To use register names with standard convension, please use CAN_MO118_EDATA4.
+*/
+#define CAN_EMO118DATA4 (CAN_MO118_EDATA4)
+
+/** \brief 1ED4, Message Object Data Register High */
+#define CAN_MO118_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019ED4u)
+
+/** Alias (User Manual Name) for CAN_MO118_EDATA5.
+* To use register names with standard convension, please use CAN_MO118_EDATA5.
+*/
+#define CAN_EMO118DATA5 (CAN_MO118_EDATA5)
+
+/** \brief 1ED8, Message Object Arbitration Register */
+#define CAN_MO118_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019ED8u)
+
+/** Alias (User Manual Name) for CAN_MO118_EDATA6.
+* To use register names with standard convension, please use CAN_MO118_EDATA6.
+*/
+#define CAN_EMO118DATA6 (CAN_MO118_EDATA6)
+
+/** \brief 1EC0, Message Object Function Control Register */
+#define CAN_MO118_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019EC0u)
+
+/** Alias (User Manual Name) for CAN_MO118_FCR.
+* To use register names with standard convension, please use CAN_MO118_FCR.
+*/
+#define CAN_MOFCR118 (CAN_MO118_FCR)
+
+/** \brief 1EC4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO118_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019EC4u)
+
+/** Alias (User Manual Name) for CAN_MO118_FGPR.
+* To use register names with standard convension, please use CAN_MO118_FGPR.
+*/
+#define CAN_MOFGPR118 (CAN_MO118_FGPR)
+
+/** \brief 1EC8, Message Object Interrupt Pointer Register */
+#define CAN_MO118_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019EC8u)
+
+/** Alias (User Manual Name) for CAN_MO118_IPR.
+* To use register names with standard convension, please use CAN_MO118_IPR.
+*/
+#define CAN_MOIPR118 (CAN_MO118_IPR)
+
+/** \brief 1EDC, Message Object Control Register */
+#define CAN_MO118_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019EDCu)
+
+/** Alias (User Manual Name) for CAN_MO118_STAT.
+* To use register names with standard convension, please use CAN_MO118_STAT.
+*/
+#define CAN_MOSTAT118 (CAN_MO118_STAT)
+
+/** \brief 1EEC, Message Object Acceptance Mask Register */
+#define CAN_MO119_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019EECu)
+
+/** Alias (User Manual Name) for CAN_MO119_AMR.
+* To use register names with standard convension, please use CAN_MO119_AMR.
+*/
+#define CAN_MOAMR119 (CAN_MO119_AMR)
+
+/** \brief 1EF8, Message Object Arbitration Register */
+#define CAN_MO119_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019EF8u)
+
+/** Alias (User Manual Name) for CAN_MO119_AR.
+* To use register names with standard convension, please use CAN_MO119_AR.
+*/
+#define CAN_MOAR119 (CAN_MO119_AR)
+
+/** \brief 1EFC, Message Object Control Register */
+#define CAN_MO119_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019EFCu)
+
+/** Alias (User Manual Name) for CAN_MO119_CTR.
+* To use register names with standard convension, please use CAN_MO119_CTR.
+*/
+#define CAN_MOCTR119 (CAN_MO119_CTR)
+
+/** \brief 1EF4, Message Object Data Register High */
+#define CAN_MO119_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019EF4u)
+
+/** Alias (User Manual Name) for CAN_MO119_DATAH.
+* To use register names with standard convension, please use CAN_MO119_DATAH.
+*/
+#define CAN_MODATAH119 (CAN_MO119_DATAH)
+
+/** \brief 1EF0, Message Object Data Register Low */
+#define CAN_MO119_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019EF0u)
+
+/** Alias (User Manual Name) for CAN_MO119_DATAL.
+* To use register names with standard convension, please use CAN_MO119_DATAL.
+*/
+#define CAN_MODATAL119 (CAN_MO119_DATAL)
+
+/** \brief 1EE0, Message Object Function Control Register */
+#define CAN_MO119_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019EE0u)
+
+/** Alias (User Manual Name) for CAN_MO119_EDATA0.
+* To use register names with standard convension, please use CAN_MO119_EDATA0.
+*/
+#define CAN_EMO119DATA0 (CAN_MO119_EDATA0)
+
+/** \brief 1EE4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO119_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019EE4u)
+
+/** Alias (User Manual Name) for CAN_MO119_EDATA1.
+* To use register names with standard convension, please use CAN_MO119_EDATA1.
+*/
+#define CAN_EMO119DATA1 (CAN_MO119_EDATA1)
+
+/** \brief 1EE8, Message Object Interrupt Pointer Register */
+#define CAN_MO119_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019EE8u)
+
+/** Alias (User Manual Name) for CAN_MO119_EDATA2.
+* To use register names with standard convension, please use CAN_MO119_EDATA2.
+*/
+#define CAN_EMO119DATA2 (CAN_MO119_EDATA2)
+
+/** \brief 1EEC, Message Object Acceptance Mask Register */
+#define CAN_MO119_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019EECu)
+
+/** Alias (User Manual Name) for CAN_MO119_EDATA3.
+* To use register names with standard convension, please use CAN_MO119_EDATA3.
+*/
+#define CAN_EMO119DATA3 (CAN_MO119_EDATA3)
+
+/** \brief 1EF0, Message Object Data Register Low */
+#define CAN_MO119_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019EF0u)
+
+/** Alias (User Manual Name) for CAN_MO119_EDATA4.
+* To use register names with standard convension, please use CAN_MO119_EDATA4.
+*/
+#define CAN_EMO119DATA4 (CAN_MO119_EDATA4)
+
+/** \brief 1EF4, Message Object Data Register High */
+#define CAN_MO119_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019EF4u)
+
+/** Alias (User Manual Name) for CAN_MO119_EDATA5.
+* To use register names with standard convension, please use CAN_MO119_EDATA5.
+*/
+#define CAN_EMO119DATA5 (CAN_MO119_EDATA5)
+
+/** \brief 1EF8, Message Object Arbitration Register */
+#define CAN_MO119_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019EF8u)
+
+/** Alias (User Manual Name) for CAN_MO119_EDATA6.
+* To use register names with standard convension, please use CAN_MO119_EDATA6.
+*/
+#define CAN_EMO119DATA6 (CAN_MO119_EDATA6)
+
+/** \brief 1EE0, Message Object Function Control Register */
+#define CAN_MO119_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019EE0u)
+
+/** Alias (User Manual Name) for CAN_MO119_FCR.
+* To use register names with standard convension, please use CAN_MO119_FCR.
+*/
+#define CAN_MOFCR119 (CAN_MO119_FCR)
+
+/** \brief 1EE4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO119_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019EE4u)
+
+/** Alias (User Manual Name) for CAN_MO119_FGPR.
+* To use register names with standard convension, please use CAN_MO119_FGPR.
+*/
+#define CAN_MOFGPR119 (CAN_MO119_FGPR)
+
+/** \brief 1EE8, Message Object Interrupt Pointer Register */
+#define CAN_MO119_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019EE8u)
+
+/** Alias (User Manual Name) for CAN_MO119_IPR.
+* To use register names with standard convension, please use CAN_MO119_IPR.
+*/
+#define CAN_MOIPR119 (CAN_MO119_IPR)
+
+/** \brief 1EFC, Message Object Control Register */
+#define CAN_MO119_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019EFCu)
+
+/** Alias (User Manual Name) for CAN_MO119_STAT.
+* To use register names with standard convension, please use CAN_MO119_STAT.
+*/
+#define CAN_MOSTAT119 (CAN_MO119_STAT)
+
+/** \brief 116C, Message Object Acceptance Mask Register */
+#define CAN_MO11_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001916Cu)
+
+/** Alias (User Manual Name) for CAN_MO11_AMR.
+* To use register names with standard convension, please use CAN_MO11_AMR.
+*/
+#define CAN_MOAMR11 (CAN_MO11_AMR)
+
+/** \brief 1178, Message Object Arbitration Register */
+#define CAN_MO11_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019178u)
+
+/** Alias (User Manual Name) for CAN_MO11_AR.
+* To use register names with standard convension, please use CAN_MO11_AR.
+*/
+#define CAN_MOAR11 (CAN_MO11_AR)
+
+/** \brief 117C, Message Object Control Register */
+#define CAN_MO11_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001917Cu)
+
+/** Alias (User Manual Name) for CAN_MO11_CTR.
+* To use register names with standard convension, please use CAN_MO11_CTR.
+*/
+#define CAN_MOCTR11 (CAN_MO11_CTR)
+
+/** \brief 1174, Message Object Data Register High */
+#define CAN_MO11_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019174u)
+
+/** Alias (User Manual Name) for CAN_MO11_DATAH.
+* To use register names with standard convension, please use CAN_MO11_DATAH.
+*/
+#define CAN_MODATAH11 (CAN_MO11_DATAH)
+
+/** \brief 1170, Message Object Data Register Low */
+#define CAN_MO11_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019170u)
+
+/** Alias (User Manual Name) for CAN_MO11_DATAL.
+* To use register names with standard convension, please use CAN_MO11_DATAL.
+*/
+#define CAN_MODATAL11 (CAN_MO11_DATAL)
+
+/** \brief 1160, Message Object Function Control Register */
+#define CAN_MO11_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019160u)
+
+/** Alias (User Manual Name) for CAN_MO11_EDATA0.
+* To use register names with standard convension, please use CAN_MO11_EDATA0.
+*/
+#define CAN_EMO11DATA0 (CAN_MO11_EDATA0)
+
+/** \brief 1164, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO11_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019164u)
+
+/** Alias (User Manual Name) for CAN_MO11_EDATA1.
+* To use register names with standard convension, please use CAN_MO11_EDATA1.
+*/
+#define CAN_EMO11DATA1 (CAN_MO11_EDATA1)
+
+/** \brief 1168, Message Object Interrupt Pointer Register */
+#define CAN_MO11_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019168u)
+
+/** Alias (User Manual Name) for CAN_MO11_EDATA2.
+* To use register names with standard convension, please use CAN_MO11_EDATA2.
+*/
+#define CAN_EMO11DATA2 (CAN_MO11_EDATA2)
+
+/** \brief 116C, Message Object Acceptance Mask Register */
+#define CAN_MO11_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001916Cu)
+
+/** Alias (User Manual Name) for CAN_MO11_EDATA3.
+* To use register names with standard convension, please use CAN_MO11_EDATA3.
+*/
+#define CAN_EMO11DATA3 (CAN_MO11_EDATA3)
+
+/** \brief 1170, Message Object Data Register Low */
+#define CAN_MO11_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019170u)
+
+/** Alias (User Manual Name) for CAN_MO11_EDATA4.
+* To use register names with standard convension, please use CAN_MO11_EDATA4.
+*/
+#define CAN_EMO11DATA4 (CAN_MO11_EDATA4)
+
+/** \brief 1174, Message Object Data Register High */
+#define CAN_MO11_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019174u)
+
+/** Alias (User Manual Name) for CAN_MO11_EDATA5.
+* To use register names with standard convension, please use CAN_MO11_EDATA5.
+*/
+#define CAN_EMO11DATA5 (CAN_MO11_EDATA5)
+
+/** \brief 1178, Message Object Arbitration Register */
+#define CAN_MO11_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019178u)
+
+/** Alias (User Manual Name) for CAN_MO11_EDATA6.
+* To use register names with standard convension, please use CAN_MO11_EDATA6.
+*/
+#define CAN_EMO11DATA6 (CAN_MO11_EDATA6)
+
+/** \brief 1160, Message Object Function Control Register */
+#define CAN_MO11_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019160u)
+
+/** Alias (User Manual Name) for CAN_MO11_FCR.
+* To use register names with standard convension, please use CAN_MO11_FCR.
+*/
+#define CAN_MOFCR11 (CAN_MO11_FCR)
+
+/** \brief 1164, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO11_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019164u)
+
+/** Alias (User Manual Name) for CAN_MO11_FGPR.
+* To use register names with standard convension, please use CAN_MO11_FGPR.
+*/
+#define CAN_MOFGPR11 (CAN_MO11_FGPR)
+
+/** \brief 1168, Message Object Interrupt Pointer Register */
+#define CAN_MO11_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019168u)
+
+/** Alias (User Manual Name) for CAN_MO11_IPR.
+* To use register names with standard convension, please use CAN_MO11_IPR.
+*/
+#define CAN_MOIPR11 (CAN_MO11_IPR)
+
+/** \brief 117C, Message Object Control Register */
+#define CAN_MO11_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001917Cu)
+
+/** Alias (User Manual Name) for CAN_MO11_STAT.
+* To use register names with standard convension, please use CAN_MO11_STAT.
+*/
+#define CAN_MOSTAT11 (CAN_MO11_STAT)
+
+/** \brief 1F0C, Message Object Acceptance Mask Register */
+#define CAN_MO120_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019F0Cu)
+
+/** Alias (User Manual Name) for CAN_MO120_AMR.
+* To use register names with standard convension, please use CAN_MO120_AMR.
+*/
+#define CAN_MOAMR120 (CAN_MO120_AMR)
+
+/** \brief 1F18, Message Object Arbitration Register */
+#define CAN_MO120_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019F18u)
+
+/** Alias (User Manual Name) for CAN_MO120_AR.
+* To use register names with standard convension, please use CAN_MO120_AR.
+*/
+#define CAN_MOAR120 (CAN_MO120_AR)
+
+/** \brief 1F1C, Message Object Control Register */
+#define CAN_MO120_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019F1Cu)
+
+/** Alias (User Manual Name) for CAN_MO120_CTR.
+* To use register names with standard convension, please use CAN_MO120_CTR.
+*/
+#define CAN_MOCTR120 (CAN_MO120_CTR)
+
+/** \brief 1F14, Message Object Data Register High */
+#define CAN_MO120_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019F14u)
+
+/** Alias (User Manual Name) for CAN_MO120_DATAH.
+* To use register names with standard convension, please use CAN_MO120_DATAH.
+*/
+#define CAN_MODATAH120 (CAN_MO120_DATAH)
+
+/** \brief 1F10, Message Object Data Register Low */
+#define CAN_MO120_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019F10u)
+
+/** Alias (User Manual Name) for CAN_MO120_DATAL.
+* To use register names with standard convension, please use CAN_MO120_DATAL.
+*/
+#define CAN_MODATAL120 (CAN_MO120_DATAL)
+
+/** \brief 1F00, Message Object Function Control Register */
+#define CAN_MO120_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019F00u)
+
+/** Alias (User Manual Name) for CAN_MO120_EDATA0.
+* To use register names with standard convension, please use CAN_MO120_EDATA0.
+*/
+#define CAN_EMO120DATA0 (CAN_MO120_EDATA0)
+
+/** \brief 1F04, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO120_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019F04u)
+
+/** Alias (User Manual Name) for CAN_MO120_EDATA1.
+* To use register names with standard convension, please use CAN_MO120_EDATA1.
+*/
+#define CAN_EMO120DATA1 (CAN_MO120_EDATA1)
+
+/** \brief 1F08, Message Object Interrupt Pointer Register */
+#define CAN_MO120_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019F08u)
+
+/** Alias (User Manual Name) for CAN_MO120_EDATA2.
+* To use register names with standard convension, please use CAN_MO120_EDATA2.
+*/
+#define CAN_EMO120DATA2 (CAN_MO120_EDATA2)
+
+/** \brief 1F0C, Message Object Acceptance Mask Register */
+#define CAN_MO120_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019F0Cu)
+
+/** Alias (User Manual Name) for CAN_MO120_EDATA3.
+* To use register names with standard convension, please use CAN_MO120_EDATA3.
+*/
+#define CAN_EMO120DATA3 (CAN_MO120_EDATA3)
+
+/** \brief 1F10, Message Object Data Register Low */
+#define CAN_MO120_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019F10u)
+
+/** Alias (User Manual Name) for CAN_MO120_EDATA4.
+* To use register names with standard convension, please use CAN_MO120_EDATA4.
+*/
+#define CAN_EMO120DATA4 (CAN_MO120_EDATA4)
+
+/** \brief 1F14, Message Object Data Register High */
+#define CAN_MO120_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019F14u)
+
+/** Alias (User Manual Name) for CAN_MO120_EDATA5.
+* To use register names with standard convension, please use CAN_MO120_EDATA5.
+*/
+#define CAN_EMO120DATA5 (CAN_MO120_EDATA5)
+
+/** \brief 1F18, Message Object Arbitration Register */
+#define CAN_MO120_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019F18u)
+
+/** Alias (User Manual Name) for CAN_MO120_EDATA6.
+* To use register names with standard convension, please use CAN_MO120_EDATA6.
+*/
+#define CAN_EMO120DATA6 (CAN_MO120_EDATA6)
+
+/** \brief 1F00, Message Object Function Control Register */
+#define CAN_MO120_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019F00u)
+
+/** Alias (User Manual Name) for CAN_MO120_FCR.
+* To use register names with standard convension, please use CAN_MO120_FCR.
+*/
+#define CAN_MOFCR120 (CAN_MO120_FCR)
+
+/** \brief 1F04, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO120_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019F04u)
+
+/** Alias (User Manual Name) for CAN_MO120_FGPR.
+* To use register names with standard convension, please use CAN_MO120_FGPR.
+*/
+#define CAN_MOFGPR120 (CAN_MO120_FGPR)
+
+/** \brief 1F08, Message Object Interrupt Pointer Register */
+#define CAN_MO120_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019F08u)
+
+/** Alias (User Manual Name) for CAN_MO120_IPR.
+* To use register names with standard convension, please use CAN_MO120_IPR.
+*/
+#define CAN_MOIPR120 (CAN_MO120_IPR)
+
+/** \brief 1F1C, Message Object Control Register */
+#define CAN_MO120_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019F1Cu)
+
+/** Alias (User Manual Name) for CAN_MO120_STAT.
+* To use register names with standard convension, please use CAN_MO120_STAT.
+*/
+#define CAN_MOSTAT120 (CAN_MO120_STAT)
+
+/** \brief 1F2C, Message Object Acceptance Mask Register */
+#define CAN_MO121_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019F2Cu)
+
+/** Alias (User Manual Name) for CAN_MO121_AMR.
+* To use register names with standard convension, please use CAN_MO121_AMR.
+*/
+#define CAN_MOAMR121 (CAN_MO121_AMR)
+
+/** \brief 1F38, Message Object Arbitration Register */
+#define CAN_MO121_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019F38u)
+
+/** Alias (User Manual Name) for CAN_MO121_AR.
+* To use register names with standard convension, please use CAN_MO121_AR.
+*/
+#define CAN_MOAR121 (CAN_MO121_AR)
+
+/** \brief 1F3C, Message Object Control Register */
+#define CAN_MO121_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019F3Cu)
+
+/** Alias (User Manual Name) for CAN_MO121_CTR.
+* To use register names with standard convension, please use CAN_MO121_CTR.
+*/
+#define CAN_MOCTR121 (CAN_MO121_CTR)
+
+/** \brief 1F34, Message Object Data Register High */
+#define CAN_MO121_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019F34u)
+
+/** Alias (User Manual Name) for CAN_MO121_DATAH.
+* To use register names with standard convension, please use CAN_MO121_DATAH.
+*/
+#define CAN_MODATAH121 (CAN_MO121_DATAH)
+
+/** \brief 1F30, Message Object Data Register Low */
+#define CAN_MO121_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019F30u)
+
+/** Alias (User Manual Name) for CAN_MO121_DATAL.
+* To use register names with standard convension, please use CAN_MO121_DATAL.
+*/
+#define CAN_MODATAL121 (CAN_MO121_DATAL)
+
+/** \brief 1F20, Message Object Function Control Register */
+#define CAN_MO121_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019F20u)
+
+/** Alias (User Manual Name) for CAN_MO121_EDATA0.
+* To use register names with standard convension, please use CAN_MO121_EDATA0.
+*/
+#define CAN_EMO121DATA0 (CAN_MO121_EDATA0)
+
+/** \brief 1F24, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO121_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019F24u)
+
+/** Alias (User Manual Name) for CAN_MO121_EDATA1.
+* To use register names with standard convension, please use CAN_MO121_EDATA1.
+*/
+#define CAN_EMO121DATA1 (CAN_MO121_EDATA1)
+
+/** \brief 1F28, Message Object Interrupt Pointer Register */
+#define CAN_MO121_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019F28u)
+
+/** Alias (User Manual Name) for CAN_MO121_EDATA2.
+* To use register names with standard convension, please use CAN_MO121_EDATA2.
+*/
+#define CAN_EMO121DATA2 (CAN_MO121_EDATA2)
+
+/** \brief 1F2C, Message Object Acceptance Mask Register */
+#define CAN_MO121_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019F2Cu)
+
+/** Alias (User Manual Name) for CAN_MO121_EDATA3.
+* To use register names with standard convension, please use CAN_MO121_EDATA3.
+*/
+#define CAN_EMO121DATA3 (CAN_MO121_EDATA3)
+
+/** \brief 1F30, Message Object Data Register Low */
+#define CAN_MO121_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019F30u)
+
+/** Alias (User Manual Name) for CAN_MO121_EDATA4.
+* To use register names with standard convension, please use CAN_MO121_EDATA4.
+*/
+#define CAN_EMO121DATA4 (CAN_MO121_EDATA4)
+
+/** \brief 1F34, Message Object Data Register High */
+#define CAN_MO121_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019F34u)
+
+/** Alias (User Manual Name) for CAN_MO121_EDATA5.
+* To use register names with standard convension, please use CAN_MO121_EDATA5.
+*/
+#define CAN_EMO121DATA5 (CAN_MO121_EDATA5)
+
+/** \brief 1F38, Message Object Arbitration Register */
+#define CAN_MO121_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019F38u)
+
+/** Alias (User Manual Name) for CAN_MO121_EDATA6.
+* To use register names with standard convension, please use CAN_MO121_EDATA6.
+*/
+#define CAN_EMO121DATA6 (CAN_MO121_EDATA6)
+
+/** \brief 1F20, Message Object Function Control Register */
+#define CAN_MO121_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019F20u)
+
+/** Alias (User Manual Name) for CAN_MO121_FCR.
+* To use register names with standard convension, please use CAN_MO121_FCR.
+*/
+#define CAN_MOFCR121 (CAN_MO121_FCR)
+
+/** \brief 1F24, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO121_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019F24u)
+
+/** Alias (User Manual Name) for CAN_MO121_FGPR.
+* To use register names with standard convension, please use CAN_MO121_FGPR.
+*/
+#define CAN_MOFGPR121 (CAN_MO121_FGPR)
+
+/** \brief 1F28, Message Object Interrupt Pointer Register */
+#define CAN_MO121_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019F28u)
+
+/** Alias (User Manual Name) for CAN_MO121_IPR.
+* To use register names with standard convension, please use CAN_MO121_IPR.
+*/
+#define CAN_MOIPR121 (CAN_MO121_IPR)
+
+/** \brief 1F3C, Message Object Control Register */
+#define CAN_MO121_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019F3Cu)
+
+/** Alias (User Manual Name) for CAN_MO121_STAT.
+* To use register names with standard convension, please use CAN_MO121_STAT.
+*/
+#define CAN_MOSTAT121 (CAN_MO121_STAT)
+
+/** \brief 1F4C, Message Object Acceptance Mask Register */
+#define CAN_MO122_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019F4Cu)
+
+/** Alias (User Manual Name) for CAN_MO122_AMR.
+* To use register names with standard convension, please use CAN_MO122_AMR.
+*/
+#define CAN_MOAMR122 (CAN_MO122_AMR)
+
+/** \brief 1F58, Message Object Arbitration Register */
+#define CAN_MO122_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019F58u)
+
+/** Alias (User Manual Name) for CAN_MO122_AR.
+* To use register names with standard convension, please use CAN_MO122_AR.
+*/
+#define CAN_MOAR122 (CAN_MO122_AR)
+
+/** \brief 1F5C, Message Object Control Register */
+#define CAN_MO122_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019F5Cu)
+
+/** Alias (User Manual Name) for CAN_MO122_CTR.
+* To use register names with standard convension, please use CAN_MO122_CTR.
+*/
+#define CAN_MOCTR122 (CAN_MO122_CTR)
+
+/** \brief 1F54, Message Object Data Register High */
+#define CAN_MO122_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019F54u)
+
+/** Alias (User Manual Name) for CAN_MO122_DATAH.
+* To use register names with standard convension, please use CAN_MO122_DATAH.
+*/
+#define CAN_MODATAH122 (CAN_MO122_DATAH)
+
+/** \brief 1F50, Message Object Data Register Low */
+#define CAN_MO122_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019F50u)
+
+/** Alias (User Manual Name) for CAN_MO122_DATAL.
+* To use register names with standard convension, please use CAN_MO122_DATAL.
+*/
+#define CAN_MODATAL122 (CAN_MO122_DATAL)
+
+/** \brief 1F40, Message Object Function Control Register */
+#define CAN_MO122_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019F40u)
+
+/** Alias (User Manual Name) for CAN_MO122_EDATA0.
+* To use register names with standard convension, please use CAN_MO122_EDATA0.
+*/
+#define CAN_EMO122DATA0 (CAN_MO122_EDATA0)
+
+/** \brief 1F44, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO122_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019F44u)
+
+/** Alias (User Manual Name) for CAN_MO122_EDATA1.
+* To use register names with standard convension, please use CAN_MO122_EDATA1.
+*/
+#define CAN_EMO122DATA1 (CAN_MO122_EDATA1)
+
+/** \brief 1F48, Message Object Interrupt Pointer Register */
+#define CAN_MO122_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019F48u)
+
+/** Alias (User Manual Name) for CAN_MO122_EDATA2.
+* To use register names with standard convension, please use CAN_MO122_EDATA2.
+*/
+#define CAN_EMO122DATA2 (CAN_MO122_EDATA2)
+
+/** \brief 1F4C, Message Object Acceptance Mask Register */
+#define CAN_MO122_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019F4Cu)
+
+/** Alias (User Manual Name) for CAN_MO122_EDATA3.
+* To use register names with standard convension, please use CAN_MO122_EDATA3.
+*/
+#define CAN_EMO122DATA3 (CAN_MO122_EDATA3)
+
+/** \brief 1F50, Message Object Data Register Low */
+#define CAN_MO122_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019F50u)
+
+/** Alias (User Manual Name) for CAN_MO122_EDATA4.
+* To use register names with standard convension, please use CAN_MO122_EDATA4.
+*/
+#define CAN_EMO122DATA4 (CAN_MO122_EDATA4)
+
+/** \brief 1F54, Message Object Data Register High */
+#define CAN_MO122_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019F54u)
+
+/** Alias (User Manual Name) for CAN_MO122_EDATA5.
+* To use register names with standard convension, please use CAN_MO122_EDATA5.
+*/
+#define CAN_EMO122DATA5 (CAN_MO122_EDATA5)
+
+/** \brief 1F58, Message Object Arbitration Register */
+#define CAN_MO122_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019F58u)
+
+/** Alias (User Manual Name) for CAN_MO122_EDATA6.
+* To use register names with standard convension, please use CAN_MO122_EDATA6.
+*/
+#define CAN_EMO122DATA6 (CAN_MO122_EDATA6)
+
+/** \brief 1F40, Message Object Function Control Register */
+#define CAN_MO122_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019F40u)
+
+/** Alias (User Manual Name) for CAN_MO122_FCR.
+* To use register names with standard convension, please use CAN_MO122_FCR.
+*/
+#define CAN_MOFCR122 (CAN_MO122_FCR)
+
+/** \brief 1F44, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO122_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019F44u)
+
+/** Alias (User Manual Name) for CAN_MO122_FGPR.
+* To use register names with standard convension, please use CAN_MO122_FGPR.
+*/
+#define CAN_MOFGPR122 (CAN_MO122_FGPR)
+
+/** \brief 1F48, Message Object Interrupt Pointer Register */
+#define CAN_MO122_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019F48u)
+
+/** Alias (User Manual Name) for CAN_MO122_IPR.
+* To use register names with standard convension, please use CAN_MO122_IPR.
+*/
+#define CAN_MOIPR122 (CAN_MO122_IPR)
+
+/** \brief 1F5C, Message Object Control Register */
+#define CAN_MO122_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019F5Cu)
+
+/** Alias (User Manual Name) for CAN_MO122_STAT.
+* To use register names with standard convension, please use CAN_MO122_STAT.
+*/
+#define CAN_MOSTAT122 (CAN_MO122_STAT)
+
+/** \brief 1F6C, Message Object Acceptance Mask Register */
+#define CAN_MO123_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019F6Cu)
+
+/** Alias (User Manual Name) for CAN_MO123_AMR.
+* To use register names with standard convension, please use CAN_MO123_AMR.
+*/
+#define CAN_MOAMR123 (CAN_MO123_AMR)
+
+/** \brief 1F78, Message Object Arbitration Register */
+#define CAN_MO123_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019F78u)
+
+/** Alias (User Manual Name) for CAN_MO123_AR.
+* To use register names with standard convension, please use CAN_MO123_AR.
+*/
+#define CAN_MOAR123 (CAN_MO123_AR)
+
+/** \brief 1F7C, Message Object Control Register */
+#define CAN_MO123_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019F7Cu)
+
+/** Alias (User Manual Name) for CAN_MO123_CTR.
+* To use register names with standard convension, please use CAN_MO123_CTR.
+*/
+#define CAN_MOCTR123 (CAN_MO123_CTR)
+
+/** \brief 1F74, Message Object Data Register High */
+#define CAN_MO123_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019F74u)
+
+/** Alias (User Manual Name) for CAN_MO123_DATAH.
+* To use register names with standard convension, please use CAN_MO123_DATAH.
+*/
+#define CAN_MODATAH123 (CAN_MO123_DATAH)
+
+/** \brief 1F70, Message Object Data Register Low */
+#define CAN_MO123_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019F70u)
+
+/** Alias (User Manual Name) for CAN_MO123_DATAL.
+* To use register names with standard convension, please use CAN_MO123_DATAL.
+*/
+#define CAN_MODATAL123 (CAN_MO123_DATAL)
+
+/** \brief 1F60, Message Object Function Control Register */
+#define CAN_MO123_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019F60u)
+
+/** Alias (User Manual Name) for CAN_MO123_EDATA0.
+* To use register names with standard convension, please use CAN_MO123_EDATA0.
+*/
+#define CAN_EMO123DATA0 (CAN_MO123_EDATA0)
+
+/** \brief 1F64, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO123_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019F64u)
+
+/** Alias (User Manual Name) for CAN_MO123_EDATA1.
+* To use register names with standard convension, please use CAN_MO123_EDATA1.
+*/
+#define CAN_EMO123DATA1 (CAN_MO123_EDATA1)
+
+/** \brief 1F68, Message Object Interrupt Pointer Register */
+#define CAN_MO123_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019F68u)
+
+/** Alias (User Manual Name) for CAN_MO123_EDATA2.
+* To use register names with standard convension, please use CAN_MO123_EDATA2.
+*/
+#define CAN_EMO123DATA2 (CAN_MO123_EDATA2)
+
+/** \brief 1F6C, Message Object Acceptance Mask Register */
+#define CAN_MO123_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019F6Cu)
+
+/** Alias (User Manual Name) for CAN_MO123_EDATA3.
+* To use register names with standard convension, please use CAN_MO123_EDATA3.
+*/
+#define CAN_EMO123DATA3 (CAN_MO123_EDATA3)
+
+/** \brief 1F70, Message Object Data Register Low */
+#define CAN_MO123_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019F70u)
+
+/** Alias (User Manual Name) for CAN_MO123_EDATA4.
+* To use register names with standard convension, please use CAN_MO123_EDATA4.
+*/
+#define CAN_EMO123DATA4 (CAN_MO123_EDATA4)
+
+/** \brief 1F74, Message Object Data Register High */
+#define CAN_MO123_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019F74u)
+
+/** Alias (User Manual Name) for CAN_MO123_EDATA5.
+* To use register names with standard convension, please use CAN_MO123_EDATA5.
+*/
+#define CAN_EMO123DATA5 (CAN_MO123_EDATA5)
+
+/** \brief 1F78, Message Object Arbitration Register */
+#define CAN_MO123_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019F78u)
+
+/** Alias (User Manual Name) for CAN_MO123_EDATA6.
+* To use register names with standard convension, please use CAN_MO123_EDATA6.
+*/
+#define CAN_EMO123DATA6 (CAN_MO123_EDATA6)
+
+/** \brief 1F60, Message Object Function Control Register */
+#define CAN_MO123_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019F60u)
+
+/** Alias (User Manual Name) for CAN_MO123_FCR.
+* To use register names with standard convension, please use CAN_MO123_FCR.
+*/
+#define CAN_MOFCR123 (CAN_MO123_FCR)
+
+/** \brief 1F64, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO123_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019F64u)
+
+/** Alias (User Manual Name) for CAN_MO123_FGPR.
+* To use register names with standard convension, please use CAN_MO123_FGPR.
+*/
+#define CAN_MOFGPR123 (CAN_MO123_FGPR)
+
+/** \brief 1F68, Message Object Interrupt Pointer Register */
+#define CAN_MO123_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019F68u)
+
+/** Alias (User Manual Name) for CAN_MO123_IPR.
+* To use register names with standard convension, please use CAN_MO123_IPR.
+*/
+#define CAN_MOIPR123 (CAN_MO123_IPR)
+
+/** \brief 1F7C, Message Object Control Register */
+#define CAN_MO123_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019F7Cu)
+
+/** Alias (User Manual Name) for CAN_MO123_STAT.
+* To use register names with standard convension, please use CAN_MO123_STAT.
+*/
+#define CAN_MOSTAT123 (CAN_MO123_STAT)
+
+/** \brief 1F8C, Message Object Acceptance Mask Register */
+#define CAN_MO124_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019F8Cu)
+
+/** Alias (User Manual Name) for CAN_MO124_AMR.
+* To use register names with standard convension, please use CAN_MO124_AMR.
+*/
+#define CAN_MOAMR124 (CAN_MO124_AMR)
+
+/** \brief 1F98, Message Object Arbitration Register */
+#define CAN_MO124_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019F98u)
+
+/** Alias (User Manual Name) for CAN_MO124_AR.
+* To use register names with standard convension, please use CAN_MO124_AR.
+*/
+#define CAN_MOAR124 (CAN_MO124_AR)
+
+/** \brief 1F9C, Message Object Control Register */
+#define CAN_MO124_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019F9Cu)
+
+/** Alias (User Manual Name) for CAN_MO124_CTR.
+* To use register names with standard convension, please use CAN_MO124_CTR.
+*/
+#define CAN_MOCTR124 (CAN_MO124_CTR)
+
+/** \brief 1F94, Message Object Data Register High */
+#define CAN_MO124_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019F94u)
+
+/** Alias (User Manual Name) for CAN_MO124_DATAH.
+* To use register names with standard convension, please use CAN_MO124_DATAH.
+*/
+#define CAN_MODATAH124 (CAN_MO124_DATAH)
+
+/** \brief 1F90, Message Object Data Register Low */
+#define CAN_MO124_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019F90u)
+
+/** Alias (User Manual Name) for CAN_MO124_DATAL.
+* To use register names with standard convension, please use CAN_MO124_DATAL.
+*/
+#define CAN_MODATAL124 (CAN_MO124_DATAL)
+
+/** \brief 1F80, Message Object Function Control Register */
+#define CAN_MO124_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019F80u)
+
+/** Alias (User Manual Name) for CAN_MO124_EDATA0.
+* To use register names with standard convension, please use CAN_MO124_EDATA0.
+*/
+#define CAN_EMO124DATA0 (CAN_MO124_EDATA0)
+
+/** \brief 1F84, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO124_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019F84u)
+
+/** Alias (User Manual Name) for CAN_MO124_EDATA1.
+* To use register names with standard convension, please use CAN_MO124_EDATA1.
+*/
+#define CAN_EMO124DATA1 (CAN_MO124_EDATA1)
+
+/** \brief 1F88, Message Object Interrupt Pointer Register */
+#define CAN_MO124_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019F88u)
+
+/** Alias (User Manual Name) for CAN_MO124_EDATA2.
+* To use register names with standard convension, please use CAN_MO124_EDATA2.
+*/
+#define CAN_EMO124DATA2 (CAN_MO124_EDATA2)
+
+/** \brief 1F8C, Message Object Acceptance Mask Register */
+#define CAN_MO124_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019F8Cu)
+
+/** Alias (User Manual Name) for CAN_MO124_EDATA3.
+* To use register names with standard convension, please use CAN_MO124_EDATA3.
+*/
+#define CAN_EMO124DATA3 (CAN_MO124_EDATA3)
+
+/** \brief 1F90, Message Object Data Register Low */
+#define CAN_MO124_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019F90u)
+
+/** Alias (User Manual Name) for CAN_MO124_EDATA4.
+* To use register names with standard convension, please use CAN_MO124_EDATA4.
+*/
+#define CAN_EMO124DATA4 (CAN_MO124_EDATA4)
+
+/** \brief 1F94, Message Object Data Register High */
+#define CAN_MO124_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019F94u)
+
+/** Alias (User Manual Name) for CAN_MO124_EDATA5.
+* To use register names with standard convension, please use CAN_MO124_EDATA5.
+*/
+#define CAN_EMO124DATA5 (CAN_MO124_EDATA5)
+
+/** \brief 1F98, Message Object Arbitration Register */
+#define CAN_MO124_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019F98u)
+
+/** Alias (User Manual Name) for CAN_MO124_EDATA6.
+* To use register names with standard convension, please use CAN_MO124_EDATA6.
+*/
+#define CAN_EMO124DATA6 (CAN_MO124_EDATA6)
+
+/** \brief 1F80, Message Object Function Control Register */
+#define CAN_MO124_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019F80u)
+
+/** Alias (User Manual Name) for CAN_MO124_FCR.
+* To use register names with standard convension, please use CAN_MO124_FCR.
+*/
+#define CAN_MOFCR124 (CAN_MO124_FCR)
+
+/** \brief 1F84, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO124_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019F84u)
+
+/** Alias (User Manual Name) for CAN_MO124_FGPR.
+* To use register names with standard convension, please use CAN_MO124_FGPR.
+*/
+#define CAN_MOFGPR124 (CAN_MO124_FGPR)
+
+/** \brief 1F88, Message Object Interrupt Pointer Register */
+#define CAN_MO124_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019F88u)
+
+/** Alias (User Manual Name) for CAN_MO124_IPR.
+* To use register names with standard convension, please use CAN_MO124_IPR.
+*/
+#define CAN_MOIPR124 (CAN_MO124_IPR)
+
+/** \brief 1F9C, Message Object Control Register */
+#define CAN_MO124_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019F9Cu)
+
+/** Alias (User Manual Name) for CAN_MO124_STAT.
+* To use register names with standard convension, please use CAN_MO124_STAT.
+*/
+#define CAN_MOSTAT124 (CAN_MO124_STAT)
+
+/** \brief 1FAC, Message Object Acceptance Mask Register */
+#define CAN_MO125_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019FACu)
+
+/** Alias (User Manual Name) for CAN_MO125_AMR.
+* To use register names with standard convension, please use CAN_MO125_AMR.
+*/
+#define CAN_MOAMR125 (CAN_MO125_AMR)
+
+/** \brief 1FB8, Message Object Arbitration Register */
+#define CAN_MO125_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019FB8u)
+
+/** Alias (User Manual Name) for CAN_MO125_AR.
+* To use register names with standard convension, please use CAN_MO125_AR.
+*/
+#define CAN_MOAR125 (CAN_MO125_AR)
+
+/** \brief 1FBC, Message Object Control Register */
+#define CAN_MO125_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019FBCu)
+
+/** Alias (User Manual Name) for CAN_MO125_CTR.
+* To use register names with standard convension, please use CAN_MO125_CTR.
+*/
+#define CAN_MOCTR125 (CAN_MO125_CTR)
+
+/** \brief 1FB4, Message Object Data Register High */
+#define CAN_MO125_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019FB4u)
+
+/** Alias (User Manual Name) for CAN_MO125_DATAH.
+* To use register names with standard convension, please use CAN_MO125_DATAH.
+*/
+#define CAN_MODATAH125 (CAN_MO125_DATAH)
+
+/** \brief 1FB0, Message Object Data Register Low */
+#define CAN_MO125_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019FB0u)
+
+/** Alias (User Manual Name) for CAN_MO125_DATAL.
+* To use register names with standard convension, please use CAN_MO125_DATAL.
+*/
+#define CAN_MODATAL125 (CAN_MO125_DATAL)
+
+/** \brief 1FA0, Message Object Function Control Register */
+#define CAN_MO125_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019FA0u)
+
+/** Alias (User Manual Name) for CAN_MO125_EDATA0.
+* To use register names with standard convension, please use CAN_MO125_EDATA0.
+*/
+#define CAN_EMO125DATA0 (CAN_MO125_EDATA0)
+
+/** \brief 1FA4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO125_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019FA4u)
+
+/** Alias (User Manual Name) for CAN_MO125_EDATA1.
+* To use register names with standard convension, please use CAN_MO125_EDATA1.
+*/
+#define CAN_EMO125DATA1 (CAN_MO125_EDATA1)
+
+/** \brief 1FA8, Message Object Interrupt Pointer Register */
+#define CAN_MO125_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019FA8u)
+
+/** Alias (User Manual Name) for CAN_MO125_EDATA2.
+* To use register names with standard convension, please use CAN_MO125_EDATA2.
+*/
+#define CAN_EMO125DATA2 (CAN_MO125_EDATA2)
+
+/** \brief 1FAC, Message Object Acceptance Mask Register */
+#define CAN_MO125_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019FACu)
+
+/** Alias (User Manual Name) for CAN_MO125_EDATA3.
+* To use register names with standard convension, please use CAN_MO125_EDATA3.
+*/
+#define CAN_EMO125DATA3 (CAN_MO125_EDATA3)
+
+/** \brief 1FB0, Message Object Data Register Low */
+#define CAN_MO125_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019FB0u)
+
+/** Alias (User Manual Name) for CAN_MO125_EDATA4.
+* To use register names with standard convension, please use CAN_MO125_EDATA4.
+*/
+#define CAN_EMO125DATA4 (CAN_MO125_EDATA4)
+
+/** \brief 1FB4, Message Object Data Register High */
+#define CAN_MO125_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019FB4u)
+
+/** Alias (User Manual Name) for CAN_MO125_EDATA5.
+* To use register names with standard convension, please use CAN_MO125_EDATA5.
+*/
+#define CAN_EMO125DATA5 (CAN_MO125_EDATA5)
+
+/** \brief 1FB8, Message Object Arbitration Register */
+#define CAN_MO125_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019FB8u)
+
+/** Alias (User Manual Name) for CAN_MO125_EDATA6.
+* To use register names with standard convension, please use CAN_MO125_EDATA6.
+*/
+#define CAN_EMO125DATA6 (CAN_MO125_EDATA6)
+
+/** \brief 1FA0, Message Object Function Control Register */
+#define CAN_MO125_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019FA0u)
+
+/** Alias (User Manual Name) for CAN_MO125_FCR.
+* To use register names with standard convension, please use CAN_MO125_FCR.
+*/
+#define CAN_MOFCR125 (CAN_MO125_FCR)
+
+/** \brief 1FA4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO125_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019FA4u)
+
+/** Alias (User Manual Name) for CAN_MO125_FGPR.
+* To use register names with standard convension, please use CAN_MO125_FGPR.
+*/
+#define CAN_MOFGPR125 (CAN_MO125_FGPR)
+
+/** \brief 1FA8, Message Object Interrupt Pointer Register */
+#define CAN_MO125_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019FA8u)
+
+/** Alias (User Manual Name) for CAN_MO125_IPR.
+* To use register names with standard convension, please use CAN_MO125_IPR.
+*/
+#define CAN_MOIPR125 (CAN_MO125_IPR)
+
+/** \brief 1FBC, Message Object Control Register */
+#define CAN_MO125_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019FBCu)
+
+/** Alias (User Manual Name) for CAN_MO125_STAT.
+* To use register names with standard convension, please use CAN_MO125_STAT.
+*/
+#define CAN_MOSTAT125 (CAN_MO125_STAT)
+
+/** \brief 1FCC, Message Object Acceptance Mask Register */
+#define CAN_MO126_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019FCCu)
+
+/** Alias (User Manual Name) for CAN_MO126_AMR.
+* To use register names with standard convension, please use CAN_MO126_AMR.
+*/
+#define CAN_MOAMR126 (CAN_MO126_AMR)
+
+/** \brief 1FD8, Message Object Arbitration Register */
+#define CAN_MO126_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019FD8u)
+
+/** Alias (User Manual Name) for CAN_MO126_AR.
+* To use register names with standard convension, please use CAN_MO126_AR.
+*/
+#define CAN_MOAR126 (CAN_MO126_AR)
+
+/** \brief 1FDC, Message Object Control Register */
+#define CAN_MO126_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019FDCu)
+
+/** Alias (User Manual Name) for CAN_MO126_CTR.
+* To use register names with standard convension, please use CAN_MO126_CTR.
+*/
+#define CAN_MOCTR126 (CAN_MO126_CTR)
+
+/** \brief 1FD4, Message Object Data Register High */
+#define CAN_MO126_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019FD4u)
+
+/** Alias (User Manual Name) for CAN_MO126_DATAH.
+* To use register names with standard convension, please use CAN_MO126_DATAH.
+*/
+#define CAN_MODATAH126 (CAN_MO126_DATAH)
+
+/** \brief 1FD0, Message Object Data Register Low */
+#define CAN_MO126_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019FD0u)
+
+/** Alias (User Manual Name) for CAN_MO126_DATAL.
+* To use register names with standard convension, please use CAN_MO126_DATAL.
+*/
+#define CAN_MODATAL126 (CAN_MO126_DATAL)
+
+/** \brief 1FC0, Message Object Function Control Register */
+#define CAN_MO126_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019FC0u)
+
+/** Alias (User Manual Name) for CAN_MO126_EDATA0.
+* To use register names with standard convension, please use CAN_MO126_EDATA0.
+*/
+#define CAN_EMO126DATA0 (CAN_MO126_EDATA0)
+
+/** \brief 1FC4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO126_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019FC4u)
+
+/** Alias (User Manual Name) for CAN_MO126_EDATA1.
+* To use register names with standard convension, please use CAN_MO126_EDATA1.
+*/
+#define CAN_EMO126DATA1 (CAN_MO126_EDATA1)
+
+/** \brief 1FC8, Message Object Interrupt Pointer Register */
+#define CAN_MO126_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019FC8u)
+
+/** Alias (User Manual Name) for CAN_MO126_EDATA2.
+* To use register names with standard convension, please use CAN_MO126_EDATA2.
+*/
+#define CAN_EMO126DATA2 (CAN_MO126_EDATA2)
+
+/** \brief 1FCC, Message Object Acceptance Mask Register */
+#define CAN_MO126_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019FCCu)
+
+/** Alias (User Manual Name) for CAN_MO126_EDATA3.
+* To use register names with standard convension, please use CAN_MO126_EDATA3.
+*/
+#define CAN_EMO126DATA3 (CAN_MO126_EDATA3)
+
+/** \brief 1FD0, Message Object Data Register Low */
+#define CAN_MO126_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019FD0u)
+
+/** Alias (User Manual Name) for CAN_MO126_EDATA4.
+* To use register names with standard convension, please use CAN_MO126_EDATA4.
+*/
+#define CAN_EMO126DATA4 (CAN_MO126_EDATA4)
+
+/** \brief 1FD4, Message Object Data Register High */
+#define CAN_MO126_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019FD4u)
+
+/** Alias (User Manual Name) for CAN_MO126_EDATA5.
+* To use register names with standard convension, please use CAN_MO126_EDATA5.
+*/
+#define CAN_EMO126DATA5 (CAN_MO126_EDATA5)
+
+/** \brief 1FD8, Message Object Arbitration Register */
+#define CAN_MO126_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019FD8u)
+
+/** Alias (User Manual Name) for CAN_MO126_EDATA6.
+* To use register names with standard convension, please use CAN_MO126_EDATA6.
+*/
+#define CAN_EMO126DATA6 (CAN_MO126_EDATA6)
+
+/** \brief 1FC0, Message Object Function Control Register */
+#define CAN_MO126_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019FC0u)
+
+/** Alias (User Manual Name) for CAN_MO126_FCR.
+* To use register names with standard convension, please use CAN_MO126_FCR.
+*/
+#define CAN_MOFCR126 (CAN_MO126_FCR)
+
+/** \brief 1FC4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO126_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019FC4u)
+
+/** Alias (User Manual Name) for CAN_MO126_FGPR.
+* To use register names with standard convension, please use CAN_MO126_FGPR.
+*/
+#define CAN_MOFGPR126 (CAN_MO126_FGPR)
+
+/** \brief 1FC8, Message Object Interrupt Pointer Register */
+#define CAN_MO126_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019FC8u)
+
+/** Alias (User Manual Name) for CAN_MO126_IPR.
+* To use register names with standard convension, please use CAN_MO126_IPR.
+*/
+#define CAN_MOIPR126 (CAN_MO126_IPR)
+
+/** \brief 1FDC, Message Object Control Register */
+#define CAN_MO126_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019FDCu)
+
+/** Alias (User Manual Name) for CAN_MO126_STAT.
+* To use register names with standard convension, please use CAN_MO126_STAT.
+*/
+#define CAN_MOSTAT126 (CAN_MO126_STAT)
+
+/** \brief 1FEC, Message Object Acceptance Mask Register */
+#define CAN_MO127_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019FECu)
+
+/** Alias (User Manual Name) for CAN_MO127_AMR.
+* To use register names with standard convension, please use CAN_MO127_AMR.
+*/
+#define CAN_MOAMR127 (CAN_MO127_AMR)
+
+/** \brief 1FF8, Message Object Arbitration Register */
+#define CAN_MO127_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019FF8u)
+
+/** Alias (User Manual Name) for CAN_MO127_AR.
+* To use register names with standard convension, please use CAN_MO127_AR.
+*/
+#define CAN_MOAR127 (CAN_MO127_AR)
+
+/** \brief 1FFC, Message Object Control Register */
+#define CAN_MO127_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019FFCu)
+
+/** Alias (User Manual Name) for CAN_MO127_CTR.
+* To use register names with standard convension, please use CAN_MO127_CTR.
+*/
+#define CAN_MOCTR127 (CAN_MO127_CTR)
+
+/** \brief 1FF4, Message Object Data Register High */
+#define CAN_MO127_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019FF4u)
+
+/** Alias (User Manual Name) for CAN_MO127_DATAH.
+* To use register names with standard convension, please use CAN_MO127_DATAH.
+*/
+#define CAN_MODATAH127 (CAN_MO127_DATAH)
+
+/** \brief 1FF0, Message Object Data Register Low */
+#define CAN_MO127_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019FF0u)
+
+/** Alias (User Manual Name) for CAN_MO127_DATAL.
+* To use register names with standard convension, please use CAN_MO127_DATAL.
+*/
+#define CAN_MODATAL127 (CAN_MO127_DATAL)
+
+/** \brief 1FE0, Message Object Function Control Register */
+#define CAN_MO127_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019FE0u)
+
+/** Alias (User Manual Name) for CAN_MO127_EDATA0.
+* To use register names with standard convension, please use CAN_MO127_EDATA0.
+*/
+#define CAN_EMO127DATA0 (CAN_MO127_EDATA0)
+
+/** \brief 1FE4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO127_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019FE4u)
+
+/** Alias (User Manual Name) for CAN_MO127_EDATA1.
+* To use register names with standard convension, please use CAN_MO127_EDATA1.
+*/
+#define CAN_EMO127DATA1 (CAN_MO127_EDATA1)
+
+/** \brief 1FE8, Message Object Interrupt Pointer Register */
+#define CAN_MO127_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019FE8u)
+
+/** Alias (User Manual Name) for CAN_MO127_EDATA2.
+* To use register names with standard convension, please use CAN_MO127_EDATA2.
+*/
+#define CAN_EMO127DATA2 (CAN_MO127_EDATA2)
+
+/** \brief 1FEC, Message Object Acceptance Mask Register */
+#define CAN_MO127_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019FECu)
+
+/** Alias (User Manual Name) for CAN_MO127_EDATA3.
+* To use register names with standard convension, please use CAN_MO127_EDATA3.
+*/
+#define CAN_EMO127DATA3 (CAN_MO127_EDATA3)
+
+/** \brief 1FF0, Message Object Data Register Low */
+#define CAN_MO127_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019FF0u)
+
+/** Alias (User Manual Name) for CAN_MO127_EDATA4.
+* To use register names with standard convension, please use CAN_MO127_EDATA4.
+*/
+#define CAN_EMO127DATA4 (CAN_MO127_EDATA4)
+
+/** \brief 1FF4, Message Object Data Register High */
+#define CAN_MO127_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019FF4u)
+
+/** Alias (User Manual Name) for CAN_MO127_EDATA5.
+* To use register names with standard convension, please use CAN_MO127_EDATA5.
+*/
+#define CAN_EMO127DATA5 (CAN_MO127_EDATA5)
+
+/** \brief 1FF8, Message Object Arbitration Register */
+#define CAN_MO127_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019FF8u)
+
+/** Alias (User Manual Name) for CAN_MO127_EDATA6.
+* To use register names with standard convension, please use CAN_MO127_EDATA6.
+*/
+#define CAN_EMO127DATA6 (CAN_MO127_EDATA6)
+
+/** \brief 1FE0, Message Object Function Control Register */
+#define CAN_MO127_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019FE0u)
+
+/** Alias (User Manual Name) for CAN_MO127_FCR.
+* To use register names with standard convension, please use CAN_MO127_FCR.
+*/
+#define CAN_MOFCR127 (CAN_MO127_FCR)
+
+/** \brief 1FE4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO127_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019FE4u)
+
+/** Alias (User Manual Name) for CAN_MO127_FGPR.
+* To use register names with standard convension, please use CAN_MO127_FGPR.
+*/
+#define CAN_MOFGPR127 (CAN_MO127_FGPR)
+
+/** \brief 1FE8, Message Object Interrupt Pointer Register */
+#define CAN_MO127_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019FE8u)
+
+/** Alias (User Manual Name) for CAN_MO127_IPR.
+* To use register names with standard convension, please use CAN_MO127_IPR.
+*/
+#define CAN_MOIPR127 (CAN_MO127_IPR)
+
+/** \brief 1FFC, Message Object Control Register */
+#define CAN_MO127_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019FFCu)
+
+/** Alias (User Manual Name) for CAN_MO127_STAT.
+* To use register names with standard convension, please use CAN_MO127_STAT.
+*/
+#define CAN_MOSTAT127 (CAN_MO127_STAT)
+
+/** \brief 200C, Message Object Acceptance Mask Register */
+#define CAN_MO128_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A00Cu)
+
+/** Alias (User Manual Name) for CAN_MO128_AMR.
+* To use register names with standard convension, please use CAN_MO128_AMR.
+*/
+#define CAN_MOAMR128 (CAN_MO128_AMR)
+
+/** \brief 2018, Message Object Arbitration Register */
+#define CAN_MO128_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A018u)
+
+/** Alias (User Manual Name) for CAN_MO128_AR.
+* To use register names with standard convension, please use CAN_MO128_AR.
+*/
+#define CAN_MOAR128 (CAN_MO128_AR)
+
+/** \brief 201C, Message Object Control Register */
+#define CAN_MO128_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A01Cu)
+
+/** Alias (User Manual Name) for CAN_MO128_CTR.
+* To use register names with standard convension, please use CAN_MO128_CTR.
+*/
+#define CAN_MOCTR128 (CAN_MO128_CTR)
+
+/** \brief 2014, Message Object Data Register High */
+#define CAN_MO128_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A014u)
+
+/** Alias (User Manual Name) for CAN_MO128_DATAH.
+* To use register names with standard convension, please use CAN_MO128_DATAH.
+*/
+#define CAN_MODATAH128 (CAN_MO128_DATAH)
+
+/** \brief 2010, Message Object Data Register Low */
+#define CAN_MO128_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A010u)
+
+/** Alias (User Manual Name) for CAN_MO128_DATAL.
+* To use register names with standard convension, please use CAN_MO128_DATAL.
+*/
+#define CAN_MODATAL128 (CAN_MO128_DATAL)
+
+/** \brief 2000, Message Object Function Control Register */
+#define CAN_MO128_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A000u)
+
+/** Alias (User Manual Name) for CAN_MO128_EDATA0.
+* To use register names with standard convension, please use CAN_MO128_EDATA0.
+*/
+#define CAN_EMO128DATA0 (CAN_MO128_EDATA0)
+
+/** \brief 2004, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO128_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A004u)
+
+/** Alias (User Manual Name) for CAN_MO128_EDATA1.
+* To use register names with standard convension, please use CAN_MO128_EDATA1.
+*/
+#define CAN_EMO128DATA1 (CAN_MO128_EDATA1)
+
+/** \brief 2008, Message Object Interrupt Pointer Register */
+#define CAN_MO128_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A008u)
+
+/** Alias (User Manual Name) for CAN_MO128_EDATA2.
+* To use register names with standard convension, please use CAN_MO128_EDATA2.
+*/
+#define CAN_EMO128DATA2 (CAN_MO128_EDATA2)
+
+/** \brief 200C, Message Object Acceptance Mask Register */
+#define CAN_MO128_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A00Cu)
+
+/** Alias (User Manual Name) for CAN_MO128_EDATA3.
+* To use register names with standard convension, please use CAN_MO128_EDATA3.
+*/
+#define CAN_EMO128DATA3 (CAN_MO128_EDATA3)
+
+/** \brief 2010, Message Object Data Register Low */
+#define CAN_MO128_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A010u)
+
+/** Alias (User Manual Name) for CAN_MO128_EDATA4.
+* To use register names with standard convension, please use CAN_MO128_EDATA4.
+*/
+#define CAN_EMO128DATA4 (CAN_MO128_EDATA4)
+
+/** \brief 2014, Message Object Data Register High */
+#define CAN_MO128_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A014u)
+
+/** Alias (User Manual Name) for CAN_MO128_EDATA5.
+* To use register names with standard convension, please use CAN_MO128_EDATA5.
+*/
+#define CAN_EMO128DATA5 (CAN_MO128_EDATA5)
+
+/** \brief 2018, Message Object Arbitration Register */
+#define CAN_MO128_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A018u)
+
+/** Alias (User Manual Name) for CAN_MO128_EDATA6.
+* To use register names with standard convension, please use CAN_MO128_EDATA6.
+*/
+#define CAN_EMO128DATA6 (CAN_MO128_EDATA6)
+
+/** \brief 2000, Message Object Function Control Register */
+#define CAN_MO128_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A000u)
+
+/** Alias (User Manual Name) for CAN_MO128_FCR.
+* To use register names with standard convension, please use CAN_MO128_FCR.
+*/
+#define CAN_MOFCR128 (CAN_MO128_FCR)
+
+/** \brief 2004, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO128_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A004u)
+
+/** Alias (User Manual Name) for CAN_MO128_FGPR.
+* To use register names with standard convension, please use CAN_MO128_FGPR.
+*/
+#define CAN_MOFGPR128 (CAN_MO128_FGPR)
+
+/** \brief 2008, Message Object Interrupt Pointer Register */
+#define CAN_MO128_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A008u)
+
+/** Alias (User Manual Name) for CAN_MO128_IPR.
+* To use register names with standard convension, please use CAN_MO128_IPR.
+*/
+#define CAN_MOIPR128 (CAN_MO128_IPR)
+
+/** \brief 201C, Message Object Control Register */
+#define CAN_MO128_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A01Cu)
+
+/** Alias (User Manual Name) for CAN_MO128_STAT.
+* To use register names with standard convension, please use CAN_MO128_STAT.
+*/
+#define CAN_MOSTAT128 (CAN_MO128_STAT)
+
+/** \brief 202C, Message Object Acceptance Mask Register */
+#define CAN_MO129_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A02Cu)
+
+/** Alias (User Manual Name) for CAN_MO129_AMR.
+* To use register names with standard convension, please use CAN_MO129_AMR.
+*/
+#define CAN_MOAMR129 (CAN_MO129_AMR)
+
+/** \brief 2038, Message Object Arbitration Register */
+#define CAN_MO129_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A038u)
+
+/** Alias (User Manual Name) for CAN_MO129_AR.
+* To use register names with standard convension, please use CAN_MO129_AR.
+*/
+#define CAN_MOAR129 (CAN_MO129_AR)
+
+/** \brief 203C, Message Object Control Register */
+#define CAN_MO129_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A03Cu)
+
+/** Alias (User Manual Name) for CAN_MO129_CTR.
+* To use register names with standard convension, please use CAN_MO129_CTR.
+*/
+#define CAN_MOCTR129 (CAN_MO129_CTR)
+
+/** \brief 2034, Message Object Data Register High */
+#define CAN_MO129_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A034u)
+
+/** Alias (User Manual Name) for CAN_MO129_DATAH.
+* To use register names with standard convension, please use CAN_MO129_DATAH.
+*/
+#define CAN_MODATAH129 (CAN_MO129_DATAH)
+
+/** \brief 2030, Message Object Data Register Low */
+#define CAN_MO129_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A030u)
+
+/** Alias (User Manual Name) for CAN_MO129_DATAL.
+* To use register names with standard convension, please use CAN_MO129_DATAL.
+*/
+#define CAN_MODATAL129 (CAN_MO129_DATAL)
+
+/** \brief 2020, Message Object Function Control Register */
+#define CAN_MO129_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A020u)
+
+/** Alias (User Manual Name) for CAN_MO129_EDATA0.
+* To use register names with standard convension, please use CAN_MO129_EDATA0.
+*/
+#define CAN_EMO129DATA0 (CAN_MO129_EDATA0)
+
+/** \brief 2024, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO129_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A024u)
+
+/** Alias (User Manual Name) for CAN_MO129_EDATA1.
+* To use register names with standard convension, please use CAN_MO129_EDATA1.
+*/
+#define CAN_EMO129DATA1 (CAN_MO129_EDATA1)
+
+/** \brief 2028, Message Object Interrupt Pointer Register */
+#define CAN_MO129_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A028u)
+
+/** Alias (User Manual Name) for CAN_MO129_EDATA2.
+* To use register names with standard convension, please use CAN_MO129_EDATA2.
+*/
+#define CAN_EMO129DATA2 (CAN_MO129_EDATA2)
+
+/** \brief 202C, Message Object Acceptance Mask Register */
+#define CAN_MO129_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A02Cu)
+
+/** Alias (User Manual Name) for CAN_MO129_EDATA3.
+* To use register names with standard convension, please use CAN_MO129_EDATA3.
+*/
+#define CAN_EMO129DATA3 (CAN_MO129_EDATA3)
+
+/** \brief 2030, Message Object Data Register Low */
+#define CAN_MO129_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A030u)
+
+/** Alias (User Manual Name) for CAN_MO129_EDATA4.
+* To use register names with standard convension, please use CAN_MO129_EDATA4.
+*/
+#define CAN_EMO129DATA4 (CAN_MO129_EDATA4)
+
+/** \brief 2034, Message Object Data Register High */
+#define CAN_MO129_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A034u)
+
+/** Alias (User Manual Name) for CAN_MO129_EDATA5.
+* To use register names with standard convension, please use CAN_MO129_EDATA5.
+*/
+#define CAN_EMO129DATA5 (CAN_MO129_EDATA5)
+
+/** \brief 2038, Message Object Arbitration Register */
+#define CAN_MO129_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A038u)
+
+/** Alias (User Manual Name) for CAN_MO129_EDATA6.
+* To use register names with standard convension, please use CAN_MO129_EDATA6.
+*/
+#define CAN_EMO129DATA6 (CAN_MO129_EDATA6)
+
+/** \brief 2020, Message Object Function Control Register */
+#define CAN_MO129_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A020u)
+
+/** Alias (User Manual Name) for CAN_MO129_FCR.
+* To use register names with standard convension, please use CAN_MO129_FCR.
+*/
+#define CAN_MOFCR129 (CAN_MO129_FCR)
+
+/** \brief 2024, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO129_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A024u)
+
+/** Alias (User Manual Name) for CAN_MO129_FGPR.
+* To use register names with standard convension, please use CAN_MO129_FGPR.
+*/
+#define CAN_MOFGPR129 (CAN_MO129_FGPR)
+
+/** \brief 2028, Message Object Interrupt Pointer Register */
+#define CAN_MO129_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A028u)
+
+/** Alias (User Manual Name) for CAN_MO129_IPR.
+* To use register names with standard convension, please use CAN_MO129_IPR.
+*/
+#define CAN_MOIPR129 (CAN_MO129_IPR)
+
+/** \brief 203C, Message Object Control Register */
+#define CAN_MO129_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A03Cu)
+
+/** Alias (User Manual Name) for CAN_MO129_STAT.
+* To use register names with standard convension, please use CAN_MO129_STAT.
+*/
+#define CAN_MOSTAT129 (CAN_MO129_STAT)
+
+/** \brief 118C, Message Object Acceptance Mask Register */
+#define CAN_MO12_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001918Cu)
+
+/** Alias (User Manual Name) for CAN_MO12_AMR.
+* To use register names with standard convension, please use CAN_MO12_AMR.
+*/
+#define CAN_MOAMR12 (CAN_MO12_AMR)
+
+/** \brief 1198, Message Object Arbitration Register */
+#define CAN_MO12_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019198u)
+
+/** Alias (User Manual Name) for CAN_MO12_AR.
+* To use register names with standard convension, please use CAN_MO12_AR.
+*/
+#define CAN_MOAR12 (CAN_MO12_AR)
+
+/** \brief 119C, Message Object Control Register */
+#define CAN_MO12_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001919Cu)
+
+/** Alias (User Manual Name) for CAN_MO12_CTR.
+* To use register names with standard convension, please use CAN_MO12_CTR.
+*/
+#define CAN_MOCTR12 (CAN_MO12_CTR)
+
+/** \brief 1194, Message Object Data Register High */
+#define CAN_MO12_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019194u)
+
+/** Alias (User Manual Name) for CAN_MO12_DATAH.
+* To use register names with standard convension, please use CAN_MO12_DATAH.
+*/
+#define CAN_MODATAH12 (CAN_MO12_DATAH)
+
+/** \brief 1190, Message Object Data Register Low */
+#define CAN_MO12_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019190u)
+
+/** Alias (User Manual Name) for CAN_MO12_DATAL.
+* To use register names with standard convension, please use CAN_MO12_DATAL.
+*/
+#define CAN_MODATAL12 (CAN_MO12_DATAL)
+
+/** \brief 1180, Message Object Function Control Register */
+#define CAN_MO12_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019180u)
+
+/** Alias (User Manual Name) for CAN_MO12_EDATA0.
+* To use register names with standard convension, please use CAN_MO12_EDATA0.
+*/
+#define CAN_EMO12DATA0 (CAN_MO12_EDATA0)
+
+/** \brief 1184, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO12_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019184u)
+
+/** Alias (User Manual Name) for CAN_MO12_EDATA1.
+* To use register names with standard convension, please use CAN_MO12_EDATA1.
+*/
+#define CAN_EMO12DATA1 (CAN_MO12_EDATA1)
+
+/** \brief 1188, Message Object Interrupt Pointer Register */
+#define CAN_MO12_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019188u)
+
+/** Alias (User Manual Name) for CAN_MO12_EDATA2.
+* To use register names with standard convension, please use CAN_MO12_EDATA2.
+*/
+#define CAN_EMO12DATA2 (CAN_MO12_EDATA2)
+
+/** \brief 118C, Message Object Acceptance Mask Register */
+#define CAN_MO12_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001918Cu)
+
+/** Alias (User Manual Name) for CAN_MO12_EDATA3.
+* To use register names with standard convension, please use CAN_MO12_EDATA3.
+*/
+#define CAN_EMO12DATA3 (CAN_MO12_EDATA3)
+
+/** \brief 1190, Message Object Data Register Low */
+#define CAN_MO12_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019190u)
+
+/** Alias (User Manual Name) for CAN_MO12_EDATA4.
+* To use register names with standard convension, please use CAN_MO12_EDATA4.
+*/
+#define CAN_EMO12DATA4 (CAN_MO12_EDATA4)
+
+/** \brief 1194, Message Object Data Register High */
+#define CAN_MO12_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019194u)
+
+/** Alias (User Manual Name) for CAN_MO12_EDATA5.
+* To use register names with standard convension, please use CAN_MO12_EDATA5.
+*/
+#define CAN_EMO12DATA5 (CAN_MO12_EDATA5)
+
+/** \brief 1198, Message Object Arbitration Register */
+#define CAN_MO12_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019198u)
+
+/** Alias (User Manual Name) for CAN_MO12_EDATA6.
+* To use register names with standard convension, please use CAN_MO12_EDATA6.
+*/
+#define CAN_EMO12DATA6 (CAN_MO12_EDATA6)
+
+/** \brief 1180, Message Object Function Control Register */
+#define CAN_MO12_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019180u)
+
+/** Alias (User Manual Name) for CAN_MO12_FCR.
+* To use register names with standard convension, please use CAN_MO12_FCR.
+*/
+#define CAN_MOFCR12 (CAN_MO12_FCR)
+
+/** \brief 1184, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO12_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019184u)
+
+/** Alias (User Manual Name) for CAN_MO12_FGPR.
+* To use register names with standard convension, please use CAN_MO12_FGPR.
+*/
+#define CAN_MOFGPR12 (CAN_MO12_FGPR)
+
+/** \brief 1188, Message Object Interrupt Pointer Register */
+#define CAN_MO12_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019188u)
+
+/** Alias (User Manual Name) for CAN_MO12_IPR.
+* To use register names with standard convension, please use CAN_MO12_IPR.
+*/
+#define CAN_MOIPR12 (CAN_MO12_IPR)
+
+/** \brief 119C, Message Object Control Register */
+#define CAN_MO12_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001919Cu)
+
+/** Alias (User Manual Name) for CAN_MO12_STAT.
+* To use register names with standard convension, please use CAN_MO12_STAT.
+*/
+#define CAN_MOSTAT12 (CAN_MO12_STAT)
+
+/** \brief 204C, Message Object Acceptance Mask Register */
+#define CAN_MO130_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A04Cu)
+
+/** Alias (User Manual Name) for CAN_MO130_AMR.
+* To use register names with standard convension, please use CAN_MO130_AMR.
+*/
+#define CAN_MOAMR130 (CAN_MO130_AMR)
+
+/** \brief 2058, Message Object Arbitration Register */
+#define CAN_MO130_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A058u)
+
+/** Alias (User Manual Name) for CAN_MO130_AR.
+* To use register names with standard convension, please use CAN_MO130_AR.
+*/
+#define CAN_MOAR130 (CAN_MO130_AR)
+
+/** \brief 205C, Message Object Control Register */
+#define CAN_MO130_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A05Cu)
+
+/** Alias (User Manual Name) for CAN_MO130_CTR.
+* To use register names with standard convension, please use CAN_MO130_CTR.
+*/
+#define CAN_MOCTR130 (CAN_MO130_CTR)
+
+/** \brief 2054, Message Object Data Register High */
+#define CAN_MO130_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A054u)
+
+/** Alias (User Manual Name) for CAN_MO130_DATAH.
+* To use register names with standard convension, please use CAN_MO130_DATAH.
+*/
+#define CAN_MODATAH130 (CAN_MO130_DATAH)
+
+/** \brief 2050, Message Object Data Register Low */
+#define CAN_MO130_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A050u)
+
+/** Alias (User Manual Name) for CAN_MO130_DATAL.
+* To use register names with standard convension, please use CAN_MO130_DATAL.
+*/
+#define CAN_MODATAL130 (CAN_MO130_DATAL)
+
+/** \brief 2040, Message Object Function Control Register */
+#define CAN_MO130_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A040u)
+
+/** Alias (User Manual Name) for CAN_MO130_EDATA0.
+* To use register names with standard convension, please use CAN_MO130_EDATA0.
+*/
+#define CAN_EMO130DATA0 (CAN_MO130_EDATA0)
+
+/** \brief 2044, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO130_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A044u)
+
+/** Alias (User Manual Name) for CAN_MO130_EDATA1.
+* To use register names with standard convension, please use CAN_MO130_EDATA1.
+*/
+#define CAN_EMO130DATA1 (CAN_MO130_EDATA1)
+
+/** \brief 2048, Message Object Interrupt Pointer Register */
+#define CAN_MO130_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A048u)
+
+/** Alias (User Manual Name) for CAN_MO130_EDATA2.
+* To use register names with standard convension, please use CAN_MO130_EDATA2.
+*/
+#define CAN_EMO130DATA2 (CAN_MO130_EDATA2)
+
+/** \brief 204C, Message Object Acceptance Mask Register */
+#define CAN_MO130_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A04Cu)
+
+/** Alias (User Manual Name) for CAN_MO130_EDATA3.
+* To use register names with standard convension, please use CAN_MO130_EDATA3.
+*/
+#define CAN_EMO130DATA3 (CAN_MO130_EDATA3)
+
+/** \brief 2050, Message Object Data Register Low */
+#define CAN_MO130_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A050u)
+
+/** Alias (User Manual Name) for CAN_MO130_EDATA4.
+* To use register names with standard convension, please use CAN_MO130_EDATA4.
+*/
+#define CAN_EMO130DATA4 (CAN_MO130_EDATA4)
+
+/** \brief 2054, Message Object Data Register High */
+#define CAN_MO130_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A054u)
+
+/** Alias (User Manual Name) for CAN_MO130_EDATA5.
+* To use register names with standard convension, please use CAN_MO130_EDATA5.
+*/
+#define CAN_EMO130DATA5 (CAN_MO130_EDATA5)
+
+/** \brief 2058, Message Object Arbitration Register */
+#define CAN_MO130_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A058u)
+
+/** Alias (User Manual Name) for CAN_MO130_EDATA6.
+* To use register names with standard convension, please use CAN_MO130_EDATA6.
+*/
+#define CAN_EMO130DATA6 (CAN_MO130_EDATA6)
+
+/** \brief 2040, Message Object Function Control Register */
+#define CAN_MO130_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A040u)
+
+/** Alias (User Manual Name) for CAN_MO130_FCR.
+* To use register names with standard convension, please use CAN_MO130_FCR.
+*/
+#define CAN_MOFCR130 (CAN_MO130_FCR)
+
+/** \brief 2044, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO130_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A044u)
+
+/** Alias (User Manual Name) for CAN_MO130_FGPR.
+* To use register names with standard convension, please use CAN_MO130_FGPR.
+*/
+#define CAN_MOFGPR130 (CAN_MO130_FGPR)
+
+/** \brief 2048, Message Object Interrupt Pointer Register */
+#define CAN_MO130_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A048u)
+
+/** Alias (User Manual Name) for CAN_MO130_IPR.
+* To use register names with standard convension, please use CAN_MO130_IPR.
+*/
+#define CAN_MOIPR130 (CAN_MO130_IPR)
+
+/** \brief 205C, Message Object Control Register */
+#define CAN_MO130_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A05Cu)
+
+/** Alias (User Manual Name) for CAN_MO130_STAT.
+* To use register names with standard convension, please use CAN_MO130_STAT.
+*/
+#define CAN_MOSTAT130 (CAN_MO130_STAT)
+
+/** \brief 206C, Message Object Acceptance Mask Register */
+#define CAN_MO131_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A06Cu)
+
+/** Alias (User Manual Name) for CAN_MO131_AMR.
+* To use register names with standard convension, please use CAN_MO131_AMR.
+*/
+#define CAN_MOAMR131 (CAN_MO131_AMR)
+
+/** \brief 2078, Message Object Arbitration Register */
+#define CAN_MO131_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A078u)
+
+/** Alias (User Manual Name) for CAN_MO131_AR.
+* To use register names with standard convension, please use CAN_MO131_AR.
+*/
+#define CAN_MOAR131 (CAN_MO131_AR)
+
+/** \brief 207C, Message Object Control Register */
+#define CAN_MO131_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A07Cu)
+
+/** Alias (User Manual Name) for CAN_MO131_CTR.
+* To use register names with standard convension, please use CAN_MO131_CTR.
+*/
+#define CAN_MOCTR131 (CAN_MO131_CTR)
+
+/** \brief 2074, Message Object Data Register High */
+#define CAN_MO131_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A074u)
+
+/** Alias (User Manual Name) for CAN_MO131_DATAH.
+* To use register names with standard convension, please use CAN_MO131_DATAH.
+*/
+#define CAN_MODATAH131 (CAN_MO131_DATAH)
+
+/** \brief 2070, Message Object Data Register Low */
+#define CAN_MO131_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A070u)
+
+/** Alias (User Manual Name) for CAN_MO131_DATAL.
+* To use register names with standard convension, please use CAN_MO131_DATAL.
+*/
+#define CAN_MODATAL131 (CAN_MO131_DATAL)
+
+/** \brief 2060, Message Object Function Control Register */
+#define CAN_MO131_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A060u)
+
+/** Alias (User Manual Name) for CAN_MO131_EDATA0.
+* To use register names with standard convension, please use CAN_MO131_EDATA0.
+*/
+#define CAN_EMO131DATA0 (CAN_MO131_EDATA0)
+
+/** \brief 2064, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO131_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A064u)
+
+/** Alias (User Manual Name) for CAN_MO131_EDATA1.
+* To use register names with standard convension, please use CAN_MO131_EDATA1.
+*/
+#define CAN_EMO131DATA1 (CAN_MO131_EDATA1)
+
+/** \brief 2068, Message Object Interrupt Pointer Register */
+#define CAN_MO131_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A068u)
+
+/** Alias (User Manual Name) for CAN_MO131_EDATA2.
+* To use register names with standard convension, please use CAN_MO131_EDATA2.
+*/
+#define CAN_EMO131DATA2 (CAN_MO131_EDATA2)
+
+/** \brief 206C, Message Object Acceptance Mask Register */
+#define CAN_MO131_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A06Cu)
+
+/** Alias (User Manual Name) for CAN_MO131_EDATA3.
+* To use register names with standard convension, please use CAN_MO131_EDATA3.
+*/
+#define CAN_EMO131DATA3 (CAN_MO131_EDATA3)
+
+/** \brief 2070, Message Object Data Register Low */
+#define CAN_MO131_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A070u)
+
+/** Alias (User Manual Name) for CAN_MO131_EDATA4.
+* To use register names with standard convension, please use CAN_MO131_EDATA4.
+*/
+#define CAN_EMO131DATA4 (CAN_MO131_EDATA4)
+
+/** \brief 2074, Message Object Data Register High */
+#define CAN_MO131_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A074u)
+
+/** Alias (User Manual Name) for CAN_MO131_EDATA5.
+* To use register names with standard convension, please use CAN_MO131_EDATA5.
+*/
+#define CAN_EMO131DATA5 (CAN_MO131_EDATA5)
+
+/** \brief 2078, Message Object Arbitration Register */
+#define CAN_MO131_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A078u)
+
+/** Alias (User Manual Name) for CAN_MO131_EDATA6.
+* To use register names with standard convension, please use CAN_MO131_EDATA6.
+*/
+#define CAN_EMO131DATA6 (CAN_MO131_EDATA6)
+
+/** \brief 2060, Message Object Function Control Register */
+#define CAN_MO131_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A060u)
+
+/** Alias (User Manual Name) for CAN_MO131_FCR.
+* To use register names with standard convension, please use CAN_MO131_FCR.
+*/
+#define CAN_MOFCR131 (CAN_MO131_FCR)
+
+/** \brief 2064, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO131_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A064u)
+
+/** Alias (User Manual Name) for CAN_MO131_FGPR.
+* To use register names with standard convension, please use CAN_MO131_FGPR.
+*/
+#define CAN_MOFGPR131 (CAN_MO131_FGPR)
+
+/** \brief 2068, Message Object Interrupt Pointer Register */
+#define CAN_MO131_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A068u)
+
+/** Alias (User Manual Name) for CAN_MO131_IPR.
+* To use register names with standard convension, please use CAN_MO131_IPR.
+*/
+#define CAN_MOIPR131 (CAN_MO131_IPR)
+
+/** \brief 207C, Message Object Control Register */
+#define CAN_MO131_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A07Cu)
+
+/** Alias (User Manual Name) for CAN_MO131_STAT.
+* To use register names with standard convension, please use CAN_MO131_STAT.
+*/
+#define CAN_MOSTAT131 (CAN_MO131_STAT)
+
+/** \brief 208C, Message Object Acceptance Mask Register */
+#define CAN_MO132_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A08Cu)
+
+/** Alias (User Manual Name) for CAN_MO132_AMR.
+* To use register names with standard convension, please use CAN_MO132_AMR.
+*/
+#define CAN_MOAMR132 (CAN_MO132_AMR)
+
+/** \brief 2098, Message Object Arbitration Register */
+#define CAN_MO132_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A098u)
+
+/** Alias (User Manual Name) for CAN_MO132_AR.
+* To use register names with standard convension, please use CAN_MO132_AR.
+*/
+#define CAN_MOAR132 (CAN_MO132_AR)
+
+/** \brief 209C, Message Object Control Register */
+#define CAN_MO132_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A09Cu)
+
+/** Alias (User Manual Name) for CAN_MO132_CTR.
+* To use register names with standard convension, please use CAN_MO132_CTR.
+*/
+#define CAN_MOCTR132 (CAN_MO132_CTR)
+
+/** \brief 2094, Message Object Data Register High */
+#define CAN_MO132_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A094u)
+
+/** Alias (User Manual Name) for CAN_MO132_DATAH.
+* To use register names with standard convension, please use CAN_MO132_DATAH.
+*/
+#define CAN_MODATAH132 (CAN_MO132_DATAH)
+
+/** \brief 2090, Message Object Data Register Low */
+#define CAN_MO132_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A090u)
+
+/** Alias (User Manual Name) for CAN_MO132_DATAL.
+* To use register names with standard convension, please use CAN_MO132_DATAL.
+*/
+#define CAN_MODATAL132 (CAN_MO132_DATAL)
+
+/** \brief 2080, Message Object Function Control Register */
+#define CAN_MO132_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A080u)
+
+/** Alias (User Manual Name) for CAN_MO132_EDATA0.
+* To use register names with standard convension, please use CAN_MO132_EDATA0.
+*/
+#define CAN_EMO132DATA0 (CAN_MO132_EDATA0)
+
+/** \brief 2084, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO132_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A084u)
+
+/** Alias (User Manual Name) for CAN_MO132_EDATA1.
+* To use register names with standard convension, please use CAN_MO132_EDATA1.
+*/
+#define CAN_EMO132DATA1 (CAN_MO132_EDATA1)
+
+/** \brief 2088, Message Object Interrupt Pointer Register */
+#define CAN_MO132_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A088u)
+
+/** Alias (User Manual Name) for CAN_MO132_EDATA2.
+* To use register names with standard convension, please use CAN_MO132_EDATA2.
+*/
+#define CAN_EMO132DATA2 (CAN_MO132_EDATA2)
+
+/** \brief 208C, Message Object Acceptance Mask Register */
+#define CAN_MO132_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A08Cu)
+
+/** Alias (User Manual Name) for CAN_MO132_EDATA3.
+* To use register names with standard convension, please use CAN_MO132_EDATA3.
+*/
+#define CAN_EMO132DATA3 (CAN_MO132_EDATA3)
+
+/** \brief 2090, Message Object Data Register Low */
+#define CAN_MO132_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A090u)
+
+/** Alias (User Manual Name) for CAN_MO132_EDATA4.
+* To use register names with standard convension, please use CAN_MO132_EDATA4.
+*/
+#define CAN_EMO132DATA4 (CAN_MO132_EDATA4)
+
+/** \brief 2094, Message Object Data Register High */
+#define CAN_MO132_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A094u)
+
+/** Alias (User Manual Name) for CAN_MO132_EDATA5.
+* To use register names with standard convension, please use CAN_MO132_EDATA5.
+*/
+#define CAN_EMO132DATA5 (CAN_MO132_EDATA5)
+
+/** \brief 2098, Message Object Arbitration Register */
+#define CAN_MO132_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A098u)
+
+/** Alias (User Manual Name) for CAN_MO132_EDATA6.
+* To use register names with standard convension, please use CAN_MO132_EDATA6.
+*/
+#define CAN_EMO132DATA6 (CAN_MO132_EDATA6)
+
+/** \brief 2080, Message Object Function Control Register */
+#define CAN_MO132_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A080u)
+
+/** Alias (User Manual Name) for CAN_MO132_FCR.
+* To use register names with standard convension, please use CAN_MO132_FCR.
+*/
+#define CAN_MOFCR132 (CAN_MO132_FCR)
+
+/** \brief 2084, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO132_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A084u)
+
+/** Alias (User Manual Name) for CAN_MO132_FGPR.
+* To use register names with standard convension, please use CAN_MO132_FGPR.
+*/
+#define CAN_MOFGPR132 (CAN_MO132_FGPR)
+
+/** \brief 2088, Message Object Interrupt Pointer Register */
+#define CAN_MO132_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A088u)
+
+/** Alias (User Manual Name) for CAN_MO132_IPR.
+* To use register names with standard convension, please use CAN_MO132_IPR.
+*/
+#define CAN_MOIPR132 (CAN_MO132_IPR)
+
+/** \brief 209C, Message Object Control Register */
+#define CAN_MO132_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A09Cu)
+
+/** Alias (User Manual Name) for CAN_MO132_STAT.
+* To use register names with standard convension, please use CAN_MO132_STAT.
+*/
+#define CAN_MOSTAT132 (CAN_MO132_STAT)
+
+/** \brief 20AC, Message Object Acceptance Mask Register */
+#define CAN_MO133_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A0ACu)
+
+/** Alias (User Manual Name) for CAN_MO133_AMR.
+* To use register names with standard convension, please use CAN_MO133_AMR.
+*/
+#define CAN_MOAMR133 (CAN_MO133_AMR)
+
+/** \brief 20B8, Message Object Arbitration Register */
+#define CAN_MO133_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A0B8u)
+
+/** Alias (User Manual Name) for CAN_MO133_AR.
+* To use register names with standard convension, please use CAN_MO133_AR.
+*/
+#define CAN_MOAR133 (CAN_MO133_AR)
+
+/** \brief 20BC, Message Object Control Register */
+#define CAN_MO133_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A0BCu)
+
+/** Alias (User Manual Name) for CAN_MO133_CTR.
+* To use register names with standard convension, please use CAN_MO133_CTR.
+*/
+#define CAN_MOCTR133 (CAN_MO133_CTR)
+
+/** \brief 20B4, Message Object Data Register High */
+#define CAN_MO133_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A0B4u)
+
+/** Alias (User Manual Name) for CAN_MO133_DATAH.
+* To use register names with standard convension, please use CAN_MO133_DATAH.
+*/
+#define CAN_MODATAH133 (CAN_MO133_DATAH)
+
+/** \brief 20B0, Message Object Data Register Low */
+#define CAN_MO133_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A0B0u)
+
+/** Alias (User Manual Name) for CAN_MO133_DATAL.
+* To use register names with standard convension, please use CAN_MO133_DATAL.
+*/
+#define CAN_MODATAL133 (CAN_MO133_DATAL)
+
+/** \brief 20A0, Message Object Function Control Register */
+#define CAN_MO133_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A0A0u)
+
+/** Alias (User Manual Name) for CAN_MO133_EDATA0.
+* To use register names with standard convension, please use CAN_MO133_EDATA0.
+*/
+#define CAN_EMO133DATA0 (CAN_MO133_EDATA0)
+
+/** \brief 20A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO133_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A0A4u)
+
+/** Alias (User Manual Name) for CAN_MO133_EDATA1.
+* To use register names with standard convension, please use CAN_MO133_EDATA1.
+*/
+#define CAN_EMO133DATA1 (CAN_MO133_EDATA1)
+
+/** \brief 20A8, Message Object Interrupt Pointer Register */
+#define CAN_MO133_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A0A8u)
+
+/** Alias (User Manual Name) for CAN_MO133_EDATA2.
+* To use register names with standard convension, please use CAN_MO133_EDATA2.
+*/
+#define CAN_EMO133DATA2 (CAN_MO133_EDATA2)
+
+/** \brief 20AC, Message Object Acceptance Mask Register */
+#define CAN_MO133_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A0ACu)
+
+/** Alias (User Manual Name) for CAN_MO133_EDATA3.
+* To use register names with standard convension, please use CAN_MO133_EDATA3.
+*/
+#define CAN_EMO133DATA3 (CAN_MO133_EDATA3)
+
+/** \brief 20B0, Message Object Data Register Low */
+#define CAN_MO133_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A0B0u)
+
+/** Alias (User Manual Name) for CAN_MO133_EDATA4.
+* To use register names with standard convension, please use CAN_MO133_EDATA4.
+*/
+#define CAN_EMO133DATA4 (CAN_MO133_EDATA4)
+
+/** \brief 20B4, Message Object Data Register High */
+#define CAN_MO133_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A0B4u)
+
+/** Alias (User Manual Name) for CAN_MO133_EDATA5.
+* To use register names with standard convension, please use CAN_MO133_EDATA5.
+*/
+#define CAN_EMO133DATA5 (CAN_MO133_EDATA5)
+
+/** \brief 20B8, Message Object Arbitration Register */
+#define CAN_MO133_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A0B8u)
+
+/** Alias (User Manual Name) for CAN_MO133_EDATA6.
+* To use register names with standard convension, please use CAN_MO133_EDATA6.
+*/
+#define CAN_EMO133DATA6 (CAN_MO133_EDATA6)
+
+/** \brief 20A0, Message Object Function Control Register */
+#define CAN_MO133_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A0A0u)
+
+/** Alias (User Manual Name) for CAN_MO133_FCR.
+* To use register names with standard convension, please use CAN_MO133_FCR.
+*/
+#define CAN_MOFCR133 (CAN_MO133_FCR)
+
+/** \brief 20A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO133_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A0A4u)
+
+/** Alias (User Manual Name) for CAN_MO133_FGPR.
+* To use register names with standard convension, please use CAN_MO133_FGPR.
+*/
+#define CAN_MOFGPR133 (CAN_MO133_FGPR)
+
+/** \brief 20A8, Message Object Interrupt Pointer Register */
+#define CAN_MO133_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A0A8u)
+
+/** Alias (User Manual Name) for CAN_MO133_IPR.
+* To use register names with standard convension, please use CAN_MO133_IPR.
+*/
+#define CAN_MOIPR133 (CAN_MO133_IPR)
+
+/** \brief 20BC, Message Object Control Register */
+#define CAN_MO133_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A0BCu)
+
+/** Alias (User Manual Name) for CAN_MO133_STAT.
+* To use register names with standard convension, please use CAN_MO133_STAT.
+*/
+#define CAN_MOSTAT133 (CAN_MO133_STAT)
+
+/** \brief 20CC, Message Object Acceptance Mask Register */
+#define CAN_MO134_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A0CCu)
+
+/** Alias (User Manual Name) for CAN_MO134_AMR.
+* To use register names with standard convension, please use CAN_MO134_AMR.
+*/
+#define CAN_MOAMR134 (CAN_MO134_AMR)
+
+/** \brief 20D8, Message Object Arbitration Register */
+#define CAN_MO134_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A0D8u)
+
+/** Alias (User Manual Name) for CAN_MO134_AR.
+* To use register names with standard convension, please use CAN_MO134_AR.
+*/
+#define CAN_MOAR134 (CAN_MO134_AR)
+
+/** \brief 20DC, Message Object Control Register */
+#define CAN_MO134_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A0DCu)
+
+/** Alias (User Manual Name) for CAN_MO134_CTR.
+* To use register names with standard convension, please use CAN_MO134_CTR.
+*/
+#define CAN_MOCTR134 (CAN_MO134_CTR)
+
+/** \brief 20D4, Message Object Data Register High */
+#define CAN_MO134_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A0D4u)
+
+/** Alias (User Manual Name) for CAN_MO134_DATAH.
+* To use register names with standard convension, please use CAN_MO134_DATAH.
+*/
+#define CAN_MODATAH134 (CAN_MO134_DATAH)
+
+/** \brief 20D0, Message Object Data Register Low */
+#define CAN_MO134_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A0D0u)
+
+/** Alias (User Manual Name) for CAN_MO134_DATAL.
+* To use register names with standard convension, please use CAN_MO134_DATAL.
+*/
+#define CAN_MODATAL134 (CAN_MO134_DATAL)
+
+/** \brief 20C0, Message Object Function Control Register */
+#define CAN_MO134_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A0C0u)
+
+/** Alias (User Manual Name) for CAN_MO134_EDATA0.
+* To use register names with standard convension, please use CAN_MO134_EDATA0.
+*/
+#define CAN_EMO134DATA0 (CAN_MO134_EDATA0)
+
+/** \brief 20C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO134_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A0C4u)
+
+/** Alias (User Manual Name) for CAN_MO134_EDATA1.
+* To use register names with standard convension, please use CAN_MO134_EDATA1.
+*/
+#define CAN_EMO134DATA1 (CAN_MO134_EDATA1)
+
+/** \brief 20C8, Message Object Interrupt Pointer Register */
+#define CAN_MO134_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A0C8u)
+
+/** Alias (User Manual Name) for CAN_MO134_EDATA2.
+* To use register names with standard convension, please use CAN_MO134_EDATA2.
+*/
+#define CAN_EMO134DATA2 (CAN_MO134_EDATA2)
+
+/** \brief 20CC, Message Object Acceptance Mask Register */
+#define CAN_MO134_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A0CCu)
+
+/** Alias (User Manual Name) for CAN_MO134_EDATA3.
+* To use register names with standard convension, please use CAN_MO134_EDATA3.
+*/
+#define CAN_EMO134DATA3 (CAN_MO134_EDATA3)
+
+/** \brief 20D0, Message Object Data Register Low */
+#define CAN_MO134_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A0D0u)
+
+/** Alias (User Manual Name) for CAN_MO134_EDATA4.
+* To use register names with standard convension, please use CAN_MO134_EDATA4.
+*/
+#define CAN_EMO134DATA4 (CAN_MO134_EDATA4)
+
+/** \brief 20D4, Message Object Data Register High */
+#define CAN_MO134_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A0D4u)
+
+/** Alias (User Manual Name) for CAN_MO134_EDATA5.
+* To use register names with standard convension, please use CAN_MO134_EDATA5.
+*/
+#define CAN_EMO134DATA5 (CAN_MO134_EDATA5)
+
+/** \brief 20D8, Message Object Arbitration Register */
+#define CAN_MO134_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A0D8u)
+
+/** Alias (User Manual Name) for CAN_MO134_EDATA6.
+* To use register names with standard convension, please use CAN_MO134_EDATA6.
+*/
+#define CAN_EMO134DATA6 (CAN_MO134_EDATA6)
+
+/** \brief 20C0, Message Object Function Control Register */
+#define CAN_MO134_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A0C0u)
+
+/** Alias (User Manual Name) for CAN_MO134_FCR.
+* To use register names with standard convension, please use CAN_MO134_FCR.
+*/
+#define CAN_MOFCR134 (CAN_MO134_FCR)
+
+/** \brief 20C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO134_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A0C4u)
+
+/** Alias (User Manual Name) for CAN_MO134_FGPR.
+* To use register names with standard convension, please use CAN_MO134_FGPR.
+*/
+#define CAN_MOFGPR134 (CAN_MO134_FGPR)
+
+/** \brief 20C8, Message Object Interrupt Pointer Register */
+#define CAN_MO134_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A0C8u)
+
+/** Alias (User Manual Name) for CAN_MO134_IPR.
+* To use register names with standard convension, please use CAN_MO134_IPR.
+*/
+#define CAN_MOIPR134 (CAN_MO134_IPR)
+
+/** \brief 20DC, Message Object Control Register */
+#define CAN_MO134_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A0DCu)
+
+/** Alias (User Manual Name) for CAN_MO134_STAT.
+* To use register names with standard convension, please use CAN_MO134_STAT.
+*/
+#define CAN_MOSTAT134 (CAN_MO134_STAT)
+
+/** \brief 20EC, Message Object Acceptance Mask Register */
+#define CAN_MO135_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A0ECu)
+
+/** Alias (User Manual Name) for CAN_MO135_AMR.
+* To use register names with standard convension, please use CAN_MO135_AMR.
+*/
+#define CAN_MOAMR135 (CAN_MO135_AMR)
+
+/** \brief 20F8, Message Object Arbitration Register */
+#define CAN_MO135_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A0F8u)
+
+/** Alias (User Manual Name) for CAN_MO135_AR.
+* To use register names with standard convension, please use CAN_MO135_AR.
+*/
+#define CAN_MOAR135 (CAN_MO135_AR)
+
+/** \brief 20FC, Message Object Control Register */
+#define CAN_MO135_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A0FCu)
+
+/** Alias (User Manual Name) for CAN_MO135_CTR.
+* To use register names with standard convension, please use CAN_MO135_CTR.
+*/
+#define CAN_MOCTR135 (CAN_MO135_CTR)
+
+/** \brief 20F4, Message Object Data Register High */
+#define CAN_MO135_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A0F4u)
+
+/** Alias (User Manual Name) for CAN_MO135_DATAH.
+* To use register names with standard convension, please use CAN_MO135_DATAH.
+*/
+#define CAN_MODATAH135 (CAN_MO135_DATAH)
+
+/** \brief 20F0, Message Object Data Register Low */
+#define CAN_MO135_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A0F0u)
+
+/** Alias (User Manual Name) for CAN_MO135_DATAL.
+* To use register names with standard convension, please use CAN_MO135_DATAL.
+*/
+#define CAN_MODATAL135 (CAN_MO135_DATAL)
+
+/** \brief 20E0, Message Object Function Control Register */
+#define CAN_MO135_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A0E0u)
+
+/** Alias (User Manual Name) for CAN_MO135_EDATA0.
+* To use register names with standard convension, please use CAN_MO135_EDATA0.
+*/
+#define CAN_EMO135DATA0 (CAN_MO135_EDATA0)
+
+/** \brief 20E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO135_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A0E4u)
+
+/** Alias (User Manual Name) for CAN_MO135_EDATA1.
+* To use register names with standard convension, please use CAN_MO135_EDATA1.
+*/
+#define CAN_EMO135DATA1 (CAN_MO135_EDATA1)
+
+/** \brief 20E8, Message Object Interrupt Pointer Register */
+#define CAN_MO135_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A0E8u)
+
+/** Alias (User Manual Name) for CAN_MO135_EDATA2.
+* To use register names with standard convension, please use CAN_MO135_EDATA2.
+*/
+#define CAN_EMO135DATA2 (CAN_MO135_EDATA2)
+
+/** \brief 20EC, Message Object Acceptance Mask Register */
+#define CAN_MO135_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A0ECu)
+
+/** Alias (User Manual Name) for CAN_MO135_EDATA3.
+* To use register names with standard convension, please use CAN_MO135_EDATA3.
+*/
+#define CAN_EMO135DATA3 (CAN_MO135_EDATA3)
+
+/** \brief 20F0, Message Object Data Register Low */
+#define CAN_MO135_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A0F0u)
+
+/** Alias (User Manual Name) for CAN_MO135_EDATA4.
+* To use register names with standard convension, please use CAN_MO135_EDATA4.
+*/
+#define CAN_EMO135DATA4 (CAN_MO135_EDATA4)
+
+/** \brief 20F4, Message Object Data Register High */
+#define CAN_MO135_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A0F4u)
+
+/** Alias (User Manual Name) for CAN_MO135_EDATA5.
+* To use register names with standard convension, please use CAN_MO135_EDATA5.
+*/
+#define CAN_EMO135DATA5 (CAN_MO135_EDATA5)
+
+/** \brief 20F8, Message Object Arbitration Register */
+#define CAN_MO135_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A0F8u)
+
+/** Alias (User Manual Name) for CAN_MO135_EDATA6.
+* To use register names with standard convension, please use CAN_MO135_EDATA6.
+*/
+#define CAN_EMO135DATA6 (CAN_MO135_EDATA6)
+
+/** \brief 20E0, Message Object Function Control Register */
+#define CAN_MO135_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A0E0u)
+
+/** Alias (User Manual Name) for CAN_MO135_FCR.
+* To use register names with standard convension, please use CAN_MO135_FCR.
+*/
+#define CAN_MOFCR135 (CAN_MO135_FCR)
+
+/** \brief 20E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO135_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A0E4u)
+
+/** Alias (User Manual Name) for CAN_MO135_FGPR.
+* To use register names with standard convension, please use CAN_MO135_FGPR.
+*/
+#define CAN_MOFGPR135 (CAN_MO135_FGPR)
+
+/** \brief 20E8, Message Object Interrupt Pointer Register */
+#define CAN_MO135_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A0E8u)
+
+/** Alias (User Manual Name) for CAN_MO135_IPR.
+* To use register names with standard convension, please use CAN_MO135_IPR.
+*/
+#define CAN_MOIPR135 (CAN_MO135_IPR)
+
+/** \brief 20FC, Message Object Control Register */
+#define CAN_MO135_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A0FCu)
+
+/** Alias (User Manual Name) for CAN_MO135_STAT.
+* To use register names with standard convension, please use CAN_MO135_STAT.
+*/
+#define CAN_MOSTAT135 (CAN_MO135_STAT)
+
+/** \brief 210C, Message Object Acceptance Mask Register */
+#define CAN_MO136_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A10Cu)
+
+/** Alias (User Manual Name) for CAN_MO136_AMR.
+* To use register names with standard convension, please use CAN_MO136_AMR.
+*/
+#define CAN_MOAMR136 (CAN_MO136_AMR)
+
+/** \brief 2118, Message Object Arbitration Register */
+#define CAN_MO136_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A118u)
+
+/** Alias (User Manual Name) for CAN_MO136_AR.
+* To use register names with standard convension, please use CAN_MO136_AR.
+*/
+#define CAN_MOAR136 (CAN_MO136_AR)
+
+/** \brief 211C, Message Object Control Register */
+#define CAN_MO136_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A11Cu)
+
+/** Alias (User Manual Name) for CAN_MO136_CTR.
+* To use register names with standard convension, please use CAN_MO136_CTR.
+*/
+#define CAN_MOCTR136 (CAN_MO136_CTR)
+
+/** \brief 2114, Message Object Data Register High */
+#define CAN_MO136_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A114u)
+
+/** Alias (User Manual Name) for CAN_MO136_DATAH.
+* To use register names with standard convension, please use CAN_MO136_DATAH.
+*/
+#define CAN_MODATAH136 (CAN_MO136_DATAH)
+
+/** \brief 2110, Message Object Data Register Low */
+#define CAN_MO136_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A110u)
+
+/** Alias (User Manual Name) for CAN_MO136_DATAL.
+* To use register names with standard convension, please use CAN_MO136_DATAL.
+*/
+#define CAN_MODATAL136 (CAN_MO136_DATAL)
+
+/** \brief 2100, Message Object Function Control Register */
+#define CAN_MO136_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A100u)
+
+/** Alias (User Manual Name) for CAN_MO136_EDATA0.
+* To use register names with standard convension, please use CAN_MO136_EDATA0.
+*/
+#define CAN_EMO136DATA0 (CAN_MO136_EDATA0)
+
+/** \brief 2104, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO136_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A104u)
+
+/** Alias (User Manual Name) for CAN_MO136_EDATA1.
+* To use register names with standard convension, please use CAN_MO136_EDATA1.
+*/
+#define CAN_EMO136DATA1 (CAN_MO136_EDATA1)
+
+/** \brief 2108, Message Object Interrupt Pointer Register */
+#define CAN_MO136_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A108u)
+
+/** Alias (User Manual Name) for CAN_MO136_EDATA2.
+* To use register names with standard convension, please use CAN_MO136_EDATA2.
+*/
+#define CAN_EMO136DATA2 (CAN_MO136_EDATA2)
+
+/** \brief 210C, Message Object Acceptance Mask Register */
+#define CAN_MO136_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A10Cu)
+
+/** Alias (User Manual Name) for CAN_MO136_EDATA3.
+* To use register names with standard convension, please use CAN_MO136_EDATA3.
+*/
+#define CAN_EMO136DATA3 (CAN_MO136_EDATA3)
+
+/** \brief 2110, Message Object Data Register Low */
+#define CAN_MO136_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A110u)
+
+/** Alias (User Manual Name) for CAN_MO136_EDATA4.
+* To use register names with standard convension, please use CAN_MO136_EDATA4.
+*/
+#define CAN_EMO136DATA4 (CAN_MO136_EDATA4)
+
+/** \brief 2114, Message Object Data Register High */
+#define CAN_MO136_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A114u)
+
+/** Alias (User Manual Name) for CAN_MO136_EDATA5.
+* To use register names with standard convension, please use CAN_MO136_EDATA5.
+*/
+#define CAN_EMO136DATA5 (CAN_MO136_EDATA5)
+
+/** \brief 2118, Message Object Arbitration Register */
+#define CAN_MO136_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A118u)
+
+/** Alias (User Manual Name) for CAN_MO136_EDATA6.
+* To use register names with standard convension, please use CAN_MO136_EDATA6.
+*/
+#define CAN_EMO136DATA6 (CAN_MO136_EDATA6)
+
+/** \brief 2100, Message Object Function Control Register */
+#define CAN_MO136_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A100u)
+
+/** Alias (User Manual Name) for CAN_MO136_FCR.
+* To use register names with standard convension, please use CAN_MO136_FCR.
+*/
+#define CAN_MOFCR136 (CAN_MO136_FCR)
+
+/** \brief 2104, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO136_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A104u)
+
+/** Alias (User Manual Name) for CAN_MO136_FGPR.
+* To use register names with standard convension, please use CAN_MO136_FGPR.
+*/
+#define CAN_MOFGPR136 (CAN_MO136_FGPR)
+
+/** \brief 2108, Message Object Interrupt Pointer Register */
+#define CAN_MO136_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A108u)
+
+/** Alias (User Manual Name) for CAN_MO136_IPR.
+* To use register names with standard convension, please use CAN_MO136_IPR.
+*/
+#define CAN_MOIPR136 (CAN_MO136_IPR)
+
+/** \brief 211C, Message Object Control Register */
+#define CAN_MO136_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A11Cu)
+
+/** Alias (User Manual Name) for CAN_MO136_STAT.
+* To use register names with standard convension, please use CAN_MO136_STAT.
+*/
+#define CAN_MOSTAT136 (CAN_MO136_STAT)
+
+/** \brief 212C, Message Object Acceptance Mask Register */
+#define CAN_MO137_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A12Cu)
+
+/** Alias (User Manual Name) for CAN_MO137_AMR.
+* To use register names with standard convension, please use CAN_MO137_AMR.
+*/
+#define CAN_MOAMR137 (CAN_MO137_AMR)
+
+/** \brief 2138, Message Object Arbitration Register */
+#define CAN_MO137_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A138u)
+
+/** Alias (User Manual Name) for CAN_MO137_AR.
+* To use register names with standard convension, please use CAN_MO137_AR.
+*/
+#define CAN_MOAR137 (CAN_MO137_AR)
+
+/** \brief 213C, Message Object Control Register */
+#define CAN_MO137_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A13Cu)
+
+/** Alias (User Manual Name) for CAN_MO137_CTR.
+* To use register names with standard convension, please use CAN_MO137_CTR.
+*/
+#define CAN_MOCTR137 (CAN_MO137_CTR)
+
+/** \brief 2134, Message Object Data Register High */
+#define CAN_MO137_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A134u)
+
+/** Alias (User Manual Name) for CAN_MO137_DATAH.
+* To use register names with standard convension, please use CAN_MO137_DATAH.
+*/
+#define CAN_MODATAH137 (CAN_MO137_DATAH)
+
+/** \brief 2130, Message Object Data Register Low */
+#define CAN_MO137_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A130u)
+
+/** Alias (User Manual Name) for CAN_MO137_DATAL.
+* To use register names with standard convension, please use CAN_MO137_DATAL.
+*/
+#define CAN_MODATAL137 (CAN_MO137_DATAL)
+
+/** \brief 2120, Message Object Function Control Register */
+#define CAN_MO137_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A120u)
+
+/** Alias (User Manual Name) for CAN_MO137_EDATA0.
+* To use register names with standard convension, please use CAN_MO137_EDATA0.
+*/
+#define CAN_EMO137DATA0 (CAN_MO137_EDATA0)
+
+/** \brief 2124, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO137_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A124u)
+
+/** Alias (User Manual Name) for CAN_MO137_EDATA1.
+* To use register names with standard convension, please use CAN_MO137_EDATA1.
+*/
+#define CAN_EMO137DATA1 (CAN_MO137_EDATA1)
+
+/** \brief 2128, Message Object Interrupt Pointer Register */
+#define CAN_MO137_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A128u)
+
+/** Alias (User Manual Name) for CAN_MO137_EDATA2.
+* To use register names with standard convension, please use CAN_MO137_EDATA2.
+*/
+#define CAN_EMO137DATA2 (CAN_MO137_EDATA2)
+
+/** \brief 212C, Message Object Acceptance Mask Register */
+#define CAN_MO137_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A12Cu)
+
+/** Alias (User Manual Name) for CAN_MO137_EDATA3.
+* To use register names with standard convension, please use CAN_MO137_EDATA3.
+*/
+#define CAN_EMO137DATA3 (CAN_MO137_EDATA3)
+
+/** \brief 2130, Message Object Data Register Low */
+#define CAN_MO137_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A130u)
+
+/** Alias (User Manual Name) for CAN_MO137_EDATA4.
+* To use register names with standard convension, please use CAN_MO137_EDATA4.
+*/
+#define CAN_EMO137DATA4 (CAN_MO137_EDATA4)
+
+/** \brief 2134, Message Object Data Register High */
+#define CAN_MO137_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A134u)
+
+/** Alias (User Manual Name) for CAN_MO137_EDATA5.
+* To use register names with standard convension, please use CAN_MO137_EDATA5.
+*/
+#define CAN_EMO137DATA5 (CAN_MO137_EDATA5)
+
+/** \brief 2138, Message Object Arbitration Register */
+#define CAN_MO137_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A138u)
+
+/** Alias (User Manual Name) for CAN_MO137_EDATA6.
+* To use register names with standard convension, please use CAN_MO137_EDATA6.
+*/
+#define CAN_EMO137DATA6 (CAN_MO137_EDATA6)
+
+/** \brief 2120, Message Object Function Control Register */
+#define CAN_MO137_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A120u)
+
+/** Alias (User Manual Name) for CAN_MO137_FCR.
+* To use register names with standard convension, please use CAN_MO137_FCR.
+*/
+#define CAN_MOFCR137 (CAN_MO137_FCR)
+
+/** \brief 2124, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO137_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A124u)
+
+/** Alias (User Manual Name) for CAN_MO137_FGPR.
+* To use register names with standard convension, please use CAN_MO137_FGPR.
+*/
+#define CAN_MOFGPR137 (CAN_MO137_FGPR)
+
+/** \brief 2128, Message Object Interrupt Pointer Register */
+#define CAN_MO137_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A128u)
+
+/** Alias (User Manual Name) for CAN_MO137_IPR.
+* To use register names with standard convension, please use CAN_MO137_IPR.
+*/
+#define CAN_MOIPR137 (CAN_MO137_IPR)
+
+/** \brief 213C, Message Object Control Register */
+#define CAN_MO137_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A13Cu)
+
+/** Alias (User Manual Name) for CAN_MO137_STAT.
+* To use register names with standard convension, please use CAN_MO137_STAT.
+*/
+#define CAN_MOSTAT137 (CAN_MO137_STAT)
+
+/** \brief 214C, Message Object Acceptance Mask Register */
+#define CAN_MO138_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A14Cu)
+
+/** Alias (User Manual Name) for CAN_MO138_AMR.
+* To use register names with standard convension, please use CAN_MO138_AMR.
+*/
+#define CAN_MOAMR138 (CAN_MO138_AMR)
+
+/** \brief 2158, Message Object Arbitration Register */
+#define CAN_MO138_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A158u)
+
+/** Alias (User Manual Name) for CAN_MO138_AR.
+* To use register names with standard convension, please use CAN_MO138_AR.
+*/
+#define CAN_MOAR138 (CAN_MO138_AR)
+
+/** \brief 215C, Message Object Control Register */
+#define CAN_MO138_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A15Cu)
+
+/** Alias (User Manual Name) for CAN_MO138_CTR.
+* To use register names with standard convension, please use CAN_MO138_CTR.
+*/
+#define CAN_MOCTR138 (CAN_MO138_CTR)
+
+/** \brief 2154, Message Object Data Register High */
+#define CAN_MO138_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A154u)
+
+/** Alias (User Manual Name) for CAN_MO138_DATAH.
+* To use register names with standard convension, please use CAN_MO138_DATAH.
+*/
+#define CAN_MODATAH138 (CAN_MO138_DATAH)
+
+/** \brief 2150, Message Object Data Register Low */
+#define CAN_MO138_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A150u)
+
+/** Alias (User Manual Name) for CAN_MO138_DATAL.
+* To use register names with standard convension, please use CAN_MO138_DATAL.
+*/
+#define CAN_MODATAL138 (CAN_MO138_DATAL)
+
+/** \brief 2140, Message Object Function Control Register */
+#define CAN_MO138_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A140u)
+
+/** Alias (User Manual Name) for CAN_MO138_EDATA0.
+* To use register names with standard convension, please use CAN_MO138_EDATA0.
+*/
+#define CAN_EMO138DATA0 (CAN_MO138_EDATA0)
+
+/** \brief 2144, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO138_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A144u)
+
+/** Alias (User Manual Name) for CAN_MO138_EDATA1.
+* To use register names with standard convension, please use CAN_MO138_EDATA1.
+*/
+#define CAN_EMO138DATA1 (CAN_MO138_EDATA1)
+
+/** \brief 2148, Message Object Interrupt Pointer Register */
+#define CAN_MO138_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A148u)
+
+/** Alias (User Manual Name) for CAN_MO138_EDATA2.
+* To use register names with standard convension, please use CAN_MO138_EDATA2.
+*/
+#define CAN_EMO138DATA2 (CAN_MO138_EDATA2)
+
+/** \brief 214C, Message Object Acceptance Mask Register */
+#define CAN_MO138_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A14Cu)
+
+/** Alias (User Manual Name) for CAN_MO138_EDATA3.
+* To use register names with standard convension, please use CAN_MO138_EDATA3.
+*/
+#define CAN_EMO138DATA3 (CAN_MO138_EDATA3)
+
+/** \brief 2150, Message Object Data Register Low */
+#define CAN_MO138_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A150u)
+
+/** Alias (User Manual Name) for CAN_MO138_EDATA4.
+* To use register names with standard convension, please use CAN_MO138_EDATA4.
+*/
+#define CAN_EMO138DATA4 (CAN_MO138_EDATA4)
+
+/** \brief 2154, Message Object Data Register High */
+#define CAN_MO138_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A154u)
+
+/** Alias (User Manual Name) for CAN_MO138_EDATA5.
+* To use register names with standard convension, please use CAN_MO138_EDATA5.
+*/
+#define CAN_EMO138DATA5 (CAN_MO138_EDATA5)
+
+/** \brief 2158, Message Object Arbitration Register */
+#define CAN_MO138_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A158u)
+
+/** Alias (User Manual Name) for CAN_MO138_EDATA6.
+* To use register names with standard convension, please use CAN_MO138_EDATA6.
+*/
+#define CAN_EMO138DATA6 (CAN_MO138_EDATA6)
+
+/** \brief 2140, Message Object Function Control Register */
+#define CAN_MO138_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A140u)
+
+/** Alias (User Manual Name) for CAN_MO138_FCR.
+* To use register names with standard convension, please use CAN_MO138_FCR.
+*/
+#define CAN_MOFCR138 (CAN_MO138_FCR)
+
+/** \brief 2144, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO138_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A144u)
+
+/** Alias (User Manual Name) for CAN_MO138_FGPR.
+* To use register names with standard convension, please use CAN_MO138_FGPR.
+*/
+#define CAN_MOFGPR138 (CAN_MO138_FGPR)
+
+/** \brief 2148, Message Object Interrupt Pointer Register */
+#define CAN_MO138_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A148u)
+
+/** Alias (User Manual Name) for CAN_MO138_IPR.
+* To use register names with standard convension, please use CAN_MO138_IPR.
+*/
+#define CAN_MOIPR138 (CAN_MO138_IPR)
+
+/** \brief 215C, Message Object Control Register */
+#define CAN_MO138_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A15Cu)
+
+/** Alias (User Manual Name) for CAN_MO138_STAT.
+* To use register names with standard convension, please use CAN_MO138_STAT.
+*/
+#define CAN_MOSTAT138 (CAN_MO138_STAT)
+
+/** \brief 216C, Message Object Acceptance Mask Register */
+#define CAN_MO139_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A16Cu)
+
+/** Alias (User Manual Name) for CAN_MO139_AMR.
+* To use register names with standard convension, please use CAN_MO139_AMR.
+*/
+#define CAN_MOAMR139 (CAN_MO139_AMR)
+
+/** \brief 2178, Message Object Arbitration Register */
+#define CAN_MO139_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A178u)
+
+/** Alias (User Manual Name) for CAN_MO139_AR.
+* To use register names with standard convension, please use CAN_MO139_AR.
+*/
+#define CAN_MOAR139 (CAN_MO139_AR)
+
+/** \brief 217C, Message Object Control Register */
+#define CAN_MO139_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A17Cu)
+
+/** Alias (User Manual Name) for CAN_MO139_CTR.
+* To use register names with standard convension, please use CAN_MO139_CTR.
+*/
+#define CAN_MOCTR139 (CAN_MO139_CTR)
+
+/** \brief 2174, Message Object Data Register High */
+#define CAN_MO139_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A174u)
+
+/** Alias (User Manual Name) for CAN_MO139_DATAH.
+* To use register names with standard convension, please use CAN_MO139_DATAH.
+*/
+#define CAN_MODATAH139 (CAN_MO139_DATAH)
+
+/** \brief 2170, Message Object Data Register Low */
+#define CAN_MO139_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A170u)
+
+/** Alias (User Manual Name) for CAN_MO139_DATAL.
+* To use register names with standard convension, please use CAN_MO139_DATAL.
+*/
+#define CAN_MODATAL139 (CAN_MO139_DATAL)
+
+/** \brief 2160, Message Object Function Control Register */
+#define CAN_MO139_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A160u)
+
+/** Alias (User Manual Name) for CAN_MO139_EDATA0.
+* To use register names with standard convension, please use CAN_MO139_EDATA0.
+*/
+#define CAN_EMO139DATA0 (CAN_MO139_EDATA0)
+
+/** \brief 2164, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO139_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A164u)
+
+/** Alias (User Manual Name) for CAN_MO139_EDATA1.
+* To use register names with standard convension, please use CAN_MO139_EDATA1.
+*/
+#define CAN_EMO139DATA1 (CAN_MO139_EDATA1)
+
+/** \brief 2168, Message Object Interrupt Pointer Register */
+#define CAN_MO139_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A168u)
+
+/** Alias (User Manual Name) for CAN_MO139_EDATA2.
+* To use register names with standard convension, please use CAN_MO139_EDATA2.
+*/
+#define CAN_EMO139DATA2 (CAN_MO139_EDATA2)
+
+/** \brief 216C, Message Object Acceptance Mask Register */
+#define CAN_MO139_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A16Cu)
+
+/** Alias (User Manual Name) for CAN_MO139_EDATA3.
+* To use register names with standard convension, please use CAN_MO139_EDATA3.
+*/
+#define CAN_EMO139DATA3 (CAN_MO139_EDATA3)
+
+/** \brief 2170, Message Object Data Register Low */
+#define CAN_MO139_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A170u)
+
+/** Alias (User Manual Name) for CAN_MO139_EDATA4.
+* To use register names with standard convension, please use CAN_MO139_EDATA4.
+*/
+#define CAN_EMO139DATA4 (CAN_MO139_EDATA4)
+
+/** \brief 2174, Message Object Data Register High */
+#define CAN_MO139_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A174u)
+
+/** Alias (User Manual Name) for CAN_MO139_EDATA5.
+* To use register names with standard convension, please use CAN_MO139_EDATA5.
+*/
+#define CAN_EMO139DATA5 (CAN_MO139_EDATA5)
+
+/** \brief 2178, Message Object Arbitration Register */
+#define CAN_MO139_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A178u)
+
+/** Alias (User Manual Name) for CAN_MO139_EDATA6.
+* To use register names with standard convension, please use CAN_MO139_EDATA6.
+*/
+#define CAN_EMO139DATA6 (CAN_MO139_EDATA6)
+
+/** \brief 2160, Message Object Function Control Register */
+#define CAN_MO139_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A160u)
+
+/** Alias (User Manual Name) for CAN_MO139_FCR.
+* To use register names with standard convension, please use CAN_MO139_FCR.
+*/
+#define CAN_MOFCR139 (CAN_MO139_FCR)
+
+/** \brief 2164, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO139_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A164u)
+
+/** Alias (User Manual Name) for CAN_MO139_FGPR.
+* To use register names with standard convension, please use CAN_MO139_FGPR.
+*/
+#define CAN_MOFGPR139 (CAN_MO139_FGPR)
+
+/** \brief 2168, Message Object Interrupt Pointer Register */
+#define CAN_MO139_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A168u)
+
+/** Alias (User Manual Name) for CAN_MO139_IPR.
+* To use register names with standard convension, please use CAN_MO139_IPR.
+*/
+#define CAN_MOIPR139 (CAN_MO139_IPR)
+
+/** \brief 217C, Message Object Control Register */
+#define CAN_MO139_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A17Cu)
+
+/** Alias (User Manual Name) for CAN_MO139_STAT.
+* To use register names with standard convension, please use CAN_MO139_STAT.
+*/
+#define CAN_MOSTAT139 (CAN_MO139_STAT)
+
+/** \brief 11AC, Message Object Acceptance Mask Register */
+#define CAN_MO13_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00191ACu)
+
+/** Alias (User Manual Name) for CAN_MO13_AMR.
+* To use register names with standard convension, please use CAN_MO13_AMR.
+*/
+#define CAN_MOAMR13 (CAN_MO13_AMR)
+
+/** \brief 11B8, Message Object Arbitration Register */
+#define CAN_MO13_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00191B8u)
+
+/** Alias (User Manual Name) for CAN_MO13_AR.
+* To use register names with standard convension, please use CAN_MO13_AR.
+*/
+#define CAN_MOAR13 (CAN_MO13_AR)
+
+/** \brief 11BC, Message Object Control Register */
+#define CAN_MO13_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00191BCu)
+
+/** Alias (User Manual Name) for CAN_MO13_CTR.
+* To use register names with standard convension, please use CAN_MO13_CTR.
+*/
+#define CAN_MOCTR13 (CAN_MO13_CTR)
+
+/** \brief 11B4, Message Object Data Register High */
+#define CAN_MO13_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00191B4u)
+
+/** Alias (User Manual Name) for CAN_MO13_DATAH.
+* To use register names with standard convension, please use CAN_MO13_DATAH.
+*/
+#define CAN_MODATAH13 (CAN_MO13_DATAH)
+
+/** \brief 11B0, Message Object Data Register Low */
+#define CAN_MO13_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00191B0u)
+
+/** Alias (User Manual Name) for CAN_MO13_DATAL.
+* To use register names with standard convension, please use CAN_MO13_DATAL.
+*/
+#define CAN_MODATAL13 (CAN_MO13_DATAL)
+
+/** \brief 11A0, Message Object Function Control Register */
+#define CAN_MO13_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00191A0u)
+
+/** Alias (User Manual Name) for CAN_MO13_EDATA0.
+* To use register names with standard convension, please use CAN_MO13_EDATA0.
+*/
+#define CAN_EMO13DATA0 (CAN_MO13_EDATA0)
+
+/** \brief 11A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO13_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00191A4u)
+
+/** Alias (User Manual Name) for CAN_MO13_EDATA1.
+* To use register names with standard convension, please use CAN_MO13_EDATA1.
+*/
+#define CAN_EMO13DATA1 (CAN_MO13_EDATA1)
+
+/** \brief 11A8, Message Object Interrupt Pointer Register */
+#define CAN_MO13_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00191A8u)
+
+/** Alias (User Manual Name) for CAN_MO13_EDATA2.
+* To use register names with standard convension, please use CAN_MO13_EDATA2.
+*/
+#define CAN_EMO13DATA2 (CAN_MO13_EDATA2)
+
+/** \brief 11AC, Message Object Acceptance Mask Register */
+#define CAN_MO13_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00191ACu)
+
+/** Alias (User Manual Name) for CAN_MO13_EDATA3.
+* To use register names with standard convension, please use CAN_MO13_EDATA3.
+*/
+#define CAN_EMO13DATA3 (CAN_MO13_EDATA3)
+
+/** \brief 11B0, Message Object Data Register Low */
+#define CAN_MO13_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00191B0u)
+
+/** Alias (User Manual Name) for CAN_MO13_EDATA4.
+* To use register names with standard convension, please use CAN_MO13_EDATA4.
+*/
+#define CAN_EMO13DATA4 (CAN_MO13_EDATA4)
+
+/** \brief 11B4, Message Object Data Register High */
+#define CAN_MO13_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00191B4u)
+
+/** Alias (User Manual Name) for CAN_MO13_EDATA5.
+* To use register names with standard convension, please use CAN_MO13_EDATA5.
+*/
+#define CAN_EMO13DATA5 (CAN_MO13_EDATA5)
+
+/** \brief 11B8, Message Object Arbitration Register */
+#define CAN_MO13_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00191B8u)
+
+/** Alias (User Manual Name) for CAN_MO13_EDATA6.
+* To use register names with standard convension, please use CAN_MO13_EDATA6.
+*/
+#define CAN_EMO13DATA6 (CAN_MO13_EDATA6)
+
+/** \brief 11A0, Message Object Function Control Register */
+#define CAN_MO13_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00191A0u)
+
+/** Alias (User Manual Name) for CAN_MO13_FCR.
+* To use register names with standard convension, please use CAN_MO13_FCR.
+*/
+#define CAN_MOFCR13 (CAN_MO13_FCR)
+
+/** \brief 11A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO13_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00191A4u)
+
+/** Alias (User Manual Name) for CAN_MO13_FGPR.
+* To use register names with standard convension, please use CAN_MO13_FGPR.
+*/
+#define CAN_MOFGPR13 (CAN_MO13_FGPR)
+
+/** \brief 11A8, Message Object Interrupt Pointer Register */
+#define CAN_MO13_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00191A8u)
+
+/** Alias (User Manual Name) for CAN_MO13_IPR.
+* To use register names with standard convension, please use CAN_MO13_IPR.
+*/
+#define CAN_MOIPR13 (CAN_MO13_IPR)
+
+/** \brief 11BC, Message Object Control Register */
+#define CAN_MO13_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00191BCu)
+
+/** Alias (User Manual Name) for CAN_MO13_STAT.
+* To use register names with standard convension, please use CAN_MO13_STAT.
+*/
+#define CAN_MOSTAT13 (CAN_MO13_STAT)
+
+/** \brief 218C, Message Object Acceptance Mask Register */
+#define CAN_MO140_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A18Cu)
+
+/** Alias (User Manual Name) for CAN_MO140_AMR.
+* To use register names with standard convension, please use CAN_MO140_AMR.
+*/
+#define CAN_MOAMR140 (CAN_MO140_AMR)
+
+/** \brief 2198, Message Object Arbitration Register */
+#define CAN_MO140_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A198u)
+
+/** Alias (User Manual Name) for CAN_MO140_AR.
+* To use register names with standard convension, please use CAN_MO140_AR.
+*/
+#define CAN_MOAR140 (CAN_MO140_AR)
+
+/** \brief 219C, Message Object Control Register */
+#define CAN_MO140_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A19Cu)
+
+/** Alias (User Manual Name) for CAN_MO140_CTR.
+* To use register names with standard convension, please use CAN_MO140_CTR.
+*/
+#define CAN_MOCTR140 (CAN_MO140_CTR)
+
+/** \brief 2194, Message Object Data Register High */
+#define CAN_MO140_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A194u)
+
+/** Alias (User Manual Name) for CAN_MO140_DATAH.
+* To use register names with standard convension, please use CAN_MO140_DATAH.
+*/
+#define CAN_MODATAH140 (CAN_MO140_DATAH)
+
+/** \brief 2190, Message Object Data Register Low */
+#define CAN_MO140_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A190u)
+
+/** Alias (User Manual Name) for CAN_MO140_DATAL.
+* To use register names with standard convension, please use CAN_MO140_DATAL.
+*/
+#define CAN_MODATAL140 (CAN_MO140_DATAL)
+
+/** \brief 2180, Message Object Function Control Register */
+#define CAN_MO140_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A180u)
+
+/** Alias (User Manual Name) for CAN_MO140_EDATA0.
+* To use register names with standard convension, please use CAN_MO140_EDATA0.
+*/
+#define CAN_EMO140DATA0 (CAN_MO140_EDATA0)
+
+/** \brief 2184, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO140_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A184u)
+
+/** Alias (User Manual Name) for CAN_MO140_EDATA1.
+* To use register names with standard convension, please use CAN_MO140_EDATA1.
+*/
+#define CAN_EMO140DATA1 (CAN_MO140_EDATA1)
+
+/** \brief 2188, Message Object Interrupt Pointer Register */
+#define CAN_MO140_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A188u)
+
+/** Alias (User Manual Name) for CAN_MO140_EDATA2.
+* To use register names with standard convension, please use CAN_MO140_EDATA2.
+*/
+#define CAN_EMO140DATA2 (CAN_MO140_EDATA2)
+
+/** \brief 218C, Message Object Acceptance Mask Register */
+#define CAN_MO140_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A18Cu)
+
+/** Alias (User Manual Name) for CAN_MO140_EDATA3.
+* To use register names with standard convension, please use CAN_MO140_EDATA3.
+*/
+#define CAN_EMO140DATA3 (CAN_MO140_EDATA3)
+
+/** \brief 2190, Message Object Data Register Low */
+#define CAN_MO140_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A190u)
+
+/** Alias (User Manual Name) for CAN_MO140_EDATA4.
+* To use register names with standard convension, please use CAN_MO140_EDATA4.
+*/
+#define CAN_EMO140DATA4 (CAN_MO140_EDATA4)
+
+/** \brief 2194, Message Object Data Register High */
+#define CAN_MO140_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A194u)
+
+/** Alias (User Manual Name) for CAN_MO140_EDATA5.
+* To use register names with standard convension, please use CAN_MO140_EDATA5.
+*/
+#define CAN_EMO140DATA5 (CAN_MO140_EDATA5)
+
+/** \brief 2198, Message Object Arbitration Register */
+#define CAN_MO140_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A198u)
+
+/** Alias (User Manual Name) for CAN_MO140_EDATA6.
+* To use register names with standard convension, please use CAN_MO140_EDATA6.
+*/
+#define CAN_EMO140DATA6 (CAN_MO140_EDATA6)
+
+/** \brief 2180, Message Object Function Control Register */
+#define CAN_MO140_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A180u)
+
+/** Alias (User Manual Name) for CAN_MO140_FCR.
+* To use register names with standard convension, please use CAN_MO140_FCR.
+*/
+#define CAN_MOFCR140 (CAN_MO140_FCR)
+
+/** \brief 2184, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO140_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A184u)
+
+/** Alias (User Manual Name) for CAN_MO140_FGPR.
+* To use register names with standard convension, please use CAN_MO140_FGPR.
+*/
+#define CAN_MOFGPR140 (CAN_MO140_FGPR)
+
+/** \brief 2188, Message Object Interrupt Pointer Register */
+#define CAN_MO140_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A188u)
+
+/** Alias (User Manual Name) for CAN_MO140_IPR.
+* To use register names with standard convension, please use CAN_MO140_IPR.
+*/
+#define CAN_MOIPR140 (CAN_MO140_IPR)
+
+/** \brief 219C, Message Object Control Register */
+#define CAN_MO140_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A19Cu)
+
+/** Alias (User Manual Name) for CAN_MO140_STAT.
+* To use register names with standard convension, please use CAN_MO140_STAT.
+*/
+#define CAN_MOSTAT140 (CAN_MO140_STAT)
+
+/** \brief 21AC, Message Object Acceptance Mask Register */
+#define CAN_MO141_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A1ACu)
+
+/** Alias (User Manual Name) for CAN_MO141_AMR.
+* To use register names with standard convension, please use CAN_MO141_AMR.
+*/
+#define CAN_MOAMR141 (CAN_MO141_AMR)
+
+/** \brief 21B8, Message Object Arbitration Register */
+#define CAN_MO141_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A1B8u)
+
+/** Alias (User Manual Name) for CAN_MO141_AR.
+* To use register names with standard convension, please use CAN_MO141_AR.
+*/
+#define CAN_MOAR141 (CAN_MO141_AR)
+
+/** \brief 21BC, Message Object Control Register */
+#define CAN_MO141_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A1BCu)
+
+/** Alias (User Manual Name) for CAN_MO141_CTR.
+* To use register names with standard convension, please use CAN_MO141_CTR.
+*/
+#define CAN_MOCTR141 (CAN_MO141_CTR)
+
+/** \brief 21B4, Message Object Data Register High */
+#define CAN_MO141_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A1B4u)
+
+/** Alias (User Manual Name) for CAN_MO141_DATAH.
+* To use register names with standard convension, please use CAN_MO141_DATAH.
+*/
+#define CAN_MODATAH141 (CAN_MO141_DATAH)
+
+/** \brief 21B0, Message Object Data Register Low */
+#define CAN_MO141_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A1B0u)
+
+/** Alias (User Manual Name) for CAN_MO141_DATAL.
+* To use register names with standard convension, please use CAN_MO141_DATAL.
+*/
+#define CAN_MODATAL141 (CAN_MO141_DATAL)
+
+/** \brief 21A0, Message Object Function Control Register */
+#define CAN_MO141_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A1A0u)
+
+/** Alias (User Manual Name) for CAN_MO141_EDATA0.
+* To use register names with standard convension, please use CAN_MO141_EDATA0.
+*/
+#define CAN_EMO141DATA0 (CAN_MO141_EDATA0)
+
+/** \brief 21A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO141_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A1A4u)
+
+/** Alias (User Manual Name) for CAN_MO141_EDATA1.
+* To use register names with standard convension, please use CAN_MO141_EDATA1.
+*/
+#define CAN_EMO141DATA1 (CAN_MO141_EDATA1)
+
+/** \brief 21A8, Message Object Interrupt Pointer Register */
+#define CAN_MO141_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A1A8u)
+
+/** Alias (User Manual Name) for CAN_MO141_EDATA2.
+* To use register names with standard convension, please use CAN_MO141_EDATA2.
+*/
+#define CAN_EMO141DATA2 (CAN_MO141_EDATA2)
+
+/** \brief 21AC, Message Object Acceptance Mask Register */
+#define CAN_MO141_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A1ACu)
+
+/** Alias (User Manual Name) for CAN_MO141_EDATA3.
+* To use register names with standard convension, please use CAN_MO141_EDATA3.
+*/
+#define CAN_EMO141DATA3 (CAN_MO141_EDATA3)
+
+/** \brief 21B0, Message Object Data Register Low */
+#define CAN_MO141_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A1B0u)
+
+/** Alias (User Manual Name) for CAN_MO141_EDATA4.
+* To use register names with standard convension, please use CAN_MO141_EDATA4.
+*/
+#define CAN_EMO141DATA4 (CAN_MO141_EDATA4)
+
+/** \brief 21B4, Message Object Data Register High */
+#define CAN_MO141_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A1B4u)
+
+/** Alias (User Manual Name) for CAN_MO141_EDATA5.
+* To use register names with standard convension, please use CAN_MO141_EDATA5.
+*/
+#define CAN_EMO141DATA5 (CAN_MO141_EDATA5)
+
+/** \brief 21B8, Message Object Arbitration Register */
+#define CAN_MO141_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A1B8u)
+
+/** Alias (User Manual Name) for CAN_MO141_EDATA6.
+* To use register names with standard convension, please use CAN_MO141_EDATA6.
+*/
+#define CAN_EMO141DATA6 (CAN_MO141_EDATA6)
+
+/** \brief 21A0, Message Object Function Control Register */
+#define CAN_MO141_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A1A0u)
+
+/** Alias (User Manual Name) for CAN_MO141_FCR.
+* To use register names with standard convension, please use CAN_MO141_FCR.
+*/
+#define CAN_MOFCR141 (CAN_MO141_FCR)
+
+/** \brief 21A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO141_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A1A4u)
+
+/** Alias (User Manual Name) for CAN_MO141_FGPR.
+* To use register names with standard convension, please use CAN_MO141_FGPR.
+*/
+#define CAN_MOFGPR141 (CAN_MO141_FGPR)
+
+/** \brief 21A8, Message Object Interrupt Pointer Register */
+#define CAN_MO141_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A1A8u)
+
+/** Alias (User Manual Name) for CAN_MO141_IPR.
+* To use register names with standard convension, please use CAN_MO141_IPR.
+*/
+#define CAN_MOIPR141 (CAN_MO141_IPR)
+
+/** \brief 21BC, Message Object Control Register */
+#define CAN_MO141_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A1BCu)
+
+/** Alias (User Manual Name) for CAN_MO141_STAT.
+* To use register names with standard convension, please use CAN_MO141_STAT.
+*/
+#define CAN_MOSTAT141 (CAN_MO141_STAT)
+
+/** \brief 21CC, Message Object Acceptance Mask Register */
+#define CAN_MO142_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A1CCu)
+
+/** Alias (User Manual Name) for CAN_MO142_AMR.
+* To use register names with standard convension, please use CAN_MO142_AMR.
+*/
+#define CAN_MOAMR142 (CAN_MO142_AMR)
+
+/** \brief 21D8, Message Object Arbitration Register */
+#define CAN_MO142_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A1D8u)
+
+/** Alias (User Manual Name) for CAN_MO142_AR.
+* To use register names with standard convension, please use CAN_MO142_AR.
+*/
+#define CAN_MOAR142 (CAN_MO142_AR)
+
+/** \brief 21DC, Message Object Control Register */
+#define CAN_MO142_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A1DCu)
+
+/** Alias (User Manual Name) for CAN_MO142_CTR.
+* To use register names with standard convension, please use CAN_MO142_CTR.
+*/
+#define CAN_MOCTR142 (CAN_MO142_CTR)
+
+/** \brief 21D4, Message Object Data Register High */
+#define CAN_MO142_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A1D4u)
+
+/** Alias (User Manual Name) for CAN_MO142_DATAH.
+* To use register names with standard convension, please use CAN_MO142_DATAH.
+*/
+#define CAN_MODATAH142 (CAN_MO142_DATAH)
+
+/** \brief 21D0, Message Object Data Register Low */
+#define CAN_MO142_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A1D0u)
+
+/** Alias (User Manual Name) for CAN_MO142_DATAL.
+* To use register names with standard convension, please use CAN_MO142_DATAL.
+*/
+#define CAN_MODATAL142 (CAN_MO142_DATAL)
+
+/** \brief 21C0, Message Object Function Control Register */
+#define CAN_MO142_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A1C0u)
+
+/** Alias (User Manual Name) for CAN_MO142_EDATA0.
+* To use register names with standard convension, please use CAN_MO142_EDATA0.
+*/
+#define CAN_EMO142DATA0 (CAN_MO142_EDATA0)
+
+/** \brief 21C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO142_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A1C4u)
+
+/** Alias (User Manual Name) for CAN_MO142_EDATA1.
+* To use register names with standard convension, please use CAN_MO142_EDATA1.
+*/
+#define CAN_EMO142DATA1 (CAN_MO142_EDATA1)
+
+/** \brief 21C8, Message Object Interrupt Pointer Register */
+#define CAN_MO142_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A1C8u)
+
+/** Alias (User Manual Name) for CAN_MO142_EDATA2.
+* To use register names with standard convension, please use CAN_MO142_EDATA2.
+*/
+#define CAN_EMO142DATA2 (CAN_MO142_EDATA2)
+
+/** \brief 21CC, Message Object Acceptance Mask Register */
+#define CAN_MO142_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A1CCu)
+
+/** Alias (User Manual Name) for CAN_MO142_EDATA3.
+* To use register names with standard convension, please use CAN_MO142_EDATA3.
+*/
+#define CAN_EMO142DATA3 (CAN_MO142_EDATA3)
+
+/** \brief 21D0, Message Object Data Register Low */
+#define CAN_MO142_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A1D0u)
+
+/** Alias (User Manual Name) for CAN_MO142_EDATA4.
+* To use register names with standard convension, please use CAN_MO142_EDATA4.
+*/
+#define CAN_EMO142DATA4 (CAN_MO142_EDATA4)
+
+/** \brief 21D4, Message Object Data Register High */
+#define CAN_MO142_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A1D4u)
+
+/** Alias (User Manual Name) for CAN_MO142_EDATA5.
+* To use register names with standard convension, please use CAN_MO142_EDATA5.
+*/
+#define CAN_EMO142DATA5 (CAN_MO142_EDATA5)
+
+/** \brief 21D8, Message Object Arbitration Register */
+#define CAN_MO142_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A1D8u)
+
+/** Alias (User Manual Name) for CAN_MO142_EDATA6.
+* To use register names with standard convension, please use CAN_MO142_EDATA6.
+*/
+#define CAN_EMO142DATA6 (CAN_MO142_EDATA6)
+
+/** \brief 21C0, Message Object Function Control Register */
+#define CAN_MO142_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A1C0u)
+
+/** Alias (User Manual Name) for CAN_MO142_FCR.
+* To use register names with standard convension, please use CAN_MO142_FCR.
+*/
+#define CAN_MOFCR142 (CAN_MO142_FCR)
+
+/** \brief 21C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO142_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A1C4u)
+
+/** Alias (User Manual Name) for CAN_MO142_FGPR.
+* To use register names with standard convension, please use CAN_MO142_FGPR.
+*/
+#define CAN_MOFGPR142 (CAN_MO142_FGPR)
+
+/** \brief 21C8, Message Object Interrupt Pointer Register */
+#define CAN_MO142_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A1C8u)
+
+/** Alias (User Manual Name) for CAN_MO142_IPR.
+* To use register names with standard convension, please use CAN_MO142_IPR.
+*/
+#define CAN_MOIPR142 (CAN_MO142_IPR)
+
+/** \brief 21DC, Message Object Control Register */
+#define CAN_MO142_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A1DCu)
+
+/** Alias (User Manual Name) for CAN_MO142_STAT.
+* To use register names with standard convension, please use CAN_MO142_STAT.
+*/
+#define CAN_MOSTAT142 (CAN_MO142_STAT)
+
+/** \brief 21EC, Message Object Acceptance Mask Register */
+#define CAN_MO143_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A1ECu)
+
+/** Alias (User Manual Name) for CAN_MO143_AMR.
+* To use register names with standard convension, please use CAN_MO143_AMR.
+*/
+#define CAN_MOAMR143 (CAN_MO143_AMR)
+
+/** \brief 21F8, Message Object Arbitration Register */
+#define CAN_MO143_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A1F8u)
+
+/** Alias (User Manual Name) for CAN_MO143_AR.
+* To use register names with standard convension, please use CAN_MO143_AR.
+*/
+#define CAN_MOAR143 (CAN_MO143_AR)
+
+/** \brief 21FC, Message Object Control Register */
+#define CAN_MO143_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A1FCu)
+
+/** Alias (User Manual Name) for CAN_MO143_CTR.
+* To use register names with standard convension, please use CAN_MO143_CTR.
+*/
+#define CAN_MOCTR143 (CAN_MO143_CTR)
+
+/** \brief 21F4, Message Object Data Register High */
+#define CAN_MO143_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A1F4u)
+
+/** Alias (User Manual Name) for CAN_MO143_DATAH.
+* To use register names with standard convension, please use CAN_MO143_DATAH.
+*/
+#define CAN_MODATAH143 (CAN_MO143_DATAH)
+
+/** \brief 21F0, Message Object Data Register Low */
+#define CAN_MO143_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A1F0u)
+
+/** Alias (User Manual Name) for CAN_MO143_DATAL.
+* To use register names with standard convension, please use CAN_MO143_DATAL.
+*/
+#define CAN_MODATAL143 (CAN_MO143_DATAL)
+
+/** \brief 21E0, Message Object Function Control Register */
+#define CAN_MO143_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A1E0u)
+
+/** Alias (User Manual Name) for CAN_MO143_EDATA0.
+* To use register names with standard convension, please use CAN_MO143_EDATA0.
+*/
+#define CAN_EMO143DATA0 (CAN_MO143_EDATA0)
+
+/** \brief 21E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO143_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A1E4u)
+
+/** Alias (User Manual Name) for CAN_MO143_EDATA1.
+* To use register names with standard convension, please use CAN_MO143_EDATA1.
+*/
+#define CAN_EMO143DATA1 (CAN_MO143_EDATA1)
+
+/** \brief 21E8, Message Object Interrupt Pointer Register */
+#define CAN_MO143_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A1E8u)
+
+/** Alias (User Manual Name) for CAN_MO143_EDATA2.
+* To use register names with standard convension, please use CAN_MO143_EDATA2.
+*/
+#define CAN_EMO143DATA2 (CAN_MO143_EDATA2)
+
+/** \brief 21EC, Message Object Acceptance Mask Register */
+#define CAN_MO143_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A1ECu)
+
+/** Alias (User Manual Name) for CAN_MO143_EDATA3.
+* To use register names with standard convension, please use CAN_MO143_EDATA3.
+*/
+#define CAN_EMO143DATA3 (CAN_MO143_EDATA3)
+
+/** \brief 21F0, Message Object Data Register Low */
+#define CAN_MO143_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A1F0u)
+
+/** Alias (User Manual Name) for CAN_MO143_EDATA4.
+* To use register names with standard convension, please use CAN_MO143_EDATA4.
+*/
+#define CAN_EMO143DATA4 (CAN_MO143_EDATA4)
+
+/** \brief 21F4, Message Object Data Register High */
+#define CAN_MO143_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A1F4u)
+
+/** Alias (User Manual Name) for CAN_MO143_EDATA5.
+* To use register names with standard convension, please use CAN_MO143_EDATA5.
+*/
+#define CAN_EMO143DATA5 (CAN_MO143_EDATA5)
+
+/** \brief 21F8, Message Object Arbitration Register */
+#define CAN_MO143_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A1F8u)
+
+/** Alias (User Manual Name) for CAN_MO143_EDATA6.
+* To use register names with standard convension, please use CAN_MO143_EDATA6.
+*/
+#define CAN_EMO143DATA6 (CAN_MO143_EDATA6)
+
+/** \brief 21E0, Message Object Function Control Register */
+#define CAN_MO143_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A1E0u)
+
+/** Alias (User Manual Name) for CAN_MO143_FCR.
+* To use register names with standard convension, please use CAN_MO143_FCR.
+*/
+#define CAN_MOFCR143 (CAN_MO143_FCR)
+
+/** \brief 21E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO143_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A1E4u)
+
+/** Alias (User Manual Name) for CAN_MO143_FGPR.
+* To use register names with standard convension, please use CAN_MO143_FGPR.
+*/
+#define CAN_MOFGPR143 (CAN_MO143_FGPR)
+
+/** \brief 21E8, Message Object Interrupt Pointer Register */
+#define CAN_MO143_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A1E8u)
+
+/** Alias (User Manual Name) for CAN_MO143_IPR.
+* To use register names with standard convension, please use CAN_MO143_IPR.
+*/
+#define CAN_MOIPR143 (CAN_MO143_IPR)
+
+/** \brief 21FC, Message Object Control Register */
+#define CAN_MO143_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A1FCu)
+
+/** Alias (User Manual Name) for CAN_MO143_STAT.
+* To use register names with standard convension, please use CAN_MO143_STAT.
+*/
+#define CAN_MOSTAT143 (CAN_MO143_STAT)
+
+/** \brief 220C, Message Object Acceptance Mask Register */
+#define CAN_MO144_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A20Cu)
+
+/** Alias (User Manual Name) for CAN_MO144_AMR.
+* To use register names with standard convension, please use CAN_MO144_AMR.
+*/
+#define CAN_MOAMR144 (CAN_MO144_AMR)
+
+/** \brief 2218, Message Object Arbitration Register */
+#define CAN_MO144_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A218u)
+
+/** Alias (User Manual Name) for CAN_MO144_AR.
+* To use register names with standard convension, please use CAN_MO144_AR.
+*/
+#define CAN_MOAR144 (CAN_MO144_AR)
+
+/** \brief 221C, Message Object Control Register */
+#define CAN_MO144_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A21Cu)
+
+/** Alias (User Manual Name) for CAN_MO144_CTR.
+* To use register names with standard convension, please use CAN_MO144_CTR.
+*/
+#define CAN_MOCTR144 (CAN_MO144_CTR)
+
+/** \brief 2214, Message Object Data Register High */
+#define CAN_MO144_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A214u)
+
+/** Alias (User Manual Name) for CAN_MO144_DATAH.
+* To use register names with standard convension, please use CAN_MO144_DATAH.
+*/
+#define CAN_MODATAH144 (CAN_MO144_DATAH)
+
+/** \brief 2210, Message Object Data Register Low */
+#define CAN_MO144_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A210u)
+
+/** Alias (User Manual Name) for CAN_MO144_DATAL.
+* To use register names with standard convension, please use CAN_MO144_DATAL.
+*/
+#define CAN_MODATAL144 (CAN_MO144_DATAL)
+
+/** \brief 2200, Message Object Function Control Register */
+#define CAN_MO144_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A200u)
+
+/** Alias (User Manual Name) for CAN_MO144_EDATA0.
+* To use register names with standard convension, please use CAN_MO144_EDATA0.
+*/
+#define CAN_EMO144DATA0 (CAN_MO144_EDATA0)
+
+/** \brief 2204, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO144_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A204u)
+
+/** Alias (User Manual Name) for CAN_MO144_EDATA1.
+* To use register names with standard convension, please use CAN_MO144_EDATA1.
+*/
+#define CAN_EMO144DATA1 (CAN_MO144_EDATA1)
+
+/** \brief 2208, Message Object Interrupt Pointer Register */
+#define CAN_MO144_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A208u)
+
+/** Alias (User Manual Name) for CAN_MO144_EDATA2.
+* To use register names with standard convension, please use CAN_MO144_EDATA2.
+*/
+#define CAN_EMO144DATA2 (CAN_MO144_EDATA2)
+
+/** \brief 220C, Message Object Acceptance Mask Register */
+#define CAN_MO144_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A20Cu)
+
+/** Alias (User Manual Name) for CAN_MO144_EDATA3.
+* To use register names with standard convension, please use CAN_MO144_EDATA3.
+*/
+#define CAN_EMO144DATA3 (CAN_MO144_EDATA3)
+
+/** \brief 2210, Message Object Data Register Low */
+#define CAN_MO144_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A210u)
+
+/** Alias (User Manual Name) for CAN_MO144_EDATA4.
+* To use register names with standard convension, please use CAN_MO144_EDATA4.
+*/
+#define CAN_EMO144DATA4 (CAN_MO144_EDATA4)
+
+/** \brief 2214, Message Object Data Register High */
+#define CAN_MO144_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A214u)
+
+/** Alias (User Manual Name) for CAN_MO144_EDATA5.
+* To use register names with standard convension, please use CAN_MO144_EDATA5.
+*/
+#define CAN_EMO144DATA5 (CAN_MO144_EDATA5)
+
+/** \brief 2218, Message Object Arbitration Register */
+#define CAN_MO144_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A218u)
+
+/** Alias (User Manual Name) for CAN_MO144_EDATA6.
+* To use register names with standard convension, please use CAN_MO144_EDATA6.
+*/
+#define CAN_EMO144DATA6 (CAN_MO144_EDATA6)
+
+/** \brief 2200, Message Object Function Control Register */
+#define CAN_MO144_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A200u)
+
+/** Alias (User Manual Name) for CAN_MO144_FCR.
+* To use register names with standard convension, please use CAN_MO144_FCR.
+*/
+#define CAN_MOFCR144 (CAN_MO144_FCR)
+
+/** \brief 2204, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO144_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A204u)
+
+/** Alias (User Manual Name) for CAN_MO144_FGPR.
+* To use register names with standard convension, please use CAN_MO144_FGPR.
+*/
+#define CAN_MOFGPR144 (CAN_MO144_FGPR)
+
+/** \brief 2208, Message Object Interrupt Pointer Register */
+#define CAN_MO144_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A208u)
+
+/** Alias (User Manual Name) for CAN_MO144_IPR.
+* To use register names with standard convension, please use CAN_MO144_IPR.
+*/
+#define CAN_MOIPR144 (CAN_MO144_IPR)
+
+/** \brief 221C, Message Object Control Register */
+#define CAN_MO144_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A21Cu)
+
+/** Alias (User Manual Name) for CAN_MO144_STAT.
+* To use register names with standard convension, please use CAN_MO144_STAT.
+*/
+#define CAN_MOSTAT144 (CAN_MO144_STAT)
+
+/** \brief 222C, Message Object Acceptance Mask Register */
+#define CAN_MO145_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A22Cu)
+
+/** Alias (User Manual Name) for CAN_MO145_AMR.
+* To use register names with standard convension, please use CAN_MO145_AMR.
+*/
+#define CAN_MOAMR145 (CAN_MO145_AMR)
+
+/** \brief 2238, Message Object Arbitration Register */
+#define CAN_MO145_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A238u)
+
+/** Alias (User Manual Name) for CAN_MO145_AR.
+* To use register names with standard convension, please use CAN_MO145_AR.
+*/
+#define CAN_MOAR145 (CAN_MO145_AR)
+
+/** \brief 223C, Message Object Control Register */
+#define CAN_MO145_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A23Cu)
+
+/** Alias (User Manual Name) for CAN_MO145_CTR.
+* To use register names with standard convension, please use CAN_MO145_CTR.
+*/
+#define CAN_MOCTR145 (CAN_MO145_CTR)
+
+/** \brief 2234, Message Object Data Register High */
+#define CAN_MO145_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A234u)
+
+/** Alias (User Manual Name) for CAN_MO145_DATAH.
+* To use register names with standard convension, please use CAN_MO145_DATAH.
+*/
+#define CAN_MODATAH145 (CAN_MO145_DATAH)
+
+/** \brief 2230, Message Object Data Register Low */
+#define CAN_MO145_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A230u)
+
+/** Alias (User Manual Name) for CAN_MO145_DATAL.
+* To use register names with standard convension, please use CAN_MO145_DATAL.
+*/
+#define CAN_MODATAL145 (CAN_MO145_DATAL)
+
+/** \brief 2220, Message Object Function Control Register */
+#define CAN_MO145_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A220u)
+
+/** Alias (User Manual Name) for CAN_MO145_EDATA0.
+* To use register names with standard convension, please use CAN_MO145_EDATA0.
+*/
+#define CAN_EMO145DATA0 (CAN_MO145_EDATA0)
+
+/** \brief 2224, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO145_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A224u)
+
+/** Alias (User Manual Name) for CAN_MO145_EDATA1.
+* To use register names with standard convension, please use CAN_MO145_EDATA1.
+*/
+#define CAN_EMO145DATA1 (CAN_MO145_EDATA1)
+
+/** \brief 2228, Message Object Interrupt Pointer Register */
+#define CAN_MO145_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A228u)
+
+/** Alias (User Manual Name) for CAN_MO145_EDATA2.
+* To use register names with standard convension, please use CAN_MO145_EDATA2.
+*/
+#define CAN_EMO145DATA2 (CAN_MO145_EDATA2)
+
+/** \brief 222C, Message Object Acceptance Mask Register */
+#define CAN_MO145_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A22Cu)
+
+/** Alias (User Manual Name) for CAN_MO145_EDATA3.
+* To use register names with standard convension, please use CAN_MO145_EDATA3.
+*/
+#define CAN_EMO145DATA3 (CAN_MO145_EDATA3)
+
+/** \brief 2230, Message Object Data Register Low */
+#define CAN_MO145_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A230u)
+
+/** Alias (User Manual Name) for CAN_MO145_EDATA4.
+* To use register names with standard convension, please use CAN_MO145_EDATA4.
+*/
+#define CAN_EMO145DATA4 (CAN_MO145_EDATA4)
+
+/** \brief 2234, Message Object Data Register High */
+#define CAN_MO145_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A234u)
+
+/** Alias (User Manual Name) for CAN_MO145_EDATA5.
+* To use register names with standard convension, please use CAN_MO145_EDATA5.
+*/
+#define CAN_EMO145DATA5 (CAN_MO145_EDATA5)
+
+/** \brief 2238, Message Object Arbitration Register */
+#define CAN_MO145_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A238u)
+
+/** Alias (User Manual Name) for CAN_MO145_EDATA6.
+* To use register names with standard convension, please use CAN_MO145_EDATA6.
+*/
+#define CAN_EMO145DATA6 (CAN_MO145_EDATA6)
+
+/** \brief 2220, Message Object Function Control Register */
+#define CAN_MO145_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A220u)
+
+/** Alias (User Manual Name) for CAN_MO145_FCR.
+* To use register names with standard convension, please use CAN_MO145_FCR.
+*/
+#define CAN_MOFCR145 (CAN_MO145_FCR)
+
+/** \brief 2224, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO145_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A224u)
+
+/** Alias (User Manual Name) for CAN_MO145_FGPR.
+* To use register names with standard convension, please use CAN_MO145_FGPR.
+*/
+#define CAN_MOFGPR145 (CAN_MO145_FGPR)
+
+/** \brief 2228, Message Object Interrupt Pointer Register */
+#define CAN_MO145_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A228u)
+
+/** Alias (User Manual Name) for CAN_MO145_IPR.
+* To use register names with standard convension, please use CAN_MO145_IPR.
+*/
+#define CAN_MOIPR145 (CAN_MO145_IPR)
+
+/** \brief 223C, Message Object Control Register */
+#define CAN_MO145_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A23Cu)
+
+/** Alias (User Manual Name) for CAN_MO145_STAT.
+* To use register names with standard convension, please use CAN_MO145_STAT.
+*/
+#define CAN_MOSTAT145 (CAN_MO145_STAT)
+
+/** \brief 224C, Message Object Acceptance Mask Register */
+#define CAN_MO146_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A24Cu)
+
+/** Alias (User Manual Name) for CAN_MO146_AMR.
+* To use register names with standard convension, please use CAN_MO146_AMR.
+*/
+#define CAN_MOAMR146 (CAN_MO146_AMR)
+
+/** \brief 2258, Message Object Arbitration Register */
+#define CAN_MO146_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A258u)
+
+/** Alias (User Manual Name) for CAN_MO146_AR.
+* To use register names with standard convension, please use CAN_MO146_AR.
+*/
+#define CAN_MOAR146 (CAN_MO146_AR)
+
+/** \brief 225C, Message Object Control Register */
+#define CAN_MO146_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A25Cu)
+
+/** Alias (User Manual Name) for CAN_MO146_CTR.
+* To use register names with standard convension, please use CAN_MO146_CTR.
+*/
+#define CAN_MOCTR146 (CAN_MO146_CTR)
+
+/** \brief 2254, Message Object Data Register High */
+#define CAN_MO146_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A254u)
+
+/** Alias (User Manual Name) for CAN_MO146_DATAH.
+* To use register names with standard convension, please use CAN_MO146_DATAH.
+*/
+#define CAN_MODATAH146 (CAN_MO146_DATAH)
+
+/** \brief 2250, Message Object Data Register Low */
+#define CAN_MO146_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A250u)
+
+/** Alias (User Manual Name) for CAN_MO146_DATAL.
+* To use register names with standard convension, please use CAN_MO146_DATAL.
+*/
+#define CAN_MODATAL146 (CAN_MO146_DATAL)
+
+/** \brief 2240, Message Object Function Control Register */
+#define CAN_MO146_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A240u)
+
+/** Alias (User Manual Name) for CAN_MO146_EDATA0.
+* To use register names with standard convension, please use CAN_MO146_EDATA0.
+*/
+#define CAN_EMO146DATA0 (CAN_MO146_EDATA0)
+
+/** \brief 2244, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO146_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A244u)
+
+/** Alias (User Manual Name) for CAN_MO146_EDATA1.
+* To use register names with standard convension, please use CAN_MO146_EDATA1.
+*/
+#define CAN_EMO146DATA1 (CAN_MO146_EDATA1)
+
+/** \brief 2248, Message Object Interrupt Pointer Register */
+#define CAN_MO146_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A248u)
+
+/** Alias (User Manual Name) for CAN_MO146_EDATA2.
+* To use register names with standard convension, please use CAN_MO146_EDATA2.
+*/
+#define CAN_EMO146DATA2 (CAN_MO146_EDATA2)
+
+/** \brief 224C, Message Object Acceptance Mask Register */
+#define CAN_MO146_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A24Cu)
+
+/** Alias (User Manual Name) for CAN_MO146_EDATA3.
+* To use register names with standard convension, please use CAN_MO146_EDATA3.
+*/
+#define CAN_EMO146DATA3 (CAN_MO146_EDATA3)
+
+/** \brief 2250, Message Object Data Register Low */
+#define CAN_MO146_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A250u)
+
+/** Alias (User Manual Name) for CAN_MO146_EDATA4.
+* To use register names with standard convension, please use CAN_MO146_EDATA4.
+*/
+#define CAN_EMO146DATA4 (CAN_MO146_EDATA4)
+
+/** \brief 2254, Message Object Data Register High */
+#define CAN_MO146_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A254u)
+
+/** Alias (User Manual Name) for CAN_MO146_EDATA5.
+* To use register names with standard convension, please use CAN_MO146_EDATA5.
+*/
+#define CAN_EMO146DATA5 (CAN_MO146_EDATA5)
+
+/** \brief 2258, Message Object Arbitration Register */
+#define CAN_MO146_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A258u)
+
+/** Alias (User Manual Name) for CAN_MO146_EDATA6.
+* To use register names with standard convension, please use CAN_MO146_EDATA6.
+*/
+#define CAN_EMO146DATA6 (CAN_MO146_EDATA6)
+
+/** \brief 2240, Message Object Function Control Register */
+#define CAN_MO146_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A240u)
+
+/** Alias (User Manual Name) for CAN_MO146_FCR.
+* To use register names with standard convension, please use CAN_MO146_FCR.
+*/
+#define CAN_MOFCR146 (CAN_MO146_FCR)
+
+/** \brief 2244, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO146_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A244u)
+
+/** Alias (User Manual Name) for CAN_MO146_FGPR.
+* To use register names with standard convension, please use CAN_MO146_FGPR.
+*/
+#define CAN_MOFGPR146 (CAN_MO146_FGPR)
+
+/** \brief 2248, Message Object Interrupt Pointer Register */
+#define CAN_MO146_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A248u)
+
+/** Alias (User Manual Name) for CAN_MO146_IPR.
+* To use register names with standard convension, please use CAN_MO146_IPR.
+*/
+#define CAN_MOIPR146 (CAN_MO146_IPR)
+
+/** \brief 225C, Message Object Control Register */
+#define CAN_MO146_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A25Cu)
+
+/** Alias (User Manual Name) for CAN_MO146_STAT.
+* To use register names with standard convension, please use CAN_MO146_STAT.
+*/
+#define CAN_MOSTAT146 (CAN_MO146_STAT)
+
+/** \brief 226C, Message Object Acceptance Mask Register */
+#define CAN_MO147_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A26Cu)
+
+/** Alias (User Manual Name) for CAN_MO147_AMR.
+* To use register names with standard convension, please use CAN_MO147_AMR.
+*/
+#define CAN_MOAMR147 (CAN_MO147_AMR)
+
+/** \brief 2278, Message Object Arbitration Register */
+#define CAN_MO147_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A278u)
+
+/** Alias (User Manual Name) for CAN_MO147_AR.
+* To use register names with standard convension, please use CAN_MO147_AR.
+*/
+#define CAN_MOAR147 (CAN_MO147_AR)
+
+/** \brief 227C, Message Object Control Register */
+#define CAN_MO147_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A27Cu)
+
+/** Alias (User Manual Name) for CAN_MO147_CTR.
+* To use register names with standard convension, please use CAN_MO147_CTR.
+*/
+#define CAN_MOCTR147 (CAN_MO147_CTR)
+
+/** \brief 2274, Message Object Data Register High */
+#define CAN_MO147_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A274u)
+
+/** Alias (User Manual Name) for CAN_MO147_DATAH.
+* To use register names with standard convension, please use CAN_MO147_DATAH.
+*/
+#define CAN_MODATAH147 (CAN_MO147_DATAH)
+
+/** \brief 2270, Message Object Data Register Low */
+#define CAN_MO147_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A270u)
+
+/** Alias (User Manual Name) for CAN_MO147_DATAL.
+* To use register names with standard convension, please use CAN_MO147_DATAL.
+*/
+#define CAN_MODATAL147 (CAN_MO147_DATAL)
+
+/** \brief 2260, Message Object Function Control Register */
+#define CAN_MO147_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A260u)
+
+/** Alias (User Manual Name) for CAN_MO147_EDATA0.
+* To use register names with standard convension, please use CAN_MO147_EDATA0.
+*/
+#define CAN_EMO147DATA0 (CAN_MO147_EDATA0)
+
+/** \brief 2264, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO147_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A264u)
+
+/** Alias (User Manual Name) for CAN_MO147_EDATA1.
+* To use register names with standard convension, please use CAN_MO147_EDATA1.
+*/
+#define CAN_EMO147DATA1 (CAN_MO147_EDATA1)
+
+/** \brief 2268, Message Object Interrupt Pointer Register */
+#define CAN_MO147_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A268u)
+
+/** Alias (User Manual Name) for CAN_MO147_EDATA2.
+* To use register names with standard convension, please use CAN_MO147_EDATA2.
+*/
+#define CAN_EMO147DATA2 (CAN_MO147_EDATA2)
+
+/** \brief 226C, Message Object Acceptance Mask Register */
+#define CAN_MO147_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A26Cu)
+
+/** Alias (User Manual Name) for CAN_MO147_EDATA3.
+* To use register names with standard convension, please use CAN_MO147_EDATA3.
+*/
+#define CAN_EMO147DATA3 (CAN_MO147_EDATA3)
+
+/** \brief 2270, Message Object Data Register Low */
+#define CAN_MO147_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A270u)
+
+/** Alias (User Manual Name) for CAN_MO147_EDATA4.
+* To use register names with standard convension, please use CAN_MO147_EDATA4.
+*/
+#define CAN_EMO147DATA4 (CAN_MO147_EDATA4)
+
+/** \brief 2274, Message Object Data Register High */
+#define CAN_MO147_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A274u)
+
+/** Alias (User Manual Name) for CAN_MO147_EDATA5.
+* To use register names with standard convension, please use CAN_MO147_EDATA5.
+*/
+#define CAN_EMO147DATA5 (CAN_MO147_EDATA5)
+
+/** \brief 2278, Message Object Arbitration Register */
+#define CAN_MO147_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A278u)
+
+/** Alias (User Manual Name) for CAN_MO147_EDATA6.
+* To use register names with standard convension, please use CAN_MO147_EDATA6.
+*/
+#define CAN_EMO147DATA6 (CAN_MO147_EDATA6)
+
+/** \brief 2260, Message Object Function Control Register */
+#define CAN_MO147_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A260u)
+
+/** Alias (User Manual Name) for CAN_MO147_FCR.
+* To use register names with standard convension, please use CAN_MO147_FCR.
+*/
+#define CAN_MOFCR147 (CAN_MO147_FCR)
+
+/** \brief 2264, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO147_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A264u)
+
+/** Alias (User Manual Name) for CAN_MO147_FGPR.
+* To use register names with standard convension, please use CAN_MO147_FGPR.
+*/
+#define CAN_MOFGPR147 (CAN_MO147_FGPR)
+
+/** \brief 2268, Message Object Interrupt Pointer Register */
+#define CAN_MO147_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A268u)
+
+/** Alias (User Manual Name) for CAN_MO147_IPR.
+* To use register names with standard convension, please use CAN_MO147_IPR.
+*/
+#define CAN_MOIPR147 (CAN_MO147_IPR)
+
+/** \brief 227C, Message Object Control Register */
+#define CAN_MO147_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A27Cu)
+
+/** Alias (User Manual Name) for CAN_MO147_STAT.
+* To use register names with standard convension, please use CAN_MO147_STAT.
+*/
+#define CAN_MOSTAT147 (CAN_MO147_STAT)
+
+/** \brief 228C, Message Object Acceptance Mask Register */
+#define CAN_MO148_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A28Cu)
+
+/** Alias (User Manual Name) for CAN_MO148_AMR.
+* To use register names with standard convension, please use CAN_MO148_AMR.
+*/
+#define CAN_MOAMR148 (CAN_MO148_AMR)
+
+/** \brief 2298, Message Object Arbitration Register */
+#define CAN_MO148_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A298u)
+
+/** Alias (User Manual Name) for CAN_MO148_AR.
+* To use register names with standard convension, please use CAN_MO148_AR.
+*/
+#define CAN_MOAR148 (CAN_MO148_AR)
+
+/** \brief 229C, Message Object Control Register */
+#define CAN_MO148_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A29Cu)
+
+/** Alias (User Manual Name) for CAN_MO148_CTR.
+* To use register names with standard convension, please use CAN_MO148_CTR.
+*/
+#define CAN_MOCTR148 (CAN_MO148_CTR)
+
+/** \brief 2294, Message Object Data Register High */
+#define CAN_MO148_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A294u)
+
+/** Alias (User Manual Name) for CAN_MO148_DATAH.
+* To use register names with standard convension, please use CAN_MO148_DATAH.
+*/
+#define CAN_MODATAH148 (CAN_MO148_DATAH)
+
+/** \brief 2290, Message Object Data Register Low */
+#define CAN_MO148_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A290u)
+
+/** Alias (User Manual Name) for CAN_MO148_DATAL.
+* To use register names with standard convension, please use CAN_MO148_DATAL.
+*/
+#define CAN_MODATAL148 (CAN_MO148_DATAL)
+
+/** \brief 2280, Message Object Function Control Register */
+#define CAN_MO148_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A280u)
+
+/** Alias (User Manual Name) for CAN_MO148_EDATA0.
+* To use register names with standard convension, please use CAN_MO148_EDATA0.
+*/
+#define CAN_EMO148DATA0 (CAN_MO148_EDATA0)
+
+/** \brief 2284, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO148_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A284u)
+
+/** Alias (User Manual Name) for CAN_MO148_EDATA1.
+* To use register names with standard convension, please use CAN_MO148_EDATA1.
+*/
+#define CAN_EMO148DATA1 (CAN_MO148_EDATA1)
+
+/** \brief 2288, Message Object Interrupt Pointer Register */
+#define CAN_MO148_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A288u)
+
+/** Alias (User Manual Name) for CAN_MO148_EDATA2.
+* To use register names with standard convension, please use CAN_MO148_EDATA2.
+*/
+#define CAN_EMO148DATA2 (CAN_MO148_EDATA2)
+
+/** \brief 228C, Message Object Acceptance Mask Register */
+#define CAN_MO148_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A28Cu)
+
+/** Alias (User Manual Name) for CAN_MO148_EDATA3.
+* To use register names with standard convension, please use CAN_MO148_EDATA3.
+*/
+#define CAN_EMO148DATA3 (CAN_MO148_EDATA3)
+
+/** \brief 2290, Message Object Data Register Low */
+#define CAN_MO148_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A290u)
+
+/** Alias (User Manual Name) for CAN_MO148_EDATA4.
+* To use register names with standard convension, please use CAN_MO148_EDATA4.
+*/
+#define CAN_EMO148DATA4 (CAN_MO148_EDATA4)
+
+/** \brief 2294, Message Object Data Register High */
+#define CAN_MO148_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A294u)
+
+/** Alias (User Manual Name) for CAN_MO148_EDATA5.
+* To use register names with standard convension, please use CAN_MO148_EDATA5.
+*/
+#define CAN_EMO148DATA5 (CAN_MO148_EDATA5)
+
+/** \brief 2298, Message Object Arbitration Register */
+#define CAN_MO148_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A298u)
+
+/** Alias (User Manual Name) for CAN_MO148_EDATA6.
+* To use register names with standard convension, please use CAN_MO148_EDATA6.
+*/
+#define CAN_EMO148DATA6 (CAN_MO148_EDATA6)
+
+/** \brief 2280, Message Object Function Control Register */
+#define CAN_MO148_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A280u)
+
+/** Alias (User Manual Name) for CAN_MO148_FCR.
+* To use register names with standard convension, please use CAN_MO148_FCR.
+*/
+#define CAN_MOFCR148 (CAN_MO148_FCR)
+
+/** \brief 2284, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO148_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A284u)
+
+/** Alias (User Manual Name) for CAN_MO148_FGPR.
+* To use register names with standard convension, please use CAN_MO148_FGPR.
+*/
+#define CAN_MOFGPR148 (CAN_MO148_FGPR)
+
+/** \brief 2288, Message Object Interrupt Pointer Register */
+#define CAN_MO148_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A288u)
+
+/** Alias (User Manual Name) for CAN_MO148_IPR.
+* To use register names with standard convension, please use CAN_MO148_IPR.
+*/
+#define CAN_MOIPR148 (CAN_MO148_IPR)
+
+/** \brief 229C, Message Object Control Register */
+#define CAN_MO148_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A29Cu)
+
+/** Alias (User Manual Name) for CAN_MO148_STAT.
+* To use register names with standard convension, please use CAN_MO148_STAT.
+*/
+#define CAN_MOSTAT148 (CAN_MO148_STAT)
+
+/** \brief 22AC, Message Object Acceptance Mask Register */
+#define CAN_MO149_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A2ACu)
+
+/** Alias (User Manual Name) for CAN_MO149_AMR.
+* To use register names with standard convension, please use CAN_MO149_AMR.
+*/
+#define CAN_MOAMR149 (CAN_MO149_AMR)
+
+/** \brief 22B8, Message Object Arbitration Register */
+#define CAN_MO149_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A2B8u)
+
+/** Alias (User Manual Name) for CAN_MO149_AR.
+* To use register names with standard convension, please use CAN_MO149_AR.
+*/
+#define CAN_MOAR149 (CAN_MO149_AR)
+
+/** \brief 22BC, Message Object Control Register */
+#define CAN_MO149_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A2BCu)
+
+/** Alias (User Manual Name) for CAN_MO149_CTR.
+* To use register names with standard convension, please use CAN_MO149_CTR.
+*/
+#define CAN_MOCTR149 (CAN_MO149_CTR)
+
+/** \brief 22B4, Message Object Data Register High */
+#define CAN_MO149_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A2B4u)
+
+/** Alias (User Manual Name) for CAN_MO149_DATAH.
+* To use register names with standard convension, please use CAN_MO149_DATAH.
+*/
+#define CAN_MODATAH149 (CAN_MO149_DATAH)
+
+/** \brief 22B0, Message Object Data Register Low */
+#define CAN_MO149_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A2B0u)
+
+/** Alias (User Manual Name) for CAN_MO149_DATAL.
+* To use register names with standard convension, please use CAN_MO149_DATAL.
+*/
+#define CAN_MODATAL149 (CAN_MO149_DATAL)
+
+/** \brief 22A0, Message Object Function Control Register */
+#define CAN_MO149_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A2A0u)
+
+/** Alias (User Manual Name) for CAN_MO149_EDATA0.
+* To use register names with standard convension, please use CAN_MO149_EDATA0.
+*/
+#define CAN_EMO149DATA0 (CAN_MO149_EDATA0)
+
+/** \brief 22A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO149_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A2A4u)
+
+/** Alias (User Manual Name) for CAN_MO149_EDATA1.
+* To use register names with standard convension, please use CAN_MO149_EDATA1.
+*/
+#define CAN_EMO149DATA1 (CAN_MO149_EDATA1)
+
+/** \brief 22A8, Message Object Interrupt Pointer Register */
+#define CAN_MO149_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A2A8u)
+
+/** Alias (User Manual Name) for CAN_MO149_EDATA2.
+* To use register names with standard convension, please use CAN_MO149_EDATA2.
+*/
+#define CAN_EMO149DATA2 (CAN_MO149_EDATA2)
+
+/** \brief 22AC, Message Object Acceptance Mask Register */
+#define CAN_MO149_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A2ACu)
+
+/** Alias (User Manual Name) for CAN_MO149_EDATA3.
+* To use register names with standard convension, please use CAN_MO149_EDATA3.
+*/
+#define CAN_EMO149DATA3 (CAN_MO149_EDATA3)
+
+/** \brief 22B0, Message Object Data Register Low */
+#define CAN_MO149_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A2B0u)
+
+/** Alias (User Manual Name) for CAN_MO149_EDATA4.
+* To use register names with standard convension, please use CAN_MO149_EDATA4.
+*/
+#define CAN_EMO149DATA4 (CAN_MO149_EDATA4)
+
+/** \brief 22B4, Message Object Data Register High */
+#define CAN_MO149_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A2B4u)
+
+/** Alias (User Manual Name) for CAN_MO149_EDATA5.
+* To use register names with standard convension, please use CAN_MO149_EDATA5.
+*/
+#define CAN_EMO149DATA5 (CAN_MO149_EDATA5)
+
+/** \brief 22B8, Message Object Arbitration Register */
+#define CAN_MO149_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A2B8u)
+
+/** Alias (User Manual Name) for CAN_MO149_EDATA6.
+* To use register names with standard convension, please use CAN_MO149_EDATA6.
+*/
+#define CAN_EMO149DATA6 (CAN_MO149_EDATA6)
+
+/** \brief 22A0, Message Object Function Control Register */
+#define CAN_MO149_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A2A0u)
+
+/** Alias (User Manual Name) for CAN_MO149_FCR.
+* To use register names with standard convension, please use CAN_MO149_FCR.
+*/
+#define CAN_MOFCR149 (CAN_MO149_FCR)
+
+/** \brief 22A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO149_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A2A4u)
+
+/** Alias (User Manual Name) for CAN_MO149_FGPR.
+* To use register names with standard convension, please use CAN_MO149_FGPR.
+*/
+#define CAN_MOFGPR149 (CAN_MO149_FGPR)
+
+/** \brief 22A8, Message Object Interrupt Pointer Register */
+#define CAN_MO149_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A2A8u)
+
+/** Alias (User Manual Name) for CAN_MO149_IPR.
+* To use register names with standard convension, please use CAN_MO149_IPR.
+*/
+#define CAN_MOIPR149 (CAN_MO149_IPR)
+
+/** \brief 22BC, Message Object Control Register */
+#define CAN_MO149_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A2BCu)
+
+/** Alias (User Manual Name) for CAN_MO149_STAT.
+* To use register names with standard convension, please use CAN_MO149_STAT.
+*/
+#define CAN_MOSTAT149 (CAN_MO149_STAT)
+
+/** \brief 11CC, Message Object Acceptance Mask Register */
+#define CAN_MO14_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00191CCu)
+
+/** Alias (User Manual Name) for CAN_MO14_AMR.
+* To use register names with standard convension, please use CAN_MO14_AMR.
+*/
+#define CAN_MOAMR14 (CAN_MO14_AMR)
+
+/** \brief 11D8, Message Object Arbitration Register */
+#define CAN_MO14_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00191D8u)
+
+/** Alias (User Manual Name) for CAN_MO14_AR.
+* To use register names with standard convension, please use CAN_MO14_AR.
+*/
+#define CAN_MOAR14 (CAN_MO14_AR)
+
+/** \brief 11DC, Message Object Control Register */
+#define CAN_MO14_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00191DCu)
+
+/** Alias (User Manual Name) for CAN_MO14_CTR.
+* To use register names with standard convension, please use CAN_MO14_CTR.
+*/
+#define CAN_MOCTR14 (CAN_MO14_CTR)
+
+/** \brief 11D4, Message Object Data Register High */
+#define CAN_MO14_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00191D4u)
+
+/** Alias (User Manual Name) for CAN_MO14_DATAH.
+* To use register names with standard convension, please use CAN_MO14_DATAH.
+*/
+#define CAN_MODATAH14 (CAN_MO14_DATAH)
+
+/** \brief 11D0, Message Object Data Register Low */
+#define CAN_MO14_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00191D0u)
+
+/** Alias (User Manual Name) for CAN_MO14_DATAL.
+* To use register names with standard convension, please use CAN_MO14_DATAL.
+*/
+#define CAN_MODATAL14 (CAN_MO14_DATAL)
+
+/** \brief 11C0, Message Object Function Control Register */
+#define CAN_MO14_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00191C0u)
+
+/** Alias (User Manual Name) for CAN_MO14_EDATA0.
+* To use register names with standard convension, please use CAN_MO14_EDATA0.
+*/
+#define CAN_EMO14DATA0 (CAN_MO14_EDATA0)
+
+/** \brief 11C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO14_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00191C4u)
+
+/** Alias (User Manual Name) for CAN_MO14_EDATA1.
+* To use register names with standard convension, please use CAN_MO14_EDATA1.
+*/
+#define CAN_EMO14DATA1 (CAN_MO14_EDATA1)
+
+/** \brief 11C8, Message Object Interrupt Pointer Register */
+#define CAN_MO14_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00191C8u)
+
+/** Alias (User Manual Name) for CAN_MO14_EDATA2.
+* To use register names with standard convension, please use CAN_MO14_EDATA2.
+*/
+#define CAN_EMO14DATA2 (CAN_MO14_EDATA2)
+
+/** \brief 11CC, Message Object Acceptance Mask Register */
+#define CAN_MO14_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00191CCu)
+
+/** Alias (User Manual Name) for CAN_MO14_EDATA3.
+* To use register names with standard convension, please use CAN_MO14_EDATA3.
+*/
+#define CAN_EMO14DATA3 (CAN_MO14_EDATA3)
+
+/** \brief 11D0, Message Object Data Register Low */
+#define CAN_MO14_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00191D0u)
+
+/** Alias (User Manual Name) for CAN_MO14_EDATA4.
+* To use register names with standard convension, please use CAN_MO14_EDATA4.
+*/
+#define CAN_EMO14DATA4 (CAN_MO14_EDATA4)
+
+/** \brief 11D4, Message Object Data Register High */
+#define CAN_MO14_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00191D4u)
+
+/** Alias (User Manual Name) for CAN_MO14_EDATA5.
+* To use register names with standard convension, please use CAN_MO14_EDATA5.
+*/
+#define CAN_EMO14DATA5 (CAN_MO14_EDATA5)
+
+/** \brief 11D8, Message Object Arbitration Register */
+#define CAN_MO14_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00191D8u)
+
+/** Alias (User Manual Name) for CAN_MO14_EDATA6.
+* To use register names with standard convension, please use CAN_MO14_EDATA6.
+*/
+#define CAN_EMO14DATA6 (CAN_MO14_EDATA6)
+
+/** \brief 11C0, Message Object Function Control Register */
+#define CAN_MO14_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00191C0u)
+
+/** Alias (User Manual Name) for CAN_MO14_FCR.
+* To use register names with standard convension, please use CAN_MO14_FCR.
+*/
+#define CAN_MOFCR14 (CAN_MO14_FCR)
+
+/** \brief 11C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO14_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00191C4u)
+
+/** Alias (User Manual Name) for CAN_MO14_FGPR.
+* To use register names with standard convension, please use CAN_MO14_FGPR.
+*/
+#define CAN_MOFGPR14 (CAN_MO14_FGPR)
+
+/** \brief 11C8, Message Object Interrupt Pointer Register */
+#define CAN_MO14_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00191C8u)
+
+/** Alias (User Manual Name) for CAN_MO14_IPR.
+* To use register names with standard convension, please use CAN_MO14_IPR.
+*/
+#define CAN_MOIPR14 (CAN_MO14_IPR)
+
+/** \brief 11DC, Message Object Control Register */
+#define CAN_MO14_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00191DCu)
+
+/** Alias (User Manual Name) for CAN_MO14_STAT.
+* To use register names with standard convension, please use CAN_MO14_STAT.
+*/
+#define CAN_MOSTAT14 (CAN_MO14_STAT)
+
+/** \brief 22CC, Message Object Acceptance Mask Register */
+#define CAN_MO150_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A2CCu)
+
+/** Alias (User Manual Name) for CAN_MO150_AMR.
+* To use register names with standard convension, please use CAN_MO150_AMR.
+*/
+#define CAN_MOAMR150 (CAN_MO150_AMR)
+
+/** \brief 22D8, Message Object Arbitration Register */
+#define CAN_MO150_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A2D8u)
+
+/** Alias (User Manual Name) for CAN_MO150_AR.
+* To use register names with standard convension, please use CAN_MO150_AR.
+*/
+#define CAN_MOAR150 (CAN_MO150_AR)
+
+/** \brief 22DC, Message Object Control Register */
+#define CAN_MO150_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A2DCu)
+
+/** Alias (User Manual Name) for CAN_MO150_CTR.
+* To use register names with standard convension, please use CAN_MO150_CTR.
+*/
+#define CAN_MOCTR150 (CAN_MO150_CTR)
+
+/** \brief 22D4, Message Object Data Register High */
+#define CAN_MO150_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A2D4u)
+
+/** Alias (User Manual Name) for CAN_MO150_DATAH.
+* To use register names with standard convension, please use CAN_MO150_DATAH.
+*/
+#define CAN_MODATAH150 (CAN_MO150_DATAH)
+
+/** \brief 22D0, Message Object Data Register Low */
+#define CAN_MO150_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A2D0u)
+
+/** Alias (User Manual Name) for CAN_MO150_DATAL.
+* To use register names with standard convension, please use CAN_MO150_DATAL.
+*/
+#define CAN_MODATAL150 (CAN_MO150_DATAL)
+
+/** \brief 22C0, Message Object Function Control Register */
+#define CAN_MO150_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A2C0u)
+
+/** Alias (User Manual Name) for CAN_MO150_EDATA0.
+* To use register names with standard convension, please use CAN_MO150_EDATA0.
+*/
+#define CAN_EMO150DATA0 (CAN_MO150_EDATA0)
+
+/** \brief 22C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO150_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A2C4u)
+
+/** Alias (User Manual Name) for CAN_MO150_EDATA1.
+* To use register names with standard convension, please use CAN_MO150_EDATA1.
+*/
+#define CAN_EMO150DATA1 (CAN_MO150_EDATA1)
+
+/** \brief 22C8, Message Object Interrupt Pointer Register */
+#define CAN_MO150_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A2C8u)
+
+/** Alias (User Manual Name) for CAN_MO150_EDATA2.
+* To use register names with standard convension, please use CAN_MO150_EDATA2.
+*/
+#define CAN_EMO150DATA2 (CAN_MO150_EDATA2)
+
+/** \brief 22CC, Message Object Acceptance Mask Register */
+#define CAN_MO150_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A2CCu)
+
+/** Alias (User Manual Name) for CAN_MO150_EDATA3.
+* To use register names with standard convension, please use CAN_MO150_EDATA3.
+*/
+#define CAN_EMO150DATA3 (CAN_MO150_EDATA3)
+
+/** \brief 22D0, Message Object Data Register Low */
+#define CAN_MO150_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A2D0u)
+
+/** Alias (User Manual Name) for CAN_MO150_EDATA4.
+* To use register names with standard convension, please use CAN_MO150_EDATA4.
+*/
+#define CAN_EMO150DATA4 (CAN_MO150_EDATA4)
+
+/** \brief 22D4, Message Object Data Register High */
+#define CAN_MO150_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A2D4u)
+
+/** Alias (User Manual Name) for CAN_MO150_EDATA5.
+* To use register names with standard convension, please use CAN_MO150_EDATA5.
+*/
+#define CAN_EMO150DATA5 (CAN_MO150_EDATA5)
+
+/** \brief 22D8, Message Object Arbitration Register */
+#define CAN_MO150_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A2D8u)
+
+/** Alias (User Manual Name) for CAN_MO150_EDATA6.
+* To use register names with standard convension, please use CAN_MO150_EDATA6.
+*/
+#define CAN_EMO150DATA6 (CAN_MO150_EDATA6)
+
+/** \brief 22C0, Message Object Function Control Register */
+#define CAN_MO150_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A2C0u)
+
+/** Alias (User Manual Name) for CAN_MO150_FCR.
+* To use register names with standard convension, please use CAN_MO150_FCR.
+*/
+#define CAN_MOFCR150 (CAN_MO150_FCR)
+
+/** \brief 22C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO150_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A2C4u)
+
+/** Alias (User Manual Name) for CAN_MO150_FGPR.
+* To use register names with standard convension, please use CAN_MO150_FGPR.
+*/
+#define CAN_MOFGPR150 (CAN_MO150_FGPR)
+
+/** \brief 22C8, Message Object Interrupt Pointer Register */
+#define CAN_MO150_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A2C8u)
+
+/** Alias (User Manual Name) for CAN_MO150_IPR.
+* To use register names with standard convension, please use CAN_MO150_IPR.
+*/
+#define CAN_MOIPR150 (CAN_MO150_IPR)
+
+/** \brief 22DC, Message Object Control Register */
+#define CAN_MO150_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A2DCu)
+
+/** Alias (User Manual Name) for CAN_MO150_STAT.
+* To use register names with standard convension, please use CAN_MO150_STAT.
+*/
+#define CAN_MOSTAT150 (CAN_MO150_STAT)
+
+/** \brief 22EC, Message Object Acceptance Mask Register */
+#define CAN_MO151_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A2ECu)
+
+/** Alias (User Manual Name) for CAN_MO151_AMR.
+* To use register names with standard convension, please use CAN_MO151_AMR.
+*/
+#define CAN_MOAMR151 (CAN_MO151_AMR)
+
+/** \brief 22F8, Message Object Arbitration Register */
+#define CAN_MO151_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A2F8u)
+
+/** Alias (User Manual Name) for CAN_MO151_AR.
+* To use register names with standard convension, please use CAN_MO151_AR.
+*/
+#define CAN_MOAR151 (CAN_MO151_AR)
+
+/** \brief 22FC, Message Object Control Register */
+#define CAN_MO151_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A2FCu)
+
+/** Alias (User Manual Name) for CAN_MO151_CTR.
+* To use register names with standard convension, please use CAN_MO151_CTR.
+*/
+#define CAN_MOCTR151 (CAN_MO151_CTR)
+
+/** \brief 22F4, Message Object Data Register High */
+#define CAN_MO151_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A2F4u)
+
+/** Alias (User Manual Name) for CAN_MO151_DATAH.
+* To use register names with standard convension, please use CAN_MO151_DATAH.
+*/
+#define CAN_MODATAH151 (CAN_MO151_DATAH)
+
+/** \brief 22F0, Message Object Data Register Low */
+#define CAN_MO151_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A2F0u)
+
+/** Alias (User Manual Name) for CAN_MO151_DATAL.
+* To use register names with standard convension, please use CAN_MO151_DATAL.
+*/
+#define CAN_MODATAL151 (CAN_MO151_DATAL)
+
+/** \brief 22E0, Message Object Function Control Register */
+#define CAN_MO151_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A2E0u)
+
+/** Alias (User Manual Name) for CAN_MO151_EDATA0.
+* To use register names with standard convension, please use CAN_MO151_EDATA0.
+*/
+#define CAN_EMO151DATA0 (CAN_MO151_EDATA0)
+
+/** \brief 22E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO151_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A2E4u)
+
+/** Alias (User Manual Name) for CAN_MO151_EDATA1.
+* To use register names with standard convension, please use CAN_MO151_EDATA1.
+*/
+#define CAN_EMO151DATA1 (CAN_MO151_EDATA1)
+
+/** \brief 22E8, Message Object Interrupt Pointer Register */
+#define CAN_MO151_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A2E8u)
+
+/** Alias (User Manual Name) for CAN_MO151_EDATA2.
+* To use register names with standard convension, please use CAN_MO151_EDATA2.
+*/
+#define CAN_EMO151DATA2 (CAN_MO151_EDATA2)
+
+/** \brief 22EC, Message Object Acceptance Mask Register */
+#define CAN_MO151_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A2ECu)
+
+/** Alias (User Manual Name) for CAN_MO151_EDATA3.
+* To use register names with standard convension, please use CAN_MO151_EDATA3.
+*/
+#define CAN_EMO151DATA3 (CAN_MO151_EDATA3)
+
+/** \brief 22F0, Message Object Data Register Low */
+#define CAN_MO151_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A2F0u)
+
+/** Alias (User Manual Name) for CAN_MO151_EDATA4.
+* To use register names with standard convension, please use CAN_MO151_EDATA4.
+*/
+#define CAN_EMO151DATA4 (CAN_MO151_EDATA4)
+
+/** \brief 22F4, Message Object Data Register High */
+#define CAN_MO151_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A2F4u)
+
+/** Alias (User Manual Name) for CAN_MO151_EDATA5.
+* To use register names with standard convension, please use CAN_MO151_EDATA5.
+*/
+#define CAN_EMO151DATA5 (CAN_MO151_EDATA5)
+
+/** \brief 22F8, Message Object Arbitration Register */
+#define CAN_MO151_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A2F8u)
+
+/** Alias (User Manual Name) for CAN_MO151_EDATA6.
+* To use register names with standard convension, please use CAN_MO151_EDATA6.
+*/
+#define CAN_EMO151DATA6 (CAN_MO151_EDATA6)
+
+/** \brief 22E0, Message Object Function Control Register */
+#define CAN_MO151_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A2E0u)
+
+/** Alias (User Manual Name) for CAN_MO151_FCR.
+* To use register names with standard convension, please use CAN_MO151_FCR.
+*/
+#define CAN_MOFCR151 (CAN_MO151_FCR)
+
+/** \brief 22E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO151_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A2E4u)
+
+/** Alias (User Manual Name) for CAN_MO151_FGPR.
+* To use register names with standard convension, please use CAN_MO151_FGPR.
+*/
+#define CAN_MOFGPR151 (CAN_MO151_FGPR)
+
+/** \brief 22E8, Message Object Interrupt Pointer Register */
+#define CAN_MO151_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A2E8u)
+
+/** Alias (User Manual Name) for CAN_MO151_IPR.
+* To use register names with standard convension, please use CAN_MO151_IPR.
+*/
+#define CAN_MOIPR151 (CAN_MO151_IPR)
+
+/** \brief 22FC, Message Object Control Register */
+#define CAN_MO151_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A2FCu)
+
+/** Alias (User Manual Name) for CAN_MO151_STAT.
+* To use register names with standard convension, please use CAN_MO151_STAT.
+*/
+#define CAN_MOSTAT151 (CAN_MO151_STAT)
+
+/** \brief 230C, Message Object Acceptance Mask Register */
+#define CAN_MO152_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A30Cu)
+
+/** Alias (User Manual Name) for CAN_MO152_AMR.
+* To use register names with standard convension, please use CAN_MO152_AMR.
+*/
+#define CAN_MOAMR152 (CAN_MO152_AMR)
+
+/** \brief 2318, Message Object Arbitration Register */
+#define CAN_MO152_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A318u)
+
+/** Alias (User Manual Name) for CAN_MO152_AR.
+* To use register names with standard convension, please use CAN_MO152_AR.
+*/
+#define CAN_MOAR152 (CAN_MO152_AR)
+
+/** \brief 231C, Message Object Control Register */
+#define CAN_MO152_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A31Cu)
+
+/** Alias (User Manual Name) for CAN_MO152_CTR.
+* To use register names with standard convension, please use CAN_MO152_CTR.
+*/
+#define CAN_MOCTR152 (CAN_MO152_CTR)
+
+/** \brief 2314, Message Object Data Register High */
+#define CAN_MO152_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A314u)
+
+/** Alias (User Manual Name) for CAN_MO152_DATAH.
+* To use register names with standard convension, please use CAN_MO152_DATAH.
+*/
+#define CAN_MODATAH152 (CAN_MO152_DATAH)
+
+/** \brief 2310, Message Object Data Register Low */
+#define CAN_MO152_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A310u)
+
+/** Alias (User Manual Name) for CAN_MO152_DATAL.
+* To use register names with standard convension, please use CAN_MO152_DATAL.
+*/
+#define CAN_MODATAL152 (CAN_MO152_DATAL)
+
+/** \brief 2300, Message Object Function Control Register */
+#define CAN_MO152_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A300u)
+
+/** Alias (User Manual Name) for CAN_MO152_EDATA0.
+* To use register names with standard convension, please use CAN_MO152_EDATA0.
+*/
+#define CAN_EMO152DATA0 (CAN_MO152_EDATA0)
+
+/** \brief 2304, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO152_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A304u)
+
+/** Alias (User Manual Name) for CAN_MO152_EDATA1.
+* To use register names with standard convension, please use CAN_MO152_EDATA1.
+*/
+#define CAN_EMO152DATA1 (CAN_MO152_EDATA1)
+
+/** \brief 2308, Message Object Interrupt Pointer Register */
+#define CAN_MO152_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A308u)
+
+/** Alias (User Manual Name) for CAN_MO152_EDATA2.
+* To use register names with standard convension, please use CAN_MO152_EDATA2.
+*/
+#define CAN_EMO152DATA2 (CAN_MO152_EDATA2)
+
+/** \brief 230C, Message Object Acceptance Mask Register */
+#define CAN_MO152_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A30Cu)
+
+/** Alias (User Manual Name) for CAN_MO152_EDATA3.
+* To use register names with standard convension, please use CAN_MO152_EDATA3.
+*/
+#define CAN_EMO152DATA3 (CAN_MO152_EDATA3)
+
+/** \brief 2310, Message Object Data Register Low */
+#define CAN_MO152_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A310u)
+
+/** Alias (User Manual Name) for CAN_MO152_EDATA4.
+* To use register names with standard convension, please use CAN_MO152_EDATA4.
+*/
+#define CAN_EMO152DATA4 (CAN_MO152_EDATA4)
+
+/** \brief 2314, Message Object Data Register High */
+#define CAN_MO152_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A314u)
+
+/** Alias (User Manual Name) for CAN_MO152_EDATA5.
+* To use register names with standard convension, please use CAN_MO152_EDATA5.
+*/
+#define CAN_EMO152DATA5 (CAN_MO152_EDATA5)
+
+/** \brief 2318, Message Object Arbitration Register */
+#define CAN_MO152_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A318u)
+
+/** Alias (User Manual Name) for CAN_MO152_EDATA6.
+* To use register names with standard convension, please use CAN_MO152_EDATA6.
+*/
+#define CAN_EMO152DATA6 (CAN_MO152_EDATA6)
+
+/** \brief 2300, Message Object Function Control Register */
+#define CAN_MO152_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A300u)
+
+/** Alias (User Manual Name) for CAN_MO152_FCR.
+* To use register names with standard convension, please use CAN_MO152_FCR.
+*/
+#define CAN_MOFCR152 (CAN_MO152_FCR)
+
+/** \brief 2304, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO152_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A304u)
+
+/** Alias (User Manual Name) for CAN_MO152_FGPR.
+* To use register names with standard convension, please use CAN_MO152_FGPR.
+*/
+#define CAN_MOFGPR152 (CAN_MO152_FGPR)
+
+/** \brief 2308, Message Object Interrupt Pointer Register */
+#define CAN_MO152_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A308u)
+
+/** Alias (User Manual Name) for CAN_MO152_IPR.
+* To use register names with standard convension, please use CAN_MO152_IPR.
+*/
+#define CAN_MOIPR152 (CAN_MO152_IPR)
+
+/** \brief 231C, Message Object Control Register */
+#define CAN_MO152_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A31Cu)
+
+/** Alias (User Manual Name) for CAN_MO152_STAT.
+* To use register names with standard convension, please use CAN_MO152_STAT.
+*/
+#define CAN_MOSTAT152 (CAN_MO152_STAT)
+
+/** \brief 232C, Message Object Acceptance Mask Register */
+#define CAN_MO153_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A32Cu)
+
+/** Alias (User Manual Name) for CAN_MO153_AMR.
+* To use register names with standard convension, please use CAN_MO153_AMR.
+*/
+#define CAN_MOAMR153 (CAN_MO153_AMR)
+
+/** \brief 2338, Message Object Arbitration Register */
+#define CAN_MO153_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A338u)
+
+/** Alias (User Manual Name) for CAN_MO153_AR.
+* To use register names with standard convension, please use CAN_MO153_AR.
+*/
+#define CAN_MOAR153 (CAN_MO153_AR)
+
+/** \brief 233C, Message Object Control Register */
+#define CAN_MO153_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A33Cu)
+
+/** Alias (User Manual Name) for CAN_MO153_CTR.
+* To use register names with standard convension, please use CAN_MO153_CTR.
+*/
+#define CAN_MOCTR153 (CAN_MO153_CTR)
+
+/** \brief 2334, Message Object Data Register High */
+#define CAN_MO153_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A334u)
+
+/** Alias (User Manual Name) for CAN_MO153_DATAH.
+* To use register names with standard convension, please use CAN_MO153_DATAH.
+*/
+#define CAN_MODATAH153 (CAN_MO153_DATAH)
+
+/** \brief 2330, Message Object Data Register Low */
+#define CAN_MO153_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A330u)
+
+/** Alias (User Manual Name) for CAN_MO153_DATAL.
+* To use register names with standard convension, please use CAN_MO153_DATAL.
+*/
+#define CAN_MODATAL153 (CAN_MO153_DATAL)
+
+/** \brief 2320, Message Object Function Control Register */
+#define CAN_MO153_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A320u)
+
+/** Alias (User Manual Name) for CAN_MO153_EDATA0.
+* To use register names with standard convension, please use CAN_MO153_EDATA0.
+*/
+#define CAN_EMO153DATA0 (CAN_MO153_EDATA0)
+
+/** \brief 2324, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO153_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A324u)
+
+/** Alias (User Manual Name) for CAN_MO153_EDATA1.
+* To use register names with standard convension, please use CAN_MO153_EDATA1.
+*/
+#define CAN_EMO153DATA1 (CAN_MO153_EDATA1)
+
+/** \brief 2328, Message Object Interrupt Pointer Register */
+#define CAN_MO153_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A328u)
+
+/** Alias (User Manual Name) for CAN_MO153_EDATA2.
+* To use register names with standard convension, please use CAN_MO153_EDATA2.
+*/
+#define CAN_EMO153DATA2 (CAN_MO153_EDATA2)
+
+/** \brief 232C, Message Object Acceptance Mask Register */
+#define CAN_MO153_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A32Cu)
+
+/** Alias (User Manual Name) for CAN_MO153_EDATA3.
+* To use register names with standard convension, please use CAN_MO153_EDATA3.
+*/
+#define CAN_EMO153DATA3 (CAN_MO153_EDATA3)
+
+/** \brief 2330, Message Object Data Register Low */
+#define CAN_MO153_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A330u)
+
+/** Alias (User Manual Name) for CAN_MO153_EDATA4.
+* To use register names with standard convension, please use CAN_MO153_EDATA4.
+*/
+#define CAN_EMO153DATA4 (CAN_MO153_EDATA4)
+
+/** \brief 2334, Message Object Data Register High */
+#define CAN_MO153_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A334u)
+
+/** Alias (User Manual Name) for CAN_MO153_EDATA5.
+* To use register names with standard convension, please use CAN_MO153_EDATA5.
+*/
+#define CAN_EMO153DATA5 (CAN_MO153_EDATA5)
+
+/** \brief 2338, Message Object Arbitration Register */
+#define CAN_MO153_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A338u)
+
+/** Alias (User Manual Name) for CAN_MO153_EDATA6.
+* To use register names with standard convension, please use CAN_MO153_EDATA6.
+*/
+#define CAN_EMO153DATA6 (CAN_MO153_EDATA6)
+
+/** \brief 2320, Message Object Function Control Register */
+#define CAN_MO153_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A320u)
+
+/** Alias (User Manual Name) for CAN_MO153_FCR.
+* To use register names with standard convension, please use CAN_MO153_FCR.
+*/
+#define CAN_MOFCR153 (CAN_MO153_FCR)
+
+/** \brief 2324, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO153_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A324u)
+
+/** Alias (User Manual Name) for CAN_MO153_FGPR.
+* To use register names with standard convension, please use CAN_MO153_FGPR.
+*/
+#define CAN_MOFGPR153 (CAN_MO153_FGPR)
+
+/** \brief 2328, Message Object Interrupt Pointer Register */
+#define CAN_MO153_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A328u)
+
+/** Alias (User Manual Name) for CAN_MO153_IPR.
+* To use register names with standard convension, please use CAN_MO153_IPR.
+*/
+#define CAN_MOIPR153 (CAN_MO153_IPR)
+
+/** \brief 233C, Message Object Control Register */
+#define CAN_MO153_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A33Cu)
+
+/** Alias (User Manual Name) for CAN_MO153_STAT.
+* To use register names with standard convension, please use CAN_MO153_STAT.
+*/
+#define CAN_MOSTAT153 (CAN_MO153_STAT)
+
+/** \brief 234C, Message Object Acceptance Mask Register */
+#define CAN_MO154_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A34Cu)
+
+/** Alias (User Manual Name) for CAN_MO154_AMR.
+* To use register names with standard convension, please use CAN_MO154_AMR.
+*/
+#define CAN_MOAMR154 (CAN_MO154_AMR)
+
+/** \brief 2358, Message Object Arbitration Register */
+#define CAN_MO154_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A358u)
+
+/** Alias (User Manual Name) for CAN_MO154_AR.
+* To use register names with standard convension, please use CAN_MO154_AR.
+*/
+#define CAN_MOAR154 (CAN_MO154_AR)
+
+/** \brief 235C, Message Object Control Register */
+#define CAN_MO154_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A35Cu)
+
+/** Alias (User Manual Name) for CAN_MO154_CTR.
+* To use register names with standard convension, please use CAN_MO154_CTR.
+*/
+#define CAN_MOCTR154 (CAN_MO154_CTR)
+
+/** \brief 2354, Message Object Data Register High */
+#define CAN_MO154_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A354u)
+
+/** Alias (User Manual Name) for CAN_MO154_DATAH.
+* To use register names with standard convension, please use CAN_MO154_DATAH.
+*/
+#define CAN_MODATAH154 (CAN_MO154_DATAH)
+
+/** \brief 2350, Message Object Data Register Low */
+#define CAN_MO154_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A350u)
+
+/** Alias (User Manual Name) for CAN_MO154_DATAL.
+* To use register names with standard convension, please use CAN_MO154_DATAL.
+*/
+#define CAN_MODATAL154 (CAN_MO154_DATAL)
+
+/** \brief 2340, Message Object Function Control Register */
+#define CAN_MO154_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A340u)
+
+/** Alias (User Manual Name) for CAN_MO154_EDATA0.
+* To use register names with standard convension, please use CAN_MO154_EDATA0.
+*/
+#define CAN_EMO154DATA0 (CAN_MO154_EDATA0)
+
+/** \brief 2344, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO154_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A344u)
+
+/** Alias (User Manual Name) for CAN_MO154_EDATA1.
+* To use register names with standard convension, please use CAN_MO154_EDATA1.
+*/
+#define CAN_EMO154DATA1 (CAN_MO154_EDATA1)
+
+/** \brief 2348, Message Object Interrupt Pointer Register */
+#define CAN_MO154_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A348u)
+
+/** Alias (User Manual Name) for CAN_MO154_EDATA2.
+* To use register names with standard convension, please use CAN_MO154_EDATA2.
+*/
+#define CAN_EMO154DATA2 (CAN_MO154_EDATA2)
+
+/** \brief 234C, Message Object Acceptance Mask Register */
+#define CAN_MO154_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A34Cu)
+
+/** Alias (User Manual Name) for CAN_MO154_EDATA3.
+* To use register names with standard convension, please use CAN_MO154_EDATA3.
+*/
+#define CAN_EMO154DATA3 (CAN_MO154_EDATA3)
+
+/** \brief 2350, Message Object Data Register Low */
+#define CAN_MO154_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A350u)
+
+/** Alias (User Manual Name) for CAN_MO154_EDATA4.
+* To use register names with standard convension, please use CAN_MO154_EDATA4.
+*/
+#define CAN_EMO154DATA4 (CAN_MO154_EDATA4)
+
+/** \brief 2354, Message Object Data Register High */
+#define CAN_MO154_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A354u)
+
+/** Alias (User Manual Name) for CAN_MO154_EDATA5.
+* To use register names with standard convension, please use CAN_MO154_EDATA5.
+*/
+#define CAN_EMO154DATA5 (CAN_MO154_EDATA5)
+
+/** \brief 2358, Message Object Arbitration Register */
+#define CAN_MO154_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A358u)
+
+/** Alias (User Manual Name) for CAN_MO154_EDATA6.
+* To use register names with standard convension, please use CAN_MO154_EDATA6.
+*/
+#define CAN_EMO154DATA6 (CAN_MO154_EDATA6)
+
+/** \brief 2340, Message Object Function Control Register */
+#define CAN_MO154_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A340u)
+
+/** Alias (User Manual Name) for CAN_MO154_FCR.
+* To use register names with standard convension, please use CAN_MO154_FCR.
+*/
+#define CAN_MOFCR154 (CAN_MO154_FCR)
+
+/** \brief 2344, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO154_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A344u)
+
+/** Alias (User Manual Name) for CAN_MO154_FGPR.
+* To use register names with standard convension, please use CAN_MO154_FGPR.
+*/
+#define CAN_MOFGPR154 (CAN_MO154_FGPR)
+
+/** \brief 2348, Message Object Interrupt Pointer Register */
+#define CAN_MO154_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A348u)
+
+/** Alias (User Manual Name) for CAN_MO154_IPR.
+* To use register names with standard convension, please use CAN_MO154_IPR.
+*/
+#define CAN_MOIPR154 (CAN_MO154_IPR)
+
+/** \brief 235C, Message Object Control Register */
+#define CAN_MO154_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A35Cu)
+
+/** Alias (User Manual Name) for CAN_MO154_STAT.
+* To use register names with standard convension, please use CAN_MO154_STAT.
+*/
+#define CAN_MOSTAT154 (CAN_MO154_STAT)
+
+/** \brief 236C, Message Object Acceptance Mask Register */
+#define CAN_MO155_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A36Cu)
+
+/** Alias (User Manual Name) for CAN_MO155_AMR.
+* To use register names with standard convension, please use CAN_MO155_AMR.
+*/
+#define CAN_MOAMR155 (CAN_MO155_AMR)
+
+/** \brief 2378, Message Object Arbitration Register */
+#define CAN_MO155_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A378u)
+
+/** Alias (User Manual Name) for CAN_MO155_AR.
+* To use register names with standard convension, please use CAN_MO155_AR.
+*/
+#define CAN_MOAR155 (CAN_MO155_AR)
+
+/** \brief 237C, Message Object Control Register */
+#define CAN_MO155_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A37Cu)
+
+/** Alias (User Manual Name) for CAN_MO155_CTR.
+* To use register names with standard convension, please use CAN_MO155_CTR.
+*/
+#define CAN_MOCTR155 (CAN_MO155_CTR)
+
+/** \brief 2374, Message Object Data Register High */
+#define CAN_MO155_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A374u)
+
+/** Alias (User Manual Name) for CAN_MO155_DATAH.
+* To use register names with standard convension, please use CAN_MO155_DATAH.
+*/
+#define CAN_MODATAH155 (CAN_MO155_DATAH)
+
+/** \brief 2370, Message Object Data Register Low */
+#define CAN_MO155_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A370u)
+
+/** Alias (User Manual Name) for CAN_MO155_DATAL.
+* To use register names with standard convension, please use CAN_MO155_DATAL.
+*/
+#define CAN_MODATAL155 (CAN_MO155_DATAL)
+
+/** \brief 2360, Message Object Function Control Register */
+#define CAN_MO155_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A360u)
+
+/** Alias (User Manual Name) for CAN_MO155_EDATA0.
+* To use register names with standard convension, please use CAN_MO155_EDATA0.
+*/
+#define CAN_EMO155DATA0 (CAN_MO155_EDATA0)
+
+/** \brief 2364, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO155_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A364u)
+
+/** Alias (User Manual Name) for CAN_MO155_EDATA1.
+* To use register names with standard convension, please use CAN_MO155_EDATA1.
+*/
+#define CAN_EMO155DATA1 (CAN_MO155_EDATA1)
+
+/** \brief 2368, Message Object Interrupt Pointer Register */
+#define CAN_MO155_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A368u)
+
+/** Alias (User Manual Name) for CAN_MO155_EDATA2.
+* To use register names with standard convension, please use CAN_MO155_EDATA2.
+*/
+#define CAN_EMO155DATA2 (CAN_MO155_EDATA2)
+
+/** \brief 236C, Message Object Acceptance Mask Register */
+#define CAN_MO155_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A36Cu)
+
+/** Alias (User Manual Name) for CAN_MO155_EDATA3.
+* To use register names with standard convension, please use CAN_MO155_EDATA3.
+*/
+#define CAN_EMO155DATA3 (CAN_MO155_EDATA3)
+
+/** \brief 2370, Message Object Data Register Low */
+#define CAN_MO155_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A370u)
+
+/** Alias (User Manual Name) for CAN_MO155_EDATA4.
+* To use register names with standard convension, please use CAN_MO155_EDATA4.
+*/
+#define CAN_EMO155DATA4 (CAN_MO155_EDATA4)
+
+/** \brief 2374, Message Object Data Register High */
+#define CAN_MO155_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A374u)
+
+/** Alias (User Manual Name) for CAN_MO155_EDATA5.
+* To use register names with standard convension, please use CAN_MO155_EDATA5.
+*/
+#define CAN_EMO155DATA5 (CAN_MO155_EDATA5)
+
+/** \brief 2378, Message Object Arbitration Register */
+#define CAN_MO155_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A378u)
+
+/** Alias (User Manual Name) for CAN_MO155_EDATA6.
+* To use register names with standard convension, please use CAN_MO155_EDATA6.
+*/
+#define CAN_EMO155DATA6 (CAN_MO155_EDATA6)
+
+/** \brief 2360, Message Object Function Control Register */
+#define CAN_MO155_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A360u)
+
+/** Alias (User Manual Name) for CAN_MO155_FCR.
+* To use register names with standard convension, please use CAN_MO155_FCR.
+*/
+#define CAN_MOFCR155 (CAN_MO155_FCR)
+
+/** \brief 2364, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO155_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A364u)
+
+/** Alias (User Manual Name) for CAN_MO155_FGPR.
+* To use register names with standard convension, please use CAN_MO155_FGPR.
+*/
+#define CAN_MOFGPR155 (CAN_MO155_FGPR)
+
+/** \brief 2368, Message Object Interrupt Pointer Register */
+#define CAN_MO155_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A368u)
+
+/** Alias (User Manual Name) for CAN_MO155_IPR.
+* To use register names with standard convension, please use CAN_MO155_IPR.
+*/
+#define CAN_MOIPR155 (CAN_MO155_IPR)
+
+/** \brief 237C, Message Object Control Register */
+#define CAN_MO155_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A37Cu)
+
+/** Alias (User Manual Name) for CAN_MO155_STAT.
+* To use register names with standard convension, please use CAN_MO155_STAT.
+*/
+#define CAN_MOSTAT155 (CAN_MO155_STAT)
+
+/** \brief 238C, Message Object Acceptance Mask Register */
+#define CAN_MO156_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A38Cu)
+
+/** Alias (User Manual Name) for CAN_MO156_AMR.
+* To use register names with standard convension, please use CAN_MO156_AMR.
+*/
+#define CAN_MOAMR156 (CAN_MO156_AMR)
+
+/** \brief 2398, Message Object Arbitration Register */
+#define CAN_MO156_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A398u)
+
+/** Alias (User Manual Name) for CAN_MO156_AR.
+* To use register names with standard convension, please use CAN_MO156_AR.
+*/
+#define CAN_MOAR156 (CAN_MO156_AR)
+
+/** \brief 239C, Message Object Control Register */
+#define CAN_MO156_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A39Cu)
+
+/** Alias (User Manual Name) for CAN_MO156_CTR.
+* To use register names with standard convension, please use CAN_MO156_CTR.
+*/
+#define CAN_MOCTR156 (CAN_MO156_CTR)
+
+/** \brief 2394, Message Object Data Register High */
+#define CAN_MO156_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A394u)
+
+/** Alias (User Manual Name) for CAN_MO156_DATAH.
+* To use register names with standard convension, please use CAN_MO156_DATAH.
+*/
+#define CAN_MODATAH156 (CAN_MO156_DATAH)
+
+/** \brief 2390, Message Object Data Register Low */
+#define CAN_MO156_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A390u)
+
+/** Alias (User Manual Name) for CAN_MO156_DATAL.
+* To use register names with standard convension, please use CAN_MO156_DATAL.
+*/
+#define CAN_MODATAL156 (CAN_MO156_DATAL)
+
+/** \brief 2380, Message Object Function Control Register */
+#define CAN_MO156_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A380u)
+
+/** Alias (User Manual Name) for CAN_MO156_EDATA0.
+* To use register names with standard convension, please use CAN_MO156_EDATA0.
+*/
+#define CAN_EMO156DATA0 (CAN_MO156_EDATA0)
+
+/** \brief 2384, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO156_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A384u)
+
+/** Alias (User Manual Name) for CAN_MO156_EDATA1.
+* To use register names with standard convension, please use CAN_MO156_EDATA1.
+*/
+#define CAN_EMO156DATA1 (CAN_MO156_EDATA1)
+
+/** \brief 2388, Message Object Interrupt Pointer Register */
+#define CAN_MO156_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A388u)
+
+/** Alias (User Manual Name) for CAN_MO156_EDATA2.
+* To use register names with standard convension, please use CAN_MO156_EDATA2.
+*/
+#define CAN_EMO156DATA2 (CAN_MO156_EDATA2)
+
+/** \brief 238C, Message Object Acceptance Mask Register */
+#define CAN_MO156_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A38Cu)
+
+/** Alias (User Manual Name) for CAN_MO156_EDATA3.
+* To use register names with standard convension, please use CAN_MO156_EDATA3.
+*/
+#define CAN_EMO156DATA3 (CAN_MO156_EDATA3)
+
+/** \brief 2390, Message Object Data Register Low */
+#define CAN_MO156_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A390u)
+
+/** Alias (User Manual Name) for CAN_MO156_EDATA4.
+* To use register names with standard convension, please use CAN_MO156_EDATA4.
+*/
+#define CAN_EMO156DATA4 (CAN_MO156_EDATA4)
+
+/** \brief 2394, Message Object Data Register High */
+#define CAN_MO156_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A394u)
+
+/** Alias (User Manual Name) for CAN_MO156_EDATA5.
+* To use register names with standard convension, please use CAN_MO156_EDATA5.
+*/
+#define CAN_EMO156DATA5 (CAN_MO156_EDATA5)
+
+/** \brief 2398, Message Object Arbitration Register */
+#define CAN_MO156_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A398u)
+
+/** Alias (User Manual Name) for CAN_MO156_EDATA6.
+* To use register names with standard convension, please use CAN_MO156_EDATA6.
+*/
+#define CAN_EMO156DATA6 (CAN_MO156_EDATA6)
+
+/** \brief 2380, Message Object Function Control Register */
+#define CAN_MO156_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A380u)
+
+/** Alias (User Manual Name) for CAN_MO156_FCR.
+* To use register names with standard convension, please use CAN_MO156_FCR.
+*/
+#define CAN_MOFCR156 (CAN_MO156_FCR)
+
+/** \brief 2384, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO156_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A384u)
+
+/** Alias (User Manual Name) for CAN_MO156_FGPR.
+* To use register names with standard convension, please use CAN_MO156_FGPR.
+*/
+#define CAN_MOFGPR156 (CAN_MO156_FGPR)
+
+/** \brief 2388, Message Object Interrupt Pointer Register */
+#define CAN_MO156_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A388u)
+
+/** Alias (User Manual Name) for CAN_MO156_IPR.
+* To use register names with standard convension, please use CAN_MO156_IPR.
+*/
+#define CAN_MOIPR156 (CAN_MO156_IPR)
+
+/** \brief 239C, Message Object Control Register */
+#define CAN_MO156_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A39Cu)
+
+/** Alias (User Manual Name) for CAN_MO156_STAT.
+* To use register names with standard convension, please use CAN_MO156_STAT.
+*/
+#define CAN_MOSTAT156 (CAN_MO156_STAT)
+
+/** \brief 23AC, Message Object Acceptance Mask Register */
+#define CAN_MO157_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A3ACu)
+
+/** Alias (User Manual Name) for CAN_MO157_AMR.
+* To use register names with standard convension, please use CAN_MO157_AMR.
+*/
+#define CAN_MOAMR157 (CAN_MO157_AMR)
+
+/** \brief 23B8, Message Object Arbitration Register */
+#define CAN_MO157_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A3B8u)
+
+/** Alias (User Manual Name) for CAN_MO157_AR.
+* To use register names with standard convension, please use CAN_MO157_AR.
+*/
+#define CAN_MOAR157 (CAN_MO157_AR)
+
+/** \brief 23BC, Message Object Control Register */
+#define CAN_MO157_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A3BCu)
+
+/** Alias (User Manual Name) for CAN_MO157_CTR.
+* To use register names with standard convension, please use CAN_MO157_CTR.
+*/
+#define CAN_MOCTR157 (CAN_MO157_CTR)
+
+/** \brief 23B4, Message Object Data Register High */
+#define CAN_MO157_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A3B4u)
+
+/** Alias (User Manual Name) for CAN_MO157_DATAH.
+* To use register names with standard convension, please use CAN_MO157_DATAH.
+*/
+#define CAN_MODATAH157 (CAN_MO157_DATAH)
+
+/** \brief 23B0, Message Object Data Register Low */
+#define CAN_MO157_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A3B0u)
+
+/** Alias (User Manual Name) for CAN_MO157_DATAL.
+* To use register names with standard convension, please use CAN_MO157_DATAL.
+*/
+#define CAN_MODATAL157 (CAN_MO157_DATAL)
+
+/** \brief 23A0, Message Object Function Control Register */
+#define CAN_MO157_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A3A0u)
+
+/** Alias (User Manual Name) for CAN_MO157_EDATA0.
+* To use register names with standard convension, please use CAN_MO157_EDATA0.
+*/
+#define CAN_EMO157DATA0 (CAN_MO157_EDATA0)
+
+/** \brief 23A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO157_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A3A4u)
+
+/** Alias (User Manual Name) for CAN_MO157_EDATA1.
+* To use register names with standard convension, please use CAN_MO157_EDATA1.
+*/
+#define CAN_EMO157DATA1 (CAN_MO157_EDATA1)
+
+/** \brief 23A8, Message Object Interrupt Pointer Register */
+#define CAN_MO157_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A3A8u)
+
+/** Alias (User Manual Name) for CAN_MO157_EDATA2.
+* To use register names with standard convension, please use CAN_MO157_EDATA2.
+*/
+#define CAN_EMO157DATA2 (CAN_MO157_EDATA2)
+
+/** \brief 23AC, Message Object Acceptance Mask Register */
+#define CAN_MO157_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A3ACu)
+
+/** Alias (User Manual Name) for CAN_MO157_EDATA3.
+* To use register names with standard convension, please use CAN_MO157_EDATA3.
+*/
+#define CAN_EMO157DATA3 (CAN_MO157_EDATA3)
+
+/** \brief 23B0, Message Object Data Register Low */
+#define CAN_MO157_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A3B0u)
+
+/** Alias (User Manual Name) for CAN_MO157_EDATA4.
+* To use register names with standard convension, please use CAN_MO157_EDATA4.
+*/
+#define CAN_EMO157DATA4 (CAN_MO157_EDATA4)
+
+/** \brief 23B4, Message Object Data Register High */
+#define CAN_MO157_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A3B4u)
+
+/** Alias (User Manual Name) for CAN_MO157_EDATA5.
+* To use register names with standard convension, please use CAN_MO157_EDATA5.
+*/
+#define CAN_EMO157DATA5 (CAN_MO157_EDATA5)
+
+/** \brief 23B8, Message Object Arbitration Register */
+#define CAN_MO157_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A3B8u)
+
+/** Alias (User Manual Name) for CAN_MO157_EDATA6.
+* To use register names with standard convension, please use CAN_MO157_EDATA6.
+*/
+#define CAN_EMO157DATA6 (CAN_MO157_EDATA6)
+
+/** \brief 23A0, Message Object Function Control Register */
+#define CAN_MO157_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A3A0u)
+
+/** Alias (User Manual Name) for CAN_MO157_FCR.
+* To use register names with standard convension, please use CAN_MO157_FCR.
+*/
+#define CAN_MOFCR157 (CAN_MO157_FCR)
+
+/** \brief 23A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO157_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A3A4u)
+
+/** Alias (User Manual Name) for CAN_MO157_FGPR.
+* To use register names with standard convension, please use CAN_MO157_FGPR.
+*/
+#define CAN_MOFGPR157 (CAN_MO157_FGPR)
+
+/** \brief 23A8, Message Object Interrupt Pointer Register */
+#define CAN_MO157_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A3A8u)
+
+/** Alias (User Manual Name) for CAN_MO157_IPR.
+* To use register names with standard convension, please use CAN_MO157_IPR.
+*/
+#define CAN_MOIPR157 (CAN_MO157_IPR)
+
+/** \brief 23BC, Message Object Control Register */
+#define CAN_MO157_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A3BCu)
+
+/** Alias (User Manual Name) for CAN_MO157_STAT.
+* To use register names with standard convension, please use CAN_MO157_STAT.
+*/
+#define CAN_MOSTAT157 (CAN_MO157_STAT)
+
+/** \brief 23CC, Message Object Acceptance Mask Register */
+#define CAN_MO158_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A3CCu)
+
+/** Alias (User Manual Name) for CAN_MO158_AMR.
+* To use register names with standard convension, please use CAN_MO158_AMR.
+*/
+#define CAN_MOAMR158 (CAN_MO158_AMR)
+
+/** \brief 23D8, Message Object Arbitration Register */
+#define CAN_MO158_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A3D8u)
+
+/** Alias (User Manual Name) for CAN_MO158_AR.
+* To use register names with standard convension, please use CAN_MO158_AR.
+*/
+#define CAN_MOAR158 (CAN_MO158_AR)
+
+/** \brief 23DC, Message Object Control Register */
+#define CAN_MO158_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A3DCu)
+
+/** Alias (User Manual Name) for CAN_MO158_CTR.
+* To use register names with standard convension, please use CAN_MO158_CTR.
+*/
+#define CAN_MOCTR158 (CAN_MO158_CTR)
+
+/** \brief 23D4, Message Object Data Register High */
+#define CAN_MO158_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A3D4u)
+
+/** Alias (User Manual Name) for CAN_MO158_DATAH.
+* To use register names with standard convension, please use CAN_MO158_DATAH.
+*/
+#define CAN_MODATAH158 (CAN_MO158_DATAH)
+
+/** \brief 23D0, Message Object Data Register Low */
+#define CAN_MO158_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A3D0u)
+
+/** Alias (User Manual Name) for CAN_MO158_DATAL.
+* To use register names with standard convension, please use CAN_MO158_DATAL.
+*/
+#define CAN_MODATAL158 (CAN_MO158_DATAL)
+
+/** \brief 23C0, Message Object Function Control Register */
+#define CAN_MO158_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A3C0u)
+
+/** Alias (User Manual Name) for CAN_MO158_EDATA0.
+* To use register names with standard convension, please use CAN_MO158_EDATA0.
+*/
+#define CAN_EMO158DATA0 (CAN_MO158_EDATA0)
+
+/** \brief 23C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO158_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A3C4u)
+
+/** Alias (User Manual Name) for CAN_MO158_EDATA1.
+* To use register names with standard convension, please use CAN_MO158_EDATA1.
+*/
+#define CAN_EMO158DATA1 (CAN_MO158_EDATA1)
+
+/** \brief 23C8, Message Object Interrupt Pointer Register */
+#define CAN_MO158_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A3C8u)
+
+/** Alias (User Manual Name) for CAN_MO158_EDATA2.
+* To use register names with standard convension, please use CAN_MO158_EDATA2.
+*/
+#define CAN_EMO158DATA2 (CAN_MO158_EDATA2)
+
+/** \brief 23CC, Message Object Acceptance Mask Register */
+#define CAN_MO158_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A3CCu)
+
+/** Alias (User Manual Name) for CAN_MO158_EDATA3.
+* To use register names with standard convension, please use CAN_MO158_EDATA3.
+*/
+#define CAN_EMO158DATA3 (CAN_MO158_EDATA3)
+
+/** \brief 23D0, Message Object Data Register Low */
+#define CAN_MO158_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A3D0u)
+
+/** Alias (User Manual Name) for CAN_MO158_EDATA4.
+* To use register names with standard convension, please use CAN_MO158_EDATA4.
+*/
+#define CAN_EMO158DATA4 (CAN_MO158_EDATA4)
+
+/** \brief 23D4, Message Object Data Register High */
+#define CAN_MO158_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A3D4u)
+
+/** Alias (User Manual Name) for CAN_MO158_EDATA5.
+* To use register names with standard convension, please use CAN_MO158_EDATA5.
+*/
+#define CAN_EMO158DATA5 (CAN_MO158_EDATA5)
+
+/** \brief 23D8, Message Object Arbitration Register */
+#define CAN_MO158_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A3D8u)
+
+/** Alias (User Manual Name) for CAN_MO158_EDATA6.
+* To use register names with standard convension, please use CAN_MO158_EDATA6.
+*/
+#define CAN_EMO158DATA6 (CAN_MO158_EDATA6)
+
+/** \brief 23C0, Message Object Function Control Register */
+#define CAN_MO158_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A3C0u)
+
+/** Alias (User Manual Name) for CAN_MO158_FCR.
+* To use register names with standard convension, please use CAN_MO158_FCR.
+*/
+#define CAN_MOFCR158 (CAN_MO158_FCR)
+
+/** \brief 23C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO158_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A3C4u)
+
+/** Alias (User Manual Name) for CAN_MO158_FGPR.
+* To use register names with standard convension, please use CAN_MO158_FGPR.
+*/
+#define CAN_MOFGPR158 (CAN_MO158_FGPR)
+
+/** \brief 23C8, Message Object Interrupt Pointer Register */
+#define CAN_MO158_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A3C8u)
+
+/** Alias (User Manual Name) for CAN_MO158_IPR.
+* To use register names with standard convension, please use CAN_MO158_IPR.
+*/
+#define CAN_MOIPR158 (CAN_MO158_IPR)
+
+/** \brief 23DC, Message Object Control Register */
+#define CAN_MO158_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A3DCu)
+
+/** Alias (User Manual Name) for CAN_MO158_STAT.
+* To use register names with standard convension, please use CAN_MO158_STAT.
+*/
+#define CAN_MOSTAT158 (CAN_MO158_STAT)
+
+/** \brief 23EC, Message Object Acceptance Mask Register */
+#define CAN_MO159_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A3ECu)
+
+/** Alias (User Manual Name) for CAN_MO159_AMR.
+* To use register names with standard convension, please use CAN_MO159_AMR.
+*/
+#define CAN_MOAMR159 (CAN_MO159_AMR)
+
+/** \brief 23F8, Message Object Arbitration Register */
+#define CAN_MO159_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A3F8u)
+
+/** Alias (User Manual Name) for CAN_MO159_AR.
+* To use register names with standard convension, please use CAN_MO159_AR.
+*/
+#define CAN_MOAR159 (CAN_MO159_AR)
+
+/** \brief 23FC, Message Object Control Register */
+#define CAN_MO159_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A3FCu)
+
+/** Alias (User Manual Name) for CAN_MO159_CTR.
+* To use register names with standard convension, please use CAN_MO159_CTR.
+*/
+#define CAN_MOCTR159 (CAN_MO159_CTR)
+
+/** \brief 23F4, Message Object Data Register High */
+#define CAN_MO159_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A3F4u)
+
+/** Alias (User Manual Name) for CAN_MO159_DATAH.
+* To use register names with standard convension, please use CAN_MO159_DATAH.
+*/
+#define CAN_MODATAH159 (CAN_MO159_DATAH)
+
+/** \brief 23F0, Message Object Data Register Low */
+#define CAN_MO159_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A3F0u)
+
+/** Alias (User Manual Name) for CAN_MO159_DATAL.
+* To use register names with standard convension, please use CAN_MO159_DATAL.
+*/
+#define CAN_MODATAL159 (CAN_MO159_DATAL)
+
+/** \brief 23E0, Message Object Function Control Register */
+#define CAN_MO159_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A3E0u)
+
+/** Alias (User Manual Name) for CAN_MO159_EDATA0.
+* To use register names with standard convension, please use CAN_MO159_EDATA0.
+*/
+#define CAN_EMO159DATA0 (CAN_MO159_EDATA0)
+
+/** \brief 23E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO159_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A3E4u)
+
+/** Alias (User Manual Name) for CAN_MO159_EDATA1.
+* To use register names with standard convension, please use CAN_MO159_EDATA1.
+*/
+#define CAN_EMO159DATA1 (CAN_MO159_EDATA1)
+
+/** \brief 23E8, Message Object Interrupt Pointer Register */
+#define CAN_MO159_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A3E8u)
+
+/** Alias (User Manual Name) for CAN_MO159_EDATA2.
+* To use register names with standard convension, please use CAN_MO159_EDATA2.
+*/
+#define CAN_EMO159DATA2 (CAN_MO159_EDATA2)
+
+/** \brief 23EC, Message Object Acceptance Mask Register */
+#define CAN_MO159_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A3ECu)
+
+/** Alias (User Manual Name) for CAN_MO159_EDATA3.
+* To use register names with standard convension, please use CAN_MO159_EDATA3.
+*/
+#define CAN_EMO159DATA3 (CAN_MO159_EDATA3)
+
+/** \brief 23F0, Message Object Data Register Low */
+#define CAN_MO159_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A3F0u)
+
+/** Alias (User Manual Name) for CAN_MO159_EDATA4.
+* To use register names with standard convension, please use CAN_MO159_EDATA4.
+*/
+#define CAN_EMO159DATA4 (CAN_MO159_EDATA4)
+
+/** \brief 23F4, Message Object Data Register High */
+#define CAN_MO159_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A3F4u)
+
+/** Alias (User Manual Name) for CAN_MO159_EDATA5.
+* To use register names with standard convension, please use CAN_MO159_EDATA5.
+*/
+#define CAN_EMO159DATA5 (CAN_MO159_EDATA5)
+
+/** \brief 23F8, Message Object Arbitration Register */
+#define CAN_MO159_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A3F8u)
+
+/** Alias (User Manual Name) for CAN_MO159_EDATA6.
+* To use register names with standard convension, please use CAN_MO159_EDATA6.
+*/
+#define CAN_EMO159DATA6 (CAN_MO159_EDATA6)
+
+/** \brief 23E0, Message Object Function Control Register */
+#define CAN_MO159_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A3E0u)
+
+/** Alias (User Manual Name) for CAN_MO159_FCR.
+* To use register names with standard convension, please use CAN_MO159_FCR.
+*/
+#define CAN_MOFCR159 (CAN_MO159_FCR)
+
+/** \brief 23E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO159_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A3E4u)
+
+/** Alias (User Manual Name) for CAN_MO159_FGPR.
+* To use register names with standard convension, please use CAN_MO159_FGPR.
+*/
+#define CAN_MOFGPR159 (CAN_MO159_FGPR)
+
+/** \brief 23E8, Message Object Interrupt Pointer Register */
+#define CAN_MO159_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A3E8u)
+
+/** Alias (User Manual Name) for CAN_MO159_IPR.
+* To use register names with standard convension, please use CAN_MO159_IPR.
+*/
+#define CAN_MOIPR159 (CAN_MO159_IPR)
+
+/** \brief 23FC, Message Object Control Register */
+#define CAN_MO159_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A3FCu)
+
+/** Alias (User Manual Name) for CAN_MO159_STAT.
+* To use register names with standard convension, please use CAN_MO159_STAT.
+*/
+#define CAN_MOSTAT159 (CAN_MO159_STAT)
+
+/** \brief 11EC, Message Object Acceptance Mask Register */
+#define CAN_MO15_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00191ECu)
+
+/** Alias (User Manual Name) for CAN_MO15_AMR.
+* To use register names with standard convension, please use CAN_MO15_AMR.
+*/
+#define CAN_MOAMR15 (CAN_MO15_AMR)
+
+/** \brief 11F8, Message Object Arbitration Register */
+#define CAN_MO15_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00191F8u)
+
+/** Alias (User Manual Name) for CAN_MO15_AR.
+* To use register names with standard convension, please use CAN_MO15_AR.
+*/
+#define CAN_MOAR15 (CAN_MO15_AR)
+
+/** \brief 11FC, Message Object Control Register */
+#define CAN_MO15_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00191FCu)
+
+/** Alias (User Manual Name) for CAN_MO15_CTR.
+* To use register names with standard convension, please use CAN_MO15_CTR.
+*/
+#define CAN_MOCTR15 (CAN_MO15_CTR)
+
+/** \brief 11F4, Message Object Data Register High */
+#define CAN_MO15_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00191F4u)
+
+/** Alias (User Manual Name) for CAN_MO15_DATAH.
+* To use register names with standard convension, please use CAN_MO15_DATAH.
+*/
+#define CAN_MODATAH15 (CAN_MO15_DATAH)
+
+/** \brief 11F0, Message Object Data Register Low */
+#define CAN_MO15_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00191F0u)
+
+/** Alias (User Manual Name) for CAN_MO15_DATAL.
+* To use register names with standard convension, please use CAN_MO15_DATAL.
+*/
+#define CAN_MODATAL15 (CAN_MO15_DATAL)
+
+/** \brief 11E0, Message Object Function Control Register */
+#define CAN_MO15_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00191E0u)
+
+/** Alias (User Manual Name) for CAN_MO15_EDATA0.
+* To use register names with standard convension, please use CAN_MO15_EDATA0.
+*/
+#define CAN_EMO15DATA0 (CAN_MO15_EDATA0)
+
+/** \brief 11E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO15_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00191E4u)
+
+/** Alias (User Manual Name) for CAN_MO15_EDATA1.
+* To use register names with standard convension, please use CAN_MO15_EDATA1.
+*/
+#define CAN_EMO15DATA1 (CAN_MO15_EDATA1)
+
+/** \brief 11E8, Message Object Interrupt Pointer Register */
+#define CAN_MO15_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00191E8u)
+
+/** Alias (User Manual Name) for CAN_MO15_EDATA2.
+* To use register names with standard convension, please use CAN_MO15_EDATA2.
+*/
+#define CAN_EMO15DATA2 (CAN_MO15_EDATA2)
+
+/** \brief 11EC, Message Object Acceptance Mask Register */
+#define CAN_MO15_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00191ECu)
+
+/** Alias (User Manual Name) for CAN_MO15_EDATA3.
+* To use register names with standard convension, please use CAN_MO15_EDATA3.
+*/
+#define CAN_EMO15DATA3 (CAN_MO15_EDATA3)
+
+/** \brief 11F0, Message Object Data Register Low */
+#define CAN_MO15_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00191F0u)
+
+/** Alias (User Manual Name) for CAN_MO15_EDATA4.
+* To use register names with standard convension, please use CAN_MO15_EDATA4.
+*/
+#define CAN_EMO15DATA4 (CAN_MO15_EDATA4)
+
+/** \brief 11F4, Message Object Data Register High */
+#define CAN_MO15_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00191F4u)
+
+/** Alias (User Manual Name) for CAN_MO15_EDATA5.
+* To use register names with standard convension, please use CAN_MO15_EDATA5.
+*/
+#define CAN_EMO15DATA5 (CAN_MO15_EDATA5)
+
+/** \brief 11F8, Message Object Arbitration Register */
+#define CAN_MO15_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00191F8u)
+
+/** Alias (User Manual Name) for CAN_MO15_EDATA6.
+* To use register names with standard convension, please use CAN_MO15_EDATA6.
+*/
+#define CAN_EMO15DATA6 (CAN_MO15_EDATA6)
+
+/** \brief 11E0, Message Object Function Control Register */
+#define CAN_MO15_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00191E0u)
+
+/** Alias (User Manual Name) for CAN_MO15_FCR.
+* To use register names with standard convension, please use CAN_MO15_FCR.
+*/
+#define CAN_MOFCR15 (CAN_MO15_FCR)
+
+/** \brief 11E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO15_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00191E4u)
+
+/** Alias (User Manual Name) for CAN_MO15_FGPR.
+* To use register names with standard convension, please use CAN_MO15_FGPR.
+*/
+#define CAN_MOFGPR15 (CAN_MO15_FGPR)
+
+/** \brief 11E8, Message Object Interrupt Pointer Register */
+#define CAN_MO15_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00191E8u)
+
+/** Alias (User Manual Name) for CAN_MO15_IPR.
+* To use register names with standard convension, please use CAN_MO15_IPR.
+*/
+#define CAN_MOIPR15 (CAN_MO15_IPR)
+
+/** \brief 11FC, Message Object Control Register */
+#define CAN_MO15_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00191FCu)
+
+/** Alias (User Manual Name) for CAN_MO15_STAT.
+* To use register names with standard convension, please use CAN_MO15_STAT.
+*/
+#define CAN_MOSTAT15 (CAN_MO15_STAT)
+
+/** \brief 240C, Message Object Acceptance Mask Register */
+#define CAN_MO160_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A40Cu)
+
+/** Alias (User Manual Name) for CAN_MO160_AMR.
+* To use register names with standard convension, please use CAN_MO160_AMR.
+*/
+#define CAN_MOAMR160 (CAN_MO160_AMR)
+
+/** \brief 2418, Message Object Arbitration Register */
+#define CAN_MO160_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A418u)
+
+/** Alias (User Manual Name) for CAN_MO160_AR.
+* To use register names with standard convension, please use CAN_MO160_AR.
+*/
+#define CAN_MOAR160 (CAN_MO160_AR)
+
+/** \brief 241C, Message Object Control Register */
+#define CAN_MO160_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A41Cu)
+
+/** Alias (User Manual Name) for CAN_MO160_CTR.
+* To use register names with standard convension, please use CAN_MO160_CTR.
+*/
+#define CAN_MOCTR160 (CAN_MO160_CTR)
+
+/** \brief 2414, Message Object Data Register High */
+#define CAN_MO160_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A414u)
+
+/** Alias (User Manual Name) for CAN_MO160_DATAH.
+* To use register names with standard convension, please use CAN_MO160_DATAH.
+*/
+#define CAN_MODATAH160 (CAN_MO160_DATAH)
+
+/** \brief 2410, Message Object Data Register Low */
+#define CAN_MO160_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A410u)
+
+/** Alias (User Manual Name) for CAN_MO160_DATAL.
+* To use register names with standard convension, please use CAN_MO160_DATAL.
+*/
+#define CAN_MODATAL160 (CAN_MO160_DATAL)
+
+/** \brief 2400, Message Object Function Control Register */
+#define CAN_MO160_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A400u)
+
+/** Alias (User Manual Name) for CAN_MO160_EDATA0.
+* To use register names with standard convension, please use CAN_MO160_EDATA0.
+*/
+#define CAN_EMO160DATA0 (CAN_MO160_EDATA0)
+
+/** \brief 2404, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO160_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A404u)
+
+/** Alias (User Manual Name) for CAN_MO160_EDATA1.
+* To use register names with standard convension, please use CAN_MO160_EDATA1.
+*/
+#define CAN_EMO160DATA1 (CAN_MO160_EDATA1)
+
+/** \brief 2408, Message Object Interrupt Pointer Register */
+#define CAN_MO160_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A408u)
+
+/** Alias (User Manual Name) for CAN_MO160_EDATA2.
+* To use register names with standard convension, please use CAN_MO160_EDATA2.
+*/
+#define CAN_EMO160DATA2 (CAN_MO160_EDATA2)
+
+/** \brief 240C, Message Object Acceptance Mask Register */
+#define CAN_MO160_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A40Cu)
+
+/** Alias (User Manual Name) for CAN_MO160_EDATA3.
+* To use register names with standard convension, please use CAN_MO160_EDATA3.
+*/
+#define CAN_EMO160DATA3 (CAN_MO160_EDATA3)
+
+/** \brief 2410, Message Object Data Register Low */
+#define CAN_MO160_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A410u)
+
+/** Alias (User Manual Name) for CAN_MO160_EDATA4.
+* To use register names with standard convension, please use CAN_MO160_EDATA4.
+*/
+#define CAN_EMO160DATA4 (CAN_MO160_EDATA4)
+
+/** \brief 2414, Message Object Data Register High */
+#define CAN_MO160_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A414u)
+
+/** Alias (User Manual Name) for CAN_MO160_EDATA5.
+* To use register names with standard convension, please use CAN_MO160_EDATA5.
+*/
+#define CAN_EMO160DATA5 (CAN_MO160_EDATA5)
+
+/** \brief 2418, Message Object Arbitration Register */
+#define CAN_MO160_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A418u)
+
+/** Alias (User Manual Name) for CAN_MO160_EDATA6.
+* To use register names with standard convension, please use CAN_MO160_EDATA6.
+*/
+#define CAN_EMO160DATA6 (CAN_MO160_EDATA6)
+
+/** \brief 2400, Message Object Function Control Register */
+#define CAN_MO160_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A400u)
+
+/** Alias (User Manual Name) for CAN_MO160_FCR.
+* To use register names with standard convension, please use CAN_MO160_FCR.
+*/
+#define CAN_MOFCR160 (CAN_MO160_FCR)
+
+/** \brief 2404, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO160_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A404u)
+
+/** Alias (User Manual Name) for CAN_MO160_FGPR.
+* To use register names with standard convension, please use CAN_MO160_FGPR.
+*/
+#define CAN_MOFGPR160 (CAN_MO160_FGPR)
+
+/** \brief 2408, Message Object Interrupt Pointer Register */
+#define CAN_MO160_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A408u)
+
+/** Alias (User Manual Name) for CAN_MO160_IPR.
+* To use register names with standard convension, please use CAN_MO160_IPR.
+*/
+#define CAN_MOIPR160 (CAN_MO160_IPR)
+
+/** \brief 241C, Message Object Control Register */
+#define CAN_MO160_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A41Cu)
+
+/** Alias (User Manual Name) for CAN_MO160_STAT.
+* To use register names with standard convension, please use CAN_MO160_STAT.
+*/
+#define CAN_MOSTAT160 (CAN_MO160_STAT)
+
+/** \brief 242C, Message Object Acceptance Mask Register */
+#define CAN_MO161_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A42Cu)
+
+/** Alias (User Manual Name) for CAN_MO161_AMR.
+* To use register names with standard convension, please use CAN_MO161_AMR.
+*/
+#define CAN_MOAMR161 (CAN_MO161_AMR)
+
+/** \brief 2438, Message Object Arbitration Register */
+#define CAN_MO161_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A438u)
+
+/** Alias (User Manual Name) for CAN_MO161_AR.
+* To use register names with standard convension, please use CAN_MO161_AR.
+*/
+#define CAN_MOAR161 (CAN_MO161_AR)
+
+/** \brief 243C, Message Object Control Register */
+#define CAN_MO161_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A43Cu)
+
+/** Alias (User Manual Name) for CAN_MO161_CTR.
+* To use register names with standard convension, please use CAN_MO161_CTR.
+*/
+#define CAN_MOCTR161 (CAN_MO161_CTR)
+
+/** \brief 2434, Message Object Data Register High */
+#define CAN_MO161_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A434u)
+
+/** Alias (User Manual Name) for CAN_MO161_DATAH.
+* To use register names with standard convension, please use CAN_MO161_DATAH.
+*/
+#define CAN_MODATAH161 (CAN_MO161_DATAH)
+
+/** \brief 2430, Message Object Data Register Low */
+#define CAN_MO161_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A430u)
+
+/** Alias (User Manual Name) for CAN_MO161_DATAL.
+* To use register names with standard convension, please use CAN_MO161_DATAL.
+*/
+#define CAN_MODATAL161 (CAN_MO161_DATAL)
+
+/** \brief 2420, Message Object Function Control Register */
+#define CAN_MO161_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A420u)
+
+/** Alias (User Manual Name) for CAN_MO161_EDATA0.
+* To use register names with standard convension, please use CAN_MO161_EDATA0.
+*/
+#define CAN_EMO161DATA0 (CAN_MO161_EDATA0)
+
+/** \brief 2424, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO161_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A424u)
+
+/** Alias (User Manual Name) for CAN_MO161_EDATA1.
+* To use register names with standard convension, please use CAN_MO161_EDATA1.
+*/
+#define CAN_EMO161DATA1 (CAN_MO161_EDATA1)
+
+/** \brief 2428, Message Object Interrupt Pointer Register */
+#define CAN_MO161_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A428u)
+
+/** Alias (User Manual Name) for CAN_MO161_EDATA2.
+* To use register names with standard convension, please use CAN_MO161_EDATA2.
+*/
+#define CAN_EMO161DATA2 (CAN_MO161_EDATA2)
+
+/** \brief 242C, Message Object Acceptance Mask Register */
+#define CAN_MO161_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A42Cu)
+
+/** Alias (User Manual Name) for CAN_MO161_EDATA3.
+* To use register names with standard convension, please use CAN_MO161_EDATA3.
+*/
+#define CAN_EMO161DATA3 (CAN_MO161_EDATA3)
+
+/** \brief 2430, Message Object Data Register Low */
+#define CAN_MO161_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A430u)
+
+/** Alias (User Manual Name) for CAN_MO161_EDATA4.
+* To use register names with standard convension, please use CAN_MO161_EDATA4.
+*/
+#define CAN_EMO161DATA4 (CAN_MO161_EDATA4)
+
+/** \brief 2434, Message Object Data Register High */
+#define CAN_MO161_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A434u)
+
+/** Alias (User Manual Name) for CAN_MO161_EDATA5.
+* To use register names with standard convension, please use CAN_MO161_EDATA5.
+*/
+#define CAN_EMO161DATA5 (CAN_MO161_EDATA5)
+
+/** \brief 2438, Message Object Arbitration Register */
+#define CAN_MO161_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A438u)
+
+/** Alias (User Manual Name) for CAN_MO161_EDATA6.
+* To use register names with standard convension, please use CAN_MO161_EDATA6.
+*/
+#define CAN_EMO161DATA6 (CAN_MO161_EDATA6)
+
+/** \brief 2420, Message Object Function Control Register */
+#define CAN_MO161_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A420u)
+
+/** Alias (User Manual Name) for CAN_MO161_FCR.
+* To use register names with standard convension, please use CAN_MO161_FCR.
+*/
+#define CAN_MOFCR161 (CAN_MO161_FCR)
+
+/** \brief 2424, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO161_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A424u)
+
+/** Alias (User Manual Name) for CAN_MO161_FGPR.
+* To use register names with standard convension, please use CAN_MO161_FGPR.
+*/
+#define CAN_MOFGPR161 (CAN_MO161_FGPR)
+
+/** \brief 2428, Message Object Interrupt Pointer Register */
+#define CAN_MO161_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A428u)
+
+/** Alias (User Manual Name) for CAN_MO161_IPR.
+* To use register names with standard convension, please use CAN_MO161_IPR.
+*/
+#define CAN_MOIPR161 (CAN_MO161_IPR)
+
+/** \brief 243C, Message Object Control Register */
+#define CAN_MO161_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A43Cu)
+
+/** Alias (User Manual Name) for CAN_MO161_STAT.
+* To use register names with standard convension, please use CAN_MO161_STAT.
+*/
+#define CAN_MOSTAT161 (CAN_MO161_STAT)
+
+/** \brief 244C, Message Object Acceptance Mask Register */
+#define CAN_MO162_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A44Cu)
+
+/** Alias (User Manual Name) for CAN_MO162_AMR.
+* To use register names with standard convension, please use CAN_MO162_AMR.
+*/
+#define CAN_MOAMR162 (CAN_MO162_AMR)
+
+/** \brief 2458, Message Object Arbitration Register */
+#define CAN_MO162_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A458u)
+
+/** Alias (User Manual Name) for CAN_MO162_AR.
+* To use register names with standard convension, please use CAN_MO162_AR.
+*/
+#define CAN_MOAR162 (CAN_MO162_AR)
+
+/** \brief 245C, Message Object Control Register */
+#define CAN_MO162_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A45Cu)
+
+/** Alias (User Manual Name) for CAN_MO162_CTR.
+* To use register names with standard convension, please use CAN_MO162_CTR.
+*/
+#define CAN_MOCTR162 (CAN_MO162_CTR)
+
+/** \brief 2454, Message Object Data Register High */
+#define CAN_MO162_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A454u)
+
+/** Alias (User Manual Name) for CAN_MO162_DATAH.
+* To use register names with standard convension, please use CAN_MO162_DATAH.
+*/
+#define CAN_MODATAH162 (CAN_MO162_DATAH)
+
+/** \brief 2450, Message Object Data Register Low */
+#define CAN_MO162_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A450u)
+
+/** Alias (User Manual Name) for CAN_MO162_DATAL.
+* To use register names with standard convension, please use CAN_MO162_DATAL.
+*/
+#define CAN_MODATAL162 (CAN_MO162_DATAL)
+
+/** \brief 2440, Message Object Function Control Register */
+#define CAN_MO162_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A440u)
+
+/** Alias (User Manual Name) for CAN_MO162_EDATA0.
+* To use register names with standard convension, please use CAN_MO162_EDATA0.
+*/
+#define CAN_EMO162DATA0 (CAN_MO162_EDATA0)
+
+/** \brief 2444, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO162_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A444u)
+
+/** Alias (User Manual Name) for CAN_MO162_EDATA1.
+* To use register names with standard convension, please use CAN_MO162_EDATA1.
+*/
+#define CAN_EMO162DATA1 (CAN_MO162_EDATA1)
+
+/** \brief 2448, Message Object Interrupt Pointer Register */
+#define CAN_MO162_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A448u)
+
+/** Alias (User Manual Name) for CAN_MO162_EDATA2.
+* To use register names with standard convension, please use CAN_MO162_EDATA2.
+*/
+#define CAN_EMO162DATA2 (CAN_MO162_EDATA2)
+
+/** \brief 244C, Message Object Acceptance Mask Register */
+#define CAN_MO162_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A44Cu)
+
+/** Alias (User Manual Name) for CAN_MO162_EDATA3.
+* To use register names with standard convension, please use CAN_MO162_EDATA3.
+*/
+#define CAN_EMO162DATA3 (CAN_MO162_EDATA3)
+
+/** \brief 2450, Message Object Data Register Low */
+#define CAN_MO162_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A450u)
+
+/** Alias (User Manual Name) for CAN_MO162_EDATA4.
+* To use register names with standard convension, please use CAN_MO162_EDATA4.
+*/
+#define CAN_EMO162DATA4 (CAN_MO162_EDATA4)
+
+/** \brief 2454, Message Object Data Register High */
+#define CAN_MO162_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A454u)
+
+/** Alias (User Manual Name) for CAN_MO162_EDATA5.
+* To use register names with standard convension, please use CAN_MO162_EDATA5.
+*/
+#define CAN_EMO162DATA5 (CAN_MO162_EDATA5)
+
+/** \brief 2458, Message Object Arbitration Register */
+#define CAN_MO162_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A458u)
+
+/** Alias (User Manual Name) for CAN_MO162_EDATA6.
+* To use register names with standard convension, please use CAN_MO162_EDATA6.
+*/
+#define CAN_EMO162DATA6 (CAN_MO162_EDATA6)
+
+/** \brief 2440, Message Object Function Control Register */
+#define CAN_MO162_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A440u)
+
+/** Alias (User Manual Name) for CAN_MO162_FCR.
+* To use register names with standard convension, please use CAN_MO162_FCR.
+*/
+#define CAN_MOFCR162 (CAN_MO162_FCR)
+
+/** \brief 2444, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO162_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A444u)
+
+/** Alias (User Manual Name) for CAN_MO162_FGPR.
+* To use register names with standard convension, please use CAN_MO162_FGPR.
+*/
+#define CAN_MOFGPR162 (CAN_MO162_FGPR)
+
+/** \brief 2448, Message Object Interrupt Pointer Register */
+#define CAN_MO162_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A448u)
+
+/** Alias (User Manual Name) for CAN_MO162_IPR.
+* To use register names with standard convension, please use CAN_MO162_IPR.
+*/
+#define CAN_MOIPR162 (CAN_MO162_IPR)
+
+/** \brief 245C, Message Object Control Register */
+#define CAN_MO162_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A45Cu)
+
+/** Alias (User Manual Name) for CAN_MO162_STAT.
+* To use register names with standard convension, please use CAN_MO162_STAT.
+*/
+#define CAN_MOSTAT162 (CAN_MO162_STAT)
+
+/** \brief 246C, Message Object Acceptance Mask Register */
+#define CAN_MO163_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A46Cu)
+
+/** Alias (User Manual Name) for CAN_MO163_AMR.
+* To use register names with standard convension, please use CAN_MO163_AMR.
+*/
+#define CAN_MOAMR163 (CAN_MO163_AMR)
+
+/** \brief 2478, Message Object Arbitration Register */
+#define CAN_MO163_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A478u)
+
+/** Alias (User Manual Name) for CAN_MO163_AR.
+* To use register names with standard convension, please use CAN_MO163_AR.
+*/
+#define CAN_MOAR163 (CAN_MO163_AR)
+
+/** \brief 247C, Message Object Control Register */
+#define CAN_MO163_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A47Cu)
+
+/** Alias (User Manual Name) for CAN_MO163_CTR.
+* To use register names with standard convension, please use CAN_MO163_CTR.
+*/
+#define CAN_MOCTR163 (CAN_MO163_CTR)
+
+/** \brief 2474, Message Object Data Register High */
+#define CAN_MO163_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A474u)
+
+/** Alias (User Manual Name) for CAN_MO163_DATAH.
+* To use register names with standard convension, please use CAN_MO163_DATAH.
+*/
+#define CAN_MODATAH163 (CAN_MO163_DATAH)
+
+/** \brief 2470, Message Object Data Register Low */
+#define CAN_MO163_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A470u)
+
+/** Alias (User Manual Name) for CAN_MO163_DATAL.
+* To use register names with standard convension, please use CAN_MO163_DATAL.
+*/
+#define CAN_MODATAL163 (CAN_MO163_DATAL)
+
+/** \brief 2460, Message Object Function Control Register */
+#define CAN_MO163_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A460u)
+
+/** Alias (User Manual Name) for CAN_MO163_EDATA0.
+* To use register names with standard convension, please use CAN_MO163_EDATA0.
+*/
+#define CAN_EMO163DATA0 (CAN_MO163_EDATA0)
+
+/** \brief 2464, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO163_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A464u)
+
+/** Alias (User Manual Name) for CAN_MO163_EDATA1.
+* To use register names with standard convension, please use CAN_MO163_EDATA1.
+*/
+#define CAN_EMO163DATA1 (CAN_MO163_EDATA1)
+
+/** \brief 2468, Message Object Interrupt Pointer Register */
+#define CAN_MO163_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A468u)
+
+/** Alias (User Manual Name) for CAN_MO163_EDATA2.
+* To use register names with standard convension, please use CAN_MO163_EDATA2.
+*/
+#define CAN_EMO163DATA2 (CAN_MO163_EDATA2)
+
+/** \brief 246C, Message Object Acceptance Mask Register */
+#define CAN_MO163_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A46Cu)
+
+/** Alias (User Manual Name) for CAN_MO163_EDATA3.
+* To use register names with standard convension, please use CAN_MO163_EDATA3.
+*/
+#define CAN_EMO163DATA3 (CAN_MO163_EDATA3)
+
+/** \brief 2470, Message Object Data Register Low */
+#define CAN_MO163_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A470u)
+
+/** Alias (User Manual Name) for CAN_MO163_EDATA4.
+* To use register names with standard convension, please use CAN_MO163_EDATA4.
+*/
+#define CAN_EMO163DATA4 (CAN_MO163_EDATA4)
+
+/** \brief 2474, Message Object Data Register High */
+#define CAN_MO163_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A474u)
+
+/** Alias (User Manual Name) for CAN_MO163_EDATA5.
+* To use register names with standard convension, please use CAN_MO163_EDATA5.
+*/
+#define CAN_EMO163DATA5 (CAN_MO163_EDATA5)
+
+/** \brief 2478, Message Object Arbitration Register */
+#define CAN_MO163_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A478u)
+
+/** Alias (User Manual Name) for CAN_MO163_EDATA6.
+* To use register names with standard convension, please use CAN_MO163_EDATA6.
+*/
+#define CAN_EMO163DATA6 (CAN_MO163_EDATA6)
+
+/** \brief 2460, Message Object Function Control Register */
+#define CAN_MO163_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A460u)
+
+/** Alias (User Manual Name) for CAN_MO163_FCR.
+* To use register names with standard convension, please use CAN_MO163_FCR.
+*/
+#define CAN_MOFCR163 (CAN_MO163_FCR)
+
+/** \brief 2464, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO163_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A464u)
+
+/** Alias (User Manual Name) for CAN_MO163_FGPR.
+* To use register names with standard convension, please use CAN_MO163_FGPR.
+*/
+#define CAN_MOFGPR163 (CAN_MO163_FGPR)
+
+/** \brief 2468, Message Object Interrupt Pointer Register */
+#define CAN_MO163_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A468u)
+
+/** Alias (User Manual Name) for CAN_MO163_IPR.
+* To use register names with standard convension, please use CAN_MO163_IPR.
+*/
+#define CAN_MOIPR163 (CAN_MO163_IPR)
+
+/** \brief 247C, Message Object Control Register */
+#define CAN_MO163_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A47Cu)
+
+/** Alias (User Manual Name) for CAN_MO163_STAT.
+* To use register names with standard convension, please use CAN_MO163_STAT.
+*/
+#define CAN_MOSTAT163 (CAN_MO163_STAT)
+
+/** \brief 248C, Message Object Acceptance Mask Register */
+#define CAN_MO164_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A48Cu)
+
+/** Alias (User Manual Name) for CAN_MO164_AMR.
+* To use register names with standard convension, please use CAN_MO164_AMR.
+*/
+#define CAN_MOAMR164 (CAN_MO164_AMR)
+
+/** \brief 2498, Message Object Arbitration Register */
+#define CAN_MO164_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A498u)
+
+/** Alias (User Manual Name) for CAN_MO164_AR.
+* To use register names with standard convension, please use CAN_MO164_AR.
+*/
+#define CAN_MOAR164 (CAN_MO164_AR)
+
+/** \brief 249C, Message Object Control Register */
+#define CAN_MO164_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A49Cu)
+
+/** Alias (User Manual Name) for CAN_MO164_CTR.
+* To use register names with standard convension, please use CAN_MO164_CTR.
+*/
+#define CAN_MOCTR164 (CAN_MO164_CTR)
+
+/** \brief 2494, Message Object Data Register High */
+#define CAN_MO164_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A494u)
+
+/** Alias (User Manual Name) for CAN_MO164_DATAH.
+* To use register names with standard convension, please use CAN_MO164_DATAH.
+*/
+#define CAN_MODATAH164 (CAN_MO164_DATAH)
+
+/** \brief 2490, Message Object Data Register Low */
+#define CAN_MO164_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A490u)
+
+/** Alias (User Manual Name) for CAN_MO164_DATAL.
+* To use register names with standard convension, please use CAN_MO164_DATAL.
+*/
+#define CAN_MODATAL164 (CAN_MO164_DATAL)
+
+/** \brief 2480, Message Object Function Control Register */
+#define CAN_MO164_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A480u)
+
+/** Alias (User Manual Name) for CAN_MO164_EDATA0.
+* To use register names with standard convension, please use CAN_MO164_EDATA0.
+*/
+#define CAN_EMO164DATA0 (CAN_MO164_EDATA0)
+
+/** \brief 2484, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO164_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A484u)
+
+/** Alias (User Manual Name) for CAN_MO164_EDATA1.
+* To use register names with standard convension, please use CAN_MO164_EDATA1.
+*/
+#define CAN_EMO164DATA1 (CAN_MO164_EDATA1)
+
+/** \brief 2488, Message Object Interrupt Pointer Register */
+#define CAN_MO164_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A488u)
+
+/** Alias (User Manual Name) for CAN_MO164_EDATA2.
+* To use register names with standard convension, please use CAN_MO164_EDATA2.
+*/
+#define CAN_EMO164DATA2 (CAN_MO164_EDATA2)
+
+/** \brief 248C, Message Object Acceptance Mask Register */
+#define CAN_MO164_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A48Cu)
+
+/** Alias (User Manual Name) for CAN_MO164_EDATA3.
+* To use register names with standard convension, please use CAN_MO164_EDATA3.
+*/
+#define CAN_EMO164DATA3 (CAN_MO164_EDATA3)
+
+/** \brief 2490, Message Object Data Register Low */
+#define CAN_MO164_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A490u)
+
+/** Alias (User Manual Name) for CAN_MO164_EDATA4.
+* To use register names with standard convension, please use CAN_MO164_EDATA4.
+*/
+#define CAN_EMO164DATA4 (CAN_MO164_EDATA4)
+
+/** \brief 2494, Message Object Data Register High */
+#define CAN_MO164_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A494u)
+
+/** Alias (User Manual Name) for CAN_MO164_EDATA5.
+* To use register names with standard convension, please use CAN_MO164_EDATA5.
+*/
+#define CAN_EMO164DATA5 (CAN_MO164_EDATA5)
+
+/** \brief 2498, Message Object Arbitration Register */
+#define CAN_MO164_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A498u)
+
+/** Alias (User Manual Name) for CAN_MO164_EDATA6.
+* To use register names with standard convension, please use CAN_MO164_EDATA6.
+*/
+#define CAN_EMO164DATA6 (CAN_MO164_EDATA6)
+
+/** \brief 2480, Message Object Function Control Register */
+#define CAN_MO164_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A480u)
+
+/** Alias (User Manual Name) for CAN_MO164_FCR.
+* To use register names with standard convension, please use CAN_MO164_FCR.
+*/
+#define CAN_MOFCR164 (CAN_MO164_FCR)
+
+/** \brief 2484, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO164_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A484u)
+
+/** Alias (User Manual Name) for CAN_MO164_FGPR.
+* To use register names with standard convension, please use CAN_MO164_FGPR.
+*/
+#define CAN_MOFGPR164 (CAN_MO164_FGPR)
+
+/** \brief 2488, Message Object Interrupt Pointer Register */
+#define CAN_MO164_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A488u)
+
+/** Alias (User Manual Name) for CAN_MO164_IPR.
+* To use register names with standard convension, please use CAN_MO164_IPR.
+*/
+#define CAN_MOIPR164 (CAN_MO164_IPR)
+
+/** \brief 249C, Message Object Control Register */
+#define CAN_MO164_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A49Cu)
+
+/** Alias (User Manual Name) for CAN_MO164_STAT.
+* To use register names with standard convension, please use CAN_MO164_STAT.
+*/
+#define CAN_MOSTAT164 (CAN_MO164_STAT)
+
+/** \brief 24AC, Message Object Acceptance Mask Register */
+#define CAN_MO165_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A4ACu)
+
+/** Alias (User Manual Name) for CAN_MO165_AMR.
+* To use register names with standard convension, please use CAN_MO165_AMR.
+*/
+#define CAN_MOAMR165 (CAN_MO165_AMR)
+
+/** \brief 24B8, Message Object Arbitration Register */
+#define CAN_MO165_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A4B8u)
+
+/** Alias (User Manual Name) for CAN_MO165_AR.
+* To use register names with standard convension, please use CAN_MO165_AR.
+*/
+#define CAN_MOAR165 (CAN_MO165_AR)
+
+/** \brief 24BC, Message Object Control Register */
+#define CAN_MO165_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A4BCu)
+
+/** Alias (User Manual Name) for CAN_MO165_CTR.
+* To use register names with standard convension, please use CAN_MO165_CTR.
+*/
+#define CAN_MOCTR165 (CAN_MO165_CTR)
+
+/** \brief 24B4, Message Object Data Register High */
+#define CAN_MO165_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A4B4u)
+
+/** Alias (User Manual Name) for CAN_MO165_DATAH.
+* To use register names with standard convension, please use CAN_MO165_DATAH.
+*/
+#define CAN_MODATAH165 (CAN_MO165_DATAH)
+
+/** \brief 24B0, Message Object Data Register Low */
+#define CAN_MO165_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A4B0u)
+
+/** Alias (User Manual Name) for CAN_MO165_DATAL.
+* To use register names with standard convension, please use CAN_MO165_DATAL.
+*/
+#define CAN_MODATAL165 (CAN_MO165_DATAL)
+
+/** \brief 24A0, Message Object Function Control Register */
+#define CAN_MO165_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A4A0u)
+
+/** Alias (User Manual Name) for CAN_MO165_EDATA0.
+* To use register names with standard convension, please use CAN_MO165_EDATA0.
+*/
+#define CAN_EMO165DATA0 (CAN_MO165_EDATA0)
+
+/** \brief 24A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO165_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A4A4u)
+
+/** Alias (User Manual Name) for CAN_MO165_EDATA1.
+* To use register names with standard convension, please use CAN_MO165_EDATA1.
+*/
+#define CAN_EMO165DATA1 (CAN_MO165_EDATA1)
+
+/** \brief 24A8, Message Object Interrupt Pointer Register */
+#define CAN_MO165_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A4A8u)
+
+/** Alias (User Manual Name) for CAN_MO165_EDATA2.
+* To use register names with standard convension, please use CAN_MO165_EDATA2.
+*/
+#define CAN_EMO165DATA2 (CAN_MO165_EDATA2)
+
+/** \brief 24AC, Message Object Acceptance Mask Register */
+#define CAN_MO165_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A4ACu)
+
+/** Alias (User Manual Name) for CAN_MO165_EDATA3.
+* To use register names with standard convension, please use CAN_MO165_EDATA3.
+*/
+#define CAN_EMO165DATA3 (CAN_MO165_EDATA3)
+
+/** \brief 24B0, Message Object Data Register Low */
+#define CAN_MO165_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A4B0u)
+
+/** Alias (User Manual Name) for CAN_MO165_EDATA4.
+* To use register names with standard convension, please use CAN_MO165_EDATA4.
+*/
+#define CAN_EMO165DATA4 (CAN_MO165_EDATA4)
+
+/** \brief 24B4, Message Object Data Register High */
+#define CAN_MO165_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A4B4u)
+
+/** Alias (User Manual Name) for CAN_MO165_EDATA5.
+* To use register names with standard convension, please use CAN_MO165_EDATA5.
+*/
+#define CAN_EMO165DATA5 (CAN_MO165_EDATA5)
+
+/** \brief 24B8, Message Object Arbitration Register */
+#define CAN_MO165_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A4B8u)
+
+/** Alias (User Manual Name) for CAN_MO165_EDATA6.
+* To use register names with standard convension, please use CAN_MO165_EDATA6.
+*/
+#define CAN_EMO165DATA6 (CAN_MO165_EDATA6)
+
+/** \brief 24A0, Message Object Function Control Register */
+#define CAN_MO165_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A4A0u)
+
+/** Alias (User Manual Name) for CAN_MO165_FCR.
+* To use register names with standard convension, please use CAN_MO165_FCR.
+*/
+#define CAN_MOFCR165 (CAN_MO165_FCR)
+
+/** \brief 24A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO165_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A4A4u)
+
+/** Alias (User Manual Name) for CAN_MO165_FGPR.
+* To use register names with standard convension, please use CAN_MO165_FGPR.
+*/
+#define CAN_MOFGPR165 (CAN_MO165_FGPR)
+
+/** \brief 24A8, Message Object Interrupt Pointer Register */
+#define CAN_MO165_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A4A8u)
+
+/** Alias (User Manual Name) for CAN_MO165_IPR.
+* To use register names with standard convension, please use CAN_MO165_IPR.
+*/
+#define CAN_MOIPR165 (CAN_MO165_IPR)
+
+/** \brief 24BC, Message Object Control Register */
+#define CAN_MO165_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A4BCu)
+
+/** Alias (User Manual Name) for CAN_MO165_STAT.
+* To use register names with standard convension, please use CAN_MO165_STAT.
+*/
+#define CAN_MOSTAT165 (CAN_MO165_STAT)
+
+/** \brief 24CC, Message Object Acceptance Mask Register */
+#define CAN_MO166_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A4CCu)
+
+/** Alias (User Manual Name) for CAN_MO166_AMR.
+* To use register names with standard convension, please use CAN_MO166_AMR.
+*/
+#define CAN_MOAMR166 (CAN_MO166_AMR)
+
+/** \brief 24D8, Message Object Arbitration Register */
+#define CAN_MO166_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A4D8u)
+
+/** Alias (User Manual Name) for CAN_MO166_AR.
+* To use register names with standard convension, please use CAN_MO166_AR.
+*/
+#define CAN_MOAR166 (CAN_MO166_AR)
+
+/** \brief 24DC, Message Object Control Register */
+#define CAN_MO166_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A4DCu)
+
+/** Alias (User Manual Name) for CAN_MO166_CTR.
+* To use register names with standard convension, please use CAN_MO166_CTR.
+*/
+#define CAN_MOCTR166 (CAN_MO166_CTR)
+
+/** \brief 24D4, Message Object Data Register High */
+#define CAN_MO166_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A4D4u)
+
+/** Alias (User Manual Name) for CAN_MO166_DATAH.
+* To use register names with standard convension, please use CAN_MO166_DATAH.
+*/
+#define CAN_MODATAH166 (CAN_MO166_DATAH)
+
+/** \brief 24D0, Message Object Data Register Low */
+#define CAN_MO166_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A4D0u)
+
+/** Alias (User Manual Name) for CAN_MO166_DATAL.
+* To use register names with standard convension, please use CAN_MO166_DATAL.
+*/
+#define CAN_MODATAL166 (CAN_MO166_DATAL)
+
+/** \brief 24C0, Message Object Function Control Register */
+#define CAN_MO166_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A4C0u)
+
+/** Alias (User Manual Name) for CAN_MO166_EDATA0.
+* To use register names with standard convension, please use CAN_MO166_EDATA0.
+*/
+#define CAN_EMO166DATA0 (CAN_MO166_EDATA0)
+
+/** \brief 24C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO166_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A4C4u)
+
+/** Alias (User Manual Name) for CAN_MO166_EDATA1.
+* To use register names with standard convension, please use CAN_MO166_EDATA1.
+*/
+#define CAN_EMO166DATA1 (CAN_MO166_EDATA1)
+
+/** \brief 24C8, Message Object Interrupt Pointer Register */
+#define CAN_MO166_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A4C8u)
+
+/** Alias (User Manual Name) for CAN_MO166_EDATA2.
+* To use register names with standard convension, please use CAN_MO166_EDATA2.
+*/
+#define CAN_EMO166DATA2 (CAN_MO166_EDATA2)
+
+/** \brief 24CC, Message Object Acceptance Mask Register */
+#define CAN_MO166_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A4CCu)
+
+/** Alias (User Manual Name) for CAN_MO166_EDATA3.
+* To use register names with standard convension, please use CAN_MO166_EDATA3.
+*/
+#define CAN_EMO166DATA3 (CAN_MO166_EDATA3)
+
+/** \brief 24D0, Message Object Data Register Low */
+#define CAN_MO166_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A4D0u)
+
+/** Alias (User Manual Name) for CAN_MO166_EDATA4.
+* To use register names with standard convension, please use CAN_MO166_EDATA4.
+*/
+#define CAN_EMO166DATA4 (CAN_MO166_EDATA4)
+
+/** \brief 24D4, Message Object Data Register High */
+#define CAN_MO166_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A4D4u)
+
+/** Alias (User Manual Name) for CAN_MO166_EDATA5.
+* To use register names with standard convension, please use CAN_MO166_EDATA5.
+*/
+#define CAN_EMO166DATA5 (CAN_MO166_EDATA5)
+
+/** \brief 24D8, Message Object Arbitration Register */
+#define CAN_MO166_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A4D8u)
+
+/** Alias (User Manual Name) for CAN_MO166_EDATA6.
+* To use register names with standard convension, please use CAN_MO166_EDATA6.
+*/
+#define CAN_EMO166DATA6 (CAN_MO166_EDATA6)
+
+/** \brief 24C0, Message Object Function Control Register */
+#define CAN_MO166_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A4C0u)
+
+/** Alias (User Manual Name) for CAN_MO166_FCR.
+* To use register names with standard convension, please use CAN_MO166_FCR.
+*/
+#define CAN_MOFCR166 (CAN_MO166_FCR)
+
+/** \brief 24C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO166_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A4C4u)
+
+/** Alias (User Manual Name) for CAN_MO166_FGPR.
+* To use register names with standard convension, please use CAN_MO166_FGPR.
+*/
+#define CAN_MOFGPR166 (CAN_MO166_FGPR)
+
+/** \brief 24C8, Message Object Interrupt Pointer Register */
+#define CAN_MO166_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A4C8u)
+
+/** Alias (User Manual Name) for CAN_MO166_IPR.
+* To use register names with standard convension, please use CAN_MO166_IPR.
+*/
+#define CAN_MOIPR166 (CAN_MO166_IPR)
+
+/** \brief 24DC, Message Object Control Register */
+#define CAN_MO166_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A4DCu)
+
+/** Alias (User Manual Name) for CAN_MO166_STAT.
+* To use register names with standard convension, please use CAN_MO166_STAT.
+*/
+#define CAN_MOSTAT166 (CAN_MO166_STAT)
+
+/** \brief 24EC, Message Object Acceptance Mask Register */
+#define CAN_MO167_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A4ECu)
+
+/** Alias (User Manual Name) for CAN_MO167_AMR.
+* To use register names with standard convension, please use CAN_MO167_AMR.
+*/
+#define CAN_MOAMR167 (CAN_MO167_AMR)
+
+/** \brief 24F8, Message Object Arbitration Register */
+#define CAN_MO167_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A4F8u)
+
+/** Alias (User Manual Name) for CAN_MO167_AR.
+* To use register names with standard convension, please use CAN_MO167_AR.
+*/
+#define CAN_MOAR167 (CAN_MO167_AR)
+
+/** \brief 24FC, Message Object Control Register */
+#define CAN_MO167_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A4FCu)
+
+/** Alias (User Manual Name) for CAN_MO167_CTR.
+* To use register names with standard convension, please use CAN_MO167_CTR.
+*/
+#define CAN_MOCTR167 (CAN_MO167_CTR)
+
+/** \brief 24F4, Message Object Data Register High */
+#define CAN_MO167_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A4F4u)
+
+/** Alias (User Manual Name) for CAN_MO167_DATAH.
+* To use register names with standard convension, please use CAN_MO167_DATAH.
+*/
+#define CAN_MODATAH167 (CAN_MO167_DATAH)
+
+/** \brief 24F0, Message Object Data Register Low */
+#define CAN_MO167_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A4F0u)
+
+/** Alias (User Manual Name) for CAN_MO167_DATAL.
+* To use register names with standard convension, please use CAN_MO167_DATAL.
+*/
+#define CAN_MODATAL167 (CAN_MO167_DATAL)
+
+/** \brief 24E0, Message Object Function Control Register */
+#define CAN_MO167_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A4E0u)
+
+/** Alias (User Manual Name) for CAN_MO167_EDATA0.
+* To use register names with standard convension, please use CAN_MO167_EDATA0.
+*/
+#define CAN_EMO167DATA0 (CAN_MO167_EDATA0)
+
+/** \brief 24E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO167_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A4E4u)
+
+/** Alias (User Manual Name) for CAN_MO167_EDATA1.
+* To use register names with standard convension, please use CAN_MO167_EDATA1.
+*/
+#define CAN_EMO167DATA1 (CAN_MO167_EDATA1)
+
+/** \brief 24E8, Message Object Interrupt Pointer Register */
+#define CAN_MO167_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A4E8u)
+
+/** Alias (User Manual Name) for CAN_MO167_EDATA2.
+* To use register names with standard convension, please use CAN_MO167_EDATA2.
+*/
+#define CAN_EMO167DATA2 (CAN_MO167_EDATA2)
+
+/** \brief 24EC, Message Object Acceptance Mask Register */
+#define CAN_MO167_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A4ECu)
+
+/** Alias (User Manual Name) for CAN_MO167_EDATA3.
+* To use register names with standard convension, please use CAN_MO167_EDATA3.
+*/
+#define CAN_EMO167DATA3 (CAN_MO167_EDATA3)
+
+/** \brief 24F0, Message Object Data Register Low */
+#define CAN_MO167_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A4F0u)
+
+/** Alias (User Manual Name) for CAN_MO167_EDATA4.
+* To use register names with standard convension, please use CAN_MO167_EDATA4.
+*/
+#define CAN_EMO167DATA4 (CAN_MO167_EDATA4)
+
+/** \brief 24F4, Message Object Data Register High */
+#define CAN_MO167_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A4F4u)
+
+/** Alias (User Manual Name) for CAN_MO167_EDATA5.
+* To use register names with standard convension, please use CAN_MO167_EDATA5.
+*/
+#define CAN_EMO167DATA5 (CAN_MO167_EDATA5)
+
+/** \brief 24F8, Message Object Arbitration Register */
+#define CAN_MO167_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A4F8u)
+
+/** Alias (User Manual Name) for CAN_MO167_EDATA6.
+* To use register names with standard convension, please use CAN_MO167_EDATA6.
+*/
+#define CAN_EMO167DATA6 (CAN_MO167_EDATA6)
+
+/** \brief 24E0, Message Object Function Control Register */
+#define CAN_MO167_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A4E0u)
+
+/** Alias (User Manual Name) for CAN_MO167_FCR.
+* To use register names with standard convension, please use CAN_MO167_FCR.
+*/
+#define CAN_MOFCR167 (CAN_MO167_FCR)
+
+/** \brief 24E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO167_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A4E4u)
+
+/** Alias (User Manual Name) for CAN_MO167_FGPR.
+* To use register names with standard convension, please use CAN_MO167_FGPR.
+*/
+#define CAN_MOFGPR167 (CAN_MO167_FGPR)
+
+/** \brief 24E8, Message Object Interrupt Pointer Register */
+#define CAN_MO167_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A4E8u)
+
+/** Alias (User Manual Name) for CAN_MO167_IPR.
+* To use register names with standard convension, please use CAN_MO167_IPR.
+*/
+#define CAN_MOIPR167 (CAN_MO167_IPR)
+
+/** \brief 24FC, Message Object Control Register */
+#define CAN_MO167_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A4FCu)
+
+/** Alias (User Manual Name) for CAN_MO167_STAT.
+* To use register names with standard convension, please use CAN_MO167_STAT.
+*/
+#define CAN_MOSTAT167 (CAN_MO167_STAT)
+
+/** \brief 250C, Message Object Acceptance Mask Register */
+#define CAN_MO168_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A50Cu)
+
+/** Alias (User Manual Name) for CAN_MO168_AMR.
+* To use register names with standard convension, please use CAN_MO168_AMR.
+*/
+#define CAN_MOAMR168 (CAN_MO168_AMR)
+
+/** \brief 2518, Message Object Arbitration Register */
+#define CAN_MO168_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A518u)
+
+/** Alias (User Manual Name) for CAN_MO168_AR.
+* To use register names with standard convension, please use CAN_MO168_AR.
+*/
+#define CAN_MOAR168 (CAN_MO168_AR)
+
+/** \brief 251C, Message Object Control Register */
+#define CAN_MO168_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A51Cu)
+
+/** Alias (User Manual Name) for CAN_MO168_CTR.
+* To use register names with standard convension, please use CAN_MO168_CTR.
+*/
+#define CAN_MOCTR168 (CAN_MO168_CTR)
+
+/** \brief 2514, Message Object Data Register High */
+#define CAN_MO168_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A514u)
+
+/** Alias (User Manual Name) for CAN_MO168_DATAH.
+* To use register names with standard convension, please use CAN_MO168_DATAH.
+*/
+#define CAN_MODATAH168 (CAN_MO168_DATAH)
+
+/** \brief 2510, Message Object Data Register Low */
+#define CAN_MO168_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A510u)
+
+/** Alias (User Manual Name) for CAN_MO168_DATAL.
+* To use register names with standard convension, please use CAN_MO168_DATAL.
+*/
+#define CAN_MODATAL168 (CAN_MO168_DATAL)
+
+/** \brief 2500, Message Object Function Control Register */
+#define CAN_MO168_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A500u)
+
+/** Alias (User Manual Name) for CAN_MO168_EDATA0.
+* To use register names with standard convension, please use CAN_MO168_EDATA0.
+*/
+#define CAN_EMO168DATA0 (CAN_MO168_EDATA0)
+
+/** \brief 2504, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO168_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A504u)
+
+/** Alias (User Manual Name) for CAN_MO168_EDATA1.
+* To use register names with standard convension, please use CAN_MO168_EDATA1.
+*/
+#define CAN_EMO168DATA1 (CAN_MO168_EDATA1)
+
+/** \brief 2508, Message Object Interrupt Pointer Register */
+#define CAN_MO168_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A508u)
+
+/** Alias (User Manual Name) for CAN_MO168_EDATA2.
+* To use register names with standard convension, please use CAN_MO168_EDATA2.
+*/
+#define CAN_EMO168DATA2 (CAN_MO168_EDATA2)
+
+/** \brief 250C, Message Object Acceptance Mask Register */
+#define CAN_MO168_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A50Cu)
+
+/** Alias (User Manual Name) for CAN_MO168_EDATA3.
+* To use register names with standard convension, please use CAN_MO168_EDATA3.
+*/
+#define CAN_EMO168DATA3 (CAN_MO168_EDATA3)
+
+/** \brief 2510, Message Object Data Register Low */
+#define CAN_MO168_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A510u)
+
+/** Alias (User Manual Name) for CAN_MO168_EDATA4.
+* To use register names with standard convension, please use CAN_MO168_EDATA4.
+*/
+#define CAN_EMO168DATA4 (CAN_MO168_EDATA4)
+
+/** \brief 2514, Message Object Data Register High */
+#define CAN_MO168_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A514u)
+
+/** Alias (User Manual Name) for CAN_MO168_EDATA5.
+* To use register names with standard convension, please use CAN_MO168_EDATA5.
+*/
+#define CAN_EMO168DATA5 (CAN_MO168_EDATA5)
+
+/** \brief 2518, Message Object Arbitration Register */
+#define CAN_MO168_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A518u)
+
+/** Alias (User Manual Name) for CAN_MO168_EDATA6.
+* To use register names with standard convension, please use CAN_MO168_EDATA6.
+*/
+#define CAN_EMO168DATA6 (CAN_MO168_EDATA6)
+
+/** \brief 2500, Message Object Function Control Register */
+#define CAN_MO168_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A500u)
+
+/** Alias (User Manual Name) for CAN_MO168_FCR.
+* To use register names with standard convension, please use CAN_MO168_FCR.
+*/
+#define CAN_MOFCR168 (CAN_MO168_FCR)
+
+/** \brief 2504, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO168_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A504u)
+
+/** Alias (User Manual Name) for CAN_MO168_FGPR.
+* To use register names with standard convension, please use CAN_MO168_FGPR.
+*/
+#define CAN_MOFGPR168 (CAN_MO168_FGPR)
+
+/** \brief 2508, Message Object Interrupt Pointer Register */
+#define CAN_MO168_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A508u)
+
+/** Alias (User Manual Name) for CAN_MO168_IPR.
+* To use register names with standard convension, please use CAN_MO168_IPR.
+*/
+#define CAN_MOIPR168 (CAN_MO168_IPR)
+
+/** \brief 251C, Message Object Control Register */
+#define CAN_MO168_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A51Cu)
+
+/** Alias (User Manual Name) for CAN_MO168_STAT.
+* To use register names with standard convension, please use CAN_MO168_STAT.
+*/
+#define CAN_MOSTAT168 (CAN_MO168_STAT)
+
+/** \brief 252C, Message Object Acceptance Mask Register */
+#define CAN_MO169_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A52Cu)
+
+/** Alias (User Manual Name) for CAN_MO169_AMR.
+* To use register names with standard convension, please use CAN_MO169_AMR.
+*/
+#define CAN_MOAMR169 (CAN_MO169_AMR)
+
+/** \brief 2538, Message Object Arbitration Register */
+#define CAN_MO169_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A538u)
+
+/** Alias (User Manual Name) for CAN_MO169_AR.
+* To use register names with standard convension, please use CAN_MO169_AR.
+*/
+#define CAN_MOAR169 (CAN_MO169_AR)
+
+/** \brief 253C, Message Object Control Register */
+#define CAN_MO169_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A53Cu)
+
+/** Alias (User Manual Name) for CAN_MO169_CTR.
+* To use register names with standard convension, please use CAN_MO169_CTR.
+*/
+#define CAN_MOCTR169 (CAN_MO169_CTR)
+
+/** \brief 2534, Message Object Data Register High */
+#define CAN_MO169_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A534u)
+
+/** Alias (User Manual Name) for CAN_MO169_DATAH.
+* To use register names with standard convension, please use CAN_MO169_DATAH.
+*/
+#define CAN_MODATAH169 (CAN_MO169_DATAH)
+
+/** \brief 2530, Message Object Data Register Low */
+#define CAN_MO169_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A530u)
+
+/** Alias (User Manual Name) for CAN_MO169_DATAL.
+* To use register names with standard convension, please use CAN_MO169_DATAL.
+*/
+#define CAN_MODATAL169 (CAN_MO169_DATAL)
+
+/** \brief 2520, Message Object Function Control Register */
+#define CAN_MO169_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A520u)
+
+/** Alias (User Manual Name) for CAN_MO169_EDATA0.
+* To use register names with standard convension, please use CAN_MO169_EDATA0.
+*/
+#define CAN_EMO169DATA0 (CAN_MO169_EDATA0)
+
+/** \brief 2524, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO169_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A524u)
+
+/** Alias (User Manual Name) for CAN_MO169_EDATA1.
+* To use register names with standard convension, please use CAN_MO169_EDATA1.
+*/
+#define CAN_EMO169DATA1 (CAN_MO169_EDATA1)
+
+/** \brief 2528, Message Object Interrupt Pointer Register */
+#define CAN_MO169_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A528u)
+
+/** Alias (User Manual Name) for CAN_MO169_EDATA2.
+* To use register names with standard convension, please use CAN_MO169_EDATA2.
+*/
+#define CAN_EMO169DATA2 (CAN_MO169_EDATA2)
+
+/** \brief 252C, Message Object Acceptance Mask Register */
+#define CAN_MO169_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A52Cu)
+
+/** Alias (User Manual Name) for CAN_MO169_EDATA3.
+* To use register names with standard convension, please use CAN_MO169_EDATA3.
+*/
+#define CAN_EMO169DATA3 (CAN_MO169_EDATA3)
+
+/** \brief 2530, Message Object Data Register Low */
+#define CAN_MO169_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A530u)
+
+/** Alias (User Manual Name) for CAN_MO169_EDATA4.
+* To use register names with standard convension, please use CAN_MO169_EDATA4.
+*/
+#define CAN_EMO169DATA4 (CAN_MO169_EDATA4)
+
+/** \brief 2534, Message Object Data Register High */
+#define CAN_MO169_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A534u)
+
+/** Alias (User Manual Name) for CAN_MO169_EDATA5.
+* To use register names with standard convension, please use CAN_MO169_EDATA5.
+*/
+#define CAN_EMO169DATA5 (CAN_MO169_EDATA5)
+
+/** \brief 2538, Message Object Arbitration Register */
+#define CAN_MO169_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A538u)
+
+/** Alias (User Manual Name) for CAN_MO169_EDATA6.
+* To use register names with standard convension, please use CAN_MO169_EDATA6.
+*/
+#define CAN_EMO169DATA6 (CAN_MO169_EDATA6)
+
+/** \brief 2520, Message Object Function Control Register */
+#define CAN_MO169_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A520u)
+
+/** Alias (User Manual Name) for CAN_MO169_FCR.
+* To use register names with standard convension, please use CAN_MO169_FCR.
+*/
+#define CAN_MOFCR169 (CAN_MO169_FCR)
+
+/** \brief 2524, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO169_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A524u)
+
+/** Alias (User Manual Name) for CAN_MO169_FGPR.
+* To use register names with standard convension, please use CAN_MO169_FGPR.
+*/
+#define CAN_MOFGPR169 (CAN_MO169_FGPR)
+
+/** \brief 2528, Message Object Interrupt Pointer Register */
+#define CAN_MO169_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A528u)
+
+/** Alias (User Manual Name) for CAN_MO169_IPR.
+* To use register names with standard convension, please use CAN_MO169_IPR.
+*/
+#define CAN_MOIPR169 (CAN_MO169_IPR)
+
+/** \brief 253C, Message Object Control Register */
+#define CAN_MO169_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A53Cu)
+
+/** Alias (User Manual Name) for CAN_MO169_STAT.
+* To use register names with standard convension, please use CAN_MO169_STAT.
+*/
+#define CAN_MOSTAT169 (CAN_MO169_STAT)
+
+/** \brief 120C, Message Object Acceptance Mask Register */
+#define CAN_MO16_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001920Cu)
+
+/** Alias (User Manual Name) for CAN_MO16_AMR.
+* To use register names with standard convension, please use CAN_MO16_AMR.
+*/
+#define CAN_MOAMR16 (CAN_MO16_AMR)
+
+/** \brief 1218, Message Object Arbitration Register */
+#define CAN_MO16_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019218u)
+
+/** Alias (User Manual Name) for CAN_MO16_AR.
+* To use register names with standard convension, please use CAN_MO16_AR.
+*/
+#define CAN_MOAR16 (CAN_MO16_AR)
+
+/** \brief 121C, Message Object Control Register */
+#define CAN_MO16_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001921Cu)
+
+/** Alias (User Manual Name) for CAN_MO16_CTR.
+* To use register names with standard convension, please use CAN_MO16_CTR.
+*/
+#define CAN_MOCTR16 (CAN_MO16_CTR)
+
+/** \brief 1214, Message Object Data Register High */
+#define CAN_MO16_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019214u)
+
+/** Alias (User Manual Name) for CAN_MO16_DATAH.
+* To use register names with standard convension, please use CAN_MO16_DATAH.
+*/
+#define CAN_MODATAH16 (CAN_MO16_DATAH)
+
+/** \brief 1210, Message Object Data Register Low */
+#define CAN_MO16_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019210u)
+
+/** Alias (User Manual Name) for CAN_MO16_DATAL.
+* To use register names with standard convension, please use CAN_MO16_DATAL.
+*/
+#define CAN_MODATAL16 (CAN_MO16_DATAL)
+
+/** \brief 1200, Message Object Function Control Register */
+#define CAN_MO16_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019200u)
+
+/** Alias (User Manual Name) for CAN_MO16_EDATA0.
+* To use register names with standard convension, please use CAN_MO16_EDATA0.
+*/
+#define CAN_EMO16DATA0 (CAN_MO16_EDATA0)
+
+/** \brief 1204, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO16_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019204u)
+
+/** Alias (User Manual Name) for CAN_MO16_EDATA1.
+* To use register names with standard convension, please use CAN_MO16_EDATA1.
+*/
+#define CAN_EMO16DATA1 (CAN_MO16_EDATA1)
+
+/** \brief 1208, Message Object Interrupt Pointer Register */
+#define CAN_MO16_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019208u)
+
+/** Alias (User Manual Name) for CAN_MO16_EDATA2.
+* To use register names with standard convension, please use CAN_MO16_EDATA2.
+*/
+#define CAN_EMO16DATA2 (CAN_MO16_EDATA2)
+
+/** \brief 120C, Message Object Acceptance Mask Register */
+#define CAN_MO16_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001920Cu)
+
+/** Alias (User Manual Name) for CAN_MO16_EDATA3.
+* To use register names with standard convension, please use CAN_MO16_EDATA3.
+*/
+#define CAN_EMO16DATA3 (CAN_MO16_EDATA3)
+
+/** \brief 1210, Message Object Data Register Low */
+#define CAN_MO16_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019210u)
+
+/** Alias (User Manual Name) for CAN_MO16_EDATA4.
+* To use register names with standard convension, please use CAN_MO16_EDATA4.
+*/
+#define CAN_EMO16DATA4 (CAN_MO16_EDATA4)
+
+/** \brief 1214, Message Object Data Register High */
+#define CAN_MO16_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019214u)
+
+/** Alias (User Manual Name) for CAN_MO16_EDATA5.
+* To use register names with standard convension, please use CAN_MO16_EDATA5.
+*/
+#define CAN_EMO16DATA5 (CAN_MO16_EDATA5)
+
+/** \brief 1218, Message Object Arbitration Register */
+#define CAN_MO16_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019218u)
+
+/** Alias (User Manual Name) for CAN_MO16_EDATA6.
+* To use register names with standard convension, please use CAN_MO16_EDATA6.
+*/
+#define CAN_EMO16DATA6 (CAN_MO16_EDATA6)
+
+/** \brief 1200, Message Object Function Control Register */
+#define CAN_MO16_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019200u)
+
+/** Alias (User Manual Name) for CAN_MO16_FCR.
+* To use register names with standard convension, please use CAN_MO16_FCR.
+*/
+#define CAN_MOFCR16 (CAN_MO16_FCR)
+
+/** \brief 1204, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO16_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019204u)
+
+/** Alias (User Manual Name) for CAN_MO16_FGPR.
+* To use register names with standard convension, please use CAN_MO16_FGPR.
+*/
+#define CAN_MOFGPR16 (CAN_MO16_FGPR)
+
+/** \brief 1208, Message Object Interrupt Pointer Register */
+#define CAN_MO16_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019208u)
+
+/** Alias (User Manual Name) for CAN_MO16_IPR.
+* To use register names with standard convension, please use CAN_MO16_IPR.
+*/
+#define CAN_MOIPR16 (CAN_MO16_IPR)
+
+/** \brief 121C, Message Object Control Register */
+#define CAN_MO16_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001921Cu)
+
+/** Alias (User Manual Name) for CAN_MO16_STAT.
+* To use register names with standard convension, please use CAN_MO16_STAT.
+*/
+#define CAN_MOSTAT16 (CAN_MO16_STAT)
+
+/** \brief 254C, Message Object Acceptance Mask Register */
+#define CAN_MO170_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A54Cu)
+
+/** Alias (User Manual Name) for CAN_MO170_AMR.
+* To use register names with standard convension, please use CAN_MO170_AMR.
+*/
+#define CAN_MOAMR170 (CAN_MO170_AMR)
+
+/** \brief 2558, Message Object Arbitration Register */
+#define CAN_MO170_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A558u)
+
+/** Alias (User Manual Name) for CAN_MO170_AR.
+* To use register names with standard convension, please use CAN_MO170_AR.
+*/
+#define CAN_MOAR170 (CAN_MO170_AR)
+
+/** \brief 255C, Message Object Control Register */
+#define CAN_MO170_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A55Cu)
+
+/** Alias (User Manual Name) for CAN_MO170_CTR.
+* To use register names with standard convension, please use CAN_MO170_CTR.
+*/
+#define CAN_MOCTR170 (CAN_MO170_CTR)
+
+/** \brief 2554, Message Object Data Register High */
+#define CAN_MO170_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A554u)
+
+/** Alias (User Manual Name) for CAN_MO170_DATAH.
+* To use register names with standard convension, please use CAN_MO170_DATAH.
+*/
+#define CAN_MODATAH170 (CAN_MO170_DATAH)
+
+/** \brief 2550, Message Object Data Register Low */
+#define CAN_MO170_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A550u)
+
+/** Alias (User Manual Name) for CAN_MO170_DATAL.
+* To use register names with standard convension, please use CAN_MO170_DATAL.
+*/
+#define CAN_MODATAL170 (CAN_MO170_DATAL)
+
+/** \brief 2540, Message Object Function Control Register */
+#define CAN_MO170_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A540u)
+
+/** Alias (User Manual Name) for CAN_MO170_EDATA0.
+* To use register names with standard convension, please use CAN_MO170_EDATA0.
+*/
+#define CAN_EMO170DATA0 (CAN_MO170_EDATA0)
+
+/** \brief 2544, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO170_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A544u)
+
+/** Alias (User Manual Name) for CAN_MO170_EDATA1.
+* To use register names with standard convension, please use CAN_MO170_EDATA1.
+*/
+#define CAN_EMO170DATA1 (CAN_MO170_EDATA1)
+
+/** \brief 2548, Message Object Interrupt Pointer Register */
+#define CAN_MO170_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A548u)
+
+/** Alias (User Manual Name) for CAN_MO170_EDATA2.
+* To use register names with standard convension, please use CAN_MO170_EDATA2.
+*/
+#define CAN_EMO170DATA2 (CAN_MO170_EDATA2)
+
+/** \brief 254C, Message Object Acceptance Mask Register */
+#define CAN_MO170_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A54Cu)
+
+/** Alias (User Manual Name) for CAN_MO170_EDATA3.
+* To use register names with standard convension, please use CAN_MO170_EDATA3.
+*/
+#define CAN_EMO170DATA3 (CAN_MO170_EDATA3)
+
+/** \brief 2550, Message Object Data Register Low */
+#define CAN_MO170_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A550u)
+
+/** Alias (User Manual Name) for CAN_MO170_EDATA4.
+* To use register names with standard convension, please use CAN_MO170_EDATA4.
+*/
+#define CAN_EMO170DATA4 (CAN_MO170_EDATA4)
+
+/** \brief 2554, Message Object Data Register High */
+#define CAN_MO170_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A554u)
+
+/** Alias (User Manual Name) for CAN_MO170_EDATA5.
+* To use register names with standard convension, please use CAN_MO170_EDATA5.
+*/
+#define CAN_EMO170DATA5 (CAN_MO170_EDATA5)
+
+/** \brief 2558, Message Object Arbitration Register */
+#define CAN_MO170_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A558u)
+
+/** Alias (User Manual Name) for CAN_MO170_EDATA6.
+* To use register names with standard convension, please use CAN_MO170_EDATA6.
+*/
+#define CAN_EMO170DATA6 (CAN_MO170_EDATA6)
+
+/** \brief 2540, Message Object Function Control Register */
+#define CAN_MO170_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A540u)
+
+/** Alias (User Manual Name) for CAN_MO170_FCR.
+* To use register names with standard convension, please use CAN_MO170_FCR.
+*/
+#define CAN_MOFCR170 (CAN_MO170_FCR)
+
+/** \brief 2544, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO170_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A544u)
+
+/** Alias (User Manual Name) for CAN_MO170_FGPR.
+* To use register names with standard convension, please use CAN_MO170_FGPR.
+*/
+#define CAN_MOFGPR170 (CAN_MO170_FGPR)
+
+/** \brief 2548, Message Object Interrupt Pointer Register */
+#define CAN_MO170_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A548u)
+
+/** Alias (User Manual Name) for CAN_MO170_IPR.
+* To use register names with standard convension, please use CAN_MO170_IPR.
+*/
+#define CAN_MOIPR170 (CAN_MO170_IPR)
+
+/** \brief 255C, Message Object Control Register */
+#define CAN_MO170_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A55Cu)
+
+/** Alias (User Manual Name) for CAN_MO170_STAT.
+* To use register names with standard convension, please use CAN_MO170_STAT.
+*/
+#define CAN_MOSTAT170 (CAN_MO170_STAT)
+
+/** \brief 256C, Message Object Acceptance Mask Register */
+#define CAN_MO171_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A56Cu)
+
+/** Alias (User Manual Name) for CAN_MO171_AMR.
+* To use register names with standard convension, please use CAN_MO171_AMR.
+*/
+#define CAN_MOAMR171 (CAN_MO171_AMR)
+
+/** \brief 2578, Message Object Arbitration Register */
+#define CAN_MO171_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A578u)
+
+/** Alias (User Manual Name) for CAN_MO171_AR.
+* To use register names with standard convension, please use CAN_MO171_AR.
+*/
+#define CAN_MOAR171 (CAN_MO171_AR)
+
+/** \brief 257C, Message Object Control Register */
+#define CAN_MO171_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A57Cu)
+
+/** Alias (User Manual Name) for CAN_MO171_CTR.
+* To use register names with standard convension, please use CAN_MO171_CTR.
+*/
+#define CAN_MOCTR171 (CAN_MO171_CTR)
+
+/** \brief 2574, Message Object Data Register High */
+#define CAN_MO171_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A574u)
+
+/** Alias (User Manual Name) for CAN_MO171_DATAH.
+* To use register names with standard convension, please use CAN_MO171_DATAH.
+*/
+#define CAN_MODATAH171 (CAN_MO171_DATAH)
+
+/** \brief 2570, Message Object Data Register Low */
+#define CAN_MO171_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A570u)
+
+/** Alias (User Manual Name) for CAN_MO171_DATAL.
+* To use register names with standard convension, please use CAN_MO171_DATAL.
+*/
+#define CAN_MODATAL171 (CAN_MO171_DATAL)
+
+/** \brief 2560, Message Object Function Control Register */
+#define CAN_MO171_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A560u)
+
+/** Alias (User Manual Name) for CAN_MO171_EDATA0.
+* To use register names with standard convension, please use CAN_MO171_EDATA0.
+*/
+#define CAN_EMO171DATA0 (CAN_MO171_EDATA0)
+
+/** \brief 2564, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO171_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A564u)
+
+/** Alias (User Manual Name) for CAN_MO171_EDATA1.
+* To use register names with standard convension, please use CAN_MO171_EDATA1.
+*/
+#define CAN_EMO171DATA1 (CAN_MO171_EDATA1)
+
+/** \brief 2568, Message Object Interrupt Pointer Register */
+#define CAN_MO171_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A568u)
+
+/** Alias (User Manual Name) for CAN_MO171_EDATA2.
+* To use register names with standard convension, please use CAN_MO171_EDATA2.
+*/
+#define CAN_EMO171DATA2 (CAN_MO171_EDATA2)
+
+/** \brief 256C, Message Object Acceptance Mask Register */
+#define CAN_MO171_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A56Cu)
+
+/** Alias (User Manual Name) for CAN_MO171_EDATA3.
+* To use register names with standard convension, please use CAN_MO171_EDATA3.
+*/
+#define CAN_EMO171DATA3 (CAN_MO171_EDATA3)
+
+/** \brief 2570, Message Object Data Register Low */
+#define CAN_MO171_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A570u)
+
+/** Alias (User Manual Name) for CAN_MO171_EDATA4.
+* To use register names with standard convension, please use CAN_MO171_EDATA4.
+*/
+#define CAN_EMO171DATA4 (CAN_MO171_EDATA4)
+
+/** \brief 2574, Message Object Data Register High */
+#define CAN_MO171_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A574u)
+
+/** Alias (User Manual Name) for CAN_MO171_EDATA5.
+* To use register names with standard convension, please use CAN_MO171_EDATA5.
+*/
+#define CAN_EMO171DATA5 (CAN_MO171_EDATA5)
+
+/** \brief 2578, Message Object Arbitration Register */
+#define CAN_MO171_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A578u)
+
+/** Alias (User Manual Name) for CAN_MO171_EDATA6.
+* To use register names with standard convension, please use CAN_MO171_EDATA6.
+*/
+#define CAN_EMO171DATA6 (CAN_MO171_EDATA6)
+
+/** \brief 2560, Message Object Function Control Register */
+#define CAN_MO171_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A560u)
+
+/** Alias (User Manual Name) for CAN_MO171_FCR.
+* To use register names with standard convension, please use CAN_MO171_FCR.
+*/
+#define CAN_MOFCR171 (CAN_MO171_FCR)
+
+/** \brief 2564, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO171_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A564u)
+
+/** Alias (User Manual Name) for CAN_MO171_FGPR.
+* To use register names with standard convension, please use CAN_MO171_FGPR.
+*/
+#define CAN_MOFGPR171 (CAN_MO171_FGPR)
+
+/** \brief 2568, Message Object Interrupt Pointer Register */
+#define CAN_MO171_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A568u)
+
+/** Alias (User Manual Name) for CAN_MO171_IPR.
+* To use register names with standard convension, please use CAN_MO171_IPR.
+*/
+#define CAN_MOIPR171 (CAN_MO171_IPR)
+
+/** \brief 257C, Message Object Control Register */
+#define CAN_MO171_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A57Cu)
+
+/** Alias (User Manual Name) for CAN_MO171_STAT.
+* To use register names with standard convension, please use CAN_MO171_STAT.
+*/
+#define CAN_MOSTAT171 (CAN_MO171_STAT)
+
+/** \brief 258C, Message Object Acceptance Mask Register */
+#define CAN_MO172_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A58Cu)
+
+/** Alias (User Manual Name) for CAN_MO172_AMR.
+* To use register names with standard convension, please use CAN_MO172_AMR.
+*/
+#define CAN_MOAMR172 (CAN_MO172_AMR)
+
+/** \brief 2598, Message Object Arbitration Register */
+#define CAN_MO172_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A598u)
+
+/** Alias (User Manual Name) for CAN_MO172_AR.
+* To use register names with standard convension, please use CAN_MO172_AR.
+*/
+#define CAN_MOAR172 (CAN_MO172_AR)
+
+/** \brief 259C, Message Object Control Register */
+#define CAN_MO172_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A59Cu)
+
+/** Alias (User Manual Name) for CAN_MO172_CTR.
+* To use register names with standard convension, please use CAN_MO172_CTR.
+*/
+#define CAN_MOCTR172 (CAN_MO172_CTR)
+
+/** \brief 2594, Message Object Data Register High */
+#define CAN_MO172_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A594u)
+
+/** Alias (User Manual Name) for CAN_MO172_DATAH.
+* To use register names with standard convension, please use CAN_MO172_DATAH.
+*/
+#define CAN_MODATAH172 (CAN_MO172_DATAH)
+
+/** \brief 2590, Message Object Data Register Low */
+#define CAN_MO172_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A590u)
+
+/** Alias (User Manual Name) for CAN_MO172_DATAL.
+* To use register names with standard convension, please use CAN_MO172_DATAL.
+*/
+#define CAN_MODATAL172 (CAN_MO172_DATAL)
+
+/** \brief 2580, Message Object Function Control Register */
+#define CAN_MO172_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A580u)
+
+/** Alias (User Manual Name) for CAN_MO172_EDATA0.
+* To use register names with standard convension, please use CAN_MO172_EDATA0.
+*/
+#define CAN_EMO172DATA0 (CAN_MO172_EDATA0)
+
+/** \brief 2584, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO172_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A584u)
+
+/** Alias (User Manual Name) for CAN_MO172_EDATA1.
+* To use register names with standard convension, please use CAN_MO172_EDATA1.
+*/
+#define CAN_EMO172DATA1 (CAN_MO172_EDATA1)
+
+/** \brief 2588, Message Object Interrupt Pointer Register */
+#define CAN_MO172_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A588u)
+
+/** Alias (User Manual Name) for CAN_MO172_EDATA2.
+* To use register names with standard convension, please use CAN_MO172_EDATA2.
+*/
+#define CAN_EMO172DATA2 (CAN_MO172_EDATA2)
+
+/** \brief 258C, Message Object Acceptance Mask Register */
+#define CAN_MO172_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A58Cu)
+
+/** Alias (User Manual Name) for CAN_MO172_EDATA3.
+* To use register names with standard convension, please use CAN_MO172_EDATA3.
+*/
+#define CAN_EMO172DATA3 (CAN_MO172_EDATA3)
+
+/** \brief 2590, Message Object Data Register Low */
+#define CAN_MO172_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A590u)
+
+/** Alias (User Manual Name) for CAN_MO172_EDATA4.
+* To use register names with standard convension, please use CAN_MO172_EDATA4.
+*/
+#define CAN_EMO172DATA4 (CAN_MO172_EDATA4)
+
+/** \brief 2594, Message Object Data Register High */
+#define CAN_MO172_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A594u)
+
+/** Alias (User Manual Name) for CAN_MO172_EDATA5.
+* To use register names with standard convension, please use CAN_MO172_EDATA5.
+*/
+#define CAN_EMO172DATA5 (CAN_MO172_EDATA5)
+
+/** \brief 2598, Message Object Arbitration Register */
+#define CAN_MO172_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A598u)
+
+/** Alias (User Manual Name) for CAN_MO172_EDATA6.
+* To use register names with standard convension, please use CAN_MO172_EDATA6.
+*/
+#define CAN_EMO172DATA6 (CAN_MO172_EDATA6)
+
+/** \brief 2580, Message Object Function Control Register */
+#define CAN_MO172_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A580u)
+
+/** Alias (User Manual Name) for CAN_MO172_FCR.
+* To use register names with standard convension, please use CAN_MO172_FCR.
+*/
+#define CAN_MOFCR172 (CAN_MO172_FCR)
+
+/** \brief 2584, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO172_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A584u)
+
+/** Alias (User Manual Name) for CAN_MO172_FGPR.
+* To use register names with standard convension, please use CAN_MO172_FGPR.
+*/
+#define CAN_MOFGPR172 (CAN_MO172_FGPR)
+
+/** \brief 2588, Message Object Interrupt Pointer Register */
+#define CAN_MO172_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A588u)
+
+/** Alias (User Manual Name) for CAN_MO172_IPR.
+* To use register names with standard convension, please use CAN_MO172_IPR.
+*/
+#define CAN_MOIPR172 (CAN_MO172_IPR)
+
+/** \brief 259C, Message Object Control Register */
+#define CAN_MO172_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A59Cu)
+
+/** Alias (User Manual Name) for CAN_MO172_STAT.
+* To use register names with standard convension, please use CAN_MO172_STAT.
+*/
+#define CAN_MOSTAT172 (CAN_MO172_STAT)
+
+/** \brief 25AC, Message Object Acceptance Mask Register */
+#define CAN_MO173_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A5ACu)
+
+/** Alias (User Manual Name) for CAN_MO173_AMR.
+* To use register names with standard convension, please use CAN_MO173_AMR.
+*/
+#define CAN_MOAMR173 (CAN_MO173_AMR)
+
+/** \brief 25B8, Message Object Arbitration Register */
+#define CAN_MO173_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A5B8u)
+
+/** Alias (User Manual Name) for CAN_MO173_AR.
+* To use register names with standard convension, please use CAN_MO173_AR.
+*/
+#define CAN_MOAR173 (CAN_MO173_AR)
+
+/** \brief 25BC, Message Object Control Register */
+#define CAN_MO173_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A5BCu)
+
+/** Alias (User Manual Name) for CAN_MO173_CTR.
+* To use register names with standard convension, please use CAN_MO173_CTR.
+*/
+#define CAN_MOCTR173 (CAN_MO173_CTR)
+
+/** \brief 25B4, Message Object Data Register High */
+#define CAN_MO173_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A5B4u)
+
+/** Alias (User Manual Name) for CAN_MO173_DATAH.
+* To use register names with standard convension, please use CAN_MO173_DATAH.
+*/
+#define CAN_MODATAH173 (CAN_MO173_DATAH)
+
+/** \brief 25B0, Message Object Data Register Low */
+#define CAN_MO173_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A5B0u)
+
+/** Alias (User Manual Name) for CAN_MO173_DATAL.
+* To use register names with standard convension, please use CAN_MO173_DATAL.
+*/
+#define CAN_MODATAL173 (CAN_MO173_DATAL)
+
+/** \brief 25A0, Message Object Function Control Register */
+#define CAN_MO173_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A5A0u)
+
+/** Alias (User Manual Name) for CAN_MO173_EDATA0.
+* To use register names with standard convension, please use CAN_MO173_EDATA0.
+*/
+#define CAN_EMO173DATA0 (CAN_MO173_EDATA0)
+
+/** \brief 25A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO173_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A5A4u)
+
+/** Alias (User Manual Name) for CAN_MO173_EDATA1.
+* To use register names with standard convension, please use CAN_MO173_EDATA1.
+*/
+#define CAN_EMO173DATA1 (CAN_MO173_EDATA1)
+
+/** \brief 25A8, Message Object Interrupt Pointer Register */
+#define CAN_MO173_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A5A8u)
+
+/** Alias (User Manual Name) for CAN_MO173_EDATA2.
+* To use register names with standard convension, please use CAN_MO173_EDATA2.
+*/
+#define CAN_EMO173DATA2 (CAN_MO173_EDATA2)
+
+/** \brief 25AC, Message Object Acceptance Mask Register */
+#define CAN_MO173_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A5ACu)
+
+/** Alias (User Manual Name) for CAN_MO173_EDATA3.
+* To use register names with standard convension, please use CAN_MO173_EDATA3.
+*/
+#define CAN_EMO173DATA3 (CAN_MO173_EDATA3)
+
+/** \brief 25B0, Message Object Data Register Low */
+#define CAN_MO173_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A5B0u)
+
+/** Alias (User Manual Name) for CAN_MO173_EDATA4.
+* To use register names with standard convension, please use CAN_MO173_EDATA4.
+*/
+#define CAN_EMO173DATA4 (CAN_MO173_EDATA4)
+
+/** \brief 25B4, Message Object Data Register High */
+#define CAN_MO173_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A5B4u)
+
+/** Alias (User Manual Name) for CAN_MO173_EDATA5.
+* To use register names with standard convension, please use CAN_MO173_EDATA5.
+*/
+#define CAN_EMO173DATA5 (CAN_MO173_EDATA5)
+
+/** \brief 25B8, Message Object Arbitration Register */
+#define CAN_MO173_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A5B8u)
+
+/** Alias (User Manual Name) for CAN_MO173_EDATA6.
+* To use register names with standard convension, please use CAN_MO173_EDATA6.
+*/
+#define CAN_EMO173DATA6 (CAN_MO173_EDATA6)
+
+/** \brief 25A0, Message Object Function Control Register */
+#define CAN_MO173_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A5A0u)
+
+/** Alias (User Manual Name) for CAN_MO173_FCR.
+* To use register names with standard convension, please use CAN_MO173_FCR.
+*/
+#define CAN_MOFCR173 (CAN_MO173_FCR)
+
+/** \brief 25A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO173_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A5A4u)
+
+/** Alias (User Manual Name) for CAN_MO173_FGPR.
+* To use register names with standard convension, please use CAN_MO173_FGPR.
+*/
+#define CAN_MOFGPR173 (CAN_MO173_FGPR)
+
+/** \brief 25A8, Message Object Interrupt Pointer Register */
+#define CAN_MO173_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A5A8u)
+
+/** Alias (User Manual Name) for CAN_MO173_IPR.
+* To use register names with standard convension, please use CAN_MO173_IPR.
+*/
+#define CAN_MOIPR173 (CAN_MO173_IPR)
+
+/** \brief 25BC, Message Object Control Register */
+#define CAN_MO173_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A5BCu)
+
+/** Alias (User Manual Name) for CAN_MO173_STAT.
+* To use register names with standard convension, please use CAN_MO173_STAT.
+*/
+#define CAN_MOSTAT173 (CAN_MO173_STAT)
+
+/** \brief 25CC, Message Object Acceptance Mask Register */
+#define CAN_MO174_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A5CCu)
+
+/** Alias (User Manual Name) for CAN_MO174_AMR.
+* To use register names with standard convension, please use CAN_MO174_AMR.
+*/
+#define CAN_MOAMR174 (CAN_MO174_AMR)
+
+/** \brief 25D8, Message Object Arbitration Register */
+#define CAN_MO174_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A5D8u)
+
+/** Alias (User Manual Name) for CAN_MO174_AR.
+* To use register names with standard convension, please use CAN_MO174_AR.
+*/
+#define CAN_MOAR174 (CAN_MO174_AR)
+
+/** \brief 25DC, Message Object Control Register */
+#define CAN_MO174_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A5DCu)
+
+/** Alias (User Manual Name) for CAN_MO174_CTR.
+* To use register names with standard convension, please use CAN_MO174_CTR.
+*/
+#define CAN_MOCTR174 (CAN_MO174_CTR)
+
+/** \brief 25D4, Message Object Data Register High */
+#define CAN_MO174_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A5D4u)
+
+/** Alias (User Manual Name) for CAN_MO174_DATAH.
+* To use register names with standard convension, please use CAN_MO174_DATAH.
+*/
+#define CAN_MODATAH174 (CAN_MO174_DATAH)
+
+/** \brief 25D0, Message Object Data Register Low */
+#define CAN_MO174_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A5D0u)
+
+/** Alias (User Manual Name) for CAN_MO174_DATAL.
+* To use register names with standard convension, please use CAN_MO174_DATAL.
+*/
+#define CAN_MODATAL174 (CAN_MO174_DATAL)
+
+/** \brief 25C0, Message Object Function Control Register */
+#define CAN_MO174_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A5C0u)
+
+/** Alias (User Manual Name) for CAN_MO174_EDATA0.
+* To use register names with standard convension, please use CAN_MO174_EDATA0.
+*/
+#define CAN_EMO174DATA0 (CAN_MO174_EDATA0)
+
+/** \brief 25C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO174_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A5C4u)
+
+/** Alias (User Manual Name) for CAN_MO174_EDATA1.
+* To use register names with standard convension, please use CAN_MO174_EDATA1.
+*/
+#define CAN_EMO174DATA1 (CAN_MO174_EDATA1)
+
+/** \brief 25C8, Message Object Interrupt Pointer Register */
+#define CAN_MO174_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A5C8u)
+
+/** Alias (User Manual Name) for CAN_MO174_EDATA2.
+* To use register names with standard convension, please use CAN_MO174_EDATA2.
+*/
+#define CAN_EMO174DATA2 (CAN_MO174_EDATA2)
+
+/** \brief 25CC, Message Object Acceptance Mask Register */
+#define CAN_MO174_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A5CCu)
+
+/** Alias (User Manual Name) for CAN_MO174_EDATA3.
+* To use register names with standard convension, please use CAN_MO174_EDATA3.
+*/
+#define CAN_EMO174DATA3 (CAN_MO174_EDATA3)
+
+/** \brief 25D0, Message Object Data Register Low */
+#define CAN_MO174_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A5D0u)
+
+/** Alias (User Manual Name) for CAN_MO174_EDATA4.
+* To use register names with standard convension, please use CAN_MO174_EDATA4.
+*/
+#define CAN_EMO174DATA4 (CAN_MO174_EDATA4)
+
+/** \brief 25D4, Message Object Data Register High */
+#define CAN_MO174_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A5D4u)
+
+/** Alias (User Manual Name) for CAN_MO174_EDATA5.
+* To use register names with standard convension, please use CAN_MO174_EDATA5.
+*/
+#define CAN_EMO174DATA5 (CAN_MO174_EDATA5)
+
+/** \brief 25D8, Message Object Arbitration Register */
+#define CAN_MO174_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A5D8u)
+
+/** Alias (User Manual Name) for CAN_MO174_EDATA6.
+* To use register names with standard convension, please use CAN_MO174_EDATA6.
+*/
+#define CAN_EMO174DATA6 (CAN_MO174_EDATA6)
+
+/** \brief 25C0, Message Object Function Control Register */
+#define CAN_MO174_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A5C0u)
+
+/** Alias (User Manual Name) for CAN_MO174_FCR.
+* To use register names with standard convension, please use CAN_MO174_FCR.
+*/
+#define CAN_MOFCR174 (CAN_MO174_FCR)
+
+/** \brief 25C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO174_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A5C4u)
+
+/** Alias (User Manual Name) for CAN_MO174_FGPR.
+* To use register names with standard convension, please use CAN_MO174_FGPR.
+*/
+#define CAN_MOFGPR174 (CAN_MO174_FGPR)
+
+/** \brief 25C8, Message Object Interrupt Pointer Register */
+#define CAN_MO174_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A5C8u)
+
+/** Alias (User Manual Name) for CAN_MO174_IPR.
+* To use register names with standard convension, please use CAN_MO174_IPR.
+*/
+#define CAN_MOIPR174 (CAN_MO174_IPR)
+
+/** \brief 25DC, Message Object Control Register */
+#define CAN_MO174_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A5DCu)
+
+/** Alias (User Manual Name) for CAN_MO174_STAT.
+* To use register names with standard convension, please use CAN_MO174_STAT.
+*/
+#define CAN_MOSTAT174 (CAN_MO174_STAT)
+
+/** \brief 25EC, Message Object Acceptance Mask Register */
+#define CAN_MO175_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A5ECu)
+
+/** Alias (User Manual Name) for CAN_MO175_AMR.
+* To use register names with standard convension, please use CAN_MO175_AMR.
+*/
+#define CAN_MOAMR175 (CAN_MO175_AMR)
+
+/** \brief 25F8, Message Object Arbitration Register */
+#define CAN_MO175_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A5F8u)
+
+/** Alias (User Manual Name) for CAN_MO175_AR.
+* To use register names with standard convension, please use CAN_MO175_AR.
+*/
+#define CAN_MOAR175 (CAN_MO175_AR)
+
+/** \brief 25FC, Message Object Control Register */
+#define CAN_MO175_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A5FCu)
+
+/** Alias (User Manual Name) for CAN_MO175_CTR.
+* To use register names with standard convension, please use CAN_MO175_CTR.
+*/
+#define CAN_MOCTR175 (CAN_MO175_CTR)
+
+/** \brief 25F4, Message Object Data Register High */
+#define CAN_MO175_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A5F4u)
+
+/** Alias (User Manual Name) for CAN_MO175_DATAH.
+* To use register names with standard convension, please use CAN_MO175_DATAH.
+*/
+#define CAN_MODATAH175 (CAN_MO175_DATAH)
+
+/** \brief 25F0, Message Object Data Register Low */
+#define CAN_MO175_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A5F0u)
+
+/** Alias (User Manual Name) for CAN_MO175_DATAL.
+* To use register names with standard convension, please use CAN_MO175_DATAL.
+*/
+#define CAN_MODATAL175 (CAN_MO175_DATAL)
+
+/** \brief 25E0, Message Object Function Control Register */
+#define CAN_MO175_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A5E0u)
+
+/** Alias (User Manual Name) for CAN_MO175_EDATA0.
+* To use register names with standard convension, please use CAN_MO175_EDATA0.
+*/
+#define CAN_EMO175DATA0 (CAN_MO175_EDATA0)
+
+/** \brief 25E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO175_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A5E4u)
+
+/** Alias (User Manual Name) for CAN_MO175_EDATA1.
+* To use register names with standard convension, please use CAN_MO175_EDATA1.
+*/
+#define CAN_EMO175DATA1 (CAN_MO175_EDATA1)
+
+/** \brief 25E8, Message Object Interrupt Pointer Register */
+#define CAN_MO175_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A5E8u)
+
+/** Alias (User Manual Name) for CAN_MO175_EDATA2.
+* To use register names with standard convension, please use CAN_MO175_EDATA2.
+*/
+#define CAN_EMO175DATA2 (CAN_MO175_EDATA2)
+
+/** \brief 25EC, Message Object Acceptance Mask Register */
+#define CAN_MO175_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A5ECu)
+
+/** Alias (User Manual Name) for CAN_MO175_EDATA3.
+* To use register names with standard convension, please use CAN_MO175_EDATA3.
+*/
+#define CAN_EMO175DATA3 (CAN_MO175_EDATA3)
+
+/** \brief 25F0, Message Object Data Register Low */
+#define CAN_MO175_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A5F0u)
+
+/** Alias (User Manual Name) for CAN_MO175_EDATA4.
+* To use register names with standard convension, please use CAN_MO175_EDATA4.
+*/
+#define CAN_EMO175DATA4 (CAN_MO175_EDATA4)
+
+/** \brief 25F4, Message Object Data Register High */
+#define CAN_MO175_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A5F4u)
+
+/** Alias (User Manual Name) for CAN_MO175_EDATA5.
+* To use register names with standard convension, please use CAN_MO175_EDATA5.
+*/
+#define CAN_EMO175DATA5 (CAN_MO175_EDATA5)
+
+/** \brief 25F8, Message Object Arbitration Register */
+#define CAN_MO175_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A5F8u)
+
+/** Alias (User Manual Name) for CAN_MO175_EDATA6.
+* To use register names with standard convension, please use CAN_MO175_EDATA6.
+*/
+#define CAN_EMO175DATA6 (CAN_MO175_EDATA6)
+
+/** \brief 25E0, Message Object Function Control Register */
+#define CAN_MO175_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A5E0u)
+
+/** Alias (User Manual Name) for CAN_MO175_FCR.
+* To use register names with standard convension, please use CAN_MO175_FCR.
+*/
+#define CAN_MOFCR175 (CAN_MO175_FCR)
+
+/** \brief 25E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO175_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A5E4u)
+
+/** Alias (User Manual Name) for CAN_MO175_FGPR.
+* To use register names with standard convension, please use CAN_MO175_FGPR.
+*/
+#define CAN_MOFGPR175 (CAN_MO175_FGPR)
+
+/** \brief 25E8, Message Object Interrupt Pointer Register */
+#define CAN_MO175_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A5E8u)
+
+/** Alias (User Manual Name) for CAN_MO175_IPR.
+* To use register names with standard convension, please use CAN_MO175_IPR.
+*/
+#define CAN_MOIPR175 (CAN_MO175_IPR)
+
+/** \brief 25FC, Message Object Control Register */
+#define CAN_MO175_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A5FCu)
+
+/** Alias (User Manual Name) for CAN_MO175_STAT.
+* To use register names with standard convension, please use CAN_MO175_STAT.
+*/
+#define CAN_MOSTAT175 (CAN_MO175_STAT)
+
+/** \brief 260C, Message Object Acceptance Mask Register */
+#define CAN_MO176_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A60Cu)
+
+/** Alias (User Manual Name) for CAN_MO176_AMR.
+* To use register names with standard convension, please use CAN_MO176_AMR.
+*/
+#define CAN_MOAMR176 (CAN_MO176_AMR)
+
+/** \brief 2618, Message Object Arbitration Register */
+#define CAN_MO176_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A618u)
+
+/** Alias (User Manual Name) for CAN_MO176_AR.
+* To use register names with standard convension, please use CAN_MO176_AR.
+*/
+#define CAN_MOAR176 (CAN_MO176_AR)
+
+/** \brief 261C, Message Object Control Register */
+#define CAN_MO176_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A61Cu)
+
+/** Alias (User Manual Name) for CAN_MO176_CTR.
+* To use register names with standard convension, please use CAN_MO176_CTR.
+*/
+#define CAN_MOCTR176 (CAN_MO176_CTR)
+
+/** \brief 2614, Message Object Data Register High */
+#define CAN_MO176_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A614u)
+
+/** Alias (User Manual Name) for CAN_MO176_DATAH.
+* To use register names with standard convension, please use CAN_MO176_DATAH.
+*/
+#define CAN_MODATAH176 (CAN_MO176_DATAH)
+
+/** \brief 2610, Message Object Data Register Low */
+#define CAN_MO176_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A610u)
+
+/** Alias (User Manual Name) for CAN_MO176_DATAL.
+* To use register names with standard convension, please use CAN_MO176_DATAL.
+*/
+#define CAN_MODATAL176 (CAN_MO176_DATAL)
+
+/** \brief 2600, Message Object Function Control Register */
+#define CAN_MO176_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A600u)
+
+/** Alias (User Manual Name) for CAN_MO176_EDATA0.
+* To use register names with standard convension, please use CAN_MO176_EDATA0.
+*/
+#define CAN_EMO176DATA0 (CAN_MO176_EDATA0)
+
+/** \brief 2604, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO176_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A604u)
+
+/** Alias (User Manual Name) for CAN_MO176_EDATA1.
+* To use register names with standard convension, please use CAN_MO176_EDATA1.
+*/
+#define CAN_EMO176DATA1 (CAN_MO176_EDATA1)
+
+/** \brief 2608, Message Object Interrupt Pointer Register */
+#define CAN_MO176_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A608u)
+
+/** Alias (User Manual Name) for CAN_MO176_EDATA2.
+* To use register names with standard convension, please use CAN_MO176_EDATA2.
+*/
+#define CAN_EMO176DATA2 (CAN_MO176_EDATA2)
+
+/** \brief 260C, Message Object Acceptance Mask Register */
+#define CAN_MO176_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A60Cu)
+
+/** Alias (User Manual Name) for CAN_MO176_EDATA3.
+* To use register names with standard convension, please use CAN_MO176_EDATA3.
+*/
+#define CAN_EMO176DATA3 (CAN_MO176_EDATA3)
+
+/** \brief 2610, Message Object Data Register Low */
+#define CAN_MO176_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A610u)
+
+/** Alias (User Manual Name) for CAN_MO176_EDATA4.
+* To use register names with standard convension, please use CAN_MO176_EDATA4.
+*/
+#define CAN_EMO176DATA4 (CAN_MO176_EDATA4)
+
+/** \brief 2614, Message Object Data Register High */
+#define CAN_MO176_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A614u)
+
+/** Alias (User Manual Name) for CAN_MO176_EDATA5.
+* To use register names with standard convension, please use CAN_MO176_EDATA5.
+*/
+#define CAN_EMO176DATA5 (CAN_MO176_EDATA5)
+
+/** \brief 2618, Message Object Arbitration Register */
+#define CAN_MO176_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A618u)
+
+/** Alias (User Manual Name) for CAN_MO176_EDATA6.
+* To use register names with standard convension, please use CAN_MO176_EDATA6.
+*/
+#define CAN_EMO176DATA6 (CAN_MO176_EDATA6)
+
+/** \brief 2600, Message Object Function Control Register */
+#define CAN_MO176_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A600u)
+
+/** Alias (User Manual Name) for CAN_MO176_FCR.
+* To use register names with standard convension, please use CAN_MO176_FCR.
+*/
+#define CAN_MOFCR176 (CAN_MO176_FCR)
+
+/** \brief 2604, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO176_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A604u)
+
+/** Alias (User Manual Name) for CAN_MO176_FGPR.
+* To use register names with standard convension, please use CAN_MO176_FGPR.
+*/
+#define CAN_MOFGPR176 (CAN_MO176_FGPR)
+
+/** \brief 2608, Message Object Interrupt Pointer Register */
+#define CAN_MO176_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A608u)
+
+/** Alias (User Manual Name) for CAN_MO176_IPR.
+* To use register names with standard convension, please use CAN_MO176_IPR.
+*/
+#define CAN_MOIPR176 (CAN_MO176_IPR)
+
+/** \brief 261C, Message Object Control Register */
+#define CAN_MO176_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A61Cu)
+
+/** Alias (User Manual Name) for CAN_MO176_STAT.
+* To use register names with standard convension, please use CAN_MO176_STAT.
+*/
+#define CAN_MOSTAT176 (CAN_MO176_STAT)
+
+/** \brief 262C, Message Object Acceptance Mask Register */
+#define CAN_MO177_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A62Cu)
+
+/** Alias (User Manual Name) for CAN_MO177_AMR.
+* To use register names with standard convension, please use CAN_MO177_AMR.
+*/
+#define CAN_MOAMR177 (CAN_MO177_AMR)
+
+/** \brief 2638, Message Object Arbitration Register */
+#define CAN_MO177_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A638u)
+
+/** Alias (User Manual Name) for CAN_MO177_AR.
+* To use register names with standard convension, please use CAN_MO177_AR.
+*/
+#define CAN_MOAR177 (CAN_MO177_AR)
+
+/** \brief 263C, Message Object Control Register */
+#define CAN_MO177_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A63Cu)
+
+/** Alias (User Manual Name) for CAN_MO177_CTR.
+* To use register names with standard convension, please use CAN_MO177_CTR.
+*/
+#define CAN_MOCTR177 (CAN_MO177_CTR)
+
+/** \brief 2634, Message Object Data Register High */
+#define CAN_MO177_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A634u)
+
+/** Alias (User Manual Name) for CAN_MO177_DATAH.
+* To use register names with standard convension, please use CAN_MO177_DATAH.
+*/
+#define CAN_MODATAH177 (CAN_MO177_DATAH)
+
+/** \brief 2630, Message Object Data Register Low */
+#define CAN_MO177_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A630u)
+
+/** Alias (User Manual Name) for CAN_MO177_DATAL.
+* To use register names with standard convension, please use CAN_MO177_DATAL.
+*/
+#define CAN_MODATAL177 (CAN_MO177_DATAL)
+
+/** \brief 2620, Message Object Function Control Register */
+#define CAN_MO177_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A620u)
+
+/** Alias (User Manual Name) for CAN_MO177_EDATA0.
+* To use register names with standard convension, please use CAN_MO177_EDATA0.
+*/
+#define CAN_EMO177DATA0 (CAN_MO177_EDATA0)
+
+/** \brief 2624, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO177_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A624u)
+
+/** Alias (User Manual Name) for CAN_MO177_EDATA1.
+* To use register names with standard convension, please use CAN_MO177_EDATA1.
+*/
+#define CAN_EMO177DATA1 (CAN_MO177_EDATA1)
+
+/** \brief 2628, Message Object Interrupt Pointer Register */
+#define CAN_MO177_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A628u)
+
+/** Alias (User Manual Name) for CAN_MO177_EDATA2.
+* To use register names with standard convension, please use CAN_MO177_EDATA2.
+*/
+#define CAN_EMO177DATA2 (CAN_MO177_EDATA2)
+
+/** \brief 262C, Message Object Acceptance Mask Register */
+#define CAN_MO177_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A62Cu)
+
+/** Alias (User Manual Name) for CAN_MO177_EDATA3.
+* To use register names with standard convension, please use CAN_MO177_EDATA3.
+*/
+#define CAN_EMO177DATA3 (CAN_MO177_EDATA3)
+
+/** \brief 2630, Message Object Data Register Low */
+#define CAN_MO177_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A630u)
+
+/** Alias (User Manual Name) for CAN_MO177_EDATA4.
+* To use register names with standard convension, please use CAN_MO177_EDATA4.
+*/
+#define CAN_EMO177DATA4 (CAN_MO177_EDATA4)
+
+/** \brief 2634, Message Object Data Register High */
+#define CAN_MO177_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A634u)
+
+/** Alias (User Manual Name) for CAN_MO177_EDATA5.
+* To use register names with standard convension, please use CAN_MO177_EDATA5.
+*/
+#define CAN_EMO177DATA5 (CAN_MO177_EDATA5)
+
+/** \brief 2638, Message Object Arbitration Register */
+#define CAN_MO177_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A638u)
+
+/** Alias (User Manual Name) for CAN_MO177_EDATA6.
+* To use register names with standard convension, please use CAN_MO177_EDATA6.
+*/
+#define CAN_EMO177DATA6 (CAN_MO177_EDATA6)
+
+/** \brief 2620, Message Object Function Control Register */
+#define CAN_MO177_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A620u)
+
+/** Alias (User Manual Name) for CAN_MO177_FCR.
+* To use register names with standard convension, please use CAN_MO177_FCR.
+*/
+#define CAN_MOFCR177 (CAN_MO177_FCR)
+
+/** \brief 2624, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO177_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A624u)
+
+/** Alias (User Manual Name) for CAN_MO177_FGPR.
+* To use register names with standard convension, please use CAN_MO177_FGPR.
+*/
+#define CAN_MOFGPR177 (CAN_MO177_FGPR)
+
+/** \brief 2628, Message Object Interrupt Pointer Register */
+#define CAN_MO177_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A628u)
+
+/** Alias (User Manual Name) for CAN_MO177_IPR.
+* To use register names with standard convension, please use CAN_MO177_IPR.
+*/
+#define CAN_MOIPR177 (CAN_MO177_IPR)
+
+/** \brief 263C, Message Object Control Register */
+#define CAN_MO177_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A63Cu)
+
+/** Alias (User Manual Name) for CAN_MO177_STAT.
+* To use register names with standard convension, please use CAN_MO177_STAT.
+*/
+#define CAN_MOSTAT177 (CAN_MO177_STAT)
+
+/** \brief 264C, Message Object Acceptance Mask Register */
+#define CAN_MO178_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A64Cu)
+
+/** Alias (User Manual Name) for CAN_MO178_AMR.
+* To use register names with standard convension, please use CAN_MO178_AMR.
+*/
+#define CAN_MOAMR178 (CAN_MO178_AMR)
+
+/** \brief 2658, Message Object Arbitration Register */
+#define CAN_MO178_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A658u)
+
+/** Alias (User Manual Name) for CAN_MO178_AR.
+* To use register names with standard convension, please use CAN_MO178_AR.
+*/
+#define CAN_MOAR178 (CAN_MO178_AR)
+
+/** \brief 265C, Message Object Control Register */
+#define CAN_MO178_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A65Cu)
+
+/** Alias (User Manual Name) for CAN_MO178_CTR.
+* To use register names with standard convension, please use CAN_MO178_CTR.
+*/
+#define CAN_MOCTR178 (CAN_MO178_CTR)
+
+/** \brief 2654, Message Object Data Register High */
+#define CAN_MO178_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A654u)
+
+/** Alias (User Manual Name) for CAN_MO178_DATAH.
+* To use register names with standard convension, please use CAN_MO178_DATAH.
+*/
+#define CAN_MODATAH178 (CAN_MO178_DATAH)
+
+/** \brief 2650, Message Object Data Register Low */
+#define CAN_MO178_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A650u)
+
+/** Alias (User Manual Name) for CAN_MO178_DATAL.
+* To use register names with standard convension, please use CAN_MO178_DATAL.
+*/
+#define CAN_MODATAL178 (CAN_MO178_DATAL)
+
+/** \brief 2640, Message Object Function Control Register */
+#define CAN_MO178_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A640u)
+
+/** Alias (User Manual Name) for CAN_MO178_EDATA0.
+* To use register names with standard convension, please use CAN_MO178_EDATA0.
+*/
+#define CAN_EMO178DATA0 (CAN_MO178_EDATA0)
+
+/** \brief 2644, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO178_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A644u)
+
+/** Alias (User Manual Name) for CAN_MO178_EDATA1.
+* To use register names with standard convension, please use CAN_MO178_EDATA1.
+*/
+#define CAN_EMO178DATA1 (CAN_MO178_EDATA1)
+
+/** \brief 2648, Message Object Interrupt Pointer Register */
+#define CAN_MO178_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A648u)
+
+/** Alias (User Manual Name) for CAN_MO178_EDATA2.
+* To use register names with standard convension, please use CAN_MO178_EDATA2.
+*/
+#define CAN_EMO178DATA2 (CAN_MO178_EDATA2)
+
+/** \brief 264C, Message Object Acceptance Mask Register */
+#define CAN_MO178_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A64Cu)
+
+/** Alias (User Manual Name) for CAN_MO178_EDATA3.
+* To use register names with standard convension, please use CAN_MO178_EDATA3.
+*/
+#define CAN_EMO178DATA3 (CAN_MO178_EDATA3)
+
+/** \brief 2650, Message Object Data Register Low */
+#define CAN_MO178_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A650u)
+
+/** Alias (User Manual Name) for CAN_MO178_EDATA4.
+* To use register names with standard convension, please use CAN_MO178_EDATA4.
+*/
+#define CAN_EMO178DATA4 (CAN_MO178_EDATA4)
+
+/** \brief 2654, Message Object Data Register High */
+#define CAN_MO178_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A654u)
+
+/** Alias (User Manual Name) for CAN_MO178_EDATA5.
+* To use register names with standard convension, please use CAN_MO178_EDATA5.
+*/
+#define CAN_EMO178DATA5 (CAN_MO178_EDATA5)
+
+/** \brief 2658, Message Object Arbitration Register */
+#define CAN_MO178_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A658u)
+
+/** Alias (User Manual Name) for CAN_MO178_EDATA6.
+* To use register names with standard convension, please use CAN_MO178_EDATA6.
+*/
+#define CAN_EMO178DATA6 (CAN_MO178_EDATA6)
+
+/** \brief 2640, Message Object Function Control Register */
+#define CAN_MO178_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A640u)
+
+/** Alias (User Manual Name) for CAN_MO178_FCR.
+* To use register names with standard convension, please use CAN_MO178_FCR.
+*/
+#define CAN_MOFCR178 (CAN_MO178_FCR)
+
+/** \brief 2644, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO178_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A644u)
+
+/** Alias (User Manual Name) for CAN_MO178_FGPR.
+* To use register names with standard convension, please use CAN_MO178_FGPR.
+*/
+#define CAN_MOFGPR178 (CAN_MO178_FGPR)
+
+/** \brief 2648, Message Object Interrupt Pointer Register */
+#define CAN_MO178_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A648u)
+
+/** Alias (User Manual Name) for CAN_MO178_IPR.
+* To use register names with standard convension, please use CAN_MO178_IPR.
+*/
+#define CAN_MOIPR178 (CAN_MO178_IPR)
+
+/** \brief 265C, Message Object Control Register */
+#define CAN_MO178_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A65Cu)
+
+/** Alias (User Manual Name) for CAN_MO178_STAT.
+* To use register names with standard convension, please use CAN_MO178_STAT.
+*/
+#define CAN_MOSTAT178 (CAN_MO178_STAT)
+
+/** \brief 266C, Message Object Acceptance Mask Register */
+#define CAN_MO179_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A66Cu)
+
+/** Alias (User Manual Name) for CAN_MO179_AMR.
+* To use register names with standard convension, please use CAN_MO179_AMR.
+*/
+#define CAN_MOAMR179 (CAN_MO179_AMR)
+
+/** \brief 2678, Message Object Arbitration Register */
+#define CAN_MO179_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A678u)
+
+/** Alias (User Manual Name) for CAN_MO179_AR.
+* To use register names with standard convension, please use CAN_MO179_AR.
+*/
+#define CAN_MOAR179 (CAN_MO179_AR)
+
+/** \brief 267C, Message Object Control Register */
+#define CAN_MO179_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A67Cu)
+
+/** Alias (User Manual Name) for CAN_MO179_CTR.
+* To use register names with standard convension, please use CAN_MO179_CTR.
+*/
+#define CAN_MOCTR179 (CAN_MO179_CTR)
+
+/** \brief 2674, Message Object Data Register High */
+#define CAN_MO179_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A674u)
+
+/** Alias (User Manual Name) for CAN_MO179_DATAH.
+* To use register names with standard convension, please use CAN_MO179_DATAH.
+*/
+#define CAN_MODATAH179 (CAN_MO179_DATAH)
+
+/** \brief 2670, Message Object Data Register Low */
+#define CAN_MO179_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A670u)
+
+/** Alias (User Manual Name) for CAN_MO179_DATAL.
+* To use register names with standard convension, please use CAN_MO179_DATAL.
+*/
+#define CAN_MODATAL179 (CAN_MO179_DATAL)
+
+/** \brief 2660, Message Object Function Control Register */
+#define CAN_MO179_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A660u)
+
+/** Alias (User Manual Name) for CAN_MO179_EDATA0.
+* To use register names with standard convension, please use CAN_MO179_EDATA0.
+*/
+#define CAN_EMO179DATA0 (CAN_MO179_EDATA0)
+
+/** \brief 2664, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO179_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A664u)
+
+/** Alias (User Manual Name) for CAN_MO179_EDATA1.
+* To use register names with standard convension, please use CAN_MO179_EDATA1.
+*/
+#define CAN_EMO179DATA1 (CAN_MO179_EDATA1)
+
+/** \brief 2668, Message Object Interrupt Pointer Register */
+#define CAN_MO179_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A668u)
+
+/** Alias (User Manual Name) for CAN_MO179_EDATA2.
+* To use register names with standard convension, please use CAN_MO179_EDATA2.
+*/
+#define CAN_EMO179DATA2 (CAN_MO179_EDATA2)
+
+/** \brief 266C, Message Object Acceptance Mask Register */
+#define CAN_MO179_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A66Cu)
+
+/** Alias (User Manual Name) for CAN_MO179_EDATA3.
+* To use register names with standard convension, please use CAN_MO179_EDATA3.
+*/
+#define CAN_EMO179DATA3 (CAN_MO179_EDATA3)
+
+/** \brief 2670, Message Object Data Register Low */
+#define CAN_MO179_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A670u)
+
+/** Alias (User Manual Name) for CAN_MO179_EDATA4.
+* To use register names with standard convension, please use CAN_MO179_EDATA4.
+*/
+#define CAN_EMO179DATA4 (CAN_MO179_EDATA4)
+
+/** \brief 2674, Message Object Data Register High */
+#define CAN_MO179_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A674u)
+
+/** Alias (User Manual Name) for CAN_MO179_EDATA5.
+* To use register names with standard convension, please use CAN_MO179_EDATA5.
+*/
+#define CAN_EMO179DATA5 (CAN_MO179_EDATA5)
+
+/** \brief 2678, Message Object Arbitration Register */
+#define CAN_MO179_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A678u)
+
+/** Alias (User Manual Name) for CAN_MO179_EDATA6.
+* To use register names with standard convension, please use CAN_MO179_EDATA6.
+*/
+#define CAN_EMO179DATA6 (CAN_MO179_EDATA6)
+
+/** \brief 2660, Message Object Function Control Register */
+#define CAN_MO179_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A660u)
+
+/** Alias (User Manual Name) for CAN_MO179_FCR.
+* To use register names with standard convension, please use CAN_MO179_FCR.
+*/
+#define CAN_MOFCR179 (CAN_MO179_FCR)
+
+/** \brief 2664, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO179_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A664u)
+
+/** Alias (User Manual Name) for CAN_MO179_FGPR.
+* To use register names with standard convension, please use CAN_MO179_FGPR.
+*/
+#define CAN_MOFGPR179 (CAN_MO179_FGPR)
+
+/** \brief 2668, Message Object Interrupt Pointer Register */
+#define CAN_MO179_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A668u)
+
+/** Alias (User Manual Name) for CAN_MO179_IPR.
+* To use register names with standard convension, please use CAN_MO179_IPR.
+*/
+#define CAN_MOIPR179 (CAN_MO179_IPR)
+
+/** \brief 267C, Message Object Control Register */
+#define CAN_MO179_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A67Cu)
+
+/** Alias (User Manual Name) for CAN_MO179_STAT.
+* To use register names with standard convension, please use CAN_MO179_STAT.
+*/
+#define CAN_MOSTAT179 (CAN_MO179_STAT)
+
+/** \brief 122C, Message Object Acceptance Mask Register */
+#define CAN_MO17_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001922Cu)
+
+/** Alias (User Manual Name) for CAN_MO17_AMR.
+* To use register names with standard convension, please use CAN_MO17_AMR.
+*/
+#define CAN_MOAMR17 (CAN_MO17_AMR)
+
+/** \brief 1238, Message Object Arbitration Register */
+#define CAN_MO17_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019238u)
+
+/** Alias (User Manual Name) for CAN_MO17_AR.
+* To use register names with standard convension, please use CAN_MO17_AR.
+*/
+#define CAN_MOAR17 (CAN_MO17_AR)
+
+/** \brief 123C, Message Object Control Register */
+#define CAN_MO17_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001923Cu)
+
+/** Alias (User Manual Name) for CAN_MO17_CTR.
+* To use register names with standard convension, please use CAN_MO17_CTR.
+*/
+#define CAN_MOCTR17 (CAN_MO17_CTR)
+
+/** \brief 1234, Message Object Data Register High */
+#define CAN_MO17_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019234u)
+
+/** Alias (User Manual Name) for CAN_MO17_DATAH.
+* To use register names with standard convension, please use CAN_MO17_DATAH.
+*/
+#define CAN_MODATAH17 (CAN_MO17_DATAH)
+
+/** \brief 1230, Message Object Data Register Low */
+#define CAN_MO17_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019230u)
+
+/** Alias (User Manual Name) for CAN_MO17_DATAL.
+* To use register names with standard convension, please use CAN_MO17_DATAL.
+*/
+#define CAN_MODATAL17 (CAN_MO17_DATAL)
+
+/** \brief 1220, Message Object Function Control Register */
+#define CAN_MO17_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019220u)
+
+/** Alias (User Manual Name) for CAN_MO17_EDATA0.
+* To use register names with standard convension, please use CAN_MO17_EDATA0.
+*/
+#define CAN_EMO17DATA0 (CAN_MO17_EDATA0)
+
+/** \brief 1224, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO17_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019224u)
+
+/** Alias (User Manual Name) for CAN_MO17_EDATA1.
+* To use register names with standard convension, please use CAN_MO17_EDATA1.
+*/
+#define CAN_EMO17DATA1 (CAN_MO17_EDATA1)
+
+/** \brief 1228, Message Object Interrupt Pointer Register */
+#define CAN_MO17_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019228u)
+
+/** Alias (User Manual Name) for CAN_MO17_EDATA2.
+* To use register names with standard convension, please use CAN_MO17_EDATA2.
+*/
+#define CAN_EMO17DATA2 (CAN_MO17_EDATA2)
+
+/** \brief 122C, Message Object Acceptance Mask Register */
+#define CAN_MO17_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001922Cu)
+
+/** Alias (User Manual Name) for CAN_MO17_EDATA3.
+* To use register names with standard convension, please use CAN_MO17_EDATA3.
+*/
+#define CAN_EMO17DATA3 (CAN_MO17_EDATA3)
+
+/** \brief 1230, Message Object Data Register Low */
+#define CAN_MO17_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019230u)
+
+/** Alias (User Manual Name) for CAN_MO17_EDATA4.
+* To use register names with standard convension, please use CAN_MO17_EDATA4.
+*/
+#define CAN_EMO17DATA4 (CAN_MO17_EDATA4)
+
+/** \brief 1234, Message Object Data Register High */
+#define CAN_MO17_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019234u)
+
+/** Alias (User Manual Name) for CAN_MO17_EDATA5.
+* To use register names with standard convension, please use CAN_MO17_EDATA5.
+*/
+#define CAN_EMO17DATA5 (CAN_MO17_EDATA5)
+
+/** \brief 1238, Message Object Arbitration Register */
+#define CAN_MO17_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019238u)
+
+/** Alias (User Manual Name) for CAN_MO17_EDATA6.
+* To use register names with standard convension, please use CAN_MO17_EDATA6.
+*/
+#define CAN_EMO17DATA6 (CAN_MO17_EDATA6)
+
+/** \brief 1220, Message Object Function Control Register */
+#define CAN_MO17_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019220u)
+
+/** Alias (User Manual Name) for CAN_MO17_FCR.
+* To use register names with standard convension, please use CAN_MO17_FCR.
+*/
+#define CAN_MOFCR17 (CAN_MO17_FCR)
+
+/** \brief 1224, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO17_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019224u)
+
+/** Alias (User Manual Name) for CAN_MO17_FGPR.
+* To use register names with standard convension, please use CAN_MO17_FGPR.
+*/
+#define CAN_MOFGPR17 (CAN_MO17_FGPR)
+
+/** \brief 1228, Message Object Interrupt Pointer Register */
+#define CAN_MO17_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019228u)
+
+/** Alias (User Manual Name) for CAN_MO17_IPR.
+* To use register names with standard convension, please use CAN_MO17_IPR.
+*/
+#define CAN_MOIPR17 (CAN_MO17_IPR)
+
+/** \brief 123C, Message Object Control Register */
+#define CAN_MO17_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001923Cu)
+
+/** Alias (User Manual Name) for CAN_MO17_STAT.
+* To use register names with standard convension, please use CAN_MO17_STAT.
+*/
+#define CAN_MOSTAT17 (CAN_MO17_STAT)
+
+/** \brief 268C, Message Object Acceptance Mask Register */
+#define CAN_MO180_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A68Cu)
+
+/** Alias (User Manual Name) for CAN_MO180_AMR.
+* To use register names with standard convension, please use CAN_MO180_AMR.
+*/
+#define CAN_MOAMR180 (CAN_MO180_AMR)
+
+/** \brief 2698, Message Object Arbitration Register */
+#define CAN_MO180_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A698u)
+
+/** Alias (User Manual Name) for CAN_MO180_AR.
+* To use register names with standard convension, please use CAN_MO180_AR.
+*/
+#define CAN_MOAR180 (CAN_MO180_AR)
+
+/** \brief 269C, Message Object Control Register */
+#define CAN_MO180_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A69Cu)
+
+/** Alias (User Manual Name) for CAN_MO180_CTR.
+* To use register names with standard convension, please use CAN_MO180_CTR.
+*/
+#define CAN_MOCTR180 (CAN_MO180_CTR)
+
+/** \brief 2694, Message Object Data Register High */
+#define CAN_MO180_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A694u)
+
+/** Alias (User Manual Name) for CAN_MO180_DATAH.
+* To use register names with standard convension, please use CAN_MO180_DATAH.
+*/
+#define CAN_MODATAH180 (CAN_MO180_DATAH)
+
+/** \brief 2690, Message Object Data Register Low */
+#define CAN_MO180_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A690u)
+
+/** Alias (User Manual Name) for CAN_MO180_DATAL.
+* To use register names with standard convension, please use CAN_MO180_DATAL.
+*/
+#define CAN_MODATAL180 (CAN_MO180_DATAL)
+
+/** \brief 2680, Message Object Function Control Register */
+#define CAN_MO180_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A680u)
+
+/** Alias (User Manual Name) for CAN_MO180_EDATA0.
+* To use register names with standard convension, please use CAN_MO180_EDATA0.
+*/
+#define CAN_EMO180DATA0 (CAN_MO180_EDATA0)
+
+/** \brief 2684, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO180_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A684u)
+
+/** Alias (User Manual Name) for CAN_MO180_EDATA1.
+* To use register names with standard convension, please use CAN_MO180_EDATA1.
+*/
+#define CAN_EMO180DATA1 (CAN_MO180_EDATA1)
+
+/** \brief 2688, Message Object Interrupt Pointer Register */
+#define CAN_MO180_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A688u)
+
+/** Alias (User Manual Name) for CAN_MO180_EDATA2.
+* To use register names with standard convension, please use CAN_MO180_EDATA2.
+*/
+#define CAN_EMO180DATA2 (CAN_MO180_EDATA2)
+
+/** \brief 268C, Message Object Acceptance Mask Register */
+#define CAN_MO180_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A68Cu)
+
+/** Alias (User Manual Name) for CAN_MO180_EDATA3.
+* To use register names with standard convension, please use CAN_MO180_EDATA3.
+*/
+#define CAN_EMO180DATA3 (CAN_MO180_EDATA3)
+
+/** \brief 2690, Message Object Data Register Low */
+#define CAN_MO180_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A690u)
+
+/** Alias (User Manual Name) for CAN_MO180_EDATA4.
+* To use register names with standard convension, please use CAN_MO180_EDATA4.
+*/
+#define CAN_EMO180DATA4 (CAN_MO180_EDATA4)
+
+/** \brief 2694, Message Object Data Register High */
+#define CAN_MO180_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A694u)
+
+/** Alias (User Manual Name) for CAN_MO180_EDATA5.
+* To use register names with standard convension, please use CAN_MO180_EDATA5.
+*/
+#define CAN_EMO180DATA5 (CAN_MO180_EDATA5)
+
+/** \brief 2698, Message Object Arbitration Register */
+#define CAN_MO180_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A698u)
+
+/** Alias (User Manual Name) for CAN_MO180_EDATA6.
+* To use register names with standard convension, please use CAN_MO180_EDATA6.
+*/
+#define CAN_EMO180DATA6 (CAN_MO180_EDATA6)
+
+/** \brief 2680, Message Object Function Control Register */
+#define CAN_MO180_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A680u)
+
+/** Alias (User Manual Name) for CAN_MO180_FCR.
+* To use register names with standard convension, please use CAN_MO180_FCR.
+*/
+#define CAN_MOFCR180 (CAN_MO180_FCR)
+
+/** \brief 2684, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO180_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A684u)
+
+/** Alias (User Manual Name) for CAN_MO180_FGPR.
+* To use register names with standard convension, please use CAN_MO180_FGPR.
+*/
+#define CAN_MOFGPR180 (CAN_MO180_FGPR)
+
+/** \brief 2688, Message Object Interrupt Pointer Register */
+#define CAN_MO180_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A688u)
+
+/** Alias (User Manual Name) for CAN_MO180_IPR.
+* To use register names with standard convension, please use CAN_MO180_IPR.
+*/
+#define CAN_MOIPR180 (CAN_MO180_IPR)
+
+/** \brief 269C, Message Object Control Register */
+#define CAN_MO180_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A69Cu)
+
+/** Alias (User Manual Name) for CAN_MO180_STAT.
+* To use register names with standard convension, please use CAN_MO180_STAT.
+*/
+#define CAN_MOSTAT180 (CAN_MO180_STAT)
+
+/** \brief 26AC, Message Object Acceptance Mask Register */
+#define CAN_MO181_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A6ACu)
+
+/** Alias (User Manual Name) for CAN_MO181_AMR.
+* To use register names with standard convension, please use CAN_MO181_AMR.
+*/
+#define CAN_MOAMR181 (CAN_MO181_AMR)
+
+/** \brief 26B8, Message Object Arbitration Register */
+#define CAN_MO181_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A6B8u)
+
+/** Alias (User Manual Name) for CAN_MO181_AR.
+* To use register names with standard convension, please use CAN_MO181_AR.
+*/
+#define CAN_MOAR181 (CAN_MO181_AR)
+
+/** \brief 26BC, Message Object Control Register */
+#define CAN_MO181_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A6BCu)
+
+/** Alias (User Manual Name) for CAN_MO181_CTR.
+* To use register names with standard convension, please use CAN_MO181_CTR.
+*/
+#define CAN_MOCTR181 (CAN_MO181_CTR)
+
+/** \brief 26B4, Message Object Data Register High */
+#define CAN_MO181_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A6B4u)
+
+/** Alias (User Manual Name) for CAN_MO181_DATAH.
+* To use register names with standard convension, please use CAN_MO181_DATAH.
+*/
+#define CAN_MODATAH181 (CAN_MO181_DATAH)
+
+/** \brief 26B0, Message Object Data Register Low */
+#define CAN_MO181_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A6B0u)
+
+/** Alias (User Manual Name) for CAN_MO181_DATAL.
+* To use register names with standard convension, please use CAN_MO181_DATAL.
+*/
+#define CAN_MODATAL181 (CAN_MO181_DATAL)
+
+/** \brief 26A0, Message Object Function Control Register */
+#define CAN_MO181_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A6A0u)
+
+/** Alias (User Manual Name) for CAN_MO181_EDATA0.
+* To use register names with standard convension, please use CAN_MO181_EDATA0.
+*/
+#define CAN_EMO181DATA0 (CAN_MO181_EDATA0)
+
+/** \brief 26A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO181_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A6A4u)
+
+/** Alias (User Manual Name) for CAN_MO181_EDATA1.
+* To use register names with standard convension, please use CAN_MO181_EDATA1.
+*/
+#define CAN_EMO181DATA1 (CAN_MO181_EDATA1)
+
+/** \brief 26A8, Message Object Interrupt Pointer Register */
+#define CAN_MO181_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A6A8u)
+
+/** Alias (User Manual Name) for CAN_MO181_EDATA2.
+* To use register names with standard convension, please use CAN_MO181_EDATA2.
+*/
+#define CAN_EMO181DATA2 (CAN_MO181_EDATA2)
+
+/** \brief 26AC, Message Object Acceptance Mask Register */
+#define CAN_MO181_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A6ACu)
+
+/** Alias (User Manual Name) for CAN_MO181_EDATA3.
+* To use register names with standard convension, please use CAN_MO181_EDATA3.
+*/
+#define CAN_EMO181DATA3 (CAN_MO181_EDATA3)
+
+/** \brief 26B0, Message Object Data Register Low */
+#define CAN_MO181_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A6B0u)
+
+/** Alias (User Manual Name) for CAN_MO181_EDATA4.
+* To use register names with standard convension, please use CAN_MO181_EDATA4.
+*/
+#define CAN_EMO181DATA4 (CAN_MO181_EDATA4)
+
+/** \brief 26B4, Message Object Data Register High */
+#define CAN_MO181_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A6B4u)
+
+/** Alias (User Manual Name) for CAN_MO181_EDATA5.
+* To use register names with standard convension, please use CAN_MO181_EDATA5.
+*/
+#define CAN_EMO181DATA5 (CAN_MO181_EDATA5)
+
+/** \brief 26B8, Message Object Arbitration Register */
+#define CAN_MO181_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A6B8u)
+
+/** Alias (User Manual Name) for CAN_MO181_EDATA6.
+* To use register names with standard convension, please use CAN_MO181_EDATA6.
+*/
+#define CAN_EMO181DATA6 (CAN_MO181_EDATA6)
+
+/** \brief 26A0, Message Object Function Control Register */
+#define CAN_MO181_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A6A0u)
+
+/** Alias (User Manual Name) for CAN_MO181_FCR.
+* To use register names with standard convension, please use CAN_MO181_FCR.
+*/
+#define CAN_MOFCR181 (CAN_MO181_FCR)
+
+/** \brief 26A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO181_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A6A4u)
+
+/** Alias (User Manual Name) for CAN_MO181_FGPR.
+* To use register names with standard convension, please use CAN_MO181_FGPR.
+*/
+#define CAN_MOFGPR181 (CAN_MO181_FGPR)
+
+/** \brief 26A8, Message Object Interrupt Pointer Register */
+#define CAN_MO181_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A6A8u)
+
+/** Alias (User Manual Name) for CAN_MO181_IPR.
+* To use register names with standard convension, please use CAN_MO181_IPR.
+*/
+#define CAN_MOIPR181 (CAN_MO181_IPR)
+
+/** \brief 26BC, Message Object Control Register */
+#define CAN_MO181_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A6BCu)
+
+/** Alias (User Manual Name) for CAN_MO181_STAT.
+* To use register names with standard convension, please use CAN_MO181_STAT.
+*/
+#define CAN_MOSTAT181 (CAN_MO181_STAT)
+
+/** \brief 26CC, Message Object Acceptance Mask Register */
+#define CAN_MO182_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A6CCu)
+
+/** Alias (User Manual Name) for CAN_MO182_AMR.
+* To use register names with standard convension, please use CAN_MO182_AMR.
+*/
+#define CAN_MOAMR182 (CAN_MO182_AMR)
+
+/** \brief 26D8, Message Object Arbitration Register */
+#define CAN_MO182_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A6D8u)
+
+/** Alias (User Manual Name) for CAN_MO182_AR.
+* To use register names with standard convension, please use CAN_MO182_AR.
+*/
+#define CAN_MOAR182 (CAN_MO182_AR)
+
+/** \brief 26DC, Message Object Control Register */
+#define CAN_MO182_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A6DCu)
+
+/** Alias (User Manual Name) for CAN_MO182_CTR.
+* To use register names with standard convension, please use CAN_MO182_CTR.
+*/
+#define CAN_MOCTR182 (CAN_MO182_CTR)
+
+/** \brief 26D4, Message Object Data Register High */
+#define CAN_MO182_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A6D4u)
+
+/** Alias (User Manual Name) for CAN_MO182_DATAH.
+* To use register names with standard convension, please use CAN_MO182_DATAH.
+*/
+#define CAN_MODATAH182 (CAN_MO182_DATAH)
+
+/** \brief 26D0, Message Object Data Register Low */
+#define CAN_MO182_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A6D0u)
+
+/** Alias (User Manual Name) for CAN_MO182_DATAL.
+* To use register names with standard convension, please use CAN_MO182_DATAL.
+*/
+#define CAN_MODATAL182 (CAN_MO182_DATAL)
+
+/** \brief 26C0, Message Object Function Control Register */
+#define CAN_MO182_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A6C0u)
+
+/** Alias (User Manual Name) for CAN_MO182_EDATA0.
+* To use register names with standard convension, please use CAN_MO182_EDATA0.
+*/
+#define CAN_EMO182DATA0 (CAN_MO182_EDATA0)
+
+/** \brief 26C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO182_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A6C4u)
+
+/** Alias (User Manual Name) for CAN_MO182_EDATA1.
+* To use register names with standard convension, please use CAN_MO182_EDATA1.
+*/
+#define CAN_EMO182DATA1 (CAN_MO182_EDATA1)
+
+/** \brief 26C8, Message Object Interrupt Pointer Register */
+#define CAN_MO182_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A6C8u)
+
+/** Alias (User Manual Name) for CAN_MO182_EDATA2.
+* To use register names with standard convension, please use CAN_MO182_EDATA2.
+*/
+#define CAN_EMO182DATA2 (CAN_MO182_EDATA2)
+
+/** \brief 26CC, Message Object Acceptance Mask Register */
+#define CAN_MO182_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A6CCu)
+
+/** Alias (User Manual Name) for CAN_MO182_EDATA3.
+* To use register names with standard convension, please use CAN_MO182_EDATA3.
+*/
+#define CAN_EMO182DATA3 (CAN_MO182_EDATA3)
+
+/** \brief 26D0, Message Object Data Register Low */
+#define CAN_MO182_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A6D0u)
+
+/** Alias (User Manual Name) for CAN_MO182_EDATA4.
+* To use register names with standard convension, please use CAN_MO182_EDATA4.
+*/
+#define CAN_EMO182DATA4 (CAN_MO182_EDATA4)
+
+/** \brief 26D4, Message Object Data Register High */
+#define CAN_MO182_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A6D4u)
+
+/** Alias (User Manual Name) for CAN_MO182_EDATA5.
+* To use register names with standard convension, please use CAN_MO182_EDATA5.
+*/
+#define CAN_EMO182DATA5 (CAN_MO182_EDATA5)
+
+/** \brief 26D8, Message Object Arbitration Register */
+#define CAN_MO182_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A6D8u)
+
+/** Alias (User Manual Name) for CAN_MO182_EDATA6.
+* To use register names with standard convension, please use CAN_MO182_EDATA6.
+*/
+#define CAN_EMO182DATA6 (CAN_MO182_EDATA6)
+
+/** \brief 26C0, Message Object Function Control Register */
+#define CAN_MO182_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A6C0u)
+
+/** Alias (User Manual Name) for CAN_MO182_FCR.
+* To use register names with standard convension, please use CAN_MO182_FCR.
+*/
+#define CAN_MOFCR182 (CAN_MO182_FCR)
+
+/** \brief 26C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO182_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A6C4u)
+
+/** Alias (User Manual Name) for CAN_MO182_FGPR.
+* To use register names with standard convension, please use CAN_MO182_FGPR.
+*/
+#define CAN_MOFGPR182 (CAN_MO182_FGPR)
+
+/** \brief 26C8, Message Object Interrupt Pointer Register */
+#define CAN_MO182_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A6C8u)
+
+/** Alias (User Manual Name) for CAN_MO182_IPR.
+* To use register names with standard convension, please use CAN_MO182_IPR.
+*/
+#define CAN_MOIPR182 (CAN_MO182_IPR)
+
+/** \brief 26DC, Message Object Control Register */
+#define CAN_MO182_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A6DCu)
+
+/** Alias (User Manual Name) for CAN_MO182_STAT.
+* To use register names with standard convension, please use CAN_MO182_STAT.
+*/
+#define CAN_MOSTAT182 (CAN_MO182_STAT)
+
+/** \brief 26EC, Message Object Acceptance Mask Register */
+#define CAN_MO183_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A6ECu)
+
+/** Alias (User Manual Name) for CAN_MO183_AMR.
+* To use register names with standard convension, please use CAN_MO183_AMR.
+*/
+#define CAN_MOAMR183 (CAN_MO183_AMR)
+
+/** \brief 26F8, Message Object Arbitration Register */
+#define CAN_MO183_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A6F8u)
+
+/** Alias (User Manual Name) for CAN_MO183_AR.
+* To use register names with standard convension, please use CAN_MO183_AR.
+*/
+#define CAN_MOAR183 (CAN_MO183_AR)
+
+/** \brief 26FC, Message Object Control Register */
+#define CAN_MO183_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A6FCu)
+
+/** Alias (User Manual Name) for CAN_MO183_CTR.
+* To use register names with standard convension, please use CAN_MO183_CTR.
+*/
+#define CAN_MOCTR183 (CAN_MO183_CTR)
+
+/** \brief 26F4, Message Object Data Register High */
+#define CAN_MO183_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A6F4u)
+
+/** Alias (User Manual Name) for CAN_MO183_DATAH.
+* To use register names with standard convension, please use CAN_MO183_DATAH.
+*/
+#define CAN_MODATAH183 (CAN_MO183_DATAH)
+
+/** \brief 26F0, Message Object Data Register Low */
+#define CAN_MO183_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A6F0u)
+
+/** Alias (User Manual Name) for CAN_MO183_DATAL.
+* To use register names with standard convension, please use CAN_MO183_DATAL.
+*/
+#define CAN_MODATAL183 (CAN_MO183_DATAL)
+
+/** \brief 26E0, Message Object Function Control Register */
+#define CAN_MO183_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A6E0u)
+
+/** Alias (User Manual Name) for CAN_MO183_EDATA0.
+* To use register names with standard convension, please use CAN_MO183_EDATA0.
+*/
+#define CAN_EMO183DATA0 (CAN_MO183_EDATA0)
+
+/** \brief 26E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO183_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A6E4u)
+
+/** Alias (User Manual Name) for CAN_MO183_EDATA1.
+* To use register names with standard convension, please use CAN_MO183_EDATA1.
+*/
+#define CAN_EMO183DATA1 (CAN_MO183_EDATA1)
+
+/** \brief 26E8, Message Object Interrupt Pointer Register */
+#define CAN_MO183_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A6E8u)
+
+/** Alias (User Manual Name) for CAN_MO183_EDATA2.
+* To use register names with standard convension, please use CAN_MO183_EDATA2.
+*/
+#define CAN_EMO183DATA2 (CAN_MO183_EDATA2)
+
+/** \brief 26EC, Message Object Acceptance Mask Register */
+#define CAN_MO183_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A6ECu)
+
+/** Alias (User Manual Name) for CAN_MO183_EDATA3.
+* To use register names with standard convension, please use CAN_MO183_EDATA3.
+*/
+#define CAN_EMO183DATA3 (CAN_MO183_EDATA3)
+
+/** \brief 26F0, Message Object Data Register Low */
+#define CAN_MO183_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A6F0u)
+
+/** Alias (User Manual Name) for CAN_MO183_EDATA4.
+* To use register names with standard convension, please use CAN_MO183_EDATA4.
+*/
+#define CAN_EMO183DATA4 (CAN_MO183_EDATA4)
+
+/** \brief 26F4, Message Object Data Register High */
+#define CAN_MO183_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A6F4u)
+
+/** Alias (User Manual Name) for CAN_MO183_EDATA5.
+* To use register names with standard convension, please use CAN_MO183_EDATA5.
+*/
+#define CAN_EMO183DATA5 (CAN_MO183_EDATA5)
+
+/** \brief 26F8, Message Object Arbitration Register */
+#define CAN_MO183_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A6F8u)
+
+/** Alias (User Manual Name) for CAN_MO183_EDATA6.
+* To use register names with standard convension, please use CAN_MO183_EDATA6.
+*/
+#define CAN_EMO183DATA6 (CAN_MO183_EDATA6)
+
+/** \brief 26E0, Message Object Function Control Register */
+#define CAN_MO183_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A6E0u)
+
+/** Alias (User Manual Name) for CAN_MO183_FCR.
+* To use register names with standard convension, please use CAN_MO183_FCR.
+*/
+#define CAN_MOFCR183 (CAN_MO183_FCR)
+
+/** \brief 26E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO183_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A6E4u)
+
+/** Alias (User Manual Name) for CAN_MO183_FGPR.
+* To use register names with standard convension, please use CAN_MO183_FGPR.
+*/
+#define CAN_MOFGPR183 (CAN_MO183_FGPR)
+
+/** \brief 26E8, Message Object Interrupt Pointer Register */
+#define CAN_MO183_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A6E8u)
+
+/** Alias (User Manual Name) for CAN_MO183_IPR.
+* To use register names with standard convension, please use CAN_MO183_IPR.
+*/
+#define CAN_MOIPR183 (CAN_MO183_IPR)
+
+/** \brief 26FC, Message Object Control Register */
+#define CAN_MO183_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A6FCu)
+
+/** Alias (User Manual Name) for CAN_MO183_STAT.
+* To use register names with standard convension, please use CAN_MO183_STAT.
+*/
+#define CAN_MOSTAT183 (CAN_MO183_STAT)
+
+/** \brief 270C, Message Object Acceptance Mask Register */
+#define CAN_MO184_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A70Cu)
+
+/** Alias (User Manual Name) for CAN_MO184_AMR.
+* To use register names with standard convension, please use CAN_MO184_AMR.
+*/
+#define CAN_MOAMR184 (CAN_MO184_AMR)
+
+/** \brief 2718, Message Object Arbitration Register */
+#define CAN_MO184_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A718u)
+
+/** Alias (User Manual Name) for CAN_MO184_AR.
+* To use register names with standard convension, please use CAN_MO184_AR.
+*/
+#define CAN_MOAR184 (CAN_MO184_AR)
+
+/** \brief 271C, Message Object Control Register */
+#define CAN_MO184_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A71Cu)
+
+/** Alias (User Manual Name) for CAN_MO184_CTR.
+* To use register names with standard convension, please use CAN_MO184_CTR.
+*/
+#define CAN_MOCTR184 (CAN_MO184_CTR)
+
+/** \brief 2714, Message Object Data Register High */
+#define CAN_MO184_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A714u)
+
+/** Alias (User Manual Name) for CAN_MO184_DATAH.
+* To use register names with standard convension, please use CAN_MO184_DATAH.
+*/
+#define CAN_MODATAH184 (CAN_MO184_DATAH)
+
+/** \brief 2710, Message Object Data Register Low */
+#define CAN_MO184_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A710u)
+
+/** Alias (User Manual Name) for CAN_MO184_DATAL.
+* To use register names with standard convension, please use CAN_MO184_DATAL.
+*/
+#define CAN_MODATAL184 (CAN_MO184_DATAL)
+
+/** \brief 2700, Message Object Function Control Register */
+#define CAN_MO184_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A700u)
+
+/** Alias (User Manual Name) for CAN_MO184_EDATA0.
+* To use register names with standard convension, please use CAN_MO184_EDATA0.
+*/
+#define CAN_EMO184DATA0 (CAN_MO184_EDATA0)
+
+/** \brief 2704, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO184_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A704u)
+
+/** Alias (User Manual Name) for CAN_MO184_EDATA1.
+* To use register names with standard convension, please use CAN_MO184_EDATA1.
+*/
+#define CAN_EMO184DATA1 (CAN_MO184_EDATA1)
+
+/** \brief 2708, Message Object Interrupt Pointer Register */
+#define CAN_MO184_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A708u)
+
+/** Alias (User Manual Name) for CAN_MO184_EDATA2.
+* To use register names with standard convension, please use CAN_MO184_EDATA2.
+*/
+#define CAN_EMO184DATA2 (CAN_MO184_EDATA2)
+
+/** \brief 270C, Message Object Acceptance Mask Register */
+#define CAN_MO184_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A70Cu)
+
+/** Alias (User Manual Name) for CAN_MO184_EDATA3.
+* To use register names with standard convension, please use CAN_MO184_EDATA3.
+*/
+#define CAN_EMO184DATA3 (CAN_MO184_EDATA3)
+
+/** \brief 2710, Message Object Data Register Low */
+#define CAN_MO184_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A710u)
+
+/** Alias (User Manual Name) for CAN_MO184_EDATA4.
+* To use register names with standard convension, please use CAN_MO184_EDATA4.
+*/
+#define CAN_EMO184DATA4 (CAN_MO184_EDATA4)
+
+/** \brief 2714, Message Object Data Register High */
+#define CAN_MO184_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A714u)
+
+/** Alias (User Manual Name) for CAN_MO184_EDATA5.
+* To use register names with standard convension, please use CAN_MO184_EDATA5.
+*/
+#define CAN_EMO184DATA5 (CAN_MO184_EDATA5)
+
+/** \brief 2718, Message Object Arbitration Register */
+#define CAN_MO184_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A718u)
+
+/** Alias (User Manual Name) for CAN_MO184_EDATA6.
+* To use register names with standard convension, please use CAN_MO184_EDATA6.
+*/
+#define CAN_EMO184DATA6 (CAN_MO184_EDATA6)
+
+/** \brief 2700, Message Object Function Control Register */
+#define CAN_MO184_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A700u)
+
+/** Alias (User Manual Name) for CAN_MO184_FCR.
+* To use register names with standard convension, please use CAN_MO184_FCR.
+*/
+#define CAN_MOFCR184 (CAN_MO184_FCR)
+
+/** \brief 2704, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO184_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A704u)
+
+/** Alias (User Manual Name) for CAN_MO184_FGPR.
+* To use register names with standard convension, please use CAN_MO184_FGPR.
+*/
+#define CAN_MOFGPR184 (CAN_MO184_FGPR)
+
+/** \brief 2708, Message Object Interrupt Pointer Register */
+#define CAN_MO184_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A708u)
+
+/** Alias (User Manual Name) for CAN_MO184_IPR.
+* To use register names with standard convension, please use CAN_MO184_IPR.
+*/
+#define CAN_MOIPR184 (CAN_MO184_IPR)
+
+/** \brief 271C, Message Object Control Register */
+#define CAN_MO184_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A71Cu)
+
+/** Alias (User Manual Name) for CAN_MO184_STAT.
+* To use register names with standard convension, please use CAN_MO184_STAT.
+*/
+#define CAN_MOSTAT184 (CAN_MO184_STAT)
+
+/** \brief 272C, Message Object Acceptance Mask Register */
+#define CAN_MO185_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A72Cu)
+
+/** Alias (User Manual Name) for CAN_MO185_AMR.
+* To use register names with standard convension, please use CAN_MO185_AMR.
+*/
+#define CAN_MOAMR185 (CAN_MO185_AMR)
+
+/** \brief 2738, Message Object Arbitration Register */
+#define CAN_MO185_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A738u)
+
+/** Alias (User Manual Name) for CAN_MO185_AR.
+* To use register names with standard convension, please use CAN_MO185_AR.
+*/
+#define CAN_MOAR185 (CAN_MO185_AR)
+
+/** \brief 273C, Message Object Control Register */
+#define CAN_MO185_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A73Cu)
+
+/** Alias (User Manual Name) for CAN_MO185_CTR.
+* To use register names with standard convension, please use CAN_MO185_CTR.
+*/
+#define CAN_MOCTR185 (CAN_MO185_CTR)
+
+/** \brief 2734, Message Object Data Register High */
+#define CAN_MO185_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A734u)
+
+/** Alias (User Manual Name) for CAN_MO185_DATAH.
+* To use register names with standard convension, please use CAN_MO185_DATAH.
+*/
+#define CAN_MODATAH185 (CAN_MO185_DATAH)
+
+/** \brief 2730, Message Object Data Register Low */
+#define CAN_MO185_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A730u)
+
+/** Alias (User Manual Name) for CAN_MO185_DATAL.
+* To use register names with standard convension, please use CAN_MO185_DATAL.
+*/
+#define CAN_MODATAL185 (CAN_MO185_DATAL)
+
+/** \brief 2720, Message Object Function Control Register */
+#define CAN_MO185_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A720u)
+
+/** Alias (User Manual Name) for CAN_MO185_EDATA0.
+* To use register names with standard convension, please use CAN_MO185_EDATA0.
+*/
+#define CAN_EMO185DATA0 (CAN_MO185_EDATA0)
+
+/** \brief 2724, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO185_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A724u)
+
+/** Alias (User Manual Name) for CAN_MO185_EDATA1.
+* To use register names with standard convension, please use CAN_MO185_EDATA1.
+*/
+#define CAN_EMO185DATA1 (CAN_MO185_EDATA1)
+
+/** \brief 2728, Message Object Interrupt Pointer Register */
+#define CAN_MO185_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A728u)
+
+/** Alias (User Manual Name) for CAN_MO185_EDATA2.
+* To use register names with standard convension, please use CAN_MO185_EDATA2.
+*/
+#define CAN_EMO185DATA2 (CAN_MO185_EDATA2)
+
+/** \brief 272C, Message Object Acceptance Mask Register */
+#define CAN_MO185_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A72Cu)
+
+/** Alias (User Manual Name) for CAN_MO185_EDATA3.
+* To use register names with standard convension, please use CAN_MO185_EDATA3.
+*/
+#define CAN_EMO185DATA3 (CAN_MO185_EDATA3)
+
+/** \brief 2730, Message Object Data Register Low */
+#define CAN_MO185_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A730u)
+
+/** Alias (User Manual Name) for CAN_MO185_EDATA4.
+* To use register names with standard convension, please use CAN_MO185_EDATA4.
+*/
+#define CAN_EMO185DATA4 (CAN_MO185_EDATA4)
+
+/** \brief 2734, Message Object Data Register High */
+#define CAN_MO185_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A734u)
+
+/** Alias (User Manual Name) for CAN_MO185_EDATA5.
+* To use register names with standard convension, please use CAN_MO185_EDATA5.
+*/
+#define CAN_EMO185DATA5 (CAN_MO185_EDATA5)
+
+/** \brief 2738, Message Object Arbitration Register */
+#define CAN_MO185_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A738u)
+
+/** Alias (User Manual Name) for CAN_MO185_EDATA6.
+* To use register names with standard convension, please use CAN_MO185_EDATA6.
+*/
+#define CAN_EMO185DATA6 (CAN_MO185_EDATA6)
+
+/** \brief 2720, Message Object Function Control Register */
+#define CAN_MO185_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A720u)
+
+/** Alias (User Manual Name) for CAN_MO185_FCR.
+* To use register names with standard convension, please use CAN_MO185_FCR.
+*/
+#define CAN_MOFCR185 (CAN_MO185_FCR)
+
+/** \brief 2724, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO185_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A724u)
+
+/** Alias (User Manual Name) for CAN_MO185_FGPR.
+* To use register names with standard convension, please use CAN_MO185_FGPR.
+*/
+#define CAN_MOFGPR185 (CAN_MO185_FGPR)
+
+/** \brief 2728, Message Object Interrupt Pointer Register */
+#define CAN_MO185_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A728u)
+
+/** Alias (User Manual Name) for CAN_MO185_IPR.
+* To use register names with standard convension, please use CAN_MO185_IPR.
+*/
+#define CAN_MOIPR185 (CAN_MO185_IPR)
+
+/** \brief 273C, Message Object Control Register */
+#define CAN_MO185_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A73Cu)
+
+/** Alias (User Manual Name) for CAN_MO185_STAT.
+* To use register names with standard convension, please use CAN_MO185_STAT.
+*/
+#define CAN_MOSTAT185 (CAN_MO185_STAT)
+
+/** \brief 274C, Message Object Acceptance Mask Register */
+#define CAN_MO186_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A74Cu)
+
+/** Alias (User Manual Name) for CAN_MO186_AMR.
+* To use register names with standard convension, please use CAN_MO186_AMR.
+*/
+#define CAN_MOAMR186 (CAN_MO186_AMR)
+
+/** \brief 2758, Message Object Arbitration Register */
+#define CAN_MO186_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A758u)
+
+/** Alias (User Manual Name) for CAN_MO186_AR.
+* To use register names with standard convension, please use CAN_MO186_AR.
+*/
+#define CAN_MOAR186 (CAN_MO186_AR)
+
+/** \brief 275C, Message Object Control Register */
+#define CAN_MO186_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A75Cu)
+
+/** Alias (User Manual Name) for CAN_MO186_CTR.
+* To use register names with standard convension, please use CAN_MO186_CTR.
+*/
+#define CAN_MOCTR186 (CAN_MO186_CTR)
+
+/** \brief 2754, Message Object Data Register High */
+#define CAN_MO186_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A754u)
+
+/** Alias (User Manual Name) for CAN_MO186_DATAH.
+* To use register names with standard convension, please use CAN_MO186_DATAH.
+*/
+#define CAN_MODATAH186 (CAN_MO186_DATAH)
+
+/** \brief 2750, Message Object Data Register Low */
+#define CAN_MO186_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A750u)
+
+/** Alias (User Manual Name) for CAN_MO186_DATAL.
+* To use register names with standard convension, please use CAN_MO186_DATAL.
+*/
+#define CAN_MODATAL186 (CAN_MO186_DATAL)
+
+/** \brief 2740, Message Object Function Control Register */
+#define CAN_MO186_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A740u)
+
+/** Alias (User Manual Name) for CAN_MO186_EDATA0.
+* To use register names with standard convension, please use CAN_MO186_EDATA0.
+*/
+#define CAN_EMO186DATA0 (CAN_MO186_EDATA0)
+
+/** \brief 2744, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO186_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A744u)
+
+/** Alias (User Manual Name) for CAN_MO186_EDATA1.
+* To use register names with standard convension, please use CAN_MO186_EDATA1.
+*/
+#define CAN_EMO186DATA1 (CAN_MO186_EDATA1)
+
+/** \brief 2748, Message Object Interrupt Pointer Register */
+#define CAN_MO186_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A748u)
+
+/** Alias (User Manual Name) for CAN_MO186_EDATA2.
+* To use register names with standard convension, please use CAN_MO186_EDATA2.
+*/
+#define CAN_EMO186DATA2 (CAN_MO186_EDATA2)
+
+/** \brief 274C, Message Object Acceptance Mask Register */
+#define CAN_MO186_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A74Cu)
+
+/** Alias (User Manual Name) for CAN_MO186_EDATA3.
+* To use register names with standard convension, please use CAN_MO186_EDATA3.
+*/
+#define CAN_EMO186DATA3 (CAN_MO186_EDATA3)
+
+/** \brief 2750, Message Object Data Register Low */
+#define CAN_MO186_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A750u)
+
+/** Alias (User Manual Name) for CAN_MO186_EDATA4.
+* To use register names with standard convension, please use CAN_MO186_EDATA4.
+*/
+#define CAN_EMO186DATA4 (CAN_MO186_EDATA4)
+
+/** \brief 2754, Message Object Data Register High */
+#define CAN_MO186_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A754u)
+
+/** Alias (User Manual Name) for CAN_MO186_EDATA5.
+* To use register names with standard convension, please use CAN_MO186_EDATA5.
+*/
+#define CAN_EMO186DATA5 (CAN_MO186_EDATA5)
+
+/** \brief 2758, Message Object Arbitration Register */
+#define CAN_MO186_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A758u)
+
+/** Alias (User Manual Name) for CAN_MO186_EDATA6.
+* To use register names with standard convension, please use CAN_MO186_EDATA6.
+*/
+#define CAN_EMO186DATA6 (CAN_MO186_EDATA6)
+
+/** \brief 2740, Message Object Function Control Register */
+#define CAN_MO186_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A740u)
+
+/** Alias (User Manual Name) for CAN_MO186_FCR.
+* To use register names with standard convension, please use CAN_MO186_FCR.
+*/
+#define CAN_MOFCR186 (CAN_MO186_FCR)
+
+/** \brief 2744, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO186_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A744u)
+
+/** Alias (User Manual Name) for CAN_MO186_FGPR.
+* To use register names with standard convension, please use CAN_MO186_FGPR.
+*/
+#define CAN_MOFGPR186 (CAN_MO186_FGPR)
+
+/** \brief 2748, Message Object Interrupt Pointer Register */
+#define CAN_MO186_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A748u)
+
+/** Alias (User Manual Name) for CAN_MO186_IPR.
+* To use register names with standard convension, please use CAN_MO186_IPR.
+*/
+#define CAN_MOIPR186 (CAN_MO186_IPR)
+
+/** \brief 275C, Message Object Control Register */
+#define CAN_MO186_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A75Cu)
+
+/** Alias (User Manual Name) for CAN_MO186_STAT.
+* To use register names with standard convension, please use CAN_MO186_STAT.
+*/
+#define CAN_MOSTAT186 (CAN_MO186_STAT)
+
+/** \brief 276C, Message Object Acceptance Mask Register */
+#define CAN_MO187_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A76Cu)
+
+/** Alias (User Manual Name) for CAN_MO187_AMR.
+* To use register names with standard convension, please use CAN_MO187_AMR.
+*/
+#define CAN_MOAMR187 (CAN_MO187_AMR)
+
+/** \brief 2778, Message Object Arbitration Register */
+#define CAN_MO187_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A778u)
+
+/** Alias (User Manual Name) for CAN_MO187_AR.
+* To use register names with standard convension, please use CAN_MO187_AR.
+*/
+#define CAN_MOAR187 (CAN_MO187_AR)
+
+/** \brief 277C, Message Object Control Register */
+#define CAN_MO187_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A77Cu)
+
+/** Alias (User Manual Name) for CAN_MO187_CTR.
+* To use register names with standard convension, please use CAN_MO187_CTR.
+*/
+#define CAN_MOCTR187 (CAN_MO187_CTR)
+
+/** \brief 2774, Message Object Data Register High */
+#define CAN_MO187_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A774u)
+
+/** Alias (User Manual Name) for CAN_MO187_DATAH.
+* To use register names with standard convension, please use CAN_MO187_DATAH.
+*/
+#define CAN_MODATAH187 (CAN_MO187_DATAH)
+
+/** \brief 2770, Message Object Data Register Low */
+#define CAN_MO187_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A770u)
+
+/** Alias (User Manual Name) for CAN_MO187_DATAL.
+* To use register names with standard convension, please use CAN_MO187_DATAL.
+*/
+#define CAN_MODATAL187 (CAN_MO187_DATAL)
+
+/** \brief 2760, Message Object Function Control Register */
+#define CAN_MO187_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A760u)
+
+/** Alias (User Manual Name) for CAN_MO187_EDATA0.
+* To use register names with standard convension, please use CAN_MO187_EDATA0.
+*/
+#define CAN_EMO187DATA0 (CAN_MO187_EDATA0)
+
+/** \brief 2764, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO187_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A764u)
+
+/** Alias (User Manual Name) for CAN_MO187_EDATA1.
+* To use register names with standard convension, please use CAN_MO187_EDATA1.
+*/
+#define CAN_EMO187DATA1 (CAN_MO187_EDATA1)
+
+/** \brief 2768, Message Object Interrupt Pointer Register */
+#define CAN_MO187_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A768u)
+
+/** Alias (User Manual Name) for CAN_MO187_EDATA2.
+* To use register names with standard convension, please use CAN_MO187_EDATA2.
+*/
+#define CAN_EMO187DATA2 (CAN_MO187_EDATA2)
+
+/** \brief 276C, Message Object Acceptance Mask Register */
+#define CAN_MO187_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A76Cu)
+
+/** Alias (User Manual Name) for CAN_MO187_EDATA3.
+* To use register names with standard convension, please use CAN_MO187_EDATA3.
+*/
+#define CAN_EMO187DATA3 (CAN_MO187_EDATA3)
+
+/** \brief 2770, Message Object Data Register Low */
+#define CAN_MO187_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A770u)
+
+/** Alias (User Manual Name) for CAN_MO187_EDATA4.
+* To use register names with standard convension, please use CAN_MO187_EDATA4.
+*/
+#define CAN_EMO187DATA4 (CAN_MO187_EDATA4)
+
+/** \brief 2774, Message Object Data Register High */
+#define CAN_MO187_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A774u)
+
+/** Alias (User Manual Name) for CAN_MO187_EDATA5.
+* To use register names with standard convension, please use CAN_MO187_EDATA5.
+*/
+#define CAN_EMO187DATA5 (CAN_MO187_EDATA5)
+
+/** \brief 2778, Message Object Arbitration Register */
+#define CAN_MO187_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A778u)
+
+/** Alias (User Manual Name) for CAN_MO187_EDATA6.
+* To use register names with standard convension, please use CAN_MO187_EDATA6.
+*/
+#define CAN_EMO187DATA6 (CAN_MO187_EDATA6)
+
+/** \brief 2760, Message Object Function Control Register */
+#define CAN_MO187_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A760u)
+
+/** Alias (User Manual Name) for CAN_MO187_FCR.
+* To use register names with standard convension, please use CAN_MO187_FCR.
+*/
+#define CAN_MOFCR187 (CAN_MO187_FCR)
+
+/** \brief 2764, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO187_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A764u)
+
+/** Alias (User Manual Name) for CAN_MO187_FGPR.
+* To use register names with standard convension, please use CAN_MO187_FGPR.
+*/
+#define CAN_MOFGPR187 (CAN_MO187_FGPR)
+
+/** \brief 2768, Message Object Interrupt Pointer Register */
+#define CAN_MO187_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A768u)
+
+/** Alias (User Manual Name) for CAN_MO187_IPR.
+* To use register names with standard convension, please use CAN_MO187_IPR.
+*/
+#define CAN_MOIPR187 (CAN_MO187_IPR)
+
+/** \brief 277C, Message Object Control Register */
+#define CAN_MO187_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A77Cu)
+
+/** Alias (User Manual Name) for CAN_MO187_STAT.
+* To use register names with standard convension, please use CAN_MO187_STAT.
+*/
+#define CAN_MOSTAT187 (CAN_MO187_STAT)
+
+/** \brief 278C, Message Object Acceptance Mask Register */
+#define CAN_MO188_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A78Cu)
+
+/** Alias (User Manual Name) for CAN_MO188_AMR.
+* To use register names with standard convension, please use CAN_MO188_AMR.
+*/
+#define CAN_MOAMR188 (CAN_MO188_AMR)
+
+/** \brief 2798, Message Object Arbitration Register */
+#define CAN_MO188_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A798u)
+
+/** Alias (User Manual Name) for CAN_MO188_AR.
+* To use register names with standard convension, please use CAN_MO188_AR.
+*/
+#define CAN_MOAR188 (CAN_MO188_AR)
+
+/** \brief 279C, Message Object Control Register */
+#define CAN_MO188_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A79Cu)
+
+/** Alias (User Manual Name) for CAN_MO188_CTR.
+* To use register names with standard convension, please use CAN_MO188_CTR.
+*/
+#define CAN_MOCTR188 (CAN_MO188_CTR)
+
+/** \brief 2794, Message Object Data Register High */
+#define CAN_MO188_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A794u)
+
+/** Alias (User Manual Name) for CAN_MO188_DATAH.
+* To use register names with standard convension, please use CAN_MO188_DATAH.
+*/
+#define CAN_MODATAH188 (CAN_MO188_DATAH)
+
+/** \brief 2790, Message Object Data Register Low */
+#define CAN_MO188_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A790u)
+
+/** Alias (User Manual Name) for CAN_MO188_DATAL.
+* To use register names with standard convension, please use CAN_MO188_DATAL.
+*/
+#define CAN_MODATAL188 (CAN_MO188_DATAL)
+
+/** \brief 2780, Message Object Function Control Register */
+#define CAN_MO188_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A780u)
+
+/** Alias (User Manual Name) for CAN_MO188_EDATA0.
+* To use register names with standard convension, please use CAN_MO188_EDATA0.
+*/
+#define CAN_EMO188DATA0 (CAN_MO188_EDATA0)
+
+/** \brief 2784, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO188_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A784u)
+
+/** Alias (User Manual Name) for CAN_MO188_EDATA1.
+* To use register names with standard convension, please use CAN_MO188_EDATA1.
+*/
+#define CAN_EMO188DATA1 (CAN_MO188_EDATA1)
+
+/** \brief 2788, Message Object Interrupt Pointer Register */
+#define CAN_MO188_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A788u)
+
+/** Alias (User Manual Name) for CAN_MO188_EDATA2.
+* To use register names with standard convension, please use CAN_MO188_EDATA2.
+*/
+#define CAN_EMO188DATA2 (CAN_MO188_EDATA2)
+
+/** \brief 278C, Message Object Acceptance Mask Register */
+#define CAN_MO188_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A78Cu)
+
+/** Alias (User Manual Name) for CAN_MO188_EDATA3.
+* To use register names with standard convension, please use CAN_MO188_EDATA3.
+*/
+#define CAN_EMO188DATA3 (CAN_MO188_EDATA3)
+
+/** \brief 2790, Message Object Data Register Low */
+#define CAN_MO188_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A790u)
+
+/** Alias (User Manual Name) for CAN_MO188_EDATA4.
+* To use register names with standard convension, please use CAN_MO188_EDATA4.
+*/
+#define CAN_EMO188DATA4 (CAN_MO188_EDATA4)
+
+/** \brief 2794, Message Object Data Register High */
+#define CAN_MO188_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A794u)
+
+/** Alias (User Manual Name) for CAN_MO188_EDATA5.
+* To use register names with standard convension, please use CAN_MO188_EDATA5.
+*/
+#define CAN_EMO188DATA5 (CAN_MO188_EDATA5)
+
+/** \brief 2798, Message Object Arbitration Register */
+#define CAN_MO188_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A798u)
+
+/** Alias (User Manual Name) for CAN_MO188_EDATA6.
+* To use register names with standard convension, please use CAN_MO188_EDATA6.
+*/
+#define CAN_EMO188DATA6 (CAN_MO188_EDATA6)
+
+/** \brief 2780, Message Object Function Control Register */
+#define CAN_MO188_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A780u)
+
+/** Alias (User Manual Name) for CAN_MO188_FCR.
+* To use register names with standard convension, please use CAN_MO188_FCR.
+*/
+#define CAN_MOFCR188 (CAN_MO188_FCR)
+
+/** \brief 2784, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO188_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A784u)
+
+/** Alias (User Manual Name) for CAN_MO188_FGPR.
+* To use register names with standard convension, please use CAN_MO188_FGPR.
+*/
+#define CAN_MOFGPR188 (CAN_MO188_FGPR)
+
+/** \brief 2788, Message Object Interrupt Pointer Register */
+#define CAN_MO188_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A788u)
+
+/** Alias (User Manual Name) for CAN_MO188_IPR.
+* To use register names with standard convension, please use CAN_MO188_IPR.
+*/
+#define CAN_MOIPR188 (CAN_MO188_IPR)
+
+/** \brief 279C, Message Object Control Register */
+#define CAN_MO188_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A79Cu)
+
+/** Alias (User Manual Name) for CAN_MO188_STAT.
+* To use register names with standard convension, please use CAN_MO188_STAT.
+*/
+#define CAN_MOSTAT188 (CAN_MO188_STAT)
+
+/** \brief 27AC, Message Object Acceptance Mask Register */
+#define CAN_MO189_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A7ACu)
+
+/** Alias (User Manual Name) for CAN_MO189_AMR.
+* To use register names with standard convension, please use CAN_MO189_AMR.
+*/
+#define CAN_MOAMR189 (CAN_MO189_AMR)
+
+/** \brief 27B8, Message Object Arbitration Register */
+#define CAN_MO189_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A7B8u)
+
+/** Alias (User Manual Name) for CAN_MO189_AR.
+* To use register names with standard convension, please use CAN_MO189_AR.
+*/
+#define CAN_MOAR189 (CAN_MO189_AR)
+
+/** \brief 27BC, Message Object Control Register */
+#define CAN_MO189_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A7BCu)
+
+/** Alias (User Manual Name) for CAN_MO189_CTR.
+* To use register names with standard convension, please use CAN_MO189_CTR.
+*/
+#define CAN_MOCTR189 (CAN_MO189_CTR)
+
+/** \brief 27B4, Message Object Data Register High */
+#define CAN_MO189_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A7B4u)
+
+/** Alias (User Manual Name) for CAN_MO189_DATAH.
+* To use register names with standard convension, please use CAN_MO189_DATAH.
+*/
+#define CAN_MODATAH189 (CAN_MO189_DATAH)
+
+/** \brief 27B0, Message Object Data Register Low */
+#define CAN_MO189_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A7B0u)
+
+/** Alias (User Manual Name) for CAN_MO189_DATAL.
+* To use register names with standard convension, please use CAN_MO189_DATAL.
+*/
+#define CAN_MODATAL189 (CAN_MO189_DATAL)
+
+/** \brief 27A0, Message Object Function Control Register */
+#define CAN_MO189_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A7A0u)
+
+/** Alias (User Manual Name) for CAN_MO189_EDATA0.
+* To use register names with standard convension, please use CAN_MO189_EDATA0.
+*/
+#define CAN_EMO189DATA0 (CAN_MO189_EDATA0)
+
+/** \brief 27A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO189_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A7A4u)
+
+/** Alias (User Manual Name) for CAN_MO189_EDATA1.
+* To use register names with standard convension, please use CAN_MO189_EDATA1.
+*/
+#define CAN_EMO189DATA1 (CAN_MO189_EDATA1)
+
+/** \brief 27A8, Message Object Interrupt Pointer Register */
+#define CAN_MO189_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A7A8u)
+
+/** Alias (User Manual Name) for CAN_MO189_EDATA2.
+* To use register names with standard convension, please use CAN_MO189_EDATA2.
+*/
+#define CAN_EMO189DATA2 (CAN_MO189_EDATA2)
+
+/** \brief 27AC, Message Object Acceptance Mask Register */
+#define CAN_MO189_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A7ACu)
+
+/** Alias (User Manual Name) for CAN_MO189_EDATA3.
+* To use register names with standard convension, please use CAN_MO189_EDATA3.
+*/
+#define CAN_EMO189DATA3 (CAN_MO189_EDATA3)
+
+/** \brief 27B0, Message Object Data Register Low */
+#define CAN_MO189_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A7B0u)
+
+/** Alias (User Manual Name) for CAN_MO189_EDATA4.
+* To use register names with standard convension, please use CAN_MO189_EDATA4.
+*/
+#define CAN_EMO189DATA4 (CAN_MO189_EDATA4)
+
+/** \brief 27B4, Message Object Data Register High */
+#define CAN_MO189_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A7B4u)
+
+/** Alias (User Manual Name) for CAN_MO189_EDATA5.
+* To use register names with standard convension, please use CAN_MO189_EDATA5.
+*/
+#define CAN_EMO189DATA5 (CAN_MO189_EDATA5)
+
+/** \brief 27B8, Message Object Arbitration Register */
+#define CAN_MO189_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A7B8u)
+
+/** Alias (User Manual Name) for CAN_MO189_EDATA6.
+* To use register names with standard convension, please use CAN_MO189_EDATA6.
+*/
+#define CAN_EMO189DATA6 (CAN_MO189_EDATA6)
+
+/** \brief 27A0, Message Object Function Control Register */
+#define CAN_MO189_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A7A0u)
+
+/** Alias (User Manual Name) for CAN_MO189_FCR.
+* To use register names with standard convension, please use CAN_MO189_FCR.
+*/
+#define CAN_MOFCR189 (CAN_MO189_FCR)
+
+/** \brief 27A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO189_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A7A4u)
+
+/** Alias (User Manual Name) for CAN_MO189_FGPR.
+* To use register names with standard convension, please use CAN_MO189_FGPR.
+*/
+#define CAN_MOFGPR189 (CAN_MO189_FGPR)
+
+/** \brief 27A8, Message Object Interrupt Pointer Register */
+#define CAN_MO189_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A7A8u)
+
+/** Alias (User Manual Name) for CAN_MO189_IPR.
+* To use register names with standard convension, please use CAN_MO189_IPR.
+*/
+#define CAN_MOIPR189 (CAN_MO189_IPR)
+
+/** \brief 27BC, Message Object Control Register */
+#define CAN_MO189_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A7BCu)
+
+/** Alias (User Manual Name) for CAN_MO189_STAT.
+* To use register names with standard convension, please use CAN_MO189_STAT.
+*/
+#define CAN_MOSTAT189 (CAN_MO189_STAT)
+
+/** \brief 124C, Message Object Acceptance Mask Register */
+#define CAN_MO18_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001924Cu)
+
+/** Alias (User Manual Name) for CAN_MO18_AMR.
+* To use register names with standard convension, please use CAN_MO18_AMR.
+*/
+#define CAN_MOAMR18 (CAN_MO18_AMR)
+
+/** \brief 1258, Message Object Arbitration Register */
+#define CAN_MO18_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019258u)
+
+/** Alias (User Manual Name) for CAN_MO18_AR.
+* To use register names with standard convension, please use CAN_MO18_AR.
+*/
+#define CAN_MOAR18 (CAN_MO18_AR)
+
+/** \brief 125C, Message Object Control Register */
+#define CAN_MO18_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001925Cu)
+
+/** Alias (User Manual Name) for CAN_MO18_CTR.
+* To use register names with standard convension, please use CAN_MO18_CTR.
+*/
+#define CAN_MOCTR18 (CAN_MO18_CTR)
+
+/** \brief 1254, Message Object Data Register High */
+#define CAN_MO18_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019254u)
+
+/** Alias (User Manual Name) for CAN_MO18_DATAH.
+* To use register names with standard convension, please use CAN_MO18_DATAH.
+*/
+#define CAN_MODATAH18 (CAN_MO18_DATAH)
+
+/** \brief 1250, Message Object Data Register Low */
+#define CAN_MO18_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019250u)
+
+/** Alias (User Manual Name) for CAN_MO18_DATAL.
+* To use register names with standard convension, please use CAN_MO18_DATAL.
+*/
+#define CAN_MODATAL18 (CAN_MO18_DATAL)
+
+/** \brief 1240, Message Object Function Control Register */
+#define CAN_MO18_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019240u)
+
+/** Alias (User Manual Name) for CAN_MO18_EDATA0.
+* To use register names with standard convension, please use CAN_MO18_EDATA0.
+*/
+#define CAN_EMO18DATA0 (CAN_MO18_EDATA0)
+
+/** \brief 1244, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO18_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019244u)
+
+/** Alias (User Manual Name) for CAN_MO18_EDATA1.
+* To use register names with standard convension, please use CAN_MO18_EDATA1.
+*/
+#define CAN_EMO18DATA1 (CAN_MO18_EDATA1)
+
+/** \brief 1248, Message Object Interrupt Pointer Register */
+#define CAN_MO18_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019248u)
+
+/** Alias (User Manual Name) for CAN_MO18_EDATA2.
+* To use register names with standard convension, please use CAN_MO18_EDATA2.
+*/
+#define CAN_EMO18DATA2 (CAN_MO18_EDATA2)
+
+/** \brief 124C, Message Object Acceptance Mask Register */
+#define CAN_MO18_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001924Cu)
+
+/** Alias (User Manual Name) for CAN_MO18_EDATA3.
+* To use register names with standard convension, please use CAN_MO18_EDATA3.
+*/
+#define CAN_EMO18DATA3 (CAN_MO18_EDATA3)
+
+/** \brief 1250, Message Object Data Register Low */
+#define CAN_MO18_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019250u)
+
+/** Alias (User Manual Name) for CAN_MO18_EDATA4.
+* To use register names with standard convension, please use CAN_MO18_EDATA4.
+*/
+#define CAN_EMO18DATA4 (CAN_MO18_EDATA4)
+
+/** \brief 1254, Message Object Data Register High */
+#define CAN_MO18_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019254u)
+
+/** Alias (User Manual Name) for CAN_MO18_EDATA5.
+* To use register names with standard convension, please use CAN_MO18_EDATA5.
+*/
+#define CAN_EMO18DATA5 (CAN_MO18_EDATA5)
+
+/** \brief 1258, Message Object Arbitration Register */
+#define CAN_MO18_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019258u)
+
+/** Alias (User Manual Name) for CAN_MO18_EDATA6.
+* To use register names with standard convension, please use CAN_MO18_EDATA6.
+*/
+#define CAN_EMO18DATA6 (CAN_MO18_EDATA6)
+
+/** \brief 1240, Message Object Function Control Register */
+#define CAN_MO18_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019240u)
+
+/** Alias (User Manual Name) for CAN_MO18_FCR.
+* To use register names with standard convension, please use CAN_MO18_FCR.
+*/
+#define CAN_MOFCR18 (CAN_MO18_FCR)
+
+/** \brief 1244, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO18_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019244u)
+
+/** Alias (User Manual Name) for CAN_MO18_FGPR.
+* To use register names with standard convension, please use CAN_MO18_FGPR.
+*/
+#define CAN_MOFGPR18 (CAN_MO18_FGPR)
+
+/** \brief 1248, Message Object Interrupt Pointer Register */
+#define CAN_MO18_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019248u)
+
+/** Alias (User Manual Name) for CAN_MO18_IPR.
+* To use register names with standard convension, please use CAN_MO18_IPR.
+*/
+#define CAN_MOIPR18 (CAN_MO18_IPR)
+
+/** \brief 125C, Message Object Control Register */
+#define CAN_MO18_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001925Cu)
+
+/** Alias (User Manual Name) for CAN_MO18_STAT.
+* To use register names with standard convension, please use CAN_MO18_STAT.
+*/
+#define CAN_MOSTAT18 (CAN_MO18_STAT)
+
+/** \brief 27CC, Message Object Acceptance Mask Register */
+#define CAN_MO190_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A7CCu)
+
+/** Alias (User Manual Name) for CAN_MO190_AMR.
+* To use register names with standard convension, please use CAN_MO190_AMR.
+*/
+#define CAN_MOAMR190 (CAN_MO190_AMR)
+
+/** \brief 27D8, Message Object Arbitration Register */
+#define CAN_MO190_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A7D8u)
+
+/** Alias (User Manual Name) for CAN_MO190_AR.
+* To use register names with standard convension, please use CAN_MO190_AR.
+*/
+#define CAN_MOAR190 (CAN_MO190_AR)
+
+/** \brief 27DC, Message Object Control Register */
+#define CAN_MO190_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A7DCu)
+
+/** Alias (User Manual Name) for CAN_MO190_CTR.
+* To use register names with standard convension, please use CAN_MO190_CTR.
+*/
+#define CAN_MOCTR190 (CAN_MO190_CTR)
+
+/** \brief 27D4, Message Object Data Register High */
+#define CAN_MO190_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A7D4u)
+
+/** Alias (User Manual Name) for CAN_MO190_DATAH.
+* To use register names with standard convension, please use CAN_MO190_DATAH.
+*/
+#define CAN_MODATAH190 (CAN_MO190_DATAH)
+
+/** \brief 27D0, Message Object Data Register Low */
+#define CAN_MO190_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A7D0u)
+
+/** Alias (User Manual Name) for CAN_MO190_DATAL.
+* To use register names with standard convension, please use CAN_MO190_DATAL.
+*/
+#define CAN_MODATAL190 (CAN_MO190_DATAL)
+
+/** \brief 27C0, Message Object Function Control Register */
+#define CAN_MO190_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A7C0u)
+
+/** Alias (User Manual Name) for CAN_MO190_EDATA0.
+* To use register names with standard convension, please use CAN_MO190_EDATA0.
+*/
+#define CAN_EMO190DATA0 (CAN_MO190_EDATA0)
+
+/** \brief 27C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO190_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A7C4u)
+
+/** Alias (User Manual Name) for CAN_MO190_EDATA1.
+* To use register names with standard convension, please use CAN_MO190_EDATA1.
+*/
+#define CAN_EMO190DATA1 (CAN_MO190_EDATA1)
+
+/** \brief 27C8, Message Object Interrupt Pointer Register */
+#define CAN_MO190_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A7C8u)
+
+/** Alias (User Manual Name) for CAN_MO190_EDATA2.
+* To use register names with standard convension, please use CAN_MO190_EDATA2.
+*/
+#define CAN_EMO190DATA2 (CAN_MO190_EDATA2)
+
+/** \brief 27CC, Message Object Acceptance Mask Register */
+#define CAN_MO190_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A7CCu)
+
+/** Alias (User Manual Name) for CAN_MO190_EDATA3.
+* To use register names with standard convension, please use CAN_MO190_EDATA3.
+*/
+#define CAN_EMO190DATA3 (CAN_MO190_EDATA3)
+
+/** \brief 27D0, Message Object Data Register Low */
+#define CAN_MO190_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A7D0u)
+
+/** Alias (User Manual Name) for CAN_MO190_EDATA4.
+* To use register names with standard convension, please use CAN_MO190_EDATA4.
+*/
+#define CAN_EMO190DATA4 (CAN_MO190_EDATA4)
+
+/** \brief 27D4, Message Object Data Register High */
+#define CAN_MO190_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A7D4u)
+
+/** Alias (User Manual Name) for CAN_MO190_EDATA5.
+* To use register names with standard convension, please use CAN_MO190_EDATA5.
+*/
+#define CAN_EMO190DATA5 (CAN_MO190_EDATA5)
+
+/** \brief 27D8, Message Object Arbitration Register */
+#define CAN_MO190_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A7D8u)
+
+/** Alias (User Manual Name) for CAN_MO190_EDATA6.
+* To use register names with standard convension, please use CAN_MO190_EDATA6.
+*/
+#define CAN_EMO190DATA6 (CAN_MO190_EDATA6)
+
+/** \brief 27C0, Message Object Function Control Register */
+#define CAN_MO190_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A7C0u)
+
+/** Alias (User Manual Name) for CAN_MO190_FCR.
+* To use register names with standard convension, please use CAN_MO190_FCR.
+*/
+#define CAN_MOFCR190 (CAN_MO190_FCR)
+
+/** \brief 27C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO190_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A7C4u)
+
+/** Alias (User Manual Name) for CAN_MO190_FGPR.
+* To use register names with standard convension, please use CAN_MO190_FGPR.
+*/
+#define CAN_MOFGPR190 (CAN_MO190_FGPR)
+
+/** \brief 27C8, Message Object Interrupt Pointer Register */
+#define CAN_MO190_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A7C8u)
+
+/** Alias (User Manual Name) for CAN_MO190_IPR.
+* To use register names with standard convension, please use CAN_MO190_IPR.
+*/
+#define CAN_MOIPR190 (CAN_MO190_IPR)
+
+/** \brief 27DC, Message Object Control Register */
+#define CAN_MO190_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A7DCu)
+
+/** Alias (User Manual Name) for CAN_MO190_STAT.
+* To use register names with standard convension, please use CAN_MO190_STAT.
+*/
+#define CAN_MOSTAT190 (CAN_MO190_STAT)
+
+/** \brief 27EC, Message Object Acceptance Mask Register */
+#define CAN_MO191_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A7ECu)
+
+/** Alias (User Manual Name) for CAN_MO191_AMR.
+* To use register names with standard convension, please use CAN_MO191_AMR.
+*/
+#define CAN_MOAMR191 (CAN_MO191_AMR)
+
+/** \brief 27F8, Message Object Arbitration Register */
+#define CAN_MO191_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A7F8u)
+
+/** Alias (User Manual Name) for CAN_MO191_AR.
+* To use register names with standard convension, please use CAN_MO191_AR.
+*/
+#define CAN_MOAR191 (CAN_MO191_AR)
+
+/** \brief 27FC, Message Object Control Register */
+#define CAN_MO191_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A7FCu)
+
+/** Alias (User Manual Name) for CAN_MO191_CTR.
+* To use register names with standard convension, please use CAN_MO191_CTR.
+*/
+#define CAN_MOCTR191 (CAN_MO191_CTR)
+
+/** \brief 27F4, Message Object Data Register High */
+#define CAN_MO191_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A7F4u)
+
+/** Alias (User Manual Name) for CAN_MO191_DATAH.
+* To use register names with standard convension, please use CAN_MO191_DATAH.
+*/
+#define CAN_MODATAH191 (CAN_MO191_DATAH)
+
+/** \brief 27F0, Message Object Data Register Low */
+#define CAN_MO191_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A7F0u)
+
+/** Alias (User Manual Name) for CAN_MO191_DATAL.
+* To use register names with standard convension, please use CAN_MO191_DATAL.
+*/
+#define CAN_MODATAL191 (CAN_MO191_DATAL)
+
+/** \brief 27E0, Message Object Function Control Register */
+#define CAN_MO191_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A7E0u)
+
+/** Alias (User Manual Name) for CAN_MO191_EDATA0.
+* To use register names with standard convension, please use CAN_MO191_EDATA0.
+*/
+#define CAN_EMO191DATA0 (CAN_MO191_EDATA0)
+
+/** \brief 27E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO191_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A7E4u)
+
+/** Alias (User Manual Name) for CAN_MO191_EDATA1.
+* To use register names with standard convension, please use CAN_MO191_EDATA1.
+*/
+#define CAN_EMO191DATA1 (CAN_MO191_EDATA1)
+
+/** \brief 27E8, Message Object Interrupt Pointer Register */
+#define CAN_MO191_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A7E8u)
+
+/** Alias (User Manual Name) for CAN_MO191_EDATA2.
+* To use register names with standard convension, please use CAN_MO191_EDATA2.
+*/
+#define CAN_EMO191DATA2 (CAN_MO191_EDATA2)
+
+/** \brief 27EC, Message Object Acceptance Mask Register */
+#define CAN_MO191_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A7ECu)
+
+/** Alias (User Manual Name) for CAN_MO191_EDATA3.
+* To use register names with standard convension, please use CAN_MO191_EDATA3.
+*/
+#define CAN_EMO191DATA3 (CAN_MO191_EDATA3)
+
+/** \brief 27F0, Message Object Data Register Low */
+#define CAN_MO191_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A7F0u)
+
+/** Alias (User Manual Name) for CAN_MO191_EDATA4.
+* To use register names with standard convension, please use CAN_MO191_EDATA4.
+*/
+#define CAN_EMO191DATA4 (CAN_MO191_EDATA4)
+
+/** \brief 27F4, Message Object Data Register High */
+#define CAN_MO191_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A7F4u)
+
+/** Alias (User Manual Name) for CAN_MO191_EDATA5.
+* To use register names with standard convension, please use CAN_MO191_EDATA5.
+*/
+#define CAN_EMO191DATA5 (CAN_MO191_EDATA5)
+
+/** \brief 27F8, Message Object Arbitration Register */
+#define CAN_MO191_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A7F8u)
+
+/** Alias (User Manual Name) for CAN_MO191_EDATA6.
+* To use register names with standard convension, please use CAN_MO191_EDATA6.
+*/
+#define CAN_EMO191DATA6 (CAN_MO191_EDATA6)
+
+/** \brief 27E0, Message Object Function Control Register */
+#define CAN_MO191_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A7E0u)
+
+/** Alias (User Manual Name) for CAN_MO191_FCR.
+* To use register names with standard convension, please use CAN_MO191_FCR.
+*/
+#define CAN_MOFCR191 (CAN_MO191_FCR)
+
+/** \brief 27E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO191_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A7E4u)
+
+/** Alias (User Manual Name) for CAN_MO191_FGPR.
+* To use register names with standard convension, please use CAN_MO191_FGPR.
+*/
+#define CAN_MOFGPR191 (CAN_MO191_FGPR)
+
+/** \brief 27E8, Message Object Interrupt Pointer Register */
+#define CAN_MO191_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A7E8u)
+
+/** Alias (User Manual Name) for CAN_MO191_IPR.
+* To use register names with standard convension, please use CAN_MO191_IPR.
+*/
+#define CAN_MOIPR191 (CAN_MO191_IPR)
+
+/** \brief 27FC, Message Object Control Register */
+#define CAN_MO191_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A7FCu)
+
+/** Alias (User Manual Name) for CAN_MO191_STAT.
+* To use register names with standard convension, please use CAN_MO191_STAT.
+*/
+#define CAN_MOSTAT191 (CAN_MO191_STAT)
+
+/** \brief 280C, Message Object Acceptance Mask Register */
+#define CAN_MO192_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A80Cu)
+
+/** Alias (User Manual Name) for CAN_MO192_AMR.
+* To use register names with standard convension, please use CAN_MO192_AMR.
+*/
+#define CAN_MOAMR192 (CAN_MO192_AMR)
+
+/** \brief 2818, Message Object Arbitration Register */
+#define CAN_MO192_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A818u)
+
+/** Alias (User Manual Name) for CAN_MO192_AR.
+* To use register names with standard convension, please use CAN_MO192_AR.
+*/
+#define CAN_MOAR192 (CAN_MO192_AR)
+
+/** \brief 281C, Message Object Control Register */
+#define CAN_MO192_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A81Cu)
+
+/** Alias (User Manual Name) for CAN_MO192_CTR.
+* To use register names with standard convension, please use CAN_MO192_CTR.
+*/
+#define CAN_MOCTR192 (CAN_MO192_CTR)
+
+/** \brief 2814, Message Object Data Register High */
+#define CAN_MO192_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A814u)
+
+/** Alias (User Manual Name) for CAN_MO192_DATAH.
+* To use register names with standard convension, please use CAN_MO192_DATAH.
+*/
+#define CAN_MODATAH192 (CAN_MO192_DATAH)
+
+/** \brief 2810, Message Object Data Register Low */
+#define CAN_MO192_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A810u)
+
+/** Alias (User Manual Name) for CAN_MO192_DATAL.
+* To use register names with standard convension, please use CAN_MO192_DATAL.
+*/
+#define CAN_MODATAL192 (CAN_MO192_DATAL)
+
+/** \brief 2800, Message Object Function Control Register */
+#define CAN_MO192_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A800u)
+
+/** Alias (User Manual Name) for CAN_MO192_EDATA0.
+* To use register names with standard convension, please use CAN_MO192_EDATA0.
+*/
+#define CAN_EMO192DATA0 (CAN_MO192_EDATA0)
+
+/** \brief 2804, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO192_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A804u)
+
+/** Alias (User Manual Name) for CAN_MO192_EDATA1.
+* To use register names with standard convension, please use CAN_MO192_EDATA1.
+*/
+#define CAN_EMO192DATA1 (CAN_MO192_EDATA1)
+
+/** \brief 2808, Message Object Interrupt Pointer Register */
+#define CAN_MO192_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A808u)
+
+/** Alias (User Manual Name) for CAN_MO192_EDATA2.
+* To use register names with standard convension, please use CAN_MO192_EDATA2.
+*/
+#define CAN_EMO192DATA2 (CAN_MO192_EDATA2)
+
+/** \brief 280C, Message Object Acceptance Mask Register */
+#define CAN_MO192_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A80Cu)
+
+/** Alias (User Manual Name) for CAN_MO192_EDATA3.
+* To use register names with standard convension, please use CAN_MO192_EDATA3.
+*/
+#define CAN_EMO192DATA3 (CAN_MO192_EDATA3)
+
+/** \brief 2810, Message Object Data Register Low */
+#define CAN_MO192_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A810u)
+
+/** Alias (User Manual Name) for CAN_MO192_EDATA4.
+* To use register names with standard convension, please use CAN_MO192_EDATA4.
+*/
+#define CAN_EMO192DATA4 (CAN_MO192_EDATA4)
+
+/** \brief 2814, Message Object Data Register High */
+#define CAN_MO192_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A814u)
+
+/** Alias (User Manual Name) for CAN_MO192_EDATA5.
+* To use register names with standard convension, please use CAN_MO192_EDATA5.
+*/
+#define CAN_EMO192DATA5 (CAN_MO192_EDATA5)
+
+/** \brief 2818, Message Object Arbitration Register */
+#define CAN_MO192_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A818u)
+
+/** Alias (User Manual Name) for CAN_MO192_EDATA6.
+* To use register names with standard convension, please use CAN_MO192_EDATA6.
+*/
+#define CAN_EMO192DATA6 (CAN_MO192_EDATA6)
+
+/** \brief 2800, Message Object Function Control Register */
+#define CAN_MO192_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A800u)
+
+/** Alias (User Manual Name) for CAN_MO192_FCR.
+* To use register names with standard convension, please use CAN_MO192_FCR.
+*/
+#define CAN_MOFCR192 (CAN_MO192_FCR)
+
+/** \brief 2804, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO192_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A804u)
+
+/** Alias (User Manual Name) for CAN_MO192_FGPR.
+* To use register names with standard convension, please use CAN_MO192_FGPR.
+*/
+#define CAN_MOFGPR192 (CAN_MO192_FGPR)
+
+/** \brief 2808, Message Object Interrupt Pointer Register */
+#define CAN_MO192_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A808u)
+
+/** Alias (User Manual Name) for CAN_MO192_IPR.
+* To use register names with standard convension, please use CAN_MO192_IPR.
+*/
+#define CAN_MOIPR192 (CAN_MO192_IPR)
+
+/** \brief 281C, Message Object Control Register */
+#define CAN_MO192_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A81Cu)
+
+/** Alias (User Manual Name) for CAN_MO192_STAT.
+* To use register names with standard convension, please use CAN_MO192_STAT.
+*/
+#define CAN_MOSTAT192 (CAN_MO192_STAT)
+
+/** \brief 282C, Message Object Acceptance Mask Register */
+#define CAN_MO193_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A82Cu)
+
+/** Alias (User Manual Name) for CAN_MO193_AMR.
+* To use register names with standard convension, please use CAN_MO193_AMR.
+*/
+#define CAN_MOAMR193 (CAN_MO193_AMR)
+
+/** \brief 2838, Message Object Arbitration Register */
+#define CAN_MO193_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A838u)
+
+/** Alias (User Manual Name) for CAN_MO193_AR.
+* To use register names with standard convension, please use CAN_MO193_AR.
+*/
+#define CAN_MOAR193 (CAN_MO193_AR)
+
+/** \brief 283C, Message Object Control Register */
+#define CAN_MO193_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A83Cu)
+
+/** Alias (User Manual Name) for CAN_MO193_CTR.
+* To use register names with standard convension, please use CAN_MO193_CTR.
+*/
+#define CAN_MOCTR193 (CAN_MO193_CTR)
+
+/** \brief 2834, Message Object Data Register High */
+#define CAN_MO193_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A834u)
+
+/** Alias (User Manual Name) for CAN_MO193_DATAH.
+* To use register names with standard convension, please use CAN_MO193_DATAH.
+*/
+#define CAN_MODATAH193 (CAN_MO193_DATAH)
+
+/** \brief 2830, Message Object Data Register Low */
+#define CAN_MO193_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A830u)
+
+/** Alias (User Manual Name) for CAN_MO193_DATAL.
+* To use register names with standard convension, please use CAN_MO193_DATAL.
+*/
+#define CAN_MODATAL193 (CAN_MO193_DATAL)
+
+/** \brief 2820, Message Object Function Control Register */
+#define CAN_MO193_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A820u)
+
+/** Alias (User Manual Name) for CAN_MO193_EDATA0.
+* To use register names with standard convension, please use CAN_MO193_EDATA0.
+*/
+#define CAN_EMO193DATA0 (CAN_MO193_EDATA0)
+
+/** \brief 2824, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO193_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A824u)
+
+/** Alias (User Manual Name) for CAN_MO193_EDATA1.
+* To use register names with standard convension, please use CAN_MO193_EDATA1.
+*/
+#define CAN_EMO193DATA1 (CAN_MO193_EDATA1)
+
+/** \brief 2828, Message Object Interrupt Pointer Register */
+#define CAN_MO193_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A828u)
+
+/** Alias (User Manual Name) for CAN_MO193_EDATA2.
+* To use register names with standard convension, please use CAN_MO193_EDATA2.
+*/
+#define CAN_EMO193DATA2 (CAN_MO193_EDATA2)
+
+/** \brief 282C, Message Object Acceptance Mask Register */
+#define CAN_MO193_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A82Cu)
+
+/** Alias (User Manual Name) for CAN_MO193_EDATA3.
+* To use register names with standard convension, please use CAN_MO193_EDATA3.
+*/
+#define CAN_EMO193DATA3 (CAN_MO193_EDATA3)
+
+/** \brief 2830, Message Object Data Register Low */
+#define CAN_MO193_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A830u)
+
+/** Alias (User Manual Name) for CAN_MO193_EDATA4.
+* To use register names with standard convension, please use CAN_MO193_EDATA4.
+*/
+#define CAN_EMO193DATA4 (CAN_MO193_EDATA4)
+
+/** \brief 2834, Message Object Data Register High */
+#define CAN_MO193_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A834u)
+
+/** Alias (User Manual Name) for CAN_MO193_EDATA5.
+* To use register names with standard convension, please use CAN_MO193_EDATA5.
+*/
+#define CAN_EMO193DATA5 (CAN_MO193_EDATA5)
+
+/** \brief 2838, Message Object Arbitration Register */
+#define CAN_MO193_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A838u)
+
+/** Alias (User Manual Name) for CAN_MO193_EDATA6.
+* To use register names with standard convension, please use CAN_MO193_EDATA6.
+*/
+#define CAN_EMO193DATA6 (CAN_MO193_EDATA6)
+
+/** \brief 2820, Message Object Function Control Register */
+#define CAN_MO193_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A820u)
+
+/** Alias (User Manual Name) for CAN_MO193_FCR.
+* To use register names with standard convension, please use CAN_MO193_FCR.
+*/
+#define CAN_MOFCR193 (CAN_MO193_FCR)
+
+/** \brief 2824, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO193_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A824u)
+
+/** Alias (User Manual Name) for CAN_MO193_FGPR.
+* To use register names with standard convension, please use CAN_MO193_FGPR.
+*/
+#define CAN_MOFGPR193 (CAN_MO193_FGPR)
+
+/** \brief 2828, Message Object Interrupt Pointer Register */
+#define CAN_MO193_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A828u)
+
+/** Alias (User Manual Name) for CAN_MO193_IPR.
+* To use register names with standard convension, please use CAN_MO193_IPR.
+*/
+#define CAN_MOIPR193 (CAN_MO193_IPR)
+
+/** \brief 283C, Message Object Control Register */
+#define CAN_MO193_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A83Cu)
+
+/** Alias (User Manual Name) for CAN_MO193_STAT.
+* To use register names with standard convension, please use CAN_MO193_STAT.
+*/
+#define CAN_MOSTAT193 (CAN_MO193_STAT)
+
+/** \brief 284C, Message Object Acceptance Mask Register */
+#define CAN_MO194_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A84Cu)
+
+/** Alias (User Manual Name) for CAN_MO194_AMR.
+* To use register names with standard convension, please use CAN_MO194_AMR.
+*/
+#define CAN_MOAMR194 (CAN_MO194_AMR)
+
+/** \brief 2858, Message Object Arbitration Register */
+#define CAN_MO194_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A858u)
+
+/** Alias (User Manual Name) for CAN_MO194_AR.
+* To use register names with standard convension, please use CAN_MO194_AR.
+*/
+#define CAN_MOAR194 (CAN_MO194_AR)
+
+/** \brief 285C, Message Object Control Register */
+#define CAN_MO194_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A85Cu)
+
+/** Alias (User Manual Name) for CAN_MO194_CTR.
+* To use register names with standard convension, please use CAN_MO194_CTR.
+*/
+#define CAN_MOCTR194 (CAN_MO194_CTR)
+
+/** \brief 2854, Message Object Data Register High */
+#define CAN_MO194_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A854u)
+
+/** Alias (User Manual Name) for CAN_MO194_DATAH.
+* To use register names with standard convension, please use CAN_MO194_DATAH.
+*/
+#define CAN_MODATAH194 (CAN_MO194_DATAH)
+
+/** \brief 2850, Message Object Data Register Low */
+#define CAN_MO194_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A850u)
+
+/** Alias (User Manual Name) for CAN_MO194_DATAL.
+* To use register names with standard convension, please use CAN_MO194_DATAL.
+*/
+#define CAN_MODATAL194 (CAN_MO194_DATAL)
+
+/** \brief 2840, Message Object Function Control Register */
+#define CAN_MO194_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A840u)
+
+/** Alias (User Manual Name) for CAN_MO194_EDATA0.
+* To use register names with standard convension, please use CAN_MO194_EDATA0.
+*/
+#define CAN_EMO194DATA0 (CAN_MO194_EDATA0)
+
+/** \brief 2844, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO194_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A844u)
+
+/** Alias (User Manual Name) for CAN_MO194_EDATA1.
+* To use register names with standard convension, please use CAN_MO194_EDATA1.
+*/
+#define CAN_EMO194DATA1 (CAN_MO194_EDATA1)
+
+/** \brief 2848, Message Object Interrupt Pointer Register */
+#define CAN_MO194_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A848u)
+
+/** Alias (User Manual Name) for CAN_MO194_EDATA2.
+* To use register names with standard convension, please use CAN_MO194_EDATA2.
+*/
+#define CAN_EMO194DATA2 (CAN_MO194_EDATA2)
+
+/** \brief 284C, Message Object Acceptance Mask Register */
+#define CAN_MO194_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A84Cu)
+
+/** Alias (User Manual Name) for CAN_MO194_EDATA3.
+* To use register names with standard convension, please use CAN_MO194_EDATA3.
+*/
+#define CAN_EMO194DATA3 (CAN_MO194_EDATA3)
+
+/** \brief 2850, Message Object Data Register Low */
+#define CAN_MO194_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A850u)
+
+/** Alias (User Manual Name) for CAN_MO194_EDATA4.
+* To use register names with standard convension, please use CAN_MO194_EDATA4.
+*/
+#define CAN_EMO194DATA4 (CAN_MO194_EDATA4)
+
+/** \brief 2854, Message Object Data Register High */
+#define CAN_MO194_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A854u)
+
+/** Alias (User Manual Name) for CAN_MO194_EDATA5.
+* To use register names with standard convension, please use CAN_MO194_EDATA5.
+*/
+#define CAN_EMO194DATA5 (CAN_MO194_EDATA5)
+
+/** \brief 2858, Message Object Arbitration Register */
+#define CAN_MO194_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A858u)
+
+/** Alias (User Manual Name) for CAN_MO194_EDATA6.
+* To use register names with standard convension, please use CAN_MO194_EDATA6.
+*/
+#define CAN_EMO194DATA6 (CAN_MO194_EDATA6)
+
+/** \brief 2840, Message Object Function Control Register */
+#define CAN_MO194_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A840u)
+
+/** Alias (User Manual Name) for CAN_MO194_FCR.
+* To use register names with standard convension, please use CAN_MO194_FCR.
+*/
+#define CAN_MOFCR194 (CAN_MO194_FCR)
+
+/** \brief 2844, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO194_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A844u)
+
+/** Alias (User Manual Name) for CAN_MO194_FGPR.
+* To use register names with standard convension, please use CAN_MO194_FGPR.
+*/
+#define CAN_MOFGPR194 (CAN_MO194_FGPR)
+
+/** \brief 2848, Message Object Interrupt Pointer Register */
+#define CAN_MO194_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A848u)
+
+/** Alias (User Manual Name) for CAN_MO194_IPR.
+* To use register names with standard convension, please use CAN_MO194_IPR.
+*/
+#define CAN_MOIPR194 (CAN_MO194_IPR)
+
+/** \brief 285C, Message Object Control Register */
+#define CAN_MO194_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A85Cu)
+
+/** Alias (User Manual Name) for CAN_MO194_STAT.
+* To use register names with standard convension, please use CAN_MO194_STAT.
+*/
+#define CAN_MOSTAT194 (CAN_MO194_STAT)
+
+/** \brief 286C, Message Object Acceptance Mask Register */
+#define CAN_MO195_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A86Cu)
+
+/** Alias (User Manual Name) for CAN_MO195_AMR.
+* To use register names with standard convension, please use CAN_MO195_AMR.
+*/
+#define CAN_MOAMR195 (CAN_MO195_AMR)
+
+/** \brief 2878, Message Object Arbitration Register */
+#define CAN_MO195_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A878u)
+
+/** Alias (User Manual Name) for CAN_MO195_AR.
+* To use register names with standard convension, please use CAN_MO195_AR.
+*/
+#define CAN_MOAR195 (CAN_MO195_AR)
+
+/** \brief 287C, Message Object Control Register */
+#define CAN_MO195_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A87Cu)
+
+/** Alias (User Manual Name) for CAN_MO195_CTR.
+* To use register names with standard convension, please use CAN_MO195_CTR.
+*/
+#define CAN_MOCTR195 (CAN_MO195_CTR)
+
+/** \brief 2874, Message Object Data Register High */
+#define CAN_MO195_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A874u)
+
+/** Alias (User Manual Name) for CAN_MO195_DATAH.
+* To use register names with standard convension, please use CAN_MO195_DATAH.
+*/
+#define CAN_MODATAH195 (CAN_MO195_DATAH)
+
+/** \brief 2870, Message Object Data Register Low */
+#define CAN_MO195_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A870u)
+
+/** Alias (User Manual Name) for CAN_MO195_DATAL.
+* To use register names with standard convension, please use CAN_MO195_DATAL.
+*/
+#define CAN_MODATAL195 (CAN_MO195_DATAL)
+
+/** \brief 2860, Message Object Function Control Register */
+#define CAN_MO195_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A860u)
+
+/** Alias (User Manual Name) for CAN_MO195_EDATA0.
+* To use register names with standard convension, please use CAN_MO195_EDATA0.
+*/
+#define CAN_EMO195DATA0 (CAN_MO195_EDATA0)
+
+/** \brief 2864, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO195_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A864u)
+
+/** Alias (User Manual Name) for CAN_MO195_EDATA1.
+* To use register names with standard convension, please use CAN_MO195_EDATA1.
+*/
+#define CAN_EMO195DATA1 (CAN_MO195_EDATA1)
+
+/** \brief 2868, Message Object Interrupt Pointer Register */
+#define CAN_MO195_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A868u)
+
+/** Alias (User Manual Name) for CAN_MO195_EDATA2.
+* To use register names with standard convension, please use CAN_MO195_EDATA2.
+*/
+#define CAN_EMO195DATA2 (CAN_MO195_EDATA2)
+
+/** \brief 286C, Message Object Acceptance Mask Register */
+#define CAN_MO195_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A86Cu)
+
+/** Alias (User Manual Name) for CAN_MO195_EDATA3.
+* To use register names with standard convension, please use CAN_MO195_EDATA3.
+*/
+#define CAN_EMO195DATA3 (CAN_MO195_EDATA3)
+
+/** \brief 2870, Message Object Data Register Low */
+#define CAN_MO195_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A870u)
+
+/** Alias (User Manual Name) for CAN_MO195_EDATA4.
+* To use register names with standard convension, please use CAN_MO195_EDATA4.
+*/
+#define CAN_EMO195DATA4 (CAN_MO195_EDATA4)
+
+/** \brief 2874, Message Object Data Register High */
+#define CAN_MO195_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A874u)
+
+/** Alias (User Manual Name) for CAN_MO195_EDATA5.
+* To use register names with standard convension, please use CAN_MO195_EDATA5.
+*/
+#define CAN_EMO195DATA5 (CAN_MO195_EDATA5)
+
+/** \brief 2878, Message Object Arbitration Register */
+#define CAN_MO195_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A878u)
+
+/** Alias (User Manual Name) for CAN_MO195_EDATA6.
+* To use register names with standard convension, please use CAN_MO195_EDATA6.
+*/
+#define CAN_EMO195DATA6 (CAN_MO195_EDATA6)
+
+/** \brief 2860, Message Object Function Control Register */
+#define CAN_MO195_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A860u)
+
+/** Alias (User Manual Name) for CAN_MO195_FCR.
+* To use register names with standard convension, please use CAN_MO195_FCR.
+*/
+#define CAN_MOFCR195 (CAN_MO195_FCR)
+
+/** \brief 2864, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO195_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A864u)
+
+/** Alias (User Manual Name) for CAN_MO195_FGPR.
+* To use register names with standard convension, please use CAN_MO195_FGPR.
+*/
+#define CAN_MOFGPR195 (CAN_MO195_FGPR)
+
+/** \brief 2868, Message Object Interrupt Pointer Register */
+#define CAN_MO195_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A868u)
+
+/** Alias (User Manual Name) for CAN_MO195_IPR.
+* To use register names with standard convension, please use CAN_MO195_IPR.
+*/
+#define CAN_MOIPR195 (CAN_MO195_IPR)
+
+/** \brief 287C, Message Object Control Register */
+#define CAN_MO195_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A87Cu)
+
+/** Alias (User Manual Name) for CAN_MO195_STAT.
+* To use register names with standard convension, please use CAN_MO195_STAT.
+*/
+#define CAN_MOSTAT195 (CAN_MO195_STAT)
+
+/** \brief 288C, Message Object Acceptance Mask Register */
+#define CAN_MO196_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A88Cu)
+
+/** Alias (User Manual Name) for CAN_MO196_AMR.
+* To use register names with standard convension, please use CAN_MO196_AMR.
+*/
+#define CAN_MOAMR196 (CAN_MO196_AMR)
+
+/** \brief 2898, Message Object Arbitration Register */
+#define CAN_MO196_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A898u)
+
+/** Alias (User Manual Name) for CAN_MO196_AR.
+* To use register names with standard convension, please use CAN_MO196_AR.
+*/
+#define CAN_MOAR196 (CAN_MO196_AR)
+
+/** \brief 289C, Message Object Control Register */
+#define CAN_MO196_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A89Cu)
+
+/** Alias (User Manual Name) for CAN_MO196_CTR.
+* To use register names with standard convension, please use CAN_MO196_CTR.
+*/
+#define CAN_MOCTR196 (CAN_MO196_CTR)
+
+/** \brief 2894, Message Object Data Register High */
+#define CAN_MO196_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A894u)
+
+/** Alias (User Manual Name) for CAN_MO196_DATAH.
+* To use register names with standard convension, please use CAN_MO196_DATAH.
+*/
+#define CAN_MODATAH196 (CAN_MO196_DATAH)
+
+/** \brief 2890, Message Object Data Register Low */
+#define CAN_MO196_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A890u)
+
+/** Alias (User Manual Name) for CAN_MO196_DATAL.
+* To use register names with standard convension, please use CAN_MO196_DATAL.
+*/
+#define CAN_MODATAL196 (CAN_MO196_DATAL)
+
+/** \brief 2880, Message Object Function Control Register */
+#define CAN_MO196_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A880u)
+
+/** Alias (User Manual Name) for CAN_MO196_EDATA0.
+* To use register names with standard convension, please use CAN_MO196_EDATA0.
+*/
+#define CAN_EMO196DATA0 (CAN_MO196_EDATA0)
+
+/** \brief 2884, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO196_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A884u)
+
+/** Alias (User Manual Name) for CAN_MO196_EDATA1.
+* To use register names with standard convension, please use CAN_MO196_EDATA1.
+*/
+#define CAN_EMO196DATA1 (CAN_MO196_EDATA1)
+
+/** \brief 2888, Message Object Interrupt Pointer Register */
+#define CAN_MO196_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A888u)
+
+/** Alias (User Manual Name) for CAN_MO196_EDATA2.
+* To use register names with standard convension, please use CAN_MO196_EDATA2.
+*/
+#define CAN_EMO196DATA2 (CAN_MO196_EDATA2)
+
+/** \brief 288C, Message Object Acceptance Mask Register */
+#define CAN_MO196_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A88Cu)
+
+/** Alias (User Manual Name) for CAN_MO196_EDATA3.
+* To use register names with standard convension, please use CAN_MO196_EDATA3.
+*/
+#define CAN_EMO196DATA3 (CAN_MO196_EDATA3)
+
+/** \brief 2890, Message Object Data Register Low */
+#define CAN_MO196_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A890u)
+
+/** Alias (User Manual Name) for CAN_MO196_EDATA4.
+* To use register names with standard convension, please use CAN_MO196_EDATA4.
+*/
+#define CAN_EMO196DATA4 (CAN_MO196_EDATA4)
+
+/** \brief 2894, Message Object Data Register High */
+#define CAN_MO196_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A894u)
+
+/** Alias (User Manual Name) for CAN_MO196_EDATA5.
+* To use register names with standard convension, please use CAN_MO196_EDATA5.
+*/
+#define CAN_EMO196DATA5 (CAN_MO196_EDATA5)
+
+/** \brief 2898, Message Object Arbitration Register */
+#define CAN_MO196_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A898u)
+
+/** Alias (User Manual Name) for CAN_MO196_EDATA6.
+* To use register names with standard convension, please use CAN_MO196_EDATA6.
+*/
+#define CAN_EMO196DATA6 (CAN_MO196_EDATA6)
+
+/** \brief 2880, Message Object Function Control Register */
+#define CAN_MO196_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A880u)
+
+/** Alias (User Manual Name) for CAN_MO196_FCR.
+* To use register names with standard convension, please use CAN_MO196_FCR.
+*/
+#define CAN_MOFCR196 (CAN_MO196_FCR)
+
+/** \brief 2884, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO196_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A884u)
+
+/** Alias (User Manual Name) for CAN_MO196_FGPR.
+* To use register names with standard convension, please use CAN_MO196_FGPR.
+*/
+#define CAN_MOFGPR196 (CAN_MO196_FGPR)
+
+/** \brief 2888, Message Object Interrupt Pointer Register */
+#define CAN_MO196_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A888u)
+
+/** Alias (User Manual Name) for CAN_MO196_IPR.
+* To use register names with standard convension, please use CAN_MO196_IPR.
+*/
+#define CAN_MOIPR196 (CAN_MO196_IPR)
+
+/** \brief 289C, Message Object Control Register */
+#define CAN_MO196_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A89Cu)
+
+/** Alias (User Manual Name) for CAN_MO196_STAT.
+* To use register names with standard convension, please use CAN_MO196_STAT.
+*/
+#define CAN_MOSTAT196 (CAN_MO196_STAT)
+
+/** \brief 28AC, Message Object Acceptance Mask Register */
+#define CAN_MO197_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A8ACu)
+
+/** Alias (User Manual Name) for CAN_MO197_AMR.
+* To use register names with standard convension, please use CAN_MO197_AMR.
+*/
+#define CAN_MOAMR197 (CAN_MO197_AMR)
+
+/** \brief 28B8, Message Object Arbitration Register */
+#define CAN_MO197_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A8B8u)
+
+/** Alias (User Manual Name) for CAN_MO197_AR.
+* To use register names with standard convension, please use CAN_MO197_AR.
+*/
+#define CAN_MOAR197 (CAN_MO197_AR)
+
+/** \brief 28BC, Message Object Control Register */
+#define CAN_MO197_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A8BCu)
+
+/** Alias (User Manual Name) for CAN_MO197_CTR.
+* To use register names with standard convension, please use CAN_MO197_CTR.
+*/
+#define CAN_MOCTR197 (CAN_MO197_CTR)
+
+/** \brief 28B4, Message Object Data Register High */
+#define CAN_MO197_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A8B4u)
+
+/** Alias (User Manual Name) for CAN_MO197_DATAH.
+* To use register names with standard convension, please use CAN_MO197_DATAH.
+*/
+#define CAN_MODATAH197 (CAN_MO197_DATAH)
+
+/** \brief 28B0, Message Object Data Register Low */
+#define CAN_MO197_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A8B0u)
+
+/** Alias (User Manual Name) for CAN_MO197_DATAL.
+* To use register names with standard convension, please use CAN_MO197_DATAL.
+*/
+#define CAN_MODATAL197 (CAN_MO197_DATAL)
+
+/** \brief 28A0, Message Object Function Control Register */
+#define CAN_MO197_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A8A0u)
+
+/** Alias (User Manual Name) for CAN_MO197_EDATA0.
+* To use register names with standard convension, please use CAN_MO197_EDATA0.
+*/
+#define CAN_EMO197DATA0 (CAN_MO197_EDATA0)
+
+/** \brief 28A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO197_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A8A4u)
+
+/** Alias (User Manual Name) for CAN_MO197_EDATA1.
+* To use register names with standard convension, please use CAN_MO197_EDATA1.
+*/
+#define CAN_EMO197DATA1 (CAN_MO197_EDATA1)
+
+/** \brief 28A8, Message Object Interrupt Pointer Register */
+#define CAN_MO197_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A8A8u)
+
+/** Alias (User Manual Name) for CAN_MO197_EDATA2.
+* To use register names with standard convension, please use CAN_MO197_EDATA2.
+*/
+#define CAN_EMO197DATA2 (CAN_MO197_EDATA2)
+
+/** \brief 28AC, Message Object Acceptance Mask Register */
+#define CAN_MO197_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A8ACu)
+
+/** Alias (User Manual Name) for CAN_MO197_EDATA3.
+* To use register names with standard convension, please use CAN_MO197_EDATA3.
+*/
+#define CAN_EMO197DATA3 (CAN_MO197_EDATA3)
+
+/** \brief 28B0, Message Object Data Register Low */
+#define CAN_MO197_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A8B0u)
+
+/** Alias (User Manual Name) for CAN_MO197_EDATA4.
+* To use register names with standard convension, please use CAN_MO197_EDATA4.
+*/
+#define CAN_EMO197DATA4 (CAN_MO197_EDATA4)
+
+/** \brief 28B4, Message Object Data Register High */
+#define CAN_MO197_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A8B4u)
+
+/** Alias (User Manual Name) for CAN_MO197_EDATA5.
+* To use register names with standard convension, please use CAN_MO197_EDATA5.
+*/
+#define CAN_EMO197DATA5 (CAN_MO197_EDATA5)
+
+/** \brief 28B8, Message Object Arbitration Register */
+#define CAN_MO197_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A8B8u)
+
+/** Alias (User Manual Name) for CAN_MO197_EDATA6.
+* To use register names with standard convension, please use CAN_MO197_EDATA6.
+*/
+#define CAN_EMO197DATA6 (CAN_MO197_EDATA6)
+
+/** \brief 28A0, Message Object Function Control Register */
+#define CAN_MO197_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A8A0u)
+
+/** Alias (User Manual Name) for CAN_MO197_FCR.
+* To use register names with standard convension, please use CAN_MO197_FCR.
+*/
+#define CAN_MOFCR197 (CAN_MO197_FCR)
+
+/** \brief 28A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO197_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A8A4u)
+
+/** Alias (User Manual Name) for CAN_MO197_FGPR.
+* To use register names with standard convension, please use CAN_MO197_FGPR.
+*/
+#define CAN_MOFGPR197 (CAN_MO197_FGPR)
+
+/** \brief 28A8, Message Object Interrupt Pointer Register */
+#define CAN_MO197_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A8A8u)
+
+/** Alias (User Manual Name) for CAN_MO197_IPR.
+* To use register names with standard convension, please use CAN_MO197_IPR.
+*/
+#define CAN_MOIPR197 (CAN_MO197_IPR)
+
+/** \brief 28BC, Message Object Control Register */
+#define CAN_MO197_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A8BCu)
+
+/** Alias (User Manual Name) for CAN_MO197_STAT.
+* To use register names with standard convension, please use CAN_MO197_STAT.
+*/
+#define CAN_MOSTAT197 (CAN_MO197_STAT)
+
+/** \brief 28CC, Message Object Acceptance Mask Register */
+#define CAN_MO198_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A8CCu)
+
+/** Alias (User Manual Name) for CAN_MO198_AMR.
+* To use register names with standard convension, please use CAN_MO198_AMR.
+*/
+#define CAN_MOAMR198 (CAN_MO198_AMR)
+
+/** \brief 28D8, Message Object Arbitration Register */
+#define CAN_MO198_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A8D8u)
+
+/** Alias (User Manual Name) for CAN_MO198_AR.
+* To use register names with standard convension, please use CAN_MO198_AR.
+*/
+#define CAN_MOAR198 (CAN_MO198_AR)
+
+/** \brief 28DC, Message Object Control Register */
+#define CAN_MO198_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A8DCu)
+
+/** Alias (User Manual Name) for CAN_MO198_CTR.
+* To use register names with standard convension, please use CAN_MO198_CTR.
+*/
+#define CAN_MOCTR198 (CAN_MO198_CTR)
+
+/** \brief 28D4, Message Object Data Register High */
+#define CAN_MO198_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A8D4u)
+
+/** Alias (User Manual Name) for CAN_MO198_DATAH.
+* To use register names with standard convension, please use CAN_MO198_DATAH.
+*/
+#define CAN_MODATAH198 (CAN_MO198_DATAH)
+
+/** \brief 28D0, Message Object Data Register Low */
+#define CAN_MO198_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A8D0u)
+
+/** Alias (User Manual Name) for CAN_MO198_DATAL.
+* To use register names with standard convension, please use CAN_MO198_DATAL.
+*/
+#define CAN_MODATAL198 (CAN_MO198_DATAL)
+
+/** \brief 28C0, Message Object Function Control Register */
+#define CAN_MO198_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A8C0u)
+
+/** Alias (User Manual Name) for CAN_MO198_EDATA0.
+* To use register names with standard convension, please use CAN_MO198_EDATA0.
+*/
+#define CAN_EMO198DATA0 (CAN_MO198_EDATA0)
+
+/** \brief 28C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO198_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A8C4u)
+
+/** Alias (User Manual Name) for CAN_MO198_EDATA1.
+* To use register names with standard convension, please use CAN_MO198_EDATA1.
+*/
+#define CAN_EMO198DATA1 (CAN_MO198_EDATA1)
+
+/** \brief 28C8, Message Object Interrupt Pointer Register */
+#define CAN_MO198_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A8C8u)
+
+/** Alias (User Manual Name) for CAN_MO198_EDATA2.
+* To use register names with standard convension, please use CAN_MO198_EDATA2.
+*/
+#define CAN_EMO198DATA2 (CAN_MO198_EDATA2)
+
+/** \brief 28CC, Message Object Acceptance Mask Register */
+#define CAN_MO198_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A8CCu)
+
+/** Alias (User Manual Name) for CAN_MO198_EDATA3.
+* To use register names with standard convension, please use CAN_MO198_EDATA3.
+*/
+#define CAN_EMO198DATA3 (CAN_MO198_EDATA3)
+
+/** \brief 28D0, Message Object Data Register Low */
+#define CAN_MO198_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A8D0u)
+
+/** Alias (User Manual Name) for CAN_MO198_EDATA4.
+* To use register names with standard convension, please use CAN_MO198_EDATA4.
+*/
+#define CAN_EMO198DATA4 (CAN_MO198_EDATA4)
+
+/** \brief 28D4, Message Object Data Register High */
+#define CAN_MO198_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A8D4u)
+
+/** Alias (User Manual Name) for CAN_MO198_EDATA5.
+* To use register names with standard convension, please use CAN_MO198_EDATA5.
+*/
+#define CAN_EMO198DATA5 (CAN_MO198_EDATA5)
+
+/** \brief 28D8, Message Object Arbitration Register */
+#define CAN_MO198_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A8D8u)
+
+/** Alias (User Manual Name) for CAN_MO198_EDATA6.
+* To use register names with standard convension, please use CAN_MO198_EDATA6.
+*/
+#define CAN_EMO198DATA6 (CAN_MO198_EDATA6)
+
+/** \brief 28C0, Message Object Function Control Register */
+#define CAN_MO198_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A8C0u)
+
+/** Alias (User Manual Name) for CAN_MO198_FCR.
+* To use register names with standard convension, please use CAN_MO198_FCR.
+*/
+#define CAN_MOFCR198 (CAN_MO198_FCR)
+
+/** \brief 28C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO198_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A8C4u)
+
+/** Alias (User Manual Name) for CAN_MO198_FGPR.
+* To use register names with standard convension, please use CAN_MO198_FGPR.
+*/
+#define CAN_MOFGPR198 (CAN_MO198_FGPR)
+
+/** \brief 28C8, Message Object Interrupt Pointer Register */
+#define CAN_MO198_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A8C8u)
+
+/** Alias (User Manual Name) for CAN_MO198_IPR.
+* To use register names with standard convension, please use CAN_MO198_IPR.
+*/
+#define CAN_MOIPR198 (CAN_MO198_IPR)
+
+/** \brief 28DC, Message Object Control Register */
+#define CAN_MO198_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A8DCu)
+
+/** Alias (User Manual Name) for CAN_MO198_STAT.
+* To use register names with standard convension, please use CAN_MO198_STAT.
+*/
+#define CAN_MOSTAT198 (CAN_MO198_STAT)
+
+/** \brief 28EC, Message Object Acceptance Mask Register */
+#define CAN_MO199_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A8ECu)
+
+/** Alias (User Manual Name) for CAN_MO199_AMR.
+* To use register names with standard convension, please use CAN_MO199_AMR.
+*/
+#define CAN_MOAMR199 (CAN_MO199_AMR)
+
+/** \brief 28F8, Message Object Arbitration Register */
+#define CAN_MO199_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A8F8u)
+
+/** Alias (User Manual Name) for CAN_MO199_AR.
+* To use register names with standard convension, please use CAN_MO199_AR.
+*/
+#define CAN_MOAR199 (CAN_MO199_AR)
+
+/** \brief 28FC, Message Object Control Register */
+#define CAN_MO199_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A8FCu)
+
+/** Alias (User Manual Name) for CAN_MO199_CTR.
+* To use register names with standard convension, please use CAN_MO199_CTR.
+*/
+#define CAN_MOCTR199 (CAN_MO199_CTR)
+
+/** \brief 28F4, Message Object Data Register High */
+#define CAN_MO199_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A8F4u)
+
+/** Alias (User Manual Name) for CAN_MO199_DATAH.
+* To use register names with standard convension, please use CAN_MO199_DATAH.
+*/
+#define CAN_MODATAH199 (CAN_MO199_DATAH)
+
+/** \brief 28F0, Message Object Data Register Low */
+#define CAN_MO199_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A8F0u)
+
+/** Alias (User Manual Name) for CAN_MO199_DATAL.
+* To use register names with standard convension, please use CAN_MO199_DATAL.
+*/
+#define CAN_MODATAL199 (CAN_MO199_DATAL)
+
+/** \brief 28E0, Message Object Function Control Register */
+#define CAN_MO199_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A8E0u)
+
+/** Alias (User Manual Name) for CAN_MO199_EDATA0.
+* To use register names with standard convension, please use CAN_MO199_EDATA0.
+*/
+#define CAN_EMO199DATA0 (CAN_MO199_EDATA0)
+
+/** \brief 28E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO199_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A8E4u)
+
+/** Alias (User Manual Name) for CAN_MO199_EDATA1.
+* To use register names with standard convension, please use CAN_MO199_EDATA1.
+*/
+#define CAN_EMO199DATA1 (CAN_MO199_EDATA1)
+
+/** \brief 28E8, Message Object Interrupt Pointer Register */
+#define CAN_MO199_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A8E8u)
+
+/** Alias (User Manual Name) for CAN_MO199_EDATA2.
+* To use register names with standard convension, please use CAN_MO199_EDATA2.
+*/
+#define CAN_EMO199DATA2 (CAN_MO199_EDATA2)
+
+/** \brief 28EC, Message Object Acceptance Mask Register */
+#define CAN_MO199_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A8ECu)
+
+/** Alias (User Manual Name) for CAN_MO199_EDATA3.
+* To use register names with standard convension, please use CAN_MO199_EDATA3.
+*/
+#define CAN_EMO199DATA3 (CAN_MO199_EDATA3)
+
+/** \brief 28F0, Message Object Data Register Low */
+#define CAN_MO199_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A8F0u)
+
+/** Alias (User Manual Name) for CAN_MO199_EDATA4.
+* To use register names with standard convension, please use CAN_MO199_EDATA4.
+*/
+#define CAN_EMO199DATA4 (CAN_MO199_EDATA4)
+
+/** \brief 28F4, Message Object Data Register High */
+#define CAN_MO199_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A8F4u)
+
+/** Alias (User Manual Name) for CAN_MO199_EDATA5.
+* To use register names with standard convension, please use CAN_MO199_EDATA5.
+*/
+#define CAN_EMO199DATA5 (CAN_MO199_EDATA5)
+
+/** \brief 28F8, Message Object Arbitration Register */
+#define CAN_MO199_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A8F8u)
+
+/** Alias (User Manual Name) for CAN_MO199_EDATA6.
+* To use register names with standard convension, please use CAN_MO199_EDATA6.
+*/
+#define CAN_EMO199DATA6 (CAN_MO199_EDATA6)
+
+/** \brief 28E0, Message Object Function Control Register */
+#define CAN_MO199_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A8E0u)
+
+/** Alias (User Manual Name) for CAN_MO199_FCR.
+* To use register names with standard convension, please use CAN_MO199_FCR.
+*/
+#define CAN_MOFCR199 (CAN_MO199_FCR)
+
+/** \brief 28E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO199_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A8E4u)
+
+/** Alias (User Manual Name) for CAN_MO199_FGPR.
+* To use register names with standard convension, please use CAN_MO199_FGPR.
+*/
+#define CAN_MOFGPR199 (CAN_MO199_FGPR)
+
+/** \brief 28E8, Message Object Interrupt Pointer Register */
+#define CAN_MO199_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A8E8u)
+
+/** Alias (User Manual Name) for CAN_MO199_IPR.
+* To use register names with standard convension, please use CAN_MO199_IPR.
+*/
+#define CAN_MOIPR199 (CAN_MO199_IPR)
+
+/** \brief 28FC, Message Object Control Register */
+#define CAN_MO199_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A8FCu)
+
+/** Alias (User Manual Name) for CAN_MO199_STAT.
+* To use register names with standard convension, please use CAN_MO199_STAT.
+*/
+#define CAN_MOSTAT199 (CAN_MO199_STAT)
+
+/** \brief 126C, Message Object Acceptance Mask Register */
+#define CAN_MO19_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001926Cu)
+
+/** Alias (User Manual Name) for CAN_MO19_AMR.
+* To use register names with standard convension, please use CAN_MO19_AMR.
+*/
+#define CAN_MOAMR19 (CAN_MO19_AMR)
+
+/** \brief 1278, Message Object Arbitration Register */
+#define CAN_MO19_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019278u)
+
+/** Alias (User Manual Name) for CAN_MO19_AR.
+* To use register names with standard convension, please use CAN_MO19_AR.
+*/
+#define CAN_MOAR19 (CAN_MO19_AR)
+
+/** \brief 127C, Message Object Control Register */
+#define CAN_MO19_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001927Cu)
+
+/** Alias (User Manual Name) for CAN_MO19_CTR.
+* To use register names with standard convension, please use CAN_MO19_CTR.
+*/
+#define CAN_MOCTR19 (CAN_MO19_CTR)
+
+/** \brief 1274, Message Object Data Register High */
+#define CAN_MO19_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019274u)
+
+/** Alias (User Manual Name) for CAN_MO19_DATAH.
+* To use register names with standard convension, please use CAN_MO19_DATAH.
+*/
+#define CAN_MODATAH19 (CAN_MO19_DATAH)
+
+/** \brief 1270, Message Object Data Register Low */
+#define CAN_MO19_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019270u)
+
+/** Alias (User Manual Name) for CAN_MO19_DATAL.
+* To use register names with standard convension, please use CAN_MO19_DATAL.
+*/
+#define CAN_MODATAL19 (CAN_MO19_DATAL)
+
+/** \brief 1260, Message Object Function Control Register */
+#define CAN_MO19_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019260u)
+
+/** Alias (User Manual Name) for CAN_MO19_EDATA0.
+* To use register names with standard convension, please use CAN_MO19_EDATA0.
+*/
+#define CAN_EMO19DATA0 (CAN_MO19_EDATA0)
+
+/** \brief 1264, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO19_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019264u)
+
+/** Alias (User Manual Name) for CAN_MO19_EDATA1.
+* To use register names with standard convension, please use CAN_MO19_EDATA1.
+*/
+#define CAN_EMO19DATA1 (CAN_MO19_EDATA1)
+
+/** \brief 1268, Message Object Interrupt Pointer Register */
+#define CAN_MO19_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019268u)
+
+/** Alias (User Manual Name) for CAN_MO19_EDATA2.
+* To use register names with standard convension, please use CAN_MO19_EDATA2.
+*/
+#define CAN_EMO19DATA2 (CAN_MO19_EDATA2)
+
+/** \brief 126C, Message Object Acceptance Mask Register */
+#define CAN_MO19_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001926Cu)
+
+/** Alias (User Manual Name) for CAN_MO19_EDATA3.
+* To use register names with standard convension, please use CAN_MO19_EDATA3.
+*/
+#define CAN_EMO19DATA3 (CAN_MO19_EDATA3)
+
+/** \brief 1270, Message Object Data Register Low */
+#define CAN_MO19_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019270u)
+
+/** Alias (User Manual Name) for CAN_MO19_EDATA4.
+* To use register names with standard convension, please use CAN_MO19_EDATA4.
+*/
+#define CAN_EMO19DATA4 (CAN_MO19_EDATA4)
+
+/** \brief 1274, Message Object Data Register High */
+#define CAN_MO19_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019274u)
+
+/** Alias (User Manual Name) for CAN_MO19_EDATA5.
+* To use register names with standard convension, please use CAN_MO19_EDATA5.
+*/
+#define CAN_EMO19DATA5 (CAN_MO19_EDATA5)
+
+/** \brief 1278, Message Object Arbitration Register */
+#define CAN_MO19_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019278u)
+
+/** Alias (User Manual Name) for CAN_MO19_EDATA6.
+* To use register names with standard convension, please use CAN_MO19_EDATA6.
+*/
+#define CAN_EMO19DATA6 (CAN_MO19_EDATA6)
+
+/** \brief 1260, Message Object Function Control Register */
+#define CAN_MO19_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019260u)
+
+/** Alias (User Manual Name) for CAN_MO19_FCR.
+* To use register names with standard convension, please use CAN_MO19_FCR.
+*/
+#define CAN_MOFCR19 (CAN_MO19_FCR)
+
+/** \brief 1264, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO19_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019264u)
+
+/** Alias (User Manual Name) for CAN_MO19_FGPR.
+* To use register names with standard convension, please use CAN_MO19_FGPR.
+*/
+#define CAN_MOFGPR19 (CAN_MO19_FGPR)
+
+/** \brief 1268, Message Object Interrupt Pointer Register */
+#define CAN_MO19_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019268u)
+
+/** Alias (User Manual Name) for CAN_MO19_IPR.
+* To use register names with standard convension, please use CAN_MO19_IPR.
+*/
+#define CAN_MOIPR19 (CAN_MO19_IPR)
+
+/** \brief 127C, Message Object Control Register */
+#define CAN_MO19_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001927Cu)
+
+/** Alias (User Manual Name) for CAN_MO19_STAT.
+* To use register names with standard convension, please use CAN_MO19_STAT.
+*/
+#define CAN_MOSTAT19 (CAN_MO19_STAT)
+
+/** \brief 102C, Message Object Acceptance Mask Register */
+#define CAN_MO1_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001902Cu)
+
+/** Alias (User Manual Name) for CAN_MO1_AMR.
+* To use register names with standard convension, please use CAN_MO1_AMR.
+*/
+#define CAN_MOAMR1 (CAN_MO1_AMR)
+
+/** \brief 1038, Message Object Arbitration Register */
+#define CAN_MO1_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019038u)
+
+/** Alias (User Manual Name) for CAN_MO1_AR.
+* To use register names with standard convension, please use CAN_MO1_AR.
+*/
+#define CAN_MOAR1 (CAN_MO1_AR)
+
+/** \brief 103C, Message Object Control Register */
+#define CAN_MO1_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001903Cu)
+
+/** Alias (User Manual Name) for CAN_MO1_CTR.
+* To use register names with standard convension, please use CAN_MO1_CTR.
+*/
+#define CAN_MOCTR1 (CAN_MO1_CTR)
+
+/** \brief 1034, Message Object Data Register High */
+#define CAN_MO1_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019034u)
+
+/** Alias (User Manual Name) for CAN_MO1_DATAH.
+* To use register names with standard convension, please use CAN_MO1_DATAH.
+*/
+#define CAN_MODATAH1 (CAN_MO1_DATAH)
+
+/** \brief 1030, Message Object Data Register Low */
+#define CAN_MO1_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019030u)
+
+/** Alias (User Manual Name) for CAN_MO1_DATAL.
+* To use register names with standard convension, please use CAN_MO1_DATAL.
+*/
+#define CAN_MODATAL1 (CAN_MO1_DATAL)
+
+/** \brief 1020, Message Object Function Control Register */
+#define CAN_MO1_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019020u)
+
+/** Alias (User Manual Name) for CAN_MO1_EDATA0.
+* To use register names with standard convension, please use CAN_MO1_EDATA0.
+*/
+#define CAN_EMO1DATA0 (CAN_MO1_EDATA0)
+
+/** \brief 1024, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO1_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019024u)
+
+/** Alias (User Manual Name) for CAN_MO1_EDATA1.
+* To use register names with standard convension, please use CAN_MO1_EDATA1.
+*/
+#define CAN_EMO1DATA1 (CAN_MO1_EDATA1)
+
+/** \brief 1028, Message Object Interrupt Pointer Register */
+#define CAN_MO1_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019028u)
+
+/** Alias (User Manual Name) for CAN_MO1_EDATA2.
+* To use register names with standard convension, please use CAN_MO1_EDATA2.
+*/
+#define CAN_EMO1DATA2 (CAN_MO1_EDATA2)
+
+/** \brief 102C, Message Object Acceptance Mask Register */
+#define CAN_MO1_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001902Cu)
+
+/** Alias (User Manual Name) for CAN_MO1_EDATA3.
+* To use register names with standard convension, please use CAN_MO1_EDATA3.
+*/
+#define CAN_EMO1DATA3 (CAN_MO1_EDATA3)
+
+/** \brief 1030, Message Object Data Register Low */
+#define CAN_MO1_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019030u)
+
+/** Alias (User Manual Name) for CAN_MO1_EDATA4.
+* To use register names with standard convension, please use CAN_MO1_EDATA4.
+*/
+#define CAN_EMO1DATA4 (CAN_MO1_EDATA4)
+
+/** \brief 1034, Message Object Data Register High */
+#define CAN_MO1_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019034u)
+
+/** Alias (User Manual Name) for CAN_MO1_EDATA5.
+* To use register names with standard convension, please use CAN_MO1_EDATA5.
+*/
+#define CAN_EMO1DATA5 (CAN_MO1_EDATA5)
+
+/** \brief 1038, Message Object Arbitration Register */
+#define CAN_MO1_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019038u)
+
+/** Alias (User Manual Name) for CAN_MO1_EDATA6.
+* To use register names with standard convension, please use CAN_MO1_EDATA6.
+*/
+#define CAN_EMO1DATA6 (CAN_MO1_EDATA6)
+
+/** \brief 1020, Message Object Function Control Register */
+#define CAN_MO1_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019020u)
+
+/** Alias (User Manual Name) for CAN_MO1_FCR.
+* To use register names with standard convension, please use CAN_MO1_FCR.
+*/
+#define CAN_MOFCR1 (CAN_MO1_FCR)
+
+/** \brief 1024, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO1_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019024u)
+
+/** Alias (User Manual Name) for CAN_MO1_FGPR.
+* To use register names with standard convension, please use CAN_MO1_FGPR.
+*/
+#define CAN_MOFGPR1 (CAN_MO1_FGPR)
+
+/** \brief 1028, Message Object Interrupt Pointer Register */
+#define CAN_MO1_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019028u)
+
+/** Alias (User Manual Name) for CAN_MO1_IPR.
+* To use register names with standard convension, please use CAN_MO1_IPR.
+*/
+#define CAN_MOIPR1 (CAN_MO1_IPR)
+
+/** \brief 103C, Message Object Control Register */
+#define CAN_MO1_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001903Cu)
+
+/** Alias (User Manual Name) for CAN_MO1_STAT.
+* To use register names with standard convension, please use CAN_MO1_STAT.
+*/
+#define CAN_MOSTAT1 (CAN_MO1_STAT)
+
+/** \brief 290C, Message Object Acceptance Mask Register */
+#define CAN_MO200_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A90Cu)
+
+/** Alias (User Manual Name) for CAN_MO200_AMR.
+* To use register names with standard convension, please use CAN_MO200_AMR.
+*/
+#define CAN_MOAMR200 (CAN_MO200_AMR)
+
+/** \brief 2918, Message Object Arbitration Register */
+#define CAN_MO200_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A918u)
+
+/** Alias (User Manual Name) for CAN_MO200_AR.
+* To use register names with standard convension, please use CAN_MO200_AR.
+*/
+#define CAN_MOAR200 (CAN_MO200_AR)
+
+/** \brief 291C, Message Object Control Register */
+#define CAN_MO200_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A91Cu)
+
+/** Alias (User Manual Name) for CAN_MO200_CTR.
+* To use register names with standard convension, please use CAN_MO200_CTR.
+*/
+#define CAN_MOCTR200 (CAN_MO200_CTR)
+
+/** \brief 2914, Message Object Data Register High */
+#define CAN_MO200_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A914u)
+
+/** Alias (User Manual Name) for CAN_MO200_DATAH.
+* To use register names with standard convension, please use CAN_MO200_DATAH.
+*/
+#define CAN_MODATAH200 (CAN_MO200_DATAH)
+
+/** \brief 2910, Message Object Data Register Low */
+#define CAN_MO200_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A910u)
+
+/** Alias (User Manual Name) for CAN_MO200_DATAL.
+* To use register names with standard convension, please use CAN_MO200_DATAL.
+*/
+#define CAN_MODATAL200 (CAN_MO200_DATAL)
+
+/** \brief 2900, Message Object Function Control Register */
+#define CAN_MO200_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A900u)
+
+/** Alias (User Manual Name) for CAN_MO200_EDATA0.
+* To use register names with standard convension, please use CAN_MO200_EDATA0.
+*/
+#define CAN_EMO200DATA0 (CAN_MO200_EDATA0)
+
+/** \brief 2904, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO200_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A904u)
+
+/** Alias (User Manual Name) for CAN_MO200_EDATA1.
+* To use register names with standard convension, please use CAN_MO200_EDATA1.
+*/
+#define CAN_EMO200DATA1 (CAN_MO200_EDATA1)
+
+/** \brief 2908, Message Object Interrupt Pointer Register */
+#define CAN_MO200_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A908u)
+
+/** Alias (User Manual Name) for CAN_MO200_EDATA2.
+* To use register names with standard convension, please use CAN_MO200_EDATA2.
+*/
+#define CAN_EMO200DATA2 (CAN_MO200_EDATA2)
+
+/** \brief 290C, Message Object Acceptance Mask Register */
+#define CAN_MO200_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A90Cu)
+
+/** Alias (User Manual Name) for CAN_MO200_EDATA3.
+* To use register names with standard convension, please use CAN_MO200_EDATA3.
+*/
+#define CAN_EMO200DATA3 (CAN_MO200_EDATA3)
+
+/** \brief 2910, Message Object Data Register Low */
+#define CAN_MO200_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A910u)
+
+/** Alias (User Manual Name) for CAN_MO200_EDATA4.
+* To use register names with standard convension, please use CAN_MO200_EDATA4.
+*/
+#define CAN_EMO200DATA4 (CAN_MO200_EDATA4)
+
+/** \brief 2914, Message Object Data Register High */
+#define CAN_MO200_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A914u)
+
+/** Alias (User Manual Name) for CAN_MO200_EDATA5.
+* To use register names with standard convension, please use CAN_MO200_EDATA5.
+*/
+#define CAN_EMO200DATA5 (CAN_MO200_EDATA5)
+
+/** \brief 2918, Message Object Arbitration Register */
+#define CAN_MO200_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A918u)
+
+/** Alias (User Manual Name) for CAN_MO200_EDATA6.
+* To use register names with standard convension, please use CAN_MO200_EDATA6.
+*/
+#define CAN_EMO200DATA6 (CAN_MO200_EDATA6)
+
+/** \brief 2900, Message Object Function Control Register */
+#define CAN_MO200_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A900u)
+
+/** Alias (User Manual Name) for CAN_MO200_FCR.
+* To use register names with standard convension, please use CAN_MO200_FCR.
+*/
+#define CAN_MOFCR200 (CAN_MO200_FCR)
+
+/** \brief 2904, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO200_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A904u)
+
+/** Alias (User Manual Name) for CAN_MO200_FGPR.
+* To use register names with standard convension, please use CAN_MO200_FGPR.
+*/
+#define CAN_MOFGPR200 (CAN_MO200_FGPR)
+
+/** \brief 2908, Message Object Interrupt Pointer Register */
+#define CAN_MO200_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A908u)
+
+/** Alias (User Manual Name) for CAN_MO200_IPR.
+* To use register names with standard convension, please use CAN_MO200_IPR.
+*/
+#define CAN_MOIPR200 (CAN_MO200_IPR)
+
+/** \brief 291C, Message Object Control Register */
+#define CAN_MO200_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A91Cu)
+
+/** Alias (User Manual Name) for CAN_MO200_STAT.
+* To use register names with standard convension, please use CAN_MO200_STAT.
+*/
+#define CAN_MOSTAT200 (CAN_MO200_STAT)
+
+/** \brief 292C, Message Object Acceptance Mask Register */
+#define CAN_MO201_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A92Cu)
+
+/** Alias (User Manual Name) for CAN_MO201_AMR.
+* To use register names with standard convension, please use CAN_MO201_AMR.
+*/
+#define CAN_MOAMR201 (CAN_MO201_AMR)
+
+/** \brief 2938, Message Object Arbitration Register */
+#define CAN_MO201_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A938u)
+
+/** Alias (User Manual Name) for CAN_MO201_AR.
+* To use register names with standard convension, please use CAN_MO201_AR.
+*/
+#define CAN_MOAR201 (CAN_MO201_AR)
+
+/** \brief 293C, Message Object Control Register */
+#define CAN_MO201_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A93Cu)
+
+/** Alias (User Manual Name) for CAN_MO201_CTR.
+* To use register names with standard convension, please use CAN_MO201_CTR.
+*/
+#define CAN_MOCTR201 (CAN_MO201_CTR)
+
+/** \brief 2934, Message Object Data Register High */
+#define CAN_MO201_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A934u)
+
+/** Alias (User Manual Name) for CAN_MO201_DATAH.
+* To use register names with standard convension, please use CAN_MO201_DATAH.
+*/
+#define CAN_MODATAH201 (CAN_MO201_DATAH)
+
+/** \brief 2930, Message Object Data Register Low */
+#define CAN_MO201_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A930u)
+
+/** Alias (User Manual Name) for CAN_MO201_DATAL.
+* To use register names with standard convension, please use CAN_MO201_DATAL.
+*/
+#define CAN_MODATAL201 (CAN_MO201_DATAL)
+
+/** \brief 2920, Message Object Function Control Register */
+#define CAN_MO201_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A920u)
+
+/** Alias (User Manual Name) for CAN_MO201_EDATA0.
+* To use register names with standard convension, please use CAN_MO201_EDATA0.
+*/
+#define CAN_EMO201DATA0 (CAN_MO201_EDATA0)
+
+/** \brief 2924, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO201_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A924u)
+
+/** Alias (User Manual Name) for CAN_MO201_EDATA1.
+* To use register names with standard convension, please use CAN_MO201_EDATA1.
+*/
+#define CAN_EMO201DATA1 (CAN_MO201_EDATA1)
+
+/** \brief 2928, Message Object Interrupt Pointer Register */
+#define CAN_MO201_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A928u)
+
+/** Alias (User Manual Name) for CAN_MO201_EDATA2.
+* To use register names with standard convension, please use CAN_MO201_EDATA2.
+*/
+#define CAN_EMO201DATA2 (CAN_MO201_EDATA2)
+
+/** \brief 292C, Message Object Acceptance Mask Register */
+#define CAN_MO201_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A92Cu)
+
+/** Alias (User Manual Name) for CAN_MO201_EDATA3.
+* To use register names with standard convension, please use CAN_MO201_EDATA3.
+*/
+#define CAN_EMO201DATA3 (CAN_MO201_EDATA3)
+
+/** \brief 2930, Message Object Data Register Low */
+#define CAN_MO201_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A930u)
+
+/** Alias (User Manual Name) for CAN_MO201_EDATA4.
+* To use register names with standard convension, please use CAN_MO201_EDATA4.
+*/
+#define CAN_EMO201DATA4 (CAN_MO201_EDATA4)
+
+/** \brief 2934, Message Object Data Register High */
+#define CAN_MO201_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A934u)
+
+/** Alias (User Manual Name) for CAN_MO201_EDATA5.
+* To use register names with standard convension, please use CAN_MO201_EDATA5.
+*/
+#define CAN_EMO201DATA5 (CAN_MO201_EDATA5)
+
+/** \brief 2938, Message Object Arbitration Register */
+#define CAN_MO201_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A938u)
+
+/** Alias (User Manual Name) for CAN_MO201_EDATA6.
+* To use register names with standard convension, please use CAN_MO201_EDATA6.
+*/
+#define CAN_EMO201DATA6 (CAN_MO201_EDATA6)
+
+/** \brief 2920, Message Object Function Control Register */
+#define CAN_MO201_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A920u)
+
+/** Alias (User Manual Name) for CAN_MO201_FCR.
+* To use register names with standard convension, please use CAN_MO201_FCR.
+*/
+#define CAN_MOFCR201 (CAN_MO201_FCR)
+
+/** \brief 2924, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO201_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A924u)
+
+/** Alias (User Manual Name) for CAN_MO201_FGPR.
+* To use register names with standard convension, please use CAN_MO201_FGPR.
+*/
+#define CAN_MOFGPR201 (CAN_MO201_FGPR)
+
+/** \brief 2928, Message Object Interrupt Pointer Register */
+#define CAN_MO201_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A928u)
+
+/** Alias (User Manual Name) for CAN_MO201_IPR.
+* To use register names with standard convension, please use CAN_MO201_IPR.
+*/
+#define CAN_MOIPR201 (CAN_MO201_IPR)
+
+/** \brief 293C, Message Object Control Register */
+#define CAN_MO201_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A93Cu)
+
+/** Alias (User Manual Name) for CAN_MO201_STAT.
+* To use register names with standard convension, please use CAN_MO201_STAT.
+*/
+#define CAN_MOSTAT201 (CAN_MO201_STAT)
+
+/** \brief 294C, Message Object Acceptance Mask Register */
+#define CAN_MO202_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A94Cu)
+
+/** Alias (User Manual Name) for CAN_MO202_AMR.
+* To use register names with standard convension, please use CAN_MO202_AMR.
+*/
+#define CAN_MOAMR202 (CAN_MO202_AMR)
+
+/** \brief 2958, Message Object Arbitration Register */
+#define CAN_MO202_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A958u)
+
+/** Alias (User Manual Name) for CAN_MO202_AR.
+* To use register names with standard convension, please use CAN_MO202_AR.
+*/
+#define CAN_MOAR202 (CAN_MO202_AR)
+
+/** \brief 295C, Message Object Control Register */
+#define CAN_MO202_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A95Cu)
+
+/** Alias (User Manual Name) for CAN_MO202_CTR.
+* To use register names with standard convension, please use CAN_MO202_CTR.
+*/
+#define CAN_MOCTR202 (CAN_MO202_CTR)
+
+/** \brief 2954, Message Object Data Register High */
+#define CAN_MO202_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A954u)
+
+/** Alias (User Manual Name) for CAN_MO202_DATAH.
+* To use register names with standard convension, please use CAN_MO202_DATAH.
+*/
+#define CAN_MODATAH202 (CAN_MO202_DATAH)
+
+/** \brief 2950, Message Object Data Register Low */
+#define CAN_MO202_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A950u)
+
+/** Alias (User Manual Name) for CAN_MO202_DATAL.
+* To use register names with standard convension, please use CAN_MO202_DATAL.
+*/
+#define CAN_MODATAL202 (CAN_MO202_DATAL)
+
+/** \brief 2940, Message Object Function Control Register */
+#define CAN_MO202_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A940u)
+
+/** Alias (User Manual Name) for CAN_MO202_EDATA0.
+* To use register names with standard convension, please use CAN_MO202_EDATA0.
+*/
+#define CAN_EMO202DATA0 (CAN_MO202_EDATA0)
+
+/** \brief 2944, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO202_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A944u)
+
+/** Alias (User Manual Name) for CAN_MO202_EDATA1.
+* To use register names with standard convension, please use CAN_MO202_EDATA1.
+*/
+#define CAN_EMO202DATA1 (CAN_MO202_EDATA1)
+
+/** \brief 2948, Message Object Interrupt Pointer Register */
+#define CAN_MO202_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A948u)
+
+/** Alias (User Manual Name) for CAN_MO202_EDATA2.
+* To use register names with standard convension, please use CAN_MO202_EDATA2.
+*/
+#define CAN_EMO202DATA2 (CAN_MO202_EDATA2)
+
+/** \brief 294C, Message Object Acceptance Mask Register */
+#define CAN_MO202_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A94Cu)
+
+/** Alias (User Manual Name) for CAN_MO202_EDATA3.
+* To use register names with standard convension, please use CAN_MO202_EDATA3.
+*/
+#define CAN_EMO202DATA3 (CAN_MO202_EDATA3)
+
+/** \brief 2950, Message Object Data Register Low */
+#define CAN_MO202_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A950u)
+
+/** Alias (User Manual Name) for CAN_MO202_EDATA4.
+* To use register names with standard convension, please use CAN_MO202_EDATA4.
+*/
+#define CAN_EMO202DATA4 (CAN_MO202_EDATA4)
+
+/** \brief 2954, Message Object Data Register High */
+#define CAN_MO202_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A954u)
+
+/** Alias (User Manual Name) for CAN_MO202_EDATA5.
+* To use register names with standard convension, please use CAN_MO202_EDATA5.
+*/
+#define CAN_EMO202DATA5 (CAN_MO202_EDATA5)
+
+/** \brief 2958, Message Object Arbitration Register */
+#define CAN_MO202_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A958u)
+
+/** Alias (User Manual Name) for CAN_MO202_EDATA6.
+* To use register names with standard convension, please use CAN_MO202_EDATA6.
+*/
+#define CAN_EMO202DATA6 (CAN_MO202_EDATA6)
+
+/** \brief 2940, Message Object Function Control Register */
+#define CAN_MO202_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A940u)
+
+/** Alias (User Manual Name) for CAN_MO202_FCR.
+* To use register names with standard convension, please use CAN_MO202_FCR.
+*/
+#define CAN_MOFCR202 (CAN_MO202_FCR)
+
+/** \brief 2944, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO202_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A944u)
+
+/** Alias (User Manual Name) for CAN_MO202_FGPR.
+* To use register names with standard convension, please use CAN_MO202_FGPR.
+*/
+#define CAN_MOFGPR202 (CAN_MO202_FGPR)
+
+/** \brief 2948, Message Object Interrupt Pointer Register */
+#define CAN_MO202_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A948u)
+
+/** Alias (User Manual Name) for CAN_MO202_IPR.
+* To use register names with standard convension, please use CAN_MO202_IPR.
+*/
+#define CAN_MOIPR202 (CAN_MO202_IPR)
+
+/** \brief 295C, Message Object Control Register */
+#define CAN_MO202_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A95Cu)
+
+/** Alias (User Manual Name) for CAN_MO202_STAT.
+* To use register names with standard convension, please use CAN_MO202_STAT.
+*/
+#define CAN_MOSTAT202 (CAN_MO202_STAT)
+
+/** \brief 296C, Message Object Acceptance Mask Register */
+#define CAN_MO203_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A96Cu)
+
+/** Alias (User Manual Name) for CAN_MO203_AMR.
+* To use register names with standard convension, please use CAN_MO203_AMR.
+*/
+#define CAN_MOAMR203 (CAN_MO203_AMR)
+
+/** \brief 2978, Message Object Arbitration Register */
+#define CAN_MO203_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A978u)
+
+/** Alias (User Manual Name) for CAN_MO203_AR.
+* To use register names with standard convension, please use CAN_MO203_AR.
+*/
+#define CAN_MOAR203 (CAN_MO203_AR)
+
+/** \brief 297C, Message Object Control Register */
+#define CAN_MO203_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A97Cu)
+
+/** Alias (User Manual Name) for CAN_MO203_CTR.
+* To use register names with standard convension, please use CAN_MO203_CTR.
+*/
+#define CAN_MOCTR203 (CAN_MO203_CTR)
+
+/** \brief 2974, Message Object Data Register High */
+#define CAN_MO203_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A974u)
+
+/** Alias (User Manual Name) for CAN_MO203_DATAH.
+* To use register names with standard convension, please use CAN_MO203_DATAH.
+*/
+#define CAN_MODATAH203 (CAN_MO203_DATAH)
+
+/** \brief 2970, Message Object Data Register Low */
+#define CAN_MO203_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A970u)
+
+/** Alias (User Manual Name) for CAN_MO203_DATAL.
+* To use register names with standard convension, please use CAN_MO203_DATAL.
+*/
+#define CAN_MODATAL203 (CAN_MO203_DATAL)
+
+/** \brief 2960, Message Object Function Control Register */
+#define CAN_MO203_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A960u)
+
+/** Alias (User Manual Name) for CAN_MO203_EDATA0.
+* To use register names with standard convension, please use CAN_MO203_EDATA0.
+*/
+#define CAN_EMO203DATA0 (CAN_MO203_EDATA0)
+
+/** \brief 2964, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO203_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A964u)
+
+/** Alias (User Manual Name) for CAN_MO203_EDATA1.
+* To use register names with standard convension, please use CAN_MO203_EDATA1.
+*/
+#define CAN_EMO203DATA1 (CAN_MO203_EDATA1)
+
+/** \brief 2968, Message Object Interrupt Pointer Register */
+#define CAN_MO203_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A968u)
+
+/** Alias (User Manual Name) for CAN_MO203_EDATA2.
+* To use register names with standard convension, please use CAN_MO203_EDATA2.
+*/
+#define CAN_EMO203DATA2 (CAN_MO203_EDATA2)
+
+/** \brief 296C, Message Object Acceptance Mask Register */
+#define CAN_MO203_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A96Cu)
+
+/** Alias (User Manual Name) for CAN_MO203_EDATA3.
+* To use register names with standard convension, please use CAN_MO203_EDATA3.
+*/
+#define CAN_EMO203DATA3 (CAN_MO203_EDATA3)
+
+/** \brief 2970, Message Object Data Register Low */
+#define CAN_MO203_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A970u)
+
+/** Alias (User Manual Name) for CAN_MO203_EDATA4.
+* To use register names with standard convension, please use CAN_MO203_EDATA4.
+*/
+#define CAN_EMO203DATA4 (CAN_MO203_EDATA4)
+
+/** \brief 2974, Message Object Data Register High */
+#define CAN_MO203_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A974u)
+
+/** Alias (User Manual Name) for CAN_MO203_EDATA5.
+* To use register names with standard convension, please use CAN_MO203_EDATA5.
+*/
+#define CAN_EMO203DATA5 (CAN_MO203_EDATA5)
+
+/** \brief 2978, Message Object Arbitration Register */
+#define CAN_MO203_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A978u)
+
+/** Alias (User Manual Name) for CAN_MO203_EDATA6.
+* To use register names with standard convension, please use CAN_MO203_EDATA6.
+*/
+#define CAN_EMO203DATA6 (CAN_MO203_EDATA6)
+
+/** \brief 2960, Message Object Function Control Register */
+#define CAN_MO203_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A960u)
+
+/** Alias (User Manual Name) for CAN_MO203_FCR.
+* To use register names with standard convension, please use CAN_MO203_FCR.
+*/
+#define CAN_MOFCR203 (CAN_MO203_FCR)
+
+/** \brief 2964, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO203_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A964u)
+
+/** Alias (User Manual Name) for CAN_MO203_FGPR.
+* To use register names with standard convension, please use CAN_MO203_FGPR.
+*/
+#define CAN_MOFGPR203 (CAN_MO203_FGPR)
+
+/** \brief 2968, Message Object Interrupt Pointer Register */
+#define CAN_MO203_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A968u)
+
+/** Alias (User Manual Name) for CAN_MO203_IPR.
+* To use register names with standard convension, please use CAN_MO203_IPR.
+*/
+#define CAN_MOIPR203 (CAN_MO203_IPR)
+
+/** \brief 297C, Message Object Control Register */
+#define CAN_MO203_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A97Cu)
+
+/** Alias (User Manual Name) for CAN_MO203_STAT.
+* To use register names with standard convension, please use CAN_MO203_STAT.
+*/
+#define CAN_MOSTAT203 (CAN_MO203_STAT)
+
+/** \brief 298C, Message Object Acceptance Mask Register */
+#define CAN_MO204_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A98Cu)
+
+/** Alias (User Manual Name) for CAN_MO204_AMR.
+* To use register names with standard convension, please use CAN_MO204_AMR.
+*/
+#define CAN_MOAMR204 (CAN_MO204_AMR)
+
+/** \brief 2998, Message Object Arbitration Register */
+#define CAN_MO204_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A998u)
+
+/** Alias (User Manual Name) for CAN_MO204_AR.
+* To use register names with standard convension, please use CAN_MO204_AR.
+*/
+#define CAN_MOAR204 (CAN_MO204_AR)
+
+/** \brief 299C, Message Object Control Register */
+#define CAN_MO204_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A99Cu)
+
+/** Alias (User Manual Name) for CAN_MO204_CTR.
+* To use register names with standard convension, please use CAN_MO204_CTR.
+*/
+#define CAN_MOCTR204 (CAN_MO204_CTR)
+
+/** \brief 2994, Message Object Data Register High */
+#define CAN_MO204_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A994u)
+
+/** Alias (User Manual Name) for CAN_MO204_DATAH.
+* To use register names with standard convension, please use CAN_MO204_DATAH.
+*/
+#define CAN_MODATAH204 (CAN_MO204_DATAH)
+
+/** \brief 2990, Message Object Data Register Low */
+#define CAN_MO204_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A990u)
+
+/** Alias (User Manual Name) for CAN_MO204_DATAL.
+* To use register names with standard convension, please use CAN_MO204_DATAL.
+*/
+#define CAN_MODATAL204 (CAN_MO204_DATAL)
+
+/** \brief 2980, Message Object Function Control Register */
+#define CAN_MO204_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A980u)
+
+/** Alias (User Manual Name) for CAN_MO204_EDATA0.
+* To use register names with standard convension, please use CAN_MO204_EDATA0.
+*/
+#define CAN_EMO204DATA0 (CAN_MO204_EDATA0)
+
+/** \brief 2984, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO204_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A984u)
+
+/** Alias (User Manual Name) for CAN_MO204_EDATA1.
+* To use register names with standard convension, please use CAN_MO204_EDATA1.
+*/
+#define CAN_EMO204DATA1 (CAN_MO204_EDATA1)
+
+/** \brief 2988, Message Object Interrupt Pointer Register */
+#define CAN_MO204_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A988u)
+
+/** Alias (User Manual Name) for CAN_MO204_EDATA2.
+* To use register names with standard convension, please use CAN_MO204_EDATA2.
+*/
+#define CAN_EMO204DATA2 (CAN_MO204_EDATA2)
+
+/** \brief 298C, Message Object Acceptance Mask Register */
+#define CAN_MO204_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A98Cu)
+
+/** Alias (User Manual Name) for CAN_MO204_EDATA3.
+* To use register names with standard convension, please use CAN_MO204_EDATA3.
+*/
+#define CAN_EMO204DATA3 (CAN_MO204_EDATA3)
+
+/** \brief 2990, Message Object Data Register Low */
+#define CAN_MO204_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A990u)
+
+/** Alias (User Manual Name) for CAN_MO204_EDATA4.
+* To use register names with standard convension, please use CAN_MO204_EDATA4.
+*/
+#define CAN_EMO204DATA4 (CAN_MO204_EDATA4)
+
+/** \brief 2994, Message Object Data Register High */
+#define CAN_MO204_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A994u)
+
+/** Alias (User Manual Name) for CAN_MO204_EDATA5.
+* To use register names with standard convension, please use CAN_MO204_EDATA5.
+*/
+#define CAN_EMO204DATA5 (CAN_MO204_EDATA5)
+
+/** \brief 2998, Message Object Arbitration Register */
+#define CAN_MO204_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A998u)
+
+/** Alias (User Manual Name) for CAN_MO204_EDATA6.
+* To use register names with standard convension, please use CAN_MO204_EDATA6.
+*/
+#define CAN_EMO204DATA6 (CAN_MO204_EDATA6)
+
+/** \brief 2980, Message Object Function Control Register */
+#define CAN_MO204_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A980u)
+
+/** Alias (User Manual Name) for CAN_MO204_FCR.
+* To use register names with standard convension, please use CAN_MO204_FCR.
+*/
+#define CAN_MOFCR204 (CAN_MO204_FCR)
+
+/** \brief 2984, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO204_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A984u)
+
+/** Alias (User Manual Name) for CAN_MO204_FGPR.
+* To use register names with standard convension, please use CAN_MO204_FGPR.
+*/
+#define CAN_MOFGPR204 (CAN_MO204_FGPR)
+
+/** \brief 2988, Message Object Interrupt Pointer Register */
+#define CAN_MO204_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A988u)
+
+/** Alias (User Manual Name) for CAN_MO204_IPR.
+* To use register names with standard convension, please use CAN_MO204_IPR.
+*/
+#define CAN_MOIPR204 (CAN_MO204_IPR)
+
+/** \brief 299C, Message Object Control Register */
+#define CAN_MO204_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A99Cu)
+
+/** Alias (User Manual Name) for CAN_MO204_STAT.
+* To use register names with standard convension, please use CAN_MO204_STAT.
+*/
+#define CAN_MOSTAT204 (CAN_MO204_STAT)
+
+/** \brief 29AC, Message Object Acceptance Mask Register */
+#define CAN_MO205_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A9ACu)
+
+/** Alias (User Manual Name) for CAN_MO205_AMR.
+* To use register names with standard convension, please use CAN_MO205_AMR.
+*/
+#define CAN_MOAMR205 (CAN_MO205_AMR)
+
+/** \brief 29B8, Message Object Arbitration Register */
+#define CAN_MO205_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A9B8u)
+
+/** Alias (User Manual Name) for CAN_MO205_AR.
+* To use register names with standard convension, please use CAN_MO205_AR.
+*/
+#define CAN_MOAR205 (CAN_MO205_AR)
+
+/** \brief 29BC, Message Object Control Register */
+#define CAN_MO205_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A9BCu)
+
+/** Alias (User Manual Name) for CAN_MO205_CTR.
+* To use register names with standard convension, please use CAN_MO205_CTR.
+*/
+#define CAN_MOCTR205 (CAN_MO205_CTR)
+
+/** \brief 29B4, Message Object Data Register High */
+#define CAN_MO205_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A9B4u)
+
+/** Alias (User Manual Name) for CAN_MO205_DATAH.
+* To use register names with standard convension, please use CAN_MO205_DATAH.
+*/
+#define CAN_MODATAH205 (CAN_MO205_DATAH)
+
+/** \brief 29B0, Message Object Data Register Low */
+#define CAN_MO205_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A9B0u)
+
+/** Alias (User Manual Name) for CAN_MO205_DATAL.
+* To use register names with standard convension, please use CAN_MO205_DATAL.
+*/
+#define CAN_MODATAL205 (CAN_MO205_DATAL)
+
+/** \brief 29A0, Message Object Function Control Register */
+#define CAN_MO205_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A9A0u)
+
+/** Alias (User Manual Name) for CAN_MO205_EDATA0.
+* To use register names with standard convension, please use CAN_MO205_EDATA0.
+*/
+#define CAN_EMO205DATA0 (CAN_MO205_EDATA0)
+
+/** \brief 29A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO205_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A9A4u)
+
+/** Alias (User Manual Name) for CAN_MO205_EDATA1.
+* To use register names with standard convension, please use CAN_MO205_EDATA1.
+*/
+#define CAN_EMO205DATA1 (CAN_MO205_EDATA1)
+
+/** \brief 29A8, Message Object Interrupt Pointer Register */
+#define CAN_MO205_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A9A8u)
+
+/** Alias (User Manual Name) for CAN_MO205_EDATA2.
+* To use register names with standard convension, please use CAN_MO205_EDATA2.
+*/
+#define CAN_EMO205DATA2 (CAN_MO205_EDATA2)
+
+/** \brief 29AC, Message Object Acceptance Mask Register */
+#define CAN_MO205_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A9ACu)
+
+/** Alias (User Manual Name) for CAN_MO205_EDATA3.
+* To use register names with standard convension, please use CAN_MO205_EDATA3.
+*/
+#define CAN_EMO205DATA3 (CAN_MO205_EDATA3)
+
+/** \brief 29B0, Message Object Data Register Low */
+#define CAN_MO205_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A9B0u)
+
+/** Alias (User Manual Name) for CAN_MO205_EDATA4.
+* To use register names with standard convension, please use CAN_MO205_EDATA4.
+*/
+#define CAN_EMO205DATA4 (CAN_MO205_EDATA4)
+
+/** \brief 29B4, Message Object Data Register High */
+#define CAN_MO205_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A9B4u)
+
+/** Alias (User Manual Name) for CAN_MO205_EDATA5.
+* To use register names with standard convension, please use CAN_MO205_EDATA5.
+*/
+#define CAN_EMO205DATA5 (CAN_MO205_EDATA5)
+
+/** \brief 29B8, Message Object Arbitration Register */
+#define CAN_MO205_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A9B8u)
+
+/** Alias (User Manual Name) for CAN_MO205_EDATA6.
+* To use register names with standard convension, please use CAN_MO205_EDATA6.
+*/
+#define CAN_EMO205DATA6 (CAN_MO205_EDATA6)
+
+/** \brief 29A0, Message Object Function Control Register */
+#define CAN_MO205_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A9A0u)
+
+/** Alias (User Manual Name) for CAN_MO205_FCR.
+* To use register names with standard convension, please use CAN_MO205_FCR.
+*/
+#define CAN_MOFCR205 (CAN_MO205_FCR)
+
+/** \brief 29A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO205_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A9A4u)
+
+/** Alias (User Manual Name) for CAN_MO205_FGPR.
+* To use register names with standard convension, please use CAN_MO205_FGPR.
+*/
+#define CAN_MOFGPR205 (CAN_MO205_FGPR)
+
+/** \brief 29A8, Message Object Interrupt Pointer Register */
+#define CAN_MO205_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A9A8u)
+
+/** Alias (User Manual Name) for CAN_MO205_IPR.
+* To use register names with standard convension, please use CAN_MO205_IPR.
+*/
+#define CAN_MOIPR205 (CAN_MO205_IPR)
+
+/** \brief 29BC, Message Object Control Register */
+#define CAN_MO205_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A9BCu)
+
+/** Alias (User Manual Name) for CAN_MO205_STAT.
+* To use register names with standard convension, please use CAN_MO205_STAT.
+*/
+#define CAN_MOSTAT205 (CAN_MO205_STAT)
+
+/** \brief 29CC, Message Object Acceptance Mask Register */
+#define CAN_MO206_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A9CCu)
+
+/** Alias (User Manual Name) for CAN_MO206_AMR.
+* To use register names with standard convension, please use CAN_MO206_AMR.
+*/
+#define CAN_MOAMR206 (CAN_MO206_AMR)
+
+/** \brief 29D8, Message Object Arbitration Register */
+#define CAN_MO206_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A9D8u)
+
+/** Alias (User Manual Name) for CAN_MO206_AR.
+* To use register names with standard convension, please use CAN_MO206_AR.
+*/
+#define CAN_MOAR206 (CAN_MO206_AR)
+
+/** \brief 29DC, Message Object Control Register */
+#define CAN_MO206_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A9DCu)
+
+/** Alias (User Manual Name) for CAN_MO206_CTR.
+* To use register names with standard convension, please use CAN_MO206_CTR.
+*/
+#define CAN_MOCTR206 (CAN_MO206_CTR)
+
+/** \brief 29D4, Message Object Data Register High */
+#define CAN_MO206_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A9D4u)
+
+/** Alias (User Manual Name) for CAN_MO206_DATAH.
+* To use register names with standard convension, please use CAN_MO206_DATAH.
+*/
+#define CAN_MODATAH206 (CAN_MO206_DATAH)
+
+/** \brief 29D0, Message Object Data Register Low */
+#define CAN_MO206_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A9D0u)
+
+/** Alias (User Manual Name) for CAN_MO206_DATAL.
+* To use register names with standard convension, please use CAN_MO206_DATAL.
+*/
+#define CAN_MODATAL206 (CAN_MO206_DATAL)
+
+/** \brief 29C0, Message Object Function Control Register */
+#define CAN_MO206_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A9C0u)
+
+/** Alias (User Manual Name) for CAN_MO206_EDATA0.
+* To use register names with standard convension, please use CAN_MO206_EDATA0.
+*/
+#define CAN_EMO206DATA0 (CAN_MO206_EDATA0)
+
+/** \brief 29C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO206_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A9C4u)
+
+/** Alias (User Manual Name) for CAN_MO206_EDATA1.
+* To use register names with standard convension, please use CAN_MO206_EDATA1.
+*/
+#define CAN_EMO206DATA1 (CAN_MO206_EDATA1)
+
+/** \brief 29C8, Message Object Interrupt Pointer Register */
+#define CAN_MO206_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A9C8u)
+
+/** Alias (User Manual Name) for CAN_MO206_EDATA2.
+* To use register names with standard convension, please use CAN_MO206_EDATA2.
+*/
+#define CAN_EMO206DATA2 (CAN_MO206_EDATA2)
+
+/** \brief 29CC, Message Object Acceptance Mask Register */
+#define CAN_MO206_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A9CCu)
+
+/** Alias (User Manual Name) for CAN_MO206_EDATA3.
+* To use register names with standard convension, please use CAN_MO206_EDATA3.
+*/
+#define CAN_EMO206DATA3 (CAN_MO206_EDATA3)
+
+/** \brief 29D0, Message Object Data Register Low */
+#define CAN_MO206_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A9D0u)
+
+/** Alias (User Manual Name) for CAN_MO206_EDATA4.
+* To use register names with standard convension, please use CAN_MO206_EDATA4.
+*/
+#define CAN_EMO206DATA4 (CAN_MO206_EDATA4)
+
+/** \brief 29D4, Message Object Data Register High */
+#define CAN_MO206_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A9D4u)
+
+/** Alias (User Manual Name) for CAN_MO206_EDATA5.
+* To use register names with standard convension, please use CAN_MO206_EDATA5.
+*/
+#define CAN_EMO206DATA5 (CAN_MO206_EDATA5)
+
+/** \brief 29D8, Message Object Arbitration Register */
+#define CAN_MO206_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A9D8u)
+
+/** Alias (User Manual Name) for CAN_MO206_EDATA6.
+* To use register names with standard convension, please use CAN_MO206_EDATA6.
+*/
+#define CAN_EMO206DATA6 (CAN_MO206_EDATA6)
+
+/** \brief 29C0, Message Object Function Control Register */
+#define CAN_MO206_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A9C0u)
+
+/** Alias (User Manual Name) for CAN_MO206_FCR.
+* To use register names with standard convension, please use CAN_MO206_FCR.
+*/
+#define CAN_MOFCR206 (CAN_MO206_FCR)
+
+/** \brief 29C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO206_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A9C4u)
+
+/** Alias (User Manual Name) for CAN_MO206_FGPR.
+* To use register names with standard convension, please use CAN_MO206_FGPR.
+*/
+#define CAN_MOFGPR206 (CAN_MO206_FGPR)
+
+/** \brief 29C8, Message Object Interrupt Pointer Register */
+#define CAN_MO206_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A9C8u)
+
+/** Alias (User Manual Name) for CAN_MO206_IPR.
+* To use register names with standard convension, please use CAN_MO206_IPR.
+*/
+#define CAN_MOIPR206 (CAN_MO206_IPR)
+
+/** \brief 29DC, Message Object Control Register */
+#define CAN_MO206_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A9DCu)
+
+/** Alias (User Manual Name) for CAN_MO206_STAT.
+* To use register names with standard convension, please use CAN_MO206_STAT.
+*/
+#define CAN_MOSTAT206 (CAN_MO206_STAT)
+
+/** \brief 29EC, Message Object Acceptance Mask Register */
+#define CAN_MO207_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001A9ECu)
+
+/** Alias (User Manual Name) for CAN_MO207_AMR.
+* To use register names with standard convension, please use CAN_MO207_AMR.
+*/
+#define CAN_MOAMR207 (CAN_MO207_AMR)
+
+/** \brief 29F8, Message Object Arbitration Register */
+#define CAN_MO207_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001A9F8u)
+
+/** Alias (User Manual Name) for CAN_MO207_AR.
+* To use register names with standard convension, please use CAN_MO207_AR.
+*/
+#define CAN_MOAR207 (CAN_MO207_AR)
+
+/** \brief 29FC, Message Object Control Register */
+#define CAN_MO207_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001A9FCu)
+
+/** Alias (User Manual Name) for CAN_MO207_CTR.
+* To use register names with standard convension, please use CAN_MO207_CTR.
+*/
+#define CAN_MOCTR207 (CAN_MO207_CTR)
+
+/** \brief 29F4, Message Object Data Register High */
+#define CAN_MO207_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001A9F4u)
+
+/** Alias (User Manual Name) for CAN_MO207_DATAH.
+* To use register names with standard convension, please use CAN_MO207_DATAH.
+*/
+#define CAN_MODATAH207 (CAN_MO207_DATAH)
+
+/** \brief 29F0, Message Object Data Register Low */
+#define CAN_MO207_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001A9F0u)
+
+/** Alias (User Manual Name) for CAN_MO207_DATAL.
+* To use register names with standard convension, please use CAN_MO207_DATAL.
+*/
+#define CAN_MODATAL207 (CAN_MO207_DATAL)
+
+/** \brief 29E0, Message Object Function Control Register */
+#define CAN_MO207_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001A9E0u)
+
+/** Alias (User Manual Name) for CAN_MO207_EDATA0.
+* To use register names with standard convension, please use CAN_MO207_EDATA0.
+*/
+#define CAN_EMO207DATA0 (CAN_MO207_EDATA0)
+
+/** \brief 29E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO207_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001A9E4u)
+
+/** Alias (User Manual Name) for CAN_MO207_EDATA1.
+* To use register names with standard convension, please use CAN_MO207_EDATA1.
+*/
+#define CAN_EMO207DATA1 (CAN_MO207_EDATA1)
+
+/** \brief 29E8, Message Object Interrupt Pointer Register */
+#define CAN_MO207_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001A9E8u)
+
+/** Alias (User Manual Name) for CAN_MO207_EDATA2.
+* To use register names with standard convension, please use CAN_MO207_EDATA2.
+*/
+#define CAN_EMO207DATA2 (CAN_MO207_EDATA2)
+
+/** \brief 29EC, Message Object Acceptance Mask Register */
+#define CAN_MO207_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001A9ECu)
+
+/** Alias (User Manual Name) for CAN_MO207_EDATA3.
+* To use register names with standard convension, please use CAN_MO207_EDATA3.
+*/
+#define CAN_EMO207DATA3 (CAN_MO207_EDATA3)
+
+/** \brief 29F0, Message Object Data Register Low */
+#define CAN_MO207_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001A9F0u)
+
+/** Alias (User Manual Name) for CAN_MO207_EDATA4.
+* To use register names with standard convension, please use CAN_MO207_EDATA4.
+*/
+#define CAN_EMO207DATA4 (CAN_MO207_EDATA4)
+
+/** \brief 29F4, Message Object Data Register High */
+#define CAN_MO207_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001A9F4u)
+
+/** Alias (User Manual Name) for CAN_MO207_EDATA5.
+* To use register names with standard convension, please use CAN_MO207_EDATA5.
+*/
+#define CAN_EMO207DATA5 (CAN_MO207_EDATA5)
+
+/** \brief 29F8, Message Object Arbitration Register */
+#define CAN_MO207_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001A9F8u)
+
+/** Alias (User Manual Name) for CAN_MO207_EDATA6.
+* To use register names with standard convension, please use CAN_MO207_EDATA6.
+*/
+#define CAN_EMO207DATA6 (CAN_MO207_EDATA6)
+
+/** \brief 29E0, Message Object Function Control Register */
+#define CAN_MO207_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001A9E0u)
+
+/** Alias (User Manual Name) for CAN_MO207_FCR.
+* To use register names with standard convension, please use CAN_MO207_FCR.
+*/
+#define CAN_MOFCR207 (CAN_MO207_FCR)
+
+/** \brief 29E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO207_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001A9E4u)
+
+/** Alias (User Manual Name) for CAN_MO207_FGPR.
+* To use register names with standard convension, please use CAN_MO207_FGPR.
+*/
+#define CAN_MOFGPR207 (CAN_MO207_FGPR)
+
+/** \brief 29E8, Message Object Interrupt Pointer Register */
+#define CAN_MO207_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001A9E8u)
+
+/** Alias (User Manual Name) for CAN_MO207_IPR.
+* To use register names with standard convension, please use CAN_MO207_IPR.
+*/
+#define CAN_MOIPR207 (CAN_MO207_IPR)
+
+/** \brief 29FC, Message Object Control Register */
+#define CAN_MO207_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001A9FCu)
+
+/** Alias (User Manual Name) for CAN_MO207_STAT.
+* To use register names with standard convension, please use CAN_MO207_STAT.
+*/
+#define CAN_MOSTAT207 (CAN_MO207_STAT)
+
+/** \brief 2A0C, Message Object Acceptance Mask Register */
+#define CAN_MO208_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AA0Cu)
+
+/** Alias (User Manual Name) for CAN_MO208_AMR.
+* To use register names with standard convension, please use CAN_MO208_AMR.
+*/
+#define CAN_MOAMR208 (CAN_MO208_AMR)
+
+/** \brief 2A18, Message Object Arbitration Register */
+#define CAN_MO208_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AA18u)
+
+/** Alias (User Manual Name) for CAN_MO208_AR.
+* To use register names with standard convension, please use CAN_MO208_AR.
+*/
+#define CAN_MOAR208 (CAN_MO208_AR)
+
+/** \brief 2A1C, Message Object Control Register */
+#define CAN_MO208_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AA1Cu)
+
+/** Alias (User Manual Name) for CAN_MO208_CTR.
+* To use register names with standard convension, please use CAN_MO208_CTR.
+*/
+#define CAN_MOCTR208 (CAN_MO208_CTR)
+
+/** \brief 2A14, Message Object Data Register High */
+#define CAN_MO208_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AA14u)
+
+/** Alias (User Manual Name) for CAN_MO208_DATAH.
+* To use register names with standard convension, please use CAN_MO208_DATAH.
+*/
+#define CAN_MODATAH208 (CAN_MO208_DATAH)
+
+/** \brief 2A10, Message Object Data Register Low */
+#define CAN_MO208_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AA10u)
+
+/** Alias (User Manual Name) for CAN_MO208_DATAL.
+* To use register names with standard convension, please use CAN_MO208_DATAL.
+*/
+#define CAN_MODATAL208 (CAN_MO208_DATAL)
+
+/** \brief 2A00, Message Object Function Control Register */
+#define CAN_MO208_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AA00u)
+
+/** Alias (User Manual Name) for CAN_MO208_EDATA0.
+* To use register names with standard convension, please use CAN_MO208_EDATA0.
+*/
+#define CAN_EMO208DATA0 (CAN_MO208_EDATA0)
+
+/** \brief 2A04, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO208_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AA04u)
+
+/** Alias (User Manual Name) for CAN_MO208_EDATA1.
+* To use register names with standard convension, please use CAN_MO208_EDATA1.
+*/
+#define CAN_EMO208DATA1 (CAN_MO208_EDATA1)
+
+/** \brief 2A08, Message Object Interrupt Pointer Register */
+#define CAN_MO208_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AA08u)
+
+/** Alias (User Manual Name) for CAN_MO208_EDATA2.
+* To use register names with standard convension, please use CAN_MO208_EDATA2.
+*/
+#define CAN_EMO208DATA2 (CAN_MO208_EDATA2)
+
+/** \brief 2A0C, Message Object Acceptance Mask Register */
+#define CAN_MO208_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AA0Cu)
+
+/** Alias (User Manual Name) for CAN_MO208_EDATA3.
+* To use register names with standard convension, please use CAN_MO208_EDATA3.
+*/
+#define CAN_EMO208DATA3 (CAN_MO208_EDATA3)
+
+/** \brief 2A10, Message Object Data Register Low */
+#define CAN_MO208_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AA10u)
+
+/** Alias (User Manual Name) for CAN_MO208_EDATA4.
+* To use register names with standard convension, please use CAN_MO208_EDATA4.
+*/
+#define CAN_EMO208DATA4 (CAN_MO208_EDATA4)
+
+/** \brief 2A14, Message Object Data Register High */
+#define CAN_MO208_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AA14u)
+
+/** Alias (User Manual Name) for CAN_MO208_EDATA5.
+* To use register names with standard convension, please use CAN_MO208_EDATA5.
+*/
+#define CAN_EMO208DATA5 (CAN_MO208_EDATA5)
+
+/** \brief 2A18, Message Object Arbitration Register */
+#define CAN_MO208_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AA18u)
+
+/** Alias (User Manual Name) for CAN_MO208_EDATA6.
+* To use register names with standard convension, please use CAN_MO208_EDATA6.
+*/
+#define CAN_EMO208DATA6 (CAN_MO208_EDATA6)
+
+/** \brief 2A00, Message Object Function Control Register */
+#define CAN_MO208_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AA00u)
+
+/** Alias (User Manual Name) for CAN_MO208_FCR.
+* To use register names with standard convension, please use CAN_MO208_FCR.
+*/
+#define CAN_MOFCR208 (CAN_MO208_FCR)
+
+/** \brief 2A04, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO208_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AA04u)
+
+/** Alias (User Manual Name) for CAN_MO208_FGPR.
+* To use register names with standard convension, please use CAN_MO208_FGPR.
+*/
+#define CAN_MOFGPR208 (CAN_MO208_FGPR)
+
+/** \brief 2A08, Message Object Interrupt Pointer Register */
+#define CAN_MO208_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AA08u)
+
+/** Alias (User Manual Name) for CAN_MO208_IPR.
+* To use register names with standard convension, please use CAN_MO208_IPR.
+*/
+#define CAN_MOIPR208 (CAN_MO208_IPR)
+
+/** \brief 2A1C, Message Object Control Register */
+#define CAN_MO208_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AA1Cu)
+
+/** Alias (User Manual Name) for CAN_MO208_STAT.
+* To use register names with standard convension, please use CAN_MO208_STAT.
+*/
+#define CAN_MOSTAT208 (CAN_MO208_STAT)
+
+/** \brief 2A2C, Message Object Acceptance Mask Register */
+#define CAN_MO209_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AA2Cu)
+
+/** Alias (User Manual Name) for CAN_MO209_AMR.
+* To use register names with standard convension, please use CAN_MO209_AMR.
+*/
+#define CAN_MOAMR209 (CAN_MO209_AMR)
+
+/** \brief 2A38, Message Object Arbitration Register */
+#define CAN_MO209_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AA38u)
+
+/** Alias (User Manual Name) for CAN_MO209_AR.
+* To use register names with standard convension, please use CAN_MO209_AR.
+*/
+#define CAN_MOAR209 (CAN_MO209_AR)
+
+/** \brief 2A3C, Message Object Control Register */
+#define CAN_MO209_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AA3Cu)
+
+/** Alias (User Manual Name) for CAN_MO209_CTR.
+* To use register names with standard convension, please use CAN_MO209_CTR.
+*/
+#define CAN_MOCTR209 (CAN_MO209_CTR)
+
+/** \brief 2A34, Message Object Data Register High */
+#define CAN_MO209_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AA34u)
+
+/** Alias (User Manual Name) for CAN_MO209_DATAH.
+* To use register names with standard convension, please use CAN_MO209_DATAH.
+*/
+#define CAN_MODATAH209 (CAN_MO209_DATAH)
+
+/** \brief 2A30, Message Object Data Register Low */
+#define CAN_MO209_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AA30u)
+
+/** Alias (User Manual Name) for CAN_MO209_DATAL.
+* To use register names with standard convension, please use CAN_MO209_DATAL.
+*/
+#define CAN_MODATAL209 (CAN_MO209_DATAL)
+
+/** \brief 2A20, Message Object Function Control Register */
+#define CAN_MO209_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AA20u)
+
+/** Alias (User Manual Name) for CAN_MO209_EDATA0.
+* To use register names with standard convension, please use CAN_MO209_EDATA0.
+*/
+#define CAN_EMO209DATA0 (CAN_MO209_EDATA0)
+
+/** \brief 2A24, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO209_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AA24u)
+
+/** Alias (User Manual Name) for CAN_MO209_EDATA1.
+* To use register names with standard convension, please use CAN_MO209_EDATA1.
+*/
+#define CAN_EMO209DATA1 (CAN_MO209_EDATA1)
+
+/** \brief 2A28, Message Object Interrupt Pointer Register */
+#define CAN_MO209_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AA28u)
+
+/** Alias (User Manual Name) for CAN_MO209_EDATA2.
+* To use register names with standard convension, please use CAN_MO209_EDATA2.
+*/
+#define CAN_EMO209DATA2 (CAN_MO209_EDATA2)
+
+/** \brief 2A2C, Message Object Acceptance Mask Register */
+#define CAN_MO209_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AA2Cu)
+
+/** Alias (User Manual Name) for CAN_MO209_EDATA3.
+* To use register names with standard convension, please use CAN_MO209_EDATA3.
+*/
+#define CAN_EMO209DATA3 (CAN_MO209_EDATA3)
+
+/** \brief 2A30, Message Object Data Register Low */
+#define CAN_MO209_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AA30u)
+
+/** Alias (User Manual Name) for CAN_MO209_EDATA4.
+* To use register names with standard convension, please use CAN_MO209_EDATA4.
+*/
+#define CAN_EMO209DATA4 (CAN_MO209_EDATA4)
+
+/** \brief 2A34, Message Object Data Register High */
+#define CAN_MO209_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AA34u)
+
+/** Alias (User Manual Name) for CAN_MO209_EDATA5.
+* To use register names with standard convension, please use CAN_MO209_EDATA5.
+*/
+#define CAN_EMO209DATA5 (CAN_MO209_EDATA5)
+
+/** \brief 2A38, Message Object Arbitration Register */
+#define CAN_MO209_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AA38u)
+
+/** Alias (User Manual Name) for CAN_MO209_EDATA6.
+* To use register names with standard convension, please use CAN_MO209_EDATA6.
+*/
+#define CAN_EMO209DATA6 (CAN_MO209_EDATA6)
+
+/** \brief 2A20, Message Object Function Control Register */
+#define CAN_MO209_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AA20u)
+
+/** Alias (User Manual Name) for CAN_MO209_FCR.
+* To use register names with standard convension, please use CAN_MO209_FCR.
+*/
+#define CAN_MOFCR209 (CAN_MO209_FCR)
+
+/** \brief 2A24, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO209_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AA24u)
+
+/** Alias (User Manual Name) for CAN_MO209_FGPR.
+* To use register names with standard convension, please use CAN_MO209_FGPR.
+*/
+#define CAN_MOFGPR209 (CAN_MO209_FGPR)
+
+/** \brief 2A28, Message Object Interrupt Pointer Register */
+#define CAN_MO209_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AA28u)
+
+/** Alias (User Manual Name) for CAN_MO209_IPR.
+* To use register names with standard convension, please use CAN_MO209_IPR.
+*/
+#define CAN_MOIPR209 (CAN_MO209_IPR)
+
+/** \brief 2A3C, Message Object Control Register */
+#define CAN_MO209_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AA3Cu)
+
+/** Alias (User Manual Name) for CAN_MO209_STAT.
+* To use register names with standard convension, please use CAN_MO209_STAT.
+*/
+#define CAN_MOSTAT209 (CAN_MO209_STAT)
+
+/** \brief 128C, Message Object Acceptance Mask Register */
+#define CAN_MO20_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001928Cu)
+
+/** Alias (User Manual Name) for CAN_MO20_AMR.
+* To use register names with standard convension, please use CAN_MO20_AMR.
+*/
+#define CAN_MOAMR20 (CAN_MO20_AMR)
+
+/** \brief 1298, Message Object Arbitration Register */
+#define CAN_MO20_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019298u)
+
+/** Alias (User Manual Name) for CAN_MO20_AR.
+* To use register names with standard convension, please use CAN_MO20_AR.
+*/
+#define CAN_MOAR20 (CAN_MO20_AR)
+
+/** \brief 129C, Message Object Control Register */
+#define CAN_MO20_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001929Cu)
+
+/** Alias (User Manual Name) for CAN_MO20_CTR.
+* To use register names with standard convension, please use CAN_MO20_CTR.
+*/
+#define CAN_MOCTR20 (CAN_MO20_CTR)
+
+/** \brief 1294, Message Object Data Register High */
+#define CAN_MO20_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019294u)
+
+/** Alias (User Manual Name) for CAN_MO20_DATAH.
+* To use register names with standard convension, please use CAN_MO20_DATAH.
+*/
+#define CAN_MODATAH20 (CAN_MO20_DATAH)
+
+/** \brief 1290, Message Object Data Register Low */
+#define CAN_MO20_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019290u)
+
+/** Alias (User Manual Name) for CAN_MO20_DATAL.
+* To use register names with standard convension, please use CAN_MO20_DATAL.
+*/
+#define CAN_MODATAL20 (CAN_MO20_DATAL)
+
+/** \brief 1280, Message Object Function Control Register */
+#define CAN_MO20_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019280u)
+
+/** Alias (User Manual Name) for CAN_MO20_EDATA0.
+* To use register names with standard convension, please use CAN_MO20_EDATA0.
+*/
+#define CAN_EMO20DATA0 (CAN_MO20_EDATA0)
+
+/** \brief 1284, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO20_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019284u)
+
+/** Alias (User Manual Name) for CAN_MO20_EDATA1.
+* To use register names with standard convension, please use CAN_MO20_EDATA1.
+*/
+#define CAN_EMO20DATA1 (CAN_MO20_EDATA1)
+
+/** \brief 1288, Message Object Interrupt Pointer Register */
+#define CAN_MO20_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019288u)
+
+/** Alias (User Manual Name) for CAN_MO20_EDATA2.
+* To use register names with standard convension, please use CAN_MO20_EDATA2.
+*/
+#define CAN_EMO20DATA2 (CAN_MO20_EDATA2)
+
+/** \brief 128C, Message Object Acceptance Mask Register */
+#define CAN_MO20_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001928Cu)
+
+/** Alias (User Manual Name) for CAN_MO20_EDATA3.
+* To use register names with standard convension, please use CAN_MO20_EDATA3.
+*/
+#define CAN_EMO20DATA3 (CAN_MO20_EDATA3)
+
+/** \brief 1290, Message Object Data Register Low */
+#define CAN_MO20_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019290u)
+
+/** Alias (User Manual Name) for CAN_MO20_EDATA4.
+* To use register names with standard convension, please use CAN_MO20_EDATA4.
+*/
+#define CAN_EMO20DATA4 (CAN_MO20_EDATA4)
+
+/** \brief 1294, Message Object Data Register High */
+#define CAN_MO20_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019294u)
+
+/** Alias (User Manual Name) for CAN_MO20_EDATA5.
+* To use register names with standard convension, please use CAN_MO20_EDATA5.
+*/
+#define CAN_EMO20DATA5 (CAN_MO20_EDATA5)
+
+/** \brief 1298, Message Object Arbitration Register */
+#define CAN_MO20_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019298u)
+
+/** Alias (User Manual Name) for CAN_MO20_EDATA6.
+* To use register names with standard convension, please use CAN_MO20_EDATA6.
+*/
+#define CAN_EMO20DATA6 (CAN_MO20_EDATA6)
+
+/** \brief 1280, Message Object Function Control Register */
+#define CAN_MO20_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019280u)
+
+/** Alias (User Manual Name) for CAN_MO20_FCR.
+* To use register names with standard convension, please use CAN_MO20_FCR.
+*/
+#define CAN_MOFCR20 (CAN_MO20_FCR)
+
+/** \brief 1284, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO20_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019284u)
+
+/** Alias (User Manual Name) for CAN_MO20_FGPR.
+* To use register names with standard convension, please use CAN_MO20_FGPR.
+*/
+#define CAN_MOFGPR20 (CAN_MO20_FGPR)
+
+/** \brief 1288, Message Object Interrupt Pointer Register */
+#define CAN_MO20_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019288u)
+
+/** Alias (User Manual Name) for CAN_MO20_IPR.
+* To use register names with standard convension, please use CAN_MO20_IPR.
+*/
+#define CAN_MOIPR20 (CAN_MO20_IPR)
+
+/** \brief 129C, Message Object Control Register */
+#define CAN_MO20_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001929Cu)
+
+/** Alias (User Manual Name) for CAN_MO20_STAT.
+* To use register names with standard convension, please use CAN_MO20_STAT.
+*/
+#define CAN_MOSTAT20 (CAN_MO20_STAT)
+
+/** \brief 2A4C, Message Object Acceptance Mask Register */
+#define CAN_MO210_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AA4Cu)
+
+/** Alias (User Manual Name) for CAN_MO210_AMR.
+* To use register names with standard convension, please use CAN_MO210_AMR.
+*/
+#define CAN_MOAMR210 (CAN_MO210_AMR)
+
+/** \brief 2A58, Message Object Arbitration Register */
+#define CAN_MO210_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AA58u)
+
+/** Alias (User Manual Name) for CAN_MO210_AR.
+* To use register names with standard convension, please use CAN_MO210_AR.
+*/
+#define CAN_MOAR210 (CAN_MO210_AR)
+
+/** \brief 2A5C, Message Object Control Register */
+#define CAN_MO210_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AA5Cu)
+
+/** Alias (User Manual Name) for CAN_MO210_CTR.
+* To use register names with standard convension, please use CAN_MO210_CTR.
+*/
+#define CAN_MOCTR210 (CAN_MO210_CTR)
+
+/** \brief 2A54, Message Object Data Register High */
+#define CAN_MO210_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AA54u)
+
+/** Alias (User Manual Name) for CAN_MO210_DATAH.
+* To use register names with standard convension, please use CAN_MO210_DATAH.
+*/
+#define CAN_MODATAH210 (CAN_MO210_DATAH)
+
+/** \brief 2A50, Message Object Data Register Low */
+#define CAN_MO210_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AA50u)
+
+/** Alias (User Manual Name) for CAN_MO210_DATAL.
+* To use register names with standard convension, please use CAN_MO210_DATAL.
+*/
+#define CAN_MODATAL210 (CAN_MO210_DATAL)
+
+/** \brief 2A40, Message Object Function Control Register */
+#define CAN_MO210_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AA40u)
+
+/** Alias (User Manual Name) for CAN_MO210_EDATA0.
+* To use register names with standard convension, please use CAN_MO210_EDATA0.
+*/
+#define CAN_EMO210DATA0 (CAN_MO210_EDATA0)
+
+/** \brief 2A44, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO210_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AA44u)
+
+/** Alias (User Manual Name) for CAN_MO210_EDATA1.
+* To use register names with standard convension, please use CAN_MO210_EDATA1.
+*/
+#define CAN_EMO210DATA1 (CAN_MO210_EDATA1)
+
+/** \brief 2A48, Message Object Interrupt Pointer Register */
+#define CAN_MO210_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AA48u)
+
+/** Alias (User Manual Name) for CAN_MO210_EDATA2.
+* To use register names with standard convension, please use CAN_MO210_EDATA2.
+*/
+#define CAN_EMO210DATA2 (CAN_MO210_EDATA2)
+
+/** \brief 2A4C, Message Object Acceptance Mask Register */
+#define CAN_MO210_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AA4Cu)
+
+/** Alias (User Manual Name) for CAN_MO210_EDATA3.
+* To use register names with standard convension, please use CAN_MO210_EDATA3.
+*/
+#define CAN_EMO210DATA3 (CAN_MO210_EDATA3)
+
+/** \brief 2A50, Message Object Data Register Low */
+#define CAN_MO210_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AA50u)
+
+/** Alias (User Manual Name) for CAN_MO210_EDATA4.
+* To use register names with standard convension, please use CAN_MO210_EDATA4.
+*/
+#define CAN_EMO210DATA4 (CAN_MO210_EDATA4)
+
+/** \brief 2A54, Message Object Data Register High */
+#define CAN_MO210_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AA54u)
+
+/** Alias (User Manual Name) for CAN_MO210_EDATA5.
+* To use register names with standard convension, please use CAN_MO210_EDATA5.
+*/
+#define CAN_EMO210DATA5 (CAN_MO210_EDATA5)
+
+/** \brief 2A58, Message Object Arbitration Register */
+#define CAN_MO210_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AA58u)
+
+/** Alias (User Manual Name) for CAN_MO210_EDATA6.
+* To use register names with standard convension, please use CAN_MO210_EDATA6.
+*/
+#define CAN_EMO210DATA6 (CAN_MO210_EDATA6)
+
+/** \brief 2A40, Message Object Function Control Register */
+#define CAN_MO210_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AA40u)
+
+/** Alias (User Manual Name) for CAN_MO210_FCR.
+* To use register names with standard convension, please use CAN_MO210_FCR.
+*/
+#define CAN_MOFCR210 (CAN_MO210_FCR)
+
+/** \brief 2A44, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO210_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AA44u)
+
+/** Alias (User Manual Name) for CAN_MO210_FGPR.
+* To use register names with standard convension, please use CAN_MO210_FGPR.
+*/
+#define CAN_MOFGPR210 (CAN_MO210_FGPR)
+
+/** \brief 2A48, Message Object Interrupt Pointer Register */
+#define CAN_MO210_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AA48u)
+
+/** Alias (User Manual Name) for CAN_MO210_IPR.
+* To use register names with standard convension, please use CAN_MO210_IPR.
+*/
+#define CAN_MOIPR210 (CAN_MO210_IPR)
+
+/** \brief 2A5C, Message Object Control Register */
+#define CAN_MO210_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AA5Cu)
+
+/** Alias (User Manual Name) for CAN_MO210_STAT.
+* To use register names with standard convension, please use CAN_MO210_STAT.
+*/
+#define CAN_MOSTAT210 (CAN_MO210_STAT)
+
+/** \brief 2A6C, Message Object Acceptance Mask Register */
+#define CAN_MO211_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AA6Cu)
+
+/** Alias (User Manual Name) for CAN_MO211_AMR.
+* To use register names with standard convension, please use CAN_MO211_AMR.
+*/
+#define CAN_MOAMR211 (CAN_MO211_AMR)
+
+/** \brief 2A78, Message Object Arbitration Register */
+#define CAN_MO211_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AA78u)
+
+/** Alias (User Manual Name) for CAN_MO211_AR.
+* To use register names with standard convension, please use CAN_MO211_AR.
+*/
+#define CAN_MOAR211 (CAN_MO211_AR)
+
+/** \brief 2A7C, Message Object Control Register */
+#define CAN_MO211_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AA7Cu)
+
+/** Alias (User Manual Name) for CAN_MO211_CTR.
+* To use register names with standard convension, please use CAN_MO211_CTR.
+*/
+#define CAN_MOCTR211 (CAN_MO211_CTR)
+
+/** \brief 2A74, Message Object Data Register High */
+#define CAN_MO211_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AA74u)
+
+/** Alias (User Manual Name) for CAN_MO211_DATAH.
+* To use register names with standard convension, please use CAN_MO211_DATAH.
+*/
+#define CAN_MODATAH211 (CAN_MO211_DATAH)
+
+/** \brief 2A70, Message Object Data Register Low */
+#define CAN_MO211_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AA70u)
+
+/** Alias (User Manual Name) for CAN_MO211_DATAL.
+* To use register names with standard convension, please use CAN_MO211_DATAL.
+*/
+#define CAN_MODATAL211 (CAN_MO211_DATAL)
+
+/** \brief 2A60, Message Object Function Control Register */
+#define CAN_MO211_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AA60u)
+
+/** Alias (User Manual Name) for CAN_MO211_EDATA0.
+* To use register names with standard convension, please use CAN_MO211_EDATA0.
+*/
+#define CAN_EMO211DATA0 (CAN_MO211_EDATA0)
+
+/** \brief 2A64, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO211_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AA64u)
+
+/** Alias (User Manual Name) for CAN_MO211_EDATA1.
+* To use register names with standard convension, please use CAN_MO211_EDATA1.
+*/
+#define CAN_EMO211DATA1 (CAN_MO211_EDATA1)
+
+/** \brief 2A68, Message Object Interrupt Pointer Register */
+#define CAN_MO211_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AA68u)
+
+/** Alias (User Manual Name) for CAN_MO211_EDATA2.
+* To use register names with standard convension, please use CAN_MO211_EDATA2.
+*/
+#define CAN_EMO211DATA2 (CAN_MO211_EDATA2)
+
+/** \brief 2A6C, Message Object Acceptance Mask Register */
+#define CAN_MO211_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AA6Cu)
+
+/** Alias (User Manual Name) for CAN_MO211_EDATA3.
+* To use register names with standard convension, please use CAN_MO211_EDATA3.
+*/
+#define CAN_EMO211DATA3 (CAN_MO211_EDATA3)
+
+/** \brief 2A70, Message Object Data Register Low */
+#define CAN_MO211_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AA70u)
+
+/** Alias (User Manual Name) for CAN_MO211_EDATA4.
+* To use register names with standard convension, please use CAN_MO211_EDATA4.
+*/
+#define CAN_EMO211DATA4 (CAN_MO211_EDATA4)
+
+/** \brief 2A74, Message Object Data Register High */
+#define CAN_MO211_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AA74u)
+
+/** Alias (User Manual Name) for CAN_MO211_EDATA5.
+* To use register names with standard convension, please use CAN_MO211_EDATA5.
+*/
+#define CAN_EMO211DATA5 (CAN_MO211_EDATA5)
+
+/** \brief 2A78, Message Object Arbitration Register */
+#define CAN_MO211_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AA78u)
+
+/** Alias (User Manual Name) for CAN_MO211_EDATA6.
+* To use register names with standard convension, please use CAN_MO211_EDATA6.
+*/
+#define CAN_EMO211DATA6 (CAN_MO211_EDATA6)
+
+/** \brief 2A60, Message Object Function Control Register */
+#define CAN_MO211_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AA60u)
+
+/** Alias (User Manual Name) for CAN_MO211_FCR.
+* To use register names with standard convension, please use CAN_MO211_FCR.
+*/
+#define CAN_MOFCR211 (CAN_MO211_FCR)
+
+/** \brief 2A64, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO211_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AA64u)
+
+/** Alias (User Manual Name) for CAN_MO211_FGPR.
+* To use register names with standard convension, please use CAN_MO211_FGPR.
+*/
+#define CAN_MOFGPR211 (CAN_MO211_FGPR)
+
+/** \brief 2A68, Message Object Interrupt Pointer Register */
+#define CAN_MO211_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AA68u)
+
+/** Alias (User Manual Name) for CAN_MO211_IPR.
+* To use register names with standard convension, please use CAN_MO211_IPR.
+*/
+#define CAN_MOIPR211 (CAN_MO211_IPR)
+
+/** \brief 2A7C, Message Object Control Register */
+#define CAN_MO211_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AA7Cu)
+
+/** Alias (User Manual Name) for CAN_MO211_STAT.
+* To use register names with standard convension, please use CAN_MO211_STAT.
+*/
+#define CAN_MOSTAT211 (CAN_MO211_STAT)
+
+/** \brief 2A8C, Message Object Acceptance Mask Register */
+#define CAN_MO212_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AA8Cu)
+
+/** Alias (User Manual Name) for CAN_MO212_AMR.
+* To use register names with standard convension, please use CAN_MO212_AMR.
+*/
+#define CAN_MOAMR212 (CAN_MO212_AMR)
+
+/** \brief 2A98, Message Object Arbitration Register */
+#define CAN_MO212_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AA98u)
+
+/** Alias (User Manual Name) for CAN_MO212_AR.
+* To use register names with standard convension, please use CAN_MO212_AR.
+*/
+#define CAN_MOAR212 (CAN_MO212_AR)
+
+/** \brief 2A9C, Message Object Control Register */
+#define CAN_MO212_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AA9Cu)
+
+/** Alias (User Manual Name) for CAN_MO212_CTR.
+* To use register names with standard convension, please use CAN_MO212_CTR.
+*/
+#define CAN_MOCTR212 (CAN_MO212_CTR)
+
+/** \brief 2A94, Message Object Data Register High */
+#define CAN_MO212_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AA94u)
+
+/** Alias (User Manual Name) for CAN_MO212_DATAH.
+* To use register names with standard convension, please use CAN_MO212_DATAH.
+*/
+#define CAN_MODATAH212 (CAN_MO212_DATAH)
+
+/** \brief 2A90, Message Object Data Register Low */
+#define CAN_MO212_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AA90u)
+
+/** Alias (User Manual Name) for CAN_MO212_DATAL.
+* To use register names with standard convension, please use CAN_MO212_DATAL.
+*/
+#define CAN_MODATAL212 (CAN_MO212_DATAL)
+
+/** \brief 2A80, Message Object Function Control Register */
+#define CAN_MO212_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AA80u)
+
+/** Alias (User Manual Name) for CAN_MO212_EDATA0.
+* To use register names with standard convension, please use CAN_MO212_EDATA0.
+*/
+#define CAN_EMO212DATA0 (CAN_MO212_EDATA0)
+
+/** \brief 2A84, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO212_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AA84u)
+
+/** Alias (User Manual Name) for CAN_MO212_EDATA1.
+* To use register names with standard convension, please use CAN_MO212_EDATA1.
+*/
+#define CAN_EMO212DATA1 (CAN_MO212_EDATA1)
+
+/** \brief 2A88, Message Object Interrupt Pointer Register */
+#define CAN_MO212_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AA88u)
+
+/** Alias (User Manual Name) for CAN_MO212_EDATA2.
+* To use register names with standard convension, please use CAN_MO212_EDATA2.
+*/
+#define CAN_EMO212DATA2 (CAN_MO212_EDATA2)
+
+/** \brief 2A8C, Message Object Acceptance Mask Register */
+#define CAN_MO212_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AA8Cu)
+
+/** Alias (User Manual Name) for CAN_MO212_EDATA3.
+* To use register names with standard convension, please use CAN_MO212_EDATA3.
+*/
+#define CAN_EMO212DATA3 (CAN_MO212_EDATA3)
+
+/** \brief 2A90, Message Object Data Register Low */
+#define CAN_MO212_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AA90u)
+
+/** Alias (User Manual Name) for CAN_MO212_EDATA4.
+* To use register names with standard convension, please use CAN_MO212_EDATA4.
+*/
+#define CAN_EMO212DATA4 (CAN_MO212_EDATA4)
+
+/** \brief 2A94, Message Object Data Register High */
+#define CAN_MO212_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AA94u)
+
+/** Alias (User Manual Name) for CAN_MO212_EDATA5.
+* To use register names with standard convension, please use CAN_MO212_EDATA5.
+*/
+#define CAN_EMO212DATA5 (CAN_MO212_EDATA5)
+
+/** \brief 2A98, Message Object Arbitration Register */
+#define CAN_MO212_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AA98u)
+
+/** Alias (User Manual Name) for CAN_MO212_EDATA6.
+* To use register names with standard convension, please use CAN_MO212_EDATA6.
+*/
+#define CAN_EMO212DATA6 (CAN_MO212_EDATA6)
+
+/** \brief 2A80, Message Object Function Control Register */
+#define CAN_MO212_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AA80u)
+
+/** Alias (User Manual Name) for CAN_MO212_FCR.
+* To use register names with standard convension, please use CAN_MO212_FCR.
+*/
+#define CAN_MOFCR212 (CAN_MO212_FCR)
+
+/** \brief 2A84, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO212_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AA84u)
+
+/** Alias (User Manual Name) for CAN_MO212_FGPR.
+* To use register names with standard convension, please use CAN_MO212_FGPR.
+*/
+#define CAN_MOFGPR212 (CAN_MO212_FGPR)
+
+/** \brief 2A88, Message Object Interrupt Pointer Register */
+#define CAN_MO212_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AA88u)
+
+/** Alias (User Manual Name) for CAN_MO212_IPR.
+* To use register names with standard convension, please use CAN_MO212_IPR.
+*/
+#define CAN_MOIPR212 (CAN_MO212_IPR)
+
+/** \brief 2A9C, Message Object Control Register */
+#define CAN_MO212_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AA9Cu)
+
+/** Alias (User Manual Name) for CAN_MO212_STAT.
+* To use register names with standard convension, please use CAN_MO212_STAT.
+*/
+#define CAN_MOSTAT212 (CAN_MO212_STAT)
+
+/** \brief 2AAC, Message Object Acceptance Mask Register */
+#define CAN_MO213_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AAACu)
+
+/** Alias (User Manual Name) for CAN_MO213_AMR.
+* To use register names with standard convension, please use CAN_MO213_AMR.
+*/
+#define CAN_MOAMR213 (CAN_MO213_AMR)
+
+/** \brief 2AB8, Message Object Arbitration Register */
+#define CAN_MO213_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AAB8u)
+
+/** Alias (User Manual Name) for CAN_MO213_AR.
+* To use register names with standard convension, please use CAN_MO213_AR.
+*/
+#define CAN_MOAR213 (CAN_MO213_AR)
+
+/** \brief 2ABC, Message Object Control Register */
+#define CAN_MO213_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AABCu)
+
+/** Alias (User Manual Name) for CAN_MO213_CTR.
+* To use register names with standard convension, please use CAN_MO213_CTR.
+*/
+#define CAN_MOCTR213 (CAN_MO213_CTR)
+
+/** \brief 2AB4, Message Object Data Register High */
+#define CAN_MO213_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AAB4u)
+
+/** Alias (User Manual Name) for CAN_MO213_DATAH.
+* To use register names with standard convension, please use CAN_MO213_DATAH.
+*/
+#define CAN_MODATAH213 (CAN_MO213_DATAH)
+
+/** \brief 2AB0, Message Object Data Register Low */
+#define CAN_MO213_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AAB0u)
+
+/** Alias (User Manual Name) for CAN_MO213_DATAL.
+* To use register names with standard convension, please use CAN_MO213_DATAL.
+*/
+#define CAN_MODATAL213 (CAN_MO213_DATAL)
+
+/** \brief 2AA0, Message Object Function Control Register */
+#define CAN_MO213_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AAA0u)
+
+/** Alias (User Manual Name) for CAN_MO213_EDATA0.
+* To use register names with standard convension, please use CAN_MO213_EDATA0.
+*/
+#define CAN_EMO213DATA0 (CAN_MO213_EDATA0)
+
+/** \brief 2AA4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO213_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AAA4u)
+
+/** Alias (User Manual Name) for CAN_MO213_EDATA1.
+* To use register names with standard convension, please use CAN_MO213_EDATA1.
+*/
+#define CAN_EMO213DATA1 (CAN_MO213_EDATA1)
+
+/** \brief 2AA8, Message Object Interrupt Pointer Register */
+#define CAN_MO213_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AAA8u)
+
+/** Alias (User Manual Name) for CAN_MO213_EDATA2.
+* To use register names with standard convension, please use CAN_MO213_EDATA2.
+*/
+#define CAN_EMO213DATA2 (CAN_MO213_EDATA2)
+
+/** \brief 2AAC, Message Object Acceptance Mask Register */
+#define CAN_MO213_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AAACu)
+
+/** Alias (User Manual Name) for CAN_MO213_EDATA3.
+* To use register names with standard convension, please use CAN_MO213_EDATA3.
+*/
+#define CAN_EMO213DATA3 (CAN_MO213_EDATA3)
+
+/** \brief 2AB0, Message Object Data Register Low */
+#define CAN_MO213_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AAB0u)
+
+/** Alias (User Manual Name) for CAN_MO213_EDATA4.
+* To use register names with standard convension, please use CAN_MO213_EDATA4.
+*/
+#define CAN_EMO213DATA4 (CAN_MO213_EDATA4)
+
+/** \brief 2AB4, Message Object Data Register High */
+#define CAN_MO213_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AAB4u)
+
+/** Alias (User Manual Name) for CAN_MO213_EDATA5.
+* To use register names with standard convension, please use CAN_MO213_EDATA5.
+*/
+#define CAN_EMO213DATA5 (CAN_MO213_EDATA5)
+
+/** \brief 2AB8, Message Object Arbitration Register */
+#define CAN_MO213_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AAB8u)
+
+/** Alias (User Manual Name) for CAN_MO213_EDATA6.
+* To use register names with standard convension, please use CAN_MO213_EDATA6.
+*/
+#define CAN_EMO213DATA6 (CAN_MO213_EDATA6)
+
+/** \brief 2AA0, Message Object Function Control Register */
+#define CAN_MO213_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AAA0u)
+
+/** Alias (User Manual Name) for CAN_MO213_FCR.
+* To use register names with standard convension, please use CAN_MO213_FCR.
+*/
+#define CAN_MOFCR213 (CAN_MO213_FCR)
+
+/** \brief 2AA4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO213_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AAA4u)
+
+/** Alias (User Manual Name) for CAN_MO213_FGPR.
+* To use register names with standard convension, please use CAN_MO213_FGPR.
+*/
+#define CAN_MOFGPR213 (CAN_MO213_FGPR)
+
+/** \brief 2AA8, Message Object Interrupt Pointer Register */
+#define CAN_MO213_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AAA8u)
+
+/** Alias (User Manual Name) for CAN_MO213_IPR.
+* To use register names with standard convension, please use CAN_MO213_IPR.
+*/
+#define CAN_MOIPR213 (CAN_MO213_IPR)
+
+/** \brief 2ABC, Message Object Control Register */
+#define CAN_MO213_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AABCu)
+
+/** Alias (User Manual Name) for CAN_MO213_STAT.
+* To use register names with standard convension, please use CAN_MO213_STAT.
+*/
+#define CAN_MOSTAT213 (CAN_MO213_STAT)
+
+/** \brief 2ACC, Message Object Acceptance Mask Register */
+#define CAN_MO214_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AACCu)
+
+/** Alias (User Manual Name) for CAN_MO214_AMR.
+* To use register names with standard convension, please use CAN_MO214_AMR.
+*/
+#define CAN_MOAMR214 (CAN_MO214_AMR)
+
+/** \brief 2AD8, Message Object Arbitration Register */
+#define CAN_MO214_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AAD8u)
+
+/** Alias (User Manual Name) for CAN_MO214_AR.
+* To use register names with standard convension, please use CAN_MO214_AR.
+*/
+#define CAN_MOAR214 (CAN_MO214_AR)
+
+/** \brief 2ADC, Message Object Control Register */
+#define CAN_MO214_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AADCu)
+
+/** Alias (User Manual Name) for CAN_MO214_CTR.
+* To use register names with standard convension, please use CAN_MO214_CTR.
+*/
+#define CAN_MOCTR214 (CAN_MO214_CTR)
+
+/** \brief 2AD4, Message Object Data Register High */
+#define CAN_MO214_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AAD4u)
+
+/** Alias (User Manual Name) for CAN_MO214_DATAH.
+* To use register names with standard convension, please use CAN_MO214_DATAH.
+*/
+#define CAN_MODATAH214 (CAN_MO214_DATAH)
+
+/** \brief 2AD0, Message Object Data Register Low */
+#define CAN_MO214_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AAD0u)
+
+/** Alias (User Manual Name) for CAN_MO214_DATAL.
+* To use register names with standard convension, please use CAN_MO214_DATAL.
+*/
+#define CAN_MODATAL214 (CAN_MO214_DATAL)
+
+/** \brief 2AC0, Message Object Function Control Register */
+#define CAN_MO214_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AAC0u)
+
+/** Alias (User Manual Name) for CAN_MO214_EDATA0.
+* To use register names with standard convension, please use CAN_MO214_EDATA0.
+*/
+#define CAN_EMO214DATA0 (CAN_MO214_EDATA0)
+
+/** \brief 2AC4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO214_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AAC4u)
+
+/** Alias (User Manual Name) for CAN_MO214_EDATA1.
+* To use register names with standard convension, please use CAN_MO214_EDATA1.
+*/
+#define CAN_EMO214DATA1 (CAN_MO214_EDATA1)
+
+/** \brief 2AC8, Message Object Interrupt Pointer Register */
+#define CAN_MO214_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AAC8u)
+
+/** Alias (User Manual Name) for CAN_MO214_EDATA2.
+* To use register names with standard convension, please use CAN_MO214_EDATA2.
+*/
+#define CAN_EMO214DATA2 (CAN_MO214_EDATA2)
+
+/** \brief 2ACC, Message Object Acceptance Mask Register */
+#define CAN_MO214_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AACCu)
+
+/** Alias (User Manual Name) for CAN_MO214_EDATA3.
+* To use register names with standard convension, please use CAN_MO214_EDATA3.
+*/
+#define CAN_EMO214DATA3 (CAN_MO214_EDATA3)
+
+/** \brief 2AD0, Message Object Data Register Low */
+#define CAN_MO214_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AAD0u)
+
+/** Alias (User Manual Name) for CAN_MO214_EDATA4.
+* To use register names with standard convension, please use CAN_MO214_EDATA4.
+*/
+#define CAN_EMO214DATA4 (CAN_MO214_EDATA4)
+
+/** \brief 2AD4, Message Object Data Register High */
+#define CAN_MO214_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AAD4u)
+
+/** Alias (User Manual Name) for CAN_MO214_EDATA5.
+* To use register names with standard convension, please use CAN_MO214_EDATA5.
+*/
+#define CAN_EMO214DATA5 (CAN_MO214_EDATA5)
+
+/** \brief 2AD8, Message Object Arbitration Register */
+#define CAN_MO214_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AAD8u)
+
+/** Alias (User Manual Name) for CAN_MO214_EDATA6.
+* To use register names with standard convension, please use CAN_MO214_EDATA6.
+*/
+#define CAN_EMO214DATA6 (CAN_MO214_EDATA6)
+
+/** \brief 2AC0, Message Object Function Control Register */
+#define CAN_MO214_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AAC0u)
+
+/** Alias (User Manual Name) for CAN_MO214_FCR.
+* To use register names with standard convension, please use CAN_MO214_FCR.
+*/
+#define CAN_MOFCR214 (CAN_MO214_FCR)
+
+/** \brief 2AC4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO214_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AAC4u)
+
+/** Alias (User Manual Name) for CAN_MO214_FGPR.
+* To use register names with standard convension, please use CAN_MO214_FGPR.
+*/
+#define CAN_MOFGPR214 (CAN_MO214_FGPR)
+
+/** \brief 2AC8, Message Object Interrupt Pointer Register */
+#define CAN_MO214_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AAC8u)
+
+/** Alias (User Manual Name) for CAN_MO214_IPR.
+* To use register names with standard convension, please use CAN_MO214_IPR.
+*/
+#define CAN_MOIPR214 (CAN_MO214_IPR)
+
+/** \brief 2ADC, Message Object Control Register */
+#define CAN_MO214_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AADCu)
+
+/** Alias (User Manual Name) for CAN_MO214_STAT.
+* To use register names with standard convension, please use CAN_MO214_STAT.
+*/
+#define CAN_MOSTAT214 (CAN_MO214_STAT)
+
+/** \brief 2AEC, Message Object Acceptance Mask Register */
+#define CAN_MO215_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AAECu)
+
+/** Alias (User Manual Name) for CAN_MO215_AMR.
+* To use register names with standard convension, please use CAN_MO215_AMR.
+*/
+#define CAN_MOAMR215 (CAN_MO215_AMR)
+
+/** \brief 2AF8, Message Object Arbitration Register */
+#define CAN_MO215_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AAF8u)
+
+/** Alias (User Manual Name) for CAN_MO215_AR.
+* To use register names with standard convension, please use CAN_MO215_AR.
+*/
+#define CAN_MOAR215 (CAN_MO215_AR)
+
+/** \brief 2AFC, Message Object Control Register */
+#define CAN_MO215_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AAFCu)
+
+/** Alias (User Manual Name) for CAN_MO215_CTR.
+* To use register names with standard convension, please use CAN_MO215_CTR.
+*/
+#define CAN_MOCTR215 (CAN_MO215_CTR)
+
+/** \brief 2AF4, Message Object Data Register High */
+#define CAN_MO215_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AAF4u)
+
+/** Alias (User Manual Name) for CAN_MO215_DATAH.
+* To use register names with standard convension, please use CAN_MO215_DATAH.
+*/
+#define CAN_MODATAH215 (CAN_MO215_DATAH)
+
+/** \brief 2AF0, Message Object Data Register Low */
+#define CAN_MO215_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AAF0u)
+
+/** Alias (User Manual Name) for CAN_MO215_DATAL.
+* To use register names with standard convension, please use CAN_MO215_DATAL.
+*/
+#define CAN_MODATAL215 (CAN_MO215_DATAL)
+
+/** \brief 2AE0, Message Object Function Control Register */
+#define CAN_MO215_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AAE0u)
+
+/** Alias (User Manual Name) for CAN_MO215_EDATA0.
+* To use register names with standard convension, please use CAN_MO215_EDATA0.
+*/
+#define CAN_EMO215DATA0 (CAN_MO215_EDATA0)
+
+/** \brief 2AE4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO215_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AAE4u)
+
+/** Alias (User Manual Name) for CAN_MO215_EDATA1.
+* To use register names with standard convension, please use CAN_MO215_EDATA1.
+*/
+#define CAN_EMO215DATA1 (CAN_MO215_EDATA1)
+
+/** \brief 2AE8, Message Object Interrupt Pointer Register */
+#define CAN_MO215_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AAE8u)
+
+/** Alias (User Manual Name) for CAN_MO215_EDATA2.
+* To use register names with standard convension, please use CAN_MO215_EDATA2.
+*/
+#define CAN_EMO215DATA2 (CAN_MO215_EDATA2)
+
+/** \brief 2AEC, Message Object Acceptance Mask Register */
+#define CAN_MO215_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AAECu)
+
+/** Alias (User Manual Name) for CAN_MO215_EDATA3.
+* To use register names with standard convension, please use CAN_MO215_EDATA3.
+*/
+#define CAN_EMO215DATA3 (CAN_MO215_EDATA3)
+
+/** \brief 2AF0, Message Object Data Register Low */
+#define CAN_MO215_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AAF0u)
+
+/** Alias (User Manual Name) for CAN_MO215_EDATA4.
+* To use register names with standard convension, please use CAN_MO215_EDATA4.
+*/
+#define CAN_EMO215DATA4 (CAN_MO215_EDATA4)
+
+/** \brief 2AF4, Message Object Data Register High */
+#define CAN_MO215_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AAF4u)
+
+/** Alias (User Manual Name) for CAN_MO215_EDATA5.
+* To use register names with standard convension, please use CAN_MO215_EDATA5.
+*/
+#define CAN_EMO215DATA5 (CAN_MO215_EDATA5)
+
+/** \brief 2AF8, Message Object Arbitration Register */
+#define CAN_MO215_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AAF8u)
+
+/** Alias (User Manual Name) for CAN_MO215_EDATA6.
+* To use register names with standard convension, please use CAN_MO215_EDATA6.
+*/
+#define CAN_EMO215DATA6 (CAN_MO215_EDATA6)
+
+/** \brief 2AE0, Message Object Function Control Register */
+#define CAN_MO215_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AAE0u)
+
+/** Alias (User Manual Name) for CAN_MO215_FCR.
+* To use register names with standard convension, please use CAN_MO215_FCR.
+*/
+#define CAN_MOFCR215 (CAN_MO215_FCR)
+
+/** \brief 2AE4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO215_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AAE4u)
+
+/** Alias (User Manual Name) for CAN_MO215_FGPR.
+* To use register names with standard convension, please use CAN_MO215_FGPR.
+*/
+#define CAN_MOFGPR215 (CAN_MO215_FGPR)
+
+/** \brief 2AE8, Message Object Interrupt Pointer Register */
+#define CAN_MO215_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AAE8u)
+
+/** Alias (User Manual Name) for CAN_MO215_IPR.
+* To use register names with standard convension, please use CAN_MO215_IPR.
+*/
+#define CAN_MOIPR215 (CAN_MO215_IPR)
+
+/** \brief 2AFC, Message Object Control Register */
+#define CAN_MO215_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AAFCu)
+
+/** Alias (User Manual Name) for CAN_MO215_STAT.
+* To use register names with standard convension, please use CAN_MO215_STAT.
+*/
+#define CAN_MOSTAT215 (CAN_MO215_STAT)
+
+/** \brief 2B0C, Message Object Acceptance Mask Register */
+#define CAN_MO216_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AB0Cu)
+
+/** Alias (User Manual Name) for CAN_MO216_AMR.
+* To use register names with standard convension, please use CAN_MO216_AMR.
+*/
+#define CAN_MOAMR216 (CAN_MO216_AMR)
+
+/** \brief 2B18, Message Object Arbitration Register */
+#define CAN_MO216_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AB18u)
+
+/** Alias (User Manual Name) for CAN_MO216_AR.
+* To use register names with standard convension, please use CAN_MO216_AR.
+*/
+#define CAN_MOAR216 (CAN_MO216_AR)
+
+/** \brief 2B1C, Message Object Control Register */
+#define CAN_MO216_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AB1Cu)
+
+/** Alias (User Manual Name) for CAN_MO216_CTR.
+* To use register names with standard convension, please use CAN_MO216_CTR.
+*/
+#define CAN_MOCTR216 (CAN_MO216_CTR)
+
+/** \brief 2B14, Message Object Data Register High */
+#define CAN_MO216_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AB14u)
+
+/** Alias (User Manual Name) for CAN_MO216_DATAH.
+* To use register names with standard convension, please use CAN_MO216_DATAH.
+*/
+#define CAN_MODATAH216 (CAN_MO216_DATAH)
+
+/** \brief 2B10, Message Object Data Register Low */
+#define CAN_MO216_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AB10u)
+
+/** Alias (User Manual Name) for CAN_MO216_DATAL.
+* To use register names with standard convension, please use CAN_MO216_DATAL.
+*/
+#define CAN_MODATAL216 (CAN_MO216_DATAL)
+
+/** \brief 2B00, Message Object Function Control Register */
+#define CAN_MO216_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AB00u)
+
+/** Alias (User Manual Name) for CAN_MO216_EDATA0.
+* To use register names with standard convension, please use CAN_MO216_EDATA0.
+*/
+#define CAN_EMO216DATA0 (CAN_MO216_EDATA0)
+
+/** \brief 2B04, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO216_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AB04u)
+
+/** Alias (User Manual Name) for CAN_MO216_EDATA1.
+* To use register names with standard convension, please use CAN_MO216_EDATA1.
+*/
+#define CAN_EMO216DATA1 (CAN_MO216_EDATA1)
+
+/** \brief 2B08, Message Object Interrupt Pointer Register */
+#define CAN_MO216_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AB08u)
+
+/** Alias (User Manual Name) for CAN_MO216_EDATA2.
+* To use register names with standard convension, please use CAN_MO216_EDATA2.
+*/
+#define CAN_EMO216DATA2 (CAN_MO216_EDATA2)
+
+/** \brief 2B0C, Message Object Acceptance Mask Register */
+#define CAN_MO216_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AB0Cu)
+
+/** Alias (User Manual Name) for CAN_MO216_EDATA3.
+* To use register names with standard convension, please use CAN_MO216_EDATA3.
+*/
+#define CAN_EMO216DATA3 (CAN_MO216_EDATA3)
+
+/** \brief 2B10, Message Object Data Register Low */
+#define CAN_MO216_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AB10u)
+
+/** Alias (User Manual Name) for CAN_MO216_EDATA4.
+* To use register names with standard convension, please use CAN_MO216_EDATA4.
+*/
+#define CAN_EMO216DATA4 (CAN_MO216_EDATA4)
+
+/** \brief 2B14, Message Object Data Register High */
+#define CAN_MO216_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AB14u)
+
+/** Alias (User Manual Name) for CAN_MO216_EDATA5.
+* To use register names with standard convension, please use CAN_MO216_EDATA5.
+*/
+#define CAN_EMO216DATA5 (CAN_MO216_EDATA5)
+
+/** \brief 2B18, Message Object Arbitration Register */
+#define CAN_MO216_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AB18u)
+
+/** Alias (User Manual Name) for CAN_MO216_EDATA6.
+* To use register names with standard convension, please use CAN_MO216_EDATA6.
+*/
+#define CAN_EMO216DATA6 (CAN_MO216_EDATA6)
+
+/** \brief 2B00, Message Object Function Control Register */
+#define CAN_MO216_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AB00u)
+
+/** Alias (User Manual Name) for CAN_MO216_FCR.
+* To use register names with standard convension, please use CAN_MO216_FCR.
+*/
+#define CAN_MOFCR216 (CAN_MO216_FCR)
+
+/** \brief 2B04, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO216_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AB04u)
+
+/** Alias (User Manual Name) for CAN_MO216_FGPR.
+* To use register names with standard convension, please use CAN_MO216_FGPR.
+*/
+#define CAN_MOFGPR216 (CAN_MO216_FGPR)
+
+/** \brief 2B08, Message Object Interrupt Pointer Register */
+#define CAN_MO216_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AB08u)
+
+/** Alias (User Manual Name) for CAN_MO216_IPR.
+* To use register names with standard convension, please use CAN_MO216_IPR.
+*/
+#define CAN_MOIPR216 (CAN_MO216_IPR)
+
+/** \brief 2B1C, Message Object Control Register */
+#define CAN_MO216_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AB1Cu)
+
+/** Alias (User Manual Name) for CAN_MO216_STAT.
+* To use register names with standard convension, please use CAN_MO216_STAT.
+*/
+#define CAN_MOSTAT216 (CAN_MO216_STAT)
+
+/** \brief 2B2C, Message Object Acceptance Mask Register */
+#define CAN_MO217_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AB2Cu)
+
+/** Alias (User Manual Name) for CAN_MO217_AMR.
+* To use register names with standard convension, please use CAN_MO217_AMR.
+*/
+#define CAN_MOAMR217 (CAN_MO217_AMR)
+
+/** \brief 2B38, Message Object Arbitration Register */
+#define CAN_MO217_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AB38u)
+
+/** Alias (User Manual Name) for CAN_MO217_AR.
+* To use register names with standard convension, please use CAN_MO217_AR.
+*/
+#define CAN_MOAR217 (CAN_MO217_AR)
+
+/** \brief 2B3C, Message Object Control Register */
+#define CAN_MO217_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AB3Cu)
+
+/** Alias (User Manual Name) for CAN_MO217_CTR.
+* To use register names with standard convension, please use CAN_MO217_CTR.
+*/
+#define CAN_MOCTR217 (CAN_MO217_CTR)
+
+/** \brief 2B34, Message Object Data Register High */
+#define CAN_MO217_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AB34u)
+
+/** Alias (User Manual Name) for CAN_MO217_DATAH.
+* To use register names with standard convension, please use CAN_MO217_DATAH.
+*/
+#define CAN_MODATAH217 (CAN_MO217_DATAH)
+
+/** \brief 2B30, Message Object Data Register Low */
+#define CAN_MO217_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AB30u)
+
+/** Alias (User Manual Name) for CAN_MO217_DATAL.
+* To use register names with standard convension, please use CAN_MO217_DATAL.
+*/
+#define CAN_MODATAL217 (CAN_MO217_DATAL)
+
+/** \brief 2B20, Message Object Function Control Register */
+#define CAN_MO217_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AB20u)
+
+/** Alias (User Manual Name) for CAN_MO217_EDATA0.
+* To use register names with standard convension, please use CAN_MO217_EDATA0.
+*/
+#define CAN_EMO217DATA0 (CAN_MO217_EDATA0)
+
+/** \brief 2B24, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO217_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AB24u)
+
+/** Alias (User Manual Name) for CAN_MO217_EDATA1.
+* To use register names with standard convension, please use CAN_MO217_EDATA1.
+*/
+#define CAN_EMO217DATA1 (CAN_MO217_EDATA1)
+
+/** \brief 2B28, Message Object Interrupt Pointer Register */
+#define CAN_MO217_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AB28u)
+
+/** Alias (User Manual Name) for CAN_MO217_EDATA2.
+* To use register names with standard convension, please use CAN_MO217_EDATA2.
+*/
+#define CAN_EMO217DATA2 (CAN_MO217_EDATA2)
+
+/** \brief 2B2C, Message Object Acceptance Mask Register */
+#define CAN_MO217_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AB2Cu)
+
+/** Alias (User Manual Name) for CAN_MO217_EDATA3.
+* To use register names with standard convension, please use CAN_MO217_EDATA3.
+*/
+#define CAN_EMO217DATA3 (CAN_MO217_EDATA3)
+
+/** \brief 2B30, Message Object Data Register Low */
+#define CAN_MO217_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AB30u)
+
+/** Alias (User Manual Name) for CAN_MO217_EDATA4.
+* To use register names with standard convension, please use CAN_MO217_EDATA4.
+*/
+#define CAN_EMO217DATA4 (CAN_MO217_EDATA4)
+
+/** \brief 2B34, Message Object Data Register High */
+#define CAN_MO217_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AB34u)
+
+/** Alias (User Manual Name) for CAN_MO217_EDATA5.
+* To use register names with standard convension, please use CAN_MO217_EDATA5.
+*/
+#define CAN_EMO217DATA5 (CAN_MO217_EDATA5)
+
+/** \brief 2B38, Message Object Arbitration Register */
+#define CAN_MO217_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AB38u)
+
+/** Alias (User Manual Name) for CAN_MO217_EDATA6.
+* To use register names with standard convension, please use CAN_MO217_EDATA6.
+*/
+#define CAN_EMO217DATA6 (CAN_MO217_EDATA6)
+
+/** \brief 2B20, Message Object Function Control Register */
+#define CAN_MO217_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AB20u)
+
+/** Alias (User Manual Name) for CAN_MO217_FCR.
+* To use register names with standard convension, please use CAN_MO217_FCR.
+*/
+#define CAN_MOFCR217 (CAN_MO217_FCR)
+
+/** \brief 2B24, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO217_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AB24u)
+
+/** Alias (User Manual Name) for CAN_MO217_FGPR.
+* To use register names with standard convension, please use CAN_MO217_FGPR.
+*/
+#define CAN_MOFGPR217 (CAN_MO217_FGPR)
+
+/** \brief 2B28, Message Object Interrupt Pointer Register */
+#define CAN_MO217_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AB28u)
+
+/** Alias (User Manual Name) for CAN_MO217_IPR.
+* To use register names with standard convension, please use CAN_MO217_IPR.
+*/
+#define CAN_MOIPR217 (CAN_MO217_IPR)
+
+/** \brief 2B3C, Message Object Control Register */
+#define CAN_MO217_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AB3Cu)
+
+/** Alias (User Manual Name) for CAN_MO217_STAT.
+* To use register names with standard convension, please use CAN_MO217_STAT.
+*/
+#define CAN_MOSTAT217 (CAN_MO217_STAT)
+
+/** \brief 2B4C, Message Object Acceptance Mask Register */
+#define CAN_MO218_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AB4Cu)
+
+/** Alias (User Manual Name) for CAN_MO218_AMR.
+* To use register names with standard convension, please use CAN_MO218_AMR.
+*/
+#define CAN_MOAMR218 (CAN_MO218_AMR)
+
+/** \brief 2B58, Message Object Arbitration Register */
+#define CAN_MO218_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AB58u)
+
+/** Alias (User Manual Name) for CAN_MO218_AR.
+* To use register names with standard convension, please use CAN_MO218_AR.
+*/
+#define CAN_MOAR218 (CAN_MO218_AR)
+
+/** \brief 2B5C, Message Object Control Register */
+#define CAN_MO218_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AB5Cu)
+
+/** Alias (User Manual Name) for CAN_MO218_CTR.
+* To use register names with standard convension, please use CAN_MO218_CTR.
+*/
+#define CAN_MOCTR218 (CAN_MO218_CTR)
+
+/** \brief 2B54, Message Object Data Register High */
+#define CAN_MO218_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AB54u)
+
+/** Alias (User Manual Name) for CAN_MO218_DATAH.
+* To use register names with standard convension, please use CAN_MO218_DATAH.
+*/
+#define CAN_MODATAH218 (CAN_MO218_DATAH)
+
+/** \brief 2B50, Message Object Data Register Low */
+#define CAN_MO218_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AB50u)
+
+/** Alias (User Manual Name) for CAN_MO218_DATAL.
+* To use register names with standard convension, please use CAN_MO218_DATAL.
+*/
+#define CAN_MODATAL218 (CAN_MO218_DATAL)
+
+/** \brief 2B40, Message Object Function Control Register */
+#define CAN_MO218_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AB40u)
+
+/** Alias (User Manual Name) for CAN_MO218_EDATA0.
+* To use register names with standard convension, please use CAN_MO218_EDATA0.
+*/
+#define CAN_EMO218DATA0 (CAN_MO218_EDATA0)
+
+/** \brief 2B44, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO218_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AB44u)
+
+/** Alias (User Manual Name) for CAN_MO218_EDATA1.
+* To use register names with standard convension, please use CAN_MO218_EDATA1.
+*/
+#define CAN_EMO218DATA1 (CAN_MO218_EDATA1)
+
+/** \brief 2B48, Message Object Interrupt Pointer Register */
+#define CAN_MO218_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AB48u)
+
+/** Alias (User Manual Name) for CAN_MO218_EDATA2.
+* To use register names with standard convension, please use CAN_MO218_EDATA2.
+*/
+#define CAN_EMO218DATA2 (CAN_MO218_EDATA2)
+
+/** \brief 2B4C, Message Object Acceptance Mask Register */
+#define CAN_MO218_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AB4Cu)
+
+/** Alias (User Manual Name) for CAN_MO218_EDATA3.
+* To use register names with standard convension, please use CAN_MO218_EDATA3.
+*/
+#define CAN_EMO218DATA3 (CAN_MO218_EDATA3)
+
+/** \brief 2B50, Message Object Data Register Low */
+#define CAN_MO218_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AB50u)
+
+/** Alias (User Manual Name) for CAN_MO218_EDATA4.
+* To use register names with standard convension, please use CAN_MO218_EDATA4.
+*/
+#define CAN_EMO218DATA4 (CAN_MO218_EDATA4)
+
+/** \brief 2B54, Message Object Data Register High */
+#define CAN_MO218_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AB54u)
+
+/** Alias (User Manual Name) for CAN_MO218_EDATA5.
+* To use register names with standard convension, please use CAN_MO218_EDATA5.
+*/
+#define CAN_EMO218DATA5 (CAN_MO218_EDATA5)
+
+/** \brief 2B58, Message Object Arbitration Register */
+#define CAN_MO218_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AB58u)
+
+/** Alias (User Manual Name) for CAN_MO218_EDATA6.
+* To use register names with standard convension, please use CAN_MO218_EDATA6.
+*/
+#define CAN_EMO218DATA6 (CAN_MO218_EDATA6)
+
+/** \brief 2B40, Message Object Function Control Register */
+#define CAN_MO218_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AB40u)
+
+/** Alias (User Manual Name) for CAN_MO218_FCR.
+* To use register names with standard convension, please use CAN_MO218_FCR.
+*/
+#define CAN_MOFCR218 (CAN_MO218_FCR)
+
+/** \brief 2B44, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO218_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AB44u)
+
+/** Alias (User Manual Name) for CAN_MO218_FGPR.
+* To use register names with standard convension, please use CAN_MO218_FGPR.
+*/
+#define CAN_MOFGPR218 (CAN_MO218_FGPR)
+
+/** \brief 2B48, Message Object Interrupt Pointer Register */
+#define CAN_MO218_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AB48u)
+
+/** Alias (User Manual Name) for CAN_MO218_IPR.
+* To use register names with standard convension, please use CAN_MO218_IPR.
+*/
+#define CAN_MOIPR218 (CAN_MO218_IPR)
+
+/** \brief 2B5C, Message Object Control Register */
+#define CAN_MO218_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AB5Cu)
+
+/** Alias (User Manual Name) for CAN_MO218_STAT.
+* To use register names with standard convension, please use CAN_MO218_STAT.
+*/
+#define CAN_MOSTAT218 (CAN_MO218_STAT)
+
+/** \brief 2B6C, Message Object Acceptance Mask Register */
+#define CAN_MO219_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AB6Cu)
+
+/** Alias (User Manual Name) for CAN_MO219_AMR.
+* To use register names with standard convension, please use CAN_MO219_AMR.
+*/
+#define CAN_MOAMR219 (CAN_MO219_AMR)
+
+/** \brief 2B78, Message Object Arbitration Register */
+#define CAN_MO219_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AB78u)
+
+/** Alias (User Manual Name) for CAN_MO219_AR.
+* To use register names with standard convension, please use CAN_MO219_AR.
+*/
+#define CAN_MOAR219 (CAN_MO219_AR)
+
+/** \brief 2B7C, Message Object Control Register */
+#define CAN_MO219_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AB7Cu)
+
+/** Alias (User Manual Name) for CAN_MO219_CTR.
+* To use register names with standard convension, please use CAN_MO219_CTR.
+*/
+#define CAN_MOCTR219 (CAN_MO219_CTR)
+
+/** \brief 2B74, Message Object Data Register High */
+#define CAN_MO219_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AB74u)
+
+/** Alias (User Manual Name) for CAN_MO219_DATAH.
+* To use register names with standard convension, please use CAN_MO219_DATAH.
+*/
+#define CAN_MODATAH219 (CAN_MO219_DATAH)
+
+/** \brief 2B70, Message Object Data Register Low */
+#define CAN_MO219_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AB70u)
+
+/** Alias (User Manual Name) for CAN_MO219_DATAL.
+* To use register names with standard convension, please use CAN_MO219_DATAL.
+*/
+#define CAN_MODATAL219 (CAN_MO219_DATAL)
+
+/** \brief 2B60, Message Object Function Control Register */
+#define CAN_MO219_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AB60u)
+
+/** Alias (User Manual Name) for CAN_MO219_EDATA0.
+* To use register names with standard convension, please use CAN_MO219_EDATA0.
+*/
+#define CAN_EMO219DATA0 (CAN_MO219_EDATA0)
+
+/** \brief 2B64, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO219_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AB64u)
+
+/** Alias (User Manual Name) for CAN_MO219_EDATA1.
+* To use register names with standard convension, please use CAN_MO219_EDATA1.
+*/
+#define CAN_EMO219DATA1 (CAN_MO219_EDATA1)
+
+/** \brief 2B68, Message Object Interrupt Pointer Register */
+#define CAN_MO219_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AB68u)
+
+/** Alias (User Manual Name) for CAN_MO219_EDATA2.
+* To use register names with standard convension, please use CAN_MO219_EDATA2.
+*/
+#define CAN_EMO219DATA2 (CAN_MO219_EDATA2)
+
+/** \brief 2B6C, Message Object Acceptance Mask Register */
+#define CAN_MO219_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AB6Cu)
+
+/** Alias (User Manual Name) for CAN_MO219_EDATA3.
+* To use register names with standard convension, please use CAN_MO219_EDATA3.
+*/
+#define CAN_EMO219DATA3 (CAN_MO219_EDATA3)
+
+/** \brief 2B70, Message Object Data Register Low */
+#define CAN_MO219_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AB70u)
+
+/** Alias (User Manual Name) for CAN_MO219_EDATA4.
+* To use register names with standard convension, please use CAN_MO219_EDATA4.
+*/
+#define CAN_EMO219DATA4 (CAN_MO219_EDATA4)
+
+/** \brief 2B74, Message Object Data Register High */
+#define CAN_MO219_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AB74u)
+
+/** Alias (User Manual Name) for CAN_MO219_EDATA5.
+* To use register names with standard convension, please use CAN_MO219_EDATA5.
+*/
+#define CAN_EMO219DATA5 (CAN_MO219_EDATA5)
+
+/** \brief 2B78, Message Object Arbitration Register */
+#define CAN_MO219_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AB78u)
+
+/** Alias (User Manual Name) for CAN_MO219_EDATA6.
+* To use register names with standard convension, please use CAN_MO219_EDATA6.
+*/
+#define CAN_EMO219DATA6 (CAN_MO219_EDATA6)
+
+/** \brief 2B60, Message Object Function Control Register */
+#define CAN_MO219_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AB60u)
+
+/** Alias (User Manual Name) for CAN_MO219_FCR.
+* To use register names with standard convension, please use CAN_MO219_FCR.
+*/
+#define CAN_MOFCR219 (CAN_MO219_FCR)
+
+/** \brief 2B64, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO219_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AB64u)
+
+/** Alias (User Manual Name) for CAN_MO219_FGPR.
+* To use register names with standard convension, please use CAN_MO219_FGPR.
+*/
+#define CAN_MOFGPR219 (CAN_MO219_FGPR)
+
+/** \brief 2B68, Message Object Interrupt Pointer Register */
+#define CAN_MO219_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AB68u)
+
+/** Alias (User Manual Name) for CAN_MO219_IPR.
+* To use register names with standard convension, please use CAN_MO219_IPR.
+*/
+#define CAN_MOIPR219 (CAN_MO219_IPR)
+
+/** \brief 2B7C, Message Object Control Register */
+#define CAN_MO219_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AB7Cu)
+
+/** Alias (User Manual Name) for CAN_MO219_STAT.
+* To use register names with standard convension, please use CAN_MO219_STAT.
+*/
+#define CAN_MOSTAT219 (CAN_MO219_STAT)
+
+/** \brief 12AC, Message Object Acceptance Mask Register */
+#define CAN_MO21_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00192ACu)
+
+/** Alias (User Manual Name) for CAN_MO21_AMR.
+* To use register names with standard convension, please use CAN_MO21_AMR.
+*/
+#define CAN_MOAMR21 (CAN_MO21_AMR)
+
+/** \brief 12B8, Message Object Arbitration Register */
+#define CAN_MO21_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00192B8u)
+
+/** Alias (User Manual Name) for CAN_MO21_AR.
+* To use register names with standard convension, please use CAN_MO21_AR.
+*/
+#define CAN_MOAR21 (CAN_MO21_AR)
+
+/** \brief 12BC, Message Object Control Register */
+#define CAN_MO21_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00192BCu)
+
+/** Alias (User Manual Name) for CAN_MO21_CTR.
+* To use register names with standard convension, please use CAN_MO21_CTR.
+*/
+#define CAN_MOCTR21 (CAN_MO21_CTR)
+
+/** \brief 12B4, Message Object Data Register High */
+#define CAN_MO21_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00192B4u)
+
+/** Alias (User Manual Name) for CAN_MO21_DATAH.
+* To use register names with standard convension, please use CAN_MO21_DATAH.
+*/
+#define CAN_MODATAH21 (CAN_MO21_DATAH)
+
+/** \brief 12B0, Message Object Data Register Low */
+#define CAN_MO21_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00192B0u)
+
+/** Alias (User Manual Name) for CAN_MO21_DATAL.
+* To use register names with standard convension, please use CAN_MO21_DATAL.
+*/
+#define CAN_MODATAL21 (CAN_MO21_DATAL)
+
+/** \brief 12A0, Message Object Function Control Register */
+#define CAN_MO21_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00192A0u)
+
+/** Alias (User Manual Name) for CAN_MO21_EDATA0.
+* To use register names with standard convension, please use CAN_MO21_EDATA0.
+*/
+#define CAN_EMO21DATA0 (CAN_MO21_EDATA0)
+
+/** \brief 12A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO21_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00192A4u)
+
+/** Alias (User Manual Name) for CAN_MO21_EDATA1.
+* To use register names with standard convension, please use CAN_MO21_EDATA1.
+*/
+#define CAN_EMO21DATA1 (CAN_MO21_EDATA1)
+
+/** \brief 12A8, Message Object Interrupt Pointer Register */
+#define CAN_MO21_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00192A8u)
+
+/** Alias (User Manual Name) for CAN_MO21_EDATA2.
+* To use register names with standard convension, please use CAN_MO21_EDATA2.
+*/
+#define CAN_EMO21DATA2 (CAN_MO21_EDATA2)
+
+/** \brief 12AC, Message Object Acceptance Mask Register */
+#define CAN_MO21_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00192ACu)
+
+/** Alias (User Manual Name) for CAN_MO21_EDATA3.
+* To use register names with standard convension, please use CAN_MO21_EDATA3.
+*/
+#define CAN_EMO21DATA3 (CAN_MO21_EDATA3)
+
+/** \brief 12B0, Message Object Data Register Low */
+#define CAN_MO21_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00192B0u)
+
+/** Alias (User Manual Name) for CAN_MO21_EDATA4.
+* To use register names with standard convension, please use CAN_MO21_EDATA4.
+*/
+#define CAN_EMO21DATA4 (CAN_MO21_EDATA4)
+
+/** \brief 12B4, Message Object Data Register High */
+#define CAN_MO21_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00192B4u)
+
+/** Alias (User Manual Name) for CAN_MO21_EDATA5.
+* To use register names with standard convension, please use CAN_MO21_EDATA5.
+*/
+#define CAN_EMO21DATA5 (CAN_MO21_EDATA5)
+
+/** \brief 12B8, Message Object Arbitration Register */
+#define CAN_MO21_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00192B8u)
+
+/** Alias (User Manual Name) for CAN_MO21_EDATA6.
+* To use register names with standard convension, please use CAN_MO21_EDATA6.
+*/
+#define CAN_EMO21DATA6 (CAN_MO21_EDATA6)
+
+/** \brief 12A0, Message Object Function Control Register */
+#define CAN_MO21_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00192A0u)
+
+/** Alias (User Manual Name) for CAN_MO21_FCR.
+* To use register names with standard convension, please use CAN_MO21_FCR.
+*/
+#define CAN_MOFCR21 (CAN_MO21_FCR)
+
+/** \brief 12A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO21_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00192A4u)
+
+/** Alias (User Manual Name) for CAN_MO21_FGPR.
+* To use register names with standard convension, please use CAN_MO21_FGPR.
+*/
+#define CAN_MOFGPR21 (CAN_MO21_FGPR)
+
+/** \brief 12A8, Message Object Interrupt Pointer Register */
+#define CAN_MO21_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00192A8u)
+
+/** Alias (User Manual Name) for CAN_MO21_IPR.
+* To use register names with standard convension, please use CAN_MO21_IPR.
+*/
+#define CAN_MOIPR21 (CAN_MO21_IPR)
+
+/** \brief 12BC, Message Object Control Register */
+#define CAN_MO21_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00192BCu)
+
+/** Alias (User Manual Name) for CAN_MO21_STAT.
+* To use register names with standard convension, please use CAN_MO21_STAT.
+*/
+#define CAN_MOSTAT21 (CAN_MO21_STAT)
+
+/** \brief 2B8C, Message Object Acceptance Mask Register */
+#define CAN_MO220_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AB8Cu)
+
+/** Alias (User Manual Name) for CAN_MO220_AMR.
+* To use register names with standard convension, please use CAN_MO220_AMR.
+*/
+#define CAN_MOAMR220 (CAN_MO220_AMR)
+
+/** \brief 2B98, Message Object Arbitration Register */
+#define CAN_MO220_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AB98u)
+
+/** Alias (User Manual Name) for CAN_MO220_AR.
+* To use register names with standard convension, please use CAN_MO220_AR.
+*/
+#define CAN_MOAR220 (CAN_MO220_AR)
+
+/** \brief 2B9C, Message Object Control Register */
+#define CAN_MO220_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AB9Cu)
+
+/** Alias (User Manual Name) for CAN_MO220_CTR.
+* To use register names with standard convension, please use CAN_MO220_CTR.
+*/
+#define CAN_MOCTR220 (CAN_MO220_CTR)
+
+/** \brief 2B94, Message Object Data Register High */
+#define CAN_MO220_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AB94u)
+
+/** Alias (User Manual Name) for CAN_MO220_DATAH.
+* To use register names with standard convension, please use CAN_MO220_DATAH.
+*/
+#define CAN_MODATAH220 (CAN_MO220_DATAH)
+
+/** \brief 2B90, Message Object Data Register Low */
+#define CAN_MO220_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AB90u)
+
+/** Alias (User Manual Name) for CAN_MO220_DATAL.
+* To use register names with standard convension, please use CAN_MO220_DATAL.
+*/
+#define CAN_MODATAL220 (CAN_MO220_DATAL)
+
+/** \brief 2B80, Message Object Function Control Register */
+#define CAN_MO220_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AB80u)
+
+/** Alias (User Manual Name) for CAN_MO220_EDATA0.
+* To use register names with standard convension, please use CAN_MO220_EDATA0.
+*/
+#define CAN_EMO220DATA0 (CAN_MO220_EDATA0)
+
+/** \brief 2B84, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO220_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AB84u)
+
+/** Alias (User Manual Name) for CAN_MO220_EDATA1.
+* To use register names with standard convension, please use CAN_MO220_EDATA1.
+*/
+#define CAN_EMO220DATA1 (CAN_MO220_EDATA1)
+
+/** \brief 2B88, Message Object Interrupt Pointer Register */
+#define CAN_MO220_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AB88u)
+
+/** Alias (User Manual Name) for CAN_MO220_EDATA2.
+* To use register names with standard convension, please use CAN_MO220_EDATA2.
+*/
+#define CAN_EMO220DATA2 (CAN_MO220_EDATA2)
+
+/** \brief 2B8C, Message Object Acceptance Mask Register */
+#define CAN_MO220_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AB8Cu)
+
+/** Alias (User Manual Name) for CAN_MO220_EDATA3.
+* To use register names with standard convension, please use CAN_MO220_EDATA3.
+*/
+#define CAN_EMO220DATA3 (CAN_MO220_EDATA3)
+
+/** \brief 2B90, Message Object Data Register Low */
+#define CAN_MO220_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AB90u)
+
+/** Alias (User Manual Name) for CAN_MO220_EDATA4.
+* To use register names with standard convension, please use CAN_MO220_EDATA4.
+*/
+#define CAN_EMO220DATA4 (CAN_MO220_EDATA4)
+
+/** \brief 2B94, Message Object Data Register High */
+#define CAN_MO220_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AB94u)
+
+/** Alias (User Manual Name) for CAN_MO220_EDATA5.
+* To use register names with standard convension, please use CAN_MO220_EDATA5.
+*/
+#define CAN_EMO220DATA5 (CAN_MO220_EDATA5)
+
+/** \brief 2B98, Message Object Arbitration Register */
+#define CAN_MO220_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AB98u)
+
+/** Alias (User Manual Name) for CAN_MO220_EDATA6.
+* To use register names with standard convension, please use CAN_MO220_EDATA6.
+*/
+#define CAN_EMO220DATA6 (CAN_MO220_EDATA6)
+
+/** \brief 2B80, Message Object Function Control Register */
+#define CAN_MO220_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AB80u)
+
+/** Alias (User Manual Name) for CAN_MO220_FCR.
+* To use register names with standard convension, please use CAN_MO220_FCR.
+*/
+#define CAN_MOFCR220 (CAN_MO220_FCR)
+
+/** \brief 2B84, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO220_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AB84u)
+
+/** Alias (User Manual Name) for CAN_MO220_FGPR.
+* To use register names with standard convension, please use CAN_MO220_FGPR.
+*/
+#define CAN_MOFGPR220 (CAN_MO220_FGPR)
+
+/** \brief 2B88, Message Object Interrupt Pointer Register */
+#define CAN_MO220_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AB88u)
+
+/** Alias (User Manual Name) for CAN_MO220_IPR.
+* To use register names with standard convension, please use CAN_MO220_IPR.
+*/
+#define CAN_MOIPR220 (CAN_MO220_IPR)
+
+/** \brief 2B9C, Message Object Control Register */
+#define CAN_MO220_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AB9Cu)
+
+/** Alias (User Manual Name) for CAN_MO220_STAT.
+* To use register names with standard convension, please use CAN_MO220_STAT.
+*/
+#define CAN_MOSTAT220 (CAN_MO220_STAT)
+
+/** \brief 2BAC, Message Object Acceptance Mask Register */
+#define CAN_MO221_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001ABACu)
+
+/** Alias (User Manual Name) for CAN_MO221_AMR.
+* To use register names with standard convension, please use CAN_MO221_AMR.
+*/
+#define CAN_MOAMR221 (CAN_MO221_AMR)
+
+/** \brief 2BB8, Message Object Arbitration Register */
+#define CAN_MO221_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001ABB8u)
+
+/** Alias (User Manual Name) for CAN_MO221_AR.
+* To use register names with standard convension, please use CAN_MO221_AR.
+*/
+#define CAN_MOAR221 (CAN_MO221_AR)
+
+/** \brief 2BBC, Message Object Control Register */
+#define CAN_MO221_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001ABBCu)
+
+/** Alias (User Manual Name) for CAN_MO221_CTR.
+* To use register names with standard convension, please use CAN_MO221_CTR.
+*/
+#define CAN_MOCTR221 (CAN_MO221_CTR)
+
+/** \brief 2BB4, Message Object Data Register High */
+#define CAN_MO221_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001ABB4u)
+
+/** Alias (User Manual Name) for CAN_MO221_DATAH.
+* To use register names with standard convension, please use CAN_MO221_DATAH.
+*/
+#define CAN_MODATAH221 (CAN_MO221_DATAH)
+
+/** \brief 2BB0, Message Object Data Register Low */
+#define CAN_MO221_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001ABB0u)
+
+/** Alias (User Manual Name) for CAN_MO221_DATAL.
+* To use register names with standard convension, please use CAN_MO221_DATAL.
+*/
+#define CAN_MODATAL221 (CAN_MO221_DATAL)
+
+/** \brief 2BA0, Message Object Function Control Register */
+#define CAN_MO221_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001ABA0u)
+
+/** Alias (User Manual Name) for CAN_MO221_EDATA0.
+* To use register names with standard convension, please use CAN_MO221_EDATA0.
+*/
+#define CAN_EMO221DATA0 (CAN_MO221_EDATA0)
+
+/** \brief 2BA4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO221_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001ABA4u)
+
+/** Alias (User Manual Name) for CAN_MO221_EDATA1.
+* To use register names with standard convension, please use CAN_MO221_EDATA1.
+*/
+#define CAN_EMO221DATA1 (CAN_MO221_EDATA1)
+
+/** \brief 2BA8, Message Object Interrupt Pointer Register */
+#define CAN_MO221_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001ABA8u)
+
+/** Alias (User Manual Name) for CAN_MO221_EDATA2.
+* To use register names with standard convension, please use CAN_MO221_EDATA2.
+*/
+#define CAN_EMO221DATA2 (CAN_MO221_EDATA2)
+
+/** \brief 2BAC, Message Object Acceptance Mask Register */
+#define CAN_MO221_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001ABACu)
+
+/** Alias (User Manual Name) for CAN_MO221_EDATA3.
+* To use register names with standard convension, please use CAN_MO221_EDATA3.
+*/
+#define CAN_EMO221DATA3 (CAN_MO221_EDATA3)
+
+/** \brief 2BB0, Message Object Data Register Low */
+#define CAN_MO221_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001ABB0u)
+
+/** Alias (User Manual Name) for CAN_MO221_EDATA4.
+* To use register names with standard convension, please use CAN_MO221_EDATA4.
+*/
+#define CAN_EMO221DATA4 (CAN_MO221_EDATA4)
+
+/** \brief 2BB4, Message Object Data Register High */
+#define CAN_MO221_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001ABB4u)
+
+/** Alias (User Manual Name) for CAN_MO221_EDATA5.
+* To use register names with standard convension, please use CAN_MO221_EDATA5.
+*/
+#define CAN_EMO221DATA5 (CAN_MO221_EDATA5)
+
+/** \brief 2BB8, Message Object Arbitration Register */
+#define CAN_MO221_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001ABB8u)
+
+/** Alias (User Manual Name) for CAN_MO221_EDATA6.
+* To use register names with standard convension, please use CAN_MO221_EDATA6.
+*/
+#define CAN_EMO221DATA6 (CAN_MO221_EDATA6)
+
+/** \brief 2BA0, Message Object Function Control Register */
+#define CAN_MO221_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001ABA0u)
+
+/** Alias (User Manual Name) for CAN_MO221_FCR.
+* To use register names with standard convension, please use CAN_MO221_FCR.
+*/
+#define CAN_MOFCR221 (CAN_MO221_FCR)
+
+/** \brief 2BA4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO221_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001ABA4u)
+
+/** Alias (User Manual Name) for CAN_MO221_FGPR.
+* To use register names with standard convension, please use CAN_MO221_FGPR.
+*/
+#define CAN_MOFGPR221 (CAN_MO221_FGPR)
+
+/** \brief 2BA8, Message Object Interrupt Pointer Register */
+#define CAN_MO221_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001ABA8u)
+
+/** Alias (User Manual Name) for CAN_MO221_IPR.
+* To use register names with standard convension, please use CAN_MO221_IPR.
+*/
+#define CAN_MOIPR221 (CAN_MO221_IPR)
+
+/** \brief 2BBC, Message Object Control Register */
+#define CAN_MO221_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001ABBCu)
+
+/** Alias (User Manual Name) for CAN_MO221_STAT.
+* To use register names with standard convension, please use CAN_MO221_STAT.
+*/
+#define CAN_MOSTAT221 (CAN_MO221_STAT)
+
+/** \brief 2BCC, Message Object Acceptance Mask Register */
+#define CAN_MO222_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001ABCCu)
+
+/** Alias (User Manual Name) for CAN_MO222_AMR.
+* To use register names with standard convension, please use CAN_MO222_AMR.
+*/
+#define CAN_MOAMR222 (CAN_MO222_AMR)
+
+/** \brief 2BD8, Message Object Arbitration Register */
+#define CAN_MO222_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001ABD8u)
+
+/** Alias (User Manual Name) for CAN_MO222_AR.
+* To use register names with standard convension, please use CAN_MO222_AR.
+*/
+#define CAN_MOAR222 (CAN_MO222_AR)
+
+/** \brief 2BDC, Message Object Control Register */
+#define CAN_MO222_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001ABDCu)
+
+/** Alias (User Manual Name) for CAN_MO222_CTR.
+* To use register names with standard convension, please use CAN_MO222_CTR.
+*/
+#define CAN_MOCTR222 (CAN_MO222_CTR)
+
+/** \brief 2BD4, Message Object Data Register High */
+#define CAN_MO222_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001ABD4u)
+
+/** Alias (User Manual Name) for CAN_MO222_DATAH.
+* To use register names with standard convension, please use CAN_MO222_DATAH.
+*/
+#define CAN_MODATAH222 (CAN_MO222_DATAH)
+
+/** \brief 2BD0, Message Object Data Register Low */
+#define CAN_MO222_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001ABD0u)
+
+/** Alias (User Manual Name) for CAN_MO222_DATAL.
+* To use register names with standard convension, please use CAN_MO222_DATAL.
+*/
+#define CAN_MODATAL222 (CAN_MO222_DATAL)
+
+/** \brief 2BC0, Message Object Function Control Register */
+#define CAN_MO222_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001ABC0u)
+
+/** Alias (User Manual Name) for CAN_MO222_EDATA0.
+* To use register names with standard convension, please use CAN_MO222_EDATA0.
+*/
+#define CAN_EMO222DATA0 (CAN_MO222_EDATA0)
+
+/** \brief 2BC4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO222_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001ABC4u)
+
+/** Alias (User Manual Name) for CAN_MO222_EDATA1.
+* To use register names with standard convension, please use CAN_MO222_EDATA1.
+*/
+#define CAN_EMO222DATA1 (CAN_MO222_EDATA1)
+
+/** \brief 2BC8, Message Object Interrupt Pointer Register */
+#define CAN_MO222_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001ABC8u)
+
+/** Alias (User Manual Name) for CAN_MO222_EDATA2.
+* To use register names with standard convension, please use CAN_MO222_EDATA2.
+*/
+#define CAN_EMO222DATA2 (CAN_MO222_EDATA2)
+
+/** \brief 2BCC, Message Object Acceptance Mask Register */
+#define CAN_MO222_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001ABCCu)
+
+/** Alias (User Manual Name) for CAN_MO222_EDATA3.
+* To use register names with standard convension, please use CAN_MO222_EDATA3.
+*/
+#define CAN_EMO222DATA3 (CAN_MO222_EDATA3)
+
+/** \brief 2BD0, Message Object Data Register Low */
+#define CAN_MO222_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001ABD0u)
+
+/** Alias (User Manual Name) for CAN_MO222_EDATA4.
+* To use register names with standard convension, please use CAN_MO222_EDATA4.
+*/
+#define CAN_EMO222DATA4 (CAN_MO222_EDATA4)
+
+/** \brief 2BD4, Message Object Data Register High */
+#define CAN_MO222_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001ABD4u)
+
+/** Alias (User Manual Name) for CAN_MO222_EDATA5.
+* To use register names with standard convension, please use CAN_MO222_EDATA5.
+*/
+#define CAN_EMO222DATA5 (CAN_MO222_EDATA5)
+
+/** \brief 2BD8, Message Object Arbitration Register */
+#define CAN_MO222_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001ABD8u)
+
+/** Alias (User Manual Name) for CAN_MO222_EDATA6.
+* To use register names with standard convension, please use CAN_MO222_EDATA6.
+*/
+#define CAN_EMO222DATA6 (CAN_MO222_EDATA6)
+
+/** \brief 2BC0, Message Object Function Control Register */
+#define CAN_MO222_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001ABC0u)
+
+/** Alias (User Manual Name) for CAN_MO222_FCR.
+* To use register names with standard convension, please use CAN_MO222_FCR.
+*/
+#define CAN_MOFCR222 (CAN_MO222_FCR)
+
+/** \brief 2BC4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO222_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001ABC4u)
+
+/** Alias (User Manual Name) for CAN_MO222_FGPR.
+* To use register names with standard convension, please use CAN_MO222_FGPR.
+*/
+#define CAN_MOFGPR222 (CAN_MO222_FGPR)
+
+/** \brief 2BC8, Message Object Interrupt Pointer Register */
+#define CAN_MO222_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001ABC8u)
+
+/** Alias (User Manual Name) for CAN_MO222_IPR.
+* To use register names with standard convension, please use CAN_MO222_IPR.
+*/
+#define CAN_MOIPR222 (CAN_MO222_IPR)
+
+/** \brief 2BDC, Message Object Control Register */
+#define CAN_MO222_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001ABDCu)
+
+/** Alias (User Manual Name) for CAN_MO222_STAT.
+* To use register names with standard convension, please use CAN_MO222_STAT.
+*/
+#define CAN_MOSTAT222 (CAN_MO222_STAT)
+
+/** \brief 2BEC, Message Object Acceptance Mask Register */
+#define CAN_MO223_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001ABECu)
+
+/** Alias (User Manual Name) for CAN_MO223_AMR.
+* To use register names with standard convension, please use CAN_MO223_AMR.
+*/
+#define CAN_MOAMR223 (CAN_MO223_AMR)
+
+/** \brief 2BF8, Message Object Arbitration Register */
+#define CAN_MO223_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001ABF8u)
+
+/** Alias (User Manual Name) for CAN_MO223_AR.
+* To use register names with standard convension, please use CAN_MO223_AR.
+*/
+#define CAN_MOAR223 (CAN_MO223_AR)
+
+/** \brief 2BFC, Message Object Control Register */
+#define CAN_MO223_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001ABFCu)
+
+/** Alias (User Manual Name) for CAN_MO223_CTR.
+* To use register names with standard convension, please use CAN_MO223_CTR.
+*/
+#define CAN_MOCTR223 (CAN_MO223_CTR)
+
+/** \brief 2BF4, Message Object Data Register High */
+#define CAN_MO223_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001ABF4u)
+
+/** Alias (User Manual Name) for CAN_MO223_DATAH.
+* To use register names with standard convension, please use CAN_MO223_DATAH.
+*/
+#define CAN_MODATAH223 (CAN_MO223_DATAH)
+
+/** \brief 2BF0, Message Object Data Register Low */
+#define CAN_MO223_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001ABF0u)
+
+/** Alias (User Manual Name) for CAN_MO223_DATAL.
+* To use register names with standard convension, please use CAN_MO223_DATAL.
+*/
+#define CAN_MODATAL223 (CAN_MO223_DATAL)
+
+/** \brief 2BE0, Message Object Function Control Register */
+#define CAN_MO223_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001ABE0u)
+
+/** Alias (User Manual Name) for CAN_MO223_EDATA0.
+* To use register names with standard convension, please use CAN_MO223_EDATA0.
+*/
+#define CAN_EMO223DATA0 (CAN_MO223_EDATA0)
+
+/** \brief 2BE4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO223_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001ABE4u)
+
+/** Alias (User Manual Name) for CAN_MO223_EDATA1.
+* To use register names with standard convension, please use CAN_MO223_EDATA1.
+*/
+#define CAN_EMO223DATA1 (CAN_MO223_EDATA1)
+
+/** \brief 2BE8, Message Object Interrupt Pointer Register */
+#define CAN_MO223_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001ABE8u)
+
+/** Alias (User Manual Name) for CAN_MO223_EDATA2.
+* To use register names with standard convension, please use CAN_MO223_EDATA2.
+*/
+#define CAN_EMO223DATA2 (CAN_MO223_EDATA2)
+
+/** \brief 2BEC, Message Object Acceptance Mask Register */
+#define CAN_MO223_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001ABECu)
+
+/** Alias (User Manual Name) for CAN_MO223_EDATA3.
+* To use register names with standard convension, please use CAN_MO223_EDATA3.
+*/
+#define CAN_EMO223DATA3 (CAN_MO223_EDATA3)
+
+/** \brief 2BF0, Message Object Data Register Low */
+#define CAN_MO223_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001ABF0u)
+
+/** Alias (User Manual Name) for CAN_MO223_EDATA4.
+* To use register names with standard convension, please use CAN_MO223_EDATA4.
+*/
+#define CAN_EMO223DATA4 (CAN_MO223_EDATA4)
+
+/** \brief 2BF4, Message Object Data Register High */
+#define CAN_MO223_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001ABF4u)
+
+/** Alias (User Manual Name) for CAN_MO223_EDATA5.
+* To use register names with standard convension, please use CAN_MO223_EDATA5.
+*/
+#define CAN_EMO223DATA5 (CAN_MO223_EDATA5)
+
+/** \brief 2BF8, Message Object Arbitration Register */
+#define CAN_MO223_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001ABF8u)
+
+/** Alias (User Manual Name) for CAN_MO223_EDATA6.
+* To use register names with standard convension, please use CAN_MO223_EDATA6.
+*/
+#define CAN_EMO223DATA6 (CAN_MO223_EDATA6)
+
+/** \brief 2BE0, Message Object Function Control Register */
+#define CAN_MO223_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001ABE0u)
+
+/** Alias (User Manual Name) for CAN_MO223_FCR.
+* To use register names with standard convension, please use CAN_MO223_FCR.
+*/
+#define CAN_MOFCR223 (CAN_MO223_FCR)
+
+/** \brief 2BE4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO223_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001ABE4u)
+
+/** Alias (User Manual Name) for CAN_MO223_FGPR.
+* To use register names with standard convension, please use CAN_MO223_FGPR.
+*/
+#define CAN_MOFGPR223 (CAN_MO223_FGPR)
+
+/** \brief 2BE8, Message Object Interrupt Pointer Register */
+#define CAN_MO223_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001ABE8u)
+
+/** Alias (User Manual Name) for CAN_MO223_IPR.
+* To use register names with standard convension, please use CAN_MO223_IPR.
+*/
+#define CAN_MOIPR223 (CAN_MO223_IPR)
+
+/** \brief 2BFC, Message Object Control Register */
+#define CAN_MO223_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001ABFCu)
+
+/** Alias (User Manual Name) for CAN_MO223_STAT.
+* To use register names with standard convension, please use CAN_MO223_STAT.
+*/
+#define CAN_MOSTAT223 (CAN_MO223_STAT)
+
+/** \brief 2C0C, Message Object Acceptance Mask Register */
+#define CAN_MO224_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AC0Cu)
+
+/** Alias (User Manual Name) for CAN_MO224_AMR.
+* To use register names with standard convension, please use CAN_MO224_AMR.
+*/
+#define CAN_MOAMR224 (CAN_MO224_AMR)
+
+/** \brief 2C18, Message Object Arbitration Register */
+#define CAN_MO224_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AC18u)
+
+/** Alias (User Manual Name) for CAN_MO224_AR.
+* To use register names with standard convension, please use CAN_MO224_AR.
+*/
+#define CAN_MOAR224 (CAN_MO224_AR)
+
+/** \brief 2C1C, Message Object Control Register */
+#define CAN_MO224_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AC1Cu)
+
+/** Alias (User Manual Name) for CAN_MO224_CTR.
+* To use register names with standard convension, please use CAN_MO224_CTR.
+*/
+#define CAN_MOCTR224 (CAN_MO224_CTR)
+
+/** \brief 2C14, Message Object Data Register High */
+#define CAN_MO224_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AC14u)
+
+/** Alias (User Manual Name) for CAN_MO224_DATAH.
+* To use register names with standard convension, please use CAN_MO224_DATAH.
+*/
+#define CAN_MODATAH224 (CAN_MO224_DATAH)
+
+/** \brief 2C10, Message Object Data Register Low */
+#define CAN_MO224_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AC10u)
+
+/** Alias (User Manual Name) for CAN_MO224_DATAL.
+* To use register names with standard convension, please use CAN_MO224_DATAL.
+*/
+#define CAN_MODATAL224 (CAN_MO224_DATAL)
+
+/** \brief 2C00, Message Object Function Control Register */
+#define CAN_MO224_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AC00u)
+
+/** Alias (User Manual Name) for CAN_MO224_EDATA0.
+* To use register names with standard convension, please use CAN_MO224_EDATA0.
+*/
+#define CAN_EMO224DATA0 (CAN_MO224_EDATA0)
+
+/** \brief 2C04, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO224_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AC04u)
+
+/** Alias (User Manual Name) for CAN_MO224_EDATA1.
+* To use register names with standard convension, please use CAN_MO224_EDATA1.
+*/
+#define CAN_EMO224DATA1 (CAN_MO224_EDATA1)
+
+/** \brief 2C08, Message Object Interrupt Pointer Register */
+#define CAN_MO224_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AC08u)
+
+/** Alias (User Manual Name) for CAN_MO224_EDATA2.
+* To use register names with standard convension, please use CAN_MO224_EDATA2.
+*/
+#define CAN_EMO224DATA2 (CAN_MO224_EDATA2)
+
+/** \brief 2C0C, Message Object Acceptance Mask Register */
+#define CAN_MO224_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AC0Cu)
+
+/** Alias (User Manual Name) for CAN_MO224_EDATA3.
+* To use register names with standard convension, please use CAN_MO224_EDATA3.
+*/
+#define CAN_EMO224DATA3 (CAN_MO224_EDATA3)
+
+/** \brief 2C10, Message Object Data Register Low */
+#define CAN_MO224_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AC10u)
+
+/** Alias (User Manual Name) for CAN_MO224_EDATA4.
+* To use register names with standard convension, please use CAN_MO224_EDATA4.
+*/
+#define CAN_EMO224DATA4 (CAN_MO224_EDATA4)
+
+/** \brief 2C14, Message Object Data Register High */
+#define CAN_MO224_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AC14u)
+
+/** Alias (User Manual Name) for CAN_MO224_EDATA5.
+* To use register names with standard convension, please use CAN_MO224_EDATA5.
+*/
+#define CAN_EMO224DATA5 (CAN_MO224_EDATA5)
+
+/** \brief 2C18, Message Object Arbitration Register */
+#define CAN_MO224_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AC18u)
+
+/** Alias (User Manual Name) for CAN_MO224_EDATA6.
+* To use register names with standard convension, please use CAN_MO224_EDATA6.
+*/
+#define CAN_EMO224DATA6 (CAN_MO224_EDATA6)
+
+/** \brief 2C00, Message Object Function Control Register */
+#define CAN_MO224_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AC00u)
+
+/** Alias (User Manual Name) for CAN_MO224_FCR.
+* To use register names with standard convension, please use CAN_MO224_FCR.
+*/
+#define CAN_MOFCR224 (CAN_MO224_FCR)
+
+/** \brief 2C04, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO224_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AC04u)
+
+/** Alias (User Manual Name) for CAN_MO224_FGPR.
+* To use register names with standard convension, please use CAN_MO224_FGPR.
+*/
+#define CAN_MOFGPR224 (CAN_MO224_FGPR)
+
+/** \brief 2C08, Message Object Interrupt Pointer Register */
+#define CAN_MO224_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AC08u)
+
+/** Alias (User Manual Name) for CAN_MO224_IPR.
+* To use register names with standard convension, please use CAN_MO224_IPR.
+*/
+#define CAN_MOIPR224 (CAN_MO224_IPR)
+
+/** \brief 2C1C, Message Object Control Register */
+#define CAN_MO224_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AC1Cu)
+
+/** Alias (User Manual Name) for CAN_MO224_STAT.
+* To use register names with standard convension, please use CAN_MO224_STAT.
+*/
+#define CAN_MOSTAT224 (CAN_MO224_STAT)
+
+/** \brief 2C2C, Message Object Acceptance Mask Register */
+#define CAN_MO225_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AC2Cu)
+
+/** Alias (User Manual Name) for CAN_MO225_AMR.
+* To use register names with standard convension, please use CAN_MO225_AMR.
+*/
+#define CAN_MOAMR225 (CAN_MO225_AMR)
+
+/** \brief 2C38, Message Object Arbitration Register */
+#define CAN_MO225_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AC38u)
+
+/** Alias (User Manual Name) for CAN_MO225_AR.
+* To use register names with standard convension, please use CAN_MO225_AR.
+*/
+#define CAN_MOAR225 (CAN_MO225_AR)
+
+/** \brief 2C3C, Message Object Control Register */
+#define CAN_MO225_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AC3Cu)
+
+/** Alias (User Manual Name) for CAN_MO225_CTR.
+* To use register names with standard convension, please use CAN_MO225_CTR.
+*/
+#define CAN_MOCTR225 (CAN_MO225_CTR)
+
+/** \brief 2C34, Message Object Data Register High */
+#define CAN_MO225_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AC34u)
+
+/** Alias (User Manual Name) for CAN_MO225_DATAH.
+* To use register names with standard convension, please use CAN_MO225_DATAH.
+*/
+#define CAN_MODATAH225 (CAN_MO225_DATAH)
+
+/** \brief 2C30, Message Object Data Register Low */
+#define CAN_MO225_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AC30u)
+
+/** Alias (User Manual Name) for CAN_MO225_DATAL.
+* To use register names with standard convension, please use CAN_MO225_DATAL.
+*/
+#define CAN_MODATAL225 (CAN_MO225_DATAL)
+
+/** \brief 2C20, Message Object Function Control Register */
+#define CAN_MO225_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AC20u)
+
+/** Alias (User Manual Name) for CAN_MO225_EDATA0.
+* To use register names with standard convension, please use CAN_MO225_EDATA0.
+*/
+#define CAN_EMO225DATA0 (CAN_MO225_EDATA0)
+
+/** \brief 2C24, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO225_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AC24u)
+
+/** Alias (User Manual Name) for CAN_MO225_EDATA1.
+* To use register names with standard convension, please use CAN_MO225_EDATA1.
+*/
+#define CAN_EMO225DATA1 (CAN_MO225_EDATA1)
+
+/** \brief 2C28, Message Object Interrupt Pointer Register */
+#define CAN_MO225_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AC28u)
+
+/** Alias (User Manual Name) for CAN_MO225_EDATA2.
+* To use register names with standard convension, please use CAN_MO225_EDATA2.
+*/
+#define CAN_EMO225DATA2 (CAN_MO225_EDATA2)
+
+/** \brief 2C2C, Message Object Acceptance Mask Register */
+#define CAN_MO225_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AC2Cu)
+
+/** Alias (User Manual Name) for CAN_MO225_EDATA3.
+* To use register names with standard convension, please use CAN_MO225_EDATA3.
+*/
+#define CAN_EMO225DATA3 (CAN_MO225_EDATA3)
+
+/** \brief 2C30, Message Object Data Register Low */
+#define CAN_MO225_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AC30u)
+
+/** Alias (User Manual Name) for CAN_MO225_EDATA4.
+* To use register names with standard convension, please use CAN_MO225_EDATA4.
+*/
+#define CAN_EMO225DATA4 (CAN_MO225_EDATA4)
+
+/** \brief 2C34, Message Object Data Register High */
+#define CAN_MO225_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AC34u)
+
+/** Alias (User Manual Name) for CAN_MO225_EDATA5.
+* To use register names with standard convension, please use CAN_MO225_EDATA5.
+*/
+#define CAN_EMO225DATA5 (CAN_MO225_EDATA5)
+
+/** \brief 2C38, Message Object Arbitration Register */
+#define CAN_MO225_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AC38u)
+
+/** Alias (User Manual Name) for CAN_MO225_EDATA6.
+* To use register names with standard convension, please use CAN_MO225_EDATA6.
+*/
+#define CAN_EMO225DATA6 (CAN_MO225_EDATA6)
+
+/** \brief 2C20, Message Object Function Control Register */
+#define CAN_MO225_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AC20u)
+
+/** Alias (User Manual Name) for CAN_MO225_FCR.
+* To use register names with standard convension, please use CAN_MO225_FCR.
+*/
+#define CAN_MOFCR225 (CAN_MO225_FCR)
+
+/** \brief 2C24, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO225_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AC24u)
+
+/** Alias (User Manual Name) for CAN_MO225_FGPR.
+* To use register names with standard convension, please use CAN_MO225_FGPR.
+*/
+#define CAN_MOFGPR225 (CAN_MO225_FGPR)
+
+/** \brief 2C28, Message Object Interrupt Pointer Register */
+#define CAN_MO225_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AC28u)
+
+/** Alias (User Manual Name) for CAN_MO225_IPR.
+* To use register names with standard convension, please use CAN_MO225_IPR.
+*/
+#define CAN_MOIPR225 (CAN_MO225_IPR)
+
+/** \brief 2C3C, Message Object Control Register */
+#define CAN_MO225_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AC3Cu)
+
+/** Alias (User Manual Name) for CAN_MO225_STAT.
+* To use register names with standard convension, please use CAN_MO225_STAT.
+*/
+#define CAN_MOSTAT225 (CAN_MO225_STAT)
+
+/** \brief 2C4C, Message Object Acceptance Mask Register */
+#define CAN_MO226_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AC4Cu)
+
+/** Alias (User Manual Name) for CAN_MO226_AMR.
+* To use register names with standard convension, please use CAN_MO226_AMR.
+*/
+#define CAN_MOAMR226 (CAN_MO226_AMR)
+
+/** \brief 2C58, Message Object Arbitration Register */
+#define CAN_MO226_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AC58u)
+
+/** Alias (User Manual Name) for CAN_MO226_AR.
+* To use register names with standard convension, please use CAN_MO226_AR.
+*/
+#define CAN_MOAR226 (CAN_MO226_AR)
+
+/** \brief 2C5C, Message Object Control Register */
+#define CAN_MO226_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AC5Cu)
+
+/** Alias (User Manual Name) for CAN_MO226_CTR.
+* To use register names with standard convension, please use CAN_MO226_CTR.
+*/
+#define CAN_MOCTR226 (CAN_MO226_CTR)
+
+/** \brief 2C54, Message Object Data Register High */
+#define CAN_MO226_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AC54u)
+
+/** Alias (User Manual Name) for CAN_MO226_DATAH.
+* To use register names with standard convension, please use CAN_MO226_DATAH.
+*/
+#define CAN_MODATAH226 (CAN_MO226_DATAH)
+
+/** \brief 2C50, Message Object Data Register Low */
+#define CAN_MO226_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AC50u)
+
+/** Alias (User Manual Name) for CAN_MO226_DATAL.
+* To use register names with standard convension, please use CAN_MO226_DATAL.
+*/
+#define CAN_MODATAL226 (CAN_MO226_DATAL)
+
+/** \brief 2C40, Message Object Function Control Register */
+#define CAN_MO226_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AC40u)
+
+/** Alias (User Manual Name) for CAN_MO226_EDATA0.
+* To use register names with standard convension, please use CAN_MO226_EDATA0.
+*/
+#define CAN_EMO226DATA0 (CAN_MO226_EDATA0)
+
+/** \brief 2C44, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO226_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AC44u)
+
+/** Alias (User Manual Name) for CAN_MO226_EDATA1.
+* To use register names with standard convension, please use CAN_MO226_EDATA1.
+*/
+#define CAN_EMO226DATA1 (CAN_MO226_EDATA1)
+
+/** \brief 2C48, Message Object Interrupt Pointer Register */
+#define CAN_MO226_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AC48u)
+
+/** Alias (User Manual Name) for CAN_MO226_EDATA2.
+* To use register names with standard convension, please use CAN_MO226_EDATA2.
+*/
+#define CAN_EMO226DATA2 (CAN_MO226_EDATA2)
+
+/** \brief 2C4C, Message Object Acceptance Mask Register */
+#define CAN_MO226_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AC4Cu)
+
+/** Alias (User Manual Name) for CAN_MO226_EDATA3.
+* To use register names with standard convension, please use CAN_MO226_EDATA3.
+*/
+#define CAN_EMO226DATA3 (CAN_MO226_EDATA3)
+
+/** \brief 2C50, Message Object Data Register Low */
+#define CAN_MO226_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AC50u)
+
+/** Alias (User Manual Name) for CAN_MO226_EDATA4.
+* To use register names with standard convension, please use CAN_MO226_EDATA4.
+*/
+#define CAN_EMO226DATA4 (CAN_MO226_EDATA4)
+
+/** \brief 2C54, Message Object Data Register High */
+#define CAN_MO226_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AC54u)
+
+/** Alias (User Manual Name) for CAN_MO226_EDATA5.
+* To use register names with standard convension, please use CAN_MO226_EDATA5.
+*/
+#define CAN_EMO226DATA5 (CAN_MO226_EDATA5)
+
+/** \brief 2C58, Message Object Arbitration Register */
+#define CAN_MO226_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AC58u)
+
+/** Alias (User Manual Name) for CAN_MO226_EDATA6.
+* To use register names with standard convension, please use CAN_MO226_EDATA6.
+*/
+#define CAN_EMO226DATA6 (CAN_MO226_EDATA6)
+
+/** \brief 2C40, Message Object Function Control Register */
+#define CAN_MO226_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AC40u)
+
+/** Alias (User Manual Name) for CAN_MO226_FCR.
+* To use register names with standard convension, please use CAN_MO226_FCR.
+*/
+#define CAN_MOFCR226 (CAN_MO226_FCR)
+
+/** \brief 2C44, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO226_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AC44u)
+
+/** Alias (User Manual Name) for CAN_MO226_FGPR.
+* To use register names with standard convension, please use CAN_MO226_FGPR.
+*/
+#define CAN_MOFGPR226 (CAN_MO226_FGPR)
+
+/** \brief 2C48, Message Object Interrupt Pointer Register */
+#define CAN_MO226_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AC48u)
+
+/** Alias (User Manual Name) for CAN_MO226_IPR.
+* To use register names with standard convension, please use CAN_MO226_IPR.
+*/
+#define CAN_MOIPR226 (CAN_MO226_IPR)
+
+/** \brief 2C5C, Message Object Control Register */
+#define CAN_MO226_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AC5Cu)
+
+/** Alias (User Manual Name) for CAN_MO226_STAT.
+* To use register names with standard convension, please use CAN_MO226_STAT.
+*/
+#define CAN_MOSTAT226 (CAN_MO226_STAT)
+
+/** \brief 2C6C, Message Object Acceptance Mask Register */
+#define CAN_MO227_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AC6Cu)
+
+/** Alias (User Manual Name) for CAN_MO227_AMR.
+* To use register names with standard convension, please use CAN_MO227_AMR.
+*/
+#define CAN_MOAMR227 (CAN_MO227_AMR)
+
+/** \brief 2C78, Message Object Arbitration Register */
+#define CAN_MO227_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AC78u)
+
+/** Alias (User Manual Name) for CAN_MO227_AR.
+* To use register names with standard convension, please use CAN_MO227_AR.
+*/
+#define CAN_MOAR227 (CAN_MO227_AR)
+
+/** \brief 2C7C, Message Object Control Register */
+#define CAN_MO227_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AC7Cu)
+
+/** Alias (User Manual Name) for CAN_MO227_CTR.
+* To use register names with standard convension, please use CAN_MO227_CTR.
+*/
+#define CAN_MOCTR227 (CAN_MO227_CTR)
+
+/** \brief 2C74, Message Object Data Register High */
+#define CAN_MO227_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AC74u)
+
+/** Alias (User Manual Name) for CAN_MO227_DATAH.
+* To use register names with standard convension, please use CAN_MO227_DATAH.
+*/
+#define CAN_MODATAH227 (CAN_MO227_DATAH)
+
+/** \brief 2C70, Message Object Data Register Low */
+#define CAN_MO227_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AC70u)
+
+/** Alias (User Manual Name) for CAN_MO227_DATAL.
+* To use register names with standard convension, please use CAN_MO227_DATAL.
+*/
+#define CAN_MODATAL227 (CAN_MO227_DATAL)
+
+/** \brief 2C60, Message Object Function Control Register */
+#define CAN_MO227_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AC60u)
+
+/** Alias (User Manual Name) for CAN_MO227_EDATA0.
+* To use register names with standard convension, please use CAN_MO227_EDATA0.
+*/
+#define CAN_EMO227DATA0 (CAN_MO227_EDATA0)
+
+/** \brief 2C64, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO227_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AC64u)
+
+/** Alias (User Manual Name) for CAN_MO227_EDATA1.
+* To use register names with standard convension, please use CAN_MO227_EDATA1.
+*/
+#define CAN_EMO227DATA1 (CAN_MO227_EDATA1)
+
+/** \brief 2C68, Message Object Interrupt Pointer Register */
+#define CAN_MO227_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AC68u)
+
+/** Alias (User Manual Name) for CAN_MO227_EDATA2.
+* To use register names with standard convension, please use CAN_MO227_EDATA2.
+*/
+#define CAN_EMO227DATA2 (CAN_MO227_EDATA2)
+
+/** \brief 2C6C, Message Object Acceptance Mask Register */
+#define CAN_MO227_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AC6Cu)
+
+/** Alias (User Manual Name) for CAN_MO227_EDATA3.
+* To use register names with standard convension, please use CAN_MO227_EDATA3.
+*/
+#define CAN_EMO227DATA3 (CAN_MO227_EDATA3)
+
+/** \brief 2C70, Message Object Data Register Low */
+#define CAN_MO227_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AC70u)
+
+/** Alias (User Manual Name) for CAN_MO227_EDATA4.
+* To use register names with standard convension, please use CAN_MO227_EDATA4.
+*/
+#define CAN_EMO227DATA4 (CAN_MO227_EDATA4)
+
+/** \brief 2C74, Message Object Data Register High */
+#define CAN_MO227_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AC74u)
+
+/** Alias (User Manual Name) for CAN_MO227_EDATA5.
+* To use register names with standard convension, please use CAN_MO227_EDATA5.
+*/
+#define CAN_EMO227DATA5 (CAN_MO227_EDATA5)
+
+/** \brief 2C78, Message Object Arbitration Register */
+#define CAN_MO227_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AC78u)
+
+/** Alias (User Manual Name) for CAN_MO227_EDATA6.
+* To use register names with standard convension, please use CAN_MO227_EDATA6.
+*/
+#define CAN_EMO227DATA6 (CAN_MO227_EDATA6)
+
+/** \brief 2C60, Message Object Function Control Register */
+#define CAN_MO227_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AC60u)
+
+/** Alias (User Manual Name) for CAN_MO227_FCR.
+* To use register names with standard convension, please use CAN_MO227_FCR.
+*/
+#define CAN_MOFCR227 (CAN_MO227_FCR)
+
+/** \brief 2C64, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO227_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AC64u)
+
+/** Alias (User Manual Name) for CAN_MO227_FGPR.
+* To use register names with standard convension, please use CAN_MO227_FGPR.
+*/
+#define CAN_MOFGPR227 (CAN_MO227_FGPR)
+
+/** \brief 2C68, Message Object Interrupt Pointer Register */
+#define CAN_MO227_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AC68u)
+
+/** Alias (User Manual Name) for CAN_MO227_IPR.
+* To use register names with standard convension, please use CAN_MO227_IPR.
+*/
+#define CAN_MOIPR227 (CAN_MO227_IPR)
+
+/** \brief 2C7C, Message Object Control Register */
+#define CAN_MO227_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AC7Cu)
+
+/** Alias (User Manual Name) for CAN_MO227_STAT.
+* To use register names with standard convension, please use CAN_MO227_STAT.
+*/
+#define CAN_MOSTAT227 (CAN_MO227_STAT)
+
+/** \brief 2C8C, Message Object Acceptance Mask Register */
+#define CAN_MO228_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AC8Cu)
+
+/** Alias (User Manual Name) for CAN_MO228_AMR.
+* To use register names with standard convension, please use CAN_MO228_AMR.
+*/
+#define CAN_MOAMR228 (CAN_MO228_AMR)
+
+/** \brief 2C98, Message Object Arbitration Register */
+#define CAN_MO228_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AC98u)
+
+/** Alias (User Manual Name) for CAN_MO228_AR.
+* To use register names with standard convension, please use CAN_MO228_AR.
+*/
+#define CAN_MOAR228 (CAN_MO228_AR)
+
+/** \brief 2C9C, Message Object Control Register */
+#define CAN_MO228_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AC9Cu)
+
+/** Alias (User Manual Name) for CAN_MO228_CTR.
+* To use register names with standard convension, please use CAN_MO228_CTR.
+*/
+#define CAN_MOCTR228 (CAN_MO228_CTR)
+
+/** \brief 2C94, Message Object Data Register High */
+#define CAN_MO228_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AC94u)
+
+/** Alias (User Manual Name) for CAN_MO228_DATAH.
+* To use register names with standard convension, please use CAN_MO228_DATAH.
+*/
+#define CAN_MODATAH228 (CAN_MO228_DATAH)
+
+/** \brief 2C90, Message Object Data Register Low */
+#define CAN_MO228_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AC90u)
+
+/** Alias (User Manual Name) for CAN_MO228_DATAL.
+* To use register names with standard convension, please use CAN_MO228_DATAL.
+*/
+#define CAN_MODATAL228 (CAN_MO228_DATAL)
+
+/** \brief 2C80, Message Object Function Control Register */
+#define CAN_MO228_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AC80u)
+
+/** Alias (User Manual Name) for CAN_MO228_EDATA0.
+* To use register names with standard convension, please use CAN_MO228_EDATA0.
+*/
+#define CAN_EMO228DATA0 (CAN_MO228_EDATA0)
+
+/** \brief 2C84, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO228_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AC84u)
+
+/** Alias (User Manual Name) for CAN_MO228_EDATA1.
+* To use register names with standard convension, please use CAN_MO228_EDATA1.
+*/
+#define CAN_EMO228DATA1 (CAN_MO228_EDATA1)
+
+/** \brief 2C88, Message Object Interrupt Pointer Register */
+#define CAN_MO228_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AC88u)
+
+/** Alias (User Manual Name) for CAN_MO228_EDATA2.
+* To use register names with standard convension, please use CAN_MO228_EDATA2.
+*/
+#define CAN_EMO228DATA2 (CAN_MO228_EDATA2)
+
+/** \brief 2C8C, Message Object Acceptance Mask Register */
+#define CAN_MO228_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AC8Cu)
+
+/** Alias (User Manual Name) for CAN_MO228_EDATA3.
+* To use register names with standard convension, please use CAN_MO228_EDATA3.
+*/
+#define CAN_EMO228DATA3 (CAN_MO228_EDATA3)
+
+/** \brief 2C90, Message Object Data Register Low */
+#define CAN_MO228_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AC90u)
+
+/** Alias (User Manual Name) for CAN_MO228_EDATA4.
+* To use register names with standard convension, please use CAN_MO228_EDATA4.
+*/
+#define CAN_EMO228DATA4 (CAN_MO228_EDATA4)
+
+/** \brief 2C94, Message Object Data Register High */
+#define CAN_MO228_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AC94u)
+
+/** Alias (User Manual Name) for CAN_MO228_EDATA5.
+* To use register names with standard convension, please use CAN_MO228_EDATA5.
+*/
+#define CAN_EMO228DATA5 (CAN_MO228_EDATA5)
+
+/** \brief 2C98, Message Object Arbitration Register */
+#define CAN_MO228_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AC98u)
+
+/** Alias (User Manual Name) for CAN_MO228_EDATA6.
+* To use register names with standard convension, please use CAN_MO228_EDATA6.
+*/
+#define CAN_EMO228DATA6 (CAN_MO228_EDATA6)
+
+/** \brief 2C80, Message Object Function Control Register */
+#define CAN_MO228_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AC80u)
+
+/** Alias (User Manual Name) for CAN_MO228_FCR.
+* To use register names with standard convension, please use CAN_MO228_FCR.
+*/
+#define CAN_MOFCR228 (CAN_MO228_FCR)
+
+/** \brief 2C84, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO228_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AC84u)
+
+/** Alias (User Manual Name) for CAN_MO228_FGPR.
+* To use register names with standard convension, please use CAN_MO228_FGPR.
+*/
+#define CAN_MOFGPR228 (CAN_MO228_FGPR)
+
+/** \brief 2C88, Message Object Interrupt Pointer Register */
+#define CAN_MO228_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AC88u)
+
+/** Alias (User Manual Name) for CAN_MO228_IPR.
+* To use register names with standard convension, please use CAN_MO228_IPR.
+*/
+#define CAN_MOIPR228 (CAN_MO228_IPR)
+
+/** \brief 2C9C, Message Object Control Register */
+#define CAN_MO228_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AC9Cu)
+
+/** Alias (User Manual Name) for CAN_MO228_STAT.
+* To use register names with standard convension, please use CAN_MO228_STAT.
+*/
+#define CAN_MOSTAT228 (CAN_MO228_STAT)
+
+/** \brief 2CAC, Message Object Acceptance Mask Register */
+#define CAN_MO229_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001ACACu)
+
+/** Alias (User Manual Name) for CAN_MO229_AMR.
+* To use register names with standard convension, please use CAN_MO229_AMR.
+*/
+#define CAN_MOAMR229 (CAN_MO229_AMR)
+
+/** \brief 2CB8, Message Object Arbitration Register */
+#define CAN_MO229_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001ACB8u)
+
+/** Alias (User Manual Name) for CAN_MO229_AR.
+* To use register names with standard convension, please use CAN_MO229_AR.
+*/
+#define CAN_MOAR229 (CAN_MO229_AR)
+
+/** \brief 2CBC, Message Object Control Register */
+#define CAN_MO229_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001ACBCu)
+
+/** Alias (User Manual Name) for CAN_MO229_CTR.
+* To use register names with standard convension, please use CAN_MO229_CTR.
+*/
+#define CAN_MOCTR229 (CAN_MO229_CTR)
+
+/** \brief 2CB4, Message Object Data Register High */
+#define CAN_MO229_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001ACB4u)
+
+/** Alias (User Manual Name) for CAN_MO229_DATAH.
+* To use register names with standard convension, please use CAN_MO229_DATAH.
+*/
+#define CAN_MODATAH229 (CAN_MO229_DATAH)
+
+/** \brief 2CB0, Message Object Data Register Low */
+#define CAN_MO229_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001ACB0u)
+
+/** Alias (User Manual Name) for CAN_MO229_DATAL.
+* To use register names with standard convension, please use CAN_MO229_DATAL.
+*/
+#define CAN_MODATAL229 (CAN_MO229_DATAL)
+
+/** \brief 2CA0, Message Object Function Control Register */
+#define CAN_MO229_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001ACA0u)
+
+/** Alias (User Manual Name) for CAN_MO229_EDATA0.
+* To use register names with standard convension, please use CAN_MO229_EDATA0.
+*/
+#define CAN_EMO229DATA0 (CAN_MO229_EDATA0)
+
+/** \brief 2CA4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO229_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001ACA4u)
+
+/** Alias (User Manual Name) for CAN_MO229_EDATA1.
+* To use register names with standard convension, please use CAN_MO229_EDATA1.
+*/
+#define CAN_EMO229DATA1 (CAN_MO229_EDATA1)
+
+/** \brief 2CA8, Message Object Interrupt Pointer Register */
+#define CAN_MO229_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001ACA8u)
+
+/** Alias (User Manual Name) for CAN_MO229_EDATA2.
+* To use register names with standard convension, please use CAN_MO229_EDATA2.
+*/
+#define CAN_EMO229DATA2 (CAN_MO229_EDATA2)
+
+/** \brief 2CAC, Message Object Acceptance Mask Register */
+#define CAN_MO229_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001ACACu)
+
+/** Alias (User Manual Name) for CAN_MO229_EDATA3.
+* To use register names with standard convension, please use CAN_MO229_EDATA3.
+*/
+#define CAN_EMO229DATA3 (CAN_MO229_EDATA3)
+
+/** \brief 2CB0, Message Object Data Register Low */
+#define CAN_MO229_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001ACB0u)
+
+/** Alias (User Manual Name) for CAN_MO229_EDATA4.
+* To use register names with standard convension, please use CAN_MO229_EDATA4.
+*/
+#define CAN_EMO229DATA4 (CAN_MO229_EDATA4)
+
+/** \brief 2CB4, Message Object Data Register High */
+#define CAN_MO229_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001ACB4u)
+
+/** Alias (User Manual Name) for CAN_MO229_EDATA5.
+* To use register names with standard convension, please use CAN_MO229_EDATA5.
+*/
+#define CAN_EMO229DATA5 (CAN_MO229_EDATA5)
+
+/** \brief 2CB8, Message Object Arbitration Register */
+#define CAN_MO229_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001ACB8u)
+
+/** Alias (User Manual Name) for CAN_MO229_EDATA6.
+* To use register names with standard convension, please use CAN_MO229_EDATA6.
+*/
+#define CAN_EMO229DATA6 (CAN_MO229_EDATA6)
+
+/** \brief 2CA0, Message Object Function Control Register */
+#define CAN_MO229_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001ACA0u)
+
+/** Alias (User Manual Name) for CAN_MO229_FCR.
+* To use register names with standard convension, please use CAN_MO229_FCR.
+*/
+#define CAN_MOFCR229 (CAN_MO229_FCR)
+
+/** \brief 2CA4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO229_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001ACA4u)
+
+/** Alias (User Manual Name) for CAN_MO229_FGPR.
+* To use register names with standard convension, please use CAN_MO229_FGPR.
+*/
+#define CAN_MOFGPR229 (CAN_MO229_FGPR)
+
+/** \brief 2CA8, Message Object Interrupt Pointer Register */
+#define CAN_MO229_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001ACA8u)
+
+/** Alias (User Manual Name) for CAN_MO229_IPR.
+* To use register names with standard convension, please use CAN_MO229_IPR.
+*/
+#define CAN_MOIPR229 (CAN_MO229_IPR)
+
+/** \brief 2CBC, Message Object Control Register */
+#define CAN_MO229_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001ACBCu)
+
+/** Alias (User Manual Name) for CAN_MO229_STAT.
+* To use register names with standard convension, please use CAN_MO229_STAT.
+*/
+#define CAN_MOSTAT229 (CAN_MO229_STAT)
+
+/** \brief 12CC, Message Object Acceptance Mask Register */
+#define CAN_MO22_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00192CCu)
+
+/** Alias (User Manual Name) for CAN_MO22_AMR.
+* To use register names with standard convension, please use CAN_MO22_AMR.
+*/
+#define CAN_MOAMR22 (CAN_MO22_AMR)
+
+/** \brief 12D8, Message Object Arbitration Register */
+#define CAN_MO22_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00192D8u)
+
+/** Alias (User Manual Name) for CAN_MO22_AR.
+* To use register names with standard convension, please use CAN_MO22_AR.
+*/
+#define CAN_MOAR22 (CAN_MO22_AR)
+
+/** \brief 12DC, Message Object Control Register */
+#define CAN_MO22_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00192DCu)
+
+/** Alias (User Manual Name) for CAN_MO22_CTR.
+* To use register names with standard convension, please use CAN_MO22_CTR.
+*/
+#define CAN_MOCTR22 (CAN_MO22_CTR)
+
+/** \brief 12D4, Message Object Data Register High */
+#define CAN_MO22_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00192D4u)
+
+/** Alias (User Manual Name) for CAN_MO22_DATAH.
+* To use register names with standard convension, please use CAN_MO22_DATAH.
+*/
+#define CAN_MODATAH22 (CAN_MO22_DATAH)
+
+/** \brief 12D0, Message Object Data Register Low */
+#define CAN_MO22_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00192D0u)
+
+/** Alias (User Manual Name) for CAN_MO22_DATAL.
+* To use register names with standard convension, please use CAN_MO22_DATAL.
+*/
+#define CAN_MODATAL22 (CAN_MO22_DATAL)
+
+/** \brief 12C0, Message Object Function Control Register */
+#define CAN_MO22_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00192C0u)
+
+/** Alias (User Manual Name) for CAN_MO22_EDATA0.
+* To use register names with standard convension, please use CAN_MO22_EDATA0.
+*/
+#define CAN_EMO22DATA0 (CAN_MO22_EDATA0)
+
+/** \brief 12C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO22_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00192C4u)
+
+/** Alias (User Manual Name) for CAN_MO22_EDATA1.
+* To use register names with standard convension, please use CAN_MO22_EDATA1.
+*/
+#define CAN_EMO22DATA1 (CAN_MO22_EDATA1)
+
+/** \brief 12C8, Message Object Interrupt Pointer Register */
+#define CAN_MO22_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00192C8u)
+
+/** Alias (User Manual Name) for CAN_MO22_EDATA2.
+* To use register names with standard convension, please use CAN_MO22_EDATA2.
+*/
+#define CAN_EMO22DATA2 (CAN_MO22_EDATA2)
+
+/** \brief 12CC, Message Object Acceptance Mask Register */
+#define CAN_MO22_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00192CCu)
+
+/** Alias (User Manual Name) for CAN_MO22_EDATA3.
+* To use register names with standard convension, please use CAN_MO22_EDATA3.
+*/
+#define CAN_EMO22DATA3 (CAN_MO22_EDATA3)
+
+/** \brief 12D0, Message Object Data Register Low */
+#define CAN_MO22_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00192D0u)
+
+/** Alias (User Manual Name) for CAN_MO22_EDATA4.
+* To use register names with standard convension, please use CAN_MO22_EDATA4.
+*/
+#define CAN_EMO22DATA4 (CAN_MO22_EDATA4)
+
+/** \brief 12D4, Message Object Data Register High */
+#define CAN_MO22_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00192D4u)
+
+/** Alias (User Manual Name) for CAN_MO22_EDATA5.
+* To use register names with standard convension, please use CAN_MO22_EDATA5.
+*/
+#define CAN_EMO22DATA5 (CAN_MO22_EDATA5)
+
+/** \brief 12D8, Message Object Arbitration Register */
+#define CAN_MO22_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00192D8u)
+
+/** Alias (User Manual Name) for CAN_MO22_EDATA6.
+* To use register names with standard convension, please use CAN_MO22_EDATA6.
+*/
+#define CAN_EMO22DATA6 (CAN_MO22_EDATA6)
+
+/** \brief 12C0, Message Object Function Control Register */
+#define CAN_MO22_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00192C0u)
+
+/** Alias (User Manual Name) for CAN_MO22_FCR.
+* To use register names with standard convension, please use CAN_MO22_FCR.
+*/
+#define CAN_MOFCR22 (CAN_MO22_FCR)
+
+/** \brief 12C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO22_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00192C4u)
+
+/** Alias (User Manual Name) for CAN_MO22_FGPR.
+* To use register names with standard convension, please use CAN_MO22_FGPR.
+*/
+#define CAN_MOFGPR22 (CAN_MO22_FGPR)
+
+/** \brief 12C8, Message Object Interrupt Pointer Register */
+#define CAN_MO22_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00192C8u)
+
+/** Alias (User Manual Name) for CAN_MO22_IPR.
+* To use register names with standard convension, please use CAN_MO22_IPR.
+*/
+#define CAN_MOIPR22 (CAN_MO22_IPR)
+
+/** \brief 12DC, Message Object Control Register */
+#define CAN_MO22_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00192DCu)
+
+/** Alias (User Manual Name) for CAN_MO22_STAT.
+* To use register names with standard convension, please use CAN_MO22_STAT.
+*/
+#define CAN_MOSTAT22 (CAN_MO22_STAT)
+
+/** \brief 2CCC, Message Object Acceptance Mask Register */
+#define CAN_MO230_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001ACCCu)
+
+/** Alias (User Manual Name) for CAN_MO230_AMR.
+* To use register names with standard convension, please use CAN_MO230_AMR.
+*/
+#define CAN_MOAMR230 (CAN_MO230_AMR)
+
+/** \brief 2CD8, Message Object Arbitration Register */
+#define CAN_MO230_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001ACD8u)
+
+/** Alias (User Manual Name) for CAN_MO230_AR.
+* To use register names with standard convension, please use CAN_MO230_AR.
+*/
+#define CAN_MOAR230 (CAN_MO230_AR)
+
+/** \brief 2CDC, Message Object Control Register */
+#define CAN_MO230_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001ACDCu)
+
+/** Alias (User Manual Name) for CAN_MO230_CTR.
+* To use register names with standard convension, please use CAN_MO230_CTR.
+*/
+#define CAN_MOCTR230 (CAN_MO230_CTR)
+
+/** \brief 2CD4, Message Object Data Register High */
+#define CAN_MO230_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001ACD4u)
+
+/** Alias (User Manual Name) for CAN_MO230_DATAH.
+* To use register names with standard convension, please use CAN_MO230_DATAH.
+*/
+#define CAN_MODATAH230 (CAN_MO230_DATAH)
+
+/** \brief 2CD0, Message Object Data Register Low */
+#define CAN_MO230_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001ACD0u)
+
+/** Alias (User Manual Name) for CAN_MO230_DATAL.
+* To use register names with standard convension, please use CAN_MO230_DATAL.
+*/
+#define CAN_MODATAL230 (CAN_MO230_DATAL)
+
+/** \brief 2CC0, Message Object Function Control Register */
+#define CAN_MO230_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001ACC0u)
+
+/** Alias (User Manual Name) for CAN_MO230_EDATA0.
+* To use register names with standard convension, please use CAN_MO230_EDATA0.
+*/
+#define CAN_EMO230DATA0 (CAN_MO230_EDATA0)
+
+/** \brief 2CC4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO230_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001ACC4u)
+
+/** Alias (User Manual Name) for CAN_MO230_EDATA1.
+* To use register names with standard convension, please use CAN_MO230_EDATA1.
+*/
+#define CAN_EMO230DATA1 (CAN_MO230_EDATA1)
+
+/** \brief 2CC8, Message Object Interrupt Pointer Register */
+#define CAN_MO230_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001ACC8u)
+
+/** Alias (User Manual Name) for CAN_MO230_EDATA2.
+* To use register names with standard convension, please use CAN_MO230_EDATA2.
+*/
+#define CAN_EMO230DATA2 (CAN_MO230_EDATA2)
+
+/** \brief 2CCC, Message Object Acceptance Mask Register */
+#define CAN_MO230_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001ACCCu)
+
+/** Alias (User Manual Name) for CAN_MO230_EDATA3.
+* To use register names with standard convension, please use CAN_MO230_EDATA3.
+*/
+#define CAN_EMO230DATA3 (CAN_MO230_EDATA3)
+
+/** \brief 2CD0, Message Object Data Register Low */
+#define CAN_MO230_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001ACD0u)
+
+/** Alias (User Manual Name) for CAN_MO230_EDATA4.
+* To use register names with standard convension, please use CAN_MO230_EDATA4.
+*/
+#define CAN_EMO230DATA4 (CAN_MO230_EDATA4)
+
+/** \brief 2CD4, Message Object Data Register High */
+#define CAN_MO230_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001ACD4u)
+
+/** Alias (User Manual Name) for CAN_MO230_EDATA5.
+* To use register names with standard convension, please use CAN_MO230_EDATA5.
+*/
+#define CAN_EMO230DATA5 (CAN_MO230_EDATA5)
+
+/** \brief 2CD8, Message Object Arbitration Register */
+#define CAN_MO230_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001ACD8u)
+
+/** Alias (User Manual Name) for CAN_MO230_EDATA6.
+* To use register names with standard convension, please use CAN_MO230_EDATA6.
+*/
+#define CAN_EMO230DATA6 (CAN_MO230_EDATA6)
+
+/** \brief 2CC0, Message Object Function Control Register */
+#define CAN_MO230_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001ACC0u)
+
+/** Alias (User Manual Name) for CAN_MO230_FCR.
+* To use register names with standard convension, please use CAN_MO230_FCR.
+*/
+#define CAN_MOFCR230 (CAN_MO230_FCR)
+
+/** \brief 2CC4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO230_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001ACC4u)
+
+/** Alias (User Manual Name) for CAN_MO230_FGPR.
+* To use register names with standard convension, please use CAN_MO230_FGPR.
+*/
+#define CAN_MOFGPR230 (CAN_MO230_FGPR)
+
+/** \brief 2CC8, Message Object Interrupt Pointer Register */
+#define CAN_MO230_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001ACC8u)
+
+/** Alias (User Manual Name) for CAN_MO230_IPR.
+* To use register names with standard convension, please use CAN_MO230_IPR.
+*/
+#define CAN_MOIPR230 (CAN_MO230_IPR)
+
+/** \brief 2CDC, Message Object Control Register */
+#define CAN_MO230_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001ACDCu)
+
+/** Alias (User Manual Name) for CAN_MO230_STAT.
+* To use register names with standard convension, please use CAN_MO230_STAT.
+*/
+#define CAN_MOSTAT230 (CAN_MO230_STAT)
+
+/** \brief 2CEC, Message Object Acceptance Mask Register */
+#define CAN_MO231_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001ACECu)
+
+/** Alias (User Manual Name) for CAN_MO231_AMR.
+* To use register names with standard convension, please use CAN_MO231_AMR.
+*/
+#define CAN_MOAMR231 (CAN_MO231_AMR)
+
+/** \brief 2CF8, Message Object Arbitration Register */
+#define CAN_MO231_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001ACF8u)
+
+/** Alias (User Manual Name) for CAN_MO231_AR.
+* To use register names with standard convension, please use CAN_MO231_AR.
+*/
+#define CAN_MOAR231 (CAN_MO231_AR)
+
+/** \brief 2CFC, Message Object Control Register */
+#define CAN_MO231_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001ACFCu)
+
+/** Alias (User Manual Name) for CAN_MO231_CTR.
+* To use register names with standard convension, please use CAN_MO231_CTR.
+*/
+#define CAN_MOCTR231 (CAN_MO231_CTR)
+
+/** \brief 2CF4, Message Object Data Register High */
+#define CAN_MO231_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001ACF4u)
+
+/** Alias (User Manual Name) for CAN_MO231_DATAH.
+* To use register names with standard convension, please use CAN_MO231_DATAH.
+*/
+#define CAN_MODATAH231 (CAN_MO231_DATAH)
+
+/** \brief 2CF0, Message Object Data Register Low */
+#define CAN_MO231_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001ACF0u)
+
+/** Alias (User Manual Name) for CAN_MO231_DATAL.
+* To use register names with standard convension, please use CAN_MO231_DATAL.
+*/
+#define CAN_MODATAL231 (CAN_MO231_DATAL)
+
+/** \brief 2CE0, Message Object Function Control Register */
+#define CAN_MO231_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001ACE0u)
+
+/** Alias (User Manual Name) for CAN_MO231_EDATA0.
+* To use register names with standard convension, please use CAN_MO231_EDATA0.
+*/
+#define CAN_EMO231DATA0 (CAN_MO231_EDATA0)
+
+/** \brief 2CE4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO231_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001ACE4u)
+
+/** Alias (User Manual Name) for CAN_MO231_EDATA1.
+* To use register names with standard convension, please use CAN_MO231_EDATA1.
+*/
+#define CAN_EMO231DATA1 (CAN_MO231_EDATA1)
+
+/** \brief 2CE8, Message Object Interrupt Pointer Register */
+#define CAN_MO231_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001ACE8u)
+
+/** Alias (User Manual Name) for CAN_MO231_EDATA2.
+* To use register names with standard convension, please use CAN_MO231_EDATA2.
+*/
+#define CAN_EMO231DATA2 (CAN_MO231_EDATA2)
+
+/** \brief 2CEC, Message Object Acceptance Mask Register */
+#define CAN_MO231_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001ACECu)
+
+/** Alias (User Manual Name) for CAN_MO231_EDATA3.
+* To use register names with standard convension, please use CAN_MO231_EDATA3.
+*/
+#define CAN_EMO231DATA3 (CAN_MO231_EDATA3)
+
+/** \brief 2CF0, Message Object Data Register Low */
+#define CAN_MO231_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001ACF0u)
+
+/** Alias (User Manual Name) for CAN_MO231_EDATA4.
+* To use register names with standard convension, please use CAN_MO231_EDATA4.
+*/
+#define CAN_EMO231DATA4 (CAN_MO231_EDATA4)
+
+/** \brief 2CF4, Message Object Data Register High */
+#define CAN_MO231_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001ACF4u)
+
+/** Alias (User Manual Name) for CAN_MO231_EDATA5.
+* To use register names with standard convension, please use CAN_MO231_EDATA5.
+*/
+#define CAN_EMO231DATA5 (CAN_MO231_EDATA5)
+
+/** \brief 2CF8, Message Object Arbitration Register */
+#define CAN_MO231_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001ACF8u)
+
+/** Alias (User Manual Name) for CAN_MO231_EDATA6.
+* To use register names with standard convension, please use CAN_MO231_EDATA6.
+*/
+#define CAN_EMO231DATA6 (CAN_MO231_EDATA6)
+
+/** \brief 2CE0, Message Object Function Control Register */
+#define CAN_MO231_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001ACE0u)
+
+/** Alias (User Manual Name) for CAN_MO231_FCR.
+* To use register names with standard convension, please use CAN_MO231_FCR.
+*/
+#define CAN_MOFCR231 (CAN_MO231_FCR)
+
+/** \brief 2CE4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO231_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001ACE4u)
+
+/** Alias (User Manual Name) for CAN_MO231_FGPR.
+* To use register names with standard convension, please use CAN_MO231_FGPR.
+*/
+#define CAN_MOFGPR231 (CAN_MO231_FGPR)
+
+/** \brief 2CE8, Message Object Interrupt Pointer Register */
+#define CAN_MO231_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001ACE8u)
+
+/** Alias (User Manual Name) for CAN_MO231_IPR.
+* To use register names with standard convension, please use CAN_MO231_IPR.
+*/
+#define CAN_MOIPR231 (CAN_MO231_IPR)
+
+/** \brief 2CFC, Message Object Control Register */
+#define CAN_MO231_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001ACFCu)
+
+/** Alias (User Manual Name) for CAN_MO231_STAT.
+* To use register names with standard convension, please use CAN_MO231_STAT.
+*/
+#define CAN_MOSTAT231 (CAN_MO231_STAT)
+
+/** \brief 2D0C, Message Object Acceptance Mask Register */
+#define CAN_MO232_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AD0Cu)
+
+/** Alias (User Manual Name) for CAN_MO232_AMR.
+* To use register names with standard convension, please use CAN_MO232_AMR.
+*/
+#define CAN_MOAMR232 (CAN_MO232_AMR)
+
+/** \brief 2D18, Message Object Arbitration Register */
+#define CAN_MO232_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AD18u)
+
+/** Alias (User Manual Name) for CAN_MO232_AR.
+* To use register names with standard convension, please use CAN_MO232_AR.
+*/
+#define CAN_MOAR232 (CAN_MO232_AR)
+
+/** \brief 2D1C, Message Object Control Register */
+#define CAN_MO232_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AD1Cu)
+
+/** Alias (User Manual Name) for CAN_MO232_CTR.
+* To use register names with standard convension, please use CAN_MO232_CTR.
+*/
+#define CAN_MOCTR232 (CAN_MO232_CTR)
+
+/** \brief 2D14, Message Object Data Register High */
+#define CAN_MO232_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AD14u)
+
+/** Alias (User Manual Name) for CAN_MO232_DATAH.
+* To use register names with standard convension, please use CAN_MO232_DATAH.
+*/
+#define CAN_MODATAH232 (CAN_MO232_DATAH)
+
+/** \brief 2D10, Message Object Data Register Low */
+#define CAN_MO232_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AD10u)
+
+/** Alias (User Manual Name) for CAN_MO232_DATAL.
+* To use register names with standard convension, please use CAN_MO232_DATAL.
+*/
+#define CAN_MODATAL232 (CAN_MO232_DATAL)
+
+/** \brief 2D00, Message Object Function Control Register */
+#define CAN_MO232_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AD00u)
+
+/** Alias (User Manual Name) for CAN_MO232_EDATA0.
+* To use register names with standard convension, please use CAN_MO232_EDATA0.
+*/
+#define CAN_EMO232DATA0 (CAN_MO232_EDATA0)
+
+/** \brief 2D04, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO232_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AD04u)
+
+/** Alias (User Manual Name) for CAN_MO232_EDATA1.
+* To use register names with standard convension, please use CAN_MO232_EDATA1.
+*/
+#define CAN_EMO232DATA1 (CAN_MO232_EDATA1)
+
+/** \brief 2D08, Message Object Interrupt Pointer Register */
+#define CAN_MO232_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AD08u)
+
+/** Alias (User Manual Name) for CAN_MO232_EDATA2.
+* To use register names with standard convension, please use CAN_MO232_EDATA2.
+*/
+#define CAN_EMO232DATA2 (CAN_MO232_EDATA2)
+
+/** \brief 2D0C, Message Object Acceptance Mask Register */
+#define CAN_MO232_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AD0Cu)
+
+/** Alias (User Manual Name) for CAN_MO232_EDATA3.
+* To use register names with standard convension, please use CAN_MO232_EDATA3.
+*/
+#define CAN_EMO232DATA3 (CAN_MO232_EDATA3)
+
+/** \brief 2D10, Message Object Data Register Low */
+#define CAN_MO232_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AD10u)
+
+/** Alias (User Manual Name) for CAN_MO232_EDATA4.
+* To use register names with standard convension, please use CAN_MO232_EDATA4.
+*/
+#define CAN_EMO232DATA4 (CAN_MO232_EDATA4)
+
+/** \brief 2D14, Message Object Data Register High */
+#define CAN_MO232_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AD14u)
+
+/** Alias (User Manual Name) for CAN_MO232_EDATA5.
+* To use register names with standard convension, please use CAN_MO232_EDATA5.
+*/
+#define CAN_EMO232DATA5 (CAN_MO232_EDATA5)
+
+/** \brief 2D18, Message Object Arbitration Register */
+#define CAN_MO232_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AD18u)
+
+/** Alias (User Manual Name) for CAN_MO232_EDATA6.
+* To use register names with standard convension, please use CAN_MO232_EDATA6.
+*/
+#define CAN_EMO232DATA6 (CAN_MO232_EDATA6)
+
+/** \brief 2D00, Message Object Function Control Register */
+#define CAN_MO232_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AD00u)
+
+/** Alias (User Manual Name) for CAN_MO232_FCR.
+* To use register names with standard convension, please use CAN_MO232_FCR.
+*/
+#define CAN_MOFCR232 (CAN_MO232_FCR)
+
+/** \brief 2D04, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO232_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AD04u)
+
+/** Alias (User Manual Name) for CAN_MO232_FGPR.
+* To use register names with standard convension, please use CAN_MO232_FGPR.
+*/
+#define CAN_MOFGPR232 (CAN_MO232_FGPR)
+
+/** \brief 2D08, Message Object Interrupt Pointer Register */
+#define CAN_MO232_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AD08u)
+
+/** Alias (User Manual Name) for CAN_MO232_IPR.
+* To use register names with standard convension, please use CAN_MO232_IPR.
+*/
+#define CAN_MOIPR232 (CAN_MO232_IPR)
+
+/** \brief 2D1C, Message Object Control Register */
+#define CAN_MO232_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AD1Cu)
+
+/** Alias (User Manual Name) for CAN_MO232_STAT.
+* To use register names with standard convension, please use CAN_MO232_STAT.
+*/
+#define CAN_MOSTAT232 (CAN_MO232_STAT)
+
+/** \brief 2D2C, Message Object Acceptance Mask Register */
+#define CAN_MO233_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AD2Cu)
+
+/** Alias (User Manual Name) for CAN_MO233_AMR.
+* To use register names with standard convension, please use CAN_MO233_AMR.
+*/
+#define CAN_MOAMR233 (CAN_MO233_AMR)
+
+/** \brief 2D38, Message Object Arbitration Register */
+#define CAN_MO233_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AD38u)
+
+/** Alias (User Manual Name) for CAN_MO233_AR.
+* To use register names with standard convension, please use CAN_MO233_AR.
+*/
+#define CAN_MOAR233 (CAN_MO233_AR)
+
+/** \brief 2D3C, Message Object Control Register */
+#define CAN_MO233_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AD3Cu)
+
+/** Alias (User Manual Name) for CAN_MO233_CTR.
+* To use register names with standard convension, please use CAN_MO233_CTR.
+*/
+#define CAN_MOCTR233 (CAN_MO233_CTR)
+
+/** \brief 2D34, Message Object Data Register High */
+#define CAN_MO233_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AD34u)
+
+/** Alias (User Manual Name) for CAN_MO233_DATAH.
+* To use register names with standard convension, please use CAN_MO233_DATAH.
+*/
+#define CAN_MODATAH233 (CAN_MO233_DATAH)
+
+/** \brief 2D30, Message Object Data Register Low */
+#define CAN_MO233_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AD30u)
+
+/** Alias (User Manual Name) for CAN_MO233_DATAL.
+* To use register names with standard convension, please use CAN_MO233_DATAL.
+*/
+#define CAN_MODATAL233 (CAN_MO233_DATAL)
+
+/** \brief 2D20, Message Object Function Control Register */
+#define CAN_MO233_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AD20u)
+
+/** Alias (User Manual Name) for CAN_MO233_EDATA0.
+* To use register names with standard convension, please use CAN_MO233_EDATA0.
+*/
+#define CAN_EMO233DATA0 (CAN_MO233_EDATA0)
+
+/** \brief 2D24, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO233_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AD24u)
+
+/** Alias (User Manual Name) for CAN_MO233_EDATA1.
+* To use register names with standard convension, please use CAN_MO233_EDATA1.
+*/
+#define CAN_EMO233DATA1 (CAN_MO233_EDATA1)
+
+/** \brief 2D28, Message Object Interrupt Pointer Register */
+#define CAN_MO233_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AD28u)
+
+/** Alias (User Manual Name) for CAN_MO233_EDATA2.
+* To use register names with standard convension, please use CAN_MO233_EDATA2.
+*/
+#define CAN_EMO233DATA2 (CAN_MO233_EDATA2)
+
+/** \brief 2D2C, Message Object Acceptance Mask Register */
+#define CAN_MO233_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AD2Cu)
+
+/** Alias (User Manual Name) for CAN_MO233_EDATA3.
+* To use register names with standard convension, please use CAN_MO233_EDATA3.
+*/
+#define CAN_EMO233DATA3 (CAN_MO233_EDATA3)
+
+/** \brief 2D30, Message Object Data Register Low */
+#define CAN_MO233_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AD30u)
+
+/** Alias (User Manual Name) for CAN_MO233_EDATA4.
+* To use register names with standard convension, please use CAN_MO233_EDATA4.
+*/
+#define CAN_EMO233DATA4 (CAN_MO233_EDATA4)
+
+/** \brief 2D34, Message Object Data Register High */
+#define CAN_MO233_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AD34u)
+
+/** Alias (User Manual Name) for CAN_MO233_EDATA5.
+* To use register names with standard convension, please use CAN_MO233_EDATA5.
+*/
+#define CAN_EMO233DATA5 (CAN_MO233_EDATA5)
+
+/** \brief 2D38, Message Object Arbitration Register */
+#define CAN_MO233_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AD38u)
+
+/** Alias (User Manual Name) for CAN_MO233_EDATA6.
+* To use register names with standard convension, please use CAN_MO233_EDATA6.
+*/
+#define CAN_EMO233DATA6 (CAN_MO233_EDATA6)
+
+/** \brief 2D20, Message Object Function Control Register */
+#define CAN_MO233_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AD20u)
+
+/** Alias (User Manual Name) for CAN_MO233_FCR.
+* To use register names with standard convension, please use CAN_MO233_FCR.
+*/
+#define CAN_MOFCR233 (CAN_MO233_FCR)
+
+/** \brief 2D24, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO233_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AD24u)
+
+/** Alias (User Manual Name) for CAN_MO233_FGPR.
+* To use register names with standard convension, please use CAN_MO233_FGPR.
+*/
+#define CAN_MOFGPR233 (CAN_MO233_FGPR)
+
+/** \brief 2D28, Message Object Interrupt Pointer Register */
+#define CAN_MO233_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AD28u)
+
+/** Alias (User Manual Name) for CAN_MO233_IPR.
+* To use register names with standard convension, please use CAN_MO233_IPR.
+*/
+#define CAN_MOIPR233 (CAN_MO233_IPR)
+
+/** \brief 2D3C, Message Object Control Register */
+#define CAN_MO233_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AD3Cu)
+
+/** Alias (User Manual Name) for CAN_MO233_STAT.
+* To use register names with standard convension, please use CAN_MO233_STAT.
+*/
+#define CAN_MOSTAT233 (CAN_MO233_STAT)
+
+/** \brief 2D4C, Message Object Acceptance Mask Register */
+#define CAN_MO234_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AD4Cu)
+
+/** Alias (User Manual Name) for CAN_MO234_AMR.
+* To use register names with standard convension, please use CAN_MO234_AMR.
+*/
+#define CAN_MOAMR234 (CAN_MO234_AMR)
+
+/** \brief 2D58, Message Object Arbitration Register */
+#define CAN_MO234_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AD58u)
+
+/** Alias (User Manual Name) for CAN_MO234_AR.
+* To use register names with standard convension, please use CAN_MO234_AR.
+*/
+#define CAN_MOAR234 (CAN_MO234_AR)
+
+/** \brief 2D5C, Message Object Control Register */
+#define CAN_MO234_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AD5Cu)
+
+/** Alias (User Manual Name) for CAN_MO234_CTR.
+* To use register names with standard convension, please use CAN_MO234_CTR.
+*/
+#define CAN_MOCTR234 (CAN_MO234_CTR)
+
+/** \brief 2D54, Message Object Data Register High */
+#define CAN_MO234_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AD54u)
+
+/** Alias (User Manual Name) for CAN_MO234_DATAH.
+* To use register names with standard convension, please use CAN_MO234_DATAH.
+*/
+#define CAN_MODATAH234 (CAN_MO234_DATAH)
+
+/** \brief 2D50, Message Object Data Register Low */
+#define CAN_MO234_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AD50u)
+
+/** Alias (User Manual Name) for CAN_MO234_DATAL.
+* To use register names with standard convension, please use CAN_MO234_DATAL.
+*/
+#define CAN_MODATAL234 (CAN_MO234_DATAL)
+
+/** \brief 2D40, Message Object Function Control Register */
+#define CAN_MO234_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AD40u)
+
+/** Alias (User Manual Name) for CAN_MO234_EDATA0.
+* To use register names with standard convension, please use CAN_MO234_EDATA0.
+*/
+#define CAN_EMO234DATA0 (CAN_MO234_EDATA0)
+
+/** \brief 2D44, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO234_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AD44u)
+
+/** Alias (User Manual Name) for CAN_MO234_EDATA1.
+* To use register names with standard convension, please use CAN_MO234_EDATA1.
+*/
+#define CAN_EMO234DATA1 (CAN_MO234_EDATA1)
+
+/** \brief 2D48, Message Object Interrupt Pointer Register */
+#define CAN_MO234_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AD48u)
+
+/** Alias (User Manual Name) for CAN_MO234_EDATA2.
+* To use register names with standard convension, please use CAN_MO234_EDATA2.
+*/
+#define CAN_EMO234DATA2 (CAN_MO234_EDATA2)
+
+/** \brief 2D4C, Message Object Acceptance Mask Register */
+#define CAN_MO234_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AD4Cu)
+
+/** Alias (User Manual Name) for CAN_MO234_EDATA3.
+* To use register names with standard convension, please use CAN_MO234_EDATA3.
+*/
+#define CAN_EMO234DATA3 (CAN_MO234_EDATA3)
+
+/** \brief 2D50, Message Object Data Register Low */
+#define CAN_MO234_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AD50u)
+
+/** Alias (User Manual Name) for CAN_MO234_EDATA4.
+* To use register names with standard convension, please use CAN_MO234_EDATA4.
+*/
+#define CAN_EMO234DATA4 (CAN_MO234_EDATA4)
+
+/** \brief 2D54, Message Object Data Register High */
+#define CAN_MO234_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AD54u)
+
+/** Alias (User Manual Name) for CAN_MO234_EDATA5.
+* To use register names with standard convension, please use CAN_MO234_EDATA5.
+*/
+#define CAN_EMO234DATA5 (CAN_MO234_EDATA5)
+
+/** \brief 2D58, Message Object Arbitration Register */
+#define CAN_MO234_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AD58u)
+
+/** Alias (User Manual Name) for CAN_MO234_EDATA6.
+* To use register names with standard convension, please use CAN_MO234_EDATA6.
+*/
+#define CAN_EMO234DATA6 (CAN_MO234_EDATA6)
+
+/** \brief 2D40, Message Object Function Control Register */
+#define CAN_MO234_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AD40u)
+
+/** Alias (User Manual Name) for CAN_MO234_FCR.
+* To use register names with standard convension, please use CAN_MO234_FCR.
+*/
+#define CAN_MOFCR234 (CAN_MO234_FCR)
+
+/** \brief 2D44, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO234_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AD44u)
+
+/** Alias (User Manual Name) for CAN_MO234_FGPR.
+* To use register names with standard convension, please use CAN_MO234_FGPR.
+*/
+#define CAN_MOFGPR234 (CAN_MO234_FGPR)
+
+/** \brief 2D48, Message Object Interrupt Pointer Register */
+#define CAN_MO234_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AD48u)
+
+/** Alias (User Manual Name) for CAN_MO234_IPR.
+* To use register names with standard convension, please use CAN_MO234_IPR.
+*/
+#define CAN_MOIPR234 (CAN_MO234_IPR)
+
+/** \brief 2D5C, Message Object Control Register */
+#define CAN_MO234_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AD5Cu)
+
+/** Alias (User Manual Name) for CAN_MO234_STAT.
+* To use register names with standard convension, please use CAN_MO234_STAT.
+*/
+#define CAN_MOSTAT234 (CAN_MO234_STAT)
+
+/** \brief 2D6C, Message Object Acceptance Mask Register */
+#define CAN_MO235_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AD6Cu)
+
+/** Alias (User Manual Name) for CAN_MO235_AMR.
+* To use register names with standard convension, please use CAN_MO235_AMR.
+*/
+#define CAN_MOAMR235 (CAN_MO235_AMR)
+
+/** \brief 2D78, Message Object Arbitration Register */
+#define CAN_MO235_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AD78u)
+
+/** Alias (User Manual Name) for CAN_MO235_AR.
+* To use register names with standard convension, please use CAN_MO235_AR.
+*/
+#define CAN_MOAR235 (CAN_MO235_AR)
+
+/** \brief 2D7C, Message Object Control Register */
+#define CAN_MO235_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AD7Cu)
+
+/** Alias (User Manual Name) for CAN_MO235_CTR.
+* To use register names with standard convension, please use CAN_MO235_CTR.
+*/
+#define CAN_MOCTR235 (CAN_MO235_CTR)
+
+/** \brief 2D74, Message Object Data Register High */
+#define CAN_MO235_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AD74u)
+
+/** Alias (User Manual Name) for CAN_MO235_DATAH.
+* To use register names with standard convension, please use CAN_MO235_DATAH.
+*/
+#define CAN_MODATAH235 (CAN_MO235_DATAH)
+
+/** \brief 2D70, Message Object Data Register Low */
+#define CAN_MO235_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AD70u)
+
+/** Alias (User Manual Name) for CAN_MO235_DATAL.
+* To use register names with standard convension, please use CAN_MO235_DATAL.
+*/
+#define CAN_MODATAL235 (CAN_MO235_DATAL)
+
+/** \brief 2D60, Message Object Function Control Register */
+#define CAN_MO235_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AD60u)
+
+/** Alias (User Manual Name) for CAN_MO235_EDATA0.
+* To use register names with standard convension, please use CAN_MO235_EDATA0.
+*/
+#define CAN_EMO235DATA0 (CAN_MO235_EDATA0)
+
+/** \brief 2D64, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO235_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AD64u)
+
+/** Alias (User Manual Name) for CAN_MO235_EDATA1.
+* To use register names with standard convension, please use CAN_MO235_EDATA1.
+*/
+#define CAN_EMO235DATA1 (CAN_MO235_EDATA1)
+
+/** \brief 2D68, Message Object Interrupt Pointer Register */
+#define CAN_MO235_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AD68u)
+
+/** Alias (User Manual Name) for CAN_MO235_EDATA2.
+* To use register names with standard convension, please use CAN_MO235_EDATA2.
+*/
+#define CAN_EMO235DATA2 (CAN_MO235_EDATA2)
+
+/** \brief 2D6C, Message Object Acceptance Mask Register */
+#define CAN_MO235_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AD6Cu)
+
+/** Alias (User Manual Name) for CAN_MO235_EDATA3.
+* To use register names with standard convension, please use CAN_MO235_EDATA3.
+*/
+#define CAN_EMO235DATA3 (CAN_MO235_EDATA3)
+
+/** \brief 2D70, Message Object Data Register Low */
+#define CAN_MO235_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AD70u)
+
+/** Alias (User Manual Name) for CAN_MO235_EDATA4.
+* To use register names with standard convension, please use CAN_MO235_EDATA4.
+*/
+#define CAN_EMO235DATA4 (CAN_MO235_EDATA4)
+
+/** \brief 2D74, Message Object Data Register High */
+#define CAN_MO235_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AD74u)
+
+/** Alias (User Manual Name) for CAN_MO235_EDATA5.
+* To use register names with standard convension, please use CAN_MO235_EDATA5.
+*/
+#define CAN_EMO235DATA5 (CAN_MO235_EDATA5)
+
+/** \brief 2D78, Message Object Arbitration Register */
+#define CAN_MO235_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AD78u)
+
+/** Alias (User Manual Name) for CAN_MO235_EDATA6.
+* To use register names with standard convension, please use CAN_MO235_EDATA6.
+*/
+#define CAN_EMO235DATA6 (CAN_MO235_EDATA6)
+
+/** \brief 2D60, Message Object Function Control Register */
+#define CAN_MO235_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AD60u)
+
+/** Alias (User Manual Name) for CAN_MO235_FCR.
+* To use register names with standard convension, please use CAN_MO235_FCR.
+*/
+#define CAN_MOFCR235 (CAN_MO235_FCR)
+
+/** \brief 2D64, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO235_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AD64u)
+
+/** Alias (User Manual Name) for CAN_MO235_FGPR.
+* To use register names with standard convension, please use CAN_MO235_FGPR.
+*/
+#define CAN_MOFGPR235 (CAN_MO235_FGPR)
+
+/** \brief 2D68, Message Object Interrupt Pointer Register */
+#define CAN_MO235_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AD68u)
+
+/** Alias (User Manual Name) for CAN_MO235_IPR.
+* To use register names with standard convension, please use CAN_MO235_IPR.
+*/
+#define CAN_MOIPR235 (CAN_MO235_IPR)
+
+/** \brief 2D7C, Message Object Control Register */
+#define CAN_MO235_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AD7Cu)
+
+/** Alias (User Manual Name) for CAN_MO235_STAT.
+* To use register names with standard convension, please use CAN_MO235_STAT.
+*/
+#define CAN_MOSTAT235 (CAN_MO235_STAT)
+
+/** \brief 2D8C, Message Object Acceptance Mask Register */
+#define CAN_MO236_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AD8Cu)
+
+/** Alias (User Manual Name) for CAN_MO236_AMR.
+* To use register names with standard convension, please use CAN_MO236_AMR.
+*/
+#define CAN_MOAMR236 (CAN_MO236_AMR)
+
+/** \brief 2D98, Message Object Arbitration Register */
+#define CAN_MO236_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AD98u)
+
+/** Alias (User Manual Name) for CAN_MO236_AR.
+* To use register names with standard convension, please use CAN_MO236_AR.
+*/
+#define CAN_MOAR236 (CAN_MO236_AR)
+
+/** \brief 2D9C, Message Object Control Register */
+#define CAN_MO236_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AD9Cu)
+
+/** Alias (User Manual Name) for CAN_MO236_CTR.
+* To use register names with standard convension, please use CAN_MO236_CTR.
+*/
+#define CAN_MOCTR236 (CAN_MO236_CTR)
+
+/** \brief 2D94, Message Object Data Register High */
+#define CAN_MO236_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AD94u)
+
+/** Alias (User Manual Name) for CAN_MO236_DATAH.
+* To use register names with standard convension, please use CAN_MO236_DATAH.
+*/
+#define CAN_MODATAH236 (CAN_MO236_DATAH)
+
+/** \brief 2D90, Message Object Data Register Low */
+#define CAN_MO236_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AD90u)
+
+/** Alias (User Manual Name) for CAN_MO236_DATAL.
+* To use register names with standard convension, please use CAN_MO236_DATAL.
+*/
+#define CAN_MODATAL236 (CAN_MO236_DATAL)
+
+/** \brief 2D80, Message Object Function Control Register */
+#define CAN_MO236_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AD80u)
+
+/** Alias (User Manual Name) for CAN_MO236_EDATA0.
+* To use register names with standard convension, please use CAN_MO236_EDATA0.
+*/
+#define CAN_EMO236DATA0 (CAN_MO236_EDATA0)
+
+/** \brief 2D84, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO236_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AD84u)
+
+/** Alias (User Manual Name) for CAN_MO236_EDATA1.
+* To use register names with standard convension, please use CAN_MO236_EDATA1.
+*/
+#define CAN_EMO236DATA1 (CAN_MO236_EDATA1)
+
+/** \brief 2D88, Message Object Interrupt Pointer Register */
+#define CAN_MO236_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AD88u)
+
+/** Alias (User Manual Name) for CAN_MO236_EDATA2.
+* To use register names with standard convension, please use CAN_MO236_EDATA2.
+*/
+#define CAN_EMO236DATA2 (CAN_MO236_EDATA2)
+
+/** \brief 2D8C, Message Object Acceptance Mask Register */
+#define CAN_MO236_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AD8Cu)
+
+/** Alias (User Manual Name) for CAN_MO236_EDATA3.
+* To use register names with standard convension, please use CAN_MO236_EDATA3.
+*/
+#define CAN_EMO236DATA3 (CAN_MO236_EDATA3)
+
+/** \brief 2D90, Message Object Data Register Low */
+#define CAN_MO236_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AD90u)
+
+/** Alias (User Manual Name) for CAN_MO236_EDATA4.
+* To use register names with standard convension, please use CAN_MO236_EDATA4.
+*/
+#define CAN_EMO236DATA4 (CAN_MO236_EDATA4)
+
+/** \brief 2D94, Message Object Data Register High */
+#define CAN_MO236_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AD94u)
+
+/** Alias (User Manual Name) for CAN_MO236_EDATA5.
+* To use register names with standard convension, please use CAN_MO236_EDATA5.
+*/
+#define CAN_EMO236DATA5 (CAN_MO236_EDATA5)
+
+/** \brief 2D98, Message Object Arbitration Register */
+#define CAN_MO236_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AD98u)
+
+/** Alias (User Manual Name) for CAN_MO236_EDATA6.
+* To use register names with standard convension, please use CAN_MO236_EDATA6.
+*/
+#define CAN_EMO236DATA6 (CAN_MO236_EDATA6)
+
+/** \brief 2D80, Message Object Function Control Register */
+#define CAN_MO236_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AD80u)
+
+/** Alias (User Manual Name) for CAN_MO236_FCR.
+* To use register names with standard convension, please use CAN_MO236_FCR.
+*/
+#define CAN_MOFCR236 (CAN_MO236_FCR)
+
+/** \brief 2D84, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO236_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AD84u)
+
+/** Alias (User Manual Name) for CAN_MO236_FGPR.
+* To use register names with standard convension, please use CAN_MO236_FGPR.
+*/
+#define CAN_MOFGPR236 (CAN_MO236_FGPR)
+
+/** \brief 2D88, Message Object Interrupt Pointer Register */
+#define CAN_MO236_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AD88u)
+
+/** Alias (User Manual Name) for CAN_MO236_IPR.
+* To use register names with standard convension, please use CAN_MO236_IPR.
+*/
+#define CAN_MOIPR236 (CAN_MO236_IPR)
+
+/** \brief 2D9C, Message Object Control Register */
+#define CAN_MO236_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AD9Cu)
+
+/** Alias (User Manual Name) for CAN_MO236_STAT.
+* To use register names with standard convension, please use CAN_MO236_STAT.
+*/
+#define CAN_MOSTAT236 (CAN_MO236_STAT)
+
+/** \brief 2DAC, Message Object Acceptance Mask Register */
+#define CAN_MO237_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001ADACu)
+
+/** Alias (User Manual Name) for CAN_MO237_AMR.
+* To use register names with standard convension, please use CAN_MO237_AMR.
+*/
+#define CAN_MOAMR237 (CAN_MO237_AMR)
+
+/** \brief 2DB8, Message Object Arbitration Register */
+#define CAN_MO237_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001ADB8u)
+
+/** Alias (User Manual Name) for CAN_MO237_AR.
+* To use register names with standard convension, please use CAN_MO237_AR.
+*/
+#define CAN_MOAR237 (CAN_MO237_AR)
+
+/** \brief 2DBC, Message Object Control Register */
+#define CAN_MO237_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001ADBCu)
+
+/** Alias (User Manual Name) for CAN_MO237_CTR.
+* To use register names with standard convension, please use CAN_MO237_CTR.
+*/
+#define CAN_MOCTR237 (CAN_MO237_CTR)
+
+/** \brief 2DB4, Message Object Data Register High */
+#define CAN_MO237_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001ADB4u)
+
+/** Alias (User Manual Name) for CAN_MO237_DATAH.
+* To use register names with standard convension, please use CAN_MO237_DATAH.
+*/
+#define CAN_MODATAH237 (CAN_MO237_DATAH)
+
+/** \brief 2DB0, Message Object Data Register Low */
+#define CAN_MO237_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001ADB0u)
+
+/** Alias (User Manual Name) for CAN_MO237_DATAL.
+* To use register names with standard convension, please use CAN_MO237_DATAL.
+*/
+#define CAN_MODATAL237 (CAN_MO237_DATAL)
+
+/** \brief 2DA0, Message Object Function Control Register */
+#define CAN_MO237_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001ADA0u)
+
+/** Alias (User Manual Name) for CAN_MO237_EDATA0.
+* To use register names with standard convension, please use CAN_MO237_EDATA0.
+*/
+#define CAN_EMO237DATA0 (CAN_MO237_EDATA0)
+
+/** \brief 2DA4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO237_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001ADA4u)
+
+/** Alias (User Manual Name) for CAN_MO237_EDATA1.
+* To use register names with standard convension, please use CAN_MO237_EDATA1.
+*/
+#define CAN_EMO237DATA1 (CAN_MO237_EDATA1)
+
+/** \brief 2DA8, Message Object Interrupt Pointer Register */
+#define CAN_MO237_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001ADA8u)
+
+/** Alias (User Manual Name) for CAN_MO237_EDATA2.
+* To use register names with standard convension, please use CAN_MO237_EDATA2.
+*/
+#define CAN_EMO237DATA2 (CAN_MO237_EDATA2)
+
+/** \brief 2DAC, Message Object Acceptance Mask Register */
+#define CAN_MO237_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001ADACu)
+
+/** Alias (User Manual Name) for CAN_MO237_EDATA3.
+* To use register names with standard convension, please use CAN_MO237_EDATA3.
+*/
+#define CAN_EMO237DATA3 (CAN_MO237_EDATA3)
+
+/** \brief 2DB0, Message Object Data Register Low */
+#define CAN_MO237_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001ADB0u)
+
+/** Alias (User Manual Name) for CAN_MO237_EDATA4.
+* To use register names with standard convension, please use CAN_MO237_EDATA4.
+*/
+#define CAN_EMO237DATA4 (CAN_MO237_EDATA4)
+
+/** \brief 2DB4, Message Object Data Register High */
+#define CAN_MO237_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001ADB4u)
+
+/** Alias (User Manual Name) for CAN_MO237_EDATA5.
+* To use register names with standard convension, please use CAN_MO237_EDATA5.
+*/
+#define CAN_EMO237DATA5 (CAN_MO237_EDATA5)
+
+/** \brief 2DB8, Message Object Arbitration Register */
+#define CAN_MO237_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001ADB8u)
+
+/** Alias (User Manual Name) for CAN_MO237_EDATA6.
+* To use register names with standard convension, please use CAN_MO237_EDATA6.
+*/
+#define CAN_EMO237DATA6 (CAN_MO237_EDATA6)
+
+/** \brief 2DA0, Message Object Function Control Register */
+#define CAN_MO237_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001ADA0u)
+
+/** Alias (User Manual Name) for CAN_MO237_FCR.
+* To use register names with standard convension, please use CAN_MO237_FCR.
+*/
+#define CAN_MOFCR237 (CAN_MO237_FCR)
+
+/** \brief 2DA4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO237_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001ADA4u)
+
+/** Alias (User Manual Name) for CAN_MO237_FGPR.
+* To use register names with standard convension, please use CAN_MO237_FGPR.
+*/
+#define CAN_MOFGPR237 (CAN_MO237_FGPR)
+
+/** \brief 2DA8, Message Object Interrupt Pointer Register */
+#define CAN_MO237_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001ADA8u)
+
+/** Alias (User Manual Name) for CAN_MO237_IPR.
+* To use register names with standard convension, please use CAN_MO237_IPR.
+*/
+#define CAN_MOIPR237 (CAN_MO237_IPR)
+
+/** \brief 2DBC, Message Object Control Register */
+#define CAN_MO237_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001ADBCu)
+
+/** Alias (User Manual Name) for CAN_MO237_STAT.
+* To use register names with standard convension, please use CAN_MO237_STAT.
+*/
+#define CAN_MOSTAT237 (CAN_MO237_STAT)
+
+/** \brief 2DCC, Message Object Acceptance Mask Register */
+#define CAN_MO238_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001ADCCu)
+
+/** Alias (User Manual Name) for CAN_MO238_AMR.
+* To use register names with standard convension, please use CAN_MO238_AMR.
+*/
+#define CAN_MOAMR238 (CAN_MO238_AMR)
+
+/** \brief 2DD8, Message Object Arbitration Register */
+#define CAN_MO238_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001ADD8u)
+
+/** Alias (User Manual Name) for CAN_MO238_AR.
+* To use register names with standard convension, please use CAN_MO238_AR.
+*/
+#define CAN_MOAR238 (CAN_MO238_AR)
+
+/** \brief 2DDC, Message Object Control Register */
+#define CAN_MO238_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001ADDCu)
+
+/** Alias (User Manual Name) for CAN_MO238_CTR.
+* To use register names with standard convension, please use CAN_MO238_CTR.
+*/
+#define CAN_MOCTR238 (CAN_MO238_CTR)
+
+/** \brief 2DD4, Message Object Data Register High */
+#define CAN_MO238_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001ADD4u)
+
+/** Alias (User Manual Name) for CAN_MO238_DATAH.
+* To use register names with standard convension, please use CAN_MO238_DATAH.
+*/
+#define CAN_MODATAH238 (CAN_MO238_DATAH)
+
+/** \brief 2DD0, Message Object Data Register Low */
+#define CAN_MO238_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001ADD0u)
+
+/** Alias (User Manual Name) for CAN_MO238_DATAL.
+* To use register names with standard convension, please use CAN_MO238_DATAL.
+*/
+#define CAN_MODATAL238 (CAN_MO238_DATAL)
+
+/** \brief 2DC0, Message Object Function Control Register */
+#define CAN_MO238_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001ADC0u)
+
+/** Alias (User Manual Name) for CAN_MO238_EDATA0.
+* To use register names with standard convension, please use CAN_MO238_EDATA0.
+*/
+#define CAN_EMO238DATA0 (CAN_MO238_EDATA0)
+
+/** \brief 2DC4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO238_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001ADC4u)
+
+/** Alias (User Manual Name) for CAN_MO238_EDATA1.
+* To use register names with standard convension, please use CAN_MO238_EDATA1.
+*/
+#define CAN_EMO238DATA1 (CAN_MO238_EDATA1)
+
+/** \brief 2DC8, Message Object Interrupt Pointer Register */
+#define CAN_MO238_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001ADC8u)
+
+/** Alias (User Manual Name) for CAN_MO238_EDATA2.
+* To use register names with standard convension, please use CAN_MO238_EDATA2.
+*/
+#define CAN_EMO238DATA2 (CAN_MO238_EDATA2)
+
+/** \brief 2DCC, Message Object Acceptance Mask Register */
+#define CAN_MO238_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001ADCCu)
+
+/** Alias (User Manual Name) for CAN_MO238_EDATA3.
+* To use register names with standard convension, please use CAN_MO238_EDATA3.
+*/
+#define CAN_EMO238DATA3 (CAN_MO238_EDATA3)
+
+/** \brief 2DD0, Message Object Data Register Low */
+#define CAN_MO238_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001ADD0u)
+
+/** Alias (User Manual Name) for CAN_MO238_EDATA4.
+* To use register names with standard convension, please use CAN_MO238_EDATA4.
+*/
+#define CAN_EMO238DATA4 (CAN_MO238_EDATA4)
+
+/** \brief 2DD4, Message Object Data Register High */
+#define CAN_MO238_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001ADD4u)
+
+/** Alias (User Manual Name) for CAN_MO238_EDATA5.
+* To use register names with standard convension, please use CAN_MO238_EDATA5.
+*/
+#define CAN_EMO238DATA5 (CAN_MO238_EDATA5)
+
+/** \brief 2DD8, Message Object Arbitration Register */
+#define CAN_MO238_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001ADD8u)
+
+/** Alias (User Manual Name) for CAN_MO238_EDATA6.
+* To use register names with standard convension, please use CAN_MO238_EDATA6.
+*/
+#define CAN_EMO238DATA6 (CAN_MO238_EDATA6)
+
+/** \brief 2DC0, Message Object Function Control Register */
+#define CAN_MO238_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001ADC0u)
+
+/** Alias (User Manual Name) for CAN_MO238_FCR.
+* To use register names with standard convension, please use CAN_MO238_FCR.
+*/
+#define CAN_MOFCR238 (CAN_MO238_FCR)
+
+/** \brief 2DC4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO238_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001ADC4u)
+
+/** Alias (User Manual Name) for CAN_MO238_FGPR.
+* To use register names with standard convension, please use CAN_MO238_FGPR.
+*/
+#define CAN_MOFGPR238 (CAN_MO238_FGPR)
+
+/** \brief 2DC8, Message Object Interrupt Pointer Register */
+#define CAN_MO238_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001ADC8u)
+
+/** Alias (User Manual Name) for CAN_MO238_IPR.
+* To use register names with standard convension, please use CAN_MO238_IPR.
+*/
+#define CAN_MOIPR238 (CAN_MO238_IPR)
+
+/** \brief 2DDC, Message Object Control Register */
+#define CAN_MO238_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001ADDCu)
+
+/** Alias (User Manual Name) for CAN_MO238_STAT.
+* To use register names with standard convension, please use CAN_MO238_STAT.
+*/
+#define CAN_MOSTAT238 (CAN_MO238_STAT)
+
+/** \brief 2DEC, Message Object Acceptance Mask Register */
+#define CAN_MO239_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001ADECu)
+
+/** Alias (User Manual Name) for CAN_MO239_AMR.
+* To use register names with standard convension, please use CAN_MO239_AMR.
+*/
+#define CAN_MOAMR239 (CAN_MO239_AMR)
+
+/** \brief 2DF8, Message Object Arbitration Register */
+#define CAN_MO239_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001ADF8u)
+
+/** Alias (User Manual Name) for CAN_MO239_AR.
+* To use register names with standard convension, please use CAN_MO239_AR.
+*/
+#define CAN_MOAR239 (CAN_MO239_AR)
+
+/** \brief 2DFC, Message Object Control Register */
+#define CAN_MO239_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001ADFCu)
+
+/** Alias (User Manual Name) for CAN_MO239_CTR.
+* To use register names with standard convension, please use CAN_MO239_CTR.
+*/
+#define CAN_MOCTR239 (CAN_MO239_CTR)
+
+/** \brief 2DF4, Message Object Data Register High */
+#define CAN_MO239_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001ADF4u)
+
+/** Alias (User Manual Name) for CAN_MO239_DATAH.
+* To use register names with standard convension, please use CAN_MO239_DATAH.
+*/
+#define CAN_MODATAH239 (CAN_MO239_DATAH)
+
+/** \brief 2DF0, Message Object Data Register Low */
+#define CAN_MO239_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001ADF0u)
+
+/** Alias (User Manual Name) for CAN_MO239_DATAL.
+* To use register names with standard convension, please use CAN_MO239_DATAL.
+*/
+#define CAN_MODATAL239 (CAN_MO239_DATAL)
+
+/** \brief 2DE0, Message Object Function Control Register */
+#define CAN_MO239_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001ADE0u)
+
+/** Alias (User Manual Name) for CAN_MO239_EDATA0.
+* To use register names with standard convension, please use CAN_MO239_EDATA0.
+*/
+#define CAN_EMO239DATA0 (CAN_MO239_EDATA0)
+
+/** \brief 2DE4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO239_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001ADE4u)
+
+/** Alias (User Manual Name) for CAN_MO239_EDATA1.
+* To use register names with standard convension, please use CAN_MO239_EDATA1.
+*/
+#define CAN_EMO239DATA1 (CAN_MO239_EDATA1)
+
+/** \brief 2DE8, Message Object Interrupt Pointer Register */
+#define CAN_MO239_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001ADE8u)
+
+/** Alias (User Manual Name) for CAN_MO239_EDATA2.
+* To use register names with standard convension, please use CAN_MO239_EDATA2.
+*/
+#define CAN_EMO239DATA2 (CAN_MO239_EDATA2)
+
+/** \brief 2DEC, Message Object Acceptance Mask Register */
+#define CAN_MO239_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001ADECu)
+
+/** Alias (User Manual Name) for CAN_MO239_EDATA3.
+* To use register names with standard convension, please use CAN_MO239_EDATA3.
+*/
+#define CAN_EMO239DATA3 (CAN_MO239_EDATA3)
+
+/** \brief 2DF0, Message Object Data Register Low */
+#define CAN_MO239_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001ADF0u)
+
+/** Alias (User Manual Name) for CAN_MO239_EDATA4.
+* To use register names with standard convension, please use CAN_MO239_EDATA4.
+*/
+#define CAN_EMO239DATA4 (CAN_MO239_EDATA4)
+
+/** \brief 2DF4, Message Object Data Register High */
+#define CAN_MO239_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001ADF4u)
+
+/** Alias (User Manual Name) for CAN_MO239_EDATA5.
+* To use register names with standard convension, please use CAN_MO239_EDATA5.
+*/
+#define CAN_EMO239DATA5 (CAN_MO239_EDATA5)
+
+/** \brief 2DF8, Message Object Arbitration Register */
+#define CAN_MO239_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001ADF8u)
+
+/** Alias (User Manual Name) for CAN_MO239_EDATA6.
+* To use register names with standard convension, please use CAN_MO239_EDATA6.
+*/
+#define CAN_EMO239DATA6 (CAN_MO239_EDATA6)
+
+/** \brief 2DE0, Message Object Function Control Register */
+#define CAN_MO239_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001ADE0u)
+
+/** Alias (User Manual Name) for CAN_MO239_FCR.
+* To use register names with standard convension, please use CAN_MO239_FCR.
+*/
+#define CAN_MOFCR239 (CAN_MO239_FCR)
+
+/** \brief 2DE4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO239_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001ADE4u)
+
+/** Alias (User Manual Name) for CAN_MO239_FGPR.
+* To use register names with standard convension, please use CAN_MO239_FGPR.
+*/
+#define CAN_MOFGPR239 (CAN_MO239_FGPR)
+
+/** \brief 2DE8, Message Object Interrupt Pointer Register */
+#define CAN_MO239_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001ADE8u)
+
+/** Alias (User Manual Name) for CAN_MO239_IPR.
+* To use register names with standard convension, please use CAN_MO239_IPR.
+*/
+#define CAN_MOIPR239 (CAN_MO239_IPR)
+
+/** \brief 2DFC, Message Object Control Register */
+#define CAN_MO239_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001ADFCu)
+
+/** Alias (User Manual Name) for CAN_MO239_STAT.
+* To use register names with standard convension, please use CAN_MO239_STAT.
+*/
+#define CAN_MOSTAT239 (CAN_MO239_STAT)
+
+/** \brief 12EC, Message Object Acceptance Mask Register */
+#define CAN_MO23_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00192ECu)
+
+/** Alias (User Manual Name) for CAN_MO23_AMR.
+* To use register names with standard convension, please use CAN_MO23_AMR.
+*/
+#define CAN_MOAMR23 (CAN_MO23_AMR)
+
+/** \brief 12F8, Message Object Arbitration Register */
+#define CAN_MO23_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00192F8u)
+
+/** Alias (User Manual Name) for CAN_MO23_AR.
+* To use register names with standard convension, please use CAN_MO23_AR.
+*/
+#define CAN_MOAR23 (CAN_MO23_AR)
+
+/** \brief 12FC, Message Object Control Register */
+#define CAN_MO23_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00192FCu)
+
+/** Alias (User Manual Name) for CAN_MO23_CTR.
+* To use register names with standard convension, please use CAN_MO23_CTR.
+*/
+#define CAN_MOCTR23 (CAN_MO23_CTR)
+
+/** \brief 12F4, Message Object Data Register High */
+#define CAN_MO23_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00192F4u)
+
+/** Alias (User Manual Name) for CAN_MO23_DATAH.
+* To use register names with standard convension, please use CAN_MO23_DATAH.
+*/
+#define CAN_MODATAH23 (CAN_MO23_DATAH)
+
+/** \brief 12F0, Message Object Data Register Low */
+#define CAN_MO23_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00192F0u)
+
+/** Alias (User Manual Name) for CAN_MO23_DATAL.
+* To use register names with standard convension, please use CAN_MO23_DATAL.
+*/
+#define CAN_MODATAL23 (CAN_MO23_DATAL)
+
+/** \brief 12E0, Message Object Function Control Register */
+#define CAN_MO23_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00192E0u)
+
+/** Alias (User Manual Name) for CAN_MO23_EDATA0.
+* To use register names with standard convension, please use CAN_MO23_EDATA0.
+*/
+#define CAN_EMO23DATA0 (CAN_MO23_EDATA0)
+
+/** \brief 12E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO23_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00192E4u)
+
+/** Alias (User Manual Name) for CAN_MO23_EDATA1.
+* To use register names with standard convension, please use CAN_MO23_EDATA1.
+*/
+#define CAN_EMO23DATA1 (CAN_MO23_EDATA1)
+
+/** \brief 12E8, Message Object Interrupt Pointer Register */
+#define CAN_MO23_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00192E8u)
+
+/** Alias (User Manual Name) for CAN_MO23_EDATA2.
+* To use register names with standard convension, please use CAN_MO23_EDATA2.
+*/
+#define CAN_EMO23DATA2 (CAN_MO23_EDATA2)
+
+/** \brief 12EC, Message Object Acceptance Mask Register */
+#define CAN_MO23_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00192ECu)
+
+/** Alias (User Manual Name) for CAN_MO23_EDATA3.
+* To use register names with standard convension, please use CAN_MO23_EDATA3.
+*/
+#define CAN_EMO23DATA3 (CAN_MO23_EDATA3)
+
+/** \brief 12F0, Message Object Data Register Low */
+#define CAN_MO23_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00192F0u)
+
+/** Alias (User Manual Name) for CAN_MO23_EDATA4.
+* To use register names with standard convension, please use CAN_MO23_EDATA4.
+*/
+#define CAN_EMO23DATA4 (CAN_MO23_EDATA4)
+
+/** \brief 12F4, Message Object Data Register High */
+#define CAN_MO23_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00192F4u)
+
+/** Alias (User Manual Name) for CAN_MO23_EDATA5.
+* To use register names with standard convension, please use CAN_MO23_EDATA5.
+*/
+#define CAN_EMO23DATA5 (CAN_MO23_EDATA5)
+
+/** \brief 12F8, Message Object Arbitration Register */
+#define CAN_MO23_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00192F8u)
+
+/** Alias (User Manual Name) for CAN_MO23_EDATA6.
+* To use register names with standard convension, please use CAN_MO23_EDATA6.
+*/
+#define CAN_EMO23DATA6 (CAN_MO23_EDATA6)
+
+/** \brief 12E0, Message Object Function Control Register */
+#define CAN_MO23_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00192E0u)
+
+/** Alias (User Manual Name) for CAN_MO23_FCR.
+* To use register names with standard convension, please use CAN_MO23_FCR.
+*/
+#define CAN_MOFCR23 (CAN_MO23_FCR)
+
+/** \brief 12E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO23_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00192E4u)
+
+/** Alias (User Manual Name) for CAN_MO23_FGPR.
+* To use register names with standard convension, please use CAN_MO23_FGPR.
+*/
+#define CAN_MOFGPR23 (CAN_MO23_FGPR)
+
+/** \brief 12E8, Message Object Interrupt Pointer Register */
+#define CAN_MO23_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00192E8u)
+
+/** Alias (User Manual Name) for CAN_MO23_IPR.
+* To use register names with standard convension, please use CAN_MO23_IPR.
+*/
+#define CAN_MOIPR23 (CAN_MO23_IPR)
+
+/** \brief 12FC, Message Object Control Register */
+#define CAN_MO23_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00192FCu)
+
+/** Alias (User Manual Name) for CAN_MO23_STAT.
+* To use register names with standard convension, please use CAN_MO23_STAT.
+*/
+#define CAN_MOSTAT23 (CAN_MO23_STAT)
+
+/** \brief 2E0C, Message Object Acceptance Mask Register */
+#define CAN_MO240_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AE0Cu)
+
+/** Alias (User Manual Name) for CAN_MO240_AMR.
+* To use register names with standard convension, please use CAN_MO240_AMR.
+*/
+#define CAN_MOAMR240 (CAN_MO240_AMR)
+
+/** \brief 2E18, Message Object Arbitration Register */
+#define CAN_MO240_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AE18u)
+
+/** Alias (User Manual Name) for CAN_MO240_AR.
+* To use register names with standard convension, please use CAN_MO240_AR.
+*/
+#define CAN_MOAR240 (CAN_MO240_AR)
+
+/** \brief 2E1C, Message Object Control Register */
+#define CAN_MO240_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AE1Cu)
+
+/** Alias (User Manual Name) for CAN_MO240_CTR.
+* To use register names with standard convension, please use CAN_MO240_CTR.
+*/
+#define CAN_MOCTR240 (CAN_MO240_CTR)
+
+/** \brief 2E14, Message Object Data Register High */
+#define CAN_MO240_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AE14u)
+
+/** Alias (User Manual Name) for CAN_MO240_DATAH.
+* To use register names with standard convension, please use CAN_MO240_DATAH.
+*/
+#define CAN_MODATAH240 (CAN_MO240_DATAH)
+
+/** \brief 2E10, Message Object Data Register Low */
+#define CAN_MO240_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AE10u)
+
+/** Alias (User Manual Name) for CAN_MO240_DATAL.
+* To use register names with standard convension, please use CAN_MO240_DATAL.
+*/
+#define CAN_MODATAL240 (CAN_MO240_DATAL)
+
+/** \brief 2E00, Message Object Function Control Register */
+#define CAN_MO240_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AE00u)
+
+/** Alias (User Manual Name) for CAN_MO240_EDATA0.
+* To use register names with standard convension, please use CAN_MO240_EDATA0.
+*/
+#define CAN_EMO240DATA0 (CAN_MO240_EDATA0)
+
+/** \brief 2E04, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO240_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AE04u)
+
+/** Alias (User Manual Name) for CAN_MO240_EDATA1.
+* To use register names with standard convension, please use CAN_MO240_EDATA1.
+*/
+#define CAN_EMO240DATA1 (CAN_MO240_EDATA1)
+
+/** \brief 2E08, Message Object Interrupt Pointer Register */
+#define CAN_MO240_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AE08u)
+
+/** Alias (User Manual Name) for CAN_MO240_EDATA2.
+* To use register names with standard convension, please use CAN_MO240_EDATA2.
+*/
+#define CAN_EMO240DATA2 (CAN_MO240_EDATA2)
+
+/** \brief 2E0C, Message Object Acceptance Mask Register */
+#define CAN_MO240_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AE0Cu)
+
+/** Alias (User Manual Name) for CAN_MO240_EDATA3.
+* To use register names with standard convension, please use CAN_MO240_EDATA3.
+*/
+#define CAN_EMO240DATA3 (CAN_MO240_EDATA3)
+
+/** \brief 2E10, Message Object Data Register Low */
+#define CAN_MO240_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AE10u)
+
+/** Alias (User Manual Name) for CAN_MO240_EDATA4.
+* To use register names with standard convension, please use CAN_MO240_EDATA4.
+*/
+#define CAN_EMO240DATA4 (CAN_MO240_EDATA4)
+
+/** \brief 2E14, Message Object Data Register High */
+#define CAN_MO240_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AE14u)
+
+/** Alias (User Manual Name) for CAN_MO240_EDATA5.
+* To use register names with standard convension, please use CAN_MO240_EDATA5.
+*/
+#define CAN_EMO240DATA5 (CAN_MO240_EDATA5)
+
+/** \brief 2E18, Message Object Arbitration Register */
+#define CAN_MO240_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AE18u)
+
+/** Alias (User Manual Name) for CAN_MO240_EDATA6.
+* To use register names with standard convension, please use CAN_MO240_EDATA6.
+*/
+#define CAN_EMO240DATA6 (CAN_MO240_EDATA6)
+
+/** \brief 2E00, Message Object Function Control Register */
+#define CAN_MO240_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AE00u)
+
+/** Alias (User Manual Name) for CAN_MO240_FCR.
+* To use register names with standard convension, please use CAN_MO240_FCR.
+*/
+#define CAN_MOFCR240 (CAN_MO240_FCR)
+
+/** \brief 2E04, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO240_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AE04u)
+
+/** Alias (User Manual Name) for CAN_MO240_FGPR.
+* To use register names with standard convension, please use CAN_MO240_FGPR.
+*/
+#define CAN_MOFGPR240 (CAN_MO240_FGPR)
+
+/** \brief 2E08, Message Object Interrupt Pointer Register */
+#define CAN_MO240_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AE08u)
+
+/** Alias (User Manual Name) for CAN_MO240_IPR.
+* To use register names with standard convension, please use CAN_MO240_IPR.
+*/
+#define CAN_MOIPR240 (CAN_MO240_IPR)
+
+/** \brief 2E1C, Message Object Control Register */
+#define CAN_MO240_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AE1Cu)
+
+/** Alias (User Manual Name) for CAN_MO240_STAT.
+* To use register names with standard convension, please use CAN_MO240_STAT.
+*/
+#define CAN_MOSTAT240 (CAN_MO240_STAT)
+
+/** \brief 2E2C, Message Object Acceptance Mask Register */
+#define CAN_MO241_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AE2Cu)
+
+/** Alias (User Manual Name) for CAN_MO241_AMR.
+* To use register names with standard convension, please use CAN_MO241_AMR.
+*/
+#define CAN_MOAMR241 (CAN_MO241_AMR)
+
+/** \brief 2E38, Message Object Arbitration Register */
+#define CAN_MO241_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AE38u)
+
+/** Alias (User Manual Name) for CAN_MO241_AR.
+* To use register names with standard convension, please use CAN_MO241_AR.
+*/
+#define CAN_MOAR241 (CAN_MO241_AR)
+
+/** \brief 2E3C, Message Object Control Register */
+#define CAN_MO241_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AE3Cu)
+
+/** Alias (User Manual Name) for CAN_MO241_CTR.
+* To use register names with standard convension, please use CAN_MO241_CTR.
+*/
+#define CAN_MOCTR241 (CAN_MO241_CTR)
+
+/** \brief 2E34, Message Object Data Register High */
+#define CAN_MO241_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AE34u)
+
+/** Alias (User Manual Name) for CAN_MO241_DATAH.
+* To use register names with standard convension, please use CAN_MO241_DATAH.
+*/
+#define CAN_MODATAH241 (CAN_MO241_DATAH)
+
+/** \brief 2E30, Message Object Data Register Low */
+#define CAN_MO241_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AE30u)
+
+/** Alias (User Manual Name) for CAN_MO241_DATAL.
+* To use register names with standard convension, please use CAN_MO241_DATAL.
+*/
+#define CAN_MODATAL241 (CAN_MO241_DATAL)
+
+/** \brief 2E20, Message Object Function Control Register */
+#define CAN_MO241_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AE20u)
+
+/** Alias (User Manual Name) for CAN_MO241_EDATA0.
+* To use register names with standard convension, please use CAN_MO241_EDATA0.
+*/
+#define CAN_EMO241DATA0 (CAN_MO241_EDATA0)
+
+/** \brief 2E24, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO241_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AE24u)
+
+/** Alias (User Manual Name) for CAN_MO241_EDATA1.
+* To use register names with standard convension, please use CAN_MO241_EDATA1.
+*/
+#define CAN_EMO241DATA1 (CAN_MO241_EDATA1)
+
+/** \brief 2E28, Message Object Interrupt Pointer Register */
+#define CAN_MO241_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AE28u)
+
+/** Alias (User Manual Name) for CAN_MO241_EDATA2.
+* To use register names with standard convension, please use CAN_MO241_EDATA2.
+*/
+#define CAN_EMO241DATA2 (CAN_MO241_EDATA2)
+
+/** \brief 2E2C, Message Object Acceptance Mask Register */
+#define CAN_MO241_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AE2Cu)
+
+/** Alias (User Manual Name) for CAN_MO241_EDATA3.
+* To use register names with standard convension, please use CAN_MO241_EDATA3.
+*/
+#define CAN_EMO241DATA3 (CAN_MO241_EDATA3)
+
+/** \brief 2E30, Message Object Data Register Low */
+#define CAN_MO241_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AE30u)
+
+/** Alias (User Manual Name) for CAN_MO241_EDATA4.
+* To use register names with standard convension, please use CAN_MO241_EDATA4.
+*/
+#define CAN_EMO241DATA4 (CAN_MO241_EDATA4)
+
+/** \brief 2E34, Message Object Data Register High */
+#define CAN_MO241_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AE34u)
+
+/** Alias (User Manual Name) for CAN_MO241_EDATA5.
+* To use register names with standard convension, please use CAN_MO241_EDATA5.
+*/
+#define CAN_EMO241DATA5 (CAN_MO241_EDATA5)
+
+/** \brief 2E38, Message Object Arbitration Register */
+#define CAN_MO241_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AE38u)
+
+/** Alias (User Manual Name) for CAN_MO241_EDATA6.
+* To use register names with standard convension, please use CAN_MO241_EDATA6.
+*/
+#define CAN_EMO241DATA6 (CAN_MO241_EDATA6)
+
+/** \brief 2E20, Message Object Function Control Register */
+#define CAN_MO241_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AE20u)
+
+/** Alias (User Manual Name) for CAN_MO241_FCR.
+* To use register names with standard convension, please use CAN_MO241_FCR.
+*/
+#define CAN_MOFCR241 (CAN_MO241_FCR)
+
+/** \brief 2E24, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO241_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AE24u)
+
+/** Alias (User Manual Name) for CAN_MO241_FGPR.
+* To use register names with standard convension, please use CAN_MO241_FGPR.
+*/
+#define CAN_MOFGPR241 (CAN_MO241_FGPR)
+
+/** \brief 2E28, Message Object Interrupt Pointer Register */
+#define CAN_MO241_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AE28u)
+
+/** Alias (User Manual Name) for CAN_MO241_IPR.
+* To use register names with standard convension, please use CAN_MO241_IPR.
+*/
+#define CAN_MOIPR241 (CAN_MO241_IPR)
+
+/** \brief 2E3C, Message Object Control Register */
+#define CAN_MO241_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AE3Cu)
+
+/** Alias (User Manual Name) for CAN_MO241_STAT.
+* To use register names with standard convension, please use CAN_MO241_STAT.
+*/
+#define CAN_MOSTAT241 (CAN_MO241_STAT)
+
+/** \brief 2E4C, Message Object Acceptance Mask Register */
+#define CAN_MO242_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AE4Cu)
+
+/** Alias (User Manual Name) for CAN_MO242_AMR.
+* To use register names with standard convension, please use CAN_MO242_AMR.
+*/
+#define CAN_MOAMR242 (CAN_MO242_AMR)
+
+/** \brief 2E58, Message Object Arbitration Register */
+#define CAN_MO242_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AE58u)
+
+/** Alias (User Manual Name) for CAN_MO242_AR.
+* To use register names with standard convension, please use CAN_MO242_AR.
+*/
+#define CAN_MOAR242 (CAN_MO242_AR)
+
+/** \brief 2E5C, Message Object Control Register */
+#define CAN_MO242_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AE5Cu)
+
+/** Alias (User Manual Name) for CAN_MO242_CTR.
+* To use register names with standard convension, please use CAN_MO242_CTR.
+*/
+#define CAN_MOCTR242 (CAN_MO242_CTR)
+
+/** \brief 2E54, Message Object Data Register High */
+#define CAN_MO242_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AE54u)
+
+/** Alias (User Manual Name) for CAN_MO242_DATAH.
+* To use register names with standard convension, please use CAN_MO242_DATAH.
+*/
+#define CAN_MODATAH242 (CAN_MO242_DATAH)
+
+/** \brief 2E50, Message Object Data Register Low */
+#define CAN_MO242_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AE50u)
+
+/** Alias (User Manual Name) for CAN_MO242_DATAL.
+* To use register names with standard convension, please use CAN_MO242_DATAL.
+*/
+#define CAN_MODATAL242 (CAN_MO242_DATAL)
+
+/** \brief 2E40, Message Object Function Control Register */
+#define CAN_MO242_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AE40u)
+
+/** Alias (User Manual Name) for CAN_MO242_EDATA0.
+* To use register names with standard convension, please use CAN_MO242_EDATA0.
+*/
+#define CAN_EMO242DATA0 (CAN_MO242_EDATA0)
+
+/** \brief 2E44, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO242_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AE44u)
+
+/** Alias (User Manual Name) for CAN_MO242_EDATA1.
+* To use register names with standard convension, please use CAN_MO242_EDATA1.
+*/
+#define CAN_EMO242DATA1 (CAN_MO242_EDATA1)
+
+/** \brief 2E48, Message Object Interrupt Pointer Register */
+#define CAN_MO242_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AE48u)
+
+/** Alias (User Manual Name) for CAN_MO242_EDATA2.
+* To use register names with standard convension, please use CAN_MO242_EDATA2.
+*/
+#define CAN_EMO242DATA2 (CAN_MO242_EDATA2)
+
+/** \brief 2E4C, Message Object Acceptance Mask Register */
+#define CAN_MO242_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AE4Cu)
+
+/** Alias (User Manual Name) for CAN_MO242_EDATA3.
+* To use register names with standard convension, please use CAN_MO242_EDATA3.
+*/
+#define CAN_EMO242DATA3 (CAN_MO242_EDATA3)
+
+/** \brief 2E50, Message Object Data Register Low */
+#define CAN_MO242_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AE50u)
+
+/** Alias (User Manual Name) for CAN_MO242_EDATA4.
+* To use register names with standard convension, please use CAN_MO242_EDATA4.
+*/
+#define CAN_EMO242DATA4 (CAN_MO242_EDATA4)
+
+/** \brief 2E54, Message Object Data Register High */
+#define CAN_MO242_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AE54u)
+
+/** Alias (User Manual Name) for CAN_MO242_EDATA5.
+* To use register names with standard convension, please use CAN_MO242_EDATA5.
+*/
+#define CAN_EMO242DATA5 (CAN_MO242_EDATA5)
+
+/** \brief 2E58, Message Object Arbitration Register */
+#define CAN_MO242_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AE58u)
+
+/** Alias (User Manual Name) for CAN_MO242_EDATA6.
+* To use register names with standard convension, please use CAN_MO242_EDATA6.
+*/
+#define CAN_EMO242DATA6 (CAN_MO242_EDATA6)
+
+/** \brief 2E40, Message Object Function Control Register */
+#define CAN_MO242_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AE40u)
+
+/** Alias (User Manual Name) for CAN_MO242_FCR.
+* To use register names with standard convension, please use CAN_MO242_FCR.
+*/
+#define CAN_MOFCR242 (CAN_MO242_FCR)
+
+/** \brief 2E44, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO242_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AE44u)
+
+/** Alias (User Manual Name) for CAN_MO242_FGPR.
+* To use register names with standard convension, please use CAN_MO242_FGPR.
+*/
+#define CAN_MOFGPR242 (CAN_MO242_FGPR)
+
+/** \brief 2E48, Message Object Interrupt Pointer Register */
+#define CAN_MO242_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AE48u)
+
+/** Alias (User Manual Name) for CAN_MO242_IPR.
+* To use register names with standard convension, please use CAN_MO242_IPR.
+*/
+#define CAN_MOIPR242 (CAN_MO242_IPR)
+
+/** \brief 2E5C, Message Object Control Register */
+#define CAN_MO242_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AE5Cu)
+
+/** Alias (User Manual Name) for CAN_MO242_STAT.
+* To use register names with standard convension, please use CAN_MO242_STAT.
+*/
+#define CAN_MOSTAT242 (CAN_MO242_STAT)
+
+/** \brief 2E6C, Message Object Acceptance Mask Register */
+#define CAN_MO243_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AE6Cu)
+
+/** Alias (User Manual Name) for CAN_MO243_AMR.
+* To use register names with standard convension, please use CAN_MO243_AMR.
+*/
+#define CAN_MOAMR243 (CAN_MO243_AMR)
+
+/** \brief 2E78, Message Object Arbitration Register */
+#define CAN_MO243_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AE78u)
+
+/** Alias (User Manual Name) for CAN_MO243_AR.
+* To use register names with standard convension, please use CAN_MO243_AR.
+*/
+#define CAN_MOAR243 (CAN_MO243_AR)
+
+/** \brief 2E7C, Message Object Control Register */
+#define CAN_MO243_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AE7Cu)
+
+/** Alias (User Manual Name) for CAN_MO243_CTR.
+* To use register names with standard convension, please use CAN_MO243_CTR.
+*/
+#define CAN_MOCTR243 (CAN_MO243_CTR)
+
+/** \brief 2E74, Message Object Data Register High */
+#define CAN_MO243_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AE74u)
+
+/** Alias (User Manual Name) for CAN_MO243_DATAH.
+* To use register names with standard convension, please use CAN_MO243_DATAH.
+*/
+#define CAN_MODATAH243 (CAN_MO243_DATAH)
+
+/** \brief 2E70, Message Object Data Register Low */
+#define CAN_MO243_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AE70u)
+
+/** Alias (User Manual Name) for CAN_MO243_DATAL.
+* To use register names with standard convension, please use CAN_MO243_DATAL.
+*/
+#define CAN_MODATAL243 (CAN_MO243_DATAL)
+
+/** \brief 2E60, Message Object Function Control Register */
+#define CAN_MO243_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AE60u)
+
+/** Alias (User Manual Name) for CAN_MO243_EDATA0.
+* To use register names with standard convension, please use CAN_MO243_EDATA0.
+*/
+#define CAN_EMO243DATA0 (CAN_MO243_EDATA0)
+
+/** \brief 2E64, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO243_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AE64u)
+
+/** Alias (User Manual Name) for CAN_MO243_EDATA1.
+* To use register names with standard convension, please use CAN_MO243_EDATA1.
+*/
+#define CAN_EMO243DATA1 (CAN_MO243_EDATA1)
+
+/** \brief 2E68, Message Object Interrupt Pointer Register */
+#define CAN_MO243_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AE68u)
+
+/** Alias (User Manual Name) for CAN_MO243_EDATA2.
+* To use register names with standard convension, please use CAN_MO243_EDATA2.
+*/
+#define CAN_EMO243DATA2 (CAN_MO243_EDATA2)
+
+/** \brief 2E6C, Message Object Acceptance Mask Register */
+#define CAN_MO243_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AE6Cu)
+
+/** Alias (User Manual Name) for CAN_MO243_EDATA3.
+* To use register names with standard convension, please use CAN_MO243_EDATA3.
+*/
+#define CAN_EMO243DATA3 (CAN_MO243_EDATA3)
+
+/** \brief 2E70, Message Object Data Register Low */
+#define CAN_MO243_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AE70u)
+
+/** Alias (User Manual Name) for CAN_MO243_EDATA4.
+* To use register names with standard convension, please use CAN_MO243_EDATA4.
+*/
+#define CAN_EMO243DATA4 (CAN_MO243_EDATA4)
+
+/** \brief 2E74, Message Object Data Register High */
+#define CAN_MO243_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AE74u)
+
+/** Alias (User Manual Name) for CAN_MO243_EDATA5.
+* To use register names with standard convension, please use CAN_MO243_EDATA5.
+*/
+#define CAN_EMO243DATA5 (CAN_MO243_EDATA5)
+
+/** \brief 2E78, Message Object Arbitration Register */
+#define CAN_MO243_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AE78u)
+
+/** Alias (User Manual Name) for CAN_MO243_EDATA6.
+* To use register names with standard convension, please use CAN_MO243_EDATA6.
+*/
+#define CAN_EMO243DATA6 (CAN_MO243_EDATA6)
+
+/** \brief 2E60, Message Object Function Control Register */
+#define CAN_MO243_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AE60u)
+
+/** Alias (User Manual Name) for CAN_MO243_FCR.
+* To use register names with standard convension, please use CAN_MO243_FCR.
+*/
+#define CAN_MOFCR243 (CAN_MO243_FCR)
+
+/** \brief 2E64, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO243_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AE64u)
+
+/** Alias (User Manual Name) for CAN_MO243_FGPR.
+* To use register names with standard convension, please use CAN_MO243_FGPR.
+*/
+#define CAN_MOFGPR243 (CAN_MO243_FGPR)
+
+/** \brief 2E68, Message Object Interrupt Pointer Register */
+#define CAN_MO243_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AE68u)
+
+/** Alias (User Manual Name) for CAN_MO243_IPR.
+* To use register names with standard convension, please use CAN_MO243_IPR.
+*/
+#define CAN_MOIPR243 (CAN_MO243_IPR)
+
+/** \brief 2E7C, Message Object Control Register */
+#define CAN_MO243_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AE7Cu)
+
+/** Alias (User Manual Name) for CAN_MO243_STAT.
+* To use register names with standard convension, please use CAN_MO243_STAT.
+*/
+#define CAN_MOSTAT243 (CAN_MO243_STAT)
+
+/** \brief 2E8C, Message Object Acceptance Mask Register */
+#define CAN_MO244_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AE8Cu)
+
+/** Alias (User Manual Name) for CAN_MO244_AMR.
+* To use register names with standard convension, please use CAN_MO244_AMR.
+*/
+#define CAN_MOAMR244 (CAN_MO244_AMR)
+
+/** \brief 2E98, Message Object Arbitration Register */
+#define CAN_MO244_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AE98u)
+
+/** Alias (User Manual Name) for CAN_MO244_AR.
+* To use register names with standard convension, please use CAN_MO244_AR.
+*/
+#define CAN_MOAR244 (CAN_MO244_AR)
+
+/** \brief 2E9C, Message Object Control Register */
+#define CAN_MO244_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AE9Cu)
+
+/** Alias (User Manual Name) for CAN_MO244_CTR.
+* To use register names with standard convension, please use CAN_MO244_CTR.
+*/
+#define CAN_MOCTR244 (CAN_MO244_CTR)
+
+/** \brief 2E94, Message Object Data Register High */
+#define CAN_MO244_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AE94u)
+
+/** Alias (User Manual Name) for CAN_MO244_DATAH.
+* To use register names with standard convension, please use CAN_MO244_DATAH.
+*/
+#define CAN_MODATAH244 (CAN_MO244_DATAH)
+
+/** \brief 2E90, Message Object Data Register Low */
+#define CAN_MO244_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AE90u)
+
+/** Alias (User Manual Name) for CAN_MO244_DATAL.
+* To use register names with standard convension, please use CAN_MO244_DATAL.
+*/
+#define CAN_MODATAL244 (CAN_MO244_DATAL)
+
+/** \brief 2E80, Message Object Function Control Register */
+#define CAN_MO244_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AE80u)
+
+/** Alias (User Manual Name) for CAN_MO244_EDATA0.
+* To use register names with standard convension, please use CAN_MO244_EDATA0.
+*/
+#define CAN_EMO244DATA0 (CAN_MO244_EDATA0)
+
+/** \brief 2E84, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO244_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AE84u)
+
+/** Alias (User Manual Name) for CAN_MO244_EDATA1.
+* To use register names with standard convension, please use CAN_MO244_EDATA1.
+*/
+#define CAN_EMO244DATA1 (CAN_MO244_EDATA1)
+
+/** \brief 2E88, Message Object Interrupt Pointer Register */
+#define CAN_MO244_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AE88u)
+
+/** Alias (User Manual Name) for CAN_MO244_EDATA2.
+* To use register names with standard convension, please use CAN_MO244_EDATA2.
+*/
+#define CAN_EMO244DATA2 (CAN_MO244_EDATA2)
+
+/** \brief 2E8C, Message Object Acceptance Mask Register */
+#define CAN_MO244_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AE8Cu)
+
+/** Alias (User Manual Name) for CAN_MO244_EDATA3.
+* To use register names with standard convension, please use CAN_MO244_EDATA3.
+*/
+#define CAN_EMO244DATA3 (CAN_MO244_EDATA3)
+
+/** \brief 2E90, Message Object Data Register Low */
+#define CAN_MO244_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AE90u)
+
+/** Alias (User Manual Name) for CAN_MO244_EDATA4.
+* To use register names with standard convension, please use CAN_MO244_EDATA4.
+*/
+#define CAN_EMO244DATA4 (CAN_MO244_EDATA4)
+
+/** \brief 2E94, Message Object Data Register High */
+#define CAN_MO244_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AE94u)
+
+/** Alias (User Manual Name) for CAN_MO244_EDATA5.
+* To use register names with standard convension, please use CAN_MO244_EDATA5.
+*/
+#define CAN_EMO244DATA5 (CAN_MO244_EDATA5)
+
+/** \brief 2E98, Message Object Arbitration Register */
+#define CAN_MO244_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AE98u)
+
+/** Alias (User Manual Name) for CAN_MO244_EDATA6.
+* To use register names with standard convension, please use CAN_MO244_EDATA6.
+*/
+#define CAN_EMO244DATA6 (CAN_MO244_EDATA6)
+
+/** \brief 2E80, Message Object Function Control Register */
+#define CAN_MO244_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AE80u)
+
+/** Alias (User Manual Name) for CAN_MO244_FCR.
+* To use register names with standard convension, please use CAN_MO244_FCR.
+*/
+#define CAN_MOFCR244 (CAN_MO244_FCR)
+
+/** \brief 2E84, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO244_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AE84u)
+
+/** Alias (User Manual Name) for CAN_MO244_FGPR.
+* To use register names with standard convension, please use CAN_MO244_FGPR.
+*/
+#define CAN_MOFGPR244 (CAN_MO244_FGPR)
+
+/** \brief 2E88, Message Object Interrupt Pointer Register */
+#define CAN_MO244_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AE88u)
+
+/** Alias (User Manual Name) for CAN_MO244_IPR.
+* To use register names with standard convension, please use CAN_MO244_IPR.
+*/
+#define CAN_MOIPR244 (CAN_MO244_IPR)
+
+/** \brief 2E9C, Message Object Control Register */
+#define CAN_MO244_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AE9Cu)
+
+/** Alias (User Manual Name) for CAN_MO244_STAT.
+* To use register names with standard convension, please use CAN_MO244_STAT.
+*/
+#define CAN_MOSTAT244 (CAN_MO244_STAT)
+
+/** \brief 2EAC, Message Object Acceptance Mask Register */
+#define CAN_MO245_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AEACu)
+
+/** Alias (User Manual Name) for CAN_MO245_AMR.
+* To use register names with standard convension, please use CAN_MO245_AMR.
+*/
+#define CAN_MOAMR245 (CAN_MO245_AMR)
+
+/** \brief 2EB8, Message Object Arbitration Register */
+#define CAN_MO245_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AEB8u)
+
+/** Alias (User Manual Name) for CAN_MO245_AR.
+* To use register names with standard convension, please use CAN_MO245_AR.
+*/
+#define CAN_MOAR245 (CAN_MO245_AR)
+
+/** \brief 2EBC, Message Object Control Register */
+#define CAN_MO245_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AEBCu)
+
+/** Alias (User Manual Name) for CAN_MO245_CTR.
+* To use register names with standard convension, please use CAN_MO245_CTR.
+*/
+#define CAN_MOCTR245 (CAN_MO245_CTR)
+
+/** \brief 2EB4, Message Object Data Register High */
+#define CAN_MO245_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AEB4u)
+
+/** Alias (User Manual Name) for CAN_MO245_DATAH.
+* To use register names with standard convension, please use CAN_MO245_DATAH.
+*/
+#define CAN_MODATAH245 (CAN_MO245_DATAH)
+
+/** \brief 2EB0, Message Object Data Register Low */
+#define CAN_MO245_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AEB0u)
+
+/** Alias (User Manual Name) for CAN_MO245_DATAL.
+* To use register names with standard convension, please use CAN_MO245_DATAL.
+*/
+#define CAN_MODATAL245 (CAN_MO245_DATAL)
+
+/** \brief 2EA0, Message Object Function Control Register */
+#define CAN_MO245_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AEA0u)
+
+/** Alias (User Manual Name) for CAN_MO245_EDATA0.
+* To use register names with standard convension, please use CAN_MO245_EDATA0.
+*/
+#define CAN_EMO245DATA0 (CAN_MO245_EDATA0)
+
+/** \brief 2EA4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO245_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AEA4u)
+
+/** Alias (User Manual Name) for CAN_MO245_EDATA1.
+* To use register names with standard convension, please use CAN_MO245_EDATA1.
+*/
+#define CAN_EMO245DATA1 (CAN_MO245_EDATA1)
+
+/** \brief 2EA8, Message Object Interrupt Pointer Register */
+#define CAN_MO245_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AEA8u)
+
+/** Alias (User Manual Name) for CAN_MO245_EDATA2.
+* To use register names with standard convension, please use CAN_MO245_EDATA2.
+*/
+#define CAN_EMO245DATA2 (CAN_MO245_EDATA2)
+
+/** \brief 2EAC, Message Object Acceptance Mask Register */
+#define CAN_MO245_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AEACu)
+
+/** Alias (User Manual Name) for CAN_MO245_EDATA3.
+* To use register names with standard convension, please use CAN_MO245_EDATA3.
+*/
+#define CAN_EMO245DATA3 (CAN_MO245_EDATA3)
+
+/** \brief 2EB0, Message Object Data Register Low */
+#define CAN_MO245_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AEB0u)
+
+/** Alias (User Manual Name) for CAN_MO245_EDATA4.
+* To use register names with standard convension, please use CAN_MO245_EDATA4.
+*/
+#define CAN_EMO245DATA4 (CAN_MO245_EDATA4)
+
+/** \brief 2EB4, Message Object Data Register High */
+#define CAN_MO245_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AEB4u)
+
+/** Alias (User Manual Name) for CAN_MO245_EDATA5.
+* To use register names with standard convension, please use CAN_MO245_EDATA5.
+*/
+#define CAN_EMO245DATA5 (CAN_MO245_EDATA5)
+
+/** \brief 2EB8, Message Object Arbitration Register */
+#define CAN_MO245_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AEB8u)
+
+/** Alias (User Manual Name) for CAN_MO245_EDATA6.
+* To use register names with standard convension, please use CAN_MO245_EDATA6.
+*/
+#define CAN_EMO245DATA6 (CAN_MO245_EDATA6)
+
+/** \brief 2EA0, Message Object Function Control Register */
+#define CAN_MO245_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AEA0u)
+
+/** Alias (User Manual Name) for CAN_MO245_FCR.
+* To use register names with standard convension, please use CAN_MO245_FCR.
+*/
+#define CAN_MOFCR245 (CAN_MO245_FCR)
+
+/** \brief 2EA4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO245_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AEA4u)
+
+/** Alias (User Manual Name) for CAN_MO245_FGPR.
+* To use register names with standard convension, please use CAN_MO245_FGPR.
+*/
+#define CAN_MOFGPR245 (CAN_MO245_FGPR)
+
+/** \brief 2EA8, Message Object Interrupt Pointer Register */
+#define CAN_MO245_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AEA8u)
+
+/** Alias (User Manual Name) for CAN_MO245_IPR.
+* To use register names with standard convension, please use CAN_MO245_IPR.
+*/
+#define CAN_MOIPR245 (CAN_MO245_IPR)
+
+/** \brief 2EBC, Message Object Control Register */
+#define CAN_MO245_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AEBCu)
+
+/** Alias (User Manual Name) for CAN_MO245_STAT.
+* To use register names with standard convension, please use CAN_MO245_STAT.
+*/
+#define CAN_MOSTAT245 (CAN_MO245_STAT)
+
+/** \brief 2ECC, Message Object Acceptance Mask Register */
+#define CAN_MO246_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AECCu)
+
+/** Alias (User Manual Name) for CAN_MO246_AMR.
+* To use register names with standard convension, please use CAN_MO246_AMR.
+*/
+#define CAN_MOAMR246 (CAN_MO246_AMR)
+
+/** \brief 2ED8, Message Object Arbitration Register */
+#define CAN_MO246_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AED8u)
+
+/** Alias (User Manual Name) for CAN_MO246_AR.
+* To use register names with standard convension, please use CAN_MO246_AR.
+*/
+#define CAN_MOAR246 (CAN_MO246_AR)
+
+/** \brief 2EDC, Message Object Control Register */
+#define CAN_MO246_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AEDCu)
+
+/** Alias (User Manual Name) for CAN_MO246_CTR.
+* To use register names with standard convension, please use CAN_MO246_CTR.
+*/
+#define CAN_MOCTR246 (CAN_MO246_CTR)
+
+/** \brief 2ED4, Message Object Data Register High */
+#define CAN_MO246_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AED4u)
+
+/** Alias (User Manual Name) for CAN_MO246_DATAH.
+* To use register names with standard convension, please use CAN_MO246_DATAH.
+*/
+#define CAN_MODATAH246 (CAN_MO246_DATAH)
+
+/** \brief 2ED0, Message Object Data Register Low */
+#define CAN_MO246_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AED0u)
+
+/** Alias (User Manual Name) for CAN_MO246_DATAL.
+* To use register names with standard convension, please use CAN_MO246_DATAL.
+*/
+#define CAN_MODATAL246 (CAN_MO246_DATAL)
+
+/** \brief 2EC0, Message Object Function Control Register */
+#define CAN_MO246_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AEC0u)
+
+/** Alias (User Manual Name) for CAN_MO246_EDATA0.
+* To use register names with standard convension, please use CAN_MO246_EDATA0.
+*/
+#define CAN_EMO246DATA0 (CAN_MO246_EDATA0)
+
+/** \brief 2EC4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO246_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AEC4u)
+
+/** Alias (User Manual Name) for CAN_MO246_EDATA1.
+* To use register names with standard convension, please use CAN_MO246_EDATA1.
+*/
+#define CAN_EMO246DATA1 (CAN_MO246_EDATA1)
+
+/** \brief 2EC8, Message Object Interrupt Pointer Register */
+#define CAN_MO246_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AEC8u)
+
+/** Alias (User Manual Name) for CAN_MO246_EDATA2.
+* To use register names with standard convension, please use CAN_MO246_EDATA2.
+*/
+#define CAN_EMO246DATA2 (CAN_MO246_EDATA2)
+
+/** \brief 2ECC, Message Object Acceptance Mask Register */
+#define CAN_MO246_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AECCu)
+
+/** Alias (User Manual Name) for CAN_MO246_EDATA3.
+* To use register names with standard convension, please use CAN_MO246_EDATA3.
+*/
+#define CAN_EMO246DATA3 (CAN_MO246_EDATA3)
+
+/** \brief 2ED0, Message Object Data Register Low */
+#define CAN_MO246_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AED0u)
+
+/** Alias (User Manual Name) for CAN_MO246_EDATA4.
+* To use register names with standard convension, please use CAN_MO246_EDATA4.
+*/
+#define CAN_EMO246DATA4 (CAN_MO246_EDATA4)
+
+/** \brief 2ED4, Message Object Data Register High */
+#define CAN_MO246_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AED4u)
+
+/** Alias (User Manual Name) for CAN_MO246_EDATA5.
+* To use register names with standard convension, please use CAN_MO246_EDATA5.
+*/
+#define CAN_EMO246DATA5 (CAN_MO246_EDATA5)
+
+/** \brief 2ED8, Message Object Arbitration Register */
+#define CAN_MO246_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AED8u)
+
+/** Alias (User Manual Name) for CAN_MO246_EDATA6.
+* To use register names with standard convension, please use CAN_MO246_EDATA6.
+*/
+#define CAN_EMO246DATA6 (CAN_MO246_EDATA6)
+
+/** \brief 2EC0, Message Object Function Control Register */
+#define CAN_MO246_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AEC0u)
+
+/** Alias (User Manual Name) for CAN_MO246_FCR.
+* To use register names with standard convension, please use CAN_MO246_FCR.
+*/
+#define CAN_MOFCR246 (CAN_MO246_FCR)
+
+/** \brief 2EC4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO246_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AEC4u)
+
+/** Alias (User Manual Name) for CAN_MO246_FGPR.
+* To use register names with standard convension, please use CAN_MO246_FGPR.
+*/
+#define CAN_MOFGPR246 (CAN_MO246_FGPR)
+
+/** \brief 2EC8, Message Object Interrupt Pointer Register */
+#define CAN_MO246_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AEC8u)
+
+/** Alias (User Manual Name) for CAN_MO246_IPR.
+* To use register names with standard convension, please use CAN_MO246_IPR.
+*/
+#define CAN_MOIPR246 (CAN_MO246_IPR)
+
+/** \brief 2EDC, Message Object Control Register */
+#define CAN_MO246_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AEDCu)
+
+/** Alias (User Manual Name) for CAN_MO246_STAT.
+* To use register names with standard convension, please use CAN_MO246_STAT.
+*/
+#define CAN_MOSTAT246 (CAN_MO246_STAT)
+
+/** \brief 2EEC, Message Object Acceptance Mask Register */
+#define CAN_MO247_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AEECu)
+
+/** Alias (User Manual Name) for CAN_MO247_AMR.
+* To use register names with standard convension, please use CAN_MO247_AMR.
+*/
+#define CAN_MOAMR247 (CAN_MO247_AMR)
+
+/** \brief 2EF8, Message Object Arbitration Register */
+#define CAN_MO247_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AEF8u)
+
+/** Alias (User Manual Name) for CAN_MO247_AR.
+* To use register names with standard convension, please use CAN_MO247_AR.
+*/
+#define CAN_MOAR247 (CAN_MO247_AR)
+
+/** \brief 2EFC, Message Object Control Register */
+#define CAN_MO247_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AEFCu)
+
+/** Alias (User Manual Name) for CAN_MO247_CTR.
+* To use register names with standard convension, please use CAN_MO247_CTR.
+*/
+#define CAN_MOCTR247 (CAN_MO247_CTR)
+
+/** \brief 2EF4, Message Object Data Register High */
+#define CAN_MO247_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AEF4u)
+
+/** Alias (User Manual Name) for CAN_MO247_DATAH.
+* To use register names with standard convension, please use CAN_MO247_DATAH.
+*/
+#define CAN_MODATAH247 (CAN_MO247_DATAH)
+
+/** \brief 2EF0, Message Object Data Register Low */
+#define CAN_MO247_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AEF0u)
+
+/** Alias (User Manual Name) for CAN_MO247_DATAL.
+* To use register names with standard convension, please use CAN_MO247_DATAL.
+*/
+#define CAN_MODATAL247 (CAN_MO247_DATAL)
+
+/** \brief 2EE0, Message Object Function Control Register */
+#define CAN_MO247_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AEE0u)
+
+/** Alias (User Manual Name) for CAN_MO247_EDATA0.
+* To use register names with standard convension, please use CAN_MO247_EDATA0.
+*/
+#define CAN_EMO247DATA0 (CAN_MO247_EDATA0)
+
+/** \brief 2EE4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO247_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AEE4u)
+
+/** Alias (User Manual Name) for CAN_MO247_EDATA1.
+* To use register names with standard convension, please use CAN_MO247_EDATA1.
+*/
+#define CAN_EMO247DATA1 (CAN_MO247_EDATA1)
+
+/** \brief 2EE8, Message Object Interrupt Pointer Register */
+#define CAN_MO247_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AEE8u)
+
+/** Alias (User Manual Name) for CAN_MO247_EDATA2.
+* To use register names with standard convension, please use CAN_MO247_EDATA2.
+*/
+#define CAN_EMO247DATA2 (CAN_MO247_EDATA2)
+
+/** \brief 2EEC, Message Object Acceptance Mask Register */
+#define CAN_MO247_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AEECu)
+
+/** Alias (User Manual Name) for CAN_MO247_EDATA3.
+* To use register names with standard convension, please use CAN_MO247_EDATA3.
+*/
+#define CAN_EMO247DATA3 (CAN_MO247_EDATA3)
+
+/** \brief 2EF0, Message Object Data Register Low */
+#define CAN_MO247_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AEF0u)
+
+/** Alias (User Manual Name) for CAN_MO247_EDATA4.
+* To use register names with standard convension, please use CAN_MO247_EDATA4.
+*/
+#define CAN_EMO247DATA4 (CAN_MO247_EDATA4)
+
+/** \brief 2EF4, Message Object Data Register High */
+#define CAN_MO247_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AEF4u)
+
+/** Alias (User Manual Name) for CAN_MO247_EDATA5.
+* To use register names with standard convension, please use CAN_MO247_EDATA5.
+*/
+#define CAN_EMO247DATA5 (CAN_MO247_EDATA5)
+
+/** \brief 2EF8, Message Object Arbitration Register */
+#define CAN_MO247_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AEF8u)
+
+/** Alias (User Manual Name) for CAN_MO247_EDATA6.
+* To use register names with standard convension, please use CAN_MO247_EDATA6.
+*/
+#define CAN_EMO247DATA6 (CAN_MO247_EDATA6)
+
+/** \brief 2EE0, Message Object Function Control Register */
+#define CAN_MO247_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AEE0u)
+
+/** Alias (User Manual Name) for CAN_MO247_FCR.
+* To use register names with standard convension, please use CAN_MO247_FCR.
+*/
+#define CAN_MOFCR247 (CAN_MO247_FCR)
+
+/** \brief 2EE4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO247_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AEE4u)
+
+/** Alias (User Manual Name) for CAN_MO247_FGPR.
+* To use register names with standard convension, please use CAN_MO247_FGPR.
+*/
+#define CAN_MOFGPR247 (CAN_MO247_FGPR)
+
+/** \brief 2EE8, Message Object Interrupt Pointer Register */
+#define CAN_MO247_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AEE8u)
+
+/** Alias (User Manual Name) for CAN_MO247_IPR.
+* To use register names with standard convension, please use CAN_MO247_IPR.
+*/
+#define CAN_MOIPR247 (CAN_MO247_IPR)
+
+/** \brief 2EFC, Message Object Control Register */
+#define CAN_MO247_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AEFCu)
+
+/** Alias (User Manual Name) for CAN_MO247_STAT.
+* To use register names with standard convension, please use CAN_MO247_STAT.
+*/
+#define CAN_MOSTAT247 (CAN_MO247_STAT)
+
+/** \brief 2F0C, Message Object Acceptance Mask Register */
+#define CAN_MO248_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AF0Cu)
+
+/** Alias (User Manual Name) for CAN_MO248_AMR.
+* To use register names with standard convension, please use CAN_MO248_AMR.
+*/
+#define CAN_MOAMR248 (CAN_MO248_AMR)
+
+/** \brief 2F18, Message Object Arbitration Register */
+#define CAN_MO248_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AF18u)
+
+/** Alias (User Manual Name) for CAN_MO248_AR.
+* To use register names with standard convension, please use CAN_MO248_AR.
+*/
+#define CAN_MOAR248 (CAN_MO248_AR)
+
+/** \brief 2F1C, Message Object Control Register */
+#define CAN_MO248_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AF1Cu)
+
+/** Alias (User Manual Name) for CAN_MO248_CTR.
+* To use register names with standard convension, please use CAN_MO248_CTR.
+*/
+#define CAN_MOCTR248 (CAN_MO248_CTR)
+
+/** \brief 2F14, Message Object Data Register High */
+#define CAN_MO248_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AF14u)
+
+/** Alias (User Manual Name) for CAN_MO248_DATAH.
+* To use register names with standard convension, please use CAN_MO248_DATAH.
+*/
+#define CAN_MODATAH248 (CAN_MO248_DATAH)
+
+/** \brief 2F10, Message Object Data Register Low */
+#define CAN_MO248_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AF10u)
+
+/** Alias (User Manual Name) for CAN_MO248_DATAL.
+* To use register names with standard convension, please use CAN_MO248_DATAL.
+*/
+#define CAN_MODATAL248 (CAN_MO248_DATAL)
+
+/** \brief 2F00, Message Object Function Control Register */
+#define CAN_MO248_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AF00u)
+
+/** Alias (User Manual Name) for CAN_MO248_EDATA0.
+* To use register names with standard convension, please use CAN_MO248_EDATA0.
+*/
+#define CAN_EMO248DATA0 (CAN_MO248_EDATA0)
+
+/** \brief 2F04, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO248_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AF04u)
+
+/** Alias (User Manual Name) for CAN_MO248_EDATA1.
+* To use register names with standard convension, please use CAN_MO248_EDATA1.
+*/
+#define CAN_EMO248DATA1 (CAN_MO248_EDATA1)
+
+/** \brief 2F08, Message Object Interrupt Pointer Register */
+#define CAN_MO248_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AF08u)
+
+/** Alias (User Manual Name) for CAN_MO248_EDATA2.
+* To use register names with standard convension, please use CAN_MO248_EDATA2.
+*/
+#define CAN_EMO248DATA2 (CAN_MO248_EDATA2)
+
+/** \brief 2F0C, Message Object Acceptance Mask Register */
+#define CAN_MO248_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AF0Cu)
+
+/** Alias (User Manual Name) for CAN_MO248_EDATA3.
+* To use register names with standard convension, please use CAN_MO248_EDATA3.
+*/
+#define CAN_EMO248DATA3 (CAN_MO248_EDATA3)
+
+/** \brief 2F10, Message Object Data Register Low */
+#define CAN_MO248_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AF10u)
+
+/** Alias (User Manual Name) for CAN_MO248_EDATA4.
+* To use register names with standard convension, please use CAN_MO248_EDATA4.
+*/
+#define CAN_EMO248DATA4 (CAN_MO248_EDATA4)
+
+/** \brief 2F14, Message Object Data Register High */
+#define CAN_MO248_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AF14u)
+
+/** Alias (User Manual Name) for CAN_MO248_EDATA5.
+* To use register names with standard convension, please use CAN_MO248_EDATA5.
+*/
+#define CAN_EMO248DATA5 (CAN_MO248_EDATA5)
+
+/** \brief 2F18, Message Object Arbitration Register */
+#define CAN_MO248_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AF18u)
+
+/** Alias (User Manual Name) for CAN_MO248_EDATA6.
+* To use register names with standard convension, please use CAN_MO248_EDATA6.
+*/
+#define CAN_EMO248DATA6 (CAN_MO248_EDATA6)
+
+/** \brief 2F00, Message Object Function Control Register */
+#define CAN_MO248_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AF00u)
+
+/** Alias (User Manual Name) for CAN_MO248_FCR.
+* To use register names with standard convension, please use CAN_MO248_FCR.
+*/
+#define CAN_MOFCR248 (CAN_MO248_FCR)
+
+/** \brief 2F04, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO248_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AF04u)
+
+/** Alias (User Manual Name) for CAN_MO248_FGPR.
+* To use register names with standard convension, please use CAN_MO248_FGPR.
+*/
+#define CAN_MOFGPR248 (CAN_MO248_FGPR)
+
+/** \brief 2F08, Message Object Interrupt Pointer Register */
+#define CAN_MO248_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AF08u)
+
+/** Alias (User Manual Name) for CAN_MO248_IPR.
+* To use register names with standard convension, please use CAN_MO248_IPR.
+*/
+#define CAN_MOIPR248 (CAN_MO248_IPR)
+
+/** \brief 2F1C, Message Object Control Register */
+#define CAN_MO248_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AF1Cu)
+
+/** Alias (User Manual Name) for CAN_MO248_STAT.
+* To use register names with standard convension, please use CAN_MO248_STAT.
+*/
+#define CAN_MOSTAT248 (CAN_MO248_STAT)
+
+/** \brief 2F2C, Message Object Acceptance Mask Register */
+#define CAN_MO249_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AF2Cu)
+
+/** Alias (User Manual Name) for CAN_MO249_AMR.
+* To use register names with standard convension, please use CAN_MO249_AMR.
+*/
+#define CAN_MOAMR249 (CAN_MO249_AMR)
+
+/** \brief 2F38, Message Object Arbitration Register */
+#define CAN_MO249_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AF38u)
+
+/** Alias (User Manual Name) for CAN_MO249_AR.
+* To use register names with standard convension, please use CAN_MO249_AR.
+*/
+#define CAN_MOAR249 (CAN_MO249_AR)
+
+/** \brief 2F3C, Message Object Control Register */
+#define CAN_MO249_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AF3Cu)
+
+/** Alias (User Manual Name) for CAN_MO249_CTR.
+* To use register names with standard convension, please use CAN_MO249_CTR.
+*/
+#define CAN_MOCTR249 (CAN_MO249_CTR)
+
+/** \brief 2F34, Message Object Data Register High */
+#define CAN_MO249_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AF34u)
+
+/** Alias (User Manual Name) for CAN_MO249_DATAH.
+* To use register names with standard convension, please use CAN_MO249_DATAH.
+*/
+#define CAN_MODATAH249 (CAN_MO249_DATAH)
+
+/** \brief 2F30, Message Object Data Register Low */
+#define CAN_MO249_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AF30u)
+
+/** Alias (User Manual Name) for CAN_MO249_DATAL.
+* To use register names with standard convension, please use CAN_MO249_DATAL.
+*/
+#define CAN_MODATAL249 (CAN_MO249_DATAL)
+
+/** \brief 2F20, Message Object Function Control Register */
+#define CAN_MO249_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AF20u)
+
+/** Alias (User Manual Name) for CAN_MO249_EDATA0.
+* To use register names with standard convension, please use CAN_MO249_EDATA0.
+*/
+#define CAN_EMO249DATA0 (CAN_MO249_EDATA0)
+
+/** \brief 2F24, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO249_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AF24u)
+
+/** Alias (User Manual Name) for CAN_MO249_EDATA1.
+* To use register names with standard convension, please use CAN_MO249_EDATA1.
+*/
+#define CAN_EMO249DATA1 (CAN_MO249_EDATA1)
+
+/** \brief 2F28, Message Object Interrupt Pointer Register */
+#define CAN_MO249_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AF28u)
+
+/** Alias (User Manual Name) for CAN_MO249_EDATA2.
+* To use register names with standard convension, please use CAN_MO249_EDATA2.
+*/
+#define CAN_EMO249DATA2 (CAN_MO249_EDATA2)
+
+/** \brief 2F2C, Message Object Acceptance Mask Register */
+#define CAN_MO249_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AF2Cu)
+
+/** Alias (User Manual Name) for CAN_MO249_EDATA3.
+* To use register names with standard convension, please use CAN_MO249_EDATA3.
+*/
+#define CAN_EMO249DATA3 (CAN_MO249_EDATA3)
+
+/** \brief 2F30, Message Object Data Register Low */
+#define CAN_MO249_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AF30u)
+
+/** Alias (User Manual Name) for CAN_MO249_EDATA4.
+* To use register names with standard convension, please use CAN_MO249_EDATA4.
+*/
+#define CAN_EMO249DATA4 (CAN_MO249_EDATA4)
+
+/** \brief 2F34, Message Object Data Register High */
+#define CAN_MO249_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AF34u)
+
+/** Alias (User Manual Name) for CAN_MO249_EDATA5.
+* To use register names with standard convension, please use CAN_MO249_EDATA5.
+*/
+#define CAN_EMO249DATA5 (CAN_MO249_EDATA5)
+
+/** \brief 2F38, Message Object Arbitration Register */
+#define CAN_MO249_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AF38u)
+
+/** Alias (User Manual Name) for CAN_MO249_EDATA6.
+* To use register names with standard convension, please use CAN_MO249_EDATA6.
+*/
+#define CAN_EMO249DATA6 (CAN_MO249_EDATA6)
+
+/** \brief 2F20, Message Object Function Control Register */
+#define CAN_MO249_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AF20u)
+
+/** Alias (User Manual Name) for CAN_MO249_FCR.
+* To use register names with standard convension, please use CAN_MO249_FCR.
+*/
+#define CAN_MOFCR249 (CAN_MO249_FCR)
+
+/** \brief 2F24, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO249_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AF24u)
+
+/** Alias (User Manual Name) for CAN_MO249_FGPR.
+* To use register names with standard convension, please use CAN_MO249_FGPR.
+*/
+#define CAN_MOFGPR249 (CAN_MO249_FGPR)
+
+/** \brief 2F28, Message Object Interrupt Pointer Register */
+#define CAN_MO249_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AF28u)
+
+/** Alias (User Manual Name) for CAN_MO249_IPR.
+* To use register names with standard convension, please use CAN_MO249_IPR.
+*/
+#define CAN_MOIPR249 (CAN_MO249_IPR)
+
+/** \brief 2F3C, Message Object Control Register */
+#define CAN_MO249_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AF3Cu)
+
+/** Alias (User Manual Name) for CAN_MO249_STAT.
+* To use register names with standard convension, please use CAN_MO249_STAT.
+*/
+#define CAN_MOSTAT249 (CAN_MO249_STAT)
+
+/** \brief 130C, Message Object Acceptance Mask Register */
+#define CAN_MO24_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001930Cu)
+
+/** Alias (User Manual Name) for CAN_MO24_AMR.
+* To use register names with standard convension, please use CAN_MO24_AMR.
+*/
+#define CAN_MOAMR24 (CAN_MO24_AMR)
+
+/** \brief 1318, Message Object Arbitration Register */
+#define CAN_MO24_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019318u)
+
+/** Alias (User Manual Name) for CAN_MO24_AR.
+* To use register names with standard convension, please use CAN_MO24_AR.
+*/
+#define CAN_MOAR24 (CAN_MO24_AR)
+
+/** \brief 131C, Message Object Control Register */
+#define CAN_MO24_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001931Cu)
+
+/** Alias (User Manual Name) for CAN_MO24_CTR.
+* To use register names with standard convension, please use CAN_MO24_CTR.
+*/
+#define CAN_MOCTR24 (CAN_MO24_CTR)
+
+/** \brief 1314, Message Object Data Register High */
+#define CAN_MO24_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019314u)
+
+/** Alias (User Manual Name) for CAN_MO24_DATAH.
+* To use register names with standard convension, please use CAN_MO24_DATAH.
+*/
+#define CAN_MODATAH24 (CAN_MO24_DATAH)
+
+/** \brief 1310, Message Object Data Register Low */
+#define CAN_MO24_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019310u)
+
+/** Alias (User Manual Name) for CAN_MO24_DATAL.
+* To use register names with standard convension, please use CAN_MO24_DATAL.
+*/
+#define CAN_MODATAL24 (CAN_MO24_DATAL)
+
+/** \brief 1300, Message Object Function Control Register */
+#define CAN_MO24_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019300u)
+
+/** Alias (User Manual Name) for CAN_MO24_EDATA0.
+* To use register names with standard convension, please use CAN_MO24_EDATA0.
+*/
+#define CAN_EMO24DATA0 (CAN_MO24_EDATA0)
+
+/** \brief 1304, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO24_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019304u)
+
+/** Alias (User Manual Name) for CAN_MO24_EDATA1.
+* To use register names with standard convension, please use CAN_MO24_EDATA1.
+*/
+#define CAN_EMO24DATA1 (CAN_MO24_EDATA1)
+
+/** \brief 1308, Message Object Interrupt Pointer Register */
+#define CAN_MO24_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019308u)
+
+/** Alias (User Manual Name) for CAN_MO24_EDATA2.
+* To use register names with standard convension, please use CAN_MO24_EDATA2.
+*/
+#define CAN_EMO24DATA2 (CAN_MO24_EDATA2)
+
+/** \brief 130C, Message Object Acceptance Mask Register */
+#define CAN_MO24_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001930Cu)
+
+/** Alias (User Manual Name) for CAN_MO24_EDATA3.
+* To use register names with standard convension, please use CAN_MO24_EDATA3.
+*/
+#define CAN_EMO24DATA3 (CAN_MO24_EDATA3)
+
+/** \brief 1310, Message Object Data Register Low */
+#define CAN_MO24_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019310u)
+
+/** Alias (User Manual Name) for CAN_MO24_EDATA4.
+* To use register names with standard convension, please use CAN_MO24_EDATA4.
+*/
+#define CAN_EMO24DATA4 (CAN_MO24_EDATA4)
+
+/** \brief 1314, Message Object Data Register High */
+#define CAN_MO24_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019314u)
+
+/** Alias (User Manual Name) for CAN_MO24_EDATA5.
+* To use register names with standard convension, please use CAN_MO24_EDATA5.
+*/
+#define CAN_EMO24DATA5 (CAN_MO24_EDATA5)
+
+/** \brief 1318, Message Object Arbitration Register */
+#define CAN_MO24_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019318u)
+
+/** Alias (User Manual Name) for CAN_MO24_EDATA6.
+* To use register names with standard convension, please use CAN_MO24_EDATA6.
+*/
+#define CAN_EMO24DATA6 (CAN_MO24_EDATA6)
+
+/** \brief 1300, Message Object Function Control Register */
+#define CAN_MO24_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019300u)
+
+/** Alias (User Manual Name) for CAN_MO24_FCR.
+* To use register names with standard convension, please use CAN_MO24_FCR.
+*/
+#define CAN_MOFCR24 (CAN_MO24_FCR)
+
+/** \brief 1304, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO24_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019304u)
+
+/** Alias (User Manual Name) for CAN_MO24_FGPR.
+* To use register names with standard convension, please use CAN_MO24_FGPR.
+*/
+#define CAN_MOFGPR24 (CAN_MO24_FGPR)
+
+/** \brief 1308, Message Object Interrupt Pointer Register */
+#define CAN_MO24_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019308u)
+
+/** Alias (User Manual Name) for CAN_MO24_IPR.
+* To use register names with standard convension, please use CAN_MO24_IPR.
+*/
+#define CAN_MOIPR24 (CAN_MO24_IPR)
+
+/** \brief 131C, Message Object Control Register */
+#define CAN_MO24_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001931Cu)
+
+/** Alias (User Manual Name) for CAN_MO24_STAT.
+* To use register names with standard convension, please use CAN_MO24_STAT.
+*/
+#define CAN_MOSTAT24 (CAN_MO24_STAT)
+
+/** \brief 2F4C, Message Object Acceptance Mask Register */
+#define CAN_MO250_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AF4Cu)
+
+/** Alias (User Manual Name) for CAN_MO250_AMR.
+* To use register names with standard convension, please use CAN_MO250_AMR.
+*/
+#define CAN_MOAMR250 (CAN_MO250_AMR)
+
+/** \brief 2F58, Message Object Arbitration Register */
+#define CAN_MO250_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AF58u)
+
+/** Alias (User Manual Name) for CAN_MO250_AR.
+* To use register names with standard convension, please use CAN_MO250_AR.
+*/
+#define CAN_MOAR250 (CAN_MO250_AR)
+
+/** \brief 2F5C, Message Object Control Register */
+#define CAN_MO250_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AF5Cu)
+
+/** Alias (User Manual Name) for CAN_MO250_CTR.
+* To use register names with standard convension, please use CAN_MO250_CTR.
+*/
+#define CAN_MOCTR250 (CAN_MO250_CTR)
+
+/** \brief 2F54, Message Object Data Register High */
+#define CAN_MO250_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AF54u)
+
+/** Alias (User Manual Name) for CAN_MO250_DATAH.
+* To use register names with standard convension, please use CAN_MO250_DATAH.
+*/
+#define CAN_MODATAH250 (CAN_MO250_DATAH)
+
+/** \brief 2F50, Message Object Data Register Low */
+#define CAN_MO250_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AF50u)
+
+/** Alias (User Manual Name) for CAN_MO250_DATAL.
+* To use register names with standard convension, please use CAN_MO250_DATAL.
+*/
+#define CAN_MODATAL250 (CAN_MO250_DATAL)
+
+/** \brief 2F40, Message Object Function Control Register */
+#define CAN_MO250_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AF40u)
+
+/** Alias (User Manual Name) for CAN_MO250_EDATA0.
+* To use register names with standard convension, please use CAN_MO250_EDATA0.
+*/
+#define CAN_EMO250DATA0 (CAN_MO250_EDATA0)
+
+/** \brief 2F44, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO250_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AF44u)
+
+/** Alias (User Manual Name) for CAN_MO250_EDATA1.
+* To use register names with standard convension, please use CAN_MO250_EDATA1.
+*/
+#define CAN_EMO250DATA1 (CAN_MO250_EDATA1)
+
+/** \brief 2F48, Message Object Interrupt Pointer Register */
+#define CAN_MO250_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AF48u)
+
+/** Alias (User Manual Name) for CAN_MO250_EDATA2.
+* To use register names with standard convension, please use CAN_MO250_EDATA2.
+*/
+#define CAN_EMO250DATA2 (CAN_MO250_EDATA2)
+
+/** \brief 2F4C, Message Object Acceptance Mask Register */
+#define CAN_MO250_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AF4Cu)
+
+/** Alias (User Manual Name) for CAN_MO250_EDATA3.
+* To use register names with standard convension, please use CAN_MO250_EDATA3.
+*/
+#define CAN_EMO250DATA3 (CAN_MO250_EDATA3)
+
+/** \brief 2F50, Message Object Data Register Low */
+#define CAN_MO250_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AF50u)
+
+/** Alias (User Manual Name) for CAN_MO250_EDATA4.
+* To use register names with standard convension, please use CAN_MO250_EDATA4.
+*/
+#define CAN_EMO250DATA4 (CAN_MO250_EDATA4)
+
+/** \brief 2F54, Message Object Data Register High */
+#define CAN_MO250_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AF54u)
+
+/** Alias (User Manual Name) for CAN_MO250_EDATA5.
+* To use register names with standard convension, please use CAN_MO250_EDATA5.
+*/
+#define CAN_EMO250DATA5 (CAN_MO250_EDATA5)
+
+/** \brief 2F58, Message Object Arbitration Register */
+#define CAN_MO250_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AF58u)
+
+/** Alias (User Manual Name) for CAN_MO250_EDATA6.
+* To use register names with standard convension, please use CAN_MO250_EDATA6.
+*/
+#define CAN_EMO250DATA6 (CAN_MO250_EDATA6)
+
+/** \brief 2F40, Message Object Function Control Register */
+#define CAN_MO250_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AF40u)
+
+/** Alias (User Manual Name) for CAN_MO250_FCR.
+* To use register names with standard convension, please use CAN_MO250_FCR.
+*/
+#define CAN_MOFCR250 (CAN_MO250_FCR)
+
+/** \brief 2F44, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO250_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AF44u)
+
+/** Alias (User Manual Name) for CAN_MO250_FGPR.
+* To use register names with standard convension, please use CAN_MO250_FGPR.
+*/
+#define CAN_MOFGPR250 (CAN_MO250_FGPR)
+
+/** \brief 2F48, Message Object Interrupt Pointer Register */
+#define CAN_MO250_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AF48u)
+
+/** Alias (User Manual Name) for CAN_MO250_IPR.
+* To use register names with standard convension, please use CAN_MO250_IPR.
+*/
+#define CAN_MOIPR250 (CAN_MO250_IPR)
+
+/** \brief 2F5C, Message Object Control Register */
+#define CAN_MO250_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AF5Cu)
+
+/** Alias (User Manual Name) for CAN_MO250_STAT.
+* To use register names with standard convension, please use CAN_MO250_STAT.
+*/
+#define CAN_MOSTAT250 (CAN_MO250_STAT)
+
+/** \brief 2F6C, Message Object Acceptance Mask Register */
+#define CAN_MO251_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AF6Cu)
+
+/** Alias (User Manual Name) for CAN_MO251_AMR.
+* To use register names with standard convension, please use CAN_MO251_AMR.
+*/
+#define CAN_MOAMR251 (CAN_MO251_AMR)
+
+/** \brief 2F78, Message Object Arbitration Register */
+#define CAN_MO251_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AF78u)
+
+/** Alias (User Manual Name) for CAN_MO251_AR.
+* To use register names with standard convension, please use CAN_MO251_AR.
+*/
+#define CAN_MOAR251 (CAN_MO251_AR)
+
+/** \brief 2F7C, Message Object Control Register */
+#define CAN_MO251_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AF7Cu)
+
+/** Alias (User Manual Name) for CAN_MO251_CTR.
+* To use register names with standard convension, please use CAN_MO251_CTR.
+*/
+#define CAN_MOCTR251 (CAN_MO251_CTR)
+
+/** \brief 2F74, Message Object Data Register High */
+#define CAN_MO251_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AF74u)
+
+/** Alias (User Manual Name) for CAN_MO251_DATAH.
+* To use register names with standard convension, please use CAN_MO251_DATAH.
+*/
+#define CAN_MODATAH251 (CAN_MO251_DATAH)
+
+/** \brief 2F70, Message Object Data Register Low */
+#define CAN_MO251_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AF70u)
+
+/** Alias (User Manual Name) for CAN_MO251_DATAL.
+* To use register names with standard convension, please use CAN_MO251_DATAL.
+*/
+#define CAN_MODATAL251 (CAN_MO251_DATAL)
+
+/** \brief 2F60, Message Object Function Control Register */
+#define CAN_MO251_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AF60u)
+
+/** Alias (User Manual Name) for CAN_MO251_EDATA0.
+* To use register names with standard convension, please use CAN_MO251_EDATA0.
+*/
+#define CAN_EMO251DATA0 (CAN_MO251_EDATA0)
+
+/** \brief 2F64, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO251_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AF64u)
+
+/** Alias (User Manual Name) for CAN_MO251_EDATA1.
+* To use register names with standard convension, please use CAN_MO251_EDATA1.
+*/
+#define CAN_EMO251DATA1 (CAN_MO251_EDATA1)
+
+/** \brief 2F68, Message Object Interrupt Pointer Register */
+#define CAN_MO251_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AF68u)
+
+/** Alias (User Manual Name) for CAN_MO251_EDATA2.
+* To use register names with standard convension, please use CAN_MO251_EDATA2.
+*/
+#define CAN_EMO251DATA2 (CAN_MO251_EDATA2)
+
+/** \brief 2F6C, Message Object Acceptance Mask Register */
+#define CAN_MO251_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AF6Cu)
+
+/** Alias (User Manual Name) for CAN_MO251_EDATA3.
+* To use register names with standard convension, please use CAN_MO251_EDATA3.
+*/
+#define CAN_EMO251DATA3 (CAN_MO251_EDATA3)
+
+/** \brief 2F70, Message Object Data Register Low */
+#define CAN_MO251_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AF70u)
+
+/** Alias (User Manual Name) for CAN_MO251_EDATA4.
+* To use register names with standard convension, please use CAN_MO251_EDATA4.
+*/
+#define CAN_EMO251DATA4 (CAN_MO251_EDATA4)
+
+/** \brief 2F74, Message Object Data Register High */
+#define CAN_MO251_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AF74u)
+
+/** Alias (User Manual Name) for CAN_MO251_EDATA5.
+* To use register names with standard convension, please use CAN_MO251_EDATA5.
+*/
+#define CAN_EMO251DATA5 (CAN_MO251_EDATA5)
+
+/** \brief 2F78, Message Object Arbitration Register */
+#define CAN_MO251_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AF78u)
+
+/** Alias (User Manual Name) for CAN_MO251_EDATA6.
+* To use register names with standard convension, please use CAN_MO251_EDATA6.
+*/
+#define CAN_EMO251DATA6 (CAN_MO251_EDATA6)
+
+/** \brief 2F60, Message Object Function Control Register */
+#define CAN_MO251_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AF60u)
+
+/** Alias (User Manual Name) for CAN_MO251_FCR.
+* To use register names with standard convension, please use CAN_MO251_FCR.
+*/
+#define CAN_MOFCR251 (CAN_MO251_FCR)
+
+/** \brief 2F64, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO251_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AF64u)
+
+/** Alias (User Manual Name) for CAN_MO251_FGPR.
+* To use register names with standard convension, please use CAN_MO251_FGPR.
+*/
+#define CAN_MOFGPR251 (CAN_MO251_FGPR)
+
+/** \brief 2F68, Message Object Interrupt Pointer Register */
+#define CAN_MO251_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AF68u)
+
+/** Alias (User Manual Name) for CAN_MO251_IPR.
+* To use register names with standard convension, please use CAN_MO251_IPR.
+*/
+#define CAN_MOIPR251 (CAN_MO251_IPR)
+
+/** \brief 2F7C, Message Object Control Register */
+#define CAN_MO251_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AF7Cu)
+
+/** Alias (User Manual Name) for CAN_MO251_STAT.
+* To use register names with standard convension, please use CAN_MO251_STAT.
+*/
+#define CAN_MOSTAT251 (CAN_MO251_STAT)
+
+/** \brief 2F8C, Message Object Acceptance Mask Register */
+#define CAN_MO252_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AF8Cu)
+
+/** Alias (User Manual Name) for CAN_MO252_AMR.
+* To use register names with standard convension, please use CAN_MO252_AMR.
+*/
+#define CAN_MOAMR252 (CAN_MO252_AMR)
+
+/** \brief 2F98, Message Object Arbitration Register */
+#define CAN_MO252_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AF98u)
+
+/** Alias (User Manual Name) for CAN_MO252_AR.
+* To use register names with standard convension, please use CAN_MO252_AR.
+*/
+#define CAN_MOAR252 (CAN_MO252_AR)
+
+/** \brief 2F9C, Message Object Control Register */
+#define CAN_MO252_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AF9Cu)
+
+/** Alias (User Manual Name) for CAN_MO252_CTR.
+* To use register names with standard convension, please use CAN_MO252_CTR.
+*/
+#define CAN_MOCTR252 (CAN_MO252_CTR)
+
+/** \brief 2F94, Message Object Data Register High */
+#define CAN_MO252_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AF94u)
+
+/** Alias (User Manual Name) for CAN_MO252_DATAH.
+* To use register names with standard convension, please use CAN_MO252_DATAH.
+*/
+#define CAN_MODATAH252 (CAN_MO252_DATAH)
+
+/** \brief 2F90, Message Object Data Register Low */
+#define CAN_MO252_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AF90u)
+
+/** Alias (User Manual Name) for CAN_MO252_DATAL.
+* To use register names with standard convension, please use CAN_MO252_DATAL.
+*/
+#define CAN_MODATAL252 (CAN_MO252_DATAL)
+
+/** \brief 2F80, Message Object Function Control Register */
+#define CAN_MO252_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AF80u)
+
+/** Alias (User Manual Name) for CAN_MO252_EDATA0.
+* To use register names with standard convension, please use CAN_MO252_EDATA0.
+*/
+#define CAN_EMO252DATA0 (CAN_MO252_EDATA0)
+
+/** \brief 2F84, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO252_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AF84u)
+
+/** Alias (User Manual Name) for CAN_MO252_EDATA1.
+* To use register names with standard convension, please use CAN_MO252_EDATA1.
+*/
+#define CAN_EMO252DATA1 (CAN_MO252_EDATA1)
+
+/** \brief 2F88, Message Object Interrupt Pointer Register */
+#define CAN_MO252_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AF88u)
+
+/** Alias (User Manual Name) for CAN_MO252_EDATA2.
+* To use register names with standard convension, please use CAN_MO252_EDATA2.
+*/
+#define CAN_EMO252DATA2 (CAN_MO252_EDATA2)
+
+/** \brief 2F8C, Message Object Acceptance Mask Register */
+#define CAN_MO252_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AF8Cu)
+
+/** Alias (User Manual Name) for CAN_MO252_EDATA3.
+* To use register names with standard convension, please use CAN_MO252_EDATA3.
+*/
+#define CAN_EMO252DATA3 (CAN_MO252_EDATA3)
+
+/** \brief 2F90, Message Object Data Register Low */
+#define CAN_MO252_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AF90u)
+
+/** Alias (User Manual Name) for CAN_MO252_EDATA4.
+* To use register names with standard convension, please use CAN_MO252_EDATA4.
+*/
+#define CAN_EMO252DATA4 (CAN_MO252_EDATA4)
+
+/** \brief 2F94, Message Object Data Register High */
+#define CAN_MO252_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AF94u)
+
+/** Alias (User Manual Name) for CAN_MO252_EDATA5.
+* To use register names with standard convension, please use CAN_MO252_EDATA5.
+*/
+#define CAN_EMO252DATA5 (CAN_MO252_EDATA5)
+
+/** \brief 2F98, Message Object Arbitration Register */
+#define CAN_MO252_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AF98u)
+
+/** Alias (User Manual Name) for CAN_MO252_EDATA6.
+* To use register names with standard convension, please use CAN_MO252_EDATA6.
+*/
+#define CAN_EMO252DATA6 (CAN_MO252_EDATA6)
+
+/** \brief 2F80, Message Object Function Control Register */
+#define CAN_MO252_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AF80u)
+
+/** Alias (User Manual Name) for CAN_MO252_FCR.
+* To use register names with standard convension, please use CAN_MO252_FCR.
+*/
+#define CAN_MOFCR252 (CAN_MO252_FCR)
+
+/** \brief 2F84, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO252_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AF84u)
+
+/** Alias (User Manual Name) for CAN_MO252_FGPR.
+* To use register names with standard convension, please use CAN_MO252_FGPR.
+*/
+#define CAN_MOFGPR252 (CAN_MO252_FGPR)
+
+/** \brief 2F88, Message Object Interrupt Pointer Register */
+#define CAN_MO252_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AF88u)
+
+/** Alias (User Manual Name) for CAN_MO252_IPR.
+* To use register names with standard convension, please use CAN_MO252_IPR.
+*/
+#define CAN_MOIPR252 (CAN_MO252_IPR)
+
+/** \brief 2F9C, Message Object Control Register */
+#define CAN_MO252_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AF9Cu)
+
+/** Alias (User Manual Name) for CAN_MO252_STAT.
+* To use register names with standard convension, please use CAN_MO252_STAT.
+*/
+#define CAN_MOSTAT252 (CAN_MO252_STAT)
+
+/** \brief 2FAC, Message Object Acceptance Mask Register */
+#define CAN_MO253_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AFACu)
+
+/** Alias (User Manual Name) for CAN_MO253_AMR.
+* To use register names with standard convension, please use CAN_MO253_AMR.
+*/
+#define CAN_MOAMR253 (CAN_MO253_AMR)
+
+/** \brief 2FB8, Message Object Arbitration Register */
+#define CAN_MO253_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AFB8u)
+
+/** Alias (User Manual Name) for CAN_MO253_AR.
+* To use register names with standard convension, please use CAN_MO253_AR.
+*/
+#define CAN_MOAR253 (CAN_MO253_AR)
+
+/** \brief 2FBC, Message Object Control Register */
+#define CAN_MO253_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AFBCu)
+
+/** Alias (User Manual Name) for CAN_MO253_CTR.
+* To use register names with standard convension, please use CAN_MO253_CTR.
+*/
+#define CAN_MOCTR253 (CAN_MO253_CTR)
+
+/** \brief 2FB4, Message Object Data Register High */
+#define CAN_MO253_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AFB4u)
+
+/** Alias (User Manual Name) for CAN_MO253_DATAH.
+* To use register names with standard convension, please use CAN_MO253_DATAH.
+*/
+#define CAN_MODATAH253 (CAN_MO253_DATAH)
+
+/** \brief 2FB0, Message Object Data Register Low */
+#define CAN_MO253_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AFB0u)
+
+/** Alias (User Manual Name) for CAN_MO253_DATAL.
+* To use register names with standard convension, please use CAN_MO253_DATAL.
+*/
+#define CAN_MODATAL253 (CAN_MO253_DATAL)
+
+/** \brief 2FA0, Message Object Function Control Register */
+#define CAN_MO253_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AFA0u)
+
+/** Alias (User Manual Name) for CAN_MO253_EDATA0.
+* To use register names with standard convension, please use CAN_MO253_EDATA0.
+*/
+#define CAN_EMO253DATA0 (CAN_MO253_EDATA0)
+
+/** \brief 2FA4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO253_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AFA4u)
+
+/** Alias (User Manual Name) for CAN_MO253_EDATA1.
+* To use register names with standard convension, please use CAN_MO253_EDATA1.
+*/
+#define CAN_EMO253DATA1 (CAN_MO253_EDATA1)
+
+/** \brief 2FA8, Message Object Interrupt Pointer Register */
+#define CAN_MO253_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AFA8u)
+
+/** Alias (User Manual Name) for CAN_MO253_EDATA2.
+* To use register names with standard convension, please use CAN_MO253_EDATA2.
+*/
+#define CAN_EMO253DATA2 (CAN_MO253_EDATA2)
+
+/** \brief 2FAC, Message Object Acceptance Mask Register */
+#define CAN_MO253_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AFACu)
+
+/** Alias (User Manual Name) for CAN_MO253_EDATA3.
+* To use register names with standard convension, please use CAN_MO253_EDATA3.
+*/
+#define CAN_EMO253DATA3 (CAN_MO253_EDATA3)
+
+/** \brief 2FB0, Message Object Data Register Low */
+#define CAN_MO253_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AFB0u)
+
+/** Alias (User Manual Name) for CAN_MO253_EDATA4.
+* To use register names with standard convension, please use CAN_MO253_EDATA4.
+*/
+#define CAN_EMO253DATA4 (CAN_MO253_EDATA4)
+
+/** \brief 2FB4, Message Object Data Register High */
+#define CAN_MO253_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AFB4u)
+
+/** Alias (User Manual Name) for CAN_MO253_EDATA5.
+* To use register names with standard convension, please use CAN_MO253_EDATA5.
+*/
+#define CAN_EMO253DATA5 (CAN_MO253_EDATA5)
+
+/** \brief 2FB8, Message Object Arbitration Register */
+#define CAN_MO253_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AFB8u)
+
+/** Alias (User Manual Name) for CAN_MO253_EDATA6.
+* To use register names with standard convension, please use CAN_MO253_EDATA6.
+*/
+#define CAN_EMO253DATA6 (CAN_MO253_EDATA6)
+
+/** \brief 2FA0, Message Object Function Control Register */
+#define CAN_MO253_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AFA0u)
+
+/** Alias (User Manual Name) for CAN_MO253_FCR.
+* To use register names with standard convension, please use CAN_MO253_FCR.
+*/
+#define CAN_MOFCR253 (CAN_MO253_FCR)
+
+/** \brief 2FA4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO253_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AFA4u)
+
+/** Alias (User Manual Name) for CAN_MO253_FGPR.
+* To use register names with standard convension, please use CAN_MO253_FGPR.
+*/
+#define CAN_MOFGPR253 (CAN_MO253_FGPR)
+
+/** \brief 2FA8, Message Object Interrupt Pointer Register */
+#define CAN_MO253_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AFA8u)
+
+/** Alias (User Manual Name) for CAN_MO253_IPR.
+* To use register names with standard convension, please use CAN_MO253_IPR.
+*/
+#define CAN_MOIPR253 (CAN_MO253_IPR)
+
+/** \brief 2FBC, Message Object Control Register */
+#define CAN_MO253_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AFBCu)
+
+/** Alias (User Manual Name) for CAN_MO253_STAT.
+* To use register names with standard convension, please use CAN_MO253_STAT.
+*/
+#define CAN_MOSTAT253 (CAN_MO253_STAT)
+
+/** \brief 2FCC, Message Object Acceptance Mask Register */
+#define CAN_MO254_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AFCCu)
+
+/** Alias (User Manual Name) for CAN_MO254_AMR.
+* To use register names with standard convension, please use CAN_MO254_AMR.
+*/
+#define CAN_MOAMR254 (CAN_MO254_AMR)
+
+/** \brief 2FD8, Message Object Arbitration Register */
+#define CAN_MO254_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AFD8u)
+
+/** Alias (User Manual Name) for CAN_MO254_AR.
+* To use register names with standard convension, please use CAN_MO254_AR.
+*/
+#define CAN_MOAR254 (CAN_MO254_AR)
+
+/** \brief 2FDC, Message Object Control Register */
+#define CAN_MO254_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AFDCu)
+
+/** Alias (User Manual Name) for CAN_MO254_CTR.
+* To use register names with standard convension, please use CAN_MO254_CTR.
+*/
+#define CAN_MOCTR254 (CAN_MO254_CTR)
+
+/** \brief 2FD4, Message Object Data Register High */
+#define CAN_MO254_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AFD4u)
+
+/** Alias (User Manual Name) for CAN_MO254_DATAH.
+* To use register names with standard convension, please use CAN_MO254_DATAH.
+*/
+#define CAN_MODATAH254 (CAN_MO254_DATAH)
+
+/** \brief 2FD0, Message Object Data Register Low */
+#define CAN_MO254_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AFD0u)
+
+/** Alias (User Manual Name) for CAN_MO254_DATAL.
+* To use register names with standard convension, please use CAN_MO254_DATAL.
+*/
+#define CAN_MODATAL254 (CAN_MO254_DATAL)
+
+/** \brief 2FC0, Message Object Function Control Register */
+#define CAN_MO254_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AFC0u)
+
+/** Alias (User Manual Name) for CAN_MO254_EDATA0.
+* To use register names with standard convension, please use CAN_MO254_EDATA0.
+*/
+#define CAN_EMO254DATA0 (CAN_MO254_EDATA0)
+
+/** \brief 2FC4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO254_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AFC4u)
+
+/** Alias (User Manual Name) for CAN_MO254_EDATA1.
+* To use register names with standard convension, please use CAN_MO254_EDATA1.
+*/
+#define CAN_EMO254DATA1 (CAN_MO254_EDATA1)
+
+/** \brief 2FC8, Message Object Interrupt Pointer Register */
+#define CAN_MO254_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AFC8u)
+
+/** Alias (User Manual Name) for CAN_MO254_EDATA2.
+* To use register names with standard convension, please use CAN_MO254_EDATA2.
+*/
+#define CAN_EMO254DATA2 (CAN_MO254_EDATA2)
+
+/** \brief 2FCC, Message Object Acceptance Mask Register */
+#define CAN_MO254_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AFCCu)
+
+/** Alias (User Manual Name) for CAN_MO254_EDATA3.
+* To use register names with standard convension, please use CAN_MO254_EDATA3.
+*/
+#define CAN_EMO254DATA3 (CAN_MO254_EDATA3)
+
+/** \brief 2FD0, Message Object Data Register Low */
+#define CAN_MO254_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AFD0u)
+
+/** Alias (User Manual Name) for CAN_MO254_EDATA4.
+* To use register names with standard convension, please use CAN_MO254_EDATA4.
+*/
+#define CAN_EMO254DATA4 (CAN_MO254_EDATA4)
+
+/** \brief 2FD4, Message Object Data Register High */
+#define CAN_MO254_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AFD4u)
+
+/** Alias (User Manual Name) for CAN_MO254_EDATA5.
+* To use register names with standard convension, please use CAN_MO254_EDATA5.
+*/
+#define CAN_EMO254DATA5 (CAN_MO254_EDATA5)
+
+/** \brief 2FD8, Message Object Arbitration Register */
+#define CAN_MO254_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AFD8u)
+
+/** Alias (User Manual Name) for CAN_MO254_EDATA6.
+* To use register names with standard convension, please use CAN_MO254_EDATA6.
+*/
+#define CAN_EMO254DATA6 (CAN_MO254_EDATA6)
+
+/** \brief 2FC0, Message Object Function Control Register */
+#define CAN_MO254_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AFC0u)
+
+/** Alias (User Manual Name) for CAN_MO254_FCR.
+* To use register names with standard convension, please use CAN_MO254_FCR.
+*/
+#define CAN_MOFCR254 (CAN_MO254_FCR)
+
+/** \brief 2FC4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO254_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AFC4u)
+
+/** Alias (User Manual Name) for CAN_MO254_FGPR.
+* To use register names with standard convension, please use CAN_MO254_FGPR.
+*/
+#define CAN_MOFGPR254 (CAN_MO254_FGPR)
+
+/** \brief 2FC8, Message Object Interrupt Pointer Register */
+#define CAN_MO254_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AFC8u)
+
+/** Alias (User Manual Name) for CAN_MO254_IPR.
+* To use register names with standard convension, please use CAN_MO254_IPR.
+*/
+#define CAN_MOIPR254 (CAN_MO254_IPR)
+
+/** \brief 2FDC, Message Object Control Register */
+#define CAN_MO254_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AFDCu)
+
+/** Alias (User Manual Name) for CAN_MO254_STAT.
+* To use register names with standard convension, please use CAN_MO254_STAT.
+*/
+#define CAN_MOSTAT254 (CAN_MO254_STAT)
+
+/** \brief 2FEC, Message Object Acceptance Mask Register */
+#define CAN_MO255_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001AFECu)
+
+/** Alias (User Manual Name) for CAN_MO255_AMR.
+* To use register names with standard convension, please use CAN_MO255_AMR.
+*/
+#define CAN_MOAMR255 (CAN_MO255_AMR)
+
+/** \brief 2FF8, Message Object Arbitration Register */
+#define CAN_MO255_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF001AFF8u)
+
+/** Alias (User Manual Name) for CAN_MO255_AR.
+* To use register names with standard convension, please use CAN_MO255_AR.
+*/
+#define CAN_MOAR255 (CAN_MO255_AR)
+
+/** \brief 2FFC, Message Object Control Register */
+#define CAN_MO255_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001AFFCu)
+
+/** Alias (User Manual Name) for CAN_MO255_CTR.
+* To use register names with standard convension, please use CAN_MO255_CTR.
+*/
+#define CAN_MOCTR255 (CAN_MO255_CTR)
+
+/** \brief 2FF4, Message Object Data Register High */
+#define CAN_MO255_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF001AFF4u)
+
+/** Alias (User Manual Name) for CAN_MO255_DATAH.
+* To use register names with standard convension, please use CAN_MO255_DATAH.
+*/
+#define CAN_MODATAH255 (CAN_MO255_DATAH)
+
+/** \brief 2FF0, Message Object Data Register Low */
+#define CAN_MO255_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF001AFF0u)
+
+/** Alias (User Manual Name) for CAN_MO255_DATAL.
+* To use register names with standard convension, please use CAN_MO255_DATAL.
+*/
+#define CAN_MODATAL255 (CAN_MO255_DATAL)
+
+/** \brief 2FE0, Message Object Function Control Register */
+#define CAN_MO255_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF001AFE0u)
+
+/** Alias (User Manual Name) for CAN_MO255_EDATA0.
+* To use register names with standard convension, please use CAN_MO255_EDATA0.
+*/
+#define CAN_EMO255DATA0 (CAN_MO255_EDATA0)
+
+/** \brief 2FE4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO255_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF001AFE4u)
+
+/** Alias (User Manual Name) for CAN_MO255_EDATA1.
+* To use register names with standard convension, please use CAN_MO255_EDATA1.
+*/
+#define CAN_EMO255DATA1 (CAN_MO255_EDATA1)
+
+/** \brief 2FE8, Message Object Interrupt Pointer Register */
+#define CAN_MO255_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF001AFE8u)
+
+/** Alias (User Manual Name) for CAN_MO255_EDATA2.
+* To use register names with standard convension, please use CAN_MO255_EDATA2.
+*/
+#define CAN_EMO255DATA2 (CAN_MO255_EDATA2)
+
+/** \brief 2FEC, Message Object Acceptance Mask Register */
+#define CAN_MO255_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001AFECu)
+
+/** Alias (User Manual Name) for CAN_MO255_EDATA3.
+* To use register names with standard convension, please use CAN_MO255_EDATA3.
+*/
+#define CAN_EMO255DATA3 (CAN_MO255_EDATA3)
+
+/** \brief 2FF0, Message Object Data Register Low */
+#define CAN_MO255_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF001AFF0u)
+
+/** Alias (User Manual Name) for CAN_MO255_EDATA4.
+* To use register names with standard convension, please use CAN_MO255_EDATA4.
+*/
+#define CAN_EMO255DATA4 (CAN_MO255_EDATA4)
+
+/** \brief 2FF4, Message Object Data Register High */
+#define CAN_MO255_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF001AFF4u)
+
+/** Alias (User Manual Name) for CAN_MO255_EDATA5.
+* To use register names with standard convension, please use CAN_MO255_EDATA5.
+*/
+#define CAN_EMO255DATA5 (CAN_MO255_EDATA5)
+
+/** \brief 2FF8, Message Object Arbitration Register */
+#define CAN_MO255_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF001AFF8u)
+
+/** Alias (User Manual Name) for CAN_MO255_EDATA6.
+* To use register names with standard convension, please use CAN_MO255_EDATA6.
+*/
+#define CAN_EMO255DATA6 (CAN_MO255_EDATA6)
+
+/** \brief 2FE0, Message Object Function Control Register */
+#define CAN_MO255_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF001AFE0u)
+
+/** Alias (User Manual Name) for CAN_MO255_FCR.
+* To use register names with standard convension, please use CAN_MO255_FCR.
+*/
+#define CAN_MOFCR255 (CAN_MO255_FCR)
+
+/** \brief 2FE4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO255_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF001AFE4u)
+
+/** Alias (User Manual Name) for CAN_MO255_FGPR.
+* To use register names with standard convension, please use CAN_MO255_FGPR.
+*/
+#define CAN_MOFGPR255 (CAN_MO255_FGPR)
+
+/** \brief 2FE8, Message Object Interrupt Pointer Register */
+#define CAN_MO255_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF001AFE8u)
+
+/** Alias (User Manual Name) for CAN_MO255_IPR.
+* To use register names with standard convension, please use CAN_MO255_IPR.
+*/
+#define CAN_MOIPR255 (CAN_MO255_IPR)
+
+/** \brief 2FFC, Message Object Control Register */
+#define CAN_MO255_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001AFFCu)
+
+/** Alias (User Manual Name) for CAN_MO255_STAT.
+* To use register names with standard convension, please use CAN_MO255_STAT.
+*/
+#define CAN_MOSTAT255 (CAN_MO255_STAT)
+
+/** \brief 132C, Message Object Acceptance Mask Register */
+#define CAN_MO25_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001932Cu)
+
+/** Alias (User Manual Name) for CAN_MO25_AMR.
+* To use register names with standard convension, please use CAN_MO25_AMR.
+*/
+#define CAN_MOAMR25 (CAN_MO25_AMR)
+
+/** \brief 1338, Message Object Arbitration Register */
+#define CAN_MO25_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019338u)
+
+/** Alias (User Manual Name) for CAN_MO25_AR.
+* To use register names with standard convension, please use CAN_MO25_AR.
+*/
+#define CAN_MOAR25 (CAN_MO25_AR)
+
+/** \brief 133C, Message Object Control Register */
+#define CAN_MO25_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001933Cu)
+
+/** Alias (User Manual Name) for CAN_MO25_CTR.
+* To use register names with standard convension, please use CAN_MO25_CTR.
+*/
+#define CAN_MOCTR25 (CAN_MO25_CTR)
+
+/** \brief 1334, Message Object Data Register High */
+#define CAN_MO25_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019334u)
+
+/** Alias (User Manual Name) for CAN_MO25_DATAH.
+* To use register names with standard convension, please use CAN_MO25_DATAH.
+*/
+#define CAN_MODATAH25 (CAN_MO25_DATAH)
+
+/** \brief 1330, Message Object Data Register Low */
+#define CAN_MO25_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019330u)
+
+/** Alias (User Manual Name) for CAN_MO25_DATAL.
+* To use register names with standard convension, please use CAN_MO25_DATAL.
+*/
+#define CAN_MODATAL25 (CAN_MO25_DATAL)
+
+/** \brief 1320, Message Object Function Control Register */
+#define CAN_MO25_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019320u)
+
+/** Alias (User Manual Name) for CAN_MO25_EDATA0.
+* To use register names with standard convension, please use CAN_MO25_EDATA0.
+*/
+#define CAN_EMO25DATA0 (CAN_MO25_EDATA0)
+
+/** \brief 1324, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO25_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019324u)
+
+/** Alias (User Manual Name) for CAN_MO25_EDATA1.
+* To use register names with standard convension, please use CAN_MO25_EDATA1.
+*/
+#define CAN_EMO25DATA1 (CAN_MO25_EDATA1)
+
+/** \brief 1328, Message Object Interrupt Pointer Register */
+#define CAN_MO25_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019328u)
+
+/** Alias (User Manual Name) for CAN_MO25_EDATA2.
+* To use register names with standard convension, please use CAN_MO25_EDATA2.
+*/
+#define CAN_EMO25DATA2 (CAN_MO25_EDATA2)
+
+/** \brief 132C, Message Object Acceptance Mask Register */
+#define CAN_MO25_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001932Cu)
+
+/** Alias (User Manual Name) for CAN_MO25_EDATA3.
+* To use register names with standard convension, please use CAN_MO25_EDATA3.
+*/
+#define CAN_EMO25DATA3 (CAN_MO25_EDATA3)
+
+/** \brief 1330, Message Object Data Register Low */
+#define CAN_MO25_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019330u)
+
+/** Alias (User Manual Name) for CAN_MO25_EDATA4.
+* To use register names with standard convension, please use CAN_MO25_EDATA4.
+*/
+#define CAN_EMO25DATA4 (CAN_MO25_EDATA4)
+
+/** \brief 1334, Message Object Data Register High */
+#define CAN_MO25_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019334u)
+
+/** Alias (User Manual Name) for CAN_MO25_EDATA5.
+* To use register names with standard convension, please use CAN_MO25_EDATA5.
+*/
+#define CAN_EMO25DATA5 (CAN_MO25_EDATA5)
+
+/** \brief 1338, Message Object Arbitration Register */
+#define CAN_MO25_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019338u)
+
+/** Alias (User Manual Name) for CAN_MO25_EDATA6.
+* To use register names with standard convension, please use CAN_MO25_EDATA6.
+*/
+#define CAN_EMO25DATA6 (CAN_MO25_EDATA6)
+
+/** \brief 1320, Message Object Function Control Register */
+#define CAN_MO25_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019320u)
+
+/** Alias (User Manual Name) for CAN_MO25_FCR.
+* To use register names with standard convension, please use CAN_MO25_FCR.
+*/
+#define CAN_MOFCR25 (CAN_MO25_FCR)
+
+/** \brief 1324, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO25_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019324u)
+
+/** Alias (User Manual Name) for CAN_MO25_FGPR.
+* To use register names with standard convension, please use CAN_MO25_FGPR.
+*/
+#define CAN_MOFGPR25 (CAN_MO25_FGPR)
+
+/** \brief 1328, Message Object Interrupt Pointer Register */
+#define CAN_MO25_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019328u)
+
+/** Alias (User Manual Name) for CAN_MO25_IPR.
+* To use register names with standard convension, please use CAN_MO25_IPR.
+*/
+#define CAN_MOIPR25 (CAN_MO25_IPR)
+
+/** \brief 133C, Message Object Control Register */
+#define CAN_MO25_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001933Cu)
+
+/** Alias (User Manual Name) for CAN_MO25_STAT.
+* To use register names with standard convension, please use CAN_MO25_STAT.
+*/
+#define CAN_MOSTAT25 (CAN_MO25_STAT)
+
+/** \brief 134C, Message Object Acceptance Mask Register */
+#define CAN_MO26_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001934Cu)
+
+/** Alias (User Manual Name) for CAN_MO26_AMR.
+* To use register names with standard convension, please use CAN_MO26_AMR.
+*/
+#define CAN_MOAMR26 (CAN_MO26_AMR)
+
+/** \brief 1358, Message Object Arbitration Register */
+#define CAN_MO26_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019358u)
+
+/** Alias (User Manual Name) for CAN_MO26_AR.
+* To use register names with standard convension, please use CAN_MO26_AR.
+*/
+#define CAN_MOAR26 (CAN_MO26_AR)
+
+/** \brief 135C, Message Object Control Register */
+#define CAN_MO26_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001935Cu)
+
+/** Alias (User Manual Name) for CAN_MO26_CTR.
+* To use register names with standard convension, please use CAN_MO26_CTR.
+*/
+#define CAN_MOCTR26 (CAN_MO26_CTR)
+
+/** \brief 1354, Message Object Data Register High */
+#define CAN_MO26_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019354u)
+
+/** Alias (User Manual Name) for CAN_MO26_DATAH.
+* To use register names with standard convension, please use CAN_MO26_DATAH.
+*/
+#define CAN_MODATAH26 (CAN_MO26_DATAH)
+
+/** \brief 1350, Message Object Data Register Low */
+#define CAN_MO26_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019350u)
+
+/** Alias (User Manual Name) for CAN_MO26_DATAL.
+* To use register names with standard convension, please use CAN_MO26_DATAL.
+*/
+#define CAN_MODATAL26 (CAN_MO26_DATAL)
+
+/** \brief 1340, Message Object Function Control Register */
+#define CAN_MO26_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019340u)
+
+/** Alias (User Manual Name) for CAN_MO26_EDATA0.
+* To use register names with standard convension, please use CAN_MO26_EDATA0.
+*/
+#define CAN_EMO26DATA0 (CAN_MO26_EDATA0)
+
+/** \brief 1344, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO26_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019344u)
+
+/** Alias (User Manual Name) for CAN_MO26_EDATA1.
+* To use register names with standard convension, please use CAN_MO26_EDATA1.
+*/
+#define CAN_EMO26DATA1 (CAN_MO26_EDATA1)
+
+/** \brief 1348, Message Object Interrupt Pointer Register */
+#define CAN_MO26_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019348u)
+
+/** Alias (User Manual Name) for CAN_MO26_EDATA2.
+* To use register names with standard convension, please use CAN_MO26_EDATA2.
+*/
+#define CAN_EMO26DATA2 (CAN_MO26_EDATA2)
+
+/** \brief 134C, Message Object Acceptance Mask Register */
+#define CAN_MO26_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001934Cu)
+
+/** Alias (User Manual Name) for CAN_MO26_EDATA3.
+* To use register names with standard convension, please use CAN_MO26_EDATA3.
+*/
+#define CAN_EMO26DATA3 (CAN_MO26_EDATA3)
+
+/** \brief 1350, Message Object Data Register Low */
+#define CAN_MO26_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019350u)
+
+/** Alias (User Manual Name) for CAN_MO26_EDATA4.
+* To use register names with standard convension, please use CAN_MO26_EDATA4.
+*/
+#define CAN_EMO26DATA4 (CAN_MO26_EDATA4)
+
+/** \brief 1354, Message Object Data Register High */
+#define CAN_MO26_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019354u)
+
+/** Alias (User Manual Name) for CAN_MO26_EDATA5.
+* To use register names with standard convension, please use CAN_MO26_EDATA5.
+*/
+#define CAN_EMO26DATA5 (CAN_MO26_EDATA5)
+
+/** \brief 1358, Message Object Arbitration Register */
+#define CAN_MO26_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019358u)
+
+/** Alias (User Manual Name) for CAN_MO26_EDATA6.
+* To use register names with standard convension, please use CAN_MO26_EDATA6.
+*/
+#define CAN_EMO26DATA6 (CAN_MO26_EDATA6)
+
+/** \brief 1340, Message Object Function Control Register */
+#define CAN_MO26_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019340u)
+
+/** Alias (User Manual Name) for CAN_MO26_FCR.
+* To use register names with standard convension, please use CAN_MO26_FCR.
+*/
+#define CAN_MOFCR26 (CAN_MO26_FCR)
+
+/** \brief 1344, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO26_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019344u)
+
+/** Alias (User Manual Name) for CAN_MO26_FGPR.
+* To use register names with standard convension, please use CAN_MO26_FGPR.
+*/
+#define CAN_MOFGPR26 (CAN_MO26_FGPR)
+
+/** \brief 1348, Message Object Interrupt Pointer Register */
+#define CAN_MO26_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019348u)
+
+/** Alias (User Manual Name) for CAN_MO26_IPR.
+* To use register names with standard convension, please use CAN_MO26_IPR.
+*/
+#define CAN_MOIPR26 (CAN_MO26_IPR)
+
+/** \brief 135C, Message Object Control Register */
+#define CAN_MO26_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001935Cu)
+
+/** Alias (User Manual Name) for CAN_MO26_STAT.
+* To use register names with standard convension, please use CAN_MO26_STAT.
+*/
+#define CAN_MOSTAT26 (CAN_MO26_STAT)
+
+/** \brief 136C, Message Object Acceptance Mask Register */
+#define CAN_MO27_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001936Cu)
+
+/** Alias (User Manual Name) for CAN_MO27_AMR.
+* To use register names with standard convension, please use CAN_MO27_AMR.
+*/
+#define CAN_MOAMR27 (CAN_MO27_AMR)
+
+/** \brief 1378, Message Object Arbitration Register */
+#define CAN_MO27_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019378u)
+
+/** Alias (User Manual Name) for CAN_MO27_AR.
+* To use register names with standard convension, please use CAN_MO27_AR.
+*/
+#define CAN_MOAR27 (CAN_MO27_AR)
+
+/** \brief 137C, Message Object Control Register */
+#define CAN_MO27_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001937Cu)
+
+/** Alias (User Manual Name) for CAN_MO27_CTR.
+* To use register names with standard convension, please use CAN_MO27_CTR.
+*/
+#define CAN_MOCTR27 (CAN_MO27_CTR)
+
+/** \brief 1374, Message Object Data Register High */
+#define CAN_MO27_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019374u)
+
+/** Alias (User Manual Name) for CAN_MO27_DATAH.
+* To use register names with standard convension, please use CAN_MO27_DATAH.
+*/
+#define CAN_MODATAH27 (CAN_MO27_DATAH)
+
+/** \brief 1370, Message Object Data Register Low */
+#define CAN_MO27_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019370u)
+
+/** Alias (User Manual Name) for CAN_MO27_DATAL.
+* To use register names with standard convension, please use CAN_MO27_DATAL.
+*/
+#define CAN_MODATAL27 (CAN_MO27_DATAL)
+
+/** \brief 1360, Message Object Function Control Register */
+#define CAN_MO27_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019360u)
+
+/** Alias (User Manual Name) for CAN_MO27_EDATA0.
+* To use register names with standard convension, please use CAN_MO27_EDATA0.
+*/
+#define CAN_EMO27DATA0 (CAN_MO27_EDATA0)
+
+/** \brief 1364, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO27_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019364u)
+
+/** Alias (User Manual Name) for CAN_MO27_EDATA1.
+* To use register names with standard convension, please use CAN_MO27_EDATA1.
+*/
+#define CAN_EMO27DATA1 (CAN_MO27_EDATA1)
+
+/** \brief 1368, Message Object Interrupt Pointer Register */
+#define CAN_MO27_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019368u)
+
+/** Alias (User Manual Name) for CAN_MO27_EDATA2.
+* To use register names with standard convension, please use CAN_MO27_EDATA2.
+*/
+#define CAN_EMO27DATA2 (CAN_MO27_EDATA2)
+
+/** \brief 136C, Message Object Acceptance Mask Register */
+#define CAN_MO27_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001936Cu)
+
+/** Alias (User Manual Name) for CAN_MO27_EDATA3.
+* To use register names with standard convension, please use CAN_MO27_EDATA3.
+*/
+#define CAN_EMO27DATA3 (CAN_MO27_EDATA3)
+
+/** \brief 1370, Message Object Data Register Low */
+#define CAN_MO27_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019370u)
+
+/** Alias (User Manual Name) for CAN_MO27_EDATA4.
+* To use register names with standard convension, please use CAN_MO27_EDATA4.
+*/
+#define CAN_EMO27DATA4 (CAN_MO27_EDATA4)
+
+/** \brief 1374, Message Object Data Register High */
+#define CAN_MO27_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019374u)
+
+/** Alias (User Manual Name) for CAN_MO27_EDATA5.
+* To use register names with standard convension, please use CAN_MO27_EDATA5.
+*/
+#define CAN_EMO27DATA5 (CAN_MO27_EDATA5)
+
+/** \brief 1378, Message Object Arbitration Register */
+#define CAN_MO27_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019378u)
+
+/** Alias (User Manual Name) for CAN_MO27_EDATA6.
+* To use register names with standard convension, please use CAN_MO27_EDATA6.
+*/
+#define CAN_EMO27DATA6 (CAN_MO27_EDATA6)
+
+/** \brief 1360, Message Object Function Control Register */
+#define CAN_MO27_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019360u)
+
+/** Alias (User Manual Name) for CAN_MO27_FCR.
+* To use register names with standard convension, please use CAN_MO27_FCR.
+*/
+#define CAN_MOFCR27 (CAN_MO27_FCR)
+
+/** \brief 1364, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO27_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019364u)
+
+/** Alias (User Manual Name) for CAN_MO27_FGPR.
+* To use register names with standard convension, please use CAN_MO27_FGPR.
+*/
+#define CAN_MOFGPR27 (CAN_MO27_FGPR)
+
+/** \brief 1368, Message Object Interrupt Pointer Register */
+#define CAN_MO27_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019368u)
+
+/** Alias (User Manual Name) for CAN_MO27_IPR.
+* To use register names with standard convension, please use CAN_MO27_IPR.
+*/
+#define CAN_MOIPR27 (CAN_MO27_IPR)
+
+/** \brief 137C, Message Object Control Register */
+#define CAN_MO27_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001937Cu)
+
+/** Alias (User Manual Name) for CAN_MO27_STAT.
+* To use register names with standard convension, please use CAN_MO27_STAT.
+*/
+#define CAN_MOSTAT27 (CAN_MO27_STAT)
+
+/** \brief 138C, Message Object Acceptance Mask Register */
+#define CAN_MO28_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001938Cu)
+
+/** Alias (User Manual Name) for CAN_MO28_AMR.
+* To use register names with standard convension, please use CAN_MO28_AMR.
+*/
+#define CAN_MOAMR28 (CAN_MO28_AMR)
+
+/** \brief 1398, Message Object Arbitration Register */
+#define CAN_MO28_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019398u)
+
+/** Alias (User Manual Name) for CAN_MO28_AR.
+* To use register names with standard convension, please use CAN_MO28_AR.
+*/
+#define CAN_MOAR28 (CAN_MO28_AR)
+
+/** \brief 139C, Message Object Control Register */
+#define CAN_MO28_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001939Cu)
+
+/** Alias (User Manual Name) for CAN_MO28_CTR.
+* To use register names with standard convension, please use CAN_MO28_CTR.
+*/
+#define CAN_MOCTR28 (CAN_MO28_CTR)
+
+/** \brief 1394, Message Object Data Register High */
+#define CAN_MO28_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019394u)
+
+/** Alias (User Manual Name) for CAN_MO28_DATAH.
+* To use register names with standard convension, please use CAN_MO28_DATAH.
+*/
+#define CAN_MODATAH28 (CAN_MO28_DATAH)
+
+/** \brief 1390, Message Object Data Register Low */
+#define CAN_MO28_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019390u)
+
+/** Alias (User Manual Name) for CAN_MO28_DATAL.
+* To use register names with standard convension, please use CAN_MO28_DATAL.
+*/
+#define CAN_MODATAL28 (CAN_MO28_DATAL)
+
+/** \brief 1380, Message Object Function Control Register */
+#define CAN_MO28_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019380u)
+
+/** Alias (User Manual Name) for CAN_MO28_EDATA0.
+* To use register names with standard convension, please use CAN_MO28_EDATA0.
+*/
+#define CAN_EMO28DATA0 (CAN_MO28_EDATA0)
+
+/** \brief 1384, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO28_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019384u)
+
+/** Alias (User Manual Name) for CAN_MO28_EDATA1.
+* To use register names with standard convension, please use CAN_MO28_EDATA1.
+*/
+#define CAN_EMO28DATA1 (CAN_MO28_EDATA1)
+
+/** \brief 1388, Message Object Interrupt Pointer Register */
+#define CAN_MO28_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019388u)
+
+/** Alias (User Manual Name) for CAN_MO28_EDATA2.
+* To use register names with standard convension, please use CAN_MO28_EDATA2.
+*/
+#define CAN_EMO28DATA2 (CAN_MO28_EDATA2)
+
+/** \brief 138C, Message Object Acceptance Mask Register */
+#define CAN_MO28_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001938Cu)
+
+/** Alias (User Manual Name) for CAN_MO28_EDATA3.
+* To use register names with standard convension, please use CAN_MO28_EDATA3.
+*/
+#define CAN_EMO28DATA3 (CAN_MO28_EDATA3)
+
+/** \brief 1390, Message Object Data Register Low */
+#define CAN_MO28_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019390u)
+
+/** Alias (User Manual Name) for CAN_MO28_EDATA4.
+* To use register names with standard convension, please use CAN_MO28_EDATA4.
+*/
+#define CAN_EMO28DATA4 (CAN_MO28_EDATA4)
+
+/** \brief 1394, Message Object Data Register High */
+#define CAN_MO28_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019394u)
+
+/** Alias (User Manual Name) for CAN_MO28_EDATA5.
+* To use register names with standard convension, please use CAN_MO28_EDATA5.
+*/
+#define CAN_EMO28DATA5 (CAN_MO28_EDATA5)
+
+/** \brief 1398, Message Object Arbitration Register */
+#define CAN_MO28_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019398u)
+
+/** Alias (User Manual Name) for CAN_MO28_EDATA6.
+* To use register names with standard convension, please use CAN_MO28_EDATA6.
+*/
+#define CAN_EMO28DATA6 (CAN_MO28_EDATA6)
+
+/** \brief 1380, Message Object Function Control Register */
+#define CAN_MO28_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019380u)
+
+/** Alias (User Manual Name) for CAN_MO28_FCR.
+* To use register names with standard convension, please use CAN_MO28_FCR.
+*/
+#define CAN_MOFCR28 (CAN_MO28_FCR)
+
+/** \brief 1384, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO28_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019384u)
+
+/** Alias (User Manual Name) for CAN_MO28_FGPR.
+* To use register names with standard convension, please use CAN_MO28_FGPR.
+*/
+#define CAN_MOFGPR28 (CAN_MO28_FGPR)
+
+/** \brief 1388, Message Object Interrupt Pointer Register */
+#define CAN_MO28_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019388u)
+
+/** Alias (User Manual Name) for CAN_MO28_IPR.
+* To use register names with standard convension, please use CAN_MO28_IPR.
+*/
+#define CAN_MOIPR28 (CAN_MO28_IPR)
+
+/** \brief 139C, Message Object Control Register */
+#define CAN_MO28_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001939Cu)
+
+/** Alias (User Manual Name) for CAN_MO28_STAT.
+* To use register names with standard convension, please use CAN_MO28_STAT.
+*/
+#define CAN_MOSTAT28 (CAN_MO28_STAT)
+
+/** \brief 13AC, Message Object Acceptance Mask Register */
+#define CAN_MO29_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00193ACu)
+
+/** Alias (User Manual Name) for CAN_MO29_AMR.
+* To use register names with standard convension, please use CAN_MO29_AMR.
+*/
+#define CAN_MOAMR29 (CAN_MO29_AMR)
+
+/** \brief 13B8, Message Object Arbitration Register */
+#define CAN_MO29_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00193B8u)
+
+/** Alias (User Manual Name) for CAN_MO29_AR.
+* To use register names with standard convension, please use CAN_MO29_AR.
+*/
+#define CAN_MOAR29 (CAN_MO29_AR)
+
+/** \brief 13BC, Message Object Control Register */
+#define CAN_MO29_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00193BCu)
+
+/** Alias (User Manual Name) for CAN_MO29_CTR.
+* To use register names with standard convension, please use CAN_MO29_CTR.
+*/
+#define CAN_MOCTR29 (CAN_MO29_CTR)
+
+/** \brief 13B4, Message Object Data Register High */
+#define CAN_MO29_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00193B4u)
+
+/** Alias (User Manual Name) for CAN_MO29_DATAH.
+* To use register names with standard convension, please use CAN_MO29_DATAH.
+*/
+#define CAN_MODATAH29 (CAN_MO29_DATAH)
+
+/** \brief 13B0, Message Object Data Register Low */
+#define CAN_MO29_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00193B0u)
+
+/** Alias (User Manual Name) for CAN_MO29_DATAL.
+* To use register names with standard convension, please use CAN_MO29_DATAL.
+*/
+#define CAN_MODATAL29 (CAN_MO29_DATAL)
+
+/** \brief 13A0, Message Object Function Control Register */
+#define CAN_MO29_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00193A0u)
+
+/** Alias (User Manual Name) for CAN_MO29_EDATA0.
+* To use register names with standard convension, please use CAN_MO29_EDATA0.
+*/
+#define CAN_EMO29DATA0 (CAN_MO29_EDATA0)
+
+/** \brief 13A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO29_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00193A4u)
+
+/** Alias (User Manual Name) for CAN_MO29_EDATA1.
+* To use register names with standard convension, please use CAN_MO29_EDATA1.
+*/
+#define CAN_EMO29DATA1 (CAN_MO29_EDATA1)
+
+/** \brief 13A8, Message Object Interrupt Pointer Register */
+#define CAN_MO29_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00193A8u)
+
+/** Alias (User Manual Name) for CAN_MO29_EDATA2.
+* To use register names with standard convension, please use CAN_MO29_EDATA2.
+*/
+#define CAN_EMO29DATA2 (CAN_MO29_EDATA2)
+
+/** \brief 13AC, Message Object Acceptance Mask Register */
+#define CAN_MO29_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00193ACu)
+
+/** Alias (User Manual Name) for CAN_MO29_EDATA3.
+* To use register names with standard convension, please use CAN_MO29_EDATA3.
+*/
+#define CAN_EMO29DATA3 (CAN_MO29_EDATA3)
+
+/** \brief 13B0, Message Object Data Register Low */
+#define CAN_MO29_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00193B0u)
+
+/** Alias (User Manual Name) for CAN_MO29_EDATA4.
+* To use register names with standard convension, please use CAN_MO29_EDATA4.
+*/
+#define CAN_EMO29DATA4 (CAN_MO29_EDATA4)
+
+/** \brief 13B4, Message Object Data Register High */
+#define CAN_MO29_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00193B4u)
+
+/** Alias (User Manual Name) for CAN_MO29_EDATA5.
+* To use register names with standard convension, please use CAN_MO29_EDATA5.
+*/
+#define CAN_EMO29DATA5 (CAN_MO29_EDATA5)
+
+/** \brief 13B8, Message Object Arbitration Register */
+#define CAN_MO29_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00193B8u)
+
+/** Alias (User Manual Name) for CAN_MO29_EDATA6.
+* To use register names with standard convension, please use CAN_MO29_EDATA6.
+*/
+#define CAN_EMO29DATA6 (CAN_MO29_EDATA6)
+
+/** \brief 13A0, Message Object Function Control Register */
+#define CAN_MO29_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00193A0u)
+
+/** Alias (User Manual Name) for CAN_MO29_FCR.
+* To use register names with standard convension, please use CAN_MO29_FCR.
+*/
+#define CAN_MOFCR29 (CAN_MO29_FCR)
+
+/** \brief 13A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO29_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00193A4u)
+
+/** Alias (User Manual Name) for CAN_MO29_FGPR.
+* To use register names with standard convension, please use CAN_MO29_FGPR.
+*/
+#define CAN_MOFGPR29 (CAN_MO29_FGPR)
+
+/** \brief 13A8, Message Object Interrupt Pointer Register */
+#define CAN_MO29_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00193A8u)
+
+/** Alias (User Manual Name) for CAN_MO29_IPR.
+* To use register names with standard convension, please use CAN_MO29_IPR.
+*/
+#define CAN_MOIPR29 (CAN_MO29_IPR)
+
+/** \brief 13BC, Message Object Control Register */
+#define CAN_MO29_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00193BCu)
+
+/** Alias (User Manual Name) for CAN_MO29_STAT.
+* To use register names with standard convension, please use CAN_MO29_STAT.
+*/
+#define CAN_MOSTAT29 (CAN_MO29_STAT)
+
+/** \brief 104C, Message Object Acceptance Mask Register */
+#define CAN_MO2_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001904Cu)
+
+/** Alias (User Manual Name) for CAN_MO2_AMR.
+* To use register names with standard convension, please use CAN_MO2_AMR.
+*/
+#define CAN_MOAMR2 (CAN_MO2_AMR)
+
+/** \brief 1058, Message Object Arbitration Register */
+#define CAN_MO2_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019058u)
+
+/** Alias (User Manual Name) for CAN_MO2_AR.
+* To use register names with standard convension, please use CAN_MO2_AR.
+*/
+#define CAN_MOAR2 (CAN_MO2_AR)
+
+/** \brief 105C, Message Object Control Register */
+#define CAN_MO2_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001905Cu)
+
+/** Alias (User Manual Name) for CAN_MO2_CTR.
+* To use register names with standard convension, please use CAN_MO2_CTR.
+*/
+#define CAN_MOCTR2 (CAN_MO2_CTR)
+
+/** \brief 1054, Message Object Data Register High */
+#define CAN_MO2_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019054u)
+
+/** Alias (User Manual Name) for CAN_MO2_DATAH.
+* To use register names with standard convension, please use CAN_MO2_DATAH.
+*/
+#define CAN_MODATAH2 (CAN_MO2_DATAH)
+
+/** \brief 1050, Message Object Data Register Low */
+#define CAN_MO2_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019050u)
+
+/** Alias (User Manual Name) for CAN_MO2_DATAL.
+* To use register names with standard convension, please use CAN_MO2_DATAL.
+*/
+#define CAN_MODATAL2 (CAN_MO2_DATAL)
+
+/** \brief 1040, Message Object Function Control Register */
+#define CAN_MO2_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019040u)
+
+/** Alias (User Manual Name) for CAN_MO2_EDATA0.
+* To use register names with standard convension, please use CAN_MO2_EDATA0.
+*/
+#define CAN_EMO2DATA0 (CAN_MO2_EDATA0)
+
+/** \brief 1044, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO2_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019044u)
+
+/** Alias (User Manual Name) for CAN_MO2_EDATA1.
+* To use register names with standard convension, please use CAN_MO2_EDATA1.
+*/
+#define CAN_EMO2DATA1 (CAN_MO2_EDATA1)
+
+/** \brief 1048, Message Object Interrupt Pointer Register */
+#define CAN_MO2_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019048u)
+
+/** Alias (User Manual Name) for CAN_MO2_EDATA2.
+* To use register names with standard convension, please use CAN_MO2_EDATA2.
+*/
+#define CAN_EMO2DATA2 (CAN_MO2_EDATA2)
+
+/** \brief 104C, Message Object Acceptance Mask Register */
+#define CAN_MO2_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001904Cu)
+
+/** Alias (User Manual Name) for CAN_MO2_EDATA3.
+* To use register names with standard convension, please use CAN_MO2_EDATA3.
+*/
+#define CAN_EMO2DATA3 (CAN_MO2_EDATA3)
+
+/** \brief 1050, Message Object Data Register Low */
+#define CAN_MO2_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019050u)
+
+/** Alias (User Manual Name) for CAN_MO2_EDATA4.
+* To use register names with standard convension, please use CAN_MO2_EDATA4.
+*/
+#define CAN_EMO2DATA4 (CAN_MO2_EDATA4)
+
+/** \brief 1054, Message Object Data Register High */
+#define CAN_MO2_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019054u)
+
+/** Alias (User Manual Name) for CAN_MO2_EDATA5.
+* To use register names with standard convension, please use CAN_MO2_EDATA5.
+*/
+#define CAN_EMO2DATA5 (CAN_MO2_EDATA5)
+
+/** \brief 1058, Message Object Arbitration Register */
+#define CAN_MO2_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019058u)
+
+/** Alias (User Manual Name) for CAN_MO2_EDATA6.
+* To use register names with standard convension, please use CAN_MO2_EDATA6.
+*/
+#define CAN_EMO2DATA6 (CAN_MO2_EDATA6)
+
+/** \brief 1040, Message Object Function Control Register */
+#define CAN_MO2_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019040u)
+
+/** Alias (User Manual Name) for CAN_MO2_FCR.
+* To use register names with standard convension, please use CAN_MO2_FCR.
+*/
+#define CAN_MOFCR2 (CAN_MO2_FCR)
+
+/** \brief 1044, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO2_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019044u)
+
+/** Alias (User Manual Name) for CAN_MO2_FGPR.
+* To use register names with standard convension, please use CAN_MO2_FGPR.
+*/
+#define CAN_MOFGPR2 (CAN_MO2_FGPR)
+
+/** \brief 1048, Message Object Interrupt Pointer Register */
+#define CAN_MO2_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019048u)
+
+/** Alias (User Manual Name) for CAN_MO2_IPR.
+* To use register names with standard convension, please use CAN_MO2_IPR.
+*/
+#define CAN_MOIPR2 (CAN_MO2_IPR)
+
+/** \brief 105C, Message Object Control Register */
+#define CAN_MO2_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001905Cu)
+
+/** Alias (User Manual Name) for CAN_MO2_STAT.
+* To use register names with standard convension, please use CAN_MO2_STAT.
+*/
+#define CAN_MOSTAT2 (CAN_MO2_STAT)
+
+/** \brief 13CC, Message Object Acceptance Mask Register */
+#define CAN_MO30_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00193CCu)
+
+/** Alias (User Manual Name) for CAN_MO30_AMR.
+* To use register names with standard convension, please use CAN_MO30_AMR.
+*/
+#define CAN_MOAMR30 (CAN_MO30_AMR)
+
+/** \brief 13D8, Message Object Arbitration Register */
+#define CAN_MO30_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00193D8u)
+
+/** Alias (User Manual Name) for CAN_MO30_AR.
+* To use register names with standard convension, please use CAN_MO30_AR.
+*/
+#define CAN_MOAR30 (CAN_MO30_AR)
+
+/** \brief 13DC, Message Object Control Register */
+#define CAN_MO30_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00193DCu)
+
+/** Alias (User Manual Name) for CAN_MO30_CTR.
+* To use register names with standard convension, please use CAN_MO30_CTR.
+*/
+#define CAN_MOCTR30 (CAN_MO30_CTR)
+
+/** \brief 13D4, Message Object Data Register High */
+#define CAN_MO30_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00193D4u)
+
+/** Alias (User Manual Name) for CAN_MO30_DATAH.
+* To use register names with standard convension, please use CAN_MO30_DATAH.
+*/
+#define CAN_MODATAH30 (CAN_MO30_DATAH)
+
+/** \brief 13D0, Message Object Data Register Low */
+#define CAN_MO30_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00193D0u)
+
+/** Alias (User Manual Name) for CAN_MO30_DATAL.
+* To use register names with standard convension, please use CAN_MO30_DATAL.
+*/
+#define CAN_MODATAL30 (CAN_MO30_DATAL)
+
+/** \brief 13C0, Message Object Function Control Register */
+#define CAN_MO30_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00193C0u)
+
+/** Alias (User Manual Name) for CAN_MO30_EDATA0.
+* To use register names with standard convension, please use CAN_MO30_EDATA0.
+*/
+#define CAN_EMO30DATA0 (CAN_MO30_EDATA0)
+
+/** \brief 13C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO30_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00193C4u)
+
+/** Alias (User Manual Name) for CAN_MO30_EDATA1.
+* To use register names with standard convension, please use CAN_MO30_EDATA1.
+*/
+#define CAN_EMO30DATA1 (CAN_MO30_EDATA1)
+
+/** \brief 13C8, Message Object Interrupt Pointer Register */
+#define CAN_MO30_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00193C8u)
+
+/** Alias (User Manual Name) for CAN_MO30_EDATA2.
+* To use register names with standard convension, please use CAN_MO30_EDATA2.
+*/
+#define CAN_EMO30DATA2 (CAN_MO30_EDATA2)
+
+/** \brief 13CC, Message Object Acceptance Mask Register */
+#define CAN_MO30_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00193CCu)
+
+/** Alias (User Manual Name) for CAN_MO30_EDATA3.
+* To use register names with standard convension, please use CAN_MO30_EDATA3.
+*/
+#define CAN_EMO30DATA3 (CAN_MO30_EDATA3)
+
+/** \brief 13D0, Message Object Data Register Low */
+#define CAN_MO30_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00193D0u)
+
+/** Alias (User Manual Name) for CAN_MO30_EDATA4.
+* To use register names with standard convension, please use CAN_MO30_EDATA4.
+*/
+#define CAN_EMO30DATA4 (CAN_MO30_EDATA4)
+
+/** \brief 13D4, Message Object Data Register High */
+#define CAN_MO30_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00193D4u)
+
+/** Alias (User Manual Name) for CAN_MO30_EDATA5.
+* To use register names with standard convension, please use CAN_MO30_EDATA5.
+*/
+#define CAN_EMO30DATA5 (CAN_MO30_EDATA5)
+
+/** \brief 13D8, Message Object Arbitration Register */
+#define CAN_MO30_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00193D8u)
+
+/** Alias (User Manual Name) for CAN_MO30_EDATA6.
+* To use register names with standard convension, please use CAN_MO30_EDATA6.
+*/
+#define CAN_EMO30DATA6 (CAN_MO30_EDATA6)
+
+/** \brief 13C0, Message Object Function Control Register */
+#define CAN_MO30_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00193C0u)
+
+/** Alias (User Manual Name) for CAN_MO30_FCR.
+* To use register names with standard convension, please use CAN_MO30_FCR.
+*/
+#define CAN_MOFCR30 (CAN_MO30_FCR)
+
+/** \brief 13C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO30_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00193C4u)
+
+/** Alias (User Manual Name) for CAN_MO30_FGPR.
+* To use register names with standard convension, please use CAN_MO30_FGPR.
+*/
+#define CAN_MOFGPR30 (CAN_MO30_FGPR)
+
+/** \brief 13C8, Message Object Interrupt Pointer Register */
+#define CAN_MO30_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00193C8u)
+
+/** Alias (User Manual Name) for CAN_MO30_IPR.
+* To use register names with standard convension, please use CAN_MO30_IPR.
+*/
+#define CAN_MOIPR30 (CAN_MO30_IPR)
+
+/** \brief 13DC, Message Object Control Register */
+#define CAN_MO30_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00193DCu)
+
+/** Alias (User Manual Name) for CAN_MO30_STAT.
+* To use register names with standard convension, please use CAN_MO30_STAT.
+*/
+#define CAN_MOSTAT30 (CAN_MO30_STAT)
+
+/** \brief 13EC, Message Object Acceptance Mask Register */
+#define CAN_MO31_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00193ECu)
+
+/** Alias (User Manual Name) for CAN_MO31_AMR.
+* To use register names with standard convension, please use CAN_MO31_AMR.
+*/
+#define CAN_MOAMR31 (CAN_MO31_AMR)
+
+/** \brief 13F8, Message Object Arbitration Register */
+#define CAN_MO31_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00193F8u)
+
+/** Alias (User Manual Name) for CAN_MO31_AR.
+* To use register names with standard convension, please use CAN_MO31_AR.
+*/
+#define CAN_MOAR31 (CAN_MO31_AR)
+
+/** \brief 13FC, Message Object Control Register */
+#define CAN_MO31_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00193FCu)
+
+/** Alias (User Manual Name) for CAN_MO31_CTR.
+* To use register names with standard convension, please use CAN_MO31_CTR.
+*/
+#define CAN_MOCTR31 (CAN_MO31_CTR)
+
+/** \brief 13F4, Message Object Data Register High */
+#define CAN_MO31_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00193F4u)
+
+/** Alias (User Manual Name) for CAN_MO31_DATAH.
+* To use register names with standard convension, please use CAN_MO31_DATAH.
+*/
+#define CAN_MODATAH31 (CAN_MO31_DATAH)
+
+/** \brief 13F0, Message Object Data Register Low */
+#define CAN_MO31_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00193F0u)
+
+/** Alias (User Manual Name) for CAN_MO31_DATAL.
+* To use register names with standard convension, please use CAN_MO31_DATAL.
+*/
+#define CAN_MODATAL31 (CAN_MO31_DATAL)
+
+/** \brief 13E0, Message Object Function Control Register */
+#define CAN_MO31_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00193E0u)
+
+/** Alias (User Manual Name) for CAN_MO31_EDATA0.
+* To use register names with standard convension, please use CAN_MO31_EDATA0.
+*/
+#define CAN_EMO31DATA0 (CAN_MO31_EDATA0)
+
+/** \brief 13E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO31_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00193E4u)
+
+/** Alias (User Manual Name) for CAN_MO31_EDATA1.
+* To use register names with standard convension, please use CAN_MO31_EDATA1.
+*/
+#define CAN_EMO31DATA1 (CAN_MO31_EDATA1)
+
+/** \brief 13E8, Message Object Interrupt Pointer Register */
+#define CAN_MO31_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00193E8u)
+
+/** Alias (User Manual Name) for CAN_MO31_EDATA2.
+* To use register names with standard convension, please use CAN_MO31_EDATA2.
+*/
+#define CAN_EMO31DATA2 (CAN_MO31_EDATA2)
+
+/** \brief 13EC, Message Object Acceptance Mask Register */
+#define CAN_MO31_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00193ECu)
+
+/** Alias (User Manual Name) for CAN_MO31_EDATA3.
+* To use register names with standard convension, please use CAN_MO31_EDATA3.
+*/
+#define CAN_EMO31DATA3 (CAN_MO31_EDATA3)
+
+/** \brief 13F0, Message Object Data Register Low */
+#define CAN_MO31_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00193F0u)
+
+/** Alias (User Manual Name) for CAN_MO31_EDATA4.
+* To use register names with standard convension, please use CAN_MO31_EDATA4.
+*/
+#define CAN_EMO31DATA4 (CAN_MO31_EDATA4)
+
+/** \brief 13F4, Message Object Data Register High */
+#define CAN_MO31_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00193F4u)
+
+/** Alias (User Manual Name) for CAN_MO31_EDATA5.
+* To use register names with standard convension, please use CAN_MO31_EDATA5.
+*/
+#define CAN_EMO31DATA5 (CAN_MO31_EDATA5)
+
+/** \brief 13F8, Message Object Arbitration Register */
+#define CAN_MO31_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00193F8u)
+
+/** Alias (User Manual Name) for CAN_MO31_EDATA6.
+* To use register names with standard convension, please use CAN_MO31_EDATA6.
+*/
+#define CAN_EMO31DATA6 (CAN_MO31_EDATA6)
+
+/** \brief 13E0, Message Object Function Control Register */
+#define CAN_MO31_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00193E0u)
+
+/** Alias (User Manual Name) for CAN_MO31_FCR.
+* To use register names with standard convension, please use CAN_MO31_FCR.
+*/
+#define CAN_MOFCR31 (CAN_MO31_FCR)
+
+/** \brief 13E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO31_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00193E4u)
+
+/** Alias (User Manual Name) for CAN_MO31_FGPR.
+* To use register names with standard convension, please use CAN_MO31_FGPR.
+*/
+#define CAN_MOFGPR31 (CAN_MO31_FGPR)
+
+/** \brief 13E8, Message Object Interrupt Pointer Register */
+#define CAN_MO31_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00193E8u)
+
+/** Alias (User Manual Name) for CAN_MO31_IPR.
+* To use register names with standard convension, please use CAN_MO31_IPR.
+*/
+#define CAN_MOIPR31 (CAN_MO31_IPR)
+
+/** \brief 13FC, Message Object Control Register */
+#define CAN_MO31_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00193FCu)
+
+/** Alias (User Manual Name) for CAN_MO31_STAT.
+* To use register names with standard convension, please use CAN_MO31_STAT.
+*/
+#define CAN_MOSTAT31 (CAN_MO31_STAT)
+
+/** \brief 140C, Message Object Acceptance Mask Register */
+#define CAN_MO32_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001940Cu)
+
+/** Alias (User Manual Name) for CAN_MO32_AMR.
+* To use register names with standard convension, please use CAN_MO32_AMR.
+*/
+#define CAN_MOAMR32 (CAN_MO32_AMR)
+
+/** \brief 1418, Message Object Arbitration Register */
+#define CAN_MO32_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019418u)
+
+/** Alias (User Manual Name) for CAN_MO32_AR.
+* To use register names with standard convension, please use CAN_MO32_AR.
+*/
+#define CAN_MOAR32 (CAN_MO32_AR)
+
+/** \brief 141C, Message Object Control Register */
+#define CAN_MO32_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001941Cu)
+
+/** Alias (User Manual Name) for CAN_MO32_CTR.
+* To use register names with standard convension, please use CAN_MO32_CTR.
+*/
+#define CAN_MOCTR32 (CAN_MO32_CTR)
+
+/** \brief 1414, Message Object Data Register High */
+#define CAN_MO32_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019414u)
+
+/** Alias (User Manual Name) for CAN_MO32_DATAH.
+* To use register names with standard convension, please use CAN_MO32_DATAH.
+*/
+#define CAN_MODATAH32 (CAN_MO32_DATAH)
+
+/** \brief 1410, Message Object Data Register Low */
+#define CAN_MO32_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019410u)
+
+/** Alias (User Manual Name) for CAN_MO32_DATAL.
+* To use register names with standard convension, please use CAN_MO32_DATAL.
+*/
+#define CAN_MODATAL32 (CAN_MO32_DATAL)
+
+/** \brief 1400, Message Object Function Control Register */
+#define CAN_MO32_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019400u)
+
+/** Alias (User Manual Name) for CAN_MO32_EDATA0.
+* To use register names with standard convension, please use CAN_MO32_EDATA0.
+*/
+#define CAN_EMO32DATA0 (CAN_MO32_EDATA0)
+
+/** \brief 1404, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO32_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019404u)
+
+/** Alias (User Manual Name) for CAN_MO32_EDATA1.
+* To use register names with standard convension, please use CAN_MO32_EDATA1.
+*/
+#define CAN_EMO32DATA1 (CAN_MO32_EDATA1)
+
+/** \brief 1408, Message Object Interrupt Pointer Register */
+#define CAN_MO32_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019408u)
+
+/** Alias (User Manual Name) for CAN_MO32_EDATA2.
+* To use register names with standard convension, please use CAN_MO32_EDATA2.
+*/
+#define CAN_EMO32DATA2 (CAN_MO32_EDATA2)
+
+/** \brief 140C, Message Object Acceptance Mask Register */
+#define CAN_MO32_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001940Cu)
+
+/** Alias (User Manual Name) for CAN_MO32_EDATA3.
+* To use register names with standard convension, please use CAN_MO32_EDATA3.
+*/
+#define CAN_EMO32DATA3 (CAN_MO32_EDATA3)
+
+/** \brief 1410, Message Object Data Register Low */
+#define CAN_MO32_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019410u)
+
+/** Alias (User Manual Name) for CAN_MO32_EDATA4.
+* To use register names with standard convension, please use CAN_MO32_EDATA4.
+*/
+#define CAN_EMO32DATA4 (CAN_MO32_EDATA4)
+
+/** \brief 1414, Message Object Data Register High */
+#define CAN_MO32_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019414u)
+
+/** Alias (User Manual Name) for CAN_MO32_EDATA5.
+* To use register names with standard convension, please use CAN_MO32_EDATA5.
+*/
+#define CAN_EMO32DATA5 (CAN_MO32_EDATA5)
+
+/** \brief 1418, Message Object Arbitration Register */
+#define CAN_MO32_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019418u)
+
+/** Alias (User Manual Name) for CAN_MO32_EDATA6.
+* To use register names with standard convension, please use CAN_MO32_EDATA6.
+*/
+#define CAN_EMO32DATA6 (CAN_MO32_EDATA6)
+
+/** \brief 1400, Message Object Function Control Register */
+#define CAN_MO32_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019400u)
+
+/** Alias (User Manual Name) for CAN_MO32_FCR.
+* To use register names with standard convension, please use CAN_MO32_FCR.
+*/
+#define CAN_MOFCR32 (CAN_MO32_FCR)
+
+/** \brief 1404, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO32_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019404u)
+
+/** Alias (User Manual Name) for CAN_MO32_FGPR.
+* To use register names with standard convension, please use CAN_MO32_FGPR.
+*/
+#define CAN_MOFGPR32 (CAN_MO32_FGPR)
+
+/** \brief 1408, Message Object Interrupt Pointer Register */
+#define CAN_MO32_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019408u)
+
+/** Alias (User Manual Name) for CAN_MO32_IPR.
+* To use register names with standard convension, please use CAN_MO32_IPR.
+*/
+#define CAN_MOIPR32 (CAN_MO32_IPR)
+
+/** \brief 141C, Message Object Control Register */
+#define CAN_MO32_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001941Cu)
+
+/** Alias (User Manual Name) for CAN_MO32_STAT.
+* To use register names with standard convension, please use CAN_MO32_STAT.
+*/
+#define CAN_MOSTAT32 (CAN_MO32_STAT)
+
+/** \brief 142C, Message Object Acceptance Mask Register */
+#define CAN_MO33_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001942Cu)
+
+/** Alias (User Manual Name) for CAN_MO33_AMR.
+* To use register names with standard convension, please use CAN_MO33_AMR.
+*/
+#define CAN_MOAMR33 (CAN_MO33_AMR)
+
+/** \brief 1438, Message Object Arbitration Register */
+#define CAN_MO33_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019438u)
+
+/** Alias (User Manual Name) for CAN_MO33_AR.
+* To use register names with standard convension, please use CAN_MO33_AR.
+*/
+#define CAN_MOAR33 (CAN_MO33_AR)
+
+/** \brief 143C, Message Object Control Register */
+#define CAN_MO33_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001943Cu)
+
+/** Alias (User Manual Name) for CAN_MO33_CTR.
+* To use register names with standard convension, please use CAN_MO33_CTR.
+*/
+#define CAN_MOCTR33 (CAN_MO33_CTR)
+
+/** \brief 1434, Message Object Data Register High */
+#define CAN_MO33_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019434u)
+
+/** Alias (User Manual Name) for CAN_MO33_DATAH.
+* To use register names with standard convension, please use CAN_MO33_DATAH.
+*/
+#define CAN_MODATAH33 (CAN_MO33_DATAH)
+
+/** \brief 1430, Message Object Data Register Low */
+#define CAN_MO33_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019430u)
+
+/** Alias (User Manual Name) for CAN_MO33_DATAL.
+* To use register names with standard convension, please use CAN_MO33_DATAL.
+*/
+#define CAN_MODATAL33 (CAN_MO33_DATAL)
+
+/** \brief 1420, Message Object Function Control Register */
+#define CAN_MO33_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019420u)
+
+/** Alias (User Manual Name) for CAN_MO33_EDATA0.
+* To use register names with standard convension, please use CAN_MO33_EDATA0.
+*/
+#define CAN_EMO33DATA0 (CAN_MO33_EDATA0)
+
+/** \brief 1424, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO33_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019424u)
+
+/** Alias (User Manual Name) for CAN_MO33_EDATA1.
+* To use register names with standard convension, please use CAN_MO33_EDATA1.
+*/
+#define CAN_EMO33DATA1 (CAN_MO33_EDATA1)
+
+/** \brief 1428, Message Object Interrupt Pointer Register */
+#define CAN_MO33_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019428u)
+
+/** Alias (User Manual Name) for CAN_MO33_EDATA2.
+* To use register names with standard convension, please use CAN_MO33_EDATA2.
+*/
+#define CAN_EMO33DATA2 (CAN_MO33_EDATA2)
+
+/** \brief 142C, Message Object Acceptance Mask Register */
+#define CAN_MO33_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001942Cu)
+
+/** Alias (User Manual Name) for CAN_MO33_EDATA3.
+* To use register names with standard convension, please use CAN_MO33_EDATA3.
+*/
+#define CAN_EMO33DATA3 (CAN_MO33_EDATA3)
+
+/** \brief 1430, Message Object Data Register Low */
+#define CAN_MO33_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019430u)
+
+/** Alias (User Manual Name) for CAN_MO33_EDATA4.
+* To use register names with standard convension, please use CAN_MO33_EDATA4.
+*/
+#define CAN_EMO33DATA4 (CAN_MO33_EDATA4)
+
+/** \brief 1434, Message Object Data Register High */
+#define CAN_MO33_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019434u)
+
+/** Alias (User Manual Name) for CAN_MO33_EDATA5.
+* To use register names with standard convension, please use CAN_MO33_EDATA5.
+*/
+#define CAN_EMO33DATA5 (CAN_MO33_EDATA5)
+
+/** \brief 1438, Message Object Arbitration Register */
+#define CAN_MO33_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019438u)
+
+/** Alias (User Manual Name) for CAN_MO33_EDATA6.
+* To use register names with standard convension, please use CAN_MO33_EDATA6.
+*/
+#define CAN_EMO33DATA6 (CAN_MO33_EDATA6)
+
+/** \brief 1420, Message Object Function Control Register */
+#define CAN_MO33_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019420u)
+
+/** Alias (User Manual Name) for CAN_MO33_FCR.
+* To use register names with standard convension, please use CAN_MO33_FCR.
+*/
+#define CAN_MOFCR33 (CAN_MO33_FCR)
+
+/** \brief 1424, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO33_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019424u)
+
+/** Alias (User Manual Name) for CAN_MO33_FGPR.
+* To use register names with standard convension, please use CAN_MO33_FGPR.
+*/
+#define CAN_MOFGPR33 (CAN_MO33_FGPR)
+
+/** \brief 1428, Message Object Interrupt Pointer Register */
+#define CAN_MO33_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019428u)
+
+/** Alias (User Manual Name) for CAN_MO33_IPR.
+* To use register names with standard convension, please use CAN_MO33_IPR.
+*/
+#define CAN_MOIPR33 (CAN_MO33_IPR)
+
+/** \brief 143C, Message Object Control Register */
+#define CAN_MO33_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001943Cu)
+
+/** Alias (User Manual Name) for CAN_MO33_STAT.
+* To use register names with standard convension, please use CAN_MO33_STAT.
+*/
+#define CAN_MOSTAT33 (CAN_MO33_STAT)
+
+/** \brief 144C, Message Object Acceptance Mask Register */
+#define CAN_MO34_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001944Cu)
+
+/** Alias (User Manual Name) for CAN_MO34_AMR.
+* To use register names with standard convension, please use CAN_MO34_AMR.
+*/
+#define CAN_MOAMR34 (CAN_MO34_AMR)
+
+/** \brief 1458, Message Object Arbitration Register */
+#define CAN_MO34_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019458u)
+
+/** Alias (User Manual Name) for CAN_MO34_AR.
+* To use register names with standard convension, please use CAN_MO34_AR.
+*/
+#define CAN_MOAR34 (CAN_MO34_AR)
+
+/** \brief 145C, Message Object Control Register */
+#define CAN_MO34_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001945Cu)
+
+/** Alias (User Manual Name) for CAN_MO34_CTR.
+* To use register names with standard convension, please use CAN_MO34_CTR.
+*/
+#define CAN_MOCTR34 (CAN_MO34_CTR)
+
+/** \brief 1454, Message Object Data Register High */
+#define CAN_MO34_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019454u)
+
+/** Alias (User Manual Name) for CAN_MO34_DATAH.
+* To use register names with standard convension, please use CAN_MO34_DATAH.
+*/
+#define CAN_MODATAH34 (CAN_MO34_DATAH)
+
+/** \brief 1450, Message Object Data Register Low */
+#define CAN_MO34_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019450u)
+
+/** Alias (User Manual Name) for CAN_MO34_DATAL.
+* To use register names with standard convension, please use CAN_MO34_DATAL.
+*/
+#define CAN_MODATAL34 (CAN_MO34_DATAL)
+
+/** \brief 1440, Message Object Function Control Register */
+#define CAN_MO34_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019440u)
+
+/** Alias (User Manual Name) for CAN_MO34_EDATA0.
+* To use register names with standard convension, please use CAN_MO34_EDATA0.
+*/
+#define CAN_EMO34DATA0 (CAN_MO34_EDATA0)
+
+/** \brief 1444, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO34_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019444u)
+
+/** Alias (User Manual Name) for CAN_MO34_EDATA1.
+* To use register names with standard convension, please use CAN_MO34_EDATA1.
+*/
+#define CAN_EMO34DATA1 (CAN_MO34_EDATA1)
+
+/** \brief 1448, Message Object Interrupt Pointer Register */
+#define CAN_MO34_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019448u)
+
+/** Alias (User Manual Name) for CAN_MO34_EDATA2.
+* To use register names with standard convension, please use CAN_MO34_EDATA2.
+*/
+#define CAN_EMO34DATA2 (CAN_MO34_EDATA2)
+
+/** \brief 144C, Message Object Acceptance Mask Register */
+#define CAN_MO34_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001944Cu)
+
+/** Alias (User Manual Name) for CAN_MO34_EDATA3.
+* To use register names with standard convension, please use CAN_MO34_EDATA3.
+*/
+#define CAN_EMO34DATA3 (CAN_MO34_EDATA3)
+
+/** \brief 1450, Message Object Data Register Low */
+#define CAN_MO34_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019450u)
+
+/** Alias (User Manual Name) for CAN_MO34_EDATA4.
+* To use register names with standard convension, please use CAN_MO34_EDATA4.
+*/
+#define CAN_EMO34DATA4 (CAN_MO34_EDATA4)
+
+/** \brief 1454, Message Object Data Register High */
+#define CAN_MO34_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019454u)
+
+/** Alias (User Manual Name) for CAN_MO34_EDATA5.
+* To use register names with standard convension, please use CAN_MO34_EDATA5.
+*/
+#define CAN_EMO34DATA5 (CAN_MO34_EDATA5)
+
+/** \brief 1458, Message Object Arbitration Register */
+#define CAN_MO34_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019458u)
+
+/** Alias (User Manual Name) for CAN_MO34_EDATA6.
+* To use register names with standard convension, please use CAN_MO34_EDATA6.
+*/
+#define CAN_EMO34DATA6 (CAN_MO34_EDATA6)
+
+/** \brief 1440, Message Object Function Control Register */
+#define CAN_MO34_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019440u)
+
+/** Alias (User Manual Name) for CAN_MO34_FCR.
+* To use register names with standard convension, please use CAN_MO34_FCR.
+*/
+#define CAN_MOFCR34 (CAN_MO34_FCR)
+
+/** \brief 1444, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO34_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019444u)
+
+/** Alias (User Manual Name) for CAN_MO34_FGPR.
+* To use register names with standard convension, please use CAN_MO34_FGPR.
+*/
+#define CAN_MOFGPR34 (CAN_MO34_FGPR)
+
+/** \brief 1448, Message Object Interrupt Pointer Register */
+#define CAN_MO34_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019448u)
+
+/** Alias (User Manual Name) for CAN_MO34_IPR.
+* To use register names with standard convension, please use CAN_MO34_IPR.
+*/
+#define CAN_MOIPR34 (CAN_MO34_IPR)
+
+/** \brief 145C, Message Object Control Register */
+#define CAN_MO34_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001945Cu)
+
+/** Alias (User Manual Name) for CAN_MO34_STAT.
+* To use register names with standard convension, please use CAN_MO34_STAT.
+*/
+#define CAN_MOSTAT34 (CAN_MO34_STAT)
+
+/** \brief 146C, Message Object Acceptance Mask Register */
+#define CAN_MO35_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001946Cu)
+
+/** Alias (User Manual Name) for CAN_MO35_AMR.
+* To use register names with standard convension, please use CAN_MO35_AMR.
+*/
+#define CAN_MOAMR35 (CAN_MO35_AMR)
+
+/** \brief 1478, Message Object Arbitration Register */
+#define CAN_MO35_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019478u)
+
+/** Alias (User Manual Name) for CAN_MO35_AR.
+* To use register names with standard convension, please use CAN_MO35_AR.
+*/
+#define CAN_MOAR35 (CAN_MO35_AR)
+
+/** \brief 147C, Message Object Control Register */
+#define CAN_MO35_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001947Cu)
+
+/** Alias (User Manual Name) for CAN_MO35_CTR.
+* To use register names with standard convension, please use CAN_MO35_CTR.
+*/
+#define CAN_MOCTR35 (CAN_MO35_CTR)
+
+/** \brief 1474, Message Object Data Register High */
+#define CAN_MO35_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019474u)
+
+/** Alias (User Manual Name) for CAN_MO35_DATAH.
+* To use register names with standard convension, please use CAN_MO35_DATAH.
+*/
+#define CAN_MODATAH35 (CAN_MO35_DATAH)
+
+/** \brief 1470, Message Object Data Register Low */
+#define CAN_MO35_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019470u)
+
+/** Alias (User Manual Name) for CAN_MO35_DATAL.
+* To use register names with standard convension, please use CAN_MO35_DATAL.
+*/
+#define CAN_MODATAL35 (CAN_MO35_DATAL)
+
+/** \brief 1460, Message Object Function Control Register */
+#define CAN_MO35_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019460u)
+
+/** Alias (User Manual Name) for CAN_MO35_EDATA0.
+* To use register names with standard convension, please use CAN_MO35_EDATA0.
+*/
+#define CAN_EMO35DATA0 (CAN_MO35_EDATA0)
+
+/** \brief 1464, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO35_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019464u)
+
+/** Alias (User Manual Name) for CAN_MO35_EDATA1.
+* To use register names with standard convension, please use CAN_MO35_EDATA1.
+*/
+#define CAN_EMO35DATA1 (CAN_MO35_EDATA1)
+
+/** \brief 1468, Message Object Interrupt Pointer Register */
+#define CAN_MO35_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019468u)
+
+/** Alias (User Manual Name) for CAN_MO35_EDATA2.
+* To use register names with standard convension, please use CAN_MO35_EDATA2.
+*/
+#define CAN_EMO35DATA2 (CAN_MO35_EDATA2)
+
+/** \brief 146C, Message Object Acceptance Mask Register */
+#define CAN_MO35_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001946Cu)
+
+/** Alias (User Manual Name) for CAN_MO35_EDATA3.
+* To use register names with standard convension, please use CAN_MO35_EDATA3.
+*/
+#define CAN_EMO35DATA3 (CAN_MO35_EDATA3)
+
+/** \brief 1470, Message Object Data Register Low */
+#define CAN_MO35_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019470u)
+
+/** Alias (User Manual Name) for CAN_MO35_EDATA4.
+* To use register names with standard convension, please use CAN_MO35_EDATA4.
+*/
+#define CAN_EMO35DATA4 (CAN_MO35_EDATA4)
+
+/** \brief 1474, Message Object Data Register High */
+#define CAN_MO35_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019474u)
+
+/** Alias (User Manual Name) for CAN_MO35_EDATA5.
+* To use register names with standard convension, please use CAN_MO35_EDATA5.
+*/
+#define CAN_EMO35DATA5 (CAN_MO35_EDATA5)
+
+/** \brief 1478, Message Object Arbitration Register */
+#define CAN_MO35_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019478u)
+
+/** Alias (User Manual Name) for CAN_MO35_EDATA6.
+* To use register names with standard convension, please use CAN_MO35_EDATA6.
+*/
+#define CAN_EMO35DATA6 (CAN_MO35_EDATA6)
+
+/** \brief 1460, Message Object Function Control Register */
+#define CAN_MO35_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019460u)
+
+/** Alias (User Manual Name) for CAN_MO35_FCR.
+* To use register names with standard convension, please use CAN_MO35_FCR.
+*/
+#define CAN_MOFCR35 (CAN_MO35_FCR)
+
+/** \brief 1464, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO35_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019464u)
+
+/** Alias (User Manual Name) for CAN_MO35_FGPR.
+* To use register names with standard convension, please use CAN_MO35_FGPR.
+*/
+#define CAN_MOFGPR35 (CAN_MO35_FGPR)
+
+/** \brief 1468, Message Object Interrupt Pointer Register */
+#define CAN_MO35_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019468u)
+
+/** Alias (User Manual Name) for CAN_MO35_IPR.
+* To use register names with standard convension, please use CAN_MO35_IPR.
+*/
+#define CAN_MOIPR35 (CAN_MO35_IPR)
+
+/** \brief 147C, Message Object Control Register */
+#define CAN_MO35_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001947Cu)
+
+/** Alias (User Manual Name) for CAN_MO35_STAT.
+* To use register names with standard convension, please use CAN_MO35_STAT.
+*/
+#define CAN_MOSTAT35 (CAN_MO35_STAT)
+
+/** \brief 148C, Message Object Acceptance Mask Register */
+#define CAN_MO36_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001948Cu)
+
+/** Alias (User Manual Name) for CAN_MO36_AMR.
+* To use register names with standard convension, please use CAN_MO36_AMR.
+*/
+#define CAN_MOAMR36 (CAN_MO36_AMR)
+
+/** \brief 1498, Message Object Arbitration Register */
+#define CAN_MO36_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019498u)
+
+/** Alias (User Manual Name) for CAN_MO36_AR.
+* To use register names with standard convension, please use CAN_MO36_AR.
+*/
+#define CAN_MOAR36 (CAN_MO36_AR)
+
+/** \brief 149C, Message Object Control Register */
+#define CAN_MO36_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001949Cu)
+
+/** Alias (User Manual Name) for CAN_MO36_CTR.
+* To use register names with standard convension, please use CAN_MO36_CTR.
+*/
+#define CAN_MOCTR36 (CAN_MO36_CTR)
+
+/** \brief 1494, Message Object Data Register High */
+#define CAN_MO36_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019494u)
+
+/** Alias (User Manual Name) for CAN_MO36_DATAH.
+* To use register names with standard convension, please use CAN_MO36_DATAH.
+*/
+#define CAN_MODATAH36 (CAN_MO36_DATAH)
+
+/** \brief 1490, Message Object Data Register Low */
+#define CAN_MO36_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019490u)
+
+/** Alias (User Manual Name) for CAN_MO36_DATAL.
+* To use register names with standard convension, please use CAN_MO36_DATAL.
+*/
+#define CAN_MODATAL36 (CAN_MO36_DATAL)
+
+/** \brief 1480, Message Object Function Control Register */
+#define CAN_MO36_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019480u)
+
+/** Alias (User Manual Name) for CAN_MO36_EDATA0.
+* To use register names with standard convension, please use CAN_MO36_EDATA0.
+*/
+#define CAN_EMO36DATA0 (CAN_MO36_EDATA0)
+
+/** \brief 1484, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO36_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019484u)
+
+/** Alias (User Manual Name) for CAN_MO36_EDATA1.
+* To use register names with standard convension, please use CAN_MO36_EDATA1.
+*/
+#define CAN_EMO36DATA1 (CAN_MO36_EDATA1)
+
+/** \brief 1488, Message Object Interrupt Pointer Register */
+#define CAN_MO36_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019488u)
+
+/** Alias (User Manual Name) for CAN_MO36_EDATA2.
+* To use register names with standard convension, please use CAN_MO36_EDATA2.
+*/
+#define CAN_EMO36DATA2 (CAN_MO36_EDATA2)
+
+/** \brief 148C, Message Object Acceptance Mask Register */
+#define CAN_MO36_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001948Cu)
+
+/** Alias (User Manual Name) for CAN_MO36_EDATA3.
+* To use register names with standard convension, please use CAN_MO36_EDATA3.
+*/
+#define CAN_EMO36DATA3 (CAN_MO36_EDATA3)
+
+/** \brief 1490, Message Object Data Register Low */
+#define CAN_MO36_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019490u)
+
+/** Alias (User Manual Name) for CAN_MO36_EDATA4.
+* To use register names with standard convension, please use CAN_MO36_EDATA4.
+*/
+#define CAN_EMO36DATA4 (CAN_MO36_EDATA4)
+
+/** \brief 1494, Message Object Data Register High */
+#define CAN_MO36_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019494u)
+
+/** Alias (User Manual Name) for CAN_MO36_EDATA5.
+* To use register names with standard convension, please use CAN_MO36_EDATA5.
+*/
+#define CAN_EMO36DATA5 (CAN_MO36_EDATA5)
+
+/** \brief 1498, Message Object Arbitration Register */
+#define CAN_MO36_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019498u)
+
+/** Alias (User Manual Name) for CAN_MO36_EDATA6.
+* To use register names with standard convension, please use CAN_MO36_EDATA6.
+*/
+#define CAN_EMO36DATA6 (CAN_MO36_EDATA6)
+
+/** \brief 1480, Message Object Function Control Register */
+#define CAN_MO36_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019480u)
+
+/** Alias (User Manual Name) for CAN_MO36_FCR.
+* To use register names with standard convension, please use CAN_MO36_FCR.
+*/
+#define CAN_MOFCR36 (CAN_MO36_FCR)
+
+/** \brief 1484, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO36_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019484u)
+
+/** Alias (User Manual Name) for CAN_MO36_FGPR.
+* To use register names with standard convension, please use CAN_MO36_FGPR.
+*/
+#define CAN_MOFGPR36 (CAN_MO36_FGPR)
+
+/** \brief 1488, Message Object Interrupt Pointer Register */
+#define CAN_MO36_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019488u)
+
+/** Alias (User Manual Name) for CAN_MO36_IPR.
+* To use register names with standard convension, please use CAN_MO36_IPR.
+*/
+#define CAN_MOIPR36 (CAN_MO36_IPR)
+
+/** \brief 149C, Message Object Control Register */
+#define CAN_MO36_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001949Cu)
+
+/** Alias (User Manual Name) for CAN_MO36_STAT.
+* To use register names with standard convension, please use CAN_MO36_STAT.
+*/
+#define CAN_MOSTAT36 (CAN_MO36_STAT)
+
+/** \brief 14AC, Message Object Acceptance Mask Register */
+#define CAN_MO37_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00194ACu)
+
+/** Alias (User Manual Name) for CAN_MO37_AMR.
+* To use register names with standard convension, please use CAN_MO37_AMR.
+*/
+#define CAN_MOAMR37 (CAN_MO37_AMR)
+
+/** \brief 14B8, Message Object Arbitration Register */
+#define CAN_MO37_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00194B8u)
+
+/** Alias (User Manual Name) for CAN_MO37_AR.
+* To use register names with standard convension, please use CAN_MO37_AR.
+*/
+#define CAN_MOAR37 (CAN_MO37_AR)
+
+/** \brief 14BC, Message Object Control Register */
+#define CAN_MO37_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00194BCu)
+
+/** Alias (User Manual Name) for CAN_MO37_CTR.
+* To use register names with standard convension, please use CAN_MO37_CTR.
+*/
+#define CAN_MOCTR37 (CAN_MO37_CTR)
+
+/** \brief 14B4, Message Object Data Register High */
+#define CAN_MO37_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00194B4u)
+
+/** Alias (User Manual Name) for CAN_MO37_DATAH.
+* To use register names with standard convension, please use CAN_MO37_DATAH.
+*/
+#define CAN_MODATAH37 (CAN_MO37_DATAH)
+
+/** \brief 14B0, Message Object Data Register Low */
+#define CAN_MO37_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00194B0u)
+
+/** Alias (User Manual Name) for CAN_MO37_DATAL.
+* To use register names with standard convension, please use CAN_MO37_DATAL.
+*/
+#define CAN_MODATAL37 (CAN_MO37_DATAL)
+
+/** \brief 14A0, Message Object Function Control Register */
+#define CAN_MO37_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00194A0u)
+
+/** Alias (User Manual Name) for CAN_MO37_EDATA0.
+* To use register names with standard convension, please use CAN_MO37_EDATA0.
+*/
+#define CAN_EMO37DATA0 (CAN_MO37_EDATA0)
+
+/** \brief 14A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO37_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00194A4u)
+
+/** Alias (User Manual Name) for CAN_MO37_EDATA1.
+* To use register names with standard convension, please use CAN_MO37_EDATA1.
+*/
+#define CAN_EMO37DATA1 (CAN_MO37_EDATA1)
+
+/** \brief 14A8, Message Object Interrupt Pointer Register */
+#define CAN_MO37_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00194A8u)
+
+/** Alias (User Manual Name) for CAN_MO37_EDATA2.
+* To use register names with standard convension, please use CAN_MO37_EDATA2.
+*/
+#define CAN_EMO37DATA2 (CAN_MO37_EDATA2)
+
+/** \brief 14AC, Message Object Acceptance Mask Register */
+#define CAN_MO37_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00194ACu)
+
+/** Alias (User Manual Name) for CAN_MO37_EDATA3.
+* To use register names with standard convension, please use CAN_MO37_EDATA3.
+*/
+#define CAN_EMO37DATA3 (CAN_MO37_EDATA3)
+
+/** \brief 14B0, Message Object Data Register Low */
+#define CAN_MO37_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00194B0u)
+
+/** Alias (User Manual Name) for CAN_MO37_EDATA4.
+* To use register names with standard convension, please use CAN_MO37_EDATA4.
+*/
+#define CAN_EMO37DATA4 (CAN_MO37_EDATA4)
+
+/** \brief 14B4, Message Object Data Register High */
+#define CAN_MO37_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00194B4u)
+
+/** Alias (User Manual Name) for CAN_MO37_EDATA5.
+* To use register names with standard convension, please use CAN_MO37_EDATA5.
+*/
+#define CAN_EMO37DATA5 (CAN_MO37_EDATA5)
+
+/** \brief 14B8, Message Object Arbitration Register */
+#define CAN_MO37_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00194B8u)
+
+/** Alias (User Manual Name) for CAN_MO37_EDATA6.
+* To use register names with standard convension, please use CAN_MO37_EDATA6.
+*/
+#define CAN_EMO37DATA6 (CAN_MO37_EDATA6)
+
+/** \brief 14A0, Message Object Function Control Register */
+#define CAN_MO37_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00194A0u)
+
+/** Alias (User Manual Name) for CAN_MO37_FCR.
+* To use register names with standard convension, please use CAN_MO37_FCR.
+*/
+#define CAN_MOFCR37 (CAN_MO37_FCR)
+
+/** \brief 14A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO37_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00194A4u)
+
+/** Alias (User Manual Name) for CAN_MO37_FGPR.
+* To use register names with standard convension, please use CAN_MO37_FGPR.
+*/
+#define CAN_MOFGPR37 (CAN_MO37_FGPR)
+
+/** \brief 14A8, Message Object Interrupt Pointer Register */
+#define CAN_MO37_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00194A8u)
+
+/** Alias (User Manual Name) for CAN_MO37_IPR.
+* To use register names with standard convension, please use CAN_MO37_IPR.
+*/
+#define CAN_MOIPR37 (CAN_MO37_IPR)
+
+/** \brief 14BC, Message Object Control Register */
+#define CAN_MO37_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00194BCu)
+
+/** Alias (User Manual Name) for CAN_MO37_STAT.
+* To use register names with standard convension, please use CAN_MO37_STAT.
+*/
+#define CAN_MOSTAT37 (CAN_MO37_STAT)
+
+/** \brief 14CC, Message Object Acceptance Mask Register */
+#define CAN_MO38_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00194CCu)
+
+/** Alias (User Manual Name) for CAN_MO38_AMR.
+* To use register names with standard convension, please use CAN_MO38_AMR.
+*/
+#define CAN_MOAMR38 (CAN_MO38_AMR)
+
+/** \brief 14D8, Message Object Arbitration Register */
+#define CAN_MO38_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00194D8u)
+
+/** Alias (User Manual Name) for CAN_MO38_AR.
+* To use register names with standard convension, please use CAN_MO38_AR.
+*/
+#define CAN_MOAR38 (CAN_MO38_AR)
+
+/** \brief 14DC, Message Object Control Register */
+#define CAN_MO38_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00194DCu)
+
+/** Alias (User Manual Name) for CAN_MO38_CTR.
+* To use register names with standard convension, please use CAN_MO38_CTR.
+*/
+#define CAN_MOCTR38 (CAN_MO38_CTR)
+
+/** \brief 14D4, Message Object Data Register High */
+#define CAN_MO38_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00194D4u)
+
+/** Alias (User Manual Name) for CAN_MO38_DATAH.
+* To use register names with standard convension, please use CAN_MO38_DATAH.
+*/
+#define CAN_MODATAH38 (CAN_MO38_DATAH)
+
+/** \brief 14D0, Message Object Data Register Low */
+#define CAN_MO38_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00194D0u)
+
+/** Alias (User Manual Name) for CAN_MO38_DATAL.
+* To use register names with standard convension, please use CAN_MO38_DATAL.
+*/
+#define CAN_MODATAL38 (CAN_MO38_DATAL)
+
+/** \brief 14C0, Message Object Function Control Register */
+#define CAN_MO38_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00194C0u)
+
+/** Alias (User Manual Name) for CAN_MO38_EDATA0.
+* To use register names with standard convension, please use CAN_MO38_EDATA0.
+*/
+#define CAN_EMO38DATA0 (CAN_MO38_EDATA0)
+
+/** \brief 14C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO38_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00194C4u)
+
+/** Alias (User Manual Name) for CAN_MO38_EDATA1.
+* To use register names with standard convension, please use CAN_MO38_EDATA1.
+*/
+#define CAN_EMO38DATA1 (CAN_MO38_EDATA1)
+
+/** \brief 14C8, Message Object Interrupt Pointer Register */
+#define CAN_MO38_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00194C8u)
+
+/** Alias (User Manual Name) for CAN_MO38_EDATA2.
+* To use register names with standard convension, please use CAN_MO38_EDATA2.
+*/
+#define CAN_EMO38DATA2 (CAN_MO38_EDATA2)
+
+/** \brief 14CC, Message Object Acceptance Mask Register */
+#define CAN_MO38_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00194CCu)
+
+/** Alias (User Manual Name) for CAN_MO38_EDATA3.
+* To use register names with standard convension, please use CAN_MO38_EDATA3.
+*/
+#define CAN_EMO38DATA3 (CAN_MO38_EDATA3)
+
+/** \brief 14D0, Message Object Data Register Low */
+#define CAN_MO38_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00194D0u)
+
+/** Alias (User Manual Name) for CAN_MO38_EDATA4.
+* To use register names with standard convension, please use CAN_MO38_EDATA4.
+*/
+#define CAN_EMO38DATA4 (CAN_MO38_EDATA4)
+
+/** \brief 14D4, Message Object Data Register High */
+#define CAN_MO38_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00194D4u)
+
+/** Alias (User Manual Name) for CAN_MO38_EDATA5.
+* To use register names with standard convension, please use CAN_MO38_EDATA5.
+*/
+#define CAN_EMO38DATA5 (CAN_MO38_EDATA5)
+
+/** \brief 14D8, Message Object Arbitration Register */
+#define CAN_MO38_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00194D8u)
+
+/** Alias (User Manual Name) for CAN_MO38_EDATA6.
+* To use register names with standard convension, please use CAN_MO38_EDATA6.
+*/
+#define CAN_EMO38DATA6 (CAN_MO38_EDATA6)
+
+/** \brief 14C0, Message Object Function Control Register */
+#define CAN_MO38_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00194C0u)
+
+/** Alias (User Manual Name) for CAN_MO38_FCR.
+* To use register names with standard convension, please use CAN_MO38_FCR.
+*/
+#define CAN_MOFCR38 (CAN_MO38_FCR)
+
+/** \brief 14C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO38_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00194C4u)
+
+/** Alias (User Manual Name) for CAN_MO38_FGPR.
+* To use register names with standard convension, please use CAN_MO38_FGPR.
+*/
+#define CAN_MOFGPR38 (CAN_MO38_FGPR)
+
+/** \brief 14C8, Message Object Interrupt Pointer Register */
+#define CAN_MO38_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00194C8u)
+
+/** Alias (User Manual Name) for CAN_MO38_IPR.
+* To use register names with standard convension, please use CAN_MO38_IPR.
+*/
+#define CAN_MOIPR38 (CAN_MO38_IPR)
+
+/** \brief 14DC, Message Object Control Register */
+#define CAN_MO38_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00194DCu)
+
+/** Alias (User Manual Name) for CAN_MO38_STAT.
+* To use register names with standard convension, please use CAN_MO38_STAT.
+*/
+#define CAN_MOSTAT38 (CAN_MO38_STAT)
+
+/** \brief 14EC, Message Object Acceptance Mask Register */
+#define CAN_MO39_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00194ECu)
+
+/** Alias (User Manual Name) for CAN_MO39_AMR.
+* To use register names with standard convension, please use CAN_MO39_AMR.
+*/
+#define CAN_MOAMR39 (CAN_MO39_AMR)
+
+/** \brief 14F8, Message Object Arbitration Register */
+#define CAN_MO39_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00194F8u)
+
+/** Alias (User Manual Name) for CAN_MO39_AR.
+* To use register names with standard convension, please use CAN_MO39_AR.
+*/
+#define CAN_MOAR39 (CAN_MO39_AR)
+
+/** \brief 14FC, Message Object Control Register */
+#define CAN_MO39_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00194FCu)
+
+/** Alias (User Manual Name) for CAN_MO39_CTR.
+* To use register names with standard convension, please use CAN_MO39_CTR.
+*/
+#define CAN_MOCTR39 (CAN_MO39_CTR)
+
+/** \brief 14F4, Message Object Data Register High */
+#define CAN_MO39_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00194F4u)
+
+/** Alias (User Manual Name) for CAN_MO39_DATAH.
+* To use register names with standard convension, please use CAN_MO39_DATAH.
+*/
+#define CAN_MODATAH39 (CAN_MO39_DATAH)
+
+/** \brief 14F0, Message Object Data Register Low */
+#define CAN_MO39_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00194F0u)
+
+/** Alias (User Manual Name) for CAN_MO39_DATAL.
+* To use register names with standard convension, please use CAN_MO39_DATAL.
+*/
+#define CAN_MODATAL39 (CAN_MO39_DATAL)
+
+/** \brief 14E0, Message Object Function Control Register */
+#define CAN_MO39_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00194E0u)
+
+/** Alias (User Manual Name) for CAN_MO39_EDATA0.
+* To use register names with standard convension, please use CAN_MO39_EDATA0.
+*/
+#define CAN_EMO39DATA0 (CAN_MO39_EDATA0)
+
+/** \brief 14E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO39_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00194E4u)
+
+/** Alias (User Manual Name) for CAN_MO39_EDATA1.
+* To use register names with standard convension, please use CAN_MO39_EDATA1.
+*/
+#define CAN_EMO39DATA1 (CAN_MO39_EDATA1)
+
+/** \brief 14E8, Message Object Interrupt Pointer Register */
+#define CAN_MO39_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00194E8u)
+
+/** Alias (User Manual Name) for CAN_MO39_EDATA2.
+* To use register names with standard convension, please use CAN_MO39_EDATA2.
+*/
+#define CAN_EMO39DATA2 (CAN_MO39_EDATA2)
+
+/** \brief 14EC, Message Object Acceptance Mask Register */
+#define CAN_MO39_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00194ECu)
+
+/** Alias (User Manual Name) for CAN_MO39_EDATA3.
+* To use register names with standard convension, please use CAN_MO39_EDATA3.
+*/
+#define CAN_EMO39DATA3 (CAN_MO39_EDATA3)
+
+/** \brief 14F0, Message Object Data Register Low */
+#define CAN_MO39_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00194F0u)
+
+/** Alias (User Manual Name) for CAN_MO39_EDATA4.
+* To use register names with standard convension, please use CAN_MO39_EDATA4.
+*/
+#define CAN_EMO39DATA4 (CAN_MO39_EDATA4)
+
+/** \brief 14F4, Message Object Data Register High */
+#define CAN_MO39_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00194F4u)
+
+/** Alias (User Manual Name) for CAN_MO39_EDATA5.
+* To use register names with standard convension, please use CAN_MO39_EDATA5.
+*/
+#define CAN_EMO39DATA5 (CAN_MO39_EDATA5)
+
+/** \brief 14F8, Message Object Arbitration Register */
+#define CAN_MO39_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00194F8u)
+
+/** Alias (User Manual Name) for CAN_MO39_EDATA6.
+* To use register names with standard convension, please use CAN_MO39_EDATA6.
+*/
+#define CAN_EMO39DATA6 (CAN_MO39_EDATA6)
+
+/** \brief 14E0, Message Object Function Control Register */
+#define CAN_MO39_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00194E0u)
+
+/** Alias (User Manual Name) for CAN_MO39_FCR.
+* To use register names with standard convension, please use CAN_MO39_FCR.
+*/
+#define CAN_MOFCR39 (CAN_MO39_FCR)
+
+/** \brief 14E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO39_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00194E4u)
+
+/** Alias (User Manual Name) for CAN_MO39_FGPR.
+* To use register names with standard convension, please use CAN_MO39_FGPR.
+*/
+#define CAN_MOFGPR39 (CAN_MO39_FGPR)
+
+/** \brief 14E8, Message Object Interrupt Pointer Register */
+#define CAN_MO39_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00194E8u)
+
+/** Alias (User Manual Name) for CAN_MO39_IPR.
+* To use register names with standard convension, please use CAN_MO39_IPR.
+*/
+#define CAN_MOIPR39 (CAN_MO39_IPR)
+
+/** \brief 14FC, Message Object Control Register */
+#define CAN_MO39_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00194FCu)
+
+/** Alias (User Manual Name) for CAN_MO39_STAT.
+* To use register names with standard convension, please use CAN_MO39_STAT.
+*/
+#define CAN_MOSTAT39 (CAN_MO39_STAT)
+
+/** \brief 106C, Message Object Acceptance Mask Register */
+#define CAN_MO3_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001906Cu)
+
+/** Alias (User Manual Name) for CAN_MO3_AMR.
+* To use register names with standard convension, please use CAN_MO3_AMR.
+*/
+#define CAN_MOAMR3 (CAN_MO3_AMR)
+
+/** \brief 1078, Message Object Arbitration Register */
+#define CAN_MO3_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019078u)
+
+/** Alias (User Manual Name) for CAN_MO3_AR.
+* To use register names with standard convension, please use CAN_MO3_AR.
+*/
+#define CAN_MOAR3 (CAN_MO3_AR)
+
+/** \brief 107C, Message Object Control Register */
+#define CAN_MO3_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001907Cu)
+
+/** Alias (User Manual Name) for CAN_MO3_CTR.
+* To use register names with standard convension, please use CAN_MO3_CTR.
+*/
+#define CAN_MOCTR3 (CAN_MO3_CTR)
+
+/** \brief 1074, Message Object Data Register High */
+#define CAN_MO3_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019074u)
+
+/** Alias (User Manual Name) for CAN_MO3_DATAH.
+* To use register names with standard convension, please use CAN_MO3_DATAH.
+*/
+#define CAN_MODATAH3 (CAN_MO3_DATAH)
+
+/** \brief 1070, Message Object Data Register Low */
+#define CAN_MO3_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019070u)
+
+/** Alias (User Manual Name) for CAN_MO3_DATAL.
+* To use register names with standard convension, please use CAN_MO3_DATAL.
+*/
+#define CAN_MODATAL3 (CAN_MO3_DATAL)
+
+/** \brief 1060, Message Object Function Control Register */
+#define CAN_MO3_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019060u)
+
+/** Alias (User Manual Name) for CAN_MO3_EDATA0.
+* To use register names with standard convension, please use CAN_MO3_EDATA0.
+*/
+#define CAN_EMO3DATA0 (CAN_MO3_EDATA0)
+
+/** \brief 1064, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO3_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019064u)
+
+/** Alias (User Manual Name) for CAN_MO3_EDATA1.
+* To use register names with standard convension, please use CAN_MO3_EDATA1.
+*/
+#define CAN_EMO3DATA1 (CAN_MO3_EDATA1)
+
+/** \brief 1068, Message Object Interrupt Pointer Register */
+#define CAN_MO3_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019068u)
+
+/** Alias (User Manual Name) for CAN_MO3_EDATA2.
+* To use register names with standard convension, please use CAN_MO3_EDATA2.
+*/
+#define CAN_EMO3DATA2 (CAN_MO3_EDATA2)
+
+/** \brief 106C, Message Object Acceptance Mask Register */
+#define CAN_MO3_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001906Cu)
+
+/** Alias (User Manual Name) for CAN_MO3_EDATA3.
+* To use register names with standard convension, please use CAN_MO3_EDATA3.
+*/
+#define CAN_EMO3DATA3 (CAN_MO3_EDATA3)
+
+/** \brief 1070, Message Object Data Register Low */
+#define CAN_MO3_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019070u)
+
+/** Alias (User Manual Name) for CAN_MO3_EDATA4.
+* To use register names with standard convension, please use CAN_MO3_EDATA4.
+*/
+#define CAN_EMO3DATA4 (CAN_MO3_EDATA4)
+
+/** \brief 1074, Message Object Data Register High */
+#define CAN_MO3_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019074u)
+
+/** Alias (User Manual Name) for CAN_MO3_EDATA5.
+* To use register names with standard convension, please use CAN_MO3_EDATA5.
+*/
+#define CAN_EMO3DATA5 (CAN_MO3_EDATA5)
+
+/** \brief 1078, Message Object Arbitration Register */
+#define CAN_MO3_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019078u)
+
+/** Alias (User Manual Name) for CAN_MO3_EDATA6.
+* To use register names with standard convension, please use CAN_MO3_EDATA6.
+*/
+#define CAN_EMO3DATA6 (CAN_MO3_EDATA6)
+
+/** \brief 1060, Message Object Function Control Register */
+#define CAN_MO3_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019060u)
+
+/** Alias (User Manual Name) for CAN_MO3_FCR.
+* To use register names with standard convension, please use CAN_MO3_FCR.
+*/
+#define CAN_MOFCR3 (CAN_MO3_FCR)
+
+/** \brief 1064, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO3_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019064u)
+
+/** Alias (User Manual Name) for CAN_MO3_FGPR.
+* To use register names with standard convension, please use CAN_MO3_FGPR.
+*/
+#define CAN_MOFGPR3 (CAN_MO3_FGPR)
+
+/** \brief 1068, Message Object Interrupt Pointer Register */
+#define CAN_MO3_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019068u)
+
+/** Alias (User Manual Name) for CAN_MO3_IPR.
+* To use register names with standard convension, please use CAN_MO3_IPR.
+*/
+#define CAN_MOIPR3 (CAN_MO3_IPR)
+
+/** \brief 107C, Message Object Control Register */
+#define CAN_MO3_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001907Cu)
+
+/** Alias (User Manual Name) for CAN_MO3_STAT.
+* To use register names with standard convension, please use CAN_MO3_STAT.
+*/
+#define CAN_MOSTAT3 (CAN_MO3_STAT)
+
+/** \brief 150C, Message Object Acceptance Mask Register */
+#define CAN_MO40_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001950Cu)
+
+/** Alias (User Manual Name) for CAN_MO40_AMR.
+* To use register names with standard convension, please use CAN_MO40_AMR.
+*/
+#define CAN_MOAMR40 (CAN_MO40_AMR)
+
+/** \brief 1518, Message Object Arbitration Register */
+#define CAN_MO40_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019518u)
+
+/** Alias (User Manual Name) for CAN_MO40_AR.
+* To use register names with standard convension, please use CAN_MO40_AR.
+*/
+#define CAN_MOAR40 (CAN_MO40_AR)
+
+/** \brief 151C, Message Object Control Register */
+#define CAN_MO40_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001951Cu)
+
+/** Alias (User Manual Name) for CAN_MO40_CTR.
+* To use register names with standard convension, please use CAN_MO40_CTR.
+*/
+#define CAN_MOCTR40 (CAN_MO40_CTR)
+
+/** \brief 1514, Message Object Data Register High */
+#define CAN_MO40_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019514u)
+
+/** Alias (User Manual Name) for CAN_MO40_DATAH.
+* To use register names with standard convension, please use CAN_MO40_DATAH.
+*/
+#define CAN_MODATAH40 (CAN_MO40_DATAH)
+
+/** \brief 1510, Message Object Data Register Low */
+#define CAN_MO40_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019510u)
+
+/** Alias (User Manual Name) for CAN_MO40_DATAL.
+* To use register names with standard convension, please use CAN_MO40_DATAL.
+*/
+#define CAN_MODATAL40 (CAN_MO40_DATAL)
+
+/** \brief 1500, Message Object Function Control Register */
+#define CAN_MO40_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019500u)
+
+/** Alias (User Manual Name) for CAN_MO40_EDATA0.
+* To use register names with standard convension, please use CAN_MO40_EDATA0.
+*/
+#define CAN_EMO40DATA0 (CAN_MO40_EDATA0)
+
+/** \brief 1504, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO40_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019504u)
+
+/** Alias (User Manual Name) for CAN_MO40_EDATA1.
+* To use register names with standard convension, please use CAN_MO40_EDATA1.
+*/
+#define CAN_EMO40DATA1 (CAN_MO40_EDATA1)
+
+/** \brief 1508, Message Object Interrupt Pointer Register */
+#define CAN_MO40_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019508u)
+
+/** Alias (User Manual Name) for CAN_MO40_EDATA2.
+* To use register names with standard convension, please use CAN_MO40_EDATA2.
+*/
+#define CAN_EMO40DATA2 (CAN_MO40_EDATA2)
+
+/** \brief 150C, Message Object Acceptance Mask Register */
+#define CAN_MO40_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001950Cu)
+
+/** Alias (User Manual Name) for CAN_MO40_EDATA3.
+* To use register names with standard convension, please use CAN_MO40_EDATA3.
+*/
+#define CAN_EMO40DATA3 (CAN_MO40_EDATA3)
+
+/** \brief 1510, Message Object Data Register Low */
+#define CAN_MO40_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019510u)
+
+/** Alias (User Manual Name) for CAN_MO40_EDATA4.
+* To use register names with standard convension, please use CAN_MO40_EDATA4.
+*/
+#define CAN_EMO40DATA4 (CAN_MO40_EDATA4)
+
+/** \brief 1514, Message Object Data Register High */
+#define CAN_MO40_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019514u)
+
+/** Alias (User Manual Name) for CAN_MO40_EDATA5.
+* To use register names with standard convension, please use CAN_MO40_EDATA5.
+*/
+#define CAN_EMO40DATA5 (CAN_MO40_EDATA5)
+
+/** \brief 1518, Message Object Arbitration Register */
+#define CAN_MO40_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019518u)
+
+/** Alias (User Manual Name) for CAN_MO40_EDATA6.
+* To use register names with standard convension, please use CAN_MO40_EDATA6.
+*/
+#define CAN_EMO40DATA6 (CAN_MO40_EDATA6)
+
+/** \brief 1500, Message Object Function Control Register */
+#define CAN_MO40_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019500u)
+
+/** Alias (User Manual Name) for CAN_MO40_FCR.
+* To use register names with standard convension, please use CAN_MO40_FCR.
+*/
+#define CAN_MOFCR40 (CAN_MO40_FCR)
+
+/** \brief 1504, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO40_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019504u)
+
+/** Alias (User Manual Name) for CAN_MO40_FGPR.
+* To use register names with standard convension, please use CAN_MO40_FGPR.
+*/
+#define CAN_MOFGPR40 (CAN_MO40_FGPR)
+
+/** \brief 1508, Message Object Interrupt Pointer Register */
+#define CAN_MO40_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019508u)
+
+/** Alias (User Manual Name) for CAN_MO40_IPR.
+* To use register names with standard convension, please use CAN_MO40_IPR.
+*/
+#define CAN_MOIPR40 (CAN_MO40_IPR)
+
+/** \brief 151C, Message Object Control Register */
+#define CAN_MO40_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001951Cu)
+
+/** Alias (User Manual Name) for CAN_MO40_STAT.
+* To use register names with standard convension, please use CAN_MO40_STAT.
+*/
+#define CAN_MOSTAT40 (CAN_MO40_STAT)
+
+/** \brief 152C, Message Object Acceptance Mask Register */
+#define CAN_MO41_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001952Cu)
+
+/** Alias (User Manual Name) for CAN_MO41_AMR.
+* To use register names with standard convension, please use CAN_MO41_AMR.
+*/
+#define CAN_MOAMR41 (CAN_MO41_AMR)
+
+/** \brief 1538, Message Object Arbitration Register */
+#define CAN_MO41_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019538u)
+
+/** Alias (User Manual Name) for CAN_MO41_AR.
+* To use register names with standard convension, please use CAN_MO41_AR.
+*/
+#define CAN_MOAR41 (CAN_MO41_AR)
+
+/** \brief 153C, Message Object Control Register */
+#define CAN_MO41_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001953Cu)
+
+/** Alias (User Manual Name) for CAN_MO41_CTR.
+* To use register names with standard convension, please use CAN_MO41_CTR.
+*/
+#define CAN_MOCTR41 (CAN_MO41_CTR)
+
+/** \brief 1534, Message Object Data Register High */
+#define CAN_MO41_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019534u)
+
+/** Alias (User Manual Name) for CAN_MO41_DATAH.
+* To use register names with standard convension, please use CAN_MO41_DATAH.
+*/
+#define CAN_MODATAH41 (CAN_MO41_DATAH)
+
+/** \brief 1530, Message Object Data Register Low */
+#define CAN_MO41_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019530u)
+
+/** Alias (User Manual Name) for CAN_MO41_DATAL.
+* To use register names with standard convension, please use CAN_MO41_DATAL.
+*/
+#define CAN_MODATAL41 (CAN_MO41_DATAL)
+
+/** \brief 1520, Message Object Function Control Register */
+#define CAN_MO41_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019520u)
+
+/** Alias (User Manual Name) for CAN_MO41_EDATA0.
+* To use register names with standard convension, please use CAN_MO41_EDATA0.
+*/
+#define CAN_EMO41DATA0 (CAN_MO41_EDATA0)
+
+/** \brief 1524, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO41_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019524u)
+
+/** Alias (User Manual Name) for CAN_MO41_EDATA1.
+* To use register names with standard convension, please use CAN_MO41_EDATA1.
+*/
+#define CAN_EMO41DATA1 (CAN_MO41_EDATA1)
+
+/** \brief 1528, Message Object Interrupt Pointer Register */
+#define CAN_MO41_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019528u)
+
+/** Alias (User Manual Name) for CAN_MO41_EDATA2.
+* To use register names with standard convension, please use CAN_MO41_EDATA2.
+*/
+#define CAN_EMO41DATA2 (CAN_MO41_EDATA2)
+
+/** \brief 152C, Message Object Acceptance Mask Register */
+#define CAN_MO41_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001952Cu)
+
+/** Alias (User Manual Name) for CAN_MO41_EDATA3.
+* To use register names with standard convension, please use CAN_MO41_EDATA3.
+*/
+#define CAN_EMO41DATA3 (CAN_MO41_EDATA3)
+
+/** \brief 1530, Message Object Data Register Low */
+#define CAN_MO41_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019530u)
+
+/** Alias (User Manual Name) for CAN_MO41_EDATA4.
+* To use register names with standard convension, please use CAN_MO41_EDATA4.
+*/
+#define CAN_EMO41DATA4 (CAN_MO41_EDATA4)
+
+/** \brief 1534, Message Object Data Register High */
+#define CAN_MO41_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019534u)
+
+/** Alias (User Manual Name) for CAN_MO41_EDATA5.
+* To use register names with standard convension, please use CAN_MO41_EDATA5.
+*/
+#define CAN_EMO41DATA5 (CAN_MO41_EDATA5)
+
+/** \brief 1538, Message Object Arbitration Register */
+#define CAN_MO41_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019538u)
+
+/** Alias (User Manual Name) for CAN_MO41_EDATA6.
+* To use register names with standard convension, please use CAN_MO41_EDATA6.
+*/
+#define CAN_EMO41DATA6 (CAN_MO41_EDATA6)
+
+/** \brief 1520, Message Object Function Control Register */
+#define CAN_MO41_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019520u)
+
+/** Alias (User Manual Name) for CAN_MO41_FCR.
+* To use register names with standard convension, please use CAN_MO41_FCR.
+*/
+#define CAN_MOFCR41 (CAN_MO41_FCR)
+
+/** \brief 1524, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO41_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019524u)
+
+/** Alias (User Manual Name) for CAN_MO41_FGPR.
+* To use register names with standard convension, please use CAN_MO41_FGPR.
+*/
+#define CAN_MOFGPR41 (CAN_MO41_FGPR)
+
+/** \brief 1528, Message Object Interrupt Pointer Register */
+#define CAN_MO41_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019528u)
+
+/** Alias (User Manual Name) for CAN_MO41_IPR.
+* To use register names with standard convension, please use CAN_MO41_IPR.
+*/
+#define CAN_MOIPR41 (CAN_MO41_IPR)
+
+/** \brief 153C, Message Object Control Register */
+#define CAN_MO41_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001953Cu)
+
+/** Alias (User Manual Name) for CAN_MO41_STAT.
+* To use register names with standard convension, please use CAN_MO41_STAT.
+*/
+#define CAN_MOSTAT41 (CAN_MO41_STAT)
+
+/** \brief 154C, Message Object Acceptance Mask Register */
+#define CAN_MO42_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001954Cu)
+
+/** Alias (User Manual Name) for CAN_MO42_AMR.
+* To use register names with standard convension, please use CAN_MO42_AMR.
+*/
+#define CAN_MOAMR42 (CAN_MO42_AMR)
+
+/** \brief 1558, Message Object Arbitration Register */
+#define CAN_MO42_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019558u)
+
+/** Alias (User Manual Name) for CAN_MO42_AR.
+* To use register names with standard convension, please use CAN_MO42_AR.
+*/
+#define CAN_MOAR42 (CAN_MO42_AR)
+
+/** \brief 155C, Message Object Control Register */
+#define CAN_MO42_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001955Cu)
+
+/** Alias (User Manual Name) for CAN_MO42_CTR.
+* To use register names with standard convension, please use CAN_MO42_CTR.
+*/
+#define CAN_MOCTR42 (CAN_MO42_CTR)
+
+/** \brief 1554, Message Object Data Register High */
+#define CAN_MO42_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019554u)
+
+/** Alias (User Manual Name) for CAN_MO42_DATAH.
+* To use register names with standard convension, please use CAN_MO42_DATAH.
+*/
+#define CAN_MODATAH42 (CAN_MO42_DATAH)
+
+/** \brief 1550, Message Object Data Register Low */
+#define CAN_MO42_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019550u)
+
+/** Alias (User Manual Name) for CAN_MO42_DATAL.
+* To use register names with standard convension, please use CAN_MO42_DATAL.
+*/
+#define CAN_MODATAL42 (CAN_MO42_DATAL)
+
+/** \brief 1540, Message Object Function Control Register */
+#define CAN_MO42_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019540u)
+
+/** Alias (User Manual Name) for CAN_MO42_EDATA0.
+* To use register names with standard convension, please use CAN_MO42_EDATA0.
+*/
+#define CAN_EMO42DATA0 (CAN_MO42_EDATA0)
+
+/** \brief 1544, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO42_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019544u)
+
+/** Alias (User Manual Name) for CAN_MO42_EDATA1.
+* To use register names with standard convension, please use CAN_MO42_EDATA1.
+*/
+#define CAN_EMO42DATA1 (CAN_MO42_EDATA1)
+
+/** \brief 1548, Message Object Interrupt Pointer Register */
+#define CAN_MO42_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019548u)
+
+/** Alias (User Manual Name) for CAN_MO42_EDATA2.
+* To use register names with standard convension, please use CAN_MO42_EDATA2.
+*/
+#define CAN_EMO42DATA2 (CAN_MO42_EDATA2)
+
+/** \brief 154C, Message Object Acceptance Mask Register */
+#define CAN_MO42_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001954Cu)
+
+/** Alias (User Manual Name) for CAN_MO42_EDATA3.
+* To use register names with standard convension, please use CAN_MO42_EDATA3.
+*/
+#define CAN_EMO42DATA3 (CAN_MO42_EDATA3)
+
+/** \brief 1550, Message Object Data Register Low */
+#define CAN_MO42_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019550u)
+
+/** Alias (User Manual Name) for CAN_MO42_EDATA4.
+* To use register names with standard convension, please use CAN_MO42_EDATA4.
+*/
+#define CAN_EMO42DATA4 (CAN_MO42_EDATA4)
+
+/** \brief 1554, Message Object Data Register High */
+#define CAN_MO42_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019554u)
+
+/** Alias (User Manual Name) for CAN_MO42_EDATA5.
+* To use register names with standard convension, please use CAN_MO42_EDATA5.
+*/
+#define CAN_EMO42DATA5 (CAN_MO42_EDATA5)
+
+/** \brief 1558, Message Object Arbitration Register */
+#define CAN_MO42_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019558u)
+
+/** Alias (User Manual Name) for CAN_MO42_EDATA6.
+* To use register names with standard convension, please use CAN_MO42_EDATA6.
+*/
+#define CAN_EMO42DATA6 (CAN_MO42_EDATA6)
+
+/** \brief 1540, Message Object Function Control Register */
+#define CAN_MO42_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019540u)
+
+/** Alias (User Manual Name) for CAN_MO42_FCR.
+* To use register names with standard convension, please use CAN_MO42_FCR.
+*/
+#define CAN_MOFCR42 (CAN_MO42_FCR)
+
+/** \brief 1544, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO42_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019544u)
+
+/** Alias (User Manual Name) for CAN_MO42_FGPR.
+* To use register names with standard convension, please use CAN_MO42_FGPR.
+*/
+#define CAN_MOFGPR42 (CAN_MO42_FGPR)
+
+/** \brief 1548, Message Object Interrupt Pointer Register */
+#define CAN_MO42_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019548u)
+
+/** Alias (User Manual Name) for CAN_MO42_IPR.
+* To use register names with standard convension, please use CAN_MO42_IPR.
+*/
+#define CAN_MOIPR42 (CAN_MO42_IPR)
+
+/** \brief 155C, Message Object Control Register */
+#define CAN_MO42_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001955Cu)
+
+/** Alias (User Manual Name) for CAN_MO42_STAT.
+* To use register names with standard convension, please use CAN_MO42_STAT.
+*/
+#define CAN_MOSTAT42 (CAN_MO42_STAT)
+
+/** \brief 156C, Message Object Acceptance Mask Register */
+#define CAN_MO43_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001956Cu)
+
+/** Alias (User Manual Name) for CAN_MO43_AMR.
+* To use register names with standard convension, please use CAN_MO43_AMR.
+*/
+#define CAN_MOAMR43 (CAN_MO43_AMR)
+
+/** \brief 1578, Message Object Arbitration Register */
+#define CAN_MO43_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019578u)
+
+/** Alias (User Manual Name) for CAN_MO43_AR.
+* To use register names with standard convension, please use CAN_MO43_AR.
+*/
+#define CAN_MOAR43 (CAN_MO43_AR)
+
+/** \brief 157C, Message Object Control Register */
+#define CAN_MO43_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001957Cu)
+
+/** Alias (User Manual Name) for CAN_MO43_CTR.
+* To use register names with standard convension, please use CAN_MO43_CTR.
+*/
+#define CAN_MOCTR43 (CAN_MO43_CTR)
+
+/** \brief 1574, Message Object Data Register High */
+#define CAN_MO43_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019574u)
+
+/** Alias (User Manual Name) for CAN_MO43_DATAH.
+* To use register names with standard convension, please use CAN_MO43_DATAH.
+*/
+#define CAN_MODATAH43 (CAN_MO43_DATAH)
+
+/** \brief 1570, Message Object Data Register Low */
+#define CAN_MO43_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019570u)
+
+/** Alias (User Manual Name) for CAN_MO43_DATAL.
+* To use register names with standard convension, please use CAN_MO43_DATAL.
+*/
+#define CAN_MODATAL43 (CAN_MO43_DATAL)
+
+/** \brief 1560, Message Object Function Control Register */
+#define CAN_MO43_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019560u)
+
+/** Alias (User Manual Name) for CAN_MO43_EDATA0.
+* To use register names with standard convension, please use CAN_MO43_EDATA0.
+*/
+#define CAN_EMO43DATA0 (CAN_MO43_EDATA0)
+
+/** \brief 1564, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO43_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019564u)
+
+/** Alias (User Manual Name) for CAN_MO43_EDATA1.
+* To use register names with standard convension, please use CAN_MO43_EDATA1.
+*/
+#define CAN_EMO43DATA1 (CAN_MO43_EDATA1)
+
+/** \brief 1568, Message Object Interrupt Pointer Register */
+#define CAN_MO43_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019568u)
+
+/** Alias (User Manual Name) for CAN_MO43_EDATA2.
+* To use register names with standard convension, please use CAN_MO43_EDATA2.
+*/
+#define CAN_EMO43DATA2 (CAN_MO43_EDATA2)
+
+/** \brief 156C, Message Object Acceptance Mask Register */
+#define CAN_MO43_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001956Cu)
+
+/** Alias (User Manual Name) for CAN_MO43_EDATA3.
+* To use register names with standard convension, please use CAN_MO43_EDATA3.
+*/
+#define CAN_EMO43DATA3 (CAN_MO43_EDATA3)
+
+/** \brief 1570, Message Object Data Register Low */
+#define CAN_MO43_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019570u)
+
+/** Alias (User Manual Name) for CAN_MO43_EDATA4.
+* To use register names with standard convension, please use CAN_MO43_EDATA4.
+*/
+#define CAN_EMO43DATA4 (CAN_MO43_EDATA4)
+
+/** \brief 1574, Message Object Data Register High */
+#define CAN_MO43_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019574u)
+
+/** Alias (User Manual Name) for CAN_MO43_EDATA5.
+* To use register names with standard convension, please use CAN_MO43_EDATA5.
+*/
+#define CAN_EMO43DATA5 (CAN_MO43_EDATA5)
+
+/** \brief 1578, Message Object Arbitration Register */
+#define CAN_MO43_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019578u)
+
+/** Alias (User Manual Name) for CAN_MO43_EDATA6.
+* To use register names with standard convension, please use CAN_MO43_EDATA6.
+*/
+#define CAN_EMO43DATA6 (CAN_MO43_EDATA6)
+
+/** \brief 1560, Message Object Function Control Register */
+#define CAN_MO43_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019560u)
+
+/** Alias (User Manual Name) for CAN_MO43_FCR.
+* To use register names with standard convension, please use CAN_MO43_FCR.
+*/
+#define CAN_MOFCR43 (CAN_MO43_FCR)
+
+/** \brief 1564, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO43_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019564u)
+
+/** Alias (User Manual Name) for CAN_MO43_FGPR.
+* To use register names with standard convension, please use CAN_MO43_FGPR.
+*/
+#define CAN_MOFGPR43 (CAN_MO43_FGPR)
+
+/** \brief 1568, Message Object Interrupt Pointer Register */
+#define CAN_MO43_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019568u)
+
+/** Alias (User Manual Name) for CAN_MO43_IPR.
+* To use register names with standard convension, please use CAN_MO43_IPR.
+*/
+#define CAN_MOIPR43 (CAN_MO43_IPR)
+
+/** \brief 157C, Message Object Control Register */
+#define CAN_MO43_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001957Cu)
+
+/** Alias (User Manual Name) for CAN_MO43_STAT.
+* To use register names with standard convension, please use CAN_MO43_STAT.
+*/
+#define CAN_MOSTAT43 (CAN_MO43_STAT)
+
+/** \brief 158C, Message Object Acceptance Mask Register */
+#define CAN_MO44_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001958Cu)
+
+/** Alias (User Manual Name) for CAN_MO44_AMR.
+* To use register names with standard convension, please use CAN_MO44_AMR.
+*/
+#define CAN_MOAMR44 (CAN_MO44_AMR)
+
+/** \brief 1598, Message Object Arbitration Register */
+#define CAN_MO44_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019598u)
+
+/** Alias (User Manual Name) for CAN_MO44_AR.
+* To use register names with standard convension, please use CAN_MO44_AR.
+*/
+#define CAN_MOAR44 (CAN_MO44_AR)
+
+/** \brief 159C, Message Object Control Register */
+#define CAN_MO44_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001959Cu)
+
+/** Alias (User Manual Name) for CAN_MO44_CTR.
+* To use register names with standard convension, please use CAN_MO44_CTR.
+*/
+#define CAN_MOCTR44 (CAN_MO44_CTR)
+
+/** \brief 1594, Message Object Data Register High */
+#define CAN_MO44_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019594u)
+
+/** Alias (User Manual Name) for CAN_MO44_DATAH.
+* To use register names with standard convension, please use CAN_MO44_DATAH.
+*/
+#define CAN_MODATAH44 (CAN_MO44_DATAH)
+
+/** \brief 1590, Message Object Data Register Low */
+#define CAN_MO44_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019590u)
+
+/** Alias (User Manual Name) for CAN_MO44_DATAL.
+* To use register names with standard convension, please use CAN_MO44_DATAL.
+*/
+#define CAN_MODATAL44 (CAN_MO44_DATAL)
+
+/** \brief 1580, Message Object Function Control Register */
+#define CAN_MO44_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019580u)
+
+/** Alias (User Manual Name) for CAN_MO44_EDATA0.
+* To use register names with standard convension, please use CAN_MO44_EDATA0.
+*/
+#define CAN_EMO44DATA0 (CAN_MO44_EDATA0)
+
+/** \brief 1584, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO44_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019584u)
+
+/** Alias (User Manual Name) for CAN_MO44_EDATA1.
+* To use register names with standard convension, please use CAN_MO44_EDATA1.
+*/
+#define CAN_EMO44DATA1 (CAN_MO44_EDATA1)
+
+/** \brief 1588, Message Object Interrupt Pointer Register */
+#define CAN_MO44_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019588u)
+
+/** Alias (User Manual Name) for CAN_MO44_EDATA2.
+* To use register names with standard convension, please use CAN_MO44_EDATA2.
+*/
+#define CAN_EMO44DATA2 (CAN_MO44_EDATA2)
+
+/** \brief 158C, Message Object Acceptance Mask Register */
+#define CAN_MO44_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001958Cu)
+
+/** Alias (User Manual Name) for CAN_MO44_EDATA3.
+* To use register names with standard convension, please use CAN_MO44_EDATA3.
+*/
+#define CAN_EMO44DATA3 (CAN_MO44_EDATA3)
+
+/** \brief 1590, Message Object Data Register Low */
+#define CAN_MO44_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019590u)
+
+/** Alias (User Manual Name) for CAN_MO44_EDATA4.
+* To use register names with standard convension, please use CAN_MO44_EDATA4.
+*/
+#define CAN_EMO44DATA4 (CAN_MO44_EDATA4)
+
+/** \brief 1594, Message Object Data Register High */
+#define CAN_MO44_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019594u)
+
+/** Alias (User Manual Name) for CAN_MO44_EDATA5.
+* To use register names with standard convension, please use CAN_MO44_EDATA5.
+*/
+#define CAN_EMO44DATA5 (CAN_MO44_EDATA5)
+
+/** \brief 1598, Message Object Arbitration Register */
+#define CAN_MO44_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019598u)
+
+/** Alias (User Manual Name) for CAN_MO44_EDATA6.
+* To use register names with standard convension, please use CAN_MO44_EDATA6.
+*/
+#define CAN_EMO44DATA6 (CAN_MO44_EDATA6)
+
+/** \brief 1580, Message Object Function Control Register */
+#define CAN_MO44_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019580u)
+
+/** Alias (User Manual Name) for CAN_MO44_FCR.
+* To use register names with standard convension, please use CAN_MO44_FCR.
+*/
+#define CAN_MOFCR44 (CAN_MO44_FCR)
+
+/** \brief 1584, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO44_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019584u)
+
+/** Alias (User Manual Name) for CAN_MO44_FGPR.
+* To use register names with standard convension, please use CAN_MO44_FGPR.
+*/
+#define CAN_MOFGPR44 (CAN_MO44_FGPR)
+
+/** \brief 1588, Message Object Interrupt Pointer Register */
+#define CAN_MO44_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019588u)
+
+/** Alias (User Manual Name) for CAN_MO44_IPR.
+* To use register names with standard convension, please use CAN_MO44_IPR.
+*/
+#define CAN_MOIPR44 (CAN_MO44_IPR)
+
+/** \brief 159C, Message Object Control Register */
+#define CAN_MO44_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001959Cu)
+
+/** Alias (User Manual Name) for CAN_MO44_STAT.
+* To use register names with standard convension, please use CAN_MO44_STAT.
+*/
+#define CAN_MOSTAT44 (CAN_MO44_STAT)
+
+/** \brief 15AC, Message Object Acceptance Mask Register */
+#define CAN_MO45_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00195ACu)
+
+/** Alias (User Manual Name) for CAN_MO45_AMR.
+* To use register names with standard convension, please use CAN_MO45_AMR.
+*/
+#define CAN_MOAMR45 (CAN_MO45_AMR)
+
+/** \brief 15B8, Message Object Arbitration Register */
+#define CAN_MO45_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00195B8u)
+
+/** Alias (User Manual Name) for CAN_MO45_AR.
+* To use register names with standard convension, please use CAN_MO45_AR.
+*/
+#define CAN_MOAR45 (CAN_MO45_AR)
+
+/** \brief 15BC, Message Object Control Register */
+#define CAN_MO45_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00195BCu)
+
+/** Alias (User Manual Name) for CAN_MO45_CTR.
+* To use register names with standard convension, please use CAN_MO45_CTR.
+*/
+#define CAN_MOCTR45 (CAN_MO45_CTR)
+
+/** \brief 15B4, Message Object Data Register High */
+#define CAN_MO45_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00195B4u)
+
+/** Alias (User Manual Name) for CAN_MO45_DATAH.
+* To use register names with standard convension, please use CAN_MO45_DATAH.
+*/
+#define CAN_MODATAH45 (CAN_MO45_DATAH)
+
+/** \brief 15B0, Message Object Data Register Low */
+#define CAN_MO45_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00195B0u)
+
+/** Alias (User Manual Name) for CAN_MO45_DATAL.
+* To use register names with standard convension, please use CAN_MO45_DATAL.
+*/
+#define CAN_MODATAL45 (CAN_MO45_DATAL)
+
+/** \brief 15A0, Message Object Function Control Register */
+#define CAN_MO45_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00195A0u)
+
+/** Alias (User Manual Name) for CAN_MO45_EDATA0.
+* To use register names with standard convension, please use CAN_MO45_EDATA0.
+*/
+#define CAN_EMO45DATA0 (CAN_MO45_EDATA0)
+
+/** \brief 15A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO45_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00195A4u)
+
+/** Alias (User Manual Name) for CAN_MO45_EDATA1.
+* To use register names with standard convension, please use CAN_MO45_EDATA1.
+*/
+#define CAN_EMO45DATA1 (CAN_MO45_EDATA1)
+
+/** \brief 15A8, Message Object Interrupt Pointer Register */
+#define CAN_MO45_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00195A8u)
+
+/** Alias (User Manual Name) for CAN_MO45_EDATA2.
+* To use register names with standard convension, please use CAN_MO45_EDATA2.
+*/
+#define CAN_EMO45DATA2 (CAN_MO45_EDATA2)
+
+/** \brief 15AC, Message Object Acceptance Mask Register */
+#define CAN_MO45_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00195ACu)
+
+/** Alias (User Manual Name) for CAN_MO45_EDATA3.
+* To use register names with standard convension, please use CAN_MO45_EDATA3.
+*/
+#define CAN_EMO45DATA3 (CAN_MO45_EDATA3)
+
+/** \brief 15B0, Message Object Data Register Low */
+#define CAN_MO45_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00195B0u)
+
+/** Alias (User Manual Name) for CAN_MO45_EDATA4.
+* To use register names with standard convension, please use CAN_MO45_EDATA4.
+*/
+#define CAN_EMO45DATA4 (CAN_MO45_EDATA4)
+
+/** \brief 15B4, Message Object Data Register High */
+#define CAN_MO45_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00195B4u)
+
+/** Alias (User Manual Name) for CAN_MO45_EDATA5.
+* To use register names with standard convension, please use CAN_MO45_EDATA5.
+*/
+#define CAN_EMO45DATA5 (CAN_MO45_EDATA5)
+
+/** \brief 15B8, Message Object Arbitration Register */
+#define CAN_MO45_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00195B8u)
+
+/** Alias (User Manual Name) for CAN_MO45_EDATA6.
+* To use register names with standard convension, please use CAN_MO45_EDATA6.
+*/
+#define CAN_EMO45DATA6 (CAN_MO45_EDATA6)
+
+/** \brief 15A0, Message Object Function Control Register */
+#define CAN_MO45_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00195A0u)
+
+/** Alias (User Manual Name) for CAN_MO45_FCR.
+* To use register names with standard convension, please use CAN_MO45_FCR.
+*/
+#define CAN_MOFCR45 (CAN_MO45_FCR)
+
+/** \brief 15A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO45_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00195A4u)
+
+/** Alias (User Manual Name) for CAN_MO45_FGPR.
+* To use register names with standard convension, please use CAN_MO45_FGPR.
+*/
+#define CAN_MOFGPR45 (CAN_MO45_FGPR)
+
+/** \brief 15A8, Message Object Interrupt Pointer Register */
+#define CAN_MO45_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00195A8u)
+
+/** Alias (User Manual Name) for CAN_MO45_IPR.
+* To use register names with standard convension, please use CAN_MO45_IPR.
+*/
+#define CAN_MOIPR45 (CAN_MO45_IPR)
+
+/** \brief 15BC, Message Object Control Register */
+#define CAN_MO45_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00195BCu)
+
+/** Alias (User Manual Name) for CAN_MO45_STAT.
+* To use register names with standard convension, please use CAN_MO45_STAT.
+*/
+#define CAN_MOSTAT45 (CAN_MO45_STAT)
+
+/** \brief 15CC, Message Object Acceptance Mask Register */
+#define CAN_MO46_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00195CCu)
+
+/** Alias (User Manual Name) for CAN_MO46_AMR.
+* To use register names with standard convension, please use CAN_MO46_AMR.
+*/
+#define CAN_MOAMR46 (CAN_MO46_AMR)
+
+/** \brief 15D8, Message Object Arbitration Register */
+#define CAN_MO46_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00195D8u)
+
+/** Alias (User Manual Name) for CAN_MO46_AR.
+* To use register names with standard convension, please use CAN_MO46_AR.
+*/
+#define CAN_MOAR46 (CAN_MO46_AR)
+
+/** \brief 15DC, Message Object Control Register */
+#define CAN_MO46_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00195DCu)
+
+/** Alias (User Manual Name) for CAN_MO46_CTR.
+* To use register names with standard convension, please use CAN_MO46_CTR.
+*/
+#define CAN_MOCTR46 (CAN_MO46_CTR)
+
+/** \brief 15D4, Message Object Data Register High */
+#define CAN_MO46_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00195D4u)
+
+/** Alias (User Manual Name) for CAN_MO46_DATAH.
+* To use register names with standard convension, please use CAN_MO46_DATAH.
+*/
+#define CAN_MODATAH46 (CAN_MO46_DATAH)
+
+/** \brief 15D0, Message Object Data Register Low */
+#define CAN_MO46_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00195D0u)
+
+/** Alias (User Manual Name) for CAN_MO46_DATAL.
+* To use register names with standard convension, please use CAN_MO46_DATAL.
+*/
+#define CAN_MODATAL46 (CAN_MO46_DATAL)
+
+/** \brief 15C0, Message Object Function Control Register */
+#define CAN_MO46_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00195C0u)
+
+/** Alias (User Manual Name) for CAN_MO46_EDATA0.
+* To use register names with standard convension, please use CAN_MO46_EDATA0.
+*/
+#define CAN_EMO46DATA0 (CAN_MO46_EDATA0)
+
+/** \brief 15C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO46_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00195C4u)
+
+/** Alias (User Manual Name) for CAN_MO46_EDATA1.
+* To use register names with standard convension, please use CAN_MO46_EDATA1.
+*/
+#define CAN_EMO46DATA1 (CAN_MO46_EDATA1)
+
+/** \brief 15C8, Message Object Interrupt Pointer Register */
+#define CAN_MO46_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00195C8u)
+
+/** Alias (User Manual Name) for CAN_MO46_EDATA2.
+* To use register names with standard convension, please use CAN_MO46_EDATA2.
+*/
+#define CAN_EMO46DATA2 (CAN_MO46_EDATA2)
+
+/** \brief 15CC, Message Object Acceptance Mask Register */
+#define CAN_MO46_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00195CCu)
+
+/** Alias (User Manual Name) for CAN_MO46_EDATA3.
+* To use register names with standard convension, please use CAN_MO46_EDATA3.
+*/
+#define CAN_EMO46DATA3 (CAN_MO46_EDATA3)
+
+/** \brief 15D0, Message Object Data Register Low */
+#define CAN_MO46_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00195D0u)
+
+/** Alias (User Manual Name) for CAN_MO46_EDATA4.
+* To use register names with standard convension, please use CAN_MO46_EDATA4.
+*/
+#define CAN_EMO46DATA4 (CAN_MO46_EDATA4)
+
+/** \brief 15D4, Message Object Data Register High */
+#define CAN_MO46_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00195D4u)
+
+/** Alias (User Manual Name) for CAN_MO46_EDATA5.
+* To use register names with standard convension, please use CAN_MO46_EDATA5.
+*/
+#define CAN_EMO46DATA5 (CAN_MO46_EDATA5)
+
+/** \brief 15D8, Message Object Arbitration Register */
+#define CAN_MO46_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00195D8u)
+
+/** Alias (User Manual Name) for CAN_MO46_EDATA6.
+* To use register names with standard convension, please use CAN_MO46_EDATA6.
+*/
+#define CAN_EMO46DATA6 (CAN_MO46_EDATA6)
+
+/** \brief 15C0, Message Object Function Control Register */
+#define CAN_MO46_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00195C0u)
+
+/** Alias (User Manual Name) for CAN_MO46_FCR.
+* To use register names with standard convension, please use CAN_MO46_FCR.
+*/
+#define CAN_MOFCR46 (CAN_MO46_FCR)
+
+/** \brief 15C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO46_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00195C4u)
+
+/** Alias (User Manual Name) for CAN_MO46_FGPR.
+* To use register names with standard convension, please use CAN_MO46_FGPR.
+*/
+#define CAN_MOFGPR46 (CAN_MO46_FGPR)
+
+/** \brief 15C8, Message Object Interrupt Pointer Register */
+#define CAN_MO46_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00195C8u)
+
+/** Alias (User Manual Name) for CAN_MO46_IPR.
+* To use register names with standard convension, please use CAN_MO46_IPR.
+*/
+#define CAN_MOIPR46 (CAN_MO46_IPR)
+
+/** \brief 15DC, Message Object Control Register */
+#define CAN_MO46_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00195DCu)
+
+/** Alias (User Manual Name) for CAN_MO46_STAT.
+* To use register names with standard convension, please use CAN_MO46_STAT.
+*/
+#define CAN_MOSTAT46 (CAN_MO46_STAT)
+
+/** \brief 15EC, Message Object Acceptance Mask Register */
+#define CAN_MO47_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00195ECu)
+
+/** Alias (User Manual Name) for CAN_MO47_AMR.
+* To use register names with standard convension, please use CAN_MO47_AMR.
+*/
+#define CAN_MOAMR47 (CAN_MO47_AMR)
+
+/** \brief 15F8, Message Object Arbitration Register */
+#define CAN_MO47_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00195F8u)
+
+/** Alias (User Manual Name) for CAN_MO47_AR.
+* To use register names with standard convension, please use CAN_MO47_AR.
+*/
+#define CAN_MOAR47 (CAN_MO47_AR)
+
+/** \brief 15FC, Message Object Control Register */
+#define CAN_MO47_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00195FCu)
+
+/** Alias (User Manual Name) for CAN_MO47_CTR.
+* To use register names with standard convension, please use CAN_MO47_CTR.
+*/
+#define CAN_MOCTR47 (CAN_MO47_CTR)
+
+/** \brief 15F4, Message Object Data Register High */
+#define CAN_MO47_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00195F4u)
+
+/** Alias (User Manual Name) for CAN_MO47_DATAH.
+* To use register names with standard convension, please use CAN_MO47_DATAH.
+*/
+#define CAN_MODATAH47 (CAN_MO47_DATAH)
+
+/** \brief 15F0, Message Object Data Register Low */
+#define CAN_MO47_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00195F0u)
+
+/** Alias (User Manual Name) for CAN_MO47_DATAL.
+* To use register names with standard convension, please use CAN_MO47_DATAL.
+*/
+#define CAN_MODATAL47 (CAN_MO47_DATAL)
+
+/** \brief 15E0, Message Object Function Control Register */
+#define CAN_MO47_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00195E0u)
+
+/** Alias (User Manual Name) for CAN_MO47_EDATA0.
+* To use register names with standard convension, please use CAN_MO47_EDATA0.
+*/
+#define CAN_EMO47DATA0 (CAN_MO47_EDATA0)
+
+/** \brief 15E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO47_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00195E4u)
+
+/** Alias (User Manual Name) for CAN_MO47_EDATA1.
+* To use register names with standard convension, please use CAN_MO47_EDATA1.
+*/
+#define CAN_EMO47DATA1 (CAN_MO47_EDATA1)
+
+/** \brief 15E8, Message Object Interrupt Pointer Register */
+#define CAN_MO47_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00195E8u)
+
+/** Alias (User Manual Name) for CAN_MO47_EDATA2.
+* To use register names with standard convension, please use CAN_MO47_EDATA2.
+*/
+#define CAN_EMO47DATA2 (CAN_MO47_EDATA2)
+
+/** \brief 15EC, Message Object Acceptance Mask Register */
+#define CAN_MO47_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00195ECu)
+
+/** Alias (User Manual Name) for CAN_MO47_EDATA3.
+* To use register names with standard convension, please use CAN_MO47_EDATA3.
+*/
+#define CAN_EMO47DATA3 (CAN_MO47_EDATA3)
+
+/** \brief 15F0, Message Object Data Register Low */
+#define CAN_MO47_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00195F0u)
+
+/** Alias (User Manual Name) for CAN_MO47_EDATA4.
+* To use register names with standard convension, please use CAN_MO47_EDATA4.
+*/
+#define CAN_EMO47DATA4 (CAN_MO47_EDATA4)
+
+/** \brief 15F4, Message Object Data Register High */
+#define CAN_MO47_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00195F4u)
+
+/** Alias (User Manual Name) for CAN_MO47_EDATA5.
+* To use register names with standard convension, please use CAN_MO47_EDATA5.
+*/
+#define CAN_EMO47DATA5 (CAN_MO47_EDATA5)
+
+/** \brief 15F8, Message Object Arbitration Register */
+#define CAN_MO47_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00195F8u)
+
+/** Alias (User Manual Name) for CAN_MO47_EDATA6.
+* To use register names with standard convension, please use CAN_MO47_EDATA6.
+*/
+#define CAN_EMO47DATA6 (CAN_MO47_EDATA6)
+
+/** \brief 15E0, Message Object Function Control Register */
+#define CAN_MO47_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00195E0u)
+
+/** Alias (User Manual Name) for CAN_MO47_FCR.
+* To use register names with standard convension, please use CAN_MO47_FCR.
+*/
+#define CAN_MOFCR47 (CAN_MO47_FCR)
+
+/** \brief 15E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO47_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00195E4u)
+
+/** Alias (User Manual Name) for CAN_MO47_FGPR.
+* To use register names with standard convension, please use CAN_MO47_FGPR.
+*/
+#define CAN_MOFGPR47 (CAN_MO47_FGPR)
+
+/** \brief 15E8, Message Object Interrupt Pointer Register */
+#define CAN_MO47_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00195E8u)
+
+/** Alias (User Manual Name) for CAN_MO47_IPR.
+* To use register names with standard convension, please use CAN_MO47_IPR.
+*/
+#define CAN_MOIPR47 (CAN_MO47_IPR)
+
+/** \brief 15FC, Message Object Control Register */
+#define CAN_MO47_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00195FCu)
+
+/** Alias (User Manual Name) for CAN_MO47_STAT.
+* To use register names with standard convension, please use CAN_MO47_STAT.
+*/
+#define CAN_MOSTAT47 (CAN_MO47_STAT)
+
+/** \brief 160C, Message Object Acceptance Mask Register */
+#define CAN_MO48_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001960Cu)
+
+/** Alias (User Manual Name) for CAN_MO48_AMR.
+* To use register names with standard convension, please use CAN_MO48_AMR.
+*/
+#define CAN_MOAMR48 (CAN_MO48_AMR)
+
+/** \brief 1618, Message Object Arbitration Register */
+#define CAN_MO48_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019618u)
+
+/** Alias (User Manual Name) for CAN_MO48_AR.
+* To use register names with standard convension, please use CAN_MO48_AR.
+*/
+#define CAN_MOAR48 (CAN_MO48_AR)
+
+/** \brief 161C, Message Object Control Register */
+#define CAN_MO48_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001961Cu)
+
+/** Alias (User Manual Name) for CAN_MO48_CTR.
+* To use register names with standard convension, please use CAN_MO48_CTR.
+*/
+#define CAN_MOCTR48 (CAN_MO48_CTR)
+
+/** \brief 1614, Message Object Data Register High */
+#define CAN_MO48_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019614u)
+
+/** Alias (User Manual Name) for CAN_MO48_DATAH.
+* To use register names with standard convension, please use CAN_MO48_DATAH.
+*/
+#define CAN_MODATAH48 (CAN_MO48_DATAH)
+
+/** \brief 1610, Message Object Data Register Low */
+#define CAN_MO48_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019610u)
+
+/** Alias (User Manual Name) for CAN_MO48_DATAL.
+* To use register names with standard convension, please use CAN_MO48_DATAL.
+*/
+#define CAN_MODATAL48 (CAN_MO48_DATAL)
+
+/** \brief 1600, Message Object Function Control Register */
+#define CAN_MO48_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019600u)
+
+/** Alias (User Manual Name) for CAN_MO48_EDATA0.
+* To use register names with standard convension, please use CAN_MO48_EDATA0.
+*/
+#define CAN_EMO48DATA0 (CAN_MO48_EDATA0)
+
+/** \brief 1604, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO48_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019604u)
+
+/** Alias (User Manual Name) for CAN_MO48_EDATA1.
+* To use register names with standard convension, please use CAN_MO48_EDATA1.
+*/
+#define CAN_EMO48DATA1 (CAN_MO48_EDATA1)
+
+/** \brief 1608, Message Object Interrupt Pointer Register */
+#define CAN_MO48_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019608u)
+
+/** Alias (User Manual Name) for CAN_MO48_EDATA2.
+* To use register names with standard convension, please use CAN_MO48_EDATA2.
+*/
+#define CAN_EMO48DATA2 (CAN_MO48_EDATA2)
+
+/** \brief 160C, Message Object Acceptance Mask Register */
+#define CAN_MO48_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001960Cu)
+
+/** Alias (User Manual Name) for CAN_MO48_EDATA3.
+* To use register names with standard convension, please use CAN_MO48_EDATA3.
+*/
+#define CAN_EMO48DATA3 (CAN_MO48_EDATA3)
+
+/** \brief 1610, Message Object Data Register Low */
+#define CAN_MO48_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019610u)
+
+/** Alias (User Manual Name) for CAN_MO48_EDATA4.
+* To use register names with standard convension, please use CAN_MO48_EDATA4.
+*/
+#define CAN_EMO48DATA4 (CAN_MO48_EDATA4)
+
+/** \brief 1614, Message Object Data Register High */
+#define CAN_MO48_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019614u)
+
+/** Alias (User Manual Name) for CAN_MO48_EDATA5.
+* To use register names with standard convension, please use CAN_MO48_EDATA5.
+*/
+#define CAN_EMO48DATA5 (CAN_MO48_EDATA5)
+
+/** \brief 1618, Message Object Arbitration Register */
+#define CAN_MO48_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019618u)
+
+/** Alias (User Manual Name) for CAN_MO48_EDATA6.
+* To use register names with standard convension, please use CAN_MO48_EDATA6.
+*/
+#define CAN_EMO48DATA6 (CAN_MO48_EDATA6)
+
+/** \brief 1600, Message Object Function Control Register */
+#define CAN_MO48_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019600u)
+
+/** Alias (User Manual Name) for CAN_MO48_FCR.
+* To use register names with standard convension, please use CAN_MO48_FCR.
+*/
+#define CAN_MOFCR48 (CAN_MO48_FCR)
+
+/** \brief 1604, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO48_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019604u)
+
+/** Alias (User Manual Name) for CAN_MO48_FGPR.
+* To use register names with standard convension, please use CAN_MO48_FGPR.
+*/
+#define CAN_MOFGPR48 (CAN_MO48_FGPR)
+
+/** \brief 1608, Message Object Interrupt Pointer Register */
+#define CAN_MO48_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019608u)
+
+/** Alias (User Manual Name) for CAN_MO48_IPR.
+* To use register names with standard convension, please use CAN_MO48_IPR.
+*/
+#define CAN_MOIPR48 (CAN_MO48_IPR)
+
+/** \brief 161C, Message Object Control Register */
+#define CAN_MO48_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001961Cu)
+
+/** Alias (User Manual Name) for CAN_MO48_STAT.
+* To use register names with standard convension, please use CAN_MO48_STAT.
+*/
+#define CAN_MOSTAT48 (CAN_MO48_STAT)
+
+/** \brief 162C, Message Object Acceptance Mask Register */
+#define CAN_MO49_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001962Cu)
+
+/** Alias (User Manual Name) for CAN_MO49_AMR.
+* To use register names with standard convension, please use CAN_MO49_AMR.
+*/
+#define CAN_MOAMR49 (CAN_MO49_AMR)
+
+/** \brief 1638, Message Object Arbitration Register */
+#define CAN_MO49_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019638u)
+
+/** Alias (User Manual Name) for CAN_MO49_AR.
+* To use register names with standard convension, please use CAN_MO49_AR.
+*/
+#define CAN_MOAR49 (CAN_MO49_AR)
+
+/** \brief 163C, Message Object Control Register */
+#define CAN_MO49_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001963Cu)
+
+/** Alias (User Manual Name) for CAN_MO49_CTR.
+* To use register names with standard convension, please use CAN_MO49_CTR.
+*/
+#define CAN_MOCTR49 (CAN_MO49_CTR)
+
+/** \brief 1634, Message Object Data Register High */
+#define CAN_MO49_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019634u)
+
+/** Alias (User Manual Name) for CAN_MO49_DATAH.
+* To use register names with standard convension, please use CAN_MO49_DATAH.
+*/
+#define CAN_MODATAH49 (CAN_MO49_DATAH)
+
+/** \brief 1630, Message Object Data Register Low */
+#define CAN_MO49_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019630u)
+
+/** Alias (User Manual Name) for CAN_MO49_DATAL.
+* To use register names with standard convension, please use CAN_MO49_DATAL.
+*/
+#define CAN_MODATAL49 (CAN_MO49_DATAL)
+
+/** \brief 1620, Message Object Function Control Register */
+#define CAN_MO49_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019620u)
+
+/** Alias (User Manual Name) for CAN_MO49_EDATA0.
+* To use register names with standard convension, please use CAN_MO49_EDATA0.
+*/
+#define CAN_EMO49DATA0 (CAN_MO49_EDATA0)
+
+/** \brief 1624, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO49_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019624u)
+
+/** Alias (User Manual Name) for CAN_MO49_EDATA1.
+* To use register names with standard convension, please use CAN_MO49_EDATA1.
+*/
+#define CAN_EMO49DATA1 (CAN_MO49_EDATA1)
+
+/** \brief 1628, Message Object Interrupt Pointer Register */
+#define CAN_MO49_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019628u)
+
+/** Alias (User Manual Name) for CAN_MO49_EDATA2.
+* To use register names with standard convension, please use CAN_MO49_EDATA2.
+*/
+#define CAN_EMO49DATA2 (CAN_MO49_EDATA2)
+
+/** \brief 162C, Message Object Acceptance Mask Register */
+#define CAN_MO49_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001962Cu)
+
+/** Alias (User Manual Name) for CAN_MO49_EDATA3.
+* To use register names with standard convension, please use CAN_MO49_EDATA3.
+*/
+#define CAN_EMO49DATA3 (CAN_MO49_EDATA3)
+
+/** \brief 1630, Message Object Data Register Low */
+#define CAN_MO49_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019630u)
+
+/** Alias (User Manual Name) for CAN_MO49_EDATA4.
+* To use register names with standard convension, please use CAN_MO49_EDATA4.
+*/
+#define CAN_EMO49DATA4 (CAN_MO49_EDATA4)
+
+/** \brief 1634, Message Object Data Register High */
+#define CAN_MO49_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019634u)
+
+/** Alias (User Manual Name) for CAN_MO49_EDATA5.
+* To use register names with standard convension, please use CAN_MO49_EDATA5.
+*/
+#define CAN_EMO49DATA5 (CAN_MO49_EDATA5)
+
+/** \brief 1638, Message Object Arbitration Register */
+#define CAN_MO49_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019638u)
+
+/** Alias (User Manual Name) for CAN_MO49_EDATA6.
+* To use register names with standard convension, please use CAN_MO49_EDATA6.
+*/
+#define CAN_EMO49DATA6 (CAN_MO49_EDATA6)
+
+/** \brief 1620, Message Object Function Control Register */
+#define CAN_MO49_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019620u)
+
+/** Alias (User Manual Name) for CAN_MO49_FCR.
+* To use register names with standard convension, please use CAN_MO49_FCR.
+*/
+#define CAN_MOFCR49 (CAN_MO49_FCR)
+
+/** \brief 1624, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO49_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019624u)
+
+/** Alias (User Manual Name) for CAN_MO49_FGPR.
+* To use register names with standard convension, please use CAN_MO49_FGPR.
+*/
+#define CAN_MOFGPR49 (CAN_MO49_FGPR)
+
+/** \brief 1628, Message Object Interrupt Pointer Register */
+#define CAN_MO49_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019628u)
+
+/** Alias (User Manual Name) for CAN_MO49_IPR.
+* To use register names with standard convension, please use CAN_MO49_IPR.
+*/
+#define CAN_MOIPR49 (CAN_MO49_IPR)
+
+/** \brief 163C, Message Object Control Register */
+#define CAN_MO49_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001963Cu)
+
+/** Alias (User Manual Name) for CAN_MO49_STAT.
+* To use register names with standard convension, please use CAN_MO49_STAT.
+*/
+#define CAN_MOSTAT49 (CAN_MO49_STAT)
+
+/** \brief 108C, Message Object Acceptance Mask Register */
+#define CAN_MO4_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001908Cu)
+
+/** Alias (User Manual Name) for CAN_MO4_AMR.
+* To use register names with standard convension, please use CAN_MO4_AMR.
+*/
+#define CAN_MOAMR4 (CAN_MO4_AMR)
+
+/** \brief 1098, Message Object Arbitration Register */
+#define CAN_MO4_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019098u)
+
+/** Alias (User Manual Name) for CAN_MO4_AR.
+* To use register names with standard convension, please use CAN_MO4_AR.
+*/
+#define CAN_MOAR4 (CAN_MO4_AR)
+
+/** \brief 109C, Message Object Control Register */
+#define CAN_MO4_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001909Cu)
+
+/** Alias (User Manual Name) for CAN_MO4_CTR.
+* To use register names with standard convension, please use CAN_MO4_CTR.
+*/
+#define CAN_MOCTR4 (CAN_MO4_CTR)
+
+/** \brief 1094, Message Object Data Register High */
+#define CAN_MO4_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019094u)
+
+/** Alias (User Manual Name) for CAN_MO4_DATAH.
+* To use register names with standard convension, please use CAN_MO4_DATAH.
+*/
+#define CAN_MODATAH4 (CAN_MO4_DATAH)
+
+/** \brief 1090, Message Object Data Register Low */
+#define CAN_MO4_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019090u)
+
+/** Alias (User Manual Name) for CAN_MO4_DATAL.
+* To use register names with standard convension, please use CAN_MO4_DATAL.
+*/
+#define CAN_MODATAL4 (CAN_MO4_DATAL)
+
+/** \brief 1080, Message Object Function Control Register */
+#define CAN_MO4_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019080u)
+
+/** Alias (User Manual Name) for CAN_MO4_EDATA0.
+* To use register names with standard convension, please use CAN_MO4_EDATA0.
+*/
+#define CAN_EMO4DATA0 (CAN_MO4_EDATA0)
+
+/** \brief 1084, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO4_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019084u)
+
+/** Alias (User Manual Name) for CAN_MO4_EDATA1.
+* To use register names with standard convension, please use CAN_MO4_EDATA1.
+*/
+#define CAN_EMO4DATA1 (CAN_MO4_EDATA1)
+
+/** \brief 1088, Message Object Interrupt Pointer Register */
+#define CAN_MO4_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019088u)
+
+/** Alias (User Manual Name) for CAN_MO4_EDATA2.
+* To use register names with standard convension, please use CAN_MO4_EDATA2.
+*/
+#define CAN_EMO4DATA2 (CAN_MO4_EDATA2)
+
+/** \brief 108C, Message Object Acceptance Mask Register */
+#define CAN_MO4_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001908Cu)
+
+/** Alias (User Manual Name) for CAN_MO4_EDATA3.
+* To use register names with standard convension, please use CAN_MO4_EDATA3.
+*/
+#define CAN_EMO4DATA3 (CAN_MO4_EDATA3)
+
+/** \brief 1090, Message Object Data Register Low */
+#define CAN_MO4_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019090u)
+
+/** Alias (User Manual Name) for CAN_MO4_EDATA4.
+* To use register names with standard convension, please use CAN_MO4_EDATA4.
+*/
+#define CAN_EMO4DATA4 (CAN_MO4_EDATA4)
+
+/** \brief 1094, Message Object Data Register High */
+#define CAN_MO4_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019094u)
+
+/** Alias (User Manual Name) for CAN_MO4_EDATA5.
+* To use register names with standard convension, please use CAN_MO4_EDATA5.
+*/
+#define CAN_EMO4DATA5 (CAN_MO4_EDATA5)
+
+/** \brief 1098, Message Object Arbitration Register */
+#define CAN_MO4_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019098u)
+
+/** Alias (User Manual Name) for CAN_MO4_EDATA6.
+* To use register names with standard convension, please use CAN_MO4_EDATA6.
+*/
+#define CAN_EMO4DATA6 (CAN_MO4_EDATA6)
+
+/** \brief 1080, Message Object Function Control Register */
+#define CAN_MO4_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019080u)
+
+/** Alias (User Manual Name) for CAN_MO4_FCR.
+* To use register names with standard convension, please use CAN_MO4_FCR.
+*/
+#define CAN_MOFCR4 (CAN_MO4_FCR)
+
+/** \brief 1084, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO4_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019084u)
+
+/** Alias (User Manual Name) for CAN_MO4_FGPR.
+* To use register names with standard convension, please use CAN_MO4_FGPR.
+*/
+#define CAN_MOFGPR4 (CAN_MO4_FGPR)
+
+/** \brief 1088, Message Object Interrupt Pointer Register */
+#define CAN_MO4_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019088u)
+
+/** Alias (User Manual Name) for CAN_MO4_IPR.
+* To use register names with standard convension, please use CAN_MO4_IPR.
+*/
+#define CAN_MOIPR4 (CAN_MO4_IPR)
+
+/** \brief 109C, Message Object Control Register */
+#define CAN_MO4_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001909Cu)
+
+/** Alias (User Manual Name) for CAN_MO4_STAT.
+* To use register names with standard convension, please use CAN_MO4_STAT.
+*/
+#define CAN_MOSTAT4 (CAN_MO4_STAT)
+
+/** \brief 164C, Message Object Acceptance Mask Register */
+#define CAN_MO50_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001964Cu)
+
+/** Alias (User Manual Name) for CAN_MO50_AMR.
+* To use register names with standard convension, please use CAN_MO50_AMR.
+*/
+#define CAN_MOAMR50 (CAN_MO50_AMR)
+
+/** \brief 1658, Message Object Arbitration Register */
+#define CAN_MO50_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019658u)
+
+/** Alias (User Manual Name) for CAN_MO50_AR.
+* To use register names with standard convension, please use CAN_MO50_AR.
+*/
+#define CAN_MOAR50 (CAN_MO50_AR)
+
+/** \brief 165C, Message Object Control Register */
+#define CAN_MO50_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001965Cu)
+
+/** Alias (User Manual Name) for CAN_MO50_CTR.
+* To use register names with standard convension, please use CAN_MO50_CTR.
+*/
+#define CAN_MOCTR50 (CAN_MO50_CTR)
+
+/** \brief 1654, Message Object Data Register High */
+#define CAN_MO50_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019654u)
+
+/** Alias (User Manual Name) for CAN_MO50_DATAH.
+* To use register names with standard convension, please use CAN_MO50_DATAH.
+*/
+#define CAN_MODATAH50 (CAN_MO50_DATAH)
+
+/** \brief 1650, Message Object Data Register Low */
+#define CAN_MO50_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019650u)
+
+/** Alias (User Manual Name) for CAN_MO50_DATAL.
+* To use register names with standard convension, please use CAN_MO50_DATAL.
+*/
+#define CAN_MODATAL50 (CAN_MO50_DATAL)
+
+/** \brief 1640, Message Object Function Control Register */
+#define CAN_MO50_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019640u)
+
+/** Alias (User Manual Name) for CAN_MO50_EDATA0.
+* To use register names with standard convension, please use CAN_MO50_EDATA0.
+*/
+#define CAN_EMO50DATA0 (CAN_MO50_EDATA0)
+
+/** \brief 1644, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO50_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019644u)
+
+/** Alias (User Manual Name) for CAN_MO50_EDATA1.
+* To use register names with standard convension, please use CAN_MO50_EDATA1.
+*/
+#define CAN_EMO50DATA1 (CAN_MO50_EDATA1)
+
+/** \brief 1648, Message Object Interrupt Pointer Register */
+#define CAN_MO50_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019648u)
+
+/** Alias (User Manual Name) for CAN_MO50_EDATA2.
+* To use register names with standard convension, please use CAN_MO50_EDATA2.
+*/
+#define CAN_EMO50DATA2 (CAN_MO50_EDATA2)
+
+/** \brief 164C, Message Object Acceptance Mask Register */
+#define CAN_MO50_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001964Cu)
+
+/** Alias (User Manual Name) for CAN_MO50_EDATA3.
+* To use register names with standard convension, please use CAN_MO50_EDATA3.
+*/
+#define CAN_EMO50DATA3 (CAN_MO50_EDATA3)
+
+/** \brief 1650, Message Object Data Register Low */
+#define CAN_MO50_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019650u)
+
+/** Alias (User Manual Name) for CAN_MO50_EDATA4.
+* To use register names with standard convension, please use CAN_MO50_EDATA4.
+*/
+#define CAN_EMO50DATA4 (CAN_MO50_EDATA4)
+
+/** \brief 1654, Message Object Data Register High */
+#define CAN_MO50_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019654u)
+
+/** Alias (User Manual Name) for CAN_MO50_EDATA5.
+* To use register names with standard convension, please use CAN_MO50_EDATA5.
+*/
+#define CAN_EMO50DATA5 (CAN_MO50_EDATA5)
+
+/** \brief 1658, Message Object Arbitration Register */
+#define CAN_MO50_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019658u)
+
+/** Alias (User Manual Name) for CAN_MO50_EDATA6.
+* To use register names with standard convension, please use CAN_MO50_EDATA6.
+*/
+#define CAN_EMO50DATA6 (CAN_MO50_EDATA6)
+
+/** \brief 1640, Message Object Function Control Register */
+#define CAN_MO50_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019640u)
+
+/** Alias (User Manual Name) for CAN_MO50_FCR.
+* To use register names with standard convension, please use CAN_MO50_FCR.
+*/
+#define CAN_MOFCR50 (CAN_MO50_FCR)
+
+/** \brief 1644, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO50_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019644u)
+
+/** Alias (User Manual Name) for CAN_MO50_FGPR.
+* To use register names with standard convension, please use CAN_MO50_FGPR.
+*/
+#define CAN_MOFGPR50 (CAN_MO50_FGPR)
+
+/** \brief 1648, Message Object Interrupt Pointer Register */
+#define CAN_MO50_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019648u)
+
+/** Alias (User Manual Name) for CAN_MO50_IPR.
+* To use register names with standard convension, please use CAN_MO50_IPR.
+*/
+#define CAN_MOIPR50 (CAN_MO50_IPR)
+
+/** \brief 165C, Message Object Control Register */
+#define CAN_MO50_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001965Cu)
+
+/** Alias (User Manual Name) for CAN_MO50_STAT.
+* To use register names with standard convension, please use CAN_MO50_STAT.
+*/
+#define CAN_MOSTAT50 (CAN_MO50_STAT)
+
+/** \brief 166C, Message Object Acceptance Mask Register */
+#define CAN_MO51_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001966Cu)
+
+/** Alias (User Manual Name) for CAN_MO51_AMR.
+* To use register names with standard convension, please use CAN_MO51_AMR.
+*/
+#define CAN_MOAMR51 (CAN_MO51_AMR)
+
+/** \brief 1678, Message Object Arbitration Register */
+#define CAN_MO51_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019678u)
+
+/** Alias (User Manual Name) for CAN_MO51_AR.
+* To use register names with standard convension, please use CAN_MO51_AR.
+*/
+#define CAN_MOAR51 (CAN_MO51_AR)
+
+/** \brief 167C, Message Object Control Register */
+#define CAN_MO51_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001967Cu)
+
+/** Alias (User Manual Name) for CAN_MO51_CTR.
+* To use register names with standard convension, please use CAN_MO51_CTR.
+*/
+#define CAN_MOCTR51 (CAN_MO51_CTR)
+
+/** \brief 1674, Message Object Data Register High */
+#define CAN_MO51_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019674u)
+
+/** Alias (User Manual Name) for CAN_MO51_DATAH.
+* To use register names with standard convension, please use CAN_MO51_DATAH.
+*/
+#define CAN_MODATAH51 (CAN_MO51_DATAH)
+
+/** \brief 1670, Message Object Data Register Low */
+#define CAN_MO51_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019670u)
+
+/** Alias (User Manual Name) for CAN_MO51_DATAL.
+* To use register names with standard convension, please use CAN_MO51_DATAL.
+*/
+#define CAN_MODATAL51 (CAN_MO51_DATAL)
+
+/** \brief 1660, Message Object Function Control Register */
+#define CAN_MO51_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019660u)
+
+/** Alias (User Manual Name) for CAN_MO51_EDATA0.
+* To use register names with standard convension, please use CAN_MO51_EDATA0.
+*/
+#define CAN_EMO51DATA0 (CAN_MO51_EDATA0)
+
+/** \brief 1664, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO51_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019664u)
+
+/** Alias (User Manual Name) for CAN_MO51_EDATA1.
+* To use register names with standard convension, please use CAN_MO51_EDATA1.
+*/
+#define CAN_EMO51DATA1 (CAN_MO51_EDATA1)
+
+/** \brief 1668, Message Object Interrupt Pointer Register */
+#define CAN_MO51_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019668u)
+
+/** Alias (User Manual Name) for CAN_MO51_EDATA2.
+* To use register names with standard convension, please use CAN_MO51_EDATA2.
+*/
+#define CAN_EMO51DATA2 (CAN_MO51_EDATA2)
+
+/** \brief 166C, Message Object Acceptance Mask Register */
+#define CAN_MO51_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001966Cu)
+
+/** Alias (User Manual Name) for CAN_MO51_EDATA3.
+* To use register names with standard convension, please use CAN_MO51_EDATA3.
+*/
+#define CAN_EMO51DATA3 (CAN_MO51_EDATA3)
+
+/** \brief 1670, Message Object Data Register Low */
+#define CAN_MO51_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019670u)
+
+/** Alias (User Manual Name) for CAN_MO51_EDATA4.
+* To use register names with standard convension, please use CAN_MO51_EDATA4.
+*/
+#define CAN_EMO51DATA4 (CAN_MO51_EDATA4)
+
+/** \brief 1674, Message Object Data Register High */
+#define CAN_MO51_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019674u)
+
+/** Alias (User Manual Name) for CAN_MO51_EDATA5.
+* To use register names with standard convension, please use CAN_MO51_EDATA5.
+*/
+#define CAN_EMO51DATA5 (CAN_MO51_EDATA5)
+
+/** \brief 1678, Message Object Arbitration Register */
+#define CAN_MO51_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019678u)
+
+/** Alias (User Manual Name) for CAN_MO51_EDATA6.
+* To use register names with standard convension, please use CAN_MO51_EDATA6.
+*/
+#define CAN_EMO51DATA6 (CAN_MO51_EDATA6)
+
+/** \brief 1660, Message Object Function Control Register */
+#define CAN_MO51_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019660u)
+
+/** Alias (User Manual Name) for CAN_MO51_FCR.
+* To use register names with standard convension, please use CAN_MO51_FCR.
+*/
+#define CAN_MOFCR51 (CAN_MO51_FCR)
+
+/** \brief 1664, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO51_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019664u)
+
+/** Alias (User Manual Name) for CAN_MO51_FGPR.
+* To use register names with standard convension, please use CAN_MO51_FGPR.
+*/
+#define CAN_MOFGPR51 (CAN_MO51_FGPR)
+
+/** \brief 1668, Message Object Interrupt Pointer Register */
+#define CAN_MO51_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019668u)
+
+/** Alias (User Manual Name) for CAN_MO51_IPR.
+* To use register names with standard convension, please use CAN_MO51_IPR.
+*/
+#define CAN_MOIPR51 (CAN_MO51_IPR)
+
+/** \brief 167C, Message Object Control Register */
+#define CAN_MO51_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001967Cu)
+
+/** Alias (User Manual Name) for CAN_MO51_STAT.
+* To use register names with standard convension, please use CAN_MO51_STAT.
+*/
+#define CAN_MOSTAT51 (CAN_MO51_STAT)
+
+/** \brief 168C, Message Object Acceptance Mask Register */
+#define CAN_MO52_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001968Cu)
+
+/** Alias (User Manual Name) for CAN_MO52_AMR.
+* To use register names with standard convension, please use CAN_MO52_AMR.
+*/
+#define CAN_MOAMR52 (CAN_MO52_AMR)
+
+/** \brief 1698, Message Object Arbitration Register */
+#define CAN_MO52_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019698u)
+
+/** Alias (User Manual Name) for CAN_MO52_AR.
+* To use register names with standard convension, please use CAN_MO52_AR.
+*/
+#define CAN_MOAR52 (CAN_MO52_AR)
+
+/** \brief 169C, Message Object Control Register */
+#define CAN_MO52_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001969Cu)
+
+/** Alias (User Manual Name) for CAN_MO52_CTR.
+* To use register names with standard convension, please use CAN_MO52_CTR.
+*/
+#define CAN_MOCTR52 (CAN_MO52_CTR)
+
+/** \brief 1694, Message Object Data Register High */
+#define CAN_MO52_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019694u)
+
+/** Alias (User Manual Name) for CAN_MO52_DATAH.
+* To use register names with standard convension, please use CAN_MO52_DATAH.
+*/
+#define CAN_MODATAH52 (CAN_MO52_DATAH)
+
+/** \brief 1690, Message Object Data Register Low */
+#define CAN_MO52_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019690u)
+
+/** Alias (User Manual Name) for CAN_MO52_DATAL.
+* To use register names with standard convension, please use CAN_MO52_DATAL.
+*/
+#define CAN_MODATAL52 (CAN_MO52_DATAL)
+
+/** \brief 1680, Message Object Function Control Register */
+#define CAN_MO52_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019680u)
+
+/** Alias (User Manual Name) for CAN_MO52_EDATA0.
+* To use register names with standard convension, please use CAN_MO52_EDATA0.
+*/
+#define CAN_EMO52DATA0 (CAN_MO52_EDATA0)
+
+/** \brief 1684, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO52_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019684u)
+
+/** Alias (User Manual Name) for CAN_MO52_EDATA1.
+* To use register names with standard convension, please use CAN_MO52_EDATA1.
+*/
+#define CAN_EMO52DATA1 (CAN_MO52_EDATA1)
+
+/** \brief 1688, Message Object Interrupt Pointer Register */
+#define CAN_MO52_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019688u)
+
+/** Alias (User Manual Name) for CAN_MO52_EDATA2.
+* To use register names with standard convension, please use CAN_MO52_EDATA2.
+*/
+#define CAN_EMO52DATA2 (CAN_MO52_EDATA2)
+
+/** \brief 168C, Message Object Acceptance Mask Register */
+#define CAN_MO52_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001968Cu)
+
+/** Alias (User Manual Name) for CAN_MO52_EDATA3.
+* To use register names with standard convension, please use CAN_MO52_EDATA3.
+*/
+#define CAN_EMO52DATA3 (CAN_MO52_EDATA3)
+
+/** \brief 1690, Message Object Data Register Low */
+#define CAN_MO52_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019690u)
+
+/** Alias (User Manual Name) for CAN_MO52_EDATA4.
+* To use register names with standard convension, please use CAN_MO52_EDATA4.
+*/
+#define CAN_EMO52DATA4 (CAN_MO52_EDATA4)
+
+/** \brief 1694, Message Object Data Register High */
+#define CAN_MO52_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019694u)
+
+/** Alias (User Manual Name) for CAN_MO52_EDATA5.
+* To use register names with standard convension, please use CAN_MO52_EDATA5.
+*/
+#define CAN_EMO52DATA5 (CAN_MO52_EDATA5)
+
+/** \brief 1698, Message Object Arbitration Register */
+#define CAN_MO52_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019698u)
+
+/** Alias (User Manual Name) for CAN_MO52_EDATA6.
+* To use register names with standard convension, please use CAN_MO52_EDATA6.
+*/
+#define CAN_EMO52DATA6 (CAN_MO52_EDATA6)
+
+/** \brief 1680, Message Object Function Control Register */
+#define CAN_MO52_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019680u)
+
+/** Alias (User Manual Name) for CAN_MO52_FCR.
+* To use register names with standard convension, please use CAN_MO52_FCR.
+*/
+#define CAN_MOFCR52 (CAN_MO52_FCR)
+
+/** \brief 1684, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO52_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019684u)
+
+/** Alias (User Manual Name) for CAN_MO52_FGPR.
+* To use register names with standard convension, please use CAN_MO52_FGPR.
+*/
+#define CAN_MOFGPR52 (CAN_MO52_FGPR)
+
+/** \brief 1688, Message Object Interrupt Pointer Register */
+#define CAN_MO52_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019688u)
+
+/** Alias (User Manual Name) for CAN_MO52_IPR.
+* To use register names with standard convension, please use CAN_MO52_IPR.
+*/
+#define CAN_MOIPR52 (CAN_MO52_IPR)
+
+/** \brief 169C, Message Object Control Register */
+#define CAN_MO52_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001969Cu)
+
+/** Alias (User Manual Name) for CAN_MO52_STAT.
+* To use register names with standard convension, please use CAN_MO52_STAT.
+*/
+#define CAN_MOSTAT52 (CAN_MO52_STAT)
+
+/** \brief 16AC, Message Object Acceptance Mask Register */
+#define CAN_MO53_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00196ACu)
+
+/** Alias (User Manual Name) for CAN_MO53_AMR.
+* To use register names with standard convension, please use CAN_MO53_AMR.
+*/
+#define CAN_MOAMR53 (CAN_MO53_AMR)
+
+/** \brief 16B8, Message Object Arbitration Register */
+#define CAN_MO53_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00196B8u)
+
+/** Alias (User Manual Name) for CAN_MO53_AR.
+* To use register names with standard convension, please use CAN_MO53_AR.
+*/
+#define CAN_MOAR53 (CAN_MO53_AR)
+
+/** \brief 16BC, Message Object Control Register */
+#define CAN_MO53_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00196BCu)
+
+/** Alias (User Manual Name) for CAN_MO53_CTR.
+* To use register names with standard convension, please use CAN_MO53_CTR.
+*/
+#define CAN_MOCTR53 (CAN_MO53_CTR)
+
+/** \brief 16B4, Message Object Data Register High */
+#define CAN_MO53_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00196B4u)
+
+/** Alias (User Manual Name) for CAN_MO53_DATAH.
+* To use register names with standard convension, please use CAN_MO53_DATAH.
+*/
+#define CAN_MODATAH53 (CAN_MO53_DATAH)
+
+/** \brief 16B0, Message Object Data Register Low */
+#define CAN_MO53_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00196B0u)
+
+/** Alias (User Manual Name) for CAN_MO53_DATAL.
+* To use register names with standard convension, please use CAN_MO53_DATAL.
+*/
+#define CAN_MODATAL53 (CAN_MO53_DATAL)
+
+/** \brief 16A0, Message Object Function Control Register */
+#define CAN_MO53_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00196A0u)
+
+/** Alias (User Manual Name) for CAN_MO53_EDATA0.
+* To use register names with standard convension, please use CAN_MO53_EDATA0.
+*/
+#define CAN_EMO53DATA0 (CAN_MO53_EDATA0)
+
+/** \brief 16A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO53_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00196A4u)
+
+/** Alias (User Manual Name) for CAN_MO53_EDATA1.
+* To use register names with standard convension, please use CAN_MO53_EDATA1.
+*/
+#define CAN_EMO53DATA1 (CAN_MO53_EDATA1)
+
+/** \brief 16A8, Message Object Interrupt Pointer Register */
+#define CAN_MO53_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00196A8u)
+
+/** Alias (User Manual Name) for CAN_MO53_EDATA2.
+* To use register names with standard convension, please use CAN_MO53_EDATA2.
+*/
+#define CAN_EMO53DATA2 (CAN_MO53_EDATA2)
+
+/** \brief 16AC, Message Object Acceptance Mask Register */
+#define CAN_MO53_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00196ACu)
+
+/** Alias (User Manual Name) for CAN_MO53_EDATA3.
+* To use register names with standard convension, please use CAN_MO53_EDATA3.
+*/
+#define CAN_EMO53DATA3 (CAN_MO53_EDATA3)
+
+/** \brief 16B0, Message Object Data Register Low */
+#define CAN_MO53_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00196B0u)
+
+/** Alias (User Manual Name) for CAN_MO53_EDATA4.
+* To use register names with standard convension, please use CAN_MO53_EDATA4.
+*/
+#define CAN_EMO53DATA4 (CAN_MO53_EDATA4)
+
+/** \brief 16B4, Message Object Data Register High */
+#define CAN_MO53_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00196B4u)
+
+/** Alias (User Manual Name) for CAN_MO53_EDATA5.
+* To use register names with standard convension, please use CAN_MO53_EDATA5.
+*/
+#define CAN_EMO53DATA5 (CAN_MO53_EDATA5)
+
+/** \brief 16B8, Message Object Arbitration Register */
+#define CAN_MO53_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00196B8u)
+
+/** Alias (User Manual Name) for CAN_MO53_EDATA6.
+* To use register names with standard convension, please use CAN_MO53_EDATA6.
+*/
+#define CAN_EMO53DATA6 (CAN_MO53_EDATA6)
+
+/** \brief 16A0, Message Object Function Control Register */
+#define CAN_MO53_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00196A0u)
+
+/** Alias (User Manual Name) for CAN_MO53_FCR.
+* To use register names with standard convension, please use CAN_MO53_FCR.
+*/
+#define CAN_MOFCR53 (CAN_MO53_FCR)
+
+/** \brief 16A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO53_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00196A4u)
+
+/** Alias (User Manual Name) for CAN_MO53_FGPR.
+* To use register names with standard convension, please use CAN_MO53_FGPR.
+*/
+#define CAN_MOFGPR53 (CAN_MO53_FGPR)
+
+/** \brief 16A8, Message Object Interrupt Pointer Register */
+#define CAN_MO53_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00196A8u)
+
+/** Alias (User Manual Name) for CAN_MO53_IPR.
+* To use register names with standard convension, please use CAN_MO53_IPR.
+*/
+#define CAN_MOIPR53 (CAN_MO53_IPR)
+
+/** \brief 16BC, Message Object Control Register */
+#define CAN_MO53_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00196BCu)
+
+/** Alias (User Manual Name) for CAN_MO53_STAT.
+* To use register names with standard convension, please use CAN_MO53_STAT.
+*/
+#define CAN_MOSTAT53 (CAN_MO53_STAT)
+
+/** \brief 16CC, Message Object Acceptance Mask Register */
+#define CAN_MO54_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00196CCu)
+
+/** Alias (User Manual Name) for CAN_MO54_AMR.
+* To use register names with standard convension, please use CAN_MO54_AMR.
+*/
+#define CAN_MOAMR54 (CAN_MO54_AMR)
+
+/** \brief 16D8, Message Object Arbitration Register */
+#define CAN_MO54_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00196D8u)
+
+/** Alias (User Manual Name) for CAN_MO54_AR.
+* To use register names with standard convension, please use CAN_MO54_AR.
+*/
+#define CAN_MOAR54 (CAN_MO54_AR)
+
+/** \brief 16DC, Message Object Control Register */
+#define CAN_MO54_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00196DCu)
+
+/** Alias (User Manual Name) for CAN_MO54_CTR.
+* To use register names with standard convension, please use CAN_MO54_CTR.
+*/
+#define CAN_MOCTR54 (CAN_MO54_CTR)
+
+/** \brief 16D4, Message Object Data Register High */
+#define CAN_MO54_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00196D4u)
+
+/** Alias (User Manual Name) for CAN_MO54_DATAH.
+* To use register names with standard convension, please use CAN_MO54_DATAH.
+*/
+#define CAN_MODATAH54 (CAN_MO54_DATAH)
+
+/** \brief 16D0, Message Object Data Register Low */
+#define CAN_MO54_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00196D0u)
+
+/** Alias (User Manual Name) for CAN_MO54_DATAL.
+* To use register names with standard convension, please use CAN_MO54_DATAL.
+*/
+#define CAN_MODATAL54 (CAN_MO54_DATAL)
+
+/** \brief 16C0, Message Object Function Control Register */
+#define CAN_MO54_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00196C0u)
+
+/** Alias (User Manual Name) for CAN_MO54_EDATA0.
+* To use register names with standard convension, please use CAN_MO54_EDATA0.
+*/
+#define CAN_EMO54DATA0 (CAN_MO54_EDATA0)
+
+/** \brief 16C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO54_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00196C4u)
+
+/** Alias (User Manual Name) for CAN_MO54_EDATA1.
+* To use register names with standard convension, please use CAN_MO54_EDATA1.
+*/
+#define CAN_EMO54DATA1 (CAN_MO54_EDATA1)
+
+/** \brief 16C8, Message Object Interrupt Pointer Register */
+#define CAN_MO54_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00196C8u)
+
+/** Alias (User Manual Name) for CAN_MO54_EDATA2.
+* To use register names with standard convension, please use CAN_MO54_EDATA2.
+*/
+#define CAN_EMO54DATA2 (CAN_MO54_EDATA2)
+
+/** \brief 16CC, Message Object Acceptance Mask Register */
+#define CAN_MO54_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00196CCu)
+
+/** Alias (User Manual Name) for CAN_MO54_EDATA3.
+* To use register names with standard convension, please use CAN_MO54_EDATA3.
+*/
+#define CAN_EMO54DATA3 (CAN_MO54_EDATA3)
+
+/** \brief 16D0, Message Object Data Register Low */
+#define CAN_MO54_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00196D0u)
+
+/** Alias (User Manual Name) for CAN_MO54_EDATA4.
+* To use register names with standard convension, please use CAN_MO54_EDATA4.
+*/
+#define CAN_EMO54DATA4 (CAN_MO54_EDATA4)
+
+/** \brief 16D4, Message Object Data Register High */
+#define CAN_MO54_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00196D4u)
+
+/** Alias (User Manual Name) for CAN_MO54_EDATA5.
+* To use register names with standard convension, please use CAN_MO54_EDATA5.
+*/
+#define CAN_EMO54DATA5 (CAN_MO54_EDATA5)
+
+/** \brief 16D8, Message Object Arbitration Register */
+#define CAN_MO54_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00196D8u)
+
+/** Alias (User Manual Name) for CAN_MO54_EDATA6.
+* To use register names with standard convension, please use CAN_MO54_EDATA6.
+*/
+#define CAN_EMO54DATA6 (CAN_MO54_EDATA6)
+
+/** \brief 16C0, Message Object Function Control Register */
+#define CAN_MO54_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00196C0u)
+
+/** Alias (User Manual Name) for CAN_MO54_FCR.
+* To use register names with standard convension, please use CAN_MO54_FCR.
+*/
+#define CAN_MOFCR54 (CAN_MO54_FCR)
+
+/** \brief 16C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO54_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00196C4u)
+
+/** Alias (User Manual Name) for CAN_MO54_FGPR.
+* To use register names with standard convension, please use CAN_MO54_FGPR.
+*/
+#define CAN_MOFGPR54 (CAN_MO54_FGPR)
+
+/** \brief 16C8, Message Object Interrupt Pointer Register */
+#define CAN_MO54_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00196C8u)
+
+/** Alias (User Manual Name) for CAN_MO54_IPR.
+* To use register names with standard convension, please use CAN_MO54_IPR.
+*/
+#define CAN_MOIPR54 (CAN_MO54_IPR)
+
+/** \brief 16DC, Message Object Control Register */
+#define CAN_MO54_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00196DCu)
+
+/** Alias (User Manual Name) for CAN_MO54_STAT.
+* To use register names with standard convension, please use CAN_MO54_STAT.
+*/
+#define CAN_MOSTAT54 (CAN_MO54_STAT)
+
+/** \brief 16EC, Message Object Acceptance Mask Register */
+#define CAN_MO55_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00196ECu)
+
+/** Alias (User Manual Name) for CAN_MO55_AMR.
+* To use register names with standard convension, please use CAN_MO55_AMR.
+*/
+#define CAN_MOAMR55 (CAN_MO55_AMR)
+
+/** \brief 16F8, Message Object Arbitration Register */
+#define CAN_MO55_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00196F8u)
+
+/** Alias (User Manual Name) for CAN_MO55_AR.
+* To use register names with standard convension, please use CAN_MO55_AR.
+*/
+#define CAN_MOAR55 (CAN_MO55_AR)
+
+/** \brief 16FC, Message Object Control Register */
+#define CAN_MO55_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00196FCu)
+
+/** Alias (User Manual Name) for CAN_MO55_CTR.
+* To use register names with standard convension, please use CAN_MO55_CTR.
+*/
+#define CAN_MOCTR55 (CAN_MO55_CTR)
+
+/** \brief 16F4, Message Object Data Register High */
+#define CAN_MO55_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00196F4u)
+
+/** Alias (User Manual Name) for CAN_MO55_DATAH.
+* To use register names with standard convension, please use CAN_MO55_DATAH.
+*/
+#define CAN_MODATAH55 (CAN_MO55_DATAH)
+
+/** \brief 16F0, Message Object Data Register Low */
+#define CAN_MO55_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00196F0u)
+
+/** Alias (User Manual Name) for CAN_MO55_DATAL.
+* To use register names with standard convension, please use CAN_MO55_DATAL.
+*/
+#define CAN_MODATAL55 (CAN_MO55_DATAL)
+
+/** \brief 16E0, Message Object Function Control Register */
+#define CAN_MO55_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00196E0u)
+
+/** Alias (User Manual Name) for CAN_MO55_EDATA0.
+* To use register names with standard convension, please use CAN_MO55_EDATA0.
+*/
+#define CAN_EMO55DATA0 (CAN_MO55_EDATA0)
+
+/** \brief 16E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO55_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00196E4u)
+
+/** Alias (User Manual Name) for CAN_MO55_EDATA1.
+* To use register names with standard convension, please use CAN_MO55_EDATA1.
+*/
+#define CAN_EMO55DATA1 (CAN_MO55_EDATA1)
+
+/** \brief 16E8, Message Object Interrupt Pointer Register */
+#define CAN_MO55_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00196E8u)
+
+/** Alias (User Manual Name) for CAN_MO55_EDATA2.
+* To use register names with standard convension, please use CAN_MO55_EDATA2.
+*/
+#define CAN_EMO55DATA2 (CAN_MO55_EDATA2)
+
+/** \brief 16EC, Message Object Acceptance Mask Register */
+#define CAN_MO55_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00196ECu)
+
+/** Alias (User Manual Name) for CAN_MO55_EDATA3.
+* To use register names with standard convension, please use CAN_MO55_EDATA3.
+*/
+#define CAN_EMO55DATA3 (CAN_MO55_EDATA3)
+
+/** \brief 16F0, Message Object Data Register Low */
+#define CAN_MO55_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00196F0u)
+
+/** Alias (User Manual Name) for CAN_MO55_EDATA4.
+* To use register names with standard convension, please use CAN_MO55_EDATA4.
+*/
+#define CAN_EMO55DATA4 (CAN_MO55_EDATA4)
+
+/** \brief 16F4, Message Object Data Register High */
+#define CAN_MO55_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00196F4u)
+
+/** Alias (User Manual Name) for CAN_MO55_EDATA5.
+* To use register names with standard convension, please use CAN_MO55_EDATA5.
+*/
+#define CAN_EMO55DATA5 (CAN_MO55_EDATA5)
+
+/** \brief 16F8, Message Object Arbitration Register */
+#define CAN_MO55_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00196F8u)
+
+/** Alias (User Manual Name) for CAN_MO55_EDATA6.
+* To use register names with standard convension, please use CAN_MO55_EDATA6.
+*/
+#define CAN_EMO55DATA6 (CAN_MO55_EDATA6)
+
+/** \brief 16E0, Message Object Function Control Register */
+#define CAN_MO55_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00196E0u)
+
+/** Alias (User Manual Name) for CAN_MO55_FCR.
+* To use register names with standard convension, please use CAN_MO55_FCR.
+*/
+#define CAN_MOFCR55 (CAN_MO55_FCR)
+
+/** \brief 16E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO55_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00196E4u)
+
+/** Alias (User Manual Name) for CAN_MO55_FGPR.
+* To use register names with standard convension, please use CAN_MO55_FGPR.
+*/
+#define CAN_MOFGPR55 (CAN_MO55_FGPR)
+
+/** \brief 16E8, Message Object Interrupt Pointer Register */
+#define CAN_MO55_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00196E8u)
+
+/** Alias (User Manual Name) for CAN_MO55_IPR.
+* To use register names with standard convension, please use CAN_MO55_IPR.
+*/
+#define CAN_MOIPR55 (CAN_MO55_IPR)
+
+/** \brief 16FC, Message Object Control Register */
+#define CAN_MO55_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00196FCu)
+
+/** Alias (User Manual Name) for CAN_MO55_STAT.
+* To use register names with standard convension, please use CAN_MO55_STAT.
+*/
+#define CAN_MOSTAT55 (CAN_MO55_STAT)
+
+/** \brief 170C, Message Object Acceptance Mask Register */
+#define CAN_MO56_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001970Cu)
+
+/** Alias (User Manual Name) for CAN_MO56_AMR.
+* To use register names with standard convension, please use CAN_MO56_AMR.
+*/
+#define CAN_MOAMR56 (CAN_MO56_AMR)
+
+/** \brief 1718, Message Object Arbitration Register */
+#define CAN_MO56_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019718u)
+
+/** Alias (User Manual Name) for CAN_MO56_AR.
+* To use register names with standard convension, please use CAN_MO56_AR.
+*/
+#define CAN_MOAR56 (CAN_MO56_AR)
+
+/** \brief 171C, Message Object Control Register */
+#define CAN_MO56_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001971Cu)
+
+/** Alias (User Manual Name) for CAN_MO56_CTR.
+* To use register names with standard convension, please use CAN_MO56_CTR.
+*/
+#define CAN_MOCTR56 (CAN_MO56_CTR)
+
+/** \brief 1714, Message Object Data Register High */
+#define CAN_MO56_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019714u)
+
+/** Alias (User Manual Name) for CAN_MO56_DATAH.
+* To use register names with standard convension, please use CAN_MO56_DATAH.
+*/
+#define CAN_MODATAH56 (CAN_MO56_DATAH)
+
+/** \brief 1710, Message Object Data Register Low */
+#define CAN_MO56_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019710u)
+
+/** Alias (User Manual Name) for CAN_MO56_DATAL.
+* To use register names with standard convension, please use CAN_MO56_DATAL.
+*/
+#define CAN_MODATAL56 (CAN_MO56_DATAL)
+
+/** \brief 1700, Message Object Function Control Register */
+#define CAN_MO56_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019700u)
+
+/** Alias (User Manual Name) for CAN_MO56_EDATA0.
+* To use register names with standard convension, please use CAN_MO56_EDATA0.
+*/
+#define CAN_EMO56DATA0 (CAN_MO56_EDATA0)
+
+/** \brief 1704, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO56_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019704u)
+
+/** Alias (User Manual Name) for CAN_MO56_EDATA1.
+* To use register names with standard convension, please use CAN_MO56_EDATA1.
+*/
+#define CAN_EMO56DATA1 (CAN_MO56_EDATA1)
+
+/** \brief 1708, Message Object Interrupt Pointer Register */
+#define CAN_MO56_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019708u)
+
+/** Alias (User Manual Name) for CAN_MO56_EDATA2.
+* To use register names with standard convension, please use CAN_MO56_EDATA2.
+*/
+#define CAN_EMO56DATA2 (CAN_MO56_EDATA2)
+
+/** \brief 170C, Message Object Acceptance Mask Register */
+#define CAN_MO56_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001970Cu)
+
+/** Alias (User Manual Name) for CAN_MO56_EDATA3.
+* To use register names with standard convension, please use CAN_MO56_EDATA3.
+*/
+#define CAN_EMO56DATA3 (CAN_MO56_EDATA3)
+
+/** \brief 1710, Message Object Data Register Low */
+#define CAN_MO56_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019710u)
+
+/** Alias (User Manual Name) for CAN_MO56_EDATA4.
+* To use register names with standard convension, please use CAN_MO56_EDATA4.
+*/
+#define CAN_EMO56DATA4 (CAN_MO56_EDATA4)
+
+/** \brief 1714, Message Object Data Register High */
+#define CAN_MO56_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019714u)
+
+/** Alias (User Manual Name) for CAN_MO56_EDATA5.
+* To use register names with standard convension, please use CAN_MO56_EDATA5.
+*/
+#define CAN_EMO56DATA5 (CAN_MO56_EDATA5)
+
+/** \brief 1718, Message Object Arbitration Register */
+#define CAN_MO56_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019718u)
+
+/** Alias (User Manual Name) for CAN_MO56_EDATA6.
+* To use register names with standard convension, please use CAN_MO56_EDATA6.
+*/
+#define CAN_EMO56DATA6 (CAN_MO56_EDATA6)
+
+/** \brief 1700, Message Object Function Control Register */
+#define CAN_MO56_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019700u)
+
+/** Alias (User Manual Name) for CAN_MO56_FCR.
+* To use register names with standard convension, please use CAN_MO56_FCR.
+*/
+#define CAN_MOFCR56 (CAN_MO56_FCR)
+
+/** \brief 1704, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO56_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019704u)
+
+/** Alias (User Manual Name) for CAN_MO56_FGPR.
+* To use register names with standard convension, please use CAN_MO56_FGPR.
+*/
+#define CAN_MOFGPR56 (CAN_MO56_FGPR)
+
+/** \brief 1708, Message Object Interrupt Pointer Register */
+#define CAN_MO56_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019708u)
+
+/** Alias (User Manual Name) for CAN_MO56_IPR.
+* To use register names with standard convension, please use CAN_MO56_IPR.
+*/
+#define CAN_MOIPR56 (CAN_MO56_IPR)
+
+/** \brief 171C, Message Object Control Register */
+#define CAN_MO56_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001971Cu)
+
+/** Alias (User Manual Name) for CAN_MO56_STAT.
+* To use register names with standard convension, please use CAN_MO56_STAT.
+*/
+#define CAN_MOSTAT56 (CAN_MO56_STAT)
+
+/** \brief 172C, Message Object Acceptance Mask Register */
+#define CAN_MO57_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001972Cu)
+
+/** Alias (User Manual Name) for CAN_MO57_AMR.
+* To use register names with standard convension, please use CAN_MO57_AMR.
+*/
+#define CAN_MOAMR57 (CAN_MO57_AMR)
+
+/** \brief 1738, Message Object Arbitration Register */
+#define CAN_MO57_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019738u)
+
+/** Alias (User Manual Name) for CAN_MO57_AR.
+* To use register names with standard convension, please use CAN_MO57_AR.
+*/
+#define CAN_MOAR57 (CAN_MO57_AR)
+
+/** \brief 173C, Message Object Control Register */
+#define CAN_MO57_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001973Cu)
+
+/** Alias (User Manual Name) for CAN_MO57_CTR.
+* To use register names with standard convension, please use CAN_MO57_CTR.
+*/
+#define CAN_MOCTR57 (CAN_MO57_CTR)
+
+/** \brief 1734, Message Object Data Register High */
+#define CAN_MO57_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019734u)
+
+/** Alias (User Manual Name) for CAN_MO57_DATAH.
+* To use register names with standard convension, please use CAN_MO57_DATAH.
+*/
+#define CAN_MODATAH57 (CAN_MO57_DATAH)
+
+/** \brief 1730, Message Object Data Register Low */
+#define CAN_MO57_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019730u)
+
+/** Alias (User Manual Name) for CAN_MO57_DATAL.
+* To use register names with standard convension, please use CAN_MO57_DATAL.
+*/
+#define CAN_MODATAL57 (CAN_MO57_DATAL)
+
+/** \brief 1720, Message Object Function Control Register */
+#define CAN_MO57_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019720u)
+
+/** Alias (User Manual Name) for CAN_MO57_EDATA0.
+* To use register names with standard convension, please use CAN_MO57_EDATA0.
+*/
+#define CAN_EMO57DATA0 (CAN_MO57_EDATA0)
+
+/** \brief 1724, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO57_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019724u)
+
+/** Alias (User Manual Name) for CAN_MO57_EDATA1.
+* To use register names with standard convension, please use CAN_MO57_EDATA1.
+*/
+#define CAN_EMO57DATA1 (CAN_MO57_EDATA1)
+
+/** \brief 1728, Message Object Interrupt Pointer Register */
+#define CAN_MO57_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019728u)
+
+/** Alias (User Manual Name) for CAN_MO57_EDATA2.
+* To use register names with standard convension, please use CAN_MO57_EDATA2.
+*/
+#define CAN_EMO57DATA2 (CAN_MO57_EDATA2)
+
+/** \brief 172C, Message Object Acceptance Mask Register */
+#define CAN_MO57_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001972Cu)
+
+/** Alias (User Manual Name) for CAN_MO57_EDATA3.
+* To use register names with standard convension, please use CAN_MO57_EDATA3.
+*/
+#define CAN_EMO57DATA3 (CAN_MO57_EDATA3)
+
+/** \brief 1730, Message Object Data Register Low */
+#define CAN_MO57_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019730u)
+
+/** Alias (User Manual Name) for CAN_MO57_EDATA4.
+* To use register names with standard convension, please use CAN_MO57_EDATA4.
+*/
+#define CAN_EMO57DATA4 (CAN_MO57_EDATA4)
+
+/** \brief 1734, Message Object Data Register High */
+#define CAN_MO57_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019734u)
+
+/** Alias (User Manual Name) for CAN_MO57_EDATA5.
+* To use register names with standard convension, please use CAN_MO57_EDATA5.
+*/
+#define CAN_EMO57DATA5 (CAN_MO57_EDATA5)
+
+/** \brief 1738, Message Object Arbitration Register */
+#define CAN_MO57_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019738u)
+
+/** Alias (User Manual Name) for CAN_MO57_EDATA6.
+* To use register names with standard convension, please use CAN_MO57_EDATA6.
+*/
+#define CAN_EMO57DATA6 (CAN_MO57_EDATA6)
+
+/** \brief 1720, Message Object Function Control Register */
+#define CAN_MO57_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019720u)
+
+/** Alias (User Manual Name) for CAN_MO57_FCR.
+* To use register names with standard convension, please use CAN_MO57_FCR.
+*/
+#define CAN_MOFCR57 (CAN_MO57_FCR)
+
+/** \brief 1724, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO57_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019724u)
+
+/** Alias (User Manual Name) for CAN_MO57_FGPR.
+* To use register names with standard convension, please use CAN_MO57_FGPR.
+*/
+#define CAN_MOFGPR57 (CAN_MO57_FGPR)
+
+/** \brief 1728, Message Object Interrupt Pointer Register */
+#define CAN_MO57_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019728u)
+
+/** Alias (User Manual Name) for CAN_MO57_IPR.
+* To use register names with standard convension, please use CAN_MO57_IPR.
+*/
+#define CAN_MOIPR57 (CAN_MO57_IPR)
+
+/** \brief 173C, Message Object Control Register */
+#define CAN_MO57_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001973Cu)
+
+/** Alias (User Manual Name) for CAN_MO57_STAT.
+* To use register names with standard convension, please use CAN_MO57_STAT.
+*/
+#define CAN_MOSTAT57 (CAN_MO57_STAT)
+
+/** \brief 174C, Message Object Acceptance Mask Register */
+#define CAN_MO58_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001974Cu)
+
+/** Alias (User Manual Name) for CAN_MO58_AMR.
+* To use register names with standard convension, please use CAN_MO58_AMR.
+*/
+#define CAN_MOAMR58 (CAN_MO58_AMR)
+
+/** \brief 1758, Message Object Arbitration Register */
+#define CAN_MO58_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019758u)
+
+/** Alias (User Manual Name) for CAN_MO58_AR.
+* To use register names with standard convension, please use CAN_MO58_AR.
+*/
+#define CAN_MOAR58 (CAN_MO58_AR)
+
+/** \brief 175C, Message Object Control Register */
+#define CAN_MO58_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001975Cu)
+
+/** Alias (User Manual Name) for CAN_MO58_CTR.
+* To use register names with standard convension, please use CAN_MO58_CTR.
+*/
+#define CAN_MOCTR58 (CAN_MO58_CTR)
+
+/** \brief 1754, Message Object Data Register High */
+#define CAN_MO58_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019754u)
+
+/** Alias (User Manual Name) for CAN_MO58_DATAH.
+* To use register names with standard convension, please use CAN_MO58_DATAH.
+*/
+#define CAN_MODATAH58 (CAN_MO58_DATAH)
+
+/** \brief 1750, Message Object Data Register Low */
+#define CAN_MO58_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019750u)
+
+/** Alias (User Manual Name) for CAN_MO58_DATAL.
+* To use register names with standard convension, please use CAN_MO58_DATAL.
+*/
+#define CAN_MODATAL58 (CAN_MO58_DATAL)
+
+/** \brief 1740, Message Object Function Control Register */
+#define CAN_MO58_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019740u)
+
+/** Alias (User Manual Name) for CAN_MO58_EDATA0.
+* To use register names with standard convension, please use CAN_MO58_EDATA0.
+*/
+#define CAN_EMO58DATA0 (CAN_MO58_EDATA0)
+
+/** \brief 1744, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO58_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019744u)
+
+/** Alias (User Manual Name) for CAN_MO58_EDATA1.
+* To use register names with standard convension, please use CAN_MO58_EDATA1.
+*/
+#define CAN_EMO58DATA1 (CAN_MO58_EDATA1)
+
+/** \brief 1748, Message Object Interrupt Pointer Register */
+#define CAN_MO58_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019748u)
+
+/** Alias (User Manual Name) for CAN_MO58_EDATA2.
+* To use register names with standard convension, please use CAN_MO58_EDATA2.
+*/
+#define CAN_EMO58DATA2 (CAN_MO58_EDATA2)
+
+/** \brief 174C, Message Object Acceptance Mask Register */
+#define CAN_MO58_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001974Cu)
+
+/** Alias (User Manual Name) for CAN_MO58_EDATA3.
+* To use register names with standard convension, please use CAN_MO58_EDATA3.
+*/
+#define CAN_EMO58DATA3 (CAN_MO58_EDATA3)
+
+/** \brief 1750, Message Object Data Register Low */
+#define CAN_MO58_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019750u)
+
+/** Alias (User Manual Name) for CAN_MO58_EDATA4.
+* To use register names with standard convension, please use CAN_MO58_EDATA4.
+*/
+#define CAN_EMO58DATA4 (CAN_MO58_EDATA4)
+
+/** \brief 1754, Message Object Data Register High */
+#define CAN_MO58_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019754u)
+
+/** Alias (User Manual Name) for CAN_MO58_EDATA5.
+* To use register names with standard convension, please use CAN_MO58_EDATA5.
+*/
+#define CAN_EMO58DATA5 (CAN_MO58_EDATA5)
+
+/** \brief 1758, Message Object Arbitration Register */
+#define CAN_MO58_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019758u)
+
+/** Alias (User Manual Name) for CAN_MO58_EDATA6.
+* To use register names with standard convension, please use CAN_MO58_EDATA6.
+*/
+#define CAN_EMO58DATA6 (CAN_MO58_EDATA6)
+
+/** \brief 1740, Message Object Function Control Register */
+#define CAN_MO58_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019740u)
+
+/** Alias (User Manual Name) for CAN_MO58_FCR.
+* To use register names with standard convension, please use CAN_MO58_FCR.
+*/
+#define CAN_MOFCR58 (CAN_MO58_FCR)
+
+/** \brief 1744, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO58_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019744u)
+
+/** Alias (User Manual Name) for CAN_MO58_FGPR.
+* To use register names with standard convension, please use CAN_MO58_FGPR.
+*/
+#define CAN_MOFGPR58 (CAN_MO58_FGPR)
+
+/** \brief 1748, Message Object Interrupt Pointer Register */
+#define CAN_MO58_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019748u)
+
+/** Alias (User Manual Name) for CAN_MO58_IPR.
+* To use register names with standard convension, please use CAN_MO58_IPR.
+*/
+#define CAN_MOIPR58 (CAN_MO58_IPR)
+
+/** \brief 175C, Message Object Control Register */
+#define CAN_MO58_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001975Cu)
+
+/** Alias (User Manual Name) for CAN_MO58_STAT.
+* To use register names with standard convension, please use CAN_MO58_STAT.
+*/
+#define CAN_MOSTAT58 (CAN_MO58_STAT)
+
+/** \brief 176C, Message Object Acceptance Mask Register */
+#define CAN_MO59_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001976Cu)
+
+/** Alias (User Manual Name) for CAN_MO59_AMR.
+* To use register names with standard convension, please use CAN_MO59_AMR.
+*/
+#define CAN_MOAMR59 (CAN_MO59_AMR)
+
+/** \brief 1778, Message Object Arbitration Register */
+#define CAN_MO59_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019778u)
+
+/** Alias (User Manual Name) for CAN_MO59_AR.
+* To use register names with standard convension, please use CAN_MO59_AR.
+*/
+#define CAN_MOAR59 (CAN_MO59_AR)
+
+/** \brief 177C, Message Object Control Register */
+#define CAN_MO59_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001977Cu)
+
+/** Alias (User Manual Name) for CAN_MO59_CTR.
+* To use register names with standard convension, please use CAN_MO59_CTR.
+*/
+#define CAN_MOCTR59 (CAN_MO59_CTR)
+
+/** \brief 1774, Message Object Data Register High */
+#define CAN_MO59_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019774u)
+
+/** Alias (User Manual Name) for CAN_MO59_DATAH.
+* To use register names with standard convension, please use CAN_MO59_DATAH.
+*/
+#define CAN_MODATAH59 (CAN_MO59_DATAH)
+
+/** \brief 1770, Message Object Data Register Low */
+#define CAN_MO59_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019770u)
+
+/** Alias (User Manual Name) for CAN_MO59_DATAL.
+* To use register names with standard convension, please use CAN_MO59_DATAL.
+*/
+#define CAN_MODATAL59 (CAN_MO59_DATAL)
+
+/** \brief 1760, Message Object Function Control Register */
+#define CAN_MO59_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019760u)
+
+/** Alias (User Manual Name) for CAN_MO59_EDATA0.
+* To use register names with standard convension, please use CAN_MO59_EDATA0.
+*/
+#define CAN_EMO59DATA0 (CAN_MO59_EDATA0)
+
+/** \brief 1764, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO59_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019764u)
+
+/** Alias (User Manual Name) for CAN_MO59_EDATA1.
+* To use register names with standard convension, please use CAN_MO59_EDATA1.
+*/
+#define CAN_EMO59DATA1 (CAN_MO59_EDATA1)
+
+/** \brief 1768, Message Object Interrupt Pointer Register */
+#define CAN_MO59_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019768u)
+
+/** Alias (User Manual Name) for CAN_MO59_EDATA2.
+* To use register names with standard convension, please use CAN_MO59_EDATA2.
+*/
+#define CAN_EMO59DATA2 (CAN_MO59_EDATA2)
+
+/** \brief 176C, Message Object Acceptance Mask Register */
+#define CAN_MO59_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001976Cu)
+
+/** Alias (User Manual Name) for CAN_MO59_EDATA3.
+* To use register names with standard convension, please use CAN_MO59_EDATA3.
+*/
+#define CAN_EMO59DATA3 (CAN_MO59_EDATA3)
+
+/** \brief 1770, Message Object Data Register Low */
+#define CAN_MO59_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019770u)
+
+/** Alias (User Manual Name) for CAN_MO59_EDATA4.
+* To use register names with standard convension, please use CAN_MO59_EDATA4.
+*/
+#define CAN_EMO59DATA4 (CAN_MO59_EDATA4)
+
+/** \brief 1774, Message Object Data Register High */
+#define CAN_MO59_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019774u)
+
+/** Alias (User Manual Name) for CAN_MO59_EDATA5.
+* To use register names with standard convension, please use CAN_MO59_EDATA5.
+*/
+#define CAN_EMO59DATA5 (CAN_MO59_EDATA5)
+
+/** \brief 1778, Message Object Arbitration Register */
+#define CAN_MO59_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019778u)
+
+/** Alias (User Manual Name) for CAN_MO59_EDATA6.
+* To use register names with standard convension, please use CAN_MO59_EDATA6.
+*/
+#define CAN_EMO59DATA6 (CAN_MO59_EDATA6)
+
+/** \brief 1760, Message Object Function Control Register */
+#define CAN_MO59_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019760u)
+
+/** Alias (User Manual Name) for CAN_MO59_FCR.
+* To use register names with standard convension, please use CAN_MO59_FCR.
+*/
+#define CAN_MOFCR59 (CAN_MO59_FCR)
+
+/** \brief 1764, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO59_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019764u)
+
+/** Alias (User Manual Name) for CAN_MO59_FGPR.
+* To use register names with standard convension, please use CAN_MO59_FGPR.
+*/
+#define CAN_MOFGPR59 (CAN_MO59_FGPR)
+
+/** \brief 1768, Message Object Interrupt Pointer Register */
+#define CAN_MO59_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019768u)
+
+/** Alias (User Manual Name) for CAN_MO59_IPR.
+* To use register names with standard convension, please use CAN_MO59_IPR.
+*/
+#define CAN_MOIPR59 (CAN_MO59_IPR)
+
+/** \brief 177C, Message Object Control Register */
+#define CAN_MO59_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001977Cu)
+
+/** Alias (User Manual Name) for CAN_MO59_STAT.
+* To use register names with standard convension, please use CAN_MO59_STAT.
+*/
+#define CAN_MOSTAT59 (CAN_MO59_STAT)
+
+/** \brief 10AC, Message Object Acceptance Mask Register */
+#define CAN_MO5_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00190ACu)
+
+/** Alias (User Manual Name) for CAN_MO5_AMR.
+* To use register names with standard convension, please use CAN_MO5_AMR.
+*/
+#define CAN_MOAMR5 (CAN_MO5_AMR)
+
+/** \brief 10B8, Message Object Arbitration Register */
+#define CAN_MO5_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00190B8u)
+
+/** Alias (User Manual Name) for CAN_MO5_AR.
+* To use register names with standard convension, please use CAN_MO5_AR.
+*/
+#define CAN_MOAR5 (CAN_MO5_AR)
+
+/** \brief 10BC, Message Object Control Register */
+#define CAN_MO5_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00190BCu)
+
+/** Alias (User Manual Name) for CAN_MO5_CTR.
+* To use register names with standard convension, please use CAN_MO5_CTR.
+*/
+#define CAN_MOCTR5 (CAN_MO5_CTR)
+
+/** \brief 10B4, Message Object Data Register High */
+#define CAN_MO5_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00190B4u)
+
+/** Alias (User Manual Name) for CAN_MO5_DATAH.
+* To use register names with standard convension, please use CAN_MO5_DATAH.
+*/
+#define CAN_MODATAH5 (CAN_MO5_DATAH)
+
+/** \brief 10B0, Message Object Data Register Low */
+#define CAN_MO5_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00190B0u)
+
+/** Alias (User Manual Name) for CAN_MO5_DATAL.
+* To use register names with standard convension, please use CAN_MO5_DATAL.
+*/
+#define CAN_MODATAL5 (CAN_MO5_DATAL)
+
+/** \brief 10A0, Message Object Function Control Register */
+#define CAN_MO5_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00190A0u)
+
+/** Alias (User Manual Name) for CAN_MO5_EDATA0.
+* To use register names with standard convension, please use CAN_MO5_EDATA0.
+*/
+#define CAN_EMO5DATA0 (CAN_MO5_EDATA0)
+
+/** \brief 10A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO5_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00190A4u)
+
+/** Alias (User Manual Name) for CAN_MO5_EDATA1.
+* To use register names with standard convension, please use CAN_MO5_EDATA1.
+*/
+#define CAN_EMO5DATA1 (CAN_MO5_EDATA1)
+
+/** \brief 10A8, Message Object Interrupt Pointer Register */
+#define CAN_MO5_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00190A8u)
+
+/** Alias (User Manual Name) for CAN_MO5_EDATA2.
+* To use register names with standard convension, please use CAN_MO5_EDATA2.
+*/
+#define CAN_EMO5DATA2 (CAN_MO5_EDATA2)
+
+/** \brief 10AC, Message Object Acceptance Mask Register */
+#define CAN_MO5_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00190ACu)
+
+/** Alias (User Manual Name) for CAN_MO5_EDATA3.
+* To use register names with standard convension, please use CAN_MO5_EDATA3.
+*/
+#define CAN_EMO5DATA3 (CAN_MO5_EDATA3)
+
+/** \brief 10B0, Message Object Data Register Low */
+#define CAN_MO5_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00190B0u)
+
+/** Alias (User Manual Name) for CAN_MO5_EDATA4.
+* To use register names with standard convension, please use CAN_MO5_EDATA4.
+*/
+#define CAN_EMO5DATA4 (CAN_MO5_EDATA4)
+
+/** \brief 10B4, Message Object Data Register High */
+#define CAN_MO5_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00190B4u)
+
+/** Alias (User Manual Name) for CAN_MO5_EDATA5.
+* To use register names with standard convension, please use CAN_MO5_EDATA5.
+*/
+#define CAN_EMO5DATA5 (CAN_MO5_EDATA5)
+
+/** \brief 10B8, Message Object Arbitration Register */
+#define CAN_MO5_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00190B8u)
+
+/** Alias (User Manual Name) for CAN_MO5_EDATA6.
+* To use register names with standard convension, please use CAN_MO5_EDATA6.
+*/
+#define CAN_EMO5DATA6 (CAN_MO5_EDATA6)
+
+/** \brief 10A0, Message Object Function Control Register */
+#define CAN_MO5_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00190A0u)
+
+/** Alias (User Manual Name) for CAN_MO5_FCR.
+* To use register names with standard convension, please use CAN_MO5_FCR.
+*/
+#define CAN_MOFCR5 (CAN_MO5_FCR)
+
+/** \brief 10A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO5_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00190A4u)
+
+/** Alias (User Manual Name) for CAN_MO5_FGPR.
+* To use register names with standard convension, please use CAN_MO5_FGPR.
+*/
+#define CAN_MOFGPR5 (CAN_MO5_FGPR)
+
+/** \brief 10A8, Message Object Interrupt Pointer Register */
+#define CAN_MO5_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00190A8u)
+
+/** Alias (User Manual Name) for CAN_MO5_IPR.
+* To use register names with standard convension, please use CAN_MO5_IPR.
+*/
+#define CAN_MOIPR5 (CAN_MO5_IPR)
+
+/** \brief 10BC, Message Object Control Register */
+#define CAN_MO5_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00190BCu)
+
+/** Alias (User Manual Name) for CAN_MO5_STAT.
+* To use register names with standard convension, please use CAN_MO5_STAT.
+*/
+#define CAN_MOSTAT5 (CAN_MO5_STAT)
+
+/** \brief 178C, Message Object Acceptance Mask Register */
+#define CAN_MO60_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001978Cu)
+
+/** Alias (User Manual Name) for CAN_MO60_AMR.
+* To use register names with standard convension, please use CAN_MO60_AMR.
+*/
+#define CAN_MOAMR60 (CAN_MO60_AMR)
+
+/** \brief 1798, Message Object Arbitration Register */
+#define CAN_MO60_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019798u)
+
+/** Alias (User Manual Name) for CAN_MO60_AR.
+* To use register names with standard convension, please use CAN_MO60_AR.
+*/
+#define CAN_MOAR60 (CAN_MO60_AR)
+
+/** \brief 179C, Message Object Control Register */
+#define CAN_MO60_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001979Cu)
+
+/** Alias (User Manual Name) for CAN_MO60_CTR.
+* To use register names with standard convension, please use CAN_MO60_CTR.
+*/
+#define CAN_MOCTR60 (CAN_MO60_CTR)
+
+/** \brief 1794, Message Object Data Register High */
+#define CAN_MO60_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019794u)
+
+/** Alias (User Manual Name) for CAN_MO60_DATAH.
+* To use register names with standard convension, please use CAN_MO60_DATAH.
+*/
+#define CAN_MODATAH60 (CAN_MO60_DATAH)
+
+/** \brief 1790, Message Object Data Register Low */
+#define CAN_MO60_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019790u)
+
+/** Alias (User Manual Name) for CAN_MO60_DATAL.
+* To use register names with standard convension, please use CAN_MO60_DATAL.
+*/
+#define CAN_MODATAL60 (CAN_MO60_DATAL)
+
+/** \brief 1780, Message Object Function Control Register */
+#define CAN_MO60_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019780u)
+
+/** Alias (User Manual Name) for CAN_MO60_EDATA0.
+* To use register names with standard convension, please use CAN_MO60_EDATA0.
+*/
+#define CAN_EMO60DATA0 (CAN_MO60_EDATA0)
+
+/** \brief 1784, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO60_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019784u)
+
+/** Alias (User Manual Name) for CAN_MO60_EDATA1.
+* To use register names with standard convension, please use CAN_MO60_EDATA1.
+*/
+#define CAN_EMO60DATA1 (CAN_MO60_EDATA1)
+
+/** \brief 1788, Message Object Interrupt Pointer Register */
+#define CAN_MO60_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019788u)
+
+/** Alias (User Manual Name) for CAN_MO60_EDATA2.
+* To use register names with standard convension, please use CAN_MO60_EDATA2.
+*/
+#define CAN_EMO60DATA2 (CAN_MO60_EDATA2)
+
+/** \brief 178C, Message Object Acceptance Mask Register */
+#define CAN_MO60_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001978Cu)
+
+/** Alias (User Manual Name) for CAN_MO60_EDATA3.
+* To use register names with standard convension, please use CAN_MO60_EDATA3.
+*/
+#define CAN_EMO60DATA3 (CAN_MO60_EDATA3)
+
+/** \brief 1790, Message Object Data Register Low */
+#define CAN_MO60_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019790u)
+
+/** Alias (User Manual Name) for CAN_MO60_EDATA4.
+* To use register names with standard convension, please use CAN_MO60_EDATA4.
+*/
+#define CAN_EMO60DATA4 (CAN_MO60_EDATA4)
+
+/** \brief 1794, Message Object Data Register High */
+#define CAN_MO60_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019794u)
+
+/** Alias (User Manual Name) for CAN_MO60_EDATA5.
+* To use register names with standard convension, please use CAN_MO60_EDATA5.
+*/
+#define CAN_EMO60DATA5 (CAN_MO60_EDATA5)
+
+/** \brief 1798, Message Object Arbitration Register */
+#define CAN_MO60_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019798u)
+
+/** Alias (User Manual Name) for CAN_MO60_EDATA6.
+* To use register names with standard convension, please use CAN_MO60_EDATA6.
+*/
+#define CAN_EMO60DATA6 (CAN_MO60_EDATA6)
+
+/** \brief 1780, Message Object Function Control Register */
+#define CAN_MO60_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019780u)
+
+/** Alias (User Manual Name) for CAN_MO60_FCR.
+* To use register names with standard convension, please use CAN_MO60_FCR.
+*/
+#define CAN_MOFCR60 (CAN_MO60_FCR)
+
+/** \brief 1784, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO60_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019784u)
+
+/** Alias (User Manual Name) for CAN_MO60_FGPR.
+* To use register names with standard convension, please use CAN_MO60_FGPR.
+*/
+#define CAN_MOFGPR60 (CAN_MO60_FGPR)
+
+/** \brief 1788, Message Object Interrupt Pointer Register */
+#define CAN_MO60_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019788u)
+
+/** Alias (User Manual Name) for CAN_MO60_IPR.
+* To use register names with standard convension, please use CAN_MO60_IPR.
+*/
+#define CAN_MOIPR60 (CAN_MO60_IPR)
+
+/** \brief 179C, Message Object Control Register */
+#define CAN_MO60_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001979Cu)
+
+/** Alias (User Manual Name) for CAN_MO60_STAT.
+* To use register names with standard convension, please use CAN_MO60_STAT.
+*/
+#define CAN_MOSTAT60 (CAN_MO60_STAT)
+
+/** \brief 17AC, Message Object Acceptance Mask Register */
+#define CAN_MO61_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00197ACu)
+
+/** Alias (User Manual Name) for CAN_MO61_AMR.
+* To use register names with standard convension, please use CAN_MO61_AMR.
+*/
+#define CAN_MOAMR61 (CAN_MO61_AMR)
+
+/** \brief 17B8, Message Object Arbitration Register */
+#define CAN_MO61_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00197B8u)
+
+/** Alias (User Manual Name) for CAN_MO61_AR.
+* To use register names with standard convension, please use CAN_MO61_AR.
+*/
+#define CAN_MOAR61 (CAN_MO61_AR)
+
+/** \brief 17BC, Message Object Control Register */
+#define CAN_MO61_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00197BCu)
+
+/** Alias (User Manual Name) for CAN_MO61_CTR.
+* To use register names with standard convension, please use CAN_MO61_CTR.
+*/
+#define CAN_MOCTR61 (CAN_MO61_CTR)
+
+/** \brief 17B4, Message Object Data Register High */
+#define CAN_MO61_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00197B4u)
+
+/** Alias (User Manual Name) for CAN_MO61_DATAH.
+* To use register names with standard convension, please use CAN_MO61_DATAH.
+*/
+#define CAN_MODATAH61 (CAN_MO61_DATAH)
+
+/** \brief 17B0, Message Object Data Register Low */
+#define CAN_MO61_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00197B0u)
+
+/** Alias (User Manual Name) for CAN_MO61_DATAL.
+* To use register names with standard convension, please use CAN_MO61_DATAL.
+*/
+#define CAN_MODATAL61 (CAN_MO61_DATAL)
+
+/** \brief 17A0, Message Object Function Control Register */
+#define CAN_MO61_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00197A0u)
+
+/** Alias (User Manual Name) for CAN_MO61_EDATA0.
+* To use register names with standard convension, please use CAN_MO61_EDATA0.
+*/
+#define CAN_EMO61DATA0 (CAN_MO61_EDATA0)
+
+/** \brief 17A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO61_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00197A4u)
+
+/** Alias (User Manual Name) for CAN_MO61_EDATA1.
+* To use register names with standard convension, please use CAN_MO61_EDATA1.
+*/
+#define CAN_EMO61DATA1 (CAN_MO61_EDATA1)
+
+/** \brief 17A8, Message Object Interrupt Pointer Register */
+#define CAN_MO61_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00197A8u)
+
+/** Alias (User Manual Name) for CAN_MO61_EDATA2.
+* To use register names with standard convension, please use CAN_MO61_EDATA2.
+*/
+#define CAN_EMO61DATA2 (CAN_MO61_EDATA2)
+
+/** \brief 17AC, Message Object Acceptance Mask Register */
+#define CAN_MO61_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00197ACu)
+
+/** Alias (User Manual Name) for CAN_MO61_EDATA3.
+* To use register names with standard convension, please use CAN_MO61_EDATA3.
+*/
+#define CAN_EMO61DATA3 (CAN_MO61_EDATA3)
+
+/** \brief 17B0, Message Object Data Register Low */
+#define CAN_MO61_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00197B0u)
+
+/** Alias (User Manual Name) for CAN_MO61_EDATA4.
+* To use register names with standard convension, please use CAN_MO61_EDATA4.
+*/
+#define CAN_EMO61DATA4 (CAN_MO61_EDATA4)
+
+/** \brief 17B4, Message Object Data Register High */
+#define CAN_MO61_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00197B4u)
+
+/** Alias (User Manual Name) for CAN_MO61_EDATA5.
+* To use register names with standard convension, please use CAN_MO61_EDATA5.
+*/
+#define CAN_EMO61DATA5 (CAN_MO61_EDATA5)
+
+/** \brief 17B8, Message Object Arbitration Register */
+#define CAN_MO61_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00197B8u)
+
+/** Alias (User Manual Name) for CAN_MO61_EDATA6.
+* To use register names with standard convension, please use CAN_MO61_EDATA6.
+*/
+#define CAN_EMO61DATA6 (CAN_MO61_EDATA6)
+
+/** \brief 17A0, Message Object Function Control Register */
+#define CAN_MO61_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00197A0u)
+
+/** Alias (User Manual Name) for CAN_MO61_FCR.
+* To use register names with standard convension, please use CAN_MO61_FCR.
+*/
+#define CAN_MOFCR61 (CAN_MO61_FCR)
+
+/** \brief 17A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO61_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00197A4u)
+
+/** Alias (User Manual Name) for CAN_MO61_FGPR.
+* To use register names with standard convension, please use CAN_MO61_FGPR.
+*/
+#define CAN_MOFGPR61 (CAN_MO61_FGPR)
+
+/** \brief 17A8, Message Object Interrupt Pointer Register */
+#define CAN_MO61_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00197A8u)
+
+/** Alias (User Manual Name) for CAN_MO61_IPR.
+* To use register names with standard convension, please use CAN_MO61_IPR.
+*/
+#define CAN_MOIPR61 (CAN_MO61_IPR)
+
+/** \brief 17BC, Message Object Control Register */
+#define CAN_MO61_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00197BCu)
+
+/** Alias (User Manual Name) for CAN_MO61_STAT.
+* To use register names with standard convension, please use CAN_MO61_STAT.
+*/
+#define CAN_MOSTAT61 (CAN_MO61_STAT)
+
+/** \brief 17CC, Message Object Acceptance Mask Register */
+#define CAN_MO62_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00197CCu)
+
+/** Alias (User Manual Name) for CAN_MO62_AMR.
+* To use register names with standard convension, please use CAN_MO62_AMR.
+*/
+#define CAN_MOAMR62 (CAN_MO62_AMR)
+
+/** \brief 17D8, Message Object Arbitration Register */
+#define CAN_MO62_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00197D8u)
+
+/** Alias (User Manual Name) for CAN_MO62_AR.
+* To use register names with standard convension, please use CAN_MO62_AR.
+*/
+#define CAN_MOAR62 (CAN_MO62_AR)
+
+/** \brief 17DC, Message Object Control Register */
+#define CAN_MO62_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00197DCu)
+
+/** Alias (User Manual Name) for CAN_MO62_CTR.
+* To use register names with standard convension, please use CAN_MO62_CTR.
+*/
+#define CAN_MOCTR62 (CAN_MO62_CTR)
+
+/** \brief 17D4, Message Object Data Register High */
+#define CAN_MO62_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00197D4u)
+
+/** Alias (User Manual Name) for CAN_MO62_DATAH.
+* To use register names with standard convension, please use CAN_MO62_DATAH.
+*/
+#define CAN_MODATAH62 (CAN_MO62_DATAH)
+
+/** \brief 17D0, Message Object Data Register Low */
+#define CAN_MO62_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00197D0u)
+
+/** Alias (User Manual Name) for CAN_MO62_DATAL.
+* To use register names with standard convension, please use CAN_MO62_DATAL.
+*/
+#define CAN_MODATAL62 (CAN_MO62_DATAL)
+
+/** \brief 17C0, Message Object Function Control Register */
+#define CAN_MO62_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00197C0u)
+
+/** Alias (User Manual Name) for CAN_MO62_EDATA0.
+* To use register names with standard convension, please use CAN_MO62_EDATA0.
+*/
+#define CAN_EMO62DATA0 (CAN_MO62_EDATA0)
+
+/** \brief 17C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO62_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00197C4u)
+
+/** Alias (User Manual Name) for CAN_MO62_EDATA1.
+* To use register names with standard convension, please use CAN_MO62_EDATA1.
+*/
+#define CAN_EMO62DATA1 (CAN_MO62_EDATA1)
+
+/** \brief 17C8, Message Object Interrupt Pointer Register */
+#define CAN_MO62_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00197C8u)
+
+/** Alias (User Manual Name) for CAN_MO62_EDATA2.
+* To use register names with standard convension, please use CAN_MO62_EDATA2.
+*/
+#define CAN_EMO62DATA2 (CAN_MO62_EDATA2)
+
+/** \brief 17CC, Message Object Acceptance Mask Register */
+#define CAN_MO62_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00197CCu)
+
+/** Alias (User Manual Name) for CAN_MO62_EDATA3.
+* To use register names with standard convension, please use CAN_MO62_EDATA3.
+*/
+#define CAN_EMO62DATA3 (CAN_MO62_EDATA3)
+
+/** \brief 17D0, Message Object Data Register Low */
+#define CAN_MO62_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00197D0u)
+
+/** Alias (User Manual Name) for CAN_MO62_EDATA4.
+* To use register names with standard convension, please use CAN_MO62_EDATA4.
+*/
+#define CAN_EMO62DATA4 (CAN_MO62_EDATA4)
+
+/** \brief 17D4, Message Object Data Register High */
+#define CAN_MO62_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00197D4u)
+
+/** Alias (User Manual Name) for CAN_MO62_EDATA5.
+* To use register names with standard convension, please use CAN_MO62_EDATA5.
+*/
+#define CAN_EMO62DATA5 (CAN_MO62_EDATA5)
+
+/** \brief 17D8, Message Object Arbitration Register */
+#define CAN_MO62_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00197D8u)
+
+/** Alias (User Manual Name) for CAN_MO62_EDATA6.
+* To use register names with standard convension, please use CAN_MO62_EDATA6.
+*/
+#define CAN_EMO62DATA6 (CAN_MO62_EDATA6)
+
+/** \brief 17C0, Message Object Function Control Register */
+#define CAN_MO62_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00197C0u)
+
+/** Alias (User Manual Name) for CAN_MO62_FCR.
+* To use register names with standard convension, please use CAN_MO62_FCR.
+*/
+#define CAN_MOFCR62 (CAN_MO62_FCR)
+
+/** \brief 17C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO62_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00197C4u)
+
+/** Alias (User Manual Name) for CAN_MO62_FGPR.
+* To use register names with standard convension, please use CAN_MO62_FGPR.
+*/
+#define CAN_MOFGPR62 (CAN_MO62_FGPR)
+
+/** \brief 17C8, Message Object Interrupt Pointer Register */
+#define CAN_MO62_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00197C8u)
+
+/** Alias (User Manual Name) for CAN_MO62_IPR.
+* To use register names with standard convension, please use CAN_MO62_IPR.
+*/
+#define CAN_MOIPR62 (CAN_MO62_IPR)
+
+/** \brief 17DC, Message Object Control Register */
+#define CAN_MO62_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00197DCu)
+
+/** Alias (User Manual Name) for CAN_MO62_STAT.
+* To use register names with standard convension, please use CAN_MO62_STAT.
+*/
+#define CAN_MOSTAT62 (CAN_MO62_STAT)
+
+/** \brief 17EC, Message Object Acceptance Mask Register */
+#define CAN_MO63_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00197ECu)
+
+/** Alias (User Manual Name) for CAN_MO63_AMR.
+* To use register names with standard convension, please use CAN_MO63_AMR.
+*/
+#define CAN_MOAMR63 (CAN_MO63_AMR)
+
+/** \brief 17F8, Message Object Arbitration Register */
+#define CAN_MO63_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00197F8u)
+
+/** Alias (User Manual Name) for CAN_MO63_AR.
+* To use register names with standard convension, please use CAN_MO63_AR.
+*/
+#define CAN_MOAR63 (CAN_MO63_AR)
+
+/** \brief 17FC, Message Object Control Register */
+#define CAN_MO63_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00197FCu)
+
+/** Alias (User Manual Name) for CAN_MO63_CTR.
+* To use register names with standard convension, please use CAN_MO63_CTR.
+*/
+#define CAN_MOCTR63 (CAN_MO63_CTR)
+
+/** \brief 17F4, Message Object Data Register High */
+#define CAN_MO63_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00197F4u)
+
+/** Alias (User Manual Name) for CAN_MO63_DATAH.
+* To use register names with standard convension, please use CAN_MO63_DATAH.
+*/
+#define CAN_MODATAH63 (CAN_MO63_DATAH)
+
+/** \brief 17F0, Message Object Data Register Low */
+#define CAN_MO63_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00197F0u)
+
+/** Alias (User Manual Name) for CAN_MO63_DATAL.
+* To use register names with standard convension, please use CAN_MO63_DATAL.
+*/
+#define CAN_MODATAL63 (CAN_MO63_DATAL)
+
+/** \brief 17E0, Message Object Function Control Register */
+#define CAN_MO63_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00197E0u)
+
+/** Alias (User Manual Name) for CAN_MO63_EDATA0.
+* To use register names with standard convension, please use CAN_MO63_EDATA0.
+*/
+#define CAN_EMO63DATA0 (CAN_MO63_EDATA0)
+
+/** \brief 17E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO63_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00197E4u)
+
+/** Alias (User Manual Name) for CAN_MO63_EDATA1.
+* To use register names with standard convension, please use CAN_MO63_EDATA1.
+*/
+#define CAN_EMO63DATA1 (CAN_MO63_EDATA1)
+
+/** \brief 17E8, Message Object Interrupt Pointer Register */
+#define CAN_MO63_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00197E8u)
+
+/** Alias (User Manual Name) for CAN_MO63_EDATA2.
+* To use register names with standard convension, please use CAN_MO63_EDATA2.
+*/
+#define CAN_EMO63DATA2 (CAN_MO63_EDATA2)
+
+/** \brief 17EC, Message Object Acceptance Mask Register */
+#define CAN_MO63_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00197ECu)
+
+/** Alias (User Manual Name) for CAN_MO63_EDATA3.
+* To use register names with standard convension, please use CAN_MO63_EDATA3.
+*/
+#define CAN_EMO63DATA3 (CAN_MO63_EDATA3)
+
+/** \brief 17F0, Message Object Data Register Low */
+#define CAN_MO63_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00197F0u)
+
+/** Alias (User Manual Name) for CAN_MO63_EDATA4.
+* To use register names with standard convension, please use CAN_MO63_EDATA4.
+*/
+#define CAN_EMO63DATA4 (CAN_MO63_EDATA4)
+
+/** \brief 17F4, Message Object Data Register High */
+#define CAN_MO63_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00197F4u)
+
+/** Alias (User Manual Name) for CAN_MO63_EDATA5.
+* To use register names with standard convension, please use CAN_MO63_EDATA5.
+*/
+#define CAN_EMO63DATA5 (CAN_MO63_EDATA5)
+
+/** \brief 17F8, Message Object Arbitration Register */
+#define CAN_MO63_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00197F8u)
+
+/** Alias (User Manual Name) for CAN_MO63_EDATA6.
+* To use register names with standard convension, please use CAN_MO63_EDATA6.
+*/
+#define CAN_EMO63DATA6 (CAN_MO63_EDATA6)
+
+/** \brief 17E0, Message Object Function Control Register */
+#define CAN_MO63_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00197E0u)
+
+/** Alias (User Manual Name) for CAN_MO63_FCR.
+* To use register names with standard convension, please use CAN_MO63_FCR.
+*/
+#define CAN_MOFCR63 (CAN_MO63_FCR)
+
+/** \brief 17E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO63_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00197E4u)
+
+/** Alias (User Manual Name) for CAN_MO63_FGPR.
+* To use register names with standard convension, please use CAN_MO63_FGPR.
+*/
+#define CAN_MOFGPR63 (CAN_MO63_FGPR)
+
+/** \brief 17E8, Message Object Interrupt Pointer Register */
+#define CAN_MO63_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00197E8u)
+
+/** Alias (User Manual Name) for CAN_MO63_IPR.
+* To use register names with standard convension, please use CAN_MO63_IPR.
+*/
+#define CAN_MOIPR63 (CAN_MO63_IPR)
+
+/** \brief 17FC, Message Object Control Register */
+#define CAN_MO63_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00197FCu)
+
+/** Alias (User Manual Name) for CAN_MO63_STAT.
+* To use register names with standard convension, please use CAN_MO63_STAT.
+*/
+#define CAN_MOSTAT63 (CAN_MO63_STAT)
+
+/** \brief 180C, Message Object Acceptance Mask Register */
+#define CAN_MO64_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001980Cu)
+
+/** Alias (User Manual Name) for CAN_MO64_AMR.
+* To use register names with standard convension, please use CAN_MO64_AMR.
+*/
+#define CAN_MOAMR64 (CAN_MO64_AMR)
+
+/** \brief 1818, Message Object Arbitration Register */
+#define CAN_MO64_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019818u)
+
+/** Alias (User Manual Name) for CAN_MO64_AR.
+* To use register names with standard convension, please use CAN_MO64_AR.
+*/
+#define CAN_MOAR64 (CAN_MO64_AR)
+
+/** \brief 181C, Message Object Control Register */
+#define CAN_MO64_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001981Cu)
+
+/** Alias (User Manual Name) for CAN_MO64_CTR.
+* To use register names with standard convension, please use CAN_MO64_CTR.
+*/
+#define CAN_MOCTR64 (CAN_MO64_CTR)
+
+/** \brief 1814, Message Object Data Register High */
+#define CAN_MO64_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019814u)
+
+/** Alias (User Manual Name) for CAN_MO64_DATAH.
+* To use register names with standard convension, please use CAN_MO64_DATAH.
+*/
+#define CAN_MODATAH64 (CAN_MO64_DATAH)
+
+/** \brief 1810, Message Object Data Register Low */
+#define CAN_MO64_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019810u)
+
+/** Alias (User Manual Name) for CAN_MO64_DATAL.
+* To use register names with standard convension, please use CAN_MO64_DATAL.
+*/
+#define CAN_MODATAL64 (CAN_MO64_DATAL)
+
+/** \brief 1800, Message Object Function Control Register */
+#define CAN_MO64_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019800u)
+
+/** Alias (User Manual Name) for CAN_MO64_EDATA0.
+* To use register names with standard convension, please use CAN_MO64_EDATA0.
+*/
+#define CAN_EMO64DATA0 (CAN_MO64_EDATA0)
+
+/** \brief 1804, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO64_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019804u)
+
+/** Alias (User Manual Name) for CAN_MO64_EDATA1.
+* To use register names with standard convension, please use CAN_MO64_EDATA1.
+*/
+#define CAN_EMO64DATA1 (CAN_MO64_EDATA1)
+
+/** \brief 1808, Message Object Interrupt Pointer Register */
+#define CAN_MO64_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019808u)
+
+/** Alias (User Manual Name) for CAN_MO64_EDATA2.
+* To use register names with standard convension, please use CAN_MO64_EDATA2.
+*/
+#define CAN_EMO64DATA2 (CAN_MO64_EDATA2)
+
+/** \brief 180C, Message Object Acceptance Mask Register */
+#define CAN_MO64_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001980Cu)
+
+/** Alias (User Manual Name) for CAN_MO64_EDATA3.
+* To use register names with standard convension, please use CAN_MO64_EDATA3.
+*/
+#define CAN_EMO64DATA3 (CAN_MO64_EDATA3)
+
+/** \brief 1810, Message Object Data Register Low */
+#define CAN_MO64_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019810u)
+
+/** Alias (User Manual Name) for CAN_MO64_EDATA4.
+* To use register names with standard convension, please use CAN_MO64_EDATA4.
+*/
+#define CAN_EMO64DATA4 (CAN_MO64_EDATA4)
+
+/** \brief 1814, Message Object Data Register High */
+#define CAN_MO64_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019814u)
+
+/** Alias (User Manual Name) for CAN_MO64_EDATA5.
+* To use register names with standard convension, please use CAN_MO64_EDATA5.
+*/
+#define CAN_EMO64DATA5 (CAN_MO64_EDATA5)
+
+/** \brief 1818, Message Object Arbitration Register */
+#define CAN_MO64_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019818u)
+
+/** Alias (User Manual Name) for CAN_MO64_EDATA6.
+* To use register names with standard convension, please use CAN_MO64_EDATA6.
+*/
+#define CAN_EMO64DATA6 (CAN_MO64_EDATA6)
+
+/** \brief 1800, Message Object Function Control Register */
+#define CAN_MO64_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019800u)
+
+/** Alias (User Manual Name) for CAN_MO64_FCR.
+* To use register names with standard convension, please use CAN_MO64_FCR.
+*/
+#define CAN_MOFCR64 (CAN_MO64_FCR)
+
+/** \brief 1804, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO64_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019804u)
+
+/** Alias (User Manual Name) for CAN_MO64_FGPR.
+* To use register names with standard convension, please use CAN_MO64_FGPR.
+*/
+#define CAN_MOFGPR64 (CAN_MO64_FGPR)
+
+/** \brief 1808, Message Object Interrupt Pointer Register */
+#define CAN_MO64_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019808u)
+
+/** Alias (User Manual Name) for CAN_MO64_IPR.
+* To use register names with standard convension, please use CAN_MO64_IPR.
+*/
+#define CAN_MOIPR64 (CAN_MO64_IPR)
+
+/** \brief 181C, Message Object Control Register */
+#define CAN_MO64_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001981Cu)
+
+/** Alias (User Manual Name) for CAN_MO64_STAT.
+* To use register names with standard convension, please use CAN_MO64_STAT.
+*/
+#define CAN_MOSTAT64 (CAN_MO64_STAT)
+
+/** \brief 182C, Message Object Acceptance Mask Register */
+#define CAN_MO65_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001982Cu)
+
+/** Alias (User Manual Name) for CAN_MO65_AMR.
+* To use register names with standard convension, please use CAN_MO65_AMR.
+*/
+#define CAN_MOAMR65 (CAN_MO65_AMR)
+
+/** \brief 1838, Message Object Arbitration Register */
+#define CAN_MO65_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019838u)
+
+/** Alias (User Manual Name) for CAN_MO65_AR.
+* To use register names with standard convension, please use CAN_MO65_AR.
+*/
+#define CAN_MOAR65 (CAN_MO65_AR)
+
+/** \brief 183C, Message Object Control Register */
+#define CAN_MO65_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001983Cu)
+
+/** Alias (User Manual Name) for CAN_MO65_CTR.
+* To use register names with standard convension, please use CAN_MO65_CTR.
+*/
+#define CAN_MOCTR65 (CAN_MO65_CTR)
+
+/** \brief 1834, Message Object Data Register High */
+#define CAN_MO65_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019834u)
+
+/** Alias (User Manual Name) for CAN_MO65_DATAH.
+* To use register names with standard convension, please use CAN_MO65_DATAH.
+*/
+#define CAN_MODATAH65 (CAN_MO65_DATAH)
+
+/** \brief 1830, Message Object Data Register Low */
+#define CAN_MO65_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019830u)
+
+/** Alias (User Manual Name) for CAN_MO65_DATAL.
+* To use register names with standard convension, please use CAN_MO65_DATAL.
+*/
+#define CAN_MODATAL65 (CAN_MO65_DATAL)
+
+/** \brief 1820, Message Object Function Control Register */
+#define CAN_MO65_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019820u)
+
+/** Alias (User Manual Name) for CAN_MO65_EDATA0.
+* To use register names with standard convension, please use CAN_MO65_EDATA0.
+*/
+#define CAN_EMO65DATA0 (CAN_MO65_EDATA0)
+
+/** \brief 1824, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO65_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019824u)
+
+/** Alias (User Manual Name) for CAN_MO65_EDATA1.
+* To use register names with standard convension, please use CAN_MO65_EDATA1.
+*/
+#define CAN_EMO65DATA1 (CAN_MO65_EDATA1)
+
+/** \brief 1828, Message Object Interrupt Pointer Register */
+#define CAN_MO65_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019828u)
+
+/** Alias (User Manual Name) for CAN_MO65_EDATA2.
+* To use register names with standard convension, please use CAN_MO65_EDATA2.
+*/
+#define CAN_EMO65DATA2 (CAN_MO65_EDATA2)
+
+/** \brief 182C, Message Object Acceptance Mask Register */
+#define CAN_MO65_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001982Cu)
+
+/** Alias (User Manual Name) for CAN_MO65_EDATA3.
+* To use register names with standard convension, please use CAN_MO65_EDATA3.
+*/
+#define CAN_EMO65DATA3 (CAN_MO65_EDATA3)
+
+/** \brief 1830, Message Object Data Register Low */
+#define CAN_MO65_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019830u)
+
+/** Alias (User Manual Name) for CAN_MO65_EDATA4.
+* To use register names with standard convension, please use CAN_MO65_EDATA4.
+*/
+#define CAN_EMO65DATA4 (CAN_MO65_EDATA4)
+
+/** \brief 1834, Message Object Data Register High */
+#define CAN_MO65_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019834u)
+
+/** Alias (User Manual Name) for CAN_MO65_EDATA5.
+* To use register names with standard convension, please use CAN_MO65_EDATA5.
+*/
+#define CAN_EMO65DATA5 (CAN_MO65_EDATA5)
+
+/** \brief 1838, Message Object Arbitration Register */
+#define CAN_MO65_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019838u)
+
+/** Alias (User Manual Name) for CAN_MO65_EDATA6.
+* To use register names with standard convension, please use CAN_MO65_EDATA6.
+*/
+#define CAN_EMO65DATA6 (CAN_MO65_EDATA6)
+
+/** \brief 1820, Message Object Function Control Register */
+#define CAN_MO65_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019820u)
+
+/** Alias (User Manual Name) for CAN_MO65_FCR.
+* To use register names with standard convension, please use CAN_MO65_FCR.
+*/
+#define CAN_MOFCR65 (CAN_MO65_FCR)
+
+/** \brief 1824, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO65_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019824u)
+
+/** Alias (User Manual Name) for CAN_MO65_FGPR.
+* To use register names with standard convension, please use CAN_MO65_FGPR.
+*/
+#define CAN_MOFGPR65 (CAN_MO65_FGPR)
+
+/** \brief 1828, Message Object Interrupt Pointer Register */
+#define CAN_MO65_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019828u)
+
+/** Alias (User Manual Name) for CAN_MO65_IPR.
+* To use register names with standard convension, please use CAN_MO65_IPR.
+*/
+#define CAN_MOIPR65 (CAN_MO65_IPR)
+
+/** \brief 183C, Message Object Control Register */
+#define CAN_MO65_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001983Cu)
+
+/** Alias (User Manual Name) for CAN_MO65_STAT.
+* To use register names with standard convension, please use CAN_MO65_STAT.
+*/
+#define CAN_MOSTAT65 (CAN_MO65_STAT)
+
+/** \brief 184C, Message Object Acceptance Mask Register */
+#define CAN_MO66_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001984Cu)
+
+/** Alias (User Manual Name) for CAN_MO66_AMR.
+* To use register names with standard convension, please use CAN_MO66_AMR.
+*/
+#define CAN_MOAMR66 (CAN_MO66_AMR)
+
+/** \brief 1858, Message Object Arbitration Register */
+#define CAN_MO66_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019858u)
+
+/** Alias (User Manual Name) for CAN_MO66_AR.
+* To use register names with standard convension, please use CAN_MO66_AR.
+*/
+#define CAN_MOAR66 (CAN_MO66_AR)
+
+/** \brief 185C, Message Object Control Register */
+#define CAN_MO66_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001985Cu)
+
+/** Alias (User Manual Name) for CAN_MO66_CTR.
+* To use register names with standard convension, please use CAN_MO66_CTR.
+*/
+#define CAN_MOCTR66 (CAN_MO66_CTR)
+
+/** \brief 1854, Message Object Data Register High */
+#define CAN_MO66_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019854u)
+
+/** Alias (User Manual Name) for CAN_MO66_DATAH.
+* To use register names with standard convension, please use CAN_MO66_DATAH.
+*/
+#define CAN_MODATAH66 (CAN_MO66_DATAH)
+
+/** \brief 1850, Message Object Data Register Low */
+#define CAN_MO66_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019850u)
+
+/** Alias (User Manual Name) for CAN_MO66_DATAL.
+* To use register names with standard convension, please use CAN_MO66_DATAL.
+*/
+#define CAN_MODATAL66 (CAN_MO66_DATAL)
+
+/** \brief 1840, Message Object Function Control Register */
+#define CAN_MO66_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019840u)
+
+/** Alias (User Manual Name) for CAN_MO66_EDATA0.
+* To use register names with standard convension, please use CAN_MO66_EDATA0.
+*/
+#define CAN_EMO66DATA0 (CAN_MO66_EDATA0)
+
+/** \brief 1844, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO66_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019844u)
+
+/** Alias (User Manual Name) for CAN_MO66_EDATA1.
+* To use register names with standard convension, please use CAN_MO66_EDATA1.
+*/
+#define CAN_EMO66DATA1 (CAN_MO66_EDATA1)
+
+/** \brief 1848, Message Object Interrupt Pointer Register */
+#define CAN_MO66_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019848u)
+
+/** Alias (User Manual Name) for CAN_MO66_EDATA2.
+* To use register names with standard convension, please use CAN_MO66_EDATA2.
+*/
+#define CAN_EMO66DATA2 (CAN_MO66_EDATA2)
+
+/** \brief 184C, Message Object Acceptance Mask Register */
+#define CAN_MO66_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001984Cu)
+
+/** Alias (User Manual Name) for CAN_MO66_EDATA3.
+* To use register names with standard convension, please use CAN_MO66_EDATA3.
+*/
+#define CAN_EMO66DATA3 (CAN_MO66_EDATA3)
+
+/** \brief 1850, Message Object Data Register Low */
+#define CAN_MO66_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019850u)
+
+/** Alias (User Manual Name) for CAN_MO66_EDATA4.
+* To use register names with standard convension, please use CAN_MO66_EDATA4.
+*/
+#define CAN_EMO66DATA4 (CAN_MO66_EDATA4)
+
+/** \brief 1854, Message Object Data Register High */
+#define CAN_MO66_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019854u)
+
+/** Alias (User Manual Name) for CAN_MO66_EDATA5.
+* To use register names with standard convension, please use CAN_MO66_EDATA5.
+*/
+#define CAN_EMO66DATA5 (CAN_MO66_EDATA5)
+
+/** \brief 1858, Message Object Arbitration Register */
+#define CAN_MO66_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019858u)
+
+/** Alias (User Manual Name) for CAN_MO66_EDATA6.
+* To use register names with standard convension, please use CAN_MO66_EDATA6.
+*/
+#define CAN_EMO66DATA6 (CAN_MO66_EDATA6)
+
+/** \brief 1840, Message Object Function Control Register */
+#define CAN_MO66_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019840u)
+
+/** Alias (User Manual Name) for CAN_MO66_FCR.
+* To use register names with standard convension, please use CAN_MO66_FCR.
+*/
+#define CAN_MOFCR66 (CAN_MO66_FCR)
+
+/** \brief 1844, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO66_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019844u)
+
+/** Alias (User Manual Name) for CAN_MO66_FGPR.
+* To use register names with standard convension, please use CAN_MO66_FGPR.
+*/
+#define CAN_MOFGPR66 (CAN_MO66_FGPR)
+
+/** \brief 1848, Message Object Interrupt Pointer Register */
+#define CAN_MO66_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019848u)
+
+/** Alias (User Manual Name) for CAN_MO66_IPR.
+* To use register names with standard convension, please use CAN_MO66_IPR.
+*/
+#define CAN_MOIPR66 (CAN_MO66_IPR)
+
+/** \brief 185C, Message Object Control Register */
+#define CAN_MO66_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001985Cu)
+
+/** Alias (User Manual Name) for CAN_MO66_STAT.
+* To use register names with standard convension, please use CAN_MO66_STAT.
+*/
+#define CAN_MOSTAT66 (CAN_MO66_STAT)
+
+/** \brief 186C, Message Object Acceptance Mask Register */
+#define CAN_MO67_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001986Cu)
+
+/** Alias (User Manual Name) for CAN_MO67_AMR.
+* To use register names with standard convension, please use CAN_MO67_AMR.
+*/
+#define CAN_MOAMR67 (CAN_MO67_AMR)
+
+/** \brief 1878, Message Object Arbitration Register */
+#define CAN_MO67_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019878u)
+
+/** Alias (User Manual Name) for CAN_MO67_AR.
+* To use register names with standard convension, please use CAN_MO67_AR.
+*/
+#define CAN_MOAR67 (CAN_MO67_AR)
+
+/** \brief 187C, Message Object Control Register */
+#define CAN_MO67_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001987Cu)
+
+/** Alias (User Manual Name) for CAN_MO67_CTR.
+* To use register names with standard convension, please use CAN_MO67_CTR.
+*/
+#define CAN_MOCTR67 (CAN_MO67_CTR)
+
+/** \brief 1874, Message Object Data Register High */
+#define CAN_MO67_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019874u)
+
+/** Alias (User Manual Name) for CAN_MO67_DATAH.
+* To use register names with standard convension, please use CAN_MO67_DATAH.
+*/
+#define CAN_MODATAH67 (CAN_MO67_DATAH)
+
+/** \brief 1870, Message Object Data Register Low */
+#define CAN_MO67_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019870u)
+
+/** Alias (User Manual Name) for CAN_MO67_DATAL.
+* To use register names with standard convension, please use CAN_MO67_DATAL.
+*/
+#define CAN_MODATAL67 (CAN_MO67_DATAL)
+
+/** \brief 1860, Message Object Function Control Register */
+#define CAN_MO67_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019860u)
+
+/** Alias (User Manual Name) for CAN_MO67_EDATA0.
+* To use register names with standard convension, please use CAN_MO67_EDATA0.
+*/
+#define CAN_EMO67DATA0 (CAN_MO67_EDATA0)
+
+/** \brief 1864, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO67_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019864u)
+
+/** Alias (User Manual Name) for CAN_MO67_EDATA1.
+* To use register names with standard convension, please use CAN_MO67_EDATA1.
+*/
+#define CAN_EMO67DATA1 (CAN_MO67_EDATA1)
+
+/** \brief 1868, Message Object Interrupt Pointer Register */
+#define CAN_MO67_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019868u)
+
+/** Alias (User Manual Name) for CAN_MO67_EDATA2.
+* To use register names with standard convension, please use CAN_MO67_EDATA2.
+*/
+#define CAN_EMO67DATA2 (CAN_MO67_EDATA2)
+
+/** \brief 186C, Message Object Acceptance Mask Register */
+#define CAN_MO67_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001986Cu)
+
+/** Alias (User Manual Name) for CAN_MO67_EDATA3.
+* To use register names with standard convension, please use CAN_MO67_EDATA3.
+*/
+#define CAN_EMO67DATA3 (CAN_MO67_EDATA3)
+
+/** \brief 1870, Message Object Data Register Low */
+#define CAN_MO67_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019870u)
+
+/** Alias (User Manual Name) for CAN_MO67_EDATA4.
+* To use register names with standard convension, please use CAN_MO67_EDATA4.
+*/
+#define CAN_EMO67DATA4 (CAN_MO67_EDATA4)
+
+/** \brief 1874, Message Object Data Register High */
+#define CAN_MO67_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019874u)
+
+/** Alias (User Manual Name) for CAN_MO67_EDATA5.
+* To use register names with standard convension, please use CAN_MO67_EDATA5.
+*/
+#define CAN_EMO67DATA5 (CAN_MO67_EDATA5)
+
+/** \brief 1878, Message Object Arbitration Register */
+#define CAN_MO67_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019878u)
+
+/** Alias (User Manual Name) for CAN_MO67_EDATA6.
+* To use register names with standard convension, please use CAN_MO67_EDATA6.
+*/
+#define CAN_EMO67DATA6 (CAN_MO67_EDATA6)
+
+/** \brief 1860, Message Object Function Control Register */
+#define CAN_MO67_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019860u)
+
+/** Alias (User Manual Name) for CAN_MO67_FCR.
+* To use register names with standard convension, please use CAN_MO67_FCR.
+*/
+#define CAN_MOFCR67 (CAN_MO67_FCR)
+
+/** \brief 1864, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO67_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019864u)
+
+/** Alias (User Manual Name) for CAN_MO67_FGPR.
+* To use register names with standard convension, please use CAN_MO67_FGPR.
+*/
+#define CAN_MOFGPR67 (CAN_MO67_FGPR)
+
+/** \brief 1868, Message Object Interrupt Pointer Register */
+#define CAN_MO67_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019868u)
+
+/** Alias (User Manual Name) for CAN_MO67_IPR.
+* To use register names with standard convension, please use CAN_MO67_IPR.
+*/
+#define CAN_MOIPR67 (CAN_MO67_IPR)
+
+/** \brief 187C, Message Object Control Register */
+#define CAN_MO67_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001987Cu)
+
+/** Alias (User Manual Name) for CAN_MO67_STAT.
+* To use register names with standard convension, please use CAN_MO67_STAT.
+*/
+#define CAN_MOSTAT67 (CAN_MO67_STAT)
+
+/** \brief 188C, Message Object Acceptance Mask Register */
+#define CAN_MO68_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001988Cu)
+
+/** Alias (User Manual Name) for CAN_MO68_AMR.
+* To use register names with standard convension, please use CAN_MO68_AMR.
+*/
+#define CAN_MOAMR68 (CAN_MO68_AMR)
+
+/** \brief 1898, Message Object Arbitration Register */
+#define CAN_MO68_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019898u)
+
+/** Alias (User Manual Name) for CAN_MO68_AR.
+* To use register names with standard convension, please use CAN_MO68_AR.
+*/
+#define CAN_MOAR68 (CAN_MO68_AR)
+
+/** \brief 189C, Message Object Control Register */
+#define CAN_MO68_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001989Cu)
+
+/** Alias (User Manual Name) for CAN_MO68_CTR.
+* To use register names with standard convension, please use CAN_MO68_CTR.
+*/
+#define CAN_MOCTR68 (CAN_MO68_CTR)
+
+/** \brief 1894, Message Object Data Register High */
+#define CAN_MO68_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019894u)
+
+/** Alias (User Manual Name) for CAN_MO68_DATAH.
+* To use register names with standard convension, please use CAN_MO68_DATAH.
+*/
+#define CAN_MODATAH68 (CAN_MO68_DATAH)
+
+/** \brief 1890, Message Object Data Register Low */
+#define CAN_MO68_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019890u)
+
+/** Alias (User Manual Name) for CAN_MO68_DATAL.
+* To use register names with standard convension, please use CAN_MO68_DATAL.
+*/
+#define CAN_MODATAL68 (CAN_MO68_DATAL)
+
+/** \brief 1880, Message Object Function Control Register */
+#define CAN_MO68_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019880u)
+
+/** Alias (User Manual Name) for CAN_MO68_EDATA0.
+* To use register names with standard convension, please use CAN_MO68_EDATA0.
+*/
+#define CAN_EMO68DATA0 (CAN_MO68_EDATA0)
+
+/** \brief 1884, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO68_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019884u)
+
+/** Alias (User Manual Name) for CAN_MO68_EDATA1.
+* To use register names with standard convension, please use CAN_MO68_EDATA1.
+*/
+#define CAN_EMO68DATA1 (CAN_MO68_EDATA1)
+
+/** \brief 1888, Message Object Interrupt Pointer Register */
+#define CAN_MO68_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019888u)
+
+/** Alias (User Manual Name) for CAN_MO68_EDATA2.
+* To use register names with standard convension, please use CAN_MO68_EDATA2.
+*/
+#define CAN_EMO68DATA2 (CAN_MO68_EDATA2)
+
+/** \brief 188C, Message Object Acceptance Mask Register */
+#define CAN_MO68_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001988Cu)
+
+/** Alias (User Manual Name) for CAN_MO68_EDATA3.
+* To use register names with standard convension, please use CAN_MO68_EDATA3.
+*/
+#define CAN_EMO68DATA3 (CAN_MO68_EDATA3)
+
+/** \brief 1890, Message Object Data Register Low */
+#define CAN_MO68_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019890u)
+
+/** Alias (User Manual Name) for CAN_MO68_EDATA4.
+* To use register names with standard convension, please use CAN_MO68_EDATA4.
+*/
+#define CAN_EMO68DATA4 (CAN_MO68_EDATA4)
+
+/** \brief 1894, Message Object Data Register High */
+#define CAN_MO68_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019894u)
+
+/** Alias (User Manual Name) for CAN_MO68_EDATA5.
+* To use register names with standard convension, please use CAN_MO68_EDATA5.
+*/
+#define CAN_EMO68DATA5 (CAN_MO68_EDATA5)
+
+/** \brief 1898, Message Object Arbitration Register */
+#define CAN_MO68_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019898u)
+
+/** Alias (User Manual Name) for CAN_MO68_EDATA6.
+* To use register names with standard convension, please use CAN_MO68_EDATA6.
+*/
+#define CAN_EMO68DATA6 (CAN_MO68_EDATA6)
+
+/** \brief 1880, Message Object Function Control Register */
+#define CAN_MO68_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019880u)
+
+/** Alias (User Manual Name) for CAN_MO68_FCR.
+* To use register names with standard convension, please use CAN_MO68_FCR.
+*/
+#define CAN_MOFCR68 (CAN_MO68_FCR)
+
+/** \brief 1884, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO68_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019884u)
+
+/** Alias (User Manual Name) for CAN_MO68_FGPR.
+* To use register names with standard convension, please use CAN_MO68_FGPR.
+*/
+#define CAN_MOFGPR68 (CAN_MO68_FGPR)
+
+/** \brief 1888, Message Object Interrupt Pointer Register */
+#define CAN_MO68_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019888u)
+
+/** Alias (User Manual Name) for CAN_MO68_IPR.
+* To use register names with standard convension, please use CAN_MO68_IPR.
+*/
+#define CAN_MOIPR68 (CAN_MO68_IPR)
+
+/** \brief 189C, Message Object Control Register */
+#define CAN_MO68_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001989Cu)
+
+/** Alias (User Manual Name) for CAN_MO68_STAT.
+* To use register names with standard convension, please use CAN_MO68_STAT.
+*/
+#define CAN_MOSTAT68 (CAN_MO68_STAT)
+
+/** \brief 18AC, Message Object Acceptance Mask Register */
+#define CAN_MO69_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00198ACu)
+
+/** Alias (User Manual Name) for CAN_MO69_AMR.
+* To use register names with standard convension, please use CAN_MO69_AMR.
+*/
+#define CAN_MOAMR69 (CAN_MO69_AMR)
+
+/** \brief 18B8, Message Object Arbitration Register */
+#define CAN_MO69_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00198B8u)
+
+/** Alias (User Manual Name) for CAN_MO69_AR.
+* To use register names with standard convension, please use CAN_MO69_AR.
+*/
+#define CAN_MOAR69 (CAN_MO69_AR)
+
+/** \brief 18BC, Message Object Control Register */
+#define CAN_MO69_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00198BCu)
+
+/** Alias (User Manual Name) for CAN_MO69_CTR.
+* To use register names with standard convension, please use CAN_MO69_CTR.
+*/
+#define CAN_MOCTR69 (CAN_MO69_CTR)
+
+/** \brief 18B4, Message Object Data Register High */
+#define CAN_MO69_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00198B4u)
+
+/** Alias (User Manual Name) for CAN_MO69_DATAH.
+* To use register names with standard convension, please use CAN_MO69_DATAH.
+*/
+#define CAN_MODATAH69 (CAN_MO69_DATAH)
+
+/** \brief 18B0, Message Object Data Register Low */
+#define CAN_MO69_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00198B0u)
+
+/** Alias (User Manual Name) for CAN_MO69_DATAL.
+* To use register names with standard convension, please use CAN_MO69_DATAL.
+*/
+#define CAN_MODATAL69 (CAN_MO69_DATAL)
+
+/** \brief 18A0, Message Object Function Control Register */
+#define CAN_MO69_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00198A0u)
+
+/** Alias (User Manual Name) for CAN_MO69_EDATA0.
+* To use register names with standard convension, please use CAN_MO69_EDATA0.
+*/
+#define CAN_EMO69DATA0 (CAN_MO69_EDATA0)
+
+/** \brief 18A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO69_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00198A4u)
+
+/** Alias (User Manual Name) for CAN_MO69_EDATA1.
+* To use register names with standard convension, please use CAN_MO69_EDATA1.
+*/
+#define CAN_EMO69DATA1 (CAN_MO69_EDATA1)
+
+/** \brief 18A8, Message Object Interrupt Pointer Register */
+#define CAN_MO69_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00198A8u)
+
+/** Alias (User Manual Name) for CAN_MO69_EDATA2.
+* To use register names with standard convension, please use CAN_MO69_EDATA2.
+*/
+#define CAN_EMO69DATA2 (CAN_MO69_EDATA2)
+
+/** \brief 18AC, Message Object Acceptance Mask Register */
+#define CAN_MO69_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00198ACu)
+
+/** Alias (User Manual Name) for CAN_MO69_EDATA3.
+* To use register names with standard convension, please use CAN_MO69_EDATA3.
+*/
+#define CAN_EMO69DATA3 (CAN_MO69_EDATA3)
+
+/** \brief 18B0, Message Object Data Register Low */
+#define CAN_MO69_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00198B0u)
+
+/** Alias (User Manual Name) for CAN_MO69_EDATA4.
+* To use register names with standard convension, please use CAN_MO69_EDATA4.
+*/
+#define CAN_EMO69DATA4 (CAN_MO69_EDATA4)
+
+/** \brief 18B4, Message Object Data Register High */
+#define CAN_MO69_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00198B4u)
+
+/** Alias (User Manual Name) for CAN_MO69_EDATA5.
+* To use register names with standard convension, please use CAN_MO69_EDATA5.
+*/
+#define CAN_EMO69DATA5 (CAN_MO69_EDATA5)
+
+/** \brief 18B8, Message Object Arbitration Register */
+#define CAN_MO69_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00198B8u)
+
+/** Alias (User Manual Name) for CAN_MO69_EDATA6.
+* To use register names with standard convension, please use CAN_MO69_EDATA6.
+*/
+#define CAN_EMO69DATA6 (CAN_MO69_EDATA6)
+
+/** \brief 18A0, Message Object Function Control Register */
+#define CAN_MO69_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00198A0u)
+
+/** Alias (User Manual Name) for CAN_MO69_FCR.
+* To use register names with standard convension, please use CAN_MO69_FCR.
+*/
+#define CAN_MOFCR69 (CAN_MO69_FCR)
+
+/** \brief 18A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO69_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00198A4u)
+
+/** Alias (User Manual Name) for CAN_MO69_FGPR.
+* To use register names with standard convension, please use CAN_MO69_FGPR.
+*/
+#define CAN_MOFGPR69 (CAN_MO69_FGPR)
+
+/** \brief 18A8, Message Object Interrupt Pointer Register */
+#define CAN_MO69_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00198A8u)
+
+/** Alias (User Manual Name) for CAN_MO69_IPR.
+* To use register names with standard convension, please use CAN_MO69_IPR.
+*/
+#define CAN_MOIPR69 (CAN_MO69_IPR)
+
+/** \brief 18BC, Message Object Control Register */
+#define CAN_MO69_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00198BCu)
+
+/** Alias (User Manual Name) for CAN_MO69_STAT.
+* To use register names with standard convension, please use CAN_MO69_STAT.
+*/
+#define CAN_MOSTAT69 (CAN_MO69_STAT)
+
+/** \brief 10CC, Message Object Acceptance Mask Register */
+#define CAN_MO6_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00190CCu)
+
+/** Alias (User Manual Name) for CAN_MO6_AMR.
+* To use register names with standard convension, please use CAN_MO6_AMR.
+*/
+#define CAN_MOAMR6 (CAN_MO6_AMR)
+
+/** \brief 10D8, Message Object Arbitration Register */
+#define CAN_MO6_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00190D8u)
+
+/** Alias (User Manual Name) for CAN_MO6_AR.
+* To use register names with standard convension, please use CAN_MO6_AR.
+*/
+#define CAN_MOAR6 (CAN_MO6_AR)
+
+/** \brief 10DC, Message Object Control Register */
+#define CAN_MO6_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00190DCu)
+
+/** Alias (User Manual Name) for CAN_MO6_CTR.
+* To use register names with standard convension, please use CAN_MO6_CTR.
+*/
+#define CAN_MOCTR6 (CAN_MO6_CTR)
+
+/** \brief 10D4, Message Object Data Register High */
+#define CAN_MO6_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00190D4u)
+
+/** Alias (User Manual Name) for CAN_MO6_DATAH.
+* To use register names with standard convension, please use CAN_MO6_DATAH.
+*/
+#define CAN_MODATAH6 (CAN_MO6_DATAH)
+
+/** \brief 10D0, Message Object Data Register Low */
+#define CAN_MO6_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00190D0u)
+
+/** Alias (User Manual Name) for CAN_MO6_DATAL.
+* To use register names with standard convension, please use CAN_MO6_DATAL.
+*/
+#define CAN_MODATAL6 (CAN_MO6_DATAL)
+
+/** \brief 10C0, Message Object Function Control Register */
+#define CAN_MO6_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00190C0u)
+
+/** Alias (User Manual Name) for CAN_MO6_EDATA0.
+* To use register names with standard convension, please use CAN_MO6_EDATA0.
+*/
+#define CAN_EMO6DATA0 (CAN_MO6_EDATA0)
+
+/** \brief 10C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO6_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00190C4u)
+
+/** Alias (User Manual Name) for CAN_MO6_EDATA1.
+* To use register names with standard convension, please use CAN_MO6_EDATA1.
+*/
+#define CAN_EMO6DATA1 (CAN_MO6_EDATA1)
+
+/** \brief 10C8, Message Object Interrupt Pointer Register */
+#define CAN_MO6_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00190C8u)
+
+/** Alias (User Manual Name) for CAN_MO6_EDATA2.
+* To use register names with standard convension, please use CAN_MO6_EDATA2.
+*/
+#define CAN_EMO6DATA2 (CAN_MO6_EDATA2)
+
+/** \brief 10CC, Message Object Acceptance Mask Register */
+#define CAN_MO6_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00190CCu)
+
+/** Alias (User Manual Name) for CAN_MO6_EDATA3.
+* To use register names with standard convension, please use CAN_MO6_EDATA3.
+*/
+#define CAN_EMO6DATA3 (CAN_MO6_EDATA3)
+
+/** \brief 10D0, Message Object Data Register Low */
+#define CAN_MO6_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00190D0u)
+
+/** Alias (User Manual Name) for CAN_MO6_EDATA4.
+* To use register names with standard convension, please use CAN_MO6_EDATA4.
+*/
+#define CAN_EMO6DATA4 (CAN_MO6_EDATA4)
+
+/** \brief 10D4, Message Object Data Register High */
+#define CAN_MO6_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00190D4u)
+
+/** Alias (User Manual Name) for CAN_MO6_EDATA5.
+* To use register names with standard convension, please use CAN_MO6_EDATA5.
+*/
+#define CAN_EMO6DATA5 (CAN_MO6_EDATA5)
+
+/** \brief 10D8, Message Object Arbitration Register */
+#define CAN_MO6_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00190D8u)
+
+/** Alias (User Manual Name) for CAN_MO6_EDATA6.
+* To use register names with standard convension, please use CAN_MO6_EDATA6.
+*/
+#define CAN_EMO6DATA6 (CAN_MO6_EDATA6)
+
+/** \brief 10C0, Message Object Function Control Register */
+#define CAN_MO6_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00190C0u)
+
+/** Alias (User Manual Name) for CAN_MO6_FCR.
+* To use register names with standard convension, please use CAN_MO6_FCR.
+*/
+#define CAN_MOFCR6 (CAN_MO6_FCR)
+
+/** \brief 10C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO6_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00190C4u)
+
+/** Alias (User Manual Name) for CAN_MO6_FGPR.
+* To use register names with standard convension, please use CAN_MO6_FGPR.
+*/
+#define CAN_MOFGPR6 (CAN_MO6_FGPR)
+
+/** \brief 10C8, Message Object Interrupt Pointer Register */
+#define CAN_MO6_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00190C8u)
+
+/** Alias (User Manual Name) for CAN_MO6_IPR.
+* To use register names with standard convension, please use CAN_MO6_IPR.
+*/
+#define CAN_MOIPR6 (CAN_MO6_IPR)
+
+/** \brief 10DC, Message Object Control Register */
+#define CAN_MO6_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00190DCu)
+
+/** Alias (User Manual Name) for CAN_MO6_STAT.
+* To use register names with standard convension, please use CAN_MO6_STAT.
+*/
+#define CAN_MOSTAT6 (CAN_MO6_STAT)
+
+/** \brief 18CC, Message Object Acceptance Mask Register */
+#define CAN_MO70_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00198CCu)
+
+/** Alias (User Manual Name) for CAN_MO70_AMR.
+* To use register names with standard convension, please use CAN_MO70_AMR.
+*/
+#define CAN_MOAMR70 (CAN_MO70_AMR)
+
+/** \brief 18D8, Message Object Arbitration Register */
+#define CAN_MO70_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00198D8u)
+
+/** Alias (User Manual Name) for CAN_MO70_AR.
+* To use register names with standard convension, please use CAN_MO70_AR.
+*/
+#define CAN_MOAR70 (CAN_MO70_AR)
+
+/** \brief 18DC, Message Object Control Register */
+#define CAN_MO70_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00198DCu)
+
+/** Alias (User Manual Name) for CAN_MO70_CTR.
+* To use register names with standard convension, please use CAN_MO70_CTR.
+*/
+#define CAN_MOCTR70 (CAN_MO70_CTR)
+
+/** \brief 18D4, Message Object Data Register High */
+#define CAN_MO70_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00198D4u)
+
+/** Alias (User Manual Name) for CAN_MO70_DATAH.
+* To use register names with standard convension, please use CAN_MO70_DATAH.
+*/
+#define CAN_MODATAH70 (CAN_MO70_DATAH)
+
+/** \brief 18D0, Message Object Data Register Low */
+#define CAN_MO70_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00198D0u)
+
+/** Alias (User Manual Name) for CAN_MO70_DATAL.
+* To use register names with standard convension, please use CAN_MO70_DATAL.
+*/
+#define CAN_MODATAL70 (CAN_MO70_DATAL)
+
+/** \brief 18C0, Message Object Function Control Register */
+#define CAN_MO70_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00198C0u)
+
+/** Alias (User Manual Name) for CAN_MO70_EDATA0.
+* To use register names with standard convension, please use CAN_MO70_EDATA0.
+*/
+#define CAN_EMO70DATA0 (CAN_MO70_EDATA0)
+
+/** \brief 18C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO70_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00198C4u)
+
+/** Alias (User Manual Name) for CAN_MO70_EDATA1.
+* To use register names with standard convension, please use CAN_MO70_EDATA1.
+*/
+#define CAN_EMO70DATA1 (CAN_MO70_EDATA1)
+
+/** \brief 18C8, Message Object Interrupt Pointer Register */
+#define CAN_MO70_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00198C8u)
+
+/** Alias (User Manual Name) for CAN_MO70_EDATA2.
+* To use register names with standard convension, please use CAN_MO70_EDATA2.
+*/
+#define CAN_EMO70DATA2 (CAN_MO70_EDATA2)
+
+/** \brief 18CC, Message Object Acceptance Mask Register */
+#define CAN_MO70_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00198CCu)
+
+/** Alias (User Manual Name) for CAN_MO70_EDATA3.
+* To use register names with standard convension, please use CAN_MO70_EDATA3.
+*/
+#define CAN_EMO70DATA3 (CAN_MO70_EDATA3)
+
+/** \brief 18D0, Message Object Data Register Low */
+#define CAN_MO70_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00198D0u)
+
+/** Alias (User Manual Name) for CAN_MO70_EDATA4.
+* To use register names with standard convension, please use CAN_MO70_EDATA4.
+*/
+#define CAN_EMO70DATA4 (CAN_MO70_EDATA4)
+
+/** \brief 18D4, Message Object Data Register High */
+#define CAN_MO70_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00198D4u)
+
+/** Alias (User Manual Name) for CAN_MO70_EDATA5.
+* To use register names with standard convension, please use CAN_MO70_EDATA5.
+*/
+#define CAN_EMO70DATA5 (CAN_MO70_EDATA5)
+
+/** \brief 18D8, Message Object Arbitration Register */
+#define CAN_MO70_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00198D8u)
+
+/** Alias (User Manual Name) for CAN_MO70_EDATA6.
+* To use register names with standard convension, please use CAN_MO70_EDATA6.
+*/
+#define CAN_EMO70DATA6 (CAN_MO70_EDATA6)
+
+/** \brief 18C0, Message Object Function Control Register */
+#define CAN_MO70_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00198C0u)
+
+/** Alias (User Manual Name) for CAN_MO70_FCR.
+* To use register names with standard convension, please use CAN_MO70_FCR.
+*/
+#define CAN_MOFCR70 (CAN_MO70_FCR)
+
+/** \brief 18C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO70_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00198C4u)
+
+/** Alias (User Manual Name) for CAN_MO70_FGPR.
+* To use register names with standard convension, please use CAN_MO70_FGPR.
+*/
+#define CAN_MOFGPR70 (CAN_MO70_FGPR)
+
+/** \brief 18C8, Message Object Interrupt Pointer Register */
+#define CAN_MO70_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00198C8u)
+
+/** Alias (User Manual Name) for CAN_MO70_IPR.
+* To use register names with standard convension, please use CAN_MO70_IPR.
+*/
+#define CAN_MOIPR70 (CAN_MO70_IPR)
+
+/** \brief 18DC, Message Object Control Register */
+#define CAN_MO70_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00198DCu)
+
+/** Alias (User Manual Name) for CAN_MO70_STAT.
+* To use register names with standard convension, please use CAN_MO70_STAT.
+*/
+#define CAN_MOSTAT70 (CAN_MO70_STAT)
+
+/** \brief 18EC, Message Object Acceptance Mask Register */
+#define CAN_MO71_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00198ECu)
+
+/** Alias (User Manual Name) for CAN_MO71_AMR.
+* To use register names with standard convension, please use CAN_MO71_AMR.
+*/
+#define CAN_MOAMR71 (CAN_MO71_AMR)
+
+/** \brief 18F8, Message Object Arbitration Register */
+#define CAN_MO71_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00198F8u)
+
+/** Alias (User Manual Name) for CAN_MO71_AR.
+* To use register names with standard convension, please use CAN_MO71_AR.
+*/
+#define CAN_MOAR71 (CAN_MO71_AR)
+
+/** \brief 18FC, Message Object Control Register */
+#define CAN_MO71_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00198FCu)
+
+/** Alias (User Manual Name) for CAN_MO71_CTR.
+* To use register names with standard convension, please use CAN_MO71_CTR.
+*/
+#define CAN_MOCTR71 (CAN_MO71_CTR)
+
+/** \brief 18F4, Message Object Data Register High */
+#define CAN_MO71_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00198F4u)
+
+/** Alias (User Manual Name) for CAN_MO71_DATAH.
+* To use register names with standard convension, please use CAN_MO71_DATAH.
+*/
+#define CAN_MODATAH71 (CAN_MO71_DATAH)
+
+/** \brief 18F0, Message Object Data Register Low */
+#define CAN_MO71_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00198F0u)
+
+/** Alias (User Manual Name) for CAN_MO71_DATAL.
+* To use register names with standard convension, please use CAN_MO71_DATAL.
+*/
+#define CAN_MODATAL71 (CAN_MO71_DATAL)
+
+/** \brief 18E0, Message Object Function Control Register */
+#define CAN_MO71_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00198E0u)
+
+/** Alias (User Manual Name) for CAN_MO71_EDATA0.
+* To use register names with standard convension, please use CAN_MO71_EDATA0.
+*/
+#define CAN_EMO71DATA0 (CAN_MO71_EDATA0)
+
+/** \brief 18E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO71_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00198E4u)
+
+/** Alias (User Manual Name) for CAN_MO71_EDATA1.
+* To use register names with standard convension, please use CAN_MO71_EDATA1.
+*/
+#define CAN_EMO71DATA1 (CAN_MO71_EDATA1)
+
+/** \brief 18E8, Message Object Interrupt Pointer Register */
+#define CAN_MO71_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00198E8u)
+
+/** Alias (User Manual Name) for CAN_MO71_EDATA2.
+* To use register names with standard convension, please use CAN_MO71_EDATA2.
+*/
+#define CAN_EMO71DATA2 (CAN_MO71_EDATA2)
+
+/** \brief 18EC, Message Object Acceptance Mask Register */
+#define CAN_MO71_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00198ECu)
+
+/** Alias (User Manual Name) for CAN_MO71_EDATA3.
+* To use register names with standard convension, please use CAN_MO71_EDATA3.
+*/
+#define CAN_EMO71DATA3 (CAN_MO71_EDATA3)
+
+/** \brief 18F0, Message Object Data Register Low */
+#define CAN_MO71_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00198F0u)
+
+/** Alias (User Manual Name) for CAN_MO71_EDATA4.
+* To use register names with standard convension, please use CAN_MO71_EDATA4.
+*/
+#define CAN_EMO71DATA4 (CAN_MO71_EDATA4)
+
+/** \brief 18F4, Message Object Data Register High */
+#define CAN_MO71_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00198F4u)
+
+/** Alias (User Manual Name) for CAN_MO71_EDATA5.
+* To use register names with standard convension, please use CAN_MO71_EDATA5.
+*/
+#define CAN_EMO71DATA5 (CAN_MO71_EDATA5)
+
+/** \brief 18F8, Message Object Arbitration Register */
+#define CAN_MO71_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00198F8u)
+
+/** Alias (User Manual Name) for CAN_MO71_EDATA6.
+* To use register names with standard convension, please use CAN_MO71_EDATA6.
+*/
+#define CAN_EMO71DATA6 (CAN_MO71_EDATA6)
+
+/** \brief 18E0, Message Object Function Control Register */
+#define CAN_MO71_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00198E0u)
+
+/** Alias (User Manual Name) for CAN_MO71_FCR.
+* To use register names with standard convension, please use CAN_MO71_FCR.
+*/
+#define CAN_MOFCR71 (CAN_MO71_FCR)
+
+/** \brief 18E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO71_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00198E4u)
+
+/** Alias (User Manual Name) for CAN_MO71_FGPR.
+* To use register names with standard convension, please use CAN_MO71_FGPR.
+*/
+#define CAN_MOFGPR71 (CAN_MO71_FGPR)
+
+/** \brief 18E8, Message Object Interrupt Pointer Register */
+#define CAN_MO71_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00198E8u)
+
+/** Alias (User Manual Name) for CAN_MO71_IPR.
+* To use register names with standard convension, please use CAN_MO71_IPR.
+*/
+#define CAN_MOIPR71 (CAN_MO71_IPR)
+
+/** \brief 18FC, Message Object Control Register */
+#define CAN_MO71_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00198FCu)
+
+/** Alias (User Manual Name) for CAN_MO71_STAT.
+* To use register names with standard convension, please use CAN_MO71_STAT.
+*/
+#define CAN_MOSTAT71 (CAN_MO71_STAT)
+
+/** \brief 190C, Message Object Acceptance Mask Register */
+#define CAN_MO72_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001990Cu)
+
+/** Alias (User Manual Name) for CAN_MO72_AMR.
+* To use register names with standard convension, please use CAN_MO72_AMR.
+*/
+#define CAN_MOAMR72 (CAN_MO72_AMR)
+
+/** \brief 1918, Message Object Arbitration Register */
+#define CAN_MO72_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019918u)
+
+/** Alias (User Manual Name) for CAN_MO72_AR.
+* To use register names with standard convension, please use CAN_MO72_AR.
+*/
+#define CAN_MOAR72 (CAN_MO72_AR)
+
+/** \brief 191C, Message Object Control Register */
+#define CAN_MO72_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001991Cu)
+
+/** Alias (User Manual Name) for CAN_MO72_CTR.
+* To use register names with standard convension, please use CAN_MO72_CTR.
+*/
+#define CAN_MOCTR72 (CAN_MO72_CTR)
+
+/** \brief 1914, Message Object Data Register High */
+#define CAN_MO72_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019914u)
+
+/** Alias (User Manual Name) for CAN_MO72_DATAH.
+* To use register names with standard convension, please use CAN_MO72_DATAH.
+*/
+#define CAN_MODATAH72 (CAN_MO72_DATAH)
+
+/** \brief 1910, Message Object Data Register Low */
+#define CAN_MO72_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019910u)
+
+/** Alias (User Manual Name) for CAN_MO72_DATAL.
+* To use register names with standard convension, please use CAN_MO72_DATAL.
+*/
+#define CAN_MODATAL72 (CAN_MO72_DATAL)
+
+/** \brief 1900, Message Object Function Control Register */
+#define CAN_MO72_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019900u)
+
+/** Alias (User Manual Name) for CAN_MO72_EDATA0.
+* To use register names with standard convension, please use CAN_MO72_EDATA0.
+*/
+#define CAN_EMO72DATA0 (CAN_MO72_EDATA0)
+
+/** \brief 1904, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO72_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019904u)
+
+/** Alias (User Manual Name) for CAN_MO72_EDATA1.
+* To use register names with standard convension, please use CAN_MO72_EDATA1.
+*/
+#define CAN_EMO72DATA1 (CAN_MO72_EDATA1)
+
+/** \brief 1908, Message Object Interrupt Pointer Register */
+#define CAN_MO72_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019908u)
+
+/** Alias (User Manual Name) for CAN_MO72_EDATA2.
+* To use register names with standard convension, please use CAN_MO72_EDATA2.
+*/
+#define CAN_EMO72DATA2 (CAN_MO72_EDATA2)
+
+/** \brief 190C, Message Object Acceptance Mask Register */
+#define CAN_MO72_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001990Cu)
+
+/** Alias (User Manual Name) for CAN_MO72_EDATA3.
+* To use register names with standard convension, please use CAN_MO72_EDATA3.
+*/
+#define CAN_EMO72DATA3 (CAN_MO72_EDATA3)
+
+/** \brief 1910, Message Object Data Register Low */
+#define CAN_MO72_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019910u)
+
+/** Alias (User Manual Name) for CAN_MO72_EDATA4.
+* To use register names with standard convension, please use CAN_MO72_EDATA4.
+*/
+#define CAN_EMO72DATA4 (CAN_MO72_EDATA4)
+
+/** \brief 1914, Message Object Data Register High */
+#define CAN_MO72_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019914u)
+
+/** Alias (User Manual Name) for CAN_MO72_EDATA5.
+* To use register names with standard convension, please use CAN_MO72_EDATA5.
+*/
+#define CAN_EMO72DATA5 (CAN_MO72_EDATA5)
+
+/** \brief 1918, Message Object Arbitration Register */
+#define CAN_MO72_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019918u)
+
+/** Alias (User Manual Name) for CAN_MO72_EDATA6.
+* To use register names with standard convension, please use CAN_MO72_EDATA6.
+*/
+#define CAN_EMO72DATA6 (CAN_MO72_EDATA6)
+
+/** \brief 1900, Message Object Function Control Register */
+#define CAN_MO72_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019900u)
+
+/** Alias (User Manual Name) for CAN_MO72_FCR.
+* To use register names with standard convension, please use CAN_MO72_FCR.
+*/
+#define CAN_MOFCR72 (CAN_MO72_FCR)
+
+/** \brief 1904, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO72_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019904u)
+
+/** Alias (User Manual Name) for CAN_MO72_FGPR.
+* To use register names with standard convension, please use CAN_MO72_FGPR.
+*/
+#define CAN_MOFGPR72 (CAN_MO72_FGPR)
+
+/** \brief 1908, Message Object Interrupt Pointer Register */
+#define CAN_MO72_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019908u)
+
+/** Alias (User Manual Name) for CAN_MO72_IPR.
+* To use register names with standard convension, please use CAN_MO72_IPR.
+*/
+#define CAN_MOIPR72 (CAN_MO72_IPR)
+
+/** \brief 191C, Message Object Control Register */
+#define CAN_MO72_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001991Cu)
+
+/** Alias (User Manual Name) for CAN_MO72_STAT.
+* To use register names with standard convension, please use CAN_MO72_STAT.
+*/
+#define CAN_MOSTAT72 (CAN_MO72_STAT)
+
+/** \brief 192C, Message Object Acceptance Mask Register */
+#define CAN_MO73_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001992Cu)
+
+/** Alias (User Manual Name) for CAN_MO73_AMR.
+* To use register names with standard convension, please use CAN_MO73_AMR.
+*/
+#define CAN_MOAMR73 (CAN_MO73_AMR)
+
+/** \brief 1938, Message Object Arbitration Register */
+#define CAN_MO73_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019938u)
+
+/** Alias (User Manual Name) for CAN_MO73_AR.
+* To use register names with standard convension, please use CAN_MO73_AR.
+*/
+#define CAN_MOAR73 (CAN_MO73_AR)
+
+/** \brief 193C, Message Object Control Register */
+#define CAN_MO73_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001993Cu)
+
+/** Alias (User Manual Name) for CAN_MO73_CTR.
+* To use register names with standard convension, please use CAN_MO73_CTR.
+*/
+#define CAN_MOCTR73 (CAN_MO73_CTR)
+
+/** \brief 1934, Message Object Data Register High */
+#define CAN_MO73_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019934u)
+
+/** Alias (User Manual Name) for CAN_MO73_DATAH.
+* To use register names with standard convension, please use CAN_MO73_DATAH.
+*/
+#define CAN_MODATAH73 (CAN_MO73_DATAH)
+
+/** \brief 1930, Message Object Data Register Low */
+#define CAN_MO73_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019930u)
+
+/** Alias (User Manual Name) for CAN_MO73_DATAL.
+* To use register names with standard convension, please use CAN_MO73_DATAL.
+*/
+#define CAN_MODATAL73 (CAN_MO73_DATAL)
+
+/** \brief 1920, Message Object Function Control Register */
+#define CAN_MO73_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019920u)
+
+/** Alias (User Manual Name) for CAN_MO73_EDATA0.
+* To use register names with standard convension, please use CAN_MO73_EDATA0.
+*/
+#define CAN_EMO73DATA0 (CAN_MO73_EDATA0)
+
+/** \brief 1924, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO73_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019924u)
+
+/** Alias (User Manual Name) for CAN_MO73_EDATA1.
+* To use register names with standard convension, please use CAN_MO73_EDATA1.
+*/
+#define CAN_EMO73DATA1 (CAN_MO73_EDATA1)
+
+/** \brief 1928, Message Object Interrupt Pointer Register */
+#define CAN_MO73_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019928u)
+
+/** Alias (User Manual Name) for CAN_MO73_EDATA2.
+* To use register names with standard convension, please use CAN_MO73_EDATA2.
+*/
+#define CAN_EMO73DATA2 (CAN_MO73_EDATA2)
+
+/** \brief 192C, Message Object Acceptance Mask Register */
+#define CAN_MO73_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001992Cu)
+
+/** Alias (User Manual Name) for CAN_MO73_EDATA3.
+* To use register names with standard convension, please use CAN_MO73_EDATA3.
+*/
+#define CAN_EMO73DATA3 (CAN_MO73_EDATA3)
+
+/** \brief 1930, Message Object Data Register Low */
+#define CAN_MO73_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019930u)
+
+/** Alias (User Manual Name) for CAN_MO73_EDATA4.
+* To use register names with standard convension, please use CAN_MO73_EDATA4.
+*/
+#define CAN_EMO73DATA4 (CAN_MO73_EDATA4)
+
+/** \brief 1934, Message Object Data Register High */
+#define CAN_MO73_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019934u)
+
+/** Alias (User Manual Name) for CAN_MO73_EDATA5.
+* To use register names with standard convension, please use CAN_MO73_EDATA5.
+*/
+#define CAN_EMO73DATA5 (CAN_MO73_EDATA5)
+
+/** \brief 1938, Message Object Arbitration Register */
+#define CAN_MO73_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019938u)
+
+/** Alias (User Manual Name) for CAN_MO73_EDATA6.
+* To use register names with standard convension, please use CAN_MO73_EDATA6.
+*/
+#define CAN_EMO73DATA6 (CAN_MO73_EDATA6)
+
+/** \brief 1920, Message Object Function Control Register */
+#define CAN_MO73_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019920u)
+
+/** Alias (User Manual Name) for CAN_MO73_FCR.
+* To use register names with standard convension, please use CAN_MO73_FCR.
+*/
+#define CAN_MOFCR73 (CAN_MO73_FCR)
+
+/** \brief 1924, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO73_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019924u)
+
+/** Alias (User Manual Name) for CAN_MO73_FGPR.
+* To use register names with standard convension, please use CAN_MO73_FGPR.
+*/
+#define CAN_MOFGPR73 (CAN_MO73_FGPR)
+
+/** \brief 1928, Message Object Interrupt Pointer Register */
+#define CAN_MO73_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019928u)
+
+/** Alias (User Manual Name) for CAN_MO73_IPR.
+* To use register names with standard convension, please use CAN_MO73_IPR.
+*/
+#define CAN_MOIPR73 (CAN_MO73_IPR)
+
+/** \brief 193C, Message Object Control Register */
+#define CAN_MO73_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001993Cu)
+
+/** Alias (User Manual Name) for CAN_MO73_STAT.
+* To use register names with standard convension, please use CAN_MO73_STAT.
+*/
+#define CAN_MOSTAT73 (CAN_MO73_STAT)
+
+/** \brief 194C, Message Object Acceptance Mask Register */
+#define CAN_MO74_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001994Cu)
+
+/** Alias (User Manual Name) for CAN_MO74_AMR.
+* To use register names with standard convension, please use CAN_MO74_AMR.
+*/
+#define CAN_MOAMR74 (CAN_MO74_AMR)
+
+/** \brief 1958, Message Object Arbitration Register */
+#define CAN_MO74_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019958u)
+
+/** Alias (User Manual Name) for CAN_MO74_AR.
+* To use register names with standard convension, please use CAN_MO74_AR.
+*/
+#define CAN_MOAR74 (CAN_MO74_AR)
+
+/** \brief 195C, Message Object Control Register */
+#define CAN_MO74_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001995Cu)
+
+/** Alias (User Manual Name) for CAN_MO74_CTR.
+* To use register names with standard convension, please use CAN_MO74_CTR.
+*/
+#define CAN_MOCTR74 (CAN_MO74_CTR)
+
+/** \brief 1954, Message Object Data Register High */
+#define CAN_MO74_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019954u)
+
+/** Alias (User Manual Name) for CAN_MO74_DATAH.
+* To use register names with standard convension, please use CAN_MO74_DATAH.
+*/
+#define CAN_MODATAH74 (CAN_MO74_DATAH)
+
+/** \brief 1950, Message Object Data Register Low */
+#define CAN_MO74_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019950u)
+
+/** Alias (User Manual Name) for CAN_MO74_DATAL.
+* To use register names with standard convension, please use CAN_MO74_DATAL.
+*/
+#define CAN_MODATAL74 (CAN_MO74_DATAL)
+
+/** \brief 1940, Message Object Function Control Register */
+#define CAN_MO74_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019940u)
+
+/** Alias (User Manual Name) for CAN_MO74_EDATA0.
+* To use register names with standard convension, please use CAN_MO74_EDATA0.
+*/
+#define CAN_EMO74DATA0 (CAN_MO74_EDATA0)
+
+/** \brief 1944, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO74_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019944u)
+
+/** Alias (User Manual Name) for CAN_MO74_EDATA1.
+* To use register names with standard convension, please use CAN_MO74_EDATA1.
+*/
+#define CAN_EMO74DATA1 (CAN_MO74_EDATA1)
+
+/** \brief 1948, Message Object Interrupt Pointer Register */
+#define CAN_MO74_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019948u)
+
+/** Alias (User Manual Name) for CAN_MO74_EDATA2.
+* To use register names with standard convension, please use CAN_MO74_EDATA2.
+*/
+#define CAN_EMO74DATA2 (CAN_MO74_EDATA2)
+
+/** \brief 194C, Message Object Acceptance Mask Register */
+#define CAN_MO74_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001994Cu)
+
+/** Alias (User Manual Name) for CAN_MO74_EDATA3.
+* To use register names with standard convension, please use CAN_MO74_EDATA3.
+*/
+#define CAN_EMO74DATA3 (CAN_MO74_EDATA3)
+
+/** \brief 1950, Message Object Data Register Low */
+#define CAN_MO74_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019950u)
+
+/** Alias (User Manual Name) for CAN_MO74_EDATA4.
+* To use register names with standard convension, please use CAN_MO74_EDATA4.
+*/
+#define CAN_EMO74DATA4 (CAN_MO74_EDATA4)
+
+/** \brief 1954, Message Object Data Register High */
+#define CAN_MO74_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019954u)
+
+/** Alias (User Manual Name) for CAN_MO74_EDATA5.
+* To use register names with standard convension, please use CAN_MO74_EDATA5.
+*/
+#define CAN_EMO74DATA5 (CAN_MO74_EDATA5)
+
+/** \brief 1958, Message Object Arbitration Register */
+#define CAN_MO74_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019958u)
+
+/** Alias (User Manual Name) for CAN_MO74_EDATA6.
+* To use register names with standard convension, please use CAN_MO74_EDATA6.
+*/
+#define CAN_EMO74DATA6 (CAN_MO74_EDATA6)
+
+/** \brief 1940, Message Object Function Control Register */
+#define CAN_MO74_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019940u)
+
+/** Alias (User Manual Name) for CAN_MO74_FCR.
+* To use register names with standard convension, please use CAN_MO74_FCR.
+*/
+#define CAN_MOFCR74 (CAN_MO74_FCR)
+
+/** \brief 1944, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO74_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019944u)
+
+/** Alias (User Manual Name) for CAN_MO74_FGPR.
+* To use register names with standard convension, please use CAN_MO74_FGPR.
+*/
+#define CAN_MOFGPR74 (CAN_MO74_FGPR)
+
+/** \brief 1948, Message Object Interrupt Pointer Register */
+#define CAN_MO74_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019948u)
+
+/** Alias (User Manual Name) for CAN_MO74_IPR.
+* To use register names with standard convension, please use CAN_MO74_IPR.
+*/
+#define CAN_MOIPR74 (CAN_MO74_IPR)
+
+/** \brief 195C, Message Object Control Register */
+#define CAN_MO74_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001995Cu)
+
+/** Alias (User Manual Name) for CAN_MO74_STAT.
+* To use register names with standard convension, please use CAN_MO74_STAT.
+*/
+#define CAN_MOSTAT74 (CAN_MO74_STAT)
+
+/** \brief 196C, Message Object Acceptance Mask Register */
+#define CAN_MO75_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001996Cu)
+
+/** Alias (User Manual Name) for CAN_MO75_AMR.
+* To use register names with standard convension, please use CAN_MO75_AMR.
+*/
+#define CAN_MOAMR75 (CAN_MO75_AMR)
+
+/** \brief 1978, Message Object Arbitration Register */
+#define CAN_MO75_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019978u)
+
+/** Alias (User Manual Name) for CAN_MO75_AR.
+* To use register names with standard convension, please use CAN_MO75_AR.
+*/
+#define CAN_MOAR75 (CAN_MO75_AR)
+
+/** \brief 197C, Message Object Control Register */
+#define CAN_MO75_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001997Cu)
+
+/** Alias (User Manual Name) for CAN_MO75_CTR.
+* To use register names with standard convension, please use CAN_MO75_CTR.
+*/
+#define CAN_MOCTR75 (CAN_MO75_CTR)
+
+/** \brief 1974, Message Object Data Register High */
+#define CAN_MO75_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019974u)
+
+/** Alias (User Manual Name) for CAN_MO75_DATAH.
+* To use register names with standard convension, please use CAN_MO75_DATAH.
+*/
+#define CAN_MODATAH75 (CAN_MO75_DATAH)
+
+/** \brief 1970, Message Object Data Register Low */
+#define CAN_MO75_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019970u)
+
+/** Alias (User Manual Name) for CAN_MO75_DATAL.
+* To use register names with standard convension, please use CAN_MO75_DATAL.
+*/
+#define CAN_MODATAL75 (CAN_MO75_DATAL)
+
+/** \brief 1960, Message Object Function Control Register */
+#define CAN_MO75_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019960u)
+
+/** Alias (User Manual Name) for CAN_MO75_EDATA0.
+* To use register names with standard convension, please use CAN_MO75_EDATA0.
+*/
+#define CAN_EMO75DATA0 (CAN_MO75_EDATA0)
+
+/** \brief 1964, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO75_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019964u)
+
+/** Alias (User Manual Name) for CAN_MO75_EDATA1.
+* To use register names with standard convension, please use CAN_MO75_EDATA1.
+*/
+#define CAN_EMO75DATA1 (CAN_MO75_EDATA1)
+
+/** \brief 1968, Message Object Interrupt Pointer Register */
+#define CAN_MO75_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019968u)
+
+/** Alias (User Manual Name) for CAN_MO75_EDATA2.
+* To use register names with standard convension, please use CAN_MO75_EDATA2.
+*/
+#define CAN_EMO75DATA2 (CAN_MO75_EDATA2)
+
+/** \brief 196C, Message Object Acceptance Mask Register */
+#define CAN_MO75_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001996Cu)
+
+/** Alias (User Manual Name) for CAN_MO75_EDATA3.
+* To use register names with standard convension, please use CAN_MO75_EDATA3.
+*/
+#define CAN_EMO75DATA3 (CAN_MO75_EDATA3)
+
+/** \brief 1970, Message Object Data Register Low */
+#define CAN_MO75_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019970u)
+
+/** Alias (User Manual Name) for CAN_MO75_EDATA4.
+* To use register names with standard convension, please use CAN_MO75_EDATA4.
+*/
+#define CAN_EMO75DATA4 (CAN_MO75_EDATA4)
+
+/** \brief 1974, Message Object Data Register High */
+#define CAN_MO75_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019974u)
+
+/** Alias (User Manual Name) for CAN_MO75_EDATA5.
+* To use register names with standard convension, please use CAN_MO75_EDATA5.
+*/
+#define CAN_EMO75DATA5 (CAN_MO75_EDATA5)
+
+/** \brief 1978, Message Object Arbitration Register */
+#define CAN_MO75_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019978u)
+
+/** Alias (User Manual Name) for CAN_MO75_EDATA6.
+* To use register names with standard convension, please use CAN_MO75_EDATA6.
+*/
+#define CAN_EMO75DATA6 (CAN_MO75_EDATA6)
+
+/** \brief 1960, Message Object Function Control Register */
+#define CAN_MO75_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019960u)
+
+/** Alias (User Manual Name) for CAN_MO75_FCR.
+* To use register names with standard convension, please use CAN_MO75_FCR.
+*/
+#define CAN_MOFCR75 (CAN_MO75_FCR)
+
+/** \brief 1964, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO75_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019964u)
+
+/** Alias (User Manual Name) for CAN_MO75_FGPR.
+* To use register names with standard convension, please use CAN_MO75_FGPR.
+*/
+#define CAN_MOFGPR75 (CAN_MO75_FGPR)
+
+/** \brief 1968, Message Object Interrupt Pointer Register */
+#define CAN_MO75_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019968u)
+
+/** Alias (User Manual Name) for CAN_MO75_IPR.
+* To use register names with standard convension, please use CAN_MO75_IPR.
+*/
+#define CAN_MOIPR75 (CAN_MO75_IPR)
+
+/** \brief 197C, Message Object Control Register */
+#define CAN_MO75_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001997Cu)
+
+/** Alias (User Manual Name) for CAN_MO75_STAT.
+* To use register names with standard convension, please use CAN_MO75_STAT.
+*/
+#define CAN_MOSTAT75 (CAN_MO75_STAT)
+
+/** \brief 198C, Message Object Acceptance Mask Register */
+#define CAN_MO76_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001998Cu)
+
+/** Alias (User Manual Name) for CAN_MO76_AMR.
+* To use register names with standard convension, please use CAN_MO76_AMR.
+*/
+#define CAN_MOAMR76 (CAN_MO76_AMR)
+
+/** \brief 1998, Message Object Arbitration Register */
+#define CAN_MO76_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019998u)
+
+/** Alias (User Manual Name) for CAN_MO76_AR.
+* To use register names with standard convension, please use CAN_MO76_AR.
+*/
+#define CAN_MOAR76 (CAN_MO76_AR)
+
+/** \brief 199C, Message Object Control Register */
+#define CAN_MO76_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001999Cu)
+
+/** Alias (User Manual Name) for CAN_MO76_CTR.
+* To use register names with standard convension, please use CAN_MO76_CTR.
+*/
+#define CAN_MOCTR76 (CAN_MO76_CTR)
+
+/** \brief 1994, Message Object Data Register High */
+#define CAN_MO76_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019994u)
+
+/** Alias (User Manual Name) for CAN_MO76_DATAH.
+* To use register names with standard convension, please use CAN_MO76_DATAH.
+*/
+#define CAN_MODATAH76 (CAN_MO76_DATAH)
+
+/** \brief 1990, Message Object Data Register Low */
+#define CAN_MO76_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019990u)
+
+/** Alias (User Manual Name) for CAN_MO76_DATAL.
+* To use register names with standard convension, please use CAN_MO76_DATAL.
+*/
+#define CAN_MODATAL76 (CAN_MO76_DATAL)
+
+/** \brief 1980, Message Object Function Control Register */
+#define CAN_MO76_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019980u)
+
+/** Alias (User Manual Name) for CAN_MO76_EDATA0.
+* To use register names with standard convension, please use CAN_MO76_EDATA0.
+*/
+#define CAN_EMO76DATA0 (CAN_MO76_EDATA0)
+
+/** \brief 1984, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO76_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019984u)
+
+/** Alias (User Manual Name) for CAN_MO76_EDATA1.
+* To use register names with standard convension, please use CAN_MO76_EDATA1.
+*/
+#define CAN_EMO76DATA1 (CAN_MO76_EDATA1)
+
+/** \brief 1988, Message Object Interrupt Pointer Register */
+#define CAN_MO76_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019988u)
+
+/** Alias (User Manual Name) for CAN_MO76_EDATA2.
+* To use register names with standard convension, please use CAN_MO76_EDATA2.
+*/
+#define CAN_EMO76DATA2 (CAN_MO76_EDATA2)
+
+/** \brief 198C, Message Object Acceptance Mask Register */
+#define CAN_MO76_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001998Cu)
+
+/** Alias (User Manual Name) for CAN_MO76_EDATA3.
+* To use register names with standard convension, please use CAN_MO76_EDATA3.
+*/
+#define CAN_EMO76DATA3 (CAN_MO76_EDATA3)
+
+/** \brief 1990, Message Object Data Register Low */
+#define CAN_MO76_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019990u)
+
+/** Alias (User Manual Name) for CAN_MO76_EDATA4.
+* To use register names with standard convension, please use CAN_MO76_EDATA4.
+*/
+#define CAN_EMO76DATA4 (CAN_MO76_EDATA4)
+
+/** \brief 1994, Message Object Data Register High */
+#define CAN_MO76_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019994u)
+
+/** Alias (User Manual Name) for CAN_MO76_EDATA5.
+* To use register names with standard convension, please use CAN_MO76_EDATA5.
+*/
+#define CAN_EMO76DATA5 (CAN_MO76_EDATA5)
+
+/** \brief 1998, Message Object Arbitration Register */
+#define CAN_MO76_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019998u)
+
+/** Alias (User Manual Name) for CAN_MO76_EDATA6.
+* To use register names with standard convension, please use CAN_MO76_EDATA6.
+*/
+#define CAN_EMO76DATA6 (CAN_MO76_EDATA6)
+
+/** \brief 1980, Message Object Function Control Register */
+#define CAN_MO76_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019980u)
+
+/** Alias (User Manual Name) for CAN_MO76_FCR.
+* To use register names with standard convension, please use CAN_MO76_FCR.
+*/
+#define CAN_MOFCR76 (CAN_MO76_FCR)
+
+/** \brief 1984, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO76_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019984u)
+
+/** Alias (User Manual Name) for CAN_MO76_FGPR.
+* To use register names with standard convension, please use CAN_MO76_FGPR.
+*/
+#define CAN_MOFGPR76 (CAN_MO76_FGPR)
+
+/** \brief 1988, Message Object Interrupt Pointer Register */
+#define CAN_MO76_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019988u)
+
+/** Alias (User Manual Name) for CAN_MO76_IPR.
+* To use register names with standard convension, please use CAN_MO76_IPR.
+*/
+#define CAN_MOIPR76 (CAN_MO76_IPR)
+
+/** \brief 199C, Message Object Control Register */
+#define CAN_MO76_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001999Cu)
+
+/** Alias (User Manual Name) for CAN_MO76_STAT.
+* To use register names with standard convension, please use CAN_MO76_STAT.
+*/
+#define CAN_MOSTAT76 (CAN_MO76_STAT)
+
+/** \brief 19AC, Message Object Acceptance Mask Register */
+#define CAN_MO77_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00199ACu)
+
+/** Alias (User Manual Name) for CAN_MO77_AMR.
+* To use register names with standard convension, please use CAN_MO77_AMR.
+*/
+#define CAN_MOAMR77 (CAN_MO77_AMR)
+
+/** \brief 19B8, Message Object Arbitration Register */
+#define CAN_MO77_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00199B8u)
+
+/** Alias (User Manual Name) for CAN_MO77_AR.
+* To use register names with standard convension, please use CAN_MO77_AR.
+*/
+#define CAN_MOAR77 (CAN_MO77_AR)
+
+/** \brief 19BC, Message Object Control Register */
+#define CAN_MO77_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00199BCu)
+
+/** Alias (User Manual Name) for CAN_MO77_CTR.
+* To use register names with standard convension, please use CAN_MO77_CTR.
+*/
+#define CAN_MOCTR77 (CAN_MO77_CTR)
+
+/** \brief 19B4, Message Object Data Register High */
+#define CAN_MO77_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00199B4u)
+
+/** Alias (User Manual Name) for CAN_MO77_DATAH.
+* To use register names with standard convension, please use CAN_MO77_DATAH.
+*/
+#define CAN_MODATAH77 (CAN_MO77_DATAH)
+
+/** \brief 19B0, Message Object Data Register Low */
+#define CAN_MO77_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00199B0u)
+
+/** Alias (User Manual Name) for CAN_MO77_DATAL.
+* To use register names with standard convension, please use CAN_MO77_DATAL.
+*/
+#define CAN_MODATAL77 (CAN_MO77_DATAL)
+
+/** \brief 19A0, Message Object Function Control Register */
+#define CAN_MO77_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00199A0u)
+
+/** Alias (User Manual Name) for CAN_MO77_EDATA0.
+* To use register names with standard convension, please use CAN_MO77_EDATA0.
+*/
+#define CAN_EMO77DATA0 (CAN_MO77_EDATA0)
+
+/** \brief 19A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO77_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00199A4u)
+
+/** Alias (User Manual Name) for CAN_MO77_EDATA1.
+* To use register names with standard convension, please use CAN_MO77_EDATA1.
+*/
+#define CAN_EMO77DATA1 (CAN_MO77_EDATA1)
+
+/** \brief 19A8, Message Object Interrupt Pointer Register */
+#define CAN_MO77_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00199A8u)
+
+/** Alias (User Manual Name) for CAN_MO77_EDATA2.
+* To use register names with standard convension, please use CAN_MO77_EDATA2.
+*/
+#define CAN_EMO77DATA2 (CAN_MO77_EDATA2)
+
+/** \brief 19AC, Message Object Acceptance Mask Register */
+#define CAN_MO77_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00199ACu)
+
+/** Alias (User Manual Name) for CAN_MO77_EDATA3.
+* To use register names with standard convension, please use CAN_MO77_EDATA3.
+*/
+#define CAN_EMO77DATA3 (CAN_MO77_EDATA3)
+
+/** \brief 19B0, Message Object Data Register Low */
+#define CAN_MO77_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00199B0u)
+
+/** Alias (User Manual Name) for CAN_MO77_EDATA4.
+* To use register names with standard convension, please use CAN_MO77_EDATA4.
+*/
+#define CAN_EMO77DATA4 (CAN_MO77_EDATA4)
+
+/** \brief 19B4, Message Object Data Register High */
+#define CAN_MO77_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00199B4u)
+
+/** Alias (User Manual Name) for CAN_MO77_EDATA5.
+* To use register names with standard convension, please use CAN_MO77_EDATA5.
+*/
+#define CAN_EMO77DATA5 (CAN_MO77_EDATA5)
+
+/** \brief 19B8, Message Object Arbitration Register */
+#define CAN_MO77_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00199B8u)
+
+/** Alias (User Manual Name) for CAN_MO77_EDATA6.
+* To use register names with standard convension, please use CAN_MO77_EDATA6.
+*/
+#define CAN_EMO77DATA6 (CAN_MO77_EDATA6)
+
+/** \brief 19A0, Message Object Function Control Register */
+#define CAN_MO77_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00199A0u)
+
+/** Alias (User Manual Name) for CAN_MO77_FCR.
+* To use register names with standard convension, please use CAN_MO77_FCR.
+*/
+#define CAN_MOFCR77 (CAN_MO77_FCR)
+
+/** \brief 19A4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO77_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00199A4u)
+
+/** Alias (User Manual Name) for CAN_MO77_FGPR.
+* To use register names with standard convension, please use CAN_MO77_FGPR.
+*/
+#define CAN_MOFGPR77 (CAN_MO77_FGPR)
+
+/** \brief 19A8, Message Object Interrupt Pointer Register */
+#define CAN_MO77_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00199A8u)
+
+/** Alias (User Manual Name) for CAN_MO77_IPR.
+* To use register names with standard convension, please use CAN_MO77_IPR.
+*/
+#define CAN_MOIPR77 (CAN_MO77_IPR)
+
+/** \brief 19BC, Message Object Control Register */
+#define CAN_MO77_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00199BCu)
+
+/** Alias (User Manual Name) for CAN_MO77_STAT.
+* To use register names with standard convension, please use CAN_MO77_STAT.
+*/
+#define CAN_MOSTAT77 (CAN_MO77_STAT)
+
+/** \brief 19CC, Message Object Acceptance Mask Register */
+#define CAN_MO78_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00199CCu)
+
+/** Alias (User Manual Name) for CAN_MO78_AMR.
+* To use register names with standard convension, please use CAN_MO78_AMR.
+*/
+#define CAN_MOAMR78 (CAN_MO78_AMR)
+
+/** \brief 19D8, Message Object Arbitration Register */
+#define CAN_MO78_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00199D8u)
+
+/** Alias (User Manual Name) for CAN_MO78_AR.
+* To use register names with standard convension, please use CAN_MO78_AR.
+*/
+#define CAN_MOAR78 (CAN_MO78_AR)
+
+/** \brief 19DC, Message Object Control Register */
+#define CAN_MO78_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00199DCu)
+
+/** Alias (User Manual Name) for CAN_MO78_CTR.
+* To use register names with standard convension, please use CAN_MO78_CTR.
+*/
+#define CAN_MOCTR78 (CAN_MO78_CTR)
+
+/** \brief 19D4, Message Object Data Register High */
+#define CAN_MO78_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00199D4u)
+
+/** Alias (User Manual Name) for CAN_MO78_DATAH.
+* To use register names with standard convension, please use CAN_MO78_DATAH.
+*/
+#define CAN_MODATAH78 (CAN_MO78_DATAH)
+
+/** \brief 19D0, Message Object Data Register Low */
+#define CAN_MO78_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00199D0u)
+
+/** Alias (User Manual Name) for CAN_MO78_DATAL.
+* To use register names with standard convension, please use CAN_MO78_DATAL.
+*/
+#define CAN_MODATAL78 (CAN_MO78_DATAL)
+
+/** \brief 19C0, Message Object Function Control Register */
+#define CAN_MO78_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00199C0u)
+
+/** Alias (User Manual Name) for CAN_MO78_EDATA0.
+* To use register names with standard convension, please use CAN_MO78_EDATA0.
+*/
+#define CAN_EMO78DATA0 (CAN_MO78_EDATA0)
+
+/** \brief 19C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO78_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00199C4u)
+
+/** Alias (User Manual Name) for CAN_MO78_EDATA1.
+* To use register names with standard convension, please use CAN_MO78_EDATA1.
+*/
+#define CAN_EMO78DATA1 (CAN_MO78_EDATA1)
+
+/** \brief 19C8, Message Object Interrupt Pointer Register */
+#define CAN_MO78_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00199C8u)
+
+/** Alias (User Manual Name) for CAN_MO78_EDATA2.
+* To use register names with standard convension, please use CAN_MO78_EDATA2.
+*/
+#define CAN_EMO78DATA2 (CAN_MO78_EDATA2)
+
+/** \brief 19CC, Message Object Acceptance Mask Register */
+#define CAN_MO78_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00199CCu)
+
+/** Alias (User Manual Name) for CAN_MO78_EDATA3.
+* To use register names with standard convension, please use CAN_MO78_EDATA3.
+*/
+#define CAN_EMO78DATA3 (CAN_MO78_EDATA3)
+
+/** \brief 19D0, Message Object Data Register Low */
+#define CAN_MO78_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00199D0u)
+
+/** Alias (User Manual Name) for CAN_MO78_EDATA4.
+* To use register names with standard convension, please use CAN_MO78_EDATA4.
+*/
+#define CAN_EMO78DATA4 (CAN_MO78_EDATA4)
+
+/** \brief 19D4, Message Object Data Register High */
+#define CAN_MO78_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00199D4u)
+
+/** Alias (User Manual Name) for CAN_MO78_EDATA5.
+* To use register names with standard convension, please use CAN_MO78_EDATA5.
+*/
+#define CAN_EMO78DATA5 (CAN_MO78_EDATA5)
+
+/** \brief 19D8, Message Object Arbitration Register */
+#define CAN_MO78_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00199D8u)
+
+/** Alias (User Manual Name) for CAN_MO78_EDATA6.
+* To use register names with standard convension, please use CAN_MO78_EDATA6.
+*/
+#define CAN_EMO78DATA6 (CAN_MO78_EDATA6)
+
+/** \brief 19C0, Message Object Function Control Register */
+#define CAN_MO78_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00199C0u)
+
+/** Alias (User Manual Name) for CAN_MO78_FCR.
+* To use register names with standard convension, please use CAN_MO78_FCR.
+*/
+#define CAN_MOFCR78 (CAN_MO78_FCR)
+
+/** \brief 19C4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO78_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00199C4u)
+
+/** Alias (User Manual Name) for CAN_MO78_FGPR.
+* To use register names with standard convension, please use CAN_MO78_FGPR.
+*/
+#define CAN_MOFGPR78 (CAN_MO78_FGPR)
+
+/** \brief 19C8, Message Object Interrupt Pointer Register */
+#define CAN_MO78_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00199C8u)
+
+/** Alias (User Manual Name) for CAN_MO78_IPR.
+* To use register names with standard convension, please use CAN_MO78_IPR.
+*/
+#define CAN_MOIPR78 (CAN_MO78_IPR)
+
+/** \brief 19DC, Message Object Control Register */
+#define CAN_MO78_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00199DCu)
+
+/** Alias (User Manual Name) for CAN_MO78_STAT.
+* To use register names with standard convension, please use CAN_MO78_STAT.
+*/
+#define CAN_MOSTAT78 (CAN_MO78_STAT)
+
+/** \brief 19EC, Message Object Acceptance Mask Register */
+#define CAN_MO79_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00199ECu)
+
+/** Alias (User Manual Name) for CAN_MO79_AMR.
+* To use register names with standard convension, please use CAN_MO79_AMR.
+*/
+#define CAN_MOAMR79 (CAN_MO79_AMR)
+
+/** \brief 19F8, Message Object Arbitration Register */
+#define CAN_MO79_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00199F8u)
+
+/** Alias (User Manual Name) for CAN_MO79_AR.
+* To use register names with standard convension, please use CAN_MO79_AR.
+*/
+#define CAN_MOAR79 (CAN_MO79_AR)
+
+/** \brief 19FC, Message Object Control Register */
+#define CAN_MO79_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00199FCu)
+
+/** Alias (User Manual Name) for CAN_MO79_CTR.
+* To use register names with standard convension, please use CAN_MO79_CTR.
+*/
+#define CAN_MOCTR79 (CAN_MO79_CTR)
+
+/** \brief 19F4, Message Object Data Register High */
+#define CAN_MO79_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00199F4u)
+
+/** Alias (User Manual Name) for CAN_MO79_DATAH.
+* To use register names with standard convension, please use CAN_MO79_DATAH.
+*/
+#define CAN_MODATAH79 (CAN_MO79_DATAH)
+
+/** \brief 19F0, Message Object Data Register Low */
+#define CAN_MO79_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00199F0u)
+
+/** Alias (User Manual Name) for CAN_MO79_DATAL.
+* To use register names with standard convension, please use CAN_MO79_DATAL.
+*/
+#define CAN_MODATAL79 (CAN_MO79_DATAL)
+
+/** \brief 19E0, Message Object Function Control Register */
+#define CAN_MO79_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00199E0u)
+
+/** Alias (User Manual Name) for CAN_MO79_EDATA0.
+* To use register names with standard convension, please use CAN_MO79_EDATA0.
+*/
+#define CAN_EMO79DATA0 (CAN_MO79_EDATA0)
+
+/** \brief 19E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO79_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00199E4u)
+
+/** Alias (User Manual Name) for CAN_MO79_EDATA1.
+* To use register names with standard convension, please use CAN_MO79_EDATA1.
+*/
+#define CAN_EMO79DATA1 (CAN_MO79_EDATA1)
+
+/** \brief 19E8, Message Object Interrupt Pointer Register */
+#define CAN_MO79_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00199E8u)
+
+/** Alias (User Manual Name) for CAN_MO79_EDATA2.
+* To use register names with standard convension, please use CAN_MO79_EDATA2.
+*/
+#define CAN_EMO79DATA2 (CAN_MO79_EDATA2)
+
+/** \brief 19EC, Message Object Acceptance Mask Register */
+#define CAN_MO79_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00199ECu)
+
+/** Alias (User Manual Name) for CAN_MO79_EDATA3.
+* To use register names with standard convension, please use CAN_MO79_EDATA3.
+*/
+#define CAN_EMO79DATA3 (CAN_MO79_EDATA3)
+
+/** \brief 19F0, Message Object Data Register Low */
+#define CAN_MO79_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00199F0u)
+
+/** Alias (User Manual Name) for CAN_MO79_EDATA4.
+* To use register names with standard convension, please use CAN_MO79_EDATA4.
+*/
+#define CAN_EMO79DATA4 (CAN_MO79_EDATA4)
+
+/** \brief 19F4, Message Object Data Register High */
+#define CAN_MO79_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00199F4u)
+
+/** Alias (User Manual Name) for CAN_MO79_EDATA5.
+* To use register names with standard convension, please use CAN_MO79_EDATA5.
+*/
+#define CAN_EMO79DATA5 (CAN_MO79_EDATA5)
+
+/** \brief 19F8, Message Object Arbitration Register */
+#define CAN_MO79_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00199F8u)
+
+/** Alias (User Manual Name) for CAN_MO79_EDATA6.
+* To use register names with standard convension, please use CAN_MO79_EDATA6.
+*/
+#define CAN_EMO79DATA6 (CAN_MO79_EDATA6)
+
+/** \brief 19E0, Message Object Function Control Register */
+#define CAN_MO79_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00199E0u)
+
+/** Alias (User Manual Name) for CAN_MO79_FCR.
+* To use register names with standard convension, please use CAN_MO79_FCR.
+*/
+#define CAN_MOFCR79 (CAN_MO79_FCR)
+
+/** \brief 19E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO79_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00199E4u)
+
+/** Alias (User Manual Name) for CAN_MO79_FGPR.
+* To use register names with standard convension, please use CAN_MO79_FGPR.
+*/
+#define CAN_MOFGPR79 (CAN_MO79_FGPR)
+
+/** \brief 19E8, Message Object Interrupt Pointer Register */
+#define CAN_MO79_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00199E8u)
+
+/** Alias (User Manual Name) for CAN_MO79_IPR.
+* To use register names with standard convension, please use CAN_MO79_IPR.
+*/
+#define CAN_MOIPR79 (CAN_MO79_IPR)
+
+/** \brief 19FC, Message Object Control Register */
+#define CAN_MO79_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00199FCu)
+
+/** Alias (User Manual Name) for CAN_MO79_STAT.
+* To use register names with standard convension, please use CAN_MO79_STAT.
+*/
+#define CAN_MOSTAT79 (CAN_MO79_STAT)
+
+/** \brief 10EC, Message Object Acceptance Mask Register */
+#define CAN_MO7_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00190ECu)
+
+/** Alias (User Manual Name) for CAN_MO7_AMR.
+* To use register names with standard convension, please use CAN_MO7_AMR.
+*/
+#define CAN_MOAMR7 (CAN_MO7_AMR)
+
+/** \brief 10F8, Message Object Arbitration Register */
+#define CAN_MO7_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00190F8u)
+
+/** Alias (User Manual Name) for CAN_MO7_AR.
+* To use register names with standard convension, please use CAN_MO7_AR.
+*/
+#define CAN_MOAR7 (CAN_MO7_AR)
+
+/** \brief 10FC, Message Object Control Register */
+#define CAN_MO7_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00190FCu)
+
+/** Alias (User Manual Name) for CAN_MO7_CTR.
+* To use register names with standard convension, please use CAN_MO7_CTR.
+*/
+#define CAN_MOCTR7 (CAN_MO7_CTR)
+
+/** \brief 10F4, Message Object Data Register High */
+#define CAN_MO7_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00190F4u)
+
+/** Alias (User Manual Name) for CAN_MO7_DATAH.
+* To use register names with standard convension, please use CAN_MO7_DATAH.
+*/
+#define CAN_MODATAH7 (CAN_MO7_DATAH)
+
+/** \brief 10F0, Message Object Data Register Low */
+#define CAN_MO7_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00190F0u)
+
+/** Alias (User Manual Name) for CAN_MO7_DATAL.
+* To use register names with standard convension, please use CAN_MO7_DATAL.
+*/
+#define CAN_MODATAL7 (CAN_MO7_DATAL)
+
+/** \brief 10E0, Message Object Function Control Register */
+#define CAN_MO7_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00190E0u)
+
+/** Alias (User Manual Name) for CAN_MO7_EDATA0.
+* To use register names with standard convension, please use CAN_MO7_EDATA0.
+*/
+#define CAN_EMO7DATA0 (CAN_MO7_EDATA0)
+
+/** \brief 10E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO7_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00190E4u)
+
+/** Alias (User Manual Name) for CAN_MO7_EDATA1.
+* To use register names with standard convension, please use CAN_MO7_EDATA1.
+*/
+#define CAN_EMO7DATA1 (CAN_MO7_EDATA1)
+
+/** \brief 10E8, Message Object Interrupt Pointer Register */
+#define CAN_MO7_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00190E8u)
+
+/** Alias (User Manual Name) for CAN_MO7_EDATA2.
+* To use register names with standard convension, please use CAN_MO7_EDATA2.
+*/
+#define CAN_EMO7DATA2 (CAN_MO7_EDATA2)
+
+/** \brief 10EC, Message Object Acceptance Mask Register */
+#define CAN_MO7_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00190ECu)
+
+/** Alias (User Manual Name) for CAN_MO7_EDATA3.
+* To use register names with standard convension, please use CAN_MO7_EDATA3.
+*/
+#define CAN_EMO7DATA3 (CAN_MO7_EDATA3)
+
+/** \brief 10F0, Message Object Data Register Low */
+#define CAN_MO7_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00190F0u)
+
+/** Alias (User Manual Name) for CAN_MO7_EDATA4.
+* To use register names with standard convension, please use CAN_MO7_EDATA4.
+*/
+#define CAN_EMO7DATA4 (CAN_MO7_EDATA4)
+
+/** \brief 10F4, Message Object Data Register High */
+#define CAN_MO7_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00190F4u)
+
+/** Alias (User Manual Name) for CAN_MO7_EDATA5.
+* To use register names with standard convension, please use CAN_MO7_EDATA5.
+*/
+#define CAN_EMO7DATA5 (CAN_MO7_EDATA5)
+
+/** \brief 10F8, Message Object Arbitration Register */
+#define CAN_MO7_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00190F8u)
+
+/** Alias (User Manual Name) for CAN_MO7_EDATA6.
+* To use register names with standard convension, please use CAN_MO7_EDATA6.
+*/
+#define CAN_EMO7DATA6 (CAN_MO7_EDATA6)
+
+/** \brief 10E0, Message Object Function Control Register */
+#define CAN_MO7_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00190E0u)
+
+/** Alias (User Manual Name) for CAN_MO7_FCR.
+* To use register names with standard convension, please use CAN_MO7_FCR.
+*/
+#define CAN_MOFCR7 (CAN_MO7_FCR)
+
+/** \brief 10E4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO7_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00190E4u)
+
+/** Alias (User Manual Name) for CAN_MO7_FGPR.
+* To use register names with standard convension, please use CAN_MO7_FGPR.
+*/
+#define CAN_MOFGPR7 (CAN_MO7_FGPR)
+
+/** \brief 10E8, Message Object Interrupt Pointer Register */
+#define CAN_MO7_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00190E8u)
+
+/** Alias (User Manual Name) for CAN_MO7_IPR.
+* To use register names with standard convension, please use CAN_MO7_IPR.
+*/
+#define CAN_MOIPR7 (CAN_MO7_IPR)
+
+/** \brief 10FC, Message Object Control Register */
+#define CAN_MO7_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00190FCu)
+
+/** Alias (User Manual Name) for CAN_MO7_STAT.
+* To use register names with standard convension, please use CAN_MO7_STAT.
+*/
+#define CAN_MOSTAT7 (CAN_MO7_STAT)
+
+/** \brief 1A0C, Message Object Acceptance Mask Register */
+#define CAN_MO80_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019A0Cu)
+
+/** Alias (User Manual Name) for CAN_MO80_AMR.
+* To use register names with standard convension, please use CAN_MO80_AMR.
+*/
+#define CAN_MOAMR80 (CAN_MO80_AMR)
+
+/** \brief 1A18, Message Object Arbitration Register */
+#define CAN_MO80_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019A18u)
+
+/** Alias (User Manual Name) for CAN_MO80_AR.
+* To use register names with standard convension, please use CAN_MO80_AR.
+*/
+#define CAN_MOAR80 (CAN_MO80_AR)
+
+/** \brief 1A1C, Message Object Control Register */
+#define CAN_MO80_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019A1Cu)
+
+/** Alias (User Manual Name) for CAN_MO80_CTR.
+* To use register names with standard convension, please use CAN_MO80_CTR.
+*/
+#define CAN_MOCTR80 (CAN_MO80_CTR)
+
+/** \brief 1A14, Message Object Data Register High */
+#define CAN_MO80_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019A14u)
+
+/** Alias (User Manual Name) for CAN_MO80_DATAH.
+* To use register names with standard convension, please use CAN_MO80_DATAH.
+*/
+#define CAN_MODATAH80 (CAN_MO80_DATAH)
+
+/** \brief 1A10, Message Object Data Register Low */
+#define CAN_MO80_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019A10u)
+
+/** Alias (User Manual Name) for CAN_MO80_DATAL.
+* To use register names with standard convension, please use CAN_MO80_DATAL.
+*/
+#define CAN_MODATAL80 (CAN_MO80_DATAL)
+
+/** \brief 1A00, Message Object Function Control Register */
+#define CAN_MO80_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019A00u)
+
+/** Alias (User Manual Name) for CAN_MO80_EDATA0.
+* To use register names with standard convension, please use CAN_MO80_EDATA0.
+*/
+#define CAN_EMO80DATA0 (CAN_MO80_EDATA0)
+
+/** \brief 1A04, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO80_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019A04u)
+
+/** Alias (User Manual Name) for CAN_MO80_EDATA1.
+* To use register names with standard convension, please use CAN_MO80_EDATA1.
+*/
+#define CAN_EMO80DATA1 (CAN_MO80_EDATA1)
+
+/** \brief 1A08, Message Object Interrupt Pointer Register */
+#define CAN_MO80_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019A08u)
+
+/** Alias (User Manual Name) for CAN_MO80_EDATA2.
+* To use register names with standard convension, please use CAN_MO80_EDATA2.
+*/
+#define CAN_EMO80DATA2 (CAN_MO80_EDATA2)
+
+/** \brief 1A0C, Message Object Acceptance Mask Register */
+#define CAN_MO80_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019A0Cu)
+
+/** Alias (User Manual Name) for CAN_MO80_EDATA3.
+* To use register names with standard convension, please use CAN_MO80_EDATA3.
+*/
+#define CAN_EMO80DATA3 (CAN_MO80_EDATA3)
+
+/** \brief 1A10, Message Object Data Register Low */
+#define CAN_MO80_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019A10u)
+
+/** Alias (User Manual Name) for CAN_MO80_EDATA4.
+* To use register names with standard convension, please use CAN_MO80_EDATA4.
+*/
+#define CAN_EMO80DATA4 (CAN_MO80_EDATA4)
+
+/** \brief 1A14, Message Object Data Register High */
+#define CAN_MO80_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019A14u)
+
+/** Alias (User Manual Name) for CAN_MO80_EDATA5.
+* To use register names with standard convension, please use CAN_MO80_EDATA5.
+*/
+#define CAN_EMO80DATA5 (CAN_MO80_EDATA5)
+
+/** \brief 1A18, Message Object Arbitration Register */
+#define CAN_MO80_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019A18u)
+
+/** Alias (User Manual Name) for CAN_MO80_EDATA6.
+* To use register names with standard convension, please use CAN_MO80_EDATA6.
+*/
+#define CAN_EMO80DATA6 (CAN_MO80_EDATA6)
+
+/** \brief 1A00, Message Object Function Control Register */
+#define CAN_MO80_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019A00u)
+
+/** Alias (User Manual Name) for CAN_MO80_FCR.
+* To use register names with standard convension, please use CAN_MO80_FCR.
+*/
+#define CAN_MOFCR80 (CAN_MO80_FCR)
+
+/** \brief 1A04, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO80_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019A04u)
+
+/** Alias (User Manual Name) for CAN_MO80_FGPR.
+* To use register names with standard convension, please use CAN_MO80_FGPR.
+*/
+#define CAN_MOFGPR80 (CAN_MO80_FGPR)
+
+/** \brief 1A08, Message Object Interrupt Pointer Register */
+#define CAN_MO80_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019A08u)
+
+/** Alias (User Manual Name) for CAN_MO80_IPR.
+* To use register names with standard convension, please use CAN_MO80_IPR.
+*/
+#define CAN_MOIPR80 (CAN_MO80_IPR)
+
+/** \brief 1A1C, Message Object Control Register */
+#define CAN_MO80_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019A1Cu)
+
+/** Alias (User Manual Name) for CAN_MO80_STAT.
+* To use register names with standard convension, please use CAN_MO80_STAT.
+*/
+#define CAN_MOSTAT80 (CAN_MO80_STAT)
+
+/** \brief 1A2C, Message Object Acceptance Mask Register */
+#define CAN_MO81_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019A2Cu)
+
+/** Alias (User Manual Name) for CAN_MO81_AMR.
+* To use register names with standard convension, please use CAN_MO81_AMR.
+*/
+#define CAN_MOAMR81 (CAN_MO81_AMR)
+
+/** \brief 1A38, Message Object Arbitration Register */
+#define CAN_MO81_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019A38u)
+
+/** Alias (User Manual Name) for CAN_MO81_AR.
+* To use register names with standard convension, please use CAN_MO81_AR.
+*/
+#define CAN_MOAR81 (CAN_MO81_AR)
+
+/** \brief 1A3C, Message Object Control Register */
+#define CAN_MO81_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019A3Cu)
+
+/** Alias (User Manual Name) for CAN_MO81_CTR.
+* To use register names with standard convension, please use CAN_MO81_CTR.
+*/
+#define CAN_MOCTR81 (CAN_MO81_CTR)
+
+/** \brief 1A34, Message Object Data Register High */
+#define CAN_MO81_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019A34u)
+
+/** Alias (User Manual Name) for CAN_MO81_DATAH.
+* To use register names with standard convension, please use CAN_MO81_DATAH.
+*/
+#define CAN_MODATAH81 (CAN_MO81_DATAH)
+
+/** \brief 1A30, Message Object Data Register Low */
+#define CAN_MO81_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019A30u)
+
+/** Alias (User Manual Name) for CAN_MO81_DATAL.
+* To use register names with standard convension, please use CAN_MO81_DATAL.
+*/
+#define CAN_MODATAL81 (CAN_MO81_DATAL)
+
+/** \brief 1A20, Message Object Function Control Register */
+#define CAN_MO81_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019A20u)
+
+/** Alias (User Manual Name) for CAN_MO81_EDATA0.
+* To use register names with standard convension, please use CAN_MO81_EDATA0.
+*/
+#define CAN_EMO81DATA0 (CAN_MO81_EDATA0)
+
+/** \brief 1A24, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO81_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019A24u)
+
+/** Alias (User Manual Name) for CAN_MO81_EDATA1.
+* To use register names with standard convension, please use CAN_MO81_EDATA1.
+*/
+#define CAN_EMO81DATA1 (CAN_MO81_EDATA1)
+
+/** \brief 1A28, Message Object Interrupt Pointer Register */
+#define CAN_MO81_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019A28u)
+
+/** Alias (User Manual Name) for CAN_MO81_EDATA2.
+* To use register names with standard convension, please use CAN_MO81_EDATA2.
+*/
+#define CAN_EMO81DATA2 (CAN_MO81_EDATA2)
+
+/** \brief 1A2C, Message Object Acceptance Mask Register */
+#define CAN_MO81_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019A2Cu)
+
+/** Alias (User Manual Name) for CAN_MO81_EDATA3.
+* To use register names with standard convension, please use CAN_MO81_EDATA3.
+*/
+#define CAN_EMO81DATA3 (CAN_MO81_EDATA3)
+
+/** \brief 1A30, Message Object Data Register Low */
+#define CAN_MO81_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019A30u)
+
+/** Alias (User Manual Name) for CAN_MO81_EDATA4.
+* To use register names with standard convension, please use CAN_MO81_EDATA4.
+*/
+#define CAN_EMO81DATA4 (CAN_MO81_EDATA4)
+
+/** \brief 1A34, Message Object Data Register High */
+#define CAN_MO81_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019A34u)
+
+/** Alias (User Manual Name) for CAN_MO81_EDATA5.
+* To use register names with standard convension, please use CAN_MO81_EDATA5.
+*/
+#define CAN_EMO81DATA5 (CAN_MO81_EDATA5)
+
+/** \brief 1A38, Message Object Arbitration Register */
+#define CAN_MO81_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019A38u)
+
+/** Alias (User Manual Name) for CAN_MO81_EDATA6.
+* To use register names with standard convension, please use CAN_MO81_EDATA6.
+*/
+#define CAN_EMO81DATA6 (CAN_MO81_EDATA6)
+
+/** \brief 1A20, Message Object Function Control Register */
+#define CAN_MO81_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019A20u)
+
+/** Alias (User Manual Name) for CAN_MO81_FCR.
+* To use register names with standard convension, please use CAN_MO81_FCR.
+*/
+#define CAN_MOFCR81 (CAN_MO81_FCR)
+
+/** \brief 1A24, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO81_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019A24u)
+
+/** Alias (User Manual Name) for CAN_MO81_FGPR.
+* To use register names with standard convension, please use CAN_MO81_FGPR.
+*/
+#define CAN_MOFGPR81 (CAN_MO81_FGPR)
+
+/** \brief 1A28, Message Object Interrupt Pointer Register */
+#define CAN_MO81_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019A28u)
+
+/** Alias (User Manual Name) for CAN_MO81_IPR.
+* To use register names with standard convension, please use CAN_MO81_IPR.
+*/
+#define CAN_MOIPR81 (CAN_MO81_IPR)
+
+/** \brief 1A3C, Message Object Control Register */
+#define CAN_MO81_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019A3Cu)
+
+/** Alias (User Manual Name) for CAN_MO81_STAT.
+* To use register names with standard convension, please use CAN_MO81_STAT.
+*/
+#define CAN_MOSTAT81 (CAN_MO81_STAT)
+
+/** \brief 1A4C, Message Object Acceptance Mask Register */
+#define CAN_MO82_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019A4Cu)
+
+/** Alias (User Manual Name) for CAN_MO82_AMR.
+* To use register names with standard convension, please use CAN_MO82_AMR.
+*/
+#define CAN_MOAMR82 (CAN_MO82_AMR)
+
+/** \brief 1A58, Message Object Arbitration Register */
+#define CAN_MO82_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019A58u)
+
+/** Alias (User Manual Name) for CAN_MO82_AR.
+* To use register names with standard convension, please use CAN_MO82_AR.
+*/
+#define CAN_MOAR82 (CAN_MO82_AR)
+
+/** \brief 1A5C, Message Object Control Register */
+#define CAN_MO82_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019A5Cu)
+
+/** Alias (User Manual Name) for CAN_MO82_CTR.
+* To use register names with standard convension, please use CAN_MO82_CTR.
+*/
+#define CAN_MOCTR82 (CAN_MO82_CTR)
+
+/** \brief 1A54, Message Object Data Register High */
+#define CAN_MO82_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019A54u)
+
+/** Alias (User Manual Name) for CAN_MO82_DATAH.
+* To use register names with standard convension, please use CAN_MO82_DATAH.
+*/
+#define CAN_MODATAH82 (CAN_MO82_DATAH)
+
+/** \brief 1A50, Message Object Data Register Low */
+#define CAN_MO82_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019A50u)
+
+/** Alias (User Manual Name) for CAN_MO82_DATAL.
+* To use register names with standard convension, please use CAN_MO82_DATAL.
+*/
+#define CAN_MODATAL82 (CAN_MO82_DATAL)
+
+/** \brief 1A40, Message Object Function Control Register */
+#define CAN_MO82_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019A40u)
+
+/** Alias (User Manual Name) for CAN_MO82_EDATA0.
+* To use register names with standard convension, please use CAN_MO82_EDATA0.
+*/
+#define CAN_EMO82DATA0 (CAN_MO82_EDATA0)
+
+/** \brief 1A44, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO82_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019A44u)
+
+/** Alias (User Manual Name) for CAN_MO82_EDATA1.
+* To use register names with standard convension, please use CAN_MO82_EDATA1.
+*/
+#define CAN_EMO82DATA1 (CAN_MO82_EDATA1)
+
+/** \brief 1A48, Message Object Interrupt Pointer Register */
+#define CAN_MO82_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019A48u)
+
+/** Alias (User Manual Name) for CAN_MO82_EDATA2.
+* To use register names with standard convension, please use CAN_MO82_EDATA2.
+*/
+#define CAN_EMO82DATA2 (CAN_MO82_EDATA2)
+
+/** \brief 1A4C, Message Object Acceptance Mask Register */
+#define CAN_MO82_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019A4Cu)
+
+/** Alias (User Manual Name) for CAN_MO82_EDATA3.
+* To use register names with standard convension, please use CAN_MO82_EDATA3.
+*/
+#define CAN_EMO82DATA3 (CAN_MO82_EDATA3)
+
+/** \brief 1A50, Message Object Data Register Low */
+#define CAN_MO82_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019A50u)
+
+/** Alias (User Manual Name) for CAN_MO82_EDATA4.
+* To use register names with standard convension, please use CAN_MO82_EDATA4.
+*/
+#define CAN_EMO82DATA4 (CAN_MO82_EDATA4)
+
+/** \brief 1A54, Message Object Data Register High */
+#define CAN_MO82_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019A54u)
+
+/** Alias (User Manual Name) for CAN_MO82_EDATA5.
+* To use register names with standard convension, please use CAN_MO82_EDATA5.
+*/
+#define CAN_EMO82DATA5 (CAN_MO82_EDATA5)
+
+/** \brief 1A58, Message Object Arbitration Register */
+#define CAN_MO82_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019A58u)
+
+/** Alias (User Manual Name) for CAN_MO82_EDATA6.
+* To use register names with standard convension, please use CAN_MO82_EDATA6.
+*/
+#define CAN_EMO82DATA6 (CAN_MO82_EDATA6)
+
+/** \brief 1A40, Message Object Function Control Register */
+#define CAN_MO82_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019A40u)
+
+/** Alias (User Manual Name) for CAN_MO82_FCR.
+* To use register names with standard convension, please use CAN_MO82_FCR.
+*/
+#define CAN_MOFCR82 (CAN_MO82_FCR)
+
+/** \brief 1A44, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO82_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019A44u)
+
+/** Alias (User Manual Name) for CAN_MO82_FGPR.
+* To use register names with standard convension, please use CAN_MO82_FGPR.
+*/
+#define CAN_MOFGPR82 (CAN_MO82_FGPR)
+
+/** \brief 1A48, Message Object Interrupt Pointer Register */
+#define CAN_MO82_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019A48u)
+
+/** Alias (User Manual Name) for CAN_MO82_IPR.
+* To use register names with standard convension, please use CAN_MO82_IPR.
+*/
+#define CAN_MOIPR82 (CAN_MO82_IPR)
+
+/** \brief 1A5C, Message Object Control Register */
+#define CAN_MO82_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019A5Cu)
+
+/** Alias (User Manual Name) for CAN_MO82_STAT.
+* To use register names with standard convension, please use CAN_MO82_STAT.
+*/
+#define CAN_MOSTAT82 (CAN_MO82_STAT)
+
+/** \brief 1A6C, Message Object Acceptance Mask Register */
+#define CAN_MO83_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019A6Cu)
+
+/** Alias (User Manual Name) for CAN_MO83_AMR.
+* To use register names with standard convension, please use CAN_MO83_AMR.
+*/
+#define CAN_MOAMR83 (CAN_MO83_AMR)
+
+/** \brief 1A78, Message Object Arbitration Register */
+#define CAN_MO83_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019A78u)
+
+/** Alias (User Manual Name) for CAN_MO83_AR.
+* To use register names with standard convension, please use CAN_MO83_AR.
+*/
+#define CAN_MOAR83 (CAN_MO83_AR)
+
+/** \brief 1A7C, Message Object Control Register */
+#define CAN_MO83_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019A7Cu)
+
+/** Alias (User Manual Name) for CAN_MO83_CTR.
+* To use register names with standard convension, please use CAN_MO83_CTR.
+*/
+#define CAN_MOCTR83 (CAN_MO83_CTR)
+
+/** \brief 1A74, Message Object Data Register High */
+#define CAN_MO83_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019A74u)
+
+/** Alias (User Manual Name) for CAN_MO83_DATAH.
+* To use register names with standard convension, please use CAN_MO83_DATAH.
+*/
+#define CAN_MODATAH83 (CAN_MO83_DATAH)
+
+/** \brief 1A70, Message Object Data Register Low */
+#define CAN_MO83_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019A70u)
+
+/** Alias (User Manual Name) for CAN_MO83_DATAL.
+* To use register names with standard convension, please use CAN_MO83_DATAL.
+*/
+#define CAN_MODATAL83 (CAN_MO83_DATAL)
+
+/** \brief 1A60, Message Object Function Control Register */
+#define CAN_MO83_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019A60u)
+
+/** Alias (User Manual Name) for CAN_MO83_EDATA0.
+* To use register names with standard convension, please use CAN_MO83_EDATA0.
+*/
+#define CAN_EMO83DATA0 (CAN_MO83_EDATA0)
+
+/** \brief 1A64, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO83_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019A64u)
+
+/** Alias (User Manual Name) for CAN_MO83_EDATA1.
+* To use register names with standard convension, please use CAN_MO83_EDATA1.
+*/
+#define CAN_EMO83DATA1 (CAN_MO83_EDATA1)
+
+/** \brief 1A68, Message Object Interrupt Pointer Register */
+#define CAN_MO83_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019A68u)
+
+/** Alias (User Manual Name) for CAN_MO83_EDATA2.
+* To use register names with standard convension, please use CAN_MO83_EDATA2.
+*/
+#define CAN_EMO83DATA2 (CAN_MO83_EDATA2)
+
+/** \brief 1A6C, Message Object Acceptance Mask Register */
+#define CAN_MO83_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019A6Cu)
+
+/** Alias (User Manual Name) for CAN_MO83_EDATA3.
+* To use register names with standard convension, please use CAN_MO83_EDATA3.
+*/
+#define CAN_EMO83DATA3 (CAN_MO83_EDATA3)
+
+/** \brief 1A70, Message Object Data Register Low */
+#define CAN_MO83_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019A70u)
+
+/** Alias (User Manual Name) for CAN_MO83_EDATA4.
+* To use register names with standard convension, please use CAN_MO83_EDATA4.
+*/
+#define CAN_EMO83DATA4 (CAN_MO83_EDATA4)
+
+/** \brief 1A74, Message Object Data Register High */
+#define CAN_MO83_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019A74u)
+
+/** Alias (User Manual Name) for CAN_MO83_EDATA5.
+* To use register names with standard convension, please use CAN_MO83_EDATA5.
+*/
+#define CAN_EMO83DATA5 (CAN_MO83_EDATA5)
+
+/** \brief 1A78, Message Object Arbitration Register */
+#define CAN_MO83_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019A78u)
+
+/** Alias (User Manual Name) for CAN_MO83_EDATA6.
+* To use register names with standard convension, please use CAN_MO83_EDATA6.
+*/
+#define CAN_EMO83DATA6 (CAN_MO83_EDATA6)
+
+/** \brief 1A60, Message Object Function Control Register */
+#define CAN_MO83_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019A60u)
+
+/** Alias (User Manual Name) for CAN_MO83_FCR.
+* To use register names with standard convension, please use CAN_MO83_FCR.
+*/
+#define CAN_MOFCR83 (CAN_MO83_FCR)
+
+/** \brief 1A64, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO83_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019A64u)
+
+/** Alias (User Manual Name) for CAN_MO83_FGPR.
+* To use register names with standard convension, please use CAN_MO83_FGPR.
+*/
+#define CAN_MOFGPR83 (CAN_MO83_FGPR)
+
+/** \brief 1A68, Message Object Interrupt Pointer Register */
+#define CAN_MO83_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019A68u)
+
+/** Alias (User Manual Name) for CAN_MO83_IPR.
+* To use register names with standard convension, please use CAN_MO83_IPR.
+*/
+#define CAN_MOIPR83 (CAN_MO83_IPR)
+
+/** \brief 1A7C, Message Object Control Register */
+#define CAN_MO83_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019A7Cu)
+
+/** Alias (User Manual Name) for CAN_MO83_STAT.
+* To use register names with standard convension, please use CAN_MO83_STAT.
+*/
+#define CAN_MOSTAT83 (CAN_MO83_STAT)
+
+/** \brief 1A8C, Message Object Acceptance Mask Register */
+#define CAN_MO84_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019A8Cu)
+
+/** Alias (User Manual Name) for CAN_MO84_AMR.
+* To use register names with standard convension, please use CAN_MO84_AMR.
+*/
+#define CAN_MOAMR84 (CAN_MO84_AMR)
+
+/** \brief 1A98, Message Object Arbitration Register */
+#define CAN_MO84_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019A98u)
+
+/** Alias (User Manual Name) for CAN_MO84_AR.
+* To use register names with standard convension, please use CAN_MO84_AR.
+*/
+#define CAN_MOAR84 (CAN_MO84_AR)
+
+/** \brief 1A9C, Message Object Control Register */
+#define CAN_MO84_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019A9Cu)
+
+/** Alias (User Manual Name) for CAN_MO84_CTR.
+* To use register names with standard convension, please use CAN_MO84_CTR.
+*/
+#define CAN_MOCTR84 (CAN_MO84_CTR)
+
+/** \brief 1A94, Message Object Data Register High */
+#define CAN_MO84_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019A94u)
+
+/** Alias (User Manual Name) for CAN_MO84_DATAH.
+* To use register names with standard convension, please use CAN_MO84_DATAH.
+*/
+#define CAN_MODATAH84 (CAN_MO84_DATAH)
+
+/** \brief 1A90, Message Object Data Register Low */
+#define CAN_MO84_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019A90u)
+
+/** Alias (User Manual Name) for CAN_MO84_DATAL.
+* To use register names with standard convension, please use CAN_MO84_DATAL.
+*/
+#define CAN_MODATAL84 (CAN_MO84_DATAL)
+
+/** \brief 1A80, Message Object Function Control Register */
+#define CAN_MO84_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019A80u)
+
+/** Alias (User Manual Name) for CAN_MO84_EDATA0.
+* To use register names with standard convension, please use CAN_MO84_EDATA0.
+*/
+#define CAN_EMO84DATA0 (CAN_MO84_EDATA0)
+
+/** \brief 1A84, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO84_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019A84u)
+
+/** Alias (User Manual Name) for CAN_MO84_EDATA1.
+* To use register names with standard convension, please use CAN_MO84_EDATA1.
+*/
+#define CAN_EMO84DATA1 (CAN_MO84_EDATA1)
+
+/** \brief 1A88, Message Object Interrupt Pointer Register */
+#define CAN_MO84_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019A88u)
+
+/** Alias (User Manual Name) for CAN_MO84_EDATA2.
+* To use register names with standard convension, please use CAN_MO84_EDATA2.
+*/
+#define CAN_EMO84DATA2 (CAN_MO84_EDATA2)
+
+/** \brief 1A8C, Message Object Acceptance Mask Register */
+#define CAN_MO84_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019A8Cu)
+
+/** Alias (User Manual Name) for CAN_MO84_EDATA3.
+* To use register names with standard convension, please use CAN_MO84_EDATA3.
+*/
+#define CAN_EMO84DATA3 (CAN_MO84_EDATA3)
+
+/** \brief 1A90, Message Object Data Register Low */
+#define CAN_MO84_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019A90u)
+
+/** Alias (User Manual Name) for CAN_MO84_EDATA4.
+* To use register names with standard convension, please use CAN_MO84_EDATA4.
+*/
+#define CAN_EMO84DATA4 (CAN_MO84_EDATA4)
+
+/** \brief 1A94, Message Object Data Register High */
+#define CAN_MO84_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019A94u)
+
+/** Alias (User Manual Name) for CAN_MO84_EDATA5.
+* To use register names with standard convension, please use CAN_MO84_EDATA5.
+*/
+#define CAN_EMO84DATA5 (CAN_MO84_EDATA5)
+
+/** \brief 1A98, Message Object Arbitration Register */
+#define CAN_MO84_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019A98u)
+
+/** Alias (User Manual Name) for CAN_MO84_EDATA6.
+* To use register names with standard convension, please use CAN_MO84_EDATA6.
+*/
+#define CAN_EMO84DATA6 (CAN_MO84_EDATA6)
+
+/** \brief 1A80, Message Object Function Control Register */
+#define CAN_MO84_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019A80u)
+
+/** Alias (User Manual Name) for CAN_MO84_FCR.
+* To use register names with standard convension, please use CAN_MO84_FCR.
+*/
+#define CAN_MOFCR84 (CAN_MO84_FCR)
+
+/** \brief 1A84, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO84_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019A84u)
+
+/** Alias (User Manual Name) for CAN_MO84_FGPR.
+* To use register names with standard convension, please use CAN_MO84_FGPR.
+*/
+#define CAN_MOFGPR84 (CAN_MO84_FGPR)
+
+/** \brief 1A88, Message Object Interrupt Pointer Register */
+#define CAN_MO84_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019A88u)
+
+/** Alias (User Manual Name) for CAN_MO84_IPR.
+* To use register names with standard convension, please use CAN_MO84_IPR.
+*/
+#define CAN_MOIPR84 (CAN_MO84_IPR)
+
+/** \brief 1A9C, Message Object Control Register */
+#define CAN_MO84_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019A9Cu)
+
+/** Alias (User Manual Name) for CAN_MO84_STAT.
+* To use register names with standard convension, please use CAN_MO84_STAT.
+*/
+#define CAN_MOSTAT84 (CAN_MO84_STAT)
+
+/** \brief 1AAC, Message Object Acceptance Mask Register */
+#define CAN_MO85_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019AACu)
+
+/** Alias (User Manual Name) for CAN_MO85_AMR.
+* To use register names with standard convension, please use CAN_MO85_AMR.
+*/
+#define CAN_MOAMR85 (CAN_MO85_AMR)
+
+/** \brief 1AB8, Message Object Arbitration Register */
+#define CAN_MO85_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019AB8u)
+
+/** Alias (User Manual Name) for CAN_MO85_AR.
+* To use register names with standard convension, please use CAN_MO85_AR.
+*/
+#define CAN_MOAR85 (CAN_MO85_AR)
+
+/** \brief 1ABC, Message Object Control Register */
+#define CAN_MO85_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019ABCu)
+
+/** Alias (User Manual Name) for CAN_MO85_CTR.
+* To use register names with standard convension, please use CAN_MO85_CTR.
+*/
+#define CAN_MOCTR85 (CAN_MO85_CTR)
+
+/** \brief 1AB4, Message Object Data Register High */
+#define CAN_MO85_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019AB4u)
+
+/** Alias (User Manual Name) for CAN_MO85_DATAH.
+* To use register names with standard convension, please use CAN_MO85_DATAH.
+*/
+#define CAN_MODATAH85 (CAN_MO85_DATAH)
+
+/** \brief 1AB0, Message Object Data Register Low */
+#define CAN_MO85_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019AB0u)
+
+/** Alias (User Manual Name) for CAN_MO85_DATAL.
+* To use register names with standard convension, please use CAN_MO85_DATAL.
+*/
+#define CAN_MODATAL85 (CAN_MO85_DATAL)
+
+/** \brief 1AA0, Message Object Function Control Register */
+#define CAN_MO85_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019AA0u)
+
+/** Alias (User Manual Name) for CAN_MO85_EDATA0.
+* To use register names with standard convension, please use CAN_MO85_EDATA0.
+*/
+#define CAN_EMO85DATA0 (CAN_MO85_EDATA0)
+
+/** \brief 1AA4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO85_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019AA4u)
+
+/** Alias (User Manual Name) for CAN_MO85_EDATA1.
+* To use register names with standard convension, please use CAN_MO85_EDATA1.
+*/
+#define CAN_EMO85DATA1 (CAN_MO85_EDATA1)
+
+/** \brief 1AA8, Message Object Interrupt Pointer Register */
+#define CAN_MO85_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019AA8u)
+
+/** Alias (User Manual Name) for CAN_MO85_EDATA2.
+* To use register names with standard convension, please use CAN_MO85_EDATA2.
+*/
+#define CAN_EMO85DATA2 (CAN_MO85_EDATA2)
+
+/** \brief 1AAC, Message Object Acceptance Mask Register */
+#define CAN_MO85_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019AACu)
+
+/** Alias (User Manual Name) for CAN_MO85_EDATA3.
+* To use register names with standard convension, please use CAN_MO85_EDATA3.
+*/
+#define CAN_EMO85DATA3 (CAN_MO85_EDATA3)
+
+/** \brief 1AB0, Message Object Data Register Low */
+#define CAN_MO85_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019AB0u)
+
+/** Alias (User Manual Name) for CAN_MO85_EDATA4.
+* To use register names with standard convension, please use CAN_MO85_EDATA4.
+*/
+#define CAN_EMO85DATA4 (CAN_MO85_EDATA4)
+
+/** \brief 1AB4, Message Object Data Register High */
+#define CAN_MO85_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019AB4u)
+
+/** Alias (User Manual Name) for CAN_MO85_EDATA5.
+* To use register names with standard convension, please use CAN_MO85_EDATA5.
+*/
+#define CAN_EMO85DATA5 (CAN_MO85_EDATA5)
+
+/** \brief 1AB8, Message Object Arbitration Register */
+#define CAN_MO85_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019AB8u)
+
+/** Alias (User Manual Name) for CAN_MO85_EDATA6.
+* To use register names with standard convension, please use CAN_MO85_EDATA6.
+*/
+#define CAN_EMO85DATA6 (CAN_MO85_EDATA6)
+
+/** \brief 1AA0, Message Object Function Control Register */
+#define CAN_MO85_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019AA0u)
+
+/** Alias (User Manual Name) for CAN_MO85_FCR.
+* To use register names with standard convension, please use CAN_MO85_FCR.
+*/
+#define CAN_MOFCR85 (CAN_MO85_FCR)
+
+/** \brief 1AA4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO85_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019AA4u)
+
+/** Alias (User Manual Name) for CAN_MO85_FGPR.
+* To use register names with standard convension, please use CAN_MO85_FGPR.
+*/
+#define CAN_MOFGPR85 (CAN_MO85_FGPR)
+
+/** \brief 1AA8, Message Object Interrupt Pointer Register */
+#define CAN_MO85_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019AA8u)
+
+/** Alias (User Manual Name) for CAN_MO85_IPR.
+* To use register names with standard convension, please use CAN_MO85_IPR.
+*/
+#define CAN_MOIPR85 (CAN_MO85_IPR)
+
+/** \brief 1ABC, Message Object Control Register */
+#define CAN_MO85_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019ABCu)
+
+/** Alias (User Manual Name) for CAN_MO85_STAT.
+* To use register names with standard convension, please use CAN_MO85_STAT.
+*/
+#define CAN_MOSTAT85 (CAN_MO85_STAT)
+
+/** \brief 1ACC, Message Object Acceptance Mask Register */
+#define CAN_MO86_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019ACCu)
+
+/** Alias (User Manual Name) for CAN_MO86_AMR.
+* To use register names with standard convension, please use CAN_MO86_AMR.
+*/
+#define CAN_MOAMR86 (CAN_MO86_AMR)
+
+/** \brief 1AD8, Message Object Arbitration Register */
+#define CAN_MO86_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019AD8u)
+
+/** Alias (User Manual Name) for CAN_MO86_AR.
+* To use register names with standard convension, please use CAN_MO86_AR.
+*/
+#define CAN_MOAR86 (CAN_MO86_AR)
+
+/** \brief 1ADC, Message Object Control Register */
+#define CAN_MO86_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019ADCu)
+
+/** Alias (User Manual Name) for CAN_MO86_CTR.
+* To use register names with standard convension, please use CAN_MO86_CTR.
+*/
+#define CAN_MOCTR86 (CAN_MO86_CTR)
+
+/** \brief 1AD4, Message Object Data Register High */
+#define CAN_MO86_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019AD4u)
+
+/** Alias (User Manual Name) for CAN_MO86_DATAH.
+* To use register names with standard convension, please use CAN_MO86_DATAH.
+*/
+#define CAN_MODATAH86 (CAN_MO86_DATAH)
+
+/** \brief 1AD0, Message Object Data Register Low */
+#define CAN_MO86_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019AD0u)
+
+/** Alias (User Manual Name) for CAN_MO86_DATAL.
+* To use register names with standard convension, please use CAN_MO86_DATAL.
+*/
+#define CAN_MODATAL86 (CAN_MO86_DATAL)
+
+/** \brief 1AC0, Message Object Function Control Register */
+#define CAN_MO86_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019AC0u)
+
+/** Alias (User Manual Name) for CAN_MO86_EDATA0.
+* To use register names with standard convension, please use CAN_MO86_EDATA0.
+*/
+#define CAN_EMO86DATA0 (CAN_MO86_EDATA0)
+
+/** \brief 1AC4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO86_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019AC4u)
+
+/** Alias (User Manual Name) for CAN_MO86_EDATA1.
+* To use register names with standard convension, please use CAN_MO86_EDATA1.
+*/
+#define CAN_EMO86DATA1 (CAN_MO86_EDATA1)
+
+/** \brief 1AC8, Message Object Interrupt Pointer Register */
+#define CAN_MO86_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019AC8u)
+
+/** Alias (User Manual Name) for CAN_MO86_EDATA2.
+* To use register names with standard convension, please use CAN_MO86_EDATA2.
+*/
+#define CAN_EMO86DATA2 (CAN_MO86_EDATA2)
+
+/** \brief 1ACC, Message Object Acceptance Mask Register */
+#define CAN_MO86_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019ACCu)
+
+/** Alias (User Manual Name) for CAN_MO86_EDATA3.
+* To use register names with standard convension, please use CAN_MO86_EDATA3.
+*/
+#define CAN_EMO86DATA3 (CAN_MO86_EDATA3)
+
+/** \brief 1AD0, Message Object Data Register Low */
+#define CAN_MO86_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019AD0u)
+
+/** Alias (User Manual Name) for CAN_MO86_EDATA4.
+* To use register names with standard convension, please use CAN_MO86_EDATA4.
+*/
+#define CAN_EMO86DATA4 (CAN_MO86_EDATA4)
+
+/** \brief 1AD4, Message Object Data Register High */
+#define CAN_MO86_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019AD4u)
+
+/** Alias (User Manual Name) for CAN_MO86_EDATA5.
+* To use register names with standard convension, please use CAN_MO86_EDATA5.
+*/
+#define CAN_EMO86DATA5 (CAN_MO86_EDATA5)
+
+/** \brief 1AD8, Message Object Arbitration Register */
+#define CAN_MO86_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019AD8u)
+
+/** Alias (User Manual Name) for CAN_MO86_EDATA6.
+* To use register names with standard convension, please use CAN_MO86_EDATA6.
+*/
+#define CAN_EMO86DATA6 (CAN_MO86_EDATA6)
+
+/** \brief 1AC0, Message Object Function Control Register */
+#define CAN_MO86_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019AC0u)
+
+/** Alias (User Manual Name) for CAN_MO86_FCR.
+* To use register names with standard convension, please use CAN_MO86_FCR.
+*/
+#define CAN_MOFCR86 (CAN_MO86_FCR)
+
+/** \brief 1AC4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO86_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019AC4u)
+
+/** Alias (User Manual Name) for CAN_MO86_FGPR.
+* To use register names with standard convension, please use CAN_MO86_FGPR.
+*/
+#define CAN_MOFGPR86 (CAN_MO86_FGPR)
+
+/** \brief 1AC8, Message Object Interrupt Pointer Register */
+#define CAN_MO86_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019AC8u)
+
+/** Alias (User Manual Name) for CAN_MO86_IPR.
+* To use register names with standard convension, please use CAN_MO86_IPR.
+*/
+#define CAN_MOIPR86 (CAN_MO86_IPR)
+
+/** \brief 1ADC, Message Object Control Register */
+#define CAN_MO86_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019ADCu)
+
+/** Alias (User Manual Name) for CAN_MO86_STAT.
+* To use register names with standard convension, please use CAN_MO86_STAT.
+*/
+#define CAN_MOSTAT86 (CAN_MO86_STAT)
+
+/** \brief 1AEC, Message Object Acceptance Mask Register */
+#define CAN_MO87_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019AECu)
+
+/** Alias (User Manual Name) for CAN_MO87_AMR.
+* To use register names with standard convension, please use CAN_MO87_AMR.
+*/
+#define CAN_MOAMR87 (CAN_MO87_AMR)
+
+/** \brief 1AF8, Message Object Arbitration Register */
+#define CAN_MO87_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019AF8u)
+
+/** Alias (User Manual Name) for CAN_MO87_AR.
+* To use register names with standard convension, please use CAN_MO87_AR.
+*/
+#define CAN_MOAR87 (CAN_MO87_AR)
+
+/** \brief 1AFC, Message Object Control Register */
+#define CAN_MO87_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019AFCu)
+
+/** Alias (User Manual Name) for CAN_MO87_CTR.
+* To use register names with standard convension, please use CAN_MO87_CTR.
+*/
+#define CAN_MOCTR87 (CAN_MO87_CTR)
+
+/** \brief 1AF4, Message Object Data Register High */
+#define CAN_MO87_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019AF4u)
+
+/** Alias (User Manual Name) for CAN_MO87_DATAH.
+* To use register names with standard convension, please use CAN_MO87_DATAH.
+*/
+#define CAN_MODATAH87 (CAN_MO87_DATAH)
+
+/** \brief 1AF0, Message Object Data Register Low */
+#define CAN_MO87_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019AF0u)
+
+/** Alias (User Manual Name) for CAN_MO87_DATAL.
+* To use register names with standard convension, please use CAN_MO87_DATAL.
+*/
+#define CAN_MODATAL87 (CAN_MO87_DATAL)
+
+/** \brief 1AE0, Message Object Function Control Register */
+#define CAN_MO87_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019AE0u)
+
+/** Alias (User Manual Name) for CAN_MO87_EDATA0.
+* To use register names with standard convension, please use CAN_MO87_EDATA0.
+*/
+#define CAN_EMO87DATA0 (CAN_MO87_EDATA0)
+
+/** \brief 1AE4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO87_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019AE4u)
+
+/** Alias (User Manual Name) for CAN_MO87_EDATA1.
+* To use register names with standard convension, please use CAN_MO87_EDATA1.
+*/
+#define CAN_EMO87DATA1 (CAN_MO87_EDATA1)
+
+/** \brief 1AE8, Message Object Interrupt Pointer Register */
+#define CAN_MO87_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019AE8u)
+
+/** Alias (User Manual Name) for CAN_MO87_EDATA2.
+* To use register names with standard convension, please use CAN_MO87_EDATA2.
+*/
+#define CAN_EMO87DATA2 (CAN_MO87_EDATA2)
+
+/** \brief 1AEC, Message Object Acceptance Mask Register */
+#define CAN_MO87_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019AECu)
+
+/** Alias (User Manual Name) for CAN_MO87_EDATA3.
+* To use register names with standard convension, please use CAN_MO87_EDATA3.
+*/
+#define CAN_EMO87DATA3 (CAN_MO87_EDATA3)
+
+/** \brief 1AF0, Message Object Data Register Low */
+#define CAN_MO87_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019AF0u)
+
+/** Alias (User Manual Name) for CAN_MO87_EDATA4.
+* To use register names with standard convension, please use CAN_MO87_EDATA4.
+*/
+#define CAN_EMO87DATA4 (CAN_MO87_EDATA4)
+
+/** \brief 1AF4, Message Object Data Register High */
+#define CAN_MO87_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019AF4u)
+
+/** Alias (User Manual Name) for CAN_MO87_EDATA5.
+* To use register names with standard convension, please use CAN_MO87_EDATA5.
+*/
+#define CAN_EMO87DATA5 (CAN_MO87_EDATA5)
+
+/** \brief 1AF8, Message Object Arbitration Register */
+#define CAN_MO87_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019AF8u)
+
+/** Alias (User Manual Name) for CAN_MO87_EDATA6.
+* To use register names with standard convension, please use CAN_MO87_EDATA6.
+*/
+#define CAN_EMO87DATA6 (CAN_MO87_EDATA6)
+
+/** \brief 1AE0, Message Object Function Control Register */
+#define CAN_MO87_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019AE0u)
+
+/** Alias (User Manual Name) for CAN_MO87_FCR.
+* To use register names with standard convension, please use CAN_MO87_FCR.
+*/
+#define CAN_MOFCR87 (CAN_MO87_FCR)
+
+/** \brief 1AE4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO87_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019AE4u)
+
+/** Alias (User Manual Name) for CAN_MO87_FGPR.
+* To use register names with standard convension, please use CAN_MO87_FGPR.
+*/
+#define CAN_MOFGPR87 (CAN_MO87_FGPR)
+
+/** \brief 1AE8, Message Object Interrupt Pointer Register */
+#define CAN_MO87_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019AE8u)
+
+/** Alias (User Manual Name) for CAN_MO87_IPR.
+* To use register names with standard convension, please use CAN_MO87_IPR.
+*/
+#define CAN_MOIPR87 (CAN_MO87_IPR)
+
+/** \brief 1AFC, Message Object Control Register */
+#define CAN_MO87_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019AFCu)
+
+/** Alias (User Manual Name) for CAN_MO87_STAT.
+* To use register names with standard convension, please use CAN_MO87_STAT.
+*/
+#define CAN_MOSTAT87 (CAN_MO87_STAT)
+
+/** \brief 1B0C, Message Object Acceptance Mask Register */
+#define CAN_MO88_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019B0Cu)
+
+/** Alias (User Manual Name) for CAN_MO88_AMR.
+* To use register names with standard convension, please use CAN_MO88_AMR.
+*/
+#define CAN_MOAMR88 (CAN_MO88_AMR)
+
+/** \brief 1B18, Message Object Arbitration Register */
+#define CAN_MO88_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019B18u)
+
+/** Alias (User Manual Name) for CAN_MO88_AR.
+* To use register names with standard convension, please use CAN_MO88_AR.
+*/
+#define CAN_MOAR88 (CAN_MO88_AR)
+
+/** \brief 1B1C, Message Object Control Register */
+#define CAN_MO88_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019B1Cu)
+
+/** Alias (User Manual Name) for CAN_MO88_CTR.
+* To use register names with standard convension, please use CAN_MO88_CTR.
+*/
+#define CAN_MOCTR88 (CAN_MO88_CTR)
+
+/** \brief 1B14, Message Object Data Register High */
+#define CAN_MO88_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019B14u)
+
+/** Alias (User Manual Name) for CAN_MO88_DATAH.
+* To use register names with standard convension, please use CAN_MO88_DATAH.
+*/
+#define CAN_MODATAH88 (CAN_MO88_DATAH)
+
+/** \brief 1B10, Message Object Data Register Low */
+#define CAN_MO88_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019B10u)
+
+/** Alias (User Manual Name) for CAN_MO88_DATAL.
+* To use register names with standard convension, please use CAN_MO88_DATAL.
+*/
+#define CAN_MODATAL88 (CAN_MO88_DATAL)
+
+/** \brief 1B00, Message Object Function Control Register */
+#define CAN_MO88_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019B00u)
+
+/** Alias (User Manual Name) for CAN_MO88_EDATA0.
+* To use register names with standard convension, please use CAN_MO88_EDATA0.
+*/
+#define CAN_EMO88DATA0 (CAN_MO88_EDATA0)
+
+/** \brief 1B04, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO88_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019B04u)
+
+/** Alias (User Manual Name) for CAN_MO88_EDATA1.
+* To use register names with standard convension, please use CAN_MO88_EDATA1.
+*/
+#define CAN_EMO88DATA1 (CAN_MO88_EDATA1)
+
+/** \brief 1B08, Message Object Interrupt Pointer Register */
+#define CAN_MO88_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019B08u)
+
+/** Alias (User Manual Name) for CAN_MO88_EDATA2.
+* To use register names with standard convension, please use CAN_MO88_EDATA2.
+*/
+#define CAN_EMO88DATA2 (CAN_MO88_EDATA2)
+
+/** \brief 1B0C, Message Object Acceptance Mask Register */
+#define CAN_MO88_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019B0Cu)
+
+/** Alias (User Manual Name) for CAN_MO88_EDATA3.
+* To use register names with standard convension, please use CAN_MO88_EDATA3.
+*/
+#define CAN_EMO88DATA3 (CAN_MO88_EDATA3)
+
+/** \brief 1B10, Message Object Data Register Low */
+#define CAN_MO88_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019B10u)
+
+/** Alias (User Manual Name) for CAN_MO88_EDATA4.
+* To use register names with standard convension, please use CAN_MO88_EDATA4.
+*/
+#define CAN_EMO88DATA4 (CAN_MO88_EDATA4)
+
+/** \brief 1B14, Message Object Data Register High */
+#define CAN_MO88_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019B14u)
+
+/** Alias (User Manual Name) for CAN_MO88_EDATA5.
+* To use register names with standard convension, please use CAN_MO88_EDATA5.
+*/
+#define CAN_EMO88DATA5 (CAN_MO88_EDATA5)
+
+/** \brief 1B18, Message Object Arbitration Register */
+#define CAN_MO88_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019B18u)
+
+/** Alias (User Manual Name) for CAN_MO88_EDATA6.
+* To use register names with standard convension, please use CAN_MO88_EDATA6.
+*/
+#define CAN_EMO88DATA6 (CAN_MO88_EDATA6)
+
+/** \brief 1B00, Message Object Function Control Register */
+#define CAN_MO88_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019B00u)
+
+/** Alias (User Manual Name) for CAN_MO88_FCR.
+* To use register names with standard convension, please use CAN_MO88_FCR.
+*/
+#define CAN_MOFCR88 (CAN_MO88_FCR)
+
+/** \brief 1B04, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO88_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019B04u)
+
+/** Alias (User Manual Name) for CAN_MO88_FGPR.
+* To use register names with standard convension, please use CAN_MO88_FGPR.
+*/
+#define CAN_MOFGPR88 (CAN_MO88_FGPR)
+
+/** \brief 1B08, Message Object Interrupt Pointer Register */
+#define CAN_MO88_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019B08u)
+
+/** Alias (User Manual Name) for CAN_MO88_IPR.
+* To use register names with standard convension, please use CAN_MO88_IPR.
+*/
+#define CAN_MOIPR88 (CAN_MO88_IPR)
+
+/** \brief 1B1C, Message Object Control Register */
+#define CAN_MO88_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019B1Cu)
+
+/** Alias (User Manual Name) for CAN_MO88_STAT.
+* To use register names with standard convension, please use CAN_MO88_STAT.
+*/
+#define CAN_MOSTAT88 (CAN_MO88_STAT)
+
+/** \brief 1B2C, Message Object Acceptance Mask Register */
+#define CAN_MO89_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019B2Cu)
+
+/** Alias (User Manual Name) for CAN_MO89_AMR.
+* To use register names with standard convension, please use CAN_MO89_AMR.
+*/
+#define CAN_MOAMR89 (CAN_MO89_AMR)
+
+/** \brief 1B38, Message Object Arbitration Register */
+#define CAN_MO89_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019B38u)
+
+/** Alias (User Manual Name) for CAN_MO89_AR.
+* To use register names with standard convension, please use CAN_MO89_AR.
+*/
+#define CAN_MOAR89 (CAN_MO89_AR)
+
+/** \brief 1B3C, Message Object Control Register */
+#define CAN_MO89_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019B3Cu)
+
+/** Alias (User Manual Name) for CAN_MO89_CTR.
+* To use register names with standard convension, please use CAN_MO89_CTR.
+*/
+#define CAN_MOCTR89 (CAN_MO89_CTR)
+
+/** \brief 1B34, Message Object Data Register High */
+#define CAN_MO89_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019B34u)
+
+/** Alias (User Manual Name) for CAN_MO89_DATAH.
+* To use register names with standard convension, please use CAN_MO89_DATAH.
+*/
+#define CAN_MODATAH89 (CAN_MO89_DATAH)
+
+/** \brief 1B30, Message Object Data Register Low */
+#define CAN_MO89_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019B30u)
+
+/** Alias (User Manual Name) for CAN_MO89_DATAL.
+* To use register names with standard convension, please use CAN_MO89_DATAL.
+*/
+#define CAN_MODATAL89 (CAN_MO89_DATAL)
+
+/** \brief 1B20, Message Object Function Control Register */
+#define CAN_MO89_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019B20u)
+
+/** Alias (User Manual Name) for CAN_MO89_EDATA0.
+* To use register names with standard convension, please use CAN_MO89_EDATA0.
+*/
+#define CAN_EMO89DATA0 (CAN_MO89_EDATA0)
+
+/** \brief 1B24, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO89_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019B24u)
+
+/** Alias (User Manual Name) for CAN_MO89_EDATA1.
+* To use register names with standard convension, please use CAN_MO89_EDATA1.
+*/
+#define CAN_EMO89DATA1 (CAN_MO89_EDATA1)
+
+/** \brief 1B28, Message Object Interrupt Pointer Register */
+#define CAN_MO89_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019B28u)
+
+/** Alias (User Manual Name) for CAN_MO89_EDATA2.
+* To use register names with standard convension, please use CAN_MO89_EDATA2.
+*/
+#define CAN_EMO89DATA2 (CAN_MO89_EDATA2)
+
+/** \brief 1B2C, Message Object Acceptance Mask Register */
+#define CAN_MO89_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019B2Cu)
+
+/** Alias (User Manual Name) for CAN_MO89_EDATA3.
+* To use register names with standard convension, please use CAN_MO89_EDATA3.
+*/
+#define CAN_EMO89DATA3 (CAN_MO89_EDATA3)
+
+/** \brief 1B30, Message Object Data Register Low */
+#define CAN_MO89_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019B30u)
+
+/** Alias (User Manual Name) for CAN_MO89_EDATA4.
+* To use register names with standard convension, please use CAN_MO89_EDATA4.
+*/
+#define CAN_EMO89DATA4 (CAN_MO89_EDATA4)
+
+/** \brief 1B34, Message Object Data Register High */
+#define CAN_MO89_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019B34u)
+
+/** Alias (User Manual Name) for CAN_MO89_EDATA5.
+* To use register names with standard convension, please use CAN_MO89_EDATA5.
+*/
+#define CAN_EMO89DATA5 (CAN_MO89_EDATA5)
+
+/** \brief 1B38, Message Object Arbitration Register */
+#define CAN_MO89_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019B38u)
+
+/** Alias (User Manual Name) for CAN_MO89_EDATA6.
+* To use register names with standard convension, please use CAN_MO89_EDATA6.
+*/
+#define CAN_EMO89DATA6 (CAN_MO89_EDATA6)
+
+/** \brief 1B20, Message Object Function Control Register */
+#define CAN_MO89_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019B20u)
+
+/** Alias (User Manual Name) for CAN_MO89_FCR.
+* To use register names with standard convension, please use CAN_MO89_FCR.
+*/
+#define CAN_MOFCR89 (CAN_MO89_FCR)
+
+/** \brief 1B24, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO89_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019B24u)
+
+/** Alias (User Manual Name) for CAN_MO89_FGPR.
+* To use register names with standard convension, please use CAN_MO89_FGPR.
+*/
+#define CAN_MOFGPR89 (CAN_MO89_FGPR)
+
+/** \brief 1B28, Message Object Interrupt Pointer Register */
+#define CAN_MO89_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019B28u)
+
+/** Alias (User Manual Name) for CAN_MO89_IPR.
+* To use register names with standard convension, please use CAN_MO89_IPR.
+*/
+#define CAN_MOIPR89 (CAN_MO89_IPR)
+
+/** \brief 1B3C, Message Object Control Register */
+#define CAN_MO89_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019B3Cu)
+
+/** Alias (User Manual Name) for CAN_MO89_STAT.
+* To use register names with standard convension, please use CAN_MO89_STAT.
+*/
+#define CAN_MOSTAT89 (CAN_MO89_STAT)
+
+/** \brief 110C, Message Object Acceptance Mask Register */
+#define CAN_MO8_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001910Cu)
+
+/** Alias (User Manual Name) for CAN_MO8_AMR.
+* To use register names with standard convension, please use CAN_MO8_AMR.
+*/
+#define CAN_MOAMR8 (CAN_MO8_AMR)
+
+/** \brief 1118, Message Object Arbitration Register */
+#define CAN_MO8_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019118u)
+
+/** Alias (User Manual Name) for CAN_MO8_AR.
+* To use register names with standard convension, please use CAN_MO8_AR.
+*/
+#define CAN_MOAR8 (CAN_MO8_AR)
+
+/** \brief 111C, Message Object Control Register */
+#define CAN_MO8_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001911Cu)
+
+/** Alias (User Manual Name) for CAN_MO8_CTR.
+* To use register names with standard convension, please use CAN_MO8_CTR.
+*/
+#define CAN_MOCTR8 (CAN_MO8_CTR)
+
+/** \brief 1114, Message Object Data Register High */
+#define CAN_MO8_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019114u)
+
+/** Alias (User Manual Name) for CAN_MO8_DATAH.
+* To use register names with standard convension, please use CAN_MO8_DATAH.
+*/
+#define CAN_MODATAH8 (CAN_MO8_DATAH)
+
+/** \brief 1110, Message Object Data Register Low */
+#define CAN_MO8_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019110u)
+
+/** Alias (User Manual Name) for CAN_MO8_DATAL.
+* To use register names with standard convension, please use CAN_MO8_DATAL.
+*/
+#define CAN_MODATAL8 (CAN_MO8_DATAL)
+
+/** \brief 1100, Message Object Function Control Register */
+#define CAN_MO8_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019100u)
+
+/** Alias (User Manual Name) for CAN_MO8_EDATA0.
+* To use register names with standard convension, please use CAN_MO8_EDATA0.
+*/
+#define CAN_EMO8DATA0 (CAN_MO8_EDATA0)
+
+/** \brief 1104, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO8_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019104u)
+
+/** Alias (User Manual Name) for CAN_MO8_EDATA1.
+* To use register names with standard convension, please use CAN_MO8_EDATA1.
+*/
+#define CAN_EMO8DATA1 (CAN_MO8_EDATA1)
+
+/** \brief 1108, Message Object Interrupt Pointer Register */
+#define CAN_MO8_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019108u)
+
+/** Alias (User Manual Name) for CAN_MO8_EDATA2.
+* To use register names with standard convension, please use CAN_MO8_EDATA2.
+*/
+#define CAN_EMO8DATA2 (CAN_MO8_EDATA2)
+
+/** \brief 110C, Message Object Acceptance Mask Register */
+#define CAN_MO8_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001910Cu)
+
+/** Alias (User Manual Name) for CAN_MO8_EDATA3.
+* To use register names with standard convension, please use CAN_MO8_EDATA3.
+*/
+#define CAN_EMO8DATA3 (CAN_MO8_EDATA3)
+
+/** \brief 1110, Message Object Data Register Low */
+#define CAN_MO8_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019110u)
+
+/** Alias (User Manual Name) for CAN_MO8_EDATA4.
+* To use register names with standard convension, please use CAN_MO8_EDATA4.
+*/
+#define CAN_EMO8DATA4 (CAN_MO8_EDATA4)
+
+/** \brief 1114, Message Object Data Register High */
+#define CAN_MO8_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019114u)
+
+/** Alias (User Manual Name) for CAN_MO8_EDATA5.
+* To use register names with standard convension, please use CAN_MO8_EDATA5.
+*/
+#define CAN_EMO8DATA5 (CAN_MO8_EDATA5)
+
+/** \brief 1118, Message Object Arbitration Register */
+#define CAN_MO8_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019118u)
+
+/** Alias (User Manual Name) for CAN_MO8_EDATA6.
+* To use register names with standard convension, please use CAN_MO8_EDATA6.
+*/
+#define CAN_EMO8DATA6 (CAN_MO8_EDATA6)
+
+/** \brief 1100, Message Object Function Control Register */
+#define CAN_MO8_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019100u)
+
+/** Alias (User Manual Name) for CAN_MO8_FCR.
+* To use register names with standard convension, please use CAN_MO8_FCR.
+*/
+#define CAN_MOFCR8 (CAN_MO8_FCR)
+
+/** \brief 1104, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO8_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019104u)
+
+/** Alias (User Manual Name) for CAN_MO8_FGPR.
+* To use register names with standard convension, please use CAN_MO8_FGPR.
+*/
+#define CAN_MOFGPR8 (CAN_MO8_FGPR)
+
+/** \brief 1108, Message Object Interrupt Pointer Register */
+#define CAN_MO8_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019108u)
+
+/** Alias (User Manual Name) for CAN_MO8_IPR.
+* To use register names with standard convension, please use CAN_MO8_IPR.
+*/
+#define CAN_MOIPR8 (CAN_MO8_IPR)
+
+/** \brief 111C, Message Object Control Register */
+#define CAN_MO8_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001911Cu)
+
+/** Alias (User Manual Name) for CAN_MO8_STAT.
+* To use register names with standard convension, please use CAN_MO8_STAT.
+*/
+#define CAN_MOSTAT8 (CAN_MO8_STAT)
+
+/** \brief 1B4C, Message Object Acceptance Mask Register */
+#define CAN_MO90_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019B4Cu)
+
+/** Alias (User Manual Name) for CAN_MO90_AMR.
+* To use register names with standard convension, please use CAN_MO90_AMR.
+*/
+#define CAN_MOAMR90 (CAN_MO90_AMR)
+
+/** \brief 1B58, Message Object Arbitration Register */
+#define CAN_MO90_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019B58u)
+
+/** Alias (User Manual Name) for CAN_MO90_AR.
+* To use register names with standard convension, please use CAN_MO90_AR.
+*/
+#define CAN_MOAR90 (CAN_MO90_AR)
+
+/** \brief 1B5C, Message Object Control Register */
+#define CAN_MO90_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019B5Cu)
+
+/** Alias (User Manual Name) for CAN_MO90_CTR.
+* To use register names with standard convension, please use CAN_MO90_CTR.
+*/
+#define CAN_MOCTR90 (CAN_MO90_CTR)
+
+/** \brief 1B54, Message Object Data Register High */
+#define CAN_MO90_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019B54u)
+
+/** Alias (User Manual Name) for CAN_MO90_DATAH.
+* To use register names with standard convension, please use CAN_MO90_DATAH.
+*/
+#define CAN_MODATAH90 (CAN_MO90_DATAH)
+
+/** \brief 1B50, Message Object Data Register Low */
+#define CAN_MO90_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019B50u)
+
+/** Alias (User Manual Name) for CAN_MO90_DATAL.
+* To use register names with standard convension, please use CAN_MO90_DATAL.
+*/
+#define CAN_MODATAL90 (CAN_MO90_DATAL)
+
+/** \brief 1B40, Message Object Function Control Register */
+#define CAN_MO90_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019B40u)
+
+/** Alias (User Manual Name) for CAN_MO90_EDATA0.
+* To use register names with standard convension, please use CAN_MO90_EDATA0.
+*/
+#define CAN_EMO90DATA0 (CAN_MO90_EDATA0)
+
+/** \brief 1B44, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO90_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019B44u)
+
+/** Alias (User Manual Name) for CAN_MO90_EDATA1.
+* To use register names with standard convension, please use CAN_MO90_EDATA1.
+*/
+#define CAN_EMO90DATA1 (CAN_MO90_EDATA1)
+
+/** \brief 1B48, Message Object Interrupt Pointer Register */
+#define CAN_MO90_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019B48u)
+
+/** Alias (User Manual Name) for CAN_MO90_EDATA2.
+* To use register names with standard convension, please use CAN_MO90_EDATA2.
+*/
+#define CAN_EMO90DATA2 (CAN_MO90_EDATA2)
+
+/** \brief 1B4C, Message Object Acceptance Mask Register */
+#define CAN_MO90_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019B4Cu)
+
+/** Alias (User Manual Name) for CAN_MO90_EDATA3.
+* To use register names with standard convension, please use CAN_MO90_EDATA3.
+*/
+#define CAN_EMO90DATA3 (CAN_MO90_EDATA3)
+
+/** \brief 1B50, Message Object Data Register Low */
+#define CAN_MO90_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019B50u)
+
+/** Alias (User Manual Name) for CAN_MO90_EDATA4.
+* To use register names with standard convension, please use CAN_MO90_EDATA4.
+*/
+#define CAN_EMO90DATA4 (CAN_MO90_EDATA4)
+
+/** \brief 1B54, Message Object Data Register High */
+#define CAN_MO90_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019B54u)
+
+/** Alias (User Manual Name) for CAN_MO90_EDATA5.
+* To use register names with standard convension, please use CAN_MO90_EDATA5.
+*/
+#define CAN_EMO90DATA5 (CAN_MO90_EDATA5)
+
+/** \brief 1B58, Message Object Arbitration Register */
+#define CAN_MO90_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019B58u)
+
+/** Alias (User Manual Name) for CAN_MO90_EDATA6.
+* To use register names with standard convension, please use CAN_MO90_EDATA6.
+*/
+#define CAN_EMO90DATA6 (CAN_MO90_EDATA6)
+
+/** \brief 1B40, Message Object Function Control Register */
+#define CAN_MO90_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019B40u)
+
+/** Alias (User Manual Name) for CAN_MO90_FCR.
+* To use register names with standard convension, please use CAN_MO90_FCR.
+*/
+#define CAN_MOFCR90 (CAN_MO90_FCR)
+
+/** \brief 1B44, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO90_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019B44u)
+
+/** Alias (User Manual Name) for CAN_MO90_FGPR.
+* To use register names with standard convension, please use CAN_MO90_FGPR.
+*/
+#define CAN_MOFGPR90 (CAN_MO90_FGPR)
+
+/** \brief 1B48, Message Object Interrupt Pointer Register */
+#define CAN_MO90_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019B48u)
+
+/** Alias (User Manual Name) for CAN_MO90_IPR.
+* To use register names with standard convension, please use CAN_MO90_IPR.
+*/
+#define CAN_MOIPR90 (CAN_MO90_IPR)
+
+/** \brief 1B5C, Message Object Control Register */
+#define CAN_MO90_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019B5Cu)
+
+/** Alias (User Manual Name) for CAN_MO90_STAT.
+* To use register names with standard convension, please use CAN_MO90_STAT.
+*/
+#define CAN_MOSTAT90 (CAN_MO90_STAT)
+
+/** \brief 1B6C, Message Object Acceptance Mask Register */
+#define CAN_MO91_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019B6Cu)
+
+/** Alias (User Manual Name) for CAN_MO91_AMR.
+* To use register names with standard convension, please use CAN_MO91_AMR.
+*/
+#define CAN_MOAMR91 (CAN_MO91_AMR)
+
+/** \brief 1B78, Message Object Arbitration Register */
+#define CAN_MO91_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019B78u)
+
+/** Alias (User Manual Name) for CAN_MO91_AR.
+* To use register names with standard convension, please use CAN_MO91_AR.
+*/
+#define CAN_MOAR91 (CAN_MO91_AR)
+
+/** \brief 1B7C, Message Object Control Register */
+#define CAN_MO91_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019B7Cu)
+
+/** Alias (User Manual Name) for CAN_MO91_CTR.
+* To use register names with standard convension, please use CAN_MO91_CTR.
+*/
+#define CAN_MOCTR91 (CAN_MO91_CTR)
+
+/** \brief 1B74, Message Object Data Register High */
+#define CAN_MO91_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019B74u)
+
+/** Alias (User Manual Name) for CAN_MO91_DATAH.
+* To use register names with standard convension, please use CAN_MO91_DATAH.
+*/
+#define CAN_MODATAH91 (CAN_MO91_DATAH)
+
+/** \brief 1B70, Message Object Data Register Low */
+#define CAN_MO91_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019B70u)
+
+/** Alias (User Manual Name) for CAN_MO91_DATAL.
+* To use register names with standard convension, please use CAN_MO91_DATAL.
+*/
+#define CAN_MODATAL91 (CAN_MO91_DATAL)
+
+/** \brief 1B60, Message Object Function Control Register */
+#define CAN_MO91_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019B60u)
+
+/** Alias (User Manual Name) for CAN_MO91_EDATA0.
+* To use register names with standard convension, please use CAN_MO91_EDATA0.
+*/
+#define CAN_EMO91DATA0 (CAN_MO91_EDATA0)
+
+/** \brief 1B64, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO91_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019B64u)
+
+/** Alias (User Manual Name) for CAN_MO91_EDATA1.
+* To use register names with standard convension, please use CAN_MO91_EDATA1.
+*/
+#define CAN_EMO91DATA1 (CAN_MO91_EDATA1)
+
+/** \brief 1B68, Message Object Interrupt Pointer Register */
+#define CAN_MO91_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019B68u)
+
+/** Alias (User Manual Name) for CAN_MO91_EDATA2.
+* To use register names with standard convension, please use CAN_MO91_EDATA2.
+*/
+#define CAN_EMO91DATA2 (CAN_MO91_EDATA2)
+
+/** \brief 1B6C, Message Object Acceptance Mask Register */
+#define CAN_MO91_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019B6Cu)
+
+/** Alias (User Manual Name) for CAN_MO91_EDATA3.
+* To use register names with standard convension, please use CAN_MO91_EDATA3.
+*/
+#define CAN_EMO91DATA3 (CAN_MO91_EDATA3)
+
+/** \brief 1B70, Message Object Data Register Low */
+#define CAN_MO91_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019B70u)
+
+/** Alias (User Manual Name) for CAN_MO91_EDATA4.
+* To use register names with standard convension, please use CAN_MO91_EDATA4.
+*/
+#define CAN_EMO91DATA4 (CAN_MO91_EDATA4)
+
+/** \brief 1B74, Message Object Data Register High */
+#define CAN_MO91_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019B74u)
+
+/** Alias (User Manual Name) for CAN_MO91_EDATA5.
+* To use register names with standard convension, please use CAN_MO91_EDATA5.
+*/
+#define CAN_EMO91DATA5 (CAN_MO91_EDATA5)
+
+/** \brief 1B78, Message Object Arbitration Register */
+#define CAN_MO91_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019B78u)
+
+/** Alias (User Manual Name) for CAN_MO91_EDATA6.
+* To use register names with standard convension, please use CAN_MO91_EDATA6.
+*/
+#define CAN_EMO91DATA6 (CAN_MO91_EDATA6)
+
+/** \brief 1B60, Message Object Function Control Register */
+#define CAN_MO91_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019B60u)
+
+/** Alias (User Manual Name) for CAN_MO91_FCR.
+* To use register names with standard convension, please use CAN_MO91_FCR.
+*/
+#define CAN_MOFCR91 (CAN_MO91_FCR)
+
+/** \brief 1B64, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO91_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019B64u)
+
+/** Alias (User Manual Name) for CAN_MO91_FGPR.
+* To use register names with standard convension, please use CAN_MO91_FGPR.
+*/
+#define CAN_MOFGPR91 (CAN_MO91_FGPR)
+
+/** \brief 1B68, Message Object Interrupt Pointer Register */
+#define CAN_MO91_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019B68u)
+
+/** Alias (User Manual Name) for CAN_MO91_IPR.
+* To use register names with standard convension, please use CAN_MO91_IPR.
+*/
+#define CAN_MOIPR91 (CAN_MO91_IPR)
+
+/** \brief 1B7C, Message Object Control Register */
+#define CAN_MO91_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019B7Cu)
+
+/** Alias (User Manual Name) for CAN_MO91_STAT.
+* To use register names with standard convension, please use CAN_MO91_STAT.
+*/
+#define CAN_MOSTAT91 (CAN_MO91_STAT)
+
+/** \brief 1B8C, Message Object Acceptance Mask Register */
+#define CAN_MO92_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019B8Cu)
+
+/** Alias (User Manual Name) for CAN_MO92_AMR.
+* To use register names with standard convension, please use CAN_MO92_AMR.
+*/
+#define CAN_MOAMR92 (CAN_MO92_AMR)
+
+/** \brief 1B98, Message Object Arbitration Register */
+#define CAN_MO92_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019B98u)
+
+/** Alias (User Manual Name) for CAN_MO92_AR.
+* To use register names with standard convension, please use CAN_MO92_AR.
+*/
+#define CAN_MOAR92 (CAN_MO92_AR)
+
+/** \brief 1B9C, Message Object Control Register */
+#define CAN_MO92_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019B9Cu)
+
+/** Alias (User Manual Name) for CAN_MO92_CTR.
+* To use register names with standard convension, please use CAN_MO92_CTR.
+*/
+#define CAN_MOCTR92 (CAN_MO92_CTR)
+
+/** \brief 1B94, Message Object Data Register High */
+#define CAN_MO92_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019B94u)
+
+/** Alias (User Manual Name) for CAN_MO92_DATAH.
+* To use register names with standard convension, please use CAN_MO92_DATAH.
+*/
+#define CAN_MODATAH92 (CAN_MO92_DATAH)
+
+/** \brief 1B90, Message Object Data Register Low */
+#define CAN_MO92_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019B90u)
+
+/** Alias (User Manual Name) for CAN_MO92_DATAL.
+* To use register names with standard convension, please use CAN_MO92_DATAL.
+*/
+#define CAN_MODATAL92 (CAN_MO92_DATAL)
+
+/** \brief 1B80, Message Object Function Control Register */
+#define CAN_MO92_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019B80u)
+
+/** Alias (User Manual Name) for CAN_MO92_EDATA0.
+* To use register names with standard convension, please use CAN_MO92_EDATA0.
+*/
+#define CAN_EMO92DATA0 (CAN_MO92_EDATA0)
+
+/** \brief 1B84, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO92_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019B84u)
+
+/** Alias (User Manual Name) for CAN_MO92_EDATA1.
+* To use register names with standard convension, please use CAN_MO92_EDATA1.
+*/
+#define CAN_EMO92DATA1 (CAN_MO92_EDATA1)
+
+/** \brief 1B88, Message Object Interrupt Pointer Register */
+#define CAN_MO92_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019B88u)
+
+/** Alias (User Manual Name) for CAN_MO92_EDATA2.
+* To use register names with standard convension, please use CAN_MO92_EDATA2.
+*/
+#define CAN_EMO92DATA2 (CAN_MO92_EDATA2)
+
+/** \brief 1B8C, Message Object Acceptance Mask Register */
+#define CAN_MO92_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019B8Cu)
+
+/** Alias (User Manual Name) for CAN_MO92_EDATA3.
+* To use register names with standard convension, please use CAN_MO92_EDATA3.
+*/
+#define CAN_EMO92DATA3 (CAN_MO92_EDATA3)
+
+/** \brief 1B90, Message Object Data Register Low */
+#define CAN_MO92_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019B90u)
+
+/** Alias (User Manual Name) for CAN_MO92_EDATA4.
+* To use register names with standard convension, please use CAN_MO92_EDATA4.
+*/
+#define CAN_EMO92DATA4 (CAN_MO92_EDATA4)
+
+/** \brief 1B94, Message Object Data Register High */
+#define CAN_MO92_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019B94u)
+
+/** Alias (User Manual Name) for CAN_MO92_EDATA5.
+* To use register names with standard convension, please use CAN_MO92_EDATA5.
+*/
+#define CAN_EMO92DATA5 (CAN_MO92_EDATA5)
+
+/** \brief 1B98, Message Object Arbitration Register */
+#define CAN_MO92_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019B98u)
+
+/** Alias (User Manual Name) for CAN_MO92_EDATA6.
+* To use register names with standard convension, please use CAN_MO92_EDATA6.
+*/
+#define CAN_EMO92DATA6 (CAN_MO92_EDATA6)
+
+/** \brief 1B80, Message Object Function Control Register */
+#define CAN_MO92_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019B80u)
+
+/** Alias (User Manual Name) for CAN_MO92_FCR.
+* To use register names with standard convension, please use CAN_MO92_FCR.
+*/
+#define CAN_MOFCR92 (CAN_MO92_FCR)
+
+/** \brief 1B84, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO92_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019B84u)
+
+/** Alias (User Manual Name) for CAN_MO92_FGPR.
+* To use register names with standard convension, please use CAN_MO92_FGPR.
+*/
+#define CAN_MOFGPR92 (CAN_MO92_FGPR)
+
+/** \brief 1B88, Message Object Interrupt Pointer Register */
+#define CAN_MO92_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019B88u)
+
+/** Alias (User Manual Name) for CAN_MO92_IPR.
+* To use register names with standard convension, please use CAN_MO92_IPR.
+*/
+#define CAN_MOIPR92 (CAN_MO92_IPR)
+
+/** \brief 1B9C, Message Object Control Register */
+#define CAN_MO92_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019B9Cu)
+
+/** Alias (User Manual Name) for CAN_MO92_STAT.
+* To use register names with standard convension, please use CAN_MO92_STAT.
+*/
+#define CAN_MOSTAT92 (CAN_MO92_STAT)
+
+/** \brief 1BAC, Message Object Acceptance Mask Register */
+#define CAN_MO93_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019BACu)
+
+/** Alias (User Manual Name) for CAN_MO93_AMR.
+* To use register names with standard convension, please use CAN_MO93_AMR.
+*/
+#define CAN_MOAMR93 (CAN_MO93_AMR)
+
+/** \brief 1BB8, Message Object Arbitration Register */
+#define CAN_MO93_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019BB8u)
+
+/** Alias (User Manual Name) for CAN_MO93_AR.
+* To use register names with standard convension, please use CAN_MO93_AR.
+*/
+#define CAN_MOAR93 (CAN_MO93_AR)
+
+/** \brief 1BBC, Message Object Control Register */
+#define CAN_MO93_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019BBCu)
+
+/** Alias (User Manual Name) for CAN_MO93_CTR.
+* To use register names with standard convension, please use CAN_MO93_CTR.
+*/
+#define CAN_MOCTR93 (CAN_MO93_CTR)
+
+/** \brief 1BB4, Message Object Data Register High */
+#define CAN_MO93_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019BB4u)
+
+/** Alias (User Manual Name) for CAN_MO93_DATAH.
+* To use register names with standard convension, please use CAN_MO93_DATAH.
+*/
+#define CAN_MODATAH93 (CAN_MO93_DATAH)
+
+/** \brief 1BB0, Message Object Data Register Low */
+#define CAN_MO93_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019BB0u)
+
+/** Alias (User Manual Name) for CAN_MO93_DATAL.
+* To use register names with standard convension, please use CAN_MO93_DATAL.
+*/
+#define CAN_MODATAL93 (CAN_MO93_DATAL)
+
+/** \brief 1BA0, Message Object Function Control Register */
+#define CAN_MO93_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019BA0u)
+
+/** Alias (User Manual Name) for CAN_MO93_EDATA0.
+* To use register names with standard convension, please use CAN_MO93_EDATA0.
+*/
+#define CAN_EMO93DATA0 (CAN_MO93_EDATA0)
+
+/** \brief 1BA4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO93_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019BA4u)
+
+/** Alias (User Manual Name) for CAN_MO93_EDATA1.
+* To use register names with standard convension, please use CAN_MO93_EDATA1.
+*/
+#define CAN_EMO93DATA1 (CAN_MO93_EDATA1)
+
+/** \brief 1BA8, Message Object Interrupt Pointer Register */
+#define CAN_MO93_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019BA8u)
+
+/** Alias (User Manual Name) for CAN_MO93_EDATA2.
+* To use register names with standard convension, please use CAN_MO93_EDATA2.
+*/
+#define CAN_EMO93DATA2 (CAN_MO93_EDATA2)
+
+/** \brief 1BAC, Message Object Acceptance Mask Register */
+#define CAN_MO93_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019BACu)
+
+/** Alias (User Manual Name) for CAN_MO93_EDATA3.
+* To use register names with standard convension, please use CAN_MO93_EDATA3.
+*/
+#define CAN_EMO93DATA3 (CAN_MO93_EDATA3)
+
+/** \brief 1BB0, Message Object Data Register Low */
+#define CAN_MO93_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019BB0u)
+
+/** Alias (User Manual Name) for CAN_MO93_EDATA4.
+* To use register names with standard convension, please use CAN_MO93_EDATA4.
+*/
+#define CAN_EMO93DATA4 (CAN_MO93_EDATA4)
+
+/** \brief 1BB4, Message Object Data Register High */
+#define CAN_MO93_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019BB4u)
+
+/** Alias (User Manual Name) for CAN_MO93_EDATA5.
+* To use register names with standard convension, please use CAN_MO93_EDATA5.
+*/
+#define CAN_EMO93DATA5 (CAN_MO93_EDATA5)
+
+/** \brief 1BB8, Message Object Arbitration Register */
+#define CAN_MO93_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019BB8u)
+
+/** Alias (User Manual Name) for CAN_MO93_EDATA6.
+* To use register names with standard convension, please use CAN_MO93_EDATA6.
+*/
+#define CAN_EMO93DATA6 (CAN_MO93_EDATA6)
+
+/** \brief 1BA0, Message Object Function Control Register */
+#define CAN_MO93_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019BA0u)
+
+/** Alias (User Manual Name) for CAN_MO93_FCR.
+* To use register names with standard convension, please use CAN_MO93_FCR.
+*/
+#define CAN_MOFCR93 (CAN_MO93_FCR)
+
+/** \brief 1BA4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO93_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019BA4u)
+
+/** Alias (User Manual Name) for CAN_MO93_FGPR.
+* To use register names with standard convension, please use CAN_MO93_FGPR.
+*/
+#define CAN_MOFGPR93 (CAN_MO93_FGPR)
+
+/** \brief 1BA8, Message Object Interrupt Pointer Register */
+#define CAN_MO93_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019BA8u)
+
+/** Alias (User Manual Name) for CAN_MO93_IPR.
+* To use register names with standard convension, please use CAN_MO93_IPR.
+*/
+#define CAN_MOIPR93 (CAN_MO93_IPR)
+
+/** \brief 1BBC, Message Object Control Register */
+#define CAN_MO93_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019BBCu)
+
+/** Alias (User Manual Name) for CAN_MO93_STAT.
+* To use register names with standard convension, please use CAN_MO93_STAT.
+*/
+#define CAN_MOSTAT93 (CAN_MO93_STAT)
+
+/** \brief 1BCC, Message Object Acceptance Mask Register */
+#define CAN_MO94_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019BCCu)
+
+/** Alias (User Manual Name) for CAN_MO94_AMR.
+* To use register names with standard convension, please use CAN_MO94_AMR.
+*/
+#define CAN_MOAMR94 (CAN_MO94_AMR)
+
+/** \brief 1BD8, Message Object Arbitration Register */
+#define CAN_MO94_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019BD8u)
+
+/** Alias (User Manual Name) for CAN_MO94_AR.
+* To use register names with standard convension, please use CAN_MO94_AR.
+*/
+#define CAN_MOAR94 (CAN_MO94_AR)
+
+/** \brief 1BDC, Message Object Control Register */
+#define CAN_MO94_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019BDCu)
+
+/** Alias (User Manual Name) for CAN_MO94_CTR.
+* To use register names with standard convension, please use CAN_MO94_CTR.
+*/
+#define CAN_MOCTR94 (CAN_MO94_CTR)
+
+/** \brief 1BD4, Message Object Data Register High */
+#define CAN_MO94_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019BD4u)
+
+/** Alias (User Manual Name) for CAN_MO94_DATAH.
+* To use register names with standard convension, please use CAN_MO94_DATAH.
+*/
+#define CAN_MODATAH94 (CAN_MO94_DATAH)
+
+/** \brief 1BD0, Message Object Data Register Low */
+#define CAN_MO94_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019BD0u)
+
+/** Alias (User Manual Name) for CAN_MO94_DATAL.
+* To use register names with standard convension, please use CAN_MO94_DATAL.
+*/
+#define CAN_MODATAL94 (CAN_MO94_DATAL)
+
+/** \brief 1BC0, Message Object Function Control Register */
+#define CAN_MO94_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019BC0u)
+
+/** Alias (User Manual Name) for CAN_MO94_EDATA0.
+* To use register names with standard convension, please use CAN_MO94_EDATA0.
+*/
+#define CAN_EMO94DATA0 (CAN_MO94_EDATA0)
+
+/** \brief 1BC4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO94_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019BC4u)
+
+/** Alias (User Manual Name) for CAN_MO94_EDATA1.
+* To use register names with standard convension, please use CAN_MO94_EDATA1.
+*/
+#define CAN_EMO94DATA1 (CAN_MO94_EDATA1)
+
+/** \brief 1BC8, Message Object Interrupt Pointer Register */
+#define CAN_MO94_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019BC8u)
+
+/** Alias (User Manual Name) for CAN_MO94_EDATA2.
+* To use register names with standard convension, please use CAN_MO94_EDATA2.
+*/
+#define CAN_EMO94DATA2 (CAN_MO94_EDATA2)
+
+/** \brief 1BCC, Message Object Acceptance Mask Register */
+#define CAN_MO94_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019BCCu)
+
+/** Alias (User Manual Name) for CAN_MO94_EDATA3.
+* To use register names with standard convension, please use CAN_MO94_EDATA3.
+*/
+#define CAN_EMO94DATA3 (CAN_MO94_EDATA3)
+
+/** \brief 1BD0, Message Object Data Register Low */
+#define CAN_MO94_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019BD0u)
+
+/** Alias (User Manual Name) for CAN_MO94_EDATA4.
+* To use register names with standard convension, please use CAN_MO94_EDATA4.
+*/
+#define CAN_EMO94DATA4 (CAN_MO94_EDATA4)
+
+/** \brief 1BD4, Message Object Data Register High */
+#define CAN_MO94_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019BD4u)
+
+/** Alias (User Manual Name) for CAN_MO94_EDATA5.
+* To use register names with standard convension, please use CAN_MO94_EDATA5.
+*/
+#define CAN_EMO94DATA5 (CAN_MO94_EDATA5)
+
+/** \brief 1BD8, Message Object Arbitration Register */
+#define CAN_MO94_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019BD8u)
+
+/** Alias (User Manual Name) for CAN_MO94_EDATA6.
+* To use register names with standard convension, please use CAN_MO94_EDATA6.
+*/
+#define CAN_EMO94DATA6 (CAN_MO94_EDATA6)
+
+/** \brief 1BC0, Message Object Function Control Register */
+#define CAN_MO94_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019BC0u)
+
+/** Alias (User Manual Name) for CAN_MO94_FCR.
+* To use register names with standard convension, please use CAN_MO94_FCR.
+*/
+#define CAN_MOFCR94 (CAN_MO94_FCR)
+
+/** \brief 1BC4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO94_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019BC4u)
+
+/** Alias (User Manual Name) for CAN_MO94_FGPR.
+* To use register names with standard convension, please use CAN_MO94_FGPR.
+*/
+#define CAN_MOFGPR94 (CAN_MO94_FGPR)
+
+/** \brief 1BC8, Message Object Interrupt Pointer Register */
+#define CAN_MO94_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019BC8u)
+
+/** Alias (User Manual Name) for CAN_MO94_IPR.
+* To use register names with standard convension, please use CAN_MO94_IPR.
+*/
+#define CAN_MOIPR94 (CAN_MO94_IPR)
+
+/** \brief 1BDC, Message Object Control Register */
+#define CAN_MO94_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019BDCu)
+
+/** Alias (User Manual Name) for CAN_MO94_STAT.
+* To use register names with standard convension, please use CAN_MO94_STAT.
+*/
+#define CAN_MOSTAT94 (CAN_MO94_STAT)
+
+/** \brief 1BEC, Message Object Acceptance Mask Register */
+#define CAN_MO95_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019BECu)
+
+/** Alias (User Manual Name) for CAN_MO95_AMR.
+* To use register names with standard convension, please use CAN_MO95_AMR.
+*/
+#define CAN_MOAMR95 (CAN_MO95_AMR)
+
+/** \brief 1BF8, Message Object Arbitration Register */
+#define CAN_MO95_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019BF8u)
+
+/** Alias (User Manual Name) for CAN_MO95_AR.
+* To use register names with standard convension, please use CAN_MO95_AR.
+*/
+#define CAN_MOAR95 (CAN_MO95_AR)
+
+/** \brief 1BFC, Message Object Control Register */
+#define CAN_MO95_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019BFCu)
+
+/** Alias (User Manual Name) for CAN_MO95_CTR.
+* To use register names with standard convension, please use CAN_MO95_CTR.
+*/
+#define CAN_MOCTR95 (CAN_MO95_CTR)
+
+/** \brief 1BF4, Message Object Data Register High */
+#define CAN_MO95_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019BF4u)
+
+/** Alias (User Manual Name) for CAN_MO95_DATAH.
+* To use register names with standard convension, please use CAN_MO95_DATAH.
+*/
+#define CAN_MODATAH95 (CAN_MO95_DATAH)
+
+/** \brief 1BF0, Message Object Data Register Low */
+#define CAN_MO95_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019BF0u)
+
+/** Alias (User Manual Name) for CAN_MO95_DATAL.
+* To use register names with standard convension, please use CAN_MO95_DATAL.
+*/
+#define CAN_MODATAL95 (CAN_MO95_DATAL)
+
+/** \brief 1BE0, Message Object Function Control Register */
+#define CAN_MO95_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019BE0u)
+
+/** Alias (User Manual Name) for CAN_MO95_EDATA0.
+* To use register names with standard convension, please use CAN_MO95_EDATA0.
+*/
+#define CAN_EMO95DATA0 (CAN_MO95_EDATA0)
+
+/** \brief 1BE4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO95_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019BE4u)
+
+/** Alias (User Manual Name) for CAN_MO95_EDATA1.
+* To use register names with standard convension, please use CAN_MO95_EDATA1.
+*/
+#define CAN_EMO95DATA1 (CAN_MO95_EDATA1)
+
+/** \brief 1BE8, Message Object Interrupt Pointer Register */
+#define CAN_MO95_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019BE8u)
+
+/** Alias (User Manual Name) for CAN_MO95_EDATA2.
+* To use register names with standard convension, please use CAN_MO95_EDATA2.
+*/
+#define CAN_EMO95DATA2 (CAN_MO95_EDATA2)
+
+/** \brief 1BEC, Message Object Acceptance Mask Register */
+#define CAN_MO95_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019BECu)
+
+/** Alias (User Manual Name) for CAN_MO95_EDATA3.
+* To use register names with standard convension, please use CAN_MO95_EDATA3.
+*/
+#define CAN_EMO95DATA3 (CAN_MO95_EDATA3)
+
+/** \brief 1BF0, Message Object Data Register Low */
+#define CAN_MO95_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019BF0u)
+
+/** Alias (User Manual Name) for CAN_MO95_EDATA4.
+* To use register names with standard convension, please use CAN_MO95_EDATA4.
+*/
+#define CAN_EMO95DATA4 (CAN_MO95_EDATA4)
+
+/** \brief 1BF4, Message Object Data Register High */
+#define CAN_MO95_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019BF4u)
+
+/** Alias (User Manual Name) for CAN_MO95_EDATA5.
+* To use register names with standard convension, please use CAN_MO95_EDATA5.
+*/
+#define CAN_EMO95DATA5 (CAN_MO95_EDATA5)
+
+/** \brief 1BF8, Message Object Arbitration Register */
+#define CAN_MO95_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019BF8u)
+
+/** Alias (User Manual Name) for CAN_MO95_EDATA6.
+* To use register names with standard convension, please use CAN_MO95_EDATA6.
+*/
+#define CAN_EMO95DATA6 (CAN_MO95_EDATA6)
+
+/** \brief 1BE0, Message Object Function Control Register */
+#define CAN_MO95_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019BE0u)
+
+/** Alias (User Manual Name) for CAN_MO95_FCR.
+* To use register names with standard convension, please use CAN_MO95_FCR.
+*/
+#define CAN_MOFCR95 (CAN_MO95_FCR)
+
+/** \brief 1BE4, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO95_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019BE4u)
+
+/** Alias (User Manual Name) for CAN_MO95_FGPR.
+* To use register names with standard convension, please use CAN_MO95_FGPR.
+*/
+#define CAN_MOFGPR95 (CAN_MO95_FGPR)
+
+/** \brief 1BE8, Message Object Interrupt Pointer Register */
+#define CAN_MO95_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019BE8u)
+
+/** Alias (User Manual Name) for CAN_MO95_IPR.
+* To use register names with standard convension, please use CAN_MO95_IPR.
+*/
+#define CAN_MOIPR95 (CAN_MO95_IPR)
+
+/** \brief 1BFC, Message Object Control Register */
+#define CAN_MO95_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019BFCu)
+
+/** Alias (User Manual Name) for CAN_MO95_STAT.
+* To use register names with standard convension, please use CAN_MO95_STAT.
+*/
+#define CAN_MOSTAT95 (CAN_MO95_STAT)
+
+/** \brief 1C0C, Message Object Acceptance Mask Register */
+#define CAN_MO96_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019C0Cu)
+
+/** Alias (User Manual Name) for CAN_MO96_AMR.
+* To use register names with standard convension, please use CAN_MO96_AMR.
+*/
+#define CAN_MOAMR96 (CAN_MO96_AMR)
+
+/** \brief 1C18, Message Object Arbitration Register */
+#define CAN_MO96_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019C18u)
+
+/** Alias (User Manual Name) for CAN_MO96_AR.
+* To use register names with standard convension, please use CAN_MO96_AR.
+*/
+#define CAN_MOAR96 (CAN_MO96_AR)
+
+/** \brief 1C1C, Message Object Control Register */
+#define CAN_MO96_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019C1Cu)
+
+/** Alias (User Manual Name) for CAN_MO96_CTR.
+* To use register names with standard convension, please use CAN_MO96_CTR.
+*/
+#define CAN_MOCTR96 (CAN_MO96_CTR)
+
+/** \brief 1C14, Message Object Data Register High */
+#define CAN_MO96_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019C14u)
+
+/** Alias (User Manual Name) for CAN_MO96_DATAH.
+* To use register names with standard convension, please use CAN_MO96_DATAH.
+*/
+#define CAN_MODATAH96 (CAN_MO96_DATAH)
+
+/** \brief 1C10, Message Object Data Register Low */
+#define CAN_MO96_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019C10u)
+
+/** Alias (User Manual Name) for CAN_MO96_DATAL.
+* To use register names with standard convension, please use CAN_MO96_DATAL.
+*/
+#define CAN_MODATAL96 (CAN_MO96_DATAL)
+
+/** \brief 1C00, Message Object Function Control Register */
+#define CAN_MO96_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019C00u)
+
+/** Alias (User Manual Name) for CAN_MO96_EDATA0.
+* To use register names with standard convension, please use CAN_MO96_EDATA0.
+*/
+#define CAN_EMO96DATA0 (CAN_MO96_EDATA0)
+
+/** \brief 1C04, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO96_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019C04u)
+
+/** Alias (User Manual Name) for CAN_MO96_EDATA1.
+* To use register names with standard convension, please use CAN_MO96_EDATA1.
+*/
+#define CAN_EMO96DATA1 (CAN_MO96_EDATA1)
+
+/** \brief 1C08, Message Object Interrupt Pointer Register */
+#define CAN_MO96_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019C08u)
+
+/** Alias (User Manual Name) for CAN_MO96_EDATA2.
+* To use register names with standard convension, please use CAN_MO96_EDATA2.
+*/
+#define CAN_EMO96DATA2 (CAN_MO96_EDATA2)
+
+/** \brief 1C0C, Message Object Acceptance Mask Register */
+#define CAN_MO96_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019C0Cu)
+
+/** Alias (User Manual Name) for CAN_MO96_EDATA3.
+* To use register names with standard convension, please use CAN_MO96_EDATA3.
+*/
+#define CAN_EMO96DATA3 (CAN_MO96_EDATA3)
+
+/** \brief 1C10, Message Object Data Register Low */
+#define CAN_MO96_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019C10u)
+
+/** Alias (User Manual Name) for CAN_MO96_EDATA4.
+* To use register names with standard convension, please use CAN_MO96_EDATA4.
+*/
+#define CAN_EMO96DATA4 (CAN_MO96_EDATA4)
+
+/** \brief 1C14, Message Object Data Register High */
+#define CAN_MO96_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019C14u)
+
+/** Alias (User Manual Name) for CAN_MO96_EDATA5.
+* To use register names with standard convension, please use CAN_MO96_EDATA5.
+*/
+#define CAN_EMO96DATA5 (CAN_MO96_EDATA5)
+
+/** \brief 1C18, Message Object Arbitration Register */
+#define CAN_MO96_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019C18u)
+
+/** Alias (User Manual Name) for CAN_MO96_EDATA6.
+* To use register names with standard convension, please use CAN_MO96_EDATA6.
+*/
+#define CAN_EMO96DATA6 (CAN_MO96_EDATA6)
+
+/** \brief 1C00, Message Object Function Control Register */
+#define CAN_MO96_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019C00u)
+
+/** Alias (User Manual Name) for CAN_MO96_FCR.
+* To use register names with standard convension, please use CAN_MO96_FCR.
+*/
+#define CAN_MOFCR96 (CAN_MO96_FCR)
+
+/** \brief 1C04, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO96_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019C04u)
+
+/** Alias (User Manual Name) for CAN_MO96_FGPR.
+* To use register names with standard convension, please use CAN_MO96_FGPR.
+*/
+#define CAN_MOFGPR96 (CAN_MO96_FGPR)
+
+/** \brief 1C08, Message Object Interrupt Pointer Register */
+#define CAN_MO96_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019C08u)
+
+/** Alias (User Manual Name) for CAN_MO96_IPR.
+* To use register names with standard convension, please use CAN_MO96_IPR.
+*/
+#define CAN_MOIPR96 (CAN_MO96_IPR)
+
+/** \brief 1C1C, Message Object Control Register */
+#define CAN_MO96_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019C1Cu)
+
+/** Alias (User Manual Name) for CAN_MO96_STAT.
+* To use register names with standard convension, please use CAN_MO96_STAT.
+*/
+#define CAN_MOSTAT96 (CAN_MO96_STAT)
+
+/** \brief 1C2C, Message Object Acceptance Mask Register */
+#define CAN_MO97_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019C2Cu)
+
+/** Alias (User Manual Name) for CAN_MO97_AMR.
+* To use register names with standard convension, please use CAN_MO97_AMR.
+*/
+#define CAN_MOAMR97 (CAN_MO97_AMR)
+
+/** \brief 1C38, Message Object Arbitration Register */
+#define CAN_MO97_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019C38u)
+
+/** Alias (User Manual Name) for CAN_MO97_AR.
+* To use register names with standard convension, please use CAN_MO97_AR.
+*/
+#define CAN_MOAR97 (CAN_MO97_AR)
+
+/** \brief 1C3C, Message Object Control Register */
+#define CAN_MO97_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019C3Cu)
+
+/** Alias (User Manual Name) for CAN_MO97_CTR.
+* To use register names with standard convension, please use CAN_MO97_CTR.
+*/
+#define CAN_MOCTR97 (CAN_MO97_CTR)
+
+/** \brief 1C34, Message Object Data Register High */
+#define CAN_MO97_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019C34u)
+
+/** Alias (User Manual Name) for CAN_MO97_DATAH.
+* To use register names with standard convension, please use CAN_MO97_DATAH.
+*/
+#define CAN_MODATAH97 (CAN_MO97_DATAH)
+
+/** \brief 1C30, Message Object Data Register Low */
+#define CAN_MO97_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019C30u)
+
+/** Alias (User Manual Name) for CAN_MO97_DATAL.
+* To use register names with standard convension, please use CAN_MO97_DATAL.
+*/
+#define CAN_MODATAL97 (CAN_MO97_DATAL)
+
+/** \brief 1C20, Message Object Function Control Register */
+#define CAN_MO97_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019C20u)
+
+/** Alias (User Manual Name) for CAN_MO97_EDATA0.
+* To use register names with standard convension, please use CAN_MO97_EDATA0.
+*/
+#define CAN_EMO97DATA0 (CAN_MO97_EDATA0)
+
+/** \brief 1C24, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO97_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019C24u)
+
+/** Alias (User Manual Name) for CAN_MO97_EDATA1.
+* To use register names with standard convension, please use CAN_MO97_EDATA1.
+*/
+#define CAN_EMO97DATA1 (CAN_MO97_EDATA1)
+
+/** \brief 1C28, Message Object Interrupt Pointer Register */
+#define CAN_MO97_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019C28u)
+
+/** Alias (User Manual Name) for CAN_MO97_EDATA2.
+* To use register names with standard convension, please use CAN_MO97_EDATA2.
+*/
+#define CAN_EMO97DATA2 (CAN_MO97_EDATA2)
+
+/** \brief 1C2C, Message Object Acceptance Mask Register */
+#define CAN_MO97_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019C2Cu)
+
+/** Alias (User Manual Name) for CAN_MO97_EDATA3.
+* To use register names with standard convension, please use CAN_MO97_EDATA3.
+*/
+#define CAN_EMO97DATA3 (CAN_MO97_EDATA3)
+
+/** \brief 1C30, Message Object Data Register Low */
+#define CAN_MO97_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019C30u)
+
+/** Alias (User Manual Name) for CAN_MO97_EDATA4.
+* To use register names with standard convension, please use CAN_MO97_EDATA4.
+*/
+#define CAN_EMO97DATA4 (CAN_MO97_EDATA4)
+
+/** \brief 1C34, Message Object Data Register High */
+#define CAN_MO97_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019C34u)
+
+/** Alias (User Manual Name) for CAN_MO97_EDATA5.
+* To use register names with standard convension, please use CAN_MO97_EDATA5.
+*/
+#define CAN_EMO97DATA5 (CAN_MO97_EDATA5)
+
+/** \brief 1C38, Message Object Arbitration Register */
+#define CAN_MO97_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019C38u)
+
+/** Alias (User Manual Name) for CAN_MO97_EDATA6.
+* To use register names with standard convension, please use CAN_MO97_EDATA6.
+*/
+#define CAN_EMO97DATA6 (CAN_MO97_EDATA6)
+
+/** \brief 1C20, Message Object Function Control Register */
+#define CAN_MO97_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019C20u)
+
+/** Alias (User Manual Name) for CAN_MO97_FCR.
+* To use register names with standard convension, please use CAN_MO97_FCR.
+*/
+#define CAN_MOFCR97 (CAN_MO97_FCR)
+
+/** \brief 1C24, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO97_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019C24u)
+
+/** Alias (User Manual Name) for CAN_MO97_FGPR.
+* To use register names with standard convension, please use CAN_MO97_FGPR.
+*/
+#define CAN_MOFGPR97 (CAN_MO97_FGPR)
+
+/** \brief 1C28, Message Object Interrupt Pointer Register */
+#define CAN_MO97_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019C28u)
+
+/** Alias (User Manual Name) for CAN_MO97_IPR.
+* To use register names with standard convension, please use CAN_MO97_IPR.
+*/
+#define CAN_MOIPR97 (CAN_MO97_IPR)
+
+/** \brief 1C3C, Message Object Control Register */
+#define CAN_MO97_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019C3Cu)
+
+/** Alias (User Manual Name) for CAN_MO97_STAT.
+* To use register names with standard convension, please use CAN_MO97_STAT.
+*/
+#define CAN_MOSTAT97 (CAN_MO97_STAT)
+
+/** \brief 1C4C, Message Object Acceptance Mask Register */
+#define CAN_MO98_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019C4Cu)
+
+/** Alias (User Manual Name) for CAN_MO98_AMR.
+* To use register names with standard convension, please use CAN_MO98_AMR.
+*/
+#define CAN_MOAMR98 (CAN_MO98_AMR)
+
+/** \brief 1C58, Message Object Arbitration Register */
+#define CAN_MO98_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019C58u)
+
+/** Alias (User Manual Name) for CAN_MO98_AR.
+* To use register names with standard convension, please use CAN_MO98_AR.
+*/
+#define CAN_MOAR98 (CAN_MO98_AR)
+
+/** \brief 1C5C, Message Object Control Register */
+#define CAN_MO98_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019C5Cu)
+
+/** Alias (User Manual Name) for CAN_MO98_CTR.
+* To use register names with standard convension, please use CAN_MO98_CTR.
+*/
+#define CAN_MOCTR98 (CAN_MO98_CTR)
+
+/** \brief 1C54, Message Object Data Register High */
+#define CAN_MO98_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019C54u)
+
+/** Alias (User Manual Name) for CAN_MO98_DATAH.
+* To use register names with standard convension, please use CAN_MO98_DATAH.
+*/
+#define CAN_MODATAH98 (CAN_MO98_DATAH)
+
+/** \brief 1C50, Message Object Data Register Low */
+#define CAN_MO98_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019C50u)
+
+/** Alias (User Manual Name) for CAN_MO98_DATAL.
+* To use register names with standard convension, please use CAN_MO98_DATAL.
+*/
+#define CAN_MODATAL98 (CAN_MO98_DATAL)
+
+/** \brief 1C40, Message Object Function Control Register */
+#define CAN_MO98_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019C40u)
+
+/** Alias (User Manual Name) for CAN_MO98_EDATA0.
+* To use register names with standard convension, please use CAN_MO98_EDATA0.
+*/
+#define CAN_EMO98DATA0 (CAN_MO98_EDATA0)
+
+/** \brief 1C44, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO98_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019C44u)
+
+/** Alias (User Manual Name) for CAN_MO98_EDATA1.
+* To use register names with standard convension, please use CAN_MO98_EDATA1.
+*/
+#define CAN_EMO98DATA1 (CAN_MO98_EDATA1)
+
+/** \brief 1C48, Message Object Interrupt Pointer Register */
+#define CAN_MO98_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019C48u)
+
+/** Alias (User Manual Name) for CAN_MO98_EDATA2.
+* To use register names with standard convension, please use CAN_MO98_EDATA2.
+*/
+#define CAN_EMO98DATA2 (CAN_MO98_EDATA2)
+
+/** \brief 1C4C, Message Object Acceptance Mask Register */
+#define CAN_MO98_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019C4Cu)
+
+/** Alias (User Manual Name) for CAN_MO98_EDATA3.
+* To use register names with standard convension, please use CAN_MO98_EDATA3.
+*/
+#define CAN_EMO98DATA3 (CAN_MO98_EDATA3)
+
+/** \brief 1C50, Message Object Data Register Low */
+#define CAN_MO98_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019C50u)
+
+/** Alias (User Manual Name) for CAN_MO98_EDATA4.
+* To use register names with standard convension, please use CAN_MO98_EDATA4.
+*/
+#define CAN_EMO98DATA4 (CAN_MO98_EDATA4)
+
+/** \brief 1C54, Message Object Data Register High */
+#define CAN_MO98_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019C54u)
+
+/** Alias (User Manual Name) for CAN_MO98_EDATA5.
+* To use register names with standard convension, please use CAN_MO98_EDATA5.
+*/
+#define CAN_EMO98DATA5 (CAN_MO98_EDATA5)
+
+/** \brief 1C58, Message Object Arbitration Register */
+#define CAN_MO98_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019C58u)
+
+/** Alias (User Manual Name) for CAN_MO98_EDATA6.
+* To use register names with standard convension, please use CAN_MO98_EDATA6.
+*/
+#define CAN_EMO98DATA6 (CAN_MO98_EDATA6)
+
+/** \brief 1C40, Message Object Function Control Register */
+#define CAN_MO98_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019C40u)
+
+/** Alias (User Manual Name) for CAN_MO98_FCR.
+* To use register names with standard convension, please use CAN_MO98_FCR.
+*/
+#define CAN_MOFCR98 (CAN_MO98_FCR)
+
+/** \brief 1C44, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO98_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019C44u)
+
+/** Alias (User Manual Name) for CAN_MO98_FGPR.
+* To use register names with standard convension, please use CAN_MO98_FGPR.
+*/
+#define CAN_MOFGPR98 (CAN_MO98_FGPR)
+
+/** \brief 1C48, Message Object Interrupt Pointer Register */
+#define CAN_MO98_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019C48u)
+
+/** Alias (User Manual Name) for CAN_MO98_IPR.
+* To use register names with standard convension, please use CAN_MO98_IPR.
+*/
+#define CAN_MOIPR98 (CAN_MO98_IPR)
+
+/** \brief 1C5C, Message Object Control Register */
+#define CAN_MO98_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019C5Cu)
+
+/** Alias (User Manual Name) for CAN_MO98_STAT.
+* To use register names with standard convension, please use CAN_MO98_STAT.
+*/
+#define CAN_MOSTAT98 (CAN_MO98_STAT)
+
+/** \brief 1C6C, Message Object Acceptance Mask Register */
+#define CAN_MO99_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019C6Cu)
+
+/** Alias (User Manual Name) for CAN_MO99_AMR.
+* To use register names with standard convension, please use CAN_MO99_AMR.
+*/
+#define CAN_MOAMR99 (CAN_MO99_AMR)
+
+/** \brief 1C78, Message Object Arbitration Register */
+#define CAN_MO99_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019C78u)
+
+/** Alias (User Manual Name) for CAN_MO99_AR.
+* To use register names with standard convension, please use CAN_MO99_AR.
+*/
+#define CAN_MOAR99 (CAN_MO99_AR)
+
+/** \brief 1C7C, Message Object Control Register */
+#define CAN_MO99_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019C7Cu)
+
+/** Alias (User Manual Name) for CAN_MO99_CTR.
+* To use register names with standard convension, please use CAN_MO99_CTR.
+*/
+#define CAN_MOCTR99 (CAN_MO99_CTR)
+
+/** \brief 1C74, Message Object Data Register High */
+#define CAN_MO99_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019C74u)
+
+/** Alias (User Manual Name) for CAN_MO99_DATAH.
+* To use register names with standard convension, please use CAN_MO99_DATAH.
+*/
+#define CAN_MODATAH99 (CAN_MO99_DATAH)
+
+/** \brief 1C70, Message Object Data Register Low */
+#define CAN_MO99_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019C70u)
+
+/** Alias (User Manual Name) for CAN_MO99_DATAL.
+* To use register names with standard convension, please use CAN_MO99_DATAL.
+*/
+#define CAN_MODATAL99 (CAN_MO99_DATAL)
+
+/** \brief 1C60, Message Object Function Control Register */
+#define CAN_MO99_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019C60u)
+
+/** Alias (User Manual Name) for CAN_MO99_EDATA0.
+* To use register names with standard convension, please use CAN_MO99_EDATA0.
+*/
+#define CAN_EMO99DATA0 (CAN_MO99_EDATA0)
+
+/** \brief 1C64, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO99_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019C64u)
+
+/** Alias (User Manual Name) for CAN_MO99_EDATA1.
+* To use register names with standard convension, please use CAN_MO99_EDATA1.
+*/
+#define CAN_EMO99DATA1 (CAN_MO99_EDATA1)
+
+/** \brief 1C68, Message Object Interrupt Pointer Register */
+#define CAN_MO99_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019C68u)
+
+/** Alias (User Manual Name) for CAN_MO99_EDATA2.
+* To use register names with standard convension, please use CAN_MO99_EDATA2.
+*/
+#define CAN_EMO99DATA2 (CAN_MO99_EDATA2)
+
+/** \brief 1C6C, Message Object Acceptance Mask Register */
+#define CAN_MO99_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019C6Cu)
+
+/** Alias (User Manual Name) for CAN_MO99_EDATA3.
+* To use register names with standard convension, please use CAN_MO99_EDATA3.
+*/
+#define CAN_EMO99DATA3 (CAN_MO99_EDATA3)
+
+/** \brief 1C70, Message Object Data Register Low */
+#define CAN_MO99_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019C70u)
+
+/** Alias (User Manual Name) for CAN_MO99_EDATA4.
+* To use register names with standard convension, please use CAN_MO99_EDATA4.
+*/
+#define CAN_EMO99DATA4 (CAN_MO99_EDATA4)
+
+/** \brief 1C74, Message Object Data Register High */
+#define CAN_MO99_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019C74u)
+
+/** Alias (User Manual Name) for CAN_MO99_EDATA5.
+* To use register names with standard convension, please use CAN_MO99_EDATA5.
+*/
+#define CAN_EMO99DATA5 (CAN_MO99_EDATA5)
+
+/** \brief 1C78, Message Object Arbitration Register */
+#define CAN_MO99_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019C78u)
+
+/** Alias (User Manual Name) for CAN_MO99_EDATA6.
+* To use register names with standard convension, please use CAN_MO99_EDATA6.
+*/
+#define CAN_EMO99DATA6 (CAN_MO99_EDATA6)
+
+/** \brief 1C60, Message Object Function Control Register */
+#define CAN_MO99_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019C60u)
+
+/** Alias (User Manual Name) for CAN_MO99_FCR.
+* To use register names with standard convension, please use CAN_MO99_FCR.
+*/
+#define CAN_MOFCR99 (CAN_MO99_FCR)
+
+/** \brief 1C64, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO99_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019C64u)
+
+/** Alias (User Manual Name) for CAN_MO99_FGPR.
+* To use register names with standard convension, please use CAN_MO99_FGPR.
+*/
+#define CAN_MOFGPR99 (CAN_MO99_FGPR)
+
+/** \brief 1C68, Message Object Interrupt Pointer Register */
+#define CAN_MO99_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019C68u)
+
+/** Alias (User Manual Name) for CAN_MO99_IPR.
+* To use register names with standard convension, please use CAN_MO99_IPR.
+*/
+#define CAN_MOIPR99 (CAN_MO99_IPR)
+
+/** \brief 1C7C, Message Object Control Register */
+#define CAN_MO99_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019C7Cu)
+
+/** Alias (User Manual Name) for CAN_MO99_STAT.
+* To use register names with standard convension, please use CAN_MO99_STAT.
+*/
+#define CAN_MOSTAT99 (CAN_MO99_STAT)
+
+/** \brief 112C, Message Object Acceptance Mask Register */
+#define CAN_MO9_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001912Cu)
+
+/** Alias (User Manual Name) for CAN_MO9_AMR.
+* To use register names with standard convension, please use CAN_MO9_AMR.
+*/
+#define CAN_MOAMR9 (CAN_MO9_AMR)
+
+/** \brief 1138, Message Object Arbitration Register */
+#define CAN_MO9_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019138u)
+
+/** Alias (User Manual Name) for CAN_MO9_AR.
+* To use register names with standard convension, please use CAN_MO9_AR.
+*/
+#define CAN_MOAR9 (CAN_MO9_AR)
+
+/** \brief 113C, Message Object Control Register */
+#define CAN_MO9_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001913Cu)
+
+/** Alias (User Manual Name) for CAN_MO9_CTR.
+* To use register names with standard convension, please use CAN_MO9_CTR.
+*/
+#define CAN_MOCTR9 (CAN_MO9_CTR)
+
+/** \brief 1134, Message Object Data Register High */
+#define CAN_MO9_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019134u)
+
+/** Alias (User Manual Name) for CAN_MO9_DATAH.
+* To use register names with standard convension, please use CAN_MO9_DATAH.
+*/
+#define CAN_MODATAH9 (CAN_MO9_DATAH)
+
+/** \brief 1130, Message Object Data Register Low */
+#define CAN_MO9_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019130u)
+
+/** Alias (User Manual Name) for CAN_MO9_DATAL.
+* To use register names with standard convension, please use CAN_MO9_DATAL.
+*/
+#define CAN_MODATAL9 (CAN_MO9_DATAL)
+
+/** \brief 1120, Message Object Function Control Register */
+#define CAN_MO9_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019120u)
+
+/** Alias (User Manual Name) for CAN_MO9_EDATA0.
+* To use register names with standard convension, please use CAN_MO9_EDATA0.
+*/
+#define CAN_EMO9DATA0 (CAN_MO9_EDATA0)
+
+/** \brief 1124, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO9_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019124u)
+
+/** Alias (User Manual Name) for CAN_MO9_EDATA1.
+* To use register names with standard convension, please use CAN_MO9_EDATA1.
+*/
+#define CAN_EMO9DATA1 (CAN_MO9_EDATA1)
+
+/** \brief 1128, Message Object Interrupt Pointer Register */
+#define CAN_MO9_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019128u)
+
+/** Alias (User Manual Name) for CAN_MO9_EDATA2.
+* To use register names with standard convension, please use CAN_MO9_EDATA2.
+*/
+#define CAN_EMO9DATA2 (CAN_MO9_EDATA2)
+
+/** \brief 112C, Message Object Acceptance Mask Register */
+#define CAN_MO9_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001912Cu)
+
+/** Alias (User Manual Name) for CAN_MO9_EDATA3.
+* To use register names with standard convension, please use CAN_MO9_EDATA3.
+*/
+#define CAN_EMO9DATA3 (CAN_MO9_EDATA3)
+
+/** \brief 1130, Message Object Data Register Low */
+#define CAN_MO9_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019130u)
+
+/** Alias (User Manual Name) for CAN_MO9_EDATA4.
+* To use register names with standard convension, please use CAN_MO9_EDATA4.
+*/
+#define CAN_EMO9DATA4 (CAN_MO9_EDATA4)
+
+/** \brief 1134, Message Object Data Register High */
+#define CAN_MO9_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019134u)
+
+/** Alias (User Manual Name) for CAN_MO9_EDATA5.
+* To use register names with standard convension, please use CAN_MO9_EDATA5.
+*/
+#define CAN_EMO9DATA5 (CAN_MO9_EDATA5)
+
+/** \brief 1138, Message Object Arbitration Register */
+#define CAN_MO9_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019138u)
+
+/** Alias (User Manual Name) for CAN_MO9_EDATA6.
+* To use register names with standard convension, please use CAN_MO9_EDATA6.
+*/
+#define CAN_EMO9DATA6 (CAN_MO9_EDATA6)
+
+/** \brief 1120, Message Object Function Control Register */
+#define CAN_MO9_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019120u)
+
+/** Alias (User Manual Name) for CAN_MO9_FCR.
+* To use register names with standard convension, please use CAN_MO9_FCR.
+*/
+#define CAN_MOFCR9 (CAN_MO9_FCR)
+
+/** \brief 1124, Message Object FIFO/Gateway Pointer Register */
+#define CAN_MO9_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019124u)
+
+/** Alias (User Manual Name) for CAN_MO9_FGPR.
+* To use register names with standard convension, please use CAN_MO9_FGPR.
+*/
+#define CAN_MOFGPR9 (CAN_MO9_FGPR)
+
+/** \brief 1128, Message Object Interrupt Pointer Register */
+#define CAN_MO9_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019128u)
+
+/** Alias (User Manual Name) for CAN_MO9_IPR.
+* To use register names with standard convension, please use CAN_MO9_IPR.
+*/
+#define CAN_MOIPR9 (CAN_MO9_IPR)
+
+/** \brief 113C, Message Object Control Register */
+#define CAN_MO9_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001913Cu)
+
+/** Alias (User Manual Name) for CAN_MO9_STAT.
+* To use register names with standard convension, please use CAN_MO9_STAT.
+*/
+#define CAN_MOSTAT9 (CAN_MO9_STAT)
+
+/** \brief 180, Message Index Register */
+#define CAN_MSID0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF0018180u)
+
+/** \brief 184, Message Index Register */
+#define CAN_MSID1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF0018184u)
+
+/** \brief 188, Message Index Register */
+#define CAN_MSID2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF0018188u)
+
+/** \brief 18C, Message Index Register */
+#define CAN_MSID3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF001818Cu)
+
+/** \brief 190, Message Index Register */
+#define CAN_MSID4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF0018190u)
+
+/** \brief 194, Message Index Register */
+#define CAN_MSID5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF0018194u)
+
+/** \brief 198, Message Index Register */
+#define CAN_MSID6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF0018198u)
+
+/** \brief 19C, Message Index Register */
+#define CAN_MSID7 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF001819Cu)
+
+/** \brief 1C0, Message Index Mask Register */
+#define CAN_MSIMASK /*lint --e(923)*/ (*(volatile Ifx_CAN_MSIMASK*)0xF00181C0u)
+
+/** \brief 140, Message Pending Register */
+#define CAN_MSPND0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF0018140u)
+
+/** \brief 144, Message Pending Register */
+#define CAN_MSPND1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF0018144u)
+
+/** \brief 148, Message Pending Register */
+#define CAN_MSPND2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF0018148u)
+
+/** \brief 14C, Message Pending Register */
+#define CAN_MSPND3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF001814Cu)
+
+/** \brief 150, Message Pending Register */
+#define CAN_MSPND4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF0018150u)
+
+/** \brief 154, Message Pending Register */
+#define CAN_MSPND5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF0018154u)
+
+/** \brief 158, Message Pending Register */
+#define CAN_MSPND6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF0018158u)
+
+/** \brief 15C, Message Pending Register */
+#define CAN_MSPND7 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF001815Cu)
+
+/** \brief 210, Node Bit Timing Register */
+#define CAN_N0_BTEVR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTEVR*)0xF0018210u)
+
+/** Alias (User Manual Name) for CAN_N0_BTEVR.
+* To use register names with standard convension, please use CAN_N0_BTEVR.
+*/
+#define CAN_NBTEVR0 (CAN_N0_BTEVR)
+
+/** \brief 210, Node Bit Timing Register */
+#define CAN_N0_BTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTR*)0xF0018210u)
+
+/** Alias (User Manual Name) for CAN_N0_BTR.
+* To use register names with standard convension, please use CAN_N0_BTR.
+*/
+#define CAN_NBTR0 (CAN_N0_BTR)
+
+/** \brief 200, Node Control Register */
+#define CAN_N0_CR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_CR*)0xF0018200u)
+
+/** Alias (User Manual Name) for CAN_N0_CR.
+* To use register names with standard convension, please use CAN_N0_CR.
+*/
+#define CAN_NCR0 (CAN_N0_CR)
+
+/** \brief 214, Node Error Counter Register */
+#define CAN_N0_ECNT /*lint --e(923)*/ (*(volatile Ifx_CAN_N_ECNT*)0xF0018214u)
+
+/** Alias (User Manual Name) for CAN_N0_ECNT.
+* To use register names with standard convension, please use CAN_N0_ECNT.
+*/
+#define CAN_NECNT0 (CAN_N0_ECNT)
+
+/** \brief 238, Fast Node Bit Timing Register */
+#define CAN_N0_FBTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FBTR*)0xF0018238u)
+
+/** Alias (User Manual Name) for CAN_N0_FBTR.
+* To use register names with standard convension, please use CAN_N0_FBTR.
+*/
+#define CAN_FNBTR0 (CAN_N0_FBTR)
+
+/** \brief 218, Node Frame Counter Register */
+#define CAN_N0_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FCR*)0xF0018218u)
+
+/** Alias (User Manual Name) for CAN_N0_FCR.
+* To use register names with standard convension, please use CAN_N0_FCR.
+*/
+#define CAN_NFCR0 (CAN_N0_FCR)
+
+/** \brief 208, Node Interrupt Pointer Register */
+#define CAN_N0_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_IPR*)0xF0018208u)
+
+/** Alias (User Manual Name) for CAN_N0_IPR.
+* To use register names with standard convension, please use CAN_N0_IPR.
+*/
+#define CAN_NIPR0 (CAN_N0_IPR)
+
+/** \brief 20C, Node Port Control Register */
+#define CAN_N0_PCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_PCR*)0xF001820Cu)
+
+/** Alias (User Manual Name) for CAN_N0_PCR.
+* To use register names with standard convension, please use CAN_N0_PCR.
+*/
+#define CAN_NPCR0 (CAN_N0_PCR)
+
+/** \brief 204, Node Status Register */
+#define CAN_N0_SR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_SR*)0xF0018204u)
+
+/** Alias (User Manual Name) for CAN_N0_SR.
+* To use register names with standard convension, please use CAN_N0_SR.
+*/
+#define CAN_NSR0 (CAN_N0_SR)
+
+/** \brief 224, Node Timer A Transmit Trigger Register */
+#define CAN_N0_TATTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0018224u)
+
+/** Alias (User Manual Name) for CAN_N0_TATTR.
+* To use register names with standard convension, please use CAN_N0_TATTR.
+*/
+#define CAN_NTATTR0 (CAN_N0_TATTR)
+
+/** \brief 228, Node Timer B Transmit Trigger Register */
+#define CAN_N0_TBTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0018228u)
+
+/** Alias (User Manual Name) for CAN_N0_TBTTR.
+* To use register names with standard convension, please use CAN_N0_TBTTR.
+*/
+#define CAN_NTBTTR0 (CAN_N0_TBTTR)
+
+/** \brief 21C, Node Timer Clock Control Register */
+#define CAN_N0_TCCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TCCR*)0xF001821Cu)
+
+/** Alias (User Manual Name) for CAN_N0_TCCR.
+* To use register names with standard convension, please use CAN_N0_TCCR.
+*/
+#define CAN_NTCCR0 (CAN_N0_TCCR)
+
+/** \brief 22C, Node Timer C Transmit Trigger Register */
+#define CAN_N0_TCTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF001822Cu)
+
+/** Alias (User Manual Name) for CAN_N0_TCTTR.
+* To use register names with standard convension, please use CAN_N0_TCTTR.
+*/
+#define CAN_NTCTTR0 (CAN_N0_TCTTR)
+
+/** \brief 23C, Node Transmitter Delay Compensation Register */
+#define CAN_N0_TDCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TDCR*)0xF001823Cu)
+
+/** Alias (User Manual Name) for CAN_N0_TDCR.
+* To use register names with standard convension, please use CAN_N0_TDCR.
+*/
+#define CAN_NTDCR0 (CAN_N0_TDCR)
+
+/** \brief 220, Node Timer Receive Timeout Register */
+#define CAN_N0_TRTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TRTR*)0xF0018220u)
+
+/** Alias (User Manual Name) for CAN_N0_TRTR.
+* To use register names with standard convension, please use CAN_N0_TRTR.
+*/
+#define CAN_NTRTR0 (CAN_N0_TRTR)
+
+/** \brief 310, Node Bit Timing Register */
+#define CAN_N1_BTEVR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTEVR*)0xF0018310u)
+
+/** Alias (User Manual Name) for CAN_N1_BTEVR.
+* To use register names with standard convension, please use CAN_N1_BTEVR.
+*/
+#define CAN_NBTEVR1 (CAN_N1_BTEVR)
+
+/** \brief 310, Node Bit Timing Register */
+#define CAN_N1_BTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTR*)0xF0018310u)
+
+/** Alias (User Manual Name) for CAN_N1_BTR.
+* To use register names with standard convension, please use CAN_N1_BTR.
+*/
+#define CAN_NBTR1 (CAN_N1_BTR)
+
+/** \brief 300, Node Control Register */
+#define CAN_N1_CR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_CR*)0xF0018300u)
+
+/** Alias (User Manual Name) for CAN_N1_CR.
+* To use register names with standard convension, please use CAN_N1_CR.
+*/
+#define CAN_NCR1 (CAN_N1_CR)
+
+/** \brief 314, Node Error Counter Register */
+#define CAN_N1_ECNT /*lint --e(923)*/ (*(volatile Ifx_CAN_N_ECNT*)0xF0018314u)
+
+/** Alias (User Manual Name) for CAN_N1_ECNT.
+* To use register names with standard convension, please use CAN_N1_ECNT.
+*/
+#define CAN_NECNT1 (CAN_N1_ECNT)
+
+/** \brief 338, Fast Node Bit Timing Register */
+#define CAN_N1_FBTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FBTR*)0xF0018338u)
+
+/** Alias (User Manual Name) for CAN_N1_FBTR.
+* To use register names with standard convension, please use CAN_N1_FBTR.
+*/
+#define CAN_FNBTR1 (CAN_N1_FBTR)
+
+/** \brief 318, Node Frame Counter Register */
+#define CAN_N1_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FCR*)0xF0018318u)
+
+/** Alias (User Manual Name) for CAN_N1_FCR.
+* To use register names with standard convension, please use CAN_N1_FCR.
+*/
+#define CAN_NFCR1 (CAN_N1_FCR)
+
+/** \brief 308, Node Interrupt Pointer Register */
+#define CAN_N1_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_IPR*)0xF0018308u)
+
+/** Alias (User Manual Name) for CAN_N1_IPR.
+* To use register names with standard convension, please use CAN_N1_IPR.
+*/
+#define CAN_NIPR1 (CAN_N1_IPR)
+
+/** \brief 30C, Node Port Control Register */
+#define CAN_N1_PCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_PCR*)0xF001830Cu)
+
+/** Alias (User Manual Name) for CAN_N1_PCR.
+* To use register names with standard convension, please use CAN_N1_PCR.
+*/
+#define CAN_NPCR1 (CAN_N1_PCR)
+
+/** \brief 304, Node Status Register */
+#define CAN_N1_SR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_SR*)0xF0018304u)
+
+/** Alias (User Manual Name) for CAN_N1_SR.
+* To use register names with standard convension, please use CAN_N1_SR.
+*/
+#define CAN_NSR1 (CAN_N1_SR)
+
+/** \brief 324, Node Timer A Transmit Trigger Register */
+#define CAN_N1_TATTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0018324u)
+
+/** Alias (User Manual Name) for CAN_N1_TATTR.
+* To use register names with standard convension, please use CAN_N1_TATTR.
+*/
+#define CAN_NTATTR1 (CAN_N1_TATTR)
+
+/** \brief 328, Node Timer B Transmit Trigger Register */
+#define CAN_N1_TBTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0018328u)
+
+/** Alias (User Manual Name) for CAN_N1_TBTTR.
+* To use register names with standard convension, please use CAN_N1_TBTTR.
+*/
+#define CAN_NTBTTR1 (CAN_N1_TBTTR)
+
+/** \brief 31C, Node Timer Clock Control Register */
+#define CAN_N1_TCCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TCCR*)0xF001831Cu)
+
+/** Alias (User Manual Name) for CAN_N1_TCCR.
+* To use register names with standard convension, please use CAN_N1_TCCR.
+*/
+#define CAN_NTCCR1 (CAN_N1_TCCR)
+
+/** \brief 32C, Node Timer C Transmit Trigger Register */
+#define CAN_N1_TCTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF001832Cu)
+
+/** Alias (User Manual Name) for CAN_N1_TCTTR.
+* To use register names with standard convension, please use CAN_N1_TCTTR.
+*/
+#define CAN_NTCTTR1 (CAN_N1_TCTTR)
+
+/** \brief 33C, Node Transmitter Delay Compensation Register */
+#define CAN_N1_TDCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TDCR*)0xF001833Cu)
+
+/** Alias (User Manual Name) for CAN_N1_TDCR.
+* To use register names with standard convension, please use CAN_N1_TDCR.
+*/
+#define CAN_NTDCR1 (CAN_N1_TDCR)
+
+/** \brief 320, Node Timer Receive Timeout Register */
+#define CAN_N1_TRTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TRTR*)0xF0018320u)
+
+/** Alias (User Manual Name) for CAN_N1_TRTR.
+* To use register names with standard convension, please use CAN_N1_TRTR.
+*/
+#define CAN_NTRTR1 (CAN_N1_TRTR)
+
+/** \brief 410, Node Bit Timing Register */
+#define CAN_N2_BTEVR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTEVR*)0xF0018410u)
+
+/** Alias (User Manual Name) for CAN_N2_BTEVR.
+* To use register names with standard convension, please use CAN_N2_BTEVR.
+*/
+#define CAN_NBTEVR2 (CAN_N2_BTEVR)
+
+/** \brief 410, Node Bit Timing Register */
+#define CAN_N2_BTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTR*)0xF0018410u)
+
+/** Alias (User Manual Name) for CAN_N2_BTR.
+* To use register names with standard convension, please use CAN_N2_BTR.
+*/
+#define CAN_NBTR2 (CAN_N2_BTR)
+
+/** \brief 400, Node Control Register */
+#define CAN_N2_CR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_CR*)0xF0018400u)
+
+/** Alias (User Manual Name) for CAN_N2_CR.
+* To use register names with standard convension, please use CAN_N2_CR.
+*/
+#define CAN_NCR2 (CAN_N2_CR)
+
+/** \brief 414, Node Error Counter Register */
+#define CAN_N2_ECNT /*lint --e(923)*/ (*(volatile Ifx_CAN_N_ECNT*)0xF0018414u)
+
+/** Alias (User Manual Name) for CAN_N2_ECNT.
+* To use register names with standard convension, please use CAN_N2_ECNT.
+*/
+#define CAN_NECNT2 (CAN_N2_ECNT)
+
+/** \brief 438, Fast Node Bit Timing Register */
+#define CAN_N2_FBTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FBTR*)0xF0018438u)
+
+/** Alias (User Manual Name) for CAN_N2_FBTR.
+* To use register names with standard convension, please use CAN_N2_FBTR.
+*/
+#define CAN_FNBTR2 (CAN_N2_FBTR)
+
+/** \brief 418, Node Frame Counter Register */
+#define CAN_N2_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FCR*)0xF0018418u)
+
+/** Alias (User Manual Name) for CAN_N2_FCR.
+* To use register names with standard convension, please use CAN_N2_FCR.
+*/
+#define CAN_NFCR2 (CAN_N2_FCR)
+
+/** \brief 408, Node Interrupt Pointer Register */
+#define CAN_N2_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_IPR*)0xF0018408u)
+
+/** Alias (User Manual Name) for CAN_N2_IPR.
+* To use register names with standard convension, please use CAN_N2_IPR.
+*/
+#define CAN_NIPR2 (CAN_N2_IPR)
+
+/** \brief 40C, Node Port Control Register */
+#define CAN_N2_PCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_PCR*)0xF001840Cu)
+
+/** Alias (User Manual Name) for CAN_N2_PCR.
+* To use register names with standard convension, please use CAN_N2_PCR.
+*/
+#define CAN_NPCR2 (CAN_N2_PCR)
+
+/** \brief 404, Node Status Register */
+#define CAN_N2_SR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_SR*)0xF0018404u)
+
+/** Alias (User Manual Name) for CAN_N2_SR.
+* To use register names with standard convension, please use CAN_N2_SR.
+*/
+#define CAN_NSR2 (CAN_N2_SR)
+
+/** \brief 424, Node Timer A Transmit Trigger Register */
+#define CAN_N2_TATTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0018424u)
+
+/** Alias (User Manual Name) for CAN_N2_TATTR.
+* To use register names with standard convension, please use CAN_N2_TATTR.
+*/
+#define CAN_NTATTR2 (CAN_N2_TATTR)
+
+/** \brief 428, Node Timer B Transmit Trigger Register */
+#define CAN_N2_TBTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0018428u)
+
+/** Alias (User Manual Name) for CAN_N2_TBTTR.
+* To use register names with standard convension, please use CAN_N2_TBTTR.
+*/
+#define CAN_NTBTTR2 (CAN_N2_TBTTR)
+
+/** \brief 41C, Node Timer Clock Control Register */
+#define CAN_N2_TCCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TCCR*)0xF001841Cu)
+
+/** Alias (User Manual Name) for CAN_N2_TCCR.
+* To use register names with standard convension, please use CAN_N2_TCCR.
+*/
+#define CAN_NTCCR2 (CAN_N2_TCCR)
+
+/** \brief 42C, Node Timer C Transmit Trigger Register */
+#define CAN_N2_TCTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF001842Cu)
+
+/** Alias (User Manual Name) for CAN_N2_TCTTR.
+* To use register names with standard convension, please use CAN_N2_TCTTR.
+*/
+#define CAN_NTCTTR2 (CAN_N2_TCTTR)
+
+/** \brief 43C, Node Transmitter Delay Compensation Register */
+#define CAN_N2_TDCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TDCR*)0xF001843Cu)
+
+/** Alias (User Manual Name) for CAN_N2_TDCR.
+* To use register names with standard convension, please use CAN_N2_TDCR.
+*/
+#define CAN_NTDCR2 (CAN_N2_TDCR)
+
+/** \brief 420, Node Timer Receive Timeout Register */
+#define CAN_N2_TRTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TRTR*)0xF0018420u)
+
+/** Alias (User Manual Name) for CAN_N2_TRTR.
+* To use register names with standard convension, please use CAN_N2_TRTR.
+*/
+#define CAN_NTRTR2 (CAN_N2_TRTR)
+
+/** \brief 510, Node Bit Timing Register */
+#define CAN_N3_BTEVR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTEVR*)0xF0018510u)
+
+/** Alias (User Manual Name) for CAN_N3_BTEVR.
+* To use register names with standard convension, please use CAN_N3_BTEVR.
+*/
+#define CAN_NBTEVR3 (CAN_N3_BTEVR)
+
+/** \brief 510, Node Bit Timing Register */
+#define CAN_N3_BTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTR*)0xF0018510u)
+
+/** Alias (User Manual Name) for CAN_N3_BTR.
+* To use register names with standard convension, please use CAN_N3_BTR.
+*/
+#define CAN_NBTR3 (CAN_N3_BTR)
+
+/** \brief 500, Node Control Register */
+#define CAN_N3_CR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_CR*)0xF0018500u)
+
+/** Alias (User Manual Name) for CAN_N3_CR.
+* To use register names with standard convension, please use CAN_N3_CR.
+*/
+#define CAN_NCR3 (CAN_N3_CR)
+
+/** \brief 514, Node Error Counter Register */
+#define CAN_N3_ECNT /*lint --e(923)*/ (*(volatile Ifx_CAN_N_ECNT*)0xF0018514u)
+
+/** Alias (User Manual Name) for CAN_N3_ECNT.
+* To use register names with standard convension, please use CAN_N3_ECNT.
+*/
+#define CAN_NECNT3 (CAN_N3_ECNT)
+
+/** \brief 538, Fast Node Bit Timing Register */
+#define CAN_N3_FBTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FBTR*)0xF0018538u)
+
+/** Alias (User Manual Name) for CAN_N3_FBTR.
+* To use register names with standard convension, please use CAN_N3_FBTR.
+*/
+#define CAN_FNBTR3 (CAN_N3_FBTR)
+
+/** \brief 518, Node Frame Counter Register */
+#define CAN_N3_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FCR*)0xF0018518u)
+
+/** Alias (User Manual Name) for CAN_N3_FCR.
+* To use register names with standard convension, please use CAN_N3_FCR.
+*/
+#define CAN_NFCR3 (CAN_N3_FCR)
+
+/** \brief 508, Node Interrupt Pointer Register */
+#define CAN_N3_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_IPR*)0xF0018508u)
+
+/** Alias (User Manual Name) for CAN_N3_IPR.
+* To use register names with standard convension, please use CAN_N3_IPR.
+*/
+#define CAN_NIPR3 (CAN_N3_IPR)
+
+/** \brief 50C, Node Port Control Register */
+#define CAN_N3_PCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_PCR*)0xF001850Cu)
+
+/** Alias (User Manual Name) for CAN_N3_PCR.
+* To use register names with standard convension, please use CAN_N3_PCR.
+*/
+#define CAN_NPCR3 (CAN_N3_PCR)
+
+/** \brief 504, Node Status Register */
+#define CAN_N3_SR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_SR*)0xF0018504u)
+
+/** Alias (User Manual Name) for CAN_N3_SR.
+* To use register names with standard convension, please use CAN_N3_SR.
+*/
+#define CAN_NSR3 (CAN_N3_SR)
+
+/** \brief 524, Node Timer A Transmit Trigger Register */
+#define CAN_N3_TATTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0018524u)
+
+/** Alias (User Manual Name) for CAN_N3_TATTR.
+* To use register names with standard convension, please use CAN_N3_TATTR.
+*/
+#define CAN_NTATTR3 (CAN_N3_TATTR)
+
+/** \brief 528, Node Timer B Transmit Trigger Register */
+#define CAN_N3_TBTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0018528u)
+
+/** Alias (User Manual Name) for CAN_N3_TBTTR.
+* To use register names with standard convension, please use CAN_N3_TBTTR.
+*/
+#define CAN_NTBTTR3 (CAN_N3_TBTTR)
+
+/** \brief 51C, Node Timer Clock Control Register */
+#define CAN_N3_TCCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TCCR*)0xF001851Cu)
+
+/** Alias (User Manual Name) for CAN_N3_TCCR.
+* To use register names with standard convension, please use CAN_N3_TCCR.
+*/
+#define CAN_NTCCR3 (CAN_N3_TCCR)
+
+/** \brief 52C, Node Timer C Transmit Trigger Register */
+#define CAN_N3_TCTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF001852Cu)
+
+/** Alias (User Manual Name) for CAN_N3_TCTTR.
+* To use register names with standard convension, please use CAN_N3_TCTTR.
+*/
+#define CAN_NTCTTR3 (CAN_N3_TCTTR)
+
+/** \brief 53C, Node Transmitter Delay Compensation Register */
+#define CAN_N3_TDCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TDCR*)0xF001853Cu)
+
+/** Alias (User Manual Name) for CAN_N3_TDCR.
+* To use register names with standard convension, please use CAN_N3_TDCR.
+*/
+#define CAN_NTDCR3 (CAN_N3_TDCR)
+
+/** \brief 520, Node Timer Receive Timeout Register */
+#define CAN_N3_TRTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TRTR*)0xF0018520u)
+
+/** Alias (User Manual Name) for CAN_N3_TRTR.
+* To use register names with standard convension, please use CAN_N3_TRTR.
+*/
+#define CAN_NTRTR3 (CAN_N3_TRTR)
+
+/** \brief 610, Node Bit Timing Register */
+#define CAN_N4_BTEVR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTEVR*)0xF0018610u)
+
+/** Alias (User Manual Name) for CAN_N4_BTEVR.
+* To use register names with standard convension, please use CAN_N4_BTEVR.
+*/
+#define CAN_NBTEVR4 (CAN_N4_BTEVR)
+
+/** \brief 610, Node Bit Timing Register */
+#define CAN_N4_BTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTR*)0xF0018610u)
+
+/** Alias (User Manual Name) for CAN_N4_BTR.
+* To use register names with standard convension, please use CAN_N4_BTR.
+*/
+#define CAN_NBTR4 (CAN_N4_BTR)
+
+/** \brief 600, Node Control Register */
+#define CAN_N4_CR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_CR*)0xF0018600u)
+
+/** Alias (User Manual Name) for CAN_N4_CR.
+* To use register names with standard convension, please use CAN_N4_CR.
+*/
+#define CAN_NCR4 (CAN_N4_CR)
+
+/** \brief 614, Node Error Counter Register */
+#define CAN_N4_ECNT /*lint --e(923)*/ (*(volatile Ifx_CAN_N_ECNT*)0xF0018614u)
+
+/** Alias (User Manual Name) for CAN_N4_ECNT.
+* To use register names with standard convension, please use CAN_N4_ECNT.
+*/
+#define CAN_NECNT4 (CAN_N4_ECNT)
+
+/** \brief 638, Fast Node Bit Timing Register */
+#define CAN_N4_FBTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FBTR*)0xF0018638u)
+
+/** Alias (User Manual Name) for CAN_N4_FBTR.
+* To use register names with standard convension, please use CAN_N4_FBTR.
+*/
+#define CAN_FNBTR4 (CAN_N4_FBTR)
+
+/** \brief 618, Node Frame Counter Register */
+#define CAN_N4_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FCR*)0xF0018618u)
+
+/** Alias (User Manual Name) for CAN_N4_FCR.
+* To use register names with standard convension, please use CAN_N4_FCR.
+*/
+#define CAN_NFCR4 (CAN_N4_FCR)
+
+/** \brief 608, Node Interrupt Pointer Register */
+#define CAN_N4_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_IPR*)0xF0018608u)
+
+/** Alias (User Manual Name) for CAN_N4_IPR.
+* To use register names with standard convension, please use CAN_N4_IPR.
+*/
+#define CAN_NIPR4 (CAN_N4_IPR)
+
+/** \brief 60C, Node Port Control Register */
+#define CAN_N4_PCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_PCR*)0xF001860Cu)
+
+/** Alias (User Manual Name) for CAN_N4_PCR.
+* To use register names with standard convension, please use CAN_N4_PCR.
+*/
+#define CAN_NPCR4 (CAN_N4_PCR)
+
+/** \brief 604, Node Status Register */
+#define CAN_N4_SR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_SR*)0xF0018604u)
+
+/** Alias (User Manual Name) for CAN_N4_SR.
+* To use register names with standard convension, please use CAN_N4_SR.
+*/
+#define CAN_NSR4 (CAN_N4_SR)
+
+/** \brief 624, Node Timer A Transmit Trigger Register */
+#define CAN_N4_TATTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0018624u)
+
+/** Alias (User Manual Name) for CAN_N4_TATTR.
+* To use register names with standard convension, please use CAN_N4_TATTR.
+*/
+#define CAN_NTATTR4 (CAN_N4_TATTR)
+
+/** \brief 628, Node Timer B Transmit Trigger Register */
+#define CAN_N4_TBTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0018628u)
+
+/** Alias (User Manual Name) for CAN_N4_TBTTR.
+* To use register names with standard convension, please use CAN_N4_TBTTR.
+*/
+#define CAN_NTBTTR4 (CAN_N4_TBTTR)
+
+/** \brief 61C, Node Timer Clock Control Register */
+#define CAN_N4_TCCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TCCR*)0xF001861Cu)
+
+/** Alias (User Manual Name) for CAN_N4_TCCR.
+* To use register names with standard convension, please use CAN_N4_TCCR.
+*/
+#define CAN_NTCCR4 (CAN_N4_TCCR)
+
+/** \brief 62C, Node Timer C Transmit Trigger Register */
+#define CAN_N4_TCTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF001862Cu)
+
+/** Alias (User Manual Name) for CAN_N4_TCTTR.
+* To use register names with standard convension, please use CAN_N4_TCTTR.
+*/
+#define CAN_NTCTTR4 (CAN_N4_TCTTR)
+
+/** \brief 63C, Node Transmitter Delay Compensation Register */
+#define CAN_N4_TDCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TDCR*)0xF001863Cu)
+
+/** Alias (User Manual Name) for CAN_N4_TDCR.
+* To use register names with standard convension, please use CAN_N4_TDCR.
+*/
+#define CAN_NTDCR4 (CAN_N4_TDCR)
+
+/** \brief 620, Node Timer Receive Timeout Register */
+#define CAN_N4_TRTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TRTR*)0xF0018620u)
+
+/** Alias (User Manual Name) for CAN_N4_TRTR.
+* To use register names with standard convension, please use CAN_N4_TRTR.
+*/
+#define CAN_NTRTR4 (CAN_N4_TRTR)
+
+/** \brief E8, OCDS Control and Status */
+#define CAN_OCS /*lint --e(923)*/ (*(volatile Ifx_CAN_OCS*)0xF00180E8u)
+
+/** \brief 1C4, Panel Control Register */
+#define CAN_PANCTR /*lint --e(923)*/ (*(volatile Ifx_CAN_PANCTR*)0xF00181C4u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXCAN_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCan_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCan_regdef.h
new file mode 100644
index 0000000..e60193a
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCan_regdef.h
@@ -0,0 +1,1093 @@
+/**
+ * \file IfxCan_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Can Can
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Can_Bitfields Bitfields
+ * \ingroup IfxLld_Can
+ *
+ * \defgroup IfxLld_Can_union Union
+ * \ingroup IfxLld_Can
+ *
+ * \defgroup IfxLld_Can_struct Struct
+ * \ingroup IfxLld_Can
+ *
+ */
+#ifndef IFXCAN_REGDEF_H
+#define IFXCAN_REGDEF_H 1
+/******************************************************************************/
+#if defined (__TASKING__)
+#pragma warning 586
+#endif
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Can_Bitfields
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef struct _Ifx_CAN_ACCEN0_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_CAN_ACCEN0_Bits;
+
+/** \brief Access Enable Register 1 */
+typedef struct _Ifx_CAN_ACCEN1_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_CAN_ACCEN1_Bits;
+
+/** \brief CAN Clock Control Register */
+typedef struct _Ifx_CAN_CLC_Bits
+{
+ unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
+ unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
+ unsigned int reserved_2:1; /**< \brief \internal Reserved */
+ unsigned int EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control (rw) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_CAN_CLC_Bits;
+
+/** \brief CAN Fractional Divider Register */
+typedef struct _Ifx_CAN_FDR_Bits
+{
+ unsigned int STEP:10; /**< \brief [9:0] Step Value (rw) */
+ unsigned int reserved_10:4; /**< \brief \internal Reserved */
+ unsigned int DM:2; /**< \brief [15:14] Divider Mode (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CAN_FDR_Bits;
+
+/** \brief Module Identification Register */
+typedef struct _Ifx_CAN_ID_Bits
+{
+ unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
+ unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_CAN_ID_Bits;
+
+/** \brief Kernel Reset Register 0 */
+typedef struct _Ifx_CAN_KRST0_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rw) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_CAN_KRST0_Bits;
+
+/** \brief Kernel Reset Register 1 */
+typedef struct _Ifx_CAN_KRST1_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_CAN_KRST1_Bits;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef struct _Ifx_CAN_KRSTCLR_Bits
+{
+ unsigned int CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_CAN_KRSTCLR_Bits;
+
+/** \brief List Register */
+typedef struct _Ifx_CAN_LIST_Bits
+{
+ unsigned int BEGIN:8; /**< \brief [7:0] List Begin (rh) */
+ unsigned int END:8; /**< \brief [15:8] List End (rh) */
+ unsigned int SIZE:8; /**< \brief [23:16] List Size (rh) */
+ unsigned int EMPTY:1; /**< \brief [24:24] List Empty Indication (rh) */
+ unsigned int reserved_25:7; /**< \brief \internal Reserved */
+} Ifx_CAN_LIST_Bits;
+
+/** \brief Module Control Register */
+typedef struct _Ifx_CAN_MCR_Bits
+{
+ unsigned int CLKSEL:4; /**< \brief [3:0] Baud Rate Logic Clock Select (rw) */
+ unsigned int reserved_4:8; /**< \brief \internal Reserved */
+ unsigned int MPSEL:4; /**< \brief [15:12] Message Pending Selector (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CAN_MCR_Bits;
+
+/** \brief Measure Control Register */
+typedef struct _Ifx_CAN_MECR_Bits
+{
+ unsigned int TH:16; /**< \brief [15:0] Threshold (rw) */
+ unsigned int INP:4; /**< \brief [19:16] Interrupt Node Pointer (rw) */
+ unsigned int NODE:3; /**< \brief [22:20] Node (rw) */
+ unsigned int reserved_23:1; /**< \brief \internal Reserved */
+ unsigned int ANYED:1; /**< \brief [24:24] Any Edge (rw) */
+ unsigned int CAPEIE:1; /**< \brief [25:25] Capture Event Interrupt Enable (rw) */
+ unsigned int reserved_26:1; /**< \brief \internal Reserved */
+ unsigned int DEPTH:3; /**< \brief [29:27] Digital Glitch Filter Depth (rw) */
+ unsigned int SOF:1; /**< \brief [30:30] Start Of Frame (rw) */
+ unsigned int reserved_31:1; /**< \brief \internal Reserved */
+} Ifx_CAN_MECR_Bits;
+
+/** \brief Measure Status Register */
+typedef struct _Ifx_CAN_MESTAT_Bits
+{
+ unsigned int CAPT:16; /**< \brief [15:0] Captured Timer (rh) */
+ unsigned int CAPRED:1; /**< \brief [16:16] Captured Rising Edge (rh) */
+ unsigned int CAPE:1; /**< \brief [17:17] Capture Event (rwh) */
+ unsigned int reserved_18:14; /**< \brief \internal Reserved */
+} Ifx_CAN_MESTAT_Bits;
+
+/** \brief Module Interrupt Trigger Register */
+typedef struct _Ifx_CAN_MITR_Bits
+{
+ unsigned int IT:16; /**< \brief [15:0] Interrupt Trigger (w) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CAN_MITR_Bits;
+
+/** \brief Message Object Acceptance Mask Register */
+typedef struct _Ifx_CAN_MO_AMR_Bits
+{
+ unsigned int AM:29; /**< \brief [28:0] Acceptance Mask for Message Identifier (rw) */
+ unsigned int MIDE:1; /**< \brief [29:29] Acceptance Mask Bit for Message IDE Bit (rw) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_CAN_MO_AMR_Bits;
+
+/** \brief Message Object Arbitration Register */
+typedef struct _Ifx_CAN_MO_AR_Bits
+{
+ unsigned int ID:29; /**< \brief [28:0] CAN Identifier of Message Object n (rwh) */
+ unsigned int IDE:1; /**< \brief [29:29] Identifier Extension Bit of Message Object n (rwh) */
+ unsigned int PRI:2; /**< \brief [31:30] Priority Class (rw) */
+} Ifx_CAN_MO_AR_Bits;
+
+/** \brief Message Object Control Register */
+typedef struct _Ifx_CAN_MO_CTR_Bits
+{
+ unsigned int RESRXPND:1; /**< \brief [0:0] Reset/Set Receive Pending (w) */
+ unsigned int RESTXPND:1; /**< \brief [1:1] Reset/Set Transmit Pending (w) */
+ unsigned int RESRXUPD:1; /**< \brief [2:2] Reset/Set Receive Updating (w) */
+ unsigned int RESNEWDAT:1; /**< \brief [3:3] Reset/Set New Data (w) */
+ unsigned int RESMSGLST:1; /**< \brief [4:4] Reset/Set Message Lost (w) */
+ unsigned int RESMSGVAL:1; /**< \brief [5:5] Reset/Set Message Valid (w) */
+ unsigned int RESRTSEL:1; /**< \brief [6:6] Reset/Set Receive/Transmit Selected (w) */
+ unsigned int RESRXEN:1; /**< \brief [7:7] Reset/Set Receive Enable (w) */
+ unsigned int RESTXRQ:1; /**< \brief [8:8] Reset/Set Transmit Request (w) */
+ unsigned int RESTXEN0:1; /**< \brief [9:9] Reset/Set Transmit Enable 0 (w) */
+ unsigned int RESTXEN1:1; /**< \brief [10:10] Reset/Set Transmit Enable 1 (w) */
+ unsigned int RESDIR:1; /**< \brief [11:11] Reset/Set Message Direction (w) */
+ unsigned int reserved_12:4; /**< \brief \internal Reserved */
+ unsigned int SETRXPND:1; /**< \brief [16:16] Reset/Set Receive Pending (w) */
+ unsigned int SETTXPND:1; /**< \brief [17:17] Reset/Set Transmit Pending (w) */
+ unsigned int SETRXUPD:1; /**< \brief [18:18] Reset/Set Receive Updating (w) */
+ unsigned int SETNEWDAT:1; /**< \brief [19:19] Reset/Set New Data (w) */
+ unsigned int SETMSGLST:1; /**< \brief [20:20] Reset/Set Message Lost (w) */
+ unsigned int SETMSGVAL:1; /**< \brief [21:21] Reset/Set Message Valid (w) */
+ unsigned int SETRTSEL:1; /**< \brief [22:22] Reset/Set Receive/Transmit Selected (w) */
+ unsigned int SETRXEN:1; /**< \brief [23:23] Reset/Set Receive Enable (w) */
+ unsigned int SETTXRQ:1; /**< \brief [24:24] Reset/Set Transmit Request (w) */
+ unsigned int SETTXEN0:1; /**< \brief [25:25] Reset/Set Transmit Enable 0 (w) */
+ unsigned int SETTXEN1:1; /**< \brief [26:26] Reset/Set Transmit Enable 1 (w) */
+ unsigned int SETDIR:1; /**< \brief [27:27] Reset/Set Message Direction (w) */
+ unsigned int reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_CAN_MO_CTR_Bits;
+
+/** \brief Message Object Data Register High */
+typedef struct _Ifx_CAN_MO_DATAH_Bits
+{
+ unsigned int DB4:8; /**< \brief [7:0] Data Byte 4 of Message Object n (rwh) */
+ unsigned int DB5:8; /**< \brief [15:8] Data Byte 5 of Message Object n (rwh) */
+ unsigned int DB6:8; /**< \brief [23:16] Data Byte 6 of Message Object n (rwh) */
+ unsigned int DB7:8; /**< \brief [31:24] Data Byte 7 of Message Object n (rwh) */
+} Ifx_CAN_MO_DATAH_Bits;
+
+/** \brief Message Object Data Register Low */
+typedef struct _Ifx_CAN_MO_DATAL_Bits
+{
+ unsigned int DB0:8; /**< \brief [7:0] Data Byte 0 of Message Object n (rwh) */
+ unsigned int DB1:8; /**< \brief [15:8] Data Byte 1 of Message Object n (rwh) */
+ unsigned int DB2:8; /**< \brief [23:16] Data Byte 2 of Message Object n (rwh) */
+ unsigned int DB3:8; /**< \brief [31:24] Data Byte 3 of Message Object n (rwh) */
+} Ifx_CAN_MO_DATAL_Bits;
+
+/** \brief Extended Message Object Data 0 Register */
+typedef struct _Ifx_CAN_MO_EDATA0_Bits
+{
+ unsigned int DB0:8; /**< \brief [7:0] Data Byte 0 of Message Object n (rwh) */
+ unsigned int DB1:8; /**< \brief [15:8] Data Byte 1 of Message Object n (rwh) */
+ unsigned int DB2:8; /**< \brief [23:16] Data Byte 2 of Message Object n (rwh) */
+ unsigned int DB3:8; /**< \brief [31:24] Data Byte 3 of Message Object n (rwh) */
+} Ifx_CAN_MO_EDATA0_Bits;
+
+/** \brief Extended Message Object Data 1 Register */
+typedef struct _Ifx_CAN_MO_EDATA1_Bits
+{
+ unsigned int DB0:8; /**< \brief [7:0] Data Byte 0 of Message Object n (rwh) */
+ unsigned int DB1:8; /**< \brief [15:8] Data Byte 1 of Message Object n (rwh) */
+ unsigned int DB2:8; /**< \brief [23:16] Data Byte 2 of Message Object n (rwh) */
+ unsigned int DB3:8; /**< \brief [31:24] Data Byte 3 of Message Object n (rwh) */
+} Ifx_CAN_MO_EDATA1_Bits;
+
+/** \brief Extended Message Object Data 2 Register */
+typedef struct _Ifx_CAN_MO_EDATA2_Bits
+{
+ unsigned int DB0:8; /**< \brief [7:0] Data Byte 0 of Message Object n (rwh) */
+ unsigned int DB1:8; /**< \brief [15:8] Data Byte 1 of Message Object n (rwh) */
+ unsigned int DB2:8; /**< \brief [23:16] Data Byte 2 of Message Object n (rwh) */
+ unsigned int DB3:8; /**< \brief [31:24] Data Byte 3 of Message Object n (rwh) */
+} Ifx_CAN_MO_EDATA2_Bits;
+
+/** \brief Extended Message Object Data 3 Register */
+typedef struct _Ifx_CAN_MO_EDATA3_Bits
+{
+ unsigned int DB0:8; /**< \brief [7:0] Data Byte 0 of Message Object n (rwh) */
+ unsigned int DB1:8; /**< \brief [15:8] Data Byte 1 of Message Object n (rwh) */
+ unsigned int DB2:8; /**< \brief [23:16] Data Byte 2 of Message Object n (rwh) */
+ unsigned int DB3:8; /**< \brief [31:24] Data Byte 3 of Message Object n (rwh) */
+} Ifx_CAN_MO_EDATA3_Bits;
+
+/** \brief Extended Message Object Data 4 Register */
+typedef struct _Ifx_CAN_MO_EDATA4_Bits
+{
+ unsigned int DB0:8; /**< \brief [7:0] Data Byte 0 of Message Object n (rwh) */
+ unsigned int DB1:8; /**< \brief [15:8] Data Byte 1 of Message Object n (rwh) */
+ unsigned int DB2:8; /**< \brief [23:16] Data Byte 2 of Message Object n (rwh) */
+ unsigned int DB3:8; /**< \brief [31:24] Data Byte 3 of Message Object n (rwh) */
+} Ifx_CAN_MO_EDATA4_Bits;
+
+/** \brief Extended Message Object Data 5 Register */
+typedef struct _Ifx_CAN_MO_EDATA5_Bits
+{
+ unsigned int DB0:8; /**< \brief [7:0] Data Byte 0 of Message Object n (rwh) */
+ unsigned int DB1:8; /**< \brief [15:8] Data Byte 1 of Message Object n (rwh) */
+ unsigned int DB2:8; /**< \brief [23:16] Data Byte 2 of Message Object n (rwh) */
+ unsigned int DB3:8; /**< \brief [31:24] Data Byte 3 of Message Object n (rwh) */
+} Ifx_CAN_MO_EDATA5_Bits;
+
+/** \brief Extended Message Object Data 6 Register */
+typedef struct _Ifx_CAN_MO_EDATA6_Bits
+{
+ unsigned int DB0:8; /**< \brief [7:0] Data Byte 0 of Message Object n (rwh) */
+ unsigned int DB1:8; /**< \brief [15:8] Data Byte 1 of Message Object n (rwh) */
+ unsigned int DB2:8; /**< \brief [23:16] Data Byte 2 of Message Object n (rwh) */
+ unsigned int DB3:8; /**< \brief [31:24] Data Byte 3 of Message Object n (rwh) */
+} Ifx_CAN_MO_EDATA6_Bits;
+
+/** \brief Message Object Function Control Register */
+typedef struct _Ifx_CAN_MO_FCR_Bits
+{
+ unsigned int MMC:4; /**< \brief [3:0] Message Mode Control (rw) */
+ unsigned int RXTOE:1; /**< \brief [4:4] Receive Time-Out Enable (rw) */
+ unsigned int BRS:1; /**< \brief [5:5] Bit Rate Switch (rwh) */
+ unsigned int FDF:1; /**< \brief [6:6] CAN FD Frame Format (rwh) */
+ unsigned int reserved_7:1; /**< \brief \internal Reserved */
+ unsigned int GDFS:1; /**< \brief [8:8] Gateway Data Frame Send (rw) */
+ unsigned int IDC:1; /**< \brief [9:9] Identifier Copy (rw) */
+ unsigned int DLCC:1; /**< \brief [10:10] Data Length Code Copy (rw) */
+ unsigned int DATC:1; /**< \brief [11:11] Data Copy (rw) */
+ unsigned int reserved_12:4; /**< \brief \internal Reserved */
+ unsigned int RXIE:1; /**< \brief [16:16] Receive Interrupt Enable (rw) */
+ unsigned int TXIE:1; /**< \brief [17:17] Transmit Interrupt Enable (rw) */
+ unsigned int OVIE:1; /**< \brief [18:18] Overflow Interrupt Enable (rw) */
+ unsigned int reserved_19:1; /**< \brief \internal Reserved */
+ unsigned int FRREN:1; /**< \brief [20:20] Foreign Remote Request Enable (rw) */
+ unsigned int RMM:1; /**< \brief [21:21] Transmit Object Remote Monitoring (rw) */
+ unsigned int SDT:1; /**< \brief [22:22] Single Data Transfer (rw) */
+ unsigned int STT:1; /**< \brief [23:23] Single Transmit Trial (rw) */
+ unsigned int DLC:4; /**< \brief [27:24] Data Length Code (rwh) */
+ unsigned int reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_CAN_MO_FCR_Bits;
+
+/** \brief Message Object FIFO/Gateway Pointer Register */
+typedef struct _Ifx_CAN_MO_FGPR_Bits
+{
+ unsigned int BOT:8; /**< \brief [7:0] Bottom Pointer (rw) */
+ unsigned int TOP:8; /**< \brief [15:8] Top Pointer (rw) */
+ unsigned int CUR:8; /**< \brief [23:16] Current Object Pointer (rwh) */
+ unsigned int SEL:8; /**< \brief [31:24] Object Select Pointer (rw) */
+} Ifx_CAN_MO_FGPR_Bits;
+
+/** \brief Message Object Interrupt Pointer Register */
+typedef struct _Ifx_CAN_MO_IPR_Bits
+{
+ unsigned int RXINP:4; /**< \brief [3:0] Receive Interrupt Node Pointer (rw) */
+ unsigned int TXINP:4; /**< \brief [7:4] Transmit Interrupt Node Pointer (rw) */
+ unsigned int MPN:8; /**< \brief [15:8] Message Pending Number (rw) */
+ unsigned int CFCVAL:16; /**< \brief [31:16] CAN Frame Counter Value (rwh) */
+} Ifx_CAN_MO_IPR_Bits;
+
+/** \brief Message Object Status Register */
+typedef struct _Ifx_CAN_MO_STAT_Bits
+{
+ unsigned int RXPND:1; /**< \brief [0:0] Receive Pending (rh) */
+ unsigned int TXPND:1; /**< \brief [1:1] Transmit Pending (rh) */
+ unsigned int RXUPD:1; /**< \brief [2:2] Receive Updating (rh) */
+ unsigned int NEWDAT:1; /**< \brief [3:3] New Data (rh) */
+ unsigned int MSGLST:1; /**< \brief [4:4] Message Lost (rh) */
+ unsigned int MSGVAL:1; /**< \brief [5:5] Message Valid (rh) */
+ unsigned int RTSEL:1; /**< \brief [6:6] Receive/Transmit Selected (rh) */
+ unsigned int RXEN:1; /**< \brief [7:7] Receive Enable (rh) */
+ unsigned int TXRQ:1; /**< \brief [8:8] Transmit Request (rh) */
+ unsigned int TXEN0:1; /**< \brief [9:9] Transmit Enable 0 (rh) */
+ unsigned int TXEN1:1; /**< \brief [10:10] Transmit Enable 1 (rh) */
+ unsigned int DIR:1; /**< \brief [11:11] Message Direction (rh) */
+ unsigned int LIST:4; /**< \brief [15:12] List Allocation (rh) */
+ unsigned int PPREV:8; /**< \brief [23:16] Pointer to Previous Message Object (rh) */
+ unsigned int PNEXT:8; /**< \brief [31:24] Pointer to Next Message Object (rh) */
+} Ifx_CAN_MO_STAT_Bits;
+
+/** \brief Message Index Register */
+typedef struct _Ifx_CAN_MSID_Bits
+{
+ unsigned int INDEX:6; /**< \brief [5:0] Message Pending Index (rh) */
+ unsigned int reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_CAN_MSID_Bits;
+
+/** \brief Message Index Mask Register */
+typedef struct _Ifx_CAN_MSIMASK_Bits
+{
+ unsigned int IM:32; /**< \brief [31:0] Message Index Mask (rw) */
+} Ifx_CAN_MSIMASK_Bits;
+
+/** \brief Message Pending Register */
+typedef struct _Ifx_CAN_MSPND_Bits
+{
+ unsigned int PND:32; /**< \brief [31:0] Message Pending (rwh) */
+} Ifx_CAN_MSPND_Bits;
+
+/** \brief Node Bit Timing Extended View Register */
+typedef struct _Ifx_CAN_N_BTEVR_Bits
+{
+ unsigned int BRP:6; /**< \brief [5:0] Baud Rate Prescaler (rw) */
+ unsigned int reserved_6:2; /**< \brief \internal Reserved */
+ unsigned int SJW:4; /**< \brief [11:8] (Re) Synchronization Jump Width (rw) */
+ unsigned int reserved_12:3; /**< \brief \internal Reserved */
+ unsigned int DIV8:1; /**< \brief [15:15] Divide Prescaler Clock by 8 (rw) */
+ unsigned int TSEG2:5; /**< \brief [20:16] Time Segment After Sample Point (rw) */
+ unsigned int reserved_21:1; /**< \brief \internal Reserved */
+ unsigned int TSEG1:6; /**< \brief [27:22] Time Segment Before Sample Point (rw) */
+ unsigned int reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_CAN_N_BTEVR_Bits;
+
+/** \brief Node Bit Timing Register */
+typedef struct _Ifx_CAN_N_BTR_Bits
+{
+ unsigned int BRP:6; /**< \brief [5:0] Baud Rate Prescaler (rw) */
+ unsigned int SJW:2; /**< \brief [7:6] (Re) Synchronization Jump Width (rw) */
+ unsigned int TSEG1:4; /**< \brief [11:8] Time Segment Before Sample Point (rw) */
+ unsigned int TSEG2:3; /**< \brief [14:12] Time Segment After Sample Point (rw) */
+ unsigned int DIV8:1; /**< \brief [15:15] Divide Prescaler Clock by 8 (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CAN_N_BTR_Bits;
+
+/** \brief Node Control Register */
+typedef struct _Ifx_CAN_N_CR_Bits
+{
+ unsigned int INIT:1; /**< \brief [0:0] Node Initialization (rwh) */
+ unsigned int TRIE:1; /**< \brief [1:1] Transfer Interrupt Enable (rw) */
+ unsigned int LECIE:1; /**< \brief [2:2] LEC Indicated Error Interrupt Enable (rw) */
+ unsigned int ALIE:1; /**< \brief [3:3] Alert Interrupt Enable (rw) */
+ unsigned int CANDIS:1; /**< \brief [4:4] CAN Disable (rw) */
+ unsigned int TXDIS:1; /**< \brief [5:5] Transmit Disable (rw) */
+ unsigned int CCE:1; /**< \brief [6:6] Configuration Change Enable (rw) */
+ unsigned int CALM:1; /**< \brief [7:7] CAN Analyzer Mode (rw) */
+ unsigned int SUSEN:1; /**< \brief [8:8] Suspend Enable (rw) */
+ unsigned int FDEN:1; /**< \brief [9:9] CAN Flexible Data-Rate Enable (rw) */
+ unsigned int reserved_10:22; /**< \brief \internal Reserved */
+} Ifx_CAN_N_CR_Bits;
+
+/** \brief Node Error Counter Register */
+typedef struct _Ifx_CAN_N_ECNT_Bits
+{
+ unsigned int REC:8; /**< \brief [7:0] Receive Error Counter (rwh) */
+ unsigned int TEC:8; /**< \brief [15:8] Transmit Error Counter (rwh) */
+ unsigned int EWRNLVL:8; /**< \brief [23:16] Error Warning Level (rw) */
+ unsigned int LETD:1; /**< \brief [24:24] Last Error Transfer Direction (rh) */
+ unsigned int LEINC:1; /**< \brief [25:25] Last Error Increment (rh) */
+ unsigned int reserved_26:6; /**< \brief \internal Reserved */
+} Ifx_CAN_N_ECNT_Bits;
+
+/** \brief Fast Node Bit Timing Register */
+typedef struct _Ifx_CAN_N_FBTR_Bits
+{
+ unsigned int FBRP:6; /**< \brief [5:0] Fast Baud Rate Prescaler (rw) */
+ unsigned int FSJW:2; /**< \brief [7:6] Fast (Re) Synchronization Jump Width (rw) */
+ unsigned int FTSEG1:4; /**< \brief [11:8] Fast Time Segment Before Sample Point (rw) */
+ unsigned int FTSEG2:3; /**< \brief [14:12] Fast Time Segment After Sample Point (rw) */
+ unsigned int reserved_15:17; /**< \brief \internal Reserved */
+} Ifx_CAN_N_FBTR_Bits;
+
+/** \brief Node Frame Counter Register */
+typedef struct _Ifx_CAN_N_FCR_Bits
+{
+ unsigned int CFC:16; /**< \brief [15:0] CAN Frame Counter (rwh) */
+ unsigned int CFSEL:3; /**< \brief [18:16] CAN Frame Count Selection (rw) */
+ unsigned int CFMOD:2; /**< \brief [20:19] CAN Frame Counter Mode (rw) */
+ unsigned int reserved_21:1; /**< \brief \internal Reserved */
+ unsigned int CFCIE:1; /**< \brief [22:22] CAN Frame Count Interrupt Enable (rw) */
+ unsigned int CFCOV:1; /**< \brief [23:23] CAN Frame Counter Overflow Flag (rwh) */
+ unsigned int reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CAN_N_FCR_Bits;
+
+/** \brief Node Interrupt Pointer Register */
+typedef struct _Ifx_CAN_N_IPR_Bits
+{
+ unsigned int ALINP:4; /**< \brief [3:0] Alert Interrupt Node Pointer (rw) */
+ unsigned int LECINP:4; /**< \brief [7:4] Last Error Code Interrupt Node Pointer (rw) */
+ unsigned int TRINP:4; /**< \brief [11:8] Transfer OK Interrupt Node Pointer (rw) */
+ unsigned int CFCINP:4; /**< \brief [15:12] Frame Counter Interrupt Node Pointer (rw) */
+ unsigned int TEINP:4; /**< \brief [19:16] Timer Event Interrupt Node Pointer (rw) */
+ unsigned int reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_CAN_N_IPR_Bits;
+
+/** \brief Node Port Control Register */
+typedef struct _Ifx_CAN_N_PCR_Bits
+{
+ unsigned int RXSEL:3; /**< \brief [2:0] Receive Select (rw) */
+ unsigned int reserved_3:5; /**< \brief \internal Reserved */
+ unsigned int LBM:1; /**< \brief [8:8] Loop-Back Mode (rw) */
+ unsigned int reserved_9:23; /**< \brief \internal Reserved */
+} Ifx_CAN_N_PCR_Bits;
+
+/** \brief Node Status Register */
+typedef struct _Ifx_CAN_N_SR_Bits
+{
+ unsigned int LEC:3; /**< \brief [2:0] Last Error Code (rwh) */
+ unsigned int TXOK:1; /**< \brief [3:3] Message Transmitted Successfully (rwh) */
+ unsigned int RXOK:1; /**< \brief [4:4] Message Received Successfully (rwh) */
+ unsigned int ALERT:1; /**< \brief [5:5] Alert Warning (rwh) */
+ unsigned int EWRN:1; /**< \brief [6:6] Error Warning Status (rh) */
+ unsigned int BOFF:1; /**< \brief [7:7] Bus-off Status (rh) */
+ unsigned int LLE:1; /**< \brief [8:8] List Length Error (rwh) */
+ unsigned int LOE:1; /**< \brief [9:9] List Object Error (rwh) */
+ unsigned int SUSACK:1; /**< \brief [10:10] Suspend Acknowledge (rh) */
+ unsigned int RESI:1; /**< \brief [11:11] Received Error State Indicator Flag This bit is an error flag that is set when the ESI flag in a received CAN FD frame is set. (rh) */
+ unsigned int FLEC:3; /**< \brief [14:12] Fast Last Error Code (rwh) */
+ unsigned int reserved_15:17; /**< \brief \internal Reserved */
+} Ifx_CAN_N_SR_Bits;
+
+/** \brief Node Timer Clock Control Register */
+typedef struct _Ifx_CAN_N_TCCR_Bits
+{
+ unsigned int reserved_0:8; /**< \brief \internal Reserved */
+ unsigned int TPSC:4; /**< \brief [11:8] Timer Prescaler (rw) */
+ unsigned int reserved_12:6; /**< \brief \internal Reserved */
+ unsigned int TRIGSRC:3; /**< \brief [20:18] Trigger Source (rw) */
+ unsigned int reserved_21:11; /**< \brief \internal Reserved */
+} Ifx_CAN_N_TCCR_Bits;
+
+/** \brief Node Transmitter Delay Compensation Register */
+typedef struct _Ifx_CAN_N_TDCR_Bits
+{
+ unsigned int TDCV:5; /**< \brief [4:0] Transmitter Delay Compensation Value (r) */
+ unsigned int reserved_5:3; /**< \brief \internal Reserved */
+ unsigned int TDCO:4; /**< \brief [11:8] Transmitter Delay Compensation Offset (rw) */
+ unsigned int reserved_12:3; /**< \brief \internal Reserved */
+ unsigned int TDC:1; /**< \brief [15:15] Transmitter Delay Compensation Enable (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CAN_N_TDCR_Bits;
+
+/** \brief Node Timer Receive Timeout Register */
+typedef struct _Ifx_CAN_N_TRTR_Bits
+{
+ unsigned int RELOAD:16; /**< \brief [15:0] Reload Value (rw) */
+ unsigned int reserved_16:6; /**< \brief \internal Reserved */
+ unsigned int TEIE:1; /**< \brief [22:22] Timer Event Interrupt Enable (rw) */
+ unsigned int TE:1; /**< \brief [23:23] Timer Event (rwh) */
+ unsigned int reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CAN_N_TRTR_Bits;
+
+/** \brief Node Timer Transmit Trigger Register */
+typedef struct _Ifx_CAN_N_TTTR_Bits
+{
+ unsigned int RELOAD:16; /**< \brief [15:0] Reload Value (rw) */
+ unsigned int TXMO:8; /**< \brief [23:16] Transmit Message Object (rw) */
+ unsigned int STRT:1; /**< \brief [24:24] Timer Start (rw) */
+ unsigned int reserved_25:7; /**< \brief \internal Reserved */
+} Ifx_CAN_N_TTTR_Bits;
+
+/** \brief OCDS Control and Status */
+typedef struct _Ifx_CAN_OCS_Bits
+{
+ unsigned int TGS:2; /**< \brief [1:0] Trigger Set for OTGB0/1 (rw) */
+ unsigned int TGB:1; /**< \brief [2:2] OTGB0/1 Bus Select (rw) */
+ unsigned int TG_P:1; /**< \brief [3:3] TGS, TGB Write Protection (w) */
+ unsigned int reserved_4:20; /**< \brief \internal Reserved */
+ unsigned int SUS:4; /**< \brief [27:24] OCDS Suspend Control (rw) */
+ unsigned int SUS_P:1; /**< \brief [28:28] SUS Write Protection (w) */
+ unsigned int SUSSTA:1; /**< \brief [29:29] Suspend State (rh) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_CAN_OCS_Bits;
+
+/** \brief Panel Control Register */
+typedef struct _Ifx_CAN_PANCTR_Bits
+{
+ unsigned int PANCMD:8; /**< \brief [7:0] Panel Command (rwh) */
+ unsigned int BUSY:1; /**< \brief [8:8] Panel Busy Flag (rh) */
+ unsigned int RBUSY:1; /**< \brief [9:9] Result Busy Flag (rh) */
+ unsigned int reserved_10:6; /**< \brief \internal Reserved */
+ unsigned int PANAR1:8; /**< \brief [23:16] Panel Argument 1 (rwh) */
+ unsigned int PANAR2:8; /**< \brief [31:24] Panel Argument 2 (rwh) */
+} Ifx_CAN_PANCTR_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Can_union
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_ACCEN0_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_ACCEN0;
+
+/** \brief Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_ACCEN1_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_ACCEN1;
+
+/** \brief CAN Clock Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_CLC_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_CLC;
+
+/** \brief CAN Fractional Divider Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_FDR_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_FDR;
+
+/** \brief Module Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_ID;
+
+/** \brief Kernel Reset Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_KRST0_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_KRST0;
+
+/** \brief Kernel Reset Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_KRST1_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_KRST1;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_KRSTCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_KRSTCLR;
+
+/** \brief List Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_LIST_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_LIST;
+
+/** \brief Module Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_MCR_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_MCR;
+
+/** \brief Measure Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_MECR_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_MECR;
+
+/** \brief Measure Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_MESTAT_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_MESTAT;
+
+/** \brief Module Interrupt Trigger Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_MITR_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_MITR;
+
+/** \brief Message Object Acceptance Mask Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_MO_AMR_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_MO_AMR;
+
+/** \brief Message Object Arbitration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_MO_AR_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_MO_AR;
+
+/** \brief Message Object Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_MO_CTR_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_MO_CTR;
+
+/** \brief Message Object Data Register High */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_MO_DATAH_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_MO_DATAH;
+
+/** \brief Message Object Data Register Low */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_MO_DATAL_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_MO_DATAL;
+
+/** \brief Extended Message Object Data 0 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_MO_EDATA0_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_MO_EDATA0;
+
+/** \brief Extended Message Object Data 1 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_MO_EDATA1_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_MO_EDATA1;
+
+/** \brief Extended Message Object Data 2 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_MO_EDATA2_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_MO_EDATA2;
+
+/** \brief Extended Message Object Data 3 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_MO_EDATA3_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_MO_EDATA3;
+
+/** \brief Extended Message Object Data 4 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_MO_EDATA4_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_MO_EDATA4;
+
+/** \brief Extended Message Object Data 5 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_MO_EDATA5_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_MO_EDATA5;
+
+/** \brief Extended Message Object Data 6 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_MO_EDATA6_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_MO_EDATA6;
+
+/** \brief Message Object Function Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_MO_FCR_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_MO_FCR;
+
+/** \brief Message Object FIFO/Gateway Pointer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_MO_FGPR_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_MO_FGPR;
+
+/** \brief Message Object Interrupt Pointer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_MO_IPR_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_MO_IPR;
+
+/** \brief Message Object Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_MO_STAT_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_MO_STAT;
+
+/** \brief Message Index Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_MSID_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_MSID;
+
+/** \brief Message Index Mask Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_MSIMASK_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_MSIMASK;
+
+/** \brief Message Pending Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_MSPND_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_MSPND;
+
+/** \brief Node Bit Timing Extended View Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_N_BTEVR_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_N_BTEVR;
+
+/** \brief Node Bit Timing Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_N_BTR_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_N_BTR;
+
+/** \brief Node Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_N_CR_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_N_CR;
+
+/** \brief Node Error Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_N_ECNT_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_N_ECNT;
+
+/** \brief Fast Node Bit Timing Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_N_FBTR_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_N_FBTR;
+
+/** \brief Node Frame Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_N_FCR_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_N_FCR;
+
+/** \brief Node Interrupt Pointer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_N_IPR_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_N_IPR;
+
+/** \brief Node Port Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_N_PCR_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_N_PCR;
+
+/** \brief Node Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_N_SR_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_N_SR;
+
+/** \brief Node Timer Clock Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_N_TCCR_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_N_TCCR;
+
+/** \brief Node Transmitter Delay Compensation Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_N_TDCR_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_N_TDCR;
+
+/** \brief Node Timer Receive Timeout Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_N_TRTR_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_N_TRTR;
+
+/** \brief Node Timer Transmit Trigger Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_N_TTTR_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_N_TTTR;
+
+/** \brief OCDS Control and Status */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_OCS_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_OCS;
+
+/** \brief Panel Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CAN_PANCTR_Bits B; /**< \brief Bitfield access */
+} Ifx_CAN_PANCTR;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Can_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L1
+ * \{ */
+
+/** \brief Message object */
+typedef volatile struct _Ifx_CAN_MO
+{
+ union
+ {
+ Ifx_CAN_MO_EDATA0 EDATA0; /**< \brief 0, Message Object Function Control Register */
+ Ifx_CAN_MO_FCR FCR; /**< \brief 0, Message Object Function Control Register */
+ };
+
+ union
+ {
+ Ifx_CAN_MO_EDATA1 EDATA1; /**< \brief 4, Message Object FIFO/Gateway Pointer Register */
+ Ifx_CAN_MO_FGPR FGPR; /**< \brief 4, Message Object FIFO/Gateway Pointer Register */
+ };
+
+ union
+ {
+ Ifx_CAN_MO_EDATA2 EDATA2; /**< \brief 8, Message Object Interrupt Pointer Register */
+ Ifx_CAN_MO_IPR IPR; /**< \brief 8, Message Object Interrupt Pointer Register */
+ };
+
+ union
+ {
+ Ifx_CAN_MO_AMR AMR; /**< \brief C, Message Object Acceptance Mask Register */
+ Ifx_CAN_MO_EDATA3 EDATA3; /**< \brief C, Message Object Acceptance Mask Register */
+ };
+
+ union
+ {
+ Ifx_CAN_MO_DATAL DATAL; /**< \brief 10, Message Object Data Register Low */
+ Ifx_CAN_MO_EDATA4 EDATA4; /**< \brief 10, Message Object Data Register Low */
+ };
+
+ union
+ {
+ Ifx_CAN_MO_DATAH DATAH; /**< \brief 14, Message Object Data Register High */
+ Ifx_CAN_MO_EDATA5 EDATA5; /**< \brief 14, Message Object Data Register High */
+ };
+
+ union
+ {
+ Ifx_CAN_MO_AR AR; /**< \brief 18, Message Object Arbitration Register */
+ Ifx_CAN_MO_EDATA6 EDATA6; /**< \brief 18, Message Object Arbitration Register */
+ };
+
+ union
+ {
+ Ifx_CAN_MO_CTR CTR; /**< \brief 1C, Message Object Control Register */
+ Ifx_CAN_MO_STAT STAT; /**< \brief 1C, Message Object Control Register */
+ };
+
+} Ifx_CAN_MO;
+
+/** \brief Node object */
+typedef volatile struct _Ifx_CAN_N
+{
+ Ifx_CAN_N_CR CR; /**< \brief 0, Node Control Register */
+ Ifx_CAN_N_SR SR; /**< \brief 4, Node Status Register */
+ Ifx_CAN_N_IPR IPR; /**< \brief 8, Node Interrupt Pointer Register */
+ Ifx_CAN_N_PCR PCR; /**< \brief C, Node Port Control Register */
+ union
+ {
+ Ifx_CAN_N_BTEVR BTEVR; /**< \brief 10, Node Bit Timing Register */
+ Ifx_CAN_N_BTR BTR; /**< \brief 10, Node Bit Timing Register */
+ };
+
+ Ifx_CAN_N_ECNT ECNT; /**< \brief 14, Node Error Counter Register */
+ Ifx_CAN_N_FCR FCR; /**< \brief 18, Node Frame Counter Register */
+ Ifx_CAN_N_TCCR TCCR; /**< \brief 1C, Node Timer Clock Control Register */
+ Ifx_CAN_N_TRTR TRTR; /**< \brief 20, Node Timer Receive Timeout Register */
+ Ifx_CAN_N_TTTR TATTR; /**< \brief 24, Node Timer A Transmit Trigger Register */
+ Ifx_CAN_N_TTTR TBTTR; /**< \brief 28, Node Timer B Transmit Trigger Register */
+ Ifx_CAN_N_TTTR TCTTR; /**< \brief 2C, Node Timer C Transmit Trigger Register */
+ unsigned char reserved_30[8]; /**< \brief 30, \internal Reserved */
+ Ifx_CAN_N_FBTR FBTR; /**< \brief 38, Fast Node Bit Timing Register */
+ Ifx_CAN_N_TDCR TDCR; /**< \brief 3C, Node Transmitter Delay Compensation Register */
+ unsigned char reserved_40[192]; /**< \brief 40, \internal Reserved */
+} Ifx_CAN_N;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Can_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief CAN object */
+typedef volatile struct _Ifx_CAN
+{
+ Ifx_CAN_CLC CLC; /**< \brief 0, CAN Clock Control Register */
+ unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
+ Ifx_CAN_ID ID; /**< \brief 8, Module Identification Register */
+ Ifx_CAN_FDR FDR; /**< \brief C, CAN Fractional Divider Register */
+ unsigned char reserved_10[216]; /**< \brief 10, \internal Reserved */
+ Ifx_CAN_OCS OCS; /**< \brief E8, OCDS Control and Status */
+ Ifx_CAN_KRSTCLR KRSTCLR; /**< \brief EC, Kernel Reset Status Clear Register */
+ Ifx_CAN_KRST1 KRST1; /**< \brief F0, Kernel Reset Register 1 */
+ Ifx_CAN_KRST0 KRST0; /**< \brief F4, Kernel Reset Register 0 */
+ Ifx_CAN_ACCEN1 ACCEN1; /**< \brief F8, Access Enable Register 1 */
+ Ifx_CAN_ACCEN0 ACCEN0; /**< \brief FC, Access Enable Register 0 */
+ Ifx_CAN_LIST LIST[16]; /**< \brief 100, List Register */
+ Ifx_CAN_MSPND MSPND[8]; /**< \brief 140, Message Pending Register */
+ unsigned char reserved_160[32]; /**< \brief 160, \internal Reserved */
+ Ifx_CAN_MSID MSID[8]; /**< \brief 180, Message Index Register */
+ unsigned char reserved_1A0[32]; /**< \brief 1A0, \internal Reserved */
+ Ifx_CAN_MSIMASK MSIMASK; /**< \brief 1C0, Message Index Mask Register */
+ Ifx_CAN_PANCTR PANCTR; /**< \brief 1C4, Panel Control Register */
+ Ifx_CAN_MCR MCR; /**< \brief 1C8, Module Control Register */
+ Ifx_CAN_MITR MITR; /**< \brief 1CC, Module Interrupt Trigger Register */
+ Ifx_CAN_MECR MECR; /**< \brief 1D0, Measure Control Register */
+ Ifx_CAN_MESTAT MESTAT; /**< \brief 1D4, Measure Status Register */
+ unsigned char reserved_1D8[40]; /**< \brief 1D8, \internal Reserved */
+ Ifx_CAN_N N[5]; /**< \brief 200, Node object */
+ unsigned char reserved_700[2304]; /**< \brief 700, \internal Reserved */
+ Ifx_CAN_MO MO[256]; /**< \brief 1000, Message objects */
+ unsigned char reserved_3000[4096]; /**< \brief 3000, \internal Reserved */
+} Ifx_CAN;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#if defined (__TASKING__)
+#pragma warning restore
+#endif
+/******************************************************************************/
+#endif /* IFXCAN_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCbs_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCbs_bf.h
new file mode 100644
index 0000000..bf7aad4
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCbs_bf.h
@@ -0,0 +1,2493 @@
+/**
+ * \file IfxCbs_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Cbs_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Cbs
+ *
+ */
+#ifndef IFXCBS_BF_H
+#define IFXCBS_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Cbs_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_CBS_COMDATA_Bits.DATA */
+#define IFX_CBS_COMDATA_DATA_LEN (32u)
+
+/** \brief Mask for Ifx_CBS_COMDATA_Bits.DATA */
+#define IFX_CBS_COMDATA_DATA_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_CBS_COMDATA_Bits.DATA */
+#define IFX_CBS_COMDATA_DATA_OFF (0u)
+
+/** \brief Length for Ifx_CBS_ICTSA_Bits.ADDR */
+#define IFX_CBS_ICTSA_ADDR_LEN (32u)
+
+/** \brief Mask for Ifx_CBS_ICTSA_Bits.ADDR */
+#define IFX_CBS_ICTSA_ADDR_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_CBS_ICTSA_Bits.ADDR */
+#define IFX_CBS_ICTSA_ADDR_OFF (0u)
+
+/** \brief Length for Ifx_CBS_ICTTA_Bits.ADDR */
+#define IFX_CBS_ICTTA_ADDR_LEN (32u)
+
+/** \brief Mask for Ifx_CBS_ICTTA_Bits.ADDR */
+#define IFX_CBS_ICTTA_ADDR_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_CBS_ICTTA_Bits.ADDR */
+#define IFX_CBS_ICTTA_ADDR_OFF (0u)
+
+/** \brief Length for Ifx_CBS_INTMOD_Bits.CHANNEL */
+#define IFX_CBS_INTMOD_CHANNEL_LEN (3u)
+
+/** \brief Mask for Ifx_CBS_INTMOD_Bits.CHANNEL */
+#define IFX_CBS_INTMOD_CHANNEL_MSK (0x7u)
+
+/** \brief Offset for Ifx_CBS_INTMOD_Bits.CHANNEL */
+#define IFX_CBS_INTMOD_CHANNEL_OFF (5u)
+
+/** \brief Length for Ifx_CBS_INTMOD_Bits.CHANNEL_P */
+#define IFX_CBS_INTMOD_CHANNEL_P_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_INTMOD_Bits.CHANNEL_P */
+#define IFX_CBS_INTMOD_CHANNEL_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_INTMOD_Bits.CHANNEL_P */
+#define IFX_CBS_INTMOD_CHANNEL_P_OFF (4u)
+
+/** \brief Length for Ifx_CBS_INTMOD_Bits.CLR_CS */
+#define IFX_CBS_INTMOD_CLR_CS_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_INTMOD_Bits.CLR_CS */
+#define IFX_CBS_INTMOD_CLR_CS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_INTMOD_Bits.CLR_CS */
+#define IFX_CBS_INTMOD_CLR_CS_OFF (3u)
+
+/** \brief Length for Ifx_CBS_INTMOD_Bits.CLR_INT_TRC */
+#define IFX_CBS_INTMOD_CLR_INT_TRC_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_INTMOD_Bits.CLR_INT_TRC */
+#define IFX_CBS_INTMOD_CLR_INT_TRC_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_INTMOD_Bits.CLR_INT_TRC */
+#define IFX_CBS_INTMOD_CLR_INT_TRC_OFF (19u)
+
+/** \brief Length for Ifx_CBS_INTMOD_Bits.INT_MOD */
+#define IFX_CBS_INTMOD_INT_MOD_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_INTMOD_Bits.INT_MOD */
+#define IFX_CBS_INTMOD_INT_MOD_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_INTMOD_Bits.INT_MOD */
+#define IFX_CBS_INTMOD_INT_MOD_OFF (24u)
+
+/** \brief Length for Ifx_CBS_INTMOD_Bits.INT_TRC */
+#define IFX_CBS_INTMOD_INT_TRC_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_INTMOD_Bits.INT_TRC */
+#define IFX_CBS_INTMOD_INT_TRC_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_INTMOD_Bits.INT_TRC */
+#define IFX_CBS_INTMOD_INT_TRC_OFF (25u)
+
+/** \brief Length for Ifx_CBS_INTMOD_Bits.SET_CRS */
+#define IFX_CBS_INTMOD_SET_CRS_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_INTMOD_Bits.SET_CRS */
+#define IFX_CBS_INTMOD_SET_CRS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_INTMOD_Bits.SET_CRS */
+#define IFX_CBS_INTMOD_SET_CRS_OFF (0u)
+
+/** \brief Length for Ifx_CBS_INTMOD_Bits.SET_CS */
+#define IFX_CBS_INTMOD_SET_CS_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_INTMOD_Bits.SET_CS */
+#define IFX_CBS_INTMOD_SET_CS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_INTMOD_Bits.SET_CS */
+#define IFX_CBS_INTMOD_SET_CS_OFF (2u)
+
+/** \brief Length for Ifx_CBS_INTMOD_Bits.SET_CWS */
+#define IFX_CBS_INTMOD_SET_CWS_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_INTMOD_Bits.SET_CWS */
+#define IFX_CBS_INTMOD_SET_CWS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_INTMOD_Bits.SET_CWS */
+#define IFX_CBS_INTMOD_SET_CWS_OFF (1u)
+
+/** \brief Length for Ifx_CBS_INTMOD_Bits.SET_INT_MOD */
+#define IFX_CBS_INTMOD_SET_INT_MOD_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_INTMOD_Bits.SET_INT_MOD */
+#define IFX_CBS_INTMOD_SET_INT_MOD_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_INTMOD_Bits.SET_INT_MOD */
+#define IFX_CBS_INTMOD_SET_INT_MOD_OFF (16u)
+
+/** \brief Length for Ifx_CBS_INTMOD_Bits.SET_INT_TRC */
+#define IFX_CBS_INTMOD_SET_INT_TRC_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_INTMOD_Bits.SET_INT_TRC */
+#define IFX_CBS_INTMOD_SET_INT_TRC_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_INTMOD_Bits.SET_INT_TRC */
+#define IFX_CBS_INTMOD_SET_INT_TRC_OFF (18u)
+
+/** \brief Length for Ifx_CBS_INTMOD_Bits.TRC_MOD */
+#define IFX_CBS_INTMOD_TRC_MOD_LEN (2u)
+
+/** \brief Mask for Ifx_CBS_INTMOD_Bits.TRC_MOD */
+#define IFX_CBS_INTMOD_TRC_MOD_MSK (0x3u)
+
+/** \brief Offset for Ifx_CBS_INTMOD_Bits.TRC_MOD */
+#define IFX_CBS_INTMOD_TRC_MOD_OFF (21u)
+
+/** \brief Length for Ifx_CBS_INTMOD_Bits.TRC_MOD_P */
+#define IFX_CBS_INTMOD_TRC_MOD_P_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_INTMOD_Bits.TRC_MOD_P */
+#define IFX_CBS_INTMOD_TRC_MOD_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_INTMOD_Bits.TRC_MOD_P */
+#define IFX_CBS_INTMOD_TRC_MOD_P_OFF (20u)
+
+/** \brief Length for Ifx_CBS_IOSR_Bits.CHANNEL */
+#define IFX_CBS_IOSR_CHANNEL_LEN (3u)
+
+/** \brief Mask for Ifx_CBS_IOSR_Bits.CHANNEL */
+#define IFX_CBS_IOSR_CHANNEL_MSK (0x7u)
+
+/** \brief Offset for Ifx_CBS_IOSR_Bits.CHANNEL */
+#define IFX_CBS_IOSR_CHANNEL_OFF (12u)
+
+/** \brief Length for Ifx_CBS_IOSR_Bits.COM_SYNC */
+#define IFX_CBS_IOSR_COM_SYNC_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_IOSR_Bits.COM_SYNC */
+#define IFX_CBS_IOSR_COM_SYNC_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_IOSR_Bits.COM_SYNC */
+#define IFX_CBS_IOSR_COM_SYNC_OFF (7u)
+
+/** \brief Length for Ifx_CBS_IOSR_Bits.CRSYNC */
+#define IFX_CBS_IOSR_CRSYNC_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_IOSR_Bits.CRSYNC */
+#define IFX_CBS_IOSR_CRSYNC_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_IOSR_Bits.CRSYNC */
+#define IFX_CBS_IOSR_CRSYNC_OFF (4u)
+
+/** \brief Length for Ifx_CBS_IOSR_Bits.CW_ACK */
+#define IFX_CBS_IOSR_CW_ACK_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_IOSR_Bits.CW_ACK */
+#define IFX_CBS_IOSR_CW_ACK_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_IOSR_Bits.CW_ACK */
+#define IFX_CBS_IOSR_CW_ACK_OFF (6u)
+
+/** \brief Length for Ifx_CBS_IOSR_Bits.CWSYNC */
+#define IFX_CBS_IOSR_CWSYNC_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_IOSR_Bits.CWSYNC */
+#define IFX_CBS_IOSR_CWSYNC_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_IOSR_Bits.CWSYNC */
+#define IFX_CBS_IOSR_CWSYNC_OFF (5u)
+
+/** \brief Length for Ifx_CBS_IOSR_Bits.HOSTED */
+#define IFX_CBS_IOSR_HOSTED_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_IOSR_Bits.HOSTED */
+#define IFX_CBS_IOSR_HOSTED_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_IOSR_Bits.HOSTED */
+#define IFX_CBS_IOSR_HOSTED_OFF (8u)
+
+/** \brief Length for Ifx_CBS_JDPID_Bits.MODNUMBER */
+#define IFX_CBS_JDPID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_CBS_JDPID_Bits.MODNUMBER */
+#define IFX_CBS_JDPID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CBS_JDPID_Bits.MODNUMBER */
+#define IFX_CBS_JDPID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_CBS_JDPID_Bits.MODREV */
+#define IFX_CBS_JDPID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_CBS_JDPID_Bits.MODREV */
+#define IFX_CBS_JDPID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_CBS_JDPID_Bits.MODREV */
+#define IFX_CBS_JDPID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_CBS_JDPID_Bits.MODTYPE */
+#define IFX_CBS_JDPID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_CBS_JDPID_Bits.MODTYPE */
+#define IFX_CBS_JDPID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_CBS_JDPID_Bits.MODTYPE */
+#define IFX_CBS_JDPID_MODTYPE_OFF (8u)
+
+/** \brief Length for Ifx_CBS_JTAGID_Bits.JTAG_ID */
+#define IFX_CBS_JTAGID_JTAG_ID_LEN (32u)
+
+/** \brief Mask for Ifx_CBS_JTAGID_Bits.JTAG_ID */
+#define IFX_CBS_JTAGID_JTAG_ID_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_CBS_JTAGID_Bits.JTAG_ID */
+#define IFX_CBS_JTAGID_JTAG_ID_OFF (0u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.OC0 */
+#define IFX_CBS_OCNTRL_OC0_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.OC0 */
+#define IFX_CBS_OCNTRL_OC0_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.OC0 */
+#define IFX_CBS_OCNTRL_OC0_OFF (1u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.OC0_P */
+#define IFX_CBS_OCNTRL_OC0_P_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.OC0_P */
+#define IFX_CBS_OCNTRL_OC0_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.OC0_P */
+#define IFX_CBS_OCNTRL_OC0_P_OFF (0u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.OC1 */
+#define IFX_CBS_OCNTRL_OC1_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.OC1 */
+#define IFX_CBS_OCNTRL_OC1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.OC1 */
+#define IFX_CBS_OCNTRL_OC1_OFF (3u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.OC1_P */
+#define IFX_CBS_OCNTRL_OC1_P_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.OC1_P */
+#define IFX_CBS_OCNTRL_OC1_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.OC1_P */
+#define IFX_CBS_OCNTRL_OC1_P_OFF (2u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.OC2 */
+#define IFX_CBS_OCNTRL_OC2_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.OC2 */
+#define IFX_CBS_OCNTRL_OC2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.OC2 */
+#define IFX_CBS_OCNTRL_OC2_OFF (5u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.OC2_P */
+#define IFX_CBS_OCNTRL_OC2_P_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.OC2_P */
+#define IFX_CBS_OCNTRL_OC2_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.OC2_P */
+#define IFX_CBS_OCNTRL_OC2_P_OFF (4u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.OC3 */
+#define IFX_CBS_OCNTRL_OC3_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.OC3 */
+#define IFX_CBS_OCNTRL_OC3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.OC3 */
+#define IFX_CBS_OCNTRL_OC3_OFF (7u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.OC3_P */
+#define IFX_CBS_OCNTRL_OC3_P_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.OC3_P */
+#define IFX_CBS_OCNTRL_OC3_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.OC3_P */
+#define IFX_CBS_OCNTRL_OC3_P_OFF (6u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.OC4 */
+#define IFX_CBS_OCNTRL_OC4_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.OC4 */
+#define IFX_CBS_OCNTRL_OC4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.OC4 */
+#define IFX_CBS_OCNTRL_OC4_OFF (9u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.OC4_P */
+#define IFX_CBS_OCNTRL_OC4_P_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.OC4_P */
+#define IFX_CBS_OCNTRL_OC4_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.OC4_P */
+#define IFX_CBS_OCNTRL_OC4_P_OFF (8u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.OC5 */
+#define IFX_CBS_OCNTRL_OC5_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.OC5 */
+#define IFX_CBS_OCNTRL_OC5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.OC5 */
+#define IFX_CBS_OCNTRL_OC5_OFF (11u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.OC5_P */
+#define IFX_CBS_OCNTRL_OC5_P_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.OC5_P */
+#define IFX_CBS_OCNTRL_OC5_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.OC5_P */
+#define IFX_CBS_OCNTRL_OC5_P_OFF (10u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.OJC0 */
+#define IFX_CBS_OCNTRL_OJC0_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.OJC0 */
+#define IFX_CBS_OCNTRL_OJC0_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.OJC0 */
+#define IFX_CBS_OCNTRL_OJC0_OFF (17u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.OJC0_P */
+#define IFX_CBS_OCNTRL_OJC0_P_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.OJC0_P */
+#define IFX_CBS_OCNTRL_OJC0_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.OJC0_P */
+#define IFX_CBS_OCNTRL_OJC0_P_OFF (16u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.OJC1 */
+#define IFX_CBS_OCNTRL_OJC1_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.OJC1 */
+#define IFX_CBS_OCNTRL_OJC1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.OJC1 */
+#define IFX_CBS_OCNTRL_OJC1_OFF (19u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.OJC1_P */
+#define IFX_CBS_OCNTRL_OJC1_P_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.OJC1_P */
+#define IFX_CBS_OCNTRL_OJC1_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.OJC1_P */
+#define IFX_CBS_OCNTRL_OJC1_P_OFF (18u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.OJC2 */
+#define IFX_CBS_OCNTRL_OJC2_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.OJC2 */
+#define IFX_CBS_OCNTRL_OJC2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.OJC2 */
+#define IFX_CBS_OCNTRL_OJC2_OFF (21u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.OJC2_P */
+#define IFX_CBS_OCNTRL_OJC2_P_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.OJC2_P */
+#define IFX_CBS_OCNTRL_OJC2_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.OJC2_P */
+#define IFX_CBS_OCNTRL_OJC2_P_OFF (20u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.OJC3 */
+#define IFX_CBS_OCNTRL_OJC3_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.OJC3 */
+#define IFX_CBS_OCNTRL_OJC3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.OJC3 */
+#define IFX_CBS_OCNTRL_OJC3_OFF (23u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.OJC3_P */
+#define IFX_CBS_OCNTRL_OJC3_P_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.OJC3_P */
+#define IFX_CBS_OCNTRL_OJC3_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.OJC3_P */
+#define IFX_CBS_OCNTRL_OJC3_P_OFF (22u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.OJC4 */
+#define IFX_CBS_OCNTRL_OJC4_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.OJC4 */
+#define IFX_CBS_OCNTRL_OJC4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.OJC4 */
+#define IFX_CBS_OCNTRL_OJC4_OFF (25u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.OJC4_P */
+#define IFX_CBS_OCNTRL_OJC4_P_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.OJC4_P */
+#define IFX_CBS_OCNTRL_OJC4_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.OJC4_P */
+#define IFX_CBS_OCNTRL_OJC4_P_OFF (24u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.OJC5 */
+#define IFX_CBS_OCNTRL_OJC5_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.OJC5 */
+#define IFX_CBS_OCNTRL_OJC5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.OJC5 */
+#define IFX_CBS_OCNTRL_OJC5_OFF (27u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.OJC5_P */
+#define IFX_CBS_OCNTRL_OJC5_P_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.OJC5_P */
+#define IFX_CBS_OCNTRL_OJC5_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.OJC5_P */
+#define IFX_CBS_OCNTRL_OJC5_P_OFF (26u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.OJC6 */
+#define IFX_CBS_OCNTRL_OJC6_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.OJC6 */
+#define IFX_CBS_OCNTRL_OJC6_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.OJC6 */
+#define IFX_CBS_OCNTRL_OJC6_OFF (29u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.OJC6_P */
+#define IFX_CBS_OCNTRL_OJC6_P_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.OJC6_P */
+#define IFX_CBS_OCNTRL_OJC6_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.OJC6_P */
+#define IFX_CBS_OCNTRL_OJC6_P_OFF (28u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.OJC7 */
+#define IFX_CBS_OCNTRL_OJC7_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.OJC7 */
+#define IFX_CBS_OCNTRL_OJC7_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.OJC7 */
+#define IFX_CBS_OCNTRL_OJC7_OFF (31u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.OJC7_P */
+#define IFX_CBS_OCNTRL_OJC7_P_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.OJC7_P */
+#define IFX_CBS_OCNTRL_OJC7_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.OJC7_P */
+#define IFX_CBS_OCNTRL_OJC7_P_OFF (30u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.STABLE */
+#define IFX_CBS_OCNTRL_STABLE_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.STABLE */
+#define IFX_CBS_OCNTRL_STABLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.STABLE */
+#define IFX_CBS_OCNTRL_STABLE_OFF (15u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.STABLE_P */
+#define IFX_CBS_OCNTRL_STABLE_P_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.STABLE_P */
+#define IFX_CBS_OCNTRL_STABLE_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.STABLE_P */
+#define IFX_CBS_OCNTRL_STABLE_P_OFF (14u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.WDTSUS */
+#define IFX_CBS_OCNTRL_WDTSUS_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.WDTSUS */
+#define IFX_CBS_OCNTRL_WDTSUS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.WDTSUS */
+#define IFX_CBS_OCNTRL_WDTSUS_OFF (13u)
+
+/** \brief Length for Ifx_CBS_OCNTRL_Bits.WDTSUS_P */
+#define IFX_CBS_OCNTRL_WDTSUS_P_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OCNTRL_Bits.WDTSUS_P */
+#define IFX_CBS_OCNTRL_WDTSUS_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OCNTRL_Bits.WDTSUS_P */
+#define IFX_CBS_OCNTRL_WDTSUS_P_OFF (12u)
+
+/** \brief Length for Ifx_CBS_OEC_Bits.AUT_OK */
+#define IFX_CBS_OEC_AUT_OK_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OEC_Bits.AUT_OK */
+#define IFX_CBS_OEC_AUT_OK_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OEC_Bits.AUT_OK */
+#define IFX_CBS_OEC_AUT_OK_OFF (19u)
+
+/** \brief Length for Ifx_CBS_OEC_Bits.AUT_OK_P */
+#define IFX_CBS_OEC_AUT_OK_P_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OEC_Bits.AUT_OK_P */
+#define IFX_CBS_OEC_AUT_OK_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OEC_Bits.AUT_OK_P */
+#define IFX_CBS_OEC_AUT_OK_P_OFF (18u)
+
+/** \brief Length for Ifx_CBS_OEC_Bits.DS */
+#define IFX_CBS_OEC_DS_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OEC_Bits.DS */
+#define IFX_CBS_OEC_DS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OEC_Bits.DS */
+#define IFX_CBS_OEC_DS_OFF (8u)
+
+/** \brief Length for Ifx_CBS_OEC_Bits.IF_LCK */
+#define IFX_CBS_OEC_IF_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OEC_Bits.IF_LCK */
+#define IFX_CBS_OEC_IF_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OEC_Bits.IF_LCK */
+#define IFX_CBS_OEC_IF_LCK_OFF (17u)
+
+/** \brief Length for Ifx_CBS_OEC_Bits.IF_LCK_P */
+#define IFX_CBS_OEC_IF_LCK_P_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OEC_Bits.IF_LCK_P */
+#define IFX_CBS_OEC_IF_LCK_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OEC_Bits.IF_LCK_P */
+#define IFX_CBS_OEC_IF_LCK_P_OFF (16u)
+
+/** \brief Length for Ifx_CBS_OEC_Bits.OCO */
+#define IFX_CBS_OEC_OCO_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OEC_Bits.OCO */
+#define IFX_CBS_OEC_OCO_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OEC_Bits.OCO */
+#define IFX_CBS_OEC_OCO_OFF (9u)
+
+/** \brief Length for Ifx_CBS_OEC_Bits.PAT */
+#define IFX_CBS_OEC_PAT_LEN (8u)
+
+/** \brief Mask for Ifx_CBS_OEC_Bits.PAT */
+#define IFX_CBS_OEC_PAT_MSK (0xffu)
+
+/** \brief Offset for Ifx_CBS_OEC_Bits.PAT */
+#define IFX_CBS_OEC_PAT_OFF (0u)
+
+/** \brief Length for Ifx_CBS_OIFM_Bits.DAPMODE */
+#define IFX_CBS_OIFM_DAPMODE_LEN (3u)
+
+/** \brief Mask for Ifx_CBS_OIFM_Bits.DAPMODE */
+#define IFX_CBS_OIFM_DAPMODE_MSK (0x7u)
+
+/** \brief Offset for Ifx_CBS_OIFM_Bits.DAPMODE */
+#define IFX_CBS_OIFM_DAPMODE_OFF (0u)
+
+/** \brief Length for Ifx_CBS_OIFM_Bits.DAPRST */
+#define IFX_CBS_OIFM_DAPRST_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OIFM_Bits.DAPRST */
+#define IFX_CBS_OIFM_DAPRST_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OIFM_Bits.DAPRST */
+#define IFX_CBS_OIFM_DAPRST_OFF (3u)
+
+/** \brief Length for Ifx_CBS_OIFM_Bits.F_JTAG */
+#define IFX_CBS_OIFM_F_JTAG_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OIFM_Bits.F_JTAG */
+#define IFX_CBS_OIFM_F_JTAG_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OIFM_Bits.F_JTAG */
+#define IFX_CBS_OIFM_F_JTAG_OFF (8u)
+
+/** \brief Length for Ifx_CBS_OIFM_Bits.N_JTAG */
+#define IFX_CBS_OIFM_N_JTAG_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OIFM_Bits.N_JTAG */
+#define IFX_CBS_OIFM_N_JTAG_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OIFM_Bits.N_JTAG */
+#define IFX_CBS_OIFM_N_JTAG_OFF (9u)
+
+/** \brief Length for Ifx_CBS_OIFM_Bits.PADCTL */
+#define IFX_CBS_OIFM_PADCTL_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_OIFM_Bits.PADCTL */
+#define IFX_CBS_OIFM_PADCTL_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_OIFM_Bits.PADCTL */
+#define IFX_CBS_OIFM_PADCTL_OFF (12u)
+
+/** \brief Length for Ifx_CBS_OSTATE_Bits.AUT_OK */
+#define IFX_CBS_OSTATE_AUT_OK_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OSTATE_Bits.AUT_OK */
+#define IFX_CBS_OSTATE_AUT_OK_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OSTATE_Bits.AUT_OK */
+#define IFX_CBS_OSTATE_AUT_OK_OFF (17u)
+
+/** \brief Length for Ifx_CBS_OSTATE_Bits.EECDIS */
+#define IFX_CBS_OSTATE_EECDIS_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OSTATE_Bits.EECDIS */
+#define IFX_CBS_OSTATE_EECDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OSTATE_Bits.EECDIS */
+#define IFX_CBS_OSTATE_EECDIS_OFF (6u)
+
+/** \brief Length for Ifx_CBS_OSTATE_Bits.EECTRC */
+#define IFX_CBS_OSTATE_EECTRC_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OSTATE_Bits.EECTRC */
+#define IFX_CBS_OSTATE_EECTRC_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OSTATE_Bits.EECTRC */
+#define IFX_CBS_OSTATE_EECTRC_OFF (5u)
+
+/** \brief Length for Ifx_CBS_OSTATE_Bits.ENIDIS */
+#define IFX_CBS_OSTATE_ENIDIS_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OSTATE_Bits.ENIDIS */
+#define IFX_CBS_OSTATE_ENIDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OSTATE_Bits.ENIDIS */
+#define IFX_CBS_OSTATE_ENIDIS_OFF (4u)
+
+/** \brief Length for Ifx_CBS_OSTATE_Bits.HARR */
+#define IFX_CBS_OSTATE_HARR_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OSTATE_Bits.HARR */
+#define IFX_CBS_OSTATE_HARR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OSTATE_Bits.HARR */
+#define IFX_CBS_OSTATE_HARR_OFF (8u)
+
+/** \brief Length for Ifx_CBS_OSTATE_Bits.IF_LCK */
+#define IFX_CBS_OSTATE_IF_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OSTATE_Bits.IF_LCK */
+#define IFX_CBS_OSTATE_IF_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OSTATE_Bits.IF_LCK */
+#define IFX_CBS_OSTATE_IF_LCK_OFF (16u)
+
+/** \brief Length for Ifx_CBS_OSTATE_Bits.OC0 */
+#define IFX_CBS_OSTATE_OC0_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OSTATE_Bits.OC0 */
+#define IFX_CBS_OSTATE_OC0_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OSTATE_Bits.OC0 */
+#define IFX_CBS_OSTATE_OC0_OFF (1u)
+
+/** \brief Length for Ifx_CBS_OSTATE_Bits.OC1 */
+#define IFX_CBS_OSTATE_OC1_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OSTATE_Bits.OC1 */
+#define IFX_CBS_OSTATE_OC1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OSTATE_Bits.OC1 */
+#define IFX_CBS_OSTATE_OC1_OFF (2u)
+
+/** \brief Length for Ifx_CBS_OSTATE_Bits.OC2 */
+#define IFX_CBS_OSTATE_OC2_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OSTATE_Bits.OC2 */
+#define IFX_CBS_OSTATE_OC2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OSTATE_Bits.OC2 */
+#define IFX_CBS_OSTATE_OC2_OFF (3u)
+
+/** \brief Length for Ifx_CBS_OSTATE_Bits.OCO */
+#define IFX_CBS_OSTATE_OCO_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OSTATE_Bits.OCO */
+#define IFX_CBS_OSTATE_OCO_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OSTATE_Bits.OCO */
+#define IFX_CBS_OSTATE_OCO_OFF (19u)
+
+/** \brief Length for Ifx_CBS_OSTATE_Bits.OEN */
+#define IFX_CBS_OSTATE_OEN_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OSTATE_Bits.OEN */
+#define IFX_CBS_OSTATE_OEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OSTATE_Bits.OEN */
+#define IFX_CBS_OSTATE_OEN_OFF (0u)
+
+/** \brief Length for Ifx_CBS_OSTATE_Bits.OJC1 */
+#define IFX_CBS_OSTATE_OJC1_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OSTATE_Bits.OJC1 */
+#define IFX_CBS_OSTATE_OJC1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OSTATE_Bits.OJC1 */
+#define IFX_CBS_OSTATE_OJC1_OFF (9u)
+
+/** \brief Length for Ifx_CBS_OSTATE_Bits.OJC2 */
+#define IFX_CBS_OSTATE_OJC2_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OSTATE_Bits.OJC2 */
+#define IFX_CBS_OSTATE_OJC2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OSTATE_Bits.OJC2 */
+#define IFX_CBS_OSTATE_OJC2_OFF (10u)
+
+/** \brief Length for Ifx_CBS_OSTATE_Bits.OJC3 */
+#define IFX_CBS_OSTATE_OJC3_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OSTATE_Bits.OJC3 */
+#define IFX_CBS_OSTATE_OJC3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OSTATE_Bits.OJC3 */
+#define IFX_CBS_OSTATE_OJC3_OFF (11u)
+
+/** \brief Length for Ifx_CBS_OSTATE_Bits.OJC6 */
+#define IFX_CBS_OSTATE_OJC6_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OSTATE_Bits.OJC6 */
+#define IFX_CBS_OSTATE_OJC6_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OSTATE_Bits.OJC6 */
+#define IFX_CBS_OSTATE_OJC6_OFF (14u)
+
+/** \brief Length for Ifx_CBS_OSTATE_Bits.RSTCL0 */
+#define IFX_CBS_OSTATE_RSTCL0_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OSTATE_Bits.RSTCL0 */
+#define IFX_CBS_OSTATE_RSTCL0_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OSTATE_Bits.RSTCL0 */
+#define IFX_CBS_OSTATE_RSTCL0_OFF (12u)
+
+/** \brief Length for Ifx_CBS_OSTATE_Bits.RSTCL1 */
+#define IFX_CBS_OSTATE_RSTCL1_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OSTATE_Bits.RSTCL1 */
+#define IFX_CBS_OSTATE_RSTCL1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OSTATE_Bits.RSTCL1 */
+#define IFX_CBS_OSTATE_RSTCL1_OFF (13u)
+
+/** \brief Length for Ifx_CBS_OSTATE_Bits.RSTCL3 */
+#define IFX_CBS_OSTATE_RSTCL3_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OSTATE_Bits.RSTCL3 */
+#define IFX_CBS_OSTATE_RSTCL3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OSTATE_Bits.RSTCL3 */
+#define IFX_CBS_OSTATE_RSTCL3_OFF (15u)
+
+/** \brief Length for Ifx_CBS_OSTATE_Bits.STABLE */
+#define IFX_CBS_OSTATE_STABLE_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OSTATE_Bits.STABLE */
+#define IFX_CBS_OSTATE_STABLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OSTATE_Bits.STABLE */
+#define IFX_CBS_OSTATE_STABLE_OFF (18u)
+
+/** \brief Length for Ifx_CBS_OSTATE_Bits.WDTSUS */
+#define IFX_CBS_OSTATE_WDTSUS_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_OSTATE_Bits.WDTSUS */
+#define IFX_CBS_OSTATE_WDTSUS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_OSTATE_Bits.WDTSUS */
+#define IFX_CBS_OSTATE_WDTSUS_OFF (7u)
+
+/** \brief Length for Ifx_CBS_TCCB_Bits.C0 */
+#define IFX_CBS_TCCB_C0_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TCCB_Bits.C0 */
+#define IFX_CBS_TCCB_C0_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TCCB_Bits.C0 */
+#define IFX_CBS_TCCB_C0_OFF (0u)
+
+/** \brief Length for Ifx_CBS_TCCB_Bits.C1 */
+#define IFX_CBS_TCCB_C1_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TCCB_Bits.C1 */
+#define IFX_CBS_TCCB_C1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TCCB_Bits.C1 */
+#define IFX_CBS_TCCB_C1_OFF (1u)
+
+/** \brief Length for Ifx_CBS_TCCB_Bits.C2 */
+#define IFX_CBS_TCCB_C2_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TCCB_Bits.C2 */
+#define IFX_CBS_TCCB_C2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TCCB_Bits.C2 */
+#define IFX_CBS_TCCB_C2_OFF (2u)
+
+/** \brief Length for Ifx_CBS_TCCB_Bits.HSM */
+#define IFX_CBS_TCCB_HSM_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TCCB_Bits.HSM */
+#define IFX_CBS_TCCB_HSM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TCCB_Bits.HSM */
+#define IFX_CBS_TCCB_HSM_OFF (31u)
+
+/** \brief Length for Ifx_CBS_TCCH_Bits.C0 */
+#define IFX_CBS_TCCH_C0_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TCCH_Bits.C0 */
+#define IFX_CBS_TCCH_C0_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TCCH_Bits.C0 */
+#define IFX_CBS_TCCH_C0_OFF (0u)
+
+/** \brief Length for Ifx_CBS_TCCH_Bits.C1 */
+#define IFX_CBS_TCCH_C1_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TCCH_Bits.C1 */
+#define IFX_CBS_TCCH_C1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TCCH_Bits.C1 */
+#define IFX_CBS_TCCH_C1_OFF (1u)
+
+/** \brief Length for Ifx_CBS_TCCH_Bits.C2 */
+#define IFX_CBS_TCCH_C2_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TCCH_Bits.C2 */
+#define IFX_CBS_TCCH_C2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TCCH_Bits.C2 */
+#define IFX_CBS_TCCH_C2_OFF (2u)
+
+/** \brief Length for Ifx_CBS_TCCH_Bits.HSM */
+#define IFX_CBS_TCCH_HSM_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TCCH_Bits.HSM */
+#define IFX_CBS_TCCH_HSM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TCCH_Bits.HSM */
+#define IFX_CBS_TCCH_HSM_OFF (31u)
+
+/** \brief Length for Ifx_CBS_TCIP_Bits.P0 */
+#define IFX_CBS_TCIP_P0_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TCIP_Bits.P0 */
+#define IFX_CBS_TCIP_P0_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TCIP_Bits.P0 */
+#define IFX_CBS_TCIP_P0_OFF (0u)
+
+/** \brief Length for Ifx_CBS_TCIP_Bits.P1 */
+#define IFX_CBS_TCIP_P1_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TCIP_Bits.P1 */
+#define IFX_CBS_TCIP_P1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TCIP_Bits.P1 */
+#define IFX_CBS_TCIP_P1_OFF (1u)
+
+/** \brief Length for Ifx_CBS_TCIP_Bits.P2 */
+#define IFX_CBS_TCIP_P2_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TCIP_Bits.P2 */
+#define IFX_CBS_TCIP_P2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TCIP_Bits.P2 */
+#define IFX_CBS_TCIP_P2_OFF (2u)
+
+/** \brief Length for Ifx_CBS_TCIP_Bits.P3 */
+#define IFX_CBS_TCIP_P3_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TCIP_Bits.P3 */
+#define IFX_CBS_TCIP_P3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TCIP_Bits.P3 */
+#define IFX_CBS_TCIP_P3_OFF (3u)
+
+/** \brief Length for Ifx_CBS_TCIP_Bits.P4 */
+#define IFX_CBS_TCIP_P4_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TCIP_Bits.P4 */
+#define IFX_CBS_TCIP_P4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TCIP_Bits.P4 */
+#define IFX_CBS_TCIP_P4_OFF (4u)
+
+/** \brief Length for Ifx_CBS_TCIP_Bits.P5 */
+#define IFX_CBS_TCIP_P5_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TCIP_Bits.P5 */
+#define IFX_CBS_TCIP_P5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TCIP_Bits.P5 */
+#define IFX_CBS_TCIP_P5_OFF (5u)
+
+/** \brief Length for Ifx_CBS_TCIP_Bits.P6 */
+#define IFX_CBS_TCIP_P6_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TCIP_Bits.P6 */
+#define IFX_CBS_TCIP_P6_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TCIP_Bits.P6 */
+#define IFX_CBS_TCIP_P6_OFF (6u)
+
+/** \brief Length for Ifx_CBS_TCIP_Bits.P7 */
+#define IFX_CBS_TCIP_P7_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TCIP_Bits.P7 */
+#define IFX_CBS_TCIP_P7_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TCIP_Bits.P7 */
+#define IFX_CBS_TCIP_P7_OFF (7u)
+
+/** \brief Length for Ifx_CBS_TCM_Bits.BRK */
+#define IFX_CBS_TCM_BRK_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TCM_Bits.BRK */
+#define IFX_CBS_TCM_BRK_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TCM_Bits.BRK */
+#define IFX_CBS_TCM_BRK_OFF (0u)
+
+/** \brief Length for Ifx_CBS_TCM_Bits.SUS */
+#define IFX_CBS_TCM_SUS_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TCM_Bits.SUS */
+#define IFX_CBS_TCM_SUS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TCM_Bits.SUS */
+#define IFX_CBS_TCM_SUS_OFF (1u)
+
+/** \brief Length for Ifx_CBS_TCM_Bits.T0 */
+#define IFX_CBS_TCM_T0_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TCM_Bits.T0 */
+#define IFX_CBS_TCM_T0_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TCM_Bits.T0 */
+#define IFX_CBS_TCM_T0_OFF (8u)
+
+/** \brief Length for Ifx_CBS_TCM_Bits.T1 */
+#define IFX_CBS_TCM_T1_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TCM_Bits.T1 */
+#define IFX_CBS_TCM_T1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TCM_Bits.T1 */
+#define IFX_CBS_TCM_T1_OFF (9u)
+
+/** \brief Length for Ifx_CBS_TCM_Bits.T2 */
+#define IFX_CBS_TCM_T2_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TCM_Bits.T2 */
+#define IFX_CBS_TCM_T2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TCM_Bits.T2 */
+#define IFX_CBS_TCM_T2_OFF (10u)
+
+/** \brief Length for Ifx_CBS_TCM_Bits.T3 */
+#define IFX_CBS_TCM_T3_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TCM_Bits.T3 */
+#define IFX_CBS_TCM_T3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TCM_Bits.T3 */
+#define IFX_CBS_TCM_T3_OFF (11u)
+
+/** \brief Length for Ifx_CBS_TCTGB_Bits.OTGB0 */
+#define IFX_CBS_TCTGB_OTGB0_LEN (16u)
+
+/** \brief Mask for Ifx_CBS_TCTGB_Bits.OTGB0 */
+#define IFX_CBS_TCTGB_OTGB0_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CBS_TCTGB_Bits.OTGB0 */
+#define IFX_CBS_TCTGB_OTGB0_OFF (0u)
+
+/** \brief Length for Ifx_CBS_TCTGB_Bits.OTGB1 */
+#define IFX_CBS_TCTGB_OTGB1_LEN (16u)
+
+/** \brief Mask for Ifx_CBS_TCTGB_Bits.OTGB1 */
+#define IFX_CBS_TCTGB_OTGB1_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CBS_TCTGB_Bits.OTGB1 */
+#define IFX_CBS_TCTGB_OTGB1_OFF (16u)
+
+/** \brief Length for Ifx_CBS_TCTL_Bits.TL1 */
+#define IFX_CBS_TCTL_TL1_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TCTL_Bits.TL1 */
+#define IFX_CBS_TCTL_TL1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TCTL_Bits.TL1 */
+#define IFX_CBS_TCTL_TL1_OFF (1u)
+
+/** \brief Length for Ifx_CBS_TCTL_Bits.TL2 */
+#define IFX_CBS_TCTL_TL2_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TCTL_Bits.TL2 */
+#define IFX_CBS_TCTL_TL2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TCTL_Bits.TL2 */
+#define IFX_CBS_TCTL_TL2_OFF (2u)
+
+/** \brief Length for Ifx_CBS_TCTL_Bits.TL3 */
+#define IFX_CBS_TCTL_TL3_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TCTL_Bits.TL3 */
+#define IFX_CBS_TCTL_TL3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TCTL_Bits.TL3 */
+#define IFX_CBS_TCTL_TL3_OFF (3u)
+
+/** \brief Length for Ifx_CBS_TCTL_Bits.TL4 */
+#define IFX_CBS_TCTL_TL4_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TCTL_Bits.TL4 */
+#define IFX_CBS_TCTL_TL4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TCTL_Bits.TL4 */
+#define IFX_CBS_TCTL_TL4_OFF (4u)
+
+/** \brief Length for Ifx_CBS_TCTL_Bits.TL5 */
+#define IFX_CBS_TCTL_TL5_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TCTL_Bits.TL5 */
+#define IFX_CBS_TCTL_TL5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TCTL_Bits.TL5 */
+#define IFX_CBS_TCTL_TL5_OFF (5u)
+
+/** \brief Length for Ifx_CBS_TCTL_Bits.TL6 */
+#define IFX_CBS_TCTL_TL6_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TCTL_Bits.TL6 */
+#define IFX_CBS_TCTL_TL6_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TCTL_Bits.TL6 */
+#define IFX_CBS_TCTL_TL6_OFF (6u)
+
+/** \brief Length for Ifx_CBS_TCTL_Bits.TL7 */
+#define IFX_CBS_TCTL_TL7_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TCTL_Bits.TL7 */
+#define IFX_CBS_TCTL_TL7_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TCTL_Bits.TL7 */
+#define IFX_CBS_TCTL_TL7_OFF (7u)
+
+/** \brief Length for Ifx_CBS_TIPR_Bits.PIN0 */
+#define IFX_CBS_TIPR_PIN0_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TIPR_Bits.PIN0 */
+#define IFX_CBS_TIPR_PIN0_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TIPR_Bits.PIN0 */
+#define IFX_CBS_TIPR_PIN0_OFF (0u)
+
+/** \brief Length for Ifx_CBS_TIPR_Bits.PIN1 */
+#define IFX_CBS_TIPR_PIN1_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TIPR_Bits.PIN1 */
+#define IFX_CBS_TIPR_PIN1_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TIPR_Bits.PIN1 */
+#define IFX_CBS_TIPR_PIN1_OFF (4u)
+
+/** \brief Length for Ifx_CBS_TIPR_Bits.PIN2 */
+#define IFX_CBS_TIPR_PIN2_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TIPR_Bits.PIN2 */
+#define IFX_CBS_TIPR_PIN2_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TIPR_Bits.PIN2 */
+#define IFX_CBS_TIPR_PIN2_OFF (8u)
+
+/** \brief Length for Ifx_CBS_TIPR_Bits.PIN3 */
+#define IFX_CBS_TIPR_PIN3_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TIPR_Bits.PIN3 */
+#define IFX_CBS_TIPR_PIN3_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TIPR_Bits.PIN3 */
+#define IFX_CBS_TIPR_PIN3_OFF (12u)
+
+/** \brief Length for Ifx_CBS_TIPR_Bits.PIN4 */
+#define IFX_CBS_TIPR_PIN4_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TIPR_Bits.PIN4 */
+#define IFX_CBS_TIPR_PIN4_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TIPR_Bits.PIN4 */
+#define IFX_CBS_TIPR_PIN4_OFF (16u)
+
+/** \brief Length for Ifx_CBS_TIPR_Bits.PIN5 */
+#define IFX_CBS_TIPR_PIN5_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TIPR_Bits.PIN5 */
+#define IFX_CBS_TIPR_PIN5_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TIPR_Bits.PIN5 */
+#define IFX_CBS_TIPR_PIN5_OFF (20u)
+
+/** \brief Length for Ifx_CBS_TIPR_Bits.PIN6 */
+#define IFX_CBS_TIPR_PIN6_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TIPR_Bits.PIN6 */
+#define IFX_CBS_TIPR_PIN6_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TIPR_Bits.PIN6 */
+#define IFX_CBS_TIPR_PIN6_OFF (24u)
+
+/** \brief Length for Ifx_CBS_TIPR_Bits.PIN7 */
+#define IFX_CBS_TIPR_PIN7_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TIPR_Bits.PIN7 */
+#define IFX_CBS_TIPR_PIN7_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TIPR_Bits.PIN7 */
+#define IFX_CBS_TIPR_PIN7_OFF (28u)
+
+/** \brief Length for Ifx_CBS_TL1ST_Bits.C0 */
+#define IFX_CBS_TL1ST_C0_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TL1ST_Bits.C0 */
+#define IFX_CBS_TL1ST_C0_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TL1ST_Bits.C0 */
+#define IFX_CBS_TL1ST_C0_OFF (0u)
+
+/** \brief Length for Ifx_CBS_TL1ST_Bits.C1 */
+#define IFX_CBS_TL1ST_C1_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TL1ST_Bits.C1 */
+#define IFX_CBS_TL1ST_C1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TL1ST_Bits.C1 */
+#define IFX_CBS_TL1ST_C1_OFF (1u)
+
+/** \brief Length for Ifx_CBS_TL1ST_Bits.C2 */
+#define IFX_CBS_TL1ST_C2_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TL1ST_Bits.C2 */
+#define IFX_CBS_TL1ST_C2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TL1ST_Bits.C2 */
+#define IFX_CBS_TL1ST_C2_OFF (2u)
+
+/** \brief Length for Ifx_CBS_TL1ST_Bits.DMA */
+#define IFX_CBS_TL1ST_DMA_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TL1ST_Bits.DMA */
+#define IFX_CBS_TL1ST_DMA_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TL1ST_Bits.DMA */
+#define IFX_CBS_TL1ST_DMA_OFF (29u)
+
+/** \brief Length for Ifx_CBS_TL1ST_Bits.HSM */
+#define IFX_CBS_TL1ST_HSM_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TL1ST_Bits.HSM */
+#define IFX_CBS_TL1ST_HSM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TL1ST_Bits.HSM */
+#define IFX_CBS_TL1ST_HSM_OFF (31u)
+
+/** \brief Length for Ifx_CBS_TL1ST_Bits.HSS */
+#define IFX_CBS_TL1ST_HSS_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TL1ST_Bits.HSS */
+#define IFX_CBS_TL1ST_HSS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TL1ST_Bits.HSS */
+#define IFX_CBS_TL1ST_HSS_OFF (28u)
+
+/** \brief Length for Ifx_CBS_TLC_Bits.TLSP1 */
+#define IFX_CBS_TLC_TLSP1_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TLC_Bits.TLSP1 */
+#define IFX_CBS_TLC_TLSP1_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TLC_Bits.TLSP1 */
+#define IFX_CBS_TLC_TLSP1_OFF (4u)
+
+/** \brief Length for Ifx_CBS_TLC_Bits.TLSP2 */
+#define IFX_CBS_TLC_TLSP2_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TLC_Bits.TLSP2 */
+#define IFX_CBS_TLC_TLSP2_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TLC_Bits.TLSP2 */
+#define IFX_CBS_TLC_TLSP2_OFF (8u)
+
+/** \brief Length for Ifx_CBS_TLC_Bits.TLSP3 */
+#define IFX_CBS_TLC_TLSP3_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TLC_Bits.TLSP3 */
+#define IFX_CBS_TLC_TLSP3_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TLC_Bits.TLSP3 */
+#define IFX_CBS_TLC_TLSP3_OFF (12u)
+
+/** \brief Length for Ifx_CBS_TLC_Bits.TLSP4 */
+#define IFX_CBS_TLC_TLSP4_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TLC_Bits.TLSP4 */
+#define IFX_CBS_TLC_TLSP4_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TLC_Bits.TLSP4 */
+#define IFX_CBS_TLC_TLSP4_OFF (16u)
+
+/** \brief Length for Ifx_CBS_TLC_Bits.TLSP5 */
+#define IFX_CBS_TLC_TLSP5_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TLC_Bits.TLSP5 */
+#define IFX_CBS_TLC_TLSP5_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TLC_Bits.TLSP5 */
+#define IFX_CBS_TLC_TLSP5_OFF (20u)
+
+/** \brief Length for Ifx_CBS_TLC_Bits.TLSP6 */
+#define IFX_CBS_TLC_TLSP6_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TLC_Bits.TLSP6 */
+#define IFX_CBS_TLC_TLSP6_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TLC_Bits.TLSP6 */
+#define IFX_CBS_TLC_TLSP6_OFF (24u)
+
+/** \brief Length for Ifx_CBS_TLC_Bits.TLSP7 */
+#define IFX_CBS_TLC_TLSP7_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TLC_Bits.TLSP7 */
+#define IFX_CBS_TLC_TLSP7_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TLC_Bits.TLSP7 */
+#define IFX_CBS_TLC_TLSP7_OFF (28u)
+
+/** \brief Length for Ifx_CBS_TLCC_Bits.CLR */
+#define IFX_CBS_TLCC_CLR_LEN (2u)
+
+/** \brief Mask for Ifx_CBS_TLCC_Bits.CLR */
+#define IFX_CBS_TLCC_CLR_MSK (0x3u)
+
+/** \brief Offset for Ifx_CBS_TLCC_Bits.CLR */
+#define IFX_CBS_TLCC_CLR_OFF (8u)
+
+/** \brief Length for Ifx_CBS_TLCC_Bits.LE */
+#define IFX_CBS_TLCC_LE_LEN (3u)
+
+/** \brief Mask for Ifx_CBS_TLCC_Bits.LE */
+#define IFX_CBS_TLCC_LE_MSK (0x7u)
+
+/** \brief Offset for Ifx_CBS_TLCC_Bits.LE */
+#define IFX_CBS_TLCC_LE_OFF (4u)
+
+/** \brief Length for Ifx_CBS_TLCC_Bits.STOP */
+#define IFX_CBS_TLCC_STOP_LEN (2u)
+
+/** \brief Mask for Ifx_CBS_TLCC_Bits.STOP */
+#define IFX_CBS_TLCC_STOP_MSK (0x3u)
+
+/** \brief Offset for Ifx_CBS_TLCC_Bits.STOP */
+#define IFX_CBS_TLCC_STOP_OFF (12u)
+
+/** \brief Length for Ifx_CBS_TLCC_Bits.TGL */
+#define IFX_CBS_TLCC_TGL_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TLCC_Bits.TGL */
+#define IFX_CBS_TLCC_TGL_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TLCC_Bits.TGL */
+#define IFX_CBS_TLCC_TGL_OFF (0u)
+
+/** \brief Length for Ifx_CBS_TLCHE_Bits.TL1 */
+#define IFX_CBS_TLCHE_TL1_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TLCHE_Bits.TL1 */
+#define IFX_CBS_TLCHE_TL1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TLCHE_Bits.TL1 */
+#define IFX_CBS_TLCHE_TL1_OFF (1u)
+
+/** \brief Length for Ifx_CBS_TLCHE_Bits.TL2 */
+#define IFX_CBS_TLCHE_TL2_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TLCHE_Bits.TL2 */
+#define IFX_CBS_TLCHE_TL2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TLCHE_Bits.TL2 */
+#define IFX_CBS_TLCHE_TL2_OFF (2u)
+
+/** \brief Length for Ifx_CBS_TLCHE_Bits.TL3 */
+#define IFX_CBS_TLCHE_TL3_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TLCHE_Bits.TL3 */
+#define IFX_CBS_TLCHE_TL3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TLCHE_Bits.TL3 */
+#define IFX_CBS_TLCHE_TL3_OFF (3u)
+
+/** \brief Length for Ifx_CBS_TLCHS_Bits.TL1 */
+#define IFX_CBS_TLCHS_TL1_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TLCHS_Bits.TL1 */
+#define IFX_CBS_TLCHS_TL1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TLCHS_Bits.TL1 */
+#define IFX_CBS_TLCHS_TL1_OFF (1u)
+
+/** \brief Length for Ifx_CBS_TLCHS_Bits.TL2 */
+#define IFX_CBS_TLCHS_TL2_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TLCHS_Bits.TL2 */
+#define IFX_CBS_TLCHS_TL2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TLCHS_Bits.TL2 */
+#define IFX_CBS_TLCHS_TL2_OFF (2u)
+
+/** \brief Length for Ifx_CBS_TLCHS_Bits.TL3 */
+#define IFX_CBS_TLCHS_TL3_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TLCHS_Bits.TL3 */
+#define IFX_CBS_TLCHS_TL3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TLCHS_Bits.TL3 */
+#define IFX_CBS_TLCHS_TL3_OFF (3u)
+
+/** \brief Length for Ifx_CBS_TLCV_Bits.CV */
+#define IFX_CBS_TLCV_CV_LEN (31u)
+
+/** \brief Mask for Ifx_CBS_TLCV_Bits.CV */
+#define IFX_CBS_TLCV_CV_MSK (0x7fffffffu)
+
+/** \brief Offset for Ifx_CBS_TLCV_Bits.CV */
+#define IFX_CBS_TLCV_CV_OFF (0u)
+
+/** \brief Length for Ifx_CBS_TLCV_Bits.SO */
+#define IFX_CBS_TLCV_SO_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TLCV_Bits.SO */
+#define IFX_CBS_TLCV_SO_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TLCV_Bits.SO */
+#define IFX_CBS_TLCV_SO_OFF (31u)
+
+/** \brief Length for Ifx_CBS_TLS_Bits.TL1 */
+#define IFX_CBS_TLS_TL1_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TLS_Bits.TL1 */
+#define IFX_CBS_TLS_TL1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TLS_Bits.TL1 */
+#define IFX_CBS_TLS_TL1_OFF (1u)
+
+/** \brief Length for Ifx_CBS_TLS_Bits.TL2 */
+#define IFX_CBS_TLS_TL2_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TLS_Bits.TL2 */
+#define IFX_CBS_TLS_TL2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TLS_Bits.TL2 */
+#define IFX_CBS_TLS_TL2_OFF (2u)
+
+/** \brief Length for Ifx_CBS_TLS_Bits.TL3 */
+#define IFX_CBS_TLS_TL3_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TLS_Bits.TL3 */
+#define IFX_CBS_TLS_TL3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TLS_Bits.TL3 */
+#define IFX_CBS_TLS_TL3_OFF (3u)
+
+/** \brief Length for Ifx_CBS_TLS_Bits.TL4 */
+#define IFX_CBS_TLS_TL4_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TLS_Bits.TL4 */
+#define IFX_CBS_TLS_TL4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TLS_Bits.TL4 */
+#define IFX_CBS_TLS_TL4_OFF (4u)
+
+/** \brief Length for Ifx_CBS_TLS_Bits.TL5 */
+#define IFX_CBS_TLS_TL5_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TLS_Bits.TL5 */
+#define IFX_CBS_TLS_TL5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TLS_Bits.TL5 */
+#define IFX_CBS_TLS_TL5_OFF (5u)
+
+/** \brief Length for Ifx_CBS_TLS_Bits.TL6 */
+#define IFX_CBS_TLS_TL6_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TLS_Bits.TL6 */
+#define IFX_CBS_TLS_TL6_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TLS_Bits.TL6 */
+#define IFX_CBS_TLS_TL6_OFF (6u)
+
+/** \brief Length for Ifx_CBS_TLS_Bits.TL7 */
+#define IFX_CBS_TLS_TL7_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TLS_Bits.TL7 */
+#define IFX_CBS_TLS_TL7_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TLS_Bits.TL7 */
+#define IFX_CBS_TLS_TL7_OFF (7u)
+
+/** \brief Length for Ifx_CBS_TLT_Bits.TGL */
+#define IFX_CBS_TLT_TGL_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TLT_Bits.TGL */
+#define IFX_CBS_TLT_TGL_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TLT_Bits.TGL */
+#define IFX_CBS_TLT_TGL_OFF (0u)
+
+/** \brief Length for Ifx_CBS_TLT_Bits.TIM */
+#define IFX_CBS_TLT_TIM_LEN (16u)
+
+/** \brief Mask for Ifx_CBS_TLT_Bits.TIM */
+#define IFX_CBS_TLT_TIM_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CBS_TLT_Bits.TIM */
+#define IFX_CBS_TLT_TIM_OFF (16u)
+
+/** \brief Length for Ifx_CBS_TLT_Bits.VTZ */
+#define IFX_CBS_TLT_VTZ_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TLT_Bits.VTZ */
+#define IFX_CBS_TLT_VTZ_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TLT_Bits.VTZ */
+#define IFX_CBS_TLT_VTZ_OFF (4u)
+
+/** \brief Length for Ifx_CBS_TLTTH_Bits.TL1 */
+#define IFX_CBS_TLTTH_TL1_LEN (2u)
+
+/** \brief Mask for Ifx_CBS_TLTTH_Bits.TL1 */
+#define IFX_CBS_TLTTH_TL1_MSK (0x3u)
+
+/** \brief Offset for Ifx_CBS_TLTTH_Bits.TL1 */
+#define IFX_CBS_TLTTH_TL1_OFF (2u)
+
+/** \brief Length for Ifx_CBS_TLTTH_Bits.TL2 */
+#define IFX_CBS_TLTTH_TL2_LEN (2u)
+
+/** \brief Mask for Ifx_CBS_TLTTH_Bits.TL2 */
+#define IFX_CBS_TLTTH_TL2_MSK (0x3u)
+
+/** \brief Offset for Ifx_CBS_TLTTH_Bits.TL2 */
+#define IFX_CBS_TLTTH_TL2_OFF (4u)
+
+/** \brief Length for Ifx_CBS_TLTTH_Bits.TL3 */
+#define IFX_CBS_TLTTH_TL3_LEN (2u)
+
+/** \brief Mask for Ifx_CBS_TLTTH_Bits.TL3 */
+#define IFX_CBS_TLTTH_TL3_MSK (0x3u)
+
+/** \brief Offset for Ifx_CBS_TLTTH_Bits.TL3 */
+#define IFX_CBS_TLTTH_TL3_OFF (6u)
+
+/** \brief Length for Ifx_CBS_TLTTH_Bits.TL4 */
+#define IFX_CBS_TLTTH_TL4_LEN (2u)
+
+/** \brief Mask for Ifx_CBS_TLTTH_Bits.TL4 */
+#define IFX_CBS_TLTTH_TL4_MSK (0x3u)
+
+/** \brief Offset for Ifx_CBS_TLTTH_Bits.TL4 */
+#define IFX_CBS_TLTTH_TL4_OFF (8u)
+
+/** \brief Length for Ifx_CBS_TLTTH_Bits.TL5 */
+#define IFX_CBS_TLTTH_TL5_LEN (2u)
+
+/** \brief Mask for Ifx_CBS_TLTTH_Bits.TL5 */
+#define IFX_CBS_TLTTH_TL5_MSK (0x3u)
+
+/** \brief Offset for Ifx_CBS_TLTTH_Bits.TL5 */
+#define IFX_CBS_TLTTH_TL5_OFF (10u)
+
+/** \brief Length for Ifx_CBS_TLTTH_Bits.TL6 */
+#define IFX_CBS_TLTTH_TL6_LEN (2u)
+
+/** \brief Mask for Ifx_CBS_TLTTH_Bits.TL6 */
+#define IFX_CBS_TLTTH_TL6_MSK (0x3u)
+
+/** \brief Offset for Ifx_CBS_TLTTH_Bits.TL6 */
+#define IFX_CBS_TLTTH_TL6_OFF (12u)
+
+/** \brief Length for Ifx_CBS_TLTTH_Bits.TL7 */
+#define IFX_CBS_TLTTH_TL7_LEN (2u)
+
+/** \brief Mask for Ifx_CBS_TLTTH_Bits.TL7 */
+#define IFX_CBS_TLTTH_TL7_MSK (0x3u)
+
+/** \brief Offset for Ifx_CBS_TLTTH_Bits.TL7 */
+#define IFX_CBS_TLTTH_TL7_OFF (14u)
+
+/** \brief Length for Ifx_CBS_TOPPS_Bits.PIN0 */
+#define IFX_CBS_TOPPS_PIN0_LEN (2u)
+
+/** \brief Mask for Ifx_CBS_TOPPS_Bits.PIN0 */
+#define IFX_CBS_TOPPS_PIN0_MSK (0x3u)
+
+/** \brief Offset for Ifx_CBS_TOPPS_Bits.PIN0 */
+#define IFX_CBS_TOPPS_PIN0_OFF (0u)
+
+/** \brief Length for Ifx_CBS_TOPPS_Bits.PIN1 */
+#define IFX_CBS_TOPPS_PIN1_LEN (2u)
+
+/** \brief Mask for Ifx_CBS_TOPPS_Bits.PIN1 */
+#define IFX_CBS_TOPPS_PIN1_MSK (0x3u)
+
+/** \brief Offset for Ifx_CBS_TOPPS_Bits.PIN1 */
+#define IFX_CBS_TOPPS_PIN1_OFF (2u)
+
+/** \brief Length for Ifx_CBS_TOPPS_Bits.PIN2 */
+#define IFX_CBS_TOPPS_PIN2_LEN (2u)
+
+/** \brief Mask for Ifx_CBS_TOPPS_Bits.PIN2 */
+#define IFX_CBS_TOPPS_PIN2_MSK (0x3u)
+
+/** \brief Offset for Ifx_CBS_TOPPS_Bits.PIN2 */
+#define IFX_CBS_TOPPS_PIN2_OFF (4u)
+
+/** \brief Length for Ifx_CBS_TOPPS_Bits.PIN3 */
+#define IFX_CBS_TOPPS_PIN3_LEN (2u)
+
+/** \brief Mask for Ifx_CBS_TOPPS_Bits.PIN3 */
+#define IFX_CBS_TOPPS_PIN3_MSK (0x3u)
+
+/** \brief Offset for Ifx_CBS_TOPPS_Bits.PIN3 */
+#define IFX_CBS_TOPPS_PIN3_OFF (6u)
+
+/** \brief Length for Ifx_CBS_TOPPS_Bits.PIN4 */
+#define IFX_CBS_TOPPS_PIN4_LEN (2u)
+
+/** \brief Mask for Ifx_CBS_TOPPS_Bits.PIN4 */
+#define IFX_CBS_TOPPS_PIN4_MSK (0x3u)
+
+/** \brief Offset for Ifx_CBS_TOPPS_Bits.PIN4 */
+#define IFX_CBS_TOPPS_PIN4_OFF (8u)
+
+/** \brief Length for Ifx_CBS_TOPPS_Bits.PIN5 */
+#define IFX_CBS_TOPPS_PIN5_LEN (2u)
+
+/** \brief Mask for Ifx_CBS_TOPPS_Bits.PIN5 */
+#define IFX_CBS_TOPPS_PIN5_MSK (0x3u)
+
+/** \brief Offset for Ifx_CBS_TOPPS_Bits.PIN5 */
+#define IFX_CBS_TOPPS_PIN5_OFF (10u)
+
+/** \brief Length for Ifx_CBS_TOPPS_Bits.PIN6 */
+#define IFX_CBS_TOPPS_PIN6_LEN (2u)
+
+/** \brief Mask for Ifx_CBS_TOPPS_Bits.PIN6 */
+#define IFX_CBS_TOPPS_PIN6_MSK (0x3u)
+
+/** \brief Offset for Ifx_CBS_TOPPS_Bits.PIN6 */
+#define IFX_CBS_TOPPS_PIN6_OFF (12u)
+
+/** \brief Length for Ifx_CBS_TOPPS_Bits.PIN7 */
+#define IFX_CBS_TOPPS_PIN7_LEN (2u)
+
+/** \brief Mask for Ifx_CBS_TOPPS_Bits.PIN7 */
+#define IFX_CBS_TOPPS_PIN7_MSK (0x3u)
+
+/** \brief Offset for Ifx_CBS_TOPPS_Bits.PIN7 */
+#define IFX_CBS_TOPPS_PIN7_OFF (14u)
+
+/** \brief Length for Ifx_CBS_TOPR_Bits.PIN0 */
+#define IFX_CBS_TOPR_PIN0_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TOPR_Bits.PIN0 */
+#define IFX_CBS_TOPR_PIN0_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TOPR_Bits.PIN0 */
+#define IFX_CBS_TOPR_PIN0_OFF (0u)
+
+/** \brief Length for Ifx_CBS_TOPR_Bits.PIN1 */
+#define IFX_CBS_TOPR_PIN1_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TOPR_Bits.PIN1 */
+#define IFX_CBS_TOPR_PIN1_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TOPR_Bits.PIN1 */
+#define IFX_CBS_TOPR_PIN1_OFF (4u)
+
+/** \brief Length for Ifx_CBS_TOPR_Bits.PIN2 */
+#define IFX_CBS_TOPR_PIN2_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TOPR_Bits.PIN2 */
+#define IFX_CBS_TOPR_PIN2_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TOPR_Bits.PIN2 */
+#define IFX_CBS_TOPR_PIN2_OFF (8u)
+
+/** \brief Length for Ifx_CBS_TOPR_Bits.PIN3 */
+#define IFX_CBS_TOPR_PIN3_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TOPR_Bits.PIN3 */
+#define IFX_CBS_TOPR_PIN3_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TOPR_Bits.PIN3 */
+#define IFX_CBS_TOPR_PIN3_OFF (12u)
+
+/** \brief Length for Ifx_CBS_TOPR_Bits.PIN4 */
+#define IFX_CBS_TOPR_PIN4_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TOPR_Bits.PIN4 */
+#define IFX_CBS_TOPR_PIN4_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TOPR_Bits.PIN4 */
+#define IFX_CBS_TOPR_PIN4_OFF (16u)
+
+/** \brief Length for Ifx_CBS_TOPR_Bits.PIN5 */
+#define IFX_CBS_TOPR_PIN5_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TOPR_Bits.PIN5 */
+#define IFX_CBS_TOPR_PIN5_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TOPR_Bits.PIN5 */
+#define IFX_CBS_TOPR_PIN5_OFF (20u)
+
+/** \brief Length for Ifx_CBS_TOPR_Bits.PIN6 */
+#define IFX_CBS_TOPR_PIN6_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TOPR_Bits.PIN6 */
+#define IFX_CBS_TOPR_PIN6_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TOPR_Bits.PIN6 */
+#define IFX_CBS_TOPR_PIN6_OFF (24u)
+
+/** \brief Length for Ifx_CBS_TOPR_Bits.PIN7 */
+#define IFX_CBS_TOPR_PIN7_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TOPR_Bits.PIN7 */
+#define IFX_CBS_TOPR_PIN7_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TOPR_Bits.PIN7 */
+#define IFX_CBS_TOPR_PIN7_OFF (28u)
+
+/** \brief Length for Ifx_CBS_TRC_Bits.BRKIN */
+#define IFX_CBS_TRC_BRKIN_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TRC_Bits.BRKIN */
+#define IFX_CBS_TRC_BRKIN_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TRC_Bits.BRKIN */
+#define IFX_CBS_TRC_BRKIN_OFF (20u)
+
+/** \brief Length for Ifx_CBS_TRC_Bits.BRKOUT */
+#define IFX_CBS_TRC_BRKOUT_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TRC_Bits.BRKOUT */
+#define IFX_CBS_TRC_BRKOUT_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TRC_Bits.BRKOUT */
+#define IFX_CBS_TRC_BRKOUT_OFF (4u)
+
+/** \brief Length for Ifx_CBS_TRC_Bits.BT1 */
+#define IFX_CBS_TRC_BT1_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRC_Bits.BT1 */
+#define IFX_CBS_TRC_BT1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRC_Bits.BT1 */
+#define IFX_CBS_TRC_BT1_OFF (8u)
+
+/** \brief Length for Ifx_CBS_TRC_Bits.HALT */
+#define IFX_CBS_TRC_HALT_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TRC_Bits.HALT */
+#define IFX_CBS_TRC_HALT_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TRC_Bits.HALT */
+#define IFX_CBS_TRC_HALT_OFF (0u)
+
+/** \brief Length for Ifx_CBS_TRC_Bits.SUSIN */
+#define IFX_CBS_TRC_SUSIN_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TRC_Bits.SUSIN */
+#define IFX_CBS_TRC_SUSIN_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TRC_Bits.SUSIN */
+#define IFX_CBS_TRC_SUSIN_OFF (24u)
+
+/** \brief Length for Ifx_CBS_TREC_Bits.TR0EV */
+#define IFX_CBS_TREC_TR0EV_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TREC_Bits.TR0EV */
+#define IFX_CBS_TREC_TR0EV_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TREC_Bits.TR0EV */
+#define IFX_CBS_TREC_TR0EV_OFF (0u)
+
+/** \brief Length for Ifx_CBS_TREC_Bits.TR2EV */
+#define IFX_CBS_TREC_TR2EV_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TREC_Bits.TR2EV */
+#define IFX_CBS_TREC_TR2EV_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TREC_Bits.TR2EV */
+#define IFX_CBS_TREC_TR2EV_OFF (8u)
+
+/** \brief Length for Ifx_CBS_TREC_Bits.TR4EV */
+#define IFX_CBS_TREC_TR4EV_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TREC_Bits.TR4EV */
+#define IFX_CBS_TREC_TR4EV_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TREC_Bits.TR4EV */
+#define IFX_CBS_TREC_TR4EV_OFF (16u)
+
+/** \brief Length for Ifx_CBS_TREC_Bits.TR6EV */
+#define IFX_CBS_TREC_TR6EV_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TREC_Bits.TR6EV */
+#define IFX_CBS_TREC_TR6EV_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TREC_Bits.TR6EV */
+#define IFX_CBS_TREC_TR6EV_OFF (24u)
+
+/** \brief Length for Ifx_CBS_TRIG_Bits.TRGx_0 */
+#define IFX_CBS_TRIG_TRGX_0_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIG_Bits.TRGx_0 */
+#define IFX_CBS_TRIG_TRGX_0_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIG_Bits.TRGx_0 */
+#define IFX_CBS_TRIG_TRGX_0_OFF (0u)
+
+/** \brief Length for Ifx_CBS_TRIG_Bits.TRGx_10 */
+#define IFX_CBS_TRIG_TRGX_10_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIG_Bits.TRGx_10 */
+#define IFX_CBS_TRIG_TRGX_10_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIG_Bits.TRGx_10 */
+#define IFX_CBS_TRIG_TRGX_10_OFF (10u)
+
+/** \brief Length for Ifx_CBS_TRIG_Bits.TRGx_11 */
+#define IFX_CBS_TRIG_TRGX_11_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIG_Bits.TRGx_11 */
+#define IFX_CBS_TRIG_TRGX_11_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIG_Bits.TRGx_11 */
+#define IFX_CBS_TRIG_TRGX_11_OFF (11u)
+
+/** \brief Length for Ifx_CBS_TRIG_Bits.TRGx_12 */
+#define IFX_CBS_TRIG_TRGX_12_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIG_Bits.TRGx_12 */
+#define IFX_CBS_TRIG_TRGX_12_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIG_Bits.TRGx_12 */
+#define IFX_CBS_TRIG_TRGX_12_OFF (12u)
+
+/** \brief Length for Ifx_CBS_TRIG_Bits.TRGx_13 */
+#define IFX_CBS_TRIG_TRGX_13_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIG_Bits.TRGx_13 */
+#define IFX_CBS_TRIG_TRGX_13_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIG_Bits.TRGx_13 */
+#define IFX_CBS_TRIG_TRGX_13_OFF (13u)
+
+/** \brief Length for Ifx_CBS_TRIG_Bits.TRGx_14 */
+#define IFX_CBS_TRIG_TRGX_14_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIG_Bits.TRGx_14 */
+#define IFX_CBS_TRIG_TRGX_14_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIG_Bits.TRGx_14 */
+#define IFX_CBS_TRIG_TRGX_14_OFF (14u)
+
+/** \brief Length for Ifx_CBS_TRIG_Bits.TRGx_15 */
+#define IFX_CBS_TRIG_TRGX_15_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIG_Bits.TRGx_15 */
+#define IFX_CBS_TRIG_TRGX_15_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIG_Bits.TRGx_15 */
+#define IFX_CBS_TRIG_TRGX_15_OFF (15u)
+
+/** \brief Length for Ifx_CBS_TRIG_Bits.TRGx_16 */
+#define IFX_CBS_TRIG_TRGX_16_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIG_Bits.TRGx_16 */
+#define IFX_CBS_TRIG_TRGX_16_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIG_Bits.TRGx_16 */
+#define IFX_CBS_TRIG_TRGX_16_OFF (16u)
+
+/** \brief Length for Ifx_CBS_TRIG_Bits.TRGx_17 */
+#define IFX_CBS_TRIG_TRGX_17_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIG_Bits.TRGx_17 */
+#define IFX_CBS_TRIG_TRGX_17_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIG_Bits.TRGx_17 */
+#define IFX_CBS_TRIG_TRGX_17_OFF (17u)
+
+/** \brief Length for Ifx_CBS_TRIG_Bits.TRGx_18 */
+#define IFX_CBS_TRIG_TRGX_18_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIG_Bits.TRGx_18 */
+#define IFX_CBS_TRIG_TRGX_18_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIG_Bits.TRGx_18 */
+#define IFX_CBS_TRIG_TRGX_18_OFF (18u)
+
+/** \brief Length for Ifx_CBS_TRIG_Bits.TRGx_19 */
+#define IFX_CBS_TRIG_TRGX_19_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIG_Bits.TRGx_19 */
+#define IFX_CBS_TRIG_TRGX_19_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIG_Bits.TRGx_19 */
+#define IFX_CBS_TRIG_TRGX_19_OFF (19u)
+
+/** \brief Length for Ifx_CBS_TRIG_Bits.TRGx_1 */
+#define IFX_CBS_TRIG_TRGX_1_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIG_Bits.TRGx_1 */
+#define IFX_CBS_TRIG_TRGX_1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIG_Bits.TRGx_1 */
+#define IFX_CBS_TRIG_TRGX_1_OFF (1u)
+
+/** \brief Length for Ifx_CBS_TRIG_Bits.TRGx_20 */
+#define IFX_CBS_TRIG_TRGX_20_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIG_Bits.TRGx_20 */
+#define IFX_CBS_TRIG_TRGX_20_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIG_Bits.TRGx_20 */
+#define IFX_CBS_TRIG_TRGX_20_OFF (20u)
+
+/** \brief Length for Ifx_CBS_TRIG_Bits.TRGx_21 */
+#define IFX_CBS_TRIG_TRGX_21_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIG_Bits.TRGx_21 */
+#define IFX_CBS_TRIG_TRGX_21_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIG_Bits.TRGx_21 */
+#define IFX_CBS_TRIG_TRGX_21_OFF (21u)
+
+/** \brief Length for Ifx_CBS_TRIG_Bits.TRGx_22 */
+#define IFX_CBS_TRIG_TRGX_22_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIG_Bits.TRGx_22 */
+#define IFX_CBS_TRIG_TRGX_22_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIG_Bits.TRGx_22 */
+#define IFX_CBS_TRIG_TRGX_22_OFF (22u)
+
+/** \brief Length for Ifx_CBS_TRIG_Bits.TRGx_23 */
+#define IFX_CBS_TRIG_TRGX_23_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIG_Bits.TRGx_23 */
+#define IFX_CBS_TRIG_TRGX_23_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIG_Bits.TRGx_23 */
+#define IFX_CBS_TRIG_TRGX_23_OFF (23u)
+
+/** \brief Length for Ifx_CBS_TRIG_Bits.TRGx_2 */
+#define IFX_CBS_TRIG_TRGX_2_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIG_Bits.TRGx_2 */
+#define IFX_CBS_TRIG_TRGX_2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIG_Bits.TRGx_2 */
+#define IFX_CBS_TRIG_TRGX_2_OFF (2u)
+
+/** \brief Length for Ifx_CBS_TRIG_Bits.TRGx_3 */
+#define IFX_CBS_TRIG_TRGX_3_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIG_Bits.TRGx_3 */
+#define IFX_CBS_TRIG_TRGX_3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIG_Bits.TRGx_3 */
+#define IFX_CBS_TRIG_TRGX_3_OFF (3u)
+
+/** \brief Length for Ifx_CBS_TRIG_Bits.TRGx_4 */
+#define IFX_CBS_TRIG_TRGX_4_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIG_Bits.TRGx_4 */
+#define IFX_CBS_TRIG_TRGX_4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIG_Bits.TRGx_4 */
+#define IFX_CBS_TRIG_TRGX_4_OFF (4u)
+
+/** \brief Length for Ifx_CBS_TRIG_Bits.TRGx_5 */
+#define IFX_CBS_TRIG_TRGX_5_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIG_Bits.TRGx_5 */
+#define IFX_CBS_TRIG_TRGX_5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIG_Bits.TRGx_5 */
+#define IFX_CBS_TRIG_TRGX_5_OFF (5u)
+
+/** \brief Length for Ifx_CBS_TRIG_Bits.TRGx_6 */
+#define IFX_CBS_TRIG_TRGX_6_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIG_Bits.TRGx_6 */
+#define IFX_CBS_TRIG_TRGX_6_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIG_Bits.TRGx_6 */
+#define IFX_CBS_TRIG_TRGX_6_OFF (6u)
+
+/** \brief Length for Ifx_CBS_TRIG_Bits.TRGx_7 */
+#define IFX_CBS_TRIG_TRGX_7_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIG_Bits.TRGx_7 */
+#define IFX_CBS_TRIG_TRGX_7_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIG_Bits.TRGx_7 */
+#define IFX_CBS_TRIG_TRGX_7_OFF (7u)
+
+/** \brief Length for Ifx_CBS_TRIG_Bits.TRGx_8 */
+#define IFX_CBS_TRIG_TRGX_8_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIG_Bits.TRGx_8 */
+#define IFX_CBS_TRIG_TRGX_8_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIG_Bits.TRGx_8 */
+#define IFX_CBS_TRIG_TRGX_8_OFF (8u)
+
+/** \brief Length for Ifx_CBS_TRIG_Bits.TRGx_9 */
+#define IFX_CBS_TRIG_TRGX_9_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIG_Bits.TRGx_9 */
+#define IFX_CBS_TRIG_TRGX_9_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIG_Bits.TRGx_9 */
+#define IFX_CBS_TRIG_TRGX_9_OFF (9u)
+
+/** \brief Length for Ifx_CBS_TRIG_Bits.x */
+#define IFX_CBS_TRIG_X_LEN (8u)
+
+/** \brief Mask for Ifx_CBS_TRIG_Bits.x */
+#define IFX_CBS_TRIG_X_MSK (0xffu)
+
+/** \brief Offset for Ifx_CBS_TRIG_Bits.x */
+#define IFX_CBS_TRIG_X_OFF (24u)
+
+/** \brief Length for Ifx_CBS_TRIGC_Bits.TRGx_0 */
+#define IFX_CBS_TRIGC_TRGX_0_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIGC_Bits.TRGx_0 */
+#define IFX_CBS_TRIGC_TRGX_0_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIGC_Bits.TRGx_0 */
+#define IFX_CBS_TRIGC_TRGX_0_OFF (0u)
+
+/** \brief Length for Ifx_CBS_TRIGC_Bits.TRGx_10 */
+#define IFX_CBS_TRIGC_TRGX_10_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIGC_Bits.TRGx_10 */
+#define IFX_CBS_TRIGC_TRGX_10_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIGC_Bits.TRGx_10 */
+#define IFX_CBS_TRIGC_TRGX_10_OFF (10u)
+
+/** \brief Length for Ifx_CBS_TRIGC_Bits.TRGx_11 */
+#define IFX_CBS_TRIGC_TRGX_11_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIGC_Bits.TRGx_11 */
+#define IFX_CBS_TRIGC_TRGX_11_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIGC_Bits.TRGx_11 */
+#define IFX_CBS_TRIGC_TRGX_11_OFF (11u)
+
+/** \brief Length for Ifx_CBS_TRIGC_Bits.TRGx_12 */
+#define IFX_CBS_TRIGC_TRGX_12_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIGC_Bits.TRGx_12 */
+#define IFX_CBS_TRIGC_TRGX_12_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIGC_Bits.TRGx_12 */
+#define IFX_CBS_TRIGC_TRGX_12_OFF (12u)
+
+/** \brief Length for Ifx_CBS_TRIGC_Bits.TRGx_13 */
+#define IFX_CBS_TRIGC_TRGX_13_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIGC_Bits.TRGx_13 */
+#define IFX_CBS_TRIGC_TRGX_13_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIGC_Bits.TRGx_13 */
+#define IFX_CBS_TRIGC_TRGX_13_OFF (13u)
+
+/** \brief Length for Ifx_CBS_TRIGC_Bits.TRGx_14 */
+#define IFX_CBS_TRIGC_TRGX_14_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIGC_Bits.TRGx_14 */
+#define IFX_CBS_TRIGC_TRGX_14_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIGC_Bits.TRGx_14 */
+#define IFX_CBS_TRIGC_TRGX_14_OFF (14u)
+
+/** \brief Length for Ifx_CBS_TRIGC_Bits.TRGx_15 */
+#define IFX_CBS_TRIGC_TRGX_15_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIGC_Bits.TRGx_15 */
+#define IFX_CBS_TRIGC_TRGX_15_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIGC_Bits.TRGx_15 */
+#define IFX_CBS_TRIGC_TRGX_15_OFF (15u)
+
+/** \brief Length for Ifx_CBS_TRIGC_Bits.TRGx_16 */
+#define IFX_CBS_TRIGC_TRGX_16_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIGC_Bits.TRGx_16 */
+#define IFX_CBS_TRIGC_TRGX_16_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIGC_Bits.TRGx_16 */
+#define IFX_CBS_TRIGC_TRGX_16_OFF (16u)
+
+/** \brief Length for Ifx_CBS_TRIGC_Bits.TRGx_17 */
+#define IFX_CBS_TRIGC_TRGX_17_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIGC_Bits.TRGx_17 */
+#define IFX_CBS_TRIGC_TRGX_17_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIGC_Bits.TRGx_17 */
+#define IFX_CBS_TRIGC_TRGX_17_OFF (17u)
+
+/** \brief Length for Ifx_CBS_TRIGC_Bits.TRGx_18 */
+#define IFX_CBS_TRIGC_TRGX_18_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIGC_Bits.TRGx_18 */
+#define IFX_CBS_TRIGC_TRGX_18_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIGC_Bits.TRGx_18 */
+#define IFX_CBS_TRIGC_TRGX_18_OFF (18u)
+
+/** \brief Length for Ifx_CBS_TRIGC_Bits.TRGx_19 */
+#define IFX_CBS_TRIGC_TRGX_19_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIGC_Bits.TRGx_19 */
+#define IFX_CBS_TRIGC_TRGX_19_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIGC_Bits.TRGx_19 */
+#define IFX_CBS_TRIGC_TRGX_19_OFF (19u)
+
+/** \brief Length for Ifx_CBS_TRIGC_Bits.TRGx_1 */
+#define IFX_CBS_TRIGC_TRGX_1_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIGC_Bits.TRGx_1 */
+#define IFX_CBS_TRIGC_TRGX_1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIGC_Bits.TRGx_1 */
+#define IFX_CBS_TRIGC_TRGX_1_OFF (1u)
+
+/** \brief Length for Ifx_CBS_TRIGC_Bits.TRGx_20 */
+#define IFX_CBS_TRIGC_TRGX_20_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIGC_Bits.TRGx_20 */
+#define IFX_CBS_TRIGC_TRGX_20_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIGC_Bits.TRGx_20 */
+#define IFX_CBS_TRIGC_TRGX_20_OFF (20u)
+
+/** \brief Length for Ifx_CBS_TRIGC_Bits.TRGx_21 */
+#define IFX_CBS_TRIGC_TRGX_21_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIGC_Bits.TRGx_21 */
+#define IFX_CBS_TRIGC_TRGX_21_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIGC_Bits.TRGx_21 */
+#define IFX_CBS_TRIGC_TRGX_21_OFF (21u)
+
+/** \brief Length for Ifx_CBS_TRIGC_Bits.TRGx_22 */
+#define IFX_CBS_TRIGC_TRGX_22_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIGC_Bits.TRGx_22 */
+#define IFX_CBS_TRIGC_TRGX_22_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIGC_Bits.TRGx_22 */
+#define IFX_CBS_TRIGC_TRGX_22_OFF (22u)
+
+/** \brief Length for Ifx_CBS_TRIGC_Bits.TRGx_23 */
+#define IFX_CBS_TRIGC_TRGX_23_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIGC_Bits.TRGx_23 */
+#define IFX_CBS_TRIGC_TRGX_23_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIGC_Bits.TRGx_23 */
+#define IFX_CBS_TRIGC_TRGX_23_OFF (23u)
+
+/** \brief Length for Ifx_CBS_TRIGC_Bits.TRGx_2 */
+#define IFX_CBS_TRIGC_TRGX_2_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIGC_Bits.TRGx_2 */
+#define IFX_CBS_TRIGC_TRGX_2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIGC_Bits.TRGx_2 */
+#define IFX_CBS_TRIGC_TRGX_2_OFF (2u)
+
+/** \brief Length for Ifx_CBS_TRIGC_Bits.TRGx_3 */
+#define IFX_CBS_TRIGC_TRGX_3_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIGC_Bits.TRGx_3 */
+#define IFX_CBS_TRIGC_TRGX_3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIGC_Bits.TRGx_3 */
+#define IFX_CBS_TRIGC_TRGX_3_OFF (3u)
+
+/** \brief Length for Ifx_CBS_TRIGC_Bits.TRGx_4 */
+#define IFX_CBS_TRIGC_TRGX_4_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIGC_Bits.TRGx_4 */
+#define IFX_CBS_TRIGC_TRGX_4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIGC_Bits.TRGx_4 */
+#define IFX_CBS_TRIGC_TRGX_4_OFF (4u)
+
+/** \brief Length for Ifx_CBS_TRIGC_Bits.TRGx_5 */
+#define IFX_CBS_TRIGC_TRGX_5_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIGC_Bits.TRGx_5 */
+#define IFX_CBS_TRIGC_TRGX_5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIGC_Bits.TRGx_5 */
+#define IFX_CBS_TRIGC_TRGX_5_OFF (5u)
+
+/** \brief Length for Ifx_CBS_TRIGC_Bits.TRGx_6 */
+#define IFX_CBS_TRIGC_TRGX_6_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIGC_Bits.TRGx_6 */
+#define IFX_CBS_TRIGC_TRGX_6_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIGC_Bits.TRGx_6 */
+#define IFX_CBS_TRIGC_TRGX_6_OFF (6u)
+
+/** \brief Length for Ifx_CBS_TRIGC_Bits.TRGx_7 */
+#define IFX_CBS_TRIGC_TRGX_7_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIGC_Bits.TRGx_7 */
+#define IFX_CBS_TRIGC_TRGX_7_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIGC_Bits.TRGx_7 */
+#define IFX_CBS_TRIGC_TRGX_7_OFF (7u)
+
+/** \brief Length for Ifx_CBS_TRIGC_Bits.TRGx_8 */
+#define IFX_CBS_TRIGC_TRGX_8_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIGC_Bits.TRGx_8 */
+#define IFX_CBS_TRIGC_TRGX_8_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIGC_Bits.TRGx_8 */
+#define IFX_CBS_TRIGC_TRGX_8_OFF (8u)
+
+/** \brief Length for Ifx_CBS_TRIGC_Bits.TRGx_9 */
+#define IFX_CBS_TRIGC_TRGX_9_LEN (1u)
+
+/** \brief Mask for Ifx_CBS_TRIGC_Bits.TRGx_9 */
+#define IFX_CBS_TRIGC_TRGX_9_MSK (0x1u)
+
+/** \brief Offset for Ifx_CBS_TRIGC_Bits.TRGx_9 */
+#define IFX_CBS_TRIGC_TRGX_9_OFF (9u)
+
+/** \brief Length for Ifx_CBS_TRIGC_Bits.x */
+#define IFX_CBS_TRIGC_X_LEN (8u)
+
+/** \brief Mask for Ifx_CBS_TRIGC_Bits.x */
+#define IFX_CBS_TRIGC_X_MSK (0xffu)
+
+/** \brief Offset for Ifx_CBS_TRIGC_Bits.x */
+#define IFX_CBS_TRIGC_X_OFF (24u)
+
+/** \brief Length for Ifx_CBS_TRIGS_Bits.BITNUM */
+#define IFX_CBS_TRIGS_BITNUM_LEN (13u)
+
+/** \brief Mask for Ifx_CBS_TRIGS_Bits.BITNUM */
+#define IFX_CBS_TRIGS_BITNUM_MSK (0x1fffu)
+
+/** \brief Offset for Ifx_CBS_TRIGS_Bits.BITNUM */
+#define IFX_CBS_TRIGS_BITNUM_OFF (0u)
+
+/** \brief Length for Ifx_CBS_TRMC_Bits.BRKIN */
+#define IFX_CBS_TRMC_BRKIN_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TRMC_Bits.BRKIN */
+#define IFX_CBS_TRMC_BRKIN_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TRMC_Bits.BRKIN */
+#define IFX_CBS_TRMC_BRKIN_OFF (20u)
+
+/** \brief Length for Ifx_CBS_TRMC_Bits.BRKOUT */
+#define IFX_CBS_TRMC_BRKOUT_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TRMC_Bits.BRKOUT */
+#define IFX_CBS_TRMC_BRKOUT_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TRMC_Bits.BRKOUT */
+#define IFX_CBS_TRMC_BRKOUT_OFF (4u)
+
+/** \brief Length for Ifx_CBS_TRMC_Bits.SUSOUT */
+#define IFX_CBS_TRMC_SUSOUT_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TRMC_Bits.SUSOUT */
+#define IFX_CBS_TRMC_SUSOUT_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TRMC_Bits.SUSOUT */
+#define IFX_CBS_TRMC_SUSOUT_OFF (8u)
+
+/** \brief Length for Ifx_CBS_TRMT_Bits.TG0 */
+#define IFX_CBS_TRMT_TG0_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TRMT_Bits.TG0 */
+#define IFX_CBS_TRMT_TG0_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TRMT_Bits.TG0 */
+#define IFX_CBS_TRMT_TG0_OFF (0u)
+
+/** \brief Length for Ifx_CBS_TRMT_Bits.TG1 */
+#define IFX_CBS_TRMT_TG1_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TRMT_Bits.TG1 */
+#define IFX_CBS_TRMT_TG1_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TRMT_Bits.TG1 */
+#define IFX_CBS_TRMT_TG1_OFF (4u)
+
+/** \brief Length for Ifx_CBS_TRMT_Bits.TG2 */
+#define IFX_CBS_TRMT_TG2_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TRMT_Bits.TG2 */
+#define IFX_CBS_TRMT_TG2_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TRMT_Bits.TG2 */
+#define IFX_CBS_TRMT_TG2_OFF (8u)
+
+/** \brief Length for Ifx_CBS_TRMT_Bits.TG3 */
+#define IFX_CBS_TRMT_TG3_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TRMT_Bits.TG3 */
+#define IFX_CBS_TRMT_TG3_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TRMT_Bits.TG3 */
+#define IFX_CBS_TRMT_TG3_OFF (12u)
+
+/** \brief Length for Ifx_CBS_TRSS_Bits.SRC0 */
+#define IFX_CBS_TRSS_SRC0_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TRSS_Bits.SRC0 */
+#define IFX_CBS_TRSS_SRC0_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TRSS_Bits.SRC0 */
+#define IFX_CBS_TRSS_SRC0_OFF (16u)
+
+/** \brief Length for Ifx_CBS_TRSS_Bits.SRC1 */
+#define IFX_CBS_TRSS_SRC1_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TRSS_Bits.SRC1 */
+#define IFX_CBS_TRSS_SRC1_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TRSS_Bits.SRC1 */
+#define IFX_CBS_TRSS_SRC1_OFF (20u)
+
+/** \brief Length for Ifx_CBS_TRSS_Bits.TT */
+#define IFX_CBS_TRSS_TT_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TRSS_Bits.TT */
+#define IFX_CBS_TRSS_TT_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TRSS_Bits.TT */
+#define IFX_CBS_TRSS_TT_OFF (0u)
+
+/** \brief Length for Ifx_CBS_TRTGB_H_Bits.TG10 */
+#define IFX_CBS_TRTGB_H_TG10_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TRTGB_H_Bits.TG10 */
+#define IFX_CBS_TRTGB_H_TG10_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TRTGB_H_Bits.TG10 */
+#define IFX_CBS_TRTGB_H_TG10_OFF (8u)
+
+/** \brief Length for Ifx_CBS_TRTGB_H_Bits.TG11 */
+#define IFX_CBS_TRTGB_H_TG11_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TRTGB_H_Bits.TG11 */
+#define IFX_CBS_TRTGB_H_TG11_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TRTGB_H_Bits.TG11 */
+#define IFX_CBS_TRTGB_H_TG11_OFF (12u)
+
+/** \brief Length for Ifx_CBS_TRTGB_H_Bits.TG12 */
+#define IFX_CBS_TRTGB_H_TG12_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TRTGB_H_Bits.TG12 */
+#define IFX_CBS_TRTGB_H_TG12_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TRTGB_H_Bits.TG12 */
+#define IFX_CBS_TRTGB_H_TG12_OFF (16u)
+
+/** \brief Length for Ifx_CBS_TRTGB_H_Bits.TG13 */
+#define IFX_CBS_TRTGB_H_TG13_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TRTGB_H_Bits.TG13 */
+#define IFX_CBS_TRTGB_H_TG13_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TRTGB_H_Bits.TG13 */
+#define IFX_CBS_TRTGB_H_TG13_OFF (20u)
+
+/** \brief Length for Ifx_CBS_TRTGB_H_Bits.TG14 */
+#define IFX_CBS_TRTGB_H_TG14_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TRTGB_H_Bits.TG14 */
+#define IFX_CBS_TRTGB_H_TG14_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TRTGB_H_Bits.TG14 */
+#define IFX_CBS_TRTGB_H_TG14_OFF (24u)
+
+/** \brief Length for Ifx_CBS_TRTGB_H_Bits.TG15 */
+#define IFX_CBS_TRTGB_H_TG15_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TRTGB_H_Bits.TG15 */
+#define IFX_CBS_TRTGB_H_TG15_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TRTGB_H_Bits.TG15 */
+#define IFX_CBS_TRTGB_H_TG15_OFF (28u)
+
+/** \brief Length for Ifx_CBS_TRTGB_H_Bits.TG8 */
+#define IFX_CBS_TRTGB_H_TG8_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TRTGB_H_Bits.TG8 */
+#define IFX_CBS_TRTGB_H_TG8_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TRTGB_H_Bits.TG8 */
+#define IFX_CBS_TRTGB_H_TG8_OFF (0u)
+
+/** \brief Length for Ifx_CBS_TRTGB_H_Bits.TG9 */
+#define IFX_CBS_TRTGB_H_TG9_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TRTGB_H_Bits.TG9 */
+#define IFX_CBS_TRTGB_H_TG9_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TRTGB_H_Bits.TG9 */
+#define IFX_CBS_TRTGB_H_TG9_OFF (4u)
+
+/** \brief Length for Ifx_CBS_TRTGB_L_Bits.TG0 */
+#define IFX_CBS_TRTGB_L_TG0_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TRTGB_L_Bits.TG0 */
+#define IFX_CBS_TRTGB_L_TG0_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TRTGB_L_Bits.TG0 */
+#define IFX_CBS_TRTGB_L_TG0_OFF (0u)
+
+/** \brief Length for Ifx_CBS_TRTGB_L_Bits.TG1 */
+#define IFX_CBS_TRTGB_L_TG1_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TRTGB_L_Bits.TG1 */
+#define IFX_CBS_TRTGB_L_TG1_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TRTGB_L_Bits.TG1 */
+#define IFX_CBS_TRTGB_L_TG1_OFF (4u)
+
+/** \brief Length for Ifx_CBS_TRTGB_L_Bits.TG2 */
+#define IFX_CBS_TRTGB_L_TG2_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TRTGB_L_Bits.TG2 */
+#define IFX_CBS_TRTGB_L_TG2_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TRTGB_L_Bits.TG2 */
+#define IFX_CBS_TRTGB_L_TG2_OFF (8u)
+
+/** \brief Length for Ifx_CBS_TRTGB_L_Bits.TG3 */
+#define IFX_CBS_TRTGB_L_TG3_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TRTGB_L_Bits.TG3 */
+#define IFX_CBS_TRTGB_L_TG3_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TRTGB_L_Bits.TG3 */
+#define IFX_CBS_TRTGB_L_TG3_OFF (12u)
+
+/** \brief Length for Ifx_CBS_TRTGB_L_Bits.TG4 */
+#define IFX_CBS_TRTGB_L_TG4_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TRTGB_L_Bits.TG4 */
+#define IFX_CBS_TRTGB_L_TG4_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TRTGB_L_Bits.TG4 */
+#define IFX_CBS_TRTGB_L_TG4_OFF (16u)
+
+/** \brief Length for Ifx_CBS_TRTGB_L_Bits.TG5 */
+#define IFX_CBS_TRTGB_L_TG5_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TRTGB_L_Bits.TG5 */
+#define IFX_CBS_TRTGB_L_TG5_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TRTGB_L_Bits.TG5 */
+#define IFX_CBS_TRTGB_L_TG5_OFF (20u)
+
+/** \brief Length for Ifx_CBS_TRTGB_L_Bits.TG6 */
+#define IFX_CBS_TRTGB_L_TG6_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TRTGB_L_Bits.TG6 */
+#define IFX_CBS_TRTGB_L_TG6_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TRTGB_L_Bits.TG6 */
+#define IFX_CBS_TRTGB_L_TG6_OFF (24u)
+
+/** \brief Length for Ifx_CBS_TRTGB_L_Bits.TG7 */
+#define IFX_CBS_TRTGB_L_TG7_LEN (4u)
+
+/** \brief Mask for Ifx_CBS_TRTGB_L_Bits.TG7 */
+#define IFX_CBS_TRTGB_L_TG7_MSK (0xfu)
+
+/** \brief Offset for Ifx_CBS_TRTGB_L_Bits.TG7 */
+#define IFX_CBS_TRTGB_L_TG7_OFF (28u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXCBS_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCbs_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCbs_reg.h
new file mode 100644
index 0000000..6a9636c
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCbs_reg.h
@@ -0,0 +1,269 @@
+/**
+ * \file IfxCbs_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Cbs_Cfg Cbs address
+ * \ingroup IfxLld_Cbs
+ *
+ * \defgroup IfxLld_Cbs_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Cbs_Cfg
+ *
+ * \defgroup IfxLld_Cbs_Cfg_Cbs 2-CBS
+ * \ingroup IfxLld_Cbs_Cfg
+ *
+ */
+#ifndef IFXCBS_REG_H
+#define IFXCBS_REG_H 1
+/******************************************************************************/
+#include "IfxCbs_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Cbs_Cfg_BaseAddress
+ * \{ */
+
+/** \brief CBS object */
+#define MODULE_CBS /*lint --e(923)*/ (*(Ifx_CBS*)0xF0000400u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Cbs_Cfg_Cbs
+ * \{ */
+
+/** \brief 68, Communication Mode Data Register */
+#define CBS_COMDATA /*lint --e(923)*/ (*(volatile Ifx_CBS_COMDATA*)0xF0000468u)
+
+/** \brief 88, Internally Controlled Trace Source Register */
+#define CBS_ICTSA /*lint --e(923)*/ (*(volatile Ifx_CBS_ICTSA*)0xF0000488u)
+
+/** \brief 8C, Internally Controlled Trace Destination Register */
+#define CBS_ICTTA /*lint --e(923)*/ (*(volatile Ifx_CBS_ICTTA*)0xF000048Cu)
+
+/** \brief 84, Internal Mode Status and Control Register */
+#define CBS_INTMOD /*lint --e(923)*/ (*(volatile Ifx_CBS_INTMOD*)0xF0000484u)
+
+/** \brief 6C, IOClient Status and Control Register */
+#define CBS_IOSR /*lint --e(923)*/ (*(volatile Ifx_CBS_IOSR*)0xF000046Cu)
+
+/** \brief 8, Module Identification Register */
+#define CBS_JDPID /*lint --e(923)*/ (*(volatile Ifx_CBS_JDPID*)0xF0000408u)
+
+/** \brief 64, JTAG Device Identification Register */
+#define CBS_JTAGID /*lint --e(923)*/ (*(volatile Ifx_CBS_JTAGID*)0xF0000464u)
+
+/** \brief 7C, OSCU Control Register */
+#define CBS_OCNTRL /*lint --e(923)*/ (*(volatile Ifx_CBS_OCNTRL*)0xF000047Cu)
+
+/** \brief 78, OCDS Enable Control Register */
+#define CBS_OEC /*lint --e(923)*/ (*(volatile Ifx_CBS_OEC*)0xF0000478u)
+
+/** \brief C, OCDS Interface Mode Register */
+#define CBS_OIFM /*lint --e(923)*/ (*(volatile Ifx_CBS_OIFM*)0xF000040Cu)
+
+/** \brief 80, OSCU Status Register */
+#define CBS_OSTATE /*lint --e(923)*/ (*(volatile Ifx_CBS_OSTATE*)0xF0000480u)
+
+/** \brief B0, TG Capture for Cores - BRKOUT */
+#define CBS_TCCB /*lint --e(923)*/ (*(volatile Ifx_CBS_TCCB*)0xF00004B0u)
+
+/** \brief B4, TG Capture for Cores - HALT */
+#define CBS_TCCH /*lint --e(923)*/ (*(volatile Ifx_CBS_TCCH*)0xF00004B4u)
+
+/** \brief 1C, TG Capture for TG Input Pins */
+#define CBS_TCIP /*lint --e(923)*/ (*(volatile Ifx_CBS_TCIP*)0xF000041Cu)
+
+/** \brief BC, TG Capture for MCDS */
+#define CBS_TCM /*lint --e(923)*/ (*(volatile Ifx_CBS_TCM*)0xF00004BCu)
+
+/** \brief B8, TG Capture for OTGB0/1 */
+#define CBS_TCTGB /*lint --e(923)*/ (*(volatile Ifx_CBS_TCTGB*)0xF00004B8u)
+
+/** \brief 74, TG Capture for TG Lines */
+#define CBS_TCTL /*lint --e(923)*/ (*(volatile Ifx_CBS_TCTL*)0xF0000474u)
+
+/** \brief 10, TG Input Pins Routing */
+#define CBS_TIPR /*lint --e(923)*/ (*(volatile Ifx_CBS_TIPR*)0xF0000410u)
+
+/** \brief 94, TG Line 1 Suspend Targets */
+#define CBS_TL1ST /*lint --e(923)*/ (*(volatile Ifx_CBS_TL1ST*)0xF0000494u)
+
+/** \brief 90, TG Line Control */
+#define CBS_TLC /*lint --e(923)*/ (*(volatile Ifx_CBS_TLC*)0xF0000490u)
+
+/** \brief 40, TG Line Counter Control */
+#define CBS_TLCC0 /*lint --e(923)*/ (*(volatile Ifx_CBS_TLCC*)0xF0000440u)
+
+/** \brief 44, TG Line Counter Control */
+#define CBS_TLCC1 /*lint --e(923)*/ (*(volatile Ifx_CBS_TLCC*)0xF0000444u)
+
+/** \brief 98, TG Line Capture and Hold Enable */
+#define CBS_TLCHE /*lint --e(923)*/ (*(volatile Ifx_CBS_TLCHE*)0xF0000498u)
+
+/** \brief 9C, TG Line Capture and Hold Clear */
+#define CBS_TLCHS /*lint --e(923)*/ (*(volatile Ifx_CBS_TLCHS*)0xF000049Cu)
+
+/** \brief 50, TG Line Counter Value */
+#define CBS_TLCV0 /*lint --e(923)*/ (*(volatile Ifx_CBS_TLCV*)0xF0000450u)
+
+/** \brief 54, TG Line Counter Value */
+#define CBS_TLCV1 /*lint --e(923)*/ (*(volatile Ifx_CBS_TLCV*)0xF0000454u)
+
+/** \brief 70, TG Line State */
+#define CBS_TLS /*lint --e(923)*/ (*(volatile Ifx_CBS_TLS*)0xF0000470u)
+
+/** \brief A8, TG Line Timer */
+#define CBS_TLT /*lint --e(923)*/ (*(volatile Ifx_CBS_TLT*)0xF00004A8u)
+
+/** \brief AC, TG Lines for Trigger to Host */
+#define CBS_TLTTH /*lint --e(923)*/ (*(volatile Ifx_CBS_TLTTH*)0xF00004ACu)
+
+/** \brief 18, TG Output Pins Pulse Stretcher */
+#define CBS_TOPPS /*lint --e(923)*/ (*(volatile Ifx_CBS_TOPPS*)0xF0000418u)
+
+/** \brief 14, TG Output Pins Routing */
+#define CBS_TOPR /*lint --e(923)*/ (*(volatile Ifx_CBS_TOPR*)0xF0000414u)
+
+/** \brief 20, TG Routing for CPU */
+#define CBS_TRC0 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRC*)0xF0000420u)
+
+/** \brief 24, TG Routing for CPU */
+#define CBS_TRC1 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRC*)0xF0000424u)
+
+/** \brief C0, TG Routing Events of CPU */
+#define CBS_TREC0 /*lint --e(923)*/ (*(volatile Ifx_CBS_TREC*)0xF00004C0u)
+
+/** \brief C4, TG Routing Events of CPU */
+#define CBS_TREC1 /*lint --e(923)*/ (*(volatile Ifx_CBS_TREC*)0xF00004C4u)
+
+/** \brief 100, Trigger to Host Register */
+#define CBS_TRIG0 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000500u)
+
+/** \brief 104, Trigger to Host Register */
+#define CBS_TRIG1 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000504u)
+
+/** \brief 128, Trigger to Host Register */
+#define CBS_TRIG10 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000528u)
+
+/** \brief 12C, Trigger to Host Register */
+#define CBS_TRIG11 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF000052Cu)
+
+/** \brief 130, Trigger to Host Register */
+#define CBS_TRIG12 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000530u)
+
+/** \brief 134, Trigger to Host Register */
+#define CBS_TRIG13 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000534u)
+
+/** \brief 138, Trigger to Host Register */
+#define CBS_TRIG14 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000538u)
+
+/** \brief 13C, Trigger to Host Register */
+#define CBS_TRIG15 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF000053Cu)
+
+/** \brief 140, Trigger to Host Register */
+#define CBS_TRIG16 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000540u)
+
+/** \brief 144, Trigger to Host Register */
+#define CBS_TRIG17 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000544u)
+
+/** \brief 148, Trigger to Host Register */
+#define CBS_TRIG18 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000548u)
+
+/** \brief 14C, Trigger to Host Register */
+#define CBS_TRIG19 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF000054Cu)
+
+/** \brief 108, Trigger to Host Register */
+#define CBS_TRIG2 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000508u)
+
+/** \brief 150, Trigger to Host Register */
+#define CBS_TRIG20 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000550u)
+
+/** \brief 154, Trigger to Host Register */
+#define CBS_TRIG21 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000554u)
+
+/** \brief 10C, Trigger to Host Register */
+#define CBS_TRIG3 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF000050Cu)
+
+/** \brief 110, Trigger to Host Register */
+#define CBS_TRIG4 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000510u)
+
+/** \brief 114, Trigger to Host Register */
+#define CBS_TRIG5 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000514u)
+
+/** \brief 118, Trigger to Host Register */
+#define CBS_TRIG6 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000518u)
+
+/** \brief 11C, Trigger to Host Register */
+#define CBS_TRIG7 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF000051Cu)
+
+/** \brief 120, Trigger to Host Register */
+#define CBS_TRIG8 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000520u)
+
+/** \brief 124, Trigger to Host Register */
+#define CBS_TRIG9 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000524u)
+
+/** \brief A4, Clear Trigger to Host Register */
+#define CBS_TRIGC /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIGC*)0xF00004A4u)
+
+/** \brief A0, Set Trigger to Host Register */
+#define CBS_TRIGS /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIGS*)0xF00004A0u)
+
+/** \brief 3C, TG Routing for MCDS Control */
+#define CBS_TRMC /*lint --e(923)*/ (*(volatile Ifx_CBS_TRMC*)0xF000043Cu)
+
+/** \brief DC, TG Routing for MCDS Triggers */
+#define CBS_TRMT /*lint --e(923)*/ (*(volatile Ifx_CBS_TRMT*)0xF00004DCu)
+
+/** \brief 60, TG Routing for Special Signals */
+#define CBS_TRSS /*lint --e(923)*/ (*(volatile Ifx_CBS_TRSS*)0xF0000460u)
+
+/** \brief E4, TG Routing for OTGB Bits [15:8] */
+#define CBS_TRTGB0_H /*lint --e(923)*/ (*(volatile Ifx_CBS_TRTGB_H*)0xF00004E4u)
+
+/** Alias (User Manual Name) for CBS_TRTGB0_H.
+* To use register names with standard convension, please use CBS_TRTGB0_H.
+*/
+#define CBS_TRTGB0H (CBS_TRTGB0_H)
+
+/** \brief E0, TG Routing for OTGB Bits [7:0] */
+#define CBS_TRTGB0_L /*lint --e(923)*/ (*(volatile Ifx_CBS_TRTGB_L*)0xF00004E0u)
+
+/** Alias (User Manual Name) for CBS_TRTGB0_L.
+* To use register names with standard convension, please use CBS_TRTGB0_L.
+*/
+#define CBS_TRTGB0L (CBS_TRTGB0_L)
+
+/** \brief EC, TG Routing for OTGB Bits [15:8] */
+#define CBS_TRTGB1_H /*lint --e(923)*/ (*(volatile Ifx_CBS_TRTGB_H*)0xF00004ECu)
+
+/** Alias (User Manual Name) for CBS_TRTGB1_H.
+* To use register names with standard convension, please use CBS_TRTGB1_H.
+*/
+#define CBS_TRTGB1H (CBS_TRTGB1_H)
+
+/** \brief E8, TG Routing for OTGB Bits [7:0] */
+#define CBS_TRTGB1_L /*lint --e(923)*/ (*(volatile Ifx_CBS_TRTGB_L*)0xF00004E8u)
+
+/** Alias (User Manual Name) for CBS_TRTGB1_L.
+* To use register names with standard convension, please use CBS_TRTGB1_L.
+*/
+#define CBS_TRTGB1L (CBS_TRTGB1_L)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXCBS_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCbs_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCbs_regdef.h
new file mode 100644
index 0000000..bf8468a
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCbs_regdef.h
@@ -0,0 +1,957 @@
+/**
+ * \file IfxCbs_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Cbs Cbs
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Cbs_Bitfields Bitfields
+ * \ingroup IfxLld_Cbs
+ *
+ * \defgroup IfxLld_Cbs_union Union
+ * \ingroup IfxLld_Cbs
+ *
+ * \defgroup IfxLld_Cbs_struct Struct
+ * \ingroup IfxLld_Cbs
+ *
+ */
+#ifndef IFXCBS_REGDEF_H
+#define IFXCBS_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Cbs_Bitfields
+ * \{ */
+
+/** \brief Communication Mode Data Register */
+typedef struct _Ifx_CBS_COMDATA_Bits
+{
+ unsigned int DATA:32; /**< \brief [31:0] Read/Write Data (rw) */
+} Ifx_CBS_COMDATA_Bits;
+
+/** \brief Internally Controlled Trace Source Register */
+typedef struct _Ifx_CBS_ICTSA_Bits
+{
+ unsigned int ADDR:32; /**< \brief [31:0] Source Address (rw) */
+} Ifx_CBS_ICTSA_Bits;
+
+/** \brief Internally Controlled Trace Destination Register */
+typedef struct _Ifx_CBS_ICTTA_Bits
+{
+ unsigned int ADDR:32; /**< \brief [31:0] Destination Address (rw) */
+} Ifx_CBS_ICTTA_Bits;
+
+/** \brief Internal Mode Status and Control Register */
+typedef struct _Ifx_CBS_INTMOD_Bits
+{
+ unsigned int SET_CRS:1; /**< \brief [0:0] Set Read Sync Flag (w) */
+ unsigned int SET_CWS:1; /**< \brief [1:1] Set Write Sync Flag (w) */
+ unsigned int SET_CS:1; /**< \brief [2:2] Set Communication Synchronization Flag (w) */
+ unsigned int CLR_CS:1; /**< \brief [3:3] Clear Communication Synchronization Flag (w) */
+ unsigned int CHANNEL_P:1; /**< \brief [4:4] CHANNEL Write Protection (w) */
+ unsigned int CHANNEL:3; /**< \brief [7:5] Channel Indication (rw) */
+ unsigned int reserved_8:8; /**< \brief \internal Reserved */
+ unsigned int SET_INT_MOD:1; /**< \brief [16:16] Enter Internal Mode (w) */
+ unsigned int reserved_17:1; /**< \brief \internal Reserved */
+ unsigned int SET_INT_TRC:1; /**< \brief [18:18] Enable Internally Controlled Triggered Transfer (w) */
+ unsigned int CLR_INT_TRC:1; /**< \brief [19:19] Disable Internally Controlled Triggered Transfer (w) */
+ unsigned int TRC_MOD_P:1; /**< \brief [20:20] TRC_MOD Write Protection (w) */
+ unsigned int TRC_MOD:2; /**< \brief [22:21] Data Size Definition for Triggered Transfer (rw) */
+ unsigned int reserved_23:1; /**< \brief \internal Reserved */
+ unsigned int INT_MOD:1; /**< \brief [24:24] Internal Mode Enabled Flag (rh) */
+ unsigned int INT_TRC:1; /**< \brief [25:25] Internally Controlled Triggered Transfer Enable (rh) */
+ unsigned int reserved_26:6; /**< \brief \internal Reserved */
+} Ifx_CBS_INTMOD_Bits;
+
+/** \brief IOClient Status and Control Register */
+typedef struct _Ifx_CBS_IOSR_Bits
+{
+ unsigned int reserved_0:4; /**< \brief \internal Reserved */
+ unsigned int CRSYNC:1; /**< \brief [4:4] Communication Mode Read Sync Flag (rh) */
+ unsigned int CWSYNC:1; /**< \brief [5:5] Communication Mode Write Sync Flag (rh) */
+ unsigned int CW_ACK:1; /**< \brief [6:6] Communication Mode Write Acknowledge (w) */
+ unsigned int COM_SYNC:1; /**< \brief [7:7] Communication Mode Synchronization Flag (rh) */
+ unsigned int HOSTED:1; /**< \brief [8:8] Tool Interface in Use (rh) */
+ unsigned int reserved_9:3; /**< \brief \internal Reserved */
+ unsigned int CHANNEL:3; /**< \brief [14:12] Channel Indication (rh) */
+ unsigned int reserved_15:17; /**< \brief \internal Reserved */
+} Ifx_CBS_IOSR_Bits;
+
+/** \brief Module Identification Register */
+typedef struct _Ifx_CBS_JDPID_Bits
+{
+ unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
+ unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_CBS_JDPID_Bits;
+
+/** \brief JTAG Device Identification Register */
+typedef struct _Ifx_CBS_JTAGID_Bits
+{
+ unsigned int JTAG_ID:32; /**< \brief [31:0] JTAG Device ID (rw) */
+} Ifx_CBS_JTAGID_Bits;
+
+/** \brief OSCU Control Register */
+typedef struct _Ifx_CBS_OCNTRL_Bits
+{
+ unsigned int OC0_P:1; /**< \brief [0:0] OC0 Write Protection (w) */
+ unsigned int OC0:1; /**< \brief [1:1] Set/Clear OCDS Control Bits Bus Domain (w) */
+ unsigned int OC1_P:1; /**< \brief [2:2] OC1 Write Protection (w) */
+ unsigned int OC1:1; /**< \brief [3:3] Set/Clear OCDS Control Bits Bus Domain (w) */
+ unsigned int OC2_P:1; /**< \brief [4:4] OC2 Write Protection (w) */
+ unsigned int OC2:1; /**< \brief [5:5] Set/Clear OCDS Control Bits Bus Domain (w) */
+ unsigned int OC3_P:1; /**< \brief [6:6] OC3 Write Protection (w) */
+ unsigned int OC3:1; /**< \brief [7:7] Set/Clear OCDS Control Bits Bus Domain (w) */
+ unsigned int OC4_P:1; /**< \brief [8:8] OC4 Write Protection (w) */
+ unsigned int OC4:1; /**< \brief [9:9] Set/Clear OCDS Control Bits Bus Domain (w) */
+ unsigned int OC5_P:1; /**< \brief [10:10] OC5 Write Protection (w) */
+ unsigned int OC5:1; /**< \brief [11:11] Set/Clear OCDS Control Bits Bus Domain (w) */
+ unsigned int WDTSUS_P:1; /**< \brief [12:12] WDTSUS Write Protection (w) */
+ unsigned int WDTSUS:1; /**< \brief [13:13] Set/Clear Watchdog Timer Suspension Control (w) */
+ unsigned int STABLE_P:1; /**< \brief [14:14] STABLE Write Protection (w) */
+ unsigned int STABLE:1; /**< \brief [15:15] Initialize Application Reset Indication (w) */
+ unsigned int OJC0_P:1; /**< \brief [16:16] OJC0 Write Protection (w) */
+ unsigned int OJC0:1; /**< \brief [17:17] Set/Clear OCDS Control Bits IOClient Domain (w) */
+ unsigned int OJC1_P:1; /**< \brief [18:18] OJC1 Write Protection (w) */
+ unsigned int OJC1:1; /**< \brief [19:19] Set/Clear OCDS Control Bits IOClient Domain (w) */
+ unsigned int OJC2_P:1; /**< \brief [20:20] OJC2 Write Protection (w) */
+ unsigned int OJC2:1; /**< \brief [21:21] Set/Clear OCDS Control Bits IOClient Domain (w) */
+ unsigned int OJC3_P:1; /**< \brief [22:22] OJC3 Write Protection (w) */
+ unsigned int OJC3:1; /**< \brief [23:23] Set/Clear OCDS Control Bits IOClient Domain (w) */
+ unsigned int OJC4_P:1; /**< \brief [24:24] OJC4 Write Protection (w) */
+ unsigned int OJC4:1; /**< \brief [25:25] Set/Clear OCDS Control Bits IOClient Domain (w) */
+ unsigned int OJC5_P:1; /**< \brief [26:26] OJC5 Write Protection (w) */
+ unsigned int OJC5:1; /**< \brief [27:27] Set/Clear OCDS Control Bits IOClient Domain (w) */
+ unsigned int OJC6_P:1; /**< \brief [28:28] OJC6 Write Protection (w) */
+ unsigned int OJC6:1; /**< \brief [29:29] Set/Clear OCDS Control Bits IOClient Domain (w) */
+ unsigned int OJC7_P:1; /**< \brief [30:30] OJC7 Write Protection (w) */
+ unsigned int OJC7:1; /**< \brief [31:31] Set/Clear OCDS Control Bits IOClient Domain (w) */
+} Ifx_CBS_OCNTRL_Bits;
+
+/** \brief OCDS Enable Control Register */
+typedef struct _Ifx_CBS_OEC_Bits
+{
+ unsigned int PAT:8; /**< \brief [7:0] OCDS Enabling Pattern (w) */
+ unsigned int DS:1; /**< \brief [8:8] Disable OCDS (w) */
+ unsigned int OCO:1; /**< \brief [9:9] OCDS Clock Off (w) */
+ unsigned int reserved_10:6; /**< \brief \internal Reserved */
+ unsigned int IF_LCK_P:1; /**< \brief [16:16] IF_LCK Write Protection (w) */
+ unsigned int IF_LCK:1; /**< \brief [17:17] Set/Clear Interface Locked Indication (w) */
+ unsigned int AUT_OK_P:1; /**< \brief [18:18] AUT_OK Write Protection (w) */
+ unsigned int AUT_OK:1; /**< \brief [19:19] Set/Clear the Authorization OK Indication (w) */
+ unsigned int reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_CBS_OEC_Bits;
+
+/** \brief OCDS Interface Mode Register */
+typedef struct _Ifx_CBS_OIFM_Bits
+{
+ unsigned int DAPMODE:3; /**< \brief [2:0] DAP Interface Mode (rw) */
+ unsigned int DAPRST:1; /**< \brief [3:3] DAP Protocol Clear (rwh) */
+ unsigned int reserved_4:4; /**< \brief \internal Reserved */
+ unsigned int F_JTAG:1; /**< \brief [8:8] Forced JTAG Mode (rw) */
+ unsigned int N_JTAG:1; /**< \brief [9:9] No Switch to JTAG (rw) */
+ unsigned int reserved_10:2; /**< \brief \internal Reserved */
+ unsigned int PADCTL:4; /**< \brief [15:12] Pad Control for Debug Interface Pins (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CBS_OIFM_Bits;
+
+/** \brief OSCU Status Register */
+typedef struct _Ifx_CBS_OSTATE_Bits
+{
+ unsigned int OEN:1; /**< \brief [0:0] OCDS Enabled Flag (rh) */
+ unsigned int OC0:1; /**< \brief [1:1] OCDS Control Bits System Bus Domain (rh) */
+ unsigned int OC1:1; /**< \brief [2:2] OCDS Control Bits System Bus Domain (rh) */
+ unsigned int OC2:1; /**< \brief [3:3] OCDS Control Bits System Bus Domain (rh) */
+ unsigned int ENIDIS:1; /**< \brief [4:4] OCDS ENDINIT Protection Override (rh) */
+ unsigned int EECTRC:1; /**< \brief [5:5] On Chip Trace Enable (rh) */
+ unsigned int EECDIS:1; /**< \brief [6:6] Emulation Logic Disable (rh) */
+ unsigned int WDTSUS:1; /**< \brief [7:7] Control of Watchdog Timer Suspension (rh) */
+ unsigned int HARR:1; /**< \brief [8:8] Halt after Reset Request (rh) */
+ unsigned int OJC1:1; /**< \brief [9:9] OCDS Control Bits IOClient Domain (rh) */
+ unsigned int OJC2:1; /**< \brief [10:10] OCDS Control Bits IOClient Domain (rh) */
+ unsigned int OJC3:1; /**< \brief [11:11] OCDS Control Bits IOClient Domain (rh) */
+ unsigned int RSTCL0:1; /**< \brief [12:12] OCDS System Reset Request (rh) */
+ unsigned int RSTCL1:1; /**< \brief [13:13] OCDS Debug Reset Request (rh) */
+ unsigned int OJC6:1; /**< \brief [14:14] OCDS Control Bits IOClient Domain (rh) */
+ unsigned int RSTCL3:1; /**< \brief [15:15] OCDS Application Reset Request (rh) */
+ unsigned int IF_LCK:1; /**< \brief [16:16] Interface Locked Indication (rh) */
+ unsigned int AUT_OK:1; /**< \brief [17:17] Authorization OK Indication (rh) */
+ unsigned int STABLE:1; /**< \brief [18:18] Application Reset Indication (rh) */
+ unsigned int OCO:1; /**< \brief [19:19] OCDS debug resource Clock On Indication (rh) */
+ unsigned int reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_CBS_OSTATE_Bits;
+
+/** \brief TG Capture for Cores - BRKOUT */
+typedef struct _Ifx_CBS_TCCB_Bits
+{
+ unsigned int C0:1; /**< \brief [0:0] Capture of BRKOUT Signal of CPU0 (rh) */
+ unsigned int C1:1; /**< \brief [1:1] Capture of BRKOUT Signal of CPU1 (rh) */
+ unsigned int C2:1; /**< \brief [2:2] Capture of BRKOUT Signal of CPU2 (rh) */
+ unsigned int reserved_3:28; /**< \brief \internal Reserved */
+ unsigned int HSM:1; /**< \brief [31:31] Capture of BRKOUT Signal of (rh) */
+} Ifx_CBS_TCCB_Bits;
+
+/** \brief TG Capture for Cores - HALT */
+typedef struct _Ifx_CBS_TCCH_Bits
+{
+ unsigned int C0:1; /**< \brief [0:0] Capture of HALT Signal of CPU0 (rh) */
+ unsigned int C1:1; /**< \brief [1:1] Capture of HALT Signal of CPU1 (rh) */
+ unsigned int C2:1; /**< \brief [2:2] Capture of HALT Signal of CPU2 (rh) */
+ unsigned int reserved_3:28; /**< \brief \internal Reserved */
+ unsigned int HSM:1; /**< \brief [31:31] Capture of HALT Signal of (rh) */
+} Ifx_CBS_TCCH_Bits;
+
+/** \brief TG Capture for TG Input Pins */
+typedef struct _Ifx_CBS_TCIP_Bits
+{
+ unsigned int P0:1; /**< \brief [0:0] Capture of Trigger Input Pin 0 (rh) */
+ unsigned int P1:1; /**< \brief [1:1] Capture of Trigger Input Pin 1 (rh) */
+ unsigned int P2:1; /**< \brief [2:2] Capture of Trigger Input Pin 2 (rh) */
+ unsigned int P3:1; /**< \brief [3:3] Capture of Trigger Input Pin 3 (rh) */
+ unsigned int P4:1; /**< \brief [4:4] Capture of Trigger Input Pin 4 (rh) */
+ unsigned int P5:1; /**< \brief [5:5] Capture of Trigger Input Pin 5 (rh) */
+ unsigned int P6:1; /**< \brief [6:6] Capture of Trigger Input Pin 6 (rh) */
+ unsigned int P7:1; /**< \brief [7:7] Capture of Trigger Input Pin 7 (rh) */
+ unsigned int reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_CBS_TCIP_Bits;
+
+/** \brief TG Capture for MCDS */
+typedef struct _Ifx_CBS_TCM_Bits
+{
+ unsigned int BRK:1; /**< \brief [0:0] Capture of MCDS break_out (rh) */
+ unsigned int SUS:1; /**< \brief [1:1] Capture of MCDS suspend_out (rh) */
+ unsigned int reserved_2:6; /**< \brief \internal Reserved */
+ unsigned int T0:1; /**< \brief [8:8] Capture of MCDS trig_out 0 (rh) */
+ unsigned int T1:1; /**< \brief [9:9] Capture of MCDS trig_out 1 (rh) */
+ unsigned int T2:1; /**< \brief [10:10] Capture of MCDS trig_out 2 (rh) */
+ unsigned int T3:1; /**< \brief [11:11] Capture of MCDS trig_out 3 (rh) */
+ unsigned int reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_CBS_TCM_Bits;
+
+/** \brief TG Capture for OTGB0/1 */
+typedef struct _Ifx_CBS_TCTGB_Bits
+{
+ unsigned int OTGB0:16; /**< \brief [15:0] Capture Bits for OTGB0 (rh) */
+ unsigned int OTGB1:16; /**< \brief [31:16] Capture Bits for OTGB1 (rh) */
+} Ifx_CBS_TCTGB_Bits;
+
+/** \brief TG Capture for TG Lines */
+typedef struct _Ifx_CBS_TCTL_Bits
+{
+ unsigned int reserved_0:1; /**< \brief \internal Reserved */
+ unsigned int TL1:1; /**< \brief [1:1] Capture of Trigger Line 1 (rh) */
+ unsigned int TL2:1; /**< \brief [2:2] Capture of Trigger Line 2 (rh) */
+ unsigned int TL3:1; /**< \brief [3:3] Capture of Trigger Line 3 (rh) */
+ unsigned int TL4:1; /**< \brief [4:4] Capture of Trigger Line 4 (rh) */
+ unsigned int TL5:1; /**< \brief [5:5] Capture of Trigger Line 5 (rh) */
+ unsigned int TL6:1; /**< \brief [6:6] Capture of Trigger Line 6 (rh) */
+ unsigned int TL7:1; /**< \brief [7:7] Capture of Trigger Line 7 (rh) */
+ unsigned int reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_CBS_TCTL_Bits;
+
+/** \brief TG Input Pins Routing */
+typedef struct _Ifx_CBS_TIPR_Bits
+{
+ unsigned int PIN0:4; /**< \brief [3:0] Trigger Pin 0 to Trigger Line Routing (rw) */
+ unsigned int PIN1:4; /**< \brief [7:4] Trigger Pin 1 to Trigger Line Routing (rw) */
+ unsigned int PIN2:4; /**< \brief [11:8] Trigger Pin 2 to Trigger Line Routing (rw) */
+ unsigned int PIN3:4; /**< \brief [15:12] Trigger Pin 3 to Trigger Line Routing (rw) */
+ unsigned int PIN4:4; /**< \brief [19:16] Trigger Pin 4 to Trigger Line Routing (rw) */
+ unsigned int PIN5:4; /**< \brief [23:20] Trigger Pin 5 to Trigger Line Routing (rw) */
+ unsigned int PIN6:4; /**< \brief [27:24] Trigger Pin 6 to Trigger Line Routing (rw) */
+ unsigned int PIN7:4; /**< \brief [31:28] Trigger Pin 7 to Trigger Line Routing (rw) */
+} Ifx_CBS_TIPR_Bits;
+
+/** \brief TG Line 1 Suspend Targets */
+typedef struct _Ifx_CBS_TL1ST_Bits
+{
+ unsigned int C0:1; /**< \brief [0:0] CPU0 as Suspend Target (rw) */
+ unsigned int C1:1; /**< \brief [1:1] CPU1 as Suspend Target (rw) */
+ unsigned int C2:1; /**< \brief [2:2] CPU2 as Suspend Target (rw) */
+ unsigned int reserved_3:25; /**< \brief \internal Reserved */
+ unsigned int HSS:1; /**< \brief [28:28] HSSL as Suspend Target (rw) */
+ unsigned int DMA:1; /**< \brief [29:29] DMA as Suspend Target (rw) */
+ unsigned int reserved_30:1; /**< \brief \internal Reserved */
+ unsigned int HSM:1; /**< \brief [31:31] as Suspend Target (rw) */
+} Ifx_CBS_TL1ST_Bits;
+
+/** \brief TG Line Control */
+typedef struct _Ifx_CBS_TLC_Bits
+{
+ unsigned int reserved_0:4; /**< \brief \internal Reserved */
+ unsigned int TLSP1:4; /**< \brief [7:4] TG Line Signal Processing (rw) */
+ unsigned int TLSP2:4; /**< \brief [11:8] TG Line Signal Processing (rw) */
+ unsigned int TLSP3:4; /**< \brief [15:12] TG Line Signal Processing (rw) */
+ unsigned int TLSP4:4; /**< \brief [19:16] TG Line Signal Processing (rw) */
+ unsigned int TLSP5:4; /**< \brief [23:20] TG Line Signal Processing (rw) */
+ unsigned int TLSP6:4; /**< \brief [27:24] TG Line Signal Processing (rw) */
+ unsigned int TLSP7:4; /**< \brief [31:28] TG Line Signal Processing (rw) */
+} Ifx_CBS_TLC_Bits;
+
+/** \brief TG Line Counter Control */
+typedef struct _Ifx_CBS_TLCC_Bits
+{
+ unsigned int TGL:4; /**< \brief [3:0] Trigger Line to Counter Routing (rw) */
+ unsigned int LE:3; /**< \brief [6:4] Level or Edge Counting (rw) */
+ unsigned int reserved_7:1; /**< \brief \internal Reserved */
+ unsigned int CLR:2; /**< \brief [9:8] Clear and Enable Counter(s) (w) */
+ unsigned int reserved_10:2; /**< \brief \internal Reserved */
+ unsigned int STOP:2; /**< \brief [13:12] Stop Counter(s) (w) */
+ unsigned int reserved_14:18; /**< \brief \internal Reserved */
+} Ifx_CBS_TLCC_Bits;
+
+/** \brief TG Line Capture and Hold Enable */
+typedef struct _Ifx_CBS_TLCHE_Bits
+{
+ unsigned int reserved_0:1; /**< \brief \internal Reserved */
+ unsigned int TL1:1; /**< \brief [1:1] Capture and Hold Enable for Trigger Line 1 (rw) */
+ unsigned int TL2:1; /**< \brief [2:2] Capture and Hold Enable for Trigger Line 2 (rw) */
+ unsigned int TL3:1; /**< \brief [3:3] Capture and Hold Enable for Trigger Line 3 (rw) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_CBS_TLCHE_Bits;
+
+/** \brief TG Line Capture and Hold Clear */
+typedef struct _Ifx_CBS_TLCHS_Bits
+{
+ unsigned int reserved_0:1; /**< \brief \internal Reserved */
+ unsigned int TL1:1; /**< \brief [1:1] Capture and Hold Clear for Trigger Line 1 (w) */
+ unsigned int TL2:1; /**< \brief [2:2] Capture and Hold Clear for Trigger Line 2 (w) */
+ unsigned int TL3:1; /**< \brief [3:3] Capture and Hold Clear for Trigger Line 3 (w) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_CBS_TLCHS_Bits;
+
+/** \brief TG Line Counter Value */
+typedef struct _Ifx_CBS_TLCV_Bits
+{
+ unsigned int CV:31; /**< \brief [30:0] Count Value (rh) */
+ unsigned int SO:1; /**< \brief [31:31] Sticky Overflow Bit (rh) */
+} Ifx_CBS_TLCV_Bits;
+
+/** \brief TG Line State */
+typedef struct _Ifx_CBS_TLS_Bits
+{
+ unsigned int reserved_0:1; /**< \brief \internal Reserved */
+ unsigned int TL1:1; /**< \brief [1:1] Current State of Trigger Line 1 (rh) */
+ unsigned int TL2:1; /**< \brief [2:2] Current State of Trigger Line 2 (rh) */
+ unsigned int TL3:1; /**< \brief [3:3] Current State of Trigger Line 3 (rh) */
+ unsigned int TL4:1; /**< \brief [4:4] Current State of Trigger Line 4 (rh) */
+ unsigned int TL5:1; /**< \brief [5:5] Current State of Trigger Line 5 (rh) */
+ unsigned int TL6:1; /**< \brief [6:6] Current State of Trigger Line 6 (rh) */
+ unsigned int TL7:1; /**< \brief [7:7] Current State of Trigger Line 7 (rh) */
+ unsigned int reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_CBS_TLS_Bits;
+
+/** \brief TG Line Timer */
+typedef struct _Ifx_CBS_TLT_Bits
+{
+ unsigned int TGL:4; /**< \brief [3:0] Timer to Trigger Line Routing (rw) */
+ unsigned int VTZ:1; /**< \brief [4:4] TG Line Value when Timer Value is Zero (rw) */
+ unsigned int reserved_5:11; /**< \brief \internal Reserved */
+ unsigned int TIM:16; /**< \brief [31:16] Timer Value (rwh) */
+} Ifx_CBS_TLT_Bits;
+
+/** \brief TG Lines for Trigger to Host */
+typedef struct _Ifx_CBS_TLTTH_Bits
+{
+ unsigned int reserved_0:2; /**< \brief \internal Reserved */
+ unsigned int TL1:2; /**< \brief [3:2] TG Line Enabling for Trigger to Host (TRIG) (rw) */
+ unsigned int TL2:2; /**< \brief [5:4] TG Line Enabling for Trigger to Host (TRIG) (rw) */
+ unsigned int TL3:2; /**< \brief [7:6] TG Line Enabling for Trigger to Host (TRIG) (rw) */
+ unsigned int TL4:2; /**< \brief [9:8] TG Line Enabling for Trigger to Host (TRIG) (rw) */
+ unsigned int TL5:2; /**< \brief [11:10] TG Line Enabling for Trigger to Host (TRIG) (rw) */
+ unsigned int TL6:2; /**< \brief [13:12] TG Line Enabling for Trigger to Host (TRIG) (rw) */
+ unsigned int TL7:2; /**< \brief [15:14] TG Line Enabling for Trigger to Host (TRIG) (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CBS_TLTTH_Bits;
+
+/** \brief TG Output Pins Pulse Stretcher */
+typedef struct _Ifx_CBS_TOPPS_Bits
+{
+ unsigned int PIN0:2; /**< \brief [1:0] Pulse Stretch Control for Trigger Pin 0 (rw) */
+ unsigned int PIN1:2; /**< \brief [3:2] Pulse Stretch Control for Trigger Pin 1 (rw) */
+ unsigned int PIN2:2; /**< \brief [5:4] Pulse Stretch Control for Trigger Pin 2 (rw) */
+ unsigned int PIN3:2; /**< \brief [7:6] Pulse Stretch Control for Trigger Pin 3 (rw) */
+ unsigned int PIN4:2; /**< \brief [9:8] Pulse Stretch Control for Trigger Pin 4 (rw) */
+ unsigned int PIN5:2; /**< \brief [11:10] Pulse Stretch Control for Trigger Pin 5 (rw) */
+ unsigned int PIN6:2; /**< \brief [13:12] Pulse Stretch Control for Trigger Pin 6 (rw) */
+ unsigned int PIN7:2; /**< \brief [15:14] Pulse Stretch Control for Trigger Pin 7 (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CBS_TOPPS_Bits;
+
+/** \brief TG Output Pins Routing */
+typedef struct _Ifx_CBS_TOPR_Bits
+{
+ unsigned int PIN0:4; /**< \brief [3:0] Trigger Line to Trigger Pin 0 Routing (rw) */
+ unsigned int PIN1:4; /**< \brief [7:4] Trigger Line to Trigger Pin 1 Routing (rw) */
+ unsigned int PIN2:4; /**< \brief [11:8] Trigger Line to Trigger Pin 2 Routing (rw) */
+ unsigned int PIN3:4; /**< \brief [15:12] Trigger Line to Trigger Pin 3 Routing (rw) */
+ unsigned int PIN4:4; /**< \brief [19:16] Trigger Line to Trigger Pin 4 Routing (rw) */
+ unsigned int PIN5:4; /**< \brief [23:20] Trigger Line to Trigger Pin 5 Routing (rw) */
+ unsigned int PIN6:4; /**< \brief [27:24] Trigger Line to Trigger Pin 6 Routing (rw) */
+ unsigned int PIN7:4; /**< \brief [31:28] Trigger Line to Trigger Pin 7 Routing (rw) */
+} Ifx_CBS_TOPR_Bits;
+
+/** \brief TG Routing for CPU */
+typedef struct _Ifx_CBS_TRC_Bits
+{
+ unsigned int HALT:4; /**< \brief [3:0] HALT to Trigger Line Routing (rw) */
+ unsigned int BRKOUT:4; /**< \brief [7:4] BRKOUT to Trigger Line Routing (rw) */
+ unsigned int BT1:1; /**< \brief [8:8] BRKOUT to Trigger Line 1 Routing (rw) */
+ unsigned int reserved_9:11; /**< \brief \internal Reserved */
+ unsigned int BRKIN:4; /**< \brief [23:20] Trigger Line to BRKIN Routing (rw) */
+ unsigned int SUSIN:4; /**< \brief [27:24] Trigger Line to SUSIN Routing (rw) */
+ unsigned int reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_CBS_TRC_Bits;
+
+/** \brief TG Routing Events of CPU */
+typedef struct _Ifx_CBS_TREC_Bits
+{
+ unsigned int TR0EV:4; /**< \brief [3:0] TRxEVT to Trigger Line Routing (rw) */
+ unsigned int reserved_4:4; /**< \brief \internal Reserved */
+ unsigned int TR2EV:4; /**< \brief [11:8] TRxEVT to Trigger Line Routing (rw) */
+ unsigned int reserved_12:4; /**< \brief \internal Reserved */
+ unsigned int TR4EV:4; /**< \brief [19:16] TRxEVT to Trigger Line Routing (rw) */
+ unsigned int reserved_20:4; /**< \brief \internal Reserved */
+ unsigned int TR6EV:4; /**< \brief [27:24] TRxEVT to Trigger Line Routing (rw) */
+ unsigned int reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_CBS_TREC_Bits;
+
+/** \brief Trigger to Host Register */
+typedef struct _Ifx_CBS_TRIG_Bits
+{
+ unsigned int TRGx_0:1; /**< \brief [0:0] Service Request Bits (rh) */
+ unsigned int TRGx_1:1; /**< \brief [1:1] Service Request Bits (rh) */
+ unsigned int TRGx_2:1; /**< \brief [2:2] Service Request Bits (rh) */
+ unsigned int TRGx_3:1; /**< \brief [3:3] Service Request Bits (rh) */
+ unsigned int TRGx_4:1; /**< \brief [4:4] Service Request Bits (rh) */
+ unsigned int TRGx_5:1; /**< \brief [5:5] Service Request Bits (rh) */
+ unsigned int TRGx_6:1; /**< \brief [6:6] Service Request Bits (rh) */
+ unsigned int TRGx_7:1; /**< \brief [7:7] Service Request Bits (rh) */
+ unsigned int TRGx_8:1; /**< \brief [8:8] Service Request Bits (rh) */
+ unsigned int TRGx_9:1; /**< \brief [9:9] Service Request Bits (rh) */
+ unsigned int TRGx_10:1; /**< \brief [10:10] Service Request Bits (rh) */
+ unsigned int TRGx_11:1; /**< \brief [11:11] Service Request Bits (rh) */
+ unsigned int TRGx_12:1; /**< \brief [12:12] Service Request Bits (rh) */
+ unsigned int TRGx_13:1; /**< \brief [13:13] Service Request Bits (rh) */
+ unsigned int TRGx_14:1; /**< \brief [14:14] Service Request Bits (rh) */
+ unsigned int TRGx_15:1; /**< \brief [15:15] Service Request Bits (rh) */
+ unsigned int TRGx_16:1; /**< \brief [16:16] Service Request Bits (rh) */
+ unsigned int TRGx_17:1; /**< \brief [17:17] Service Request Bits (rh) */
+ unsigned int TRGx_18:1; /**< \brief [18:18] Service Request Bits (rh) */
+ unsigned int TRGx_19:1; /**< \brief [19:19] Service Request Bits (rh) */
+ unsigned int TRGx_20:1; /**< \brief [20:20] Service Request Bits (rh) */
+ unsigned int TRGx_21:1; /**< \brief [21:21] Service Request Bits (rh) */
+ unsigned int TRGx_22:1; /**< \brief [22:22] Service Request Bits (rh) */
+ unsigned int TRGx_23:1; /**< \brief [23:23] Service Request Bits (rh) */
+ unsigned int x:8; /**< \brief [31:24] TRIG register number (rh) */
+} Ifx_CBS_TRIG_Bits;
+
+/** \brief Clear Trigger to Host Register */
+typedef struct _Ifx_CBS_TRIGC_Bits
+{
+ unsigned int TRGx_0:1; /**< \brief [0:0] Request Bits of most important register TRIGx (rh) */
+ unsigned int TRGx_1:1; /**< \brief [1:1] Request Bits of most important register TRIGx (rh) */
+ unsigned int TRGx_2:1; /**< \brief [2:2] Request Bits of most important register TRIGx (rh) */
+ unsigned int TRGx_3:1; /**< \brief [3:3] Request Bits of most important register TRIGx (rh) */
+ unsigned int TRGx_4:1; /**< \brief [4:4] Request Bits of most important register TRIGx (rh) */
+ unsigned int TRGx_5:1; /**< \brief [5:5] Request Bits of most important register TRIGx (rh) */
+ unsigned int TRGx_6:1; /**< \brief [6:6] Request Bits of most important register TRIGx (rh) */
+ unsigned int TRGx_7:1; /**< \brief [7:7] Request Bits of most important register TRIGx (rh) */
+ unsigned int TRGx_8:1; /**< \brief [8:8] Request Bits of most important register TRIGx (rh) */
+ unsigned int TRGx_9:1; /**< \brief [9:9] Request Bits of most important register TRIGx (rh) */
+ unsigned int TRGx_10:1; /**< \brief [10:10] Request Bits of most important register TRIGx (rh) */
+ unsigned int TRGx_11:1; /**< \brief [11:11] Request Bits of most important register TRIGx (rh) */
+ unsigned int TRGx_12:1; /**< \brief [12:12] Request Bits of most important register TRIGx (rh) */
+ unsigned int TRGx_13:1; /**< \brief [13:13] Request Bits of most important register TRIGx (rh) */
+ unsigned int TRGx_14:1; /**< \brief [14:14] Request Bits of most important register TRIGx (rh) */
+ unsigned int TRGx_15:1; /**< \brief [15:15] Request Bits of most important register TRIGx (rh) */
+ unsigned int TRGx_16:1; /**< \brief [16:16] Request Bits of most important register TRIGx (rh) */
+ unsigned int TRGx_17:1; /**< \brief [17:17] Request Bits of most important register TRIGx (rh) */
+ unsigned int TRGx_18:1; /**< \brief [18:18] Request Bits of most important register TRIGx (rh) */
+ unsigned int TRGx_19:1; /**< \brief [19:19] Request Bits of most important register TRIGx (rh) */
+ unsigned int TRGx_20:1; /**< \brief [20:20] Request Bits of most important register TRIGx (rh) */
+ unsigned int TRGx_21:1; /**< \brief [21:21] Request Bits of most important register TRIGx (rh) */
+ unsigned int TRGx_22:1; /**< \brief [22:22] Request Bits of most important register TRIGx (rh) */
+ unsigned int TRGx_23:1; /**< \brief [23:23] Request Bits of most important register TRIGx (rh) */
+ unsigned int x:8; /**< \brief [31:24] Index of most important register TRIGx (rh) */
+} Ifx_CBS_TRIGC_Bits;
+
+/** \brief Set Trigger to Host Register */
+typedef struct _Ifx_CBS_TRIGS_Bits
+{
+ unsigned int BITNUM:13; /**< \brief [12:0] Service Request Bit Number to Set (w) */
+ unsigned int reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_CBS_TRIGS_Bits;
+
+/** \brief TG Routing for MCDS Control */
+typedef struct _Ifx_CBS_TRMC_Bits
+{
+ unsigned int reserved_0:4; /**< \brief \internal Reserved */
+ unsigned int BRKOUT:4; /**< \brief [7:4] MCDS break_out to Trigger Line Routing (rw) */
+ unsigned int SUSOUT:4; /**< \brief [11:8] MCDS suspend_out to Trigger Line Routing (rw) */
+ unsigned int reserved_12:8; /**< \brief \internal Reserved */
+ unsigned int BRKIN:4; /**< \brief [23:20] Trigger Line to MCDS break_in Routing (rw) */
+ unsigned int reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CBS_TRMC_Bits;
+
+/** \brief TG Routing for MCDS Triggers */
+typedef struct _Ifx_CBS_TRMT_Bits
+{
+ unsigned int TG0:4; /**< \brief [3:0] MCDS trig_out 0 to Trigger Line Routing (rw) */
+ unsigned int TG1:4; /**< \brief [7:4] MCDS trig_out 1 to Trigger Line Routing (rw) */
+ unsigned int TG2:4; /**< \brief [11:8] MCDS trig_out 2 to Trigger Line Routing (rw) */
+ unsigned int TG3:4; /**< \brief [15:12] MCDS trig_out 3 to Trigger Line Routing (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CBS_TRMT_Bits;
+
+/** \brief TG Routing for Special Signals */
+typedef struct _Ifx_CBS_TRSS_Bits
+{
+ unsigned int TT:4; /**< \brief [3:0] Trigger Line to Cerberus’ Triggered Transfer Routing (rw) */
+ unsigned int reserved_4:12; /**< \brief \internal Reserved */
+ unsigned int SRC0:4; /**< \brief [19:16] Trigger Line to SRC0 Interrupt Routing (rw) */
+ unsigned int SRC1:4; /**< \brief [23:20] Trigger Line to SRC1 Interrupt Routing (rw) */
+ unsigned int reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CBS_TRSS_Bits;
+
+/** \brief TG Routing for OTGB Bits [15:8] */
+typedef struct _Ifx_CBS_TRTGB_H_Bits
+{
+ unsigned int TG8:4; /**< \brief [3:0] (rw) */
+ unsigned int TG9:4; /**< \brief [7:4] (rw) */
+ unsigned int TG10:4; /**< \brief [11:8] (rw) */
+ unsigned int TG11:4; /**< \brief [15:12] (rw) */
+ unsigned int TG12:4; /**< \brief [19:16] (rw) */
+ unsigned int TG13:4; /**< \brief [23:20] (rw) */
+ unsigned int TG14:4; /**< \brief [27:24] (rw) */
+ unsigned int TG15:4; /**< \brief [31:28] (rw) */
+} Ifx_CBS_TRTGB_H_Bits;
+
+/** \brief TG Routing for OTGB Bits [7:0] */
+typedef struct _Ifx_CBS_TRTGB_L_Bits
+{
+ unsigned int TG0:4; /**< \brief [3:0] (rw) */
+ unsigned int TG1:4; /**< \brief [7:4] (rw) */
+ unsigned int TG2:4; /**< \brief [11:8] (rw) */
+ unsigned int TG3:4; /**< \brief [15:12] (rw) */
+ unsigned int TG4:4; /**< \brief [19:16] (rw) */
+ unsigned int TG5:4; /**< \brief [23:20] (rw) */
+ unsigned int TG6:4; /**< \brief [27:24] (rw) */
+ unsigned int TG7:4; /**< \brief [31:28] (rw) */
+} Ifx_CBS_TRTGB_L_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Cbs_union
+ * \{ */
+
+/** \brief Communication Mode Data Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_COMDATA_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_COMDATA;
+
+/** \brief Internally Controlled Trace Source Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_ICTSA_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_ICTSA;
+
+/** \brief Internally Controlled Trace Destination Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_ICTTA_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_ICTTA;
+
+/** \brief Internal Mode Status and Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_INTMOD_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_INTMOD;
+
+/** \brief IOClient Status and Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_IOSR_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_IOSR;
+
+/** \brief Module Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_JDPID_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_JDPID;
+
+/** \brief JTAG Device Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_JTAGID_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_JTAGID;
+
+/** \brief OSCU Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_OCNTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_OCNTRL;
+
+/** \brief OCDS Enable Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_OEC_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_OEC;
+
+/** \brief OCDS Interface Mode Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_OIFM_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_OIFM;
+
+/** \brief OSCU Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_OSTATE_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_OSTATE;
+
+/** \brief TG Capture for Cores - BRKOUT */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_TCCB_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_TCCB;
+
+/** \brief TG Capture for Cores - HALT */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_TCCH_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_TCCH;
+
+/** \brief TG Capture for TG Input Pins */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_TCIP_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_TCIP;
+
+/** \brief TG Capture for MCDS */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_TCM_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_TCM;
+
+/** \brief TG Capture for OTGB0/1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_TCTGB_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_TCTGB;
+
+/** \brief TG Capture for TG Lines */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_TCTL_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_TCTL;
+
+/** \brief TG Input Pins Routing */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_TIPR_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_TIPR;
+
+/** \brief TG Line 1 Suspend Targets */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_TL1ST_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_TL1ST;
+
+/** \brief TG Line Control */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_TLC_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_TLC;
+
+/** \brief TG Line Counter Control */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_TLCC_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_TLCC;
+
+/** \brief TG Line Capture and Hold Enable */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_TLCHE_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_TLCHE;
+
+/** \brief TG Line Capture and Hold Clear */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_TLCHS_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_TLCHS;
+
+/** \brief TG Line Counter Value */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_TLCV_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_TLCV;
+
+/** \brief TG Line State */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_TLS_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_TLS;
+
+/** \brief TG Line Timer */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_TLT_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_TLT;
+
+/** \brief TG Lines for Trigger to Host */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_TLTTH_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_TLTTH;
+
+/** \brief TG Output Pins Pulse Stretcher */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_TOPPS_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_TOPPS;
+
+/** \brief TG Output Pins Routing */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_TOPR_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_TOPR;
+
+/** \brief TG Routing for CPU */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_TRC_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_TRC;
+
+/** \brief TG Routing Events of CPU */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_TREC_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_TREC;
+
+/** \brief Trigger to Host Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_TRIG_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_TRIG;
+
+/** \brief Clear Trigger to Host Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_TRIGC_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_TRIGC;
+
+/** \brief Set Trigger to Host Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_TRIGS_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_TRIGS;
+
+/** \brief TG Routing for MCDS Control */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_TRMC_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_TRMC;
+
+/** \brief TG Routing for MCDS Triggers */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_TRMT_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_TRMT;
+
+/** \brief TG Routing for Special Signals */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_TRSS_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_TRSS;
+
+/** \brief TG Routing for OTGB Bits [15:8] */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_TRTGB_H_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_TRTGB_H;
+
+/** \brief TG Routing for OTGB Bits [7:0] */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CBS_TRTGB_L_Bits B; /**< \brief Bitfield access */
+} Ifx_CBS_TRTGB_L;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Cbs_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L1
+ * \{ */
+
+/** \brief TG Routing for OTGB */
+typedef volatile struct _Ifx_CBS_TRTGB
+{
+ Ifx_CBS_TRTGB_L L; /**< \brief 0, TG Routing for OTGB Bits [7:0] */
+ Ifx_CBS_TRTGB_H H; /**< \brief 4, TG Routing for OTGB Bits [15:8] */
+} Ifx_CBS_TRTGB;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Cbs_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief CBS object */
+typedef volatile struct _Ifx_CBS
+{
+ unsigned char reserved_0[8]; /**< \brief 0, \internal Reserved */
+ Ifx_CBS_JDPID JDPID; /**< \brief 8, Module Identification Register */
+ Ifx_CBS_OIFM OIFM; /**< \brief C, OCDS Interface Mode Register */
+ Ifx_CBS_TIPR TIPR; /**< \brief 10, TG Input Pins Routing */
+ Ifx_CBS_TOPR TOPR; /**< \brief 14, TG Output Pins Routing */
+ Ifx_CBS_TOPPS TOPPS; /**< \brief 18, TG Output Pins Pulse Stretcher */
+ Ifx_CBS_TCIP TCIP; /**< \brief 1C, TG Capture for TG Input Pins */
+ Ifx_CBS_TRC TRC[2]; /**< \brief 20, TG Routing for CPU */
+ unsigned char reserved_28[20]; /**< \brief 28, \internal Reserved */
+ Ifx_CBS_TRMC TRMC; /**< \brief 3C, TG Routing for MCDS Control */
+ Ifx_CBS_TLCC TLCC[2]; /**< \brief 40, TG Line Counter Control */
+ unsigned char reserved_48[8]; /**< \brief 48, \internal Reserved */
+ Ifx_CBS_TLCV TLCV[2]; /**< \brief 50, TG Line Counter Value */
+ unsigned char reserved_58[8]; /**< \brief 58, \internal Reserved */
+ Ifx_CBS_TRSS TRSS; /**< \brief 60, TG Routing for Special Signals */
+ Ifx_CBS_JTAGID JTAGID; /**< \brief 64, JTAG Device Identification Register */
+ Ifx_CBS_COMDATA COMDATA; /**< \brief 68, Communication Mode Data Register */
+ Ifx_CBS_IOSR IOSR; /**< \brief 6C, IOClient Status and Control Register */
+ Ifx_CBS_TLS TLS; /**< \brief 70, TG Line State */
+ Ifx_CBS_TCTL TCTL; /**< \brief 74, TG Capture for TG Lines */
+ Ifx_CBS_OEC OEC; /**< \brief 78, OCDS Enable Control Register */
+ Ifx_CBS_OCNTRL OCNTRL; /**< \brief 7C, OSCU Control Register */
+ Ifx_CBS_OSTATE OSTATE; /**< \brief 80, OSCU Status Register */
+ Ifx_CBS_INTMOD INTMOD; /**< \brief 84, Internal Mode Status and Control Register */
+ Ifx_CBS_ICTSA ICTSA; /**< \brief 88, Internally Controlled Trace Source Register */
+ Ifx_CBS_ICTTA ICTTA; /**< \brief 8C, Internally Controlled Trace Destination Register */
+ Ifx_CBS_TLC TLC; /**< \brief 90, TG Line Control */
+ Ifx_CBS_TL1ST TL1ST; /**< \brief 94, TG Line 1 Suspend Targets */
+ Ifx_CBS_TLCHE TLCHE; /**< \brief 98, TG Line Capture and Hold Enable */
+ Ifx_CBS_TLCHS TLCHS; /**< \brief 9C, TG Line Capture and Hold Clear */
+ Ifx_CBS_TRIGS TRIGS; /**< \brief A0, Set Trigger to Host Register */
+ Ifx_CBS_TRIGC TRIGC; /**< \brief A4, Clear Trigger to Host Register */
+ Ifx_CBS_TLT TLT; /**< \brief A8, TG Line Timer */
+ Ifx_CBS_TLTTH TLTTH; /**< \brief AC, TG Lines for Trigger to Host */
+ Ifx_CBS_TCCB TCCB; /**< \brief B0, TG Capture for Cores - BRKOUT */
+ Ifx_CBS_TCCH TCCH; /**< \brief B4, TG Capture for Cores - HALT */
+ Ifx_CBS_TCTGB TCTGB; /**< \brief B8, TG Capture for OTGB0/1 */
+ Ifx_CBS_TCM TCM; /**< \brief BC, TG Capture for MCDS */
+ Ifx_CBS_TREC TREC[2]; /**< \brief C0, TG Routing Events of CPU */
+ unsigned char reserved_C8[20]; /**< \brief C8, \internal Reserved */
+ Ifx_CBS_TRMT TRMT; /**< \brief DC, TG Routing for MCDS Triggers */
+ Ifx_CBS_TRTGB TRTGB[2]; /**< \brief E0, TG Routing for OTGB */
+ unsigned char reserved_F0[16]; /**< \brief F0, \internal Reserved */
+ Ifx_CBS_TRIG TRIG[22]; /**< \brief 100, Trigger to Host Register */
+ unsigned char reserved_158[168]; /**< \brief 158, \internal Reserved */
+} Ifx_CBS;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXCBS_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCcu6_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCcu6_bf.h
new file mode 100644
index 0000000..8b4ac24
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCcu6_bf.h
@@ -0,0 +1,2394 @@
+/**
+ * \file IfxCcu6_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Ccu6_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Ccu6
+ *
+ */
+#ifndef IFXCCU6_BF_H
+#define IFXCCU6_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Ccu6_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN0 */
+#define IFX_CCU6_ACCEN0_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN0 */
+#define IFX_CCU6_ACCEN0_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN0 */
+#define IFX_CCU6_ACCEN0_EN0_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN10 */
+#define IFX_CCU6_ACCEN0_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN10 */
+#define IFX_CCU6_ACCEN0_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN10 */
+#define IFX_CCU6_ACCEN0_EN10_OFF (10u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN11 */
+#define IFX_CCU6_ACCEN0_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN11 */
+#define IFX_CCU6_ACCEN0_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN11 */
+#define IFX_CCU6_ACCEN0_EN11_OFF (11u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN12 */
+#define IFX_CCU6_ACCEN0_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN12 */
+#define IFX_CCU6_ACCEN0_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN12 */
+#define IFX_CCU6_ACCEN0_EN12_OFF (12u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN13 */
+#define IFX_CCU6_ACCEN0_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN13 */
+#define IFX_CCU6_ACCEN0_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN13 */
+#define IFX_CCU6_ACCEN0_EN13_OFF (13u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN14 */
+#define IFX_CCU6_ACCEN0_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN14 */
+#define IFX_CCU6_ACCEN0_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN14 */
+#define IFX_CCU6_ACCEN0_EN14_OFF (14u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN15 */
+#define IFX_CCU6_ACCEN0_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN15 */
+#define IFX_CCU6_ACCEN0_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN15 */
+#define IFX_CCU6_ACCEN0_EN15_OFF (15u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN16 */
+#define IFX_CCU6_ACCEN0_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN16 */
+#define IFX_CCU6_ACCEN0_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN16 */
+#define IFX_CCU6_ACCEN0_EN16_OFF (16u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN17 */
+#define IFX_CCU6_ACCEN0_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN17 */
+#define IFX_CCU6_ACCEN0_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN17 */
+#define IFX_CCU6_ACCEN0_EN17_OFF (17u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN18 */
+#define IFX_CCU6_ACCEN0_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN18 */
+#define IFX_CCU6_ACCEN0_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN18 */
+#define IFX_CCU6_ACCEN0_EN18_OFF (18u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN19 */
+#define IFX_CCU6_ACCEN0_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN19 */
+#define IFX_CCU6_ACCEN0_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN19 */
+#define IFX_CCU6_ACCEN0_EN19_OFF (19u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN1 */
+#define IFX_CCU6_ACCEN0_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN1 */
+#define IFX_CCU6_ACCEN0_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN1 */
+#define IFX_CCU6_ACCEN0_EN1_OFF (1u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN20 */
+#define IFX_CCU6_ACCEN0_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN20 */
+#define IFX_CCU6_ACCEN0_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN20 */
+#define IFX_CCU6_ACCEN0_EN20_OFF (20u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN21 */
+#define IFX_CCU6_ACCEN0_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN21 */
+#define IFX_CCU6_ACCEN0_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN21 */
+#define IFX_CCU6_ACCEN0_EN21_OFF (21u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN22 */
+#define IFX_CCU6_ACCEN0_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN22 */
+#define IFX_CCU6_ACCEN0_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN22 */
+#define IFX_CCU6_ACCEN0_EN22_OFF (22u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN23 */
+#define IFX_CCU6_ACCEN0_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN23 */
+#define IFX_CCU6_ACCEN0_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN23 */
+#define IFX_CCU6_ACCEN0_EN23_OFF (23u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN24 */
+#define IFX_CCU6_ACCEN0_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN24 */
+#define IFX_CCU6_ACCEN0_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN24 */
+#define IFX_CCU6_ACCEN0_EN24_OFF (24u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN25 */
+#define IFX_CCU6_ACCEN0_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN25 */
+#define IFX_CCU6_ACCEN0_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN25 */
+#define IFX_CCU6_ACCEN0_EN25_OFF (25u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN26 */
+#define IFX_CCU6_ACCEN0_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN26 */
+#define IFX_CCU6_ACCEN0_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN26 */
+#define IFX_CCU6_ACCEN0_EN26_OFF (26u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN27 */
+#define IFX_CCU6_ACCEN0_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN27 */
+#define IFX_CCU6_ACCEN0_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN27 */
+#define IFX_CCU6_ACCEN0_EN27_OFF (27u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN28 */
+#define IFX_CCU6_ACCEN0_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN28 */
+#define IFX_CCU6_ACCEN0_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN28 */
+#define IFX_CCU6_ACCEN0_EN28_OFF (28u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN29 */
+#define IFX_CCU6_ACCEN0_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN29 */
+#define IFX_CCU6_ACCEN0_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN29 */
+#define IFX_CCU6_ACCEN0_EN29_OFF (29u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN2 */
+#define IFX_CCU6_ACCEN0_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN2 */
+#define IFX_CCU6_ACCEN0_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN2 */
+#define IFX_CCU6_ACCEN0_EN2_OFF (2u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN30 */
+#define IFX_CCU6_ACCEN0_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN30 */
+#define IFX_CCU6_ACCEN0_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN30 */
+#define IFX_CCU6_ACCEN0_EN30_OFF (30u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN31 */
+#define IFX_CCU6_ACCEN0_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN31 */
+#define IFX_CCU6_ACCEN0_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN31 */
+#define IFX_CCU6_ACCEN0_EN31_OFF (31u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN3 */
+#define IFX_CCU6_ACCEN0_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN3 */
+#define IFX_CCU6_ACCEN0_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN3 */
+#define IFX_CCU6_ACCEN0_EN3_OFF (3u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN4 */
+#define IFX_CCU6_ACCEN0_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN4 */
+#define IFX_CCU6_ACCEN0_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN4 */
+#define IFX_CCU6_ACCEN0_EN4_OFF (4u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN5 */
+#define IFX_CCU6_ACCEN0_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN5 */
+#define IFX_CCU6_ACCEN0_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN5 */
+#define IFX_CCU6_ACCEN0_EN5_OFF (5u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN6 */
+#define IFX_CCU6_ACCEN0_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN6 */
+#define IFX_CCU6_ACCEN0_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN6 */
+#define IFX_CCU6_ACCEN0_EN6_OFF (6u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN7 */
+#define IFX_CCU6_ACCEN0_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN7 */
+#define IFX_CCU6_ACCEN0_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN7 */
+#define IFX_CCU6_ACCEN0_EN7_OFF (7u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN8 */
+#define IFX_CCU6_ACCEN0_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN8 */
+#define IFX_CCU6_ACCEN0_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN8 */
+#define IFX_CCU6_ACCEN0_EN8_OFF (8u)
+
+/** \brief Length for Ifx_CCU6_ACCEN0_Bits.EN9 */
+#define IFX_CCU6_ACCEN0_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ACCEN0_Bits.EN9 */
+#define IFX_CCU6_ACCEN0_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ACCEN0_Bits.EN9 */
+#define IFX_CCU6_ACCEN0_EN9_OFF (9u)
+
+/** \brief Length for Ifx_CCU6_CC60R_Bits.CCV */
+#define IFX_CCU6_CC60R_CCV_LEN (16u)
+
+/** \brief Mask for Ifx_CCU6_CC60R_Bits.CCV */
+#define IFX_CCU6_CC60R_CCV_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CCU6_CC60R_Bits.CCV */
+#define IFX_CCU6_CC60R_CCV_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_CC60SR_Bits.CCS */
+#define IFX_CCU6_CC60SR_CCS_LEN (16u)
+
+/** \brief Mask for Ifx_CCU6_CC60SR_Bits.CCS */
+#define IFX_CCU6_CC60SR_CCS_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CCU6_CC60SR_Bits.CCS */
+#define IFX_CCU6_CC60SR_CCS_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_CC61R_Bits.CCV */
+#define IFX_CCU6_CC61R_CCV_LEN (16u)
+
+/** \brief Mask for Ifx_CCU6_CC61R_Bits.CCV */
+#define IFX_CCU6_CC61R_CCV_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CCU6_CC61R_Bits.CCV */
+#define IFX_CCU6_CC61R_CCV_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_CC61SR_Bits.CCS */
+#define IFX_CCU6_CC61SR_CCS_LEN (16u)
+
+/** \brief Mask for Ifx_CCU6_CC61SR_Bits.CCS */
+#define IFX_CCU6_CC61SR_CCS_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CCU6_CC61SR_Bits.CCS */
+#define IFX_CCU6_CC61SR_CCS_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_CC62R_Bits.CCV */
+#define IFX_CCU6_CC62R_CCV_LEN (16u)
+
+/** \brief Mask for Ifx_CCU6_CC62R_Bits.CCV */
+#define IFX_CCU6_CC62R_CCV_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CCU6_CC62R_Bits.CCV */
+#define IFX_CCU6_CC62R_CCV_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_CC62SR_Bits.CCS */
+#define IFX_CCU6_CC62SR_CCS_LEN (16u)
+
+/** \brief Mask for Ifx_CCU6_CC62SR_Bits.CCS */
+#define IFX_CCU6_CC62SR_CCS_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CCU6_CC62SR_Bits.CCS */
+#define IFX_CCU6_CC62SR_CCS_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_CC63R_Bits.CCV */
+#define IFX_CCU6_CC63R_CCV_LEN (16u)
+
+/** \brief Mask for Ifx_CCU6_CC63R_Bits.CCV */
+#define IFX_CCU6_CC63R_CCV_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CCU6_CC63R_Bits.CCV */
+#define IFX_CCU6_CC63R_CCV_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_CC63SR_Bits.CCS */
+#define IFX_CCU6_CC63SR_CCS_LEN (16u)
+
+/** \brief Mask for Ifx_CCU6_CC63SR_Bits.CCS */
+#define IFX_CCU6_CC63SR_CCS_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CCU6_CC63SR_Bits.CCS */
+#define IFX_CCU6_CC63SR_CCS_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_CLC_Bits.DISR */
+#define IFX_CCU6_CLC_DISR_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_CLC_Bits.DISR */
+#define IFX_CCU6_CLC_DISR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_CLC_Bits.DISR */
+#define IFX_CCU6_CLC_DISR_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_CLC_Bits.DISS */
+#define IFX_CCU6_CLC_DISS_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_CLC_Bits.DISS */
+#define IFX_CCU6_CLC_DISS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_CLC_Bits.DISS */
+#define IFX_CCU6_CLC_DISS_OFF (1u)
+
+/** \brief Length for Ifx_CCU6_CLC_Bits.EDIS */
+#define IFX_CCU6_CLC_EDIS_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_CLC_Bits.EDIS */
+#define IFX_CCU6_CLC_EDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_CLC_Bits.EDIS */
+#define IFX_CCU6_CLC_EDIS_OFF (3u)
+
+/** \brief Length for Ifx_CCU6_CMPMODIF_Bits.MCC60R */
+#define IFX_CCU6_CMPMODIF_MCC60R_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_CMPMODIF_Bits.MCC60R */
+#define IFX_CCU6_CMPMODIF_MCC60R_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_CMPMODIF_Bits.MCC60R */
+#define IFX_CCU6_CMPMODIF_MCC60R_OFF (8u)
+
+/** \brief Length for Ifx_CCU6_CMPMODIF_Bits.MCC60S */
+#define IFX_CCU6_CMPMODIF_MCC60S_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_CMPMODIF_Bits.MCC60S */
+#define IFX_CCU6_CMPMODIF_MCC60S_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_CMPMODIF_Bits.MCC60S */
+#define IFX_CCU6_CMPMODIF_MCC60S_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_CMPMODIF_Bits.MCC61R */
+#define IFX_CCU6_CMPMODIF_MCC61R_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_CMPMODIF_Bits.MCC61R */
+#define IFX_CCU6_CMPMODIF_MCC61R_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_CMPMODIF_Bits.MCC61R */
+#define IFX_CCU6_CMPMODIF_MCC61R_OFF (9u)
+
+/** \brief Length for Ifx_CCU6_CMPMODIF_Bits.MCC61S */
+#define IFX_CCU6_CMPMODIF_MCC61S_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_CMPMODIF_Bits.MCC61S */
+#define IFX_CCU6_CMPMODIF_MCC61S_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_CMPMODIF_Bits.MCC61S */
+#define IFX_CCU6_CMPMODIF_MCC61S_OFF (1u)
+
+/** \brief Length for Ifx_CCU6_CMPMODIF_Bits.MCC62R */
+#define IFX_CCU6_CMPMODIF_MCC62R_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_CMPMODIF_Bits.MCC62R */
+#define IFX_CCU6_CMPMODIF_MCC62R_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_CMPMODIF_Bits.MCC62R */
+#define IFX_CCU6_CMPMODIF_MCC62R_OFF (10u)
+
+/** \brief Length for Ifx_CCU6_CMPMODIF_Bits.MCC62S */
+#define IFX_CCU6_CMPMODIF_MCC62S_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_CMPMODIF_Bits.MCC62S */
+#define IFX_CCU6_CMPMODIF_MCC62S_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_CMPMODIF_Bits.MCC62S */
+#define IFX_CCU6_CMPMODIF_MCC62S_OFF (2u)
+
+/** \brief Length for Ifx_CCU6_CMPMODIF_Bits.MCC63R */
+#define IFX_CCU6_CMPMODIF_MCC63R_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_CMPMODIF_Bits.MCC63R */
+#define IFX_CCU6_CMPMODIF_MCC63R_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_CMPMODIF_Bits.MCC63R */
+#define IFX_CCU6_CMPMODIF_MCC63R_OFF (14u)
+
+/** \brief Length for Ifx_CCU6_CMPMODIF_Bits.MCC63S */
+#define IFX_CCU6_CMPMODIF_MCC63S_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_CMPMODIF_Bits.MCC63S */
+#define IFX_CCU6_CMPMODIF_MCC63S_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_CMPMODIF_Bits.MCC63S */
+#define IFX_CCU6_CMPMODIF_MCC63S_OFF (6u)
+
+/** \brief Length for Ifx_CCU6_CMPSTAT_Bits.CC60PS */
+#define IFX_CCU6_CMPSTAT_CC60PS_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_CMPSTAT_Bits.CC60PS */
+#define IFX_CCU6_CMPSTAT_CC60PS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_CMPSTAT_Bits.CC60PS */
+#define IFX_CCU6_CMPSTAT_CC60PS_OFF (8u)
+
+/** \brief Length for Ifx_CCU6_CMPSTAT_Bits.CC60ST */
+#define IFX_CCU6_CMPSTAT_CC60ST_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_CMPSTAT_Bits.CC60ST */
+#define IFX_CCU6_CMPSTAT_CC60ST_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_CMPSTAT_Bits.CC60ST */
+#define IFX_CCU6_CMPSTAT_CC60ST_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_CMPSTAT_Bits.CC61PS */
+#define IFX_CCU6_CMPSTAT_CC61PS_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_CMPSTAT_Bits.CC61PS */
+#define IFX_CCU6_CMPSTAT_CC61PS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_CMPSTAT_Bits.CC61PS */
+#define IFX_CCU6_CMPSTAT_CC61PS_OFF (10u)
+
+/** \brief Length for Ifx_CCU6_CMPSTAT_Bits.CC61ST */
+#define IFX_CCU6_CMPSTAT_CC61ST_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_CMPSTAT_Bits.CC61ST */
+#define IFX_CCU6_CMPSTAT_CC61ST_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_CMPSTAT_Bits.CC61ST */
+#define IFX_CCU6_CMPSTAT_CC61ST_OFF (1u)
+
+/** \brief Length for Ifx_CCU6_CMPSTAT_Bits.CC62PS */
+#define IFX_CCU6_CMPSTAT_CC62PS_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_CMPSTAT_Bits.CC62PS */
+#define IFX_CCU6_CMPSTAT_CC62PS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_CMPSTAT_Bits.CC62PS */
+#define IFX_CCU6_CMPSTAT_CC62PS_OFF (12u)
+
+/** \brief Length for Ifx_CCU6_CMPSTAT_Bits.CC62ST */
+#define IFX_CCU6_CMPSTAT_CC62ST_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_CMPSTAT_Bits.CC62ST */
+#define IFX_CCU6_CMPSTAT_CC62ST_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_CMPSTAT_Bits.CC62ST */
+#define IFX_CCU6_CMPSTAT_CC62ST_OFF (2u)
+
+/** \brief Length for Ifx_CCU6_CMPSTAT_Bits.CC63ST */
+#define IFX_CCU6_CMPSTAT_CC63ST_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_CMPSTAT_Bits.CC63ST */
+#define IFX_CCU6_CMPSTAT_CC63ST_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_CMPSTAT_Bits.CC63ST */
+#define IFX_CCU6_CMPSTAT_CC63ST_OFF (6u)
+
+/** \brief Length for Ifx_CCU6_CMPSTAT_Bits.CCPOS60 */
+#define IFX_CCU6_CMPSTAT_CCPOS60_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_CMPSTAT_Bits.CCPOS60 */
+#define IFX_CCU6_CMPSTAT_CCPOS60_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_CMPSTAT_Bits.CCPOS60 */
+#define IFX_CCU6_CMPSTAT_CCPOS60_OFF (3u)
+
+/** \brief Length for Ifx_CCU6_CMPSTAT_Bits.CCPOS61 */
+#define IFX_CCU6_CMPSTAT_CCPOS61_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_CMPSTAT_Bits.CCPOS61 */
+#define IFX_CCU6_CMPSTAT_CCPOS61_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_CMPSTAT_Bits.CCPOS61 */
+#define IFX_CCU6_CMPSTAT_CCPOS61_OFF (4u)
+
+/** \brief Length for Ifx_CCU6_CMPSTAT_Bits.CCPOS62 */
+#define IFX_CCU6_CMPSTAT_CCPOS62_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_CMPSTAT_Bits.CCPOS62 */
+#define IFX_CCU6_CMPSTAT_CCPOS62_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_CMPSTAT_Bits.CCPOS62 */
+#define IFX_CCU6_CMPSTAT_CCPOS62_OFF (5u)
+
+/** \brief Length for Ifx_CCU6_CMPSTAT_Bits.COUT60PS */
+#define IFX_CCU6_CMPSTAT_COUT60PS_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_CMPSTAT_Bits.COUT60PS */
+#define IFX_CCU6_CMPSTAT_COUT60PS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_CMPSTAT_Bits.COUT60PS */
+#define IFX_CCU6_CMPSTAT_COUT60PS_OFF (9u)
+
+/** \brief Length for Ifx_CCU6_CMPSTAT_Bits.COUT61PS */
+#define IFX_CCU6_CMPSTAT_COUT61PS_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_CMPSTAT_Bits.COUT61PS */
+#define IFX_CCU6_CMPSTAT_COUT61PS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_CMPSTAT_Bits.COUT61PS */
+#define IFX_CCU6_CMPSTAT_COUT61PS_OFF (11u)
+
+/** \brief Length for Ifx_CCU6_CMPSTAT_Bits.COUT62PS */
+#define IFX_CCU6_CMPSTAT_COUT62PS_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_CMPSTAT_Bits.COUT62PS */
+#define IFX_CCU6_CMPSTAT_COUT62PS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_CMPSTAT_Bits.COUT62PS */
+#define IFX_CCU6_CMPSTAT_COUT62PS_OFF (13u)
+
+/** \brief Length for Ifx_CCU6_CMPSTAT_Bits.COUT63PS */
+#define IFX_CCU6_CMPSTAT_COUT63PS_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_CMPSTAT_Bits.COUT63PS */
+#define IFX_CCU6_CMPSTAT_COUT63PS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_CMPSTAT_Bits.COUT63PS */
+#define IFX_CCU6_CMPSTAT_COUT63PS_OFF (14u)
+
+/** \brief Length for Ifx_CCU6_CMPSTAT_Bits.T13IM */
+#define IFX_CCU6_CMPSTAT_T13IM_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_CMPSTAT_Bits.T13IM */
+#define IFX_CCU6_CMPSTAT_T13IM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_CMPSTAT_Bits.T13IM */
+#define IFX_CCU6_CMPSTAT_T13IM_OFF (15u)
+
+/** \brief Length for Ifx_CCU6_ID_Bits.MODNUMBER */
+#define IFX_CCU6_ID_MODNUMBER_LEN (8u)
+
+/** \brief Mask for Ifx_CCU6_ID_Bits.MODNUMBER */
+#define IFX_CCU6_ID_MODNUMBER_MSK (0xffu)
+
+/** \brief Offset for Ifx_CCU6_ID_Bits.MODNUMBER */
+#define IFX_CCU6_ID_MODNUMBER_OFF (8u)
+
+/** \brief Length for Ifx_CCU6_ID_Bits.MODREV */
+#define IFX_CCU6_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_CCU6_ID_Bits.MODREV */
+#define IFX_CCU6_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_CCU6_ID_Bits.MODREV */
+#define IFX_CCU6_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_IEN_Bits.ENCC60F */
+#define IFX_CCU6_IEN_ENCC60F_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IEN_Bits.ENCC60F */
+#define IFX_CCU6_IEN_ENCC60F_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IEN_Bits.ENCC60F */
+#define IFX_CCU6_IEN_ENCC60F_OFF (1u)
+
+/** \brief Length for Ifx_CCU6_IEN_Bits.ENCC60R */
+#define IFX_CCU6_IEN_ENCC60R_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IEN_Bits.ENCC60R */
+#define IFX_CCU6_IEN_ENCC60R_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IEN_Bits.ENCC60R */
+#define IFX_CCU6_IEN_ENCC60R_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_IEN_Bits.ENCC61F */
+#define IFX_CCU6_IEN_ENCC61F_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IEN_Bits.ENCC61F */
+#define IFX_CCU6_IEN_ENCC61F_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IEN_Bits.ENCC61F */
+#define IFX_CCU6_IEN_ENCC61F_OFF (3u)
+
+/** \brief Length for Ifx_CCU6_IEN_Bits.ENCC61R */
+#define IFX_CCU6_IEN_ENCC61R_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IEN_Bits.ENCC61R */
+#define IFX_CCU6_IEN_ENCC61R_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IEN_Bits.ENCC61R */
+#define IFX_CCU6_IEN_ENCC61R_OFF (2u)
+
+/** \brief Length for Ifx_CCU6_IEN_Bits.ENCC62F */
+#define IFX_CCU6_IEN_ENCC62F_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IEN_Bits.ENCC62F */
+#define IFX_CCU6_IEN_ENCC62F_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IEN_Bits.ENCC62F */
+#define IFX_CCU6_IEN_ENCC62F_OFF (5u)
+
+/** \brief Length for Ifx_CCU6_IEN_Bits.ENCC62R */
+#define IFX_CCU6_IEN_ENCC62R_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IEN_Bits.ENCC62R */
+#define IFX_CCU6_IEN_ENCC62R_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IEN_Bits.ENCC62R */
+#define IFX_CCU6_IEN_ENCC62R_OFF (4u)
+
+/** \brief Length for Ifx_CCU6_IEN_Bits.ENCHE */
+#define IFX_CCU6_IEN_ENCHE_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IEN_Bits.ENCHE */
+#define IFX_CCU6_IEN_ENCHE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IEN_Bits.ENCHE */
+#define IFX_CCU6_IEN_ENCHE_OFF (12u)
+
+/** \brief Length for Ifx_CCU6_IEN_Bits.ENIDLE */
+#define IFX_CCU6_IEN_ENIDLE_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IEN_Bits.ENIDLE */
+#define IFX_CCU6_IEN_ENIDLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IEN_Bits.ENIDLE */
+#define IFX_CCU6_IEN_ENIDLE_OFF (14u)
+
+/** \brief Length for Ifx_CCU6_IEN_Bits.ENSTR */
+#define IFX_CCU6_IEN_ENSTR_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IEN_Bits.ENSTR */
+#define IFX_CCU6_IEN_ENSTR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IEN_Bits.ENSTR */
+#define IFX_CCU6_IEN_ENSTR_OFF (15u)
+
+/** \brief Length for Ifx_CCU6_IEN_Bits.ENT12OM */
+#define IFX_CCU6_IEN_ENT12OM_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IEN_Bits.ENT12OM */
+#define IFX_CCU6_IEN_ENT12OM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IEN_Bits.ENT12OM */
+#define IFX_CCU6_IEN_ENT12OM_OFF (6u)
+
+/** \brief Length for Ifx_CCU6_IEN_Bits.ENT12PM */
+#define IFX_CCU6_IEN_ENT12PM_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IEN_Bits.ENT12PM */
+#define IFX_CCU6_IEN_ENT12PM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IEN_Bits.ENT12PM */
+#define IFX_CCU6_IEN_ENT12PM_OFF (7u)
+
+/** \brief Length for Ifx_CCU6_IEN_Bits.ENT13CM */
+#define IFX_CCU6_IEN_ENT13CM_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IEN_Bits.ENT13CM */
+#define IFX_CCU6_IEN_ENT13CM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IEN_Bits.ENT13CM */
+#define IFX_CCU6_IEN_ENT13CM_OFF (8u)
+
+/** \brief Length for Ifx_CCU6_IEN_Bits.ENT13PM */
+#define IFX_CCU6_IEN_ENT13PM_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IEN_Bits.ENT13PM */
+#define IFX_CCU6_IEN_ENT13PM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IEN_Bits.ENT13PM */
+#define IFX_CCU6_IEN_ENT13PM_OFF (9u)
+
+/** \brief Length for Ifx_CCU6_IEN_Bits.ENTRPF */
+#define IFX_CCU6_IEN_ENTRPF_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IEN_Bits.ENTRPF */
+#define IFX_CCU6_IEN_ENTRPF_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IEN_Bits.ENTRPF */
+#define IFX_CCU6_IEN_ENTRPF_OFF (10u)
+
+/** \brief Length for Ifx_CCU6_IEN_Bits.ENWHE */
+#define IFX_CCU6_IEN_ENWHE_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IEN_Bits.ENWHE */
+#define IFX_CCU6_IEN_ENWHE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IEN_Bits.ENWHE */
+#define IFX_CCU6_IEN_ENWHE_OFF (13u)
+
+/** \brief Length for Ifx_CCU6_IMON_Bits.CC60INI */
+#define IFX_CCU6_IMON_CC60INI_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IMON_Bits.CC60INI */
+#define IFX_CCU6_IMON_CC60INI_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IMON_Bits.CC60INI */
+#define IFX_CCU6_IMON_CC60INI_OFF (4u)
+
+/** \brief Length for Ifx_CCU6_IMON_Bits.CC61INI */
+#define IFX_CCU6_IMON_CC61INI_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IMON_Bits.CC61INI */
+#define IFX_CCU6_IMON_CC61INI_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IMON_Bits.CC61INI */
+#define IFX_CCU6_IMON_CC61INI_OFF (5u)
+
+/** \brief Length for Ifx_CCU6_IMON_Bits.CC62INI */
+#define IFX_CCU6_IMON_CC62INI_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IMON_Bits.CC62INI */
+#define IFX_CCU6_IMON_CC62INI_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IMON_Bits.CC62INI */
+#define IFX_CCU6_IMON_CC62INI_OFF (6u)
+
+/** \brief Length for Ifx_CCU6_IMON_Bits.CCPOS0I */
+#define IFX_CCU6_IMON_CCPOS0I_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IMON_Bits.CCPOS0I */
+#define IFX_CCU6_IMON_CCPOS0I_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IMON_Bits.CCPOS0I */
+#define IFX_CCU6_IMON_CCPOS0I_OFF (1u)
+
+/** \brief Length for Ifx_CCU6_IMON_Bits.CCPOS1I */
+#define IFX_CCU6_IMON_CCPOS1I_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IMON_Bits.CCPOS1I */
+#define IFX_CCU6_IMON_CCPOS1I_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IMON_Bits.CCPOS1I */
+#define IFX_CCU6_IMON_CCPOS1I_OFF (2u)
+
+/** \brief Length for Ifx_CCU6_IMON_Bits.CCPOS2I */
+#define IFX_CCU6_IMON_CCPOS2I_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IMON_Bits.CCPOS2I */
+#define IFX_CCU6_IMON_CCPOS2I_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IMON_Bits.CCPOS2I */
+#define IFX_CCU6_IMON_CCPOS2I_OFF (3u)
+
+/** \brief Length for Ifx_CCU6_IMON_Bits.CTRAPI */
+#define IFX_CCU6_IMON_CTRAPI_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IMON_Bits.CTRAPI */
+#define IFX_CCU6_IMON_CTRAPI_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IMON_Bits.CTRAPI */
+#define IFX_CCU6_IMON_CTRAPI_OFF (7u)
+
+/** \brief Length for Ifx_CCU6_IMON_Bits.LBE */
+#define IFX_CCU6_IMON_LBE_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IMON_Bits.LBE */
+#define IFX_CCU6_IMON_LBE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IMON_Bits.LBE */
+#define IFX_CCU6_IMON_LBE_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_IMON_Bits.T12HRI */
+#define IFX_CCU6_IMON_T12HRI_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IMON_Bits.T12HRI */
+#define IFX_CCU6_IMON_T12HRI_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IMON_Bits.T12HRI */
+#define IFX_CCU6_IMON_T12HRI_OFF (8u)
+
+/** \brief Length for Ifx_CCU6_IMON_Bits.T13HRI */
+#define IFX_CCU6_IMON_T13HRI_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IMON_Bits.T13HRI */
+#define IFX_CCU6_IMON_T13HRI_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IMON_Bits.T13HRI */
+#define IFX_CCU6_IMON_T13HRI_OFF (9u)
+
+/** \brief Length for Ifx_CCU6_INP_Bits.INPCC60 */
+#define IFX_CCU6_INP_INPCC60_LEN (2u)
+
+/** \brief Mask for Ifx_CCU6_INP_Bits.INPCC60 */
+#define IFX_CCU6_INP_INPCC60_MSK (0x3u)
+
+/** \brief Offset for Ifx_CCU6_INP_Bits.INPCC60 */
+#define IFX_CCU6_INP_INPCC60_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_INP_Bits.INPCC61 */
+#define IFX_CCU6_INP_INPCC61_LEN (2u)
+
+/** \brief Mask for Ifx_CCU6_INP_Bits.INPCC61 */
+#define IFX_CCU6_INP_INPCC61_MSK (0x3u)
+
+/** \brief Offset for Ifx_CCU6_INP_Bits.INPCC61 */
+#define IFX_CCU6_INP_INPCC61_OFF (2u)
+
+/** \brief Length for Ifx_CCU6_INP_Bits.INPCC62 */
+#define IFX_CCU6_INP_INPCC62_LEN (2u)
+
+/** \brief Mask for Ifx_CCU6_INP_Bits.INPCC62 */
+#define IFX_CCU6_INP_INPCC62_MSK (0x3u)
+
+/** \brief Offset for Ifx_CCU6_INP_Bits.INPCC62 */
+#define IFX_CCU6_INP_INPCC62_OFF (4u)
+
+/** \brief Length for Ifx_CCU6_INP_Bits.INPCHE */
+#define IFX_CCU6_INP_INPCHE_LEN (2u)
+
+/** \brief Mask for Ifx_CCU6_INP_Bits.INPCHE */
+#define IFX_CCU6_INP_INPCHE_MSK (0x3u)
+
+/** \brief Offset for Ifx_CCU6_INP_Bits.INPCHE */
+#define IFX_CCU6_INP_INPCHE_OFF (6u)
+
+/** \brief Length for Ifx_CCU6_INP_Bits.INPERR */
+#define IFX_CCU6_INP_INPERR_LEN (2u)
+
+/** \brief Mask for Ifx_CCU6_INP_Bits.INPERR */
+#define IFX_CCU6_INP_INPERR_MSK (0x3u)
+
+/** \brief Offset for Ifx_CCU6_INP_Bits.INPERR */
+#define IFX_CCU6_INP_INPERR_OFF (8u)
+
+/** \brief Length for Ifx_CCU6_INP_Bits.INPT12 */
+#define IFX_CCU6_INP_INPT12_LEN (2u)
+
+/** \brief Mask for Ifx_CCU6_INP_Bits.INPT12 */
+#define IFX_CCU6_INP_INPT12_MSK (0x3u)
+
+/** \brief Offset for Ifx_CCU6_INP_Bits.INPT12 */
+#define IFX_CCU6_INP_INPT12_OFF (10u)
+
+/** \brief Length for Ifx_CCU6_INP_Bits.INPT13 */
+#define IFX_CCU6_INP_INPT13_LEN (2u)
+
+/** \brief Mask for Ifx_CCU6_INP_Bits.INPT13 */
+#define IFX_CCU6_INP_INPT13_MSK (0x3u)
+
+/** \brief Offset for Ifx_CCU6_INP_Bits.INPT13 */
+#define IFX_CCU6_INP_INPT13_OFF (12u)
+
+/** \brief Length for Ifx_CCU6_IS_Bits.CHE */
+#define IFX_CCU6_IS_CHE_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IS_Bits.CHE */
+#define IFX_CCU6_IS_CHE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IS_Bits.CHE */
+#define IFX_CCU6_IS_CHE_OFF (12u)
+
+/** \brief Length for Ifx_CCU6_IS_Bits.ICC60F */
+#define IFX_CCU6_IS_ICC60F_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IS_Bits.ICC60F */
+#define IFX_CCU6_IS_ICC60F_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IS_Bits.ICC60F */
+#define IFX_CCU6_IS_ICC60F_OFF (1u)
+
+/** \brief Length for Ifx_CCU6_IS_Bits.ICC60R */
+#define IFX_CCU6_IS_ICC60R_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IS_Bits.ICC60R */
+#define IFX_CCU6_IS_ICC60R_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IS_Bits.ICC60R */
+#define IFX_CCU6_IS_ICC60R_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_IS_Bits.ICC61F */
+#define IFX_CCU6_IS_ICC61F_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IS_Bits.ICC61F */
+#define IFX_CCU6_IS_ICC61F_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IS_Bits.ICC61F */
+#define IFX_CCU6_IS_ICC61F_OFF (3u)
+
+/** \brief Length for Ifx_CCU6_IS_Bits.ICC61R */
+#define IFX_CCU6_IS_ICC61R_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IS_Bits.ICC61R */
+#define IFX_CCU6_IS_ICC61R_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IS_Bits.ICC61R */
+#define IFX_CCU6_IS_ICC61R_OFF (2u)
+
+/** \brief Length for Ifx_CCU6_IS_Bits.ICC62F */
+#define IFX_CCU6_IS_ICC62F_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IS_Bits.ICC62F */
+#define IFX_CCU6_IS_ICC62F_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IS_Bits.ICC62F */
+#define IFX_CCU6_IS_ICC62F_OFF (5u)
+
+/** \brief Length for Ifx_CCU6_IS_Bits.ICC62R */
+#define IFX_CCU6_IS_ICC62R_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IS_Bits.ICC62R */
+#define IFX_CCU6_IS_ICC62R_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IS_Bits.ICC62R */
+#define IFX_CCU6_IS_ICC62R_OFF (4u)
+
+/** \brief Length for Ifx_CCU6_IS_Bits.IDLE */
+#define IFX_CCU6_IS_IDLE_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IS_Bits.IDLE */
+#define IFX_CCU6_IS_IDLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IS_Bits.IDLE */
+#define IFX_CCU6_IS_IDLE_OFF (14u)
+
+/** \brief Length for Ifx_CCU6_IS_Bits.STR */
+#define IFX_CCU6_IS_STR_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IS_Bits.STR */
+#define IFX_CCU6_IS_STR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IS_Bits.STR */
+#define IFX_CCU6_IS_STR_OFF (15u)
+
+/** \brief Length for Ifx_CCU6_IS_Bits.T12OM */
+#define IFX_CCU6_IS_T12OM_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IS_Bits.T12OM */
+#define IFX_CCU6_IS_T12OM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IS_Bits.T12OM */
+#define IFX_CCU6_IS_T12OM_OFF (6u)
+
+/** \brief Length for Ifx_CCU6_IS_Bits.T12PM */
+#define IFX_CCU6_IS_T12PM_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IS_Bits.T12PM */
+#define IFX_CCU6_IS_T12PM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IS_Bits.T12PM */
+#define IFX_CCU6_IS_T12PM_OFF (7u)
+
+/** \brief Length for Ifx_CCU6_IS_Bits.T13CM */
+#define IFX_CCU6_IS_T13CM_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IS_Bits.T13CM */
+#define IFX_CCU6_IS_T13CM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IS_Bits.T13CM */
+#define IFX_CCU6_IS_T13CM_OFF (8u)
+
+/** \brief Length for Ifx_CCU6_IS_Bits.T13PM */
+#define IFX_CCU6_IS_T13PM_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IS_Bits.T13PM */
+#define IFX_CCU6_IS_T13PM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IS_Bits.T13PM */
+#define IFX_CCU6_IS_T13PM_OFF (9u)
+
+/** \brief Length for Ifx_CCU6_IS_Bits.TRPF */
+#define IFX_CCU6_IS_TRPF_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IS_Bits.TRPF */
+#define IFX_CCU6_IS_TRPF_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IS_Bits.TRPF */
+#define IFX_CCU6_IS_TRPF_OFF (10u)
+
+/** \brief Length for Ifx_CCU6_IS_Bits.TRPS */
+#define IFX_CCU6_IS_TRPS_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IS_Bits.TRPS */
+#define IFX_CCU6_IS_TRPS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IS_Bits.TRPS */
+#define IFX_CCU6_IS_TRPS_OFF (11u)
+
+/** \brief Length for Ifx_CCU6_IS_Bits.WHE */
+#define IFX_CCU6_IS_WHE_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_IS_Bits.WHE */
+#define IFX_CCU6_IS_WHE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_IS_Bits.WHE */
+#define IFX_CCU6_IS_WHE_OFF (13u)
+
+/** \brief Length for Ifx_CCU6_ISR_Bits.RCC60F */
+#define IFX_CCU6_ISR_RCC60F_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISR_Bits.RCC60F */
+#define IFX_CCU6_ISR_RCC60F_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISR_Bits.RCC60F */
+#define IFX_CCU6_ISR_RCC60F_OFF (1u)
+
+/** \brief Length for Ifx_CCU6_ISR_Bits.RCC60R */
+#define IFX_CCU6_ISR_RCC60R_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISR_Bits.RCC60R */
+#define IFX_CCU6_ISR_RCC60R_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISR_Bits.RCC60R */
+#define IFX_CCU6_ISR_RCC60R_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_ISR_Bits.RCC61F */
+#define IFX_CCU6_ISR_RCC61F_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISR_Bits.RCC61F */
+#define IFX_CCU6_ISR_RCC61F_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISR_Bits.RCC61F */
+#define IFX_CCU6_ISR_RCC61F_OFF (3u)
+
+/** \brief Length for Ifx_CCU6_ISR_Bits.RCC61R */
+#define IFX_CCU6_ISR_RCC61R_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISR_Bits.RCC61R */
+#define IFX_CCU6_ISR_RCC61R_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISR_Bits.RCC61R */
+#define IFX_CCU6_ISR_RCC61R_OFF (2u)
+
+/** \brief Length for Ifx_CCU6_ISR_Bits.RCC62F */
+#define IFX_CCU6_ISR_RCC62F_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISR_Bits.RCC62F */
+#define IFX_CCU6_ISR_RCC62F_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISR_Bits.RCC62F */
+#define IFX_CCU6_ISR_RCC62F_OFF (5u)
+
+/** \brief Length for Ifx_CCU6_ISR_Bits.RCC62R */
+#define IFX_CCU6_ISR_RCC62R_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISR_Bits.RCC62R */
+#define IFX_CCU6_ISR_RCC62R_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISR_Bits.RCC62R */
+#define IFX_CCU6_ISR_RCC62R_OFF (4u)
+
+/** \brief Length for Ifx_CCU6_ISR_Bits.RCHE */
+#define IFX_CCU6_ISR_RCHE_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISR_Bits.RCHE */
+#define IFX_CCU6_ISR_RCHE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISR_Bits.RCHE */
+#define IFX_CCU6_ISR_RCHE_OFF (12u)
+
+/** \brief Length for Ifx_CCU6_ISR_Bits.RIDLE */
+#define IFX_CCU6_ISR_RIDLE_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISR_Bits.RIDLE */
+#define IFX_CCU6_ISR_RIDLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISR_Bits.RIDLE */
+#define IFX_CCU6_ISR_RIDLE_OFF (14u)
+
+/** \brief Length for Ifx_CCU6_ISR_Bits.RSTR */
+#define IFX_CCU6_ISR_RSTR_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISR_Bits.RSTR */
+#define IFX_CCU6_ISR_RSTR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISR_Bits.RSTR */
+#define IFX_CCU6_ISR_RSTR_OFF (15u)
+
+/** \brief Length for Ifx_CCU6_ISR_Bits.RT12OM */
+#define IFX_CCU6_ISR_RT12OM_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISR_Bits.RT12OM */
+#define IFX_CCU6_ISR_RT12OM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISR_Bits.RT12OM */
+#define IFX_CCU6_ISR_RT12OM_OFF (6u)
+
+/** \brief Length for Ifx_CCU6_ISR_Bits.RT12PM */
+#define IFX_CCU6_ISR_RT12PM_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISR_Bits.RT12PM */
+#define IFX_CCU6_ISR_RT12PM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISR_Bits.RT12PM */
+#define IFX_CCU6_ISR_RT12PM_OFF (7u)
+
+/** \brief Length for Ifx_CCU6_ISR_Bits.RT13CM */
+#define IFX_CCU6_ISR_RT13CM_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISR_Bits.RT13CM */
+#define IFX_CCU6_ISR_RT13CM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISR_Bits.RT13CM */
+#define IFX_CCU6_ISR_RT13CM_OFF (8u)
+
+/** \brief Length for Ifx_CCU6_ISR_Bits.RT13PM */
+#define IFX_CCU6_ISR_RT13PM_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISR_Bits.RT13PM */
+#define IFX_CCU6_ISR_RT13PM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISR_Bits.RT13PM */
+#define IFX_CCU6_ISR_RT13PM_OFF (9u)
+
+/** \brief Length for Ifx_CCU6_ISR_Bits.RTRPF */
+#define IFX_CCU6_ISR_RTRPF_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISR_Bits.RTRPF */
+#define IFX_CCU6_ISR_RTRPF_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISR_Bits.RTRPF */
+#define IFX_CCU6_ISR_RTRPF_OFF (10u)
+
+/** \brief Length for Ifx_CCU6_ISR_Bits.RWHE */
+#define IFX_CCU6_ISR_RWHE_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISR_Bits.RWHE */
+#define IFX_CCU6_ISR_RWHE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISR_Bits.RWHE */
+#define IFX_CCU6_ISR_RWHE_OFF (13u)
+
+/** \brief Length for Ifx_CCU6_ISS_Bits.SCC60F */
+#define IFX_CCU6_ISS_SCC60F_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISS_Bits.SCC60F */
+#define IFX_CCU6_ISS_SCC60F_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISS_Bits.SCC60F */
+#define IFX_CCU6_ISS_SCC60F_OFF (1u)
+
+/** \brief Length for Ifx_CCU6_ISS_Bits.SCC60R */
+#define IFX_CCU6_ISS_SCC60R_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISS_Bits.SCC60R */
+#define IFX_CCU6_ISS_SCC60R_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISS_Bits.SCC60R */
+#define IFX_CCU6_ISS_SCC60R_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_ISS_Bits.SCC61F */
+#define IFX_CCU6_ISS_SCC61F_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISS_Bits.SCC61F */
+#define IFX_CCU6_ISS_SCC61F_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISS_Bits.SCC61F */
+#define IFX_CCU6_ISS_SCC61F_OFF (3u)
+
+/** \brief Length for Ifx_CCU6_ISS_Bits.SCC61R */
+#define IFX_CCU6_ISS_SCC61R_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISS_Bits.SCC61R */
+#define IFX_CCU6_ISS_SCC61R_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISS_Bits.SCC61R */
+#define IFX_CCU6_ISS_SCC61R_OFF (2u)
+
+/** \brief Length for Ifx_CCU6_ISS_Bits.SCC62F */
+#define IFX_CCU6_ISS_SCC62F_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISS_Bits.SCC62F */
+#define IFX_CCU6_ISS_SCC62F_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISS_Bits.SCC62F */
+#define IFX_CCU6_ISS_SCC62F_OFF (5u)
+
+/** \brief Length for Ifx_CCU6_ISS_Bits.SCC62R */
+#define IFX_CCU6_ISS_SCC62R_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISS_Bits.SCC62R */
+#define IFX_CCU6_ISS_SCC62R_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISS_Bits.SCC62R */
+#define IFX_CCU6_ISS_SCC62R_OFF (4u)
+
+/** \brief Length for Ifx_CCU6_ISS_Bits.SCHE */
+#define IFX_CCU6_ISS_SCHE_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISS_Bits.SCHE */
+#define IFX_CCU6_ISS_SCHE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISS_Bits.SCHE */
+#define IFX_CCU6_ISS_SCHE_OFF (12u)
+
+/** \brief Length for Ifx_CCU6_ISS_Bits.SIDLE */
+#define IFX_CCU6_ISS_SIDLE_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISS_Bits.SIDLE */
+#define IFX_CCU6_ISS_SIDLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISS_Bits.SIDLE */
+#define IFX_CCU6_ISS_SIDLE_OFF (14u)
+
+/** \brief Length for Ifx_CCU6_ISS_Bits.SSTR */
+#define IFX_CCU6_ISS_SSTR_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISS_Bits.SSTR */
+#define IFX_CCU6_ISS_SSTR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISS_Bits.SSTR */
+#define IFX_CCU6_ISS_SSTR_OFF (15u)
+
+/** \brief Length for Ifx_CCU6_ISS_Bits.ST12OM */
+#define IFX_CCU6_ISS_ST12OM_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISS_Bits.ST12OM */
+#define IFX_CCU6_ISS_ST12OM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISS_Bits.ST12OM */
+#define IFX_CCU6_ISS_ST12OM_OFF (6u)
+
+/** \brief Length for Ifx_CCU6_ISS_Bits.ST12PM */
+#define IFX_CCU6_ISS_ST12PM_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISS_Bits.ST12PM */
+#define IFX_CCU6_ISS_ST12PM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISS_Bits.ST12PM */
+#define IFX_CCU6_ISS_ST12PM_OFF (7u)
+
+/** \brief Length for Ifx_CCU6_ISS_Bits.ST13CM */
+#define IFX_CCU6_ISS_ST13CM_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISS_Bits.ST13CM */
+#define IFX_CCU6_ISS_ST13CM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISS_Bits.ST13CM */
+#define IFX_CCU6_ISS_ST13CM_OFF (8u)
+
+/** \brief Length for Ifx_CCU6_ISS_Bits.ST13PM */
+#define IFX_CCU6_ISS_ST13PM_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISS_Bits.ST13PM */
+#define IFX_CCU6_ISS_ST13PM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISS_Bits.ST13PM */
+#define IFX_CCU6_ISS_ST13PM_OFF (9u)
+
+/** \brief Length for Ifx_CCU6_ISS_Bits.STRPF */
+#define IFX_CCU6_ISS_STRPF_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISS_Bits.STRPF */
+#define IFX_CCU6_ISS_STRPF_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISS_Bits.STRPF */
+#define IFX_CCU6_ISS_STRPF_OFF (10u)
+
+/** \brief Length for Ifx_CCU6_ISS_Bits.SWHC */
+#define IFX_CCU6_ISS_SWHC_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISS_Bits.SWHC */
+#define IFX_CCU6_ISS_SWHC_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISS_Bits.SWHC */
+#define IFX_CCU6_ISS_SWHC_OFF (11u)
+
+/** \brief Length for Ifx_CCU6_ISS_Bits.SWHE */
+#define IFX_CCU6_ISS_SWHE_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_ISS_Bits.SWHE */
+#define IFX_CCU6_ISS_SWHE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_ISS_Bits.SWHE */
+#define IFX_CCU6_ISS_SWHE_OFF (13u)
+
+/** \brief Length for Ifx_CCU6_KRST0_Bits.RST */
+#define IFX_CCU6_KRST0_RST_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_KRST0_Bits.RST */
+#define IFX_CCU6_KRST0_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_KRST0_Bits.RST */
+#define IFX_CCU6_KRST0_RST_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_KRST0_Bits.RSTSTAT */
+#define IFX_CCU6_KRST0_RSTSTAT_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_KRST0_Bits.RSTSTAT */
+#define IFX_CCU6_KRST0_RSTSTAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_KRST0_Bits.RSTSTAT */
+#define IFX_CCU6_KRST0_RSTSTAT_OFF (1u)
+
+/** \brief Length for Ifx_CCU6_KRST1_Bits.RST */
+#define IFX_CCU6_KRST1_RST_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_KRST1_Bits.RST */
+#define IFX_CCU6_KRST1_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_KRST1_Bits.RST */
+#define IFX_CCU6_KRST1_RST_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_KRSTCLR_Bits.CLR */
+#define IFX_CCU6_KRSTCLR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_KRSTCLR_Bits.CLR */
+#define IFX_CCU6_KRSTCLR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_KRSTCLR_Bits.CLR */
+#define IFX_CCU6_KRSTCLR_CLR_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_KSCSR_Bits.SB0 */
+#define IFX_CCU6_KSCSR_SB0_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_KSCSR_Bits.SB0 */
+#define IFX_CCU6_KSCSR_SB0_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_KSCSR_Bits.SB0 */
+#define IFX_CCU6_KSCSR_SB0_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_KSCSR_Bits.SB1 */
+#define IFX_CCU6_KSCSR_SB1_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_KSCSR_Bits.SB1 */
+#define IFX_CCU6_KSCSR_SB1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_KSCSR_Bits.SB1 */
+#define IFX_CCU6_KSCSR_SB1_OFF (1u)
+
+/** \brief Length for Ifx_CCU6_KSCSR_Bits.SB2 */
+#define IFX_CCU6_KSCSR_SB2_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_KSCSR_Bits.SB2 */
+#define IFX_CCU6_KSCSR_SB2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_KSCSR_Bits.SB2 */
+#define IFX_CCU6_KSCSR_SB2_OFF (2u)
+
+/** \brief Length for Ifx_CCU6_KSCSR_Bits.SB3 */
+#define IFX_CCU6_KSCSR_SB3_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_KSCSR_Bits.SB3 */
+#define IFX_CCU6_KSCSR_SB3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_KSCSR_Bits.SB3 */
+#define IFX_CCU6_KSCSR_SB3_OFF (3u)
+
+/** \brief Length for Ifx_CCU6_LI_Bits.CC60INEN */
+#define IFX_CCU6_LI_CC60INEN_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_LI_Bits.CC60INEN */
+#define IFX_CCU6_LI_CC60INEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_LI_Bits.CC60INEN */
+#define IFX_CCU6_LI_CC60INEN_OFF (4u)
+
+/** \brief Length for Ifx_CCU6_LI_Bits.CC61INEN */
+#define IFX_CCU6_LI_CC61INEN_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_LI_Bits.CC61INEN */
+#define IFX_CCU6_LI_CC61INEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_LI_Bits.CC61INEN */
+#define IFX_CCU6_LI_CC61INEN_OFF (5u)
+
+/** \brief Length for Ifx_CCU6_LI_Bits.CC62INEN */
+#define IFX_CCU6_LI_CC62INEN_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_LI_Bits.CC62INEN */
+#define IFX_CCU6_LI_CC62INEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_LI_Bits.CC62INEN */
+#define IFX_CCU6_LI_CC62INEN_OFF (6u)
+
+/** \brief Length for Ifx_CCU6_LI_Bits.CCPOS0EN */
+#define IFX_CCU6_LI_CCPOS0EN_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_LI_Bits.CCPOS0EN */
+#define IFX_CCU6_LI_CCPOS0EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_LI_Bits.CCPOS0EN */
+#define IFX_CCU6_LI_CCPOS0EN_OFF (1u)
+
+/** \brief Length for Ifx_CCU6_LI_Bits.CCPOS1EN */
+#define IFX_CCU6_LI_CCPOS1EN_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_LI_Bits.CCPOS1EN */
+#define IFX_CCU6_LI_CCPOS1EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_LI_Bits.CCPOS1EN */
+#define IFX_CCU6_LI_CCPOS1EN_OFF (2u)
+
+/** \brief Length for Ifx_CCU6_LI_Bits.CCPOS2EN */
+#define IFX_CCU6_LI_CCPOS2EN_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_LI_Bits.CCPOS2EN */
+#define IFX_CCU6_LI_CCPOS2EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_LI_Bits.CCPOS2EN */
+#define IFX_CCU6_LI_CCPOS2EN_OFF (3u)
+
+/** \brief Length for Ifx_CCU6_LI_Bits.CTRAPEN */
+#define IFX_CCU6_LI_CTRAPEN_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_LI_Bits.CTRAPEN */
+#define IFX_CCU6_LI_CTRAPEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_LI_Bits.CTRAPEN */
+#define IFX_CCU6_LI_CTRAPEN_OFF (7u)
+
+/** \brief Length for Ifx_CCU6_LI_Bits.INPLBE */
+#define IFX_CCU6_LI_INPLBE_LEN (2u)
+
+/** \brief Mask for Ifx_CCU6_LI_Bits.INPLBE */
+#define IFX_CCU6_LI_INPLBE_MSK (0x3u)
+
+/** \brief Offset for Ifx_CCU6_LI_Bits.INPLBE */
+#define IFX_CCU6_LI_INPLBE_OFF (14u)
+
+/** \brief Length for Ifx_CCU6_LI_Bits.LBEEN */
+#define IFX_CCU6_LI_LBEEN_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_LI_Bits.LBEEN */
+#define IFX_CCU6_LI_LBEEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_LI_Bits.LBEEN */
+#define IFX_CCU6_LI_LBEEN_OFF (13u)
+
+/** \brief Length for Ifx_CCU6_LI_Bits.T12HREN */
+#define IFX_CCU6_LI_T12HREN_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_LI_Bits.T12HREN */
+#define IFX_CCU6_LI_T12HREN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_LI_Bits.T12HREN */
+#define IFX_CCU6_LI_T12HREN_OFF (8u)
+
+/** \brief Length for Ifx_CCU6_LI_Bits.T13HREN */
+#define IFX_CCU6_LI_T13HREN_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_LI_Bits.T13HREN */
+#define IFX_CCU6_LI_T13HREN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_LI_Bits.T13HREN */
+#define IFX_CCU6_LI_T13HREN_OFF (9u)
+
+/** \brief Length for Ifx_CCU6_MCFG_Bits.MCM */
+#define IFX_CCU6_MCFG_MCM_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_MCFG_Bits.MCM */
+#define IFX_CCU6_MCFG_MCM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_MCFG_Bits.MCM */
+#define IFX_CCU6_MCFG_MCM_OFF (2u)
+
+/** \brief Length for Ifx_CCU6_MCFG_Bits.T12 */
+#define IFX_CCU6_MCFG_T12_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_MCFG_Bits.T12 */
+#define IFX_CCU6_MCFG_T12_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_MCFG_Bits.T12 */
+#define IFX_CCU6_MCFG_T12_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_MCFG_Bits.T13 */
+#define IFX_CCU6_MCFG_T13_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_MCFG_Bits.T13 */
+#define IFX_CCU6_MCFG_T13_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_MCFG_Bits.T13 */
+#define IFX_CCU6_MCFG_T13_OFF (1u)
+
+/** \brief Length for Ifx_CCU6_MCMCTR_Bits.STE12D */
+#define IFX_CCU6_MCMCTR_STE12D_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_MCMCTR_Bits.STE12D */
+#define IFX_CCU6_MCMCTR_STE12D_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_MCMCTR_Bits.STE12D */
+#define IFX_CCU6_MCMCTR_STE12D_OFF (9u)
+
+/** \brief Length for Ifx_CCU6_MCMCTR_Bits.STE12U */
+#define IFX_CCU6_MCMCTR_STE12U_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_MCMCTR_Bits.STE12U */
+#define IFX_CCU6_MCMCTR_STE12U_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_MCMCTR_Bits.STE12U */
+#define IFX_CCU6_MCMCTR_STE12U_OFF (8u)
+
+/** \brief Length for Ifx_CCU6_MCMCTR_Bits.STE13U */
+#define IFX_CCU6_MCMCTR_STE13U_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_MCMCTR_Bits.STE13U */
+#define IFX_CCU6_MCMCTR_STE13U_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_MCMCTR_Bits.STE13U */
+#define IFX_CCU6_MCMCTR_STE13U_OFF (10u)
+
+/** \brief Length for Ifx_CCU6_MCMCTR_Bits.SWSEL */
+#define IFX_CCU6_MCMCTR_SWSEL_LEN (3u)
+
+/** \brief Mask for Ifx_CCU6_MCMCTR_Bits.SWSEL */
+#define IFX_CCU6_MCMCTR_SWSEL_MSK (0x7u)
+
+/** \brief Offset for Ifx_CCU6_MCMCTR_Bits.SWSEL */
+#define IFX_CCU6_MCMCTR_SWSEL_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_MCMCTR_Bits.SWSYN */
+#define IFX_CCU6_MCMCTR_SWSYN_LEN (2u)
+
+/** \brief Mask for Ifx_CCU6_MCMCTR_Bits.SWSYN */
+#define IFX_CCU6_MCMCTR_SWSYN_MSK (0x3u)
+
+/** \brief Offset for Ifx_CCU6_MCMCTR_Bits.SWSYN */
+#define IFX_CCU6_MCMCTR_SWSYN_OFF (4u)
+
+/** \brief Length for Ifx_CCU6_MCMOUT_Bits.CURH */
+#define IFX_CCU6_MCMOUT_CURH_LEN (3u)
+
+/** \brief Mask for Ifx_CCU6_MCMOUT_Bits.CURH */
+#define IFX_CCU6_MCMOUT_CURH_MSK (0x7u)
+
+/** \brief Offset for Ifx_CCU6_MCMOUT_Bits.CURH */
+#define IFX_CCU6_MCMOUT_CURH_OFF (11u)
+
+/** \brief Length for Ifx_CCU6_MCMOUT_Bits.EXPH */
+#define IFX_CCU6_MCMOUT_EXPH_LEN (3u)
+
+/** \brief Mask for Ifx_CCU6_MCMOUT_Bits.EXPH */
+#define IFX_CCU6_MCMOUT_EXPH_MSK (0x7u)
+
+/** \brief Offset for Ifx_CCU6_MCMOUT_Bits.EXPH */
+#define IFX_CCU6_MCMOUT_EXPH_OFF (8u)
+
+/** \brief Length for Ifx_CCU6_MCMOUT_Bits.MCMP */
+#define IFX_CCU6_MCMOUT_MCMP_LEN (6u)
+
+/** \brief Mask for Ifx_CCU6_MCMOUT_Bits.MCMP */
+#define IFX_CCU6_MCMOUT_MCMP_MSK (0x3fu)
+
+/** \brief Offset for Ifx_CCU6_MCMOUT_Bits.MCMP */
+#define IFX_CCU6_MCMOUT_MCMP_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_MCMOUT_Bits.R */
+#define IFX_CCU6_MCMOUT_R_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_MCMOUT_Bits.R */
+#define IFX_CCU6_MCMOUT_R_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_MCMOUT_Bits.R */
+#define IFX_CCU6_MCMOUT_R_OFF (6u)
+
+/** \brief Length for Ifx_CCU6_MCMOUTS_Bits.CURHS */
+#define IFX_CCU6_MCMOUTS_CURHS_LEN (3u)
+
+/** \brief Mask for Ifx_CCU6_MCMOUTS_Bits.CURHS */
+#define IFX_CCU6_MCMOUTS_CURHS_MSK (0x7u)
+
+/** \brief Offset for Ifx_CCU6_MCMOUTS_Bits.CURHS */
+#define IFX_CCU6_MCMOUTS_CURHS_OFF (11u)
+
+/** \brief Length for Ifx_CCU6_MCMOUTS_Bits.EXPHS */
+#define IFX_CCU6_MCMOUTS_EXPHS_LEN (3u)
+
+/** \brief Mask for Ifx_CCU6_MCMOUTS_Bits.EXPHS */
+#define IFX_CCU6_MCMOUTS_EXPHS_MSK (0x7u)
+
+/** \brief Offset for Ifx_CCU6_MCMOUTS_Bits.EXPHS */
+#define IFX_CCU6_MCMOUTS_EXPHS_OFF (8u)
+
+/** \brief Length for Ifx_CCU6_MCMOUTS_Bits.MCMPS */
+#define IFX_CCU6_MCMOUTS_MCMPS_LEN (6u)
+
+/** \brief Mask for Ifx_CCU6_MCMOUTS_Bits.MCMPS */
+#define IFX_CCU6_MCMOUTS_MCMPS_MSK (0x3fu)
+
+/** \brief Offset for Ifx_CCU6_MCMOUTS_Bits.MCMPS */
+#define IFX_CCU6_MCMOUTS_MCMPS_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_MCMOUTS_Bits.STRHP */
+#define IFX_CCU6_MCMOUTS_STRHP_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_MCMOUTS_Bits.STRHP */
+#define IFX_CCU6_MCMOUTS_STRHP_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_MCMOUTS_Bits.STRHP */
+#define IFX_CCU6_MCMOUTS_STRHP_OFF (15u)
+
+/** \brief Length for Ifx_CCU6_MCMOUTS_Bits.STRMCM */
+#define IFX_CCU6_MCMOUTS_STRMCM_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_MCMOUTS_Bits.STRMCM */
+#define IFX_CCU6_MCMOUTS_STRMCM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_MCMOUTS_Bits.STRMCM */
+#define IFX_CCU6_MCMOUTS_STRMCM_OFF (7u)
+
+/** \brief Length for Ifx_CCU6_MODCTR_Bits.ECT13O */
+#define IFX_CCU6_MODCTR_ECT13O_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_MODCTR_Bits.ECT13O */
+#define IFX_CCU6_MODCTR_ECT13O_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_MODCTR_Bits.ECT13O */
+#define IFX_CCU6_MODCTR_ECT13O_OFF (15u)
+
+/** \brief Length for Ifx_CCU6_MODCTR_Bits.MCMEN */
+#define IFX_CCU6_MODCTR_MCMEN_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_MODCTR_Bits.MCMEN */
+#define IFX_CCU6_MODCTR_MCMEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_MODCTR_Bits.MCMEN */
+#define IFX_CCU6_MODCTR_MCMEN_OFF (7u)
+
+/** \brief Length for Ifx_CCU6_MODCTR_Bits.T12MODEN */
+#define IFX_CCU6_MODCTR_T12MODEN_LEN (6u)
+
+/** \brief Mask for Ifx_CCU6_MODCTR_Bits.T12MODEN */
+#define IFX_CCU6_MODCTR_T12MODEN_MSK (0x3fu)
+
+/** \brief Offset for Ifx_CCU6_MODCTR_Bits.T12MODEN */
+#define IFX_CCU6_MODCTR_T12MODEN_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_MODCTR_Bits.T13MODEN */
+#define IFX_CCU6_MODCTR_T13MODEN_LEN (6u)
+
+/** \brief Mask for Ifx_CCU6_MODCTR_Bits.T13MODEN */
+#define IFX_CCU6_MODCTR_T13MODEN_MSK (0x3fu)
+
+/** \brief Offset for Ifx_CCU6_MODCTR_Bits.T13MODEN */
+#define IFX_CCU6_MODCTR_T13MODEN_OFF (8u)
+
+/** \brief Length for Ifx_CCU6_MOSEL_Bits.TRIG0SEL */
+#define IFX_CCU6_MOSEL_TRIG0SEL_LEN (3u)
+
+/** \brief Mask for Ifx_CCU6_MOSEL_Bits.TRIG0SEL */
+#define IFX_CCU6_MOSEL_TRIG0SEL_MSK (0x7u)
+
+/** \brief Offset for Ifx_CCU6_MOSEL_Bits.TRIG0SEL */
+#define IFX_CCU6_MOSEL_TRIG0SEL_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_MOSEL_Bits.TRIG1SEL */
+#define IFX_CCU6_MOSEL_TRIG1SEL_LEN (3u)
+
+/** \brief Mask for Ifx_CCU6_MOSEL_Bits.TRIG1SEL */
+#define IFX_CCU6_MOSEL_TRIG1SEL_MSK (0x7u)
+
+/** \brief Offset for Ifx_CCU6_MOSEL_Bits.TRIG1SEL */
+#define IFX_CCU6_MOSEL_TRIG1SEL_OFF (3u)
+
+/** \brief Length for Ifx_CCU6_MOSEL_Bits.TRIG2SEL */
+#define IFX_CCU6_MOSEL_TRIG2SEL_LEN (3u)
+
+/** \brief Mask for Ifx_CCU6_MOSEL_Bits.TRIG2SEL */
+#define IFX_CCU6_MOSEL_TRIG2SEL_MSK (0x7u)
+
+/** \brief Offset for Ifx_CCU6_MOSEL_Bits.TRIG2SEL */
+#define IFX_CCU6_MOSEL_TRIG2SEL_OFF (6u)
+
+/** \brief Length for Ifx_CCU6_OCS_Bits.SUS */
+#define IFX_CCU6_OCS_SUS_LEN (4u)
+
+/** \brief Mask for Ifx_CCU6_OCS_Bits.SUS */
+#define IFX_CCU6_OCS_SUS_MSK (0xfu)
+
+/** \brief Offset for Ifx_CCU6_OCS_Bits.SUS */
+#define IFX_CCU6_OCS_SUS_OFF (24u)
+
+/** \brief Length for Ifx_CCU6_OCS_Bits.SUS_P */
+#define IFX_CCU6_OCS_SUS_P_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_OCS_Bits.SUS_P */
+#define IFX_CCU6_OCS_SUS_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_OCS_Bits.SUS_P */
+#define IFX_CCU6_OCS_SUS_P_OFF (28u)
+
+/** \brief Length for Ifx_CCU6_OCS_Bits.SUSSTA */
+#define IFX_CCU6_OCS_SUSSTA_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_OCS_Bits.SUSSTA */
+#define IFX_CCU6_OCS_SUSSTA_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_OCS_Bits.SUSSTA */
+#define IFX_CCU6_OCS_SUSSTA_OFF (29u)
+
+/** \brief Length for Ifx_CCU6_OCS_Bits.TG_P */
+#define IFX_CCU6_OCS_TG_P_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_OCS_Bits.TG_P */
+#define IFX_CCU6_OCS_TG_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_OCS_Bits.TG_P */
+#define IFX_CCU6_OCS_TG_P_OFF (3u)
+
+/** \brief Length for Ifx_CCU6_OCS_Bits.TGB */
+#define IFX_CCU6_OCS_TGB_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_OCS_Bits.TGB */
+#define IFX_CCU6_OCS_TGB_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_OCS_Bits.TGB */
+#define IFX_CCU6_OCS_TGB_OFF (2u)
+
+/** \brief Length for Ifx_CCU6_OCS_Bits.TGS */
+#define IFX_CCU6_OCS_TGS_LEN (2u)
+
+/** \brief Mask for Ifx_CCU6_OCS_Bits.TGS */
+#define IFX_CCU6_OCS_TGS_MSK (0x3u)
+
+/** \brief Offset for Ifx_CCU6_OCS_Bits.TGS */
+#define IFX_CCU6_OCS_TGS_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_PISEL0_Bits.ISCC60 */
+#define IFX_CCU6_PISEL0_ISCC60_LEN (2u)
+
+/** \brief Mask for Ifx_CCU6_PISEL0_Bits.ISCC60 */
+#define IFX_CCU6_PISEL0_ISCC60_MSK (0x3u)
+
+/** \brief Offset for Ifx_CCU6_PISEL0_Bits.ISCC60 */
+#define IFX_CCU6_PISEL0_ISCC60_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_PISEL0_Bits.ISCC61 */
+#define IFX_CCU6_PISEL0_ISCC61_LEN (2u)
+
+/** \brief Mask for Ifx_CCU6_PISEL0_Bits.ISCC61 */
+#define IFX_CCU6_PISEL0_ISCC61_MSK (0x3u)
+
+/** \brief Offset for Ifx_CCU6_PISEL0_Bits.ISCC61 */
+#define IFX_CCU6_PISEL0_ISCC61_OFF (2u)
+
+/** \brief Length for Ifx_CCU6_PISEL0_Bits.ISCC62 */
+#define IFX_CCU6_PISEL0_ISCC62_LEN (2u)
+
+/** \brief Mask for Ifx_CCU6_PISEL0_Bits.ISCC62 */
+#define IFX_CCU6_PISEL0_ISCC62_MSK (0x3u)
+
+/** \brief Offset for Ifx_CCU6_PISEL0_Bits.ISCC62 */
+#define IFX_CCU6_PISEL0_ISCC62_OFF (4u)
+
+/** \brief Length for Ifx_CCU6_PISEL0_Bits.ISPOS0 */
+#define IFX_CCU6_PISEL0_ISPOS0_LEN (2u)
+
+/** \brief Mask for Ifx_CCU6_PISEL0_Bits.ISPOS0 */
+#define IFX_CCU6_PISEL0_ISPOS0_MSK (0x3u)
+
+/** \brief Offset for Ifx_CCU6_PISEL0_Bits.ISPOS0 */
+#define IFX_CCU6_PISEL0_ISPOS0_OFF (8u)
+
+/** \brief Length for Ifx_CCU6_PISEL0_Bits.ISPOS1 */
+#define IFX_CCU6_PISEL0_ISPOS1_LEN (2u)
+
+/** \brief Mask for Ifx_CCU6_PISEL0_Bits.ISPOS1 */
+#define IFX_CCU6_PISEL0_ISPOS1_MSK (0x3u)
+
+/** \brief Offset for Ifx_CCU6_PISEL0_Bits.ISPOS1 */
+#define IFX_CCU6_PISEL0_ISPOS1_OFF (10u)
+
+/** \brief Length for Ifx_CCU6_PISEL0_Bits.ISPOS2 */
+#define IFX_CCU6_PISEL0_ISPOS2_LEN (2u)
+
+/** \brief Mask for Ifx_CCU6_PISEL0_Bits.ISPOS2 */
+#define IFX_CCU6_PISEL0_ISPOS2_MSK (0x3u)
+
+/** \brief Offset for Ifx_CCU6_PISEL0_Bits.ISPOS2 */
+#define IFX_CCU6_PISEL0_ISPOS2_OFF (12u)
+
+/** \brief Length for Ifx_CCU6_PISEL0_Bits.IST12HR */
+#define IFX_CCU6_PISEL0_IST12HR_LEN (2u)
+
+/** \brief Mask for Ifx_CCU6_PISEL0_Bits.IST12HR */
+#define IFX_CCU6_PISEL0_IST12HR_MSK (0x3u)
+
+/** \brief Offset for Ifx_CCU6_PISEL0_Bits.IST12HR */
+#define IFX_CCU6_PISEL0_IST12HR_OFF (14u)
+
+/** \brief Length for Ifx_CCU6_PISEL0_Bits.ISTRP */
+#define IFX_CCU6_PISEL0_ISTRP_LEN (2u)
+
+/** \brief Mask for Ifx_CCU6_PISEL0_Bits.ISTRP */
+#define IFX_CCU6_PISEL0_ISTRP_MSK (0x3u)
+
+/** \brief Offset for Ifx_CCU6_PISEL0_Bits.ISTRP */
+#define IFX_CCU6_PISEL0_ISTRP_OFF (6u)
+
+/** \brief Length for Ifx_CCU6_PISEL2_Bits.ISCNT12 */
+#define IFX_CCU6_PISEL2_ISCNT12_LEN (2u)
+
+/** \brief Mask for Ifx_CCU6_PISEL2_Bits.ISCNT12 */
+#define IFX_CCU6_PISEL2_ISCNT12_MSK (0x3u)
+
+/** \brief Offset for Ifx_CCU6_PISEL2_Bits.ISCNT12 */
+#define IFX_CCU6_PISEL2_ISCNT12_OFF (2u)
+
+/** \brief Length for Ifx_CCU6_PISEL2_Bits.ISCNT13 */
+#define IFX_CCU6_PISEL2_ISCNT13_LEN (2u)
+
+/** \brief Mask for Ifx_CCU6_PISEL2_Bits.ISCNT13 */
+#define IFX_CCU6_PISEL2_ISCNT13_MSK (0x3u)
+
+/** \brief Offset for Ifx_CCU6_PISEL2_Bits.ISCNT13 */
+#define IFX_CCU6_PISEL2_ISCNT13_OFF (4u)
+
+/** \brief Length for Ifx_CCU6_PISEL2_Bits.IST13HR */
+#define IFX_CCU6_PISEL2_IST13HR_LEN (2u)
+
+/** \brief Mask for Ifx_CCU6_PISEL2_Bits.IST13HR */
+#define IFX_CCU6_PISEL2_IST13HR_MSK (0x3u)
+
+/** \brief Offset for Ifx_CCU6_PISEL2_Bits.IST13HR */
+#define IFX_CCU6_PISEL2_IST13HR_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_PISEL2_Bits.T12EXT */
+#define IFX_CCU6_PISEL2_T12EXT_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_PISEL2_Bits.T12EXT */
+#define IFX_CCU6_PISEL2_T12EXT_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_PISEL2_Bits.T12EXT */
+#define IFX_CCU6_PISEL2_T12EXT_OFF (6u)
+
+/** \brief Length for Ifx_CCU6_PISEL2_Bits.T13EXT */
+#define IFX_CCU6_PISEL2_T13EXT_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_PISEL2_Bits.T13EXT */
+#define IFX_CCU6_PISEL2_T13EXT_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_PISEL2_Bits.T13EXT */
+#define IFX_CCU6_PISEL2_T13EXT_OFF (7u)
+
+/** \brief Length for Ifx_CCU6_PSLR_Bits.PSL63 */
+#define IFX_CCU6_PSLR_PSL63_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_PSLR_Bits.PSL63 */
+#define IFX_CCU6_PSLR_PSL63_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_PSLR_Bits.PSL63 */
+#define IFX_CCU6_PSLR_PSL63_OFF (7u)
+
+/** \brief Length for Ifx_CCU6_PSLR_Bits.PSL */
+#define IFX_CCU6_PSLR_PSL_LEN (6u)
+
+/** \brief Mask for Ifx_CCU6_PSLR_Bits.PSL */
+#define IFX_CCU6_PSLR_PSL_MSK (0x3fu)
+
+/** \brief Offset for Ifx_CCU6_PSLR_Bits.PSL */
+#define IFX_CCU6_PSLR_PSL_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_T12_Bits.T12CV */
+#define IFX_CCU6_T12_T12CV_LEN (16u)
+
+/** \brief Mask for Ifx_CCU6_T12_Bits.T12CV */
+#define IFX_CCU6_T12_T12CV_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CCU6_T12_Bits.T12CV */
+#define IFX_CCU6_T12_T12CV_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_T12DTC_Bits.DTE0 */
+#define IFX_CCU6_T12DTC_DTE0_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_T12DTC_Bits.DTE0 */
+#define IFX_CCU6_T12DTC_DTE0_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_T12DTC_Bits.DTE0 */
+#define IFX_CCU6_T12DTC_DTE0_OFF (8u)
+
+/** \brief Length for Ifx_CCU6_T12DTC_Bits.DTE1 */
+#define IFX_CCU6_T12DTC_DTE1_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_T12DTC_Bits.DTE1 */
+#define IFX_CCU6_T12DTC_DTE1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_T12DTC_Bits.DTE1 */
+#define IFX_CCU6_T12DTC_DTE1_OFF (9u)
+
+/** \brief Length for Ifx_CCU6_T12DTC_Bits.DTE2 */
+#define IFX_CCU6_T12DTC_DTE2_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_T12DTC_Bits.DTE2 */
+#define IFX_CCU6_T12DTC_DTE2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_T12DTC_Bits.DTE2 */
+#define IFX_CCU6_T12DTC_DTE2_OFF (10u)
+
+/** \brief Length for Ifx_CCU6_T12DTC_Bits.DTM */
+#define IFX_CCU6_T12DTC_DTM_LEN (8u)
+
+/** \brief Mask for Ifx_CCU6_T12DTC_Bits.DTM */
+#define IFX_CCU6_T12DTC_DTM_MSK (0xffu)
+
+/** \brief Offset for Ifx_CCU6_T12DTC_Bits.DTM */
+#define IFX_CCU6_T12DTC_DTM_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_T12DTC_Bits.DTR0 */
+#define IFX_CCU6_T12DTC_DTR0_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_T12DTC_Bits.DTR0 */
+#define IFX_CCU6_T12DTC_DTR0_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_T12DTC_Bits.DTR0 */
+#define IFX_CCU6_T12DTC_DTR0_OFF (12u)
+
+/** \brief Length for Ifx_CCU6_T12DTC_Bits.DTR1 */
+#define IFX_CCU6_T12DTC_DTR1_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_T12DTC_Bits.DTR1 */
+#define IFX_CCU6_T12DTC_DTR1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_T12DTC_Bits.DTR1 */
+#define IFX_CCU6_T12DTC_DTR1_OFF (13u)
+
+/** \brief Length for Ifx_CCU6_T12DTC_Bits.DTR2 */
+#define IFX_CCU6_T12DTC_DTR2_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_T12DTC_Bits.DTR2 */
+#define IFX_CCU6_T12DTC_DTR2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_T12DTC_Bits.DTR2 */
+#define IFX_CCU6_T12DTC_DTR2_OFF (14u)
+
+/** \brief Length for Ifx_CCU6_T12MSEL_Bits.DBYP */
+#define IFX_CCU6_T12MSEL_DBYP_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_T12MSEL_Bits.DBYP */
+#define IFX_CCU6_T12MSEL_DBYP_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_T12MSEL_Bits.DBYP */
+#define IFX_CCU6_T12MSEL_DBYP_OFF (15u)
+
+/** \brief Length for Ifx_CCU6_T12MSEL_Bits.HSYNC */
+#define IFX_CCU6_T12MSEL_HSYNC_LEN (3u)
+
+/** \brief Mask for Ifx_CCU6_T12MSEL_Bits.HSYNC */
+#define IFX_CCU6_T12MSEL_HSYNC_MSK (0x7u)
+
+/** \brief Offset for Ifx_CCU6_T12MSEL_Bits.HSYNC */
+#define IFX_CCU6_T12MSEL_HSYNC_OFF (12u)
+
+/** \brief Length for Ifx_CCU6_T12MSEL_Bits.MSEL60 */
+#define IFX_CCU6_T12MSEL_MSEL60_LEN (4u)
+
+/** \brief Mask for Ifx_CCU6_T12MSEL_Bits.MSEL60 */
+#define IFX_CCU6_T12MSEL_MSEL60_MSK (0xfu)
+
+/** \brief Offset for Ifx_CCU6_T12MSEL_Bits.MSEL60 */
+#define IFX_CCU6_T12MSEL_MSEL60_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_T12MSEL_Bits.MSEL61 */
+#define IFX_CCU6_T12MSEL_MSEL61_LEN (4u)
+
+/** \brief Mask for Ifx_CCU6_T12MSEL_Bits.MSEL61 */
+#define IFX_CCU6_T12MSEL_MSEL61_MSK (0xfu)
+
+/** \brief Offset for Ifx_CCU6_T12MSEL_Bits.MSEL61 */
+#define IFX_CCU6_T12MSEL_MSEL61_OFF (4u)
+
+/** \brief Length for Ifx_CCU6_T12MSEL_Bits.MSEL62 */
+#define IFX_CCU6_T12MSEL_MSEL62_LEN (4u)
+
+/** \brief Mask for Ifx_CCU6_T12MSEL_Bits.MSEL62 */
+#define IFX_CCU6_T12MSEL_MSEL62_MSK (0xfu)
+
+/** \brief Offset for Ifx_CCU6_T12MSEL_Bits.MSEL62 */
+#define IFX_CCU6_T12MSEL_MSEL62_OFF (8u)
+
+/** \brief Length for Ifx_CCU6_T12PR_Bits.T12PV */
+#define IFX_CCU6_T12PR_T12PV_LEN (16u)
+
+/** \brief Mask for Ifx_CCU6_T12PR_Bits.T12PV */
+#define IFX_CCU6_T12PR_T12PV_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CCU6_T12PR_Bits.T12PV */
+#define IFX_CCU6_T12PR_T12PV_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_T13_Bits.T13CV */
+#define IFX_CCU6_T13_T13CV_LEN (16u)
+
+/** \brief Mask for Ifx_CCU6_T13_Bits.T13CV */
+#define IFX_CCU6_T13_T13CV_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CCU6_T13_Bits.T13CV */
+#define IFX_CCU6_T13_T13CV_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_T13PR_Bits.T13PV */
+#define IFX_CCU6_T13PR_T13PV_LEN (16u)
+
+/** \brief Mask for Ifx_CCU6_T13PR_Bits.T13PV */
+#define IFX_CCU6_T13PR_T13PV_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CCU6_T13PR_Bits.T13PV */
+#define IFX_CCU6_T13PR_T13PV_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_TCTR0_Bits.CDIR */
+#define IFX_CCU6_TCTR0_CDIR_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_TCTR0_Bits.CDIR */
+#define IFX_CCU6_TCTR0_CDIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_TCTR0_Bits.CDIR */
+#define IFX_CCU6_TCTR0_CDIR_OFF (6u)
+
+/** \brief Length for Ifx_CCU6_TCTR0_Bits.CTM */
+#define IFX_CCU6_TCTR0_CTM_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_TCTR0_Bits.CTM */
+#define IFX_CCU6_TCTR0_CTM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_TCTR0_Bits.CTM */
+#define IFX_CCU6_TCTR0_CTM_OFF (7u)
+
+/** \brief Length for Ifx_CCU6_TCTR0_Bits.STE12 */
+#define IFX_CCU6_TCTR0_STE12_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_TCTR0_Bits.STE12 */
+#define IFX_CCU6_TCTR0_STE12_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_TCTR0_Bits.STE12 */
+#define IFX_CCU6_TCTR0_STE12_OFF (5u)
+
+/** \brief Length for Ifx_CCU6_TCTR0_Bits.STE13 */
+#define IFX_CCU6_TCTR0_STE13_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_TCTR0_Bits.STE13 */
+#define IFX_CCU6_TCTR0_STE13_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_TCTR0_Bits.STE13 */
+#define IFX_CCU6_TCTR0_STE13_OFF (13u)
+
+/** \brief Length for Ifx_CCU6_TCTR0_Bits.T12CLK */
+#define IFX_CCU6_TCTR0_T12CLK_LEN (3u)
+
+/** \brief Mask for Ifx_CCU6_TCTR0_Bits.T12CLK */
+#define IFX_CCU6_TCTR0_T12CLK_MSK (0x7u)
+
+/** \brief Offset for Ifx_CCU6_TCTR0_Bits.T12CLK */
+#define IFX_CCU6_TCTR0_T12CLK_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_TCTR0_Bits.T12PRE */
+#define IFX_CCU6_TCTR0_T12PRE_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_TCTR0_Bits.T12PRE */
+#define IFX_CCU6_TCTR0_T12PRE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_TCTR0_Bits.T12PRE */
+#define IFX_CCU6_TCTR0_T12PRE_OFF (3u)
+
+/** \brief Length for Ifx_CCU6_TCTR0_Bits.T12R */
+#define IFX_CCU6_TCTR0_T12R_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_TCTR0_Bits.T12R */
+#define IFX_CCU6_TCTR0_T12R_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_TCTR0_Bits.T12R */
+#define IFX_CCU6_TCTR0_T12R_OFF (4u)
+
+/** \brief Length for Ifx_CCU6_TCTR0_Bits.T13CLK */
+#define IFX_CCU6_TCTR0_T13CLK_LEN (3u)
+
+/** \brief Mask for Ifx_CCU6_TCTR0_Bits.T13CLK */
+#define IFX_CCU6_TCTR0_T13CLK_MSK (0x7u)
+
+/** \brief Offset for Ifx_CCU6_TCTR0_Bits.T13CLK */
+#define IFX_CCU6_TCTR0_T13CLK_OFF (8u)
+
+/** \brief Length for Ifx_CCU6_TCTR0_Bits.T13PRE */
+#define IFX_CCU6_TCTR0_T13PRE_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_TCTR0_Bits.T13PRE */
+#define IFX_CCU6_TCTR0_T13PRE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_TCTR0_Bits.T13PRE */
+#define IFX_CCU6_TCTR0_T13PRE_OFF (11u)
+
+/** \brief Length for Ifx_CCU6_TCTR0_Bits.T13R */
+#define IFX_CCU6_TCTR0_T13R_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_TCTR0_Bits.T13R */
+#define IFX_CCU6_TCTR0_T13R_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_TCTR0_Bits.T13R */
+#define IFX_CCU6_TCTR0_T13R_OFF (12u)
+
+/** \brief Length for Ifx_CCU6_TCTR2_Bits.T12RSEL */
+#define IFX_CCU6_TCTR2_T12RSEL_LEN (2u)
+
+/** \brief Mask for Ifx_CCU6_TCTR2_Bits.T12RSEL */
+#define IFX_CCU6_TCTR2_T12RSEL_MSK (0x3u)
+
+/** \brief Offset for Ifx_CCU6_TCTR2_Bits.T12RSEL */
+#define IFX_CCU6_TCTR2_T12RSEL_OFF (8u)
+
+/** \brief Length for Ifx_CCU6_TCTR2_Bits.T12SSC */
+#define IFX_CCU6_TCTR2_T12SSC_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_TCTR2_Bits.T12SSC */
+#define IFX_CCU6_TCTR2_T12SSC_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_TCTR2_Bits.T12SSC */
+#define IFX_CCU6_TCTR2_T12SSC_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_TCTR2_Bits.T13RSEL */
+#define IFX_CCU6_TCTR2_T13RSEL_LEN (2u)
+
+/** \brief Mask for Ifx_CCU6_TCTR2_Bits.T13RSEL */
+#define IFX_CCU6_TCTR2_T13RSEL_MSK (0x3u)
+
+/** \brief Offset for Ifx_CCU6_TCTR2_Bits.T13RSEL */
+#define IFX_CCU6_TCTR2_T13RSEL_OFF (10u)
+
+/** \brief Length for Ifx_CCU6_TCTR2_Bits.T13SSC */
+#define IFX_CCU6_TCTR2_T13SSC_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_TCTR2_Bits.T13SSC */
+#define IFX_CCU6_TCTR2_T13SSC_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_TCTR2_Bits.T13SSC */
+#define IFX_CCU6_TCTR2_T13SSC_OFF (1u)
+
+/** \brief Length for Ifx_CCU6_TCTR2_Bits.T13TEC */
+#define IFX_CCU6_TCTR2_T13TEC_LEN (3u)
+
+/** \brief Mask for Ifx_CCU6_TCTR2_Bits.T13TEC */
+#define IFX_CCU6_TCTR2_T13TEC_MSK (0x7u)
+
+/** \brief Offset for Ifx_CCU6_TCTR2_Bits.T13TEC */
+#define IFX_CCU6_TCTR2_T13TEC_OFF (2u)
+
+/** \brief Length for Ifx_CCU6_TCTR2_Bits.T13TED */
+#define IFX_CCU6_TCTR2_T13TED_LEN (2u)
+
+/** \brief Mask for Ifx_CCU6_TCTR2_Bits.T13TED */
+#define IFX_CCU6_TCTR2_T13TED_MSK (0x3u)
+
+/** \brief Offset for Ifx_CCU6_TCTR2_Bits.T13TED */
+#define IFX_CCU6_TCTR2_T13TED_OFF (5u)
+
+/** \brief Length for Ifx_CCU6_TCTR4_Bits.DTRES */
+#define IFX_CCU6_TCTR4_DTRES_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_TCTR4_Bits.DTRES */
+#define IFX_CCU6_TCTR4_DTRES_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_TCTR4_Bits.DTRES */
+#define IFX_CCU6_TCTR4_DTRES_OFF (3u)
+
+/** \brief Length for Ifx_CCU6_TCTR4_Bits.T12CNT */
+#define IFX_CCU6_TCTR4_T12CNT_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_TCTR4_Bits.T12CNT */
+#define IFX_CCU6_TCTR4_T12CNT_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_TCTR4_Bits.T12CNT */
+#define IFX_CCU6_TCTR4_T12CNT_OFF (5u)
+
+/** \brief Length for Ifx_CCU6_TCTR4_Bits.T12RES */
+#define IFX_CCU6_TCTR4_T12RES_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_TCTR4_Bits.T12RES */
+#define IFX_CCU6_TCTR4_T12RES_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_TCTR4_Bits.T12RES */
+#define IFX_CCU6_TCTR4_T12RES_OFF (2u)
+
+/** \brief Length for Ifx_CCU6_TCTR4_Bits.T12RR */
+#define IFX_CCU6_TCTR4_T12RR_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_TCTR4_Bits.T12RR */
+#define IFX_CCU6_TCTR4_T12RR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_TCTR4_Bits.T12RR */
+#define IFX_CCU6_TCTR4_T12RR_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_TCTR4_Bits.T12RS */
+#define IFX_CCU6_TCTR4_T12RS_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_TCTR4_Bits.T12RS */
+#define IFX_CCU6_TCTR4_T12RS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_TCTR4_Bits.T12RS */
+#define IFX_CCU6_TCTR4_T12RS_OFF (1u)
+
+/** \brief Length for Ifx_CCU6_TCTR4_Bits.T12STD */
+#define IFX_CCU6_TCTR4_T12STD_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_TCTR4_Bits.T12STD */
+#define IFX_CCU6_TCTR4_T12STD_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_TCTR4_Bits.T12STD */
+#define IFX_CCU6_TCTR4_T12STD_OFF (7u)
+
+/** \brief Length for Ifx_CCU6_TCTR4_Bits.T12STR */
+#define IFX_CCU6_TCTR4_T12STR_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_TCTR4_Bits.T12STR */
+#define IFX_CCU6_TCTR4_T12STR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_TCTR4_Bits.T12STR */
+#define IFX_CCU6_TCTR4_T12STR_OFF (6u)
+
+/** \brief Length for Ifx_CCU6_TCTR4_Bits.T13CNT */
+#define IFX_CCU6_TCTR4_T13CNT_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_TCTR4_Bits.T13CNT */
+#define IFX_CCU6_TCTR4_T13CNT_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_TCTR4_Bits.T13CNT */
+#define IFX_CCU6_TCTR4_T13CNT_OFF (13u)
+
+/** \brief Length for Ifx_CCU6_TCTR4_Bits.T13RES */
+#define IFX_CCU6_TCTR4_T13RES_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_TCTR4_Bits.T13RES */
+#define IFX_CCU6_TCTR4_T13RES_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_TCTR4_Bits.T13RES */
+#define IFX_CCU6_TCTR4_T13RES_OFF (10u)
+
+/** \brief Length for Ifx_CCU6_TCTR4_Bits.T13RR */
+#define IFX_CCU6_TCTR4_T13RR_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_TCTR4_Bits.T13RR */
+#define IFX_CCU6_TCTR4_T13RR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_TCTR4_Bits.T13RR */
+#define IFX_CCU6_TCTR4_T13RR_OFF (8u)
+
+/** \brief Length for Ifx_CCU6_TCTR4_Bits.T13RS */
+#define IFX_CCU6_TCTR4_T13RS_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_TCTR4_Bits.T13RS */
+#define IFX_CCU6_TCTR4_T13RS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_TCTR4_Bits.T13RS */
+#define IFX_CCU6_TCTR4_T13RS_OFF (9u)
+
+/** \brief Length for Ifx_CCU6_TCTR4_Bits.T13STD */
+#define IFX_CCU6_TCTR4_T13STD_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_TCTR4_Bits.T13STD */
+#define IFX_CCU6_TCTR4_T13STD_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_TCTR4_Bits.T13STD */
+#define IFX_CCU6_TCTR4_T13STD_OFF (15u)
+
+/** \brief Length for Ifx_CCU6_TCTR4_Bits.T13STR */
+#define IFX_CCU6_TCTR4_T13STR_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_TCTR4_Bits.T13STR */
+#define IFX_CCU6_TCTR4_T13STR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_TCTR4_Bits.T13STR */
+#define IFX_CCU6_TCTR4_T13STR_OFF (14u)
+
+/** \brief Length for Ifx_CCU6_TRPCTR_Bits.TRPEN13 */
+#define IFX_CCU6_TRPCTR_TRPEN13_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_TRPCTR_Bits.TRPEN13 */
+#define IFX_CCU6_TRPCTR_TRPEN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_TRPCTR_Bits.TRPEN13 */
+#define IFX_CCU6_TRPCTR_TRPEN13_OFF (14u)
+
+/** \brief Length for Ifx_CCU6_TRPCTR_Bits.TRPEN */
+#define IFX_CCU6_TRPCTR_TRPEN_LEN (6u)
+
+/** \brief Mask for Ifx_CCU6_TRPCTR_Bits.TRPEN */
+#define IFX_CCU6_TRPCTR_TRPEN_MSK (0x3fu)
+
+/** \brief Offset for Ifx_CCU6_TRPCTR_Bits.TRPEN */
+#define IFX_CCU6_TRPCTR_TRPEN_OFF (8u)
+
+/** \brief Length for Ifx_CCU6_TRPCTR_Bits.TRPM0 */
+#define IFX_CCU6_TRPCTR_TRPM0_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_TRPCTR_Bits.TRPM0 */
+#define IFX_CCU6_TRPCTR_TRPM0_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_TRPCTR_Bits.TRPM0 */
+#define IFX_CCU6_TRPCTR_TRPM0_OFF (0u)
+
+/** \brief Length for Ifx_CCU6_TRPCTR_Bits.TRPM1 */
+#define IFX_CCU6_TRPCTR_TRPM1_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_TRPCTR_Bits.TRPM1 */
+#define IFX_CCU6_TRPCTR_TRPM1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_TRPCTR_Bits.TRPM1 */
+#define IFX_CCU6_TRPCTR_TRPM1_OFF (1u)
+
+/** \brief Length for Ifx_CCU6_TRPCTR_Bits.TRPM2 */
+#define IFX_CCU6_TRPCTR_TRPM2_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_TRPCTR_Bits.TRPM2 */
+#define IFX_CCU6_TRPCTR_TRPM2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_TRPCTR_Bits.TRPM2 */
+#define IFX_CCU6_TRPCTR_TRPM2_OFF (2u)
+
+/** \brief Length for Ifx_CCU6_TRPCTR_Bits.TRPPEN */
+#define IFX_CCU6_TRPCTR_TRPPEN_LEN (1u)
+
+/** \brief Mask for Ifx_CCU6_TRPCTR_Bits.TRPPEN */
+#define IFX_CCU6_TRPCTR_TRPPEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CCU6_TRPCTR_Bits.TRPPEN */
+#define IFX_CCU6_TRPCTR_TRPPEN_OFF (15u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXCCU6_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCcu6_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCcu6_reg.h
new file mode 100644
index 0000000..bd9ed5d
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCcu6_reg.h
@@ -0,0 +1,329 @@
+/**
+ * \file IfxCcu6_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Ccu6_Cfg Ccu6 address
+ * \ingroup IfxLld_Ccu6
+ *
+ * \defgroup IfxLld_Ccu6_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Ccu6_Cfg
+ *
+ * \defgroup IfxLld_Ccu6_Cfg_Ccu60 2-CCU60
+ * \ingroup IfxLld_Ccu6_Cfg
+ *
+ * \defgroup IfxLld_Ccu6_Cfg_Ccu61 2-CCU61
+ * \ingroup IfxLld_Ccu6_Cfg
+ *
+ */
+#ifndef IFXCCU6_REG_H
+#define IFXCCU6_REG_H 1
+/******************************************************************************/
+#include "IfxCcu6_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Ccu6_Cfg_BaseAddress
+ * \{ */
+
+/** \brief CCU6 object */
+#define MODULE_CCU60 /*lint --e(923)*/ (*(Ifx_CCU6*)0xF0002A00u)
+
+/** \brief CCU6 object */
+#define MODULE_CCU61 /*lint --e(923)*/ (*(Ifx_CCU6*)0xF0002B00u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Ccu6_Cfg_Ccu60
+ * \{ */
+
+/** \brief FC, Access Enable Register 0 */
+#define CCU60_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_CCU6_ACCEN0*)0xF0002AFCu)
+
+/** \brief F8, Access Enable Register 1 */
+#define CCU60_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_CCU6_ACCEN1*)0xF0002AF8u)
+
+/** \brief 30, Capture/Compare Register for Channel CC60 */
+#define CCU60_CC60R /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC60R*)0xF0002A30u)
+
+/** \brief 40, Capture/Compare Shadow Reg. for Channel CC60 */
+#define CCU60_CC60SR /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC60SR*)0xF0002A40u)
+
+/** \brief 34, Capture/Compare Register for Channel CC61 */
+#define CCU60_CC61R /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC61R*)0xF0002A34u)
+
+/** \brief 44, Capture/Compare Shadow Reg. for Channel CC61 */
+#define CCU60_CC61SR /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC61SR*)0xF0002A44u)
+
+/** \brief 38, Capture/Compare Register for Channel CC62 */
+#define CCU60_CC62R /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC62R*)0xF0002A38u)
+
+/** \brief 48, Capture/Compare Shadow Reg. for Channel CC62 */
+#define CCU60_CC62SR /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC62SR*)0xF0002A48u)
+
+/** \brief 58, Compare Register for T13 */
+#define CCU60_CC63R /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC63R*)0xF0002A58u)
+
+/** \brief 5C, Compare Shadow Register for T13 */
+#define CCU60_CC63SR /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC63SR*)0xF0002A5Cu)
+
+/** \brief 0, Clock Control Register */
+#define CCU60_CLC /*lint --e(923)*/ (*(volatile Ifx_CCU6_CLC*)0xF0002A00u)
+
+/** \brief 64, Compare State Modification Register */
+#define CCU60_CMPMODIF /*lint --e(923)*/ (*(volatile Ifx_CCU6_CMPMODIF*)0xF0002A64u)
+
+/** \brief 60, Compare State Register */
+#define CCU60_CMPSTAT /*lint --e(923)*/ (*(volatile Ifx_CCU6_CMPSTAT*)0xF0002A60u)
+
+/** \brief 8, Module Identification Register */
+#define CCU60_ID /*lint --e(923)*/ (*(volatile Ifx_CCU6_ID*)0xF0002A08u)
+
+/** \brief B0, Interrupt Enable Register */
+#define CCU60_IEN /*lint --e(923)*/ (*(volatile Ifx_CCU6_IEN*)0xF0002AB0u)
+
+/** \brief 98, Input Monitoring Register */
+#define CCU60_IMON /*lint --e(923)*/ (*(volatile Ifx_CCU6_IMON*)0xF0002A98u)
+
+/** \brief AC, Interrupt Node Pointer Register */
+#define CCU60_INP /*lint --e(923)*/ (*(volatile Ifx_CCU6_INP*)0xF0002AACu)
+
+/** \brief A0, Interrupt Status Register */
+#define CCU60_IS /*lint --e(923)*/ (*(volatile Ifx_CCU6_IS*)0xF0002AA0u)
+
+/** \brief A8, Interrupt Status Reset Register */
+#define CCU60_ISR /*lint --e(923)*/ (*(volatile Ifx_CCU6_ISR*)0xF0002AA8u)
+
+/** \brief A4, Interrupt Status Set Register */
+#define CCU60_ISS /*lint --e(923)*/ (*(volatile Ifx_CCU6_ISS*)0xF0002AA4u)
+
+/** \brief F4, Kernel Reset Register 0 */
+#define CCU60_KRST0 /*lint --e(923)*/ (*(volatile Ifx_CCU6_KRST0*)0xF0002AF4u)
+
+/** \brief F0, Kernel Reset Register 1 */
+#define CCU60_KRST1 /*lint --e(923)*/ (*(volatile Ifx_CCU6_KRST1*)0xF0002AF0u)
+
+/** \brief EC, Kernel Reset Status Clear Register */
+#define CCU60_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_CCU6_KRSTCLR*)0xF0002AECu)
+
+/** \brief 1C, Kernel State Control Sensitivity Register */
+#define CCU60_KSCSR /*lint --e(923)*/ (*(volatile Ifx_CCU6_KSCSR*)0xF0002A1Cu)
+
+/** \brief 9C, Lost Indicator Register */
+#define CCU60_LI /*lint --e(923)*/ (*(volatile Ifx_CCU6_LI*)0xF0002A9Cu)
+
+/** \brief 4, Module Configuration Register */
+#define CCU60_MCFG /*lint --e(923)*/ (*(volatile Ifx_CCU6_MCFG*)0xF0002A04u)
+
+/** \brief 94, Multi-Channel Mode Control Register */
+#define CCU60_MCMCTR /*lint --e(923)*/ (*(volatile Ifx_CCU6_MCMCTR*)0xF0002A94u)
+
+/** \brief 90, Multi-Channel Mode Output Register */
+#define CCU60_MCMOUT /*lint --e(923)*/ (*(volatile Ifx_CCU6_MCMOUT*)0xF0002A90u)
+
+/** \brief 8C, Multi-Channel Mode Output Shadow Register */
+#define CCU60_MCMOUTS /*lint --e(923)*/ (*(volatile Ifx_CCU6_MCMOUTS*)0xF0002A8Cu)
+
+/** \brief 80, Modulation Control Register */
+#define CCU60_MODCTR /*lint --e(923)*/ (*(volatile Ifx_CCU6_MODCTR*)0xF0002A80u)
+
+/** \brief C, CCU60 Module Output Select Register */
+#define CCU60_MOSEL /*lint --e(923)*/ (*(volatile Ifx_CCU6_MOSEL*)0xF0002A0Cu)
+
+/** \brief E8, OCDS Control and Status Register */
+#define CCU60_OCS /*lint --e(923)*/ (*(volatile Ifx_CCU6_OCS*)0xF0002AE8u)
+
+/** \brief 10, Port Input Select Register 0 */
+#define CCU60_PISEL0 /*lint --e(923)*/ (*(volatile Ifx_CCU6_PISEL0*)0xF0002A10u)
+
+/** \brief 14, Port Input Select Register 2 */
+#define CCU60_PISEL2 /*lint --e(923)*/ (*(volatile Ifx_CCU6_PISEL2*)0xF0002A14u)
+
+/** \brief 88, Passive State Level Register */
+#define CCU60_PSLR /*lint --e(923)*/ (*(volatile Ifx_CCU6_PSLR*)0xF0002A88u)
+
+/** \brief 20, Timer T12 Counter Register */
+#define CCU60_T12 /*lint --e(923)*/ (*(volatile Ifx_CCU6_T12*)0xF0002A20u)
+
+/** \brief 28, Dead-Time Control Register for Timer12 */
+#define CCU60_T12DTC /*lint --e(923)*/ (*(volatile Ifx_CCU6_T12DTC*)0xF0002A28u)
+
+/** \brief 68, T12 Mode Select Register */
+#define CCU60_T12MSEL /*lint --e(923)*/ (*(volatile Ifx_CCU6_T12MSEL*)0xF0002A68u)
+
+/** \brief 24, Timer 12 Period Register */
+#define CCU60_T12PR /*lint --e(923)*/ (*(volatile Ifx_CCU6_T12PR*)0xF0002A24u)
+
+/** \brief 50, Timer T13 Counter Register */
+#define CCU60_T13 /*lint --e(923)*/ (*(volatile Ifx_CCU6_T13*)0xF0002A50u)
+
+/** \brief 54, Timer 13 Period Register */
+#define CCU60_T13PR /*lint --e(923)*/ (*(volatile Ifx_CCU6_T13PR*)0xF0002A54u)
+
+/** \brief 70, Timer Control Register 0 */
+#define CCU60_TCTR0 /*lint --e(923)*/ (*(volatile Ifx_CCU6_TCTR0*)0xF0002A70u)
+
+/** \brief 74, Timer Control Register 2 */
+#define CCU60_TCTR2 /*lint --e(923)*/ (*(volatile Ifx_CCU6_TCTR2*)0xF0002A74u)
+
+/** \brief 78, Timer Control Register 4 */
+#define CCU60_TCTR4 /*lint --e(923)*/ (*(volatile Ifx_CCU6_TCTR4*)0xF0002A78u)
+
+/** \brief 84, Trap Control Register */
+#define CCU60_TRPCTR /*lint --e(923)*/ (*(volatile Ifx_CCU6_TRPCTR*)0xF0002A84u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Ccu6_Cfg_Ccu61
+ * \{ */
+
+/** \brief FC, Access Enable Register 0 */
+#define CCU61_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_CCU6_ACCEN0*)0xF0002BFCu)
+
+/** \brief F8, Access Enable Register 1 */
+#define CCU61_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_CCU6_ACCEN1*)0xF0002BF8u)
+
+/** \brief 30, Capture/Compare Register for Channel CC60 */
+#define CCU61_CC60R /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC60R*)0xF0002B30u)
+
+/** \brief 40, Capture/Compare Shadow Reg. for Channel CC60 */
+#define CCU61_CC60SR /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC60SR*)0xF0002B40u)
+
+/** \brief 34, Capture/Compare Register for Channel CC61 */
+#define CCU61_CC61R /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC61R*)0xF0002B34u)
+
+/** \brief 44, Capture/Compare Shadow Reg. for Channel CC61 */
+#define CCU61_CC61SR /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC61SR*)0xF0002B44u)
+
+/** \brief 38, Capture/Compare Register for Channel CC62 */
+#define CCU61_CC62R /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC62R*)0xF0002B38u)
+
+/** \brief 48, Capture/Compare Shadow Reg. for Channel CC62 */
+#define CCU61_CC62SR /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC62SR*)0xF0002B48u)
+
+/** \brief 58, Compare Register for T13 */
+#define CCU61_CC63R /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC63R*)0xF0002B58u)
+
+/** \brief 5C, Compare Shadow Register for T13 */
+#define CCU61_CC63SR /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC63SR*)0xF0002B5Cu)
+
+/** \brief 0, Clock Control Register */
+#define CCU61_CLC /*lint --e(923)*/ (*(volatile Ifx_CCU6_CLC*)0xF0002B00u)
+
+/** \brief 64, Compare State Modification Register */
+#define CCU61_CMPMODIF /*lint --e(923)*/ (*(volatile Ifx_CCU6_CMPMODIF*)0xF0002B64u)
+
+/** \brief 60, Compare State Register */
+#define CCU61_CMPSTAT /*lint --e(923)*/ (*(volatile Ifx_CCU6_CMPSTAT*)0xF0002B60u)
+
+/** \brief 8, Module Identification Register */
+#define CCU61_ID /*lint --e(923)*/ (*(volatile Ifx_CCU6_ID*)0xF0002B08u)
+
+/** \brief B0, Interrupt Enable Register */
+#define CCU61_IEN /*lint --e(923)*/ (*(volatile Ifx_CCU6_IEN*)0xF0002BB0u)
+
+/** \brief 98, Input Monitoring Register */
+#define CCU61_IMON /*lint --e(923)*/ (*(volatile Ifx_CCU6_IMON*)0xF0002B98u)
+
+/** \brief AC, Interrupt Node Pointer Register */
+#define CCU61_INP /*lint --e(923)*/ (*(volatile Ifx_CCU6_INP*)0xF0002BACu)
+
+/** \brief A0, Interrupt Status Register */
+#define CCU61_IS /*lint --e(923)*/ (*(volatile Ifx_CCU6_IS*)0xF0002BA0u)
+
+/** \brief A8, Interrupt Status Reset Register */
+#define CCU61_ISR /*lint --e(923)*/ (*(volatile Ifx_CCU6_ISR*)0xF0002BA8u)
+
+/** \brief A4, Interrupt Status Set Register */
+#define CCU61_ISS /*lint --e(923)*/ (*(volatile Ifx_CCU6_ISS*)0xF0002BA4u)
+
+/** \brief F4, Kernel Reset Register 0 */
+#define CCU61_KRST0 /*lint --e(923)*/ (*(volatile Ifx_CCU6_KRST0*)0xF0002BF4u)
+
+/** \brief F0, Kernel Reset Register 1 */
+#define CCU61_KRST1 /*lint --e(923)*/ (*(volatile Ifx_CCU6_KRST1*)0xF0002BF0u)
+
+/** \brief EC, Kernel Reset Status Clear Register */
+#define CCU61_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_CCU6_KRSTCLR*)0xF0002BECu)
+
+/** \brief 1C, Kernel State Control Sensitivity Register */
+#define CCU61_KSCSR /*lint --e(923)*/ (*(volatile Ifx_CCU6_KSCSR*)0xF0002B1Cu)
+
+/** \brief 9C, Lost Indicator Register */
+#define CCU61_LI /*lint --e(923)*/ (*(volatile Ifx_CCU6_LI*)0xF0002B9Cu)
+
+/** \brief 4, Module Configuration Register */
+#define CCU61_MCFG /*lint --e(923)*/ (*(volatile Ifx_CCU6_MCFG*)0xF0002B04u)
+
+/** \brief 94, Multi-Channel Mode Control Register */
+#define CCU61_MCMCTR /*lint --e(923)*/ (*(volatile Ifx_CCU6_MCMCTR*)0xF0002B94u)
+
+/** \brief 90, Multi-Channel Mode Output Register */
+#define CCU61_MCMOUT /*lint --e(923)*/ (*(volatile Ifx_CCU6_MCMOUT*)0xF0002B90u)
+
+/** \brief 8C, Multi-Channel Mode Output Shadow Register */
+#define CCU61_MCMOUTS /*lint --e(923)*/ (*(volatile Ifx_CCU6_MCMOUTS*)0xF0002B8Cu)
+
+/** \brief 80, Modulation Control Register */
+#define CCU61_MODCTR /*lint --e(923)*/ (*(volatile Ifx_CCU6_MODCTR*)0xF0002B80u)
+
+/** \brief E8, OCDS Control and Status Register */
+#define CCU61_OCS /*lint --e(923)*/ (*(volatile Ifx_CCU6_OCS*)0xF0002BE8u)
+
+/** \brief 10, Port Input Select Register 0 */
+#define CCU61_PISEL0 /*lint --e(923)*/ (*(volatile Ifx_CCU6_PISEL0*)0xF0002B10u)
+
+/** \brief 14, Port Input Select Register 2 */
+#define CCU61_PISEL2 /*lint --e(923)*/ (*(volatile Ifx_CCU6_PISEL2*)0xF0002B14u)
+
+/** \brief 88, Passive State Level Register */
+#define CCU61_PSLR /*lint --e(923)*/ (*(volatile Ifx_CCU6_PSLR*)0xF0002B88u)
+
+/** \brief 20, Timer T12 Counter Register */
+#define CCU61_T12 /*lint --e(923)*/ (*(volatile Ifx_CCU6_T12*)0xF0002B20u)
+
+/** \brief 28, Dead-Time Control Register for Timer12 */
+#define CCU61_T12DTC /*lint --e(923)*/ (*(volatile Ifx_CCU6_T12DTC*)0xF0002B28u)
+
+/** \brief 68, T12 Mode Select Register */
+#define CCU61_T12MSEL /*lint --e(923)*/ (*(volatile Ifx_CCU6_T12MSEL*)0xF0002B68u)
+
+/** \brief 24, Timer 12 Period Register */
+#define CCU61_T12PR /*lint --e(923)*/ (*(volatile Ifx_CCU6_T12PR*)0xF0002B24u)
+
+/** \brief 50, Timer T13 Counter Register */
+#define CCU61_T13 /*lint --e(923)*/ (*(volatile Ifx_CCU6_T13*)0xF0002B50u)
+
+/** \brief 54, Timer 13 Period Register */
+#define CCU61_T13PR /*lint --e(923)*/ (*(volatile Ifx_CCU6_T13PR*)0xF0002B54u)
+
+/** \brief 70, Timer Control Register 0 */
+#define CCU61_TCTR0 /*lint --e(923)*/ (*(volatile Ifx_CCU6_TCTR0*)0xF0002B70u)
+
+/** \brief 74, Timer Control Register 2 */
+#define CCU61_TCTR2 /*lint --e(923)*/ (*(volatile Ifx_CCU6_TCTR2*)0xF0002B74u)
+
+/** \brief 78, Timer Control Register 4 */
+#define CCU61_TCTR4 /*lint --e(923)*/ (*(volatile Ifx_CCU6_TCTR4*)0xF0002B78u)
+
+/** \brief 84, Trap Control Register */
+#define CCU61_TRPCTR /*lint --e(923)*/ (*(volatile Ifx_CCU6_TRPCTR*)0xF0002B84u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXCCU6_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCcu6_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCcu6_regdef.h
new file mode 100644
index 0000000..8dc237d
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCcu6_regdef.h
@@ -0,0 +1,1032 @@
+/**
+ * \file IfxCcu6_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Ccu6 Ccu6
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Ccu6_Bitfields Bitfields
+ * \ingroup IfxLld_Ccu6
+ *
+ * \defgroup IfxLld_Ccu6_union Union
+ * \ingroup IfxLld_Ccu6
+ *
+ * \defgroup IfxLld_Ccu6_struct Struct
+ * \ingroup IfxLld_Ccu6
+ *
+ */
+#ifndef IFXCCU6_REGDEF_H
+#define IFXCCU6_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Ccu6_Bitfields
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef struct _Ifx_CCU6_ACCEN0_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_CCU6_ACCEN0_Bits;
+
+/** \brief Access Enable Register 1 */
+typedef struct _Ifx_CCU6_ACCEN1_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_CCU6_ACCEN1_Bits;
+
+/** \brief Capture/Compare Register for Channel CC60 */
+typedef struct _Ifx_CCU6_CC60R_Bits
+{
+ unsigned int CCV:16; /**< \brief [15:0] Capture/Compare Value (rh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CCU6_CC60R_Bits;
+
+/** \brief Capture/Compare Shadow Reg. for Channel CC60 */
+typedef struct _Ifx_CCU6_CC60SR_Bits
+{
+ unsigned int CCS:16; /**< \brief [15:0] Shadow Register for Channel x Capture/Compare Value (rwh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CCU6_CC60SR_Bits;
+
+/** \brief Capture/Compare Register for Channel CC61 */
+typedef struct _Ifx_CCU6_CC61R_Bits
+{
+ unsigned int CCV:16; /**< \brief [15:0] Capture/Compare Value (rh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CCU6_CC61R_Bits;
+
+/** \brief Capture/Compare Shadow Reg. for Channel CC61 */
+typedef struct _Ifx_CCU6_CC61SR_Bits
+{
+ unsigned int CCS:16; /**< \brief [15:0] Shadow Register for Channel x Capture/Compare Value (rwh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CCU6_CC61SR_Bits;
+
+/** \brief Capture/Compare Register for Channel CC62 */
+typedef struct _Ifx_CCU6_CC62R_Bits
+{
+ unsigned int CCV:16; /**< \brief [15:0] Capture/Compare Value (rh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CCU6_CC62R_Bits;
+
+/** \brief Capture/Compare Shadow Reg. for Channel CC62 */
+typedef struct _Ifx_CCU6_CC62SR_Bits
+{
+ unsigned int CCS:16; /**< \brief [15:0] Shadow Register for Channel x Capture/Compare Value (rwh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CCU6_CC62SR_Bits;
+
+/** \brief Compare Register for T13 */
+typedef struct _Ifx_CCU6_CC63R_Bits
+{
+ unsigned int CCV:16; /**< \brief [15:0] Channel CC63 Compare Value (rh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CCU6_CC63R_Bits;
+
+/** \brief Compare Shadow Register for T13 */
+typedef struct _Ifx_CCU6_CC63SR_Bits
+{
+ unsigned int CCS:16; /**< \brief [15:0] Shadow Register for Channel CC63 Compare Value (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CCU6_CC63SR_Bits;
+
+/** \brief Clock Control Register */
+typedef struct _Ifx_CCU6_CLC_Bits
+{
+ unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
+ unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
+ unsigned int reserved_2:1; /**< \brief \internal Reserved */
+ unsigned int EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control (rw) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_CCU6_CLC_Bits;
+
+/** \brief Compare State Modification Register */
+typedef struct _Ifx_CCU6_CMPMODIF_Bits
+{
+ unsigned int MCC60S:1; /**< \brief [0:0] Capture/Compare Status Modification Bits (w) */
+ unsigned int MCC61S:1; /**< \brief [1:1] Capture/Compare Status Modification Bits (w) */
+ unsigned int MCC62S:1; /**< \brief [2:2] Capture/Compare Status Modification Bits (w) */
+ unsigned int reserved_3:3; /**< \brief \internal Reserved */
+ unsigned int MCC63S:1; /**< \brief [6:6] Capture/Compare Status Modification Bits (w) */
+ unsigned int reserved_7:1; /**< \brief \internal Reserved */
+ unsigned int MCC60R:1; /**< \brief [8:8] Capture/Compare Status Modification Bits (w) */
+ unsigned int MCC61R:1; /**< \brief [9:9] Capture/Compare Status Modification Bits (w) */
+ unsigned int MCC62R:1; /**< \brief [10:10] Capture/Compare Status Modification Bits (w) */
+ unsigned int reserved_11:3; /**< \brief \internal Reserved */
+ unsigned int MCC63R:1; /**< \brief [14:14] Capture/Compare Status Modification Bits (w) */
+ unsigned int reserved_15:17; /**< \brief \internal Reserved */
+} Ifx_CCU6_CMPMODIF_Bits;
+
+/** \brief Compare State Register */
+typedef struct _Ifx_CCU6_CMPSTAT_Bits
+{
+ unsigned int CC60ST:1; /**< \brief [0:0] Capture/Compare State Bits (rh) */
+ unsigned int CC61ST:1; /**< \brief [1:1] Capture/Compare State Bits (rh) */
+ unsigned int CC62ST:1; /**< \brief [2:2] Capture/Compare State Bits (rh) */
+ unsigned int CCPOS60:1; /**< \brief [3:3] Sampled Hall Pattern Bits (rh) */
+ unsigned int CCPOS61:1; /**< \brief [4:4] Sampled Hall Pattern Bits (rh) */
+ unsigned int CCPOS62:1; /**< \brief [5:5] Sampled Hall Pattern Bits (rh) */
+ unsigned int CC63ST:1; /**< \brief [6:6] Capture/Compare State Bits (rh) */
+ unsigned int reserved_7:1; /**< \brief \internal Reserved */
+ unsigned int CC60PS:1; /**< \brief [8:8] Passive State Select for Compare Outputs (rwh) */
+ unsigned int COUT60PS:1; /**< \brief [9:9] Passive State Select for Compare Outputs (rwh) */
+ unsigned int CC61PS:1; /**< \brief [10:10] Passive State Select for Compare Outputs (rwh) */
+ unsigned int COUT61PS:1; /**< \brief [11:11] Passive State Select for Compare Outputs (rwh) */
+ unsigned int CC62PS:1; /**< \brief [12:12] Passive State Select for Compare Outputs (rwh) */
+ unsigned int COUT62PS:1; /**< \brief [13:13] Passive State Select for Compare Outputs (rwh) */
+ unsigned int COUT63PS:1; /**< \brief [14:14] Passive State Select for Compare Outputs (rwh) */
+ unsigned int T13IM:1; /**< \brief [15:15] T13 Inverted Modulation (rwh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CCU6_CMPSTAT_Bits;
+
+/** \brief Module Identification Register */
+typedef struct _Ifx_CCU6_ID_Bits
+{
+ unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ unsigned int MODNUMBER:8; /**< \brief [15:8] Module Number Value (r) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CCU6_ID_Bits;
+
+/** \brief Interrupt Enable Register */
+typedef struct _Ifx_CCU6_IEN_Bits
+{
+ unsigned int ENCC60R:1; /**< \brief [0:0] Capture, Compare-Match Rising Edge Interrupt Enable for Channel CC6x (rw) */
+ unsigned int ENCC60F:1; /**< \brief [1:1] Capture, Compare-Match Falling Edge Interrupt Enable for Channel CC6x (rw) */
+ unsigned int ENCC61R:1; /**< \brief [2:2] Capture, Compare-Match Rising Edge Interrupt Enable for Channel CC6x (rw) */
+ unsigned int ENCC61F:1; /**< \brief [3:3] Capture, Compare-Match Falling Edge Interrupt Enable for Channel CC6x (rw) */
+ unsigned int ENCC62R:1; /**< \brief [4:4] Capture, Compare-Match Rising Edge Interrupt Enable for Channel CC6x (rw) */
+ unsigned int ENCC62F:1; /**< \brief [5:5] Capture, Compare-Match Falling Edge Interrupt Enable for Channel CC6x (rw) */
+ unsigned int ENT12OM:1; /**< \brief [6:6] Enable Interrupt for T12 One-Match (rw) */
+ unsigned int ENT12PM:1; /**< \brief [7:7] Enable Interrupt for T12 Period-Match (rw) */
+ unsigned int ENT13CM:1; /**< \brief [8:8] Enable Interrupt for T13 Compare-Match (rw) */
+ unsigned int ENT13PM:1; /**< \brief [9:9] Enable Interrupt for T13 Period-Match (rw) */
+ unsigned int ENTRPF:1; /**< \brief [10:10] Enable Interrupt for Trap Flag (rw) */
+ unsigned int reserved_11:1; /**< \brief \internal Reserved */
+ unsigned int ENCHE:1; /**< \brief [12:12] Enable Interrupt for Correct Hall Event (rw) */
+ unsigned int ENWHE:1; /**< \brief [13:13] Enable Interrupt for Wrong Hall Event (rw) */
+ unsigned int ENIDLE:1; /**< \brief [14:14] Enable Idle (rw) */
+ unsigned int ENSTR:1; /**< \brief [15:15] Enable Multi-Channel Mode Shadow Transfer Interrupt (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CCU6_IEN_Bits;
+
+/** \brief Input Monitoring Register */
+typedef struct _Ifx_CCU6_IMON_Bits
+{
+ unsigned int LBE:1; /**< \brief [0:0] Lost Bit Event (rwh) */
+ unsigned int CCPOS0I:1; /**< \brief [1:1] Event indication for input signal CCPOS0 (rwh) */
+ unsigned int CCPOS1I:1; /**< \brief [2:2] Event indication for input signal CCPOS1 (rwh) */
+ unsigned int CCPOS2I:1; /**< \brief [3:3] Event indication for input signal CCPOS2 (rwh) */
+ unsigned int CC60INI:1; /**< \brief [4:4] Event indication for input signal CC60IN (rwh) */
+ unsigned int CC61INI:1; /**< \brief [5:5] Event indication for input signal CC61IN (rwh) */
+ unsigned int CC62INI:1; /**< \brief [6:6] Event indication for input signal CC62IN (rwh) */
+ unsigned int CTRAPI:1; /**< \brief [7:7] Event indication for input signal CTRAP (rwh) */
+ unsigned int T12HRI:1; /**< \brief [8:8] Event indication for input signal T12HR (rwh) */
+ unsigned int T13HRI:1; /**< \brief [9:9] Event indication for input signal T13HR (rwh) */
+ unsigned int reserved_10:22; /**< \brief \internal Reserved */
+} Ifx_CCU6_IMON_Bits;
+
+/** \brief Interrupt Node Pointer Register */
+typedef struct _Ifx_CCU6_INP_Bits
+{
+ unsigned int INPCC60:2; /**< \brief [1:0] Interrupt Node Pointer for Channel CC6x Interrupts (rw) */
+ unsigned int INPCC61:2; /**< \brief [3:2] Interrupt Node Pointer for Channel CC6x Interrupts (rw) */
+ unsigned int INPCC62:2; /**< \brief [5:4] Interrupt Node Pointer for Channel CC6x Interrupts (rw) */
+ unsigned int INPCHE:2; /**< \brief [7:6] Interrupt Node Pointer for the CHE Interrupt (rw) */
+ unsigned int INPERR:2; /**< \brief [9:8] Interrupt Node Pointer for Error Interrupts (rw) */
+ unsigned int INPT12:2; /**< \brief [11:10] Interrupt Node Pointer for Timer12 Interrupts (rw) */
+ unsigned int INPT13:2; /**< \brief [13:12] Interrupt Node Pointer for Timer13 Interrupt (rw) */
+ unsigned int reserved_14:18; /**< \brief \internal Reserved */
+} Ifx_CCU6_INP_Bits;
+
+/** \brief Interrupt Status Register */
+typedef struct _Ifx_CCU6_IS_Bits
+{
+ unsigned int ICC60R:1; /**< \brief [0:0] Capture, Compare-Match Rising Edge Flag (rh) */
+ unsigned int ICC60F:1; /**< \brief [1:1] Capture, Compare-Match Falling Edge Flag (rh) */
+ unsigned int ICC61R:1; /**< \brief [2:2] Capture, Compare-Match Rising Edge Flag (rh) */
+ unsigned int ICC61F:1; /**< \brief [3:3] Capture, Compare-Match Falling Edge Flag (rh) */
+ unsigned int ICC62R:1; /**< \brief [4:4] Capture, Compare-Match Rising Edge Flag (rh) */
+ unsigned int ICC62F:1; /**< \brief [5:5] Capture, Compare-Match Falling Edge Flag (rh) */
+ unsigned int T12OM:1; /**< \brief [6:6] Timer T12 One-Match Flag (rh) */
+ unsigned int T12PM:1; /**< \brief [7:7] Timer T12 Period-Match Flag (rh) */
+ unsigned int T13CM:1; /**< \brief [8:8] Timer T13 Compare-Match Flag (rh) */
+ unsigned int T13PM:1; /**< \brief [9:9] Timer T13 Period-Match Flag (rh) */
+ unsigned int TRPF:1; /**< \brief [10:10] Trap Flag (rh) */
+ unsigned int TRPS:1; /**< \brief [11:11] Trap State (rh) */
+ unsigned int CHE:1; /**< \brief [12:12] Correct Hall Event (rh) */
+ unsigned int WHE:1; /**< \brief [13:13] Wrong Hall Event (rh) */
+ unsigned int IDLE:1; /**< \brief [14:14] IDLE State (rh) */
+ unsigned int STR:1; /**< \brief [15:15] Multi-Channel Mode Shadow Transfer Request (rh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CCU6_IS_Bits;
+
+/** \brief Interrupt Status Reset Register */
+typedef struct _Ifx_CCU6_ISR_Bits
+{
+ unsigned int RCC60R:1; /**< \brief [0:0] Reset Capture, Compare-Match Rising Edge Flag (w) */
+ unsigned int RCC60F:1; /**< \brief [1:1] Reset Capture, Compare-Match Falling Edge Flag (w) */
+ unsigned int RCC61R:1; /**< \brief [2:2] Reset Capture, Compare-Match Rising Edge Flag (w) */
+ unsigned int RCC61F:1; /**< \brief [3:3] Reset Capture, Compare-Match Falling Edge Flag (w) */
+ unsigned int RCC62R:1; /**< \brief [4:4] Reset Capture, Compare-Match Rising Edge Flag (w) */
+ unsigned int RCC62F:1; /**< \brief [5:5] Reset Capture, Compare-Match Falling Edge Flag (w) */
+ unsigned int RT12OM:1; /**< \brief [6:6] Reset Timer T12 One-Match Flag (w) */
+ unsigned int RT12PM:1; /**< \brief [7:7] Reset Timer T12 Period-Match Flag (w) */
+ unsigned int RT13CM:1; /**< \brief [8:8] Reset Timer T13 Compare-Match Flag (w) */
+ unsigned int RT13PM:1; /**< \brief [9:9] Reset Timer T13 Period-Match Flag (w) */
+ unsigned int RTRPF:1; /**< \brief [10:10] Reset Trap Flag (w) */
+ unsigned int reserved_11:1; /**< \brief \internal Reserved */
+ unsigned int RCHE:1; /**< \brief [12:12] Reset Correct Hall Event Flag (w) */
+ unsigned int RWHE:1; /**< \brief [13:13] Reset Wrong Hall Event Flag (w) */
+ unsigned int RIDLE:1; /**< \brief [14:14] Reset IDLE Flag (w) */
+ unsigned int RSTR:1; /**< \brief [15:15] Reset STR Flag (w) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CCU6_ISR_Bits;
+
+/** \brief Interrupt Status Set Register */
+typedef struct _Ifx_CCU6_ISS_Bits
+{
+ unsigned int SCC60R:1; /**< \brief [0:0] Set Capture, Compare-Match Rising Edge Flag (w) */
+ unsigned int SCC60F:1; /**< \brief [1:1] Set Capture, Compare-Match Falling Edge Flag (w) */
+ unsigned int SCC61R:1; /**< \brief [2:2] Set Capture, Compare-Match Rising Edge Flag (w) */
+ unsigned int SCC61F:1; /**< \brief [3:3] Set Capture, Compare-Match Falling Edge Flag (w) */
+ unsigned int SCC62R:1; /**< \brief [4:4] Set Capture, Compare-Match Rising Edge Flag (w) */
+ unsigned int SCC62F:1; /**< \brief [5:5] Set Capture, Compare-Match Falling Edge Flag (w) */
+ unsigned int ST12OM:1; /**< \brief [6:6] Set Timer T12 One-Match Flag (w) */
+ unsigned int ST12PM:1; /**< \brief [7:7] Set Timer T12 Period-Match Flag (w) */
+ unsigned int ST13CM:1; /**< \brief [8:8] Set Timer T13 Compare-Match Flag (w) */
+ unsigned int ST13PM:1; /**< \brief [9:9] Set Timer T13 Period-Match Flag (w) */
+ unsigned int STRPF:1; /**< \brief [10:10] Set Trap Flag (w) */
+ unsigned int SWHC:1; /**< \brief [11:11] Software Hall Compare (w) */
+ unsigned int SCHE:1; /**< \brief [12:12] Set Correct Hall Event Flag (w) */
+ unsigned int SWHE:1; /**< \brief [13:13] Set Wrong Hall Event Flag (w) */
+ unsigned int SIDLE:1; /**< \brief [14:14] Set IDLE Flag (w) */
+ unsigned int SSTR:1; /**< \brief [15:15] Set STR Flag (w) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CCU6_ISS_Bits;
+
+/** \brief Kernel Reset Register 0 */
+typedef struct _Ifx_CCU6_KRST0_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rh) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_CCU6_KRST0_Bits;
+
+/** \brief Kernel Reset Register 1 */
+typedef struct _Ifx_CCU6_KRST1_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_CCU6_KRST1_Bits;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef struct _Ifx_CCU6_KRSTCLR_Bits
+{
+ unsigned int CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_CCU6_KRSTCLR_Bits;
+
+/** \brief Kernel State Control Sensitivity Register */
+typedef struct _Ifx_CCU6_KSCSR_Bits
+{
+ unsigned int SB0:1; /**< \brief [0:0] Sensitivity Block x (rw) */
+ unsigned int SB1:1; /**< \brief [1:1] Sensitivity Block x (rw) */
+ unsigned int SB2:1; /**< \brief [2:2] Sensitivity Block x (rw) */
+ unsigned int SB3:1; /**< \brief [3:3] Sensitivity Block x (rw) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_CCU6_KSCSR_Bits;
+
+/** \brief Lost Indicator Register */
+typedef struct _Ifx_CCU6_LI_Bits
+{
+ unsigned int reserved_0:1; /**< \brief \internal Reserved */
+ unsigned int CCPOS0EN:1; /**< \brief [1:1] Lost Indicator Enable for input signal CCPOS0 (rw) */
+ unsigned int CCPOS1EN:1; /**< \brief [2:2] Lost Indicator Enable for input signal CCPOS1 (rw) */
+ unsigned int CCPOS2EN:1; /**< \brief [3:3] Lost Indicator Enable for input signal CCPOS2 (rw) */
+ unsigned int CC60INEN:1; /**< \brief [4:4] Lost Indicator Enable for input signal CC60IN (rw) */
+ unsigned int CC61INEN:1; /**< \brief [5:5] Lost Indicator Enable for input signal CC61IN (rw) */
+ unsigned int CC62INEN:1; /**< \brief [6:6] Lost Indicator Enable for input signal CC62IN (rw) */
+ unsigned int CTRAPEN:1; /**< \brief [7:7] Lost Indicator Enable for input signal CTRAP (rw) */
+ unsigned int T12HREN:1; /**< \brief [8:8] Lost Indicator Enable for input signal T12HR (rw) */
+ unsigned int T13HREN:1; /**< \brief [9:9] Lost Indicator Enable for input signal T13HR (rw) */
+ unsigned int reserved_10:3; /**< \brief \internal Reserved */
+ unsigned int LBEEN:1; /**< \brief [13:13] Interrupt Enable for Lost Bit Event (rw) */
+ unsigned int INPLBE:2; /**< \brief [15:14] Interrupt Node Pointer for lost bit event (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CCU6_LI_Bits;
+
+/** \brief Module Configuration Register */
+typedef struct _Ifx_CCU6_MCFG_Bits
+{
+ unsigned int T12:1; /**< \brief [0:0] T12 Available (r) */
+ unsigned int T13:1; /**< \brief [1:1] T13 Available (r) */
+ unsigned int MCM:1; /**< \brief [2:2] Multi-Channel Mode Available (r) */
+ unsigned int reserved_3:29; /**< \brief \internal Reserved */
+} Ifx_CCU6_MCFG_Bits;
+
+/** \brief Multi-Channel Mode Control Register */
+typedef struct _Ifx_CCU6_MCMCTR_Bits
+{
+ unsigned int SWSEL:3; /**< \brief [2:0] Switching Selection (rw) */
+ unsigned int reserved_3:1; /**< \brief \internal Reserved */
+ unsigned int SWSYN:2; /**< \brief [5:4] Switching Synchronization (rw) */
+ unsigned int reserved_6:2; /**< \brief \internal Reserved */
+ unsigned int STE12U:1; /**< \brief [8:8] Shadow Transfer Enable for T12 Upcounting (rw) */
+ unsigned int STE12D:1; /**< \brief [9:9] Shadow Transfer Enable for T12 Downcounting (rw) */
+ unsigned int STE13U:1; /**< \brief [10:10] Shadow Transfer Enable for T13 Upcounting (rw) */
+ unsigned int reserved_11:21; /**< \brief \internal Reserved */
+} Ifx_CCU6_MCMCTR_Bits;
+
+/** \brief Multi-Channel Mode Output Register */
+typedef struct _Ifx_CCU6_MCMOUT_Bits
+{
+ unsigned int MCMP:6; /**< \brief [5:0] Multi-Channel PWM Pattern (rh) */
+ unsigned int R:1; /**< \brief [6:6] Reminder Flag (rh) */
+ unsigned int reserved_7:1; /**< \brief \internal Reserved */
+ unsigned int EXPH:3; /**< \brief [10:8] Expected Hall Pattern (rh) */
+ unsigned int CURH:3; /**< \brief [13:11] Current Hall Pattern (rh) */
+ unsigned int reserved_14:18; /**< \brief \internal Reserved */
+} Ifx_CCU6_MCMOUT_Bits;
+
+/** \brief Multi-Channel Mode Output Shadow Register */
+typedef struct _Ifx_CCU6_MCMOUTS_Bits
+{
+ unsigned int MCMPS:6; /**< \brief [5:0] Multi-Channel PWM Pattern Shadow (rw) */
+ unsigned int reserved_6:1; /**< \brief \internal Reserved */
+ unsigned int STRMCM:1; /**< \brief [7:7] Shadow Transfer Request for MCMPS (w) */
+ unsigned int EXPHS:3; /**< \brief [10:8] Expected Hall Pattern Shadow (rw) */
+ unsigned int CURHS:3; /**< \brief [13:11] Current Hall Pattern Shadow (rw) */
+ unsigned int reserved_14:1; /**< \brief \internal Reserved */
+ unsigned int STRHP:1; /**< \brief [15:15] Shadow Transfer Request for the Hall Pattern (w) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CCU6_MCMOUTS_Bits;
+
+/** \brief Modulation Control Register */
+typedef struct _Ifx_CCU6_MODCTR_Bits
+{
+ unsigned int T12MODEN:6; /**< \brief [5:0] T12 Modulation Enable (rw) */
+ unsigned int reserved_6:1; /**< \brief \internal Reserved */
+ unsigned int MCMEN:1; /**< \brief [7:7] Multi-Channel Mode Enable (rw) */
+ unsigned int T13MODEN:6; /**< \brief [13:8] T13 Modulation Enable (rw) */
+ unsigned int reserved_14:1; /**< \brief \internal Reserved */
+ unsigned int ECT13O:1; /**< \brief [15:15] Enable Compare Timer T13 Output (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CCU6_MODCTR_Bits;
+
+/** \brief CCU60 Module Output Select Register */
+typedef struct _Ifx_CCU6_MOSEL_Bits
+{
+ unsigned int TRIG0SEL:3; /**< \brief [2:0] (rw) */
+ unsigned int TRIG1SEL:3; /**< \brief [5:3] (rw) */
+ unsigned int TRIG2SEL:3; /**< \brief [8:6] (rw) */
+ unsigned int reserved_9:23; /**< \brief \internal Reserved */
+} Ifx_CCU6_MOSEL_Bits;
+
+/** \brief OCDS Control and Status Register */
+typedef struct _Ifx_CCU6_OCS_Bits
+{
+ unsigned int TGS:2; /**< \brief [1:0] Trigger Set for OTGB0/1 (rw) */
+ unsigned int TGB:1; /**< \brief [2:2] OTGB0/1 Bus Select (rw) */
+ unsigned int TG_P:1; /**< \brief [3:3] TGS, TGB Write Protection (w) */
+ unsigned int reserved_4:20; /**< \brief \internal Reserved */
+ unsigned int SUS:4; /**< \brief [27:24] OCDS Suspend Control (rw) */
+ unsigned int SUS_P:1; /**< \brief [28:28] SUS Write Protection (w) */
+ unsigned int SUSSTA:1; /**< \brief [29:29] Suspend State (rh) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_CCU6_OCS_Bits;
+
+/** \brief Port Input Select Register 0 */
+typedef struct _Ifx_CCU6_PISEL0_Bits
+{
+ unsigned int ISCC60:2; /**< \brief [1:0] Input Select for CC60 (rw) */
+ unsigned int ISCC61:2; /**< \brief [3:2] Input Select for CC61 (rw) */
+ unsigned int ISCC62:2; /**< \brief [5:4] Input Select for CC62 (rw) */
+ unsigned int ISTRP:2; /**< \brief [7:6] Input Select for CTRAP (rw) */
+ unsigned int ISPOS0:2; /**< \brief [9:8] Input Select for CCPOS0 (rw) */
+ unsigned int ISPOS1:2; /**< \brief [11:10] Input Select for CCPOS1 (rw) */
+ unsigned int ISPOS2:2; /**< \brief [13:12] Input Select for CCPOS2 (rw) */
+ unsigned int IST12HR:2; /**< \brief [15:14] Input Select for T12HR (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CCU6_PISEL0_Bits;
+
+/** \brief Port Input Select Register 2 */
+typedef struct _Ifx_CCU6_PISEL2_Bits
+{
+ unsigned int IST13HR:2; /**< \brief [1:0] Input Select for T13HR (rw) */
+ unsigned int ISCNT12:2; /**< \brief [3:2] Input Select for T12 Counting Input (rw) */
+ unsigned int ISCNT13:2; /**< \brief [5:4] Input Select for T13 Counting Input (rw) */
+ unsigned int T12EXT:1; /**< \brief [6:6] Extension for T12HR Inputs (rw) */
+ unsigned int T13EXT:1; /**< \brief [7:7] Extension for T13HR Inputs (rw) */
+ unsigned int reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_CCU6_PISEL2_Bits;
+
+/** \brief Passive State Level Register */
+typedef struct _Ifx_CCU6_PSLR_Bits
+{
+ unsigned int PSL:6; /**< \brief [5:0] Compare Outputs Passive State Level (rwh) */
+ unsigned int reserved_6:1; /**< \brief \internal Reserved */
+ unsigned int PSL63:1; /**< \brief [7:7] Passive State Level of Output COUT63 (rwh) */
+ unsigned int reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_CCU6_PSLR_Bits;
+
+/** \brief Timer T12 Counter Register */
+typedef struct _Ifx_CCU6_T12_Bits
+{
+ unsigned int T12CV:16; /**< \brief [15:0] Timer 12 Counter Value (rwh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CCU6_T12_Bits;
+
+/** \brief Dead-Time Control Register for Timer12 */
+typedef struct _Ifx_CCU6_T12DTC_Bits
+{
+ unsigned int DTM:8; /**< \brief [7:0] Dead-Time (rw) */
+ unsigned int DTE0:1; /**< \brief [8:8] Dead Time Enable Bits (rw) */
+ unsigned int DTE1:1; /**< \brief [9:9] Dead Time Enable Bits (rw) */
+ unsigned int DTE2:1; /**< \brief [10:10] Dead Time Enable Bits (rw) */
+ unsigned int reserved_11:1; /**< \brief \internal Reserved */
+ unsigned int DTR0:1; /**< \brief [12:12] Dead Time Run Indication Bits (rh) */
+ unsigned int DTR1:1; /**< \brief [13:13] Dead Time Run Indication Bits (rh) */
+ unsigned int DTR2:1; /**< \brief [14:14] Dead Time Run Indication Bits (rh) */
+ unsigned int reserved_15:17; /**< \brief \internal Reserved */
+} Ifx_CCU6_T12DTC_Bits;
+
+/** \brief T12 Mode Select Register */
+typedef struct _Ifx_CCU6_T12MSEL_Bits
+{
+ unsigned int MSEL60:4; /**< \brief [3:0] Capture/Compare Mode Selection (rw) */
+ unsigned int MSEL61:4; /**< \brief [7:4] Capture/Compare Mode Selection (rw) */
+ unsigned int MSEL62:4; /**< \brief [11:8] Capture/Compare Mode Selection (rw) */
+ unsigned int HSYNC:3; /**< \brief [14:12] Hall Synchronization (rw) */
+ unsigned int DBYP:1; /**< \brief [15:15] Delay Bypass (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CCU6_T12MSEL_Bits;
+
+/** \brief Timer 12 Period Register */
+typedef struct _Ifx_CCU6_T12PR_Bits
+{
+ unsigned int T12PV:16; /**< \brief [15:0] T12 Period Value (rwh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CCU6_T12PR_Bits;
+
+/** \brief Timer T13 Counter Register */
+typedef struct _Ifx_CCU6_T13_Bits
+{
+ unsigned int T13CV:16; /**< \brief [15:0] Timer 13 Counter Value (rwh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CCU6_T13_Bits;
+
+/** \brief Timer 13 Period Register */
+typedef struct _Ifx_CCU6_T13PR_Bits
+{
+ unsigned int T13PV:16; /**< \brief [15:0] T13 Period Value (rwh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CCU6_T13PR_Bits;
+
+/** \brief Timer Control Register 0 */
+typedef struct _Ifx_CCU6_TCTR0_Bits
+{
+ unsigned int T12CLK:3; /**< \brief [2:0] Timer T12 Input Clock Select (rw) */
+ unsigned int T12PRE:1; /**< \brief [3:3] Timer T12 Prescaler Bit (rw) */
+ unsigned int T12R:1; /**< \brief [4:4] Timer T12 Run Bit (rh) */
+ unsigned int STE12:1; /**< \brief [5:5] Timer T12 Shadow Transfer Enable (rh) */
+ unsigned int CDIR:1; /**< \brief [6:6] Count Direction of Timer T12 (rh) */
+ unsigned int CTM:1; /**< \brief [7:7] T12 Operating Mode (rw) */
+ unsigned int T13CLK:3; /**< \brief [10:8] Timer T13 Input Clock Select (rw) */
+ unsigned int T13PRE:1; /**< \brief [11:11] Timer T13 Prescaler Bit (rw) */
+ unsigned int T13R:1; /**< \brief [12:12] Timer T13 Run Bit (rh) */
+ unsigned int STE13:1; /**< \brief [13:13] Timer T13 Shadow Transfer Enable (rh) */
+ unsigned int reserved_14:18; /**< \brief \internal Reserved */
+} Ifx_CCU6_TCTR0_Bits;
+
+/** \brief Timer Control Register 2 */
+typedef struct _Ifx_CCU6_TCTR2_Bits
+{
+ unsigned int T12SSC:1; /**< \brief [0:0] Timer T12 Single Shot Control (rw) */
+ unsigned int T13SSC:1; /**< \brief [1:1] Timer T13 Single Shot Control (rw) */
+ unsigned int T13TEC:3; /**< \brief [4:2] T13 Trigger Event Control (rw) */
+ unsigned int T13TED:2; /**< \brief [6:5] Timer T13 Trigger Event Direction (rw) */
+ unsigned int reserved_7:1; /**< \brief \internal Reserved */
+ unsigned int T12RSEL:2; /**< \brief [9:8] Timer T12 External Run Selection (rw) */
+ unsigned int T13RSEL:2; /**< \brief [11:10] Timer T13 External Run Selection (rw) */
+ unsigned int reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_CCU6_TCTR2_Bits;
+
+/** \brief Timer Control Register 4 */
+typedef struct _Ifx_CCU6_TCTR4_Bits
+{
+ unsigned int T12RR:1; /**< \brief [0:0] Timer T12 Run Reset (w) */
+ unsigned int T12RS:1; /**< \brief [1:1] Timer T12 Run Set (w) */
+ unsigned int T12RES:1; /**< \brief [2:2] Timer T12 Reset (w) */
+ unsigned int DTRES:1; /**< \brief [3:3] Dead-Time Counter Reset (w) */
+ unsigned int reserved_4:1; /**< \brief \internal Reserved */
+ unsigned int T12CNT:1; /**< \brief [5:5] Timer T12 Count Event (w) */
+ unsigned int T12STR:1; /**< \brief [6:6] Timer T12 Shadow Transfer Request (w) */
+ unsigned int T12STD:1; /**< \brief [7:7] Timer T12 Shadow Transfer Disable (w) */
+ unsigned int T13RR:1; /**< \brief [8:8] Timer T13 Run Reset (w) */
+ unsigned int T13RS:1; /**< \brief [9:9] Timer T13 Run Set (w) */
+ unsigned int T13RES:1; /**< \brief [10:10] Timer T13 Reset (w) */
+ unsigned int reserved_11:2; /**< \brief \internal Reserved */
+ unsigned int T13CNT:1; /**< \brief [13:13] Timer T13 Count Event (w) */
+ unsigned int T13STR:1; /**< \brief [14:14] Timer T13 Shadow Transfer Request (w) */
+ unsigned int T13STD:1; /**< \brief [15:15] Timer T13 Shadow Transfer Disable (w) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CCU6_TCTR4_Bits;
+
+/** \brief Trap Control Register */
+typedef struct _Ifx_CCU6_TRPCTR_Bits
+{
+ unsigned int TRPM0:1; /**< \brief [0:0] Trap Mode Control Bits 1, 0 (rw) */
+ unsigned int TRPM1:1; /**< \brief [1:1] Trap Mode Control Bits 1, 0 (rw) */
+ unsigned int TRPM2:1; /**< \brief [2:2] Trap Mode Control Bit 2 (rw) */
+ unsigned int reserved_3:5; /**< \brief \internal Reserved */
+ unsigned int TRPEN:6; /**< \brief [13:8] Trap Enable Control (rw) */
+ unsigned int TRPEN13:1; /**< \brief [14:14] Trap Enable Control for Timer T13 (rw) */
+ unsigned int TRPPEN:1; /**< \brief [15:15] Trap Pin Enable (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CCU6_TRPCTR_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Ccu6_union
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_ACCEN0_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_ACCEN0;
+
+/** \brief Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_ACCEN1_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_ACCEN1;
+
+/** \brief Capture/Compare Register for Channel CC60 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_CC60R_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_CC60R;
+
+/** \brief Capture/Compare Shadow Reg. for Channel CC60 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_CC60SR_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_CC60SR;
+
+/** \brief Capture/Compare Register for Channel CC61 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_CC61R_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_CC61R;
+
+/** \brief Capture/Compare Shadow Reg. for Channel CC61 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_CC61SR_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_CC61SR;
+
+/** \brief Capture/Compare Register for Channel CC62 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_CC62R_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_CC62R;
+
+/** \brief Capture/Compare Shadow Reg. for Channel CC62 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_CC62SR_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_CC62SR;
+
+/** \brief Compare Register for T13 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_CC63R_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_CC63R;
+
+/** \brief Compare Shadow Register for T13 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_CC63SR_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_CC63SR;
+
+/** \brief Clock Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_CLC_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_CLC;
+
+/** \brief Compare State Modification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_CMPMODIF_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_CMPMODIF;
+
+/** \brief Compare State Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_CMPSTAT_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_CMPSTAT;
+
+/** \brief Module Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_ID;
+
+/** \brief Interrupt Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_IEN_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_IEN;
+
+/** \brief Input Monitoring Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_IMON_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_IMON;
+
+/** \brief Interrupt Node Pointer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_INP_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_INP;
+
+/** \brief Interrupt Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_IS_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_IS;
+
+/** \brief Interrupt Status Reset Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_ISR_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_ISR;
+
+/** \brief Interrupt Status Set Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_ISS_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_ISS;
+
+/** \brief Kernel Reset Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_KRST0_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_KRST0;
+
+/** \brief Kernel Reset Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_KRST1_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_KRST1;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_KRSTCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_KRSTCLR;
+
+/** \brief Kernel State Control Sensitivity Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_KSCSR_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_KSCSR;
+
+/** \brief Lost Indicator Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_LI_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_LI;
+
+/** \brief Module Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_MCFG_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_MCFG;
+
+/** \brief Multi-Channel Mode Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_MCMCTR_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_MCMCTR;
+
+/** \brief Multi-Channel Mode Output Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_MCMOUT_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_MCMOUT;
+
+/** \brief Multi-Channel Mode Output Shadow Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_MCMOUTS_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_MCMOUTS;
+
+/** \brief Modulation Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_MODCTR_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_MODCTR;
+
+/** \brief CCU60 Module Output Select Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_MOSEL_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_MOSEL;
+
+/** \brief OCDS Control and Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_OCS_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_OCS;
+
+/** \brief Port Input Select Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_PISEL0_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_PISEL0;
+
+/** \brief Port Input Select Register 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_PISEL2_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_PISEL2;
+
+/** \brief Passive State Level Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_PSLR_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_PSLR;
+
+/** \brief Timer T12 Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_T12_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_T12;
+
+/** \brief Dead-Time Control Register for Timer12 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_T12DTC_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_T12DTC;
+
+/** \brief T12 Mode Select Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_T12MSEL_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_T12MSEL;
+
+/** \brief Timer 12 Period Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_T12PR_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_T12PR;
+
+/** \brief Timer T13 Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_T13_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_T13;
+
+/** \brief Timer 13 Period Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_T13PR_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_T13PR;
+
+/** \brief Timer Control Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_TCTR0_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_TCTR0;
+
+/** \brief Timer Control Register 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_TCTR2_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_TCTR2;
+
+/** \brief Timer Control Register 4 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_TCTR4_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_TCTR4;
+
+/** \brief Trap Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CCU6_TRPCTR_Bits B; /**< \brief Bitfield access */
+} Ifx_CCU6_TRPCTR;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Ccu6_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief CCU6 object */
+typedef volatile struct _Ifx_CCU6
+{
+ Ifx_CCU6_CLC CLC; /**< \brief 0, Clock Control Register */
+ Ifx_CCU6_MCFG MCFG; /**< \brief 4, Module Configuration Register */
+ Ifx_CCU6_ID ID; /**< \brief 8, Module Identification Register */
+ Ifx_CCU6_MOSEL MOSEL; /**< \brief C, CCU60 Module Output Select Register */
+ Ifx_CCU6_PISEL0 PISEL0; /**< \brief 10, Port Input Select Register 0 */
+ Ifx_CCU6_PISEL2 PISEL2; /**< \brief 14, Port Input Select Register 2 */
+ unsigned char reserved_18[4]; /**< \brief 18, \internal Reserved */
+ Ifx_CCU6_KSCSR KSCSR; /**< \brief 1C, Kernel State Control Sensitivity Register */
+ Ifx_CCU6_T12 T12; /**< \brief 20, Timer T12 Counter Register */
+ Ifx_CCU6_T12PR T12PR; /**< \brief 24, Timer 12 Period Register */
+ Ifx_CCU6_T12DTC T12DTC; /**< \brief 28, Dead-Time Control Register for Timer12 */
+ unsigned char reserved_2C[4]; /**< \brief 2C, \internal Reserved */
+ Ifx_CCU6_CC60R CC60R; /**< \brief 30, Capture/Compare Register for Channel CC60 */
+ Ifx_CCU6_CC61R CC61R; /**< \brief 34, Capture/Compare Register for Channel CC61 */
+ Ifx_CCU6_CC62R CC62R; /**< \brief 38, Capture/Compare Register for Channel CC62 */
+ unsigned char reserved_3C[4]; /**< \brief 3C, \internal Reserved */
+ Ifx_CCU6_CC60SR CC60SR; /**< \brief 40, Capture/Compare Shadow Reg. for Channel CC60 */
+ Ifx_CCU6_CC61SR CC61SR; /**< \brief 44, Capture/Compare Shadow Reg. for Channel CC61 */
+ Ifx_CCU6_CC62SR CC62SR; /**< \brief 48, Capture/Compare Shadow Reg. for Channel CC62 */
+ unsigned char reserved_4C[4]; /**< \brief 4C, \internal Reserved */
+ Ifx_CCU6_T13 T13; /**< \brief 50, Timer T13 Counter Register */
+ Ifx_CCU6_T13PR T13PR; /**< \brief 54, Timer 13 Period Register */
+ Ifx_CCU6_CC63R CC63R; /**< \brief 58, Compare Register for T13 */
+ Ifx_CCU6_CC63SR CC63SR; /**< \brief 5C, Compare Shadow Register for T13 */
+ Ifx_CCU6_CMPSTAT CMPSTAT; /**< \brief 60, Compare State Register */
+ Ifx_CCU6_CMPMODIF CMPMODIF; /**< \brief 64, Compare State Modification Register */
+ Ifx_CCU6_T12MSEL T12MSEL; /**< \brief 68, T12 Mode Select Register */
+ unsigned char reserved_6C[4]; /**< \brief 6C, \internal Reserved */
+ Ifx_CCU6_TCTR0 TCTR0; /**< \brief 70, Timer Control Register 0 */
+ Ifx_CCU6_TCTR2 TCTR2; /**< \brief 74, Timer Control Register 2 */
+ Ifx_CCU6_TCTR4 TCTR4; /**< \brief 78, Timer Control Register 4 */
+ unsigned char reserved_7C[4]; /**< \brief 7C, \internal Reserved */
+ Ifx_CCU6_MODCTR MODCTR; /**< \brief 80, Modulation Control Register */
+ Ifx_CCU6_TRPCTR TRPCTR; /**< \brief 84, Trap Control Register */
+ Ifx_CCU6_PSLR PSLR; /**< \brief 88, Passive State Level Register */
+ Ifx_CCU6_MCMOUTS MCMOUTS; /**< \brief 8C, Multi-Channel Mode Output Shadow Register */
+ Ifx_CCU6_MCMOUT MCMOUT; /**< \brief 90, Multi-Channel Mode Output Register */
+ Ifx_CCU6_MCMCTR MCMCTR; /**< \brief 94, Multi-Channel Mode Control Register */
+ Ifx_CCU6_IMON IMON; /**< \brief 98, Input Monitoring Register */
+ Ifx_CCU6_LI LI; /**< \brief 9C, Lost Indicator Register */
+ Ifx_CCU6_IS IS; /**< \brief A0, Interrupt Status Register */
+ Ifx_CCU6_ISS ISS; /**< \brief A4, Interrupt Status Set Register */
+ Ifx_CCU6_ISR ISR; /**< \brief A8, Interrupt Status Reset Register */
+ Ifx_CCU6_INP INP; /**< \brief AC, Interrupt Node Pointer Register */
+ Ifx_CCU6_IEN IEN; /**< \brief B0, Interrupt Enable Register */
+ unsigned char reserved_B4[52]; /**< \brief B4, \internal Reserved */
+ Ifx_CCU6_OCS OCS; /**< \brief E8, OCDS Control and Status Register */
+ Ifx_CCU6_KRSTCLR KRSTCLR; /**< \brief EC, Kernel Reset Status Clear Register */
+ Ifx_CCU6_KRST1 KRST1; /**< \brief F0, Kernel Reset Register 1 */
+ Ifx_CCU6_KRST0 KRST0; /**< \brief F4, Kernel Reset Register 0 */
+ Ifx_CCU6_ACCEN1 ACCEN1; /**< \brief F8, Access Enable Register 1 */
+ Ifx_CCU6_ACCEN0 ACCEN0; /**< \brief FC, Access Enable Register 0 */
+} Ifx_CCU6;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXCCU6_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCif_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCif_bf.h
new file mode 100644
index 0000000..b15bdf6
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCif_bf.h
@@ -0,0 +1,4959 @@
+/**
+ * \file IfxCif_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Cif_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Cif
+ *
+ */
+#ifndef IFXCIF_BF_H
+#define IFXCIF_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Cif_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN0 */
+#define IFX_CIF_BBB_ACCEN0_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN0 */
+#define IFX_CIF_BBB_ACCEN0_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN0 */
+#define IFX_CIF_BBB_ACCEN0_EN0_OFF (0u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN10 */
+#define IFX_CIF_BBB_ACCEN0_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN10 */
+#define IFX_CIF_BBB_ACCEN0_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN10 */
+#define IFX_CIF_BBB_ACCEN0_EN10_OFF (10u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN11 */
+#define IFX_CIF_BBB_ACCEN0_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN11 */
+#define IFX_CIF_BBB_ACCEN0_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN11 */
+#define IFX_CIF_BBB_ACCEN0_EN11_OFF (11u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN12 */
+#define IFX_CIF_BBB_ACCEN0_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN12 */
+#define IFX_CIF_BBB_ACCEN0_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN12 */
+#define IFX_CIF_BBB_ACCEN0_EN12_OFF (12u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN13 */
+#define IFX_CIF_BBB_ACCEN0_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN13 */
+#define IFX_CIF_BBB_ACCEN0_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN13 */
+#define IFX_CIF_BBB_ACCEN0_EN13_OFF (13u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN14 */
+#define IFX_CIF_BBB_ACCEN0_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN14 */
+#define IFX_CIF_BBB_ACCEN0_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN14 */
+#define IFX_CIF_BBB_ACCEN0_EN14_OFF (14u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN15 */
+#define IFX_CIF_BBB_ACCEN0_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN15 */
+#define IFX_CIF_BBB_ACCEN0_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN15 */
+#define IFX_CIF_BBB_ACCEN0_EN15_OFF (15u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN16 */
+#define IFX_CIF_BBB_ACCEN0_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN16 */
+#define IFX_CIF_BBB_ACCEN0_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN16 */
+#define IFX_CIF_BBB_ACCEN0_EN16_OFF (16u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN17 */
+#define IFX_CIF_BBB_ACCEN0_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN17 */
+#define IFX_CIF_BBB_ACCEN0_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN17 */
+#define IFX_CIF_BBB_ACCEN0_EN17_OFF (17u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN18 */
+#define IFX_CIF_BBB_ACCEN0_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN18 */
+#define IFX_CIF_BBB_ACCEN0_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN18 */
+#define IFX_CIF_BBB_ACCEN0_EN18_OFF (18u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN19 */
+#define IFX_CIF_BBB_ACCEN0_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN19 */
+#define IFX_CIF_BBB_ACCEN0_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN19 */
+#define IFX_CIF_BBB_ACCEN0_EN19_OFF (19u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN1 */
+#define IFX_CIF_BBB_ACCEN0_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN1 */
+#define IFX_CIF_BBB_ACCEN0_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN1 */
+#define IFX_CIF_BBB_ACCEN0_EN1_OFF (1u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN20 */
+#define IFX_CIF_BBB_ACCEN0_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN20 */
+#define IFX_CIF_BBB_ACCEN0_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN20 */
+#define IFX_CIF_BBB_ACCEN0_EN20_OFF (20u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN21 */
+#define IFX_CIF_BBB_ACCEN0_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN21 */
+#define IFX_CIF_BBB_ACCEN0_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN21 */
+#define IFX_CIF_BBB_ACCEN0_EN21_OFF (21u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN22 */
+#define IFX_CIF_BBB_ACCEN0_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN22 */
+#define IFX_CIF_BBB_ACCEN0_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN22 */
+#define IFX_CIF_BBB_ACCEN0_EN22_OFF (22u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN23 */
+#define IFX_CIF_BBB_ACCEN0_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN23 */
+#define IFX_CIF_BBB_ACCEN0_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN23 */
+#define IFX_CIF_BBB_ACCEN0_EN23_OFF (23u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN24 */
+#define IFX_CIF_BBB_ACCEN0_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN24 */
+#define IFX_CIF_BBB_ACCEN0_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN24 */
+#define IFX_CIF_BBB_ACCEN0_EN24_OFF (24u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN25 */
+#define IFX_CIF_BBB_ACCEN0_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN25 */
+#define IFX_CIF_BBB_ACCEN0_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN25 */
+#define IFX_CIF_BBB_ACCEN0_EN25_OFF (25u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN26 */
+#define IFX_CIF_BBB_ACCEN0_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN26 */
+#define IFX_CIF_BBB_ACCEN0_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN26 */
+#define IFX_CIF_BBB_ACCEN0_EN26_OFF (26u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN27 */
+#define IFX_CIF_BBB_ACCEN0_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN27 */
+#define IFX_CIF_BBB_ACCEN0_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN27 */
+#define IFX_CIF_BBB_ACCEN0_EN27_OFF (27u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN28 */
+#define IFX_CIF_BBB_ACCEN0_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN28 */
+#define IFX_CIF_BBB_ACCEN0_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN28 */
+#define IFX_CIF_BBB_ACCEN0_EN28_OFF (28u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN29 */
+#define IFX_CIF_BBB_ACCEN0_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN29 */
+#define IFX_CIF_BBB_ACCEN0_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN29 */
+#define IFX_CIF_BBB_ACCEN0_EN29_OFF (29u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN2 */
+#define IFX_CIF_BBB_ACCEN0_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN2 */
+#define IFX_CIF_BBB_ACCEN0_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN2 */
+#define IFX_CIF_BBB_ACCEN0_EN2_OFF (2u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN30 */
+#define IFX_CIF_BBB_ACCEN0_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN30 */
+#define IFX_CIF_BBB_ACCEN0_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN30 */
+#define IFX_CIF_BBB_ACCEN0_EN30_OFF (30u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN31 */
+#define IFX_CIF_BBB_ACCEN0_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN31 */
+#define IFX_CIF_BBB_ACCEN0_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN31 */
+#define IFX_CIF_BBB_ACCEN0_EN31_OFF (31u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN3 */
+#define IFX_CIF_BBB_ACCEN0_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN3 */
+#define IFX_CIF_BBB_ACCEN0_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN3 */
+#define IFX_CIF_BBB_ACCEN0_EN3_OFF (3u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN4 */
+#define IFX_CIF_BBB_ACCEN0_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN4 */
+#define IFX_CIF_BBB_ACCEN0_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN4 */
+#define IFX_CIF_BBB_ACCEN0_EN4_OFF (4u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN5 */
+#define IFX_CIF_BBB_ACCEN0_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN5 */
+#define IFX_CIF_BBB_ACCEN0_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN5 */
+#define IFX_CIF_BBB_ACCEN0_EN5_OFF (5u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN6 */
+#define IFX_CIF_BBB_ACCEN0_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN6 */
+#define IFX_CIF_BBB_ACCEN0_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN6 */
+#define IFX_CIF_BBB_ACCEN0_EN6_OFF (6u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN7 */
+#define IFX_CIF_BBB_ACCEN0_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN7 */
+#define IFX_CIF_BBB_ACCEN0_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN7 */
+#define IFX_CIF_BBB_ACCEN0_EN7_OFF (7u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN8 */
+#define IFX_CIF_BBB_ACCEN0_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN8 */
+#define IFX_CIF_BBB_ACCEN0_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN8 */
+#define IFX_CIF_BBB_ACCEN0_EN8_OFF (8u)
+
+/** \brief Length for Ifx_CIF_BBB_ACCEN0_Bits.EN9 */
+#define IFX_CIF_BBB_ACCEN0_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_ACCEN0_Bits.EN9 */
+#define IFX_CIF_BBB_ACCEN0_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_ACCEN0_Bits.EN9 */
+#define IFX_CIF_BBB_ACCEN0_EN9_OFF (9u)
+
+/** \brief Length for Ifx_CIF_BBB_CLC_Bits.DISR */
+#define IFX_CIF_BBB_CLC_DISR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_CLC_Bits.DISR */
+#define IFX_CIF_BBB_CLC_DISR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_CLC_Bits.DISR */
+#define IFX_CIF_BBB_CLC_DISR_OFF (0u)
+
+/** \brief Length for Ifx_CIF_BBB_CLC_Bits.DISS */
+#define IFX_CIF_BBB_CLC_DISS_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_CLC_Bits.DISS */
+#define IFX_CIF_BBB_CLC_DISS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_CLC_Bits.DISS */
+#define IFX_CIF_BBB_CLC_DISS_OFF (1u)
+
+/** \brief Length for Ifx_CIF_BBB_GPCTL_Bits.PISEL */
+#define IFX_CIF_BBB_GPCTL_PISEL_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_GPCTL_Bits.PISEL */
+#define IFX_CIF_BBB_GPCTL_PISEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_GPCTL_Bits.PISEL */
+#define IFX_CIF_BBB_GPCTL_PISEL_OFF (0u)
+
+/** \brief Length for Ifx_CIF_BBB_KRST0_Bits.RST */
+#define IFX_CIF_BBB_KRST0_RST_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_KRST0_Bits.RST */
+#define IFX_CIF_BBB_KRST0_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_KRST0_Bits.RST */
+#define IFX_CIF_BBB_KRST0_RST_OFF (0u)
+
+/** \brief Length for Ifx_CIF_BBB_KRST0_Bits.RSTSTAT */
+#define IFX_CIF_BBB_KRST0_RSTSTAT_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_KRST0_Bits.RSTSTAT */
+#define IFX_CIF_BBB_KRST0_RSTSTAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_KRST0_Bits.RSTSTAT */
+#define IFX_CIF_BBB_KRST0_RSTSTAT_OFF (1u)
+
+/** \brief Length for Ifx_CIF_BBB_KRST1_Bits.RST */
+#define IFX_CIF_BBB_KRST1_RST_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_KRST1_Bits.RST */
+#define IFX_CIF_BBB_KRST1_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_KRST1_Bits.RST */
+#define IFX_CIF_BBB_KRST1_RST_OFF (0u)
+
+/** \brief Length for Ifx_CIF_BBB_KRSTCLR_Bits.CLR */
+#define IFX_CIF_BBB_KRSTCLR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_BBB_KRSTCLR_Bits.CLR */
+#define IFX_CIF_BBB_KRSTCLR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_BBB_KRSTCLR_Bits.CLR */
+#define IFX_CIF_BBB_KRSTCLR_CLR_OFF (0u)
+
+/** \brief Length for Ifx_CIF_BBB_MODID_Bits.MODNUMBER */
+#define IFX_CIF_BBB_MODID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_CIF_BBB_MODID_Bits.MODNUMBER */
+#define IFX_CIF_BBB_MODID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CIF_BBB_MODID_Bits.MODNUMBER */
+#define IFX_CIF_BBB_MODID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_CIF_BBB_MODID_Bits.MODREV */
+#define IFX_CIF_BBB_MODID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_CIF_BBB_MODID_Bits.MODREV */
+#define IFX_CIF_BBB_MODID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_CIF_BBB_MODID_Bits.MODREV */
+#define IFX_CIF_BBB_MODID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_CIF_BBB_MODID_Bits.MODTYPE */
+#define IFX_CIF_BBB_MODID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_CIF_BBB_MODID_Bits.MODTYPE */
+#define IFX_CIF_BBB_MODID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_CIF_BBB_MODID_Bits.MODTYPE */
+#define IFX_CIF_BBB_MODID_MODTYPE_OFF (8u)
+
+/** \brief Length for Ifx_CIF_CCL_Bits.CIF_CCLDISS */
+#define IFX_CIF_CCL_CIF_CCLDISS_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_CCL_Bits.CIF_CCLDISS */
+#define IFX_CIF_CCL_CIF_CCLDISS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_CCL_Bits.CIF_CCLDISS */
+#define IFX_CIF_CCL_CIF_CCLDISS_OFF (1u)
+
+/** \brief Length for Ifx_CIF_CCL_Bits.CIF_CCLFDIS */
+#define IFX_CIF_CCL_CIF_CCLFDIS_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_CCL_Bits.CIF_CCLFDIS */
+#define IFX_CIF_CCL_CIF_CCLFDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_CCL_Bits.CIF_CCLFDIS */
+#define IFX_CIF_CCL_CIF_CCLFDIS_OFF (2u)
+
+/** \brief Length for Ifx_CIF_DP_CTRL_Bits.DP_EN */
+#define IFX_CIF_DP_CTRL_DP_EN_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_DP_CTRL_Bits.DP_EN */
+#define IFX_CIF_DP_CTRL_DP_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_DP_CTRL_Bits.DP_EN */
+#define IFX_CIF_DP_CTRL_DP_EN_OFF (0u)
+
+/** \brief Length for Ifx_CIF_DP_CTRL_Bits.DP_SEL */
+#define IFX_CIF_DP_CTRL_DP_SEL_LEN (3u)
+
+/** \brief Mask for Ifx_CIF_DP_CTRL_Bits.DP_SEL */
+#define IFX_CIF_DP_CTRL_DP_SEL_MSK (0x7u)
+
+/** \brief Offset for Ifx_CIF_DP_CTRL_Bits.DP_SEL */
+#define IFX_CIF_DP_CTRL_DP_SEL_OFF (1u)
+
+/** \brief Length for Ifx_CIF_DP_CTRL_Bits.FNC_EN */
+#define IFX_CIF_DP_CTRL_FNC_EN_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_DP_CTRL_Bits.FNC_EN */
+#define IFX_CIF_DP_CTRL_FNC_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_DP_CTRL_Bits.FNC_EN */
+#define IFX_CIF_DP_CTRL_FNC_EN_OFF (13u)
+
+/** \brief Length for Ifx_CIF_DP_CTRL_Bits.LNC_EN */
+#define IFX_CIF_DP_CTRL_LNC_EN_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_DP_CTRL_Bits.LNC_EN */
+#define IFX_CIF_DP_CTRL_LNC_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_DP_CTRL_Bits.LNC_EN */
+#define IFX_CIF_DP_CTRL_LNC_EN_OFF (14u)
+
+/** \brief Length for Ifx_CIF_DP_CTRL_Bits.RST_FNC */
+#define IFX_CIF_DP_CTRL_RST_FNC_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_DP_CTRL_Bits.RST_FNC */
+#define IFX_CIF_DP_CTRL_RST_FNC_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_DP_CTRL_Bits.RST_FNC */
+#define IFX_CIF_DP_CTRL_RST_FNC_OFF (8u)
+
+/** \brief Length for Ifx_CIF_DP_CTRL_Bits.RST_LNC */
+#define IFX_CIF_DP_CTRL_RST_LNC_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_DP_CTRL_Bits.RST_LNC */
+#define IFX_CIF_DP_CTRL_RST_LNC_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_DP_CTRL_Bits.RST_LNC */
+#define IFX_CIF_DP_CTRL_RST_LNC_OFF (9u)
+
+/** \brief Length for Ifx_CIF_DP_CTRL_Bits.RST_PD */
+#define IFX_CIF_DP_CTRL_RST_PD_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_DP_CTRL_Bits.RST_PD */
+#define IFX_CIF_DP_CTRL_RST_PD_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_DP_CTRL_Bits.RST_PD */
+#define IFX_CIF_DP_CTRL_RST_PD_OFF (11u)
+
+/** \brief Length for Ifx_CIF_DP_CTRL_Bits.RST_TSC */
+#define IFX_CIF_DP_CTRL_RST_TSC_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_DP_CTRL_Bits.RST_TSC */
+#define IFX_CIF_DP_CTRL_RST_TSC_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_DP_CTRL_Bits.RST_TSC */
+#define IFX_CIF_DP_CTRL_RST_TSC_OFF (10u)
+
+/** \brief Length for Ifx_CIF_DP_CTRL_Bits.TSC_EN */
+#define IFX_CIF_DP_CTRL_TSC_EN_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_DP_CTRL_Bits.TSC_EN */
+#define IFX_CIF_DP_CTRL_TSC_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_DP_CTRL_Bits.TSC_EN */
+#define IFX_CIF_DP_CTRL_TSC_EN_OFF (15u)
+
+/** \brief Length for Ifx_CIF_DP_CTRL_Bits.UDS1 */
+#define IFX_CIF_DP_CTRL_UDS1_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_DP_CTRL_Bits.UDS1 */
+#define IFX_CIF_DP_CTRL_UDS1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_DP_CTRL_Bits.UDS1 */
+#define IFX_CIF_DP_CTRL_UDS1_OFF (16u)
+
+/** \brief Length for Ifx_CIF_DP_CTRL_Bits.UDS2 */
+#define IFX_CIF_DP_CTRL_UDS2_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_DP_CTRL_Bits.UDS2 */
+#define IFX_CIF_DP_CTRL_UDS2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_DP_CTRL_Bits.UDS2 */
+#define IFX_CIF_DP_CTRL_UDS2_OFF (17u)
+
+/** \brief Length for Ifx_CIF_DP_CTRL_Bits.UDS3 */
+#define IFX_CIF_DP_CTRL_UDS3_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_DP_CTRL_Bits.UDS3 */
+#define IFX_CIF_DP_CTRL_UDS3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_DP_CTRL_Bits.UDS3 */
+#define IFX_CIF_DP_CTRL_UDS3_OFF (18u)
+
+/** \brief Length for Ifx_CIF_DP_CTRL_Bits.UDS4 */
+#define IFX_CIF_DP_CTRL_UDS4_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_DP_CTRL_Bits.UDS4 */
+#define IFX_CIF_DP_CTRL_UDS4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_DP_CTRL_Bits.UDS4 */
+#define IFX_CIF_DP_CTRL_UDS4_OFF (19u)
+
+/** \brief Length for Ifx_CIF_DP_CTRL_Bits.UDS5 */
+#define IFX_CIF_DP_CTRL_UDS5_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_DP_CTRL_Bits.UDS5 */
+#define IFX_CIF_DP_CTRL_UDS5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_DP_CTRL_Bits.UDS5 */
+#define IFX_CIF_DP_CTRL_UDS5_OFF (20u)
+
+/** \brief Length for Ifx_CIF_DP_CTRL_Bits.UDS6 */
+#define IFX_CIF_DP_CTRL_UDS6_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_DP_CTRL_Bits.UDS6 */
+#define IFX_CIF_DP_CTRL_UDS6_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_DP_CTRL_Bits.UDS6 */
+#define IFX_CIF_DP_CTRL_UDS6_OFF (21u)
+
+/** \brief Length for Ifx_CIF_DP_CTRL_Bits.UDS7 */
+#define IFX_CIF_DP_CTRL_UDS7_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_DP_CTRL_Bits.UDS7 */
+#define IFX_CIF_DP_CTRL_UDS7_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_DP_CTRL_Bits.UDS7 */
+#define IFX_CIF_DP_CTRL_UDS7_OFF (22u)
+
+/** \brief Length for Ifx_CIF_DP_CTRL_Bits.UDS8 */
+#define IFX_CIF_DP_CTRL_UDS8_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_DP_CTRL_Bits.UDS8 */
+#define IFX_CIF_DP_CTRL_UDS8_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_DP_CTRL_Bits.UDS8 */
+#define IFX_CIF_DP_CTRL_UDS8_OFF (23u)
+
+/** \brief Length for Ifx_CIF_DP_FLC_STAT_Bits.FNC_VAL */
+#define IFX_CIF_DP_FLC_STAT_FNC_VAL_LEN (15u)
+
+/** \brief Mask for Ifx_CIF_DP_FLC_STAT_Bits.FNC_VAL */
+#define IFX_CIF_DP_FLC_STAT_FNC_VAL_MSK (0x7fffu)
+
+/** \brief Offset for Ifx_CIF_DP_FLC_STAT_Bits.FNC_VAL */
+#define IFX_CIF_DP_FLC_STAT_FNC_VAL_OFF (0u)
+
+/** \brief Length for Ifx_CIF_DP_FLC_STAT_Bits.LNC_VAL */
+#define IFX_CIF_DP_FLC_STAT_LNC_VAL_LEN (15u)
+
+/** \brief Mask for Ifx_CIF_DP_FLC_STAT_Bits.LNC_VAL */
+#define IFX_CIF_DP_FLC_STAT_LNC_VAL_MSK (0x7fffu)
+
+/** \brief Offset for Ifx_CIF_DP_FLC_STAT_Bits.LNC_VAL */
+#define IFX_CIF_DP_FLC_STAT_LNC_VAL_OFF (16u)
+
+/** \brief Length for Ifx_CIF_DP_PDIV_CTRL_Bits.PDIV_VAL */
+#define IFX_CIF_DP_PDIV_CTRL_PDIV_VAL_LEN (32u)
+
+/** \brief Mask for Ifx_CIF_DP_PDIV_CTRL_Bits.PDIV_VAL */
+#define IFX_CIF_DP_PDIV_CTRL_PDIV_VAL_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_CIF_DP_PDIV_CTRL_Bits.PDIV_VAL */
+#define IFX_CIF_DP_PDIV_CTRL_PDIV_VAL_OFF (0u)
+
+/** \brief Length for Ifx_CIF_DP_PDIV_STAT_Bits.PDIV_VAL */
+#define IFX_CIF_DP_PDIV_STAT_PDIV_VAL_LEN (32u)
+
+/** \brief Mask for Ifx_CIF_DP_PDIV_STAT_Bits.PDIV_VAL */
+#define IFX_CIF_DP_PDIV_STAT_PDIV_VAL_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_CIF_DP_PDIV_STAT_Bits.PDIV_VAL */
+#define IFX_CIF_DP_PDIV_STAT_PDIV_VAL_OFF (0u)
+
+/** \brief Length for Ifx_CIF_DP_TSC_STAT_Bits.TSC_VAL */
+#define IFX_CIF_DP_TSC_STAT_TSC_VAL_LEN (30u)
+
+/** \brief Mask for Ifx_CIF_DP_TSC_STAT_Bits.TSC_VAL */
+#define IFX_CIF_DP_TSC_STAT_TSC_VAL_MSK (0x3fffffffu)
+
+/** \brief Offset for Ifx_CIF_DP_TSC_STAT_Bits.TSC_VAL */
+#define IFX_CIF_DP_TSC_STAT_TSC_VAL_OFF (0u)
+
+/** \brief Length for Ifx_CIF_DP_UDS_Bits.UDS */
+#define IFX_CIF_DP_UDS_UDS_LEN (15u)
+
+/** \brief Mask for Ifx_CIF_DP_UDS_Bits.UDS */
+#define IFX_CIF_DP_UDS_UDS_MSK (0x7fffu)
+
+/** \brief Offset for Ifx_CIF_DP_UDS_Bits.UDS */
+#define IFX_CIF_DP_UDS_UDS_OFF (0u)
+
+/** \brief Length for Ifx_CIF_DPCL_Bits.CIF_CHAN_MODE */
+#define IFX_CIF_DPCL_CIF_CHAN_MODE_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_DPCL_Bits.CIF_CHAN_MODE */
+#define IFX_CIF_DPCL_CIF_CHAN_MODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_DPCL_Bits.CIF_CHAN_MODE */
+#define IFX_CIF_DPCL_CIF_CHAN_MODE_OFF (2u)
+
+/** \brief Length for Ifx_CIF_DPCL_Bits.CIF_MP_MUX */
+#define IFX_CIF_DPCL_CIF_MP_MUX_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_DPCL_Bits.CIF_MP_MUX */
+#define IFX_CIF_DPCL_CIF_MP_MUX_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_DPCL_Bits.CIF_MP_MUX */
+#define IFX_CIF_DPCL_CIF_MP_MUX_OFF (0u)
+
+/** \brief Length for Ifx_CIF_DPCL_Bits.IF_SELECT */
+#define IFX_CIF_DPCL_IF_SELECT_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_DPCL_Bits.IF_SELECT */
+#define IFX_CIF_DPCL_IF_SELECT_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_DPCL_Bits.IF_SELECT */
+#define IFX_CIF_DPCL_IF_SELECT_OFF (8u)
+
+/** \brief Length for Ifx_CIF_EP_IC_CTRL_Bits.IC_EN */
+#define IFX_CIF_EP_IC_CTRL_IC_EN_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_EP_IC_CTRL_Bits.IC_EN */
+#define IFX_CIF_EP_IC_CTRL_IC_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_EP_IC_CTRL_Bits.IC_EN */
+#define IFX_CIF_EP_IC_CTRL_IC_EN_OFF (0u)
+
+/** \brief Length for Ifx_CIF_EP_IC_DISPLACE_Bits.DX */
+#define IFX_CIF_EP_IC_DISPLACE_DX_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_EP_IC_DISPLACE_Bits.DX */
+#define IFX_CIF_EP_IC_DISPLACE_DX_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_EP_IC_DISPLACE_Bits.DX */
+#define IFX_CIF_EP_IC_DISPLACE_DX_OFF (0u)
+
+/** \brief Length for Ifx_CIF_EP_IC_DISPLACE_Bits.DY */
+#define IFX_CIF_EP_IC_DISPLACE_DY_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_EP_IC_DISPLACE_Bits.DY */
+#define IFX_CIF_EP_IC_DISPLACE_DY_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_EP_IC_DISPLACE_Bits.DY */
+#define IFX_CIF_EP_IC_DISPLACE_DY_OFF (16u)
+
+/** \brief Length for Ifx_CIF_EP_IC_H_OFFS_Bits.H_OFFS */
+#define IFX_CIF_EP_IC_H_OFFS_H_OFFS_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_EP_IC_H_OFFS_Bits.H_OFFS */
+#define IFX_CIF_EP_IC_H_OFFS_H_OFFS_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_EP_IC_H_OFFS_Bits.H_OFFS */
+#define IFX_CIF_EP_IC_H_OFFS_H_OFFS_OFF (0u)
+
+/** \brief Length for Ifx_CIF_EP_IC_H_OFFS_SHD_Bits.H_OFFS_SHD */
+#define IFX_CIF_EP_IC_H_OFFS_SHD_H_OFFS_SHD_LEN (13u)
+
+/** \brief Mask for Ifx_CIF_EP_IC_H_OFFS_SHD_Bits.H_OFFS_SHD */
+#define IFX_CIF_EP_IC_H_OFFS_SHD_H_OFFS_SHD_MSK (0x1fffu)
+
+/** \brief Offset for Ifx_CIF_EP_IC_H_OFFS_SHD_Bits.H_OFFS_SHD */
+#define IFX_CIF_EP_IC_H_OFFS_SHD_H_OFFS_SHD_OFF (0u)
+
+/** \brief Length for Ifx_CIF_EP_IC_H_SIZE_Bits.H_SIZE */
+#define IFX_CIF_EP_IC_H_SIZE_H_SIZE_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_EP_IC_H_SIZE_Bits.H_SIZE */
+#define IFX_CIF_EP_IC_H_SIZE_H_SIZE_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_EP_IC_H_SIZE_Bits.H_SIZE */
+#define IFX_CIF_EP_IC_H_SIZE_H_SIZE_OFF (0u)
+
+/** \brief Length for Ifx_CIF_EP_IC_H_SIZE_SHD_Bits.H_SIZE_SHD */
+#define IFX_CIF_EP_IC_H_SIZE_SHD_H_SIZE_SHD_LEN (13u)
+
+/** \brief Mask for Ifx_CIF_EP_IC_H_SIZE_SHD_Bits.H_SIZE_SHD */
+#define IFX_CIF_EP_IC_H_SIZE_SHD_H_SIZE_SHD_MSK (0x1fffu)
+
+/** \brief Offset for Ifx_CIF_EP_IC_H_SIZE_SHD_Bits.H_SIZE_SHD */
+#define IFX_CIF_EP_IC_H_SIZE_SHD_H_SIZE_SHD_OFF (0u)
+
+/** \brief Length for Ifx_CIF_EP_IC_MAX_DX_Bits.MAX_DX */
+#define IFX_CIF_EP_IC_MAX_DX_MAX_DX_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_EP_IC_MAX_DX_Bits.MAX_DX */
+#define IFX_CIF_EP_IC_MAX_DX_MAX_DX_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_EP_IC_MAX_DX_Bits.MAX_DX */
+#define IFX_CIF_EP_IC_MAX_DX_MAX_DX_OFF (0u)
+
+/** \brief Length for Ifx_CIF_EP_IC_MAX_DY_Bits.MAX_DY */
+#define IFX_CIF_EP_IC_MAX_DY_MAX_DY_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_EP_IC_MAX_DY_Bits.MAX_DY */
+#define IFX_CIF_EP_IC_MAX_DY_MAX_DY_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_EP_IC_MAX_DY_Bits.MAX_DY */
+#define IFX_CIF_EP_IC_MAX_DY_MAX_DY_OFF (0u)
+
+/** \brief Length for Ifx_CIF_EP_IC_RECENTER_Bits.RECENTER */
+#define IFX_CIF_EP_IC_RECENTER_RECENTER_LEN (3u)
+
+/** \brief Mask for Ifx_CIF_EP_IC_RECENTER_Bits.RECENTER */
+#define IFX_CIF_EP_IC_RECENTER_RECENTER_MSK (0x7u)
+
+/** \brief Offset for Ifx_CIF_EP_IC_RECENTER_Bits.RECENTER */
+#define IFX_CIF_EP_IC_RECENTER_RECENTER_OFF (0u)
+
+/** \brief Length for Ifx_CIF_EP_IC_V_OFFS_SHD_Bits.V_OFFS_SHD */
+#define IFX_CIF_EP_IC_V_OFFS_SHD_V_OFFS_SHD_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_EP_IC_V_OFFS_SHD_Bits.V_OFFS_SHD */
+#define IFX_CIF_EP_IC_V_OFFS_SHD_V_OFFS_SHD_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_EP_IC_V_OFFS_SHD_Bits.V_OFFS_SHD */
+#define IFX_CIF_EP_IC_V_OFFS_SHD_V_OFFS_SHD_OFF (0u)
+
+/** \brief Length for Ifx_CIF_EP_IC_V_OFFS_Bits.V_OFFS */
+#define IFX_CIF_EP_IC_V_OFFS_V_OFFS_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_EP_IC_V_OFFS_Bits.V_OFFS */
+#define IFX_CIF_EP_IC_V_OFFS_V_OFFS_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_EP_IC_V_OFFS_Bits.V_OFFS */
+#define IFX_CIF_EP_IC_V_OFFS_V_OFFS_OFF (0u)
+
+/** \brief Length for Ifx_CIF_EP_IC_V_SIZE_SHD_Bits.V_SIZE_SHD */
+#define IFX_CIF_EP_IC_V_SIZE_SHD_V_SIZE_SHD_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_EP_IC_V_SIZE_SHD_Bits.V_SIZE_SHD */
+#define IFX_CIF_EP_IC_V_SIZE_SHD_V_SIZE_SHD_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_EP_IC_V_SIZE_SHD_Bits.V_SIZE_SHD */
+#define IFX_CIF_EP_IC_V_SIZE_SHD_V_SIZE_SHD_OFF (0u)
+
+/** \brief Length for Ifx_CIF_EP_IC_V_SIZE_Bits.V_SIZE */
+#define IFX_CIF_EP_IC_V_SIZE_V_SIZE_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_EP_IC_V_SIZE_Bits.V_SIZE */
+#define IFX_CIF_EP_IC_V_SIZE_V_SIZE_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_EP_IC_V_SIZE_Bits.V_SIZE */
+#define IFX_CIF_EP_IC_V_SIZE_V_SIZE_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ICCL_Bits.CIF_DEBUG_PATH_CLK_EN */
+#define IFX_CIF_ICCL_CIF_DEBUG_PATH_CLK_EN_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ICCL_Bits.CIF_DEBUG_PATH_CLK_EN */
+#define IFX_CIF_ICCL_CIF_DEBUG_PATH_CLK_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ICCL_Bits.CIF_DEBUG_PATH_CLK_EN */
+#define IFX_CIF_ICCL_CIF_DEBUG_PATH_CLK_EN_OFF (19u)
+
+/** \brief Length for Ifx_CIF_ICCL_Bits.CIF_EXTRA_PATHS_CLK_ENABLE */
+#define IFX_CIF_ICCL_CIF_EXTRA_PATHS_CLK_ENABLE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ICCL_Bits.CIF_EXTRA_PATHS_CLK_ENABLE */
+#define IFX_CIF_ICCL_CIF_EXTRA_PATHS_CLK_ENABLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ICCL_Bits.CIF_EXTRA_PATHS_CLK_ENABLE */
+#define IFX_CIF_ICCL_CIF_EXTRA_PATHS_CLK_ENABLE_OFF (18u)
+
+/** \brief Length for Ifx_CIF_ICCL_Bits.CIF_ISP_CLK_ENABLE */
+#define IFX_CIF_ICCL_CIF_ISP_CLK_ENABLE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ICCL_Bits.CIF_ISP_CLK_ENABLE */
+#define IFX_CIF_ICCL_CIF_ISP_CLK_ENABLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ICCL_Bits.CIF_ISP_CLK_ENABLE */
+#define IFX_CIF_ICCL_CIF_ISP_CLK_ENABLE_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ICCL_Bits.CIF_JPEG_CLK_ENABLE */
+#define IFX_CIF_ICCL_CIF_JPEG_CLK_ENABLE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ICCL_Bits.CIF_JPEG_CLK_ENABLE */
+#define IFX_CIF_ICCL_CIF_JPEG_CLK_ENABLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ICCL_Bits.CIF_JPEG_CLK_ENABLE */
+#define IFX_CIF_ICCL_CIF_JPEG_CLK_ENABLE_OFF (5u)
+
+/** \brief Length for Ifx_CIF_ICCL_Bits.CIF_LIN_DSCALER_CLK_ENABLE */
+#define IFX_CIF_ICCL_CIF_LIN_DSCALER_CLK_ENABLE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ICCL_Bits.CIF_LIN_DSCALER_CLK_ENABLE */
+#define IFX_CIF_ICCL_CIF_LIN_DSCALER_CLK_ENABLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ICCL_Bits.CIF_LIN_DSCALER_CLK_ENABLE */
+#define IFX_CIF_ICCL_CIF_LIN_DSCALER_CLK_ENABLE_OFF (17u)
+
+/** \brief Length for Ifx_CIF_ICCL_Bits.CIF_MI_CLK_ENABLE */
+#define IFX_CIF_ICCL_CIF_MI_CLK_ENABLE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ICCL_Bits.CIF_MI_CLK_ENABLE */
+#define IFX_CIF_ICCL_CIF_MI_CLK_ENABLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ICCL_Bits.CIF_MI_CLK_ENABLE */
+#define IFX_CIF_ICCL_CIF_MI_CLK_ENABLE_OFF (6u)
+
+/** \brief Length for Ifx_CIF_ICCL_Bits.CIF_WATCHDOG_CLK_ENABLE */
+#define IFX_CIF_ICCL_CIF_WATCHDOG_CLK_ENABLE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ICCL_Bits.CIF_WATCHDOG_CLK_ENABLE */
+#define IFX_CIF_ICCL_CIF_WATCHDOG_CLK_ENABLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ICCL_Bits.CIF_WATCHDOG_CLK_ENABLE */
+#define IFX_CIF_ICCL_CIF_WATCHDOG_CLK_ENABLE_OFF (16u)
+
+/** \brief Length for Ifx_CIF_ID_Bits.MODNUMBER */
+#define IFX_CIF_ID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_CIF_ID_Bits.MODNUMBER */
+#define IFX_CIF_ID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CIF_ID_Bits.MODNUMBER */
+#define IFX_CIF_ID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_CIF_ID_Bits.MODREV */
+#define IFX_CIF_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_CIF_ID_Bits.MODREV */
+#define IFX_CIF_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_CIF_ID_Bits.MODREV */
+#define IFX_CIF_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ID_Bits.MODTYPE */
+#define IFX_CIF_ID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_CIF_ID_Bits.MODTYPE */
+#define IFX_CIF_ID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_CIF_ID_Bits.MODTYPE */
+#define IFX_CIF_ID_MODTYPE_OFF (8u)
+
+/** \brief Length for Ifx_CIF_IRCL_Bits.CIF_DEBUG_PATH_RST */
+#define IFX_CIF_IRCL_CIF_DEBUG_PATH_RST_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_IRCL_Bits.CIF_DEBUG_PATH_RST */
+#define IFX_CIF_IRCL_CIF_DEBUG_PATH_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_IRCL_Bits.CIF_DEBUG_PATH_RST */
+#define IFX_CIF_IRCL_CIF_DEBUG_PATH_RST_OFF (19u)
+
+/** \brief Length for Ifx_CIF_IRCL_Bits.CIF_EXTRA_PATHS_RST */
+#define IFX_CIF_IRCL_CIF_EXTRA_PATHS_RST_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_IRCL_Bits.CIF_EXTRA_PATHS_RST */
+#define IFX_CIF_IRCL_CIF_EXTRA_PATHS_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_IRCL_Bits.CIF_EXTRA_PATHS_RST */
+#define IFX_CIF_IRCL_CIF_EXTRA_PATHS_RST_OFF (18u)
+
+/** \brief Length for Ifx_CIF_IRCL_Bits.CIF_GLOBAL_RST */
+#define IFX_CIF_IRCL_CIF_GLOBAL_RST_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_IRCL_Bits.CIF_GLOBAL_RST */
+#define IFX_CIF_IRCL_CIF_GLOBAL_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_IRCL_Bits.CIF_GLOBAL_RST */
+#define IFX_CIF_IRCL_CIF_GLOBAL_RST_OFF (7u)
+
+/** \brief Length for Ifx_CIF_IRCL_Bits.CIF_ISP_SOFT_RST */
+#define IFX_CIF_IRCL_CIF_ISP_SOFT_RST_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_IRCL_Bits.CIF_ISP_SOFT_RST */
+#define IFX_CIF_IRCL_CIF_ISP_SOFT_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_IRCL_Bits.CIF_ISP_SOFT_RST */
+#define IFX_CIF_IRCL_CIF_ISP_SOFT_RST_OFF (0u)
+
+/** \brief Length for Ifx_CIF_IRCL_Bits.CIF_JPEG_SOFT_RST */
+#define IFX_CIF_IRCL_CIF_JPEG_SOFT_RST_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_IRCL_Bits.CIF_JPEG_SOFT_RST */
+#define IFX_CIF_IRCL_CIF_JPEG_SOFT_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_IRCL_Bits.CIF_JPEG_SOFT_RST */
+#define IFX_CIF_IRCL_CIF_JPEG_SOFT_RST_OFF (5u)
+
+/** \brief Length for Ifx_CIF_IRCL_Bits.CIF_LIN_DSCALER_RST */
+#define IFX_CIF_IRCL_CIF_LIN_DSCALER_RST_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_IRCL_Bits.CIF_LIN_DSCALER_RST */
+#define IFX_CIF_IRCL_CIF_LIN_DSCALER_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_IRCL_Bits.CIF_LIN_DSCALER_RST */
+#define IFX_CIF_IRCL_CIF_LIN_DSCALER_RST_OFF (17u)
+
+/** \brief Length for Ifx_CIF_IRCL_Bits.CIF_MI_SOFT_RST */
+#define IFX_CIF_IRCL_CIF_MI_SOFT_RST_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_IRCL_Bits.CIF_MI_SOFT_RST */
+#define IFX_CIF_IRCL_CIF_MI_SOFT_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_IRCL_Bits.CIF_MI_SOFT_RST */
+#define IFX_CIF_IRCL_CIF_MI_SOFT_RST_OFF (6u)
+
+/** \brief Length for Ifx_CIF_IRCL_Bits.CIF_WATCHDOG_RST */
+#define IFX_CIF_IRCL_CIF_WATCHDOG_RST_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_IRCL_Bits.CIF_WATCHDOG_RST */
+#define IFX_CIF_IRCL_CIF_WATCHDOG_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_IRCL_Bits.CIF_WATCHDOG_RST */
+#define IFX_CIF_IRCL_CIF_WATCHDOG_RST_OFF (16u)
+
+/** \brief Length for Ifx_CIF_IRCL_Bits.CIF_YCS_SOFT_RST */
+#define IFX_CIF_IRCL_CIF_YCS_SOFT_RST_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_IRCL_Bits.CIF_YCS_SOFT_RST */
+#define IFX_CIF_IRCL_CIF_YCS_SOFT_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_IRCL_Bits.CIF_YCS_SOFT_RST */
+#define IFX_CIF_IRCL_CIF_YCS_SOFT_RST_OFF (2u)
+
+/** \brief Length for Ifx_CIF_ISP_ACQ_H_OFFS_Bits.ACQ_H_OFFS */
+#define IFX_CIF_ISP_ACQ_H_OFFS_ACQ_H_OFFS_LEN (13u)
+
+/** \brief Mask for Ifx_CIF_ISP_ACQ_H_OFFS_Bits.ACQ_H_OFFS */
+#define IFX_CIF_ISP_ACQ_H_OFFS_ACQ_H_OFFS_MSK (0x1fffu)
+
+/** \brief Offset for Ifx_CIF_ISP_ACQ_H_OFFS_Bits.ACQ_H_OFFS */
+#define IFX_CIF_ISP_ACQ_H_OFFS_ACQ_H_OFFS_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISP_ACQ_H_SIZE_Bits.ACQ_H_SIZE */
+#define IFX_CIF_ISP_ACQ_H_SIZE_ACQ_H_SIZE_LEN (13u)
+
+/** \brief Mask for Ifx_CIF_ISP_ACQ_H_SIZE_Bits.ACQ_H_SIZE */
+#define IFX_CIF_ISP_ACQ_H_SIZE_ACQ_H_SIZE_MSK (0x1fffu)
+
+/** \brief Offset for Ifx_CIF_ISP_ACQ_H_SIZE_Bits.ACQ_H_SIZE */
+#define IFX_CIF_ISP_ACQ_H_SIZE_ACQ_H_SIZE_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISP_ACQ_NR_FRAMES_Bits.ACQ_NR_FRAMES */
+#define IFX_CIF_ISP_ACQ_NR_FRAMES_ACQ_NR_FRAMES_LEN (10u)
+
+/** \brief Mask for Ifx_CIF_ISP_ACQ_NR_FRAMES_Bits.ACQ_NR_FRAMES */
+#define IFX_CIF_ISP_ACQ_NR_FRAMES_ACQ_NR_FRAMES_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_CIF_ISP_ACQ_NR_FRAMES_Bits.ACQ_NR_FRAMES */
+#define IFX_CIF_ISP_ACQ_NR_FRAMES_ACQ_NR_FRAMES_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISP_ACQ_PROP_Bits.CCIR_SEQ */
+#define IFX_CIF_ISP_ACQ_PROP_CCIR_SEQ_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_ISP_ACQ_PROP_Bits.CCIR_SEQ */
+#define IFX_CIF_ISP_ACQ_PROP_CCIR_SEQ_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_ISP_ACQ_PROP_Bits.CCIR_SEQ */
+#define IFX_CIF_ISP_ACQ_PROP_CCIR_SEQ_OFF (7u)
+
+/** \brief Length for Ifx_CIF_ISP_ACQ_PROP_Bits.FIELD_INVERT */
+#define IFX_CIF_ISP_ACQ_PROP_FIELD_INVERT_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_ACQ_PROP_Bits.FIELD_INVERT */
+#define IFX_CIF_ISP_ACQ_PROP_FIELD_INVERT_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_ACQ_PROP_Bits.FIELD_INVERT */
+#define IFX_CIF_ISP_ACQ_PROP_FIELD_INVERT_OFF (11u)
+
+/** \brief Length for Ifx_CIF_ISP_ACQ_PROP_Bits.FIELD_SELECTION */
+#define IFX_CIF_ISP_ACQ_PROP_FIELD_SELECTION_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_ISP_ACQ_PROP_Bits.FIELD_SELECTION */
+#define IFX_CIF_ISP_ACQ_PROP_FIELD_SELECTION_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_ISP_ACQ_PROP_Bits.FIELD_SELECTION */
+#define IFX_CIF_ISP_ACQ_PROP_FIELD_SELECTION_OFF (9u)
+
+/** \brief Length for Ifx_CIF_ISP_ACQ_PROP_Bits.HSYNC_POL */
+#define IFX_CIF_ISP_ACQ_PROP_HSYNC_POL_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_ACQ_PROP_Bits.HSYNC_POL */
+#define IFX_CIF_ISP_ACQ_PROP_HSYNC_POL_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_ACQ_PROP_Bits.HSYNC_POL */
+#define IFX_CIF_ISP_ACQ_PROP_HSYNC_POL_OFF (1u)
+
+/** \brief Length for Ifx_CIF_ISP_ACQ_PROP_Bits.INPUT_SELECTION */
+#define IFX_CIF_ISP_ACQ_PROP_INPUT_SELECTION_LEN (4u)
+
+/** \brief Mask for Ifx_CIF_ISP_ACQ_PROP_Bits.INPUT_SELECTION */
+#define IFX_CIF_ISP_ACQ_PROP_INPUT_SELECTION_MSK (0xfu)
+
+/** \brief Length for Ifx_CIF_ISP_ACQ_PROP_Bits.INPUT_SELECTION_NO_APP */
+#define IFX_CIF_ISP_ACQ_PROP_INPUT_SELECTION_NO_APP_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_ACQ_PROP_Bits.INPUT_SELECTION_NO_APP */
+#define IFX_CIF_ISP_ACQ_PROP_INPUT_SELECTION_NO_APP_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_ACQ_PROP_Bits.INPUT_SELECTION_NO_APP */
+#define IFX_CIF_ISP_ACQ_PROP_INPUT_SELECTION_NO_APP_OFF (20u)
+
+/** \brief Offset for Ifx_CIF_ISP_ACQ_PROP_Bits.INPUT_SELECTION */
+#define IFX_CIF_ISP_ACQ_PROP_INPUT_SELECTION_OFF (12u)
+
+/** \brief Length for Ifx_CIF_ISP_ACQ_PROP_Bits.SAMPLE_EDGE */
+#define IFX_CIF_ISP_ACQ_PROP_SAMPLE_EDGE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_ACQ_PROP_Bits.SAMPLE_EDGE */
+#define IFX_CIF_ISP_ACQ_PROP_SAMPLE_EDGE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_ACQ_PROP_Bits.SAMPLE_EDGE */
+#define IFX_CIF_ISP_ACQ_PROP_SAMPLE_EDGE_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISP_ACQ_PROP_Bits.VSYNC_POL */
+#define IFX_CIF_ISP_ACQ_PROP_VSYNC_POL_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_ACQ_PROP_Bits.VSYNC_POL */
+#define IFX_CIF_ISP_ACQ_PROP_VSYNC_POL_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_ACQ_PROP_Bits.VSYNC_POL */
+#define IFX_CIF_ISP_ACQ_PROP_VSYNC_POL_OFF (2u)
+
+/** \brief Length for Ifx_CIF_ISP_ACQ_V_OFFS_Bits.ACQ_V_OFFS */
+#define IFX_CIF_ISP_ACQ_V_OFFS_ACQ_V_OFFS_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_ISP_ACQ_V_OFFS_Bits.ACQ_V_OFFS */
+#define IFX_CIF_ISP_ACQ_V_OFFS_ACQ_V_OFFS_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_ISP_ACQ_V_OFFS_Bits.ACQ_V_OFFS */
+#define IFX_CIF_ISP_ACQ_V_OFFS_ACQ_V_OFFS_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISP_ACQ_V_SIZE_Bits.ACQ_V_SIZE */
+#define IFX_CIF_ISP_ACQ_V_SIZE_ACQ_V_SIZE_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_ISP_ACQ_V_SIZE_Bits.ACQ_V_SIZE */
+#define IFX_CIF_ISP_ACQ_V_SIZE_ACQ_V_SIZE_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_ISP_ACQ_V_SIZE_Bits.ACQ_V_SIZE */
+#define IFX_CIF_ISP_ACQ_V_SIZE_ACQ_V_SIZE_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISP_CTRL_Bits.ISP_CFG_UPD */
+#define IFX_CIF_ISP_CTRL_ISP_CFG_UPD_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_CTRL_Bits.ISP_CFG_UPD */
+#define IFX_CIF_ISP_CTRL_ISP_CFG_UPD_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_CTRL_Bits.ISP_CFG_UPD */
+#define IFX_CIF_ISP_CTRL_ISP_CFG_UPD_OFF (9u)
+
+/** \brief Length for Ifx_CIF_ISP_CTRL_Bits.ISP_CSM_C_RANGE */
+#define IFX_CIF_ISP_CTRL_ISP_CSM_C_RANGE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_CTRL_Bits.ISP_CSM_C_RANGE */
+#define IFX_CIF_ISP_CTRL_ISP_CSM_C_RANGE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_CTRL_Bits.ISP_CSM_C_RANGE */
+#define IFX_CIF_ISP_CTRL_ISP_CSM_C_RANGE_OFF (14u)
+
+/** \brief Length for Ifx_CIF_ISP_CTRL_Bits.ISP_CSM_Y_RANGE */
+#define IFX_CIF_ISP_CTRL_ISP_CSM_Y_RANGE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_CTRL_Bits.ISP_CSM_Y_RANGE */
+#define IFX_CIF_ISP_CTRL_ISP_CSM_Y_RANGE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_CTRL_Bits.ISP_CSM_Y_RANGE */
+#define IFX_CIF_ISP_CTRL_ISP_CSM_Y_RANGE_OFF (13u)
+
+/** \brief Length for Ifx_CIF_ISP_CTRL_Bits.ISP_ENABLE */
+#define IFX_CIF_ISP_CTRL_ISP_ENABLE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_CTRL_Bits.ISP_ENABLE */
+#define IFX_CIF_ISP_CTRL_ISP_ENABLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_CTRL_Bits.ISP_ENABLE */
+#define IFX_CIF_ISP_CTRL_ISP_ENABLE_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISP_CTRL_Bits.ISP_GEN_CFG_UPD */
+#define IFX_CIF_ISP_CTRL_ISP_GEN_CFG_UPD_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_CTRL_Bits.ISP_GEN_CFG_UPD */
+#define IFX_CIF_ISP_CTRL_ISP_GEN_CFG_UPD_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_CTRL_Bits.ISP_GEN_CFG_UPD */
+#define IFX_CIF_ISP_CTRL_ISP_GEN_CFG_UPD_OFF (10u)
+
+/** \brief Length for Ifx_CIF_ISP_CTRL_Bits.ISP_INFORM_ENABLE */
+#define IFX_CIF_ISP_CTRL_ISP_INFORM_ENABLE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_CTRL_Bits.ISP_INFORM_ENABLE */
+#define IFX_CIF_ISP_CTRL_ISP_INFORM_ENABLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_CTRL_Bits.ISP_INFORM_ENABLE */
+#define IFX_CIF_ISP_CTRL_ISP_INFORM_ENABLE_OFF (4u)
+
+/** \brief Length for Ifx_CIF_ISP_CTRL_Bits.ISP_MODE */
+#define IFX_CIF_ISP_CTRL_ISP_MODE_LEN (3u)
+
+/** \brief Mask for Ifx_CIF_ISP_CTRL_Bits.ISP_MODE */
+#define IFX_CIF_ISP_CTRL_ISP_MODE_MSK (0x7u)
+
+/** \brief Offset for Ifx_CIF_ISP_CTRL_Bits.ISP_MODE */
+#define IFX_CIF_ISP_CTRL_ISP_MODE_OFF (1u)
+
+/** \brief Length for Ifx_CIF_ISP_ERR_CLR_Bits.INFORM_SIZE_ERR_CLR */
+#define IFX_CIF_ISP_ERR_CLR_INFORM_SIZE_ERR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_ERR_CLR_Bits.INFORM_SIZE_ERR_CLR */
+#define IFX_CIF_ISP_ERR_CLR_INFORM_SIZE_ERR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_ERR_CLR_Bits.INFORM_SIZE_ERR_CLR */
+#define IFX_CIF_ISP_ERR_CLR_INFORM_SIZE_ERR_CLR_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISP_ERR_CLR_Bits.IS_SIZE_ERR_CLR */
+#define IFX_CIF_ISP_ERR_CLR_IS_SIZE_ERR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_ERR_CLR_Bits.IS_SIZE_ERR_CLR */
+#define IFX_CIF_ISP_ERR_CLR_IS_SIZE_ERR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_ERR_CLR_Bits.IS_SIZE_ERR_CLR */
+#define IFX_CIF_ISP_ERR_CLR_IS_SIZE_ERR_CLR_OFF (1u)
+
+/** \brief Length for Ifx_CIF_ISP_ERR_CLR_Bits.OUTFORM_SIZE_ERR_CLR */
+#define IFX_CIF_ISP_ERR_CLR_OUTFORM_SIZE_ERR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_ERR_CLR_Bits.OUTFORM_SIZE_ERR_CLR */
+#define IFX_CIF_ISP_ERR_CLR_OUTFORM_SIZE_ERR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_ERR_CLR_Bits.OUTFORM_SIZE_ERR_CLR */
+#define IFX_CIF_ISP_ERR_CLR_OUTFORM_SIZE_ERR_CLR_OFF (2u)
+
+/** \brief Length for Ifx_CIF_ISP_ERR_Bits.INFORM_SIZE_ERR */
+#define IFX_CIF_ISP_ERR_INFORM_SIZE_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_ERR_Bits.INFORM_SIZE_ERR */
+#define IFX_CIF_ISP_ERR_INFORM_SIZE_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_ERR_Bits.INFORM_SIZE_ERR */
+#define IFX_CIF_ISP_ERR_INFORM_SIZE_ERR_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISP_ERR_Bits.IS_SIZE_ERR */
+#define IFX_CIF_ISP_ERR_IS_SIZE_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_ERR_Bits.IS_SIZE_ERR */
+#define IFX_CIF_ISP_ERR_IS_SIZE_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_ERR_Bits.IS_SIZE_ERR */
+#define IFX_CIF_ISP_ERR_IS_SIZE_ERR_OFF (1u)
+
+/** \brief Length for Ifx_CIF_ISP_ERR_Bits.OUTFORM_SIZE_ERR */
+#define IFX_CIF_ISP_ERR_OUTFORM_SIZE_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_ERR_Bits.OUTFORM_SIZE_ERR */
+#define IFX_CIF_ISP_ERR_OUTFORM_SIZE_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_ERR_Bits.OUTFORM_SIZE_ERR */
+#define IFX_CIF_ISP_ERR_OUTFORM_SIZE_ERR_OFF (2u)
+
+/** \brief Length for Ifx_CIF_ISP_FLAGS_SHD_Bits.INFORM_FIELD */
+#define IFX_CIF_ISP_FLAGS_SHD_INFORM_FIELD_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_FLAGS_SHD_Bits.INFORM_FIELD */
+#define IFX_CIF_ISP_FLAGS_SHD_INFORM_FIELD_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_FLAGS_SHD_Bits.INFORM_FIELD */
+#define IFX_CIF_ISP_FLAGS_SHD_INFORM_FIELD_OFF (2u)
+
+/** \brief Length for Ifx_CIF_ISP_FLAGS_SHD_Bits.ISP_ENABLE_SHD */
+#define IFX_CIF_ISP_FLAGS_SHD_ISP_ENABLE_SHD_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_FLAGS_SHD_Bits.ISP_ENABLE_SHD */
+#define IFX_CIF_ISP_FLAGS_SHD_ISP_ENABLE_SHD_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_FLAGS_SHD_Bits.ISP_ENABLE_SHD */
+#define IFX_CIF_ISP_FLAGS_SHD_ISP_ENABLE_SHD_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISP_FLAGS_SHD_Bits.ISP_INFORM_ENABLE_SHD */
+#define IFX_CIF_ISP_FLAGS_SHD_ISP_INFORM_ENABLE_SHD_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_FLAGS_SHD_Bits.ISP_INFORM_ENABLE_SHD */
+#define IFX_CIF_ISP_FLAGS_SHD_ISP_INFORM_ENABLE_SHD_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_FLAGS_SHD_Bits.ISP_INFORM_ENABLE_SHD */
+#define IFX_CIF_ISP_FLAGS_SHD_ISP_INFORM_ENABLE_SHD_OFF (1u)
+
+/** \brief Length for Ifx_CIF_ISP_FLAGS_SHD_Bits.S_DATA */
+#define IFX_CIF_ISP_FLAGS_SHD_S_DATA_LEN (16u)
+
+/** \brief Mask for Ifx_CIF_ISP_FLAGS_SHD_Bits.S_DATA */
+#define IFX_CIF_ISP_FLAGS_SHD_S_DATA_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CIF_ISP_FLAGS_SHD_Bits.S_DATA */
+#define IFX_CIF_ISP_FLAGS_SHD_S_DATA_OFF (14u)
+
+/** \brief Length for Ifx_CIF_ISP_FLAGS_SHD_Bits.S_HSYNC */
+#define IFX_CIF_ISP_FLAGS_SHD_S_HSYNC_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_FLAGS_SHD_Bits.S_HSYNC */
+#define IFX_CIF_ISP_FLAGS_SHD_S_HSYNC_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_FLAGS_SHD_Bits.S_HSYNC */
+#define IFX_CIF_ISP_FLAGS_SHD_S_HSYNC_OFF (31u)
+
+/** \brief Length for Ifx_CIF_ISP_FLAGS_SHD_Bits.S_VSYNC */
+#define IFX_CIF_ISP_FLAGS_SHD_S_VSYNC_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_FLAGS_SHD_Bits.S_VSYNC */
+#define IFX_CIF_ISP_FLAGS_SHD_S_VSYNC_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_FLAGS_SHD_Bits.S_VSYNC */
+#define IFX_CIF_ISP_FLAGS_SHD_S_VSYNC_OFF (30u)
+
+/** \brief Length for Ifx_CIF_ISP_FRAME_COUNT_Bits.FRAME_COUNTER */
+#define IFX_CIF_ISP_FRAME_COUNT_FRAME_COUNTER_LEN (10u)
+
+/** \brief Mask for Ifx_CIF_ISP_FRAME_COUNT_Bits.FRAME_COUNTER */
+#define IFX_CIF_ISP_FRAME_COUNT_FRAME_COUNTER_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_CIF_ISP_FRAME_COUNT_Bits.FRAME_COUNTER */
+#define IFX_CIF_ISP_FRAME_COUNT_FRAME_COUNTER_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISP_ICR_Bits.ICR_DATA_LOSS */
+#define IFX_CIF_ISP_ICR_ICR_DATA_LOSS_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_ICR_Bits.ICR_DATA_LOSS */
+#define IFX_CIF_ISP_ICR_ICR_DATA_LOSS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_ICR_Bits.ICR_DATA_LOSS */
+#define IFX_CIF_ISP_ICR_ICR_DATA_LOSS_OFF (2u)
+
+/** \brief Length for Ifx_CIF_ISP_ICR_Bits.ICR_FRAME_IN */
+#define IFX_CIF_ISP_ICR_ICR_FRAME_IN_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_ICR_Bits.ICR_FRAME_IN */
+#define IFX_CIF_ISP_ICR_ICR_FRAME_IN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_ICR_Bits.ICR_FRAME_IN */
+#define IFX_CIF_ISP_ICR_ICR_FRAME_IN_OFF (5u)
+
+/** \brief Length for Ifx_CIF_ISP_ICR_Bits.ICR_FRAME */
+#define IFX_CIF_ISP_ICR_ICR_FRAME_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_ICR_Bits.ICR_FRAME */
+#define IFX_CIF_ISP_ICR_ICR_FRAME_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_ICR_Bits.ICR_FRAME */
+#define IFX_CIF_ISP_ICR_ICR_FRAME_OFF (1u)
+
+/** \brief Length for Ifx_CIF_ISP_ICR_Bits.ICR_H_START */
+#define IFX_CIF_ISP_ICR_ICR_H_START_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_ICR_Bits.ICR_H_START */
+#define IFX_CIF_ISP_ICR_ICR_H_START_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_ICR_Bits.ICR_H_START */
+#define IFX_CIF_ISP_ICR_ICR_H_START_OFF (7u)
+
+/** \brief Length for Ifx_CIF_ISP_ICR_Bits.ICR_ISP_OFF */
+#define IFX_CIF_ISP_ICR_ICR_ISP_OFF_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_ICR_Bits.ICR_ISP_OFF */
+#define IFX_CIF_ISP_ICR_ICR_ISP_OFF_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_ICR_Bits.ICR_ISP_OFF */
+#define IFX_CIF_ISP_ICR_ICR_ISP_OFF_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISP_ICR_Bits.ICR_PIC_SIZE_ERR */
+#define IFX_CIF_ISP_ICR_ICR_PIC_SIZE_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_ICR_Bits.ICR_PIC_SIZE_ERR */
+#define IFX_CIF_ISP_ICR_ICR_PIC_SIZE_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_ICR_Bits.ICR_PIC_SIZE_ERR */
+#define IFX_CIF_ISP_ICR_ICR_PIC_SIZE_ERR_OFF (3u)
+
+/** \brief Length for Ifx_CIF_ISP_ICR_Bits.ICR_V_START */
+#define IFX_CIF_ISP_ICR_ICR_V_START_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_ICR_Bits.ICR_V_START */
+#define IFX_CIF_ISP_ICR_ICR_V_START_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_ICR_Bits.ICR_V_START */
+#define IFX_CIF_ISP_ICR_ICR_V_START_OFF (6u)
+
+/** \brief Length for Ifx_CIF_ISP_ICR_Bits.ICR_WD_TRIG */
+#define IFX_CIF_ISP_ICR_ICR_WD_TRIG_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_ICR_Bits.ICR_WD_TRIG */
+#define IFX_CIF_ISP_ICR_ICR_WD_TRIG_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_ICR_Bits.ICR_WD_TRIG */
+#define IFX_CIF_ISP_ICR_ICR_WD_TRIG_OFF (19u)
+
+/** \brief Length for Ifx_CIF_ISP_IMSC_Bits.IMSC_DATA_LOSS */
+#define IFX_CIF_ISP_IMSC_IMSC_DATA_LOSS_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_IMSC_Bits.IMSC_DATA_LOSS */
+#define IFX_CIF_ISP_IMSC_IMSC_DATA_LOSS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_IMSC_Bits.IMSC_DATA_LOSS */
+#define IFX_CIF_ISP_IMSC_IMSC_DATA_LOSS_OFF (2u)
+
+/** \brief Length for Ifx_CIF_ISP_IMSC_Bits.IMSC_FRAME_IN */
+#define IFX_CIF_ISP_IMSC_IMSC_FRAME_IN_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_IMSC_Bits.IMSC_FRAME_IN */
+#define IFX_CIF_ISP_IMSC_IMSC_FRAME_IN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_IMSC_Bits.IMSC_FRAME_IN */
+#define IFX_CIF_ISP_IMSC_IMSC_FRAME_IN_OFF (5u)
+
+/** \brief Length for Ifx_CIF_ISP_IMSC_Bits.IMSC_FRAME */
+#define IFX_CIF_ISP_IMSC_IMSC_FRAME_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_IMSC_Bits.IMSC_FRAME */
+#define IFX_CIF_ISP_IMSC_IMSC_FRAME_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_IMSC_Bits.IMSC_FRAME */
+#define IFX_CIF_ISP_IMSC_IMSC_FRAME_OFF (1u)
+
+/** \brief Length for Ifx_CIF_ISP_IMSC_Bits.IMSC_H_START */
+#define IFX_CIF_ISP_IMSC_IMSC_H_START_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_IMSC_Bits.IMSC_H_START */
+#define IFX_CIF_ISP_IMSC_IMSC_H_START_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_IMSC_Bits.IMSC_H_START */
+#define IFX_CIF_ISP_IMSC_IMSC_H_START_OFF (7u)
+
+/** \brief Length for Ifx_CIF_ISP_IMSC_Bits.IMSC_ISP_OFF */
+#define IFX_CIF_ISP_IMSC_IMSC_ISP_OFF_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_IMSC_Bits.IMSC_ISP_OFF */
+#define IFX_CIF_ISP_IMSC_IMSC_ISP_OFF_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_IMSC_Bits.IMSC_ISP_OFF */
+#define IFX_CIF_ISP_IMSC_IMSC_ISP_OFF_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISP_IMSC_Bits.IMSC_PIC_SIZE_ERR */
+#define IFX_CIF_ISP_IMSC_IMSC_PIC_SIZE_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_IMSC_Bits.IMSC_PIC_SIZE_ERR */
+#define IFX_CIF_ISP_IMSC_IMSC_PIC_SIZE_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_IMSC_Bits.IMSC_PIC_SIZE_ERR */
+#define IFX_CIF_ISP_IMSC_IMSC_PIC_SIZE_ERR_OFF (3u)
+
+/** \brief Length for Ifx_CIF_ISP_IMSC_Bits.IMSC_V_START */
+#define IFX_CIF_ISP_IMSC_IMSC_V_START_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_IMSC_Bits.IMSC_V_START */
+#define IFX_CIF_ISP_IMSC_IMSC_V_START_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_IMSC_Bits.IMSC_V_START */
+#define IFX_CIF_ISP_IMSC_IMSC_V_START_OFF (6u)
+
+/** \brief Length for Ifx_CIF_ISP_IMSC_Bits.IMSC_WD_TRIG */
+#define IFX_CIF_ISP_IMSC_IMSC_WD_TRIG_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_IMSC_Bits.IMSC_WD_TRIG */
+#define IFX_CIF_ISP_IMSC_IMSC_WD_TRIG_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_IMSC_Bits.IMSC_WD_TRIG */
+#define IFX_CIF_ISP_IMSC_IMSC_WD_TRIG_OFF (19u)
+
+/** \brief Length for Ifx_CIF_ISP_ISR_Bits.ISR_DATA_LOSS */
+#define IFX_CIF_ISP_ISR_ISR_DATA_LOSS_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_ISR_Bits.ISR_DATA_LOSS */
+#define IFX_CIF_ISP_ISR_ISR_DATA_LOSS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_ISR_Bits.ISR_DATA_LOSS */
+#define IFX_CIF_ISP_ISR_ISR_DATA_LOSS_OFF (2u)
+
+/** \brief Length for Ifx_CIF_ISP_ISR_Bits.ISR_FRAME_IN */
+#define IFX_CIF_ISP_ISR_ISR_FRAME_IN_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_ISR_Bits.ISR_FRAME_IN */
+#define IFX_CIF_ISP_ISR_ISR_FRAME_IN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_ISR_Bits.ISR_FRAME_IN */
+#define IFX_CIF_ISP_ISR_ISR_FRAME_IN_OFF (5u)
+
+/** \brief Length for Ifx_CIF_ISP_ISR_Bits.ISR_FRAME */
+#define IFX_CIF_ISP_ISR_ISR_FRAME_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_ISR_Bits.ISR_FRAME */
+#define IFX_CIF_ISP_ISR_ISR_FRAME_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_ISR_Bits.ISR_FRAME */
+#define IFX_CIF_ISP_ISR_ISR_FRAME_OFF (1u)
+
+/** \brief Length for Ifx_CIF_ISP_ISR_Bits.ISR_H_START */
+#define IFX_CIF_ISP_ISR_ISR_H_START_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_ISR_Bits.ISR_H_START */
+#define IFX_CIF_ISP_ISR_ISR_H_START_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_ISR_Bits.ISR_H_START */
+#define IFX_CIF_ISP_ISR_ISR_H_START_OFF (7u)
+
+/** \brief Length for Ifx_CIF_ISP_ISR_Bits.ISR_ISP_OFF */
+#define IFX_CIF_ISP_ISR_ISR_ISP_OFF_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_ISR_Bits.ISR_ISP_OFF */
+#define IFX_CIF_ISP_ISR_ISR_ISP_OFF_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_ISR_Bits.ISR_ISP_OFF */
+#define IFX_CIF_ISP_ISR_ISR_ISP_OFF_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISP_ISR_Bits.ISR_PIC_SIZE_ERR */
+#define IFX_CIF_ISP_ISR_ISR_PIC_SIZE_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_ISR_Bits.ISR_PIC_SIZE_ERR */
+#define IFX_CIF_ISP_ISR_ISR_PIC_SIZE_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_ISR_Bits.ISR_PIC_SIZE_ERR */
+#define IFX_CIF_ISP_ISR_ISR_PIC_SIZE_ERR_OFF (3u)
+
+/** \brief Length for Ifx_CIF_ISP_ISR_Bits.ISR_V_START */
+#define IFX_CIF_ISP_ISR_ISR_V_START_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_ISR_Bits.ISR_V_START */
+#define IFX_CIF_ISP_ISR_ISR_V_START_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_ISR_Bits.ISR_V_START */
+#define IFX_CIF_ISP_ISR_ISR_V_START_OFF (6u)
+
+/** \brief Length for Ifx_CIF_ISP_ISR_Bits.ISR_WD_TRIG */
+#define IFX_CIF_ISP_ISR_ISR_WD_TRIG_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_ISR_Bits.ISR_WD_TRIG */
+#define IFX_CIF_ISP_ISR_ISR_WD_TRIG_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_ISR_Bits.ISR_WD_TRIG */
+#define IFX_CIF_ISP_ISR_ISR_WD_TRIG_OFF (19u)
+
+/** \brief Length for Ifx_CIF_ISP_MIS_Bits.MIS_DATA_LOSS */
+#define IFX_CIF_ISP_MIS_MIS_DATA_LOSS_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_MIS_Bits.MIS_DATA_LOSS */
+#define IFX_CIF_ISP_MIS_MIS_DATA_LOSS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_MIS_Bits.MIS_DATA_LOSS */
+#define IFX_CIF_ISP_MIS_MIS_DATA_LOSS_OFF (2u)
+
+/** \brief Length for Ifx_CIF_ISP_MIS_Bits.MIS_FRAME_IN */
+#define IFX_CIF_ISP_MIS_MIS_FRAME_IN_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_MIS_Bits.MIS_FRAME_IN */
+#define IFX_CIF_ISP_MIS_MIS_FRAME_IN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_MIS_Bits.MIS_FRAME_IN */
+#define IFX_CIF_ISP_MIS_MIS_FRAME_IN_OFF (5u)
+
+/** \brief Length for Ifx_CIF_ISP_MIS_Bits.MIS_FRAME */
+#define IFX_CIF_ISP_MIS_MIS_FRAME_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_MIS_Bits.MIS_FRAME */
+#define IFX_CIF_ISP_MIS_MIS_FRAME_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_MIS_Bits.MIS_FRAME */
+#define IFX_CIF_ISP_MIS_MIS_FRAME_OFF (1u)
+
+/** \brief Length for Ifx_CIF_ISP_MIS_Bits.MIS_H_START */
+#define IFX_CIF_ISP_MIS_MIS_H_START_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_MIS_Bits.MIS_H_START */
+#define IFX_CIF_ISP_MIS_MIS_H_START_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_MIS_Bits.MIS_H_START */
+#define IFX_CIF_ISP_MIS_MIS_H_START_OFF (7u)
+
+/** \brief Length for Ifx_CIF_ISP_MIS_Bits.MIS_ISP_OFF */
+#define IFX_CIF_ISP_MIS_MIS_ISP_OFF_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_MIS_Bits.MIS_ISP_OFF */
+#define IFX_CIF_ISP_MIS_MIS_ISP_OFF_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_MIS_Bits.MIS_ISP_OFF */
+#define IFX_CIF_ISP_MIS_MIS_ISP_OFF_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISP_MIS_Bits.MIS_PIC_SIZE_ERR */
+#define IFX_CIF_ISP_MIS_MIS_PIC_SIZE_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_MIS_Bits.MIS_PIC_SIZE_ERR */
+#define IFX_CIF_ISP_MIS_MIS_PIC_SIZE_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_MIS_Bits.MIS_PIC_SIZE_ERR */
+#define IFX_CIF_ISP_MIS_MIS_PIC_SIZE_ERR_OFF (3u)
+
+/** \brief Length for Ifx_CIF_ISP_MIS_Bits.MIS_V_START */
+#define IFX_CIF_ISP_MIS_MIS_V_START_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_MIS_Bits.MIS_V_START */
+#define IFX_CIF_ISP_MIS_MIS_V_START_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_MIS_Bits.MIS_V_START */
+#define IFX_CIF_ISP_MIS_MIS_V_START_OFF (6u)
+
+/** \brief Length for Ifx_CIF_ISP_MIS_Bits.MIS_WD_TRIG */
+#define IFX_CIF_ISP_MIS_MIS_WD_TRIG_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_MIS_Bits.MIS_WD_TRIG */
+#define IFX_CIF_ISP_MIS_MIS_WD_TRIG_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_MIS_Bits.MIS_WD_TRIG */
+#define IFX_CIF_ISP_MIS_MIS_WD_TRIG_OFF (19u)
+
+/** \brief Length for Ifx_CIF_ISP_OUT_H_OFFS_Bits.ISP_OUT_H_OFFS */
+#define IFX_CIF_ISP_OUT_H_OFFS_ISP_OUT_H_OFFS_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_ISP_OUT_H_OFFS_Bits.ISP_OUT_H_OFFS */
+#define IFX_CIF_ISP_OUT_H_OFFS_ISP_OUT_H_OFFS_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_ISP_OUT_H_OFFS_Bits.ISP_OUT_H_OFFS */
+#define IFX_CIF_ISP_OUT_H_OFFS_ISP_OUT_H_OFFS_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISP_OUT_H_OFFS_SHD_Bits.ISP_OUT_H_OFFS_SHD */
+#define IFX_CIF_ISP_OUT_H_OFFS_SHD_ISP_OUT_H_OFFS_SHD_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_ISP_OUT_H_OFFS_SHD_Bits.ISP_OUT_H_OFFS_SHD */
+#define IFX_CIF_ISP_OUT_H_OFFS_SHD_ISP_OUT_H_OFFS_SHD_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_ISP_OUT_H_OFFS_SHD_Bits.ISP_OUT_H_OFFS_SHD */
+#define IFX_CIF_ISP_OUT_H_OFFS_SHD_ISP_OUT_H_OFFS_SHD_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISP_OUT_H_SIZE_Bits.ISP_OUT_H_SIZE */
+#define IFX_CIF_ISP_OUT_H_SIZE_ISP_OUT_H_SIZE_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_ISP_OUT_H_SIZE_Bits.ISP_OUT_H_SIZE */
+#define IFX_CIF_ISP_OUT_H_SIZE_ISP_OUT_H_SIZE_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_ISP_OUT_H_SIZE_Bits.ISP_OUT_H_SIZE */
+#define IFX_CIF_ISP_OUT_H_SIZE_ISP_OUT_H_SIZE_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISP_OUT_H_SIZE_SHD_Bits.ISP_OUT_H_SIZE_SHD */
+#define IFX_CIF_ISP_OUT_H_SIZE_SHD_ISP_OUT_H_SIZE_SHD_LEN (13u)
+
+/** \brief Mask for Ifx_CIF_ISP_OUT_H_SIZE_SHD_Bits.ISP_OUT_H_SIZE_SHD */
+#define IFX_CIF_ISP_OUT_H_SIZE_SHD_ISP_OUT_H_SIZE_SHD_MSK (0x1fffu)
+
+/** \brief Offset for Ifx_CIF_ISP_OUT_H_SIZE_SHD_Bits.ISP_OUT_H_SIZE_SHD */
+#define IFX_CIF_ISP_OUT_H_SIZE_SHD_ISP_OUT_H_SIZE_SHD_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISP_OUT_V_OFFS_Bits.ISP_OUT_V_OFFS */
+#define IFX_CIF_ISP_OUT_V_OFFS_ISP_OUT_V_OFFS_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_ISP_OUT_V_OFFS_Bits.ISP_OUT_V_OFFS */
+#define IFX_CIF_ISP_OUT_V_OFFS_ISP_OUT_V_OFFS_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_ISP_OUT_V_OFFS_Bits.ISP_OUT_V_OFFS */
+#define IFX_CIF_ISP_OUT_V_OFFS_ISP_OUT_V_OFFS_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISP_OUT_V_OFFS_SHD_Bits.ISP_OUT_V_OFFS_SHD */
+#define IFX_CIF_ISP_OUT_V_OFFS_SHD_ISP_OUT_V_OFFS_SHD_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_ISP_OUT_V_OFFS_SHD_Bits.ISP_OUT_V_OFFS_SHD */
+#define IFX_CIF_ISP_OUT_V_OFFS_SHD_ISP_OUT_V_OFFS_SHD_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_ISP_OUT_V_OFFS_SHD_Bits.ISP_OUT_V_OFFS_SHD */
+#define IFX_CIF_ISP_OUT_V_OFFS_SHD_ISP_OUT_V_OFFS_SHD_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISP_OUT_V_SIZE_Bits.ISP_OUT_V_SIZE */
+#define IFX_CIF_ISP_OUT_V_SIZE_ISP_OUT_V_SIZE_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_ISP_OUT_V_SIZE_Bits.ISP_OUT_V_SIZE */
+#define IFX_CIF_ISP_OUT_V_SIZE_ISP_OUT_V_SIZE_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_ISP_OUT_V_SIZE_Bits.ISP_OUT_V_SIZE */
+#define IFX_CIF_ISP_OUT_V_SIZE_ISP_OUT_V_SIZE_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISP_OUT_V_SIZE_SHD_Bits.ISP_OUT_V_SIZE_SHD */
+#define IFX_CIF_ISP_OUT_V_SIZE_SHD_ISP_OUT_V_SIZE_SHD_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_ISP_OUT_V_SIZE_SHD_Bits.ISP_OUT_V_SIZE_SHD */
+#define IFX_CIF_ISP_OUT_V_SIZE_SHD_ISP_OUT_V_SIZE_SHD_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_ISP_OUT_V_SIZE_SHD_Bits.ISP_OUT_V_SIZE_SHD */
+#define IFX_CIF_ISP_OUT_V_SIZE_SHD_ISP_OUT_V_SIZE_SHD_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISP_RIS_Bits.RIS_DATA_LOSS */
+#define IFX_CIF_ISP_RIS_RIS_DATA_LOSS_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_RIS_Bits.RIS_DATA_LOSS */
+#define IFX_CIF_ISP_RIS_RIS_DATA_LOSS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_RIS_Bits.RIS_DATA_LOSS */
+#define IFX_CIF_ISP_RIS_RIS_DATA_LOSS_OFF (2u)
+
+/** \brief Length for Ifx_CIF_ISP_RIS_Bits.RIS_FRAME_IN */
+#define IFX_CIF_ISP_RIS_RIS_FRAME_IN_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_RIS_Bits.RIS_FRAME_IN */
+#define IFX_CIF_ISP_RIS_RIS_FRAME_IN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_RIS_Bits.RIS_FRAME_IN */
+#define IFX_CIF_ISP_RIS_RIS_FRAME_IN_OFF (5u)
+
+/** \brief Length for Ifx_CIF_ISP_RIS_Bits.RIS_FRAME */
+#define IFX_CIF_ISP_RIS_RIS_FRAME_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_RIS_Bits.RIS_FRAME */
+#define IFX_CIF_ISP_RIS_RIS_FRAME_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_RIS_Bits.RIS_FRAME */
+#define IFX_CIF_ISP_RIS_RIS_FRAME_OFF (1u)
+
+/** \brief Length for Ifx_CIF_ISP_RIS_Bits.RIS_H_START */
+#define IFX_CIF_ISP_RIS_RIS_H_START_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_RIS_Bits.RIS_H_START */
+#define IFX_CIF_ISP_RIS_RIS_H_START_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_RIS_Bits.RIS_H_START */
+#define IFX_CIF_ISP_RIS_RIS_H_START_OFF (7u)
+
+/** \brief Length for Ifx_CIF_ISP_RIS_Bits.RIS_ISP_OFF */
+#define IFX_CIF_ISP_RIS_RIS_ISP_OFF_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_RIS_Bits.RIS_ISP_OFF */
+#define IFX_CIF_ISP_RIS_RIS_ISP_OFF_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_RIS_Bits.RIS_ISP_OFF */
+#define IFX_CIF_ISP_RIS_RIS_ISP_OFF_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISP_RIS_Bits.RIS_PIC_SIZE_ERR */
+#define IFX_CIF_ISP_RIS_RIS_PIC_SIZE_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_RIS_Bits.RIS_PIC_SIZE_ERR */
+#define IFX_CIF_ISP_RIS_RIS_PIC_SIZE_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_RIS_Bits.RIS_PIC_SIZE_ERR */
+#define IFX_CIF_ISP_RIS_RIS_PIC_SIZE_ERR_OFF (3u)
+
+/** \brief Length for Ifx_CIF_ISP_RIS_Bits.RIS_V_START */
+#define IFX_CIF_ISP_RIS_RIS_V_START_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_RIS_Bits.RIS_V_START */
+#define IFX_CIF_ISP_RIS_RIS_V_START_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_RIS_Bits.RIS_V_START */
+#define IFX_CIF_ISP_RIS_RIS_V_START_OFF (6u)
+
+/** \brief Length for Ifx_CIF_ISP_RIS_Bits.RIS_WD_TRIG */
+#define IFX_CIF_ISP_RIS_RIS_WD_TRIG_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISP_RIS_Bits.RIS_WD_TRIG */
+#define IFX_CIF_ISP_RIS_RIS_WD_TRIG_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISP_RIS_Bits.RIS_WD_TRIG */
+#define IFX_CIF_ISP_RIS_RIS_WD_TRIG_OFF (19u)
+
+/** \brief Length for Ifx_CIF_ISPIS_CTRL_Bits.IS_EN */
+#define IFX_CIF_ISPIS_CTRL_IS_EN_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_ISPIS_CTRL_Bits.IS_EN */
+#define IFX_CIF_ISPIS_CTRL_IS_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_ISPIS_CTRL_Bits.IS_EN */
+#define IFX_CIF_ISPIS_CTRL_IS_EN_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISPIS_DISPLACE_Bits.DX */
+#define IFX_CIF_ISPIS_DISPLACE_DX_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_ISPIS_DISPLACE_Bits.DX */
+#define IFX_CIF_ISPIS_DISPLACE_DX_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_ISPIS_DISPLACE_Bits.DX */
+#define IFX_CIF_ISPIS_DISPLACE_DX_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISPIS_DISPLACE_Bits.DY */
+#define IFX_CIF_ISPIS_DISPLACE_DY_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_ISPIS_DISPLACE_Bits.DY */
+#define IFX_CIF_ISPIS_DISPLACE_DY_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_ISPIS_DISPLACE_Bits.DY */
+#define IFX_CIF_ISPIS_DISPLACE_DY_OFF (16u)
+
+/** \brief Length for Ifx_CIF_ISPIS_H_OFFS_Bits.IS_H_OFFS */
+#define IFX_CIF_ISPIS_H_OFFS_IS_H_OFFS_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_ISPIS_H_OFFS_Bits.IS_H_OFFS */
+#define IFX_CIF_ISPIS_H_OFFS_IS_H_OFFS_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_ISPIS_H_OFFS_Bits.IS_H_OFFS */
+#define IFX_CIF_ISPIS_H_OFFS_IS_H_OFFS_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISPIS_H_OFFS_SHD_Bits.IS_H_OFFS_SHD */
+#define IFX_CIF_ISPIS_H_OFFS_SHD_IS_H_OFFS_SHD_LEN (13u)
+
+/** \brief Mask for Ifx_CIF_ISPIS_H_OFFS_SHD_Bits.IS_H_OFFS_SHD */
+#define IFX_CIF_ISPIS_H_OFFS_SHD_IS_H_OFFS_SHD_MSK (0x1fffu)
+
+/** \brief Offset for Ifx_CIF_ISPIS_H_OFFS_SHD_Bits.IS_H_OFFS_SHD */
+#define IFX_CIF_ISPIS_H_OFFS_SHD_IS_H_OFFS_SHD_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISPIS_H_SIZE_Bits.IS_H_SIZE */
+#define IFX_CIF_ISPIS_H_SIZE_IS_H_SIZE_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_ISPIS_H_SIZE_Bits.IS_H_SIZE */
+#define IFX_CIF_ISPIS_H_SIZE_IS_H_SIZE_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_ISPIS_H_SIZE_Bits.IS_H_SIZE */
+#define IFX_CIF_ISPIS_H_SIZE_IS_H_SIZE_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISPIS_H_SIZE_SHD_Bits.ISP_H_SIZE_SHD */
+#define IFX_CIF_ISPIS_H_SIZE_SHD_ISP_H_SIZE_SHD_LEN (13u)
+
+/** \brief Mask for Ifx_CIF_ISPIS_H_SIZE_SHD_Bits.ISP_H_SIZE_SHD */
+#define IFX_CIF_ISPIS_H_SIZE_SHD_ISP_H_SIZE_SHD_MSK (0x1fffu)
+
+/** \brief Offset for Ifx_CIF_ISPIS_H_SIZE_SHD_Bits.ISP_H_SIZE_SHD */
+#define IFX_CIF_ISPIS_H_SIZE_SHD_ISP_H_SIZE_SHD_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISPIS_MAX_DX_Bits.IS_MAX_DX */
+#define IFX_CIF_ISPIS_MAX_DX_IS_MAX_DX_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_ISPIS_MAX_DX_Bits.IS_MAX_DX */
+#define IFX_CIF_ISPIS_MAX_DX_IS_MAX_DX_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_ISPIS_MAX_DX_Bits.IS_MAX_DX */
+#define IFX_CIF_ISPIS_MAX_DX_IS_MAX_DX_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISPIS_MAX_DY_Bits.IS_MAX_DY */
+#define IFX_CIF_ISPIS_MAX_DY_IS_MAX_DY_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_ISPIS_MAX_DY_Bits.IS_MAX_DY */
+#define IFX_CIF_ISPIS_MAX_DY_IS_MAX_DY_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_ISPIS_MAX_DY_Bits.IS_MAX_DY */
+#define IFX_CIF_ISPIS_MAX_DY_IS_MAX_DY_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISPIS_RECENTER_Bits.RECENTER */
+#define IFX_CIF_ISPIS_RECENTER_RECENTER_LEN (3u)
+
+/** \brief Mask for Ifx_CIF_ISPIS_RECENTER_Bits.RECENTER */
+#define IFX_CIF_ISPIS_RECENTER_RECENTER_MSK (0x7u)
+
+/** \brief Offset for Ifx_CIF_ISPIS_RECENTER_Bits.RECENTER */
+#define IFX_CIF_ISPIS_RECENTER_RECENTER_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISPIS_V_OFFS_Bits.IS_V_OFFS */
+#define IFX_CIF_ISPIS_V_OFFS_IS_V_OFFS_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_ISPIS_V_OFFS_Bits.IS_V_OFFS */
+#define IFX_CIF_ISPIS_V_OFFS_IS_V_OFFS_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_ISPIS_V_OFFS_Bits.IS_V_OFFS */
+#define IFX_CIF_ISPIS_V_OFFS_IS_V_OFFS_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISPIS_V_OFFS_SHD_Bits.IS_V_OFFS_SHD */
+#define IFX_CIF_ISPIS_V_OFFS_SHD_IS_V_OFFS_SHD_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_ISPIS_V_OFFS_SHD_Bits.IS_V_OFFS_SHD */
+#define IFX_CIF_ISPIS_V_OFFS_SHD_IS_V_OFFS_SHD_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_ISPIS_V_OFFS_SHD_Bits.IS_V_OFFS_SHD */
+#define IFX_CIF_ISPIS_V_OFFS_SHD_IS_V_OFFS_SHD_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISPIS_V_SIZE_Bits.IS_V_SIZE */
+#define IFX_CIF_ISPIS_V_SIZE_IS_V_SIZE_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_ISPIS_V_SIZE_Bits.IS_V_SIZE */
+#define IFX_CIF_ISPIS_V_SIZE_IS_V_SIZE_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_ISPIS_V_SIZE_Bits.IS_V_SIZE */
+#define IFX_CIF_ISPIS_V_SIZE_IS_V_SIZE_OFF (0u)
+
+/** \brief Length for Ifx_CIF_ISPIS_V_SIZE_SHD_Bits.ISP_V_SIZE_SHD */
+#define IFX_CIF_ISPIS_V_SIZE_SHD_ISP_V_SIZE_SHD_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_ISPIS_V_SIZE_SHD_Bits.ISP_V_SIZE_SHD */
+#define IFX_CIF_ISPIS_V_SIZE_SHD_ISP_V_SIZE_SHD_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_ISPIS_V_SIZE_SHD_Bits.ISP_V_SIZE_SHD */
+#define IFX_CIF_ISPIS_V_SIZE_SHD_ISP_V_SIZE_SHD_OFF (0u)
+
+/** \brief Length for Ifx_CIF_JPE_AC_TABLE_SELECT_Bits.AC_TABLE_SELECT */
+#define IFX_CIF_JPE_AC_TABLE_SELECT_AC_TABLE_SELECT_LEN (3u)
+
+/** \brief Mask for Ifx_CIF_JPE_AC_TABLE_SELECT_Bits.AC_TABLE_SELECT */
+#define IFX_CIF_JPE_AC_TABLE_SELECT_AC_TABLE_SELECT_MSK (0x7u)
+
+/** \brief Offset for Ifx_CIF_JPE_AC_TABLE_SELECT_Bits.AC_TABLE_SELECT */
+#define IFX_CIF_JPE_AC_TABLE_SELECT_AC_TABLE_SELECT_OFF (0u)
+
+/** \brief Length for Ifx_CIF_JPE_CBCR_SCALE_EN_Bits.CBCR_SCALE_EN */
+#define IFX_CIF_JPE_CBCR_SCALE_EN_CBCR_SCALE_EN_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_CBCR_SCALE_EN_Bits.CBCR_SCALE_EN */
+#define IFX_CIF_JPE_CBCR_SCALE_EN_CBCR_SCALE_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_CBCR_SCALE_EN_Bits.CBCR_SCALE_EN */
+#define IFX_CIF_JPE_CBCR_SCALE_EN_CBCR_SCALE_EN_OFF (0u)
+
+/** \brief Length for Ifx_CIF_JPE_DC_TABLE_SELECT_Bits.DC_TABLE_SELECT */
+#define IFX_CIF_JPE_DC_TABLE_SELECT_DC_TABLE_SELECT_LEN (3u)
+
+/** \brief Mask for Ifx_CIF_JPE_DC_TABLE_SELECT_Bits.DC_TABLE_SELECT */
+#define IFX_CIF_JPE_DC_TABLE_SELECT_DC_TABLE_SELECT_MSK (0x7u)
+
+/** \brief Offset for Ifx_CIF_JPE_DC_TABLE_SELECT_Bits.DC_TABLE_SELECT */
+#define IFX_CIF_JPE_DC_TABLE_SELECT_DC_TABLE_SELECT_OFF (0u)
+
+/** \brief Length for Ifx_CIF_JPE_DEBUG_Bits.DEB_BAD_TABLE_ACCESS */
+#define IFX_CIF_JPE_DEBUG_DEB_BAD_TABLE_ACCESS_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_DEBUG_Bits.DEB_BAD_TABLE_ACCESS */
+#define IFX_CIF_JPE_DEBUG_DEB_BAD_TABLE_ACCESS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_DEBUG_Bits.DEB_BAD_TABLE_ACCESS */
+#define IFX_CIF_JPE_DEBUG_DEB_BAD_TABLE_ACCESS_OFF (8u)
+
+/** \brief Length for Ifx_CIF_JPE_DEBUG_Bits.DEB_QIQ_TABLE_ACC */
+#define IFX_CIF_JPE_DEBUG_DEB_QIQ_TABLE_ACC_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_DEBUG_Bits.DEB_QIQ_TABLE_ACC */
+#define IFX_CIF_JPE_DEBUG_DEB_QIQ_TABLE_ACC_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_DEBUG_Bits.DEB_QIQ_TABLE_ACC */
+#define IFX_CIF_JPE_DEBUG_DEB_QIQ_TABLE_ACC_OFF (2u)
+
+/** \brief Length for Ifx_CIF_JPE_DEBUG_Bits.DEB_R2B_MEMORY_FULL */
+#define IFX_CIF_JPE_DEBUG_DEB_R2B_MEMORY_FULL_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_DEBUG_Bits.DEB_R2B_MEMORY_FULL */
+#define IFX_CIF_JPE_DEBUG_DEB_R2B_MEMORY_FULL_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_DEBUG_Bits.DEB_R2B_MEMORY_FULL */
+#define IFX_CIF_JPE_DEBUG_DEB_R2B_MEMORY_FULL_OFF (4u)
+
+/** \brief Length for Ifx_CIF_JPE_DEBUG_Bits.DEB_VLC_ENCODE_BUSY */
+#define IFX_CIF_JPE_DEBUG_DEB_VLC_ENCODE_BUSY_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_DEBUG_Bits.DEB_VLC_ENCODE_BUSY */
+#define IFX_CIF_JPE_DEBUG_DEB_VLC_ENCODE_BUSY_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_DEBUG_Bits.DEB_VLC_ENCODE_BUSY */
+#define IFX_CIF_JPE_DEBUG_DEB_VLC_ENCODE_BUSY_OFF (3u)
+
+/** \brief Length for Ifx_CIF_JPE_DEBUG_Bits.DEB_VLC_TABLE_BUSY */
+#define IFX_CIF_JPE_DEBUG_DEB_VLC_TABLE_BUSY_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_DEBUG_Bits.DEB_VLC_TABLE_BUSY */
+#define IFX_CIF_JPE_DEBUG_DEB_VLC_TABLE_BUSY_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_DEBUG_Bits.DEB_VLC_TABLE_BUSY */
+#define IFX_CIF_JPE_DEBUG_DEB_VLC_TABLE_BUSY_OFF (5u)
+
+/** \brief Length for Ifx_CIF_JPE_ENC_HSIZE_Bits.ENC_HSIZE */
+#define IFX_CIF_JPE_ENC_HSIZE_ENC_HSIZE_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_JPE_ENC_HSIZE_Bits.ENC_HSIZE */
+#define IFX_CIF_JPE_ENC_HSIZE_ENC_HSIZE_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_JPE_ENC_HSIZE_Bits.ENC_HSIZE */
+#define IFX_CIF_JPE_ENC_HSIZE_ENC_HSIZE_OFF (0u)
+
+/** \brief Length for Ifx_CIF_JPE_ENC_VSIZE_Bits.ENC_VSIZE */
+#define IFX_CIF_JPE_ENC_VSIZE_ENC_VSIZE_LEN (12u)
+
+/** \brief Mask for Ifx_CIF_JPE_ENC_VSIZE_Bits.ENC_VSIZE */
+#define IFX_CIF_JPE_ENC_VSIZE_ENC_VSIZE_MSK (0xfffu)
+
+/** \brief Offset for Ifx_CIF_JPE_ENC_VSIZE_Bits.ENC_VSIZE */
+#define IFX_CIF_JPE_ENC_VSIZE_ENC_VSIZE_OFF (0u)
+
+/** \brief Length for Ifx_CIF_JPE_ENCODE_Bits.CONT_MODE */
+#define IFX_CIF_JPE_ENCODE_CONT_MODE_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_JPE_ENCODE_Bits.CONT_MODE */
+#define IFX_CIF_JPE_ENCODE_CONT_MODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_JPE_ENCODE_Bits.CONT_MODE */
+#define IFX_CIF_JPE_ENCODE_CONT_MODE_OFF (4u)
+
+/** \brief Length for Ifx_CIF_JPE_ENCODE_Bits.ENCODE */
+#define IFX_CIF_JPE_ENCODE_ENCODE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_ENCODE_Bits.ENCODE */
+#define IFX_CIF_JPE_ENCODE_ENCODE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_ENCODE_Bits.ENCODE */
+#define IFX_CIF_JPE_ENCODE_ENCODE_OFF (0u)
+
+/** \brief Length for Ifx_CIF_JPE_ENCODE_MODE_Bits.ENCODE_MODE */
+#define IFX_CIF_JPE_ENCODE_MODE_ENCODE_MODE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_ENCODE_MODE_Bits.ENCODE_MODE */
+#define IFX_CIF_JPE_ENCODE_MODE_ENCODE_MODE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_ENCODE_MODE_Bits.ENCODE_MODE */
+#define IFX_CIF_JPE_ENCODE_MODE_ENCODE_MODE_OFF (0u)
+
+/** \brief Length for Ifx_CIF_JPE_ENCODER_BUSY_Bits.CODEC_BUSY */
+#define IFX_CIF_JPE_ENCODER_BUSY_CODEC_BUSY_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_ENCODER_BUSY_Bits.CODEC_BUSY */
+#define IFX_CIF_JPE_ENCODER_BUSY_CODEC_BUSY_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_ENCODER_BUSY_Bits.CODEC_BUSY */
+#define IFX_CIF_JPE_ENCODER_BUSY_CODEC_BUSY_OFF (0u)
+
+/** \brief Length for Ifx_CIF_JPE_ERROR_ICR_Bits.DCT_ERR */
+#define IFX_CIF_JPE_ERROR_ICR_DCT_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_ERROR_ICR_Bits.DCT_ERR */
+#define IFX_CIF_JPE_ERROR_ICR_DCT_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_ERROR_ICR_Bits.DCT_ERR */
+#define IFX_CIF_JPE_ERROR_ICR_DCT_ERR_OFF (7u)
+
+/** \brief Length for Ifx_CIF_JPE_ERROR_ICR_Bits.R2B_IMG_SIZE_ERR */
+#define IFX_CIF_JPE_ERROR_ICR_R2B_IMG_SIZE_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_ERROR_ICR_Bits.R2B_IMG_SIZE_ERR */
+#define IFX_CIF_JPE_ERROR_ICR_R2B_IMG_SIZE_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_ERROR_ICR_Bits.R2B_IMG_SIZE_ERR */
+#define IFX_CIF_JPE_ERROR_ICR_R2B_IMG_SIZE_ERR_OFF (9u)
+
+/** \brief Length for Ifx_CIF_JPE_ERROR_ICR_Bits.VLC_SYMBOL_ERR */
+#define IFX_CIF_JPE_ERROR_ICR_VLC_SYMBOL_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_ERROR_ICR_Bits.VLC_SYMBOL_ERR */
+#define IFX_CIF_JPE_ERROR_ICR_VLC_SYMBOL_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_ERROR_ICR_Bits.VLC_SYMBOL_ERR */
+#define IFX_CIF_JPE_ERROR_ICR_VLC_SYMBOL_ERR_OFF (4u)
+
+/** \brief Length for Ifx_CIF_JPE_ERROR_ICR_Bits.VLC_TABLE_ERR */
+#define IFX_CIF_JPE_ERROR_ICR_VLC_TABLE_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_ERROR_ICR_Bits.VLC_TABLE_ERR */
+#define IFX_CIF_JPE_ERROR_ICR_VLC_TABLE_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_ERROR_ICR_Bits.VLC_TABLE_ERR */
+#define IFX_CIF_JPE_ERROR_ICR_VLC_TABLE_ERR_OFF (10u)
+
+/** \brief Length for Ifx_CIF_JPE_ERROR_IMR_Bits.DCT_ERR */
+#define IFX_CIF_JPE_ERROR_IMR_DCT_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_ERROR_IMR_Bits.DCT_ERR */
+#define IFX_CIF_JPE_ERROR_IMR_DCT_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_ERROR_IMR_Bits.DCT_ERR */
+#define IFX_CIF_JPE_ERROR_IMR_DCT_ERR_OFF (7u)
+
+/** \brief Length for Ifx_CIF_JPE_ERROR_IMR_Bits.R2B_IMG_SIZE_ERR */
+#define IFX_CIF_JPE_ERROR_IMR_R2B_IMG_SIZE_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_ERROR_IMR_Bits.R2B_IMG_SIZE_ERR */
+#define IFX_CIF_JPE_ERROR_IMR_R2B_IMG_SIZE_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_ERROR_IMR_Bits.R2B_IMG_SIZE_ERR */
+#define IFX_CIF_JPE_ERROR_IMR_R2B_IMG_SIZE_ERR_OFF (9u)
+
+/** \brief Length for Ifx_CIF_JPE_ERROR_IMR_Bits.VLC_SYMBOL_ERR */
+#define IFX_CIF_JPE_ERROR_IMR_VLC_SYMBOL_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_ERROR_IMR_Bits.VLC_SYMBOL_ERR */
+#define IFX_CIF_JPE_ERROR_IMR_VLC_SYMBOL_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_ERROR_IMR_Bits.VLC_SYMBOL_ERR */
+#define IFX_CIF_JPE_ERROR_IMR_VLC_SYMBOL_ERR_OFF (4u)
+
+/** \brief Length for Ifx_CIF_JPE_ERROR_IMR_Bits.VLC_TABLE_ERR */
+#define IFX_CIF_JPE_ERROR_IMR_VLC_TABLE_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_ERROR_IMR_Bits.VLC_TABLE_ERR */
+#define IFX_CIF_JPE_ERROR_IMR_VLC_TABLE_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_ERROR_IMR_Bits.VLC_TABLE_ERR */
+#define IFX_CIF_JPE_ERROR_IMR_VLC_TABLE_ERR_OFF (10u)
+
+/** \brief Length for Ifx_CIF_JPE_ERROR_ISR_Bits.DCT_ERR */
+#define IFX_CIF_JPE_ERROR_ISR_DCT_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_ERROR_ISR_Bits.DCT_ERR */
+#define IFX_CIF_JPE_ERROR_ISR_DCT_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_ERROR_ISR_Bits.DCT_ERR */
+#define IFX_CIF_JPE_ERROR_ISR_DCT_ERR_OFF (7u)
+
+/** \brief Length for Ifx_CIF_JPE_ERROR_ISR_Bits.R2B_IMG_SIZE_ERR */
+#define IFX_CIF_JPE_ERROR_ISR_R2B_IMG_SIZE_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_ERROR_ISR_Bits.R2B_IMG_SIZE_ERR */
+#define IFX_CIF_JPE_ERROR_ISR_R2B_IMG_SIZE_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_ERROR_ISR_Bits.R2B_IMG_SIZE_ERR */
+#define IFX_CIF_JPE_ERROR_ISR_R2B_IMG_SIZE_ERR_OFF (9u)
+
+/** \brief Length for Ifx_CIF_JPE_ERROR_ISR_Bits.VLC_SYMBOL_ERR */
+#define IFX_CIF_JPE_ERROR_ISR_VLC_SYMBOL_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_ERROR_ISR_Bits.VLC_SYMBOL_ERR */
+#define IFX_CIF_JPE_ERROR_ISR_VLC_SYMBOL_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_ERROR_ISR_Bits.VLC_SYMBOL_ERR */
+#define IFX_CIF_JPE_ERROR_ISR_VLC_SYMBOL_ERR_OFF (4u)
+
+/** \brief Length for Ifx_CIF_JPE_ERROR_ISR_Bits.VLC_TABLE_ERR */
+#define IFX_CIF_JPE_ERROR_ISR_VLC_TABLE_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_ERROR_ISR_Bits.VLC_TABLE_ERR */
+#define IFX_CIF_JPE_ERROR_ISR_VLC_TABLE_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_ERROR_ISR_Bits.VLC_TABLE_ERR */
+#define IFX_CIF_JPE_ERROR_ISR_VLC_TABLE_ERR_OFF (10u)
+
+/** \brief Length for Ifx_CIF_JPE_ERROR_MIS_Bits.DCT_ERR */
+#define IFX_CIF_JPE_ERROR_MIS_DCT_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_ERROR_MIS_Bits.DCT_ERR */
+#define IFX_CIF_JPE_ERROR_MIS_DCT_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_ERROR_MIS_Bits.DCT_ERR */
+#define IFX_CIF_JPE_ERROR_MIS_DCT_ERR_OFF (7u)
+
+/** \brief Length for Ifx_CIF_JPE_ERROR_MIS_Bits.R2B_IMG_SIZE_ERR */
+#define IFX_CIF_JPE_ERROR_MIS_R2B_IMG_SIZE_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_ERROR_MIS_Bits.R2B_IMG_SIZE_ERR */
+#define IFX_CIF_JPE_ERROR_MIS_R2B_IMG_SIZE_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_ERROR_MIS_Bits.R2B_IMG_SIZE_ERR */
+#define IFX_CIF_JPE_ERROR_MIS_R2B_IMG_SIZE_ERR_OFF (9u)
+
+/** \brief Length for Ifx_CIF_JPE_ERROR_MIS_Bits.VLC_SYMBOL_ERR */
+#define IFX_CIF_JPE_ERROR_MIS_VLC_SYMBOL_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_ERROR_MIS_Bits.VLC_SYMBOL_ERR */
+#define IFX_CIF_JPE_ERROR_MIS_VLC_SYMBOL_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_ERROR_MIS_Bits.VLC_SYMBOL_ERR */
+#define IFX_CIF_JPE_ERROR_MIS_VLC_SYMBOL_ERR_OFF (4u)
+
+/** \brief Length for Ifx_CIF_JPE_ERROR_MIS_Bits.VLC_TABLE_ERR */
+#define IFX_CIF_JPE_ERROR_MIS_VLC_TABLE_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_ERROR_MIS_Bits.VLC_TABLE_ERR */
+#define IFX_CIF_JPE_ERROR_MIS_VLC_TABLE_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_ERROR_MIS_Bits.VLC_TABLE_ERR */
+#define IFX_CIF_JPE_ERROR_MIS_VLC_TABLE_ERR_OFF (10u)
+
+/** \brief Length for Ifx_CIF_JPE_ERROR_RIS_Bits.DCT_ERR */
+#define IFX_CIF_JPE_ERROR_RIS_DCT_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_ERROR_RIS_Bits.DCT_ERR */
+#define IFX_CIF_JPE_ERROR_RIS_DCT_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_ERROR_RIS_Bits.DCT_ERR */
+#define IFX_CIF_JPE_ERROR_RIS_DCT_ERR_OFF (7u)
+
+/** \brief Length for Ifx_CIF_JPE_ERROR_RIS_Bits.R2B_IMG_SIZE_ERR */
+#define IFX_CIF_JPE_ERROR_RIS_R2B_IMG_SIZE_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_ERROR_RIS_Bits.R2B_IMG_SIZE_ERR */
+#define IFX_CIF_JPE_ERROR_RIS_R2B_IMG_SIZE_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_ERROR_RIS_Bits.R2B_IMG_SIZE_ERR */
+#define IFX_CIF_JPE_ERROR_RIS_R2B_IMG_SIZE_ERR_OFF (9u)
+
+/** \brief Length for Ifx_CIF_JPE_ERROR_RIS_Bits.VLC_SYMBOL_ERR */
+#define IFX_CIF_JPE_ERROR_RIS_VLC_SYMBOL_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_ERROR_RIS_Bits.VLC_SYMBOL_ERR */
+#define IFX_CIF_JPE_ERROR_RIS_VLC_SYMBOL_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_ERROR_RIS_Bits.VLC_SYMBOL_ERR */
+#define IFX_CIF_JPE_ERROR_RIS_VLC_SYMBOL_ERR_OFF (4u)
+
+/** \brief Length for Ifx_CIF_JPE_ERROR_RIS_Bits.VLC_TABLE_ERR */
+#define IFX_CIF_JPE_ERROR_RIS_VLC_TABLE_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_ERROR_RIS_Bits.VLC_TABLE_ERR */
+#define IFX_CIF_JPE_ERROR_RIS_VLC_TABLE_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_ERROR_RIS_Bits.VLC_TABLE_ERR */
+#define IFX_CIF_JPE_ERROR_RIS_VLC_TABLE_ERR_OFF (10u)
+
+/** \brief Length for Ifx_CIF_JPE_GEN_HEADER_Bits.GEN_HEADER */
+#define IFX_CIF_JPE_GEN_HEADER_GEN_HEADER_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_GEN_HEADER_Bits.GEN_HEADER */
+#define IFX_CIF_JPE_GEN_HEADER_GEN_HEADER_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_GEN_HEADER_Bits.GEN_HEADER */
+#define IFX_CIF_JPE_GEN_HEADER_GEN_HEADER_OFF (0u)
+
+/** \brief Length for Ifx_CIF_JPE_HEADER_MODE_Bits.HEADER_MODE */
+#define IFX_CIF_JPE_HEADER_MODE_HEADER_MODE_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_JPE_HEADER_MODE_Bits.HEADER_MODE */
+#define IFX_CIF_JPE_HEADER_MODE_HEADER_MODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_JPE_HEADER_MODE_Bits.HEADER_MODE */
+#define IFX_CIF_JPE_HEADER_MODE_HEADER_MODE_OFF (0u)
+
+/** \brief Length for Ifx_CIF_JPE_INIT_Bits.JP_INIT */
+#define IFX_CIF_JPE_INIT_JP_INIT_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_INIT_Bits.JP_INIT */
+#define IFX_CIF_JPE_INIT_JP_INIT_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_INIT_Bits.JP_INIT */
+#define IFX_CIF_JPE_INIT_JP_INIT_OFF (0u)
+
+/** \brief Length for Ifx_CIF_JPE_PIC_FORMAT_Bits.ENC_PIC_FORMAT */
+#define IFX_CIF_JPE_PIC_FORMAT_ENC_PIC_FORMAT_LEN (3u)
+
+/** \brief Mask for Ifx_CIF_JPE_PIC_FORMAT_Bits.ENC_PIC_FORMAT */
+#define IFX_CIF_JPE_PIC_FORMAT_ENC_PIC_FORMAT_MSK (0x7u)
+
+/** \brief Offset for Ifx_CIF_JPE_PIC_FORMAT_Bits.ENC_PIC_FORMAT */
+#define IFX_CIF_JPE_PIC_FORMAT_ENC_PIC_FORMAT_OFF (0u)
+
+/** \brief Length for Ifx_CIF_JPE_RESTART_INTERVAL_Bits.RESTART_INTERVAL */
+#define IFX_CIF_JPE_RESTART_INTERVAL_RESTART_INTERVAL_LEN (16u)
+
+/** \brief Mask for Ifx_CIF_JPE_RESTART_INTERVAL_Bits.RESTART_INTERVAL */
+#define IFX_CIF_JPE_RESTART_INTERVAL_RESTART_INTERVAL_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CIF_JPE_RESTART_INTERVAL_Bits.RESTART_INTERVAL */
+#define IFX_CIF_JPE_RESTART_INTERVAL_RESTART_INTERVAL_OFF (0u)
+
+/** \brief Length for Ifx_CIF_JPE_STATUS_ICR_Bits.ENCODE_DONE */
+#define IFX_CIF_JPE_STATUS_ICR_ENCODE_DONE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_STATUS_ICR_Bits.ENCODE_DONE */
+#define IFX_CIF_JPE_STATUS_ICR_ENCODE_DONE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_STATUS_ICR_Bits.ENCODE_DONE */
+#define IFX_CIF_JPE_STATUS_ICR_ENCODE_DONE_OFF (4u)
+
+/** \brief Length for Ifx_CIF_JPE_STATUS_ICR_Bits.GEN_HEADER_DONE */
+#define IFX_CIF_JPE_STATUS_ICR_GEN_HEADER_DONE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_STATUS_ICR_Bits.GEN_HEADER_DONE */
+#define IFX_CIF_JPE_STATUS_ICR_GEN_HEADER_DONE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_STATUS_ICR_Bits.GEN_HEADER_DONE */
+#define IFX_CIF_JPE_STATUS_ICR_GEN_HEADER_DONE_OFF (5u)
+
+/** \brief Length for Ifx_CIF_JPE_STATUS_IMR_Bits.ENCODE_DONE */
+#define IFX_CIF_JPE_STATUS_IMR_ENCODE_DONE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_STATUS_IMR_Bits.ENCODE_DONE */
+#define IFX_CIF_JPE_STATUS_IMR_ENCODE_DONE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_STATUS_IMR_Bits.ENCODE_DONE */
+#define IFX_CIF_JPE_STATUS_IMR_ENCODE_DONE_OFF (4u)
+
+/** \brief Length for Ifx_CIF_JPE_STATUS_IMR_Bits.GEN_HEADER_DONE */
+#define IFX_CIF_JPE_STATUS_IMR_GEN_HEADER_DONE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_STATUS_IMR_Bits.GEN_HEADER_DONE */
+#define IFX_CIF_JPE_STATUS_IMR_GEN_HEADER_DONE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_STATUS_IMR_Bits.GEN_HEADER_DONE */
+#define IFX_CIF_JPE_STATUS_IMR_GEN_HEADER_DONE_OFF (5u)
+
+/** \brief Length for Ifx_CIF_JPE_STATUS_ISR_Bits.ENCODE_DONE */
+#define IFX_CIF_JPE_STATUS_ISR_ENCODE_DONE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_STATUS_ISR_Bits.ENCODE_DONE */
+#define IFX_CIF_JPE_STATUS_ISR_ENCODE_DONE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_STATUS_ISR_Bits.ENCODE_DONE */
+#define IFX_CIF_JPE_STATUS_ISR_ENCODE_DONE_OFF (4u)
+
+/** \brief Length for Ifx_CIF_JPE_STATUS_ISR_Bits.GEN_HEADER_DONE */
+#define IFX_CIF_JPE_STATUS_ISR_GEN_HEADER_DONE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_STATUS_ISR_Bits.GEN_HEADER_DONE */
+#define IFX_CIF_JPE_STATUS_ISR_GEN_HEADER_DONE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_STATUS_ISR_Bits.GEN_HEADER_DONE */
+#define IFX_CIF_JPE_STATUS_ISR_GEN_HEADER_DONE_OFF (5u)
+
+/** \brief Length for Ifx_CIF_JPE_STATUS_MIS_Bits.ENCODE_DONE */
+#define IFX_CIF_JPE_STATUS_MIS_ENCODE_DONE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_STATUS_MIS_Bits.ENCODE_DONE */
+#define IFX_CIF_JPE_STATUS_MIS_ENCODE_DONE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_STATUS_MIS_Bits.ENCODE_DONE */
+#define IFX_CIF_JPE_STATUS_MIS_ENCODE_DONE_OFF (4u)
+
+/** \brief Length for Ifx_CIF_JPE_STATUS_MIS_Bits.GEN_HEADER_DONE */
+#define IFX_CIF_JPE_STATUS_MIS_GEN_HEADER_DONE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_STATUS_MIS_Bits.GEN_HEADER_DONE */
+#define IFX_CIF_JPE_STATUS_MIS_GEN_HEADER_DONE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_STATUS_MIS_Bits.GEN_HEADER_DONE */
+#define IFX_CIF_JPE_STATUS_MIS_GEN_HEADER_DONE_OFF (5u)
+
+/** \brief Length for Ifx_CIF_JPE_STATUS_RIS_Bits.ENCODE_DONE */
+#define IFX_CIF_JPE_STATUS_RIS_ENCODE_DONE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_STATUS_RIS_Bits.ENCODE_DONE */
+#define IFX_CIF_JPE_STATUS_RIS_ENCODE_DONE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_STATUS_RIS_Bits.ENCODE_DONE */
+#define IFX_CIF_JPE_STATUS_RIS_ENCODE_DONE_OFF (4u)
+
+/** \brief Length for Ifx_CIF_JPE_STATUS_RIS_Bits.GEN_HEADER_DONE */
+#define IFX_CIF_JPE_STATUS_RIS_GEN_HEADER_DONE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_STATUS_RIS_Bits.GEN_HEADER_DONE */
+#define IFX_CIF_JPE_STATUS_RIS_GEN_HEADER_DONE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_STATUS_RIS_Bits.GEN_HEADER_DONE */
+#define IFX_CIF_JPE_STATUS_RIS_GEN_HEADER_DONE_OFF (5u)
+
+/** \brief Length for Ifx_CIF_JPE_TABLE_DATA_Bits.TABLE_WDATA_H */
+#define IFX_CIF_JPE_TABLE_DATA_TABLE_WDATA_H_LEN (8u)
+
+/** \brief Mask for Ifx_CIF_JPE_TABLE_DATA_Bits.TABLE_WDATA_H */
+#define IFX_CIF_JPE_TABLE_DATA_TABLE_WDATA_H_MSK (0xffu)
+
+/** \brief Offset for Ifx_CIF_JPE_TABLE_DATA_Bits.TABLE_WDATA_H */
+#define IFX_CIF_JPE_TABLE_DATA_TABLE_WDATA_H_OFF (8u)
+
+/** \brief Length for Ifx_CIF_JPE_TABLE_DATA_Bits.TABLE_WDATA_L */
+#define IFX_CIF_JPE_TABLE_DATA_TABLE_WDATA_L_LEN (8u)
+
+/** \brief Mask for Ifx_CIF_JPE_TABLE_DATA_Bits.TABLE_WDATA_L */
+#define IFX_CIF_JPE_TABLE_DATA_TABLE_WDATA_L_MSK (0xffu)
+
+/** \brief Offset for Ifx_CIF_JPE_TABLE_DATA_Bits.TABLE_WDATA_L */
+#define IFX_CIF_JPE_TABLE_DATA_TABLE_WDATA_L_OFF (0u)
+
+/** \brief Length for Ifx_CIF_JPE_TABLE_FLUSH_Bits.TABLE_FLUSH */
+#define IFX_CIF_JPE_TABLE_FLUSH_TABLE_FLUSH_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_TABLE_FLUSH_Bits.TABLE_FLUSH */
+#define IFX_CIF_JPE_TABLE_FLUSH_TABLE_FLUSH_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_TABLE_FLUSH_Bits.TABLE_FLUSH */
+#define IFX_CIF_JPE_TABLE_FLUSH_TABLE_FLUSH_OFF (0u)
+
+/** \brief Length for Ifx_CIF_JPE_TABLE_ID_Bits.TABLE_ID */
+#define IFX_CIF_JPE_TABLE_ID_TABLE_ID_LEN (4u)
+
+/** \brief Mask for Ifx_CIF_JPE_TABLE_ID_Bits.TABLE_ID */
+#define IFX_CIF_JPE_TABLE_ID_TABLE_ID_MSK (0xfu)
+
+/** \brief Offset for Ifx_CIF_JPE_TABLE_ID_Bits.TABLE_ID */
+#define IFX_CIF_JPE_TABLE_ID_TABLE_ID_OFF (0u)
+
+/** \brief Length for Ifx_CIF_JPE_TAC0_LEN_Bits.TAC0_LEN */
+#define IFX_CIF_JPE_TAC0_LEN_TAC0_LEN_LEN (8u)
+
+/** \brief Mask for Ifx_CIF_JPE_TAC0_LEN_Bits.TAC0_LEN */
+#define IFX_CIF_JPE_TAC0_LEN_TAC0_LEN_MSK (0xffu)
+
+/** \brief Offset for Ifx_CIF_JPE_TAC0_LEN_Bits.TAC0_LEN */
+#define IFX_CIF_JPE_TAC0_LEN_TAC0_LEN_OFF (0u)
+
+/** \brief Length for Ifx_CIF_JPE_TAC1_LEN_Bits.TAC1_LEN */
+#define IFX_CIF_JPE_TAC1_LEN_TAC1_LEN_LEN (8u)
+
+/** \brief Mask for Ifx_CIF_JPE_TAC1_LEN_Bits.TAC1_LEN */
+#define IFX_CIF_JPE_TAC1_LEN_TAC1_LEN_MSK (0xffu)
+
+/** \brief Offset for Ifx_CIF_JPE_TAC1_LEN_Bits.TAC1_LEN */
+#define IFX_CIF_JPE_TAC1_LEN_TAC1_LEN_OFF (0u)
+
+/** \brief Length for Ifx_CIF_JPE_TDC0_LEN_Bits.TDC0_LEN */
+#define IFX_CIF_JPE_TDC0_LEN_TDC0_LEN_LEN (8u)
+
+/** \brief Mask for Ifx_CIF_JPE_TDC0_LEN_Bits.TDC0_LEN */
+#define IFX_CIF_JPE_TDC0_LEN_TDC0_LEN_MSK (0xffu)
+
+/** \brief Offset for Ifx_CIF_JPE_TDC0_LEN_Bits.TDC0_LEN */
+#define IFX_CIF_JPE_TDC0_LEN_TDC0_LEN_OFF (0u)
+
+/** \brief Length for Ifx_CIF_JPE_TDC1_LEN_Bits.TDC1_LEN */
+#define IFX_CIF_JPE_TDC1_LEN_TDC1_LEN_LEN (8u)
+
+/** \brief Mask for Ifx_CIF_JPE_TDC1_LEN_Bits.TDC1_LEN */
+#define IFX_CIF_JPE_TDC1_LEN_TDC1_LEN_MSK (0xffu)
+
+/** \brief Offset for Ifx_CIF_JPE_TDC1_LEN_Bits.TDC1_LEN */
+#define IFX_CIF_JPE_TDC1_LEN_TDC1_LEN_OFF (0u)
+
+/** \brief Length for Ifx_CIF_JPE_TQ_U_SELECT_Bits.TQ1_SELECT */
+#define IFX_CIF_JPE_TQ_U_SELECT_TQ1_SELECT_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_JPE_TQ_U_SELECT_Bits.TQ1_SELECT */
+#define IFX_CIF_JPE_TQ_U_SELECT_TQ1_SELECT_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_JPE_TQ_U_SELECT_Bits.TQ1_SELECT */
+#define IFX_CIF_JPE_TQ_U_SELECT_TQ1_SELECT_OFF (0u)
+
+/** \brief Length for Ifx_CIF_JPE_TQ_V_SELECT_Bits.TQ2_SELECT */
+#define IFX_CIF_JPE_TQ_V_SELECT_TQ2_SELECT_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_JPE_TQ_V_SELECT_Bits.TQ2_SELECT */
+#define IFX_CIF_JPE_TQ_V_SELECT_TQ2_SELECT_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_JPE_TQ_V_SELECT_Bits.TQ2_SELECT */
+#define IFX_CIF_JPE_TQ_V_SELECT_TQ2_SELECT_OFF (0u)
+
+/** \brief Length for Ifx_CIF_JPE_TQ_Y_SELECT_Bits.TQ0_SELECT */
+#define IFX_CIF_JPE_TQ_Y_SELECT_TQ0_SELECT_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_JPE_TQ_Y_SELECT_Bits.TQ0_SELECT */
+#define IFX_CIF_JPE_TQ_Y_SELECT_TQ0_SELECT_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_JPE_TQ_Y_SELECT_Bits.TQ0_SELECT */
+#define IFX_CIF_JPE_TQ_Y_SELECT_TQ0_SELECT_OFF (0u)
+
+/** \brief Length for Ifx_CIF_JPE_Y_SCALE_EN_Bits.Y_SCALE_EN */
+#define IFX_CIF_JPE_Y_SCALE_EN_Y_SCALE_EN_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_JPE_Y_SCALE_EN_Bits.Y_SCALE_EN */
+#define IFX_CIF_JPE_Y_SCALE_EN_Y_SCALE_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_JPE_Y_SCALE_EN_Bits.Y_SCALE_EN */
+#define IFX_CIF_JPE_Y_SCALE_EN_Y_SCALE_EN_OFF (0u)
+
+/** \brief Length for Ifx_CIF_LDS_CTRL_Bits.LDS_H_EN */
+#define IFX_CIF_LDS_CTRL_LDS_H_EN_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_LDS_CTRL_Bits.LDS_H_EN */
+#define IFX_CIF_LDS_CTRL_LDS_H_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_LDS_CTRL_Bits.LDS_H_EN */
+#define IFX_CIF_LDS_CTRL_LDS_H_EN_OFF (1u)
+
+/** \brief Length for Ifx_CIF_LDS_CTRL_Bits.LDS_H_MODE */
+#define IFX_CIF_LDS_CTRL_LDS_H_MODE_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_LDS_CTRL_Bits.LDS_H_MODE */
+#define IFX_CIF_LDS_CTRL_LDS_H_MODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_LDS_CTRL_Bits.LDS_H_MODE */
+#define IFX_CIF_LDS_CTRL_LDS_H_MODE_OFF (8u)
+
+/** \brief Length for Ifx_CIF_LDS_CTRL_Bits.LDS_V_EN */
+#define IFX_CIF_LDS_CTRL_LDS_V_EN_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_LDS_CTRL_Bits.LDS_V_EN */
+#define IFX_CIF_LDS_CTRL_LDS_V_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_LDS_CTRL_Bits.LDS_V_EN */
+#define IFX_CIF_LDS_CTRL_LDS_V_EN_OFF (0u)
+
+/** \brief Length for Ifx_CIF_LDS_CTRL_Bits.LDS_V_MODE */
+#define IFX_CIF_LDS_CTRL_LDS_V_MODE_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_LDS_CTRL_Bits.LDS_V_MODE */
+#define IFX_CIF_LDS_CTRL_LDS_V_MODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_LDS_CTRL_Bits.LDS_V_MODE */
+#define IFX_CIF_LDS_CTRL_LDS_V_MODE_OFF (4u)
+
+/** \brief Length for Ifx_CIF_LDS_FAC_Bits.LDS_H_FAC */
+#define IFX_CIF_LDS_FAC_LDS_H_FAC_LEN (8u)
+
+/** \brief Mask for Ifx_CIF_LDS_FAC_Bits.LDS_H_FAC */
+#define IFX_CIF_LDS_FAC_LDS_H_FAC_MSK (0xffu)
+
+/** \brief Offset for Ifx_CIF_LDS_FAC_Bits.LDS_H_FAC */
+#define IFX_CIF_LDS_FAC_LDS_H_FAC_OFF (16u)
+
+/** \brief Length for Ifx_CIF_LDS_FAC_Bits.LDS_V_FAC */
+#define IFX_CIF_LDS_FAC_LDS_V_FAC_LEN (8u)
+
+/** \brief Mask for Ifx_CIF_LDS_FAC_Bits.LDS_V_FAC */
+#define IFX_CIF_LDS_FAC_LDS_V_FAC_MSK (0xffu)
+
+/** \brief Offset for Ifx_CIF_LDS_FAC_Bits.LDS_V_FAC */
+#define IFX_CIF_LDS_FAC_LDS_V_FAC_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_BYTE_CNT_Bits.BYTE_CNT */
+#define IFX_CIF_MI_BYTE_CNT_BYTE_CNT_LEN (24u)
+
+/** \brief Mask for Ifx_CIF_MI_BYTE_CNT_Bits.BYTE_CNT */
+#define IFX_CIF_MI_BYTE_CNT_BYTE_CNT_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_CIF_MI_BYTE_CNT_Bits.BYTE_CNT */
+#define IFX_CIF_MI_BYTE_CNT_BYTE_CNT_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_CTRL_Bits.BURST_LEN_CHROM */
+#define IFX_CIF_MI_CTRL_BURST_LEN_CHROM_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_CTRL_Bits.BURST_LEN_CHROM */
+#define IFX_CIF_MI_CTRL_BURST_LEN_CHROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_CTRL_Bits.BURST_LEN_CHROM */
+#define IFX_CIF_MI_CTRL_BURST_LEN_CHROM_OFF (18u)
+
+/** \brief Length for Ifx_CIF_MI_CTRL_Bits.BURST_LEN_LUM */
+#define IFX_CIF_MI_CTRL_BURST_LEN_LUM_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_CTRL_Bits.BURST_LEN_LUM */
+#define IFX_CIF_MI_CTRL_BURST_LEN_LUM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_CTRL_Bits.BURST_LEN_LUM */
+#define IFX_CIF_MI_CTRL_BURST_LEN_LUM_OFF (16u)
+
+/** \brief Length for Ifx_CIF_MI_CTRL_Bits.BYTE_SWAP */
+#define IFX_CIF_MI_CTRL_BYTE_SWAP_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_CTRL_Bits.BYTE_SWAP */
+#define IFX_CIF_MI_CTRL_BYTE_SWAP_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_CTRL_Bits.BYTE_SWAP */
+#define IFX_CIF_MI_CTRL_BYTE_SWAP_OFF (7u)
+
+/** \brief Length for Ifx_CIF_MI_CTRL_Bits.INIT_BASE_EN */
+#define IFX_CIF_MI_CTRL_INIT_BASE_EN_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_CTRL_Bits.INIT_BASE_EN */
+#define IFX_CIF_MI_CTRL_INIT_BASE_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_CTRL_Bits.INIT_BASE_EN */
+#define IFX_CIF_MI_CTRL_INIT_BASE_EN_OFF (20u)
+
+/** \brief Length for Ifx_CIF_MI_CTRL_Bits.INIT_OFFSET_EN */
+#define IFX_CIF_MI_CTRL_INIT_OFFSET_EN_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_CTRL_Bits.INIT_OFFSET_EN */
+#define IFX_CIF_MI_CTRL_INIT_OFFSET_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_CTRL_Bits.INIT_OFFSET_EN */
+#define IFX_CIF_MI_CTRL_INIT_OFFSET_EN_OFF (21u)
+
+/** \brief Length for Ifx_CIF_MI_CTRL_Bits.JPEG_ENABLE */
+#define IFX_CIF_MI_CTRL_JPEG_ENABLE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_CTRL_Bits.JPEG_ENABLE */
+#define IFX_CIF_MI_CTRL_JPEG_ENABLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_CTRL_Bits.JPEG_ENABLE */
+#define IFX_CIF_MI_CTRL_JPEG_ENABLE_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_CTRL_Bits.MP_ENABLE */
+#define IFX_CIF_MI_CTRL_MP_ENABLE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_CTRL_Bits.MP_ENABLE */
+#define IFX_CIF_MI_CTRL_MP_ENABLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_CTRL_Bits.MP_ENABLE */
+#define IFX_CIF_MI_CTRL_MP_ENABLE_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_CTRL_Bits.MP_WRITE_FORMAT */
+#define IFX_CIF_MI_CTRL_MP_WRITE_FORMAT_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MI_CTRL_Bits.MP_WRITE_FORMAT */
+#define IFX_CIF_MI_CTRL_MP_WRITE_FORMAT_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MI_CTRL_Bits.MP_WRITE_FORMAT */
+#define IFX_CIF_MI_CTRL_MP_WRITE_FORMAT_OFF (22u)
+
+/** \brief Length for Ifx_CIF_MI_CTRL_Bits.RAW_ENABLE */
+#define IFX_CIF_MI_CTRL_RAW_ENABLE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_CTRL_Bits.RAW_ENABLE */
+#define IFX_CIF_MI_CTRL_RAW_ENABLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_CTRL_Bits.RAW_ENABLE */
+#define IFX_CIF_MI_CTRL_RAW_ENABLE_OFF (3u)
+
+/** \brief Length for Ifx_CIF_MI_CTRL_SHD_Bits.JPEG_ENABLE_IN */
+#define IFX_CIF_MI_CTRL_SHD_JPEG_ENABLE_IN_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_CTRL_SHD_Bits.JPEG_ENABLE_IN */
+#define IFX_CIF_MI_CTRL_SHD_JPEG_ENABLE_IN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_CTRL_SHD_Bits.JPEG_ENABLE_IN */
+#define IFX_CIF_MI_CTRL_SHD_JPEG_ENABLE_IN_OFF (4u)
+
+/** \brief Length for Ifx_CIF_MI_CTRL_SHD_Bits.JPEG_ENABLE_OUT */
+#define IFX_CIF_MI_CTRL_SHD_JPEG_ENABLE_OUT_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_CTRL_SHD_Bits.JPEG_ENABLE_OUT */
+#define IFX_CIF_MI_CTRL_SHD_JPEG_ENABLE_OUT_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_CTRL_SHD_Bits.JPEG_ENABLE_OUT */
+#define IFX_CIF_MI_CTRL_SHD_JPEG_ENABLE_OUT_OFF (18u)
+
+/** \brief Length for Ifx_CIF_MI_CTRL_SHD_Bits.MP_ENABLE_IN */
+#define IFX_CIF_MI_CTRL_SHD_MP_ENABLE_IN_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_CTRL_SHD_Bits.MP_ENABLE_IN */
+#define IFX_CIF_MI_CTRL_SHD_MP_ENABLE_IN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_CTRL_SHD_Bits.MP_ENABLE_IN */
+#define IFX_CIF_MI_CTRL_SHD_MP_ENABLE_IN_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_CTRL_SHD_Bits.MP_ENABLE_OUT */
+#define IFX_CIF_MI_CTRL_SHD_MP_ENABLE_OUT_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_CTRL_SHD_Bits.MP_ENABLE_OUT */
+#define IFX_CIF_MI_CTRL_SHD_MP_ENABLE_OUT_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_CTRL_SHD_Bits.MP_ENABLE_OUT */
+#define IFX_CIF_MI_CTRL_SHD_MP_ENABLE_OUT_OFF (16u)
+
+/** \brief Length for Ifx_CIF_MI_CTRL_SHD_Bits.RAW_ENABLE_IN */
+#define IFX_CIF_MI_CTRL_SHD_RAW_ENABLE_IN_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_CTRL_SHD_Bits.RAW_ENABLE_IN */
+#define IFX_CIF_MI_CTRL_SHD_RAW_ENABLE_IN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_CTRL_SHD_Bits.RAW_ENABLE_IN */
+#define IFX_CIF_MI_CTRL_SHD_RAW_ENABLE_IN_OFF (5u)
+
+/** \brief Length for Ifx_CIF_MI_CTRL_SHD_Bits.RAW_ENABLE_OUT */
+#define IFX_CIF_MI_CTRL_SHD_RAW_ENABLE_OUT_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_CTRL_SHD_Bits.RAW_ENABLE_OUT */
+#define IFX_CIF_MI_CTRL_SHD_RAW_ENABLE_OUT_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_CTRL_SHD_Bits.RAW_ENABLE_OUT */
+#define IFX_CIF_MI_CTRL_SHD_RAW_ENABLE_OUT_OFF (19u)
+
+/** \brief Length for Ifx_CIF_MI_ICR_Bits.BUS_ERROR */
+#define IFX_CIF_MI_ICR_BUS_ERROR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_ICR_Bits.BUS_ERROR */
+#define IFX_CIF_MI_ICR_BUS_ERROR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_ICR_Bits.BUS_ERROR */
+#define IFX_CIF_MI_ICR_BUS_ERROR_OFF (10u)
+
+/** \brief Length for Ifx_CIF_MI_ICR_Bits.FILL_MPY */
+#define IFX_CIF_MI_ICR_FILL_MPY_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_ICR_Bits.FILL_MPY */
+#define IFX_CIF_MI_ICR_FILL_MPY_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_ICR_Bits.FILL_MPY */
+#define IFX_CIF_MI_ICR_FILL_MPY_OFF (3u)
+
+/** \brief Length for Ifx_CIF_MI_ICR_Bits.MBLK_LINE */
+#define IFX_CIF_MI_ICR_MBLK_LINE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_ICR_Bits.MBLK_LINE */
+#define IFX_CIF_MI_ICR_MBLK_LINE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_ICR_Bits.MBLK_LINE */
+#define IFX_CIF_MI_ICR_MBLK_LINE_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_ICR_Bits.MP_FRAME_END */
+#define IFX_CIF_MI_ICR_MP_FRAME_END_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_ICR_Bits.MP_FRAME_END */
+#define IFX_CIF_MI_ICR_MP_FRAME_END_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_ICR_Bits.MP_FRAME_END */
+#define IFX_CIF_MI_ICR_MP_FRAME_END_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_ICR_Bits.WRAP_MP_CB */
+#define IFX_CIF_MI_ICR_WRAP_MP_CB_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_ICR_Bits.WRAP_MP_CB */
+#define IFX_CIF_MI_ICR_WRAP_MP_CB_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_ICR_Bits.WRAP_MP_CB */
+#define IFX_CIF_MI_ICR_WRAP_MP_CB_OFF (5u)
+
+/** \brief Length for Ifx_CIF_MI_ICR_Bits.WRAP_MP_CR */
+#define IFX_CIF_MI_ICR_WRAP_MP_CR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_ICR_Bits.WRAP_MP_CR */
+#define IFX_CIF_MI_ICR_WRAP_MP_CR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_ICR_Bits.WRAP_MP_CR */
+#define IFX_CIF_MI_ICR_WRAP_MP_CR_OFF (6u)
+
+/** \brief Length for Ifx_CIF_MI_ICR_Bits.WRAP_MP_Y */
+#define IFX_CIF_MI_ICR_WRAP_MP_Y_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_ICR_Bits.WRAP_MP_Y */
+#define IFX_CIF_MI_ICR_WRAP_MP_Y_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_ICR_Bits.WRAP_MP_Y */
+#define IFX_CIF_MI_ICR_WRAP_MP_Y_OFF (4u)
+
+/** \brief Length for Ifx_CIF_MI_IMSC_Bits.BUS_ERROR */
+#define IFX_CIF_MI_IMSC_BUS_ERROR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_IMSC_Bits.BUS_ERROR */
+#define IFX_CIF_MI_IMSC_BUS_ERROR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_IMSC_Bits.BUS_ERROR */
+#define IFX_CIF_MI_IMSC_BUS_ERROR_OFF (10u)
+
+/** \brief Length for Ifx_CIF_MI_IMSC_Bits.FILL_MP_Y */
+#define IFX_CIF_MI_IMSC_FILL_MP_Y_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_IMSC_Bits.FILL_MP_Y */
+#define IFX_CIF_MI_IMSC_FILL_MP_Y_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_IMSC_Bits.FILL_MP_Y */
+#define IFX_CIF_MI_IMSC_FILL_MP_Y_OFF (3u)
+
+/** \brief Length for Ifx_CIF_MI_IMSC_Bits.MBLK_LINE */
+#define IFX_CIF_MI_IMSC_MBLK_LINE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_IMSC_Bits.MBLK_LINE */
+#define IFX_CIF_MI_IMSC_MBLK_LINE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_IMSC_Bits.MBLK_LINE */
+#define IFX_CIF_MI_IMSC_MBLK_LINE_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_IMSC_Bits.MP_FRAME_END */
+#define IFX_CIF_MI_IMSC_MP_FRAME_END_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_IMSC_Bits.MP_FRAME_END */
+#define IFX_CIF_MI_IMSC_MP_FRAME_END_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_IMSC_Bits.MP_FRAME_END */
+#define IFX_CIF_MI_IMSC_MP_FRAME_END_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_IMSC_Bits.WRAP_MP_CB */
+#define IFX_CIF_MI_IMSC_WRAP_MP_CB_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_IMSC_Bits.WRAP_MP_CB */
+#define IFX_CIF_MI_IMSC_WRAP_MP_CB_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_IMSC_Bits.WRAP_MP_CB */
+#define IFX_CIF_MI_IMSC_WRAP_MP_CB_OFF (5u)
+
+/** \brief Length for Ifx_CIF_MI_IMSC_Bits.WRAP_MP_CR */
+#define IFX_CIF_MI_IMSC_WRAP_MP_CR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_IMSC_Bits.WRAP_MP_CR */
+#define IFX_CIF_MI_IMSC_WRAP_MP_CR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_IMSC_Bits.WRAP_MP_CR */
+#define IFX_CIF_MI_IMSC_WRAP_MP_CR_OFF (6u)
+
+/** \brief Length for Ifx_CIF_MI_IMSC_Bits.WRAP_MP_Y */
+#define IFX_CIF_MI_IMSC_WRAP_MP_Y_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_IMSC_Bits.WRAP_MP_Y */
+#define IFX_CIF_MI_IMSC_WRAP_MP_Y_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_IMSC_Bits.WRAP_MP_Y */
+#define IFX_CIF_MI_IMSC_WRAP_MP_Y_OFF (4u)
+
+/** \brief Length for Ifx_CIF_MI_INIT_Bits.MI_CFG_UPD */
+#define IFX_CIF_MI_INIT_MI_CFG_UPD_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_INIT_Bits.MI_CFG_UPD */
+#define IFX_CIF_MI_INIT_MI_CFG_UPD_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_INIT_Bits.MI_CFG_UPD */
+#define IFX_CIF_MI_INIT_MI_CFG_UPD_OFF (4u)
+
+/** \brief Length for Ifx_CIF_MI_INIT_Bits.MI_SKIP */
+#define IFX_CIF_MI_INIT_MI_SKIP_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_INIT_Bits.MI_SKIP */
+#define IFX_CIF_MI_INIT_MI_SKIP_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_INIT_Bits.MI_SKIP */
+#define IFX_CIF_MI_INIT_MI_SKIP_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_ISR_Bits.Bus_ERROR */
+#define IFX_CIF_MI_ISR_BUS_ERROR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_ISR_Bits.Bus_ERROR */
+#define IFX_CIF_MI_ISR_BUS_ERROR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_ISR_Bits.Bus_ERROR */
+#define IFX_CIF_MI_ISR_BUS_ERROR_OFF (10u)
+
+/** \brief Length for Ifx_CIF_MI_ISR_Bits.FILL_MP_Y */
+#define IFX_CIF_MI_ISR_FILL_MP_Y_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_ISR_Bits.FILL_MP_Y */
+#define IFX_CIF_MI_ISR_FILL_MP_Y_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_ISR_Bits.FILL_MP_Y */
+#define IFX_CIF_MI_ISR_FILL_MP_Y_OFF (3u)
+
+/** \brief Length for Ifx_CIF_MI_ISR_Bits.MBLK_LINE */
+#define IFX_CIF_MI_ISR_MBLK_LINE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_ISR_Bits.MBLK_LINE */
+#define IFX_CIF_MI_ISR_MBLK_LINE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_ISR_Bits.MBLK_LINE */
+#define IFX_CIF_MI_ISR_MBLK_LINE_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_ISR_Bits.MP_FRAME_END */
+#define IFX_CIF_MI_ISR_MP_FRAME_END_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_ISR_Bits.MP_FRAME_END */
+#define IFX_CIF_MI_ISR_MP_FRAME_END_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_ISR_Bits.MP_FRAME_END */
+#define IFX_CIF_MI_ISR_MP_FRAME_END_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_ISR_Bits.WRAP_MP_CB */
+#define IFX_CIF_MI_ISR_WRAP_MP_CB_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_ISR_Bits.WRAP_MP_CB */
+#define IFX_CIF_MI_ISR_WRAP_MP_CB_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_ISR_Bits.WRAP_MP_CB */
+#define IFX_CIF_MI_ISR_WRAP_MP_CB_OFF (5u)
+
+/** \brief Length for Ifx_CIF_MI_ISR_Bits.WRAP_MP_CR */
+#define IFX_CIF_MI_ISR_WRAP_MP_CR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_ISR_Bits.WRAP_MP_CR */
+#define IFX_CIF_MI_ISR_WRAP_MP_CR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_ISR_Bits.WRAP_MP_CR */
+#define IFX_CIF_MI_ISR_WRAP_MP_CR_OFF (6u)
+
+/** \brief Length for Ifx_CIF_MI_ISR_Bits.WRAP_MP_Y */
+#define IFX_CIF_MI_ISR_WRAP_MP_Y_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_ISR_Bits.WRAP_MP_Y */
+#define IFX_CIF_MI_ISR_WRAP_MP_Y_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_ISR_Bits.WRAP_MP_Y */
+#define IFX_CIF_MI_ISR_WRAP_MP_Y_OFF (4u)
+
+/** \brief Length for Ifx_CIF_MI_MIS_Bits.BUS_ERROR */
+#define IFX_CIF_MI_MIS_BUS_ERROR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_MIS_Bits.BUS_ERROR */
+#define IFX_CIF_MI_MIS_BUS_ERROR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_MIS_Bits.BUS_ERROR */
+#define IFX_CIF_MI_MIS_BUS_ERROR_OFF (10u)
+
+/** \brief Length for Ifx_CIF_MI_MIS_Bits.FILL_MP_Y */
+#define IFX_CIF_MI_MIS_FILL_MP_Y_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_MIS_Bits.FILL_MP_Y */
+#define IFX_CIF_MI_MIS_FILL_MP_Y_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_MIS_Bits.FILL_MP_Y */
+#define IFX_CIF_MI_MIS_FILL_MP_Y_OFF (3u)
+
+/** \brief Length for Ifx_CIF_MI_MIS_Bits.MBLK_LINE */
+#define IFX_CIF_MI_MIS_MBLK_LINE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_MIS_Bits.MBLK_LINE */
+#define IFX_CIF_MI_MIS_MBLK_LINE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_MIS_Bits.MBLK_LINE */
+#define IFX_CIF_MI_MIS_MBLK_LINE_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_MIS_Bits.MP_FRAME_END */
+#define IFX_CIF_MI_MIS_MP_FRAME_END_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_MIS_Bits.MP_FRAME_END */
+#define IFX_CIF_MI_MIS_MP_FRAME_END_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_MIS_Bits.MP_FRAME_END */
+#define IFX_CIF_MI_MIS_MP_FRAME_END_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_MIS_Bits.WRAP_MP_CB */
+#define IFX_CIF_MI_MIS_WRAP_MP_CB_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_MIS_Bits.WRAP_MP_CB */
+#define IFX_CIF_MI_MIS_WRAP_MP_CB_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_MIS_Bits.WRAP_MP_CB */
+#define IFX_CIF_MI_MIS_WRAP_MP_CB_OFF (5u)
+
+/** \brief Length for Ifx_CIF_MI_MIS_Bits.WRAP_MP_CR */
+#define IFX_CIF_MI_MIS_WRAP_MP_CR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_MIS_Bits.WRAP_MP_CR */
+#define IFX_CIF_MI_MIS_WRAP_MP_CR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_MIS_Bits.WRAP_MP_CR */
+#define IFX_CIF_MI_MIS_WRAP_MP_CR_OFF (6u)
+
+/** \brief Length for Ifx_CIF_MI_MIS_Bits.WRAP_MP_Y */
+#define IFX_CIF_MI_MIS_WRAP_MP_Y_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_MIS_Bits.WRAP_MP_Y */
+#define IFX_CIF_MI_MIS_WRAP_MP_Y_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_MIS_Bits.WRAP_MP_Y */
+#define IFX_CIF_MI_MIS_WRAP_MP_Y_OFF (4u)
+
+/** \brief Length for Ifx_CIF_MI_MP_CB_BASE_AD_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CB_BASE_AD_INIT_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_CB_BASE_AD_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CB_BASE_AD_INIT_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MI_MP_CB_BASE_AD_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CB_BASE_AD_INIT_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_MP_CB_BASE_AD_INIT_Bits.MP_CB_BASEAD_INIT */
+#define IFX_CIF_MI_MP_CB_BASE_AD_INIT_MP_CB_BASEAD_INIT_LEN (30u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_CB_BASE_AD_INIT_Bits.MP_CB_BASEAD_INIT */
+#define IFX_CIF_MI_MP_CB_BASE_AD_INIT_MP_CB_BASEAD_INIT_MSK (0x3fffffffu)
+
+/** \brief Offset for Ifx_CIF_MI_MP_CB_BASE_AD_INIT_Bits.MP_CB_BASEAD_INIT */
+#define IFX_CIF_MI_MP_CB_BASE_AD_INIT_MP_CB_BASEAD_INIT_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_MP_CB_BASE_AD_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CB_BASE_AD_SHD_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_CB_BASE_AD_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CB_BASE_AD_SHD_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MI_MP_CB_BASE_AD_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CB_BASE_AD_SHD_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_MP_CB_BASE_AD_SHD_Bits.MP_CB_BASE_AD */
+#define IFX_CIF_MI_MP_CB_BASE_AD_SHD_MP_CB_BASE_AD_LEN (30u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_CB_BASE_AD_SHD_Bits.MP_CB_BASE_AD */
+#define IFX_CIF_MI_MP_CB_BASE_AD_SHD_MP_CB_BASE_AD_MSK (0x3fffffffu)
+
+/** \brief Offset for Ifx_CIF_MI_MP_CB_BASE_AD_SHD_Bits.MP_CB_BASE_AD */
+#define IFX_CIF_MI_MP_CB_BASE_AD_SHD_MP_CB_BASE_AD_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_MP_CB_OFFS_CNT_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CB_OFFS_CNT_INIT_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_CB_OFFS_CNT_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CB_OFFS_CNT_INIT_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MI_MP_CB_OFFS_CNT_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CB_OFFS_CNT_INIT_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_MP_CB_OFFS_CNT_INIT_Bits.MP_CB_OFFS_CNT_INIT */
+#define IFX_CIF_MI_MP_CB_OFFS_CNT_INIT_MP_CB_OFFS_CNT_INIT_LEN (22u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_CB_OFFS_CNT_INIT_Bits.MP_CB_OFFS_CNT_INIT */
+#define IFX_CIF_MI_MP_CB_OFFS_CNT_INIT_MP_CB_OFFS_CNT_INIT_MSK (0x3fffffu)
+
+/** \brief Offset for Ifx_CIF_MI_MP_CB_OFFS_CNT_INIT_Bits.MP_CB_OFFS_CNT_INIT */
+#define IFX_CIF_MI_MP_CB_OFFS_CNT_INIT_MP_CB_OFFS_CNT_INIT_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_MP_CB_OFFS_CNT_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CB_OFFS_CNT_SHD_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_CB_OFFS_CNT_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CB_OFFS_CNT_SHD_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MI_MP_CB_OFFS_CNT_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CB_OFFS_CNT_SHD_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_MP_CB_OFFS_CNT_SHD_Bits.MP_CB_OFFS_CNT */
+#define IFX_CIF_MI_MP_CB_OFFS_CNT_SHD_MP_CB_OFFS_CNT_LEN (22u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_CB_OFFS_CNT_SHD_Bits.MP_CB_OFFS_CNT */
+#define IFX_CIF_MI_MP_CB_OFFS_CNT_SHD_MP_CB_OFFS_CNT_MSK (0x3fffffu)
+
+/** \brief Offset for Ifx_CIF_MI_MP_CB_OFFS_CNT_SHD_Bits.MP_CB_OFFS_CNT */
+#define IFX_CIF_MI_MP_CB_OFFS_CNT_SHD_MP_CB_OFFS_CNT_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_MP_CB_OFFS_CNT_START_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CB_OFFS_CNT_START_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_CB_OFFS_CNT_START_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CB_OFFS_CNT_START_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MI_MP_CB_OFFS_CNT_START_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CB_OFFS_CNT_START_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_MP_CB_OFFS_CNT_START_Bits.MP_CB_OFFS_CNT_START */
+#define IFX_CIF_MI_MP_CB_OFFS_CNT_START_MP_CB_OFFS_CNT_START_LEN (22u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_CB_OFFS_CNT_START_Bits.MP_CB_OFFS_CNT_START */
+#define IFX_CIF_MI_MP_CB_OFFS_CNT_START_MP_CB_OFFS_CNT_START_MSK (0x3fffffu)
+
+/** \brief Offset for Ifx_CIF_MI_MP_CB_OFFS_CNT_START_Bits.MP_CB_OFFS_CNT_START */
+#define IFX_CIF_MI_MP_CB_OFFS_CNT_START_MP_CB_OFFS_CNT_START_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_MP_CB_SIZE_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CB_SIZE_INIT_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_CB_SIZE_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CB_SIZE_INIT_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MI_MP_CB_SIZE_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CB_SIZE_INIT_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_MP_CB_SIZE_INIT_Bits.MP_CB_SIZE_INIT */
+#define IFX_CIF_MI_MP_CB_SIZE_INIT_MP_CB_SIZE_INIT_LEN (22u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_CB_SIZE_INIT_Bits.MP_CB_SIZE_INIT */
+#define IFX_CIF_MI_MP_CB_SIZE_INIT_MP_CB_SIZE_INIT_MSK (0x3fffffu)
+
+/** \brief Offset for Ifx_CIF_MI_MP_CB_SIZE_INIT_Bits.MP_CB_SIZE_INIT */
+#define IFX_CIF_MI_MP_CB_SIZE_INIT_MP_CB_SIZE_INIT_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_MP_CB_SIZE_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CB_SIZE_SHD_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_CB_SIZE_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CB_SIZE_SHD_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MI_MP_CB_SIZE_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CB_SIZE_SHD_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_MP_CB_SIZE_SHD_Bits.MP_CB_SIZE */
+#define IFX_CIF_MI_MP_CB_SIZE_SHD_MP_CB_SIZE_LEN (22u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_CB_SIZE_SHD_Bits.MP_CB_SIZE */
+#define IFX_CIF_MI_MP_CB_SIZE_SHD_MP_CB_SIZE_MSK (0x3fffffu)
+
+/** \brief Offset for Ifx_CIF_MI_MP_CB_SIZE_SHD_Bits.MP_CB_SIZE */
+#define IFX_CIF_MI_MP_CB_SIZE_SHD_MP_CB_SIZE_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_MP_CR_BASE_AD_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CR_BASE_AD_INIT_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_CR_BASE_AD_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CR_BASE_AD_INIT_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MI_MP_CR_BASE_AD_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CR_BASE_AD_INIT_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_MP_CR_BASE_AD_INIT_Bits.MP_CR_BASE_AD_INIT */
+#define IFX_CIF_MI_MP_CR_BASE_AD_INIT_MP_CR_BASE_AD_INIT_LEN (30u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_CR_BASE_AD_INIT_Bits.MP_CR_BASE_AD_INIT */
+#define IFX_CIF_MI_MP_CR_BASE_AD_INIT_MP_CR_BASE_AD_INIT_MSK (0x3fffffffu)
+
+/** \brief Offset for Ifx_CIF_MI_MP_CR_BASE_AD_INIT_Bits.MP_CR_BASE_AD_INIT */
+#define IFX_CIF_MI_MP_CR_BASE_AD_INIT_MP_CR_BASE_AD_INIT_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_MP_CR_BASE_AD_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CR_BASE_AD_SHD_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_CR_BASE_AD_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CR_BASE_AD_SHD_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MI_MP_CR_BASE_AD_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CR_BASE_AD_SHD_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_MP_CR_BASE_AD_SHD_Bits.MP_CR_BASE_AD */
+#define IFX_CIF_MI_MP_CR_BASE_AD_SHD_MP_CR_BASE_AD_LEN (30u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_CR_BASE_AD_SHD_Bits.MP_CR_BASE_AD */
+#define IFX_CIF_MI_MP_CR_BASE_AD_SHD_MP_CR_BASE_AD_MSK (0x3fffffffu)
+
+/** \brief Offset for Ifx_CIF_MI_MP_CR_BASE_AD_SHD_Bits.MP_CR_BASE_AD */
+#define IFX_CIF_MI_MP_CR_BASE_AD_SHD_MP_CR_BASE_AD_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_MP_CR_OFFS_CNT_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CR_OFFS_CNT_INIT_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_CR_OFFS_CNT_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CR_OFFS_CNT_INIT_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MI_MP_CR_OFFS_CNT_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CR_OFFS_CNT_INIT_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_MP_CR_OFFS_CNT_INIT_Bits.MP_CR_OFFS_CNT_INIT */
+#define IFX_CIF_MI_MP_CR_OFFS_CNT_INIT_MP_CR_OFFS_CNT_INIT_LEN (22u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_CR_OFFS_CNT_INIT_Bits.MP_CR_OFFS_CNT_INIT */
+#define IFX_CIF_MI_MP_CR_OFFS_CNT_INIT_MP_CR_OFFS_CNT_INIT_MSK (0x3fffffu)
+
+/** \brief Offset for Ifx_CIF_MI_MP_CR_OFFS_CNT_INIT_Bits.MP_CR_OFFS_CNT_INIT */
+#define IFX_CIF_MI_MP_CR_OFFS_CNT_INIT_MP_CR_OFFS_CNT_INIT_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_MP_CR_OFFS_CNT_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CR_OFFS_CNT_SHD_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_CR_OFFS_CNT_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CR_OFFS_CNT_SHD_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MI_MP_CR_OFFS_CNT_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CR_OFFS_CNT_SHD_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_MP_CR_OFFS_CNT_SHD_Bits.MP_CR_OFFS_CNT */
+#define IFX_CIF_MI_MP_CR_OFFS_CNT_SHD_MP_CR_OFFS_CNT_LEN (22u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_CR_OFFS_CNT_SHD_Bits.MP_CR_OFFS_CNT */
+#define IFX_CIF_MI_MP_CR_OFFS_CNT_SHD_MP_CR_OFFS_CNT_MSK (0x3fffffu)
+
+/** \brief Offset for Ifx_CIF_MI_MP_CR_OFFS_CNT_SHD_Bits.MP_CR_OFFS_CNT */
+#define IFX_CIF_MI_MP_CR_OFFS_CNT_SHD_MP_CR_OFFS_CNT_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_MP_CR_OFFS_CNT_START_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CR_OFFS_CNT_START_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_CR_OFFS_CNT_START_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CR_OFFS_CNT_START_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MI_MP_CR_OFFS_CNT_START_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CR_OFFS_CNT_START_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_MP_CR_OFFS_CNT_START_Bits.MP_CR_OFFS_CNT_START */
+#define IFX_CIF_MI_MP_CR_OFFS_CNT_START_MP_CR_OFFS_CNT_START_LEN (22u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_CR_OFFS_CNT_START_Bits.MP_CR_OFFS_CNT_START */
+#define IFX_CIF_MI_MP_CR_OFFS_CNT_START_MP_CR_OFFS_CNT_START_MSK (0x3fffffu)
+
+/** \brief Offset for Ifx_CIF_MI_MP_CR_OFFS_CNT_START_Bits.MP_CR_OFFS_CNT_START */
+#define IFX_CIF_MI_MP_CR_OFFS_CNT_START_MP_CR_OFFS_CNT_START_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_MP_CR_SIZE_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CR_SIZE_INIT_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_CR_SIZE_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CR_SIZE_INIT_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MI_MP_CR_SIZE_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CR_SIZE_INIT_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_MP_CR_SIZE_INIT_Bits.MP_CR_SIZE_INIT */
+#define IFX_CIF_MI_MP_CR_SIZE_INIT_MP_CR_SIZE_INIT_LEN (22u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_CR_SIZE_INIT_Bits.MP_CR_SIZE_INIT */
+#define IFX_CIF_MI_MP_CR_SIZE_INIT_MP_CR_SIZE_INIT_MSK (0x3fffffu)
+
+/** \brief Offset for Ifx_CIF_MI_MP_CR_SIZE_INIT_Bits.MP_CR_SIZE_INIT */
+#define IFX_CIF_MI_MP_CR_SIZE_INIT_MP_CR_SIZE_INIT_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_MP_CR_SIZE_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CR_SIZE_SHD_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_CR_SIZE_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CR_SIZE_SHD_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MI_MP_CR_SIZE_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_CR_SIZE_SHD_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_MP_CR_SIZE_SHD_Bits.MP_CR_SIZE */
+#define IFX_CIF_MI_MP_CR_SIZE_SHD_MP_CR_SIZE_LEN (22u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_CR_SIZE_SHD_Bits.MP_CR_SIZE */
+#define IFX_CIF_MI_MP_CR_SIZE_SHD_MP_CR_SIZE_MSK (0x3fffffu)
+
+/** \brief Offset for Ifx_CIF_MI_MP_CR_SIZE_SHD_Bits.MP_CR_SIZE */
+#define IFX_CIF_MI_MP_CR_SIZE_SHD_MP_CR_SIZE_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_MP_Y_BASE_AD_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_Y_BASE_AD_INIT_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_Y_BASE_AD_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_Y_BASE_AD_INIT_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MI_MP_Y_BASE_AD_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_Y_BASE_AD_INIT_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_MP_Y_BASE_AD_INIT_Bits.MP_Y_BASE_AD_INIT */
+#define IFX_CIF_MI_MP_Y_BASE_AD_INIT_MP_Y_BASE_AD_INIT_LEN (30u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_Y_BASE_AD_INIT_Bits.MP_Y_BASE_AD_INIT */
+#define IFX_CIF_MI_MP_Y_BASE_AD_INIT_MP_Y_BASE_AD_INIT_MSK (0x3fffffffu)
+
+/** \brief Offset for Ifx_CIF_MI_MP_Y_BASE_AD_INIT_Bits.MP_Y_BASE_AD_INIT */
+#define IFX_CIF_MI_MP_Y_BASE_AD_INIT_MP_Y_BASE_AD_INIT_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_MP_Y_BASE_AD_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_Y_BASE_AD_SHD_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_Y_BASE_AD_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_Y_BASE_AD_SHD_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MI_MP_Y_BASE_AD_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_Y_BASE_AD_SHD_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_MP_Y_BASE_AD_SHD_Bits.MP_Y_BASE_AD */
+#define IFX_CIF_MI_MP_Y_BASE_AD_SHD_MP_Y_BASE_AD_LEN (30u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_Y_BASE_AD_SHD_Bits.MP_Y_BASE_AD */
+#define IFX_CIF_MI_MP_Y_BASE_AD_SHD_MP_Y_BASE_AD_MSK (0x3fffffffu)
+
+/** \brief Offset for Ifx_CIF_MI_MP_Y_BASE_AD_SHD_Bits.MP_Y_BASE_AD */
+#define IFX_CIF_MI_MP_Y_BASE_AD_SHD_MP_Y_BASE_AD_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_MP_Y_IRQ_OFFS_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_Y_IRQ_OFFS_INIT_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_Y_IRQ_OFFS_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_Y_IRQ_OFFS_INIT_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MI_MP_Y_IRQ_OFFS_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_Y_IRQ_OFFS_INIT_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_MP_Y_IRQ_OFFS_INIT_Bits.MP_Y_IRQ_OFFS_INIT */
+#define IFX_CIF_MI_MP_Y_IRQ_OFFS_INIT_MP_Y_IRQ_OFFS_INIT_LEN (22u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_Y_IRQ_OFFS_INIT_Bits.MP_Y_IRQ_OFFS_INIT */
+#define IFX_CIF_MI_MP_Y_IRQ_OFFS_INIT_MP_Y_IRQ_OFFS_INIT_MSK (0x3fffffu)
+
+/** \brief Offset for Ifx_CIF_MI_MP_Y_IRQ_OFFS_INIT_Bits.MP_Y_IRQ_OFFS_INIT */
+#define IFX_CIF_MI_MP_Y_IRQ_OFFS_INIT_MP_Y_IRQ_OFFS_INIT_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_MP_Y_IRQ_OFFS_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_Y_IRQ_OFFS_SHD_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_Y_IRQ_OFFS_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_Y_IRQ_OFFS_SHD_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MI_MP_Y_IRQ_OFFS_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_Y_IRQ_OFFS_SHD_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_MP_Y_IRQ_OFFS_SHD_Bits.MP_Y_IRQ_OFFS */
+#define IFX_CIF_MI_MP_Y_IRQ_OFFS_SHD_MP_Y_IRQ_OFFS_LEN (22u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_Y_IRQ_OFFS_SHD_Bits.MP_Y_IRQ_OFFS */
+#define IFX_CIF_MI_MP_Y_IRQ_OFFS_SHD_MP_Y_IRQ_OFFS_MSK (0x3fffffu)
+
+/** \brief Offset for Ifx_CIF_MI_MP_Y_IRQ_OFFS_SHD_Bits.MP_Y_IRQ_OFFS */
+#define IFX_CIF_MI_MP_Y_IRQ_OFFS_SHD_MP_Y_IRQ_OFFS_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_MP_Y_OFFS_CNT_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_Y_OFFS_CNT_INIT_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_Y_OFFS_CNT_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_Y_OFFS_CNT_INIT_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MI_MP_Y_OFFS_CNT_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_Y_OFFS_CNT_INIT_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_MP_Y_OFFS_CNT_INIT_Bits.MP_Y_OFFS_CNT_INIT */
+#define IFX_CIF_MI_MP_Y_OFFS_CNT_INIT_MP_Y_OFFS_CNT_INIT_LEN (22u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_Y_OFFS_CNT_INIT_Bits.MP_Y_OFFS_CNT_INIT */
+#define IFX_CIF_MI_MP_Y_OFFS_CNT_INIT_MP_Y_OFFS_CNT_INIT_MSK (0x3fffffu)
+
+/** \brief Offset for Ifx_CIF_MI_MP_Y_OFFS_CNT_INIT_Bits.MP_Y_OFFS_CNT_INIT */
+#define IFX_CIF_MI_MP_Y_OFFS_CNT_INIT_MP_Y_OFFS_CNT_INIT_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_MP_Y_OFFS_CNT_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_Y_OFFS_CNT_SHD_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_Y_OFFS_CNT_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_Y_OFFS_CNT_SHD_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MI_MP_Y_OFFS_CNT_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_Y_OFFS_CNT_SHD_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_MP_Y_OFFS_CNT_SHD_Bits.MP_Y_OFFS_CNT */
+#define IFX_CIF_MI_MP_Y_OFFS_CNT_SHD_MP_Y_OFFS_CNT_LEN (22u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_Y_OFFS_CNT_SHD_Bits.MP_Y_OFFS_CNT */
+#define IFX_CIF_MI_MP_Y_OFFS_CNT_SHD_MP_Y_OFFS_CNT_MSK (0x3fffffu)
+
+/** \brief Offset for Ifx_CIF_MI_MP_Y_OFFS_CNT_SHD_Bits.MP_Y_OFFS_CNT */
+#define IFX_CIF_MI_MP_Y_OFFS_CNT_SHD_MP_Y_OFFS_CNT_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_MP_Y_OFFS_CNT_START_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_Y_OFFS_CNT_START_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_Y_OFFS_CNT_START_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_Y_OFFS_CNT_START_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MI_MP_Y_OFFS_CNT_START_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_Y_OFFS_CNT_START_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_MP_Y_OFFS_CNT_START_Bits.MP_Y_OFFS_CNT_START */
+#define IFX_CIF_MI_MP_Y_OFFS_CNT_START_MP_Y_OFFS_CNT_START_LEN (22u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_Y_OFFS_CNT_START_Bits.MP_Y_OFFS_CNT_START */
+#define IFX_CIF_MI_MP_Y_OFFS_CNT_START_MP_Y_OFFS_CNT_START_MSK (0x3fffffu)
+
+/** \brief Offset for Ifx_CIF_MI_MP_Y_OFFS_CNT_START_Bits.MP_Y_OFFS_CNT_START */
+#define IFX_CIF_MI_MP_Y_OFFS_CNT_START_MP_Y_OFFS_CNT_START_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_MP_Y_SIZE_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_Y_SIZE_INIT_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_Y_SIZE_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_Y_SIZE_INIT_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MI_MP_Y_SIZE_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_Y_SIZE_INIT_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_MP_Y_SIZE_INIT_Bits.MP_Y_SIZE_INIT */
+#define IFX_CIF_MI_MP_Y_SIZE_INIT_MP_Y_SIZE_INIT_LEN (22u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_Y_SIZE_INIT_Bits.MP_Y_SIZE_INIT */
+#define IFX_CIF_MI_MP_Y_SIZE_INIT_MP_Y_SIZE_INIT_MSK (0x3fffffu)
+
+/** \brief Offset for Ifx_CIF_MI_MP_Y_SIZE_INIT_Bits.MP_Y_SIZE_INIT */
+#define IFX_CIF_MI_MP_Y_SIZE_INIT_MP_Y_SIZE_INIT_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_MP_Y_SIZE_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_Y_SIZE_SHD_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_Y_SIZE_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_Y_SIZE_SHD_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MI_MP_Y_SIZE_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MI_MP_Y_SIZE_SHD_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_MP_Y_SIZE_SHD_Bits.MP_Y_SIZE */
+#define IFX_CIF_MI_MP_Y_SIZE_SHD_MP_Y_SIZE_LEN (22u)
+
+/** \brief Mask for Ifx_CIF_MI_MP_Y_SIZE_SHD_Bits.MP_Y_SIZE */
+#define IFX_CIF_MI_MP_Y_SIZE_SHD_MP_Y_SIZE_MSK (0x3fffffu)
+
+/** \brief Offset for Ifx_CIF_MI_MP_Y_SIZE_SHD_Bits.MP_Y_SIZE */
+#define IFX_CIF_MI_MP_Y_SIZE_SHD_MP_Y_SIZE_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_RIS_Bits.BUS_ERROR */
+#define IFX_CIF_MI_RIS_BUS_ERROR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_RIS_Bits.BUS_ERROR */
+#define IFX_CIF_MI_RIS_BUS_ERROR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_RIS_Bits.BUS_ERROR */
+#define IFX_CIF_MI_RIS_BUS_ERROR_OFF (10u)
+
+/** \brief Length for Ifx_CIF_MI_RIS_Bits.FILL_MP_Y */
+#define IFX_CIF_MI_RIS_FILL_MP_Y_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_RIS_Bits.FILL_MP_Y */
+#define IFX_CIF_MI_RIS_FILL_MP_Y_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_RIS_Bits.FILL_MP_Y */
+#define IFX_CIF_MI_RIS_FILL_MP_Y_OFF (3u)
+
+/** \brief Length for Ifx_CIF_MI_RIS_Bits.MBLK_LINE */
+#define IFX_CIF_MI_RIS_MBLK_LINE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_RIS_Bits.MBLK_LINE */
+#define IFX_CIF_MI_RIS_MBLK_LINE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_RIS_Bits.MBLK_LINE */
+#define IFX_CIF_MI_RIS_MBLK_LINE_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_RIS_Bits.MP_FRAME_END */
+#define IFX_CIF_MI_RIS_MP_FRAME_END_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_RIS_Bits.MP_FRAME_END */
+#define IFX_CIF_MI_RIS_MP_FRAME_END_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_RIS_Bits.MP_FRAME_END */
+#define IFX_CIF_MI_RIS_MP_FRAME_END_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_RIS_Bits.WRAP_MP_CB */
+#define IFX_CIF_MI_RIS_WRAP_MP_CB_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_RIS_Bits.WRAP_MP_CB */
+#define IFX_CIF_MI_RIS_WRAP_MP_CB_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_RIS_Bits.WRAP_MP_CB */
+#define IFX_CIF_MI_RIS_WRAP_MP_CB_OFF (5u)
+
+/** \brief Length for Ifx_CIF_MI_RIS_Bits.WRAP_MP_CR */
+#define IFX_CIF_MI_RIS_WRAP_MP_CR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_RIS_Bits.WRAP_MP_CR */
+#define IFX_CIF_MI_RIS_WRAP_MP_CR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_RIS_Bits.WRAP_MP_CR */
+#define IFX_CIF_MI_RIS_WRAP_MP_CR_OFF (6u)
+
+/** \brief Length for Ifx_CIF_MI_RIS_Bits.WRAP_MP_Y */
+#define IFX_CIF_MI_RIS_WRAP_MP_Y_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_RIS_Bits.WRAP_MP_Y */
+#define IFX_CIF_MI_RIS_WRAP_MP_Y_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_RIS_Bits.WRAP_MP_Y */
+#define IFX_CIF_MI_RIS_WRAP_MP_Y_OFF (4u)
+
+/** \brief Length for Ifx_CIF_MI_STATUS_Bits.BUS_WRITE_ERROR */
+#define IFX_CIF_MI_STATUS_BUS_WRITE_ERROR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_STATUS_Bits.BUS_WRITE_ERROR */
+#define IFX_CIF_MI_STATUS_BUS_WRITE_ERROR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_STATUS_Bits.BUS_WRITE_ERROR */
+#define IFX_CIF_MI_STATUS_BUS_WRITE_ERROR_OFF (8u)
+
+/** \brief Length for Ifx_CIF_MI_STATUS_CLR_Bits.BUS_WRITE_ERROR */
+#define IFX_CIF_MI_STATUS_CLR_BUS_WRITE_ERROR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_STATUS_CLR_Bits.BUS_WRITE_ERROR */
+#define IFX_CIF_MI_STATUS_CLR_BUS_WRITE_ERROR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_STATUS_CLR_Bits.BUS_WRITE_ERROR */
+#define IFX_CIF_MI_STATUS_CLR_BUS_WRITE_ERROR_OFF (8u)
+
+/** \brief Length for Ifx_CIF_MI_STATUS_CLR_Bits.EP_1_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_CLR_EP_1_FIFO_FULL_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_STATUS_CLR_Bits.EP_1_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_CLR_EP_1_FIFO_FULL_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_STATUS_CLR_Bits.EP_1_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_CLR_EP_1_FIFO_FULL_OFF (24u)
+
+/** \brief Length for Ifx_CIF_MI_STATUS_CLR_Bits.EP_2_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_CLR_EP_2_FIFO_FULL_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_STATUS_CLR_Bits.EP_2_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_CLR_EP_2_FIFO_FULL_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_STATUS_CLR_Bits.EP_2_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_CLR_EP_2_FIFO_FULL_OFF (25u)
+
+/** \brief Length for Ifx_CIF_MI_STATUS_CLR_Bits.EP_3_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_CLR_EP_3_FIFO_FULL_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_STATUS_CLR_Bits.EP_3_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_CLR_EP_3_FIFO_FULL_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_STATUS_CLR_Bits.EP_3_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_CLR_EP_3_FIFO_FULL_OFF (26u)
+
+/** \brief Length for Ifx_CIF_MI_STATUS_CLR_Bits.EP_4_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_CLR_EP_4_FIFO_FULL_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_STATUS_CLR_Bits.EP_4_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_CLR_EP_4_FIFO_FULL_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_STATUS_CLR_Bits.EP_4_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_CLR_EP_4_FIFO_FULL_OFF (27u)
+
+/** \brief Length for Ifx_CIF_MI_STATUS_CLR_Bits.EP_5_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_CLR_EP_5_FIFO_FULL_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_STATUS_CLR_Bits.EP_5_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_CLR_EP_5_FIFO_FULL_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_STATUS_CLR_Bits.EP_5_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_CLR_EP_5_FIFO_FULL_OFF (28u)
+
+/** \brief Length for Ifx_CIF_MI_STATUS_CLR_Bits.MP_CB_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_CLR_MP_CB_FIFO_FULL_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_STATUS_CLR_Bits.MP_CB_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_CLR_MP_CB_FIFO_FULL_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_STATUS_CLR_Bits.MP_CB_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_CLR_MP_CB_FIFO_FULL_OFF (1u)
+
+/** \brief Length for Ifx_CIF_MI_STATUS_CLR_Bits.MP_CR_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_CLR_MP_CR_FIFO_FULL_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_STATUS_CLR_Bits.MP_CR_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_CLR_MP_CR_FIFO_FULL_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_STATUS_CLR_Bits.MP_CR_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_CLR_MP_CR_FIFO_FULL_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_STATUS_CLR_Bits.MP_Y_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_CLR_MP_Y_FIFO_FULL_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_STATUS_CLR_Bits.MP_Y_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_CLR_MP_Y_FIFO_FULL_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_STATUS_CLR_Bits.MP_Y_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_CLR_MP_Y_FIFO_FULL_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MI_STATUS_Bits.MP_CB_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_MP_CB_FIFO_FULL_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_STATUS_Bits.MP_CB_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_MP_CB_FIFO_FULL_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_STATUS_Bits.MP_CB_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_MP_CB_FIFO_FULL_OFF (1u)
+
+/** \brief Length for Ifx_CIF_MI_STATUS_Bits.MP_CR_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_MP_CR_FIFO_FULL_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_STATUS_Bits.MP_CR_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_MP_CR_FIFO_FULL_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_STATUS_Bits.MP_CR_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_MP_CR_FIFO_FULL_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MI_STATUS_Bits.MP_Y_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_MP_Y_FIFO_FULL_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MI_STATUS_Bits.MP_Y_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_MP_Y_FIFO_FULL_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MI_STATUS_Bits.MP_Y_FIFO_FULL */
+#define IFX_CIF_MI_STATUS_MP_Y_FIFO_FULL_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MIEP_CH_BASE_AD_INIT_Bits.EP_BASE_AD_INIT */
+#define IFX_CIF_MIEP_CH_BASE_AD_INIT_EP_BASE_AD_INIT_LEN (30u)
+
+/** \brief Mask for Ifx_CIF_MIEP_CH_BASE_AD_INIT_Bits.EP_BASE_AD_INIT */
+#define IFX_CIF_MIEP_CH_BASE_AD_INIT_EP_BASE_AD_INIT_MSK (0x3fffffffu)
+
+/** \brief Offset for Ifx_CIF_MIEP_CH_BASE_AD_INIT_Bits.EP_BASE_AD_INIT */
+#define IFX_CIF_MIEP_CH_BASE_AD_INIT_EP_BASE_AD_INIT_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MIEP_CH_BASE_AD_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MIEP_CH_BASE_AD_INIT_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MIEP_CH_BASE_AD_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MIEP_CH_BASE_AD_INIT_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MIEP_CH_BASE_AD_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MIEP_CH_BASE_AD_INIT_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MIEP_CH_BASE_AD_SHD_Bits.EP_BASE_AD */
+#define IFX_CIF_MIEP_CH_BASE_AD_SHD_EP_BASE_AD_LEN (30u)
+
+/** \brief Mask for Ifx_CIF_MIEP_CH_BASE_AD_SHD_Bits.EP_BASE_AD */
+#define IFX_CIF_MIEP_CH_BASE_AD_SHD_EP_BASE_AD_MSK (0x3fffffffu)
+
+/** \brief Offset for Ifx_CIF_MIEP_CH_BASE_AD_SHD_Bits.EP_BASE_AD */
+#define IFX_CIF_MIEP_CH_BASE_AD_SHD_EP_BASE_AD_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MIEP_CH_BASE_AD_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MIEP_CH_BASE_AD_SHD_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MIEP_CH_BASE_AD_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MIEP_CH_BASE_AD_SHD_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MIEP_CH_BASE_AD_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MIEP_CH_BASE_AD_SHD_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MIEP_CH_CTRL_Bits.BYTE_SWAP */
+#define IFX_CIF_MIEP_CH_CTRL_BYTE_SWAP_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_CH_CTRL_Bits.BYTE_SWAP */
+#define IFX_CIF_MIEP_CH_CTRL_BYTE_SWAP_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_CH_CTRL_Bits.BYTE_SWAP */
+#define IFX_CIF_MIEP_CH_CTRL_BYTE_SWAP_OFF (7u)
+
+/** \brief Length for Ifx_CIF_MIEP_CH_CTRL_Bits.EP_ENABLE */
+#define IFX_CIF_MIEP_CH_CTRL_EP_ENABLE_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_CH_CTRL_Bits.EP_ENABLE */
+#define IFX_CIF_MIEP_CH_CTRL_EP_ENABLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_CH_CTRL_Bits.EP_ENABLE */
+#define IFX_CIF_MIEP_CH_CTRL_EP_ENABLE_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MIEP_CH_CTRL_Bits.EP_WRITE_FORMAT */
+#define IFX_CIF_MIEP_CH_CTRL_EP_WRITE_FORMAT_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MIEP_CH_CTRL_Bits.EP_WRITE_FORMAT */
+#define IFX_CIF_MIEP_CH_CTRL_EP_WRITE_FORMAT_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MIEP_CH_CTRL_Bits.EP_WRITE_FORMAT */
+#define IFX_CIF_MIEP_CH_CTRL_EP_WRITE_FORMAT_OFF (22u)
+
+/** \brief Length for Ifx_CIF_MIEP_CH_CTRL_Bits.INIT_BASE_EN */
+#define IFX_CIF_MIEP_CH_CTRL_INIT_BASE_EN_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_CH_CTRL_Bits.INIT_BASE_EN */
+#define IFX_CIF_MIEP_CH_CTRL_INIT_BASE_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_CH_CTRL_Bits.INIT_BASE_EN */
+#define IFX_CIF_MIEP_CH_CTRL_INIT_BASE_EN_OFF (20u)
+
+/** \brief Length for Ifx_CIF_MIEP_CH_CTRL_Bits.INIT_OFFSET_EN */
+#define IFX_CIF_MIEP_CH_CTRL_INIT_OFFSET_EN_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_CH_CTRL_Bits.INIT_OFFSET_EN */
+#define IFX_CIF_MIEP_CH_CTRL_INIT_OFFSET_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_CH_CTRL_Bits.INIT_OFFSET_EN */
+#define IFX_CIF_MIEP_CH_CTRL_INIT_OFFSET_EN_OFF (21u)
+
+/** \brief Length for Ifx_CIF_MIEP_CH_CTRL_SHD_Bits.EP_ENABLE_IN */
+#define IFX_CIF_MIEP_CH_CTRL_SHD_EP_ENABLE_IN_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_CH_CTRL_SHD_Bits.EP_ENABLE_IN */
+#define IFX_CIF_MIEP_CH_CTRL_SHD_EP_ENABLE_IN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_CH_CTRL_SHD_Bits.EP_ENABLE_IN */
+#define IFX_CIF_MIEP_CH_CTRL_SHD_EP_ENABLE_IN_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MIEP_CH_CTRL_SHD_Bits.EP_ENABLE_OUT */
+#define IFX_CIF_MIEP_CH_CTRL_SHD_EP_ENABLE_OUT_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_CH_CTRL_SHD_Bits.EP_ENABLE_OUT */
+#define IFX_CIF_MIEP_CH_CTRL_SHD_EP_ENABLE_OUT_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_CH_CTRL_SHD_Bits.EP_ENABLE_OUT */
+#define IFX_CIF_MIEP_CH_CTRL_SHD_EP_ENABLE_OUT_OFF (16u)
+
+/** \brief Length for Ifx_CIF_MIEP_CH_INIT_Bits.MI_EP_CFG_UPD */
+#define IFX_CIF_MIEP_CH_INIT_MI_EP_CFG_UPD_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_CH_INIT_Bits.MI_EP_CFG_UPD */
+#define IFX_CIF_MIEP_CH_INIT_MI_EP_CFG_UPD_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_CH_INIT_Bits.MI_EP_CFG_UPD */
+#define IFX_CIF_MIEP_CH_INIT_MI_EP_CFG_UPD_OFF (4u)
+
+/** \brief Length for Ifx_CIF_MIEP_CH_INIT_Bits.MI_EP_SKIP */
+#define IFX_CIF_MIEP_CH_INIT_MI_EP_SKIP_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_CH_INIT_Bits.MI_EP_SKIP */
+#define IFX_CIF_MIEP_CH_INIT_MI_EP_SKIP_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_CH_INIT_Bits.MI_EP_SKIP */
+#define IFX_CIF_MIEP_CH_INIT_MI_EP_SKIP_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MIEP_CH_IRQ_OFFS_INIT_Bits.EP_IRQ_OFFS_INIT */
+#define IFX_CIF_MIEP_CH_IRQ_OFFS_INIT_EP_IRQ_OFFS_INIT_LEN (22u)
+
+/** \brief Mask for Ifx_CIF_MIEP_CH_IRQ_OFFS_INIT_Bits.EP_IRQ_OFFS_INIT */
+#define IFX_CIF_MIEP_CH_IRQ_OFFS_INIT_EP_IRQ_OFFS_INIT_MSK (0x3fffffu)
+
+/** \brief Offset for Ifx_CIF_MIEP_CH_IRQ_OFFS_INIT_Bits.EP_IRQ_OFFS_INIT */
+#define IFX_CIF_MIEP_CH_IRQ_OFFS_INIT_EP_IRQ_OFFS_INIT_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MIEP_CH_IRQ_OFFS_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MIEP_CH_IRQ_OFFS_INIT_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MIEP_CH_IRQ_OFFS_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MIEP_CH_IRQ_OFFS_INIT_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MIEP_CH_IRQ_OFFS_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MIEP_CH_IRQ_OFFS_INIT_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MIEP_CH_IRQ_OFFS_SHD_Bits.EP_IRQ_OFFS */
+#define IFX_CIF_MIEP_CH_IRQ_OFFS_SHD_EP_IRQ_OFFS_LEN (22u)
+
+/** \brief Mask for Ifx_CIF_MIEP_CH_IRQ_OFFS_SHD_Bits.EP_IRQ_OFFS */
+#define IFX_CIF_MIEP_CH_IRQ_OFFS_SHD_EP_IRQ_OFFS_MSK (0x3fffffu)
+
+/** \brief Offset for Ifx_CIF_MIEP_CH_IRQ_OFFS_SHD_Bits.EP_IRQ_OFFS */
+#define IFX_CIF_MIEP_CH_IRQ_OFFS_SHD_EP_IRQ_OFFS_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MIEP_CH_IRQ_OFFS_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MIEP_CH_IRQ_OFFS_SHD_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MIEP_CH_IRQ_OFFS_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MIEP_CH_IRQ_OFFS_SHD_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MIEP_CH_IRQ_OFFS_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MIEP_CH_IRQ_OFFS_SHD_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MIEP_CH_OFFS_CNT_INIT_Bits.EP_OFFS_CNT_INIT */
+#define IFX_CIF_MIEP_CH_OFFS_CNT_INIT_EP_OFFS_CNT_INIT_LEN (22u)
+
+/** \brief Mask for Ifx_CIF_MIEP_CH_OFFS_CNT_INIT_Bits.EP_OFFS_CNT_INIT */
+#define IFX_CIF_MIEP_CH_OFFS_CNT_INIT_EP_OFFS_CNT_INIT_MSK (0x3fffffu)
+
+/** \brief Offset for Ifx_CIF_MIEP_CH_OFFS_CNT_INIT_Bits.EP_OFFS_CNT_INIT */
+#define IFX_CIF_MIEP_CH_OFFS_CNT_INIT_EP_OFFS_CNT_INIT_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MIEP_CH_OFFS_CNT_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MIEP_CH_OFFS_CNT_INIT_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MIEP_CH_OFFS_CNT_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MIEP_CH_OFFS_CNT_INIT_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MIEP_CH_OFFS_CNT_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MIEP_CH_OFFS_CNT_INIT_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MIEP_CH_OFFS_CNT_SHD_Bits.EP_OFFS_CNT */
+#define IFX_CIF_MIEP_CH_OFFS_CNT_SHD_EP_OFFS_CNT_LEN (22u)
+
+/** \brief Mask for Ifx_CIF_MIEP_CH_OFFS_CNT_SHD_Bits.EP_OFFS_CNT */
+#define IFX_CIF_MIEP_CH_OFFS_CNT_SHD_EP_OFFS_CNT_MSK (0x3fffffu)
+
+/** \brief Offset for Ifx_CIF_MIEP_CH_OFFS_CNT_SHD_Bits.EP_OFFS_CNT */
+#define IFX_CIF_MIEP_CH_OFFS_CNT_SHD_EP_OFFS_CNT_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MIEP_CH_OFFS_CNT_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MIEP_CH_OFFS_CNT_SHD_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MIEP_CH_OFFS_CNT_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MIEP_CH_OFFS_CNT_SHD_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MIEP_CH_OFFS_CNT_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MIEP_CH_OFFS_CNT_SHD_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MIEP_CH_OFFS_CNT_START_Bits.EP_OFFS_CNT_START */
+#define IFX_CIF_MIEP_CH_OFFS_CNT_START_EP_OFFS_CNT_START_LEN (22u)
+
+/** \brief Mask for Ifx_CIF_MIEP_CH_OFFS_CNT_START_Bits.EP_OFFS_CNT_START */
+#define IFX_CIF_MIEP_CH_OFFS_CNT_START_EP_OFFS_CNT_START_MSK (0x3fffffu)
+
+/** \brief Offset for Ifx_CIF_MIEP_CH_OFFS_CNT_START_Bits.EP_OFFS_CNT_START */
+#define IFX_CIF_MIEP_CH_OFFS_CNT_START_EP_OFFS_CNT_START_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MIEP_CH_OFFS_CNT_START_Bits.FIXED_TO_00 */
+#define IFX_CIF_MIEP_CH_OFFS_CNT_START_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MIEP_CH_OFFS_CNT_START_Bits.FIXED_TO_00 */
+#define IFX_CIF_MIEP_CH_OFFS_CNT_START_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MIEP_CH_OFFS_CNT_START_Bits.FIXED_TO_00 */
+#define IFX_CIF_MIEP_CH_OFFS_CNT_START_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MIEP_CH_SIZE_INIT_Bits.EP_SIZE_INIT */
+#define IFX_CIF_MIEP_CH_SIZE_INIT_EP_SIZE_INIT_LEN (22u)
+
+/** \brief Mask for Ifx_CIF_MIEP_CH_SIZE_INIT_Bits.EP_SIZE_INIT */
+#define IFX_CIF_MIEP_CH_SIZE_INIT_EP_SIZE_INIT_MSK (0x3fffffu)
+
+/** \brief Offset for Ifx_CIF_MIEP_CH_SIZE_INIT_Bits.EP_SIZE_INIT */
+#define IFX_CIF_MIEP_CH_SIZE_INIT_EP_SIZE_INIT_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MIEP_CH_SIZE_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MIEP_CH_SIZE_INIT_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MIEP_CH_SIZE_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MIEP_CH_SIZE_INIT_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MIEP_CH_SIZE_INIT_Bits.FIXED_TO_00 */
+#define IFX_CIF_MIEP_CH_SIZE_INIT_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MIEP_CH_SIZE_SHD_Bits.EP_SIZE */
+#define IFX_CIF_MIEP_CH_SIZE_SHD_EP_SIZE_LEN (22u)
+
+/** \brief Mask for Ifx_CIF_MIEP_CH_SIZE_SHD_Bits.EP_SIZE */
+#define IFX_CIF_MIEP_CH_SIZE_SHD_EP_SIZE_MSK (0x3fffffu)
+
+/** \brief Offset for Ifx_CIF_MIEP_CH_SIZE_SHD_Bits.EP_SIZE */
+#define IFX_CIF_MIEP_CH_SIZE_SHD_EP_SIZE_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MIEP_CH_SIZE_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MIEP_CH_SIZE_SHD_FIXED_TO_00_LEN (2u)
+
+/** \brief Mask for Ifx_CIF_MIEP_CH_SIZE_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MIEP_CH_SIZE_SHD_FIXED_TO_00_MSK (0x3u)
+
+/** \brief Offset for Ifx_CIF_MIEP_CH_SIZE_SHD_Bits.FIXED_TO_00 */
+#define IFX_CIF_MIEP_CH_SIZE_SHD_FIXED_TO_00_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MIEP_ICR_Bits.FILL_EP_1 */
+#define IFX_CIF_MIEP_ICR_FILL_EP_1_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ICR_Bits.FILL_EP_1 */
+#define IFX_CIF_MIEP_ICR_FILL_EP_1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ICR_Bits.FILL_EP_1 */
+#define IFX_CIF_MIEP_ICR_FILL_EP_1_OFF (1u)
+
+/** \brief Length for Ifx_CIF_MIEP_ICR_Bits.FILL_EP_2 */
+#define IFX_CIF_MIEP_ICR_FILL_EP_2_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ICR_Bits.FILL_EP_2 */
+#define IFX_CIF_MIEP_ICR_FILL_EP_2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ICR_Bits.FILL_EP_2 */
+#define IFX_CIF_MIEP_ICR_FILL_EP_2_OFF (5u)
+
+/** \brief Length for Ifx_CIF_MIEP_ICR_Bits.FILL_EP_3 */
+#define IFX_CIF_MIEP_ICR_FILL_EP_3_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ICR_Bits.FILL_EP_3 */
+#define IFX_CIF_MIEP_ICR_FILL_EP_3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ICR_Bits.FILL_EP_3 */
+#define IFX_CIF_MIEP_ICR_FILL_EP_3_OFF (9u)
+
+/** \brief Length for Ifx_CIF_MIEP_ICR_Bits.FILL_EP_4 */
+#define IFX_CIF_MIEP_ICR_FILL_EP_4_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ICR_Bits.FILL_EP_4 */
+#define IFX_CIF_MIEP_ICR_FILL_EP_4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ICR_Bits.FILL_EP_4 */
+#define IFX_CIF_MIEP_ICR_FILL_EP_4_OFF (13u)
+
+/** \brief Length for Ifx_CIF_MIEP_ICR_Bits.FILL_EP_5 */
+#define IFX_CIF_MIEP_ICR_FILL_EP_5_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ICR_Bits.FILL_EP_5 */
+#define IFX_CIF_MIEP_ICR_FILL_EP_5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ICR_Bits.FILL_EP_5 */
+#define IFX_CIF_MIEP_ICR_FILL_EP_5_OFF (17u)
+
+/** \brief Length for Ifx_CIF_MIEP_ICR_Bits.FRAME_END_EP_1 */
+#define IFX_CIF_MIEP_ICR_FRAME_END_EP_1_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ICR_Bits.FRAME_END_EP_1 */
+#define IFX_CIF_MIEP_ICR_FRAME_END_EP_1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ICR_Bits.FRAME_END_EP_1 */
+#define IFX_CIF_MIEP_ICR_FRAME_END_EP_1_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MIEP_ICR_Bits.FRAME_END_EP_2 */
+#define IFX_CIF_MIEP_ICR_FRAME_END_EP_2_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ICR_Bits.FRAME_END_EP_2 */
+#define IFX_CIF_MIEP_ICR_FRAME_END_EP_2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ICR_Bits.FRAME_END_EP_2 */
+#define IFX_CIF_MIEP_ICR_FRAME_END_EP_2_OFF (4u)
+
+/** \brief Length for Ifx_CIF_MIEP_ICR_Bits.FRAME_END_EP_3 */
+#define IFX_CIF_MIEP_ICR_FRAME_END_EP_3_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ICR_Bits.FRAME_END_EP_3 */
+#define IFX_CIF_MIEP_ICR_FRAME_END_EP_3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ICR_Bits.FRAME_END_EP_3 */
+#define IFX_CIF_MIEP_ICR_FRAME_END_EP_3_OFF (8u)
+
+/** \brief Length for Ifx_CIF_MIEP_ICR_Bits.FRAME_END_EP_4 */
+#define IFX_CIF_MIEP_ICR_FRAME_END_EP_4_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ICR_Bits.FRAME_END_EP_4 */
+#define IFX_CIF_MIEP_ICR_FRAME_END_EP_4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ICR_Bits.FRAME_END_EP_4 */
+#define IFX_CIF_MIEP_ICR_FRAME_END_EP_4_OFF (12u)
+
+/** \brief Length for Ifx_CIF_MIEP_ICR_Bits.FRAME_END_EP_5 */
+#define IFX_CIF_MIEP_ICR_FRAME_END_EP_5_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ICR_Bits.FRAME_END_EP_5 */
+#define IFX_CIF_MIEP_ICR_FRAME_END_EP_5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ICR_Bits.FRAME_END_EP_5 */
+#define IFX_CIF_MIEP_ICR_FRAME_END_EP_5_OFF (16u)
+
+/** \brief Length for Ifx_CIF_MIEP_ICR_Bits.MBLK_LINE_EP_1 */
+#define IFX_CIF_MIEP_ICR_MBLK_LINE_EP_1_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ICR_Bits.MBLK_LINE_EP_1 */
+#define IFX_CIF_MIEP_ICR_MBLK_LINE_EP_1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ICR_Bits.MBLK_LINE_EP_1 */
+#define IFX_CIF_MIEP_ICR_MBLK_LINE_EP_1_OFF (3u)
+
+/** \brief Length for Ifx_CIF_MIEP_ICR_Bits.MBLK_LINE_EP_3 */
+#define IFX_CIF_MIEP_ICR_MBLK_LINE_EP_3_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ICR_Bits.MBLK_LINE_EP_3 */
+#define IFX_CIF_MIEP_ICR_MBLK_LINE_EP_3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ICR_Bits.MBLK_LINE_EP_3 */
+#define IFX_CIF_MIEP_ICR_MBLK_LINE_EP_3_OFF (11u)
+
+/** \brief Length for Ifx_CIF_MIEP_ICR_Bits.MBLK_LINE_EP_4 */
+#define IFX_CIF_MIEP_ICR_MBLK_LINE_EP_4_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ICR_Bits.MBLK_LINE_EP_4 */
+#define IFX_CIF_MIEP_ICR_MBLK_LINE_EP_4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ICR_Bits.MBLK_LINE_EP_4 */
+#define IFX_CIF_MIEP_ICR_MBLK_LINE_EP_4_OFF (15u)
+
+/** \brief Length for Ifx_CIF_MIEP_ICR_Bits.MBLK_LINE_EP_5 */
+#define IFX_CIF_MIEP_ICR_MBLK_LINE_EP_5_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ICR_Bits.MBLK_LINE_EP_5 */
+#define IFX_CIF_MIEP_ICR_MBLK_LINE_EP_5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ICR_Bits.MBLK_LINE_EP_5 */
+#define IFX_CIF_MIEP_ICR_MBLK_LINE_EP_5_OFF (19u)
+
+/** \brief Length for Ifx_CIF_MIEP_ICR_Bits.WRAP_EP_1 */
+#define IFX_CIF_MIEP_ICR_WRAP_EP_1_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ICR_Bits.WRAP_EP_1 */
+#define IFX_CIF_MIEP_ICR_WRAP_EP_1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ICR_Bits.WRAP_EP_1 */
+#define IFX_CIF_MIEP_ICR_WRAP_EP_1_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MIEP_ICR_Bits.WRAP_EP_2 */
+#define IFX_CIF_MIEP_ICR_WRAP_EP_2_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ICR_Bits.WRAP_EP_2 */
+#define IFX_CIF_MIEP_ICR_WRAP_EP_2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ICR_Bits.WRAP_EP_2 */
+#define IFX_CIF_MIEP_ICR_WRAP_EP_2_OFF (6u)
+
+/** \brief Length for Ifx_CIF_MIEP_ICR_Bits.WRAP_EP_3 */
+#define IFX_CIF_MIEP_ICR_WRAP_EP_3_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ICR_Bits.WRAP_EP_3 */
+#define IFX_CIF_MIEP_ICR_WRAP_EP_3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ICR_Bits.WRAP_EP_3 */
+#define IFX_CIF_MIEP_ICR_WRAP_EP_3_OFF (10u)
+
+/** \brief Length for Ifx_CIF_MIEP_ICR_Bits.WRAP_EP_4 */
+#define IFX_CIF_MIEP_ICR_WRAP_EP_4_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ICR_Bits.WRAP_EP_4 */
+#define IFX_CIF_MIEP_ICR_WRAP_EP_4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ICR_Bits.WRAP_EP_4 */
+#define IFX_CIF_MIEP_ICR_WRAP_EP_4_OFF (14u)
+
+/** \brief Length for Ifx_CIF_MIEP_ICR_Bits.WRAP_EP_5 */
+#define IFX_CIF_MIEP_ICR_WRAP_EP_5_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ICR_Bits.WRAP_EP_5 */
+#define IFX_CIF_MIEP_ICR_WRAP_EP_5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ICR_Bits.WRAP_EP_5 */
+#define IFX_CIF_MIEP_ICR_WRAP_EP_5_OFF (18u)
+
+/** \brief Length for Ifx_CIF_MIEP_IMSC_Bits.FILL_EP_1 */
+#define IFX_CIF_MIEP_IMSC_FILL_EP_1_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_IMSC_Bits.FILL_EP_1 */
+#define IFX_CIF_MIEP_IMSC_FILL_EP_1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_IMSC_Bits.FILL_EP_1 */
+#define IFX_CIF_MIEP_IMSC_FILL_EP_1_OFF (1u)
+
+/** \brief Length for Ifx_CIF_MIEP_IMSC_Bits.FILL_EP_2 */
+#define IFX_CIF_MIEP_IMSC_FILL_EP_2_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_IMSC_Bits.FILL_EP_2 */
+#define IFX_CIF_MIEP_IMSC_FILL_EP_2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_IMSC_Bits.FILL_EP_2 */
+#define IFX_CIF_MIEP_IMSC_FILL_EP_2_OFF (5u)
+
+/** \brief Length for Ifx_CIF_MIEP_IMSC_Bits.FILL_EP_3 */
+#define IFX_CIF_MIEP_IMSC_FILL_EP_3_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_IMSC_Bits.FILL_EP_3 */
+#define IFX_CIF_MIEP_IMSC_FILL_EP_3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_IMSC_Bits.FILL_EP_3 */
+#define IFX_CIF_MIEP_IMSC_FILL_EP_3_OFF (9u)
+
+/** \brief Length for Ifx_CIF_MIEP_IMSC_Bits.FILL_EP_4 */
+#define IFX_CIF_MIEP_IMSC_FILL_EP_4_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_IMSC_Bits.FILL_EP_4 */
+#define IFX_CIF_MIEP_IMSC_FILL_EP_4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_IMSC_Bits.FILL_EP_4 */
+#define IFX_CIF_MIEP_IMSC_FILL_EP_4_OFF (13u)
+
+/** \brief Length for Ifx_CIF_MIEP_IMSC_Bits.FILL_EP_5 */
+#define IFX_CIF_MIEP_IMSC_FILL_EP_5_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_IMSC_Bits.FILL_EP_5 */
+#define IFX_CIF_MIEP_IMSC_FILL_EP_5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_IMSC_Bits.FILL_EP_5 */
+#define IFX_CIF_MIEP_IMSC_FILL_EP_5_OFF (17u)
+
+/** \brief Length for Ifx_CIF_MIEP_IMSC_Bits.FRAME_END_EP_1 */
+#define IFX_CIF_MIEP_IMSC_FRAME_END_EP_1_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_IMSC_Bits.FRAME_END_EP_1 */
+#define IFX_CIF_MIEP_IMSC_FRAME_END_EP_1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_IMSC_Bits.FRAME_END_EP_1 */
+#define IFX_CIF_MIEP_IMSC_FRAME_END_EP_1_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MIEP_IMSC_Bits.FRAME_END_EP_2 */
+#define IFX_CIF_MIEP_IMSC_FRAME_END_EP_2_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_IMSC_Bits.FRAME_END_EP_2 */
+#define IFX_CIF_MIEP_IMSC_FRAME_END_EP_2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_IMSC_Bits.FRAME_END_EP_2 */
+#define IFX_CIF_MIEP_IMSC_FRAME_END_EP_2_OFF (4u)
+
+/** \brief Length for Ifx_CIF_MIEP_IMSC_Bits.FRAME_END_EP_3 */
+#define IFX_CIF_MIEP_IMSC_FRAME_END_EP_3_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_IMSC_Bits.FRAME_END_EP_3 */
+#define IFX_CIF_MIEP_IMSC_FRAME_END_EP_3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_IMSC_Bits.FRAME_END_EP_3 */
+#define IFX_CIF_MIEP_IMSC_FRAME_END_EP_3_OFF (8u)
+
+/** \brief Length for Ifx_CIF_MIEP_IMSC_Bits.FRAME_END_EP_4 */
+#define IFX_CIF_MIEP_IMSC_FRAME_END_EP_4_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_IMSC_Bits.FRAME_END_EP_4 */
+#define IFX_CIF_MIEP_IMSC_FRAME_END_EP_4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_IMSC_Bits.FRAME_END_EP_4 */
+#define IFX_CIF_MIEP_IMSC_FRAME_END_EP_4_OFF (12u)
+
+/** \brief Length for Ifx_CIF_MIEP_IMSC_Bits.FRAME_END_EP_5 */
+#define IFX_CIF_MIEP_IMSC_FRAME_END_EP_5_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_IMSC_Bits.FRAME_END_EP_5 */
+#define IFX_CIF_MIEP_IMSC_FRAME_END_EP_5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_IMSC_Bits.FRAME_END_EP_5 */
+#define IFX_CIF_MIEP_IMSC_FRAME_END_EP_5_OFF (16u)
+
+/** \brief Length for Ifx_CIF_MIEP_IMSC_Bits.MBLK_LINE_EP_1 */
+#define IFX_CIF_MIEP_IMSC_MBLK_LINE_EP_1_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_IMSC_Bits.MBLK_LINE_EP_1 */
+#define IFX_CIF_MIEP_IMSC_MBLK_LINE_EP_1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_IMSC_Bits.MBLK_LINE_EP_1 */
+#define IFX_CIF_MIEP_IMSC_MBLK_LINE_EP_1_OFF (3u)
+
+/** \brief Length for Ifx_CIF_MIEP_IMSC_Bits.MBLK_LINE_EP_2 */
+#define IFX_CIF_MIEP_IMSC_MBLK_LINE_EP_2_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_IMSC_Bits.MBLK_LINE_EP_2 */
+#define IFX_CIF_MIEP_IMSC_MBLK_LINE_EP_2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_IMSC_Bits.MBLK_LINE_EP_2 */
+#define IFX_CIF_MIEP_IMSC_MBLK_LINE_EP_2_OFF (7u)
+
+/** \brief Length for Ifx_CIF_MIEP_IMSC_Bits.MBLK_LINE_EP_3 */
+#define IFX_CIF_MIEP_IMSC_MBLK_LINE_EP_3_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_IMSC_Bits.MBLK_LINE_EP_3 */
+#define IFX_CIF_MIEP_IMSC_MBLK_LINE_EP_3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_IMSC_Bits.MBLK_LINE_EP_3 */
+#define IFX_CIF_MIEP_IMSC_MBLK_LINE_EP_3_OFF (11u)
+
+/** \brief Length for Ifx_CIF_MIEP_IMSC_Bits.MBLK_LINE_EP_4 */
+#define IFX_CIF_MIEP_IMSC_MBLK_LINE_EP_4_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_IMSC_Bits.MBLK_LINE_EP_4 */
+#define IFX_CIF_MIEP_IMSC_MBLK_LINE_EP_4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_IMSC_Bits.MBLK_LINE_EP_4 */
+#define IFX_CIF_MIEP_IMSC_MBLK_LINE_EP_4_OFF (15u)
+
+/** \brief Length for Ifx_CIF_MIEP_IMSC_Bits.MBLK_LINE_EP_5 */
+#define IFX_CIF_MIEP_IMSC_MBLK_LINE_EP_5_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_IMSC_Bits.MBLK_LINE_EP_5 */
+#define IFX_CIF_MIEP_IMSC_MBLK_LINE_EP_5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_IMSC_Bits.MBLK_LINE_EP_5 */
+#define IFX_CIF_MIEP_IMSC_MBLK_LINE_EP_5_OFF (19u)
+
+/** \brief Length for Ifx_CIF_MIEP_IMSC_Bits.WRAP_EP_1 */
+#define IFX_CIF_MIEP_IMSC_WRAP_EP_1_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_IMSC_Bits.WRAP_EP_1 */
+#define IFX_CIF_MIEP_IMSC_WRAP_EP_1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_IMSC_Bits.WRAP_EP_1 */
+#define IFX_CIF_MIEP_IMSC_WRAP_EP_1_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MIEP_IMSC_Bits.WRAP_EP_2 */
+#define IFX_CIF_MIEP_IMSC_WRAP_EP_2_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_IMSC_Bits.WRAP_EP_2 */
+#define IFX_CIF_MIEP_IMSC_WRAP_EP_2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_IMSC_Bits.WRAP_EP_2 */
+#define IFX_CIF_MIEP_IMSC_WRAP_EP_2_OFF (6u)
+
+/** \brief Length for Ifx_CIF_MIEP_IMSC_Bits.WRAP_EP_3 */
+#define IFX_CIF_MIEP_IMSC_WRAP_EP_3_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_IMSC_Bits.WRAP_EP_3 */
+#define IFX_CIF_MIEP_IMSC_WRAP_EP_3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_IMSC_Bits.WRAP_EP_3 */
+#define IFX_CIF_MIEP_IMSC_WRAP_EP_3_OFF (10u)
+
+/** \brief Length for Ifx_CIF_MIEP_IMSC_Bits.WRAP_EP_4 */
+#define IFX_CIF_MIEP_IMSC_WRAP_EP_4_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_IMSC_Bits.WRAP_EP_4 */
+#define IFX_CIF_MIEP_IMSC_WRAP_EP_4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_IMSC_Bits.WRAP_EP_4 */
+#define IFX_CIF_MIEP_IMSC_WRAP_EP_4_OFF (14u)
+
+/** \brief Length for Ifx_CIF_MIEP_IMSC_Bits.WRAP_EP_5 */
+#define IFX_CIF_MIEP_IMSC_WRAP_EP_5_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_IMSC_Bits.WRAP_EP_5 */
+#define IFX_CIF_MIEP_IMSC_WRAP_EP_5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_IMSC_Bits.WRAP_EP_5 */
+#define IFX_CIF_MIEP_IMSC_WRAP_EP_5_OFF (18u)
+
+/** \brief Length for Ifx_CIF_MIEP_ISR_Bits.FILL_EP_1 */
+#define IFX_CIF_MIEP_ISR_FILL_EP_1_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ISR_Bits.FILL_EP_1 */
+#define IFX_CIF_MIEP_ISR_FILL_EP_1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ISR_Bits.FILL_EP_1 */
+#define IFX_CIF_MIEP_ISR_FILL_EP_1_OFF (1u)
+
+/** \brief Length for Ifx_CIF_MIEP_ISR_Bits.FILL_EP_2 */
+#define IFX_CIF_MIEP_ISR_FILL_EP_2_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ISR_Bits.FILL_EP_2 */
+#define IFX_CIF_MIEP_ISR_FILL_EP_2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ISR_Bits.FILL_EP_2 */
+#define IFX_CIF_MIEP_ISR_FILL_EP_2_OFF (5u)
+
+/** \brief Length for Ifx_CIF_MIEP_ISR_Bits.FILL_EP_3 */
+#define IFX_CIF_MIEP_ISR_FILL_EP_3_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ISR_Bits.FILL_EP_3 */
+#define IFX_CIF_MIEP_ISR_FILL_EP_3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ISR_Bits.FILL_EP_3 */
+#define IFX_CIF_MIEP_ISR_FILL_EP_3_OFF (9u)
+
+/** \brief Length for Ifx_CIF_MIEP_ISR_Bits.FILL_EP_4 */
+#define IFX_CIF_MIEP_ISR_FILL_EP_4_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ISR_Bits.FILL_EP_4 */
+#define IFX_CIF_MIEP_ISR_FILL_EP_4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ISR_Bits.FILL_EP_4 */
+#define IFX_CIF_MIEP_ISR_FILL_EP_4_OFF (13u)
+
+/** \brief Length for Ifx_CIF_MIEP_ISR_Bits.FILL_EP_5 */
+#define IFX_CIF_MIEP_ISR_FILL_EP_5_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ISR_Bits.FILL_EP_5 */
+#define IFX_CIF_MIEP_ISR_FILL_EP_5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ISR_Bits.FILL_EP_5 */
+#define IFX_CIF_MIEP_ISR_FILL_EP_5_OFF (17u)
+
+/** \brief Length for Ifx_CIF_MIEP_ISR_Bits.FRAME_END_EP_1 */
+#define IFX_CIF_MIEP_ISR_FRAME_END_EP_1_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ISR_Bits.FRAME_END_EP_1 */
+#define IFX_CIF_MIEP_ISR_FRAME_END_EP_1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ISR_Bits.FRAME_END_EP_1 */
+#define IFX_CIF_MIEP_ISR_FRAME_END_EP_1_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MIEP_ISR_Bits.FRAME_END_EP_2 */
+#define IFX_CIF_MIEP_ISR_FRAME_END_EP_2_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ISR_Bits.FRAME_END_EP_2 */
+#define IFX_CIF_MIEP_ISR_FRAME_END_EP_2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ISR_Bits.FRAME_END_EP_2 */
+#define IFX_CIF_MIEP_ISR_FRAME_END_EP_2_OFF (4u)
+
+/** \brief Length for Ifx_CIF_MIEP_ISR_Bits.FRAME_END_EP_3 */
+#define IFX_CIF_MIEP_ISR_FRAME_END_EP_3_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ISR_Bits.FRAME_END_EP_3 */
+#define IFX_CIF_MIEP_ISR_FRAME_END_EP_3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ISR_Bits.FRAME_END_EP_3 */
+#define IFX_CIF_MIEP_ISR_FRAME_END_EP_3_OFF (8u)
+
+/** \brief Length for Ifx_CIF_MIEP_ISR_Bits.FRAME_END_EP_4 */
+#define IFX_CIF_MIEP_ISR_FRAME_END_EP_4_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ISR_Bits.FRAME_END_EP_4 */
+#define IFX_CIF_MIEP_ISR_FRAME_END_EP_4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ISR_Bits.FRAME_END_EP_4 */
+#define IFX_CIF_MIEP_ISR_FRAME_END_EP_4_OFF (12u)
+
+/** \brief Length for Ifx_CIF_MIEP_ISR_Bits.FRAME_END_EP_5 */
+#define IFX_CIF_MIEP_ISR_FRAME_END_EP_5_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ISR_Bits.FRAME_END_EP_5 */
+#define IFX_CIF_MIEP_ISR_FRAME_END_EP_5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ISR_Bits.FRAME_END_EP_5 */
+#define IFX_CIF_MIEP_ISR_FRAME_END_EP_5_OFF (16u)
+
+/** \brief Length for Ifx_CIF_MIEP_ISR_Bits.MBLK_LINE_EP_1 */
+#define IFX_CIF_MIEP_ISR_MBLK_LINE_EP_1_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ISR_Bits.MBLK_LINE_EP_1 */
+#define IFX_CIF_MIEP_ISR_MBLK_LINE_EP_1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ISR_Bits.MBLK_LINE_EP_1 */
+#define IFX_CIF_MIEP_ISR_MBLK_LINE_EP_1_OFF (3u)
+
+/** \brief Length for Ifx_CIF_MIEP_ISR_Bits.MBLK_LINE_EP_2 */
+#define IFX_CIF_MIEP_ISR_MBLK_LINE_EP_2_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ISR_Bits.MBLK_LINE_EP_2 */
+#define IFX_CIF_MIEP_ISR_MBLK_LINE_EP_2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ISR_Bits.MBLK_LINE_EP_2 */
+#define IFX_CIF_MIEP_ISR_MBLK_LINE_EP_2_OFF (7u)
+
+/** \brief Length for Ifx_CIF_MIEP_ISR_Bits.MBLK_LINE_EP_3 */
+#define IFX_CIF_MIEP_ISR_MBLK_LINE_EP_3_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ISR_Bits.MBLK_LINE_EP_3 */
+#define IFX_CIF_MIEP_ISR_MBLK_LINE_EP_3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ISR_Bits.MBLK_LINE_EP_3 */
+#define IFX_CIF_MIEP_ISR_MBLK_LINE_EP_3_OFF (11u)
+
+/** \brief Length for Ifx_CIF_MIEP_ISR_Bits.MBLK_LINE_EP_4 */
+#define IFX_CIF_MIEP_ISR_MBLK_LINE_EP_4_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ISR_Bits.MBLK_LINE_EP_4 */
+#define IFX_CIF_MIEP_ISR_MBLK_LINE_EP_4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ISR_Bits.MBLK_LINE_EP_4 */
+#define IFX_CIF_MIEP_ISR_MBLK_LINE_EP_4_OFF (15u)
+
+/** \brief Length for Ifx_CIF_MIEP_ISR_Bits.MBLK_LINE_EP_5 */
+#define IFX_CIF_MIEP_ISR_MBLK_LINE_EP_5_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ISR_Bits.MBLK_LINE_EP_5 */
+#define IFX_CIF_MIEP_ISR_MBLK_LINE_EP_5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ISR_Bits.MBLK_LINE_EP_5 */
+#define IFX_CIF_MIEP_ISR_MBLK_LINE_EP_5_OFF (19u)
+
+/** \brief Length for Ifx_CIF_MIEP_ISR_Bits.WRAP_EP_1 */
+#define IFX_CIF_MIEP_ISR_WRAP_EP_1_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ISR_Bits.WRAP_EP_1 */
+#define IFX_CIF_MIEP_ISR_WRAP_EP_1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ISR_Bits.WRAP_EP_1 */
+#define IFX_CIF_MIEP_ISR_WRAP_EP_1_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MIEP_ISR_Bits.WRAP_EP_2 */
+#define IFX_CIF_MIEP_ISR_WRAP_EP_2_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ISR_Bits.WRAP_EP_2 */
+#define IFX_CIF_MIEP_ISR_WRAP_EP_2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ISR_Bits.WRAP_EP_2 */
+#define IFX_CIF_MIEP_ISR_WRAP_EP_2_OFF (6u)
+
+/** \brief Length for Ifx_CIF_MIEP_ISR_Bits.WRAP_EP_3 */
+#define IFX_CIF_MIEP_ISR_WRAP_EP_3_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ISR_Bits.WRAP_EP_3 */
+#define IFX_CIF_MIEP_ISR_WRAP_EP_3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ISR_Bits.WRAP_EP_3 */
+#define IFX_CIF_MIEP_ISR_WRAP_EP_3_OFF (10u)
+
+/** \brief Length for Ifx_CIF_MIEP_ISR_Bits.WRAP_EP_4 */
+#define IFX_CIF_MIEP_ISR_WRAP_EP_4_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ISR_Bits.WRAP_EP_4 */
+#define IFX_CIF_MIEP_ISR_WRAP_EP_4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ISR_Bits.WRAP_EP_4 */
+#define IFX_CIF_MIEP_ISR_WRAP_EP_4_OFF (14u)
+
+/** \brief Length for Ifx_CIF_MIEP_ISR_Bits.WRAP_EP_5 */
+#define IFX_CIF_MIEP_ISR_WRAP_EP_5_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_ISR_Bits.WRAP_EP_5 */
+#define IFX_CIF_MIEP_ISR_WRAP_EP_5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_ISR_Bits.WRAP_EP_5 */
+#define IFX_CIF_MIEP_ISR_WRAP_EP_5_OFF (18u)
+
+/** \brief Length for Ifx_CIF_MIEP_MIS_Bits.FILL_EP_1 */
+#define IFX_CIF_MIEP_MIS_FILL_EP_1_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_MIS_Bits.FILL_EP_1 */
+#define IFX_CIF_MIEP_MIS_FILL_EP_1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_MIS_Bits.FILL_EP_1 */
+#define IFX_CIF_MIEP_MIS_FILL_EP_1_OFF (1u)
+
+/** \brief Length for Ifx_CIF_MIEP_MIS_Bits.FILL_EP_2 */
+#define IFX_CIF_MIEP_MIS_FILL_EP_2_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_MIS_Bits.FILL_EP_2 */
+#define IFX_CIF_MIEP_MIS_FILL_EP_2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_MIS_Bits.FILL_EP_2 */
+#define IFX_CIF_MIEP_MIS_FILL_EP_2_OFF (5u)
+
+/** \brief Length for Ifx_CIF_MIEP_MIS_Bits.FILL_EP_3 */
+#define IFX_CIF_MIEP_MIS_FILL_EP_3_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_MIS_Bits.FILL_EP_3 */
+#define IFX_CIF_MIEP_MIS_FILL_EP_3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_MIS_Bits.FILL_EP_3 */
+#define IFX_CIF_MIEP_MIS_FILL_EP_3_OFF (9u)
+
+/** \brief Length for Ifx_CIF_MIEP_MIS_Bits.FILL_EP_4 */
+#define IFX_CIF_MIEP_MIS_FILL_EP_4_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_MIS_Bits.FILL_EP_4 */
+#define IFX_CIF_MIEP_MIS_FILL_EP_4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_MIS_Bits.FILL_EP_4 */
+#define IFX_CIF_MIEP_MIS_FILL_EP_4_OFF (13u)
+
+/** \brief Length for Ifx_CIF_MIEP_MIS_Bits.FILL_EP_5 */
+#define IFX_CIF_MIEP_MIS_FILL_EP_5_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_MIS_Bits.FILL_EP_5 */
+#define IFX_CIF_MIEP_MIS_FILL_EP_5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_MIS_Bits.FILL_EP_5 */
+#define IFX_CIF_MIEP_MIS_FILL_EP_5_OFF (17u)
+
+/** \brief Length for Ifx_CIF_MIEP_MIS_Bits.FRAME_END_EP_1 */
+#define IFX_CIF_MIEP_MIS_FRAME_END_EP_1_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_MIS_Bits.FRAME_END_EP_1 */
+#define IFX_CIF_MIEP_MIS_FRAME_END_EP_1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_MIS_Bits.FRAME_END_EP_1 */
+#define IFX_CIF_MIEP_MIS_FRAME_END_EP_1_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MIEP_MIS_Bits.FRAME_END_EP_2 */
+#define IFX_CIF_MIEP_MIS_FRAME_END_EP_2_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_MIS_Bits.FRAME_END_EP_2 */
+#define IFX_CIF_MIEP_MIS_FRAME_END_EP_2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_MIS_Bits.FRAME_END_EP_2 */
+#define IFX_CIF_MIEP_MIS_FRAME_END_EP_2_OFF (4u)
+
+/** \brief Length for Ifx_CIF_MIEP_MIS_Bits.FRAME_END_EP_3 */
+#define IFX_CIF_MIEP_MIS_FRAME_END_EP_3_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_MIS_Bits.FRAME_END_EP_3 */
+#define IFX_CIF_MIEP_MIS_FRAME_END_EP_3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_MIS_Bits.FRAME_END_EP_3 */
+#define IFX_CIF_MIEP_MIS_FRAME_END_EP_3_OFF (8u)
+
+/** \brief Length for Ifx_CIF_MIEP_MIS_Bits.FRAME_END_EP_4 */
+#define IFX_CIF_MIEP_MIS_FRAME_END_EP_4_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_MIS_Bits.FRAME_END_EP_4 */
+#define IFX_CIF_MIEP_MIS_FRAME_END_EP_4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_MIS_Bits.FRAME_END_EP_4 */
+#define IFX_CIF_MIEP_MIS_FRAME_END_EP_4_OFF (12u)
+
+/** \brief Length for Ifx_CIF_MIEP_MIS_Bits.FRAME_END_EP_5 */
+#define IFX_CIF_MIEP_MIS_FRAME_END_EP_5_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_MIS_Bits.FRAME_END_EP_5 */
+#define IFX_CIF_MIEP_MIS_FRAME_END_EP_5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_MIS_Bits.FRAME_END_EP_5 */
+#define IFX_CIF_MIEP_MIS_FRAME_END_EP_5_OFF (16u)
+
+/** \brief Length for Ifx_CIF_MIEP_MIS_Bits.MBLK_LINE_EP_1 */
+#define IFX_CIF_MIEP_MIS_MBLK_LINE_EP_1_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_MIS_Bits.MBLK_LINE_EP_1 */
+#define IFX_CIF_MIEP_MIS_MBLK_LINE_EP_1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_MIS_Bits.MBLK_LINE_EP_1 */
+#define IFX_CIF_MIEP_MIS_MBLK_LINE_EP_1_OFF (3u)
+
+/** \brief Length for Ifx_CIF_MIEP_MIS_Bits.MBLK_LINE_EP_2 */
+#define IFX_CIF_MIEP_MIS_MBLK_LINE_EP_2_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_MIS_Bits.MBLK_LINE_EP_2 */
+#define IFX_CIF_MIEP_MIS_MBLK_LINE_EP_2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_MIS_Bits.MBLK_LINE_EP_2 */
+#define IFX_CIF_MIEP_MIS_MBLK_LINE_EP_2_OFF (7u)
+
+/** \brief Length for Ifx_CIF_MIEP_MIS_Bits.MBLK_LINE_EP_3 */
+#define IFX_CIF_MIEP_MIS_MBLK_LINE_EP_3_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_MIS_Bits.MBLK_LINE_EP_3 */
+#define IFX_CIF_MIEP_MIS_MBLK_LINE_EP_3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_MIS_Bits.MBLK_LINE_EP_3 */
+#define IFX_CIF_MIEP_MIS_MBLK_LINE_EP_3_OFF (11u)
+
+/** \brief Length for Ifx_CIF_MIEP_MIS_Bits.MBLK_LINE_EP_4 */
+#define IFX_CIF_MIEP_MIS_MBLK_LINE_EP_4_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_MIS_Bits.MBLK_LINE_EP_4 */
+#define IFX_CIF_MIEP_MIS_MBLK_LINE_EP_4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_MIS_Bits.MBLK_LINE_EP_4 */
+#define IFX_CIF_MIEP_MIS_MBLK_LINE_EP_4_OFF (15u)
+
+/** \brief Length for Ifx_CIF_MIEP_MIS_Bits.MBLK_LINE_EP_5 */
+#define IFX_CIF_MIEP_MIS_MBLK_LINE_EP_5_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_MIS_Bits.MBLK_LINE_EP_5 */
+#define IFX_CIF_MIEP_MIS_MBLK_LINE_EP_5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_MIS_Bits.MBLK_LINE_EP_5 */
+#define IFX_CIF_MIEP_MIS_MBLK_LINE_EP_5_OFF (19u)
+
+/** \brief Length for Ifx_CIF_MIEP_MIS_Bits.WRAP_EP_1 */
+#define IFX_CIF_MIEP_MIS_WRAP_EP_1_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_MIS_Bits.WRAP_EP_1 */
+#define IFX_CIF_MIEP_MIS_WRAP_EP_1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_MIS_Bits.WRAP_EP_1 */
+#define IFX_CIF_MIEP_MIS_WRAP_EP_1_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MIEP_MIS_Bits.WRAP_EP_2 */
+#define IFX_CIF_MIEP_MIS_WRAP_EP_2_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_MIS_Bits.WRAP_EP_2 */
+#define IFX_CIF_MIEP_MIS_WRAP_EP_2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_MIS_Bits.WRAP_EP_2 */
+#define IFX_CIF_MIEP_MIS_WRAP_EP_2_OFF (6u)
+
+/** \brief Length for Ifx_CIF_MIEP_MIS_Bits.WRAP_EP_3 */
+#define IFX_CIF_MIEP_MIS_WRAP_EP_3_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_MIS_Bits.WRAP_EP_3 */
+#define IFX_CIF_MIEP_MIS_WRAP_EP_3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_MIS_Bits.WRAP_EP_3 */
+#define IFX_CIF_MIEP_MIS_WRAP_EP_3_OFF (10u)
+
+/** \brief Length for Ifx_CIF_MIEP_MIS_Bits.WRAP_EP_4 */
+#define IFX_CIF_MIEP_MIS_WRAP_EP_4_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_MIS_Bits.WRAP_EP_4 */
+#define IFX_CIF_MIEP_MIS_WRAP_EP_4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_MIS_Bits.WRAP_EP_4 */
+#define IFX_CIF_MIEP_MIS_WRAP_EP_4_OFF (14u)
+
+/** \brief Length for Ifx_CIF_MIEP_MIS_Bits.WRAP_EP_5 */
+#define IFX_CIF_MIEP_MIS_WRAP_EP_5_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_MIS_Bits.WRAP_EP_5 */
+#define IFX_CIF_MIEP_MIS_WRAP_EP_5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_MIS_Bits.WRAP_EP_5 */
+#define IFX_CIF_MIEP_MIS_WRAP_EP_5_OFF (18u)
+
+/** \brief Length for Ifx_CIF_MIEP_RIS_Bits.FILL_EP_1 */
+#define IFX_CIF_MIEP_RIS_FILL_EP_1_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_RIS_Bits.FILL_EP_1 */
+#define IFX_CIF_MIEP_RIS_FILL_EP_1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_RIS_Bits.FILL_EP_1 */
+#define IFX_CIF_MIEP_RIS_FILL_EP_1_OFF (1u)
+
+/** \brief Length for Ifx_CIF_MIEP_RIS_Bits.FILL_EP_2 */
+#define IFX_CIF_MIEP_RIS_FILL_EP_2_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_RIS_Bits.FILL_EP_2 */
+#define IFX_CIF_MIEP_RIS_FILL_EP_2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_RIS_Bits.FILL_EP_2 */
+#define IFX_CIF_MIEP_RIS_FILL_EP_2_OFF (5u)
+
+/** \brief Length for Ifx_CIF_MIEP_RIS_Bits.FILL_EP_3 */
+#define IFX_CIF_MIEP_RIS_FILL_EP_3_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_RIS_Bits.FILL_EP_3 */
+#define IFX_CIF_MIEP_RIS_FILL_EP_3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_RIS_Bits.FILL_EP_3 */
+#define IFX_CIF_MIEP_RIS_FILL_EP_3_OFF (9u)
+
+/** \brief Length for Ifx_CIF_MIEP_RIS_Bits.FILL_EP_4 */
+#define IFX_CIF_MIEP_RIS_FILL_EP_4_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_RIS_Bits.FILL_EP_4 */
+#define IFX_CIF_MIEP_RIS_FILL_EP_4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_RIS_Bits.FILL_EP_4 */
+#define IFX_CIF_MIEP_RIS_FILL_EP_4_OFF (13u)
+
+/** \brief Length for Ifx_CIF_MIEP_RIS_Bits.FILL_EP_5 */
+#define IFX_CIF_MIEP_RIS_FILL_EP_5_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_RIS_Bits.FILL_EP_5 */
+#define IFX_CIF_MIEP_RIS_FILL_EP_5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_RIS_Bits.FILL_EP_5 */
+#define IFX_CIF_MIEP_RIS_FILL_EP_5_OFF (17u)
+
+/** \brief Length for Ifx_CIF_MIEP_RIS_Bits.FRAME_END_EP_1 */
+#define IFX_CIF_MIEP_RIS_FRAME_END_EP_1_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_RIS_Bits.FRAME_END_EP_1 */
+#define IFX_CIF_MIEP_RIS_FRAME_END_EP_1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_RIS_Bits.FRAME_END_EP_1 */
+#define IFX_CIF_MIEP_RIS_FRAME_END_EP_1_OFF (0u)
+
+/** \brief Length for Ifx_CIF_MIEP_RIS_Bits.FRAME_END_EP_2 */
+#define IFX_CIF_MIEP_RIS_FRAME_END_EP_2_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_RIS_Bits.FRAME_END_EP_2 */
+#define IFX_CIF_MIEP_RIS_FRAME_END_EP_2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_RIS_Bits.FRAME_END_EP_2 */
+#define IFX_CIF_MIEP_RIS_FRAME_END_EP_2_OFF (4u)
+
+/** \brief Length for Ifx_CIF_MIEP_RIS_Bits.FRAME_END_EP_3 */
+#define IFX_CIF_MIEP_RIS_FRAME_END_EP_3_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_RIS_Bits.FRAME_END_EP_3 */
+#define IFX_CIF_MIEP_RIS_FRAME_END_EP_3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_RIS_Bits.FRAME_END_EP_3 */
+#define IFX_CIF_MIEP_RIS_FRAME_END_EP_3_OFF (8u)
+
+/** \brief Length for Ifx_CIF_MIEP_RIS_Bits.FRAME_END_EP_4 */
+#define IFX_CIF_MIEP_RIS_FRAME_END_EP_4_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_RIS_Bits.FRAME_END_EP_4 */
+#define IFX_CIF_MIEP_RIS_FRAME_END_EP_4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_RIS_Bits.FRAME_END_EP_4 */
+#define IFX_CIF_MIEP_RIS_FRAME_END_EP_4_OFF (12u)
+
+/** \brief Length for Ifx_CIF_MIEP_RIS_Bits.FRAME_END_EP_5 */
+#define IFX_CIF_MIEP_RIS_FRAME_END_EP_5_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_RIS_Bits.FRAME_END_EP_5 */
+#define IFX_CIF_MIEP_RIS_FRAME_END_EP_5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_RIS_Bits.FRAME_END_EP_5 */
+#define IFX_CIF_MIEP_RIS_FRAME_END_EP_5_OFF (16u)
+
+/** \brief Length for Ifx_CIF_MIEP_RIS_Bits.MBLK_LINE_EP_1 */
+#define IFX_CIF_MIEP_RIS_MBLK_LINE_EP_1_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_RIS_Bits.MBLK_LINE_EP_1 */
+#define IFX_CIF_MIEP_RIS_MBLK_LINE_EP_1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_RIS_Bits.MBLK_LINE_EP_1 */
+#define IFX_CIF_MIEP_RIS_MBLK_LINE_EP_1_OFF (3u)
+
+/** \brief Length for Ifx_CIF_MIEP_RIS_Bits.MBLK_LINE_EP_2 */
+#define IFX_CIF_MIEP_RIS_MBLK_LINE_EP_2_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_RIS_Bits.MBLK_LINE_EP_2 */
+#define IFX_CIF_MIEP_RIS_MBLK_LINE_EP_2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_RIS_Bits.MBLK_LINE_EP_2 */
+#define IFX_CIF_MIEP_RIS_MBLK_LINE_EP_2_OFF (7u)
+
+/** \brief Length for Ifx_CIF_MIEP_RIS_Bits.MBLK_LINE_EP_3 */
+#define IFX_CIF_MIEP_RIS_MBLK_LINE_EP_3_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_RIS_Bits.MBLK_LINE_EP_3 */
+#define IFX_CIF_MIEP_RIS_MBLK_LINE_EP_3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_RIS_Bits.MBLK_LINE_EP_3 */
+#define IFX_CIF_MIEP_RIS_MBLK_LINE_EP_3_OFF (11u)
+
+/** \brief Length for Ifx_CIF_MIEP_RIS_Bits.MBLK_LINE_EP_4 */
+#define IFX_CIF_MIEP_RIS_MBLK_LINE_EP_4_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_RIS_Bits.MBLK_LINE_EP_4 */
+#define IFX_CIF_MIEP_RIS_MBLK_LINE_EP_4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_RIS_Bits.MBLK_LINE_EP_4 */
+#define IFX_CIF_MIEP_RIS_MBLK_LINE_EP_4_OFF (15u)
+
+/** \brief Length for Ifx_CIF_MIEP_RIS_Bits.MBLK_LINE_EP_5 */
+#define IFX_CIF_MIEP_RIS_MBLK_LINE_EP_5_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_RIS_Bits.MBLK_LINE_EP_5 */
+#define IFX_CIF_MIEP_RIS_MBLK_LINE_EP_5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_RIS_Bits.MBLK_LINE_EP_5 */
+#define IFX_CIF_MIEP_RIS_MBLK_LINE_EP_5_OFF (19u)
+
+/** \brief Length for Ifx_CIF_MIEP_RIS_Bits.WRAP_EP_1 */
+#define IFX_CIF_MIEP_RIS_WRAP_EP_1_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_RIS_Bits.WRAP_EP_1 */
+#define IFX_CIF_MIEP_RIS_WRAP_EP_1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_RIS_Bits.WRAP_EP_1 */
+#define IFX_CIF_MIEP_RIS_WRAP_EP_1_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MIEP_RIS_Bits.WRAP_EP_2 */
+#define IFX_CIF_MIEP_RIS_WRAP_EP_2_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_RIS_Bits.WRAP_EP_2 */
+#define IFX_CIF_MIEP_RIS_WRAP_EP_2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_RIS_Bits.WRAP_EP_2 */
+#define IFX_CIF_MIEP_RIS_WRAP_EP_2_OFF (6u)
+
+/** \brief Length for Ifx_CIF_MIEP_RIS_Bits.WRAP_EP_3 */
+#define IFX_CIF_MIEP_RIS_WRAP_EP_3_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_RIS_Bits.WRAP_EP_3 */
+#define IFX_CIF_MIEP_RIS_WRAP_EP_3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_RIS_Bits.WRAP_EP_3 */
+#define IFX_CIF_MIEP_RIS_WRAP_EP_3_OFF (10u)
+
+/** \brief Length for Ifx_CIF_MIEP_RIS_Bits.WRAP_EP_4 */
+#define IFX_CIF_MIEP_RIS_WRAP_EP_4_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_RIS_Bits.WRAP_EP_4 */
+#define IFX_CIF_MIEP_RIS_WRAP_EP_4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_RIS_Bits.WRAP_EP_4 */
+#define IFX_CIF_MIEP_RIS_WRAP_EP_4_OFF (14u)
+
+/** \brief Length for Ifx_CIF_MIEP_RIS_Bits.WRAP_EP_5 */
+#define IFX_CIF_MIEP_RIS_WRAP_EP_5_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_RIS_Bits.WRAP_EP_5 */
+#define IFX_CIF_MIEP_RIS_WRAP_EP_5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_RIS_Bits.WRAP_EP_5 */
+#define IFX_CIF_MIEP_RIS_WRAP_EP_5_OFF (18u)
+
+/** \brief Length for Ifx_CIF_MIEP_STA_ERR_CLR_Bits.EP_1_IC_SIZE_ERR_CLR */
+#define IFX_CIF_MIEP_STA_ERR_CLR_EP_1_IC_SIZE_ERR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_STA_ERR_CLR_Bits.EP_1_IC_SIZE_ERR_CLR */
+#define IFX_CIF_MIEP_STA_ERR_CLR_EP_1_IC_SIZE_ERR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_STA_ERR_CLR_Bits.EP_1_IC_SIZE_ERR_CLR */
+#define IFX_CIF_MIEP_STA_ERR_CLR_EP_1_IC_SIZE_ERR_CLR_OFF (1u)
+
+/** \brief Length for Ifx_CIF_MIEP_STA_ERR_CLR_Bits.EP_2_IC_SIZE_ERR_CLR */
+#define IFX_CIF_MIEP_STA_ERR_CLR_EP_2_IC_SIZE_ERR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_STA_ERR_CLR_Bits.EP_2_IC_SIZE_ERR_CLR */
+#define IFX_CIF_MIEP_STA_ERR_CLR_EP_2_IC_SIZE_ERR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_STA_ERR_CLR_Bits.EP_2_IC_SIZE_ERR_CLR */
+#define IFX_CIF_MIEP_STA_ERR_CLR_EP_2_IC_SIZE_ERR_CLR_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MIEP_STA_ERR_CLR_Bits.EP_3_IC_SIZE_ERR_CLR */
+#define IFX_CIF_MIEP_STA_ERR_CLR_EP_3_IC_SIZE_ERR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_STA_ERR_CLR_Bits.EP_3_IC_SIZE_ERR_CLR */
+#define IFX_CIF_MIEP_STA_ERR_CLR_EP_3_IC_SIZE_ERR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_STA_ERR_CLR_Bits.EP_3_IC_SIZE_ERR_CLR */
+#define IFX_CIF_MIEP_STA_ERR_CLR_EP_3_IC_SIZE_ERR_CLR_OFF (3u)
+
+/** \brief Length for Ifx_CIF_MIEP_STA_ERR_CLR_Bits.EP_4_IC_SIZE_ERR_CLR */
+#define IFX_CIF_MIEP_STA_ERR_CLR_EP_4_IC_SIZE_ERR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_STA_ERR_CLR_Bits.EP_4_IC_SIZE_ERR_CLR */
+#define IFX_CIF_MIEP_STA_ERR_CLR_EP_4_IC_SIZE_ERR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_STA_ERR_CLR_Bits.EP_4_IC_SIZE_ERR_CLR */
+#define IFX_CIF_MIEP_STA_ERR_CLR_EP_4_IC_SIZE_ERR_CLR_OFF (4u)
+
+/** \brief Length for Ifx_CIF_MIEP_STA_ERR_CLR_Bits.EP_5_IC_SIZE_ERR_CLR */
+#define IFX_CIF_MIEP_STA_ERR_CLR_EP_5_IC_SIZE_ERR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_STA_ERR_CLR_Bits.EP_5_IC_SIZE_ERR_CLR */
+#define IFX_CIF_MIEP_STA_ERR_CLR_EP_5_IC_SIZE_ERR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_STA_ERR_CLR_Bits.EP_5_IC_SIZE_ERR_CLR */
+#define IFX_CIF_MIEP_STA_ERR_CLR_EP_5_IC_SIZE_ERR_CLR_OFF (5u)
+
+/** \brief Length for Ifx_CIF_MIEP_STA_ERR_Bits.EP_1_FIFO_FULL */
+#define IFX_CIF_MIEP_STA_ERR_EP_1_FIFO_FULL_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_STA_ERR_Bits.EP_1_FIFO_FULL */
+#define IFX_CIF_MIEP_STA_ERR_EP_1_FIFO_FULL_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_STA_ERR_Bits.EP_1_FIFO_FULL */
+#define IFX_CIF_MIEP_STA_ERR_EP_1_FIFO_FULL_OFF (17u)
+
+/** \brief Length for Ifx_CIF_MIEP_STA_ERR_Bits.EP_1_IC_SIZE_ERR */
+#define IFX_CIF_MIEP_STA_ERR_EP_1_IC_SIZE_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_STA_ERR_Bits.EP_1_IC_SIZE_ERR */
+#define IFX_CIF_MIEP_STA_ERR_EP_1_IC_SIZE_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_STA_ERR_Bits.EP_1_IC_SIZE_ERR */
+#define IFX_CIF_MIEP_STA_ERR_EP_1_IC_SIZE_ERR_OFF (1u)
+
+/** \brief Length for Ifx_CIF_MIEP_STA_ERR_Bits.EP_2_FIFO_FULL */
+#define IFX_CIF_MIEP_STA_ERR_EP_2_FIFO_FULL_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_STA_ERR_Bits.EP_2_FIFO_FULL */
+#define IFX_CIF_MIEP_STA_ERR_EP_2_FIFO_FULL_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_STA_ERR_Bits.EP_2_FIFO_FULL */
+#define IFX_CIF_MIEP_STA_ERR_EP_2_FIFO_FULL_OFF (18u)
+
+/** \brief Length for Ifx_CIF_MIEP_STA_ERR_Bits.EP_2_IC_SIZE_ERR */
+#define IFX_CIF_MIEP_STA_ERR_EP_2_IC_SIZE_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_STA_ERR_Bits.EP_2_IC_SIZE_ERR */
+#define IFX_CIF_MIEP_STA_ERR_EP_2_IC_SIZE_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_STA_ERR_Bits.EP_2_IC_SIZE_ERR */
+#define IFX_CIF_MIEP_STA_ERR_EP_2_IC_SIZE_ERR_OFF (2u)
+
+/** \brief Length for Ifx_CIF_MIEP_STA_ERR_Bits.EP_3_FIFO_FULL */
+#define IFX_CIF_MIEP_STA_ERR_EP_3_FIFO_FULL_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_STA_ERR_Bits.EP_3_FIFO_FULL */
+#define IFX_CIF_MIEP_STA_ERR_EP_3_FIFO_FULL_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_STA_ERR_Bits.EP_3_FIFO_FULL */
+#define IFX_CIF_MIEP_STA_ERR_EP_3_FIFO_FULL_OFF (19u)
+
+/** \brief Length for Ifx_CIF_MIEP_STA_ERR_Bits.EP_3_IC_SIZE_ERR */
+#define IFX_CIF_MIEP_STA_ERR_EP_3_IC_SIZE_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_STA_ERR_Bits.EP_3_IC_SIZE_ERR */
+#define IFX_CIF_MIEP_STA_ERR_EP_3_IC_SIZE_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_STA_ERR_Bits.EP_3_IC_SIZE_ERR */
+#define IFX_CIF_MIEP_STA_ERR_EP_3_IC_SIZE_ERR_OFF (3u)
+
+/** \brief Length for Ifx_CIF_MIEP_STA_ERR_Bits.EP_4_FIFO_FULL */
+#define IFX_CIF_MIEP_STA_ERR_EP_4_FIFO_FULL_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_STA_ERR_Bits.EP_4_FIFO_FULL */
+#define IFX_CIF_MIEP_STA_ERR_EP_4_FIFO_FULL_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_STA_ERR_Bits.EP_4_FIFO_FULL */
+#define IFX_CIF_MIEP_STA_ERR_EP_4_FIFO_FULL_OFF (20u)
+
+/** \brief Length for Ifx_CIF_MIEP_STA_ERR_Bits.EP_4_IC_SIZE_ERR */
+#define IFX_CIF_MIEP_STA_ERR_EP_4_IC_SIZE_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_STA_ERR_Bits.EP_4_IC_SIZE_ERR */
+#define IFX_CIF_MIEP_STA_ERR_EP_4_IC_SIZE_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_STA_ERR_Bits.EP_4_IC_SIZE_ERR */
+#define IFX_CIF_MIEP_STA_ERR_EP_4_IC_SIZE_ERR_OFF (4u)
+
+/** \brief Length for Ifx_CIF_MIEP_STA_ERR_Bits.EP_5_FIFO_FULL */
+#define IFX_CIF_MIEP_STA_ERR_EP_5_FIFO_FULL_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_STA_ERR_Bits.EP_5_FIFO_FULL */
+#define IFX_CIF_MIEP_STA_ERR_EP_5_FIFO_FULL_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_STA_ERR_Bits.EP_5_FIFO_FULL */
+#define IFX_CIF_MIEP_STA_ERR_EP_5_FIFO_FULL_OFF (21u)
+
+/** \brief Length for Ifx_CIF_MIEP_STA_ERR_Bits.EP_5_IC_SIZE_ERR */
+#define IFX_CIF_MIEP_STA_ERR_EP_5_IC_SIZE_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_MIEP_STA_ERR_Bits.EP_5_IC_SIZE_ERR */
+#define IFX_CIF_MIEP_STA_ERR_EP_5_IC_SIZE_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_MIEP_STA_ERR_Bits.EP_5_IC_SIZE_ERR */
+#define IFX_CIF_MIEP_STA_ERR_EP_5_IC_SIZE_ERR_OFF (5u)
+
+/** \brief Length for Ifx_CIF_WD_CTRL_Bits.RST_H_CNT */
+#define IFX_CIF_WD_CTRL_RST_H_CNT_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_WD_CTRL_Bits.RST_H_CNT */
+#define IFX_CIF_WD_CTRL_RST_H_CNT_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_WD_CTRL_Bits.RST_H_CNT */
+#define IFX_CIF_WD_CTRL_RST_H_CNT_OFF (1u)
+
+/** \brief Length for Ifx_CIF_WD_CTRL_Bits.RST_PD_CNT */
+#define IFX_CIF_WD_CTRL_RST_PD_CNT_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_WD_CTRL_Bits.RST_PD_CNT */
+#define IFX_CIF_WD_CTRL_RST_PD_CNT_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_WD_CTRL_Bits.RST_PD_CNT */
+#define IFX_CIF_WD_CTRL_RST_PD_CNT_OFF (3u)
+
+/** \brief Length for Ifx_CIF_WD_CTRL_Bits.RST_V_CNT */
+#define IFX_CIF_WD_CTRL_RST_V_CNT_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_WD_CTRL_Bits.RST_V_CNT */
+#define IFX_CIF_WD_CTRL_RST_V_CNT_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_WD_CTRL_Bits.RST_V_CNT */
+#define IFX_CIF_WD_CTRL_RST_V_CNT_OFF (2u)
+
+/** \brief Length for Ifx_CIF_WD_CTRL_Bits.WD_EN */
+#define IFX_CIF_WD_CTRL_WD_EN_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_WD_CTRL_Bits.WD_EN */
+#define IFX_CIF_WD_CTRL_WD_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_WD_CTRL_Bits.WD_EN */
+#define IFX_CIF_WD_CTRL_WD_EN_OFF (0u)
+
+/** \brief Length for Ifx_CIF_WD_CTRL_Bits.WD_PREDIV */
+#define IFX_CIF_WD_CTRL_WD_PREDIV_LEN (16u)
+
+/** \brief Mask for Ifx_CIF_WD_CTRL_Bits.WD_PREDIV */
+#define IFX_CIF_WD_CTRL_WD_PREDIV_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CIF_WD_CTRL_Bits.WD_PREDIV */
+#define IFX_CIF_WD_CTRL_WD_PREDIV_OFF (16u)
+
+/** \brief Length for Ifx_CIF_WD_H_TIMEOUT_Bits.WD_HES_TO */
+#define IFX_CIF_WD_H_TIMEOUT_WD_HES_TO_LEN (16u)
+
+/** \brief Mask for Ifx_CIF_WD_H_TIMEOUT_Bits.WD_HES_TO */
+#define IFX_CIF_WD_H_TIMEOUT_WD_HES_TO_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CIF_WD_H_TIMEOUT_Bits.WD_HES_TO */
+#define IFX_CIF_WD_H_TIMEOUT_WD_HES_TO_OFF (16u)
+
+/** \brief Length for Ifx_CIF_WD_H_TIMEOUT_Bits.WD_HSE_TO */
+#define IFX_CIF_WD_H_TIMEOUT_WD_HSE_TO_LEN (16u)
+
+/** \brief Mask for Ifx_CIF_WD_H_TIMEOUT_Bits.WD_HSE_TO */
+#define IFX_CIF_WD_H_TIMEOUT_WD_HSE_TO_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CIF_WD_H_TIMEOUT_Bits.WD_HSE_TO */
+#define IFX_CIF_WD_H_TIMEOUT_WD_HSE_TO_OFF (0u)
+
+/** \brief Length for Ifx_CIF_WD_ICR_Bits.ICR_WD_HES_TO */
+#define IFX_CIF_WD_ICR_ICR_WD_HES_TO_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_WD_ICR_Bits.ICR_WD_HES_TO */
+#define IFX_CIF_WD_ICR_ICR_WD_HES_TO_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_WD_ICR_Bits.ICR_WD_HES_TO */
+#define IFX_CIF_WD_ICR_ICR_WD_HES_TO_OFF (1u)
+
+/** \brief Length for Ifx_CIF_WD_ICR_Bits.ICR_WD_HSE_TO */
+#define IFX_CIF_WD_ICR_ICR_WD_HSE_TO_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_WD_ICR_Bits.ICR_WD_HSE_TO */
+#define IFX_CIF_WD_ICR_ICR_WD_HSE_TO_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_WD_ICR_Bits.ICR_WD_HSE_TO */
+#define IFX_CIF_WD_ICR_ICR_WD_HSE_TO_OFF (0u)
+
+/** \brief Length for Ifx_CIF_WD_ICR_Bits.ICR_WD_VES_TO */
+#define IFX_CIF_WD_ICR_ICR_WD_VES_TO_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_WD_ICR_Bits.ICR_WD_VES_TO */
+#define IFX_CIF_WD_ICR_ICR_WD_VES_TO_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_WD_ICR_Bits.ICR_WD_VES_TO */
+#define IFX_CIF_WD_ICR_ICR_WD_VES_TO_OFF (3u)
+
+/** \brief Length for Ifx_CIF_WD_ICR_Bits.ICR_WD_VSE_TO */
+#define IFX_CIF_WD_ICR_ICR_WD_VSE_TO_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_WD_ICR_Bits.ICR_WD_VSE_TO */
+#define IFX_CIF_WD_ICR_ICR_WD_VSE_TO_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_WD_ICR_Bits.ICR_WD_VSE_TO */
+#define IFX_CIF_WD_ICR_ICR_WD_VSE_TO_OFF (2u)
+
+/** \brief Length for Ifx_CIF_WD_IMSC_Bits.IMSC_WD_HES_TO */
+#define IFX_CIF_WD_IMSC_IMSC_WD_HES_TO_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_WD_IMSC_Bits.IMSC_WD_HES_TO */
+#define IFX_CIF_WD_IMSC_IMSC_WD_HES_TO_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_WD_IMSC_Bits.IMSC_WD_HES_TO */
+#define IFX_CIF_WD_IMSC_IMSC_WD_HES_TO_OFF (1u)
+
+/** \brief Length for Ifx_CIF_WD_IMSC_Bits.IMSC_WD_HSE_TO */
+#define IFX_CIF_WD_IMSC_IMSC_WD_HSE_TO_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_WD_IMSC_Bits.IMSC_WD_HSE_TO */
+#define IFX_CIF_WD_IMSC_IMSC_WD_HSE_TO_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_WD_IMSC_Bits.IMSC_WD_HSE_TO */
+#define IFX_CIF_WD_IMSC_IMSC_WD_HSE_TO_OFF (0u)
+
+/** \brief Length for Ifx_CIF_WD_IMSC_Bits.IMSC_WD_VES_TO */
+#define IFX_CIF_WD_IMSC_IMSC_WD_VES_TO_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_WD_IMSC_Bits.IMSC_WD_VES_TO */
+#define IFX_CIF_WD_IMSC_IMSC_WD_VES_TO_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_WD_IMSC_Bits.IMSC_WD_VES_TO */
+#define IFX_CIF_WD_IMSC_IMSC_WD_VES_TO_OFF (3u)
+
+/** \brief Length for Ifx_CIF_WD_IMSC_Bits.IMSC_WD_VSE_TO */
+#define IFX_CIF_WD_IMSC_IMSC_WD_VSE_TO_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_WD_IMSC_Bits.IMSC_WD_VSE_TO */
+#define IFX_CIF_WD_IMSC_IMSC_WD_VSE_TO_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_WD_IMSC_Bits.IMSC_WD_VSE_TO */
+#define IFX_CIF_WD_IMSC_IMSC_WD_VSE_TO_OFF (2u)
+
+/** \brief Length for Ifx_CIF_WD_ISR_Bits.ISR_WD_HES_TO */
+#define IFX_CIF_WD_ISR_ISR_WD_HES_TO_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_WD_ISR_Bits.ISR_WD_HES_TO */
+#define IFX_CIF_WD_ISR_ISR_WD_HES_TO_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_WD_ISR_Bits.ISR_WD_HES_TO */
+#define IFX_CIF_WD_ISR_ISR_WD_HES_TO_OFF (1u)
+
+/** \brief Length for Ifx_CIF_WD_ISR_Bits.ISR_WD_HSE_TO */
+#define IFX_CIF_WD_ISR_ISR_WD_HSE_TO_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_WD_ISR_Bits.ISR_WD_HSE_TO */
+#define IFX_CIF_WD_ISR_ISR_WD_HSE_TO_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_WD_ISR_Bits.ISR_WD_HSE_TO */
+#define IFX_CIF_WD_ISR_ISR_WD_HSE_TO_OFF (0u)
+
+/** \brief Length for Ifx_CIF_WD_ISR_Bits.ISR_WD_VES_TO */
+#define IFX_CIF_WD_ISR_ISR_WD_VES_TO_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_WD_ISR_Bits.ISR_WD_VES_TO */
+#define IFX_CIF_WD_ISR_ISR_WD_VES_TO_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_WD_ISR_Bits.ISR_WD_VES_TO */
+#define IFX_CIF_WD_ISR_ISR_WD_VES_TO_OFF (3u)
+
+/** \brief Length for Ifx_CIF_WD_ISR_Bits.ISR_WD_VSE_TO */
+#define IFX_CIF_WD_ISR_ISR_WD_VSE_TO_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_WD_ISR_Bits.ISR_WD_VSE_TO */
+#define IFX_CIF_WD_ISR_ISR_WD_VSE_TO_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_WD_ISR_Bits.ISR_WD_VSE_TO */
+#define IFX_CIF_WD_ISR_ISR_WD_VSE_TO_OFF (2u)
+
+/** \brief Length for Ifx_CIF_WD_MIS_Bits.MIS_WD_HES_TO */
+#define IFX_CIF_WD_MIS_MIS_WD_HES_TO_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_WD_MIS_Bits.MIS_WD_HES_TO */
+#define IFX_CIF_WD_MIS_MIS_WD_HES_TO_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_WD_MIS_Bits.MIS_WD_HES_TO */
+#define IFX_CIF_WD_MIS_MIS_WD_HES_TO_OFF (1u)
+
+/** \brief Length for Ifx_CIF_WD_MIS_Bits.MIS_WD_HSE_TO */
+#define IFX_CIF_WD_MIS_MIS_WD_HSE_TO_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_WD_MIS_Bits.MIS_WD_HSE_TO */
+#define IFX_CIF_WD_MIS_MIS_WD_HSE_TO_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_WD_MIS_Bits.MIS_WD_HSE_TO */
+#define IFX_CIF_WD_MIS_MIS_WD_HSE_TO_OFF (0u)
+
+/** \brief Length for Ifx_CIF_WD_MIS_Bits.MIS_WD_VES_TO */
+#define IFX_CIF_WD_MIS_MIS_WD_VES_TO_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_WD_MIS_Bits.MIS_WD_VES_TO */
+#define IFX_CIF_WD_MIS_MIS_WD_VES_TO_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_WD_MIS_Bits.MIS_WD_VES_TO */
+#define IFX_CIF_WD_MIS_MIS_WD_VES_TO_OFF (3u)
+
+/** \brief Length for Ifx_CIF_WD_MIS_Bits.MIS_WD_VSE_TO */
+#define IFX_CIF_WD_MIS_MIS_WD_VSE_TO_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_WD_MIS_Bits.MIS_WD_VSE_TO */
+#define IFX_CIF_WD_MIS_MIS_WD_VSE_TO_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_WD_MIS_Bits.MIS_WD_VSE_TO */
+#define IFX_CIF_WD_MIS_MIS_WD_VSE_TO_OFF (2u)
+
+/** \brief Length for Ifx_CIF_WD_RIS_Bits.RIS_WD_HES_TO */
+#define IFX_CIF_WD_RIS_RIS_WD_HES_TO_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_WD_RIS_Bits.RIS_WD_HES_TO */
+#define IFX_CIF_WD_RIS_RIS_WD_HES_TO_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_WD_RIS_Bits.RIS_WD_HES_TO */
+#define IFX_CIF_WD_RIS_RIS_WD_HES_TO_OFF (1u)
+
+/** \brief Length for Ifx_CIF_WD_RIS_Bits.RIS_WD_HSE_TO */
+#define IFX_CIF_WD_RIS_RIS_WD_HSE_TO_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_WD_RIS_Bits.RIS_WD_HSE_TO */
+#define IFX_CIF_WD_RIS_RIS_WD_HSE_TO_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_WD_RIS_Bits.RIS_WD_HSE_TO */
+#define IFX_CIF_WD_RIS_RIS_WD_HSE_TO_OFF (0u)
+
+/** \brief Length for Ifx_CIF_WD_RIS_Bits.RIS_WD_VES_TO */
+#define IFX_CIF_WD_RIS_RIS_WD_VES_TO_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_WD_RIS_Bits.RIS_WD_VES_TO */
+#define IFX_CIF_WD_RIS_RIS_WD_VES_TO_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_WD_RIS_Bits.RIS_WD_VES_TO */
+#define IFX_CIF_WD_RIS_RIS_WD_VES_TO_OFF (3u)
+
+/** \brief Length for Ifx_CIF_WD_RIS_Bits.RIS_WD_VSE_TO */
+#define IFX_CIF_WD_RIS_RIS_WD_VSE_TO_LEN (1u)
+
+/** \brief Mask for Ifx_CIF_WD_RIS_Bits.RIS_WD_VSE_TO */
+#define IFX_CIF_WD_RIS_RIS_WD_VSE_TO_MSK (0x1u)
+
+/** \brief Offset for Ifx_CIF_WD_RIS_Bits.RIS_WD_VSE_TO */
+#define IFX_CIF_WD_RIS_RIS_WD_VSE_TO_OFF (2u)
+
+/** \brief Length for Ifx_CIF_WD_V_TIMEOUT_Bits.WD_VES_TO */
+#define IFX_CIF_WD_V_TIMEOUT_WD_VES_TO_LEN (16u)
+
+/** \brief Mask for Ifx_CIF_WD_V_TIMEOUT_Bits.WD_VES_TO */
+#define IFX_CIF_WD_V_TIMEOUT_WD_VES_TO_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CIF_WD_V_TIMEOUT_Bits.WD_VES_TO */
+#define IFX_CIF_WD_V_TIMEOUT_WD_VES_TO_OFF (16u)
+
+/** \brief Length for Ifx_CIF_WD_V_TIMEOUT_Bits.WD_VSE_TO */
+#define IFX_CIF_WD_V_TIMEOUT_WD_VSE_TO_LEN (16u)
+
+/** \brief Mask for Ifx_CIF_WD_V_TIMEOUT_Bits.WD_VSE_TO */
+#define IFX_CIF_WD_V_TIMEOUT_WD_VSE_TO_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CIF_WD_V_TIMEOUT_Bits.WD_VSE_TO */
+#define IFX_CIF_WD_V_TIMEOUT_WD_VSE_TO_OFF (0u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXCIF_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCif_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCif_reg.h
new file mode 100644
index 0000000..b69496b
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCif_reg.h
@@ -0,0 +1,2362 @@
+/**
+ * \file IfxCif_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Cif_Cfg Cif address
+ * \ingroup IfxLld_Cif
+ *
+ * \defgroup IfxLld_Cif_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Cif_Cfg
+ *
+ * \defgroup IfxLld_Cif_Cfg_Cif 2-CIF
+ * \ingroup IfxLld_Cif_Cfg
+ *
+ */
+#ifndef IFXCIF_REG_H
+#define IFXCIF_REG_H 1
+/******************************************************************************/
+#include "IfxCif_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Cif_Cfg_BaseAddress
+ * \{ */
+
+/** \brief CIF object */
+#define MODULE_CIF /*lint --e(923)*/ (*(Ifx_CIF*)0xF90E1F00u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Cif_Cfg_Cif
+ * \{ */
+
+/** \brief C, Access Enable Register 0 */
+#define CIF_BBB_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_CIF_BBB_ACCEN0*)0xF90E1F0Cu)
+
+/** Alias (User Manual Name) for CIF_BBB_ACCEN0.
+* To use register names with standard convension, please use CIF_BBB_ACCEN0.
+*/
+#define CIFBBB_ACCEN0 (CIF_BBB_ACCEN0)
+
+/** \brief 10, Access Enable Register 1 */
+#define CIF_BBB_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_CIF_BBB_ACCEN1*)0xF90E1F10u)
+
+/** Alias (User Manual Name) for CIF_BBB_ACCEN1.
+* To use register names with standard convension, please use CIF_BBB_ACCEN1.
+*/
+#define CIFBBB_ACCEN1 (CIF_BBB_ACCEN1)
+
+/** \brief 0, Clock Control Register */
+#define CIF_BBB_CLC /*lint --e(923)*/ (*(volatile Ifx_CIF_BBB_CLC*)0xF90E1F00u)
+
+/** Alias (User Manual Name) for CIF_BBB_CLC.
+* To use register names with standard convension, please use CIF_BBB_CLC.
+*/
+#define CIFBBB_CLC (CIF_BBB_CLC)
+
+/** \brief 8, General Purpose Control Register */
+#define CIF_BBB_GPCTL /*lint --e(923)*/ (*(volatile Ifx_CIF_BBB_GPCTL*)0xF90E1F08u)
+
+/** Alias (User Manual Name) for CIF_BBB_GPCTL.
+* To use register names with standard convension, please use CIF_BBB_GPCTL.
+*/
+#define CIFBBB_GPCTL (CIF_BBB_GPCTL)
+
+/** \brief 14, Kernel Reset Register 0 */
+#define CIF_BBB_KRST0 /*lint --e(923)*/ (*(volatile Ifx_CIF_BBB_KRST0*)0xF90E1F14u)
+
+/** Alias (User Manual Name) for CIF_BBB_KRST0.
+* To use register names with standard convension, please use CIF_BBB_KRST0.
+*/
+#define CIFBBB_KRST0 (CIF_BBB_KRST0)
+
+/** \brief 18, Kernel Reset Register 1 */
+#define CIF_BBB_KRST1 /*lint --e(923)*/ (*(volatile Ifx_CIF_BBB_KRST1*)0xF90E1F18u)
+
+/** Alias (User Manual Name) for CIF_BBB_KRST1.
+* To use register names with standard convension, please use CIF_BBB_KRST1.
+*/
+#define CIFBBB_KRST1 (CIF_BBB_KRST1)
+
+/** \brief 1C, Kernel Reset Status Clear Register */
+#define CIF_BBB_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_CIF_BBB_KRSTCLR*)0xF90E1F1Cu)
+
+/** Alias (User Manual Name) for CIF_BBB_KRSTCLR.
+* To use register names with standard convension, please use CIF_BBB_KRSTCLR.
+*/
+#define CIFBBB_KRSTCLR (CIF_BBB_KRSTCLR)
+
+/** \brief 4, Module Identification Register */
+#define CIF_BBB_MODID /*lint --e(923)*/ (*(volatile Ifx_CIF_BBB_MODID*)0xF90E1F04u)
+
+/** Alias (User Manual Name) for CIF_BBB_MODID.
+* To use register names with standard convension, please use CIF_BBB_MODID.
+*/
+#define CIFBBB_MODID (CIF_BBB_MODID)
+
+/** \brief 100, Clock Control Register */
+#define CIF_CCL /*lint --e(923)*/ (*(volatile Ifx_CIF_CCL*)0xF90E2000u)
+
+/** \brief 2800, Debug Path Control Register */
+#define CIF_DP_CTRL /*lint --e(923)*/ (*(volatile Ifx_CIF_DP_CTRL*)0xF90E4700u)
+
+/** Alias (User Manual Name) for CIF_DP_CTRL.
+* To use register names with standard convension, please use CIF_DP_CTRL.
+*/
+#define CIFDP_CTRL (CIF_DP_CTRL)
+
+/** \brief 2808, Debug Path Frame/Line Counter Status Register */
+#define CIF_DP_FLC_STAT /*lint --e(923)*/ (*(volatile Ifx_CIF_DP_FLC_STAT*)0xF90E4708u)
+
+/** Alias (User Manual Name) for CIF_DP_FLC_STAT.
+* To use register names with standard convension, please use CIF_DP_FLC_STAT.
+*/
+#define CIFDP_FLC_STAT (CIF_DP_FLC_STAT)
+
+/** \brief 2804, Debug Path Predivider Control Register */
+#define CIF_DP_PDIV_CTRL /*lint --e(923)*/ (*(volatile Ifx_CIF_DP_PDIV_CTRL*)0xF90E4704u)
+
+/** Alias (User Manual Name) for CIF_DP_PDIV_CTRL.
+* To use register names with standard convension, please use CIF_DP_PDIV_CTRL.
+*/
+#define CIFDP_PDIV_CTRL (CIF_DP_PDIV_CTRL)
+
+/** \brief 280C, Debug Path Predivider Counter Status Register */
+#define CIF_DP_PDIV_STAT /*lint --e(923)*/ (*(volatile Ifx_CIF_DP_PDIV_STAT*)0xF90E470Cu)
+
+/** Alias (User Manual Name) for CIF_DP_PDIV_STAT.
+* To use register names with standard convension, please use CIF_DP_PDIV_STAT.
+*/
+#define CIFDP_PDIV_STAT (CIF_DP_PDIV_STAT)
+
+/** \brief 2810, Debug Path Timestamp Counter Status Register */
+#define CIF_DP_TSC_STAT /*lint --e(923)*/ (*(volatile Ifx_CIF_DP_TSC_STAT*)0xF90E4710u)
+
+/** Alias (User Manual Name) for CIF_DP_TSC_STAT.
+* To use register names with standard convension, please use CIF_DP_TSC_STAT.
+*/
+#define CIFDP_TSC_STAT (CIF_DP_TSC_STAT)
+
+/** \brief 2814, Debug Path User Defined Symbol Register \note Array index
+ * shifted by 1. Example: defined register UDS_1S[0]/UDS_1S0 corresponds to user
+ * manual UDS_1S1, ... */
+#define CIF_DP_UDS_1S0 /*lint --e(923)*/ (*(volatile Ifx_CIF_DP_UDS*)0xF90E4714u)
+
+/** Alias (User Manual Name) for CIF_DP_UDS_1S0.
+* To use register names with standard convension, please use CIF_DP_UDS_1S0.
+*/
+#define CIFDP_UDS_1 (CIF_DP_UDS_1S0)
+
+/** \brief 2818, Debug Path User Defined Symbol Register \note Array index
+ * shifted by 1. Example: defined register UDS_1S[0]/UDS_1S0 corresponds to user
+ * manual UDS_1S1, ... */
+#define CIF_DP_UDS_1S1 /*lint --e(923)*/ (*(volatile Ifx_CIF_DP_UDS*)0xF90E4718u)
+
+/** Alias (User Manual Name) for CIF_DP_UDS_1S1.
+* To use register names with standard convension, please use CIF_DP_UDS_1S1.
+*/
+#define CIFDP_UDS_2 (CIF_DP_UDS_1S1)
+
+/** \brief 281C, Debug Path User Defined Symbol Register \note Array index
+ * shifted by 1. Example: defined register UDS_1S[0]/UDS_1S0 corresponds to user
+ * manual UDS_1S1, ... */
+#define CIF_DP_UDS_1S2 /*lint --e(923)*/ (*(volatile Ifx_CIF_DP_UDS*)0xF90E471Cu)
+
+/** Alias (User Manual Name) for CIF_DP_UDS_1S2.
+* To use register names with standard convension, please use CIF_DP_UDS_1S2.
+*/
+#define CIFDP_UDS_3 (CIF_DP_UDS_1S2)
+
+/** \brief 2820, Debug Path User Defined Symbol Register \note Array index
+ * shifted by 1. Example: defined register UDS_1S[0]/UDS_1S0 corresponds to user
+ * manual UDS_1S1, ... */
+#define CIF_DP_UDS_1S3 /*lint --e(923)*/ (*(volatile Ifx_CIF_DP_UDS*)0xF90E4720u)
+
+/** Alias (User Manual Name) for CIF_DP_UDS_1S3.
+* To use register names with standard convension, please use CIF_DP_UDS_1S3.
+*/
+#define CIFDP_UDS_4 (CIF_DP_UDS_1S3)
+
+/** \brief 2824, Debug Path User Defined Symbol Register \note Array index
+ * shifted by 1. Example: defined register UDS_1S[0]/UDS_1S0 corresponds to user
+ * manual UDS_1S1, ... */
+#define CIF_DP_UDS_1S4 /*lint --e(923)*/ (*(volatile Ifx_CIF_DP_UDS*)0xF90E4724u)
+
+/** Alias (User Manual Name) for CIF_DP_UDS_1S4.
+* To use register names with standard convension, please use CIF_DP_UDS_1S4.
+*/
+#define CIFDP_UDS_5 (CIF_DP_UDS_1S4)
+
+/** \brief 2828, Debug Path User Defined Symbol Register \note Array index
+ * shifted by 1. Example: defined register UDS_1S[0]/UDS_1S0 corresponds to user
+ * manual UDS_1S1, ... */
+#define CIF_DP_UDS_1S5 /*lint --e(923)*/ (*(volatile Ifx_CIF_DP_UDS*)0xF90E4728u)
+
+/** Alias (User Manual Name) for CIF_DP_UDS_1S5.
+* To use register names with standard convension, please use CIF_DP_UDS_1S5.
+*/
+#define CIFDP_UDS_6 (CIF_DP_UDS_1S5)
+
+/** \brief 282C, Debug Path User Defined Symbol Register \note Array index
+ * shifted by 1. Example: defined register UDS_1S[0]/UDS_1S0 corresponds to user
+ * manual UDS_1S1, ... */
+#define CIF_DP_UDS_1S6 /*lint --e(923)*/ (*(volatile Ifx_CIF_DP_UDS*)0xF90E472Cu)
+
+/** Alias (User Manual Name) for CIF_DP_UDS_1S6.
+* To use register names with standard convension, please use CIF_DP_UDS_1S6.
+*/
+#define CIFDP_UDS_7 (CIF_DP_UDS_1S6)
+
+/** \brief 2830, Debug Path User Defined Symbol Register \note Array index
+ * shifted by 1. Example: defined register UDS_1S[0]/UDS_1S0 corresponds to user
+ * manual UDS_1S1, ... */
+#define CIF_DP_UDS_1S7 /*lint --e(923)*/ (*(volatile Ifx_CIF_DP_UDS*)0xF90E4730u)
+
+/** Alias (User Manual Name) for CIF_DP_UDS_1S7.
+* To use register names with standard convension, please use CIF_DP_UDS_1S7.
+*/
+#define CIFDP_UDS_8 (CIF_DP_UDS_1S7)
+
+/** \brief 118, CIF Data Path Control Register */
+#define CIF_DPCL /*lint --e(923)*/ (*(volatile Ifx_CIF_DPCL*)0xF90E2018u)
+
+/** \brief 2A00, Extra Path Image Cropping Control Register */
+#define CIF_EP_IC_1S0_CTRL /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_CTRL*)0xF90E4900u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S0_CTRL.
+* To use register names with standard convension, please use CIF_EP_IC_1S0_CTRL.
+*/
+#define CIFEP_1_IC_CTRL (CIF_EP_IC_1S0_CTRL)
+
+/** \brief 2A20, Extra Path Image Cropping Camera Displacement Register */
+#define CIF_EP_IC_1S0_DISPLACE /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_DISPLACE*)0xF90E4920u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S0_DISPLACE.
+* To use register names with standard convension, please use CIF_EP_IC_1S0_DISPLACE.
+*/
+#define CIFEP_1_IC_DISPLACE (CIF_EP_IC_1S0_DISPLACE)
+
+/** \brief 2A08, Extra Path Image Cropping Horizontal Offset of Output Window
+ * Register */
+#define CIF_EP_IC_1S0_H_OFFS /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_H_OFFS*)0xF90E4908u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S0_H_OFFS.
+* To use register names with standard convension, please use CIF_EP_IC_1S0_H_OFFS.
+*/
+#define CIFEP_1_IC_H_OFFS (CIF_EP_IC_1S0_H_OFFS)
+
+/** \brief 2A24, Extra Path Image Current Horizontal Offset Of Output Window
+ * Shadow Register */
+#define CIF_EP_IC_1S0_H_OFFS_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_H_OFFS_SHD*)0xF90E4924u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S0_H_OFFS_SHD.
+* To use register names with standard convension, please use CIF_EP_IC_1S0_H_OFFS_SHD.
+*/
+#define CIFEP_1_IC_H_OFFS_SHD (CIF_EP_IC_1S0_H_OFFS_SHD)
+
+/** \brief 2A10, Extra Path Image Cropping Output Horizontal Picture Size
+ * Register */
+#define CIF_EP_IC_1S0_H_SIZE /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_H_SIZE*)0xF90E4910u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S0_H_SIZE.
+* To use register names with standard convension, please use CIF_EP_IC_1S0_H_SIZE.
+*/
+#define CIFEP_1_IC_H_SIZE (CIF_EP_IC_1S0_H_SIZE)
+
+/** \brief 2A2C, Extra Path Image Current Output Horizontal Picture Size Shadow
+ * Register */
+#define CIF_EP_IC_1S0_H_SIZE_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_H_SIZE_SHD*)0xF90E492Cu)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S0_H_SIZE_SHD.
+* To use register names with standard convension, please use CIF_EP_IC_1S0_H_SIZE_SHD.
+*/
+#define CIFEP_1_IC_H_SIZE_SHD (CIF_EP_IC_1S0_H_SIZE_SHD)
+
+/** \brief 2A18, Extra Path Image Cropping Maximum Horizontal Displacement
+ * Register */
+#define CIF_EP_IC_1S0_MAX_DX /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_MAX_DX*)0xF90E4918u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S0_MAX_DX.
+* To use register names with standard convension, please use CIF_EP_IC_1S0_MAX_DX.
+*/
+#define CIFEP_1_IC_MAX_DX (CIF_EP_IC_1S0_MAX_DX)
+
+/** \brief 2A1C, Extra Path Image Cropping Maximum Vertical Displacement
+ * Register */
+#define CIF_EP_IC_1S0_MAX_DY /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_MAX_DY*)0xF90E491Cu)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S0_MAX_DY.
+* To use register names with standard convension, please use CIF_EP_IC_1S0_MAX_DY.
+*/
+#define CIFEP_1_IC_MAX_DY (CIF_EP_IC_1S0_MAX_DY)
+
+/** \brief 2A04, Extra Path Image Cropping Recenter Register */
+#define CIF_EP_IC_1S0_RECENTER /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_RECENTER*)0xF90E4904u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S0_RECENTER.
+* To use register names with standard convension, please use CIF_EP_IC_1S0_RECENTER.
+*/
+#define CIFEP_1_IC_RECENTER (CIF_EP_IC_1S0_RECENTER)
+
+/** \brief 2A0C, Extra Path Image Cropping Vertical Offset Of Output Window
+ * Register */
+#define CIF_EP_IC_1S0_V_OFFS /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_V_OFFS*)0xF90E490Cu)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S0_V_OFFS.
+* To use register names with standard convension, please use CIF_EP_IC_1S0_V_OFFS.
+*/
+#define CIFEP_1_IC_V_OFFS (CIF_EP_IC_1S0_V_OFFS)
+
+/** \brief 2A28, Extra Path Image Current Vertical Offset Of Output Window
+ * Shadow Register */
+#define CIF_EP_IC_1S0_V_OFFS_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_V_OFFS_SHD*)0xF90E4928u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S0_V_OFFS_SHD.
+* To use register names with standard convension, please use CIF_EP_IC_1S0_V_OFFS_SHD.
+*/
+#define CIFEP_1_IC_V_OFFS_SHD (CIF_EP_IC_1S0_V_OFFS_SHD)
+
+/** \brief 2A14, Extra Path Image Cropping Output Vertical Picture Size
+ * Register */
+#define CIF_EP_IC_1S0_V_SIZE /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_V_SIZE*)0xF90E4914u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S0_V_SIZE.
+* To use register names with standard convension, please use CIF_EP_IC_1S0_V_SIZE.
+*/
+#define CIFEP_1_IC_V_SIZE (CIF_EP_IC_1S0_V_SIZE)
+
+/** \brief 2A30, Extra Path Image Current Output Vertical Picture Size Shadow
+ * Register */
+#define CIF_EP_IC_1S0_V_SIZE_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_V_SIZE_SHD*)0xF90E4930u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S0_V_SIZE_SHD.
+* To use register names with standard convension, please use CIF_EP_IC_1S0_V_SIZE_SHD.
+*/
+#define CIFEP_1_IC_V_SIZE_SHD (CIF_EP_IC_1S0_V_SIZE_SHD)
+
+/** \brief 2B00, Extra Path Image Cropping Control Register */
+#define CIF_EP_IC_1S1_CTRL /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_CTRL*)0xF90E4A00u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S1_CTRL.
+* To use register names with standard convension, please use CIF_EP_IC_1S1_CTRL.
+*/
+#define CIFEP_2_IC_CTRL (CIF_EP_IC_1S1_CTRL)
+
+/** \brief 2B20, Extra Path Image Cropping Camera Displacement Register */
+#define CIF_EP_IC_1S1_DISPLACE /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_DISPLACE*)0xF90E4A20u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S1_DISPLACE.
+* To use register names with standard convension, please use CIF_EP_IC_1S1_DISPLACE.
+*/
+#define CIFEP_2_IC_DISPLACE (CIF_EP_IC_1S1_DISPLACE)
+
+/** \brief 2B08, Extra Path Image Cropping Horizontal Offset of Output Window
+ * Register */
+#define CIF_EP_IC_1S1_H_OFFS /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_H_OFFS*)0xF90E4A08u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S1_H_OFFS.
+* To use register names with standard convension, please use CIF_EP_IC_1S1_H_OFFS.
+*/
+#define CIFEP_2_IC_H_OFFS (CIF_EP_IC_1S1_H_OFFS)
+
+/** \brief 2B24, Extra Path Image Current Horizontal Offset Of Output Window
+ * Shadow Register */
+#define CIF_EP_IC_1S1_H_OFFS_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_H_OFFS_SHD*)0xF90E4A24u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S1_H_OFFS_SHD.
+* To use register names with standard convension, please use CIF_EP_IC_1S1_H_OFFS_SHD.
+*/
+#define CIFEP_2_IC_H_OFFS_SHD (CIF_EP_IC_1S1_H_OFFS_SHD)
+
+/** \brief 2B10, Extra Path Image Cropping Output Horizontal Picture Size
+ * Register */
+#define CIF_EP_IC_1S1_H_SIZE /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_H_SIZE*)0xF90E4A10u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S1_H_SIZE.
+* To use register names with standard convension, please use CIF_EP_IC_1S1_H_SIZE.
+*/
+#define CIFEP_2_IC_H_SIZE (CIF_EP_IC_1S1_H_SIZE)
+
+/** \brief 2B2C, Extra Path Image Current Output Horizontal Picture Size Shadow
+ * Register */
+#define CIF_EP_IC_1S1_H_SIZE_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_H_SIZE_SHD*)0xF90E4A2Cu)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S1_H_SIZE_SHD.
+* To use register names with standard convension, please use CIF_EP_IC_1S1_H_SIZE_SHD.
+*/
+#define CIFEP_2_IC_H_SIZE_SHD (CIF_EP_IC_1S1_H_SIZE_SHD)
+
+/** \brief 2B18, Extra Path Image Cropping Maximum Horizontal Displacement
+ * Register */
+#define CIF_EP_IC_1S1_MAX_DX /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_MAX_DX*)0xF90E4A18u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S1_MAX_DX.
+* To use register names with standard convension, please use CIF_EP_IC_1S1_MAX_DX.
+*/
+#define CIFEP_2_IC_MAX_DX (CIF_EP_IC_1S1_MAX_DX)
+
+/** \brief 2B1C, Extra Path Image Cropping Maximum Vertical Displacement
+ * Register */
+#define CIF_EP_IC_1S1_MAX_DY /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_MAX_DY*)0xF90E4A1Cu)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S1_MAX_DY.
+* To use register names with standard convension, please use CIF_EP_IC_1S1_MAX_DY.
+*/
+#define CIFEP_2_IC_MAX_DY (CIF_EP_IC_1S1_MAX_DY)
+
+/** \brief 2B04, Extra Path Image Cropping Recenter Register */
+#define CIF_EP_IC_1S1_RECENTER /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_RECENTER*)0xF90E4A04u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S1_RECENTER.
+* To use register names with standard convension, please use CIF_EP_IC_1S1_RECENTER.
+*/
+#define CIFEP_2_IC_RECENTER (CIF_EP_IC_1S1_RECENTER)
+
+/** \brief 2B0C, Extra Path Image Cropping Vertical Offset Of Output Window
+ * Register */
+#define CIF_EP_IC_1S1_V_OFFS /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_V_OFFS*)0xF90E4A0Cu)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S1_V_OFFS.
+* To use register names with standard convension, please use CIF_EP_IC_1S1_V_OFFS.
+*/
+#define CIFEP_2_IC_V_OFFS (CIF_EP_IC_1S1_V_OFFS)
+
+/** \brief 2B28, Extra Path Image Current Vertical Offset Of Output Window
+ * Shadow Register */
+#define CIF_EP_IC_1S1_V_OFFS_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_V_OFFS_SHD*)0xF90E4A28u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S1_V_OFFS_SHD.
+* To use register names with standard convension, please use CIF_EP_IC_1S1_V_OFFS_SHD.
+*/
+#define CIFEP_2_IC_V_OFFS_SHD (CIF_EP_IC_1S1_V_OFFS_SHD)
+
+/** \brief 2B14, Extra Path Image Cropping Output Vertical Picture Size
+ * Register */
+#define CIF_EP_IC_1S1_V_SIZE /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_V_SIZE*)0xF90E4A14u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S1_V_SIZE.
+* To use register names with standard convension, please use CIF_EP_IC_1S1_V_SIZE.
+*/
+#define CIFEP_2_IC_V_SIZE (CIF_EP_IC_1S1_V_SIZE)
+
+/** \brief 2B30, Extra Path Image Current Output Vertical Picture Size Shadow
+ * Register */
+#define CIF_EP_IC_1S1_V_SIZE_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_V_SIZE_SHD*)0xF90E4A30u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S1_V_SIZE_SHD.
+* To use register names with standard convension, please use CIF_EP_IC_1S1_V_SIZE_SHD.
+*/
+#define CIFEP_2_IC_V_SIZE_SHD (CIF_EP_IC_1S1_V_SIZE_SHD)
+
+/** \brief 2C00, Extra Path Image Cropping Control Register */
+#define CIF_EP_IC_1S2_CTRL /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_CTRL*)0xF90E4B00u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S2_CTRL.
+* To use register names with standard convension, please use CIF_EP_IC_1S2_CTRL.
+*/
+#define CIFEP_3_IC_CTRL (CIF_EP_IC_1S2_CTRL)
+
+/** \brief 2C20, Extra Path Image Cropping Camera Displacement Register */
+#define CIF_EP_IC_1S2_DISPLACE /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_DISPLACE*)0xF90E4B20u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S2_DISPLACE.
+* To use register names with standard convension, please use CIF_EP_IC_1S2_DISPLACE.
+*/
+#define CIFEP_3_IC_DISPLACE (CIF_EP_IC_1S2_DISPLACE)
+
+/** \brief 2C08, Extra Path Image Cropping Horizontal Offset of Output Window
+ * Register */
+#define CIF_EP_IC_1S2_H_OFFS /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_H_OFFS*)0xF90E4B08u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S2_H_OFFS.
+* To use register names with standard convension, please use CIF_EP_IC_1S2_H_OFFS.
+*/
+#define CIFEP_3_IC_H_OFFS (CIF_EP_IC_1S2_H_OFFS)
+
+/** \brief 2C24, Extra Path Image Current Horizontal Offset Of Output Window
+ * Shadow Register */
+#define CIF_EP_IC_1S2_H_OFFS_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_H_OFFS_SHD*)0xF90E4B24u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S2_H_OFFS_SHD.
+* To use register names with standard convension, please use CIF_EP_IC_1S2_H_OFFS_SHD.
+*/
+#define CIFEP_3_IC_H_OFFS_SHD (CIF_EP_IC_1S2_H_OFFS_SHD)
+
+/** \brief 2C10, Extra Path Image Cropping Output Horizontal Picture Size
+ * Register */
+#define CIF_EP_IC_1S2_H_SIZE /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_H_SIZE*)0xF90E4B10u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S2_H_SIZE.
+* To use register names with standard convension, please use CIF_EP_IC_1S2_H_SIZE.
+*/
+#define CIFEP_3_IC_H_SIZE (CIF_EP_IC_1S2_H_SIZE)
+
+/** \brief 2C2C, Extra Path Image Current Output Horizontal Picture Size Shadow
+ * Register */
+#define CIF_EP_IC_1S2_H_SIZE_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_H_SIZE_SHD*)0xF90E4B2Cu)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S2_H_SIZE_SHD.
+* To use register names with standard convension, please use CIF_EP_IC_1S2_H_SIZE_SHD.
+*/
+#define CIFEP_3_IC_H_SIZE_SHD (CIF_EP_IC_1S2_H_SIZE_SHD)
+
+/** \brief 2C18, Extra Path Image Cropping Maximum Horizontal Displacement
+ * Register */
+#define CIF_EP_IC_1S2_MAX_DX /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_MAX_DX*)0xF90E4B18u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S2_MAX_DX.
+* To use register names with standard convension, please use CIF_EP_IC_1S2_MAX_DX.
+*/
+#define CIFEP_3_IC_MAX_DX (CIF_EP_IC_1S2_MAX_DX)
+
+/** \brief 2C1C, Extra Path Image Cropping Maximum Vertical Displacement
+ * Register */
+#define CIF_EP_IC_1S2_MAX_DY /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_MAX_DY*)0xF90E4B1Cu)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S2_MAX_DY.
+* To use register names with standard convension, please use CIF_EP_IC_1S2_MAX_DY.
+*/
+#define CIFEP_3_IC_MAX_DY (CIF_EP_IC_1S2_MAX_DY)
+
+/** \brief 2C04, Extra Path Image Cropping Recenter Register */
+#define CIF_EP_IC_1S2_RECENTER /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_RECENTER*)0xF90E4B04u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S2_RECENTER.
+* To use register names with standard convension, please use CIF_EP_IC_1S2_RECENTER.
+*/
+#define CIFEP_3_IC_RECENTER (CIF_EP_IC_1S2_RECENTER)
+
+/** \brief 2C0C, Extra Path Image Cropping Vertical Offset Of Output Window
+ * Register */
+#define CIF_EP_IC_1S2_V_OFFS /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_V_OFFS*)0xF90E4B0Cu)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S2_V_OFFS.
+* To use register names with standard convension, please use CIF_EP_IC_1S2_V_OFFS.
+*/
+#define CIFEP_3_IC_V_OFFS (CIF_EP_IC_1S2_V_OFFS)
+
+/** \brief 2C28, Extra Path Image Current Vertical Offset Of Output Window
+ * Shadow Register */
+#define CIF_EP_IC_1S2_V_OFFS_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_V_OFFS_SHD*)0xF90E4B28u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S2_V_OFFS_SHD.
+* To use register names with standard convension, please use CIF_EP_IC_1S2_V_OFFS_SHD.
+*/
+#define CIFEP_3_IC_V_OFFS_SHD (CIF_EP_IC_1S2_V_OFFS_SHD)
+
+/** \brief 2C14, Extra Path Image Cropping Output Vertical Picture Size
+ * Register */
+#define CIF_EP_IC_1S2_V_SIZE /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_V_SIZE*)0xF90E4B14u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S2_V_SIZE.
+* To use register names with standard convension, please use CIF_EP_IC_1S2_V_SIZE.
+*/
+#define CIFEP_3_IC_V_SIZE (CIF_EP_IC_1S2_V_SIZE)
+
+/** \brief 2C30, Extra Path Image Current Output Vertical Picture Size Shadow
+ * Register */
+#define CIF_EP_IC_1S2_V_SIZE_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_V_SIZE_SHD*)0xF90E4B30u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S2_V_SIZE_SHD.
+* To use register names with standard convension, please use CIF_EP_IC_1S2_V_SIZE_SHD.
+*/
+#define CIFEP_3_IC_V_SIZE_SHD (CIF_EP_IC_1S2_V_SIZE_SHD)
+
+/** \brief 2D00, Extra Path Image Cropping Control Register */
+#define CIF_EP_IC_1S3_CTRL /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_CTRL*)0xF90E4C00u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S3_CTRL.
+* To use register names with standard convension, please use CIF_EP_IC_1S3_CTRL.
+*/
+#define CIFEP_4_IC_CTRL (CIF_EP_IC_1S3_CTRL)
+
+/** \brief 2D20, Extra Path Image Cropping Camera Displacement Register */
+#define CIF_EP_IC_1S3_DISPLACE /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_DISPLACE*)0xF90E4C20u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S3_DISPLACE.
+* To use register names with standard convension, please use CIF_EP_IC_1S3_DISPLACE.
+*/
+#define CIFEP_4_IC_DISPLACE (CIF_EP_IC_1S3_DISPLACE)
+
+/** \brief 2D08, Extra Path Image Cropping Horizontal Offset of Output Window
+ * Register */
+#define CIF_EP_IC_1S3_H_OFFS /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_H_OFFS*)0xF90E4C08u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S3_H_OFFS.
+* To use register names with standard convension, please use CIF_EP_IC_1S3_H_OFFS.
+*/
+#define CIFEP_4_IC_H_OFFS (CIF_EP_IC_1S3_H_OFFS)
+
+/** \brief 2D24, Extra Path Image Current Horizontal Offset Of Output Window
+ * Shadow Register */
+#define CIF_EP_IC_1S3_H_OFFS_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_H_OFFS_SHD*)0xF90E4C24u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S3_H_OFFS_SHD.
+* To use register names with standard convension, please use CIF_EP_IC_1S3_H_OFFS_SHD.
+*/
+#define CIFEP_4_IC_H_OFFS_SHD (CIF_EP_IC_1S3_H_OFFS_SHD)
+
+/** \brief 2D10, Extra Path Image Cropping Output Horizontal Picture Size
+ * Register */
+#define CIF_EP_IC_1S3_H_SIZE /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_H_SIZE*)0xF90E4C10u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S3_H_SIZE.
+* To use register names with standard convension, please use CIF_EP_IC_1S3_H_SIZE.
+*/
+#define CIFEP_4_IC_H_SIZE (CIF_EP_IC_1S3_H_SIZE)
+
+/** \brief 2D2C, Extra Path Image Current Output Horizontal Picture Size Shadow
+ * Register */
+#define CIF_EP_IC_1S3_H_SIZE_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_H_SIZE_SHD*)0xF90E4C2Cu)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S3_H_SIZE_SHD.
+* To use register names with standard convension, please use CIF_EP_IC_1S3_H_SIZE_SHD.
+*/
+#define CIFEP_4_IC_H_SIZE_SHD (CIF_EP_IC_1S3_H_SIZE_SHD)
+
+/** \brief 2D18, Extra Path Image Cropping Maximum Horizontal Displacement
+ * Register */
+#define CIF_EP_IC_1S3_MAX_DX /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_MAX_DX*)0xF90E4C18u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S3_MAX_DX.
+* To use register names with standard convension, please use CIF_EP_IC_1S3_MAX_DX.
+*/
+#define CIFEP_4_IC_MAX_DX (CIF_EP_IC_1S3_MAX_DX)
+
+/** \brief 2D1C, Extra Path Image Cropping Maximum Vertical Displacement
+ * Register */
+#define CIF_EP_IC_1S3_MAX_DY /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_MAX_DY*)0xF90E4C1Cu)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S3_MAX_DY.
+* To use register names with standard convension, please use CIF_EP_IC_1S3_MAX_DY.
+*/
+#define CIFEP_4_IC_MAX_DY (CIF_EP_IC_1S3_MAX_DY)
+
+/** \brief 2D04, Extra Path Image Cropping Recenter Register */
+#define CIF_EP_IC_1S3_RECENTER /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_RECENTER*)0xF90E4C04u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S3_RECENTER.
+* To use register names with standard convension, please use CIF_EP_IC_1S3_RECENTER.
+*/
+#define CIFEP_4_IC_RECENTER (CIF_EP_IC_1S3_RECENTER)
+
+/** \brief 2D0C, Extra Path Image Cropping Vertical Offset Of Output Window
+ * Register */
+#define CIF_EP_IC_1S3_V_OFFS /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_V_OFFS*)0xF90E4C0Cu)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S3_V_OFFS.
+* To use register names with standard convension, please use CIF_EP_IC_1S3_V_OFFS.
+*/
+#define CIFEP_4_IC_V_OFFS (CIF_EP_IC_1S3_V_OFFS)
+
+/** \brief 2D28, Extra Path Image Current Vertical Offset Of Output Window
+ * Shadow Register */
+#define CIF_EP_IC_1S3_V_OFFS_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_V_OFFS_SHD*)0xF90E4C28u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S3_V_OFFS_SHD.
+* To use register names with standard convension, please use CIF_EP_IC_1S3_V_OFFS_SHD.
+*/
+#define CIFEP_4_IC_V_OFFS_SHD (CIF_EP_IC_1S3_V_OFFS_SHD)
+
+/** \brief 2D14, Extra Path Image Cropping Output Vertical Picture Size
+ * Register */
+#define CIF_EP_IC_1S3_V_SIZE /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_V_SIZE*)0xF90E4C14u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S3_V_SIZE.
+* To use register names with standard convension, please use CIF_EP_IC_1S3_V_SIZE.
+*/
+#define CIFEP_4_IC_V_SIZE (CIF_EP_IC_1S3_V_SIZE)
+
+/** \brief 2D30, Extra Path Image Current Output Vertical Picture Size Shadow
+ * Register */
+#define CIF_EP_IC_1S3_V_SIZE_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_V_SIZE_SHD*)0xF90E4C30u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S3_V_SIZE_SHD.
+* To use register names with standard convension, please use CIF_EP_IC_1S3_V_SIZE_SHD.
+*/
+#define CIFEP_4_IC_V_SIZE_SHD (CIF_EP_IC_1S3_V_SIZE_SHD)
+
+/** \brief 2E00, Extra Path Image Cropping Control Register */
+#define CIF_EP_IC_1S4_CTRL /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_CTRL*)0xF90E4D00u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S4_CTRL.
+* To use register names with standard convension, please use CIF_EP_IC_1S4_CTRL.
+*/
+#define CIFEP_5_IC_CTRL (CIF_EP_IC_1S4_CTRL)
+
+/** \brief 2E20, Extra Path Image Cropping Camera Displacement Register */
+#define CIF_EP_IC_1S4_DISPLACE /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_DISPLACE*)0xF90E4D20u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S4_DISPLACE.
+* To use register names with standard convension, please use CIF_EP_IC_1S4_DISPLACE.
+*/
+#define CIFEP_5_IC_DISPLACE (CIF_EP_IC_1S4_DISPLACE)
+
+/** \brief 2E08, Extra Path Image Cropping Horizontal Offset of Output Window
+ * Register */
+#define CIF_EP_IC_1S4_H_OFFS /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_H_OFFS*)0xF90E4D08u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S4_H_OFFS.
+* To use register names with standard convension, please use CIF_EP_IC_1S4_H_OFFS.
+*/
+#define CIFEP_5_IC_H_OFFS (CIF_EP_IC_1S4_H_OFFS)
+
+/** \brief 2E24, Extra Path Image Current Horizontal Offset Of Output Window
+ * Shadow Register */
+#define CIF_EP_IC_1S4_H_OFFS_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_H_OFFS_SHD*)0xF90E4D24u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S4_H_OFFS_SHD.
+* To use register names with standard convension, please use CIF_EP_IC_1S4_H_OFFS_SHD.
+*/
+#define CIFEP_5_IC_H_OFFS_SHD (CIF_EP_IC_1S4_H_OFFS_SHD)
+
+/** \brief 2E10, Extra Path Image Cropping Output Horizontal Picture Size
+ * Register */
+#define CIF_EP_IC_1S4_H_SIZE /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_H_SIZE*)0xF90E4D10u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S4_H_SIZE.
+* To use register names with standard convension, please use CIF_EP_IC_1S4_H_SIZE.
+*/
+#define CIFEP_5_IC_H_SIZE (CIF_EP_IC_1S4_H_SIZE)
+
+/** \brief 2E2C, Extra Path Image Current Output Horizontal Picture Size Shadow
+ * Register */
+#define CIF_EP_IC_1S4_H_SIZE_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_H_SIZE_SHD*)0xF90E4D2Cu)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S4_H_SIZE_SHD.
+* To use register names with standard convension, please use CIF_EP_IC_1S4_H_SIZE_SHD.
+*/
+#define CIFEP_5_IC_H_SIZE_SHD (CIF_EP_IC_1S4_H_SIZE_SHD)
+
+/** \brief 2E18, Extra Path Image Cropping Maximum Horizontal Displacement
+ * Register */
+#define CIF_EP_IC_1S4_MAX_DX /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_MAX_DX*)0xF90E4D18u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S4_MAX_DX.
+* To use register names with standard convension, please use CIF_EP_IC_1S4_MAX_DX.
+*/
+#define CIFEP_5_IC_MAX_DX (CIF_EP_IC_1S4_MAX_DX)
+
+/** \brief 2E1C, Extra Path Image Cropping Maximum Vertical Displacement
+ * Register */
+#define CIF_EP_IC_1S4_MAX_DY /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_MAX_DY*)0xF90E4D1Cu)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S4_MAX_DY.
+* To use register names with standard convension, please use CIF_EP_IC_1S4_MAX_DY.
+*/
+#define CIFEP_5_IC_MAX_DY (CIF_EP_IC_1S4_MAX_DY)
+
+/** \brief 2E04, Extra Path Image Cropping Recenter Register */
+#define CIF_EP_IC_1S4_RECENTER /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_RECENTER*)0xF90E4D04u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S4_RECENTER.
+* To use register names with standard convension, please use CIF_EP_IC_1S4_RECENTER.
+*/
+#define CIFEP_5_IC_RECENTER (CIF_EP_IC_1S4_RECENTER)
+
+/** \brief 2E0C, Extra Path Image Cropping Vertical Offset Of Output Window
+ * Register */
+#define CIF_EP_IC_1S4_V_OFFS /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_V_OFFS*)0xF90E4D0Cu)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S4_V_OFFS.
+* To use register names with standard convension, please use CIF_EP_IC_1S4_V_OFFS.
+*/
+#define CIFEP_5_IC_V_OFFS (CIF_EP_IC_1S4_V_OFFS)
+
+/** \brief 2E28, Extra Path Image Current Vertical Offset Of Output Window
+ * Shadow Register */
+#define CIF_EP_IC_1S4_V_OFFS_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_V_OFFS_SHD*)0xF90E4D28u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S4_V_OFFS_SHD.
+* To use register names with standard convension, please use CIF_EP_IC_1S4_V_OFFS_SHD.
+*/
+#define CIFEP_5_IC_V_OFFS_SHD (CIF_EP_IC_1S4_V_OFFS_SHD)
+
+/** \brief 2E14, Extra Path Image Cropping Output Vertical Picture Size
+ * Register */
+#define CIF_EP_IC_1S4_V_SIZE /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_V_SIZE*)0xF90E4D14u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S4_V_SIZE.
+* To use register names with standard convension, please use CIF_EP_IC_1S4_V_SIZE.
+*/
+#define CIFEP_5_IC_V_SIZE (CIF_EP_IC_1S4_V_SIZE)
+
+/** \brief 2E30, Extra Path Image Current Output Vertical Picture Size Shadow
+ * Register */
+#define CIF_EP_IC_1S4_V_SIZE_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_EP_IC_V_SIZE_SHD*)0xF90E4D30u)
+
+/** Alias (User Manual Name) for CIF_EP_IC_1S4_V_SIZE_SHD.
+* To use register names with standard convension, please use CIF_EP_IC_1S4_V_SIZE_SHD.
+*/
+#define CIFEP_5_IC_V_SIZE_SHD (CIF_EP_IC_1S4_V_SIZE_SHD)
+
+/** \brief 110, CIF Internal Clock Control Register */
+#define CIF_ICCL /*lint --e(923)*/ (*(volatile Ifx_CIF_ICCL*)0xF90E2010u)
+
+/** \brief 108, CIF Revision Identification Register */
+#define CIF_ID /*lint --e(923)*/ (*(volatile Ifx_CIF_ID*)0xF90E2008u)
+
+/** \brief 114, CIF Internal Reset Control Register */
+#define CIF_IRCL /*lint --e(923)*/ (*(volatile Ifx_CIF_IRCL*)0xF90E2014u)
+
+/** \brief 508, ISP Acquisition Horizontal Offset Register */
+#define CIF_ISP_ACQ_H_OFFS /*lint --e(923)*/ (*(volatile Ifx_CIF_ISP_ACQ_H_OFFS*)0xF90E2408u)
+
+/** Alias (User Manual Name) for CIF_ISP_ACQ_H_OFFS.
+* To use register names with standard convension, please use CIF_ISP_ACQ_H_OFFS.
+*/
+#define CIFISP_ACQ_H_OFFS (CIF_ISP_ACQ_H_OFFS)
+
+/** \brief 510, ISP Acquisition Horizontal Size Register */
+#define CIF_ISP_ACQ_H_SIZE /*lint --e(923)*/ (*(volatile Ifx_CIF_ISP_ACQ_H_SIZE*)0xF90E2410u)
+
+/** Alias (User Manual Name) for CIF_ISP_ACQ_H_SIZE.
+* To use register names with standard convension, please use CIF_ISP_ACQ_H_SIZE.
+*/
+#define CIFISP_ACQ_H_SIZE (CIF_ISP_ACQ_H_SIZE)
+
+/** \brief 518, ISP Acquisition Number of Frames Register */
+#define CIF_ISP_ACQ_NR_FRAMES /*lint --e(923)*/ (*(volatile Ifx_CIF_ISP_ACQ_NR_FRAMES*)0xF90E2418u)
+
+/** Alias (User Manual Name) for CIF_ISP_ACQ_NR_FRAMES.
+* To use register names with standard convension, please use CIF_ISP_ACQ_NR_FRAMES.
+*/
+#define CIFISP_ACQ_NR_FRAMES (CIF_ISP_ACQ_NR_FRAMES)
+
+/** \brief 504, ISP Acquisition Properties Register */
+#define CIF_ISP_ACQ_PROP /*lint --e(923)*/ (*(volatile Ifx_CIF_ISP_ACQ_PROP*)0xF90E2404u)
+
+/** Alias (User Manual Name) for CIF_ISP_ACQ_PROP.
+* To use register names with standard convension, please use CIF_ISP_ACQ_PROP.
+*/
+#define CIFISP_ACQ_PROP (CIF_ISP_ACQ_PROP)
+
+/** \brief 50C, ISP Acquistion Vertical Offset Register */
+#define CIF_ISP_ACQ_V_OFFS /*lint --e(923)*/ (*(volatile Ifx_CIF_ISP_ACQ_V_OFFS*)0xF90E240Cu)
+
+/** Alias (User Manual Name) for CIF_ISP_ACQ_V_OFFS.
+* To use register names with standard convension, please use CIF_ISP_ACQ_V_OFFS.
+*/
+#define CIFISP_ACQ_V_OFFS (CIF_ISP_ACQ_V_OFFS)
+
+/** \brief 514, ISP Acquisition Vertical Size Register */
+#define CIF_ISP_ACQ_V_SIZE /*lint --e(923)*/ (*(volatile Ifx_CIF_ISP_ACQ_V_SIZE*)0xF90E2414u)
+
+/** Alias (User Manual Name) for CIF_ISP_ACQ_V_SIZE.
+* To use register names with standard convension, please use CIF_ISP_ACQ_V_SIZE.
+*/
+#define CIFISP_ACQ_V_SIZE (CIF_ISP_ACQ_V_SIZE)
+
+/** \brief 500, ISP Global Control Register */
+#define CIF_ISP_CTRL /*lint --e(923)*/ (*(volatile Ifx_CIF_ISP_CTRL*)0xF90E2400u)
+
+/** Alias (User Manual Name) for CIF_ISP_CTRL.
+* To use register names with standard convension, please use CIF_ISP_CTRL.
+*/
+#define CIFISP_CTRL (CIF_ISP_CTRL)
+
+/** \brief 73C, ISP Error Register */
+#define CIF_ISP_ERR /*lint --e(923)*/ (*(volatile Ifx_CIF_ISP_ERR*)0xF90E263Cu)
+
+/** Alias (User Manual Name) for CIF_ISP_ERR.
+* To use register names with standard convension, please use CIF_ISP_ERR.
+*/
+#define CIFISP_ERR (CIF_ISP_ERR)
+
+/** \brief 740, ISP Error Clear Register */
+#define CIF_ISP_ERR_CLR /*lint --e(923)*/ (*(volatile Ifx_CIF_ISP_ERR_CLR*)0xF90E2640u)
+
+/** Alias (User Manual Name) for CIF_ISP_ERR_CLR.
+* To use register names with standard convension, please use CIF_ISP_ERR_CLR.
+*/
+#define CIFISP_ERR_CLR (CIF_ISP_ERR_CLR)
+
+/** \brief 6A8, ISP Shadow Flags Register */
+#define CIF_ISP_FLAGS_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_ISP_FLAGS_SHD*)0xF90E25A8u)
+
+/** Alias (User Manual Name) for CIF_ISP_FLAGS_SHD.
+* To use register names with standard convension, please use CIF_ISP_FLAGS_SHD.
+*/
+#define CIFISP_FLAGS_SHD (CIF_ISP_FLAGS_SHD)
+
+/** \brief 744, ISP Frame Counter Register */
+#define CIF_ISP_FRAME_COUNT /*lint --e(923)*/ (*(volatile Ifx_CIF_ISP_FRAME_COUNT*)0xF90E2644u)
+
+/** Alias (User Manual Name) for CIF_ISP_FRAME_COUNT.
+* To use register names with standard convension, please use CIF_ISP_FRAME_COUNT.
+*/
+#define CIFISP_FRAME_COUNT (CIF_ISP_FRAME_COUNT)
+
+/** \brief 6C8, ISP Interrupt Clear Register */
+#define CIF_ISP_ICR /*lint --e(923)*/ (*(volatile Ifx_CIF_ISP_ICR*)0xF90E25C8u)
+
+/** Alias (User Manual Name) for CIF_ISP_ICR.
+* To use register names with standard convension, please use CIF_ISP_ICR.
+*/
+#define CIFISP_ICR (CIF_ISP_ICR)
+
+/** \brief 6BC, ISP Interrupt Mask Register */
+#define CIF_ISP_IMSC /*lint --e(923)*/ (*(volatile Ifx_CIF_ISP_IMSC*)0xF90E25BCu)
+
+/** Alias (User Manual Name) for CIF_ISP_IMSC.
+* To use register names with standard convension, please use CIF_ISP_IMSC.
+*/
+#define CIFISP_IMSC (CIF_ISP_IMSC)
+
+/** \brief 6CC, ISP Interrupt Set Register */
+#define CIF_ISP_ISR /*lint --e(923)*/ (*(volatile Ifx_CIF_ISP_ISR*)0xF90E25CCu)
+
+/** Alias (User Manual Name) for CIF_ISP_ISR.
+* To use register names with standard convension, please use CIF_ISP_ISR.
+*/
+#define CIFISP_ISR (CIF_ISP_ISR)
+
+/** \brief 6C4, ISP Masked Interrupt Status Register */
+#define CIF_ISP_MIS /*lint --e(923)*/ (*(volatile Ifx_CIF_ISP_MIS*)0xF90E25C4u)
+
+/** Alias (User Manual Name) for CIF_ISP_MIS.
+* To use register names with standard convension, please use CIF_ISP_MIS.
+*/
+#define CIFISP_MIS (CIF_ISP_MIS)
+
+/** \brief 694, ISP Output Window Horizontal Offset Register */
+#define CIF_ISP_OUT_H_OFFS /*lint --e(923)*/ (*(volatile Ifx_CIF_ISP_OUT_H_OFFS*)0xF90E2594u)
+
+/** Alias (User Manual Name) for CIF_ISP_OUT_H_OFFS.
+* To use register names with standard convension, please use CIF_ISP_OUT_H_OFFS.
+*/
+#define CIFISP_OUT_H_OFFS (CIF_ISP_OUT_H_OFFS)
+
+/** \brief 6AC, ISP Output Window Horizontal Offset Shadow Register */
+#define CIF_ISP_OUT_H_OFFS_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_ISP_OUT_H_OFFS_SHD*)0xF90E25ACu)
+
+/** Alias (User Manual Name) for CIF_ISP_OUT_H_OFFS_SHD.
+* To use register names with standard convension, please use CIF_ISP_OUT_H_OFFS_SHD.
+*/
+#define CIFISP_OUT_H_OFFS_SHD (CIF_ISP_OUT_H_OFFS_SHD)
+
+/** \brief 69C, ISP Output Horizontal Picture Size Register */
+#define CIF_ISP_OUT_H_SIZE /*lint --e(923)*/ (*(volatile Ifx_CIF_ISP_OUT_H_SIZE*)0xF90E259Cu)
+
+/** Alias (User Manual Name) for CIF_ISP_OUT_H_SIZE.
+* To use register names with standard convension, please use CIF_ISP_OUT_H_SIZE.
+*/
+#define CIFISP_OUT_H_SIZE (CIF_ISP_OUT_H_SIZE)
+
+/** \brief 6B4, ISP Output Horizontal Picture Size Shadow Register */
+#define CIF_ISP_OUT_H_SIZE_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_ISP_OUT_H_SIZE_SHD*)0xF90E25B4u)
+
+/** Alias (User Manual Name) for CIF_ISP_OUT_H_SIZE_SHD.
+* To use register names with standard convension, please use CIF_ISP_OUT_H_SIZE_SHD.
+*/
+#define CIFISP_OUT_H_SIZE_SHD (CIF_ISP_OUT_H_SIZE_SHD)
+
+/** \brief 698, ISP Output Window Vertical Offset Register */
+#define CIF_ISP_OUT_V_OFFS /*lint --e(923)*/ (*(volatile Ifx_CIF_ISP_OUT_V_OFFS*)0xF90E2598u)
+
+/** Alias (User Manual Name) for CIF_ISP_OUT_V_OFFS.
+* To use register names with standard convension, please use CIF_ISP_OUT_V_OFFS.
+*/
+#define CIFISP_OUT_V_OFFS (CIF_ISP_OUT_V_OFFS)
+
+/** \brief 6B0, ISP Output Window Vertical Offset Shadow Register */
+#define CIF_ISP_OUT_V_OFFS_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_ISP_OUT_V_OFFS_SHD*)0xF90E25B0u)
+
+/** Alias (User Manual Name) for CIF_ISP_OUT_V_OFFS_SHD.
+* To use register names with standard convension, please use CIF_ISP_OUT_V_OFFS_SHD.
+*/
+#define CIFISP_OUT_V_OFFS_SHD (CIF_ISP_OUT_V_OFFS_SHD)
+
+/** \brief 6A0, ISP Output Vertical Picture Size Register */
+#define CIF_ISP_OUT_V_SIZE /*lint --e(923)*/ (*(volatile Ifx_CIF_ISP_OUT_V_SIZE*)0xF90E25A0u)
+
+/** Alias (User Manual Name) for CIF_ISP_OUT_V_SIZE.
+* To use register names with standard convension, please use CIF_ISP_OUT_V_SIZE.
+*/
+#define CIFISP_OUT_V_SIZE (CIF_ISP_OUT_V_SIZE)
+
+/** \brief 6B8, ISP Output Vertical Picture Size Shadow Register */
+#define CIF_ISP_OUT_V_SIZE_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_ISP_OUT_V_SIZE_SHD*)0xF90E25B8u)
+
+/** Alias (User Manual Name) for CIF_ISP_OUT_V_SIZE_SHD.
+* To use register names with standard convension, please use CIF_ISP_OUT_V_SIZE_SHD.
+*/
+#define CIFISP_OUT_V_SIZE_SHD (CIF_ISP_OUT_V_SIZE_SHD)
+
+/** \brief 6C0, ISP Raw Interrupt Status Register */
+#define CIF_ISP_RIS /*lint --e(923)*/ (*(volatile Ifx_CIF_ISP_RIS*)0xF90E25C0u)
+
+/** Alias (User Manual Name) for CIF_ISP_RIS.
+* To use register names with standard convension, please use CIF_ISP_RIS.
+*/
+#define CIFISP_RIS (CIF_ISP_RIS)
+
+/** \brief 2400, ISP Image Stabilization Control Register */
+#define CIF_ISPIS_CTRL /*lint --e(923)*/ (*(volatile Ifx_CIF_ISPIS_CTRL*)0xF90E4300u)
+
+/** Alias (User Manual Name) for CIF_ISPIS_CTRL.
+* To use register names with standard convension, please use CIF_ISPIS_CTRL.
+*/
+#define CIFISPIS_CTRL (CIF_ISPIS_CTRL)
+
+/** \brief 2420, ISP Image Stabilization Camera Displacement Register */
+#define CIF_ISPIS_DISPLACE /*lint --e(923)*/ (*(volatile Ifx_CIF_ISPIS_DISPLACE*)0xF90E4320u)
+
+/** Alias (User Manual Name) for CIF_ISPIS_DISPLACE.
+* To use register names with standard convension, please use CIF_ISPIS_DISPLACE.
+*/
+#define CIFISPIS_DISPLACE (CIF_ISPIS_DISPLACE)
+
+/** \brief 2408, ISP Image Stabilization Horizontal Offset Of Output Window
+ * Register */
+#define CIF_ISPIS_H_OFFS /*lint --e(923)*/ (*(volatile Ifx_CIF_ISPIS_H_OFFS*)0xF90E4308u)
+
+/** Alias (User Manual Name) for CIF_ISPIS_H_OFFS.
+* To use register names with standard convension, please use CIF_ISPIS_H_OFFS.
+*/
+#define CIFISPIS_H_OFFS (CIF_ISPIS_H_OFFS)
+
+/** \brief 2424, SP Image Current Horizontal Offset Of Output Window Shadow
+ * Register */
+#define CIF_ISPIS_H_OFFS_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_ISPIS_H_OFFS_SHD*)0xF90E4324u)
+
+/** Alias (User Manual Name) for CIF_ISPIS_H_OFFS_SHD.
+* To use register names with standard convension, please use CIF_ISPIS_H_OFFS_SHD.
+*/
+#define CIFISPIS_H_OFFS_SHD (CIF_ISPIS_H_OFFS_SHD)
+
+/** \brief 2410, ISP Image Stabilization Output Horizontal Picture Size
+ * Register */
+#define CIF_ISPIS_H_SIZE /*lint --e(923)*/ (*(volatile Ifx_CIF_ISPIS_H_SIZE*)0xF90E4310u)
+
+/** Alias (User Manual Name) for CIF_ISPIS_H_SIZE.
+* To use register names with standard convension, please use CIF_ISPIS_H_SIZE.
+*/
+#define CIFISPIS_H_SIZE (CIF_ISPIS_H_SIZE)
+
+/** \brief 242C, ISP Image Current Output Horizontal Picture Size Shadow
+ * Register */
+#define CIF_ISPIS_H_SIZE_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_ISPIS_H_SIZE_SHD*)0xF90E432Cu)
+
+/** Alias (User Manual Name) for CIF_ISPIS_H_SIZE_SHD.
+* To use register names with standard convension, please use CIF_ISPIS_H_SIZE_SHD.
+*/
+#define CIFISPIS_H_SIZE_SHD (CIF_ISPIS_H_SIZE_SHD)
+
+/** \brief 2418, ISP Image Stabilization Maximum Horizontal Displacement
+ * Register */
+#define CIF_ISPIS_MAX_DX /*lint --e(923)*/ (*(volatile Ifx_CIF_ISPIS_MAX_DX*)0xF90E4318u)
+
+/** Alias (User Manual Name) for CIF_ISPIS_MAX_DX.
+* To use register names with standard convension, please use CIF_ISPIS_MAX_DX.
+*/
+#define CIFISPIS_MAX_DX (CIF_ISPIS_MAX_DX)
+
+/** \brief 241C, ISP Image Stabilization Maximum Vertical Displacement Register */
+#define CIF_ISPIS_MAX_DY /*lint --e(923)*/ (*(volatile Ifx_CIF_ISPIS_MAX_DY*)0xF90E431Cu)
+
+/** Alias (User Manual Name) for CIF_ISPIS_MAX_DY.
+* To use register names with standard convension, please use CIF_ISPIS_MAX_DY.
+*/
+#define CIFISPIS_MAX_DY (CIF_ISPIS_MAX_DY)
+
+/** \brief 2404, ISP Image Stabilization Recenter Register */
+#define CIF_ISPIS_RECENTER /*lint --e(923)*/ (*(volatile Ifx_CIF_ISPIS_RECENTER*)0xF90E4304u)
+
+/** Alias (User Manual Name) for CIF_ISPIS_RECENTER.
+* To use register names with standard convension, please use CIF_ISPIS_RECENTER.
+*/
+#define CIFISPIS_RECENTER (CIF_ISPIS_RECENTER)
+
+/** \brief 240C, ISP Image Stabilization Vertical Offset Of Output Window
+ * Register */
+#define CIF_ISPIS_V_OFFS /*lint --e(923)*/ (*(volatile Ifx_CIF_ISPIS_V_OFFS*)0xF90E430Cu)
+
+/** Alias (User Manual Name) for CIF_ISPIS_V_OFFS.
+* To use register names with standard convension, please use CIF_ISPIS_V_OFFS.
+*/
+#define CIFISPIS_V_OFFS (CIF_ISPIS_V_OFFS)
+
+/** \brief 2428, ISP Image Current Vertical Offset Of Output Window Shadow
+ * Register */
+#define CIF_ISPIS_V_OFFS_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_ISPIS_V_OFFS_SHD*)0xF90E4328u)
+
+/** Alias (User Manual Name) for CIF_ISPIS_V_OFFS_SHD.
+* To use register names with standard convension, please use CIF_ISPIS_V_OFFS_SHD.
+*/
+#define CIFISPIS_V_OFFS_SHD (CIF_ISPIS_V_OFFS_SHD)
+
+/** \brief 2414, ISP Image Stabilization Output Vertical Picture Size Register */
+#define CIF_ISPIS_V_SIZE /*lint --e(923)*/ (*(volatile Ifx_CIF_ISPIS_V_SIZE*)0xF90E4314u)
+
+/** Alias (User Manual Name) for CIF_ISPIS_V_SIZE.
+* To use register names with standard convension, please use CIF_ISPIS_V_SIZE.
+*/
+#define CIFISPIS_V_SIZE (CIF_ISPIS_V_SIZE)
+
+/** \brief 2430, ISP Image Current Output Vertical Picture Size Shadow Register */
+#define CIF_ISPIS_V_SIZE_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_ISPIS_V_SIZE_SHD*)0xF90E4330u)
+
+/** Alias (User Manual Name) for CIF_ISPIS_V_SIZE_SHD.
+* To use register names with standard convension, please use CIF_ISPIS_V_SIZE_SHD.
+*/
+#define CIFISPIS_V_SIZE_SHD (CIF_ISPIS_V_SIZE_SHD)
+
+/** \brief 1938, JPE Huffman Table Selector For AC Values Register */
+#define CIF_JPE_AC_TABLE_SELECT /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_AC_TABLE_SELECT*)0xF90E3838u)
+
+/** Alias (User Manual Name) for CIF_JPE_AC_TABLE_SELECT.
+* To use register names with standard convension, please use CIF_JPE_AC_TABLE_SELECT.
+*/
+#define CIFJPE_AC_TABLE_SELECT (CIF_JPE_AC_TABLE_SELECT)
+
+/** \brief 1910, JPE Cb/Cr Value Scaling Control Register */
+#define CIF_JPE_CBCR_SCALE_EN /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_CBCR_SCALE_EN*)0xF90E3810u)
+
+/** Alias (User Manual Name) for CIF_JPE_CBCR_SCALE_EN.
+* To use register names with standard convension, please use CIF_JPE_CBCR_SCALE_EN.
+*/
+#define CIFJPE_CBCR_SCALE_EN (CIF_JPE_CBCR_SCALE_EN)
+
+/** \brief 1934, JPE Huffman Table Selector For DC Values Register */
+#define CIF_JPE_DC_TABLE_SELECT /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_DC_TABLE_SELECT*)0xF90E3834u)
+
+/** Alias (User Manual Name) for CIF_JPE_DC_TABLE_SELECT.
+* To use register names with standard convension, please use CIF_JPE_DC_TABLE_SELECT.
+*/
+#define CIFJPE_DC_TABLE_SELECT (CIF_JPE_DC_TABLE_SELECT)
+
+/** \brief 1964, JPE Debug Information Register */
+#define CIF_JPE_DEBUG /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_DEBUG*)0xF90E3864u)
+
+/** Alias (User Manual Name) for CIF_JPE_DEBUG.
+* To use register names with standard convension, please use CIF_JPE_DEBUG.
+*/
+#define CIFJPE_DEBUG (CIF_JPE_DEBUG)
+
+/** \brief 1918, JPEG Codec Horizontal Image Size For Encoding Register */
+#define CIF_JPE_ENC_HSIZE /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_ENC_HSIZE*)0xF90E3818u)
+
+/** Alias (User Manual Name) for CIF_JPE_ENC_HSIZE.
+* To use register names with standard convension, please use CIF_JPE_ENC_HSIZE.
+*/
+#define CIFJPE_ENC_HSIZE (CIF_JPE_ENC_HSIZE)
+
+/** \brief 191C, JPEG Codec Vertical Image Size For Encoding Register */
+#define CIF_JPE_ENC_VSIZE /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_ENC_VSIZE*)0xF90E381Cu)
+
+/** Alias (User Manual Name) for CIF_JPE_ENC_VSIZE.
+* To use register names with standard convension, please use CIF_JPE_ENC_VSIZE.
+*/
+#define CIFJPE_ENC_VSIZE (CIF_JPE_ENC_VSIZE)
+
+/** \brief 1904, JPE Start Command To Start JFIF Stream Encoding Register */
+#define CIF_JPE_ENCODE /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_ENCODE*)0xF90E3804u)
+
+/** Alias (User Manual Name) for CIF_JPE_ENCODE.
+* To use register names with standard convension, please use CIF_JPE_ENCODE.
+*/
+#define CIFJPE_ENCODE (CIF_JPE_ENCODE)
+
+/** \brief 1960, JPE Encode Mode Register */
+#define CIF_JPE_ENCODE_MODE /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_ENCODE_MODE*)0xF90E3860u)
+
+/** Alias (User Manual Name) for CIF_JPE_ENCODE_MODE.
+* To use register names with standard convension, please use CIF_JPE_ENCODE_MODE.
+*/
+#define CIFJPE_ENCODE_MODE (CIF_JPE_ENCODE_MODE)
+
+/** \brief 1958, JPE Encoder Status Flag Register */
+#define CIF_JPE_ENCODER_BUSY /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_ENCODER_BUSY*)0xF90E3858u)
+
+/** Alias (User Manual Name) for CIF_JPE_ENCODER_BUSY.
+* To use register names with standard convension, please use CIF_JPE_ENCODER_BUSY.
+*/
+#define CIFJPE_ENCODER_BUSY (CIF_JPE_ENCODER_BUSY)
+
+/** \brief 1974, JPE Error Interrupt Clear Register */
+#define CIF_JPE_ERROR_ICR /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_ERROR_ICR*)0xF90E3874u)
+
+/** Alias (User Manual Name) for CIF_JPE_ERROR_ICR.
+* To use register names with standard convension, please use CIF_JPE_ERROR_ICR.
+*/
+#define CIFJPE_ERROR_ICR (CIF_JPE_ERROR_ICR)
+
+/** \brief 1968, JPE Error Interrupt Mask Register */
+#define CIF_JPE_ERROR_IMR /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_ERROR_IMR*)0xF90E3868u)
+
+/** Alias (User Manual Name) for CIF_JPE_ERROR_IMR.
+* To use register names with standard convension, please use CIF_JPE_ERROR_IMR.
+*/
+#define CIFJPE_ERROR_IMR (CIF_JPE_ERROR_IMR)
+
+/** \brief 1978, JPE Error Interrupt Set Register */
+#define CIF_JPE_ERROR_ISR /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_ERROR_ISR*)0xF90E3878u)
+
+/** Alias (User Manual Name) for CIF_JPE_ERROR_ISR.
+* To use register names with standard convension, please use CIF_JPE_ERROR_ISR.
+*/
+#define CIFJPE_ERROR_ISR (CIF_JPE_ERROR_ISR)
+
+/** \brief 1970, JPE Error Masked Interrupt Status Register */
+#define CIF_JPE_ERROR_MIS /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_ERROR_MIS*)0xF90E3870u)
+
+/** Alias (User Manual Name) for CIF_JPE_ERROR_MIS.
+* To use register names with standard convension, please use CIF_JPE_ERROR_MIS.
+*/
+#define CIFJPE_ERROR_MIS (CIF_JPE_ERROR_MIS)
+
+/** \brief 196C, JPE Error Raw Interrupt Status Register */
+#define CIF_JPE_ERROR_RIS /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_ERROR_RIS*)0xF90E386Cu)
+
+/** Alias (User Manual Name) for CIF_JPE_ERROR_RIS.
+* To use register names with standard convension, please use CIF_JPE_ERROR_RIS.
+*/
+#define CIFJPE_ERROR_RIS (CIF_JPE_ERROR_RIS)
+
+/** \brief 1900, JPE Command To Start Stream Header Generation Register */
+#define CIF_JPE_GEN_HEADER /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_GEN_HEADER*)0xF90E3800u)
+
+/** Alias (User Manual Name) for CIF_JPE_GEN_HEADER.
+* To use register names with standard convension, please use CIF_JPE_GEN_HEADER.
+*/
+#define CIFJPE_GEN_HEADER (CIF_JPE_GEN_HEADER)
+
+/** \brief 195C, JPE Header Mode Definition Register */
+#define CIF_JPE_HEADER_MODE /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_HEADER_MODE*)0xF90E385Cu)
+
+/** Alias (User Manual Name) for CIF_JPE_HEADER_MODE.
+* To use register names with standard convension, please use CIF_JPE_HEADER_MODE.
+*/
+#define CIFJPE_HEADER_MODE (CIF_JPE_HEADER_MODE)
+
+/** \brief 1908, JPE Automatic Configuration Update Register */
+#define CIF_JPE_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_INIT*)0xF90E3808u)
+
+/** Alias (User Manual Name) for CIF_JPE_INIT.
+* To use register names with standard convension, please use CIF_JPE_INIT.
+*/
+#define CIFJPE_INIT (CIF_JPE_INIT)
+
+/** \brief 1920, JPEG Picture Encoding Format Register */
+#define CIF_JPE_PIC_FORMAT /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_PIC_FORMAT*)0xF90E3820u)
+
+/** Alias (User Manual Name) for CIF_JPE_PIC_FORMAT.
+* To use register names with standard convension, please use CIF_JPE_PIC_FORMAT.
+*/
+#define CIFJPE_PIC_FORMAT (CIF_JPE_PIC_FORMAT)
+
+/** \brief 1924, JPE Restart Marker Insertion Register */
+#define CIF_JPE_RESTART_INTERVAL /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_RESTART_INTERVAL*)0xF90E3824u)
+
+/** Alias (User Manual Name) for CIF_JPE_RESTART_INTERVAL.
+* To use register names with standard convension, please use CIF_JPE_RESTART_INTERVAL.
+*/
+#define CIFJPE_RESTART_INTERVAL (CIF_JPE_RESTART_INTERVAL)
+
+/** \brief 1988, JPEG Status Interrupt Clear Register */
+#define CIF_JPE_STATUS_ICR /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_STATUS_ICR*)0xF90E3888u)
+
+/** Alias (User Manual Name) for CIF_JPE_STATUS_ICR.
+* To use register names with standard convension, please use CIF_JPE_STATUS_ICR.
+*/
+#define CIFJPE_STATUS_ICR (CIF_JPE_STATUS_ICR)
+
+/** \brief 197C, JPEG Status Interrupt Mask Register */
+#define CIF_JPE_STATUS_IMR /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_STATUS_IMR*)0xF90E387Cu)
+
+/** Alias (User Manual Name) for CIF_JPE_STATUS_IMR.
+* To use register names with standard convension, please use CIF_JPE_STATUS_IMR.
+*/
+#define CIFJPE_STATUS_IMR (CIF_JPE_STATUS_IMR)
+
+/** \brief 198C, JPEG Status Interrupt Set Register */
+#define CIF_JPE_STATUS_ISR /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_STATUS_ISR*)0xF90E388Cu)
+
+/** Alias (User Manual Name) for CIF_JPE_STATUS_ISR.
+* To use register names with standard convension, please use CIF_JPE_STATUS_ISR.
+*/
+#define CIFJPE_STATUS_ISR (CIF_JPE_STATUS_ISR)
+
+/** \brief 1984, JPEG Status Masked Interrupt Status Register */
+#define CIF_JPE_STATUS_MIS /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_STATUS_MIS*)0xF90E3884u)
+
+/** Alias (User Manual Name) for CIF_JPE_STATUS_MIS.
+* To use register names with standard convension, please use CIF_JPE_STATUS_MIS.
+*/
+#define CIFJPE_STATUS_MIS (CIF_JPE_STATUS_MIS)
+
+/** \brief 1980, JPEG Status Raw Interrupt Status Register */
+#define CIF_JPE_STATUS_RIS /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_STATUS_RIS*)0xF90E3880u)
+
+/** Alias (User Manual Name) for CIF_JPE_STATUS_RIS.
+* To use register names with standard convension, please use CIF_JPE_STATUS_RIS.
+*/
+#define CIFJPE_STATUS_RIS (CIF_JPE_STATUS_RIS)
+
+/** \brief 193C, JPE Table Programming Register */
+#define CIF_JPE_TABLE_DATA /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_TABLE_DATA*)0xF90E383Cu)
+
+/** Alias (User Manual Name) for CIF_JPE_TABLE_DATA.
+* To use register names with standard convension, please use CIF_JPE_TABLE_DATA.
+*/
+#define CIFJPE_TABLE_DATA (CIF_JPE_TABLE_DATA)
+
+/** \brief 1914, JPE Header Generation Debug Register */
+#define CIF_JPE_TABLE_FLUSH /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_TABLE_FLUSH*)0xF90E3814u)
+
+/** Alias (User Manual Name) for CIF_JPE_TABLE_FLUSH.
+* To use register names with standard convension, please use CIF_JPE_TABLE_FLUSH.
+*/
+#define CIFJPE_TABLE_FLUSH (CIF_JPE_TABLE_FLUSH)
+
+/** \brief 1940, JPE Table Programming Select Register */
+#define CIF_JPE_TABLE_ID /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_TABLE_ID*)0xF90E3840u)
+
+/** Alias (User Manual Name) for CIF_JPE_TABLE_ID.
+* To use register names with standard convension, please use CIF_JPE_TABLE_ID.
+*/
+#define CIFJPE_TABLE_ID (CIF_JPE_TABLE_ID)
+
+/** \brief 1944, JPE Huffman AC Table 0 Length Register */
+#define CIF_JPE_TAC0_LEN /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_TAC0_LEN*)0xF90E3844u)
+
+/** Alias (User Manual Name) for CIF_JPE_TAC0_LEN.
+* To use register names with standard convension, please use CIF_JPE_TAC0_LEN.
+*/
+#define CIFJPE_TAC0_LEN (CIF_JPE_TAC0_LEN)
+
+/** \brief 194C, JPE Huffman AC Table 1 Length Register */
+#define CIF_JPE_TAC1_LEN /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_TAC1_LEN*)0xF90E384Cu)
+
+/** Alias (User Manual Name) for CIF_JPE_TAC1_LEN.
+* To use register names with standard convension, please use CIF_JPE_TAC1_LEN.
+*/
+#define CIFJPE_TAC1_LEN (CIF_JPE_TAC1_LEN)
+
+/** \brief 1948, JPE Huffman DC Table 0 Length Register */
+#define CIF_JPE_TDC0_LEN /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_TDC0_LEN*)0xF90E3848u)
+
+/** Alias (User Manual Name) for CIF_JPE_TDC0_LEN.
+* To use register names with standard convension, please use CIF_JPE_TDC0_LEN.
+*/
+#define CIFJPE_TDC0_LEN (CIF_JPE_TDC0_LEN)
+
+/** \brief 1950, JPE Huffman DC Table 1 Length Register */
+#define CIF_JPE_TDC1_LEN /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_TDC1_LEN*)0xF90E3850u)
+
+/** Alias (User Manual Name) for CIF_JPE_TDC1_LEN.
+* To use register names with standard convension, please use CIF_JPE_TDC1_LEN.
+*/
+#define CIFJPE_TDC1_LEN (CIF_JPE_TDC1_LEN)
+
+/** \brief 192C, Q- table Selector 1, Quant. Table For U Component */
+#define CIF_JPE_TQ_U_SELECT /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_TQ_U_SELECT*)0xF90E382Cu)
+
+/** Alias (User Manual Name) for CIF_JPE_TQ_U_SELECT.
+* To use register names with standard convension, please use CIF_JPE_TQ_U_SELECT.
+*/
+#define CIFJPE_TQ_U_SELECT (CIF_JPE_TQ_U_SELECT)
+
+/** \brief 1930, Q- table Selector 2 Quant Table For V Component */
+#define CIF_JPE_TQ_V_SELECT /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_TQ_V_SELECT*)0xF90E3830u)
+
+/** Alias (User Manual Name) for CIF_JPE_TQ_V_SELECT.
+* To use register names with standard convension, please use CIF_JPE_TQ_V_SELECT.
+*/
+#define CIFJPE_TQ_V_SELECT (CIF_JPE_TQ_V_SELECT)
+
+/** \brief 1928, Q- table Selector 0 Quant Table For Y Component */
+#define CIF_JPE_TQ_Y_SELECT /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_TQ_Y_SELECT*)0xF90E3828u)
+
+/** Alias (User Manual Name) for CIF_JPE_TQ_Y_SELECT.
+* To use register names with standard convension, please use CIF_JPE_TQ_Y_SELECT.
+*/
+#define CIFJPE_TQ_Y_SELECT (CIF_JPE_TQ_Y_SELECT)
+
+/** \brief 190C, JPE Y Value Scaling Control Register */
+#define CIF_JPE_Y_SCALE_EN /*lint --e(923)*/ (*(volatile Ifx_CIF_JPE_Y_SCALE_EN*)0xF90E380Cu)
+
+/** Alias (User Manual Name) for CIF_JPE_Y_SCALE_EN.
+* To use register names with standard convension, please use CIF_JPE_Y_SCALE_EN.
+*/
+#define CIFJPE_Y_SCALE_EN (CIF_JPE_Y_SCALE_EN)
+
+/** \brief 2600, Linear Downscaler Control Register */
+#define CIF_LDS_CTRL /*lint --e(923)*/ (*(volatile Ifx_CIF_LDS_CTRL*)0xF90E4500u)
+
+/** Alias (User Manual Name) for CIF_LDS_CTRL.
+* To use register names with standard convension, please use CIF_LDS_CTRL.
+*/
+#define CIFLDS_CTRL (CIF_LDS_CTRL)
+
+/** \brief 2604, Linear Downscaler Factor Register */
+#define CIF_LDS_FAC /*lint --e(923)*/ (*(volatile Ifx_CIF_LDS_FAC*)0xF90E4504u)
+
+/** Alias (User Manual Name) for CIF_LDS_FAC.
+* To use register names with standard convension, please use CIF_LDS_FAC.
+*/
+#define CIFLDS_FAC (CIF_LDS_FAC)
+
+/** \brief 1570, Memory Interface Counter Value of JPEG or RAW Data Bytes
+ * Register */
+#define CIF_MI_BYTE_CNT /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_BYTE_CNT*)0xF90E3470u)
+
+/** Alias (User Manual Name) for CIF_MI_BYTE_CNT.
+* To use register names with standard convension, please use CIF_MI_BYTE_CNT.
+*/
+#define CIFMI_BYTE_CNT (CIF_MI_BYTE_CNT)
+
+/** \brief 1500, Memory Interface Global Control Register */
+#define CIF_MI_CTRL /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_CTRL*)0xF90E3400u)
+
+/** Alias (User Manual Name) for CIF_MI_CTRL.
+* To use register names with standard convension, please use CIF_MI_CTRL.
+*/
+#define CIFMI_CTRL (CIF_MI_CTRL)
+
+/** \brief 1574, Memory Interface Global Control Internal Shadow Register */
+#define CIF_MI_CTRL_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_CTRL_SHD*)0xF90E3474u)
+
+/** Alias (User Manual Name) for CIF_MI_CTRL_SHD.
+* To use register names with standard convension, please use CIF_MI_CTRL_SHD.
+*/
+#define CIFMI_CTRL_SHD (CIF_MI_CTRL_SHD)
+
+/** \brief 1604, MI Interrupt Clear Register */
+#define CIF_MI_ICR /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_ICR*)0xF90E3504u)
+
+/** Alias (User Manual Name) for CIF_MI_ICR.
+* To use register names with standard convension, please use CIF_MI_ICR.
+*/
+#define CIFMI_ICR (CIF_MI_ICR)
+
+/** \brief 15F8, MI Interrupt Mask ‘1’ interrupt active ‘0’ interrupt masked */
+#define CIF_MI_IMSC /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_IMSC*)0xF90E34F8u)
+
+/** Alias (User Manual Name) for CIF_MI_IMSC.
+* To use register names with standard convension, please use CIF_MI_IMSC.
+*/
+#define CIFMI_IMSC (CIF_MI_IMSC)
+
+/** \brief 1504, Memory Interface Control Register For Address Init And Skip
+ * Function Register */
+#define CIF_MI_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_INIT*)0xF90E3404u)
+
+/** Alias (User Manual Name) for CIF_MI_INIT.
+* To use register names with standard convension, please use CIF_MI_INIT.
+*/
+#define CIFMI_INIT (CIF_MI_INIT)
+
+/** \brief 1608, MI Interrupt Set Register */
+#define CIF_MI_ISR /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_ISR*)0xF90E3508u)
+
+/** Alias (User Manual Name) for CIF_MI_ISR.
+* To use register names with standard convension, please use CIF_MI_ISR.
+*/
+#define CIFMI_ISR (CIF_MI_ISR)
+
+/** \brief 1600, MI Masked Interrupt Status Registe */
+#define CIF_MI_MIS /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_MIS*)0xF90E3500u)
+
+/** Alias (User Manual Name) for CIF_MI_MIS.
+* To use register names with standard convension, please use CIF_MI_MIS.
+*/
+#define CIFMI_MIS (CIF_MI_MIS)
+
+/** \brief 151C, Memory Interface Base Address For Main Picture Cb Component
+ * Ring Buffer Register */
+#define CIF_MI_MP_CB_BASE_AD_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_MP_CB_BASE_AD_INIT*)0xF90E341Cu)
+
+/** Alias (User Manual Name) for CIF_MI_MP_CB_BASE_AD_INIT.
+* To use register names with standard convension, please use CIF_MI_MP_CB_BASE_AD_INIT.
+*/
+#define CIFMI_MP_CB_BASE_AD_INIT (CIF_MI_MP_CB_BASE_AD_INIT)
+
+/** \brief 1588, Memory Interface Base Address Shadow Register For Main Picture
+ * Cb Component Ring Register */
+#define CIF_MI_MP_CB_BASE_AD_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_MP_CB_BASE_AD_SHD*)0xF90E3488u)
+
+/** Alias (User Manual Name) for CIF_MI_MP_CB_BASE_AD_SHD.
+* To use register names with standard convension, please use CIF_MI_MP_CB_BASE_AD_SHD.
+*/
+#define CIFMI_MP_CB_BASE_AD_SHD (CIF_MI_MP_CB_BASE_AD_SHD)
+
+/** \brief 1524, Memory Interface Offset Counter Init Value For Main Picture Cb
+ * Component Ring Buffer Register */
+#define CIF_MI_MP_CB_OFFS_CNT_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_MP_CB_OFFS_CNT_INIT*)0xF90E3424u)
+
+/** Alias (User Manual Name) for CIF_MI_MP_CB_OFFS_CNT_INIT.
+* To use register names with standard convension, please use CIF_MI_MP_CB_OFFS_CNT_INIT.
+*/
+#define CIFMI_MP_CB_OFFS_CNT_INIT (CIF_MI_MP_CB_OFFS_CNT_INIT)
+
+/** \brief 1590, Memory Interface Current Offset Counter Of Main Picture Cb
+ * Component Ring Buffer Register */
+#define CIF_MI_MP_CB_OFFS_CNT_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_MP_CB_OFFS_CNT_SHD*)0xF90E3490u)
+
+/** Alias (User Manual Name) for CIF_MI_MP_CB_OFFS_CNT_SHD.
+* To use register names with standard convension, please use CIF_MI_MP_CB_OFFS_CNT_SHD.
+*/
+#define CIFMI_MP_CB_OFFS_CNT_SHD (CIF_MI_MP_CB_OFFS_CNT_SHD)
+
+/** \brief 1528, Memory Interface Offset Counter Start Value For Main Picture
+ * Cb Component Ring Buffer Register */
+#define CIF_MI_MP_CB_OFFS_CNT_START /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_MP_CB_OFFS_CNT_START*)0xF90E3428u)
+
+/** Alias (User Manual Name) for CIF_MI_MP_CB_OFFS_CNT_START.
+* To use register names with standard convension, please use CIF_MI_MP_CB_OFFS_CNT_START.
+*/
+#define CIFMI_MP_CB_OFFS_CNT_START (CIF_MI_MP_CB_OFFS_CNT_START)
+
+/** \brief 1520, Memory Interface Size Of Main Picture Cb Component Ring Buffer
+ * Register */
+#define CIF_MI_MP_CB_SIZE_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_MP_CB_SIZE_INIT*)0xF90E3420u)
+
+/** Alias (User Manual Name) for CIF_MI_MP_CB_SIZE_INIT.
+* To use register names with standard convension, please use CIF_MI_MP_CB_SIZE_INIT.
+*/
+#define CIFMI_MP_CB_SIZE_INIT (CIF_MI_MP_CB_SIZE_INIT)
+
+/** \brief 158C, Memory Interface Size Shadow Register Of Main Picture Cb
+ * Component Ring Buffer Register */
+#define CIF_MI_MP_CB_SIZE_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_MP_CB_SIZE_SHD*)0xF90E348Cu)
+
+/** Alias (User Manual Name) for CIF_MI_MP_CB_SIZE_SHD.
+* To use register names with standard convension, please use CIF_MI_MP_CB_SIZE_SHD.
+*/
+#define CIFMI_MP_CB_SIZE_SHD (CIF_MI_MP_CB_SIZE_SHD)
+
+/** \brief 152C, Memory Interface Base Address For Main Picture Cr Component
+ * Ring Buffer Register */
+#define CIF_MI_MP_CR_BASE_AD_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_MP_CR_BASE_AD_INIT*)0xF90E342Cu)
+
+/** Alias (User Manual Name) for CIF_MI_MP_CR_BASE_AD_INIT.
+* To use register names with standard convension, please use CIF_MI_MP_CR_BASE_AD_INIT.
+*/
+#define CIFMI_MP_CR_BASE_AD_INIT (CIF_MI_MP_CR_BASE_AD_INIT)
+
+/** \brief 1594, Memory Interface Base Address Shadow Register For Main Picture
+ * Cr Component Ring Register */
+#define CIF_MI_MP_CR_BASE_AD_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_MP_CR_BASE_AD_SHD*)0xF90E3494u)
+
+/** Alias (User Manual Name) for CIF_MI_MP_CR_BASE_AD_SHD.
+* To use register names with standard convension, please use CIF_MI_MP_CR_BASE_AD_SHD.
+*/
+#define CIFMI_MP_CR_BASE_AD_SHD (CIF_MI_MP_CR_BASE_AD_SHD)
+
+/** \brief 1534, Memory Interface Offset Counter Init value For Main Picture Cr
+ * Component Ring Buffer Register */
+#define CIF_MI_MP_CR_OFFS_CNT_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_MP_CR_OFFS_CNT_INIT*)0xF90E3434u)
+
+/** Alias (User Manual Name) for CIF_MI_MP_CR_OFFS_CNT_INIT.
+* To use register names with standard convension, please use CIF_MI_MP_CR_OFFS_CNT_INIT.
+*/
+#define CIFMI_MP_CR_OFFS_CNT_INIT (CIF_MI_MP_CR_OFFS_CNT_INIT)
+
+/** \brief 159C, Memory Interface Current Offset Counter Of Main Picture Cr
+ * Component Ring Buffer Register */
+#define CIF_MI_MP_CR_OFFS_CNT_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_MP_CR_OFFS_CNT_SHD*)0xF90E349Cu)
+
+/** Alias (User Manual Name) for CIF_MI_MP_CR_OFFS_CNT_SHD.
+* To use register names with standard convension, please use CIF_MI_MP_CR_OFFS_CNT_SHD.
+*/
+#define CIFMI_MP_CR_OFFS_CNT_SHD (CIF_MI_MP_CR_OFFS_CNT_SHD)
+
+/** \brief 1538, Memory Interface Offset Counter Start Value For Main Picture
+ * Cr Component Ring Buffer Register */
+#define CIF_MI_MP_CR_OFFS_CNT_START /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_MP_CR_OFFS_CNT_START*)0xF90E3438u)
+
+/** Alias (User Manual Name) for CIF_MI_MP_CR_OFFS_CNT_START.
+* To use register names with standard convension, please use CIF_MI_MP_CR_OFFS_CNT_START.
+*/
+#define CIFMI_MP_CR_OFFS_CNT_START (CIF_MI_MP_CR_OFFS_CNT_START)
+
+/** \brief 1530, Memory Interface Size Of Main Picture Cr Component Ring Buffer
+ * Register */
+#define CIF_MI_MP_CR_SIZE_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_MP_CR_SIZE_INIT*)0xF90E3430u)
+
+/** Alias (User Manual Name) for CIF_MI_MP_CR_SIZE_INIT.
+* To use register names with standard convension, please use CIF_MI_MP_CR_SIZE_INIT.
+*/
+#define CIFMI_MP_CR_SIZE_INIT (CIF_MI_MP_CR_SIZE_INIT)
+
+/** \brief 1598, Memory Interface Size Shadow Register Of Main Picture Cr
+ * Component Ring Buffer Register */
+#define CIF_MI_MP_CR_SIZE_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_MP_CR_SIZE_SHD*)0xF90E3498u)
+
+/** Alias (User Manual Name) for CIF_MI_MP_CR_SIZE_SHD.
+* To use register names with standard convension, please use CIF_MI_MP_CR_SIZE_SHD.
+*/
+#define CIFMI_MP_CR_SIZE_SHD (CIF_MI_MP_CR_SIZE_SHD)
+
+/** \brief 1508, Memory Interface Base Address For Main Picture Y Component,
+ * JPEG or RAW Data Register */
+#define CIF_MI_MP_Y_BASE_AD_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_MP_Y_BASE_AD_INIT*)0xF90E3408u)
+
+/** Alias (User Manual Name) for CIF_MI_MP_Y_BASE_AD_INIT.
+* To use register names with standard convension, please use CIF_MI_MP_Y_BASE_AD_INIT.
+*/
+#define CIFMI_MP_Y_BASE_AD_INIT (CIF_MI_MP_Y_BASE_AD_INIT)
+
+/** \brief 1578, Memory Interface Base Address Shadow Register For Main Picture
+ * Y Component, JPEG Register */
+#define CIF_MI_MP_Y_BASE_AD_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_MP_Y_BASE_AD_SHD*)0xF90E3478u)
+
+/** Alias (User Manual Name) for CIF_MI_MP_Y_BASE_AD_SHD.
+* To use register names with standard convension, please use CIF_MI_MP_Y_BASE_AD_SHD.
+*/
+#define CIFMI_MP_Y_BASE_AD_SHD (CIF_MI_MP_Y_BASE_AD_SHD)
+
+/** \brief 1518, Memory Interface Fill Level Interrupt Offset Value For Main
+ * Picture Y, JPEG or RAW Data Register */
+#define CIF_MI_MP_Y_IRQ_OFFS_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_MP_Y_IRQ_OFFS_INIT*)0xF90E3418u)
+
+/** Alias (User Manual Name) for CIF_MI_MP_Y_IRQ_OFFS_INIT.
+* To use register names with standard convension, please use CIF_MI_MP_Y_IRQ_OFFS_INIT.
+*/
+#define CIFMI_MP_Y_IRQ_OFFS_INIT (CIF_MI_MP_Y_IRQ_OFFS_INIT)
+
+/** \brief 1584, Memory Interface Shadow Register of Fill Level Interrupt
+ * Offset Value For Main Picture Y Register */
+#define CIF_MI_MP_Y_IRQ_OFFS_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_MP_Y_IRQ_OFFS_SHD*)0xF90E3484u)
+
+/** Alias (User Manual Name) for CIF_MI_MP_Y_IRQ_OFFS_SHD.
+* To use register names with standard convension, please use CIF_MI_MP_Y_IRQ_OFFS_SHD.
+*/
+#define CIFMI_MP_Y_IRQ_OFFS_SHD (CIF_MI_MP_Y_IRQ_OFFS_SHD)
+
+/** \brief 1510, Memory Interface Offset Counter Init Value For Main Picture Y,
+ * JPEG or RAW Data Register */
+#define CIF_MI_MP_Y_OFFS_CNT_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_MP_Y_OFFS_CNT_INIT*)0xF90E3410u)
+
+/** Alias (User Manual Name) for CIF_MI_MP_Y_OFFS_CNT_INIT.
+* To use register names with standard convension, please use CIF_MI_MP_Y_OFFS_CNT_INIT.
+*/
+#define CIFMI_MP_Y_OFFS_CNT_INIT (CIF_MI_MP_Y_OFFS_CNT_INIT)
+
+/** \brief 1580, Memory Interface Current Offset Counter of Main Picture Y
+ * Component JPEG or RAW Register */
+#define CIF_MI_MP_Y_OFFS_CNT_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_MP_Y_OFFS_CNT_SHD*)0xF90E3480u)
+
+/** Alias (User Manual Name) for CIF_MI_MP_Y_OFFS_CNT_SHD.
+* To use register names with standard convension, please use CIF_MI_MP_Y_OFFS_CNT_SHD.
+*/
+#define CIFMI_MP_Y_OFFS_CNT_SHD (CIF_MI_MP_Y_OFFS_CNT_SHD)
+
+/** \brief 1514, Memory Interface Offset Counter Start Value For Main Picture
+ * Y, JPEG or RAW Data Register */
+#define CIF_MI_MP_Y_OFFS_CNT_START /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_MP_Y_OFFS_CNT_START*)0xF90E3414u)
+
+/** Alias (User Manual Name) for CIF_MI_MP_Y_OFFS_CNT_START.
+* To use register names with standard convension, please use CIF_MI_MP_Y_OFFS_CNT_START.
+*/
+#define CIFMI_MP_Y_OFFS_CNT_START (CIF_MI_MP_Y_OFFS_CNT_START)
+
+/** \brief 150C, Memory Interface Size of main picture Y component, JPEG or RAW
+ * data Register */
+#define CIF_MI_MP_Y_SIZE_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_MP_Y_SIZE_INIT*)0xF90E340Cu)
+
+/** Alias (User Manual Name) for CIF_MI_MP_Y_SIZE_INIT.
+* To use register names with standard convension, please use CIF_MI_MP_Y_SIZE_INIT.
+*/
+#define CIFMI_MP_Y_SIZE_INIT (CIF_MI_MP_Y_SIZE_INIT)
+
+/** \brief 157C, Memory Interface Size Shadow Register of Main Picture Y
+ * Component,JPEG or RAW Data Register */
+#define CIF_MI_MP_Y_SIZE_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_MP_Y_SIZE_SHD*)0xF90E347Cu)
+
+/** Alias (User Manual Name) for CIF_MI_MP_Y_SIZE_SHD.
+* To use register names with standard convension, please use CIF_MI_MP_Y_SIZE_SHD.
+*/
+#define CIFMI_MP_Y_SIZE_SHD (CIF_MI_MP_Y_SIZE_SHD)
+
+/** \brief 15FC, MI Raw Interrupt Status Register */
+#define CIF_MI_RIS /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_RIS*)0xF90E34FCu)
+
+/** Alias (User Manual Name) for CIF_MI_RIS.
+* To use register names with standard convension, please use CIF_MI_RIS.
+*/
+#define CIFMI_RIS (CIF_MI_RIS)
+
+/** \brief 160C, MI Status Register */
+#define CIF_MI_STATUS /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_STATUS*)0xF90E350Cu)
+
+/** Alias (User Manual Name) for CIF_MI_STATUS.
+* To use register names with standard convension, please use CIF_MI_STATUS.
+*/
+#define CIFMI_STATUS (CIF_MI_STATUS)
+
+/** \brief 1610, MI Status Clear Register */
+#define CIF_MI_STATUS_CLR /*lint --e(923)*/ (*(volatile Ifx_CIF_MI_STATUS_CLR*)0xF90E3510u)
+
+/** Alias (User Manual Name) for CIF_MI_STATUS_CLR.
+* To use register names with standard convension, please use CIF_MI_STATUS_CLR.
+*/
+#define CIFMI_STATUS_CLR (CIF_MI_STATUS_CLR)
+
+/** \brief 3608, Memory Interface Base Address For Extra Path Data Buffer
+ * Register */
+#define CIF_MIEP_CH_1S0_BASE_AD_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_BASE_AD_INIT*)0xF90E5508u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S0_BASE_AD_INIT.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S0_BASE_AD_INIT.
+*/
+#define CIFMIEP_1_BASE_AD_INIT (CIF_MIEP_CH_1S0_BASE_AD_INIT)
+
+/** \brief 3620, Memory Interface Base Address Shadow Register for Extra Path
+ * Buffer Register */
+#define CIF_MIEP_CH_1S0_BASE_AD_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_BASE_AD_SHD*)0xF90E5520u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S0_BASE_AD_SHD.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S0_BASE_AD_SHD.
+*/
+#define CIFMIEP_1_BASE_AD_SHD (CIF_MIEP_CH_1S0_BASE_AD_SHD)
+
+/** \brief 3600, Memory Interface Extra Path Control Register */
+#define CIF_MIEP_CH_1S0_CTRL /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_CTRL*)0xF90E5500u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S0_CTRL.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S0_CTRL.
+*/
+#define CIFMIEP_1_CTRL (CIF_MIEP_CH_1S0_CTRL)
+
+/** \brief 361C, Memory Interface Extra Path Control Internal Shadow Register */
+#define CIF_MIEP_CH_1S0_CTRL_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_CTRL_SHD*)0xF90E551Cu)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S0_CTRL_SHD.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S0_CTRL_SHD.
+*/
+#define CIFMIEP_1_CTRL_SHD (CIF_MIEP_CH_1S0_CTRL_SHD)
+
+/** \brief 3604, Memory Interface Extra Path Control Register For Address Init
+ * And Skip Function Register */
+#define CIF_MIEP_CH_1S0_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_INIT*)0xF90E5504u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S0_INIT.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S0_INIT.
+*/
+#define CIFMIEP_1_INIT (CIF_MIEP_CH_1S0_INIT)
+
+/** \brief 3618, Memory Interface Fill Level Interrupt Offset Value For Extra
+ * Path Register */
+#define CIF_MIEP_CH_1S0_IRQ_OFFS_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_IRQ_OFFS_INIT*)0xF90E5518u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S0_IRQ_OFFS_INIT.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S0_IRQ_OFFS_INIT.
+*/
+#define CIFMIEP_1_IRQ_OFFS_INIT (CIF_MIEP_CH_1S0_IRQ_OFFS_INIT)
+
+/** \brief 362C, Memory Interface Shadow Register of Fill Level Interrupt
+ * Offset Value For Extra Path Register */
+#define CIF_MIEP_CH_1S0_IRQ_OFFS_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_IRQ_OFFS_SHD*)0xF90E552Cu)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S0_IRQ_OFFS_SHD.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S0_IRQ_OFFS_SHD.
+*/
+#define CIFMIEP_1_IRQ_OFFS_SHD (CIF_MIEP_CH_1S0_IRQ_OFFS_SHD)
+
+/** \brief 3610, Memory Interface Offset Counter Init Value For Extra Path
+ * Buffer Register */
+#define CIF_MIEP_CH_1S0_OFFS_CNT_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_OFFS_CNT_INIT*)0xF90E5510u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S0_OFFS_CNT_INIT.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S0_OFFS_CNT_INIT.
+*/
+#define CIFMIEP_1_OFFS_CNT_INIT (CIF_MIEP_CH_1S0_OFFS_CNT_INIT)
+
+/** \brief 3628, Memory Interface Current Offset Counter of Extra Path Buffer
+ * Register */
+#define CIF_MIEP_CH_1S0_OFFS_CNT_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_OFFS_CNT_SHD*)0xF90E5528u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S0_OFFS_CNT_SHD.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S0_OFFS_CNT_SHD.
+*/
+#define CIFMIEP_1_OFFS_CNT_SHD (CIF_MIEP_CH_1S0_OFFS_CNT_SHD)
+
+/** \brief 3614, Memory Interface Offset Counter Start Value For Extra Path
+ * Register */
+#define CIF_MIEP_CH_1S0_OFFS_CNT_START /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_OFFS_CNT_START*)0xF90E5514u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S0_OFFS_CNT_START.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S0_OFFS_CNT_START.
+*/
+#define CIFMIEP_1_OFFS_CNT_START (CIF_MIEP_CH_1S0_OFFS_CNT_START)
+
+/** \brief 360C, Memory Interface Size of Extra Path Data Buffer Register */
+#define CIF_MIEP_CH_1S0_SIZE_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_SIZE_INIT*)0xF90E550Cu)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S0_SIZE_INIT.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S0_SIZE_INIT.
+*/
+#define CIFMIEP_1_SIZE_INIT (CIF_MIEP_CH_1S0_SIZE_INIT)
+
+/** \brief 3624, Memory Interface Size Shadow Register of Extra Path Buffer
+ * Register */
+#define CIF_MIEP_CH_1S0_SIZE_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_SIZE_SHD*)0xF90E5524u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S0_SIZE_SHD.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S0_SIZE_SHD.
+*/
+#define CIFMIEP_1_SIZE_SHD (CIF_MIEP_CH_1S0_SIZE_SHD)
+
+/** \brief 3708, Memory Interface Base Address For Extra Path Data Buffer
+ * Register */
+#define CIF_MIEP_CH_1S1_BASE_AD_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_BASE_AD_INIT*)0xF90E5608u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S1_BASE_AD_INIT.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S1_BASE_AD_INIT.
+*/
+#define CIFMIEP_2_BASE_AD_INIT (CIF_MIEP_CH_1S1_BASE_AD_INIT)
+
+/** \brief 3720, Memory Interface Base Address Shadow Register for Extra Path
+ * Buffer Register */
+#define CIF_MIEP_CH_1S1_BASE_AD_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_BASE_AD_SHD*)0xF90E5620u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S1_BASE_AD_SHD.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S1_BASE_AD_SHD.
+*/
+#define CIFMIEP_2_BASE_AD_SHD (CIF_MIEP_CH_1S1_BASE_AD_SHD)
+
+/** \brief 3700, Memory Interface Extra Path Control Register */
+#define CIF_MIEP_CH_1S1_CTRL /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_CTRL*)0xF90E5600u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S1_CTRL.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S1_CTRL.
+*/
+#define CIFMIEP_2_CTRL (CIF_MIEP_CH_1S1_CTRL)
+
+/** \brief 371C, Memory Interface Extra Path Control Internal Shadow Register */
+#define CIF_MIEP_CH_1S1_CTRL_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_CTRL_SHD*)0xF90E561Cu)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S1_CTRL_SHD.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S1_CTRL_SHD.
+*/
+#define CIFMIEP_2_CTRL_SHD (CIF_MIEP_CH_1S1_CTRL_SHD)
+
+/** \brief 3704, Memory Interface Extra Path Control Register For Address Init
+ * And Skip Function Register */
+#define CIF_MIEP_CH_1S1_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_INIT*)0xF90E5604u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S1_INIT.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S1_INIT.
+*/
+#define CIFMIEP_2_INIT (CIF_MIEP_CH_1S1_INIT)
+
+/** \brief 3718, Memory Interface Fill Level Interrupt Offset Value For Extra
+ * Path Register */
+#define CIF_MIEP_CH_1S1_IRQ_OFFS_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_IRQ_OFFS_INIT*)0xF90E5618u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S1_IRQ_OFFS_INIT.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S1_IRQ_OFFS_INIT.
+*/
+#define CIFMIEP_2_IRQ_OFFS_INIT (CIF_MIEP_CH_1S1_IRQ_OFFS_INIT)
+
+/** \brief 372C, Memory Interface Shadow Register of Fill Level Interrupt
+ * Offset Value For Extra Path Register */
+#define CIF_MIEP_CH_1S1_IRQ_OFFS_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_IRQ_OFFS_SHD*)0xF90E562Cu)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S1_IRQ_OFFS_SHD.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S1_IRQ_OFFS_SHD.
+*/
+#define CIFMIEP_2_IRQ_OFFS_SHD (CIF_MIEP_CH_1S1_IRQ_OFFS_SHD)
+
+/** \brief 3710, Memory Interface Offset Counter Init Value For Extra Path
+ * Buffer Register */
+#define CIF_MIEP_CH_1S1_OFFS_CNT_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_OFFS_CNT_INIT*)0xF90E5610u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S1_OFFS_CNT_INIT.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S1_OFFS_CNT_INIT.
+*/
+#define CIFMIEP_2_OFFS_CNT_INIT (CIF_MIEP_CH_1S1_OFFS_CNT_INIT)
+
+/** \brief 3728, Memory Interface Current Offset Counter of Extra Path Buffer
+ * Register */
+#define CIF_MIEP_CH_1S1_OFFS_CNT_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_OFFS_CNT_SHD*)0xF90E5628u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S1_OFFS_CNT_SHD.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S1_OFFS_CNT_SHD.
+*/
+#define CIFMIEP_2_OFFS_CNT_SHD (CIF_MIEP_CH_1S1_OFFS_CNT_SHD)
+
+/** \brief 3714, Memory Interface Offset Counter Start Value For Extra Path
+ * Register */
+#define CIF_MIEP_CH_1S1_OFFS_CNT_START /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_OFFS_CNT_START*)0xF90E5614u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S1_OFFS_CNT_START.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S1_OFFS_CNT_START.
+*/
+#define CIFMIEP_2_OFFS_CNT_START (CIF_MIEP_CH_1S1_OFFS_CNT_START)
+
+/** \brief 370C, Memory Interface Size of Extra Path Data Buffer Register */
+#define CIF_MIEP_CH_1S1_SIZE_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_SIZE_INIT*)0xF90E560Cu)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S1_SIZE_INIT.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S1_SIZE_INIT.
+*/
+#define CIFMIEP_2_SIZE_INIT (CIF_MIEP_CH_1S1_SIZE_INIT)
+
+/** \brief 3724, Memory Interface Size Shadow Register of Extra Path Buffer
+ * Register */
+#define CIF_MIEP_CH_1S1_SIZE_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_SIZE_SHD*)0xF90E5624u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S1_SIZE_SHD.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S1_SIZE_SHD.
+*/
+#define CIFMIEP_2_SIZE_SHD (CIF_MIEP_CH_1S1_SIZE_SHD)
+
+/** \brief 3808, Memory Interface Base Address For Extra Path Data Buffer
+ * Register */
+#define CIF_MIEP_CH_1S2_BASE_AD_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_BASE_AD_INIT*)0xF90E5708u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S2_BASE_AD_INIT.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S2_BASE_AD_INIT.
+*/
+#define CIFMIEP_3_BASE_AD_INIT (CIF_MIEP_CH_1S2_BASE_AD_INIT)
+
+/** \brief 3820, Memory Interface Base Address Shadow Register for Extra Path
+ * Buffer Register */
+#define CIF_MIEP_CH_1S2_BASE_AD_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_BASE_AD_SHD*)0xF90E5720u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S2_BASE_AD_SHD.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S2_BASE_AD_SHD.
+*/
+#define CIFMIEP_3_BASE_AD_SHD (CIF_MIEP_CH_1S2_BASE_AD_SHD)
+
+/** \brief 3800, Memory Interface Extra Path Control Register */
+#define CIF_MIEP_CH_1S2_CTRL /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_CTRL*)0xF90E5700u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S2_CTRL.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S2_CTRL.
+*/
+#define CIFMIEP_3_CTRL (CIF_MIEP_CH_1S2_CTRL)
+
+/** \brief 381C, Memory Interface Extra Path Control Internal Shadow Register */
+#define CIF_MIEP_CH_1S2_CTRL_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_CTRL_SHD*)0xF90E571Cu)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S2_CTRL_SHD.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S2_CTRL_SHD.
+*/
+#define CIFMIEP_3_CTRL_SHD (CIF_MIEP_CH_1S2_CTRL_SHD)
+
+/** \brief 3804, Memory Interface Extra Path Control Register For Address Init
+ * And Skip Function Register */
+#define CIF_MIEP_CH_1S2_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_INIT*)0xF90E5704u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S2_INIT.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S2_INIT.
+*/
+#define CIFMIEP_3_INIT (CIF_MIEP_CH_1S2_INIT)
+
+/** \brief 3818, Memory Interface Fill Level Interrupt Offset Value For Extra
+ * Path Register */
+#define CIF_MIEP_CH_1S2_IRQ_OFFS_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_IRQ_OFFS_INIT*)0xF90E5718u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S2_IRQ_OFFS_INIT.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S2_IRQ_OFFS_INIT.
+*/
+#define CIFMIEP_3_IRQ_OFFS_INIT (CIF_MIEP_CH_1S2_IRQ_OFFS_INIT)
+
+/** \brief 382C, Memory Interface Shadow Register of Fill Level Interrupt
+ * Offset Value For Extra Path Register */
+#define CIF_MIEP_CH_1S2_IRQ_OFFS_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_IRQ_OFFS_SHD*)0xF90E572Cu)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S2_IRQ_OFFS_SHD.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S2_IRQ_OFFS_SHD.
+*/
+#define CIFMIEP_3_IRQ_OFFS_SHD (CIF_MIEP_CH_1S2_IRQ_OFFS_SHD)
+
+/** \brief 3810, Memory Interface Offset Counter Init Value For Extra Path
+ * Buffer Register */
+#define CIF_MIEP_CH_1S2_OFFS_CNT_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_OFFS_CNT_INIT*)0xF90E5710u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S2_OFFS_CNT_INIT.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S2_OFFS_CNT_INIT.
+*/
+#define CIFMIEP_3_OFFS_CNT_INIT (CIF_MIEP_CH_1S2_OFFS_CNT_INIT)
+
+/** \brief 3828, Memory Interface Current Offset Counter of Extra Path Buffer
+ * Register */
+#define CIF_MIEP_CH_1S2_OFFS_CNT_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_OFFS_CNT_SHD*)0xF90E5728u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S2_OFFS_CNT_SHD.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S2_OFFS_CNT_SHD.
+*/
+#define CIFMIEP_3_OFFS_CNT_SHD (CIF_MIEP_CH_1S2_OFFS_CNT_SHD)
+
+/** \brief 3814, Memory Interface Offset Counter Start Value For Extra Path
+ * Register */
+#define CIF_MIEP_CH_1S2_OFFS_CNT_START /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_OFFS_CNT_START*)0xF90E5714u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S2_OFFS_CNT_START.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S2_OFFS_CNT_START.
+*/
+#define CIFMIEP_3_OFFS_CNT_START (CIF_MIEP_CH_1S2_OFFS_CNT_START)
+
+/** \brief 380C, Memory Interface Size of Extra Path Data Buffer Register */
+#define CIF_MIEP_CH_1S2_SIZE_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_SIZE_INIT*)0xF90E570Cu)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S2_SIZE_INIT.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S2_SIZE_INIT.
+*/
+#define CIFMIEP_3_SIZE_INIT (CIF_MIEP_CH_1S2_SIZE_INIT)
+
+/** \brief 3824, Memory Interface Size Shadow Register of Extra Path Buffer
+ * Register */
+#define CIF_MIEP_CH_1S2_SIZE_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_SIZE_SHD*)0xF90E5724u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S2_SIZE_SHD.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S2_SIZE_SHD.
+*/
+#define CIFMIEP_3_SIZE_SHD (CIF_MIEP_CH_1S2_SIZE_SHD)
+
+/** \brief 3908, Memory Interface Base Address For Extra Path Data Buffer
+ * Register */
+#define CIF_MIEP_CH_1S3_BASE_AD_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_BASE_AD_INIT*)0xF90E5808u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S3_BASE_AD_INIT.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S3_BASE_AD_INIT.
+*/
+#define CIFMIEP_4_BASE_AD_INIT (CIF_MIEP_CH_1S3_BASE_AD_INIT)
+
+/** \brief 3920, Memory Interface Base Address Shadow Register for Extra Path
+ * Buffer Register */
+#define CIF_MIEP_CH_1S3_BASE_AD_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_BASE_AD_SHD*)0xF90E5820u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S3_BASE_AD_SHD.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S3_BASE_AD_SHD.
+*/
+#define CIFMIEP_4_BASE_AD_SHD (CIF_MIEP_CH_1S3_BASE_AD_SHD)
+
+/** \brief 3900, Memory Interface Extra Path Control Register */
+#define CIF_MIEP_CH_1S3_CTRL /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_CTRL*)0xF90E5800u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S3_CTRL.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S3_CTRL.
+*/
+#define CIFMIEP_4_CTRL (CIF_MIEP_CH_1S3_CTRL)
+
+/** \brief 391C, Memory Interface Extra Path Control Internal Shadow Register */
+#define CIF_MIEP_CH_1S3_CTRL_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_CTRL_SHD*)0xF90E581Cu)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S3_CTRL_SHD.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S3_CTRL_SHD.
+*/
+#define CIFMIEP_4_CTRL_SHD (CIF_MIEP_CH_1S3_CTRL_SHD)
+
+/** \brief 3904, Memory Interface Extra Path Control Register For Address Init
+ * And Skip Function Register */
+#define CIF_MIEP_CH_1S3_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_INIT*)0xF90E5804u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S3_INIT.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S3_INIT.
+*/
+#define CIFMIEP_4_INIT (CIF_MIEP_CH_1S3_INIT)
+
+/** \brief 3918, Memory Interface Fill Level Interrupt Offset Value For Extra
+ * Path Register */
+#define CIF_MIEP_CH_1S3_IRQ_OFFS_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_IRQ_OFFS_INIT*)0xF90E5818u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S3_IRQ_OFFS_INIT.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S3_IRQ_OFFS_INIT.
+*/
+#define CIFMIEP_4_IRQ_OFFS_INIT (CIF_MIEP_CH_1S3_IRQ_OFFS_INIT)
+
+/** \brief 392C, Memory Interface Shadow Register of Fill Level Interrupt
+ * Offset Value For Extra Path Register */
+#define CIF_MIEP_CH_1S3_IRQ_OFFS_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_IRQ_OFFS_SHD*)0xF90E582Cu)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S3_IRQ_OFFS_SHD.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S3_IRQ_OFFS_SHD.
+*/
+#define CIFMIEP_4_IRQ_OFFS_SHD (CIF_MIEP_CH_1S3_IRQ_OFFS_SHD)
+
+/** \brief 3910, Memory Interface Offset Counter Init Value For Extra Path
+ * Buffer Register */
+#define CIF_MIEP_CH_1S3_OFFS_CNT_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_OFFS_CNT_INIT*)0xF90E5810u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S3_OFFS_CNT_INIT.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S3_OFFS_CNT_INIT.
+*/
+#define CIFMIEP_4_OFFS_CNT_INIT (CIF_MIEP_CH_1S3_OFFS_CNT_INIT)
+
+/** \brief 3928, Memory Interface Current Offset Counter of Extra Path Buffer
+ * Register */
+#define CIF_MIEP_CH_1S3_OFFS_CNT_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_OFFS_CNT_SHD*)0xF90E5828u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S3_OFFS_CNT_SHD.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S3_OFFS_CNT_SHD.
+*/
+#define CIFMIEP_4_OFFS_CNT_SHD (CIF_MIEP_CH_1S3_OFFS_CNT_SHD)
+
+/** \brief 3914, Memory Interface Offset Counter Start Value For Extra Path
+ * Register */
+#define CIF_MIEP_CH_1S3_OFFS_CNT_START /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_OFFS_CNT_START*)0xF90E5814u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S3_OFFS_CNT_START.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S3_OFFS_CNT_START.
+*/
+#define CIFMIEP_4_OFFS_CNT_START (CIF_MIEP_CH_1S3_OFFS_CNT_START)
+
+/** \brief 390C, Memory Interface Size of Extra Path Data Buffer Register */
+#define CIF_MIEP_CH_1S3_SIZE_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_SIZE_INIT*)0xF90E580Cu)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S3_SIZE_INIT.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S3_SIZE_INIT.
+*/
+#define CIFMIEP_4_SIZE_INIT (CIF_MIEP_CH_1S3_SIZE_INIT)
+
+/** \brief 3924, Memory Interface Size Shadow Register of Extra Path Buffer
+ * Register */
+#define CIF_MIEP_CH_1S3_SIZE_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_SIZE_SHD*)0xF90E5824u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S3_SIZE_SHD.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S3_SIZE_SHD.
+*/
+#define CIFMIEP_4_SIZE_SHD (CIF_MIEP_CH_1S3_SIZE_SHD)
+
+/** \brief 3A08, Memory Interface Base Address For Extra Path Data Buffer
+ * Register */
+#define CIF_MIEP_CH_1S4_BASE_AD_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_BASE_AD_INIT*)0xF90E5908u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S4_BASE_AD_INIT.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S4_BASE_AD_INIT.
+*/
+#define CIFMIEP_5_BASE_AD_INIT (CIF_MIEP_CH_1S4_BASE_AD_INIT)
+
+/** \brief 3A20, Memory Interface Base Address Shadow Register for Extra Path
+ * Buffer Register */
+#define CIF_MIEP_CH_1S4_BASE_AD_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_BASE_AD_SHD*)0xF90E5920u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S4_BASE_AD_SHD.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S4_BASE_AD_SHD.
+*/
+#define CIFMIEP_5_BASE_AD_SHD (CIF_MIEP_CH_1S4_BASE_AD_SHD)
+
+/** \brief 3A00, Memory Interface Extra Path Control Register */
+#define CIF_MIEP_CH_1S4_CTRL /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_CTRL*)0xF90E5900u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S4_CTRL.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S4_CTRL.
+*/
+#define CIFMIEP_5_CTRL (CIF_MIEP_CH_1S4_CTRL)
+
+/** \brief 3A1C, Memory Interface Extra Path Control Internal Shadow Register */
+#define CIF_MIEP_CH_1S4_CTRL_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_CTRL_SHD*)0xF90E591Cu)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S4_CTRL_SHD.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S4_CTRL_SHD.
+*/
+#define CIFMIEP_5_CTRL_SHD (CIF_MIEP_CH_1S4_CTRL_SHD)
+
+/** \brief 3A04, Memory Interface Extra Path Control Register For Address Init
+ * And Skip Function Register */
+#define CIF_MIEP_CH_1S4_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_INIT*)0xF90E5904u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S4_INIT.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S4_INIT.
+*/
+#define CIFMIEP_5_INIT (CIF_MIEP_CH_1S4_INIT)
+
+/** \brief 3A18, Memory Interface Fill Level Interrupt Offset Value For Extra
+ * Path Register */
+#define CIF_MIEP_CH_1S4_IRQ_OFFS_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_IRQ_OFFS_INIT*)0xF90E5918u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S4_IRQ_OFFS_INIT.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S4_IRQ_OFFS_INIT.
+*/
+#define CIFMIEP_5_IRQ_OFFS_INIT (CIF_MIEP_CH_1S4_IRQ_OFFS_INIT)
+
+/** \brief 3A2C, Memory Interface Shadow Register of Fill Level Interrupt
+ * Offset Value For Extra Path Register */
+#define CIF_MIEP_CH_1S4_IRQ_OFFS_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_IRQ_OFFS_SHD*)0xF90E592Cu)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S4_IRQ_OFFS_SHD.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S4_IRQ_OFFS_SHD.
+*/
+#define CIFMIEP_5_IRQ_OFFS_SHD (CIF_MIEP_CH_1S4_IRQ_OFFS_SHD)
+
+/** \brief 3A10, Memory Interface Offset Counter Init Value For Extra Path
+ * Buffer Register */
+#define CIF_MIEP_CH_1S4_OFFS_CNT_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_OFFS_CNT_INIT*)0xF90E5910u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S4_OFFS_CNT_INIT.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S4_OFFS_CNT_INIT.
+*/
+#define CIFMIEP_5_OFFS_CNT_INIT (CIF_MIEP_CH_1S4_OFFS_CNT_INIT)
+
+/** \brief 3A28, Memory Interface Current Offset Counter of Extra Path Buffer
+ * Register */
+#define CIF_MIEP_CH_1S4_OFFS_CNT_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_OFFS_CNT_SHD*)0xF90E5928u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S4_OFFS_CNT_SHD.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S4_OFFS_CNT_SHD.
+*/
+#define CIFMIEP_5_OFFS_CNT_SHD (CIF_MIEP_CH_1S4_OFFS_CNT_SHD)
+
+/** \brief 3A14, Memory Interface Offset Counter Start Value For Extra Path
+ * Register */
+#define CIF_MIEP_CH_1S4_OFFS_CNT_START /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_OFFS_CNT_START*)0xF90E5914u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S4_OFFS_CNT_START.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S4_OFFS_CNT_START.
+*/
+#define CIFMIEP_5_OFFS_CNT_START (CIF_MIEP_CH_1S4_OFFS_CNT_START)
+
+/** \brief 3A0C, Memory Interface Size of Extra Path Data Buffer Register */
+#define CIF_MIEP_CH_1S4_SIZE_INIT /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_SIZE_INIT*)0xF90E590Cu)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S4_SIZE_INIT.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S4_SIZE_INIT.
+*/
+#define CIFMIEP_5_SIZE_INIT (CIF_MIEP_CH_1S4_SIZE_INIT)
+
+/** \brief 3A24, Memory Interface Size Shadow Register of Extra Path Buffer
+ * Register */
+#define CIF_MIEP_CH_1S4_SIZE_SHD /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_CH_SIZE_SHD*)0xF90E5924u)
+
+/** Alias (User Manual Name) for CIF_MIEP_CH_1S4_SIZE_SHD.
+* To use register names with standard convension, please use CIF_MIEP_CH_1S4_SIZE_SHD.
+*/
+#define CIFMIEP_5_SIZE_SHD (CIF_MIEP_CH_1S4_SIZE_SHD)
+
+/** \brief 3514, MI Extra Path Interrupt Clear Register */
+#define CIF_MIEP_ICR /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_ICR*)0xF90E5414u)
+
+/** Alias (User Manual Name) for CIF_MIEP_ICR.
+* To use register names with standard convension, please use CIF_MIEP_ICR.
+*/
+#define CIFMIEP_ICR (CIF_MIEP_ICR)
+
+/** \brief 3508, MI Extra Path Interrupt Mask ‘1’: interrupt active, ‘0’:
+ * interrupt masked */
+#define CIF_MIEP_IMSC /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_IMSC*)0xF90E5408u)
+
+/** Alias (User Manual Name) for CIF_MIEP_IMSC.
+* To use register names with standard convension, please use CIF_MIEP_IMSC.
+*/
+#define CIFMIEP_IMSC (CIF_MIEP_IMSC)
+
+/** \brief 3518, MI Extra Path Interrupt Set Register */
+#define CIF_MIEP_ISR /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_ISR*)0xF90E5418u)
+
+/** Alias (User Manual Name) for CIF_MIEP_ISR.
+* To use register names with standard convension, please use CIF_MIEP_ISR.
+*/
+#define CIFMIEP_ISR (CIF_MIEP_ISR)
+
+/** \brief 3510, MI Extra Path Masked Interrupt Status Register */
+#define CIF_MIEP_MIS /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_MIS*)0xF90E5410u)
+
+/** Alias (User Manual Name) for CIF_MIEP_MIS.
+* To use register names with standard convension, please use CIF_MIEP_MIS.
+*/
+#define CIFMIEP_MIS (CIF_MIEP_MIS)
+
+/** \brief 350C, MI Extra Path Raw Interrupt Status Register */
+#define CIF_MIEP_RIS /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_RIS*)0xF90E540Cu)
+
+/** Alias (User Manual Name) for CIF_MIEP_RIS.
+* To use register names with standard convension, please use CIF_MIEP_RIS.
+*/
+#define CIFMIEP_RIS (CIF_MIEP_RIS)
+
+/** \brief 3500, Extra Path Error Register */
+#define CIF_MIEP_STA_ERR /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_STA_ERR*)0xF90E5400u)
+
+/** Alias (User Manual Name) for CIF_MIEP_STA_ERR.
+* To use register names with standard convension, please use CIF_MIEP_STA_ERR.
+*/
+#define CIFMIEP_STA_ERR (CIF_MIEP_STA_ERR)
+
+/** \brief 3504, Extra Path Error Clear Register */
+#define CIF_MIEP_STA_ERR_CLR /*lint --e(923)*/ (*(volatile Ifx_CIF_MIEP_STA_ERR_CLR*)0xF90E5404u)
+
+/** Alias (User Manual Name) for CIF_MIEP_STA_ERR_CLR.
+* To use register names with standard convension, please use CIF_MIEP_STA_ERR_CLR.
+*/
+#define CIFMIEP_STA_ERR_CLR (CIF_MIEP_STA_ERR_CLR)
+
+/** \brief 2500, Watchdog Control Register */
+#define CIF_WD_CTRL /*lint --e(923)*/ (*(volatile Ifx_CIF_WD_CTRL*)0xF90E4400u)
+
+/** Alias (User Manual Name) for CIF_WD_CTRL.
+* To use register names with standard convension, please use CIF_WD_CTRL.
+*/
+#define CIFWD_CTRL (CIF_WD_CTRL)
+
+/** \brief 2508, Watchdog Horizontal Timeout Register */
+#define CIF_WD_H_TIMEOUT /*lint --e(923)*/ (*(volatile Ifx_CIF_WD_H_TIMEOUT*)0xF90E4408u)
+
+/** Alias (User Manual Name) for CIF_WD_H_TIMEOUT.
+* To use register names with standard convension, please use CIF_WD_H_TIMEOUT.
+*/
+#define CIFWD_H_TIMEOUT (CIF_WD_H_TIMEOUT)
+
+/** \brief 2518, Watchdog Interrupt Clear Register */
+#define CIF_WD_ICR /*lint --e(923)*/ (*(volatile Ifx_CIF_WD_ICR*)0xF90E4418u)
+
+/** Alias (User Manual Name) for CIF_WD_ICR.
+* To use register names with standard convension, please use CIF_WD_ICR.
+*/
+#define CIFWD_ICR (CIF_WD_ICR)
+
+/** \brief 250C, Watchdog Interrupt Mask Register */
+#define CIF_WD_IMSC /*lint --e(923)*/ (*(volatile Ifx_CIF_WD_IMSC*)0xF90E440Cu)
+
+/** Alias (User Manual Name) for CIF_WD_IMSC.
+* To use register names with standard convension, please use CIF_WD_IMSC.
+*/
+#define CIFWD_IMSC (CIF_WD_IMSC)
+
+/** \brief 251C, Watchdog Interrupt Set Register */
+#define CIF_WD_ISR /*lint --e(923)*/ (*(volatile Ifx_CIF_WD_ISR*)0xF90E441Cu)
+
+/** Alias (User Manual Name) for CIF_WD_ISR.
+* To use register names with standard convension, please use CIF_WD_ISR.
+*/
+#define CIFWD_ISR (CIF_WD_ISR)
+
+/** \brief 2514, Watchdog Masked Interrupt Status Register */
+#define CIF_WD_MIS /*lint --e(923)*/ (*(volatile Ifx_CIF_WD_MIS*)0xF90E4414u)
+
+/** Alias (User Manual Name) for CIF_WD_MIS.
+* To use register names with standard convension, please use CIF_WD_MIS.
+*/
+#define CIFWD_MIS (CIF_WD_MIS)
+
+/** \brief 2510, Watchdog Raw Interrupt Status Register */
+#define CIF_WD_RIS /*lint --e(923)*/ (*(volatile Ifx_CIF_WD_RIS*)0xF90E4410u)
+
+/** Alias (User Manual Name) for CIF_WD_RIS.
+* To use register names with standard convension, please use CIF_WD_RIS.
+*/
+#define CIFWD_RIS (CIF_WD_RIS)
+
+/** \brief 2504, Watchdog Vertical Timeout Register */
+#define CIF_WD_V_TIMEOUT /*lint --e(923)*/ (*(volatile Ifx_CIF_WD_V_TIMEOUT*)0xF90E4404u)
+
+/** Alias (User Manual Name) for CIF_WD_V_TIMEOUT.
+* To use register names with standard convension, please use CIF_WD_V_TIMEOUT.
+*/
+#define CIFWD_V_TIMEOUT (CIF_WD_V_TIMEOUT)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXCIF_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCif_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCif_regdef.h
new file mode 100644
index 0000000..a29092b
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCif_regdef.h
@@ -0,0 +1,3367 @@
+/**
+ * \file IfxCif_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Cif Cif
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Cif_Bitfields Bitfields
+ * \ingroup IfxLld_Cif
+ *
+ * \defgroup IfxLld_Cif_union Union
+ * \ingroup IfxLld_Cif
+ *
+ * \defgroup IfxLld_Cif_struct Struct
+ * \ingroup IfxLld_Cif
+ *
+ */
+#ifndef IFXCIF_REGDEF_H
+#define IFXCIF_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Cif_Bitfields
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef struct _Ifx_CIF_BBB_ACCEN0_Bits
+{
+ Ifx_Strict_32Bit EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ Ifx_Strict_32Bit EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ Ifx_Strict_32Bit EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ Ifx_Strict_32Bit EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ Ifx_Strict_32Bit EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ Ifx_Strict_32Bit EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ Ifx_Strict_32Bit EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ Ifx_Strict_32Bit EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ Ifx_Strict_32Bit EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ Ifx_Strict_32Bit EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ Ifx_Strict_32Bit EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ Ifx_Strict_32Bit EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ Ifx_Strict_32Bit EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ Ifx_Strict_32Bit EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ Ifx_Strict_32Bit EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ Ifx_Strict_32Bit EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ Ifx_Strict_32Bit EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ Ifx_Strict_32Bit EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ Ifx_Strict_32Bit EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ Ifx_Strict_32Bit EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ Ifx_Strict_32Bit EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ Ifx_Strict_32Bit EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ Ifx_Strict_32Bit EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ Ifx_Strict_32Bit EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ Ifx_Strict_32Bit EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ Ifx_Strict_32Bit EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ Ifx_Strict_32Bit EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ Ifx_Strict_32Bit EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ Ifx_Strict_32Bit EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ Ifx_Strict_32Bit EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ Ifx_Strict_32Bit EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ Ifx_Strict_32Bit EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_CIF_BBB_ACCEN0_Bits;
+
+/** \brief Access Enable Register 1 */
+typedef struct _Ifx_CIF_BBB_ACCEN1_Bits
+{
+ Ifx_Strict_32Bit reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_CIF_BBB_ACCEN1_Bits;
+
+/** \brief Clock Control Register */
+typedef struct _Ifx_CIF_BBB_CLC_Bits
+{
+ Ifx_Strict_32Bit DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
+ Ifx_Strict_32Bit DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_CIF_BBB_CLC_Bits;
+
+/** \brief General Purpose Control Register */
+typedef struct _Ifx_CIF_BBB_GPCTL_Bits
+{
+ Ifx_Strict_32Bit PISEL:1; /**< \brief [0:0] Port Input Select Bit (r) */
+ Ifx_Strict_32Bit reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_CIF_BBB_GPCTL_Bits;
+
+/** \brief Kernel Reset Register 0 */
+typedef struct _Ifx_CIF_BBB_KRST0_Bits
+{
+ Ifx_Strict_32Bit RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ Ifx_Strict_32Bit RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rh) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_CIF_BBB_KRST0_Bits;
+
+/** \brief Kernel Reset Register 1 */
+typedef struct _Ifx_CIF_BBB_KRST1_Bits
+{
+ Ifx_Strict_32Bit RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ Ifx_Strict_32Bit reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_CIF_BBB_KRST1_Bits;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef struct _Ifx_CIF_BBB_KRSTCLR_Bits
+{
+ Ifx_Strict_32Bit CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
+ Ifx_Strict_32Bit reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_CIF_BBB_KRSTCLR_Bits;
+
+/** \brief Module Identification Register */
+typedef struct _Ifx_CIF_BBB_MODID_Bits
+{
+ Ifx_Strict_32Bit MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ Ifx_Strict_32Bit MODTYPE:8; /**< \brief [15:8] Module Type (r) */
+ Ifx_Strict_32Bit MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_CIF_BBB_MODID_Bits;
+
+/** \brief Clock Control Register */
+typedef struct _Ifx_CIF_CCL_Bits
+{
+ Ifx_Strict_32Bit reserved_0:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit CIF_CCLDISS:1; /**< \brief [1:1] Status of cif_ccl[2] bit (r) */
+ Ifx_Strict_32Bit CIF_CCLFDIS:1; /**< \brief [2:2] Clock Control Logic disable (rw) */
+ Ifx_Strict_32Bit reserved_3:29; /**< \brief \internal Reserved */
+} Ifx_CIF_CCL_Bits;
+
+/** \brief Debug Path Control Register */
+typedef struct _Ifx_CIF_DP_CTRL_Bits
+{
+ Ifx_Strict_32Bit DP_EN:1; /**< \brief [0:0] Debug Path Enable (rw) */
+ Ifx_Strict_32Bit DP_SEL:3; /**< \brief [3:1] Select Source Path which will be transfered over the Debug Interface (rw) */
+ Ifx_Strict_32Bit reserved_4:4; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit RST_FNC:1; /**< \brief [8:8] Reset Frame Number Counter (w) */
+ Ifx_Strict_32Bit RST_LNC:1; /**< \brief [9:9] Reset Line Number Counter (w) */
+ Ifx_Strict_32Bit RST_TSC:1; /**< \brief [10:10] Reset Timestamp Counter (w) */
+ Ifx_Strict_32Bit RST_PD:1; /**< \brief [11:11] Reset Predivider Counter (w) */
+ Ifx_Strict_32Bit reserved_12:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit FNC_EN:1; /**< \brief [13:13] Enable/disable Frame Number Counter (rw) */
+ Ifx_Strict_32Bit LNC_EN:1; /**< \brief [14:14] Enable/disable Line Number Counter (rw) */
+ Ifx_Strict_32Bit TSC_EN:1; /**< \brief [15:15] Enable/disable Timestamp Counter (rw) */
+ Ifx_Strict_32Bit UDS1:1; /**< \brief [16:16] Enable/disable sending of User Defined Symbol 1 (rw) */
+ Ifx_Strict_32Bit UDS2:1; /**< \brief [17:17] Enable/disable sending of User Defined Symbol 2 (rw) */
+ Ifx_Strict_32Bit UDS3:1; /**< \brief [18:18] Enable/disable sending of User Defined Symbol 3 (rw) */
+ Ifx_Strict_32Bit UDS4:1; /**< \brief [19:19] Enable/disable sending of User Defined Symbol 4 (rw) */
+ Ifx_Strict_32Bit UDS5:1; /**< \brief [20:20] Enable/disable sending of User Defined Symbol 5 (rw) */
+ Ifx_Strict_32Bit UDS6:1; /**< \brief [21:21] Enable/disable sending of User Defined Symbol 6 (rw) */
+ Ifx_Strict_32Bit UDS7:1; /**< \brief [22:22] Enable/disable sending of User Defined Symbol 7 (rw) */
+ Ifx_Strict_32Bit UDS8:1; /**< \brief [23:23] Enable/disable sending of User Defined Symbol 8 (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CIF_DP_CTRL_Bits;
+
+/** \brief Debug Path Frame/Line Counter Status Register */
+typedef struct _Ifx_CIF_DP_FLC_STAT_Bits
+{
+ Ifx_Strict_32Bit FNC_VAL:15; /**< \brief [14:0] Returns the current value of the Frame Number Counter (r) */
+ Ifx_Strict_32Bit reserved_15:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit LNC_VAL:15; /**< \brief [30:16] Returns the current value of the Line Number Counter (r) */
+ Ifx_Strict_32Bit reserved_31:1; /**< \brief \internal Reserved */
+} Ifx_CIF_DP_FLC_STAT_Bits;
+
+/** \brief Debug Path Predivider Control Register */
+typedef struct _Ifx_CIF_DP_PDIV_CTRL_Bits
+{
+ Ifx_Strict_32Bit PDIV_VAL:32; /**< \brief [31:0] If the Debug Path and the Timestamp Counter are enabled, the timestamp counter will be increased with every pdiv_val+1 CIF module clock cycle. (rw) */
+} Ifx_CIF_DP_PDIV_CTRL_Bits;
+
+/** \brief Debug Path Predivider Counter Status Register */
+typedef struct _Ifx_CIF_DP_PDIV_STAT_Bits
+{
+ Ifx_Strict_32Bit PDIV_VAL:32; /**< \brief [31:0] Returns the current value of the Predivider Counter. (r) */
+} Ifx_CIF_DP_PDIV_STAT_Bits;
+
+/** \brief Debug Path Timestamp Counter Status Register */
+typedef struct _Ifx_CIF_DP_TSC_STAT_Bits
+{
+ Ifx_Strict_32Bit TSC_VAL:30; /**< \brief [29:0] Returns the current value of the Timestamp Counter. (r) */
+ Ifx_Strict_32Bit reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_CIF_DP_TSC_STAT_Bits;
+
+/** \brief Debug Path User Defined Symbol Register */
+typedef struct _Ifx_CIF_DP_UDS_Bits
+{
+ Ifx_Strict_32Bit UDS:15; /**< \brief [14:0] User Defined Symbol which may be inserted into debug stream (rw) */
+ Ifx_Strict_32Bit reserved_15:17; /**< \brief \internal Reserved */
+} Ifx_CIF_DP_UDS_Bits;
+
+/** \brief CIF Data Path Control Register */
+typedef struct _Ifx_CIF_DPCL_Bits
+{
+ Ifx_Strict_32Bit CIF_MP_MUX:2; /**< \brief [1:0] Data path selector for main path (rw) */
+ Ifx_Strict_32Bit CIF_CHAN_MODE:2; /**< \brief [3:2] Y/C splitter channel mode (rw) */
+ Ifx_Strict_32Bit reserved_4:4; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit IF_SELECT:2; /**< \brief [9:8] Selects input interface (rw) */
+ Ifx_Strict_32Bit reserved_10:22; /**< \brief \internal Reserved */
+} Ifx_CIF_DPCL_Bits;
+
+/** \brief Extra Path Image Cropping Control Register */
+typedef struct _Ifx_CIF_EP_IC_CTRL_Bits
+{
+ Ifx_Strict_32Bit IC_EN:1; /**< \brief [0:0] Image Cropping Enable (rw) */
+ Ifx_Strict_32Bit reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_CIF_EP_IC_CTRL_Bits;
+
+/** \brief Extra Path Image Cropping Camera Displacement Register */
+typedef struct _Ifx_CIF_EP_IC_DISPLACE_Bits
+{
+ Ifx_Strict_32Bit DX:12; /**< \brief [11:0] Camera Displacement (rw) */
+ Ifx_Strict_32Bit reserved_12:4; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit DY:12; /**< \brief [27:16] Camera Displacement (rw) */
+ Ifx_Strict_32Bit reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_CIF_EP_IC_DISPLACE_Bits;
+
+/** \brief Extra Path Image Cropping Horizontal Offset of Output Window
+ * Register */
+typedef struct _Ifx_CIF_EP_IC_H_OFFS_Bits
+{
+ Ifx_Strict_32Bit H_OFFS:12; /**< \brief [11:0] Horizontal Picture Offset (rw) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_CIF_EP_IC_H_OFFS_Bits;
+
+/** \brief Extra Path Image Current Horizontal Offset Of Output Window Shadow
+ * Register */
+typedef struct _Ifx_CIF_EP_IC_H_OFFS_SHD_Bits
+{
+ Ifx_Strict_32Bit H_OFFS_SHD:13; /**< \brief [12:0] Horizontal Picture Offset (r) */
+ Ifx_Strict_32Bit reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_CIF_EP_IC_H_OFFS_SHD_Bits;
+
+/** \brief Extra Path Image Cropping Output Horizontal Picture Size Register */
+typedef struct _Ifx_CIF_EP_IC_H_SIZE_Bits
+{
+ Ifx_Strict_32Bit H_SIZE:12; /**< \brief [11:0] Horizontal Picture Size (rw) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_CIF_EP_IC_H_SIZE_Bits;
+
+/** \brief Extra Path Image Current Output Horizontal Picture Size Shadow
+ * Register */
+typedef struct _Ifx_CIF_EP_IC_H_SIZE_SHD_Bits
+{
+ Ifx_Strict_32Bit H_SIZE_SHD:13; /**< \brief [12:0] Horizontal Picture Size (r) */
+ Ifx_Strict_32Bit reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_CIF_EP_IC_H_SIZE_SHD_Bits;
+
+/** \brief Extra Path Image Cropping Maximum Horizontal Displacement Register */
+typedef struct _Ifx_CIF_EP_IC_MAX_DX_Bits
+{
+ Ifx_Strict_32Bit MAX_DX:12; /**< \brief [11:0] Maximum Horizontal Displacement (rw) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_CIF_EP_IC_MAX_DX_Bits;
+
+/** \brief Extra Path Image Cropping Maximum Vertical Displacement Register */
+typedef struct _Ifx_CIF_EP_IC_MAX_DY_Bits
+{
+ Ifx_Strict_32Bit MAX_DY:12; /**< \brief [11:0] Maximum Vertical Displacement (rw) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_CIF_EP_IC_MAX_DY_Bits;
+
+/** \brief Extra Path Image Cropping Recenter Register */
+typedef struct _Ifx_CIF_EP_IC_RECENTER_Bits
+{
+ Ifx_Strict_32Bit RECENTER:3; /**< \brief [2:0] Recenter (rw) */
+ Ifx_Strict_32Bit reserved_3:29; /**< \brief \internal Reserved */
+} Ifx_CIF_EP_IC_RECENTER_Bits;
+
+/** \brief Extra Path Image Cropping Vertical Offset Of Output Window Register */
+typedef struct _Ifx_CIF_EP_IC_V_OFFS_Bits
+{
+ Ifx_Strict_32Bit V_OFFS:12; /**< \brief [11:0] Vertical Picture Offset (rw) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_CIF_EP_IC_V_OFFS_Bits;
+
+/** \brief Extra Path Image Current Vertical Offset Of Output Window Shadow
+ * Register */
+typedef struct _Ifx_CIF_EP_IC_V_OFFS_SHD_Bits
+{
+ Ifx_Strict_32Bit V_OFFS_SHD:12; /**< \brief [11:0] Vertical Picture Offset (r) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_CIF_EP_IC_V_OFFS_SHD_Bits;
+
+/** \brief Extra Path Image Cropping Output Vertical Picture Size Register */
+typedef struct _Ifx_CIF_EP_IC_V_SIZE_Bits
+{
+ Ifx_Strict_32Bit V_SIZE:12; /**< \brief [11:0] Vertical Picture Size (rw) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_CIF_EP_IC_V_SIZE_Bits;
+
+/** \brief Extra Path Image Current Output Vertical Picture Size Shadow
+ * Register */
+typedef struct _Ifx_CIF_EP_IC_V_SIZE_SHD_Bits
+{
+ Ifx_Strict_32Bit V_SIZE_SHD:12; /**< \brief [11:0] Vertical Picture Size (r) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_CIF_EP_IC_V_SIZE_SHD_Bits;
+
+/** \brief CIF Internal Clock Control Register */
+typedef struct _Ifx_CIF_ICCL_Bits
+{
+ Ifx_Strict_32Bit CIF_ISP_CLK_ENABLE:1; /**< \brief [0:0] ISP processing clock enable (rw) */
+ Ifx_Strict_32Bit reserved_1:4; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit CIF_JPEG_CLK_ENABLE:1; /**< \brief [5:5] JPEG encoder clock enable (rw) */
+ Ifx_Strict_32Bit CIF_MI_CLK_ENABLE:1; /**< \brief [6:6] Memory interface clock enable (rw) */
+ Ifx_Strict_32Bit reserved_7:9; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit CIF_WATCHDOG_CLK_ENABLE:1; /**< \brief [16:16] Security Watchdog clock enable (rw) */
+ Ifx_Strict_32Bit CIF_LIN_DSCALER_CLK_ENABLE:1; /**< \brief [17:17] Linear Downscaler clock enable (rw) */
+ Ifx_Strict_32Bit CIF_EXTRA_PATHS_CLK_ENABLE:1; /**< \brief [18:18] Extra Paths clock enable (rw) */
+ Ifx_Strict_32Bit CIF_DEBUG_PATH_CLK_EN:1; /**< \brief [19:19] Debug Path clock enable (rw) */
+ Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_CIF_ICCL_Bits;
+
+/** \brief CIF Revision Identification Register */
+typedef struct _Ifx_CIF_ID_Bits
+{
+ Ifx_Strict_32Bit MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ Ifx_Strict_32Bit MODTYPE:8; /**< \brief [15:8] Module Type (r) */
+ Ifx_Strict_32Bit MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_CIF_ID_Bits;
+
+/** \brief CIF Internal Reset Control Register */
+typedef struct _Ifx_CIF_IRCL_Bits
+{
+ Ifx_Strict_32Bit CIF_ISP_SOFT_RST:1; /**< \brief [0:0] Isp software reset (rw) */
+ Ifx_Strict_32Bit reserved_1:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit CIF_YCS_SOFT_RST:1; /**< \brief [2:2] Y/C splitter software reset (rw) */
+ Ifx_Strict_32Bit reserved_3:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit CIF_JPEG_SOFT_RST:1; /**< \brief [5:5] JPEG encoder software reset (rw) */
+ Ifx_Strict_32Bit CIF_MI_SOFT_RST:1; /**< \brief [6:6] Memory interface software reset (rw) */
+ Ifx_Strict_32Bit CIF_GLOBAL_RST:1; /**< \brief [7:7] Soft reset of entire CIF (rw) */
+ Ifx_Strict_32Bit reserved_8:8; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit CIF_WATCHDOG_RST:1; /**< \brief [16:16] Securtiy Watchdog software reset (rw) */
+ Ifx_Strict_32Bit CIF_LIN_DSCALER_RST:1; /**< \brief [17:17] Linear Downscaler software reset (rw) */
+ Ifx_Strict_32Bit CIF_EXTRA_PATHS_RST:1; /**< \brief [18:18] Extra Paths software reset (rw) */
+ Ifx_Strict_32Bit CIF_DEBUG_PATH_RST:1; /**< \brief [19:19] Debug Path software reset (rw) */
+ Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_CIF_IRCL_Bits;
+
+/** \brief ISP Acquisition Horizontal Offset Register */
+typedef struct _Ifx_CIF_ISP_ACQ_H_OFFS_Bits
+{
+ Ifx_Strict_32Bit ACQ_H_OFFS:13; /**< \brief [12:0] Horizontal sample offset (rw) */
+ Ifx_Strict_32Bit reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_CIF_ISP_ACQ_H_OFFS_Bits;
+
+/** \brief ISP Acquisition Horizontal Size Register */
+typedef struct _Ifx_CIF_ISP_ACQ_H_SIZE_Bits
+{
+ Ifx_Strict_32Bit ACQ_H_SIZE:13; /**< \brief [12:0] Horizontal sample size (rw) */
+ Ifx_Strict_32Bit reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_CIF_ISP_ACQ_H_SIZE_Bits;
+
+/** \brief ISP Acquisition Number of Frames Register */
+typedef struct _Ifx_CIF_ISP_ACQ_NR_FRAMES_Bits
+{
+ Ifx_Strict_32Bit ACQ_NR_FRAMES:10; /**< \brief [9:0] Number of Input Frames (rw) */
+ Ifx_Strict_32Bit reserved_10:22; /**< \brief \internal Reserved */
+} Ifx_CIF_ISP_ACQ_NR_FRAMES_Bits;
+
+/** \brief ISP Acquisition Properties Register */
+typedef struct _Ifx_CIF_ISP_ACQ_PROP_Bits
+{
+ Ifx_Strict_32Bit SAMPLE_EDGE:1; /**< \brief [0:0] Sample Edge (rw) */
+ Ifx_Strict_32Bit HSYNC_POL:1; /**< \brief [1:1] Horizontal sync polarity (rw) */
+ Ifx_Strict_32Bit VSYNC_POL:1; /**< \brief [2:2] Vertical sync polarity (rw) */
+ Ifx_Strict_32Bit reserved_3:4; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit CCIR_SEQ:2; /**< \brief [8:7] CCIR Sequence (rw) */
+ Ifx_Strict_32Bit FIELD_SELECTION:2; /**< \brief [10:9] Field Selection (rw) */
+ Ifx_Strict_32Bit FIELD_INVERT:1; /**< \brief [11:11] Field Invert (rw) */
+ Ifx_Strict_32Bit INPUT_SELECTION:4; /**< \brief [15:12] Input Selection (rw) */
+ Ifx_Strict_32Bit reserved_16:4; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit INPUT_SELECTION_NO_APP:1; /**< \brief [20:20] Input Selection No Append (rw) */
+ Ifx_Strict_32Bit reserved_21:11; /**< \brief \internal Reserved */
+} Ifx_CIF_ISP_ACQ_PROP_Bits;
+
+/** \brief ISP Acquistion Vertical Offset Register */
+typedef struct _Ifx_CIF_ISP_ACQ_V_OFFS_Bits
+{
+ Ifx_Strict_32Bit ACQ_V_OFFS:12; /**< \brief [11:0] Vertical sample offset (rw) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_CIF_ISP_ACQ_V_OFFS_Bits;
+
+/** \brief ISP Acquisition Vertical Size Register */
+typedef struct _Ifx_CIF_ISP_ACQ_V_SIZE_Bits
+{
+ Ifx_Strict_32Bit ACQ_V_SIZE:12; /**< \brief [11:0] Vertical sample size (rw) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_CIF_ISP_ACQ_V_SIZE_Bits;
+
+/** \brief ISP Global Control Register */
+typedef struct _Ifx_CIF_ISP_CTRL_Bits
+{
+ Ifx_Strict_32Bit ISP_ENABLE:1; /**< \brief [0:0] ISP output enable (rw) */
+ Ifx_Strict_32Bit ISP_MODE:3; /**< \brief [3:1] ISP Mode (rw) */
+ Ifx_Strict_32Bit ISP_INFORM_ENABLE:1; /**< \brief [4:4] ISP Input Formater Enable (rw) */
+ Ifx_Strict_32Bit reserved_5:4; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit ISP_CFG_UPD:1; /**< \brief [9:9] ISP Config Update (w) */
+ Ifx_Strict_32Bit ISP_GEN_CFG_UPD:1; /**< \brief [10:10] ISP Generate Config Update (w) */
+ Ifx_Strict_32Bit reserved_11:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit ISP_CSM_Y_RANGE:1; /**< \brief [13:13] Color Space Matrix luminance clipping range for ISP output (rw) */
+ Ifx_Strict_32Bit ISP_CSM_C_RANGE:1; /**< \brief [14:14] Color Space Matrix chrominance clipping range for ISP output (rw) */
+ Ifx_Strict_32Bit reserved_15:17; /**< \brief \internal Reserved */
+} Ifx_CIF_ISP_CTRL_Bits;
+
+/** \brief ISP Error Register */
+typedef struct _Ifx_CIF_ISP_ERR_Bits
+{
+ Ifx_Strict_32Bit INFORM_SIZE_ERR:1; /**< \brief [0:0] Size error is generated in inform submodule (r) */
+ Ifx_Strict_32Bit IS_SIZE_ERR:1; /**< \brief [1:1] Size error is generated in image stabilization submodule (r) */
+ Ifx_Strict_32Bit OUTFORM_SIZE_ERR:1; /**< \brief [2:2] Size error is generated in outmux submodule (r) */
+ Ifx_Strict_32Bit reserved_3:29; /**< \brief \internal Reserved */
+} Ifx_CIF_ISP_ERR_Bits;
+
+/** \brief ISP Error Clear Register */
+typedef struct _Ifx_CIF_ISP_ERR_CLR_Bits
+{
+ Ifx_Strict_32Bit INFORM_SIZE_ERR_CLR:1; /**< \brief [0:0] Size error is cleared (w) */
+ Ifx_Strict_32Bit IS_SIZE_ERR_CLR:1; /**< \brief [1:1] Size error is cleared (w) */
+ Ifx_Strict_32Bit OUTFORM_SIZE_ERR_CLR:1; /**< \brief [2:2] Size error is cleared (w) */
+ Ifx_Strict_32Bit reserved_3:29; /**< \brief \internal Reserved */
+} Ifx_CIF_ISP_ERR_CLR_Bits;
+
+/** \brief ISP Shadow Flags Register */
+typedef struct _Ifx_CIF_ISP_FLAGS_SHD_Bits
+{
+ Ifx_Strict_32Bit ISP_ENABLE_SHD:1; /**< \brief [0:0] ISP enable shadow register (r) */
+ Ifx_Strict_32Bit ISP_INFORM_ENABLE_SHD:1; /**< \brief [1:1] Input formatter enable shadow register (r) */
+ Ifx_Strict_32Bit INFORM_FIELD:1; /**< \brief [2:2] Current field information (r) */
+ Ifx_Strict_32Bit reserved_3:11; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit S_DATA:16; /**< \brief [29:14] State of ISP input port s_data (r) */
+ Ifx_Strict_32Bit S_VSYNC:1; /**< \brief [30:30] State of ISP input port s_vsync (r) */
+ Ifx_Strict_32Bit S_HSYNC:1; /**< \brief [31:31] State of ISP input port s_hsync (r) */
+} Ifx_CIF_ISP_FLAGS_SHD_Bits;
+
+/** \brief ISP Frame Counter Register */
+typedef struct _Ifx_CIF_ISP_FRAME_COUNT_Bits
+{
+ Ifx_Strict_32Bit FRAME_COUNTER:10; /**< \brief [9:0] Current Frame Count of Processing (r) */
+ Ifx_Strict_32Bit reserved_10:22; /**< \brief \internal Reserved */
+} Ifx_CIF_ISP_FRAME_COUNT_Bits;
+
+/** \brief ISP Interrupt Clear Register */
+typedef struct _Ifx_CIF_ISP_ICR_Bits
+{
+ Ifx_Strict_32Bit ICR_ISP_OFF:1; /**< \brief [0:0] Isp was Turned Off (vsynced) (w) */
+ Ifx_Strict_32Bit ICR_FRAME:1; /**< \brief [1:1] Frame was Completely Put Out (w) */
+ Ifx_Strict_32Bit ICR_DATA_LOSS:1; /**< \brief [2:2] Loss of Data (w) */
+ Ifx_Strict_32Bit ICR_PIC_SIZE_ERR:1; /**< \brief [3:3] Pic Size Violation Occurred (w) */
+ Ifx_Strict_32Bit reserved_4:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit ICR_FRAME_IN:1; /**< \brief [5:5] Sampled Input Frame is Complete (w) */
+ Ifx_Strict_32Bit ICR_V_START:1; /**< \brief [6:6] Start Edge of v_sync (w) */
+ Ifx_Strict_32Bit ICR_H_START:1; /**< \brief [7:7] Start Edge of h_sync (w) */
+ Ifx_Strict_32Bit reserved_8:11; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit ICR_WD_TRIG:1; /**< \brief [19:19] A watchdog timeout was triggered at the ISP input (w) */
+ Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_CIF_ISP_ICR_Bits;
+
+/** \brief ISP Interrupt Mask Register */
+typedef struct _Ifx_CIF_ISP_IMSC_Bits
+{
+ Ifx_Strict_32Bit IMSC_ISP_OFF:1; /**< \brief [0:0] Isp was Turned Off (vsynced) (rw) */
+ Ifx_Strict_32Bit IMSC_FRAME:1; /**< \brief [1:1] Frame was Completely Put Out (rw) */
+ Ifx_Strict_32Bit IMSC_DATA_LOSS:1; /**< \brief [2:2] Loss of Data (rw) */
+ Ifx_Strict_32Bit IMSC_PIC_SIZE_ERR:1; /**< \brief [3:3] Pic Size Violation Occurred (rw) */
+ Ifx_Strict_32Bit reserved_4:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit IMSC_FRAME_IN:1; /**< \brief [5:5] Sampled Input Frame is Complete (rw) */
+ Ifx_Strict_32Bit IMSC_V_START:1; /**< \brief [6:6] Start Edge of v_sync (rw) */
+ Ifx_Strict_32Bit IMSC_H_START:1; /**< \brief [7:7] Start Edge of h_sync (rw) */
+ Ifx_Strict_32Bit reserved_8:11; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit IMSC_WD_TRIG:1; /**< \brief [19:19] A watchdog timeout was triggered at the ISP input (rw) */
+ Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_CIF_ISP_IMSC_Bits;
+
+/** \brief ISP Interrupt Set Register */
+typedef struct _Ifx_CIF_ISP_ISR_Bits
+{
+ Ifx_Strict_32Bit ISR_ISP_OFF:1; /**< \brief [0:0] Isp was Turned Off (vsynced) (w) */
+ Ifx_Strict_32Bit ISR_FRAME:1; /**< \brief [1:1] Frame was Completely Put Out (w) */
+ Ifx_Strict_32Bit ISR_DATA_LOSS:1; /**< \brief [2:2] Loss of Data (w) */
+ Ifx_Strict_32Bit ISR_PIC_SIZE_ERR:1; /**< \brief [3:3] Pic Size Violation Occurred (w) */
+ Ifx_Strict_32Bit reserved_4:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit ISR_FRAME_IN:1; /**< \brief [5:5] Sampled Input Frame is Complete (w) */
+ Ifx_Strict_32Bit ISR_V_START:1; /**< \brief [6:6] Start Edge of v_sync (w) */
+ Ifx_Strict_32Bit ISR_H_START:1; /**< \brief [7:7] Start Edge of h_sync (w) */
+ Ifx_Strict_32Bit reserved_8:11; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit ISR_WD_TRIG:1; /**< \brief [19:19] A watchdog timeout was triggered at the ISP input (w) */
+ Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_CIF_ISP_ISR_Bits;
+
+/** \brief ISP Masked Interrupt Status Register */
+typedef struct _Ifx_CIF_ISP_MIS_Bits
+{
+ Ifx_Strict_32Bit MIS_ISP_OFF:1; /**< \brief [0:0] Isp was Turned Off (vsynced) (r) */
+ Ifx_Strict_32Bit MIS_FRAME:1; /**< \brief [1:1] Frame was Completely Put Out (r) */
+ Ifx_Strict_32Bit MIS_DATA_LOSS:1; /**< \brief [2:2] Loss of Data (r) */
+ Ifx_Strict_32Bit MIS_PIC_SIZE_ERR:1; /**< \brief [3:3] Pic Size Violation Occurred (r) */
+ Ifx_Strict_32Bit reserved_4:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit MIS_FRAME_IN:1; /**< \brief [5:5] Sampled Input Frame is Complete (r) */
+ Ifx_Strict_32Bit MIS_V_START:1; /**< \brief [6:6] Start Edge of v_sync (r) */
+ Ifx_Strict_32Bit MIS_H_START:1; /**< \brief [7:7] Start Edge of h_sync (r) */
+ Ifx_Strict_32Bit reserved_8:11; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit MIS_WD_TRIG:1; /**< \brief [19:19] A watchdog timeout was triggered at the ISP input (r) */
+ Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_CIF_ISP_MIS_Bits;
+
+/** \brief ISP Output Window Horizontal Offset Register */
+typedef struct _Ifx_CIF_ISP_OUT_H_OFFS_Bits
+{
+ Ifx_Strict_32Bit ISP_OUT_H_OFFS:12; /**< \brief [11:0] Horizontal Picture Offset (rw) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_CIF_ISP_OUT_H_OFFS_Bits;
+
+/** \brief ISP Output Window Horizontal Offset Shadow Register */
+typedef struct _Ifx_CIF_ISP_OUT_H_OFFS_SHD_Bits
+{
+ Ifx_Strict_32Bit ISP_OUT_H_OFFS_SHD:12; /**< \brief [11:0] Current horizontal picture offset (r) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_CIF_ISP_OUT_H_OFFS_SHD_Bits;
+
+/** \brief ISP Output Horizontal Picture Size Register */
+typedef struct _Ifx_CIF_ISP_OUT_H_SIZE_Bits
+{
+ Ifx_Strict_32Bit ISP_OUT_H_SIZE:12; /**< \brief [11:0] Horizontal picture size (rw) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_CIF_ISP_OUT_H_SIZE_Bits;
+
+/** \brief ISP Output Horizontal Picture Size Shadow Register */
+typedef struct _Ifx_CIF_ISP_OUT_H_SIZE_SHD_Bits
+{
+ Ifx_Strict_32Bit ISP_OUT_H_SIZE_SHD:13; /**< \brief [12:0] Current horizontal picture size (r) */
+ Ifx_Strict_32Bit reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_CIF_ISP_OUT_H_SIZE_SHD_Bits;
+
+/** \brief ISP Output Window Vertical Offset Register */
+typedef struct _Ifx_CIF_ISP_OUT_V_OFFS_Bits
+{
+ Ifx_Strict_32Bit ISP_OUT_V_OFFS:12; /**< \brief [11:0] Vertical Picture Offset (rw) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_CIF_ISP_OUT_V_OFFS_Bits;
+
+/** \brief ISP Output Window Vertical Offset Shadow Register */
+typedef struct _Ifx_CIF_ISP_OUT_V_OFFS_SHD_Bits
+{
+ Ifx_Strict_32Bit ISP_OUT_V_OFFS_SHD:12; /**< \brief [11:0] Current vertical picture offset (r) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_CIF_ISP_OUT_V_OFFS_SHD_Bits;
+
+/** \brief ISP Output Vertical Picture Size Register */
+typedef struct _Ifx_CIF_ISP_OUT_V_SIZE_Bits
+{
+ Ifx_Strict_32Bit ISP_OUT_V_SIZE:12; /**< \brief [11:0] Vertical picture size (rw) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_CIF_ISP_OUT_V_SIZE_Bits;
+
+/** \brief ISP Output Vertical Picture Size Shadow Register */
+typedef struct _Ifx_CIF_ISP_OUT_V_SIZE_SHD_Bits
+{
+ Ifx_Strict_32Bit ISP_OUT_V_SIZE_SHD:12; /**< \brief [11:0] Current vertical pic size (r) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_CIF_ISP_OUT_V_SIZE_SHD_Bits;
+
+/** \brief ISP Raw Interrupt Status Register */
+typedef struct _Ifx_CIF_ISP_RIS_Bits
+{
+ Ifx_Strict_32Bit RIS_ISP_OFF:1; /**< \brief [0:0] Isp was Turned Off (vsynced) (r) */
+ Ifx_Strict_32Bit RIS_FRAME:1; /**< \brief [1:1] Frame was Completely Put Out (r) */
+ Ifx_Strict_32Bit RIS_DATA_LOSS:1; /**< \brief [2:2] Loss of Data (r) */
+ Ifx_Strict_32Bit RIS_PIC_SIZE_ERR:1; /**< \brief [3:3] Pic Size Violation Occurred (r) */
+ Ifx_Strict_32Bit reserved_4:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit RIS_FRAME_IN:1; /**< \brief [5:5] Sampled Input Frame is Complete (r) */
+ Ifx_Strict_32Bit RIS_V_START:1; /**< \brief [6:6] Start Edge of v_sync (r) */
+ Ifx_Strict_32Bit RIS_H_START:1; /**< \brief [7:7] Start Edge of h_sync (r) */
+ Ifx_Strict_32Bit reserved_8:11; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit RIS_WD_TRIG:1; /**< \brief [19:19] A watchdog timeout was triggered at the ISP input (r) */
+ Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_CIF_ISP_RIS_Bits;
+
+/** \brief ISP Image Stabilization Control Register */
+typedef struct _Ifx_CIF_ISPIS_CTRL_Bits
+{
+ Ifx_Strict_32Bit IS_EN:1; /**< \brief [0:0] Image Stabilization Enable (rw) */
+ Ifx_Strict_32Bit reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_CIF_ISPIS_CTRL_Bits;
+
+/** \brief ISP Image Stabilization Camera Displacement Register */
+typedef struct _Ifx_CIF_ISPIS_DISPLACE_Bits
+{
+ Ifx_Strict_32Bit DX:12; /**< \brief [11:0] Camera Displacement (rw) */
+ Ifx_Strict_32Bit reserved_12:4; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit DY:12; /**< \brief [27:16] Camera Displacement (rw) */
+ Ifx_Strict_32Bit reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_CIF_ISPIS_DISPLACE_Bits;
+
+/** \brief ISP Image Stabilization Horizontal Offset Of Output Window Register */
+typedef struct _Ifx_CIF_ISPIS_H_OFFS_Bits
+{
+ Ifx_Strict_32Bit IS_H_OFFS:12; /**< \brief [11:0] Horizontal Picture Offset (rw) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_CIF_ISPIS_H_OFFS_Bits;
+
+/** \brief SP Image Current Horizontal Offset Of Output Window Shadow Register */
+typedef struct _Ifx_CIF_ISPIS_H_OFFS_SHD_Bits
+{
+ Ifx_Strict_32Bit IS_H_OFFS_SHD:13; /**< \brief [12:0] Horizontal Picture Offset (r) */
+ Ifx_Strict_32Bit reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_CIF_ISPIS_H_OFFS_SHD_Bits;
+
+/** \brief ISP Image Stabilization Output Horizontal Picture Size Register */
+typedef struct _Ifx_CIF_ISPIS_H_SIZE_Bits
+{
+ Ifx_Strict_32Bit IS_H_SIZE:12; /**< \brief [11:0] Horizontal Picture Size (rw) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_CIF_ISPIS_H_SIZE_Bits;
+
+/** \brief ISP Image Current Output Horizontal Picture Size Shadow Register */
+typedef struct _Ifx_CIF_ISPIS_H_SIZE_SHD_Bits
+{
+ Ifx_Strict_32Bit ISP_H_SIZE_SHD:13; /**< \brief [12:0] Horizontal Picture Size (r) */
+ Ifx_Strict_32Bit reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_CIF_ISPIS_H_SIZE_SHD_Bits;
+
+/** \brief ISP Image Stabilization Maximum Horizontal Displacement Register */
+typedef struct _Ifx_CIF_ISPIS_MAX_DX_Bits
+{
+ Ifx_Strict_32Bit IS_MAX_DX:12; /**< \brief [11:0] Maximum Horizontal Displacement (rw) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_CIF_ISPIS_MAX_DX_Bits;
+
+/** \brief ISP Image Stabilization Maximum Vertical Displacement Register */
+typedef struct _Ifx_CIF_ISPIS_MAX_DY_Bits
+{
+ Ifx_Strict_32Bit IS_MAX_DY:12; /**< \brief [11:0] Maximum Vertical Displacement (rw) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_CIF_ISPIS_MAX_DY_Bits;
+
+/** \brief ISP Image Stabilization Recenter Register */
+typedef struct _Ifx_CIF_ISPIS_RECENTER_Bits
+{
+ Ifx_Strict_32Bit RECENTER:3; /**< \brief [2:0] Recenter (rw) */
+ Ifx_Strict_32Bit reserved_3:29; /**< \brief \internal Reserved */
+} Ifx_CIF_ISPIS_RECENTER_Bits;
+
+/** \brief ISP Image Stabilization Vertical Offset Of Output Window Register */
+typedef struct _Ifx_CIF_ISPIS_V_OFFS_Bits
+{
+ Ifx_Strict_32Bit IS_V_OFFS:12; /**< \brief [11:0] Vertical Picture Offset (rw) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_CIF_ISPIS_V_OFFS_Bits;
+
+/** \brief ISP Image Current Vertical Offset Of Output Window Shadow Register */
+typedef struct _Ifx_CIF_ISPIS_V_OFFS_SHD_Bits
+{
+ Ifx_Strict_32Bit IS_V_OFFS_SHD:12; /**< \brief [11:0] Vertical Picture Offset (r) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_CIF_ISPIS_V_OFFS_SHD_Bits;
+
+/** \brief ISP Image Stabilization Output Vertical Picture Size Register */
+typedef struct _Ifx_CIF_ISPIS_V_SIZE_Bits
+{
+ Ifx_Strict_32Bit IS_V_SIZE:12; /**< \brief [11:0] Vertical Picture Size (rw) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_CIF_ISPIS_V_SIZE_Bits;
+
+/** \brief ISP Image Current Output Vertical Picture Size Shadow Register */
+typedef struct _Ifx_CIF_ISPIS_V_SIZE_SHD_Bits
+{
+ Ifx_Strict_32Bit ISP_V_SIZE_SHD:12; /**< \brief [11:0] Vertical Picture Size (r) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_CIF_ISPIS_V_SIZE_SHD_Bits;
+
+/** \brief JPE Huffman Table Selector For AC Values Register */
+typedef struct _Ifx_CIF_JPE_AC_TABLE_SELECT_Bits
+{
+ Ifx_Strict_32Bit AC_TABLE_SELECT:3; /**< \brief [2:0] AC Table Selector (rw) */
+ Ifx_Strict_32Bit reserved_3:29; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_AC_TABLE_SELECT_Bits;
+
+/** \brief JPE Cb/Cr Value Scaling Control Register */
+typedef struct _Ifx_CIF_JPE_CBCR_SCALE_EN_Bits
+{
+ Ifx_Strict_32Bit CBCR_SCALE_EN:1; /**< \brief [0:0] Cb/Cr scale flag (rw) */
+ Ifx_Strict_32Bit reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_CBCR_SCALE_EN_Bits;
+
+/** \brief JPE Huffman Table Selector For DC Values Register */
+typedef struct _Ifx_CIF_JPE_DC_TABLE_SELECT_Bits
+{
+ Ifx_Strict_32Bit DC_TABLE_SELECT:3; /**< \brief [2:0] DC Table Selector (rw) */
+ Ifx_Strict_32Bit reserved_3:29; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_DC_TABLE_SELECT_Bits;
+
+/** \brief JPE Debug Information Register */
+typedef struct _Ifx_CIF_JPE_DEBUG_Bits
+{
+ Ifx_Strict_32Bit reserved_0:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit DEB_QIQ_TABLE_ACC:1; /**< \brief [2:2] QIQ Table Access (r) */
+ Ifx_Strict_32Bit DEB_VLC_ENCODE_BUSY:1; /**< \brief [3:3] VLC Encode Busy (r) */
+ Ifx_Strict_32Bit DEB_R2B_MEMORY_FULL:1; /**< \brief [4:4] R2B Memory Full (r) */
+ Ifx_Strict_32Bit DEB_VLC_TABLE_BUSY:1; /**< \brief [5:5] Debug VLC Table Busy (r) */
+ Ifx_Strict_32Bit reserved_6:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit DEB_BAD_TABLE_ACCESS:1; /**< \brief [8:8] Debug Bad Table Access (r) */
+ Ifx_Strict_32Bit reserved_9:23; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_DEBUG_Bits;
+
+/** \brief JPEG Codec Horizontal Image Size For Encoding Register */
+typedef struct _Ifx_CIF_JPE_ENC_HSIZE_Bits
+{
+ Ifx_Strict_32Bit ENC_HSIZE:12; /**< \brief [11:0] Horizontal Size (rw) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_ENC_HSIZE_Bits;
+
+/** \brief JPEG Codec Vertical Image Size For Encoding Register */
+typedef struct _Ifx_CIF_JPE_ENC_VSIZE_Bits
+{
+ Ifx_Strict_32Bit ENC_VSIZE:12; /**< \brief [11:0] Vertical Size (rw) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_ENC_VSIZE_Bits;
+
+/** \brief JPE Start Command To Start JFIF Stream Encoding Register */
+typedef struct _Ifx_CIF_JPE_ENCODE_Bits
+{
+ Ifx_Strict_32Bit ENCODE:1; /**< \brief [0:0] Encode (w) */
+ Ifx_Strict_32Bit reserved_1:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit CONT_MODE:2; /**< \brief [5:4] Encoder continuous mode (rw) */
+ Ifx_Strict_32Bit reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_ENCODE_Bits;
+
+/** \brief JPE Encode Mode Register */
+typedef struct _Ifx_CIF_JPE_ENCODE_MODE_Bits
+{
+ Ifx_Strict_32Bit ENCODE_MODE:1; /**< \brief [0:0] Encode Mode (r) */
+ Ifx_Strict_32Bit reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_ENCODE_MODE_Bits;
+
+/** \brief JPE Encoder Status Flag Register */
+typedef struct _Ifx_CIF_JPE_ENCODER_BUSY_Bits
+{
+ Ifx_Strict_32Bit CODEC_BUSY:1; /**< \brief [0:0] Codec Busy (r) */
+ Ifx_Strict_32Bit reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_ENCODER_BUSY_Bits;
+
+/** \brief JPE Error Interrupt Clear Register */
+typedef struct _Ifx_CIF_JPE_ERROR_ICR_Bits
+{
+ Ifx_Strict_32Bit reserved_0:4; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit VLC_SYMBOL_ERR:1; /**< \brief [4:4] VLC Symbol Error (w) */
+ Ifx_Strict_32Bit reserved_5:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit DCT_ERR:1; /**< \brief [7:7] DC Table Error (w) */
+ Ifx_Strict_32Bit reserved_8:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit R2B_IMG_SIZE_ERR:1; /**< \brief [9:9] R2B Image Size Error (w) */
+ Ifx_Strict_32Bit VLC_TABLE_ERR:1; /**< \brief [10:10] VLC Table Error (w) */
+ Ifx_Strict_32Bit reserved_11:21; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_ERROR_ICR_Bits;
+
+/** \brief JPE Error Interrupt Mask Register */
+typedef struct _Ifx_CIF_JPE_ERROR_IMR_Bits
+{
+ Ifx_Strict_32Bit reserved_0:4; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit VLC_SYMBOL_ERR:1; /**< \brief [4:4] VLC Symbol Error (rw) */
+ Ifx_Strict_32Bit reserved_5:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit DCT_ERR:1; /**< \brief [7:7] DC Table Error (rw) */
+ Ifx_Strict_32Bit reserved_8:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit R2B_IMG_SIZE_ERR:1; /**< \brief [9:9] R2B Image Size Error (rw) */
+ Ifx_Strict_32Bit VLC_TABLE_ERR:1; /**< \brief [10:10] VLC Table Error (rw) */
+ Ifx_Strict_32Bit reserved_11:21; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_ERROR_IMR_Bits;
+
+/** \brief JPE Error Interrupt Set Register */
+typedef struct _Ifx_CIF_JPE_ERROR_ISR_Bits
+{
+ Ifx_Strict_32Bit reserved_0:4; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit VLC_SYMBOL_ERR:1; /**< \brief [4:4] VLC Symbol Error (w) */
+ Ifx_Strict_32Bit reserved_5:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit DCT_ERR:1; /**< \brief [7:7] DC Table Error (w) */
+ Ifx_Strict_32Bit reserved_8:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit R2B_IMG_SIZE_ERR:1; /**< \brief [9:9] R2B Image Size Error (w) */
+ Ifx_Strict_32Bit VLC_TABLE_ERR:1; /**< \brief [10:10] VLC Table Error (w) */
+ Ifx_Strict_32Bit reserved_11:21; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_ERROR_ISR_Bits;
+
+/** \brief JPE Error Masked Interrupt Status Register */
+typedef struct _Ifx_CIF_JPE_ERROR_MIS_Bits
+{
+ Ifx_Strict_32Bit reserved_0:4; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit VLC_SYMBOL_ERR:1; /**< \brief [4:4] VLC Symbol Error (r) */
+ Ifx_Strict_32Bit reserved_5:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit DCT_ERR:1; /**< \brief [7:7] DC Table Error (r) */
+ Ifx_Strict_32Bit reserved_8:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit R2B_IMG_SIZE_ERR:1; /**< \brief [9:9] R2B Image Size Error (r) */
+ Ifx_Strict_32Bit VLC_TABLE_ERR:1; /**< \brief [10:10] VLC Table Error (r) */
+ Ifx_Strict_32Bit reserved_11:21; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_ERROR_MIS_Bits;
+
+/** \brief JPE Error Raw Interrupt Status Register */
+typedef struct _Ifx_CIF_JPE_ERROR_RIS_Bits
+{
+ Ifx_Strict_32Bit reserved_0:4; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit VLC_SYMBOL_ERR:1; /**< \brief [4:4] VLC Symbol Error (r) */
+ Ifx_Strict_32Bit reserved_5:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit DCT_ERR:1; /**< \brief [7:7] DC Table Error (r) */
+ Ifx_Strict_32Bit reserved_8:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit R2B_IMG_SIZE_ERR:1; /**< \brief [9:9] R2B Image Size Error (r) */
+ Ifx_Strict_32Bit VLC_TABLE_ERR:1; /**< \brief [10:10] VLC Table Error (r) */
+ Ifx_Strict_32Bit reserved_11:21; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_ERROR_RIS_Bits;
+
+/** \brief JPE Command To Start Stream Header Generation Register */
+typedef struct _Ifx_CIF_JPE_GEN_HEADER_Bits
+{
+ Ifx_Strict_32Bit GEN_HEADER:1; /**< \brief [0:0] Generate Header (w) */
+ Ifx_Strict_32Bit reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_GEN_HEADER_Bits;
+
+/** \brief JPE Header Mode Definition Register */
+typedef struct _Ifx_CIF_JPE_HEADER_MODE_Bits
+{
+ Ifx_Strict_32Bit HEADER_MODE:2; /**< \brief [1:0] Header Mode (rw) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_HEADER_MODE_Bits;
+
+/** \brief JPE Automatic Configuration Update Register */
+typedef struct _Ifx_CIF_JPE_INIT_Bits
+{
+ Ifx_Strict_32Bit JP_INIT:1; /**< \brief [0:0] JPEG Init (w) */
+ Ifx_Strict_32Bit reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_INIT_Bits;
+
+/** \brief JPEG Picture Encoding Format Register */
+typedef struct _Ifx_CIF_JPE_PIC_FORMAT_Bits
+{
+ Ifx_Strict_32Bit ENC_PIC_FORMAT:3; /**< \brief [2:0] Picture Encoding Format (rw) */
+ Ifx_Strict_32Bit reserved_3:29; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_PIC_FORMAT_Bits;
+
+/** \brief JPE Restart Marker Insertion Register */
+typedef struct _Ifx_CIF_JPE_RESTART_INTERVAL_Bits
+{
+ Ifx_Strict_32Bit RESTART_INTERVAL:16; /**< \brief [15:0] Restart Interval (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_RESTART_INTERVAL_Bits;
+
+/** \brief JPEG Status Interrupt Clear Register */
+typedef struct _Ifx_CIF_JPE_STATUS_ICR_Bits
+{
+ Ifx_Strict_32Bit reserved_0:4; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit ENCODE_DONE:1; /**< \brief [4:4] Encoding Complete (w) */
+ Ifx_Strict_32Bit GEN_HEADER_DONE:1; /**< \brief [5:5] Header Generation Complete (w) */
+ Ifx_Strict_32Bit reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_STATUS_ICR_Bits;
+
+/** \brief JPEG Status Interrupt Mask Register */
+typedef struct _Ifx_CIF_JPE_STATUS_IMR_Bits
+{
+ Ifx_Strict_32Bit reserved_0:4; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit ENCODE_DONE:1; /**< \brief [4:4] Encoding Complete (rw) */
+ Ifx_Strict_32Bit GEN_HEADER_DONE:1; /**< \brief [5:5] Header Generation Complete (rw) */
+ Ifx_Strict_32Bit reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_STATUS_IMR_Bits;
+
+/** \brief JPEG Status Interrupt Set Register */
+typedef struct _Ifx_CIF_JPE_STATUS_ISR_Bits
+{
+ Ifx_Strict_32Bit reserved_0:4; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit ENCODE_DONE:1; /**< \brief [4:4] Encoding Complete (w) */
+ Ifx_Strict_32Bit GEN_HEADER_DONE:1; /**< \brief [5:5] Header Generation Complete (w) */
+ Ifx_Strict_32Bit reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_STATUS_ISR_Bits;
+
+/** \brief JPEG Status Masked Interrupt Status Register */
+typedef struct _Ifx_CIF_JPE_STATUS_MIS_Bits
+{
+ Ifx_Strict_32Bit reserved_0:4; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit ENCODE_DONE:1; /**< \brief [4:4] Encoding Complete (r) */
+ Ifx_Strict_32Bit GEN_HEADER_DONE:1; /**< \brief [5:5] Header Generation Complete (r) */
+ Ifx_Strict_32Bit reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_STATUS_MIS_Bits;
+
+/** \brief JPEG Status Raw Interrupt Status Register */
+typedef struct _Ifx_CIF_JPE_STATUS_RIS_Bits
+{
+ Ifx_Strict_32Bit reserved_0:4; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit ENCODE_DONE:1; /**< \brief [4:4] Encoding Complete (r) */
+ Ifx_Strict_32Bit GEN_HEADER_DONE:1; /**< \brief [5:5] Header Generation Complete (r) */
+ Ifx_Strict_32Bit reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_STATUS_RIS_Bits;
+
+/** \brief JPE Table Programming Register */
+typedef struct _Ifx_CIF_JPE_TABLE_DATA_Bits
+{
+ Ifx_Strict_32Bit TABLE_WDATA_L:8; /**< \brief [7:0] Table data LSB (w) */
+ Ifx_Strict_32Bit TABLE_WDATA_H:8; /**< \brief [15:8] Table data MSB (w) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_TABLE_DATA_Bits;
+
+/** \brief JPE Header Generation Debug Register */
+typedef struct _Ifx_CIF_JPE_TABLE_FLUSH_Bits
+{
+ Ifx_Strict_32Bit TABLE_FLUSH:1; /**< \brief [0:0] Header generation debug control flag (rw) */
+ Ifx_Strict_32Bit reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_TABLE_FLUSH_Bits;
+
+/** \brief JPE Table Programming Select Register */
+typedef struct _Ifx_CIF_JPE_TABLE_ID_Bits
+{
+ Ifx_Strict_32Bit TABLE_ID:4; /**< \brief [3:0] JPE Table ID (rw) */
+ Ifx_Strict_32Bit reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_TABLE_ID_Bits;
+
+/** \brief JPE Huffman AC Table 0 Length Register */
+typedef struct _Ifx_CIF_JPE_TAC0_LEN_Bits
+{
+ Ifx_Strict_32Bit TAC0_LEN:8; /**< \brief [7:0] AC Table 0 Length (rw) */
+ Ifx_Strict_32Bit reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_TAC0_LEN_Bits;
+
+/** \brief JPE Huffman AC Table 1 Length Register */
+typedef struct _Ifx_CIF_JPE_TAC1_LEN_Bits
+{
+ Ifx_Strict_32Bit TAC1_LEN:8; /**< \brief [7:0] AC Table 1 Length (rw) */
+ Ifx_Strict_32Bit reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_TAC1_LEN_Bits;
+
+/** \brief JPE Huffman DC Table 0 Length Register */
+typedef struct _Ifx_CIF_JPE_TDC0_LEN_Bits
+{
+ Ifx_Strict_32Bit TDC0_LEN:8; /**< \brief [7:0] DC Table 0 Length (rw) */
+ Ifx_Strict_32Bit reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_TDC0_LEN_Bits;
+
+/** \brief JPE Huffman DC Table 1 Length Register */
+typedef struct _Ifx_CIF_JPE_TDC1_LEN_Bits
+{
+ Ifx_Strict_32Bit TDC1_LEN:8; /**< \brief [7:0] DC Table 1 Length (rw) */
+ Ifx_Strict_32Bit reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_TDC1_LEN_Bits;
+
+/** \brief Q- table Selector 1, Quant. Table For U Component */
+typedef struct _Ifx_CIF_JPE_TQ_U_SELECT_Bits
+{
+ Ifx_Strict_32Bit TQ1_SELECT:2; /**< \brief [1:0] Q-Table Selector U (rw) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_TQ_U_SELECT_Bits;
+
+/** \brief Q- table Selector 2 Quant Table For V Component */
+typedef struct _Ifx_CIF_JPE_TQ_V_SELECT_Bits
+{
+ Ifx_Strict_32Bit TQ2_SELECT:2; /**< \brief [1:0] Q-Table Selector V (rw) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_TQ_V_SELECT_Bits;
+
+/** \brief Q- table Selector 0 Quant Table For Y Component */
+typedef struct _Ifx_CIF_JPE_TQ_Y_SELECT_Bits
+{
+ Ifx_Strict_32Bit TQ0_SELECT:2; /**< \brief [1:0] Q-Table Selector Y (rw) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_TQ_Y_SELECT_Bits;
+
+/** \brief JPE Y Value Scaling Control Register */
+typedef struct _Ifx_CIF_JPE_Y_SCALE_EN_Bits
+{
+ Ifx_Strict_32Bit Y_SCALE_EN:1; /**< \brief [0:0] Y scale flag (rw) */
+ Ifx_Strict_32Bit reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_CIF_JPE_Y_SCALE_EN_Bits;
+
+/** \brief Linear Downscaler Control Register */
+typedef struct _Ifx_CIF_LDS_CTRL_Bits
+{
+ Ifx_Strict_32Bit LDS_V_EN:1; /**< \brief [0:0] Vertical scaling enable (rw) */
+ Ifx_Strict_32Bit LDS_H_EN:1; /**< \brief [1:1] Horizontal scaling enable (rw) */
+ Ifx_Strict_32Bit reserved_2:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit LDS_V_MODE:2; /**< \brief [5:4] Vertical scaling mode (rw) */
+ Ifx_Strict_32Bit reserved_6:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit LDS_H_MODE:2; /**< \brief [9:8] Horizontal scaling mode (rw) */
+ Ifx_Strict_32Bit reserved_10:22; /**< \brief \internal Reserved */
+} Ifx_CIF_LDS_CTRL_Bits;
+
+/** \brief Linear Downscaler Factor Register */
+typedef struct _Ifx_CIF_LDS_FAC_Bits
+{
+ Ifx_Strict_32Bit LDS_V_FAC:8; /**< \brief [7:0] Vertical scaling factor (rw) */
+ Ifx_Strict_32Bit reserved_8:8; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit LDS_H_FAC:8; /**< \brief [23:16] Horizontal scaling factor (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CIF_LDS_FAC_Bits;
+
+/** \brief Memory Interface Counter Value of JPEG or RAW Data Bytes Register */
+typedef struct _Ifx_CIF_MI_BYTE_CNT_Bits
+{
+ Ifx_Strict_32Bit BYTE_CNT:24; /**< \brief [23:0] Byte Count (r) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CIF_MI_BYTE_CNT_Bits;
+
+/** \brief Memory Interface Global Control Register */
+typedef struct _Ifx_CIF_MI_CTRL_Bits
+{
+ Ifx_Strict_32Bit MP_ENABLE:1; /**< \brief [0:0] Enables main picture data path, YCbCr mode (rw) */
+ Ifx_Strict_32Bit reserved_1:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit JPEG_ENABLE:1; /**< \brief [2:2] Enables JPEG mode (rw) */
+ Ifx_Strict_32Bit RAW_ENABLE:1; /**< \brief [3:3] Enables RAW mode (rw) */
+ Ifx_Strict_32Bit reserved_4:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit BYTE_SWAP:1; /**< \brief [7:7] Byte Swap Enable (rw) */
+ Ifx_Strict_32Bit reserved_8:8; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit BURST_LEN_LUM:1; /**< \brief [16:16] Luminance Burst Length (rw) */
+ Ifx_Strict_32Bit reserved_17:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit BURST_LEN_CHROM:1; /**< \brief [18:18] Chrominance Burst Length (rw) */
+ Ifx_Strict_32Bit reserved_19:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit INIT_BASE_EN:1; /**< \brief [20:20] Init Base Address Enable (rw) */
+ Ifx_Strict_32Bit INIT_OFFSET_EN:1; /**< \brief [21:21] Init Offset Counter Enable (rw) */
+ Ifx_Strict_32Bit MP_WRITE_FORMAT:2; /**< \brief [23:22] Main Picture YCbCr Write Format (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CIF_MI_CTRL_Bits;
+
+/** \brief Memory Interface Global Control Internal Shadow Register */
+typedef struct _Ifx_CIF_MI_CTRL_SHD_Bits
+{
+ Ifx_Strict_32Bit MP_ENABLE_IN:1; /**< \brief [0:0] Main Picture In Enable (r) */
+ Ifx_Strict_32Bit reserved_1:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit JPEG_ENABLE_IN:1; /**< \brief [4:4] JPEG In Enable (r) */
+ Ifx_Strict_32Bit RAW_ENABLE_IN:1; /**< \brief [5:5] RAW In Enable (r) */
+ Ifx_Strict_32Bit reserved_6:10; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit MP_ENABLE_OUT:1; /**< \brief [16:16] Main Picture Out Enable (r) */
+ Ifx_Strict_32Bit reserved_17:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit JPEG_ENABLE_OUT:1; /**< \brief [18:18] JPEG Out Enable (r) */
+ Ifx_Strict_32Bit RAW_ENABLE_OUT:1; /**< \brief [19:19] RAW Out Enable (r) */
+ Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_CIF_MI_CTRL_SHD_Bits;
+
+/** \brief MI Interrupt Clear Register */
+typedef struct _Ifx_CIF_MI_ICR_Bits
+{
+ Ifx_Strict_32Bit MP_FRAME_END:1; /**< \brief [0:0] Main Picture Frame End (w) */
+ Ifx_Strict_32Bit reserved_1:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit MBLK_LINE:1; /**< \brief [2:2] Macro Block Line Interrupt (w) */
+ Ifx_Strict_32Bit FILL_MPY:1; /**< \brief [3:3] Fill Main Picture Y (w) */
+ Ifx_Strict_32Bit WRAP_MP_Y:1; /**< \brief [4:4] Wrap Main Picture Y (w) */
+ Ifx_Strict_32Bit WRAP_MP_CB:1; /**< \brief [5:5] Wrap Main Picture Cb (w) */
+ Ifx_Strict_32Bit WRAP_MP_CR:1; /**< \brief [6:6] Wrap Main Picture Cr (w) */
+ Ifx_Strict_32Bit reserved_7:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit BUS_ERROR:1; /**< \brief [10:10] Bus Error (w) */
+ Ifx_Strict_32Bit reserved_11:21; /**< \brief \internal Reserved */
+} Ifx_CIF_MI_ICR_Bits;
+
+/** \brief MI Interrupt Mask ‘1’ interrupt active ‘0’ interrupt masked */
+typedef struct _Ifx_CIF_MI_IMSC_Bits
+{
+ Ifx_Strict_32Bit MP_FRAME_END:1; /**< \brief [0:0] Main Picture Frame End (rw) */
+ Ifx_Strict_32Bit reserved_1:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit MBLK_LINE:1; /**< \brief [2:2] Macro Block Line Interrupt (rw) */
+ Ifx_Strict_32Bit FILL_MP_Y:1; /**< \brief [3:3] Fill Main Picture Y (rw) */
+ Ifx_Strict_32Bit WRAP_MP_Y:1; /**< \brief [4:4] Wrap Main Picture Y (rw) */
+ Ifx_Strict_32Bit WRAP_MP_CB:1; /**< \brief [5:5] Wrap Main Picture Cb (rw) */
+ Ifx_Strict_32Bit WRAP_MP_CR:1; /**< \brief [6:6] Wrap Main Picture Cr (rw) */
+ Ifx_Strict_32Bit reserved_7:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit BUS_ERROR:1; /**< \brief [10:10] Bus Error (rw) */
+ Ifx_Strict_32Bit reserved_11:21; /**< \brief \internal Reserved */
+} Ifx_CIF_MI_IMSC_Bits;
+
+/** \brief Memory Interface Control Register For Address Init And Skip Function
+ * Register */
+typedef struct _Ifx_CIF_MI_INIT_Bits
+{
+ Ifx_Strict_32Bit reserved_0:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit MI_SKIP:1; /**< \brief [2:2] Skip Picture (w) */
+ Ifx_Strict_32Bit reserved_3:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit MI_CFG_UPD:1; /**< \brief [4:4] Forced Configuration Update (w) */
+ Ifx_Strict_32Bit reserved_5:27; /**< \brief \internal Reserved */
+} Ifx_CIF_MI_INIT_Bits;
+
+/** \brief MI Interrupt Set Register */
+typedef struct _Ifx_CIF_MI_ISR_Bits
+{
+ Ifx_Strict_32Bit MP_FRAME_END:1; /**< \brief [0:0] Main Picture Frame End (w) */
+ Ifx_Strict_32Bit reserved_1:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit MBLK_LINE:1; /**< \brief [2:2] Macro Block Line Interrupt (w) */
+ Ifx_Strict_32Bit FILL_MP_Y:1; /**< \brief [3:3] Fill Main Picture Y (w) */
+ Ifx_Strict_32Bit WRAP_MP_Y:1; /**< \brief [4:4] Wrap Main Picture Y (w) */
+ Ifx_Strict_32Bit WRAP_MP_CB:1; /**< \brief [5:5] Wrap Main Picture Cb (w) */
+ Ifx_Strict_32Bit WRAP_MP_CR:1; /**< \brief [6:6] Wrap Main Picture Cr (w) */
+ Ifx_Strict_32Bit reserved_7:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit Bus_ERROR:1; /**< \brief [10:10] Bus Error (w) */
+ Ifx_Strict_32Bit reserved_11:21; /**< \brief \internal Reserved */
+} Ifx_CIF_MI_ISR_Bits;
+
+/** \brief MI Masked Interrupt Status Registe */
+typedef struct _Ifx_CIF_MI_MIS_Bits
+{
+ Ifx_Strict_32Bit MP_FRAME_END:1; /**< \brief [0:0] Main Picture Frame End (r) */
+ Ifx_Strict_32Bit reserved_1:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit MBLK_LINE:1; /**< \brief [2:2] Macro Block Line Interrupt (r) */
+ Ifx_Strict_32Bit FILL_MP_Y:1; /**< \brief [3:3] Fill Main Picture Y (r) */
+ Ifx_Strict_32Bit WRAP_MP_Y:1; /**< \brief [4:4] Wrap Main Picture Y (r) */
+ Ifx_Strict_32Bit WRAP_MP_CB:1; /**< \brief [5:5] Wrap Main Picture Cb (r) */
+ Ifx_Strict_32Bit WRAP_MP_CR:1; /**< \brief [6:6] Wrap Main Picture Cr (r) */
+ Ifx_Strict_32Bit reserved_7:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit BUS_ERROR:1; /**< \brief [10:10] Bus Error (r) */
+ Ifx_Strict_32Bit reserved_11:21; /**< \brief \internal Reserved */
+} Ifx_CIF_MI_MIS_Bits;
+
+/** \brief Memory Interface Base Address For Main Picture Cb Component Ring
+ * Buffer Register */
+typedef struct _Ifx_CIF_MI_MP_CB_BASE_AD_INIT_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit MP_CB_BASEAD_INIT:30; /**< \brief [31:2] Main Picture Cb Base Address Init (rw) */
+} Ifx_CIF_MI_MP_CB_BASE_AD_INIT_Bits;
+
+/** \brief Memory Interface Base Address Shadow Register For Main Picture Cb
+ * Component Ring Register */
+typedef struct _Ifx_CIF_MI_MP_CB_BASE_AD_SHD_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit MP_CB_BASE_AD:30; /**< \brief [31:2] Main Picture Cb Base Address (r) */
+} Ifx_CIF_MI_MP_CB_BASE_AD_SHD_Bits;
+
+/** \brief Memory Interface Offset Counter Init Value For Main Picture Cb
+ * Component Ring Buffer Register */
+typedef struct _Ifx_CIF_MI_MP_CB_OFFS_CNT_INIT_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit MP_CB_OFFS_CNT_INIT:22; /**< \brief [23:2] Main Picture Cb Offset Counter Init (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CIF_MI_MP_CB_OFFS_CNT_INIT_Bits;
+
+/** \brief Memory Interface Current Offset Counter Of Main Picture Cb Component
+ * Ring Buffer Register */
+typedef struct _Ifx_CIF_MI_MP_CB_OFFS_CNT_SHD_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit MP_CB_OFFS_CNT:22; /**< \brief [23:2] Main Picture Cb Offset Counter (r) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CIF_MI_MP_CB_OFFS_CNT_SHD_Bits;
+
+/** \brief Memory Interface Offset Counter Start Value For Main Picture Cb
+ * Component Ring Buffer Register */
+typedef struct _Ifx_CIF_MI_MP_CB_OFFS_CNT_START_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit MP_CB_OFFS_CNT_START:22; /**< \brief [23:2] Main Picture Cb Offset Count Start (r) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CIF_MI_MP_CB_OFFS_CNT_START_Bits;
+
+/** \brief Memory Interface Size Of Main Picture Cb Component Ring Buffer
+ * Register */
+typedef struct _Ifx_CIF_MI_MP_CB_SIZE_INIT_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit MP_CB_SIZE_INIT:22; /**< \brief [23:2] Main Picture Cb Size Init (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CIF_MI_MP_CB_SIZE_INIT_Bits;
+
+/** \brief Memory Interface Size Shadow Register Of Main Picture Cb Component
+ * Ring Buffer Register */
+typedef struct _Ifx_CIF_MI_MP_CB_SIZE_SHD_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit MP_CB_SIZE:22; /**< \brief [23:2] Main Picture Cb Size (r) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CIF_MI_MP_CB_SIZE_SHD_Bits;
+
+/** \brief Memory Interface Base Address For Main Picture Cr Component Ring
+ * Buffer Register */
+typedef struct _Ifx_CIF_MI_MP_CR_BASE_AD_INIT_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit MP_CR_BASE_AD_INIT:30; /**< \brief [31:2] Main Picture Cr Base Address Init (rw) */
+} Ifx_CIF_MI_MP_CR_BASE_AD_INIT_Bits;
+
+/** \brief Memory Interface Base Address Shadow Register For Main Picture Cr
+ * Component Ring Register */
+typedef struct _Ifx_CIF_MI_MP_CR_BASE_AD_SHD_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit MP_CR_BASE_AD:30; /**< \brief [31:2] Main Picture Cr Base Address (r) */
+} Ifx_CIF_MI_MP_CR_BASE_AD_SHD_Bits;
+
+/** \brief Memory Interface Offset Counter Init value For Main Picture Cr
+ * Component Ring Buffer Register */
+typedef struct _Ifx_CIF_MI_MP_CR_OFFS_CNT_INIT_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit MP_CR_OFFS_CNT_INIT:22; /**< \brief [23:2] Main Picture Cr Offset Counter Init (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CIF_MI_MP_CR_OFFS_CNT_INIT_Bits;
+
+/** \brief Memory Interface Current Offset Counter Of Main Picture Cr Component
+ * Ring Buffer Register */
+typedef struct _Ifx_CIF_MI_MP_CR_OFFS_CNT_SHD_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit MP_CR_OFFS_CNT:22; /**< \brief [23:2] Main Picture Cr Offset Counter (r) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CIF_MI_MP_CR_OFFS_CNT_SHD_Bits;
+
+/** \brief Memory Interface Offset Counter Start Value For Main Picture Cr
+ * Component Ring Buffer Register */
+typedef struct _Ifx_CIF_MI_MP_CR_OFFS_CNT_START_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit MP_CR_OFFS_CNT_START:22; /**< \brief [23:2] Main Picture Cr Offset Counter Start (r) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CIF_MI_MP_CR_OFFS_CNT_START_Bits;
+
+/** \brief Memory Interface Size Of Main Picture Cr Component Ring Buffer
+ * Register */
+typedef struct _Ifx_CIF_MI_MP_CR_SIZE_INIT_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit MP_CR_SIZE_INIT:22; /**< \brief [23:2] Main Picture Cr Size Init (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CIF_MI_MP_CR_SIZE_INIT_Bits;
+
+/** \brief Memory Interface Size Shadow Register Of Main Picture Cr Component
+ * Ring Buffer Register */
+typedef struct _Ifx_CIF_MI_MP_CR_SIZE_SHD_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit MP_CR_SIZE:22; /**< \brief [23:2] Main Picture Cr Size (r) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CIF_MI_MP_CR_SIZE_SHD_Bits;
+
+/** \brief Memory Interface Base Address For Main Picture Y Component, JPEG or
+ * RAW Data Register */
+typedef struct _Ifx_CIF_MI_MP_Y_BASE_AD_INIT_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit MP_Y_BASE_AD_INIT:30; /**< \brief [31:2] Main Picture Y Base Address Init (rw) */
+} Ifx_CIF_MI_MP_Y_BASE_AD_INIT_Bits;
+
+/** \brief Memory Interface Base Address Shadow Register For Main Picture Y
+ * Component, JPEG Register */
+typedef struct _Ifx_CIF_MI_MP_Y_BASE_AD_SHD_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit MP_Y_BASE_AD:30; /**< \brief [31:2] Main Picture Y Base Address (r) */
+} Ifx_CIF_MI_MP_Y_BASE_AD_SHD_Bits;
+
+/** \brief Memory Interface Fill Level Interrupt Offset Value For Main Picture
+ * Y, JPEG or RAW Data Register */
+typedef struct _Ifx_CIF_MI_MP_Y_IRQ_OFFS_INIT_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit MP_Y_IRQ_OFFS_INIT:22; /**< \brief [23:2] Main Picture Y IRQ Offset Init (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CIF_MI_MP_Y_IRQ_OFFS_INIT_Bits;
+
+/** \brief Memory Interface Shadow Register of Fill Level Interrupt Offset
+ * Value For Main Picture Y Register */
+typedef struct _Ifx_CIF_MI_MP_Y_IRQ_OFFS_SHD_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit MP_Y_IRQ_OFFS:22; /**< \brief [23:2] Main Picture Y IRQ Offset (r) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CIF_MI_MP_Y_IRQ_OFFS_SHD_Bits;
+
+/** \brief Memory Interface Offset Counter Init Value For Main Picture Y, JPEG
+ * or RAW Data Register */
+typedef struct _Ifx_CIF_MI_MP_Y_OFFS_CNT_INIT_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit MP_Y_OFFS_CNT_INIT:22; /**< \brief [23:2] Main Picture Y Offset Counter Init (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CIF_MI_MP_Y_OFFS_CNT_INIT_Bits;
+
+/** \brief Memory Interface Current Offset Counter of Main Picture Y Component
+ * JPEG or RAW Register */
+typedef struct _Ifx_CIF_MI_MP_Y_OFFS_CNT_SHD_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit MP_Y_OFFS_CNT:22; /**< \brief [23:2] Main Picture Y Offset Counter (r) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CIF_MI_MP_Y_OFFS_CNT_SHD_Bits;
+
+/** \brief Memory Interface Offset Counter Start Value For Main Picture Y, JPEG
+ * or RAW Data Register */
+typedef struct _Ifx_CIF_MI_MP_Y_OFFS_CNT_START_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit MP_Y_OFFS_CNT_START:22; /**< \brief [23:2] Main Picture Y Offset Counter Start (r) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CIF_MI_MP_Y_OFFS_CNT_START_Bits;
+
+/** \brief Memory Interface Size of main picture Y component, JPEG or RAW data
+ * Register */
+typedef struct _Ifx_CIF_MI_MP_Y_SIZE_INIT_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit MP_Y_SIZE_INIT:22; /**< \brief [23:2] Main Picture Y Size Init (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CIF_MI_MP_Y_SIZE_INIT_Bits;
+
+/** \brief Memory Interface Size Shadow Register of Main Picture Y
+ * Component,JPEG or RAW Data Register */
+typedef struct _Ifx_CIF_MI_MP_Y_SIZE_SHD_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit MP_Y_SIZE:22; /**< \brief [23:2] Main Picture Y Size (r) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CIF_MI_MP_Y_SIZE_SHD_Bits;
+
+/** \brief MI Raw Interrupt Status Register */
+typedef struct _Ifx_CIF_MI_RIS_Bits
+{
+ Ifx_Strict_32Bit MP_FRAME_END:1; /**< \brief [0:0] Main Picture Frame End (r) */
+ Ifx_Strict_32Bit reserved_1:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit MBLK_LINE:1; /**< \brief [2:2] Macro Block Line Interrupt (r) */
+ Ifx_Strict_32Bit FILL_MP_Y:1; /**< \brief [3:3] Fill Main Picture Y (r) */
+ Ifx_Strict_32Bit WRAP_MP_Y:1; /**< \brief [4:4] Wrap Main Picture Y (r) */
+ Ifx_Strict_32Bit WRAP_MP_CB:1; /**< \brief [5:5] Wrap Main Picture Cb (r) */
+ Ifx_Strict_32Bit WRAP_MP_CR:1; /**< \brief [6:6] Wrap Main Picture Cr (r) */
+ Ifx_Strict_32Bit reserved_7:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit BUS_ERROR:1; /**< \brief [10:10] Bus Error (r) */
+ Ifx_Strict_32Bit reserved_11:21; /**< \brief \internal Reserved */
+} Ifx_CIF_MI_RIS_Bits;
+
+/** \brief MI Status Register */
+typedef struct _Ifx_CIF_MI_STATUS_Bits
+{
+ Ifx_Strict_32Bit MP_Y_FIFO_FULL:1; /**< \brief [0:0] Main Picture Y FIFO Full (r) */
+ Ifx_Strict_32Bit MP_CB_FIFO_FULL:1; /**< \brief [1:1] Main Picture Cb FIFO Full (r) */
+ Ifx_Strict_32Bit MP_CR_FIFO_FULL:1; /**< \brief [2:2] Main Picture Cr FIFO Full (r) */
+ Ifx_Strict_32Bit reserved_3:5; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit BUS_WRITE_ERROR:1; /**< \brief [8:8] Bus Write Error (r) */
+ Ifx_Strict_32Bit reserved_9:23; /**< \brief \internal Reserved */
+} Ifx_CIF_MI_STATUS_Bits;
+
+/** \brief MI Status Clear Register */
+typedef struct _Ifx_CIF_MI_STATUS_CLR_Bits
+{
+ Ifx_Strict_32Bit MP_Y_FIFO_FULL:1; /**< \brief [0:0] Main Picture Y FIFO Full (w) */
+ Ifx_Strict_32Bit MP_CB_FIFO_FULL:1; /**< \brief [1:1] Main Picture Cb FIFO Full (w) */
+ Ifx_Strict_32Bit MP_CR_FIFO_FULL:1; /**< \brief [2:2] Main Picture Cr FIFO Full (w) */
+ Ifx_Strict_32Bit reserved_3:5; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit BUS_WRITE_ERROR:1; /**< \brief [8:8] Bus Write Error (w) */
+ Ifx_Strict_32Bit reserved_9:15; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit EP_1_FIFO_FULL:1; /**< \brief [24:24] Extra Path 1 FIFO Full (w) */
+ Ifx_Strict_32Bit EP_2_FIFO_FULL:1; /**< \brief [25:25] Extra Path 2 FIFO Full (w) */
+ Ifx_Strict_32Bit EP_3_FIFO_FULL:1; /**< \brief [26:26] Extra Path 3 FIFO Full (w) */
+ Ifx_Strict_32Bit EP_4_FIFO_FULL:1; /**< \brief [27:27] Extra Path 4 FIFO Full (w) */
+ Ifx_Strict_32Bit EP_5_FIFO_FULL:1; /**< \brief [28:28] Extra Path 5 FIFO Full (w) */
+ Ifx_Strict_32Bit reserved_29:3; /**< \brief \internal Reserved */
+} Ifx_CIF_MI_STATUS_CLR_Bits;
+
+/** \brief Memory Interface Base Address For Extra Path Data Buffer Register */
+typedef struct _Ifx_CIF_MIEP_CH_BASE_AD_INIT_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit EP_BASE_AD_INIT:30; /**< \brief [31:2] Extra Path Base Address Init (rw) */
+} Ifx_CIF_MIEP_CH_BASE_AD_INIT_Bits;
+
+/** \brief Memory Interface Base Address Shadow Register for Extra Path Buffer
+ * Register */
+typedef struct _Ifx_CIF_MIEP_CH_BASE_AD_SHD_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit EP_BASE_AD:30; /**< \brief [31:2] Extra Path Base Address (r) */
+} Ifx_CIF_MIEP_CH_BASE_AD_SHD_Bits;
+
+/** \brief Memory Interface Extra Path Control Register */
+typedef struct _Ifx_CIF_MIEP_CH_CTRL_Bits
+{
+ Ifx_Strict_32Bit EP_ENABLE:1; /**< \brief [0:0] Enables enable ep picture data path (rw) */
+ Ifx_Strict_32Bit reserved_1:6; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit BYTE_SWAP:1; /**< \brief [7:7] Byte Swap Enable (rw) */
+ Ifx_Strict_32Bit reserved_8:12; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit INIT_BASE_EN:1; /**< \brief [20:20] Init Base Address Enable (rw) */
+ Ifx_Strict_32Bit INIT_OFFSET_EN:1; /**< \brief [21:21] Init Offset Counter Enable (rw) */
+ Ifx_Strict_32Bit EP_WRITE_FORMAT:2; /**< \brief [23:22] Extra Path Write Format (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CIF_MIEP_CH_CTRL_Bits;
+
+/** \brief Memory Interface Extra Path Control Internal Shadow Register */
+typedef struct _Ifx_CIF_MIEP_CH_CTRL_SHD_Bits
+{
+ Ifx_Strict_32Bit EP_ENABLE_IN:1; /**< \brief [0:0] Extra Path In Enable (r) */
+ Ifx_Strict_32Bit reserved_1:15; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit EP_ENABLE_OUT:1; /**< \brief [16:16] Extra Path Out Enable (r) */
+ Ifx_Strict_32Bit reserved_17:15; /**< \brief \internal Reserved */
+} Ifx_CIF_MIEP_CH_CTRL_SHD_Bits;
+
+/** \brief Memory Interface Extra Path Control Register For Address Init And
+ * Skip Function Register */
+typedef struct _Ifx_CIF_MIEP_CH_INIT_Bits
+{
+ Ifx_Strict_32Bit reserved_0:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit MI_EP_SKIP:1; /**< \brief [2:2] Skip Picture (w) */
+ Ifx_Strict_32Bit reserved_3:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit MI_EP_CFG_UPD:1; /**< \brief [4:4] Forced Configuration Update (w) */
+ Ifx_Strict_32Bit reserved_5:27; /**< \brief \internal Reserved */
+} Ifx_CIF_MIEP_CH_INIT_Bits;
+
+/** \brief Memory Interface Fill Level Interrupt Offset Value For Extra Path
+ * Register */
+typedef struct _Ifx_CIF_MIEP_CH_IRQ_OFFS_INIT_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit EP_IRQ_OFFS_INIT:22; /**< \brief [23:2] Extra Path Y IRQ Offset Init (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CIF_MIEP_CH_IRQ_OFFS_INIT_Bits;
+
+/** \brief Memory Interface Shadow Register of Fill Level Interrupt Offset
+ * Value For Extra Path Register */
+typedef struct _Ifx_CIF_MIEP_CH_IRQ_OFFS_SHD_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit EP_IRQ_OFFS:22; /**< \brief [23:2] Extra Path IRQ Offset (r) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CIF_MIEP_CH_IRQ_OFFS_SHD_Bits;
+
+/** \brief Memory Interface Offset Counter Init Value For Extra Path Buffer
+ * Register */
+typedef struct _Ifx_CIF_MIEP_CH_OFFS_CNT_INIT_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit EP_OFFS_CNT_INIT:22; /**< \brief [23:2] Extra Path Offset Counter Init (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CIF_MIEP_CH_OFFS_CNT_INIT_Bits;
+
+/** \brief Memory Interface Current Offset Counter of Extra Path Buffer
+ * Register */
+typedef struct _Ifx_CIF_MIEP_CH_OFFS_CNT_SHD_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit EP_OFFS_CNT:22; /**< \brief [23:2] Extra Path Y Offset Counter (r) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CIF_MIEP_CH_OFFS_CNT_SHD_Bits;
+
+/** \brief Memory Interface Offset Counter Start Value For Extra Path Register */
+typedef struct _Ifx_CIF_MIEP_CH_OFFS_CNT_START_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit EP_OFFS_CNT_START:22; /**< \brief [23:2] Extra Path Offset Counter Start (r) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CIF_MIEP_CH_OFFS_CNT_START_Bits;
+
+/** \brief Memory Interface Size of Extra Path Data Buffer Register */
+typedef struct _Ifx_CIF_MIEP_CH_SIZE_INIT_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit EP_SIZE_INIT:22; /**< \brief [23:2] Extra Path Size Init (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CIF_MIEP_CH_SIZE_INIT_Bits;
+
+/** \brief Memory Interface Size Shadow Register of Extra Path Buffer Register */
+typedef struct _Ifx_CIF_MIEP_CH_SIZE_SHD_Bits
+{
+ Ifx_Strict_32Bit FIXED_TO_00:2; /**< \brief [1:0] Bits [1:0] are set to "00" (word aligned value). (r) */
+ Ifx_Strict_32Bit EP_SIZE:22; /**< \brief [23:2] Extra Path Size (r) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_CIF_MIEP_CH_SIZE_SHD_Bits;
+
+/** \brief MI Extra Path Interrupt Clear Register */
+typedef struct _Ifx_CIF_MIEP_ICR_Bits
+{
+ Ifx_Strict_32Bit FRAME_END_EP_1:1; /**< \brief [0:0] Extra Path 1 Frame End (w) */
+ Ifx_Strict_32Bit FILL_EP_1:1; /**< \brief [1:1] Fill Extra Path 1 (w) */
+ Ifx_Strict_32Bit WRAP_EP_1:1; /**< \brief [2:2] Wrap Extra Path 1 (w) */
+ Ifx_Strict_32Bit MBLK_LINE_EP_1:1; /**< \brief [3:3] Macro Block Line Interrupt Extra Path 1 (w) */
+ Ifx_Strict_32Bit FRAME_END_EP_2:1; /**< \brief [4:4] Extra Path 2 Frame End (w) */
+ Ifx_Strict_32Bit FILL_EP_2:1; /**< \brief [5:5] Fill Extra Path 2 (w) */
+ Ifx_Strict_32Bit WRAP_EP_2:1; /**< \brief [6:6] Wrap Extra Path 2 (w) */
+ Ifx_Strict_32Bit reserved_7:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit FRAME_END_EP_3:1; /**< \brief [8:8] Extra Path 3 Frame End (w) */
+ Ifx_Strict_32Bit FILL_EP_3:1; /**< \brief [9:9] Fill Extra Path 3 (w) */
+ Ifx_Strict_32Bit WRAP_EP_3:1; /**< \brief [10:10] Wrap Extra Path 3 (w) */
+ Ifx_Strict_32Bit MBLK_LINE_EP_3:1; /**< \brief [11:11] Macro Block Line Interrupt Extra Path 3 (w) */
+ Ifx_Strict_32Bit FRAME_END_EP_4:1; /**< \brief [12:12] Extra Path 4 Frame End (w) */
+ Ifx_Strict_32Bit FILL_EP_4:1; /**< \brief [13:13] Fill Extra Path 4 (w) */
+ Ifx_Strict_32Bit WRAP_EP_4:1; /**< \brief [14:14] Wrap Extra Path 4 (w) */
+ Ifx_Strict_32Bit MBLK_LINE_EP_4:1; /**< \brief [15:15] Macro Block Line Interrupt Extra Path 4 (w) */
+ Ifx_Strict_32Bit FRAME_END_EP_5:1; /**< \brief [16:16] Extra Path 5 Frame End (w) */
+ Ifx_Strict_32Bit FILL_EP_5:1; /**< \brief [17:17] Fill Extra Path 5 (w) */
+ Ifx_Strict_32Bit WRAP_EP_5:1; /**< \brief [18:18] Wrap Extra Path 5 (w) */
+ Ifx_Strict_32Bit MBLK_LINE_EP_5:1; /**< \brief [19:19] Macro Block Line Interrupt Extra Path 5 (w) */
+ Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_CIF_MIEP_ICR_Bits;
+
+/** \brief MI Extra Path Interrupt Mask ‘1’: interrupt active, ‘0’: interrupt
+ * masked */
+typedef struct _Ifx_CIF_MIEP_IMSC_Bits
+{
+ Ifx_Strict_32Bit FRAME_END_EP_1:1; /**< \brief [0:0] Extra Path 1 Frame End (rw) */
+ Ifx_Strict_32Bit FILL_EP_1:1; /**< \brief [1:1] Fill Extra Path 1 (rw) */
+ Ifx_Strict_32Bit WRAP_EP_1:1; /**< \brief [2:2] Wrap Extra Path 1 (rw) */
+ Ifx_Strict_32Bit MBLK_LINE_EP_1:1; /**< \brief [3:3] Macro Block Line Interrupt Extra Path 1 (rw) */
+ Ifx_Strict_32Bit FRAME_END_EP_2:1; /**< \brief [4:4] Extra Path 2 Frame End (rw) */
+ Ifx_Strict_32Bit FILL_EP_2:1; /**< \brief [5:5] Fill Extra Path 2 (rw) */
+ Ifx_Strict_32Bit WRAP_EP_2:1; /**< \brief [6:6] Wrap Extra Path 2 (rw) */
+ Ifx_Strict_32Bit MBLK_LINE_EP_2:1; /**< \brief [7:7] Macro Block Line Interrupt Extra Path 2 (rw) */
+ Ifx_Strict_32Bit FRAME_END_EP_3:1; /**< \brief [8:8] Extra Path 3 Frame End (rw) */
+ Ifx_Strict_32Bit FILL_EP_3:1; /**< \brief [9:9] Fill Extra Path 3 (rw) */
+ Ifx_Strict_32Bit WRAP_EP_3:1; /**< \brief [10:10] Wrap Extra Path 3 (rw) */
+ Ifx_Strict_32Bit MBLK_LINE_EP_3:1; /**< \brief [11:11] Macro Block Line Interrupt Extra Path 3 (rw) */
+ Ifx_Strict_32Bit FRAME_END_EP_4:1; /**< \brief [12:12] Extra Path 4 Frame End (rw) */
+ Ifx_Strict_32Bit FILL_EP_4:1; /**< \brief [13:13] Fill Extra Path 4 (rw) */
+ Ifx_Strict_32Bit WRAP_EP_4:1; /**< \brief [14:14] Wrap Extra Path 4 (rw) */
+ Ifx_Strict_32Bit MBLK_LINE_EP_4:1; /**< \brief [15:15] Macro Block Line Interrupt Extra Path 4 (rw) */
+ Ifx_Strict_32Bit FRAME_END_EP_5:1; /**< \brief [16:16] Extra Path 5 Frame End (rw) */
+ Ifx_Strict_32Bit FILL_EP_5:1; /**< \brief [17:17] Fill Extra Path 5 (rw) */
+ Ifx_Strict_32Bit WRAP_EP_5:1; /**< \brief [18:18] Wrap Extra Path 5 (rw) */
+ Ifx_Strict_32Bit MBLK_LINE_EP_5:1; /**< \brief [19:19] Macro Block Line Interrupt Extra Path 5 (rw) */
+ Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_CIF_MIEP_IMSC_Bits;
+
+/** \brief MI Extra Path Interrupt Set Register */
+typedef struct _Ifx_CIF_MIEP_ISR_Bits
+{
+ Ifx_Strict_32Bit FRAME_END_EP_1:1; /**< \brief [0:0] Extra Path 1 Frame End (w) */
+ Ifx_Strict_32Bit FILL_EP_1:1; /**< \brief [1:1] Fill Extra Path 1 (w) */
+ Ifx_Strict_32Bit WRAP_EP_1:1; /**< \brief [2:2] Wrap Extra Path 1 (w) */
+ Ifx_Strict_32Bit MBLK_LINE_EP_1:1; /**< \brief [3:3] Macro Block Line Interrupt Extra Path 1 (w) */
+ Ifx_Strict_32Bit FRAME_END_EP_2:1; /**< \brief [4:4] Extra Path 2 Frame End (w) */
+ Ifx_Strict_32Bit FILL_EP_2:1; /**< \brief [5:5] Fill Extra Path 2 (w) */
+ Ifx_Strict_32Bit WRAP_EP_2:1; /**< \brief [6:6] Wrap Extra Path 2 (w) */
+ Ifx_Strict_32Bit MBLK_LINE_EP_2:1; /**< \brief [7:7] Macro Block Line Interrupt Extra Path 2 (w) */
+ Ifx_Strict_32Bit FRAME_END_EP_3:1; /**< \brief [8:8] Extra Path 3 Frame End (w) */
+ Ifx_Strict_32Bit FILL_EP_3:1; /**< \brief [9:9] Fill Extra Path 3 (w) */
+ Ifx_Strict_32Bit WRAP_EP_3:1; /**< \brief [10:10] Wrap Extra Path 3 (w) */
+ Ifx_Strict_32Bit MBLK_LINE_EP_3:1; /**< \brief [11:11] Macro Block Line Interrupt Extra Path 3 (w) */
+ Ifx_Strict_32Bit FRAME_END_EP_4:1; /**< \brief [12:12] Extra Path 4 Frame End (w) */
+ Ifx_Strict_32Bit FILL_EP_4:1; /**< \brief [13:13] Fill Extra Path 4 (w) */
+ Ifx_Strict_32Bit WRAP_EP_4:1; /**< \brief [14:14] Wrap Extra Path 4 (w) */
+ Ifx_Strict_32Bit MBLK_LINE_EP_4:1; /**< \brief [15:15] Macro Block Line Interrupt Extra Path 4 (w) */
+ Ifx_Strict_32Bit FRAME_END_EP_5:1; /**< \brief [16:16] Extra Path 5 Frame End (w) */
+ Ifx_Strict_32Bit FILL_EP_5:1; /**< \brief [17:17] Fill Extra Path 5 (w) */
+ Ifx_Strict_32Bit WRAP_EP_5:1; /**< \brief [18:18] Wrap Extra Path 5 (w) */
+ Ifx_Strict_32Bit MBLK_LINE_EP_5:1; /**< \brief [19:19] Macro Block Line Interrupt Extra Path 5 (w) */
+ Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_CIF_MIEP_ISR_Bits;
+
+/** \brief MI Extra Path Masked Interrupt Status Register */
+typedef struct _Ifx_CIF_MIEP_MIS_Bits
+{
+ Ifx_Strict_32Bit FRAME_END_EP_1:1; /**< \brief [0:0] Extra Path 1 Frame End (r) */
+ Ifx_Strict_32Bit FILL_EP_1:1; /**< \brief [1:1] Fill Extra Path 1 (r) */
+ Ifx_Strict_32Bit WRAP_EP_1:1; /**< \brief [2:2] Wrap Extra Path 1 (r) */
+ Ifx_Strict_32Bit MBLK_LINE_EP_1:1; /**< \brief [3:3] Macro Block Line Interrupt Extra Path 1 (r) */
+ Ifx_Strict_32Bit FRAME_END_EP_2:1; /**< \brief [4:4] Extra Path 2 Frame End (r) */
+ Ifx_Strict_32Bit FILL_EP_2:1; /**< \brief [5:5] Fill Extra Path 2 (r) */
+ Ifx_Strict_32Bit WRAP_EP_2:1; /**< \brief [6:6] Wrap Extra Path 2 (r) */
+ Ifx_Strict_32Bit MBLK_LINE_EP_2:1; /**< \brief [7:7] Macro Block Line Interrupt Extra Path 2 (r) */
+ Ifx_Strict_32Bit FRAME_END_EP_3:1; /**< \brief [8:8] Extra Path 3 Frame End (r) */
+ Ifx_Strict_32Bit FILL_EP_3:1; /**< \brief [9:9] Fill Extra Path 3 (r) */
+ Ifx_Strict_32Bit WRAP_EP_3:1; /**< \brief [10:10] Wrap Extra Path 3 (r) */
+ Ifx_Strict_32Bit MBLK_LINE_EP_3:1; /**< \brief [11:11] Macro Block Line Interrupt Extra Path 3 (r) */
+ Ifx_Strict_32Bit FRAME_END_EP_4:1; /**< \brief [12:12] Extra Path 4 Frame End (r) */
+ Ifx_Strict_32Bit FILL_EP_4:1; /**< \brief [13:13] Fill Extra Path 4 (r) */
+ Ifx_Strict_32Bit WRAP_EP_4:1; /**< \brief [14:14] Wrap Extra Path 4 (r) */
+ Ifx_Strict_32Bit MBLK_LINE_EP_4:1; /**< \brief [15:15] Macro Block Line Interrupt Extra Path 4 (r) */
+ Ifx_Strict_32Bit FRAME_END_EP_5:1; /**< \brief [16:16] Extra Path 5 Frame End (r) */
+ Ifx_Strict_32Bit FILL_EP_5:1; /**< \brief [17:17] Fill Extra Path 5 (r) */
+ Ifx_Strict_32Bit WRAP_EP_5:1; /**< \brief [18:18] Wrap Extra Path 5 (r) */
+ Ifx_Strict_32Bit MBLK_LINE_EP_5:1; /**< \brief [19:19] Macro Block Line Interrupt Extra Path 5 (r) */
+ Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_CIF_MIEP_MIS_Bits;
+
+/** \brief MI Extra Path Raw Interrupt Status Register */
+typedef struct _Ifx_CIF_MIEP_RIS_Bits
+{
+ Ifx_Strict_32Bit FRAME_END_EP_1:1; /**< \brief [0:0] Extra Path 1 Frame End (r) */
+ Ifx_Strict_32Bit FILL_EP_1:1; /**< \brief [1:1] Fill Extra Path 1 (r) */
+ Ifx_Strict_32Bit WRAP_EP_1:1; /**< \brief [2:2] Wrap Extra Path 1 (r) */
+ Ifx_Strict_32Bit MBLK_LINE_EP_1:1; /**< \brief [3:3] Macro Block Line Interrupt Extra Path 1 (r) */
+ Ifx_Strict_32Bit FRAME_END_EP_2:1; /**< \brief [4:4] Extra Path 2 Frame End (r) */
+ Ifx_Strict_32Bit FILL_EP_2:1; /**< \brief [5:5] Fill Extra Path 2 (r) */
+ Ifx_Strict_32Bit WRAP_EP_2:1; /**< \brief [6:6] Wrap Extra Path 2 (r) */
+ Ifx_Strict_32Bit MBLK_LINE_EP_2:1; /**< \brief [7:7] Macro Block Line Interrupt Extra Path 2 (r) */
+ Ifx_Strict_32Bit FRAME_END_EP_3:1; /**< \brief [8:8] Extra Path 3 Frame End (r) */
+ Ifx_Strict_32Bit FILL_EP_3:1; /**< \brief [9:9] Fill Extra Path 3 (r) */
+ Ifx_Strict_32Bit WRAP_EP_3:1; /**< \brief [10:10] Wrap Extra Path 3 (r) */
+ Ifx_Strict_32Bit MBLK_LINE_EP_3:1; /**< \brief [11:11] Macro Block Line Interrupt Extra Path 3 (r) */
+ Ifx_Strict_32Bit FRAME_END_EP_4:1; /**< \brief [12:12] Extra Path 4 Frame End (r) */
+ Ifx_Strict_32Bit FILL_EP_4:1; /**< \brief [13:13] Fill Extra Path 4 (r) */
+ Ifx_Strict_32Bit WRAP_EP_4:1; /**< \brief [14:14] Wrap Extra Path 4 (r) */
+ Ifx_Strict_32Bit MBLK_LINE_EP_4:1; /**< \brief [15:15] Macro Block Line Interrupt Extra Path 4 (r) */
+ Ifx_Strict_32Bit FRAME_END_EP_5:1; /**< \brief [16:16] Extra Path 5 Frame End (r) */
+ Ifx_Strict_32Bit FILL_EP_5:1; /**< \brief [17:17] Fill Extra Path 5 (r) */
+ Ifx_Strict_32Bit WRAP_EP_5:1; /**< \brief [18:18] Wrap Extra Path 5 (r) */
+ Ifx_Strict_32Bit MBLK_LINE_EP_5:1; /**< \brief [19:19] Macro Block Line Interrupt Extra Path 5 (r) */
+ Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_CIF_MIEP_RIS_Bits;
+
+/** \brief Extra Path Error Register */
+typedef struct _Ifx_CIF_MIEP_STA_ERR_Bits
+{
+ Ifx_Strict_32Bit reserved_0:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit EP_1_IC_SIZE_ERR:1; /**< \brief [1:1] Size error is generated in Extra Path 1 image cropping submodule (r) */
+ Ifx_Strict_32Bit EP_2_IC_SIZE_ERR:1; /**< \brief [2:2] Size error is generated in Extra Path 2 image cropping submodule (r) */
+ Ifx_Strict_32Bit EP_3_IC_SIZE_ERR:1; /**< \brief [3:3] Size error is generated in Extra Path 3 image cropping submodule (r) */
+ Ifx_Strict_32Bit EP_4_IC_SIZE_ERR:1; /**< \brief [4:4] Size error is generated in Extra Path 4 image cropping submodule (r) */
+ Ifx_Strict_32Bit EP_5_IC_SIZE_ERR:1; /**< \brief [5:5] Size error is generated in Extra Path 5 image cropping submodule (r) */
+ Ifx_Strict_32Bit reserved_6:11; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit EP_1_FIFO_FULL:1; /**< \brief [17:17] Extra Path 1 FIFO Full (r) */
+ Ifx_Strict_32Bit EP_2_FIFO_FULL:1; /**< \brief [18:18] Extra Path 2 FIFO Full (r) */
+ Ifx_Strict_32Bit EP_3_FIFO_FULL:1; /**< \brief [19:19] Extra Path 3 FIFO Full (r) */
+ Ifx_Strict_32Bit EP_4_FIFO_FULL:1; /**< \brief [20:20] Extra Path 4 FIFO Full (r) */
+ Ifx_Strict_32Bit EP_5_FIFO_FULL:1; /**< \brief [21:21] Extra Path 5 FIFO Full (r) */
+ Ifx_Strict_32Bit reserved_22:10; /**< \brief \internal Reserved */
+} Ifx_CIF_MIEP_STA_ERR_Bits;
+
+/** \brief Extra Path Error Clear Register */
+typedef struct _Ifx_CIF_MIEP_STA_ERR_CLR_Bits
+{
+ Ifx_Strict_32Bit reserved_0:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit EP_1_IC_SIZE_ERR_CLR:1; /**< \brief [1:1] Size error is cleared (w) */
+ Ifx_Strict_32Bit EP_2_IC_SIZE_ERR_CLR:1; /**< \brief [2:2] Size error is cleared (w) */
+ Ifx_Strict_32Bit EP_3_IC_SIZE_ERR_CLR:1; /**< \brief [3:3] Size error is cleared (w) */
+ Ifx_Strict_32Bit EP_4_IC_SIZE_ERR_CLR:1; /**< \brief [4:4] Size error is cleared (w) */
+ Ifx_Strict_32Bit EP_5_IC_SIZE_ERR_CLR:1; /**< \brief [5:5] Size error is cleared (w) */
+ Ifx_Strict_32Bit reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_CIF_MIEP_STA_ERR_CLR_Bits;
+
+/** \brief Watchdog Control Register */
+typedef struct _Ifx_CIF_WD_CTRL_Bits
+{
+ Ifx_Strict_32Bit WD_EN:1; /**< \brief [0:0] Enable Security Watchdog (rw) */
+ Ifx_Strict_32Bit RST_H_CNT:1; /**< \brief [1:1] Reset Horizontal Counter (w) */
+ Ifx_Strict_32Bit RST_V_CNT:1; /**< \brief [2:2] Reset Vertical Counter (w) */
+ Ifx_Strict_32Bit RST_PD_CNT:1; /**< \brief [3:3] Reset Predivider Counter (w) */
+ Ifx_Strict_32Bit reserved_4:12; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit WD_PREDIV:16; /**< \brief [31:16] Watchdog Counter Predivider (rw) */
+} Ifx_CIF_WD_CTRL_Bits;
+
+/** \brief Watchdog Horizontal Timeout Register */
+typedef struct _Ifx_CIF_WD_H_TIMEOUT_Bits
+{
+ Ifx_Strict_32Bit WD_HSE_TO:16; /**< \brief [15:0] Watchdog Horizontal Start End Timeout (rw) */
+ Ifx_Strict_32Bit WD_HES_TO:16; /**< \brief [31:16] Watchdog Horizontal End Start Timeout (rw) */
+} Ifx_CIF_WD_H_TIMEOUT_Bits;
+
+/** \brief Watchdog Interrupt Clear Register */
+typedef struct _Ifx_CIF_WD_ICR_Bits
+{
+ Ifx_Strict_32Bit ICR_WD_HSE_TO:1; /**< \brief [0:0] Horizontal Start End Timeout (w) */
+ Ifx_Strict_32Bit ICR_WD_HES_TO:1; /**< \brief [1:1] Horizontal End Start Timeout (w) */
+ Ifx_Strict_32Bit ICR_WD_VSE_TO:1; /**< \brief [2:2] Vertical Start End Timeout (w) */
+ Ifx_Strict_32Bit ICR_WD_VES_TO:1; /**< \brief [3:3] Vertical End Start Timeout (w) */
+ Ifx_Strict_32Bit reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_CIF_WD_ICR_Bits;
+
+/** \brief Watchdog Interrupt Mask Register */
+typedef struct _Ifx_CIF_WD_IMSC_Bits
+{
+ Ifx_Strict_32Bit IMSC_WD_HSE_TO:1; /**< \brief [0:0] Horizontal Start End Timeout (rw) */
+ Ifx_Strict_32Bit IMSC_WD_HES_TO:1; /**< \brief [1:1] Horizontal End Start Timeout (rw) */
+ Ifx_Strict_32Bit IMSC_WD_VSE_TO:1; /**< \brief [2:2] Vertical Start End Timeout (rw) */
+ Ifx_Strict_32Bit IMSC_WD_VES_TO:1; /**< \brief [3:3] Vertical End Start Timeout (rw) */
+ Ifx_Strict_32Bit reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_CIF_WD_IMSC_Bits;
+
+/** \brief Watchdog Interrupt Set Register */
+typedef struct _Ifx_CIF_WD_ISR_Bits
+{
+ Ifx_Strict_32Bit ISR_WD_HSE_TO:1; /**< \brief [0:0] Horizontal Start End Timeout (w) */
+ Ifx_Strict_32Bit ISR_WD_HES_TO:1; /**< \brief [1:1] Horizontal End Start Timeout (w) */
+ Ifx_Strict_32Bit ISR_WD_VSE_TO:1; /**< \brief [2:2] Vertical Start End Timeout (w) */
+ Ifx_Strict_32Bit ISR_WD_VES_TO:1; /**< \brief [3:3] Vertical End Start Timeout (w) */
+ Ifx_Strict_32Bit reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_CIF_WD_ISR_Bits;
+
+/** \brief Watchdog Masked Interrupt Status Register */
+typedef struct _Ifx_CIF_WD_MIS_Bits
+{
+ Ifx_Strict_32Bit MIS_WD_HSE_TO:1; /**< \brief [0:0] Horizontal Start End Timeout (r) */
+ Ifx_Strict_32Bit MIS_WD_HES_TO:1; /**< \brief [1:1] Horizontal End Start Timeout (r) */
+ Ifx_Strict_32Bit MIS_WD_VSE_TO:1; /**< \brief [2:2] Vertical Start End Timeout (r) */
+ Ifx_Strict_32Bit MIS_WD_VES_TO:1; /**< \brief [3:3] Vertical End Start Timeout (r) */
+ Ifx_Strict_32Bit reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_CIF_WD_MIS_Bits;
+
+/** \brief Watchdog Raw Interrupt Status Register */
+typedef struct _Ifx_CIF_WD_RIS_Bits
+{
+ Ifx_Strict_32Bit RIS_WD_HSE_TO:1; /**< \brief [0:0] Horizontal Start End Timeout (r) */
+ Ifx_Strict_32Bit RIS_WD_HES_TO:1; /**< \brief [1:1] Horizontal End Start Timeout (r) */
+ Ifx_Strict_32Bit RIS_WD_VSE_TO:1; /**< \brief [2:2] Vertical Start End Timeout (r) */
+ Ifx_Strict_32Bit RIS_WD_VES_TO:1; /**< \brief [3:3] Vertical End Start Timeout (r) */
+ Ifx_Strict_32Bit reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_CIF_WD_RIS_Bits;
+
+/** \brief Watchdog Vertical Timeout Register */
+typedef struct _Ifx_CIF_WD_V_TIMEOUT_Bits
+{
+ Ifx_Strict_32Bit WD_VSE_TO:16; /**< \brief [15:0] Watchdog Vertical Start End Timeout (rw) */
+ Ifx_Strict_32Bit WD_VES_TO:16; /**< \brief [31:16] Watchdog Vertical End Start Timeout (rw) */
+} Ifx_CIF_WD_V_TIMEOUT_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Cif_union
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_BBB_ACCEN0_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_BBB_ACCEN0;
+
+/** \brief Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_BBB_ACCEN1_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_BBB_ACCEN1;
+
+/** \brief Clock Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_BBB_CLC_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_BBB_CLC;
+
+/** \brief General Purpose Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_BBB_GPCTL_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_BBB_GPCTL;
+
+/** \brief Kernel Reset Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_BBB_KRST0_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_BBB_KRST0;
+
+/** \brief Kernel Reset Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_BBB_KRST1_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_BBB_KRST1;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_BBB_KRSTCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_BBB_KRSTCLR;
+
+/** \brief Module Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_BBB_MODID_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_BBB_MODID;
+
+/** \brief Clock Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_CCL_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_CCL;
+
+/** \brief Debug Path Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_DP_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_DP_CTRL;
+
+/** \brief Debug Path Frame/Line Counter Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_DP_FLC_STAT_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_DP_FLC_STAT;
+
+/** \brief Debug Path Predivider Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_DP_PDIV_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_DP_PDIV_CTRL;
+
+/** \brief Debug Path Predivider Counter Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_DP_PDIV_STAT_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_DP_PDIV_STAT;
+
+/** \brief Debug Path Timestamp Counter Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_DP_TSC_STAT_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_DP_TSC_STAT;
+
+/** \brief Debug Path User Defined Symbol Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_DP_UDS_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_DP_UDS;
+
+/** \brief CIF Data Path Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_DPCL_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_DPCL;
+
+/** \brief Extra Path Image Cropping Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_EP_IC_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_EP_IC_CTRL;
+
+/** \brief Extra Path Image Cropping Camera Displacement Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_EP_IC_DISPLACE_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_EP_IC_DISPLACE;
+
+/** \brief Extra Path Image Cropping Horizontal Offset of Output Window
+ * Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_EP_IC_H_OFFS_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_EP_IC_H_OFFS;
+
+/** \brief Extra Path Image Current Horizontal Offset Of Output Window Shadow
+ * Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_EP_IC_H_OFFS_SHD_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_EP_IC_H_OFFS_SHD;
+
+/** \brief Extra Path Image Cropping Output Horizontal Picture Size Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_EP_IC_H_SIZE_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_EP_IC_H_SIZE;
+
+/** \brief Extra Path Image Current Output Horizontal Picture Size Shadow
+ * Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_EP_IC_H_SIZE_SHD_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_EP_IC_H_SIZE_SHD;
+
+/** \brief Extra Path Image Cropping Maximum Horizontal Displacement Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_EP_IC_MAX_DX_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_EP_IC_MAX_DX;
+
+/** \brief Extra Path Image Cropping Maximum Vertical Displacement Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_EP_IC_MAX_DY_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_EP_IC_MAX_DY;
+
+/** \brief Extra Path Image Cropping Recenter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_EP_IC_RECENTER_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_EP_IC_RECENTER;
+
+/** \brief Extra Path Image Cropping Vertical Offset Of Output Window Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_EP_IC_V_OFFS_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_EP_IC_V_OFFS;
+
+/** \brief Extra Path Image Current Vertical Offset Of Output Window Shadow
+ * Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_EP_IC_V_OFFS_SHD_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_EP_IC_V_OFFS_SHD;
+
+/** \brief Extra Path Image Cropping Output Vertical Picture Size Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_EP_IC_V_SIZE_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_EP_IC_V_SIZE;
+
+/** \brief Extra Path Image Current Output Vertical Picture Size Shadow
+ * Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_EP_IC_V_SIZE_SHD_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_EP_IC_V_SIZE_SHD;
+
+/** \brief CIF Internal Clock Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ICCL_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ICCL;
+
+/** \brief CIF Revision Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ID;
+
+/** \brief CIF Internal Reset Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_IRCL_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_IRCL;
+
+/** \brief ISP Acquisition Horizontal Offset Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISP_ACQ_H_OFFS_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISP_ACQ_H_OFFS;
+
+/** \brief ISP Acquisition Horizontal Size Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISP_ACQ_H_SIZE_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISP_ACQ_H_SIZE;
+
+/** \brief ISP Acquisition Number of Frames Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISP_ACQ_NR_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISP_ACQ_NR_FRAMES;
+
+/** \brief ISP Acquisition Properties Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISP_ACQ_PROP_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISP_ACQ_PROP;
+
+/** \brief ISP Acquistion Vertical Offset Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISP_ACQ_V_OFFS_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISP_ACQ_V_OFFS;
+
+/** \brief ISP Acquisition Vertical Size Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISP_ACQ_V_SIZE_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISP_ACQ_V_SIZE;
+
+/** \brief ISP Global Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISP_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISP_CTRL;
+
+/** \brief ISP Error Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISP_ERR_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISP_ERR;
+
+/** \brief ISP Error Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISP_ERR_CLR_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISP_ERR_CLR;
+
+/** \brief ISP Shadow Flags Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISP_FLAGS_SHD_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISP_FLAGS_SHD;
+
+/** \brief ISP Frame Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISP_FRAME_COUNT_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISP_FRAME_COUNT;
+
+/** \brief ISP Interrupt Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISP_ICR_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISP_ICR;
+
+/** \brief ISP Interrupt Mask Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISP_IMSC_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISP_IMSC;
+
+/** \brief ISP Interrupt Set Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISP_ISR_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISP_ISR;
+
+/** \brief ISP Masked Interrupt Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISP_MIS_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISP_MIS;
+
+/** \brief ISP Output Window Horizontal Offset Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISP_OUT_H_OFFS_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISP_OUT_H_OFFS;
+
+/** \brief ISP Output Window Horizontal Offset Shadow Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISP_OUT_H_OFFS_SHD_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISP_OUT_H_OFFS_SHD;
+
+/** \brief ISP Output Horizontal Picture Size Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISP_OUT_H_SIZE_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISP_OUT_H_SIZE;
+
+/** \brief ISP Output Horizontal Picture Size Shadow Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISP_OUT_H_SIZE_SHD_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISP_OUT_H_SIZE_SHD;
+
+/** \brief ISP Output Window Vertical Offset Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISP_OUT_V_OFFS_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISP_OUT_V_OFFS;
+
+/** \brief ISP Output Window Vertical Offset Shadow Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISP_OUT_V_OFFS_SHD_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISP_OUT_V_OFFS_SHD;
+
+/** \brief ISP Output Vertical Picture Size Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISP_OUT_V_SIZE_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISP_OUT_V_SIZE;
+
+/** \brief ISP Output Vertical Picture Size Shadow Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISP_OUT_V_SIZE_SHD_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISP_OUT_V_SIZE_SHD;
+
+/** \brief ISP Raw Interrupt Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISP_RIS_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISP_RIS;
+
+/** \brief ISP Image Stabilization Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISPIS_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISPIS_CTRL;
+
+/** \brief ISP Image Stabilization Camera Displacement Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISPIS_DISPLACE_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISPIS_DISPLACE;
+
+/** \brief ISP Image Stabilization Horizontal Offset Of Output Window Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISPIS_H_OFFS_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISPIS_H_OFFS;
+
+/** \brief SP Image Current Horizontal Offset Of Output Window Shadow Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISPIS_H_OFFS_SHD_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISPIS_H_OFFS_SHD;
+
+/** \brief ISP Image Stabilization Output Horizontal Picture Size Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISPIS_H_SIZE_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISPIS_H_SIZE;
+
+/** \brief ISP Image Current Output Horizontal Picture Size Shadow Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISPIS_H_SIZE_SHD_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISPIS_H_SIZE_SHD;
+
+/** \brief ISP Image Stabilization Maximum Horizontal Displacement Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISPIS_MAX_DX_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISPIS_MAX_DX;
+
+/** \brief ISP Image Stabilization Maximum Vertical Displacement Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISPIS_MAX_DY_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISPIS_MAX_DY;
+
+/** \brief ISP Image Stabilization Recenter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISPIS_RECENTER_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISPIS_RECENTER;
+
+/** \brief ISP Image Stabilization Vertical Offset Of Output Window Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISPIS_V_OFFS_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISPIS_V_OFFS;
+
+/** \brief ISP Image Current Vertical Offset Of Output Window Shadow Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISPIS_V_OFFS_SHD_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISPIS_V_OFFS_SHD;
+
+/** \brief ISP Image Stabilization Output Vertical Picture Size Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISPIS_V_SIZE_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISPIS_V_SIZE;
+
+/** \brief ISP Image Current Output Vertical Picture Size Shadow Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_ISPIS_V_SIZE_SHD_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_ISPIS_V_SIZE_SHD;
+
+/** \brief JPE Huffman Table Selector For AC Values Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_AC_TABLE_SELECT_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_AC_TABLE_SELECT;
+
+/** \brief JPE Cb/Cr Value Scaling Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_CBCR_SCALE_EN_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_CBCR_SCALE_EN;
+
+/** \brief JPE Huffman Table Selector For DC Values Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_DC_TABLE_SELECT_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_DC_TABLE_SELECT;
+
+/** \brief JPE Debug Information Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_DEBUG_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_DEBUG;
+
+/** \brief JPEG Codec Horizontal Image Size For Encoding Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_ENC_HSIZE_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_ENC_HSIZE;
+
+/** \brief JPEG Codec Vertical Image Size For Encoding Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_ENC_VSIZE_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_ENC_VSIZE;
+
+/** \brief JPE Start Command To Start JFIF Stream Encoding Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_ENCODE_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_ENCODE;
+
+/** \brief JPE Encode Mode Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_ENCODE_MODE_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_ENCODE_MODE;
+
+/** \brief JPE Encoder Status Flag Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_ENCODER_BUSY_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_ENCODER_BUSY;
+
+/** \brief JPE Error Interrupt Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_ERROR_ICR_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_ERROR_ICR;
+
+/** \brief JPE Error Interrupt Mask Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_ERROR_IMR_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_ERROR_IMR;
+
+/** \brief JPE Error Interrupt Set Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_ERROR_ISR_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_ERROR_ISR;
+
+/** \brief JPE Error Masked Interrupt Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_ERROR_MIS_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_ERROR_MIS;
+
+/** \brief JPE Error Raw Interrupt Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_ERROR_RIS_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_ERROR_RIS;
+
+/** \brief JPE Command To Start Stream Header Generation Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_GEN_HEADER_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_GEN_HEADER;
+
+/** \brief JPE Header Mode Definition Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_HEADER_MODE_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_HEADER_MODE;
+
+/** \brief JPE Automatic Configuration Update Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_INIT_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_INIT;
+
+/** \brief JPEG Picture Encoding Format Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_PIC_FORMAT_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_PIC_FORMAT;
+
+/** \brief JPE Restart Marker Insertion Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_RESTART_INTERVAL_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_RESTART_INTERVAL;
+
+/** \brief JPEG Status Interrupt Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_STATUS_ICR_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_STATUS_ICR;
+
+/** \brief JPEG Status Interrupt Mask Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_STATUS_IMR_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_STATUS_IMR;
+
+/** \brief JPEG Status Interrupt Set Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_STATUS_ISR_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_STATUS_ISR;
+
+/** \brief JPEG Status Masked Interrupt Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_STATUS_MIS_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_STATUS_MIS;
+
+/** \brief JPEG Status Raw Interrupt Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_STATUS_RIS_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_STATUS_RIS;
+
+/** \brief JPE Table Programming Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_TABLE_DATA_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_TABLE_DATA;
+
+/** \brief JPE Header Generation Debug Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_TABLE_FLUSH_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_TABLE_FLUSH;
+
+/** \brief JPE Table Programming Select Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_TABLE_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_TABLE_ID;
+
+/** \brief JPE Huffman AC Table 0 Length Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_TAC0_LEN_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_TAC0_LEN;
+
+/** \brief JPE Huffman AC Table 1 Length Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_TAC1_LEN_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_TAC1_LEN;
+
+/** \brief JPE Huffman DC Table 0 Length Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_TDC0_LEN_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_TDC0_LEN;
+
+/** \brief JPE Huffman DC Table 1 Length Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_TDC1_LEN_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_TDC1_LEN;
+
+/** \brief Q- table Selector 1, Quant. Table For U Component */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_TQ_U_SELECT_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_TQ_U_SELECT;
+
+/** \brief Q- table Selector 2 Quant Table For V Component */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_TQ_V_SELECT_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_TQ_V_SELECT;
+
+/** \brief Q- table Selector 0 Quant Table For Y Component */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_TQ_Y_SELECT_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_TQ_Y_SELECT;
+
+/** \brief JPE Y Value Scaling Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_JPE_Y_SCALE_EN_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_JPE_Y_SCALE_EN;
+
+/** \brief Linear Downscaler Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_LDS_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_LDS_CTRL;
+
+/** \brief Linear Downscaler Factor Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_LDS_FAC_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_LDS_FAC;
+
+/** \brief Memory Interface Counter Value of JPEG or RAW Data Bytes Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_BYTE_CNT_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_BYTE_CNT;
+
+/** \brief Memory Interface Global Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_CTRL;
+
+/** \brief Memory Interface Global Control Internal Shadow Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_CTRL_SHD_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_CTRL_SHD;
+
+/** \brief MI Interrupt Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_ICR_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_ICR;
+
+/** \brief MI Interrupt Mask ‘1’ interrupt active ‘0’ interrupt masked */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_IMSC_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_IMSC;
+
+/** \brief Memory Interface Control Register For Address Init And Skip Function
+ * Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_INIT_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_INIT;
+
+/** \brief MI Interrupt Set Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_ISR_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_ISR;
+
+/** \brief MI Masked Interrupt Status Registe */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_MIS_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_MIS;
+
+/** \brief Memory Interface Base Address For Main Picture Cb Component Ring
+ * Buffer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_MP_CB_BASE_AD_INIT_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_MP_CB_BASE_AD_INIT;
+
+/** \brief Memory Interface Base Address Shadow Register For Main Picture Cb
+ * Component Ring Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_MP_CB_BASE_AD_SHD_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_MP_CB_BASE_AD_SHD;
+
+/** \brief Memory Interface Offset Counter Init Value For Main Picture Cb
+ * Component Ring Buffer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_MP_CB_OFFS_CNT_INIT_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_MP_CB_OFFS_CNT_INIT;
+
+/** \brief Memory Interface Current Offset Counter Of Main Picture Cb Component
+ * Ring Buffer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_MP_CB_OFFS_CNT_SHD_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_MP_CB_OFFS_CNT_SHD;
+
+/** \brief Memory Interface Offset Counter Start Value For Main Picture Cb
+ * Component Ring Buffer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_MP_CB_OFFS_CNT_START_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_MP_CB_OFFS_CNT_START;
+
+/** \brief Memory Interface Size Of Main Picture Cb Component Ring Buffer
+ * Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_MP_CB_SIZE_INIT_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_MP_CB_SIZE_INIT;
+
+/** \brief Memory Interface Size Shadow Register Of Main Picture Cb Component
+ * Ring Buffer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_MP_CB_SIZE_SHD_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_MP_CB_SIZE_SHD;
+
+/** \brief Memory Interface Base Address For Main Picture Cr Component Ring
+ * Buffer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_MP_CR_BASE_AD_INIT_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_MP_CR_BASE_AD_INIT;
+
+/** \brief Memory Interface Base Address Shadow Register For Main Picture Cr
+ * Component Ring Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_MP_CR_BASE_AD_SHD_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_MP_CR_BASE_AD_SHD;
+
+/** \brief Memory Interface Offset Counter Init value For Main Picture Cr
+ * Component Ring Buffer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_MP_CR_OFFS_CNT_INIT_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_MP_CR_OFFS_CNT_INIT;
+
+/** \brief Memory Interface Current Offset Counter Of Main Picture Cr Component
+ * Ring Buffer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_MP_CR_OFFS_CNT_SHD_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_MP_CR_OFFS_CNT_SHD;
+
+/** \brief Memory Interface Offset Counter Start Value For Main Picture Cr
+ * Component Ring Buffer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_MP_CR_OFFS_CNT_START_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_MP_CR_OFFS_CNT_START;
+
+/** \brief Memory Interface Size Of Main Picture Cr Component Ring Buffer
+ * Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_MP_CR_SIZE_INIT_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_MP_CR_SIZE_INIT;
+
+/** \brief Memory Interface Size Shadow Register Of Main Picture Cr Component
+ * Ring Buffer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_MP_CR_SIZE_SHD_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_MP_CR_SIZE_SHD;
+
+/** \brief Memory Interface Base Address For Main Picture Y Component, JPEG or
+ * RAW Data Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_MP_Y_BASE_AD_INIT_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_MP_Y_BASE_AD_INIT;
+
+/** \brief Memory Interface Base Address Shadow Register For Main Picture Y
+ * Component, JPEG Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_MP_Y_BASE_AD_SHD_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_MP_Y_BASE_AD_SHD;
+
+/** \brief Memory Interface Fill Level Interrupt Offset Value For Main Picture
+ * Y, JPEG or RAW Data Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_MP_Y_IRQ_OFFS_INIT_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_MP_Y_IRQ_OFFS_INIT;
+
+/** \brief Memory Interface Shadow Register of Fill Level Interrupt Offset
+ * Value For Main Picture Y Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_MP_Y_IRQ_OFFS_SHD_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_MP_Y_IRQ_OFFS_SHD;
+
+/** \brief Memory Interface Offset Counter Init Value For Main Picture Y, JPEG
+ * or RAW Data Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_MP_Y_OFFS_CNT_INIT_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_MP_Y_OFFS_CNT_INIT;
+
+/** \brief Memory Interface Current Offset Counter of Main Picture Y Component
+ * JPEG or RAW Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_MP_Y_OFFS_CNT_SHD_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_MP_Y_OFFS_CNT_SHD;
+
+/** \brief Memory Interface Offset Counter Start Value For Main Picture Y, JPEG
+ * or RAW Data Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_MP_Y_OFFS_CNT_START_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_MP_Y_OFFS_CNT_START;
+
+/** \brief Memory Interface Size of main picture Y component, JPEG or RAW data
+ * Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_MP_Y_SIZE_INIT_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_MP_Y_SIZE_INIT;
+
+/** \brief Memory Interface Size Shadow Register of Main Picture Y
+ * Component,JPEG or RAW Data Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_MP_Y_SIZE_SHD_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_MP_Y_SIZE_SHD;
+
+/** \brief MI Raw Interrupt Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_RIS_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_RIS;
+
+/** \brief MI Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_STATUS_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_STATUS;
+
+/** \brief MI Status Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MI_STATUS_CLR_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MI_STATUS_CLR;
+
+/** \brief Memory Interface Base Address For Extra Path Data Buffer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MIEP_CH_BASE_AD_INIT_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MIEP_CH_BASE_AD_INIT;
+
+/** \brief Memory Interface Base Address Shadow Register for Extra Path Buffer
+ * Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MIEP_CH_BASE_AD_SHD_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MIEP_CH_BASE_AD_SHD;
+
+/** \brief Memory Interface Extra Path Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MIEP_CH_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MIEP_CH_CTRL;
+
+/** \brief Memory Interface Extra Path Control Internal Shadow Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MIEP_CH_CTRL_SHD_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MIEP_CH_CTRL_SHD;
+
+/** \brief Memory Interface Extra Path Control Register For Address Init And
+ * Skip Function Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MIEP_CH_INIT_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MIEP_CH_INIT;
+
+/** \brief Memory Interface Fill Level Interrupt Offset Value For Extra Path
+ * Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MIEP_CH_IRQ_OFFS_INIT_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MIEP_CH_IRQ_OFFS_INIT;
+
+/** \brief Memory Interface Shadow Register of Fill Level Interrupt Offset
+ * Value For Extra Path Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MIEP_CH_IRQ_OFFS_SHD_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MIEP_CH_IRQ_OFFS_SHD;
+
+/** \brief Memory Interface Offset Counter Init Value For Extra Path Buffer
+ * Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MIEP_CH_OFFS_CNT_INIT_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MIEP_CH_OFFS_CNT_INIT;
+
+/** \brief Memory Interface Current Offset Counter of Extra Path Buffer
+ * Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MIEP_CH_OFFS_CNT_SHD_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MIEP_CH_OFFS_CNT_SHD;
+
+/** \brief Memory Interface Offset Counter Start Value For Extra Path Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MIEP_CH_OFFS_CNT_START_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MIEP_CH_OFFS_CNT_START;
+
+/** \brief Memory Interface Size of Extra Path Data Buffer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MIEP_CH_SIZE_INIT_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MIEP_CH_SIZE_INIT;
+
+/** \brief Memory Interface Size Shadow Register of Extra Path Buffer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MIEP_CH_SIZE_SHD_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MIEP_CH_SIZE_SHD;
+
+/** \brief MI Extra Path Interrupt Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MIEP_ICR_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MIEP_ICR;
+
+/** \brief MI Extra Path Interrupt Mask ‘1’: interrupt active, ‘0’: interrupt
+ * masked */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MIEP_IMSC_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MIEP_IMSC;
+
+/** \brief MI Extra Path Interrupt Set Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MIEP_ISR_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MIEP_ISR;
+
+/** \brief MI Extra Path Masked Interrupt Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MIEP_MIS_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MIEP_MIS;
+
+/** \brief MI Extra Path Raw Interrupt Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MIEP_RIS_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MIEP_RIS;
+
+/** \brief Extra Path Error Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MIEP_STA_ERR_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MIEP_STA_ERR;
+
+/** \brief Extra Path Error Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_MIEP_STA_ERR_CLR_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_MIEP_STA_ERR_CLR;
+
+/** \brief Watchdog Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_WD_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_WD_CTRL;
+
+/** \brief Watchdog Horizontal Timeout Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_WD_H_TIMEOUT_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_WD_H_TIMEOUT;
+
+/** \brief Watchdog Interrupt Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_WD_ICR_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_WD_ICR;
+
+/** \brief Watchdog Interrupt Mask Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_WD_IMSC_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_WD_IMSC;
+
+/** \brief Watchdog Interrupt Set Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_WD_ISR_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_WD_ISR;
+
+/** \brief Watchdog Masked Interrupt Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_WD_MIS_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_WD_MIS;
+
+/** \brief Watchdog Raw Interrupt Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_WD_RIS_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_WD_RIS;
+
+/** \brief Watchdog Vertical Timeout Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CIF_WD_V_TIMEOUT_Bits B; /**< \brief Bitfield access */
+} Ifx_CIF_WD_V_TIMEOUT;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Cif_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L2
+ * \{ */
+
+/** \brief Memory interface channel */
+typedef volatile struct _Ifx_CIF_MIEP_CH
+{
+ Ifx_CIF_MIEP_CH_CTRL CTRL; /**< \brief 0, Memory Interface Extra Path Control Register */
+ Ifx_CIF_MIEP_CH_INIT INIT; /**< \brief 4, Memory Interface Extra Path Control Register For Address Init And Skip Function Register */
+ Ifx_CIF_MIEP_CH_BASE_AD_INIT BASE_AD_INIT; /**< \brief 8, Memory Interface Base Address For Extra Path Data Buffer Register */
+ Ifx_CIF_MIEP_CH_SIZE_INIT SIZE_INIT; /**< \brief C, Memory Interface Size of Extra Path Data Buffer Register */
+ Ifx_CIF_MIEP_CH_OFFS_CNT_INIT OFFS_CNT_INIT; /**< \brief 10, Memory Interface Offset Counter Init Value For Extra Path Buffer Register */
+ Ifx_CIF_MIEP_CH_OFFS_CNT_START OFFS_CNT_START; /**< \brief 14, Memory Interface Offset Counter Start Value For Extra Path Register */
+ Ifx_CIF_MIEP_CH_IRQ_OFFS_INIT IRQ_OFFS_INIT; /**< \brief 18, Memory Interface Fill Level Interrupt Offset Value For Extra Path Register */
+ Ifx_CIF_MIEP_CH_CTRL_SHD CTRL_SHD; /**< \brief 1C, Memory Interface Extra Path Control Internal Shadow Register */
+ Ifx_CIF_MIEP_CH_BASE_AD_SHD BASE_AD_SHD; /**< \brief 20, Memory Interface Base Address Shadow Register for Extra Path Buffer Register */
+ Ifx_CIF_MIEP_CH_SIZE_SHD SIZE_SHD; /**< \brief 24, Memory Interface Size Shadow Register of Extra Path Buffer Register */
+ Ifx_CIF_MIEP_CH_OFFS_CNT_SHD OFFS_CNT_SHD; /**< \brief 28, Memory Interface Current Offset Counter of Extra Path Buffer Register */
+ Ifx_CIF_MIEP_CH_IRQ_OFFS_SHD IRQ_OFFS_SHD; /**< \brief 2C, Memory Interface Shadow Register of Fill Level Interrupt Offset Value For Extra Path Register */
+ unsigned char reserved_30[208]; /**< \brief 30, \internal Reserved */
+} Ifx_CIF_MIEP_CH;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Cif_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L1
+ * \{ */
+
+/** \brief BBB Object */
+typedef volatile struct _Ifx_CIF_BBB
+{
+ Ifx_CIF_BBB_CLC CLC; /**< \brief 0, Clock Control Register */
+ Ifx_CIF_BBB_MODID MODID; /**< \brief 4, Module Identification Register */
+ Ifx_CIF_BBB_GPCTL GPCTL; /**< \brief 8, General Purpose Control Register */
+ Ifx_CIF_BBB_ACCEN0 ACCEN0; /**< \brief C, Access Enable Register 0 */
+ Ifx_CIF_BBB_ACCEN1 ACCEN1; /**< \brief 10, Access Enable Register 1 */
+ Ifx_CIF_BBB_KRST0 KRST0; /**< \brief 14, Kernel Reset Register 0 */
+ Ifx_CIF_BBB_KRST1 KRST1; /**< \brief 18, Kernel Reset Register 1 */
+ Ifx_CIF_BBB_KRSTCLR KRSTCLR; /**< \brief 1C, Kernel Reset Status Clear Register */
+} Ifx_CIF_BBB;
+
+/** \brief DP Object */
+typedef volatile struct _Ifx_CIF_DP
+{
+ Ifx_CIF_DP_CTRL CTRL; /**< \brief 0, Debug Path Control Register */
+ Ifx_CIF_DP_PDIV_CTRL PDIV_CTRL; /**< \brief 4, Debug Path Predivider Control Register */
+ Ifx_CIF_DP_FLC_STAT FLC_STAT; /**< \brief 8, Debug Path Frame/Line Counter Status Register */
+ Ifx_CIF_DP_PDIV_STAT PDIV_STAT; /**< \brief C, Debug Path Predivider Counter Status Register */
+ Ifx_CIF_DP_TSC_STAT TSC_STAT; /**< \brief 10, Debug Path Timestamp Counter Status Register */
+ Ifx_CIF_DP_UDS UDS_1S[8]; /**< \brief 14, Debug Path User Defined Symbol Register \note Array index shifted by 1. Example: defined register UDS_1S[0]/UDS_1S0 corresponds to user manual UDS_1S1, ... */
+} Ifx_CIF_DP;
+
+/** \brief EP Object */
+typedef volatile struct _Ifx_CIF_EP_IC
+{
+ Ifx_CIF_EP_IC_CTRL CTRL; /**< \brief 0, Extra Path Image Cropping Control Register */
+ Ifx_CIF_EP_IC_RECENTER RECENTER; /**< \brief 4, Extra Path Image Cropping Recenter Register */
+ Ifx_CIF_EP_IC_H_OFFS H_OFFS; /**< \brief 8, Extra Path Image Cropping Horizontal Offset of Output Window Register */
+ Ifx_CIF_EP_IC_V_OFFS V_OFFS; /**< \brief C, Extra Path Image Cropping Vertical Offset Of Output Window Register */
+ Ifx_CIF_EP_IC_H_SIZE H_SIZE; /**< \brief 10, Extra Path Image Cropping Output Horizontal Picture Size Register */
+ Ifx_CIF_EP_IC_V_SIZE V_SIZE; /**< \brief 14, Extra Path Image Cropping Output Vertical Picture Size Register */
+ Ifx_CIF_EP_IC_MAX_DX MAX_DX; /**< \brief 18, Extra Path Image Cropping Maximum Horizontal Displacement Register */
+ Ifx_CIF_EP_IC_MAX_DY MAX_DY; /**< \brief 1C, Extra Path Image Cropping Maximum Vertical Displacement Register */
+ Ifx_CIF_EP_IC_DISPLACE DISPLACE; /**< \brief 20, Extra Path Image Cropping Camera Displacement Register */
+ Ifx_CIF_EP_IC_H_OFFS_SHD H_OFFS_SHD; /**< \brief 24, Extra Path Image Current Horizontal Offset Of Output Window Shadow Register */
+ Ifx_CIF_EP_IC_V_OFFS_SHD V_OFFS_SHD; /**< \brief 28, Extra Path Image Current Vertical Offset Of Output Window Shadow Register */
+ Ifx_CIF_EP_IC_H_SIZE_SHD H_SIZE_SHD; /**< \brief 2C, Extra Path Image Current Output Horizontal Picture Size Shadow Register */
+ Ifx_CIF_EP_IC_V_SIZE_SHD V_SIZE_SHD; /**< \brief 30, Extra Path Image Current Output Vertical Picture Size Shadow Register */
+ unsigned char reserved_34[204]; /**< \brief 34, \internal Reserved */
+} Ifx_CIF_EP_IC;
+
+/** \brief ISP Object */
+typedef volatile struct _Ifx_CIF_ISP
+{
+ Ifx_CIF_ISP_CTRL CTRL; /**< \brief 0, ISP Global Control Register */
+ Ifx_CIF_ISP_ACQ_PROP ACQ_PROP; /**< \brief 4, ISP Acquisition Properties Register */
+ Ifx_CIF_ISP_ACQ_H_OFFS ACQ_H_OFFS; /**< \brief 8, ISP Acquisition Horizontal Offset Register */
+ Ifx_CIF_ISP_ACQ_V_OFFS ACQ_V_OFFS; /**< \brief C, ISP Acquistion Vertical Offset Register */
+ Ifx_CIF_ISP_ACQ_H_SIZE ACQ_H_SIZE; /**< \brief 10, ISP Acquisition Horizontal Size Register */
+ Ifx_CIF_ISP_ACQ_V_SIZE ACQ_V_SIZE; /**< \brief 14, ISP Acquisition Vertical Size Register */
+ Ifx_CIF_ISP_ACQ_NR_FRAMES ACQ_NR_FRAMES; /**< \brief 18, ISP Acquisition Number of Frames Register */
+ unsigned char reserved_1C[376]; /**< \brief 1C, \internal Reserved */
+ Ifx_CIF_ISP_OUT_H_OFFS OUT_H_OFFS; /**< \brief 194, ISP Output Window Horizontal Offset Register */
+ Ifx_CIF_ISP_OUT_V_OFFS OUT_V_OFFS; /**< \brief 198, ISP Output Window Vertical Offset Register */
+ Ifx_CIF_ISP_OUT_H_SIZE OUT_H_SIZE; /**< \brief 19C, ISP Output Horizontal Picture Size Register */
+ Ifx_CIF_ISP_OUT_V_SIZE OUT_V_SIZE; /**< \brief 1A0, ISP Output Vertical Picture Size Register */
+ unsigned char reserved_1A4[4]; /**< \brief 1A4, \internal Reserved */
+ Ifx_CIF_ISP_FLAGS_SHD FLAGS_SHD; /**< \brief 1A8, ISP Shadow Flags Register */
+ Ifx_CIF_ISP_OUT_H_OFFS_SHD OUT_H_OFFS_SHD; /**< \brief 1AC, ISP Output Window Horizontal Offset Shadow Register */
+ Ifx_CIF_ISP_OUT_V_OFFS_SHD OUT_V_OFFS_SHD; /**< \brief 1B0, ISP Output Window Vertical Offset Shadow Register */
+ Ifx_CIF_ISP_OUT_H_SIZE_SHD OUT_H_SIZE_SHD; /**< \brief 1B4, ISP Output Horizontal Picture Size Shadow Register */
+ Ifx_CIF_ISP_OUT_V_SIZE_SHD OUT_V_SIZE_SHD; /**< \brief 1B8, ISP Output Vertical Picture Size Shadow Register */
+ Ifx_CIF_ISP_IMSC IMSC; /**< \brief 1BC, ISP Interrupt Mask Register */
+ Ifx_CIF_ISP_RIS RIS; /**< \brief 1C0, ISP Raw Interrupt Status Register */
+ Ifx_CIF_ISP_MIS MIS; /**< \brief 1C4, ISP Masked Interrupt Status Register */
+ Ifx_CIF_ISP_ICR ICR; /**< \brief 1C8, ISP Interrupt Clear Register */
+ Ifx_CIF_ISP_ISR ISR; /**< \brief 1CC, ISP Interrupt Set Register */
+ unsigned char reserved_1D0[108]; /**< \brief 1D0, \internal Reserved */
+ Ifx_CIF_ISP_ERR ERR; /**< \brief 23C, ISP Error Register */
+ Ifx_CIF_ISP_ERR_CLR ERR_CLR; /**< \brief 240, ISP Error Clear Register */
+ Ifx_CIF_ISP_FRAME_COUNT FRAME_COUNT; /**< \brief 244, ISP Frame Counter Register */
+} Ifx_CIF_ISP;
+
+/** \brief ISPIS Object */
+typedef volatile struct _Ifx_CIF_ISPIS
+{
+ Ifx_CIF_ISPIS_CTRL CTRL; /**< \brief 0, ISP Image Stabilization Control Register */
+ Ifx_CIF_ISPIS_RECENTER RECENTER; /**< \brief 4, ISP Image Stabilization Recenter Register */
+ Ifx_CIF_ISPIS_H_OFFS H_OFFS; /**< \brief 8, ISP Image Stabilization Horizontal Offset Of Output Window Register */
+ Ifx_CIF_ISPIS_V_OFFS V_OFFS; /**< \brief C, ISP Image Stabilization Vertical Offset Of Output Window Register */
+ Ifx_CIF_ISPIS_H_SIZE H_SIZE; /**< \brief 10, ISP Image Stabilization Output Horizontal Picture Size Register */
+ Ifx_CIF_ISPIS_V_SIZE V_SIZE; /**< \brief 14, ISP Image Stabilization Output Vertical Picture Size Register */
+ Ifx_CIF_ISPIS_MAX_DX MAX_DX; /**< \brief 18, ISP Image Stabilization Maximum Horizontal Displacement Register */
+ Ifx_CIF_ISPIS_MAX_DY MAX_DY; /**< \brief 1C, ISP Image Stabilization Maximum Vertical Displacement Register */
+ Ifx_CIF_ISPIS_DISPLACE DISPLACE; /**< \brief 20, ISP Image Stabilization Camera Displacement Register */
+ Ifx_CIF_ISPIS_H_OFFS_SHD H_OFFS_SHD; /**< \brief 24, SP Image Current Horizontal Offset Of Output Window Shadow Register */
+ Ifx_CIF_ISPIS_V_OFFS_SHD V_OFFS_SHD; /**< \brief 28, ISP Image Current Vertical Offset Of Output Window Shadow Register */
+ Ifx_CIF_ISPIS_H_SIZE_SHD H_SIZE_SHD; /**< \brief 2C, ISP Image Current Output Horizontal Picture Size Shadow Register */
+ Ifx_CIF_ISPIS_V_SIZE_SHD V_SIZE_SHD; /**< \brief 30, ISP Image Current Output Vertical Picture Size Shadow Register */
+} Ifx_CIF_ISPIS;
+
+/** \brief JPE Object */
+typedef volatile struct _Ifx_CIF_JPE
+{
+ Ifx_CIF_JPE_GEN_HEADER GEN_HEADER; /**< \brief 0, JPE Command To Start Stream Header Generation Register */
+ Ifx_CIF_JPE_ENCODE ENCODE; /**< \brief 4, JPE Start Command To Start JFIF Stream Encoding Register */
+ Ifx_CIF_JPE_INIT INIT; /**< \brief 8, JPE Automatic Configuration Update Register */
+ Ifx_CIF_JPE_Y_SCALE_EN Y_SCALE_EN; /**< \brief C, JPE Y Value Scaling Control Register */
+ Ifx_CIF_JPE_CBCR_SCALE_EN CBCR_SCALE_EN; /**< \brief 10, JPE Cb/Cr Value Scaling Control Register */
+ Ifx_CIF_JPE_TABLE_FLUSH TABLE_FLUSH; /**< \brief 14, JPE Header Generation Debug Register */
+ Ifx_CIF_JPE_ENC_HSIZE ENC_HSIZE; /**< \brief 18, JPEG Codec Horizontal Image Size For Encoding Register */
+ Ifx_CIF_JPE_ENC_VSIZE ENC_VSIZE; /**< \brief 1C, JPEG Codec Vertical Image Size For Encoding Register */
+ Ifx_CIF_JPE_PIC_FORMAT PIC_FORMAT; /**< \brief 20, JPEG Picture Encoding Format Register */
+ Ifx_CIF_JPE_RESTART_INTERVAL RESTART_INTERVAL; /**< \brief 24, JPE Restart Marker Insertion Register */
+ Ifx_CIF_JPE_TQ_Y_SELECT TQ_Y_SELECT; /**< \brief 28, Q- table Selector 0 Quant Table For Y Component */
+ Ifx_CIF_JPE_TQ_U_SELECT TQ_U_SELECT; /**< \brief 2C, Q- table Selector 1, Quant. Table For U Component */
+ Ifx_CIF_JPE_TQ_V_SELECT TQ_V_SELECT; /**< \brief 30, Q- table Selector 2 Quant Table For V Component */
+ Ifx_CIF_JPE_DC_TABLE_SELECT DC_TABLE_SELECT; /**< \brief 34, JPE Huffman Table Selector For DC Values Register */
+ Ifx_CIF_JPE_AC_TABLE_SELECT AC_TABLE_SELECT; /**< \brief 38, JPE Huffman Table Selector For AC Values Register */
+ Ifx_CIF_JPE_TABLE_DATA TABLE_DATA; /**< \brief 3C, JPE Table Programming Register */
+ Ifx_CIF_JPE_TABLE_ID TABLE_ID; /**< \brief 40, JPE Table Programming Select Register */
+ Ifx_CIF_JPE_TAC0_LEN TAC0_LEN; /**< \brief 44, JPE Huffman AC Table 0 Length Register */
+ Ifx_CIF_JPE_TDC0_LEN TDC0_LEN; /**< \brief 48, JPE Huffman DC Table 0 Length Register */
+ Ifx_CIF_JPE_TAC1_LEN TAC1_LEN; /**< \brief 4C, JPE Huffman AC Table 1 Length Register */
+ Ifx_CIF_JPE_TDC1_LEN TDC1_LEN; /**< \brief 50, JPE Huffman DC Table 1 Length Register */
+ unsigned char reserved_54[4]; /**< \brief 54, \internal Reserved */
+ Ifx_CIF_JPE_ENCODER_BUSY ENCODER_BUSY; /**< \brief 58, JPE Encoder Status Flag Register */
+ Ifx_CIF_JPE_HEADER_MODE HEADER_MODE; /**< \brief 5C, JPE Header Mode Definition Register */
+ Ifx_CIF_JPE_ENCODE_MODE ENCODE_MODE; /**< \brief 60, JPE Encode Mode Register */
+ Ifx_CIF_JPE_DEBUG DEBUG; /**< \brief 64, JPE Debug Information Register */
+ Ifx_CIF_JPE_ERROR_IMR ERROR_IMR; /**< \brief 68, JPE Error Interrupt Mask Register */
+ Ifx_CIF_JPE_ERROR_RIS ERROR_RIS; /**< \brief 6C, JPE Error Raw Interrupt Status Register */
+ Ifx_CIF_JPE_ERROR_MIS ERROR_MIS; /**< \brief 70, JPE Error Masked Interrupt Status Register */
+ Ifx_CIF_JPE_ERROR_ICR ERROR_ICR; /**< \brief 74, JPE Error Interrupt Clear Register */
+ Ifx_CIF_JPE_ERROR_ISR ERROR_ISR; /**< \brief 78, JPE Error Interrupt Set Register */
+ Ifx_CIF_JPE_STATUS_IMR STATUS_IMR; /**< \brief 7C, JPEG Status Interrupt Mask Register */
+ Ifx_CIF_JPE_STATUS_RIS STATUS_RIS; /**< \brief 80, JPEG Status Raw Interrupt Status Register */
+ Ifx_CIF_JPE_STATUS_MIS STATUS_MIS; /**< \brief 84, JPEG Status Masked Interrupt Status Register */
+ Ifx_CIF_JPE_STATUS_ICR STATUS_ICR; /**< \brief 88, JPEG Status Interrupt Clear Register */
+ Ifx_CIF_JPE_STATUS_ISR STATUS_ISR; /**< \brief 8C, JPEG Status Interrupt Set Register */
+} Ifx_CIF_JPE;
+
+/** \brief LDS Object */
+typedef volatile struct _Ifx_CIF_LDS
+{
+ Ifx_CIF_LDS_CTRL CTRL; /**< \brief 0, Linear Downscaler Control Register */
+ Ifx_CIF_LDS_FAC FAC; /**< \brief 4, Linear Downscaler Factor Register */
+} Ifx_CIF_LDS;
+
+/** \brief MI Object */
+typedef volatile struct _Ifx_CIF_MI
+{
+ Ifx_CIF_MI_CTRL CTRL; /**< \brief 0, Memory Interface Global Control Register */
+ Ifx_CIF_MI_INIT INIT; /**< \brief 4, Memory Interface Control Register For Address Init And Skip Function Register */
+ Ifx_CIF_MI_MP_Y_BASE_AD_INIT MP_Y_BASE_AD_INIT; /**< \brief 8, Memory Interface Base Address For Main Picture Y Component, JPEG or RAW Data Register */
+ Ifx_CIF_MI_MP_Y_SIZE_INIT MP_Y_SIZE_INIT; /**< \brief C, Memory Interface Size of main picture Y component, JPEG or RAW data Register */
+ Ifx_CIF_MI_MP_Y_OFFS_CNT_INIT MP_Y_OFFS_CNT_INIT; /**< \brief 10, Memory Interface Offset Counter Init Value For Main Picture Y, JPEG or RAW Data Register */
+ Ifx_CIF_MI_MP_Y_OFFS_CNT_START MP_Y_OFFS_CNT_START; /**< \brief 14, Memory Interface Offset Counter Start Value For Main Picture Y, JPEG or RAW Data Register */
+ Ifx_CIF_MI_MP_Y_IRQ_OFFS_INIT MP_Y_IRQ_OFFS_INIT; /**< \brief 18, Memory Interface Fill Level Interrupt Offset Value For Main Picture Y, JPEG or RAW Data Register */
+ Ifx_CIF_MI_MP_CB_BASE_AD_INIT MP_CB_BASE_AD_INIT; /**< \brief 1C, Memory Interface Base Address For Main Picture Cb Component Ring Buffer Register */
+ Ifx_CIF_MI_MP_CB_SIZE_INIT MP_CB_SIZE_INIT; /**< \brief 20, Memory Interface Size Of Main Picture Cb Component Ring Buffer Register */
+ Ifx_CIF_MI_MP_CB_OFFS_CNT_INIT MP_CB_OFFS_CNT_INIT; /**< \brief 24, Memory Interface Offset Counter Init Value For Main Picture Cb Component Ring Buffer Register */
+ Ifx_CIF_MI_MP_CB_OFFS_CNT_START MP_CB_OFFS_CNT_START; /**< \brief 28, Memory Interface Offset Counter Start Value For Main Picture Cb Component Ring Buffer Register */
+ Ifx_CIF_MI_MP_CR_BASE_AD_INIT MP_CR_BASE_AD_INIT; /**< \brief 2C, Memory Interface Base Address For Main Picture Cr Component Ring Buffer Register */
+ Ifx_CIF_MI_MP_CR_SIZE_INIT MP_CR_SIZE_INIT; /**< \brief 30, Memory Interface Size Of Main Picture Cr Component Ring Buffer Register */
+ Ifx_CIF_MI_MP_CR_OFFS_CNT_INIT MP_CR_OFFS_CNT_INIT; /**< \brief 34, Memory Interface Offset Counter Init value For Main Picture Cr Component Ring Buffer Register */
+ Ifx_CIF_MI_MP_CR_OFFS_CNT_START MP_CR_OFFS_CNT_START; /**< \brief 38, Memory Interface Offset Counter Start Value For Main Picture Cr Component Ring Buffer Register */
+ unsigned char reserved_3C[52]; /**< \brief 3C, \internal Reserved */
+ Ifx_CIF_MI_BYTE_CNT BYTE_CNT; /**< \brief 70, Memory Interface Counter Value of JPEG or RAW Data Bytes Register */
+ Ifx_CIF_MI_CTRL_SHD CTRL_SHD; /**< \brief 74, Memory Interface Global Control Internal Shadow Register */
+ Ifx_CIF_MI_MP_Y_BASE_AD_SHD MP_Y_BASE_AD_SHD; /**< \brief 78, Memory Interface Base Address Shadow Register For Main Picture Y Component, JPEG Register */
+ Ifx_CIF_MI_MP_Y_SIZE_SHD MP_Y_SIZE_SHD; /**< \brief 7C, Memory Interface Size Shadow Register of Main Picture Y Component,JPEG or RAW Data Register */
+ Ifx_CIF_MI_MP_Y_OFFS_CNT_SHD MP_Y_OFFS_CNT_SHD; /**< \brief 80, Memory Interface Current Offset Counter of Main Picture Y Component JPEG or RAW Register */
+ Ifx_CIF_MI_MP_Y_IRQ_OFFS_SHD MP_Y_IRQ_OFFS_SHD; /**< \brief 84, Memory Interface Shadow Register of Fill Level Interrupt Offset Value For Main Picture Y Register */
+ Ifx_CIF_MI_MP_CB_BASE_AD_SHD MP_CB_BASE_AD_SHD; /**< \brief 88, Memory Interface Base Address Shadow Register For Main Picture Cb Component Ring Register */
+ Ifx_CIF_MI_MP_CB_SIZE_SHD MP_CB_SIZE_SHD; /**< \brief 8C, Memory Interface Size Shadow Register Of Main Picture Cb Component Ring Buffer Register */
+ Ifx_CIF_MI_MP_CB_OFFS_CNT_SHD MP_CB_OFFS_CNT_SHD; /**< \brief 90, Memory Interface Current Offset Counter Of Main Picture Cb Component Ring Buffer Register */
+ Ifx_CIF_MI_MP_CR_BASE_AD_SHD MP_CR_BASE_AD_SHD; /**< \brief 94, Memory Interface Base Address Shadow Register For Main Picture Cr Component Ring Register */
+ Ifx_CIF_MI_MP_CR_SIZE_SHD MP_CR_SIZE_SHD; /**< \brief 98, Memory Interface Size Shadow Register Of Main Picture Cr Component Ring Buffer Register */
+ Ifx_CIF_MI_MP_CR_OFFS_CNT_SHD MP_CR_OFFS_CNT_SHD; /**< \brief 9C, Memory Interface Current Offset Counter Of Main Picture Cr Component Ring Buffer Register */
+ unsigned char reserved_A0[88]; /**< \brief A0, \internal Reserved */
+ Ifx_CIF_MI_IMSC IMSC; /**< \brief F8, MI Interrupt Mask ‘1’ interrupt active ‘0’ interrupt masked */
+ Ifx_CIF_MI_RIS RIS; /**< \brief FC, MI Raw Interrupt Status Register */
+ Ifx_CIF_MI_MIS MIS; /**< \brief 100, MI Masked Interrupt Status Registe */
+ Ifx_CIF_MI_ICR ICR; /**< \brief 104, MI Interrupt Clear Register */
+ Ifx_CIF_MI_ISR ISR; /**< \brief 108, MI Interrupt Set Register */
+ Ifx_CIF_MI_STATUS STATUS; /**< \brief 10C, MI Status Register */
+ Ifx_CIF_MI_STATUS_CLR STATUS_CLR; /**< \brief 110, MI Status Clear Register */
+} Ifx_CIF_MI;
+
+/** \brief MIEP Object */
+typedef volatile struct _Ifx_CIF_MIEP
+{
+ Ifx_CIF_MIEP_STA_ERR STA_ERR; /**< \brief 0, Extra Path Error Register */
+ Ifx_CIF_MIEP_STA_ERR_CLR STA_ERR_CLR; /**< \brief 4, Extra Path Error Clear Register */
+ Ifx_CIF_MIEP_IMSC IMSC; /**< \brief 8, MI Extra Path Interrupt Mask ‘1’: interrupt active, ‘0’: interrupt masked */
+ Ifx_CIF_MIEP_RIS RIS; /**< \brief C, MI Extra Path Raw Interrupt Status Register */
+ Ifx_CIF_MIEP_MIS MIS; /**< \brief 10, MI Extra Path Masked Interrupt Status Register */
+ Ifx_CIF_MIEP_ICR ICR; /**< \brief 14, MI Extra Path Interrupt Clear Register */
+ Ifx_CIF_MIEP_ISR ISR; /**< \brief 18, MI Extra Path Interrupt Set Register */
+ unsigned char reserved_1C[228]; /**< \brief 1C, \internal Reserved */
+ Ifx_CIF_MIEP_CH CH_1S[5]; /**< \brief 100, Memory interface channel \note Array index shifted by 1. Example: defined register CH_1S[0]/CH_1S0 corresponds to user manual CH_1S1, ... */
+} Ifx_CIF_MIEP;
+
+/** \brief WD Object */
+typedef volatile struct _Ifx_CIF_WD
+{
+ Ifx_CIF_WD_CTRL CTRL; /**< \brief 0, Watchdog Control Register */
+ Ifx_CIF_WD_V_TIMEOUT V_TIMEOUT; /**< \brief 4, Watchdog Vertical Timeout Register */
+ Ifx_CIF_WD_H_TIMEOUT H_TIMEOUT; /**< \brief 8, Watchdog Horizontal Timeout Register */
+ Ifx_CIF_WD_IMSC IMSC; /**< \brief C, Watchdog Interrupt Mask Register */
+ Ifx_CIF_WD_RIS RIS; /**< \brief 10, Watchdog Raw Interrupt Status Register */
+ Ifx_CIF_WD_MIS MIS; /**< \brief 14, Watchdog Masked Interrupt Status Register */
+ Ifx_CIF_WD_ICR ICR; /**< \brief 18, Watchdog Interrupt Clear Register */
+ Ifx_CIF_WD_ISR ISR; /**< \brief 1C, Watchdog Interrupt Set Register */
+} Ifx_CIF_WD;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Cif_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief CIF object */
+typedef volatile struct _Ifx_CIF
+{
+ Ifx_CIF_BBB BBB; /**< \brief 0, BBB Object */
+ unsigned char reserved_20[224]; /**< \brief 20, \internal Reserved */
+ Ifx_CIF_CCL CCL; /**< \brief 100, Clock Control Register */
+ unsigned char reserved_104[4]; /**< \brief 104, \internal Reserved */
+ Ifx_CIF_ID ID; /**< \brief 108, CIF Revision Identification Register */
+ unsigned char reserved_10C[4]; /**< \brief 10C, \internal Reserved */
+ Ifx_CIF_ICCL ICCL; /**< \brief 110, CIF Internal Clock Control Register */
+ Ifx_CIF_IRCL IRCL; /**< \brief 114, CIF Internal Reset Control Register */
+ Ifx_CIF_DPCL DPCL; /**< \brief 118, CIF Data Path Control Register */
+ unsigned char reserved_11C[996]; /**< \brief 11C, \internal Reserved */
+ Ifx_CIF_ISP ISP; /**< \brief 500, ISP Object */
+ unsigned char reserved_748[3512]; /**< \brief 748, \internal Reserved */
+ Ifx_CIF_MI MI; /**< \brief 1500, MI Object */
+ unsigned char reserved_1614[748]; /**< \brief 1614, \internal Reserved */
+ Ifx_CIF_JPE JPE; /**< \brief 1900, JPE Object */
+ unsigned char reserved_1990[2672]; /**< \brief 1990, \internal Reserved */
+ Ifx_CIF_ISPIS ISPIS; /**< \brief 2400, ISPIS Object */
+ unsigned char reserved_2434[204]; /**< \brief 2434, \internal Reserved */
+ Ifx_CIF_WD WD; /**< \brief 2500, WD Object */
+ unsigned char reserved_2520[224]; /**< \brief 2520, \internal Reserved */
+ Ifx_CIF_LDS LDS; /**< \brief 2600, LDS Object */
+ unsigned char reserved_2608[504]; /**< \brief 2608, \internal Reserved */
+ Ifx_CIF_DP DP; /**< \brief 2800, DP Object */
+ unsigned char reserved_2834[460]; /**< \brief 2834, \internal Reserved */
+ Ifx_CIF_EP_IC EP_IC_1S[5]; /**< \brief 2A00, EP Object \note Array index shifted by 1. Example: defined register EP_IC_1S[0]/EP_IC_1S0 corresponds to user manual EP_IC_1S1, ... */
+ unsigned char reserved_2F00[1536]; /**< \brief 2F00, \internal Reserved */
+ Ifx_CIF_MIEP MIEP; /**< \brief 3500, MIEP Object */
+ unsigned char reserved_3B00[1]; /**< \brief 3B00, \internal Reserved */
+} Ifx_CIF;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXCIF_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCpu_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCpu_bf.h
new file mode 100644
index 0000000..531cb30
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCpu_bf.h
@@ -0,0 +1,1845 @@
+/**
+ * \file IfxCpu_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Cpu_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Cpu
+ *
+ */
+#ifndef IFXCPU_BF_H
+#define IFXCPU_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Cpu_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_CPU_A_Bits.ADDR */
+#define IFX_CPU_A_ADDR_LEN (32u)
+
+/** \brief Mask for Ifx_CPU_A_Bits.ADDR */
+#define IFX_CPU_A_ADDR_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_CPU_A_Bits.ADDR */
+#define IFX_CPU_A_ADDR_OFF (0u)
+
+/** \brief Length for Ifx_CPU_BIV_Bits.BIV */
+#define IFX_CPU_BIV_BIV_LEN (31u)
+
+/** \brief Mask for Ifx_CPU_BIV_Bits.BIV */
+#define IFX_CPU_BIV_BIV_MSK (0x7fffffffu)
+
+/** \brief Offset for Ifx_CPU_BIV_Bits.BIV */
+#define IFX_CPU_BIV_BIV_OFF (1u)
+
+/** \brief Length for Ifx_CPU_BIV_Bits.VSS */
+#define IFX_CPU_BIV_VSS_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_BIV_Bits.VSS */
+#define IFX_CPU_BIV_VSS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_BIV_Bits.VSS */
+#define IFX_CPU_BIV_VSS_OFF (0u)
+
+/** \brief Length for Ifx_CPU_BTV_Bits.BTV */
+#define IFX_CPU_BTV_BTV_LEN (31u)
+
+/** \brief Mask for Ifx_CPU_BTV_Bits.BTV */
+#define IFX_CPU_BTV_BTV_MSK (0x7fffffffu)
+
+/** \brief Offset for Ifx_CPU_BTV_Bits.BTV */
+#define IFX_CPU_BTV_BTV_OFF (1u)
+
+/** \brief Length for Ifx_CPU_CCNT_Bits.CountValue */
+#define IFX_CPU_CCNT_COUNTVALUE_LEN (31u)
+
+/** \brief Mask for Ifx_CPU_CCNT_Bits.CountValue */
+#define IFX_CPU_CCNT_COUNTVALUE_MSK (0x7fffffffu)
+
+/** \brief Offset for Ifx_CPU_CCNT_Bits.CountValue */
+#define IFX_CPU_CCNT_COUNTVALUE_OFF (0u)
+
+/** \brief Length for Ifx_CPU_CCNT_Bits.SOvf */
+#define IFX_CPU_CCNT_SOVF_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_CCNT_Bits.SOvf */
+#define IFX_CPU_CCNT_SOVF_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_CCNT_Bits.SOvf */
+#define IFX_CPU_CCNT_SOVF_OFF (31u)
+
+/** \brief Length for Ifx_CPU_CCTRL_Bits.CE */
+#define IFX_CPU_CCTRL_CE_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_CCTRL_Bits.CE */
+#define IFX_CPU_CCTRL_CE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_CCTRL_Bits.CE */
+#define IFX_CPU_CCTRL_CE_OFF (1u)
+
+/** \brief Length for Ifx_CPU_CCTRL_Bits.CM */
+#define IFX_CPU_CCTRL_CM_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_CCTRL_Bits.CM */
+#define IFX_CPU_CCTRL_CM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_CCTRL_Bits.CM */
+#define IFX_CPU_CCTRL_CM_OFF (0u)
+
+/** \brief Length for Ifx_CPU_CCTRL_Bits.M1 */
+#define IFX_CPU_CCTRL_M1_LEN (3u)
+
+/** \brief Mask for Ifx_CPU_CCTRL_Bits.M1 */
+#define IFX_CPU_CCTRL_M1_MSK (0x7u)
+
+/** \brief Offset for Ifx_CPU_CCTRL_Bits.M1 */
+#define IFX_CPU_CCTRL_M1_OFF (2u)
+
+/** \brief Length for Ifx_CPU_CCTRL_Bits.M2 */
+#define IFX_CPU_CCTRL_M2_LEN (3u)
+
+/** \brief Mask for Ifx_CPU_CCTRL_Bits.M2 */
+#define IFX_CPU_CCTRL_M2_MSK (0x7u)
+
+/** \brief Offset for Ifx_CPU_CCTRL_Bits.M2 */
+#define IFX_CPU_CCTRL_M2_OFF (5u)
+
+/** \brief Length for Ifx_CPU_CCTRL_Bits.M3 */
+#define IFX_CPU_CCTRL_M3_LEN (3u)
+
+/** \brief Mask for Ifx_CPU_CCTRL_Bits.M3 */
+#define IFX_CPU_CCTRL_M3_MSK (0x7u)
+
+/** \brief Offset for Ifx_CPU_CCTRL_Bits.M3 */
+#define IFX_CPU_CCTRL_M3_OFF (8u)
+
+/** \brief Length for Ifx_CPU_COMPAT_Bits.RM */
+#define IFX_CPU_COMPAT_RM_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_COMPAT_Bits.RM */
+#define IFX_CPU_COMPAT_RM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_COMPAT_Bits.RM */
+#define IFX_CPU_COMPAT_RM_OFF (3u)
+
+/** \brief Length for Ifx_CPU_COMPAT_Bits.SP */
+#define IFX_CPU_COMPAT_SP_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_COMPAT_Bits.SP */
+#define IFX_CPU_COMPAT_SP_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_COMPAT_Bits.SP */
+#define IFX_CPU_COMPAT_SP_OFF (4u)
+
+/** \brief Length for Ifx_CPU_CORE_ID_Bits.CORE_ID */
+#define IFX_CPU_CORE_ID_CORE_ID_LEN (3u)
+
+/** \brief Mask for Ifx_CPU_CORE_ID_Bits.CORE_ID */
+#define IFX_CPU_CORE_ID_CORE_ID_MSK (0x7u)
+
+/** \brief Offset for Ifx_CPU_CORE_ID_Bits.CORE_ID */
+#define IFX_CPU_CORE_ID_CORE_ID_OFF (0u)
+
+/** \brief Length for Ifx_CPU_CPR_L_Bits.LOWBND */
+#define IFX_CPU_CPR_L_LOWBND_LEN (29u)
+
+/** \brief Mask for Ifx_CPU_CPR_L_Bits.LOWBND */
+#define IFX_CPU_CPR_L_LOWBND_MSK (0x1fffffffu)
+
+/** \brief Offset for Ifx_CPU_CPR_L_Bits.LOWBND */
+#define IFX_CPU_CPR_L_LOWBND_OFF (3u)
+
+/** \brief Length for Ifx_CPU_CPR_U_Bits.UPPBND */
+#define IFX_CPU_CPR_U_UPPBND_LEN (29u)
+
+/** \brief Mask for Ifx_CPU_CPR_U_Bits.UPPBND */
+#define IFX_CPU_CPR_U_UPPBND_MSK (0x1fffffffu)
+
+/** \brief Offset for Ifx_CPU_CPR_U_Bits.UPPBND */
+#define IFX_CPU_CPR_U_UPPBND_OFF (3u)
+
+/** \brief Length for Ifx_CPU_CPU_ID_Bits.MOD_32B */
+#define IFX_CPU_CPU_ID_MOD_32B_LEN (8u)
+
+/** \brief Mask for Ifx_CPU_CPU_ID_Bits.MOD_32B */
+#define IFX_CPU_CPU_ID_MOD_32B_MSK (0xffu)
+
+/** \brief Offset for Ifx_CPU_CPU_ID_Bits.MOD_32B */
+#define IFX_CPU_CPU_ID_MOD_32B_OFF (8u)
+
+/** \brief Length for Ifx_CPU_CPU_ID_Bits.MOD */
+#define IFX_CPU_CPU_ID_MOD_LEN (16u)
+
+/** \brief Mask for Ifx_CPU_CPU_ID_Bits.MOD */
+#define IFX_CPU_CPU_ID_MOD_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CPU_CPU_ID_Bits.MOD */
+#define IFX_CPU_CPU_ID_MOD_OFF (16u)
+
+/** \brief Length for Ifx_CPU_CPU_ID_Bits.MODREV */
+#define IFX_CPU_CPU_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_CPU_CPU_ID_Bits.MODREV */
+#define IFX_CPU_CPU_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_CPU_CPU_ID_Bits.MODREV */
+#define IFX_CPU_CPU_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_CPU_CPXE_Bits.XE */
+#define IFX_CPU_CPXE_XE_LEN (8u)
+
+/** \brief Mask for Ifx_CPU_CPXE_Bits.XE */
+#define IFX_CPU_CPXE_XE_MSK (0xffu)
+
+/** \brief Offset for Ifx_CPU_CPXE_Bits.XE */
+#define IFX_CPU_CPXE_XE_OFF (0u)
+
+/** \brief Length for Ifx_CPU_CREVT_Bits.BBM */
+#define IFX_CPU_CREVT_BBM_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_CREVT_Bits.BBM */
+#define IFX_CPU_CREVT_BBM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_CREVT_Bits.BBM */
+#define IFX_CPU_CREVT_BBM_OFF (3u)
+
+/** \brief Length for Ifx_CPU_CREVT_Bits.BOD */
+#define IFX_CPU_CREVT_BOD_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_CREVT_Bits.BOD */
+#define IFX_CPU_CREVT_BOD_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_CREVT_Bits.BOD */
+#define IFX_CPU_CREVT_BOD_OFF (4u)
+
+/** \brief Length for Ifx_CPU_CREVT_Bits.CNT */
+#define IFX_CPU_CREVT_CNT_LEN (2u)
+
+/** \brief Mask for Ifx_CPU_CREVT_Bits.CNT */
+#define IFX_CPU_CREVT_CNT_MSK (0x3u)
+
+/** \brief Offset for Ifx_CPU_CREVT_Bits.CNT */
+#define IFX_CPU_CREVT_CNT_OFF (6u)
+
+/** \brief Length for Ifx_CPU_CREVT_Bits.EVTA */
+#define IFX_CPU_CREVT_EVTA_LEN (3u)
+
+/** \brief Mask for Ifx_CPU_CREVT_Bits.EVTA */
+#define IFX_CPU_CREVT_EVTA_MSK (0x7u)
+
+/** \brief Offset for Ifx_CPU_CREVT_Bits.EVTA */
+#define IFX_CPU_CREVT_EVTA_OFF (0u)
+
+/** \brief Length for Ifx_CPU_CREVT_Bits.SUSP */
+#define IFX_CPU_CREVT_SUSP_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_CREVT_Bits.SUSP */
+#define IFX_CPU_CREVT_SUSP_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_CREVT_Bits.SUSP */
+#define IFX_CPU_CREVT_SUSP_OFF (5u)
+
+/** \brief Length for Ifx_CPU_CUS_ID_Bits.CID */
+#define IFX_CPU_CUS_ID_CID_LEN (3u)
+
+/** \brief Mask for Ifx_CPU_CUS_ID_Bits.CID */
+#define IFX_CPU_CUS_ID_CID_MSK (0x7u)
+
+/** \brief Offset for Ifx_CPU_CUS_ID_Bits.CID */
+#define IFX_CPU_CUS_ID_CID_OFF (0u)
+
+/** \brief Length for Ifx_CPU_D_Bits.DATA */
+#define IFX_CPU_D_DATA_LEN (32u)
+
+/** \brief Mask for Ifx_CPU_D_Bits.DATA */
+#define IFX_CPU_D_DATA_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_CPU_D_Bits.DATA */
+#define IFX_CPU_D_DATA_OFF (0u)
+
+/** \brief Length for Ifx_CPU_DATR_Bits.CFE */
+#define IFX_CPU_DATR_CFE_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DATR_Bits.CFE */
+#define IFX_CPU_DATR_CFE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DATR_Bits.CFE */
+#define IFX_CPU_DATR_CFE_OFF (10u)
+
+/** \brief Length for Ifx_CPU_DATR_Bits.CWE */
+#define IFX_CPU_DATR_CWE_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DATR_Bits.CWE */
+#define IFX_CPU_DATR_CWE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DATR_Bits.CWE */
+#define IFX_CPU_DATR_CWE_OFF (9u)
+
+/** \brief Length for Ifx_CPU_DATR_Bits.SBE */
+#define IFX_CPU_DATR_SBE_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DATR_Bits.SBE */
+#define IFX_CPU_DATR_SBE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DATR_Bits.SBE */
+#define IFX_CPU_DATR_SBE_OFF (3u)
+
+/** \brief Length for Ifx_CPU_DATR_Bits.SME */
+#define IFX_CPU_DATR_SME_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DATR_Bits.SME */
+#define IFX_CPU_DATR_SME_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DATR_Bits.SME */
+#define IFX_CPU_DATR_SME_OFF (15u)
+
+/** \brief Length for Ifx_CPU_DATR_Bits.SOE */
+#define IFX_CPU_DATR_SOE_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DATR_Bits.SOE */
+#define IFX_CPU_DATR_SOE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DATR_Bits.SOE */
+#define IFX_CPU_DATR_SOE_OFF (14u)
+
+/** \brief Length for Ifx_CPU_DBGSR_Bits.DE */
+#define IFX_CPU_DBGSR_DE_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DBGSR_Bits.DE */
+#define IFX_CPU_DBGSR_DE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DBGSR_Bits.DE */
+#define IFX_CPU_DBGSR_DE_OFF (0u)
+
+/** \brief Length for Ifx_CPU_DBGSR_Bits.EVTSRC */
+#define IFX_CPU_DBGSR_EVTSRC_LEN (5u)
+
+/** \brief Mask for Ifx_CPU_DBGSR_Bits.EVTSRC */
+#define IFX_CPU_DBGSR_EVTSRC_MSK (0x1fu)
+
+/** \brief Offset for Ifx_CPU_DBGSR_Bits.EVTSRC */
+#define IFX_CPU_DBGSR_EVTSRC_OFF (8u)
+
+/** \brief Length for Ifx_CPU_DBGSR_Bits.HALT */
+#define IFX_CPU_DBGSR_HALT_LEN (2u)
+
+/** \brief Mask for Ifx_CPU_DBGSR_Bits.HALT */
+#define IFX_CPU_DBGSR_HALT_MSK (0x3u)
+
+/** \brief Offset for Ifx_CPU_DBGSR_Bits.HALT */
+#define IFX_CPU_DBGSR_HALT_OFF (1u)
+
+/** \brief Length for Ifx_CPU_DBGSR_Bits.PEVT */
+#define IFX_CPU_DBGSR_PEVT_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DBGSR_Bits.PEVT */
+#define IFX_CPU_DBGSR_PEVT_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DBGSR_Bits.PEVT */
+#define IFX_CPU_DBGSR_PEVT_OFF (7u)
+
+/** \brief Length for Ifx_CPU_DBGSR_Bits.PREVSUSP */
+#define IFX_CPU_DBGSR_PREVSUSP_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DBGSR_Bits.PREVSUSP */
+#define IFX_CPU_DBGSR_PREVSUSP_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DBGSR_Bits.PREVSUSP */
+#define IFX_CPU_DBGSR_PREVSUSP_OFF (6u)
+
+/** \brief Length for Ifx_CPU_DBGSR_Bits.SIH */
+#define IFX_CPU_DBGSR_SIH_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DBGSR_Bits.SIH */
+#define IFX_CPU_DBGSR_SIH_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DBGSR_Bits.SIH */
+#define IFX_CPU_DBGSR_SIH_OFF (3u)
+
+/** \brief Length for Ifx_CPU_DBGSR_Bits.SUSP */
+#define IFX_CPU_DBGSR_SUSP_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DBGSR_Bits.SUSP */
+#define IFX_CPU_DBGSR_SUSP_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DBGSR_Bits.SUSP */
+#define IFX_CPU_DBGSR_SUSP_OFF (4u)
+
+/** \brief Length for Ifx_CPU_DBGTCR_Bits.DTA */
+#define IFX_CPU_DBGTCR_DTA_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DBGTCR_Bits.DTA */
+#define IFX_CPU_DBGTCR_DTA_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DBGTCR_Bits.DTA */
+#define IFX_CPU_DBGTCR_DTA_OFF (0u)
+
+/** \brief Length for Ifx_CPU_DCON0_Bits.DCBYP */
+#define IFX_CPU_DCON0_DCBYP_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DCON0_Bits.DCBYP */
+#define IFX_CPU_DCON0_DCBYP_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DCON0_Bits.DCBYP */
+#define IFX_CPU_DCON0_DCBYP_OFF (1u)
+
+/** \brief Length for Ifx_CPU_DCON2_Bits.DCACHE_SZE */
+#define IFX_CPU_DCON2_DCACHE_SZE_LEN (16u)
+
+/** \brief Mask for Ifx_CPU_DCON2_Bits.DCACHE_SZE */
+#define IFX_CPU_DCON2_DCACHE_SZE_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CPU_DCON2_Bits.DCACHE_SZE */
+#define IFX_CPU_DCON2_DCACHE_SZE_OFF (0u)
+
+/** \brief Length for Ifx_CPU_DCON2_Bits.DSCRATCH_SZE */
+#define IFX_CPU_DCON2_DSCRATCH_SZE_LEN (16u)
+
+/** \brief Mask for Ifx_CPU_DCON2_Bits.DSCRATCH_SZE */
+#define IFX_CPU_DCON2_DSCRATCH_SZE_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CPU_DCON2_Bits.DSCRATCH_SZE */
+#define IFX_CPU_DCON2_DSCRATCH_SZE_OFF (16u)
+
+/** \brief Length for Ifx_CPU_DCX_Bits.DCXValue */
+#define IFX_CPU_DCX_DCXVALUE_LEN (26u)
+
+/** \brief Mask for Ifx_CPU_DCX_Bits.DCXValue */
+#define IFX_CPU_DCX_DCXVALUE_MSK (0x3ffffffu)
+
+/** \brief Offset for Ifx_CPU_DCX_Bits.DCXValue */
+#define IFX_CPU_DCX_DCXVALUE_OFF (6u)
+
+/** \brief Length for Ifx_CPU_DEADD_Bits.ERROR_ADDRESS */
+#define IFX_CPU_DEADD_ERROR_ADDRESS_LEN (32u)
+
+/** \brief Mask for Ifx_CPU_DEADD_Bits.ERROR_ADDRESS */
+#define IFX_CPU_DEADD_ERROR_ADDRESS_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_CPU_DEADD_Bits.ERROR_ADDRESS */
+#define IFX_CPU_DEADD_ERROR_ADDRESS_OFF (0u)
+
+/** \brief Length for Ifx_CPU_DIEAR_Bits.TA */
+#define IFX_CPU_DIEAR_TA_LEN (32u)
+
+/** \brief Mask for Ifx_CPU_DIEAR_Bits.TA */
+#define IFX_CPU_DIEAR_TA_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_CPU_DIEAR_Bits.TA */
+#define IFX_CPU_DIEAR_TA_OFF (0u)
+
+/** \brief Length for Ifx_CPU_DIETR_Bits.E_INFO */
+#define IFX_CPU_DIETR_E_INFO_LEN (6u)
+
+/** \brief Mask for Ifx_CPU_DIETR_Bits.E_INFO */
+#define IFX_CPU_DIETR_E_INFO_MSK (0x3fu)
+
+/** \brief Offset for Ifx_CPU_DIETR_Bits.E_INFO */
+#define IFX_CPU_DIETR_E_INFO_OFF (5u)
+
+/** \brief Length for Ifx_CPU_DIETR_Bits.IE_BI */
+#define IFX_CPU_DIETR_IE_BI_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DIETR_Bits.IE_BI */
+#define IFX_CPU_DIETR_IE_BI_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DIETR_Bits.IE_BI */
+#define IFX_CPU_DIETR_IE_BI_OFF (4u)
+
+/** \brief Length for Ifx_CPU_DIETR_Bits.IE_BS */
+#define IFX_CPU_DIETR_IE_BS_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DIETR_Bits.IE_BS */
+#define IFX_CPU_DIETR_IE_BS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DIETR_Bits.IE_BS */
+#define IFX_CPU_DIETR_IE_BS_OFF (13u)
+
+/** \brief Length for Ifx_CPU_DIETR_Bits.IE_C */
+#define IFX_CPU_DIETR_IE_C_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DIETR_Bits.IE_C */
+#define IFX_CPU_DIETR_IE_C_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DIETR_Bits.IE_C */
+#define IFX_CPU_DIETR_IE_C_OFF (2u)
+
+/** \brief Length for Ifx_CPU_DIETR_Bits.IE_DUAL */
+#define IFX_CPU_DIETR_IE_DUAL_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DIETR_Bits.IE_DUAL */
+#define IFX_CPU_DIETR_IE_DUAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DIETR_Bits.IE_DUAL */
+#define IFX_CPU_DIETR_IE_DUAL_OFF (11u)
+
+/** \brief Length for Ifx_CPU_DIETR_Bits.IE_S */
+#define IFX_CPU_DIETR_IE_S_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DIETR_Bits.IE_S */
+#define IFX_CPU_DIETR_IE_S_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DIETR_Bits.IE_S */
+#define IFX_CPU_DIETR_IE_S_OFF (3u)
+
+/** \brief Length for Ifx_CPU_DIETR_Bits.IE_SP */
+#define IFX_CPU_DIETR_IE_SP_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DIETR_Bits.IE_SP */
+#define IFX_CPU_DIETR_IE_SP_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DIETR_Bits.IE_SP */
+#define IFX_CPU_DIETR_IE_SP_OFF (12u)
+
+/** \brief Length for Ifx_CPU_DIETR_Bits.IE_T */
+#define IFX_CPU_DIETR_IE_T_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DIETR_Bits.IE_T */
+#define IFX_CPU_DIETR_IE_T_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DIETR_Bits.IE_T */
+#define IFX_CPU_DIETR_IE_T_OFF (1u)
+
+/** \brief Length for Ifx_CPU_DIETR_Bits.IED */
+#define IFX_CPU_DIETR_IED_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DIETR_Bits.IED */
+#define IFX_CPU_DIETR_IED_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DIETR_Bits.IED */
+#define IFX_CPU_DIETR_IED_OFF (0u)
+
+/** \brief Length for Ifx_CPU_DMS_Bits.DMSValue */
+#define IFX_CPU_DMS_DMSVALUE_LEN (31u)
+
+/** \brief Mask for Ifx_CPU_DMS_Bits.DMSValue */
+#define IFX_CPU_DMS_DMSVALUE_MSK (0x7fffffffu)
+
+/** \brief Offset for Ifx_CPU_DMS_Bits.DMSValue */
+#define IFX_CPU_DMS_DMSVALUE_OFF (1u)
+
+/** \brief Length for Ifx_CPU_DPR_L_Bits.LOWBND */
+#define IFX_CPU_DPR_L_LOWBND_LEN (29u)
+
+/** \brief Mask for Ifx_CPU_DPR_L_Bits.LOWBND */
+#define IFX_CPU_DPR_L_LOWBND_MSK (0x1fffffffu)
+
+/** \brief Offset for Ifx_CPU_DPR_L_Bits.LOWBND */
+#define IFX_CPU_DPR_L_LOWBND_OFF (3u)
+
+/** \brief Length for Ifx_CPU_DPR_U_Bits.UPPBND */
+#define IFX_CPU_DPR_U_UPPBND_LEN (29u)
+
+/** \brief Mask for Ifx_CPU_DPR_U_Bits.UPPBND */
+#define IFX_CPU_DPR_U_UPPBND_MSK (0x1fffffffu)
+
+/** \brief Offset for Ifx_CPU_DPR_U_Bits.UPPBND */
+#define IFX_CPU_DPR_U_UPPBND_OFF (3u)
+
+/** \brief Length for Ifx_CPU_DPRE_Bits.RE */
+#define IFX_CPU_DPRE_RE_LEN (16u)
+
+/** \brief Mask for Ifx_CPU_DPRE_Bits.RE */
+#define IFX_CPU_DPRE_RE_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CPU_DPRE_Bits.RE */
+#define IFX_CPU_DPRE_RE_OFF (0u)
+
+/** \brief Length for Ifx_CPU_DPWE_Bits.WE */
+#define IFX_CPU_DPWE_WE_LEN (16u)
+
+/** \brief Mask for Ifx_CPU_DPWE_Bits.WE */
+#define IFX_CPU_DPWE_WE_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CPU_DPWE_Bits.WE */
+#define IFX_CPU_DPWE_WE_OFF (0u)
+
+/** \brief Length for Ifx_CPU_DSTR_Bits.ALN */
+#define IFX_CPU_DSTR_ALN_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DSTR_Bits.ALN */
+#define IFX_CPU_DSTR_ALN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DSTR_Bits.ALN */
+#define IFX_CPU_DSTR_ALN_OFF (24u)
+
+/** \brief Length for Ifx_CPU_DSTR_Bits.CAC */
+#define IFX_CPU_DSTR_CAC_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DSTR_Bits.CAC */
+#define IFX_CPU_DSTR_CAC_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DSTR_Bits.CAC */
+#define IFX_CPU_DSTR_CAC_OFF (18u)
+
+/** \brief Length for Ifx_CPU_DSTR_Bits.CLE */
+#define IFX_CPU_DSTR_CLE_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DSTR_Bits.CLE */
+#define IFX_CPU_DSTR_CLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DSTR_Bits.CLE */
+#define IFX_CPU_DSTR_CLE_OFF (20u)
+
+/** \brief Length for Ifx_CPU_DSTR_Bits.CRE */
+#define IFX_CPU_DSTR_CRE_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DSTR_Bits.CRE */
+#define IFX_CPU_DSTR_CRE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DSTR_Bits.CRE */
+#define IFX_CPU_DSTR_CRE_OFF (6u)
+
+/** \brief Length for Ifx_CPU_DSTR_Bits.DTME */
+#define IFX_CPU_DSTR_DTME_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DSTR_Bits.DTME */
+#define IFX_CPU_DSTR_DTME_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DSTR_Bits.DTME */
+#define IFX_CPU_DSTR_DTME_OFF (14u)
+
+/** \brief Length for Ifx_CPU_DSTR_Bits.GAE */
+#define IFX_CPU_DSTR_GAE_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DSTR_Bits.GAE */
+#define IFX_CPU_DSTR_GAE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DSTR_Bits.GAE */
+#define IFX_CPU_DSTR_GAE_OFF (1u)
+
+/** \brief Length for Ifx_CPU_DSTR_Bits.LBE */
+#define IFX_CPU_DSTR_LBE_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DSTR_Bits.LBE */
+#define IFX_CPU_DSTR_LBE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DSTR_Bits.LBE */
+#define IFX_CPU_DSTR_LBE_OFF (2u)
+
+/** \brief Length for Ifx_CPU_DSTR_Bits.LOE */
+#define IFX_CPU_DSTR_LOE_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DSTR_Bits.LOE */
+#define IFX_CPU_DSTR_LOE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DSTR_Bits.LOE */
+#define IFX_CPU_DSTR_LOE_OFF (15u)
+
+/** \brief Length for Ifx_CPU_DSTR_Bits.MPE */
+#define IFX_CPU_DSTR_MPE_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DSTR_Bits.MPE */
+#define IFX_CPU_DSTR_MPE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DSTR_Bits.MPE */
+#define IFX_CPU_DSTR_MPE_OFF (19u)
+
+/** \brief Length for Ifx_CPU_DSTR_Bits.SCE */
+#define IFX_CPU_DSTR_SCE_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DSTR_Bits.SCE */
+#define IFX_CPU_DSTR_SCE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DSTR_Bits.SCE */
+#define IFX_CPU_DSTR_SCE_OFF (17u)
+
+/** \brief Length for Ifx_CPU_DSTR_Bits.SDE */
+#define IFX_CPU_DSTR_SDE_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DSTR_Bits.SDE */
+#define IFX_CPU_DSTR_SDE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DSTR_Bits.SDE */
+#define IFX_CPU_DSTR_SDE_OFF (16u)
+
+/** \brief Length for Ifx_CPU_DSTR_Bits.SRE */
+#define IFX_CPU_DSTR_SRE_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_DSTR_Bits.SRE */
+#define IFX_CPU_DSTR_SRE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_DSTR_Bits.SRE */
+#define IFX_CPU_DSTR_SRE_OFF (0u)
+
+/** \brief Length for Ifx_CPU_EXEVT_Bits.BBM */
+#define IFX_CPU_EXEVT_BBM_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_EXEVT_Bits.BBM */
+#define IFX_CPU_EXEVT_BBM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_EXEVT_Bits.BBM */
+#define IFX_CPU_EXEVT_BBM_OFF (3u)
+
+/** \brief Length for Ifx_CPU_EXEVT_Bits.BOD */
+#define IFX_CPU_EXEVT_BOD_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_EXEVT_Bits.BOD */
+#define IFX_CPU_EXEVT_BOD_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_EXEVT_Bits.BOD */
+#define IFX_CPU_EXEVT_BOD_OFF (4u)
+
+/** \brief Length for Ifx_CPU_EXEVT_Bits.CNT */
+#define IFX_CPU_EXEVT_CNT_LEN (2u)
+
+/** \brief Mask for Ifx_CPU_EXEVT_Bits.CNT */
+#define IFX_CPU_EXEVT_CNT_MSK (0x3u)
+
+/** \brief Offset for Ifx_CPU_EXEVT_Bits.CNT */
+#define IFX_CPU_EXEVT_CNT_OFF (6u)
+
+/** \brief Length for Ifx_CPU_EXEVT_Bits.EVTA */
+#define IFX_CPU_EXEVT_EVTA_LEN (3u)
+
+/** \brief Mask for Ifx_CPU_EXEVT_Bits.EVTA */
+#define IFX_CPU_EXEVT_EVTA_MSK (0x7u)
+
+/** \brief Offset for Ifx_CPU_EXEVT_Bits.EVTA */
+#define IFX_CPU_EXEVT_EVTA_OFF (0u)
+
+/** \brief Length for Ifx_CPU_EXEVT_Bits.SUSP */
+#define IFX_CPU_EXEVT_SUSP_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_EXEVT_Bits.SUSP */
+#define IFX_CPU_EXEVT_SUSP_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_EXEVT_Bits.SUSP */
+#define IFX_CPU_EXEVT_SUSP_OFF (5u)
+
+/** \brief Length for Ifx_CPU_FCX_Bits.FCXO */
+#define IFX_CPU_FCX_FCXO_LEN (16u)
+
+/** \brief Mask for Ifx_CPU_FCX_Bits.FCXO */
+#define IFX_CPU_FCX_FCXO_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CPU_FCX_Bits.FCXO */
+#define IFX_CPU_FCX_FCXO_OFF (0u)
+
+/** \brief Length for Ifx_CPU_FCX_Bits.FCXS */
+#define IFX_CPU_FCX_FCXS_LEN (4u)
+
+/** \brief Mask for Ifx_CPU_FCX_Bits.FCXS */
+#define IFX_CPU_FCX_FCXS_MSK (0xfu)
+
+/** \brief Offset for Ifx_CPU_FCX_Bits.FCXS */
+#define IFX_CPU_FCX_FCXS_OFF (16u)
+
+/** \brief Length for Ifx_CPU_FPU_TRAP_CON_Bits.FI */
+#define IFX_CPU_FPU_TRAP_CON_FI_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_FPU_TRAP_CON_Bits.FI */
+#define IFX_CPU_FPU_TRAP_CON_FI_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_FPU_TRAP_CON_Bits.FI */
+#define IFX_CPU_FPU_TRAP_CON_FI_OFF (30u)
+
+/** \brief Length for Ifx_CPU_FPU_TRAP_CON_Bits.FIE */
+#define IFX_CPU_FPU_TRAP_CON_FIE_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_FPU_TRAP_CON_Bits.FIE */
+#define IFX_CPU_FPU_TRAP_CON_FIE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_FPU_TRAP_CON_Bits.FIE */
+#define IFX_CPU_FPU_TRAP_CON_FIE_OFF (22u)
+
+/** \brief Length for Ifx_CPU_FPU_TRAP_CON_Bits.FU */
+#define IFX_CPU_FPU_TRAP_CON_FU_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_FPU_TRAP_CON_Bits.FU */
+#define IFX_CPU_FPU_TRAP_CON_FU_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_FPU_TRAP_CON_Bits.FU */
+#define IFX_CPU_FPU_TRAP_CON_FU_OFF (27u)
+
+/** \brief Length for Ifx_CPU_FPU_TRAP_CON_Bits.FUE */
+#define IFX_CPU_FPU_TRAP_CON_FUE_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_FPU_TRAP_CON_Bits.FUE */
+#define IFX_CPU_FPU_TRAP_CON_FUE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_FPU_TRAP_CON_Bits.FUE */
+#define IFX_CPU_FPU_TRAP_CON_FUE_OFF (19u)
+
+/** \brief Length for Ifx_CPU_FPU_TRAP_CON_Bits.FV */
+#define IFX_CPU_FPU_TRAP_CON_FV_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_FPU_TRAP_CON_Bits.FV */
+#define IFX_CPU_FPU_TRAP_CON_FV_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_FPU_TRAP_CON_Bits.FV */
+#define IFX_CPU_FPU_TRAP_CON_FV_OFF (29u)
+
+/** \brief Length for Ifx_CPU_FPU_TRAP_CON_Bits.FVE */
+#define IFX_CPU_FPU_TRAP_CON_FVE_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_FPU_TRAP_CON_Bits.FVE */
+#define IFX_CPU_FPU_TRAP_CON_FVE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_FPU_TRAP_CON_Bits.FVE */
+#define IFX_CPU_FPU_TRAP_CON_FVE_OFF (21u)
+
+/** \brief Length for Ifx_CPU_FPU_TRAP_CON_Bits.FX */
+#define IFX_CPU_FPU_TRAP_CON_FX_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_FPU_TRAP_CON_Bits.FX */
+#define IFX_CPU_FPU_TRAP_CON_FX_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_FPU_TRAP_CON_Bits.FX */
+#define IFX_CPU_FPU_TRAP_CON_FX_OFF (26u)
+
+/** \brief Length for Ifx_CPU_FPU_TRAP_CON_Bits.FXE */
+#define IFX_CPU_FPU_TRAP_CON_FXE_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_FPU_TRAP_CON_Bits.FXE */
+#define IFX_CPU_FPU_TRAP_CON_FXE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_FPU_TRAP_CON_Bits.FXE */
+#define IFX_CPU_FPU_TRAP_CON_FXE_OFF (18u)
+
+/** \brief Length for Ifx_CPU_FPU_TRAP_CON_Bits.FZ */
+#define IFX_CPU_FPU_TRAP_CON_FZ_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_FPU_TRAP_CON_Bits.FZ */
+#define IFX_CPU_FPU_TRAP_CON_FZ_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_FPU_TRAP_CON_Bits.FZ */
+#define IFX_CPU_FPU_TRAP_CON_FZ_OFF (28u)
+
+/** \brief Length for Ifx_CPU_FPU_TRAP_CON_Bits.FZE */
+#define IFX_CPU_FPU_TRAP_CON_FZE_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_FPU_TRAP_CON_Bits.FZE */
+#define IFX_CPU_FPU_TRAP_CON_FZE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_FPU_TRAP_CON_Bits.FZE */
+#define IFX_CPU_FPU_TRAP_CON_FZE_OFF (20u)
+
+/** \brief Length for Ifx_CPU_FPU_TRAP_CON_Bits.RM */
+#define IFX_CPU_FPU_TRAP_CON_RM_LEN (2u)
+
+/** \brief Mask for Ifx_CPU_FPU_TRAP_CON_Bits.RM */
+#define IFX_CPU_FPU_TRAP_CON_RM_MSK (0x3u)
+
+/** \brief Offset for Ifx_CPU_FPU_TRAP_CON_Bits.RM */
+#define IFX_CPU_FPU_TRAP_CON_RM_OFF (8u)
+
+/** \brief Length for Ifx_CPU_FPU_TRAP_CON_Bits.TCL */
+#define IFX_CPU_FPU_TRAP_CON_TCL_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_FPU_TRAP_CON_Bits.TCL */
+#define IFX_CPU_FPU_TRAP_CON_TCL_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_FPU_TRAP_CON_Bits.TCL */
+#define IFX_CPU_FPU_TRAP_CON_TCL_OFF (1u)
+
+/** \brief Length for Ifx_CPU_FPU_TRAP_CON_Bits.TST */
+#define IFX_CPU_FPU_TRAP_CON_TST_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_FPU_TRAP_CON_Bits.TST */
+#define IFX_CPU_FPU_TRAP_CON_TST_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_FPU_TRAP_CON_Bits.TST */
+#define IFX_CPU_FPU_TRAP_CON_TST_OFF (0u)
+
+/** \brief Length for Ifx_CPU_FPU_TRAP_OPC_Bits.DREG */
+#define IFX_CPU_FPU_TRAP_OPC_DREG_LEN (4u)
+
+/** \brief Mask for Ifx_CPU_FPU_TRAP_OPC_Bits.DREG */
+#define IFX_CPU_FPU_TRAP_OPC_DREG_MSK (0xfu)
+
+/** \brief Offset for Ifx_CPU_FPU_TRAP_OPC_Bits.DREG */
+#define IFX_CPU_FPU_TRAP_OPC_DREG_OFF (16u)
+
+/** \brief Length for Ifx_CPU_FPU_TRAP_OPC_Bits.FMT */
+#define IFX_CPU_FPU_TRAP_OPC_FMT_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_FPU_TRAP_OPC_Bits.FMT */
+#define IFX_CPU_FPU_TRAP_OPC_FMT_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_FPU_TRAP_OPC_Bits.FMT */
+#define IFX_CPU_FPU_TRAP_OPC_FMT_OFF (8u)
+
+/** \brief Length for Ifx_CPU_FPU_TRAP_OPC_Bits.OPC */
+#define IFX_CPU_FPU_TRAP_OPC_OPC_LEN (8u)
+
+/** \brief Mask for Ifx_CPU_FPU_TRAP_OPC_Bits.OPC */
+#define IFX_CPU_FPU_TRAP_OPC_OPC_MSK (0xffu)
+
+/** \brief Offset for Ifx_CPU_FPU_TRAP_OPC_Bits.OPC */
+#define IFX_CPU_FPU_TRAP_OPC_OPC_OFF (0u)
+
+/** \brief Length for Ifx_CPU_FPU_TRAP_PC_Bits.PC */
+#define IFX_CPU_FPU_TRAP_PC_PC_LEN (32u)
+
+/** \brief Mask for Ifx_CPU_FPU_TRAP_PC_Bits.PC */
+#define IFX_CPU_FPU_TRAP_PC_PC_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_CPU_FPU_TRAP_PC_Bits.PC */
+#define IFX_CPU_FPU_TRAP_PC_PC_OFF (0u)
+
+/** \brief Length for Ifx_CPU_FPU_TRAP_SRC1_Bits.SRC1 */
+#define IFX_CPU_FPU_TRAP_SRC1_SRC1_LEN (32u)
+
+/** \brief Mask for Ifx_CPU_FPU_TRAP_SRC1_Bits.SRC1 */
+#define IFX_CPU_FPU_TRAP_SRC1_SRC1_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_CPU_FPU_TRAP_SRC1_Bits.SRC1 */
+#define IFX_CPU_FPU_TRAP_SRC1_SRC1_OFF (0u)
+
+/** \brief Length for Ifx_CPU_FPU_TRAP_SRC2_Bits.SRC2 */
+#define IFX_CPU_FPU_TRAP_SRC2_SRC2_LEN (32u)
+
+/** \brief Mask for Ifx_CPU_FPU_TRAP_SRC2_Bits.SRC2 */
+#define IFX_CPU_FPU_TRAP_SRC2_SRC2_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_CPU_FPU_TRAP_SRC2_Bits.SRC2 */
+#define IFX_CPU_FPU_TRAP_SRC2_SRC2_OFF (0u)
+
+/** \brief Length for Ifx_CPU_FPU_TRAP_SRC3_Bits.SRC3 */
+#define IFX_CPU_FPU_TRAP_SRC3_SRC3_LEN (32u)
+
+/** \brief Mask for Ifx_CPU_FPU_TRAP_SRC3_Bits.SRC3 */
+#define IFX_CPU_FPU_TRAP_SRC3_SRC3_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_CPU_FPU_TRAP_SRC3_Bits.SRC3 */
+#define IFX_CPU_FPU_TRAP_SRC3_SRC3_OFF (0u)
+
+/** \brief Length for Ifx_CPU_ICNT_Bits.CountValue */
+#define IFX_CPU_ICNT_COUNTVALUE_LEN (31u)
+
+/** \brief Mask for Ifx_CPU_ICNT_Bits.CountValue */
+#define IFX_CPU_ICNT_COUNTVALUE_MSK (0x7fffffffu)
+
+/** \brief Offset for Ifx_CPU_ICNT_Bits.CountValue */
+#define IFX_CPU_ICNT_COUNTVALUE_OFF (0u)
+
+/** \brief Length for Ifx_CPU_ICNT_Bits.SOvf */
+#define IFX_CPU_ICNT_SOVF_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_ICNT_Bits.SOvf */
+#define IFX_CPU_ICNT_SOVF_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_ICNT_Bits.SOvf */
+#define IFX_CPU_ICNT_SOVF_OFF (31u)
+
+/** \brief Length for Ifx_CPU_ICR_Bits.CCPN */
+#define IFX_CPU_ICR_CCPN_LEN (10u)
+
+/** \brief Mask for Ifx_CPU_ICR_Bits.CCPN */
+#define IFX_CPU_ICR_CCPN_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_CPU_ICR_Bits.CCPN */
+#define IFX_CPU_ICR_CCPN_OFF (0u)
+
+/** \brief Length for Ifx_CPU_ICR_Bits.IE */
+#define IFX_CPU_ICR_IE_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_ICR_Bits.IE */
+#define IFX_CPU_ICR_IE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_ICR_Bits.IE */
+#define IFX_CPU_ICR_IE_OFF (15u)
+
+/** \brief Length for Ifx_CPU_ICR_Bits.PIPN */
+#define IFX_CPU_ICR_PIPN_LEN (10u)
+
+/** \brief Mask for Ifx_CPU_ICR_Bits.PIPN */
+#define IFX_CPU_ICR_PIPN_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_CPU_ICR_Bits.PIPN */
+#define IFX_CPU_ICR_PIPN_OFF (16u)
+
+/** \brief Length for Ifx_CPU_ISP_Bits.ISP */
+#define IFX_CPU_ISP_ISP_LEN (32u)
+
+/** \brief Mask for Ifx_CPU_ISP_Bits.ISP */
+#define IFX_CPU_ISP_ISP_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_CPU_ISP_Bits.ISP */
+#define IFX_CPU_ISP_ISP_OFF (0u)
+
+/** \brief Length for Ifx_CPU_LCX_Bits.LCXO */
+#define IFX_CPU_LCX_LCXO_LEN (16u)
+
+/** \brief Mask for Ifx_CPU_LCX_Bits.LCXO */
+#define IFX_CPU_LCX_LCXO_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CPU_LCX_Bits.LCXO */
+#define IFX_CPU_LCX_LCXO_OFF (0u)
+
+/** \brief Length for Ifx_CPU_LCX_Bits.LCXS */
+#define IFX_CPU_LCX_LCXS_LEN (4u)
+
+/** \brief Mask for Ifx_CPU_LCX_Bits.LCXS */
+#define IFX_CPU_LCX_LCXS_MSK (0xfu)
+
+/** \brief Offset for Ifx_CPU_LCX_Bits.LCXS */
+#define IFX_CPU_LCX_LCXS_OFF (16u)
+
+/** \brief Length for Ifx_CPU_M1CNT_Bits.CountValue */
+#define IFX_CPU_M1CNT_COUNTVALUE_LEN (31u)
+
+/** \brief Mask for Ifx_CPU_M1CNT_Bits.CountValue */
+#define IFX_CPU_M1CNT_COUNTVALUE_MSK (0x7fffffffu)
+
+/** \brief Offset for Ifx_CPU_M1CNT_Bits.CountValue */
+#define IFX_CPU_M1CNT_COUNTVALUE_OFF (0u)
+
+/** \brief Length for Ifx_CPU_M1CNT_Bits.SOvf */
+#define IFX_CPU_M1CNT_SOVF_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_M1CNT_Bits.SOvf */
+#define IFX_CPU_M1CNT_SOVF_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_M1CNT_Bits.SOvf */
+#define IFX_CPU_M1CNT_SOVF_OFF (31u)
+
+/** \brief Length for Ifx_CPU_M2CNT_Bits.CountValue */
+#define IFX_CPU_M2CNT_COUNTVALUE_LEN (31u)
+
+/** \brief Mask for Ifx_CPU_M2CNT_Bits.CountValue */
+#define IFX_CPU_M2CNT_COUNTVALUE_MSK (0x7fffffffu)
+
+/** \brief Offset for Ifx_CPU_M2CNT_Bits.CountValue */
+#define IFX_CPU_M2CNT_COUNTVALUE_OFF (0u)
+
+/** \brief Length for Ifx_CPU_M2CNT_Bits.SOvf */
+#define IFX_CPU_M2CNT_SOVF_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_M2CNT_Bits.SOvf */
+#define IFX_CPU_M2CNT_SOVF_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_M2CNT_Bits.SOvf */
+#define IFX_CPU_M2CNT_SOVF_OFF (31u)
+
+/** \brief Length for Ifx_CPU_M3CNT_Bits.CountValue */
+#define IFX_CPU_M3CNT_COUNTVALUE_LEN (31u)
+
+/** \brief Mask for Ifx_CPU_M3CNT_Bits.CountValue */
+#define IFX_CPU_M3CNT_COUNTVALUE_MSK (0x7fffffffu)
+
+/** \brief Offset for Ifx_CPU_M3CNT_Bits.CountValue */
+#define IFX_CPU_M3CNT_COUNTVALUE_OFF (0u)
+
+/** \brief Length for Ifx_CPU_M3CNT_Bits.SOvf */
+#define IFX_CPU_M3CNT_SOVF_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_M3CNT_Bits.SOvf */
+#define IFX_CPU_M3CNT_SOVF_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_M3CNT_Bits.SOvf */
+#define IFX_CPU_M3CNT_SOVF_OFF (31u)
+
+/** \brief Length for Ifx_CPU_PC_Bits.PC */
+#define IFX_CPU_PC_PC_LEN (31u)
+
+/** \brief Mask for Ifx_CPU_PC_Bits.PC */
+#define IFX_CPU_PC_PC_MSK (0x7fffffffu)
+
+/** \brief Offset for Ifx_CPU_PC_Bits.PC */
+#define IFX_CPU_PC_PC_OFF (1u)
+
+/** \brief Length for Ifx_CPU_PCON0_Bits.PCBYP */
+#define IFX_CPU_PCON0_PCBYP_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_PCON0_Bits.PCBYP */
+#define IFX_CPU_PCON0_PCBYP_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_PCON0_Bits.PCBYP */
+#define IFX_CPU_PCON0_PCBYP_OFF (1u)
+
+/** \brief Length for Ifx_CPU_PCON1_Bits.PBINV */
+#define IFX_CPU_PCON1_PBINV_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_PCON1_Bits.PBINV */
+#define IFX_CPU_PCON1_PBINV_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_PCON1_Bits.PBINV */
+#define IFX_CPU_PCON1_PBINV_OFF (1u)
+
+/** \brief Length for Ifx_CPU_PCON1_Bits.PCINV */
+#define IFX_CPU_PCON1_PCINV_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_PCON1_Bits.PCINV */
+#define IFX_CPU_PCON1_PCINV_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_PCON1_Bits.PCINV */
+#define IFX_CPU_PCON1_PCINV_OFF (0u)
+
+/** \brief Length for Ifx_CPU_PCON2_Bits.PCACHE_SZE */
+#define IFX_CPU_PCON2_PCACHE_SZE_LEN (16u)
+
+/** \brief Mask for Ifx_CPU_PCON2_Bits.PCACHE_SZE */
+#define IFX_CPU_PCON2_PCACHE_SZE_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CPU_PCON2_Bits.PCACHE_SZE */
+#define IFX_CPU_PCON2_PCACHE_SZE_OFF (0u)
+
+/** \brief Length for Ifx_CPU_PCON2_Bits.PSCRATCH_SZE */
+#define IFX_CPU_PCON2_PSCRATCH_SZE_LEN (16u)
+
+/** \brief Mask for Ifx_CPU_PCON2_Bits.PSCRATCH_SZE */
+#define IFX_CPU_PCON2_PSCRATCH_SZE_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CPU_PCON2_Bits.PSCRATCH_SZE */
+#define IFX_CPU_PCON2_PSCRATCH_SZE_OFF (16u)
+
+/** \brief Length for Ifx_CPU_PCXI_Bits.PCPN */
+#define IFX_CPU_PCXI_PCPN_LEN (10u)
+
+/** \brief Mask for Ifx_CPU_PCXI_Bits.PCPN */
+#define IFX_CPU_PCXI_PCPN_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_CPU_PCXI_Bits.PCPN */
+#define IFX_CPU_PCXI_PCPN_OFF (22u)
+
+/** \brief Length for Ifx_CPU_PCXI_Bits.PCXO */
+#define IFX_CPU_PCXI_PCXO_LEN (16u)
+
+/** \brief Mask for Ifx_CPU_PCXI_Bits.PCXO */
+#define IFX_CPU_PCXI_PCXO_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CPU_PCXI_Bits.PCXO */
+#define IFX_CPU_PCXI_PCXO_OFF (0u)
+
+/** \brief Length for Ifx_CPU_PCXI_Bits.PCXS */
+#define IFX_CPU_PCXI_PCXS_LEN (4u)
+
+/** \brief Mask for Ifx_CPU_PCXI_Bits.PCXS */
+#define IFX_CPU_PCXI_PCXS_MSK (0xfu)
+
+/** \brief Offset for Ifx_CPU_PCXI_Bits.PCXS */
+#define IFX_CPU_PCXI_PCXS_OFF (16u)
+
+/** \brief Length for Ifx_CPU_PCXI_Bits.PIE */
+#define IFX_CPU_PCXI_PIE_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_PCXI_Bits.PIE */
+#define IFX_CPU_PCXI_PIE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_PCXI_Bits.PIE */
+#define IFX_CPU_PCXI_PIE_OFF (21u)
+
+/** \brief Length for Ifx_CPU_PCXI_Bits.UL */
+#define IFX_CPU_PCXI_UL_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_PCXI_Bits.UL */
+#define IFX_CPU_PCXI_UL_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_PCXI_Bits.UL */
+#define IFX_CPU_PCXI_UL_OFF (20u)
+
+/** \brief Length for Ifx_CPU_PIEAR_Bits.TA */
+#define IFX_CPU_PIEAR_TA_LEN (32u)
+
+/** \brief Mask for Ifx_CPU_PIEAR_Bits.TA */
+#define IFX_CPU_PIEAR_TA_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_CPU_PIEAR_Bits.TA */
+#define IFX_CPU_PIEAR_TA_OFF (0u)
+
+/** \brief Length for Ifx_CPU_PIETR_Bits.E_INFO */
+#define IFX_CPU_PIETR_E_INFO_LEN (6u)
+
+/** \brief Mask for Ifx_CPU_PIETR_Bits.E_INFO */
+#define IFX_CPU_PIETR_E_INFO_MSK (0x3fu)
+
+/** \brief Offset for Ifx_CPU_PIETR_Bits.E_INFO */
+#define IFX_CPU_PIETR_E_INFO_OFF (5u)
+
+/** \brief Length for Ifx_CPU_PIETR_Bits.IE_BI */
+#define IFX_CPU_PIETR_IE_BI_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_PIETR_Bits.IE_BI */
+#define IFX_CPU_PIETR_IE_BI_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_PIETR_Bits.IE_BI */
+#define IFX_CPU_PIETR_IE_BI_OFF (4u)
+
+/** \brief Length for Ifx_CPU_PIETR_Bits.IE_BS */
+#define IFX_CPU_PIETR_IE_BS_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_PIETR_Bits.IE_BS */
+#define IFX_CPU_PIETR_IE_BS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_PIETR_Bits.IE_BS */
+#define IFX_CPU_PIETR_IE_BS_OFF (13u)
+
+/** \brief Length for Ifx_CPU_PIETR_Bits.IE_C */
+#define IFX_CPU_PIETR_IE_C_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_PIETR_Bits.IE_C */
+#define IFX_CPU_PIETR_IE_C_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_PIETR_Bits.IE_C */
+#define IFX_CPU_PIETR_IE_C_OFF (2u)
+
+/** \brief Length for Ifx_CPU_PIETR_Bits.IE_DUAL */
+#define IFX_CPU_PIETR_IE_DUAL_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_PIETR_Bits.IE_DUAL */
+#define IFX_CPU_PIETR_IE_DUAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_PIETR_Bits.IE_DUAL */
+#define IFX_CPU_PIETR_IE_DUAL_OFF (11u)
+
+/** \brief Length for Ifx_CPU_PIETR_Bits.IE_S */
+#define IFX_CPU_PIETR_IE_S_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_PIETR_Bits.IE_S */
+#define IFX_CPU_PIETR_IE_S_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_PIETR_Bits.IE_S */
+#define IFX_CPU_PIETR_IE_S_OFF (3u)
+
+/** \brief Length for Ifx_CPU_PIETR_Bits.IE_SP */
+#define IFX_CPU_PIETR_IE_SP_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_PIETR_Bits.IE_SP */
+#define IFX_CPU_PIETR_IE_SP_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_PIETR_Bits.IE_SP */
+#define IFX_CPU_PIETR_IE_SP_OFF (12u)
+
+/** \brief Length for Ifx_CPU_PIETR_Bits.IE_T */
+#define IFX_CPU_PIETR_IE_T_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_PIETR_Bits.IE_T */
+#define IFX_CPU_PIETR_IE_T_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_PIETR_Bits.IE_T */
+#define IFX_CPU_PIETR_IE_T_OFF (1u)
+
+/** \brief Length for Ifx_CPU_PIETR_Bits.IED */
+#define IFX_CPU_PIETR_IED_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_PIETR_Bits.IED */
+#define IFX_CPU_PIETR_IED_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_PIETR_Bits.IED */
+#define IFX_CPU_PIETR_IED_OFF (0u)
+
+/** \brief Length for Ifx_CPU_PMA0_Bits.DAC */
+#define IFX_CPU_PMA0_DAC_LEN (3u)
+
+/** \brief Mask for Ifx_CPU_PMA0_Bits.DAC */
+#define IFX_CPU_PMA0_DAC_MSK (0x7u)
+
+/** \brief Offset for Ifx_CPU_PMA0_Bits.DAC */
+#define IFX_CPU_PMA0_DAC_OFF (13u)
+
+/** \brief Length for Ifx_CPU_PMA1_Bits.CAC */
+#define IFX_CPU_PMA1_CAC_LEN (2u)
+
+/** \brief Mask for Ifx_CPU_PMA1_Bits.CAC */
+#define IFX_CPU_PMA1_CAC_MSK (0x3u)
+
+/** \brief Offset for Ifx_CPU_PMA1_Bits.CAC */
+#define IFX_CPU_PMA1_CAC_OFF (14u)
+
+/** \brief Length for Ifx_CPU_PMA2_Bits.PSI */
+#define IFX_CPU_PMA2_PSI_LEN (16u)
+
+/** \brief Mask for Ifx_CPU_PMA2_Bits.PSI */
+#define IFX_CPU_PMA2_PSI_MSK (0xffffu)
+
+/** \brief Offset for Ifx_CPU_PMA2_Bits.PSI */
+#define IFX_CPU_PMA2_PSI_OFF (0u)
+
+/** \brief Length for Ifx_CPU_PSTR_Bits.FBE */
+#define IFX_CPU_PSTR_FBE_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_PSTR_Bits.FBE */
+#define IFX_CPU_PSTR_FBE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_PSTR_Bits.FBE */
+#define IFX_CPU_PSTR_FBE_OFF (2u)
+
+/** \brief Length for Ifx_CPU_PSTR_Bits.FME */
+#define IFX_CPU_PSTR_FME_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_PSTR_Bits.FME */
+#define IFX_CPU_PSTR_FME_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_PSTR_Bits.FME */
+#define IFX_CPU_PSTR_FME_OFF (14u)
+
+/** \brief Length for Ifx_CPU_PSTR_Bits.FPE */
+#define IFX_CPU_PSTR_FPE_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_PSTR_Bits.FPE */
+#define IFX_CPU_PSTR_FPE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_PSTR_Bits.FPE */
+#define IFX_CPU_PSTR_FPE_OFF (12u)
+
+/** \brief Length for Ifx_CPU_PSTR_Bits.FRE */
+#define IFX_CPU_PSTR_FRE_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_PSTR_Bits.FRE */
+#define IFX_CPU_PSTR_FRE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_PSTR_Bits.FRE */
+#define IFX_CPU_PSTR_FRE_OFF (0u)
+
+/** \brief Length for Ifx_CPU_PSW_Bits.AV */
+#define IFX_CPU_PSW_AV_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_PSW_Bits.AV */
+#define IFX_CPU_PSW_AV_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_PSW_Bits.AV */
+#define IFX_CPU_PSW_AV_OFF (28u)
+
+/** \brief Length for Ifx_CPU_PSW_Bits.C */
+#define IFX_CPU_PSW_C_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_PSW_Bits.C */
+#define IFX_CPU_PSW_C_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_PSW_Bits.C */
+#define IFX_CPU_PSW_C_OFF (31u)
+
+/** \brief Length for Ifx_CPU_PSW_Bits.CDC */
+#define IFX_CPU_PSW_CDC_LEN (7u)
+
+/** \brief Mask for Ifx_CPU_PSW_Bits.CDC */
+#define IFX_CPU_PSW_CDC_MSK (0x7fu)
+
+/** \brief Offset for Ifx_CPU_PSW_Bits.CDC */
+#define IFX_CPU_PSW_CDC_OFF (0u)
+
+/** \brief Length for Ifx_CPU_PSW_Bits.CDE */
+#define IFX_CPU_PSW_CDE_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_PSW_Bits.CDE */
+#define IFX_CPU_PSW_CDE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_PSW_Bits.CDE */
+#define IFX_CPU_PSW_CDE_OFF (7u)
+
+/** \brief Length for Ifx_CPU_PSW_Bits.GW */
+#define IFX_CPU_PSW_GW_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_PSW_Bits.GW */
+#define IFX_CPU_PSW_GW_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_PSW_Bits.GW */
+#define IFX_CPU_PSW_GW_OFF (8u)
+
+/** \brief Length for Ifx_CPU_PSW_Bits.IO */
+#define IFX_CPU_PSW_IO_LEN (2u)
+
+/** \brief Mask for Ifx_CPU_PSW_Bits.IO */
+#define IFX_CPU_PSW_IO_MSK (0x3u)
+
+/** \brief Offset for Ifx_CPU_PSW_Bits.IO */
+#define IFX_CPU_PSW_IO_OFF (10u)
+
+/** \brief Length for Ifx_CPU_PSW_Bits.IS */
+#define IFX_CPU_PSW_IS_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_PSW_Bits.IS */
+#define IFX_CPU_PSW_IS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_PSW_Bits.IS */
+#define IFX_CPU_PSW_IS_OFF (9u)
+
+/** \brief Length for Ifx_CPU_PSW_Bits.PRS */
+#define IFX_CPU_PSW_PRS_LEN (2u)
+
+/** \brief Mask for Ifx_CPU_PSW_Bits.PRS */
+#define IFX_CPU_PSW_PRS_MSK (0x3u)
+
+/** \brief Offset for Ifx_CPU_PSW_Bits.PRS */
+#define IFX_CPU_PSW_PRS_OFF (12u)
+
+/** \brief Length for Ifx_CPU_PSW_Bits.S */
+#define IFX_CPU_PSW_S_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_PSW_Bits.S */
+#define IFX_CPU_PSW_S_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_PSW_Bits.S */
+#define IFX_CPU_PSW_S_OFF (14u)
+
+/** \brief Length for Ifx_CPU_PSW_Bits.SAV */
+#define IFX_CPU_PSW_SAV_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_PSW_Bits.SAV */
+#define IFX_CPU_PSW_SAV_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_PSW_Bits.SAV */
+#define IFX_CPU_PSW_SAV_OFF (27u)
+
+/** \brief Length for Ifx_CPU_PSW_Bits.SV */
+#define IFX_CPU_PSW_SV_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_PSW_Bits.SV */
+#define IFX_CPU_PSW_SV_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_PSW_Bits.SV */
+#define IFX_CPU_PSW_SV_OFF (29u)
+
+/** \brief Length for Ifx_CPU_PSW_Bits.V */
+#define IFX_CPU_PSW_V_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_PSW_Bits.V */
+#define IFX_CPU_PSW_V_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_PSW_Bits.V */
+#define IFX_CPU_PSW_V_OFF (30u)
+
+/** \brief Length for Ifx_CPU_SEGEN_Bits.ADFLIP */
+#define IFX_CPU_SEGEN_ADFLIP_LEN (8u)
+
+/** \brief Mask for Ifx_CPU_SEGEN_Bits.ADFLIP */
+#define IFX_CPU_SEGEN_ADFLIP_MSK (0xffu)
+
+/** \brief Offset for Ifx_CPU_SEGEN_Bits.ADFLIP */
+#define IFX_CPU_SEGEN_ADFLIP_OFF (0u)
+
+/** \brief Length for Ifx_CPU_SEGEN_Bits.ADTYPE */
+#define IFX_CPU_SEGEN_ADTYPE_LEN (2u)
+
+/** \brief Mask for Ifx_CPU_SEGEN_Bits.ADTYPE */
+#define IFX_CPU_SEGEN_ADTYPE_MSK (0x3u)
+
+/** \brief Offset for Ifx_CPU_SEGEN_Bits.ADTYPE */
+#define IFX_CPU_SEGEN_ADTYPE_OFF (8u)
+
+/** \brief Length for Ifx_CPU_SEGEN_Bits.AE */
+#define IFX_CPU_SEGEN_AE_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_SEGEN_Bits.AE */
+#define IFX_CPU_SEGEN_AE_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_SEGEN_Bits.AE */
+#define IFX_CPU_SEGEN_AE_OFF (31u)
+
+/** \brief Length for Ifx_CPU_SMACON_Bits.DC */
+#define IFX_CPU_SMACON_DC_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_SMACON_Bits.DC */
+#define IFX_CPU_SMACON_DC_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_SMACON_Bits.DC */
+#define IFX_CPU_SMACON_DC_OFF (8u)
+
+/** \brief Length for Ifx_CPU_SMACON_Bits.DT */
+#define IFX_CPU_SMACON_DT_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_SMACON_Bits.DT */
+#define IFX_CPU_SMACON_DT_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_SMACON_Bits.DT */
+#define IFX_CPU_SMACON_DT_OFF (10u)
+
+/** \brief Length for Ifx_CPU_SMACON_Bits.IODT */
+#define IFX_CPU_SMACON_IODT_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_SMACON_Bits.IODT */
+#define IFX_CPU_SMACON_IODT_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_SMACON_Bits.IODT */
+#define IFX_CPU_SMACON_IODT_OFF (24u)
+
+/** \brief Length for Ifx_CPU_SMACON_Bits.PC */
+#define IFX_CPU_SMACON_PC_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_SMACON_Bits.PC */
+#define IFX_CPU_SMACON_PC_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_SMACON_Bits.PC */
+#define IFX_CPU_SMACON_PC_OFF (0u)
+
+/** \brief Length for Ifx_CPU_SMACON_Bits.PT */
+#define IFX_CPU_SMACON_PT_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_SMACON_Bits.PT */
+#define IFX_CPU_SMACON_PT_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_SMACON_Bits.PT */
+#define IFX_CPU_SMACON_PT_OFF (2u)
+
+/** \brief Length for Ifx_CPU_SPROT_ACCENA_Bits.EN */
+#define IFX_CPU_SPROT_ACCENA_EN_LEN (32u)
+
+/** \brief Mask for Ifx_CPU_SPROT_ACCENA_Bits.EN */
+#define IFX_CPU_SPROT_ACCENA_EN_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_CPU_SPROT_ACCENA_Bits.EN */
+#define IFX_CPU_SPROT_ACCENA_EN_OFF (0u)
+
+/** \brief Length for Ifx_CPU_SPROT_RGN_ACCENA_Bits.EN */
+#define IFX_CPU_SPROT_RGN_ACCENA_EN_LEN (32u)
+
+/** \brief Mask for Ifx_CPU_SPROT_RGN_ACCENA_Bits.EN */
+#define IFX_CPU_SPROT_RGN_ACCENA_EN_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_CPU_SPROT_RGN_ACCENA_Bits.EN */
+#define IFX_CPU_SPROT_RGN_ACCENA_EN_OFF (0u)
+
+/** \brief Length for Ifx_CPU_SPROT_RGN_LA_Bits.ADDR */
+#define IFX_CPU_SPROT_RGN_LA_ADDR_LEN (27u)
+
+/** \brief Mask for Ifx_CPU_SPROT_RGN_LA_Bits.ADDR */
+#define IFX_CPU_SPROT_RGN_LA_ADDR_MSK (0x7ffffffu)
+
+/** \brief Offset for Ifx_CPU_SPROT_RGN_LA_Bits.ADDR */
+#define IFX_CPU_SPROT_RGN_LA_ADDR_OFF (5u)
+
+/** \brief Length for Ifx_CPU_SPROT_RGN_UA_Bits.ADDR */
+#define IFX_CPU_SPROT_RGN_UA_ADDR_LEN (27u)
+
+/** \brief Mask for Ifx_CPU_SPROT_RGN_UA_Bits.ADDR */
+#define IFX_CPU_SPROT_RGN_UA_ADDR_MSK (0x7ffffffu)
+
+/** \brief Offset for Ifx_CPU_SPROT_RGN_UA_Bits.ADDR */
+#define IFX_CPU_SPROT_RGN_UA_ADDR_OFF (5u)
+
+/** \brief Length for Ifx_CPU_SWEVT_Bits.BBM */
+#define IFX_CPU_SWEVT_BBM_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_SWEVT_Bits.BBM */
+#define IFX_CPU_SWEVT_BBM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_SWEVT_Bits.BBM */
+#define IFX_CPU_SWEVT_BBM_OFF (3u)
+
+/** \brief Length for Ifx_CPU_SWEVT_Bits.BOD */
+#define IFX_CPU_SWEVT_BOD_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_SWEVT_Bits.BOD */
+#define IFX_CPU_SWEVT_BOD_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_SWEVT_Bits.BOD */
+#define IFX_CPU_SWEVT_BOD_OFF (4u)
+
+/** \brief Length for Ifx_CPU_SWEVT_Bits.CNT */
+#define IFX_CPU_SWEVT_CNT_LEN (2u)
+
+/** \brief Mask for Ifx_CPU_SWEVT_Bits.CNT */
+#define IFX_CPU_SWEVT_CNT_MSK (0x3u)
+
+/** \brief Offset for Ifx_CPU_SWEVT_Bits.CNT */
+#define IFX_CPU_SWEVT_CNT_OFF (6u)
+
+/** \brief Length for Ifx_CPU_SWEVT_Bits.EVTA */
+#define IFX_CPU_SWEVT_EVTA_LEN (3u)
+
+/** \brief Mask for Ifx_CPU_SWEVT_Bits.EVTA */
+#define IFX_CPU_SWEVT_EVTA_MSK (0x7u)
+
+/** \brief Offset for Ifx_CPU_SWEVT_Bits.EVTA */
+#define IFX_CPU_SWEVT_EVTA_OFF (0u)
+
+/** \brief Length for Ifx_CPU_SWEVT_Bits.SUSP */
+#define IFX_CPU_SWEVT_SUSP_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_SWEVT_Bits.SUSP */
+#define IFX_CPU_SWEVT_SUSP_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_SWEVT_Bits.SUSP */
+#define IFX_CPU_SWEVT_SUSP_OFF (5u)
+
+/** \brief Length for Ifx_CPU_SYSCON_Bits.FCDSF */
+#define IFX_CPU_SYSCON_FCDSF_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_SYSCON_Bits.FCDSF */
+#define IFX_CPU_SYSCON_FCDSF_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_SYSCON_Bits.FCDSF */
+#define IFX_CPU_SYSCON_FCDSF_OFF (0u)
+
+/** \brief Length for Ifx_CPU_SYSCON_Bits.IS */
+#define IFX_CPU_SYSCON_IS_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_SYSCON_Bits.IS */
+#define IFX_CPU_SYSCON_IS_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_SYSCON_Bits.IS */
+#define IFX_CPU_SYSCON_IS_OFF (3u)
+
+/** \brief Length for Ifx_CPU_SYSCON_Bits.IT */
+#define IFX_CPU_SYSCON_IT_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_SYSCON_Bits.IT */
+#define IFX_CPU_SYSCON_IT_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_SYSCON_Bits.IT */
+#define IFX_CPU_SYSCON_IT_OFF (4u)
+
+/** \brief Length for Ifx_CPU_SYSCON_Bits.PROTEN */
+#define IFX_CPU_SYSCON_PROTEN_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_SYSCON_Bits.PROTEN */
+#define IFX_CPU_SYSCON_PROTEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_SYSCON_Bits.PROTEN */
+#define IFX_CPU_SYSCON_PROTEN_OFF (1u)
+
+/** \brief Length for Ifx_CPU_SYSCON_Bits.TPROTEN */
+#define IFX_CPU_SYSCON_TPROTEN_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_SYSCON_Bits.TPROTEN */
+#define IFX_CPU_SYSCON_TPROTEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_SYSCON_Bits.TPROTEN */
+#define IFX_CPU_SYSCON_TPROTEN_OFF (2u)
+
+/** \brief Length for Ifx_CPU_TASK_ASI_Bits.ASI */
+#define IFX_CPU_TASK_ASI_ASI_LEN (5u)
+
+/** \brief Mask for Ifx_CPU_TASK_ASI_Bits.ASI */
+#define IFX_CPU_TASK_ASI_ASI_MSK (0x1fu)
+
+/** \brief Offset for Ifx_CPU_TASK_ASI_Bits.ASI */
+#define IFX_CPU_TASK_ASI_ASI_OFF (0u)
+
+/** \brief Length for Ifx_CPU_TPS_CON_Bits.TEXP0 */
+#define IFX_CPU_TPS_CON_TEXP0_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_TPS_CON_Bits.TEXP0 */
+#define IFX_CPU_TPS_CON_TEXP0_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_TPS_CON_Bits.TEXP0 */
+#define IFX_CPU_TPS_CON_TEXP0_OFF (0u)
+
+/** \brief Length for Ifx_CPU_TPS_CON_Bits.TEXP1 */
+#define IFX_CPU_TPS_CON_TEXP1_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_TPS_CON_Bits.TEXP1 */
+#define IFX_CPU_TPS_CON_TEXP1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_TPS_CON_Bits.TEXP1 */
+#define IFX_CPU_TPS_CON_TEXP1_OFF (1u)
+
+/** \brief Length for Ifx_CPU_TPS_CON_Bits.TEXP2 */
+#define IFX_CPU_TPS_CON_TEXP2_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_TPS_CON_Bits.TEXP2 */
+#define IFX_CPU_TPS_CON_TEXP2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_TPS_CON_Bits.TEXP2 */
+#define IFX_CPU_TPS_CON_TEXP2_OFF (2u)
+
+/** \brief Length for Ifx_CPU_TPS_CON_Bits.TTRAP */
+#define IFX_CPU_TPS_CON_TTRAP_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_TPS_CON_Bits.TTRAP */
+#define IFX_CPU_TPS_CON_TTRAP_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_TPS_CON_Bits.TTRAP */
+#define IFX_CPU_TPS_CON_TTRAP_OFF (16u)
+
+/** \brief Length for Ifx_CPU_TPS_TIMER_Bits.Timer */
+#define IFX_CPU_TPS_TIMER_TIMER_LEN (32u)
+
+/** \brief Mask for Ifx_CPU_TPS_TIMER_Bits.Timer */
+#define IFX_CPU_TPS_TIMER_TIMER_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_CPU_TPS_TIMER_Bits.Timer */
+#define IFX_CPU_TPS_TIMER_TIMER_OFF (0u)
+
+/** \brief Length for Ifx_CPU_TR_ADR_Bits.ADDR */
+#define IFX_CPU_TR_ADR_ADDR_LEN (32u)
+
+/** \brief Mask for Ifx_CPU_TR_ADR_Bits.ADDR */
+#define IFX_CPU_TR_ADR_ADDR_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_CPU_TR_ADR_Bits.ADDR */
+#define IFX_CPU_TR_ADR_ADDR_OFF (0u)
+
+/** \brief Length for Ifx_CPU_TR_EVT_Bits.ALD */
+#define IFX_CPU_TR_EVT_ALD_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_TR_EVT_Bits.ALD */
+#define IFX_CPU_TR_EVT_ALD_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_TR_EVT_Bits.ALD */
+#define IFX_CPU_TR_EVT_ALD_OFF (28u)
+
+/** \brief Length for Ifx_CPU_TR_EVT_Bits.ASI_EN */
+#define IFX_CPU_TR_EVT_ASI_EN_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_TR_EVT_Bits.ASI_EN */
+#define IFX_CPU_TR_EVT_ASI_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_TR_EVT_Bits.ASI_EN */
+#define IFX_CPU_TR_EVT_ASI_EN_OFF (15u)
+
+/** \brief Length for Ifx_CPU_TR_EVT_Bits.ASI */
+#define IFX_CPU_TR_EVT_ASI_LEN (5u)
+
+/** \brief Mask for Ifx_CPU_TR_EVT_Bits.ASI */
+#define IFX_CPU_TR_EVT_ASI_MSK (0x1fu)
+
+/** \brief Offset for Ifx_CPU_TR_EVT_Bits.ASI */
+#define IFX_CPU_TR_EVT_ASI_OFF (16u)
+
+/** \brief Length for Ifx_CPU_TR_EVT_Bits.AST */
+#define IFX_CPU_TR_EVT_AST_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_TR_EVT_Bits.AST */
+#define IFX_CPU_TR_EVT_AST_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_TR_EVT_Bits.AST */
+#define IFX_CPU_TR_EVT_AST_OFF (27u)
+
+/** \brief Length for Ifx_CPU_TR_EVT_Bits.BBM */
+#define IFX_CPU_TR_EVT_BBM_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_TR_EVT_Bits.BBM */
+#define IFX_CPU_TR_EVT_BBM_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_TR_EVT_Bits.BBM */
+#define IFX_CPU_TR_EVT_BBM_OFF (3u)
+
+/** \brief Length for Ifx_CPU_TR_EVT_Bits.BOD */
+#define IFX_CPU_TR_EVT_BOD_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_TR_EVT_Bits.BOD */
+#define IFX_CPU_TR_EVT_BOD_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_TR_EVT_Bits.BOD */
+#define IFX_CPU_TR_EVT_BOD_OFF (4u)
+
+/** \brief Length for Ifx_CPU_TR_EVT_Bits.CNT */
+#define IFX_CPU_TR_EVT_CNT_LEN (2u)
+
+/** \brief Mask for Ifx_CPU_TR_EVT_Bits.CNT */
+#define IFX_CPU_TR_EVT_CNT_MSK (0x3u)
+
+/** \brief Offset for Ifx_CPU_TR_EVT_Bits.CNT */
+#define IFX_CPU_TR_EVT_CNT_OFF (6u)
+
+/** \brief Length for Ifx_CPU_TR_EVT_Bits.EVTA */
+#define IFX_CPU_TR_EVT_EVTA_LEN (3u)
+
+/** \brief Mask for Ifx_CPU_TR_EVT_Bits.EVTA */
+#define IFX_CPU_TR_EVT_EVTA_MSK (0x7u)
+
+/** \brief Offset for Ifx_CPU_TR_EVT_Bits.EVTA */
+#define IFX_CPU_TR_EVT_EVTA_OFF (0u)
+
+/** \brief Length for Ifx_CPU_TR_EVT_Bits.RNG */
+#define IFX_CPU_TR_EVT_RNG_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_TR_EVT_Bits.RNG */
+#define IFX_CPU_TR_EVT_RNG_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_TR_EVT_Bits.RNG */
+#define IFX_CPU_TR_EVT_RNG_OFF (13u)
+
+/** \brief Length for Ifx_CPU_TR_EVT_Bits.SUSP */
+#define IFX_CPU_TR_EVT_SUSP_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_TR_EVT_Bits.SUSP */
+#define IFX_CPU_TR_EVT_SUSP_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_TR_EVT_Bits.SUSP */
+#define IFX_CPU_TR_EVT_SUSP_OFF (5u)
+
+/** \brief Length for Ifx_CPU_TR_EVT_Bits.TYP */
+#define IFX_CPU_TR_EVT_TYP_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_TR_EVT_Bits.TYP */
+#define IFX_CPU_TR_EVT_TYP_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_TR_EVT_Bits.TYP */
+#define IFX_CPU_TR_EVT_TYP_OFF (12u)
+
+/** \brief Length for Ifx_CPU_TRIG_ACC_Bits.T0 */
+#define IFX_CPU_TRIG_ACC_T0_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_TRIG_ACC_Bits.T0 */
+#define IFX_CPU_TRIG_ACC_T0_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_TRIG_ACC_Bits.T0 */
+#define IFX_CPU_TRIG_ACC_T0_OFF (0u)
+
+/** \brief Length for Ifx_CPU_TRIG_ACC_Bits.T1 */
+#define IFX_CPU_TRIG_ACC_T1_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_TRIG_ACC_Bits.T1 */
+#define IFX_CPU_TRIG_ACC_T1_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_TRIG_ACC_Bits.T1 */
+#define IFX_CPU_TRIG_ACC_T1_OFF (1u)
+
+/** \brief Length for Ifx_CPU_TRIG_ACC_Bits.T2 */
+#define IFX_CPU_TRIG_ACC_T2_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_TRIG_ACC_Bits.T2 */
+#define IFX_CPU_TRIG_ACC_T2_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_TRIG_ACC_Bits.T2 */
+#define IFX_CPU_TRIG_ACC_T2_OFF (2u)
+
+/** \brief Length for Ifx_CPU_TRIG_ACC_Bits.T3 */
+#define IFX_CPU_TRIG_ACC_T3_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_TRIG_ACC_Bits.T3 */
+#define IFX_CPU_TRIG_ACC_T3_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_TRIG_ACC_Bits.T3 */
+#define IFX_CPU_TRIG_ACC_T3_OFF (3u)
+
+/** \brief Length for Ifx_CPU_TRIG_ACC_Bits.T4 */
+#define IFX_CPU_TRIG_ACC_T4_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_TRIG_ACC_Bits.T4 */
+#define IFX_CPU_TRIG_ACC_T4_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_TRIG_ACC_Bits.T4 */
+#define IFX_CPU_TRIG_ACC_T4_OFF (4u)
+
+/** \brief Length for Ifx_CPU_TRIG_ACC_Bits.T5 */
+#define IFX_CPU_TRIG_ACC_T5_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_TRIG_ACC_Bits.T5 */
+#define IFX_CPU_TRIG_ACC_T5_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_TRIG_ACC_Bits.T5 */
+#define IFX_CPU_TRIG_ACC_T5_OFF (5u)
+
+/** \brief Length for Ifx_CPU_TRIG_ACC_Bits.T6 */
+#define IFX_CPU_TRIG_ACC_T6_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_TRIG_ACC_Bits.T6 */
+#define IFX_CPU_TRIG_ACC_T6_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_TRIG_ACC_Bits.T6 */
+#define IFX_CPU_TRIG_ACC_T6_OFF (6u)
+
+/** \brief Length for Ifx_CPU_TRIG_ACC_Bits.T7 */
+#define IFX_CPU_TRIG_ACC_T7_LEN (1u)
+
+/** \brief Mask for Ifx_CPU_TRIG_ACC_Bits.T7 */
+#define IFX_CPU_TRIG_ACC_T7_MSK (0x1u)
+
+/** \brief Offset for Ifx_CPU_TRIG_ACC_Bits.T7 */
+#define IFX_CPU_TRIG_ACC_T7_OFF (7u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXCPU_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCpu_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCpu_reg.h
new file mode 100644
index 0000000..825ccad
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCpu_reg.h
@@ -0,0 +1,2452 @@
+/**
+ * \file IfxCpu_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Cpu_Cfg Cpu address
+ * \ingroup IfxLld_Cpu
+ *
+ * \defgroup IfxLld_Cpu_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Cpu_Cfg
+ *
+ * \defgroup IfxLld_Cpu_Cfg_Cpu0 2-CPU0
+ * \ingroup IfxLld_Cpu_Cfg
+ *
+ * \defgroup IfxLld_Cpu_Cfg_Cpu1 2-CPU1
+ * \ingroup IfxLld_Cpu_Cfg
+ *
+ * \defgroup IfxLld_Cpu_Cfg_Cpu 2-CPU
+ * \ingroup IfxLld_Cpu_Cfg
+ *
+ * \defgroup IfxLld_Cpu_Cfg_Cpu0_sprot 2-CPU0_SPROT
+ * \ingroup IfxLld_Cpu_Cfg
+ *
+ * \defgroup IfxLld_Cpu_Cfg_Cpu1_sprot 2-CPU1_SPROT
+ * \ingroup IfxLld_Cpu_Cfg
+ *
+ */
+#ifndef IFXCPU_REG_H
+#define IFXCPU_REG_H 1
+/******************************************************************************/
+#include "IfxCpu_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Cpu_Cfg_BaseAddress
+ * \{ */
+
+/** \brief CPU object */
+#define MODULE_CPU0 /*lint --e(923)*/ (*(Ifx_CPU*)0xF8810000u)
+
+/** \brief CPU SPROT object */
+#define MODULE_CPU0_SPROT /*lint --e(923)*/ (*(Ifx_CPU_SPROT*)0xF8800000u)
+
+/** \brief CPU object */
+#define MODULE_CPU1 /*lint --e(923)*/ (*(Ifx_CPU*)0xF8830000u)
+
+/** \brief CPU SPROT object */
+#define MODULE_CPU1_SPROT /*lint --e(923)*/ (*(Ifx_CPU_SPROT*)0xF8820000u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Cpu_Cfg_Cpu0
+ * \{ */
+
+/** \brief FF80, Address General Purpose Register */
+#define CPU0_A0 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FF80u)
+
+/** \brief FF84, Address General Purpose Register */
+#define CPU0_A1 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FF84u)
+
+/** \brief FFA8, Address General Purpose Register */
+#define CPU0_A10 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FFA8u)
+
+/** \brief FFAC, Address General Purpose Register */
+#define CPU0_A11 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FFACu)
+
+/** \brief FFB0, Address General Purpose Register */
+#define CPU0_A12 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FFB0u)
+
+/** \brief FFB4, Address General Purpose Register */
+#define CPU0_A13 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FFB4u)
+
+/** \brief FFB8, Address General Purpose Register */
+#define CPU0_A14 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FFB8u)
+
+/** \brief FFBC, Address General Purpose Register */
+#define CPU0_A15 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FFBCu)
+
+/** \brief FF88, Address General Purpose Register */
+#define CPU0_A2 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FF88u)
+
+/** \brief FF8C, Address General Purpose Register */
+#define CPU0_A3 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FF8Cu)
+
+/** \brief FF90, Address General Purpose Register */
+#define CPU0_A4 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FF90u)
+
+/** \brief FF94, Address General Purpose Register */
+#define CPU0_A5 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FF94u)
+
+/** \brief FF98, Address General Purpose Register */
+#define CPU0_A6 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FF98u)
+
+/** \brief FF9C, Address General Purpose Register */
+#define CPU0_A7 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FF9Cu)
+
+/** \brief FFA0, Address General Purpose Register */
+#define CPU0_A8 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FFA0u)
+
+/** \brief FFA4, Address General Purpose Register */
+#define CPU0_A9 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FFA4u)
+
+/** \brief FE20, Base Interrupt Vector Table Pointer */
+#define CPU0_BIV /*lint --e(923)*/ (*(volatile Ifx_CPU_BIV*)0xF881FE20u)
+
+/** \brief FE24, Base Trap Vector Table Pointer */
+#define CPU0_BTV /*lint --e(923)*/ (*(volatile Ifx_CPU_BTV*)0xF881FE24u)
+
+/** \brief FC04, CPU Clock Cycle Count */
+#define CPU0_CCNT /*lint --e(923)*/ (*(volatile Ifx_CPU_CCNT*)0xF881FC04u)
+
+/** \brief FC00, Counter Control */
+#define CPU0_CCTRL /*lint --e(923)*/ (*(volatile Ifx_CPU_CCTRL*)0xF881FC00u)
+
+/** \brief 9400, Compatibility Control Register */
+#define CPU0_COMPAT /*lint --e(923)*/ (*(volatile Ifx_CPU_COMPAT*)0xF8819400u)
+
+/** \brief FE1C, CPU Core Identification Register */
+#define CPU0_CORE_ID /*lint --e(923)*/ (*(volatile Ifx_CPU_CORE_ID*)0xF881FE1Cu)
+
+/** \brief D000, CPU Code Protection Range Lower Bound Register */
+#define CPU0_CPR0_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF881D000u)
+
+/** \brief D004, CPU Code Protection Range Upper Bound Register */
+#define CPU0_CPR0_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF881D004u)
+
+/** \brief D008, CPU Code Protection Range Lower Bound Register */
+#define CPU0_CPR1_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF881D008u)
+
+/** \brief D00C, CPU Code Protection Range Upper Bound Register */
+#define CPU0_CPR1_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF881D00Cu)
+
+/** \brief D010, CPU Code Protection Range Lower Bound Register */
+#define CPU0_CPR2_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF881D010u)
+
+/** \brief D014, CPU Code Protection Range Upper Bound Register */
+#define CPU0_CPR2_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF881D014u)
+
+/** \brief D018, CPU Code Protection Range Lower Bound Register */
+#define CPU0_CPR3_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF881D018u)
+
+/** \brief D01C, CPU Code Protection Range Upper Bound Register */
+#define CPU0_CPR3_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF881D01Cu)
+
+/** \brief D020, CPU Code Protection Range Lower Bound Register */
+#define CPU0_CPR4_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF881D020u)
+
+/** \brief D024, CPU Code Protection Range Upper Bound Register */
+#define CPU0_CPR4_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF881D024u)
+
+/** \brief D028, CPU Code Protection Range Lower Bound Register */
+#define CPU0_CPR5_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF881D028u)
+
+/** \brief D02C, CPU Code Protection Range Upper Bound Register */
+#define CPU0_CPR5_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF881D02Cu)
+
+/** \brief D030, CPU Code Protection Range Lower Bound Register */
+#define CPU0_CPR6_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF881D030u)
+
+/** \brief D034, CPU Code Protection Range Upper Bound Register */
+#define CPU0_CPR6_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF881D034u)
+
+/** \brief D038, CPU Code Protection Range Lower Bound Register */
+#define CPU0_CPR7_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF881D038u)
+
+/** \brief D03C, CPU Code Protection Range Upper Bound Register */
+#define CPU0_CPR7_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF881D03Cu)
+
+/** \brief FE18, CPU Identification Register TC1.6P */
+#define CPU0_CPU_ID /*lint --e(923)*/ (*(volatile Ifx_CPU_CPU_ID*)0xF881FE18u)
+
+/** \brief E000, CPU Code Protection Execute Enable Register Set */
+#define CPU0_CPXE0 /*lint --e(923)*/ (*(volatile Ifx_CPU_CPXE*)0xF881E000u)
+
+/** Alias (User Manual Name) for CPU0_CPXE0.
+* To use register names with standard convension, please use CPU0_CPXE0.
+*/
+#define CPU0_CPXE_0 (CPU0_CPXE0)
+
+/** \brief E004, CPU Code Protection Execute Enable Register Set */
+#define CPU0_CPXE1 /*lint --e(923)*/ (*(volatile Ifx_CPU_CPXE*)0xF881E004u)
+
+/** Alias (User Manual Name) for CPU0_CPXE1.
+* To use register names with standard convension, please use CPU0_CPXE1.
+*/
+#define CPU0_CPXE_1 (CPU0_CPXE1)
+
+/** \brief E008, CPU Code Protection Execute Enable Register Set */
+#define CPU0_CPXE2 /*lint --e(923)*/ (*(volatile Ifx_CPU_CPXE*)0xF881E008u)
+
+/** Alias (User Manual Name) for CPU0_CPXE2.
+* To use register names with standard convension, please use CPU0_CPXE2.
+*/
+#define CPU0_CPXE_2 (CPU0_CPXE2)
+
+/** \brief E00C, CPU Code Protection Execute Enable Register Set */
+#define CPU0_CPXE3 /*lint --e(923)*/ (*(volatile Ifx_CPU_CPXE*)0xF881E00Cu)
+
+/** Alias (User Manual Name) for CPU0_CPXE3.
+* To use register names with standard convension, please use CPU0_CPXE3.
+*/
+#define CPU0_CPXE_3 (CPU0_CPXE3)
+
+/** \brief FD0C, Core Register Access Event */
+#define CPU0_CREVT /*lint --e(923)*/ (*(volatile Ifx_CPU_CREVT*)0xF881FD0Cu)
+
+/** \brief FE50, CPU Customer ID register */
+#define CPU0_CUS_ID /*lint --e(923)*/ (*(volatile Ifx_CPU_CUS_ID*)0xF881FE50u)
+
+/** \brief FF00, Data General Purpose Register */
+#define CPU0_D0 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF00u)
+
+/** \brief FF04, Data General Purpose Register */
+#define CPU0_D1 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF04u)
+
+/** \brief FF28, Data General Purpose Register */
+#define CPU0_D10 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF28u)
+
+/** \brief FF2C, Data General Purpose Register */
+#define CPU0_D11 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF2Cu)
+
+/** \brief FF30, Data General Purpose Register */
+#define CPU0_D12 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF30u)
+
+/** \brief FF34, Data General Purpose Register */
+#define CPU0_D13 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF34u)
+
+/** \brief FF38, Data General Purpose Register */
+#define CPU0_D14 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF38u)
+
+/** \brief FF3C, Data General Purpose Register */
+#define CPU0_D15 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF3Cu)
+
+/** \brief FF08, Data General Purpose Register */
+#define CPU0_D2 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF08u)
+
+/** \brief FF0C, Data General Purpose Register */
+#define CPU0_D3 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF0Cu)
+
+/** \brief FF10, Data General Purpose Register */
+#define CPU0_D4 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF10u)
+
+/** \brief FF14, Data General Purpose Register */
+#define CPU0_D5 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF14u)
+
+/** \brief FF18, Data General Purpose Register */
+#define CPU0_D6 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF18u)
+
+/** \brief FF1C, Data General Purpose Register */
+#define CPU0_D7 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF1Cu)
+
+/** \brief FF20, Data General Purpose Register */
+#define CPU0_D8 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF20u)
+
+/** \brief FF24, Data General Purpose Register */
+#define CPU0_D9 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF24u)
+
+/** \brief 9018, Data Asynchronous Trap Register */
+#define CPU0_DATR /*lint --e(923)*/ (*(volatile Ifx_CPU_DATR*)0xF8819018u)
+
+/** \brief FD00, Debug Status Register */
+#define CPU0_DBGSR /*lint --e(923)*/ (*(volatile Ifx_CPU_DBGSR*)0xF881FD00u)
+
+/** \brief FD48, Debug Trap Control Register */
+#define CPU0_DBGTCR /*lint --e(923)*/ (*(volatile Ifx_CPU_DBGTCR*)0xF881FD48u)
+
+/** \brief 9040, Data Memory Control Register */
+#define CPU0_DCON0 /*lint --e(923)*/ (*(volatile Ifx_CPU_DCON0*)0xF8819040u)
+
+/** \brief 9000, Data Control Register 2 */
+#define CPU0_DCON2 /*lint --e(923)*/ (*(volatile Ifx_CPU_DCON2*)0xF8819000u)
+
+/** \brief FD44, CPU Debug Context Save Area Pointer */
+#define CPU0_DCX /*lint --e(923)*/ (*(volatile Ifx_CPU_DCX*)0xF881FD44u)
+
+/** \brief 901C, Data Error Address Register */
+#define CPU0_DEADD /*lint --e(923)*/ (*(volatile Ifx_CPU_DEADD*)0xF881901Cu)
+
+/** \brief 9020, Data Integrity Error Address Register */
+#define CPU0_DIEAR /*lint --e(923)*/ (*(volatile Ifx_CPU_DIEAR*)0xF8819020u)
+
+/** \brief 9024, Data Integrity Error Trap Register */
+#define CPU0_DIETR /*lint --e(923)*/ (*(volatile Ifx_CPU_DIETR*)0xF8819024u)
+
+/** \brief FD40, CPU Debug Monitor Start Address */
+#define CPU0_DMS /*lint --e(923)*/ (*(volatile Ifx_CPU_DMS*)0xF881FD40u)
+
+/** \brief C000, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR0_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C000u)
+
+/** \brief C004, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR0_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C004u)
+
+/** \brief C050, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR10_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C050u)
+
+/** \brief C054, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR10_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C054u)
+
+/** \brief C058, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR11_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C058u)
+
+/** \brief C05C, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR11_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C05Cu)
+
+/** \brief C060, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR12_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C060u)
+
+/** \brief C064, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR12_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C064u)
+
+/** \brief C068, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR13_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C068u)
+
+/** \brief C06C, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR13_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C06Cu)
+
+/** \brief C070, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR14_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C070u)
+
+/** \brief C074, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR14_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C074u)
+
+/** \brief C078, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR15_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C078u)
+
+/** \brief C07C, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR15_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C07Cu)
+
+/** \brief C008, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR1_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C008u)
+
+/** \brief C00C, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR1_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C00Cu)
+
+/** \brief C010, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR2_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C010u)
+
+/** \brief C014, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR2_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C014u)
+
+/** \brief C018, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR3_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C018u)
+
+/** \brief C01C, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR3_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C01Cu)
+
+/** \brief C020, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR4_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C020u)
+
+/** \brief C024, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR4_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C024u)
+
+/** \brief C028, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR5_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C028u)
+
+/** \brief C02C, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR5_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C02Cu)
+
+/** \brief C030, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR6_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C030u)
+
+/** \brief C034, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR6_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C034u)
+
+/** \brief C038, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR7_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C038u)
+
+/** \brief C03C, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR7_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C03Cu)
+
+/** \brief C040, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR8_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C040u)
+
+/** \brief C044, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR8_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C044u)
+
+/** \brief C048, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR9_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C048u)
+
+/** \brief C04C, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR9_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C04Cu)
+
+/** \brief E010, CPU Data Protection Read Enable Register Set */
+#define CPU0_DPRE0 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPRE*)0xF881E010u)
+
+/** Alias (User Manual Name) for CPU0_DPRE0.
+* To use register names with standard convension, please use CPU0_DPRE0.
+*/
+#define CPU0_DPRE_0 (CPU0_DPRE0)
+
+/** \brief E014, CPU Data Protection Read Enable Register Set */
+#define CPU0_DPRE1 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPRE*)0xF881E014u)
+
+/** Alias (User Manual Name) for CPU0_DPRE1.
+* To use register names with standard convension, please use CPU0_DPRE1.
+*/
+#define CPU0_DPRE_1 (CPU0_DPRE1)
+
+/** \brief E018, CPU Data Protection Read Enable Register Set */
+#define CPU0_DPRE2 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPRE*)0xF881E018u)
+
+/** Alias (User Manual Name) for CPU0_DPRE2.
+* To use register names with standard convension, please use CPU0_DPRE2.
+*/
+#define CPU0_DPRE_2 (CPU0_DPRE2)
+
+/** \brief E01C, CPU Data Protection Read Enable Register Set */
+#define CPU0_DPRE3 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPRE*)0xF881E01Cu)
+
+/** Alias (User Manual Name) for CPU0_DPRE3.
+* To use register names with standard convension, please use CPU0_DPRE3.
+*/
+#define CPU0_DPRE_3 (CPU0_DPRE3)
+
+/** \brief E020, CPU Data Protection Write Enable Register Set */
+#define CPU0_DPWE0 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPWE*)0xF881E020u)
+
+/** Alias (User Manual Name) for CPU0_DPWE0.
+* To use register names with standard convension, please use CPU0_DPWE0.
+*/
+#define CPU0_DPWE_0 (CPU0_DPWE0)
+
+/** \brief E024, CPU Data Protection Write Enable Register Set */
+#define CPU0_DPWE1 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPWE*)0xF881E024u)
+
+/** Alias (User Manual Name) for CPU0_DPWE1.
+* To use register names with standard convension, please use CPU0_DPWE1.
+*/
+#define CPU0_DPWE_1 (CPU0_DPWE1)
+
+/** \brief E028, CPU Data Protection Write Enable Register Set */
+#define CPU0_DPWE2 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPWE*)0xF881E028u)
+
+/** Alias (User Manual Name) for CPU0_DPWE2.
+* To use register names with standard convension, please use CPU0_DPWE2.
+*/
+#define CPU0_DPWE_2 (CPU0_DPWE2)
+
+/** \brief E02C, CPU Data Protection Write Enable Register Set */
+#define CPU0_DPWE3 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPWE*)0xF881E02Cu)
+
+/** Alias (User Manual Name) for CPU0_DPWE3.
+* To use register names with standard convension, please use CPU0_DPWE3.
+*/
+#define CPU0_DPWE_3 (CPU0_DPWE3)
+
+/** \brief 9010, Data Synchronous Trap Register */
+#define CPU0_DSTR /*lint --e(923)*/ (*(volatile Ifx_CPU_DSTR*)0xF8819010u)
+
+/** \brief FD08, External Event Register */
+#define CPU0_EXEVT /*lint --e(923)*/ (*(volatile Ifx_CPU_EXEVT*)0xF881FD08u)
+
+/** \brief FE38, Free CSA List Head Pointer */
+#define CPU0_FCX /*lint --e(923)*/ (*(volatile Ifx_CPU_FCX*)0xF881FE38u)
+
+/** \brief A000, CPU Trap Control Register */
+#define CPU0_FPU_TRAP_CON /*lint --e(923)*/ (*(volatile Ifx_CPU_FPU_TRAP_CON*)0xF881A000u)
+
+/** \brief A008, CPU Trapping Instruction Opcode Register */
+#define CPU0_FPU_TRAP_OPC /*lint --e(923)*/ (*(volatile Ifx_CPU_FPU_TRAP_OPC*)0xF881A008u)
+
+/** \brief A004, CPU Trapping Instruction Program Counter Register */
+#define CPU0_FPU_TRAP_PC /*lint --e(923)*/ (*(volatile Ifx_CPU_FPU_TRAP_PC*)0xF881A004u)
+
+/** \brief A010, CPU Trapping Instruction Operand Register */
+#define CPU0_FPU_TRAP_SRC1 /*lint --e(923)*/ (*(volatile Ifx_CPU_FPU_TRAP_SRC1*)0xF881A010u)
+
+/** \brief A014, CPU Trapping Instruction Operand Register */
+#define CPU0_FPU_TRAP_SRC2 /*lint --e(923)*/ (*(volatile Ifx_CPU_FPU_TRAP_SRC2*)0xF881A014u)
+
+/** \brief A018, Trapping Instruction Operand Register */
+#define CPU0_FPU_TRAP_SRC3 /*lint --e(923)*/ (*(volatile Ifx_CPU_FPU_TRAP_SRC3*)0xF881A018u)
+
+/** \brief FC08, Instruction Count */
+#define CPU0_ICNT /*lint --e(923)*/ (*(volatile Ifx_CPU_ICNT*)0xF881FC08u)
+
+/** \brief FE2C, Interrupt Control Register */
+#define CPU0_ICR /*lint --e(923)*/ (*(volatile Ifx_CPU_ICR*)0xF881FE2Cu)
+
+/** \brief FE28, Interrupt Stack Pointer */
+#define CPU0_ISP /*lint --e(923)*/ (*(volatile Ifx_CPU_ISP*)0xF881FE28u)
+
+/** \brief FE3C, Free CSA List Limit Pointer */
+#define CPU0_LCX /*lint --e(923)*/ (*(volatile Ifx_CPU_LCX*)0xF881FE3Cu)
+
+/** \brief FC0C, Multi-Count Register 1 */
+#define CPU0_M1CNT /*lint --e(923)*/ (*(volatile Ifx_CPU_M1CNT*)0xF881FC0Cu)
+
+/** \brief FC10, Multi-Count Register 2 */
+#define CPU0_M2CNT /*lint --e(923)*/ (*(volatile Ifx_CPU_M2CNT*)0xF881FC10u)
+
+/** \brief FC14, Multi-Count Register 3 */
+#define CPU0_M3CNT /*lint --e(923)*/ (*(volatile Ifx_CPU_M3CNT*)0xF881FC14u)
+
+/** \brief FE08, Program Counter */
+#define CPU0_PC /*lint --e(923)*/ (*(volatile Ifx_CPU_PC*)0xF881FE08u)
+
+/** \brief 920C, Program Control 0 */
+#define CPU0_PCON0 /*lint --e(923)*/ (*(volatile Ifx_CPU_PCON0*)0xF881920Cu)
+
+/** \brief 9204, Program Control 1 */
+#define CPU0_PCON1 /*lint --e(923)*/ (*(volatile Ifx_CPU_PCON1*)0xF8819204u)
+
+/** \brief 9208, Program Control 2 */
+#define CPU0_PCON2 /*lint --e(923)*/ (*(volatile Ifx_CPU_PCON2*)0xF8819208u)
+
+/** \brief FE00, Previous Context Information Register */
+#define CPU0_PCXI /*lint --e(923)*/ (*(volatile Ifx_CPU_PCXI*)0xF881FE00u)
+
+/** \brief 9210, Program Integrity Error Address Register */
+#define CPU0_PIEAR /*lint --e(923)*/ (*(volatile Ifx_CPU_PIEAR*)0xF8819210u)
+
+/** \brief 9214, Program Integrity Error Trap Register */
+#define CPU0_PIETR /*lint --e(923)*/ (*(volatile Ifx_CPU_PIETR*)0xF8819214u)
+
+/** \brief 8100, Data Access CacheabilityRegister */
+#define CPU0_PMA0 /*lint --e(923)*/ (*(volatile Ifx_CPU_PMA0*)0xF8818100u)
+
+/** \brief 8104, Code Access CacheabilityRegister */
+#define CPU0_PMA1 /*lint --e(923)*/ (*(volatile Ifx_CPU_PMA1*)0xF8818104u)
+
+/** \brief 8108, Peripheral Space Identifier register */
+#define CPU0_PMA2 /*lint --e(923)*/ (*(volatile Ifx_CPU_PMA2*)0xF8818108u)
+
+/** \brief 9200, Program Synchronous Trap Register */
+#define CPU0_PSTR /*lint --e(923)*/ (*(volatile Ifx_CPU_PSTR*)0xF8819200u)
+
+/** \brief FE04, Program Status Word */
+#define CPU0_PSW /*lint --e(923)*/ (*(volatile Ifx_CPU_PSW*)0xF881FE04u)
+
+/** \brief 1030, SRI Error Generation Register */
+#define CPU0_SEGEN /*lint --e(923)*/ (*(volatile Ifx_CPU_SEGEN*)0xF8811030u)
+
+/** \brief 900C, SIST Mode Access Control Register */
+#define CPU0_SMACON /*lint --e(923)*/ (*(volatile Ifx_CPU_SMACON*)0xF881900Cu)
+
+/** \brief FD10, Software Debug Event */
+#define CPU0_SWEVT /*lint --e(923)*/ (*(volatile Ifx_CPU_SWEVT*)0xF881FD10u)
+
+/** \brief FE14, System Configuration Register */
+#define CPU0_SYSCON /*lint --e(923)*/ (*(volatile Ifx_CPU_SYSCON*)0xF881FE14u)
+
+/** \brief 8004, CPU Task Address Space Identifier Register */
+#define CPU0_TASK_ASI /*lint --e(923)*/ (*(volatile Ifx_CPU_TASK_ASI*)0xF8818004u)
+
+/** \brief E400, CPU Temporal Protection System Control Register */
+#define CPU0_TPS_CON /*lint --e(923)*/ (*(volatile Ifx_CPU_TPS_CON*)0xF881E400u)
+
+/** \brief E404, CPU Temporal Protection System Timer Register */
+#define CPU0_TPS_TIMER0 /*lint --e(923)*/ (*(volatile Ifx_CPU_TPS_TIMER*)0xF881E404u)
+
+/** \brief E408, CPU Temporal Protection System Timer Register */
+#define CPU0_TPS_TIMER1 /*lint --e(923)*/ (*(volatile Ifx_CPU_TPS_TIMER*)0xF881E408u)
+
+/** \brief E40C, CPU Temporal Protection System Timer Register */
+#define CPU0_TPS_TIMER2 /*lint --e(923)*/ (*(volatile Ifx_CPU_TPS_TIMER*)0xF881E40Cu)
+
+/** \brief F004, Trigger Address */
+#define CPU0_TR0_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF881F004u)
+
+/** Alias (User Manual Name) for CPU0_TR0_ADR.
+* To use register names with standard convension, please use CPU0_TR0_ADR.
+*/
+#define CPU0_TR0ADR (CPU0_TR0_ADR)
+
+/** \brief F000, Trigger Event */
+#define CPU0_TR0_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF881F000u)
+
+/** Alias (User Manual Name) for CPU0_TR0_EVT.
+* To use register names with standard convension, please use CPU0_TR0_EVT.
+*/
+#define CPU0_TR0EVT (CPU0_TR0_EVT)
+
+/** \brief F00C, Trigger Address */
+#define CPU0_TR1_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF881F00Cu)
+
+/** Alias (User Manual Name) for CPU0_TR1_ADR.
+* To use register names with standard convension, please use CPU0_TR1_ADR.
+*/
+#define CPU0_TR1ADR (CPU0_TR1_ADR)
+
+/** \brief F008, Trigger Event */
+#define CPU0_TR1_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF881F008u)
+
+/** Alias (User Manual Name) for CPU0_TR1_EVT.
+* To use register names with standard convension, please use CPU0_TR1_EVT.
+*/
+#define CPU0_TR1EVT (CPU0_TR1_EVT)
+
+/** \brief F014, Trigger Address */
+#define CPU0_TR2_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF881F014u)
+
+/** Alias (User Manual Name) for CPU0_TR2_ADR.
+* To use register names with standard convension, please use CPU0_TR2_ADR.
+*/
+#define CPU0_TR2ADR (CPU0_TR2_ADR)
+
+/** \brief F010, Trigger Event */
+#define CPU0_TR2_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF881F010u)
+
+/** Alias (User Manual Name) for CPU0_TR2_EVT.
+* To use register names with standard convension, please use CPU0_TR2_EVT.
+*/
+#define CPU0_TR2EVT (CPU0_TR2_EVT)
+
+/** \brief F01C, Trigger Address */
+#define CPU0_TR3_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF881F01Cu)
+
+/** Alias (User Manual Name) for CPU0_TR3_ADR.
+* To use register names with standard convension, please use CPU0_TR3_ADR.
+*/
+#define CPU0_TR3ADR (CPU0_TR3_ADR)
+
+/** \brief F018, Trigger Event */
+#define CPU0_TR3_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF881F018u)
+
+/** Alias (User Manual Name) for CPU0_TR3_EVT.
+* To use register names with standard convension, please use CPU0_TR3_EVT.
+*/
+#define CPU0_TR3EVT (CPU0_TR3_EVT)
+
+/** \brief F024, Trigger Address */
+#define CPU0_TR4_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF881F024u)
+
+/** Alias (User Manual Name) for CPU0_TR4_ADR.
+* To use register names with standard convension, please use CPU0_TR4_ADR.
+*/
+#define CPU0_TR4ADR (CPU0_TR4_ADR)
+
+/** \brief F020, Trigger Event */
+#define CPU0_TR4_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF881F020u)
+
+/** Alias (User Manual Name) for CPU0_TR4_EVT.
+* To use register names with standard convension, please use CPU0_TR4_EVT.
+*/
+#define CPU0_TR4EVT (CPU0_TR4_EVT)
+
+/** \brief F02C, Trigger Address */
+#define CPU0_TR5_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF881F02Cu)
+
+/** Alias (User Manual Name) for CPU0_TR5_ADR.
+* To use register names with standard convension, please use CPU0_TR5_ADR.
+*/
+#define CPU0_TR5ADR (CPU0_TR5_ADR)
+
+/** \brief F028, Trigger Event */
+#define CPU0_TR5_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF881F028u)
+
+/** Alias (User Manual Name) for CPU0_TR5_EVT.
+* To use register names with standard convension, please use CPU0_TR5_EVT.
+*/
+#define CPU0_TR5EVT (CPU0_TR5_EVT)
+
+/** \brief F034, Trigger Address */
+#define CPU0_TR6_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF881F034u)
+
+/** Alias (User Manual Name) for CPU0_TR6_ADR.
+* To use register names with standard convension, please use CPU0_TR6_ADR.
+*/
+#define CPU0_TR6ADR (CPU0_TR6_ADR)
+
+/** \brief F030, Trigger Event */
+#define CPU0_TR6_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF881F030u)
+
+/** Alias (User Manual Name) for CPU0_TR6_EVT.
+* To use register names with standard convension, please use CPU0_TR6_EVT.
+*/
+#define CPU0_TR6EVT (CPU0_TR6_EVT)
+
+/** \brief F03C, Trigger Address */
+#define CPU0_TR7_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF881F03Cu)
+
+/** Alias (User Manual Name) for CPU0_TR7_ADR.
+* To use register names with standard convension, please use CPU0_TR7_ADR.
+*/
+#define CPU0_TR7ADR (CPU0_TR7_ADR)
+
+/** \brief F038, Trigger Event */
+#define CPU0_TR7_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF881F038u)
+
+/** Alias (User Manual Name) for CPU0_TR7_EVT.
+* To use register names with standard convension, please use CPU0_TR7_EVT.
+*/
+#define CPU0_TR7EVT (CPU0_TR7_EVT)
+
+/** \brief FD30, CPU Trigger Address x */
+#define CPU0_TRIG_ACC /*lint --e(923)*/ (*(volatile Ifx_CPU_TRIG_ACC*)0xF881FD30u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Cpu_Cfg_Cpu1
+ * \{ */
+
+/** \brief FF80, Address General Purpose Register */
+#define CPU1_A0 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF883FF80u)
+
+/** \brief FF84, Address General Purpose Register */
+#define CPU1_A1 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF883FF84u)
+
+/** \brief FFA8, Address General Purpose Register */
+#define CPU1_A10 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF883FFA8u)
+
+/** \brief FFAC, Address General Purpose Register */
+#define CPU1_A11 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF883FFACu)
+
+/** \brief FFB0, Address General Purpose Register */
+#define CPU1_A12 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF883FFB0u)
+
+/** \brief FFB4, Address General Purpose Register */
+#define CPU1_A13 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF883FFB4u)
+
+/** \brief FFB8, Address General Purpose Register */
+#define CPU1_A14 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF883FFB8u)
+
+/** \brief FFBC, Address General Purpose Register */
+#define CPU1_A15 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF883FFBCu)
+
+/** \brief FF88, Address General Purpose Register */
+#define CPU1_A2 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF883FF88u)
+
+/** \brief FF8C, Address General Purpose Register */
+#define CPU1_A3 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF883FF8Cu)
+
+/** \brief FF90, Address General Purpose Register */
+#define CPU1_A4 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF883FF90u)
+
+/** \brief FF94, Address General Purpose Register */
+#define CPU1_A5 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF883FF94u)
+
+/** \brief FF98, Address General Purpose Register */
+#define CPU1_A6 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF883FF98u)
+
+/** \brief FF9C, Address General Purpose Register */
+#define CPU1_A7 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF883FF9Cu)
+
+/** \brief FFA0, Address General Purpose Register */
+#define CPU1_A8 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF883FFA0u)
+
+/** \brief FFA4, Address General Purpose Register */
+#define CPU1_A9 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF883FFA4u)
+
+/** \brief FE20, Base Interrupt Vector Table Pointer */
+#define CPU1_BIV /*lint --e(923)*/ (*(volatile Ifx_CPU_BIV*)0xF883FE20u)
+
+/** \brief FE24, Base Trap Vector Table Pointer */
+#define CPU1_BTV /*lint --e(923)*/ (*(volatile Ifx_CPU_BTV*)0xF883FE24u)
+
+/** \brief FC04, CPU Clock Cycle Count */
+#define CPU1_CCNT /*lint --e(923)*/ (*(volatile Ifx_CPU_CCNT*)0xF883FC04u)
+
+/** \brief FC00, Counter Control */
+#define CPU1_CCTRL /*lint --e(923)*/ (*(volatile Ifx_CPU_CCTRL*)0xF883FC00u)
+
+/** \brief 9400, Compatibility Control Register */
+#define CPU1_COMPAT /*lint --e(923)*/ (*(volatile Ifx_CPU_COMPAT*)0xF8839400u)
+
+/** \brief FE1C, CPU Core Identification Register */
+#define CPU1_CORE_ID /*lint --e(923)*/ (*(volatile Ifx_CPU_CORE_ID*)0xF883FE1Cu)
+
+/** \brief D000, CPU Code Protection Range Lower Bound Register */
+#define CPU1_CPR0_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF883D000u)
+
+/** \brief D004, CPU Code Protection Range Upper Bound Register */
+#define CPU1_CPR0_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF883D004u)
+
+/** \brief D008, CPU Code Protection Range Lower Bound Register */
+#define CPU1_CPR1_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF883D008u)
+
+/** \brief D00C, CPU Code Protection Range Upper Bound Register */
+#define CPU1_CPR1_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF883D00Cu)
+
+/** \brief D010, CPU Code Protection Range Lower Bound Register */
+#define CPU1_CPR2_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF883D010u)
+
+/** \brief D014, CPU Code Protection Range Upper Bound Register */
+#define CPU1_CPR2_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF883D014u)
+
+/** \brief D018, CPU Code Protection Range Lower Bound Register */
+#define CPU1_CPR3_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF883D018u)
+
+/** \brief D01C, CPU Code Protection Range Upper Bound Register */
+#define CPU1_CPR3_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF883D01Cu)
+
+/** \brief D020, CPU Code Protection Range Lower Bound Register */
+#define CPU1_CPR4_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF883D020u)
+
+/** \brief D024, CPU Code Protection Range Upper Bound Register */
+#define CPU1_CPR4_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF883D024u)
+
+/** \brief D028, CPU Code Protection Range Lower Bound Register */
+#define CPU1_CPR5_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF883D028u)
+
+/** \brief D02C, CPU Code Protection Range Upper Bound Register */
+#define CPU1_CPR5_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF883D02Cu)
+
+/** \brief D030, CPU Code Protection Range Lower Bound Register */
+#define CPU1_CPR6_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF883D030u)
+
+/** \brief D034, CPU Code Protection Range Upper Bound Register */
+#define CPU1_CPR6_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF883D034u)
+
+/** \brief D038, CPU Code Protection Range Lower Bound Register */
+#define CPU1_CPR7_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF883D038u)
+
+/** \brief D03C, CPU Code Protection Range Upper Bound Register */
+#define CPU1_CPR7_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF883D03Cu)
+
+/** \brief FE18, CPU Identification Register TC1.6P */
+#define CPU1_CPU_ID /*lint --e(923)*/ (*(volatile Ifx_CPU_CPU_ID*)0xF883FE18u)
+
+/** \brief E000, CPU Code Protection Execute Enable Register Set */
+#define CPU1_CPXE0 /*lint --e(923)*/ (*(volatile Ifx_CPU_CPXE*)0xF883E000u)
+
+/** Alias (User Manual Name) for CPU1_CPXE0.
+* To use register names with standard convension, please use CPU1_CPXE0.
+*/
+#define CPU1_CPXE_0 (CPU1_CPXE0)
+
+/** \brief E004, CPU Code Protection Execute Enable Register Set */
+#define CPU1_CPXE1 /*lint --e(923)*/ (*(volatile Ifx_CPU_CPXE*)0xF883E004u)
+
+/** Alias (User Manual Name) for CPU1_CPXE1.
+* To use register names with standard convension, please use CPU1_CPXE1.
+*/
+#define CPU1_CPXE_1 (CPU1_CPXE1)
+
+/** \brief E008, CPU Code Protection Execute Enable Register Set */
+#define CPU1_CPXE2 /*lint --e(923)*/ (*(volatile Ifx_CPU_CPXE*)0xF883E008u)
+
+/** Alias (User Manual Name) for CPU1_CPXE2.
+* To use register names with standard convension, please use CPU1_CPXE2.
+*/
+#define CPU1_CPXE_2 (CPU1_CPXE2)
+
+/** \brief E00C, CPU Code Protection Execute Enable Register Set */
+#define CPU1_CPXE3 /*lint --e(923)*/ (*(volatile Ifx_CPU_CPXE*)0xF883E00Cu)
+
+/** Alias (User Manual Name) for CPU1_CPXE3.
+* To use register names with standard convension, please use CPU1_CPXE3.
+*/
+#define CPU1_CPXE_3 (CPU1_CPXE3)
+
+/** \brief FD0C, Core Register Access Event */
+#define CPU1_CREVT /*lint --e(923)*/ (*(volatile Ifx_CPU_CREVT*)0xF883FD0Cu)
+
+/** \brief FE50, CPU Customer ID register */
+#define CPU1_CUS_ID /*lint --e(923)*/ (*(volatile Ifx_CPU_CUS_ID*)0xF883FE50u)
+
+/** \brief FF00, Data General Purpose Register */
+#define CPU1_D0 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF883FF00u)
+
+/** \brief FF04, Data General Purpose Register */
+#define CPU1_D1 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF883FF04u)
+
+/** \brief FF28, Data General Purpose Register */
+#define CPU1_D10 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF883FF28u)
+
+/** \brief FF2C, Data General Purpose Register */
+#define CPU1_D11 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF883FF2Cu)
+
+/** \brief FF30, Data General Purpose Register */
+#define CPU1_D12 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF883FF30u)
+
+/** \brief FF34, Data General Purpose Register */
+#define CPU1_D13 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF883FF34u)
+
+/** \brief FF38, Data General Purpose Register */
+#define CPU1_D14 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF883FF38u)
+
+/** \brief FF3C, Data General Purpose Register */
+#define CPU1_D15 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF883FF3Cu)
+
+/** \brief FF08, Data General Purpose Register */
+#define CPU1_D2 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF883FF08u)
+
+/** \brief FF0C, Data General Purpose Register */
+#define CPU1_D3 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF883FF0Cu)
+
+/** \brief FF10, Data General Purpose Register */
+#define CPU1_D4 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF883FF10u)
+
+/** \brief FF14, Data General Purpose Register */
+#define CPU1_D5 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF883FF14u)
+
+/** \brief FF18, Data General Purpose Register */
+#define CPU1_D6 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF883FF18u)
+
+/** \brief FF1C, Data General Purpose Register */
+#define CPU1_D7 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF883FF1Cu)
+
+/** \brief FF20, Data General Purpose Register */
+#define CPU1_D8 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF883FF20u)
+
+/** \brief FF24, Data General Purpose Register */
+#define CPU1_D9 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF883FF24u)
+
+/** \brief 9018, Data Asynchronous Trap Register */
+#define CPU1_DATR /*lint --e(923)*/ (*(volatile Ifx_CPU_DATR*)0xF8839018u)
+
+/** \brief FD00, Debug Status Register */
+#define CPU1_DBGSR /*lint --e(923)*/ (*(volatile Ifx_CPU_DBGSR*)0xF883FD00u)
+
+/** \brief FD48, Debug Trap Control Register */
+#define CPU1_DBGTCR /*lint --e(923)*/ (*(volatile Ifx_CPU_DBGTCR*)0xF883FD48u)
+
+/** \brief 9040, Data Memory Control Register */
+#define CPU1_DCON0 /*lint --e(923)*/ (*(volatile Ifx_CPU_DCON0*)0xF8839040u)
+
+/** \brief 9000, Data Control Register 2 */
+#define CPU1_DCON2 /*lint --e(923)*/ (*(volatile Ifx_CPU_DCON2*)0xF8839000u)
+
+/** \brief FD44, CPU Debug Context Save Area Pointer */
+#define CPU1_DCX /*lint --e(923)*/ (*(volatile Ifx_CPU_DCX*)0xF883FD44u)
+
+/** \brief 901C, Data Error Address Register */
+#define CPU1_DEADD /*lint --e(923)*/ (*(volatile Ifx_CPU_DEADD*)0xF883901Cu)
+
+/** \brief 9020, Data Integrity Error Address Register */
+#define CPU1_DIEAR /*lint --e(923)*/ (*(volatile Ifx_CPU_DIEAR*)0xF8839020u)
+
+/** \brief 9024, Data Integrity Error Trap Register */
+#define CPU1_DIETR /*lint --e(923)*/ (*(volatile Ifx_CPU_DIETR*)0xF8839024u)
+
+/** \brief FD40, CPU Debug Monitor Start Address */
+#define CPU1_DMS /*lint --e(923)*/ (*(volatile Ifx_CPU_DMS*)0xF883FD40u)
+
+/** \brief C000, CPU Data Protection Range, Lower Bound Register */
+#define CPU1_DPR0_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF883C000u)
+
+/** \brief C004, CPU Data Protection Range, Upper Bound Register */
+#define CPU1_DPR0_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF883C004u)
+
+/** \brief C050, CPU Data Protection Range, Lower Bound Register */
+#define CPU1_DPR10_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF883C050u)
+
+/** \brief C054, CPU Data Protection Range, Upper Bound Register */
+#define CPU1_DPR10_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF883C054u)
+
+/** \brief C058, CPU Data Protection Range, Lower Bound Register */
+#define CPU1_DPR11_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF883C058u)
+
+/** \brief C05C, CPU Data Protection Range, Upper Bound Register */
+#define CPU1_DPR11_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF883C05Cu)
+
+/** \brief C060, CPU Data Protection Range, Lower Bound Register */
+#define CPU1_DPR12_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF883C060u)
+
+/** \brief C064, CPU Data Protection Range, Upper Bound Register */
+#define CPU1_DPR12_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF883C064u)
+
+/** \brief C068, CPU Data Protection Range, Lower Bound Register */
+#define CPU1_DPR13_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF883C068u)
+
+/** \brief C06C, CPU Data Protection Range, Upper Bound Register */
+#define CPU1_DPR13_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF883C06Cu)
+
+/** \brief C070, CPU Data Protection Range, Lower Bound Register */
+#define CPU1_DPR14_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF883C070u)
+
+/** \brief C074, CPU Data Protection Range, Upper Bound Register */
+#define CPU1_DPR14_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF883C074u)
+
+/** \brief C078, CPU Data Protection Range, Lower Bound Register */
+#define CPU1_DPR15_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF883C078u)
+
+/** \brief C07C, CPU Data Protection Range, Upper Bound Register */
+#define CPU1_DPR15_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF883C07Cu)
+
+/** \brief C008, CPU Data Protection Range, Lower Bound Register */
+#define CPU1_DPR1_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF883C008u)
+
+/** \brief C00C, CPU Data Protection Range, Upper Bound Register */
+#define CPU1_DPR1_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF883C00Cu)
+
+/** \brief C010, CPU Data Protection Range, Lower Bound Register */
+#define CPU1_DPR2_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF883C010u)
+
+/** \brief C014, CPU Data Protection Range, Upper Bound Register */
+#define CPU1_DPR2_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF883C014u)
+
+/** \brief C018, CPU Data Protection Range, Lower Bound Register */
+#define CPU1_DPR3_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF883C018u)
+
+/** \brief C01C, CPU Data Protection Range, Upper Bound Register */
+#define CPU1_DPR3_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF883C01Cu)
+
+/** \brief C020, CPU Data Protection Range, Lower Bound Register */
+#define CPU1_DPR4_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF883C020u)
+
+/** \brief C024, CPU Data Protection Range, Upper Bound Register */
+#define CPU1_DPR4_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF883C024u)
+
+/** \brief C028, CPU Data Protection Range, Lower Bound Register */
+#define CPU1_DPR5_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF883C028u)
+
+/** \brief C02C, CPU Data Protection Range, Upper Bound Register */
+#define CPU1_DPR5_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF883C02Cu)
+
+/** \brief C030, CPU Data Protection Range, Lower Bound Register */
+#define CPU1_DPR6_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF883C030u)
+
+/** \brief C034, CPU Data Protection Range, Upper Bound Register */
+#define CPU1_DPR6_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF883C034u)
+
+/** \brief C038, CPU Data Protection Range, Lower Bound Register */
+#define CPU1_DPR7_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF883C038u)
+
+/** \brief C03C, CPU Data Protection Range, Upper Bound Register */
+#define CPU1_DPR7_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF883C03Cu)
+
+/** \brief C040, CPU Data Protection Range, Lower Bound Register */
+#define CPU1_DPR8_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF883C040u)
+
+/** \brief C044, CPU Data Protection Range, Upper Bound Register */
+#define CPU1_DPR8_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF883C044u)
+
+/** \brief C048, CPU Data Protection Range, Lower Bound Register */
+#define CPU1_DPR9_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF883C048u)
+
+/** \brief C04C, CPU Data Protection Range, Upper Bound Register */
+#define CPU1_DPR9_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF883C04Cu)
+
+/** \brief E010, CPU Data Protection Read Enable Register Set */
+#define CPU1_DPRE0 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPRE*)0xF883E010u)
+
+/** Alias (User Manual Name) for CPU1_DPRE0.
+* To use register names with standard convension, please use CPU1_DPRE0.
+*/
+#define CPU1_DPRE_0 (CPU1_DPRE0)
+
+/** \brief E014, CPU Data Protection Read Enable Register Set */
+#define CPU1_DPRE1 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPRE*)0xF883E014u)
+
+/** Alias (User Manual Name) for CPU1_DPRE1.
+* To use register names with standard convension, please use CPU1_DPRE1.
+*/
+#define CPU1_DPRE_1 (CPU1_DPRE1)
+
+/** \brief E018, CPU Data Protection Read Enable Register Set */
+#define CPU1_DPRE2 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPRE*)0xF883E018u)
+
+/** Alias (User Manual Name) for CPU1_DPRE2.
+* To use register names with standard convension, please use CPU1_DPRE2.
+*/
+#define CPU1_DPRE_2 (CPU1_DPRE2)
+
+/** \brief E01C, CPU Data Protection Read Enable Register Set */
+#define CPU1_DPRE3 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPRE*)0xF883E01Cu)
+
+/** Alias (User Manual Name) for CPU1_DPRE3.
+* To use register names with standard convension, please use CPU1_DPRE3.
+*/
+#define CPU1_DPRE_3 (CPU1_DPRE3)
+
+/** \brief E020, CPU Data Protection Write Enable Register Set */
+#define CPU1_DPWE0 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPWE*)0xF883E020u)
+
+/** Alias (User Manual Name) for CPU1_DPWE0.
+* To use register names with standard convension, please use CPU1_DPWE0.
+*/
+#define CPU1_DPWE_0 (CPU1_DPWE0)
+
+/** \brief E024, CPU Data Protection Write Enable Register Set */
+#define CPU1_DPWE1 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPWE*)0xF883E024u)
+
+/** Alias (User Manual Name) for CPU1_DPWE1.
+* To use register names with standard convension, please use CPU1_DPWE1.
+*/
+#define CPU1_DPWE_1 (CPU1_DPWE1)
+
+/** \brief E028, CPU Data Protection Write Enable Register Set */
+#define CPU1_DPWE2 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPWE*)0xF883E028u)
+
+/** Alias (User Manual Name) for CPU1_DPWE2.
+* To use register names with standard convension, please use CPU1_DPWE2.
+*/
+#define CPU1_DPWE_2 (CPU1_DPWE2)
+
+/** \brief E02C, CPU Data Protection Write Enable Register Set */
+#define CPU1_DPWE3 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPWE*)0xF883E02Cu)
+
+/** Alias (User Manual Name) for CPU1_DPWE3.
+* To use register names with standard convension, please use CPU1_DPWE3.
+*/
+#define CPU1_DPWE_3 (CPU1_DPWE3)
+
+/** \brief 9010, Data Synchronous Trap Register */
+#define CPU1_DSTR /*lint --e(923)*/ (*(volatile Ifx_CPU_DSTR*)0xF8839010u)
+
+/** \brief FD08, External Event Register */
+#define CPU1_EXEVT /*lint --e(923)*/ (*(volatile Ifx_CPU_EXEVT*)0xF883FD08u)
+
+/** \brief FE38, Free CSA List Head Pointer */
+#define CPU1_FCX /*lint --e(923)*/ (*(volatile Ifx_CPU_FCX*)0xF883FE38u)
+
+/** \brief A000, CPU Trap Control Register */
+#define CPU1_FPU_TRAP_CON /*lint --e(923)*/ (*(volatile Ifx_CPU_FPU_TRAP_CON*)0xF883A000u)
+
+/** \brief A008, CPU Trapping Instruction Opcode Register */
+#define CPU1_FPU_TRAP_OPC /*lint --e(923)*/ (*(volatile Ifx_CPU_FPU_TRAP_OPC*)0xF883A008u)
+
+/** \brief A004, CPU Trapping Instruction Program Counter Register */
+#define CPU1_FPU_TRAP_PC /*lint --e(923)*/ (*(volatile Ifx_CPU_FPU_TRAP_PC*)0xF883A004u)
+
+/** \brief A010, CPU Trapping Instruction Operand Register */
+#define CPU1_FPU_TRAP_SRC1 /*lint --e(923)*/ (*(volatile Ifx_CPU_FPU_TRAP_SRC1*)0xF883A010u)
+
+/** \brief A014, CPU Trapping Instruction Operand Register */
+#define CPU1_FPU_TRAP_SRC2 /*lint --e(923)*/ (*(volatile Ifx_CPU_FPU_TRAP_SRC2*)0xF883A014u)
+
+/** \brief A018, Trapping Instruction Operand Register */
+#define CPU1_FPU_TRAP_SRC3 /*lint --e(923)*/ (*(volatile Ifx_CPU_FPU_TRAP_SRC3*)0xF883A018u)
+
+/** \brief FC08, Instruction Count */
+#define CPU1_ICNT /*lint --e(923)*/ (*(volatile Ifx_CPU_ICNT*)0xF883FC08u)
+
+/** \brief FE2C, Interrupt Control Register */
+#define CPU1_ICR /*lint --e(923)*/ (*(volatile Ifx_CPU_ICR*)0xF883FE2Cu)
+
+/** \brief FE28, Interrupt Stack Pointer */
+#define CPU1_ISP /*lint --e(923)*/ (*(volatile Ifx_CPU_ISP*)0xF883FE28u)
+
+/** \brief FE3C, Free CSA List Limit Pointer */
+#define CPU1_LCX /*lint --e(923)*/ (*(volatile Ifx_CPU_LCX*)0xF883FE3Cu)
+
+/** \brief FC0C, Multi-Count Register 1 */
+#define CPU1_M1CNT /*lint --e(923)*/ (*(volatile Ifx_CPU_M1CNT*)0xF883FC0Cu)
+
+/** \brief FC10, Multi-Count Register 2 */
+#define CPU1_M2CNT /*lint --e(923)*/ (*(volatile Ifx_CPU_M2CNT*)0xF883FC10u)
+
+/** \brief FC14, Multi-Count Register 3 */
+#define CPU1_M3CNT /*lint --e(923)*/ (*(volatile Ifx_CPU_M3CNT*)0xF883FC14u)
+
+/** \brief FE08, Program Counter */
+#define CPU1_PC /*lint --e(923)*/ (*(volatile Ifx_CPU_PC*)0xF883FE08u)
+
+/** \brief 920C, Program Control 0 */
+#define CPU1_PCON0 /*lint --e(923)*/ (*(volatile Ifx_CPU_PCON0*)0xF883920Cu)
+
+/** \brief 9204, Program Control 1 */
+#define CPU1_PCON1 /*lint --e(923)*/ (*(volatile Ifx_CPU_PCON1*)0xF8839204u)
+
+/** \brief 9208, Program Control 2 */
+#define CPU1_PCON2 /*lint --e(923)*/ (*(volatile Ifx_CPU_PCON2*)0xF8839208u)
+
+/** \brief FE00, Previous Context Information Register */
+#define CPU1_PCXI /*lint --e(923)*/ (*(volatile Ifx_CPU_PCXI*)0xF883FE00u)
+
+/** \brief 9210, Program Integrity Error Address Register */
+#define CPU1_PIEAR /*lint --e(923)*/ (*(volatile Ifx_CPU_PIEAR*)0xF8839210u)
+
+/** \brief 9214, Program Integrity Error Trap Register */
+#define CPU1_PIETR /*lint --e(923)*/ (*(volatile Ifx_CPU_PIETR*)0xF8839214u)
+
+/** \brief 8100, Data Access CacheabilityRegister */
+#define CPU1_PMA0 /*lint --e(923)*/ (*(volatile Ifx_CPU_PMA0*)0xF8838100u)
+
+/** \brief 8104, Code Access CacheabilityRegister */
+#define CPU1_PMA1 /*lint --e(923)*/ (*(volatile Ifx_CPU_PMA1*)0xF8838104u)
+
+/** \brief 8108, Peripheral Space Identifier register */
+#define CPU1_PMA2 /*lint --e(923)*/ (*(volatile Ifx_CPU_PMA2*)0xF8838108u)
+
+/** \brief 9200, Program Synchronous Trap Register */
+#define CPU1_PSTR /*lint --e(923)*/ (*(volatile Ifx_CPU_PSTR*)0xF8839200u)
+
+/** \brief FE04, Program Status Word */
+#define CPU1_PSW /*lint --e(923)*/ (*(volatile Ifx_CPU_PSW*)0xF883FE04u)
+
+/** \brief 1030, SRI Error Generation Register */
+#define CPU1_SEGEN /*lint --e(923)*/ (*(volatile Ifx_CPU_SEGEN*)0xF8831030u)
+
+/** \brief 900C, SIST Mode Access Control Register */
+#define CPU1_SMACON /*lint --e(923)*/ (*(volatile Ifx_CPU_SMACON*)0xF883900Cu)
+
+/** \brief FD10, Software Debug Event */
+#define CPU1_SWEVT /*lint --e(923)*/ (*(volatile Ifx_CPU_SWEVT*)0xF883FD10u)
+
+/** \brief FE14, System Configuration Register */
+#define CPU1_SYSCON /*lint --e(923)*/ (*(volatile Ifx_CPU_SYSCON*)0xF883FE14u)
+
+/** \brief 8004, CPU Task Address Space Identifier Register */
+#define CPU1_TASK_ASI /*lint --e(923)*/ (*(volatile Ifx_CPU_TASK_ASI*)0xF8838004u)
+
+/** \brief E400, CPU Temporal Protection System Control Register */
+#define CPU1_TPS_CON /*lint --e(923)*/ (*(volatile Ifx_CPU_TPS_CON*)0xF883E400u)
+
+/** \brief E404, CPU Temporal Protection System Timer Register */
+#define CPU1_TPS_TIMER0 /*lint --e(923)*/ (*(volatile Ifx_CPU_TPS_TIMER*)0xF883E404u)
+
+/** \brief E408, CPU Temporal Protection System Timer Register */
+#define CPU1_TPS_TIMER1 /*lint --e(923)*/ (*(volatile Ifx_CPU_TPS_TIMER*)0xF883E408u)
+
+/** \brief E40C, CPU Temporal Protection System Timer Register */
+#define CPU1_TPS_TIMER2 /*lint --e(923)*/ (*(volatile Ifx_CPU_TPS_TIMER*)0xF883E40Cu)
+
+/** \brief F004, Trigger Address */
+#define CPU1_TR0_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF883F004u)
+
+/** Alias (User Manual Name) for CPU1_TR0_ADR.
+* To use register names with standard convension, please use CPU1_TR0_ADR.
+*/
+#define CPU1_TR0ADR (CPU1_TR0_ADR)
+
+/** \brief F000, Trigger Event */
+#define CPU1_TR0_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF883F000u)
+
+/** Alias (User Manual Name) for CPU1_TR0_EVT.
+* To use register names with standard convension, please use CPU1_TR0_EVT.
+*/
+#define CPU1_TR0EVT (CPU1_TR0_EVT)
+
+/** \brief F00C, Trigger Address */
+#define CPU1_TR1_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF883F00Cu)
+
+/** Alias (User Manual Name) for CPU1_TR1_ADR.
+* To use register names with standard convension, please use CPU1_TR1_ADR.
+*/
+#define CPU1_TR1ADR (CPU1_TR1_ADR)
+
+/** \brief F008, Trigger Event */
+#define CPU1_TR1_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF883F008u)
+
+/** Alias (User Manual Name) for CPU1_TR1_EVT.
+* To use register names with standard convension, please use CPU1_TR1_EVT.
+*/
+#define CPU1_TR1EVT (CPU1_TR1_EVT)
+
+/** \brief F014, Trigger Address */
+#define CPU1_TR2_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF883F014u)
+
+/** Alias (User Manual Name) for CPU1_TR2_ADR.
+* To use register names with standard convension, please use CPU1_TR2_ADR.
+*/
+#define CPU1_TR2ADR (CPU1_TR2_ADR)
+
+/** \brief F010, Trigger Event */
+#define CPU1_TR2_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF883F010u)
+
+/** Alias (User Manual Name) for CPU1_TR2_EVT.
+* To use register names with standard convension, please use CPU1_TR2_EVT.
+*/
+#define CPU1_TR2EVT (CPU1_TR2_EVT)
+
+/** \brief F01C, Trigger Address */
+#define CPU1_TR3_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF883F01Cu)
+
+/** Alias (User Manual Name) for CPU1_TR3_ADR.
+* To use register names with standard convension, please use CPU1_TR3_ADR.
+*/
+#define CPU1_TR3ADR (CPU1_TR3_ADR)
+
+/** \brief F018, Trigger Event */
+#define CPU1_TR3_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF883F018u)
+
+/** Alias (User Manual Name) for CPU1_TR3_EVT.
+* To use register names with standard convension, please use CPU1_TR3_EVT.
+*/
+#define CPU1_TR3EVT (CPU1_TR3_EVT)
+
+/** \brief F024, Trigger Address */
+#define CPU1_TR4_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF883F024u)
+
+/** Alias (User Manual Name) for CPU1_TR4_ADR.
+* To use register names with standard convension, please use CPU1_TR4_ADR.
+*/
+#define CPU1_TR4ADR (CPU1_TR4_ADR)
+
+/** \brief F020, Trigger Event */
+#define CPU1_TR4_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF883F020u)
+
+/** Alias (User Manual Name) for CPU1_TR4_EVT.
+* To use register names with standard convension, please use CPU1_TR4_EVT.
+*/
+#define CPU1_TR4EVT (CPU1_TR4_EVT)
+
+/** \brief F02C, Trigger Address */
+#define CPU1_TR5_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF883F02Cu)
+
+/** Alias (User Manual Name) for CPU1_TR5_ADR.
+* To use register names with standard convension, please use CPU1_TR5_ADR.
+*/
+#define CPU1_TR5ADR (CPU1_TR5_ADR)
+
+/** \brief F028, Trigger Event */
+#define CPU1_TR5_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF883F028u)
+
+/** Alias (User Manual Name) for CPU1_TR5_EVT.
+* To use register names with standard convension, please use CPU1_TR5_EVT.
+*/
+#define CPU1_TR5EVT (CPU1_TR5_EVT)
+
+/** \brief F034, Trigger Address */
+#define CPU1_TR6_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF883F034u)
+
+/** Alias (User Manual Name) for CPU1_TR6_ADR.
+* To use register names with standard convension, please use CPU1_TR6_ADR.
+*/
+#define CPU1_TR6ADR (CPU1_TR6_ADR)
+
+/** \brief F030, Trigger Event */
+#define CPU1_TR6_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF883F030u)
+
+/** Alias (User Manual Name) for CPU1_TR6_EVT.
+* To use register names with standard convension, please use CPU1_TR6_EVT.
+*/
+#define CPU1_TR6EVT (CPU1_TR6_EVT)
+
+/** \brief F03C, Trigger Address */
+#define CPU1_TR7_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF883F03Cu)
+
+/** Alias (User Manual Name) for CPU1_TR7_ADR.
+* To use register names with standard convension, please use CPU1_TR7_ADR.
+*/
+#define CPU1_TR7ADR (CPU1_TR7_ADR)
+
+/** \brief F038, Trigger Event */
+#define CPU1_TR7_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF883F038u)
+
+/** Alias (User Manual Name) for CPU1_TR7_EVT.
+* To use register names with standard convension, please use CPU1_TR7_EVT.
+*/
+#define CPU1_TR7EVT (CPU1_TR7_EVT)
+
+/** \brief FD30, CPU Trigger Address x */
+#define CPU1_TRIG_ACC /*lint --e(923)*/ (*(volatile Ifx_CPU_TRIG_ACC*)0xF883FD30u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Cpu_Cfg_Cpu
+ * \{ */
+
+/** \brief FF80, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A0 0xFF80
+
+/** \brief FF84, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A1 0xFF84
+
+/** \brief FFA8, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A10 0xFFA8
+
+/** \brief FFAC, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A11 0xFFAC
+
+/** \brief FFB0, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A12 0xFFB0
+
+/** \brief FFB4, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A13 0xFFB4
+
+/** \brief FFB8, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A14 0xFFB8
+
+/** \brief FFBC, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A15 0xFFBC
+
+/** \brief FF88, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A2 0xFF88
+
+/** \brief FF8C, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A3 0xFF8C
+
+/** \brief FF90, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A4 0xFF90
+
+/** \brief FF94, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A5 0xFF94
+
+/** \brief FF98, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A6 0xFF98
+
+/** \brief FF9C, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A7 0xFF9C
+
+/** \brief FFA0, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A8 0xFFA0
+
+/** \brief FFA4, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A9 0xFFA4
+
+/** \brief FE20, , type: Ifx_CPU_BIV, Base Interrupt Vector Table Pointer */
+#define CPU_BIV 0xFE20
+
+/** \brief FE24, , type: Ifx_CPU_BTV, Base Trap Vector Table Pointer */
+#define CPU_BTV 0xFE24
+
+/** \brief FC04, , type: Ifx_CPU_CCNT, CPU Clock Cycle Count */
+#define CPU_CCNT 0xFC04
+
+/** \brief FC00, , type: Ifx_CPU_CCTRL, Counter Control */
+#define CPU_CCTRL 0xFC00
+
+/** \brief 9400, , type: Ifx_CPU_COMPAT, Compatibility Control Register */
+#define CPU_COMPAT 0x9400
+
+/** \brief FE1C, , type: Ifx_CPU_CORE_ID, CPU Core Identification Register */
+#define CPU_CORE_ID 0xFE1C
+
+/** \brief D000, , type: Ifx_CPU_CPR_L, CPU Code Protection Range Lower Bound
+ * Register */
+#define CPU_CPR0_L 0xD000
+
+/** \brief D004, , type: Ifx_CPU_CPR_U, CPU Code Protection Range Upper Bound
+ * Register */
+#define CPU_CPR0_U 0xD004
+
+/** \brief D008, , type: Ifx_CPU_CPR_L, CPU Code Protection Range Lower Bound
+ * Register */
+#define CPU_CPR1_L 0xD008
+
+/** \brief D00C, , type: Ifx_CPU_CPR_U, CPU Code Protection Range Upper Bound
+ * Register */
+#define CPU_CPR1_U 0xD00C
+
+/** \brief D010, , type: Ifx_CPU_CPR_L, CPU Code Protection Range Lower Bound
+ * Register */
+#define CPU_CPR2_L 0xD010
+
+/** \brief D014, , type: Ifx_CPU_CPR_U, CPU Code Protection Range Upper Bound
+ * Register */
+#define CPU_CPR2_U 0xD014
+
+/** \brief D018, , type: Ifx_CPU_CPR_L, CPU Code Protection Range Lower Bound
+ * Register */
+#define CPU_CPR3_L 0xD018
+
+/** \brief D01C, , type: Ifx_CPU_CPR_U, CPU Code Protection Range Upper Bound
+ * Register */
+#define CPU_CPR3_U 0xD01C
+
+/** \brief D020, , type: Ifx_CPU_CPR_L, CPU Code Protection Range Lower Bound
+ * Register */
+#define CPU_CPR4_L 0xD020
+
+/** \brief D024, , type: Ifx_CPU_CPR_U, CPU Code Protection Range Upper Bound
+ * Register */
+#define CPU_CPR4_U 0xD024
+
+/** \brief D028, , type: Ifx_CPU_CPR_L, CPU Code Protection Range Lower Bound
+ * Register */
+#define CPU_CPR5_L 0xD028
+
+/** \brief D02C, , type: Ifx_CPU_CPR_U, CPU Code Protection Range Upper Bound
+ * Register */
+#define CPU_CPR5_U 0xD02C
+
+/** \brief D030, , type: Ifx_CPU_CPR_L, CPU Code Protection Range Lower Bound
+ * Register */
+#define CPU_CPR6_L 0xD030
+
+/** \brief D034, , type: Ifx_CPU_CPR_U, CPU Code Protection Range Upper Bound
+ * Register */
+#define CPU_CPR6_U 0xD034
+
+/** \brief D038, , type: Ifx_CPU_CPR_L, CPU Code Protection Range Lower Bound
+ * Register */
+#define CPU_CPR7_L 0xD038
+
+/** \brief D03C, , type: Ifx_CPU_CPR_U, CPU Code Protection Range Upper Bound
+ * Register */
+#define CPU_CPR7_U 0xD03C
+
+/** \brief FE18, , type: Ifx_CPU_CPU_ID, CPU Identification Register TC1.6P */
+#define CPU_CPU_ID 0xFE18
+
+/** \brief E000, , type: Ifx_CPU_CPXE, CPU Code Protection Execute Enable
+ * Register Set */
+#define CPU_CPXE0 0xE000
+
+/** \brief E004, , type: Ifx_CPU_CPXE, CPU Code Protection Execute Enable
+ * Register Set */
+#define CPU_CPXE1 0xE004
+
+/** \brief E008, , type: Ifx_CPU_CPXE, CPU Code Protection Execute Enable
+ * Register Set */
+#define CPU_CPXE2 0xE008
+
+/** \brief E00C, , type: Ifx_CPU_CPXE, CPU Code Protection Execute Enable
+ * Register Set */
+#define CPU_CPXE3 0xE00C
+
+/** \brief FD0C, , type: Ifx_CPU_CREVT, Core Register Access Event */
+#define CPU_CREVT 0xFD0C
+
+/** \brief FE50, , type: Ifx_CPU_CUS_ID, CPU Customer ID register */
+#define CPU_CUS_ID 0xFE50
+
+/** \brief FF00, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D0 0xFF00
+
+/** \brief FF04, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D1 0xFF04
+
+/** \brief FF28, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D10 0xFF28
+
+/** \brief FF2C, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D11 0xFF2C
+
+/** \brief FF30, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D12 0xFF30
+
+/** \brief FF34, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D13 0xFF34
+
+/** \brief FF38, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D14 0xFF38
+
+/** \brief FF3C, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D15 0xFF3C
+
+/** \brief FF08, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D2 0xFF08
+
+/** \brief FF0C, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D3 0xFF0C
+
+/** \brief FF10, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D4 0xFF10
+
+/** \brief FF14, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D5 0xFF14
+
+/** \brief FF18, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D6 0xFF18
+
+/** \brief FF1C, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D7 0xFF1C
+
+/** \brief FF20, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D8 0xFF20
+
+/** \brief FF24, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D9 0xFF24
+
+/** \brief 9018, , type: Ifx_CPU_DATR, Data Asynchronous Trap Register */
+#define CPU_DATR 0x9018
+
+/** \brief FD00, , type: Ifx_CPU_DBGSR, Debug Status Register */
+#define CPU_DBGSR 0xFD00
+
+/** \brief FD48, , type: Ifx_CPU_DBGTCR, Debug Trap Control Register */
+#define CPU_DBGTCR 0xFD48
+
+/** \brief 9040, , type: Ifx_CPU_DCON0, Data Memory Control Register */
+#define CPU_DCON0 0x9040
+
+/** \brief 9000, , type: Ifx_CPU_DCON2, Data Control Register 2 */
+#define CPU_DCON2 0x9000
+
+/** \brief FD44, , type: Ifx_CPU_DCX, CPU Debug Context Save Area Pointer */
+#define CPU_DCX 0xFD44
+
+/** \brief 901C, , type: Ifx_CPU_DEADD, Data Error Address Register */
+#define CPU_DEADD 0x901C
+
+/** \brief 9020, , type: Ifx_CPU_DIEAR, Data Integrity Error Address Register */
+#define CPU_DIEAR 0x9020
+
+/** \brief 9024, , type: Ifx_CPU_DIETR, Data Integrity Error Trap Register */
+#define CPU_DIETR 0x9024
+
+/** \brief FD40, , type: Ifx_CPU_DMS, CPU Debug Monitor Start Address */
+#define CPU_DMS 0xFD40
+
+/** \brief C000, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR0_L 0xC000
+
+/** \brief C004, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR0_U 0xC004
+
+/** \brief C050, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR10_L 0xC050
+
+/** \brief C054, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR10_U 0xC054
+
+/** \brief C058, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR11_L 0xC058
+
+/** \brief C05C, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR11_U 0xC05C
+
+/** \brief C060, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR12_L 0xC060
+
+/** \brief C064, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR12_U 0xC064
+
+/** \brief C068, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR13_L 0xC068
+
+/** \brief C06C, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR13_U 0xC06C
+
+/** \brief C070, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR14_L 0xC070
+
+/** \brief C074, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR14_U 0xC074
+
+/** \brief C078, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR15_L 0xC078
+
+/** \brief C07C, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR15_U 0xC07C
+
+/** \brief C008, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR1_L 0xC008
+
+/** \brief C00C, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR1_U 0xC00C
+
+/** \brief C010, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR2_L 0xC010
+
+/** \brief C014, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR2_U 0xC014
+
+/** \brief C018, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR3_L 0xC018
+
+/** \brief C01C, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR3_U 0xC01C
+
+/** \brief C020, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR4_L 0xC020
+
+/** \brief C024, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR4_U 0xC024
+
+/** \brief C028, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR5_L 0xC028
+
+/** \brief C02C, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR5_U 0xC02C
+
+/** \brief C030, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR6_L 0xC030
+
+/** \brief C034, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR6_U 0xC034
+
+/** \brief C038, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR7_L 0xC038
+
+/** \brief C03C, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR7_U 0xC03C
+
+/** \brief C040, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR8_L 0xC040
+
+/** \brief C044, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR8_U 0xC044
+
+/** \brief C048, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR9_L 0xC048
+
+/** \brief C04C, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR9_U 0xC04C
+
+/** \brief E010, , type: Ifx_CPU_DPRE, CPU Data Protection Read Enable Register
+ * Set */
+#define CPU_DPRE0 0xE010
+
+/** \brief E014, , type: Ifx_CPU_DPRE, CPU Data Protection Read Enable Register
+ * Set */
+#define CPU_DPRE1 0xE014
+
+/** \brief E018, , type: Ifx_CPU_DPRE, CPU Data Protection Read Enable Register
+ * Set */
+#define CPU_DPRE2 0xE018
+
+/** \brief E01C, , type: Ifx_CPU_DPRE, CPU Data Protection Read Enable Register
+ * Set */
+#define CPU_DPRE3 0xE01C
+
+/** \brief E020, , type: Ifx_CPU_DPWE, CPU Data Protection Write Enable
+ * Register Set */
+#define CPU_DPWE0 0xE020
+
+/** \brief E024, , type: Ifx_CPU_DPWE, CPU Data Protection Write Enable
+ * Register Set */
+#define CPU_DPWE1 0xE024
+
+/** \brief E028, , type: Ifx_CPU_DPWE, CPU Data Protection Write Enable
+ * Register Set */
+#define CPU_DPWE2 0xE028
+
+/** \brief E02C, , type: Ifx_CPU_DPWE, CPU Data Protection Write Enable
+ * Register Set */
+#define CPU_DPWE3 0xE02C
+
+/** \brief 9010, , type: Ifx_CPU_DSTR, Data Synchronous Trap Register */
+#define CPU_DSTR 0x9010
+
+/** \brief FD08, , type: Ifx_CPU_EXEVT, External Event Register */
+#define CPU_EXEVT 0xFD08
+
+/** \brief FE38, , type: Ifx_CPU_FCX, Free CSA List Head Pointer */
+#define CPU_FCX 0xFE38
+
+/** \brief A000, , type: Ifx_CPU_FPU_TRAP_CON, CPU Trap Control Register */
+#define CPU_FPU_TRAP_CON 0xA000
+
+/** \brief A008, , type: Ifx_CPU_FPU_TRAP_OPC, CPU Trapping Instruction Opcode
+ * Register */
+#define CPU_FPU_TRAP_OPC 0xA008
+
+/** \brief A004, , type: Ifx_CPU_FPU_TRAP_PC, CPU Trapping Instruction Program
+ * Counter Register */
+#define CPU_FPU_TRAP_PC 0xA004
+
+/** \brief A010, , type: Ifx_CPU_FPU_TRAP_SRC1, CPU Trapping Instruction
+ * Operand Register */
+#define CPU_FPU_TRAP_SRC1 0xA010
+
+/** \brief A014, , type: Ifx_CPU_FPU_TRAP_SRC2, CPU Trapping Instruction
+ * Operand Register */
+#define CPU_FPU_TRAP_SRC2 0xA014
+
+/** \brief A018, , type: Ifx_CPU_FPU_TRAP_SRC3, Trapping Instruction Operand
+ * Register */
+#define CPU_FPU_TRAP_SRC3 0xA018
+
+/** \brief FC08, , type: Ifx_CPU_ICNT, Instruction Count */
+#define CPU_ICNT 0xFC08
+
+/** \brief FE2C, , type: Ifx_CPU_ICR, Interrupt Control Register */
+#define CPU_ICR 0xFE2C
+
+/** \brief FE28, , type: Ifx_CPU_ISP, Interrupt Stack Pointer */
+#define CPU_ISP 0xFE28
+
+/** \brief FE3C, , type: Ifx_CPU_LCX, Free CSA List Limit Pointer */
+#define CPU_LCX 0xFE3C
+
+/** \brief FC0C, , type: Ifx_CPU_M1CNT, Multi-Count Register 1 */
+#define CPU_M1CNT 0xFC0C
+
+/** \brief FC10, , type: Ifx_CPU_M2CNT, Multi-Count Register 2 */
+#define CPU_M2CNT 0xFC10
+
+/** \brief FC14, , type: Ifx_CPU_M3CNT, Multi-Count Register 3 */
+#define CPU_M3CNT 0xFC14
+
+/** \brief FE08, , type: Ifx_CPU_PC, Program Counter */
+#define CPU_PC 0xFE08
+
+/** \brief 920C, , type: Ifx_CPU_PCON0, Program Control 0 */
+#define CPU_PCON0 0x920C
+
+/** \brief 9204, , type: Ifx_CPU_PCON1, Program Control 1 */
+#define CPU_PCON1 0x9204
+
+/** \brief 9208, , type: Ifx_CPU_PCON2, Program Control 2 */
+#define CPU_PCON2 0x9208
+
+/** \brief FE00, , type: Ifx_CPU_PCXI, Previous Context Information Register */
+#define CPU_PCXI 0xFE00
+
+/** \brief 9210, , type: Ifx_CPU_PIEAR, Program Integrity Error Address
+ * Register */
+#define CPU_PIEAR 0x9210
+
+/** \brief 9214, , type: Ifx_CPU_PIETR, Program Integrity Error Trap Register */
+#define CPU_PIETR 0x9214
+
+/** \brief 8100, , type: Ifx_CPU_PMA0, Data Access CacheabilityRegister */
+#define CPU_PMA0 0x8100
+
+/** \brief 8104, , type: Ifx_CPU_PMA1, Code Access CacheabilityRegister */
+#define CPU_PMA1 0x8104
+
+/** \brief 8108, , type: Ifx_CPU_PMA2, Peripheral Space Identifier register */
+#define CPU_PMA2 0x8108
+
+/** \brief 9200, , type: Ifx_CPU_PSTR, Program Synchronous Trap Register */
+#define CPU_PSTR 0x9200
+
+/** \brief FE04, , type: Ifx_CPU_PSW, Program Status Word */
+#define CPU_PSW 0xFE04
+
+/** \brief 1030, , type: Ifx_CPU_SEGEN, SRI Error Generation Register */
+#define CPU_SEGEN 0x1030
+
+/** \brief 900C, , type: Ifx_CPU_SMACON, SIST Mode Access Control Register */
+#define CPU_SMACON 0x900C
+
+/** \brief FD10, , type: Ifx_CPU_SWEVT, Software Debug Event */
+#define CPU_SWEVT 0xFD10
+
+/** \brief FE14, , type: Ifx_CPU_SYSCON, System Configuration Register */
+#define CPU_SYSCON 0xFE14
+
+/** \brief 8004, , type: Ifx_CPU_TASK_ASI, CPU Task Address Space Identifier
+ * Register */
+#define CPU_TASK_ASI 0x8004
+
+/** \brief E400, , type: Ifx_CPU_TPS_CON, CPU Temporal Protection System
+ * Control Register */
+#define CPU_TPS_CON 0xE400
+
+/** \brief E404, , type: Ifx_CPU_TPS_TIMER, CPU Temporal Protection System
+ * Timer Register */
+#define CPU_TPS_TIMER0 0xE404
+
+/** \brief E408, , type: Ifx_CPU_TPS_TIMER, CPU Temporal Protection System
+ * Timer Register */
+#define CPU_TPS_TIMER1 0xE408
+
+/** \brief E40C, , type: Ifx_CPU_TPS_TIMER, CPU Temporal Protection System
+ * Timer Register */
+#define CPU_TPS_TIMER2 0xE40C
+
+/** \brief F004, , type: Ifx_CPU_TR_ADR, Trigger Address */
+#define CPU_TR0_ADR 0xF004
+
+/** \brief F000, , type: Ifx_CPU_TR_EVT, Trigger Event */
+#define CPU_TR0_EVT 0xF000
+
+/** \brief F00C, , type: Ifx_CPU_TR_ADR, Trigger Address */
+#define CPU_TR1_ADR 0xF00C
+
+/** \brief F008, , type: Ifx_CPU_TR_EVT, Trigger Event */
+#define CPU_TR1_EVT 0xF008
+
+/** \brief F014, , type: Ifx_CPU_TR_ADR, Trigger Address */
+#define CPU_TR2_ADR 0xF014
+
+/** \brief F010, , type: Ifx_CPU_TR_EVT, Trigger Event */
+#define CPU_TR2_EVT 0xF010
+
+/** \brief F01C, , type: Ifx_CPU_TR_ADR, Trigger Address */
+#define CPU_TR3_ADR 0xF01C
+
+/** \brief F018, , type: Ifx_CPU_TR_EVT, Trigger Event */
+#define CPU_TR3_EVT 0xF018
+
+/** \brief F024, , type: Ifx_CPU_TR_ADR, Trigger Address */
+#define CPU_TR4_ADR 0xF024
+
+/** \brief F020, , type: Ifx_CPU_TR_EVT, Trigger Event */
+#define CPU_TR4_EVT 0xF020
+
+/** \brief F02C, , type: Ifx_CPU_TR_ADR, Trigger Address */
+#define CPU_TR5_ADR 0xF02C
+
+/** \brief F028, , type: Ifx_CPU_TR_EVT, Trigger Event */
+#define CPU_TR5_EVT 0xF028
+
+/** \brief F034, , type: Ifx_CPU_TR_ADR, Trigger Address */
+#define CPU_TR6_ADR 0xF034
+
+/** \brief F030, , type: Ifx_CPU_TR_EVT, Trigger Event */
+#define CPU_TR6_EVT 0xF030
+
+/** \brief F03C, , type: Ifx_CPU_TR_ADR, Trigger Address */
+#define CPU_TR7_ADR 0xF03C
+
+/** \brief F038, , type: Ifx_CPU_TR_EVT, Trigger Event */
+#define CPU_TR7_EVT 0xF038
+
+/** \brief FD30, , type: Ifx_CPU_TRIG_ACC, CPU Trigger Address x */
+#define CPU_TRIG_ACC 0xFD30
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Cpu_Cfg_Cpu0_sprot
+ * \{ */
+
+/** \brief E100, CPU Safety Protection Register Access Enable Register A */
+#define CPU0_SPROT_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_ACCENA*)0xF880E100u)
+
+/** \brief E104, CPU Safety Protection Region Access Enable Register B */
+#define CPU0_SPROT_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_ACCENB*)0xF880E104u)
+
+/** \brief E008, CPU Safety Protection Region Access Enable Register A */
+#define CPU0_SPROT_RGN0_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF880E008u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN0_ACCENA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN0_ACCENA.
+*/
+#define CPU0_SPROT_RGNACCENA0 (CPU0_SPROT_RGN0_ACCENA)
+
+/** \brief E00C, CPU Safety Protection Region Access Enable Register B */
+#define CPU0_SPROT_RGN0_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF880E00Cu)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN0_ACCENB.
+* To use register names with standard convension, please use CPU0_SPROT_RGN0_ACCENB.
+*/
+#define CPU0_SPROT_RGNACCENB0 (CPU0_SPROT_RGN0_ACCENB)
+
+/** \brief E000, CPU Safety Protection Region Lower Address Register */
+#define CPU0_SPROT_RGN0_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF880E000u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN0_LA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN0_LA.
+*/
+#define CPU0_SPROT_RGNLA0 (CPU0_SPROT_RGN0_LA)
+
+/** \brief E004, CPU Safety protection Region Upper Address Register */
+#define CPU0_SPROT_RGN0_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF880E004u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN0_UA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN0_UA.
+*/
+#define CPU0_SPROT_RGNUA0 (CPU0_SPROT_RGN0_UA)
+
+/** \brief E018, CPU Safety Protection Region Access Enable Register A */
+#define CPU0_SPROT_RGN1_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF880E018u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN1_ACCENA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN1_ACCENA.
+*/
+#define CPU0_SPROT_RGNACCENA1 (CPU0_SPROT_RGN1_ACCENA)
+
+/** \brief E01C, CPU Safety Protection Region Access Enable Register B */
+#define CPU0_SPROT_RGN1_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF880E01Cu)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN1_ACCENB.
+* To use register names with standard convension, please use CPU0_SPROT_RGN1_ACCENB.
+*/
+#define CPU0_SPROT_RGNACCENB1 (CPU0_SPROT_RGN1_ACCENB)
+
+/** \brief E010, CPU Safety Protection Region Lower Address Register */
+#define CPU0_SPROT_RGN1_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF880E010u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN1_LA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN1_LA.
+*/
+#define CPU0_SPROT_RGNLA1 (CPU0_SPROT_RGN1_LA)
+
+/** \brief E014, CPU Safety protection Region Upper Address Register */
+#define CPU0_SPROT_RGN1_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF880E014u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN1_UA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN1_UA.
+*/
+#define CPU0_SPROT_RGNUA1 (CPU0_SPROT_RGN1_UA)
+
+/** \brief E028, CPU Safety Protection Region Access Enable Register A */
+#define CPU0_SPROT_RGN2_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF880E028u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN2_ACCENA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN2_ACCENA.
+*/
+#define CPU0_SPROT_RGNACCENA2 (CPU0_SPROT_RGN2_ACCENA)
+
+/** \brief E02C, CPU Safety Protection Region Access Enable Register B */
+#define CPU0_SPROT_RGN2_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF880E02Cu)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN2_ACCENB.
+* To use register names with standard convension, please use CPU0_SPROT_RGN2_ACCENB.
+*/
+#define CPU0_SPROT_RGNACCENB2 (CPU0_SPROT_RGN2_ACCENB)
+
+/** \brief E020, CPU Safety Protection Region Lower Address Register */
+#define CPU0_SPROT_RGN2_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF880E020u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN2_LA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN2_LA.
+*/
+#define CPU0_SPROT_RGNLA2 (CPU0_SPROT_RGN2_LA)
+
+/** \brief E024, CPU Safety protection Region Upper Address Register */
+#define CPU0_SPROT_RGN2_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF880E024u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN2_UA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN2_UA.
+*/
+#define CPU0_SPROT_RGNUA2 (CPU0_SPROT_RGN2_UA)
+
+/** \brief E038, CPU Safety Protection Region Access Enable Register A */
+#define CPU0_SPROT_RGN3_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF880E038u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN3_ACCENA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN3_ACCENA.
+*/
+#define CPU0_SPROT_RGNACCENA3 (CPU0_SPROT_RGN3_ACCENA)
+
+/** \brief E03C, CPU Safety Protection Region Access Enable Register B */
+#define CPU0_SPROT_RGN3_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF880E03Cu)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN3_ACCENB.
+* To use register names with standard convension, please use CPU0_SPROT_RGN3_ACCENB.
+*/
+#define CPU0_SPROT_RGNACCENB3 (CPU0_SPROT_RGN3_ACCENB)
+
+/** \brief E030, CPU Safety Protection Region Lower Address Register */
+#define CPU0_SPROT_RGN3_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF880E030u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN3_LA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN3_LA.
+*/
+#define CPU0_SPROT_RGNLA3 (CPU0_SPROT_RGN3_LA)
+
+/** \brief E034, CPU Safety protection Region Upper Address Register */
+#define CPU0_SPROT_RGN3_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF880E034u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN3_UA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN3_UA.
+*/
+#define CPU0_SPROT_RGNUA3 (CPU0_SPROT_RGN3_UA)
+
+/** \brief E048, CPU Safety Protection Region Access Enable Register A */
+#define CPU0_SPROT_RGN4_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF880E048u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN4_ACCENA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN4_ACCENA.
+*/
+#define CPU0_SPROT_RGNACCENA4 (CPU0_SPROT_RGN4_ACCENA)
+
+/** \brief E04C, CPU Safety Protection Region Access Enable Register B */
+#define CPU0_SPROT_RGN4_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF880E04Cu)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN4_ACCENB.
+* To use register names with standard convension, please use CPU0_SPROT_RGN4_ACCENB.
+*/
+#define CPU0_SPROT_RGNACCENB4 (CPU0_SPROT_RGN4_ACCENB)
+
+/** \brief E040, CPU Safety Protection Region Lower Address Register */
+#define CPU0_SPROT_RGN4_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF880E040u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN4_LA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN4_LA.
+*/
+#define CPU0_SPROT_RGNLA4 (CPU0_SPROT_RGN4_LA)
+
+/** \brief E044, CPU Safety protection Region Upper Address Register */
+#define CPU0_SPROT_RGN4_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF880E044u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN4_UA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN4_UA.
+*/
+#define CPU0_SPROT_RGNUA4 (CPU0_SPROT_RGN4_UA)
+
+/** \brief E058, CPU Safety Protection Region Access Enable Register A */
+#define CPU0_SPROT_RGN5_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF880E058u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN5_ACCENA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN5_ACCENA.
+*/
+#define CPU0_SPROT_RGNACCENA5 (CPU0_SPROT_RGN5_ACCENA)
+
+/** \brief E05C, CPU Safety Protection Region Access Enable Register B */
+#define CPU0_SPROT_RGN5_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF880E05Cu)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN5_ACCENB.
+* To use register names with standard convension, please use CPU0_SPROT_RGN5_ACCENB.
+*/
+#define CPU0_SPROT_RGNACCENB5 (CPU0_SPROT_RGN5_ACCENB)
+
+/** \brief E050, CPU Safety Protection Region Lower Address Register */
+#define CPU0_SPROT_RGN5_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF880E050u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN5_LA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN5_LA.
+*/
+#define CPU0_SPROT_RGNLA5 (CPU0_SPROT_RGN5_LA)
+
+/** \brief E054, CPU Safety protection Region Upper Address Register */
+#define CPU0_SPROT_RGN5_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF880E054u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN5_UA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN5_UA.
+*/
+#define CPU0_SPROT_RGNUA5 (CPU0_SPROT_RGN5_UA)
+
+/** \brief E068, CPU Safety Protection Region Access Enable Register A */
+#define CPU0_SPROT_RGN6_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF880E068u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN6_ACCENA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN6_ACCENA.
+*/
+#define CPU0_SPROT_RGNACCENA6 (CPU0_SPROT_RGN6_ACCENA)
+
+/** \brief E06C, CPU Safety Protection Region Access Enable Register B */
+#define CPU0_SPROT_RGN6_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF880E06Cu)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN6_ACCENB.
+* To use register names with standard convension, please use CPU0_SPROT_RGN6_ACCENB.
+*/
+#define CPU0_SPROT_RGNACCENB6 (CPU0_SPROT_RGN6_ACCENB)
+
+/** \brief E060, CPU Safety Protection Region Lower Address Register */
+#define CPU0_SPROT_RGN6_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF880E060u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN6_LA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN6_LA.
+*/
+#define CPU0_SPROT_RGNLA6 (CPU0_SPROT_RGN6_LA)
+
+/** \brief E064, CPU Safety protection Region Upper Address Register */
+#define CPU0_SPROT_RGN6_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF880E064u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN6_UA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN6_UA.
+*/
+#define CPU0_SPROT_RGNUA6 (CPU0_SPROT_RGN6_UA)
+
+/** \brief E078, CPU Safety Protection Region Access Enable Register A */
+#define CPU0_SPROT_RGN7_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF880E078u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN7_ACCENA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN7_ACCENA.
+*/
+#define CPU0_SPROT_RGNACCENA7 (CPU0_SPROT_RGN7_ACCENA)
+
+/** \brief E07C, CPU Safety Protection Region Access Enable Register B */
+#define CPU0_SPROT_RGN7_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF880E07Cu)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN7_ACCENB.
+* To use register names with standard convension, please use CPU0_SPROT_RGN7_ACCENB.
+*/
+#define CPU0_SPROT_RGNACCENB7 (CPU0_SPROT_RGN7_ACCENB)
+
+/** \brief E070, CPU Safety Protection Region Lower Address Register */
+#define CPU0_SPROT_RGN7_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF880E070u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN7_LA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN7_LA.
+*/
+#define CPU0_SPROT_RGNLA7 (CPU0_SPROT_RGN7_LA)
+
+/** \brief E074, CPU Safety protection Region Upper Address Register */
+#define CPU0_SPROT_RGN7_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF880E074u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN7_UA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN7_UA.
+*/
+#define CPU0_SPROT_RGNUA7 (CPU0_SPROT_RGN7_UA)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Cpu_Cfg_Cpu1_sprot
+ * \{ */
+
+/** \brief E100, CPU Safety Protection Register Access Enable Register A */
+#define CPU1_SPROT_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_ACCENA*)0xF882E100u)
+
+/** \brief E104, CPU Safety Protection Region Access Enable Register B */
+#define CPU1_SPROT_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_ACCENB*)0xF882E104u)
+
+/** \brief E008, CPU Safety Protection Region Access Enable Register A */
+#define CPU1_SPROT_RGN0_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF882E008u)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN0_ACCENA.
+* To use register names with standard convension, please use CPU1_SPROT_RGN0_ACCENA.
+*/
+#define CPU1_SPROT_RGNACCENA0 (CPU1_SPROT_RGN0_ACCENA)
+
+/** \brief E00C, CPU Safety Protection Region Access Enable Register B */
+#define CPU1_SPROT_RGN0_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF882E00Cu)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN0_ACCENB.
+* To use register names with standard convension, please use CPU1_SPROT_RGN0_ACCENB.
+*/
+#define CPU1_SPROT_RGNACCENB0 (CPU1_SPROT_RGN0_ACCENB)
+
+/** \brief E000, CPU Safety Protection Region Lower Address Register */
+#define CPU1_SPROT_RGN0_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF882E000u)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN0_LA.
+* To use register names with standard convension, please use CPU1_SPROT_RGN0_LA.
+*/
+#define CPU1_SPROT_RGNLA0 (CPU1_SPROT_RGN0_LA)
+
+/** \brief E004, CPU Safety protection Region Upper Address Register */
+#define CPU1_SPROT_RGN0_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF882E004u)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN0_UA.
+* To use register names with standard convension, please use CPU1_SPROT_RGN0_UA.
+*/
+#define CPU1_SPROT_RGNUA0 (CPU1_SPROT_RGN0_UA)
+
+/** \brief E018, CPU Safety Protection Region Access Enable Register A */
+#define CPU1_SPROT_RGN1_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF882E018u)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN1_ACCENA.
+* To use register names with standard convension, please use CPU1_SPROT_RGN1_ACCENA.
+*/
+#define CPU1_SPROT_RGNACCENA1 (CPU1_SPROT_RGN1_ACCENA)
+
+/** \brief E01C, CPU Safety Protection Region Access Enable Register B */
+#define CPU1_SPROT_RGN1_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF882E01Cu)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN1_ACCENB.
+* To use register names with standard convension, please use CPU1_SPROT_RGN1_ACCENB.
+*/
+#define CPU1_SPROT_RGNACCENB1 (CPU1_SPROT_RGN1_ACCENB)
+
+/** \brief E010, CPU Safety Protection Region Lower Address Register */
+#define CPU1_SPROT_RGN1_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF882E010u)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN1_LA.
+* To use register names with standard convension, please use CPU1_SPROT_RGN1_LA.
+*/
+#define CPU1_SPROT_RGNLA1 (CPU1_SPROT_RGN1_LA)
+
+/** \brief E014, CPU Safety protection Region Upper Address Register */
+#define CPU1_SPROT_RGN1_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF882E014u)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN1_UA.
+* To use register names with standard convension, please use CPU1_SPROT_RGN1_UA.
+*/
+#define CPU1_SPROT_RGNUA1 (CPU1_SPROT_RGN1_UA)
+
+/** \brief E028, CPU Safety Protection Region Access Enable Register A */
+#define CPU1_SPROT_RGN2_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF882E028u)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN2_ACCENA.
+* To use register names with standard convension, please use CPU1_SPROT_RGN2_ACCENA.
+*/
+#define CPU1_SPROT_RGNACCENA2 (CPU1_SPROT_RGN2_ACCENA)
+
+/** \brief E02C, CPU Safety Protection Region Access Enable Register B */
+#define CPU1_SPROT_RGN2_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF882E02Cu)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN2_ACCENB.
+* To use register names with standard convension, please use CPU1_SPROT_RGN2_ACCENB.
+*/
+#define CPU1_SPROT_RGNACCENB2 (CPU1_SPROT_RGN2_ACCENB)
+
+/** \brief E020, CPU Safety Protection Region Lower Address Register */
+#define CPU1_SPROT_RGN2_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF882E020u)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN2_LA.
+* To use register names with standard convension, please use CPU1_SPROT_RGN2_LA.
+*/
+#define CPU1_SPROT_RGNLA2 (CPU1_SPROT_RGN2_LA)
+
+/** \brief E024, CPU Safety protection Region Upper Address Register */
+#define CPU1_SPROT_RGN2_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF882E024u)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN2_UA.
+* To use register names with standard convension, please use CPU1_SPROT_RGN2_UA.
+*/
+#define CPU1_SPROT_RGNUA2 (CPU1_SPROT_RGN2_UA)
+
+/** \brief E038, CPU Safety Protection Region Access Enable Register A */
+#define CPU1_SPROT_RGN3_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF882E038u)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN3_ACCENA.
+* To use register names with standard convension, please use CPU1_SPROT_RGN3_ACCENA.
+*/
+#define CPU1_SPROT_RGNACCENA3 (CPU1_SPROT_RGN3_ACCENA)
+
+/** \brief E03C, CPU Safety Protection Region Access Enable Register B */
+#define CPU1_SPROT_RGN3_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF882E03Cu)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN3_ACCENB.
+* To use register names with standard convension, please use CPU1_SPROT_RGN3_ACCENB.
+*/
+#define CPU1_SPROT_RGNACCENB3 (CPU1_SPROT_RGN3_ACCENB)
+
+/** \brief E030, CPU Safety Protection Region Lower Address Register */
+#define CPU1_SPROT_RGN3_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF882E030u)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN3_LA.
+* To use register names with standard convension, please use CPU1_SPROT_RGN3_LA.
+*/
+#define CPU1_SPROT_RGNLA3 (CPU1_SPROT_RGN3_LA)
+
+/** \brief E034, CPU Safety protection Region Upper Address Register */
+#define CPU1_SPROT_RGN3_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF882E034u)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN3_UA.
+* To use register names with standard convension, please use CPU1_SPROT_RGN3_UA.
+*/
+#define CPU1_SPROT_RGNUA3 (CPU1_SPROT_RGN3_UA)
+
+/** \brief E048, CPU Safety Protection Region Access Enable Register A */
+#define CPU1_SPROT_RGN4_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF882E048u)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN4_ACCENA.
+* To use register names with standard convension, please use CPU1_SPROT_RGN4_ACCENA.
+*/
+#define CPU1_SPROT_RGNACCENA4 (CPU1_SPROT_RGN4_ACCENA)
+
+/** \brief E04C, CPU Safety Protection Region Access Enable Register B */
+#define CPU1_SPROT_RGN4_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF882E04Cu)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN4_ACCENB.
+* To use register names with standard convension, please use CPU1_SPROT_RGN4_ACCENB.
+*/
+#define CPU1_SPROT_RGNACCENB4 (CPU1_SPROT_RGN4_ACCENB)
+
+/** \brief E040, CPU Safety Protection Region Lower Address Register */
+#define CPU1_SPROT_RGN4_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF882E040u)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN4_LA.
+* To use register names with standard convension, please use CPU1_SPROT_RGN4_LA.
+*/
+#define CPU1_SPROT_RGNLA4 (CPU1_SPROT_RGN4_LA)
+
+/** \brief E044, CPU Safety protection Region Upper Address Register */
+#define CPU1_SPROT_RGN4_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF882E044u)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN4_UA.
+* To use register names with standard convension, please use CPU1_SPROT_RGN4_UA.
+*/
+#define CPU1_SPROT_RGNUA4 (CPU1_SPROT_RGN4_UA)
+
+/** \brief E058, CPU Safety Protection Region Access Enable Register A */
+#define CPU1_SPROT_RGN5_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF882E058u)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN5_ACCENA.
+* To use register names with standard convension, please use CPU1_SPROT_RGN5_ACCENA.
+*/
+#define CPU1_SPROT_RGNACCENA5 (CPU1_SPROT_RGN5_ACCENA)
+
+/** \brief E05C, CPU Safety Protection Region Access Enable Register B */
+#define CPU1_SPROT_RGN5_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF882E05Cu)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN5_ACCENB.
+* To use register names with standard convension, please use CPU1_SPROT_RGN5_ACCENB.
+*/
+#define CPU1_SPROT_RGNACCENB5 (CPU1_SPROT_RGN5_ACCENB)
+
+/** \brief E050, CPU Safety Protection Region Lower Address Register */
+#define CPU1_SPROT_RGN5_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF882E050u)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN5_LA.
+* To use register names with standard convension, please use CPU1_SPROT_RGN5_LA.
+*/
+#define CPU1_SPROT_RGNLA5 (CPU1_SPROT_RGN5_LA)
+
+/** \brief E054, CPU Safety protection Region Upper Address Register */
+#define CPU1_SPROT_RGN5_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF882E054u)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN5_UA.
+* To use register names with standard convension, please use CPU1_SPROT_RGN5_UA.
+*/
+#define CPU1_SPROT_RGNUA5 (CPU1_SPROT_RGN5_UA)
+
+/** \brief E068, CPU Safety Protection Region Access Enable Register A */
+#define CPU1_SPROT_RGN6_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF882E068u)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN6_ACCENA.
+* To use register names with standard convension, please use CPU1_SPROT_RGN6_ACCENA.
+*/
+#define CPU1_SPROT_RGNACCENA6 (CPU1_SPROT_RGN6_ACCENA)
+
+/** \brief E06C, CPU Safety Protection Region Access Enable Register B */
+#define CPU1_SPROT_RGN6_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF882E06Cu)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN6_ACCENB.
+* To use register names with standard convension, please use CPU1_SPROT_RGN6_ACCENB.
+*/
+#define CPU1_SPROT_RGNACCENB6 (CPU1_SPROT_RGN6_ACCENB)
+
+/** \brief E060, CPU Safety Protection Region Lower Address Register */
+#define CPU1_SPROT_RGN6_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF882E060u)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN6_LA.
+* To use register names with standard convension, please use CPU1_SPROT_RGN6_LA.
+*/
+#define CPU1_SPROT_RGNLA6 (CPU1_SPROT_RGN6_LA)
+
+/** \brief E064, CPU Safety protection Region Upper Address Register */
+#define CPU1_SPROT_RGN6_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF882E064u)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN6_UA.
+* To use register names with standard convension, please use CPU1_SPROT_RGN6_UA.
+*/
+#define CPU1_SPROT_RGNUA6 (CPU1_SPROT_RGN6_UA)
+
+/** \brief E078, CPU Safety Protection Region Access Enable Register A */
+#define CPU1_SPROT_RGN7_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF882E078u)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN7_ACCENA.
+* To use register names with standard convension, please use CPU1_SPROT_RGN7_ACCENA.
+*/
+#define CPU1_SPROT_RGNACCENA7 (CPU1_SPROT_RGN7_ACCENA)
+
+/** \brief E07C, CPU Safety Protection Region Access Enable Register B */
+#define CPU1_SPROT_RGN7_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF882E07Cu)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN7_ACCENB.
+* To use register names with standard convension, please use CPU1_SPROT_RGN7_ACCENB.
+*/
+#define CPU1_SPROT_RGNACCENB7 (CPU1_SPROT_RGN7_ACCENB)
+
+/** \brief E070, CPU Safety Protection Region Lower Address Register */
+#define CPU1_SPROT_RGN7_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF882E070u)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN7_LA.
+* To use register names with standard convension, please use CPU1_SPROT_RGN7_LA.
+*/
+#define CPU1_SPROT_RGNLA7 (CPU1_SPROT_RGN7_LA)
+
+/** \brief E074, CPU Safety protection Region Upper Address Register */
+#define CPU1_SPROT_RGN7_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF882E074u)
+
+/** Alias (User Manual Name) for CPU1_SPROT_RGN7_UA.
+* To use register names with standard convension, please use CPU1_SPROT_RGN7_UA.
+*/
+#define CPU1_SPROT_RGNUA7 (CPU1_SPROT_RGN7_UA)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXCPU_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCpu_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCpu_regdef.h
new file mode 100644
index 0000000..418a712
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxCpu_regdef.h
@@ -0,0 +1,1427 @@
+/**
+ * \file IfxCpu_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Cpu Cpu
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Cpu_Bitfields Bitfields
+ * \ingroup IfxLld_Cpu
+ *
+ * \defgroup IfxLld_Cpu_union Union
+ * \ingroup IfxLld_Cpu
+ *
+ * \defgroup IfxLld_Cpu_struct Struct
+ * \ingroup IfxLld_Cpu
+ *
+ */
+#ifndef IFXCPU_REGDEF_H
+#define IFXCPU_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Cpu_Bitfields
+ * \{ */
+
+/** \brief Address General Purpose Register */
+typedef struct _Ifx_CPU_A_Bits
+{
+ Ifx_Strict_32Bit ADDR:32; /**< \brief [31:0] Address Register (rw) */
+} Ifx_CPU_A_Bits;
+
+/** \brief Base Interrupt Vector Table Pointer */
+typedef struct _Ifx_CPU_BIV_Bits
+{
+ Ifx_Strict_32Bit VSS:1; /**< \brief [0:0] Vector Spacing Select (rw) */
+ Ifx_Strict_32Bit BIV:31; /**< \brief [31:1] Base Address of Interrupt Vector Table (rw) */
+} Ifx_CPU_BIV_Bits;
+
+/** \brief Base Trap Vector Table Pointer */
+typedef struct _Ifx_CPU_BTV_Bits
+{
+ Ifx_Strict_32Bit reserved_0:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit BTV:31; /**< \brief [31:1] Base Address of Trap Vector Table (rw) */
+} Ifx_CPU_BTV_Bits;
+
+/** \brief CPU Clock Cycle Count */
+typedef struct _Ifx_CPU_CCNT_Bits
+{
+ Ifx_Strict_32Bit CountValue:31; /**< \brief [30:0] Count Value (rw) */
+ Ifx_Strict_32Bit SOvf:1; /**< \brief [31:31] Sticky Overflow Bit (rw) */
+} Ifx_CPU_CCNT_Bits;
+
+/** \brief Counter Control */
+typedef struct _Ifx_CPU_CCTRL_Bits
+{
+ Ifx_Strict_32Bit CM:1; /**< \brief [0:0] Counter Mode (rw) */
+ Ifx_Strict_32Bit CE:1; /**< \brief [1:1] Count Enable (rw) */
+ Ifx_Strict_32Bit M1:3; /**< \brief [4:2] M1CNT Configuration (rw) */
+ Ifx_Strict_32Bit M2:3; /**< \brief [7:5] M2CNT Configuration (rw) */
+ Ifx_Strict_32Bit M3:3; /**< \brief [10:8] M3CNT Configuration (rw) */
+ Ifx_Strict_32Bit reserved_11:21; /**< \brief \internal Reserved */
+} Ifx_CPU_CCTRL_Bits;
+
+/** \brief Compatibility Control Register */
+typedef struct _Ifx_CPU_COMPAT_Bits
+{
+ Ifx_Strict_32Bit reserved_0:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit RM:1; /**< \brief [3:3] Rounding Mode Compatibility (rw) */
+ Ifx_Strict_32Bit SP:1; /**< \brief [4:4] SYSCON Safety Protection Mode Compatibility (rw) */
+ Ifx_Strict_32Bit reserved_5:27; /**< \brief \internal Reserved */
+} Ifx_CPU_COMPAT_Bits;
+
+/** \brief CPU Core Identification Register */
+typedef struct _Ifx_CPU_CORE_ID_Bits
+{
+ Ifx_Strict_32Bit CORE_ID:3; /**< \brief [2:0] Core Identification Number (rw) */
+ Ifx_Strict_32Bit reserved_3:29; /**< \brief \internal Reserved */
+} Ifx_CPU_CORE_ID_Bits;
+
+/** \brief CPU Code Protection Range Lower Bound Register */
+typedef struct _Ifx_CPU_CPR_L_Bits
+{
+ Ifx_Strict_32Bit reserved_0:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit LOWBND:29; /**< \brief [31:3] CPRy Lower Boundary Address (rw) */
+} Ifx_CPU_CPR_L_Bits;
+
+/** \brief CPU Code Protection Range Upper Bound Register */
+typedef struct _Ifx_CPU_CPR_U_Bits
+{
+ Ifx_Strict_32Bit reserved_0:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit UPPBND:29; /**< \brief [31:3] CPR0_m Upper Boundary Address (rw) */
+} Ifx_CPU_CPR_U_Bits;
+
+/** \brief CPU Identification Register TC1.6P */
+typedef struct _Ifx_CPU_CPU_ID_Bits
+{
+ Ifx_Strict_32Bit MODREV:8; /**< \brief [7:0] Revision Number (r) */
+ Ifx_Strict_32Bit MOD_32B:8; /**< \brief [15:8] 32-Bit Module Enable (r) */
+ Ifx_Strict_32Bit MOD:16; /**< \brief [31:16] Module Identification Number (r) */
+} Ifx_CPU_CPU_ID_Bits;
+
+/** \brief CPU Code Protection Execute Enable Register Set */
+typedef struct _Ifx_CPU_CPXE_Bits
+{
+ Ifx_Strict_32Bit XE:8; /**< \brief [7:0] Execute Enable Range select (rw) */
+ Ifx_Strict_32Bit reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_CPU_CPXE_Bits;
+
+/** \brief Core Register Access Event */
+typedef struct _Ifx_CPU_CREVT_Bits
+{
+ Ifx_Strict_32Bit EVTA:3; /**< \brief [2:0] Event Associated (rw) */
+ Ifx_Strict_32Bit BBM:1; /**< \brief [3:3] Break Before Make (BBM) or Break After Make (BAM) Selection (rw) */
+ Ifx_Strict_32Bit BOD:1; /**< \brief [4:4] Breakout Disable (rw) */
+ Ifx_Strict_32Bit SUSP:1; /**< \brief [5:5] CDC Suspend-Out Signal State (rw) */
+ Ifx_Strict_32Bit CNT:2; /**< \brief [7:6] Counter (rw) */
+ Ifx_Strict_32Bit reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_CPU_CREVT_Bits;
+
+/** \brief CPU Customer ID register */
+typedef struct _Ifx_CPU_CUS_ID_Bits
+{
+ Ifx_Strict_32Bit CID:3; /**< \brief [2:0] Customer ID (r) */
+ Ifx_Strict_32Bit reserved_3:29; /**< \brief \internal Reserved */
+} Ifx_CPU_CUS_ID_Bits;
+
+/** \brief Data General Purpose Register */
+typedef struct _Ifx_CPU_D_Bits
+{
+ Ifx_Strict_32Bit DATA:32; /**< \brief [31:0] Data Register (rw) */
+} Ifx_CPU_D_Bits;
+
+/** \brief Data Asynchronous Trap Register */
+typedef struct _Ifx_CPU_DATR_Bits
+{
+ Ifx_Strict_32Bit reserved_0:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SBE:1; /**< \brief [3:3] Store Bus Error (rwh) */
+ Ifx_Strict_32Bit reserved_4:5; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit CWE:1; /**< \brief [9:9] Cache Writeback Error (rwh) */
+ Ifx_Strict_32Bit CFE:1; /**< \brief [10:10] Cache Flush Error (rwh) */
+ Ifx_Strict_32Bit reserved_11:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SOE:1; /**< \brief [14:14] Store Overlay Error (rwh) */
+ Ifx_Strict_32Bit SME:1; /**< \brief [15:15] Store MIST Error (rwh) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CPU_DATR_Bits;
+
+/** \brief Debug Status Register */
+typedef struct _Ifx_CPU_DBGSR_Bits
+{
+ Ifx_Strict_32Bit DE:1; /**< \brief [0:0] Debug Enable (rh) */
+ Ifx_Strict_32Bit HALT:2; /**< \brief [2:1] CPU Halt Request / Status Field (rwh) */
+ Ifx_Strict_32Bit SIH:1; /**< \brief [3:3] Suspend-in Halt (rh) */
+ Ifx_Strict_32Bit SUSP:1; /**< \brief [4:4] Current State of the Core Suspend-Out Signal (rwh) */
+ Ifx_Strict_32Bit reserved_5:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit PREVSUSP:1; /**< \brief [6:6] Previous State of Core Suspend-Out Signal (rh) */
+ Ifx_Strict_32Bit PEVT:1; /**< \brief [7:7] Posted Event (rwh) */
+ Ifx_Strict_32Bit EVTSRC:5; /**< \brief [12:8] Event Source (rh) */
+ Ifx_Strict_32Bit reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_CPU_DBGSR_Bits;
+
+/** \brief Debug Trap Control Register */
+typedef struct _Ifx_CPU_DBGTCR_Bits
+{
+ Ifx_Strict_32Bit DTA:1; /**< \brief [0:0] Debug Trap Active Bit (rwh) */
+ Ifx_Strict_32Bit reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_CPU_DBGTCR_Bits;
+
+/** \brief Data Memory Control Register */
+typedef struct _Ifx_CPU_DCON0_Bits
+{
+ Ifx_Strict_32Bit reserved_0:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit DCBYP:1; /**< \brief [1:1] Data Cache Bypass (rw) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_CPU_DCON0_Bits;
+
+/** \brief Data Control Register 2 */
+typedef struct _Ifx_CPU_DCON2_Bits
+{
+ Ifx_Strict_32Bit DCACHE_SZE:16; /**< \brief [15:0] Data Cache Size (r) */
+ Ifx_Strict_32Bit DSCRATCH_SZE:16; /**< \brief [31:16] Data Scratch Size (r) */
+} Ifx_CPU_DCON2_Bits;
+
+/** \brief CPU Debug Context Save Area Pointer */
+typedef struct _Ifx_CPU_DCX_Bits
+{
+ Ifx_Strict_32Bit reserved_0:6; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit DCXValue:26; /**< \brief [31:6] Debug Context Save Area Pointer (rw) */
+} Ifx_CPU_DCX_Bits;
+
+/** \brief Data Error Address Register */
+typedef struct _Ifx_CPU_DEADD_Bits
+{
+ Ifx_Strict_32Bit ERROR_ADDRESS:32; /**< \brief [31:0] Error Address (rh) */
+} Ifx_CPU_DEADD_Bits;
+
+/** \brief Data Integrity Error Address Register */
+typedef struct _Ifx_CPU_DIEAR_Bits
+{
+ Ifx_Strict_32Bit TA:32; /**< \brief [31:0] Transaction Address (rh) */
+} Ifx_CPU_DIEAR_Bits;
+
+/** \brief Data Integrity Error Trap Register */
+typedef struct _Ifx_CPU_DIETR_Bits
+{
+ Ifx_Strict_32Bit IED:1; /**< \brief [0:0] Integrity Error Detected (rwh) */
+ Ifx_Strict_32Bit IE_T:1; /**< \brief [1:1] Integrity Error - Tag Memory (rh) */
+ Ifx_Strict_32Bit IE_C:1; /**< \brief [2:2] Integrity Error - Cache Memory (rh) */
+ Ifx_Strict_32Bit IE_S:1; /**< \brief [3:3] Integrity Error - Scratchpad Memory (rh) */
+ Ifx_Strict_32Bit IE_BI:1; /**< \brief [4:4] Integrity Error - Bus Integrity (rh) */
+ Ifx_Strict_32Bit E_INFO:6; /**< \brief [10:5] Error Information (rh) */
+ Ifx_Strict_32Bit IE_DUAL:1; /**< \brief [11:11] Dual Bit Error Detected (rh) */
+ Ifx_Strict_32Bit IE_SP:1; /**< \brief [12:12] Safety Protection Error Detected (rh) */
+ Ifx_Strict_32Bit IE_BS:1; /**< \brief [13:13] Bus Slave Access Indicator (rh) */
+ Ifx_Strict_32Bit reserved_14:18; /**< \brief \internal Reserved */
+} Ifx_CPU_DIETR_Bits;
+
+/** \brief CPU Debug Monitor Start Address */
+typedef struct _Ifx_CPU_DMS_Bits
+{
+ Ifx_Strict_32Bit reserved_0:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit DMSValue:31; /**< \brief [31:1] Debug Monitor Start Address (rw) */
+} Ifx_CPU_DMS_Bits;
+
+/** \brief CPU Data Protection Range, Lower Bound Register */
+typedef struct _Ifx_CPU_DPR_L_Bits
+{
+ Ifx_Strict_32Bit reserved_0:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit LOWBND:29; /**< \brief [31:3] DPRy Lower Boundary Address (rw) */
+} Ifx_CPU_DPR_L_Bits;
+
+/** \brief CPU Data Protection Range, Upper Bound Register */
+typedef struct _Ifx_CPU_DPR_U_Bits
+{
+ Ifx_Strict_32Bit reserved_0:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit UPPBND:29; /**< \brief [31:3] DPRy Upper Boundary Address (rw) */
+} Ifx_CPU_DPR_U_Bits;
+
+/** \brief CPU Data Protection Read Enable Register Set */
+typedef struct _Ifx_CPU_DPRE_Bits
+{
+ Ifx_Strict_32Bit RE:16; /**< \brief [15:0] Read Enable Range Select (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CPU_DPRE_Bits;
+
+/** \brief CPU Data Protection Write Enable Register Set */
+typedef struct _Ifx_CPU_DPWE_Bits
+{
+ Ifx_Strict_32Bit WE:16; /**< \brief [15:0] Write Enable Range Select (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CPU_DPWE_Bits;
+
+/** \brief Data Synchronous Trap Register */
+typedef struct _Ifx_CPU_DSTR_Bits
+{
+ Ifx_Strict_32Bit SRE:1; /**< \brief [0:0] Scratch Range Error (rwh) */
+ Ifx_Strict_32Bit GAE:1; /**< \brief [1:1] Global Address Error (rwh) */
+ Ifx_Strict_32Bit LBE:1; /**< \brief [2:2] Load Bus Error (rwh) */
+ Ifx_Strict_32Bit reserved_3:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit CRE:1; /**< \brief [6:6] Cache Refill Error (rwh) */
+ Ifx_Strict_32Bit reserved_7:7; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit DTME:1; /**< \brief [14:14] DTAG MSIST Error (rwh) */
+ Ifx_Strict_32Bit LOE:1; /**< \brief [15:15] Load Overlay Error (rwh) */
+ Ifx_Strict_32Bit SDE:1; /**< \brief [16:16] Segment Difference Error (rwh) */
+ Ifx_Strict_32Bit SCE:1; /**< \brief [17:17] Segment Crossing Error (rwh) */
+ Ifx_Strict_32Bit CAC:1; /**< \brief [18:18] CSFR Access Error (rwh) */
+ Ifx_Strict_32Bit MPE:1; /**< \brief [19:19] Memory Protection Error (rwh) */
+ Ifx_Strict_32Bit CLE:1; /**< \brief [20:20] Context Location Error (rwh) */
+ Ifx_Strict_32Bit reserved_21:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit ALN:1; /**< \brief [24:24] Alignment Error (rwh) */
+ Ifx_Strict_32Bit reserved_25:7; /**< \brief \internal Reserved */
+} Ifx_CPU_DSTR_Bits;
+
+/** \brief External Event Register */
+typedef struct _Ifx_CPU_EXEVT_Bits
+{
+ Ifx_Strict_32Bit EVTA:3; /**< \brief [2:0] Event Associated (rw) */
+ Ifx_Strict_32Bit BBM:1; /**< \brief [3:3] Break Before Make (BBM) or Break After Make (BAM) Selection (rw) */
+ Ifx_Strict_32Bit BOD:1; /**< \brief [4:4] Breakout Disable (rw) */
+ Ifx_Strict_32Bit SUSP:1; /**< \brief [5:5] CDC Suspend-Out Signal State (rw) */
+ Ifx_Strict_32Bit CNT:2; /**< \brief [7:6] Counter (rw) */
+ Ifx_Strict_32Bit reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_CPU_EXEVT_Bits;
+
+/** \brief Free CSA List Head Pointer */
+typedef struct _Ifx_CPU_FCX_Bits
+{
+ Ifx_Strict_32Bit FCXO:16; /**< \brief [15:0] FCX Offset Address Field (rw) */
+ Ifx_Strict_32Bit FCXS:4; /**< \brief [19:16] FCX Segment Address Field (rw) */
+ Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_CPU_FCX_Bits;
+
+/** \brief CPU Trap Control Register */
+typedef struct _Ifx_CPU_FPU_TRAP_CON_Bits
+{
+ Ifx_Strict_32Bit TST:1; /**< \brief [0:0] Trap Status (rh) */
+ Ifx_Strict_32Bit TCL:1; /**< \brief [1:1] Trap Clear (w) */
+ Ifx_Strict_32Bit reserved_2:6; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit RM:2; /**< \brief [9:8] Captured Rounding Mode (rh) */
+ Ifx_Strict_32Bit reserved_10:8; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit FXE:1; /**< \brief [18:18] FX Trap Enable (rw) */
+ Ifx_Strict_32Bit FUE:1; /**< \brief [19:19] FU Trap Enable (rw) */
+ Ifx_Strict_32Bit FZE:1; /**< \brief [20:20] FZ Trap Enable (rw) */
+ Ifx_Strict_32Bit FVE:1; /**< \brief [21:21] FV Trap Enable (rw) */
+ Ifx_Strict_32Bit FIE:1; /**< \brief [22:22] FI Trap Enable (rw) */
+ Ifx_Strict_32Bit reserved_23:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit FX:1; /**< \brief [26:26] Captured FX (rh) */
+ Ifx_Strict_32Bit FU:1; /**< \brief [27:27] Captured FU (rh) */
+ Ifx_Strict_32Bit FZ:1; /**< \brief [28:28] Captured FZ (rh) */
+ Ifx_Strict_32Bit FV:1; /**< \brief [29:29] Captured FV (rh) */
+ Ifx_Strict_32Bit FI:1; /**< \brief [30:30] Captured FI (rh) */
+ Ifx_Strict_32Bit reserved_31:1; /**< \brief \internal Reserved */
+} Ifx_CPU_FPU_TRAP_CON_Bits;
+
+/** \brief CPU Trapping Instruction Opcode Register */
+typedef struct _Ifx_CPU_FPU_TRAP_OPC_Bits
+{
+ Ifx_Strict_32Bit OPC:8; /**< \brief [7:0] Captured Opcode (rh) */
+ Ifx_Strict_32Bit FMT:1; /**< \brief [8:8] Captured Instruction Format (rh) */
+ Ifx_Strict_32Bit reserved_9:7; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit DREG:4; /**< \brief [19:16] Captured Destination Register (rh) */
+ Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_CPU_FPU_TRAP_OPC_Bits;
+
+/** \brief CPU Trapping Instruction Program Counter Register */
+typedef struct _Ifx_CPU_FPU_TRAP_PC_Bits
+{
+ Ifx_Strict_32Bit PC:32; /**< \brief [31:0] Captured Program Counter (rh) */
+} Ifx_CPU_FPU_TRAP_PC_Bits;
+
+/** \brief CPU Trapping Instruction Operand Register */
+typedef struct _Ifx_CPU_FPU_TRAP_SRC1_Bits
+{
+ Ifx_Strict_32Bit SRC1:32; /**< \brief [31:0] Captured SRC1 Operand (rh) */
+} Ifx_CPU_FPU_TRAP_SRC1_Bits;
+
+/** \brief CPU Trapping Instruction Operand Register */
+typedef struct _Ifx_CPU_FPU_TRAP_SRC2_Bits
+{
+ Ifx_Strict_32Bit SRC2:32; /**< \brief [31:0] Captured SRC2 Operand (rh) */
+} Ifx_CPU_FPU_TRAP_SRC2_Bits;
+
+/** \brief Trapping Instruction Operand Register */
+typedef struct _Ifx_CPU_FPU_TRAP_SRC3_Bits
+{
+ Ifx_Strict_32Bit SRC3:32; /**< \brief [31:0] Captured SRC3 Operand (rh) */
+} Ifx_CPU_FPU_TRAP_SRC3_Bits;
+
+/** \brief Instruction Count */
+typedef struct _Ifx_CPU_ICNT_Bits
+{
+ Ifx_Strict_32Bit CountValue:31; /**< \brief [30:0] Count Value (rw) */
+ Ifx_Strict_32Bit SOvf:1; /**< \brief [31:31] Sticky Overflow Bit (rw) */
+} Ifx_CPU_ICNT_Bits;
+
+/** \brief Interrupt Control Register */
+typedef struct _Ifx_CPU_ICR_Bits
+{
+ Ifx_Strict_32Bit CCPN:10; /**< \brief [9:0] Current CPU Priority Number (rwh) */
+ Ifx_Strict_32Bit reserved_10:5; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit IE:1; /**< \brief [15:15] Global Interrupt Enable Bit (rwh) */
+ Ifx_Strict_32Bit PIPN:10; /**< \brief [25:16] Pending Interrupt Priority Number (rh) */
+ Ifx_Strict_32Bit reserved_26:6; /**< \brief \internal Reserved */
+} Ifx_CPU_ICR_Bits;
+
+/** \brief Interrupt Stack Pointer */
+typedef struct _Ifx_CPU_ISP_Bits
+{
+ Ifx_Strict_32Bit ISP:32; /**< \brief [31:0] Interrupt Stack Pointer (rw) */
+} Ifx_CPU_ISP_Bits;
+
+/** \brief Free CSA List Limit Pointer */
+typedef struct _Ifx_CPU_LCX_Bits
+{
+ Ifx_Strict_32Bit LCXO:16; /**< \brief [15:0] LCX Offset Field (rw) */
+ Ifx_Strict_32Bit LCXS:4; /**< \brief [19:16] LCX Segment Address (rw) */
+ Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_CPU_LCX_Bits;
+
+/** \brief Multi-Count Register 1 */
+typedef struct _Ifx_CPU_M1CNT_Bits
+{
+ Ifx_Strict_32Bit CountValue:31; /**< \brief [30:0] Count Value (rw) */
+ Ifx_Strict_32Bit SOvf:1; /**< \brief [31:31] Sticky Overflow Bit (rw) */
+} Ifx_CPU_M1CNT_Bits;
+
+/** \brief Multi-Count Register 2 */
+typedef struct _Ifx_CPU_M2CNT_Bits
+{
+ Ifx_Strict_32Bit CountValue:31; /**< \brief [30:0] Count Value (rw) */
+ Ifx_Strict_32Bit SOvf:1; /**< \brief [31:31] Sticky Overflow Bit (rw) */
+} Ifx_CPU_M2CNT_Bits;
+
+/** \brief Multi-Count Register 3 */
+typedef struct _Ifx_CPU_M3CNT_Bits
+{
+ Ifx_Strict_32Bit CountValue:31; /**< \brief [30:0] Count Value (rw) */
+ Ifx_Strict_32Bit SOvf:1; /**< \brief [31:31] Sticky Overflow Bit (rw) */
+} Ifx_CPU_M3CNT_Bits;
+
+/** \brief Program Counter */
+typedef struct _Ifx_CPU_PC_Bits
+{
+ Ifx_Strict_32Bit reserved_0:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit PC:31; /**< \brief [31:1] Program Counter (r) */
+} Ifx_CPU_PC_Bits;
+
+/** \brief Program Control 0 */
+typedef struct _Ifx_CPU_PCON0_Bits
+{
+ Ifx_Strict_32Bit reserved_0:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit PCBYP:1; /**< \brief [1:1] Program Cache Bypass (rw) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_CPU_PCON0_Bits;
+
+/** \brief Program Control 1 */
+typedef struct _Ifx_CPU_PCON1_Bits
+{
+ Ifx_Strict_32Bit PCINV:1; /**< \brief [0:0] Program Cache Invalidate (rw) */
+ Ifx_Strict_32Bit PBINV:1; /**< \brief [1:1] Program Buffer Invalidate (rw) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_CPU_PCON1_Bits;
+
+/** \brief Program Control 2 */
+typedef struct _Ifx_CPU_PCON2_Bits
+{
+ Ifx_Strict_32Bit PCACHE_SZE:16; /**< \brief [15:0] Program Cache Size (ICACHE) in KBytes (r) */
+ Ifx_Strict_32Bit PSCRATCH_SZE:16; /**< \brief [31:16] Program Scratch Size in KBytes (r) */
+} Ifx_CPU_PCON2_Bits;
+
+/** \brief Previous Context Information Register */
+typedef struct _Ifx_CPU_PCXI_Bits
+{
+ Ifx_Strict_32Bit PCXO:16; /**< \brief [15:0] Previous Context Pointer Offset Field (rw) */
+ Ifx_Strict_32Bit PCXS:4; /**< \brief [19:16] Previous Context Pointer Segment Address (rw) */
+ Ifx_Strict_32Bit UL:1; /**< \brief [20:20] Upper or Lower Context Tag (rw) */
+ Ifx_Strict_32Bit PIE:1; /**< \brief [21:21] Previous Interrupt Enable (rw) */
+ Ifx_Strict_32Bit PCPN:10; /**< \brief [31:22] Previous CPU Priority Number (rw) */
+} Ifx_CPU_PCXI_Bits;
+
+/** \brief Program Integrity Error Address Register */
+typedef struct _Ifx_CPU_PIEAR_Bits
+{
+ Ifx_Strict_32Bit TA:32; /**< \brief [31:0] Transaction Address (rh) */
+} Ifx_CPU_PIEAR_Bits;
+
+/** \brief Program Integrity Error Trap Register */
+typedef struct _Ifx_CPU_PIETR_Bits
+{
+ Ifx_Strict_32Bit IED:1; /**< \brief [0:0] Integrity Error Detected (rwh) */
+ Ifx_Strict_32Bit IE_T:1; /**< \brief [1:1] Integrity Error - Tag Memory (rh) */
+ Ifx_Strict_32Bit IE_C:1; /**< \brief [2:2] Integrity Error - Cache Memory (rh) */
+ Ifx_Strict_32Bit IE_S:1; /**< \brief [3:3] Integrity Error - Scratchpad Memory (rh) */
+ Ifx_Strict_32Bit IE_BI:1; /**< \brief [4:4] Integrity Error - Bus Interface (rh) */
+ Ifx_Strict_32Bit E_INFO:6; /**< \brief [10:5] Error Information (rh) */
+ Ifx_Strict_32Bit IE_DUAL:1; /**< \brief [11:11] Integrity Error - Dual Error Detected (r) */
+ Ifx_Strict_32Bit IE_SP:1; /**< \brief [12:12] Safety Protection Error Detected (rh) */
+ Ifx_Strict_32Bit IE_BS:1; /**< \brief [13:13] Bus Slave Access Indicator (rh) */
+ Ifx_Strict_32Bit reserved_14:18; /**< \brief \internal Reserved */
+} Ifx_CPU_PIETR_Bits;
+
+/** \brief Data Access CacheabilityRegister */
+typedef struct _Ifx_CPU_PMA0_Bits
+{
+ Ifx_Strict_32Bit reserved_0:13; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit DAC:3; /**< \brief [15:13] Data Access Cacheability Segments FH,EH,DH (r) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CPU_PMA0_Bits;
+
+/** \brief Code Access CacheabilityRegister */
+typedef struct _Ifx_CPU_PMA1_Bits
+{
+ Ifx_Strict_32Bit reserved_0:14; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit CAC:2; /**< \brief [15:14] Code Access Cacheability Segments FH,EH (r) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CPU_PMA1_Bits;
+
+/** \brief Peripheral Space Identifier register */
+typedef struct _Ifx_CPU_PMA2_Bits
+{
+ Ifx_Strict_32Bit PSI:16; /**< \brief [15:0] Peripheral Space Identifier Segments FH-0H (r) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_CPU_PMA2_Bits;
+
+/** \brief Program Synchronous Trap Register */
+typedef struct _Ifx_CPU_PSTR_Bits
+{
+ Ifx_Strict_32Bit FRE:1; /**< \brief [0:0] Fetch Range Error (rwh) */
+ Ifx_Strict_32Bit reserved_1:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit FBE:1; /**< \brief [2:2] Fetch Bus Error (rwh) */
+ Ifx_Strict_32Bit reserved_3:9; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit FPE:1; /**< \brief [12:12] Fetch Peripheral Error (rwh) */
+ Ifx_Strict_32Bit reserved_13:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit FME:1; /**< \brief [14:14] Fetch MSIST Error (rwh) */
+ Ifx_Strict_32Bit reserved_15:17; /**< \brief \internal Reserved */
+} Ifx_CPU_PSTR_Bits;
+
+/** \brief Program Status Word */
+typedef struct _Ifx_CPU_PSW_Bits
+{
+ Ifx_Strict_32Bit CDC:7; /**< \brief [6:0] Call Depth Counter (rwh) */
+ Ifx_Strict_32Bit CDE:1; /**< \brief [7:7] Call Depth Count Enable (rwh) */
+ Ifx_Strict_32Bit GW:1; /**< \brief [8:8] Global Address Register Write Permission (rwh) */
+ Ifx_Strict_32Bit IS:1; /**< \brief [9:9] Interrupt Stack Control (rwh) */
+ Ifx_Strict_32Bit IO:2; /**< \brief [11:10] Access Privilege Level Control (I/O Privilege) (rwh) */
+ Ifx_Strict_32Bit PRS:2; /**< \brief [13:12] Protection Register Set (rwh) */
+ Ifx_Strict_32Bit S:1; /**< \brief [14:14] Safe Task Identifier (rwh) */
+ Ifx_Strict_32Bit reserved_15:12; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SAV:1; /**< \brief [27:27] Sticky Advance Overflow Flag (rwh) */
+ Ifx_Strict_32Bit AV:1; /**< \brief [28:28] Advance Overflow Flag (rwh) */
+ Ifx_Strict_32Bit SV:1; /**< \brief [29:29] Sticky Overflow Flag (rwh) */
+ Ifx_Strict_32Bit V:1; /**< \brief [30:30] Overflow Flag (rwh) */
+ Ifx_Strict_32Bit C:1; /**< \brief [31:31] Carry Flag (rwh) */
+} Ifx_CPU_PSW_Bits;
+
+/** \brief SRI Error Generation Register */
+typedef struct _Ifx_CPU_SEGEN_Bits
+{
+ Ifx_Strict_32Bit ADFLIP:8; /**< \brief [7:0] Address ECC Bit Flip (rw) */
+ Ifx_Strict_32Bit ADTYPE:2; /**< \brief [9:8] Type of error (rw) */
+ Ifx_Strict_32Bit reserved_10:21; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit AE:1; /**< \brief [31:31] Activate Error Enable (rwh) */
+} Ifx_CPU_SEGEN_Bits;
+
+/** \brief SIST Mode Access Control Register */
+typedef struct _Ifx_CPU_SMACON_Bits
+{
+ Ifx_Strict_32Bit PC:1; /**< \brief [0:0] Instruction Cache Memory SIST Mode Access Control (rw) */
+ Ifx_Strict_32Bit reserved_1:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit PT:1; /**< \brief [2:2] Program Tag Memory SIST Mode Access Control (rw) */
+ Ifx_Strict_32Bit reserved_3:5; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit DC:1; /**< \brief [8:8] Data Cache Memory SIST Mode Access Control (rw) */
+ Ifx_Strict_32Bit reserved_9:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit DT:1; /**< \brief [10:10] Data Tag Memory SIST Mode Access Control (rw) */
+ Ifx_Strict_32Bit reserved_11:13; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit IODT:1; /**< \brief [24:24] In-Order Data Transactions (rw) */
+ Ifx_Strict_32Bit reserved_25:7; /**< \brief \internal Reserved */
+} Ifx_CPU_SMACON_Bits;
+
+/** \brief CPU Safety Protection Register Access Enable Register A */
+typedef struct _Ifx_CPU_SPROT_ACCENA_Bits
+{
+ unsigned int EN:32; /**< \brief [31:0] Access Enable for Master TAG ID n (n= 0-31) (rw) */
+} Ifx_CPU_SPROT_ACCENA_Bits;
+
+/** \brief CPU Safety Protection Region Access Enable Register B */
+typedef struct _Ifx_CPU_SPROT_ACCENB_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_CPU_SPROT_ACCENB_Bits;
+
+/** \brief CPU Safety Protection Region Access Enable Register A */
+typedef struct _Ifx_CPU_SPROT_RGN_ACCENA_Bits
+{
+ unsigned int EN:32; /**< \brief [31:0] Access Enable for Master TAG ID n (n = 0-31) (rw) */
+} Ifx_CPU_SPROT_RGN_ACCENA_Bits;
+
+/** \brief CPU Safety Protection Region Access Enable Register B */
+typedef struct _Ifx_CPU_SPROT_RGN_ACCENB_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_CPU_SPROT_RGN_ACCENB_Bits;
+
+/** \brief CPU Safety Protection Region Lower Address Register */
+typedef struct _Ifx_CPU_SPROT_RGN_LA_Bits
+{
+ unsigned int reserved_0:5; /**< \brief \internal Reserved */
+ unsigned int ADDR:27; /**< \brief [31:5] Region Lower Address (rw) */
+} Ifx_CPU_SPROT_RGN_LA_Bits;
+
+/** \brief CPU Safety protection Region Upper Address Register */
+typedef struct _Ifx_CPU_SPROT_RGN_UA_Bits
+{
+ unsigned int reserved_0:5; /**< \brief \internal Reserved */
+ unsigned int ADDR:27; /**< \brief [31:5] Region Upper Address (rw) */
+} Ifx_CPU_SPROT_RGN_UA_Bits;
+
+/** \brief Software Debug Event */
+typedef struct _Ifx_CPU_SWEVT_Bits
+{
+ Ifx_Strict_32Bit EVTA:3; /**< \brief [2:0] Event Associated (rw) */
+ Ifx_Strict_32Bit BBM:1; /**< \brief [3:3] Break Before Make (BBM) or Break After Make (BAM) Selection (rw) */
+ Ifx_Strict_32Bit BOD:1; /**< \brief [4:4] Breakout Disable (rw) */
+ Ifx_Strict_32Bit SUSP:1; /**< \brief [5:5] CDC Suspend-Out Signal State (rw) */
+ Ifx_Strict_32Bit CNT:2; /**< \brief [7:6] Counter (rw) */
+ Ifx_Strict_32Bit reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_CPU_SWEVT_Bits;
+
+/** \brief System Configuration Register */
+typedef struct _Ifx_CPU_SYSCON_Bits
+{
+ Ifx_Strict_32Bit FCDSF:1; /**< \brief [0:0] Free Context List Depleted Sticky Flag (rwh) */
+ Ifx_Strict_32Bit PROTEN:1; /**< \brief [1:1] Memory Protection Enable (rw) */
+ Ifx_Strict_32Bit TPROTEN:1; /**< \brief [2:2] Temporal Protection Enable (rw) */
+ Ifx_Strict_32Bit IS:1; /**< \brief [3:3] Initial State (rw) */
+ Ifx_Strict_32Bit IT:1; /**< \brief [4:4] Initial State (rw) */
+ Ifx_Strict_32Bit reserved_5:27; /**< \brief \internal Reserved */
+} Ifx_CPU_SYSCON_Bits;
+
+/** \brief CPU Task Address Space Identifier Register */
+typedef struct _Ifx_CPU_TASK_ASI_Bits
+{
+ Ifx_Strict_32Bit ASI:5; /**< \brief [4:0] Address Space Identifier (rw) */
+ Ifx_Strict_32Bit reserved_5:27; /**< \brief \internal Reserved */
+} Ifx_CPU_TASK_ASI_Bits;
+
+/** \brief CPU Temporal Protection System Control Register */
+typedef struct _Ifx_CPU_TPS_CON_Bits
+{
+ Ifx_Strict_32Bit TEXP0:1; /**< \brief [0:0] Timer0 Expired Flag (rh) */
+ Ifx_Strict_32Bit TEXP1:1; /**< \brief [1:1] Timer1 Expired Flag (rh) */
+ Ifx_Strict_32Bit TEXP2:1; /**< \brief [2:2] Timer1 Expired Flag (rh) */
+ Ifx_Strict_32Bit reserved_3:13; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit TTRAP:1; /**< \brief [16:16] Temporal Protection Trap (rh) */
+ Ifx_Strict_32Bit reserved_17:15; /**< \brief \internal Reserved */
+} Ifx_CPU_TPS_CON_Bits;
+
+/** \brief CPU Temporal Protection System Timer Register */
+typedef struct _Ifx_CPU_TPS_TIMER_Bits
+{
+ Ifx_Strict_32Bit Timer:32; /**< \brief [31:0] Temporal Protection Timer (rwh) */
+} Ifx_CPU_TPS_TIMER_Bits;
+
+/** \brief Trigger Address */
+typedef struct _Ifx_CPU_TR_ADR_Bits
+{
+ Ifx_Strict_32Bit ADDR:32; /**< \brief [31:0] Comparison Address (rw) */
+} Ifx_CPU_TR_ADR_Bits;
+
+/** \brief Trigger Event */
+typedef struct _Ifx_CPU_TR_EVT_Bits
+{
+ Ifx_Strict_32Bit EVTA:3; /**< \brief [2:0] Event Associated (rw) */
+ Ifx_Strict_32Bit BBM:1; /**< \brief [3:3] Break Before Make (BBM) or Break After Make (BAM) Selection (rw) */
+ Ifx_Strict_32Bit BOD:1; /**< \brief [4:4] Breakout Disable (rw) */
+ Ifx_Strict_32Bit SUSP:1; /**< \brief [5:5] CDC Suspend-Out Signal State (rw) */
+ Ifx_Strict_32Bit CNT:2; /**< \brief [7:6] Counter (rw) */
+ Ifx_Strict_32Bit reserved_8:4; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit TYP:1; /**< \brief [12:12] Input Selection (rw) */
+ Ifx_Strict_32Bit RNG:1; /**< \brief [13:13] Compare Type (rw) */
+ Ifx_Strict_32Bit reserved_14:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit ASI_EN:1; /**< \brief [15:15] Enable ASI Comparison (rw) */
+ Ifx_Strict_32Bit ASI:5; /**< \brief [20:16] Address Space Identifier (rw) */
+ Ifx_Strict_32Bit reserved_21:6; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit AST:1; /**< \brief [27:27] Address Store (rw) */
+ Ifx_Strict_32Bit ALD:1; /**< \brief [28:28] Address Load (rw) */
+ Ifx_Strict_32Bit reserved_29:3; /**< \brief \internal Reserved */
+} Ifx_CPU_TR_EVT_Bits;
+
+/** \brief CPU Trigger Address x */
+typedef struct _Ifx_CPU_TRIG_ACC_Bits
+{
+ Ifx_Strict_32Bit T0:1; /**< \brief [0:0] Trigger-0 (rh) */
+ Ifx_Strict_32Bit T1:1; /**< \brief [1:1] Trigger-1 (rh) */
+ Ifx_Strict_32Bit T2:1; /**< \brief [2:2] Trigger-2 (rh) */
+ Ifx_Strict_32Bit T3:1; /**< \brief [3:3] Trigger-3 (rh) */
+ Ifx_Strict_32Bit T4:1; /**< \brief [4:4] Trigger-4 (rh) */
+ Ifx_Strict_32Bit T5:1; /**< \brief [5:5] Trigger-5 (rh) */
+ Ifx_Strict_32Bit T6:1; /**< \brief [6:6] Trigger-6 (rh) */
+ Ifx_Strict_32Bit T7:1; /**< \brief [7:7] Trigger-7 (rh) */
+ Ifx_Strict_32Bit reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_CPU_TRIG_ACC_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Cpu_union
+ * \{ */
+
+/** \brief Address General Purpose Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_A_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_A;
+
+/** \brief Base Interrupt Vector Table Pointer */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_BIV_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_BIV;
+
+/** \brief Base Trap Vector Table Pointer */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_BTV_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_BTV;
+
+/** \brief CPU Clock Cycle Count */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_CCNT_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_CCNT;
+
+/** \brief Counter Control */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_CCTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_CCTRL;
+
+/** \brief Compatibility Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_COMPAT_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_COMPAT;
+
+/** \brief CPU Core Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_CORE_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_CORE_ID;
+
+/** \brief CPU Code Protection Range Lower Bound Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_CPR_L_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_CPR_L;
+
+/** \brief CPU Code Protection Range Upper Bound Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_CPR_U_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_CPR_U;
+
+/** \brief CPU Identification Register TC1.6P */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_CPU_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_CPU_ID;
+
+/** \brief CPU Code Protection Execute Enable Register Set */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_CPXE_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_CPXE;
+
+/** \brief Core Register Access Event */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_CREVT_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_CREVT;
+
+/** \brief CPU Customer ID register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_CUS_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_CUS_ID;
+
+/** \brief Data General Purpose Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_D_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_D;
+
+/** \brief Data Asynchronous Trap Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_DATR_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_DATR;
+
+/** \brief Debug Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_DBGSR_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_DBGSR;
+
+/** \brief Debug Trap Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_DBGTCR_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_DBGTCR;
+
+/** \brief Data Memory Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_DCON0_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_DCON0;
+
+/** \brief Data Control Register 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_DCON2_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_DCON2;
+
+/** \brief CPU Debug Context Save Area Pointer */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_DCX_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_DCX;
+
+/** \brief Data Error Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_DEADD_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_DEADD;
+
+/** \brief Data Integrity Error Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_DIEAR_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_DIEAR;
+
+/** \brief Data Integrity Error Trap Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_DIETR_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_DIETR;
+
+/** \brief CPU Debug Monitor Start Address */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_DMS_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_DMS;
+
+/** \brief CPU Data Protection Range, Lower Bound Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_DPR_L_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_DPR_L;
+
+/** \brief CPU Data Protection Range, Upper Bound Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_DPR_U_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_DPR_U;
+
+/** \brief CPU Data Protection Read Enable Register Set */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_DPRE_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_DPRE;
+
+/** \brief CPU Data Protection Write Enable Register Set */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_DPWE_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_DPWE;
+
+/** \brief Data Synchronous Trap Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_DSTR_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_DSTR;
+
+/** \brief External Event Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_EXEVT_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_EXEVT;
+
+/** \brief Free CSA List Head Pointer */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_FCX_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_FCX;
+
+/** \brief CPU Trap Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_FPU_TRAP_CON_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_FPU_TRAP_CON;
+
+/** \brief CPU Trapping Instruction Opcode Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_FPU_TRAP_OPC_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_FPU_TRAP_OPC;
+
+/** \brief CPU Trapping Instruction Program Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_FPU_TRAP_PC_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_FPU_TRAP_PC;
+
+/** \brief CPU Trapping Instruction Operand Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_FPU_TRAP_SRC1_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_FPU_TRAP_SRC1;
+
+/** \brief CPU Trapping Instruction Operand Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_FPU_TRAP_SRC2_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_FPU_TRAP_SRC2;
+
+/** \brief Trapping Instruction Operand Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_FPU_TRAP_SRC3_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_FPU_TRAP_SRC3;
+
+/** \brief Instruction Count */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_ICNT_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_ICNT;
+
+/** \brief Interrupt Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_ICR_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_ICR;
+
+/** \brief Interrupt Stack Pointer */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_ISP_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_ISP;
+
+/** \brief Free CSA List Limit Pointer */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_LCX_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_LCX;
+
+/** \brief Multi-Count Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_M1CNT_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_M1CNT;
+
+/** \brief Multi-Count Register 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_M2CNT_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_M2CNT;
+
+/** \brief Multi-Count Register 3 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_M3CNT_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_M3CNT;
+
+/** \brief Program Counter */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_PC_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_PC;
+
+/** \brief Program Control 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_PCON0_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_PCON0;
+
+/** \brief Program Control 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_PCON1_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_PCON1;
+
+/** \brief Program Control 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_PCON2_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_PCON2;
+
+/** \brief Previous Context Information Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_PCXI_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_PCXI;
+
+/** \brief Program Integrity Error Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_PIEAR_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_PIEAR;
+
+/** \brief Program Integrity Error Trap Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_PIETR_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_PIETR;
+
+/** \brief Data Access CacheabilityRegister */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_PMA0_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_PMA0;
+
+/** \brief Code Access CacheabilityRegister */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_PMA1_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_PMA1;
+
+/** \brief Peripheral Space Identifier register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_PMA2_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_PMA2;
+
+/** \brief Program Synchronous Trap Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_PSTR_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_PSTR;
+
+/** \brief Program Status Word */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_PSW_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_PSW;
+
+/** \brief SRI Error Generation Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_SEGEN_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_SEGEN;
+
+/** \brief SIST Mode Access Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_SMACON_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_SMACON;
+
+/** \brief CPU Safety Protection Register Access Enable Register A */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_SPROT_ACCENA_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_SPROT_ACCENA;
+
+/** \brief CPU Safety Protection Region Access Enable Register B */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_SPROT_ACCENB_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_SPROT_ACCENB;
+
+/** \brief CPU Safety Protection Region Access Enable Register A */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_SPROT_RGN_ACCENA_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_SPROT_RGN_ACCENA;
+
+/** \brief CPU Safety Protection Region Access Enable Register B */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_SPROT_RGN_ACCENB_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_SPROT_RGN_ACCENB;
+
+/** \brief CPU Safety Protection Region Lower Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_SPROT_RGN_LA_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_SPROT_RGN_LA;
+
+/** \brief CPU Safety protection Region Upper Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_SPROT_RGN_UA_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_SPROT_RGN_UA;
+
+/** \brief Software Debug Event */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_SWEVT_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_SWEVT;
+
+/** \brief System Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_SYSCON_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_SYSCON;
+
+/** \brief CPU Task Address Space Identifier Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_TASK_ASI_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_TASK_ASI;
+
+/** \brief CPU Temporal Protection System Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_TPS_CON_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_TPS_CON;
+
+/** \brief CPU Temporal Protection System Timer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_TPS_TIMER_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_TPS_TIMER;
+
+/** \brief Trigger Address */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_TR_ADR_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_TR_ADR;
+
+/** \brief Trigger Event */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_TR_EVT_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_TR_EVT;
+
+/** \brief CPU Trigger Address x */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_CPU_TRIG_ACC_Bits B; /**< \brief Bitfield access */
+} Ifx_CPU_TRIG_ACC;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Cpu_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L1
+ * \{ */
+
+/** \brief Protection range */
+typedef volatile struct _Ifx_CPU_CPR
+{
+ Ifx_CPU_CPR_L L; /**< \brief 0, CPU Code Protection Range Lower Bound Register */
+ Ifx_CPU_CPR_U U; /**< \brief 4, CPU Code Protection Range Upper Bound Register */
+} Ifx_CPU_CPR;
+
+/** \brief Protection range */
+typedef volatile struct _Ifx_CPU_DPR
+{
+ Ifx_CPU_DPR_L L; /**< \brief 0, CPU Data Protection Range, Lower Bound Register */
+ Ifx_CPU_DPR_U U; /**< \brief 4, CPU Data Protection Range, Upper Bound Register */
+} Ifx_CPU_DPR;
+
+/** \brief Safety protection region */
+typedef volatile struct _Ifx_CPU_SPROT_RGN
+{
+ Ifx_CPU_SPROT_RGN_LA LA; /**< \brief 0, CPU Safety Protection Region Lower Address Register */
+ Ifx_CPU_SPROT_RGN_UA UA; /**< \brief 4, CPU Safety protection Region Upper Address Register */
+ Ifx_CPU_SPROT_RGN_ACCENA ACCENA; /**< \brief 8, CPU Safety Protection Region Access Enable Register A */
+ Ifx_CPU_SPROT_RGN_ACCENB ACCENB; /**< \brief C, CPU Safety Protection Region Access Enable Register B */
+} Ifx_CPU_SPROT_RGN;
+
+/** \brief Temporal Protection System */
+typedef volatile struct _Ifx_CPU_TPS
+{
+ Ifx_CPU_TPS_CON CON; /**< \brief 0, CPU Temporal Protection System Control Register */
+ Ifx_CPU_TPS_TIMER TIMER[3]; /**< \brief 4, CPU Temporal Protection System Timer Register */
+} Ifx_CPU_TPS;
+
+/** \brief Trigger */
+typedef volatile struct _Ifx_CPU_TR
+{
+ Ifx_CPU_TR_EVT EVT; /**< \brief 0, Trigger Event */
+ Ifx_CPU_TR_ADR ADR; /**< \brief 4, Trigger Address */
+} Ifx_CPU_TR;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Cpu_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief CPU object */
+typedef volatile struct _Ifx_CPU
+{
+ unsigned char reserved_0[4144]; /**< \brief 0, \internal Reserved */
+ Ifx_CPU_SEGEN SEGEN; /**< \brief 1030, SRI Error Generation Register */
+ unsigned char reserved_1034[28624]; /**< \brief 1034, \internal Reserved */
+ Ifx_CPU_TASK_ASI TASK_ASI; /**< \brief 8004, CPU Task Address Space Identifier Register */
+ unsigned char reserved_8008[248]; /**< \brief 8008, \internal Reserved */
+ Ifx_CPU_PMA0 PMA0; /**< \brief 8100, Data Access CacheabilityRegister */
+ Ifx_CPU_PMA1 PMA1; /**< \brief 8104, Code Access CacheabilityRegister */
+ Ifx_CPU_PMA2 PMA2; /**< \brief 8108, Peripheral Space Identifier register */
+ unsigned char reserved_810C[3828]; /**< \brief 810C, \internal Reserved */
+ Ifx_CPU_DCON2 DCON2; /**< \brief 9000, Data Control Register 2 */
+ unsigned char reserved_9004[8]; /**< \brief 9004, \internal Reserved */
+ Ifx_CPU_SMACON SMACON; /**< \brief 900C, SIST Mode Access Control Register */
+ Ifx_CPU_DSTR DSTR; /**< \brief 9010, Data Synchronous Trap Register */
+ unsigned char reserved_9014[4]; /**< \brief 9014, \internal Reserved */
+ Ifx_CPU_DATR DATR; /**< \brief 9018, Data Asynchronous Trap Register */
+ Ifx_CPU_DEADD DEADD; /**< \brief 901C, Data Error Address Register */
+ Ifx_CPU_DIEAR DIEAR; /**< \brief 9020, Data Integrity Error Address Register */
+ Ifx_CPU_DIETR DIETR; /**< \brief 9024, Data Integrity Error Trap Register */
+ unsigned char reserved_9028[24]; /**< \brief 9028, \internal Reserved */
+ Ifx_CPU_DCON0 DCON0; /**< \brief 9040, Data Memory Control Register */
+ unsigned char reserved_9044[444]; /**< \brief 9044, \internal Reserved */
+ Ifx_CPU_PSTR PSTR; /**< \brief 9200, Program Synchronous Trap Register */
+ Ifx_CPU_PCON1 PCON1; /**< \brief 9204, Program Control 1 */
+ Ifx_CPU_PCON2 PCON2; /**< \brief 9208, Program Control 2 */
+ Ifx_CPU_PCON0 PCON0; /**< \brief 920C, Program Control 0 */
+ Ifx_CPU_PIEAR PIEAR; /**< \brief 9210, Program Integrity Error Address Register */
+ Ifx_CPU_PIETR PIETR; /**< \brief 9214, Program Integrity Error Trap Register */
+ unsigned char reserved_9218[488]; /**< \brief 9218, \internal Reserved */
+ Ifx_CPU_COMPAT COMPAT; /**< \brief 9400, Compatibility Control Register */
+ unsigned char reserved_9404[3068]; /**< \brief 9404, \internal Reserved */
+ Ifx_CPU_FPU_TRAP_CON FPU_TRAP_CON; /**< \brief A000, CPU Trap Control Register */
+ Ifx_CPU_FPU_TRAP_PC FPU_TRAP_PC; /**< \brief A004, CPU Trapping Instruction Program Counter Register */
+ Ifx_CPU_FPU_TRAP_OPC FPU_TRAP_OPC; /**< \brief A008, CPU Trapping Instruction Opcode Register */
+ unsigned char reserved_A00C[4]; /**< \brief A00C, \internal Reserved */
+ Ifx_CPU_FPU_TRAP_SRC1 FPU_TRAP_SRC1; /**< \brief A010, CPU Trapping Instruction Operand Register */
+ Ifx_CPU_FPU_TRAP_SRC2 FPU_TRAP_SRC2; /**< \brief A014, CPU Trapping Instruction Operand Register */
+ Ifx_CPU_FPU_TRAP_SRC3 FPU_TRAP_SRC3; /**< \brief A018, Trapping Instruction Operand Register */
+ unsigned char reserved_A01C[8164]; /**< \brief A01C, \internal Reserved */
+ Ifx_CPU_DPR DPR[16]; /**< \brief C000, Protection range */
+ unsigned char reserved_C080[3968]; /**< \brief C080, \internal Reserved */
+ Ifx_CPU_CPR CPR[8]; /**< \brief D000, Protection range */
+ unsigned char reserved_D040[4032]; /**< \brief D040, \internal Reserved */
+ Ifx_CPU_CPXE CPXE[4]; /**< \brief E000, CPU Code Protection Execute Enable Register Set */
+ Ifx_CPU_DPRE DPRE[4]; /**< \brief E010, CPU Data Protection Read Enable Register Set */
+ Ifx_CPU_DPWE DPWE[4]; /**< \brief E020, CPU Data Protection Write Enable Register Set */
+ unsigned char reserved_E030[976]; /**< \brief E030, \internal Reserved */
+ Ifx_CPU_TPS TPS; /**< \brief E400, Temporal Protection System */
+ unsigned char reserved_E410[3056]; /**< \brief E410, \internal Reserved */
+ Ifx_CPU_TR TR[8]; /**< \brief F000, Trigger */
+ unsigned char reserved_F040[3008]; /**< \brief F040, \internal Reserved */
+ Ifx_CPU_CCTRL CCTRL; /**< \brief FC00, Counter Control */
+ Ifx_CPU_CCNT CCNT; /**< \brief FC04, CPU Clock Cycle Count */
+ Ifx_CPU_ICNT ICNT; /**< \brief FC08, Instruction Count */
+ Ifx_CPU_M1CNT M1CNT; /**< \brief FC0C, Multi-Count Register 1 */
+ Ifx_CPU_M2CNT M2CNT; /**< \brief FC10, Multi-Count Register 2 */
+ Ifx_CPU_M3CNT M3CNT; /**< \brief FC14, Multi-Count Register 3 */
+ unsigned char reserved_FC18[232]; /**< \brief FC18, \internal Reserved */
+ Ifx_CPU_DBGSR DBGSR; /**< \brief FD00, Debug Status Register */
+ unsigned char reserved_FD04[4]; /**< \brief FD04, \internal Reserved */
+ Ifx_CPU_EXEVT EXEVT; /**< \brief FD08, External Event Register */
+ Ifx_CPU_CREVT CREVT; /**< \brief FD0C, Core Register Access Event */
+ Ifx_CPU_SWEVT SWEVT; /**< \brief FD10, Software Debug Event */
+ unsigned char reserved_FD14[28]; /**< \brief FD14, \internal Reserved */
+ Ifx_CPU_TRIG_ACC TRIG_ACC; /**< \brief FD30, CPU Trigger Address x */
+ unsigned char reserved_FD34[12]; /**< \brief FD34, \internal Reserved */
+ Ifx_CPU_DMS DMS; /**< \brief FD40, CPU Debug Monitor Start Address */
+ Ifx_CPU_DCX DCX; /**< \brief FD44, CPU Debug Context Save Area Pointer */
+ Ifx_CPU_DBGTCR DBGTCR; /**< \brief FD48, Debug Trap Control Register */
+ unsigned char reserved_FD4C[180]; /**< \brief FD4C, \internal Reserved */
+ Ifx_CPU_PCXI PCXI; /**< \brief FE00, Previous Context Information Register */
+ Ifx_CPU_PSW PSW; /**< \brief FE04, Program Status Word */
+ Ifx_CPU_PC PC; /**< \brief FE08, Program Counter */
+ unsigned char reserved_FE0C[8]; /**< \brief FE0C, \internal Reserved */
+ Ifx_CPU_SYSCON SYSCON; /**< \brief FE14, System Configuration Register */
+ Ifx_CPU_CPU_ID CPU_ID; /**< \brief FE18, CPU Identification Register TC1.6P */
+ Ifx_CPU_CORE_ID CORE_ID; /**< \brief FE1C, CPU Core Identification Register */
+ Ifx_CPU_BIV BIV; /**< \brief FE20, Base Interrupt Vector Table Pointer */
+ Ifx_CPU_BTV BTV; /**< \brief FE24, Base Trap Vector Table Pointer */
+ Ifx_CPU_ISP ISP; /**< \brief FE28, Interrupt Stack Pointer */
+ Ifx_CPU_ICR ICR; /**< \brief FE2C, Interrupt Control Register */
+ unsigned char reserved_FE30[8]; /**< \brief FE30, \internal Reserved */
+ Ifx_CPU_FCX FCX; /**< \brief FE38, Free CSA List Head Pointer */
+ Ifx_CPU_LCX LCX; /**< \brief FE3C, Free CSA List Limit Pointer */
+ unsigned char reserved_FE40[16]; /**< \brief FE40, \internal Reserved */
+ Ifx_CPU_CUS_ID CUS_ID; /**< \brief FE50, CPU Customer ID register */
+ unsigned char reserved_FE54[172]; /**< \brief FE54, \internal Reserved */
+ Ifx_CPU_D D[16]; /**< \brief FF00, Data General Purpose Register */
+ unsigned char reserved_FF40[64]; /**< \brief FF40, \internal Reserved */
+ Ifx_CPU_A A[16]; /**< \brief FF80, Address General Purpose Register */
+ unsigned char reserved_FFC0[64]; /**< \brief FFC0, \internal Reserved */
+} Ifx_CPU;
+
+/** \brief CPU SPROT object */
+typedef volatile struct _Ifx_CPU_SPROT
+{
+ unsigned char reserved_0[57344]; /**< \brief 0, \internal Reserved */
+ Ifx_CPU_SPROT_RGN RGN[8]; /**< \brief E000, Safety protection region */
+ unsigned char reserved_E080[128]; /**< \brief E080, \internal Reserved */
+ Ifx_CPU_SPROT_ACCENA ACCENA; /**< \brief E100, CPU Safety Protection Register Access Enable Register A */
+ Ifx_CPU_SPROT_ACCENB ACCENB; /**< \brief E104, CPU Safety Protection Region Access Enable Register B */
+ unsigned char reserved_E108[7928]; /**< \brief E108, \internal Reserved */
+} Ifx_CPU_SPROT;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXCPU_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxDma_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxDma_bf.h
new file mode 100644
index 0000000..a6bda16
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxDma_bf.h
@@ -0,0 +1,2700 @@
+/**
+ * \file IfxDma_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Dma_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Dma
+ *
+ */
+#ifndef IFXDMA_BF_H
+#define IFXDMA_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Dma_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN0 */
+#define IFX_DMA_ACCEN00_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN0 */
+#define IFX_DMA_ACCEN00_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN0 */
+#define IFX_DMA_ACCEN00_EN0_OFF (0u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN10 */
+#define IFX_DMA_ACCEN00_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN10 */
+#define IFX_DMA_ACCEN00_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN10 */
+#define IFX_DMA_ACCEN00_EN10_OFF (10u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN11 */
+#define IFX_DMA_ACCEN00_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN11 */
+#define IFX_DMA_ACCEN00_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN11 */
+#define IFX_DMA_ACCEN00_EN11_OFF (11u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN12 */
+#define IFX_DMA_ACCEN00_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN12 */
+#define IFX_DMA_ACCEN00_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN12 */
+#define IFX_DMA_ACCEN00_EN12_OFF (12u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN13 */
+#define IFX_DMA_ACCEN00_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN13 */
+#define IFX_DMA_ACCEN00_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN13 */
+#define IFX_DMA_ACCEN00_EN13_OFF (13u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN14 */
+#define IFX_DMA_ACCEN00_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN14 */
+#define IFX_DMA_ACCEN00_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN14 */
+#define IFX_DMA_ACCEN00_EN14_OFF (14u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN15 */
+#define IFX_DMA_ACCEN00_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN15 */
+#define IFX_DMA_ACCEN00_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN15 */
+#define IFX_DMA_ACCEN00_EN15_OFF (15u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN16 */
+#define IFX_DMA_ACCEN00_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN16 */
+#define IFX_DMA_ACCEN00_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN16 */
+#define IFX_DMA_ACCEN00_EN16_OFF (16u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN17 */
+#define IFX_DMA_ACCEN00_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN17 */
+#define IFX_DMA_ACCEN00_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN17 */
+#define IFX_DMA_ACCEN00_EN17_OFF (17u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN18 */
+#define IFX_DMA_ACCEN00_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN18 */
+#define IFX_DMA_ACCEN00_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN18 */
+#define IFX_DMA_ACCEN00_EN18_OFF (18u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN19 */
+#define IFX_DMA_ACCEN00_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN19 */
+#define IFX_DMA_ACCEN00_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN19 */
+#define IFX_DMA_ACCEN00_EN19_OFF (19u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN1 */
+#define IFX_DMA_ACCEN00_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN1 */
+#define IFX_DMA_ACCEN00_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN1 */
+#define IFX_DMA_ACCEN00_EN1_OFF (1u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN20 */
+#define IFX_DMA_ACCEN00_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN20 */
+#define IFX_DMA_ACCEN00_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN20 */
+#define IFX_DMA_ACCEN00_EN20_OFF (20u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN21 */
+#define IFX_DMA_ACCEN00_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN21 */
+#define IFX_DMA_ACCEN00_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN21 */
+#define IFX_DMA_ACCEN00_EN21_OFF (21u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN22 */
+#define IFX_DMA_ACCEN00_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN22 */
+#define IFX_DMA_ACCEN00_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN22 */
+#define IFX_DMA_ACCEN00_EN22_OFF (22u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN23 */
+#define IFX_DMA_ACCEN00_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN23 */
+#define IFX_DMA_ACCEN00_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN23 */
+#define IFX_DMA_ACCEN00_EN23_OFF (23u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN24 */
+#define IFX_DMA_ACCEN00_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN24 */
+#define IFX_DMA_ACCEN00_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN24 */
+#define IFX_DMA_ACCEN00_EN24_OFF (24u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN25 */
+#define IFX_DMA_ACCEN00_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN25 */
+#define IFX_DMA_ACCEN00_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN25 */
+#define IFX_DMA_ACCEN00_EN25_OFF (25u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN26 */
+#define IFX_DMA_ACCEN00_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN26 */
+#define IFX_DMA_ACCEN00_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN26 */
+#define IFX_DMA_ACCEN00_EN26_OFF (26u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN27 */
+#define IFX_DMA_ACCEN00_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN27 */
+#define IFX_DMA_ACCEN00_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN27 */
+#define IFX_DMA_ACCEN00_EN27_OFF (27u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN28 */
+#define IFX_DMA_ACCEN00_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN28 */
+#define IFX_DMA_ACCEN00_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN28 */
+#define IFX_DMA_ACCEN00_EN28_OFF (28u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN29 */
+#define IFX_DMA_ACCEN00_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN29 */
+#define IFX_DMA_ACCEN00_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN29 */
+#define IFX_DMA_ACCEN00_EN29_OFF (29u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN2 */
+#define IFX_DMA_ACCEN00_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN2 */
+#define IFX_DMA_ACCEN00_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN2 */
+#define IFX_DMA_ACCEN00_EN2_OFF (2u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN30 */
+#define IFX_DMA_ACCEN00_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN30 */
+#define IFX_DMA_ACCEN00_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN30 */
+#define IFX_DMA_ACCEN00_EN30_OFF (30u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN31 */
+#define IFX_DMA_ACCEN00_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN31 */
+#define IFX_DMA_ACCEN00_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN31 */
+#define IFX_DMA_ACCEN00_EN31_OFF (31u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN3 */
+#define IFX_DMA_ACCEN00_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN3 */
+#define IFX_DMA_ACCEN00_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN3 */
+#define IFX_DMA_ACCEN00_EN3_OFF (3u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN4 */
+#define IFX_DMA_ACCEN00_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN4 */
+#define IFX_DMA_ACCEN00_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN4 */
+#define IFX_DMA_ACCEN00_EN4_OFF (4u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN5 */
+#define IFX_DMA_ACCEN00_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN5 */
+#define IFX_DMA_ACCEN00_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN5 */
+#define IFX_DMA_ACCEN00_EN5_OFF (5u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN6 */
+#define IFX_DMA_ACCEN00_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN6 */
+#define IFX_DMA_ACCEN00_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN6 */
+#define IFX_DMA_ACCEN00_EN6_OFF (6u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN7 */
+#define IFX_DMA_ACCEN00_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN7 */
+#define IFX_DMA_ACCEN00_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN7 */
+#define IFX_DMA_ACCEN00_EN7_OFF (7u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN8 */
+#define IFX_DMA_ACCEN00_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN8 */
+#define IFX_DMA_ACCEN00_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN8 */
+#define IFX_DMA_ACCEN00_EN8_OFF (8u)
+
+/** \brief Length for Ifx_DMA_ACCEN00_Bits.EN9 */
+#define IFX_DMA_ACCEN00_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN00_Bits.EN9 */
+#define IFX_DMA_ACCEN00_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN00_Bits.EN9 */
+#define IFX_DMA_ACCEN00_EN9_OFF (9u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN0 */
+#define IFX_DMA_ACCEN10_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN0 */
+#define IFX_DMA_ACCEN10_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN0 */
+#define IFX_DMA_ACCEN10_EN0_OFF (0u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN10 */
+#define IFX_DMA_ACCEN10_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN10 */
+#define IFX_DMA_ACCEN10_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN10 */
+#define IFX_DMA_ACCEN10_EN10_OFF (10u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN11 */
+#define IFX_DMA_ACCEN10_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN11 */
+#define IFX_DMA_ACCEN10_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN11 */
+#define IFX_DMA_ACCEN10_EN11_OFF (11u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN12 */
+#define IFX_DMA_ACCEN10_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN12 */
+#define IFX_DMA_ACCEN10_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN12 */
+#define IFX_DMA_ACCEN10_EN12_OFF (12u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN13 */
+#define IFX_DMA_ACCEN10_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN13 */
+#define IFX_DMA_ACCEN10_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN13 */
+#define IFX_DMA_ACCEN10_EN13_OFF (13u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN14 */
+#define IFX_DMA_ACCEN10_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN14 */
+#define IFX_DMA_ACCEN10_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN14 */
+#define IFX_DMA_ACCEN10_EN14_OFF (14u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN15 */
+#define IFX_DMA_ACCEN10_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN15 */
+#define IFX_DMA_ACCEN10_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN15 */
+#define IFX_DMA_ACCEN10_EN15_OFF (15u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN16 */
+#define IFX_DMA_ACCEN10_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN16 */
+#define IFX_DMA_ACCEN10_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN16 */
+#define IFX_DMA_ACCEN10_EN16_OFF (16u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN17 */
+#define IFX_DMA_ACCEN10_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN17 */
+#define IFX_DMA_ACCEN10_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN17 */
+#define IFX_DMA_ACCEN10_EN17_OFF (17u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN18 */
+#define IFX_DMA_ACCEN10_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN18 */
+#define IFX_DMA_ACCEN10_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN18 */
+#define IFX_DMA_ACCEN10_EN18_OFF (18u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN19 */
+#define IFX_DMA_ACCEN10_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN19 */
+#define IFX_DMA_ACCEN10_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN19 */
+#define IFX_DMA_ACCEN10_EN19_OFF (19u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN1 */
+#define IFX_DMA_ACCEN10_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN1 */
+#define IFX_DMA_ACCEN10_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN1 */
+#define IFX_DMA_ACCEN10_EN1_OFF (1u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN20 */
+#define IFX_DMA_ACCEN10_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN20 */
+#define IFX_DMA_ACCEN10_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN20 */
+#define IFX_DMA_ACCEN10_EN20_OFF (20u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN21 */
+#define IFX_DMA_ACCEN10_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN21 */
+#define IFX_DMA_ACCEN10_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN21 */
+#define IFX_DMA_ACCEN10_EN21_OFF (21u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN22 */
+#define IFX_DMA_ACCEN10_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN22 */
+#define IFX_DMA_ACCEN10_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN22 */
+#define IFX_DMA_ACCEN10_EN22_OFF (22u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN23 */
+#define IFX_DMA_ACCEN10_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN23 */
+#define IFX_DMA_ACCEN10_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN23 */
+#define IFX_DMA_ACCEN10_EN23_OFF (23u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN24 */
+#define IFX_DMA_ACCEN10_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN24 */
+#define IFX_DMA_ACCEN10_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN24 */
+#define IFX_DMA_ACCEN10_EN24_OFF (24u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN25 */
+#define IFX_DMA_ACCEN10_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN25 */
+#define IFX_DMA_ACCEN10_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN25 */
+#define IFX_DMA_ACCEN10_EN25_OFF (25u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN26 */
+#define IFX_DMA_ACCEN10_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN26 */
+#define IFX_DMA_ACCEN10_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN26 */
+#define IFX_DMA_ACCEN10_EN26_OFF (26u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN27 */
+#define IFX_DMA_ACCEN10_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN27 */
+#define IFX_DMA_ACCEN10_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN27 */
+#define IFX_DMA_ACCEN10_EN27_OFF (27u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN28 */
+#define IFX_DMA_ACCEN10_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN28 */
+#define IFX_DMA_ACCEN10_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN28 */
+#define IFX_DMA_ACCEN10_EN28_OFF (28u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN29 */
+#define IFX_DMA_ACCEN10_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN29 */
+#define IFX_DMA_ACCEN10_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN29 */
+#define IFX_DMA_ACCEN10_EN29_OFF (29u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN2 */
+#define IFX_DMA_ACCEN10_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN2 */
+#define IFX_DMA_ACCEN10_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN2 */
+#define IFX_DMA_ACCEN10_EN2_OFF (2u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN30 */
+#define IFX_DMA_ACCEN10_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN30 */
+#define IFX_DMA_ACCEN10_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN30 */
+#define IFX_DMA_ACCEN10_EN30_OFF (30u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN31 */
+#define IFX_DMA_ACCEN10_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN31 */
+#define IFX_DMA_ACCEN10_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN31 */
+#define IFX_DMA_ACCEN10_EN31_OFF (31u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN3 */
+#define IFX_DMA_ACCEN10_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN3 */
+#define IFX_DMA_ACCEN10_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN3 */
+#define IFX_DMA_ACCEN10_EN3_OFF (3u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN4 */
+#define IFX_DMA_ACCEN10_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN4 */
+#define IFX_DMA_ACCEN10_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN4 */
+#define IFX_DMA_ACCEN10_EN4_OFF (4u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN5 */
+#define IFX_DMA_ACCEN10_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN5 */
+#define IFX_DMA_ACCEN10_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN5 */
+#define IFX_DMA_ACCEN10_EN5_OFF (5u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN6 */
+#define IFX_DMA_ACCEN10_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN6 */
+#define IFX_DMA_ACCEN10_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN6 */
+#define IFX_DMA_ACCEN10_EN6_OFF (6u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN7 */
+#define IFX_DMA_ACCEN10_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN7 */
+#define IFX_DMA_ACCEN10_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN7 */
+#define IFX_DMA_ACCEN10_EN7_OFF (7u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN8 */
+#define IFX_DMA_ACCEN10_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN8 */
+#define IFX_DMA_ACCEN10_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN8 */
+#define IFX_DMA_ACCEN10_EN8_OFF (8u)
+
+/** \brief Length for Ifx_DMA_ACCEN10_Bits.EN9 */
+#define IFX_DMA_ACCEN10_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN10_Bits.EN9 */
+#define IFX_DMA_ACCEN10_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN10_Bits.EN9 */
+#define IFX_DMA_ACCEN10_EN9_OFF (9u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN0 */
+#define IFX_DMA_ACCEN20_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN0 */
+#define IFX_DMA_ACCEN20_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN0 */
+#define IFX_DMA_ACCEN20_EN0_OFF (0u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN10 */
+#define IFX_DMA_ACCEN20_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN10 */
+#define IFX_DMA_ACCEN20_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN10 */
+#define IFX_DMA_ACCEN20_EN10_OFF (10u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN11 */
+#define IFX_DMA_ACCEN20_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN11 */
+#define IFX_DMA_ACCEN20_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN11 */
+#define IFX_DMA_ACCEN20_EN11_OFF (11u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN12 */
+#define IFX_DMA_ACCEN20_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN12 */
+#define IFX_DMA_ACCEN20_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN12 */
+#define IFX_DMA_ACCEN20_EN12_OFF (12u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN13 */
+#define IFX_DMA_ACCEN20_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN13 */
+#define IFX_DMA_ACCEN20_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN13 */
+#define IFX_DMA_ACCEN20_EN13_OFF (13u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN14 */
+#define IFX_DMA_ACCEN20_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN14 */
+#define IFX_DMA_ACCEN20_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN14 */
+#define IFX_DMA_ACCEN20_EN14_OFF (14u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN15 */
+#define IFX_DMA_ACCEN20_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN15 */
+#define IFX_DMA_ACCEN20_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN15 */
+#define IFX_DMA_ACCEN20_EN15_OFF (15u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN16 */
+#define IFX_DMA_ACCEN20_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN16 */
+#define IFX_DMA_ACCEN20_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN16 */
+#define IFX_DMA_ACCEN20_EN16_OFF (16u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN17 */
+#define IFX_DMA_ACCEN20_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN17 */
+#define IFX_DMA_ACCEN20_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN17 */
+#define IFX_DMA_ACCEN20_EN17_OFF (17u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN18 */
+#define IFX_DMA_ACCEN20_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN18 */
+#define IFX_DMA_ACCEN20_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN18 */
+#define IFX_DMA_ACCEN20_EN18_OFF (18u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN19 */
+#define IFX_DMA_ACCEN20_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN19 */
+#define IFX_DMA_ACCEN20_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN19 */
+#define IFX_DMA_ACCEN20_EN19_OFF (19u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN1 */
+#define IFX_DMA_ACCEN20_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN1 */
+#define IFX_DMA_ACCEN20_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN1 */
+#define IFX_DMA_ACCEN20_EN1_OFF (1u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN20 */
+#define IFX_DMA_ACCEN20_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN20 */
+#define IFX_DMA_ACCEN20_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN20 */
+#define IFX_DMA_ACCEN20_EN20_OFF (20u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN21 */
+#define IFX_DMA_ACCEN20_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN21 */
+#define IFX_DMA_ACCEN20_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN21 */
+#define IFX_DMA_ACCEN20_EN21_OFF (21u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN22 */
+#define IFX_DMA_ACCEN20_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN22 */
+#define IFX_DMA_ACCEN20_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN22 */
+#define IFX_DMA_ACCEN20_EN22_OFF (22u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN23 */
+#define IFX_DMA_ACCEN20_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN23 */
+#define IFX_DMA_ACCEN20_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN23 */
+#define IFX_DMA_ACCEN20_EN23_OFF (23u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN24 */
+#define IFX_DMA_ACCEN20_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN24 */
+#define IFX_DMA_ACCEN20_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN24 */
+#define IFX_DMA_ACCEN20_EN24_OFF (24u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN25 */
+#define IFX_DMA_ACCEN20_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN25 */
+#define IFX_DMA_ACCEN20_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN25 */
+#define IFX_DMA_ACCEN20_EN25_OFF (25u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN26 */
+#define IFX_DMA_ACCEN20_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN26 */
+#define IFX_DMA_ACCEN20_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN26 */
+#define IFX_DMA_ACCEN20_EN26_OFF (26u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN27 */
+#define IFX_DMA_ACCEN20_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN27 */
+#define IFX_DMA_ACCEN20_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN27 */
+#define IFX_DMA_ACCEN20_EN27_OFF (27u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN28 */
+#define IFX_DMA_ACCEN20_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN28 */
+#define IFX_DMA_ACCEN20_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN28 */
+#define IFX_DMA_ACCEN20_EN28_OFF (28u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN29 */
+#define IFX_DMA_ACCEN20_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN29 */
+#define IFX_DMA_ACCEN20_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN29 */
+#define IFX_DMA_ACCEN20_EN29_OFF (29u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN2 */
+#define IFX_DMA_ACCEN20_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN2 */
+#define IFX_DMA_ACCEN20_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN2 */
+#define IFX_DMA_ACCEN20_EN2_OFF (2u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN30 */
+#define IFX_DMA_ACCEN20_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN30 */
+#define IFX_DMA_ACCEN20_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN30 */
+#define IFX_DMA_ACCEN20_EN30_OFF (30u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN31 */
+#define IFX_DMA_ACCEN20_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN31 */
+#define IFX_DMA_ACCEN20_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN31 */
+#define IFX_DMA_ACCEN20_EN31_OFF (31u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN3 */
+#define IFX_DMA_ACCEN20_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN3 */
+#define IFX_DMA_ACCEN20_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN3 */
+#define IFX_DMA_ACCEN20_EN3_OFF (3u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN4 */
+#define IFX_DMA_ACCEN20_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN4 */
+#define IFX_DMA_ACCEN20_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN4 */
+#define IFX_DMA_ACCEN20_EN4_OFF (4u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN5 */
+#define IFX_DMA_ACCEN20_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN5 */
+#define IFX_DMA_ACCEN20_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN5 */
+#define IFX_DMA_ACCEN20_EN5_OFF (5u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN6 */
+#define IFX_DMA_ACCEN20_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN6 */
+#define IFX_DMA_ACCEN20_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN6 */
+#define IFX_DMA_ACCEN20_EN6_OFF (6u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN7 */
+#define IFX_DMA_ACCEN20_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN7 */
+#define IFX_DMA_ACCEN20_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN7 */
+#define IFX_DMA_ACCEN20_EN7_OFF (7u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN8 */
+#define IFX_DMA_ACCEN20_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN8 */
+#define IFX_DMA_ACCEN20_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN8 */
+#define IFX_DMA_ACCEN20_EN8_OFF (8u)
+
+/** \brief Length for Ifx_DMA_ACCEN20_Bits.EN9 */
+#define IFX_DMA_ACCEN20_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN20_Bits.EN9 */
+#define IFX_DMA_ACCEN20_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN20_Bits.EN9 */
+#define IFX_DMA_ACCEN20_EN9_OFF (9u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN0 */
+#define IFX_DMA_ACCEN30_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN0 */
+#define IFX_DMA_ACCEN30_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN0 */
+#define IFX_DMA_ACCEN30_EN0_OFF (0u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN10 */
+#define IFX_DMA_ACCEN30_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN10 */
+#define IFX_DMA_ACCEN30_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN10 */
+#define IFX_DMA_ACCEN30_EN10_OFF (10u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN11 */
+#define IFX_DMA_ACCEN30_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN11 */
+#define IFX_DMA_ACCEN30_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN11 */
+#define IFX_DMA_ACCEN30_EN11_OFF (11u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN12 */
+#define IFX_DMA_ACCEN30_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN12 */
+#define IFX_DMA_ACCEN30_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN12 */
+#define IFX_DMA_ACCEN30_EN12_OFF (12u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN13 */
+#define IFX_DMA_ACCEN30_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN13 */
+#define IFX_DMA_ACCEN30_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN13 */
+#define IFX_DMA_ACCEN30_EN13_OFF (13u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN14 */
+#define IFX_DMA_ACCEN30_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN14 */
+#define IFX_DMA_ACCEN30_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN14 */
+#define IFX_DMA_ACCEN30_EN14_OFF (14u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN15 */
+#define IFX_DMA_ACCEN30_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN15 */
+#define IFX_DMA_ACCEN30_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN15 */
+#define IFX_DMA_ACCEN30_EN15_OFF (15u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN16 */
+#define IFX_DMA_ACCEN30_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN16 */
+#define IFX_DMA_ACCEN30_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN16 */
+#define IFX_DMA_ACCEN30_EN16_OFF (16u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN17 */
+#define IFX_DMA_ACCEN30_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN17 */
+#define IFX_DMA_ACCEN30_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN17 */
+#define IFX_DMA_ACCEN30_EN17_OFF (17u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN18 */
+#define IFX_DMA_ACCEN30_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN18 */
+#define IFX_DMA_ACCEN30_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN18 */
+#define IFX_DMA_ACCEN30_EN18_OFF (18u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN19 */
+#define IFX_DMA_ACCEN30_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN19 */
+#define IFX_DMA_ACCEN30_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN19 */
+#define IFX_DMA_ACCEN30_EN19_OFF (19u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN1 */
+#define IFX_DMA_ACCEN30_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN1 */
+#define IFX_DMA_ACCEN30_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN1 */
+#define IFX_DMA_ACCEN30_EN1_OFF (1u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN20 */
+#define IFX_DMA_ACCEN30_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN20 */
+#define IFX_DMA_ACCEN30_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN20 */
+#define IFX_DMA_ACCEN30_EN20_OFF (20u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN21 */
+#define IFX_DMA_ACCEN30_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN21 */
+#define IFX_DMA_ACCEN30_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN21 */
+#define IFX_DMA_ACCEN30_EN21_OFF (21u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN22 */
+#define IFX_DMA_ACCEN30_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN22 */
+#define IFX_DMA_ACCEN30_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN22 */
+#define IFX_DMA_ACCEN30_EN22_OFF (22u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN23 */
+#define IFX_DMA_ACCEN30_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN23 */
+#define IFX_DMA_ACCEN30_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN23 */
+#define IFX_DMA_ACCEN30_EN23_OFF (23u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN24 */
+#define IFX_DMA_ACCEN30_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN24 */
+#define IFX_DMA_ACCEN30_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN24 */
+#define IFX_DMA_ACCEN30_EN24_OFF (24u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN25 */
+#define IFX_DMA_ACCEN30_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN25 */
+#define IFX_DMA_ACCEN30_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN25 */
+#define IFX_DMA_ACCEN30_EN25_OFF (25u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN26 */
+#define IFX_DMA_ACCEN30_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN26 */
+#define IFX_DMA_ACCEN30_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN26 */
+#define IFX_DMA_ACCEN30_EN26_OFF (26u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN27 */
+#define IFX_DMA_ACCEN30_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN27 */
+#define IFX_DMA_ACCEN30_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN27 */
+#define IFX_DMA_ACCEN30_EN27_OFF (27u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN28 */
+#define IFX_DMA_ACCEN30_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN28 */
+#define IFX_DMA_ACCEN30_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN28 */
+#define IFX_DMA_ACCEN30_EN28_OFF (28u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN29 */
+#define IFX_DMA_ACCEN30_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN29 */
+#define IFX_DMA_ACCEN30_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN29 */
+#define IFX_DMA_ACCEN30_EN29_OFF (29u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN2 */
+#define IFX_DMA_ACCEN30_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN2 */
+#define IFX_DMA_ACCEN30_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN2 */
+#define IFX_DMA_ACCEN30_EN2_OFF (2u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN30 */
+#define IFX_DMA_ACCEN30_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN30 */
+#define IFX_DMA_ACCEN30_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN30 */
+#define IFX_DMA_ACCEN30_EN30_OFF (30u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN31 */
+#define IFX_DMA_ACCEN30_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN31 */
+#define IFX_DMA_ACCEN30_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN31 */
+#define IFX_DMA_ACCEN30_EN31_OFF (31u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN3 */
+#define IFX_DMA_ACCEN30_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN3 */
+#define IFX_DMA_ACCEN30_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN3 */
+#define IFX_DMA_ACCEN30_EN3_OFF (3u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN4 */
+#define IFX_DMA_ACCEN30_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN4 */
+#define IFX_DMA_ACCEN30_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN4 */
+#define IFX_DMA_ACCEN30_EN4_OFF (4u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN5 */
+#define IFX_DMA_ACCEN30_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN5 */
+#define IFX_DMA_ACCEN30_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN5 */
+#define IFX_DMA_ACCEN30_EN5_OFF (5u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN6 */
+#define IFX_DMA_ACCEN30_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN6 */
+#define IFX_DMA_ACCEN30_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN6 */
+#define IFX_DMA_ACCEN30_EN6_OFF (6u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN7 */
+#define IFX_DMA_ACCEN30_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN7 */
+#define IFX_DMA_ACCEN30_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN7 */
+#define IFX_DMA_ACCEN30_EN7_OFF (7u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN8 */
+#define IFX_DMA_ACCEN30_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN8 */
+#define IFX_DMA_ACCEN30_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN8 */
+#define IFX_DMA_ACCEN30_EN8_OFF (8u)
+
+/** \brief Length for Ifx_DMA_ACCEN30_Bits.EN9 */
+#define IFX_DMA_ACCEN30_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ACCEN30_Bits.EN9 */
+#define IFX_DMA_ACCEN30_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ACCEN30_Bits.EN9 */
+#define IFX_DMA_ACCEN30_EN9_OFF (9u)
+
+/** \brief Length for Ifx_DMA_BLK_CLRE_Bits.CDER */
+#define IFX_DMA_BLK_CLRE_CDER_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_CLRE_Bits.CDER */
+#define IFX_DMA_BLK_CLRE_CDER_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_CLRE_Bits.CDER */
+#define IFX_DMA_BLK_CLRE_CDER_OFF (17u)
+
+/** \brief Length for Ifx_DMA_BLK_CLRE_Bits.CDLLER */
+#define IFX_DMA_BLK_CLRE_CDLLER_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_CLRE_Bits.CDLLER */
+#define IFX_DMA_BLK_CLRE_CDLLER_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_CLRE_Bits.CDLLER */
+#define IFX_DMA_BLK_CLRE_CDLLER_OFF (26u)
+
+/** \brief Length for Ifx_DMA_BLK_CLRE_Bits.CRAMER */
+#define IFX_DMA_BLK_CLRE_CRAMER_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_CLRE_Bits.CRAMER */
+#define IFX_DMA_BLK_CLRE_CRAMER_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_CLRE_Bits.CRAMER */
+#define IFX_DMA_BLK_CLRE_CRAMER_OFF (24u)
+
+/** \brief Length for Ifx_DMA_BLK_CLRE_Bits.CSER */
+#define IFX_DMA_BLK_CLRE_CSER_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_CLRE_Bits.CSER */
+#define IFX_DMA_BLK_CLRE_CSER_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_CLRE_Bits.CSER */
+#define IFX_DMA_BLK_CLRE_CSER_OFF (16u)
+
+/** \brief Length for Ifx_DMA_BLK_CLRE_Bits.CSLLER */
+#define IFX_DMA_BLK_CLRE_CSLLER_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_CLRE_Bits.CSLLER */
+#define IFX_DMA_BLK_CLRE_CSLLER_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_CLRE_Bits.CSLLER */
+#define IFX_DMA_BLK_CLRE_CSLLER_OFF (25u)
+
+/** \brief Length for Ifx_DMA_BLK_CLRE_Bits.CSPBER */
+#define IFX_DMA_BLK_CLRE_CSPBER_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_CLRE_Bits.CSPBER */
+#define IFX_DMA_BLK_CLRE_CSPBER_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_CLRE_Bits.CSPBER */
+#define IFX_DMA_BLK_CLRE_CSPBER_OFF (20u)
+
+/** \brief Length for Ifx_DMA_BLK_CLRE_Bits.CSRIER */
+#define IFX_DMA_BLK_CLRE_CSRIER_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_CLRE_Bits.CSRIER */
+#define IFX_DMA_BLK_CLRE_CSRIER_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_CLRE_Bits.CSRIER */
+#define IFX_DMA_BLK_CLRE_CSRIER_OFF (21u)
+
+/** \brief Length for Ifx_DMA_BLK_EER_Bits.EDER */
+#define IFX_DMA_BLK_EER_EDER_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_EER_Bits.EDER */
+#define IFX_DMA_BLK_EER_EDER_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_EER_Bits.EDER */
+#define IFX_DMA_BLK_EER_EDER_OFF (17u)
+
+/** \brief Length for Ifx_DMA_BLK_EER_Bits.ELER */
+#define IFX_DMA_BLK_EER_ELER_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_EER_Bits.ELER */
+#define IFX_DMA_BLK_EER_ELER_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_EER_Bits.ELER */
+#define IFX_DMA_BLK_EER_ELER_OFF (26u)
+
+/** \brief Length for Ifx_DMA_BLK_EER_Bits.ERER */
+#define IFX_DMA_BLK_EER_ERER_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_EER_Bits.ERER */
+#define IFX_DMA_BLK_EER_ERER_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_EER_Bits.ERER */
+#define IFX_DMA_BLK_EER_ERER_OFF (24u)
+
+/** \brief Length for Ifx_DMA_BLK_EER_Bits.ESER */
+#define IFX_DMA_BLK_EER_ESER_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_EER_Bits.ESER */
+#define IFX_DMA_BLK_EER_ESER_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_EER_Bits.ESER */
+#define IFX_DMA_BLK_EER_ESER_OFF (16u)
+
+/** \brief Length for Ifx_DMA_BLK_ERRSR_Bits.DER */
+#define IFX_DMA_BLK_ERRSR_DER_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_ERRSR_Bits.DER */
+#define IFX_DMA_BLK_ERRSR_DER_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_ERRSR_Bits.DER */
+#define IFX_DMA_BLK_ERRSR_DER_OFF (17u)
+
+/** \brief Length for Ifx_DMA_BLK_ERRSR_Bits.DLLER */
+#define IFX_DMA_BLK_ERRSR_DLLER_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_ERRSR_Bits.DLLER */
+#define IFX_DMA_BLK_ERRSR_DLLER_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_ERRSR_Bits.DLLER */
+#define IFX_DMA_BLK_ERRSR_DLLER_OFF (26u)
+
+/** \brief Length for Ifx_DMA_BLK_ERRSR_Bits.LEC */
+#define IFX_DMA_BLK_ERRSR_LEC_LEN (7u)
+
+/** \brief Mask for Ifx_DMA_BLK_ERRSR_Bits.LEC */
+#define IFX_DMA_BLK_ERRSR_LEC_MSK (0x7fu)
+
+/** \brief Offset for Ifx_DMA_BLK_ERRSR_Bits.LEC */
+#define IFX_DMA_BLK_ERRSR_LEC_OFF (0u)
+
+/** \brief Length for Ifx_DMA_BLK_ERRSR_Bits.RAMER */
+#define IFX_DMA_BLK_ERRSR_RAMER_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_ERRSR_Bits.RAMER */
+#define IFX_DMA_BLK_ERRSR_RAMER_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_ERRSR_Bits.RAMER */
+#define IFX_DMA_BLK_ERRSR_RAMER_OFF (24u)
+
+/** \brief Length for Ifx_DMA_BLK_ERRSR_Bits.SER */
+#define IFX_DMA_BLK_ERRSR_SER_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_ERRSR_Bits.SER */
+#define IFX_DMA_BLK_ERRSR_SER_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_ERRSR_Bits.SER */
+#define IFX_DMA_BLK_ERRSR_SER_OFF (16u)
+
+/** \brief Length for Ifx_DMA_BLK_ERRSR_Bits.SLLER */
+#define IFX_DMA_BLK_ERRSR_SLLER_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_ERRSR_Bits.SLLER */
+#define IFX_DMA_BLK_ERRSR_SLLER_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_ERRSR_Bits.SLLER */
+#define IFX_DMA_BLK_ERRSR_SLLER_OFF (25u)
+
+/** \brief Length for Ifx_DMA_BLK_ERRSR_Bits.SPBER */
+#define IFX_DMA_BLK_ERRSR_SPBER_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_ERRSR_Bits.SPBER */
+#define IFX_DMA_BLK_ERRSR_SPBER_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_ERRSR_Bits.SPBER */
+#define IFX_DMA_BLK_ERRSR_SPBER_OFF (20u)
+
+/** \brief Length for Ifx_DMA_BLK_ERRSR_Bits.SRIER */
+#define IFX_DMA_BLK_ERRSR_SRIER_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_ERRSR_Bits.SRIER */
+#define IFX_DMA_BLK_ERRSR_SRIER_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_ERRSR_Bits.SRIER */
+#define IFX_DMA_BLK_ERRSR_SRIER_OFF (21u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_ADICR_Bits.CBLD */
+#define IFX_DMA_BLK_ME_ADICR_CBLD_LEN (4u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_ADICR_Bits.CBLD */
+#define IFX_DMA_BLK_ME_ADICR_CBLD_MSK (0xfu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_ADICR_Bits.CBLD */
+#define IFX_DMA_BLK_ME_ADICR_CBLD_OFF (12u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_ADICR_Bits.CBLS */
+#define IFX_DMA_BLK_ME_ADICR_CBLS_LEN (4u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_ADICR_Bits.CBLS */
+#define IFX_DMA_BLK_ME_ADICR_CBLS_MSK (0xfu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_ADICR_Bits.CBLS */
+#define IFX_DMA_BLK_ME_ADICR_CBLS_OFF (8u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_ADICR_Bits.DCBE */
+#define IFX_DMA_BLK_ME_ADICR_DCBE_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_ADICR_Bits.DCBE */
+#define IFX_DMA_BLK_ME_ADICR_DCBE_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_ADICR_Bits.DCBE */
+#define IFX_DMA_BLK_ME_ADICR_DCBE_OFF (21u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_ADICR_Bits.DMF */
+#define IFX_DMA_BLK_ME_ADICR_DMF_LEN (3u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_ADICR_Bits.DMF */
+#define IFX_DMA_BLK_ME_ADICR_DMF_MSK (0x7u)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_ADICR_Bits.DMF */
+#define IFX_DMA_BLK_ME_ADICR_DMF_OFF (4u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_ADICR_Bits.ETRL */
+#define IFX_DMA_BLK_ME_ADICR_ETRL_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_ADICR_Bits.ETRL */
+#define IFX_DMA_BLK_ME_ADICR_ETRL_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_ADICR_Bits.ETRL */
+#define IFX_DMA_BLK_ME_ADICR_ETRL_OFF (23u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_ADICR_Bits.INCD */
+#define IFX_DMA_BLK_ME_ADICR_INCD_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_ADICR_Bits.INCD */
+#define IFX_DMA_BLK_ME_ADICR_INCD_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_ADICR_Bits.INCD */
+#define IFX_DMA_BLK_ME_ADICR_INCD_OFF (7u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_ADICR_Bits.INCS */
+#define IFX_DMA_BLK_ME_ADICR_INCS_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_ADICR_Bits.INCS */
+#define IFX_DMA_BLK_ME_ADICR_INCS_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_ADICR_Bits.INCS */
+#define IFX_DMA_BLK_ME_ADICR_INCS_OFF (3u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_ADICR_Bits.INTCT */
+#define IFX_DMA_BLK_ME_ADICR_INTCT_LEN (2u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_ADICR_Bits.INTCT */
+#define IFX_DMA_BLK_ME_ADICR_INTCT_MSK (0x3u)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_ADICR_Bits.INTCT */
+#define IFX_DMA_BLK_ME_ADICR_INTCT_OFF (26u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_ADICR_Bits.IRDV */
+#define IFX_DMA_BLK_ME_ADICR_IRDV_LEN (4u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_ADICR_Bits.IRDV */
+#define IFX_DMA_BLK_ME_ADICR_IRDV_MSK (0xfu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_ADICR_Bits.IRDV */
+#define IFX_DMA_BLK_ME_ADICR_IRDV_OFF (28u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_ADICR_Bits.SCBE */
+#define IFX_DMA_BLK_ME_ADICR_SCBE_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_ADICR_Bits.SCBE */
+#define IFX_DMA_BLK_ME_ADICR_SCBE_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_ADICR_Bits.SCBE */
+#define IFX_DMA_BLK_ME_ADICR_SCBE_OFF (20u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_ADICR_Bits.SHCT */
+#define IFX_DMA_BLK_ME_ADICR_SHCT_LEN (4u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_ADICR_Bits.SHCT */
+#define IFX_DMA_BLK_ME_ADICR_SHCT_MSK (0xfu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_ADICR_Bits.SHCT */
+#define IFX_DMA_BLK_ME_ADICR_SHCT_OFF (16u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_ADICR_Bits.SMF */
+#define IFX_DMA_BLK_ME_ADICR_SMF_LEN (3u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_ADICR_Bits.SMF */
+#define IFX_DMA_BLK_ME_ADICR_SMF_MSK (0x7u)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_ADICR_Bits.SMF */
+#define IFX_DMA_BLK_ME_ADICR_SMF_OFF (0u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_ADICR_Bits.STAMP */
+#define IFX_DMA_BLK_ME_ADICR_STAMP_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_ADICR_Bits.STAMP */
+#define IFX_DMA_BLK_ME_ADICR_STAMP_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_ADICR_Bits.STAMP */
+#define IFX_DMA_BLK_ME_ADICR_STAMP_OFF (22u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_ADICR_Bits.WRPDE */
+#define IFX_DMA_BLK_ME_ADICR_WRPDE_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_ADICR_Bits.WRPDE */
+#define IFX_DMA_BLK_ME_ADICR_WRPDE_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_ADICR_Bits.WRPDE */
+#define IFX_DMA_BLK_ME_ADICR_WRPDE_OFF (25u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_ADICR_Bits.WRPSE */
+#define IFX_DMA_BLK_ME_ADICR_WRPSE_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_ADICR_Bits.WRPSE */
+#define IFX_DMA_BLK_ME_ADICR_WRPSE_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_ADICR_Bits.WRPSE */
+#define IFX_DMA_BLK_ME_ADICR_WRPSE_OFF (24u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_CHCR_Bits.BLKM */
+#define IFX_DMA_BLK_ME_CHCR_BLKM_LEN (3u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_CHCR_Bits.BLKM */
+#define IFX_DMA_BLK_ME_CHCR_BLKM_MSK (0x7u)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_CHCR_Bits.BLKM */
+#define IFX_DMA_BLK_ME_CHCR_BLKM_OFF (16u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_CHCR_Bits.CHDW */
+#define IFX_DMA_BLK_ME_CHCR_CHDW_LEN (3u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_CHCR_Bits.CHDW */
+#define IFX_DMA_BLK_ME_CHCR_CHDW_MSK (0x7u)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_CHCR_Bits.CHDW */
+#define IFX_DMA_BLK_ME_CHCR_CHDW_OFF (21u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_CHCR_Bits.CHMODE */
+#define IFX_DMA_BLK_ME_CHCR_CHMODE_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_CHCR_Bits.CHMODE */
+#define IFX_DMA_BLK_ME_CHCR_CHMODE_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_CHCR_Bits.CHMODE */
+#define IFX_DMA_BLK_ME_CHCR_CHMODE_OFF (20u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_CHCR_Bits.DMAPRIO */
+#define IFX_DMA_BLK_ME_CHCR_DMAPRIO_LEN (2u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_CHCR_Bits.DMAPRIO */
+#define IFX_DMA_BLK_ME_CHCR_DMAPRIO_MSK (0x3u)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_CHCR_Bits.DMAPRIO */
+#define IFX_DMA_BLK_ME_CHCR_DMAPRIO_OFF (30u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_CHCR_Bits.PATSEL */
+#define IFX_DMA_BLK_ME_CHCR_PATSEL_LEN (3u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_CHCR_Bits.PATSEL */
+#define IFX_DMA_BLK_ME_CHCR_PATSEL_MSK (0x7u)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_CHCR_Bits.PATSEL */
+#define IFX_DMA_BLK_ME_CHCR_PATSEL_OFF (24u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_CHCR_Bits.PRSEL */
+#define IFX_DMA_BLK_ME_CHCR_PRSEL_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_CHCR_Bits.PRSEL */
+#define IFX_DMA_BLK_ME_CHCR_PRSEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_CHCR_Bits.PRSEL */
+#define IFX_DMA_BLK_ME_CHCR_PRSEL_OFF (28u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_CHCR_Bits.RROAT */
+#define IFX_DMA_BLK_ME_CHCR_RROAT_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_CHCR_Bits.RROAT */
+#define IFX_DMA_BLK_ME_CHCR_RROAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_CHCR_Bits.RROAT */
+#define IFX_DMA_BLK_ME_CHCR_RROAT_OFF (19u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_CHCR_Bits.TREL */
+#define IFX_DMA_BLK_ME_CHCR_TREL_LEN (14u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_CHCR_Bits.TREL */
+#define IFX_DMA_BLK_ME_CHCR_TREL_MSK (0x3fffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_CHCR_Bits.TREL */
+#define IFX_DMA_BLK_ME_CHCR_TREL_OFF (0u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_CHSR_Bits.BUFFER */
+#define IFX_DMA_BLK_ME_CHSR_BUFFER_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_CHSR_Bits.BUFFER */
+#define IFX_DMA_BLK_ME_CHSR_BUFFER_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_CHSR_Bits.BUFFER */
+#define IFX_DMA_BLK_ME_CHSR_BUFFER_OFF (22u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_CHSR_Bits.FROZEN */
+#define IFX_DMA_BLK_ME_CHSR_FROZEN_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_CHSR_Bits.FROZEN */
+#define IFX_DMA_BLK_ME_CHSR_FROZEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_CHSR_Bits.FROZEN */
+#define IFX_DMA_BLK_ME_CHSR_FROZEN_OFF (23u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_CHSR_Bits.ICH */
+#define IFX_DMA_BLK_ME_CHSR_ICH_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_CHSR_Bits.ICH */
+#define IFX_DMA_BLK_ME_CHSR_ICH_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_CHSR_Bits.ICH */
+#define IFX_DMA_BLK_ME_CHSR_ICH_OFF (18u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_CHSR_Bits.IPM */
+#define IFX_DMA_BLK_ME_CHSR_IPM_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_CHSR_Bits.IPM */
+#define IFX_DMA_BLK_ME_CHSR_IPM_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_CHSR_Bits.IPM */
+#define IFX_DMA_BLK_ME_CHSR_IPM_OFF (19u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_CHSR_Bits.LXO */
+#define IFX_DMA_BLK_ME_CHSR_LXO_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_CHSR_Bits.LXO */
+#define IFX_DMA_BLK_ME_CHSR_LXO_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_CHSR_Bits.LXO */
+#define IFX_DMA_BLK_ME_CHSR_LXO_OFF (15u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_CHSR_Bits.TCOUNT */
+#define IFX_DMA_BLK_ME_CHSR_TCOUNT_LEN (14u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_CHSR_Bits.TCOUNT */
+#define IFX_DMA_BLK_ME_CHSR_TCOUNT_MSK (0x3fffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_CHSR_Bits.TCOUNT */
+#define IFX_DMA_BLK_ME_CHSR_TCOUNT_OFF (0u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_CHSR_Bits.WRPD */
+#define IFX_DMA_BLK_ME_CHSR_WRPD_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_CHSR_Bits.WRPD */
+#define IFX_DMA_BLK_ME_CHSR_WRPD_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_CHSR_Bits.WRPD */
+#define IFX_DMA_BLK_ME_CHSR_WRPD_OFF (17u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_CHSR_Bits.WRPS */
+#define IFX_DMA_BLK_ME_CHSR_WRPS_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_CHSR_Bits.WRPS */
+#define IFX_DMA_BLK_ME_CHSR_WRPS_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_CHSR_Bits.WRPS */
+#define IFX_DMA_BLK_ME_CHSR_WRPS_OFF (16u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_DADR_Bits.DADR */
+#define IFX_DMA_BLK_ME_DADR_DADR_LEN (32u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_DADR_Bits.DADR */
+#define IFX_DMA_BLK_ME_DADR_DADR_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_DADR_Bits.DADR */
+#define IFX_DMA_BLK_ME_DADR_DADR_OFF (0u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R0_Bits.RD00 */
+#define IFX_DMA_BLK_ME_R0_RD00_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R0_Bits.RD00 */
+#define IFX_DMA_BLK_ME_R0_RD00_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R0_Bits.RD00 */
+#define IFX_DMA_BLK_ME_R0_RD00_OFF (0u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R0_Bits.RD01 */
+#define IFX_DMA_BLK_ME_R0_RD01_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R0_Bits.RD01 */
+#define IFX_DMA_BLK_ME_R0_RD01_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R0_Bits.RD01 */
+#define IFX_DMA_BLK_ME_R0_RD01_OFF (8u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R0_Bits.RD02 */
+#define IFX_DMA_BLK_ME_R0_RD02_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R0_Bits.RD02 */
+#define IFX_DMA_BLK_ME_R0_RD02_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R0_Bits.RD02 */
+#define IFX_DMA_BLK_ME_R0_RD02_OFF (16u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R0_Bits.RD03 */
+#define IFX_DMA_BLK_ME_R0_RD03_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R0_Bits.RD03 */
+#define IFX_DMA_BLK_ME_R0_RD03_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R0_Bits.RD03 */
+#define IFX_DMA_BLK_ME_R0_RD03_OFF (24u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R1_Bits.RD10 */
+#define IFX_DMA_BLK_ME_R1_RD10_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R1_Bits.RD10 */
+#define IFX_DMA_BLK_ME_R1_RD10_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R1_Bits.RD10 */
+#define IFX_DMA_BLK_ME_R1_RD10_OFF (0u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R1_Bits.RD11 */
+#define IFX_DMA_BLK_ME_R1_RD11_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R1_Bits.RD11 */
+#define IFX_DMA_BLK_ME_R1_RD11_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R1_Bits.RD11 */
+#define IFX_DMA_BLK_ME_R1_RD11_OFF (8u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R1_Bits.RD12 */
+#define IFX_DMA_BLK_ME_R1_RD12_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R1_Bits.RD12 */
+#define IFX_DMA_BLK_ME_R1_RD12_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R1_Bits.RD12 */
+#define IFX_DMA_BLK_ME_R1_RD12_OFF (16u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R1_Bits.RD13 */
+#define IFX_DMA_BLK_ME_R1_RD13_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R1_Bits.RD13 */
+#define IFX_DMA_BLK_ME_R1_RD13_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R1_Bits.RD13 */
+#define IFX_DMA_BLK_ME_R1_RD13_OFF (24u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R2_Bits.RD20 */
+#define IFX_DMA_BLK_ME_R2_RD20_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R2_Bits.RD20 */
+#define IFX_DMA_BLK_ME_R2_RD20_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R2_Bits.RD20 */
+#define IFX_DMA_BLK_ME_R2_RD20_OFF (0u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R2_Bits.RD21 */
+#define IFX_DMA_BLK_ME_R2_RD21_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R2_Bits.RD21 */
+#define IFX_DMA_BLK_ME_R2_RD21_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R2_Bits.RD21 */
+#define IFX_DMA_BLK_ME_R2_RD21_OFF (8u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R2_Bits.RD22 */
+#define IFX_DMA_BLK_ME_R2_RD22_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R2_Bits.RD22 */
+#define IFX_DMA_BLK_ME_R2_RD22_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R2_Bits.RD22 */
+#define IFX_DMA_BLK_ME_R2_RD22_OFF (16u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R2_Bits.RD23 */
+#define IFX_DMA_BLK_ME_R2_RD23_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R2_Bits.RD23 */
+#define IFX_DMA_BLK_ME_R2_RD23_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R2_Bits.RD23 */
+#define IFX_DMA_BLK_ME_R2_RD23_OFF (24u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R3_Bits.RD30 */
+#define IFX_DMA_BLK_ME_R3_RD30_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R3_Bits.RD30 */
+#define IFX_DMA_BLK_ME_R3_RD30_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R3_Bits.RD30 */
+#define IFX_DMA_BLK_ME_R3_RD30_OFF (0u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R3_Bits.RD31 */
+#define IFX_DMA_BLK_ME_R3_RD31_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R3_Bits.RD31 */
+#define IFX_DMA_BLK_ME_R3_RD31_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R3_Bits.RD31 */
+#define IFX_DMA_BLK_ME_R3_RD31_OFF (8u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R3_Bits.RD32 */
+#define IFX_DMA_BLK_ME_R3_RD32_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R3_Bits.RD32 */
+#define IFX_DMA_BLK_ME_R3_RD32_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R3_Bits.RD32 */
+#define IFX_DMA_BLK_ME_R3_RD32_OFF (16u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R3_Bits.RD33 */
+#define IFX_DMA_BLK_ME_R3_RD33_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R3_Bits.RD33 */
+#define IFX_DMA_BLK_ME_R3_RD33_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R3_Bits.RD33 */
+#define IFX_DMA_BLK_ME_R3_RD33_OFF (24u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R4_Bits.RD40 */
+#define IFX_DMA_BLK_ME_R4_RD40_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R4_Bits.RD40 */
+#define IFX_DMA_BLK_ME_R4_RD40_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R4_Bits.RD40 */
+#define IFX_DMA_BLK_ME_R4_RD40_OFF (0u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R4_Bits.RD41 */
+#define IFX_DMA_BLK_ME_R4_RD41_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R4_Bits.RD41 */
+#define IFX_DMA_BLK_ME_R4_RD41_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R4_Bits.RD41 */
+#define IFX_DMA_BLK_ME_R4_RD41_OFF (8u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R4_Bits.RD42 */
+#define IFX_DMA_BLK_ME_R4_RD42_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R4_Bits.RD42 */
+#define IFX_DMA_BLK_ME_R4_RD42_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R4_Bits.RD42 */
+#define IFX_DMA_BLK_ME_R4_RD42_OFF (16u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R4_Bits.RD43 */
+#define IFX_DMA_BLK_ME_R4_RD43_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R4_Bits.RD43 */
+#define IFX_DMA_BLK_ME_R4_RD43_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R4_Bits.RD43 */
+#define IFX_DMA_BLK_ME_R4_RD43_OFF (24u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R5_Bits.RD50 */
+#define IFX_DMA_BLK_ME_R5_RD50_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R5_Bits.RD50 */
+#define IFX_DMA_BLK_ME_R5_RD50_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R5_Bits.RD50 */
+#define IFX_DMA_BLK_ME_R5_RD50_OFF (0u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R5_Bits.RD51 */
+#define IFX_DMA_BLK_ME_R5_RD51_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R5_Bits.RD51 */
+#define IFX_DMA_BLK_ME_R5_RD51_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R5_Bits.RD51 */
+#define IFX_DMA_BLK_ME_R5_RD51_OFF (8u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R5_Bits.RD52 */
+#define IFX_DMA_BLK_ME_R5_RD52_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R5_Bits.RD52 */
+#define IFX_DMA_BLK_ME_R5_RD52_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R5_Bits.RD52 */
+#define IFX_DMA_BLK_ME_R5_RD52_OFF (16u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R5_Bits.RD53 */
+#define IFX_DMA_BLK_ME_R5_RD53_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R5_Bits.RD53 */
+#define IFX_DMA_BLK_ME_R5_RD53_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R5_Bits.RD53 */
+#define IFX_DMA_BLK_ME_R5_RD53_OFF (24u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R6_Bits.RD60 */
+#define IFX_DMA_BLK_ME_R6_RD60_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R6_Bits.RD60 */
+#define IFX_DMA_BLK_ME_R6_RD60_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R6_Bits.RD60 */
+#define IFX_DMA_BLK_ME_R6_RD60_OFF (0u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R6_Bits.RD61 */
+#define IFX_DMA_BLK_ME_R6_RD61_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R6_Bits.RD61 */
+#define IFX_DMA_BLK_ME_R6_RD61_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R6_Bits.RD61 */
+#define IFX_DMA_BLK_ME_R6_RD61_OFF (8u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R6_Bits.RD62 */
+#define IFX_DMA_BLK_ME_R6_RD62_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R6_Bits.RD62 */
+#define IFX_DMA_BLK_ME_R6_RD62_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R6_Bits.RD62 */
+#define IFX_DMA_BLK_ME_R6_RD62_OFF (16u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R6_Bits.RD63 */
+#define IFX_DMA_BLK_ME_R6_RD63_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R6_Bits.RD63 */
+#define IFX_DMA_BLK_ME_R6_RD63_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R6_Bits.RD63 */
+#define IFX_DMA_BLK_ME_R6_RD63_OFF (24u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R7_Bits.RD70 */
+#define IFX_DMA_BLK_ME_R7_RD70_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R7_Bits.RD70 */
+#define IFX_DMA_BLK_ME_R7_RD70_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R7_Bits.RD70 */
+#define IFX_DMA_BLK_ME_R7_RD70_OFF (0u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R7_Bits.RD71 */
+#define IFX_DMA_BLK_ME_R7_RD71_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R7_Bits.RD71 */
+#define IFX_DMA_BLK_ME_R7_RD71_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R7_Bits.RD71 */
+#define IFX_DMA_BLK_ME_R7_RD71_OFF (8u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R7_Bits.RD72 */
+#define IFX_DMA_BLK_ME_R7_RD72_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R7_Bits.RD72 */
+#define IFX_DMA_BLK_ME_R7_RD72_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R7_Bits.RD72 */
+#define IFX_DMA_BLK_ME_R7_RD72_OFF (16u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_R7_Bits.RD73 */
+#define IFX_DMA_BLK_ME_R7_RD73_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_R7_Bits.RD73 */
+#define IFX_DMA_BLK_ME_R7_RD73_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_R7_Bits.RD73 */
+#define IFX_DMA_BLK_ME_R7_RD73_OFF (24u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_RDCRC_Bits.RDCRC */
+#define IFX_DMA_BLK_ME_RDCRC_RDCRC_LEN (32u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_RDCRC_Bits.RDCRC */
+#define IFX_DMA_BLK_ME_RDCRC_RDCRC_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_RDCRC_Bits.RDCRC */
+#define IFX_DMA_BLK_ME_RDCRC_RDCRC_OFF (0u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_SADR_Bits.SADR */
+#define IFX_DMA_BLK_ME_SADR_SADR_LEN (32u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_SADR_Bits.SADR */
+#define IFX_DMA_BLK_ME_SADR_SADR_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_SADR_Bits.SADR */
+#define IFX_DMA_BLK_ME_SADR_SADR_OFF (0u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_SDCRC_Bits.SDCRC */
+#define IFX_DMA_BLK_ME_SDCRC_SDCRC_LEN (32u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_SDCRC_Bits.SDCRC */
+#define IFX_DMA_BLK_ME_SDCRC_SDCRC_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_SDCRC_Bits.SDCRC */
+#define IFX_DMA_BLK_ME_SDCRC_SDCRC_OFF (0u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_SHADR_Bits.SHADR */
+#define IFX_DMA_BLK_ME_SHADR_SHADR_LEN (32u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_SHADR_Bits.SHADR */
+#define IFX_DMA_BLK_ME_SHADR_SHADR_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_SHADR_Bits.SHADR */
+#define IFX_DMA_BLK_ME_SHADR_SHADR_OFF (0u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_SR_Bits.CH */
+#define IFX_DMA_BLK_ME_SR_CH_LEN (7u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_SR_Bits.CH */
+#define IFX_DMA_BLK_ME_SR_CH_MSK (0x7fu)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_SR_Bits.CH */
+#define IFX_DMA_BLK_ME_SR_CH_OFF (16u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_SR_Bits.RS */
+#define IFX_DMA_BLK_ME_SR_RS_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_SR_Bits.RS */
+#define IFX_DMA_BLK_ME_SR_RS_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_SR_Bits.RS */
+#define IFX_DMA_BLK_ME_SR_RS_OFF (0u)
+
+/** \brief Length for Ifx_DMA_BLK_ME_SR_Bits.WS */
+#define IFX_DMA_BLK_ME_SR_WS_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_BLK_ME_SR_Bits.WS */
+#define IFX_DMA_BLK_ME_SR_WS_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_BLK_ME_SR_Bits.WS */
+#define IFX_DMA_BLK_ME_SR_WS_OFF (4u)
+
+/** \brief Length for Ifx_DMA_CH_ADICR_Bits.CBLD */
+#define IFX_DMA_CH_ADICR_CBLD_LEN (4u)
+
+/** \brief Mask for Ifx_DMA_CH_ADICR_Bits.CBLD */
+#define IFX_DMA_CH_ADICR_CBLD_MSK (0xfu)
+
+/** \brief Offset for Ifx_DMA_CH_ADICR_Bits.CBLD */
+#define IFX_DMA_CH_ADICR_CBLD_OFF (12u)
+
+/** \brief Length for Ifx_DMA_CH_ADICR_Bits.CBLS */
+#define IFX_DMA_CH_ADICR_CBLS_LEN (4u)
+
+/** \brief Mask for Ifx_DMA_CH_ADICR_Bits.CBLS */
+#define IFX_DMA_CH_ADICR_CBLS_MSK (0xfu)
+
+/** \brief Offset for Ifx_DMA_CH_ADICR_Bits.CBLS */
+#define IFX_DMA_CH_ADICR_CBLS_OFF (8u)
+
+/** \brief Length for Ifx_DMA_CH_ADICR_Bits.DCBE */
+#define IFX_DMA_CH_ADICR_DCBE_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_CH_ADICR_Bits.DCBE */
+#define IFX_DMA_CH_ADICR_DCBE_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_CH_ADICR_Bits.DCBE */
+#define IFX_DMA_CH_ADICR_DCBE_OFF (21u)
+
+/** \brief Length for Ifx_DMA_CH_ADICR_Bits.DMF */
+#define IFX_DMA_CH_ADICR_DMF_LEN (3u)
+
+/** \brief Mask for Ifx_DMA_CH_ADICR_Bits.DMF */
+#define IFX_DMA_CH_ADICR_DMF_MSK (0x7u)
+
+/** \brief Offset for Ifx_DMA_CH_ADICR_Bits.DMF */
+#define IFX_DMA_CH_ADICR_DMF_OFF (4u)
+
+/** \brief Length for Ifx_DMA_CH_ADICR_Bits.ETRL */
+#define IFX_DMA_CH_ADICR_ETRL_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_CH_ADICR_Bits.ETRL */
+#define IFX_DMA_CH_ADICR_ETRL_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_CH_ADICR_Bits.ETRL */
+#define IFX_DMA_CH_ADICR_ETRL_OFF (23u)
+
+/** \brief Length for Ifx_DMA_CH_ADICR_Bits.INCD */
+#define IFX_DMA_CH_ADICR_INCD_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_CH_ADICR_Bits.INCD */
+#define IFX_DMA_CH_ADICR_INCD_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_CH_ADICR_Bits.INCD */
+#define IFX_DMA_CH_ADICR_INCD_OFF (7u)
+
+/** \brief Length for Ifx_DMA_CH_ADICR_Bits.INCS */
+#define IFX_DMA_CH_ADICR_INCS_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_CH_ADICR_Bits.INCS */
+#define IFX_DMA_CH_ADICR_INCS_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_CH_ADICR_Bits.INCS */
+#define IFX_DMA_CH_ADICR_INCS_OFF (3u)
+
+/** \brief Length for Ifx_DMA_CH_ADICR_Bits.INTCT */
+#define IFX_DMA_CH_ADICR_INTCT_LEN (2u)
+
+/** \brief Mask for Ifx_DMA_CH_ADICR_Bits.INTCT */
+#define IFX_DMA_CH_ADICR_INTCT_MSK (0x3u)
+
+/** \brief Offset for Ifx_DMA_CH_ADICR_Bits.INTCT */
+#define IFX_DMA_CH_ADICR_INTCT_OFF (26u)
+
+/** \brief Length for Ifx_DMA_CH_ADICR_Bits.IRDV */
+#define IFX_DMA_CH_ADICR_IRDV_LEN (4u)
+
+/** \brief Mask for Ifx_DMA_CH_ADICR_Bits.IRDV */
+#define IFX_DMA_CH_ADICR_IRDV_MSK (0xfu)
+
+/** \brief Offset for Ifx_DMA_CH_ADICR_Bits.IRDV */
+#define IFX_DMA_CH_ADICR_IRDV_OFF (28u)
+
+/** \brief Length for Ifx_DMA_CH_ADICR_Bits.SCBE */
+#define IFX_DMA_CH_ADICR_SCBE_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_CH_ADICR_Bits.SCBE */
+#define IFX_DMA_CH_ADICR_SCBE_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_CH_ADICR_Bits.SCBE */
+#define IFX_DMA_CH_ADICR_SCBE_OFF (20u)
+
+/** \brief Length for Ifx_DMA_CH_ADICR_Bits.SHCT */
+#define IFX_DMA_CH_ADICR_SHCT_LEN (4u)
+
+/** \brief Mask for Ifx_DMA_CH_ADICR_Bits.SHCT */
+#define IFX_DMA_CH_ADICR_SHCT_MSK (0xfu)
+
+/** \brief Offset for Ifx_DMA_CH_ADICR_Bits.SHCT */
+#define IFX_DMA_CH_ADICR_SHCT_OFF (16u)
+
+/** \brief Length for Ifx_DMA_CH_ADICR_Bits.SMF */
+#define IFX_DMA_CH_ADICR_SMF_LEN (3u)
+
+/** \brief Mask for Ifx_DMA_CH_ADICR_Bits.SMF */
+#define IFX_DMA_CH_ADICR_SMF_MSK (0x7u)
+
+/** \brief Offset for Ifx_DMA_CH_ADICR_Bits.SMF */
+#define IFX_DMA_CH_ADICR_SMF_OFF (0u)
+
+/** \brief Length for Ifx_DMA_CH_ADICR_Bits.STAMP */
+#define IFX_DMA_CH_ADICR_STAMP_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_CH_ADICR_Bits.STAMP */
+#define IFX_DMA_CH_ADICR_STAMP_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_CH_ADICR_Bits.STAMP */
+#define IFX_DMA_CH_ADICR_STAMP_OFF (22u)
+
+/** \brief Length for Ifx_DMA_CH_ADICR_Bits.WRPDE */
+#define IFX_DMA_CH_ADICR_WRPDE_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_CH_ADICR_Bits.WRPDE */
+#define IFX_DMA_CH_ADICR_WRPDE_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_CH_ADICR_Bits.WRPDE */
+#define IFX_DMA_CH_ADICR_WRPDE_OFF (25u)
+
+/** \brief Length for Ifx_DMA_CH_ADICR_Bits.WRPSE */
+#define IFX_DMA_CH_ADICR_WRPSE_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_CH_ADICR_Bits.WRPSE */
+#define IFX_DMA_CH_ADICR_WRPSE_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_CH_ADICR_Bits.WRPSE */
+#define IFX_DMA_CH_ADICR_WRPSE_OFF (24u)
+
+/** \brief Length for Ifx_DMA_CH_CHCFGR_Bits.BLKM */
+#define IFX_DMA_CH_CHCFGR_BLKM_LEN (3u)
+
+/** \brief Mask for Ifx_DMA_CH_CHCFGR_Bits.BLKM */
+#define IFX_DMA_CH_CHCFGR_BLKM_MSK (0x7u)
+
+/** \brief Offset for Ifx_DMA_CH_CHCFGR_Bits.BLKM */
+#define IFX_DMA_CH_CHCFGR_BLKM_OFF (16u)
+
+/** \brief Length for Ifx_DMA_CH_CHCFGR_Bits.CHDW */
+#define IFX_DMA_CH_CHCFGR_CHDW_LEN (3u)
+
+/** \brief Mask for Ifx_DMA_CH_CHCFGR_Bits.CHDW */
+#define IFX_DMA_CH_CHCFGR_CHDW_MSK (0x7u)
+
+/** \brief Offset for Ifx_DMA_CH_CHCFGR_Bits.CHDW */
+#define IFX_DMA_CH_CHCFGR_CHDW_OFF (21u)
+
+/** \brief Length for Ifx_DMA_CH_CHCFGR_Bits.CHMODE */
+#define IFX_DMA_CH_CHCFGR_CHMODE_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_CH_CHCFGR_Bits.CHMODE */
+#define IFX_DMA_CH_CHCFGR_CHMODE_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_CH_CHCFGR_Bits.CHMODE */
+#define IFX_DMA_CH_CHCFGR_CHMODE_OFF (20u)
+
+/** \brief Length for Ifx_DMA_CH_CHCFGR_Bits.DMAPRIO */
+#define IFX_DMA_CH_CHCFGR_DMAPRIO_LEN (2u)
+
+/** \brief Mask for Ifx_DMA_CH_CHCFGR_Bits.DMAPRIO */
+#define IFX_DMA_CH_CHCFGR_DMAPRIO_MSK (0x3u)
+
+/** \brief Offset for Ifx_DMA_CH_CHCFGR_Bits.DMAPRIO */
+#define IFX_DMA_CH_CHCFGR_DMAPRIO_OFF (30u)
+
+/** \brief Length for Ifx_DMA_CH_CHCFGR_Bits.PATSEL */
+#define IFX_DMA_CH_CHCFGR_PATSEL_LEN (3u)
+
+/** \brief Mask for Ifx_DMA_CH_CHCFGR_Bits.PATSEL */
+#define IFX_DMA_CH_CHCFGR_PATSEL_MSK (0x7u)
+
+/** \brief Offset for Ifx_DMA_CH_CHCFGR_Bits.PATSEL */
+#define IFX_DMA_CH_CHCFGR_PATSEL_OFF (24u)
+
+/** \brief Length for Ifx_DMA_CH_CHCFGR_Bits.PRSEL */
+#define IFX_DMA_CH_CHCFGR_PRSEL_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_CH_CHCFGR_Bits.PRSEL */
+#define IFX_DMA_CH_CHCFGR_PRSEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_CH_CHCFGR_Bits.PRSEL */
+#define IFX_DMA_CH_CHCFGR_PRSEL_OFF (28u)
+
+/** \brief Length for Ifx_DMA_CH_CHCFGR_Bits.RROAT */
+#define IFX_DMA_CH_CHCFGR_RROAT_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_CH_CHCFGR_Bits.RROAT */
+#define IFX_DMA_CH_CHCFGR_RROAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_CH_CHCFGR_Bits.RROAT */
+#define IFX_DMA_CH_CHCFGR_RROAT_OFF (19u)
+
+/** \brief Length for Ifx_DMA_CH_CHCFGR_Bits.TREL */
+#define IFX_DMA_CH_CHCFGR_TREL_LEN (14u)
+
+/** \brief Mask for Ifx_DMA_CH_CHCFGR_Bits.TREL */
+#define IFX_DMA_CH_CHCFGR_TREL_MSK (0x3fffu)
+
+/** \brief Offset for Ifx_DMA_CH_CHCFGR_Bits.TREL */
+#define IFX_DMA_CH_CHCFGR_TREL_OFF (0u)
+
+/** \brief Length for Ifx_DMA_CH_CHCSR_Bits.BUFFER */
+#define IFX_DMA_CH_CHCSR_BUFFER_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_CH_CHCSR_Bits.BUFFER */
+#define IFX_DMA_CH_CHCSR_BUFFER_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_CH_CHCSR_Bits.BUFFER */
+#define IFX_DMA_CH_CHCSR_BUFFER_OFF (22u)
+
+/** \brief Length for Ifx_DMA_CH_CHCSR_Bits.CICH */
+#define IFX_DMA_CH_CHCSR_CICH_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_CH_CHCSR_Bits.CICH */
+#define IFX_DMA_CH_CHCSR_CICH_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_CH_CHCSR_Bits.CICH */
+#define IFX_DMA_CH_CHCSR_CICH_OFF (26u)
+
+/** \brief Length for Ifx_DMA_CH_CHCSR_Bits.CWRP */
+#define IFX_DMA_CH_CHCSR_CWRP_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_CH_CHCSR_Bits.CWRP */
+#define IFX_DMA_CH_CHCSR_CWRP_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_CH_CHCSR_Bits.CWRP */
+#define IFX_DMA_CH_CHCSR_CWRP_OFF (25u)
+
+/** \brief Length for Ifx_DMA_CH_CHCSR_Bits.FROZEN */
+#define IFX_DMA_CH_CHCSR_FROZEN_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_CH_CHCSR_Bits.FROZEN */
+#define IFX_DMA_CH_CHCSR_FROZEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_CH_CHCSR_Bits.FROZEN */
+#define IFX_DMA_CH_CHCSR_FROZEN_OFF (23u)
+
+/** \brief Length for Ifx_DMA_CH_CHCSR_Bits.ICH */
+#define IFX_DMA_CH_CHCSR_ICH_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_CH_CHCSR_Bits.ICH */
+#define IFX_DMA_CH_CHCSR_ICH_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_CH_CHCSR_Bits.ICH */
+#define IFX_DMA_CH_CHCSR_ICH_OFF (18u)
+
+/** \brief Length for Ifx_DMA_CH_CHCSR_Bits.IPM */
+#define IFX_DMA_CH_CHCSR_IPM_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_CH_CHCSR_Bits.IPM */
+#define IFX_DMA_CH_CHCSR_IPM_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_CH_CHCSR_Bits.IPM */
+#define IFX_DMA_CH_CHCSR_IPM_OFF (19u)
+
+/** \brief Length for Ifx_DMA_CH_CHCSR_Bits.LXO */
+#define IFX_DMA_CH_CHCSR_LXO_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_CH_CHCSR_Bits.LXO */
+#define IFX_DMA_CH_CHCSR_LXO_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_CH_CHCSR_Bits.LXO */
+#define IFX_DMA_CH_CHCSR_LXO_OFF (15u)
+
+/** \brief Length for Ifx_DMA_CH_CHCSR_Bits.SCH */
+#define IFX_DMA_CH_CHCSR_SCH_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_CH_CHCSR_Bits.SCH */
+#define IFX_DMA_CH_CHCSR_SCH_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_CH_CHCSR_Bits.SCH */
+#define IFX_DMA_CH_CHCSR_SCH_OFF (31u)
+
+/** \brief Length for Ifx_DMA_CH_CHCSR_Bits.SIT */
+#define IFX_DMA_CH_CHCSR_SIT_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_CH_CHCSR_Bits.SIT */
+#define IFX_DMA_CH_CHCSR_SIT_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_CH_CHCSR_Bits.SIT */
+#define IFX_DMA_CH_CHCSR_SIT_OFF (27u)
+
+/** \brief Length for Ifx_DMA_CH_CHCSR_Bits.SWB */
+#define IFX_DMA_CH_CHCSR_SWB_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_CH_CHCSR_Bits.SWB */
+#define IFX_DMA_CH_CHCSR_SWB_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_CH_CHCSR_Bits.SWB */
+#define IFX_DMA_CH_CHCSR_SWB_OFF (24u)
+
+/** \brief Length for Ifx_DMA_CH_CHCSR_Bits.TCOUNT */
+#define IFX_DMA_CH_CHCSR_TCOUNT_LEN (14u)
+
+/** \brief Mask for Ifx_DMA_CH_CHCSR_Bits.TCOUNT */
+#define IFX_DMA_CH_CHCSR_TCOUNT_MSK (0x3fffu)
+
+/** \brief Offset for Ifx_DMA_CH_CHCSR_Bits.TCOUNT */
+#define IFX_DMA_CH_CHCSR_TCOUNT_OFF (0u)
+
+/** \brief Length for Ifx_DMA_CH_CHCSR_Bits.WRPD */
+#define IFX_DMA_CH_CHCSR_WRPD_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_CH_CHCSR_Bits.WRPD */
+#define IFX_DMA_CH_CHCSR_WRPD_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_CH_CHCSR_Bits.WRPD */
+#define IFX_DMA_CH_CHCSR_WRPD_OFF (17u)
+
+/** \brief Length for Ifx_DMA_CH_CHCSR_Bits.WRPS */
+#define IFX_DMA_CH_CHCSR_WRPS_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_CH_CHCSR_Bits.WRPS */
+#define IFX_DMA_CH_CHCSR_WRPS_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_CH_CHCSR_Bits.WRPS */
+#define IFX_DMA_CH_CHCSR_WRPS_OFF (16u)
+
+/** \brief Length for Ifx_DMA_CH_DADR_Bits.DADR */
+#define IFX_DMA_CH_DADR_DADR_LEN (32u)
+
+/** \brief Mask for Ifx_DMA_CH_DADR_Bits.DADR */
+#define IFX_DMA_CH_DADR_DADR_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_DMA_CH_DADR_Bits.DADR */
+#define IFX_DMA_CH_DADR_DADR_OFF (0u)
+
+/** \brief Length for Ifx_DMA_CH_RDCRCR_Bits.RDCRC */
+#define IFX_DMA_CH_RDCRCR_RDCRC_LEN (32u)
+
+/** \brief Mask for Ifx_DMA_CH_RDCRCR_Bits.RDCRC */
+#define IFX_DMA_CH_RDCRCR_RDCRC_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_DMA_CH_RDCRCR_Bits.RDCRC */
+#define IFX_DMA_CH_RDCRCR_RDCRC_OFF (0u)
+
+/** \brief Length for Ifx_DMA_CH_SADR_Bits.SADR */
+#define IFX_DMA_CH_SADR_SADR_LEN (32u)
+
+/** \brief Mask for Ifx_DMA_CH_SADR_Bits.SADR */
+#define IFX_DMA_CH_SADR_SADR_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_DMA_CH_SADR_Bits.SADR */
+#define IFX_DMA_CH_SADR_SADR_OFF (0u)
+
+/** \brief Length for Ifx_DMA_CH_SDCRCR_Bits.SDCRC */
+#define IFX_DMA_CH_SDCRCR_SDCRC_LEN (32u)
+
+/** \brief Mask for Ifx_DMA_CH_SDCRCR_Bits.SDCRC */
+#define IFX_DMA_CH_SDCRCR_SDCRC_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_DMA_CH_SDCRCR_Bits.SDCRC */
+#define IFX_DMA_CH_SDCRCR_SDCRC_OFF (0u)
+
+/** \brief Length for Ifx_DMA_CH_SHADR_Bits.SHADR */
+#define IFX_DMA_CH_SHADR_SHADR_LEN (32u)
+
+/** \brief Mask for Ifx_DMA_CH_SHADR_Bits.SHADR */
+#define IFX_DMA_CH_SHADR_SHADR_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_DMA_CH_SHADR_Bits.SHADR */
+#define IFX_DMA_CH_SHADR_SHADR_OFF (0u)
+
+/** \brief Length for Ifx_DMA_CLC_Bits.DISR */
+#define IFX_DMA_CLC_DISR_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_CLC_Bits.DISR */
+#define IFX_DMA_CLC_DISR_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_CLC_Bits.DISR */
+#define IFX_DMA_CLC_DISR_OFF (0u)
+
+/** \brief Length for Ifx_DMA_CLC_Bits.DISS */
+#define IFX_DMA_CLC_DISS_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_CLC_Bits.DISS */
+#define IFX_DMA_CLC_DISS_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_CLC_Bits.DISS */
+#define IFX_DMA_CLC_DISS_OFF (1u)
+
+/** \brief Length for Ifx_DMA_CLC_Bits.EDIS */
+#define IFX_DMA_CLC_EDIS_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_CLC_Bits.EDIS */
+#define IFX_DMA_CLC_EDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_CLC_Bits.EDIS */
+#define IFX_DMA_CLC_EDIS_OFF (3u)
+
+/** \brief Length for Ifx_DMA_ERRINTR_Bits.SIT */
+#define IFX_DMA_ERRINTR_SIT_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_ERRINTR_Bits.SIT */
+#define IFX_DMA_ERRINTR_SIT_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_ERRINTR_Bits.SIT */
+#define IFX_DMA_ERRINTR_SIT_OFF (0u)
+
+/** \brief Length for Ifx_DMA_HRR_Bits.HRP */
+#define IFX_DMA_HRR_HRP_LEN (2u)
+
+/** \brief Mask for Ifx_DMA_HRR_Bits.HRP */
+#define IFX_DMA_HRR_HRP_MSK (0x3u)
+
+/** \brief Offset for Ifx_DMA_HRR_Bits.HRP */
+#define IFX_DMA_HRR_HRP_OFF (0u)
+
+/** \brief Length for Ifx_DMA_ID_Bits.MODNUMBER */
+#define IFX_DMA_ID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_DMA_ID_Bits.MODNUMBER */
+#define IFX_DMA_ID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_DMA_ID_Bits.MODNUMBER */
+#define IFX_DMA_ID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_DMA_ID_Bits.MODREV */
+#define IFX_DMA_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_ID_Bits.MODREV */
+#define IFX_DMA_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_ID_Bits.MODREV */
+#define IFX_DMA_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_DMA_ID_Bits.MODTYPE */
+#define IFX_DMA_ID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_ID_Bits.MODTYPE */
+#define IFX_DMA_ID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_ID_Bits.MODTYPE */
+#define IFX_DMA_ID_MODTYPE_OFF (8u)
+
+/** \brief Length for Ifx_DMA_MEMCON_Bits.DATAERR */
+#define IFX_DMA_MEMCON_DATAERR_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_MEMCON_Bits.DATAERR */
+#define IFX_DMA_MEMCON_DATAERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_MEMCON_Bits.DATAERR */
+#define IFX_DMA_MEMCON_DATAERR_OFF (6u)
+
+/** \brief Length for Ifx_DMA_MEMCON_Bits.ERRDIS */
+#define IFX_DMA_MEMCON_ERRDIS_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_MEMCON_Bits.ERRDIS */
+#define IFX_DMA_MEMCON_ERRDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_MEMCON_Bits.ERRDIS */
+#define IFX_DMA_MEMCON_ERRDIS_OFF (9u)
+
+/** \brief Length for Ifx_DMA_MEMCON_Bits.INTERR */
+#define IFX_DMA_MEMCON_INTERR_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_MEMCON_Bits.INTERR */
+#define IFX_DMA_MEMCON_INTERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_MEMCON_Bits.INTERR */
+#define IFX_DMA_MEMCON_INTERR_OFF (2u)
+
+/** \brief Length for Ifx_DMA_MEMCON_Bits.PMIC */
+#define IFX_DMA_MEMCON_PMIC_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_MEMCON_Bits.PMIC */
+#define IFX_DMA_MEMCON_PMIC_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_MEMCON_Bits.PMIC */
+#define IFX_DMA_MEMCON_PMIC_OFF (8u)
+
+/** \brief Length for Ifx_DMA_MEMCON_Bits.RMWERR */
+#define IFX_DMA_MEMCON_RMWERR_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_MEMCON_Bits.RMWERR */
+#define IFX_DMA_MEMCON_RMWERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_MEMCON_Bits.RMWERR */
+#define IFX_DMA_MEMCON_RMWERR_OFF (4u)
+
+/** \brief Length for Ifx_DMA_MODE_Bits.MODE */
+#define IFX_DMA_MODE_MODE_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_MODE_Bits.MODE */
+#define IFX_DMA_MODE_MODE_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_MODE_Bits.MODE */
+#define IFX_DMA_MODE_MODE_OFF (0u)
+
+/** \brief Length for Ifx_DMA_OTSS_Bits.BS */
+#define IFX_DMA_OTSS_BS_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_OTSS_Bits.BS */
+#define IFX_DMA_OTSS_BS_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_OTSS_Bits.BS */
+#define IFX_DMA_OTSS_BS_OFF (7u)
+
+/** \brief Length for Ifx_DMA_OTSS_Bits.TGS */
+#define IFX_DMA_OTSS_TGS_LEN (4u)
+
+/** \brief Mask for Ifx_DMA_OTSS_Bits.TGS */
+#define IFX_DMA_OTSS_TGS_MSK (0xfu)
+
+/** \brief Offset for Ifx_DMA_OTSS_Bits.TGS */
+#define IFX_DMA_OTSS_TGS_OFF (0u)
+
+/** \brief Length for Ifx_DMA_PRR0_Bits.PAT00 */
+#define IFX_DMA_PRR0_PAT00_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_PRR0_Bits.PAT00 */
+#define IFX_DMA_PRR0_PAT00_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_PRR0_Bits.PAT00 */
+#define IFX_DMA_PRR0_PAT00_OFF (0u)
+
+/** \brief Length for Ifx_DMA_PRR0_Bits.PAT01 */
+#define IFX_DMA_PRR0_PAT01_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_PRR0_Bits.PAT01 */
+#define IFX_DMA_PRR0_PAT01_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_PRR0_Bits.PAT01 */
+#define IFX_DMA_PRR0_PAT01_OFF (8u)
+
+/** \brief Length for Ifx_DMA_PRR0_Bits.PAT02 */
+#define IFX_DMA_PRR0_PAT02_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_PRR0_Bits.PAT02 */
+#define IFX_DMA_PRR0_PAT02_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_PRR0_Bits.PAT02 */
+#define IFX_DMA_PRR0_PAT02_OFF (16u)
+
+/** \brief Length for Ifx_DMA_PRR0_Bits.PAT03 */
+#define IFX_DMA_PRR0_PAT03_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_PRR0_Bits.PAT03 */
+#define IFX_DMA_PRR0_PAT03_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_PRR0_Bits.PAT03 */
+#define IFX_DMA_PRR0_PAT03_OFF (24u)
+
+/** \brief Length for Ifx_DMA_PRR1_Bits.PAT10 */
+#define IFX_DMA_PRR1_PAT10_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_PRR1_Bits.PAT10 */
+#define IFX_DMA_PRR1_PAT10_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_PRR1_Bits.PAT10 */
+#define IFX_DMA_PRR1_PAT10_OFF (0u)
+
+/** \brief Length for Ifx_DMA_PRR1_Bits.PAT11 */
+#define IFX_DMA_PRR1_PAT11_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_PRR1_Bits.PAT11 */
+#define IFX_DMA_PRR1_PAT11_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_PRR1_Bits.PAT11 */
+#define IFX_DMA_PRR1_PAT11_OFF (8u)
+
+/** \brief Length for Ifx_DMA_PRR1_Bits.PAT12 */
+#define IFX_DMA_PRR1_PAT12_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_PRR1_Bits.PAT12 */
+#define IFX_DMA_PRR1_PAT12_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_PRR1_Bits.PAT12 */
+#define IFX_DMA_PRR1_PAT12_OFF (16u)
+
+/** \brief Length for Ifx_DMA_PRR1_Bits.PAT13 */
+#define IFX_DMA_PRR1_PAT13_LEN (8u)
+
+/** \brief Mask for Ifx_DMA_PRR1_Bits.PAT13 */
+#define IFX_DMA_PRR1_PAT13_MSK (0xffu)
+
+/** \brief Offset for Ifx_DMA_PRR1_Bits.PAT13 */
+#define IFX_DMA_PRR1_PAT13_OFF (24u)
+
+/** \brief Length for Ifx_DMA_SUSACR_Bits.SUSAC */
+#define IFX_DMA_SUSACR_SUSAC_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_SUSACR_Bits.SUSAC */
+#define IFX_DMA_SUSACR_SUSAC_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_SUSACR_Bits.SUSAC */
+#define IFX_DMA_SUSACR_SUSAC_OFF (0u)
+
+/** \brief Length for Ifx_DMA_SUSENR_Bits.SUSEN */
+#define IFX_DMA_SUSENR_SUSEN_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_SUSENR_Bits.SUSEN */
+#define IFX_DMA_SUSENR_SUSEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_SUSENR_Bits.SUSEN */
+#define IFX_DMA_SUSENR_SUSEN_OFF (0u)
+
+/** \brief Length for Ifx_DMA_TIME_Bits.COUNT */
+#define IFX_DMA_TIME_COUNT_LEN (32u)
+
+/** \brief Mask for Ifx_DMA_TIME_Bits.COUNT */
+#define IFX_DMA_TIME_COUNT_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_DMA_TIME_Bits.COUNT */
+#define IFX_DMA_TIME_COUNT_OFF (0u)
+
+/** \brief Length for Ifx_DMA_TSR_Bits.CH */
+#define IFX_DMA_TSR_CH_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_TSR_Bits.CH */
+#define IFX_DMA_TSR_CH_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_TSR_Bits.CH */
+#define IFX_DMA_TSR_CH_OFF (3u)
+
+/** \brief Length for Ifx_DMA_TSR_Bits.CTL */
+#define IFX_DMA_TSR_CTL_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_TSR_Bits.CTL */
+#define IFX_DMA_TSR_CTL_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_TSR_Bits.CTL */
+#define IFX_DMA_TSR_CTL_OFF (18u)
+
+/** \brief Length for Ifx_DMA_TSR_Bits.DCH */
+#define IFX_DMA_TSR_DCH_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_TSR_Bits.DCH */
+#define IFX_DMA_TSR_DCH_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_TSR_Bits.DCH */
+#define IFX_DMA_TSR_DCH_OFF (17u)
+
+/** \brief Length for Ifx_DMA_TSR_Bits.ECH */
+#define IFX_DMA_TSR_ECH_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_TSR_Bits.ECH */
+#define IFX_DMA_TSR_ECH_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_TSR_Bits.ECH */
+#define IFX_DMA_TSR_ECH_OFF (16u)
+
+/** \brief Length for Ifx_DMA_TSR_Bits.HLTACK */
+#define IFX_DMA_TSR_HLTACK_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_TSR_Bits.HLTACK */
+#define IFX_DMA_TSR_HLTACK_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_TSR_Bits.HLTACK */
+#define IFX_DMA_TSR_HLTACK_OFF (9u)
+
+/** \brief Length for Ifx_DMA_TSR_Bits.HLTCLR */
+#define IFX_DMA_TSR_HLTCLR_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_TSR_Bits.HLTCLR */
+#define IFX_DMA_TSR_HLTCLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_TSR_Bits.HLTCLR */
+#define IFX_DMA_TSR_HLTCLR_OFF (24u)
+
+/** \brief Length for Ifx_DMA_TSR_Bits.HLTREQ */
+#define IFX_DMA_TSR_HLTREQ_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_TSR_Bits.HLTREQ */
+#define IFX_DMA_TSR_HLTREQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_TSR_Bits.HLTREQ */
+#define IFX_DMA_TSR_HLTREQ_OFF (8u)
+
+/** \brief Length for Ifx_DMA_TSR_Bits.HTRE */
+#define IFX_DMA_TSR_HTRE_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_TSR_Bits.HTRE */
+#define IFX_DMA_TSR_HTRE_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_TSR_Bits.HTRE */
+#define IFX_DMA_TSR_HTRE_OFF (1u)
+
+/** \brief Length for Ifx_DMA_TSR_Bits.RST */
+#define IFX_DMA_TSR_RST_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_TSR_Bits.RST */
+#define IFX_DMA_TSR_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_TSR_Bits.RST */
+#define IFX_DMA_TSR_RST_OFF (0u)
+
+/** \brief Length for Ifx_DMA_TSR_Bits.TRL */
+#define IFX_DMA_TSR_TRL_LEN (1u)
+
+/** \brief Mask for Ifx_DMA_TSR_Bits.TRL */
+#define IFX_DMA_TSR_TRL_MSK (0x1u)
+
+/** \brief Offset for Ifx_DMA_TSR_Bits.TRL */
+#define IFX_DMA_TSR_TRL_OFF (2u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXDMA_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxDma_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxDma_reg.h
new file mode 100644
index 0000000..a403844
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxDma_reg.h
@@ -0,0 +1,5041 @@
+/**
+ * \file IfxDma_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Dma_Cfg Dma address
+ * \ingroup IfxLld_Dma
+ *
+ * \defgroup IfxLld_Dma_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Dma_Cfg
+ *
+ * \defgroup IfxLld_Dma_Cfg_Dma 2-DMA
+ * \ingroup IfxLld_Dma_Cfg
+ *
+ */
+#ifndef IFXDMA_REG_H
+#define IFXDMA_REG_H 1
+/******************************************************************************/
+#include "IfxDma_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Dma_Cfg_BaseAddress
+ * \{ */
+
+/** \brief DMA object */
+#define MODULE_DMA /*lint --e(923)*/ (*(Ifx_DMA*)0xF0010000u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Dma_Cfg_Dma
+ * \{ */
+
+/** \brief 40, DMA Hardware Resource 0 Access Enable Register 0 */
+#define DMA_ACCEN00 /*lint --e(923)*/ (*(volatile Ifx_DMA_ACCEN00*)0xF0010040u)
+
+/** \brief 44, DMA Hardware Resource 0 Access Enable Register 1 */
+#define DMA_ACCEN01 /*lint --e(923)*/ (*(volatile Ifx_DMA_ACCEN01*)0xF0010044u)
+
+/** \brief 48, DMA Hardware Resource 1 Access Enable Register 0 */
+#define DMA_ACCEN10 /*lint --e(923)*/ (*(volatile Ifx_DMA_ACCEN10*)0xF0010048u)
+
+/** \brief 4C, DMA Hardware Resource 1 Access Enable Register 1 */
+#define DMA_ACCEN11 /*lint --e(923)*/ (*(volatile Ifx_DMA_ACCEN11*)0xF001004Cu)
+
+/** \brief 50, DMA Hardware Resource 2 Access Enable Register 0 */
+#define DMA_ACCEN20 /*lint --e(923)*/ (*(volatile Ifx_DMA_ACCEN20*)0xF0010050u)
+
+/** \brief 54, DMA Hardware Resource 2 Access Enable Register 1 */
+#define DMA_ACCEN21 /*lint --e(923)*/ (*(volatile Ifx_DMA_ACCEN21*)0xF0010054u)
+
+/** \brief 58, DMA Hardware Resource 3 Access Enable Register 0 */
+#define DMA_ACCEN30 /*lint --e(923)*/ (*(volatile Ifx_DMA_ACCEN30*)0xF0010058u)
+
+/** \brief 5C, DMA Hardware Resource 3 Access Enable Register 1 */
+#define DMA_ACCEN31 /*lint --e(923)*/ (*(volatile Ifx_DMA_ACCEN31*)0xF001005Cu)
+
+/** \brief 128, DMA Clear Error Register */
+#define DMA_BLK0_CLRE /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_CLRE*)0xF0010128u)
+
+/** Alias (User Manual Name) for DMA_BLK0_CLRE.
+* To use register names with standard convension, please use DMA_BLK0_CLRE.
+*/
+#define DMA_CLRE0 (DMA_BLK0_CLRE)
+
+/** \brief 120, DMA Enable Error Register */
+#define DMA_BLK0_EER /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_EER*)0xF0010120u)
+
+/** Alias (User Manual Name) for DMA_BLK0_EER.
+* To use register names with standard convension, please use DMA_BLK0_EER.
+*/
+#define DMA_EER0 (DMA_BLK0_EER)
+
+/** \brief 124, DMA Error Status Register */
+#define DMA_BLK0_ERRSR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ERRSR*)0xF0010124u)
+
+/** Alias (User Manual Name) for DMA_BLK0_ERRSR.
+* To use register names with standard convension, please use DMA_BLK0_ERRSR.
+*/
+#define DMA_ERRSR0 (DMA_BLK0_ERRSR)
+
+/** \brief 190, DMA Move Engine Channel Address and Interrupt Control Register */
+#define DMA_BLK0_ME_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_ADICR*)0xF0010190u)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_ADICR.
+* To use register names with standard convension, please use DMA_BLK0_ME_ADICR.
+*/
+#define DMA_ME0ADICR (DMA_BLK0_ME_ADICR)
+
+/** \brief 194, DMA Move Engine Channel Control Register */
+#define DMA_BLK0_ME_CHCR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_CHCR*)0xF0010194u)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_CHCR.
+* To use register names with standard convension, please use DMA_BLK0_ME_CHCR.
+*/
+#define DMA_ME0CHCR (DMA_BLK0_ME_CHCR)
+
+/** \brief 19C, DMA Move Engine Channel Status Register */
+#define DMA_BLK0_ME_CHSR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_CHSR*)0xF001019Cu)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_CHSR.
+* To use register names with standard convension, please use DMA_BLK0_ME_CHSR.
+*/
+#define DMA_ME0CHSR (DMA_BLK0_ME_CHSR)
+
+/** \brief 18C, DMA Move Engine Channel Destination Address Register x */
+#define DMA_BLK0_ME_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_DADR*)0xF001018Cu)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_DADR.
+* To use register names with standard convension, please use DMA_BLK0_ME_DADR.
+*/
+#define DMA_ME0DADR (DMA_BLK0_ME_DADR)
+
+/** \brief 140, DMA Move Engine Read Register 0 */
+#define DMA_BLK0_ME_R0 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R0*)0xF0010140u)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_R0.
+* To use register names with standard convension, please use DMA_BLK0_ME_R0.
+*/
+#define DMA_ME00R (DMA_BLK0_ME_R0)
+
+/** \brief 144, DMA Move Engine Read Register 1 */
+#define DMA_BLK0_ME_R1 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R1*)0xF0010144u)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_R1.
+* To use register names with standard convension, please use DMA_BLK0_ME_R1.
+*/
+#define DMA_ME01R (DMA_BLK0_ME_R1)
+
+/** \brief 148, DMA Move Engine Read Register 2 */
+#define DMA_BLK0_ME_R2 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R2*)0xF0010148u)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_R2.
+* To use register names with standard convension, please use DMA_BLK0_ME_R2.
+*/
+#define DMA_ME02R (DMA_BLK0_ME_R2)
+
+/** \brief 14C, DMA Move Engine Read Register 3 */
+#define DMA_BLK0_ME_R3 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R3*)0xF001014Cu)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_R3.
+* To use register names with standard convension, please use DMA_BLK0_ME_R3.
+*/
+#define DMA_ME03R (DMA_BLK0_ME_R3)
+
+/** \brief 150, DMA Move Engine Read Register 4 */
+#define DMA_BLK0_ME_R4 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R4*)0xF0010150u)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_R4.
+* To use register names with standard convension, please use DMA_BLK0_ME_R4.
+*/
+#define DMA_ME04R (DMA_BLK0_ME_R4)
+
+/** \brief 154, DMA Move Engine Read Register 5 */
+#define DMA_BLK0_ME_R5 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R5*)0xF0010154u)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_R5.
+* To use register names with standard convension, please use DMA_BLK0_ME_R5.
+*/
+#define DMA_ME05R (DMA_BLK0_ME_R5)
+
+/** \brief 158, DMA Move Engine Read Register 6 */
+#define DMA_BLK0_ME_R6 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R6*)0xF0010158u)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_R6.
+* To use register names with standard convension, please use DMA_BLK0_ME_R6.
+*/
+#define DMA_ME06R (DMA_BLK0_ME_R6)
+
+/** \brief 15C, DMA Move Engine Read Register 7 */
+#define DMA_BLK0_ME_R7 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R7*)0xF001015Cu)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_R7.
+* To use register names with standard convension, please use DMA_BLK0_ME_R7.
+*/
+#define DMA_ME07R (DMA_BLK0_ME_R7)
+
+/** \brief 180, DMA Move Engine Channel Read Data CRC Register */
+#define DMA_BLK0_ME_RDCRC /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_RDCRC*)0xF0010180u)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_RDCRC.
+* To use register names with standard convension, please use DMA_BLK0_ME_RDCRC.
+*/
+#define DMA_ME0RDCRC (DMA_BLK0_ME_RDCRC)
+
+/** \brief 188, DMA Move Engine Channel Source Address Register */
+#define DMA_BLK0_ME_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_SADR*)0xF0010188u)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_SADR.
+* To use register names with standard convension, please use DMA_BLK0_ME_SADR.
+*/
+#define DMA_ME0SADR (DMA_BLK0_ME_SADR)
+
+/** \brief 184, DMA Move Engine Channel Source and Destination Address CRC
+ * Register */
+#define DMA_BLK0_ME_SDCRC /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_SDCRC*)0xF0010184u)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_SDCRC.
+* To use register names with standard convension, please use DMA_BLK0_ME_SDCRC.
+*/
+#define DMA_ME0SDCRC (DMA_BLK0_ME_SDCRC)
+
+/** \brief 198, DMA Move Engine Channel Shadow Address Register */
+#define DMA_BLK0_ME_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_SHADR*)0xF0010198u)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_SHADR.
+* To use register names with standard convension, please use DMA_BLK0_ME_SHADR.
+*/
+#define DMA_ME0SHADR (DMA_BLK0_ME_SHADR)
+
+/** \brief 130, DMA Move Engine Status Register */
+#define DMA_BLK0_ME_SR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_SR*)0xF0010130u)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_SR.
+* To use register names with standard convension, please use DMA_BLK0_ME_SR.
+*/
+#define DMA_ME0SR (DMA_BLK0_ME_SR)
+
+/** \brief 1128, DMA Clear Error Register */
+#define DMA_BLK1_CLRE /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_CLRE*)0xF0011128u)
+
+/** Alias (User Manual Name) for DMA_BLK1_CLRE.
+* To use register names with standard convension, please use DMA_BLK1_CLRE.
+*/
+#define DMA_CLRE1 (DMA_BLK1_CLRE)
+
+/** \brief 1120, DMA Enable Error Register */
+#define DMA_BLK1_EER /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_EER*)0xF0011120u)
+
+/** Alias (User Manual Name) for DMA_BLK1_EER.
+* To use register names with standard convension, please use DMA_BLK1_EER.
+*/
+#define DMA_EER1 (DMA_BLK1_EER)
+
+/** \brief 1124, DMA Error Status Register */
+#define DMA_BLK1_ERRSR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ERRSR*)0xF0011124u)
+
+/** Alias (User Manual Name) for DMA_BLK1_ERRSR.
+* To use register names with standard convension, please use DMA_BLK1_ERRSR.
+*/
+#define DMA_ERRSR1 (DMA_BLK1_ERRSR)
+
+/** \brief 1190, DMA Move Engine Channel Address and Interrupt Control Register */
+#define DMA_BLK1_ME_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_ADICR*)0xF0011190u)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_ADICR.
+* To use register names with standard convension, please use DMA_BLK1_ME_ADICR.
+*/
+#define DMA_ME1ADICR (DMA_BLK1_ME_ADICR)
+
+/** \brief 1194, DMA Move Engine Channel Control Register */
+#define DMA_BLK1_ME_CHCR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_CHCR*)0xF0011194u)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_CHCR.
+* To use register names with standard convension, please use DMA_BLK1_ME_CHCR.
+*/
+#define DMA_ME1CHCR (DMA_BLK1_ME_CHCR)
+
+/** \brief 119C, DMA Move Engine Channel Status Register */
+#define DMA_BLK1_ME_CHSR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_CHSR*)0xF001119Cu)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_CHSR.
+* To use register names with standard convension, please use DMA_BLK1_ME_CHSR.
+*/
+#define DMA_ME1CHSR (DMA_BLK1_ME_CHSR)
+
+/** \brief 118C, DMA Move Engine Channel Destination Address Register x */
+#define DMA_BLK1_ME_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_DADR*)0xF001118Cu)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_DADR.
+* To use register names with standard convension, please use DMA_BLK1_ME_DADR.
+*/
+#define DMA_ME1DADR (DMA_BLK1_ME_DADR)
+
+/** \brief 1140, DMA Move Engine Read Register 0 */
+#define DMA_BLK1_ME_R0 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R0*)0xF0011140u)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_R0.
+* To use register names with standard convension, please use DMA_BLK1_ME_R0.
+*/
+#define DMA_ME10R (DMA_BLK1_ME_R0)
+
+/** \brief 1144, DMA Move Engine Read Register 1 */
+#define DMA_BLK1_ME_R1 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R1*)0xF0011144u)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_R1.
+* To use register names with standard convension, please use DMA_BLK1_ME_R1.
+*/
+#define DMA_ME11R (DMA_BLK1_ME_R1)
+
+/** \brief 1148, DMA Move Engine Read Register 2 */
+#define DMA_BLK1_ME_R2 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R2*)0xF0011148u)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_R2.
+* To use register names with standard convension, please use DMA_BLK1_ME_R2.
+*/
+#define DMA_ME12R (DMA_BLK1_ME_R2)
+
+/** \brief 114C, DMA Move Engine Read Register 3 */
+#define DMA_BLK1_ME_R3 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R3*)0xF001114Cu)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_R3.
+* To use register names with standard convension, please use DMA_BLK1_ME_R3.
+*/
+#define DMA_ME13R (DMA_BLK1_ME_R3)
+
+/** \brief 1150, DMA Move Engine Read Register 4 */
+#define DMA_BLK1_ME_R4 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R4*)0xF0011150u)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_R4.
+* To use register names with standard convension, please use DMA_BLK1_ME_R4.
+*/
+#define DMA_ME14R (DMA_BLK1_ME_R4)
+
+/** \brief 1154, DMA Move Engine Read Register 5 */
+#define DMA_BLK1_ME_R5 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R5*)0xF0011154u)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_R5.
+* To use register names with standard convension, please use DMA_BLK1_ME_R5.
+*/
+#define DMA_ME15R (DMA_BLK1_ME_R5)
+
+/** \brief 1158, DMA Move Engine Read Register 6 */
+#define DMA_BLK1_ME_R6 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R6*)0xF0011158u)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_R6.
+* To use register names with standard convension, please use DMA_BLK1_ME_R6.
+*/
+#define DMA_ME16R (DMA_BLK1_ME_R6)
+
+/** \brief 115C, DMA Move Engine Read Register 7 */
+#define DMA_BLK1_ME_R7 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R7*)0xF001115Cu)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_R7.
+* To use register names with standard convension, please use DMA_BLK1_ME_R7.
+*/
+#define DMA_ME17R (DMA_BLK1_ME_R7)
+
+/** \brief 1180, DMA Move Engine Channel Read Data CRC Register */
+#define DMA_BLK1_ME_RDCRC /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_RDCRC*)0xF0011180u)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_RDCRC.
+* To use register names with standard convension, please use DMA_BLK1_ME_RDCRC.
+*/
+#define DMA_ME1RDCRC (DMA_BLK1_ME_RDCRC)
+
+/** \brief 1188, DMA Move Engine Channel Source Address Register */
+#define DMA_BLK1_ME_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_SADR*)0xF0011188u)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_SADR.
+* To use register names with standard convension, please use DMA_BLK1_ME_SADR.
+*/
+#define DMA_ME1SADR (DMA_BLK1_ME_SADR)
+
+/** \brief 1184, DMA Move Engine Channel Source and Destination Address CRC
+ * Register */
+#define DMA_BLK1_ME_SDCRC /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_SDCRC*)0xF0011184u)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_SDCRC.
+* To use register names with standard convension, please use DMA_BLK1_ME_SDCRC.
+*/
+#define DMA_ME1SDCRC (DMA_BLK1_ME_SDCRC)
+
+/** \brief 1198, DMA Move Engine Channel Shadow Address Register */
+#define DMA_BLK1_ME_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_SHADR*)0xF0011198u)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_SHADR.
+* To use register names with standard convension, please use DMA_BLK1_ME_SHADR.
+*/
+#define DMA_ME1SHADR (DMA_BLK1_ME_SHADR)
+
+/** \brief 1130, DMA Move Engine Status Register */
+#define DMA_BLK1_ME_SR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_SR*)0xF0011130u)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_SR.
+* To use register names with standard convension, please use DMA_BLK1_ME_SR.
+*/
+#define DMA_ME1SR (DMA_BLK1_ME_SR)
+
+/** \brief 2010, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH0_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012010u)
+
+/** Alias (User Manual Name) for DMA_CH0_ADICR.
+* To use register names with standard convension, please use DMA_CH0_ADICR.
+*/
+#define DMA_ADICR000 (DMA_CH0_ADICR)
+
+/** \brief 2014, DMA Channel Configuration Register */
+#define DMA_CH0_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012014u)
+
+/** Alias (User Manual Name) for DMA_CH0_CHCFGR.
+* To use register names with standard convension, please use DMA_CH0_CHCFGR.
+*/
+#define DMA_CHCFGR000 (DMA_CH0_CHCFGR)
+
+/** \brief 201C, DMARAM Channel Control and Status Register */
+#define DMA_CH0_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001201Cu)
+
+/** Alias (User Manual Name) for DMA_CH0_CHCSR.
+* To use register names with standard convension, please use DMA_CH0_CHCSR.
+*/
+#define DMA_CHCSR000 (DMA_CH0_CHCSR)
+
+/** \brief 200C, DMA Channel Destination Address Register x */
+#define DMA_CH0_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001200Cu)
+
+/** Alias (User Manual Name) for DMA_CH0_DADR.
+* To use register names with standard convension, please use DMA_CH0_DADR.
+*/
+#define DMA_DADR000 (DMA_CH0_DADR)
+
+/** \brief 2000, DMA Channel Read Data CRC Register */
+#define DMA_CH0_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012000u)
+
+/** Alias (User Manual Name) for DMA_CH0_RDCRCR.
+* To use register names with standard convension, please use DMA_CH0_RDCRCR.
+*/
+#define DMA_RDCRCR000 (DMA_CH0_RDCRCR)
+
+/** \brief 2008, DMA Channel Source Address Register */
+#define DMA_CH0_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012008u)
+
+/** Alias (User Manual Name) for DMA_CH0_SADR.
+* To use register names with standard convension, please use DMA_CH0_SADR.
+*/
+#define DMA_SADR000 (DMA_CH0_SADR)
+
+/** \brief 2004, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH0_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012004u)
+
+/** Alias (User Manual Name) for DMA_CH0_SDCRCR.
+* To use register names with standard convension, please use DMA_CH0_SDCRCR.
+*/
+#define DMA_SDCRCR000 (DMA_CH0_SDCRCR)
+
+/** \brief 2018, DMA Channel Shadow Address Register */
+#define DMA_CH0_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012018u)
+
+/** Alias (User Manual Name) for DMA_CH0_SHADR.
+* To use register names with standard convension, please use DMA_CH0_SHADR.
+*/
+#define DMA_SHADR000 (DMA_CH0_SHADR)
+
+/** \brief 2150, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH10_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012150u)
+
+/** Alias (User Manual Name) for DMA_CH10_ADICR.
+* To use register names with standard convension, please use DMA_CH10_ADICR.
+*/
+#define DMA_ADICR010 (DMA_CH10_ADICR)
+
+/** \brief 2154, DMA Channel Configuration Register */
+#define DMA_CH10_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012154u)
+
+/** Alias (User Manual Name) for DMA_CH10_CHCFGR.
+* To use register names with standard convension, please use DMA_CH10_CHCFGR.
+*/
+#define DMA_CHCFGR010 (DMA_CH10_CHCFGR)
+
+/** \brief 215C, DMARAM Channel Control and Status Register */
+#define DMA_CH10_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001215Cu)
+
+/** Alias (User Manual Name) for DMA_CH10_CHCSR.
+* To use register names with standard convension, please use DMA_CH10_CHCSR.
+*/
+#define DMA_CHCSR010 (DMA_CH10_CHCSR)
+
+/** \brief 214C, DMA Channel Destination Address Register x */
+#define DMA_CH10_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001214Cu)
+
+/** Alias (User Manual Name) for DMA_CH10_DADR.
+* To use register names with standard convension, please use DMA_CH10_DADR.
+*/
+#define DMA_DADR010 (DMA_CH10_DADR)
+
+/** \brief 2140, DMA Channel Read Data CRC Register */
+#define DMA_CH10_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012140u)
+
+/** Alias (User Manual Name) for DMA_CH10_RDCRCR.
+* To use register names with standard convension, please use DMA_CH10_RDCRCR.
+*/
+#define DMA_RDCRCR010 (DMA_CH10_RDCRCR)
+
+/** \brief 2148, DMA Channel Source Address Register */
+#define DMA_CH10_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012148u)
+
+/** Alias (User Manual Name) for DMA_CH10_SADR.
+* To use register names with standard convension, please use DMA_CH10_SADR.
+*/
+#define DMA_SADR010 (DMA_CH10_SADR)
+
+/** \brief 2144, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH10_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012144u)
+
+/** Alias (User Manual Name) for DMA_CH10_SDCRCR.
+* To use register names with standard convension, please use DMA_CH10_SDCRCR.
+*/
+#define DMA_SDCRCR010 (DMA_CH10_SDCRCR)
+
+/** \brief 2158, DMA Channel Shadow Address Register */
+#define DMA_CH10_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012158u)
+
+/** Alias (User Manual Name) for DMA_CH10_SHADR.
+* To use register names with standard convension, please use DMA_CH10_SHADR.
+*/
+#define DMA_SHADR010 (DMA_CH10_SHADR)
+
+/** \brief 2170, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH11_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012170u)
+
+/** Alias (User Manual Name) for DMA_CH11_ADICR.
+* To use register names with standard convension, please use DMA_CH11_ADICR.
+*/
+#define DMA_ADICR011 (DMA_CH11_ADICR)
+
+/** \brief 2174, DMA Channel Configuration Register */
+#define DMA_CH11_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012174u)
+
+/** Alias (User Manual Name) for DMA_CH11_CHCFGR.
+* To use register names with standard convension, please use DMA_CH11_CHCFGR.
+*/
+#define DMA_CHCFGR011 (DMA_CH11_CHCFGR)
+
+/** \brief 217C, DMARAM Channel Control and Status Register */
+#define DMA_CH11_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001217Cu)
+
+/** Alias (User Manual Name) for DMA_CH11_CHCSR.
+* To use register names with standard convension, please use DMA_CH11_CHCSR.
+*/
+#define DMA_CHCSR011 (DMA_CH11_CHCSR)
+
+/** \brief 216C, DMA Channel Destination Address Register x */
+#define DMA_CH11_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001216Cu)
+
+/** Alias (User Manual Name) for DMA_CH11_DADR.
+* To use register names with standard convension, please use DMA_CH11_DADR.
+*/
+#define DMA_DADR011 (DMA_CH11_DADR)
+
+/** \brief 2160, DMA Channel Read Data CRC Register */
+#define DMA_CH11_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012160u)
+
+/** Alias (User Manual Name) for DMA_CH11_RDCRCR.
+* To use register names with standard convension, please use DMA_CH11_RDCRCR.
+*/
+#define DMA_RDCRCR011 (DMA_CH11_RDCRCR)
+
+/** \brief 2168, DMA Channel Source Address Register */
+#define DMA_CH11_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012168u)
+
+/** Alias (User Manual Name) for DMA_CH11_SADR.
+* To use register names with standard convension, please use DMA_CH11_SADR.
+*/
+#define DMA_SADR011 (DMA_CH11_SADR)
+
+/** \brief 2164, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH11_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012164u)
+
+/** Alias (User Manual Name) for DMA_CH11_SDCRCR.
+* To use register names with standard convension, please use DMA_CH11_SDCRCR.
+*/
+#define DMA_SDCRCR011 (DMA_CH11_SDCRCR)
+
+/** \brief 2178, DMA Channel Shadow Address Register */
+#define DMA_CH11_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012178u)
+
+/** Alias (User Manual Name) for DMA_CH11_SHADR.
+* To use register names with standard convension, please use DMA_CH11_SHADR.
+*/
+#define DMA_SHADR011 (DMA_CH11_SHADR)
+
+/** \brief 2190, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH12_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012190u)
+
+/** Alias (User Manual Name) for DMA_CH12_ADICR.
+* To use register names with standard convension, please use DMA_CH12_ADICR.
+*/
+#define DMA_ADICR012 (DMA_CH12_ADICR)
+
+/** \brief 2194, DMA Channel Configuration Register */
+#define DMA_CH12_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012194u)
+
+/** Alias (User Manual Name) for DMA_CH12_CHCFGR.
+* To use register names with standard convension, please use DMA_CH12_CHCFGR.
+*/
+#define DMA_CHCFGR012 (DMA_CH12_CHCFGR)
+
+/** \brief 219C, DMARAM Channel Control and Status Register */
+#define DMA_CH12_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001219Cu)
+
+/** Alias (User Manual Name) for DMA_CH12_CHCSR.
+* To use register names with standard convension, please use DMA_CH12_CHCSR.
+*/
+#define DMA_CHCSR012 (DMA_CH12_CHCSR)
+
+/** \brief 218C, DMA Channel Destination Address Register x */
+#define DMA_CH12_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001218Cu)
+
+/** Alias (User Manual Name) for DMA_CH12_DADR.
+* To use register names with standard convension, please use DMA_CH12_DADR.
+*/
+#define DMA_DADR012 (DMA_CH12_DADR)
+
+/** \brief 2180, DMA Channel Read Data CRC Register */
+#define DMA_CH12_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012180u)
+
+/** Alias (User Manual Name) for DMA_CH12_RDCRCR.
+* To use register names with standard convension, please use DMA_CH12_RDCRCR.
+*/
+#define DMA_RDCRCR012 (DMA_CH12_RDCRCR)
+
+/** \brief 2188, DMA Channel Source Address Register */
+#define DMA_CH12_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012188u)
+
+/** Alias (User Manual Name) for DMA_CH12_SADR.
+* To use register names with standard convension, please use DMA_CH12_SADR.
+*/
+#define DMA_SADR012 (DMA_CH12_SADR)
+
+/** \brief 2184, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH12_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012184u)
+
+/** Alias (User Manual Name) for DMA_CH12_SDCRCR.
+* To use register names with standard convension, please use DMA_CH12_SDCRCR.
+*/
+#define DMA_SDCRCR012 (DMA_CH12_SDCRCR)
+
+/** \brief 2198, DMA Channel Shadow Address Register */
+#define DMA_CH12_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012198u)
+
+/** Alias (User Manual Name) for DMA_CH12_SHADR.
+* To use register names with standard convension, please use DMA_CH12_SHADR.
+*/
+#define DMA_SHADR012 (DMA_CH12_SHADR)
+
+/** \brief 21B0, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH13_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF00121B0u)
+
+/** Alias (User Manual Name) for DMA_CH13_ADICR.
+* To use register names with standard convension, please use DMA_CH13_ADICR.
+*/
+#define DMA_ADICR013 (DMA_CH13_ADICR)
+
+/** \brief 21B4, DMA Channel Configuration Register */
+#define DMA_CH13_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF00121B4u)
+
+/** Alias (User Manual Name) for DMA_CH13_CHCFGR.
+* To use register names with standard convension, please use DMA_CH13_CHCFGR.
+*/
+#define DMA_CHCFGR013 (DMA_CH13_CHCFGR)
+
+/** \brief 21BC, DMARAM Channel Control and Status Register */
+#define DMA_CH13_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF00121BCu)
+
+/** Alias (User Manual Name) for DMA_CH13_CHCSR.
+* To use register names with standard convension, please use DMA_CH13_CHCSR.
+*/
+#define DMA_CHCSR013 (DMA_CH13_CHCSR)
+
+/** \brief 21AC, DMA Channel Destination Address Register x */
+#define DMA_CH13_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF00121ACu)
+
+/** Alias (User Manual Name) for DMA_CH13_DADR.
+* To use register names with standard convension, please use DMA_CH13_DADR.
+*/
+#define DMA_DADR013 (DMA_CH13_DADR)
+
+/** \brief 21A0, DMA Channel Read Data CRC Register */
+#define DMA_CH13_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF00121A0u)
+
+/** Alias (User Manual Name) for DMA_CH13_RDCRCR.
+* To use register names with standard convension, please use DMA_CH13_RDCRCR.
+*/
+#define DMA_RDCRCR013 (DMA_CH13_RDCRCR)
+
+/** \brief 21A8, DMA Channel Source Address Register */
+#define DMA_CH13_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF00121A8u)
+
+/** Alias (User Manual Name) for DMA_CH13_SADR.
+* To use register names with standard convension, please use DMA_CH13_SADR.
+*/
+#define DMA_SADR013 (DMA_CH13_SADR)
+
+/** \brief 21A4, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH13_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF00121A4u)
+
+/** Alias (User Manual Name) for DMA_CH13_SDCRCR.
+* To use register names with standard convension, please use DMA_CH13_SDCRCR.
+*/
+#define DMA_SDCRCR013 (DMA_CH13_SDCRCR)
+
+/** \brief 21B8, DMA Channel Shadow Address Register */
+#define DMA_CH13_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF00121B8u)
+
+/** Alias (User Manual Name) for DMA_CH13_SHADR.
+* To use register names with standard convension, please use DMA_CH13_SHADR.
+*/
+#define DMA_SHADR013 (DMA_CH13_SHADR)
+
+/** \brief 21D0, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH14_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF00121D0u)
+
+/** Alias (User Manual Name) for DMA_CH14_ADICR.
+* To use register names with standard convension, please use DMA_CH14_ADICR.
+*/
+#define DMA_ADICR014 (DMA_CH14_ADICR)
+
+/** \brief 21D4, DMA Channel Configuration Register */
+#define DMA_CH14_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF00121D4u)
+
+/** Alias (User Manual Name) for DMA_CH14_CHCFGR.
+* To use register names with standard convension, please use DMA_CH14_CHCFGR.
+*/
+#define DMA_CHCFGR014 (DMA_CH14_CHCFGR)
+
+/** \brief 21DC, DMARAM Channel Control and Status Register */
+#define DMA_CH14_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF00121DCu)
+
+/** Alias (User Manual Name) for DMA_CH14_CHCSR.
+* To use register names with standard convension, please use DMA_CH14_CHCSR.
+*/
+#define DMA_CHCSR014 (DMA_CH14_CHCSR)
+
+/** \brief 21CC, DMA Channel Destination Address Register x */
+#define DMA_CH14_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF00121CCu)
+
+/** Alias (User Manual Name) for DMA_CH14_DADR.
+* To use register names with standard convension, please use DMA_CH14_DADR.
+*/
+#define DMA_DADR014 (DMA_CH14_DADR)
+
+/** \brief 21C0, DMA Channel Read Data CRC Register */
+#define DMA_CH14_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF00121C0u)
+
+/** Alias (User Manual Name) for DMA_CH14_RDCRCR.
+* To use register names with standard convension, please use DMA_CH14_RDCRCR.
+*/
+#define DMA_RDCRCR014 (DMA_CH14_RDCRCR)
+
+/** \brief 21C8, DMA Channel Source Address Register */
+#define DMA_CH14_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF00121C8u)
+
+/** Alias (User Manual Name) for DMA_CH14_SADR.
+* To use register names with standard convension, please use DMA_CH14_SADR.
+*/
+#define DMA_SADR014 (DMA_CH14_SADR)
+
+/** \brief 21C4, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH14_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF00121C4u)
+
+/** Alias (User Manual Name) for DMA_CH14_SDCRCR.
+* To use register names with standard convension, please use DMA_CH14_SDCRCR.
+*/
+#define DMA_SDCRCR014 (DMA_CH14_SDCRCR)
+
+/** \brief 21D8, DMA Channel Shadow Address Register */
+#define DMA_CH14_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF00121D8u)
+
+/** Alias (User Manual Name) for DMA_CH14_SHADR.
+* To use register names with standard convension, please use DMA_CH14_SHADR.
+*/
+#define DMA_SHADR014 (DMA_CH14_SHADR)
+
+/** \brief 21F0, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH15_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF00121F0u)
+
+/** Alias (User Manual Name) for DMA_CH15_ADICR.
+* To use register names with standard convension, please use DMA_CH15_ADICR.
+*/
+#define DMA_ADICR015 (DMA_CH15_ADICR)
+
+/** \brief 21F4, DMA Channel Configuration Register */
+#define DMA_CH15_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF00121F4u)
+
+/** Alias (User Manual Name) for DMA_CH15_CHCFGR.
+* To use register names with standard convension, please use DMA_CH15_CHCFGR.
+*/
+#define DMA_CHCFGR015 (DMA_CH15_CHCFGR)
+
+/** \brief 21FC, DMARAM Channel Control and Status Register */
+#define DMA_CH15_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF00121FCu)
+
+/** Alias (User Manual Name) for DMA_CH15_CHCSR.
+* To use register names with standard convension, please use DMA_CH15_CHCSR.
+*/
+#define DMA_CHCSR015 (DMA_CH15_CHCSR)
+
+/** \brief 21EC, DMA Channel Destination Address Register x */
+#define DMA_CH15_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF00121ECu)
+
+/** Alias (User Manual Name) for DMA_CH15_DADR.
+* To use register names with standard convension, please use DMA_CH15_DADR.
+*/
+#define DMA_DADR015 (DMA_CH15_DADR)
+
+/** \brief 21E0, DMA Channel Read Data CRC Register */
+#define DMA_CH15_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF00121E0u)
+
+/** Alias (User Manual Name) for DMA_CH15_RDCRCR.
+* To use register names with standard convension, please use DMA_CH15_RDCRCR.
+*/
+#define DMA_RDCRCR015 (DMA_CH15_RDCRCR)
+
+/** \brief 21E8, DMA Channel Source Address Register */
+#define DMA_CH15_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF00121E8u)
+
+/** Alias (User Manual Name) for DMA_CH15_SADR.
+* To use register names with standard convension, please use DMA_CH15_SADR.
+*/
+#define DMA_SADR015 (DMA_CH15_SADR)
+
+/** \brief 21E4, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH15_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF00121E4u)
+
+/** Alias (User Manual Name) for DMA_CH15_SDCRCR.
+* To use register names with standard convension, please use DMA_CH15_SDCRCR.
+*/
+#define DMA_SDCRCR015 (DMA_CH15_SDCRCR)
+
+/** \brief 21F8, DMA Channel Shadow Address Register */
+#define DMA_CH15_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF00121F8u)
+
+/** Alias (User Manual Name) for DMA_CH15_SHADR.
+* To use register names with standard convension, please use DMA_CH15_SHADR.
+*/
+#define DMA_SHADR015 (DMA_CH15_SHADR)
+
+/** \brief 2210, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH16_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012210u)
+
+/** Alias (User Manual Name) for DMA_CH16_ADICR.
+* To use register names with standard convension, please use DMA_CH16_ADICR.
+*/
+#define DMA_ADICR016 (DMA_CH16_ADICR)
+
+/** \brief 2214, DMA Channel Configuration Register */
+#define DMA_CH16_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012214u)
+
+/** Alias (User Manual Name) for DMA_CH16_CHCFGR.
+* To use register names with standard convension, please use DMA_CH16_CHCFGR.
+*/
+#define DMA_CHCFGR016 (DMA_CH16_CHCFGR)
+
+/** \brief 221C, DMARAM Channel Control and Status Register */
+#define DMA_CH16_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001221Cu)
+
+/** Alias (User Manual Name) for DMA_CH16_CHCSR.
+* To use register names with standard convension, please use DMA_CH16_CHCSR.
+*/
+#define DMA_CHCSR016 (DMA_CH16_CHCSR)
+
+/** \brief 220C, DMA Channel Destination Address Register x */
+#define DMA_CH16_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001220Cu)
+
+/** Alias (User Manual Name) for DMA_CH16_DADR.
+* To use register names with standard convension, please use DMA_CH16_DADR.
+*/
+#define DMA_DADR016 (DMA_CH16_DADR)
+
+/** \brief 2200, DMA Channel Read Data CRC Register */
+#define DMA_CH16_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012200u)
+
+/** Alias (User Manual Name) for DMA_CH16_RDCRCR.
+* To use register names with standard convension, please use DMA_CH16_RDCRCR.
+*/
+#define DMA_RDCRCR016 (DMA_CH16_RDCRCR)
+
+/** \brief 2208, DMA Channel Source Address Register */
+#define DMA_CH16_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012208u)
+
+/** Alias (User Manual Name) for DMA_CH16_SADR.
+* To use register names with standard convension, please use DMA_CH16_SADR.
+*/
+#define DMA_SADR016 (DMA_CH16_SADR)
+
+/** \brief 2204, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH16_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012204u)
+
+/** Alias (User Manual Name) for DMA_CH16_SDCRCR.
+* To use register names with standard convension, please use DMA_CH16_SDCRCR.
+*/
+#define DMA_SDCRCR016 (DMA_CH16_SDCRCR)
+
+/** \brief 2218, DMA Channel Shadow Address Register */
+#define DMA_CH16_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012218u)
+
+/** Alias (User Manual Name) for DMA_CH16_SHADR.
+* To use register names with standard convension, please use DMA_CH16_SHADR.
+*/
+#define DMA_SHADR016 (DMA_CH16_SHADR)
+
+/** \brief 2230, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH17_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012230u)
+
+/** Alias (User Manual Name) for DMA_CH17_ADICR.
+* To use register names with standard convension, please use DMA_CH17_ADICR.
+*/
+#define DMA_ADICR017 (DMA_CH17_ADICR)
+
+/** \brief 2234, DMA Channel Configuration Register */
+#define DMA_CH17_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012234u)
+
+/** Alias (User Manual Name) for DMA_CH17_CHCFGR.
+* To use register names with standard convension, please use DMA_CH17_CHCFGR.
+*/
+#define DMA_CHCFGR017 (DMA_CH17_CHCFGR)
+
+/** \brief 223C, DMARAM Channel Control and Status Register */
+#define DMA_CH17_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001223Cu)
+
+/** Alias (User Manual Name) for DMA_CH17_CHCSR.
+* To use register names with standard convension, please use DMA_CH17_CHCSR.
+*/
+#define DMA_CHCSR017 (DMA_CH17_CHCSR)
+
+/** \brief 222C, DMA Channel Destination Address Register x */
+#define DMA_CH17_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001222Cu)
+
+/** Alias (User Manual Name) for DMA_CH17_DADR.
+* To use register names with standard convension, please use DMA_CH17_DADR.
+*/
+#define DMA_DADR017 (DMA_CH17_DADR)
+
+/** \brief 2220, DMA Channel Read Data CRC Register */
+#define DMA_CH17_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012220u)
+
+/** Alias (User Manual Name) for DMA_CH17_RDCRCR.
+* To use register names with standard convension, please use DMA_CH17_RDCRCR.
+*/
+#define DMA_RDCRCR017 (DMA_CH17_RDCRCR)
+
+/** \brief 2228, DMA Channel Source Address Register */
+#define DMA_CH17_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012228u)
+
+/** Alias (User Manual Name) for DMA_CH17_SADR.
+* To use register names with standard convension, please use DMA_CH17_SADR.
+*/
+#define DMA_SADR017 (DMA_CH17_SADR)
+
+/** \brief 2224, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH17_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012224u)
+
+/** Alias (User Manual Name) for DMA_CH17_SDCRCR.
+* To use register names with standard convension, please use DMA_CH17_SDCRCR.
+*/
+#define DMA_SDCRCR017 (DMA_CH17_SDCRCR)
+
+/** \brief 2238, DMA Channel Shadow Address Register */
+#define DMA_CH17_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012238u)
+
+/** Alias (User Manual Name) for DMA_CH17_SHADR.
+* To use register names with standard convension, please use DMA_CH17_SHADR.
+*/
+#define DMA_SHADR017 (DMA_CH17_SHADR)
+
+/** \brief 2250, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH18_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012250u)
+
+/** Alias (User Manual Name) for DMA_CH18_ADICR.
+* To use register names with standard convension, please use DMA_CH18_ADICR.
+*/
+#define DMA_ADICR018 (DMA_CH18_ADICR)
+
+/** \brief 2254, DMA Channel Configuration Register */
+#define DMA_CH18_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012254u)
+
+/** Alias (User Manual Name) for DMA_CH18_CHCFGR.
+* To use register names with standard convension, please use DMA_CH18_CHCFGR.
+*/
+#define DMA_CHCFGR018 (DMA_CH18_CHCFGR)
+
+/** \brief 225C, DMARAM Channel Control and Status Register */
+#define DMA_CH18_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001225Cu)
+
+/** Alias (User Manual Name) for DMA_CH18_CHCSR.
+* To use register names with standard convension, please use DMA_CH18_CHCSR.
+*/
+#define DMA_CHCSR018 (DMA_CH18_CHCSR)
+
+/** \brief 224C, DMA Channel Destination Address Register x */
+#define DMA_CH18_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001224Cu)
+
+/** Alias (User Manual Name) for DMA_CH18_DADR.
+* To use register names with standard convension, please use DMA_CH18_DADR.
+*/
+#define DMA_DADR018 (DMA_CH18_DADR)
+
+/** \brief 2240, DMA Channel Read Data CRC Register */
+#define DMA_CH18_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012240u)
+
+/** Alias (User Manual Name) for DMA_CH18_RDCRCR.
+* To use register names with standard convension, please use DMA_CH18_RDCRCR.
+*/
+#define DMA_RDCRCR018 (DMA_CH18_RDCRCR)
+
+/** \brief 2248, DMA Channel Source Address Register */
+#define DMA_CH18_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012248u)
+
+/** Alias (User Manual Name) for DMA_CH18_SADR.
+* To use register names with standard convension, please use DMA_CH18_SADR.
+*/
+#define DMA_SADR018 (DMA_CH18_SADR)
+
+/** \brief 2244, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH18_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012244u)
+
+/** Alias (User Manual Name) for DMA_CH18_SDCRCR.
+* To use register names with standard convension, please use DMA_CH18_SDCRCR.
+*/
+#define DMA_SDCRCR018 (DMA_CH18_SDCRCR)
+
+/** \brief 2258, DMA Channel Shadow Address Register */
+#define DMA_CH18_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012258u)
+
+/** Alias (User Manual Name) for DMA_CH18_SHADR.
+* To use register names with standard convension, please use DMA_CH18_SHADR.
+*/
+#define DMA_SHADR018 (DMA_CH18_SHADR)
+
+/** \brief 2270, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH19_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012270u)
+
+/** Alias (User Manual Name) for DMA_CH19_ADICR.
+* To use register names with standard convension, please use DMA_CH19_ADICR.
+*/
+#define DMA_ADICR019 (DMA_CH19_ADICR)
+
+/** \brief 2274, DMA Channel Configuration Register */
+#define DMA_CH19_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012274u)
+
+/** Alias (User Manual Name) for DMA_CH19_CHCFGR.
+* To use register names with standard convension, please use DMA_CH19_CHCFGR.
+*/
+#define DMA_CHCFGR019 (DMA_CH19_CHCFGR)
+
+/** \brief 227C, DMARAM Channel Control and Status Register */
+#define DMA_CH19_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001227Cu)
+
+/** Alias (User Manual Name) for DMA_CH19_CHCSR.
+* To use register names with standard convension, please use DMA_CH19_CHCSR.
+*/
+#define DMA_CHCSR019 (DMA_CH19_CHCSR)
+
+/** \brief 226C, DMA Channel Destination Address Register x */
+#define DMA_CH19_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001226Cu)
+
+/** Alias (User Manual Name) for DMA_CH19_DADR.
+* To use register names with standard convension, please use DMA_CH19_DADR.
+*/
+#define DMA_DADR019 (DMA_CH19_DADR)
+
+/** \brief 2260, DMA Channel Read Data CRC Register */
+#define DMA_CH19_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012260u)
+
+/** Alias (User Manual Name) for DMA_CH19_RDCRCR.
+* To use register names with standard convension, please use DMA_CH19_RDCRCR.
+*/
+#define DMA_RDCRCR019 (DMA_CH19_RDCRCR)
+
+/** \brief 2268, DMA Channel Source Address Register */
+#define DMA_CH19_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012268u)
+
+/** Alias (User Manual Name) for DMA_CH19_SADR.
+* To use register names with standard convension, please use DMA_CH19_SADR.
+*/
+#define DMA_SADR019 (DMA_CH19_SADR)
+
+/** \brief 2264, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH19_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012264u)
+
+/** Alias (User Manual Name) for DMA_CH19_SDCRCR.
+* To use register names with standard convension, please use DMA_CH19_SDCRCR.
+*/
+#define DMA_SDCRCR019 (DMA_CH19_SDCRCR)
+
+/** \brief 2278, DMA Channel Shadow Address Register */
+#define DMA_CH19_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012278u)
+
+/** Alias (User Manual Name) for DMA_CH19_SHADR.
+* To use register names with standard convension, please use DMA_CH19_SHADR.
+*/
+#define DMA_SHADR019 (DMA_CH19_SHADR)
+
+/** \brief 2030, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH1_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012030u)
+
+/** Alias (User Manual Name) for DMA_CH1_ADICR.
+* To use register names with standard convension, please use DMA_CH1_ADICR.
+*/
+#define DMA_ADICR001 (DMA_CH1_ADICR)
+
+/** \brief 2034, DMA Channel Configuration Register */
+#define DMA_CH1_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012034u)
+
+/** Alias (User Manual Name) for DMA_CH1_CHCFGR.
+* To use register names with standard convension, please use DMA_CH1_CHCFGR.
+*/
+#define DMA_CHCFGR001 (DMA_CH1_CHCFGR)
+
+/** \brief 203C, DMARAM Channel Control and Status Register */
+#define DMA_CH1_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001203Cu)
+
+/** Alias (User Manual Name) for DMA_CH1_CHCSR.
+* To use register names with standard convension, please use DMA_CH1_CHCSR.
+*/
+#define DMA_CHCSR001 (DMA_CH1_CHCSR)
+
+/** \brief 202C, DMA Channel Destination Address Register x */
+#define DMA_CH1_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001202Cu)
+
+/** Alias (User Manual Name) for DMA_CH1_DADR.
+* To use register names with standard convension, please use DMA_CH1_DADR.
+*/
+#define DMA_DADR001 (DMA_CH1_DADR)
+
+/** \brief 2020, DMA Channel Read Data CRC Register */
+#define DMA_CH1_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012020u)
+
+/** Alias (User Manual Name) for DMA_CH1_RDCRCR.
+* To use register names with standard convension, please use DMA_CH1_RDCRCR.
+*/
+#define DMA_RDCRCR001 (DMA_CH1_RDCRCR)
+
+/** \brief 2028, DMA Channel Source Address Register */
+#define DMA_CH1_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012028u)
+
+/** Alias (User Manual Name) for DMA_CH1_SADR.
+* To use register names with standard convension, please use DMA_CH1_SADR.
+*/
+#define DMA_SADR001 (DMA_CH1_SADR)
+
+/** \brief 2024, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH1_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012024u)
+
+/** Alias (User Manual Name) for DMA_CH1_SDCRCR.
+* To use register names with standard convension, please use DMA_CH1_SDCRCR.
+*/
+#define DMA_SDCRCR001 (DMA_CH1_SDCRCR)
+
+/** \brief 2038, DMA Channel Shadow Address Register */
+#define DMA_CH1_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012038u)
+
+/** Alias (User Manual Name) for DMA_CH1_SHADR.
+* To use register names with standard convension, please use DMA_CH1_SHADR.
+*/
+#define DMA_SHADR001 (DMA_CH1_SHADR)
+
+/** \brief 2290, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH20_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012290u)
+
+/** Alias (User Manual Name) for DMA_CH20_ADICR.
+* To use register names with standard convension, please use DMA_CH20_ADICR.
+*/
+#define DMA_ADICR020 (DMA_CH20_ADICR)
+
+/** \brief 2294, DMA Channel Configuration Register */
+#define DMA_CH20_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012294u)
+
+/** Alias (User Manual Name) for DMA_CH20_CHCFGR.
+* To use register names with standard convension, please use DMA_CH20_CHCFGR.
+*/
+#define DMA_CHCFGR020 (DMA_CH20_CHCFGR)
+
+/** \brief 229C, DMARAM Channel Control and Status Register */
+#define DMA_CH20_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001229Cu)
+
+/** Alias (User Manual Name) for DMA_CH20_CHCSR.
+* To use register names with standard convension, please use DMA_CH20_CHCSR.
+*/
+#define DMA_CHCSR020 (DMA_CH20_CHCSR)
+
+/** \brief 228C, DMA Channel Destination Address Register x */
+#define DMA_CH20_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001228Cu)
+
+/** Alias (User Manual Name) for DMA_CH20_DADR.
+* To use register names with standard convension, please use DMA_CH20_DADR.
+*/
+#define DMA_DADR020 (DMA_CH20_DADR)
+
+/** \brief 2280, DMA Channel Read Data CRC Register */
+#define DMA_CH20_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012280u)
+
+/** Alias (User Manual Name) for DMA_CH20_RDCRCR.
+* To use register names with standard convension, please use DMA_CH20_RDCRCR.
+*/
+#define DMA_RDCRCR020 (DMA_CH20_RDCRCR)
+
+/** \brief 2288, DMA Channel Source Address Register */
+#define DMA_CH20_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012288u)
+
+/** Alias (User Manual Name) for DMA_CH20_SADR.
+* To use register names with standard convension, please use DMA_CH20_SADR.
+*/
+#define DMA_SADR020 (DMA_CH20_SADR)
+
+/** \brief 2284, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH20_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012284u)
+
+/** Alias (User Manual Name) for DMA_CH20_SDCRCR.
+* To use register names with standard convension, please use DMA_CH20_SDCRCR.
+*/
+#define DMA_SDCRCR020 (DMA_CH20_SDCRCR)
+
+/** \brief 2298, DMA Channel Shadow Address Register */
+#define DMA_CH20_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012298u)
+
+/** Alias (User Manual Name) for DMA_CH20_SHADR.
+* To use register names with standard convension, please use DMA_CH20_SHADR.
+*/
+#define DMA_SHADR020 (DMA_CH20_SHADR)
+
+/** \brief 22B0, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH21_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF00122B0u)
+
+/** Alias (User Manual Name) for DMA_CH21_ADICR.
+* To use register names with standard convension, please use DMA_CH21_ADICR.
+*/
+#define DMA_ADICR021 (DMA_CH21_ADICR)
+
+/** \brief 22B4, DMA Channel Configuration Register */
+#define DMA_CH21_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF00122B4u)
+
+/** Alias (User Manual Name) for DMA_CH21_CHCFGR.
+* To use register names with standard convension, please use DMA_CH21_CHCFGR.
+*/
+#define DMA_CHCFGR021 (DMA_CH21_CHCFGR)
+
+/** \brief 22BC, DMARAM Channel Control and Status Register */
+#define DMA_CH21_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF00122BCu)
+
+/** Alias (User Manual Name) for DMA_CH21_CHCSR.
+* To use register names with standard convension, please use DMA_CH21_CHCSR.
+*/
+#define DMA_CHCSR021 (DMA_CH21_CHCSR)
+
+/** \brief 22AC, DMA Channel Destination Address Register x */
+#define DMA_CH21_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF00122ACu)
+
+/** Alias (User Manual Name) for DMA_CH21_DADR.
+* To use register names with standard convension, please use DMA_CH21_DADR.
+*/
+#define DMA_DADR021 (DMA_CH21_DADR)
+
+/** \brief 22A0, DMA Channel Read Data CRC Register */
+#define DMA_CH21_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF00122A0u)
+
+/** Alias (User Manual Name) for DMA_CH21_RDCRCR.
+* To use register names with standard convension, please use DMA_CH21_RDCRCR.
+*/
+#define DMA_RDCRCR021 (DMA_CH21_RDCRCR)
+
+/** \brief 22A8, DMA Channel Source Address Register */
+#define DMA_CH21_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF00122A8u)
+
+/** Alias (User Manual Name) for DMA_CH21_SADR.
+* To use register names with standard convension, please use DMA_CH21_SADR.
+*/
+#define DMA_SADR021 (DMA_CH21_SADR)
+
+/** \brief 22A4, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH21_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF00122A4u)
+
+/** Alias (User Manual Name) for DMA_CH21_SDCRCR.
+* To use register names with standard convension, please use DMA_CH21_SDCRCR.
+*/
+#define DMA_SDCRCR021 (DMA_CH21_SDCRCR)
+
+/** \brief 22B8, DMA Channel Shadow Address Register */
+#define DMA_CH21_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF00122B8u)
+
+/** Alias (User Manual Name) for DMA_CH21_SHADR.
+* To use register names with standard convension, please use DMA_CH21_SHADR.
+*/
+#define DMA_SHADR021 (DMA_CH21_SHADR)
+
+/** \brief 22D0, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH22_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF00122D0u)
+
+/** Alias (User Manual Name) for DMA_CH22_ADICR.
+* To use register names with standard convension, please use DMA_CH22_ADICR.
+*/
+#define DMA_ADICR022 (DMA_CH22_ADICR)
+
+/** \brief 22D4, DMA Channel Configuration Register */
+#define DMA_CH22_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF00122D4u)
+
+/** Alias (User Manual Name) for DMA_CH22_CHCFGR.
+* To use register names with standard convension, please use DMA_CH22_CHCFGR.
+*/
+#define DMA_CHCFGR022 (DMA_CH22_CHCFGR)
+
+/** \brief 22DC, DMARAM Channel Control and Status Register */
+#define DMA_CH22_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF00122DCu)
+
+/** Alias (User Manual Name) for DMA_CH22_CHCSR.
+* To use register names with standard convension, please use DMA_CH22_CHCSR.
+*/
+#define DMA_CHCSR022 (DMA_CH22_CHCSR)
+
+/** \brief 22CC, DMA Channel Destination Address Register x */
+#define DMA_CH22_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF00122CCu)
+
+/** Alias (User Manual Name) for DMA_CH22_DADR.
+* To use register names with standard convension, please use DMA_CH22_DADR.
+*/
+#define DMA_DADR022 (DMA_CH22_DADR)
+
+/** \brief 22C0, DMA Channel Read Data CRC Register */
+#define DMA_CH22_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF00122C0u)
+
+/** Alias (User Manual Name) for DMA_CH22_RDCRCR.
+* To use register names with standard convension, please use DMA_CH22_RDCRCR.
+*/
+#define DMA_RDCRCR022 (DMA_CH22_RDCRCR)
+
+/** \brief 22C8, DMA Channel Source Address Register */
+#define DMA_CH22_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF00122C8u)
+
+/** Alias (User Manual Name) for DMA_CH22_SADR.
+* To use register names with standard convension, please use DMA_CH22_SADR.
+*/
+#define DMA_SADR022 (DMA_CH22_SADR)
+
+/** \brief 22C4, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH22_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF00122C4u)
+
+/** Alias (User Manual Name) for DMA_CH22_SDCRCR.
+* To use register names with standard convension, please use DMA_CH22_SDCRCR.
+*/
+#define DMA_SDCRCR022 (DMA_CH22_SDCRCR)
+
+/** \brief 22D8, DMA Channel Shadow Address Register */
+#define DMA_CH22_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF00122D8u)
+
+/** Alias (User Manual Name) for DMA_CH22_SHADR.
+* To use register names with standard convension, please use DMA_CH22_SHADR.
+*/
+#define DMA_SHADR022 (DMA_CH22_SHADR)
+
+/** \brief 22F0, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH23_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF00122F0u)
+
+/** Alias (User Manual Name) for DMA_CH23_ADICR.
+* To use register names with standard convension, please use DMA_CH23_ADICR.
+*/
+#define DMA_ADICR023 (DMA_CH23_ADICR)
+
+/** \brief 22F4, DMA Channel Configuration Register */
+#define DMA_CH23_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF00122F4u)
+
+/** Alias (User Manual Name) for DMA_CH23_CHCFGR.
+* To use register names with standard convension, please use DMA_CH23_CHCFGR.
+*/
+#define DMA_CHCFGR023 (DMA_CH23_CHCFGR)
+
+/** \brief 22FC, DMARAM Channel Control and Status Register */
+#define DMA_CH23_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF00122FCu)
+
+/** Alias (User Manual Name) for DMA_CH23_CHCSR.
+* To use register names with standard convension, please use DMA_CH23_CHCSR.
+*/
+#define DMA_CHCSR023 (DMA_CH23_CHCSR)
+
+/** \brief 22EC, DMA Channel Destination Address Register x */
+#define DMA_CH23_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF00122ECu)
+
+/** Alias (User Manual Name) for DMA_CH23_DADR.
+* To use register names with standard convension, please use DMA_CH23_DADR.
+*/
+#define DMA_DADR023 (DMA_CH23_DADR)
+
+/** \brief 22E0, DMA Channel Read Data CRC Register */
+#define DMA_CH23_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF00122E0u)
+
+/** Alias (User Manual Name) for DMA_CH23_RDCRCR.
+* To use register names with standard convension, please use DMA_CH23_RDCRCR.
+*/
+#define DMA_RDCRCR023 (DMA_CH23_RDCRCR)
+
+/** \brief 22E8, DMA Channel Source Address Register */
+#define DMA_CH23_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF00122E8u)
+
+/** Alias (User Manual Name) for DMA_CH23_SADR.
+* To use register names with standard convension, please use DMA_CH23_SADR.
+*/
+#define DMA_SADR023 (DMA_CH23_SADR)
+
+/** \brief 22E4, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH23_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF00122E4u)
+
+/** Alias (User Manual Name) for DMA_CH23_SDCRCR.
+* To use register names with standard convension, please use DMA_CH23_SDCRCR.
+*/
+#define DMA_SDCRCR023 (DMA_CH23_SDCRCR)
+
+/** \brief 22F8, DMA Channel Shadow Address Register */
+#define DMA_CH23_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF00122F8u)
+
+/** Alias (User Manual Name) for DMA_CH23_SHADR.
+* To use register names with standard convension, please use DMA_CH23_SHADR.
+*/
+#define DMA_SHADR023 (DMA_CH23_SHADR)
+
+/** \brief 2310, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH24_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012310u)
+
+/** Alias (User Manual Name) for DMA_CH24_ADICR.
+* To use register names with standard convension, please use DMA_CH24_ADICR.
+*/
+#define DMA_ADICR024 (DMA_CH24_ADICR)
+
+/** \brief 2314, DMA Channel Configuration Register */
+#define DMA_CH24_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012314u)
+
+/** Alias (User Manual Name) for DMA_CH24_CHCFGR.
+* To use register names with standard convension, please use DMA_CH24_CHCFGR.
+*/
+#define DMA_CHCFGR024 (DMA_CH24_CHCFGR)
+
+/** \brief 231C, DMARAM Channel Control and Status Register */
+#define DMA_CH24_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001231Cu)
+
+/** Alias (User Manual Name) for DMA_CH24_CHCSR.
+* To use register names with standard convension, please use DMA_CH24_CHCSR.
+*/
+#define DMA_CHCSR024 (DMA_CH24_CHCSR)
+
+/** \brief 230C, DMA Channel Destination Address Register x */
+#define DMA_CH24_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001230Cu)
+
+/** Alias (User Manual Name) for DMA_CH24_DADR.
+* To use register names with standard convension, please use DMA_CH24_DADR.
+*/
+#define DMA_DADR024 (DMA_CH24_DADR)
+
+/** \brief 2300, DMA Channel Read Data CRC Register */
+#define DMA_CH24_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012300u)
+
+/** Alias (User Manual Name) for DMA_CH24_RDCRCR.
+* To use register names with standard convension, please use DMA_CH24_RDCRCR.
+*/
+#define DMA_RDCRCR024 (DMA_CH24_RDCRCR)
+
+/** \brief 2308, DMA Channel Source Address Register */
+#define DMA_CH24_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012308u)
+
+/** Alias (User Manual Name) for DMA_CH24_SADR.
+* To use register names with standard convension, please use DMA_CH24_SADR.
+*/
+#define DMA_SADR024 (DMA_CH24_SADR)
+
+/** \brief 2304, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH24_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012304u)
+
+/** Alias (User Manual Name) for DMA_CH24_SDCRCR.
+* To use register names with standard convension, please use DMA_CH24_SDCRCR.
+*/
+#define DMA_SDCRCR024 (DMA_CH24_SDCRCR)
+
+/** \brief 2318, DMA Channel Shadow Address Register */
+#define DMA_CH24_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012318u)
+
+/** Alias (User Manual Name) for DMA_CH24_SHADR.
+* To use register names with standard convension, please use DMA_CH24_SHADR.
+*/
+#define DMA_SHADR024 (DMA_CH24_SHADR)
+
+/** \brief 2330, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH25_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012330u)
+
+/** Alias (User Manual Name) for DMA_CH25_ADICR.
+* To use register names with standard convension, please use DMA_CH25_ADICR.
+*/
+#define DMA_ADICR025 (DMA_CH25_ADICR)
+
+/** \brief 2334, DMA Channel Configuration Register */
+#define DMA_CH25_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012334u)
+
+/** Alias (User Manual Name) for DMA_CH25_CHCFGR.
+* To use register names with standard convension, please use DMA_CH25_CHCFGR.
+*/
+#define DMA_CHCFGR025 (DMA_CH25_CHCFGR)
+
+/** \brief 233C, DMARAM Channel Control and Status Register */
+#define DMA_CH25_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001233Cu)
+
+/** Alias (User Manual Name) for DMA_CH25_CHCSR.
+* To use register names with standard convension, please use DMA_CH25_CHCSR.
+*/
+#define DMA_CHCSR025 (DMA_CH25_CHCSR)
+
+/** \brief 232C, DMA Channel Destination Address Register x */
+#define DMA_CH25_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001232Cu)
+
+/** Alias (User Manual Name) for DMA_CH25_DADR.
+* To use register names with standard convension, please use DMA_CH25_DADR.
+*/
+#define DMA_DADR025 (DMA_CH25_DADR)
+
+/** \brief 2320, DMA Channel Read Data CRC Register */
+#define DMA_CH25_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012320u)
+
+/** Alias (User Manual Name) for DMA_CH25_RDCRCR.
+* To use register names with standard convension, please use DMA_CH25_RDCRCR.
+*/
+#define DMA_RDCRCR025 (DMA_CH25_RDCRCR)
+
+/** \brief 2328, DMA Channel Source Address Register */
+#define DMA_CH25_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012328u)
+
+/** Alias (User Manual Name) for DMA_CH25_SADR.
+* To use register names with standard convension, please use DMA_CH25_SADR.
+*/
+#define DMA_SADR025 (DMA_CH25_SADR)
+
+/** \brief 2324, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH25_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012324u)
+
+/** Alias (User Manual Name) for DMA_CH25_SDCRCR.
+* To use register names with standard convension, please use DMA_CH25_SDCRCR.
+*/
+#define DMA_SDCRCR025 (DMA_CH25_SDCRCR)
+
+/** \brief 2338, DMA Channel Shadow Address Register */
+#define DMA_CH25_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012338u)
+
+/** Alias (User Manual Name) for DMA_CH25_SHADR.
+* To use register names with standard convension, please use DMA_CH25_SHADR.
+*/
+#define DMA_SHADR025 (DMA_CH25_SHADR)
+
+/** \brief 2350, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH26_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012350u)
+
+/** Alias (User Manual Name) for DMA_CH26_ADICR.
+* To use register names with standard convension, please use DMA_CH26_ADICR.
+*/
+#define DMA_ADICR026 (DMA_CH26_ADICR)
+
+/** \brief 2354, DMA Channel Configuration Register */
+#define DMA_CH26_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012354u)
+
+/** Alias (User Manual Name) for DMA_CH26_CHCFGR.
+* To use register names with standard convension, please use DMA_CH26_CHCFGR.
+*/
+#define DMA_CHCFGR026 (DMA_CH26_CHCFGR)
+
+/** \brief 235C, DMARAM Channel Control and Status Register */
+#define DMA_CH26_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001235Cu)
+
+/** Alias (User Manual Name) for DMA_CH26_CHCSR.
+* To use register names with standard convension, please use DMA_CH26_CHCSR.
+*/
+#define DMA_CHCSR026 (DMA_CH26_CHCSR)
+
+/** \brief 234C, DMA Channel Destination Address Register x */
+#define DMA_CH26_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001234Cu)
+
+/** Alias (User Manual Name) for DMA_CH26_DADR.
+* To use register names with standard convension, please use DMA_CH26_DADR.
+*/
+#define DMA_DADR026 (DMA_CH26_DADR)
+
+/** \brief 2340, DMA Channel Read Data CRC Register */
+#define DMA_CH26_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012340u)
+
+/** Alias (User Manual Name) for DMA_CH26_RDCRCR.
+* To use register names with standard convension, please use DMA_CH26_RDCRCR.
+*/
+#define DMA_RDCRCR026 (DMA_CH26_RDCRCR)
+
+/** \brief 2348, DMA Channel Source Address Register */
+#define DMA_CH26_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012348u)
+
+/** Alias (User Manual Name) for DMA_CH26_SADR.
+* To use register names with standard convension, please use DMA_CH26_SADR.
+*/
+#define DMA_SADR026 (DMA_CH26_SADR)
+
+/** \brief 2344, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH26_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012344u)
+
+/** Alias (User Manual Name) for DMA_CH26_SDCRCR.
+* To use register names with standard convension, please use DMA_CH26_SDCRCR.
+*/
+#define DMA_SDCRCR026 (DMA_CH26_SDCRCR)
+
+/** \brief 2358, DMA Channel Shadow Address Register */
+#define DMA_CH26_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012358u)
+
+/** Alias (User Manual Name) for DMA_CH26_SHADR.
+* To use register names with standard convension, please use DMA_CH26_SHADR.
+*/
+#define DMA_SHADR026 (DMA_CH26_SHADR)
+
+/** \brief 2370, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH27_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012370u)
+
+/** Alias (User Manual Name) for DMA_CH27_ADICR.
+* To use register names with standard convension, please use DMA_CH27_ADICR.
+*/
+#define DMA_ADICR027 (DMA_CH27_ADICR)
+
+/** \brief 2374, DMA Channel Configuration Register */
+#define DMA_CH27_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012374u)
+
+/** Alias (User Manual Name) for DMA_CH27_CHCFGR.
+* To use register names with standard convension, please use DMA_CH27_CHCFGR.
+*/
+#define DMA_CHCFGR027 (DMA_CH27_CHCFGR)
+
+/** \brief 237C, DMARAM Channel Control and Status Register */
+#define DMA_CH27_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001237Cu)
+
+/** Alias (User Manual Name) for DMA_CH27_CHCSR.
+* To use register names with standard convension, please use DMA_CH27_CHCSR.
+*/
+#define DMA_CHCSR027 (DMA_CH27_CHCSR)
+
+/** \brief 236C, DMA Channel Destination Address Register x */
+#define DMA_CH27_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001236Cu)
+
+/** Alias (User Manual Name) for DMA_CH27_DADR.
+* To use register names with standard convension, please use DMA_CH27_DADR.
+*/
+#define DMA_DADR027 (DMA_CH27_DADR)
+
+/** \brief 2360, DMA Channel Read Data CRC Register */
+#define DMA_CH27_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012360u)
+
+/** Alias (User Manual Name) for DMA_CH27_RDCRCR.
+* To use register names with standard convension, please use DMA_CH27_RDCRCR.
+*/
+#define DMA_RDCRCR027 (DMA_CH27_RDCRCR)
+
+/** \brief 2368, DMA Channel Source Address Register */
+#define DMA_CH27_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012368u)
+
+/** Alias (User Manual Name) for DMA_CH27_SADR.
+* To use register names with standard convension, please use DMA_CH27_SADR.
+*/
+#define DMA_SADR027 (DMA_CH27_SADR)
+
+/** \brief 2364, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH27_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012364u)
+
+/** Alias (User Manual Name) for DMA_CH27_SDCRCR.
+* To use register names with standard convension, please use DMA_CH27_SDCRCR.
+*/
+#define DMA_SDCRCR027 (DMA_CH27_SDCRCR)
+
+/** \brief 2378, DMA Channel Shadow Address Register */
+#define DMA_CH27_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012378u)
+
+/** Alias (User Manual Name) for DMA_CH27_SHADR.
+* To use register names with standard convension, please use DMA_CH27_SHADR.
+*/
+#define DMA_SHADR027 (DMA_CH27_SHADR)
+
+/** \brief 2390, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH28_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012390u)
+
+/** Alias (User Manual Name) for DMA_CH28_ADICR.
+* To use register names with standard convension, please use DMA_CH28_ADICR.
+*/
+#define DMA_ADICR028 (DMA_CH28_ADICR)
+
+/** \brief 2394, DMA Channel Configuration Register */
+#define DMA_CH28_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012394u)
+
+/** Alias (User Manual Name) for DMA_CH28_CHCFGR.
+* To use register names with standard convension, please use DMA_CH28_CHCFGR.
+*/
+#define DMA_CHCFGR028 (DMA_CH28_CHCFGR)
+
+/** \brief 239C, DMARAM Channel Control and Status Register */
+#define DMA_CH28_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001239Cu)
+
+/** Alias (User Manual Name) for DMA_CH28_CHCSR.
+* To use register names with standard convension, please use DMA_CH28_CHCSR.
+*/
+#define DMA_CHCSR028 (DMA_CH28_CHCSR)
+
+/** \brief 238C, DMA Channel Destination Address Register x */
+#define DMA_CH28_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001238Cu)
+
+/** Alias (User Manual Name) for DMA_CH28_DADR.
+* To use register names with standard convension, please use DMA_CH28_DADR.
+*/
+#define DMA_DADR028 (DMA_CH28_DADR)
+
+/** \brief 2380, DMA Channel Read Data CRC Register */
+#define DMA_CH28_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012380u)
+
+/** Alias (User Manual Name) for DMA_CH28_RDCRCR.
+* To use register names with standard convension, please use DMA_CH28_RDCRCR.
+*/
+#define DMA_RDCRCR028 (DMA_CH28_RDCRCR)
+
+/** \brief 2388, DMA Channel Source Address Register */
+#define DMA_CH28_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012388u)
+
+/** Alias (User Manual Name) for DMA_CH28_SADR.
+* To use register names with standard convension, please use DMA_CH28_SADR.
+*/
+#define DMA_SADR028 (DMA_CH28_SADR)
+
+/** \brief 2384, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH28_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012384u)
+
+/** Alias (User Manual Name) for DMA_CH28_SDCRCR.
+* To use register names with standard convension, please use DMA_CH28_SDCRCR.
+*/
+#define DMA_SDCRCR028 (DMA_CH28_SDCRCR)
+
+/** \brief 2398, DMA Channel Shadow Address Register */
+#define DMA_CH28_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012398u)
+
+/** Alias (User Manual Name) for DMA_CH28_SHADR.
+* To use register names with standard convension, please use DMA_CH28_SHADR.
+*/
+#define DMA_SHADR028 (DMA_CH28_SHADR)
+
+/** \brief 23B0, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH29_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF00123B0u)
+
+/** Alias (User Manual Name) for DMA_CH29_ADICR.
+* To use register names with standard convension, please use DMA_CH29_ADICR.
+*/
+#define DMA_ADICR029 (DMA_CH29_ADICR)
+
+/** \brief 23B4, DMA Channel Configuration Register */
+#define DMA_CH29_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF00123B4u)
+
+/** Alias (User Manual Name) for DMA_CH29_CHCFGR.
+* To use register names with standard convension, please use DMA_CH29_CHCFGR.
+*/
+#define DMA_CHCFGR029 (DMA_CH29_CHCFGR)
+
+/** \brief 23BC, DMARAM Channel Control and Status Register */
+#define DMA_CH29_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF00123BCu)
+
+/** Alias (User Manual Name) for DMA_CH29_CHCSR.
+* To use register names with standard convension, please use DMA_CH29_CHCSR.
+*/
+#define DMA_CHCSR029 (DMA_CH29_CHCSR)
+
+/** \brief 23AC, DMA Channel Destination Address Register x */
+#define DMA_CH29_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF00123ACu)
+
+/** Alias (User Manual Name) for DMA_CH29_DADR.
+* To use register names with standard convension, please use DMA_CH29_DADR.
+*/
+#define DMA_DADR029 (DMA_CH29_DADR)
+
+/** \brief 23A0, DMA Channel Read Data CRC Register */
+#define DMA_CH29_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF00123A0u)
+
+/** Alias (User Manual Name) for DMA_CH29_RDCRCR.
+* To use register names with standard convension, please use DMA_CH29_RDCRCR.
+*/
+#define DMA_RDCRCR029 (DMA_CH29_RDCRCR)
+
+/** \brief 23A8, DMA Channel Source Address Register */
+#define DMA_CH29_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF00123A8u)
+
+/** Alias (User Manual Name) for DMA_CH29_SADR.
+* To use register names with standard convension, please use DMA_CH29_SADR.
+*/
+#define DMA_SADR029 (DMA_CH29_SADR)
+
+/** \brief 23A4, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH29_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF00123A4u)
+
+/** Alias (User Manual Name) for DMA_CH29_SDCRCR.
+* To use register names with standard convension, please use DMA_CH29_SDCRCR.
+*/
+#define DMA_SDCRCR029 (DMA_CH29_SDCRCR)
+
+/** \brief 23B8, DMA Channel Shadow Address Register */
+#define DMA_CH29_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF00123B8u)
+
+/** Alias (User Manual Name) for DMA_CH29_SHADR.
+* To use register names with standard convension, please use DMA_CH29_SHADR.
+*/
+#define DMA_SHADR029 (DMA_CH29_SHADR)
+
+/** \brief 2050, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH2_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012050u)
+
+/** Alias (User Manual Name) for DMA_CH2_ADICR.
+* To use register names with standard convension, please use DMA_CH2_ADICR.
+*/
+#define DMA_ADICR002 (DMA_CH2_ADICR)
+
+/** \brief 2054, DMA Channel Configuration Register */
+#define DMA_CH2_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012054u)
+
+/** Alias (User Manual Name) for DMA_CH2_CHCFGR.
+* To use register names with standard convension, please use DMA_CH2_CHCFGR.
+*/
+#define DMA_CHCFGR002 (DMA_CH2_CHCFGR)
+
+/** \brief 205C, DMARAM Channel Control and Status Register */
+#define DMA_CH2_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001205Cu)
+
+/** Alias (User Manual Name) for DMA_CH2_CHCSR.
+* To use register names with standard convension, please use DMA_CH2_CHCSR.
+*/
+#define DMA_CHCSR002 (DMA_CH2_CHCSR)
+
+/** \brief 204C, DMA Channel Destination Address Register x */
+#define DMA_CH2_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001204Cu)
+
+/** Alias (User Manual Name) for DMA_CH2_DADR.
+* To use register names with standard convension, please use DMA_CH2_DADR.
+*/
+#define DMA_DADR002 (DMA_CH2_DADR)
+
+/** \brief 2040, DMA Channel Read Data CRC Register */
+#define DMA_CH2_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012040u)
+
+/** Alias (User Manual Name) for DMA_CH2_RDCRCR.
+* To use register names with standard convension, please use DMA_CH2_RDCRCR.
+*/
+#define DMA_RDCRCR002 (DMA_CH2_RDCRCR)
+
+/** \brief 2048, DMA Channel Source Address Register */
+#define DMA_CH2_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012048u)
+
+/** Alias (User Manual Name) for DMA_CH2_SADR.
+* To use register names with standard convension, please use DMA_CH2_SADR.
+*/
+#define DMA_SADR002 (DMA_CH2_SADR)
+
+/** \brief 2044, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH2_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012044u)
+
+/** Alias (User Manual Name) for DMA_CH2_SDCRCR.
+* To use register names with standard convension, please use DMA_CH2_SDCRCR.
+*/
+#define DMA_SDCRCR002 (DMA_CH2_SDCRCR)
+
+/** \brief 2058, DMA Channel Shadow Address Register */
+#define DMA_CH2_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012058u)
+
+/** Alias (User Manual Name) for DMA_CH2_SHADR.
+* To use register names with standard convension, please use DMA_CH2_SHADR.
+*/
+#define DMA_SHADR002 (DMA_CH2_SHADR)
+
+/** \brief 23D0, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH30_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF00123D0u)
+
+/** Alias (User Manual Name) for DMA_CH30_ADICR.
+* To use register names with standard convension, please use DMA_CH30_ADICR.
+*/
+#define DMA_ADICR030 (DMA_CH30_ADICR)
+
+/** \brief 23D4, DMA Channel Configuration Register */
+#define DMA_CH30_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF00123D4u)
+
+/** Alias (User Manual Name) for DMA_CH30_CHCFGR.
+* To use register names with standard convension, please use DMA_CH30_CHCFGR.
+*/
+#define DMA_CHCFGR030 (DMA_CH30_CHCFGR)
+
+/** \brief 23DC, DMARAM Channel Control and Status Register */
+#define DMA_CH30_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF00123DCu)
+
+/** Alias (User Manual Name) for DMA_CH30_CHCSR.
+* To use register names with standard convension, please use DMA_CH30_CHCSR.
+*/
+#define DMA_CHCSR030 (DMA_CH30_CHCSR)
+
+/** \brief 23CC, DMA Channel Destination Address Register x */
+#define DMA_CH30_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF00123CCu)
+
+/** Alias (User Manual Name) for DMA_CH30_DADR.
+* To use register names with standard convension, please use DMA_CH30_DADR.
+*/
+#define DMA_DADR030 (DMA_CH30_DADR)
+
+/** \brief 23C0, DMA Channel Read Data CRC Register */
+#define DMA_CH30_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF00123C0u)
+
+/** Alias (User Manual Name) for DMA_CH30_RDCRCR.
+* To use register names with standard convension, please use DMA_CH30_RDCRCR.
+*/
+#define DMA_RDCRCR030 (DMA_CH30_RDCRCR)
+
+/** \brief 23C8, DMA Channel Source Address Register */
+#define DMA_CH30_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF00123C8u)
+
+/** Alias (User Manual Name) for DMA_CH30_SADR.
+* To use register names with standard convension, please use DMA_CH30_SADR.
+*/
+#define DMA_SADR030 (DMA_CH30_SADR)
+
+/** \brief 23C4, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH30_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF00123C4u)
+
+/** Alias (User Manual Name) for DMA_CH30_SDCRCR.
+* To use register names with standard convension, please use DMA_CH30_SDCRCR.
+*/
+#define DMA_SDCRCR030 (DMA_CH30_SDCRCR)
+
+/** \brief 23D8, DMA Channel Shadow Address Register */
+#define DMA_CH30_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF00123D8u)
+
+/** Alias (User Manual Name) for DMA_CH30_SHADR.
+* To use register names with standard convension, please use DMA_CH30_SHADR.
+*/
+#define DMA_SHADR030 (DMA_CH30_SHADR)
+
+/** \brief 23F0, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH31_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF00123F0u)
+
+/** Alias (User Manual Name) for DMA_CH31_ADICR.
+* To use register names with standard convension, please use DMA_CH31_ADICR.
+*/
+#define DMA_ADICR031 (DMA_CH31_ADICR)
+
+/** \brief 23F4, DMA Channel Configuration Register */
+#define DMA_CH31_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF00123F4u)
+
+/** Alias (User Manual Name) for DMA_CH31_CHCFGR.
+* To use register names with standard convension, please use DMA_CH31_CHCFGR.
+*/
+#define DMA_CHCFGR031 (DMA_CH31_CHCFGR)
+
+/** \brief 23FC, DMARAM Channel Control and Status Register */
+#define DMA_CH31_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF00123FCu)
+
+/** Alias (User Manual Name) for DMA_CH31_CHCSR.
+* To use register names with standard convension, please use DMA_CH31_CHCSR.
+*/
+#define DMA_CHCSR031 (DMA_CH31_CHCSR)
+
+/** \brief 23EC, DMA Channel Destination Address Register x */
+#define DMA_CH31_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF00123ECu)
+
+/** Alias (User Manual Name) for DMA_CH31_DADR.
+* To use register names with standard convension, please use DMA_CH31_DADR.
+*/
+#define DMA_DADR031 (DMA_CH31_DADR)
+
+/** \brief 23E0, DMA Channel Read Data CRC Register */
+#define DMA_CH31_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF00123E0u)
+
+/** Alias (User Manual Name) for DMA_CH31_RDCRCR.
+* To use register names with standard convension, please use DMA_CH31_RDCRCR.
+*/
+#define DMA_RDCRCR031 (DMA_CH31_RDCRCR)
+
+/** \brief 23E8, DMA Channel Source Address Register */
+#define DMA_CH31_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF00123E8u)
+
+/** Alias (User Manual Name) for DMA_CH31_SADR.
+* To use register names with standard convension, please use DMA_CH31_SADR.
+*/
+#define DMA_SADR031 (DMA_CH31_SADR)
+
+/** \brief 23E4, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH31_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF00123E4u)
+
+/** Alias (User Manual Name) for DMA_CH31_SDCRCR.
+* To use register names with standard convension, please use DMA_CH31_SDCRCR.
+*/
+#define DMA_SDCRCR031 (DMA_CH31_SDCRCR)
+
+/** \brief 23F8, DMA Channel Shadow Address Register */
+#define DMA_CH31_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF00123F8u)
+
+/** Alias (User Manual Name) for DMA_CH31_SHADR.
+* To use register names with standard convension, please use DMA_CH31_SHADR.
+*/
+#define DMA_SHADR031 (DMA_CH31_SHADR)
+
+/** \brief 2410, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH32_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012410u)
+
+/** Alias (User Manual Name) for DMA_CH32_ADICR.
+* To use register names with standard convension, please use DMA_CH32_ADICR.
+*/
+#define DMA_ADICR032 (DMA_CH32_ADICR)
+
+/** \brief 2414, DMA Channel Configuration Register */
+#define DMA_CH32_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012414u)
+
+/** Alias (User Manual Name) for DMA_CH32_CHCFGR.
+* To use register names with standard convension, please use DMA_CH32_CHCFGR.
+*/
+#define DMA_CHCFGR032 (DMA_CH32_CHCFGR)
+
+/** \brief 241C, DMARAM Channel Control and Status Register */
+#define DMA_CH32_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001241Cu)
+
+/** Alias (User Manual Name) for DMA_CH32_CHCSR.
+* To use register names with standard convension, please use DMA_CH32_CHCSR.
+*/
+#define DMA_CHCSR032 (DMA_CH32_CHCSR)
+
+/** \brief 240C, DMA Channel Destination Address Register x */
+#define DMA_CH32_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001240Cu)
+
+/** Alias (User Manual Name) for DMA_CH32_DADR.
+* To use register names with standard convension, please use DMA_CH32_DADR.
+*/
+#define DMA_DADR032 (DMA_CH32_DADR)
+
+/** \brief 2400, DMA Channel Read Data CRC Register */
+#define DMA_CH32_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012400u)
+
+/** Alias (User Manual Name) for DMA_CH32_RDCRCR.
+* To use register names with standard convension, please use DMA_CH32_RDCRCR.
+*/
+#define DMA_RDCRCR032 (DMA_CH32_RDCRCR)
+
+/** \brief 2408, DMA Channel Source Address Register */
+#define DMA_CH32_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012408u)
+
+/** Alias (User Manual Name) for DMA_CH32_SADR.
+* To use register names with standard convension, please use DMA_CH32_SADR.
+*/
+#define DMA_SADR032 (DMA_CH32_SADR)
+
+/** \brief 2404, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH32_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012404u)
+
+/** Alias (User Manual Name) for DMA_CH32_SDCRCR.
+* To use register names with standard convension, please use DMA_CH32_SDCRCR.
+*/
+#define DMA_SDCRCR032 (DMA_CH32_SDCRCR)
+
+/** \brief 2418, DMA Channel Shadow Address Register */
+#define DMA_CH32_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012418u)
+
+/** Alias (User Manual Name) for DMA_CH32_SHADR.
+* To use register names with standard convension, please use DMA_CH32_SHADR.
+*/
+#define DMA_SHADR032 (DMA_CH32_SHADR)
+
+/** \brief 2430, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH33_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012430u)
+
+/** Alias (User Manual Name) for DMA_CH33_ADICR.
+* To use register names with standard convension, please use DMA_CH33_ADICR.
+*/
+#define DMA_ADICR033 (DMA_CH33_ADICR)
+
+/** \brief 2434, DMA Channel Configuration Register */
+#define DMA_CH33_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012434u)
+
+/** Alias (User Manual Name) for DMA_CH33_CHCFGR.
+* To use register names with standard convension, please use DMA_CH33_CHCFGR.
+*/
+#define DMA_CHCFGR033 (DMA_CH33_CHCFGR)
+
+/** \brief 243C, DMARAM Channel Control and Status Register */
+#define DMA_CH33_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001243Cu)
+
+/** Alias (User Manual Name) for DMA_CH33_CHCSR.
+* To use register names with standard convension, please use DMA_CH33_CHCSR.
+*/
+#define DMA_CHCSR033 (DMA_CH33_CHCSR)
+
+/** \brief 242C, DMA Channel Destination Address Register x */
+#define DMA_CH33_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001242Cu)
+
+/** Alias (User Manual Name) for DMA_CH33_DADR.
+* To use register names with standard convension, please use DMA_CH33_DADR.
+*/
+#define DMA_DADR033 (DMA_CH33_DADR)
+
+/** \brief 2420, DMA Channel Read Data CRC Register */
+#define DMA_CH33_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012420u)
+
+/** Alias (User Manual Name) for DMA_CH33_RDCRCR.
+* To use register names with standard convension, please use DMA_CH33_RDCRCR.
+*/
+#define DMA_RDCRCR033 (DMA_CH33_RDCRCR)
+
+/** \brief 2428, DMA Channel Source Address Register */
+#define DMA_CH33_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012428u)
+
+/** Alias (User Manual Name) for DMA_CH33_SADR.
+* To use register names with standard convension, please use DMA_CH33_SADR.
+*/
+#define DMA_SADR033 (DMA_CH33_SADR)
+
+/** \brief 2424, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH33_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012424u)
+
+/** Alias (User Manual Name) for DMA_CH33_SDCRCR.
+* To use register names with standard convension, please use DMA_CH33_SDCRCR.
+*/
+#define DMA_SDCRCR033 (DMA_CH33_SDCRCR)
+
+/** \brief 2438, DMA Channel Shadow Address Register */
+#define DMA_CH33_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012438u)
+
+/** Alias (User Manual Name) for DMA_CH33_SHADR.
+* To use register names with standard convension, please use DMA_CH33_SHADR.
+*/
+#define DMA_SHADR033 (DMA_CH33_SHADR)
+
+/** \brief 2450, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH34_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012450u)
+
+/** Alias (User Manual Name) for DMA_CH34_ADICR.
+* To use register names with standard convension, please use DMA_CH34_ADICR.
+*/
+#define DMA_ADICR034 (DMA_CH34_ADICR)
+
+/** \brief 2454, DMA Channel Configuration Register */
+#define DMA_CH34_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012454u)
+
+/** Alias (User Manual Name) for DMA_CH34_CHCFGR.
+* To use register names with standard convension, please use DMA_CH34_CHCFGR.
+*/
+#define DMA_CHCFGR034 (DMA_CH34_CHCFGR)
+
+/** \brief 245C, DMARAM Channel Control and Status Register */
+#define DMA_CH34_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001245Cu)
+
+/** Alias (User Manual Name) for DMA_CH34_CHCSR.
+* To use register names with standard convension, please use DMA_CH34_CHCSR.
+*/
+#define DMA_CHCSR034 (DMA_CH34_CHCSR)
+
+/** \brief 244C, DMA Channel Destination Address Register x */
+#define DMA_CH34_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001244Cu)
+
+/** Alias (User Manual Name) for DMA_CH34_DADR.
+* To use register names with standard convension, please use DMA_CH34_DADR.
+*/
+#define DMA_DADR034 (DMA_CH34_DADR)
+
+/** \brief 2440, DMA Channel Read Data CRC Register */
+#define DMA_CH34_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012440u)
+
+/** Alias (User Manual Name) for DMA_CH34_RDCRCR.
+* To use register names with standard convension, please use DMA_CH34_RDCRCR.
+*/
+#define DMA_RDCRCR034 (DMA_CH34_RDCRCR)
+
+/** \brief 2448, DMA Channel Source Address Register */
+#define DMA_CH34_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012448u)
+
+/** Alias (User Manual Name) for DMA_CH34_SADR.
+* To use register names with standard convension, please use DMA_CH34_SADR.
+*/
+#define DMA_SADR034 (DMA_CH34_SADR)
+
+/** \brief 2444, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH34_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012444u)
+
+/** Alias (User Manual Name) for DMA_CH34_SDCRCR.
+* To use register names with standard convension, please use DMA_CH34_SDCRCR.
+*/
+#define DMA_SDCRCR034 (DMA_CH34_SDCRCR)
+
+/** \brief 2458, DMA Channel Shadow Address Register */
+#define DMA_CH34_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012458u)
+
+/** Alias (User Manual Name) for DMA_CH34_SHADR.
+* To use register names with standard convension, please use DMA_CH34_SHADR.
+*/
+#define DMA_SHADR034 (DMA_CH34_SHADR)
+
+/** \brief 2470, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH35_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012470u)
+
+/** Alias (User Manual Name) for DMA_CH35_ADICR.
+* To use register names with standard convension, please use DMA_CH35_ADICR.
+*/
+#define DMA_ADICR035 (DMA_CH35_ADICR)
+
+/** \brief 2474, DMA Channel Configuration Register */
+#define DMA_CH35_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012474u)
+
+/** Alias (User Manual Name) for DMA_CH35_CHCFGR.
+* To use register names with standard convension, please use DMA_CH35_CHCFGR.
+*/
+#define DMA_CHCFGR035 (DMA_CH35_CHCFGR)
+
+/** \brief 247C, DMARAM Channel Control and Status Register */
+#define DMA_CH35_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001247Cu)
+
+/** Alias (User Manual Name) for DMA_CH35_CHCSR.
+* To use register names with standard convension, please use DMA_CH35_CHCSR.
+*/
+#define DMA_CHCSR035 (DMA_CH35_CHCSR)
+
+/** \brief 246C, DMA Channel Destination Address Register x */
+#define DMA_CH35_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001246Cu)
+
+/** Alias (User Manual Name) for DMA_CH35_DADR.
+* To use register names with standard convension, please use DMA_CH35_DADR.
+*/
+#define DMA_DADR035 (DMA_CH35_DADR)
+
+/** \brief 2460, DMA Channel Read Data CRC Register */
+#define DMA_CH35_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012460u)
+
+/** Alias (User Manual Name) for DMA_CH35_RDCRCR.
+* To use register names with standard convension, please use DMA_CH35_RDCRCR.
+*/
+#define DMA_RDCRCR035 (DMA_CH35_RDCRCR)
+
+/** \brief 2468, DMA Channel Source Address Register */
+#define DMA_CH35_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012468u)
+
+/** Alias (User Manual Name) for DMA_CH35_SADR.
+* To use register names with standard convension, please use DMA_CH35_SADR.
+*/
+#define DMA_SADR035 (DMA_CH35_SADR)
+
+/** \brief 2464, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH35_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012464u)
+
+/** Alias (User Manual Name) for DMA_CH35_SDCRCR.
+* To use register names with standard convension, please use DMA_CH35_SDCRCR.
+*/
+#define DMA_SDCRCR035 (DMA_CH35_SDCRCR)
+
+/** \brief 2478, DMA Channel Shadow Address Register */
+#define DMA_CH35_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012478u)
+
+/** Alias (User Manual Name) for DMA_CH35_SHADR.
+* To use register names with standard convension, please use DMA_CH35_SHADR.
+*/
+#define DMA_SHADR035 (DMA_CH35_SHADR)
+
+/** \brief 2490, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH36_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012490u)
+
+/** Alias (User Manual Name) for DMA_CH36_ADICR.
+* To use register names with standard convension, please use DMA_CH36_ADICR.
+*/
+#define DMA_ADICR036 (DMA_CH36_ADICR)
+
+/** \brief 2494, DMA Channel Configuration Register */
+#define DMA_CH36_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012494u)
+
+/** Alias (User Manual Name) for DMA_CH36_CHCFGR.
+* To use register names with standard convension, please use DMA_CH36_CHCFGR.
+*/
+#define DMA_CHCFGR036 (DMA_CH36_CHCFGR)
+
+/** \brief 249C, DMARAM Channel Control and Status Register */
+#define DMA_CH36_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001249Cu)
+
+/** Alias (User Manual Name) for DMA_CH36_CHCSR.
+* To use register names with standard convension, please use DMA_CH36_CHCSR.
+*/
+#define DMA_CHCSR036 (DMA_CH36_CHCSR)
+
+/** \brief 248C, DMA Channel Destination Address Register x */
+#define DMA_CH36_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001248Cu)
+
+/** Alias (User Manual Name) for DMA_CH36_DADR.
+* To use register names with standard convension, please use DMA_CH36_DADR.
+*/
+#define DMA_DADR036 (DMA_CH36_DADR)
+
+/** \brief 2480, DMA Channel Read Data CRC Register */
+#define DMA_CH36_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012480u)
+
+/** Alias (User Manual Name) for DMA_CH36_RDCRCR.
+* To use register names with standard convension, please use DMA_CH36_RDCRCR.
+*/
+#define DMA_RDCRCR036 (DMA_CH36_RDCRCR)
+
+/** \brief 2488, DMA Channel Source Address Register */
+#define DMA_CH36_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012488u)
+
+/** Alias (User Manual Name) for DMA_CH36_SADR.
+* To use register names with standard convension, please use DMA_CH36_SADR.
+*/
+#define DMA_SADR036 (DMA_CH36_SADR)
+
+/** \brief 2484, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH36_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012484u)
+
+/** Alias (User Manual Name) for DMA_CH36_SDCRCR.
+* To use register names with standard convension, please use DMA_CH36_SDCRCR.
+*/
+#define DMA_SDCRCR036 (DMA_CH36_SDCRCR)
+
+/** \brief 2498, DMA Channel Shadow Address Register */
+#define DMA_CH36_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012498u)
+
+/** Alias (User Manual Name) for DMA_CH36_SHADR.
+* To use register names with standard convension, please use DMA_CH36_SHADR.
+*/
+#define DMA_SHADR036 (DMA_CH36_SHADR)
+
+/** \brief 24B0, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH37_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF00124B0u)
+
+/** Alias (User Manual Name) for DMA_CH37_ADICR.
+* To use register names with standard convension, please use DMA_CH37_ADICR.
+*/
+#define DMA_ADICR037 (DMA_CH37_ADICR)
+
+/** \brief 24B4, DMA Channel Configuration Register */
+#define DMA_CH37_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF00124B4u)
+
+/** Alias (User Manual Name) for DMA_CH37_CHCFGR.
+* To use register names with standard convension, please use DMA_CH37_CHCFGR.
+*/
+#define DMA_CHCFGR037 (DMA_CH37_CHCFGR)
+
+/** \brief 24BC, DMARAM Channel Control and Status Register */
+#define DMA_CH37_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF00124BCu)
+
+/** Alias (User Manual Name) for DMA_CH37_CHCSR.
+* To use register names with standard convension, please use DMA_CH37_CHCSR.
+*/
+#define DMA_CHCSR037 (DMA_CH37_CHCSR)
+
+/** \brief 24AC, DMA Channel Destination Address Register x */
+#define DMA_CH37_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF00124ACu)
+
+/** Alias (User Manual Name) for DMA_CH37_DADR.
+* To use register names with standard convension, please use DMA_CH37_DADR.
+*/
+#define DMA_DADR037 (DMA_CH37_DADR)
+
+/** \brief 24A0, DMA Channel Read Data CRC Register */
+#define DMA_CH37_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF00124A0u)
+
+/** Alias (User Manual Name) for DMA_CH37_RDCRCR.
+* To use register names with standard convension, please use DMA_CH37_RDCRCR.
+*/
+#define DMA_RDCRCR037 (DMA_CH37_RDCRCR)
+
+/** \brief 24A8, DMA Channel Source Address Register */
+#define DMA_CH37_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF00124A8u)
+
+/** Alias (User Manual Name) for DMA_CH37_SADR.
+* To use register names with standard convension, please use DMA_CH37_SADR.
+*/
+#define DMA_SADR037 (DMA_CH37_SADR)
+
+/** \brief 24A4, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH37_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF00124A4u)
+
+/** Alias (User Manual Name) for DMA_CH37_SDCRCR.
+* To use register names with standard convension, please use DMA_CH37_SDCRCR.
+*/
+#define DMA_SDCRCR037 (DMA_CH37_SDCRCR)
+
+/** \brief 24B8, DMA Channel Shadow Address Register */
+#define DMA_CH37_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF00124B8u)
+
+/** Alias (User Manual Name) for DMA_CH37_SHADR.
+* To use register names with standard convension, please use DMA_CH37_SHADR.
+*/
+#define DMA_SHADR037 (DMA_CH37_SHADR)
+
+/** \brief 24D0, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH38_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF00124D0u)
+
+/** Alias (User Manual Name) for DMA_CH38_ADICR.
+* To use register names with standard convension, please use DMA_CH38_ADICR.
+*/
+#define DMA_ADICR038 (DMA_CH38_ADICR)
+
+/** \brief 24D4, DMA Channel Configuration Register */
+#define DMA_CH38_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF00124D4u)
+
+/** Alias (User Manual Name) for DMA_CH38_CHCFGR.
+* To use register names with standard convension, please use DMA_CH38_CHCFGR.
+*/
+#define DMA_CHCFGR038 (DMA_CH38_CHCFGR)
+
+/** \brief 24DC, DMARAM Channel Control and Status Register */
+#define DMA_CH38_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF00124DCu)
+
+/** Alias (User Manual Name) for DMA_CH38_CHCSR.
+* To use register names with standard convension, please use DMA_CH38_CHCSR.
+*/
+#define DMA_CHCSR038 (DMA_CH38_CHCSR)
+
+/** \brief 24CC, DMA Channel Destination Address Register x */
+#define DMA_CH38_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF00124CCu)
+
+/** Alias (User Manual Name) for DMA_CH38_DADR.
+* To use register names with standard convension, please use DMA_CH38_DADR.
+*/
+#define DMA_DADR038 (DMA_CH38_DADR)
+
+/** \brief 24C0, DMA Channel Read Data CRC Register */
+#define DMA_CH38_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF00124C0u)
+
+/** Alias (User Manual Name) for DMA_CH38_RDCRCR.
+* To use register names with standard convension, please use DMA_CH38_RDCRCR.
+*/
+#define DMA_RDCRCR038 (DMA_CH38_RDCRCR)
+
+/** \brief 24C8, DMA Channel Source Address Register */
+#define DMA_CH38_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF00124C8u)
+
+/** Alias (User Manual Name) for DMA_CH38_SADR.
+* To use register names with standard convension, please use DMA_CH38_SADR.
+*/
+#define DMA_SADR038 (DMA_CH38_SADR)
+
+/** \brief 24C4, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH38_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF00124C4u)
+
+/** Alias (User Manual Name) for DMA_CH38_SDCRCR.
+* To use register names with standard convension, please use DMA_CH38_SDCRCR.
+*/
+#define DMA_SDCRCR038 (DMA_CH38_SDCRCR)
+
+/** \brief 24D8, DMA Channel Shadow Address Register */
+#define DMA_CH38_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF00124D8u)
+
+/** Alias (User Manual Name) for DMA_CH38_SHADR.
+* To use register names with standard convension, please use DMA_CH38_SHADR.
+*/
+#define DMA_SHADR038 (DMA_CH38_SHADR)
+
+/** \brief 24F0, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH39_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF00124F0u)
+
+/** Alias (User Manual Name) for DMA_CH39_ADICR.
+* To use register names with standard convension, please use DMA_CH39_ADICR.
+*/
+#define DMA_ADICR039 (DMA_CH39_ADICR)
+
+/** \brief 24F4, DMA Channel Configuration Register */
+#define DMA_CH39_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF00124F4u)
+
+/** Alias (User Manual Name) for DMA_CH39_CHCFGR.
+* To use register names with standard convension, please use DMA_CH39_CHCFGR.
+*/
+#define DMA_CHCFGR039 (DMA_CH39_CHCFGR)
+
+/** \brief 24FC, DMARAM Channel Control and Status Register */
+#define DMA_CH39_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF00124FCu)
+
+/** Alias (User Manual Name) for DMA_CH39_CHCSR.
+* To use register names with standard convension, please use DMA_CH39_CHCSR.
+*/
+#define DMA_CHCSR039 (DMA_CH39_CHCSR)
+
+/** \brief 24EC, DMA Channel Destination Address Register x */
+#define DMA_CH39_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF00124ECu)
+
+/** Alias (User Manual Name) for DMA_CH39_DADR.
+* To use register names with standard convension, please use DMA_CH39_DADR.
+*/
+#define DMA_DADR039 (DMA_CH39_DADR)
+
+/** \brief 24E0, DMA Channel Read Data CRC Register */
+#define DMA_CH39_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF00124E0u)
+
+/** Alias (User Manual Name) for DMA_CH39_RDCRCR.
+* To use register names with standard convension, please use DMA_CH39_RDCRCR.
+*/
+#define DMA_RDCRCR039 (DMA_CH39_RDCRCR)
+
+/** \brief 24E8, DMA Channel Source Address Register */
+#define DMA_CH39_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF00124E8u)
+
+/** Alias (User Manual Name) for DMA_CH39_SADR.
+* To use register names with standard convension, please use DMA_CH39_SADR.
+*/
+#define DMA_SADR039 (DMA_CH39_SADR)
+
+/** \brief 24E4, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH39_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF00124E4u)
+
+/** Alias (User Manual Name) for DMA_CH39_SDCRCR.
+* To use register names with standard convension, please use DMA_CH39_SDCRCR.
+*/
+#define DMA_SDCRCR039 (DMA_CH39_SDCRCR)
+
+/** \brief 24F8, DMA Channel Shadow Address Register */
+#define DMA_CH39_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF00124F8u)
+
+/** Alias (User Manual Name) for DMA_CH39_SHADR.
+* To use register names with standard convension, please use DMA_CH39_SHADR.
+*/
+#define DMA_SHADR039 (DMA_CH39_SHADR)
+
+/** \brief 2070, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH3_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012070u)
+
+/** Alias (User Manual Name) for DMA_CH3_ADICR.
+* To use register names with standard convension, please use DMA_CH3_ADICR.
+*/
+#define DMA_ADICR003 (DMA_CH3_ADICR)
+
+/** \brief 2074, DMA Channel Configuration Register */
+#define DMA_CH3_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012074u)
+
+/** Alias (User Manual Name) for DMA_CH3_CHCFGR.
+* To use register names with standard convension, please use DMA_CH3_CHCFGR.
+*/
+#define DMA_CHCFGR003 (DMA_CH3_CHCFGR)
+
+/** \brief 207C, DMARAM Channel Control and Status Register */
+#define DMA_CH3_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001207Cu)
+
+/** Alias (User Manual Name) for DMA_CH3_CHCSR.
+* To use register names with standard convension, please use DMA_CH3_CHCSR.
+*/
+#define DMA_CHCSR003 (DMA_CH3_CHCSR)
+
+/** \brief 206C, DMA Channel Destination Address Register x */
+#define DMA_CH3_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001206Cu)
+
+/** Alias (User Manual Name) for DMA_CH3_DADR.
+* To use register names with standard convension, please use DMA_CH3_DADR.
+*/
+#define DMA_DADR003 (DMA_CH3_DADR)
+
+/** \brief 2060, DMA Channel Read Data CRC Register */
+#define DMA_CH3_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012060u)
+
+/** Alias (User Manual Name) for DMA_CH3_RDCRCR.
+* To use register names with standard convension, please use DMA_CH3_RDCRCR.
+*/
+#define DMA_RDCRCR003 (DMA_CH3_RDCRCR)
+
+/** \brief 2068, DMA Channel Source Address Register */
+#define DMA_CH3_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012068u)
+
+/** Alias (User Manual Name) for DMA_CH3_SADR.
+* To use register names with standard convension, please use DMA_CH3_SADR.
+*/
+#define DMA_SADR003 (DMA_CH3_SADR)
+
+/** \brief 2064, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH3_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012064u)
+
+/** Alias (User Manual Name) for DMA_CH3_SDCRCR.
+* To use register names with standard convension, please use DMA_CH3_SDCRCR.
+*/
+#define DMA_SDCRCR003 (DMA_CH3_SDCRCR)
+
+/** \brief 2078, DMA Channel Shadow Address Register */
+#define DMA_CH3_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012078u)
+
+/** Alias (User Manual Name) for DMA_CH3_SHADR.
+* To use register names with standard convension, please use DMA_CH3_SHADR.
+*/
+#define DMA_SHADR003 (DMA_CH3_SHADR)
+
+/** \brief 2510, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH40_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012510u)
+
+/** Alias (User Manual Name) for DMA_CH40_ADICR.
+* To use register names with standard convension, please use DMA_CH40_ADICR.
+*/
+#define DMA_ADICR040 (DMA_CH40_ADICR)
+
+/** \brief 2514, DMA Channel Configuration Register */
+#define DMA_CH40_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012514u)
+
+/** Alias (User Manual Name) for DMA_CH40_CHCFGR.
+* To use register names with standard convension, please use DMA_CH40_CHCFGR.
+*/
+#define DMA_CHCFGR040 (DMA_CH40_CHCFGR)
+
+/** \brief 251C, DMARAM Channel Control and Status Register */
+#define DMA_CH40_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001251Cu)
+
+/** Alias (User Manual Name) for DMA_CH40_CHCSR.
+* To use register names with standard convension, please use DMA_CH40_CHCSR.
+*/
+#define DMA_CHCSR040 (DMA_CH40_CHCSR)
+
+/** \brief 250C, DMA Channel Destination Address Register x */
+#define DMA_CH40_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001250Cu)
+
+/** Alias (User Manual Name) for DMA_CH40_DADR.
+* To use register names with standard convension, please use DMA_CH40_DADR.
+*/
+#define DMA_DADR040 (DMA_CH40_DADR)
+
+/** \brief 2500, DMA Channel Read Data CRC Register */
+#define DMA_CH40_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012500u)
+
+/** Alias (User Manual Name) for DMA_CH40_RDCRCR.
+* To use register names with standard convension, please use DMA_CH40_RDCRCR.
+*/
+#define DMA_RDCRCR040 (DMA_CH40_RDCRCR)
+
+/** \brief 2508, DMA Channel Source Address Register */
+#define DMA_CH40_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012508u)
+
+/** Alias (User Manual Name) for DMA_CH40_SADR.
+* To use register names with standard convension, please use DMA_CH40_SADR.
+*/
+#define DMA_SADR040 (DMA_CH40_SADR)
+
+/** \brief 2504, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH40_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012504u)
+
+/** Alias (User Manual Name) for DMA_CH40_SDCRCR.
+* To use register names with standard convension, please use DMA_CH40_SDCRCR.
+*/
+#define DMA_SDCRCR040 (DMA_CH40_SDCRCR)
+
+/** \brief 2518, DMA Channel Shadow Address Register */
+#define DMA_CH40_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012518u)
+
+/** Alias (User Manual Name) for DMA_CH40_SHADR.
+* To use register names with standard convension, please use DMA_CH40_SHADR.
+*/
+#define DMA_SHADR040 (DMA_CH40_SHADR)
+
+/** \brief 2530, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH41_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012530u)
+
+/** Alias (User Manual Name) for DMA_CH41_ADICR.
+* To use register names with standard convension, please use DMA_CH41_ADICR.
+*/
+#define DMA_ADICR041 (DMA_CH41_ADICR)
+
+/** \brief 2534, DMA Channel Configuration Register */
+#define DMA_CH41_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012534u)
+
+/** Alias (User Manual Name) for DMA_CH41_CHCFGR.
+* To use register names with standard convension, please use DMA_CH41_CHCFGR.
+*/
+#define DMA_CHCFGR041 (DMA_CH41_CHCFGR)
+
+/** \brief 253C, DMARAM Channel Control and Status Register */
+#define DMA_CH41_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001253Cu)
+
+/** Alias (User Manual Name) for DMA_CH41_CHCSR.
+* To use register names with standard convension, please use DMA_CH41_CHCSR.
+*/
+#define DMA_CHCSR041 (DMA_CH41_CHCSR)
+
+/** \brief 252C, DMA Channel Destination Address Register x */
+#define DMA_CH41_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001252Cu)
+
+/** Alias (User Manual Name) for DMA_CH41_DADR.
+* To use register names with standard convension, please use DMA_CH41_DADR.
+*/
+#define DMA_DADR041 (DMA_CH41_DADR)
+
+/** \brief 2520, DMA Channel Read Data CRC Register */
+#define DMA_CH41_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012520u)
+
+/** Alias (User Manual Name) for DMA_CH41_RDCRCR.
+* To use register names with standard convension, please use DMA_CH41_RDCRCR.
+*/
+#define DMA_RDCRCR041 (DMA_CH41_RDCRCR)
+
+/** \brief 2528, DMA Channel Source Address Register */
+#define DMA_CH41_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012528u)
+
+/** Alias (User Manual Name) for DMA_CH41_SADR.
+* To use register names with standard convension, please use DMA_CH41_SADR.
+*/
+#define DMA_SADR041 (DMA_CH41_SADR)
+
+/** \brief 2524, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH41_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012524u)
+
+/** Alias (User Manual Name) for DMA_CH41_SDCRCR.
+* To use register names with standard convension, please use DMA_CH41_SDCRCR.
+*/
+#define DMA_SDCRCR041 (DMA_CH41_SDCRCR)
+
+/** \brief 2538, DMA Channel Shadow Address Register */
+#define DMA_CH41_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012538u)
+
+/** Alias (User Manual Name) for DMA_CH41_SHADR.
+* To use register names with standard convension, please use DMA_CH41_SHADR.
+*/
+#define DMA_SHADR041 (DMA_CH41_SHADR)
+
+/** \brief 2550, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH42_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012550u)
+
+/** Alias (User Manual Name) for DMA_CH42_ADICR.
+* To use register names with standard convension, please use DMA_CH42_ADICR.
+*/
+#define DMA_ADICR042 (DMA_CH42_ADICR)
+
+/** \brief 2554, DMA Channel Configuration Register */
+#define DMA_CH42_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012554u)
+
+/** Alias (User Manual Name) for DMA_CH42_CHCFGR.
+* To use register names with standard convension, please use DMA_CH42_CHCFGR.
+*/
+#define DMA_CHCFGR042 (DMA_CH42_CHCFGR)
+
+/** \brief 255C, DMARAM Channel Control and Status Register */
+#define DMA_CH42_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001255Cu)
+
+/** Alias (User Manual Name) for DMA_CH42_CHCSR.
+* To use register names with standard convension, please use DMA_CH42_CHCSR.
+*/
+#define DMA_CHCSR042 (DMA_CH42_CHCSR)
+
+/** \brief 254C, DMA Channel Destination Address Register x */
+#define DMA_CH42_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001254Cu)
+
+/** Alias (User Manual Name) for DMA_CH42_DADR.
+* To use register names with standard convension, please use DMA_CH42_DADR.
+*/
+#define DMA_DADR042 (DMA_CH42_DADR)
+
+/** \brief 2540, DMA Channel Read Data CRC Register */
+#define DMA_CH42_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012540u)
+
+/** Alias (User Manual Name) for DMA_CH42_RDCRCR.
+* To use register names with standard convension, please use DMA_CH42_RDCRCR.
+*/
+#define DMA_RDCRCR042 (DMA_CH42_RDCRCR)
+
+/** \brief 2548, DMA Channel Source Address Register */
+#define DMA_CH42_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012548u)
+
+/** Alias (User Manual Name) for DMA_CH42_SADR.
+* To use register names with standard convension, please use DMA_CH42_SADR.
+*/
+#define DMA_SADR042 (DMA_CH42_SADR)
+
+/** \brief 2544, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH42_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012544u)
+
+/** Alias (User Manual Name) for DMA_CH42_SDCRCR.
+* To use register names with standard convension, please use DMA_CH42_SDCRCR.
+*/
+#define DMA_SDCRCR042 (DMA_CH42_SDCRCR)
+
+/** \brief 2558, DMA Channel Shadow Address Register */
+#define DMA_CH42_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012558u)
+
+/** Alias (User Manual Name) for DMA_CH42_SHADR.
+* To use register names with standard convension, please use DMA_CH42_SHADR.
+*/
+#define DMA_SHADR042 (DMA_CH42_SHADR)
+
+/** \brief 2570, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH43_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012570u)
+
+/** Alias (User Manual Name) for DMA_CH43_ADICR.
+* To use register names with standard convension, please use DMA_CH43_ADICR.
+*/
+#define DMA_ADICR043 (DMA_CH43_ADICR)
+
+/** \brief 2574, DMA Channel Configuration Register */
+#define DMA_CH43_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012574u)
+
+/** Alias (User Manual Name) for DMA_CH43_CHCFGR.
+* To use register names with standard convension, please use DMA_CH43_CHCFGR.
+*/
+#define DMA_CHCFGR043 (DMA_CH43_CHCFGR)
+
+/** \brief 257C, DMARAM Channel Control and Status Register */
+#define DMA_CH43_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001257Cu)
+
+/** Alias (User Manual Name) for DMA_CH43_CHCSR.
+* To use register names with standard convension, please use DMA_CH43_CHCSR.
+*/
+#define DMA_CHCSR043 (DMA_CH43_CHCSR)
+
+/** \brief 256C, DMA Channel Destination Address Register x */
+#define DMA_CH43_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001256Cu)
+
+/** Alias (User Manual Name) for DMA_CH43_DADR.
+* To use register names with standard convension, please use DMA_CH43_DADR.
+*/
+#define DMA_DADR043 (DMA_CH43_DADR)
+
+/** \brief 2560, DMA Channel Read Data CRC Register */
+#define DMA_CH43_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012560u)
+
+/** Alias (User Manual Name) for DMA_CH43_RDCRCR.
+* To use register names with standard convension, please use DMA_CH43_RDCRCR.
+*/
+#define DMA_RDCRCR043 (DMA_CH43_RDCRCR)
+
+/** \brief 2568, DMA Channel Source Address Register */
+#define DMA_CH43_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012568u)
+
+/** Alias (User Manual Name) for DMA_CH43_SADR.
+* To use register names with standard convension, please use DMA_CH43_SADR.
+*/
+#define DMA_SADR043 (DMA_CH43_SADR)
+
+/** \brief 2564, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH43_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012564u)
+
+/** Alias (User Manual Name) for DMA_CH43_SDCRCR.
+* To use register names with standard convension, please use DMA_CH43_SDCRCR.
+*/
+#define DMA_SDCRCR043 (DMA_CH43_SDCRCR)
+
+/** \brief 2578, DMA Channel Shadow Address Register */
+#define DMA_CH43_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012578u)
+
+/** Alias (User Manual Name) for DMA_CH43_SHADR.
+* To use register names with standard convension, please use DMA_CH43_SHADR.
+*/
+#define DMA_SHADR043 (DMA_CH43_SHADR)
+
+/** \brief 2590, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH44_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012590u)
+
+/** Alias (User Manual Name) for DMA_CH44_ADICR.
+* To use register names with standard convension, please use DMA_CH44_ADICR.
+*/
+#define DMA_ADICR044 (DMA_CH44_ADICR)
+
+/** \brief 2594, DMA Channel Configuration Register */
+#define DMA_CH44_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012594u)
+
+/** Alias (User Manual Name) for DMA_CH44_CHCFGR.
+* To use register names with standard convension, please use DMA_CH44_CHCFGR.
+*/
+#define DMA_CHCFGR044 (DMA_CH44_CHCFGR)
+
+/** \brief 259C, DMARAM Channel Control and Status Register */
+#define DMA_CH44_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001259Cu)
+
+/** Alias (User Manual Name) for DMA_CH44_CHCSR.
+* To use register names with standard convension, please use DMA_CH44_CHCSR.
+*/
+#define DMA_CHCSR044 (DMA_CH44_CHCSR)
+
+/** \brief 258C, DMA Channel Destination Address Register x */
+#define DMA_CH44_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001258Cu)
+
+/** Alias (User Manual Name) for DMA_CH44_DADR.
+* To use register names with standard convension, please use DMA_CH44_DADR.
+*/
+#define DMA_DADR044 (DMA_CH44_DADR)
+
+/** \brief 2580, DMA Channel Read Data CRC Register */
+#define DMA_CH44_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012580u)
+
+/** Alias (User Manual Name) for DMA_CH44_RDCRCR.
+* To use register names with standard convension, please use DMA_CH44_RDCRCR.
+*/
+#define DMA_RDCRCR044 (DMA_CH44_RDCRCR)
+
+/** \brief 2588, DMA Channel Source Address Register */
+#define DMA_CH44_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012588u)
+
+/** Alias (User Manual Name) for DMA_CH44_SADR.
+* To use register names with standard convension, please use DMA_CH44_SADR.
+*/
+#define DMA_SADR044 (DMA_CH44_SADR)
+
+/** \brief 2584, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH44_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012584u)
+
+/** Alias (User Manual Name) for DMA_CH44_SDCRCR.
+* To use register names with standard convension, please use DMA_CH44_SDCRCR.
+*/
+#define DMA_SDCRCR044 (DMA_CH44_SDCRCR)
+
+/** \brief 2598, DMA Channel Shadow Address Register */
+#define DMA_CH44_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012598u)
+
+/** Alias (User Manual Name) for DMA_CH44_SHADR.
+* To use register names with standard convension, please use DMA_CH44_SHADR.
+*/
+#define DMA_SHADR044 (DMA_CH44_SHADR)
+
+/** \brief 25B0, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH45_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF00125B0u)
+
+/** Alias (User Manual Name) for DMA_CH45_ADICR.
+* To use register names with standard convension, please use DMA_CH45_ADICR.
+*/
+#define DMA_ADICR045 (DMA_CH45_ADICR)
+
+/** \brief 25B4, DMA Channel Configuration Register */
+#define DMA_CH45_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF00125B4u)
+
+/** Alias (User Manual Name) for DMA_CH45_CHCFGR.
+* To use register names with standard convension, please use DMA_CH45_CHCFGR.
+*/
+#define DMA_CHCFGR045 (DMA_CH45_CHCFGR)
+
+/** \brief 25BC, DMARAM Channel Control and Status Register */
+#define DMA_CH45_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF00125BCu)
+
+/** Alias (User Manual Name) for DMA_CH45_CHCSR.
+* To use register names with standard convension, please use DMA_CH45_CHCSR.
+*/
+#define DMA_CHCSR045 (DMA_CH45_CHCSR)
+
+/** \brief 25AC, DMA Channel Destination Address Register x */
+#define DMA_CH45_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF00125ACu)
+
+/** Alias (User Manual Name) for DMA_CH45_DADR.
+* To use register names with standard convension, please use DMA_CH45_DADR.
+*/
+#define DMA_DADR045 (DMA_CH45_DADR)
+
+/** \brief 25A0, DMA Channel Read Data CRC Register */
+#define DMA_CH45_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF00125A0u)
+
+/** Alias (User Manual Name) for DMA_CH45_RDCRCR.
+* To use register names with standard convension, please use DMA_CH45_RDCRCR.
+*/
+#define DMA_RDCRCR045 (DMA_CH45_RDCRCR)
+
+/** \brief 25A8, DMA Channel Source Address Register */
+#define DMA_CH45_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF00125A8u)
+
+/** Alias (User Manual Name) for DMA_CH45_SADR.
+* To use register names with standard convension, please use DMA_CH45_SADR.
+*/
+#define DMA_SADR045 (DMA_CH45_SADR)
+
+/** \brief 25A4, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH45_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF00125A4u)
+
+/** Alias (User Manual Name) for DMA_CH45_SDCRCR.
+* To use register names with standard convension, please use DMA_CH45_SDCRCR.
+*/
+#define DMA_SDCRCR045 (DMA_CH45_SDCRCR)
+
+/** \brief 25B8, DMA Channel Shadow Address Register */
+#define DMA_CH45_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF00125B8u)
+
+/** Alias (User Manual Name) for DMA_CH45_SHADR.
+* To use register names with standard convension, please use DMA_CH45_SHADR.
+*/
+#define DMA_SHADR045 (DMA_CH45_SHADR)
+
+/** \brief 25D0, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH46_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF00125D0u)
+
+/** Alias (User Manual Name) for DMA_CH46_ADICR.
+* To use register names with standard convension, please use DMA_CH46_ADICR.
+*/
+#define DMA_ADICR046 (DMA_CH46_ADICR)
+
+/** \brief 25D4, DMA Channel Configuration Register */
+#define DMA_CH46_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF00125D4u)
+
+/** Alias (User Manual Name) for DMA_CH46_CHCFGR.
+* To use register names with standard convension, please use DMA_CH46_CHCFGR.
+*/
+#define DMA_CHCFGR046 (DMA_CH46_CHCFGR)
+
+/** \brief 25DC, DMARAM Channel Control and Status Register */
+#define DMA_CH46_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF00125DCu)
+
+/** Alias (User Manual Name) for DMA_CH46_CHCSR.
+* To use register names with standard convension, please use DMA_CH46_CHCSR.
+*/
+#define DMA_CHCSR046 (DMA_CH46_CHCSR)
+
+/** \brief 25CC, DMA Channel Destination Address Register x */
+#define DMA_CH46_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF00125CCu)
+
+/** Alias (User Manual Name) for DMA_CH46_DADR.
+* To use register names with standard convension, please use DMA_CH46_DADR.
+*/
+#define DMA_DADR046 (DMA_CH46_DADR)
+
+/** \brief 25C0, DMA Channel Read Data CRC Register */
+#define DMA_CH46_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF00125C0u)
+
+/** Alias (User Manual Name) for DMA_CH46_RDCRCR.
+* To use register names with standard convension, please use DMA_CH46_RDCRCR.
+*/
+#define DMA_RDCRCR046 (DMA_CH46_RDCRCR)
+
+/** \brief 25C8, DMA Channel Source Address Register */
+#define DMA_CH46_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF00125C8u)
+
+/** Alias (User Manual Name) for DMA_CH46_SADR.
+* To use register names with standard convension, please use DMA_CH46_SADR.
+*/
+#define DMA_SADR046 (DMA_CH46_SADR)
+
+/** \brief 25C4, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH46_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF00125C4u)
+
+/** Alias (User Manual Name) for DMA_CH46_SDCRCR.
+* To use register names with standard convension, please use DMA_CH46_SDCRCR.
+*/
+#define DMA_SDCRCR046 (DMA_CH46_SDCRCR)
+
+/** \brief 25D8, DMA Channel Shadow Address Register */
+#define DMA_CH46_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF00125D8u)
+
+/** Alias (User Manual Name) for DMA_CH46_SHADR.
+* To use register names with standard convension, please use DMA_CH46_SHADR.
+*/
+#define DMA_SHADR046 (DMA_CH46_SHADR)
+
+/** \brief 25F0, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH47_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF00125F0u)
+
+/** Alias (User Manual Name) for DMA_CH47_ADICR.
+* To use register names with standard convension, please use DMA_CH47_ADICR.
+*/
+#define DMA_ADICR047 (DMA_CH47_ADICR)
+
+/** \brief 25F4, DMA Channel Configuration Register */
+#define DMA_CH47_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF00125F4u)
+
+/** Alias (User Manual Name) for DMA_CH47_CHCFGR.
+* To use register names with standard convension, please use DMA_CH47_CHCFGR.
+*/
+#define DMA_CHCFGR047 (DMA_CH47_CHCFGR)
+
+/** \brief 25FC, DMARAM Channel Control and Status Register */
+#define DMA_CH47_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF00125FCu)
+
+/** Alias (User Manual Name) for DMA_CH47_CHCSR.
+* To use register names with standard convension, please use DMA_CH47_CHCSR.
+*/
+#define DMA_CHCSR047 (DMA_CH47_CHCSR)
+
+/** \brief 25EC, DMA Channel Destination Address Register x */
+#define DMA_CH47_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF00125ECu)
+
+/** Alias (User Manual Name) for DMA_CH47_DADR.
+* To use register names with standard convension, please use DMA_CH47_DADR.
+*/
+#define DMA_DADR047 (DMA_CH47_DADR)
+
+/** \brief 25E0, DMA Channel Read Data CRC Register */
+#define DMA_CH47_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF00125E0u)
+
+/** Alias (User Manual Name) for DMA_CH47_RDCRCR.
+* To use register names with standard convension, please use DMA_CH47_RDCRCR.
+*/
+#define DMA_RDCRCR047 (DMA_CH47_RDCRCR)
+
+/** \brief 25E8, DMA Channel Source Address Register */
+#define DMA_CH47_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF00125E8u)
+
+/** Alias (User Manual Name) for DMA_CH47_SADR.
+* To use register names with standard convension, please use DMA_CH47_SADR.
+*/
+#define DMA_SADR047 (DMA_CH47_SADR)
+
+/** \brief 25E4, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH47_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF00125E4u)
+
+/** Alias (User Manual Name) for DMA_CH47_SDCRCR.
+* To use register names with standard convension, please use DMA_CH47_SDCRCR.
+*/
+#define DMA_SDCRCR047 (DMA_CH47_SDCRCR)
+
+/** \brief 25F8, DMA Channel Shadow Address Register */
+#define DMA_CH47_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF00125F8u)
+
+/** Alias (User Manual Name) for DMA_CH47_SHADR.
+* To use register names with standard convension, please use DMA_CH47_SHADR.
+*/
+#define DMA_SHADR047 (DMA_CH47_SHADR)
+
+/** \brief 2090, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH4_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012090u)
+
+/** Alias (User Manual Name) for DMA_CH4_ADICR.
+* To use register names with standard convension, please use DMA_CH4_ADICR.
+*/
+#define DMA_ADICR004 (DMA_CH4_ADICR)
+
+/** \brief 2094, DMA Channel Configuration Register */
+#define DMA_CH4_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012094u)
+
+/** Alias (User Manual Name) for DMA_CH4_CHCFGR.
+* To use register names with standard convension, please use DMA_CH4_CHCFGR.
+*/
+#define DMA_CHCFGR004 (DMA_CH4_CHCFGR)
+
+/** \brief 209C, DMARAM Channel Control and Status Register */
+#define DMA_CH4_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001209Cu)
+
+/** Alias (User Manual Name) for DMA_CH4_CHCSR.
+* To use register names with standard convension, please use DMA_CH4_CHCSR.
+*/
+#define DMA_CHCSR004 (DMA_CH4_CHCSR)
+
+/** \brief 208C, DMA Channel Destination Address Register x */
+#define DMA_CH4_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001208Cu)
+
+/** Alias (User Manual Name) for DMA_CH4_DADR.
+* To use register names with standard convension, please use DMA_CH4_DADR.
+*/
+#define DMA_DADR004 (DMA_CH4_DADR)
+
+/** \brief 2080, DMA Channel Read Data CRC Register */
+#define DMA_CH4_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012080u)
+
+/** Alias (User Manual Name) for DMA_CH4_RDCRCR.
+* To use register names with standard convension, please use DMA_CH4_RDCRCR.
+*/
+#define DMA_RDCRCR004 (DMA_CH4_RDCRCR)
+
+/** \brief 2088, DMA Channel Source Address Register */
+#define DMA_CH4_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012088u)
+
+/** Alias (User Manual Name) for DMA_CH4_SADR.
+* To use register names with standard convension, please use DMA_CH4_SADR.
+*/
+#define DMA_SADR004 (DMA_CH4_SADR)
+
+/** \brief 2084, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH4_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012084u)
+
+/** Alias (User Manual Name) for DMA_CH4_SDCRCR.
+* To use register names with standard convension, please use DMA_CH4_SDCRCR.
+*/
+#define DMA_SDCRCR004 (DMA_CH4_SDCRCR)
+
+/** \brief 2098, DMA Channel Shadow Address Register */
+#define DMA_CH4_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012098u)
+
+/** Alias (User Manual Name) for DMA_CH4_SHADR.
+* To use register names with standard convension, please use DMA_CH4_SHADR.
+*/
+#define DMA_SHADR004 (DMA_CH4_SHADR)
+
+/** \brief 20B0, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH5_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF00120B0u)
+
+/** Alias (User Manual Name) for DMA_CH5_ADICR.
+* To use register names with standard convension, please use DMA_CH5_ADICR.
+*/
+#define DMA_ADICR005 (DMA_CH5_ADICR)
+
+/** \brief 20B4, DMA Channel Configuration Register */
+#define DMA_CH5_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF00120B4u)
+
+/** Alias (User Manual Name) for DMA_CH5_CHCFGR.
+* To use register names with standard convension, please use DMA_CH5_CHCFGR.
+*/
+#define DMA_CHCFGR005 (DMA_CH5_CHCFGR)
+
+/** \brief 20BC, DMARAM Channel Control and Status Register */
+#define DMA_CH5_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF00120BCu)
+
+/** Alias (User Manual Name) for DMA_CH5_CHCSR.
+* To use register names with standard convension, please use DMA_CH5_CHCSR.
+*/
+#define DMA_CHCSR005 (DMA_CH5_CHCSR)
+
+/** \brief 20AC, DMA Channel Destination Address Register x */
+#define DMA_CH5_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF00120ACu)
+
+/** Alias (User Manual Name) for DMA_CH5_DADR.
+* To use register names with standard convension, please use DMA_CH5_DADR.
+*/
+#define DMA_DADR005 (DMA_CH5_DADR)
+
+/** \brief 20A0, DMA Channel Read Data CRC Register */
+#define DMA_CH5_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF00120A0u)
+
+/** Alias (User Manual Name) for DMA_CH5_RDCRCR.
+* To use register names with standard convension, please use DMA_CH5_RDCRCR.
+*/
+#define DMA_RDCRCR005 (DMA_CH5_RDCRCR)
+
+/** \brief 20A8, DMA Channel Source Address Register */
+#define DMA_CH5_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF00120A8u)
+
+/** Alias (User Manual Name) for DMA_CH5_SADR.
+* To use register names with standard convension, please use DMA_CH5_SADR.
+*/
+#define DMA_SADR005 (DMA_CH5_SADR)
+
+/** \brief 20A4, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH5_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF00120A4u)
+
+/** Alias (User Manual Name) for DMA_CH5_SDCRCR.
+* To use register names with standard convension, please use DMA_CH5_SDCRCR.
+*/
+#define DMA_SDCRCR005 (DMA_CH5_SDCRCR)
+
+/** \brief 20B8, DMA Channel Shadow Address Register */
+#define DMA_CH5_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF00120B8u)
+
+/** Alias (User Manual Name) for DMA_CH5_SHADR.
+* To use register names with standard convension, please use DMA_CH5_SHADR.
+*/
+#define DMA_SHADR005 (DMA_CH5_SHADR)
+
+/** \brief 20D0, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH6_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF00120D0u)
+
+/** Alias (User Manual Name) for DMA_CH6_ADICR.
+* To use register names with standard convension, please use DMA_CH6_ADICR.
+*/
+#define DMA_ADICR006 (DMA_CH6_ADICR)
+
+/** \brief 20D4, DMA Channel Configuration Register */
+#define DMA_CH6_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF00120D4u)
+
+/** Alias (User Manual Name) for DMA_CH6_CHCFGR.
+* To use register names with standard convension, please use DMA_CH6_CHCFGR.
+*/
+#define DMA_CHCFGR006 (DMA_CH6_CHCFGR)
+
+/** \brief 20DC, DMARAM Channel Control and Status Register */
+#define DMA_CH6_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF00120DCu)
+
+/** Alias (User Manual Name) for DMA_CH6_CHCSR.
+* To use register names with standard convension, please use DMA_CH6_CHCSR.
+*/
+#define DMA_CHCSR006 (DMA_CH6_CHCSR)
+
+/** \brief 20CC, DMA Channel Destination Address Register x */
+#define DMA_CH6_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF00120CCu)
+
+/** Alias (User Manual Name) for DMA_CH6_DADR.
+* To use register names with standard convension, please use DMA_CH6_DADR.
+*/
+#define DMA_DADR006 (DMA_CH6_DADR)
+
+/** \brief 20C0, DMA Channel Read Data CRC Register */
+#define DMA_CH6_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF00120C0u)
+
+/** Alias (User Manual Name) for DMA_CH6_RDCRCR.
+* To use register names with standard convension, please use DMA_CH6_RDCRCR.
+*/
+#define DMA_RDCRCR006 (DMA_CH6_RDCRCR)
+
+/** \brief 20C8, DMA Channel Source Address Register */
+#define DMA_CH6_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF00120C8u)
+
+/** Alias (User Manual Name) for DMA_CH6_SADR.
+* To use register names with standard convension, please use DMA_CH6_SADR.
+*/
+#define DMA_SADR006 (DMA_CH6_SADR)
+
+/** \brief 20C4, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH6_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF00120C4u)
+
+/** Alias (User Manual Name) for DMA_CH6_SDCRCR.
+* To use register names with standard convension, please use DMA_CH6_SDCRCR.
+*/
+#define DMA_SDCRCR006 (DMA_CH6_SDCRCR)
+
+/** \brief 20D8, DMA Channel Shadow Address Register */
+#define DMA_CH6_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF00120D8u)
+
+/** Alias (User Manual Name) for DMA_CH6_SHADR.
+* To use register names with standard convension, please use DMA_CH6_SHADR.
+*/
+#define DMA_SHADR006 (DMA_CH6_SHADR)
+
+/** \brief 20F0, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH7_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF00120F0u)
+
+/** Alias (User Manual Name) for DMA_CH7_ADICR.
+* To use register names with standard convension, please use DMA_CH7_ADICR.
+*/
+#define DMA_ADICR007 (DMA_CH7_ADICR)
+
+/** \brief 20F4, DMA Channel Configuration Register */
+#define DMA_CH7_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF00120F4u)
+
+/** Alias (User Manual Name) for DMA_CH7_CHCFGR.
+* To use register names with standard convension, please use DMA_CH7_CHCFGR.
+*/
+#define DMA_CHCFGR007 (DMA_CH7_CHCFGR)
+
+/** \brief 20FC, DMARAM Channel Control and Status Register */
+#define DMA_CH7_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF00120FCu)
+
+/** Alias (User Manual Name) for DMA_CH7_CHCSR.
+* To use register names with standard convension, please use DMA_CH7_CHCSR.
+*/
+#define DMA_CHCSR007 (DMA_CH7_CHCSR)
+
+/** \brief 20EC, DMA Channel Destination Address Register x */
+#define DMA_CH7_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF00120ECu)
+
+/** Alias (User Manual Name) for DMA_CH7_DADR.
+* To use register names with standard convension, please use DMA_CH7_DADR.
+*/
+#define DMA_DADR007 (DMA_CH7_DADR)
+
+/** \brief 20E0, DMA Channel Read Data CRC Register */
+#define DMA_CH7_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF00120E0u)
+
+/** Alias (User Manual Name) for DMA_CH7_RDCRCR.
+* To use register names with standard convension, please use DMA_CH7_RDCRCR.
+*/
+#define DMA_RDCRCR007 (DMA_CH7_RDCRCR)
+
+/** \brief 20E8, DMA Channel Source Address Register */
+#define DMA_CH7_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF00120E8u)
+
+/** Alias (User Manual Name) for DMA_CH7_SADR.
+* To use register names with standard convension, please use DMA_CH7_SADR.
+*/
+#define DMA_SADR007 (DMA_CH7_SADR)
+
+/** \brief 20E4, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH7_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF00120E4u)
+
+/** Alias (User Manual Name) for DMA_CH7_SDCRCR.
+* To use register names with standard convension, please use DMA_CH7_SDCRCR.
+*/
+#define DMA_SDCRCR007 (DMA_CH7_SDCRCR)
+
+/** \brief 20F8, DMA Channel Shadow Address Register */
+#define DMA_CH7_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF00120F8u)
+
+/** Alias (User Manual Name) for DMA_CH7_SHADR.
+* To use register names with standard convension, please use DMA_CH7_SHADR.
+*/
+#define DMA_SHADR007 (DMA_CH7_SHADR)
+
+/** \brief 2110, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH8_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012110u)
+
+/** Alias (User Manual Name) for DMA_CH8_ADICR.
+* To use register names with standard convension, please use DMA_CH8_ADICR.
+*/
+#define DMA_ADICR008 (DMA_CH8_ADICR)
+
+/** \brief 2114, DMA Channel Configuration Register */
+#define DMA_CH8_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012114u)
+
+/** Alias (User Manual Name) for DMA_CH8_CHCFGR.
+* To use register names with standard convension, please use DMA_CH8_CHCFGR.
+*/
+#define DMA_CHCFGR008 (DMA_CH8_CHCFGR)
+
+/** \brief 211C, DMARAM Channel Control and Status Register */
+#define DMA_CH8_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001211Cu)
+
+/** Alias (User Manual Name) for DMA_CH8_CHCSR.
+* To use register names with standard convension, please use DMA_CH8_CHCSR.
+*/
+#define DMA_CHCSR008 (DMA_CH8_CHCSR)
+
+/** \brief 210C, DMA Channel Destination Address Register x */
+#define DMA_CH8_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001210Cu)
+
+/** Alias (User Manual Name) for DMA_CH8_DADR.
+* To use register names with standard convension, please use DMA_CH8_DADR.
+*/
+#define DMA_DADR008 (DMA_CH8_DADR)
+
+/** \brief 2100, DMA Channel Read Data CRC Register */
+#define DMA_CH8_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012100u)
+
+/** Alias (User Manual Name) for DMA_CH8_RDCRCR.
+* To use register names with standard convension, please use DMA_CH8_RDCRCR.
+*/
+#define DMA_RDCRCR008 (DMA_CH8_RDCRCR)
+
+/** \brief 2108, DMA Channel Source Address Register */
+#define DMA_CH8_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012108u)
+
+/** Alias (User Manual Name) for DMA_CH8_SADR.
+* To use register names with standard convension, please use DMA_CH8_SADR.
+*/
+#define DMA_SADR008 (DMA_CH8_SADR)
+
+/** \brief 2104, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH8_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012104u)
+
+/** Alias (User Manual Name) for DMA_CH8_SDCRCR.
+* To use register names with standard convension, please use DMA_CH8_SDCRCR.
+*/
+#define DMA_SDCRCR008 (DMA_CH8_SDCRCR)
+
+/** \brief 2118, DMA Channel Shadow Address Register */
+#define DMA_CH8_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012118u)
+
+/** Alias (User Manual Name) for DMA_CH8_SHADR.
+* To use register names with standard convension, please use DMA_CH8_SHADR.
+*/
+#define DMA_SHADR008 (DMA_CH8_SHADR)
+
+/** \brief 2130, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH9_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012130u)
+
+/** Alias (User Manual Name) for DMA_CH9_ADICR.
+* To use register names with standard convension, please use DMA_CH9_ADICR.
+*/
+#define DMA_ADICR009 (DMA_CH9_ADICR)
+
+/** \brief 2134, DMA Channel Configuration Register */
+#define DMA_CH9_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012134u)
+
+/** Alias (User Manual Name) for DMA_CH9_CHCFGR.
+* To use register names with standard convension, please use DMA_CH9_CHCFGR.
+*/
+#define DMA_CHCFGR009 (DMA_CH9_CHCFGR)
+
+/** \brief 213C, DMARAM Channel Control and Status Register */
+#define DMA_CH9_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001213Cu)
+
+/** Alias (User Manual Name) for DMA_CH9_CHCSR.
+* To use register names with standard convension, please use DMA_CH9_CHCSR.
+*/
+#define DMA_CHCSR009 (DMA_CH9_CHCSR)
+
+/** \brief 212C, DMA Channel Destination Address Register x */
+#define DMA_CH9_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001212Cu)
+
+/** Alias (User Manual Name) for DMA_CH9_DADR.
+* To use register names with standard convension, please use DMA_CH9_DADR.
+*/
+#define DMA_DADR009 (DMA_CH9_DADR)
+
+/** \brief 2120, DMA Channel Read Data CRC Register */
+#define DMA_CH9_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012120u)
+
+/** Alias (User Manual Name) for DMA_CH9_RDCRCR.
+* To use register names with standard convension, please use DMA_CH9_RDCRCR.
+*/
+#define DMA_RDCRCR009 (DMA_CH9_RDCRCR)
+
+/** \brief 2128, DMA Channel Source Address Register */
+#define DMA_CH9_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012128u)
+
+/** Alias (User Manual Name) for DMA_CH9_SADR.
+* To use register names with standard convension, please use DMA_CH9_SADR.
+*/
+#define DMA_SADR009 (DMA_CH9_SADR)
+
+/** \brief 2124, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH9_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012124u)
+
+/** Alias (User Manual Name) for DMA_CH9_SDCRCR.
+* To use register names with standard convension, please use DMA_CH9_SDCRCR.
+*/
+#define DMA_SDCRCR009 (DMA_CH9_SDCRCR)
+
+/** \brief 2138, DMA Channel Shadow Address Register */
+#define DMA_CH9_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012138u)
+
+/** Alias (User Manual Name) for DMA_CH9_SHADR.
+* To use register names with standard convension, please use DMA_CH9_SHADR.
+*/
+#define DMA_SHADR009 (DMA_CH9_SHADR)
+
+/** \brief 0, DMA Clock Control Register */
+#define DMA_CLC /*lint --e(923)*/ (*(volatile Ifx_DMA_CLC*)0xF0010000u)
+
+/** \brief 1204, DMA Error Interrupt Set Register */
+#define DMA_ERRINTR /*lint --e(923)*/ (*(volatile Ifx_DMA_ERRINTR*)0xF0011204u)
+
+/** \brief 1800, DMA Channel Hardware Resource Register */
+#define DMA_HRR0 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011800u)
+
+/** Alias (User Manual Name) for DMA_HRR0.
+* To use register names with standard convension, please use DMA_HRR0.
+*/
+#define DMA_HRR000 (DMA_HRR0)
+
+/** \brief 1804, DMA Channel Hardware Resource Register */
+#define DMA_HRR1 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011804u)
+
+/** Alias (User Manual Name) for DMA_HRR1.
+* To use register names with standard convension, please use DMA_HRR1.
+*/
+#define DMA_HRR001 (DMA_HRR1)
+
+/** \brief 1828, DMA Channel Hardware Resource Register */
+#define DMA_HRR10 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011828u)
+
+/** Alias (User Manual Name) for DMA_HRR10.
+* To use register names with standard convension, please use DMA_HRR10.
+*/
+#define DMA_HRR010 (DMA_HRR10)
+
+/** \brief 182C, DMA Channel Hardware Resource Register */
+#define DMA_HRR11 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF001182Cu)
+
+/** Alias (User Manual Name) for DMA_HRR11.
+* To use register names with standard convension, please use DMA_HRR11.
+*/
+#define DMA_HRR011 (DMA_HRR11)
+
+/** \brief 1830, DMA Channel Hardware Resource Register */
+#define DMA_HRR12 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011830u)
+
+/** Alias (User Manual Name) for DMA_HRR12.
+* To use register names with standard convension, please use DMA_HRR12.
+*/
+#define DMA_HRR012 (DMA_HRR12)
+
+/** \brief 1834, DMA Channel Hardware Resource Register */
+#define DMA_HRR13 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011834u)
+
+/** Alias (User Manual Name) for DMA_HRR13.
+* To use register names with standard convension, please use DMA_HRR13.
+*/
+#define DMA_HRR013 (DMA_HRR13)
+
+/** \brief 1838, DMA Channel Hardware Resource Register */
+#define DMA_HRR14 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011838u)
+
+/** Alias (User Manual Name) for DMA_HRR14.
+* To use register names with standard convension, please use DMA_HRR14.
+*/
+#define DMA_HRR014 (DMA_HRR14)
+
+/** \brief 183C, DMA Channel Hardware Resource Register */
+#define DMA_HRR15 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF001183Cu)
+
+/** Alias (User Manual Name) for DMA_HRR15.
+* To use register names with standard convension, please use DMA_HRR15.
+*/
+#define DMA_HRR015 (DMA_HRR15)
+
+/** \brief 1840, DMA Channel Hardware Resource Register */
+#define DMA_HRR16 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011840u)
+
+/** Alias (User Manual Name) for DMA_HRR16.
+* To use register names with standard convension, please use DMA_HRR16.
+*/
+#define DMA_HRR016 (DMA_HRR16)
+
+/** \brief 1844, DMA Channel Hardware Resource Register */
+#define DMA_HRR17 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011844u)
+
+/** Alias (User Manual Name) for DMA_HRR17.
+* To use register names with standard convension, please use DMA_HRR17.
+*/
+#define DMA_HRR017 (DMA_HRR17)
+
+/** \brief 1848, DMA Channel Hardware Resource Register */
+#define DMA_HRR18 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011848u)
+
+/** Alias (User Manual Name) for DMA_HRR18.
+* To use register names with standard convension, please use DMA_HRR18.
+*/
+#define DMA_HRR018 (DMA_HRR18)
+
+/** \brief 184C, DMA Channel Hardware Resource Register */
+#define DMA_HRR19 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF001184Cu)
+
+/** Alias (User Manual Name) for DMA_HRR19.
+* To use register names with standard convension, please use DMA_HRR19.
+*/
+#define DMA_HRR019 (DMA_HRR19)
+
+/** \brief 1808, DMA Channel Hardware Resource Register */
+#define DMA_HRR2 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011808u)
+
+/** Alias (User Manual Name) for DMA_HRR2.
+* To use register names with standard convension, please use DMA_HRR2.
+*/
+#define DMA_HRR002 (DMA_HRR2)
+
+/** \brief 1850, DMA Channel Hardware Resource Register */
+#define DMA_HRR20 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011850u)
+
+/** Alias (User Manual Name) for DMA_HRR20.
+* To use register names with standard convension, please use DMA_HRR20.
+*/
+#define DMA_HRR020 (DMA_HRR20)
+
+/** \brief 1854, DMA Channel Hardware Resource Register */
+#define DMA_HRR21 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011854u)
+
+/** Alias (User Manual Name) for DMA_HRR21.
+* To use register names with standard convension, please use DMA_HRR21.
+*/
+#define DMA_HRR021 (DMA_HRR21)
+
+/** \brief 1858, DMA Channel Hardware Resource Register */
+#define DMA_HRR22 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011858u)
+
+/** Alias (User Manual Name) for DMA_HRR22.
+* To use register names with standard convension, please use DMA_HRR22.
+*/
+#define DMA_HRR022 (DMA_HRR22)
+
+/** \brief 185C, DMA Channel Hardware Resource Register */
+#define DMA_HRR23 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF001185Cu)
+
+/** Alias (User Manual Name) for DMA_HRR23.
+* To use register names with standard convension, please use DMA_HRR23.
+*/
+#define DMA_HRR023 (DMA_HRR23)
+
+/** \brief 1860, DMA Channel Hardware Resource Register */
+#define DMA_HRR24 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011860u)
+
+/** Alias (User Manual Name) for DMA_HRR24.
+* To use register names with standard convension, please use DMA_HRR24.
+*/
+#define DMA_HRR024 (DMA_HRR24)
+
+/** \brief 1864, DMA Channel Hardware Resource Register */
+#define DMA_HRR25 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011864u)
+
+/** Alias (User Manual Name) for DMA_HRR25.
+* To use register names with standard convension, please use DMA_HRR25.
+*/
+#define DMA_HRR025 (DMA_HRR25)
+
+/** \brief 1868, DMA Channel Hardware Resource Register */
+#define DMA_HRR26 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011868u)
+
+/** Alias (User Manual Name) for DMA_HRR26.
+* To use register names with standard convension, please use DMA_HRR26.
+*/
+#define DMA_HRR026 (DMA_HRR26)
+
+/** \brief 186C, DMA Channel Hardware Resource Register */
+#define DMA_HRR27 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF001186Cu)
+
+/** Alias (User Manual Name) for DMA_HRR27.
+* To use register names with standard convension, please use DMA_HRR27.
+*/
+#define DMA_HRR027 (DMA_HRR27)
+
+/** \brief 1870, DMA Channel Hardware Resource Register */
+#define DMA_HRR28 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011870u)
+
+/** Alias (User Manual Name) for DMA_HRR28.
+* To use register names with standard convension, please use DMA_HRR28.
+*/
+#define DMA_HRR028 (DMA_HRR28)
+
+/** \brief 1874, DMA Channel Hardware Resource Register */
+#define DMA_HRR29 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011874u)
+
+/** Alias (User Manual Name) for DMA_HRR29.
+* To use register names with standard convension, please use DMA_HRR29.
+*/
+#define DMA_HRR029 (DMA_HRR29)
+
+/** \brief 180C, DMA Channel Hardware Resource Register */
+#define DMA_HRR3 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF001180Cu)
+
+/** Alias (User Manual Name) for DMA_HRR3.
+* To use register names with standard convension, please use DMA_HRR3.
+*/
+#define DMA_HRR003 (DMA_HRR3)
+
+/** \brief 1878, DMA Channel Hardware Resource Register */
+#define DMA_HRR30 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011878u)
+
+/** Alias (User Manual Name) for DMA_HRR30.
+* To use register names with standard convension, please use DMA_HRR30.
+*/
+#define DMA_HRR030 (DMA_HRR30)
+
+/** \brief 187C, DMA Channel Hardware Resource Register */
+#define DMA_HRR31 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF001187Cu)
+
+/** Alias (User Manual Name) for DMA_HRR31.
+* To use register names with standard convension, please use DMA_HRR31.
+*/
+#define DMA_HRR031 (DMA_HRR31)
+
+/** \brief 1880, DMA Channel Hardware Resource Register */
+#define DMA_HRR32 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011880u)
+
+/** Alias (User Manual Name) for DMA_HRR32.
+* To use register names with standard convension, please use DMA_HRR32.
+*/
+#define DMA_HRR032 (DMA_HRR32)
+
+/** \brief 1884, DMA Channel Hardware Resource Register */
+#define DMA_HRR33 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011884u)
+
+/** Alias (User Manual Name) for DMA_HRR33.
+* To use register names with standard convension, please use DMA_HRR33.
+*/
+#define DMA_HRR033 (DMA_HRR33)
+
+/** \brief 1888, DMA Channel Hardware Resource Register */
+#define DMA_HRR34 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011888u)
+
+/** Alias (User Manual Name) for DMA_HRR34.
+* To use register names with standard convension, please use DMA_HRR34.
+*/
+#define DMA_HRR034 (DMA_HRR34)
+
+/** \brief 188C, DMA Channel Hardware Resource Register */
+#define DMA_HRR35 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF001188Cu)
+
+/** Alias (User Manual Name) for DMA_HRR35.
+* To use register names with standard convension, please use DMA_HRR35.
+*/
+#define DMA_HRR035 (DMA_HRR35)
+
+/** \brief 1890, DMA Channel Hardware Resource Register */
+#define DMA_HRR36 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011890u)
+
+/** Alias (User Manual Name) for DMA_HRR36.
+* To use register names with standard convension, please use DMA_HRR36.
+*/
+#define DMA_HRR036 (DMA_HRR36)
+
+/** \brief 1894, DMA Channel Hardware Resource Register */
+#define DMA_HRR37 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011894u)
+
+/** Alias (User Manual Name) for DMA_HRR37.
+* To use register names with standard convension, please use DMA_HRR37.
+*/
+#define DMA_HRR037 (DMA_HRR37)
+
+/** \brief 1898, DMA Channel Hardware Resource Register */
+#define DMA_HRR38 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011898u)
+
+/** Alias (User Manual Name) for DMA_HRR38.
+* To use register names with standard convension, please use DMA_HRR38.
+*/
+#define DMA_HRR038 (DMA_HRR38)
+
+/** \brief 189C, DMA Channel Hardware Resource Register */
+#define DMA_HRR39 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF001189Cu)
+
+/** Alias (User Manual Name) for DMA_HRR39.
+* To use register names with standard convension, please use DMA_HRR39.
+*/
+#define DMA_HRR039 (DMA_HRR39)
+
+/** \brief 1810, DMA Channel Hardware Resource Register */
+#define DMA_HRR4 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011810u)
+
+/** Alias (User Manual Name) for DMA_HRR4.
+* To use register names with standard convension, please use DMA_HRR4.
+*/
+#define DMA_HRR004 (DMA_HRR4)
+
+/** \brief 18A0, DMA Channel Hardware Resource Register */
+#define DMA_HRR40 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF00118A0u)
+
+/** Alias (User Manual Name) for DMA_HRR40.
+* To use register names with standard convension, please use DMA_HRR40.
+*/
+#define DMA_HRR040 (DMA_HRR40)
+
+/** \brief 18A4, DMA Channel Hardware Resource Register */
+#define DMA_HRR41 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF00118A4u)
+
+/** Alias (User Manual Name) for DMA_HRR41.
+* To use register names with standard convension, please use DMA_HRR41.
+*/
+#define DMA_HRR041 (DMA_HRR41)
+
+/** \brief 18A8, DMA Channel Hardware Resource Register */
+#define DMA_HRR42 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF00118A8u)
+
+/** Alias (User Manual Name) for DMA_HRR42.
+* To use register names with standard convension, please use DMA_HRR42.
+*/
+#define DMA_HRR042 (DMA_HRR42)
+
+/** \brief 18AC, DMA Channel Hardware Resource Register */
+#define DMA_HRR43 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF00118ACu)
+
+/** Alias (User Manual Name) for DMA_HRR43.
+* To use register names with standard convension, please use DMA_HRR43.
+*/
+#define DMA_HRR043 (DMA_HRR43)
+
+/** \brief 18B0, DMA Channel Hardware Resource Register */
+#define DMA_HRR44 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF00118B0u)
+
+/** Alias (User Manual Name) for DMA_HRR44.
+* To use register names with standard convension, please use DMA_HRR44.
+*/
+#define DMA_HRR044 (DMA_HRR44)
+
+/** \brief 18B4, DMA Channel Hardware Resource Register */
+#define DMA_HRR45 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF00118B4u)
+
+/** Alias (User Manual Name) for DMA_HRR45.
+* To use register names with standard convension, please use DMA_HRR45.
+*/
+#define DMA_HRR045 (DMA_HRR45)
+
+/** \brief 18B8, DMA Channel Hardware Resource Register */
+#define DMA_HRR46 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF00118B8u)
+
+/** Alias (User Manual Name) for DMA_HRR46.
+* To use register names with standard convension, please use DMA_HRR46.
+*/
+#define DMA_HRR046 (DMA_HRR46)
+
+/** \brief 18BC, DMA Channel Hardware Resource Register */
+#define DMA_HRR47 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF00118BCu)
+
+/** Alias (User Manual Name) for DMA_HRR47.
+* To use register names with standard convension, please use DMA_HRR47.
+*/
+#define DMA_HRR047 (DMA_HRR47)
+
+/** \brief 1814, DMA Channel Hardware Resource Register */
+#define DMA_HRR5 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011814u)
+
+/** Alias (User Manual Name) for DMA_HRR5.
+* To use register names with standard convension, please use DMA_HRR5.
+*/
+#define DMA_HRR005 (DMA_HRR5)
+
+/** \brief 1818, DMA Channel Hardware Resource Register */
+#define DMA_HRR6 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011818u)
+
+/** Alias (User Manual Name) for DMA_HRR6.
+* To use register names with standard convension, please use DMA_HRR6.
+*/
+#define DMA_HRR006 (DMA_HRR6)
+
+/** \brief 181C, DMA Channel Hardware Resource Register */
+#define DMA_HRR7 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF001181Cu)
+
+/** Alias (User Manual Name) for DMA_HRR7.
+* To use register names with standard convension, please use DMA_HRR7.
+*/
+#define DMA_HRR007 (DMA_HRR7)
+
+/** \brief 1820, DMA Channel Hardware Resource Register */
+#define DMA_HRR8 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011820u)
+
+/** Alias (User Manual Name) for DMA_HRR8.
+* To use register names with standard convension, please use DMA_HRR8.
+*/
+#define DMA_HRR008 (DMA_HRR8)
+
+/** \brief 1824, DMA Channel Hardware Resource Register */
+#define DMA_HRR9 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011824u)
+
+/** Alias (User Manual Name) for DMA_HRR9.
+* To use register names with standard convension, please use DMA_HRR9.
+*/
+#define DMA_HRR009 (DMA_HRR9)
+
+/** \brief 8, Module Identification Register */
+#define DMA_ID /*lint --e(923)*/ (*(volatile Ifx_DMA_ID*)0xF0010008u)
+
+/** \brief 20, DMA Memory Control Register */
+#define DMA_MEMCON /*lint --e(923)*/ (*(volatile Ifx_DMA_MEMCON*)0xF0010020u)
+
+/** \brief 1300, DMA Mode Register */
+#define DMA_MODE0 /*lint --e(923)*/ (*(volatile Ifx_DMA_MODE*)0xF0011300u)
+
+/** \brief 1304, DMA Mode Register */
+#define DMA_MODE1 /*lint --e(923)*/ (*(volatile Ifx_DMA_MODE*)0xF0011304u)
+
+/** \brief 1308, DMA Mode Register */
+#define DMA_MODE2 /*lint --e(923)*/ (*(volatile Ifx_DMA_MODE*)0xF0011308u)
+
+/** \brief 130C, DMA Mode Register */
+#define DMA_MODE3 /*lint --e(923)*/ (*(volatile Ifx_DMA_MODE*)0xF001130Cu)
+
+/** \brief 1200, DMA OCDS Trigger Set Select */
+#define DMA_OTSS /*lint --e(923)*/ (*(volatile Ifx_DMA_OTSS*)0xF0011200u)
+
+/** \brief 1208, Pattern Read Register 0 */
+#define DMA_PRR0 /*lint --e(923)*/ (*(volatile Ifx_DMA_PRR0*)0xF0011208u)
+
+/** \brief 120C, Pattern Read Register 1 */
+#define DMA_PRR1 /*lint --e(923)*/ (*(volatile Ifx_DMA_PRR1*)0xF001120Cu)
+
+/** \brief 1C00, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR0 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C00u)
+
+/** Alias (User Manual Name) for DMA_SUSACR0.
+* To use register names with standard convension, please use DMA_SUSACR0.
+*/
+#define DMA_SUSACR000 (DMA_SUSACR0)
+
+/** \brief 1C04, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR1 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C04u)
+
+/** Alias (User Manual Name) for DMA_SUSACR1.
+* To use register names with standard convension, please use DMA_SUSACR1.
+*/
+#define DMA_SUSACR001 (DMA_SUSACR1)
+
+/** \brief 1C28, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR10 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C28u)
+
+/** Alias (User Manual Name) for DMA_SUSACR10.
+* To use register names with standard convension, please use DMA_SUSACR10.
+*/
+#define DMA_SUSACR010 (DMA_SUSACR10)
+
+/** \brief 1C2C, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR11 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C2Cu)
+
+/** Alias (User Manual Name) for DMA_SUSACR11.
+* To use register names with standard convension, please use DMA_SUSACR11.
+*/
+#define DMA_SUSACR011 (DMA_SUSACR11)
+
+/** \brief 1C30, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR12 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C30u)
+
+/** Alias (User Manual Name) for DMA_SUSACR12.
+* To use register names with standard convension, please use DMA_SUSACR12.
+*/
+#define DMA_SUSACR012 (DMA_SUSACR12)
+
+/** \brief 1C34, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR13 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C34u)
+
+/** Alias (User Manual Name) for DMA_SUSACR13.
+* To use register names with standard convension, please use DMA_SUSACR13.
+*/
+#define DMA_SUSACR013 (DMA_SUSACR13)
+
+/** \brief 1C38, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR14 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C38u)
+
+/** Alias (User Manual Name) for DMA_SUSACR14.
+* To use register names with standard convension, please use DMA_SUSACR14.
+*/
+#define DMA_SUSACR014 (DMA_SUSACR14)
+
+/** \brief 1C3C, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR15 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C3Cu)
+
+/** Alias (User Manual Name) for DMA_SUSACR15.
+* To use register names with standard convension, please use DMA_SUSACR15.
+*/
+#define DMA_SUSACR015 (DMA_SUSACR15)
+
+/** \brief 1C40, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR16 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C40u)
+
+/** Alias (User Manual Name) for DMA_SUSACR16.
+* To use register names with standard convension, please use DMA_SUSACR16.
+*/
+#define DMA_SUSACR016 (DMA_SUSACR16)
+
+/** \brief 1C44, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR17 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C44u)
+
+/** Alias (User Manual Name) for DMA_SUSACR17.
+* To use register names with standard convension, please use DMA_SUSACR17.
+*/
+#define DMA_SUSACR017 (DMA_SUSACR17)
+
+/** \brief 1C48, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR18 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C48u)
+
+/** Alias (User Manual Name) for DMA_SUSACR18.
+* To use register names with standard convension, please use DMA_SUSACR18.
+*/
+#define DMA_SUSACR018 (DMA_SUSACR18)
+
+/** \brief 1C4C, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR19 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C4Cu)
+
+/** Alias (User Manual Name) for DMA_SUSACR19.
+* To use register names with standard convension, please use DMA_SUSACR19.
+*/
+#define DMA_SUSACR019 (DMA_SUSACR19)
+
+/** \brief 1C08, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR2 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C08u)
+
+/** Alias (User Manual Name) for DMA_SUSACR2.
+* To use register names with standard convension, please use DMA_SUSACR2.
+*/
+#define DMA_SUSACR002 (DMA_SUSACR2)
+
+/** \brief 1C50, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR20 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C50u)
+
+/** Alias (User Manual Name) for DMA_SUSACR20.
+* To use register names with standard convension, please use DMA_SUSACR20.
+*/
+#define DMA_SUSACR020 (DMA_SUSACR20)
+
+/** \brief 1C54, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR21 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C54u)
+
+/** Alias (User Manual Name) for DMA_SUSACR21.
+* To use register names with standard convension, please use DMA_SUSACR21.
+*/
+#define DMA_SUSACR021 (DMA_SUSACR21)
+
+/** \brief 1C58, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR22 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C58u)
+
+/** Alias (User Manual Name) for DMA_SUSACR22.
+* To use register names with standard convension, please use DMA_SUSACR22.
+*/
+#define DMA_SUSACR022 (DMA_SUSACR22)
+
+/** \brief 1C5C, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR23 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C5Cu)
+
+/** Alias (User Manual Name) for DMA_SUSACR23.
+* To use register names with standard convension, please use DMA_SUSACR23.
+*/
+#define DMA_SUSACR023 (DMA_SUSACR23)
+
+/** \brief 1C60, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR24 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C60u)
+
+/** Alias (User Manual Name) for DMA_SUSACR24.
+* To use register names with standard convension, please use DMA_SUSACR24.
+*/
+#define DMA_SUSACR024 (DMA_SUSACR24)
+
+/** \brief 1C64, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR25 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C64u)
+
+/** Alias (User Manual Name) for DMA_SUSACR25.
+* To use register names with standard convension, please use DMA_SUSACR25.
+*/
+#define DMA_SUSACR025 (DMA_SUSACR25)
+
+/** \brief 1C68, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR26 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C68u)
+
+/** Alias (User Manual Name) for DMA_SUSACR26.
+* To use register names with standard convension, please use DMA_SUSACR26.
+*/
+#define DMA_SUSACR026 (DMA_SUSACR26)
+
+/** \brief 1C6C, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR27 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C6Cu)
+
+/** Alias (User Manual Name) for DMA_SUSACR27.
+* To use register names with standard convension, please use DMA_SUSACR27.
+*/
+#define DMA_SUSACR027 (DMA_SUSACR27)
+
+/** \brief 1C70, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR28 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C70u)
+
+/** Alias (User Manual Name) for DMA_SUSACR28.
+* To use register names with standard convension, please use DMA_SUSACR28.
+*/
+#define DMA_SUSACR028 (DMA_SUSACR28)
+
+/** \brief 1C74, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR29 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C74u)
+
+/** Alias (User Manual Name) for DMA_SUSACR29.
+* To use register names with standard convension, please use DMA_SUSACR29.
+*/
+#define DMA_SUSACR029 (DMA_SUSACR29)
+
+/** \brief 1C0C, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR3 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C0Cu)
+
+/** Alias (User Manual Name) for DMA_SUSACR3.
+* To use register names with standard convension, please use DMA_SUSACR3.
+*/
+#define DMA_SUSACR003 (DMA_SUSACR3)
+
+/** \brief 1C78, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR30 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C78u)
+
+/** Alias (User Manual Name) for DMA_SUSACR30.
+* To use register names with standard convension, please use DMA_SUSACR30.
+*/
+#define DMA_SUSACR030 (DMA_SUSACR30)
+
+/** \brief 1C7C, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR31 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C7Cu)
+
+/** Alias (User Manual Name) for DMA_SUSACR31.
+* To use register names with standard convension, please use DMA_SUSACR31.
+*/
+#define DMA_SUSACR031 (DMA_SUSACR31)
+
+/** \brief 1C80, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR32 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C80u)
+
+/** Alias (User Manual Name) for DMA_SUSACR32.
+* To use register names with standard convension, please use DMA_SUSACR32.
+*/
+#define DMA_SUSACR032 (DMA_SUSACR32)
+
+/** \brief 1C84, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR33 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C84u)
+
+/** Alias (User Manual Name) for DMA_SUSACR33.
+* To use register names with standard convension, please use DMA_SUSACR33.
+*/
+#define DMA_SUSACR033 (DMA_SUSACR33)
+
+/** \brief 1C88, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR34 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C88u)
+
+/** Alias (User Manual Name) for DMA_SUSACR34.
+* To use register names with standard convension, please use DMA_SUSACR34.
+*/
+#define DMA_SUSACR034 (DMA_SUSACR34)
+
+/** \brief 1C8C, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR35 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C8Cu)
+
+/** Alias (User Manual Name) for DMA_SUSACR35.
+* To use register names with standard convension, please use DMA_SUSACR35.
+*/
+#define DMA_SUSACR035 (DMA_SUSACR35)
+
+/** \brief 1C90, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR36 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C90u)
+
+/** Alias (User Manual Name) for DMA_SUSACR36.
+* To use register names with standard convension, please use DMA_SUSACR36.
+*/
+#define DMA_SUSACR036 (DMA_SUSACR36)
+
+/** \brief 1C94, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR37 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C94u)
+
+/** Alias (User Manual Name) for DMA_SUSACR37.
+* To use register names with standard convension, please use DMA_SUSACR37.
+*/
+#define DMA_SUSACR037 (DMA_SUSACR37)
+
+/** \brief 1C98, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR38 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C98u)
+
+/** Alias (User Manual Name) for DMA_SUSACR38.
+* To use register names with standard convension, please use DMA_SUSACR38.
+*/
+#define DMA_SUSACR038 (DMA_SUSACR38)
+
+/** \brief 1C9C, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR39 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C9Cu)
+
+/** Alias (User Manual Name) for DMA_SUSACR39.
+* To use register names with standard convension, please use DMA_SUSACR39.
+*/
+#define DMA_SUSACR039 (DMA_SUSACR39)
+
+/** \brief 1C10, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR4 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C10u)
+
+/** Alias (User Manual Name) for DMA_SUSACR4.
+* To use register names with standard convension, please use DMA_SUSACR4.
+*/
+#define DMA_SUSACR004 (DMA_SUSACR4)
+
+/** \brief 1CA0, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR40 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011CA0u)
+
+/** Alias (User Manual Name) for DMA_SUSACR40.
+* To use register names with standard convension, please use DMA_SUSACR40.
+*/
+#define DMA_SUSACR040 (DMA_SUSACR40)
+
+/** \brief 1CA4, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR41 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011CA4u)
+
+/** Alias (User Manual Name) for DMA_SUSACR41.
+* To use register names with standard convension, please use DMA_SUSACR41.
+*/
+#define DMA_SUSACR041 (DMA_SUSACR41)
+
+/** \brief 1CA8, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR42 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011CA8u)
+
+/** Alias (User Manual Name) for DMA_SUSACR42.
+* To use register names with standard convension, please use DMA_SUSACR42.
+*/
+#define DMA_SUSACR042 (DMA_SUSACR42)
+
+/** \brief 1CAC, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR43 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011CACu)
+
+/** Alias (User Manual Name) for DMA_SUSACR43.
+* To use register names with standard convension, please use DMA_SUSACR43.
+*/
+#define DMA_SUSACR043 (DMA_SUSACR43)
+
+/** \brief 1CB0, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR44 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011CB0u)
+
+/** Alias (User Manual Name) for DMA_SUSACR44.
+* To use register names with standard convension, please use DMA_SUSACR44.
+*/
+#define DMA_SUSACR044 (DMA_SUSACR44)
+
+/** \brief 1CB4, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR45 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011CB4u)
+
+/** Alias (User Manual Name) for DMA_SUSACR45.
+* To use register names with standard convension, please use DMA_SUSACR45.
+*/
+#define DMA_SUSACR045 (DMA_SUSACR45)
+
+/** \brief 1CB8, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR46 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011CB8u)
+
+/** Alias (User Manual Name) for DMA_SUSACR46.
+* To use register names with standard convension, please use DMA_SUSACR46.
+*/
+#define DMA_SUSACR046 (DMA_SUSACR46)
+
+/** \brief 1CBC, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR47 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011CBCu)
+
+/** Alias (User Manual Name) for DMA_SUSACR47.
+* To use register names with standard convension, please use DMA_SUSACR47.
+*/
+#define DMA_SUSACR047 (DMA_SUSACR47)
+
+/** \brief 1C14, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR5 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C14u)
+
+/** Alias (User Manual Name) for DMA_SUSACR5.
+* To use register names with standard convension, please use DMA_SUSACR5.
+*/
+#define DMA_SUSACR005 (DMA_SUSACR5)
+
+/** \brief 1C18, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR6 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C18u)
+
+/** Alias (User Manual Name) for DMA_SUSACR6.
+* To use register names with standard convension, please use DMA_SUSACR6.
+*/
+#define DMA_SUSACR006 (DMA_SUSACR6)
+
+/** \brief 1C1C, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR7 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C1Cu)
+
+/** Alias (User Manual Name) for DMA_SUSACR7.
+* To use register names with standard convension, please use DMA_SUSACR7.
+*/
+#define DMA_SUSACR007 (DMA_SUSACR7)
+
+/** \brief 1C20, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR8 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C20u)
+
+/** Alias (User Manual Name) for DMA_SUSACR8.
+* To use register names with standard convension, please use DMA_SUSACR8.
+*/
+#define DMA_SUSACR008 (DMA_SUSACR8)
+
+/** \brief 1C24, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR9 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C24u)
+
+/** Alias (User Manual Name) for DMA_SUSACR9.
+* To use register names with standard convension, please use DMA_SUSACR9.
+*/
+#define DMA_SUSACR009 (DMA_SUSACR9)
+
+/** \brief 1A00, DMA Suspend Enable Register */
+#define DMA_SUSENR0 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A00u)
+
+/** Alias (User Manual Name) for DMA_SUSENR0.
+* To use register names with standard convension, please use DMA_SUSENR0.
+*/
+#define DMA_SUSENR000 (DMA_SUSENR0)
+
+/** \brief 1A04, DMA Suspend Enable Register */
+#define DMA_SUSENR1 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A04u)
+
+/** Alias (User Manual Name) for DMA_SUSENR1.
+* To use register names with standard convension, please use DMA_SUSENR1.
+*/
+#define DMA_SUSENR001 (DMA_SUSENR1)
+
+/** \brief 1A28, DMA Suspend Enable Register */
+#define DMA_SUSENR10 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A28u)
+
+/** Alias (User Manual Name) for DMA_SUSENR10.
+* To use register names with standard convension, please use DMA_SUSENR10.
+*/
+#define DMA_SUSENR010 (DMA_SUSENR10)
+
+/** \brief 1A2C, DMA Suspend Enable Register */
+#define DMA_SUSENR11 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A2Cu)
+
+/** Alias (User Manual Name) for DMA_SUSENR11.
+* To use register names with standard convension, please use DMA_SUSENR11.
+*/
+#define DMA_SUSENR011 (DMA_SUSENR11)
+
+/** \brief 1A30, DMA Suspend Enable Register */
+#define DMA_SUSENR12 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A30u)
+
+/** Alias (User Manual Name) for DMA_SUSENR12.
+* To use register names with standard convension, please use DMA_SUSENR12.
+*/
+#define DMA_SUSENR012 (DMA_SUSENR12)
+
+/** \brief 1A34, DMA Suspend Enable Register */
+#define DMA_SUSENR13 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A34u)
+
+/** Alias (User Manual Name) for DMA_SUSENR13.
+* To use register names with standard convension, please use DMA_SUSENR13.
+*/
+#define DMA_SUSENR013 (DMA_SUSENR13)
+
+/** \brief 1A38, DMA Suspend Enable Register */
+#define DMA_SUSENR14 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A38u)
+
+/** Alias (User Manual Name) for DMA_SUSENR14.
+* To use register names with standard convension, please use DMA_SUSENR14.
+*/
+#define DMA_SUSENR014 (DMA_SUSENR14)
+
+/** \brief 1A3C, DMA Suspend Enable Register */
+#define DMA_SUSENR15 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A3Cu)
+
+/** Alias (User Manual Name) for DMA_SUSENR15.
+* To use register names with standard convension, please use DMA_SUSENR15.
+*/
+#define DMA_SUSENR015 (DMA_SUSENR15)
+
+/** \brief 1A40, DMA Suspend Enable Register */
+#define DMA_SUSENR16 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A40u)
+
+/** Alias (User Manual Name) for DMA_SUSENR16.
+* To use register names with standard convension, please use DMA_SUSENR16.
+*/
+#define DMA_SUSENR016 (DMA_SUSENR16)
+
+/** \brief 1A44, DMA Suspend Enable Register */
+#define DMA_SUSENR17 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A44u)
+
+/** Alias (User Manual Name) for DMA_SUSENR17.
+* To use register names with standard convension, please use DMA_SUSENR17.
+*/
+#define DMA_SUSENR017 (DMA_SUSENR17)
+
+/** \brief 1A48, DMA Suspend Enable Register */
+#define DMA_SUSENR18 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A48u)
+
+/** Alias (User Manual Name) for DMA_SUSENR18.
+* To use register names with standard convension, please use DMA_SUSENR18.
+*/
+#define DMA_SUSENR018 (DMA_SUSENR18)
+
+/** \brief 1A4C, DMA Suspend Enable Register */
+#define DMA_SUSENR19 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A4Cu)
+
+/** Alias (User Manual Name) for DMA_SUSENR19.
+* To use register names with standard convension, please use DMA_SUSENR19.
+*/
+#define DMA_SUSENR019 (DMA_SUSENR19)
+
+/** \brief 1A08, DMA Suspend Enable Register */
+#define DMA_SUSENR2 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A08u)
+
+/** Alias (User Manual Name) for DMA_SUSENR2.
+* To use register names with standard convension, please use DMA_SUSENR2.
+*/
+#define DMA_SUSENR002 (DMA_SUSENR2)
+
+/** \brief 1A50, DMA Suspend Enable Register */
+#define DMA_SUSENR20 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A50u)
+
+/** Alias (User Manual Name) for DMA_SUSENR20.
+* To use register names with standard convension, please use DMA_SUSENR20.
+*/
+#define DMA_SUSENR020 (DMA_SUSENR20)
+
+/** \brief 1A54, DMA Suspend Enable Register */
+#define DMA_SUSENR21 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A54u)
+
+/** Alias (User Manual Name) for DMA_SUSENR21.
+* To use register names with standard convension, please use DMA_SUSENR21.
+*/
+#define DMA_SUSENR021 (DMA_SUSENR21)
+
+/** \brief 1A58, DMA Suspend Enable Register */
+#define DMA_SUSENR22 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A58u)
+
+/** Alias (User Manual Name) for DMA_SUSENR22.
+* To use register names with standard convension, please use DMA_SUSENR22.
+*/
+#define DMA_SUSENR022 (DMA_SUSENR22)
+
+/** \brief 1A5C, DMA Suspend Enable Register */
+#define DMA_SUSENR23 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A5Cu)
+
+/** Alias (User Manual Name) for DMA_SUSENR23.
+* To use register names with standard convension, please use DMA_SUSENR23.
+*/
+#define DMA_SUSENR023 (DMA_SUSENR23)
+
+/** \brief 1A60, DMA Suspend Enable Register */
+#define DMA_SUSENR24 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A60u)
+
+/** Alias (User Manual Name) for DMA_SUSENR24.
+* To use register names with standard convension, please use DMA_SUSENR24.
+*/
+#define DMA_SUSENR024 (DMA_SUSENR24)
+
+/** \brief 1A64, DMA Suspend Enable Register */
+#define DMA_SUSENR25 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A64u)
+
+/** Alias (User Manual Name) for DMA_SUSENR25.
+* To use register names with standard convension, please use DMA_SUSENR25.
+*/
+#define DMA_SUSENR025 (DMA_SUSENR25)
+
+/** \brief 1A68, DMA Suspend Enable Register */
+#define DMA_SUSENR26 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A68u)
+
+/** Alias (User Manual Name) for DMA_SUSENR26.
+* To use register names with standard convension, please use DMA_SUSENR26.
+*/
+#define DMA_SUSENR026 (DMA_SUSENR26)
+
+/** \brief 1A6C, DMA Suspend Enable Register */
+#define DMA_SUSENR27 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A6Cu)
+
+/** Alias (User Manual Name) for DMA_SUSENR27.
+* To use register names with standard convension, please use DMA_SUSENR27.
+*/
+#define DMA_SUSENR027 (DMA_SUSENR27)
+
+/** \brief 1A70, DMA Suspend Enable Register */
+#define DMA_SUSENR28 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A70u)
+
+/** Alias (User Manual Name) for DMA_SUSENR28.
+* To use register names with standard convension, please use DMA_SUSENR28.
+*/
+#define DMA_SUSENR028 (DMA_SUSENR28)
+
+/** \brief 1A74, DMA Suspend Enable Register */
+#define DMA_SUSENR29 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A74u)
+
+/** Alias (User Manual Name) for DMA_SUSENR29.
+* To use register names with standard convension, please use DMA_SUSENR29.
+*/
+#define DMA_SUSENR029 (DMA_SUSENR29)
+
+/** \brief 1A0C, DMA Suspend Enable Register */
+#define DMA_SUSENR3 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A0Cu)
+
+/** Alias (User Manual Name) for DMA_SUSENR3.
+* To use register names with standard convension, please use DMA_SUSENR3.
+*/
+#define DMA_SUSENR003 (DMA_SUSENR3)
+
+/** \brief 1A78, DMA Suspend Enable Register */
+#define DMA_SUSENR30 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A78u)
+
+/** Alias (User Manual Name) for DMA_SUSENR30.
+* To use register names with standard convension, please use DMA_SUSENR30.
+*/
+#define DMA_SUSENR030 (DMA_SUSENR30)
+
+/** \brief 1A7C, DMA Suspend Enable Register */
+#define DMA_SUSENR31 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A7Cu)
+
+/** Alias (User Manual Name) for DMA_SUSENR31.
+* To use register names with standard convension, please use DMA_SUSENR31.
+*/
+#define DMA_SUSENR031 (DMA_SUSENR31)
+
+/** \brief 1A80, DMA Suspend Enable Register */
+#define DMA_SUSENR32 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A80u)
+
+/** Alias (User Manual Name) for DMA_SUSENR32.
+* To use register names with standard convension, please use DMA_SUSENR32.
+*/
+#define DMA_SUSENR032 (DMA_SUSENR32)
+
+/** \brief 1A84, DMA Suspend Enable Register */
+#define DMA_SUSENR33 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A84u)
+
+/** Alias (User Manual Name) for DMA_SUSENR33.
+* To use register names with standard convension, please use DMA_SUSENR33.
+*/
+#define DMA_SUSENR033 (DMA_SUSENR33)
+
+/** \brief 1A88, DMA Suspend Enable Register */
+#define DMA_SUSENR34 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A88u)
+
+/** Alias (User Manual Name) for DMA_SUSENR34.
+* To use register names with standard convension, please use DMA_SUSENR34.
+*/
+#define DMA_SUSENR034 (DMA_SUSENR34)
+
+/** \brief 1A8C, DMA Suspend Enable Register */
+#define DMA_SUSENR35 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A8Cu)
+
+/** Alias (User Manual Name) for DMA_SUSENR35.
+* To use register names with standard convension, please use DMA_SUSENR35.
+*/
+#define DMA_SUSENR035 (DMA_SUSENR35)
+
+/** \brief 1A90, DMA Suspend Enable Register */
+#define DMA_SUSENR36 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A90u)
+
+/** Alias (User Manual Name) for DMA_SUSENR36.
+* To use register names with standard convension, please use DMA_SUSENR36.
+*/
+#define DMA_SUSENR036 (DMA_SUSENR36)
+
+/** \brief 1A94, DMA Suspend Enable Register */
+#define DMA_SUSENR37 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A94u)
+
+/** Alias (User Manual Name) for DMA_SUSENR37.
+* To use register names with standard convension, please use DMA_SUSENR37.
+*/
+#define DMA_SUSENR037 (DMA_SUSENR37)
+
+/** \brief 1A98, DMA Suspend Enable Register */
+#define DMA_SUSENR38 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A98u)
+
+/** Alias (User Manual Name) for DMA_SUSENR38.
+* To use register names with standard convension, please use DMA_SUSENR38.
+*/
+#define DMA_SUSENR038 (DMA_SUSENR38)
+
+/** \brief 1A9C, DMA Suspend Enable Register */
+#define DMA_SUSENR39 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A9Cu)
+
+/** Alias (User Manual Name) for DMA_SUSENR39.
+* To use register names with standard convension, please use DMA_SUSENR39.
+*/
+#define DMA_SUSENR039 (DMA_SUSENR39)
+
+/** \brief 1A10, DMA Suspend Enable Register */
+#define DMA_SUSENR4 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A10u)
+
+/** Alias (User Manual Name) for DMA_SUSENR4.
+* To use register names with standard convension, please use DMA_SUSENR4.
+*/
+#define DMA_SUSENR004 (DMA_SUSENR4)
+
+/** \brief 1AA0, DMA Suspend Enable Register */
+#define DMA_SUSENR40 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011AA0u)
+
+/** Alias (User Manual Name) for DMA_SUSENR40.
+* To use register names with standard convension, please use DMA_SUSENR40.
+*/
+#define DMA_SUSENR040 (DMA_SUSENR40)
+
+/** \brief 1AA4, DMA Suspend Enable Register */
+#define DMA_SUSENR41 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011AA4u)
+
+/** Alias (User Manual Name) for DMA_SUSENR41.
+* To use register names with standard convension, please use DMA_SUSENR41.
+*/
+#define DMA_SUSENR041 (DMA_SUSENR41)
+
+/** \brief 1AA8, DMA Suspend Enable Register */
+#define DMA_SUSENR42 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011AA8u)
+
+/** Alias (User Manual Name) for DMA_SUSENR42.
+* To use register names with standard convension, please use DMA_SUSENR42.
+*/
+#define DMA_SUSENR042 (DMA_SUSENR42)
+
+/** \brief 1AAC, DMA Suspend Enable Register */
+#define DMA_SUSENR43 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011AACu)
+
+/** Alias (User Manual Name) for DMA_SUSENR43.
+* To use register names with standard convension, please use DMA_SUSENR43.
+*/
+#define DMA_SUSENR043 (DMA_SUSENR43)
+
+/** \brief 1AB0, DMA Suspend Enable Register */
+#define DMA_SUSENR44 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011AB0u)
+
+/** Alias (User Manual Name) for DMA_SUSENR44.
+* To use register names with standard convension, please use DMA_SUSENR44.
+*/
+#define DMA_SUSENR044 (DMA_SUSENR44)
+
+/** \brief 1AB4, DMA Suspend Enable Register */
+#define DMA_SUSENR45 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011AB4u)
+
+/** Alias (User Manual Name) for DMA_SUSENR45.
+* To use register names with standard convension, please use DMA_SUSENR45.
+*/
+#define DMA_SUSENR045 (DMA_SUSENR45)
+
+/** \brief 1AB8, DMA Suspend Enable Register */
+#define DMA_SUSENR46 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011AB8u)
+
+/** Alias (User Manual Name) for DMA_SUSENR46.
+* To use register names with standard convension, please use DMA_SUSENR46.
+*/
+#define DMA_SUSENR046 (DMA_SUSENR46)
+
+/** \brief 1ABC, DMA Suspend Enable Register */
+#define DMA_SUSENR47 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011ABCu)
+
+/** Alias (User Manual Name) for DMA_SUSENR47.
+* To use register names with standard convension, please use DMA_SUSENR47.
+*/
+#define DMA_SUSENR047 (DMA_SUSENR47)
+
+/** \brief 1A14, DMA Suspend Enable Register */
+#define DMA_SUSENR5 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A14u)
+
+/** Alias (User Manual Name) for DMA_SUSENR5.
+* To use register names with standard convension, please use DMA_SUSENR5.
+*/
+#define DMA_SUSENR005 (DMA_SUSENR5)
+
+/** \brief 1A18, DMA Suspend Enable Register */
+#define DMA_SUSENR6 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A18u)
+
+/** Alias (User Manual Name) for DMA_SUSENR6.
+* To use register names with standard convension, please use DMA_SUSENR6.
+*/
+#define DMA_SUSENR006 (DMA_SUSENR6)
+
+/** \brief 1A1C, DMA Suspend Enable Register */
+#define DMA_SUSENR7 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A1Cu)
+
+/** Alias (User Manual Name) for DMA_SUSENR7.
+* To use register names with standard convension, please use DMA_SUSENR7.
+*/
+#define DMA_SUSENR007 (DMA_SUSENR7)
+
+/** \brief 1A20, DMA Suspend Enable Register */
+#define DMA_SUSENR8 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A20u)
+
+/** Alias (User Manual Name) for DMA_SUSENR8.
+* To use register names with standard convension, please use DMA_SUSENR8.
+*/
+#define DMA_SUSENR008 (DMA_SUSENR8)
+
+/** \brief 1A24, DMA Suspend Enable Register */
+#define DMA_SUSENR9 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A24u)
+
+/** Alias (User Manual Name) for DMA_SUSENR9.
+* To use register names with standard convension, please use DMA_SUSENR9.
+*/
+#define DMA_SUSENR009 (DMA_SUSENR9)
+
+/** \brief 1210, Time Register */
+#define DMA_TIME /*lint --e(923)*/ (*(volatile Ifx_DMA_TIME*)0xF0011210u)
+
+/** \brief 1E00, DMA Transaction State Register */
+#define DMA_TSR0 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E00u)
+
+/** Alias (User Manual Name) for DMA_TSR0.
+* To use register names with standard convension, please use DMA_TSR0.
+*/
+#define DMA_TSR000 (DMA_TSR0)
+
+/** \brief 1E04, DMA Transaction State Register */
+#define DMA_TSR1 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E04u)
+
+/** Alias (User Manual Name) for DMA_TSR1.
+* To use register names with standard convension, please use DMA_TSR1.
+*/
+#define DMA_TSR001 (DMA_TSR1)
+
+/** \brief 1E28, DMA Transaction State Register */
+#define DMA_TSR10 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E28u)
+
+/** Alias (User Manual Name) for DMA_TSR10.
+* To use register names with standard convension, please use DMA_TSR10.
+*/
+#define DMA_TSR010 (DMA_TSR10)
+
+/** \brief 1E2C, DMA Transaction State Register */
+#define DMA_TSR11 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E2Cu)
+
+/** Alias (User Manual Name) for DMA_TSR11.
+* To use register names with standard convension, please use DMA_TSR11.
+*/
+#define DMA_TSR011 (DMA_TSR11)
+
+/** \brief 1E30, DMA Transaction State Register */
+#define DMA_TSR12 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E30u)
+
+/** Alias (User Manual Name) for DMA_TSR12.
+* To use register names with standard convension, please use DMA_TSR12.
+*/
+#define DMA_TSR012 (DMA_TSR12)
+
+/** \brief 1E34, DMA Transaction State Register */
+#define DMA_TSR13 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E34u)
+
+/** Alias (User Manual Name) for DMA_TSR13.
+* To use register names with standard convension, please use DMA_TSR13.
+*/
+#define DMA_TSR013 (DMA_TSR13)
+
+/** \brief 1E38, DMA Transaction State Register */
+#define DMA_TSR14 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E38u)
+
+/** Alias (User Manual Name) for DMA_TSR14.
+* To use register names with standard convension, please use DMA_TSR14.
+*/
+#define DMA_TSR014 (DMA_TSR14)
+
+/** \brief 1E3C, DMA Transaction State Register */
+#define DMA_TSR15 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E3Cu)
+
+/** Alias (User Manual Name) for DMA_TSR15.
+* To use register names with standard convension, please use DMA_TSR15.
+*/
+#define DMA_TSR015 (DMA_TSR15)
+
+/** \brief 1E40, DMA Transaction State Register */
+#define DMA_TSR16 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E40u)
+
+/** Alias (User Manual Name) for DMA_TSR16.
+* To use register names with standard convension, please use DMA_TSR16.
+*/
+#define DMA_TSR016 (DMA_TSR16)
+
+/** \brief 1E44, DMA Transaction State Register */
+#define DMA_TSR17 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E44u)
+
+/** Alias (User Manual Name) for DMA_TSR17.
+* To use register names with standard convension, please use DMA_TSR17.
+*/
+#define DMA_TSR017 (DMA_TSR17)
+
+/** \brief 1E48, DMA Transaction State Register */
+#define DMA_TSR18 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E48u)
+
+/** Alias (User Manual Name) for DMA_TSR18.
+* To use register names with standard convension, please use DMA_TSR18.
+*/
+#define DMA_TSR018 (DMA_TSR18)
+
+/** \brief 1E4C, DMA Transaction State Register */
+#define DMA_TSR19 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E4Cu)
+
+/** Alias (User Manual Name) for DMA_TSR19.
+* To use register names with standard convension, please use DMA_TSR19.
+*/
+#define DMA_TSR019 (DMA_TSR19)
+
+/** \brief 1E08, DMA Transaction State Register */
+#define DMA_TSR2 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E08u)
+
+/** Alias (User Manual Name) for DMA_TSR2.
+* To use register names with standard convension, please use DMA_TSR2.
+*/
+#define DMA_TSR002 (DMA_TSR2)
+
+/** \brief 1E50, DMA Transaction State Register */
+#define DMA_TSR20 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E50u)
+
+/** Alias (User Manual Name) for DMA_TSR20.
+* To use register names with standard convension, please use DMA_TSR20.
+*/
+#define DMA_TSR020 (DMA_TSR20)
+
+/** \brief 1E54, DMA Transaction State Register */
+#define DMA_TSR21 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E54u)
+
+/** Alias (User Manual Name) for DMA_TSR21.
+* To use register names with standard convension, please use DMA_TSR21.
+*/
+#define DMA_TSR021 (DMA_TSR21)
+
+/** \brief 1E58, DMA Transaction State Register */
+#define DMA_TSR22 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E58u)
+
+/** Alias (User Manual Name) for DMA_TSR22.
+* To use register names with standard convension, please use DMA_TSR22.
+*/
+#define DMA_TSR022 (DMA_TSR22)
+
+/** \brief 1E5C, DMA Transaction State Register */
+#define DMA_TSR23 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E5Cu)
+
+/** Alias (User Manual Name) for DMA_TSR23.
+* To use register names with standard convension, please use DMA_TSR23.
+*/
+#define DMA_TSR023 (DMA_TSR23)
+
+/** \brief 1E60, DMA Transaction State Register */
+#define DMA_TSR24 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E60u)
+
+/** Alias (User Manual Name) for DMA_TSR24.
+* To use register names with standard convension, please use DMA_TSR24.
+*/
+#define DMA_TSR024 (DMA_TSR24)
+
+/** \brief 1E64, DMA Transaction State Register */
+#define DMA_TSR25 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E64u)
+
+/** Alias (User Manual Name) for DMA_TSR25.
+* To use register names with standard convension, please use DMA_TSR25.
+*/
+#define DMA_TSR025 (DMA_TSR25)
+
+/** \brief 1E68, DMA Transaction State Register */
+#define DMA_TSR26 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E68u)
+
+/** Alias (User Manual Name) for DMA_TSR26.
+* To use register names with standard convension, please use DMA_TSR26.
+*/
+#define DMA_TSR026 (DMA_TSR26)
+
+/** \brief 1E6C, DMA Transaction State Register */
+#define DMA_TSR27 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E6Cu)
+
+/** Alias (User Manual Name) for DMA_TSR27.
+* To use register names with standard convension, please use DMA_TSR27.
+*/
+#define DMA_TSR027 (DMA_TSR27)
+
+/** \brief 1E70, DMA Transaction State Register */
+#define DMA_TSR28 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E70u)
+
+/** Alias (User Manual Name) for DMA_TSR28.
+* To use register names with standard convension, please use DMA_TSR28.
+*/
+#define DMA_TSR028 (DMA_TSR28)
+
+/** \brief 1E74, DMA Transaction State Register */
+#define DMA_TSR29 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E74u)
+
+/** Alias (User Manual Name) for DMA_TSR29.
+* To use register names with standard convension, please use DMA_TSR29.
+*/
+#define DMA_TSR029 (DMA_TSR29)
+
+/** \brief 1E0C, DMA Transaction State Register */
+#define DMA_TSR3 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E0Cu)
+
+/** Alias (User Manual Name) for DMA_TSR3.
+* To use register names with standard convension, please use DMA_TSR3.
+*/
+#define DMA_TSR003 (DMA_TSR3)
+
+/** \brief 1E78, DMA Transaction State Register */
+#define DMA_TSR30 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E78u)
+
+/** Alias (User Manual Name) for DMA_TSR30.
+* To use register names with standard convension, please use DMA_TSR30.
+*/
+#define DMA_TSR030 (DMA_TSR30)
+
+/** \brief 1E7C, DMA Transaction State Register */
+#define DMA_TSR31 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E7Cu)
+
+/** Alias (User Manual Name) for DMA_TSR31.
+* To use register names with standard convension, please use DMA_TSR31.
+*/
+#define DMA_TSR031 (DMA_TSR31)
+
+/** \brief 1E80, DMA Transaction State Register */
+#define DMA_TSR32 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E80u)
+
+/** Alias (User Manual Name) for DMA_TSR32.
+* To use register names with standard convension, please use DMA_TSR32.
+*/
+#define DMA_TSR032 (DMA_TSR32)
+
+/** \brief 1E84, DMA Transaction State Register */
+#define DMA_TSR33 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E84u)
+
+/** Alias (User Manual Name) for DMA_TSR33.
+* To use register names with standard convension, please use DMA_TSR33.
+*/
+#define DMA_TSR033 (DMA_TSR33)
+
+/** \brief 1E88, DMA Transaction State Register */
+#define DMA_TSR34 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E88u)
+
+/** Alias (User Manual Name) for DMA_TSR34.
+* To use register names with standard convension, please use DMA_TSR34.
+*/
+#define DMA_TSR034 (DMA_TSR34)
+
+/** \brief 1E8C, DMA Transaction State Register */
+#define DMA_TSR35 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E8Cu)
+
+/** Alias (User Manual Name) for DMA_TSR35.
+* To use register names with standard convension, please use DMA_TSR35.
+*/
+#define DMA_TSR035 (DMA_TSR35)
+
+/** \brief 1E90, DMA Transaction State Register */
+#define DMA_TSR36 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E90u)
+
+/** Alias (User Manual Name) for DMA_TSR36.
+* To use register names with standard convension, please use DMA_TSR36.
+*/
+#define DMA_TSR036 (DMA_TSR36)
+
+/** \brief 1E94, DMA Transaction State Register */
+#define DMA_TSR37 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E94u)
+
+/** Alias (User Manual Name) for DMA_TSR37.
+* To use register names with standard convension, please use DMA_TSR37.
+*/
+#define DMA_TSR037 (DMA_TSR37)
+
+/** \brief 1E98, DMA Transaction State Register */
+#define DMA_TSR38 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E98u)
+
+/** Alias (User Manual Name) for DMA_TSR38.
+* To use register names with standard convension, please use DMA_TSR38.
+*/
+#define DMA_TSR038 (DMA_TSR38)
+
+/** \brief 1E9C, DMA Transaction State Register */
+#define DMA_TSR39 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E9Cu)
+
+/** Alias (User Manual Name) for DMA_TSR39.
+* To use register names with standard convension, please use DMA_TSR39.
+*/
+#define DMA_TSR039 (DMA_TSR39)
+
+/** \brief 1E10, DMA Transaction State Register */
+#define DMA_TSR4 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E10u)
+
+/** Alias (User Manual Name) for DMA_TSR4.
+* To use register names with standard convension, please use DMA_TSR4.
+*/
+#define DMA_TSR004 (DMA_TSR4)
+
+/** \brief 1EA0, DMA Transaction State Register */
+#define DMA_TSR40 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011EA0u)
+
+/** Alias (User Manual Name) for DMA_TSR40.
+* To use register names with standard convension, please use DMA_TSR40.
+*/
+#define DMA_TSR040 (DMA_TSR40)
+
+/** \brief 1EA4, DMA Transaction State Register */
+#define DMA_TSR41 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011EA4u)
+
+/** Alias (User Manual Name) for DMA_TSR41.
+* To use register names with standard convension, please use DMA_TSR41.
+*/
+#define DMA_TSR041 (DMA_TSR41)
+
+/** \brief 1EA8, DMA Transaction State Register */
+#define DMA_TSR42 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011EA8u)
+
+/** Alias (User Manual Name) for DMA_TSR42.
+* To use register names with standard convension, please use DMA_TSR42.
+*/
+#define DMA_TSR042 (DMA_TSR42)
+
+/** \brief 1EAC, DMA Transaction State Register */
+#define DMA_TSR43 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011EACu)
+
+/** Alias (User Manual Name) for DMA_TSR43.
+* To use register names with standard convension, please use DMA_TSR43.
+*/
+#define DMA_TSR043 (DMA_TSR43)
+
+/** \brief 1EB0, DMA Transaction State Register */
+#define DMA_TSR44 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011EB0u)
+
+/** Alias (User Manual Name) for DMA_TSR44.
+* To use register names with standard convension, please use DMA_TSR44.
+*/
+#define DMA_TSR044 (DMA_TSR44)
+
+/** \brief 1EB4, DMA Transaction State Register */
+#define DMA_TSR45 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011EB4u)
+
+/** Alias (User Manual Name) for DMA_TSR45.
+* To use register names with standard convension, please use DMA_TSR45.
+*/
+#define DMA_TSR045 (DMA_TSR45)
+
+/** \brief 1EB8, DMA Transaction State Register */
+#define DMA_TSR46 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011EB8u)
+
+/** Alias (User Manual Name) for DMA_TSR46.
+* To use register names with standard convension, please use DMA_TSR46.
+*/
+#define DMA_TSR046 (DMA_TSR46)
+
+/** \brief 1EBC, DMA Transaction State Register */
+#define DMA_TSR47 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011EBCu)
+
+/** Alias (User Manual Name) for DMA_TSR47.
+* To use register names with standard convension, please use DMA_TSR47.
+*/
+#define DMA_TSR047 (DMA_TSR47)
+
+/** \brief 1E14, DMA Transaction State Register */
+#define DMA_TSR5 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E14u)
+
+/** Alias (User Manual Name) for DMA_TSR5.
+* To use register names with standard convension, please use DMA_TSR5.
+*/
+#define DMA_TSR005 (DMA_TSR5)
+
+/** \brief 1E18, DMA Transaction State Register */
+#define DMA_TSR6 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E18u)
+
+/** Alias (User Manual Name) for DMA_TSR6.
+* To use register names with standard convension, please use DMA_TSR6.
+*/
+#define DMA_TSR006 (DMA_TSR6)
+
+/** \brief 1E1C, DMA Transaction State Register */
+#define DMA_TSR7 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E1Cu)
+
+/** Alias (User Manual Name) for DMA_TSR7.
+* To use register names with standard convension, please use DMA_TSR7.
+*/
+#define DMA_TSR007 (DMA_TSR7)
+
+/** \brief 1E20, DMA Transaction State Register */
+#define DMA_TSR8 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E20u)
+
+/** Alias (User Manual Name) for DMA_TSR8.
+* To use register names with standard convension, please use DMA_TSR8.
+*/
+#define DMA_TSR008 (DMA_TSR8)
+
+/** \brief 1E24, DMA Transaction State Register */
+#define DMA_TSR9 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E24u)
+
+/** Alias (User Manual Name) for DMA_TSR9.
+* To use register names with standard convension, please use DMA_TSR9.
+*/
+#define DMA_TSR009 (DMA_TSR9)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXDMA_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxDma_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxDma_regdef.h
new file mode 100644
index 0000000..3d2104e
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxDma_regdef.h
@@ -0,0 +1,1152 @@
+/**
+ * \file IfxDma_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Dma Dma
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Dma_Bitfields Bitfields
+ * \ingroup IfxLld_Dma
+ *
+ * \defgroup IfxLld_Dma_union Union
+ * \ingroup IfxLld_Dma
+ *
+ * \defgroup IfxLld_Dma_struct Struct
+ * \ingroup IfxLld_Dma
+ *
+ */
+#ifndef IFXDMA_REGDEF_H
+#define IFXDMA_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Dma_Bitfields
+ * \{ */
+
+/** \brief DMA Hardware Resource 0 Access Enable Register 0 */
+typedef struct _Ifx_DMA_ACCEN00_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_DMA_ACCEN00_Bits;
+
+/** \brief DMA Hardware Resource 0 Access Enable Register 1 */
+typedef struct _Ifx_DMA_ACCEN01_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_DMA_ACCEN01_Bits;
+
+/** \brief DMA Hardware Resource 1 Access Enable Register 0 */
+typedef struct _Ifx_DMA_ACCEN10_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_DMA_ACCEN10_Bits;
+
+/** \brief DMA Hardware Resource 1 Access Enable Register 1 */
+typedef struct _Ifx_DMA_ACCEN11_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_DMA_ACCEN11_Bits;
+
+/** \brief DMA Hardware Resource 2 Access Enable Register 0 */
+typedef struct _Ifx_DMA_ACCEN20_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_DMA_ACCEN20_Bits;
+
+/** \brief DMA Hardware Resource 2 Access Enable Register 1 */
+typedef struct _Ifx_DMA_ACCEN21_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_DMA_ACCEN21_Bits;
+
+/** \brief DMA Hardware Resource 3 Access Enable Register 0 */
+typedef struct _Ifx_DMA_ACCEN30_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_DMA_ACCEN30_Bits;
+
+/** \brief DMA Hardware Resource 3 Access Enable Register 1 */
+typedef struct _Ifx_DMA_ACCEN31_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_DMA_ACCEN31_Bits;
+
+/** \brief DMA Clear Error Register */
+typedef struct _Ifx_DMA_BLK_CLRE_Bits
+{
+ unsigned int reserved_0:16; /**< \brief \internal Reserved */
+ unsigned int CSER:1; /**< \brief [16:16] Clear Move Engine x Source Error (w) */
+ unsigned int CDER:1; /**< \brief [17:17] Clear Move Engine x Destination Error (w) */
+ unsigned int reserved_18:2; /**< \brief \internal Reserved */
+ unsigned int CSPBER:1; /**< \brief [20:20] Clear SPB Error (w) */
+ unsigned int CSRIER:1; /**< \brief [21:21] Clear SRI Error (w) */
+ unsigned int reserved_22:2; /**< \brief \internal Reserved */
+ unsigned int CRAMER:1; /**< \brief [24:24] Clear RAM Error (w) */
+ unsigned int CSLLER:1; /**< \brief [25:25] Clear SLL Error (w) */
+ unsigned int CDLLER:1; /**< \brief [26:26] Clear DLL Error (w) */
+ unsigned int reserved_27:5; /**< \brief \internal Reserved */
+} Ifx_DMA_BLK_CLRE_Bits;
+
+/** \brief DMA Enable Error Register */
+typedef struct _Ifx_DMA_BLK_EER_Bits
+{
+ unsigned int reserved_0:16; /**< \brief \internal Reserved */
+ unsigned int ESER:1; /**< \brief [16:16] Enable Move Engine x Source Error (rw) */
+ unsigned int EDER:1; /**< \brief [17:17] Enable Move Engine x Destination Error (rw) */
+ unsigned int reserved_18:6; /**< \brief \internal Reserved */
+ unsigned int ERER:1; /**< \brief [24:24] Enable Move Engine x RAM Error (rw) */
+ unsigned int reserved_25:1; /**< \brief \internal Reserved */
+ unsigned int ELER:1; /**< \brief [26:26] Enable Move Engine x DMA Linked List Error (rw) */
+ unsigned int reserved_27:5; /**< \brief \internal Reserved */
+} Ifx_DMA_BLK_EER_Bits;
+
+/** \brief DMA Error Status Register */
+typedef struct _Ifx_DMA_BLK_ERRSR_Bits
+{
+ unsigned int LEC:7; /**< \brief [6:0] Move Engine x Last Error Channel (rh) */
+ unsigned int reserved_7:9; /**< \brief \internal Reserved */
+ unsigned int SER:1; /**< \brief [16:16] Move Engine x Source Error (rh) */
+ unsigned int DER:1; /**< \brief [17:17] Move Engine x Destination Error (rh) */
+ unsigned int reserved_18:2; /**< \brief \internal Reserved */
+ unsigned int SPBER:1; /**< \brief [20:20] Move Engine x SPB Bus Error (rh) */
+ unsigned int SRIER:1; /**< \brief [21:21] Move Engine x SRI Bus Error (rh) */
+ unsigned int reserved_22:2; /**< \brief \internal Reserved */
+ unsigned int RAMER:1; /**< \brief [24:24] Move Engine x RAM Error (rh) */
+ unsigned int SLLER:1; /**< \brief [25:25] Move Engine x Safe Linked List Error (rh) */
+ unsigned int DLLER:1; /**< \brief [26:26] Move Engine x DMA Linked List Error (rh) */
+ unsigned int reserved_27:5; /**< \brief \internal Reserved */
+} Ifx_DMA_BLK_ERRSR_Bits;
+
+/** \brief DMA Move Engine Channel Address and Interrupt Control Register */
+typedef struct _Ifx_DMA_BLK_ME_ADICR_Bits
+{
+ unsigned int SMF:3; /**< \brief [2:0] Source Address Modification Factor (rh) */
+ unsigned int INCS:1; /**< \brief [3:3] Increment of Source Address (rh) */
+ unsigned int DMF:3; /**< \brief [6:4] Destination Address Modification Factor (rh) */
+ unsigned int INCD:1; /**< \brief [7:7] Increment of Destination Address (rh) */
+ unsigned int CBLS:4; /**< \brief [11:8] Circular Buffer Length Source (rh) */
+ unsigned int CBLD:4; /**< \brief [15:12] Circular Buffer Length Destination (rh) */
+ unsigned int SHCT:4; /**< \brief [19:16] Shadow Control (rh) */
+ unsigned int SCBE:1; /**< \brief [20:20] Source Circular Buffer Enable (rh) */
+ unsigned int DCBE:1; /**< \brief [21:21] Destination Circular Buffer Enable (rh) */
+ unsigned int STAMP:1; /**< \brief [22:22] Time Stamp (rh) */
+ unsigned int ETRL:1; /**< \brief [23:23] Enable Transaction Request Lost Interrupt (rh) */
+ unsigned int WRPSE:1; /**< \brief [24:24] Wrap Source Enable (rh) */
+ unsigned int WRPDE:1; /**< \brief [25:25] Wrap Destination Enable (rh) */
+ unsigned int INTCT:2; /**< \brief [27:26] Interrupt Control (rh) */
+ unsigned int IRDV:4; /**< \brief [31:28] Interrupt Raise Detect Value (rh) */
+} Ifx_DMA_BLK_ME_ADICR_Bits;
+
+/** \brief DMA Move Engine Channel Control Register */
+typedef struct _Ifx_DMA_BLK_ME_CHCR_Bits
+{
+ unsigned int TREL:14; /**< \brief [13:0] Transfer Reload Value (rh) */
+ unsigned int reserved_14:2; /**< \brief \internal Reserved */
+ unsigned int BLKM:3; /**< \brief [18:16] Block Mode (rh) */
+ unsigned int RROAT:1; /**< \brief [19:19] Reset Request Only After Transaction (rh) */
+ unsigned int CHMODE:1; /**< \brief [20:20] Channel Operation Mode (rh) */
+ unsigned int CHDW:3; /**< \brief [23:21] Channel Data Width (rh) */
+ unsigned int PATSEL:3; /**< \brief [26:24] Pattern Select (rh) */
+ unsigned int reserved_27:1; /**< \brief \internal Reserved */
+ unsigned int PRSEL:1; /**< \brief [28:28] Peripheral Request Select (rh) */
+ unsigned int reserved_29:1; /**< \brief \internal Reserved */
+ unsigned int DMAPRIO:2; /**< \brief [31:30] DMA Priority (rh) */
+} Ifx_DMA_BLK_ME_CHCR_Bits;
+
+/** \brief DMA Move Engine Channel Status Register */
+typedef struct _Ifx_DMA_BLK_ME_CHSR_Bits
+{
+ unsigned int TCOUNT:14; /**< \brief [13:0] Transfer Count Status (rh) */
+ unsigned int reserved_14:1; /**< \brief \internal Reserved */
+ unsigned int LXO:1; /**< \brief [15:15] Old Value of Pattern Detection (rh) */
+ unsigned int WRPS:1; /**< \brief [16:16] Wrap Source Buffer (rh) */
+ unsigned int WRPD:1; /**< \brief [17:17] Wrap Destination Buffer (rh) */
+ unsigned int ICH:1; /**< \brief [18:18] Interrupt from Channel (rh) */
+ unsigned int IPM:1; /**< \brief [19:19] Pattern Detection from Channel (rh) */
+ unsigned int reserved_20:2; /**< \brief \internal Reserved */
+ unsigned int BUFFER:1; /**< \brief [22:22] DMA Double Buffering Active Buffer (rh) */
+ unsigned int FROZEN:1; /**< \brief [23:23] DMA Double Buffering Frozen Buffer (rh) */
+ unsigned int reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_DMA_BLK_ME_CHSR_Bits;
+
+/** \brief DMA Move Engine Channel Destination Address Register x */
+typedef struct _Ifx_DMA_BLK_ME_DADR_Bits
+{
+ unsigned int DADR:32; /**< \brief [31:0] Destination Address (rh) */
+} Ifx_DMA_BLK_ME_DADR_Bits;
+
+/** \brief DMA Move Engine Read Register 0 */
+typedef struct _Ifx_DMA_BLK_ME_R0_Bits
+{
+ unsigned int RD00:8; /**< \brief [7:0] Read Value for Move Engine x (rh) */
+ unsigned int RD01:8; /**< \brief [15:8] Read Value for Move Engine x (rh) */
+ unsigned int RD02:8; /**< \brief [23:16] Read Value for Move Engine x (rh) */
+ unsigned int RD03:8; /**< \brief [31:24] Read Value for Move Engine x (rh) */
+} Ifx_DMA_BLK_ME_R0_Bits;
+
+/** \brief DMA Move Engine Read Register 1 */
+typedef struct _Ifx_DMA_BLK_ME_R1_Bits
+{
+ unsigned int RD10:8; /**< \brief [7:0] Read Value for Move Engine x (rh) */
+ unsigned int RD11:8; /**< \brief [15:8] Read Value for Move Engine x (rh) */
+ unsigned int RD12:8; /**< \brief [23:16] Read Value for Move Engine x (rh) */
+ unsigned int RD13:8; /**< \brief [31:24] Read Value for Move Engine x (rh) */
+} Ifx_DMA_BLK_ME_R1_Bits;
+
+/** \brief DMA Move Engine Read Register 2 */
+typedef struct _Ifx_DMA_BLK_ME_R2_Bits
+{
+ unsigned int RD20:8; /**< \brief [7:0] Read Value for Move Engine x (rh) */
+ unsigned int RD21:8; /**< \brief [15:8] Read Value for Move Engine x (rh) */
+ unsigned int RD22:8; /**< \brief [23:16] Read Value for Move Engine x (rh) */
+ unsigned int RD23:8; /**< \brief [31:24] Read Value for Move Engine x (rh) */
+} Ifx_DMA_BLK_ME_R2_Bits;
+
+/** \brief DMA Move Engine Read Register 3 */
+typedef struct _Ifx_DMA_BLK_ME_R3_Bits
+{
+ unsigned int RD30:8; /**< \brief [7:0] Read Value for Move Engine x (rh) */
+ unsigned int RD31:8; /**< \brief [15:8] Read Value for Move Engine x (rh) */
+ unsigned int RD32:8; /**< \brief [23:16] Read Value for Move Engine x (rh) */
+ unsigned int RD33:8; /**< \brief [31:24] Read Value for Move Engine x (rh) */
+} Ifx_DMA_BLK_ME_R3_Bits;
+
+/** \brief DMA Move Engine Read Register 4 */
+typedef struct _Ifx_DMA_BLK_ME_R4_Bits
+{
+ unsigned int RD40:8; /**< \brief [7:0] Read Value for Move Engine x (rh) */
+ unsigned int RD41:8; /**< \brief [15:8] Read Value for Move Engine x (rh) */
+ unsigned int RD42:8; /**< \brief [23:16] Read Value for Move Engine x (rh) */
+ unsigned int RD43:8; /**< \brief [31:24] Read Value for Move Engine x (rh) */
+} Ifx_DMA_BLK_ME_R4_Bits;
+
+/** \brief DMA Move Engine Read Register 5 */
+typedef struct _Ifx_DMA_BLK_ME_R5_Bits
+{
+ unsigned int RD50:8; /**< \brief [7:0] Read Value for Move Engine x (rh) */
+ unsigned int RD51:8; /**< \brief [15:8] Read Value for Move Engine x (rh) */
+ unsigned int RD52:8; /**< \brief [23:16] Read Value for Move Engine x (rh) */
+ unsigned int RD53:8; /**< \brief [31:24] Read Value for Move Engine x (rh) */
+} Ifx_DMA_BLK_ME_R5_Bits;
+
+/** \brief DMA Move Engine Read Register 6 */
+typedef struct _Ifx_DMA_BLK_ME_R6_Bits
+{
+ unsigned int RD60:8; /**< \brief [7:0] Read Value for Move Engine x (rh) */
+ unsigned int RD61:8; /**< \brief [15:8] Read Value for Move Engine x (rh) */
+ unsigned int RD62:8; /**< \brief [23:16] Read Value for Move Engine x (rh) */
+ unsigned int RD63:8; /**< \brief [31:24] Read Value for Move Engine x (rh) */
+} Ifx_DMA_BLK_ME_R6_Bits;
+
+/** \brief DMA Move Engine Read Register 7 */
+typedef struct _Ifx_DMA_BLK_ME_R7_Bits
+{
+ unsigned int RD70:8; /**< \brief [7:0] Read Value for Move Engine x (rh) */
+ unsigned int RD71:8; /**< \brief [15:8] Read Value for Move Engine x (rh) */
+ unsigned int RD72:8; /**< \brief [23:16] Read Value for Move Engine x (rh) */
+ unsigned int RD73:8; /**< \brief [31:24] Read Value for Move Engine x (rh) */
+} Ifx_DMA_BLK_ME_R7_Bits;
+
+/** \brief DMA Move Engine Channel Read Data CRC Register */
+typedef struct _Ifx_DMA_BLK_ME_RDCRC_Bits
+{
+ unsigned int RDCRC:32; /**< \brief [31:0] Read Data CRC (rh) */
+} Ifx_DMA_BLK_ME_RDCRC_Bits;
+
+/** \brief DMA Move Engine Channel Source Address Register */
+typedef struct _Ifx_DMA_BLK_ME_SADR_Bits
+{
+ unsigned int SADR:32; /**< \brief [31:0] Source Start Address (rh) */
+} Ifx_DMA_BLK_ME_SADR_Bits;
+
+/** \brief DMA Move Engine Channel Source and Destination Address CRC Register */
+typedef struct _Ifx_DMA_BLK_ME_SDCRC_Bits
+{
+ unsigned int SDCRC:32; /**< \brief [31:0] Source and Destination Address CRC (rh) */
+} Ifx_DMA_BLK_ME_SDCRC_Bits;
+
+/** \brief DMA Move Engine Channel Shadow Address Register */
+typedef struct _Ifx_DMA_BLK_ME_SHADR_Bits
+{
+ unsigned int SHADR:32; /**< \brief [31:0] Shadowed Address (rh) */
+} Ifx_DMA_BLK_ME_SHADR_Bits;
+
+/** \brief DMA Move Engine Status Register */
+typedef struct _Ifx_DMA_BLK_ME_SR_Bits
+{
+ unsigned int RS:1; /**< \brief [0:0] Move Engine x Read Status (rh) */
+ unsigned int reserved_1:3; /**< \brief \internal Reserved */
+ unsigned int WS:1; /**< \brief [4:4] Move Engine x Write Status (rh) */
+ unsigned int reserved_5:11; /**< \brief \internal Reserved */
+ unsigned int CH:7; /**< \brief [22:16] Active Channel z in Move Engine x (rh) */
+ unsigned int reserved_23:9; /**< \brief \internal Reserved */
+} Ifx_DMA_BLK_ME_SR_Bits;
+
+/** \brief DMA Channel Address and Interrupt Control Register x */
+typedef struct _Ifx_DMA_CH_ADICR_Bits
+{
+ unsigned int SMF:3; /**< \brief [2:0] Source Address Modification Factor (rwh) */
+ unsigned int INCS:1; /**< \brief [3:3] Increment of Source Address (rwh) */
+ unsigned int DMF:3; /**< \brief [6:4] Destination Address Modification Factor (rwh) */
+ unsigned int INCD:1; /**< \brief [7:7] Increment of Destination Address (rwh) */
+ unsigned int CBLS:4; /**< \brief [11:8] Circular Buffer Length Source (rwh) */
+ unsigned int CBLD:4; /**< \brief [15:12] Circular Buffer Length Destination (rwh) */
+ unsigned int SHCT:4; /**< \brief [19:16] Shadow Control (rwh) */
+ unsigned int SCBE:1; /**< \brief [20:20] Source Circular Buffer Enable (rwh) */
+ unsigned int DCBE:1; /**< \brief [21:21] Destination Circular Buffer Enable (rwh) */
+ unsigned int STAMP:1; /**< \brief [22:22] Time Stamp (rwh) */
+ unsigned int ETRL:1; /**< \brief [23:23] Enable Transaction Request Lost Interrupt (rwh) */
+ unsigned int WRPSE:1; /**< \brief [24:24] Wrap Source Enable (rwh) */
+ unsigned int WRPDE:1; /**< \brief [25:25] Wrap Destination Enable (rwh) */
+ unsigned int INTCT:2; /**< \brief [27:26] Interrupt Control (rwh) */
+ unsigned int IRDV:4; /**< \brief [31:28] Interrupt Raise Detect Value (rwh) */
+} Ifx_DMA_CH_ADICR_Bits;
+
+/** \brief DMA Channel Configuration Register */
+typedef struct _Ifx_DMA_CH_CHCFGR_Bits
+{
+ unsigned int TREL:14; /**< \brief [13:0] Transfer Reload Value (rwh) */
+ unsigned int reserved_14:2; /**< \brief \internal Reserved */
+ unsigned int BLKM:3; /**< \brief [18:16] Block Mode (rwh) */
+ unsigned int RROAT:1; /**< \brief [19:19] Reset Request Only After Transaction (rwh) */
+ unsigned int CHMODE:1; /**< \brief [20:20] Channel Operation Mode (rwh) */
+ unsigned int CHDW:3; /**< \brief [23:21] Channel Data Width (rwh) */
+ unsigned int PATSEL:3; /**< \brief [26:24] Pattern Select (rwh) */
+ unsigned int reserved_27:1; /**< \brief \internal Reserved */
+ unsigned int PRSEL:1; /**< \brief [28:28] Peripheral Request Select (rwh) */
+ unsigned int reserved_29:1; /**< \brief \internal Reserved */
+ unsigned int DMAPRIO:2; /**< \brief [31:30] DMA Priority (rwh) */
+} Ifx_DMA_CH_CHCFGR_Bits;
+
+/** \brief DMARAM Channel Control and Status Register */
+typedef struct _Ifx_DMA_CH_CHCSR_Bits
+{
+ unsigned int TCOUNT:14; /**< \brief [13:0] Transfer Count Status (rh) */
+ unsigned int reserved_14:1; /**< \brief \internal Reserved */
+ unsigned int LXO:1; /**< \brief [15:15] Old Value of Pattern Detection (rh) */
+ unsigned int WRPS:1; /**< \brief [16:16] Wrap Source Buffer (rh) */
+ unsigned int WRPD:1; /**< \brief [17:17] Wrap Destination Buffer (rh) */
+ unsigned int ICH:1; /**< \brief [18:18] Interrupt from Channel (rh) */
+ unsigned int IPM:1; /**< \brief [19:19] Pattern Detection from Channel (rh) */
+ unsigned int reserved_20:2; /**< \brief \internal Reserved */
+ unsigned int BUFFER:1; /**< \brief [22:22] DMA Double Buffering Active Buffer (rh) */
+ unsigned int FROZEN:1; /**< \brief [23:23] DMA Double Buffering Frozen Buffer (rwh) */
+ unsigned int SWB:1; /**< \brief [24:24] DMA Double Buffering Switch Buffer (w) */
+ unsigned int CWRP:1; /**< \brief [25:25] Clear Wrap Buffer Interrupt z (w) */
+ unsigned int CICH:1; /**< \brief [26:26] Clear Interrupt for DMA Channel z (w) */
+ unsigned int SIT:1; /**< \brief [27:27] Set Interrupt Trigger for DMA Channel z (w) */
+ unsigned int reserved_28:3; /**< \brief \internal Reserved */
+ unsigned int SCH:1; /**< \brief [31:31] Set Transaction Request for DMA Channel (w) */
+} Ifx_DMA_CH_CHCSR_Bits;
+
+/** \brief DMA Channel Destination Address Register x */
+typedef struct _Ifx_DMA_CH_DADR_Bits
+{
+ unsigned int DADR:32; /**< \brief [31:0] Destination Address (rwh) */
+} Ifx_DMA_CH_DADR_Bits;
+
+/** \brief DMA Channel Read Data CRC Register */
+typedef struct _Ifx_DMA_CH_RDCRCR_Bits
+{
+ unsigned int RDCRC:32; /**< \brief [31:0] Read Data CRC (rwh) */
+} Ifx_DMA_CH_RDCRCR_Bits;
+
+/** \brief DMA Channel Source Address Register */
+typedef struct _Ifx_DMA_CH_SADR_Bits
+{
+ unsigned int SADR:32; /**< \brief [31:0] Source Address (rwh) */
+} Ifx_DMA_CH_SADR_Bits;
+
+/** \brief DMA Channel Source and Destination Address CRC Register */
+typedef struct _Ifx_DMA_CH_SDCRCR_Bits
+{
+ unsigned int SDCRC:32; /**< \brief [31:0] Source and Destination Address CRC (rwh) */
+} Ifx_DMA_CH_SDCRCR_Bits;
+
+/** \brief DMA Channel Shadow Address Register */
+typedef struct _Ifx_DMA_CH_SHADR_Bits
+{
+ unsigned int SHADR:32; /**< \brief [31:0] Shadowed Address (rwh) */
+} Ifx_DMA_CH_SHADR_Bits;
+
+/** \brief DMA Clock Control Register */
+typedef struct _Ifx_DMA_CLC_Bits
+{
+ unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
+ unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
+ unsigned int reserved_2:1; /**< \brief \internal Reserved */
+ unsigned int EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control (rw) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_DMA_CLC_Bits;
+
+/** \brief DMA Error Interrupt Set Register */
+typedef struct _Ifx_DMA_ERRINTR_Bits
+{
+ unsigned int SIT:1; /**< \brief [0:0] Set Error Interrupt Service Request (w) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_DMA_ERRINTR_Bits;
+
+/** \brief DMA Channel Hardware Resource Register */
+typedef struct _Ifx_DMA_HRR_Bits
+{
+ unsigned int HRP:2; /**< \brief [1:0] Hardware Resource Partition y (rw) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_DMA_HRR_Bits;
+
+/** \brief Module Identification Register */
+typedef struct _Ifx_DMA_ID_Bits
+{
+ unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
+ unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_DMA_ID_Bits;
+
+/** \brief DMA Memory Control Register */
+typedef struct _Ifx_DMA_MEMCON_Bits
+{
+ Ifx_Strict_32Bit reserved_0:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit INTERR:1; /**< \brief [2:2] Internal ECC Error (rwh) */
+ Ifx_Strict_32Bit reserved_3:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit RMWERR:1; /**< \brief [4:4] Internal Read Modify Write Error (rwh) */
+ Ifx_Strict_32Bit reserved_5:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit DATAERR:1; /**< \brief [6:6] SPB Data Phase ECC Error (rwh) */
+ Ifx_Strict_32Bit reserved_7:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit PMIC:1; /**< \brief [8:8] Protection Bit for Memory Integrity Control Bit (w) */
+ Ifx_Strict_32Bit ERRDIS:1; /**< \brief [9:9] ECC Error Disable (rw) */
+ Ifx_Strict_32Bit reserved_10:22; /**< \brief \internal Reserved */
+} Ifx_DMA_MEMCON_Bits;
+
+/** \brief DMA Mode Register */
+typedef struct _Ifx_DMA_MODE_Bits
+{
+ unsigned int MODE:1; /**< \brief [0:0] Hardware Resource Supervisor Mode (rw) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_DMA_MODE_Bits;
+
+/** \brief DMA OCDS Trigger Set Select */
+typedef struct _Ifx_DMA_OTSS_Bits
+{
+ unsigned int TGS:4; /**< \brief [3:0] Trigger Set () for OTGB0/1 (rw) */
+ unsigned int reserved_4:3; /**< \brief \internal Reserved */
+ unsigned int BS:1; /**< \brief [7:7] OTGB0/1 Bus Select (rw) */
+ unsigned int reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_DMA_OTSS_Bits;
+
+/** \brief Pattern Read Register 0 */
+typedef struct _Ifx_DMA_PRR0_Bits
+{
+ unsigned int PAT00:8; /**< \brief [7:0] Pattern for Move Engine (rw) */
+ unsigned int PAT01:8; /**< \brief [15:8] Pattern for Move Engine (rw) */
+ unsigned int PAT02:8; /**< \brief [23:16] Pattern for Move Engine (rw) */
+ unsigned int PAT03:8; /**< \brief [31:24] Pattern for Move Engine (rw) */
+} Ifx_DMA_PRR0_Bits;
+
+/** \brief Pattern Read Register 1 */
+typedef struct _Ifx_DMA_PRR1_Bits
+{
+ unsigned int PAT10:8; /**< \brief [7:0] Pattern for Move Engine (rw) */
+ unsigned int PAT11:8; /**< \brief [15:8] Pattern for Move Engine (rw) */
+ unsigned int PAT12:8; /**< \brief [23:16] Pattern for Move Engine (rw) */
+ unsigned int PAT13:8; /**< \brief [31:24] Pattern for Move Engine (rw) */
+} Ifx_DMA_PRR1_Bits;
+
+/** \brief DMA Suspend Acknowledge Register */
+typedef struct _Ifx_DMA_SUSACR_Bits
+{
+ unsigned int SUSAC:1; /**< \brief [0:0] Channel Suspend Mode or Frozen State Active for DMA Channel z (rh) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_DMA_SUSACR_Bits;
+
+/** \brief DMA Suspend Enable Register */
+typedef struct _Ifx_DMA_SUSENR_Bits
+{
+ unsigned int SUSEN:1; /**< \brief [0:0] Channel Suspend Enable for DMA Channel z (rw) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_DMA_SUSENR_Bits;
+
+/** \brief Time Register */
+typedef struct _Ifx_DMA_TIME_Bits
+{
+ unsigned int COUNT:32; /**< \brief [31:0] Timestamp Count (r) */
+} Ifx_DMA_TIME_Bits;
+
+/** \brief DMA Transaction State Register */
+typedef struct _Ifx_DMA_TSR_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] DMA Channel Reset (rwh) */
+ unsigned int HTRE:1; /**< \brief [1:1] Hardware Transaction Request Enable State (rh) */
+ unsigned int TRL:1; /**< \brief [2:2] Transaction/Transfer Request Lost of DMA Channel (rh) */
+ unsigned int CH:1; /**< \brief [3:3] Transaction Request State (rh) */
+ unsigned int reserved_4:4; /**< \brief \internal Reserved */
+ unsigned int HLTREQ:1; /**< \brief [8:8] Halt Request (rwh) */
+ unsigned int HLTACK:1; /**< \brief [9:9] Halt Acknowledge (rh) */
+ unsigned int reserved_10:6; /**< \brief \internal Reserved */
+ unsigned int ECH:1; /**< \brief [16:16] Enable Hardware Transfer Request (w) */
+ unsigned int DCH:1; /**< \brief [17:17] Disable Hardware Transfer Request (w) */
+ unsigned int CTL:1; /**< \brief [18:18] Clear Transaction Request Lost for DMA Channel z (w) */
+ unsigned int reserved_19:5; /**< \brief \internal Reserved */
+ unsigned int HLTCLR:1; /**< \brief [24:24] Clear Halt Request and Acknowledge (w) */
+ unsigned int reserved_25:7; /**< \brief \internal Reserved */
+} Ifx_DMA_TSR_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Dma_union
+ * \{ */
+
+/** \brief DMA Hardware Resource 0 Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_ACCEN00_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_ACCEN00;
+
+/** \brief DMA Hardware Resource 0 Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_ACCEN01_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_ACCEN01;
+
+/** \brief DMA Hardware Resource 1 Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_ACCEN10_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_ACCEN10;
+
+/** \brief DMA Hardware Resource 1 Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_ACCEN11_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_ACCEN11;
+
+/** \brief DMA Hardware Resource 2 Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_ACCEN20_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_ACCEN20;
+
+/** \brief DMA Hardware Resource 2 Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_ACCEN21_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_ACCEN21;
+
+/** \brief DMA Hardware Resource 3 Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_ACCEN30_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_ACCEN30;
+
+/** \brief DMA Hardware Resource 3 Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_ACCEN31_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_ACCEN31;
+
+/** \brief DMA Clear Error Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_BLK_CLRE_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_BLK_CLRE;
+
+/** \brief DMA Enable Error Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_BLK_EER_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_BLK_EER;
+
+/** \brief DMA Error Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_BLK_ERRSR_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_BLK_ERRSR;
+
+/** \brief DMA Move Engine Channel Address and Interrupt Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_BLK_ME_ADICR_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_BLK_ME_ADICR;
+
+/** \brief DMA Move Engine Channel Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_BLK_ME_CHCR_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_BLK_ME_CHCR;
+
+/** \brief DMA Move Engine Channel Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_BLK_ME_CHSR_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_BLK_ME_CHSR;
+
+/** \brief DMA Move Engine Channel Destination Address Register x */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_BLK_ME_DADR_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_BLK_ME_DADR;
+
+/** \brief DMA Move Engine Read Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_BLK_ME_R0_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_BLK_ME_R0;
+
+/** \brief DMA Move Engine Read Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_BLK_ME_R1_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_BLK_ME_R1;
+
+/** \brief DMA Move Engine Read Register 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_BLK_ME_R2_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_BLK_ME_R2;
+
+/** \brief DMA Move Engine Read Register 3 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_BLK_ME_R3_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_BLK_ME_R3;
+
+/** \brief DMA Move Engine Read Register 4 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_BLK_ME_R4_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_BLK_ME_R4;
+
+/** \brief DMA Move Engine Read Register 5 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_BLK_ME_R5_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_BLK_ME_R5;
+
+/** \brief DMA Move Engine Read Register 6 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_BLK_ME_R6_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_BLK_ME_R6;
+
+/** \brief DMA Move Engine Read Register 7 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_BLK_ME_R7_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_BLK_ME_R7;
+
+/** \brief DMA Move Engine Channel Read Data CRC Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_BLK_ME_RDCRC_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_BLK_ME_RDCRC;
+
+/** \brief DMA Move Engine Channel Source Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_BLK_ME_SADR_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_BLK_ME_SADR;
+
+/** \brief DMA Move Engine Channel Source and Destination Address CRC Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_BLK_ME_SDCRC_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_BLK_ME_SDCRC;
+
+/** \brief DMA Move Engine Channel Shadow Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_BLK_ME_SHADR_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_BLK_ME_SHADR;
+
+/** \brief DMA Move Engine Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_BLK_ME_SR_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_BLK_ME_SR;
+
+/** \brief DMA Channel Address and Interrupt Control Register x */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_CH_ADICR_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_CH_ADICR;
+
+/** \brief DMA Channel Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_CH_CHCFGR_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_CH_CHCFGR;
+
+/** \brief DMARAM Channel Control and Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_CH_CHCSR_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_CH_CHCSR;
+
+/** \brief DMA Channel Destination Address Register x */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_CH_DADR_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_CH_DADR;
+
+/** \brief DMA Channel Read Data CRC Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_CH_RDCRCR_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_CH_RDCRCR;
+
+/** \brief DMA Channel Source Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_CH_SADR_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_CH_SADR;
+
+/** \brief DMA Channel Source and Destination Address CRC Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_CH_SDCRCR_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_CH_SDCRCR;
+
+/** \brief DMA Channel Shadow Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_CH_SHADR_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_CH_SHADR;
+
+/** \brief DMA Clock Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_CLC_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_CLC;
+
+/** \brief DMA Error Interrupt Set Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_ERRINTR_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_ERRINTR;
+
+/** \brief DMA Channel Hardware Resource Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_HRR_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_HRR;
+
+/** \brief Module Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_ID;
+
+/** \brief DMA Memory Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_MEMCON_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_MEMCON;
+
+/** \brief DMA Mode Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_MODE_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_MODE;
+
+/** \brief DMA OCDS Trigger Set Select */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_OTSS_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_OTSS;
+
+/** \brief Pattern Read Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_PRR0_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_PRR0;
+
+/** \brief Pattern Read Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_PRR1_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_PRR1;
+
+/** \brief DMA Suspend Acknowledge Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_SUSACR_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_SUSACR;
+
+/** \brief DMA Suspend Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_SUSENR_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_SUSENR;
+
+/** \brief Time Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_TIME_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_TIME;
+
+/** \brief DMA Transaction State Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DMA_TSR_Bits B; /**< \brief Bitfield access */
+} Ifx_DMA_TSR;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Dma_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L2
+ * \{ */
+
+/** \brief DMA move engine */
+typedef volatile struct _Ifx_DMA_BLK_ME
+{
+ Ifx_DMA_BLK_ME_SR SR; /**< \brief 0, DMA Move Engine Status Register */
+ unsigned char reserved_4[12]; /**< \brief 4, \internal Reserved */
+ Ifx_DMA_BLK_ME_R0 R0; /**< \brief 10, DMA Move Engine Read Register 0 */
+ Ifx_DMA_BLK_ME_R1 R1; /**< \brief 14, DMA Move Engine Read Register 1 */
+ Ifx_DMA_BLK_ME_R2 R2; /**< \brief 18, DMA Move Engine Read Register 2 */
+ Ifx_DMA_BLK_ME_R3 R3; /**< \brief 1C, DMA Move Engine Read Register 3 */
+ Ifx_DMA_BLK_ME_R4 R4; /**< \brief 20, DMA Move Engine Read Register 4 */
+ Ifx_DMA_BLK_ME_R5 R5; /**< \brief 24, DMA Move Engine Read Register 5 */
+ Ifx_DMA_BLK_ME_R6 R6; /**< \brief 28, DMA Move Engine Read Register 6 */
+ Ifx_DMA_BLK_ME_R7 R7; /**< \brief 2C, DMA Move Engine Read Register 7 */
+ unsigned char reserved_30[32]; /**< \brief 30, \internal Reserved */
+ Ifx_DMA_BLK_ME_RDCRC RDCRC; /**< \brief 50, DMA Move Engine Channel Read Data CRC Register */
+ Ifx_DMA_BLK_ME_SDCRC SDCRC; /**< \brief 54, DMA Move Engine Channel Source and Destination Address CRC Register */
+ Ifx_DMA_BLK_ME_SADR SADR; /**< \brief 58, DMA Move Engine Channel Source Address Register */
+ Ifx_DMA_BLK_ME_DADR DADR; /**< \brief 5C, DMA Move Engine Channel Destination Address Register x */
+ Ifx_DMA_BLK_ME_ADICR ADICR; /**< \brief 60, DMA Move Engine Channel Address and Interrupt Control Register */
+ Ifx_DMA_BLK_ME_CHCR CHCR; /**< \brief 64, DMA Move Engine Channel Control Register */
+ Ifx_DMA_BLK_ME_SHADR SHADR; /**< \brief 68, DMA Move Engine Channel Shadow Address Register */
+ Ifx_DMA_BLK_ME_CHSR CHSR; /**< \brief 6C, DMA Move Engine Channel Status Register */
+} Ifx_DMA_BLK_ME;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Dma_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L1
+ * \{ */
+
+/** \brief DMA sub block */
+typedef volatile struct _Ifx_DMA_BLK
+{
+ Ifx_DMA_BLK_EER EER; /**< \brief 0, DMA Enable Error Register */
+ Ifx_DMA_BLK_ERRSR ERRSR; /**< \brief 4, DMA Error Status Register */
+ Ifx_DMA_BLK_CLRE CLRE; /**< \brief 8, DMA Clear Error Register */
+ unsigned char reserved_C[4]; /**< \brief C, \internal Reserved */
+ Ifx_DMA_BLK_ME ME; /**< \brief 10, DMA move engine */
+} Ifx_DMA_BLK;
+
+/** \brief DMA channels */
+typedef volatile struct _Ifx_DMA_CH
+{
+ Ifx_DMA_CH_RDCRCR RDCRCR; /**< \brief 0, DMA Channel Read Data CRC Register */
+ Ifx_DMA_CH_SDCRCR SDCRCR; /**< \brief 4, DMA Channel Source and Destination Address CRC Register */
+ Ifx_DMA_CH_SADR SADR; /**< \brief 8, DMA Channel Source Address Register */
+ Ifx_DMA_CH_DADR DADR; /**< \brief C, DMA Channel Destination Address Register x */
+ Ifx_DMA_CH_ADICR ADICR; /**< \brief 10, DMA Channel Address and Interrupt Control Register x */
+ Ifx_DMA_CH_CHCFGR CHCFGR; /**< \brief 14, DMA Channel Configuration Register */
+ Ifx_DMA_CH_SHADR SHADR; /**< \brief 18, DMA Channel Shadow Address Register */
+ Ifx_DMA_CH_CHCSR CHCSR; /**< \brief 1C, DMARAM Channel Control and Status Register */
+} Ifx_DMA_CH;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Dma_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief DMA object */
+typedef volatile struct _Ifx_DMA
+{
+ Ifx_DMA_CLC CLC; /**< \brief 0, DMA Clock Control Register */
+ unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
+ Ifx_DMA_ID ID; /**< \brief 8, Module Identification Register */
+ unsigned char reserved_C[20]; /**< \brief C, \internal Reserved */
+ Ifx_DMA_MEMCON MEMCON; /**< \brief 20, DMA Memory Control Register */
+ unsigned char reserved_24[28]; /**< \brief 24, \internal Reserved */
+ Ifx_DMA_ACCEN00 ACCEN00; /**< \brief 40, DMA Hardware Resource 0 Access Enable Register 0 */
+ Ifx_DMA_ACCEN01 ACCEN01; /**< \brief 44, DMA Hardware Resource 0 Access Enable Register 1 */
+ Ifx_DMA_ACCEN10 ACCEN10; /**< \brief 48, DMA Hardware Resource 1 Access Enable Register 0 */
+ Ifx_DMA_ACCEN11 ACCEN11; /**< \brief 4C, DMA Hardware Resource 1 Access Enable Register 1 */
+ Ifx_DMA_ACCEN20 ACCEN20; /**< \brief 50, DMA Hardware Resource 2 Access Enable Register 0 */
+ Ifx_DMA_ACCEN21 ACCEN21; /**< \brief 54, DMA Hardware Resource 2 Access Enable Register 1 */
+ Ifx_DMA_ACCEN30 ACCEN30; /**< \brief 58, DMA Hardware Resource 3 Access Enable Register 0 */
+ Ifx_DMA_ACCEN31 ACCEN31; /**< \brief 5C, DMA Hardware Resource 3 Access Enable Register 1 */
+ unsigned char reserved_60[192]; /**< \brief 60, \internal Reserved */
+ Ifx_DMA_BLK BLK0; /**< \brief 120, DMA sub block 0 */
+ unsigned char reserved_1A0[3968]; /**< \brief 1A0, \internal Reserved */
+ Ifx_DMA_BLK BLK1; /**< \brief 1120, DMA sub block 1 */
+ unsigned char reserved_11A0[96]; /**< \brief 11A0, \internal Reserved */
+ Ifx_DMA_OTSS OTSS; /**< \brief 1200, DMA OCDS Trigger Set Select */
+ Ifx_DMA_ERRINTR ERRINTR; /**< \brief 1204, DMA Error Interrupt Set Register */
+ Ifx_DMA_PRR0 PRR0; /**< \brief 1208, Pattern Read Register 0 */
+ Ifx_DMA_PRR1 PRR1; /**< \brief 120C, Pattern Read Register 1 */
+ Ifx_DMA_TIME TIME; /**< \brief 1210, Time Register */
+ unsigned char reserved_1214[236]; /**< \brief 1214, \internal Reserved */
+ Ifx_DMA_MODE MODE[4]; /**< \brief 1300, DMA Mode Register */
+ unsigned char reserved_1310[1264]; /**< \brief 1310, \internal Reserved */
+ Ifx_DMA_HRR HRR[48]; /**< \brief 1800, DMA Channel Hardware Resource Register */
+ unsigned char reserved_18C0[320]; /**< \brief 18C0, \internal Reserved */
+ Ifx_DMA_SUSENR SUSENR[48]; /**< \brief 1A00, DMA Suspend Enable Register */
+ unsigned char reserved_1AC0[320]; /**< \brief 1AC0, \internal Reserved */
+ Ifx_DMA_SUSACR SUSACR[48]; /**< \brief 1C00, DMA Suspend Acknowledge Register */
+ unsigned char reserved_1CC0[320]; /**< \brief 1CC0, \internal Reserved */
+ Ifx_DMA_TSR TSR[48]; /**< \brief 1E00, DMA Transaction State Register */
+ unsigned char reserved_1EC0[320]; /**< \brief 1EC0, \internal Reserved */
+ Ifx_DMA_CH CH[48]; /**< \brief 2000, DMA channels */
+ unsigned char reserved_2600[6656]; /**< \brief 2600, \internal Reserved */
+} Ifx_DMA;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXDMA_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxDsadc_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxDsadc_bf.h
new file mode 100644
index 0000000..877d50e
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxDsadc_bf.h
@@ -0,0 +1,1647 @@
+/**
+ * \file IfxDsadc_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Dsadc_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Dsadc
+ *
+ */
+#ifndef IFXDSADC_BF_H
+#define IFXDSADC_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Dsadc_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN0 */
+#define IFX_DSADC_ACCEN0_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN0 */
+#define IFX_DSADC_ACCEN0_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN0 */
+#define IFX_DSADC_ACCEN0_EN0_OFF (0u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN10 */
+#define IFX_DSADC_ACCEN0_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN10 */
+#define IFX_DSADC_ACCEN0_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN10 */
+#define IFX_DSADC_ACCEN0_EN10_OFF (10u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN11 */
+#define IFX_DSADC_ACCEN0_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN11 */
+#define IFX_DSADC_ACCEN0_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN11 */
+#define IFX_DSADC_ACCEN0_EN11_OFF (11u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN12 */
+#define IFX_DSADC_ACCEN0_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN12 */
+#define IFX_DSADC_ACCEN0_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN12 */
+#define IFX_DSADC_ACCEN0_EN12_OFF (12u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN13 */
+#define IFX_DSADC_ACCEN0_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN13 */
+#define IFX_DSADC_ACCEN0_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN13 */
+#define IFX_DSADC_ACCEN0_EN13_OFF (13u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN14 */
+#define IFX_DSADC_ACCEN0_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN14 */
+#define IFX_DSADC_ACCEN0_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN14 */
+#define IFX_DSADC_ACCEN0_EN14_OFF (14u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN15 */
+#define IFX_DSADC_ACCEN0_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN15 */
+#define IFX_DSADC_ACCEN0_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN15 */
+#define IFX_DSADC_ACCEN0_EN15_OFF (15u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN16 */
+#define IFX_DSADC_ACCEN0_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN16 */
+#define IFX_DSADC_ACCEN0_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN16 */
+#define IFX_DSADC_ACCEN0_EN16_OFF (16u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN17 */
+#define IFX_DSADC_ACCEN0_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN17 */
+#define IFX_DSADC_ACCEN0_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN17 */
+#define IFX_DSADC_ACCEN0_EN17_OFF (17u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN18 */
+#define IFX_DSADC_ACCEN0_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN18 */
+#define IFX_DSADC_ACCEN0_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN18 */
+#define IFX_DSADC_ACCEN0_EN18_OFF (18u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN19 */
+#define IFX_DSADC_ACCEN0_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN19 */
+#define IFX_DSADC_ACCEN0_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN19 */
+#define IFX_DSADC_ACCEN0_EN19_OFF (19u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN1 */
+#define IFX_DSADC_ACCEN0_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN1 */
+#define IFX_DSADC_ACCEN0_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN1 */
+#define IFX_DSADC_ACCEN0_EN1_OFF (1u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN20 */
+#define IFX_DSADC_ACCEN0_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN20 */
+#define IFX_DSADC_ACCEN0_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN20 */
+#define IFX_DSADC_ACCEN0_EN20_OFF (20u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN21 */
+#define IFX_DSADC_ACCEN0_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN21 */
+#define IFX_DSADC_ACCEN0_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN21 */
+#define IFX_DSADC_ACCEN0_EN21_OFF (21u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN22 */
+#define IFX_DSADC_ACCEN0_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN22 */
+#define IFX_DSADC_ACCEN0_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN22 */
+#define IFX_DSADC_ACCEN0_EN22_OFF (22u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN23 */
+#define IFX_DSADC_ACCEN0_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN23 */
+#define IFX_DSADC_ACCEN0_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN23 */
+#define IFX_DSADC_ACCEN0_EN23_OFF (23u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN24 */
+#define IFX_DSADC_ACCEN0_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN24 */
+#define IFX_DSADC_ACCEN0_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN24 */
+#define IFX_DSADC_ACCEN0_EN24_OFF (24u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN25 */
+#define IFX_DSADC_ACCEN0_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN25 */
+#define IFX_DSADC_ACCEN0_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN25 */
+#define IFX_DSADC_ACCEN0_EN25_OFF (25u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN26 */
+#define IFX_DSADC_ACCEN0_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN26 */
+#define IFX_DSADC_ACCEN0_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN26 */
+#define IFX_DSADC_ACCEN0_EN26_OFF (26u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN27 */
+#define IFX_DSADC_ACCEN0_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN27 */
+#define IFX_DSADC_ACCEN0_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN27 */
+#define IFX_DSADC_ACCEN0_EN27_OFF (27u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN28 */
+#define IFX_DSADC_ACCEN0_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN28 */
+#define IFX_DSADC_ACCEN0_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN28 */
+#define IFX_DSADC_ACCEN0_EN28_OFF (28u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN29 */
+#define IFX_DSADC_ACCEN0_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN29 */
+#define IFX_DSADC_ACCEN0_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN29 */
+#define IFX_DSADC_ACCEN0_EN29_OFF (29u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN2 */
+#define IFX_DSADC_ACCEN0_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN2 */
+#define IFX_DSADC_ACCEN0_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN2 */
+#define IFX_DSADC_ACCEN0_EN2_OFF (2u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN30 */
+#define IFX_DSADC_ACCEN0_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN30 */
+#define IFX_DSADC_ACCEN0_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN30 */
+#define IFX_DSADC_ACCEN0_EN30_OFF (30u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN31 */
+#define IFX_DSADC_ACCEN0_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN31 */
+#define IFX_DSADC_ACCEN0_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN31 */
+#define IFX_DSADC_ACCEN0_EN31_OFF (31u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN3 */
+#define IFX_DSADC_ACCEN0_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN3 */
+#define IFX_DSADC_ACCEN0_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN3 */
+#define IFX_DSADC_ACCEN0_EN3_OFF (3u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN4 */
+#define IFX_DSADC_ACCEN0_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN4 */
+#define IFX_DSADC_ACCEN0_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN4 */
+#define IFX_DSADC_ACCEN0_EN4_OFF (4u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN5 */
+#define IFX_DSADC_ACCEN0_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN5 */
+#define IFX_DSADC_ACCEN0_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN5 */
+#define IFX_DSADC_ACCEN0_EN5_OFF (5u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN6 */
+#define IFX_DSADC_ACCEN0_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN6 */
+#define IFX_DSADC_ACCEN0_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN6 */
+#define IFX_DSADC_ACCEN0_EN6_OFF (6u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN7 */
+#define IFX_DSADC_ACCEN0_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN7 */
+#define IFX_DSADC_ACCEN0_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN7 */
+#define IFX_DSADC_ACCEN0_EN7_OFF (7u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN8 */
+#define IFX_DSADC_ACCEN0_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN8 */
+#define IFX_DSADC_ACCEN0_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN8 */
+#define IFX_DSADC_ACCEN0_EN8_OFF (8u)
+
+/** \brief Length for Ifx_DSADC_ACCEN0_Bits.EN9 */
+#define IFX_DSADC_ACCEN0_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCEN0_Bits.EN9 */
+#define IFX_DSADC_ACCEN0_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCEN0_Bits.EN9 */
+#define IFX_DSADC_ACCEN0_EN9_OFF (9u)
+
+/** \brief Length for Ifx_DSADC_ACCPROT_Bits.RG00 */
+#define IFX_DSADC_ACCPROT_RG00_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCPROT_Bits.RG00 */
+#define IFX_DSADC_ACCPROT_RG00_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCPROT_Bits.RG00 */
+#define IFX_DSADC_ACCPROT_RG00_OFF (0u)
+
+/** \brief Length for Ifx_DSADC_ACCPROT_Bits.RG01 */
+#define IFX_DSADC_ACCPROT_RG01_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCPROT_Bits.RG01 */
+#define IFX_DSADC_ACCPROT_RG01_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCPROT_Bits.RG01 */
+#define IFX_DSADC_ACCPROT_RG01_OFF (1u)
+
+/** \brief Length for Ifx_DSADC_ACCPROT_Bits.RG02 */
+#define IFX_DSADC_ACCPROT_RG02_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCPROT_Bits.RG02 */
+#define IFX_DSADC_ACCPROT_RG02_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCPROT_Bits.RG02 */
+#define IFX_DSADC_ACCPROT_RG02_OFF (2u)
+
+/** \brief Length for Ifx_DSADC_ACCPROT_Bits.RG03 */
+#define IFX_DSADC_ACCPROT_RG03_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCPROT_Bits.RG03 */
+#define IFX_DSADC_ACCPROT_RG03_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCPROT_Bits.RG03 */
+#define IFX_DSADC_ACCPROT_RG03_OFF (3u)
+
+/** \brief Length for Ifx_DSADC_ACCPROT_Bits.RG04 */
+#define IFX_DSADC_ACCPROT_RG04_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCPROT_Bits.RG04 */
+#define IFX_DSADC_ACCPROT_RG04_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCPROT_Bits.RG04 */
+#define IFX_DSADC_ACCPROT_RG04_OFF (4u)
+
+/** \brief Length for Ifx_DSADC_ACCPROT_Bits.RG10 */
+#define IFX_DSADC_ACCPROT_RG10_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCPROT_Bits.RG10 */
+#define IFX_DSADC_ACCPROT_RG10_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCPROT_Bits.RG10 */
+#define IFX_DSADC_ACCPROT_RG10_OFF (14u)
+
+/** \brief Length for Ifx_DSADC_ACCPROT_Bits.RG11 */
+#define IFX_DSADC_ACCPROT_RG11_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_ACCPROT_Bits.RG11 */
+#define IFX_DSADC_ACCPROT_RG11_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_ACCPROT_Bits.RG11 */
+#define IFX_DSADC_ACCPROT_RG11_OFF (15u)
+
+/** \brief Length for Ifx_DSADC_CGCFG_Bits.BITCOUNT */
+#define IFX_DSADC_CGCFG_BITCOUNT_LEN (5u)
+
+/** \brief Mask for Ifx_DSADC_CGCFG_Bits.BITCOUNT */
+#define IFX_DSADC_CGCFG_BITCOUNT_MSK (0x1fu)
+
+/** \brief Offset for Ifx_DSADC_CGCFG_Bits.BITCOUNT */
+#define IFX_DSADC_CGCFG_BITCOUNT_OFF (16u)
+
+/** \brief Length for Ifx_DSADC_CGCFG_Bits.BREV */
+#define IFX_DSADC_CGCFG_BREV_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CGCFG_Bits.BREV */
+#define IFX_DSADC_CGCFG_BREV_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CGCFG_Bits.BREV */
+#define IFX_DSADC_CGCFG_BREV_OFF (2u)
+
+/** \brief Length for Ifx_DSADC_CGCFG_Bits.CGMOD */
+#define IFX_DSADC_CGCFG_CGMOD_LEN (2u)
+
+/** \brief Mask for Ifx_DSADC_CGCFG_Bits.CGMOD */
+#define IFX_DSADC_CGCFG_CGMOD_MSK (0x3u)
+
+/** \brief Offset for Ifx_DSADC_CGCFG_Bits.CGMOD */
+#define IFX_DSADC_CGCFG_CGMOD_OFF (0u)
+
+/** \brief Length for Ifx_DSADC_CGCFG_Bits.DIVCG */
+#define IFX_DSADC_CGCFG_DIVCG_LEN (4u)
+
+/** \brief Mask for Ifx_DSADC_CGCFG_Bits.DIVCG */
+#define IFX_DSADC_CGCFG_DIVCG_MSK (0xfu)
+
+/** \brief Offset for Ifx_DSADC_CGCFG_Bits.DIVCG */
+#define IFX_DSADC_CGCFG_DIVCG_OFF (4u)
+
+/** \brief Length for Ifx_DSADC_CGCFG_Bits.RUN */
+#define IFX_DSADC_CGCFG_RUN_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CGCFG_Bits.RUN */
+#define IFX_DSADC_CGCFG_RUN_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CGCFG_Bits.RUN */
+#define IFX_DSADC_CGCFG_RUN_OFF (15u)
+
+/** \brief Length for Ifx_DSADC_CGCFG_Bits.SGNCG */
+#define IFX_DSADC_CGCFG_SGNCG_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CGCFG_Bits.SGNCG */
+#define IFX_DSADC_CGCFG_SGNCG_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CGCFG_Bits.SGNCG */
+#define IFX_DSADC_CGCFG_SGNCG_OFF (30u)
+
+/** \brief Length for Ifx_DSADC_CGCFG_Bits.SIGPOL */
+#define IFX_DSADC_CGCFG_SIGPOL_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CGCFG_Bits.SIGPOL */
+#define IFX_DSADC_CGCFG_SIGPOL_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CGCFG_Bits.SIGPOL */
+#define IFX_DSADC_CGCFG_SIGPOL_OFF (3u)
+
+/** \brief Length for Ifx_DSADC_CGCFG_Bits.STEPCOUNT */
+#define IFX_DSADC_CGCFG_STEPCOUNT_LEN (4u)
+
+/** \brief Mask for Ifx_DSADC_CGCFG_Bits.STEPCOUNT */
+#define IFX_DSADC_CGCFG_STEPCOUNT_MSK (0xfu)
+
+/** \brief Offset for Ifx_DSADC_CGCFG_Bits.STEPCOUNT */
+#define IFX_DSADC_CGCFG_STEPCOUNT_OFF (24u)
+
+/** \brief Length for Ifx_DSADC_CGCFG_Bits.STEPD */
+#define IFX_DSADC_CGCFG_STEPD_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CGCFG_Bits.STEPD */
+#define IFX_DSADC_CGCFG_STEPD_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CGCFG_Bits.STEPD */
+#define IFX_DSADC_CGCFG_STEPD_OFF (29u)
+
+/** \brief Length for Ifx_DSADC_CGCFG_Bits.STEPS */
+#define IFX_DSADC_CGCFG_STEPS_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CGCFG_Bits.STEPS */
+#define IFX_DSADC_CGCFG_STEPS_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CGCFG_Bits.STEPS */
+#define IFX_DSADC_CGCFG_STEPS_OFF (28u)
+
+/** \brief Length for Ifx_DSADC_CH_BOUNDSEL_Bits.BOUNDARYL */
+#define IFX_DSADC_CH_BOUNDSEL_BOUNDARYL_LEN (16u)
+
+/** \brief Mask for Ifx_DSADC_CH_BOUNDSEL_Bits.BOUNDARYL */
+#define IFX_DSADC_CH_BOUNDSEL_BOUNDARYL_MSK (0xffffu)
+
+/** \brief Offset for Ifx_DSADC_CH_BOUNDSEL_Bits.BOUNDARYL */
+#define IFX_DSADC_CH_BOUNDSEL_BOUNDARYL_OFF (0u)
+
+/** \brief Length for Ifx_DSADC_CH_BOUNDSEL_Bits.BOUNDARYU */
+#define IFX_DSADC_CH_BOUNDSEL_BOUNDARYU_LEN (16u)
+
+/** \brief Mask for Ifx_DSADC_CH_BOUNDSEL_Bits.BOUNDARYU */
+#define IFX_DSADC_CH_BOUNDSEL_BOUNDARYU_MSK (0xffffu)
+
+/** \brief Offset for Ifx_DSADC_CH_BOUNDSEL_Bits.BOUNDARYU */
+#define IFX_DSADC_CH_BOUNDSEL_BOUNDARYU_OFF (16u)
+
+/** \brief Length for Ifx_DSADC_CH_CGSYNC_Bits.SDCAP */
+#define IFX_DSADC_CH_CGSYNC_SDCAP_LEN (8u)
+
+/** \brief Mask for Ifx_DSADC_CH_CGSYNC_Bits.SDCAP */
+#define IFX_DSADC_CH_CGSYNC_SDCAP_MSK (0xffu)
+
+/** \brief Offset for Ifx_DSADC_CH_CGSYNC_Bits.SDCAP */
+#define IFX_DSADC_CH_CGSYNC_SDCAP_OFF (8u)
+
+/** \brief Length for Ifx_DSADC_CH_CGSYNC_Bits.SDCOUNT */
+#define IFX_DSADC_CH_CGSYNC_SDCOUNT_LEN (8u)
+
+/** \brief Mask for Ifx_DSADC_CH_CGSYNC_Bits.SDCOUNT */
+#define IFX_DSADC_CH_CGSYNC_SDCOUNT_MSK (0xffu)
+
+/** \brief Offset for Ifx_DSADC_CH_CGSYNC_Bits.SDCOUNT */
+#define IFX_DSADC_CH_CGSYNC_SDCOUNT_OFF (0u)
+
+/** \brief Length for Ifx_DSADC_CH_CGSYNC_Bits.SDNEG */
+#define IFX_DSADC_CH_CGSYNC_SDNEG_LEN (8u)
+
+/** \brief Mask for Ifx_DSADC_CH_CGSYNC_Bits.SDNEG */
+#define IFX_DSADC_CH_CGSYNC_SDNEG_MSK (0xffu)
+
+/** \brief Offset for Ifx_DSADC_CH_CGSYNC_Bits.SDNEG */
+#define IFX_DSADC_CH_CGSYNC_SDNEG_OFF (24u)
+
+/** \brief Length for Ifx_DSADC_CH_CGSYNC_Bits.SDPOS */
+#define IFX_DSADC_CH_CGSYNC_SDPOS_LEN (8u)
+
+/** \brief Mask for Ifx_DSADC_CH_CGSYNC_Bits.SDPOS */
+#define IFX_DSADC_CH_CGSYNC_SDPOS_MSK (0xffu)
+
+/** \brief Offset for Ifx_DSADC_CH_CGSYNC_Bits.SDPOS */
+#define IFX_DSADC_CH_CGSYNC_SDPOS_OFF (16u)
+
+/** \brief Length for Ifx_DSADC_CH_DICFG_Bits.CSRC */
+#define IFX_DSADC_CH_DICFG_CSRC_LEN (4u)
+
+/** \brief Mask for Ifx_DSADC_CH_DICFG_Bits.CSRC */
+#define IFX_DSADC_CH_DICFG_CSRC_MSK (0xfu)
+
+/** \brief Offset for Ifx_DSADC_CH_DICFG_Bits.CSRC */
+#define IFX_DSADC_CH_DICFG_CSRC_OFF (16u)
+
+/** \brief Length for Ifx_DSADC_CH_DICFG_Bits.DSRC */
+#define IFX_DSADC_CH_DICFG_DSRC_LEN (4u)
+
+/** \brief Mask for Ifx_DSADC_CH_DICFG_Bits.DSRC */
+#define IFX_DSADC_CH_DICFG_DSRC_MSK (0xfu)
+
+/** \brief Offset for Ifx_DSADC_CH_DICFG_Bits.DSRC */
+#define IFX_DSADC_CH_DICFG_DSRC_OFF (0u)
+
+/** \brief Length for Ifx_DSADC_CH_DICFG_Bits.DSWC */
+#define IFX_DSADC_CH_DICFG_DSWC_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CH_DICFG_Bits.DSWC */
+#define IFX_DSADC_CH_DICFG_DSWC_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CH_DICFG_Bits.DSWC */
+#define IFX_DSADC_CH_DICFG_DSWC_OFF (7u)
+
+/** \brief Length for Ifx_DSADC_CH_DICFG_Bits.ITRMODE */
+#define IFX_DSADC_CH_DICFG_ITRMODE_LEN (2u)
+
+/** \brief Mask for Ifx_DSADC_CH_DICFG_Bits.ITRMODE */
+#define IFX_DSADC_CH_DICFG_ITRMODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_DSADC_CH_DICFG_Bits.ITRMODE */
+#define IFX_DSADC_CH_DICFG_ITRMODE_OFF (8u)
+
+/** \brief Length for Ifx_DSADC_CH_DICFG_Bits.SCWC */
+#define IFX_DSADC_CH_DICFG_SCWC_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CH_DICFG_Bits.SCWC */
+#define IFX_DSADC_CH_DICFG_SCWC_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CH_DICFG_Bits.SCWC */
+#define IFX_DSADC_CH_DICFG_SCWC_OFF (31u)
+
+/** \brief Length for Ifx_DSADC_CH_DICFG_Bits.STROBE */
+#define IFX_DSADC_CH_DICFG_STROBE_LEN (4u)
+
+/** \brief Mask for Ifx_DSADC_CH_DICFG_Bits.STROBE */
+#define IFX_DSADC_CH_DICFG_STROBE_MSK (0xfu)
+
+/** \brief Offset for Ifx_DSADC_CH_DICFG_Bits.STROBE */
+#define IFX_DSADC_CH_DICFG_STROBE_OFF (20u)
+
+/** \brief Length for Ifx_DSADC_CH_DICFG_Bits.TRSEL */
+#define IFX_DSADC_CH_DICFG_TRSEL_LEN (3u)
+
+/** \brief Mask for Ifx_DSADC_CH_DICFG_Bits.TRSEL */
+#define IFX_DSADC_CH_DICFG_TRSEL_MSK (0x7u)
+
+/** \brief Offset for Ifx_DSADC_CH_DICFG_Bits.TRSEL */
+#define IFX_DSADC_CH_DICFG_TRSEL_OFF (12u)
+
+/** \brief Length for Ifx_DSADC_CH_DICFG_Bits.TRWC */
+#define IFX_DSADC_CH_DICFG_TRWC_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CH_DICFG_Bits.TRWC */
+#define IFX_DSADC_CH_DICFG_TRWC_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CH_DICFG_Bits.TRWC */
+#define IFX_DSADC_CH_DICFG_TRWC_OFF (15u)
+
+/** \brief Length for Ifx_DSADC_CH_DICFG_Bits.TSTRMODE */
+#define IFX_DSADC_CH_DICFG_TSTRMODE_LEN (2u)
+
+/** \brief Mask for Ifx_DSADC_CH_DICFG_Bits.TSTRMODE */
+#define IFX_DSADC_CH_DICFG_TSTRMODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_DSADC_CH_DICFG_Bits.TSTRMODE */
+#define IFX_DSADC_CH_DICFG_TSTRMODE_OFF (10u)
+
+/** \brief Length for Ifx_DSADC_CH_FCFGA_Bits.AFSC */
+#define IFX_DSADC_CH_FCFGA_AFSC_LEN (2u)
+
+/** \brief Mask for Ifx_DSADC_CH_FCFGA_Bits.AFSC */
+#define IFX_DSADC_CH_FCFGA_AFSC_MSK (0x3u)
+
+/** \brief Offset for Ifx_DSADC_CH_FCFGA_Bits.AFSC */
+#define IFX_DSADC_CH_FCFGA_AFSC_OFF (16u)
+
+/** \brief Length for Ifx_DSADC_CH_FCFGA_Bits.CFAC */
+#define IFX_DSADC_CH_FCFGA_CFAC_LEN (2u)
+
+/** \brief Mask for Ifx_DSADC_CH_FCFGA_Bits.CFAC */
+#define IFX_DSADC_CH_FCFGA_CFAC_MSK (0x3u)
+
+/** \brief Offset for Ifx_DSADC_CH_FCFGA_Bits.CFAC */
+#define IFX_DSADC_CH_FCFGA_CFAC_OFF (8u)
+
+/** \brief Length for Ifx_DSADC_CH_FCFGA_Bits.CFADCNT */
+#define IFX_DSADC_CH_FCFGA_CFADCNT_LEN (8u)
+
+/** \brief Mask for Ifx_DSADC_CH_FCFGA_Bits.CFADCNT */
+#define IFX_DSADC_CH_FCFGA_CFADCNT_MSK (0xffu)
+
+/** \brief Offset for Ifx_DSADC_CH_FCFGA_Bits.CFADCNT */
+#define IFX_DSADC_CH_FCFGA_CFADCNT_OFF (24u)
+
+/** \brief Length for Ifx_DSADC_CH_FCFGA_Bits.CFADF */
+#define IFX_DSADC_CH_FCFGA_CFADF_LEN (8u)
+
+/** \brief Mask for Ifx_DSADC_CH_FCFGA_Bits.CFADF */
+#define IFX_DSADC_CH_FCFGA_CFADF_MSK (0xffu)
+
+/** \brief Offset for Ifx_DSADC_CH_FCFGA_Bits.CFADF */
+#define IFX_DSADC_CH_FCFGA_CFADF_OFF (0u)
+
+/** \brief Length for Ifx_DSADC_CH_FCFGA_Bits.EGT */
+#define IFX_DSADC_CH_FCFGA_EGT_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CH_FCFGA_Bits.EGT */
+#define IFX_DSADC_CH_FCFGA_EGT_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CH_FCFGA_Bits.EGT */
+#define IFX_DSADC_CH_FCFGA_EGT_OFF (14u)
+
+/** \brief Length for Ifx_DSADC_CH_FCFGA_Bits.ESEL */
+#define IFX_DSADC_CH_FCFGA_ESEL_LEN (2u)
+
+/** \brief Mask for Ifx_DSADC_CH_FCFGA_Bits.ESEL */
+#define IFX_DSADC_CH_FCFGA_ESEL_MSK (0x3u)
+
+/** \brief Offset for Ifx_DSADC_CH_FCFGA_Bits.ESEL */
+#define IFX_DSADC_CH_FCFGA_ESEL_OFF (12u)
+
+/** \brief Length for Ifx_DSADC_CH_FCFGA_Bits.SRGA */
+#define IFX_DSADC_CH_FCFGA_SRGA_LEN (2u)
+
+/** \brief Mask for Ifx_DSADC_CH_FCFGA_Bits.SRGA */
+#define IFX_DSADC_CH_FCFGA_SRGA_MSK (0x3u)
+
+/** \brief Offset for Ifx_DSADC_CH_FCFGA_Bits.SRGA */
+#define IFX_DSADC_CH_FCFGA_SRGA_OFF (10u)
+
+/** \brief Length for Ifx_DSADC_CH_FCFGC_Bits.CFEN */
+#define IFX_DSADC_CH_FCFGC_CFEN_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CH_FCFGC_Bits.CFEN */
+#define IFX_DSADC_CH_FCFGC_CFEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CH_FCFGC_Bits.CFEN */
+#define IFX_DSADC_CH_FCFGC_CFEN_OFF (10u)
+
+/** \brief Length for Ifx_DSADC_CH_FCFGC_Bits.CFMC */
+#define IFX_DSADC_CH_FCFGC_CFMC_LEN (2u)
+
+/** \brief Mask for Ifx_DSADC_CH_FCFGC_Bits.CFMC */
+#define IFX_DSADC_CH_FCFGC_CFMC_MSK (0x3u)
+
+/** \brief Offset for Ifx_DSADC_CH_FCFGC_Bits.CFMC */
+#define IFX_DSADC_CH_FCFGC_CFMC_OFF (8u)
+
+/** \brief Length for Ifx_DSADC_CH_FCFGC_Bits.CFMDCNT */
+#define IFX_DSADC_CH_FCFGC_CFMDCNT_LEN (8u)
+
+/** \brief Mask for Ifx_DSADC_CH_FCFGC_Bits.CFMDCNT */
+#define IFX_DSADC_CH_FCFGC_CFMDCNT_MSK (0xffu)
+
+/** \brief Offset for Ifx_DSADC_CH_FCFGC_Bits.CFMDCNT */
+#define IFX_DSADC_CH_FCFGC_CFMDCNT_OFF (24u)
+
+/** \brief Length for Ifx_DSADC_CH_FCFGC_Bits.CFMDF */
+#define IFX_DSADC_CH_FCFGC_CFMDF_LEN (8u)
+
+/** \brief Mask for Ifx_DSADC_CH_FCFGC_Bits.CFMDF */
+#define IFX_DSADC_CH_FCFGC_CFMDF_MSK (0xffu)
+
+/** \brief Offset for Ifx_DSADC_CH_FCFGC_Bits.CFMDF */
+#define IFX_DSADC_CH_FCFGC_CFMDF_OFF (0u)
+
+/** \brief Length for Ifx_DSADC_CH_FCFGC_Bits.CFMSV */
+#define IFX_DSADC_CH_FCFGC_CFMSV_LEN (8u)
+
+/** \brief Mask for Ifx_DSADC_CH_FCFGC_Bits.CFMSV */
+#define IFX_DSADC_CH_FCFGC_CFMSV_MSK (0xffu)
+
+/** \brief Offset for Ifx_DSADC_CH_FCFGC_Bits.CFMSV */
+#define IFX_DSADC_CH_FCFGC_CFMSV_OFF (16u)
+
+/** \brief Length for Ifx_DSADC_CH_FCFGC_Bits.MFSC */
+#define IFX_DSADC_CH_FCFGC_MFSC_LEN (2u)
+
+/** \brief Mask for Ifx_DSADC_CH_FCFGC_Bits.MFSC */
+#define IFX_DSADC_CH_FCFGC_MFSC_MSK (0x3u)
+
+/** \brief Offset for Ifx_DSADC_CH_FCFGC_Bits.MFSC */
+#define IFX_DSADC_CH_FCFGC_MFSC_OFF (12u)
+
+/** \brief Length for Ifx_DSADC_CH_FCFGC_Bits.SRGM */
+#define IFX_DSADC_CH_FCFGC_SRGM_LEN (2u)
+
+/** \brief Mask for Ifx_DSADC_CH_FCFGC_Bits.SRGM */
+#define IFX_DSADC_CH_FCFGC_SRGM_MSK (0x3u)
+
+/** \brief Offset for Ifx_DSADC_CH_FCFGC_Bits.SRGM */
+#define IFX_DSADC_CH_FCFGC_SRGM_OFF (14u)
+
+/** \brief Length for Ifx_DSADC_CH_FCFGM_Bits.DSH */
+#define IFX_DSADC_CH_FCFGM_DSH_LEN (2u)
+
+/** \brief Mask for Ifx_DSADC_CH_FCFGM_Bits.DSH */
+#define IFX_DSADC_CH_FCFGM_DSH_MSK (0x3u)
+
+/** \brief Offset for Ifx_DSADC_CH_FCFGM_Bits.DSH */
+#define IFX_DSADC_CH_FCFGM_DSH_OFF (3u)
+
+/** \brief Length for Ifx_DSADC_CH_FCFGM_Bits.FIR0EN */
+#define IFX_DSADC_CH_FCFGM_FIR0EN_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CH_FCFGM_Bits.FIR0EN */
+#define IFX_DSADC_CH_FCFGM_FIR0EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CH_FCFGM_Bits.FIR0EN */
+#define IFX_DSADC_CH_FCFGM_FIR0EN_OFF (0u)
+
+/** \brief Length for Ifx_DSADC_CH_FCFGM_Bits.FIR1EN */
+#define IFX_DSADC_CH_FCFGM_FIR1EN_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CH_FCFGM_Bits.FIR1EN */
+#define IFX_DSADC_CH_FCFGM_FIR1EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CH_FCFGM_Bits.FIR1EN */
+#define IFX_DSADC_CH_FCFGM_FIR1EN_OFF (1u)
+
+/** \brief Length for Ifx_DSADC_CH_FCFGM_Bits.FSH */
+#define IFX_DSADC_CH_FCFGM_FSH_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CH_FCFGM_Bits.FSH */
+#define IFX_DSADC_CH_FCFGM_FSH_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CH_FCFGM_Bits.FSH */
+#define IFX_DSADC_CH_FCFGM_FSH_OFF (5u)
+
+/** \brief Length for Ifx_DSADC_CH_FCFGM_Bits.OCEN */
+#define IFX_DSADC_CH_FCFGM_OCEN_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CH_FCFGM_Bits.OCEN */
+#define IFX_DSADC_CH_FCFGM_OCEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CH_FCFGM_Bits.OCEN */
+#define IFX_DSADC_CH_FCFGM_OCEN_OFF (2u)
+
+/** \brief Length for Ifx_DSADC_CH_ICCFG_Bits.DI0 */
+#define IFX_DSADC_CH_ICCFG_DI0_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CH_ICCFG_Bits.DI0 */
+#define IFX_DSADC_CH_ICCFG_DI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CH_ICCFG_Bits.DI0 */
+#define IFX_DSADC_CH_ICCFG_DI0_OFF (0u)
+
+/** \brief Length for Ifx_DSADC_CH_ICCFG_Bits.DI1 */
+#define IFX_DSADC_CH_ICCFG_DI1_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CH_ICCFG_Bits.DI1 */
+#define IFX_DSADC_CH_ICCFG_DI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CH_ICCFG_Bits.DI1 */
+#define IFX_DSADC_CH_ICCFG_DI1_OFF (1u)
+
+/** \brief Length for Ifx_DSADC_CH_ICCFG_Bits.IREN */
+#define IFX_DSADC_CH_ICCFG_IREN_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CH_ICCFG_Bits.IREN */
+#define IFX_DSADC_CH_ICCFG_IREN_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CH_ICCFG_Bits.IREN */
+#define IFX_DSADC_CH_ICCFG_IREN_OFF (4u)
+
+/** \brief Length for Ifx_DSADC_CH_ICCFG_Bits.TWINSP */
+#define IFX_DSADC_CH_ICCFG_TWINSP_LEN (6u)
+
+/** \brief Mask for Ifx_DSADC_CH_ICCFG_Bits.TWINSP */
+#define IFX_DSADC_CH_ICCFG_TWINSP_MSK (0x3fu)
+
+/** \brief Offset for Ifx_DSADC_CH_ICCFG_Bits.TWINSP */
+#define IFX_DSADC_CH_ICCFG_TWINSP_OFF (8u)
+
+/** \brief Length for Ifx_DSADC_CH_ICCFG_Bits.WREN */
+#define IFX_DSADC_CH_ICCFG_WREN_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CH_ICCFG_Bits.WREN */
+#define IFX_DSADC_CH_ICCFG_WREN_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CH_ICCFG_Bits.WREN */
+#define IFX_DSADC_CH_ICCFG_WREN_OFF (31u)
+
+/** \brief Length for Ifx_DSADC_CH_IWCTR_Bits.INTEN */
+#define IFX_DSADC_CH_IWCTR_INTEN_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CH_IWCTR_Bits.INTEN */
+#define IFX_DSADC_CH_IWCTR_INTEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CH_IWCTR_Bits.INTEN */
+#define IFX_DSADC_CH_IWCTR_INTEN_OFF (7u)
+
+/** \brief Length for Ifx_DSADC_CH_IWCTR_Bits.IWS */
+#define IFX_DSADC_CH_IWCTR_IWS_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CH_IWCTR_Bits.IWS */
+#define IFX_DSADC_CH_IWCTR_IWS_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CH_IWCTR_Bits.IWS */
+#define IFX_DSADC_CH_IWCTR_IWS_OFF (23u)
+
+/** \brief Length for Ifx_DSADC_CH_IWCTR_Bits.NVALCNT */
+#define IFX_DSADC_CH_IWCTR_NVALCNT_LEN (6u)
+
+/** \brief Mask for Ifx_DSADC_CH_IWCTR_Bits.NVALCNT */
+#define IFX_DSADC_CH_IWCTR_NVALCNT_MSK (0x3fu)
+
+/** \brief Offset for Ifx_DSADC_CH_IWCTR_Bits.NVALCNT */
+#define IFX_DSADC_CH_IWCTR_NVALCNT_OFF (0u)
+
+/** \brief Length for Ifx_DSADC_CH_IWCTR_Bits.NVALDIS */
+#define IFX_DSADC_CH_IWCTR_NVALDIS_LEN (6u)
+
+/** \brief Mask for Ifx_DSADC_CH_IWCTR_Bits.NVALDIS */
+#define IFX_DSADC_CH_IWCTR_NVALDIS_MSK (0x3fu)
+
+/** \brief Offset for Ifx_DSADC_CH_IWCTR_Bits.NVALDIS */
+#define IFX_DSADC_CH_IWCTR_NVALDIS_OFF (16u)
+
+/** \brief Length for Ifx_DSADC_CH_IWCTR_Bits.NVALINT */
+#define IFX_DSADC_CH_IWCTR_NVALINT_LEN (6u)
+
+/** \brief Mask for Ifx_DSADC_CH_IWCTR_Bits.NVALINT */
+#define IFX_DSADC_CH_IWCTR_NVALINT_MSK (0x3fu)
+
+/** \brief Offset for Ifx_DSADC_CH_IWCTR_Bits.NVALINT */
+#define IFX_DSADC_CH_IWCTR_NVALINT_OFF (24u)
+
+/** \brief Length for Ifx_DSADC_CH_IWCTR_Bits.REPCNT */
+#define IFX_DSADC_CH_IWCTR_REPCNT_LEN (4u)
+
+/** \brief Mask for Ifx_DSADC_CH_IWCTR_Bits.REPCNT */
+#define IFX_DSADC_CH_IWCTR_REPCNT_MSK (0xfu)
+
+/** \brief Offset for Ifx_DSADC_CH_IWCTR_Bits.REPCNT */
+#define IFX_DSADC_CH_IWCTR_REPCNT_OFF (8u)
+
+/** \brief Length for Ifx_DSADC_CH_IWCTR_Bits.REPVAL */
+#define IFX_DSADC_CH_IWCTR_REPVAL_LEN (4u)
+
+/** \brief Mask for Ifx_DSADC_CH_IWCTR_Bits.REPVAL */
+#define IFX_DSADC_CH_IWCTR_REPVAL_MSK (0xfu)
+
+/** \brief Offset for Ifx_DSADC_CH_IWCTR_Bits.REPVAL */
+#define IFX_DSADC_CH_IWCTR_REPVAL_OFF (12u)
+
+/** \brief Length for Ifx_DSADC_CH_MODCFG_Bits.APC */
+#define IFX_DSADC_CH_MODCFG_APC_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CH_MODCFG_Bits.APC */
+#define IFX_DSADC_CH_MODCFG_APC_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CH_MODCFG_Bits.APC */
+#define IFX_DSADC_CH_MODCFG_APC_OFF (29u)
+
+/** \brief Length for Ifx_DSADC_CH_MODCFG_Bits.CMVS */
+#define IFX_DSADC_CH_MODCFG_CMVS_LEN (2u)
+
+/** \brief Mask for Ifx_DSADC_CH_MODCFG_Bits.CMVS */
+#define IFX_DSADC_CH_MODCFG_CMVS_MSK (0x3u)
+
+/** \brief Offset for Ifx_DSADC_CH_MODCFG_Bits.CMVS */
+#define IFX_DSADC_CH_MODCFG_CMVS_OFF (24u)
+
+/** \brief Length for Ifx_DSADC_CH_MODCFG_Bits.DIVM */
+#define IFX_DSADC_CH_MODCFG_DIVM_LEN (4u)
+
+/** \brief Mask for Ifx_DSADC_CH_MODCFG_Bits.DIVM */
+#define IFX_DSADC_CH_MODCFG_DIVM_MSK (0xfu)
+
+/** \brief Offset for Ifx_DSADC_CH_MODCFG_Bits.DIVM */
+#define IFX_DSADC_CH_MODCFG_DIVM_OFF (16u)
+
+/** \brief Length for Ifx_DSADC_CH_MODCFG_Bits.DWC */
+#define IFX_DSADC_CH_MODCFG_DWC_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CH_MODCFG_Bits.DWC */
+#define IFX_DSADC_CH_MODCFG_DWC_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CH_MODCFG_Bits.DWC */
+#define IFX_DSADC_CH_MODCFG_DWC_OFF (23u)
+
+/** \brief Length for Ifx_DSADC_CH_MODCFG_Bits.GAINSEL */
+#define IFX_DSADC_CH_MODCFG_GAINSEL_LEN (4u)
+
+/** \brief Mask for Ifx_DSADC_CH_MODCFG_Bits.GAINSEL */
+#define IFX_DSADC_CH_MODCFG_GAINSEL_MSK (0xfu)
+
+/** \brief Offset for Ifx_DSADC_CH_MODCFG_Bits.GAINSEL */
+#define IFX_DSADC_CH_MODCFG_GAINSEL_OFF (4u)
+
+/** \brief Length for Ifx_DSADC_CH_MODCFG_Bits.GCEN */
+#define IFX_DSADC_CH_MODCFG_GCEN_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CH_MODCFG_Bits.GCEN */
+#define IFX_DSADC_CH_MODCFG_GCEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CH_MODCFG_Bits.GCEN */
+#define IFX_DSADC_CH_MODCFG_GCEN_OFF (28u)
+
+/** \brief Length for Ifx_DSADC_CH_MODCFG_Bits.INCFGN */
+#define IFX_DSADC_CH_MODCFG_INCFGN_LEN (2u)
+
+/** \brief Mask for Ifx_DSADC_CH_MODCFG_Bits.INCFGN */
+#define IFX_DSADC_CH_MODCFG_INCFGN_MSK (0x3u)
+
+/** \brief Offset for Ifx_DSADC_CH_MODCFG_Bits.INCFGN */
+#define IFX_DSADC_CH_MODCFG_INCFGN_OFF (2u)
+
+/** \brief Length for Ifx_DSADC_CH_MODCFG_Bits.INCFGP */
+#define IFX_DSADC_CH_MODCFG_INCFGP_LEN (2u)
+
+/** \brief Mask for Ifx_DSADC_CH_MODCFG_Bits.INCFGP */
+#define IFX_DSADC_CH_MODCFG_INCFGP_MSK (0x3u)
+
+/** \brief Offset for Ifx_DSADC_CH_MODCFG_Bits.INCFGP */
+#define IFX_DSADC_CH_MODCFG_INCFGP_OFF (0u)
+
+/** \brief Length for Ifx_DSADC_CH_MODCFG_Bits.INCWC */
+#define IFX_DSADC_CH_MODCFG_INCWC_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CH_MODCFG_Bits.INCWC */
+#define IFX_DSADC_CH_MODCFG_INCWC_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CH_MODCFG_Bits.INCWC */
+#define IFX_DSADC_CH_MODCFG_INCWC_OFF (15u)
+
+/** \brief Length for Ifx_DSADC_CH_MODCFG_Bits.INMAC */
+#define IFX_DSADC_CH_MODCFG_INMAC_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CH_MODCFG_Bits.INMAC */
+#define IFX_DSADC_CH_MODCFG_INMAC_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CH_MODCFG_Bits.INMAC */
+#define IFX_DSADC_CH_MODCFG_INMAC_OFF (14u)
+
+/** \brief Length for Ifx_DSADC_CH_MODCFG_Bits.INMODE */
+#define IFX_DSADC_CH_MODCFG_INMODE_LEN (2u)
+
+/** \brief Mask for Ifx_DSADC_CH_MODCFG_Bits.INMODE */
+#define IFX_DSADC_CH_MODCFG_INMODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_DSADC_CH_MODCFG_Bits.INMODE */
+#define IFX_DSADC_CH_MODCFG_INMODE_OFF (12u)
+
+/** \brief Length for Ifx_DSADC_CH_MODCFG_Bits.INMUX */
+#define IFX_DSADC_CH_MODCFG_INMUX_LEN (2u)
+
+/** \brief Mask for Ifx_DSADC_CH_MODCFG_Bits.INMUX */
+#define IFX_DSADC_CH_MODCFG_INMUX_MSK (0x3u)
+
+/** \brief Offset for Ifx_DSADC_CH_MODCFG_Bits.INMUX */
+#define IFX_DSADC_CH_MODCFG_INMUX_OFF (10u)
+
+/** \brief Length for Ifx_DSADC_CH_MODCFG_Bits.INSEL */
+#define IFX_DSADC_CH_MODCFG_INSEL_LEN (2u)
+
+/** \brief Mask for Ifx_DSADC_CH_MODCFG_Bits.INSEL */
+#define IFX_DSADC_CH_MODCFG_INSEL_MSK (0x3u)
+
+/** \brief Offset for Ifx_DSADC_CH_MODCFG_Bits.INSEL */
+#define IFX_DSADC_CH_MODCFG_INSEL_OFF (8u)
+
+/** \brief Length for Ifx_DSADC_CH_MODCFG_Bits.MCFG */
+#define IFX_DSADC_CH_MODCFG_MCFG_LEN (2u)
+
+/** \brief Mask for Ifx_DSADC_CH_MODCFG_Bits.MCFG */
+#define IFX_DSADC_CH_MODCFG_MCFG_MSK (0x3u)
+
+/** \brief Offset for Ifx_DSADC_CH_MODCFG_Bits.MCFG */
+#define IFX_DSADC_CH_MODCFG_MCFG_OFF (26u)
+
+/** \brief Length for Ifx_DSADC_CH_MODCFG_Bits.MWC */
+#define IFX_DSADC_CH_MODCFG_MWC_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CH_MODCFG_Bits.MWC */
+#define IFX_DSADC_CH_MODCFG_MWC_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CH_MODCFG_Bits.MWC */
+#define IFX_DSADC_CH_MODCFG_MWC_OFF (31u)
+
+/** \brief Length for Ifx_DSADC_CH_OFFM_Bits.OFFSET */
+#define IFX_DSADC_CH_OFFM_OFFSET_LEN (16u)
+
+/** \brief Mask for Ifx_DSADC_CH_OFFM_Bits.OFFSET */
+#define IFX_DSADC_CH_OFFM_OFFSET_MSK (0xffffu)
+
+/** \brief Offset for Ifx_DSADC_CH_OFFM_Bits.OFFSET */
+#define IFX_DSADC_CH_OFFM_OFFSET_OFF (0u)
+
+/** \brief Length for Ifx_DSADC_CH_RECTCFG_Bits.RFEN */
+#define IFX_DSADC_CH_RECTCFG_RFEN_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CH_RECTCFG_Bits.RFEN */
+#define IFX_DSADC_CH_RECTCFG_RFEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CH_RECTCFG_Bits.RFEN */
+#define IFX_DSADC_CH_RECTCFG_RFEN_OFF (0u)
+
+/** \brief Length for Ifx_DSADC_CH_RECTCFG_Bits.SDCVAL */
+#define IFX_DSADC_CH_RECTCFG_SDCVAL_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CH_RECTCFG_Bits.SDCVAL */
+#define IFX_DSADC_CH_RECTCFG_SDCVAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CH_RECTCFG_Bits.SDCVAL */
+#define IFX_DSADC_CH_RECTCFG_SDCVAL_OFF (15u)
+
+/** \brief Length for Ifx_DSADC_CH_RECTCFG_Bits.SGNCS */
+#define IFX_DSADC_CH_RECTCFG_SGNCS_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CH_RECTCFG_Bits.SGNCS */
+#define IFX_DSADC_CH_RECTCFG_SGNCS_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CH_RECTCFG_Bits.SGNCS */
+#define IFX_DSADC_CH_RECTCFG_SGNCS_OFF (30u)
+
+/** \brief Length for Ifx_DSADC_CH_RECTCFG_Bits.SGND */
+#define IFX_DSADC_CH_RECTCFG_SGND_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CH_RECTCFG_Bits.SGND */
+#define IFX_DSADC_CH_RECTCFG_SGND_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CH_RECTCFG_Bits.SGND */
+#define IFX_DSADC_CH_RECTCFG_SGND_OFF (31u)
+
+/** \brief Length for Ifx_DSADC_CH_RECTCFG_Bits.SSRC */
+#define IFX_DSADC_CH_RECTCFG_SSRC_LEN (2u)
+
+/** \brief Mask for Ifx_DSADC_CH_RECTCFG_Bits.SSRC */
+#define IFX_DSADC_CH_RECTCFG_SSRC_MSK (0x3u)
+
+/** \brief Offset for Ifx_DSADC_CH_RECTCFG_Bits.SSRC */
+#define IFX_DSADC_CH_RECTCFG_SSRC_OFF (4u)
+
+/** \brief Length for Ifx_DSADC_CH_RESA_Bits.RESULT */
+#define IFX_DSADC_CH_RESA_RESULT_LEN (16u)
+
+/** \brief Mask for Ifx_DSADC_CH_RESA_Bits.RESULT */
+#define IFX_DSADC_CH_RESA_RESULT_MSK (0xffffu)
+
+/** \brief Offset for Ifx_DSADC_CH_RESA_Bits.RESULT */
+#define IFX_DSADC_CH_RESA_RESULT_OFF (0u)
+
+/** \brief Length for Ifx_DSADC_CH_RESM_Bits.RESULT */
+#define IFX_DSADC_CH_RESM_RESULT_LEN (16u)
+
+/** \brief Mask for Ifx_DSADC_CH_RESM_Bits.RESULT */
+#define IFX_DSADC_CH_RESM_RESULT_MSK (0xffffu)
+
+/** \brief Offset for Ifx_DSADC_CH_RESM_Bits.RESULT */
+#define IFX_DSADC_CH_RESM_RESULT_OFF (0u)
+
+/** \brief Length for Ifx_DSADC_CH_TSTMP_Bits.CFMDCNT */
+#define IFX_DSADC_CH_TSTMP_CFMDCNT_LEN (8u)
+
+/** \brief Mask for Ifx_DSADC_CH_TSTMP_Bits.CFMDCNT */
+#define IFX_DSADC_CH_TSTMP_CFMDCNT_MSK (0xffu)
+
+/** \brief Offset for Ifx_DSADC_CH_TSTMP_Bits.CFMDCNT */
+#define IFX_DSADC_CH_TSTMP_CFMDCNT_OFF (16u)
+
+/** \brief Length for Ifx_DSADC_CH_TSTMP_Bits.NVALCNT */
+#define IFX_DSADC_CH_TSTMP_NVALCNT_LEN (6u)
+
+/** \brief Mask for Ifx_DSADC_CH_TSTMP_Bits.NVALCNT */
+#define IFX_DSADC_CH_TSTMP_NVALCNT_MSK (0x3fu)
+
+/** \brief Offset for Ifx_DSADC_CH_TSTMP_Bits.NVALCNT */
+#define IFX_DSADC_CH_TSTMP_NVALCNT_OFF (24u)
+
+/** \brief Length for Ifx_DSADC_CH_TSTMP_Bits.RESULT */
+#define IFX_DSADC_CH_TSTMP_RESULT_LEN (16u)
+
+/** \brief Mask for Ifx_DSADC_CH_TSTMP_Bits.RESULT */
+#define IFX_DSADC_CH_TSTMP_RESULT_MSK (0xffffu)
+
+/** \brief Offset for Ifx_DSADC_CH_TSTMP_Bits.RESULT */
+#define IFX_DSADC_CH_TSTMP_RESULT_OFF (0u)
+
+/** \brief Length for Ifx_DSADC_CH_TSTMP_Bits.TSSR */
+#define IFX_DSADC_CH_TSTMP_TSSR_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CH_TSTMP_Bits.TSSR */
+#define IFX_DSADC_CH_TSTMP_TSSR_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CH_TSTMP_Bits.TSSR */
+#define IFX_DSADC_CH_TSTMP_TSSR_OFF (31u)
+
+/** \brief Length for Ifx_DSADC_CH_TSTMP_Bits.TSVAL */
+#define IFX_DSADC_CH_TSTMP_TSVAL_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CH_TSTMP_Bits.TSVAL */
+#define IFX_DSADC_CH_TSTMP_TSVAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CH_TSTMP_Bits.TSVAL */
+#define IFX_DSADC_CH_TSTMP_TSVAL_OFF (30u)
+
+/** \brief Length for Ifx_DSADC_CLC_Bits.DISR */
+#define IFX_DSADC_CLC_DISR_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CLC_Bits.DISR */
+#define IFX_DSADC_CLC_DISR_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CLC_Bits.DISR */
+#define IFX_DSADC_CLC_DISR_OFF (0u)
+
+/** \brief Length for Ifx_DSADC_CLC_Bits.DISS */
+#define IFX_DSADC_CLC_DISS_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CLC_Bits.DISS */
+#define IFX_DSADC_CLC_DISS_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CLC_Bits.DISS */
+#define IFX_DSADC_CLC_DISS_OFF (1u)
+
+/** \brief Length for Ifx_DSADC_CLC_Bits.EDIS */
+#define IFX_DSADC_CLC_EDIS_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_CLC_Bits.EDIS */
+#define IFX_DSADC_CLC_EDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_CLC_Bits.EDIS */
+#define IFX_DSADC_CLC_EDIS_OFF (3u)
+
+/** \brief Length for Ifx_DSADC_EVFLAG_Bits.ALEV0 */
+#define IFX_DSADC_EVFLAG_ALEV0_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_EVFLAG_Bits.ALEV0 */
+#define IFX_DSADC_EVFLAG_ALEV0_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_EVFLAG_Bits.ALEV0 */
+#define IFX_DSADC_EVFLAG_ALEV0_OFF (16u)
+
+/** \brief Length for Ifx_DSADC_EVFLAG_Bits.ALEV2 */
+#define IFX_DSADC_EVFLAG_ALEV2_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_EVFLAG_Bits.ALEV2 */
+#define IFX_DSADC_EVFLAG_ALEV2_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_EVFLAG_Bits.ALEV2 */
+#define IFX_DSADC_EVFLAG_ALEV2_OFF (18u)
+
+/** \brief Length for Ifx_DSADC_EVFLAG_Bits.ALEV3 */
+#define IFX_DSADC_EVFLAG_ALEV3_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_EVFLAG_Bits.ALEV3 */
+#define IFX_DSADC_EVFLAG_ALEV3_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_EVFLAG_Bits.ALEV3 */
+#define IFX_DSADC_EVFLAG_ALEV3_OFF (19u)
+
+/** \brief Length for Ifx_DSADC_EVFLAG_Bits.RESEV0 */
+#define IFX_DSADC_EVFLAG_RESEV0_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_EVFLAG_Bits.RESEV0 */
+#define IFX_DSADC_EVFLAG_RESEV0_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_EVFLAG_Bits.RESEV0 */
+#define IFX_DSADC_EVFLAG_RESEV0_OFF (0u)
+
+/** \brief Length for Ifx_DSADC_EVFLAG_Bits.RESEV2 */
+#define IFX_DSADC_EVFLAG_RESEV2_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_EVFLAG_Bits.RESEV2 */
+#define IFX_DSADC_EVFLAG_RESEV2_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_EVFLAG_Bits.RESEV2 */
+#define IFX_DSADC_EVFLAG_RESEV2_OFF (2u)
+
+/** \brief Length for Ifx_DSADC_EVFLAG_Bits.RESEV3 */
+#define IFX_DSADC_EVFLAG_RESEV3_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_EVFLAG_Bits.RESEV3 */
+#define IFX_DSADC_EVFLAG_RESEV3_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_EVFLAG_Bits.RESEV3 */
+#define IFX_DSADC_EVFLAG_RESEV3_OFF (3u)
+
+/** \brief Length for Ifx_DSADC_EVFLAGCLR_Bits.ALEC0 */
+#define IFX_DSADC_EVFLAGCLR_ALEC0_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_EVFLAGCLR_Bits.ALEC0 */
+#define IFX_DSADC_EVFLAGCLR_ALEC0_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_EVFLAGCLR_Bits.ALEC0 */
+#define IFX_DSADC_EVFLAGCLR_ALEC0_OFF (16u)
+
+/** \brief Length for Ifx_DSADC_EVFLAGCLR_Bits.ALEC2 */
+#define IFX_DSADC_EVFLAGCLR_ALEC2_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_EVFLAGCLR_Bits.ALEC2 */
+#define IFX_DSADC_EVFLAGCLR_ALEC2_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_EVFLAGCLR_Bits.ALEC2 */
+#define IFX_DSADC_EVFLAGCLR_ALEC2_OFF (18u)
+
+/** \brief Length for Ifx_DSADC_EVFLAGCLR_Bits.ALEC3 */
+#define IFX_DSADC_EVFLAGCLR_ALEC3_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_EVFLAGCLR_Bits.ALEC3 */
+#define IFX_DSADC_EVFLAGCLR_ALEC3_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_EVFLAGCLR_Bits.ALEC3 */
+#define IFX_DSADC_EVFLAGCLR_ALEC3_OFF (19u)
+
+/** \brief Length for Ifx_DSADC_EVFLAGCLR_Bits.RESEC0 */
+#define IFX_DSADC_EVFLAGCLR_RESEC0_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_EVFLAGCLR_Bits.RESEC0 */
+#define IFX_DSADC_EVFLAGCLR_RESEC0_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_EVFLAGCLR_Bits.RESEC0 */
+#define IFX_DSADC_EVFLAGCLR_RESEC0_OFF (0u)
+
+/** \brief Length for Ifx_DSADC_EVFLAGCLR_Bits.RESEC2 */
+#define IFX_DSADC_EVFLAGCLR_RESEC2_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_EVFLAGCLR_Bits.RESEC2 */
+#define IFX_DSADC_EVFLAGCLR_RESEC2_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_EVFLAGCLR_Bits.RESEC2 */
+#define IFX_DSADC_EVFLAGCLR_RESEC2_OFF (2u)
+
+/** \brief Length for Ifx_DSADC_EVFLAGCLR_Bits.RESEC3 */
+#define IFX_DSADC_EVFLAGCLR_RESEC3_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_EVFLAGCLR_Bits.RESEC3 */
+#define IFX_DSADC_EVFLAGCLR_RESEC3_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_EVFLAGCLR_Bits.RESEC3 */
+#define IFX_DSADC_EVFLAGCLR_RESEC3_OFF (3u)
+
+/** \brief Length for Ifx_DSADC_GLOBCFG_Bits.IBSEL */
+#define IFX_DSADC_GLOBCFG_IBSEL_LEN (4u)
+
+/** \brief Mask for Ifx_DSADC_GLOBCFG_Bits.IBSEL */
+#define IFX_DSADC_GLOBCFG_IBSEL_MSK (0xfu)
+
+/** \brief Offset for Ifx_DSADC_GLOBCFG_Bits.IBSEL */
+#define IFX_DSADC_GLOBCFG_IBSEL_OFF (16u)
+
+/** \brief Length for Ifx_DSADC_GLOBCFG_Bits.ICT */
+#define IFX_DSADC_GLOBCFG_ICT_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_GLOBCFG_Bits.ICT */
+#define IFX_DSADC_GLOBCFG_ICT_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_GLOBCFG_Bits.ICT */
+#define IFX_DSADC_GLOBCFG_ICT_OFF (22u)
+
+/** \brief Length for Ifx_DSADC_GLOBCFG_Bits.IRM0 */
+#define IFX_DSADC_GLOBCFG_IRM0_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_GLOBCFG_Bits.IRM0 */
+#define IFX_DSADC_GLOBCFG_IRM0_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_GLOBCFG_Bits.IRM0 */
+#define IFX_DSADC_GLOBCFG_IRM0_OFF (11u)
+
+/** \brief Length for Ifx_DSADC_GLOBCFG_Bits.LOSUP */
+#define IFX_DSADC_GLOBCFG_LOSUP_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_GLOBCFG_Bits.LOSUP */
+#define IFX_DSADC_GLOBCFG_LOSUP_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_GLOBCFG_Bits.LOSUP */
+#define IFX_DSADC_GLOBCFG_LOSUP_OFF (20u)
+
+/** \brief Length for Ifx_DSADC_GLOBCFG_Bits.MCSEL */
+#define IFX_DSADC_GLOBCFG_MCSEL_LEN (3u)
+
+/** \brief Mask for Ifx_DSADC_GLOBCFG_Bits.MCSEL */
+#define IFX_DSADC_GLOBCFG_MCSEL_MSK (0x7u)
+
+/** \brief Offset for Ifx_DSADC_GLOBCFG_Bits.MCSEL */
+#define IFX_DSADC_GLOBCFG_MCSEL_OFF (0u)
+
+/** \brief Length for Ifx_DSADC_GLOBCFG_Bits.PSWC */
+#define IFX_DSADC_GLOBCFG_PSWC_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_GLOBCFG_Bits.PSWC */
+#define IFX_DSADC_GLOBCFG_PSWC_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_GLOBCFG_Bits.PSWC */
+#define IFX_DSADC_GLOBCFG_PSWC_OFF (23u)
+
+/** \brief Length for Ifx_DSADC_GLOBRC_Bits.CH0RUN */
+#define IFX_DSADC_GLOBRC_CH0RUN_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_GLOBRC_Bits.CH0RUN */
+#define IFX_DSADC_GLOBRC_CH0RUN_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_GLOBRC_Bits.CH0RUN */
+#define IFX_DSADC_GLOBRC_CH0RUN_OFF (0u)
+
+/** \brief Length for Ifx_DSADC_GLOBRC_Bits.CH2RUN */
+#define IFX_DSADC_GLOBRC_CH2RUN_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_GLOBRC_Bits.CH2RUN */
+#define IFX_DSADC_GLOBRC_CH2RUN_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_GLOBRC_Bits.CH2RUN */
+#define IFX_DSADC_GLOBRC_CH2RUN_OFF (2u)
+
+/** \brief Length for Ifx_DSADC_GLOBRC_Bits.CH3RUN */
+#define IFX_DSADC_GLOBRC_CH3RUN_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_GLOBRC_Bits.CH3RUN */
+#define IFX_DSADC_GLOBRC_CH3RUN_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_GLOBRC_Bits.CH3RUN */
+#define IFX_DSADC_GLOBRC_CH3RUN_OFF (3u)
+
+/** \brief Length for Ifx_DSADC_GLOBRC_Bits.M0RUN */
+#define IFX_DSADC_GLOBRC_M0RUN_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_GLOBRC_Bits.M0RUN */
+#define IFX_DSADC_GLOBRC_M0RUN_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_GLOBRC_Bits.M0RUN */
+#define IFX_DSADC_GLOBRC_M0RUN_OFF (16u)
+
+/** \brief Length for Ifx_DSADC_GLOBRC_Bits.M2RUN */
+#define IFX_DSADC_GLOBRC_M2RUN_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_GLOBRC_Bits.M2RUN */
+#define IFX_DSADC_GLOBRC_M2RUN_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_GLOBRC_Bits.M2RUN */
+#define IFX_DSADC_GLOBRC_M2RUN_OFF (18u)
+
+/** \brief Length for Ifx_DSADC_GLOBRC_Bits.M3RUN */
+#define IFX_DSADC_GLOBRC_M3RUN_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_GLOBRC_Bits.M3RUN */
+#define IFX_DSADC_GLOBRC_M3RUN_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_GLOBRC_Bits.M3RUN */
+#define IFX_DSADC_GLOBRC_M3RUN_OFF (19u)
+
+/** \brief Length for Ifx_DSADC_GLOBVCMH0_Bits.IN0NVC0 */
+#define IFX_DSADC_GLOBVCMH0_IN0NVC0_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_GLOBVCMH0_Bits.IN0NVC0 */
+#define IFX_DSADC_GLOBVCMH0_IN0NVC0_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_GLOBVCMH0_Bits.IN0NVC0 */
+#define IFX_DSADC_GLOBVCMH0_IN0NVC0_OFF (4u)
+
+/** \brief Length for Ifx_DSADC_GLOBVCMH0_Bits.IN0NVC1 */
+#define IFX_DSADC_GLOBVCMH0_IN0NVC1_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_GLOBVCMH0_Bits.IN0NVC1 */
+#define IFX_DSADC_GLOBVCMH0_IN0NVC1_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_GLOBVCMH0_Bits.IN0NVC1 */
+#define IFX_DSADC_GLOBVCMH0_IN0NVC1_OFF (5u)
+
+/** \brief Length for Ifx_DSADC_GLOBVCMH0_Bits.IN0PVC0 */
+#define IFX_DSADC_GLOBVCMH0_IN0PVC0_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_GLOBVCMH0_Bits.IN0PVC0 */
+#define IFX_DSADC_GLOBVCMH0_IN0PVC0_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_GLOBVCMH0_Bits.IN0PVC0 */
+#define IFX_DSADC_GLOBVCMH0_IN0PVC0_OFF (0u)
+
+/** \brief Length for Ifx_DSADC_GLOBVCMH0_Bits.IN0PVC1 */
+#define IFX_DSADC_GLOBVCMH0_IN0PVC1_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_GLOBVCMH0_Bits.IN0PVC1 */
+#define IFX_DSADC_GLOBVCMH0_IN0PVC1_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_GLOBVCMH0_Bits.IN0PVC1 */
+#define IFX_DSADC_GLOBVCMH0_IN0PVC1_OFF (1u)
+
+/** \brief Length for Ifx_DSADC_GLOBVCMH0_Bits.IN2NVC0 */
+#define IFX_DSADC_GLOBVCMH0_IN2NVC0_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_GLOBVCMH0_Bits.IN2NVC0 */
+#define IFX_DSADC_GLOBVCMH0_IN2NVC0_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_GLOBVCMH0_Bits.IN2NVC0 */
+#define IFX_DSADC_GLOBVCMH0_IN2NVC0_OFF (20u)
+
+/** \brief Length for Ifx_DSADC_GLOBVCMH0_Bits.IN2PVC0 */
+#define IFX_DSADC_GLOBVCMH0_IN2PVC0_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_GLOBVCMH0_Bits.IN2PVC0 */
+#define IFX_DSADC_GLOBVCMH0_IN2PVC0_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_GLOBVCMH0_Bits.IN2PVC0 */
+#define IFX_DSADC_GLOBVCMH0_IN2PVC0_OFF (16u)
+
+/** \brief Length for Ifx_DSADC_GLOBVCMH0_Bits.IN3NVC0 */
+#define IFX_DSADC_GLOBVCMH0_IN3NVC0_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_GLOBVCMH0_Bits.IN3NVC0 */
+#define IFX_DSADC_GLOBVCMH0_IN3NVC0_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_GLOBVCMH0_Bits.IN3NVC0 */
+#define IFX_DSADC_GLOBVCMH0_IN3NVC0_OFF (28u)
+
+/** \brief Length for Ifx_DSADC_GLOBVCMH0_Bits.IN3NVC1 */
+#define IFX_DSADC_GLOBVCMH0_IN3NVC1_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_GLOBVCMH0_Bits.IN3NVC1 */
+#define IFX_DSADC_GLOBVCMH0_IN3NVC1_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_GLOBVCMH0_Bits.IN3NVC1 */
+#define IFX_DSADC_GLOBVCMH0_IN3NVC1_OFF (29u)
+
+/** \brief Length for Ifx_DSADC_GLOBVCMH0_Bits.IN3NVC2 */
+#define IFX_DSADC_GLOBVCMH0_IN3NVC2_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_GLOBVCMH0_Bits.IN3NVC2 */
+#define IFX_DSADC_GLOBVCMH0_IN3NVC2_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_GLOBVCMH0_Bits.IN3NVC2 */
+#define IFX_DSADC_GLOBVCMH0_IN3NVC2_OFF (30u)
+
+/** \brief Length for Ifx_DSADC_GLOBVCMH0_Bits.IN3NVC3 */
+#define IFX_DSADC_GLOBVCMH0_IN3NVC3_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_GLOBVCMH0_Bits.IN3NVC3 */
+#define IFX_DSADC_GLOBVCMH0_IN3NVC3_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_GLOBVCMH0_Bits.IN3NVC3 */
+#define IFX_DSADC_GLOBVCMH0_IN3NVC3_OFF (31u)
+
+/** \brief Length for Ifx_DSADC_GLOBVCMH0_Bits.IN3PVC0 */
+#define IFX_DSADC_GLOBVCMH0_IN3PVC0_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_GLOBVCMH0_Bits.IN3PVC0 */
+#define IFX_DSADC_GLOBVCMH0_IN3PVC0_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_GLOBVCMH0_Bits.IN3PVC0 */
+#define IFX_DSADC_GLOBVCMH0_IN3PVC0_OFF (24u)
+
+/** \brief Length for Ifx_DSADC_GLOBVCMH0_Bits.IN3PVC1 */
+#define IFX_DSADC_GLOBVCMH0_IN3PVC1_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_GLOBVCMH0_Bits.IN3PVC1 */
+#define IFX_DSADC_GLOBVCMH0_IN3PVC1_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_GLOBVCMH0_Bits.IN3PVC1 */
+#define IFX_DSADC_GLOBVCMH0_IN3PVC1_OFF (25u)
+
+/** \brief Length for Ifx_DSADC_GLOBVCMH0_Bits.IN3PVC2 */
+#define IFX_DSADC_GLOBVCMH0_IN3PVC2_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_GLOBVCMH0_Bits.IN3PVC2 */
+#define IFX_DSADC_GLOBVCMH0_IN3PVC2_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_GLOBVCMH0_Bits.IN3PVC2 */
+#define IFX_DSADC_GLOBVCMH0_IN3PVC2_OFF (26u)
+
+/** \brief Length for Ifx_DSADC_GLOBVCMH0_Bits.IN3PVC3 */
+#define IFX_DSADC_GLOBVCMH0_IN3PVC3_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_GLOBVCMH0_Bits.IN3PVC3 */
+#define IFX_DSADC_GLOBVCMH0_IN3PVC3_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_GLOBVCMH0_Bits.IN3PVC3 */
+#define IFX_DSADC_GLOBVCMH0_IN3PVC3_OFF (27u)
+
+/** \brief Length for Ifx_DSADC_GLOBVCMH2_Bits.VCMHS */
+#define IFX_DSADC_GLOBVCMH2_VCMHS_LEN (2u)
+
+/** \brief Mask for Ifx_DSADC_GLOBVCMH2_Bits.VCMHS */
+#define IFX_DSADC_GLOBVCMH2_VCMHS_MSK (0x3u)
+
+/** \brief Offset for Ifx_DSADC_GLOBVCMH2_Bits.VCMHS */
+#define IFX_DSADC_GLOBVCMH2_VCMHS_OFF (30u)
+
+/** \brief Length for Ifx_DSADC_GLOBVCMH2_Bits.VHON */
+#define IFX_DSADC_GLOBVCMH2_VHON_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_GLOBVCMH2_Bits.VHON */
+#define IFX_DSADC_GLOBVCMH2_VHON_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_GLOBVCMH2_Bits.VHON */
+#define IFX_DSADC_GLOBVCMH2_VHON_OFF (29u)
+
+/** \brief Length for Ifx_DSADC_ID_Bits.MODNUMBER */
+#define IFX_DSADC_ID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_DSADC_ID_Bits.MODNUMBER */
+#define IFX_DSADC_ID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_DSADC_ID_Bits.MODNUMBER */
+#define IFX_DSADC_ID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_DSADC_ID_Bits.MODREV */
+#define IFX_DSADC_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_DSADC_ID_Bits.MODREV */
+#define IFX_DSADC_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_DSADC_ID_Bits.MODREV */
+#define IFX_DSADC_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_DSADC_ID_Bits.MODTYPE */
+#define IFX_DSADC_ID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_DSADC_ID_Bits.MODTYPE */
+#define IFX_DSADC_ID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_DSADC_ID_Bits.MODTYPE */
+#define IFX_DSADC_ID_MODTYPE_OFF (8u)
+
+/** \brief Length for Ifx_DSADC_IGCFG_Bits.DITRIM */
+#define IFX_DSADC_IGCFG_DITRIM_LEN (3u)
+
+/** \brief Mask for Ifx_DSADC_IGCFG_Bits.DITRIM */
+#define IFX_DSADC_IGCFG_DITRIM_MSK (0x7u)
+
+/** \brief Offset for Ifx_DSADC_IGCFG_Bits.DITRIM */
+#define IFX_DSADC_IGCFG_DITRIM_OFF (0u)
+
+/** \brief Length for Ifx_DSADC_IGCFG_Bits.GLOBSP */
+#define IFX_DSADC_IGCFG_GLOBSP_LEN (10u)
+
+/** \brief Mask for Ifx_DSADC_IGCFG_Bits.GLOBSP */
+#define IFX_DSADC_IGCFG_GLOBSP_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_DSADC_IGCFG_Bits.GLOBSP */
+#define IFX_DSADC_IGCFG_GLOBSP_OFF (16u)
+
+/** \brief Length for Ifx_DSADC_IGCFG_Bits.WREN */
+#define IFX_DSADC_IGCFG_WREN_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_IGCFG_Bits.WREN */
+#define IFX_DSADC_IGCFG_WREN_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_IGCFG_Bits.WREN */
+#define IFX_DSADC_IGCFG_WREN_OFF (31u)
+
+/** \brief Length for Ifx_DSADC_KRST0_Bits.RST */
+#define IFX_DSADC_KRST0_RST_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_KRST0_Bits.RST */
+#define IFX_DSADC_KRST0_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_KRST0_Bits.RST */
+#define IFX_DSADC_KRST0_RST_OFF (0u)
+
+/** \brief Length for Ifx_DSADC_KRST0_Bits.RSTSTAT */
+#define IFX_DSADC_KRST0_RSTSTAT_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_KRST0_Bits.RSTSTAT */
+#define IFX_DSADC_KRST0_RSTSTAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_KRST0_Bits.RSTSTAT */
+#define IFX_DSADC_KRST0_RSTSTAT_OFF (1u)
+
+/** \brief Length for Ifx_DSADC_KRST1_Bits.RST */
+#define IFX_DSADC_KRST1_RST_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_KRST1_Bits.RST */
+#define IFX_DSADC_KRST1_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_KRST1_Bits.RST */
+#define IFX_DSADC_KRST1_RST_OFF (0u)
+
+/** \brief Length for Ifx_DSADC_KRSTCLR_Bits.CLR */
+#define IFX_DSADC_KRSTCLR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_KRSTCLR_Bits.CLR */
+#define IFX_DSADC_KRSTCLR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_KRSTCLR_Bits.CLR */
+#define IFX_DSADC_KRSTCLR_CLR_OFF (0u)
+
+/** \brief Length for Ifx_DSADC_OCS_Bits.SUS */
+#define IFX_DSADC_OCS_SUS_LEN (4u)
+
+/** \brief Mask for Ifx_DSADC_OCS_Bits.SUS */
+#define IFX_DSADC_OCS_SUS_MSK (0xfu)
+
+/** \brief Offset for Ifx_DSADC_OCS_Bits.SUS */
+#define IFX_DSADC_OCS_SUS_OFF (24u)
+
+/** \brief Length for Ifx_DSADC_OCS_Bits.SUS_P */
+#define IFX_DSADC_OCS_SUS_P_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_OCS_Bits.SUS_P */
+#define IFX_DSADC_OCS_SUS_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_OCS_Bits.SUS_P */
+#define IFX_DSADC_OCS_SUS_P_OFF (28u)
+
+/** \brief Length for Ifx_DSADC_OCS_Bits.SUSSTA */
+#define IFX_DSADC_OCS_SUSSTA_LEN (1u)
+
+/** \brief Mask for Ifx_DSADC_OCS_Bits.SUSSTA */
+#define IFX_DSADC_OCS_SUSSTA_MSK (0x1u)
+
+/** \brief Offset for Ifx_DSADC_OCS_Bits.SUSSTA */
+#define IFX_DSADC_OCS_SUSSTA_OFF (29u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXDSADC_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxDsadc_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxDsadc_reg.h
new file mode 100644
index 0000000..8c7e90b
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxDsadc_reg.h
@@ -0,0 +1,435 @@
+/**
+ * \file IfxDsadc_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Dsadc_Cfg Dsadc address
+ * \ingroup IfxLld_Dsadc
+ *
+ * \defgroup IfxLld_Dsadc_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Dsadc_Cfg
+ *
+ * \defgroup IfxLld_Dsadc_Cfg_Dsadc 2-DSADC
+ * \ingroup IfxLld_Dsadc_Cfg
+ *
+ */
+#ifndef IFXDSADC_REG_H
+#define IFXDSADC_REG_H 1
+/******************************************************************************/
+#include "IfxDsadc_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Dsadc_Cfg_BaseAddress
+ * \{ */
+
+/** \brief DSADC object */
+#define MODULE_DSADC /*lint --e(923)*/ (*(Ifx_DSADC*)0xF0024000u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Dsadc_Cfg_Dsadc
+ * \{ */
+
+/** \brief 3C, Access Enable Register 0 */
+#define DSADC_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_DSADC_ACCEN0*)0xF002403Cu)
+
+/** \brief 90, Access Protection Register */
+#define DSADC_ACCPROT /*lint --e(923)*/ (*(volatile Ifx_DSADC_ACCPROT*)0xF0024090u)
+
+/** \brief A0, Carrier Generator Configuration Register */
+#define DSADC_CGCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CGCFG*)0xF00240A0u)
+
+/** \brief 128, Boundary Select Register */
+#define DSADC_CH0_BOUNDSEL /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_BOUNDSEL*)0xF0024128u)
+
+/** Alias (User Manual Name) for DSADC_CH0_BOUNDSEL.
+* To use register names with standard convension, please use DSADC_CH0_BOUNDSEL.
+*/
+#define DSADC_BOUNDSEL0 (DSADC_CH0_BOUNDSEL)
+
+/** \brief 1A0, Carrier Generator Synchronization Register */
+#define DSADC_CH0_CGSYNC /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_CGSYNC*)0xF00241A0u)
+
+/** Alias (User Manual Name) for DSADC_CH0_CGSYNC.
+* To use register names with standard convension, please use DSADC_CH0_CGSYNC.
+*/
+#define DSADC_CGSYNC0 (DSADC_CH0_CGSYNC)
+
+/** \brief 108, Demodulator Input Configuration Register */
+#define DSADC_CH0_DICFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_DICFG*)0xF0024108u)
+
+/** Alias (User Manual Name) for DSADC_CH0_DICFG.
+* To use register names with standard convension, please use DSADC_CH0_DICFG.
+*/
+#define DSADC_DICFG0 (DSADC_CH0_DICFG)
+
+/** \brief 118, Filter Configuration Register, Auxiliary Filter */
+#define DSADC_CH0_FCFGA /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_FCFGA*)0xF0024118u)
+
+/** Alias (User Manual Name) for DSADC_CH0_FCFGA.
+* To use register names with standard convension, please use DSADC_CH0_FCFGA.
+*/
+#define DSADC_FCFGA0 (DSADC_CH0_FCFGA)
+
+/** \brief 114, Filter Configuration Register, Main CIC Filter */
+#define DSADC_CH0_FCFGC /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_FCFGC*)0xF0024114u)
+
+/** Alias (User Manual Name) for DSADC_CH0_FCFGC.
+* To use register names with standard convension, please use DSADC_CH0_FCFGC.
+*/
+#define DSADC_FCFGC0 (DSADC_CH0_FCFGC)
+
+/** \brief 110, Filter Configuration Register, Main Filter Chain */
+#define DSADC_CH0_FCFGM /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_FCFGM*)0xF0024110u)
+
+/** Alias (User Manual Name) for DSADC_CH0_FCFGM.
+* To use register names with standard convension, please use DSADC_CH0_FCFGM.
+*/
+#define DSADC_FCFGM0 (DSADC_CH0_FCFGM)
+
+/** \brief 1D0, Initial Channel Config. Reg. 0 */
+#define DSADC_CH0_ICCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_ICCFG*)0xF00241D0u)
+
+/** Alias (User Manual Name) for DSADC_CH0_ICCFG.
+* To use register names with standard convension, please use DSADC_CH0_ICCFG.
+*/
+#define DSADC_ICCFG0 (DSADC_CH0_ICCFG)
+
+/** \brief 120, Integration Window Control Register */
+#define DSADC_CH0_IWCTR /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_IWCTR*)0xF0024120u)
+
+/** Alias (User Manual Name) for DSADC_CH0_IWCTR.
+* To use register names with standard convension, please use DSADC_CH0_IWCTR.
+*/
+#define DSADC_IWCTR0 (DSADC_CH0_IWCTR)
+
+/** \brief 100, Modulator Configuration Register */
+#define DSADC_CH0_MODCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_MODCFG*)0xF0024100u)
+
+/** Alias (User Manual Name) for DSADC_CH0_MODCFG.
+* To use register names with standard convension, please use DSADC_CH0_MODCFG.
+*/
+#define DSADC_MODCFG0 (DSADC_CH0_MODCFG)
+
+/** \brief 138, Offset Register Main Filter */
+#define DSADC_CH0_OFFM /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_OFFM*)0xF0024138u)
+
+/** Alias (User Manual Name) for DSADC_CH0_OFFM.
+* To use register names with standard convension, please use DSADC_CH0_OFFM.
+*/
+#define DSADC_OFFM0 (DSADC_CH0_OFFM)
+
+/** \brief 1A8, Rectification Configuration Register */
+#define DSADC_CH0_RECTCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_RECTCFG*)0xF00241A8u)
+
+/** Alias (User Manual Name) for DSADC_CH0_RECTCFG.
+* To use register names with standard convension, please use DSADC_CH0_RECTCFG.
+*/
+#define DSADC_RECTCFG0 (DSADC_CH0_RECTCFG)
+
+/** \brief 140, Result Register Auxiliary Filter */
+#define DSADC_CH0_RESA /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_RESA*)0xF0024140u)
+
+/** Alias (User Manual Name) for DSADC_CH0_RESA.
+* To use register names with standard convension, please use DSADC_CH0_RESA.
+*/
+#define DSADC_RESA0 (DSADC_CH0_RESA)
+
+/** \brief 130, Result Register Main Filter */
+#define DSADC_CH0_RESM /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_RESM*)0xF0024130u)
+
+/** Alias (User Manual Name) for DSADC_CH0_RESM.
+* To use register names with standard convension, please use DSADC_CH0_RESM.
+*/
+#define DSADC_RESM0 (DSADC_CH0_RESM)
+
+/** \brief 150, Time-Stamp Register */
+#define DSADC_CH0_TSTMP /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_TSTMP*)0xF0024150u)
+
+/** Alias (User Manual Name) for DSADC_CH0_TSTMP.
+* To use register names with standard convension, please use DSADC_CH0_TSTMP.
+*/
+#define DSADC_TSTMP0 (DSADC_CH0_TSTMP)
+
+/** \brief 328, Boundary Select Register */
+#define DSADC_CH2_BOUNDSEL /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_BOUNDSEL*)0xF0024328u)
+
+/** Alias (User Manual Name) for DSADC_CH2_BOUNDSEL.
+* To use register names with standard convension, please use DSADC_CH2_BOUNDSEL.
+*/
+#define DSADC_BOUNDSEL2 (DSADC_CH2_BOUNDSEL)
+
+/** \brief 3A0, Carrier Generator Synchronization Register */
+#define DSADC_CH2_CGSYNC /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_CGSYNC*)0xF00243A0u)
+
+/** Alias (User Manual Name) for DSADC_CH2_CGSYNC.
+* To use register names with standard convension, please use DSADC_CH2_CGSYNC.
+*/
+#define DSADC_CGSYNC2 (DSADC_CH2_CGSYNC)
+
+/** \brief 308, Demodulator Input Configuration Register */
+#define DSADC_CH2_DICFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_DICFG*)0xF0024308u)
+
+/** Alias (User Manual Name) for DSADC_CH2_DICFG.
+* To use register names with standard convension, please use DSADC_CH2_DICFG.
+*/
+#define DSADC_DICFG2 (DSADC_CH2_DICFG)
+
+/** \brief 318, Filter Configuration Register, Auxiliary Filter */
+#define DSADC_CH2_FCFGA /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_FCFGA*)0xF0024318u)
+
+/** Alias (User Manual Name) for DSADC_CH2_FCFGA.
+* To use register names with standard convension, please use DSADC_CH2_FCFGA.
+*/
+#define DSADC_FCFGA2 (DSADC_CH2_FCFGA)
+
+/** \brief 314, Filter Configuration Register, Main CIC Filter */
+#define DSADC_CH2_FCFGC /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_FCFGC*)0xF0024314u)
+
+/** Alias (User Manual Name) for DSADC_CH2_FCFGC.
+* To use register names with standard convension, please use DSADC_CH2_FCFGC.
+*/
+#define DSADC_FCFGC2 (DSADC_CH2_FCFGC)
+
+/** \brief 310, Filter Configuration Register, Main Filter Chain */
+#define DSADC_CH2_FCFGM /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_FCFGM*)0xF0024310u)
+
+/** Alias (User Manual Name) for DSADC_CH2_FCFGM.
+* To use register names with standard convension, please use DSADC_CH2_FCFGM.
+*/
+#define DSADC_FCFGM2 (DSADC_CH2_FCFGM)
+
+/** \brief 3D0, Initial Channel Config. Reg. 0 */
+#define DSADC_CH2_ICCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_ICCFG*)0xF00243D0u)
+
+/** Alias (User Manual Name) for DSADC_CH2_ICCFG.
+* To use register names with standard convension, please use DSADC_CH2_ICCFG.
+*/
+#define DSADC_ICCFG2 (DSADC_CH2_ICCFG)
+
+/** \brief 320, Integration Window Control Register */
+#define DSADC_CH2_IWCTR /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_IWCTR*)0xF0024320u)
+
+/** Alias (User Manual Name) for DSADC_CH2_IWCTR.
+* To use register names with standard convension, please use DSADC_CH2_IWCTR.
+*/
+#define DSADC_IWCTR2 (DSADC_CH2_IWCTR)
+
+/** \brief 300, Modulator Configuration Register */
+#define DSADC_CH2_MODCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_MODCFG*)0xF0024300u)
+
+/** Alias (User Manual Name) for DSADC_CH2_MODCFG.
+* To use register names with standard convension, please use DSADC_CH2_MODCFG.
+*/
+#define DSADC_MODCFG2 (DSADC_CH2_MODCFG)
+
+/** \brief 338, Offset Register Main Filter */
+#define DSADC_CH2_OFFM /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_OFFM*)0xF0024338u)
+
+/** Alias (User Manual Name) for DSADC_CH2_OFFM.
+* To use register names with standard convension, please use DSADC_CH2_OFFM.
+*/
+#define DSADC_OFFM2 (DSADC_CH2_OFFM)
+
+/** \brief 3A8, Rectification Configuration Register */
+#define DSADC_CH2_RECTCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_RECTCFG*)0xF00243A8u)
+
+/** Alias (User Manual Name) for DSADC_CH2_RECTCFG.
+* To use register names with standard convension, please use DSADC_CH2_RECTCFG.
+*/
+#define DSADC_RECTCFG2 (DSADC_CH2_RECTCFG)
+
+/** \brief 340, Result Register Auxiliary Filter */
+#define DSADC_CH2_RESA /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_RESA*)0xF0024340u)
+
+/** Alias (User Manual Name) for DSADC_CH2_RESA.
+* To use register names with standard convension, please use DSADC_CH2_RESA.
+*/
+#define DSADC_RESA2 (DSADC_CH2_RESA)
+
+/** \brief 330, Result Register Main Filter */
+#define DSADC_CH2_RESM /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_RESM*)0xF0024330u)
+
+/** Alias (User Manual Name) for DSADC_CH2_RESM.
+* To use register names with standard convension, please use DSADC_CH2_RESM.
+*/
+#define DSADC_RESM2 (DSADC_CH2_RESM)
+
+/** \brief 350, Time-Stamp Register */
+#define DSADC_CH2_TSTMP /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_TSTMP*)0xF0024350u)
+
+/** Alias (User Manual Name) for DSADC_CH2_TSTMP.
+* To use register names with standard convension, please use DSADC_CH2_TSTMP.
+*/
+#define DSADC_TSTMP2 (DSADC_CH2_TSTMP)
+
+/** \brief 428, Boundary Select Register */
+#define DSADC_CH3_BOUNDSEL /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_BOUNDSEL*)0xF0024428u)
+
+/** Alias (User Manual Name) for DSADC_CH3_BOUNDSEL.
+* To use register names with standard convension, please use DSADC_CH3_BOUNDSEL.
+*/
+#define DSADC_BOUNDSEL3 (DSADC_CH3_BOUNDSEL)
+
+/** \brief 4A0, Carrier Generator Synchronization Register */
+#define DSADC_CH3_CGSYNC /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_CGSYNC*)0xF00244A0u)
+
+/** Alias (User Manual Name) for DSADC_CH3_CGSYNC.
+* To use register names with standard convension, please use DSADC_CH3_CGSYNC.
+*/
+#define DSADC_CGSYNC3 (DSADC_CH3_CGSYNC)
+
+/** \brief 408, Demodulator Input Configuration Register */
+#define DSADC_CH3_DICFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_DICFG*)0xF0024408u)
+
+/** Alias (User Manual Name) for DSADC_CH3_DICFG.
+* To use register names with standard convension, please use DSADC_CH3_DICFG.
+*/
+#define DSADC_DICFG3 (DSADC_CH3_DICFG)
+
+/** \brief 418, Filter Configuration Register, Auxiliary Filter */
+#define DSADC_CH3_FCFGA /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_FCFGA*)0xF0024418u)
+
+/** Alias (User Manual Name) for DSADC_CH3_FCFGA.
+* To use register names with standard convension, please use DSADC_CH3_FCFGA.
+*/
+#define DSADC_FCFGA3 (DSADC_CH3_FCFGA)
+
+/** \brief 414, Filter Configuration Register, Main CIC Filter */
+#define DSADC_CH3_FCFGC /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_FCFGC*)0xF0024414u)
+
+/** Alias (User Manual Name) for DSADC_CH3_FCFGC.
+* To use register names with standard convension, please use DSADC_CH3_FCFGC.
+*/
+#define DSADC_FCFGC3 (DSADC_CH3_FCFGC)
+
+/** \brief 410, Filter Configuration Register, Main Filter Chain */
+#define DSADC_CH3_FCFGM /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_FCFGM*)0xF0024410u)
+
+/** Alias (User Manual Name) for DSADC_CH3_FCFGM.
+* To use register names with standard convension, please use DSADC_CH3_FCFGM.
+*/
+#define DSADC_FCFGM3 (DSADC_CH3_FCFGM)
+
+/** \brief 4D0, Initial Channel Config. Reg. 0 */
+#define DSADC_CH3_ICCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_ICCFG*)0xF00244D0u)
+
+/** Alias (User Manual Name) for DSADC_CH3_ICCFG.
+* To use register names with standard convension, please use DSADC_CH3_ICCFG.
+*/
+#define DSADC_ICCFG3 (DSADC_CH3_ICCFG)
+
+/** \brief 420, Integration Window Control Register */
+#define DSADC_CH3_IWCTR /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_IWCTR*)0xF0024420u)
+
+/** Alias (User Manual Name) for DSADC_CH3_IWCTR.
+* To use register names with standard convension, please use DSADC_CH3_IWCTR.
+*/
+#define DSADC_IWCTR3 (DSADC_CH3_IWCTR)
+
+/** \brief 400, Modulator Configuration Register */
+#define DSADC_CH3_MODCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_MODCFG*)0xF0024400u)
+
+/** Alias (User Manual Name) for DSADC_CH3_MODCFG.
+* To use register names with standard convension, please use DSADC_CH3_MODCFG.
+*/
+#define DSADC_MODCFG3 (DSADC_CH3_MODCFG)
+
+/** \brief 438, Offset Register Main Filter */
+#define DSADC_CH3_OFFM /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_OFFM*)0xF0024438u)
+
+/** Alias (User Manual Name) for DSADC_CH3_OFFM.
+* To use register names with standard convension, please use DSADC_CH3_OFFM.
+*/
+#define DSADC_OFFM3 (DSADC_CH3_OFFM)
+
+/** \brief 4A8, Rectification Configuration Register */
+#define DSADC_CH3_RECTCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_RECTCFG*)0xF00244A8u)
+
+/** Alias (User Manual Name) for DSADC_CH3_RECTCFG.
+* To use register names with standard convension, please use DSADC_CH3_RECTCFG.
+*/
+#define DSADC_RECTCFG3 (DSADC_CH3_RECTCFG)
+
+/** \brief 440, Result Register Auxiliary Filter */
+#define DSADC_CH3_RESA /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_RESA*)0xF0024440u)
+
+/** Alias (User Manual Name) for DSADC_CH3_RESA.
+* To use register names with standard convension, please use DSADC_CH3_RESA.
+*/
+#define DSADC_RESA3 (DSADC_CH3_RESA)
+
+/** \brief 430, Result Register Main Filter */
+#define DSADC_CH3_RESM /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_RESM*)0xF0024430u)
+
+/** Alias (User Manual Name) for DSADC_CH3_RESM.
+* To use register names with standard convension, please use DSADC_CH3_RESM.
+*/
+#define DSADC_RESM3 (DSADC_CH3_RESM)
+
+/** \brief 450, Time-Stamp Register */
+#define DSADC_CH3_TSTMP /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_TSTMP*)0xF0024450u)
+
+/** Alias (User Manual Name) for DSADC_CH3_TSTMP.
+* To use register names with standard convension, please use DSADC_CH3_TSTMP.
+*/
+#define DSADC_TSTMP3 (DSADC_CH3_TSTMP)
+
+/** \brief 0, Clock Control Register */
+#define DSADC_CLC /*lint --e(923)*/ (*(volatile Ifx_DSADC_CLC*)0xF0024000u)
+
+/** \brief E0, Event Flag Register */
+#define DSADC_EVFLAG /*lint --e(923)*/ (*(volatile Ifx_DSADC_EVFLAG*)0xF00240E0u)
+
+/** \brief E4, Event Flag Clear Register */
+#define DSADC_EVFLAGCLR /*lint --e(923)*/ (*(volatile Ifx_DSADC_EVFLAGCLR*)0xF00240E4u)
+
+/** \brief 80, Global Configuration Register */
+#define DSADC_GLOBCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_GLOBCFG*)0xF0024080u)
+
+/** \brief 88, Global Run Control Register */
+#define DSADC_GLOBRC /*lint --e(923)*/ (*(volatile Ifx_DSADC_GLOBRC*)0xF0024088u)
+
+/** \brief B0, Common Mode Hold Voltage Register 0 */
+#define DSADC_GLOBVCMH0 /*lint --e(923)*/ (*(volatile Ifx_DSADC_GLOBVCMH0*)0xF00240B0u)
+
+/** \brief B8, Common Mode Hold Voltage Register 2 */
+#define DSADC_GLOBVCMH2 /*lint --e(923)*/ (*(volatile Ifx_DSADC_GLOBVCMH2*)0xF00240B8u)
+
+/** \brief 8, Module Identification Register */
+#define DSADC_ID /*lint --e(923)*/ (*(volatile Ifx_DSADC_ID*)0xF0024008u)
+
+/** \brief D0, Initial Global Config. Register */
+#define DSADC_IGCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_IGCFG*)0xF00240D0u)
+
+/** \brief 34, Kernel Reset Register 0 */
+#define DSADC_KRST0 /*lint --e(923)*/ (*(volatile Ifx_DSADC_KRST0*)0xF0024034u)
+
+/** \brief 30, Kernel Reset Register 1 */
+#define DSADC_KRST1 /*lint --e(923)*/ (*(volatile Ifx_DSADC_KRST1*)0xF0024030u)
+
+/** \brief 2C, Kernel Reset Status Clear Register */
+#define DSADC_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_DSADC_KRSTCLR*)0xF002402Cu)
+
+/** \brief 28, OCDS Control and Status Register */
+#define DSADC_OCS /*lint --e(923)*/ (*(volatile Ifx_DSADC_OCS*)0xF0024028u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXDSADC_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxDsadc_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxDsadc_regdef.h
new file mode 100644
index 0000000..5ca9818
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxDsadc_regdef.h
@@ -0,0 +1,761 @@
+/**
+ * \file IfxDsadc_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Dsadc Dsadc
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Dsadc_Bitfields Bitfields
+ * \ingroup IfxLld_Dsadc
+ *
+ * \defgroup IfxLld_Dsadc_union Union
+ * \ingroup IfxLld_Dsadc
+ *
+ * \defgroup IfxLld_Dsadc_struct Struct
+ * \ingroup IfxLld_Dsadc
+ *
+ */
+#ifndef IFXDSADC_REGDEF_H
+#define IFXDSADC_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Dsadc_Bitfields
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef struct _Ifx_DSADC_ACCEN0_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_DSADC_ACCEN0_Bits;
+
+/** \brief Access Protection Register */
+typedef struct _Ifx_DSADC_ACCPROT_Bits
+{
+ unsigned int RG00:1; /**< \brief [0:0] Register Group 0, Channels 0, 2, 3 (rw) */
+ unsigned int RG01:1; /**< \brief [1:1] Register Group 1, Channels 0, 2, 3 (rw) */
+ unsigned int RG02:1; /**< \brief [2:2] Register Group 2, Channels 0, 2, 3 (rw) */
+ unsigned int RG03:1; /**< \brief [3:3] Register Group 3, Channels 0, 2, 3 (rw) */
+ unsigned int RG04:1; /**< \brief [4:4] Register Group 4, Channels 0, 2, 3 (rw) */
+ unsigned int reserved_5:9; /**< \brief \internal Reserved */
+ unsigned int RG10:1; /**< \brief [14:14] Register Group 0/1, General Control (rw) */
+ unsigned int RG11:1; /**< \brief [15:15] Register Group 0/1, General Control (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_DSADC_ACCPROT_Bits;
+
+/** \brief Carrier Generator Configuration Register */
+typedef struct _Ifx_DSADC_CGCFG_Bits
+{
+ unsigned int CGMOD:2; /**< \brief [1:0] Carrier Generator Operating Mode (rw) */
+ unsigned int BREV:1; /**< \brief [2:2] Bit-Reverse PWM Generation (rw) */
+ unsigned int SIGPOL:1; /**< \brief [3:3] Signal Polarity (rw) */
+ unsigned int DIVCG:4; /**< \brief [7:4] Divider Factor for the PWM Pattern Signal Generator (rw) */
+ unsigned int reserved_8:7; /**< \brief \internal Reserved */
+ unsigned int RUN:1; /**< \brief [15:15] Run Indicator (rh) */
+ unsigned int BITCOUNT:5; /**< \brief [20:16] Bit Counter (rh) */
+ unsigned int reserved_21:3; /**< \brief \internal Reserved */
+ unsigned int STEPCOUNT:4; /**< \brief [27:24] Step Counter (rh) */
+ unsigned int STEPS:1; /**< \brief [28:28] Step Counter Sign (rh) */
+ unsigned int STEPD:1; /**< \brief [29:29] Step Counter Direction (rh) */
+ unsigned int SGNCG:1; /**< \brief [30:30] Sign Signal from Carrier Generator (rh) */
+ unsigned int reserved_31:1; /**< \brief \internal Reserved */
+} Ifx_DSADC_CGCFG_Bits;
+
+/** \brief Boundary Select Register */
+typedef struct _Ifx_DSADC_CH_BOUNDSEL_Bits
+{
+ unsigned int BOUNDARYL:16; /**< \brief [15:0] Lower Boundary Value for Limit Checking (rw) */
+ unsigned int BOUNDARYU:16; /**< \brief [31:16] Upper Boundary Value for Limit Checking (rw) */
+} Ifx_DSADC_CH_BOUNDSEL_Bits;
+
+/** \brief Carrier Generator Synchronization Register */
+typedef struct _Ifx_DSADC_CH_CGSYNC_Bits
+{
+ unsigned int SDCOUNT:8; /**< \brief [7:0] Sign Delay Counter (rh) */
+ unsigned int SDCAP:8; /**< \brief [15:8] Sign Delay Capture Value (rh) */
+ unsigned int SDPOS:8; /**< \brief [23:16] Sign Delay Value for Positive Halfwave (rw) */
+ unsigned int SDNEG:8; /**< \brief [31:24] Sign Delay Value for Negative Halfwave (rw) */
+} Ifx_DSADC_CH_CGSYNC_Bits;
+
+/** \brief Demodulator Input Configuration Register */
+typedef struct _Ifx_DSADC_CH_DICFG_Bits
+{
+ unsigned int DSRC:4; /**< \brief [3:0] Input Data Source Select (rw) */
+ unsigned int reserved_4:3; /**< \brief \internal Reserved */
+ unsigned int DSWC:1; /**< \brief [7:7] Write Control for Data Selection (w) */
+ unsigned int ITRMODE:2; /**< \brief [9:8] Integrator Trigger Mode (rw) */
+ unsigned int TSTRMODE:2; /**< \brief [11:10] Timestamp Trigger Mode (rw) */
+ unsigned int TRSEL:3; /**< \brief [14:12] Trigger Select (rw) */
+ unsigned int TRWC:1; /**< \brief [15:15] Write Control for Trigger Parameters (w) */
+ unsigned int CSRC:4; /**< \brief [19:16] Sample Clock Source Select (rw) */
+ unsigned int STROBE:4; /**< \brief [23:20] Data Strobe Generation Mode (rw) */
+ unsigned int reserved_24:7; /**< \brief \internal Reserved */
+ unsigned int SCWC:1; /**< \brief [31:31] Write Control for Strobe/Clock Selection (w) */
+} Ifx_DSADC_CH_DICFG_Bits;
+
+/** \brief Filter Configuration Register, Auxiliary Filter */
+typedef struct _Ifx_DSADC_CH_FCFGA_Bits
+{
+ unsigned int CFADF:8; /**< \brief [7:0] CIC Filter (Auxiliary) Decimation Factor (rw) */
+ unsigned int CFAC:2; /**< \brief [9:8] CIC Filter (Auxiliary) Configuration (rw) */
+ unsigned int SRGA:2; /**< \brief [11:10] Service Request Generation Auxiliary Filter (rw) */
+ unsigned int ESEL:2; /**< \brief [13:12] Event Select (rw) */
+ unsigned int EGT:1; /**< \brief [14:14] Event Gating (rw) */
+ unsigned int reserved_15:1; /**< \brief \internal Reserved */
+ unsigned int AFSC:2; /**< \brief [17:16] Auxiliary Filter Shift Control (rw) */
+ unsigned int reserved_18:6; /**< \brief \internal Reserved */
+ unsigned int CFADCNT:8; /**< \brief [31:24] CIC Filter (Auxiliary) Decimation Counter (rh) */
+} Ifx_DSADC_CH_FCFGA_Bits;
+
+/** \brief Filter Configuration Register, Main CIC Filter */
+typedef struct _Ifx_DSADC_CH_FCFGC_Bits
+{
+ unsigned int CFMDF:8; /**< \brief [7:0] CIC Filter (Main Chain) Decimation Factor (rw) */
+ unsigned int CFMC:2; /**< \brief [9:8] CIC Filter (Main Chain) Configuration (rw) */
+ unsigned int CFEN:1; /**< \brief [10:10] CIC Filter Enable (rw) */
+ unsigned int reserved_11:1; /**< \brief \internal Reserved */
+ unsigned int MFSC:2; /**< \brief [13:12] Main Filter Shift Control (rw) */
+ unsigned int SRGM:2; /**< \brief [15:14] Service Request Generation Main Chain (rw) */
+ unsigned int CFMSV:8; /**< \brief [23:16] CIC Filter (Main Chain) Start Value (rw) */
+ unsigned int CFMDCNT:8; /**< \brief [31:24] CIC Filter (Main Chain) Decimation Counter (rh) */
+} Ifx_DSADC_CH_FCFGC_Bits;
+
+/** \brief Filter Configuration Register, Main Filter Chain */
+typedef struct _Ifx_DSADC_CH_FCFGM_Bits
+{
+ unsigned int FIR0EN:1; /**< \brief [0:0] FIR Filter 0 Enable (rw) */
+ unsigned int FIR1EN:1; /**< \brief [1:1] FIR Filter 1 Enable (rw) */
+ unsigned int OCEN:1; /**< \brief [2:2] Offset Compensation Filter Enable (rw) */
+ unsigned int DSH:2; /**< \brief [4:3] Data Shift Control (rw) */
+ unsigned int FSH:1; /**< \brief [5:5] FIR Shift Control (rw) */
+ unsigned int reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_DSADC_CH_FCFGM_Bits;
+
+/** \brief Initial Channel Config. Reg. 0 */
+typedef struct _Ifx_DSADC_CH_ICCFG_Bits
+{
+ unsigned int DI0:1; /**< \brief [0:0] Dithering Function Enable (rw) */
+ unsigned int DI1:1; /**< \brief [1:1] Dithering Function Enable (rw) */
+ unsigned int reserved_2:2; /**< \brief \internal Reserved */
+ unsigned int IREN:1; /**< \brief [4:4] Integrator Reset Enable (rw) */
+ unsigned int reserved_5:3; /**< \brief \internal Reserved */
+ unsigned int TWINSP:6; /**< \brief [13:8] Setup Parameters for this Twin Modulator (rw) */
+ unsigned int reserved_14:17; /**< \brief \internal Reserved */
+ unsigned int WREN:1; /**< \brief [31:31] Write Enable (rw) */
+} Ifx_DSADC_CH_ICCFG_Bits;
+
+/** \brief Integration Window Control Register */
+typedef struct _Ifx_DSADC_CH_IWCTR_Bits
+{
+ unsigned int NVALCNT:6; /**< \brief [5:0] Number of Values Counted (rh) */
+ unsigned int reserved_6:1; /**< \brief \internal Reserved */
+ unsigned int INTEN:1; /**< \brief [7:7] Integration Enable (rh) */
+ unsigned int REPCNT:4; /**< \brief [11:8] Integration Cycle Counter (rh) */
+ unsigned int REPVAL:4; /**< \brief [15:12] Number of Integration Cycles (rw) */
+ unsigned int NVALDIS:6; /**< \brief [21:16] Number of Values Discarded (rw) */
+ unsigned int reserved_22:1; /**< \brief \internal Reserved */
+ unsigned int IWS:1; /**< \brief [23:23] Integration Window Size (rw) */
+ unsigned int NVALINT:6; /**< \brief [29:24] Number of Values Integrated (rw) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_DSADC_CH_IWCTR_Bits;
+
+/** \brief Modulator Configuration Register */
+typedef struct _Ifx_DSADC_CH_MODCFG_Bits
+{
+ unsigned int INCFGP:2; /**< \brief [1:0] Configuration of Positive Input Line (rw) */
+ unsigned int INCFGN:2; /**< \brief [3:2] Configuration of Negative Input Line (rw) */
+ unsigned int GAINSEL:4; /**< \brief [7:4] Gain Select of Analog Input Path (rw) */
+ unsigned int INSEL:2; /**< \brief [9:8] Input Pin Selection (rw) */
+ unsigned int INMUX:2; /**< \brief [11:10] Input Multiplexer Setting (rh) */
+ unsigned int INMODE:2; /**< \brief [13:12] Input Multiplexer Control Mode (rw) */
+ unsigned int INMAC:1; /**< \brief [14:14] Input Multiplexer Action Control (rw) */
+ unsigned int INCWC:1; /**< \brief [15:15] Write Control for Input Parameters (w) */
+ unsigned int DIVM:4; /**< \brief [19:16] Divider Factor for Modulator Clock (rw) */
+ unsigned int reserved_20:3; /**< \brief \internal Reserved */
+ unsigned int DWC:1; /**< \brief [23:23] Write Control for Divider Factor (w) */
+ unsigned int CMVS:2; /**< \brief [25:24] Common Mode Voltage Selection (rw) */
+ unsigned int MCFG:2; /**< \brief [27:26] Modulator Configuration (rw) */
+ unsigned int GCEN:1; /**< \brief [28:28] Gain Calibration Enable (rw) */
+ unsigned int APC:1; /**< \brief [29:29] Automatic Power Control (rw) */
+ unsigned int reserved_30:1; /**< \brief \internal Reserved */
+ unsigned int MWC:1; /**< \brief [31:31] Write Control for Mode Selection (w) */
+} Ifx_DSADC_CH_MODCFG_Bits;
+
+/** \brief Offset Register Main Filter */
+typedef struct _Ifx_DSADC_CH_OFFM_Bits
+{
+ unsigned int OFFSET:16; /**< \brief [15:0] Offset Value (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_DSADC_CH_OFFM_Bits;
+
+/** \brief Rectification Configuration Register */
+typedef struct _Ifx_DSADC_CH_RECTCFG_Bits
+{
+ unsigned int RFEN:1; /**< \brief [0:0] Rectification Enable (rw) */
+ unsigned int reserved_1:3; /**< \brief \internal Reserved */
+ unsigned int SSRC:2; /**< \brief [5:4] Sign Source (rw) */
+ unsigned int reserved_6:9; /**< \brief \internal Reserved */
+ unsigned int SDCVAL:1; /**< \brief [15:15] Sign Delay Capture Valid Flag (rh) */
+ unsigned int reserved_16:14; /**< \brief \internal Reserved */
+ unsigned int SGNCS:1; /**< \brief [30:30] Selected Carrier Sign Signal (rh) */
+ unsigned int SGND:1; /**< \brief [31:31] Sign Signal Delayed (rh) */
+} Ifx_DSADC_CH_RECTCFG_Bits;
+
+/** \brief Result Register Auxiliary Filter */
+typedef struct _Ifx_DSADC_CH_RESA_Bits
+{
+ unsigned int RESULT:16; /**< \brief [15:0] Result of most recent conversion (rh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_DSADC_CH_RESA_Bits;
+
+/** \brief Result Register Main Filter */
+typedef struct _Ifx_DSADC_CH_RESM_Bits
+{
+ unsigned int RESULT:16; /**< \brief [15:0] Result of most recent conversion (rh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_DSADC_CH_RESM_Bits;
+
+/** \brief Time-Stamp Register */
+typedef struct _Ifx_DSADC_CH_TSTMP_Bits
+{
+ unsigned int RESULT:16; /**< \brief [15:0] Result of most recent conversion (rh) */
+ unsigned int CFMDCNT:8; /**< \brief [23:16] CIC Filter (Main Chain) Decimation Counter (rh) */
+ unsigned int NVALCNT:6; /**< \brief [29:24] Number of Values Counted (rh) */
+ unsigned int TSVAL:1; /**< \brief [30:30] Timestamp Valid (rh) */
+ unsigned int TSSR:1; /**< \brief [31:31] Timestamp Service Request (rw) */
+} Ifx_DSADC_CH_TSTMP_Bits;
+
+/** \brief Clock Control Register */
+typedef struct _Ifx_DSADC_CLC_Bits
+{
+ unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
+ unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (r) */
+ unsigned int reserved_2:1; /**< \brief \internal Reserved */
+ unsigned int EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control (rw) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_DSADC_CLC_Bits;
+
+/** \brief Event Flag Register */
+typedef struct _Ifx_DSADC_EVFLAG_Bits
+{
+ unsigned int RESEV0:1; /**< \brief [0:0] Result Event (rwh) */
+ unsigned int reserved_1:1; /**< \brief \internal Reserved */
+ unsigned int RESEV2:1; /**< \brief [2:2] Result Event (rwh) */
+ unsigned int RESEV3:1; /**< \brief [3:3] Result Event (rwh) */
+ unsigned int reserved_4:12; /**< \brief \internal Reserved */
+ unsigned int ALEV0:1; /**< \brief [16:16] Alarm Event (rwh) */
+ unsigned int reserved_17:1; /**< \brief \internal Reserved */
+ unsigned int ALEV2:1; /**< \brief [18:18] Alarm Event (rwh) */
+ unsigned int ALEV3:1; /**< \brief [19:19] Alarm Event (rwh) */
+ unsigned int reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_DSADC_EVFLAG_Bits;
+
+/** \brief Event Flag Clear Register */
+typedef struct _Ifx_DSADC_EVFLAGCLR_Bits
+{
+ unsigned int RESEC0:1; /**< \brief [0:0] Result Event Clear (w) */
+ unsigned int reserved_1:1; /**< \brief \internal Reserved */
+ unsigned int RESEC2:1; /**< \brief [2:2] Result Event Clear (w) */
+ unsigned int RESEC3:1; /**< \brief [3:3] Result Event Clear (w) */
+ unsigned int reserved_4:12; /**< \brief \internal Reserved */
+ unsigned int ALEC0:1; /**< \brief [16:16] Alarm Event Clear (w) */
+ unsigned int reserved_17:1; /**< \brief \internal Reserved */
+ unsigned int ALEC2:1; /**< \brief [18:18] Alarm Event Clear (w) */
+ unsigned int ALEC3:1; /**< \brief [19:19] Alarm Event Clear (w) */
+ unsigned int reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_DSADC_EVFLAGCLR_Bits;
+
+/** \brief Global Configuration Register */
+typedef struct _Ifx_DSADC_GLOBCFG_Bits
+{
+ unsigned int MCSEL:3; /**< \brief [2:0] Modulator Clock Select (rw) */
+ unsigned int reserved_3:8; /**< \brief \internal Reserved */
+ unsigned int IRM0:1; /**< \brief [11:11] Internal Resistance Measurement Control (rw) */
+ unsigned int reserved_12:4; /**< \brief \internal Reserved */
+ unsigned int IBSEL:4; /**< \brief [19:16] Bias Current Select (rw) */
+ unsigned int LOSUP:1; /**< \brief [20:20] Low Power Supply Voltage Select (rw) */
+ unsigned int reserved_21:1; /**< \brief \internal Reserved */
+ unsigned int ICT:1; /**< \brief [22:22] Internal Channel Test (rw) */
+ unsigned int PSWC:1; /**< \brief [23:23] Write Control for Power Supply Parameters (w) */
+ unsigned int reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_DSADC_GLOBCFG_Bits;
+
+/** \brief Global Run Control Register */
+typedef struct _Ifx_DSADC_GLOBRC_Bits
+{
+ unsigned int CH0RUN:1; /**< \brief [0:0] Channel 0 Run Control (rw) */
+ unsigned int reserved_1:1; /**< \brief \internal Reserved */
+ unsigned int CH2RUN:1; /**< \brief [2:2] Channel 2 Run Control (rw) */
+ unsigned int CH3RUN:1; /**< \brief [3:3] Channel 3 Run Control (rw) */
+ unsigned int reserved_4:12; /**< \brief \internal Reserved */
+ unsigned int M0RUN:1; /**< \brief [16:16] Modulator 0 Run Control (rw) */
+ unsigned int reserved_17:1; /**< \brief \internal Reserved */
+ unsigned int M2RUN:1; /**< \brief [18:18] Modulator 2 Run Control (rw) */
+ unsigned int M3RUN:1; /**< \brief [19:19] Modulator 3 Run Control (rw) */
+ unsigned int reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_DSADC_GLOBRC_Bits;
+
+/** \brief Common Mode Hold Voltage Register 0 */
+typedef struct _Ifx_DSADC_GLOBVCMH0_Bits
+{
+ unsigned int IN0PVC0:1; /**< \brief [0:0] Voltage Control of Positive Inputs 0-1 of CH0 (rw) */
+ unsigned int IN0PVC1:1; /**< \brief [1:1] Voltage Control of Positive Inputs 0-1 of CH0 (rw) */
+ unsigned int reserved_2:2; /**< \brief \internal Reserved */
+ unsigned int IN0NVC0:1; /**< \brief [4:4] Voltage Control of Negative Inputs 0-1 of CH0 (rw) */
+ unsigned int IN0NVC1:1; /**< \brief [5:5] Voltage Control of Negative Inputs 0-1 of CH0 (rw) */
+ unsigned int reserved_6:10; /**< \brief \internal Reserved */
+ unsigned int IN2PVC0:1; /**< \brief [16:16] Voltage Control of Positive Input 0 of CH2 (rw) */
+ unsigned int reserved_17:3; /**< \brief \internal Reserved */
+ unsigned int IN2NVC0:1; /**< \brief [20:20] Voltage Control of Negative Input 0 of CH2 (rw) */
+ unsigned int reserved_21:3; /**< \brief \internal Reserved */
+ unsigned int IN3PVC0:1; /**< \brief [24:24] Voltage Control of Positive Inputs 0-3 of CH3 (rw) */
+ unsigned int IN3PVC1:1; /**< \brief [25:25] Voltage Control of Positive Inputs 0-3 of CH3 (rw) */
+ unsigned int IN3PVC2:1; /**< \brief [26:26] Voltage Control of Positive Inputs 0-3 of CH3 (rw) */
+ unsigned int IN3PVC3:1; /**< \brief [27:27] Voltage Control of Positive Inputs 0-3 of CH3 (rw) */
+ unsigned int IN3NVC0:1; /**< \brief [28:28] Voltage Control of Negative Inputs 0-3 of CH3 (rw) */
+ unsigned int IN3NVC1:1; /**< \brief [29:29] Voltage Control of Negative Inputs 0-3 of CH3 (rw) */
+ unsigned int IN3NVC2:1; /**< \brief [30:30] Voltage Control of Negative Inputs 0-3 of CH3 (rw) */
+ unsigned int IN3NVC3:1; /**< \brief [31:31] Voltage Control of Negative Inputs 0-3 of CH3 (rw) */
+} Ifx_DSADC_GLOBVCMH0_Bits;
+
+/** \brief Common Mode Hold Voltage Register 2 */
+typedef struct _Ifx_DSADC_GLOBVCMH2_Bits
+{
+ unsigned int reserved_0:29; /**< \brief \internal Reserved */
+ unsigned int VHON:1; /**< \brief [29:29] Common Mode Hold Voltage On (rw) */
+ unsigned int VCMHS:2; /**< \brief [31:30] Common Mode Hold Voltage Selection (rw) */
+} Ifx_DSADC_GLOBVCMH2_Bits;
+
+/** \brief Module Identification Register */
+typedef struct _Ifx_DSADC_ID_Bits
+{
+ unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
+ unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_DSADC_ID_Bits;
+
+/** \brief Initial Global Config. Register */
+typedef struct _Ifx_DSADC_IGCFG_Bits
+{
+ unsigned int DITRIM:3; /**< \brief [2:0] Trimming Value for the Dithering Function (rw) */
+ unsigned int reserved_3:13; /**< \brief \internal Reserved */
+ unsigned int GLOBSP:10; /**< \brief [25:16] Global Setup Parameters for the MultiADC (rw) */
+ unsigned int reserved_26:5; /**< \brief \internal Reserved */
+ unsigned int WREN:1; /**< \brief [31:31] Write Enable (rw) */
+} Ifx_DSADC_IGCFG_Bits;
+
+/** \brief Kernel Reset Register 0 */
+typedef struct _Ifx_DSADC_KRST0_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rh) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_DSADC_KRST0_Bits;
+
+/** \brief Kernel Reset Register 1 */
+typedef struct _Ifx_DSADC_KRST1_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_DSADC_KRST1_Bits;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef struct _Ifx_DSADC_KRSTCLR_Bits
+{
+ unsigned int CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_DSADC_KRSTCLR_Bits;
+
+/** \brief OCDS Control and Status Register */
+typedef struct _Ifx_DSADC_OCS_Bits
+{
+ unsigned int reserved_0:24; /**< \brief \internal Reserved */
+ unsigned int SUS:4; /**< \brief [27:24] OCDS Suspend Control (rw) */
+ unsigned int SUS_P:1; /**< \brief [28:28] SUS Write Protection (w) */
+ unsigned int SUSSTA:1; /**< \brief [29:29] Suspend State (rh) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_DSADC_OCS_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Dsadc_union
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DSADC_ACCEN0_Bits B; /**< \brief Bitfield access */
+} Ifx_DSADC_ACCEN0;
+
+/** \brief Access Protection Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DSADC_ACCPROT_Bits B; /**< \brief Bitfield access */
+} Ifx_DSADC_ACCPROT;
+
+/** \brief Carrier Generator Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DSADC_CGCFG_Bits B; /**< \brief Bitfield access */
+} Ifx_DSADC_CGCFG;
+
+/** \brief Boundary Select Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DSADC_CH_BOUNDSEL_Bits B; /**< \brief Bitfield access */
+} Ifx_DSADC_CH_BOUNDSEL;
+
+/** \brief Carrier Generator Synchronization Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DSADC_CH_CGSYNC_Bits B; /**< \brief Bitfield access */
+} Ifx_DSADC_CH_CGSYNC;
+
+/** \brief Demodulator Input Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DSADC_CH_DICFG_Bits B; /**< \brief Bitfield access */
+} Ifx_DSADC_CH_DICFG;
+
+/** \brief Filter Configuration Register, Auxiliary Filter */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DSADC_CH_FCFGA_Bits B; /**< \brief Bitfield access */
+} Ifx_DSADC_CH_FCFGA;
+
+/** \brief Filter Configuration Register, Main CIC Filter */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DSADC_CH_FCFGC_Bits B; /**< \brief Bitfield access */
+} Ifx_DSADC_CH_FCFGC;
+
+/** \brief Filter Configuration Register, Main Filter Chain */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DSADC_CH_FCFGM_Bits B; /**< \brief Bitfield access */
+} Ifx_DSADC_CH_FCFGM;
+
+/** \brief Initial Channel Config. Reg. 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DSADC_CH_ICCFG_Bits B; /**< \brief Bitfield access */
+} Ifx_DSADC_CH_ICCFG;
+
+/** \brief Integration Window Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DSADC_CH_IWCTR_Bits B; /**< \brief Bitfield access */
+} Ifx_DSADC_CH_IWCTR;
+
+/** \brief Modulator Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DSADC_CH_MODCFG_Bits B; /**< \brief Bitfield access */
+} Ifx_DSADC_CH_MODCFG;
+
+/** \brief Offset Register Main Filter */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DSADC_CH_OFFM_Bits B; /**< \brief Bitfield access */
+} Ifx_DSADC_CH_OFFM;
+
+/** \brief Rectification Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DSADC_CH_RECTCFG_Bits B; /**< \brief Bitfield access */
+} Ifx_DSADC_CH_RECTCFG;
+
+/** \brief Result Register Auxiliary Filter */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DSADC_CH_RESA_Bits B; /**< \brief Bitfield access */
+} Ifx_DSADC_CH_RESA;
+
+/** \brief Result Register Main Filter */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DSADC_CH_RESM_Bits B; /**< \brief Bitfield access */
+} Ifx_DSADC_CH_RESM;
+
+/** \brief Time-Stamp Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DSADC_CH_TSTMP_Bits B; /**< \brief Bitfield access */
+} Ifx_DSADC_CH_TSTMP;
+
+/** \brief Clock Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DSADC_CLC_Bits B; /**< \brief Bitfield access */
+} Ifx_DSADC_CLC;
+
+/** \brief Event Flag Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DSADC_EVFLAG_Bits B; /**< \brief Bitfield access */
+} Ifx_DSADC_EVFLAG;
+
+/** \brief Event Flag Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DSADC_EVFLAGCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_DSADC_EVFLAGCLR;
+
+/** \brief Global Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DSADC_GLOBCFG_Bits B; /**< \brief Bitfield access */
+} Ifx_DSADC_GLOBCFG;
+
+/** \brief Global Run Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DSADC_GLOBRC_Bits B; /**< \brief Bitfield access */
+} Ifx_DSADC_GLOBRC;
+
+/** \brief Common Mode Hold Voltage Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DSADC_GLOBVCMH0_Bits B; /**< \brief Bitfield access */
+} Ifx_DSADC_GLOBVCMH0;
+
+/** \brief Common Mode Hold Voltage Register 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DSADC_GLOBVCMH2_Bits B; /**< \brief Bitfield access */
+} Ifx_DSADC_GLOBVCMH2;
+
+/** \brief Module Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DSADC_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_DSADC_ID;
+
+/** \brief Initial Global Config. Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DSADC_IGCFG_Bits B; /**< \brief Bitfield access */
+} Ifx_DSADC_IGCFG;
+
+/** \brief Kernel Reset Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DSADC_KRST0_Bits B; /**< \brief Bitfield access */
+} Ifx_DSADC_KRST0;
+
+/** \brief Kernel Reset Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DSADC_KRST1_Bits B; /**< \brief Bitfield access */
+} Ifx_DSADC_KRST1;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DSADC_KRSTCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_DSADC_KRSTCLR;
+
+/** \brief OCDS Control and Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_DSADC_OCS_Bits B; /**< \brief Bitfield access */
+} Ifx_DSADC_OCS;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Dsadc_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L1
+ * \{ */
+
+/** \brief Channel objects */
+typedef volatile struct _Ifx_DSADC_CH
+{
+ Ifx_DSADC_CH_MODCFG MODCFG; /**< \brief 0, Modulator Configuration Register */
+ unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
+ Ifx_DSADC_CH_DICFG DICFG; /**< \brief 8, Demodulator Input Configuration Register */
+ unsigned char reserved_C[4]; /**< \brief C, \internal Reserved */
+ Ifx_DSADC_CH_FCFGM FCFGM; /**< \brief 10, Filter Configuration Register, Main Filter Chain */
+ Ifx_DSADC_CH_FCFGC FCFGC; /**< \brief 14, Filter Configuration Register, Main CIC Filter */
+ Ifx_DSADC_CH_FCFGA FCFGA; /**< \brief 18, Filter Configuration Register, Auxiliary Filter */
+ unsigned char reserved_1C[4]; /**< \brief 1C, \internal Reserved */
+ Ifx_DSADC_CH_IWCTR IWCTR; /**< \brief 20, Integration Window Control Register */
+ unsigned char reserved_24[4]; /**< \brief 24, \internal Reserved */
+ Ifx_DSADC_CH_BOUNDSEL BOUNDSEL; /**< \brief 28, Boundary Select Register */
+ unsigned char reserved_2C[4]; /**< \brief 2C, \internal Reserved */
+ Ifx_DSADC_CH_RESM RESM; /**< \brief 30, Result Register Main Filter */
+ unsigned char reserved_34[4]; /**< \brief 34, \internal Reserved */
+ Ifx_DSADC_CH_OFFM OFFM; /**< \brief 38, Offset Register Main Filter */
+ unsigned char reserved_3C[4]; /**< \brief 3C, \internal Reserved */
+ Ifx_DSADC_CH_RESA RESA; /**< \brief 40, Result Register Auxiliary Filter */
+ unsigned char reserved_44[12]; /**< \brief 44, \internal Reserved */
+ Ifx_DSADC_CH_TSTMP TSTMP; /**< \brief 50, Time-Stamp Register */
+ unsigned char reserved_54[76]; /**< \brief 54, \internal Reserved */
+ Ifx_DSADC_CH_CGSYNC CGSYNC; /**< \brief A0, Carrier Generator Synchronization Register */
+ unsigned char reserved_A4[4]; /**< \brief A4, \internal Reserved */
+ Ifx_DSADC_CH_RECTCFG RECTCFG; /**< \brief A8, Rectification Configuration Register */
+ unsigned char reserved_AC[36]; /**< \brief AC, \internal Reserved */
+ Ifx_DSADC_CH_ICCFG ICCFG; /**< \brief D0, Initial Channel Config. Reg. 0 */
+ unsigned char reserved_D4[44]; /**< \brief D4, \internal Reserved */
+} Ifx_DSADC_CH;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Dsadc_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief DSADC object */
+typedef volatile struct _Ifx_DSADC
+{
+ Ifx_DSADC_CLC CLC; /**< \brief 0, Clock Control Register */
+ unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
+ Ifx_DSADC_ID ID; /**< \brief 8, Module Identification Register */
+ unsigned char reserved_C[28]; /**< \brief C, \internal Reserved */
+ Ifx_DSADC_OCS OCS; /**< \brief 28, OCDS Control and Status Register */
+ Ifx_DSADC_KRSTCLR KRSTCLR; /**< \brief 2C, Kernel Reset Status Clear Register */
+ Ifx_DSADC_KRST1 KRST1; /**< \brief 30, Kernel Reset Register 1 */
+ Ifx_DSADC_KRST0 KRST0; /**< \brief 34, Kernel Reset Register 0 */
+ unsigned char reserved_38[4]; /**< \brief 38, \internal Reserved */
+ Ifx_DSADC_ACCEN0 ACCEN0; /**< \brief 3C, Access Enable Register 0 */
+ unsigned char reserved_40[64]; /**< \brief 40, \internal Reserved */
+ Ifx_DSADC_GLOBCFG GLOBCFG; /**< \brief 80, Global Configuration Register */
+ unsigned char reserved_84[4]; /**< \brief 84, \internal Reserved */
+ Ifx_DSADC_GLOBRC GLOBRC; /**< \brief 88, Global Run Control Register */
+ unsigned char reserved_8C[4]; /**< \brief 8C, \internal Reserved */
+ Ifx_DSADC_ACCPROT ACCPROT; /**< \brief 90, Access Protection Register */
+ unsigned char reserved_94[12]; /**< \brief 94, \internal Reserved */
+ Ifx_DSADC_CGCFG CGCFG; /**< \brief A0, Carrier Generator Configuration Register */
+ unsigned char reserved_A4[12]; /**< \brief A4, \internal Reserved */
+ Ifx_DSADC_GLOBVCMH0 GLOBVCMH0; /**< \brief B0, Common Mode Hold Voltage Register 0 */
+ unsigned char reserved_B4[4]; /**< \brief B4, \internal Reserved */
+ Ifx_DSADC_GLOBVCMH2 GLOBVCMH2; /**< \brief B8, Common Mode Hold Voltage Register 2 */
+ unsigned char reserved_BC[20]; /**< \brief BC, \internal Reserved */
+ Ifx_DSADC_IGCFG IGCFG; /**< \brief D0, Initial Global Config. Register */
+ unsigned char reserved_D4[12]; /**< \brief D4, \internal Reserved */
+ Ifx_DSADC_EVFLAG EVFLAG; /**< \brief E0, Event Flag Register */
+ Ifx_DSADC_EVFLAGCLR EVFLAGCLR; /**< \brief E4, Event Flag Clear Register */
+ unsigned char reserved_E8[24]; /**< \brief E8, \internal Reserved */
+ Ifx_DSADC_CH CH[4]; /**< \brief 100, Channel objects */
+ unsigned char reserved_500[2816]; /**< \brief 500, \internal Reserved */
+} Ifx_DSADC;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXDSADC_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEbcu_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEbcu_bf.h
new file mode 100644
index 0000000..1c36532
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEbcu_bf.h
@@ -0,0 +1,621 @@
+/**
+ * \file IfxEbcu_bf.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC2XXED_TS_V1.0.R2
+ * Specification: AurixED_TS_V1.0_CPU_VIEW_SFR.xml (Revision: V1.0)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Ebcu_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Ebcu
+ *
+ */
+#ifndef IFXEBCU_BF_H
+#define IFXEBCU_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Ebcu_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN0 */
+#define IFX_EBCU_ACCEN0_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN0 */
+#define IFX_EBCU_ACCEN0_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN0 */
+#define IFX_EBCU_ACCEN0_EN0_OFF (0u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN10 */
+#define IFX_EBCU_ACCEN0_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN10 */
+#define IFX_EBCU_ACCEN0_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN10 */
+#define IFX_EBCU_ACCEN0_EN10_OFF (10u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN11 */
+#define IFX_EBCU_ACCEN0_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN11 */
+#define IFX_EBCU_ACCEN0_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN11 */
+#define IFX_EBCU_ACCEN0_EN11_OFF (11u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN12 */
+#define IFX_EBCU_ACCEN0_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN12 */
+#define IFX_EBCU_ACCEN0_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN12 */
+#define IFX_EBCU_ACCEN0_EN12_OFF (12u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN13 */
+#define IFX_EBCU_ACCEN0_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN13 */
+#define IFX_EBCU_ACCEN0_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN13 */
+#define IFX_EBCU_ACCEN0_EN13_OFF (13u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN14 */
+#define IFX_EBCU_ACCEN0_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN14 */
+#define IFX_EBCU_ACCEN0_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN14 */
+#define IFX_EBCU_ACCEN0_EN14_OFF (14u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN15 */
+#define IFX_EBCU_ACCEN0_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN15 */
+#define IFX_EBCU_ACCEN0_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN15 */
+#define IFX_EBCU_ACCEN0_EN15_OFF (15u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN16 */
+#define IFX_EBCU_ACCEN0_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN16 */
+#define IFX_EBCU_ACCEN0_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN16 */
+#define IFX_EBCU_ACCEN0_EN16_OFF (16u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN17 */
+#define IFX_EBCU_ACCEN0_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN17 */
+#define IFX_EBCU_ACCEN0_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN17 */
+#define IFX_EBCU_ACCEN0_EN17_OFF (17u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN18 */
+#define IFX_EBCU_ACCEN0_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN18 */
+#define IFX_EBCU_ACCEN0_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN18 */
+#define IFX_EBCU_ACCEN0_EN18_OFF (18u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN19 */
+#define IFX_EBCU_ACCEN0_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN19 */
+#define IFX_EBCU_ACCEN0_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN19 */
+#define IFX_EBCU_ACCEN0_EN19_OFF (19u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN1 */
+#define IFX_EBCU_ACCEN0_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN1 */
+#define IFX_EBCU_ACCEN0_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN1 */
+#define IFX_EBCU_ACCEN0_EN1_OFF (1u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN20 */
+#define IFX_EBCU_ACCEN0_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN20 */
+#define IFX_EBCU_ACCEN0_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN20 */
+#define IFX_EBCU_ACCEN0_EN20_OFF (20u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN21 */
+#define IFX_EBCU_ACCEN0_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN21 */
+#define IFX_EBCU_ACCEN0_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN21 */
+#define IFX_EBCU_ACCEN0_EN21_OFF (21u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN22 */
+#define IFX_EBCU_ACCEN0_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN22 */
+#define IFX_EBCU_ACCEN0_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN22 */
+#define IFX_EBCU_ACCEN0_EN22_OFF (22u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN23 */
+#define IFX_EBCU_ACCEN0_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN23 */
+#define IFX_EBCU_ACCEN0_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN23 */
+#define IFX_EBCU_ACCEN0_EN23_OFF (23u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN24 */
+#define IFX_EBCU_ACCEN0_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN24 */
+#define IFX_EBCU_ACCEN0_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN24 */
+#define IFX_EBCU_ACCEN0_EN24_OFF (24u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN25 */
+#define IFX_EBCU_ACCEN0_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN25 */
+#define IFX_EBCU_ACCEN0_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN25 */
+#define IFX_EBCU_ACCEN0_EN25_OFF (25u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN26 */
+#define IFX_EBCU_ACCEN0_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN26 */
+#define IFX_EBCU_ACCEN0_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN26 */
+#define IFX_EBCU_ACCEN0_EN26_OFF (26u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN27 */
+#define IFX_EBCU_ACCEN0_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN27 */
+#define IFX_EBCU_ACCEN0_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN27 */
+#define IFX_EBCU_ACCEN0_EN27_OFF (27u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN28 */
+#define IFX_EBCU_ACCEN0_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN28 */
+#define IFX_EBCU_ACCEN0_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN28 */
+#define IFX_EBCU_ACCEN0_EN28_OFF (28u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN29 */
+#define IFX_EBCU_ACCEN0_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN29 */
+#define IFX_EBCU_ACCEN0_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN29 */
+#define IFX_EBCU_ACCEN0_EN29_OFF (29u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN2 */
+#define IFX_EBCU_ACCEN0_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN2 */
+#define IFX_EBCU_ACCEN0_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN2 */
+#define IFX_EBCU_ACCEN0_EN2_OFF (2u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN30 */
+#define IFX_EBCU_ACCEN0_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN30 */
+#define IFX_EBCU_ACCEN0_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN30 */
+#define IFX_EBCU_ACCEN0_EN30_OFF (30u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN31 */
+#define IFX_EBCU_ACCEN0_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN31 */
+#define IFX_EBCU_ACCEN0_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN31 */
+#define IFX_EBCU_ACCEN0_EN31_OFF (31u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN3 */
+#define IFX_EBCU_ACCEN0_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN3 */
+#define IFX_EBCU_ACCEN0_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN3 */
+#define IFX_EBCU_ACCEN0_EN3_OFF (3u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN4 */
+#define IFX_EBCU_ACCEN0_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN4 */
+#define IFX_EBCU_ACCEN0_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN4 */
+#define IFX_EBCU_ACCEN0_EN4_OFF (4u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN5 */
+#define IFX_EBCU_ACCEN0_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN5 */
+#define IFX_EBCU_ACCEN0_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN5 */
+#define IFX_EBCU_ACCEN0_EN5_OFF (5u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN6 */
+#define IFX_EBCU_ACCEN0_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN6 */
+#define IFX_EBCU_ACCEN0_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN6 */
+#define IFX_EBCU_ACCEN0_EN6_OFF (6u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN7 */
+#define IFX_EBCU_ACCEN0_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN7 */
+#define IFX_EBCU_ACCEN0_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN7 */
+#define IFX_EBCU_ACCEN0_EN7_OFF (7u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN8 */
+#define IFX_EBCU_ACCEN0_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN8 */
+#define IFX_EBCU_ACCEN0_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN8 */
+#define IFX_EBCU_ACCEN0_EN8_OFF (8u)
+
+/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN9 */
+#define IFX_EBCU_ACCEN0_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN9 */
+#define IFX_EBCU_ACCEN0_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN9 */
+#define IFX_EBCU_ACCEN0_EN9_OFF (9u)
+
+/** \brief Length for Ifx_EBCU_CON_Bits.DBG */
+#define IFX_EBCU_CON_DBG_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_CON_Bits.DBG */
+#define IFX_EBCU_CON_DBG_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_CON_Bits.DBG */
+#define IFX_EBCU_CON_DBG_OFF (16u)
+
+/** \brief Length for Ifx_EBCU_CON_Bits.SPC */
+#define IFX_EBCU_CON_SPC_LEN (8u)
+
+/** \brief Mask for Ifx_EBCU_CON_Bits.SPC */
+#define IFX_EBCU_CON_SPC_MSK (0xffu)
+
+/** \brief Offset for Ifx_EBCU_CON_Bits.SPC */
+#define IFX_EBCU_CON_SPC_OFF (24u)
+
+/** \brief Length for Ifx_EBCU_CON_Bits.TOUT */
+#define IFX_EBCU_CON_TOUT_LEN (16u)
+
+/** \brief Mask for Ifx_EBCU_CON_Bits.TOUT */
+#define IFX_EBCU_CON_TOUT_MSK (0xffffu)
+
+/** \brief Offset for Ifx_EBCU_CON_Bits.TOUT */
+#define IFX_EBCU_CON_TOUT_OFF (0u)
+
+/** \brief Length for Ifx_EBCU_EADD_Bits.FPIADR */
+#define IFX_EBCU_EADD_FPIADR_LEN (32u)
+
+/** \brief Mask for Ifx_EBCU_EADD_Bits.FPIADR */
+#define IFX_EBCU_EADD_FPIADR_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_EBCU_EADD_Bits.FPIADR */
+#define IFX_EBCU_EADD_FPIADR_OFF (0u)
+
+/** \brief Length for Ifx_EBCU_ECON_Bits.ABT */
+#define IFX_EBCU_ECON_ABT_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ECON_Bits.ABT */
+#define IFX_EBCU_ECON_ABT_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ECON_Bits.ABT */
+#define IFX_EBCU_ECON_ABT_OFF (16u)
+
+/** \brief Length for Ifx_EBCU_ECON_Bits.ACK */
+#define IFX_EBCU_ECON_ACK_LEN (2u)
+
+/** \brief Mask for Ifx_EBCU_ECON_Bits.ACK */
+#define IFX_EBCU_ECON_ACK_MSK (0x3u)
+
+/** \brief Offset for Ifx_EBCU_ECON_Bits.ACK */
+#define IFX_EBCU_ECON_ACK_OFF (17u)
+
+/** \brief Length for Ifx_EBCU_ECON_Bits.ERRCNT */
+#define IFX_EBCU_ECON_ERRCNT_LEN (14u)
+
+/** \brief Mask for Ifx_EBCU_ECON_Bits.ERRCNT */
+#define IFX_EBCU_ECON_ERRCNT_MSK (0x3fffu)
+
+/** \brief Offset for Ifx_EBCU_ECON_Bits.ERRCNT */
+#define IFX_EBCU_ECON_ERRCNT_OFF (0u)
+
+/** \brief Length for Ifx_EBCU_ECON_Bits.OPC */
+#define IFX_EBCU_ECON_OPC_LEN (4u)
+
+/** \brief Mask for Ifx_EBCU_ECON_Bits.OPC */
+#define IFX_EBCU_ECON_OPC_MSK (0xfu)
+
+/** \brief Offset for Ifx_EBCU_ECON_Bits.OPC */
+#define IFX_EBCU_ECON_OPC_OFF (28u)
+
+/** \brief Length for Ifx_EBCU_ECON_Bits.RDN */
+#define IFX_EBCU_ECON_RDN_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ECON_Bits.RDN */
+#define IFX_EBCU_ECON_RDN_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ECON_Bits.RDN */
+#define IFX_EBCU_ECON_RDN_OFF (21u)
+
+/** \brief Length for Ifx_EBCU_ECON_Bits.RDY */
+#define IFX_EBCU_ECON_RDY_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ECON_Bits.RDY */
+#define IFX_EBCU_ECON_RDY_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ECON_Bits.RDY */
+#define IFX_EBCU_ECON_RDY_OFF (15u)
+
+/** \brief Length for Ifx_EBCU_ECON_Bits.SVM */
+#define IFX_EBCU_ECON_SVM_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ECON_Bits.SVM */
+#define IFX_EBCU_ECON_SVM_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ECON_Bits.SVM */
+#define IFX_EBCU_ECON_SVM_OFF (19u)
+
+/** \brief Length for Ifx_EBCU_ECON_Bits.TAG */
+#define IFX_EBCU_ECON_TAG_LEN (6u)
+
+/** \brief Mask for Ifx_EBCU_ECON_Bits.TAG */
+#define IFX_EBCU_ECON_TAG_MSK (0x3fu)
+
+/** \brief Offset for Ifx_EBCU_ECON_Bits.TAG */
+#define IFX_EBCU_ECON_TAG_OFF (22u)
+
+/** \brief Length for Ifx_EBCU_ECON_Bits.TOUT */
+#define IFX_EBCU_ECON_TOUT_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ECON_Bits.TOUT */
+#define IFX_EBCU_ECON_TOUT_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ECON_Bits.TOUT */
+#define IFX_EBCU_ECON_TOUT_OFF (14u)
+
+/** \brief Length for Ifx_EBCU_ECON_Bits.WRN */
+#define IFX_EBCU_ECON_WRN_LEN (1u)
+
+/** \brief Mask for Ifx_EBCU_ECON_Bits.WRN */
+#define IFX_EBCU_ECON_WRN_MSK (0x1u)
+
+/** \brief Offset for Ifx_EBCU_ECON_Bits.WRN */
+#define IFX_EBCU_ECON_WRN_OFF (20u)
+
+/** \brief Length for Ifx_EBCU_EDAT_Bits.FPIDAT */
+#define IFX_EBCU_EDAT_FPIDAT_LEN (32u)
+
+/** \brief Mask for Ifx_EBCU_EDAT_Bits.FPIDAT */
+#define IFX_EBCU_EDAT_FPIDAT_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_EBCU_EDAT_Bits.FPIDAT */
+#define IFX_EBCU_EDAT_FPIDAT_OFF (0u)
+
+/** \brief Length for Ifx_EBCU_ID_Bits.MOD_REV */
+#define IFX_EBCU_ID_MOD_REV_LEN (8u)
+
+/** \brief Mask for Ifx_EBCU_ID_Bits.MOD_REV */
+#define IFX_EBCU_ID_MOD_REV_MSK (0xffu)
+
+/** \brief Offset for Ifx_EBCU_ID_Bits.MOD_REV */
+#define IFX_EBCU_ID_MOD_REV_OFF (0u)
+
+/** \brief Length for Ifx_EBCU_ID_Bits.MODNUMBER */
+#define IFX_EBCU_ID_MODNUMBER_LEN (8u)
+
+/** \brief Mask for Ifx_EBCU_ID_Bits.MODNUMBER */
+#define IFX_EBCU_ID_MODNUMBER_MSK (0xffu)
+
+/** \brief Offset for Ifx_EBCU_ID_Bits.MODNUMBER */
+#define IFX_EBCU_ID_MODNUMBER_OFF (8u)
+
+/** \brief Length for Ifx_EBCU_PRIOH_Bits.MASTER10 */
+#define IFX_EBCU_PRIOH_MASTER10_LEN (4u)
+
+/** \brief Mask for Ifx_EBCU_PRIOH_Bits.MASTER10 */
+#define IFX_EBCU_PRIOH_MASTER10_MSK (0xfu)
+
+/** \brief Offset for Ifx_EBCU_PRIOH_Bits.MASTER10 */
+#define IFX_EBCU_PRIOH_MASTER10_OFF (8u)
+
+/** \brief Length for Ifx_EBCU_PRIOH_Bits.MASTER11 */
+#define IFX_EBCU_PRIOH_MASTER11_LEN (4u)
+
+/** \brief Mask for Ifx_EBCU_PRIOH_Bits.MASTER11 */
+#define IFX_EBCU_PRIOH_MASTER11_MSK (0xfu)
+
+/** \brief Offset for Ifx_EBCU_PRIOH_Bits.MASTER11 */
+#define IFX_EBCU_PRIOH_MASTER11_OFF (12u)
+
+/** \brief Length for Ifx_EBCU_PRIOH_Bits.MASTER12 */
+#define IFX_EBCU_PRIOH_MASTER12_LEN (4u)
+
+/** \brief Mask for Ifx_EBCU_PRIOH_Bits.MASTER12 */
+#define IFX_EBCU_PRIOH_MASTER12_MSK (0xfu)
+
+/** \brief Offset for Ifx_EBCU_PRIOH_Bits.MASTER12 */
+#define IFX_EBCU_PRIOH_MASTER12_OFF (16u)
+
+/** \brief Length for Ifx_EBCU_PRIOH_Bits.MASTER13 */
+#define IFX_EBCU_PRIOH_MASTER13_LEN (4u)
+
+/** \brief Mask for Ifx_EBCU_PRIOH_Bits.MASTER13 */
+#define IFX_EBCU_PRIOH_MASTER13_MSK (0xfu)
+
+/** \brief Offset for Ifx_EBCU_PRIOH_Bits.MASTER13 */
+#define IFX_EBCU_PRIOH_MASTER13_OFF (20u)
+
+/** \brief Length for Ifx_EBCU_PRIOH_Bits.MASTER14 */
+#define IFX_EBCU_PRIOH_MASTER14_LEN (4u)
+
+/** \brief Mask for Ifx_EBCU_PRIOH_Bits.MASTER14 */
+#define IFX_EBCU_PRIOH_MASTER14_MSK (0xfu)
+
+/** \brief Offset for Ifx_EBCU_PRIOH_Bits.MASTER14 */
+#define IFX_EBCU_PRIOH_MASTER14_OFF (24u)
+
+/** \brief Length for Ifx_EBCU_PRIOH_Bits.MASTER15 */
+#define IFX_EBCU_PRIOH_MASTER15_LEN (4u)
+
+/** \brief Mask for Ifx_EBCU_PRIOH_Bits.MASTER15 */
+#define IFX_EBCU_PRIOH_MASTER15_MSK (0xfu)
+
+/** \brief Offset for Ifx_EBCU_PRIOH_Bits.MASTER15 */
+#define IFX_EBCU_PRIOH_MASTER15_OFF (28u)
+
+/** \brief Length for Ifx_EBCU_PRIOH_Bits.MASTER8 */
+#define IFX_EBCU_PRIOH_MASTER8_LEN (4u)
+
+/** \brief Mask for Ifx_EBCU_PRIOH_Bits.MASTER8 */
+#define IFX_EBCU_PRIOH_MASTER8_MSK (0xfu)
+
+/** \brief Offset for Ifx_EBCU_PRIOH_Bits.MASTER8 */
+#define IFX_EBCU_PRIOH_MASTER8_OFF (0u)
+
+/** \brief Length for Ifx_EBCU_PRIOH_Bits.MASTER9 */
+#define IFX_EBCU_PRIOH_MASTER9_LEN (4u)
+
+/** \brief Mask for Ifx_EBCU_PRIOH_Bits.MASTER9 */
+#define IFX_EBCU_PRIOH_MASTER9_MSK (0xfu)
+
+/** \brief Offset for Ifx_EBCU_PRIOH_Bits.MASTER9 */
+#define IFX_EBCU_PRIOH_MASTER9_OFF (4u)
+
+/** \brief Length for Ifx_EBCU_PRIOL_Bits.MASTER0 */
+#define IFX_EBCU_PRIOL_MASTER0_LEN (4u)
+
+/** \brief Mask for Ifx_EBCU_PRIOL_Bits.MASTER0 */
+#define IFX_EBCU_PRIOL_MASTER0_MSK (0xfu)
+
+/** \brief Offset for Ifx_EBCU_PRIOL_Bits.MASTER0 */
+#define IFX_EBCU_PRIOL_MASTER0_OFF (0u)
+
+/** \brief Length for Ifx_EBCU_PRIOL_Bits.MASTER1 */
+#define IFX_EBCU_PRIOL_MASTER1_LEN (4u)
+
+/** \brief Mask for Ifx_EBCU_PRIOL_Bits.MASTER1 */
+#define IFX_EBCU_PRIOL_MASTER1_MSK (0xfu)
+
+/** \brief Offset for Ifx_EBCU_PRIOL_Bits.MASTER1 */
+#define IFX_EBCU_PRIOL_MASTER1_OFF (4u)
+
+/** \brief Length for Ifx_EBCU_PRIOL_Bits.MASTER2 */
+#define IFX_EBCU_PRIOL_MASTER2_LEN (4u)
+
+/** \brief Mask for Ifx_EBCU_PRIOL_Bits.MASTER2 */
+#define IFX_EBCU_PRIOL_MASTER2_MSK (0xfu)
+
+/** \brief Offset for Ifx_EBCU_PRIOL_Bits.MASTER2 */
+#define IFX_EBCU_PRIOL_MASTER2_OFF (8u)
+
+/** \brief Length for Ifx_EBCU_PRIOL_Bits.MASTER3 */
+#define IFX_EBCU_PRIOL_MASTER3_LEN (4u)
+
+/** \brief Mask for Ifx_EBCU_PRIOL_Bits.MASTER3 */
+#define IFX_EBCU_PRIOL_MASTER3_MSK (0xfu)
+
+/** \brief Offset for Ifx_EBCU_PRIOL_Bits.MASTER3 */
+#define IFX_EBCU_PRIOL_MASTER3_OFF (12u)
+
+/** \brief Length for Ifx_EBCU_PRIOL_Bits.MASTER4 */
+#define IFX_EBCU_PRIOL_MASTER4_LEN (4u)
+
+/** \brief Mask for Ifx_EBCU_PRIOL_Bits.MASTER4 */
+#define IFX_EBCU_PRIOL_MASTER4_MSK (0xfu)
+
+/** \brief Offset for Ifx_EBCU_PRIOL_Bits.MASTER4 */
+#define IFX_EBCU_PRIOL_MASTER4_OFF (16u)
+
+/** \brief Length for Ifx_EBCU_PRIOL_Bits.MASTER5 */
+#define IFX_EBCU_PRIOL_MASTER5_LEN (4u)
+
+/** \brief Mask for Ifx_EBCU_PRIOL_Bits.MASTER5 */
+#define IFX_EBCU_PRIOL_MASTER5_MSK (0xfu)
+
+/** \brief Offset for Ifx_EBCU_PRIOL_Bits.MASTER5 */
+#define IFX_EBCU_PRIOL_MASTER5_OFF (20u)
+
+/** \brief Length for Ifx_EBCU_PRIOL_Bits.MASTER6 */
+#define IFX_EBCU_PRIOL_MASTER6_LEN (4u)
+
+/** \brief Mask for Ifx_EBCU_PRIOL_Bits.MASTER6 */
+#define IFX_EBCU_PRIOL_MASTER6_MSK (0xfu)
+
+/** \brief Offset for Ifx_EBCU_PRIOL_Bits.MASTER6 */
+#define IFX_EBCU_PRIOL_MASTER6_OFF (24u)
+
+/** \brief Length for Ifx_EBCU_PRIOL_Bits.MASTER7 */
+#define IFX_EBCU_PRIOL_MASTER7_LEN (4u)
+
+/** \brief Mask for Ifx_EBCU_PRIOL_Bits.MASTER7 */
+#define IFX_EBCU_PRIOL_MASTER7_MSK (0xfu)
+
+/** \brief Offset for Ifx_EBCU_PRIOL_Bits.MASTER7 */
+#define IFX_EBCU_PRIOL_MASTER7_OFF (28u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXEBCU_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEbcu_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEbcu_reg.h
new file mode 100644
index 0000000..694d133
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEbcu_reg.h
@@ -0,0 +1,123 @@
+/**
+ * \file IfxEbcu_reg.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC2XXED_TS_V1.0.R2
+ * Specification: AurixED_TS_V1.0_CPU_VIEW_SFR.xml (Revision: V1.0)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Ebcu_Cfg Ebcu address
+ * \ingroup IfxLld_Ebcu
+ *
+ * \defgroup IfxLld_Ebcu_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Ebcu_Cfg
+ *
+ * \defgroup IfxLld_Ebcu_Cfg_Ebcu0 2-EBCU0
+ * \ingroup IfxLld_Ebcu_Cfg
+ *
+ */
+#ifndef IFXEBCU_REG_H
+#define IFXEBCU_REG_H 1
+/******************************************************************************/
+#include "IfxEbcu_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Ebcu_Cfg_BaseAddress
+ * \{ */
+
+/** \brief EBCU object */
+#define MODULE_EBCU0 /*lint --e(923)*/ (*(Ifx_EBCU*)0xF90E0100u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Ebcu_Cfg_Ebcu0
+ * \{ */
+
+/** \brief FC, Access Enable Register 0 */
+#define EBCU0_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_EBCU_ACCEN0*)0xF90E01FCu)
+
+/** Alias (User Manual Name) for EBCU0_ACCEN0.
+* To use register names with standard convension, please use EBCU0_ACCEN0.
+*/
+#define EBCU_ACCEN0 (EBCU0_ACCEN0)
+
+/** \brief F8, Access Enable Register 1 */
+#define EBCU0_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_EBCU_ACCEN1*)0xF90E01F8u)
+
+/** Alias (User Manual Name) for EBCU0_ACCEN1.
+* To use register names with standard convension, please use EBCU0_ACCEN1.
+*/
+#define EBCU_ACCEN1 (EBCU0_ACCEN1)
+
+/** \brief 10, EBCU Control Register */
+#define EBCU0_CON /*lint --e(923)*/ (*(volatile Ifx_EBCU_CON*)0xF90E0110u)
+
+/** Alias (User Manual Name) for EBCU0_CON.
+* To use register names with standard convension, please use EBCU0_CON.
+*/
+#define EBCU_CON (EBCU0_CON)
+
+/** \brief 24, Error Address Capture Register */
+#define EBCU0_EADD /*lint --e(923)*/ (*(volatile Ifx_EBCU_EADD*)0xF90E0124u)
+
+/** Alias (User Manual Name) for EBCU0_EADD.
+* To use register names with standard convension, please use EBCU0_EADD.
+*/
+#define EBCU_EADD (EBCU0_EADD)
+
+/** \brief 20, Error Control Capture Register */
+#define EBCU0_ECON /*lint --e(923)*/ (*(volatile Ifx_EBCU_ECON*)0xF90E0120u)
+
+/** Alias (User Manual Name) for EBCU0_ECON.
+* To use register names with standard convension, please use EBCU0_ECON.
+*/
+#define EBCU_ECON (EBCU0_ECON)
+
+/** \brief 28, Error Data Capture Register */
+#define EBCU0_EDAT /*lint --e(923)*/ (*(volatile Ifx_EBCU_EDAT*)0xF90E0128u)
+
+/** Alias (User Manual Name) for EBCU0_EDAT.
+* To use register names with standard convension, please use EBCU0_EDAT.
+*/
+#define EBCU_EDAT (EBCU0_EDAT)
+
+/** \brief 8, Module Identification Register */
+#define EBCU0_ID /*lint --e(923)*/ (*(volatile Ifx_EBCU_ID*)0xF90E0108u)
+
+/** Alias (User Manual Name) for EBCU0_ID.
+* To use register names with standard convension, please use EBCU0_ID.
+*/
+#define EBCU_ID (EBCU0_ID)
+
+/** \brief 14, Arbiter Priority Register */
+#define EBCU0_PRIOH /*lint --e(923)*/ (*(volatile Ifx_EBCU_PRIOH*)0xF90E0114u)
+
+/** Alias (User Manual Name) for EBCU0_PRIOH.
+* To use register names with standard convension, please use EBCU0_PRIOH.
+*/
+#define EBCU_PRIOH (EBCU0_PRIOH)
+
+/** \brief 18, Arbiter Priority Register */
+#define EBCU0_PRIOL /*lint --e(923)*/ (*(volatile Ifx_EBCU_PRIOL*)0xF90E0118u)
+
+/** Alias (User Manual Name) for EBCU0_PRIOL.
+* To use register names with standard convension, please use EBCU0_PRIOL.
+*/
+#define EBCU_PRIOL (EBCU0_PRIOL)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXEBCU_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEbcu_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEbcu_regdef.h
new file mode 100644
index 0000000..df803c7
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEbcu_regdef.h
@@ -0,0 +1,264 @@
+/**
+ * \file IfxEbcu_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC2XXED_TS_V1.0.R2
+ * Specification: AurixED_TS_V1.0_CPU_VIEW_SFR.xml (Revision: V1.0)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Ebcu Ebcu
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Ebcu_Bitfields Bitfields
+ * \ingroup IfxLld_Ebcu
+ *
+ * \defgroup IfxLld_Ebcu_union Union
+ * \ingroup IfxLld_Ebcu
+ *
+ * \defgroup IfxLld_Ebcu_struct Struct
+ * \ingroup IfxLld_Ebcu
+ *
+ */
+#ifndef IFXEBCU_REGDEF_H
+#define IFXEBCU_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Ebcu_Bitfields
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef struct _Ifx_EBCU_ACCEN0_Bits
+{
+ Ifx_Strict_32Bit EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID x (rw) */
+ Ifx_Strict_32Bit EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID x (rw) */
+} Ifx_EBCU_ACCEN0_Bits;
+
+/** \brief Access Enable Register 1 */
+typedef struct _Ifx_EBCU_ACCEN1_Bits
+{
+ Ifx_Strict_32Bit reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_EBCU_ACCEN1_Bits;
+
+/** \brief EBCU Control Register */
+typedef struct _Ifx_EBCU_CON_Bits
+{
+ Ifx_Strict_32Bit TOUT:16; /**< \brief [15:0] Bus Time-Out Value (rw) */
+ Ifx_Strict_32Bit DBG:1; /**< \brief [16:16] Debug Trace Enable (rw) */
+ Ifx_Strict_32Bit reserved_17:7; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SPC:8; /**< \brief [31:24] Starvation Period Control (rw) */
+} Ifx_EBCU_CON_Bits;
+
+/** \brief Error Address Capture Register */
+typedef struct _Ifx_EBCU_EADD_Bits
+{
+ Ifx_Strict_32Bit FPIADR:32; /**< \brief [31:0] Captured FPI Bus Address (rwh) */
+} Ifx_EBCU_EADD_Bits;
+
+/** \brief Error Control Capture Register */
+typedef struct _Ifx_EBCU_ECON_Bits
+{
+ Ifx_Strict_32Bit ERRCNT:14; /**< \brief [13:0] FPI Bus Error Counter (rwh) */
+ Ifx_Strict_32Bit TOUT:1; /**< \brief [14:14] State of FPI Bus Time-Out Signal (rwh) */
+ Ifx_Strict_32Bit RDY:1; /**< \brief [15:15] State of FPI Bus Ready Signal (rwh) */
+ Ifx_Strict_32Bit ABT:1; /**< \brief [16:16] State of FPI Bus Abort Signal (rwh) */
+ Ifx_Strict_32Bit ACK:2; /**< \brief [18:17] State of FPI Bus Acknowledge Signals (rwh) */
+ Ifx_Strict_32Bit SVM:1; /**< \brief [19:19] State of FPI Bus Supervisor Mode Signal (rwh) */
+ Ifx_Strict_32Bit WRN:1; /**< \brief [20:20] State of FPI Bus Write Signal (rwh) */
+ Ifx_Strict_32Bit RDN:1; /**< \brief [21:21] State of FPI Bus Read Signal (rwh) */
+ Ifx_Strict_32Bit TAG:6; /**< \brief [27:22] FPI Bus Master Tag Number Signals (rwh) */
+ Ifx_Strict_32Bit OPC:4; /**< \brief [31:28] FPI Bus Operation Code Signals (rwh) */
+} Ifx_EBCU_ECON_Bits;
+
+/** \brief Error Data Capture Register */
+typedef struct _Ifx_EBCU_EDAT_Bits
+{
+ Ifx_Strict_32Bit FPIDAT:32; /**< \brief [31:0] Captured FPI Bus Address (rwh) */
+} Ifx_EBCU_EDAT_Bits;
+
+/** \brief Module Identification Register */
+typedef struct _Ifx_EBCU_ID_Bits
+{
+ Ifx_Strict_32Bit MOD_REV:8; /**< \brief [7:0] Module Revision Number (r) */
+ Ifx_Strict_32Bit MODNUMBER:8; /**< \brief [15:8] Module Number Value (r) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_EBCU_ID_Bits;
+
+/** \brief Arbiter Priority Register */
+typedef struct _Ifx_EBCU_PRIOH_Bits
+{
+ Ifx_Strict_32Bit MASTER8:4; /**< \brief [3:0] Master 8 Priority (rw) */
+ Ifx_Strict_32Bit MASTER9:4; /**< \brief [7:4] Master 9 Priority (rw) */
+ Ifx_Strict_32Bit MASTER10:4; /**< \brief [11:8] Master 10 Priority (rw) */
+ Ifx_Strict_32Bit MASTER11:4; /**< \brief [15:12] Master 11 Priority (rw) */
+ Ifx_Strict_32Bit MASTER12:4; /**< \brief [19:16] Master 12 Priority (rw) */
+ Ifx_Strict_32Bit MASTER13:4; /**< \brief [23:20] Master 13 Priority (rw) */
+ Ifx_Strict_32Bit MASTER14:4; /**< \brief [27:24] Master 14 Priority (rw) */
+ Ifx_Strict_32Bit MASTER15:4; /**< \brief [31:28] Master 15 Priority (rw) */
+} Ifx_EBCU_PRIOH_Bits;
+
+/** \brief Arbiter Priority Register */
+typedef struct _Ifx_EBCU_PRIOL_Bits
+{
+ Ifx_Strict_32Bit MASTER0:4; /**< \brief [3:0] Master 0 Priority (rw) */
+ Ifx_Strict_32Bit MASTER1:4; /**< \brief [7:4] Master 1 Priority (rw) */
+ Ifx_Strict_32Bit MASTER2:4; /**< \brief [11:8] Master 2 Priority (rw) */
+ Ifx_Strict_32Bit MASTER3:4; /**< \brief [15:12] Master 3 Priority (rw) */
+ Ifx_Strict_32Bit MASTER4:4; /**< \brief [19:16] Master 4 Priority (rw) */
+ Ifx_Strict_32Bit MASTER5:4; /**< \brief [23:20] Master 5 Priority (rw) */
+ Ifx_Strict_32Bit MASTER6:4; /**< \brief [27:24] Master 6 Priority (rw) */
+ Ifx_Strict_32Bit MASTER7:4; /**< \brief [31:28] Master 7 Priority (rw) */
+} Ifx_EBCU_PRIOL_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Ebcu_union
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_EBCU_ACCEN0_Bits B; /**< \brief Bitfield access */
+} Ifx_EBCU_ACCEN0;
+
+/** \brief Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_EBCU_ACCEN1_Bits B; /**< \brief Bitfield access */
+} Ifx_EBCU_ACCEN1;
+
+/** \brief EBCU Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_EBCU_CON_Bits B; /**< \brief Bitfield access */
+} Ifx_EBCU_CON;
+
+/** \brief Error Address Capture Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_EBCU_EADD_Bits B; /**< \brief Bitfield access */
+} Ifx_EBCU_EADD;
+
+/** \brief Error Control Capture Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_EBCU_ECON_Bits B; /**< \brief Bitfield access */
+} Ifx_EBCU_ECON;
+
+/** \brief Error Data Capture Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_EBCU_EDAT_Bits B; /**< \brief Bitfield access */
+} Ifx_EBCU_EDAT;
+
+/** \brief Module Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_EBCU_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_EBCU_ID;
+
+/** \brief Arbiter Priority Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_EBCU_PRIOH_Bits B; /**< \brief Bitfield access */
+} Ifx_EBCU_PRIOH;
+
+/** \brief Arbiter Priority Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_EBCU_PRIOL_Bits B; /**< \brief Bitfield access */
+} Ifx_EBCU_PRIOL;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Ebcu_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief EBCU object */
+typedef volatile struct _Ifx_EBCU
+{
+ unsigned char reserved_0[8]; /**< \brief 0, \internal Reserved */
+ Ifx_EBCU_ID ID; /**< \brief 8, Module Identification Register */
+ unsigned char reserved_C[4]; /**< \brief C, \internal Reserved */
+ Ifx_EBCU_CON CON; /**< \brief 10, EBCU Control Register */
+ Ifx_EBCU_PRIOH PRIOH; /**< \brief 14, Arbiter Priority Register */
+ Ifx_EBCU_PRIOL PRIOL; /**< \brief 18, Arbiter Priority Register */
+ unsigned char reserved_1C[4]; /**< \brief 1C, \internal Reserved */
+ Ifx_EBCU_ECON ECON; /**< \brief 20, Error Control Capture Register */
+ Ifx_EBCU_EADD EADD; /**< \brief 24, Error Address Capture Register */
+ Ifx_EBCU_EDAT EDAT; /**< \brief 28, Error Data Capture Register */
+ unsigned char reserved_2C[204]; /**< \brief 2C, \internal Reserved */
+ Ifx_EBCU_ACCEN1 ACCEN1; /**< \brief F8, Access Enable Register 1 */
+ Ifx_EBCU_ACCEN0 ACCEN0; /**< \brief FC, Access Enable Register 0 */
+} Ifx_EBCU;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXEBCU_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEmem_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEmem_bf.h
new file mode 100644
index 0000000..075de8c
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEmem_bf.h
@@ -0,0 +1,954 @@
+/**
+ * \file IfxEmem_bf.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC2XXED_TS_V1.0.R2
+ * Specification: AurixED_TS_V1.0_CPU_VIEW_SFR.xml (Revision: V1.0)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Emem_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Emem
+ *
+ */
+#ifndef IFXEMEM_BF_H
+#define IFXEMEM_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Emem_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_EMEM_CLC_Bits.DISR */
+#define IFX_EMEM_CLC_DISR_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_CLC_Bits.DISR */
+#define IFX_EMEM_CLC_DISR_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_CLC_Bits.DISR */
+#define IFX_EMEM_CLC_DISR_OFF (0u)
+
+/** \brief Length for Ifx_EMEM_CLC_Bits.DISS */
+#define IFX_EMEM_CLC_DISS_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_CLC_Bits.DISS */
+#define IFX_EMEM_CLC_DISS_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_CLC_Bits.DISS */
+#define IFX_EMEM_CLC_DISS_OFF (1u)
+
+/** \brief Length for Ifx_EMEM_ID_Bits.MOD_REV */
+#define IFX_EMEM_ID_MOD_REV_LEN (8u)
+
+/** \brief Mask for Ifx_EMEM_ID_Bits.MOD_REV */
+#define IFX_EMEM_ID_MOD_REV_MSK (0xffu)
+
+/** \brief Offset for Ifx_EMEM_ID_Bits.MOD_REV */
+#define IFX_EMEM_ID_MOD_REV_OFF (0u)
+
+/** \brief Length for Ifx_EMEM_ID_Bits.MOD_TYPE */
+#define IFX_EMEM_ID_MOD_TYPE_LEN (8u)
+
+/** \brief Mask for Ifx_EMEM_ID_Bits.MOD_TYPE */
+#define IFX_EMEM_ID_MOD_TYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_EMEM_ID_Bits.MOD_TYPE */
+#define IFX_EMEM_ID_MOD_TYPE_OFF (8u)
+
+/** \brief Length for Ifx_EMEM_ID_Bits.MODNUMBER */
+#define IFX_EMEM_ID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_EMEM_ID_Bits.MODNUMBER */
+#define IFX_EMEM_ID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_EMEM_ID_Bits.MODNUMBER */
+#define IFX_EMEM_ID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGEN */
+#define IFX_EMEM_SBRCTR_ACGEN_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGEN */
+#define IFX_EMEM_SBRCTR_ACGEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGEN */
+#define IFX_EMEM_SBRCTR_ACGEN_OFF (12u)
+
+/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST0 */
+#define IFX_EMEM_SBRCTR_ACGST0_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST0 */
+#define IFX_EMEM_SBRCTR_ACGST0_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST0 */
+#define IFX_EMEM_SBRCTR_ACGST0_OFF (16u)
+
+/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST10 */
+#define IFX_EMEM_SBRCTR_ACGST10_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST10 */
+#define IFX_EMEM_SBRCTR_ACGST10_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST10 */
+#define IFX_EMEM_SBRCTR_ACGST10_OFF (26u)
+
+/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST11 */
+#define IFX_EMEM_SBRCTR_ACGST11_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST11 */
+#define IFX_EMEM_SBRCTR_ACGST11_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST11 */
+#define IFX_EMEM_SBRCTR_ACGST11_OFF (27u)
+
+/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST12 */
+#define IFX_EMEM_SBRCTR_ACGST12_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST12 */
+#define IFX_EMEM_SBRCTR_ACGST12_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST12 */
+#define IFX_EMEM_SBRCTR_ACGST12_OFF (28u)
+
+/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST13 */
+#define IFX_EMEM_SBRCTR_ACGST13_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST13 */
+#define IFX_EMEM_SBRCTR_ACGST13_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST13 */
+#define IFX_EMEM_SBRCTR_ACGST13_OFF (29u)
+
+/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST14 */
+#define IFX_EMEM_SBRCTR_ACGST14_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST14 */
+#define IFX_EMEM_SBRCTR_ACGST14_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST14 */
+#define IFX_EMEM_SBRCTR_ACGST14_OFF (30u)
+
+/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST15 */
+#define IFX_EMEM_SBRCTR_ACGST15_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST15 */
+#define IFX_EMEM_SBRCTR_ACGST15_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST15 */
+#define IFX_EMEM_SBRCTR_ACGST15_OFF (31u)
+
+/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST1 */
+#define IFX_EMEM_SBRCTR_ACGST1_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST1 */
+#define IFX_EMEM_SBRCTR_ACGST1_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST1 */
+#define IFX_EMEM_SBRCTR_ACGST1_OFF (17u)
+
+/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST2 */
+#define IFX_EMEM_SBRCTR_ACGST2_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST2 */
+#define IFX_EMEM_SBRCTR_ACGST2_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST2 */
+#define IFX_EMEM_SBRCTR_ACGST2_OFF (18u)
+
+/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST3 */
+#define IFX_EMEM_SBRCTR_ACGST3_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST3 */
+#define IFX_EMEM_SBRCTR_ACGST3_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST3 */
+#define IFX_EMEM_SBRCTR_ACGST3_OFF (19u)
+
+/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST4 */
+#define IFX_EMEM_SBRCTR_ACGST4_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST4 */
+#define IFX_EMEM_SBRCTR_ACGST4_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST4 */
+#define IFX_EMEM_SBRCTR_ACGST4_OFF (20u)
+
+/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST5 */
+#define IFX_EMEM_SBRCTR_ACGST5_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST5 */
+#define IFX_EMEM_SBRCTR_ACGST5_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST5 */
+#define IFX_EMEM_SBRCTR_ACGST5_OFF (21u)
+
+/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST6 */
+#define IFX_EMEM_SBRCTR_ACGST6_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST6 */
+#define IFX_EMEM_SBRCTR_ACGST6_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST6 */
+#define IFX_EMEM_SBRCTR_ACGST6_OFF (22u)
+
+/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST7 */
+#define IFX_EMEM_SBRCTR_ACGST7_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST7 */
+#define IFX_EMEM_SBRCTR_ACGST7_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST7 */
+#define IFX_EMEM_SBRCTR_ACGST7_OFF (23u)
+
+/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST8 */
+#define IFX_EMEM_SBRCTR_ACGST8_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST8 */
+#define IFX_EMEM_SBRCTR_ACGST8_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST8 */
+#define IFX_EMEM_SBRCTR_ACGST8_OFF (24u)
+
+/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST9 */
+#define IFX_EMEM_SBRCTR_ACGST9_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST9 */
+#define IFX_EMEM_SBRCTR_ACGST9_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST9 */
+#define IFX_EMEM_SBRCTR_ACGST9_OFF (25u)
+
+/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGSXCM0 */
+#define IFX_EMEM_SBRCTR_ACGSXCM0_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGSXCM0 */
+#define IFX_EMEM_SBRCTR_ACGSXCM0_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGSXCM0 */
+#define IFX_EMEM_SBRCTR_ACGSXCM0_OFF (8u)
+
+/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGSXTM0 */
+#define IFX_EMEM_SBRCTR_ACGSXTM0_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGSXTM0 */
+#define IFX_EMEM_SBRCTR_ACGSXTM0_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGSXTM0 */
+#define IFX_EMEM_SBRCTR_ACGSXTM0_OFF (13u)
+
+/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGSXTM1 */
+#define IFX_EMEM_SBRCTR_ACGSXTM1_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGSXTM1 */
+#define IFX_EMEM_SBRCTR_ACGSXTM1_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGSXTM1 */
+#define IFX_EMEM_SBRCTR_ACGSXTM1_OFF (14u)
+
+/** \brief Length for Ifx_EMEM_SBRCTR_Bits.STBLOCK */
+#define IFX_EMEM_SBRCTR_STBLOCK_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.STBLOCK */
+#define IFX_EMEM_SBRCTR_STBLOCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.STBLOCK */
+#define IFX_EMEM_SBRCTR_STBLOCK_OFF (0u)
+
+/** \brief Length for Ifx_EMEM_SBRCTR_Bits.STBSLK */
+#define IFX_EMEM_SBRCTR_STBSLK_LEN (4u)
+
+/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.STBSLK */
+#define IFX_EMEM_SBRCTR_STBSLK_MSK (0xfu)
+
+/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.STBSLK */
+#define IFX_EMEM_SBRCTR_STBSLK_OFF (4u)
+
+/** \brief Length for Ifx_EMEM_SBRCTR_Bits.STBULK */
+#define IFX_EMEM_SBRCTR_STBULK_LEN (3u)
+
+/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.STBULK */
+#define IFX_EMEM_SBRCTR_STBULK_MSK (0x7u)
+
+/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.STBULK */
+#define IFX_EMEM_SBRCTR_STBULK_OFF (1u)
+
+/** \brief Length for Ifx_EMEM_TILECC_Bits.T0 */
+#define IFX_EMEM_TILECC_T0_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECC_Bits.T0 */
+#define IFX_EMEM_TILECC_T0_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECC_Bits.T0 */
+#define IFX_EMEM_TILECC_T0_OFF (0u)
+
+/** \brief Length for Ifx_EMEM_TILECC_Bits.T10 */
+#define IFX_EMEM_TILECC_T10_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECC_Bits.T10 */
+#define IFX_EMEM_TILECC_T10_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECC_Bits.T10 */
+#define IFX_EMEM_TILECC_T10_OFF (10u)
+
+/** \brief Length for Ifx_EMEM_TILECC_Bits.T11 */
+#define IFX_EMEM_TILECC_T11_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECC_Bits.T11 */
+#define IFX_EMEM_TILECC_T11_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECC_Bits.T11 */
+#define IFX_EMEM_TILECC_T11_OFF (11u)
+
+/** \brief Length for Ifx_EMEM_TILECC_Bits.T12 */
+#define IFX_EMEM_TILECC_T12_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECC_Bits.T12 */
+#define IFX_EMEM_TILECC_T12_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECC_Bits.T12 */
+#define IFX_EMEM_TILECC_T12_OFF (12u)
+
+/** \brief Length for Ifx_EMEM_TILECC_Bits.T13 */
+#define IFX_EMEM_TILECC_T13_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECC_Bits.T13 */
+#define IFX_EMEM_TILECC_T13_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECC_Bits.T13 */
+#define IFX_EMEM_TILECC_T13_OFF (13u)
+
+/** \brief Length for Ifx_EMEM_TILECC_Bits.T14 */
+#define IFX_EMEM_TILECC_T14_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECC_Bits.T14 */
+#define IFX_EMEM_TILECC_T14_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECC_Bits.T14 */
+#define IFX_EMEM_TILECC_T14_OFF (14u)
+
+/** \brief Length for Ifx_EMEM_TILECC_Bits.T15 */
+#define IFX_EMEM_TILECC_T15_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECC_Bits.T15 */
+#define IFX_EMEM_TILECC_T15_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECC_Bits.T15 */
+#define IFX_EMEM_TILECC_T15_OFF (15u)
+
+/** \brief Length for Ifx_EMEM_TILECC_Bits.T1 */
+#define IFX_EMEM_TILECC_T1_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECC_Bits.T1 */
+#define IFX_EMEM_TILECC_T1_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECC_Bits.T1 */
+#define IFX_EMEM_TILECC_T1_OFF (1u)
+
+/** \brief Length for Ifx_EMEM_TILECC_Bits.T2 */
+#define IFX_EMEM_TILECC_T2_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECC_Bits.T2 */
+#define IFX_EMEM_TILECC_T2_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECC_Bits.T2 */
+#define IFX_EMEM_TILECC_T2_OFF (2u)
+
+/** \brief Length for Ifx_EMEM_TILECC_Bits.T3 */
+#define IFX_EMEM_TILECC_T3_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECC_Bits.T3 */
+#define IFX_EMEM_TILECC_T3_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECC_Bits.T3 */
+#define IFX_EMEM_TILECC_T3_OFF (3u)
+
+/** \brief Length for Ifx_EMEM_TILECC_Bits.T4 */
+#define IFX_EMEM_TILECC_T4_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECC_Bits.T4 */
+#define IFX_EMEM_TILECC_T4_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECC_Bits.T4 */
+#define IFX_EMEM_TILECC_T4_OFF (4u)
+
+/** \brief Length for Ifx_EMEM_TILECC_Bits.T5 */
+#define IFX_EMEM_TILECC_T5_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECC_Bits.T5 */
+#define IFX_EMEM_TILECC_T5_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECC_Bits.T5 */
+#define IFX_EMEM_TILECC_T5_OFF (5u)
+
+/** \brief Length for Ifx_EMEM_TILECC_Bits.T6 */
+#define IFX_EMEM_TILECC_T6_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECC_Bits.T6 */
+#define IFX_EMEM_TILECC_T6_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECC_Bits.T6 */
+#define IFX_EMEM_TILECC_T6_OFF (6u)
+
+/** \brief Length for Ifx_EMEM_TILECC_Bits.T7 */
+#define IFX_EMEM_TILECC_T7_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECC_Bits.T7 */
+#define IFX_EMEM_TILECC_T7_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECC_Bits.T7 */
+#define IFX_EMEM_TILECC_T7_OFF (7u)
+
+/** \brief Length for Ifx_EMEM_TILECC_Bits.T8 */
+#define IFX_EMEM_TILECC_T8_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECC_Bits.T8 */
+#define IFX_EMEM_TILECC_T8_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECC_Bits.T8 */
+#define IFX_EMEM_TILECC_T8_OFF (8u)
+
+/** \brief Length for Ifx_EMEM_TILECC_Bits.T9 */
+#define IFX_EMEM_TILECC_T9_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECC_Bits.T9 */
+#define IFX_EMEM_TILECC_T9_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECC_Bits.T9 */
+#define IFX_EMEM_TILECC_T9_OFF (9u)
+
+/** \brief Length for Ifx_EMEM_TILECC_Bits.XTM0 */
+#define IFX_EMEM_TILECC_XTM0_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECC_Bits.XTM0 */
+#define IFX_EMEM_TILECC_XTM0_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECC_Bits.XTM0 */
+#define IFX_EMEM_TILECC_XTM0_OFF (16u)
+
+/** \brief Length for Ifx_EMEM_TILECC_Bits.XTM1 */
+#define IFX_EMEM_TILECC_XTM1_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECC_Bits.XTM1 */
+#define IFX_EMEM_TILECC_XTM1_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECC_Bits.XTM1 */
+#define IFX_EMEM_TILECC_XTM1_OFF (17u)
+
+/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T0 */
+#define IFX_EMEM_TILECONFIG_T0_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T0 */
+#define IFX_EMEM_TILECONFIG_T0_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T0 */
+#define IFX_EMEM_TILECONFIG_T0_OFF (0u)
+
+/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T10 */
+#define IFX_EMEM_TILECONFIG_T10_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T10 */
+#define IFX_EMEM_TILECONFIG_T10_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T10 */
+#define IFX_EMEM_TILECONFIG_T10_OFF (20u)
+
+/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T11 */
+#define IFX_EMEM_TILECONFIG_T11_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T11 */
+#define IFX_EMEM_TILECONFIG_T11_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T11 */
+#define IFX_EMEM_TILECONFIG_T11_OFF (22u)
+
+/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T12 */
+#define IFX_EMEM_TILECONFIG_T12_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T12 */
+#define IFX_EMEM_TILECONFIG_T12_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T12 */
+#define IFX_EMEM_TILECONFIG_T12_OFF (24u)
+
+/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T13 */
+#define IFX_EMEM_TILECONFIG_T13_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T13 */
+#define IFX_EMEM_TILECONFIG_T13_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T13 */
+#define IFX_EMEM_TILECONFIG_T13_OFF (26u)
+
+/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T14 */
+#define IFX_EMEM_TILECONFIG_T14_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T14 */
+#define IFX_EMEM_TILECONFIG_T14_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T14 */
+#define IFX_EMEM_TILECONFIG_T14_OFF (28u)
+
+/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T15 */
+#define IFX_EMEM_TILECONFIG_T15_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T15 */
+#define IFX_EMEM_TILECONFIG_T15_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T15 */
+#define IFX_EMEM_TILECONFIG_T15_OFF (30u)
+
+/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T1 */
+#define IFX_EMEM_TILECONFIG_T1_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T1 */
+#define IFX_EMEM_TILECONFIG_T1_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T1 */
+#define IFX_EMEM_TILECONFIG_T1_OFF (2u)
+
+/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T2 */
+#define IFX_EMEM_TILECONFIG_T2_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T2 */
+#define IFX_EMEM_TILECONFIG_T2_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T2 */
+#define IFX_EMEM_TILECONFIG_T2_OFF (4u)
+
+/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T3 */
+#define IFX_EMEM_TILECONFIG_T3_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T3 */
+#define IFX_EMEM_TILECONFIG_T3_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T3 */
+#define IFX_EMEM_TILECONFIG_T3_OFF (6u)
+
+/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T4 */
+#define IFX_EMEM_TILECONFIG_T4_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T4 */
+#define IFX_EMEM_TILECONFIG_T4_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T4 */
+#define IFX_EMEM_TILECONFIG_T4_OFF (8u)
+
+/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T5 */
+#define IFX_EMEM_TILECONFIG_T5_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T5 */
+#define IFX_EMEM_TILECONFIG_T5_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T5 */
+#define IFX_EMEM_TILECONFIG_T5_OFF (10u)
+
+/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T6 */
+#define IFX_EMEM_TILECONFIG_T6_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T6 */
+#define IFX_EMEM_TILECONFIG_T6_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T6 */
+#define IFX_EMEM_TILECONFIG_T6_OFF (12u)
+
+/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T7 */
+#define IFX_EMEM_TILECONFIG_T7_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T7 */
+#define IFX_EMEM_TILECONFIG_T7_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T7 */
+#define IFX_EMEM_TILECONFIG_T7_OFF (14u)
+
+/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T8 */
+#define IFX_EMEM_TILECONFIG_T8_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T8 */
+#define IFX_EMEM_TILECONFIG_T8_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T8 */
+#define IFX_EMEM_TILECONFIG_T8_OFF (16u)
+
+/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T9 */
+#define IFX_EMEM_TILECONFIG_T9_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T9 */
+#define IFX_EMEM_TILECONFIG_T9_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T9 */
+#define IFX_EMEM_TILECONFIG_T9_OFF (18u)
+
+/** \brief Length for Ifx_EMEM_TILECONFIGXM_Bits.XCM0 */
+#define IFX_EMEM_TILECONFIGXM_XCM0_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILECONFIGXM_Bits.XCM0 */
+#define IFX_EMEM_TILECONFIGXM_XCM0_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILECONFIGXM_Bits.XCM0 */
+#define IFX_EMEM_TILECONFIGXM_XCM0_OFF (0u)
+
+/** \brief Length for Ifx_EMEM_TILECONFIGXM_Bits.XTM0 */
+#define IFX_EMEM_TILECONFIGXM_XTM0_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILECONFIGXM_Bits.XTM0 */
+#define IFX_EMEM_TILECONFIGXM_XTM0_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILECONFIGXM_Bits.XTM0 */
+#define IFX_EMEM_TILECONFIGXM_XTM0_OFF (16u)
+
+/** \brief Length for Ifx_EMEM_TILECONFIGXM_Bits.XTM1 */
+#define IFX_EMEM_TILECONFIGXM_XTM1_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILECONFIGXM_Bits.XTM1 */
+#define IFX_EMEM_TILECONFIGXM_XTM1_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILECONFIGXM_Bits.XTM1 */
+#define IFX_EMEM_TILECONFIGXM_XTM1_OFF (18u)
+
+/** \brief Length for Ifx_EMEM_TILECT_Bits.T0 */
+#define IFX_EMEM_TILECT_T0_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECT_Bits.T0 */
+#define IFX_EMEM_TILECT_T0_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECT_Bits.T0 */
+#define IFX_EMEM_TILECT_T0_OFF (0u)
+
+/** \brief Length for Ifx_EMEM_TILECT_Bits.T10 */
+#define IFX_EMEM_TILECT_T10_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECT_Bits.T10 */
+#define IFX_EMEM_TILECT_T10_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECT_Bits.T10 */
+#define IFX_EMEM_TILECT_T10_OFF (10u)
+
+/** \brief Length for Ifx_EMEM_TILECT_Bits.T11 */
+#define IFX_EMEM_TILECT_T11_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECT_Bits.T11 */
+#define IFX_EMEM_TILECT_T11_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECT_Bits.T11 */
+#define IFX_EMEM_TILECT_T11_OFF (11u)
+
+/** \brief Length for Ifx_EMEM_TILECT_Bits.T12 */
+#define IFX_EMEM_TILECT_T12_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECT_Bits.T12 */
+#define IFX_EMEM_TILECT_T12_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECT_Bits.T12 */
+#define IFX_EMEM_TILECT_T12_OFF (12u)
+
+/** \brief Length for Ifx_EMEM_TILECT_Bits.T13 */
+#define IFX_EMEM_TILECT_T13_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECT_Bits.T13 */
+#define IFX_EMEM_TILECT_T13_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECT_Bits.T13 */
+#define IFX_EMEM_TILECT_T13_OFF (13u)
+
+/** \brief Length for Ifx_EMEM_TILECT_Bits.T14 */
+#define IFX_EMEM_TILECT_T14_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECT_Bits.T14 */
+#define IFX_EMEM_TILECT_T14_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECT_Bits.T14 */
+#define IFX_EMEM_TILECT_T14_OFF (14u)
+
+/** \brief Length for Ifx_EMEM_TILECT_Bits.T15 */
+#define IFX_EMEM_TILECT_T15_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECT_Bits.T15 */
+#define IFX_EMEM_TILECT_T15_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECT_Bits.T15 */
+#define IFX_EMEM_TILECT_T15_OFF (15u)
+
+/** \brief Length for Ifx_EMEM_TILECT_Bits.T1 */
+#define IFX_EMEM_TILECT_T1_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECT_Bits.T1 */
+#define IFX_EMEM_TILECT_T1_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECT_Bits.T1 */
+#define IFX_EMEM_TILECT_T1_OFF (1u)
+
+/** \brief Length for Ifx_EMEM_TILECT_Bits.T2 */
+#define IFX_EMEM_TILECT_T2_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECT_Bits.T2 */
+#define IFX_EMEM_TILECT_T2_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECT_Bits.T2 */
+#define IFX_EMEM_TILECT_T2_OFF (2u)
+
+/** \brief Length for Ifx_EMEM_TILECT_Bits.T3 */
+#define IFX_EMEM_TILECT_T3_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECT_Bits.T3 */
+#define IFX_EMEM_TILECT_T3_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECT_Bits.T3 */
+#define IFX_EMEM_TILECT_T3_OFF (3u)
+
+/** \brief Length for Ifx_EMEM_TILECT_Bits.T4 */
+#define IFX_EMEM_TILECT_T4_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECT_Bits.T4 */
+#define IFX_EMEM_TILECT_T4_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECT_Bits.T4 */
+#define IFX_EMEM_TILECT_T4_OFF (4u)
+
+/** \brief Length for Ifx_EMEM_TILECT_Bits.T5 */
+#define IFX_EMEM_TILECT_T5_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECT_Bits.T5 */
+#define IFX_EMEM_TILECT_T5_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECT_Bits.T5 */
+#define IFX_EMEM_TILECT_T5_OFF (5u)
+
+/** \brief Length for Ifx_EMEM_TILECT_Bits.T6 */
+#define IFX_EMEM_TILECT_T6_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECT_Bits.T6 */
+#define IFX_EMEM_TILECT_T6_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECT_Bits.T6 */
+#define IFX_EMEM_TILECT_T6_OFF (6u)
+
+/** \brief Length for Ifx_EMEM_TILECT_Bits.T7 */
+#define IFX_EMEM_TILECT_T7_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECT_Bits.T7 */
+#define IFX_EMEM_TILECT_T7_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECT_Bits.T7 */
+#define IFX_EMEM_TILECT_T7_OFF (7u)
+
+/** \brief Length for Ifx_EMEM_TILECT_Bits.T8 */
+#define IFX_EMEM_TILECT_T8_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECT_Bits.T8 */
+#define IFX_EMEM_TILECT_T8_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECT_Bits.T8 */
+#define IFX_EMEM_TILECT_T8_OFF (8u)
+
+/** \brief Length for Ifx_EMEM_TILECT_Bits.T9 */
+#define IFX_EMEM_TILECT_T9_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECT_Bits.T9 */
+#define IFX_EMEM_TILECT_T9_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECT_Bits.T9 */
+#define IFX_EMEM_TILECT_T9_OFF (9u)
+
+/** \brief Length for Ifx_EMEM_TILECT_Bits.XTM0 */
+#define IFX_EMEM_TILECT_XTM0_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECT_Bits.XTM0 */
+#define IFX_EMEM_TILECT_XTM0_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECT_Bits.XTM0 */
+#define IFX_EMEM_TILECT_XTM0_OFF (16u)
+
+/** \brief Length for Ifx_EMEM_TILECT_Bits.XTM1 */
+#define IFX_EMEM_TILECT_XTM1_LEN (1u)
+
+/** \brief Mask for Ifx_EMEM_TILECT_Bits.XTM1 */
+#define IFX_EMEM_TILECT_XTM1_MSK (0x1u)
+
+/** \brief Offset for Ifx_EMEM_TILECT_Bits.XTM1 */
+#define IFX_EMEM_TILECT_XTM1_OFF (17u)
+
+/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE0 */
+#define IFX_EMEM_TILESTATE_TILE0_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE0 */
+#define IFX_EMEM_TILESTATE_TILE0_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE0 */
+#define IFX_EMEM_TILESTATE_TILE0_OFF (0u)
+
+/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE10 */
+#define IFX_EMEM_TILESTATE_TILE10_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE10 */
+#define IFX_EMEM_TILESTATE_TILE10_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE10 */
+#define IFX_EMEM_TILESTATE_TILE10_OFF (20u)
+
+/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE11 */
+#define IFX_EMEM_TILESTATE_TILE11_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE11 */
+#define IFX_EMEM_TILESTATE_TILE11_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE11 */
+#define IFX_EMEM_TILESTATE_TILE11_OFF (22u)
+
+/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE12 */
+#define IFX_EMEM_TILESTATE_TILE12_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE12 */
+#define IFX_EMEM_TILESTATE_TILE12_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE12 */
+#define IFX_EMEM_TILESTATE_TILE12_OFF (24u)
+
+/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE13 */
+#define IFX_EMEM_TILESTATE_TILE13_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE13 */
+#define IFX_EMEM_TILESTATE_TILE13_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE13 */
+#define IFX_EMEM_TILESTATE_TILE13_OFF (26u)
+
+/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE14 */
+#define IFX_EMEM_TILESTATE_TILE14_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE14 */
+#define IFX_EMEM_TILESTATE_TILE14_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE14 */
+#define IFX_EMEM_TILESTATE_TILE14_OFF (28u)
+
+/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE15 */
+#define IFX_EMEM_TILESTATE_TILE15_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE15 */
+#define IFX_EMEM_TILESTATE_TILE15_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE15 */
+#define IFX_EMEM_TILESTATE_TILE15_OFF (30u)
+
+/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE1 */
+#define IFX_EMEM_TILESTATE_TILE1_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE1 */
+#define IFX_EMEM_TILESTATE_TILE1_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE1 */
+#define IFX_EMEM_TILESTATE_TILE1_OFF (2u)
+
+/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE2 */
+#define IFX_EMEM_TILESTATE_TILE2_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE2 */
+#define IFX_EMEM_TILESTATE_TILE2_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE2 */
+#define IFX_EMEM_TILESTATE_TILE2_OFF (4u)
+
+/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE3 */
+#define IFX_EMEM_TILESTATE_TILE3_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE3 */
+#define IFX_EMEM_TILESTATE_TILE3_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE3 */
+#define IFX_EMEM_TILESTATE_TILE3_OFF (6u)
+
+/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE4 */
+#define IFX_EMEM_TILESTATE_TILE4_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE4 */
+#define IFX_EMEM_TILESTATE_TILE4_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE4 */
+#define IFX_EMEM_TILESTATE_TILE4_OFF (8u)
+
+/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE5 */
+#define IFX_EMEM_TILESTATE_TILE5_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE5 */
+#define IFX_EMEM_TILESTATE_TILE5_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE5 */
+#define IFX_EMEM_TILESTATE_TILE5_OFF (10u)
+
+/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE6 */
+#define IFX_EMEM_TILESTATE_TILE6_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE6 */
+#define IFX_EMEM_TILESTATE_TILE6_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE6 */
+#define IFX_EMEM_TILESTATE_TILE6_OFF (12u)
+
+/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE7 */
+#define IFX_EMEM_TILESTATE_TILE7_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE7 */
+#define IFX_EMEM_TILESTATE_TILE7_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE7 */
+#define IFX_EMEM_TILESTATE_TILE7_OFF (14u)
+
+/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE8 */
+#define IFX_EMEM_TILESTATE_TILE8_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE8 */
+#define IFX_EMEM_TILESTATE_TILE8_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE8 */
+#define IFX_EMEM_TILESTATE_TILE8_OFF (16u)
+
+/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE9 */
+#define IFX_EMEM_TILESTATE_TILE9_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE9 */
+#define IFX_EMEM_TILESTATE_TILE9_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE9 */
+#define IFX_EMEM_TILESTATE_TILE9_OFF (18u)
+
+/** \brief Length for Ifx_EMEM_TILESTATEXM_Bits.XCM0 */
+#define IFX_EMEM_TILESTATEXM_XCM0_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILESTATEXM_Bits.XCM0 */
+#define IFX_EMEM_TILESTATEXM_XCM0_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILESTATEXM_Bits.XCM0 */
+#define IFX_EMEM_TILESTATEXM_XCM0_OFF (0u)
+
+/** \brief Length for Ifx_EMEM_TILESTATEXM_Bits.XTM0 */
+#define IFX_EMEM_TILESTATEXM_XTM0_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILESTATEXM_Bits.XTM0 */
+#define IFX_EMEM_TILESTATEXM_XTM0_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILESTATEXM_Bits.XTM0 */
+#define IFX_EMEM_TILESTATEXM_XTM0_OFF (16u)
+
+/** \brief Length for Ifx_EMEM_TILESTATEXM_Bits.XTM1 */
+#define IFX_EMEM_TILESTATEXM_XTM1_LEN (2u)
+
+/** \brief Mask for Ifx_EMEM_TILESTATEXM_Bits.XTM1 */
+#define IFX_EMEM_TILESTATEXM_XTM1_MSK (0x3u)
+
+/** \brief Offset for Ifx_EMEM_TILESTATEXM_Bits.XTM1 */
+#define IFX_EMEM_TILESTATEXM_XTM1_OFF (18u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXEMEM_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEmem_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEmem_reg.h
new file mode 100644
index 0000000..8ba9f76
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEmem_reg.h
@@ -0,0 +1,78 @@
+/**
+ * \file IfxEmem_reg.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC2XXED_TS_V1.0.R2
+ * Specification: AurixED_TS_V1.0_CPU_VIEW_SFR.xml (Revision: V1.0)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Emem_Cfg Emem address
+ * \ingroup IfxLld_Emem
+ *
+ * \defgroup IfxLld_Emem_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Emem_Cfg
+ *
+ * \defgroup IfxLld_Emem_Cfg_Emem 2-EMEM
+ * \ingroup IfxLld_Emem_Cfg
+ *
+ */
+#ifndef IFXEMEM_REG_H
+#define IFXEMEM_REG_H 1
+/******************************************************************************/
+#include "IfxEmem_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Emem_Cfg_BaseAddress
+ * \{ */
+
+/** \brief EMEM object */
+#define MODULE_EMEM /*lint --e(923)*/ (*(Ifx_EMEM*)0xF90E6000u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Emem_Cfg_Emem
+ * \{ */
+
+/** \brief 0, Clock Control Register */
+#define EMEM_CLC /*lint --e(923)*/ (*(volatile Ifx_EMEM_CLC*)0xF90E6000u)
+
+/** \brief 8, Module Identification Register */
+#define EMEM_ID /*lint --e(923)*/ (*(volatile Ifx_EMEM_ID*)0xF90E6008u)
+
+/** \brief 34, Standby RAM Control Register */
+#define EMEM_SBRCTR /*lint --e(923)*/ (*(volatile Ifx_EMEM_SBRCTR*)0xF90E6034u)
+
+/** \brief 24, Calibration Tile Control Register */
+#define EMEM_TILECC /*lint --e(923)*/ (*(volatile Ifx_EMEM_TILECC*)0xF90E6024u)
+
+/** \brief 20, Tile Configuration Register */
+#define EMEM_TILECONFIG /*lint --e(923)*/ (*(volatile Ifx_EMEM_TILECONFIG*)0xF90E6020u)
+
+/** \brief 40, Extended Tile Configuration Register */
+#define EMEM_TILECONFIGXM /*lint --e(923)*/ (*(volatile Ifx_EMEM_TILECONFIGXM*)0xF90E6040u)
+
+/** \brief 28, Trace Tile Control Register */
+#define EMEM_TILECT /*lint --e(923)*/ (*(volatile Ifx_EMEM_TILECT*)0xF90E6028u)
+
+/** \brief 2C, Tile Status Register */
+#define EMEM_TILESTATE /*lint --e(923)*/ (*(volatile Ifx_EMEM_TILESTATE*)0xF90E602Cu)
+
+/** \brief 4C, Extended Tile Status Register */
+#define EMEM_TILESTATEXM /*lint --e(923)*/ (*(volatile Ifx_EMEM_TILESTATEXM*)0xF90E604Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXEMEM_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEmem_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEmem_regdef.h
new file mode 100644
index 0000000..06f5693
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEmem_regdef.h
@@ -0,0 +1,309 @@
+/**
+ * \file IfxEmem_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC2XXED_TS_V1.0.R2
+ * Specification: AurixED_TS_V1.0_CPU_VIEW_SFR.xml (Revision: V1.0)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Emem Emem
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Emem_Bitfields Bitfields
+ * \ingroup IfxLld_Emem
+ *
+ * \defgroup IfxLld_Emem_union Union
+ * \ingroup IfxLld_Emem
+ *
+ * \defgroup IfxLld_Emem_struct Struct
+ * \ingroup IfxLld_Emem
+ *
+ */
+#ifndef IFXEMEM_REGDEF_H
+#define IFXEMEM_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Emem_Bitfields
+ * \{ */
+
+/** \brief Clock Control Register */
+typedef struct _Ifx_EMEM_CLC_Bits
+{
+ Ifx_Strict_32Bit DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
+ Ifx_Strict_32Bit DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_EMEM_CLC_Bits;
+
+/** \brief Module Identification Register */
+typedef struct _Ifx_EMEM_ID_Bits
+{
+ Ifx_Strict_32Bit MOD_REV:8; /**< \brief [7:0] Module Revision Number (r) */
+ Ifx_Strict_32Bit MOD_TYPE:8; /**< \brief [15:8] Module Type (r) */
+ Ifx_Strict_32Bit MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_EMEM_ID_Bits;
+
+/** \brief Standby RAM Control Register */
+typedef struct _Ifx_EMEM_SBRCTR_Bits
+{
+ Ifx_Strict_32Bit STBLOCK:1; /**< \brief [0:0] Standby Lock Flag (rh) */
+ Ifx_Strict_32Bit STBULK:3; /**< \brief [3:1] Unlock Standby Lock Flag (w) */
+ Ifx_Strict_32Bit STBSLK:4; /**< \brief [7:4] Set Standby Lock Flag (w) */
+ Ifx_Strict_32Bit ACGSXCM0:1; /**< \brief [8:8] Automatic Clock Gating Status of XCM0 (rh) */
+ Ifx_Strict_32Bit reserved_9:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit ACGEN:1; /**< \brief [12:12] Automatic Clock Gating Enabling (rw) */
+ Ifx_Strict_32Bit ACGSXTM0:1; /**< \brief [13:13] Automatic Clock Gating Status of XTM0 (rh) */
+ Ifx_Strict_32Bit ACGSXTM1:1; /**< \brief [14:14] Automatic Clock Gating Status of XTM1 (rh) */
+ Ifx_Strict_32Bit reserved_15:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit ACGST0:1; /**< \brief [16:16] Automatic Clock Gating Status of Tile 0 (rh) */
+ Ifx_Strict_32Bit ACGST1:1; /**< \brief [17:17] Automatic Clock Gating Status of Tile 1 (rh) */
+ Ifx_Strict_32Bit ACGST2:1; /**< \brief [18:18] Automatic Clock Gating Status of Tile 2 (rh) */
+ Ifx_Strict_32Bit ACGST3:1; /**< \brief [19:19] Automatic Clock Gating Status of Tile 3 (rh) */
+ Ifx_Strict_32Bit ACGST4:1; /**< \brief [20:20] Automatic Clock Gating Status of Tile 4 (rh) */
+ Ifx_Strict_32Bit ACGST5:1; /**< \brief [21:21] Automatic Clock Gating Status of Tile 5 (rh) */
+ Ifx_Strict_32Bit ACGST6:1; /**< \brief [22:22] Automatic Clock Gating Status of Tile 6 (rh) */
+ Ifx_Strict_32Bit ACGST7:1; /**< \brief [23:23] Automatic Clock Gating Status of Tile 7 (rh) */
+ Ifx_Strict_32Bit ACGST8:1; /**< \brief [24:24] Automatic Clock Gating Status of Tile 8 (rh) */
+ Ifx_Strict_32Bit ACGST9:1; /**< \brief [25:25] Automatic Clock Gating Status of Tile 9 (rh) */
+ Ifx_Strict_32Bit ACGST10:1; /**< \brief [26:26] Automatic Clock Gating Status of Tile 10 (rh) */
+ Ifx_Strict_32Bit ACGST11:1; /**< \brief [27:27] Automatic Clock Gating Status of Tile 11 (rh) */
+ Ifx_Strict_32Bit ACGST12:1; /**< \brief [28:28] Automatic Clock Gating Status of Tile 12 (rh) */
+ Ifx_Strict_32Bit ACGST13:1; /**< \brief [29:29] Automatic Clock Gating Status of Tile 13 (rh) */
+ Ifx_Strict_32Bit ACGST14:1; /**< \brief [30:30] Automatic Clock Gating Status of Tile 14 (rh) */
+ Ifx_Strict_32Bit ACGST15:1; /**< \brief [31:31] Automatic Clock Gating Status of Tile 15 (rh) */
+} Ifx_EMEM_SBRCTR_Bits;
+
+/** \brief Calibration Tile Control Register */
+typedef struct _Ifx_EMEM_TILECC_Bits
+{
+ Ifx_Strict_32Bit T0:1; /**< \brief [0:0] Calibration Tile 0 Control Bit (w) */
+ Ifx_Strict_32Bit T1:1; /**< \brief [1:1] Calibration Tile 1 Control Bit (w) */
+ Ifx_Strict_32Bit T2:1; /**< \brief [2:2] Calibration Tile 2 Control Bit (w) */
+ Ifx_Strict_32Bit T3:1; /**< \brief [3:3] Calibration Tile 3 Control Bit (w) */
+ Ifx_Strict_32Bit T4:1; /**< \brief [4:4] Calibration Tile 4 Control Bit (w) */
+ Ifx_Strict_32Bit T5:1; /**< \brief [5:5] Calibration Tile 5 Control Bit (w) */
+ Ifx_Strict_32Bit T6:1; /**< \brief [6:6] Calibration Tile 6 Control Bit (w) */
+ Ifx_Strict_32Bit T7:1; /**< \brief [7:7] Calibration Tile 7 Control Bit (w) */
+ Ifx_Strict_32Bit T8:1; /**< \brief [8:8] Calibration Tile 8 Control Bit (w) */
+ Ifx_Strict_32Bit T9:1; /**< \brief [9:9] Calibration Tile 9 Control Bit (w) */
+ Ifx_Strict_32Bit T10:1; /**< \brief [10:10] Calibration Tile 10 Control Bit (w) */
+ Ifx_Strict_32Bit T11:1; /**< \brief [11:11] Calibration Tile 11 Control Bit (w) */
+ Ifx_Strict_32Bit T12:1; /**< \brief [12:12] Calibration Tile 12 Control Bit (w) */
+ Ifx_Strict_32Bit T13:1; /**< \brief [13:13] Calibration Tile 13 Control Bit (w) */
+ Ifx_Strict_32Bit T14:1; /**< \brief [14:14] Calibration Tile 14 Control Bit (w) */
+ Ifx_Strict_32Bit T15:1; /**< \brief [15:15] Calibration Tile 15 Control Bit (w) */
+ Ifx_Strict_32Bit XTM0:1; /**< \brief [16:16] Calibration XTM0 Tile Control Bit (w) */
+ Ifx_Strict_32Bit XTM1:1; /**< \brief [17:17] Calibration XTM1 Tile Control Bit (w) */
+ Ifx_Strict_32Bit reserved_18:14; /**< \brief \internal Reserved */
+} Ifx_EMEM_TILECC_Bits;
+
+/** \brief Tile Configuration Register */
+typedef struct _Ifx_EMEM_TILECONFIG_Bits
+{
+ Ifx_Strict_32Bit T0:2; /**< \brief [1:0] Tile 0 Allocation (w) */
+ Ifx_Strict_32Bit T1:2; /**< \brief [3:2] Tile 1 Allocation (w) */
+ Ifx_Strict_32Bit T2:2; /**< \brief [5:4] Tile 2 Allocation (w) */
+ Ifx_Strict_32Bit T3:2; /**< \brief [7:6] Tile 3 Allocation (w) */
+ Ifx_Strict_32Bit T4:2; /**< \brief [9:8] Tile 4 Allocation (w) */
+ Ifx_Strict_32Bit T5:2; /**< \brief [11:10] Tile 5 Allocation (w) */
+ Ifx_Strict_32Bit T6:2; /**< \brief [13:12] Tile 6 Allocation (w) */
+ Ifx_Strict_32Bit T7:2; /**< \brief [15:14] Tile 7 Allocation (w) */
+ Ifx_Strict_32Bit T8:2; /**< \brief [17:16] Tile 8 Allocation (w) */
+ Ifx_Strict_32Bit T9:2; /**< \brief [19:18] Tile 9 Allocation (w) */
+ Ifx_Strict_32Bit T10:2; /**< \brief [21:20] Tile 10 Allocation (w) */
+ Ifx_Strict_32Bit T11:2; /**< \brief [23:22] Tile 11 Allocation (w) */
+ Ifx_Strict_32Bit T12:2; /**< \brief [25:24] Tile 12 Allocation (w) */
+ Ifx_Strict_32Bit T13:2; /**< \brief [27:26] Tile 13 Allocation (w) */
+ Ifx_Strict_32Bit T14:2; /**< \brief [29:28] Tile 14 Allocation (w) */
+ Ifx_Strict_32Bit T15:2; /**< \brief [31:30] Tile 15 Allocation (w) */
+} Ifx_EMEM_TILECONFIG_Bits;
+
+/** \brief Extended Tile Configuration Register */
+typedef struct _Ifx_EMEM_TILECONFIGXM_Bits
+{
+ Ifx_Strict_32Bit XCM0:2; /**< \brief [1:0] XCM0 Tile Allocation (w) */
+ Ifx_Strict_32Bit reserved_2:14; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit XTM0:2; /**< \brief [17:16] XTM0 Tile Allocation (w) */
+ Ifx_Strict_32Bit XTM1:2; /**< \brief [19:18] XTM1 Tile Allocation (w) */
+ Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_EMEM_TILECONFIGXM_Bits;
+
+/** \brief Trace Tile Control Register */
+typedef struct _Ifx_EMEM_TILECT_Bits
+{
+ Ifx_Strict_32Bit T0:1; /**< \brief [0:0] Trace Tile 0 Control Bit (w) */
+ Ifx_Strict_32Bit T1:1; /**< \brief [1:1] Trace Tile 1 Control Bit (w) */
+ Ifx_Strict_32Bit T2:1; /**< \brief [2:2] Trace Tile 2 Control Bit (w) */
+ Ifx_Strict_32Bit T3:1; /**< \brief [3:3] Trace Tile 3 Control Bit (w) */
+ Ifx_Strict_32Bit T4:1; /**< \brief [4:4] Trace Tile 4 Control Bit (w) */
+ Ifx_Strict_32Bit T5:1; /**< \brief [5:5] Trace Tile 5 Control Bit (w) */
+ Ifx_Strict_32Bit T6:1; /**< \brief [6:6] Trace Tile 6 Control Bit (w) */
+ Ifx_Strict_32Bit T7:1; /**< \brief [7:7] Trace Tile 7 Control Bit (w) */
+ Ifx_Strict_32Bit T8:1; /**< \brief [8:8] Trace Tile 8 Control Bit (w) */
+ Ifx_Strict_32Bit T9:1; /**< \brief [9:9] Trace Tile 9 Control Bit (w) */
+ Ifx_Strict_32Bit T10:1; /**< \brief [10:10] Trace Tile 10 Control Bit (w) */
+ Ifx_Strict_32Bit T11:1; /**< \brief [11:11] Trace Tile 11 Control Bit (w) */
+ Ifx_Strict_32Bit T12:1; /**< \brief [12:12] Trace Tile 12 Control Bit (w) */
+ Ifx_Strict_32Bit T13:1; /**< \brief [13:13] Trace Tile 13 Control Bit (w) */
+ Ifx_Strict_32Bit T14:1; /**< \brief [14:14] Trace Tile 14 Control Bit (w) */
+ Ifx_Strict_32Bit T15:1; /**< \brief [15:15] Trace Tile 15 Control Bit (w) */
+ Ifx_Strict_32Bit XTM0:1; /**< \brief [16:16] Trace XTM0 Tile Control Bit (w) */
+ Ifx_Strict_32Bit XTM1:1; /**< \brief [17:17] Trace XTM1 Tile Control Bit (w) */
+ Ifx_Strict_32Bit reserved_18:14; /**< \brief \internal Reserved */
+} Ifx_EMEM_TILECT_Bits;
+
+/** \brief Tile Status Register */
+typedef struct _Ifx_EMEM_TILESTATE_Bits
+{
+ Ifx_Strict_32Bit TILE0:2; /**< \brief [1:0] Usage of Tile 0 (rh) */
+ Ifx_Strict_32Bit TILE1:2; /**< \brief [3:2] Usage of Tile 1 (rh) */
+ Ifx_Strict_32Bit TILE2:2; /**< \brief [5:4] Usage of Tile 2 (rh) */
+ Ifx_Strict_32Bit TILE3:2; /**< \brief [7:6] Usage of Tile 3 (rh) */
+ Ifx_Strict_32Bit TILE4:2; /**< \brief [9:8] Usage of Tile 4 (rh) */
+ Ifx_Strict_32Bit TILE5:2; /**< \brief [11:10] Usage of Tile 5 (rh) */
+ Ifx_Strict_32Bit TILE6:2; /**< \brief [13:12] Usage of Tile 6 (rh) */
+ Ifx_Strict_32Bit TILE7:2; /**< \brief [15:14] Usage of Tile 7 (rh) */
+ Ifx_Strict_32Bit TILE8:2; /**< \brief [17:16] Usage of Tile 8 (rh) */
+ Ifx_Strict_32Bit TILE9:2; /**< \brief [19:18] Usage of Tile 9 (rh) */
+ Ifx_Strict_32Bit TILE10:2; /**< \brief [21:20] Usage of Tile 10 (rh) */
+ Ifx_Strict_32Bit TILE11:2; /**< \brief [23:22] Usage of Tile 11 (rh) */
+ Ifx_Strict_32Bit TILE12:2; /**< \brief [25:24] Usage of Tile 12 (rh) */
+ Ifx_Strict_32Bit TILE13:2; /**< \brief [27:26] Usage of Tile 13 (rh) */
+ Ifx_Strict_32Bit TILE14:2; /**< \brief [29:28] Usage of Tile 14 (rh) */
+ Ifx_Strict_32Bit TILE15:2; /**< \brief [31:30] Usage of Tile 15 (rh) */
+} Ifx_EMEM_TILESTATE_Bits;
+
+/** \brief Extended Tile Status Register */
+typedef struct _Ifx_EMEM_TILESTATEXM_Bits
+{
+ Ifx_Strict_32Bit XCM0:2; /**< \brief [1:0] Usage of XCM0 Tile (rh) */
+ Ifx_Strict_32Bit reserved_2:14; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit XTM0:2; /**< \brief [17:16] Usage of XTM0 Tile (rh) */
+ Ifx_Strict_32Bit XTM1:2; /**< \brief [19:18] Usage of XTM1 Tile (rh) */
+ Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_EMEM_TILESTATEXM_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Emem_union
+ * \{ */
+
+/** \brief Clock Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_EMEM_CLC_Bits B; /**< \brief Bitfield access */
+} Ifx_EMEM_CLC;
+
+/** \brief Module Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_EMEM_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_EMEM_ID;
+
+/** \brief Standby RAM Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_EMEM_SBRCTR_Bits B; /**< \brief Bitfield access */
+} Ifx_EMEM_SBRCTR;
+
+/** \brief Calibration Tile Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_EMEM_TILECC_Bits B; /**< \brief Bitfield access */
+} Ifx_EMEM_TILECC;
+
+/** \brief Tile Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_EMEM_TILECONFIG_Bits B; /**< \brief Bitfield access */
+} Ifx_EMEM_TILECONFIG;
+
+/** \brief Extended Tile Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_EMEM_TILECONFIGXM_Bits B; /**< \brief Bitfield access */
+} Ifx_EMEM_TILECONFIGXM;
+
+/** \brief Trace Tile Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_EMEM_TILECT_Bits B; /**< \brief Bitfield access */
+} Ifx_EMEM_TILECT;
+
+/** \brief Tile Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_EMEM_TILESTATE_Bits B; /**< \brief Bitfield access */
+} Ifx_EMEM_TILESTATE;
+
+/** \brief Extended Tile Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_EMEM_TILESTATEXM_Bits B; /**< \brief Bitfield access */
+} Ifx_EMEM_TILESTATEXM;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Emem_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief EMEM object */
+typedef volatile struct _Ifx_EMEM
+{
+ Ifx_EMEM_CLC CLC; /**< \brief 0, Clock Control Register */
+ unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
+ Ifx_EMEM_ID ID; /**< \brief 8, Module Identification Register */
+ unsigned char reserved_C[20]; /**< \brief C, \internal Reserved */
+ Ifx_EMEM_TILECONFIG TILECONFIG; /**< \brief 20, Tile Configuration Register */
+ Ifx_EMEM_TILECC TILECC; /**< \brief 24, Calibration Tile Control Register */
+ Ifx_EMEM_TILECT TILECT; /**< \brief 28, Trace Tile Control Register */
+ Ifx_EMEM_TILESTATE TILESTATE; /**< \brief 2C, Tile Status Register */
+ unsigned char reserved_30[4]; /**< \brief 30, \internal Reserved */
+ Ifx_EMEM_SBRCTR SBRCTR; /**< \brief 34, Standby RAM Control Register */
+ unsigned char reserved_38[8]; /**< \brief 38, \internal Reserved */
+ Ifx_EMEM_TILECONFIGXM TILECONFIGXM; /**< \brief 40, Extended Tile Configuration Register */
+ unsigned char reserved_44[8]; /**< \brief 44, \internal Reserved */
+ Ifx_EMEM_TILESTATEXM TILESTATEXM; /**< \brief 4C, Extended Tile Status Register */
+ unsigned char reserved_50[176]; /**< \brief 50, \internal Reserved */
+} Ifx_EMEM;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXEMEM_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEray_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEray_bf.h
new file mode 100644
index 0000000..78b3fb9
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEray_bf.h
@@ -0,0 +1,10179 @@
+/**
+ * \file IfxEray_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Eray_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Eray
+ *
+ */
+#ifndef IFXERAY_BF_H
+#define IFXERAY_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Eray_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN0 */
+#define IFX_ERAY_ACCEN0_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN0 */
+#define IFX_ERAY_ACCEN0_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN0 */
+#define IFX_ERAY_ACCEN0_EN0_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN10 */
+#define IFX_ERAY_ACCEN0_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN10 */
+#define IFX_ERAY_ACCEN0_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN10 */
+#define IFX_ERAY_ACCEN0_EN10_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN11 */
+#define IFX_ERAY_ACCEN0_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN11 */
+#define IFX_ERAY_ACCEN0_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN11 */
+#define IFX_ERAY_ACCEN0_EN11_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN12 */
+#define IFX_ERAY_ACCEN0_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN12 */
+#define IFX_ERAY_ACCEN0_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN12 */
+#define IFX_ERAY_ACCEN0_EN12_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN13 */
+#define IFX_ERAY_ACCEN0_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN13 */
+#define IFX_ERAY_ACCEN0_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN13 */
+#define IFX_ERAY_ACCEN0_EN13_OFF (13u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN14 */
+#define IFX_ERAY_ACCEN0_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN14 */
+#define IFX_ERAY_ACCEN0_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN14 */
+#define IFX_ERAY_ACCEN0_EN14_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN15 */
+#define IFX_ERAY_ACCEN0_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN15 */
+#define IFX_ERAY_ACCEN0_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN15 */
+#define IFX_ERAY_ACCEN0_EN15_OFF (15u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN16 */
+#define IFX_ERAY_ACCEN0_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN16 */
+#define IFX_ERAY_ACCEN0_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN16 */
+#define IFX_ERAY_ACCEN0_EN16_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN17 */
+#define IFX_ERAY_ACCEN0_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN17 */
+#define IFX_ERAY_ACCEN0_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN17 */
+#define IFX_ERAY_ACCEN0_EN17_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN18 */
+#define IFX_ERAY_ACCEN0_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN18 */
+#define IFX_ERAY_ACCEN0_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN18 */
+#define IFX_ERAY_ACCEN0_EN18_OFF (18u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN19 */
+#define IFX_ERAY_ACCEN0_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN19 */
+#define IFX_ERAY_ACCEN0_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN19 */
+#define IFX_ERAY_ACCEN0_EN19_OFF (19u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN1 */
+#define IFX_ERAY_ACCEN0_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN1 */
+#define IFX_ERAY_ACCEN0_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN1 */
+#define IFX_ERAY_ACCEN0_EN1_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN20 */
+#define IFX_ERAY_ACCEN0_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN20 */
+#define IFX_ERAY_ACCEN0_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN20 */
+#define IFX_ERAY_ACCEN0_EN20_OFF (20u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN21 */
+#define IFX_ERAY_ACCEN0_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN21 */
+#define IFX_ERAY_ACCEN0_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN21 */
+#define IFX_ERAY_ACCEN0_EN21_OFF (21u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN22 */
+#define IFX_ERAY_ACCEN0_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN22 */
+#define IFX_ERAY_ACCEN0_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN22 */
+#define IFX_ERAY_ACCEN0_EN22_OFF (22u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN23 */
+#define IFX_ERAY_ACCEN0_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN23 */
+#define IFX_ERAY_ACCEN0_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN23 */
+#define IFX_ERAY_ACCEN0_EN23_OFF (23u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN24 */
+#define IFX_ERAY_ACCEN0_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN24 */
+#define IFX_ERAY_ACCEN0_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN24 */
+#define IFX_ERAY_ACCEN0_EN24_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN25 */
+#define IFX_ERAY_ACCEN0_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN25 */
+#define IFX_ERAY_ACCEN0_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN25 */
+#define IFX_ERAY_ACCEN0_EN25_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN26 */
+#define IFX_ERAY_ACCEN0_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN26 */
+#define IFX_ERAY_ACCEN0_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN26 */
+#define IFX_ERAY_ACCEN0_EN26_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN27 */
+#define IFX_ERAY_ACCEN0_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN27 */
+#define IFX_ERAY_ACCEN0_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN27 */
+#define IFX_ERAY_ACCEN0_EN27_OFF (27u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN28 */
+#define IFX_ERAY_ACCEN0_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN28 */
+#define IFX_ERAY_ACCEN0_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN28 */
+#define IFX_ERAY_ACCEN0_EN28_OFF (28u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN29 */
+#define IFX_ERAY_ACCEN0_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN29 */
+#define IFX_ERAY_ACCEN0_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN29 */
+#define IFX_ERAY_ACCEN0_EN29_OFF (29u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN2 */
+#define IFX_ERAY_ACCEN0_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN2 */
+#define IFX_ERAY_ACCEN0_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN2 */
+#define IFX_ERAY_ACCEN0_EN2_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN30 */
+#define IFX_ERAY_ACCEN0_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN30 */
+#define IFX_ERAY_ACCEN0_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN30 */
+#define IFX_ERAY_ACCEN0_EN30_OFF (30u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN31 */
+#define IFX_ERAY_ACCEN0_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN31 */
+#define IFX_ERAY_ACCEN0_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN31 */
+#define IFX_ERAY_ACCEN0_EN31_OFF (31u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN3 */
+#define IFX_ERAY_ACCEN0_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN3 */
+#define IFX_ERAY_ACCEN0_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN3 */
+#define IFX_ERAY_ACCEN0_EN3_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN4 */
+#define IFX_ERAY_ACCEN0_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN4 */
+#define IFX_ERAY_ACCEN0_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN4 */
+#define IFX_ERAY_ACCEN0_EN4_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN5 */
+#define IFX_ERAY_ACCEN0_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN5 */
+#define IFX_ERAY_ACCEN0_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN5 */
+#define IFX_ERAY_ACCEN0_EN5_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN6 */
+#define IFX_ERAY_ACCEN0_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN6 */
+#define IFX_ERAY_ACCEN0_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN6 */
+#define IFX_ERAY_ACCEN0_EN6_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN7 */
+#define IFX_ERAY_ACCEN0_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN7 */
+#define IFX_ERAY_ACCEN0_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN7 */
+#define IFX_ERAY_ACCEN0_EN7_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN8 */
+#define IFX_ERAY_ACCEN0_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN8 */
+#define IFX_ERAY_ACCEN0_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN8 */
+#define IFX_ERAY_ACCEN0_EN8_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_ACCEN0_Bits.EN9 */
+#define IFX_ERAY_ACCEN0_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACCEN0_Bits.EN9 */
+#define IFX_ERAY_ACCEN0_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACCEN0_Bits.EN9 */
+#define IFX_ERAY_ACCEN0_EN9_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_ACS_Bits.CEDA */
+#define IFX_ERAY_ACS_CEDA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACS_Bits.CEDA */
+#define IFX_ERAY_ACS_CEDA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACS_Bits.CEDA */
+#define IFX_ERAY_ACS_CEDA_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_ACS_Bits.CEDB */
+#define IFX_ERAY_ACS_CEDB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACS_Bits.CEDB */
+#define IFX_ERAY_ACS_CEDB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACS_Bits.CEDB */
+#define IFX_ERAY_ACS_CEDB_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_ACS_Bits.CIA */
+#define IFX_ERAY_ACS_CIA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACS_Bits.CIA */
+#define IFX_ERAY_ACS_CIA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACS_Bits.CIA */
+#define IFX_ERAY_ACS_CIA_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_ACS_Bits.CIB */
+#define IFX_ERAY_ACS_CIB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACS_Bits.CIB */
+#define IFX_ERAY_ACS_CIB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACS_Bits.CIB */
+#define IFX_ERAY_ACS_CIB_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_ACS_Bits.SBVA */
+#define IFX_ERAY_ACS_SBVA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACS_Bits.SBVA */
+#define IFX_ERAY_ACS_SBVA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACS_Bits.SBVA */
+#define IFX_ERAY_ACS_SBVA_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_ACS_Bits.SBVB */
+#define IFX_ERAY_ACS_SBVB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACS_Bits.SBVB */
+#define IFX_ERAY_ACS_SBVB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACS_Bits.SBVB */
+#define IFX_ERAY_ACS_SBVB_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_ACS_Bits.SEDA */
+#define IFX_ERAY_ACS_SEDA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACS_Bits.SEDA */
+#define IFX_ERAY_ACS_SEDA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACS_Bits.SEDA */
+#define IFX_ERAY_ACS_SEDA_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_ACS_Bits.SEDB */
+#define IFX_ERAY_ACS_SEDB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACS_Bits.SEDB */
+#define IFX_ERAY_ACS_SEDB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACS_Bits.SEDB */
+#define IFX_ERAY_ACS_SEDB_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_ACS_Bits.VFRA */
+#define IFX_ERAY_ACS_VFRA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACS_Bits.VFRA */
+#define IFX_ERAY_ACS_VFRA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACS_Bits.VFRA */
+#define IFX_ERAY_ACS_VFRA_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_ACS_Bits.VFRB */
+#define IFX_ERAY_ACS_VFRB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ACS_Bits.VFRB */
+#define IFX_ERAY_ACS_VFRB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ACS_Bits.VFRB */
+#define IFX_ERAY_ACS_VFRB_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_CCEV_Bits.CCFC */
+#define IFX_ERAY_CCEV_CCFC_LEN (4u)
+
+/** \brief Mask for Ifx_ERAY_CCEV_Bits.CCFC */
+#define IFX_ERAY_CCEV_CCFC_MSK (0xfu)
+
+/** \brief Offset for Ifx_ERAY_CCEV_Bits.CCFC */
+#define IFX_ERAY_CCEV_CCFC_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_CCEV_Bits.ERRM */
+#define IFX_ERAY_CCEV_ERRM_LEN (2u)
+
+/** \brief Mask for Ifx_ERAY_CCEV_Bits.ERRM */
+#define IFX_ERAY_CCEV_ERRM_MSK (0x3u)
+
+/** \brief Offset for Ifx_ERAY_CCEV_Bits.ERRM */
+#define IFX_ERAY_CCEV_ERRM_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_CCEV_Bits.PTAC */
+#define IFX_ERAY_CCEV_PTAC_LEN (5u)
+
+/** \brief Mask for Ifx_ERAY_CCEV_Bits.PTAC */
+#define IFX_ERAY_CCEV_PTAC_MSK (0x1fu)
+
+/** \brief Offset for Ifx_ERAY_CCEV_Bits.PTAC */
+#define IFX_ERAY_CCEV_PTAC_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_CCSV_Bits.CSAI */
+#define IFX_ERAY_CCSV_CSAI_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_CCSV_Bits.CSAI */
+#define IFX_ERAY_CCSV_CSAI_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_CCSV_Bits.CSAI */
+#define IFX_ERAY_CCSV_CSAI_OFF (13u)
+
+/** \brief Length for Ifx_ERAY_CCSV_Bits.CSI */
+#define IFX_ERAY_CCSV_CSI_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_CCSV_Bits.CSI */
+#define IFX_ERAY_CCSV_CSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_CCSV_Bits.CSI */
+#define IFX_ERAY_CCSV_CSI_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_CCSV_Bits.CSNI */
+#define IFX_ERAY_CCSV_CSNI_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_CCSV_Bits.CSNI */
+#define IFX_ERAY_CCSV_CSNI_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_CCSV_Bits.CSNI */
+#define IFX_ERAY_CCSV_CSNI_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_CCSV_Bits.FSI */
+#define IFX_ERAY_CCSV_FSI_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_CCSV_Bits.FSI */
+#define IFX_ERAY_CCSV_FSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_CCSV_Bits.FSI */
+#define IFX_ERAY_CCSV_FSI_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_CCSV_Bits.HRQ */
+#define IFX_ERAY_CCSV_HRQ_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_CCSV_Bits.HRQ */
+#define IFX_ERAY_CCSV_HRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_CCSV_Bits.HRQ */
+#define IFX_ERAY_CCSV_HRQ_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_CCSV_Bits.POCS */
+#define IFX_ERAY_CCSV_POCS_LEN (6u)
+
+/** \brief Mask for Ifx_ERAY_CCSV_Bits.POCS */
+#define IFX_ERAY_CCSV_POCS_MSK (0x3fu)
+
+/** \brief Offset for Ifx_ERAY_CCSV_Bits.POCS */
+#define IFX_ERAY_CCSV_POCS_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_CCSV_Bits.PSL */
+#define IFX_ERAY_CCSV_PSL_LEN (6u)
+
+/** \brief Mask for Ifx_ERAY_CCSV_Bits.PSL */
+#define IFX_ERAY_CCSV_PSL_MSK (0x3fu)
+
+/** \brief Offset for Ifx_ERAY_CCSV_Bits.PSL */
+#define IFX_ERAY_CCSV_PSL_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_CCSV_Bits.RCA */
+#define IFX_ERAY_CCSV_RCA_LEN (5u)
+
+/** \brief Mask for Ifx_ERAY_CCSV_Bits.RCA */
+#define IFX_ERAY_CCSV_RCA_MSK (0x1fu)
+
+/** \brief Offset for Ifx_ERAY_CCSV_Bits.RCA */
+#define IFX_ERAY_CCSV_RCA_OFF (19u)
+
+/** \brief Length for Ifx_ERAY_CCSV_Bits.SLM */
+#define IFX_ERAY_CCSV_SLM_LEN (2u)
+
+/** \brief Mask for Ifx_ERAY_CCSV_Bits.SLM */
+#define IFX_ERAY_CCSV_SLM_MSK (0x3u)
+
+/** \brief Offset for Ifx_ERAY_CCSV_Bits.SLM */
+#define IFX_ERAY_CCSV_SLM_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_CCSV_Bits.WSV */
+#define IFX_ERAY_CCSV_WSV_LEN (3u)
+
+/** \brief Mask for Ifx_ERAY_CCSV_Bits.WSV */
+#define IFX_ERAY_CCSV_WSV_MSK (0x7u)
+
+/** \brief Offset for Ifx_ERAY_CCSV_Bits.WSV */
+#define IFX_ERAY_CCSV_WSV_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_CLC_Bits.DISR */
+#define IFX_ERAY_CLC_DISR_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_CLC_Bits.DISR */
+#define IFX_ERAY_CLC_DISR_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_CLC_Bits.DISR */
+#define IFX_ERAY_CLC_DISR_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_CLC_Bits.DISS */
+#define IFX_ERAY_CLC_DISS_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_CLC_Bits.DISS */
+#define IFX_ERAY_CLC_DISS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_CLC_Bits.DISS */
+#define IFX_ERAY_CLC_DISS_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_CLC_Bits.EDIS */
+#define IFX_ERAY_CLC_EDIS_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_CLC_Bits.EDIS */
+#define IFX_ERAY_CLC_EDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_CLC_Bits.EDIS */
+#define IFX_ERAY_CLC_EDIS_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_CLC_Bits.RMC */
+#define IFX_ERAY_CLC_RMC_LEN (3u)
+
+/** \brief Mask for Ifx_ERAY_CLC_Bits.RMC */
+#define IFX_ERAY_CLC_RMC_MSK (0x7u)
+
+/** \brief Offset for Ifx_ERAY_CLC_Bits.RMC */
+#define IFX_ERAY_CLC_RMC_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_CREL_Bits.DAY */
+#define IFX_ERAY_CREL_DAY_LEN (8u)
+
+/** \brief Mask for Ifx_ERAY_CREL_Bits.DAY */
+#define IFX_ERAY_CREL_DAY_MSK (0xffu)
+
+/** \brief Offset for Ifx_ERAY_CREL_Bits.DAY */
+#define IFX_ERAY_CREL_DAY_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_CREL_Bits.MON */
+#define IFX_ERAY_CREL_MON_LEN (8u)
+
+/** \brief Mask for Ifx_ERAY_CREL_Bits.MON */
+#define IFX_ERAY_CREL_MON_MSK (0xffu)
+
+/** \brief Offset for Ifx_ERAY_CREL_Bits.MON */
+#define IFX_ERAY_CREL_MON_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_CREL_Bits.REL */
+#define IFX_ERAY_CREL_REL_LEN (4u)
+
+/** \brief Mask for Ifx_ERAY_CREL_Bits.REL */
+#define IFX_ERAY_CREL_REL_MSK (0xfu)
+
+/** \brief Offset for Ifx_ERAY_CREL_Bits.REL */
+#define IFX_ERAY_CREL_REL_OFF (28u)
+
+/** \brief Length for Ifx_ERAY_CREL_Bits.STEP */
+#define IFX_ERAY_CREL_STEP_LEN (4u)
+
+/** \brief Mask for Ifx_ERAY_CREL_Bits.STEP */
+#define IFX_ERAY_CREL_STEP_MSK (0xfu)
+
+/** \brief Offset for Ifx_ERAY_CREL_Bits.STEP */
+#define IFX_ERAY_CREL_STEP_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_CREL_Bits.SUBSTEP */
+#define IFX_ERAY_CREL_SUBSTEP_LEN (4u)
+
+/** \brief Mask for Ifx_ERAY_CREL_Bits.SUBSTEP */
+#define IFX_ERAY_CREL_SUBSTEP_MSK (0xfu)
+
+/** \brief Offset for Ifx_ERAY_CREL_Bits.SUBSTEP */
+#define IFX_ERAY_CREL_SUBSTEP_OFF (20u)
+
+/** \brief Length for Ifx_ERAY_CREL_Bits.YEAR */
+#define IFX_ERAY_CREL_YEAR_LEN (4u)
+
+/** \brief Mask for Ifx_ERAY_CREL_Bits.YEAR */
+#define IFX_ERAY_CREL_YEAR_MSK (0xfu)
+
+/** \brief Offset for Ifx_ERAY_CREL_Bits.YEAR */
+#define IFX_ERAY_CREL_YEAR_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_CUST1_Bits.IBF1PAG */
+#define IFX_ERAY_CUST1_IBF1PAG_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_CUST1_Bits.IBF1PAG */
+#define IFX_ERAY_CUST1_IBF1PAG_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_CUST1_Bits.IBF1PAG */
+#define IFX_ERAY_CUST1_IBF1PAG_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_CUST1_Bits.IBF2PAG */
+#define IFX_ERAY_CUST1_IBF2PAG_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_CUST1_Bits.IBF2PAG */
+#define IFX_ERAY_CUST1_IBF2PAG_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_CUST1_Bits.IBF2PAG */
+#define IFX_ERAY_CUST1_IBF2PAG_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_CUST1_Bits.IBFS */
+#define IFX_ERAY_CUST1_IBFS_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_CUST1_Bits.IBFS */
+#define IFX_ERAY_CUST1_IBFS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_CUST1_Bits.IBFS */
+#define IFX_ERAY_CUST1_IBFS_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_CUST1_Bits.IEN */
+#define IFX_ERAY_CUST1_IEN_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_CUST1_Bits.IEN */
+#define IFX_ERAY_CUST1_IEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_CUST1_Bits.IEN */
+#define IFX_ERAY_CUST1_IEN_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_CUST1_Bits.INT0 */
+#define IFX_ERAY_CUST1_INT0_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_CUST1_Bits.INT0 */
+#define IFX_ERAY_CUST1_INT0_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_CUST1_Bits.INT0 */
+#define IFX_ERAY_CUST1_INT0_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_CUST1_Bits.OEN */
+#define IFX_ERAY_CUST1_OEN_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_CUST1_Bits.OEN */
+#define IFX_ERAY_CUST1_OEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_CUST1_Bits.OEN */
+#define IFX_ERAY_CUST1_OEN_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_CUST1_Bits.RISA */
+#define IFX_ERAY_CUST1_RISA_LEN (2u)
+
+/** \brief Mask for Ifx_ERAY_CUST1_Bits.RISA */
+#define IFX_ERAY_CUST1_RISA_MSK (0x3u)
+
+/** \brief Offset for Ifx_ERAY_CUST1_Bits.RISA */
+#define IFX_ERAY_CUST1_RISA_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_CUST1_Bits.RISB */
+#define IFX_ERAY_CUST1_RISB_LEN (2u)
+
+/** \brief Mask for Ifx_ERAY_CUST1_Bits.RISB */
+#define IFX_ERAY_CUST1_RISB_MSK (0x3u)
+
+/** \brief Offset for Ifx_ERAY_CUST1_Bits.RISB */
+#define IFX_ERAY_CUST1_RISB_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_CUST1_Bits.STPWTS */
+#define IFX_ERAY_CUST1_STPWTS_LEN (2u)
+
+/** \brief Mask for Ifx_ERAY_CUST1_Bits.STPWTS */
+#define IFX_ERAY_CUST1_STPWTS_MSK (0x3u)
+
+/** \brief Offset for Ifx_ERAY_CUST1_Bits.STPWTS */
+#define IFX_ERAY_CUST1_STPWTS_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_CUST3_Bits.TO */
+#define IFX_ERAY_CUST3_TO_LEN (32u)
+
+/** \brief Mask for Ifx_ERAY_CUST3_Bits.TO */
+#define IFX_ERAY_CUST3_TO_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ERAY_CUST3_Bits.TO */
+#define IFX_ERAY_CUST3_TO_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_EIER_Bits.CCFE */
+#define IFX_ERAY_EIER_CCFE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIER_Bits.CCFE */
+#define IFX_ERAY_EIER_CCFE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIER_Bits.CCFE */
+#define IFX_ERAY_EIER_CCFE_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_EIER_Bits.CCLE */
+#define IFX_ERAY_EIER_CCLE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIER_Bits.CCLE */
+#define IFX_ERAY_EIER_CCLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIER_Bits.CCLE */
+#define IFX_ERAY_EIER_CCLE_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_EIER_Bits.CNAE */
+#define IFX_ERAY_EIER_CNAE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIER_Bits.CNAE */
+#define IFX_ERAY_EIER_CNAE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIER_Bits.CNAE */
+#define IFX_ERAY_EIER_CNAE_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_EIER_Bits.EDAE */
+#define IFX_ERAY_EIER_EDAE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIER_Bits.EDAE */
+#define IFX_ERAY_EIER_EDAE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIER_Bits.EDAE */
+#define IFX_ERAY_EIER_EDAE_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_EIER_Bits.EDBE */
+#define IFX_ERAY_EIER_EDBE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIER_Bits.EDBE */
+#define IFX_ERAY_EIER_EDBE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIER_Bits.EDBE */
+#define IFX_ERAY_EIER_EDBE_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_EIER_Bits.EERRE */
+#define IFX_ERAY_EIER_EERRE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIER_Bits.EERRE */
+#define IFX_ERAY_EIER_EERRE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIER_Bits.EERRE */
+#define IFX_ERAY_EIER_EERRE_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_EIER_Bits.EFAE */
+#define IFX_ERAY_EIER_EFAE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIER_Bits.EFAE */
+#define IFX_ERAY_EIER_EFAE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIER_Bits.EFAE */
+#define IFX_ERAY_EIER_EFAE_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_EIER_Bits.IIBAE */
+#define IFX_ERAY_EIER_IIBAE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIER_Bits.IIBAE */
+#define IFX_ERAY_EIER_IIBAE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIER_Bits.IIBAE */
+#define IFX_ERAY_EIER_IIBAE_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_EIER_Bits.IOBAE */
+#define IFX_ERAY_EIER_IOBAE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIER_Bits.IOBAE */
+#define IFX_ERAY_EIER_IOBAE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIER_Bits.IOBAE */
+#define IFX_ERAY_EIER_IOBAE_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_EIER_Bits.LTVAE */
+#define IFX_ERAY_EIER_LTVAE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIER_Bits.LTVAE */
+#define IFX_ERAY_EIER_LTVAE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIER_Bits.LTVAE */
+#define IFX_ERAY_EIER_LTVAE_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_EIER_Bits.LTVBE */
+#define IFX_ERAY_EIER_LTVBE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIER_Bits.LTVBE */
+#define IFX_ERAY_EIER_LTVBE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIER_Bits.LTVBE */
+#define IFX_ERAY_EIER_LTVBE_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_EIER_Bits.MHFE */
+#define IFX_ERAY_EIER_MHFE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIER_Bits.MHFE */
+#define IFX_ERAY_EIER_MHFE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIER_Bits.MHFE */
+#define IFX_ERAY_EIER_MHFE_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_EIER_Bits.PEMCE */
+#define IFX_ERAY_EIER_PEMCE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIER_Bits.PEMCE */
+#define IFX_ERAY_EIER_PEMCE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIER_Bits.PEMCE */
+#define IFX_ERAY_EIER_PEMCE_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_EIER_Bits.RFOE */
+#define IFX_ERAY_EIER_RFOE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIER_Bits.RFOE */
+#define IFX_ERAY_EIER_RFOE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIER_Bits.RFOE */
+#define IFX_ERAY_EIER_RFOE_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_EIER_Bits.SFBME */
+#define IFX_ERAY_EIER_SFBME_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIER_Bits.SFBME */
+#define IFX_ERAY_EIER_SFBME_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIER_Bits.SFBME */
+#define IFX_ERAY_EIER_SFBME_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_EIER_Bits.SFOE */
+#define IFX_ERAY_EIER_SFOE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIER_Bits.SFOE */
+#define IFX_ERAY_EIER_SFOE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIER_Bits.SFOE */
+#define IFX_ERAY_EIER_SFOE_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_EIER_Bits.TABAE */
+#define IFX_ERAY_EIER_TABAE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIER_Bits.TABAE */
+#define IFX_ERAY_EIER_TABAE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIER_Bits.TABAE */
+#define IFX_ERAY_EIER_TABAE_OFF (18u)
+
+/** \brief Length for Ifx_ERAY_EIER_Bits.TABBE */
+#define IFX_ERAY_EIER_TABBE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIER_Bits.TABBE */
+#define IFX_ERAY_EIER_TABBE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIER_Bits.TABBE */
+#define IFX_ERAY_EIER_TABBE_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_EIES_Bits.CCFE */
+#define IFX_ERAY_EIES_CCFE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIES_Bits.CCFE */
+#define IFX_ERAY_EIES_CCFE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIES_Bits.CCFE */
+#define IFX_ERAY_EIES_CCFE_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_EIES_Bits.CCLE */
+#define IFX_ERAY_EIES_CCLE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIES_Bits.CCLE */
+#define IFX_ERAY_EIES_CCLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIES_Bits.CCLE */
+#define IFX_ERAY_EIES_CCLE_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_EIES_Bits.CNAE */
+#define IFX_ERAY_EIES_CNAE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIES_Bits.CNAE */
+#define IFX_ERAY_EIES_CNAE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIES_Bits.CNAE */
+#define IFX_ERAY_EIES_CNAE_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_EIES_Bits.EDAE */
+#define IFX_ERAY_EIES_EDAE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIES_Bits.EDAE */
+#define IFX_ERAY_EIES_EDAE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIES_Bits.EDAE */
+#define IFX_ERAY_EIES_EDAE_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_EIES_Bits.EDBE */
+#define IFX_ERAY_EIES_EDBE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIES_Bits.EDBE */
+#define IFX_ERAY_EIES_EDBE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIES_Bits.EDBE */
+#define IFX_ERAY_EIES_EDBE_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_EIES_Bits.EERRE */
+#define IFX_ERAY_EIES_EERRE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIES_Bits.EERRE */
+#define IFX_ERAY_EIES_EERRE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIES_Bits.EERRE */
+#define IFX_ERAY_EIES_EERRE_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_EIES_Bits.EFAE */
+#define IFX_ERAY_EIES_EFAE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIES_Bits.EFAE */
+#define IFX_ERAY_EIES_EFAE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIES_Bits.EFAE */
+#define IFX_ERAY_EIES_EFAE_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_EIES_Bits.IIBAE */
+#define IFX_ERAY_EIES_IIBAE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIES_Bits.IIBAE */
+#define IFX_ERAY_EIES_IIBAE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIES_Bits.IIBAE */
+#define IFX_ERAY_EIES_IIBAE_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_EIES_Bits.IOBAE */
+#define IFX_ERAY_EIES_IOBAE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIES_Bits.IOBAE */
+#define IFX_ERAY_EIES_IOBAE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIES_Bits.IOBAE */
+#define IFX_ERAY_EIES_IOBAE_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_EIES_Bits.LTVAE */
+#define IFX_ERAY_EIES_LTVAE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIES_Bits.LTVAE */
+#define IFX_ERAY_EIES_LTVAE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIES_Bits.LTVAE */
+#define IFX_ERAY_EIES_LTVAE_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_EIES_Bits.LTVBE */
+#define IFX_ERAY_EIES_LTVBE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIES_Bits.LTVBE */
+#define IFX_ERAY_EIES_LTVBE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIES_Bits.LTVBE */
+#define IFX_ERAY_EIES_LTVBE_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_EIES_Bits.MHFE */
+#define IFX_ERAY_EIES_MHFE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIES_Bits.MHFE */
+#define IFX_ERAY_EIES_MHFE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIES_Bits.MHFE */
+#define IFX_ERAY_EIES_MHFE_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_EIES_Bits.PEMCE */
+#define IFX_ERAY_EIES_PEMCE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIES_Bits.PEMCE */
+#define IFX_ERAY_EIES_PEMCE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIES_Bits.PEMCE */
+#define IFX_ERAY_EIES_PEMCE_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_EIES_Bits.RFOE */
+#define IFX_ERAY_EIES_RFOE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIES_Bits.RFOE */
+#define IFX_ERAY_EIES_RFOE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIES_Bits.RFOE */
+#define IFX_ERAY_EIES_RFOE_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_EIES_Bits.SFBME */
+#define IFX_ERAY_EIES_SFBME_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIES_Bits.SFBME */
+#define IFX_ERAY_EIES_SFBME_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIES_Bits.SFBME */
+#define IFX_ERAY_EIES_SFBME_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_EIES_Bits.SFOE */
+#define IFX_ERAY_EIES_SFOE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIES_Bits.SFOE */
+#define IFX_ERAY_EIES_SFOE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIES_Bits.SFOE */
+#define IFX_ERAY_EIES_SFOE_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_EIES_Bits.TABAE */
+#define IFX_ERAY_EIES_TABAE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIES_Bits.TABAE */
+#define IFX_ERAY_EIES_TABAE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIES_Bits.TABAE */
+#define IFX_ERAY_EIES_TABAE_OFF (18u)
+
+/** \brief Length for Ifx_ERAY_EIES_Bits.TABBE */
+#define IFX_ERAY_EIES_TABBE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIES_Bits.TABBE */
+#define IFX_ERAY_EIES_TABBE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIES_Bits.TABBE */
+#define IFX_ERAY_EIES_TABBE_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_EILS_Bits.CCFL */
+#define IFX_ERAY_EILS_CCFL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EILS_Bits.CCFL */
+#define IFX_ERAY_EILS_CCFL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EILS_Bits.CCFL */
+#define IFX_ERAY_EILS_CCFL_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_EILS_Bits.CCLL */
+#define IFX_ERAY_EILS_CCLL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EILS_Bits.CCLL */
+#define IFX_ERAY_EILS_CCLL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EILS_Bits.CCLL */
+#define IFX_ERAY_EILS_CCLL_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_EILS_Bits.CNAL */
+#define IFX_ERAY_EILS_CNAL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EILS_Bits.CNAL */
+#define IFX_ERAY_EILS_CNAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EILS_Bits.CNAL */
+#define IFX_ERAY_EILS_CNAL_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_EILS_Bits.EDAL */
+#define IFX_ERAY_EILS_EDAL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EILS_Bits.EDAL */
+#define IFX_ERAY_EILS_EDAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EILS_Bits.EDAL */
+#define IFX_ERAY_EILS_EDAL_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_EILS_Bits.EDBL */
+#define IFX_ERAY_EILS_EDBL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EILS_Bits.EDBL */
+#define IFX_ERAY_EILS_EDBL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EILS_Bits.EDBL */
+#define IFX_ERAY_EILS_EDBL_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_EILS_Bits.EERRL */
+#define IFX_ERAY_EILS_EERRL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EILS_Bits.EERRL */
+#define IFX_ERAY_EILS_EERRL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EILS_Bits.EERRL */
+#define IFX_ERAY_EILS_EERRL_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_EILS_Bits.EFAL */
+#define IFX_ERAY_EILS_EFAL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EILS_Bits.EFAL */
+#define IFX_ERAY_EILS_EFAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EILS_Bits.EFAL */
+#define IFX_ERAY_EILS_EFAL_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_EILS_Bits.IIBAL */
+#define IFX_ERAY_EILS_IIBAL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EILS_Bits.IIBAL */
+#define IFX_ERAY_EILS_IIBAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EILS_Bits.IIBAL */
+#define IFX_ERAY_EILS_IIBAL_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_EILS_Bits.IOBAL */
+#define IFX_ERAY_EILS_IOBAL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EILS_Bits.IOBAL */
+#define IFX_ERAY_EILS_IOBAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EILS_Bits.IOBAL */
+#define IFX_ERAY_EILS_IOBAL_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_EILS_Bits.LTVAL */
+#define IFX_ERAY_EILS_LTVAL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EILS_Bits.LTVAL */
+#define IFX_ERAY_EILS_LTVAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EILS_Bits.LTVAL */
+#define IFX_ERAY_EILS_LTVAL_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_EILS_Bits.LTVBL */
+#define IFX_ERAY_EILS_LTVBL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EILS_Bits.LTVBL */
+#define IFX_ERAY_EILS_LTVBL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EILS_Bits.LTVBL */
+#define IFX_ERAY_EILS_LTVBL_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_EILS_Bits.MHFL */
+#define IFX_ERAY_EILS_MHFL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EILS_Bits.MHFL */
+#define IFX_ERAY_EILS_MHFL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EILS_Bits.MHFL */
+#define IFX_ERAY_EILS_MHFL_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_EILS_Bits.PEMCL */
+#define IFX_ERAY_EILS_PEMCL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EILS_Bits.PEMCL */
+#define IFX_ERAY_EILS_PEMCL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EILS_Bits.PEMCL */
+#define IFX_ERAY_EILS_PEMCL_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_EILS_Bits.RFOL */
+#define IFX_ERAY_EILS_RFOL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EILS_Bits.RFOL */
+#define IFX_ERAY_EILS_RFOL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EILS_Bits.RFOL */
+#define IFX_ERAY_EILS_RFOL_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_EILS_Bits.SFBML */
+#define IFX_ERAY_EILS_SFBML_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EILS_Bits.SFBML */
+#define IFX_ERAY_EILS_SFBML_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EILS_Bits.SFBML */
+#define IFX_ERAY_EILS_SFBML_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_EILS_Bits.SFOL */
+#define IFX_ERAY_EILS_SFOL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EILS_Bits.SFOL */
+#define IFX_ERAY_EILS_SFOL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EILS_Bits.SFOL */
+#define IFX_ERAY_EILS_SFOL_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_EILS_Bits.TABAL */
+#define IFX_ERAY_EILS_TABAL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EILS_Bits.TABAL */
+#define IFX_ERAY_EILS_TABAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EILS_Bits.TABAL */
+#define IFX_ERAY_EILS_TABAL_OFF (18u)
+
+/** \brief Length for Ifx_ERAY_EILS_Bits.TABBL */
+#define IFX_ERAY_EILS_TABBL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EILS_Bits.TABBL */
+#define IFX_ERAY_EILS_TABBL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EILS_Bits.TABBL */
+#define IFX_ERAY_EILS_TABBL_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_EIR_Bits.CCF */
+#define IFX_ERAY_EIR_CCF_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIR_Bits.CCF */
+#define IFX_ERAY_EIR_CCF_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIR_Bits.CCF */
+#define IFX_ERAY_EIR_CCF_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_EIR_Bits.CCL */
+#define IFX_ERAY_EIR_CCL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIR_Bits.CCL */
+#define IFX_ERAY_EIR_CCL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIR_Bits.CCL */
+#define IFX_ERAY_EIR_CCL_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_EIR_Bits.CNA */
+#define IFX_ERAY_EIR_CNA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIR_Bits.CNA */
+#define IFX_ERAY_EIR_CNA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIR_Bits.CNA */
+#define IFX_ERAY_EIR_CNA_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_EIR_Bits.EDA */
+#define IFX_ERAY_EIR_EDA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIR_Bits.EDA */
+#define IFX_ERAY_EIR_EDA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIR_Bits.EDA */
+#define IFX_ERAY_EIR_EDA_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_EIR_Bits.EDB */
+#define IFX_ERAY_EIR_EDB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIR_Bits.EDB */
+#define IFX_ERAY_EIR_EDB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIR_Bits.EDB */
+#define IFX_ERAY_EIR_EDB_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_EIR_Bits.EERR */
+#define IFX_ERAY_EIR_EERR_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIR_Bits.EERR */
+#define IFX_ERAY_EIR_EERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIR_Bits.EERR */
+#define IFX_ERAY_EIR_EERR_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_EIR_Bits.EFA */
+#define IFX_ERAY_EIR_EFA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIR_Bits.EFA */
+#define IFX_ERAY_EIR_EFA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIR_Bits.EFA */
+#define IFX_ERAY_EIR_EFA_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_EIR_Bits.IIBA */
+#define IFX_ERAY_EIR_IIBA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIR_Bits.IIBA */
+#define IFX_ERAY_EIR_IIBA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIR_Bits.IIBA */
+#define IFX_ERAY_EIR_IIBA_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_EIR_Bits.IOBA */
+#define IFX_ERAY_EIR_IOBA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIR_Bits.IOBA */
+#define IFX_ERAY_EIR_IOBA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIR_Bits.IOBA */
+#define IFX_ERAY_EIR_IOBA_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_EIR_Bits.LTVA */
+#define IFX_ERAY_EIR_LTVA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIR_Bits.LTVA */
+#define IFX_ERAY_EIR_LTVA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIR_Bits.LTVA */
+#define IFX_ERAY_EIR_LTVA_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_EIR_Bits.LTVB */
+#define IFX_ERAY_EIR_LTVB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIR_Bits.LTVB */
+#define IFX_ERAY_EIR_LTVB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIR_Bits.LTVB */
+#define IFX_ERAY_EIR_LTVB_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_EIR_Bits.MHF */
+#define IFX_ERAY_EIR_MHF_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIR_Bits.MHF */
+#define IFX_ERAY_EIR_MHF_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIR_Bits.MHF */
+#define IFX_ERAY_EIR_MHF_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_EIR_Bits.PEMC */
+#define IFX_ERAY_EIR_PEMC_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIR_Bits.PEMC */
+#define IFX_ERAY_EIR_PEMC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIR_Bits.PEMC */
+#define IFX_ERAY_EIR_PEMC_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_EIR_Bits.RFO */
+#define IFX_ERAY_EIR_RFO_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIR_Bits.RFO */
+#define IFX_ERAY_EIR_RFO_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIR_Bits.RFO */
+#define IFX_ERAY_EIR_RFO_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_EIR_Bits.SFBM */
+#define IFX_ERAY_EIR_SFBM_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIR_Bits.SFBM */
+#define IFX_ERAY_EIR_SFBM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIR_Bits.SFBM */
+#define IFX_ERAY_EIR_SFBM_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_EIR_Bits.SFO */
+#define IFX_ERAY_EIR_SFO_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIR_Bits.SFO */
+#define IFX_ERAY_EIR_SFO_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIR_Bits.SFO */
+#define IFX_ERAY_EIR_SFO_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_EIR_Bits.TABA */
+#define IFX_ERAY_EIR_TABA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIR_Bits.TABA */
+#define IFX_ERAY_EIR_TABA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIR_Bits.TABA */
+#define IFX_ERAY_EIR_TABA_OFF (18u)
+
+/** \brief Length for Ifx_ERAY_EIR_Bits.TABB */
+#define IFX_ERAY_EIR_TABB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_EIR_Bits.TABB */
+#define IFX_ERAY_EIR_TABB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_EIR_Bits.TABB */
+#define IFX_ERAY_EIR_TABB_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_ENDN_Bits.ETV */
+#define IFX_ERAY_ENDN_ETV_LEN (32u)
+
+/** \brief Mask for Ifx_ERAY_ENDN_Bits.ETV */
+#define IFX_ERAY_ENDN_ETV_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ERAY_ENDN_Bits.ETV */
+#define IFX_ERAY_ENDN_ETV_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_ESID_Bits.EID */
+#define IFX_ERAY_ESID_EID_LEN (10u)
+
+/** \brief Mask for Ifx_ERAY_ESID_Bits.EID */
+#define IFX_ERAY_ESID_EID_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_ERAY_ESID_Bits.EID */
+#define IFX_ERAY_ESID_EID_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_ESID_Bits.RXEA */
+#define IFX_ERAY_ESID_RXEA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ESID_Bits.RXEA */
+#define IFX_ERAY_ESID_RXEA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ESID_Bits.RXEA */
+#define IFX_ERAY_ESID_RXEA_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_ESID_Bits.RXEB */
+#define IFX_ERAY_ESID_RXEB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ESID_Bits.RXEB */
+#define IFX_ERAY_ESID_RXEB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ESID_Bits.RXEB */
+#define IFX_ERAY_ESID_RXEB_OFF (15u)
+
+/** \brief Length for Ifx_ERAY_FCL_Bits.CL */
+#define IFX_ERAY_FCL_CL_LEN (8u)
+
+/** \brief Mask for Ifx_ERAY_FCL_Bits.CL */
+#define IFX_ERAY_FCL_CL_MSK (0xffu)
+
+/** \brief Offset for Ifx_ERAY_FCL_Bits.CL */
+#define IFX_ERAY_FCL_CL_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_FRF_Bits.CH */
+#define IFX_ERAY_FRF_CH_LEN (2u)
+
+/** \brief Mask for Ifx_ERAY_FRF_Bits.CH */
+#define IFX_ERAY_FRF_CH_MSK (0x3u)
+
+/** \brief Offset for Ifx_ERAY_FRF_Bits.CH */
+#define IFX_ERAY_FRF_CH_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_FRF_Bits.CYF */
+#define IFX_ERAY_FRF_CYF_LEN (7u)
+
+/** \brief Mask for Ifx_ERAY_FRF_Bits.CYF */
+#define IFX_ERAY_FRF_CYF_MSK (0x7fu)
+
+/** \brief Offset for Ifx_ERAY_FRF_Bits.CYF */
+#define IFX_ERAY_FRF_CYF_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_FRF_Bits.FID */
+#define IFX_ERAY_FRF_FID_LEN (11u)
+
+/** \brief Mask for Ifx_ERAY_FRF_Bits.FID */
+#define IFX_ERAY_FRF_FID_MSK (0x7ffu)
+
+/** \brief Offset for Ifx_ERAY_FRF_Bits.FID */
+#define IFX_ERAY_FRF_FID_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_FRF_Bits.RNF */
+#define IFX_ERAY_FRF_RNF_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_FRF_Bits.RNF */
+#define IFX_ERAY_FRF_RNF_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_FRF_Bits.RNF */
+#define IFX_ERAY_FRF_RNF_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_FRF_Bits.RSS */
+#define IFX_ERAY_FRF_RSS_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_FRF_Bits.RSS */
+#define IFX_ERAY_FRF_RSS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_FRF_Bits.RSS */
+#define IFX_ERAY_FRF_RSS_OFF (23u)
+
+/** \brief Length for Ifx_ERAY_FRFM_Bits.MFID */
+#define IFX_ERAY_FRFM_MFID_LEN (11u)
+
+/** \brief Mask for Ifx_ERAY_FRFM_Bits.MFID */
+#define IFX_ERAY_FRFM_MFID_MSK (0x7ffu)
+
+/** \brief Offset for Ifx_ERAY_FRFM_Bits.MFID */
+#define IFX_ERAY_FRFM_MFID_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_FSR_Bits.RFCL */
+#define IFX_ERAY_FSR_RFCL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_FSR_Bits.RFCL */
+#define IFX_ERAY_FSR_RFCL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_FSR_Bits.RFCL */
+#define IFX_ERAY_FSR_RFCL_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_FSR_Bits.RFFL */
+#define IFX_ERAY_FSR_RFFL_LEN (8u)
+
+/** \brief Mask for Ifx_ERAY_FSR_Bits.RFFL */
+#define IFX_ERAY_FSR_RFFL_MSK (0xffu)
+
+/** \brief Offset for Ifx_ERAY_FSR_Bits.RFFL */
+#define IFX_ERAY_FSR_RFFL_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_FSR_Bits.RFNE */
+#define IFX_ERAY_FSR_RFNE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_FSR_Bits.RFNE */
+#define IFX_ERAY_FSR_RFNE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_FSR_Bits.RFNE */
+#define IFX_ERAY_FSR_RFNE_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_FSR_Bits.RFO */
+#define IFX_ERAY_FSR_RFO_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_FSR_Bits.RFO */
+#define IFX_ERAY_FSR_RFO_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_FSR_Bits.RFO */
+#define IFX_ERAY_FSR_RFO_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_GTUC01_Bits.UT */
+#define IFX_ERAY_GTUC01_UT_LEN (20u)
+
+/** \brief Mask for Ifx_ERAY_GTUC01_Bits.UT */
+#define IFX_ERAY_GTUC01_UT_MSK (0xfffffu)
+
+/** \brief Offset for Ifx_ERAY_GTUC01_Bits.UT */
+#define IFX_ERAY_GTUC01_UT_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_GTUC02_Bits.MPC */
+#define IFX_ERAY_GTUC02_MPC_LEN (14u)
+
+/** \brief Mask for Ifx_ERAY_GTUC02_Bits.MPC */
+#define IFX_ERAY_GTUC02_MPC_MSK (0x3fffu)
+
+/** \brief Offset for Ifx_ERAY_GTUC02_Bits.MPC */
+#define IFX_ERAY_GTUC02_MPC_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_GTUC02_Bits.SNM */
+#define IFX_ERAY_GTUC02_SNM_LEN (4u)
+
+/** \brief Mask for Ifx_ERAY_GTUC02_Bits.SNM */
+#define IFX_ERAY_GTUC02_SNM_MSK (0xfu)
+
+/** \brief Offset for Ifx_ERAY_GTUC02_Bits.SNM */
+#define IFX_ERAY_GTUC02_SNM_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_GTUC03_Bits.MIOA */
+#define IFX_ERAY_GTUC03_MIOA_LEN (7u)
+
+/** \brief Mask for Ifx_ERAY_GTUC03_Bits.MIOA */
+#define IFX_ERAY_GTUC03_MIOA_MSK (0x7fu)
+
+/** \brief Offset for Ifx_ERAY_GTUC03_Bits.MIOA */
+#define IFX_ERAY_GTUC03_MIOA_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_GTUC03_Bits.MIOB */
+#define IFX_ERAY_GTUC03_MIOB_LEN (7u)
+
+/** \brief Mask for Ifx_ERAY_GTUC03_Bits.MIOB */
+#define IFX_ERAY_GTUC03_MIOB_MSK (0x7fu)
+
+/** \brief Offset for Ifx_ERAY_GTUC03_Bits.MIOB */
+#define IFX_ERAY_GTUC03_MIOB_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_GTUC03_Bits.UIOA */
+#define IFX_ERAY_GTUC03_UIOA_LEN (8u)
+
+/** \brief Mask for Ifx_ERAY_GTUC03_Bits.UIOA */
+#define IFX_ERAY_GTUC03_UIOA_MSK (0xffu)
+
+/** \brief Offset for Ifx_ERAY_GTUC03_Bits.UIOA */
+#define IFX_ERAY_GTUC03_UIOA_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_GTUC03_Bits.UIOB */
+#define IFX_ERAY_GTUC03_UIOB_LEN (8u)
+
+/** \brief Mask for Ifx_ERAY_GTUC03_Bits.UIOB */
+#define IFX_ERAY_GTUC03_UIOB_MSK (0xffu)
+
+/** \brief Offset for Ifx_ERAY_GTUC03_Bits.UIOB */
+#define IFX_ERAY_GTUC03_UIOB_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_GTUC04_Bits.NIT */
+#define IFX_ERAY_GTUC04_NIT_LEN (14u)
+
+/** \brief Mask for Ifx_ERAY_GTUC04_Bits.NIT */
+#define IFX_ERAY_GTUC04_NIT_MSK (0x3fffu)
+
+/** \brief Offset for Ifx_ERAY_GTUC04_Bits.NIT */
+#define IFX_ERAY_GTUC04_NIT_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_GTUC04_Bits.OCS */
+#define IFX_ERAY_GTUC04_OCS_LEN (14u)
+
+/** \brief Mask for Ifx_ERAY_GTUC04_Bits.OCS */
+#define IFX_ERAY_GTUC04_OCS_MSK (0x3fffu)
+
+/** \brief Offset for Ifx_ERAY_GTUC04_Bits.OCS */
+#define IFX_ERAY_GTUC04_OCS_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_GTUC05_Bits.CDD */
+#define IFX_ERAY_GTUC05_CDD_LEN (5u)
+
+/** \brief Mask for Ifx_ERAY_GTUC05_Bits.CDD */
+#define IFX_ERAY_GTUC05_CDD_MSK (0x1fu)
+
+/** \brief Offset for Ifx_ERAY_GTUC05_Bits.CDD */
+#define IFX_ERAY_GTUC05_CDD_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_GTUC05_Bits.DCA */
+#define IFX_ERAY_GTUC05_DCA_LEN (8u)
+
+/** \brief Mask for Ifx_ERAY_GTUC05_Bits.DCA */
+#define IFX_ERAY_GTUC05_DCA_MSK (0xffu)
+
+/** \brief Offset for Ifx_ERAY_GTUC05_Bits.DCA */
+#define IFX_ERAY_GTUC05_DCA_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_GTUC05_Bits.DCB */
+#define IFX_ERAY_GTUC05_DCB_LEN (8u)
+
+/** \brief Mask for Ifx_ERAY_GTUC05_Bits.DCB */
+#define IFX_ERAY_GTUC05_DCB_MSK (0xffu)
+
+/** \brief Offset for Ifx_ERAY_GTUC05_Bits.DCB */
+#define IFX_ERAY_GTUC05_DCB_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_GTUC05_Bits.DEC */
+#define IFX_ERAY_GTUC05_DEC_LEN (8u)
+
+/** \brief Mask for Ifx_ERAY_GTUC05_Bits.DEC */
+#define IFX_ERAY_GTUC05_DEC_MSK (0xffu)
+
+/** \brief Offset for Ifx_ERAY_GTUC05_Bits.DEC */
+#define IFX_ERAY_GTUC05_DEC_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_GTUC06_Bits.ASR */
+#define IFX_ERAY_GTUC06_ASR_LEN (11u)
+
+/** \brief Mask for Ifx_ERAY_GTUC06_Bits.ASR */
+#define IFX_ERAY_GTUC06_ASR_MSK (0x7ffu)
+
+/** \brief Offset for Ifx_ERAY_GTUC06_Bits.ASR */
+#define IFX_ERAY_GTUC06_ASR_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_GTUC06_Bits.MOD */
+#define IFX_ERAY_GTUC06_MOD_LEN (11u)
+
+/** \brief Mask for Ifx_ERAY_GTUC06_Bits.MOD */
+#define IFX_ERAY_GTUC06_MOD_MSK (0x7ffu)
+
+/** \brief Offset for Ifx_ERAY_GTUC06_Bits.MOD */
+#define IFX_ERAY_GTUC06_MOD_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_GTUC07_Bits.NSS */
+#define IFX_ERAY_GTUC07_NSS_LEN (10u)
+
+/** \brief Mask for Ifx_ERAY_GTUC07_Bits.NSS */
+#define IFX_ERAY_GTUC07_NSS_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_ERAY_GTUC07_Bits.NSS */
+#define IFX_ERAY_GTUC07_NSS_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_GTUC07_Bits.SSL */
+#define IFX_ERAY_GTUC07_SSL_LEN (10u)
+
+/** \brief Mask for Ifx_ERAY_GTUC07_Bits.SSL */
+#define IFX_ERAY_GTUC07_SSL_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_ERAY_GTUC07_Bits.SSL */
+#define IFX_ERAY_GTUC07_SSL_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_GTUC08_Bits.MSL */
+#define IFX_ERAY_GTUC08_MSL_LEN (6u)
+
+/** \brief Mask for Ifx_ERAY_GTUC08_Bits.MSL */
+#define IFX_ERAY_GTUC08_MSL_MSK (0x3fu)
+
+/** \brief Offset for Ifx_ERAY_GTUC08_Bits.MSL */
+#define IFX_ERAY_GTUC08_MSL_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_GTUC08_Bits.NMS */
+#define IFX_ERAY_GTUC08_NMS_LEN (13u)
+
+/** \brief Mask for Ifx_ERAY_GTUC08_Bits.NMS */
+#define IFX_ERAY_GTUC08_NMS_MSK (0x1fffu)
+
+/** \brief Offset for Ifx_ERAY_GTUC08_Bits.NMS */
+#define IFX_ERAY_GTUC08_NMS_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_GTUC09_Bits.APO */
+#define IFX_ERAY_GTUC09_APO_LEN (6u)
+
+/** \brief Mask for Ifx_ERAY_GTUC09_Bits.APO */
+#define IFX_ERAY_GTUC09_APO_MSK (0x3fu)
+
+/** \brief Offset for Ifx_ERAY_GTUC09_Bits.APO */
+#define IFX_ERAY_GTUC09_APO_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_GTUC09_Bits.DSI */
+#define IFX_ERAY_GTUC09_DSI_LEN (2u)
+
+/** \brief Mask for Ifx_ERAY_GTUC09_Bits.DSI */
+#define IFX_ERAY_GTUC09_DSI_MSK (0x3u)
+
+/** \brief Offset for Ifx_ERAY_GTUC09_Bits.DSI */
+#define IFX_ERAY_GTUC09_DSI_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_GTUC09_Bits.MAPO */
+#define IFX_ERAY_GTUC09_MAPO_LEN (5u)
+
+/** \brief Mask for Ifx_ERAY_GTUC09_Bits.MAPO */
+#define IFX_ERAY_GTUC09_MAPO_MSK (0x1fu)
+
+/** \brief Offset for Ifx_ERAY_GTUC09_Bits.MAPO */
+#define IFX_ERAY_GTUC09_MAPO_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_GTUC10_Bits.MOC */
+#define IFX_ERAY_GTUC10_MOC_LEN (14u)
+
+/** \brief Mask for Ifx_ERAY_GTUC10_Bits.MOC */
+#define IFX_ERAY_GTUC10_MOC_MSK (0x3fffu)
+
+/** \brief Offset for Ifx_ERAY_GTUC10_Bits.MOC */
+#define IFX_ERAY_GTUC10_MOC_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_GTUC10_Bits.MRC */
+#define IFX_ERAY_GTUC10_MRC_LEN (11u)
+
+/** \brief Mask for Ifx_ERAY_GTUC10_Bits.MRC */
+#define IFX_ERAY_GTUC10_MRC_MSK (0x7ffu)
+
+/** \brief Offset for Ifx_ERAY_GTUC10_Bits.MRC */
+#define IFX_ERAY_GTUC10_MRC_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_GTUC11_Bits.EOC */
+#define IFX_ERAY_GTUC11_EOC_LEN (3u)
+
+/** \brief Mask for Ifx_ERAY_GTUC11_Bits.EOC */
+#define IFX_ERAY_GTUC11_EOC_MSK (0x7u)
+
+/** \brief Offset for Ifx_ERAY_GTUC11_Bits.EOC */
+#define IFX_ERAY_GTUC11_EOC_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_GTUC11_Bits.EOCC */
+#define IFX_ERAY_GTUC11_EOCC_LEN (2u)
+
+/** \brief Mask for Ifx_ERAY_GTUC11_Bits.EOCC */
+#define IFX_ERAY_GTUC11_EOCC_MSK (0x3u)
+
+/** \brief Offset for Ifx_ERAY_GTUC11_Bits.EOCC */
+#define IFX_ERAY_GTUC11_EOCC_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_GTUC11_Bits.ERC */
+#define IFX_ERAY_GTUC11_ERC_LEN (3u)
+
+/** \brief Mask for Ifx_ERAY_GTUC11_Bits.ERC */
+#define IFX_ERAY_GTUC11_ERC_MSK (0x7u)
+
+/** \brief Offset for Ifx_ERAY_GTUC11_Bits.ERC */
+#define IFX_ERAY_GTUC11_ERC_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_GTUC11_Bits.ERCC */
+#define IFX_ERAY_GTUC11_ERCC_LEN (2u)
+
+/** \brief Mask for Ifx_ERAY_GTUC11_Bits.ERCC */
+#define IFX_ERAY_GTUC11_ERCC_MSK (0x3u)
+
+/** \brief Offset for Ifx_ERAY_GTUC11_Bits.ERCC */
+#define IFX_ERAY_GTUC11_ERCC_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_IBCM_Bits.LDSH */
+#define IFX_ERAY_IBCM_LDSH_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_IBCM_Bits.LDSH */
+#define IFX_ERAY_IBCM_LDSH_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_IBCM_Bits.LDSH */
+#define IFX_ERAY_IBCM_LDSH_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_IBCM_Bits.LDSS */
+#define IFX_ERAY_IBCM_LDSS_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_IBCM_Bits.LDSS */
+#define IFX_ERAY_IBCM_LDSS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_IBCM_Bits.LDSS */
+#define IFX_ERAY_IBCM_LDSS_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_IBCM_Bits.LHSH */
+#define IFX_ERAY_IBCM_LHSH_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_IBCM_Bits.LHSH */
+#define IFX_ERAY_IBCM_LHSH_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_IBCM_Bits.LHSH */
+#define IFX_ERAY_IBCM_LHSH_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_IBCM_Bits.LHSS */
+#define IFX_ERAY_IBCM_LHSS_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_IBCM_Bits.LHSS */
+#define IFX_ERAY_IBCM_LHSS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_IBCM_Bits.LHSS */
+#define IFX_ERAY_IBCM_LHSS_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_IBCM_Bits.STXRH */
+#define IFX_ERAY_IBCM_STXRH_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_IBCM_Bits.STXRH */
+#define IFX_ERAY_IBCM_STXRH_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_IBCM_Bits.STXRH */
+#define IFX_ERAY_IBCM_STXRH_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_IBCM_Bits.STXRS */
+#define IFX_ERAY_IBCM_STXRS_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_IBCM_Bits.STXRS */
+#define IFX_ERAY_IBCM_STXRS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_IBCM_Bits.STXRS */
+#define IFX_ERAY_IBCM_STXRS_OFF (18u)
+
+/** \brief Length for Ifx_ERAY_IBCR_Bits.IBRH */
+#define IFX_ERAY_IBCR_IBRH_LEN (7u)
+
+/** \brief Mask for Ifx_ERAY_IBCR_Bits.IBRH */
+#define IFX_ERAY_IBCR_IBRH_MSK (0x7fu)
+
+/** \brief Offset for Ifx_ERAY_IBCR_Bits.IBRH */
+#define IFX_ERAY_IBCR_IBRH_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_IBCR_Bits.IBRS */
+#define IFX_ERAY_IBCR_IBRS_LEN (7u)
+
+/** \brief Mask for Ifx_ERAY_IBCR_Bits.IBRS */
+#define IFX_ERAY_IBCR_IBRS_MSK (0x7fu)
+
+/** \brief Offset for Ifx_ERAY_IBCR_Bits.IBRS */
+#define IFX_ERAY_IBCR_IBRS_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_IBCR_Bits.IBSYH */
+#define IFX_ERAY_IBCR_IBSYH_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_IBCR_Bits.IBSYH */
+#define IFX_ERAY_IBCR_IBSYH_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_IBCR_Bits.IBSYH */
+#define IFX_ERAY_IBCR_IBSYH_OFF (15u)
+
+/** \brief Length for Ifx_ERAY_IBCR_Bits.IBSYS */
+#define IFX_ERAY_IBCR_IBSYS_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_IBCR_Bits.IBSYS */
+#define IFX_ERAY_IBCR_IBSYS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_IBCR_Bits.IBSYS */
+#define IFX_ERAY_IBCR_IBSYS_OFF (31u)
+
+/** \brief Length for Ifx_ERAY_ID_Bits.MODNUMBER */
+#define IFX_ERAY_ID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_ERAY_ID_Bits.MODNUMBER */
+#define IFX_ERAY_ID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_ERAY_ID_Bits.MODNUMBER */
+#define IFX_ERAY_ID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_ID_Bits.MODREV */
+#define IFX_ERAY_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_ERAY_ID_Bits.MODREV */
+#define IFX_ERAY_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_ERAY_ID_Bits.MODREV */
+#define IFX_ERAY_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_ID_Bits.MODTYPE */
+#define IFX_ERAY_ID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_ERAY_ID_Bits.MODTYPE */
+#define IFX_ERAY_ID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_ERAY_ID_Bits.MODTYPE */
+#define IFX_ERAY_ID_MODTYPE_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_ILE_Bits.EINT0 */
+#define IFX_ERAY_ILE_EINT0_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ILE_Bits.EINT0 */
+#define IFX_ERAY_ILE_EINT0_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ILE_Bits.EINT0 */
+#define IFX_ERAY_ILE_EINT0_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_ILE_Bits.EINT1 */
+#define IFX_ERAY_ILE_EINT1_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_ILE_Bits.EINT1 */
+#define IFX_ERAY_ILE_EINT1_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_ILE_Bits.EINT1 */
+#define IFX_ERAY_ILE_EINT1_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_KRST0_Bits.RST */
+#define IFX_ERAY_KRST0_RST_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_KRST0_Bits.RST */
+#define IFX_ERAY_KRST0_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_KRST0_Bits.RST */
+#define IFX_ERAY_KRST0_RST_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_KRST0_Bits.RSTSTAT */
+#define IFX_ERAY_KRST0_RSTSTAT_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_KRST0_Bits.RSTSTAT */
+#define IFX_ERAY_KRST0_RSTSTAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_KRST0_Bits.RSTSTAT */
+#define IFX_ERAY_KRST0_RSTSTAT_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_KRST1_Bits.RST */
+#define IFX_ERAY_KRST1_RST_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_KRST1_Bits.RST */
+#define IFX_ERAY_KRST1_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_KRST1_Bits.RST */
+#define IFX_ERAY_KRST1_RST_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_KRSTCLR_Bits.CLR */
+#define IFX_ERAY_KRSTCLR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_KRSTCLR_Bits.CLR */
+#define IFX_ERAY_KRSTCLR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_KRSTCLR_Bits.CLR */
+#define IFX_ERAY_KRSTCLR_CLR_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_LCK_Bits.CLK */
+#define IFX_ERAY_LCK_CLK_LEN (8u)
+
+/** \brief Mask for Ifx_ERAY_LCK_Bits.CLK */
+#define IFX_ERAY_LCK_CLK_MSK (0xffu)
+
+/** \brief Offset for Ifx_ERAY_LCK_Bits.CLK */
+#define IFX_ERAY_LCK_CLK_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_LCK_Bits.TMK */
+#define IFX_ERAY_LCK_TMK_LEN (8u)
+
+/** \brief Mask for Ifx_ERAY_LCK_Bits.TMK */
+#define IFX_ERAY_LCK_TMK_MSK (0xffu)
+
+/** \brief Offset for Ifx_ERAY_LCK_Bits.TMK */
+#define IFX_ERAY_LCK_TMK_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_LDTS_Bits.LDTA */
+#define IFX_ERAY_LDTS_LDTA_LEN (11u)
+
+/** \brief Mask for Ifx_ERAY_LDTS_Bits.LDTA */
+#define IFX_ERAY_LDTS_LDTA_MSK (0x7ffu)
+
+/** \brief Offset for Ifx_ERAY_LDTS_Bits.LDTA */
+#define IFX_ERAY_LDTS_LDTA_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_LDTS_Bits.LDTB */
+#define IFX_ERAY_LDTS_LDTB_LEN (11u)
+
+/** \brief Mask for Ifx_ERAY_LDTS_Bits.LDTB */
+#define IFX_ERAY_LDTS_LDTB_MSK (0x7ffu)
+
+/** \brief Offset for Ifx_ERAY_LDTS_Bits.LDTB */
+#define IFX_ERAY_LDTS_LDTB_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_MBS_Bits.CCS */
+#define IFX_ERAY_MBS_CCS_LEN (6u)
+
+/** \brief Mask for Ifx_ERAY_MBS_Bits.CCS */
+#define IFX_ERAY_MBS_CCS_MSK (0x3fu)
+
+/** \brief Offset for Ifx_ERAY_MBS_Bits.CCS */
+#define IFX_ERAY_MBS_CCS_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_MBS_Bits.CEOA */
+#define IFX_ERAY_MBS_CEOA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBS_Bits.CEOA */
+#define IFX_ERAY_MBS_CEOA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBS_Bits.CEOA */
+#define IFX_ERAY_MBS_CEOA_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_MBS_Bits.CEOB */
+#define IFX_ERAY_MBS_CEOB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBS_Bits.CEOB */
+#define IFX_ERAY_MBS_CEOB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBS_Bits.CEOB */
+#define IFX_ERAY_MBS_CEOB_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_MBS_Bits.ESA */
+#define IFX_ERAY_MBS_ESA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBS_Bits.ESA */
+#define IFX_ERAY_MBS_ESA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBS_Bits.ESA */
+#define IFX_ERAY_MBS_ESA_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_MBS_Bits.ESB */
+#define IFX_ERAY_MBS_ESB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBS_Bits.ESB */
+#define IFX_ERAY_MBS_ESB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBS_Bits.ESB */
+#define IFX_ERAY_MBS_ESB_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_MBS_Bits.FTA */
+#define IFX_ERAY_MBS_FTA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBS_Bits.FTA */
+#define IFX_ERAY_MBS_FTA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBS_Bits.FTA */
+#define IFX_ERAY_MBS_FTA_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_MBS_Bits.FTB */
+#define IFX_ERAY_MBS_FTB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBS_Bits.FTB */
+#define IFX_ERAY_MBS_FTB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBS_Bits.FTB */
+#define IFX_ERAY_MBS_FTB_OFF (15u)
+
+/** \brief Length for Ifx_ERAY_MBS_Bits.MLST */
+#define IFX_ERAY_MBS_MLST_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBS_Bits.MLST */
+#define IFX_ERAY_MBS_MLST_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBS_Bits.MLST */
+#define IFX_ERAY_MBS_MLST_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_MBS_Bits.NFIS */
+#define IFX_ERAY_MBS_NFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBS_Bits.NFIS */
+#define IFX_ERAY_MBS_NFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBS_Bits.NFIS */
+#define IFX_ERAY_MBS_NFIS_OFF (27u)
+
+/** \brief Length for Ifx_ERAY_MBS_Bits.PPIS */
+#define IFX_ERAY_MBS_PPIS_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBS_Bits.PPIS */
+#define IFX_ERAY_MBS_PPIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBS_Bits.PPIS */
+#define IFX_ERAY_MBS_PPIS_OFF (28u)
+
+/** \brief Length for Ifx_ERAY_MBS_Bits.RCIS */
+#define IFX_ERAY_MBS_RCIS_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBS_Bits.RCIS */
+#define IFX_ERAY_MBS_RCIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBS_Bits.RCIS */
+#define IFX_ERAY_MBS_RCIS_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_MBS_Bits.RESS */
+#define IFX_ERAY_MBS_RESS_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBS_Bits.RESS */
+#define IFX_ERAY_MBS_RESS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBS_Bits.RESS */
+#define IFX_ERAY_MBS_RESS_OFF (29u)
+
+/** \brief Length for Ifx_ERAY_MBS_Bits.SEOA */
+#define IFX_ERAY_MBS_SEOA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBS_Bits.SEOA */
+#define IFX_ERAY_MBS_SEOA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBS_Bits.SEOA */
+#define IFX_ERAY_MBS_SEOA_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_MBS_Bits.SEOB */
+#define IFX_ERAY_MBS_SEOB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBS_Bits.SEOB */
+#define IFX_ERAY_MBS_SEOB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBS_Bits.SEOB */
+#define IFX_ERAY_MBS_SEOB_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_MBS_Bits.SFIS */
+#define IFX_ERAY_MBS_SFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBS_Bits.SFIS */
+#define IFX_ERAY_MBS_SFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBS_Bits.SFIS */
+#define IFX_ERAY_MBS_SFIS_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_MBS_Bits.SVOA */
+#define IFX_ERAY_MBS_SVOA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBS_Bits.SVOA */
+#define IFX_ERAY_MBS_SVOA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBS_Bits.SVOA */
+#define IFX_ERAY_MBS_SVOA_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_MBS_Bits.SVOB */
+#define IFX_ERAY_MBS_SVOB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBS_Bits.SVOB */
+#define IFX_ERAY_MBS_SVOB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBS_Bits.SVOB */
+#define IFX_ERAY_MBS_SVOB_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_MBS_Bits.SYNS */
+#define IFX_ERAY_MBS_SYNS_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBS_Bits.SYNS */
+#define IFX_ERAY_MBS_SYNS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBS_Bits.SYNS */
+#define IFX_ERAY_MBS_SYNS_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_MBS_Bits.TCIA */
+#define IFX_ERAY_MBS_TCIA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBS_Bits.TCIA */
+#define IFX_ERAY_MBS_TCIA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBS_Bits.TCIA */
+#define IFX_ERAY_MBS_TCIA_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_MBS_Bits.TCIB */
+#define IFX_ERAY_MBS_TCIB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBS_Bits.TCIB */
+#define IFX_ERAY_MBS_TCIB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBS_Bits.TCIB */
+#define IFX_ERAY_MBS_TCIB_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_MBS_Bits.VFRA */
+#define IFX_ERAY_MBS_VFRA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBS_Bits.VFRA */
+#define IFX_ERAY_MBS_VFRA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBS_Bits.VFRA */
+#define IFX_ERAY_MBS_VFRA_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_MBS_Bits.VFRB */
+#define IFX_ERAY_MBS_VFRB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBS_Bits.VFRB */
+#define IFX_ERAY_MBS_VFRB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBS_Bits.VFRB */
+#define IFX_ERAY_MBS_VFRB_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC0 */
+#define IFX_ERAY_MBSC1_MBC0_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC0 */
+#define IFX_ERAY_MBSC1_MBC0_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC0 */
+#define IFX_ERAY_MBSC1_MBC0_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC10 */
+#define IFX_ERAY_MBSC1_MBC10_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC10 */
+#define IFX_ERAY_MBSC1_MBC10_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC10 */
+#define IFX_ERAY_MBSC1_MBC10_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC11 */
+#define IFX_ERAY_MBSC1_MBC11_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC11 */
+#define IFX_ERAY_MBSC1_MBC11_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC11 */
+#define IFX_ERAY_MBSC1_MBC11_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC12 */
+#define IFX_ERAY_MBSC1_MBC12_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC12 */
+#define IFX_ERAY_MBSC1_MBC12_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC12 */
+#define IFX_ERAY_MBSC1_MBC12_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC13 */
+#define IFX_ERAY_MBSC1_MBC13_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC13 */
+#define IFX_ERAY_MBSC1_MBC13_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC13 */
+#define IFX_ERAY_MBSC1_MBC13_OFF (13u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC14 */
+#define IFX_ERAY_MBSC1_MBC14_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC14 */
+#define IFX_ERAY_MBSC1_MBC14_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC14 */
+#define IFX_ERAY_MBSC1_MBC14_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC15 */
+#define IFX_ERAY_MBSC1_MBC15_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC15 */
+#define IFX_ERAY_MBSC1_MBC15_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC15 */
+#define IFX_ERAY_MBSC1_MBC15_OFF (15u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC16 */
+#define IFX_ERAY_MBSC1_MBC16_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC16 */
+#define IFX_ERAY_MBSC1_MBC16_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC16 */
+#define IFX_ERAY_MBSC1_MBC16_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC17 */
+#define IFX_ERAY_MBSC1_MBC17_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC17 */
+#define IFX_ERAY_MBSC1_MBC17_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC17 */
+#define IFX_ERAY_MBSC1_MBC17_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC18 */
+#define IFX_ERAY_MBSC1_MBC18_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC18 */
+#define IFX_ERAY_MBSC1_MBC18_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC18 */
+#define IFX_ERAY_MBSC1_MBC18_OFF (18u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC19 */
+#define IFX_ERAY_MBSC1_MBC19_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC19 */
+#define IFX_ERAY_MBSC1_MBC19_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC19 */
+#define IFX_ERAY_MBSC1_MBC19_OFF (19u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC1 */
+#define IFX_ERAY_MBSC1_MBC1_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC1 */
+#define IFX_ERAY_MBSC1_MBC1_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC1 */
+#define IFX_ERAY_MBSC1_MBC1_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC20 */
+#define IFX_ERAY_MBSC1_MBC20_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC20 */
+#define IFX_ERAY_MBSC1_MBC20_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC20 */
+#define IFX_ERAY_MBSC1_MBC20_OFF (20u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC21 */
+#define IFX_ERAY_MBSC1_MBC21_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC21 */
+#define IFX_ERAY_MBSC1_MBC21_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC21 */
+#define IFX_ERAY_MBSC1_MBC21_OFF (21u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC22 */
+#define IFX_ERAY_MBSC1_MBC22_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC22 */
+#define IFX_ERAY_MBSC1_MBC22_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC22 */
+#define IFX_ERAY_MBSC1_MBC22_OFF (22u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC23 */
+#define IFX_ERAY_MBSC1_MBC23_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC23 */
+#define IFX_ERAY_MBSC1_MBC23_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC23 */
+#define IFX_ERAY_MBSC1_MBC23_OFF (23u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC24 */
+#define IFX_ERAY_MBSC1_MBC24_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC24 */
+#define IFX_ERAY_MBSC1_MBC24_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC24 */
+#define IFX_ERAY_MBSC1_MBC24_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC25 */
+#define IFX_ERAY_MBSC1_MBC25_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC25 */
+#define IFX_ERAY_MBSC1_MBC25_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC25 */
+#define IFX_ERAY_MBSC1_MBC25_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC26 */
+#define IFX_ERAY_MBSC1_MBC26_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC26 */
+#define IFX_ERAY_MBSC1_MBC26_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC26 */
+#define IFX_ERAY_MBSC1_MBC26_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC27 */
+#define IFX_ERAY_MBSC1_MBC27_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC27 */
+#define IFX_ERAY_MBSC1_MBC27_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC27 */
+#define IFX_ERAY_MBSC1_MBC27_OFF (27u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC28 */
+#define IFX_ERAY_MBSC1_MBC28_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC28 */
+#define IFX_ERAY_MBSC1_MBC28_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC28 */
+#define IFX_ERAY_MBSC1_MBC28_OFF (28u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC29 */
+#define IFX_ERAY_MBSC1_MBC29_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC29 */
+#define IFX_ERAY_MBSC1_MBC29_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC29 */
+#define IFX_ERAY_MBSC1_MBC29_OFF (29u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC2 */
+#define IFX_ERAY_MBSC1_MBC2_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC2 */
+#define IFX_ERAY_MBSC1_MBC2_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC2 */
+#define IFX_ERAY_MBSC1_MBC2_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC30 */
+#define IFX_ERAY_MBSC1_MBC30_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC30 */
+#define IFX_ERAY_MBSC1_MBC30_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC30 */
+#define IFX_ERAY_MBSC1_MBC30_OFF (30u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC31 */
+#define IFX_ERAY_MBSC1_MBC31_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC31 */
+#define IFX_ERAY_MBSC1_MBC31_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC31 */
+#define IFX_ERAY_MBSC1_MBC31_OFF (31u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC3 */
+#define IFX_ERAY_MBSC1_MBC3_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC3 */
+#define IFX_ERAY_MBSC1_MBC3_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC3 */
+#define IFX_ERAY_MBSC1_MBC3_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC4 */
+#define IFX_ERAY_MBSC1_MBC4_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC4 */
+#define IFX_ERAY_MBSC1_MBC4_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC4 */
+#define IFX_ERAY_MBSC1_MBC4_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC5 */
+#define IFX_ERAY_MBSC1_MBC5_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC5 */
+#define IFX_ERAY_MBSC1_MBC5_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC5 */
+#define IFX_ERAY_MBSC1_MBC5_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC6 */
+#define IFX_ERAY_MBSC1_MBC6_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC6 */
+#define IFX_ERAY_MBSC1_MBC6_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC6 */
+#define IFX_ERAY_MBSC1_MBC6_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC7 */
+#define IFX_ERAY_MBSC1_MBC7_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC7 */
+#define IFX_ERAY_MBSC1_MBC7_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC7 */
+#define IFX_ERAY_MBSC1_MBC7_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC8 */
+#define IFX_ERAY_MBSC1_MBC8_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC8 */
+#define IFX_ERAY_MBSC1_MBC8_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC8 */
+#define IFX_ERAY_MBSC1_MBC8_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_MBSC1_Bits.MBC9 */
+#define IFX_ERAY_MBSC1_MBC9_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC1_Bits.MBC9 */
+#define IFX_ERAY_MBSC1_MBC9_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC1_Bits.MBC9 */
+#define IFX_ERAY_MBSC1_MBC9_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC32 */
+#define IFX_ERAY_MBSC2_MBC32_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC32 */
+#define IFX_ERAY_MBSC2_MBC32_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC32 */
+#define IFX_ERAY_MBSC2_MBC32_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC33 */
+#define IFX_ERAY_MBSC2_MBC33_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC33 */
+#define IFX_ERAY_MBSC2_MBC33_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC33 */
+#define IFX_ERAY_MBSC2_MBC33_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC34 */
+#define IFX_ERAY_MBSC2_MBC34_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC34 */
+#define IFX_ERAY_MBSC2_MBC34_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC34 */
+#define IFX_ERAY_MBSC2_MBC34_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC35 */
+#define IFX_ERAY_MBSC2_MBC35_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC35 */
+#define IFX_ERAY_MBSC2_MBC35_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC35 */
+#define IFX_ERAY_MBSC2_MBC35_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC36 */
+#define IFX_ERAY_MBSC2_MBC36_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC36 */
+#define IFX_ERAY_MBSC2_MBC36_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC36 */
+#define IFX_ERAY_MBSC2_MBC36_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC37 */
+#define IFX_ERAY_MBSC2_MBC37_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC37 */
+#define IFX_ERAY_MBSC2_MBC37_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC37 */
+#define IFX_ERAY_MBSC2_MBC37_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC38 */
+#define IFX_ERAY_MBSC2_MBC38_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC38 */
+#define IFX_ERAY_MBSC2_MBC38_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC38 */
+#define IFX_ERAY_MBSC2_MBC38_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC39 */
+#define IFX_ERAY_MBSC2_MBC39_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC39 */
+#define IFX_ERAY_MBSC2_MBC39_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC39 */
+#define IFX_ERAY_MBSC2_MBC39_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC40 */
+#define IFX_ERAY_MBSC2_MBC40_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC40 */
+#define IFX_ERAY_MBSC2_MBC40_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC40 */
+#define IFX_ERAY_MBSC2_MBC40_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC41 */
+#define IFX_ERAY_MBSC2_MBC41_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC41 */
+#define IFX_ERAY_MBSC2_MBC41_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC41 */
+#define IFX_ERAY_MBSC2_MBC41_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC42 */
+#define IFX_ERAY_MBSC2_MBC42_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC42 */
+#define IFX_ERAY_MBSC2_MBC42_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC42 */
+#define IFX_ERAY_MBSC2_MBC42_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC43 */
+#define IFX_ERAY_MBSC2_MBC43_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC43 */
+#define IFX_ERAY_MBSC2_MBC43_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC43 */
+#define IFX_ERAY_MBSC2_MBC43_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC44 */
+#define IFX_ERAY_MBSC2_MBC44_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC44 */
+#define IFX_ERAY_MBSC2_MBC44_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC44 */
+#define IFX_ERAY_MBSC2_MBC44_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC45 */
+#define IFX_ERAY_MBSC2_MBC45_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC45 */
+#define IFX_ERAY_MBSC2_MBC45_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC45 */
+#define IFX_ERAY_MBSC2_MBC45_OFF (13u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC46 */
+#define IFX_ERAY_MBSC2_MBC46_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC46 */
+#define IFX_ERAY_MBSC2_MBC46_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC46 */
+#define IFX_ERAY_MBSC2_MBC46_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC47 */
+#define IFX_ERAY_MBSC2_MBC47_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC47 */
+#define IFX_ERAY_MBSC2_MBC47_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC47 */
+#define IFX_ERAY_MBSC2_MBC47_OFF (15u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC48 */
+#define IFX_ERAY_MBSC2_MBC48_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC48 */
+#define IFX_ERAY_MBSC2_MBC48_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC48 */
+#define IFX_ERAY_MBSC2_MBC48_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC49 */
+#define IFX_ERAY_MBSC2_MBC49_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC49 */
+#define IFX_ERAY_MBSC2_MBC49_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC49 */
+#define IFX_ERAY_MBSC2_MBC49_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC50 */
+#define IFX_ERAY_MBSC2_MBC50_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC50 */
+#define IFX_ERAY_MBSC2_MBC50_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC50 */
+#define IFX_ERAY_MBSC2_MBC50_OFF (18u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC51 */
+#define IFX_ERAY_MBSC2_MBC51_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC51 */
+#define IFX_ERAY_MBSC2_MBC51_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC51 */
+#define IFX_ERAY_MBSC2_MBC51_OFF (19u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC52 */
+#define IFX_ERAY_MBSC2_MBC52_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC52 */
+#define IFX_ERAY_MBSC2_MBC52_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC52 */
+#define IFX_ERAY_MBSC2_MBC52_OFF (20u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC53 */
+#define IFX_ERAY_MBSC2_MBC53_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC53 */
+#define IFX_ERAY_MBSC2_MBC53_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC53 */
+#define IFX_ERAY_MBSC2_MBC53_OFF (21u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC54 */
+#define IFX_ERAY_MBSC2_MBC54_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC54 */
+#define IFX_ERAY_MBSC2_MBC54_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC54 */
+#define IFX_ERAY_MBSC2_MBC54_OFF (22u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC55 */
+#define IFX_ERAY_MBSC2_MBC55_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC55 */
+#define IFX_ERAY_MBSC2_MBC55_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC55 */
+#define IFX_ERAY_MBSC2_MBC55_OFF (23u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC56 */
+#define IFX_ERAY_MBSC2_MBC56_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC56 */
+#define IFX_ERAY_MBSC2_MBC56_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC56 */
+#define IFX_ERAY_MBSC2_MBC56_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC57 */
+#define IFX_ERAY_MBSC2_MBC57_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC57 */
+#define IFX_ERAY_MBSC2_MBC57_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC57 */
+#define IFX_ERAY_MBSC2_MBC57_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC58 */
+#define IFX_ERAY_MBSC2_MBC58_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC58 */
+#define IFX_ERAY_MBSC2_MBC58_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC58 */
+#define IFX_ERAY_MBSC2_MBC58_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC59 */
+#define IFX_ERAY_MBSC2_MBC59_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC59 */
+#define IFX_ERAY_MBSC2_MBC59_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC59 */
+#define IFX_ERAY_MBSC2_MBC59_OFF (27u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC60 */
+#define IFX_ERAY_MBSC2_MBC60_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC60 */
+#define IFX_ERAY_MBSC2_MBC60_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC60 */
+#define IFX_ERAY_MBSC2_MBC60_OFF (28u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC61 */
+#define IFX_ERAY_MBSC2_MBC61_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC61 */
+#define IFX_ERAY_MBSC2_MBC61_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC61 */
+#define IFX_ERAY_MBSC2_MBC61_OFF (29u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC62 */
+#define IFX_ERAY_MBSC2_MBC62_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC62 */
+#define IFX_ERAY_MBSC2_MBC62_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC62 */
+#define IFX_ERAY_MBSC2_MBC62_OFF (30u)
+
+/** \brief Length for Ifx_ERAY_MBSC2_Bits.MBC63 */
+#define IFX_ERAY_MBSC2_MBC63_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC2_Bits.MBC63 */
+#define IFX_ERAY_MBSC2_MBC63_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC2_Bits.MBC63 */
+#define IFX_ERAY_MBSC2_MBC63_OFF (31u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC64 */
+#define IFX_ERAY_MBSC3_MBC64_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC64 */
+#define IFX_ERAY_MBSC3_MBC64_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC64 */
+#define IFX_ERAY_MBSC3_MBC64_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC65 */
+#define IFX_ERAY_MBSC3_MBC65_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC65 */
+#define IFX_ERAY_MBSC3_MBC65_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC65 */
+#define IFX_ERAY_MBSC3_MBC65_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC66 */
+#define IFX_ERAY_MBSC3_MBC66_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC66 */
+#define IFX_ERAY_MBSC3_MBC66_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC66 */
+#define IFX_ERAY_MBSC3_MBC66_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC67 */
+#define IFX_ERAY_MBSC3_MBC67_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC67 */
+#define IFX_ERAY_MBSC3_MBC67_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC67 */
+#define IFX_ERAY_MBSC3_MBC67_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC68 */
+#define IFX_ERAY_MBSC3_MBC68_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC68 */
+#define IFX_ERAY_MBSC3_MBC68_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC68 */
+#define IFX_ERAY_MBSC3_MBC68_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC69 */
+#define IFX_ERAY_MBSC3_MBC69_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC69 */
+#define IFX_ERAY_MBSC3_MBC69_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC69 */
+#define IFX_ERAY_MBSC3_MBC69_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC70 */
+#define IFX_ERAY_MBSC3_MBC70_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC70 */
+#define IFX_ERAY_MBSC3_MBC70_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC70 */
+#define IFX_ERAY_MBSC3_MBC70_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC71 */
+#define IFX_ERAY_MBSC3_MBC71_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC71 */
+#define IFX_ERAY_MBSC3_MBC71_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC71 */
+#define IFX_ERAY_MBSC3_MBC71_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC72 */
+#define IFX_ERAY_MBSC3_MBC72_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC72 */
+#define IFX_ERAY_MBSC3_MBC72_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC72 */
+#define IFX_ERAY_MBSC3_MBC72_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC73 */
+#define IFX_ERAY_MBSC3_MBC73_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC73 */
+#define IFX_ERAY_MBSC3_MBC73_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC73 */
+#define IFX_ERAY_MBSC3_MBC73_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC74 */
+#define IFX_ERAY_MBSC3_MBC74_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC74 */
+#define IFX_ERAY_MBSC3_MBC74_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC74 */
+#define IFX_ERAY_MBSC3_MBC74_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC75 */
+#define IFX_ERAY_MBSC3_MBC75_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC75 */
+#define IFX_ERAY_MBSC3_MBC75_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC75 */
+#define IFX_ERAY_MBSC3_MBC75_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC76 */
+#define IFX_ERAY_MBSC3_MBC76_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC76 */
+#define IFX_ERAY_MBSC3_MBC76_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC76 */
+#define IFX_ERAY_MBSC3_MBC76_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC77 */
+#define IFX_ERAY_MBSC3_MBC77_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC77 */
+#define IFX_ERAY_MBSC3_MBC77_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC77 */
+#define IFX_ERAY_MBSC3_MBC77_OFF (13u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC78 */
+#define IFX_ERAY_MBSC3_MBC78_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC78 */
+#define IFX_ERAY_MBSC3_MBC78_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC78 */
+#define IFX_ERAY_MBSC3_MBC78_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC79 */
+#define IFX_ERAY_MBSC3_MBC79_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC79 */
+#define IFX_ERAY_MBSC3_MBC79_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC79 */
+#define IFX_ERAY_MBSC3_MBC79_OFF (15u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC80 */
+#define IFX_ERAY_MBSC3_MBC80_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC80 */
+#define IFX_ERAY_MBSC3_MBC80_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC80 */
+#define IFX_ERAY_MBSC3_MBC80_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC81 */
+#define IFX_ERAY_MBSC3_MBC81_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC81 */
+#define IFX_ERAY_MBSC3_MBC81_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC81 */
+#define IFX_ERAY_MBSC3_MBC81_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC82 */
+#define IFX_ERAY_MBSC3_MBC82_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC82 */
+#define IFX_ERAY_MBSC3_MBC82_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC82 */
+#define IFX_ERAY_MBSC3_MBC82_OFF (18u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC83 */
+#define IFX_ERAY_MBSC3_MBC83_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC83 */
+#define IFX_ERAY_MBSC3_MBC83_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC83 */
+#define IFX_ERAY_MBSC3_MBC83_OFF (19u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC84 */
+#define IFX_ERAY_MBSC3_MBC84_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC84 */
+#define IFX_ERAY_MBSC3_MBC84_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC84 */
+#define IFX_ERAY_MBSC3_MBC84_OFF (20u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC85 */
+#define IFX_ERAY_MBSC3_MBC85_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC85 */
+#define IFX_ERAY_MBSC3_MBC85_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC85 */
+#define IFX_ERAY_MBSC3_MBC85_OFF (21u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC86 */
+#define IFX_ERAY_MBSC3_MBC86_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC86 */
+#define IFX_ERAY_MBSC3_MBC86_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC86 */
+#define IFX_ERAY_MBSC3_MBC86_OFF (22u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC87 */
+#define IFX_ERAY_MBSC3_MBC87_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC87 */
+#define IFX_ERAY_MBSC3_MBC87_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC87 */
+#define IFX_ERAY_MBSC3_MBC87_OFF (23u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC88 */
+#define IFX_ERAY_MBSC3_MBC88_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC88 */
+#define IFX_ERAY_MBSC3_MBC88_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC88 */
+#define IFX_ERAY_MBSC3_MBC88_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC89 */
+#define IFX_ERAY_MBSC3_MBC89_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC89 */
+#define IFX_ERAY_MBSC3_MBC89_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC89 */
+#define IFX_ERAY_MBSC3_MBC89_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC90 */
+#define IFX_ERAY_MBSC3_MBC90_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC90 */
+#define IFX_ERAY_MBSC3_MBC90_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC90 */
+#define IFX_ERAY_MBSC3_MBC90_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC91 */
+#define IFX_ERAY_MBSC3_MBC91_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC91 */
+#define IFX_ERAY_MBSC3_MBC91_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC91 */
+#define IFX_ERAY_MBSC3_MBC91_OFF (27u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC92 */
+#define IFX_ERAY_MBSC3_MBC92_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC92 */
+#define IFX_ERAY_MBSC3_MBC92_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC92 */
+#define IFX_ERAY_MBSC3_MBC92_OFF (28u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC93 */
+#define IFX_ERAY_MBSC3_MBC93_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC93 */
+#define IFX_ERAY_MBSC3_MBC93_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC93 */
+#define IFX_ERAY_MBSC3_MBC93_OFF (29u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC94 */
+#define IFX_ERAY_MBSC3_MBC94_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC94 */
+#define IFX_ERAY_MBSC3_MBC94_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC94 */
+#define IFX_ERAY_MBSC3_MBC94_OFF (30u)
+
+/** \brief Length for Ifx_ERAY_MBSC3_Bits.MBC95 */
+#define IFX_ERAY_MBSC3_MBC95_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC3_Bits.MBC95 */
+#define IFX_ERAY_MBSC3_MBC95_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC3_Bits.MBC95 */
+#define IFX_ERAY_MBSC3_MBC95_OFF (31u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC100 */
+#define IFX_ERAY_MBSC4_MBC100_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC100 */
+#define IFX_ERAY_MBSC4_MBC100_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC100 */
+#define IFX_ERAY_MBSC4_MBC100_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC101 */
+#define IFX_ERAY_MBSC4_MBC101_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC101 */
+#define IFX_ERAY_MBSC4_MBC101_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC101 */
+#define IFX_ERAY_MBSC4_MBC101_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC102 */
+#define IFX_ERAY_MBSC4_MBC102_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC102 */
+#define IFX_ERAY_MBSC4_MBC102_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC102 */
+#define IFX_ERAY_MBSC4_MBC102_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC103 */
+#define IFX_ERAY_MBSC4_MBC103_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC103 */
+#define IFX_ERAY_MBSC4_MBC103_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC103 */
+#define IFX_ERAY_MBSC4_MBC103_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC104 */
+#define IFX_ERAY_MBSC4_MBC104_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC104 */
+#define IFX_ERAY_MBSC4_MBC104_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC104 */
+#define IFX_ERAY_MBSC4_MBC104_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC105 */
+#define IFX_ERAY_MBSC4_MBC105_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC105 */
+#define IFX_ERAY_MBSC4_MBC105_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC105 */
+#define IFX_ERAY_MBSC4_MBC105_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC106 */
+#define IFX_ERAY_MBSC4_MBC106_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC106 */
+#define IFX_ERAY_MBSC4_MBC106_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC106 */
+#define IFX_ERAY_MBSC4_MBC106_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC107 */
+#define IFX_ERAY_MBSC4_MBC107_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC107 */
+#define IFX_ERAY_MBSC4_MBC107_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC107 */
+#define IFX_ERAY_MBSC4_MBC107_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC108 */
+#define IFX_ERAY_MBSC4_MBC108_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC108 */
+#define IFX_ERAY_MBSC4_MBC108_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC108 */
+#define IFX_ERAY_MBSC4_MBC108_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC109 */
+#define IFX_ERAY_MBSC4_MBC109_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC109 */
+#define IFX_ERAY_MBSC4_MBC109_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC109 */
+#define IFX_ERAY_MBSC4_MBC109_OFF (13u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC110 */
+#define IFX_ERAY_MBSC4_MBC110_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC110 */
+#define IFX_ERAY_MBSC4_MBC110_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC110 */
+#define IFX_ERAY_MBSC4_MBC110_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC111 */
+#define IFX_ERAY_MBSC4_MBC111_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC111 */
+#define IFX_ERAY_MBSC4_MBC111_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC111 */
+#define IFX_ERAY_MBSC4_MBC111_OFF (15u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC112 */
+#define IFX_ERAY_MBSC4_MBC112_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC112 */
+#define IFX_ERAY_MBSC4_MBC112_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC112 */
+#define IFX_ERAY_MBSC4_MBC112_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC113 */
+#define IFX_ERAY_MBSC4_MBC113_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC113 */
+#define IFX_ERAY_MBSC4_MBC113_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC113 */
+#define IFX_ERAY_MBSC4_MBC113_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC114 */
+#define IFX_ERAY_MBSC4_MBC114_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC114 */
+#define IFX_ERAY_MBSC4_MBC114_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC114 */
+#define IFX_ERAY_MBSC4_MBC114_OFF (18u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC115 */
+#define IFX_ERAY_MBSC4_MBC115_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC115 */
+#define IFX_ERAY_MBSC4_MBC115_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC115 */
+#define IFX_ERAY_MBSC4_MBC115_OFF (19u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC116 */
+#define IFX_ERAY_MBSC4_MBC116_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC116 */
+#define IFX_ERAY_MBSC4_MBC116_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC116 */
+#define IFX_ERAY_MBSC4_MBC116_OFF (20u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC117 */
+#define IFX_ERAY_MBSC4_MBC117_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC117 */
+#define IFX_ERAY_MBSC4_MBC117_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC117 */
+#define IFX_ERAY_MBSC4_MBC117_OFF (21u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC118 */
+#define IFX_ERAY_MBSC4_MBC118_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC118 */
+#define IFX_ERAY_MBSC4_MBC118_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC118 */
+#define IFX_ERAY_MBSC4_MBC118_OFF (22u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC119 */
+#define IFX_ERAY_MBSC4_MBC119_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC119 */
+#define IFX_ERAY_MBSC4_MBC119_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC119 */
+#define IFX_ERAY_MBSC4_MBC119_OFF (23u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC120 */
+#define IFX_ERAY_MBSC4_MBC120_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC120 */
+#define IFX_ERAY_MBSC4_MBC120_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC120 */
+#define IFX_ERAY_MBSC4_MBC120_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC121 */
+#define IFX_ERAY_MBSC4_MBC121_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC121 */
+#define IFX_ERAY_MBSC4_MBC121_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC121 */
+#define IFX_ERAY_MBSC4_MBC121_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC122 */
+#define IFX_ERAY_MBSC4_MBC122_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC122 */
+#define IFX_ERAY_MBSC4_MBC122_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC122 */
+#define IFX_ERAY_MBSC4_MBC122_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC123 */
+#define IFX_ERAY_MBSC4_MBC123_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC123 */
+#define IFX_ERAY_MBSC4_MBC123_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC123 */
+#define IFX_ERAY_MBSC4_MBC123_OFF (27u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC124 */
+#define IFX_ERAY_MBSC4_MBC124_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC124 */
+#define IFX_ERAY_MBSC4_MBC124_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC124 */
+#define IFX_ERAY_MBSC4_MBC124_OFF (28u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC125 */
+#define IFX_ERAY_MBSC4_MBC125_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC125 */
+#define IFX_ERAY_MBSC4_MBC125_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC125 */
+#define IFX_ERAY_MBSC4_MBC125_OFF (29u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC126 */
+#define IFX_ERAY_MBSC4_MBC126_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC126 */
+#define IFX_ERAY_MBSC4_MBC126_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC126 */
+#define IFX_ERAY_MBSC4_MBC126_OFF (30u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC127 */
+#define IFX_ERAY_MBSC4_MBC127_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC127 */
+#define IFX_ERAY_MBSC4_MBC127_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC127 */
+#define IFX_ERAY_MBSC4_MBC127_OFF (31u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC96 */
+#define IFX_ERAY_MBSC4_MBC96_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC96 */
+#define IFX_ERAY_MBSC4_MBC96_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC96 */
+#define IFX_ERAY_MBSC4_MBC96_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC97 */
+#define IFX_ERAY_MBSC4_MBC97_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC97 */
+#define IFX_ERAY_MBSC4_MBC97_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC97 */
+#define IFX_ERAY_MBSC4_MBC97_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC98 */
+#define IFX_ERAY_MBSC4_MBC98_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC98 */
+#define IFX_ERAY_MBSC4_MBC98_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC98 */
+#define IFX_ERAY_MBSC4_MBC98_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_MBSC4_Bits.MBC99 */
+#define IFX_ERAY_MBSC4_MBC99_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MBSC4_Bits.MBC99 */
+#define IFX_ERAY_MBSC4_MBC99_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MBSC4_Bits.MBC99 */
+#define IFX_ERAY_MBSC4_MBC99_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_MHDC_Bits.SFDL */
+#define IFX_ERAY_MHDC_SFDL_LEN (7u)
+
+/** \brief Mask for Ifx_ERAY_MHDC_Bits.SFDL */
+#define IFX_ERAY_MHDC_SFDL_MSK (0x7fu)
+
+/** \brief Offset for Ifx_ERAY_MHDC_Bits.SFDL */
+#define IFX_ERAY_MHDC_SFDL_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_MHDC_Bits.SLT */
+#define IFX_ERAY_MHDC_SLT_LEN (13u)
+
+/** \brief Mask for Ifx_ERAY_MHDC_Bits.SLT */
+#define IFX_ERAY_MHDC_SLT_MSK (0x1fffu)
+
+/** \brief Offset for Ifx_ERAY_MHDC_Bits.SLT */
+#define IFX_ERAY_MHDC_SLT_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_MHDF_Bits.FNFA */
+#define IFX_ERAY_MHDF_FNFA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MHDF_Bits.FNFA */
+#define IFX_ERAY_MHDF_FNFA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MHDF_Bits.FNFA */
+#define IFX_ERAY_MHDF_FNFA_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_MHDF_Bits.FNFB */
+#define IFX_ERAY_MHDF_FNFB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MHDF_Bits.FNFB */
+#define IFX_ERAY_MHDF_FNFB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MHDF_Bits.FNFB */
+#define IFX_ERAY_MHDF_FNFB_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_MHDF_Bits.SNUA */
+#define IFX_ERAY_MHDF_SNUA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MHDF_Bits.SNUA */
+#define IFX_ERAY_MHDF_SNUA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MHDF_Bits.SNUA */
+#define IFX_ERAY_MHDF_SNUA_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_MHDF_Bits.SNUB */
+#define IFX_ERAY_MHDF_SNUB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MHDF_Bits.SNUB */
+#define IFX_ERAY_MHDF_SNUB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MHDF_Bits.SNUB */
+#define IFX_ERAY_MHDF_SNUB_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_MHDF_Bits.TBFA */
+#define IFX_ERAY_MHDF_TBFA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MHDF_Bits.TBFA */
+#define IFX_ERAY_MHDF_TBFA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MHDF_Bits.TBFA */
+#define IFX_ERAY_MHDF_TBFA_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_MHDF_Bits.TBFB */
+#define IFX_ERAY_MHDF_TBFB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MHDF_Bits.TBFB */
+#define IFX_ERAY_MHDF_TBFB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MHDF_Bits.TBFB */
+#define IFX_ERAY_MHDF_TBFB_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_MHDF_Bits.TNSA */
+#define IFX_ERAY_MHDF_TNSA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MHDF_Bits.TNSA */
+#define IFX_ERAY_MHDF_TNSA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MHDF_Bits.TNSA */
+#define IFX_ERAY_MHDF_TNSA_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_MHDF_Bits.TNSB */
+#define IFX_ERAY_MHDF_TNSB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MHDF_Bits.TNSB */
+#define IFX_ERAY_MHDF_TNSB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MHDF_Bits.TNSB */
+#define IFX_ERAY_MHDF_TNSB_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_MHDF_Bits.WAHP */
+#define IFX_ERAY_MHDF_WAHP_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MHDF_Bits.WAHP */
+#define IFX_ERAY_MHDF_WAHP_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MHDF_Bits.WAHP */
+#define IFX_ERAY_MHDF_WAHP_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_MHDS_Bits.CRAM */
+#define IFX_ERAY_MHDS_CRAM_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MHDS_Bits.CRAM */
+#define IFX_ERAY_MHDS_CRAM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MHDS_Bits.CRAM */
+#define IFX_ERAY_MHDS_CRAM_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_MHDS_Bits.EIBF */
+#define IFX_ERAY_MHDS_EIBF_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MHDS_Bits.EIBF */
+#define IFX_ERAY_MHDS_EIBF_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MHDS_Bits.EIBF */
+#define IFX_ERAY_MHDS_EIBF_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_MHDS_Bits.EMR */
+#define IFX_ERAY_MHDS_EMR_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MHDS_Bits.EMR */
+#define IFX_ERAY_MHDS_EMR_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MHDS_Bits.EMR */
+#define IFX_ERAY_MHDS_EMR_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_MHDS_Bits.EOBF */
+#define IFX_ERAY_MHDS_EOBF_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MHDS_Bits.EOBF */
+#define IFX_ERAY_MHDS_EOBF_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MHDS_Bits.EOBF */
+#define IFX_ERAY_MHDS_EOBF_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_MHDS_Bits.ETBF1 */
+#define IFX_ERAY_MHDS_ETBF1_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MHDS_Bits.ETBF1 */
+#define IFX_ERAY_MHDS_ETBF1_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MHDS_Bits.ETBF1 */
+#define IFX_ERAY_MHDS_ETBF1_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_MHDS_Bits.ETBF2 */
+#define IFX_ERAY_MHDS_ETBF2_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MHDS_Bits.ETBF2 */
+#define IFX_ERAY_MHDS_ETBF2_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MHDS_Bits.ETBF2 */
+#define IFX_ERAY_MHDS_ETBF2_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_MHDS_Bits.FMB */
+#define IFX_ERAY_MHDS_FMB_LEN (7u)
+
+/** \brief Mask for Ifx_ERAY_MHDS_Bits.FMB */
+#define IFX_ERAY_MHDS_FMB_MSK (0x7fu)
+
+/** \brief Offset for Ifx_ERAY_MHDS_Bits.FMB */
+#define IFX_ERAY_MHDS_FMB_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_MHDS_Bits.FMBD */
+#define IFX_ERAY_MHDS_FMBD_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MHDS_Bits.FMBD */
+#define IFX_ERAY_MHDS_FMBD_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MHDS_Bits.FMBD */
+#define IFX_ERAY_MHDS_FMBD_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_MHDS_Bits.MBT */
+#define IFX_ERAY_MHDS_MBT_LEN (7u)
+
+/** \brief Mask for Ifx_ERAY_MHDS_Bits.MBT */
+#define IFX_ERAY_MHDS_MBT_MSK (0x7fu)
+
+/** \brief Offset for Ifx_ERAY_MHDS_Bits.MBT */
+#define IFX_ERAY_MHDS_MBT_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_MHDS_Bits.MBU */
+#define IFX_ERAY_MHDS_MBU_LEN (7u)
+
+/** \brief Mask for Ifx_ERAY_MHDS_Bits.MBU */
+#define IFX_ERAY_MHDS_MBU_MSK (0x7fu)
+
+/** \brief Offset for Ifx_ERAY_MHDS_Bits.MBU */
+#define IFX_ERAY_MHDS_MBU_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_MHDS_Bits.MFMB */
+#define IFX_ERAY_MHDS_MFMB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MHDS_Bits.MFMB */
+#define IFX_ERAY_MHDS_MFMB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MHDS_Bits.MFMB */
+#define IFX_ERAY_MHDS_MFMB_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_MRC_Bits.FDB */
+#define IFX_ERAY_MRC_FDB_LEN (8u)
+
+/** \brief Mask for Ifx_ERAY_MRC_Bits.FDB */
+#define IFX_ERAY_MRC_FDB_MSK (0xffu)
+
+/** \brief Offset for Ifx_ERAY_MRC_Bits.FDB */
+#define IFX_ERAY_MRC_FDB_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_MRC_Bits.FFB */
+#define IFX_ERAY_MRC_FFB_LEN (8u)
+
+/** \brief Mask for Ifx_ERAY_MRC_Bits.FFB */
+#define IFX_ERAY_MRC_FFB_MSK (0xffu)
+
+/** \brief Offset for Ifx_ERAY_MRC_Bits.FFB */
+#define IFX_ERAY_MRC_FFB_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_MRC_Bits.LCB */
+#define IFX_ERAY_MRC_LCB_LEN (8u)
+
+/** \brief Mask for Ifx_ERAY_MRC_Bits.LCB */
+#define IFX_ERAY_MRC_LCB_MSK (0xffu)
+
+/** \brief Offset for Ifx_ERAY_MRC_Bits.LCB */
+#define IFX_ERAY_MRC_LCB_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_MRC_Bits.SEC */
+#define IFX_ERAY_MRC_SEC_LEN (2u)
+
+/** \brief Mask for Ifx_ERAY_MRC_Bits.SEC */
+#define IFX_ERAY_MRC_SEC_MSK (0x3u)
+
+/** \brief Offset for Ifx_ERAY_MRC_Bits.SEC */
+#define IFX_ERAY_MRC_SEC_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_MRC_Bits.SPLM */
+#define IFX_ERAY_MRC_SPLM_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MRC_Bits.SPLM */
+#define IFX_ERAY_MRC_SPLM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MRC_Bits.SPLM */
+#define IFX_ERAY_MRC_SPLM_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP0 */
+#define IFX_ERAY_MSIC1_MSIP0_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP0 */
+#define IFX_ERAY_MSIC1_MSIP0_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP0 */
+#define IFX_ERAY_MSIC1_MSIP0_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP10 */
+#define IFX_ERAY_MSIC1_MSIP10_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP10 */
+#define IFX_ERAY_MSIC1_MSIP10_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP10 */
+#define IFX_ERAY_MSIC1_MSIP10_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP11 */
+#define IFX_ERAY_MSIC1_MSIP11_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP11 */
+#define IFX_ERAY_MSIC1_MSIP11_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP11 */
+#define IFX_ERAY_MSIC1_MSIP11_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP12 */
+#define IFX_ERAY_MSIC1_MSIP12_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP12 */
+#define IFX_ERAY_MSIC1_MSIP12_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP12 */
+#define IFX_ERAY_MSIC1_MSIP12_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP13 */
+#define IFX_ERAY_MSIC1_MSIP13_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP13 */
+#define IFX_ERAY_MSIC1_MSIP13_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP13 */
+#define IFX_ERAY_MSIC1_MSIP13_OFF (13u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP14 */
+#define IFX_ERAY_MSIC1_MSIP14_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP14 */
+#define IFX_ERAY_MSIC1_MSIP14_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP14 */
+#define IFX_ERAY_MSIC1_MSIP14_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP15 */
+#define IFX_ERAY_MSIC1_MSIP15_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP15 */
+#define IFX_ERAY_MSIC1_MSIP15_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP15 */
+#define IFX_ERAY_MSIC1_MSIP15_OFF (15u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP16 */
+#define IFX_ERAY_MSIC1_MSIP16_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP16 */
+#define IFX_ERAY_MSIC1_MSIP16_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP16 */
+#define IFX_ERAY_MSIC1_MSIP16_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP17 */
+#define IFX_ERAY_MSIC1_MSIP17_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP17 */
+#define IFX_ERAY_MSIC1_MSIP17_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP17 */
+#define IFX_ERAY_MSIC1_MSIP17_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP18 */
+#define IFX_ERAY_MSIC1_MSIP18_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP18 */
+#define IFX_ERAY_MSIC1_MSIP18_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP18 */
+#define IFX_ERAY_MSIC1_MSIP18_OFF (18u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP19 */
+#define IFX_ERAY_MSIC1_MSIP19_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP19 */
+#define IFX_ERAY_MSIC1_MSIP19_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP19 */
+#define IFX_ERAY_MSIC1_MSIP19_OFF (19u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP1 */
+#define IFX_ERAY_MSIC1_MSIP1_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP1 */
+#define IFX_ERAY_MSIC1_MSIP1_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP1 */
+#define IFX_ERAY_MSIC1_MSIP1_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP20 */
+#define IFX_ERAY_MSIC1_MSIP20_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP20 */
+#define IFX_ERAY_MSIC1_MSIP20_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP20 */
+#define IFX_ERAY_MSIC1_MSIP20_OFF (20u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP21 */
+#define IFX_ERAY_MSIC1_MSIP21_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP21 */
+#define IFX_ERAY_MSIC1_MSIP21_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP21 */
+#define IFX_ERAY_MSIC1_MSIP21_OFF (21u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP22 */
+#define IFX_ERAY_MSIC1_MSIP22_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP22 */
+#define IFX_ERAY_MSIC1_MSIP22_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP22 */
+#define IFX_ERAY_MSIC1_MSIP22_OFF (22u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP23 */
+#define IFX_ERAY_MSIC1_MSIP23_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP23 */
+#define IFX_ERAY_MSIC1_MSIP23_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP23 */
+#define IFX_ERAY_MSIC1_MSIP23_OFF (23u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP24 */
+#define IFX_ERAY_MSIC1_MSIP24_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP24 */
+#define IFX_ERAY_MSIC1_MSIP24_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP24 */
+#define IFX_ERAY_MSIC1_MSIP24_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP25 */
+#define IFX_ERAY_MSIC1_MSIP25_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP25 */
+#define IFX_ERAY_MSIC1_MSIP25_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP25 */
+#define IFX_ERAY_MSIC1_MSIP25_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP26 */
+#define IFX_ERAY_MSIC1_MSIP26_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP26 */
+#define IFX_ERAY_MSIC1_MSIP26_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP26 */
+#define IFX_ERAY_MSIC1_MSIP26_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP27 */
+#define IFX_ERAY_MSIC1_MSIP27_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP27 */
+#define IFX_ERAY_MSIC1_MSIP27_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP27 */
+#define IFX_ERAY_MSIC1_MSIP27_OFF (27u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP28 */
+#define IFX_ERAY_MSIC1_MSIP28_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP28 */
+#define IFX_ERAY_MSIC1_MSIP28_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP28 */
+#define IFX_ERAY_MSIC1_MSIP28_OFF (28u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP29 */
+#define IFX_ERAY_MSIC1_MSIP29_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP29 */
+#define IFX_ERAY_MSIC1_MSIP29_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP29 */
+#define IFX_ERAY_MSIC1_MSIP29_OFF (29u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP2 */
+#define IFX_ERAY_MSIC1_MSIP2_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP2 */
+#define IFX_ERAY_MSIC1_MSIP2_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP2 */
+#define IFX_ERAY_MSIC1_MSIP2_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP30 */
+#define IFX_ERAY_MSIC1_MSIP30_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP30 */
+#define IFX_ERAY_MSIC1_MSIP30_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP30 */
+#define IFX_ERAY_MSIC1_MSIP30_OFF (30u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP31 */
+#define IFX_ERAY_MSIC1_MSIP31_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP31 */
+#define IFX_ERAY_MSIC1_MSIP31_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP31 */
+#define IFX_ERAY_MSIC1_MSIP31_OFF (31u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP3 */
+#define IFX_ERAY_MSIC1_MSIP3_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP3 */
+#define IFX_ERAY_MSIC1_MSIP3_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP3 */
+#define IFX_ERAY_MSIC1_MSIP3_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP4 */
+#define IFX_ERAY_MSIC1_MSIP4_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP4 */
+#define IFX_ERAY_MSIC1_MSIP4_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP4 */
+#define IFX_ERAY_MSIC1_MSIP4_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP5 */
+#define IFX_ERAY_MSIC1_MSIP5_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP5 */
+#define IFX_ERAY_MSIC1_MSIP5_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP5 */
+#define IFX_ERAY_MSIC1_MSIP5_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP6 */
+#define IFX_ERAY_MSIC1_MSIP6_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP6 */
+#define IFX_ERAY_MSIC1_MSIP6_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP6 */
+#define IFX_ERAY_MSIC1_MSIP6_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP7 */
+#define IFX_ERAY_MSIC1_MSIP7_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP7 */
+#define IFX_ERAY_MSIC1_MSIP7_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP7 */
+#define IFX_ERAY_MSIC1_MSIP7_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP8 */
+#define IFX_ERAY_MSIC1_MSIP8_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP8 */
+#define IFX_ERAY_MSIC1_MSIP8_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP8 */
+#define IFX_ERAY_MSIC1_MSIP8_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_MSIC1_Bits.MSIP9 */
+#define IFX_ERAY_MSIC1_MSIP9_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC1_Bits.MSIP9 */
+#define IFX_ERAY_MSIC1_MSIP9_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC1_Bits.MSIP9 */
+#define IFX_ERAY_MSIC1_MSIP9_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP32 */
+#define IFX_ERAY_MSIC2_MSIP32_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP32 */
+#define IFX_ERAY_MSIC2_MSIP32_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP32 */
+#define IFX_ERAY_MSIC2_MSIP32_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP33 */
+#define IFX_ERAY_MSIC2_MSIP33_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP33 */
+#define IFX_ERAY_MSIC2_MSIP33_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP33 */
+#define IFX_ERAY_MSIC2_MSIP33_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP34 */
+#define IFX_ERAY_MSIC2_MSIP34_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP34 */
+#define IFX_ERAY_MSIC2_MSIP34_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP34 */
+#define IFX_ERAY_MSIC2_MSIP34_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP35 */
+#define IFX_ERAY_MSIC2_MSIP35_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP35 */
+#define IFX_ERAY_MSIC2_MSIP35_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP35 */
+#define IFX_ERAY_MSIC2_MSIP35_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP36 */
+#define IFX_ERAY_MSIC2_MSIP36_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP36 */
+#define IFX_ERAY_MSIC2_MSIP36_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP36 */
+#define IFX_ERAY_MSIC2_MSIP36_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP37 */
+#define IFX_ERAY_MSIC2_MSIP37_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP37 */
+#define IFX_ERAY_MSIC2_MSIP37_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP37 */
+#define IFX_ERAY_MSIC2_MSIP37_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP38 */
+#define IFX_ERAY_MSIC2_MSIP38_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP38 */
+#define IFX_ERAY_MSIC2_MSIP38_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP38 */
+#define IFX_ERAY_MSIC2_MSIP38_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP39 */
+#define IFX_ERAY_MSIC2_MSIP39_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP39 */
+#define IFX_ERAY_MSIC2_MSIP39_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP39 */
+#define IFX_ERAY_MSIC2_MSIP39_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP40 */
+#define IFX_ERAY_MSIC2_MSIP40_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP40 */
+#define IFX_ERAY_MSIC2_MSIP40_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP40 */
+#define IFX_ERAY_MSIC2_MSIP40_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP41 */
+#define IFX_ERAY_MSIC2_MSIP41_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP41 */
+#define IFX_ERAY_MSIC2_MSIP41_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP41 */
+#define IFX_ERAY_MSIC2_MSIP41_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP42 */
+#define IFX_ERAY_MSIC2_MSIP42_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP42 */
+#define IFX_ERAY_MSIC2_MSIP42_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP42 */
+#define IFX_ERAY_MSIC2_MSIP42_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP43 */
+#define IFX_ERAY_MSIC2_MSIP43_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP43 */
+#define IFX_ERAY_MSIC2_MSIP43_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP43 */
+#define IFX_ERAY_MSIC2_MSIP43_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP44 */
+#define IFX_ERAY_MSIC2_MSIP44_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP44 */
+#define IFX_ERAY_MSIC2_MSIP44_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP44 */
+#define IFX_ERAY_MSIC2_MSIP44_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP45 */
+#define IFX_ERAY_MSIC2_MSIP45_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP45 */
+#define IFX_ERAY_MSIC2_MSIP45_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP45 */
+#define IFX_ERAY_MSIC2_MSIP45_OFF (13u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP46 */
+#define IFX_ERAY_MSIC2_MSIP46_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP46 */
+#define IFX_ERAY_MSIC2_MSIP46_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP46 */
+#define IFX_ERAY_MSIC2_MSIP46_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP47 */
+#define IFX_ERAY_MSIC2_MSIP47_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP47 */
+#define IFX_ERAY_MSIC2_MSIP47_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP47 */
+#define IFX_ERAY_MSIC2_MSIP47_OFF (15u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP48 */
+#define IFX_ERAY_MSIC2_MSIP48_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP48 */
+#define IFX_ERAY_MSIC2_MSIP48_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP48 */
+#define IFX_ERAY_MSIC2_MSIP48_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP49 */
+#define IFX_ERAY_MSIC2_MSIP49_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP49 */
+#define IFX_ERAY_MSIC2_MSIP49_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP49 */
+#define IFX_ERAY_MSIC2_MSIP49_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP50 */
+#define IFX_ERAY_MSIC2_MSIP50_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP50 */
+#define IFX_ERAY_MSIC2_MSIP50_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP50 */
+#define IFX_ERAY_MSIC2_MSIP50_OFF (18u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP51 */
+#define IFX_ERAY_MSIC2_MSIP51_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP51 */
+#define IFX_ERAY_MSIC2_MSIP51_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP51 */
+#define IFX_ERAY_MSIC2_MSIP51_OFF (19u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP52 */
+#define IFX_ERAY_MSIC2_MSIP52_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP52 */
+#define IFX_ERAY_MSIC2_MSIP52_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP52 */
+#define IFX_ERAY_MSIC2_MSIP52_OFF (20u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP53 */
+#define IFX_ERAY_MSIC2_MSIP53_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP53 */
+#define IFX_ERAY_MSIC2_MSIP53_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP53 */
+#define IFX_ERAY_MSIC2_MSIP53_OFF (21u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP54 */
+#define IFX_ERAY_MSIC2_MSIP54_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP54 */
+#define IFX_ERAY_MSIC2_MSIP54_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP54 */
+#define IFX_ERAY_MSIC2_MSIP54_OFF (22u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP55 */
+#define IFX_ERAY_MSIC2_MSIP55_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP55 */
+#define IFX_ERAY_MSIC2_MSIP55_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP55 */
+#define IFX_ERAY_MSIC2_MSIP55_OFF (23u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP56 */
+#define IFX_ERAY_MSIC2_MSIP56_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP56 */
+#define IFX_ERAY_MSIC2_MSIP56_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP56 */
+#define IFX_ERAY_MSIC2_MSIP56_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP57 */
+#define IFX_ERAY_MSIC2_MSIP57_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP57 */
+#define IFX_ERAY_MSIC2_MSIP57_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP57 */
+#define IFX_ERAY_MSIC2_MSIP57_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP58 */
+#define IFX_ERAY_MSIC2_MSIP58_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP58 */
+#define IFX_ERAY_MSIC2_MSIP58_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP58 */
+#define IFX_ERAY_MSIC2_MSIP58_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP59 */
+#define IFX_ERAY_MSIC2_MSIP59_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP59 */
+#define IFX_ERAY_MSIC2_MSIP59_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP59 */
+#define IFX_ERAY_MSIC2_MSIP59_OFF (27u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP60 */
+#define IFX_ERAY_MSIC2_MSIP60_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP60 */
+#define IFX_ERAY_MSIC2_MSIP60_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP60 */
+#define IFX_ERAY_MSIC2_MSIP60_OFF (28u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP61 */
+#define IFX_ERAY_MSIC2_MSIP61_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP61 */
+#define IFX_ERAY_MSIC2_MSIP61_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP61 */
+#define IFX_ERAY_MSIC2_MSIP61_OFF (29u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP62 */
+#define IFX_ERAY_MSIC2_MSIP62_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP62 */
+#define IFX_ERAY_MSIC2_MSIP62_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP62 */
+#define IFX_ERAY_MSIC2_MSIP62_OFF (30u)
+
+/** \brief Length for Ifx_ERAY_MSIC2_Bits.MSIP63 */
+#define IFX_ERAY_MSIC2_MSIP63_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC2_Bits.MSIP63 */
+#define IFX_ERAY_MSIC2_MSIP63_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC2_Bits.MSIP63 */
+#define IFX_ERAY_MSIC2_MSIP63_OFF (31u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP64 */
+#define IFX_ERAY_MSIC3_MSIP64_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP64 */
+#define IFX_ERAY_MSIC3_MSIP64_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP64 */
+#define IFX_ERAY_MSIC3_MSIP64_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP65 */
+#define IFX_ERAY_MSIC3_MSIP65_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP65 */
+#define IFX_ERAY_MSIC3_MSIP65_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP65 */
+#define IFX_ERAY_MSIC3_MSIP65_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP66 */
+#define IFX_ERAY_MSIC3_MSIP66_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP66 */
+#define IFX_ERAY_MSIC3_MSIP66_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP66 */
+#define IFX_ERAY_MSIC3_MSIP66_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP67 */
+#define IFX_ERAY_MSIC3_MSIP67_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP67 */
+#define IFX_ERAY_MSIC3_MSIP67_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP67 */
+#define IFX_ERAY_MSIC3_MSIP67_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP68 */
+#define IFX_ERAY_MSIC3_MSIP68_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP68 */
+#define IFX_ERAY_MSIC3_MSIP68_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP68 */
+#define IFX_ERAY_MSIC3_MSIP68_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP69 */
+#define IFX_ERAY_MSIC3_MSIP69_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP69 */
+#define IFX_ERAY_MSIC3_MSIP69_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP69 */
+#define IFX_ERAY_MSIC3_MSIP69_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP70 */
+#define IFX_ERAY_MSIC3_MSIP70_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP70 */
+#define IFX_ERAY_MSIC3_MSIP70_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP70 */
+#define IFX_ERAY_MSIC3_MSIP70_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP71 */
+#define IFX_ERAY_MSIC3_MSIP71_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP71 */
+#define IFX_ERAY_MSIC3_MSIP71_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP71 */
+#define IFX_ERAY_MSIC3_MSIP71_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP72 */
+#define IFX_ERAY_MSIC3_MSIP72_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP72 */
+#define IFX_ERAY_MSIC3_MSIP72_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP72 */
+#define IFX_ERAY_MSIC3_MSIP72_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP73 */
+#define IFX_ERAY_MSIC3_MSIP73_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP73 */
+#define IFX_ERAY_MSIC3_MSIP73_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP73 */
+#define IFX_ERAY_MSIC3_MSIP73_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP74 */
+#define IFX_ERAY_MSIC3_MSIP74_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP74 */
+#define IFX_ERAY_MSIC3_MSIP74_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP74 */
+#define IFX_ERAY_MSIC3_MSIP74_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP75 */
+#define IFX_ERAY_MSIC3_MSIP75_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP75 */
+#define IFX_ERAY_MSIC3_MSIP75_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP75 */
+#define IFX_ERAY_MSIC3_MSIP75_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP76 */
+#define IFX_ERAY_MSIC3_MSIP76_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP76 */
+#define IFX_ERAY_MSIC3_MSIP76_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP76 */
+#define IFX_ERAY_MSIC3_MSIP76_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP77 */
+#define IFX_ERAY_MSIC3_MSIP77_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP77 */
+#define IFX_ERAY_MSIC3_MSIP77_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP77 */
+#define IFX_ERAY_MSIC3_MSIP77_OFF (13u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP78 */
+#define IFX_ERAY_MSIC3_MSIP78_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP78 */
+#define IFX_ERAY_MSIC3_MSIP78_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP78 */
+#define IFX_ERAY_MSIC3_MSIP78_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP79 */
+#define IFX_ERAY_MSIC3_MSIP79_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP79 */
+#define IFX_ERAY_MSIC3_MSIP79_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP79 */
+#define IFX_ERAY_MSIC3_MSIP79_OFF (15u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP80 */
+#define IFX_ERAY_MSIC3_MSIP80_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP80 */
+#define IFX_ERAY_MSIC3_MSIP80_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP80 */
+#define IFX_ERAY_MSIC3_MSIP80_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP81 */
+#define IFX_ERAY_MSIC3_MSIP81_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP81 */
+#define IFX_ERAY_MSIC3_MSIP81_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP81 */
+#define IFX_ERAY_MSIC3_MSIP81_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP82 */
+#define IFX_ERAY_MSIC3_MSIP82_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP82 */
+#define IFX_ERAY_MSIC3_MSIP82_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP82 */
+#define IFX_ERAY_MSIC3_MSIP82_OFF (18u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP83 */
+#define IFX_ERAY_MSIC3_MSIP83_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP83 */
+#define IFX_ERAY_MSIC3_MSIP83_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP83 */
+#define IFX_ERAY_MSIC3_MSIP83_OFF (19u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP84 */
+#define IFX_ERAY_MSIC3_MSIP84_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP84 */
+#define IFX_ERAY_MSIC3_MSIP84_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP84 */
+#define IFX_ERAY_MSIC3_MSIP84_OFF (20u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP85 */
+#define IFX_ERAY_MSIC3_MSIP85_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP85 */
+#define IFX_ERAY_MSIC3_MSIP85_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP85 */
+#define IFX_ERAY_MSIC3_MSIP85_OFF (21u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP86 */
+#define IFX_ERAY_MSIC3_MSIP86_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP86 */
+#define IFX_ERAY_MSIC3_MSIP86_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP86 */
+#define IFX_ERAY_MSIC3_MSIP86_OFF (22u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP87 */
+#define IFX_ERAY_MSIC3_MSIP87_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP87 */
+#define IFX_ERAY_MSIC3_MSIP87_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP87 */
+#define IFX_ERAY_MSIC3_MSIP87_OFF (23u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP88 */
+#define IFX_ERAY_MSIC3_MSIP88_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP88 */
+#define IFX_ERAY_MSIC3_MSIP88_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP88 */
+#define IFX_ERAY_MSIC3_MSIP88_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP89 */
+#define IFX_ERAY_MSIC3_MSIP89_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP89 */
+#define IFX_ERAY_MSIC3_MSIP89_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP89 */
+#define IFX_ERAY_MSIC3_MSIP89_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP90 */
+#define IFX_ERAY_MSIC3_MSIP90_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP90 */
+#define IFX_ERAY_MSIC3_MSIP90_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP90 */
+#define IFX_ERAY_MSIC3_MSIP90_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP91 */
+#define IFX_ERAY_MSIC3_MSIP91_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP91 */
+#define IFX_ERAY_MSIC3_MSIP91_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP91 */
+#define IFX_ERAY_MSIC3_MSIP91_OFF (27u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP92 */
+#define IFX_ERAY_MSIC3_MSIP92_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP92 */
+#define IFX_ERAY_MSIC3_MSIP92_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP92 */
+#define IFX_ERAY_MSIC3_MSIP92_OFF (28u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP93 */
+#define IFX_ERAY_MSIC3_MSIP93_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP93 */
+#define IFX_ERAY_MSIC3_MSIP93_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP93 */
+#define IFX_ERAY_MSIC3_MSIP93_OFF (29u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP94 */
+#define IFX_ERAY_MSIC3_MSIP94_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP94 */
+#define IFX_ERAY_MSIC3_MSIP94_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP94 */
+#define IFX_ERAY_MSIC3_MSIP94_OFF (30u)
+
+/** \brief Length for Ifx_ERAY_MSIC3_Bits.MSIP95 */
+#define IFX_ERAY_MSIC3_MSIP95_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC3_Bits.MSIP95 */
+#define IFX_ERAY_MSIC3_MSIP95_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC3_Bits.MSIP95 */
+#define IFX_ERAY_MSIC3_MSIP95_OFF (31u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP100 */
+#define IFX_ERAY_MSIC4_MSIP100_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP100 */
+#define IFX_ERAY_MSIC4_MSIP100_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP100 */
+#define IFX_ERAY_MSIC4_MSIP100_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP101 */
+#define IFX_ERAY_MSIC4_MSIP101_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP101 */
+#define IFX_ERAY_MSIC4_MSIP101_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP101 */
+#define IFX_ERAY_MSIC4_MSIP101_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP102 */
+#define IFX_ERAY_MSIC4_MSIP102_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP102 */
+#define IFX_ERAY_MSIC4_MSIP102_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP102 */
+#define IFX_ERAY_MSIC4_MSIP102_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP103 */
+#define IFX_ERAY_MSIC4_MSIP103_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP103 */
+#define IFX_ERAY_MSIC4_MSIP103_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP103 */
+#define IFX_ERAY_MSIC4_MSIP103_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP104 */
+#define IFX_ERAY_MSIC4_MSIP104_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP104 */
+#define IFX_ERAY_MSIC4_MSIP104_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP104 */
+#define IFX_ERAY_MSIC4_MSIP104_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP105 */
+#define IFX_ERAY_MSIC4_MSIP105_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP105 */
+#define IFX_ERAY_MSIC4_MSIP105_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP105 */
+#define IFX_ERAY_MSIC4_MSIP105_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP106 */
+#define IFX_ERAY_MSIC4_MSIP106_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP106 */
+#define IFX_ERAY_MSIC4_MSIP106_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP106 */
+#define IFX_ERAY_MSIC4_MSIP106_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP107 */
+#define IFX_ERAY_MSIC4_MSIP107_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP107 */
+#define IFX_ERAY_MSIC4_MSIP107_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP107 */
+#define IFX_ERAY_MSIC4_MSIP107_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP108 */
+#define IFX_ERAY_MSIC4_MSIP108_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP108 */
+#define IFX_ERAY_MSIC4_MSIP108_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP108 */
+#define IFX_ERAY_MSIC4_MSIP108_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP109 */
+#define IFX_ERAY_MSIC4_MSIP109_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP109 */
+#define IFX_ERAY_MSIC4_MSIP109_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP109 */
+#define IFX_ERAY_MSIC4_MSIP109_OFF (13u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP110 */
+#define IFX_ERAY_MSIC4_MSIP110_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP110 */
+#define IFX_ERAY_MSIC4_MSIP110_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP110 */
+#define IFX_ERAY_MSIC4_MSIP110_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP111 */
+#define IFX_ERAY_MSIC4_MSIP111_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP111 */
+#define IFX_ERAY_MSIC4_MSIP111_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP111 */
+#define IFX_ERAY_MSIC4_MSIP111_OFF (15u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP112 */
+#define IFX_ERAY_MSIC4_MSIP112_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP112 */
+#define IFX_ERAY_MSIC4_MSIP112_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP112 */
+#define IFX_ERAY_MSIC4_MSIP112_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP113 */
+#define IFX_ERAY_MSIC4_MSIP113_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP113 */
+#define IFX_ERAY_MSIC4_MSIP113_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP113 */
+#define IFX_ERAY_MSIC4_MSIP113_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP114 */
+#define IFX_ERAY_MSIC4_MSIP114_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP114 */
+#define IFX_ERAY_MSIC4_MSIP114_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP114 */
+#define IFX_ERAY_MSIC4_MSIP114_OFF (18u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP115 */
+#define IFX_ERAY_MSIC4_MSIP115_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP115 */
+#define IFX_ERAY_MSIC4_MSIP115_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP115 */
+#define IFX_ERAY_MSIC4_MSIP115_OFF (19u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP116 */
+#define IFX_ERAY_MSIC4_MSIP116_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP116 */
+#define IFX_ERAY_MSIC4_MSIP116_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP116 */
+#define IFX_ERAY_MSIC4_MSIP116_OFF (20u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP117 */
+#define IFX_ERAY_MSIC4_MSIP117_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP117 */
+#define IFX_ERAY_MSIC4_MSIP117_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP117 */
+#define IFX_ERAY_MSIC4_MSIP117_OFF (21u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP118 */
+#define IFX_ERAY_MSIC4_MSIP118_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP118 */
+#define IFX_ERAY_MSIC4_MSIP118_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP118 */
+#define IFX_ERAY_MSIC4_MSIP118_OFF (22u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP119 */
+#define IFX_ERAY_MSIC4_MSIP119_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP119 */
+#define IFX_ERAY_MSIC4_MSIP119_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP119 */
+#define IFX_ERAY_MSIC4_MSIP119_OFF (23u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP120 */
+#define IFX_ERAY_MSIC4_MSIP120_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP120 */
+#define IFX_ERAY_MSIC4_MSIP120_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP120 */
+#define IFX_ERAY_MSIC4_MSIP120_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP121 */
+#define IFX_ERAY_MSIC4_MSIP121_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP121 */
+#define IFX_ERAY_MSIC4_MSIP121_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP121 */
+#define IFX_ERAY_MSIC4_MSIP121_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP122 */
+#define IFX_ERAY_MSIC4_MSIP122_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP122 */
+#define IFX_ERAY_MSIC4_MSIP122_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP122 */
+#define IFX_ERAY_MSIC4_MSIP122_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP123 */
+#define IFX_ERAY_MSIC4_MSIP123_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP123 */
+#define IFX_ERAY_MSIC4_MSIP123_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP123 */
+#define IFX_ERAY_MSIC4_MSIP123_OFF (27u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP124 */
+#define IFX_ERAY_MSIC4_MSIP124_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP124 */
+#define IFX_ERAY_MSIC4_MSIP124_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP124 */
+#define IFX_ERAY_MSIC4_MSIP124_OFF (28u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP125 */
+#define IFX_ERAY_MSIC4_MSIP125_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP125 */
+#define IFX_ERAY_MSIC4_MSIP125_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP125 */
+#define IFX_ERAY_MSIC4_MSIP125_OFF (29u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP126 */
+#define IFX_ERAY_MSIC4_MSIP126_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP126 */
+#define IFX_ERAY_MSIC4_MSIP126_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP126 */
+#define IFX_ERAY_MSIC4_MSIP126_OFF (30u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP127 */
+#define IFX_ERAY_MSIC4_MSIP127_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP127 */
+#define IFX_ERAY_MSIC4_MSIP127_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP127 */
+#define IFX_ERAY_MSIC4_MSIP127_OFF (31u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP96 */
+#define IFX_ERAY_MSIC4_MSIP96_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP96 */
+#define IFX_ERAY_MSIC4_MSIP96_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP96 */
+#define IFX_ERAY_MSIC4_MSIP96_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP97 */
+#define IFX_ERAY_MSIC4_MSIP97_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP97 */
+#define IFX_ERAY_MSIC4_MSIP97_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP97 */
+#define IFX_ERAY_MSIC4_MSIP97_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP98 */
+#define IFX_ERAY_MSIC4_MSIP98_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP98 */
+#define IFX_ERAY_MSIC4_MSIP98_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP98 */
+#define IFX_ERAY_MSIC4_MSIP98_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_MSIC4_Bits.MSIP99 */
+#define IFX_ERAY_MSIC4_MSIP99_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_MSIC4_Bits.MSIP99 */
+#define IFX_ERAY_MSIC4_MSIP99_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_MSIC4_Bits.MSIP99 */
+#define IFX_ERAY_MSIC4_MSIP99_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_MTCCV_Bits.CCV */
+#define IFX_ERAY_MTCCV_CCV_LEN (6u)
+
+/** \brief Mask for Ifx_ERAY_MTCCV_Bits.CCV */
+#define IFX_ERAY_MTCCV_CCV_MSK (0x3fu)
+
+/** \brief Offset for Ifx_ERAY_MTCCV_Bits.CCV */
+#define IFX_ERAY_MTCCV_CCV_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_MTCCV_Bits.MTV */
+#define IFX_ERAY_MTCCV_MTV_LEN (14u)
+
+/** \brief Mask for Ifx_ERAY_MTCCV_Bits.MTV */
+#define IFX_ERAY_MTCCV_MTV_MSK (0x3fffu)
+
+/** \brief Offset for Ifx_ERAY_MTCCV_Bits.MTV */
+#define IFX_ERAY_MTCCV_MTV_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND0 */
+#define IFX_ERAY_NDAT1_ND0_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND0 */
+#define IFX_ERAY_NDAT1_ND0_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND0 */
+#define IFX_ERAY_NDAT1_ND0_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND10 */
+#define IFX_ERAY_NDAT1_ND10_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND10 */
+#define IFX_ERAY_NDAT1_ND10_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND10 */
+#define IFX_ERAY_NDAT1_ND10_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND11 */
+#define IFX_ERAY_NDAT1_ND11_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND11 */
+#define IFX_ERAY_NDAT1_ND11_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND11 */
+#define IFX_ERAY_NDAT1_ND11_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND12 */
+#define IFX_ERAY_NDAT1_ND12_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND12 */
+#define IFX_ERAY_NDAT1_ND12_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND12 */
+#define IFX_ERAY_NDAT1_ND12_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND13 */
+#define IFX_ERAY_NDAT1_ND13_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND13 */
+#define IFX_ERAY_NDAT1_ND13_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND13 */
+#define IFX_ERAY_NDAT1_ND13_OFF (13u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND14 */
+#define IFX_ERAY_NDAT1_ND14_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND14 */
+#define IFX_ERAY_NDAT1_ND14_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND14 */
+#define IFX_ERAY_NDAT1_ND14_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND15 */
+#define IFX_ERAY_NDAT1_ND15_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND15 */
+#define IFX_ERAY_NDAT1_ND15_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND15 */
+#define IFX_ERAY_NDAT1_ND15_OFF (15u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND16 */
+#define IFX_ERAY_NDAT1_ND16_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND16 */
+#define IFX_ERAY_NDAT1_ND16_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND16 */
+#define IFX_ERAY_NDAT1_ND16_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND17 */
+#define IFX_ERAY_NDAT1_ND17_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND17 */
+#define IFX_ERAY_NDAT1_ND17_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND17 */
+#define IFX_ERAY_NDAT1_ND17_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND18 */
+#define IFX_ERAY_NDAT1_ND18_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND18 */
+#define IFX_ERAY_NDAT1_ND18_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND18 */
+#define IFX_ERAY_NDAT1_ND18_OFF (18u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND19 */
+#define IFX_ERAY_NDAT1_ND19_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND19 */
+#define IFX_ERAY_NDAT1_ND19_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND19 */
+#define IFX_ERAY_NDAT1_ND19_OFF (19u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND1 */
+#define IFX_ERAY_NDAT1_ND1_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND1 */
+#define IFX_ERAY_NDAT1_ND1_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND1 */
+#define IFX_ERAY_NDAT1_ND1_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND20 */
+#define IFX_ERAY_NDAT1_ND20_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND20 */
+#define IFX_ERAY_NDAT1_ND20_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND20 */
+#define IFX_ERAY_NDAT1_ND20_OFF (20u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND21 */
+#define IFX_ERAY_NDAT1_ND21_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND21 */
+#define IFX_ERAY_NDAT1_ND21_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND21 */
+#define IFX_ERAY_NDAT1_ND21_OFF (21u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND22 */
+#define IFX_ERAY_NDAT1_ND22_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND22 */
+#define IFX_ERAY_NDAT1_ND22_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND22 */
+#define IFX_ERAY_NDAT1_ND22_OFF (22u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND23 */
+#define IFX_ERAY_NDAT1_ND23_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND23 */
+#define IFX_ERAY_NDAT1_ND23_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND23 */
+#define IFX_ERAY_NDAT1_ND23_OFF (23u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND24 */
+#define IFX_ERAY_NDAT1_ND24_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND24 */
+#define IFX_ERAY_NDAT1_ND24_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND24 */
+#define IFX_ERAY_NDAT1_ND24_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND25 */
+#define IFX_ERAY_NDAT1_ND25_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND25 */
+#define IFX_ERAY_NDAT1_ND25_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND25 */
+#define IFX_ERAY_NDAT1_ND25_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND26 */
+#define IFX_ERAY_NDAT1_ND26_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND26 */
+#define IFX_ERAY_NDAT1_ND26_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND26 */
+#define IFX_ERAY_NDAT1_ND26_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND27 */
+#define IFX_ERAY_NDAT1_ND27_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND27 */
+#define IFX_ERAY_NDAT1_ND27_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND27 */
+#define IFX_ERAY_NDAT1_ND27_OFF (27u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND28 */
+#define IFX_ERAY_NDAT1_ND28_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND28 */
+#define IFX_ERAY_NDAT1_ND28_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND28 */
+#define IFX_ERAY_NDAT1_ND28_OFF (28u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND29 */
+#define IFX_ERAY_NDAT1_ND29_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND29 */
+#define IFX_ERAY_NDAT1_ND29_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND29 */
+#define IFX_ERAY_NDAT1_ND29_OFF (29u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND2 */
+#define IFX_ERAY_NDAT1_ND2_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND2 */
+#define IFX_ERAY_NDAT1_ND2_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND2 */
+#define IFX_ERAY_NDAT1_ND2_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND30 */
+#define IFX_ERAY_NDAT1_ND30_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND30 */
+#define IFX_ERAY_NDAT1_ND30_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND30 */
+#define IFX_ERAY_NDAT1_ND30_OFF (30u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND31 */
+#define IFX_ERAY_NDAT1_ND31_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND31 */
+#define IFX_ERAY_NDAT1_ND31_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND31 */
+#define IFX_ERAY_NDAT1_ND31_OFF (31u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND3 */
+#define IFX_ERAY_NDAT1_ND3_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND3 */
+#define IFX_ERAY_NDAT1_ND3_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND3 */
+#define IFX_ERAY_NDAT1_ND3_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND4 */
+#define IFX_ERAY_NDAT1_ND4_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND4 */
+#define IFX_ERAY_NDAT1_ND4_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND4 */
+#define IFX_ERAY_NDAT1_ND4_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND5 */
+#define IFX_ERAY_NDAT1_ND5_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND5 */
+#define IFX_ERAY_NDAT1_ND5_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND5 */
+#define IFX_ERAY_NDAT1_ND5_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND6 */
+#define IFX_ERAY_NDAT1_ND6_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND6 */
+#define IFX_ERAY_NDAT1_ND6_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND6 */
+#define IFX_ERAY_NDAT1_ND6_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND7 */
+#define IFX_ERAY_NDAT1_ND7_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND7 */
+#define IFX_ERAY_NDAT1_ND7_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND7 */
+#define IFX_ERAY_NDAT1_ND7_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND8 */
+#define IFX_ERAY_NDAT1_ND8_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND8 */
+#define IFX_ERAY_NDAT1_ND8_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND8 */
+#define IFX_ERAY_NDAT1_ND8_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_NDAT1_Bits.ND9 */
+#define IFX_ERAY_NDAT1_ND9_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT1_Bits.ND9 */
+#define IFX_ERAY_NDAT1_ND9_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT1_Bits.ND9 */
+#define IFX_ERAY_NDAT1_ND9_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND32 */
+#define IFX_ERAY_NDAT2_ND32_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND32 */
+#define IFX_ERAY_NDAT2_ND32_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND32 */
+#define IFX_ERAY_NDAT2_ND32_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND33 */
+#define IFX_ERAY_NDAT2_ND33_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND33 */
+#define IFX_ERAY_NDAT2_ND33_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND33 */
+#define IFX_ERAY_NDAT2_ND33_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND34 */
+#define IFX_ERAY_NDAT2_ND34_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND34 */
+#define IFX_ERAY_NDAT2_ND34_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND34 */
+#define IFX_ERAY_NDAT2_ND34_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND35 */
+#define IFX_ERAY_NDAT2_ND35_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND35 */
+#define IFX_ERAY_NDAT2_ND35_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND35 */
+#define IFX_ERAY_NDAT2_ND35_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND36 */
+#define IFX_ERAY_NDAT2_ND36_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND36 */
+#define IFX_ERAY_NDAT2_ND36_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND36 */
+#define IFX_ERAY_NDAT2_ND36_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND37 */
+#define IFX_ERAY_NDAT2_ND37_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND37 */
+#define IFX_ERAY_NDAT2_ND37_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND37 */
+#define IFX_ERAY_NDAT2_ND37_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND38 */
+#define IFX_ERAY_NDAT2_ND38_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND38 */
+#define IFX_ERAY_NDAT2_ND38_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND38 */
+#define IFX_ERAY_NDAT2_ND38_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND39 */
+#define IFX_ERAY_NDAT2_ND39_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND39 */
+#define IFX_ERAY_NDAT2_ND39_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND39 */
+#define IFX_ERAY_NDAT2_ND39_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND40 */
+#define IFX_ERAY_NDAT2_ND40_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND40 */
+#define IFX_ERAY_NDAT2_ND40_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND40 */
+#define IFX_ERAY_NDAT2_ND40_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND41 */
+#define IFX_ERAY_NDAT2_ND41_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND41 */
+#define IFX_ERAY_NDAT2_ND41_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND41 */
+#define IFX_ERAY_NDAT2_ND41_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND42 */
+#define IFX_ERAY_NDAT2_ND42_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND42 */
+#define IFX_ERAY_NDAT2_ND42_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND42 */
+#define IFX_ERAY_NDAT2_ND42_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND43 */
+#define IFX_ERAY_NDAT2_ND43_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND43 */
+#define IFX_ERAY_NDAT2_ND43_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND43 */
+#define IFX_ERAY_NDAT2_ND43_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND44 */
+#define IFX_ERAY_NDAT2_ND44_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND44 */
+#define IFX_ERAY_NDAT2_ND44_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND44 */
+#define IFX_ERAY_NDAT2_ND44_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND45 */
+#define IFX_ERAY_NDAT2_ND45_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND45 */
+#define IFX_ERAY_NDAT2_ND45_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND45 */
+#define IFX_ERAY_NDAT2_ND45_OFF (13u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND46 */
+#define IFX_ERAY_NDAT2_ND46_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND46 */
+#define IFX_ERAY_NDAT2_ND46_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND46 */
+#define IFX_ERAY_NDAT2_ND46_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND47 */
+#define IFX_ERAY_NDAT2_ND47_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND47 */
+#define IFX_ERAY_NDAT2_ND47_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND47 */
+#define IFX_ERAY_NDAT2_ND47_OFF (15u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND48 */
+#define IFX_ERAY_NDAT2_ND48_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND48 */
+#define IFX_ERAY_NDAT2_ND48_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND48 */
+#define IFX_ERAY_NDAT2_ND48_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND49 */
+#define IFX_ERAY_NDAT2_ND49_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND49 */
+#define IFX_ERAY_NDAT2_ND49_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND49 */
+#define IFX_ERAY_NDAT2_ND49_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND50 */
+#define IFX_ERAY_NDAT2_ND50_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND50 */
+#define IFX_ERAY_NDAT2_ND50_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND50 */
+#define IFX_ERAY_NDAT2_ND50_OFF (18u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND51 */
+#define IFX_ERAY_NDAT2_ND51_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND51 */
+#define IFX_ERAY_NDAT2_ND51_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND51 */
+#define IFX_ERAY_NDAT2_ND51_OFF (19u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND52 */
+#define IFX_ERAY_NDAT2_ND52_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND52 */
+#define IFX_ERAY_NDAT2_ND52_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND52 */
+#define IFX_ERAY_NDAT2_ND52_OFF (20u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND53 */
+#define IFX_ERAY_NDAT2_ND53_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND53 */
+#define IFX_ERAY_NDAT2_ND53_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND53 */
+#define IFX_ERAY_NDAT2_ND53_OFF (21u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND54 */
+#define IFX_ERAY_NDAT2_ND54_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND54 */
+#define IFX_ERAY_NDAT2_ND54_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND54 */
+#define IFX_ERAY_NDAT2_ND54_OFF (22u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND55 */
+#define IFX_ERAY_NDAT2_ND55_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND55 */
+#define IFX_ERAY_NDAT2_ND55_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND55 */
+#define IFX_ERAY_NDAT2_ND55_OFF (23u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND56 */
+#define IFX_ERAY_NDAT2_ND56_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND56 */
+#define IFX_ERAY_NDAT2_ND56_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND56 */
+#define IFX_ERAY_NDAT2_ND56_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND57 */
+#define IFX_ERAY_NDAT2_ND57_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND57 */
+#define IFX_ERAY_NDAT2_ND57_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND57 */
+#define IFX_ERAY_NDAT2_ND57_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND58 */
+#define IFX_ERAY_NDAT2_ND58_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND58 */
+#define IFX_ERAY_NDAT2_ND58_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND58 */
+#define IFX_ERAY_NDAT2_ND58_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND59 */
+#define IFX_ERAY_NDAT2_ND59_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND59 */
+#define IFX_ERAY_NDAT2_ND59_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND59 */
+#define IFX_ERAY_NDAT2_ND59_OFF (27u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND60 */
+#define IFX_ERAY_NDAT2_ND60_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND60 */
+#define IFX_ERAY_NDAT2_ND60_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND60 */
+#define IFX_ERAY_NDAT2_ND60_OFF (28u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND61 */
+#define IFX_ERAY_NDAT2_ND61_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND61 */
+#define IFX_ERAY_NDAT2_ND61_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND61 */
+#define IFX_ERAY_NDAT2_ND61_OFF (29u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND62 */
+#define IFX_ERAY_NDAT2_ND62_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND62 */
+#define IFX_ERAY_NDAT2_ND62_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND62 */
+#define IFX_ERAY_NDAT2_ND62_OFF (30u)
+
+/** \brief Length for Ifx_ERAY_NDAT2_Bits.ND63 */
+#define IFX_ERAY_NDAT2_ND63_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT2_Bits.ND63 */
+#define IFX_ERAY_NDAT2_ND63_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT2_Bits.ND63 */
+#define IFX_ERAY_NDAT2_ND63_OFF (31u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND64 */
+#define IFX_ERAY_NDAT3_ND64_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND64 */
+#define IFX_ERAY_NDAT3_ND64_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND64 */
+#define IFX_ERAY_NDAT3_ND64_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND65 */
+#define IFX_ERAY_NDAT3_ND65_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND65 */
+#define IFX_ERAY_NDAT3_ND65_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND65 */
+#define IFX_ERAY_NDAT3_ND65_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND66 */
+#define IFX_ERAY_NDAT3_ND66_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND66 */
+#define IFX_ERAY_NDAT3_ND66_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND66 */
+#define IFX_ERAY_NDAT3_ND66_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND67 */
+#define IFX_ERAY_NDAT3_ND67_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND67 */
+#define IFX_ERAY_NDAT3_ND67_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND67 */
+#define IFX_ERAY_NDAT3_ND67_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND68 */
+#define IFX_ERAY_NDAT3_ND68_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND68 */
+#define IFX_ERAY_NDAT3_ND68_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND68 */
+#define IFX_ERAY_NDAT3_ND68_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND69 */
+#define IFX_ERAY_NDAT3_ND69_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND69 */
+#define IFX_ERAY_NDAT3_ND69_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND69 */
+#define IFX_ERAY_NDAT3_ND69_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND70 */
+#define IFX_ERAY_NDAT3_ND70_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND70 */
+#define IFX_ERAY_NDAT3_ND70_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND70 */
+#define IFX_ERAY_NDAT3_ND70_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND71 */
+#define IFX_ERAY_NDAT3_ND71_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND71 */
+#define IFX_ERAY_NDAT3_ND71_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND71 */
+#define IFX_ERAY_NDAT3_ND71_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND72 */
+#define IFX_ERAY_NDAT3_ND72_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND72 */
+#define IFX_ERAY_NDAT3_ND72_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND72 */
+#define IFX_ERAY_NDAT3_ND72_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND73 */
+#define IFX_ERAY_NDAT3_ND73_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND73 */
+#define IFX_ERAY_NDAT3_ND73_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND73 */
+#define IFX_ERAY_NDAT3_ND73_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND74 */
+#define IFX_ERAY_NDAT3_ND74_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND74 */
+#define IFX_ERAY_NDAT3_ND74_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND74 */
+#define IFX_ERAY_NDAT3_ND74_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND75 */
+#define IFX_ERAY_NDAT3_ND75_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND75 */
+#define IFX_ERAY_NDAT3_ND75_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND75 */
+#define IFX_ERAY_NDAT3_ND75_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND76 */
+#define IFX_ERAY_NDAT3_ND76_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND76 */
+#define IFX_ERAY_NDAT3_ND76_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND76 */
+#define IFX_ERAY_NDAT3_ND76_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND77 */
+#define IFX_ERAY_NDAT3_ND77_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND77 */
+#define IFX_ERAY_NDAT3_ND77_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND77 */
+#define IFX_ERAY_NDAT3_ND77_OFF (13u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND78 */
+#define IFX_ERAY_NDAT3_ND78_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND78 */
+#define IFX_ERAY_NDAT3_ND78_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND78 */
+#define IFX_ERAY_NDAT3_ND78_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND79 */
+#define IFX_ERAY_NDAT3_ND79_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND79 */
+#define IFX_ERAY_NDAT3_ND79_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND79 */
+#define IFX_ERAY_NDAT3_ND79_OFF (15u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND80 */
+#define IFX_ERAY_NDAT3_ND80_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND80 */
+#define IFX_ERAY_NDAT3_ND80_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND80 */
+#define IFX_ERAY_NDAT3_ND80_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND81 */
+#define IFX_ERAY_NDAT3_ND81_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND81 */
+#define IFX_ERAY_NDAT3_ND81_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND81 */
+#define IFX_ERAY_NDAT3_ND81_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND82 */
+#define IFX_ERAY_NDAT3_ND82_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND82 */
+#define IFX_ERAY_NDAT3_ND82_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND82 */
+#define IFX_ERAY_NDAT3_ND82_OFF (18u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND83 */
+#define IFX_ERAY_NDAT3_ND83_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND83 */
+#define IFX_ERAY_NDAT3_ND83_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND83 */
+#define IFX_ERAY_NDAT3_ND83_OFF (19u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND84 */
+#define IFX_ERAY_NDAT3_ND84_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND84 */
+#define IFX_ERAY_NDAT3_ND84_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND84 */
+#define IFX_ERAY_NDAT3_ND84_OFF (20u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND85 */
+#define IFX_ERAY_NDAT3_ND85_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND85 */
+#define IFX_ERAY_NDAT3_ND85_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND85 */
+#define IFX_ERAY_NDAT3_ND85_OFF (21u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND86 */
+#define IFX_ERAY_NDAT3_ND86_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND86 */
+#define IFX_ERAY_NDAT3_ND86_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND86 */
+#define IFX_ERAY_NDAT3_ND86_OFF (22u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND87 */
+#define IFX_ERAY_NDAT3_ND87_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND87 */
+#define IFX_ERAY_NDAT3_ND87_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND87 */
+#define IFX_ERAY_NDAT3_ND87_OFF (23u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND88 */
+#define IFX_ERAY_NDAT3_ND88_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND88 */
+#define IFX_ERAY_NDAT3_ND88_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND88 */
+#define IFX_ERAY_NDAT3_ND88_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND89 */
+#define IFX_ERAY_NDAT3_ND89_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND89 */
+#define IFX_ERAY_NDAT3_ND89_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND89 */
+#define IFX_ERAY_NDAT3_ND89_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND90 */
+#define IFX_ERAY_NDAT3_ND90_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND90 */
+#define IFX_ERAY_NDAT3_ND90_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND90 */
+#define IFX_ERAY_NDAT3_ND90_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND91 */
+#define IFX_ERAY_NDAT3_ND91_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND91 */
+#define IFX_ERAY_NDAT3_ND91_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND91 */
+#define IFX_ERAY_NDAT3_ND91_OFF (27u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND92 */
+#define IFX_ERAY_NDAT3_ND92_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND92 */
+#define IFX_ERAY_NDAT3_ND92_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND92 */
+#define IFX_ERAY_NDAT3_ND92_OFF (28u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND93 */
+#define IFX_ERAY_NDAT3_ND93_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND93 */
+#define IFX_ERAY_NDAT3_ND93_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND93 */
+#define IFX_ERAY_NDAT3_ND93_OFF (29u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND94 */
+#define IFX_ERAY_NDAT3_ND94_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND94 */
+#define IFX_ERAY_NDAT3_ND94_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND94 */
+#define IFX_ERAY_NDAT3_ND94_OFF (30u)
+
+/** \brief Length for Ifx_ERAY_NDAT3_Bits.ND95 */
+#define IFX_ERAY_NDAT3_ND95_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT3_Bits.ND95 */
+#define IFX_ERAY_NDAT3_ND95_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT3_Bits.ND95 */
+#define IFX_ERAY_NDAT3_ND95_OFF (31u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND100 */
+#define IFX_ERAY_NDAT4_ND100_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND100 */
+#define IFX_ERAY_NDAT4_ND100_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND100 */
+#define IFX_ERAY_NDAT4_ND100_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND101 */
+#define IFX_ERAY_NDAT4_ND101_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND101 */
+#define IFX_ERAY_NDAT4_ND101_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND101 */
+#define IFX_ERAY_NDAT4_ND101_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND102 */
+#define IFX_ERAY_NDAT4_ND102_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND102 */
+#define IFX_ERAY_NDAT4_ND102_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND102 */
+#define IFX_ERAY_NDAT4_ND102_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND103 */
+#define IFX_ERAY_NDAT4_ND103_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND103 */
+#define IFX_ERAY_NDAT4_ND103_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND103 */
+#define IFX_ERAY_NDAT4_ND103_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND104 */
+#define IFX_ERAY_NDAT4_ND104_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND104 */
+#define IFX_ERAY_NDAT4_ND104_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND104 */
+#define IFX_ERAY_NDAT4_ND104_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND105 */
+#define IFX_ERAY_NDAT4_ND105_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND105 */
+#define IFX_ERAY_NDAT4_ND105_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND105 */
+#define IFX_ERAY_NDAT4_ND105_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND106 */
+#define IFX_ERAY_NDAT4_ND106_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND106 */
+#define IFX_ERAY_NDAT4_ND106_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND106 */
+#define IFX_ERAY_NDAT4_ND106_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND107 */
+#define IFX_ERAY_NDAT4_ND107_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND107 */
+#define IFX_ERAY_NDAT4_ND107_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND107 */
+#define IFX_ERAY_NDAT4_ND107_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND108 */
+#define IFX_ERAY_NDAT4_ND108_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND108 */
+#define IFX_ERAY_NDAT4_ND108_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND108 */
+#define IFX_ERAY_NDAT4_ND108_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND109 */
+#define IFX_ERAY_NDAT4_ND109_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND109 */
+#define IFX_ERAY_NDAT4_ND109_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND109 */
+#define IFX_ERAY_NDAT4_ND109_OFF (13u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND110 */
+#define IFX_ERAY_NDAT4_ND110_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND110 */
+#define IFX_ERAY_NDAT4_ND110_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND110 */
+#define IFX_ERAY_NDAT4_ND110_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND111 */
+#define IFX_ERAY_NDAT4_ND111_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND111 */
+#define IFX_ERAY_NDAT4_ND111_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND111 */
+#define IFX_ERAY_NDAT4_ND111_OFF (15u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND112 */
+#define IFX_ERAY_NDAT4_ND112_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND112 */
+#define IFX_ERAY_NDAT4_ND112_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND112 */
+#define IFX_ERAY_NDAT4_ND112_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND113 */
+#define IFX_ERAY_NDAT4_ND113_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND113 */
+#define IFX_ERAY_NDAT4_ND113_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND113 */
+#define IFX_ERAY_NDAT4_ND113_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND114 */
+#define IFX_ERAY_NDAT4_ND114_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND114 */
+#define IFX_ERAY_NDAT4_ND114_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND114 */
+#define IFX_ERAY_NDAT4_ND114_OFF (18u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND115 */
+#define IFX_ERAY_NDAT4_ND115_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND115 */
+#define IFX_ERAY_NDAT4_ND115_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND115 */
+#define IFX_ERAY_NDAT4_ND115_OFF (19u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND116 */
+#define IFX_ERAY_NDAT4_ND116_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND116 */
+#define IFX_ERAY_NDAT4_ND116_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND116 */
+#define IFX_ERAY_NDAT4_ND116_OFF (20u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND117 */
+#define IFX_ERAY_NDAT4_ND117_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND117 */
+#define IFX_ERAY_NDAT4_ND117_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND117 */
+#define IFX_ERAY_NDAT4_ND117_OFF (21u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND118 */
+#define IFX_ERAY_NDAT4_ND118_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND118 */
+#define IFX_ERAY_NDAT4_ND118_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND118 */
+#define IFX_ERAY_NDAT4_ND118_OFF (22u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND119 */
+#define IFX_ERAY_NDAT4_ND119_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND119 */
+#define IFX_ERAY_NDAT4_ND119_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND119 */
+#define IFX_ERAY_NDAT4_ND119_OFF (23u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND120 */
+#define IFX_ERAY_NDAT4_ND120_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND120 */
+#define IFX_ERAY_NDAT4_ND120_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND120 */
+#define IFX_ERAY_NDAT4_ND120_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND121 */
+#define IFX_ERAY_NDAT4_ND121_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND121 */
+#define IFX_ERAY_NDAT4_ND121_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND121 */
+#define IFX_ERAY_NDAT4_ND121_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND122 */
+#define IFX_ERAY_NDAT4_ND122_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND122 */
+#define IFX_ERAY_NDAT4_ND122_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND122 */
+#define IFX_ERAY_NDAT4_ND122_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND123 */
+#define IFX_ERAY_NDAT4_ND123_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND123 */
+#define IFX_ERAY_NDAT4_ND123_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND123 */
+#define IFX_ERAY_NDAT4_ND123_OFF (27u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND124 */
+#define IFX_ERAY_NDAT4_ND124_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND124 */
+#define IFX_ERAY_NDAT4_ND124_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND124 */
+#define IFX_ERAY_NDAT4_ND124_OFF (28u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND125 */
+#define IFX_ERAY_NDAT4_ND125_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND125 */
+#define IFX_ERAY_NDAT4_ND125_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND125 */
+#define IFX_ERAY_NDAT4_ND125_OFF (29u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND126 */
+#define IFX_ERAY_NDAT4_ND126_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND126 */
+#define IFX_ERAY_NDAT4_ND126_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND126 */
+#define IFX_ERAY_NDAT4_ND126_OFF (30u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND127 */
+#define IFX_ERAY_NDAT4_ND127_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND127 */
+#define IFX_ERAY_NDAT4_ND127_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND127 */
+#define IFX_ERAY_NDAT4_ND127_OFF (31u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND96 */
+#define IFX_ERAY_NDAT4_ND96_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND96 */
+#define IFX_ERAY_NDAT4_ND96_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND96 */
+#define IFX_ERAY_NDAT4_ND96_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND97 */
+#define IFX_ERAY_NDAT4_ND97_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND97 */
+#define IFX_ERAY_NDAT4_ND97_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND97 */
+#define IFX_ERAY_NDAT4_ND97_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND98 */
+#define IFX_ERAY_NDAT4_ND98_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND98 */
+#define IFX_ERAY_NDAT4_ND98_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND98 */
+#define IFX_ERAY_NDAT4_ND98_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_NDAT4_Bits.ND99 */
+#define IFX_ERAY_NDAT4_ND99_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDAT4_Bits.ND99 */
+#define IFX_ERAY_NDAT4_ND99_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDAT4_Bits.ND99 */
+#define IFX_ERAY_NDAT4_ND99_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP0 */
+#define IFX_ERAY_NDIC1_NDIP0_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP0 */
+#define IFX_ERAY_NDIC1_NDIP0_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP0 */
+#define IFX_ERAY_NDIC1_NDIP0_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP10 */
+#define IFX_ERAY_NDIC1_NDIP10_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP10 */
+#define IFX_ERAY_NDIC1_NDIP10_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP10 */
+#define IFX_ERAY_NDIC1_NDIP10_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP11 */
+#define IFX_ERAY_NDIC1_NDIP11_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP11 */
+#define IFX_ERAY_NDIC1_NDIP11_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP11 */
+#define IFX_ERAY_NDIC1_NDIP11_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP12 */
+#define IFX_ERAY_NDIC1_NDIP12_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP12 */
+#define IFX_ERAY_NDIC1_NDIP12_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP12 */
+#define IFX_ERAY_NDIC1_NDIP12_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP13 */
+#define IFX_ERAY_NDIC1_NDIP13_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP13 */
+#define IFX_ERAY_NDIC1_NDIP13_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP13 */
+#define IFX_ERAY_NDIC1_NDIP13_OFF (13u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP14 */
+#define IFX_ERAY_NDIC1_NDIP14_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP14 */
+#define IFX_ERAY_NDIC1_NDIP14_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP14 */
+#define IFX_ERAY_NDIC1_NDIP14_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP15 */
+#define IFX_ERAY_NDIC1_NDIP15_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP15 */
+#define IFX_ERAY_NDIC1_NDIP15_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP15 */
+#define IFX_ERAY_NDIC1_NDIP15_OFF (15u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP16 */
+#define IFX_ERAY_NDIC1_NDIP16_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP16 */
+#define IFX_ERAY_NDIC1_NDIP16_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP16 */
+#define IFX_ERAY_NDIC1_NDIP16_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP17 */
+#define IFX_ERAY_NDIC1_NDIP17_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP17 */
+#define IFX_ERAY_NDIC1_NDIP17_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP17 */
+#define IFX_ERAY_NDIC1_NDIP17_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP18 */
+#define IFX_ERAY_NDIC1_NDIP18_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP18 */
+#define IFX_ERAY_NDIC1_NDIP18_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP18 */
+#define IFX_ERAY_NDIC1_NDIP18_OFF (18u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP19 */
+#define IFX_ERAY_NDIC1_NDIP19_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP19 */
+#define IFX_ERAY_NDIC1_NDIP19_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP19 */
+#define IFX_ERAY_NDIC1_NDIP19_OFF (19u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP1 */
+#define IFX_ERAY_NDIC1_NDIP1_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP1 */
+#define IFX_ERAY_NDIC1_NDIP1_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP1 */
+#define IFX_ERAY_NDIC1_NDIP1_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP20 */
+#define IFX_ERAY_NDIC1_NDIP20_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP20 */
+#define IFX_ERAY_NDIC1_NDIP20_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP20 */
+#define IFX_ERAY_NDIC1_NDIP20_OFF (20u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP21 */
+#define IFX_ERAY_NDIC1_NDIP21_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP21 */
+#define IFX_ERAY_NDIC1_NDIP21_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP21 */
+#define IFX_ERAY_NDIC1_NDIP21_OFF (21u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP22 */
+#define IFX_ERAY_NDIC1_NDIP22_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP22 */
+#define IFX_ERAY_NDIC1_NDIP22_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP22 */
+#define IFX_ERAY_NDIC1_NDIP22_OFF (22u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP23 */
+#define IFX_ERAY_NDIC1_NDIP23_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP23 */
+#define IFX_ERAY_NDIC1_NDIP23_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP23 */
+#define IFX_ERAY_NDIC1_NDIP23_OFF (23u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP24 */
+#define IFX_ERAY_NDIC1_NDIP24_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP24 */
+#define IFX_ERAY_NDIC1_NDIP24_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP24 */
+#define IFX_ERAY_NDIC1_NDIP24_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP25 */
+#define IFX_ERAY_NDIC1_NDIP25_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP25 */
+#define IFX_ERAY_NDIC1_NDIP25_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP25 */
+#define IFX_ERAY_NDIC1_NDIP25_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP26 */
+#define IFX_ERAY_NDIC1_NDIP26_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP26 */
+#define IFX_ERAY_NDIC1_NDIP26_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP26 */
+#define IFX_ERAY_NDIC1_NDIP26_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP27 */
+#define IFX_ERAY_NDIC1_NDIP27_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP27 */
+#define IFX_ERAY_NDIC1_NDIP27_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP27 */
+#define IFX_ERAY_NDIC1_NDIP27_OFF (27u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP28 */
+#define IFX_ERAY_NDIC1_NDIP28_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP28 */
+#define IFX_ERAY_NDIC1_NDIP28_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP28 */
+#define IFX_ERAY_NDIC1_NDIP28_OFF (28u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP29 */
+#define IFX_ERAY_NDIC1_NDIP29_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP29 */
+#define IFX_ERAY_NDIC1_NDIP29_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP29 */
+#define IFX_ERAY_NDIC1_NDIP29_OFF (29u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP2 */
+#define IFX_ERAY_NDIC1_NDIP2_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP2 */
+#define IFX_ERAY_NDIC1_NDIP2_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP2 */
+#define IFX_ERAY_NDIC1_NDIP2_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP30 */
+#define IFX_ERAY_NDIC1_NDIP30_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP30 */
+#define IFX_ERAY_NDIC1_NDIP30_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP30 */
+#define IFX_ERAY_NDIC1_NDIP30_OFF (30u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP31 */
+#define IFX_ERAY_NDIC1_NDIP31_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP31 */
+#define IFX_ERAY_NDIC1_NDIP31_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP31 */
+#define IFX_ERAY_NDIC1_NDIP31_OFF (31u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP3 */
+#define IFX_ERAY_NDIC1_NDIP3_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP3 */
+#define IFX_ERAY_NDIC1_NDIP3_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP3 */
+#define IFX_ERAY_NDIC1_NDIP3_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP4 */
+#define IFX_ERAY_NDIC1_NDIP4_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP4 */
+#define IFX_ERAY_NDIC1_NDIP4_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP4 */
+#define IFX_ERAY_NDIC1_NDIP4_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP5 */
+#define IFX_ERAY_NDIC1_NDIP5_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP5 */
+#define IFX_ERAY_NDIC1_NDIP5_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP5 */
+#define IFX_ERAY_NDIC1_NDIP5_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP6 */
+#define IFX_ERAY_NDIC1_NDIP6_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP6 */
+#define IFX_ERAY_NDIC1_NDIP6_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP6 */
+#define IFX_ERAY_NDIC1_NDIP6_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP7 */
+#define IFX_ERAY_NDIC1_NDIP7_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP7 */
+#define IFX_ERAY_NDIC1_NDIP7_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP7 */
+#define IFX_ERAY_NDIC1_NDIP7_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP8 */
+#define IFX_ERAY_NDIC1_NDIP8_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP8 */
+#define IFX_ERAY_NDIC1_NDIP8_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP8 */
+#define IFX_ERAY_NDIC1_NDIP8_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_NDIC1_Bits.NDIP9 */
+#define IFX_ERAY_NDIC1_NDIP9_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC1_Bits.NDIP9 */
+#define IFX_ERAY_NDIC1_NDIP9_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC1_Bits.NDIP9 */
+#define IFX_ERAY_NDIC1_NDIP9_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP32 */
+#define IFX_ERAY_NDIC2_NDIP32_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP32 */
+#define IFX_ERAY_NDIC2_NDIP32_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP32 */
+#define IFX_ERAY_NDIC2_NDIP32_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP33 */
+#define IFX_ERAY_NDIC2_NDIP33_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP33 */
+#define IFX_ERAY_NDIC2_NDIP33_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP33 */
+#define IFX_ERAY_NDIC2_NDIP33_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP34 */
+#define IFX_ERAY_NDIC2_NDIP34_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP34 */
+#define IFX_ERAY_NDIC2_NDIP34_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP34 */
+#define IFX_ERAY_NDIC2_NDIP34_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP35 */
+#define IFX_ERAY_NDIC2_NDIP35_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP35 */
+#define IFX_ERAY_NDIC2_NDIP35_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP35 */
+#define IFX_ERAY_NDIC2_NDIP35_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP36 */
+#define IFX_ERAY_NDIC2_NDIP36_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP36 */
+#define IFX_ERAY_NDIC2_NDIP36_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP36 */
+#define IFX_ERAY_NDIC2_NDIP36_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP37 */
+#define IFX_ERAY_NDIC2_NDIP37_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP37 */
+#define IFX_ERAY_NDIC2_NDIP37_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP37 */
+#define IFX_ERAY_NDIC2_NDIP37_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP38 */
+#define IFX_ERAY_NDIC2_NDIP38_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP38 */
+#define IFX_ERAY_NDIC2_NDIP38_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP38 */
+#define IFX_ERAY_NDIC2_NDIP38_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP39 */
+#define IFX_ERAY_NDIC2_NDIP39_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP39 */
+#define IFX_ERAY_NDIC2_NDIP39_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP39 */
+#define IFX_ERAY_NDIC2_NDIP39_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP40 */
+#define IFX_ERAY_NDIC2_NDIP40_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP40 */
+#define IFX_ERAY_NDIC2_NDIP40_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP40 */
+#define IFX_ERAY_NDIC2_NDIP40_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP41 */
+#define IFX_ERAY_NDIC2_NDIP41_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP41 */
+#define IFX_ERAY_NDIC2_NDIP41_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP41 */
+#define IFX_ERAY_NDIC2_NDIP41_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP42 */
+#define IFX_ERAY_NDIC2_NDIP42_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP42 */
+#define IFX_ERAY_NDIC2_NDIP42_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP42 */
+#define IFX_ERAY_NDIC2_NDIP42_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP43 */
+#define IFX_ERAY_NDIC2_NDIP43_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP43 */
+#define IFX_ERAY_NDIC2_NDIP43_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP43 */
+#define IFX_ERAY_NDIC2_NDIP43_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP44 */
+#define IFX_ERAY_NDIC2_NDIP44_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP44 */
+#define IFX_ERAY_NDIC2_NDIP44_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP44 */
+#define IFX_ERAY_NDIC2_NDIP44_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP45 */
+#define IFX_ERAY_NDIC2_NDIP45_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP45 */
+#define IFX_ERAY_NDIC2_NDIP45_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP45 */
+#define IFX_ERAY_NDIC2_NDIP45_OFF (13u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP46 */
+#define IFX_ERAY_NDIC2_NDIP46_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP46 */
+#define IFX_ERAY_NDIC2_NDIP46_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP46 */
+#define IFX_ERAY_NDIC2_NDIP46_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP47 */
+#define IFX_ERAY_NDIC2_NDIP47_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP47 */
+#define IFX_ERAY_NDIC2_NDIP47_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP47 */
+#define IFX_ERAY_NDIC2_NDIP47_OFF (15u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP48 */
+#define IFX_ERAY_NDIC2_NDIP48_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP48 */
+#define IFX_ERAY_NDIC2_NDIP48_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP48 */
+#define IFX_ERAY_NDIC2_NDIP48_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP49 */
+#define IFX_ERAY_NDIC2_NDIP49_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP49 */
+#define IFX_ERAY_NDIC2_NDIP49_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP49 */
+#define IFX_ERAY_NDIC2_NDIP49_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP50 */
+#define IFX_ERAY_NDIC2_NDIP50_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP50 */
+#define IFX_ERAY_NDIC2_NDIP50_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP50 */
+#define IFX_ERAY_NDIC2_NDIP50_OFF (18u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP51 */
+#define IFX_ERAY_NDIC2_NDIP51_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP51 */
+#define IFX_ERAY_NDIC2_NDIP51_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP51 */
+#define IFX_ERAY_NDIC2_NDIP51_OFF (19u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP52 */
+#define IFX_ERAY_NDIC2_NDIP52_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP52 */
+#define IFX_ERAY_NDIC2_NDIP52_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP52 */
+#define IFX_ERAY_NDIC2_NDIP52_OFF (20u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP53 */
+#define IFX_ERAY_NDIC2_NDIP53_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP53 */
+#define IFX_ERAY_NDIC2_NDIP53_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP53 */
+#define IFX_ERAY_NDIC2_NDIP53_OFF (21u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP54 */
+#define IFX_ERAY_NDIC2_NDIP54_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP54 */
+#define IFX_ERAY_NDIC2_NDIP54_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP54 */
+#define IFX_ERAY_NDIC2_NDIP54_OFF (22u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP55 */
+#define IFX_ERAY_NDIC2_NDIP55_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP55 */
+#define IFX_ERAY_NDIC2_NDIP55_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP55 */
+#define IFX_ERAY_NDIC2_NDIP55_OFF (23u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP56 */
+#define IFX_ERAY_NDIC2_NDIP56_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP56 */
+#define IFX_ERAY_NDIC2_NDIP56_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP56 */
+#define IFX_ERAY_NDIC2_NDIP56_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP57 */
+#define IFX_ERAY_NDIC2_NDIP57_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP57 */
+#define IFX_ERAY_NDIC2_NDIP57_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP57 */
+#define IFX_ERAY_NDIC2_NDIP57_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP58 */
+#define IFX_ERAY_NDIC2_NDIP58_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP58 */
+#define IFX_ERAY_NDIC2_NDIP58_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP58 */
+#define IFX_ERAY_NDIC2_NDIP58_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP59 */
+#define IFX_ERAY_NDIC2_NDIP59_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP59 */
+#define IFX_ERAY_NDIC2_NDIP59_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP59 */
+#define IFX_ERAY_NDIC2_NDIP59_OFF (27u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP60 */
+#define IFX_ERAY_NDIC2_NDIP60_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP60 */
+#define IFX_ERAY_NDIC2_NDIP60_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP60 */
+#define IFX_ERAY_NDIC2_NDIP60_OFF (28u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP61 */
+#define IFX_ERAY_NDIC2_NDIP61_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP61 */
+#define IFX_ERAY_NDIC2_NDIP61_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP61 */
+#define IFX_ERAY_NDIC2_NDIP61_OFF (29u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP62 */
+#define IFX_ERAY_NDIC2_NDIP62_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP62 */
+#define IFX_ERAY_NDIC2_NDIP62_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP62 */
+#define IFX_ERAY_NDIC2_NDIP62_OFF (30u)
+
+/** \brief Length for Ifx_ERAY_NDIC2_Bits.NDIP63 */
+#define IFX_ERAY_NDIC2_NDIP63_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC2_Bits.NDIP63 */
+#define IFX_ERAY_NDIC2_NDIP63_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC2_Bits.NDIP63 */
+#define IFX_ERAY_NDIC2_NDIP63_OFF (31u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP64 */
+#define IFX_ERAY_NDIC3_NDIP64_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP64 */
+#define IFX_ERAY_NDIC3_NDIP64_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP64 */
+#define IFX_ERAY_NDIC3_NDIP64_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP65 */
+#define IFX_ERAY_NDIC3_NDIP65_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP65 */
+#define IFX_ERAY_NDIC3_NDIP65_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP65 */
+#define IFX_ERAY_NDIC3_NDIP65_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP66 */
+#define IFX_ERAY_NDIC3_NDIP66_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP66 */
+#define IFX_ERAY_NDIC3_NDIP66_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP66 */
+#define IFX_ERAY_NDIC3_NDIP66_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP67 */
+#define IFX_ERAY_NDIC3_NDIP67_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP67 */
+#define IFX_ERAY_NDIC3_NDIP67_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP67 */
+#define IFX_ERAY_NDIC3_NDIP67_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP68 */
+#define IFX_ERAY_NDIC3_NDIP68_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP68 */
+#define IFX_ERAY_NDIC3_NDIP68_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP68 */
+#define IFX_ERAY_NDIC3_NDIP68_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP69 */
+#define IFX_ERAY_NDIC3_NDIP69_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP69 */
+#define IFX_ERAY_NDIC3_NDIP69_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP69 */
+#define IFX_ERAY_NDIC3_NDIP69_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP70 */
+#define IFX_ERAY_NDIC3_NDIP70_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP70 */
+#define IFX_ERAY_NDIC3_NDIP70_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP70 */
+#define IFX_ERAY_NDIC3_NDIP70_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP71 */
+#define IFX_ERAY_NDIC3_NDIP71_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP71 */
+#define IFX_ERAY_NDIC3_NDIP71_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP71 */
+#define IFX_ERAY_NDIC3_NDIP71_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP72 */
+#define IFX_ERAY_NDIC3_NDIP72_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP72 */
+#define IFX_ERAY_NDIC3_NDIP72_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP72 */
+#define IFX_ERAY_NDIC3_NDIP72_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP73 */
+#define IFX_ERAY_NDIC3_NDIP73_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP73 */
+#define IFX_ERAY_NDIC3_NDIP73_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP73 */
+#define IFX_ERAY_NDIC3_NDIP73_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP74 */
+#define IFX_ERAY_NDIC3_NDIP74_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP74 */
+#define IFX_ERAY_NDIC3_NDIP74_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP74 */
+#define IFX_ERAY_NDIC3_NDIP74_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP75 */
+#define IFX_ERAY_NDIC3_NDIP75_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP75 */
+#define IFX_ERAY_NDIC3_NDIP75_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP75 */
+#define IFX_ERAY_NDIC3_NDIP75_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP76 */
+#define IFX_ERAY_NDIC3_NDIP76_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP76 */
+#define IFX_ERAY_NDIC3_NDIP76_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP76 */
+#define IFX_ERAY_NDIC3_NDIP76_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP77 */
+#define IFX_ERAY_NDIC3_NDIP77_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP77 */
+#define IFX_ERAY_NDIC3_NDIP77_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP77 */
+#define IFX_ERAY_NDIC3_NDIP77_OFF (13u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP78 */
+#define IFX_ERAY_NDIC3_NDIP78_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP78 */
+#define IFX_ERAY_NDIC3_NDIP78_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP78 */
+#define IFX_ERAY_NDIC3_NDIP78_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP79 */
+#define IFX_ERAY_NDIC3_NDIP79_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP79 */
+#define IFX_ERAY_NDIC3_NDIP79_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP79 */
+#define IFX_ERAY_NDIC3_NDIP79_OFF (15u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP80 */
+#define IFX_ERAY_NDIC3_NDIP80_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP80 */
+#define IFX_ERAY_NDIC3_NDIP80_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP80 */
+#define IFX_ERAY_NDIC3_NDIP80_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP81 */
+#define IFX_ERAY_NDIC3_NDIP81_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP81 */
+#define IFX_ERAY_NDIC3_NDIP81_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP81 */
+#define IFX_ERAY_NDIC3_NDIP81_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP82 */
+#define IFX_ERAY_NDIC3_NDIP82_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP82 */
+#define IFX_ERAY_NDIC3_NDIP82_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP82 */
+#define IFX_ERAY_NDIC3_NDIP82_OFF (18u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP83 */
+#define IFX_ERAY_NDIC3_NDIP83_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP83 */
+#define IFX_ERAY_NDIC3_NDIP83_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP83 */
+#define IFX_ERAY_NDIC3_NDIP83_OFF (19u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP84 */
+#define IFX_ERAY_NDIC3_NDIP84_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP84 */
+#define IFX_ERAY_NDIC3_NDIP84_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP84 */
+#define IFX_ERAY_NDIC3_NDIP84_OFF (20u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP85 */
+#define IFX_ERAY_NDIC3_NDIP85_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP85 */
+#define IFX_ERAY_NDIC3_NDIP85_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP85 */
+#define IFX_ERAY_NDIC3_NDIP85_OFF (21u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP86 */
+#define IFX_ERAY_NDIC3_NDIP86_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP86 */
+#define IFX_ERAY_NDIC3_NDIP86_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP86 */
+#define IFX_ERAY_NDIC3_NDIP86_OFF (22u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP87 */
+#define IFX_ERAY_NDIC3_NDIP87_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP87 */
+#define IFX_ERAY_NDIC3_NDIP87_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP87 */
+#define IFX_ERAY_NDIC3_NDIP87_OFF (23u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP88 */
+#define IFX_ERAY_NDIC3_NDIP88_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP88 */
+#define IFX_ERAY_NDIC3_NDIP88_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP88 */
+#define IFX_ERAY_NDIC3_NDIP88_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP89 */
+#define IFX_ERAY_NDIC3_NDIP89_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP89 */
+#define IFX_ERAY_NDIC3_NDIP89_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP89 */
+#define IFX_ERAY_NDIC3_NDIP89_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP90 */
+#define IFX_ERAY_NDIC3_NDIP90_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP90 */
+#define IFX_ERAY_NDIC3_NDIP90_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP90 */
+#define IFX_ERAY_NDIC3_NDIP90_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP91 */
+#define IFX_ERAY_NDIC3_NDIP91_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP91 */
+#define IFX_ERAY_NDIC3_NDIP91_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP91 */
+#define IFX_ERAY_NDIC3_NDIP91_OFF (27u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP92 */
+#define IFX_ERAY_NDIC3_NDIP92_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP92 */
+#define IFX_ERAY_NDIC3_NDIP92_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP92 */
+#define IFX_ERAY_NDIC3_NDIP92_OFF (28u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP93 */
+#define IFX_ERAY_NDIC3_NDIP93_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP93 */
+#define IFX_ERAY_NDIC3_NDIP93_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP93 */
+#define IFX_ERAY_NDIC3_NDIP93_OFF (29u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP94 */
+#define IFX_ERAY_NDIC3_NDIP94_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP94 */
+#define IFX_ERAY_NDIC3_NDIP94_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP94 */
+#define IFX_ERAY_NDIC3_NDIP94_OFF (30u)
+
+/** \brief Length for Ifx_ERAY_NDIC3_Bits.NDIP95 */
+#define IFX_ERAY_NDIC3_NDIP95_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC3_Bits.NDIP95 */
+#define IFX_ERAY_NDIC3_NDIP95_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC3_Bits.NDIP95 */
+#define IFX_ERAY_NDIC3_NDIP95_OFF (31u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP100 */
+#define IFX_ERAY_NDIC4_NDIP100_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP100 */
+#define IFX_ERAY_NDIC4_NDIP100_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP100 */
+#define IFX_ERAY_NDIC4_NDIP100_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP101 */
+#define IFX_ERAY_NDIC4_NDIP101_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP101 */
+#define IFX_ERAY_NDIC4_NDIP101_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP101 */
+#define IFX_ERAY_NDIC4_NDIP101_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP102 */
+#define IFX_ERAY_NDIC4_NDIP102_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP102 */
+#define IFX_ERAY_NDIC4_NDIP102_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP102 */
+#define IFX_ERAY_NDIC4_NDIP102_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP103 */
+#define IFX_ERAY_NDIC4_NDIP103_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP103 */
+#define IFX_ERAY_NDIC4_NDIP103_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP103 */
+#define IFX_ERAY_NDIC4_NDIP103_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP104 */
+#define IFX_ERAY_NDIC4_NDIP104_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP104 */
+#define IFX_ERAY_NDIC4_NDIP104_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP104 */
+#define IFX_ERAY_NDIC4_NDIP104_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP105 */
+#define IFX_ERAY_NDIC4_NDIP105_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP105 */
+#define IFX_ERAY_NDIC4_NDIP105_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP105 */
+#define IFX_ERAY_NDIC4_NDIP105_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP106 */
+#define IFX_ERAY_NDIC4_NDIP106_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP106 */
+#define IFX_ERAY_NDIC4_NDIP106_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP106 */
+#define IFX_ERAY_NDIC4_NDIP106_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP107 */
+#define IFX_ERAY_NDIC4_NDIP107_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP107 */
+#define IFX_ERAY_NDIC4_NDIP107_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP107 */
+#define IFX_ERAY_NDIC4_NDIP107_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP108 */
+#define IFX_ERAY_NDIC4_NDIP108_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP108 */
+#define IFX_ERAY_NDIC4_NDIP108_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP108 */
+#define IFX_ERAY_NDIC4_NDIP108_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP109 */
+#define IFX_ERAY_NDIC4_NDIP109_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP109 */
+#define IFX_ERAY_NDIC4_NDIP109_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP109 */
+#define IFX_ERAY_NDIC4_NDIP109_OFF (13u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP110 */
+#define IFX_ERAY_NDIC4_NDIP110_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP110 */
+#define IFX_ERAY_NDIC4_NDIP110_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP110 */
+#define IFX_ERAY_NDIC4_NDIP110_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP111 */
+#define IFX_ERAY_NDIC4_NDIP111_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP111 */
+#define IFX_ERAY_NDIC4_NDIP111_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP111 */
+#define IFX_ERAY_NDIC4_NDIP111_OFF (15u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP112 */
+#define IFX_ERAY_NDIC4_NDIP112_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP112 */
+#define IFX_ERAY_NDIC4_NDIP112_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP112 */
+#define IFX_ERAY_NDIC4_NDIP112_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP113 */
+#define IFX_ERAY_NDIC4_NDIP113_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP113 */
+#define IFX_ERAY_NDIC4_NDIP113_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP113 */
+#define IFX_ERAY_NDIC4_NDIP113_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP114 */
+#define IFX_ERAY_NDIC4_NDIP114_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP114 */
+#define IFX_ERAY_NDIC4_NDIP114_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP114 */
+#define IFX_ERAY_NDIC4_NDIP114_OFF (18u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP115 */
+#define IFX_ERAY_NDIC4_NDIP115_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP115 */
+#define IFX_ERAY_NDIC4_NDIP115_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP115 */
+#define IFX_ERAY_NDIC4_NDIP115_OFF (19u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP116 */
+#define IFX_ERAY_NDIC4_NDIP116_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP116 */
+#define IFX_ERAY_NDIC4_NDIP116_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP116 */
+#define IFX_ERAY_NDIC4_NDIP116_OFF (20u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP117 */
+#define IFX_ERAY_NDIC4_NDIP117_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP117 */
+#define IFX_ERAY_NDIC4_NDIP117_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP117 */
+#define IFX_ERAY_NDIC4_NDIP117_OFF (21u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP118 */
+#define IFX_ERAY_NDIC4_NDIP118_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP118 */
+#define IFX_ERAY_NDIC4_NDIP118_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP118 */
+#define IFX_ERAY_NDIC4_NDIP118_OFF (22u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP119 */
+#define IFX_ERAY_NDIC4_NDIP119_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP119 */
+#define IFX_ERAY_NDIC4_NDIP119_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP119 */
+#define IFX_ERAY_NDIC4_NDIP119_OFF (23u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP120 */
+#define IFX_ERAY_NDIC4_NDIP120_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP120 */
+#define IFX_ERAY_NDIC4_NDIP120_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP120 */
+#define IFX_ERAY_NDIC4_NDIP120_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP121 */
+#define IFX_ERAY_NDIC4_NDIP121_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP121 */
+#define IFX_ERAY_NDIC4_NDIP121_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP121 */
+#define IFX_ERAY_NDIC4_NDIP121_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP122 */
+#define IFX_ERAY_NDIC4_NDIP122_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP122 */
+#define IFX_ERAY_NDIC4_NDIP122_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP122 */
+#define IFX_ERAY_NDIC4_NDIP122_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP123 */
+#define IFX_ERAY_NDIC4_NDIP123_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP123 */
+#define IFX_ERAY_NDIC4_NDIP123_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP123 */
+#define IFX_ERAY_NDIC4_NDIP123_OFF (27u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP124 */
+#define IFX_ERAY_NDIC4_NDIP124_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP124 */
+#define IFX_ERAY_NDIC4_NDIP124_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP124 */
+#define IFX_ERAY_NDIC4_NDIP124_OFF (28u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP125 */
+#define IFX_ERAY_NDIC4_NDIP125_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP125 */
+#define IFX_ERAY_NDIC4_NDIP125_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP125 */
+#define IFX_ERAY_NDIC4_NDIP125_OFF (29u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP126 */
+#define IFX_ERAY_NDIC4_NDIP126_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP126 */
+#define IFX_ERAY_NDIC4_NDIP126_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP126 */
+#define IFX_ERAY_NDIC4_NDIP126_OFF (30u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP127 */
+#define IFX_ERAY_NDIC4_NDIP127_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP127 */
+#define IFX_ERAY_NDIC4_NDIP127_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP127 */
+#define IFX_ERAY_NDIC4_NDIP127_OFF (31u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP96 */
+#define IFX_ERAY_NDIC4_NDIP96_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP96 */
+#define IFX_ERAY_NDIC4_NDIP96_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP96 */
+#define IFX_ERAY_NDIC4_NDIP96_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP97 */
+#define IFX_ERAY_NDIC4_NDIP97_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP97 */
+#define IFX_ERAY_NDIC4_NDIP97_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP97 */
+#define IFX_ERAY_NDIC4_NDIP97_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP98 */
+#define IFX_ERAY_NDIC4_NDIP98_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP98 */
+#define IFX_ERAY_NDIC4_NDIP98_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP98 */
+#define IFX_ERAY_NDIC4_NDIP98_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_NDIC4_Bits.NDIP99 */
+#define IFX_ERAY_NDIC4_NDIP99_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_NDIC4_Bits.NDIP99 */
+#define IFX_ERAY_NDIC4_NDIP99_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_NDIC4_Bits.NDIP99 */
+#define IFX_ERAY_NDIC4_NDIP99_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_NEMC_Bits.NML */
+#define IFX_ERAY_NEMC_NML_LEN (4u)
+
+/** \brief Mask for Ifx_ERAY_NEMC_Bits.NML */
+#define IFX_ERAY_NEMC_NML_MSK (0xfu)
+
+/** \brief Offset for Ifx_ERAY_NEMC_Bits.NML */
+#define IFX_ERAY_NEMC_NML_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_NMV_Bits.NM */
+#define IFX_ERAY_NMV_NM_LEN (32u)
+
+/** \brief Mask for Ifx_ERAY_NMV_Bits.NM */
+#define IFX_ERAY_NMV_NM_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ERAY_NMV_Bits.NM */
+#define IFX_ERAY_NMV_NM_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_OBCM_Bits.RDSH */
+#define IFX_ERAY_OBCM_RDSH_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_OBCM_Bits.RDSH */
+#define IFX_ERAY_OBCM_RDSH_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_OBCM_Bits.RDSH */
+#define IFX_ERAY_OBCM_RDSH_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_OBCM_Bits.RDSS */
+#define IFX_ERAY_OBCM_RDSS_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_OBCM_Bits.RDSS */
+#define IFX_ERAY_OBCM_RDSS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_OBCM_Bits.RDSS */
+#define IFX_ERAY_OBCM_RDSS_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_OBCM_Bits.RHSH */
+#define IFX_ERAY_OBCM_RHSH_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_OBCM_Bits.RHSH */
+#define IFX_ERAY_OBCM_RHSH_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_OBCM_Bits.RHSH */
+#define IFX_ERAY_OBCM_RHSH_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_OBCM_Bits.RHSS */
+#define IFX_ERAY_OBCM_RHSS_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_OBCM_Bits.RHSS */
+#define IFX_ERAY_OBCM_RHSS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_OBCM_Bits.RHSS */
+#define IFX_ERAY_OBCM_RHSS_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_OBCR_Bits.OBRH */
+#define IFX_ERAY_OBCR_OBRH_LEN (7u)
+
+/** \brief Mask for Ifx_ERAY_OBCR_Bits.OBRH */
+#define IFX_ERAY_OBCR_OBRH_MSK (0x7fu)
+
+/** \brief Offset for Ifx_ERAY_OBCR_Bits.OBRH */
+#define IFX_ERAY_OBCR_OBRH_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_OBCR_Bits.OBRS */
+#define IFX_ERAY_OBCR_OBRS_LEN (7u)
+
+/** \brief Mask for Ifx_ERAY_OBCR_Bits.OBRS */
+#define IFX_ERAY_OBCR_OBRS_MSK (0x7fu)
+
+/** \brief Offset for Ifx_ERAY_OBCR_Bits.OBRS */
+#define IFX_ERAY_OBCR_OBRS_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_OBCR_Bits.OBSYS */
+#define IFX_ERAY_OBCR_OBSYS_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_OBCR_Bits.OBSYS */
+#define IFX_ERAY_OBCR_OBSYS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_OBCR_Bits.OBSYS */
+#define IFX_ERAY_OBCR_OBSYS_OFF (15u)
+
+/** \brief Length for Ifx_ERAY_OBCR_Bits.REQ */
+#define IFX_ERAY_OBCR_REQ_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_OBCR_Bits.REQ */
+#define IFX_ERAY_OBCR_REQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_OBCR_Bits.REQ */
+#define IFX_ERAY_OBCR_REQ_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_OBCR_Bits.VIEW */
+#define IFX_ERAY_OBCR_VIEW_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_OBCR_Bits.VIEW */
+#define IFX_ERAY_OBCR_VIEW_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_OBCR_Bits.VIEW */
+#define IFX_ERAY_OBCR_VIEW_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_OCS_Bits.SUS */
+#define IFX_ERAY_OCS_SUS_LEN (4u)
+
+/** \brief Mask for Ifx_ERAY_OCS_Bits.SUS */
+#define IFX_ERAY_OCS_SUS_MSK (0xfu)
+
+/** \brief Offset for Ifx_ERAY_OCS_Bits.SUS */
+#define IFX_ERAY_OCS_SUS_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_OCS_Bits.SUS_P */
+#define IFX_ERAY_OCS_SUS_P_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_OCS_Bits.SUS_P */
+#define IFX_ERAY_OCS_SUS_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_OCS_Bits.SUS_P */
+#define IFX_ERAY_OCS_SUS_P_OFF (28u)
+
+/** \brief Length for Ifx_ERAY_OCS_Bits.SUSSTA */
+#define IFX_ERAY_OCS_SUSSTA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_OCS_Bits.SUSSTA */
+#define IFX_ERAY_OCS_SUSSTA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_OCS_Bits.SUSSTA */
+#define IFX_ERAY_OCS_SUSSTA_OFF (29u)
+
+/** \brief Length for Ifx_ERAY_OCV_Bits.OCV */
+#define IFX_ERAY_OCV_OCV_LEN (19u)
+
+/** \brief Mask for Ifx_ERAY_OCV_Bits.OCV */
+#define IFX_ERAY_OCV_OCV_MSK (0x7ffffu)
+
+/** \brief Offset for Ifx_ERAY_OCV_Bits.OCV */
+#define IFX_ERAY_OCV_OCV_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_OSID_Bits.OID */
+#define IFX_ERAY_OSID_OID_LEN (10u)
+
+/** \brief Mask for Ifx_ERAY_OSID_Bits.OID */
+#define IFX_ERAY_OSID_OID_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_ERAY_OSID_Bits.OID */
+#define IFX_ERAY_OSID_OID_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_OSID_Bits.RXOA */
+#define IFX_ERAY_OSID_RXOA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_OSID_Bits.RXOA */
+#define IFX_ERAY_OSID_RXOA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_OSID_Bits.RXOA */
+#define IFX_ERAY_OSID_RXOA_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_OSID_Bits.RXOB */
+#define IFX_ERAY_OSID_RXOB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_OSID_Bits.RXOB */
+#define IFX_ERAY_OSID_RXOB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_OSID_Bits.RXOB */
+#define IFX_ERAY_OSID_RXOB_OFF (15u)
+
+/** \brief Length for Ifx_ERAY_OTSS_Bits.OTGB0 */
+#define IFX_ERAY_OTSS_OTGB0_LEN (2u)
+
+/** \brief Mask for Ifx_ERAY_OTSS_Bits.OTGB0 */
+#define IFX_ERAY_OTSS_OTGB0_MSK (0x3u)
+
+/** \brief Offset for Ifx_ERAY_OTSS_Bits.OTGB0 */
+#define IFX_ERAY_OTSS_OTGB0_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_OTSS_Bits.OTGB1 */
+#define IFX_ERAY_OTSS_OTGB1_LEN (2u)
+
+/** \brief Mask for Ifx_ERAY_OTSS_Bits.OTGB1 */
+#define IFX_ERAY_OTSS_OTGB1_MSK (0x3u)
+
+/** \brief Offset for Ifx_ERAY_OTSS_Bits.OTGB1 */
+#define IFX_ERAY_OTSS_OTGB1_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_OTSS_Bits.OTGB2 */
+#define IFX_ERAY_OTSS_OTGB2_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_OTSS_Bits.OTGB2 */
+#define IFX_ERAY_OTSS_OTGB2_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_OTSS_Bits.OTGB2 */
+#define IFX_ERAY_OTSS_OTGB2_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_PRTC1_Bits.BRP */
+#define IFX_ERAY_PRTC1_BRP_LEN (2u)
+
+/** \brief Mask for Ifx_ERAY_PRTC1_Bits.BRP */
+#define IFX_ERAY_PRTC1_BRP_MSK (0x3u)
+
+/** \brief Offset for Ifx_ERAY_PRTC1_Bits.BRP */
+#define IFX_ERAY_PRTC1_BRP_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_PRTC1_Bits.CASM */
+#define IFX_ERAY_PRTC1_CASM_LEN (7u)
+
+/** \brief Mask for Ifx_ERAY_PRTC1_Bits.CASM */
+#define IFX_ERAY_PRTC1_CASM_MSK (0x7fu)
+
+/** \brief Offset for Ifx_ERAY_PRTC1_Bits.CASM */
+#define IFX_ERAY_PRTC1_CASM_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_PRTC1_Bits.RWP */
+#define IFX_ERAY_PRTC1_RWP_LEN (6u)
+
+/** \brief Mask for Ifx_ERAY_PRTC1_Bits.RWP */
+#define IFX_ERAY_PRTC1_RWP_MSK (0x3fu)
+
+/** \brief Offset for Ifx_ERAY_PRTC1_Bits.RWP */
+#define IFX_ERAY_PRTC1_RWP_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_PRTC1_Bits.RXW */
+#define IFX_ERAY_PRTC1_RXW_LEN (9u)
+
+/** \brief Mask for Ifx_ERAY_PRTC1_Bits.RXW */
+#define IFX_ERAY_PRTC1_RXW_MSK (0x1ffu)
+
+/** \brief Offset for Ifx_ERAY_PRTC1_Bits.RXW */
+#define IFX_ERAY_PRTC1_RXW_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_PRTC1_Bits.SPP */
+#define IFX_ERAY_PRTC1_SPP_LEN (2u)
+
+/** \brief Mask for Ifx_ERAY_PRTC1_Bits.SPP */
+#define IFX_ERAY_PRTC1_SPP_MSK (0x3u)
+
+/** \brief Offset for Ifx_ERAY_PRTC1_Bits.SPP */
+#define IFX_ERAY_PRTC1_SPP_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_PRTC1_Bits.TSST */
+#define IFX_ERAY_PRTC1_TSST_LEN (4u)
+
+/** \brief Mask for Ifx_ERAY_PRTC1_Bits.TSST */
+#define IFX_ERAY_PRTC1_TSST_MSK (0xfu)
+
+/** \brief Offset for Ifx_ERAY_PRTC1_Bits.TSST */
+#define IFX_ERAY_PRTC1_TSST_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_PRTC2_Bits.RXI */
+#define IFX_ERAY_PRTC2_RXI_LEN (6u)
+
+/** \brief Mask for Ifx_ERAY_PRTC2_Bits.RXI */
+#define IFX_ERAY_PRTC2_RXI_MSK (0x3fu)
+
+/** \brief Offset for Ifx_ERAY_PRTC2_Bits.RXI */
+#define IFX_ERAY_PRTC2_RXI_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_PRTC2_Bits.RXL */
+#define IFX_ERAY_PRTC2_RXL_LEN (6u)
+
+/** \brief Mask for Ifx_ERAY_PRTC2_Bits.RXL */
+#define IFX_ERAY_PRTC2_RXL_MSK (0x3fu)
+
+/** \brief Offset for Ifx_ERAY_PRTC2_Bits.RXL */
+#define IFX_ERAY_PRTC2_RXL_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_PRTC2_Bits.TXI */
+#define IFX_ERAY_PRTC2_TXI_LEN (8u)
+
+/** \brief Mask for Ifx_ERAY_PRTC2_Bits.TXI */
+#define IFX_ERAY_PRTC2_TXI_MSK (0xffu)
+
+/** \brief Offset for Ifx_ERAY_PRTC2_Bits.TXI */
+#define IFX_ERAY_PRTC2_TXI_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_PRTC2_Bits.TXL */
+#define IFX_ERAY_PRTC2_TXL_LEN (6u)
+
+/** \brief Mask for Ifx_ERAY_PRTC2_Bits.TXL */
+#define IFX_ERAY_PRTC2_TXL_MSK (0x3fu)
+
+/** \brief Offset for Ifx_ERAY_PRTC2_Bits.TXL */
+#define IFX_ERAY_PRTC2_TXL_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_RCV_Bits.RCV */
+#define IFX_ERAY_RCV_RCV_LEN (12u)
+
+/** \brief Mask for Ifx_ERAY_RCV_Bits.RCV */
+#define IFX_ERAY_RCV_RCV_MSK (0xfffu)
+
+/** \brief Offset for Ifx_ERAY_RCV_Bits.RCV */
+#define IFX_ERAY_RCV_RCV_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_RDDS_Bits.MDRB0 */
+#define IFX_ERAY_RDDS_MDRB0_LEN (8u)
+
+/** \brief Mask for Ifx_ERAY_RDDS_Bits.MDRB0 */
+#define IFX_ERAY_RDDS_MDRB0_MSK (0xffu)
+
+/** \brief Offset for Ifx_ERAY_RDDS_Bits.MDRB0 */
+#define IFX_ERAY_RDDS_MDRB0_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_RDDS_Bits.MDRB1 */
+#define IFX_ERAY_RDDS_MDRB1_LEN (8u)
+
+/** \brief Mask for Ifx_ERAY_RDDS_Bits.MDRB1 */
+#define IFX_ERAY_RDDS_MDRB1_MSK (0xffu)
+
+/** \brief Offset for Ifx_ERAY_RDDS_Bits.MDRB1 */
+#define IFX_ERAY_RDDS_MDRB1_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_RDDS_Bits.MDRB2 */
+#define IFX_ERAY_RDDS_MDRB2_LEN (8u)
+
+/** \brief Mask for Ifx_ERAY_RDDS_Bits.MDRB2 */
+#define IFX_ERAY_RDDS_MDRB2_MSK (0xffu)
+
+/** \brief Offset for Ifx_ERAY_RDDS_Bits.MDRB2 */
+#define IFX_ERAY_RDDS_MDRB2_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_RDDS_Bits.MDRB3 */
+#define IFX_ERAY_RDDS_MDRB3_LEN (8u)
+
+/** \brief Mask for Ifx_ERAY_RDDS_Bits.MDRB3 */
+#define IFX_ERAY_RDDS_MDRB3_MSK (0xffu)
+
+/** \brief Offset for Ifx_ERAY_RDDS_Bits.MDRB3 */
+#define IFX_ERAY_RDDS_MDRB3_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_RDHS1_Bits.CFG */
+#define IFX_ERAY_RDHS1_CFG_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_RDHS1_Bits.CFG */
+#define IFX_ERAY_RDHS1_CFG_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_RDHS1_Bits.CFG */
+#define IFX_ERAY_RDHS1_CFG_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_RDHS1_Bits.CHA */
+#define IFX_ERAY_RDHS1_CHA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_RDHS1_Bits.CHA */
+#define IFX_ERAY_RDHS1_CHA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_RDHS1_Bits.CHA */
+#define IFX_ERAY_RDHS1_CHA_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_RDHS1_Bits.CHB */
+#define IFX_ERAY_RDHS1_CHB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_RDHS1_Bits.CHB */
+#define IFX_ERAY_RDHS1_CHB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_RDHS1_Bits.CHB */
+#define IFX_ERAY_RDHS1_CHB_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_RDHS1_Bits.CYC */
+#define IFX_ERAY_RDHS1_CYC_LEN (7u)
+
+/** \brief Mask for Ifx_ERAY_RDHS1_Bits.CYC */
+#define IFX_ERAY_RDHS1_CYC_MSK (0x7fu)
+
+/** \brief Offset for Ifx_ERAY_RDHS1_Bits.CYC */
+#define IFX_ERAY_RDHS1_CYC_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_RDHS1_Bits.FID */
+#define IFX_ERAY_RDHS1_FID_LEN (11u)
+
+/** \brief Mask for Ifx_ERAY_RDHS1_Bits.FID */
+#define IFX_ERAY_RDHS1_FID_MSK (0x7ffu)
+
+/** \brief Offset for Ifx_ERAY_RDHS1_Bits.FID */
+#define IFX_ERAY_RDHS1_FID_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_RDHS1_Bits.MBI */
+#define IFX_ERAY_RDHS1_MBI_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_RDHS1_Bits.MBI */
+#define IFX_ERAY_RDHS1_MBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_RDHS1_Bits.MBI */
+#define IFX_ERAY_RDHS1_MBI_OFF (29u)
+
+/** \brief Length for Ifx_ERAY_RDHS1_Bits.PPIT */
+#define IFX_ERAY_RDHS1_PPIT_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_RDHS1_Bits.PPIT */
+#define IFX_ERAY_RDHS1_PPIT_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_RDHS1_Bits.PPIT */
+#define IFX_ERAY_RDHS1_PPIT_OFF (27u)
+
+/** \brief Length for Ifx_ERAY_RDHS1_Bits.TXM */
+#define IFX_ERAY_RDHS1_TXM_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_RDHS1_Bits.TXM */
+#define IFX_ERAY_RDHS1_TXM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_RDHS1_Bits.TXM */
+#define IFX_ERAY_RDHS1_TXM_OFF (28u)
+
+/** \brief Length for Ifx_ERAY_RDHS2_Bits.CRC */
+#define IFX_ERAY_RDHS2_CRC_LEN (11u)
+
+/** \brief Mask for Ifx_ERAY_RDHS2_Bits.CRC */
+#define IFX_ERAY_RDHS2_CRC_MSK (0x7ffu)
+
+/** \brief Offset for Ifx_ERAY_RDHS2_Bits.CRC */
+#define IFX_ERAY_RDHS2_CRC_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_RDHS2_Bits.PLC */
+#define IFX_ERAY_RDHS2_PLC_LEN (7u)
+
+/** \brief Mask for Ifx_ERAY_RDHS2_Bits.PLC */
+#define IFX_ERAY_RDHS2_PLC_MSK (0x7fu)
+
+/** \brief Offset for Ifx_ERAY_RDHS2_Bits.PLC */
+#define IFX_ERAY_RDHS2_PLC_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_RDHS2_Bits.PLR */
+#define IFX_ERAY_RDHS2_PLR_LEN (7u)
+
+/** \brief Mask for Ifx_ERAY_RDHS2_Bits.PLR */
+#define IFX_ERAY_RDHS2_PLR_MSK (0x7fu)
+
+/** \brief Offset for Ifx_ERAY_RDHS2_Bits.PLR */
+#define IFX_ERAY_RDHS2_PLR_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_RDHS3_Bits.DP */
+#define IFX_ERAY_RDHS3_DP_LEN (11u)
+
+/** \brief Mask for Ifx_ERAY_RDHS3_Bits.DP */
+#define IFX_ERAY_RDHS3_DP_MSK (0x7ffu)
+
+/** \brief Offset for Ifx_ERAY_RDHS3_Bits.DP */
+#define IFX_ERAY_RDHS3_DP_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_RDHS3_Bits.NFI */
+#define IFX_ERAY_RDHS3_NFI_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_RDHS3_Bits.NFI */
+#define IFX_ERAY_RDHS3_NFI_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_RDHS3_Bits.NFI */
+#define IFX_ERAY_RDHS3_NFI_OFF (27u)
+
+/** \brief Length for Ifx_ERAY_RDHS3_Bits.PPI */
+#define IFX_ERAY_RDHS3_PPI_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_RDHS3_Bits.PPI */
+#define IFX_ERAY_RDHS3_PPI_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_RDHS3_Bits.PPI */
+#define IFX_ERAY_RDHS3_PPI_OFF (28u)
+
+/** \brief Length for Ifx_ERAY_RDHS3_Bits.RCC */
+#define IFX_ERAY_RDHS3_RCC_LEN (6u)
+
+/** \brief Mask for Ifx_ERAY_RDHS3_Bits.RCC */
+#define IFX_ERAY_RDHS3_RCC_MSK (0x3fu)
+
+/** \brief Offset for Ifx_ERAY_RDHS3_Bits.RCC */
+#define IFX_ERAY_RDHS3_RCC_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_RDHS3_Bits.RCI */
+#define IFX_ERAY_RDHS3_RCI_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_RDHS3_Bits.RCI */
+#define IFX_ERAY_RDHS3_RCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_RDHS3_Bits.RCI */
+#define IFX_ERAY_RDHS3_RCI_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_RDHS3_Bits.RES */
+#define IFX_ERAY_RDHS3_RES_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_RDHS3_Bits.RES */
+#define IFX_ERAY_RDHS3_RES_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_RDHS3_Bits.RES */
+#define IFX_ERAY_RDHS3_RES_OFF (29u)
+
+/** \brief Length for Ifx_ERAY_RDHS3_Bits.SFI */
+#define IFX_ERAY_RDHS3_SFI_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_RDHS3_Bits.SFI */
+#define IFX_ERAY_RDHS3_SFI_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_RDHS3_Bits.SFI */
+#define IFX_ERAY_RDHS3_SFI_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_RDHS3_Bits.SYN */
+#define IFX_ERAY_RDHS3_SYN_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_RDHS3_Bits.SYN */
+#define IFX_ERAY_RDHS3_SYN_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_RDHS3_Bits.SYN */
+#define IFX_ERAY_RDHS3_SYN_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_SCV_Bits.SCCA */
+#define IFX_ERAY_SCV_SCCA_LEN (11u)
+
+/** \brief Mask for Ifx_ERAY_SCV_Bits.SCCA */
+#define IFX_ERAY_SCV_SCCA_MSK (0x7ffu)
+
+/** \brief Offset for Ifx_ERAY_SCV_Bits.SCCA */
+#define IFX_ERAY_SCV_SCCA_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_SCV_Bits.SCCB */
+#define IFX_ERAY_SCV_SCCB_LEN (11u)
+
+/** \brief Mask for Ifx_ERAY_SCV_Bits.SCCB */
+#define IFX_ERAY_SCV_SCCB_MSK (0x7ffu)
+
+/** \brief Offset for Ifx_ERAY_SCV_Bits.SCCB */
+#define IFX_ERAY_SCV_SCCB_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_SFS_Bits.MOCS */
+#define IFX_ERAY_SFS_MOCS_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SFS_Bits.MOCS */
+#define IFX_ERAY_SFS_MOCS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SFS_Bits.MOCS */
+#define IFX_ERAY_SFS_MOCS_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_SFS_Bits.MRCS */
+#define IFX_ERAY_SFS_MRCS_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SFS_Bits.MRCS */
+#define IFX_ERAY_SFS_MRCS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SFS_Bits.MRCS */
+#define IFX_ERAY_SFS_MRCS_OFF (18u)
+
+/** \brief Length for Ifx_ERAY_SFS_Bits.OCLR */
+#define IFX_ERAY_SFS_OCLR_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SFS_Bits.OCLR */
+#define IFX_ERAY_SFS_OCLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SFS_Bits.OCLR */
+#define IFX_ERAY_SFS_OCLR_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_SFS_Bits.RCLR */
+#define IFX_ERAY_SFS_RCLR_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SFS_Bits.RCLR */
+#define IFX_ERAY_SFS_RCLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SFS_Bits.RCLR */
+#define IFX_ERAY_SFS_RCLR_OFF (19u)
+
+/** \brief Length for Ifx_ERAY_SFS_Bits.VSAE */
+#define IFX_ERAY_SFS_VSAE_LEN (4u)
+
+/** \brief Mask for Ifx_ERAY_SFS_Bits.VSAE */
+#define IFX_ERAY_SFS_VSAE_MSK (0xfu)
+
+/** \brief Offset for Ifx_ERAY_SFS_Bits.VSAE */
+#define IFX_ERAY_SFS_VSAE_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_SFS_Bits.VSAO */
+#define IFX_ERAY_SFS_VSAO_LEN (4u)
+
+/** \brief Mask for Ifx_ERAY_SFS_Bits.VSAO */
+#define IFX_ERAY_SFS_VSAO_MSK (0xfu)
+
+/** \brief Offset for Ifx_ERAY_SFS_Bits.VSAO */
+#define IFX_ERAY_SFS_VSAO_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_SFS_Bits.VSBE */
+#define IFX_ERAY_SFS_VSBE_LEN (4u)
+
+/** \brief Mask for Ifx_ERAY_SFS_Bits.VSBE */
+#define IFX_ERAY_SFS_VSBE_MSK (0xfu)
+
+/** \brief Offset for Ifx_ERAY_SFS_Bits.VSBE */
+#define IFX_ERAY_SFS_VSBE_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_SFS_Bits.VSBO */
+#define IFX_ERAY_SFS_VSBO_LEN (4u)
+
+/** \brief Mask for Ifx_ERAY_SFS_Bits.VSBO */
+#define IFX_ERAY_SFS_VSBO_MSK (0xfu)
+
+/** \brief Offset for Ifx_ERAY_SFS_Bits.VSBO */
+#define IFX_ERAY_SFS_VSBO_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_SIER_Bits.CASE */
+#define IFX_ERAY_SIER_CASE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIER_Bits.CASE */
+#define IFX_ERAY_SIER_CASE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIER_Bits.CASE */
+#define IFX_ERAY_SIER_CASE_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_SIER_Bits.CYCSE */
+#define IFX_ERAY_SIER_CYCSE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIER_Bits.CYCSE */
+#define IFX_ERAY_SIER_CYCSE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIER_Bits.CYCSE */
+#define IFX_ERAY_SIER_CYCSE_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_SIER_Bits.MBSIE */
+#define IFX_ERAY_SIER_MBSIE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIER_Bits.MBSIE */
+#define IFX_ERAY_SIER_MBSIE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIER_Bits.MBSIE */
+#define IFX_ERAY_SIER_MBSIE_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_SIER_Bits.MTSAE */
+#define IFX_ERAY_SIER_MTSAE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIER_Bits.MTSAE */
+#define IFX_ERAY_SIER_MTSAE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIER_Bits.MTSAE */
+#define IFX_ERAY_SIER_MTSAE_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_SIER_Bits.MTSBE */
+#define IFX_ERAY_SIER_MTSBE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIER_Bits.MTSBE */
+#define IFX_ERAY_SIER_MTSBE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIER_Bits.MTSBE */
+#define IFX_ERAY_SIER_MTSBE_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_SIER_Bits.NMVCE */
+#define IFX_ERAY_SIER_NMVCE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIER_Bits.NMVCE */
+#define IFX_ERAY_SIER_NMVCE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIER_Bits.NMVCE */
+#define IFX_ERAY_SIER_NMVCE_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_SIER_Bits.RFCLE */
+#define IFX_ERAY_SIER_RFCLE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIER_Bits.RFCLE */
+#define IFX_ERAY_SIER_RFCLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIER_Bits.RFCLE */
+#define IFX_ERAY_SIER_RFCLE_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_SIER_Bits.RFNEE */
+#define IFX_ERAY_SIER_RFNEE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIER_Bits.RFNEE */
+#define IFX_ERAY_SIER_RFNEE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIER_Bits.RFNEE */
+#define IFX_ERAY_SIER_RFNEE_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_SIER_Bits.RXIE */
+#define IFX_ERAY_SIER_RXIE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIER_Bits.RXIE */
+#define IFX_ERAY_SIER_RXIE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIER_Bits.RXIE */
+#define IFX_ERAY_SIER_RXIE_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_SIER_Bits.SDSE */
+#define IFX_ERAY_SIER_SDSE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIER_Bits.SDSE */
+#define IFX_ERAY_SIER_SDSE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIER_Bits.SDSE */
+#define IFX_ERAY_SIER_SDSE_OFF (15u)
+
+/** \brief Length for Ifx_ERAY_SIER_Bits.SUCSE */
+#define IFX_ERAY_SIER_SUCSE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIER_Bits.SUCSE */
+#define IFX_ERAY_SIER_SUCSE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIER_Bits.SUCSE */
+#define IFX_ERAY_SIER_SUCSE_OFF (13u)
+
+/** \brief Length for Ifx_ERAY_SIER_Bits.SWEE */
+#define IFX_ERAY_SIER_SWEE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIER_Bits.SWEE */
+#define IFX_ERAY_SIER_SWEE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIER_Bits.SWEE */
+#define IFX_ERAY_SIER_SWEE_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_SIER_Bits.TI0E */
+#define IFX_ERAY_SIER_TI0E_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIER_Bits.TI0E */
+#define IFX_ERAY_SIER_TI0E_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIER_Bits.TI0E */
+#define IFX_ERAY_SIER_TI0E_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_SIER_Bits.TI1E */
+#define IFX_ERAY_SIER_TI1E_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIER_Bits.TI1E */
+#define IFX_ERAY_SIER_TI1E_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIER_Bits.TI1E */
+#define IFX_ERAY_SIER_TI1E_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_SIER_Bits.TIBCE */
+#define IFX_ERAY_SIER_TIBCE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIER_Bits.TIBCE */
+#define IFX_ERAY_SIER_TIBCE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIER_Bits.TIBCE */
+#define IFX_ERAY_SIER_TIBCE_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_SIER_Bits.TOBCE */
+#define IFX_ERAY_SIER_TOBCE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIER_Bits.TOBCE */
+#define IFX_ERAY_SIER_TOBCE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIER_Bits.TOBCE */
+#define IFX_ERAY_SIER_TOBCE_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_SIER_Bits.TXIE */
+#define IFX_ERAY_SIER_TXIE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIER_Bits.TXIE */
+#define IFX_ERAY_SIER_TXIE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIER_Bits.TXIE */
+#define IFX_ERAY_SIER_TXIE_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_SIER_Bits.WSTE */
+#define IFX_ERAY_SIER_WSTE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIER_Bits.WSTE */
+#define IFX_ERAY_SIER_WSTE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIER_Bits.WSTE */
+#define IFX_ERAY_SIER_WSTE_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_SIER_Bits.WUPAE */
+#define IFX_ERAY_SIER_WUPAE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIER_Bits.WUPAE */
+#define IFX_ERAY_SIER_WUPAE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIER_Bits.WUPAE */
+#define IFX_ERAY_SIER_WUPAE_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_SIER_Bits.WUPBE */
+#define IFX_ERAY_SIER_WUPBE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIER_Bits.WUPBE */
+#define IFX_ERAY_SIER_WUPBE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIER_Bits.WUPBE */
+#define IFX_ERAY_SIER_WUPBE_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_SIES_Bits.CASE */
+#define IFX_ERAY_SIES_CASE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIES_Bits.CASE */
+#define IFX_ERAY_SIES_CASE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIES_Bits.CASE */
+#define IFX_ERAY_SIES_CASE_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_SIES_Bits.CYCSE */
+#define IFX_ERAY_SIES_CYCSE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIES_Bits.CYCSE */
+#define IFX_ERAY_SIES_CYCSE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIES_Bits.CYCSE */
+#define IFX_ERAY_SIES_CYCSE_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_SIES_Bits.MBSIE */
+#define IFX_ERAY_SIES_MBSIE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIES_Bits.MBSIE */
+#define IFX_ERAY_SIES_MBSIE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIES_Bits.MBSIE */
+#define IFX_ERAY_SIES_MBSIE_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_SIES_Bits.MTSAE */
+#define IFX_ERAY_SIES_MTSAE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIES_Bits.MTSAE */
+#define IFX_ERAY_SIES_MTSAE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIES_Bits.MTSAE */
+#define IFX_ERAY_SIES_MTSAE_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_SIES_Bits.MTSBE */
+#define IFX_ERAY_SIES_MTSBE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIES_Bits.MTSBE */
+#define IFX_ERAY_SIES_MTSBE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIES_Bits.MTSBE */
+#define IFX_ERAY_SIES_MTSBE_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_SIES_Bits.NMVCE */
+#define IFX_ERAY_SIES_NMVCE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIES_Bits.NMVCE */
+#define IFX_ERAY_SIES_NMVCE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIES_Bits.NMVCE */
+#define IFX_ERAY_SIES_NMVCE_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_SIES_Bits.RFCLE */
+#define IFX_ERAY_SIES_RFCLE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIES_Bits.RFCLE */
+#define IFX_ERAY_SIES_RFCLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIES_Bits.RFCLE */
+#define IFX_ERAY_SIES_RFCLE_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_SIES_Bits.RFNEE */
+#define IFX_ERAY_SIES_RFNEE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIES_Bits.RFNEE */
+#define IFX_ERAY_SIES_RFNEE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIES_Bits.RFNEE */
+#define IFX_ERAY_SIES_RFNEE_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_SIES_Bits.RXIE */
+#define IFX_ERAY_SIES_RXIE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIES_Bits.RXIE */
+#define IFX_ERAY_SIES_RXIE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIES_Bits.RXIE */
+#define IFX_ERAY_SIES_RXIE_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_SIES_Bits.SDSE */
+#define IFX_ERAY_SIES_SDSE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIES_Bits.SDSE */
+#define IFX_ERAY_SIES_SDSE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIES_Bits.SDSE */
+#define IFX_ERAY_SIES_SDSE_OFF (15u)
+
+/** \brief Length for Ifx_ERAY_SIES_Bits.SUCSE */
+#define IFX_ERAY_SIES_SUCSE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIES_Bits.SUCSE */
+#define IFX_ERAY_SIES_SUCSE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIES_Bits.SUCSE */
+#define IFX_ERAY_SIES_SUCSE_OFF (13u)
+
+/** \brief Length for Ifx_ERAY_SIES_Bits.SWEE */
+#define IFX_ERAY_SIES_SWEE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIES_Bits.SWEE */
+#define IFX_ERAY_SIES_SWEE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIES_Bits.SWEE */
+#define IFX_ERAY_SIES_SWEE_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_SIES_Bits.TI0E */
+#define IFX_ERAY_SIES_TI0E_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIES_Bits.TI0E */
+#define IFX_ERAY_SIES_TI0E_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIES_Bits.TI0E */
+#define IFX_ERAY_SIES_TI0E_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_SIES_Bits.TI1E */
+#define IFX_ERAY_SIES_TI1E_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIES_Bits.TI1E */
+#define IFX_ERAY_SIES_TI1E_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIES_Bits.TI1E */
+#define IFX_ERAY_SIES_TI1E_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_SIES_Bits.TIBCE */
+#define IFX_ERAY_SIES_TIBCE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIES_Bits.TIBCE */
+#define IFX_ERAY_SIES_TIBCE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIES_Bits.TIBCE */
+#define IFX_ERAY_SIES_TIBCE_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_SIES_Bits.TOBCE */
+#define IFX_ERAY_SIES_TOBCE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIES_Bits.TOBCE */
+#define IFX_ERAY_SIES_TOBCE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIES_Bits.TOBCE */
+#define IFX_ERAY_SIES_TOBCE_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_SIES_Bits.TXIE */
+#define IFX_ERAY_SIES_TXIE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIES_Bits.TXIE */
+#define IFX_ERAY_SIES_TXIE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIES_Bits.TXIE */
+#define IFX_ERAY_SIES_TXIE_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_SIES_Bits.WSTE */
+#define IFX_ERAY_SIES_WSTE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIES_Bits.WSTE */
+#define IFX_ERAY_SIES_WSTE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIES_Bits.WSTE */
+#define IFX_ERAY_SIES_WSTE_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_SIES_Bits.WUPAE */
+#define IFX_ERAY_SIES_WUPAE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIES_Bits.WUPAE */
+#define IFX_ERAY_SIES_WUPAE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIES_Bits.WUPAE */
+#define IFX_ERAY_SIES_WUPAE_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_SIES_Bits.WUPBE */
+#define IFX_ERAY_SIES_WUPBE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIES_Bits.WUPBE */
+#define IFX_ERAY_SIES_WUPBE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIES_Bits.WUPBE */
+#define IFX_ERAY_SIES_WUPBE_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_SILS_Bits.CASL */
+#define IFX_ERAY_SILS_CASL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SILS_Bits.CASL */
+#define IFX_ERAY_SILS_CASL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SILS_Bits.CASL */
+#define IFX_ERAY_SILS_CASL_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_SILS_Bits.CYCSL */
+#define IFX_ERAY_SILS_CYCSL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SILS_Bits.CYCSL */
+#define IFX_ERAY_SILS_CYCSL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SILS_Bits.CYCSL */
+#define IFX_ERAY_SILS_CYCSL_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_SILS_Bits.MBSIL */
+#define IFX_ERAY_SILS_MBSIL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SILS_Bits.MBSIL */
+#define IFX_ERAY_SILS_MBSIL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SILS_Bits.MBSIL */
+#define IFX_ERAY_SILS_MBSIL_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_SILS_Bits.MTSAL */
+#define IFX_ERAY_SILS_MTSAL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SILS_Bits.MTSAL */
+#define IFX_ERAY_SILS_MTSAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SILS_Bits.MTSAL */
+#define IFX_ERAY_SILS_MTSAL_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_SILS_Bits.MTSBL */
+#define IFX_ERAY_SILS_MTSBL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SILS_Bits.MTSBL */
+#define IFX_ERAY_SILS_MTSBL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SILS_Bits.MTSBL */
+#define IFX_ERAY_SILS_MTSBL_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_SILS_Bits.NMVCL */
+#define IFX_ERAY_SILS_NMVCL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SILS_Bits.NMVCL */
+#define IFX_ERAY_SILS_NMVCL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SILS_Bits.NMVCL */
+#define IFX_ERAY_SILS_NMVCL_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_SILS_Bits.RFCLL */
+#define IFX_ERAY_SILS_RFCLL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SILS_Bits.RFCLL */
+#define IFX_ERAY_SILS_RFCLL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SILS_Bits.RFCLL */
+#define IFX_ERAY_SILS_RFCLL_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_SILS_Bits.RFNEL */
+#define IFX_ERAY_SILS_RFNEL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SILS_Bits.RFNEL */
+#define IFX_ERAY_SILS_RFNEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SILS_Bits.RFNEL */
+#define IFX_ERAY_SILS_RFNEL_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_SILS_Bits.RXIL */
+#define IFX_ERAY_SILS_RXIL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SILS_Bits.RXIL */
+#define IFX_ERAY_SILS_RXIL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SILS_Bits.RXIL */
+#define IFX_ERAY_SILS_RXIL_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_SILS_Bits.SDSL */
+#define IFX_ERAY_SILS_SDSL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SILS_Bits.SDSL */
+#define IFX_ERAY_SILS_SDSL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SILS_Bits.SDSL */
+#define IFX_ERAY_SILS_SDSL_OFF (15u)
+
+/** \brief Length for Ifx_ERAY_SILS_Bits.SUCSL */
+#define IFX_ERAY_SILS_SUCSL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SILS_Bits.SUCSL */
+#define IFX_ERAY_SILS_SUCSL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SILS_Bits.SUCSL */
+#define IFX_ERAY_SILS_SUCSL_OFF (13u)
+
+/** \brief Length for Ifx_ERAY_SILS_Bits.SWEL */
+#define IFX_ERAY_SILS_SWEL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SILS_Bits.SWEL */
+#define IFX_ERAY_SILS_SWEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SILS_Bits.SWEL */
+#define IFX_ERAY_SILS_SWEL_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_SILS_Bits.TI0L */
+#define IFX_ERAY_SILS_TI0L_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SILS_Bits.TI0L */
+#define IFX_ERAY_SILS_TI0L_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SILS_Bits.TI0L */
+#define IFX_ERAY_SILS_TI0L_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_SILS_Bits.TI1L */
+#define IFX_ERAY_SILS_TI1L_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SILS_Bits.TI1L */
+#define IFX_ERAY_SILS_TI1L_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SILS_Bits.TI1L */
+#define IFX_ERAY_SILS_TI1L_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_SILS_Bits.TIBCL */
+#define IFX_ERAY_SILS_TIBCL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SILS_Bits.TIBCL */
+#define IFX_ERAY_SILS_TIBCL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SILS_Bits.TIBCL */
+#define IFX_ERAY_SILS_TIBCL_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_SILS_Bits.TOBCL */
+#define IFX_ERAY_SILS_TOBCL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SILS_Bits.TOBCL */
+#define IFX_ERAY_SILS_TOBCL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SILS_Bits.TOBCL */
+#define IFX_ERAY_SILS_TOBCL_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_SILS_Bits.TXIL */
+#define IFX_ERAY_SILS_TXIL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SILS_Bits.TXIL */
+#define IFX_ERAY_SILS_TXIL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SILS_Bits.TXIL */
+#define IFX_ERAY_SILS_TXIL_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_SILS_Bits.WSTL */
+#define IFX_ERAY_SILS_WSTL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SILS_Bits.WSTL */
+#define IFX_ERAY_SILS_WSTL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SILS_Bits.WSTL */
+#define IFX_ERAY_SILS_WSTL_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_SILS_Bits.WUPAL */
+#define IFX_ERAY_SILS_WUPAL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SILS_Bits.WUPAL */
+#define IFX_ERAY_SILS_WUPAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SILS_Bits.WUPAL */
+#define IFX_ERAY_SILS_WUPAL_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_SILS_Bits.WUPBL */
+#define IFX_ERAY_SILS_WUPBL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SILS_Bits.WUPBL */
+#define IFX_ERAY_SILS_WUPBL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SILS_Bits.WUPBL */
+#define IFX_ERAY_SILS_WUPBL_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_SIR_Bits.CAS */
+#define IFX_ERAY_SIR_CAS_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIR_Bits.CAS */
+#define IFX_ERAY_SIR_CAS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIR_Bits.CAS */
+#define IFX_ERAY_SIR_CAS_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_SIR_Bits.CYCS */
+#define IFX_ERAY_SIR_CYCS_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIR_Bits.CYCS */
+#define IFX_ERAY_SIR_CYCS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIR_Bits.CYCS */
+#define IFX_ERAY_SIR_CYCS_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_SIR_Bits.MBSI */
+#define IFX_ERAY_SIR_MBSI_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIR_Bits.MBSI */
+#define IFX_ERAY_SIR_MBSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIR_Bits.MBSI */
+#define IFX_ERAY_SIR_MBSI_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_SIR_Bits.MTSA */
+#define IFX_ERAY_SIR_MTSA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIR_Bits.MTSA */
+#define IFX_ERAY_SIR_MTSA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIR_Bits.MTSA */
+#define IFX_ERAY_SIR_MTSA_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_SIR_Bits.MTSB */
+#define IFX_ERAY_SIR_MTSB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIR_Bits.MTSB */
+#define IFX_ERAY_SIR_MTSB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIR_Bits.MTSB */
+#define IFX_ERAY_SIR_MTSB_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_SIR_Bits.NMVC */
+#define IFX_ERAY_SIR_NMVC_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIR_Bits.NMVC */
+#define IFX_ERAY_SIR_NMVC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIR_Bits.NMVC */
+#define IFX_ERAY_SIR_NMVC_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_SIR_Bits.RFCL */
+#define IFX_ERAY_SIR_RFCL_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIR_Bits.RFCL */
+#define IFX_ERAY_SIR_RFCL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIR_Bits.RFCL */
+#define IFX_ERAY_SIR_RFCL_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_SIR_Bits.RFNE */
+#define IFX_ERAY_SIR_RFNE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIR_Bits.RFNE */
+#define IFX_ERAY_SIR_RFNE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIR_Bits.RFNE */
+#define IFX_ERAY_SIR_RFNE_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_SIR_Bits.RXI */
+#define IFX_ERAY_SIR_RXI_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIR_Bits.RXI */
+#define IFX_ERAY_SIR_RXI_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIR_Bits.RXI */
+#define IFX_ERAY_SIR_RXI_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_SIR_Bits.SDS */
+#define IFX_ERAY_SIR_SDS_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIR_Bits.SDS */
+#define IFX_ERAY_SIR_SDS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIR_Bits.SDS */
+#define IFX_ERAY_SIR_SDS_OFF (15u)
+
+/** \brief Length for Ifx_ERAY_SIR_Bits.SUCS */
+#define IFX_ERAY_SIR_SUCS_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIR_Bits.SUCS */
+#define IFX_ERAY_SIR_SUCS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIR_Bits.SUCS */
+#define IFX_ERAY_SIR_SUCS_OFF (13u)
+
+/** \brief Length for Ifx_ERAY_SIR_Bits.SWE */
+#define IFX_ERAY_SIR_SWE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIR_Bits.SWE */
+#define IFX_ERAY_SIR_SWE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIR_Bits.SWE */
+#define IFX_ERAY_SIR_SWE_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_SIR_Bits.TI0 */
+#define IFX_ERAY_SIR_TI0_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIR_Bits.TI0 */
+#define IFX_ERAY_SIR_TI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIR_Bits.TI0 */
+#define IFX_ERAY_SIR_TI0_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_SIR_Bits.TI1 */
+#define IFX_ERAY_SIR_TI1_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIR_Bits.TI1 */
+#define IFX_ERAY_SIR_TI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIR_Bits.TI1 */
+#define IFX_ERAY_SIR_TI1_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_SIR_Bits.TIBC */
+#define IFX_ERAY_SIR_TIBC_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIR_Bits.TIBC */
+#define IFX_ERAY_SIR_TIBC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIR_Bits.TIBC */
+#define IFX_ERAY_SIR_TIBC_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_SIR_Bits.TOBC */
+#define IFX_ERAY_SIR_TOBC_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIR_Bits.TOBC */
+#define IFX_ERAY_SIR_TOBC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIR_Bits.TOBC */
+#define IFX_ERAY_SIR_TOBC_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_SIR_Bits.TXI */
+#define IFX_ERAY_SIR_TXI_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIR_Bits.TXI */
+#define IFX_ERAY_SIR_TXI_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIR_Bits.TXI */
+#define IFX_ERAY_SIR_TXI_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_SIR_Bits.WST */
+#define IFX_ERAY_SIR_WST_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIR_Bits.WST */
+#define IFX_ERAY_SIR_WST_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIR_Bits.WST */
+#define IFX_ERAY_SIR_WST_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_SIR_Bits.WUPA */
+#define IFX_ERAY_SIR_WUPA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIR_Bits.WUPA */
+#define IFX_ERAY_SIR_WUPA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIR_Bits.WUPA */
+#define IFX_ERAY_SIR_WUPA_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_SIR_Bits.WUPB */
+#define IFX_ERAY_SIR_WUPB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SIR_Bits.WUPB */
+#define IFX_ERAY_SIR_WUPB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SIR_Bits.WUPB */
+#define IFX_ERAY_SIR_WUPB_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_STPW1_Bits.EDGE */
+#define IFX_ERAY_STPW1_EDGE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_STPW1_Bits.EDGE */
+#define IFX_ERAY_STPW1_EDGE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_STPW1_Bits.EDGE */
+#define IFX_ERAY_STPW1_EDGE_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_STPW1_Bits.EETP */
+#define IFX_ERAY_STPW1_EETP_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_STPW1_Bits.EETP */
+#define IFX_ERAY_STPW1_EETP_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_STPW1_Bits.EETP */
+#define IFX_ERAY_STPW1_EETP_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_STPW1_Bits.EINT0 */
+#define IFX_ERAY_STPW1_EINT0_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_STPW1_Bits.EINT0 */
+#define IFX_ERAY_STPW1_EINT0_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_STPW1_Bits.EINT0 */
+#define IFX_ERAY_STPW1_EINT0_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_STPW1_Bits.EINT1 */
+#define IFX_ERAY_STPW1_EINT1_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_STPW1_Bits.EINT1 */
+#define IFX_ERAY_STPW1_EINT1_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_STPW1_Bits.EINT1 */
+#define IFX_ERAY_STPW1_EINT1_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_STPW1_Bits.ESWT */
+#define IFX_ERAY_STPW1_ESWT_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_STPW1_Bits.ESWT */
+#define IFX_ERAY_STPW1_ESWT_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_STPW1_Bits.ESWT */
+#define IFX_ERAY_STPW1_ESWT_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_STPW1_Bits.SCCV */
+#define IFX_ERAY_STPW1_SCCV_LEN (6u)
+
+/** \brief Mask for Ifx_ERAY_STPW1_Bits.SCCV */
+#define IFX_ERAY_STPW1_SCCV_MSK (0x3fu)
+
+/** \brief Offset for Ifx_ERAY_STPW1_Bits.SCCV */
+#define IFX_ERAY_STPW1_SCCV_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_STPW1_Bits.SMTV */
+#define IFX_ERAY_STPW1_SMTV_LEN (14u)
+
+/** \brief Mask for Ifx_ERAY_STPW1_Bits.SMTV */
+#define IFX_ERAY_STPW1_SMTV_MSK (0x3fffu)
+
+/** \brief Offset for Ifx_ERAY_STPW1_Bits.SMTV */
+#define IFX_ERAY_STPW1_SMTV_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_STPW1_Bits.SSWT */
+#define IFX_ERAY_STPW1_SSWT_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_STPW1_Bits.SSWT */
+#define IFX_ERAY_STPW1_SSWT_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_STPW1_Bits.SSWT */
+#define IFX_ERAY_STPW1_SSWT_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_STPW1_Bits.SWMS */
+#define IFX_ERAY_STPW1_SWMS_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_STPW1_Bits.SWMS */
+#define IFX_ERAY_STPW1_SWMS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_STPW1_Bits.SWMS */
+#define IFX_ERAY_STPW1_SWMS_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_STPW2_Bits.SSCVA */
+#define IFX_ERAY_STPW2_SSCVA_LEN (11u)
+
+/** \brief Mask for Ifx_ERAY_STPW2_Bits.SSCVA */
+#define IFX_ERAY_STPW2_SSCVA_MSK (0x7ffu)
+
+/** \brief Offset for Ifx_ERAY_STPW2_Bits.SSCVA */
+#define IFX_ERAY_STPW2_SSCVA_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_STPW2_Bits.SSCVB */
+#define IFX_ERAY_STPW2_SSCVB_LEN (11u)
+
+/** \brief Mask for Ifx_ERAY_STPW2_Bits.SSCVB */
+#define IFX_ERAY_STPW2_SSCVB_MSK (0x7ffu)
+
+/** \brief Offset for Ifx_ERAY_STPW2_Bits.SSCVB */
+#define IFX_ERAY_STPW2_SSCVB_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_SUCC1_Bits.CCHA */
+#define IFX_ERAY_SUCC1_CCHA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SUCC1_Bits.CCHA */
+#define IFX_ERAY_SUCC1_CCHA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SUCC1_Bits.CCHA */
+#define IFX_ERAY_SUCC1_CCHA_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_SUCC1_Bits.CCHB */
+#define IFX_ERAY_SUCC1_CCHB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SUCC1_Bits.CCHB */
+#define IFX_ERAY_SUCC1_CCHB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SUCC1_Bits.CCHB */
+#define IFX_ERAY_SUCC1_CCHB_OFF (27u)
+
+/** \brief Length for Ifx_ERAY_SUCC1_Bits.CMD */
+#define IFX_ERAY_SUCC1_CMD_LEN (4u)
+
+/** \brief Mask for Ifx_ERAY_SUCC1_Bits.CMD */
+#define IFX_ERAY_SUCC1_CMD_MSK (0xfu)
+
+/** \brief Offset for Ifx_ERAY_SUCC1_Bits.CMD */
+#define IFX_ERAY_SUCC1_CMD_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_SUCC1_Bits.CSA */
+#define IFX_ERAY_SUCC1_CSA_LEN (5u)
+
+/** \brief Mask for Ifx_ERAY_SUCC1_Bits.CSA */
+#define IFX_ERAY_SUCC1_CSA_MSK (0x1fu)
+
+/** \brief Offset for Ifx_ERAY_SUCC1_Bits.CSA */
+#define IFX_ERAY_SUCC1_CSA_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_SUCC1_Bits.HCSE */
+#define IFX_ERAY_SUCC1_HCSE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SUCC1_Bits.HCSE */
+#define IFX_ERAY_SUCC1_HCSE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SUCC1_Bits.HCSE */
+#define IFX_ERAY_SUCC1_HCSE_OFF (23u)
+
+/** \brief Length for Ifx_ERAY_SUCC1_Bits.MTSA */
+#define IFX_ERAY_SUCC1_MTSA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SUCC1_Bits.MTSA */
+#define IFX_ERAY_SUCC1_MTSA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SUCC1_Bits.MTSA */
+#define IFX_ERAY_SUCC1_MTSA_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_SUCC1_Bits.MTSB */
+#define IFX_ERAY_SUCC1_MTSB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SUCC1_Bits.MTSB */
+#define IFX_ERAY_SUCC1_MTSB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SUCC1_Bits.MTSB */
+#define IFX_ERAY_SUCC1_MTSB_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_SUCC1_Bits.PBSY */
+#define IFX_ERAY_SUCC1_PBSY_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SUCC1_Bits.PBSY */
+#define IFX_ERAY_SUCC1_PBSY_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SUCC1_Bits.PBSY */
+#define IFX_ERAY_SUCC1_PBSY_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_SUCC1_Bits.PTA */
+#define IFX_ERAY_SUCC1_PTA_LEN (5u)
+
+/** \brief Mask for Ifx_ERAY_SUCC1_Bits.PTA */
+#define IFX_ERAY_SUCC1_PTA_MSK (0x1fu)
+
+/** \brief Offset for Ifx_ERAY_SUCC1_Bits.PTA */
+#define IFX_ERAY_SUCC1_PTA_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_SUCC1_Bits.TSM */
+#define IFX_ERAY_SUCC1_TSM_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SUCC1_Bits.TSM */
+#define IFX_ERAY_SUCC1_TSM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SUCC1_Bits.TSM */
+#define IFX_ERAY_SUCC1_TSM_OFF (22u)
+
+/** \brief Length for Ifx_ERAY_SUCC1_Bits.TXST */
+#define IFX_ERAY_SUCC1_TXST_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SUCC1_Bits.TXST */
+#define IFX_ERAY_SUCC1_TXST_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SUCC1_Bits.TXST */
+#define IFX_ERAY_SUCC1_TXST_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_SUCC1_Bits.TXSY */
+#define IFX_ERAY_SUCC1_TXSY_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SUCC1_Bits.TXSY */
+#define IFX_ERAY_SUCC1_TXSY_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SUCC1_Bits.TXSY */
+#define IFX_ERAY_SUCC1_TXSY_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_SUCC1_Bits.WUCS */
+#define IFX_ERAY_SUCC1_WUCS_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SUCC1_Bits.WUCS */
+#define IFX_ERAY_SUCC1_WUCS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SUCC1_Bits.WUCS */
+#define IFX_ERAY_SUCC1_WUCS_OFF (21u)
+
+/** \brief Length for Ifx_ERAY_SUCC2_Bits.LT */
+#define IFX_ERAY_SUCC2_LT_LEN (21u)
+
+/** \brief Mask for Ifx_ERAY_SUCC2_Bits.LT */
+#define IFX_ERAY_SUCC2_LT_MSK (0x1fffffu)
+
+/** \brief Offset for Ifx_ERAY_SUCC2_Bits.LT */
+#define IFX_ERAY_SUCC2_LT_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_SUCC2_Bits.LTN */
+#define IFX_ERAY_SUCC2_LTN_LEN (4u)
+
+/** \brief Mask for Ifx_ERAY_SUCC2_Bits.LTN */
+#define IFX_ERAY_SUCC2_LTN_MSK (0xfu)
+
+/** \brief Offset for Ifx_ERAY_SUCC2_Bits.LTN */
+#define IFX_ERAY_SUCC2_LTN_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_SUCC3_Bits.WCF */
+#define IFX_ERAY_SUCC3_WCF_LEN (4u)
+
+/** \brief Mask for Ifx_ERAY_SUCC3_Bits.WCF */
+#define IFX_ERAY_SUCC3_WCF_MSK (0xfu)
+
+/** \brief Offset for Ifx_ERAY_SUCC3_Bits.WCF */
+#define IFX_ERAY_SUCC3_WCF_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_SUCC3_Bits.WCP */
+#define IFX_ERAY_SUCC3_WCP_LEN (4u)
+
+/** \brief Mask for Ifx_ERAY_SUCC3_Bits.WCP */
+#define IFX_ERAY_SUCC3_WCP_MSK (0xfu)
+
+/** \brief Offset for Ifx_ERAY_SUCC3_Bits.WCP */
+#define IFX_ERAY_SUCC3_WCP_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_SWNIT_Bits.MTSA */
+#define IFX_ERAY_SWNIT_MTSA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SWNIT_Bits.MTSA */
+#define IFX_ERAY_SWNIT_MTSA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SWNIT_Bits.MTSA */
+#define IFX_ERAY_SWNIT_MTSA_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_SWNIT_Bits.MTSB */
+#define IFX_ERAY_SWNIT_MTSB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SWNIT_Bits.MTSB */
+#define IFX_ERAY_SWNIT_MTSB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SWNIT_Bits.MTSB */
+#define IFX_ERAY_SWNIT_MTSB_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_SWNIT_Bits.SBNA */
+#define IFX_ERAY_SWNIT_SBNA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SWNIT_Bits.SBNA */
+#define IFX_ERAY_SWNIT_SBNA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SWNIT_Bits.SBNA */
+#define IFX_ERAY_SWNIT_SBNA_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_SWNIT_Bits.SBNB */
+#define IFX_ERAY_SWNIT_SBNB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SWNIT_Bits.SBNB */
+#define IFX_ERAY_SWNIT_SBNB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SWNIT_Bits.SBNB */
+#define IFX_ERAY_SWNIT_SBNB_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_SWNIT_Bits.SBSA */
+#define IFX_ERAY_SWNIT_SBSA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SWNIT_Bits.SBSA */
+#define IFX_ERAY_SWNIT_SBSA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SWNIT_Bits.SBSA */
+#define IFX_ERAY_SWNIT_SBSA_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_SWNIT_Bits.SBSB */
+#define IFX_ERAY_SWNIT_SBSB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SWNIT_Bits.SBSB */
+#define IFX_ERAY_SWNIT_SBSB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SWNIT_Bits.SBSB */
+#define IFX_ERAY_SWNIT_SBSB_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_SWNIT_Bits.SENA */
+#define IFX_ERAY_SWNIT_SENA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SWNIT_Bits.SENA */
+#define IFX_ERAY_SWNIT_SENA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SWNIT_Bits.SENA */
+#define IFX_ERAY_SWNIT_SENA_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_SWNIT_Bits.SENB */
+#define IFX_ERAY_SWNIT_SENB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SWNIT_Bits.SENB */
+#define IFX_ERAY_SWNIT_SENB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SWNIT_Bits.SENB */
+#define IFX_ERAY_SWNIT_SENB_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_SWNIT_Bits.SESA */
+#define IFX_ERAY_SWNIT_SESA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SWNIT_Bits.SESA */
+#define IFX_ERAY_SWNIT_SESA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SWNIT_Bits.SESA */
+#define IFX_ERAY_SWNIT_SESA_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_SWNIT_Bits.SESB */
+#define IFX_ERAY_SWNIT_SESB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SWNIT_Bits.SESB */
+#define IFX_ERAY_SWNIT_SESB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SWNIT_Bits.SESB */
+#define IFX_ERAY_SWNIT_SESB_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_SWNIT_Bits.TCSA */
+#define IFX_ERAY_SWNIT_TCSA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SWNIT_Bits.TCSA */
+#define IFX_ERAY_SWNIT_TCSA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SWNIT_Bits.TCSA */
+#define IFX_ERAY_SWNIT_TCSA_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_SWNIT_Bits.TCSB */
+#define IFX_ERAY_SWNIT_TCSB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_SWNIT_Bits.TCSB */
+#define IFX_ERAY_SWNIT_TCSB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_SWNIT_Bits.TCSB */
+#define IFX_ERAY_SWNIT_TCSB_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_T0C_Bits.T0CC */
+#define IFX_ERAY_T0C_T0CC_LEN (7u)
+
+/** \brief Mask for Ifx_ERAY_T0C_Bits.T0CC */
+#define IFX_ERAY_T0C_T0CC_MSK (0x7fu)
+
+/** \brief Offset for Ifx_ERAY_T0C_Bits.T0CC */
+#define IFX_ERAY_T0C_T0CC_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_T0C_Bits.T0MO */
+#define IFX_ERAY_T0C_T0MO_LEN (14u)
+
+/** \brief Mask for Ifx_ERAY_T0C_Bits.T0MO */
+#define IFX_ERAY_T0C_T0MO_MSK (0x3fffu)
+
+/** \brief Offset for Ifx_ERAY_T0C_Bits.T0MO */
+#define IFX_ERAY_T0C_T0MO_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_T0C_Bits.T0MS */
+#define IFX_ERAY_T0C_T0MS_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_T0C_Bits.T0MS */
+#define IFX_ERAY_T0C_T0MS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_T0C_Bits.T0MS */
+#define IFX_ERAY_T0C_T0MS_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_T0C_Bits.T0RC */
+#define IFX_ERAY_T0C_T0RC_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_T0C_Bits.T0RC */
+#define IFX_ERAY_T0C_T0RC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_T0C_Bits.T0RC */
+#define IFX_ERAY_T0C_T0RC_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_T1C_Bits.T1MC */
+#define IFX_ERAY_T1C_T1MC_LEN (14u)
+
+/** \brief Mask for Ifx_ERAY_T1C_Bits.T1MC */
+#define IFX_ERAY_T1C_T1MC_MSK (0x3fffu)
+
+/** \brief Offset for Ifx_ERAY_T1C_Bits.T1MC */
+#define IFX_ERAY_T1C_T1MC_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_T1C_Bits.T1MS */
+#define IFX_ERAY_T1C_T1MS_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_T1C_Bits.T1MS */
+#define IFX_ERAY_T1C_T1MS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_T1C_Bits.T1MS */
+#define IFX_ERAY_T1C_T1MS_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_T1C_Bits.T1RC */
+#define IFX_ERAY_T1C_T1RC_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_T1C_Bits.T1RC */
+#define IFX_ERAY_T1C_T1RC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_T1C_Bits.T1RC */
+#define IFX_ERAY_T1C_T1RC_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_TEST1_Bits.AOA */
+#define IFX_ERAY_TEST1_AOA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TEST1_Bits.AOA */
+#define IFX_ERAY_TEST1_AOA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TEST1_Bits.AOA */
+#define IFX_ERAY_TEST1_AOA_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_TEST1_Bits.AOB */
+#define IFX_ERAY_TEST1_AOB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TEST1_Bits.AOB */
+#define IFX_ERAY_TEST1_AOB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TEST1_Bits.AOB */
+#define IFX_ERAY_TEST1_AOB_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_TEST1_Bits.CERA */
+#define IFX_ERAY_TEST1_CERA_LEN (4u)
+
+/** \brief Mask for Ifx_ERAY_TEST1_Bits.CERA */
+#define IFX_ERAY_TEST1_CERA_MSK (0xfu)
+
+/** \brief Offset for Ifx_ERAY_TEST1_Bits.CERA */
+#define IFX_ERAY_TEST1_CERA_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_TEST1_Bits.CERB */
+#define IFX_ERAY_TEST1_CERB_LEN (4u)
+
+/** \brief Mask for Ifx_ERAY_TEST1_Bits.CERB */
+#define IFX_ERAY_TEST1_CERB_MSK (0xfu)
+
+/** \brief Offset for Ifx_ERAY_TEST1_Bits.CERB */
+#define IFX_ERAY_TEST1_CERB_OFF (28u)
+
+/** \brief Length for Ifx_ERAY_TEST1_Bits.ELBE */
+#define IFX_ERAY_TEST1_ELBE_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TEST1_Bits.ELBE */
+#define IFX_ERAY_TEST1_ELBE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TEST1_Bits.ELBE */
+#define IFX_ERAY_TEST1_ELBE_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_TEST1_Bits.RXA */
+#define IFX_ERAY_TEST1_RXA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TEST1_Bits.RXA */
+#define IFX_ERAY_TEST1_RXA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TEST1_Bits.RXA */
+#define IFX_ERAY_TEST1_RXA_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_TEST1_Bits.RXB */
+#define IFX_ERAY_TEST1_RXB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TEST1_Bits.RXB */
+#define IFX_ERAY_TEST1_RXB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TEST1_Bits.RXB */
+#define IFX_ERAY_TEST1_RXB_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_TEST1_Bits.TMC */
+#define IFX_ERAY_TEST1_TMC_LEN (2u)
+
+/** \brief Mask for Ifx_ERAY_TEST1_Bits.TMC */
+#define IFX_ERAY_TEST1_TMC_MSK (0x3u)
+
+/** \brief Offset for Ifx_ERAY_TEST1_Bits.TMC */
+#define IFX_ERAY_TEST1_TMC_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_TEST1_Bits.TXA */
+#define IFX_ERAY_TEST1_TXA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TEST1_Bits.TXA */
+#define IFX_ERAY_TEST1_TXA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TEST1_Bits.TXA */
+#define IFX_ERAY_TEST1_TXA_OFF (18u)
+
+/** \brief Length for Ifx_ERAY_TEST1_Bits.TXB */
+#define IFX_ERAY_TEST1_TXB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TEST1_Bits.TXB */
+#define IFX_ERAY_TEST1_TXB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TEST1_Bits.TXB */
+#define IFX_ERAY_TEST1_TXB_OFF (19u)
+
+/** \brief Length for Ifx_ERAY_TEST1_Bits.TXENA */
+#define IFX_ERAY_TEST1_TXENA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TEST1_Bits.TXENA */
+#define IFX_ERAY_TEST1_TXENA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TEST1_Bits.TXENA */
+#define IFX_ERAY_TEST1_TXENA_OFF (20u)
+
+/** \brief Length for Ifx_ERAY_TEST1_Bits.TXENB */
+#define IFX_ERAY_TEST1_TXENB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TEST1_Bits.TXENB */
+#define IFX_ERAY_TEST1_TXENB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TEST1_Bits.TXENB */
+#define IFX_ERAY_TEST1_TXENB_OFF (21u)
+
+/** \brief Length for Ifx_ERAY_TEST1_Bits.WRTEN */
+#define IFX_ERAY_TEST1_WRTEN_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TEST1_Bits.WRTEN */
+#define IFX_ERAY_TEST1_WRTEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TEST1_Bits.WRTEN */
+#define IFX_ERAY_TEST1_WRTEN_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_TEST2_Bits.RS */
+#define IFX_ERAY_TEST2_RS_LEN (3u)
+
+/** \brief Mask for Ifx_ERAY_TEST2_Bits.RS */
+#define IFX_ERAY_TEST2_RS_MSK (0x7u)
+
+/** \brief Offset for Ifx_ERAY_TEST2_Bits.RS */
+#define IFX_ERAY_TEST2_RS_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_TEST2_Bits.SSEL */
+#define IFX_ERAY_TEST2_SSEL_LEN (3u)
+
+/** \brief Mask for Ifx_ERAY_TEST2_Bits.SSEL */
+#define IFX_ERAY_TEST2_SSEL_MSK (0x7u)
+
+/** \brief Offset for Ifx_ERAY_TEST2_Bits.SSEL */
+#define IFX_ERAY_TEST2_SSEL_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_TEST2_Bits.WRECC */
+#define IFX_ERAY_TEST2_WRECC_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TEST2_Bits.WRECC */
+#define IFX_ERAY_TEST2_WRECC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TEST2_Bits.WRECC */
+#define IFX_ERAY_TEST2_WRECC_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR0 */
+#define IFX_ERAY_TXRQ1_TXR0_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR0 */
+#define IFX_ERAY_TXRQ1_TXR0_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR0 */
+#define IFX_ERAY_TXRQ1_TXR0_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR10 */
+#define IFX_ERAY_TXRQ1_TXR10_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR10 */
+#define IFX_ERAY_TXRQ1_TXR10_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR10 */
+#define IFX_ERAY_TXRQ1_TXR10_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR11 */
+#define IFX_ERAY_TXRQ1_TXR11_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR11 */
+#define IFX_ERAY_TXRQ1_TXR11_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR11 */
+#define IFX_ERAY_TXRQ1_TXR11_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR12 */
+#define IFX_ERAY_TXRQ1_TXR12_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR12 */
+#define IFX_ERAY_TXRQ1_TXR12_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR12 */
+#define IFX_ERAY_TXRQ1_TXR12_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR13 */
+#define IFX_ERAY_TXRQ1_TXR13_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR13 */
+#define IFX_ERAY_TXRQ1_TXR13_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR13 */
+#define IFX_ERAY_TXRQ1_TXR13_OFF (13u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR14 */
+#define IFX_ERAY_TXRQ1_TXR14_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR14 */
+#define IFX_ERAY_TXRQ1_TXR14_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR14 */
+#define IFX_ERAY_TXRQ1_TXR14_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR15 */
+#define IFX_ERAY_TXRQ1_TXR15_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR15 */
+#define IFX_ERAY_TXRQ1_TXR15_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR15 */
+#define IFX_ERAY_TXRQ1_TXR15_OFF (15u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR16 */
+#define IFX_ERAY_TXRQ1_TXR16_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR16 */
+#define IFX_ERAY_TXRQ1_TXR16_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR16 */
+#define IFX_ERAY_TXRQ1_TXR16_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR17 */
+#define IFX_ERAY_TXRQ1_TXR17_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR17 */
+#define IFX_ERAY_TXRQ1_TXR17_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR17 */
+#define IFX_ERAY_TXRQ1_TXR17_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR18 */
+#define IFX_ERAY_TXRQ1_TXR18_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR18 */
+#define IFX_ERAY_TXRQ1_TXR18_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR18 */
+#define IFX_ERAY_TXRQ1_TXR18_OFF (18u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR19 */
+#define IFX_ERAY_TXRQ1_TXR19_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR19 */
+#define IFX_ERAY_TXRQ1_TXR19_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR19 */
+#define IFX_ERAY_TXRQ1_TXR19_OFF (19u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR1 */
+#define IFX_ERAY_TXRQ1_TXR1_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR1 */
+#define IFX_ERAY_TXRQ1_TXR1_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR1 */
+#define IFX_ERAY_TXRQ1_TXR1_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR20 */
+#define IFX_ERAY_TXRQ1_TXR20_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR20 */
+#define IFX_ERAY_TXRQ1_TXR20_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR20 */
+#define IFX_ERAY_TXRQ1_TXR20_OFF (20u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR21 */
+#define IFX_ERAY_TXRQ1_TXR21_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR21 */
+#define IFX_ERAY_TXRQ1_TXR21_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR21 */
+#define IFX_ERAY_TXRQ1_TXR21_OFF (21u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR22 */
+#define IFX_ERAY_TXRQ1_TXR22_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR22 */
+#define IFX_ERAY_TXRQ1_TXR22_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR22 */
+#define IFX_ERAY_TXRQ1_TXR22_OFF (22u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR23 */
+#define IFX_ERAY_TXRQ1_TXR23_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR23 */
+#define IFX_ERAY_TXRQ1_TXR23_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR23 */
+#define IFX_ERAY_TXRQ1_TXR23_OFF (23u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR24 */
+#define IFX_ERAY_TXRQ1_TXR24_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR24 */
+#define IFX_ERAY_TXRQ1_TXR24_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR24 */
+#define IFX_ERAY_TXRQ1_TXR24_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR25 */
+#define IFX_ERAY_TXRQ1_TXR25_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR25 */
+#define IFX_ERAY_TXRQ1_TXR25_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR25 */
+#define IFX_ERAY_TXRQ1_TXR25_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR26 */
+#define IFX_ERAY_TXRQ1_TXR26_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR26 */
+#define IFX_ERAY_TXRQ1_TXR26_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR26 */
+#define IFX_ERAY_TXRQ1_TXR26_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR27 */
+#define IFX_ERAY_TXRQ1_TXR27_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR27 */
+#define IFX_ERAY_TXRQ1_TXR27_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR27 */
+#define IFX_ERAY_TXRQ1_TXR27_OFF (27u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR28 */
+#define IFX_ERAY_TXRQ1_TXR28_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR28 */
+#define IFX_ERAY_TXRQ1_TXR28_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR28 */
+#define IFX_ERAY_TXRQ1_TXR28_OFF (28u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR29 */
+#define IFX_ERAY_TXRQ1_TXR29_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR29 */
+#define IFX_ERAY_TXRQ1_TXR29_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR29 */
+#define IFX_ERAY_TXRQ1_TXR29_OFF (29u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR2 */
+#define IFX_ERAY_TXRQ1_TXR2_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR2 */
+#define IFX_ERAY_TXRQ1_TXR2_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR2 */
+#define IFX_ERAY_TXRQ1_TXR2_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR30 */
+#define IFX_ERAY_TXRQ1_TXR30_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR30 */
+#define IFX_ERAY_TXRQ1_TXR30_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR30 */
+#define IFX_ERAY_TXRQ1_TXR30_OFF (30u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR31 */
+#define IFX_ERAY_TXRQ1_TXR31_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR31 */
+#define IFX_ERAY_TXRQ1_TXR31_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR31 */
+#define IFX_ERAY_TXRQ1_TXR31_OFF (31u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR3 */
+#define IFX_ERAY_TXRQ1_TXR3_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR3 */
+#define IFX_ERAY_TXRQ1_TXR3_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR3 */
+#define IFX_ERAY_TXRQ1_TXR3_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR4 */
+#define IFX_ERAY_TXRQ1_TXR4_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR4 */
+#define IFX_ERAY_TXRQ1_TXR4_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR4 */
+#define IFX_ERAY_TXRQ1_TXR4_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR5 */
+#define IFX_ERAY_TXRQ1_TXR5_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR5 */
+#define IFX_ERAY_TXRQ1_TXR5_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR5 */
+#define IFX_ERAY_TXRQ1_TXR5_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR6 */
+#define IFX_ERAY_TXRQ1_TXR6_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR6 */
+#define IFX_ERAY_TXRQ1_TXR6_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR6 */
+#define IFX_ERAY_TXRQ1_TXR6_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR7 */
+#define IFX_ERAY_TXRQ1_TXR7_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR7 */
+#define IFX_ERAY_TXRQ1_TXR7_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR7 */
+#define IFX_ERAY_TXRQ1_TXR7_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR8 */
+#define IFX_ERAY_TXRQ1_TXR8_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR8 */
+#define IFX_ERAY_TXRQ1_TXR8_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR8 */
+#define IFX_ERAY_TXRQ1_TXR8_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_TXRQ1_Bits.TXR9 */
+#define IFX_ERAY_TXRQ1_TXR9_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ1_Bits.TXR9 */
+#define IFX_ERAY_TXRQ1_TXR9_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ1_Bits.TXR9 */
+#define IFX_ERAY_TXRQ1_TXR9_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR32 */
+#define IFX_ERAY_TXRQ2_TXR32_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR32 */
+#define IFX_ERAY_TXRQ2_TXR32_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR32 */
+#define IFX_ERAY_TXRQ2_TXR32_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR33 */
+#define IFX_ERAY_TXRQ2_TXR33_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR33 */
+#define IFX_ERAY_TXRQ2_TXR33_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR33 */
+#define IFX_ERAY_TXRQ2_TXR33_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR34 */
+#define IFX_ERAY_TXRQ2_TXR34_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR34 */
+#define IFX_ERAY_TXRQ2_TXR34_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR34 */
+#define IFX_ERAY_TXRQ2_TXR34_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR35 */
+#define IFX_ERAY_TXRQ2_TXR35_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR35 */
+#define IFX_ERAY_TXRQ2_TXR35_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR35 */
+#define IFX_ERAY_TXRQ2_TXR35_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR36 */
+#define IFX_ERAY_TXRQ2_TXR36_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR36 */
+#define IFX_ERAY_TXRQ2_TXR36_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR36 */
+#define IFX_ERAY_TXRQ2_TXR36_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR37 */
+#define IFX_ERAY_TXRQ2_TXR37_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR37 */
+#define IFX_ERAY_TXRQ2_TXR37_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR37 */
+#define IFX_ERAY_TXRQ2_TXR37_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR38 */
+#define IFX_ERAY_TXRQ2_TXR38_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR38 */
+#define IFX_ERAY_TXRQ2_TXR38_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR38 */
+#define IFX_ERAY_TXRQ2_TXR38_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR39 */
+#define IFX_ERAY_TXRQ2_TXR39_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR39 */
+#define IFX_ERAY_TXRQ2_TXR39_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR39 */
+#define IFX_ERAY_TXRQ2_TXR39_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR40 */
+#define IFX_ERAY_TXRQ2_TXR40_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR40 */
+#define IFX_ERAY_TXRQ2_TXR40_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR40 */
+#define IFX_ERAY_TXRQ2_TXR40_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR41 */
+#define IFX_ERAY_TXRQ2_TXR41_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR41 */
+#define IFX_ERAY_TXRQ2_TXR41_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR41 */
+#define IFX_ERAY_TXRQ2_TXR41_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR42 */
+#define IFX_ERAY_TXRQ2_TXR42_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR42 */
+#define IFX_ERAY_TXRQ2_TXR42_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR42 */
+#define IFX_ERAY_TXRQ2_TXR42_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR43 */
+#define IFX_ERAY_TXRQ2_TXR43_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR43 */
+#define IFX_ERAY_TXRQ2_TXR43_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR43 */
+#define IFX_ERAY_TXRQ2_TXR43_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR44 */
+#define IFX_ERAY_TXRQ2_TXR44_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR44 */
+#define IFX_ERAY_TXRQ2_TXR44_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR44 */
+#define IFX_ERAY_TXRQ2_TXR44_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR45 */
+#define IFX_ERAY_TXRQ2_TXR45_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR45 */
+#define IFX_ERAY_TXRQ2_TXR45_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR45 */
+#define IFX_ERAY_TXRQ2_TXR45_OFF (13u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR46 */
+#define IFX_ERAY_TXRQ2_TXR46_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR46 */
+#define IFX_ERAY_TXRQ2_TXR46_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR46 */
+#define IFX_ERAY_TXRQ2_TXR46_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR47 */
+#define IFX_ERAY_TXRQ2_TXR47_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR47 */
+#define IFX_ERAY_TXRQ2_TXR47_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR47 */
+#define IFX_ERAY_TXRQ2_TXR47_OFF (15u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR48 */
+#define IFX_ERAY_TXRQ2_TXR48_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR48 */
+#define IFX_ERAY_TXRQ2_TXR48_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR48 */
+#define IFX_ERAY_TXRQ2_TXR48_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR49 */
+#define IFX_ERAY_TXRQ2_TXR49_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR49 */
+#define IFX_ERAY_TXRQ2_TXR49_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR49 */
+#define IFX_ERAY_TXRQ2_TXR49_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR50 */
+#define IFX_ERAY_TXRQ2_TXR50_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR50 */
+#define IFX_ERAY_TXRQ2_TXR50_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR50 */
+#define IFX_ERAY_TXRQ2_TXR50_OFF (18u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR51 */
+#define IFX_ERAY_TXRQ2_TXR51_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR51 */
+#define IFX_ERAY_TXRQ2_TXR51_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR51 */
+#define IFX_ERAY_TXRQ2_TXR51_OFF (19u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR52 */
+#define IFX_ERAY_TXRQ2_TXR52_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR52 */
+#define IFX_ERAY_TXRQ2_TXR52_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR52 */
+#define IFX_ERAY_TXRQ2_TXR52_OFF (20u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR53 */
+#define IFX_ERAY_TXRQ2_TXR53_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR53 */
+#define IFX_ERAY_TXRQ2_TXR53_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR53 */
+#define IFX_ERAY_TXRQ2_TXR53_OFF (21u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR54 */
+#define IFX_ERAY_TXRQ2_TXR54_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR54 */
+#define IFX_ERAY_TXRQ2_TXR54_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR54 */
+#define IFX_ERAY_TXRQ2_TXR54_OFF (22u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR55 */
+#define IFX_ERAY_TXRQ2_TXR55_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR55 */
+#define IFX_ERAY_TXRQ2_TXR55_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR55 */
+#define IFX_ERAY_TXRQ2_TXR55_OFF (23u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR56 */
+#define IFX_ERAY_TXRQ2_TXR56_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR56 */
+#define IFX_ERAY_TXRQ2_TXR56_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR56 */
+#define IFX_ERAY_TXRQ2_TXR56_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR57 */
+#define IFX_ERAY_TXRQ2_TXR57_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR57 */
+#define IFX_ERAY_TXRQ2_TXR57_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR57 */
+#define IFX_ERAY_TXRQ2_TXR57_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR58 */
+#define IFX_ERAY_TXRQ2_TXR58_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR58 */
+#define IFX_ERAY_TXRQ2_TXR58_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR58 */
+#define IFX_ERAY_TXRQ2_TXR58_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR59 */
+#define IFX_ERAY_TXRQ2_TXR59_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR59 */
+#define IFX_ERAY_TXRQ2_TXR59_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR59 */
+#define IFX_ERAY_TXRQ2_TXR59_OFF (27u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR60 */
+#define IFX_ERAY_TXRQ2_TXR60_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR60 */
+#define IFX_ERAY_TXRQ2_TXR60_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR60 */
+#define IFX_ERAY_TXRQ2_TXR60_OFF (28u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR61 */
+#define IFX_ERAY_TXRQ2_TXR61_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR61 */
+#define IFX_ERAY_TXRQ2_TXR61_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR61 */
+#define IFX_ERAY_TXRQ2_TXR61_OFF (29u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR62 */
+#define IFX_ERAY_TXRQ2_TXR62_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR62 */
+#define IFX_ERAY_TXRQ2_TXR62_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR62 */
+#define IFX_ERAY_TXRQ2_TXR62_OFF (30u)
+
+/** \brief Length for Ifx_ERAY_TXRQ2_Bits.TXR63 */
+#define IFX_ERAY_TXRQ2_TXR63_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ2_Bits.TXR63 */
+#define IFX_ERAY_TXRQ2_TXR63_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ2_Bits.TXR63 */
+#define IFX_ERAY_TXRQ2_TXR63_OFF (31u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR64 */
+#define IFX_ERAY_TXRQ3_TXR64_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR64 */
+#define IFX_ERAY_TXRQ3_TXR64_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR64 */
+#define IFX_ERAY_TXRQ3_TXR64_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR65 */
+#define IFX_ERAY_TXRQ3_TXR65_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR65 */
+#define IFX_ERAY_TXRQ3_TXR65_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR65 */
+#define IFX_ERAY_TXRQ3_TXR65_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR66 */
+#define IFX_ERAY_TXRQ3_TXR66_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR66 */
+#define IFX_ERAY_TXRQ3_TXR66_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR66 */
+#define IFX_ERAY_TXRQ3_TXR66_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR67 */
+#define IFX_ERAY_TXRQ3_TXR67_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR67 */
+#define IFX_ERAY_TXRQ3_TXR67_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR67 */
+#define IFX_ERAY_TXRQ3_TXR67_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR68 */
+#define IFX_ERAY_TXRQ3_TXR68_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR68 */
+#define IFX_ERAY_TXRQ3_TXR68_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR68 */
+#define IFX_ERAY_TXRQ3_TXR68_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR69 */
+#define IFX_ERAY_TXRQ3_TXR69_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR69 */
+#define IFX_ERAY_TXRQ3_TXR69_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR69 */
+#define IFX_ERAY_TXRQ3_TXR69_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR70 */
+#define IFX_ERAY_TXRQ3_TXR70_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR70 */
+#define IFX_ERAY_TXRQ3_TXR70_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR70 */
+#define IFX_ERAY_TXRQ3_TXR70_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR71 */
+#define IFX_ERAY_TXRQ3_TXR71_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR71 */
+#define IFX_ERAY_TXRQ3_TXR71_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR71 */
+#define IFX_ERAY_TXRQ3_TXR71_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR72 */
+#define IFX_ERAY_TXRQ3_TXR72_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR72 */
+#define IFX_ERAY_TXRQ3_TXR72_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR72 */
+#define IFX_ERAY_TXRQ3_TXR72_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR73 */
+#define IFX_ERAY_TXRQ3_TXR73_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR73 */
+#define IFX_ERAY_TXRQ3_TXR73_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR73 */
+#define IFX_ERAY_TXRQ3_TXR73_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR74 */
+#define IFX_ERAY_TXRQ3_TXR74_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR74 */
+#define IFX_ERAY_TXRQ3_TXR74_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR74 */
+#define IFX_ERAY_TXRQ3_TXR74_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR75 */
+#define IFX_ERAY_TXRQ3_TXR75_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR75 */
+#define IFX_ERAY_TXRQ3_TXR75_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR75 */
+#define IFX_ERAY_TXRQ3_TXR75_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR76 */
+#define IFX_ERAY_TXRQ3_TXR76_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR76 */
+#define IFX_ERAY_TXRQ3_TXR76_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR76 */
+#define IFX_ERAY_TXRQ3_TXR76_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR77 */
+#define IFX_ERAY_TXRQ3_TXR77_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR77 */
+#define IFX_ERAY_TXRQ3_TXR77_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR77 */
+#define IFX_ERAY_TXRQ3_TXR77_OFF (13u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR78 */
+#define IFX_ERAY_TXRQ3_TXR78_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR78 */
+#define IFX_ERAY_TXRQ3_TXR78_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR78 */
+#define IFX_ERAY_TXRQ3_TXR78_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR79 */
+#define IFX_ERAY_TXRQ3_TXR79_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR79 */
+#define IFX_ERAY_TXRQ3_TXR79_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR79 */
+#define IFX_ERAY_TXRQ3_TXR79_OFF (15u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR80 */
+#define IFX_ERAY_TXRQ3_TXR80_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR80 */
+#define IFX_ERAY_TXRQ3_TXR80_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR80 */
+#define IFX_ERAY_TXRQ3_TXR80_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR81 */
+#define IFX_ERAY_TXRQ3_TXR81_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR81 */
+#define IFX_ERAY_TXRQ3_TXR81_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR81 */
+#define IFX_ERAY_TXRQ3_TXR81_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR82 */
+#define IFX_ERAY_TXRQ3_TXR82_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR82 */
+#define IFX_ERAY_TXRQ3_TXR82_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR82 */
+#define IFX_ERAY_TXRQ3_TXR82_OFF (18u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR83 */
+#define IFX_ERAY_TXRQ3_TXR83_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR83 */
+#define IFX_ERAY_TXRQ3_TXR83_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR83 */
+#define IFX_ERAY_TXRQ3_TXR83_OFF (19u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR84 */
+#define IFX_ERAY_TXRQ3_TXR84_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR84 */
+#define IFX_ERAY_TXRQ3_TXR84_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR84 */
+#define IFX_ERAY_TXRQ3_TXR84_OFF (20u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR85 */
+#define IFX_ERAY_TXRQ3_TXR85_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR85 */
+#define IFX_ERAY_TXRQ3_TXR85_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR85 */
+#define IFX_ERAY_TXRQ3_TXR85_OFF (21u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR86 */
+#define IFX_ERAY_TXRQ3_TXR86_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR86 */
+#define IFX_ERAY_TXRQ3_TXR86_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR86 */
+#define IFX_ERAY_TXRQ3_TXR86_OFF (22u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR87 */
+#define IFX_ERAY_TXRQ3_TXR87_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR87 */
+#define IFX_ERAY_TXRQ3_TXR87_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR87 */
+#define IFX_ERAY_TXRQ3_TXR87_OFF (23u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR88 */
+#define IFX_ERAY_TXRQ3_TXR88_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR88 */
+#define IFX_ERAY_TXRQ3_TXR88_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR88 */
+#define IFX_ERAY_TXRQ3_TXR88_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR89 */
+#define IFX_ERAY_TXRQ3_TXR89_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR89 */
+#define IFX_ERAY_TXRQ3_TXR89_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR89 */
+#define IFX_ERAY_TXRQ3_TXR89_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR90 */
+#define IFX_ERAY_TXRQ3_TXR90_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR90 */
+#define IFX_ERAY_TXRQ3_TXR90_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR90 */
+#define IFX_ERAY_TXRQ3_TXR90_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR91 */
+#define IFX_ERAY_TXRQ3_TXR91_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR91 */
+#define IFX_ERAY_TXRQ3_TXR91_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR91 */
+#define IFX_ERAY_TXRQ3_TXR91_OFF (27u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR92 */
+#define IFX_ERAY_TXRQ3_TXR92_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR92 */
+#define IFX_ERAY_TXRQ3_TXR92_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR92 */
+#define IFX_ERAY_TXRQ3_TXR92_OFF (28u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR93 */
+#define IFX_ERAY_TXRQ3_TXR93_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR93 */
+#define IFX_ERAY_TXRQ3_TXR93_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR93 */
+#define IFX_ERAY_TXRQ3_TXR93_OFF (29u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR94 */
+#define IFX_ERAY_TXRQ3_TXR94_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR94 */
+#define IFX_ERAY_TXRQ3_TXR94_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR94 */
+#define IFX_ERAY_TXRQ3_TXR94_OFF (30u)
+
+/** \brief Length for Ifx_ERAY_TXRQ3_Bits.TXR95 */
+#define IFX_ERAY_TXRQ3_TXR95_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ3_Bits.TXR95 */
+#define IFX_ERAY_TXRQ3_TXR95_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ3_Bits.TXR95 */
+#define IFX_ERAY_TXRQ3_TXR95_OFF (31u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR100 */
+#define IFX_ERAY_TXRQ4_TXR100_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR100 */
+#define IFX_ERAY_TXRQ4_TXR100_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR100 */
+#define IFX_ERAY_TXRQ4_TXR100_OFF (4u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR101 */
+#define IFX_ERAY_TXRQ4_TXR101_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR101 */
+#define IFX_ERAY_TXRQ4_TXR101_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR101 */
+#define IFX_ERAY_TXRQ4_TXR101_OFF (5u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR102 */
+#define IFX_ERAY_TXRQ4_TXR102_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR102 */
+#define IFX_ERAY_TXRQ4_TXR102_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR102 */
+#define IFX_ERAY_TXRQ4_TXR102_OFF (6u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR103 */
+#define IFX_ERAY_TXRQ4_TXR103_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR103 */
+#define IFX_ERAY_TXRQ4_TXR103_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR103 */
+#define IFX_ERAY_TXRQ4_TXR103_OFF (7u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR104 */
+#define IFX_ERAY_TXRQ4_TXR104_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR104 */
+#define IFX_ERAY_TXRQ4_TXR104_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR104 */
+#define IFX_ERAY_TXRQ4_TXR104_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR105 */
+#define IFX_ERAY_TXRQ4_TXR105_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR105 */
+#define IFX_ERAY_TXRQ4_TXR105_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR105 */
+#define IFX_ERAY_TXRQ4_TXR105_OFF (9u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR106 */
+#define IFX_ERAY_TXRQ4_TXR106_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR106 */
+#define IFX_ERAY_TXRQ4_TXR106_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR106 */
+#define IFX_ERAY_TXRQ4_TXR106_OFF (10u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR107 */
+#define IFX_ERAY_TXRQ4_TXR107_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR107 */
+#define IFX_ERAY_TXRQ4_TXR107_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR107 */
+#define IFX_ERAY_TXRQ4_TXR107_OFF (11u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR108 */
+#define IFX_ERAY_TXRQ4_TXR108_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR108 */
+#define IFX_ERAY_TXRQ4_TXR108_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR108 */
+#define IFX_ERAY_TXRQ4_TXR108_OFF (12u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR109 */
+#define IFX_ERAY_TXRQ4_TXR109_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR109 */
+#define IFX_ERAY_TXRQ4_TXR109_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR109 */
+#define IFX_ERAY_TXRQ4_TXR109_OFF (13u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR110 */
+#define IFX_ERAY_TXRQ4_TXR110_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR110 */
+#define IFX_ERAY_TXRQ4_TXR110_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR110 */
+#define IFX_ERAY_TXRQ4_TXR110_OFF (14u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR111 */
+#define IFX_ERAY_TXRQ4_TXR111_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR111 */
+#define IFX_ERAY_TXRQ4_TXR111_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR111 */
+#define IFX_ERAY_TXRQ4_TXR111_OFF (15u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR112 */
+#define IFX_ERAY_TXRQ4_TXR112_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR112 */
+#define IFX_ERAY_TXRQ4_TXR112_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR112 */
+#define IFX_ERAY_TXRQ4_TXR112_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR113 */
+#define IFX_ERAY_TXRQ4_TXR113_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR113 */
+#define IFX_ERAY_TXRQ4_TXR113_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR113 */
+#define IFX_ERAY_TXRQ4_TXR113_OFF (17u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR114 */
+#define IFX_ERAY_TXRQ4_TXR114_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR114 */
+#define IFX_ERAY_TXRQ4_TXR114_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR114 */
+#define IFX_ERAY_TXRQ4_TXR114_OFF (18u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR115 */
+#define IFX_ERAY_TXRQ4_TXR115_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR115 */
+#define IFX_ERAY_TXRQ4_TXR115_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR115 */
+#define IFX_ERAY_TXRQ4_TXR115_OFF (19u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR116 */
+#define IFX_ERAY_TXRQ4_TXR116_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR116 */
+#define IFX_ERAY_TXRQ4_TXR116_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR116 */
+#define IFX_ERAY_TXRQ4_TXR116_OFF (20u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR117 */
+#define IFX_ERAY_TXRQ4_TXR117_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR117 */
+#define IFX_ERAY_TXRQ4_TXR117_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR117 */
+#define IFX_ERAY_TXRQ4_TXR117_OFF (21u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR118 */
+#define IFX_ERAY_TXRQ4_TXR118_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR118 */
+#define IFX_ERAY_TXRQ4_TXR118_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR118 */
+#define IFX_ERAY_TXRQ4_TXR118_OFF (22u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR119 */
+#define IFX_ERAY_TXRQ4_TXR119_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR119 */
+#define IFX_ERAY_TXRQ4_TXR119_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR119 */
+#define IFX_ERAY_TXRQ4_TXR119_OFF (23u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR120 */
+#define IFX_ERAY_TXRQ4_TXR120_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR120 */
+#define IFX_ERAY_TXRQ4_TXR120_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR120 */
+#define IFX_ERAY_TXRQ4_TXR120_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR121 */
+#define IFX_ERAY_TXRQ4_TXR121_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR121 */
+#define IFX_ERAY_TXRQ4_TXR121_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR121 */
+#define IFX_ERAY_TXRQ4_TXR121_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR122 */
+#define IFX_ERAY_TXRQ4_TXR122_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR122 */
+#define IFX_ERAY_TXRQ4_TXR122_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR122 */
+#define IFX_ERAY_TXRQ4_TXR122_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR123 */
+#define IFX_ERAY_TXRQ4_TXR123_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR123 */
+#define IFX_ERAY_TXRQ4_TXR123_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR123 */
+#define IFX_ERAY_TXRQ4_TXR123_OFF (27u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR124 */
+#define IFX_ERAY_TXRQ4_TXR124_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR124 */
+#define IFX_ERAY_TXRQ4_TXR124_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR124 */
+#define IFX_ERAY_TXRQ4_TXR124_OFF (28u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR125 */
+#define IFX_ERAY_TXRQ4_TXR125_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR125 */
+#define IFX_ERAY_TXRQ4_TXR125_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR125 */
+#define IFX_ERAY_TXRQ4_TXR125_OFF (29u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR126 */
+#define IFX_ERAY_TXRQ4_TXR126_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR126 */
+#define IFX_ERAY_TXRQ4_TXR126_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR126 */
+#define IFX_ERAY_TXRQ4_TXR126_OFF (30u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR127 */
+#define IFX_ERAY_TXRQ4_TXR127_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR127 */
+#define IFX_ERAY_TXRQ4_TXR127_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR127 */
+#define IFX_ERAY_TXRQ4_TXR127_OFF (31u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR96 */
+#define IFX_ERAY_TXRQ4_TXR96_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR96 */
+#define IFX_ERAY_TXRQ4_TXR96_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR96 */
+#define IFX_ERAY_TXRQ4_TXR96_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR97 */
+#define IFX_ERAY_TXRQ4_TXR97_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR97 */
+#define IFX_ERAY_TXRQ4_TXR97_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR97 */
+#define IFX_ERAY_TXRQ4_TXR97_OFF (1u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR98 */
+#define IFX_ERAY_TXRQ4_TXR98_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR98 */
+#define IFX_ERAY_TXRQ4_TXR98_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR98 */
+#define IFX_ERAY_TXRQ4_TXR98_OFF (2u)
+
+/** \brief Length for Ifx_ERAY_TXRQ4_Bits.TXR99 */
+#define IFX_ERAY_TXRQ4_TXR99_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_TXRQ4_Bits.TXR99 */
+#define IFX_ERAY_TXRQ4_TXR99_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_TXRQ4_Bits.TXR99 */
+#define IFX_ERAY_TXRQ4_TXR99_OFF (3u)
+
+/** \brief Length for Ifx_ERAY_WRDS_Bits.MDWB0 */
+#define IFX_ERAY_WRDS_MDWB0_LEN (8u)
+
+/** \brief Mask for Ifx_ERAY_WRDS_Bits.MDWB0 */
+#define IFX_ERAY_WRDS_MDWB0_MSK (0xffu)
+
+/** \brief Offset for Ifx_ERAY_WRDS_Bits.MDWB0 */
+#define IFX_ERAY_WRDS_MDWB0_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_WRDS_Bits.MDWB1 */
+#define IFX_ERAY_WRDS_MDWB1_LEN (8u)
+
+/** \brief Mask for Ifx_ERAY_WRDS_Bits.MDWB1 */
+#define IFX_ERAY_WRDS_MDWB1_MSK (0xffu)
+
+/** \brief Offset for Ifx_ERAY_WRDS_Bits.MDWB1 */
+#define IFX_ERAY_WRDS_MDWB1_OFF (8u)
+
+/** \brief Length for Ifx_ERAY_WRDS_Bits.MDWB2 */
+#define IFX_ERAY_WRDS_MDWB2_LEN (8u)
+
+/** \brief Mask for Ifx_ERAY_WRDS_Bits.MDWB2 */
+#define IFX_ERAY_WRDS_MDWB2_MSK (0xffu)
+
+/** \brief Offset for Ifx_ERAY_WRDS_Bits.MDWB2 */
+#define IFX_ERAY_WRDS_MDWB2_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_WRDS_Bits.MDWB3 */
+#define IFX_ERAY_WRDS_MDWB3_LEN (8u)
+
+/** \brief Mask for Ifx_ERAY_WRDS_Bits.MDWB3 */
+#define IFX_ERAY_WRDS_MDWB3_MSK (0xffu)
+
+/** \brief Offset for Ifx_ERAY_WRDS_Bits.MDWB3 */
+#define IFX_ERAY_WRDS_MDWB3_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_WRHS1_Bits.CFG */
+#define IFX_ERAY_WRHS1_CFG_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_WRHS1_Bits.CFG */
+#define IFX_ERAY_WRHS1_CFG_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_WRHS1_Bits.CFG */
+#define IFX_ERAY_WRHS1_CFG_OFF (26u)
+
+/** \brief Length for Ifx_ERAY_WRHS1_Bits.CHA */
+#define IFX_ERAY_WRHS1_CHA_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_WRHS1_Bits.CHA */
+#define IFX_ERAY_WRHS1_CHA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_WRHS1_Bits.CHA */
+#define IFX_ERAY_WRHS1_CHA_OFF (24u)
+
+/** \brief Length for Ifx_ERAY_WRHS1_Bits.CHB */
+#define IFX_ERAY_WRHS1_CHB_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_WRHS1_Bits.CHB */
+#define IFX_ERAY_WRHS1_CHB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_WRHS1_Bits.CHB */
+#define IFX_ERAY_WRHS1_CHB_OFF (25u)
+
+/** \brief Length for Ifx_ERAY_WRHS1_Bits.CYC */
+#define IFX_ERAY_WRHS1_CYC_LEN (7u)
+
+/** \brief Mask for Ifx_ERAY_WRHS1_Bits.CYC */
+#define IFX_ERAY_WRHS1_CYC_MSK (0x7fu)
+
+/** \brief Offset for Ifx_ERAY_WRHS1_Bits.CYC */
+#define IFX_ERAY_WRHS1_CYC_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_WRHS1_Bits.FID */
+#define IFX_ERAY_WRHS1_FID_LEN (11u)
+
+/** \brief Mask for Ifx_ERAY_WRHS1_Bits.FID */
+#define IFX_ERAY_WRHS1_FID_MSK (0x7ffu)
+
+/** \brief Offset for Ifx_ERAY_WRHS1_Bits.FID */
+#define IFX_ERAY_WRHS1_FID_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_WRHS1_Bits.MBI */
+#define IFX_ERAY_WRHS1_MBI_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_WRHS1_Bits.MBI */
+#define IFX_ERAY_WRHS1_MBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_WRHS1_Bits.MBI */
+#define IFX_ERAY_WRHS1_MBI_OFF (29u)
+
+/** \brief Length for Ifx_ERAY_WRHS1_Bits.PPIT */
+#define IFX_ERAY_WRHS1_PPIT_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_WRHS1_Bits.PPIT */
+#define IFX_ERAY_WRHS1_PPIT_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_WRHS1_Bits.PPIT */
+#define IFX_ERAY_WRHS1_PPIT_OFF (27u)
+
+/** \brief Length for Ifx_ERAY_WRHS1_Bits.TXM */
+#define IFX_ERAY_WRHS1_TXM_LEN (1u)
+
+/** \brief Mask for Ifx_ERAY_WRHS1_Bits.TXM */
+#define IFX_ERAY_WRHS1_TXM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ERAY_WRHS1_Bits.TXM */
+#define IFX_ERAY_WRHS1_TXM_OFF (28u)
+
+/** \brief Length for Ifx_ERAY_WRHS2_Bits.CRC */
+#define IFX_ERAY_WRHS2_CRC_LEN (11u)
+
+/** \brief Mask for Ifx_ERAY_WRHS2_Bits.CRC */
+#define IFX_ERAY_WRHS2_CRC_MSK (0x7ffu)
+
+/** \brief Offset for Ifx_ERAY_WRHS2_Bits.CRC */
+#define IFX_ERAY_WRHS2_CRC_OFF (0u)
+
+/** \brief Length for Ifx_ERAY_WRHS2_Bits.PLC */
+#define IFX_ERAY_WRHS2_PLC_LEN (7u)
+
+/** \brief Mask for Ifx_ERAY_WRHS2_Bits.PLC */
+#define IFX_ERAY_WRHS2_PLC_MSK (0x7fu)
+
+/** \brief Offset for Ifx_ERAY_WRHS2_Bits.PLC */
+#define IFX_ERAY_WRHS2_PLC_OFF (16u)
+
+/** \brief Length for Ifx_ERAY_WRHS3_Bits.DP */
+#define IFX_ERAY_WRHS3_DP_LEN (11u)
+
+/** \brief Mask for Ifx_ERAY_WRHS3_Bits.DP */
+#define IFX_ERAY_WRHS3_DP_MSK (0x7ffu)
+
+/** \brief Offset for Ifx_ERAY_WRHS3_Bits.DP */
+#define IFX_ERAY_WRHS3_DP_OFF (0u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXERAY_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEray_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEray_reg.h
new file mode 100644
index 0000000..b2304ff
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEray_reg.h
@@ -0,0 +1,2293 @@
+/**
+ * \file IfxEray_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Eray_Cfg Eray address
+ * \ingroup IfxLld_Eray
+ *
+ * \defgroup IfxLld_Eray_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Eray_Cfg
+ *
+ * \defgroup IfxLld_Eray_Cfg_Eray0 2-ERAY0
+ * \ingroup IfxLld_Eray_Cfg
+ *
+ */
+#ifndef IFXERAY_REG_H
+#define IFXERAY_REG_H 1
+/******************************************************************************/
+#include "IfxEray_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Eray_Cfg_BaseAddress
+ * \{ */
+
+/** \brief ERAY object */
+#define MODULE_ERAY0 /*lint --e(923)*/ (*(Ifx_ERAY*)0xF001C000u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Eray_Cfg_Eray0
+ * \{ */
+
+/** \brief 8FC, Access Enable Register 0 */
+#define ERAY0_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_ERAY_ACCEN0*)0xF001C8FCu)
+
+/** Alias (User Manual Name) for ERAY0_ACCEN0.
+* To use register names with standard convension, please use ERAY0_ACCEN0.
+*/
+#define ERAY_ACCEN0 (ERAY0_ACCEN0)
+
+/** \brief 8F8, Access Enable Register 1 */
+#define ERAY0_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_ERAY_ACCEN1*)0xF001C8F8u)
+
+/** Alias (User Manual Name) for ERAY0_ACCEN1.
+* To use register names with standard convension, please use ERAY0_ACCEN1.
+*/
+#define ERAY_ACCEN1 (ERAY0_ACCEN1)
+
+/** \brief 128, Aggregated Channel Status */
+#define ERAY0_ACS /*lint --e(923)*/ (*(volatile Ifx_ERAY_ACS*)0xF001C128u)
+
+/** Alias (User Manual Name) for ERAY0_ACS.
+* To use register names with standard convension, please use ERAY0_ACS.
+*/
+#define ERAY_ACS (ERAY0_ACS)
+
+/** \brief 104, Communication Controller Error Vector */
+#define ERAY0_CCEV /*lint --e(923)*/ (*(volatile Ifx_ERAY_CCEV*)0xF001C104u)
+
+/** Alias (User Manual Name) for ERAY0_CCEV.
+* To use register names with standard convension, please use ERAY0_CCEV.
+*/
+#define ERAY_CCEV (ERAY0_CCEV)
+
+/** \brief 100, Communication Controller Status Vector */
+#define ERAY0_CCSV /*lint --e(923)*/ (*(volatile Ifx_ERAY_CCSV*)0xF001C100u)
+
+/** Alias (User Manual Name) for ERAY0_CCSV.
+* To use register names with standard convension, please use ERAY0_CCSV.
+*/
+#define ERAY_CCSV (ERAY0_CCSV)
+
+/** \brief 0, Clock Control Register */
+#define ERAY0_CLC /*lint --e(923)*/ (*(volatile Ifx_ERAY_CLC*)0xF001C000u)
+
+/** Alias (User Manual Name) for ERAY0_CLC.
+* To use register names with standard convension, please use ERAY0_CLC.
+*/
+#define ERAY_CLC (ERAY0_CLC)
+
+/** \brief 3F0, Core Release Register */
+#define ERAY0_CREL /*lint --e(923)*/ (*(volatile Ifx_ERAY_CREL*)0xF001C3F0u)
+
+/** Alias (User Manual Name) for ERAY0_CREL.
+* To use register names with standard convension, please use ERAY0_CREL.
+*/
+#define ERAY_CREL (ERAY0_CREL)
+
+/** \brief 4, Busy and Input Buffer Control Register */
+#define ERAY0_CUST1 /*lint --e(923)*/ (*(volatile Ifx_ERAY_CUST1*)0xF001C004u)
+
+/** Alias (User Manual Name) for ERAY0_CUST1.
+* To use register names with standard convension, please use ERAY0_CUST1.
+*/
+#define ERAY_CUST1 (ERAY0_CUST1)
+
+/** \brief C, Customer Interface Timeout Counter */
+#define ERAY0_CUST3 /*lint --e(923)*/ (*(volatile Ifx_ERAY_CUST3*)0xF001C00Cu)
+
+/** Alias (User Manual Name) for ERAY0_CUST3.
+* To use register names with standard convension, please use ERAY0_CUST3.
+*/
+#define ERAY_CUST3 (ERAY0_CUST3)
+
+/** \brief 34, Error Service Request Enable Reset */
+#define ERAY0_EIER /*lint --e(923)*/ (*(volatile Ifx_ERAY_EIER*)0xF001C034u)
+
+/** Alias (User Manual Name) for ERAY0_EIER.
+* To use register names with standard convension, please use ERAY0_EIER.
+*/
+#define ERAY_EIER (ERAY0_EIER)
+
+/** \brief 30, Error Service Request Enable Set */
+#define ERAY0_EIES /*lint --e(923)*/ (*(volatile Ifx_ERAY_EIES*)0xF001C030u)
+
+/** Alias (User Manual Name) for ERAY0_EIES.
+* To use register names with standard convension, please use ERAY0_EIES.
+*/
+#define ERAY_EIES (ERAY0_EIES)
+
+/** \brief 28, Error Service Request Line Select */
+#define ERAY0_EILS /*lint --e(923)*/ (*(volatile Ifx_ERAY_EILS*)0xF001C028u)
+
+/** Alias (User Manual Name) for ERAY0_EILS.
+* To use register names with standard convension, please use ERAY0_EILS.
+*/
+#define ERAY_EILS (ERAY0_EILS)
+
+/** \brief 20, Error Service Request Register */
+#define ERAY0_EIR /*lint --e(923)*/ (*(volatile Ifx_ERAY_EIR*)0xF001C020u)
+
+/** Alias (User Manual Name) for ERAY0_EIR.
+* To use register names with standard convension, please use ERAY0_EIR.
+*/
+#define ERAY_EIR (ERAY0_EIR)
+
+/** \brief 3F4, Endian Register */
+#define ERAY0_ENDN /*lint --e(923)*/ (*(volatile Ifx_ERAY_ENDN*)0xF001C3F4u)
+
+/** Alias (User Manual Name) for ERAY0_ENDN.
+* To use register names with standard convension, please use ERAY0_ENDN.
+*/
+#define ERAY_ENDN (ERAY0_ENDN)
+
+/** \brief 130, Even Sync ID Symbol Window \note Array index shifted by 1.
+ * Example: defined register ESID_1S[0]/ESID_1S0 corresponds to user manual
+ * ESID_1S1, ... */
+#define ERAY0_ESID_1S0 /*lint --e(923)*/ (*(volatile Ifx_ERAY_ESID*)0xF001C130u)
+
+/** Alias (User Manual Name) for ERAY0_ESID_1S0.
+* To use register names with standard convension, please use ERAY0_ESID_1S0.
+*/
+#define ERAY_ESID01 (ERAY0_ESID_1S0)
+
+/** \brief 134, Even Sync ID Symbol Window \note Array index shifted by 1.
+ * Example: defined register ESID_1S[0]/ESID_1S0 corresponds to user manual
+ * ESID_1S1, ... */
+#define ERAY0_ESID_1S1 /*lint --e(923)*/ (*(volatile Ifx_ERAY_ESID*)0xF001C134u)
+
+/** Alias (User Manual Name) for ERAY0_ESID_1S1.
+* To use register names with standard convension, please use ERAY0_ESID_1S1.
+*/
+#define ERAY_ESID02 (ERAY0_ESID_1S1)
+
+/** \brief 158, Even Sync ID Symbol Window \note Array index shifted by 1.
+ * Example: defined register ESID_1S[0]/ESID_1S0 corresponds to user manual
+ * ESID_1S1, ... */
+#define ERAY0_ESID_1S10 /*lint --e(923)*/ (*(volatile Ifx_ERAY_ESID*)0xF001C158u)
+
+/** Alias (User Manual Name) for ERAY0_ESID_1S10.
+* To use register names with standard convension, please use ERAY0_ESID_1S10.
+*/
+#define ERAY_ESID11 (ERAY0_ESID_1S10)
+
+/** \brief 15C, Even Sync ID Symbol Window \note Array index shifted by 1.
+ * Example: defined register ESID_1S[0]/ESID_1S0 corresponds to user manual
+ * ESID_1S1, ... */
+#define ERAY0_ESID_1S11 /*lint --e(923)*/ (*(volatile Ifx_ERAY_ESID*)0xF001C15Cu)
+
+/** Alias (User Manual Name) for ERAY0_ESID_1S11.
+* To use register names with standard convension, please use ERAY0_ESID_1S11.
+*/
+#define ERAY_ESID12 (ERAY0_ESID_1S11)
+
+/** \brief 160, Even Sync ID Symbol Window \note Array index shifted by 1.
+ * Example: defined register ESID_1S[0]/ESID_1S0 corresponds to user manual
+ * ESID_1S1, ... */
+#define ERAY0_ESID_1S12 /*lint --e(923)*/ (*(volatile Ifx_ERAY_ESID*)0xF001C160u)
+
+/** Alias (User Manual Name) for ERAY0_ESID_1S12.
+* To use register names with standard convension, please use ERAY0_ESID_1S12.
+*/
+#define ERAY_ESID13 (ERAY0_ESID_1S12)
+
+/** \brief 164, Even Sync ID Symbol Window \note Array index shifted by 1.
+ * Example: defined register ESID_1S[0]/ESID_1S0 corresponds to user manual
+ * ESID_1S1, ... */
+#define ERAY0_ESID_1S13 /*lint --e(923)*/ (*(volatile Ifx_ERAY_ESID*)0xF001C164u)
+
+/** Alias (User Manual Name) for ERAY0_ESID_1S13.
+* To use register names with standard convension, please use ERAY0_ESID_1S13.
+*/
+#define ERAY_ESID14 (ERAY0_ESID_1S13)
+
+/** \brief 168, Even Sync ID Symbol Window \note Array index shifted by 1.
+ * Example: defined register ESID_1S[0]/ESID_1S0 corresponds to user manual
+ * ESID_1S1, ... */
+#define ERAY0_ESID_1S14 /*lint --e(923)*/ (*(volatile Ifx_ERAY_ESID*)0xF001C168u)
+
+/** Alias (User Manual Name) for ERAY0_ESID_1S14.
+* To use register names with standard convension, please use ERAY0_ESID_1S14.
+*/
+#define ERAY_ESID15 (ERAY0_ESID_1S14)
+
+/** \brief 138, Even Sync ID Symbol Window \note Array index shifted by 1.
+ * Example: defined register ESID_1S[0]/ESID_1S0 corresponds to user manual
+ * ESID_1S1, ... */
+#define ERAY0_ESID_1S2 /*lint --e(923)*/ (*(volatile Ifx_ERAY_ESID*)0xF001C138u)
+
+/** Alias (User Manual Name) for ERAY0_ESID_1S2.
+* To use register names with standard convension, please use ERAY0_ESID_1S2.
+*/
+#define ERAY_ESID03 (ERAY0_ESID_1S2)
+
+/** \brief 13C, Even Sync ID Symbol Window \note Array index shifted by 1.
+ * Example: defined register ESID_1S[0]/ESID_1S0 corresponds to user manual
+ * ESID_1S1, ... */
+#define ERAY0_ESID_1S3 /*lint --e(923)*/ (*(volatile Ifx_ERAY_ESID*)0xF001C13Cu)
+
+/** Alias (User Manual Name) for ERAY0_ESID_1S3.
+* To use register names with standard convension, please use ERAY0_ESID_1S3.
+*/
+#define ERAY_ESID04 (ERAY0_ESID_1S3)
+
+/** \brief 140, Even Sync ID Symbol Window \note Array index shifted by 1.
+ * Example: defined register ESID_1S[0]/ESID_1S0 corresponds to user manual
+ * ESID_1S1, ... */
+#define ERAY0_ESID_1S4 /*lint --e(923)*/ (*(volatile Ifx_ERAY_ESID*)0xF001C140u)
+
+/** Alias (User Manual Name) for ERAY0_ESID_1S4.
+* To use register names with standard convension, please use ERAY0_ESID_1S4.
+*/
+#define ERAY_ESID05 (ERAY0_ESID_1S4)
+
+/** \brief 144, Even Sync ID Symbol Window \note Array index shifted by 1.
+ * Example: defined register ESID_1S[0]/ESID_1S0 corresponds to user manual
+ * ESID_1S1, ... */
+#define ERAY0_ESID_1S5 /*lint --e(923)*/ (*(volatile Ifx_ERAY_ESID*)0xF001C144u)
+
+/** Alias (User Manual Name) for ERAY0_ESID_1S5.
+* To use register names with standard convension, please use ERAY0_ESID_1S5.
+*/
+#define ERAY_ESID06 (ERAY0_ESID_1S5)
+
+/** \brief 148, Even Sync ID Symbol Window \note Array index shifted by 1.
+ * Example: defined register ESID_1S[0]/ESID_1S0 corresponds to user manual
+ * ESID_1S1, ... */
+#define ERAY0_ESID_1S6 /*lint --e(923)*/ (*(volatile Ifx_ERAY_ESID*)0xF001C148u)
+
+/** Alias (User Manual Name) for ERAY0_ESID_1S6.
+* To use register names with standard convension, please use ERAY0_ESID_1S6.
+*/
+#define ERAY_ESID07 (ERAY0_ESID_1S6)
+
+/** \brief 14C, Even Sync ID Symbol Window \note Array index shifted by 1.
+ * Example: defined register ESID_1S[0]/ESID_1S0 corresponds to user manual
+ * ESID_1S1, ... */
+#define ERAY0_ESID_1S7 /*lint --e(923)*/ (*(volatile Ifx_ERAY_ESID*)0xF001C14Cu)
+
+/** Alias (User Manual Name) for ERAY0_ESID_1S7.
+* To use register names with standard convension, please use ERAY0_ESID_1S7.
+*/
+#define ERAY_ESID08 (ERAY0_ESID_1S7)
+
+/** \brief 150, Even Sync ID Symbol Window \note Array index shifted by 1.
+ * Example: defined register ESID_1S[0]/ESID_1S0 corresponds to user manual
+ * ESID_1S1, ... */
+#define ERAY0_ESID_1S8 /*lint --e(923)*/ (*(volatile Ifx_ERAY_ESID*)0xF001C150u)
+
+/** Alias (User Manual Name) for ERAY0_ESID_1S8.
+* To use register names with standard convension, please use ERAY0_ESID_1S8.
+*/
+#define ERAY_ESID09 (ERAY0_ESID_1S8)
+
+/** \brief 154, Even Sync ID Symbol Window \note Array index shifted by 1.
+ * Example: defined register ESID_1S[0]/ESID_1S0 corresponds to user manual
+ * ESID_1S1, ... */
+#define ERAY0_ESID_1S9 /*lint --e(923)*/ (*(volatile Ifx_ERAY_ESID*)0xF001C154u)
+
+/** Alias (User Manual Name) for ERAY0_ESID_1S9.
+* To use register names with standard convension, please use ERAY0_ESID_1S9.
+*/
+#define ERAY_ESID10 (ERAY0_ESID_1S9)
+
+/** \brief 30C, FIFO Critical Level */
+#define ERAY0_FCL /*lint --e(923)*/ (*(volatile Ifx_ERAY_FCL*)0xF001C30Cu)
+
+/** Alias (User Manual Name) for ERAY0_FCL.
+* To use register names with standard convension, please use ERAY0_FCL.
+*/
+#define ERAY_FCL (ERAY0_FCL)
+
+/** \brief 304, FIFO Rejection Filter */
+#define ERAY0_FRF /*lint --e(923)*/ (*(volatile Ifx_ERAY_FRF*)0xF001C304u)
+
+/** Alias (User Manual Name) for ERAY0_FRF.
+* To use register names with standard convension, please use ERAY0_FRF.
+*/
+#define ERAY_FRF (ERAY0_FRF)
+
+/** \brief 308, FIFO Rejection Filter Mask */
+#define ERAY0_FRFM /*lint --e(923)*/ (*(volatile Ifx_ERAY_FRFM*)0xF001C308u)
+
+/** Alias (User Manual Name) for ERAY0_FRFM.
+* To use register names with standard convension, please use ERAY0_FRFM.
+*/
+#define ERAY_FRFM (ERAY0_FRFM)
+
+/** \brief 318, FIFO Status Register */
+#define ERAY0_FSR /*lint --e(923)*/ (*(volatile Ifx_ERAY_FSR*)0xF001C318u)
+
+/** Alias (User Manual Name) for ERAY0_FSR.
+* To use register names with standard convension, please use ERAY0_FSR.
+*/
+#define ERAY_FSR (ERAY0_FSR)
+
+/** \brief A0, GTU Configuration Register 1 */
+#define ERAY0_GTUC01 /*lint --e(923)*/ (*(volatile Ifx_ERAY_GTUC01*)0xF001C0A0u)
+
+/** Alias (User Manual Name) for ERAY0_GTUC01.
+* To use register names with standard convension, please use ERAY0_GTUC01.
+*/
+#define ERAY_GTUC01 (ERAY0_GTUC01)
+
+/** \brief A4, GTU Configuration Register 2 */
+#define ERAY0_GTUC02 /*lint --e(923)*/ (*(volatile Ifx_ERAY_GTUC02*)0xF001C0A4u)
+
+/** Alias (User Manual Name) for ERAY0_GTUC02.
+* To use register names with standard convension, please use ERAY0_GTUC02.
+*/
+#define ERAY_GTUC02 (ERAY0_GTUC02)
+
+/** \brief A8, GTU Configuration Register 3 */
+#define ERAY0_GTUC03 /*lint --e(923)*/ (*(volatile Ifx_ERAY_GTUC03*)0xF001C0A8u)
+
+/** Alias (User Manual Name) for ERAY0_GTUC03.
+* To use register names with standard convension, please use ERAY0_GTUC03.
+*/
+#define ERAY_GTUC03 (ERAY0_GTUC03)
+
+/** \brief AC, GTU Configuration Register 4 */
+#define ERAY0_GTUC04 /*lint --e(923)*/ (*(volatile Ifx_ERAY_GTUC04*)0xF001C0ACu)
+
+/** Alias (User Manual Name) for ERAY0_GTUC04.
+* To use register names with standard convension, please use ERAY0_GTUC04.
+*/
+#define ERAY_GTUC04 (ERAY0_GTUC04)
+
+/** \brief B0, GTU Configuration Register 5 */
+#define ERAY0_GTUC05 /*lint --e(923)*/ (*(volatile Ifx_ERAY_GTUC05*)0xF001C0B0u)
+
+/** Alias (User Manual Name) for ERAY0_GTUC05.
+* To use register names with standard convension, please use ERAY0_GTUC05.
+*/
+#define ERAY_GTUC05 (ERAY0_GTUC05)
+
+/** \brief B4, GTU Configuration Register 6 */
+#define ERAY0_GTUC06 /*lint --e(923)*/ (*(volatile Ifx_ERAY_GTUC06*)0xF001C0B4u)
+
+/** Alias (User Manual Name) for ERAY0_GTUC06.
+* To use register names with standard convension, please use ERAY0_GTUC06.
+*/
+#define ERAY_GTUC06 (ERAY0_GTUC06)
+
+/** \brief B8, GTU Configuration Register 7 */
+#define ERAY0_GTUC07 /*lint --e(923)*/ (*(volatile Ifx_ERAY_GTUC07*)0xF001C0B8u)
+
+/** Alias (User Manual Name) for ERAY0_GTUC07.
+* To use register names with standard convension, please use ERAY0_GTUC07.
+*/
+#define ERAY_GTUC07 (ERAY0_GTUC07)
+
+/** \brief BC, GTU Configuration Register 8 */
+#define ERAY0_GTUC08 /*lint --e(923)*/ (*(volatile Ifx_ERAY_GTUC08*)0xF001C0BCu)
+
+/** Alias (User Manual Name) for ERAY0_GTUC08.
+* To use register names with standard convension, please use ERAY0_GTUC08.
+*/
+#define ERAY_GTUC08 (ERAY0_GTUC08)
+
+/** \brief C0, GTU Configuration Register 9 */
+#define ERAY0_GTUC09 /*lint --e(923)*/ (*(volatile Ifx_ERAY_GTUC09*)0xF001C0C0u)
+
+/** Alias (User Manual Name) for ERAY0_GTUC09.
+* To use register names with standard convension, please use ERAY0_GTUC09.
+*/
+#define ERAY_GTUC09 (ERAY0_GTUC09)
+
+/** \brief C4, GTU Configuration Register 10 */
+#define ERAY0_GTUC10 /*lint --e(923)*/ (*(volatile Ifx_ERAY_GTUC10*)0xF001C0C4u)
+
+/** Alias (User Manual Name) for ERAY0_GTUC10.
+* To use register names with standard convension, please use ERAY0_GTUC10.
+*/
+#define ERAY_GTUC10 (ERAY0_GTUC10)
+
+/** \brief C8, GTU Configuration Register 11 */
+#define ERAY0_GTUC11 /*lint --e(923)*/ (*(volatile Ifx_ERAY_GTUC11*)0xF001C0C8u)
+
+/** Alias (User Manual Name) for ERAY0_GTUC11.
+* To use register names with standard convension, please use ERAY0_GTUC11.
+*/
+#define ERAY_GTUC11 (ERAY0_GTUC11)
+
+/** \brief 510, Input Buffer Command Mask */
+#define ERAY0_IBCM /*lint --e(923)*/ (*(volatile Ifx_ERAY_IBCM*)0xF001C510u)
+
+/** Alias (User Manual Name) for ERAY0_IBCM.
+* To use register names with standard convension, please use ERAY0_IBCM.
+*/
+#define ERAY_IBCM (ERAY0_IBCM)
+
+/** \brief 514, Input Buffer Command Request */
+#define ERAY0_IBCR /*lint --e(923)*/ (*(volatile Ifx_ERAY_IBCR*)0xF001C514u)
+
+/** Alias (User Manual Name) for ERAY0_IBCR.
+* To use register names with standard convension, please use ERAY0_IBCR.
+*/
+#define ERAY_IBCR (ERAY0_IBCR)
+
+/** \brief 8, Module Identification Register */
+#define ERAY0_ID /*lint --e(923)*/ (*(volatile Ifx_ERAY_ID*)0xF001C008u)
+
+/** Alias (User Manual Name) for ERAY0_ID.
+* To use register names with standard convension, please use ERAY0_ID.
+*/
+#define ERAY_ID (ERAY0_ID)
+
+/** \brief 40, Service Request Line Enable */
+#define ERAY0_ILE /*lint --e(923)*/ (*(volatile Ifx_ERAY_ILE*)0xF001C040u)
+
+/** Alias (User Manual Name) for ERAY0_ILE.
+* To use register names with standard convension, please use ERAY0_ILE.
+*/
+#define ERAY_ILE (ERAY0_ILE)
+
+/** \brief 8F4, Kernel Reset Register 0 */
+#define ERAY0_KRST0 /*lint --e(923)*/ (*(volatile Ifx_ERAY_KRST0*)0xF001C8F4u)
+
+/** Alias (User Manual Name) for ERAY0_KRST0.
+* To use register names with standard convension, please use ERAY0_KRST0.
+*/
+#define ERAY_KRST0 (ERAY0_KRST0)
+
+/** \brief 8F0, Kernel Reset Register 1 */
+#define ERAY0_KRST1 /*lint --e(923)*/ (*(volatile Ifx_ERAY_KRST1*)0xF001C8F0u)
+
+/** Alias (User Manual Name) for ERAY0_KRST1.
+* To use register names with standard convension, please use ERAY0_KRST1.
+*/
+#define ERAY_KRST1 (ERAY0_KRST1)
+
+/** \brief 8EC, Kernel Reset Status Clear Register */
+#define ERAY0_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_ERAY_KRSTCLR*)0xF001C8ECu)
+
+/** Alias (User Manual Name) for ERAY0_KRSTCLR.
+* To use register names with standard convension, please use ERAY0_KRSTCLR.
+*/
+#define ERAY_KRSTCLR (ERAY0_KRSTCLR)
+
+/** \brief 1C, Lock Register */
+#define ERAY0_LCK /*lint --e(923)*/ (*(volatile Ifx_ERAY_LCK*)0xF001C01Cu)
+
+/** Alias (User Manual Name) for ERAY0_LCK.
+* To use register names with standard convension, please use ERAY0_LCK.
+*/
+#define ERAY_LCK (ERAY0_LCK)
+
+/** \brief 314, Last Dynamic Transmit Slot */
+#define ERAY0_LDTS /*lint --e(923)*/ (*(volatile Ifx_ERAY_LDTS*)0xF001C314u)
+
+/** Alias (User Manual Name) for ERAY0_LDTS.
+* To use register names with standard convension, please use ERAY0_LDTS.
+*/
+#define ERAY_LDTS (ERAY0_LDTS)
+
+/** \brief 70C, Message Buffer Status */
+#define ERAY0_MBS /*lint --e(923)*/ (*(volatile Ifx_ERAY_MBS*)0xF001C70Cu)
+
+/** Alias (User Manual Name) for ERAY0_MBS.
+* To use register names with standard convension, please use ERAY0_MBS.
+*/
+#define ERAY_MBS (ERAY0_MBS)
+
+/** \brief 340, Message Buffer Status Changed 1 */
+#define ERAY0_MBSC1 /*lint --e(923)*/ (*(volatile Ifx_ERAY_MBSC1*)0xF001C340u)
+
+/** Alias (User Manual Name) for ERAY0_MBSC1.
+* To use register names with standard convension, please use ERAY0_MBSC1.
+*/
+#define ERAY_MBSC1 (ERAY0_MBSC1)
+
+/** \brief 344, Message Buffer Status Changed 2 */
+#define ERAY0_MBSC2 /*lint --e(923)*/ (*(volatile Ifx_ERAY_MBSC2*)0xF001C344u)
+
+/** Alias (User Manual Name) for ERAY0_MBSC2.
+* To use register names with standard convension, please use ERAY0_MBSC2.
+*/
+#define ERAY_MBSC2 (ERAY0_MBSC2)
+
+/** \brief 348, Message Buffer Status Changed 3 */
+#define ERAY0_MBSC3 /*lint --e(923)*/ (*(volatile Ifx_ERAY_MBSC3*)0xF001C348u)
+
+/** Alias (User Manual Name) for ERAY0_MBSC3.
+* To use register names with standard convension, please use ERAY0_MBSC3.
+*/
+#define ERAY_MBSC3 (ERAY0_MBSC3)
+
+/** \brief 34C, Message Buffer Status Changed 4 */
+#define ERAY0_MBSC4 /*lint --e(923)*/ (*(volatile Ifx_ERAY_MBSC4*)0xF001C34Cu)
+
+/** Alias (User Manual Name) for ERAY0_MBSC4.
+* To use register names with standard convension, please use ERAY0_MBSC4.
+*/
+#define ERAY_MBSC4 (ERAY0_MBSC4)
+
+/** \brief 98, MHD Configuration Register */
+#define ERAY0_MHDC /*lint --e(923)*/ (*(volatile Ifx_ERAY_MHDC*)0xF001C098u)
+
+/** Alias (User Manual Name) for ERAY0_MHDC.
+* To use register names with standard convension, please use ERAY0_MHDC.
+*/
+#define ERAY_MHDC (ERAY0_MHDC)
+
+/** \brief 31C, Message Handler Constraints Flags */
+#define ERAY0_MHDF /*lint --e(923)*/ (*(volatile Ifx_ERAY_MHDF*)0xF001C31Cu)
+
+/** Alias (User Manual Name) for ERAY0_MHDF.
+* To use register names with standard convension, please use ERAY0_MHDF.
+*/
+#define ERAY_MHDF (ERAY0_MHDF)
+
+/** \brief 310, Message Handler Status */
+#define ERAY0_MHDS /*lint --e(923)*/ (*(volatile Ifx_ERAY_MHDS*)0xF001C310u)
+
+/** Alias (User Manual Name) for ERAY0_MHDS.
+* To use register names with standard convension, please use ERAY0_MHDS.
+*/
+#define ERAY_MHDS (ERAY0_MHDS)
+
+/** \brief 300, Message RAM Configuration */
+#define ERAY0_MRC /*lint --e(923)*/ (*(volatile Ifx_ERAY_MRC*)0xF001C300u)
+
+/** Alias (User Manual Name) for ERAY0_MRC.
+* To use register names with standard convension, please use ERAY0_MRC.
+*/
+#define ERAY_MRC (ERAY0_MRC)
+
+/** \brief 3B8, Message Buffer Status Changed Interrupt Control 1 */
+#define ERAY0_MSIC1 /*lint --e(923)*/ (*(volatile Ifx_ERAY_MSIC1*)0xF001C3B8u)
+
+/** Alias (User Manual Name) for ERAY0_MSIC1.
+* To use register names with standard convension, please use ERAY0_MSIC1.
+*/
+#define ERAY_MSIC1 (ERAY0_MSIC1)
+
+/** \brief 3BC, Message Buffer Status Changed Interrupt Control 2 */
+#define ERAY0_MSIC2 /*lint --e(923)*/ (*(volatile Ifx_ERAY_MSIC2*)0xF001C3BCu)
+
+/** Alias (User Manual Name) for ERAY0_MSIC2.
+* To use register names with standard convension, please use ERAY0_MSIC2.
+*/
+#define ERAY_MSIC2 (ERAY0_MSIC2)
+
+/** \brief 3C0, Message Buffer Status Changed Interrupt Control 3 */
+#define ERAY0_MSIC3 /*lint --e(923)*/ (*(volatile Ifx_ERAY_MSIC3*)0xF001C3C0u)
+
+/** Alias (User Manual Name) for ERAY0_MSIC3.
+* To use register names with standard convension, please use ERAY0_MSIC3.
+*/
+#define ERAY_MSIC3 (ERAY0_MSIC3)
+
+/** \brief 3C4, Message Buffer Status Changed Interrupt Control 4 */
+#define ERAY0_MSIC4 /*lint --e(923)*/ (*(volatile Ifx_ERAY_MSIC4*)0xF001C3C4u)
+
+/** Alias (User Manual Name) for ERAY0_MSIC4.
+* To use register names with standard convension, please use ERAY0_MSIC4.
+*/
+#define ERAY_MSIC4 (ERAY0_MSIC4)
+
+/** \brief 114, Macrotick and Cycle Counter Value */
+#define ERAY0_MTCCV /*lint --e(923)*/ (*(volatile Ifx_ERAY_MTCCV*)0xF001C114u)
+
+/** Alias (User Manual Name) for ERAY0_MTCCV.
+* To use register names with standard convension, please use ERAY0_MTCCV.
+*/
+#define ERAY_MTCCV (ERAY0_MTCCV)
+
+/** \brief 330, New Data Register 1 */
+#define ERAY0_NDAT1 /*lint --e(923)*/ (*(volatile Ifx_ERAY_NDAT1*)0xF001C330u)
+
+/** Alias (User Manual Name) for ERAY0_NDAT1.
+* To use register names with standard convension, please use ERAY0_NDAT1.
+*/
+#define ERAY_NDAT1 (ERAY0_NDAT1)
+
+/** \brief 334, New Data Register 2 */
+#define ERAY0_NDAT2 /*lint --e(923)*/ (*(volatile Ifx_ERAY_NDAT2*)0xF001C334u)
+
+/** Alias (User Manual Name) for ERAY0_NDAT2.
+* To use register names with standard convension, please use ERAY0_NDAT2.
+*/
+#define ERAY_NDAT2 (ERAY0_NDAT2)
+
+/** \brief 338, New Data Register 3 */
+#define ERAY0_NDAT3 /*lint --e(923)*/ (*(volatile Ifx_ERAY_NDAT3*)0xF001C338u)
+
+/** Alias (User Manual Name) for ERAY0_NDAT3.
+* To use register names with standard convension, please use ERAY0_NDAT3.
+*/
+#define ERAY_NDAT3 (ERAY0_NDAT3)
+
+/** \brief 33C, New Data Register 4 */
+#define ERAY0_NDAT4 /*lint --e(923)*/ (*(volatile Ifx_ERAY_NDAT4*)0xF001C33Cu)
+
+/** Alias (User Manual Name) for ERAY0_NDAT4.
+* To use register names with standard convension, please use ERAY0_NDAT4.
+*/
+#define ERAY_NDAT4 (ERAY0_NDAT4)
+
+/** \brief 3A8, New Data Interrupt Control 1 */
+#define ERAY0_NDIC1 /*lint --e(923)*/ (*(volatile Ifx_ERAY_NDIC1*)0xF001C3A8u)
+
+/** Alias (User Manual Name) for ERAY0_NDIC1.
+* To use register names with standard convension, please use ERAY0_NDIC1.
+*/
+#define ERAY_NDIC1 (ERAY0_NDIC1)
+
+/** \brief 3AC, New Data Interrupt Control 2 */
+#define ERAY0_NDIC2 /*lint --e(923)*/ (*(volatile Ifx_ERAY_NDIC2*)0xF001C3ACu)
+
+/** Alias (User Manual Name) for ERAY0_NDIC2.
+* To use register names with standard convension, please use ERAY0_NDIC2.
+*/
+#define ERAY_NDIC2 (ERAY0_NDIC2)
+
+/** \brief 3B0, New Data Interrupt Control 3 */
+#define ERAY0_NDIC3 /*lint --e(923)*/ (*(volatile Ifx_ERAY_NDIC3*)0xF001C3B0u)
+
+/** Alias (User Manual Name) for ERAY0_NDIC3.
+* To use register names with standard convension, please use ERAY0_NDIC3.
+*/
+#define ERAY_NDIC3 (ERAY0_NDIC3)
+
+/** \brief 3B4, New Data Interrupt Control 4 */
+#define ERAY0_NDIC4 /*lint --e(923)*/ (*(volatile Ifx_ERAY_NDIC4*)0xF001C3B4u)
+
+/** Alias (User Manual Name) for ERAY0_NDIC4.
+* To use register names with standard convension, please use ERAY0_NDIC4.
+*/
+#define ERAY_NDIC4 (ERAY0_NDIC4)
+
+/** \brief 8C, NEM Configuration Register */
+#define ERAY0_NEMC /*lint --e(923)*/ (*(volatile Ifx_ERAY_NEMC*)0xF001C08Cu)
+
+/** Alias (User Manual Name) for ERAY0_NEMC.
+* To use register names with standard convension, please use ERAY0_NEMC.
+*/
+#define ERAY_NEMC (ERAY0_NEMC)
+
+/** \brief 1B0, Network Management Vector \note Array index shifted by 1.
+ * Example: defined register NMV_1S[0]/NMV_1S0 corresponds to user manual
+ * NMV_1S1, ... */
+#define ERAY0_NMV_1S0 /*lint --e(923)*/ (*(volatile Ifx_ERAY_NMV*)0xF001C1B0u)
+
+/** Alias (User Manual Name) for ERAY0_NMV_1S0.
+* To use register names with standard convension, please use ERAY0_NMV_1S0.
+*/
+#define ERAY_NMV1 (ERAY0_NMV_1S0)
+
+/** \brief 1B4, Network Management Vector \note Array index shifted by 1.
+ * Example: defined register NMV_1S[0]/NMV_1S0 corresponds to user manual
+ * NMV_1S1, ... */
+#define ERAY0_NMV_1S1 /*lint --e(923)*/ (*(volatile Ifx_ERAY_NMV*)0xF001C1B4u)
+
+/** Alias (User Manual Name) for ERAY0_NMV_1S1.
+* To use register names with standard convension, please use ERAY0_NMV_1S1.
+*/
+#define ERAY_NMV2 (ERAY0_NMV_1S1)
+
+/** \brief 1B8, Network Management Vector \note Array index shifted by 1.
+ * Example: defined register NMV_1S[0]/NMV_1S0 corresponds to user manual
+ * NMV_1S1, ... */
+#define ERAY0_NMV_1S2 /*lint --e(923)*/ (*(volatile Ifx_ERAY_NMV*)0xF001C1B8u)
+
+/** Alias (User Manual Name) for ERAY0_NMV_1S2.
+* To use register names with standard convension, please use ERAY0_NMV_1S2.
+*/
+#define ERAY_NMV3 (ERAY0_NMV_1S2)
+
+/** \brief 710, Output Buffer Command Mask */
+#define ERAY0_OBCM /*lint --e(923)*/ (*(volatile Ifx_ERAY_OBCM*)0xF001C710u)
+
+/** Alias (User Manual Name) for ERAY0_OBCM.
+* To use register names with standard convension, please use ERAY0_OBCM.
+*/
+#define ERAY_OBCM (ERAY0_OBCM)
+
+/** \brief 714, Output Buffer Command Request */
+#define ERAY0_OBCR /*lint --e(923)*/ (*(volatile Ifx_ERAY_OBCR*)0xF001C714u)
+
+/** Alias (User Manual Name) for ERAY0_OBCR.
+* To use register names with standard convension, please use ERAY0_OBCR.
+*/
+#define ERAY_OBCR (ERAY0_OBCR)
+
+/** \brief 8E8, OCDS Control and Status */
+#define ERAY0_OCS /*lint --e(923)*/ (*(volatile Ifx_ERAY_OCS*)0xF001C8E8u)
+
+/** Alias (User Manual Name) for ERAY0_OCS.
+* To use register names with standard convension, please use ERAY0_OCS.
+*/
+#define ERAY_OCS (ERAY0_OCS)
+
+/** \brief 11C, Offset Correction Value */
+#define ERAY0_OCV /*lint --e(923)*/ (*(volatile Ifx_ERAY_OCV*)0xF001C11Cu)
+
+/** Alias (User Manual Name) for ERAY0_OCV.
+* To use register names with standard convension, please use ERAY0_OCV.
+*/
+#define ERAY_OCV (ERAY0_OCV)
+
+/** \brief 170, Odd Sync ID Symbol Window \note Array index shifted by 1.
+ * Example: defined register OSID_1S[0]/OSID_1S0 corresponds to user manual
+ * OSID_1S1, ... */
+#define ERAY0_OSID_1S0 /*lint --e(923)*/ (*(volatile Ifx_ERAY_OSID*)0xF001C170u)
+
+/** Alias (User Manual Name) for ERAY0_OSID_1S0.
+* To use register names with standard convension, please use ERAY0_OSID_1S0.
+*/
+#define ERAY_OSID01 (ERAY0_OSID_1S0)
+
+/** \brief 174, Odd Sync ID Symbol Window \note Array index shifted by 1.
+ * Example: defined register OSID_1S[0]/OSID_1S0 corresponds to user manual
+ * OSID_1S1, ... */
+#define ERAY0_OSID_1S1 /*lint --e(923)*/ (*(volatile Ifx_ERAY_OSID*)0xF001C174u)
+
+/** Alias (User Manual Name) for ERAY0_OSID_1S1.
+* To use register names with standard convension, please use ERAY0_OSID_1S1.
+*/
+#define ERAY_OSID02 (ERAY0_OSID_1S1)
+
+/** \brief 198, Odd Sync ID Symbol Window \note Array index shifted by 1.
+ * Example: defined register OSID_1S[0]/OSID_1S0 corresponds to user manual
+ * OSID_1S1, ... */
+#define ERAY0_OSID_1S10 /*lint --e(923)*/ (*(volatile Ifx_ERAY_OSID*)0xF001C198u)
+
+/** Alias (User Manual Name) for ERAY0_OSID_1S10.
+* To use register names with standard convension, please use ERAY0_OSID_1S10.
+*/
+#define ERAY_OSID11 (ERAY0_OSID_1S10)
+
+/** \brief 19C, Odd Sync ID Symbol Window \note Array index shifted by 1.
+ * Example: defined register OSID_1S[0]/OSID_1S0 corresponds to user manual
+ * OSID_1S1, ... */
+#define ERAY0_OSID_1S11 /*lint --e(923)*/ (*(volatile Ifx_ERAY_OSID*)0xF001C19Cu)
+
+/** Alias (User Manual Name) for ERAY0_OSID_1S11.
+* To use register names with standard convension, please use ERAY0_OSID_1S11.
+*/
+#define ERAY_OSID12 (ERAY0_OSID_1S11)
+
+/** \brief 1A0, Odd Sync ID Symbol Window \note Array index shifted by 1.
+ * Example: defined register OSID_1S[0]/OSID_1S0 corresponds to user manual
+ * OSID_1S1, ... */
+#define ERAY0_OSID_1S12 /*lint --e(923)*/ (*(volatile Ifx_ERAY_OSID*)0xF001C1A0u)
+
+/** Alias (User Manual Name) for ERAY0_OSID_1S12.
+* To use register names with standard convension, please use ERAY0_OSID_1S12.
+*/
+#define ERAY_OSID13 (ERAY0_OSID_1S12)
+
+/** \brief 1A4, Odd Sync ID Symbol Window \note Array index shifted by 1.
+ * Example: defined register OSID_1S[0]/OSID_1S0 corresponds to user manual
+ * OSID_1S1, ... */
+#define ERAY0_OSID_1S13 /*lint --e(923)*/ (*(volatile Ifx_ERAY_OSID*)0xF001C1A4u)
+
+/** Alias (User Manual Name) for ERAY0_OSID_1S13.
+* To use register names with standard convension, please use ERAY0_OSID_1S13.
+*/
+#define ERAY_OSID14 (ERAY0_OSID_1S13)
+
+/** \brief 1A8, Odd Sync ID Symbol Window \note Array index shifted by 1.
+ * Example: defined register OSID_1S[0]/OSID_1S0 corresponds to user manual
+ * OSID_1S1, ... */
+#define ERAY0_OSID_1S14 /*lint --e(923)*/ (*(volatile Ifx_ERAY_OSID*)0xF001C1A8u)
+
+/** Alias (User Manual Name) for ERAY0_OSID_1S14.
+* To use register names with standard convension, please use ERAY0_OSID_1S14.
+*/
+#define ERAY_OSID15 (ERAY0_OSID_1S14)
+
+/** \brief 178, Odd Sync ID Symbol Window \note Array index shifted by 1.
+ * Example: defined register OSID_1S[0]/OSID_1S0 corresponds to user manual
+ * OSID_1S1, ... */
+#define ERAY0_OSID_1S2 /*lint --e(923)*/ (*(volatile Ifx_ERAY_OSID*)0xF001C178u)
+
+/** Alias (User Manual Name) for ERAY0_OSID_1S2.
+* To use register names with standard convension, please use ERAY0_OSID_1S2.
+*/
+#define ERAY_OSID03 (ERAY0_OSID_1S2)
+
+/** \brief 17C, Odd Sync ID Symbol Window \note Array index shifted by 1.
+ * Example: defined register OSID_1S[0]/OSID_1S0 corresponds to user manual
+ * OSID_1S1, ... */
+#define ERAY0_OSID_1S3 /*lint --e(923)*/ (*(volatile Ifx_ERAY_OSID*)0xF001C17Cu)
+
+/** Alias (User Manual Name) for ERAY0_OSID_1S3.
+* To use register names with standard convension, please use ERAY0_OSID_1S3.
+*/
+#define ERAY_OSID04 (ERAY0_OSID_1S3)
+
+/** \brief 180, Odd Sync ID Symbol Window \note Array index shifted by 1.
+ * Example: defined register OSID_1S[0]/OSID_1S0 corresponds to user manual
+ * OSID_1S1, ... */
+#define ERAY0_OSID_1S4 /*lint --e(923)*/ (*(volatile Ifx_ERAY_OSID*)0xF001C180u)
+
+/** Alias (User Manual Name) for ERAY0_OSID_1S4.
+* To use register names with standard convension, please use ERAY0_OSID_1S4.
+*/
+#define ERAY_OSID05 (ERAY0_OSID_1S4)
+
+/** \brief 184, Odd Sync ID Symbol Window \note Array index shifted by 1.
+ * Example: defined register OSID_1S[0]/OSID_1S0 corresponds to user manual
+ * OSID_1S1, ... */
+#define ERAY0_OSID_1S5 /*lint --e(923)*/ (*(volatile Ifx_ERAY_OSID*)0xF001C184u)
+
+/** Alias (User Manual Name) for ERAY0_OSID_1S5.
+* To use register names with standard convension, please use ERAY0_OSID_1S5.
+*/
+#define ERAY_OSID06 (ERAY0_OSID_1S5)
+
+/** \brief 188, Odd Sync ID Symbol Window \note Array index shifted by 1.
+ * Example: defined register OSID_1S[0]/OSID_1S0 corresponds to user manual
+ * OSID_1S1, ... */
+#define ERAY0_OSID_1S6 /*lint --e(923)*/ (*(volatile Ifx_ERAY_OSID*)0xF001C188u)
+
+/** Alias (User Manual Name) for ERAY0_OSID_1S6.
+* To use register names with standard convension, please use ERAY0_OSID_1S6.
+*/
+#define ERAY_OSID07 (ERAY0_OSID_1S6)
+
+/** \brief 18C, Odd Sync ID Symbol Window \note Array index shifted by 1.
+ * Example: defined register OSID_1S[0]/OSID_1S0 corresponds to user manual
+ * OSID_1S1, ... */
+#define ERAY0_OSID_1S7 /*lint --e(923)*/ (*(volatile Ifx_ERAY_OSID*)0xF001C18Cu)
+
+/** Alias (User Manual Name) for ERAY0_OSID_1S7.
+* To use register names with standard convension, please use ERAY0_OSID_1S7.
+*/
+#define ERAY_OSID08 (ERAY0_OSID_1S7)
+
+/** \brief 190, Odd Sync ID Symbol Window \note Array index shifted by 1.
+ * Example: defined register OSID_1S[0]/OSID_1S0 corresponds to user manual
+ * OSID_1S1, ... */
+#define ERAY0_OSID_1S8 /*lint --e(923)*/ (*(volatile Ifx_ERAY_OSID*)0xF001C190u)
+
+/** Alias (User Manual Name) for ERAY0_OSID_1S8.
+* To use register names with standard convension, please use ERAY0_OSID_1S8.
+*/
+#define ERAY_OSID09 (ERAY0_OSID_1S8)
+
+/** \brief 194, Odd Sync ID Symbol Window \note Array index shifted by 1.
+ * Example: defined register OSID_1S[0]/OSID_1S0 corresponds to user manual
+ * OSID_1S1, ... */
+#define ERAY0_OSID_1S9 /*lint --e(923)*/ (*(volatile Ifx_ERAY_OSID*)0xF001C194u)
+
+/** Alias (User Manual Name) for ERAY0_OSID_1S9.
+* To use register names with standard convension, please use ERAY0_OSID_1S9.
+*/
+#define ERAY_OSID10 (ERAY0_OSID_1S9)
+
+/** \brief 870, OCDS Trigger Set Select */
+#define ERAY0_OTSS /*lint --e(923)*/ (*(volatile Ifx_ERAY_OTSS*)0xF001C870u)
+
+/** Alias (User Manual Name) for ERAY0_OTSS.
+* To use register names with standard convension, please use ERAY0_OTSS.
+*/
+#define ERAY_OTSS (ERAY0_OTSS)
+
+/** \brief 90, PRT Configuration Register 1 */
+#define ERAY0_PRTC1 /*lint --e(923)*/ (*(volatile Ifx_ERAY_PRTC1*)0xF001C090u)
+
+/** Alias (User Manual Name) for ERAY0_PRTC1.
+* To use register names with standard convension, please use ERAY0_PRTC1.
+*/
+#define ERAY_PRTC1 (ERAY0_PRTC1)
+
+/** \brief 94, PRT Configuration Register 2 */
+#define ERAY0_PRTC2 /*lint --e(923)*/ (*(volatile Ifx_ERAY_PRTC2*)0xF001C094u)
+
+/** Alias (User Manual Name) for ERAY0_PRTC2.
+* To use register names with standard convension, please use ERAY0_PRTC2.
+*/
+#define ERAY_PRTC2 (ERAY0_PRTC2)
+
+/** \brief 118, Rate Correction Value */
+#define ERAY0_RCV /*lint --e(923)*/ (*(volatile Ifx_ERAY_RCV*)0xF001C118u)
+
+/** Alias (User Manual Name) for ERAY0_RCV.
+* To use register names with standard convension, please use ERAY0_RCV.
+*/
+#define ERAY_RCV (ERAY0_RCV)
+
+/** \brief 600, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S0 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C600u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S0.
+* To use register names with standard convension, please use ERAY0_RDDS_1S0.
+*/
+#define ERAY_RDDS01 (ERAY0_RDDS_1S0)
+
+/** \brief 604, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S1 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C604u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S1.
+* To use register names with standard convension, please use ERAY0_RDDS_1S1.
+*/
+#define ERAY_RDDS02 (ERAY0_RDDS_1S1)
+
+/** \brief 628, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S10 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C628u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S10.
+* To use register names with standard convension, please use ERAY0_RDDS_1S10.
+*/
+#define ERAY_RDDS11 (ERAY0_RDDS_1S10)
+
+/** \brief 62C, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S11 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C62Cu)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S11.
+* To use register names with standard convension, please use ERAY0_RDDS_1S11.
+*/
+#define ERAY_RDDS12 (ERAY0_RDDS_1S11)
+
+/** \brief 630, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S12 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C630u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S12.
+* To use register names with standard convension, please use ERAY0_RDDS_1S12.
+*/
+#define ERAY_RDDS13 (ERAY0_RDDS_1S12)
+
+/** \brief 634, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S13 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C634u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S13.
+* To use register names with standard convension, please use ERAY0_RDDS_1S13.
+*/
+#define ERAY_RDDS14 (ERAY0_RDDS_1S13)
+
+/** \brief 638, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S14 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C638u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S14.
+* To use register names with standard convension, please use ERAY0_RDDS_1S14.
+*/
+#define ERAY_RDDS15 (ERAY0_RDDS_1S14)
+
+/** \brief 63C, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S15 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C63Cu)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S15.
+* To use register names with standard convension, please use ERAY0_RDDS_1S15.
+*/
+#define ERAY_RDDS16 (ERAY0_RDDS_1S15)
+
+/** \brief 640, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S16 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C640u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S16.
+* To use register names with standard convension, please use ERAY0_RDDS_1S16.
+*/
+#define ERAY_RDDS17 (ERAY0_RDDS_1S16)
+
+/** \brief 644, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S17 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C644u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S17.
+* To use register names with standard convension, please use ERAY0_RDDS_1S17.
+*/
+#define ERAY_RDDS18 (ERAY0_RDDS_1S17)
+
+/** \brief 648, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S18 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C648u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S18.
+* To use register names with standard convension, please use ERAY0_RDDS_1S18.
+*/
+#define ERAY_RDDS19 (ERAY0_RDDS_1S18)
+
+/** \brief 64C, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S19 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C64Cu)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S19.
+* To use register names with standard convension, please use ERAY0_RDDS_1S19.
+*/
+#define ERAY_RDDS20 (ERAY0_RDDS_1S19)
+
+/** \brief 608, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S2 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C608u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S2.
+* To use register names with standard convension, please use ERAY0_RDDS_1S2.
+*/
+#define ERAY_RDDS03 (ERAY0_RDDS_1S2)
+
+/** \brief 650, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S20 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C650u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S20.
+* To use register names with standard convension, please use ERAY0_RDDS_1S20.
+*/
+#define ERAY_RDDS21 (ERAY0_RDDS_1S20)
+
+/** \brief 654, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S21 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C654u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S21.
+* To use register names with standard convension, please use ERAY0_RDDS_1S21.
+*/
+#define ERAY_RDDS22 (ERAY0_RDDS_1S21)
+
+/** \brief 658, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S22 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C658u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S22.
+* To use register names with standard convension, please use ERAY0_RDDS_1S22.
+*/
+#define ERAY_RDDS23 (ERAY0_RDDS_1S22)
+
+/** \brief 65C, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S23 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C65Cu)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S23.
+* To use register names with standard convension, please use ERAY0_RDDS_1S23.
+*/
+#define ERAY_RDDS24 (ERAY0_RDDS_1S23)
+
+/** \brief 660, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S24 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C660u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S24.
+* To use register names with standard convension, please use ERAY0_RDDS_1S24.
+*/
+#define ERAY_RDDS25 (ERAY0_RDDS_1S24)
+
+/** \brief 664, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S25 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C664u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S25.
+* To use register names with standard convension, please use ERAY0_RDDS_1S25.
+*/
+#define ERAY_RDDS26 (ERAY0_RDDS_1S25)
+
+/** \brief 668, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S26 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C668u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S26.
+* To use register names with standard convension, please use ERAY0_RDDS_1S26.
+*/
+#define ERAY_RDDS27 (ERAY0_RDDS_1S26)
+
+/** \brief 66C, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S27 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C66Cu)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S27.
+* To use register names with standard convension, please use ERAY0_RDDS_1S27.
+*/
+#define ERAY_RDDS28 (ERAY0_RDDS_1S27)
+
+/** \brief 670, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S28 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C670u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S28.
+* To use register names with standard convension, please use ERAY0_RDDS_1S28.
+*/
+#define ERAY_RDDS29 (ERAY0_RDDS_1S28)
+
+/** \brief 674, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S29 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C674u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S29.
+* To use register names with standard convension, please use ERAY0_RDDS_1S29.
+*/
+#define ERAY_RDDS30 (ERAY0_RDDS_1S29)
+
+/** \brief 60C, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S3 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C60Cu)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S3.
+* To use register names with standard convension, please use ERAY0_RDDS_1S3.
+*/
+#define ERAY_RDDS04 (ERAY0_RDDS_1S3)
+
+/** \brief 678, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S30 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C678u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S30.
+* To use register names with standard convension, please use ERAY0_RDDS_1S30.
+*/
+#define ERAY_RDDS31 (ERAY0_RDDS_1S30)
+
+/** \brief 67C, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S31 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C67Cu)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S31.
+* To use register names with standard convension, please use ERAY0_RDDS_1S31.
+*/
+#define ERAY_RDDS32 (ERAY0_RDDS_1S31)
+
+/** \brief 680, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S32 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C680u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S32.
+* To use register names with standard convension, please use ERAY0_RDDS_1S32.
+*/
+#define ERAY_RDDS33 (ERAY0_RDDS_1S32)
+
+/** \brief 684, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S33 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C684u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S33.
+* To use register names with standard convension, please use ERAY0_RDDS_1S33.
+*/
+#define ERAY_RDDS34 (ERAY0_RDDS_1S33)
+
+/** \brief 688, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S34 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C688u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S34.
+* To use register names with standard convension, please use ERAY0_RDDS_1S34.
+*/
+#define ERAY_RDDS35 (ERAY0_RDDS_1S34)
+
+/** \brief 68C, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S35 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C68Cu)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S35.
+* To use register names with standard convension, please use ERAY0_RDDS_1S35.
+*/
+#define ERAY_RDDS36 (ERAY0_RDDS_1S35)
+
+/** \brief 690, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S36 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C690u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S36.
+* To use register names with standard convension, please use ERAY0_RDDS_1S36.
+*/
+#define ERAY_RDDS37 (ERAY0_RDDS_1S36)
+
+/** \brief 694, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S37 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C694u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S37.
+* To use register names with standard convension, please use ERAY0_RDDS_1S37.
+*/
+#define ERAY_RDDS38 (ERAY0_RDDS_1S37)
+
+/** \brief 698, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S38 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C698u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S38.
+* To use register names with standard convension, please use ERAY0_RDDS_1S38.
+*/
+#define ERAY_RDDS39 (ERAY0_RDDS_1S38)
+
+/** \brief 69C, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S39 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C69Cu)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S39.
+* To use register names with standard convension, please use ERAY0_RDDS_1S39.
+*/
+#define ERAY_RDDS40 (ERAY0_RDDS_1S39)
+
+/** \brief 610, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S4 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C610u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S4.
+* To use register names with standard convension, please use ERAY0_RDDS_1S4.
+*/
+#define ERAY_RDDS05 (ERAY0_RDDS_1S4)
+
+/** \brief 6A0, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S40 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C6A0u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S40.
+* To use register names with standard convension, please use ERAY0_RDDS_1S40.
+*/
+#define ERAY_RDDS41 (ERAY0_RDDS_1S40)
+
+/** \brief 6A4, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S41 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C6A4u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S41.
+* To use register names with standard convension, please use ERAY0_RDDS_1S41.
+*/
+#define ERAY_RDDS42 (ERAY0_RDDS_1S41)
+
+/** \brief 6A8, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S42 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C6A8u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S42.
+* To use register names with standard convension, please use ERAY0_RDDS_1S42.
+*/
+#define ERAY_RDDS43 (ERAY0_RDDS_1S42)
+
+/** \brief 6AC, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S43 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C6ACu)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S43.
+* To use register names with standard convension, please use ERAY0_RDDS_1S43.
+*/
+#define ERAY_RDDS44 (ERAY0_RDDS_1S43)
+
+/** \brief 6B0, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S44 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C6B0u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S44.
+* To use register names with standard convension, please use ERAY0_RDDS_1S44.
+*/
+#define ERAY_RDDS45 (ERAY0_RDDS_1S44)
+
+/** \brief 6B4, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S45 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C6B4u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S45.
+* To use register names with standard convension, please use ERAY0_RDDS_1S45.
+*/
+#define ERAY_RDDS46 (ERAY0_RDDS_1S45)
+
+/** \brief 6B8, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S46 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C6B8u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S46.
+* To use register names with standard convension, please use ERAY0_RDDS_1S46.
+*/
+#define ERAY_RDDS47 (ERAY0_RDDS_1S46)
+
+/** \brief 6BC, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S47 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C6BCu)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S47.
+* To use register names with standard convension, please use ERAY0_RDDS_1S47.
+*/
+#define ERAY_RDDS48 (ERAY0_RDDS_1S47)
+
+/** \brief 6C0, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S48 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C6C0u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S48.
+* To use register names with standard convension, please use ERAY0_RDDS_1S48.
+*/
+#define ERAY_RDDS49 (ERAY0_RDDS_1S48)
+
+/** \brief 6C4, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S49 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C6C4u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S49.
+* To use register names with standard convension, please use ERAY0_RDDS_1S49.
+*/
+#define ERAY_RDDS50 (ERAY0_RDDS_1S49)
+
+/** \brief 614, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S5 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C614u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S5.
+* To use register names with standard convension, please use ERAY0_RDDS_1S5.
+*/
+#define ERAY_RDDS06 (ERAY0_RDDS_1S5)
+
+/** \brief 6C8, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S50 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C6C8u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S50.
+* To use register names with standard convension, please use ERAY0_RDDS_1S50.
+*/
+#define ERAY_RDDS51 (ERAY0_RDDS_1S50)
+
+/** \brief 6CC, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S51 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C6CCu)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S51.
+* To use register names with standard convension, please use ERAY0_RDDS_1S51.
+*/
+#define ERAY_RDDS52 (ERAY0_RDDS_1S51)
+
+/** \brief 6D0, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S52 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C6D0u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S52.
+* To use register names with standard convension, please use ERAY0_RDDS_1S52.
+*/
+#define ERAY_RDDS53 (ERAY0_RDDS_1S52)
+
+/** \brief 6D4, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S53 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C6D4u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S53.
+* To use register names with standard convension, please use ERAY0_RDDS_1S53.
+*/
+#define ERAY_RDDS54 (ERAY0_RDDS_1S53)
+
+/** \brief 6D8, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S54 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C6D8u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S54.
+* To use register names with standard convension, please use ERAY0_RDDS_1S54.
+*/
+#define ERAY_RDDS55 (ERAY0_RDDS_1S54)
+
+/** \brief 6DC, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S55 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C6DCu)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S55.
+* To use register names with standard convension, please use ERAY0_RDDS_1S55.
+*/
+#define ERAY_RDDS56 (ERAY0_RDDS_1S55)
+
+/** \brief 6E0, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S56 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C6E0u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S56.
+* To use register names with standard convension, please use ERAY0_RDDS_1S56.
+*/
+#define ERAY_RDDS57 (ERAY0_RDDS_1S56)
+
+/** \brief 6E4, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S57 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C6E4u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S57.
+* To use register names with standard convension, please use ERAY0_RDDS_1S57.
+*/
+#define ERAY_RDDS58 (ERAY0_RDDS_1S57)
+
+/** \brief 6E8, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S58 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C6E8u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S58.
+* To use register names with standard convension, please use ERAY0_RDDS_1S58.
+*/
+#define ERAY_RDDS59 (ERAY0_RDDS_1S58)
+
+/** \brief 6EC, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S59 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C6ECu)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S59.
+* To use register names with standard convension, please use ERAY0_RDDS_1S59.
+*/
+#define ERAY_RDDS60 (ERAY0_RDDS_1S59)
+
+/** \brief 618, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S6 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C618u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S6.
+* To use register names with standard convension, please use ERAY0_RDDS_1S6.
+*/
+#define ERAY_RDDS07 (ERAY0_RDDS_1S6)
+
+/** \brief 6F0, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S60 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C6F0u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S60.
+* To use register names with standard convension, please use ERAY0_RDDS_1S60.
+*/
+#define ERAY_RDDS61 (ERAY0_RDDS_1S60)
+
+/** \brief 6F4, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S61 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C6F4u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S61.
+* To use register names with standard convension, please use ERAY0_RDDS_1S61.
+*/
+#define ERAY_RDDS62 (ERAY0_RDDS_1S61)
+
+/** \brief 6F8, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S62 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C6F8u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S62.
+* To use register names with standard convension, please use ERAY0_RDDS_1S62.
+*/
+#define ERAY_RDDS63 (ERAY0_RDDS_1S62)
+
+/** \brief 6FC, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S63 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C6FCu)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S63.
+* To use register names with standard convension, please use ERAY0_RDDS_1S63.
+*/
+#define ERAY_RDDS64 (ERAY0_RDDS_1S63)
+
+/** \brief 61C, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S7 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C61Cu)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S7.
+* To use register names with standard convension, please use ERAY0_RDDS_1S7.
+*/
+#define ERAY_RDDS08 (ERAY0_RDDS_1S7)
+
+/** \brief 620, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S8 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C620u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S8.
+* To use register names with standard convension, please use ERAY0_RDDS_1S8.
+*/
+#define ERAY_RDDS09 (ERAY0_RDDS_1S8)
+
+/** \brief 624, Read Data Section \note Array index shifted by 1. Example:
+ * defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+#define ERAY0_RDDS_1S9 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDDS*)0xF001C624u)
+
+/** Alias (User Manual Name) for ERAY0_RDDS_1S9.
+* To use register names with standard convension, please use ERAY0_RDDS_1S9.
+*/
+#define ERAY_RDDS10 (ERAY0_RDDS_1S9)
+
+/** \brief 700, Read Header Section 1 */
+#define ERAY0_RDHS1 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDHS1*)0xF001C700u)
+
+/** Alias (User Manual Name) for ERAY0_RDHS1.
+* To use register names with standard convension, please use ERAY0_RDHS1.
+*/
+#define ERAY_RDHS1 (ERAY0_RDHS1)
+
+/** \brief 704, Read Header Section 2 */
+#define ERAY0_RDHS2 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDHS2*)0xF001C704u)
+
+/** Alias (User Manual Name) for ERAY0_RDHS2.
+* To use register names with standard convension, please use ERAY0_RDHS2.
+*/
+#define ERAY_RDHS2 (ERAY0_RDHS2)
+
+/** \brief 708, Read Header Section 3 */
+#define ERAY0_RDHS3 /*lint --e(923)*/ (*(volatile Ifx_ERAY_RDHS3*)0xF001C708u)
+
+/** Alias (User Manual Name) for ERAY0_RDHS3.
+* To use register names with standard convension, please use ERAY0_RDHS3.
+*/
+#define ERAY_RDHS3 (ERAY0_RDHS3)
+
+/** \brief 110, Slot Counter Value */
+#define ERAY0_SCV /*lint --e(923)*/ (*(volatile Ifx_ERAY_SCV*)0xF001C110u)
+
+/** Alias (User Manual Name) for ERAY0_SCV.
+* To use register names with standard convension, please use ERAY0_SCV.
+*/
+#define ERAY_SCV (ERAY0_SCV)
+
+/** \brief 120, SYNC Frame Status */
+#define ERAY0_SFS /*lint --e(923)*/ (*(volatile Ifx_ERAY_SFS*)0xF001C120u)
+
+/** Alias (User Manual Name) for ERAY0_SFS.
+* To use register names with standard convension, please use ERAY0_SFS.
+*/
+#define ERAY_SFS (ERAY0_SFS)
+
+/** \brief 3C, Status Service Request Enable Reset */
+#define ERAY0_SIER /*lint --e(923)*/ (*(volatile Ifx_ERAY_SIER*)0xF001C03Cu)
+
+/** Alias (User Manual Name) for ERAY0_SIER.
+* To use register names with standard convension, please use ERAY0_SIER.
+*/
+#define ERAY_SIER (ERAY0_SIER)
+
+/** \brief 38, Status Service Request Enable Set */
+#define ERAY0_SIES /*lint --e(923)*/ (*(volatile Ifx_ERAY_SIES*)0xF001C038u)
+
+/** Alias (User Manual Name) for ERAY0_SIES.
+* To use register names with standard convension, please use ERAY0_SIES.
+*/
+#define ERAY_SIES (ERAY0_SIES)
+
+/** \brief 2C, Status Service Request Line Select */
+#define ERAY0_SILS /*lint --e(923)*/ (*(volatile Ifx_ERAY_SILS*)0xF001C02Cu)
+
+/** Alias (User Manual Name) for ERAY0_SILS.
+* To use register names with standard convension, please use ERAY0_SILS.
+*/
+#define ERAY_SILS (ERAY0_SILS)
+
+/** \brief 24, Status Service Request Register */
+#define ERAY0_SIR /*lint --e(923)*/ (*(volatile Ifx_ERAY_SIR*)0xF001C024u)
+
+/** Alias (User Manual Name) for ERAY0_SIR.
+* To use register names with standard convension, please use ERAY0_SIR.
+*/
+#define ERAY_SIR (ERAY0_SIR)
+
+/** \brief 4C, Stop Watch Register 1 */
+#define ERAY0_STPW1 /*lint --e(923)*/ (*(volatile Ifx_ERAY_STPW1*)0xF001C04Cu)
+
+/** Alias (User Manual Name) for ERAY0_STPW1.
+* To use register names with standard convension, please use ERAY0_STPW1.
+*/
+#define ERAY_STPW1 (ERAY0_STPW1)
+
+/** \brief 50, Stop Watch Register 2 */
+#define ERAY0_STPW2 /*lint --e(923)*/ (*(volatile Ifx_ERAY_STPW2*)0xF001C050u)
+
+/** Alias (User Manual Name) for ERAY0_STPW2.
+* To use register names with standard convension, please use ERAY0_STPW2.
+*/
+#define ERAY_STPW2 (ERAY0_STPW2)
+
+/** \brief 80, SUC Configuration Register 1 */
+#define ERAY0_SUCC1 /*lint --e(923)*/ (*(volatile Ifx_ERAY_SUCC1*)0xF001C080u)
+
+/** Alias (User Manual Name) for ERAY0_SUCC1.
+* To use register names with standard convension, please use ERAY0_SUCC1.
+*/
+#define ERAY_SUCC1 (ERAY0_SUCC1)
+
+/** \brief 84, SUC Configuration Register 2 */
+#define ERAY0_SUCC2 /*lint --e(923)*/ (*(volatile Ifx_ERAY_SUCC2*)0xF001C084u)
+
+/** Alias (User Manual Name) for ERAY0_SUCC2.
+* To use register names with standard convension, please use ERAY0_SUCC2.
+*/
+#define ERAY_SUCC2 (ERAY0_SUCC2)
+
+/** \brief 88, SUC Configuration Register 3 */
+#define ERAY0_SUCC3 /*lint --e(923)*/ (*(volatile Ifx_ERAY_SUCC3*)0xF001C088u)
+
+/** Alias (User Manual Name) for ERAY0_SUCC3.
+* To use register names with standard convension, please use ERAY0_SUCC3.
+*/
+#define ERAY_SUCC3 (ERAY0_SUCC3)
+
+/** \brief 124, Symbol Window and Network Idle Time Status */
+#define ERAY0_SWNIT /*lint --e(923)*/ (*(volatile Ifx_ERAY_SWNIT*)0xF001C124u)
+
+/** Alias (User Manual Name) for ERAY0_SWNIT.
+* To use register names with standard convension, please use ERAY0_SWNIT.
+*/
+#define ERAY_SWNIT (ERAY0_SWNIT)
+
+/** \brief 44, Timer 0 Configuration */
+#define ERAY0_T0C /*lint --e(923)*/ (*(volatile Ifx_ERAY_T0C*)0xF001C044u)
+
+/** Alias (User Manual Name) for ERAY0_T0C.
+* To use register names with standard convension, please use ERAY0_T0C.
+*/
+#define ERAY_T0C (ERAY0_T0C)
+
+/** \brief 48, Timer 1 Configuration */
+#define ERAY0_T1C /*lint --e(923)*/ (*(volatile Ifx_ERAY_T1C*)0xF001C048u)
+
+/** Alias (User Manual Name) for ERAY0_T1C.
+* To use register names with standard convension, please use ERAY0_T1C.
+*/
+#define ERAY_T1C (ERAY0_T1C)
+
+/** \brief 10, Test Register 1 */
+#define ERAY0_TEST1 /*lint --e(923)*/ (*(volatile Ifx_ERAY_TEST1*)0xF001C010u)
+
+/** Alias (User Manual Name) for ERAY0_TEST1.
+* To use register names with standard convension, please use ERAY0_TEST1.
+*/
+#define ERAY_TEST1 (ERAY0_TEST1)
+
+/** \brief 14, Test Register 2 */
+#define ERAY0_TEST2 /*lint --e(923)*/ (*(volatile Ifx_ERAY_TEST2*)0xF001C014u)
+
+/** Alias (User Manual Name) for ERAY0_TEST2.
+* To use register names with standard convension, please use ERAY0_TEST2.
+*/
+#define ERAY_TEST2 (ERAY0_TEST2)
+
+/** \brief 320, Transmission Request Register 1 */
+#define ERAY0_TXRQ1 /*lint --e(923)*/ (*(volatile Ifx_ERAY_TXRQ1*)0xF001C320u)
+
+/** Alias (User Manual Name) for ERAY0_TXRQ1.
+* To use register names with standard convension, please use ERAY0_TXRQ1.
+*/
+#define ERAY_TXRQ1 (ERAY0_TXRQ1)
+
+/** \brief 324, Transmission Request Register 2 */
+#define ERAY0_TXRQ2 /*lint --e(923)*/ (*(volatile Ifx_ERAY_TXRQ2*)0xF001C324u)
+
+/** Alias (User Manual Name) for ERAY0_TXRQ2.
+* To use register names with standard convension, please use ERAY0_TXRQ2.
+*/
+#define ERAY_TXRQ2 (ERAY0_TXRQ2)
+
+/** \brief 328, Transmission Request Register 3 */
+#define ERAY0_TXRQ3 /*lint --e(923)*/ (*(volatile Ifx_ERAY_TXRQ3*)0xF001C328u)
+
+/** Alias (User Manual Name) for ERAY0_TXRQ3.
+* To use register names with standard convension, please use ERAY0_TXRQ3.
+*/
+#define ERAY_TXRQ3 (ERAY0_TXRQ3)
+
+/** \brief 32C, Transmission Request Register 4 */
+#define ERAY0_TXRQ4 /*lint --e(923)*/ (*(volatile Ifx_ERAY_TXRQ4*)0xF001C32Cu)
+
+/** Alias (User Manual Name) for ERAY0_TXRQ4.
+* To use register names with standard convension, please use ERAY0_TXRQ4.
+*/
+#define ERAY_TXRQ4 (ERAY0_TXRQ4)
+
+/** \brief 400, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S0 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C400u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S0.
+* To use register names with standard convension, please use ERAY0_WRDS_1S0.
+*/
+#define ERAY_WRDS01 (ERAY0_WRDS_1S0)
+
+/** \brief 404, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S1 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C404u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S1.
+* To use register names with standard convension, please use ERAY0_WRDS_1S1.
+*/
+#define ERAY_WRDS02 (ERAY0_WRDS_1S1)
+
+/** \brief 428, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S10 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C428u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S10.
+* To use register names with standard convension, please use ERAY0_WRDS_1S10.
+*/
+#define ERAY_WRDS11 (ERAY0_WRDS_1S10)
+
+/** \brief 42C, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S11 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C42Cu)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S11.
+* To use register names with standard convension, please use ERAY0_WRDS_1S11.
+*/
+#define ERAY_WRDS12 (ERAY0_WRDS_1S11)
+
+/** \brief 430, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S12 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C430u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S12.
+* To use register names with standard convension, please use ERAY0_WRDS_1S12.
+*/
+#define ERAY_WRDS13 (ERAY0_WRDS_1S12)
+
+/** \brief 434, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S13 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C434u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S13.
+* To use register names with standard convension, please use ERAY0_WRDS_1S13.
+*/
+#define ERAY_WRDS14 (ERAY0_WRDS_1S13)
+
+/** \brief 438, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S14 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C438u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S14.
+* To use register names with standard convension, please use ERAY0_WRDS_1S14.
+*/
+#define ERAY_WRDS15 (ERAY0_WRDS_1S14)
+
+/** \brief 43C, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S15 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C43Cu)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S15.
+* To use register names with standard convension, please use ERAY0_WRDS_1S15.
+*/
+#define ERAY_WRDS16 (ERAY0_WRDS_1S15)
+
+/** \brief 440, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S16 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C440u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S16.
+* To use register names with standard convension, please use ERAY0_WRDS_1S16.
+*/
+#define ERAY_WRDS17 (ERAY0_WRDS_1S16)
+
+/** \brief 444, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S17 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C444u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S17.
+* To use register names with standard convension, please use ERAY0_WRDS_1S17.
+*/
+#define ERAY_WRDS18 (ERAY0_WRDS_1S17)
+
+/** \brief 448, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S18 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C448u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S18.
+* To use register names with standard convension, please use ERAY0_WRDS_1S18.
+*/
+#define ERAY_WRDS19 (ERAY0_WRDS_1S18)
+
+/** \brief 44C, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S19 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C44Cu)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S19.
+* To use register names with standard convension, please use ERAY0_WRDS_1S19.
+*/
+#define ERAY_WRDS20 (ERAY0_WRDS_1S19)
+
+/** \brief 408, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S2 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C408u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S2.
+* To use register names with standard convension, please use ERAY0_WRDS_1S2.
+*/
+#define ERAY_WRDS03 (ERAY0_WRDS_1S2)
+
+/** \brief 450, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S20 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C450u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S20.
+* To use register names with standard convension, please use ERAY0_WRDS_1S20.
+*/
+#define ERAY_WRDS21 (ERAY0_WRDS_1S20)
+
+/** \brief 454, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S21 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C454u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S21.
+* To use register names with standard convension, please use ERAY0_WRDS_1S21.
+*/
+#define ERAY_WRDS22 (ERAY0_WRDS_1S21)
+
+/** \brief 458, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S22 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C458u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S22.
+* To use register names with standard convension, please use ERAY0_WRDS_1S22.
+*/
+#define ERAY_WRDS23 (ERAY0_WRDS_1S22)
+
+/** \brief 45C, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S23 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C45Cu)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S23.
+* To use register names with standard convension, please use ERAY0_WRDS_1S23.
+*/
+#define ERAY_WRDS24 (ERAY0_WRDS_1S23)
+
+/** \brief 460, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S24 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C460u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S24.
+* To use register names with standard convension, please use ERAY0_WRDS_1S24.
+*/
+#define ERAY_WRDS25 (ERAY0_WRDS_1S24)
+
+/** \brief 464, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S25 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C464u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S25.
+* To use register names with standard convension, please use ERAY0_WRDS_1S25.
+*/
+#define ERAY_WRDS26 (ERAY0_WRDS_1S25)
+
+/** \brief 468, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S26 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C468u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S26.
+* To use register names with standard convension, please use ERAY0_WRDS_1S26.
+*/
+#define ERAY_WRDS27 (ERAY0_WRDS_1S26)
+
+/** \brief 46C, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S27 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C46Cu)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S27.
+* To use register names with standard convension, please use ERAY0_WRDS_1S27.
+*/
+#define ERAY_WRDS28 (ERAY0_WRDS_1S27)
+
+/** \brief 470, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S28 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C470u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S28.
+* To use register names with standard convension, please use ERAY0_WRDS_1S28.
+*/
+#define ERAY_WRDS29 (ERAY0_WRDS_1S28)
+
+/** \brief 474, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S29 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C474u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S29.
+* To use register names with standard convension, please use ERAY0_WRDS_1S29.
+*/
+#define ERAY_WRDS30 (ERAY0_WRDS_1S29)
+
+/** \brief 40C, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S3 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C40Cu)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S3.
+* To use register names with standard convension, please use ERAY0_WRDS_1S3.
+*/
+#define ERAY_WRDS04 (ERAY0_WRDS_1S3)
+
+/** \brief 478, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S30 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C478u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S30.
+* To use register names with standard convension, please use ERAY0_WRDS_1S30.
+*/
+#define ERAY_WRDS31 (ERAY0_WRDS_1S30)
+
+/** \brief 47C, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S31 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C47Cu)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S31.
+* To use register names with standard convension, please use ERAY0_WRDS_1S31.
+*/
+#define ERAY_WRDS32 (ERAY0_WRDS_1S31)
+
+/** \brief 480, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S32 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C480u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S32.
+* To use register names with standard convension, please use ERAY0_WRDS_1S32.
+*/
+#define ERAY_WRDS33 (ERAY0_WRDS_1S32)
+
+/** \brief 484, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S33 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C484u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S33.
+* To use register names with standard convension, please use ERAY0_WRDS_1S33.
+*/
+#define ERAY_WRDS34 (ERAY0_WRDS_1S33)
+
+/** \brief 488, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S34 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C488u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S34.
+* To use register names with standard convension, please use ERAY0_WRDS_1S34.
+*/
+#define ERAY_WRDS35 (ERAY0_WRDS_1S34)
+
+/** \brief 48C, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S35 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C48Cu)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S35.
+* To use register names with standard convension, please use ERAY0_WRDS_1S35.
+*/
+#define ERAY_WRDS36 (ERAY0_WRDS_1S35)
+
+/** \brief 490, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S36 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C490u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S36.
+* To use register names with standard convension, please use ERAY0_WRDS_1S36.
+*/
+#define ERAY_WRDS37 (ERAY0_WRDS_1S36)
+
+/** \brief 494, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S37 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C494u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S37.
+* To use register names with standard convension, please use ERAY0_WRDS_1S37.
+*/
+#define ERAY_WRDS38 (ERAY0_WRDS_1S37)
+
+/** \brief 498, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S38 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C498u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S38.
+* To use register names with standard convension, please use ERAY0_WRDS_1S38.
+*/
+#define ERAY_WRDS39 (ERAY0_WRDS_1S38)
+
+/** \brief 49C, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S39 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C49Cu)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S39.
+* To use register names with standard convension, please use ERAY0_WRDS_1S39.
+*/
+#define ERAY_WRDS40 (ERAY0_WRDS_1S39)
+
+/** \brief 410, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S4 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C410u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S4.
+* To use register names with standard convension, please use ERAY0_WRDS_1S4.
+*/
+#define ERAY_WRDS05 (ERAY0_WRDS_1S4)
+
+/** \brief 4A0, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S40 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C4A0u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S40.
+* To use register names with standard convension, please use ERAY0_WRDS_1S40.
+*/
+#define ERAY_WRDS41 (ERAY0_WRDS_1S40)
+
+/** \brief 4A4, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S41 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C4A4u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S41.
+* To use register names with standard convension, please use ERAY0_WRDS_1S41.
+*/
+#define ERAY_WRDS42 (ERAY0_WRDS_1S41)
+
+/** \brief 4A8, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S42 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C4A8u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S42.
+* To use register names with standard convension, please use ERAY0_WRDS_1S42.
+*/
+#define ERAY_WRDS43 (ERAY0_WRDS_1S42)
+
+/** \brief 4AC, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S43 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C4ACu)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S43.
+* To use register names with standard convension, please use ERAY0_WRDS_1S43.
+*/
+#define ERAY_WRDS44 (ERAY0_WRDS_1S43)
+
+/** \brief 4B0, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S44 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C4B0u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S44.
+* To use register names with standard convension, please use ERAY0_WRDS_1S44.
+*/
+#define ERAY_WRDS45 (ERAY0_WRDS_1S44)
+
+/** \brief 4B4, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S45 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C4B4u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S45.
+* To use register names with standard convension, please use ERAY0_WRDS_1S45.
+*/
+#define ERAY_WRDS46 (ERAY0_WRDS_1S45)
+
+/** \brief 4B8, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S46 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C4B8u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S46.
+* To use register names with standard convension, please use ERAY0_WRDS_1S46.
+*/
+#define ERAY_WRDS47 (ERAY0_WRDS_1S46)
+
+/** \brief 4BC, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S47 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C4BCu)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S47.
+* To use register names with standard convension, please use ERAY0_WRDS_1S47.
+*/
+#define ERAY_WRDS48 (ERAY0_WRDS_1S47)
+
+/** \brief 4C0, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S48 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C4C0u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S48.
+* To use register names with standard convension, please use ERAY0_WRDS_1S48.
+*/
+#define ERAY_WRDS49 (ERAY0_WRDS_1S48)
+
+/** \brief 4C4, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S49 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C4C4u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S49.
+* To use register names with standard convension, please use ERAY0_WRDS_1S49.
+*/
+#define ERAY_WRDS50 (ERAY0_WRDS_1S49)
+
+/** \brief 414, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S5 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C414u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S5.
+* To use register names with standard convension, please use ERAY0_WRDS_1S5.
+*/
+#define ERAY_WRDS06 (ERAY0_WRDS_1S5)
+
+/** \brief 4C8, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S50 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C4C8u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S50.
+* To use register names with standard convension, please use ERAY0_WRDS_1S50.
+*/
+#define ERAY_WRDS51 (ERAY0_WRDS_1S50)
+
+/** \brief 4CC, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S51 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C4CCu)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S51.
+* To use register names with standard convension, please use ERAY0_WRDS_1S51.
+*/
+#define ERAY_WRDS52 (ERAY0_WRDS_1S51)
+
+/** \brief 4D0, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S52 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C4D0u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S52.
+* To use register names with standard convension, please use ERAY0_WRDS_1S52.
+*/
+#define ERAY_WRDS53 (ERAY0_WRDS_1S52)
+
+/** \brief 4D4, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S53 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C4D4u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S53.
+* To use register names with standard convension, please use ERAY0_WRDS_1S53.
+*/
+#define ERAY_WRDS54 (ERAY0_WRDS_1S53)
+
+/** \brief 4D8, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S54 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C4D8u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S54.
+* To use register names with standard convension, please use ERAY0_WRDS_1S54.
+*/
+#define ERAY_WRDS55 (ERAY0_WRDS_1S54)
+
+/** \brief 4DC, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S55 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C4DCu)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S55.
+* To use register names with standard convension, please use ERAY0_WRDS_1S55.
+*/
+#define ERAY_WRDS56 (ERAY0_WRDS_1S55)
+
+/** \brief 4E0, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S56 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C4E0u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S56.
+* To use register names with standard convension, please use ERAY0_WRDS_1S56.
+*/
+#define ERAY_WRDS57 (ERAY0_WRDS_1S56)
+
+/** \brief 4E4, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S57 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C4E4u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S57.
+* To use register names with standard convension, please use ERAY0_WRDS_1S57.
+*/
+#define ERAY_WRDS58 (ERAY0_WRDS_1S57)
+
+/** \brief 4E8, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S58 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C4E8u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S58.
+* To use register names with standard convension, please use ERAY0_WRDS_1S58.
+*/
+#define ERAY_WRDS59 (ERAY0_WRDS_1S58)
+
+/** \brief 4EC, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S59 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C4ECu)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S59.
+* To use register names with standard convension, please use ERAY0_WRDS_1S59.
+*/
+#define ERAY_WRDS60 (ERAY0_WRDS_1S59)
+
+/** \brief 418, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S6 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C418u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S6.
+* To use register names with standard convension, please use ERAY0_WRDS_1S6.
+*/
+#define ERAY_WRDS07 (ERAY0_WRDS_1S6)
+
+/** \brief 4F0, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S60 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C4F0u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S60.
+* To use register names with standard convension, please use ERAY0_WRDS_1S60.
+*/
+#define ERAY_WRDS61 (ERAY0_WRDS_1S60)
+
+/** \brief 4F4, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S61 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C4F4u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S61.
+* To use register names with standard convension, please use ERAY0_WRDS_1S61.
+*/
+#define ERAY_WRDS62 (ERAY0_WRDS_1S61)
+
+/** \brief 4F8, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S62 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C4F8u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S62.
+* To use register names with standard convension, please use ERAY0_WRDS_1S62.
+*/
+#define ERAY_WRDS63 (ERAY0_WRDS_1S62)
+
+/** \brief 4FC, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S63 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C4FCu)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S63.
+* To use register names with standard convension, please use ERAY0_WRDS_1S63.
+*/
+#define ERAY_WRDS64 (ERAY0_WRDS_1S63)
+
+/** \brief 41C, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S7 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C41Cu)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S7.
+* To use register names with standard convension, please use ERAY0_WRDS_1S7.
+*/
+#define ERAY_WRDS08 (ERAY0_WRDS_1S7)
+
+/** \brief 420, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S8 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C420u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S8.
+* To use register names with standard convension, please use ERAY0_WRDS_1S8.
+*/
+#define ERAY_WRDS09 (ERAY0_WRDS_1S8)
+
+/** \brief 424, Write Data Section \note Array index shifted by 1. Example:
+ * defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+#define ERAY0_WRDS_1S9 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRDS*)0xF001C424u)
+
+/** Alias (User Manual Name) for ERAY0_WRDS_1S9.
+* To use register names with standard convension, please use ERAY0_WRDS_1S9.
+*/
+#define ERAY_WRDS10 (ERAY0_WRDS_1S9)
+
+/** \brief 500, Write Header Section 1 */
+#define ERAY0_WRHS1 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRHS1*)0xF001C500u)
+
+/** Alias (User Manual Name) for ERAY0_WRHS1.
+* To use register names with standard convension, please use ERAY0_WRHS1.
+*/
+#define ERAY_WRHS1 (ERAY0_WRHS1)
+
+/** \brief 504, Write Header Section 2 */
+#define ERAY0_WRHS2 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRHS2*)0xF001C504u)
+
+/** Alias (User Manual Name) for ERAY0_WRHS2.
+* To use register names with standard convension, please use ERAY0_WRHS2.
+*/
+#define ERAY_WRHS2 (ERAY0_WRHS2)
+
+/** \brief 508, Write Header Section 3 */
+#define ERAY0_WRHS3 /*lint --e(923)*/ (*(volatile Ifx_ERAY_WRHS3*)0xF001C508u)
+
+/** Alias (User Manual Name) for ERAY0_WRHS3.
+* To use register names with standard convension, please use ERAY0_WRHS3.
+*/
+#define ERAY_WRHS3 (ERAY0_WRHS3)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXERAY_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEray_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEray_regdef.h
new file mode 100644
index 0000000..1913abb
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEray_regdef.h
@@ -0,0 +1,2761 @@
+/**
+ * \file IfxEray_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Eray Eray
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Eray_Bitfields Bitfields
+ * \ingroup IfxLld_Eray
+ *
+ * \defgroup IfxLld_Eray_union Union
+ * \ingroup IfxLld_Eray
+ *
+ * \defgroup IfxLld_Eray_struct Struct
+ * \ingroup IfxLld_Eray
+ *
+ */
+#ifndef IFXERAY_REGDEF_H
+#define IFXERAY_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Eray_Bitfields
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef struct _Ifx_ERAY_ACCEN0_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_ERAY_ACCEN0_Bits;
+
+/** \brief Access Enable Register 1 */
+typedef struct _Ifx_ERAY_ACCEN1_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_ERAY_ACCEN1_Bits;
+
+/** \brief Aggregated Channel Status */
+typedef struct _Ifx_ERAY_ACS_Bits
+{
+ unsigned int VFRA:1; /**< \brief [0:0] Valid Frame Received on Channel A (vSS!ValidFrameA) (rwh) */
+ unsigned int SEDA:1; /**< \brief [1:1] Syntax Error Detected on Channel A (vSS!SyntaxErrorA) (rwh) */
+ unsigned int CEDA:1; /**< \brief [2:2] Content Error Detected on Channel A (vSS!ContentErrorA) (rwh) */
+ unsigned int CIA:1; /**< \brief [3:3] Communication Indicator Channel A (rwh) */
+ unsigned int SBVA:1; /**< \brief [4:4] Slot Boundary Violation on Channel A (vSS!BViolationA) (rwh) */
+ unsigned int reserved_5:3; /**< \brief \internal Reserved */
+ unsigned int VFRB:1; /**< \brief [8:8] Valid Frame Received on Channel B (vSS!ValidFrameB) (rwh) */
+ unsigned int SEDB:1; /**< \brief [9:9] Syntax Error Detected on Channel B (vSS!SyntaxErrorB) (rwh) */
+ unsigned int CEDB:1; /**< \brief [10:10] Content Error Detected on Channel B (vSS!ContentErrorB) (rwh) */
+ unsigned int CIB:1; /**< \brief [11:11] Communication Indicator Channel B (rwh) */
+ unsigned int SBVB:1; /**< \brief [12:12] Slot Boundary Violation on Channel B (vSS!BViolationB) (rwh) */
+ unsigned int reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_ERAY_ACS_Bits;
+
+/** \brief Communication Controller Error Vector */
+typedef struct _Ifx_ERAY_CCEV_Bits
+{
+ unsigned int CCFC:4; /**< \brief [3:0] Clock Correction Failed Counter (vClockCorrectionFailed) (rh) */
+ unsigned int reserved_4:2; /**< \brief \internal Reserved */
+ unsigned int ERRM:2; /**< \brief [7:6] Error Mode (vPOC!ErrorMode) (rh) */
+ unsigned int PTAC:5; /**< \brief [12:8] Passive to Active Count (vAllowPassiveToActive) (rh) */
+ unsigned int reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_ERAY_CCEV_Bits;
+
+/** \brief Communication Controller Status Vector */
+typedef struct _Ifx_ERAY_CCSV_Bits
+{
+ unsigned int POCS:6; /**< \brief [5:0] Protocol Operation Control Status (rh) */
+ unsigned int FSI:1; /**< \brief [6:6] Freeze Status Indicator (vPOC!Freeze) (rh) */
+ unsigned int HRQ:1; /**< \brief [7:7] Halt Request (vPOC!CHIHaltRequest) (rh) */
+ unsigned int SLM:2; /**< \brief [9:8] Slot Mode (vPOC!SlotMode) (rh) */
+ unsigned int reserved_10:2; /**< \brief \internal Reserved */
+ unsigned int CSNI:1; /**< \brief [12:12] Coldstart Noise Indicator (vPOC!ColdstartNoise) (rh) */
+ unsigned int CSAI:1; /**< \brief [13:13] Coldstart Abort Indicator (rh) */
+ unsigned int CSI:1; /**< \brief [14:14] Cold Start Inhibit (vColdStartInhibit) (rh) */
+ unsigned int reserved_15:1; /**< \brief \internal Reserved */
+ unsigned int WSV:3; /**< \brief [18:16] Wakeup Status (vPOC!WakeupStatus) (rh) */
+ unsigned int RCA:5; /**< \brief [23:19] Remaining Coldstart Attempts (vRemainingColdstartAttempts) (rh) */
+ unsigned int PSL:6; /**< \brief [29:24] POC Status Log (rh) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_ERAY_CCSV_Bits;
+
+/** \brief Clock Control Register */
+typedef struct _Ifx_ERAY_CLC_Bits
+{
+ unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
+ unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
+ unsigned int reserved_2:1; /**< \brief \internal Reserved */
+ unsigned int EDIS:1; /**< \brief [3:3] External Sleep Mode Request Disable Bit (rw) */
+ unsigned int reserved_4:4; /**< \brief \internal Reserved */
+ unsigned int RMC:3; /**< \brief [10:8] Clock Divider in Run Mode (rw) */
+ unsigned int reserved_11:21; /**< \brief \internal Reserved */
+} Ifx_ERAY_CLC_Bits;
+
+/** \brief Core Release Register */
+typedef struct _Ifx_ERAY_CREL_Bits
+{
+ unsigned int DAY:8; /**< \brief [7:0] Design Time Stamp, Day (r) */
+ unsigned int MON:8; /**< \brief [15:8] Design Time Stamp, Month (r) */
+ unsigned int YEAR:4; /**< \brief [19:16] Design Time Stamp, Year (r) */
+ unsigned int SUBSTEP:4; /**< \brief [23:20] Sub-Step of Core Release (r) */
+ unsigned int STEP:4; /**< \brief [27:24] Step of Core Release (r) */
+ unsigned int REL:4; /**< \brief [31:28] Core Release (r) */
+} Ifx_ERAY_CREL_Bits;
+
+/** \brief Busy and Input Buffer Control Register */
+typedef struct _Ifx_ERAY_CUST1_Bits
+{
+ unsigned int INT0:1; /**< \brief [0:0] CIF Timeout Service Request Status (rwh) */
+ unsigned int OEN:1; /**< \brief [1:1] Enable auto delay scheme for Output Buffer Control Register (OBCR) (rw) */
+ unsigned int IEN:1; /**< \brief [2:2] Enable auto delay scheme for Input Buffer Control Register (IBCR) (rw) */
+ unsigned int IBFS:1; /**< \brief [3:3] Input Buffer Status Register (rh) */
+ unsigned int IBF1PAG:1; /**< \brief [4:4] Input Buffer 1 Page Select Register (rw) */
+ unsigned int reserved_5:2; /**< \brief \internal Reserved */
+ unsigned int IBF2PAG:1; /**< \brief [7:7] Input Buffer 2 Page Select Register (rw) */
+ unsigned int reserved_8:2; /**< \brief \internal Reserved */
+ unsigned int RISA:2; /**< \brief [11:10] Receive Input Select Channel A (rw) */
+ unsigned int RISB:2; /**< \brief [13:12] Receive Input Select Channel B (rw) */
+ unsigned int STPWTS:2; /**< \brief [15:14] Stop Watch Trigger Input Select (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_ERAY_CUST1_Bits;
+
+/** \brief Customer Interface Timeout Counter */
+typedef struct _Ifx_ERAY_CUST3_Bits
+{
+ unsigned int TO:32; /**< \brief [31:0] CIF Timeout Reload Value (rw) */
+} Ifx_ERAY_CUST3_Bits;
+
+/** \brief Error Service Request Enable Reset */
+typedef struct _Ifx_ERAY_EIER_Bits
+{
+ unsigned int PEMCE:1; /**< \brief [0:0] POC Error Mode Changed Service Request Enable (rwh) */
+ unsigned int CNAE:1; /**< \brief [1:1] Command Not Accepted Service Request Enable (rwh) */
+ unsigned int SFBME:1; /**< \brief [2:2] SYNC Frames Below Minimum Service Request Enable (rwh) */
+ unsigned int SFOE:1; /**< \brief [3:3] SYNC Frame Overflow Service Request Enable (rwh) */
+ unsigned int CCFE:1; /**< \brief [4:4] Clock Correction Failure Service Request Enable (rwh) */
+ unsigned int CCLE:1; /**< \brief [5:5] CHI Command Locked Service Request Enable (rwh) */
+ unsigned int EERRE:1; /**< \brief [6:6] ECC Error Service Request Enable (rwh) */
+ unsigned int RFOE:1; /**< \brief [7:7] Receive FIFO Overrun Service Request Enable (rwh) */
+ unsigned int EFAE:1; /**< \brief [8:8] Empty FIFO Access Service Request Enable (rwh) */
+ unsigned int IIBAE:1; /**< \brief [9:9] Illegal Input Buffer Access Service Request Enable (rwh) */
+ unsigned int IOBAE:1; /**< \brief [10:10] Illegal Output Buffer Access Service Request Enable (rwh) */
+ unsigned int MHFE:1; /**< \brief [11:11] Message Handler Constraints Flag Service Request Enable (rwh) */
+ unsigned int reserved_12:4; /**< \brief \internal Reserved */
+ unsigned int EDAE:1; /**< \brief [16:16] Error Detected on Channel A Service Request Enable (rwh) */
+ unsigned int LTVAE:1; /**< \brief [17:17] Latest Transmit Violation Channel A Service Request Enable (rwh) */
+ unsigned int TABAE:1; /**< \brief [18:18] Transmission Across Boundary Channel A Service Request Enable (rwh) */
+ unsigned int reserved_19:5; /**< \brief \internal Reserved */
+ unsigned int EDBE:1; /**< \brief [24:24] Error Detected on Channel B Service Request Enable (rwh) */
+ unsigned int LTVBE:1; /**< \brief [25:25] Latest Transmit Violation Channel B Service Request Enable (rwh) */
+ unsigned int TABBE:1; /**< \brief [26:26] Transmission Across Boundary Channel B Service Request Enable (rwh) */
+ unsigned int reserved_27:5; /**< \brief \internal Reserved */
+} Ifx_ERAY_EIER_Bits;
+
+/** \brief Error Service Request Enable Set */
+typedef struct _Ifx_ERAY_EIES_Bits
+{
+ unsigned int PEMCE:1; /**< \brief [0:0] POC Error Mode Changed Service Request Enable (rwh) */
+ unsigned int CNAE:1; /**< \brief [1:1] Command Not Accepted Service Request Enable (rwh) */
+ unsigned int SFBME:1; /**< \brief [2:2] SYNC Frames Below Minimum Service Request Enable (rwh) */
+ unsigned int SFOE:1; /**< \brief [3:3] SYNC Frame Overflow Service Request Enable (rwh) */
+ unsigned int CCFE:1; /**< \brief [4:4] Clock Correction Failure Service Request Enable (rwh) */
+ unsigned int CCLE:1; /**< \brief [5:5] CHI Command Locked Service Request Enable (rwh) */
+ unsigned int EERRE:1; /**< \brief [6:6] ECC Error Service Request Enable (rwh) */
+ unsigned int RFOE:1; /**< \brief [7:7] Receive FIFO Overrun Service Request Enable (rwh) */
+ unsigned int EFAE:1; /**< \brief [8:8] Empty FIFO Access Service Request Enable (rwh) */
+ unsigned int IIBAE:1; /**< \brief [9:9] Illegal Input Buffer Access Service Request Enable (rwh) */
+ unsigned int IOBAE:1; /**< \brief [10:10] Illegal Output Buffer Access Service Request Enable (rwh) */
+ unsigned int MHFE:1; /**< \brief [11:11] Message Handler Constraints Flag Service Request Enable (rwh) */
+ unsigned int reserved_12:4; /**< \brief \internal Reserved */
+ unsigned int EDAE:1; /**< \brief [16:16] Error Detected on Channel A Service Request Enable (rwh) */
+ unsigned int LTVAE:1; /**< \brief [17:17] Latest Transmit Violation Channel A Service Request Enable (rwh) */
+ unsigned int TABAE:1; /**< \brief [18:18] Transmission Across Boundary Channel A Service Request Enable (rwh) */
+ unsigned int reserved_19:5; /**< \brief \internal Reserved */
+ unsigned int EDBE:1; /**< \brief [24:24] Error Detected on Channel B Service Request Enable (rwh) */
+ unsigned int LTVBE:1; /**< \brief [25:25] Latest Transmit Violation Channel B Service Request Enable (rwh) */
+ unsigned int TABBE:1; /**< \brief [26:26] Transmission Across Boundary Channel B Service Request Enable (rwh) */
+ unsigned int reserved_27:5; /**< \brief \internal Reserved */
+} Ifx_ERAY_EIES_Bits;
+
+/** \brief Error Service Request Line Select */
+typedef struct _Ifx_ERAY_EILS_Bits
+{
+ unsigned int PEMCL:1; /**< \brief [0:0] POC Error Mode Changed Service Request Line (rw) */
+ unsigned int CNAL:1; /**< \brief [1:1] Command Not Accepted Service Request Line (rw) */
+ unsigned int SFBML:1; /**< \brief [2:2] SYNC Frames Below Minimum Service Request Line (rw) */
+ unsigned int SFOL:1; /**< \brief [3:3] SYNC Frame Overflow Service Request Line (rw) */
+ unsigned int CCFL:1; /**< \brief [4:4] Clock Correction Failure Service Request Line (rw) */
+ unsigned int CCLL:1; /**< \brief [5:5] CHI Command Locked Service Request Line (rw) */
+ unsigned int EERRL:1; /**< \brief [6:6] ECC Error Service Request Line (rw) */
+ unsigned int RFOL:1; /**< \brief [7:7] Receive FIFO Overrun Service Request Line (rw) */
+ unsigned int EFAL:1; /**< \brief [8:8] Empty FIFO Access Service Request Line (rw) */
+ unsigned int IIBAL:1; /**< \brief [9:9] Illegal Input Buffer Access Service Request Line (rw) */
+ unsigned int IOBAL:1; /**< \brief [10:10] Illegal Output Buffer Access Service Request Line (rw) */
+ unsigned int MHFL:1; /**< \brief [11:11] Message Handler Constrains Flag Service Request Line (rw) */
+ unsigned int reserved_12:4; /**< \brief \internal Reserved */
+ unsigned int EDAL:1; /**< \brief [16:16] Error Detected on Channel A Service Request Line (rw) */
+ unsigned int LTVAL:1; /**< \brief [17:17] Latest Transmit Violation Channel A Service Request Line (rw) */
+ unsigned int TABAL:1; /**< \brief [18:18] Transmission Across Boundary Channel A Service Request Line (rw) */
+ unsigned int reserved_19:5; /**< \brief \internal Reserved */
+ unsigned int EDBL:1; /**< \brief [24:24] Error Detected on Channel B Service Request Line (rw) */
+ unsigned int LTVBL:1; /**< \brief [25:25] Latest Transmit Violation Channel B Service Request Line (rw) */
+ unsigned int TABBL:1; /**< \brief [26:26] Transmission Across Boundary Channel A Service Request Line (rw) */
+ unsigned int reserved_27:5; /**< \brief \internal Reserved */
+} Ifx_ERAY_EILS_Bits;
+
+/** \brief Error Service Request Register */
+typedef struct _Ifx_ERAY_EIR_Bits
+{
+ unsigned int PEMC:1; /**< \brief [0:0] POC Error Mode Changed (rwh) */
+ unsigned int CNA:1; /**< \brief [1:1] Command Not Accepted (rwh) */
+ unsigned int SFBM:1; /**< \brief [2:2] SYNC Frames Below Minimum (rwh) */
+ unsigned int SFO:1; /**< \brief [3:3] SYNC Frame Overflow (rwh) */
+ unsigned int CCF:1; /**< \brief [4:4] Clock Correction Failure (rwh) */
+ unsigned int CCL:1; /**< \brief [5:5] CHI Command Locked (rwh) */
+ unsigned int EERR:1; /**< \brief [6:6] ECC Error (rh) */
+ unsigned int RFO:1; /**< \brief [7:7] Receive FIFO Overrun (rh) */
+ unsigned int EFA:1; /**< \brief [8:8] Empty FIFO Access (rwh) */
+ unsigned int IIBA:1; /**< \brief [9:9] Illegal Input Buffer Access (rwh) */
+ unsigned int IOBA:1; /**< \brief [10:10] Illegal Output Buffer Access (rwh) */
+ unsigned int MHF:1; /**< \brief [11:11] Message Handler Constraints Flag (rwh) */
+ unsigned int reserved_12:4; /**< \brief \internal Reserved */
+ unsigned int EDA:1; /**< \brief [16:16] Error Detected on Channel A (rwh) */
+ unsigned int LTVA:1; /**< \brief [17:17] Latest Transmit Violation Channel A (rwh) */
+ unsigned int TABA:1; /**< \brief [18:18] Transmission Across Boundary Channel A (rwh) */
+ unsigned int reserved_19:5; /**< \brief \internal Reserved */
+ unsigned int EDB:1; /**< \brief [24:24] Error Detected on Channel B (rwh) */
+ unsigned int LTVB:1; /**< \brief [25:25] Latest Transmit Violation Channel B (rwh) */
+ unsigned int TABB:1; /**< \brief [26:26] Transmission Across Boundary Channel B (rwh) */
+ unsigned int reserved_27:5; /**< \brief \internal Reserved */
+} Ifx_ERAY_EIR_Bits;
+
+/** \brief Endian Register */
+typedef struct _Ifx_ERAY_ENDN_Bits
+{
+ unsigned int ETV:32; /**< \brief [31:0] Endianness Test Value (r) */
+} Ifx_ERAY_ENDN_Bits;
+
+/** \brief Even Sync ID Symbol Window */
+typedef struct _Ifx_ERAY_ESID_Bits
+{
+ unsigned int EID:10; /**< \brief [9:0] Even Sync ID (vsSyncIDListA,B even) (rh) */
+ unsigned int reserved_10:4; /**< \brief \internal Reserved */
+ unsigned int RXEA:1; /**< \brief [14:14] Received/Configured Even Sync ID on Channel A (rh) */
+ unsigned int RXEB:1; /**< \brief [15:15] Received/Configured Even Sync ID on Channel B (rh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_ERAY_ESID_Bits;
+
+/** \brief FIFO Critical Level */
+typedef struct _Ifx_ERAY_FCL_Bits
+{
+ unsigned int CL:8; /**< \brief [7:0] Critical Level (rw) */
+ unsigned int reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_ERAY_FCL_Bits;
+
+/** \brief FIFO Rejection Filter */
+typedef struct _Ifx_ERAY_FRF_Bits
+{
+ unsigned int CH:2; /**< \brief [1:0] Channel Filter (rw) */
+ unsigned int FID:11; /**< \brief [12:2] Frame ID Filter (rw) */
+ unsigned int reserved_13:3; /**< \brief \internal Reserved */
+ unsigned int CYF:7; /**< \brief [22:16] Cycle Counter Filter (rw) */
+ unsigned int RSS:1; /**< \brief [23:23] Reject in Static Segment (rw) */
+ unsigned int RNF:1; /**< \brief [24:24] Reject NULL Frames (rw) */
+ unsigned int reserved_25:7; /**< \brief \internal Reserved */
+} Ifx_ERAY_FRF_Bits;
+
+/** \brief FIFO Rejection Filter Mask */
+typedef struct _Ifx_ERAY_FRFM_Bits
+{
+ unsigned int reserved_0:2; /**< \brief \internal Reserved */
+ unsigned int MFID:11; /**< \brief [12:2] Mask Frame ID Filter (rw) */
+ unsigned int reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_ERAY_FRFM_Bits;
+
+/** \brief FIFO Status Register */
+typedef struct _Ifx_ERAY_FSR_Bits
+{
+ unsigned int RFNE:1; /**< \brief [0:0] Receive FIFO Not Empty (rh) */
+ unsigned int RFCL:1; /**< \brief [1:1] Receive FIFO Critical Level (rh) */
+ unsigned int RFO:1; /**< \brief [2:2] Receive FIFO Overrun (rh) */
+ unsigned int reserved_3:5; /**< \brief \internal Reserved */
+ unsigned int RFFL:8; /**< \brief [15:8] Receive FIFO Fill Level (rh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_ERAY_FSR_Bits;
+
+/** \brief GTU Configuration Register 1 */
+typedef struct _Ifx_ERAY_GTUC01_Bits
+{
+ unsigned int UT:20; /**< \brief [19:0] Microtick per Cycle (pMicroPerCycle) (rw) */
+ unsigned int reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_ERAY_GTUC01_Bits;
+
+/** \brief GTU Configuration Register 2 */
+typedef struct _Ifx_ERAY_GTUC02_Bits
+{
+ unsigned int MPC:14; /**< \brief [13:0] Macrotick Per Cycle (gMacroPerCycle) (rw) */
+ unsigned int reserved_14:2; /**< \brief \internal Reserved */
+ unsigned int SNM:4; /**< \brief [19:16] Sync Node Max (gSyncNodeMax) (rw) */
+ unsigned int reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_ERAY_GTUC02_Bits;
+
+/** \brief GTU Configuration Register 3 */
+typedef struct _Ifx_ERAY_GTUC03_Bits
+{
+ unsigned int UIOA:8; /**< \brief [7:0] Microtick Initial Offset Channel A (pMicroInitialOffset[A]) (rw) */
+ unsigned int UIOB:8; /**< \brief [15:8] Microtick Initial Offset Channel B (pMicroInitialOffset[B]) (rw) */
+ unsigned int MIOA:7; /**< \brief [22:16] Macrotick Initial Offset Channel A (gMacroInitialOffset[A]) (rw) */
+ unsigned int reserved_23:1; /**< \brief \internal Reserved */
+ unsigned int MIOB:7; /**< \brief [30:24] Macrotick Initial Offset Channel B (gMacroInitialOffset[B]) (rw) */
+ unsigned int reserved_31:1; /**< \brief \internal Reserved */
+} Ifx_ERAY_GTUC03_Bits;
+
+/** \brief GTU Configuration Register 4 */
+typedef struct _Ifx_ERAY_GTUC04_Bits
+{
+ unsigned int NIT:14; /**< \brief [13:0] Network Idle Time Start (gMacroPerCycle - gdNIT - 1) (rw) */
+ unsigned int reserved_14:2; /**< \brief \internal Reserved */
+ unsigned int OCS:14; /**< \brief [29:16] Offset Correction Start (gOffsetCorrectionStart - 1) (rw) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_ERAY_GTUC04_Bits;
+
+/** \brief GTU Configuration Register 5 */
+typedef struct _Ifx_ERAY_GTUC05_Bits
+{
+ unsigned int DCA:8; /**< \brief [7:0] Delay Compensation Channel A (pDelayCompensation[A]) (rw) */
+ unsigned int DCB:8; /**< \brief [15:8] Delay Compensation Channel B (pDelayCompensation[B]) (rw) */
+ unsigned int CDD:5; /**< \brief [20:16] Cluster Drift Damping (pClusterDriftDamping) (rw) */
+ unsigned int reserved_21:3; /**< \brief \internal Reserved */
+ unsigned int DEC:8; /**< \brief [31:24] Decoding Correction (pDecodingCorrection) (rw) */
+} Ifx_ERAY_GTUC05_Bits;
+
+/** \brief GTU Configuration Register 6 */
+typedef struct _Ifx_ERAY_GTUC06_Bits
+{
+ unsigned int ASR:11; /**< \brief [10:0] Accepted Startup Range (pdAcceptedStartupRange) (rw) */
+ unsigned int reserved_11:5; /**< \brief \internal Reserved */
+ unsigned int MOD:11; /**< \brief [26:16] Maximum Oscillator Drift (pdMaxDrift) (rw) */
+ unsigned int reserved_27:5; /**< \brief \internal Reserved */
+} Ifx_ERAY_GTUC06_Bits;
+
+/** \brief GTU Configuration Register 7 */
+typedef struct _Ifx_ERAY_GTUC07_Bits
+{
+ unsigned int SSL:10; /**< \brief [9:0] Static Slot Length (gdStaticSlot) (rw) */
+ unsigned int reserved_10:6; /**< \brief \internal Reserved */
+ unsigned int NSS:10; /**< \brief [25:16] Number of Static Slots (gNumberOfStaticSlots) (rw) */
+ unsigned int reserved_26:6; /**< \brief \internal Reserved */
+} Ifx_ERAY_GTUC07_Bits;
+
+/** \brief GTU Configuration Register 8 */
+typedef struct _Ifx_ERAY_GTUC08_Bits
+{
+ unsigned int MSL:6; /**< \brief [5:0] Minislot Length (gdMinislot) (rw) */
+ unsigned int reserved_6:10; /**< \brief \internal Reserved */
+ unsigned int NMS:13; /**< \brief [28:16] Number of Minislots (gNumberOfMinislots) (rw) */
+ unsigned int reserved_29:3; /**< \brief \internal Reserved */
+} Ifx_ERAY_GTUC08_Bits;
+
+/** \brief GTU Configuration Register 9 */
+typedef struct _Ifx_ERAY_GTUC09_Bits
+{
+ unsigned int APO:6; /**< \brief [5:0] Action Point Offset (gdActionPointOffset) (rw) */
+ unsigned int reserved_6:2; /**< \brief \internal Reserved */
+ unsigned int MAPO:5; /**< \brief [12:8] Minislot Action Point Offset (gd Minislot Action Point Offset) (rw) */
+ unsigned int reserved_13:3; /**< \brief \internal Reserved */
+ unsigned int DSI:2; /**< \brief [17:16] Dynamic Slot Idle Phase (gdDynamicSlotIdlePhase) (rw) */
+ unsigned int reserved_18:14; /**< \brief \internal Reserved */
+} Ifx_ERAY_GTUC09_Bits;
+
+/** \brief GTU Configuration Register 10 */
+typedef struct _Ifx_ERAY_GTUC10_Bits
+{
+ unsigned int MOC:14; /**< \brief [13:0] Maximum Offset Correction (pOffsetCorrectionOut) (rw) */
+ unsigned int reserved_14:2; /**< \brief \internal Reserved */
+ unsigned int MRC:11; /**< \brief [26:16] Maximum Rate Correction (pRateCorrectionOut) (rw) */
+ unsigned int reserved_27:5; /**< \brief \internal Reserved */
+} Ifx_ERAY_GTUC10_Bits;
+
+/** \brief GTU Configuration Register 11 */
+typedef struct _Ifx_ERAY_GTUC11_Bits
+{
+ unsigned int EOCC:2; /**< \brief [1:0] External Offset Correction Control (pExternOffsetControl) (rw) */
+ unsigned int reserved_2:6; /**< \brief \internal Reserved */
+ unsigned int ERCC:2; /**< \brief [9:8] External Rate Correction Control (pExternRateControl) (rw) */
+ unsigned int reserved_10:6; /**< \brief \internal Reserved */
+ unsigned int EOC:3; /**< \brief [18:16] External Offset Correction (pExternOffsetCorrection) (rw) */
+ unsigned int reserved_19:5; /**< \brief \internal Reserved */
+ unsigned int ERC:3; /**< \brief [26:24] External Rate Correction (pExternRateCorrection) (rw) */
+ unsigned int reserved_27:5; /**< \brief \internal Reserved */
+} Ifx_ERAY_GTUC11_Bits;
+
+/** \brief Input Buffer Command Mask */
+typedef struct _Ifx_ERAY_IBCM_Bits
+{
+ unsigned int LHSH:1; /**< \brief [0:0] Load Header Section Host (rwh) */
+ unsigned int LDSH:1; /**< \brief [1:1] Load Data Section Host (rwh) */
+ unsigned int STXRH:1; /**< \brief [2:2] Set Transmission Request Host (rwh) */
+ unsigned int reserved_3:13; /**< \brief \internal Reserved */
+ unsigned int LHSS:1; /**< \brief [16:16] Load Header Section Shadow (rh) */
+ unsigned int LDSS:1; /**< \brief [17:17] Load Data Section Shadow (rh) */
+ unsigned int STXRS:1; /**< \brief [18:18] Transmission Request Shadow (rh) */
+ unsigned int reserved_19:13; /**< \brief \internal Reserved */
+} Ifx_ERAY_IBCM_Bits;
+
+/** \brief Input Buffer Command Request */
+typedef struct _Ifx_ERAY_IBCR_Bits
+{
+ unsigned int IBRH:7; /**< \brief [6:0] Input Buffer Request Host (rwh) */
+ unsigned int reserved_7:8; /**< \brief \internal Reserved */
+ unsigned int IBSYH:1; /**< \brief [15:15] Input Buffer Busy Host (rh) */
+ unsigned int IBRS:7; /**< \brief [22:16] Input Buffer Request Shadow (rh) */
+ unsigned int reserved_23:8; /**< \brief \internal Reserved */
+ unsigned int IBSYS:1; /**< \brief [31:31] Input Buffer Busy Shadow (rh) */
+} Ifx_ERAY_IBCR_Bits;
+
+/** \brief Module Identification Register */
+typedef struct _Ifx_ERAY_ID_Bits
+{
+ unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
+ unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_ERAY_ID_Bits;
+
+/** \brief Service Request Line Enable */
+typedef struct _Ifx_ERAY_ILE_Bits
+{
+ unsigned int EINT0:1; /**< \brief [0:0] Enable Service Request Line 0 (INT0SRC) (rw) */
+ unsigned int EINT1:1; /**< \brief [1:1] Enable Service Request Line 1 (INT1SRC) (rw) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_ERAY_ILE_Bits;
+
+/** \brief Kernel Reset Register 0 */
+typedef struct _Ifx_ERAY_KRST0_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rw) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_ERAY_KRST0_Bits;
+
+/** \brief Kernel Reset Register 1 */
+typedef struct _Ifx_ERAY_KRST1_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_ERAY_KRST1_Bits;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef struct _Ifx_ERAY_KRSTCLR_Bits
+{
+ unsigned int CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_ERAY_KRSTCLR_Bits;
+
+/** \brief Lock Register */
+typedef struct _Ifx_ERAY_LCK_Bits
+{
+ unsigned int CLK:8; /**< \brief [7:0] Configuration Lock Key (w) */
+ unsigned int TMK:8; /**< \brief [15:8] Test Mode Key (w) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_ERAY_LCK_Bits;
+
+/** \brief Last Dynamic Transmit Slot */
+typedef struct _Ifx_ERAY_LDTS_Bits
+{
+ unsigned int LDTA:11; /**< \brief [10:0] Last Dynamic Transmission Channel A (rh) */
+ unsigned int reserved_11:5; /**< \brief \internal Reserved */
+ unsigned int LDTB:11; /**< \brief [26:16] Last Dynamic Transmission Channel B (rh) */
+ unsigned int reserved_27:5; /**< \brief \internal Reserved */
+} Ifx_ERAY_LDTS_Bits;
+
+/** \brief Message Buffer Status */
+typedef struct _Ifx_ERAY_MBS_Bits
+{
+ unsigned int VFRA:1; /**< \brief [0:0] Valid Frame Received on Channel A (vSS!ValidFrameA) (rh) */
+ unsigned int VFRB:1; /**< \brief [1:1] Valid Frame Received on Channel B (vSS!ValidFrameB) (rh) */
+ unsigned int SEOA:1; /**< \brief [2:2] Syntax Error Observed on Channel A (vSS!SyntaxErrorA) (rh) */
+ unsigned int SEOB:1; /**< \brief [3:3] Syntax Error Observed on Channel B (vSS!SyntaxErrorB) (rh) */
+ unsigned int CEOA:1; /**< \brief [4:4] Content Error Observed on Channel A (vSS!ContentErrorA) (rh) */
+ unsigned int CEOB:1; /**< \brief [5:5] Content Error Observed on Channel B (vSS!ContentErrorB) (rh) */
+ unsigned int SVOA:1; /**< \brief [6:6] Slot Boundary Violation Observed on Channel A (vSS!BViolationA) (rh) */
+ unsigned int SVOB:1; /**< \brief [7:7] Slot Boundary Violation Observed on Channel B (vSS!BViolationB) (rh) */
+ unsigned int TCIA:1; /**< \brief [8:8] Transmission Conflict Indication Channel A (vSS!TxConflictA) (rh) */
+ unsigned int TCIB:1; /**< \brief [9:9] Transmission Conflict Indication Channel B (vSS!TxConflictB) (rh) */
+ unsigned int ESA:1; /**< \brief [10:10] Empty Slot Channel A (rh) */
+ unsigned int ESB:1; /**< \brief [11:11] Empty Slot Channel B (rh) */
+ unsigned int MLST:1; /**< \brief [12:12] Message Lost (rh) */
+ unsigned int reserved_13:1; /**< \brief \internal Reserved */
+ unsigned int FTA:1; /**< \brief [14:14] Frame Transmitted on Channel A (rh) */
+ unsigned int FTB:1; /**< \brief [15:15] Frame Transmitted on Channel B (rh) */
+ unsigned int CCS:6; /**< \brief [21:16] Cycle Count Status (rh) */
+ unsigned int reserved_22:2; /**< \brief \internal Reserved */
+ unsigned int RCIS:1; /**< \brief [24:24] Received on Channel Indicator Status (vSS!Channel) (rh) */
+ unsigned int SFIS:1; /**< \brief [25:25] Startup Frame Indicator Status (vRF!Header!SuFIndicator) (rh) */
+ unsigned int SYNS:1; /**< \brief [26:26] SYNC Frame Indicator Status (vRF!Header!SyFIndicator) (rh) */
+ unsigned int NFIS:1; /**< \brief [27:27] NULL Frame Indicator Status (vRF!Header!NFIndicator) (rh) */
+ unsigned int PPIS:1; /**< \brief [28:28] Payload Preamble Indictor Status (vRF!Header!PPIndicator) (rh) */
+ unsigned int RESS:1; /**< \brief [29:29] Reserved Bit Status (vRF!Header!Reserved) (rh) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_ERAY_MBS_Bits;
+
+/** \brief Message Buffer Status Changed 1 */
+typedef struct _Ifx_ERAY_MBSC1_Bits
+{
+ unsigned int MBC0:1; /**< \brief [0:0] Message Buffer Status Changed 0 (0 = 0-31) (rh) */
+ unsigned int MBC1:1; /**< \brief [1:1] Message Buffer Status Changed 1 (1 = 0-31) (rh) */
+ unsigned int MBC2:1; /**< \brief [2:2] Message Buffer Status Changed 2 (2 = 0-31) (rh) */
+ unsigned int MBC3:1; /**< \brief [3:3] Message Buffer Status Changed 3 (3 = 0-31) (rh) */
+ unsigned int MBC4:1; /**< \brief [4:4] Message Buffer Status Changed 4 (4 = 0-31) (rh) */
+ unsigned int MBC5:1; /**< \brief [5:5] Message Buffer Status Changed 5 (5 = 0-31) (rh) */
+ unsigned int MBC6:1; /**< \brief [6:6] Message Buffer Status Changed 6 (6 = 0-31) (rh) */
+ unsigned int MBC7:1; /**< \brief [7:7] Message Buffer Status Changed 7 (7 = 0-31) (rh) */
+ unsigned int MBC8:1; /**< \brief [8:8] Message Buffer Status Changed 8 (8 = 0-31) (rh) */
+ unsigned int MBC9:1; /**< \brief [9:9] Message Buffer Status Changed 9 (9 = 0-31) (rh) */
+ unsigned int MBC10:1; /**< \brief [10:10] Message Buffer Status Changed 10 (10 = 0-31) (rh) */
+ unsigned int MBC11:1; /**< \brief [11:11] Message Buffer Status Changed 11 (11 = 0-31) (rh) */
+ unsigned int MBC12:1; /**< \brief [12:12] Message Buffer Status Changed 12 (12 = 0-31) (rh) */
+ unsigned int MBC13:1; /**< \brief [13:13] Message Buffer Status Changed 13 (13 = 0-31) (rh) */
+ unsigned int MBC14:1; /**< \brief [14:14] Message Buffer Status Changed 14 (14 = 0-31) (rh) */
+ unsigned int MBC15:1; /**< \brief [15:15] Message Buffer Status Changed 15 (15 = 0-31) (rh) */
+ unsigned int MBC16:1; /**< \brief [16:16] Message Buffer Status Changed 16 (16 = 0-31) (rh) */
+ unsigned int MBC17:1; /**< \brief [17:17] Message Buffer Status Changed 17 (17 = 0-31) (rh) */
+ unsigned int MBC18:1; /**< \brief [18:18] Message Buffer Status Changed 18 (18 = 0-31) (rh) */
+ unsigned int MBC19:1; /**< \brief [19:19] Message Buffer Status Changed 19 (19 = 0-31) (rh) */
+ unsigned int MBC20:1; /**< \brief [20:20] Message Buffer Status Changed 20 (20 = 0-31) (rh) */
+ unsigned int MBC21:1; /**< \brief [21:21] Message Buffer Status Changed 21 (21 = 0-31) (rh) */
+ unsigned int MBC22:1; /**< \brief [22:22] Message Buffer Status Changed 22 (22 = 0-31) (rh) */
+ unsigned int MBC23:1; /**< \brief [23:23] Message Buffer Status Changed 23 (23 = 0-31) (rh) */
+ unsigned int MBC24:1; /**< \brief [24:24] Message Buffer Status Changed 24 (24 = 0-31) (rh) */
+ unsigned int MBC25:1; /**< \brief [25:25] Message Buffer Status Changed 25 (25 = 0-31) (rh) */
+ unsigned int MBC26:1; /**< \brief [26:26] Message Buffer Status Changed 26 (26 = 0-31) (rh) */
+ unsigned int MBC27:1; /**< \brief [27:27] Message Buffer Status Changed 27 (27 = 0-31) (rh) */
+ unsigned int MBC28:1; /**< \brief [28:28] Message Buffer Status Changed 28 (28 = 0-31) (rh) */
+ unsigned int MBC29:1; /**< \brief [29:29] Message Buffer Status Changed 29 (29 = 0-31) (rh) */
+ unsigned int MBC30:1; /**< \brief [30:30] Message Buffer Status Changed 30 (30 = 0-31) (rh) */
+ unsigned int MBC31:1; /**< \brief [31:31] Message Buffer Status Changed 31 (31 = 0-31) (rh) */
+} Ifx_ERAY_MBSC1_Bits;
+
+/** \brief Message Buffer Status Changed 2 */
+typedef struct _Ifx_ERAY_MBSC2_Bits
+{
+ unsigned int MBC32:1; /**< \brief [0:0] Message Buffer Status Changed 32 (32 = 32-63) (rh) */
+ unsigned int MBC33:1; /**< \brief [1:1] Message Buffer Status Changed 33 (33 = 32-63) (rh) */
+ unsigned int MBC34:1; /**< \brief [2:2] Message Buffer Status Changed 34 (34 = 32-63) (rh) */
+ unsigned int MBC35:1; /**< \brief [3:3] Message Buffer Status Changed 35 (35 = 32-63) (rh) */
+ unsigned int MBC36:1; /**< \brief [4:4] Message Buffer Status Changed 36 (36 = 32-63) (rh) */
+ unsigned int MBC37:1; /**< \brief [5:5] Message Buffer Status Changed 37 (37 = 32-63) (rh) */
+ unsigned int MBC38:1; /**< \brief [6:6] Message Buffer Status Changed 38 (38 = 32-63) (rh) */
+ unsigned int MBC39:1; /**< \brief [7:7] Message Buffer Status Changed 39 (39 = 32-63) (rh) */
+ unsigned int MBC40:1; /**< \brief [8:8] Message Buffer Status Changed 40 (40 = 32-63) (rh) */
+ unsigned int MBC41:1; /**< \brief [9:9] Message Buffer Status Changed 41 (41 = 32-63) (rh) */
+ unsigned int MBC42:1; /**< \brief [10:10] Message Buffer Status Changed 42 (42 = 32-63) (rh) */
+ unsigned int MBC43:1; /**< \brief [11:11] Message Buffer Status Changed 43 (43 = 32-63) (rh) */
+ unsigned int MBC44:1; /**< \brief [12:12] Message Buffer Status Changed 44 (44 = 32-63) (rh) */
+ unsigned int MBC45:1; /**< \brief [13:13] Message Buffer Status Changed 45 (45 = 32-63) (rh) */
+ unsigned int MBC46:1; /**< \brief [14:14] Message Buffer Status Changed 46 (46 = 32-63) (rh) */
+ unsigned int MBC47:1; /**< \brief [15:15] Message Buffer Status Changed 47 (47 = 32-63) (rh) */
+ unsigned int MBC48:1; /**< \brief [16:16] Message Buffer Status Changed 48 (48 = 32-63) (rh) */
+ unsigned int MBC49:1; /**< \brief [17:17] Message Buffer Status Changed 49 (49 = 32-63) (rh) */
+ unsigned int MBC50:1; /**< \brief [18:18] Message Buffer Status Changed 50 (50 = 32-63) (rh) */
+ unsigned int MBC51:1; /**< \brief [19:19] Message Buffer Status Changed 51 (51 = 32-63) (rh) */
+ unsigned int MBC52:1; /**< \brief [20:20] Message Buffer Status Changed 52 (52 = 32-63) (rh) */
+ unsigned int MBC53:1; /**< \brief [21:21] Message Buffer Status Changed 53 (53 = 32-63) (rh) */
+ unsigned int MBC54:1; /**< \brief [22:22] Message Buffer Status Changed 54 (54 = 32-63) (rh) */
+ unsigned int MBC55:1; /**< \brief [23:23] Message Buffer Status Changed 55 (55 = 32-63) (rh) */
+ unsigned int MBC56:1; /**< \brief [24:24] Message Buffer Status Changed 56 (56 = 32-63) (rh) */
+ unsigned int MBC57:1; /**< \brief [25:25] Message Buffer Status Changed 57 (57 = 32-63) (rh) */
+ unsigned int MBC58:1; /**< \brief [26:26] Message Buffer Status Changed 58 (58 = 32-63) (rh) */
+ unsigned int MBC59:1; /**< \brief [27:27] Message Buffer Status Changed 59 (59 = 32-63) (rh) */
+ unsigned int MBC60:1; /**< \brief [28:28] Message Buffer Status Changed 60 (60 = 32-63) (rh) */
+ unsigned int MBC61:1; /**< \brief [29:29] Message Buffer Status Changed 61 (61 = 32-63) (rh) */
+ unsigned int MBC62:1; /**< \brief [30:30] Message Buffer Status Changed 62 (62 = 32-63) (rh) */
+ unsigned int MBC63:1; /**< \brief [31:31] Message Buffer Status Changed 63 (63 = 32-63) (rh) */
+} Ifx_ERAY_MBSC2_Bits;
+
+/** \brief Message Buffer Status Changed 3 */
+typedef struct _Ifx_ERAY_MBSC3_Bits
+{
+ unsigned int MBC64:1; /**< \brief [0:0] Message Buffer Status Changed 64 (64 = 64-95) (rh) */
+ unsigned int MBC65:1; /**< \brief [1:1] Message Buffer Status Changed 65 (65 = 64-95) (rh) */
+ unsigned int MBC66:1; /**< \brief [2:2] Message Buffer Status Changed 66 (66 = 64-95) (rh) */
+ unsigned int MBC67:1; /**< \brief [3:3] Message Buffer Status Changed 67 (67 = 64-95) (rh) */
+ unsigned int MBC68:1; /**< \brief [4:4] Message Buffer Status Changed 68 (68 = 64-95) (rh) */
+ unsigned int MBC69:1; /**< \brief [5:5] Message Buffer Status Changed 69 (69 = 64-95) (rh) */
+ unsigned int MBC70:1; /**< \brief [6:6] Message Buffer Status Changed 70 (70 = 64-95) (rh) */
+ unsigned int MBC71:1; /**< \brief [7:7] Message Buffer Status Changed 71 (71 = 64-95) (rh) */
+ unsigned int MBC72:1; /**< \brief [8:8] Message Buffer Status Changed 72 (72 = 64-95) (rh) */
+ unsigned int MBC73:1; /**< \brief [9:9] Message Buffer Status Changed 73 (73 = 64-95) (rh) */
+ unsigned int MBC74:1; /**< \brief [10:10] Message Buffer Status Changed 74 (74 = 64-95) (rh) */
+ unsigned int MBC75:1; /**< \brief [11:11] Message Buffer Status Changed 75 (75 = 64-95) (rh) */
+ unsigned int MBC76:1; /**< \brief [12:12] Message Buffer Status Changed 76 (76 = 64-95) (rh) */
+ unsigned int MBC77:1; /**< \brief [13:13] Message Buffer Status Changed 77 (77 = 64-95) (rh) */
+ unsigned int MBC78:1; /**< \brief [14:14] Message Buffer Status Changed 78 (78 = 64-95) (rh) */
+ unsigned int MBC79:1; /**< \brief [15:15] Message Buffer Status Changed 79 (79 = 64-95) (rh) */
+ unsigned int MBC80:1; /**< \brief [16:16] Message Buffer Status Changed 80 (80 = 64-95) (rh) */
+ unsigned int MBC81:1; /**< \brief [17:17] Message Buffer Status Changed 81 (81 = 64-95) (rh) */
+ unsigned int MBC82:1; /**< \brief [18:18] Message Buffer Status Changed 82 (82 = 64-95) (rh) */
+ unsigned int MBC83:1; /**< \brief [19:19] Message Buffer Status Changed 83 (83 = 64-95) (rh) */
+ unsigned int MBC84:1; /**< \brief [20:20] Message Buffer Status Changed 84 (84 = 64-95) (rh) */
+ unsigned int MBC85:1; /**< \brief [21:21] Message Buffer Status Changed 85 (85 = 64-95) (rh) */
+ unsigned int MBC86:1; /**< \brief [22:22] Message Buffer Status Changed 86 (86 = 64-95) (rh) */
+ unsigned int MBC87:1; /**< \brief [23:23] Message Buffer Status Changed 87 (87 = 64-95) (rh) */
+ unsigned int MBC88:1; /**< \brief [24:24] Message Buffer Status Changed 88 (88 = 64-95) (rh) */
+ unsigned int MBC89:1; /**< \brief [25:25] Message Buffer Status Changed 89 (89 = 64-95) (rh) */
+ unsigned int MBC90:1; /**< \brief [26:26] Message Buffer Status Changed 90 (90 = 64-95) (rh) */
+ unsigned int MBC91:1; /**< \brief [27:27] Message Buffer Status Changed 91 (91 = 64-95) (rh) */
+ unsigned int MBC92:1; /**< \brief [28:28] Message Buffer Status Changed 92 (92 = 64-95) (rh) */
+ unsigned int MBC93:1; /**< \brief [29:29] Message Buffer Status Changed 93 (93 = 64-95) (rh) */
+ unsigned int MBC94:1; /**< \brief [30:30] Message Buffer Status Changed 94 (94 = 64-95) (rh) */
+ unsigned int MBC95:1; /**< \brief [31:31] Message Buffer Status Changed 95 (95 = 64-95) (rh) */
+} Ifx_ERAY_MBSC3_Bits;
+
+/** \brief Message Buffer Status Changed 4 */
+typedef struct _Ifx_ERAY_MBSC4_Bits
+{
+ unsigned int MBC96:1; /**< \brief [0:0] Message Buffer Status Changed 96 (96 = 96-127) (rh) */
+ unsigned int MBC97:1; /**< \brief [1:1] Message Buffer Status Changed 97 (97 = 96-127) (rh) */
+ unsigned int MBC98:1; /**< \brief [2:2] Message Buffer Status Changed 98 (98 = 96-127) (rh) */
+ unsigned int MBC99:1; /**< \brief [3:3] Message Buffer Status Changed 99 (99 = 96-127) (rh) */
+ unsigned int MBC100:1; /**< \brief [4:4] Message Buffer Status Changed 100 (100 = 96-127) (rh) */
+ unsigned int MBC101:1; /**< \brief [5:5] Message Buffer Status Changed 101 (101 = 96-127) (rh) */
+ unsigned int MBC102:1; /**< \brief [6:6] Message Buffer Status Changed 102 (102 = 96-127) (rh) */
+ unsigned int MBC103:1; /**< \brief [7:7] Message Buffer Status Changed 103 (103 = 96-127) (rh) */
+ unsigned int MBC104:1; /**< \brief [8:8] Message Buffer Status Changed 104 (104 = 96-127) (rh) */
+ unsigned int MBC105:1; /**< \brief [9:9] Message Buffer Status Changed 105 (105 = 96-127) (rh) */
+ unsigned int MBC106:1; /**< \brief [10:10] Message Buffer Status Changed 106 (106 = 96-127) (rh) */
+ unsigned int MBC107:1; /**< \brief [11:11] Message Buffer Status Changed 107 (107 = 96-127) (rh) */
+ unsigned int MBC108:1; /**< \brief [12:12] Message Buffer Status Changed 108 (108 = 96-127) (rh) */
+ unsigned int MBC109:1; /**< \brief [13:13] Message Buffer Status Changed 109 (109 = 96-127) (rh) */
+ unsigned int MBC110:1; /**< \brief [14:14] Message Buffer Status Changed 110 (110 = 96-127) (rh) */
+ unsigned int MBC111:1; /**< \brief [15:15] Message Buffer Status Changed 111 (111 = 96-127) (rh) */
+ unsigned int MBC112:1; /**< \brief [16:16] Message Buffer Status Changed 112 (112 = 96-127) (rh) */
+ unsigned int MBC113:1; /**< \brief [17:17] Message Buffer Status Changed 113 (113 = 96-127) (rh) */
+ unsigned int MBC114:1; /**< \brief [18:18] Message Buffer Status Changed 114 (114 = 96-127) (rh) */
+ unsigned int MBC115:1; /**< \brief [19:19] Message Buffer Status Changed 115 (115 = 96-127) (rh) */
+ unsigned int MBC116:1; /**< \brief [20:20] Message Buffer Status Changed 116 (116 = 96-127) (rh) */
+ unsigned int MBC117:1; /**< \brief [21:21] Message Buffer Status Changed 117 (117 = 96-127) (rh) */
+ unsigned int MBC118:1; /**< \brief [22:22] Message Buffer Status Changed 118 (118 = 96-127) (rh) */
+ unsigned int MBC119:1; /**< \brief [23:23] Message Buffer Status Changed 119 (119 = 96-127) (rh) */
+ unsigned int MBC120:1; /**< \brief [24:24] Message Buffer Status Changed 120 (120 = 96-127) (rh) */
+ unsigned int MBC121:1; /**< \brief [25:25] Message Buffer Status Changed 121 (121 = 96-127) (rh) */
+ unsigned int MBC122:1; /**< \brief [26:26] Message Buffer Status Changed 122 (122 = 96-127) (rh) */
+ unsigned int MBC123:1; /**< \brief [27:27] Message Buffer Status Changed 123 (123 = 96-127) (rh) */
+ unsigned int MBC124:1; /**< \brief [28:28] Message Buffer Status Changed 124 (124 = 96-127) (rh) */
+ unsigned int MBC125:1; /**< \brief [29:29] Message Buffer Status Changed 125 (125 = 96-127) (rh) */
+ unsigned int MBC126:1; /**< \brief [30:30] Message Buffer Status Changed 126 (126 = 96-127) (rh) */
+ unsigned int MBC127:1; /**< \brief [31:31] Message Buffer Status Changed 127 (127 = 96-127) (rh) */
+} Ifx_ERAY_MBSC4_Bits;
+
+/** \brief MHD Configuration Register */
+typedef struct _Ifx_ERAY_MHDC_Bits
+{
+ unsigned int SFDL:7; /**< \brief [6:0] Static Frame Data Length (gPayloadLengthStatic) (rw) */
+ unsigned int reserved_7:9; /**< \brief \internal Reserved */
+ unsigned int SLT:13; /**< \brief [28:16] Start of Latest Transmit (pLatestTx) (rw) */
+ unsigned int reserved_29:3; /**< \brief \internal Reserved */
+} Ifx_ERAY_MHDC_Bits;
+
+/** \brief Message Handler Constraints Flags */
+typedef struct _Ifx_ERAY_MHDF_Bits
+{
+ unsigned int SNUA:1; /**< \brief [0:0] Status Not Updated Channel A (rwh) */
+ unsigned int SNUB:1; /**< \brief [1:1] Status Not Updated Channel B (rwh) */
+ unsigned int FNFA:1; /**< \brief [2:2] Find Sequence Not Finished Channel A (rwh) */
+ unsigned int FNFB:1; /**< \brief [3:3] Find Sequence Not Finished Channel B (rwh) */
+ unsigned int TBFA:1; /**< \brief [4:4] Transient Buffer Access Failure A (rwh) */
+ unsigned int TBFB:1; /**< \brief [5:5] Transient Buffer Access Failure B (rwh) */
+ unsigned int TNSA:1; /**< \brief [6:6] Transmission Not Started Channel A (rwh) */
+ unsigned int TNSB:1; /**< \brief [7:7] Transmission Not Started Channel B (rwh) */
+ unsigned int WAHP:1; /**< \brief [8:8] Write Attempt to Header Partition (rwh) */
+ unsigned int reserved_9:23; /**< \brief \internal Reserved */
+} Ifx_ERAY_MHDF_Bits;
+
+/** \brief Message Handler Status */
+typedef struct _Ifx_ERAY_MHDS_Bits
+{
+ unsigned int EIBF:1; /**< \brief [0:0] ECC Error Input Buffer RAM 1,2 (rwh) */
+ unsigned int EOBF:1; /**< \brief [1:1] ECC Error Output Buffer RAM 1,2 (rwh) */
+ unsigned int EMR:1; /**< \brief [2:2] ECC Error Message RAM (rwh) */
+ unsigned int ETBF1:1; /**< \brief [3:3] ECC Error Transient Buffer RAM A (rwh) */
+ unsigned int ETBF2:1; /**< \brief [4:4] ECC Error Transient Buffer RAM B (rwh) */
+ unsigned int FMBD:1; /**< \brief [5:5] Faulty Message Buffer Detected (rwh) */
+ unsigned int MFMB:1; /**< \brief [6:6] Multiple Faulty Message Buffers detected (rwh) */
+ unsigned int CRAM:1; /**< \brief [7:7] Clear all internal RAM’s (rh) */
+ unsigned int FMB:7; /**< \brief [14:8] Faulty Message Buffer (rh) */
+ unsigned int reserved_15:1; /**< \brief \internal Reserved */
+ unsigned int MBT:7; /**< \brief [22:16] Message Buffer Transmitted (rh) */
+ unsigned int reserved_23:1; /**< \brief \internal Reserved */
+ unsigned int MBU:7; /**< \brief [30:24] Message Buffer Updated (rh) */
+ unsigned int reserved_31:1; /**< \brief \internal Reserved */
+} Ifx_ERAY_MHDS_Bits;
+
+/** \brief Message RAM Configuration */
+typedef struct _Ifx_ERAY_MRC_Bits
+{
+ unsigned int FDB:8; /**< \brief [7:0] First Dynamic Buffer (rw) */
+ unsigned int FFB:8; /**< \brief [15:8] First Buffer of FIFO (rw) */
+ unsigned int LCB:8; /**< \brief [23:16] Last Configured Buffer (rw) */
+ unsigned int SEC:2; /**< \brief [25:24] Secure Buffers (rw) */
+ unsigned int SPLM:1; /**< \brief [26:26] SYNC Frame Payload Multiplex (rw) */
+ unsigned int reserved_27:5; /**< \brief \internal Reserved */
+} Ifx_ERAY_MRC_Bits;
+
+/** \brief Message Buffer Status Changed Interrupt Control 1 */
+typedef struct _Ifx_ERAY_MSIC1_Bits
+{
+ unsigned int MSIP0:1; /**< \brief [0:0] Message Buffer Status Changed Interrupt Pointer 0 (0 = 0-31) (rw) */
+ unsigned int MSIP1:1; /**< \brief [1:1] Message Buffer Status Changed Interrupt Pointer 1 (1 = 0-31) (rw) */
+ unsigned int MSIP2:1; /**< \brief [2:2] Message Buffer Status Changed Interrupt Pointer 2 (2 = 0-31) (rw) */
+ unsigned int MSIP3:1; /**< \brief [3:3] Message Buffer Status Changed Interrupt Pointer 3 (3 = 0-31) (rw) */
+ unsigned int MSIP4:1; /**< \brief [4:4] Message Buffer Status Changed Interrupt Pointer 4 (4 = 0-31) (rw) */
+ unsigned int MSIP5:1; /**< \brief [5:5] Message Buffer Status Changed Interrupt Pointer 5 (5 = 0-31) (rw) */
+ unsigned int MSIP6:1; /**< \brief [6:6] Message Buffer Status Changed Interrupt Pointer 6 (6 = 0-31) (rw) */
+ unsigned int MSIP7:1; /**< \brief [7:7] Message Buffer Status Changed Interrupt Pointer 7 (7 = 0-31) (rw) */
+ unsigned int MSIP8:1; /**< \brief [8:8] Message Buffer Status Changed Interrupt Pointer 8 (8 = 0-31) (rw) */
+ unsigned int MSIP9:1; /**< \brief [9:9] Message Buffer Status Changed Interrupt Pointer 9 (9 = 0-31) (rw) */
+ unsigned int MSIP10:1; /**< \brief [10:10] Message Buffer Status Changed Interrupt Pointer 10 (10 = 0-31) (rw) */
+ unsigned int MSIP11:1; /**< \brief [11:11] Message Buffer Status Changed Interrupt Pointer 11 (11 = 0-31) (rw) */
+ unsigned int MSIP12:1; /**< \brief [12:12] Message Buffer Status Changed Interrupt Pointer 12 (12 = 0-31) (rw) */
+ unsigned int MSIP13:1; /**< \brief [13:13] Message Buffer Status Changed Interrupt Pointer 13 (13 = 0-31) (rw) */
+ unsigned int MSIP14:1; /**< \brief [14:14] Message Buffer Status Changed Interrupt Pointer 14 (14 = 0-31) (rw) */
+ unsigned int MSIP15:1; /**< \brief [15:15] Message Buffer Status Changed Interrupt Pointer 15 (15 = 0-31) (rw) */
+ unsigned int MSIP16:1; /**< \brief [16:16] Message Buffer Status Changed Interrupt Pointer 16 (16 = 0-31) (rw) */
+ unsigned int MSIP17:1; /**< \brief [17:17] Message Buffer Status Changed Interrupt Pointer 17 (17 = 0-31) (rw) */
+ unsigned int MSIP18:1; /**< \brief [18:18] Message Buffer Status Changed Interrupt Pointer 18 (18 = 0-31) (rw) */
+ unsigned int MSIP19:1; /**< \brief [19:19] Message Buffer Status Changed Interrupt Pointer 19 (19 = 0-31) (rw) */
+ unsigned int MSIP20:1; /**< \brief [20:20] Message Buffer Status Changed Interrupt Pointer 20 (20 = 0-31) (rw) */
+ unsigned int MSIP21:1; /**< \brief [21:21] Message Buffer Status Changed Interrupt Pointer 21 (21 = 0-31) (rw) */
+ unsigned int MSIP22:1; /**< \brief [22:22] Message Buffer Status Changed Interrupt Pointer 22 (22 = 0-31) (rw) */
+ unsigned int MSIP23:1; /**< \brief [23:23] Message Buffer Status Changed Interrupt Pointer 23 (23 = 0-31) (rw) */
+ unsigned int MSIP24:1; /**< \brief [24:24] Message Buffer Status Changed Interrupt Pointer 24 (24 = 0-31) (rw) */
+ unsigned int MSIP25:1; /**< \brief [25:25] Message Buffer Status Changed Interrupt Pointer 25 (25 = 0-31) (rw) */
+ unsigned int MSIP26:1; /**< \brief [26:26] Message Buffer Status Changed Interrupt Pointer 26 (26 = 0-31) (rw) */
+ unsigned int MSIP27:1; /**< \brief [27:27] Message Buffer Status Changed Interrupt Pointer 27 (27 = 0-31) (rw) */
+ unsigned int MSIP28:1; /**< \brief [28:28] Message Buffer Status Changed Interrupt Pointer 28 (28 = 0-31) (rw) */
+ unsigned int MSIP29:1; /**< \brief [29:29] Message Buffer Status Changed Interrupt Pointer 29 (29 = 0-31) (rw) */
+ unsigned int MSIP30:1; /**< \brief [30:30] Message Buffer Status Changed Interrupt Pointer 30 (30 = 0-31) (rw) */
+ unsigned int MSIP31:1; /**< \brief [31:31] Message Buffer Status Changed Interrupt Pointer 31 (31 = 0-31) (rw) */
+} Ifx_ERAY_MSIC1_Bits;
+
+/** \brief Message Buffer Status Changed Interrupt Control 2 */
+typedef struct _Ifx_ERAY_MSIC2_Bits
+{
+ unsigned int MSIP32:1; /**< \brief [0:0] Message Buffer Status Changed Interrupt Pointer 32 (32 = 32-63) (rh) */
+ unsigned int MSIP33:1; /**< \brief [1:1] Message Buffer Status Changed Interrupt Pointer 33 (33 = 32-63) (rh) */
+ unsigned int MSIP34:1; /**< \brief [2:2] Message Buffer Status Changed Interrupt Pointer 34 (34 = 32-63) (rh) */
+ unsigned int MSIP35:1; /**< \brief [3:3] Message Buffer Status Changed Interrupt Pointer 35 (35 = 32-63) (rh) */
+ unsigned int MSIP36:1; /**< \brief [4:4] Message Buffer Status Changed Interrupt Pointer 36 (36 = 32-63) (rh) */
+ unsigned int MSIP37:1; /**< \brief [5:5] Message Buffer Status Changed Interrupt Pointer 37 (37 = 32-63) (rh) */
+ unsigned int MSIP38:1; /**< \brief [6:6] Message Buffer Status Changed Interrupt Pointer 38 (38 = 32-63) (rh) */
+ unsigned int MSIP39:1; /**< \brief [7:7] Message Buffer Status Changed Interrupt Pointer 39 (39 = 32-63) (rh) */
+ unsigned int MSIP40:1; /**< \brief [8:8] Message Buffer Status Changed Interrupt Pointer 40 (40 = 32-63) (rh) */
+ unsigned int MSIP41:1; /**< \brief [9:9] Message Buffer Status Changed Interrupt Pointer 41 (41 = 32-63) (rh) */
+ unsigned int MSIP42:1; /**< \brief [10:10] Message Buffer Status Changed Interrupt Pointer 42 (42 = 32-63) (rh) */
+ unsigned int MSIP43:1; /**< \brief [11:11] Message Buffer Status Changed Interrupt Pointer 43 (43 = 32-63) (rh) */
+ unsigned int MSIP44:1; /**< \brief [12:12] Message Buffer Status Changed Interrupt Pointer 44 (44 = 32-63) (rh) */
+ unsigned int MSIP45:1; /**< \brief [13:13] Message Buffer Status Changed Interrupt Pointer 45 (45 = 32-63) (rh) */
+ unsigned int MSIP46:1; /**< \brief [14:14] Message Buffer Status Changed Interrupt Pointer 46 (46 = 32-63) (rh) */
+ unsigned int MSIP47:1; /**< \brief [15:15] Message Buffer Status Changed Interrupt Pointer 47 (47 = 32-63) (rh) */
+ unsigned int MSIP48:1; /**< \brief [16:16] Message Buffer Status Changed Interrupt Pointer 48 (48 = 32-63) (rh) */
+ unsigned int MSIP49:1; /**< \brief [17:17] Message Buffer Status Changed Interrupt Pointer 49 (49 = 32-63) (rh) */
+ unsigned int MSIP50:1; /**< \brief [18:18] Message Buffer Status Changed Interrupt Pointer 50 (50 = 32-63) (rh) */
+ unsigned int MSIP51:1; /**< \brief [19:19] Message Buffer Status Changed Interrupt Pointer 51 (51 = 32-63) (rh) */
+ unsigned int MSIP52:1; /**< \brief [20:20] Message Buffer Status Changed Interrupt Pointer 52 (52 = 32-63) (rh) */
+ unsigned int MSIP53:1; /**< \brief [21:21] Message Buffer Status Changed Interrupt Pointer 53 (53 = 32-63) (rh) */
+ unsigned int MSIP54:1; /**< \brief [22:22] Message Buffer Status Changed Interrupt Pointer 54 (54 = 32-63) (rh) */
+ unsigned int MSIP55:1; /**< \brief [23:23] Message Buffer Status Changed Interrupt Pointer 55 (55 = 32-63) (rh) */
+ unsigned int MSIP56:1; /**< \brief [24:24] Message Buffer Status Changed Interrupt Pointer 56 (56 = 32-63) (rh) */
+ unsigned int MSIP57:1; /**< \brief [25:25] Message Buffer Status Changed Interrupt Pointer 57 (57 = 32-63) (rh) */
+ unsigned int MSIP58:1; /**< \brief [26:26] Message Buffer Status Changed Interrupt Pointer 58 (58 = 32-63) (rh) */
+ unsigned int MSIP59:1; /**< \brief [27:27] Message Buffer Status Changed Interrupt Pointer 59 (59 = 32-63) (rh) */
+ unsigned int MSIP60:1; /**< \brief [28:28] Message Buffer Status Changed Interrupt Pointer 60 (60 = 32-63) (rh) */
+ unsigned int MSIP61:1; /**< \brief [29:29] Message Buffer Status Changed Interrupt Pointer 61 (61 = 32-63) (rh) */
+ unsigned int MSIP62:1; /**< \brief [30:30] Message Buffer Status Changed Interrupt Pointer 62 (62 = 32-63) (rh) */
+ unsigned int MSIP63:1; /**< \brief [31:31] Message Buffer Status Changed Interrupt Pointer 63 (63 = 32-63) (rh) */
+} Ifx_ERAY_MSIC2_Bits;
+
+/** \brief Message Buffer Status Changed Interrupt Control 3 */
+typedef struct _Ifx_ERAY_MSIC3_Bits
+{
+ unsigned int MSIP64:1; /**< \brief [0:0] Message Buffer Status Changed Interrupt Pointer 64 (64 = 64-95) (rw) */
+ unsigned int MSIP65:1; /**< \brief [1:1] Message Buffer Status Changed Interrupt Pointer 65 (65 = 64-95) (rw) */
+ unsigned int MSIP66:1; /**< \brief [2:2] Message Buffer Status Changed Interrupt Pointer 66 (66 = 64-95) (rw) */
+ unsigned int MSIP67:1; /**< \brief [3:3] Message Buffer Status Changed Interrupt Pointer 67 (67 = 64-95) (rw) */
+ unsigned int MSIP68:1; /**< \brief [4:4] Message Buffer Status Changed Interrupt Pointer 68 (68 = 64-95) (rw) */
+ unsigned int MSIP69:1; /**< \brief [5:5] Message Buffer Status Changed Interrupt Pointer 69 (69 = 64-95) (rw) */
+ unsigned int MSIP70:1; /**< \brief [6:6] Message Buffer Status Changed Interrupt Pointer 70 (70 = 64-95) (rw) */
+ unsigned int MSIP71:1; /**< \brief [7:7] Message Buffer Status Changed Interrupt Pointer 71 (71 = 64-95) (rw) */
+ unsigned int MSIP72:1; /**< \brief [8:8] Message Buffer Status Changed Interrupt Pointer 72 (72 = 64-95) (rw) */
+ unsigned int MSIP73:1; /**< \brief [9:9] Message Buffer Status Changed Interrupt Pointer 73 (73 = 64-95) (rw) */
+ unsigned int MSIP74:1; /**< \brief [10:10] Message Buffer Status Changed Interrupt Pointer 74 (74 = 64-95) (rw) */
+ unsigned int MSIP75:1; /**< \brief [11:11] Message Buffer Status Changed Interrupt Pointer 75 (75 = 64-95) (rw) */
+ unsigned int MSIP76:1; /**< \brief [12:12] Message Buffer Status Changed Interrupt Pointer 76 (76 = 64-95) (rw) */
+ unsigned int MSIP77:1; /**< \brief [13:13] Message Buffer Status Changed Interrupt Pointer 77 (77 = 64-95) (rw) */
+ unsigned int MSIP78:1; /**< \brief [14:14] Message Buffer Status Changed Interrupt Pointer 78 (78 = 64-95) (rw) */
+ unsigned int MSIP79:1; /**< \brief [15:15] Message Buffer Status Changed Interrupt Pointer 79 (79 = 64-95) (rw) */
+ unsigned int MSIP80:1; /**< \brief [16:16] Message Buffer Status Changed Interrupt Pointer 80 (80 = 64-95) (rw) */
+ unsigned int MSIP81:1; /**< \brief [17:17] Message Buffer Status Changed Interrupt Pointer 81 (81 = 64-95) (rw) */
+ unsigned int MSIP82:1; /**< \brief [18:18] Message Buffer Status Changed Interrupt Pointer 82 (82 = 64-95) (rw) */
+ unsigned int MSIP83:1; /**< \brief [19:19] Message Buffer Status Changed Interrupt Pointer 83 (83 = 64-95) (rw) */
+ unsigned int MSIP84:1; /**< \brief [20:20] Message Buffer Status Changed Interrupt Pointer 84 (84 = 64-95) (rw) */
+ unsigned int MSIP85:1; /**< \brief [21:21] Message Buffer Status Changed Interrupt Pointer 85 (85 = 64-95) (rw) */
+ unsigned int MSIP86:1; /**< \brief [22:22] Message Buffer Status Changed Interrupt Pointer 86 (86 = 64-95) (rw) */
+ unsigned int MSIP87:1; /**< \brief [23:23] Message Buffer Status Changed Interrupt Pointer 87 (87 = 64-95) (rw) */
+ unsigned int MSIP88:1; /**< \brief [24:24] Message Buffer Status Changed Interrupt Pointer 88 (88 = 64-95) (rw) */
+ unsigned int MSIP89:1; /**< \brief [25:25] Message Buffer Status Changed Interrupt Pointer 89 (89 = 64-95) (rw) */
+ unsigned int MSIP90:1; /**< \brief [26:26] Message Buffer Status Changed Interrupt Pointer 90 (90 = 64-95) (rw) */
+ unsigned int MSIP91:1; /**< \brief [27:27] Message Buffer Status Changed Interrupt Pointer 91 (91 = 64-95) (rw) */
+ unsigned int MSIP92:1; /**< \brief [28:28] Message Buffer Status Changed Interrupt Pointer 92 (92 = 64-95) (rw) */
+ unsigned int MSIP93:1; /**< \brief [29:29] Message Buffer Status Changed Interrupt Pointer 93 (93 = 64-95) (rw) */
+ unsigned int MSIP94:1; /**< \brief [30:30] Message Buffer Status Changed Interrupt Pointer 94 (94 = 64-95) (rw) */
+ unsigned int MSIP95:1; /**< \brief [31:31] Message Buffer Status Changed Interrupt Pointer 95 (95 = 64-95) (rw) */
+} Ifx_ERAY_MSIC3_Bits;
+
+/** \brief Message Buffer Status Changed Interrupt Control 4 */
+typedef struct _Ifx_ERAY_MSIC4_Bits
+{
+ unsigned int MSIP96:1; /**< \brief [0:0] Message Buffer Status Changed Interrupt Pointer 96 (96 = 96-127) (rw) */
+ unsigned int MSIP97:1; /**< \brief [1:1] Message Buffer Status Changed Interrupt Pointer 97 (97 = 96-127) (rw) */
+ unsigned int MSIP98:1; /**< \brief [2:2] Message Buffer Status Changed Interrupt Pointer 98 (98 = 96-127) (rw) */
+ unsigned int MSIP99:1; /**< \brief [3:3] Message Buffer Status Changed Interrupt Pointer 99 (99 = 96-127) (rw) */
+ unsigned int MSIP100:1; /**< \brief [4:4] Message Buffer Status Changed Interrupt Pointer 100 (100 = 96-127) (rw) */
+ unsigned int MSIP101:1; /**< \brief [5:5] Message Buffer Status Changed Interrupt Pointer 101 (101 = 96-127) (rw) */
+ unsigned int MSIP102:1; /**< \brief [6:6] Message Buffer Status Changed Interrupt Pointer 102 (102 = 96-127) (rw) */
+ unsigned int MSIP103:1; /**< \brief [7:7] Message Buffer Status Changed Interrupt Pointer 103 (103 = 96-127) (rw) */
+ unsigned int MSIP104:1; /**< \brief [8:8] Message Buffer Status Changed Interrupt Pointer 104 (104 = 96-127) (rw) */
+ unsigned int MSIP105:1; /**< \brief [9:9] Message Buffer Status Changed Interrupt Pointer 105 (105 = 96-127) (rw) */
+ unsigned int MSIP106:1; /**< \brief [10:10] Message Buffer Status Changed Interrupt Pointer 106 (106 = 96-127) (rw) */
+ unsigned int MSIP107:1; /**< \brief [11:11] Message Buffer Status Changed Interrupt Pointer 107 (107 = 96-127) (rw) */
+ unsigned int MSIP108:1; /**< \brief [12:12] Message Buffer Status Changed Interrupt Pointer 108 (108 = 96-127) (rw) */
+ unsigned int MSIP109:1; /**< \brief [13:13] Message Buffer Status Changed Interrupt Pointer 109 (109 = 96-127) (rw) */
+ unsigned int MSIP110:1; /**< \brief [14:14] Message Buffer Status Changed Interrupt Pointer 110 (110 = 96-127) (rw) */
+ unsigned int MSIP111:1; /**< \brief [15:15] Message Buffer Status Changed Interrupt Pointer 111 (111 = 96-127) (rw) */
+ unsigned int MSIP112:1; /**< \brief [16:16] Message Buffer Status Changed Interrupt Pointer 112 (112 = 96-127) (rw) */
+ unsigned int MSIP113:1; /**< \brief [17:17] Message Buffer Status Changed Interrupt Pointer 113 (113 = 96-127) (rw) */
+ unsigned int MSIP114:1; /**< \brief [18:18] Message Buffer Status Changed Interrupt Pointer 114 (114 = 96-127) (rw) */
+ unsigned int MSIP115:1; /**< \brief [19:19] Message Buffer Status Changed Interrupt Pointer 115 (115 = 96-127) (rw) */
+ unsigned int MSIP116:1; /**< \brief [20:20] Message Buffer Status Changed Interrupt Pointer 116 (116 = 96-127) (rw) */
+ unsigned int MSIP117:1; /**< \brief [21:21] Message Buffer Status Changed Interrupt Pointer 117 (117 = 96-127) (rw) */
+ unsigned int MSIP118:1; /**< \brief [22:22] Message Buffer Status Changed Interrupt Pointer 118 (118 = 96-127) (rw) */
+ unsigned int MSIP119:1; /**< \brief [23:23] Message Buffer Status Changed Interrupt Pointer 119 (119 = 96-127) (rw) */
+ unsigned int MSIP120:1; /**< \brief [24:24] Message Buffer Status Changed Interrupt Pointer 120 (120 = 96-127) (rw) */
+ unsigned int MSIP121:1; /**< \brief [25:25] Message Buffer Status Changed Interrupt Pointer 121 (121 = 96-127) (rw) */
+ unsigned int MSIP122:1; /**< \brief [26:26] Message Buffer Status Changed Interrupt Pointer 122 (122 = 96-127) (rw) */
+ unsigned int MSIP123:1; /**< \brief [27:27] Message Buffer Status Changed Interrupt Pointer 123 (123 = 96-127) (rw) */
+ unsigned int MSIP124:1; /**< \brief [28:28] Message Buffer Status Changed Interrupt Pointer 124 (124 = 96-127) (rw) */
+ unsigned int MSIP125:1; /**< \brief [29:29] Message Buffer Status Changed Interrupt Pointer 125 (125 = 96-127) (rw) */
+ unsigned int MSIP126:1; /**< \brief [30:30] Message Buffer Status Changed Interrupt Pointer 126 (126 = 96-127) (rw) */
+ unsigned int MSIP127:1; /**< \brief [31:31] Message Buffer Status Changed Interrupt Pointer 127 (127 = 96-127) (rw) */
+} Ifx_ERAY_MSIC4_Bits;
+
+/** \brief Macrotick and Cycle Counter Value */
+typedef struct _Ifx_ERAY_MTCCV_Bits
+{
+ unsigned int MTV:14; /**< \brief [13:0] Macrotick Value (vMacrotick) (rh) */
+ unsigned int reserved_14:2; /**< \brief \internal Reserved */
+ unsigned int CCV:6; /**< \brief [21:16] Cycle Counter Value (vCycleCounter) (rh) */
+ unsigned int reserved_22:10; /**< \brief \internal Reserved */
+} Ifx_ERAY_MTCCV_Bits;
+
+/** \brief New Data Register 1 */
+typedef struct _Ifx_ERAY_NDAT1_Bits
+{
+ unsigned int ND0:1; /**< \brief [0:0] New Data 0 (0 = 0-31) (rh) */
+ unsigned int ND1:1; /**< \brief [1:1] New Data 1 (1 = 0-31) (rh) */
+ unsigned int ND2:1; /**< \brief [2:2] New Data 2 (2 = 0-31) (rh) */
+ unsigned int ND3:1; /**< \brief [3:3] New Data 3 (3 = 0-31) (rh) */
+ unsigned int ND4:1; /**< \brief [4:4] New Data 4 (4 = 0-31) (rh) */
+ unsigned int ND5:1; /**< \brief [5:5] New Data 5 (5 = 0-31) (rh) */
+ unsigned int ND6:1; /**< \brief [6:6] New Data 6 (6 = 0-31) (rh) */
+ unsigned int ND7:1; /**< \brief [7:7] New Data 7 (7 = 0-31) (rh) */
+ unsigned int ND8:1; /**< \brief [8:8] New Data 8 (8 = 0-31) (rh) */
+ unsigned int ND9:1; /**< \brief [9:9] New Data 9 (9 = 0-31) (rh) */
+ unsigned int ND10:1; /**< \brief [10:10] New Data 10 (10 = 0-31) (rh) */
+ unsigned int ND11:1; /**< \brief [11:11] New Data 11 (11 = 0-31) (rh) */
+ unsigned int ND12:1; /**< \brief [12:12] New Data 12 (12 = 0-31) (rh) */
+ unsigned int ND13:1; /**< \brief [13:13] New Data 13 (13 = 0-31) (rh) */
+ unsigned int ND14:1; /**< \brief [14:14] New Data 14 (14 = 0-31) (rh) */
+ unsigned int ND15:1; /**< \brief [15:15] New Data 15 (15 = 0-31) (rh) */
+ unsigned int ND16:1; /**< \brief [16:16] New Data 16 (16 = 0-31) (rh) */
+ unsigned int ND17:1; /**< \brief [17:17] New Data 17 (17 = 0-31) (rh) */
+ unsigned int ND18:1; /**< \brief [18:18] New Data 18 (18 = 0-31) (rh) */
+ unsigned int ND19:1; /**< \brief [19:19] New Data 19 (19 = 0-31) (rh) */
+ unsigned int ND20:1; /**< \brief [20:20] New Data 20 (20 = 0-31) (rh) */
+ unsigned int ND21:1; /**< \brief [21:21] New Data 21 (21 = 0-31) (rh) */
+ unsigned int ND22:1; /**< \brief [22:22] New Data 22 (22 = 0-31) (rh) */
+ unsigned int ND23:1; /**< \brief [23:23] New Data 23 (23 = 0-31) (rh) */
+ unsigned int ND24:1; /**< \brief [24:24] New Data 24 (24 = 0-31) (rh) */
+ unsigned int ND25:1; /**< \brief [25:25] New Data 25 (25 = 0-31) (rh) */
+ unsigned int ND26:1; /**< \brief [26:26] New Data 26 (26 = 0-31) (rh) */
+ unsigned int ND27:1; /**< \brief [27:27] New Data 27 (27 = 0-31) (rh) */
+ unsigned int ND28:1; /**< \brief [28:28] New Data 28 (28 = 0-31) (rh) */
+ unsigned int ND29:1; /**< \brief [29:29] New Data 29 (29 = 0-31) (rh) */
+ unsigned int ND30:1; /**< \brief [30:30] New Data 30 (30 = 0-31) (rh) */
+ unsigned int ND31:1; /**< \brief [31:31] New Data 31 (31 = 0-31) (rh) */
+} Ifx_ERAY_NDAT1_Bits;
+
+/** \brief New Data Register 2 */
+typedef struct _Ifx_ERAY_NDAT2_Bits
+{
+ unsigned int ND32:1; /**< \brief [0:0] New Data 32 (32 = 32-63) (rh) */
+ unsigned int ND33:1; /**< \brief [1:1] New Data 33 (33 = 32-63) (rh) */
+ unsigned int ND34:1; /**< \brief [2:2] New Data 34 (34 = 32-63) (rh) */
+ unsigned int ND35:1; /**< \brief [3:3] New Data 35 (35 = 32-63) (rh) */
+ unsigned int ND36:1; /**< \brief [4:4] New Data 36 (36 = 32-63) (rh) */
+ unsigned int ND37:1; /**< \brief [5:5] New Data 37 (37 = 32-63) (rh) */
+ unsigned int ND38:1; /**< \brief [6:6] New Data 38 (38 = 32-63) (rh) */
+ unsigned int ND39:1; /**< \brief [7:7] New Data 39 (39 = 32-63) (rh) */
+ unsigned int ND40:1; /**< \brief [8:8] New Data 40 (40 = 32-63) (rh) */
+ unsigned int ND41:1; /**< \brief [9:9] New Data 41 (41 = 32-63) (rh) */
+ unsigned int ND42:1; /**< \brief [10:10] New Data 42 (42 = 32-63) (rh) */
+ unsigned int ND43:1; /**< \brief [11:11] New Data 43 (43 = 32-63) (rh) */
+ unsigned int ND44:1; /**< \brief [12:12] New Data 44 (44 = 32-63) (rh) */
+ unsigned int ND45:1; /**< \brief [13:13] New Data 45 (45 = 32-63) (rh) */
+ unsigned int ND46:1; /**< \brief [14:14] New Data 46 (46 = 32-63) (rh) */
+ unsigned int ND47:1; /**< \brief [15:15] New Data 47 (47 = 32-63) (rh) */
+ unsigned int ND48:1; /**< \brief [16:16] New Data 48 (48 = 32-63) (rh) */
+ unsigned int ND49:1; /**< \brief [17:17] New Data 49 (49 = 32-63) (rh) */
+ unsigned int ND50:1; /**< \brief [18:18] New Data 50 (50 = 32-63) (rh) */
+ unsigned int ND51:1; /**< \brief [19:19] New Data 51 (51 = 32-63) (rh) */
+ unsigned int ND52:1; /**< \brief [20:20] New Data 52 (52 = 32-63) (rh) */
+ unsigned int ND53:1; /**< \brief [21:21] New Data 53 (53 = 32-63) (rh) */
+ unsigned int ND54:1; /**< \brief [22:22] New Data 54 (54 = 32-63) (rh) */
+ unsigned int ND55:1; /**< \brief [23:23] New Data 55 (55 = 32-63) (rh) */
+ unsigned int ND56:1; /**< \brief [24:24] New Data 56 (56 = 32-63) (rh) */
+ unsigned int ND57:1; /**< \brief [25:25] New Data 57 (57 = 32-63) (rh) */
+ unsigned int ND58:1; /**< \brief [26:26] New Data 58 (58 = 32-63) (rh) */
+ unsigned int ND59:1; /**< \brief [27:27] New Data 59 (59 = 32-63) (rh) */
+ unsigned int ND60:1; /**< \brief [28:28] New Data 60 (60 = 32-63) (rh) */
+ unsigned int ND61:1; /**< \brief [29:29] New Data 61 (61 = 32-63) (rh) */
+ unsigned int ND62:1; /**< \brief [30:30] New Data 62 (62 = 32-63) (rh) */
+ unsigned int ND63:1; /**< \brief [31:31] New Data 63 (63 = 32-63) (rh) */
+} Ifx_ERAY_NDAT2_Bits;
+
+/** \brief New Data Register 3 */
+typedef struct _Ifx_ERAY_NDAT3_Bits
+{
+ unsigned int ND64:1; /**< \brief [0:0] New Data 64 (64 = 64-95) (rh) */
+ unsigned int ND65:1; /**< \brief [1:1] New Data 65 (65 = 64-95) (rh) */
+ unsigned int ND66:1; /**< \brief [2:2] New Data 66 (66 = 64-95) (rh) */
+ unsigned int ND67:1; /**< \brief [3:3] New Data 67 (67 = 64-95) (rh) */
+ unsigned int ND68:1; /**< \brief [4:4] New Data 68 (68 = 64-95) (rh) */
+ unsigned int ND69:1; /**< \brief [5:5] New Data 69 (69 = 64-95) (rh) */
+ unsigned int ND70:1; /**< \brief [6:6] New Data 70 (70 = 64-95) (rh) */
+ unsigned int ND71:1; /**< \brief [7:7] New Data 71 (71 = 64-95) (rh) */
+ unsigned int ND72:1; /**< \brief [8:8] New Data 72 (72 = 64-95) (rh) */
+ unsigned int ND73:1; /**< \brief [9:9] New Data 73 (73 = 64-95) (rh) */
+ unsigned int ND74:1; /**< \brief [10:10] New Data 74 (74 = 64-95) (rh) */
+ unsigned int ND75:1; /**< \brief [11:11] New Data 75 (75 = 64-95) (rh) */
+ unsigned int ND76:1; /**< \brief [12:12] New Data 76 (76 = 64-95) (rh) */
+ unsigned int ND77:1; /**< \brief [13:13] New Data 77 (77 = 64-95) (rh) */
+ unsigned int ND78:1; /**< \brief [14:14] New Data 78 (78 = 64-95) (rh) */
+ unsigned int ND79:1; /**< \brief [15:15] New Data 79 (79 = 64-95) (rh) */
+ unsigned int ND80:1; /**< \brief [16:16] New Data 80 (80 = 64-95) (rh) */
+ unsigned int ND81:1; /**< \brief [17:17] New Data 81 (81 = 64-95) (rh) */
+ unsigned int ND82:1; /**< \brief [18:18] New Data 82 (82 = 64-95) (rh) */
+ unsigned int ND83:1; /**< \brief [19:19] New Data 83 (83 = 64-95) (rh) */
+ unsigned int ND84:1; /**< \brief [20:20] New Data 84 (84 = 64-95) (rh) */
+ unsigned int ND85:1; /**< \brief [21:21] New Data 85 (85 = 64-95) (rh) */
+ unsigned int ND86:1; /**< \brief [22:22] New Data 86 (86 = 64-95) (rh) */
+ unsigned int ND87:1; /**< \brief [23:23] New Data 87 (87 = 64-95) (rh) */
+ unsigned int ND88:1; /**< \brief [24:24] New Data 88 (88 = 64-95) (rh) */
+ unsigned int ND89:1; /**< \brief [25:25] New Data 89 (89 = 64-95) (rh) */
+ unsigned int ND90:1; /**< \brief [26:26] New Data 90 (90 = 64-95) (rh) */
+ unsigned int ND91:1; /**< \brief [27:27] New Data 91 (91 = 64-95) (rh) */
+ unsigned int ND92:1; /**< \brief [28:28] New Data 92 (92 = 64-95) (rh) */
+ unsigned int ND93:1; /**< \brief [29:29] New Data 93 (93 = 64-95) (rh) */
+ unsigned int ND94:1; /**< \brief [30:30] New Data 94 (94 = 64-95) (rh) */
+ unsigned int ND95:1; /**< \brief [31:31] New Data 95 (95 = 64-95) (rh) */
+} Ifx_ERAY_NDAT3_Bits;
+
+/** \brief New Data Register 4 */
+typedef struct _Ifx_ERAY_NDAT4_Bits
+{
+ unsigned int ND96:1; /**< \brief [0:0] New Data 96 (96 = 96-127) (rh) */
+ unsigned int ND97:1; /**< \brief [1:1] New Data 97 (97 = 96-127) (rh) */
+ unsigned int ND98:1; /**< \brief [2:2] New Data 98 (98 = 96-127) (rh) */
+ unsigned int ND99:1; /**< \brief [3:3] New Data 99 (99 = 96-127) (rh) */
+ unsigned int ND100:1; /**< \brief [4:4] New Data 100 (100 = 96-127) (rh) */
+ unsigned int ND101:1; /**< \brief [5:5] New Data 101 (101 = 96-127) (rh) */
+ unsigned int ND102:1; /**< \brief [6:6] New Data 102 (102 = 96-127) (rh) */
+ unsigned int ND103:1; /**< \brief [7:7] New Data 103 (103 = 96-127) (rh) */
+ unsigned int ND104:1; /**< \brief [8:8] New Data 104 (104 = 96-127) (rh) */
+ unsigned int ND105:1; /**< \brief [9:9] New Data 105 (105 = 96-127) (rh) */
+ unsigned int ND106:1; /**< \brief [10:10] New Data 106 (106 = 96-127) (rh) */
+ unsigned int ND107:1; /**< \brief [11:11] New Data 107 (107 = 96-127) (rh) */
+ unsigned int ND108:1; /**< \brief [12:12] New Data 108 (108 = 96-127) (rh) */
+ unsigned int ND109:1; /**< \brief [13:13] New Data 109 (109 = 96-127) (rh) */
+ unsigned int ND110:1; /**< \brief [14:14] New Data 110 (110 = 96-127) (rh) */
+ unsigned int ND111:1; /**< \brief [15:15] New Data 111 (111 = 96-127) (rh) */
+ unsigned int ND112:1; /**< \brief [16:16] New Data 112 (112 = 96-127) (rh) */
+ unsigned int ND113:1; /**< \brief [17:17] New Data 113 (113 = 96-127) (rh) */
+ unsigned int ND114:1; /**< \brief [18:18] New Data 114 (114 = 96-127) (rh) */
+ unsigned int ND115:1; /**< \brief [19:19] New Data 115 (115 = 96-127) (rh) */
+ unsigned int ND116:1; /**< \brief [20:20] New Data 116 (116 = 96-127) (rh) */
+ unsigned int ND117:1; /**< \brief [21:21] New Data 117 (117 = 96-127) (rh) */
+ unsigned int ND118:1; /**< \brief [22:22] New Data 118 (118 = 96-127) (rh) */
+ unsigned int ND119:1; /**< \brief [23:23] New Data 119 (119 = 96-127) (rh) */
+ unsigned int ND120:1; /**< \brief [24:24] New Data 120 (120 = 96-127) (rh) */
+ unsigned int ND121:1; /**< \brief [25:25] New Data 121 (121 = 96-127) (rh) */
+ unsigned int ND122:1; /**< \brief [26:26] New Data 122 (122 = 96-127) (rh) */
+ unsigned int ND123:1; /**< \brief [27:27] New Data 123 (123 = 96-127) (rh) */
+ unsigned int ND124:1; /**< \brief [28:28] New Data 124 (124 = 96-127) (rh) */
+ unsigned int ND125:1; /**< \brief [29:29] New Data 125 (125 = 96-127) (rh) */
+ unsigned int ND126:1; /**< \brief [30:30] New Data 126 (126 = 96-127) (rh) */
+ unsigned int ND127:1; /**< \brief [31:31] New Data 127 (127 = 96-127) (rh) */
+} Ifx_ERAY_NDAT4_Bits;
+
+/** \brief New Data Interrupt Control 1 */
+typedef struct _Ifx_ERAY_NDIC1_Bits
+{
+ unsigned int NDIP0:1; /**< \brief [0:0] New Data Interrupt Pointer 0 (0 = 0-31) (rw) */
+ unsigned int NDIP1:1; /**< \brief [1:1] New Data Interrupt Pointer 1 (1 = 0-31) (rw) */
+ unsigned int NDIP2:1; /**< \brief [2:2] New Data Interrupt Pointer 2 (2 = 0-31) (rw) */
+ unsigned int NDIP3:1; /**< \brief [3:3] New Data Interrupt Pointer 3 (3 = 0-31) (rw) */
+ unsigned int NDIP4:1; /**< \brief [4:4] New Data Interrupt Pointer 4 (4 = 0-31) (rw) */
+ unsigned int NDIP5:1; /**< \brief [5:5] New Data Interrupt Pointer 5 (5 = 0-31) (rw) */
+ unsigned int NDIP6:1; /**< \brief [6:6] New Data Interrupt Pointer 6 (6 = 0-31) (rw) */
+ unsigned int NDIP7:1; /**< \brief [7:7] New Data Interrupt Pointer 7 (7 = 0-31) (rw) */
+ unsigned int NDIP8:1; /**< \brief [8:8] New Data Interrupt Pointer 8 (8 = 0-31) (rw) */
+ unsigned int NDIP9:1; /**< \brief [9:9] New Data Interrupt Pointer 9 (9 = 0-31) (rw) */
+ unsigned int NDIP10:1; /**< \brief [10:10] New Data Interrupt Pointer 10 (10 = 0-31) (rw) */
+ unsigned int NDIP11:1; /**< \brief [11:11] New Data Interrupt Pointer 11 (11 = 0-31) (rw) */
+ unsigned int NDIP12:1; /**< \brief [12:12] New Data Interrupt Pointer 12 (12 = 0-31) (rw) */
+ unsigned int NDIP13:1; /**< \brief [13:13] New Data Interrupt Pointer 13 (13 = 0-31) (rw) */
+ unsigned int NDIP14:1; /**< \brief [14:14] New Data Interrupt Pointer 14 (14 = 0-31) (rw) */
+ unsigned int NDIP15:1; /**< \brief [15:15] New Data Interrupt Pointer 15 (15 = 0-31) (rw) */
+ unsigned int NDIP16:1; /**< \brief [16:16] New Data Interrupt Pointer 16 (16 = 0-31) (rw) */
+ unsigned int NDIP17:1; /**< \brief [17:17] New Data Interrupt Pointer 17 (17 = 0-31) (rw) */
+ unsigned int NDIP18:1; /**< \brief [18:18] New Data Interrupt Pointer 18 (18 = 0-31) (rw) */
+ unsigned int NDIP19:1; /**< \brief [19:19] New Data Interrupt Pointer 19 (19 = 0-31) (rw) */
+ unsigned int NDIP20:1; /**< \brief [20:20] New Data Interrupt Pointer 20 (20 = 0-31) (rw) */
+ unsigned int NDIP21:1; /**< \brief [21:21] New Data Interrupt Pointer 21 (21 = 0-31) (rw) */
+ unsigned int NDIP22:1; /**< \brief [22:22] New Data Interrupt Pointer 22 (22 = 0-31) (rw) */
+ unsigned int NDIP23:1; /**< \brief [23:23] New Data Interrupt Pointer 23 (23 = 0-31) (rw) */
+ unsigned int NDIP24:1; /**< \brief [24:24] New Data Interrupt Pointer 24 (24 = 0-31) (rw) */
+ unsigned int NDIP25:1; /**< \brief [25:25] New Data Interrupt Pointer 25 (25 = 0-31) (rw) */
+ unsigned int NDIP26:1; /**< \brief [26:26] New Data Interrupt Pointer 26 (26 = 0-31) (rw) */
+ unsigned int NDIP27:1; /**< \brief [27:27] New Data Interrupt Pointer 27 (27 = 0-31) (rw) */
+ unsigned int NDIP28:1; /**< \brief [28:28] New Data Interrupt Pointer 28 (28 = 0-31) (rw) */
+ unsigned int NDIP29:1; /**< \brief [29:29] New Data Interrupt Pointer 29 (29 = 0-31) (rw) */
+ unsigned int NDIP30:1; /**< \brief [30:30] New Data Interrupt Pointer 30 (30 = 0-31) (rw) */
+ unsigned int NDIP31:1; /**< \brief [31:31] New Data Interrupt Pointer 31 (31 = 0-31) (rw) */
+} Ifx_ERAY_NDIC1_Bits;
+
+/** \brief New Data Interrupt Control 2 */
+typedef struct _Ifx_ERAY_NDIC2_Bits
+{
+ unsigned int NDIP32:1; /**< \brief [0:0] New Data Interrupt Pointer 32 (32 = 32-63) (rw) */
+ unsigned int NDIP33:1; /**< \brief [1:1] New Data Interrupt Pointer 33 (33 = 32-63) (rw) */
+ unsigned int NDIP34:1; /**< \brief [2:2] New Data Interrupt Pointer 34 (34 = 32-63) (rw) */
+ unsigned int NDIP35:1; /**< \brief [3:3] New Data Interrupt Pointer 35 (35 = 32-63) (rw) */
+ unsigned int NDIP36:1; /**< \brief [4:4] New Data Interrupt Pointer 36 (36 = 32-63) (rw) */
+ unsigned int NDIP37:1; /**< \brief [5:5] New Data Interrupt Pointer 37 (37 = 32-63) (rw) */
+ unsigned int NDIP38:1; /**< \brief [6:6] New Data Interrupt Pointer 38 (38 = 32-63) (rw) */
+ unsigned int NDIP39:1; /**< \brief [7:7] New Data Interrupt Pointer 39 (39 = 32-63) (rw) */
+ unsigned int NDIP40:1; /**< \brief [8:8] New Data Interrupt Pointer 40 (40 = 32-63) (rw) */
+ unsigned int NDIP41:1; /**< \brief [9:9] New Data Interrupt Pointer 41 (41 = 32-63) (rw) */
+ unsigned int NDIP42:1; /**< \brief [10:10] New Data Interrupt Pointer 42 (42 = 32-63) (rw) */
+ unsigned int NDIP43:1; /**< \brief [11:11] New Data Interrupt Pointer 43 (43 = 32-63) (rw) */
+ unsigned int NDIP44:1; /**< \brief [12:12] New Data Interrupt Pointer 44 (44 = 32-63) (rw) */
+ unsigned int NDIP45:1; /**< \brief [13:13] New Data Interrupt Pointer 45 (45 = 32-63) (rw) */
+ unsigned int NDIP46:1; /**< \brief [14:14] New Data Interrupt Pointer 46 (46 = 32-63) (rw) */
+ unsigned int NDIP47:1; /**< \brief [15:15] New Data Interrupt Pointer 47 (47 = 32-63) (rw) */
+ unsigned int NDIP48:1; /**< \brief [16:16] New Data Interrupt Pointer 48 (48 = 32-63) (rw) */
+ unsigned int NDIP49:1; /**< \brief [17:17] New Data Interrupt Pointer 49 (49 = 32-63) (rw) */
+ unsigned int NDIP50:1; /**< \brief [18:18] New Data Interrupt Pointer 50 (50 = 32-63) (rw) */
+ unsigned int NDIP51:1; /**< \brief [19:19] New Data Interrupt Pointer 51 (51 = 32-63) (rw) */
+ unsigned int NDIP52:1; /**< \brief [20:20] New Data Interrupt Pointer 52 (52 = 32-63) (rw) */
+ unsigned int NDIP53:1; /**< \brief [21:21] New Data Interrupt Pointer 53 (53 = 32-63) (rw) */
+ unsigned int NDIP54:1; /**< \brief [22:22] New Data Interrupt Pointer 54 (54 = 32-63) (rw) */
+ unsigned int NDIP55:1; /**< \brief [23:23] New Data Interrupt Pointer 55 (55 = 32-63) (rw) */
+ unsigned int NDIP56:1; /**< \brief [24:24] New Data Interrupt Pointer 56 (56 = 32-63) (rw) */
+ unsigned int NDIP57:1; /**< \brief [25:25] New Data Interrupt Pointer 57 (57 = 32-63) (rw) */
+ unsigned int NDIP58:1; /**< \brief [26:26] New Data Interrupt Pointer 58 (58 = 32-63) (rw) */
+ unsigned int NDIP59:1; /**< \brief [27:27] New Data Interrupt Pointer 59 (59 = 32-63) (rw) */
+ unsigned int NDIP60:1; /**< \brief [28:28] New Data Interrupt Pointer 60 (60 = 32-63) (rw) */
+ unsigned int NDIP61:1; /**< \brief [29:29] New Data Interrupt Pointer 61 (61 = 32-63) (rw) */
+ unsigned int NDIP62:1; /**< \brief [30:30] New Data Interrupt Pointer 62 (62 = 32-63) (rw) */
+ unsigned int NDIP63:1; /**< \brief [31:31] New Data Interrupt Pointer 63 (63 = 32-63) (rw) */
+} Ifx_ERAY_NDIC2_Bits;
+
+/** \brief New Data Interrupt Control 3 */
+typedef struct _Ifx_ERAY_NDIC3_Bits
+{
+ unsigned int NDIP64:1; /**< \brief [0:0] New Data Interrupt Pointer 64 (64 = 64-95) (rw) */
+ unsigned int NDIP65:1; /**< \brief [1:1] New Data Interrupt Pointer 65 (65 = 64-95) (rw) */
+ unsigned int NDIP66:1; /**< \brief [2:2] New Data Interrupt Pointer 66 (66 = 64-95) (rw) */
+ unsigned int NDIP67:1; /**< \brief [3:3] New Data Interrupt Pointer 67 (67 = 64-95) (rw) */
+ unsigned int NDIP68:1; /**< \brief [4:4] New Data Interrupt Pointer 68 (68 = 64-95) (rw) */
+ unsigned int NDIP69:1; /**< \brief [5:5] New Data Interrupt Pointer 69 (69 = 64-95) (rw) */
+ unsigned int NDIP70:1; /**< \brief [6:6] New Data Interrupt Pointer 70 (70 = 64-95) (rw) */
+ unsigned int NDIP71:1; /**< \brief [7:7] New Data Interrupt Pointer 71 (71 = 64-95) (rw) */
+ unsigned int NDIP72:1; /**< \brief [8:8] New Data Interrupt Pointer 72 (72 = 64-95) (rw) */
+ unsigned int NDIP73:1; /**< \brief [9:9] New Data Interrupt Pointer 73 (73 = 64-95) (rw) */
+ unsigned int NDIP74:1; /**< \brief [10:10] New Data Interrupt Pointer 74 (74 = 64-95) (rw) */
+ unsigned int NDIP75:1; /**< \brief [11:11] New Data Interrupt Pointer 75 (75 = 64-95) (rw) */
+ unsigned int NDIP76:1; /**< \brief [12:12] New Data Interrupt Pointer 76 (76 = 64-95) (rw) */
+ unsigned int NDIP77:1; /**< \brief [13:13] New Data Interrupt Pointer 77 (77 = 64-95) (rw) */
+ unsigned int NDIP78:1; /**< \brief [14:14] New Data Interrupt Pointer 78 (78 = 64-95) (rw) */
+ unsigned int NDIP79:1; /**< \brief [15:15] New Data Interrupt Pointer 79 (79 = 64-95) (rw) */
+ unsigned int NDIP80:1; /**< \brief [16:16] New Data Interrupt Pointer 80 (80 = 64-95) (rw) */
+ unsigned int NDIP81:1; /**< \brief [17:17] New Data Interrupt Pointer 81 (81 = 64-95) (rw) */
+ unsigned int NDIP82:1; /**< \brief [18:18] New Data Interrupt Pointer 82 (82 = 64-95) (rw) */
+ unsigned int NDIP83:1; /**< \brief [19:19] New Data Interrupt Pointer 83 (83 = 64-95) (rw) */
+ unsigned int NDIP84:1; /**< \brief [20:20] New Data Interrupt Pointer 84 (84 = 64-95) (rw) */
+ unsigned int NDIP85:1; /**< \brief [21:21] New Data Interrupt Pointer 85 (85 = 64-95) (rw) */
+ unsigned int NDIP86:1; /**< \brief [22:22] New Data Interrupt Pointer 86 (86 = 64-95) (rw) */
+ unsigned int NDIP87:1; /**< \brief [23:23] New Data Interrupt Pointer 87 (87 = 64-95) (rw) */
+ unsigned int NDIP88:1; /**< \brief [24:24] New Data Interrupt Pointer 88 (88 = 64-95) (rw) */
+ unsigned int NDIP89:1; /**< \brief [25:25] New Data Interrupt Pointer 89 (89 = 64-95) (rw) */
+ unsigned int NDIP90:1; /**< \brief [26:26] New Data Interrupt Pointer 90 (90 = 64-95) (rw) */
+ unsigned int NDIP91:1; /**< \brief [27:27] New Data Interrupt Pointer 91 (91 = 64-95) (rw) */
+ unsigned int NDIP92:1; /**< \brief [28:28] New Data Interrupt Pointer 92 (92 = 64-95) (rw) */
+ unsigned int NDIP93:1; /**< \brief [29:29] New Data Interrupt Pointer 93 (93 = 64-95) (rw) */
+ unsigned int NDIP94:1; /**< \brief [30:30] New Data Interrupt Pointer 94 (94 = 64-95) (rw) */
+ unsigned int NDIP95:1; /**< \brief [31:31] New Data Interrupt Pointer 95 (95 = 64-95) (rw) */
+} Ifx_ERAY_NDIC3_Bits;
+
+/** \brief New Data Interrupt Control 4 */
+typedef struct _Ifx_ERAY_NDIC4_Bits
+{
+ unsigned int NDIP96:1; /**< \brief [0:0] New Data Interrupt Pointer 96 (96 = 96-127) (rw) */
+ unsigned int NDIP97:1; /**< \brief [1:1] New Data Interrupt Pointer 97 (97 = 96-127) (rw) */
+ unsigned int NDIP98:1; /**< \brief [2:2] New Data Interrupt Pointer 98 (98 = 96-127) (rw) */
+ unsigned int NDIP99:1; /**< \brief [3:3] New Data Interrupt Pointer 99 (99 = 96-127) (rw) */
+ unsigned int NDIP100:1; /**< \brief [4:4] New Data Interrupt Pointer 100 (100 = 96-127) (rw) */
+ unsigned int NDIP101:1; /**< \brief [5:5] New Data Interrupt Pointer 101 (101 = 96-127) (rw) */
+ unsigned int NDIP102:1; /**< \brief [6:6] New Data Interrupt Pointer 102 (102 = 96-127) (rw) */
+ unsigned int NDIP103:1; /**< \brief [7:7] New Data Interrupt Pointer 103 (103 = 96-127) (rw) */
+ unsigned int NDIP104:1; /**< \brief [8:8] New Data Interrupt Pointer 104 (104 = 96-127) (rw) */
+ unsigned int NDIP105:1; /**< \brief [9:9] New Data Interrupt Pointer 105 (105 = 96-127) (rw) */
+ unsigned int NDIP106:1; /**< \brief [10:10] New Data Interrupt Pointer 106 (106 = 96-127) (rw) */
+ unsigned int NDIP107:1; /**< \brief [11:11] New Data Interrupt Pointer 107 (107 = 96-127) (rw) */
+ unsigned int NDIP108:1; /**< \brief [12:12] New Data Interrupt Pointer 108 (108 = 96-127) (rw) */
+ unsigned int NDIP109:1; /**< \brief [13:13] New Data Interrupt Pointer 109 (109 = 96-127) (rw) */
+ unsigned int NDIP110:1; /**< \brief [14:14] New Data Interrupt Pointer 110 (110 = 96-127) (rw) */
+ unsigned int NDIP111:1; /**< \brief [15:15] New Data Interrupt Pointer 111 (111 = 96-127) (rw) */
+ unsigned int NDIP112:1; /**< \brief [16:16] New Data Interrupt Pointer 112 (112 = 96-127) (rw) */
+ unsigned int NDIP113:1; /**< \brief [17:17] New Data Interrupt Pointer 113 (113 = 96-127) (rw) */
+ unsigned int NDIP114:1; /**< \brief [18:18] New Data Interrupt Pointer 114 (114 = 96-127) (rw) */
+ unsigned int NDIP115:1; /**< \brief [19:19] New Data Interrupt Pointer 115 (115 = 96-127) (rw) */
+ unsigned int NDIP116:1; /**< \brief [20:20] New Data Interrupt Pointer 116 (116 = 96-127) (rw) */
+ unsigned int NDIP117:1; /**< \brief [21:21] New Data Interrupt Pointer 117 (117 = 96-127) (rw) */
+ unsigned int NDIP118:1; /**< \brief [22:22] New Data Interrupt Pointer 118 (118 = 96-127) (rw) */
+ unsigned int NDIP119:1; /**< \brief [23:23] New Data Interrupt Pointer 119 (119 = 96-127) (rw) */
+ unsigned int NDIP120:1; /**< \brief [24:24] New Data Interrupt Pointer 120 (120 = 96-127) (rw) */
+ unsigned int NDIP121:1; /**< \brief [25:25] New Data Interrupt Pointer 121 (121 = 96-127) (rw) */
+ unsigned int NDIP122:1; /**< \brief [26:26] New Data Interrupt Pointer 122 (122 = 96-127) (rw) */
+ unsigned int NDIP123:1; /**< \brief [27:27] New Data Interrupt Pointer 123 (123 = 96-127) (rw) */
+ unsigned int NDIP124:1; /**< \brief [28:28] New Data Interrupt Pointer 124 (124 = 96-127) (rw) */
+ unsigned int NDIP125:1; /**< \brief [29:29] New Data Interrupt Pointer 125 (125 = 96-127) (rw) */
+ unsigned int NDIP126:1; /**< \brief [30:30] New Data Interrupt Pointer 126 (126 = 96-127) (rw) */
+ unsigned int NDIP127:1; /**< \brief [31:31] New Data Interrupt Pointer 127 (127 = 96-127) (rw) */
+} Ifx_ERAY_NDIC4_Bits;
+
+/** \brief NEM Configuration Register */
+typedef struct _Ifx_ERAY_NEMC_Bits
+{
+ unsigned int NML:4; /**< \brief [3:0] Network Management Vector Length (gNetworkManagementVectorLength) (rw) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_ERAY_NEMC_Bits;
+
+/** \brief Network Management Vector */
+typedef struct _Ifx_ERAY_NMV_Bits
+{
+ unsigned int NM:32; /**< \brief [31:0] Network Management Vector (rh) */
+} Ifx_ERAY_NMV_Bits;
+
+/** \brief Output Buffer Command Mask */
+typedef struct _Ifx_ERAY_OBCM_Bits
+{
+ unsigned int RHSS:1; /**< \brief [0:0] Read Header Section Shadow (rwh) */
+ unsigned int RDSS:1; /**< \brief [1:1] Read Data Section Shadow (rwh) */
+ unsigned int reserved_2:14; /**< \brief \internal Reserved */
+ unsigned int RHSH:1; /**< \brief [16:16] Read Header Section Host (rh) */
+ unsigned int RDSH:1; /**< \brief [17:17] Read Data Section Host (rh) */
+ unsigned int reserved_18:14; /**< \brief \internal Reserved */
+} Ifx_ERAY_OBCM_Bits;
+
+/** \brief Output Buffer Command Request */
+typedef struct _Ifx_ERAY_OBCR_Bits
+{
+ unsigned int OBRS:7; /**< \brief [6:0] Output Buffer Request Shadow (rw) */
+ unsigned int reserved_7:1; /**< \brief \internal Reserved */
+ unsigned int VIEW:1; /**< \brief [8:8] View Shadow Buffer (rw) */
+ unsigned int REQ:1; /**< \brief [9:9] Request Message RAM Transfer (rw) */
+ unsigned int reserved_10:5; /**< \brief \internal Reserved */
+ unsigned int OBSYS:1; /**< \brief [15:15] Output Buffer Busy Shadow (rh) */
+ unsigned int OBRH:7; /**< \brief [22:16] Output Buffer Request Host (rh) */
+ unsigned int reserved_23:9; /**< \brief \internal Reserved */
+} Ifx_ERAY_OBCR_Bits;
+
+/** \brief OCDS Control and Status */
+typedef struct _Ifx_ERAY_OCS_Bits
+{
+ unsigned int reserved_0:24; /**< \brief \internal Reserved */
+ unsigned int SUS:4; /**< \brief [27:24] OCDS Suspend Control (rw) */
+ unsigned int SUS_P:1; /**< \brief [28:28] SUS Write Protection (w) */
+ unsigned int SUSSTA:1; /**< \brief [29:29] Suspend State (rh) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_ERAY_OCS_Bits;
+
+/** \brief Offset Correction Value */
+typedef struct _Ifx_ERAY_OCV_Bits
+{
+ unsigned int OCV:19; /**< \brief [18:0] Offset Correction Value (vOffsetCorrection) (rh) */
+ unsigned int reserved_19:13; /**< \brief \internal Reserved */
+} Ifx_ERAY_OCV_Bits;
+
+/** \brief Odd Sync ID Symbol Window */
+typedef struct _Ifx_ERAY_OSID_Bits
+{
+ unsigned int OID:10; /**< \brief [9:0] Odd Sync ID (vsSyncIDListA,B odd) (rh) */
+ unsigned int reserved_10:4; /**< \brief \internal Reserved */
+ unsigned int RXOA:1; /**< \brief [14:14] Received Odd Sync ID on Channel A (rh) */
+ unsigned int RXOB:1; /**< \brief [15:15] Received Odd Sync ID on Channel B (rh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_ERAY_OSID_Bits;
+
+/** \brief OCDS Trigger Set Select */
+typedef struct _Ifx_ERAY_OTSS_Bits
+{
+ unsigned int OTGB0:2; /**< \brief [1:0] Trigger Set for OTGB0 (rw) */
+ unsigned int reserved_2:6; /**< \brief \internal Reserved */
+ unsigned int OTGB1:2; /**< \brief [9:8] Trigger Set for OTGB1 (rw) */
+ unsigned int reserved_10:6; /**< \brief \internal Reserved */
+ unsigned int OTGB2:1; /**< \brief [16:16] Trigger Set for OTGB2 (rw) */
+ unsigned int reserved_17:15; /**< \brief \internal Reserved */
+} Ifx_ERAY_OTSS_Bits;
+
+/** \brief PRT Configuration Register 1 */
+typedef struct _Ifx_ERAY_PRTC1_Bits
+{
+ unsigned int TSST:4; /**< \brief [3:0] Transmission Start Sequence Transmitter (gdTSSTransmitter) (rw) */
+ unsigned int CASM:7; /**< \brief [10:4] Collision Avoidance Symbol Maximum(gdCASRxLowMax) (rw) */
+ unsigned int reserved_11:1; /**< \brief \internal Reserved */
+ unsigned int SPP:2; /**< \brief [13:12] Strobe Point Position (rw) */
+ unsigned int BRP:2; /**< \brief [15:14] Baud Rate Prescaler(gdSampleClockPeriod, pSamplePerMicrotick) (rw) */
+ unsigned int RXW:9; /**< \brief [24:16] Wakeup Symbol Receive Window Length (gdWakeupSymbolRxWindow) (rw) */
+ unsigned int reserved_25:1; /**< \brief \internal Reserved */
+ unsigned int RWP:6; /**< \brief [31:26] Repetitions of Tx Wakeup Pattern (pWakeupPattern) (rw) */
+} Ifx_ERAY_PRTC1_Bits;
+
+/** \brief PRT Configuration Register 2 */
+typedef struct _Ifx_ERAY_PRTC2_Bits
+{
+ unsigned int RXI:6; /**< \brief [5:0] Wakeup Symbol Receive Idle (gdWakeupSymbolRxIdle) (rw) */
+ unsigned int reserved_6:2; /**< \brief \internal Reserved */
+ unsigned int RXL:6; /**< \brief [13:8] Wakeup Symbol Receive Low(gdWakeupSymbolRxLow) (rw) */
+ unsigned int reserved_14:2; /**< \brief \internal Reserved */
+ unsigned int TXI:8; /**< \brief [23:16] Wakeup Symbol Transmit Idle (gdWakeupSymbolTxIdle) (rw) */
+ unsigned int TXL:6; /**< \brief [29:24] Wakeup Symbol Transmit Low (gdWakeupSymbolTxLow) (rw) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_ERAY_PRTC2_Bits;
+
+/** \brief Rate Correction Value */
+typedef struct _Ifx_ERAY_RCV_Bits
+{
+ unsigned int RCV:12; /**< \brief [11:0] Rate Correction Value (vRateCorrection) (rh) */
+ unsigned int reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_ERAY_RCV_Bits;
+
+/** \brief Read Data Section */
+typedef struct _Ifx_ERAY_RDDS_Bits
+{
+ unsigned int MDRB0:8; /**< \brief [7:0] 32-Bit Word nn, Byte 0 (rh) */
+ unsigned int MDRB1:8; /**< \brief [15:8] 32-Bit Word nn, Byte 1 (rh) */
+ unsigned int MDRB2:8; /**< \brief [23:16] 32-Bit Word nn, Byte 2 (rh) */
+ unsigned int MDRB3:8; /**< \brief [31:24] 32-Bit Word nn, Byte 3 (rh) */
+} Ifx_ERAY_RDDS_Bits;
+
+/** \brief Read Header Section 1 */
+typedef struct _Ifx_ERAY_RDHS1_Bits
+{
+ unsigned int FID:11; /**< \brief [10:0] Frame ID (rh) */
+ unsigned int reserved_11:5; /**< \brief \internal Reserved */
+ unsigned int CYC:7; /**< \brief [22:16] Cycle Code (rh) */
+ unsigned int reserved_23:1; /**< \brief \internal Reserved */
+ unsigned int CHA:1; /**< \brief [24:24] Channel Filter Control A (rh) */
+ unsigned int CHB:1; /**< \brief [25:25] Channel Filter Control B (rh) */
+ unsigned int CFG:1; /**< \brief [26:26] Message Buffer Direction Configuration Bit (rh) */
+ unsigned int PPIT:1; /**< \brief [27:27] Payload Preamble Indicator Transmit (rh) */
+ unsigned int TXM:1; /**< \brief [28:28] Transmission Mode (rh) */
+ unsigned int MBI:1; /**< \brief [29:29] Message Buffer Service Request (rh) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_ERAY_RDHS1_Bits;
+
+/** \brief Read Header Section 2 */
+typedef struct _Ifx_ERAY_RDHS2_Bits
+{
+ unsigned int CRC:11; /**< \brief [10:0] Header CRC (vRF!Header!HeaderCRC) (rh) */
+ unsigned int reserved_11:5; /**< \brief \internal Reserved */
+ unsigned int PLC:7; /**< \brief [22:16] Payload Length Configured (rh) */
+ unsigned int reserved_23:1; /**< \brief \internal Reserved */
+ unsigned int PLR:7; /**< \brief [30:24] Payload Length Received (vRF!Header!Length) (rh) */
+ unsigned int reserved_31:1; /**< \brief \internal Reserved */
+} Ifx_ERAY_RDHS2_Bits;
+
+/** \brief Read Header Section 3 */
+typedef struct _Ifx_ERAY_RDHS3_Bits
+{
+ unsigned int DP:11; /**< \brief [10:0] Data Pointer (rh) */
+ unsigned int reserved_11:5; /**< \brief \internal Reserved */
+ unsigned int RCC:6; /**< \brief [21:16] Receive Cycle Count (vRF!Header!CycleCount) (rh) */
+ unsigned int reserved_22:2; /**< \brief \internal Reserved */
+ unsigned int RCI:1; /**< \brief [24:24] Received on Channel Indicator (vSS!Channel) (rh) */
+ unsigned int SFI:1; /**< \brief [25:25] Startup Frame Indicator (vRF!Header!SuFIndicator) (rh) */
+ unsigned int SYN:1; /**< \brief [26:26] SYNC Frame Indicator (vRF!Header!SyFIndicator) (rh) */
+ unsigned int NFI:1; /**< \brief [27:27] NULL Frame Indicator (vRF!Header!NFIndicator) (rh) */
+ unsigned int PPI:1; /**< \brief [28:28] Payload Preamble Indicator (vRF!Header!PPIndicator) (rh) */
+ unsigned int RES:1; /**< \brief [29:29] Reserved Bit (vRF!Header!Reserved) (rh) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_ERAY_RDHS3_Bits;
+
+/** \brief Slot Counter Value */
+typedef struct _Ifx_ERAY_SCV_Bits
+{
+ unsigned int SCCA:11; /**< \brief [10:0] Slot Counter Channel A (vSlotCounter[A]) (rh) */
+ unsigned int reserved_11:5; /**< \brief \internal Reserved */
+ unsigned int SCCB:11; /**< \brief [26:16] Slot Counter Channel B (vSlotCounter[B]) (rh) */
+ unsigned int reserved_27:5; /**< \brief \internal Reserved */
+} Ifx_ERAY_SCV_Bits;
+
+/** \brief SYNC Frame Status */
+typedef struct _Ifx_ERAY_SFS_Bits
+{
+ unsigned int VSAE:4; /**< \brief [3:0] Valid SYNC Frames Channel A, even communication cycle (rh) */
+ unsigned int VSAO:4; /**< \brief [7:4] Valid SYNC Frames Channel A, odd communication cycle (rh) */
+ unsigned int VSBE:4; /**< \brief [11:8] Valid SYNC Frames Channel B, even communication cycle (rh) */
+ unsigned int VSBO:4; /**< \brief [15:12] Valid SYNC Frames Channel B, odd communication cycle (rh) */
+ unsigned int MOCS:1; /**< \brief [16:16] Missing Offset Correction Signal (rh) */
+ unsigned int OCLR:1; /**< \brief [17:17] Offset Correction Limit Reached (rh) */
+ unsigned int MRCS:1; /**< \brief [18:18] Missing Rate Correction Signal (rh) */
+ unsigned int RCLR:1; /**< \brief [19:19] Rate Correction Limit Reached (rh) */
+ unsigned int reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_ERAY_SFS_Bits;
+
+/** \brief Status Service Request Enable Reset */
+typedef struct _Ifx_ERAY_SIER_Bits
+{
+ unsigned int WSTE:1; /**< \brief [0:0] Wakeup Status Service Request Enable (rwh) */
+ unsigned int CASE:1; /**< \brief [1:1] Collision Avoidance Symbol Service Request Enable (rwh) */
+ unsigned int CYCSE:1; /**< \brief [2:2] Cycle Start Service Request Enable (rwh) */
+ unsigned int TXIE:1; /**< \brief [3:3] Transmit Service Request Enable (rwh) */
+ unsigned int RXIE:1; /**< \brief [4:4] Receive Service Request Enable (rwh) */
+ unsigned int RFNEE:1; /**< \brief [5:5] Receive FIFO Not Empty Service Request Enable (rwh) */
+ unsigned int RFCLE:1; /**< \brief [6:6] Receive FIFO Critical Level Service Request Enable (rwh) */
+ unsigned int NMVCE:1; /**< \brief [7:7] Network Management Vector Changed Service Request Enable (rwh) */
+ unsigned int TI0E:1; /**< \brief [8:8] Timer Service Request 0 Enable (rwh) */
+ unsigned int TI1E:1; /**< \brief [9:9] Timer Service Request 1 Enable (rwh) */
+ unsigned int TIBCE:1; /**< \brief [10:10] Transfer Input Buffer Completed Service Request Enable (rwh) */
+ unsigned int TOBCE:1; /**< \brief [11:11] Transfer Output Buffer Completed Service Request Enable (rwh) */
+ unsigned int SWEE:1; /**< \brief [12:12] Stop Watch Event Service Request Enable (rwh) */
+ unsigned int SUCSE:1; /**< \brief [13:13] Startup Completed Successfully Service Request Enable (rwh) */
+ unsigned int MBSIE:1; /**< \brief [14:14] Message Buffer Status Service Request Enable (rwh) */
+ unsigned int SDSE:1; /**< \brief [15:15] Start of Dynamic Segment Service Request Enable (rwh) */
+ unsigned int WUPAE:1; /**< \brief [16:16] Wakeup Pattern Channel A Service Request Enable (rwh) */
+ unsigned int MTSAE:1; /**< \brief [17:17] Media Access Test Symbol Channel A Service Request Enable (rwh) */
+ unsigned int reserved_18:6; /**< \brief \internal Reserved */
+ unsigned int WUPBE:1; /**< \brief [24:24] Wakeup Pattern Channel B Service Request Enable (rwh) */
+ unsigned int MTSBE:1; /**< \brief [25:25] Media Access Test Symbol Channel B Service Request Enable (rwh) */
+ unsigned int reserved_26:6; /**< \brief \internal Reserved */
+} Ifx_ERAY_SIER_Bits;
+
+/** \brief Status Service Request Enable Set */
+typedef struct _Ifx_ERAY_SIES_Bits
+{
+ unsigned int WSTE:1; /**< \brief [0:0] Wakeup Status Service Request Enable (rwh) */
+ unsigned int CASE:1; /**< \brief [1:1] Collision Avoidance Symbol Service Request Enable (rwh) */
+ unsigned int CYCSE:1; /**< \brief [2:2] Cycle Start Service Request Enable (rwh) */
+ unsigned int TXIE:1; /**< \brief [3:3] Transmit Service Request Enable (rwh) */
+ unsigned int RXIE:1; /**< \brief [4:4] Receive Service Request Enable (rwh) */
+ unsigned int RFNEE:1; /**< \brief [5:5] Receive FIFO Not Empty Service Request Enable (rwh) */
+ unsigned int RFCLE:1; /**< \brief [6:6] Receive FIFO Critical Level Service Request Enable (rwh) */
+ unsigned int NMVCE:1; /**< \brief [7:7] Network Management Vector Changed Service Request Enable (rwh) */
+ unsigned int TI0E:1; /**< \brief [8:8] Timer Service Request 0 Enable (rwh) */
+ unsigned int TI1E:1; /**< \brief [9:9] Timer Service Request 1 Enable (rwh) */
+ unsigned int TIBCE:1; /**< \brief [10:10] Transfer Input Buffer Completed Service Request Enable (rwh) */
+ unsigned int TOBCE:1; /**< \brief [11:11] Transfer Output Buffer Completed Service Request Enable (rwh) */
+ unsigned int SWEE:1; /**< \brief [12:12] Stop Watch Event Service Request Enable (rwh) */
+ unsigned int SUCSE:1; /**< \brief [13:13] Startup Completed Successfully Service Request Enable (rwh) */
+ unsigned int MBSIE:1; /**< \brief [14:14] Message Buffer Status Service Request Enable (rwh) */
+ unsigned int SDSE:1; /**< \brief [15:15] Start of Dynamic Segment Service Request Enable (rwh) */
+ unsigned int WUPAE:1; /**< \brief [16:16] Wakeup Pattern Channel A Service Request Enable (rwh) */
+ unsigned int MTSAE:1; /**< \brief [17:17] Media Access Test Symbol Channel A Service Request Enable (rwh) */
+ unsigned int reserved_18:6; /**< \brief \internal Reserved */
+ unsigned int WUPBE:1; /**< \brief [24:24] Wakeup Pattern Channel B Service Request Enable (rwh) */
+ unsigned int MTSBE:1; /**< \brief [25:25] Media Access Test Symbol Channel B Service Request Enable (rwh) */
+ unsigned int reserved_26:6; /**< \brief \internal Reserved */
+} Ifx_ERAY_SIES_Bits;
+
+/** \brief Status Service Request Line Select */
+typedef struct _Ifx_ERAY_SILS_Bits
+{
+ unsigned int WSTL:1; /**< \brief [0:0] Wakeup Status Service Request Line (rw) */
+ unsigned int CASL:1; /**< \brief [1:1] Collision Avoidance Symbol Service Request Line (rw) */
+ unsigned int CYCSL:1; /**< \brief [2:2] Cycle Start Service Request Line (rw) */
+ unsigned int TXIL:1; /**< \brief [3:3] Transmit Service Request Line (rw) */
+ unsigned int RXIL:1; /**< \brief [4:4] Receive Service Request Line (rw) */
+ unsigned int RFNEL:1; /**< \brief [5:5] Receive FIFO Not Empty Service Request Line (rw) */
+ unsigned int RFCLL:1; /**< \brief [6:6] Receive FIFO Critical Level Service Request Line (rw) */
+ unsigned int NMVCL:1; /**< \brief [7:7] Network Management Vector Changed Service Request Line (rw) */
+ unsigned int TI0L:1; /**< \brief [8:8] Timer Service Request 0 Line (rw) */
+ unsigned int TI1L:1; /**< \brief [9:9] Timer Service Request 1 Line (rw) */
+ unsigned int TIBCL:1; /**< \brief [10:10] Transfer Input Buffer Completed Service Request Line (rw) */
+ unsigned int TOBCL:1; /**< \brief [11:11] Transfer Output Buffer Completed Service Request Line (rw) */
+ unsigned int SWEL:1; /**< \brief [12:12] Stop Watch Event Service Request Line (rw) */
+ unsigned int SUCSL:1; /**< \brief [13:13] Startup Completed Successfully Service Request Line (rw) */
+ unsigned int MBSIL:1; /**< \brief [14:14] Message Buffer Status Service Request Line (rw) */
+ unsigned int SDSL:1; /**< \brief [15:15] Start of Dynamic Segment Service Request Line (rw) */
+ unsigned int WUPAL:1; /**< \brief [16:16] Wakeup Pattern Channel A Service Request Line (rw) */
+ unsigned int MTSAL:1; /**< \brief [17:17] Media Access Test Symbol Channel A Service Request Line (rw) */
+ unsigned int reserved_18:6; /**< \brief \internal Reserved */
+ unsigned int WUPBL:1; /**< \brief [24:24] Wakeup Pattern Channel B Service Request Line (rw) */
+ unsigned int MTSBL:1; /**< \brief [25:25] Media Access Test Symbol Channel B Service Request Line (rw) */
+ unsigned int reserved_26:6; /**< \brief \internal Reserved */
+} Ifx_ERAY_SILS_Bits;
+
+/** \brief Status Service Request Register */
+typedef struct _Ifx_ERAY_SIR_Bits
+{
+ unsigned int WST:1; /**< \brief [0:0] Wakeup Status (rwh) */
+ unsigned int CAS:1; /**< \brief [1:1] Collision Avoidance Symbol (rwh) */
+ unsigned int CYCS:1; /**< \brief [2:2] Cycle Start Service Request (rwh) */
+ unsigned int TXI:1; /**< \brief [3:3] Transmit Service Request (rwh) */
+ unsigned int RXI:1; /**< \brief [4:4] Receive Service Request (rwh) */
+ unsigned int RFNE:1; /**< \brief [5:5] Receive FIFO Not Empty (rh) */
+ unsigned int RFCL:1; /**< \brief [6:6] Receive FIFO Critical Level (rh) */
+ unsigned int NMVC:1; /**< \brief [7:7] Network Management Vector Changed (rwh) */
+ unsigned int TI0:1; /**< \brief [8:8] Timer Service Request 0 (rwh) */
+ unsigned int TI1:1; /**< \brief [9:9] Timer Service Request 1 (rwh) */
+ unsigned int TIBC:1; /**< \brief [10:10] Transfer Input Buffer Completed (rwh) */
+ unsigned int TOBC:1; /**< \brief [11:11] Transfer Output Buffer Completed (rwh) */
+ unsigned int SWE:1; /**< \brief [12:12] Stop Watch Event (rwh) */
+ unsigned int SUCS:1; /**< \brief [13:13] Startup Completed Successfully (rwh) */
+ unsigned int MBSI:1; /**< \brief [14:14] Message Buffer Status Service Request (rwh) */
+ unsigned int SDS:1; /**< \brief [15:15] Start of Dynamic Segment (rwh) */
+ unsigned int WUPA:1; /**< \brief [16:16] Wakeup Pattern Channel A (rwh) */
+ unsigned int MTSA:1; /**< \brief [17:17] MTS Received on Channel A (vSS!ValidMTSA) (rwh) */
+ unsigned int reserved_18:6; /**< \brief \internal Reserved */
+ unsigned int WUPB:1; /**< \brief [24:24] Wakeup Pattern Channel B (rwh) */
+ unsigned int MTSB:1; /**< \brief [25:25] MTS Received on Channel B (vSS!ValidMTSB) (rwh) */
+ unsigned int reserved_26:6; /**< \brief \internal Reserved */
+} Ifx_ERAY_SIR_Bits;
+
+/** \brief Stop Watch Register 1 */
+typedef struct _Ifx_ERAY_STPW1_Bits
+{
+ unsigned int ESWT:1; /**< \brief [0:0] Enable Stop Watch Trigger (rwh) */
+ unsigned int SWMS:1; /**< \brief [1:1] Stop Watch Mode Select (rw) */
+ unsigned int EDGE:1; /**< \brief [2:2] Stop Watch Trigger Edge Select (rw) */
+ unsigned int SSWT:1; /**< \brief [3:3] Software Stop Watch Trigger (rwh) */
+ unsigned int EETP:1; /**< \brief [4:4] Enable External Trigger Pin (rw) */
+ unsigned int EINT0:1; /**< \brief [5:5] Enable Service Request 0 Trigger (rw) */
+ unsigned int EINT1:1; /**< \brief [6:6] Enable Service Request 1 Trigger (rw) */
+ unsigned int reserved_7:1; /**< \brief \internal Reserved */
+ unsigned int SCCV:6; /**< \brief [13:8] Stopped Cycle Counter Value (rh) */
+ unsigned int reserved_14:2; /**< \brief \internal Reserved */
+ unsigned int SMTV:14; /**< \brief [29:16] Stopped Macrotick Value (rh) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_ERAY_STPW1_Bits;
+
+/** \brief Stop Watch Register 2 */
+typedef struct _Ifx_ERAY_STPW2_Bits
+{
+ unsigned int SSCVA:11; /**< \brief [10:0] Stop Watch Captured Slot Counter Value Channel A (rh) */
+ unsigned int reserved_11:5; /**< \brief \internal Reserved */
+ unsigned int SSCVB:11; /**< \brief [26:16] Stop Watch Captured Slot Counter Value Channel B (rh) */
+ unsigned int reserved_27:5; /**< \brief \internal Reserved */
+} Ifx_ERAY_STPW2_Bits;
+
+/** \brief SUC Configuration Register 1 */
+typedef struct _Ifx_ERAY_SUCC1_Bits
+{
+ unsigned int CMD:4; /**< \brief [3:0] CHI Command Vector (rwh) */
+ unsigned int reserved_4:3; /**< \brief \internal Reserved */
+ unsigned int PBSY:1; /**< \brief [7:7] POC Busy (rh) */
+ unsigned int TXST:1; /**< \brief [8:8] Transmit Startup Frame in Key Slot (pKeySlotUsedForStartup) (rw) */
+ unsigned int TXSY:1; /**< \brief [9:9] Transmit SYNC Frame in Key Slot(pKeySlotUsedForSync) (rw) */
+ unsigned int reserved_10:1; /**< \brief \internal Reserved */
+ unsigned int CSA:5; /**< \brief [15:11] Cold Start Attempts(gColdStartAttempts) (rw) */
+ unsigned int PTA:5; /**< \brief [20:16] Passive to Active (pAllowPassiveToActive) (rw) */
+ unsigned int WUCS:1; /**< \brief [21:21] Wakeup Channel Select (pWakeupChannel) (rw) */
+ unsigned int TSM:1; /**< \brief [22:22] Transmission Slot Mode (pSingleSlotEnabled) (rw) */
+ unsigned int HCSE:1; /**< \brief [23:23] Halt due to Clock Sync Error (pAllowHaltDueToClock) (rw) */
+ unsigned int MTSA:1; /**< \brief [24:24] Select Channel A for MTS Transmission (rw) */
+ unsigned int MTSB:1; /**< \brief [25:25] Select Channel B for MTS Transmission (rw) */
+ unsigned int CCHA:1; /**< \brief [26:26] Connected to Channel A (pChannels) (rw) */
+ unsigned int CCHB:1; /**< \brief [27:27] Connected to Channel B (pChannels) (rw) */
+ unsigned int reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_ERAY_SUCC1_Bits;
+
+/** \brief SUC Configuration Register 2 */
+typedef struct _Ifx_ERAY_SUCC2_Bits
+{
+ unsigned int LT:21; /**< \brief [20:0] Listen Timeout (pdListenTimeout) (rw) */
+ unsigned int reserved_21:3; /**< \brief \internal Reserved */
+ unsigned int LTN:4; /**< \brief [27:24] Listen Time-out Noise (gListenNoise - 1) (rw) */
+ unsigned int reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_ERAY_SUCC2_Bits;
+
+/** \brief SUC Configuration Register 3 */
+typedef struct _Ifx_ERAY_SUCC3_Bits
+{
+ unsigned int WCP:4; /**< \brief [3:0] Maximum Without Clock Correction Passive (gMaxWithoutClockCorrectionPassive) (rw) */
+ unsigned int WCF:4; /**< \brief [7:4] Maximum Without Clock Correction Fatal (gMaxWithoutClockCorrecti on Fatal) (rw) */
+ unsigned int reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_ERAY_SUCC3_Bits;
+
+/** \brief Symbol Window and Network Idle Time Status */
+typedef struct _Ifx_ERAY_SWNIT_Bits
+{
+ unsigned int SESA:1; /**< \brief [0:0] Syntax Error in Symbol Window Channel A (vSS!SyntaxErrorA) (rh) */
+ unsigned int SBSA:1; /**< \brief [1:1] Slot Boundary Violation in Symbol Window Channel A (vSS!BViolationA) (rh) */
+ unsigned int TCSA:1; /**< \brief [2:2] Transmission Conflict in Symbol Window Channel A (vSS!TxConflictA) (rh) */
+ unsigned int SESB:1; /**< \brief [3:3] Syntax Error in Symbol Window Channel B (vSS!SyntaxErrorB) (rh) */
+ unsigned int SBSB:1; /**< \brief [4:4] Slot Boundary Violation in Symbol Window Channel B (vSS!BViolationB) (rh) */
+ unsigned int TCSB:1; /**< \brief [5:5] Transmission Conflict in Symbol Window Channel B (vSS!TxConflictB) (rh) */
+ unsigned int MTSA:1; /**< \brief [6:6] MTS Received on Channel A (vSS!ValidMTSA) (rh) */
+ unsigned int MTSB:1; /**< \brief [7:7] MTS Received on Channel B (vSS!ValidMTSB) (rh) */
+ unsigned int SENA:1; /**< \brief [8:8] Syntax Error during network idle time (NIT) Channel A (vSS!SyntaxErrorA) (rh) */
+ unsigned int SBNA:1; /**< \brief [9:9] Slot Boundary Violation during network idle time (NIT) Channel A (vSS!BViolationA) (rh) */
+ unsigned int SENB:1; /**< \brief [10:10] Syntax Error during network idle time (NIT) Channel B (vSS!SyntaxErrorB) (rh) */
+ unsigned int SBNB:1; /**< \brief [11:11] Slot Boundary Violation during network idle time (NIT) Channel B (vSS!BViolationB) (rh) */
+ unsigned int reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_ERAY_SWNIT_Bits;
+
+/** \brief Timer 0 Configuration */
+typedef struct _Ifx_ERAY_T0C_Bits
+{
+ unsigned int T0RC:1; /**< \brief [0:0] Timer 0 Run Control (rwh) */
+ unsigned int T0MS:1; /**< \brief [1:1] Timer 0 Mode Select (rw) */
+ unsigned int reserved_2:6; /**< \brief \internal Reserved */
+ unsigned int T0CC:7; /**< \brief [14:8] Timer 0 Cycle Code (rw) */
+ unsigned int reserved_15:1; /**< \brief \internal Reserved */
+ unsigned int T0MO:14; /**< \brief [29:16] Timer 0 Macrotick Offset (rw) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_ERAY_T0C_Bits;
+
+/** \brief Timer 1 Configuration */
+typedef struct _Ifx_ERAY_T1C_Bits
+{
+ unsigned int T1RC:1; /**< \brief [0:0] Timer 1 Run Control (rwh) */
+ unsigned int T1MS:1; /**< \brief [1:1] Timer 1 Mode Select (rw) */
+ unsigned int reserved_2:14; /**< \brief \internal Reserved */
+ unsigned int T1MC:14; /**< \brief [29:16] Timer 1 Macrotick Count (rw) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_ERAY_T1C_Bits;
+
+/** \brief Test Register 1 */
+typedef struct _Ifx_ERAY_TEST1_Bits
+{
+ unsigned int WRTEN:1; /**< \brief [0:0] Write Test Register Enable (rw) */
+ unsigned int ELBE:1; /**< \brief [1:1] External Loop Back Enable (rw) */
+ unsigned int reserved_2:2; /**< \brief \internal Reserved */
+ unsigned int TMC:2; /**< \brief [5:4] Test Multiplexer Control (rw) */
+ unsigned int reserved_6:2; /**< \brief \internal Reserved */
+ unsigned int AOA:1; /**< \brief [8:8] Activity on A (rh) */
+ unsigned int AOB:1; /**< \brief [9:9] Activity on B (rh) */
+ unsigned int reserved_10:6; /**< \brief \internal Reserved */
+ unsigned int RXA:1; /**< \brief [16:16] Read Channel A Receive Pin (rh) */
+ unsigned int RXB:1; /**< \brief [17:17] Read Channel B Receive Pin (rh) */
+ unsigned int TXA:1; /**< \brief [18:18] Read or Write to Channel A Transmit Pin (rwh) */
+ unsigned int TXB:1; /**< \brief [19:19] Read or Write to Channel B Transmit Pin (rwh) */
+ unsigned int TXENA:1; /**< \brief [20:20] Read or Write to Channel A Transmit Enable Pin (rwh) */
+ unsigned int TXENB:1; /**< \brief [21:21] Read or Write to Channel B Transmit Enable Pin (rwh) */
+ unsigned int reserved_22:2; /**< \brief \internal Reserved */
+ unsigned int CERA:4; /**< \brief [27:24] Coding Error Report Channel A (rh) */
+ unsigned int CERB:4; /**< \brief [31:28] Coding Error Report Channel B (rh) */
+} Ifx_ERAY_TEST1_Bits;
+
+/** \brief Test Register 2 */
+typedef struct _Ifx_ERAY_TEST2_Bits
+{
+ unsigned int RS:3; /**< \brief [2:0] RAM Select (rw) */
+ unsigned int reserved_3:1; /**< \brief \internal Reserved */
+ unsigned int SSEL:3; /**< \brief [6:4] Segment Select (rw) */
+ unsigned int reserved_7:7; /**< \brief \internal Reserved */
+ unsigned int WRECC:1; /**< \brief [14:14] Write ECC Data Enable (rw) */
+ unsigned int reserved_15:17; /**< \brief \internal Reserved */
+} Ifx_ERAY_TEST2_Bits;
+
+/** \brief Transmission Request Register 1 */
+typedef struct _Ifx_ERAY_TXRQ1_Bits
+{
+ unsigned int TXR0:1; /**< \brief [0:0] Transmission Request 0 (0 = 0-31) (rh) */
+ unsigned int TXR1:1; /**< \brief [1:1] Transmission Request 1 (1 = 0-31) (rh) */
+ unsigned int TXR2:1; /**< \brief [2:2] Transmission Request 2 (2 = 0-31) (rh) */
+ unsigned int TXR3:1; /**< \brief [3:3] Transmission Request 3 (3 = 0-31) (rh) */
+ unsigned int TXR4:1; /**< \brief [4:4] Transmission Request 4 (4 = 0-31) (rh) */
+ unsigned int TXR5:1; /**< \brief [5:5] Transmission Request 5 (5 = 0-31) (rh) */
+ unsigned int TXR6:1; /**< \brief [6:6] Transmission Request 6 (6 = 0-31) (rh) */
+ unsigned int TXR7:1; /**< \brief [7:7] Transmission Request 7 (7 = 0-31) (rh) */
+ unsigned int TXR8:1; /**< \brief [8:8] Transmission Request 8 (8 = 0-31) (rh) */
+ unsigned int TXR9:1; /**< \brief [9:9] Transmission Request 9 (9 = 0-31) (rh) */
+ unsigned int TXR10:1; /**< \brief [10:10] Transmission Request 10 (10 = 0-31) (rh) */
+ unsigned int TXR11:1; /**< \brief [11:11] Transmission Request 11 (11 = 0-31) (rh) */
+ unsigned int TXR12:1; /**< \brief [12:12] Transmission Request 12 (12 = 0-31) (rh) */
+ unsigned int TXR13:1; /**< \brief [13:13] Transmission Request 13 (13 = 0-31) (rh) */
+ unsigned int TXR14:1; /**< \brief [14:14] Transmission Request 14 (14 = 0-31) (rh) */
+ unsigned int TXR15:1; /**< \brief [15:15] Transmission Request 15 (15 = 0-31) (rh) */
+ unsigned int TXR16:1; /**< \brief [16:16] Transmission Request 16 (16 = 0-31) (rh) */
+ unsigned int TXR17:1; /**< \brief [17:17] Transmission Request 17 (17 = 0-31) (rh) */
+ unsigned int TXR18:1; /**< \brief [18:18] Transmission Request 18 (18 = 0-31) (rh) */
+ unsigned int TXR19:1; /**< \brief [19:19] Transmission Request 19 (19 = 0-31) (rh) */
+ unsigned int TXR20:1; /**< \brief [20:20] Transmission Request 20 (20 = 0-31) (rh) */
+ unsigned int TXR21:1; /**< \brief [21:21] Transmission Request 21 (21 = 0-31) (rh) */
+ unsigned int TXR22:1; /**< \brief [22:22] Transmission Request 22 (22 = 0-31) (rh) */
+ unsigned int TXR23:1; /**< \brief [23:23] Transmission Request 23 (23 = 0-31) (rh) */
+ unsigned int TXR24:1; /**< \brief [24:24] Transmission Request 24 (24 = 0-31) (rh) */
+ unsigned int TXR25:1; /**< \brief [25:25] Transmission Request 25 (25 = 0-31) (rh) */
+ unsigned int TXR26:1; /**< \brief [26:26] Transmission Request 26 (26 = 0-31) (rh) */
+ unsigned int TXR27:1; /**< \brief [27:27] Transmission Request 27 (27 = 0-31) (rh) */
+ unsigned int TXR28:1; /**< \brief [28:28] Transmission Request 28 (28 = 0-31) (rh) */
+ unsigned int TXR29:1; /**< \brief [29:29] Transmission Request 29 (29 = 0-31) (rh) */
+ unsigned int TXR30:1; /**< \brief [30:30] Transmission Request 30 (30 = 0-31) (rh) */
+ unsigned int TXR31:1; /**< \brief [31:31] Transmission Request 31 (31 = 0-31) (rh) */
+} Ifx_ERAY_TXRQ1_Bits;
+
+/** \brief Transmission Request Register 2 */
+typedef struct _Ifx_ERAY_TXRQ2_Bits
+{
+ unsigned int TXR32:1; /**< \brief [0:0] Transmission Request 32 (32 = 32-63) (rh) */
+ unsigned int TXR33:1; /**< \brief [1:1] Transmission Request 33 (33 = 32-63) (rh) */
+ unsigned int TXR34:1; /**< \brief [2:2] Transmission Request 34 (34 = 32-63) (rh) */
+ unsigned int TXR35:1; /**< \brief [3:3] Transmission Request 35 (35 = 32-63) (rh) */
+ unsigned int TXR36:1; /**< \brief [4:4] Transmission Request 36 (36 = 32-63) (rh) */
+ unsigned int TXR37:1; /**< \brief [5:5] Transmission Request 37 (37 = 32-63) (rh) */
+ unsigned int TXR38:1; /**< \brief [6:6] Transmission Request 38 (38 = 32-63) (rh) */
+ unsigned int TXR39:1; /**< \brief [7:7] Transmission Request 39 (39 = 32-63) (rh) */
+ unsigned int TXR40:1; /**< \brief [8:8] Transmission Request 40 (40 = 32-63) (rh) */
+ unsigned int TXR41:1; /**< \brief [9:9] Transmission Request 41 (41 = 32-63) (rh) */
+ unsigned int TXR42:1; /**< \brief [10:10] Transmission Request 42 (42 = 32-63) (rh) */
+ unsigned int TXR43:1; /**< \brief [11:11] Transmission Request 43 (43 = 32-63) (rh) */
+ unsigned int TXR44:1; /**< \brief [12:12] Transmission Request 44 (44 = 32-63) (rh) */
+ unsigned int TXR45:1; /**< \brief [13:13] Transmission Request 45 (45 = 32-63) (rh) */
+ unsigned int TXR46:1; /**< \brief [14:14] Transmission Request 46 (46 = 32-63) (rh) */
+ unsigned int TXR47:1; /**< \brief [15:15] Transmission Request 47 (47 = 32-63) (rh) */
+ unsigned int TXR48:1; /**< \brief [16:16] Transmission Request 48 (48 = 32-63) (rh) */
+ unsigned int TXR49:1; /**< \brief [17:17] Transmission Request 49 (49 = 32-63) (rh) */
+ unsigned int TXR50:1; /**< \brief [18:18] Transmission Request 50 (50 = 32-63) (rh) */
+ unsigned int TXR51:1; /**< \brief [19:19] Transmission Request 51 (51 = 32-63) (rh) */
+ unsigned int TXR52:1; /**< \brief [20:20] Transmission Request 52 (52 = 32-63) (rh) */
+ unsigned int TXR53:1; /**< \brief [21:21] Transmission Request 53 (53 = 32-63) (rh) */
+ unsigned int TXR54:1; /**< \brief [22:22] Transmission Request 54 (54 = 32-63) (rh) */
+ unsigned int TXR55:1; /**< \brief [23:23] Transmission Request 55 (55 = 32-63) (rh) */
+ unsigned int TXR56:1; /**< \brief [24:24] Transmission Request 56 (56 = 32-63) (rh) */
+ unsigned int TXR57:1; /**< \brief [25:25] Transmission Request 57 (57 = 32-63) (rh) */
+ unsigned int TXR58:1; /**< \brief [26:26] Transmission Request 58 (58 = 32-63) (rh) */
+ unsigned int TXR59:1; /**< \brief [27:27] Transmission Request 59 (59 = 32-63) (rh) */
+ unsigned int TXR60:1; /**< \brief [28:28] Transmission Request 60 (60 = 32-63) (rh) */
+ unsigned int TXR61:1; /**< \brief [29:29] Transmission Request 61 (61 = 32-63) (rh) */
+ unsigned int TXR62:1; /**< \brief [30:30] Transmission Request 62 (62 = 32-63) (rh) */
+ unsigned int TXR63:1; /**< \brief [31:31] Transmission Request 63 (63 = 32-63) (rh) */
+} Ifx_ERAY_TXRQ2_Bits;
+
+/** \brief Transmission Request Register 3 */
+typedef struct _Ifx_ERAY_TXRQ3_Bits
+{
+ unsigned int TXR64:1; /**< \brief [0:0] Transmission Request 64 (64 = 64-95) (rh) */
+ unsigned int TXR65:1; /**< \brief [1:1] Transmission Request 65 (65 = 64-95) (rh) */
+ unsigned int TXR66:1; /**< \brief [2:2] Transmission Request 66 (66 = 64-95) (rh) */
+ unsigned int TXR67:1; /**< \brief [3:3] Transmission Request 67 (67 = 64-95) (rh) */
+ unsigned int TXR68:1; /**< \brief [4:4] Transmission Request 68 (68 = 64-95) (rh) */
+ unsigned int TXR69:1; /**< \brief [5:5] Transmission Request 69 (69 = 64-95) (rh) */
+ unsigned int TXR70:1; /**< \brief [6:6] Transmission Request 70 (70 = 64-95) (rh) */
+ unsigned int TXR71:1; /**< \brief [7:7] Transmission Request 71 (71 = 64-95) (rh) */
+ unsigned int TXR72:1; /**< \brief [8:8] Transmission Request 72 (72 = 64-95) (rh) */
+ unsigned int TXR73:1; /**< \brief [9:9] Transmission Request 73 (73 = 64-95) (rh) */
+ unsigned int TXR74:1; /**< \brief [10:10] Transmission Request 74 (74 = 64-95) (rh) */
+ unsigned int TXR75:1; /**< \brief [11:11] Transmission Request 75 (75 = 64-95) (rh) */
+ unsigned int TXR76:1; /**< \brief [12:12] Transmission Request 76 (76 = 64-95) (rh) */
+ unsigned int TXR77:1; /**< \brief [13:13] Transmission Request 77 (77 = 64-95) (rh) */
+ unsigned int TXR78:1; /**< \brief [14:14] Transmission Request 78 (78 = 64-95) (rh) */
+ unsigned int TXR79:1; /**< \brief [15:15] Transmission Request 79 (79 = 64-95) (rh) */
+ unsigned int TXR80:1; /**< \brief [16:16] Transmission Request 80 (80 = 64-95) (rh) */
+ unsigned int TXR81:1; /**< \brief [17:17] Transmission Request 81 (81 = 64-95) (rh) */
+ unsigned int TXR82:1; /**< \brief [18:18] Transmission Request 82 (82 = 64-95) (rh) */
+ unsigned int TXR83:1; /**< \brief [19:19] Transmission Request 83 (83 = 64-95) (rh) */
+ unsigned int TXR84:1; /**< \brief [20:20] Transmission Request 84 (84 = 64-95) (rh) */
+ unsigned int TXR85:1; /**< \brief [21:21] Transmission Request 85 (85 = 64-95) (rh) */
+ unsigned int TXR86:1; /**< \brief [22:22] Transmission Request 86 (86 = 64-95) (rh) */
+ unsigned int TXR87:1; /**< \brief [23:23] Transmission Request 87 (87 = 64-95) (rh) */
+ unsigned int TXR88:1; /**< \brief [24:24] Transmission Request 88 (88 = 64-95) (rh) */
+ unsigned int TXR89:1; /**< \brief [25:25] Transmission Request 89 (89 = 64-95) (rh) */
+ unsigned int TXR90:1; /**< \brief [26:26] Transmission Request 90 (90 = 64-95) (rh) */
+ unsigned int TXR91:1; /**< \brief [27:27] Transmission Request 91 (91 = 64-95) (rh) */
+ unsigned int TXR92:1; /**< \brief [28:28] Transmission Request 92 (92 = 64-95) (rh) */
+ unsigned int TXR93:1; /**< \brief [29:29] Transmission Request 93 (93 = 64-95) (rh) */
+ unsigned int TXR94:1; /**< \brief [30:30] Transmission Request 94 (94 = 64-95) (rh) */
+ unsigned int TXR95:1; /**< \brief [31:31] Transmission Request 95 (95 = 64-95) (rh) */
+} Ifx_ERAY_TXRQ3_Bits;
+
+/** \brief Transmission Request Register 4 */
+typedef struct _Ifx_ERAY_TXRQ4_Bits
+{
+ unsigned int TXR96:1; /**< \brief [0:0] Transmission Request 96 (96 = 96-127) (rh) */
+ unsigned int TXR97:1; /**< \brief [1:1] Transmission Request 97 (97 = 96-127) (rh) */
+ unsigned int TXR98:1; /**< \brief [2:2] Transmission Request 98 (98 = 96-127) (rh) */
+ unsigned int TXR99:1; /**< \brief [3:3] Transmission Request 99 (99 = 96-127) (rh) */
+ unsigned int TXR100:1; /**< \brief [4:4] Transmission Request 100 (100 = 96-127) (rh) */
+ unsigned int TXR101:1; /**< \brief [5:5] Transmission Request 101 (101 = 96-127) (rh) */
+ unsigned int TXR102:1; /**< \brief [6:6] Transmission Request 102 (102 = 96-127) (rh) */
+ unsigned int TXR103:1; /**< \brief [7:7] Transmission Request 103 (103 = 96-127) (rh) */
+ unsigned int TXR104:1; /**< \brief [8:8] Transmission Request 104 (104 = 96-127) (rh) */
+ unsigned int TXR105:1; /**< \brief [9:9] Transmission Request 105 (105 = 96-127) (rh) */
+ unsigned int TXR106:1; /**< \brief [10:10] Transmission Request 106 (106 = 96-127) (rh) */
+ unsigned int TXR107:1; /**< \brief [11:11] Transmission Request 107 (107 = 96-127) (rh) */
+ unsigned int TXR108:1; /**< \brief [12:12] Transmission Request 108 (108 = 96-127) (rh) */
+ unsigned int TXR109:1; /**< \brief [13:13] Transmission Request 109 (109 = 96-127) (rh) */
+ unsigned int TXR110:1; /**< \brief [14:14] Transmission Request 110 (110 = 96-127) (rh) */
+ unsigned int TXR111:1; /**< \brief [15:15] Transmission Request 111 (111 = 96-127) (rh) */
+ unsigned int TXR112:1; /**< \brief [16:16] Transmission Request 112 (112 = 96-127) (rh) */
+ unsigned int TXR113:1; /**< \brief [17:17] Transmission Request 113 (113 = 96-127) (rh) */
+ unsigned int TXR114:1; /**< \brief [18:18] Transmission Request 114 (114 = 96-127) (rh) */
+ unsigned int TXR115:1; /**< \brief [19:19] Transmission Request 115 (115 = 96-127) (rh) */
+ unsigned int TXR116:1; /**< \brief [20:20] Transmission Request 116 (116 = 96-127) (rh) */
+ unsigned int TXR117:1; /**< \brief [21:21] Transmission Request 117 (117 = 96-127) (rh) */
+ unsigned int TXR118:1; /**< \brief [22:22] Transmission Request 118 (118 = 96-127) (rh) */
+ unsigned int TXR119:1; /**< \brief [23:23] Transmission Request 119 (119 = 96-127) (rh) */
+ unsigned int TXR120:1; /**< \brief [24:24] Transmission Request 120 (120 = 96-127) (rh) */
+ unsigned int TXR121:1; /**< \brief [25:25] Transmission Request 121 (121 = 96-127) (rh) */
+ unsigned int TXR122:1; /**< \brief [26:26] Transmission Request 122 (122 = 96-127) (rh) */
+ unsigned int TXR123:1; /**< \brief [27:27] Transmission Request 123 (123 = 96-127) (rh) */
+ unsigned int TXR124:1; /**< \brief [28:28] Transmission Request 124 (124 = 96-127) (rh) */
+ unsigned int TXR125:1; /**< \brief [29:29] Transmission Request 125 (125 = 96-127) (rh) */
+ unsigned int TXR126:1; /**< \brief [30:30] Transmission Request 126 (126 = 96-127) (rh) */
+ unsigned int TXR127:1; /**< \brief [31:31] Transmission Request 127 (127 = 96-127) (rh) */
+} Ifx_ERAY_TXRQ4_Bits;
+
+/** \brief Write Data Section */
+typedef struct _Ifx_ERAY_WRDS_Bits
+{
+ unsigned int MDWB0:8; /**< \brief [7:0] 32-Bit Word nn, Byte 0 (rw) */
+ unsigned int MDWB1:8; /**< \brief [15:8] 32-Bit Word nn, Byte 1 (rw) */
+ unsigned int MDWB2:8; /**< \brief [23:16] 32-Bit Word nn, Byte 2 (rw) */
+ unsigned int MDWB3:8; /**< \brief [31:24] 32-Bit Word nn, Byte 3 (rw) */
+} Ifx_ERAY_WRDS_Bits;
+
+/** \brief Write Header Section 1 */
+typedef struct _Ifx_ERAY_WRHS1_Bits
+{
+ unsigned int FID:11; /**< \brief [10:0] Frame ID (rw) */
+ unsigned int reserved_11:5; /**< \brief \internal Reserved */
+ unsigned int CYC:7; /**< \brief [22:16] Cycle Code (rw) */
+ unsigned int reserved_23:1; /**< \brief \internal Reserved */
+ unsigned int CHA:1; /**< \brief [24:24] Channel Filter Control A (rw) */
+ unsigned int CHB:1; /**< \brief [25:25] Channel Filter Control B (rw) */
+ unsigned int CFG:1; /**< \brief [26:26] Message Buffer Direction Configuration Bit (rw) */
+ unsigned int PPIT:1; /**< \brief [27:27] Payload Preamble Indicator Transmit (rw) */
+ unsigned int TXM:1; /**< \brief [28:28] Transmission Mode (rw) */
+ unsigned int MBI:1; /**< \brief [29:29] Message Buffer Service Request (rw) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_ERAY_WRHS1_Bits;
+
+/** \brief Write Header Section 2 */
+typedef struct _Ifx_ERAY_WRHS2_Bits
+{
+ unsigned int CRC:11; /**< \brief [10:0] Header CRC (vRF!Header!HeaderCRC) (rw) */
+ unsigned int reserved_11:5; /**< \brief \internal Reserved */
+ unsigned int PLC:7; /**< \brief [22:16] Payload Length Configured (rw) */
+ unsigned int reserved_23:9; /**< \brief \internal Reserved */
+} Ifx_ERAY_WRHS2_Bits;
+
+/** \brief Write Header Section 3 */
+typedef struct _Ifx_ERAY_WRHS3_Bits
+{
+ unsigned int DP:11; /**< \brief [10:0] Data Pointer (rw) */
+ unsigned int reserved_11:21; /**< \brief \internal Reserved */
+} Ifx_ERAY_WRHS3_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Eray_union
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_ACCEN0_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_ACCEN0;
+
+/** \brief Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_ACCEN1_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_ACCEN1;
+
+/** \brief Aggregated Channel Status */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_ACS_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_ACS;
+
+/** \brief Communication Controller Error Vector */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_CCEV_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_CCEV;
+
+/** \brief Communication Controller Status Vector */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_CCSV_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_CCSV;
+
+/** \brief Clock Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_CLC_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_CLC;
+
+/** \brief Core Release Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_CREL_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_CREL;
+
+/** \brief Busy and Input Buffer Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_CUST1_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_CUST1;
+
+/** \brief Customer Interface Timeout Counter */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_CUST3_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_CUST3;
+
+/** \brief Error Service Request Enable Reset */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_EIER_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_EIER;
+
+/** \brief Error Service Request Enable Set */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_EIES_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_EIES;
+
+/** \brief Error Service Request Line Select */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_EILS_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_EILS;
+
+/** \brief Error Service Request Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_EIR_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_EIR;
+
+/** \brief Endian Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_ENDN_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_ENDN;
+
+/** \brief Even Sync ID Symbol Window */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_ESID_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_ESID;
+
+/** \brief FIFO Critical Level */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_FCL_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_FCL;
+
+/** \brief FIFO Rejection Filter */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_FRF_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_FRF;
+
+/** \brief FIFO Rejection Filter Mask */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_FRFM_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_FRFM;
+
+/** \brief FIFO Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_FSR_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_FSR;
+
+/** \brief GTU Configuration Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_GTUC01_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_GTUC01;
+
+/** \brief GTU Configuration Register 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_GTUC02_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_GTUC02;
+
+/** \brief GTU Configuration Register 3 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_GTUC03_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_GTUC03;
+
+/** \brief GTU Configuration Register 4 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_GTUC04_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_GTUC04;
+
+/** \brief GTU Configuration Register 5 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_GTUC05_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_GTUC05;
+
+/** \brief GTU Configuration Register 6 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_GTUC06_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_GTUC06;
+
+/** \brief GTU Configuration Register 7 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_GTUC07_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_GTUC07;
+
+/** \brief GTU Configuration Register 8 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_GTUC08_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_GTUC08;
+
+/** \brief GTU Configuration Register 9 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_GTUC09_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_GTUC09;
+
+/** \brief GTU Configuration Register 10 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_GTUC10_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_GTUC10;
+
+/** \brief GTU Configuration Register 11 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_GTUC11_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_GTUC11;
+
+/** \brief Input Buffer Command Mask */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_IBCM_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_IBCM;
+
+/** \brief Input Buffer Command Request */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_IBCR_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_IBCR;
+
+/** \brief Module Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_ID;
+
+/** \brief Service Request Line Enable */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_ILE_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_ILE;
+
+/** \brief Kernel Reset Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_KRST0_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_KRST0;
+
+/** \brief Kernel Reset Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_KRST1_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_KRST1;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_KRSTCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_KRSTCLR;
+
+/** \brief Lock Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_LCK_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_LCK;
+
+/** \brief Last Dynamic Transmit Slot */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_LDTS_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_LDTS;
+
+/** \brief Message Buffer Status */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_MBS_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_MBS;
+
+/** \brief Message Buffer Status Changed 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_MBSC1_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_MBSC1;
+
+/** \brief Message Buffer Status Changed 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_MBSC2_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_MBSC2;
+
+/** \brief Message Buffer Status Changed 3 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_MBSC3_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_MBSC3;
+
+/** \brief Message Buffer Status Changed 4 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_MBSC4_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_MBSC4;
+
+/** \brief MHD Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_MHDC_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_MHDC;
+
+/** \brief Message Handler Constraints Flags */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_MHDF_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_MHDF;
+
+/** \brief Message Handler Status */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_MHDS_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_MHDS;
+
+/** \brief Message RAM Configuration */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_MRC_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_MRC;
+
+/** \brief Message Buffer Status Changed Interrupt Control 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_MSIC1_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_MSIC1;
+
+/** \brief Message Buffer Status Changed Interrupt Control 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_MSIC2_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_MSIC2;
+
+/** \brief Message Buffer Status Changed Interrupt Control 3 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_MSIC3_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_MSIC3;
+
+/** \brief Message Buffer Status Changed Interrupt Control 4 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_MSIC4_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_MSIC4;
+
+/** \brief Macrotick and Cycle Counter Value */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_MTCCV_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_MTCCV;
+
+/** \brief New Data Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_NDAT1_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_NDAT1;
+
+/** \brief New Data Register 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_NDAT2_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_NDAT2;
+
+/** \brief New Data Register 3 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_NDAT3_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_NDAT3;
+
+/** \brief New Data Register 4 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_NDAT4_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_NDAT4;
+
+/** \brief New Data Interrupt Control 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_NDIC1_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_NDIC1;
+
+/** \brief New Data Interrupt Control 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_NDIC2_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_NDIC2;
+
+/** \brief New Data Interrupt Control 3 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_NDIC3_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_NDIC3;
+
+/** \brief New Data Interrupt Control 4 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_NDIC4_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_NDIC4;
+
+/** \brief NEM Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_NEMC_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_NEMC;
+
+/** \brief Network Management Vector */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_NMV_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_NMV;
+
+/** \brief Output Buffer Command Mask */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_OBCM_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_OBCM;
+
+/** \brief Output Buffer Command Request */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_OBCR_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_OBCR;
+
+/** \brief OCDS Control and Status */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_OCS_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_OCS;
+
+/** \brief Offset Correction Value */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_OCV_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_OCV;
+
+/** \brief Odd Sync ID Symbol Window */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_OSID_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_OSID;
+
+/** \brief OCDS Trigger Set Select */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_OTSS_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_OTSS;
+
+/** \brief PRT Configuration Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_PRTC1_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_PRTC1;
+
+/** \brief PRT Configuration Register 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_PRTC2_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_PRTC2;
+
+/** \brief Rate Correction Value */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_RCV_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_RCV;
+
+/** \brief Read Data Section */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_RDDS_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_RDDS;
+
+/** \brief Read Header Section 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_RDHS1_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_RDHS1;
+
+/** \brief Read Header Section 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_RDHS2_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_RDHS2;
+
+/** \brief Read Header Section 3 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_RDHS3_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_RDHS3;
+
+/** \brief Slot Counter Value */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_SCV_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_SCV;
+
+/** \brief SYNC Frame Status */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_SFS_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_SFS;
+
+/** \brief Status Service Request Enable Reset */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_SIER_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_SIER;
+
+/** \brief Status Service Request Enable Set */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_SIES_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_SIES;
+
+/** \brief Status Service Request Line Select */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_SILS_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_SILS;
+
+/** \brief Status Service Request Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_SIR_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_SIR;
+
+/** \brief Stop Watch Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_STPW1_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_STPW1;
+
+/** \brief Stop Watch Register 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_STPW2_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_STPW2;
+
+/** \brief SUC Configuration Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_SUCC1_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_SUCC1;
+
+/** \brief SUC Configuration Register 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_SUCC2_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_SUCC2;
+
+/** \brief SUC Configuration Register 3 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_SUCC3_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_SUCC3;
+
+/** \brief Symbol Window and Network Idle Time Status */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_SWNIT_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_SWNIT;
+
+/** \brief Timer 0 Configuration */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_T0C_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_T0C;
+
+/** \brief Timer 1 Configuration */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_T1C_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_T1C;
+
+/** \brief Test Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_TEST1_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_TEST1;
+
+/** \brief Test Register 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_TEST2_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_TEST2;
+
+/** \brief Transmission Request Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_TXRQ1_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_TXRQ1;
+
+/** \brief Transmission Request Register 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_TXRQ2_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_TXRQ2;
+
+/** \brief Transmission Request Register 3 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_TXRQ3_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_TXRQ3;
+
+/** \brief Transmission Request Register 4 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_TXRQ4_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_TXRQ4;
+
+/** \brief Write Data Section */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_WRDS_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_WRDS;
+
+/** \brief Write Header Section 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_WRHS1_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_WRHS1;
+
+/** \brief Write Header Section 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_WRHS2_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_WRHS2;
+
+/** \brief Write Header Section 3 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ERAY_WRHS3_Bits B; /**< \brief Bitfield access */
+} Ifx_ERAY_WRHS3;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Eray_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief ERAY object */
+typedef volatile struct _Ifx_ERAY
+{
+ Ifx_ERAY_CLC CLC; /**< \brief 0, Clock Control Register */
+ Ifx_ERAY_CUST1 CUST1; /**< \brief 4, Busy and Input Buffer Control Register */
+ Ifx_ERAY_ID ID; /**< \brief 8, Module Identification Register */
+ Ifx_ERAY_CUST3 CUST3; /**< \brief C, Customer Interface Timeout Counter */
+ Ifx_ERAY_TEST1 TEST1; /**< \brief 10, Test Register 1 */
+ Ifx_ERAY_TEST2 TEST2; /**< \brief 14, Test Register 2 */
+ unsigned char reserved_18[4]; /**< \brief 18, \internal Reserved */
+ Ifx_ERAY_LCK LCK; /**< \brief 1C, Lock Register */
+ Ifx_ERAY_EIR EIR; /**< \brief 20, Error Service Request Register */
+ Ifx_ERAY_SIR SIR; /**< \brief 24, Status Service Request Register */
+ Ifx_ERAY_EILS EILS; /**< \brief 28, Error Service Request Line Select */
+ Ifx_ERAY_SILS SILS; /**< \brief 2C, Status Service Request Line Select */
+ Ifx_ERAY_EIES EIES; /**< \brief 30, Error Service Request Enable Set */
+ Ifx_ERAY_EIER EIER; /**< \brief 34, Error Service Request Enable Reset */
+ Ifx_ERAY_SIES SIES; /**< \brief 38, Status Service Request Enable Set */
+ Ifx_ERAY_SIER SIER; /**< \brief 3C, Status Service Request Enable Reset */
+ Ifx_ERAY_ILE ILE; /**< \brief 40, Service Request Line Enable */
+ Ifx_ERAY_T0C T0C; /**< \brief 44, Timer 0 Configuration */
+ Ifx_ERAY_T1C T1C; /**< \brief 48, Timer 1 Configuration */
+ Ifx_ERAY_STPW1 STPW1; /**< \brief 4C, Stop Watch Register 1 */
+ Ifx_ERAY_STPW2 STPW2; /**< \brief 50, Stop Watch Register 2 */
+ unsigned char reserved_54[44]; /**< \brief 54, \internal Reserved */
+ Ifx_ERAY_SUCC1 SUCC1; /**< \brief 80, SUC Configuration Register 1 */
+ Ifx_ERAY_SUCC2 SUCC2; /**< \brief 84, SUC Configuration Register 2 */
+ Ifx_ERAY_SUCC3 SUCC3; /**< \brief 88, SUC Configuration Register 3 */
+ Ifx_ERAY_NEMC NEMC; /**< \brief 8C, NEM Configuration Register */
+ Ifx_ERAY_PRTC1 PRTC1; /**< \brief 90, PRT Configuration Register 1 */
+ Ifx_ERAY_PRTC2 PRTC2; /**< \brief 94, PRT Configuration Register 2 */
+ Ifx_ERAY_MHDC MHDC; /**< \brief 98, MHD Configuration Register */
+ unsigned char reserved_9C[4]; /**< \brief 9C, \internal Reserved */
+ Ifx_ERAY_GTUC01 GTUC01; /**< \brief A0, GTU Configuration Register 1 */
+ Ifx_ERAY_GTUC02 GTUC02; /**< \brief A4, GTU Configuration Register 2 */
+ Ifx_ERAY_GTUC03 GTUC03; /**< \brief A8, GTU Configuration Register 3 */
+ Ifx_ERAY_GTUC04 GTUC04; /**< \brief AC, GTU Configuration Register 4 */
+ Ifx_ERAY_GTUC05 GTUC05; /**< \brief B0, GTU Configuration Register 5 */
+ Ifx_ERAY_GTUC06 GTUC06; /**< \brief B4, GTU Configuration Register 6 */
+ Ifx_ERAY_GTUC07 GTUC07; /**< \brief B8, GTU Configuration Register 7 */
+ Ifx_ERAY_GTUC08 GTUC08; /**< \brief BC, GTU Configuration Register 8 */
+ Ifx_ERAY_GTUC09 GTUC09; /**< \brief C0, GTU Configuration Register 9 */
+ Ifx_ERAY_GTUC10 GTUC10; /**< \brief C4, GTU Configuration Register 10 */
+ Ifx_ERAY_GTUC11 GTUC11; /**< \brief C8, GTU Configuration Register 11 */
+ unsigned char reserved_CC[52]; /**< \brief CC, \internal Reserved */
+ Ifx_ERAY_CCSV CCSV; /**< \brief 100, Communication Controller Status Vector */
+ Ifx_ERAY_CCEV CCEV; /**< \brief 104, Communication Controller Error Vector */
+ unsigned char reserved_108[8]; /**< \brief 108, \internal Reserved */
+ Ifx_ERAY_SCV SCV; /**< \brief 110, Slot Counter Value */
+ Ifx_ERAY_MTCCV MTCCV; /**< \brief 114, Macrotick and Cycle Counter Value */
+ Ifx_ERAY_RCV RCV; /**< \brief 118, Rate Correction Value */
+ Ifx_ERAY_OCV OCV; /**< \brief 11C, Offset Correction Value */
+ Ifx_ERAY_SFS SFS; /**< \brief 120, SYNC Frame Status */
+ Ifx_ERAY_SWNIT SWNIT; /**< \brief 124, Symbol Window and Network Idle Time Status */
+ Ifx_ERAY_ACS ACS; /**< \brief 128, Aggregated Channel Status */
+ unsigned char reserved_12C[4]; /**< \brief 12C, \internal Reserved */
+ Ifx_ERAY_ESID ESID_1S[15]; /**< \brief 130, Even Sync ID Symbol Window \note Array index shifted by 1. Example: defined register ESID_1S[0]/ESID_1S0 corresponds to user manual ESID_1S1, ... */
+ unsigned char reserved_16C[4]; /**< \brief 16C, \internal Reserved */
+ Ifx_ERAY_OSID OSID_1S[15]; /**< \brief 170, Odd Sync ID Symbol Window \note Array index shifted by 1. Example: defined register OSID_1S[0]/OSID_1S0 corresponds to user manual OSID_1S1, ... */
+ unsigned char reserved_1AC[4]; /**< \brief 1AC, \internal Reserved */
+ Ifx_ERAY_NMV NMV_1S[3]; /**< \brief 1B0, Network Management Vector \note Array index shifted by 1. Example: defined register NMV_1S[0]/NMV_1S0 corresponds to user manual NMV_1S1, ... */
+ unsigned char reserved_1BC[324]; /**< \brief 1BC, \internal Reserved */
+ Ifx_ERAY_MRC MRC; /**< \brief 300, Message RAM Configuration */
+ Ifx_ERAY_FRF FRF; /**< \brief 304, FIFO Rejection Filter */
+ Ifx_ERAY_FRFM FRFM; /**< \brief 308, FIFO Rejection Filter Mask */
+ Ifx_ERAY_FCL FCL; /**< \brief 30C, FIFO Critical Level */
+ Ifx_ERAY_MHDS MHDS; /**< \brief 310, Message Handler Status */
+ Ifx_ERAY_LDTS LDTS; /**< \brief 314, Last Dynamic Transmit Slot */
+ Ifx_ERAY_FSR FSR; /**< \brief 318, FIFO Status Register */
+ Ifx_ERAY_MHDF MHDF; /**< \brief 31C, Message Handler Constraints Flags */
+ Ifx_ERAY_TXRQ1 TXRQ1; /**< \brief 320, Transmission Request Register 1 */
+ Ifx_ERAY_TXRQ2 TXRQ2; /**< \brief 324, Transmission Request Register 2 */
+ Ifx_ERAY_TXRQ3 TXRQ3; /**< \brief 328, Transmission Request Register 3 */
+ Ifx_ERAY_TXRQ4 TXRQ4; /**< \brief 32C, Transmission Request Register 4 */
+ Ifx_ERAY_NDAT1 NDAT1; /**< \brief 330, New Data Register 1 */
+ Ifx_ERAY_NDAT2 NDAT2; /**< \brief 334, New Data Register 2 */
+ Ifx_ERAY_NDAT3 NDAT3; /**< \brief 338, New Data Register 3 */
+ Ifx_ERAY_NDAT4 NDAT4; /**< \brief 33C, New Data Register 4 */
+ Ifx_ERAY_MBSC1 MBSC1; /**< \brief 340, Message Buffer Status Changed 1 */
+ Ifx_ERAY_MBSC2 MBSC2; /**< \brief 344, Message Buffer Status Changed 2 */
+ Ifx_ERAY_MBSC3 MBSC3; /**< \brief 348, Message Buffer Status Changed 3 */
+ Ifx_ERAY_MBSC4 MBSC4; /**< \brief 34C, Message Buffer Status Changed 4 */
+ unsigned char reserved_350[88]; /**< \brief 350, \internal Reserved */
+ Ifx_ERAY_NDIC1 NDIC1; /**< \brief 3A8, New Data Interrupt Control 1 */
+ Ifx_ERAY_NDIC2 NDIC2; /**< \brief 3AC, New Data Interrupt Control 2 */
+ Ifx_ERAY_NDIC3 NDIC3; /**< \brief 3B0, New Data Interrupt Control 3 */
+ Ifx_ERAY_NDIC4 NDIC4; /**< \brief 3B4, New Data Interrupt Control 4 */
+ Ifx_ERAY_MSIC1 MSIC1; /**< \brief 3B8, Message Buffer Status Changed Interrupt Control 1 */
+ Ifx_ERAY_MSIC2 MSIC2; /**< \brief 3BC, Message Buffer Status Changed Interrupt Control 2 */
+ Ifx_ERAY_MSIC3 MSIC3; /**< \brief 3C0, Message Buffer Status Changed Interrupt Control 3 */
+ Ifx_ERAY_MSIC4 MSIC4; /**< \brief 3C4, Message Buffer Status Changed Interrupt Control 4 */
+ unsigned char reserved_3C8[40]; /**< \brief 3C8, \internal Reserved */
+ Ifx_ERAY_CREL CREL; /**< \brief 3F0, Core Release Register */
+ Ifx_ERAY_ENDN ENDN; /**< \brief 3F4, Endian Register */
+ unsigned char reserved_3F8[8]; /**< \brief 3F8, \internal Reserved */
+ Ifx_ERAY_WRDS WRDS_1S[64]; /**< \brief 400, Write Data Section \note Array index shifted by 1. Example: defined register WRDS_1S[0]/WRDS_1S0 corresponds to user manual WRDS_1S1, ... */
+ Ifx_ERAY_WRHS1 WRHS1; /**< \brief 500, Write Header Section 1 */
+ Ifx_ERAY_WRHS2 WRHS2; /**< \brief 504, Write Header Section 2 */
+ Ifx_ERAY_WRHS3 WRHS3; /**< \brief 508, Write Header Section 3 */
+ unsigned char reserved_50C[4]; /**< \brief 50C, \internal Reserved */
+ Ifx_ERAY_IBCM IBCM; /**< \brief 510, Input Buffer Command Mask */
+ Ifx_ERAY_IBCR IBCR; /**< \brief 514, Input Buffer Command Request */
+ unsigned char reserved_518[232]; /**< \brief 518, \internal Reserved */
+ Ifx_ERAY_RDDS RDDS_1S[64]; /**< \brief 600, Read Data Section \note Array index shifted by 1. Example: defined register RDDS_1S[0]/RDDS_1S0 corresponds to user manual RDDS_1S1, ... */
+ Ifx_ERAY_RDHS1 RDHS1; /**< \brief 700, Read Header Section 1 */
+ Ifx_ERAY_RDHS2 RDHS2; /**< \brief 704, Read Header Section 2 */
+ Ifx_ERAY_RDHS3 RDHS3; /**< \brief 708, Read Header Section 3 */
+ Ifx_ERAY_MBS MBS; /**< \brief 70C, Message Buffer Status */
+ Ifx_ERAY_OBCM OBCM; /**< \brief 710, Output Buffer Command Mask */
+ Ifx_ERAY_OBCR OBCR; /**< \brief 714, Output Buffer Command Request */
+ unsigned char reserved_718[344]; /**< \brief 718, \internal Reserved */
+ Ifx_ERAY_OTSS OTSS; /**< \brief 870, OCDS Trigger Set Select */
+ unsigned char reserved_874[116]; /**< \brief 874, \internal Reserved */
+ Ifx_ERAY_OCS OCS; /**< \brief 8E8, OCDS Control and Status */
+ Ifx_ERAY_KRSTCLR KRSTCLR; /**< \brief 8EC, Kernel Reset Status Clear Register */
+ Ifx_ERAY_KRST1 KRST1; /**< \brief 8F0, Kernel Reset Register 1 */
+ Ifx_ERAY_KRST0 KRST0; /**< \brief 8F4, Kernel Reset Register 0 */
+ Ifx_ERAY_ACCEN1 ACCEN1; /**< \brief 8F8, Access Enable Register 1 */
+ Ifx_ERAY_ACCEN0 ACCEN0; /**< \brief 8FC, Access Enable Register 0 */
+ unsigned char reserved_900[1792]; /**< \brief 900, \internal Reserved */
+} Ifx_ERAY;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXERAY_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEth_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEth_bf.h
new file mode 100644
index 0000000..1d18055
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEth_bf.h
@@ -0,0 +1,5224 @@
+/**
+ * \file IfxEth_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Eth_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Eth
+ *
+ */
+#ifndef IFXETH_BF_H
+#define IFXETH_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Eth_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN0 */
+#define IFX_ETH_ACCEN0_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN0 */
+#define IFX_ETH_ACCEN0_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN0 */
+#define IFX_ETH_ACCEN0_EN0_OFF (0u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN10 */
+#define IFX_ETH_ACCEN0_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN10 */
+#define IFX_ETH_ACCEN0_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN10 */
+#define IFX_ETH_ACCEN0_EN10_OFF (10u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN11 */
+#define IFX_ETH_ACCEN0_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN11 */
+#define IFX_ETH_ACCEN0_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN11 */
+#define IFX_ETH_ACCEN0_EN11_OFF (11u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN12 */
+#define IFX_ETH_ACCEN0_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN12 */
+#define IFX_ETH_ACCEN0_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN12 */
+#define IFX_ETH_ACCEN0_EN12_OFF (12u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN13 */
+#define IFX_ETH_ACCEN0_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN13 */
+#define IFX_ETH_ACCEN0_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN13 */
+#define IFX_ETH_ACCEN0_EN13_OFF (13u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN14 */
+#define IFX_ETH_ACCEN0_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN14 */
+#define IFX_ETH_ACCEN0_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN14 */
+#define IFX_ETH_ACCEN0_EN14_OFF (14u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN15 */
+#define IFX_ETH_ACCEN0_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN15 */
+#define IFX_ETH_ACCEN0_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN15 */
+#define IFX_ETH_ACCEN0_EN15_OFF (15u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN16 */
+#define IFX_ETH_ACCEN0_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN16 */
+#define IFX_ETH_ACCEN0_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN16 */
+#define IFX_ETH_ACCEN0_EN16_OFF (16u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN17 */
+#define IFX_ETH_ACCEN0_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN17 */
+#define IFX_ETH_ACCEN0_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN17 */
+#define IFX_ETH_ACCEN0_EN17_OFF (17u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN18 */
+#define IFX_ETH_ACCEN0_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN18 */
+#define IFX_ETH_ACCEN0_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN18 */
+#define IFX_ETH_ACCEN0_EN18_OFF (18u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN19 */
+#define IFX_ETH_ACCEN0_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN19 */
+#define IFX_ETH_ACCEN0_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN19 */
+#define IFX_ETH_ACCEN0_EN19_OFF (19u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN1 */
+#define IFX_ETH_ACCEN0_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN1 */
+#define IFX_ETH_ACCEN0_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN1 */
+#define IFX_ETH_ACCEN0_EN1_OFF (1u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN20 */
+#define IFX_ETH_ACCEN0_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN20 */
+#define IFX_ETH_ACCEN0_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN20 */
+#define IFX_ETH_ACCEN0_EN20_OFF (20u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN21 */
+#define IFX_ETH_ACCEN0_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN21 */
+#define IFX_ETH_ACCEN0_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN21 */
+#define IFX_ETH_ACCEN0_EN21_OFF (21u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN22 */
+#define IFX_ETH_ACCEN0_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN22 */
+#define IFX_ETH_ACCEN0_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN22 */
+#define IFX_ETH_ACCEN0_EN22_OFF (22u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN23 */
+#define IFX_ETH_ACCEN0_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN23 */
+#define IFX_ETH_ACCEN0_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN23 */
+#define IFX_ETH_ACCEN0_EN23_OFF (23u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN24 */
+#define IFX_ETH_ACCEN0_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN24 */
+#define IFX_ETH_ACCEN0_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN24 */
+#define IFX_ETH_ACCEN0_EN24_OFF (24u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN25 */
+#define IFX_ETH_ACCEN0_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN25 */
+#define IFX_ETH_ACCEN0_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN25 */
+#define IFX_ETH_ACCEN0_EN25_OFF (25u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN26 */
+#define IFX_ETH_ACCEN0_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN26 */
+#define IFX_ETH_ACCEN0_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN26 */
+#define IFX_ETH_ACCEN0_EN26_OFF (26u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN27 */
+#define IFX_ETH_ACCEN0_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN27 */
+#define IFX_ETH_ACCEN0_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN27 */
+#define IFX_ETH_ACCEN0_EN27_OFF (27u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN28 */
+#define IFX_ETH_ACCEN0_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN28 */
+#define IFX_ETH_ACCEN0_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN28 */
+#define IFX_ETH_ACCEN0_EN28_OFF (28u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN29 */
+#define IFX_ETH_ACCEN0_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN29 */
+#define IFX_ETH_ACCEN0_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN29 */
+#define IFX_ETH_ACCEN0_EN29_OFF (29u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN2 */
+#define IFX_ETH_ACCEN0_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN2 */
+#define IFX_ETH_ACCEN0_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN2 */
+#define IFX_ETH_ACCEN0_EN2_OFF (2u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN30 */
+#define IFX_ETH_ACCEN0_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN30 */
+#define IFX_ETH_ACCEN0_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN30 */
+#define IFX_ETH_ACCEN0_EN30_OFF (30u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN31 */
+#define IFX_ETH_ACCEN0_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN31 */
+#define IFX_ETH_ACCEN0_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN31 */
+#define IFX_ETH_ACCEN0_EN31_OFF (31u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN3 */
+#define IFX_ETH_ACCEN0_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN3 */
+#define IFX_ETH_ACCEN0_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN3 */
+#define IFX_ETH_ACCEN0_EN3_OFF (3u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN4 */
+#define IFX_ETH_ACCEN0_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN4 */
+#define IFX_ETH_ACCEN0_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN4 */
+#define IFX_ETH_ACCEN0_EN4_OFF (4u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN5 */
+#define IFX_ETH_ACCEN0_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN5 */
+#define IFX_ETH_ACCEN0_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN5 */
+#define IFX_ETH_ACCEN0_EN5_OFF (5u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN6 */
+#define IFX_ETH_ACCEN0_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN6 */
+#define IFX_ETH_ACCEN0_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN6 */
+#define IFX_ETH_ACCEN0_EN6_OFF (6u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN7 */
+#define IFX_ETH_ACCEN0_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN7 */
+#define IFX_ETH_ACCEN0_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN7 */
+#define IFX_ETH_ACCEN0_EN7_OFF (7u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN8 */
+#define IFX_ETH_ACCEN0_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN8 */
+#define IFX_ETH_ACCEN0_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN8 */
+#define IFX_ETH_ACCEN0_EN8_OFF (8u)
+
+/** \brief Length for Ifx_ETH_ACCEN0_Bits.EN9 */
+#define IFX_ETH_ACCEN0_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_ACCEN0_Bits.EN9 */
+#define IFX_ETH_ACCEN0_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_ACCEN0_Bits.EN9 */
+#define IFX_ETH_ACCEN0_EN9_OFF (9u)
+
+/** \brief Length for Ifx_ETH_AHB_OR_AXI_STATUS_Bits.AXIRDSTS */
+#define IFX_ETH_AHB_OR_AXI_STATUS_AXIRDSTS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_AHB_OR_AXI_STATUS_Bits.AXIRDSTS */
+#define IFX_ETH_AHB_OR_AXI_STATUS_AXIRDSTS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_AHB_OR_AXI_STATUS_Bits.AXIRDSTS */
+#define IFX_ETH_AHB_OR_AXI_STATUS_AXIRDSTS_OFF (1u)
+
+/** \brief Length for Ifx_ETH_AHB_OR_AXI_STATUS_Bits.AXWHSTS */
+#define IFX_ETH_AHB_OR_AXI_STATUS_AXWHSTS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_AHB_OR_AXI_STATUS_Bits.AXWHSTS */
+#define IFX_ETH_AHB_OR_AXI_STATUS_AXWHSTS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_AHB_OR_AXI_STATUS_Bits.AXWHSTS */
+#define IFX_ETH_AHB_OR_AXI_STATUS_AXWHSTS_OFF (0u)
+
+/** \brief Length for Ifx_ETH_BUS_MODE_Bits.AAL */
+#define IFX_ETH_BUS_MODE_AAL_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_BUS_MODE_Bits.AAL */
+#define IFX_ETH_BUS_MODE_AAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_BUS_MODE_Bits.AAL */
+#define IFX_ETH_BUS_MODE_AAL_OFF (25u)
+
+/** \brief Length for Ifx_ETH_BUS_MODE_Bits.ATDS */
+#define IFX_ETH_BUS_MODE_ATDS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_BUS_MODE_Bits.ATDS */
+#define IFX_ETH_BUS_MODE_ATDS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_BUS_MODE_Bits.ATDS */
+#define IFX_ETH_BUS_MODE_ATDS_OFF (7u)
+
+/** \brief Length for Ifx_ETH_BUS_MODE_Bits.DA */
+#define IFX_ETH_BUS_MODE_DA_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_BUS_MODE_Bits.DA */
+#define IFX_ETH_BUS_MODE_DA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_BUS_MODE_Bits.DA */
+#define IFX_ETH_BUS_MODE_DA_OFF (1u)
+
+/** \brief Length for Ifx_ETH_BUS_MODE_Bits.DSL */
+#define IFX_ETH_BUS_MODE_DSL_LEN (5u)
+
+/** \brief Mask for Ifx_ETH_BUS_MODE_Bits.DSL */
+#define IFX_ETH_BUS_MODE_DSL_MSK (0x1fu)
+
+/** \brief Offset for Ifx_ETH_BUS_MODE_Bits.DSL */
+#define IFX_ETH_BUS_MODE_DSL_OFF (2u)
+
+/** \brief Length for Ifx_ETH_BUS_MODE_Bits.FB */
+#define IFX_ETH_BUS_MODE_FB_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_BUS_MODE_Bits.FB */
+#define IFX_ETH_BUS_MODE_FB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_BUS_MODE_Bits.FB */
+#define IFX_ETH_BUS_MODE_FB_OFF (16u)
+
+/** \brief Length for Ifx_ETH_BUS_MODE_Bits.MB */
+#define IFX_ETH_BUS_MODE_MB_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_BUS_MODE_Bits.MB */
+#define IFX_ETH_BUS_MODE_MB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_BUS_MODE_Bits.MB */
+#define IFX_ETH_BUS_MODE_MB_OFF (26u)
+
+/** \brief Length for Ifx_ETH_BUS_MODE_Bits.PBL */
+#define IFX_ETH_BUS_MODE_PBL_LEN (6u)
+
+/** \brief Mask for Ifx_ETH_BUS_MODE_Bits.PBL */
+#define IFX_ETH_BUS_MODE_PBL_MSK (0x3fu)
+
+/** \brief Offset for Ifx_ETH_BUS_MODE_Bits.PBL */
+#define IFX_ETH_BUS_MODE_PBL_OFF (8u)
+
+/** \brief Length for Ifx_ETH_BUS_MODE_Bits.PBLx8 */
+#define IFX_ETH_BUS_MODE_PBLX8_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_BUS_MODE_Bits.PBLx8 */
+#define IFX_ETH_BUS_MODE_PBLX8_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_BUS_MODE_Bits.PBLx8 */
+#define IFX_ETH_BUS_MODE_PBLX8_OFF (24u)
+
+/** \brief Length for Ifx_ETH_BUS_MODE_Bits.PR */
+#define IFX_ETH_BUS_MODE_PR_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_BUS_MODE_Bits.PR */
+#define IFX_ETH_BUS_MODE_PR_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_BUS_MODE_Bits.PR */
+#define IFX_ETH_BUS_MODE_PR_OFF (14u)
+
+/** \brief Length for Ifx_ETH_BUS_MODE_Bits.PRWG */
+#define IFX_ETH_BUS_MODE_PRWG_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_BUS_MODE_Bits.PRWG */
+#define IFX_ETH_BUS_MODE_PRWG_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_BUS_MODE_Bits.PRWG */
+#define IFX_ETH_BUS_MODE_PRWG_OFF (28u)
+
+/** \brief Length for Ifx_ETH_BUS_MODE_Bits.RPBL */
+#define IFX_ETH_BUS_MODE_RPBL_LEN (6u)
+
+/** \brief Mask for Ifx_ETH_BUS_MODE_Bits.RPBL */
+#define IFX_ETH_BUS_MODE_RPBL_MSK (0x3fu)
+
+/** \brief Offset for Ifx_ETH_BUS_MODE_Bits.RPBL */
+#define IFX_ETH_BUS_MODE_RPBL_OFF (17u)
+
+/** \brief Length for Ifx_ETH_BUS_MODE_Bits.SWR */
+#define IFX_ETH_BUS_MODE_SWR_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_BUS_MODE_Bits.SWR */
+#define IFX_ETH_BUS_MODE_SWR_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_BUS_MODE_Bits.SWR */
+#define IFX_ETH_BUS_MODE_SWR_OFF (0u)
+
+/** \brief Length for Ifx_ETH_BUS_MODE_Bits.TXPR */
+#define IFX_ETH_BUS_MODE_TXPR_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_BUS_MODE_Bits.TXPR */
+#define IFX_ETH_BUS_MODE_TXPR_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_BUS_MODE_Bits.TXPR */
+#define IFX_ETH_BUS_MODE_TXPR_OFF (27u)
+
+/** \brief Length for Ifx_ETH_BUS_MODE_Bits.USP */
+#define IFX_ETH_BUS_MODE_USP_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_BUS_MODE_Bits.USP */
+#define IFX_ETH_BUS_MODE_USP_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_BUS_MODE_Bits.USP */
+#define IFX_ETH_BUS_MODE_USP_OFF (23u)
+
+/** \brief Length for Ifx_ETH_CLC_Bits.DISR */
+#define IFX_ETH_CLC_DISR_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_CLC_Bits.DISR */
+#define IFX_ETH_CLC_DISR_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_CLC_Bits.DISR */
+#define IFX_ETH_CLC_DISR_OFF (0u)
+
+/** \brief Length for Ifx_ETH_CLC_Bits.DISS */
+#define IFX_ETH_CLC_DISS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_CLC_Bits.DISS */
+#define IFX_ETH_CLC_DISS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_CLC_Bits.DISS */
+#define IFX_ETH_CLC_DISS_OFF (1u)
+
+/** \brief Length for
+ * Ifx_ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_Bits.CURRBUFAPTR */
+#define IFX_ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_LEN (32u)
+
+/** \brief Mask for
+ * Ifx_ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_Bits.CURRBUFAPTR */
+#define IFX_ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_MSK (0xffffffffu)
+
+/** \brief Offset for
+ * Ifx_ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_Bits.CURRBUFAPTR */
+#define IFX_ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_OFF (0u)
+
+/** \brief Length for Ifx_ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_Bits.CURRDESAPTR */
+#define IFX_ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_Bits.CURRDESAPTR */
+#define IFX_ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_Bits.CURRDESAPTR */
+#define IFX_ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_OFF (0u)
+
+/** \brief Length for
+ * Ifx_ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_Bits.CURTBUFAPTR */
+#define IFX_ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_LEN (32u)
+
+/** \brief Mask for
+ * Ifx_ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_Bits.CURTBUFAPTR */
+#define IFX_ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_MSK (0xffffffffu)
+
+/** \brief Offset for
+ * Ifx_ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_Bits.CURTBUFAPTR */
+#define IFX_ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_OFF (0u)
+
+/** \brief Length for Ifx_ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_Bits.CURTDESAPTR */
+#define IFX_ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_Bits.CURTDESAPTR */
+#define IFX_ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_Bits.CURTDESAPTR */
+#define IFX_ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_OFF (0u)
+
+/** \brief Length for Ifx_ETH_DEBUG_Bits.RFCFCSTS */
+#define IFX_ETH_DEBUG_RFCFCSTS_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_DEBUG_Bits.RFCFCSTS */
+#define IFX_ETH_DEBUG_RFCFCSTS_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_DEBUG_Bits.RFCFCSTS */
+#define IFX_ETH_DEBUG_RFCFCSTS_OFF (1u)
+
+/** \brief Length for Ifx_ETH_DEBUG_Bits.RPESTS */
+#define IFX_ETH_DEBUG_RPESTS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_DEBUG_Bits.RPESTS */
+#define IFX_ETH_DEBUG_RPESTS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_DEBUG_Bits.RPESTS */
+#define IFX_ETH_DEBUG_RPESTS_OFF (0u)
+
+/** \brief Length for Ifx_ETH_DEBUG_Bits.RRCSTS */
+#define IFX_ETH_DEBUG_RRCSTS_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_DEBUG_Bits.RRCSTS */
+#define IFX_ETH_DEBUG_RRCSTS_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_DEBUG_Bits.RRCSTS */
+#define IFX_ETH_DEBUG_RRCSTS_OFF (5u)
+
+/** \brief Length for Ifx_ETH_DEBUG_Bits.RWCSTS */
+#define IFX_ETH_DEBUG_RWCSTS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_DEBUG_Bits.RWCSTS */
+#define IFX_ETH_DEBUG_RWCSTS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_DEBUG_Bits.RWCSTS */
+#define IFX_ETH_DEBUG_RWCSTS_OFF (4u)
+
+/** \brief Length for Ifx_ETH_DEBUG_Bits.RXFSTS */
+#define IFX_ETH_DEBUG_RXFSTS_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_DEBUG_Bits.RXFSTS */
+#define IFX_ETH_DEBUG_RXFSTS_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_DEBUG_Bits.RXFSTS */
+#define IFX_ETH_DEBUG_RXFSTS_OFF (8u)
+
+/** \brief Length for Ifx_ETH_DEBUG_Bits.TFCSTS */
+#define IFX_ETH_DEBUG_TFCSTS_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_DEBUG_Bits.TFCSTS */
+#define IFX_ETH_DEBUG_TFCSTS_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_DEBUG_Bits.TFCSTS */
+#define IFX_ETH_DEBUG_TFCSTS_OFF (17u)
+
+/** \brief Length for Ifx_ETH_DEBUG_Bits.TPESTS */
+#define IFX_ETH_DEBUG_TPESTS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_DEBUG_Bits.TPESTS */
+#define IFX_ETH_DEBUG_TPESTS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_DEBUG_Bits.TPESTS */
+#define IFX_ETH_DEBUG_TPESTS_OFF (16u)
+
+/** \brief Length for Ifx_ETH_DEBUG_Bits.TRCSTS */
+#define IFX_ETH_DEBUG_TRCSTS_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_DEBUG_Bits.TRCSTS */
+#define IFX_ETH_DEBUG_TRCSTS_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_DEBUG_Bits.TRCSTS */
+#define IFX_ETH_DEBUG_TRCSTS_OFF (20u)
+
+/** \brief Length for Ifx_ETH_DEBUG_Bits.TWCSTS */
+#define IFX_ETH_DEBUG_TWCSTS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_DEBUG_Bits.TWCSTS */
+#define IFX_ETH_DEBUG_TWCSTS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_DEBUG_Bits.TWCSTS */
+#define IFX_ETH_DEBUG_TWCSTS_OFF (22u)
+
+/** \brief Length for Ifx_ETH_DEBUG_Bits.TXFSTS */
+#define IFX_ETH_DEBUG_TXFSTS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_DEBUG_Bits.TXFSTS */
+#define IFX_ETH_DEBUG_TXFSTS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_DEBUG_Bits.TXFSTS */
+#define IFX_ETH_DEBUG_TXFSTS_OFF (24u)
+
+/** \brief Length for Ifx_ETH_DEBUG_Bits.TXPAUSED */
+#define IFX_ETH_DEBUG_TXPAUSED_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_DEBUG_Bits.TXPAUSED */
+#define IFX_ETH_DEBUG_TXPAUSED_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_DEBUG_Bits.TXPAUSED */
+#define IFX_ETH_DEBUG_TXPAUSED_OFF (19u)
+
+/** \brief Length for Ifx_ETH_DEBUG_Bits.TXSTSFSTS */
+#define IFX_ETH_DEBUG_TXSTSFSTS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_DEBUG_Bits.TXSTSFSTS */
+#define IFX_ETH_DEBUG_TXSTSFSTS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_DEBUG_Bits.TXSTSFSTS */
+#define IFX_ETH_DEBUG_TXSTSFSTS_OFF (25u)
+
+/** \brief Length for Ifx_ETH_FLOW_CONTROL_Bits.DZPQ */
+#define IFX_ETH_FLOW_CONTROL_DZPQ_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_FLOW_CONTROL_Bits.DZPQ */
+#define IFX_ETH_FLOW_CONTROL_DZPQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_FLOW_CONTROL_Bits.DZPQ */
+#define IFX_ETH_FLOW_CONTROL_DZPQ_OFF (7u)
+
+/** \brief Length for Ifx_ETH_FLOW_CONTROL_Bits.FCA_BPA */
+#define IFX_ETH_FLOW_CONTROL_FCA_BPA_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_FLOW_CONTROL_Bits.FCA_BPA */
+#define IFX_ETH_FLOW_CONTROL_FCA_BPA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_FLOW_CONTROL_Bits.FCA_BPA */
+#define IFX_ETH_FLOW_CONTROL_FCA_BPA_OFF (0u)
+
+/** \brief Length for Ifx_ETH_FLOW_CONTROL_Bits.PLT */
+#define IFX_ETH_FLOW_CONTROL_PLT_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_FLOW_CONTROL_Bits.PLT */
+#define IFX_ETH_FLOW_CONTROL_PLT_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_FLOW_CONTROL_Bits.PLT */
+#define IFX_ETH_FLOW_CONTROL_PLT_OFF (4u)
+
+/** \brief Length for Ifx_ETH_FLOW_CONTROL_Bits.PT */
+#define IFX_ETH_FLOW_CONTROL_PT_LEN (16u)
+
+/** \brief Mask for Ifx_ETH_FLOW_CONTROL_Bits.PT */
+#define IFX_ETH_FLOW_CONTROL_PT_MSK (0xffffu)
+
+/** \brief Offset for Ifx_ETH_FLOW_CONTROL_Bits.PT */
+#define IFX_ETH_FLOW_CONTROL_PT_OFF (16u)
+
+/** \brief Length for Ifx_ETH_FLOW_CONTROL_Bits.RFE */
+#define IFX_ETH_FLOW_CONTROL_RFE_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_FLOW_CONTROL_Bits.RFE */
+#define IFX_ETH_FLOW_CONTROL_RFE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_FLOW_CONTROL_Bits.RFE */
+#define IFX_ETH_FLOW_CONTROL_RFE_OFF (2u)
+
+/** \brief Length for Ifx_ETH_FLOW_CONTROL_Bits.TFE */
+#define IFX_ETH_FLOW_CONTROL_TFE_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_FLOW_CONTROL_Bits.TFE */
+#define IFX_ETH_FLOW_CONTROL_TFE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_FLOW_CONTROL_Bits.TFE */
+#define IFX_ETH_FLOW_CONTROL_TFE_OFF (1u)
+
+/** \brief Length for Ifx_ETH_FLOW_CONTROL_Bits.UP */
+#define IFX_ETH_FLOW_CONTROL_UP_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_FLOW_CONTROL_Bits.UP */
+#define IFX_ETH_FLOW_CONTROL_UP_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_FLOW_CONTROL_Bits.UP */
+#define IFX_ETH_FLOW_CONTROL_UP_OFF (3u)
+
+/** \brief Length for Ifx_ETH_GMII_ADDRESS_Bits.CR */
+#define IFX_ETH_GMII_ADDRESS_CR_LEN (4u)
+
+/** \brief Mask for Ifx_ETH_GMII_ADDRESS_Bits.CR */
+#define IFX_ETH_GMII_ADDRESS_CR_MSK (0xfu)
+
+/** \brief Offset for Ifx_ETH_GMII_ADDRESS_Bits.CR */
+#define IFX_ETH_GMII_ADDRESS_CR_OFF (2u)
+
+/** \brief Length for Ifx_ETH_GMII_ADDRESS_Bits.GB */
+#define IFX_ETH_GMII_ADDRESS_GB_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_GMII_ADDRESS_Bits.GB */
+#define IFX_ETH_GMII_ADDRESS_GB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_GMII_ADDRESS_Bits.GB */
+#define IFX_ETH_GMII_ADDRESS_GB_OFF (0u)
+
+/** \brief Length for Ifx_ETH_GMII_ADDRESS_Bits.GR */
+#define IFX_ETH_GMII_ADDRESS_GR_LEN (5u)
+
+/** \brief Mask for Ifx_ETH_GMII_ADDRESS_Bits.GR */
+#define IFX_ETH_GMII_ADDRESS_GR_MSK (0x1fu)
+
+/** \brief Offset for Ifx_ETH_GMII_ADDRESS_Bits.GR */
+#define IFX_ETH_GMII_ADDRESS_GR_OFF (6u)
+
+/** \brief Length for Ifx_ETH_GMII_ADDRESS_Bits.GW */
+#define IFX_ETH_GMII_ADDRESS_GW_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_GMII_ADDRESS_Bits.GW */
+#define IFX_ETH_GMII_ADDRESS_GW_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_GMII_ADDRESS_Bits.GW */
+#define IFX_ETH_GMII_ADDRESS_GW_OFF (1u)
+
+/** \brief Length for Ifx_ETH_GMII_ADDRESS_Bits.PA */
+#define IFX_ETH_GMII_ADDRESS_PA_LEN (5u)
+
+/** \brief Mask for Ifx_ETH_GMII_ADDRESS_Bits.PA */
+#define IFX_ETH_GMII_ADDRESS_PA_MSK (0x1fu)
+
+/** \brief Offset for Ifx_ETH_GMII_ADDRESS_Bits.PA */
+#define IFX_ETH_GMII_ADDRESS_PA_OFF (11u)
+
+/** \brief Length for Ifx_ETH_GMII_DATA_Bits.GD */
+#define IFX_ETH_GMII_DATA_GD_LEN (16u)
+
+/** \brief Mask for Ifx_ETH_GMII_DATA_Bits.GD */
+#define IFX_ETH_GMII_DATA_GD_MSK (0xffffu)
+
+/** \brief Offset for Ifx_ETH_GMII_DATA_Bits.GD */
+#define IFX_ETH_GMII_DATA_GD_OFF (0u)
+
+/** \brief Length for Ifx_ETH_GPCTL_Bits.ALTI0 */
+#define IFX_ETH_GPCTL_ALTI0_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_GPCTL_Bits.ALTI0 */
+#define IFX_ETH_GPCTL_ALTI0_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_GPCTL_Bits.ALTI0 */
+#define IFX_ETH_GPCTL_ALTI0_OFF (0u)
+
+/** \brief Length for Ifx_ETH_GPCTL_Bits.ALTI10 */
+#define IFX_ETH_GPCTL_ALTI10_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_GPCTL_Bits.ALTI10 */
+#define IFX_ETH_GPCTL_ALTI10_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_GPCTL_Bits.ALTI10 */
+#define IFX_ETH_GPCTL_ALTI10_OFF (20u)
+
+/** \brief Length for Ifx_ETH_GPCTL_Bits.ALTI1 */
+#define IFX_ETH_GPCTL_ALTI1_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_GPCTL_Bits.ALTI1 */
+#define IFX_ETH_GPCTL_ALTI1_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_GPCTL_Bits.ALTI1 */
+#define IFX_ETH_GPCTL_ALTI1_OFF (2u)
+
+/** \brief Length for Ifx_ETH_GPCTL_Bits.ALTI2 */
+#define IFX_ETH_GPCTL_ALTI2_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_GPCTL_Bits.ALTI2 */
+#define IFX_ETH_GPCTL_ALTI2_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_GPCTL_Bits.ALTI2 */
+#define IFX_ETH_GPCTL_ALTI2_OFF (4u)
+
+/** \brief Length for Ifx_ETH_GPCTL_Bits.ALTI3 */
+#define IFX_ETH_GPCTL_ALTI3_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_GPCTL_Bits.ALTI3 */
+#define IFX_ETH_GPCTL_ALTI3_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_GPCTL_Bits.ALTI3 */
+#define IFX_ETH_GPCTL_ALTI3_OFF (6u)
+
+/** \brief Length for Ifx_ETH_GPCTL_Bits.ALTI4 */
+#define IFX_ETH_GPCTL_ALTI4_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_GPCTL_Bits.ALTI4 */
+#define IFX_ETH_GPCTL_ALTI4_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_GPCTL_Bits.ALTI4 */
+#define IFX_ETH_GPCTL_ALTI4_OFF (8u)
+
+/** \brief Length for Ifx_ETH_GPCTL_Bits.ALTI5 */
+#define IFX_ETH_GPCTL_ALTI5_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_GPCTL_Bits.ALTI5 */
+#define IFX_ETH_GPCTL_ALTI5_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_GPCTL_Bits.ALTI5 */
+#define IFX_ETH_GPCTL_ALTI5_OFF (10u)
+
+/** \brief Length for Ifx_ETH_GPCTL_Bits.ALTI6 */
+#define IFX_ETH_GPCTL_ALTI6_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_GPCTL_Bits.ALTI6 */
+#define IFX_ETH_GPCTL_ALTI6_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_GPCTL_Bits.ALTI6 */
+#define IFX_ETH_GPCTL_ALTI6_OFF (12u)
+
+/** \brief Length for Ifx_ETH_GPCTL_Bits.ALTI7 */
+#define IFX_ETH_GPCTL_ALTI7_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_GPCTL_Bits.ALTI7 */
+#define IFX_ETH_GPCTL_ALTI7_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_GPCTL_Bits.ALTI7 */
+#define IFX_ETH_GPCTL_ALTI7_OFF (14u)
+
+/** \brief Length for Ifx_ETH_GPCTL_Bits.ALTI8 */
+#define IFX_ETH_GPCTL_ALTI8_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_GPCTL_Bits.ALTI8 */
+#define IFX_ETH_GPCTL_ALTI8_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_GPCTL_Bits.ALTI8 */
+#define IFX_ETH_GPCTL_ALTI8_OFF (16u)
+
+/** \brief Length for Ifx_ETH_GPCTL_Bits.ALTI9 */
+#define IFX_ETH_GPCTL_ALTI9_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_GPCTL_Bits.ALTI9 */
+#define IFX_ETH_GPCTL_ALTI9_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_GPCTL_Bits.ALTI9 */
+#define IFX_ETH_GPCTL_ALTI9_OFF (18u)
+
+/** \brief Length for Ifx_ETH_GPCTL_Bits.DIV */
+#define IFX_ETH_GPCTL_DIV_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_GPCTL_Bits.DIV */
+#define IFX_ETH_GPCTL_DIV_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_GPCTL_Bits.DIV */
+#define IFX_ETH_GPCTL_DIV_OFF (25u)
+
+/** \brief Length for Ifx_ETH_GPCTL_Bits.EPR */
+#define IFX_ETH_GPCTL_EPR_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_GPCTL_Bits.EPR */
+#define IFX_ETH_GPCTL_EPR_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_GPCTL_Bits.EPR */
+#define IFX_ETH_GPCTL_EPR_OFF (24u)
+
+/** \brief Length for Ifx_ETH_HASH_TABLE_HIGH_Bits.HTH */
+#define IFX_ETH_HASH_TABLE_HIGH_HTH_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_HASH_TABLE_HIGH_Bits.HTH */
+#define IFX_ETH_HASH_TABLE_HIGH_HTH_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_HASH_TABLE_HIGH_Bits.HTH */
+#define IFX_ETH_HASH_TABLE_HIGH_HTH_OFF (0u)
+
+/** \brief Length for Ifx_ETH_HASH_TABLE_LOW_Bits.HTL */
+#define IFX_ETH_HASH_TABLE_LOW_HTL_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_HASH_TABLE_LOW_Bits.HTL */
+#define IFX_ETH_HASH_TABLE_LOW_HTL_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_HASH_TABLE_LOW_Bits.HTL */
+#define IFX_ETH_HASH_TABLE_LOW_HTL_OFF (0u)
+
+/** \brief Length for Ifx_ETH_HW_FEATURE_Bits.ACTPHYIF */
+#define IFX_ETH_HW_FEATURE_ACTPHYIF_LEN (3u)
+
+/** \brief Mask for Ifx_ETH_HW_FEATURE_Bits.ACTPHYIF */
+#define IFX_ETH_HW_FEATURE_ACTPHYIF_MSK (0x7u)
+
+/** \brief Offset for Ifx_ETH_HW_FEATURE_Bits.ACTPHYIF */
+#define IFX_ETH_HW_FEATURE_ACTPHYIF_OFF (28u)
+
+/** \brief Length for Ifx_ETH_HW_FEATURE_Bits.ADDMACADRSEL */
+#define IFX_ETH_HW_FEATURE_ADDMACADRSEL_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_HW_FEATURE_Bits.ADDMACADRSEL */
+#define IFX_ETH_HW_FEATURE_ADDMACADRSEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_HW_FEATURE_Bits.ADDMACADRSEL */
+#define IFX_ETH_HW_FEATURE_ADDMACADRSEL_OFF (5u)
+
+/** \brief Length for Ifx_ETH_HW_FEATURE_Bits.AVSEL */
+#define IFX_ETH_HW_FEATURE_AVSEL_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_HW_FEATURE_Bits.AVSEL */
+#define IFX_ETH_HW_FEATURE_AVSEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_HW_FEATURE_Bits.AVSEL */
+#define IFX_ETH_HW_FEATURE_AVSEL_OFF (15u)
+
+/** \brief Length for Ifx_ETH_HW_FEATURE_Bits.EEESEL */
+#define IFX_ETH_HW_FEATURE_EEESEL_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_HW_FEATURE_Bits.EEESEL */
+#define IFX_ETH_HW_FEATURE_EEESEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_HW_FEATURE_Bits.EEESEL */
+#define IFX_ETH_HW_FEATURE_EEESEL_OFF (14u)
+
+/** \brief Length for Ifx_ETH_HW_FEATURE_Bits.ENHDESSEL */
+#define IFX_ETH_HW_FEATURE_ENHDESSEL_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_HW_FEATURE_Bits.ENHDESSEL */
+#define IFX_ETH_HW_FEATURE_ENHDESSEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_HW_FEATURE_Bits.ENHDESSEL */
+#define IFX_ETH_HW_FEATURE_ENHDESSEL_OFF (24u)
+
+/** \brief Length for Ifx_ETH_HW_FEATURE_Bits.EXTHASHEN */
+#define IFX_ETH_HW_FEATURE_EXTHASHEN_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_HW_FEATURE_Bits.EXTHASHEN */
+#define IFX_ETH_HW_FEATURE_EXTHASHEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_HW_FEATURE_Bits.EXTHASHEN */
+#define IFX_ETH_HW_FEATURE_EXTHASHEN_OFF (3u)
+
+/** \brief Length for Ifx_ETH_HW_FEATURE_Bits.FLEXIPPSEN */
+#define IFX_ETH_HW_FEATURE_FLEXIPPSEN_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_HW_FEATURE_Bits.FLEXIPPSEN */
+#define IFX_ETH_HW_FEATURE_FLEXIPPSEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_HW_FEATURE_Bits.FLEXIPPSEN */
+#define IFX_ETH_HW_FEATURE_FLEXIPPSEN_OFF (26u)
+
+/** \brief Length for Ifx_ETH_HW_FEATURE_Bits.GMIISEL */
+#define IFX_ETH_HW_FEATURE_GMIISEL_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_HW_FEATURE_Bits.GMIISEL */
+#define IFX_ETH_HW_FEATURE_GMIISEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_HW_FEATURE_Bits.GMIISEL */
+#define IFX_ETH_HW_FEATURE_GMIISEL_OFF (1u)
+
+/** \brief Length for Ifx_ETH_HW_FEATURE_Bits.HASHSEL */
+#define IFX_ETH_HW_FEATURE_HASHSEL_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_HW_FEATURE_Bits.HASHSEL */
+#define IFX_ETH_HW_FEATURE_HASHSEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_HW_FEATURE_Bits.HASHSEL */
+#define IFX_ETH_HW_FEATURE_HASHSEL_OFF (4u)
+
+/** \brief Length for Ifx_ETH_HW_FEATURE_Bits.HDSEL */
+#define IFX_ETH_HW_FEATURE_HDSEL_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_HW_FEATURE_Bits.HDSEL */
+#define IFX_ETH_HW_FEATURE_HDSEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_HW_FEATURE_Bits.HDSEL */
+#define IFX_ETH_HW_FEATURE_HDSEL_OFF (2u)
+
+/** \brief Length for Ifx_ETH_HW_FEATURE_Bits.INTTSEN */
+#define IFX_ETH_HW_FEATURE_INTTSEN_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_HW_FEATURE_Bits.INTTSEN */
+#define IFX_ETH_HW_FEATURE_INTTSEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_HW_FEATURE_Bits.INTTSEN */
+#define IFX_ETH_HW_FEATURE_INTTSEN_OFF (25u)
+
+/** \brief Length for Ifx_ETH_HW_FEATURE_Bits.L3L4FLTREN */
+#define IFX_ETH_HW_FEATURE_L3L4FLTREN_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_HW_FEATURE_Bits.L3L4FLTREN */
+#define IFX_ETH_HW_FEATURE_L3L4FLTREN_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_HW_FEATURE_Bits.L3L4FLTREN */
+#define IFX_ETH_HW_FEATURE_L3L4FLTREN_OFF (7u)
+
+/** \brief Length for Ifx_ETH_HW_FEATURE_Bits.MGKSEL */
+#define IFX_ETH_HW_FEATURE_MGKSEL_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_HW_FEATURE_Bits.MGKSEL */
+#define IFX_ETH_HW_FEATURE_MGKSEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_HW_FEATURE_Bits.MGKSEL */
+#define IFX_ETH_HW_FEATURE_MGKSEL_OFF (10u)
+
+/** \brief Length for Ifx_ETH_HW_FEATURE_Bits.MIISEL */
+#define IFX_ETH_HW_FEATURE_MIISEL_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_HW_FEATURE_Bits.MIISEL */
+#define IFX_ETH_HW_FEATURE_MIISEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_HW_FEATURE_Bits.MIISEL */
+#define IFX_ETH_HW_FEATURE_MIISEL_OFF (0u)
+
+/** \brief Length for Ifx_ETH_HW_FEATURE_Bits.MMCSEL */
+#define IFX_ETH_HW_FEATURE_MMCSEL_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_HW_FEATURE_Bits.MMCSEL */
+#define IFX_ETH_HW_FEATURE_MMCSEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_HW_FEATURE_Bits.MMCSEL */
+#define IFX_ETH_HW_FEATURE_MMCSEL_OFF (11u)
+
+/** \brief Length for Ifx_ETH_HW_FEATURE_Bits.PCSSEL */
+#define IFX_ETH_HW_FEATURE_PCSSEL_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_HW_FEATURE_Bits.PCSSEL */
+#define IFX_ETH_HW_FEATURE_PCSSEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_HW_FEATURE_Bits.PCSSEL */
+#define IFX_ETH_HW_FEATURE_PCSSEL_OFF (6u)
+
+/** \brief Length for Ifx_ETH_HW_FEATURE_Bits.RWKSEL */
+#define IFX_ETH_HW_FEATURE_RWKSEL_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_HW_FEATURE_Bits.RWKSEL */
+#define IFX_ETH_HW_FEATURE_RWKSEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_HW_FEATURE_Bits.RWKSEL */
+#define IFX_ETH_HW_FEATURE_RWKSEL_OFF (9u)
+
+/** \brief Length for Ifx_ETH_HW_FEATURE_Bits.RXCHCNT */
+#define IFX_ETH_HW_FEATURE_RXCHCNT_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_HW_FEATURE_Bits.RXCHCNT */
+#define IFX_ETH_HW_FEATURE_RXCHCNT_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_HW_FEATURE_Bits.RXCHCNT */
+#define IFX_ETH_HW_FEATURE_RXCHCNT_OFF (20u)
+
+/** \brief Length for Ifx_ETH_HW_FEATURE_Bits.RXFIFOSIZE */
+#define IFX_ETH_HW_FEATURE_RXFIFOSIZE_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_HW_FEATURE_Bits.RXFIFOSIZE */
+#define IFX_ETH_HW_FEATURE_RXFIFOSIZE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_HW_FEATURE_Bits.RXFIFOSIZE */
+#define IFX_ETH_HW_FEATURE_RXFIFOSIZE_OFF (19u)
+
+/** \brief Length for Ifx_ETH_HW_FEATURE_Bits.RXTYP1COE */
+#define IFX_ETH_HW_FEATURE_RXTYP1COE_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_HW_FEATURE_Bits.RXTYP1COE */
+#define IFX_ETH_HW_FEATURE_RXTYP1COE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_HW_FEATURE_Bits.RXTYP1COE */
+#define IFX_ETH_HW_FEATURE_RXTYP1COE_OFF (17u)
+
+/** \brief Length for Ifx_ETH_HW_FEATURE_Bits.RXTYP2COE */
+#define IFX_ETH_HW_FEATURE_RXTYP2COE_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_HW_FEATURE_Bits.RXTYP2COE */
+#define IFX_ETH_HW_FEATURE_RXTYP2COE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_HW_FEATURE_Bits.RXTYP2COE */
+#define IFX_ETH_HW_FEATURE_RXTYP2COE_OFF (18u)
+
+/** \brief Length for Ifx_ETH_HW_FEATURE_Bits.SAVLANINS */
+#define IFX_ETH_HW_FEATURE_SAVLANINS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_HW_FEATURE_Bits.SAVLANINS */
+#define IFX_ETH_HW_FEATURE_SAVLANINS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_HW_FEATURE_Bits.SAVLANINS */
+#define IFX_ETH_HW_FEATURE_SAVLANINS_OFF (27u)
+
+/** \brief Length for Ifx_ETH_HW_FEATURE_Bits.SMASEL */
+#define IFX_ETH_HW_FEATURE_SMASEL_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_HW_FEATURE_Bits.SMASEL */
+#define IFX_ETH_HW_FEATURE_SMASEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_HW_FEATURE_Bits.SMASEL */
+#define IFX_ETH_HW_FEATURE_SMASEL_OFF (8u)
+
+/** \brief Length for Ifx_ETH_HW_FEATURE_Bits.TSVER1SEL */
+#define IFX_ETH_HW_FEATURE_TSVER1SEL_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_HW_FEATURE_Bits.TSVER1SEL */
+#define IFX_ETH_HW_FEATURE_TSVER1SEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_HW_FEATURE_Bits.TSVER1SEL */
+#define IFX_ETH_HW_FEATURE_TSVER1SEL_OFF (12u)
+
+/** \brief Length for Ifx_ETH_HW_FEATURE_Bits.TSVER2SEL */
+#define IFX_ETH_HW_FEATURE_TSVER2SEL_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_HW_FEATURE_Bits.TSVER2SEL */
+#define IFX_ETH_HW_FEATURE_TSVER2SEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_HW_FEATURE_Bits.TSVER2SEL */
+#define IFX_ETH_HW_FEATURE_TSVER2SEL_OFF (13u)
+
+/** \brief Length for Ifx_ETH_HW_FEATURE_Bits.TXCHCNT */
+#define IFX_ETH_HW_FEATURE_TXCHCNT_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_HW_FEATURE_Bits.TXCHCNT */
+#define IFX_ETH_HW_FEATURE_TXCHCNT_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_HW_FEATURE_Bits.TXCHCNT */
+#define IFX_ETH_HW_FEATURE_TXCHCNT_OFF (22u)
+
+/** \brief Length for Ifx_ETH_HW_FEATURE_Bits.TXCOESEL */
+#define IFX_ETH_HW_FEATURE_TXCOESEL_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_HW_FEATURE_Bits.TXCOESEL */
+#define IFX_ETH_HW_FEATURE_TXCOESEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_HW_FEATURE_Bits.TXCOESEL */
+#define IFX_ETH_HW_FEATURE_TXCOESEL_OFF (16u)
+
+/** \brief Length for Ifx_ETH_ID_Bits.MODNUMBER */
+#define IFX_ETH_ID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_ETH_ID_Bits.MODNUMBER */
+#define IFX_ETH_ID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_ETH_ID_Bits.MODNUMBER */
+#define IFX_ETH_ID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_ETH_ID_Bits.MODREV */
+#define IFX_ETH_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_ETH_ID_Bits.MODREV */
+#define IFX_ETH_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_ETH_ID_Bits.MODREV */
+#define IFX_ETH_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_ETH_ID_Bits.MODTYPE */
+#define IFX_ETH_ID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_ETH_ID_Bits.MODTYPE */
+#define IFX_ETH_ID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_ETH_ID_Bits.MODTYPE */
+#define IFX_ETH_ID_MODTYPE_OFF (8u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_ENABLE_Bits.AIE */
+#define IFX_ETH_INTERRUPT_ENABLE_AIE_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_ENABLE_Bits.AIE */
+#define IFX_ETH_INTERRUPT_ENABLE_AIE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_ENABLE_Bits.AIE */
+#define IFX_ETH_INTERRUPT_ENABLE_AIE_OFF (15u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_ENABLE_Bits.ERE */
+#define IFX_ETH_INTERRUPT_ENABLE_ERE_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_ENABLE_Bits.ERE */
+#define IFX_ETH_INTERRUPT_ENABLE_ERE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_ENABLE_Bits.ERE */
+#define IFX_ETH_INTERRUPT_ENABLE_ERE_OFF (14u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_ENABLE_Bits.ETE */
+#define IFX_ETH_INTERRUPT_ENABLE_ETE_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_ENABLE_Bits.ETE */
+#define IFX_ETH_INTERRUPT_ENABLE_ETE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_ENABLE_Bits.ETE */
+#define IFX_ETH_INTERRUPT_ENABLE_ETE_OFF (10u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_ENABLE_Bits.FBE */
+#define IFX_ETH_INTERRUPT_ENABLE_FBE_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_ENABLE_Bits.FBE */
+#define IFX_ETH_INTERRUPT_ENABLE_FBE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_ENABLE_Bits.FBE */
+#define IFX_ETH_INTERRUPT_ENABLE_FBE_OFF (13u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_ENABLE_Bits.NIE */
+#define IFX_ETH_INTERRUPT_ENABLE_NIE_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_ENABLE_Bits.NIE */
+#define IFX_ETH_INTERRUPT_ENABLE_NIE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_ENABLE_Bits.NIE */
+#define IFX_ETH_INTERRUPT_ENABLE_NIE_OFF (16u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_ENABLE_Bits.OVE */
+#define IFX_ETH_INTERRUPT_ENABLE_OVE_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_ENABLE_Bits.OVE */
+#define IFX_ETH_INTERRUPT_ENABLE_OVE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_ENABLE_Bits.OVE */
+#define IFX_ETH_INTERRUPT_ENABLE_OVE_OFF (4u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_ENABLE_Bits.RIE */
+#define IFX_ETH_INTERRUPT_ENABLE_RIE_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_ENABLE_Bits.RIE */
+#define IFX_ETH_INTERRUPT_ENABLE_RIE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_ENABLE_Bits.RIE */
+#define IFX_ETH_INTERRUPT_ENABLE_RIE_OFF (6u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_ENABLE_Bits.RSE */
+#define IFX_ETH_INTERRUPT_ENABLE_RSE_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_ENABLE_Bits.RSE */
+#define IFX_ETH_INTERRUPT_ENABLE_RSE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_ENABLE_Bits.RSE */
+#define IFX_ETH_INTERRUPT_ENABLE_RSE_OFF (8u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_ENABLE_Bits.RUE */
+#define IFX_ETH_INTERRUPT_ENABLE_RUE_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_ENABLE_Bits.RUE */
+#define IFX_ETH_INTERRUPT_ENABLE_RUE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_ENABLE_Bits.RUE */
+#define IFX_ETH_INTERRUPT_ENABLE_RUE_OFF (7u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_ENABLE_Bits.RWE */
+#define IFX_ETH_INTERRUPT_ENABLE_RWE_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_ENABLE_Bits.RWE */
+#define IFX_ETH_INTERRUPT_ENABLE_RWE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_ENABLE_Bits.RWE */
+#define IFX_ETH_INTERRUPT_ENABLE_RWE_OFF (9u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_ENABLE_Bits.TIE */
+#define IFX_ETH_INTERRUPT_ENABLE_TIE_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_ENABLE_Bits.TIE */
+#define IFX_ETH_INTERRUPT_ENABLE_TIE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_ENABLE_Bits.TIE */
+#define IFX_ETH_INTERRUPT_ENABLE_TIE_OFF (0u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_ENABLE_Bits.TJE */
+#define IFX_ETH_INTERRUPT_ENABLE_TJE_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_ENABLE_Bits.TJE */
+#define IFX_ETH_INTERRUPT_ENABLE_TJE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_ENABLE_Bits.TJE */
+#define IFX_ETH_INTERRUPT_ENABLE_TJE_OFF (3u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_ENABLE_Bits.TSE */
+#define IFX_ETH_INTERRUPT_ENABLE_TSE_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_ENABLE_Bits.TSE */
+#define IFX_ETH_INTERRUPT_ENABLE_TSE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_ENABLE_Bits.TSE */
+#define IFX_ETH_INTERRUPT_ENABLE_TSE_OFF (1u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_ENABLE_Bits.TUE */
+#define IFX_ETH_INTERRUPT_ENABLE_TUE_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_ENABLE_Bits.TUE */
+#define IFX_ETH_INTERRUPT_ENABLE_TUE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_ENABLE_Bits.TUE */
+#define IFX_ETH_INTERRUPT_ENABLE_TUE_OFF (2u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_ENABLE_Bits.UNE */
+#define IFX_ETH_INTERRUPT_ENABLE_UNE_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_ENABLE_Bits.UNE */
+#define IFX_ETH_INTERRUPT_ENABLE_UNE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_ENABLE_Bits.UNE */
+#define IFX_ETH_INTERRUPT_ENABLE_UNE_OFF (5u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_MASK_Bits.LPIIM */
+#define IFX_ETH_INTERRUPT_MASK_LPIIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_MASK_Bits.LPIIM */
+#define IFX_ETH_INTERRUPT_MASK_LPIIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_MASK_Bits.LPIIM */
+#define IFX_ETH_INTERRUPT_MASK_LPIIM_OFF (10u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_MASK_Bits.PCSANCIM */
+#define IFX_ETH_INTERRUPT_MASK_PCSANCIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_MASK_Bits.PCSANCIM */
+#define IFX_ETH_INTERRUPT_MASK_PCSANCIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_MASK_Bits.PCSANCIM */
+#define IFX_ETH_INTERRUPT_MASK_PCSANCIM_OFF (2u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_MASK_Bits.PCSLCHGIM */
+#define IFX_ETH_INTERRUPT_MASK_PCSLCHGIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_MASK_Bits.PCSLCHGIM */
+#define IFX_ETH_INTERRUPT_MASK_PCSLCHGIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_MASK_Bits.PCSLCHGIM */
+#define IFX_ETH_INTERRUPT_MASK_PCSLCHGIM_OFF (1u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_MASK_Bits.PMTIM */
+#define IFX_ETH_INTERRUPT_MASK_PMTIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_MASK_Bits.PMTIM */
+#define IFX_ETH_INTERRUPT_MASK_PMTIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_MASK_Bits.PMTIM */
+#define IFX_ETH_INTERRUPT_MASK_PMTIM_OFF (3u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_MASK_Bits.RGSMIIIM */
+#define IFX_ETH_INTERRUPT_MASK_RGSMIIIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_MASK_Bits.RGSMIIIM */
+#define IFX_ETH_INTERRUPT_MASK_RGSMIIIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_MASK_Bits.RGSMIIIM */
+#define IFX_ETH_INTERRUPT_MASK_RGSMIIIM_OFF (0u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_MASK_Bits.TSIM */
+#define IFX_ETH_INTERRUPT_MASK_TSIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_MASK_Bits.TSIM */
+#define IFX_ETH_INTERRUPT_MASK_TSIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_MASK_Bits.TSIM */
+#define IFX_ETH_INTERRUPT_MASK_TSIM_OFF (9u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_STATUS_Bits.LPIIS */
+#define IFX_ETH_INTERRUPT_STATUS_LPIIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_STATUS_Bits.LPIIS */
+#define IFX_ETH_INTERRUPT_STATUS_LPIIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_STATUS_Bits.LPIIS */
+#define IFX_ETH_INTERRUPT_STATUS_LPIIS_OFF (10u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_STATUS_Bits.MMCIS */
+#define IFX_ETH_INTERRUPT_STATUS_MMCIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_STATUS_Bits.MMCIS */
+#define IFX_ETH_INTERRUPT_STATUS_MMCIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_STATUS_Bits.MMCIS */
+#define IFX_ETH_INTERRUPT_STATUS_MMCIS_OFF (4u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_STATUS_Bits.MMCRXIPIS */
+#define IFX_ETH_INTERRUPT_STATUS_MMCRXIPIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_STATUS_Bits.MMCRXIPIS */
+#define IFX_ETH_INTERRUPT_STATUS_MMCRXIPIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_STATUS_Bits.MMCRXIPIS */
+#define IFX_ETH_INTERRUPT_STATUS_MMCRXIPIS_OFF (7u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_STATUS_Bits.MMCRXIS */
+#define IFX_ETH_INTERRUPT_STATUS_MMCRXIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_STATUS_Bits.MMCRXIS */
+#define IFX_ETH_INTERRUPT_STATUS_MMCRXIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_STATUS_Bits.MMCRXIS */
+#define IFX_ETH_INTERRUPT_STATUS_MMCRXIS_OFF (5u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_STATUS_Bits.MMCTXIS */
+#define IFX_ETH_INTERRUPT_STATUS_MMCTXIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_STATUS_Bits.MMCTXIS */
+#define IFX_ETH_INTERRUPT_STATUS_MMCTXIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_STATUS_Bits.MMCTXIS */
+#define IFX_ETH_INTERRUPT_STATUS_MMCTXIS_OFF (6u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_STATUS_Bits.PCSANCIS */
+#define IFX_ETH_INTERRUPT_STATUS_PCSANCIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_STATUS_Bits.PCSANCIS */
+#define IFX_ETH_INTERRUPT_STATUS_PCSANCIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_STATUS_Bits.PCSANCIS */
+#define IFX_ETH_INTERRUPT_STATUS_PCSANCIS_OFF (2u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_STATUS_Bits.PCSLCHGIS */
+#define IFX_ETH_INTERRUPT_STATUS_PCSLCHGIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_STATUS_Bits.PCSLCHGIS */
+#define IFX_ETH_INTERRUPT_STATUS_PCSLCHGIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_STATUS_Bits.PCSLCHGIS */
+#define IFX_ETH_INTERRUPT_STATUS_PCSLCHGIS_OFF (1u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_STATUS_Bits.PMTIS */
+#define IFX_ETH_INTERRUPT_STATUS_PMTIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_STATUS_Bits.PMTIS */
+#define IFX_ETH_INTERRUPT_STATUS_PMTIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_STATUS_Bits.PMTIS */
+#define IFX_ETH_INTERRUPT_STATUS_PMTIS_OFF (3u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_STATUS_Bits.RGSMIIIS */
+#define IFX_ETH_INTERRUPT_STATUS_RGSMIIIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_STATUS_Bits.RGSMIIIS */
+#define IFX_ETH_INTERRUPT_STATUS_RGSMIIIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_STATUS_Bits.RGSMIIIS */
+#define IFX_ETH_INTERRUPT_STATUS_RGSMIIIS_OFF (0u)
+
+/** \brief Length for Ifx_ETH_INTERRUPT_STATUS_Bits.TSIS */
+#define IFX_ETH_INTERRUPT_STATUS_TSIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_INTERRUPT_STATUS_Bits.TSIS */
+#define IFX_ETH_INTERRUPT_STATUS_TSIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_INTERRUPT_STATUS_Bits.TSIS */
+#define IFX_ETH_INTERRUPT_STATUS_TSIS_OFF (9u)
+
+/** \brief Length for Ifx_ETH_KRST0_Bits.RST */
+#define IFX_ETH_KRST0_RST_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_KRST0_Bits.RST */
+#define IFX_ETH_KRST0_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_KRST0_Bits.RST */
+#define IFX_ETH_KRST0_RST_OFF (0u)
+
+/** \brief Length for Ifx_ETH_KRST0_Bits.RSTSTAT */
+#define IFX_ETH_KRST0_RSTSTAT_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_KRST0_Bits.RSTSTAT */
+#define IFX_ETH_KRST0_RSTSTAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_KRST0_Bits.RSTSTAT */
+#define IFX_ETH_KRST0_RSTSTAT_OFF (1u)
+
+/** \brief Length for Ifx_ETH_KRST1_Bits.RST */
+#define IFX_ETH_KRST1_RST_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_KRST1_Bits.RST */
+#define IFX_ETH_KRST1_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_KRST1_Bits.RST */
+#define IFX_ETH_KRST1_RST_OFF (0u)
+
+/** \brief Length for Ifx_ETH_KRSTCLR_Bits.CLR */
+#define IFX_ETH_KRSTCLR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_KRSTCLR_Bits.CLR */
+#define IFX_ETH_KRSTCLR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_KRSTCLR_Bits.CLR */
+#define IFX_ETH_KRSTCLR_CLR_OFF (0u)
+
+/** \brief Length for Ifx_ETH_MAC_ADDRESS_HIGH_Bits.ADDRHI */
+#define IFX_ETH_MAC_ADDRESS_HIGH_ADDRHI_LEN (16u)
+
+/** \brief Mask for Ifx_ETH_MAC_ADDRESS_HIGH_Bits.ADDRHI */
+#define IFX_ETH_MAC_ADDRESS_HIGH_ADDRHI_MSK (0xffffu)
+
+/** \brief Offset for Ifx_ETH_MAC_ADDRESS_HIGH_Bits.ADDRHI */
+#define IFX_ETH_MAC_ADDRESS_HIGH_ADDRHI_OFF (0u)
+
+/** \brief Length for Ifx_ETH_MAC_ADDRESS_HIGH_Bits.AE */
+#define IFX_ETH_MAC_ADDRESS_HIGH_AE_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_ADDRESS_HIGH_Bits.AE */
+#define IFX_ETH_MAC_ADDRESS_HIGH_AE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_ADDRESS_HIGH_Bits.AE */
+#define IFX_ETH_MAC_ADDRESS_HIGH_AE_OFF (31u)
+
+/** \brief Length for Ifx_ETH_MAC_ADDRESS_HIGH_Bits.MBC */
+#define IFX_ETH_MAC_ADDRESS_HIGH_MBC_LEN (6u)
+
+/** \brief Mask for Ifx_ETH_MAC_ADDRESS_HIGH_Bits.MBC */
+#define IFX_ETH_MAC_ADDRESS_HIGH_MBC_MSK (0x3fu)
+
+/** \brief Offset for Ifx_ETH_MAC_ADDRESS_HIGH_Bits.MBC */
+#define IFX_ETH_MAC_ADDRESS_HIGH_MBC_OFF (24u)
+
+/** \brief Length for Ifx_ETH_MAC_ADDRESS_HIGH_Bits.SA */
+#define IFX_ETH_MAC_ADDRESS_HIGH_SA_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_ADDRESS_HIGH_Bits.SA */
+#define IFX_ETH_MAC_ADDRESS_HIGH_SA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_ADDRESS_HIGH_Bits.SA */
+#define IFX_ETH_MAC_ADDRESS_HIGH_SA_OFF (30u)
+
+/** \brief Length for Ifx_ETH_MAC_ADDRESS_LOW_Bits.ADDRLO */
+#define IFX_ETH_MAC_ADDRESS_LOW_ADDRLO_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_MAC_ADDRESS_LOW_Bits.ADDRLO */
+#define IFX_ETH_MAC_ADDRESS_LOW_ADDRLO_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_MAC_ADDRESS_LOW_Bits.ADDRLO */
+#define IFX_ETH_MAC_ADDRESS_LOW_ADDRLO_OFF (0u)
+
+/** \brief Length for Ifx_ETH_MAC_CONFIGURATION_Bits.ACS */
+#define IFX_ETH_MAC_CONFIGURATION_ACS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_CONFIGURATION_Bits.ACS */
+#define IFX_ETH_MAC_CONFIGURATION_ACS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_CONFIGURATION_Bits.ACS */
+#define IFX_ETH_MAC_CONFIGURATION_ACS_OFF (7u)
+
+/** \brief Length for Ifx_ETH_MAC_CONFIGURATION_Bits.BE */
+#define IFX_ETH_MAC_CONFIGURATION_BE_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_CONFIGURATION_Bits.BE */
+#define IFX_ETH_MAC_CONFIGURATION_BE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_CONFIGURATION_Bits.BE */
+#define IFX_ETH_MAC_CONFIGURATION_BE_OFF (21u)
+
+/** \brief Length for Ifx_ETH_MAC_CONFIGURATION_Bits.BL */
+#define IFX_ETH_MAC_CONFIGURATION_BL_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_MAC_CONFIGURATION_Bits.BL */
+#define IFX_ETH_MAC_CONFIGURATION_BL_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_MAC_CONFIGURATION_Bits.BL */
+#define IFX_ETH_MAC_CONFIGURATION_BL_OFF (5u)
+
+/** \brief Length for Ifx_ETH_MAC_CONFIGURATION_Bits.CST */
+#define IFX_ETH_MAC_CONFIGURATION_CST_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_CONFIGURATION_Bits.CST */
+#define IFX_ETH_MAC_CONFIGURATION_CST_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_CONFIGURATION_Bits.CST */
+#define IFX_ETH_MAC_CONFIGURATION_CST_OFF (25u)
+
+/** \brief Length for Ifx_ETH_MAC_CONFIGURATION_Bits.DC */
+#define IFX_ETH_MAC_CONFIGURATION_DC_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_CONFIGURATION_Bits.DC */
+#define IFX_ETH_MAC_CONFIGURATION_DC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_CONFIGURATION_Bits.DC */
+#define IFX_ETH_MAC_CONFIGURATION_DC_OFF (4u)
+
+/** \brief Length for Ifx_ETH_MAC_CONFIGURATION_Bits.DCRS */
+#define IFX_ETH_MAC_CONFIGURATION_DCRS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_CONFIGURATION_Bits.DCRS */
+#define IFX_ETH_MAC_CONFIGURATION_DCRS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_CONFIGURATION_Bits.DCRS */
+#define IFX_ETH_MAC_CONFIGURATION_DCRS_OFF (16u)
+
+/** \brief Length for Ifx_ETH_MAC_CONFIGURATION_Bits.DM */
+#define IFX_ETH_MAC_CONFIGURATION_DM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_CONFIGURATION_Bits.DM */
+#define IFX_ETH_MAC_CONFIGURATION_DM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_CONFIGURATION_Bits.DM */
+#define IFX_ETH_MAC_CONFIGURATION_DM_OFF (11u)
+
+/** \brief Length for Ifx_ETH_MAC_CONFIGURATION_Bits.DO */
+#define IFX_ETH_MAC_CONFIGURATION_DO_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_CONFIGURATION_Bits.DO */
+#define IFX_ETH_MAC_CONFIGURATION_DO_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_CONFIGURATION_Bits.DO */
+#define IFX_ETH_MAC_CONFIGURATION_DO_OFF (13u)
+
+/** \brief Length for Ifx_ETH_MAC_CONFIGURATION_Bits.DR */
+#define IFX_ETH_MAC_CONFIGURATION_DR_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_CONFIGURATION_Bits.DR */
+#define IFX_ETH_MAC_CONFIGURATION_DR_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_CONFIGURATION_Bits.DR */
+#define IFX_ETH_MAC_CONFIGURATION_DR_OFF (9u)
+
+/** \brief Length for Ifx_ETH_MAC_CONFIGURATION_Bits.FES */
+#define IFX_ETH_MAC_CONFIGURATION_FES_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_CONFIGURATION_Bits.FES */
+#define IFX_ETH_MAC_CONFIGURATION_FES_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_CONFIGURATION_Bits.FES */
+#define IFX_ETH_MAC_CONFIGURATION_FES_OFF (14u)
+
+/** \brief Length for Ifx_ETH_MAC_CONFIGURATION_Bits.IFG */
+#define IFX_ETH_MAC_CONFIGURATION_IFG_LEN (3u)
+
+/** \brief Mask for Ifx_ETH_MAC_CONFIGURATION_Bits.IFG */
+#define IFX_ETH_MAC_CONFIGURATION_IFG_MSK (0x7u)
+
+/** \brief Offset for Ifx_ETH_MAC_CONFIGURATION_Bits.IFG */
+#define IFX_ETH_MAC_CONFIGURATION_IFG_OFF (17u)
+
+/** \brief Length for Ifx_ETH_MAC_CONFIGURATION_Bits.IPC */
+#define IFX_ETH_MAC_CONFIGURATION_IPC_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_CONFIGURATION_Bits.IPC */
+#define IFX_ETH_MAC_CONFIGURATION_IPC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_CONFIGURATION_Bits.IPC */
+#define IFX_ETH_MAC_CONFIGURATION_IPC_OFF (10u)
+
+/** \brief Length for Ifx_ETH_MAC_CONFIGURATION_Bits.JD */
+#define IFX_ETH_MAC_CONFIGURATION_JD_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_CONFIGURATION_Bits.JD */
+#define IFX_ETH_MAC_CONFIGURATION_JD_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_CONFIGURATION_Bits.JD */
+#define IFX_ETH_MAC_CONFIGURATION_JD_OFF (22u)
+
+/** \brief Length for Ifx_ETH_MAC_CONFIGURATION_Bits.JE */
+#define IFX_ETH_MAC_CONFIGURATION_JE_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_CONFIGURATION_Bits.JE */
+#define IFX_ETH_MAC_CONFIGURATION_JE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_CONFIGURATION_Bits.JE */
+#define IFX_ETH_MAC_CONFIGURATION_JE_OFF (20u)
+
+/** \brief Length for Ifx_ETH_MAC_CONFIGURATION_Bits.LM */
+#define IFX_ETH_MAC_CONFIGURATION_LM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_CONFIGURATION_Bits.LM */
+#define IFX_ETH_MAC_CONFIGURATION_LM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_CONFIGURATION_Bits.LM */
+#define IFX_ETH_MAC_CONFIGURATION_LM_OFF (12u)
+
+/** \brief Length for Ifx_ETH_MAC_CONFIGURATION_Bits.LUD */
+#define IFX_ETH_MAC_CONFIGURATION_LUD_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_CONFIGURATION_Bits.LUD */
+#define IFX_ETH_MAC_CONFIGURATION_LUD_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_CONFIGURATION_Bits.LUD */
+#define IFX_ETH_MAC_CONFIGURATION_LUD_OFF (8u)
+
+/** \brief Length for Ifx_ETH_MAC_CONFIGURATION_Bits.PRELEN */
+#define IFX_ETH_MAC_CONFIGURATION_PRELEN_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_MAC_CONFIGURATION_Bits.PRELEN */
+#define IFX_ETH_MAC_CONFIGURATION_PRELEN_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_MAC_CONFIGURATION_Bits.PRELEN */
+#define IFX_ETH_MAC_CONFIGURATION_PRELEN_OFF (0u)
+
+/** \brief Length for Ifx_ETH_MAC_CONFIGURATION_Bits.PS */
+#define IFX_ETH_MAC_CONFIGURATION_PS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_CONFIGURATION_Bits.PS */
+#define IFX_ETH_MAC_CONFIGURATION_PS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_CONFIGURATION_Bits.PS */
+#define IFX_ETH_MAC_CONFIGURATION_PS_OFF (15u)
+
+/** \brief Length for Ifx_ETH_MAC_CONFIGURATION_Bits.RE */
+#define IFX_ETH_MAC_CONFIGURATION_RE_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_CONFIGURATION_Bits.RE */
+#define IFX_ETH_MAC_CONFIGURATION_RE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_CONFIGURATION_Bits.RE */
+#define IFX_ETH_MAC_CONFIGURATION_RE_OFF (2u)
+
+/** \brief Length for Ifx_ETH_MAC_CONFIGURATION_Bits.SARC */
+#define IFX_ETH_MAC_CONFIGURATION_SARC_LEN (3u)
+
+/** \brief Mask for Ifx_ETH_MAC_CONFIGURATION_Bits.SARC */
+#define IFX_ETH_MAC_CONFIGURATION_SARC_MSK (0x7u)
+
+/** \brief Offset for Ifx_ETH_MAC_CONFIGURATION_Bits.SARC */
+#define IFX_ETH_MAC_CONFIGURATION_SARC_OFF (28u)
+
+/** \brief Length for Ifx_ETH_MAC_CONFIGURATION_Bits.SFTERR */
+#define IFX_ETH_MAC_CONFIGURATION_SFTERR_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_CONFIGURATION_Bits.SFTERR */
+#define IFX_ETH_MAC_CONFIGURATION_SFTERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_CONFIGURATION_Bits.SFTERR */
+#define IFX_ETH_MAC_CONFIGURATION_SFTERR_OFF (26u)
+
+/** \brief Length for Ifx_ETH_MAC_CONFIGURATION_Bits.TC */
+#define IFX_ETH_MAC_CONFIGURATION_TC_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_CONFIGURATION_Bits.TC */
+#define IFX_ETH_MAC_CONFIGURATION_TC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_CONFIGURATION_Bits.TC */
+#define IFX_ETH_MAC_CONFIGURATION_TC_OFF (24u)
+
+/** \brief Length for Ifx_ETH_MAC_CONFIGURATION_Bits.TE */
+#define IFX_ETH_MAC_CONFIGURATION_TE_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_CONFIGURATION_Bits.TE */
+#define IFX_ETH_MAC_CONFIGURATION_TE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_CONFIGURATION_Bits.TE */
+#define IFX_ETH_MAC_CONFIGURATION_TE_OFF (3u)
+
+/** \brief Length for Ifx_ETH_MAC_CONFIGURATION_Bits.TWOKPE */
+#define IFX_ETH_MAC_CONFIGURATION_TWOKPE_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_CONFIGURATION_Bits.TWOKPE */
+#define IFX_ETH_MAC_CONFIGURATION_TWOKPE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_CONFIGURATION_Bits.TWOKPE */
+#define IFX_ETH_MAC_CONFIGURATION_TWOKPE_OFF (27u)
+
+/** \brief Length for Ifx_ETH_MAC_CONFIGURATION_Bits.WD */
+#define IFX_ETH_MAC_CONFIGURATION_WD_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_CONFIGURATION_Bits.WD */
+#define IFX_ETH_MAC_CONFIGURATION_WD_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_CONFIGURATION_Bits.WD */
+#define IFX_ETH_MAC_CONFIGURATION_WD_OFF (23u)
+
+/** \brief Length for Ifx_ETH_MAC_FRAME_FILTER_Bits.DAIF */
+#define IFX_ETH_MAC_FRAME_FILTER_DAIF_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_FRAME_FILTER_Bits.DAIF */
+#define IFX_ETH_MAC_FRAME_FILTER_DAIF_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_FRAME_FILTER_Bits.DAIF */
+#define IFX_ETH_MAC_FRAME_FILTER_DAIF_OFF (3u)
+
+/** \brief Length for Ifx_ETH_MAC_FRAME_FILTER_Bits.DBF */
+#define IFX_ETH_MAC_FRAME_FILTER_DBF_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_FRAME_FILTER_Bits.DBF */
+#define IFX_ETH_MAC_FRAME_FILTER_DBF_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_FRAME_FILTER_Bits.DBF */
+#define IFX_ETH_MAC_FRAME_FILTER_DBF_OFF (5u)
+
+/** \brief Length for Ifx_ETH_MAC_FRAME_FILTER_Bits.DNTU */
+#define IFX_ETH_MAC_FRAME_FILTER_DNTU_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_FRAME_FILTER_Bits.DNTU */
+#define IFX_ETH_MAC_FRAME_FILTER_DNTU_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_FRAME_FILTER_Bits.DNTU */
+#define IFX_ETH_MAC_FRAME_FILTER_DNTU_OFF (21u)
+
+/** \brief Length for Ifx_ETH_MAC_FRAME_FILTER_Bits.HMC */
+#define IFX_ETH_MAC_FRAME_FILTER_HMC_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_FRAME_FILTER_Bits.HMC */
+#define IFX_ETH_MAC_FRAME_FILTER_HMC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_FRAME_FILTER_Bits.HMC */
+#define IFX_ETH_MAC_FRAME_FILTER_HMC_OFF (2u)
+
+/** \brief Length for Ifx_ETH_MAC_FRAME_FILTER_Bits.HPF */
+#define IFX_ETH_MAC_FRAME_FILTER_HPF_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_FRAME_FILTER_Bits.HPF */
+#define IFX_ETH_MAC_FRAME_FILTER_HPF_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_FRAME_FILTER_Bits.HPF */
+#define IFX_ETH_MAC_FRAME_FILTER_HPF_OFF (10u)
+
+/** \brief Length for Ifx_ETH_MAC_FRAME_FILTER_Bits.HUC */
+#define IFX_ETH_MAC_FRAME_FILTER_HUC_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_FRAME_FILTER_Bits.HUC */
+#define IFX_ETH_MAC_FRAME_FILTER_HUC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_FRAME_FILTER_Bits.HUC */
+#define IFX_ETH_MAC_FRAME_FILTER_HUC_OFF (1u)
+
+/** \brief Length for Ifx_ETH_MAC_FRAME_FILTER_Bits.IPFE */
+#define IFX_ETH_MAC_FRAME_FILTER_IPFE_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_FRAME_FILTER_Bits.IPFE */
+#define IFX_ETH_MAC_FRAME_FILTER_IPFE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_FRAME_FILTER_Bits.IPFE */
+#define IFX_ETH_MAC_FRAME_FILTER_IPFE_OFF (20u)
+
+/** \brief Length for Ifx_ETH_MAC_FRAME_FILTER_Bits.PCF */
+#define IFX_ETH_MAC_FRAME_FILTER_PCF_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_MAC_FRAME_FILTER_Bits.PCF */
+#define IFX_ETH_MAC_FRAME_FILTER_PCF_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_MAC_FRAME_FILTER_Bits.PCF */
+#define IFX_ETH_MAC_FRAME_FILTER_PCF_OFF (6u)
+
+/** \brief Length for Ifx_ETH_MAC_FRAME_FILTER_Bits.PM */
+#define IFX_ETH_MAC_FRAME_FILTER_PM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_FRAME_FILTER_Bits.PM */
+#define IFX_ETH_MAC_FRAME_FILTER_PM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_FRAME_FILTER_Bits.PM */
+#define IFX_ETH_MAC_FRAME_FILTER_PM_OFF (4u)
+
+/** \brief Length for Ifx_ETH_MAC_FRAME_FILTER_Bits.PR */
+#define IFX_ETH_MAC_FRAME_FILTER_PR_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_FRAME_FILTER_Bits.PR */
+#define IFX_ETH_MAC_FRAME_FILTER_PR_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_FRAME_FILTER_Bits.PR */
+#define IFX_ETH_MAC_FRAME_FILTER_PR_OFF (0u)
+
+/** \brief Length for Ifx_ETH_MAC_FRAME_FILTER_Bits.RA */
+#define IFX_ETH_MAC_FRAME_FILTER_RA_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_FRAME_FILTER_Bits.RA */
+#define IFX_ETH_MAC_FRAME_FILTER_RA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_FRAME_FILTER_Bits.RA */
+#define IFX_ETH_MAC_FRAME_FILTER_RA_OFF (31u)
+
+/** \brief Length for Ifx_ETH_MAC_FRAME_FILTER_Bits.SAF */
+#define IFX_ETH_MAC_FRAME_FILTER_SAF_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_FRAME_FILTER_Bits.SAF */
+#define IFX_ETH_MAC_FRAME_FILTER_SAF_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_FRAME_FILTER_Bits.SAF */
+#define IFX_ETH_MAC_FRAME_FILTER_SAF_OFF (9u)
+
+/** \brief Length for Ifx_ETH_MAC_FRAME_FILTER_Bits.SAIF */
+#define IFX_ETH_MAC_FRAME_FILTER_SAIF_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_FRAME_FILTER_Bits.SAIF */
+#define IFX_ETH_MAC_FRAME_FILTER_SAIF_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_FRAME_FILTER_Bits.SAIF */
+#define IFX_ETH_MAC_FRAME_FILTER_SAIF_OFF (8u)
+
+/** \brief Length for Ifx_ETH_MAC_FRAME_FILTER_Bits.VTFE */
+#define IFX_ETH_MAC_FRAME_FILTER_VTFE_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MAC_FRAME_FILTER_Bits.VTFE */
+#define IFX_ETH_MAC_FRAME_FILTER_VTFE_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MAC_FRAME_FILTER_Bits.VTFE */
+#define IFX_ETH_MAC_FRAME_FILTER_VTFE_OFF (16u)
+
+/** \brief Length for
+ * Ifx_ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_Bits.MISCNTOVF */
+#define IFX_ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_LEN (1u)
+
+/** \brief Mask for
+ * Ifx_ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_Bits.MISCNTOVF */
+#define IFX_ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_MSK (0x1u)
+
+/** \brief Offset for
+ * Ifx_ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_Bits.MISCNTOVF */
+#define IFX_ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_OFF (16u)
+
+/** \brief Length for
+ * Ifx_ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_Bits.MISFRMCNT */
+#define IFX_ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_LEN (16u)
+
+/** \brief Mask for
+ * Ifx_ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_Bits.MISFRMCNT */
+#define IFX_ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_MSK (0xffffu)
+
+/** \brief Offset for
+ * Ifx_ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_Bits.MISFRMCNT */
+#define IFX_ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_OFF (0u)
+
+/** \brief Length for
+ * Ifx_ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_Bits.OVFCNTOVF */
+#define IFX_ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_LEN (1u)
+
+/** \brief Mask for
+ * Ifx_ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_Bits.OVFCNTOVF */
+#define IFX_ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_MSK (0x1u)
+
+/** \brief Offset for
+ * Ifx_ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_Bits.OVFCNTOVF */
+#define IFX_ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_OFF (28u)
+
+/** \brief Length for
+ * Ifx_ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_Bits.OVFFRMCNT */
+#define IFX_ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_LEN (11u)
+
+/** \brief Mask for
+ * Ifx_ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_Bits.OVFFRMCNT */
+#define IFX_ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_MSK (0x7ffu)
+
+/** \brief Offset for
+ * Ifx_ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_Bits.OVFFRMCNT */
+#define IFX_ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_OFF (17u)
+
+/** \brief Length for Ifx_ETH_MMC_CONTROL_Bits.CNTFREEZ */
+#define IFX_ETH_MMC_CONTROL_CNTFREEZ_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_CONTROL_Bits.CNTFREEZ */
+#define IFX_ETH_MMC_CONTROL_CNTFREEZ_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_CONTROL_Bits.CNTFREEZ */
+#define IFX_ETH_MMC_CONTROL_CNTFREEZ_OFF (3u)
+
+/** \brief Length for Ifx_ETH_MMC_CONTROL_Bits.CNTPRST */
+#define IFX_ETH_MMC_CONTROL_CNTPRST_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_CONTROL_Bits.CNTPRST */
+#define IFX_ETH_MMC_CONTROL_CNTPRST_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_CONTROL_Bits.CNTPRST */
+#define IFX_ETH_MMC_CONTROL_CNTPRST_OFF (4u)
+
+/** \brief Length for Ifx_ETH_MMC_CONTROL_Bits.CNTPRSTLVL */
+#define IFX_ETH_MMC_CONTROL_CNTPRSTLVL_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_CONTROL_Bits.CNTPRSTLVL */
+#define IFX_ETH_MMC_CONTROL_CNTPRSTLVL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_CONTROL_Bits.CNTPRSTLVL */
+#define IFX_ETH_MMC_CONTROL_CNTPRSTLVL_OFF (5u)
+
+/** \brief Length for Ifx_ETH_MMC_CONTROL_Bits.CNTRST */
+#define IFX_ETH_MMC_CONTROL_CNTRST_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_CONTROL_Bits.CNTRST */
+#define IFX_ETH_MMC_CONTROL_CNTRST_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_CONTROL_Bits.CNTRST */
+#define IFX_ETH_MMC_CONTROL_CNTRST_OFF (0u)
+
+/** \brief Length for Ifx_ETH_MMC_CONTROL_Bits.CNTSTOPRO */
+#define IFX_ETH_MMC_CONTROL_CNTSTOPRO_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_CONTROL_Bits.CNTSTOPRO */
+#define IFX_ETH_MMC_CONTROL_CNTSTOPRO_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_CONTROL_Bits.CNTSTOPRO */
+#define IFX_ETH_MMC_CONTROL_CNTSTOPRO_OFF (1u)
+
+/** \brief Length for Ifx_ETH_MMC_CONTROL_Bits.RSTONRD */
+#define IFX_ETH_MMC_CONTROL_RSTONRD_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_CONTROL_Bits.RSTONRD */
+#define IFX_ETH_MMC_CONTROL_RSTONRD_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_CONTROL_Bits.RSTONRD */
+#define IFX_ETH_MMC_CONTROL_RSTONRD_OFF (2u)
+
+/** \brief Length for Ifx_ETH_MMC_CONTROL_Bits.UCDBC */
+#define IFX_ETH_MMC_CONTROL_UCDBC_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_CONTROL_Bits.UCDBC */
+#define IFX_ETH_MMC_CONTROL_UCDBC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_CONTROL_Bits.UCDBC */
+#define IFX_ETH_MMC_CONTROL_UCDBC_OFF (8u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXICMPERFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXICMPERFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXICMPERFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM_OFF (13u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXICMPEROIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXICMPEROIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXICMPEROIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM_OFF (29u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXICMPGFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXICMPGFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXICMPGFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM_OFF (12u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXICMPGOIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXICMPGOIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXICMPGOIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM_OFF (28u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV4FRAGFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV4FRAGFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV4FRAGFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM_OFF (3u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV4FRAGOIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV4FRAGOIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV4FRAGOIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM_OFF (19u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV4GFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV4GFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV4GFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM_OFF (0u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV4GOIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV4GOIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV4GOIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM_OFF (16u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV4HERFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV4HERFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV4HERFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM_OFF (1u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV4HEROIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV4HEROIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV4HEROIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM_OFF (17u)
+
+/** \brief Length for
+ * Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV4NOPAYFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV4NOPAYFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM_MSK (0x1u)
+
+/** \brief Offset for
+ * Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV4NOPAYFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM_OFF (2u)
+
+/** \brief Length for
+ * Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV4NOPAYOIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV4NOPAYOIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM_MSK (0x1u)
+
+/** \brief Offset for
+ * Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV4NOPAYOIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM_OFF (18u)
+
+/** \brief Length for
+ * Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV4UDSBLFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV4UDSBLFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM_MSK (0x1u)
+
+/** \brief Offset for
+ * Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV4UDSBLFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM_OFF (4u)
+
+/** \brief Length for
+ * Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV4UDSBLOIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV4UDSBLOIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM_MSK (0x1u)
+
+/** \brief Offset for
+ * Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV4UDSBLOIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM_OFF (20u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV6GFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV6GFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV6GFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM_OFF (5u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV6GOIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV6GOIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV6GOIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM_OFF (21u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV6HERFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV6HERFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV6HERFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM_OFF (6u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV6HEROIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV6HEROIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV6HEROIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM_OFF (22u)
+
+/** \brief Length for
+ * Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV6NOPAYFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV6NOPAYFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM_MSK (0x1u)
+
+/** \brief Offset for
+ * Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV6NOPAYFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM_OFF (7u)
+
+/** \brief Length for
+ * Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV6NOPAYOIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV6NOPAYOIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM_MSK (0x1u)
+
+/** \brief Offset for
+ * Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXIPV6NOPAYOIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM_OFF (23u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXTCPERFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXTCPERFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXTCPERFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM_OFF (11u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXTCPEROIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXTCPEROIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXTCPEROIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM_OFF (27u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXTCPGFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXTCPGFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXTCPGFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM_OFF (10u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXTCPGOIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXTCPGOIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXTCPGOIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM_OFF (26u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXUDPERFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXUDPERFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXUDPERFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM_OFF (9u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXUDPEROIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXUDPEROIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXUDPEROIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM_OFF (25u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXUDPGFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXUDPGFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXUDPGFIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM_OFF (8u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXUDPGOIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXUDPGOIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits.RXUDPGOIM */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM_OFF (24u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXICMPERFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXICMPERFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXICMPERFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS_OFF (13u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXICMPEROIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXICMPEROIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXICMPEROIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS_OFF (29u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXICMPGFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXICMPGFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXICMPGFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS_OFF (12u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXICMPGOIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXICMPGOIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXICMPGOIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS_OFF (28u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV4FRAGFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV4FRAGFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV4FRAGFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS_OFF (3u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV4FRAGOIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV4FRAGOIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV4FRAGOIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS_OFF (19u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV4GFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV4GFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV4GFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS_OFF (0u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV4GOIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV4GOIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV4GOIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS_OFF (16u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV4HERFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV4HERFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV4HERFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS_OFF (1u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV4HEROIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV4HEROIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV4HEROIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS_OFF (17u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV4NOPAYFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV4NOPAYFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV4NOPAYFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS_OFF (2u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV4NOPAYOIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV4NOPAYOIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV4NOPAYOIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS_OFF (18u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV4UDSBLFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV4UDSBLFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV4UDSBLFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS_OFF (4u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV4UDSBLOIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV4UDSBLOIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV4UDSBLOIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS_OFF (20u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV6GFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV6GFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV6GFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS_OFF (5u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV6GOIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV6GOIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV6GOIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS_OFF (21u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV6HERFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV6HERFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV6HERFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS_OFF (6u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV6HEROIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV6HEROIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV6HEROIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS_OFF (22u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV6NOPAYFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV6NOPAYFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV6NOPAYFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS_OFF (7u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV6NOPAYOIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV6NOPAYOIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXIPV6NOPAYOIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS_OFF (23u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXTCPERFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXTCPERFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXTCPERFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS_OFF (11u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXTCPEROIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXTCPEROIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXTCPEROIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS_OFF (27u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXTCPGFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXTCPGFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXTCPGFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS_OFF (10u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXTCPGOIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXTCPGOIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXTCPGOIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS_OFF (26u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXUDPERFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXUDPERFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXUDPERFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS_OFF (9u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXUDPEROIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXUDPEROIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXUDPEROIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS_OFF (25u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXUDPGFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXUDPGFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXUDPGFIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS_OFF (8u)
+
+/** \brief Length for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXUDPGOIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXUDPGOIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits.RXUDPGOIS */
+#define IFX_ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS_OFF (24u)
+
+/** \brief Length for
+ * Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RX1024TMAXOCTGBFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RX1024TMAXOCTGBFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM_MSK (0x1u)
+
+/** \brief Offset for
+ * Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RX1024TMAXOCTGBFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM_OFF (16u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RX128T255OCTGBFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RX128T255OCTGBFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RX128T255OCTGBFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM_OFF (13u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RX256T511OCTGBFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RX256T511OCTGBFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RX256T511OCTGBFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM_OFF (14u)
+
+/** \brief Length for
+ * Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RX512T1023OCTGBFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RX512T1023OCTGBFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM_MSK (0x1u)
+
+/** \brief Offset for
+ * Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RX512T1023OCTGBFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM_OFF (15u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RX64OCTGBFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RX64OCTGBFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RX64OCTGBFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM_OFF (11u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RX65T127OCTGBFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RX65T127OCTGBFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RX65T127OCTGBFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM_OFF (12u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXALGNERFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXALGNERFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXALGNERFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM_OFF (6u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXBCGFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXBCGFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXBCGFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM_OFF (3u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXCRCERFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXCRCERFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXCRCERFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM_OFF (5u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXCTRLFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXCTRLFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXCTRLFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM_OFF (25u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXFOVFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXFOVFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXFOVFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM_OFF (21u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXGBFRMIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXGBFRMIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXGBFRMIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM_OFF (0u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXGBOCTIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXGBOCTIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXGBOCTIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM_OFF (1u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXGOCTIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXGOCTIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXGOCTIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM_OFF (2u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXJABERFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXJABERFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXJABERFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM_OFF (8u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXLENERFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXLENERFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXLENERFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM_OFF (18u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXMCGFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXMCGFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXMCGFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM_OFF (4u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXORANGEFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXORANGEFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXORANGEFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM_OFF (19u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXOSIZEGFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXOSIZEGFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXOSIZEGFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM_OFF (10u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXPAUSFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXPAUSFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXPAUSFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM_OFF (20u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXRCVERRFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXRCVERRFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXRCVERRFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM_OFF (24u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXRUNTFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXRUNTFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXRUNTFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM_OFF (7u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXUCGFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXUCGFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXUCGFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM_OFF (17u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXUSIZEGFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXUSIZEGFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXUSIZEGFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM_OFF (9u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXVLANGBFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXVLANGBFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXVLANGBFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM_OFF (22u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXWDOGFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXWDOGFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits.RXWDOGFIM */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM_OFF (23u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RX1024TMAXOCTGBFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RX1024TMAXOCTGBFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RX1024TMAXOCTGBFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_OFF (16u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RX128T255OCTGBFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RX128T255OCTGBFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RX128T255OCTGBFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_OFF (13u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RX256T511OCTGBFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RX256T511OCTGBFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RX256T511OCTGBFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_OFF (14u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RX512T1023OCTGBFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RX512T1023OCTGBFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RX512T1023OCTGBFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_OFF (15u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RX64OCTGBFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RX64OCTGBFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RX64OCTGBFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_OFF (11u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RX65T127OCTGBFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RX65T127OCTGBFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RX65T127OCTGBFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_OFF (12u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXALGNERFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXALGNERFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXALGNERFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXALGNERFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXALGNERFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXALGNERFIS_OFF (6u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXBCGFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXBCGFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXBCGFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXBCGFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXBCGFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXBCGFIS_OFF (3u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXCRCERFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXCRCERFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXCRCERFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXCRCERFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXCRCERFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXCRCERFIS_OFF (5u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXCTRLFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXCTRLFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXCTRLFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXCTRLFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXCTRLFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXCTRLFIS_OFF (25u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXFOVFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXFOVFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXFOVFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXFOVFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXFOVFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXFOVFIS_OFF (21u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXGBFRMIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXGBFRMIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXGBFRMIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXGBFRMIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXGBFRMIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXGBFRMIS_OFF (0u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXGBOCTIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXGBOCTIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXGBOCTIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXGBOCTIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXGBOCTIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXGBOCTIS_OFF (1u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXGOCTIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXGOCTIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXGOCTIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXGOCTIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXGOCTIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXGOCTIS_OFF (2u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXJABERFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXJABERFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXJABERFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXJABERFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXJABERFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXJABERFIS_OFF (8u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXLENERFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXLENERFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXLENERFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXLENERFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXLENERFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXLENERFIS_OFF (18u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXMCGFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXMCGFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXMCGFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXMCGFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXMCGFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXMCGFIS_OFF (4u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXORANGEFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXORANGEFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXORANGEFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXORANGEFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXORANGEFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXORANGEFIS_OFF (19u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXOSIZEGFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXOSIZEGFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXOSIZEGFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_OFF (10u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXPAUSFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXPAUSFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXPAUSFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXPAUSFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXPAUSFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXPAUSFIS_OFF (20u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXRCVERRFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXRCVERRFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXRCVERRFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS_OFF (24u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXRUNTFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXRUNTFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXRUNTFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXRUNTFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXRUNTFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXRUNTFIS_OFF (7u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXUCGFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXUCGFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXUCGFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXUCGFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXUCGFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXUCGFIS_OFF (17u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXUSIZEGFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXUSIZEGFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXUSIZEGFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_OFF (9u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXVLANGBFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXVLANGBFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXVLANGBFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_OFF (22u)
+
+/** \brief Length for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXWDOGFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXWDOGFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXWDOGFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXWDOGFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits.RXWDOGFIS */
+#define IFX_ETH_MMC_RECEIVE_INTERRUPT_RXWDOGFIS_OFF (23u)
+
+/** \brief Length for
+ * Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TX1024TMAXOCTGBFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TX1024TMAXOCTGBFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM_MSK (0x1u)
+
+/** \brief Offset for
+ * Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TX1024TMAXOCTGBFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM_OFF (9u)
+
+/** \brief Length for
+ * Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TX128T255OCTGBFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TX128T255OCTGBFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM_MSK (0x1u)
+
+/** \brief Offset for
+ * Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TX128T255OCTGBFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM_OFF (6u)
+
+/** \brief Length for
+ * Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TX256T511OCTGBFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TX256T511OCTGBFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM_MSK (0x1u)
+
+/** \brief Offset for
+ * Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TX256T511OCTGBFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM_OFF (7u)
+
+/** \brief Length for
+ * Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TX512T1023OCTGBFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TX512T1023OCTGBFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM_MSK (0x1u)
+
+/** \brief Offset for
+ * Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TX512T1023OCTGBFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM_OFF (8u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TX64OCTGBFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TX64OCTGBFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TX64OCTGBFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM_OFF (4u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TX65T127OCTGBFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TX65T127OCTGBFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TX65T127OCTGBFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM_OFF (5u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXBCGBFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXBCGBFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXBCGBFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM_OFF (12u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXBCGFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXBCGFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXBCGFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM_OFF (2u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXCARERFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXCARERFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXCARERFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM_OFF (19u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXDEFFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXDEFFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXDEFFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM_OFF (16u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXEXCOLFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXEXCOLFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXEXCOLFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM_OFF (18u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXEXDEFFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXEXDEFFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXEXDEFFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM_OFF (22u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXGBFRMIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXGBFRMIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXGBFRMIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM_OFF (1u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXGBOCTIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXGBOCTIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXGBOCTIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM_OFF (0u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXGFRMIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXGFRMIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXGFRMIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM_OFF (21u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXGOCTIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXGOCTIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXGOCTIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM_OFF (20u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXLATCOLFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXLATCOLFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXLATCOLFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM_OFF (17u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXMCGBFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXMCGBFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXMCGBFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM_OFF (11u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXMCGFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXMCGFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXMCGFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM_OFF (3u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXMCOLGFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXMCOLGFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXMCOLGFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM_OFF (15u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXOSIZEGFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXOSIZEGFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXOSIZEGFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM_OFF (25u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXPAUSFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXPAUSFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXPAUSFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM_OFF (23u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXSCOLGFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXSCOLGFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXSCOLGFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM_OFF (14u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXUCGBFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXUCGBFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXUCGBFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM_OFF (10u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXUFLOWERFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXUFLOWERFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXUFLOWERFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM_OFF (13u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXVLANGFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXVLANGFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits.TXVLANGFIM */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM_OFF (24u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TX1024TMAXOCTGBFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TX1024TMAXOCTGBFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TX1024TMAXOCTGBFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_OFF (9u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TX128T255OCTGBFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TX128T255OCTGBFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TX128T255OCTGBFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_OFF (6u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TX256T511OCTGBFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TX256T511OCTGBFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TX256T511OCTGBFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_OFF (7u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TX512T1023OCTGBFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TX512T1023OCTGBFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TX512T1023OCTGBFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_OFF (8u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TX64OCTGBFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TX64OCTGBFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TX64OCTGBFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_OFF (4u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TX65T127OCTGBFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TX65T127OCTGBFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TX65T127OCTGBFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_OFF (5u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXBCGBFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXBCGBFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXBCGBFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_OFF (12u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXBCGFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXBCGFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXBCGFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXBCGFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXBCGFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXBCGFIS_OFF (2u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXCARERFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXCARERFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXCARERFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXCARERFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXCARERFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXCARERFIS_OFF (19u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXDEFFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXDEFFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXDEFFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXDEFFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXDEFFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXDEFFIS_OFF (16u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXEXCOLFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXEXCOLFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXEXCOLFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS_OFF (18u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXEXDEFFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXEXDEFFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXEXDEFFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS_OFF (22u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXGBFRMIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXGBFRMIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXGBFRMIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_OFF (1u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXGBOCTIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXGBOCTIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXGBOCTIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_OFF (0u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXGFRMIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXGFRMIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXGFRMIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXGFRMIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXGFRMIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXGFRMIS_OFF (21u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXGOCTIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXGOCTIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXGOCTIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXGOCTIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXGOCTIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXGOCTIS_OFF (20u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXLATCOLFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXLATCOLFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXLATCOLFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS_OFF (17u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXMCGBFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXMCGBFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXMCGBFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_OFF (11u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXMCGFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXMCGFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXMCGFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXMCGFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXMCGFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXMCGFIS_OFF (3u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXMCOLGFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXMCOLGFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXMCOLGFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS_OFF (15u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXOSIZEGFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXOSIZEGFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXOSIZEGFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS_OFF (25u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXPAUSFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXPAUSFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXPAUSFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_OFF (23u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXSCOLGFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXSCOLGFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXSCOLGFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS_OFF (14u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXUCGBFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXUCGBFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXUCGBFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_OFF (10u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXUFLOWERFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXUFLOWERFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXUFLOWERFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_OFF (13u)
+
+/** \brief Length for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXVLANGFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXVLANGFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits.TXVLANGFIS */
+#define IFX_ETH_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_OFF (24u)
+
+/** \brief Length for Ifx_ETH_OPERATION_MODE_Bits.DFF */
+#define IFX_ETH_OPERATION_MODE_DFF_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_OPERATION_MODE_Bits.DFF */
+#define IFX_ETH_OPERATION_MODE_DFF_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_OPERATION_MODE_Bits.DFF */
+#define IFX_ETH_OPERATION_MODE_DFF_OFF (24u)
+
+/** \brief Length for Ifx_ETH_OPERATION_MODE_Bits.DT */
+#define IFX_ETH_OPERATION_MODE_DT_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_OPERATION_MODE_Bits.DT */
+#define IFX_ETH_OPERATION_MODE_DT_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_OPERATION_MODE_Bits.DT */
+#define IFX_ETH_OPERATION_MODE_DT_OFF (26u)
+
+/** \brief Length for Ifx_ETH_OPERATION_MODE_Bits.EFC */
+#define IFX_ETH_OPERATION_MODE_EFC_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_OPERATION_MODE_Bits.EFC */
+#define IFX_ETH_OPERATION_MODE_EFC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_OPERATION_MODE_Bits.EFC */
+#define IFX_ETH_OPERATION_MODE_EFC_OFF (8u)
+
+/** \brief Length for Ifx_ETH_OPERATION_MODE_Bits.FEF */
+#define IFX_ETH_OPERATION_MODE_FEF_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_OPERATION_MODE_Bits.FEF */
+#define IFX_ETH_OPERATION_MODE_FEF_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_OPERATION_MODE_Bits.FEF */
+#define IFX_ETH_OPERATION_MODE_FEF_OFF (7u)
+
+/** \brief Length for Ifx_ETH_OPERATION_MODE_Bits.FTF */
+#define IFX_ETH_OPERATION_MODE_FTF_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_OPERATION_MODE_Bits.FTF */
+#define IFX_ETH_OPERATION_MODE_FTF_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_OPERATION_MODE_Bits.FTF */
+#define IFX_ETH_OPERATION_MODE_FTF_OFF (20u)
+
+/** \brief Length for Ifx_ETH_OPERATION_MODE_Bits.FUF */
+#define IFX_ETH_OPERATION_MODE_FUF_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_OPERATION_MODE_Bits.FUF */
+#define IFX_ETH_OPERATION_MODE_FUF_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_OPERATION_MODE_Bits.FUF */
+#define IFX_ETH_OPERATION_MODE_FUF_OFF (6u)
+
+/** \brief Length for Ifx_ETH_OPERATION_MODE_Bits.OSF */
+#define IFX_ETH_OPERATION_MODE_OSF_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_OPERATION_MODE_Bits.OSF */
+#define IFX_ETH_OPERATION_MODE_OSF_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_OPERATION_MODE_Bits.OSF */
+#define IFX_ETH_OPERATION_MODE_OSF_OFF (2u)
+
+/** \brief Length for Ifx_ETH_OPERATION_MODE_Bits.RFA_2 */
+#define IFX_ETH_OPERATION_MODE_RFA_2_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_OPERATION_MODE_Bits.RFA_2 */
+#define IFX_ETH_OPERATION_MODE_RFA_2_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_OPERATION_MODE_Bits.RFA_2 */
+#define IFX_ETH_OPERATION_MODE_RFA_2_OFF (23u)
+
+/** \brief Length for Ifx_ETH_OPERATION_MODE_Bits.RFA */
+#define IFX_ETH_OPERATION_MODE_RFA_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_OPERATION_MODE_Bits.RFA */
+#define IFX_ETH_OPERATION_MODE_RFA_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_OPERATION_MODE_Bits.RFA */
+#define IFX_ETH_OPERATION_MODE_RFA_OFF (9u)
+
+/** \brief Length for Ifx_ETH_OPERATION_MODE_Bits.RFD_2 */
+#define IFX_ETH_OPERATION_MODE_RFD_2_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_OPERATION_MODE_Bits.RFD_2 */
+#define IFX_ETH_OPERATION_MODE_RFD_2_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_OPERATION_MODE_Bits.RFD_2 */
+#define IFX_ETH_OPERATION_MODE_RFD_2_OFF (22u)
+
+/** \brief Length for Ifx_ETH_OPERATION_MODE_Bits.RFD */
+#define IFX_ETH_OPERATION_MODE_RFD_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_OPERATION_MODE_Bits.RFD */
+#define IFX_ETH_OPERATION_MODE_RFD_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_OPERATION_MODE_Bits.RFD */
+#define IFX_ETH_OPERATION_MODE_RFD_OFF (11u)
+
+/** \brief Length for Ifx_ETH_OPERATION_MODE_Bits.RSF */
+#define IFX_ETH_OPERATION_MODE_RSF_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_OPERATION_MODE_Bits.RSF */
+#define IFX_ETH_OPERATION_MODE_RSF_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_OPERATION_MODE_Bits.RSF */
+#define IFX_ETH_OPERATION_MODE_RSF_OFF (25u)
+
+/** \brief Length for Ifx_ETH_OPERATION_MODE_Bits.RTC */
+#define IFX_ETH_OPERATION_MODE_RTC_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_OPERATION_MODE_Bits.RTC */
+#define IFX_ETH_OPERATION_MODE_RTC_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_OPERATION_MODE_Bits.RTC */
+#define IFX_ETH_OPERATION_MODE_RTC_OFF (3u)
+
+/** \brief Length for Ifx_ETH_OPERATION_MODE_Bits.SR */
+#define IFX_ETH_OPERATION_MODE_SR_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_OPERATION_MODE_Bits.SR */
+#define IFX_ETH_OPERATION_MODE_SR_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_OPERATION_MODE_Bits.SR */
+#define IFX_ETH_OPERATION_MODE_SR_OFF (1u)
+
+/** \brief Length for Ifx_ETH_OPERATION_MODE_Bits.ST */
+#define IFX_ETH_OPERATION_MODE_ST_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_OPERATION_MODE_Bits.ST */
+#define IFX_ETH_OPERATION_MODE_ST_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_OPERATION_MODE_Bits.ST */
+#define IFX_ETH_OPERATION_MODE_ST_OFF (13u)
+
+/** \brief Length for Ifx_ETH_OPERATION_MODE_Bits.TSF */
+#define IFX_ETH_OPERATION_MODE_TSF_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_OPERATION_MODE_Bits.TSF */
+#define IFX_ETH_OPERATION_MODE_TSF_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_OPERATION_MODE_Bits.TSF */
+#define IFX_ETH_OPERATION_MODE_TSF_OFF (21u)
+
+/** \brief Length for Ifx_ETH_OPERATION_MODE_Bits.TTC */
+#define IFX_ETH_OPERATION_MODE_TTC_LEN (3u)
+
+/** \brief Mask for Ifx_ETH_OPERATION_MODE_Bits.TTC */
+#define IFX_ETH_OPERATION_MODE_TTC_MSK (0x7u)
+
+/** \brief Offset for Ifx_ETH_OPERATION_MODE_Bits.TTC */
+#define IFX_ETH_OPERATION_MODE_TTC_OFF (14u)
+
+/** \brief Length for Ifx_ETH_PMT_CONTROL_STATUS_Bits.GLBLUCAST */
+#define IFX_ETH_PMT_CONTROL_STATUS_GLBLUCAST_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_PMT_CONTROL_STATUS_Bits.GLBLUCAST */
+#define IFX_ETH_PMT_CONTROL_STATUS_GLBLUCAST_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_PMT_CONTROL_STATUS_Bits.GLBLUCAST */
+#define IFX_ETH_PMT_CONTROL_STATUS_GLBLUCAST_OFF (9u)
+
+/** \brief Length for Ifx_ETH_PMT_CONTROL_STATUS_Bits.MGKPKTEN */
+#define IFX_ETH_PMT_CONTROL_STATUS_MGKPKTEN_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_PMT_CONTROL_STATUS_Bits.MGKPKTEN */
+#define IFX_ETH_PMT_CONTROL_STATUS_MGKPKTEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_PMT_CONTROL_STATUS_Bits.MGKPKTEN */
+#define IFX_ETH_PMT_CONTROL_STATUS_MGKPKTEN_OFF (1u)
+
+/** \brief Length for Ifx_ETH_PMT_CONTROL_STATUS_Bits.MGKPRCVD */
+#define IFX_ETH_PMT_CONTROL_STATUS_MGKPRCVD_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_PMT_CONTROL_STATUS_Bits.MGKPRCVD */
+#define IFX_ETH_PMT_CONTROL_STATUS_MGKPRCVD_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_PMT_CONTROL_STATUS_Bits.MGKPRCVD */
+#define IFX_ETH_PMT_CONTROL_STATUS_MGKPRCVD_OFF (5u)
+
+/** \brief Length for Ifx_ETH_PMT_CONTROL_STATUS_Bits.PWRDWN */
+#define IFX_ETH_PMT_CONTROL_STATUS_PWRDWN_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_PMT_CONTROL_STATUS_Bits.PWRDWN */
+#define IFX_ETH_PMT_CONTROL_STATUS_PWRDWN_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_PMT_CONTROL_STATUS_Bits.PWRDWN */
+#define IFX_ETH_PMT_CONTROL_STATUS_PWRDWN_OFF (0u)
+
+/** \brief Length for Ifx_ETH_PMT_CONTROL_STATUS_Bits.RWKFILTRST */
+#define IFX_ETH_PMT_CONTROL_STATUS_RWKFILTRST_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_PMT_CONTROL_STATUS_Bits.RWKFILTRST */
+#define IFX_ETH_PMT_CONTROL_STATUS_RWKFILTRST_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_PMT_CONTROL_STATUS_Bits.RWKFILTRST */
+#define IFX_ETH_PMT_CONTROL_STATUS_RWKFILTRST_OFF (31u)
+
+/** \brief Length for Ifx_ETH_PMT_CONTROL_STATUS_Bits.RWKPKTEN */
+#define IFX_ETH_PMT_CONTROL_STATUS_RWKPKTEN_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_PMT_CONTROL_STATUS_Bits.RWKPKTEN */
+#define IFX_ETH_PMT_CONTROL_STATUS_RWKPKTEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_PMT_CONTROL_STATUS_Bits.RWKPKTEN */
+#define IFX_ETH_PMT_CONTROL_STATUS_RWKPKTEN_OFF (2u)
+
+/** \brief Length for Ifx_ETH_PMT_CONTROL_STATUS_Bits.RWKPRCVD */
+#define IFX_ETH_PMT_CONTROL_STATUS_RWKPRCVD_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_PMT_CONTROL_STATUS_Bits.RWKPRCVD */
+#define IFX_ETH_PMT_CONTROL_STATUS_RWKPRCVD_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_PMT_CONTROL_STATUS_Bits.RWKPRCVD */
+#define IFX_ETH_PMT_CONTROL_STATUS_RWKPRCVD_OFF (6u)
+
+/** \brief Length for Ifx_ETH_PPS_CONTROL_Bits.PPSCMD1 */
+#define IFX_ETH_PPS_CONTROL_PPSCMD1_LEN (3u)
+
+/** \brief Mask for Ifx_ETH_PPS_CONTROL_Bits.PPSCMD1 */
+#define IFX_ETH_PPS_CONTROL_PPSCMD1_MSK (0x7u)
+
+/** \brief Offset for Ifx_ETH_PPS_CONTROL_Bits.PPSCMD1 */
+#define IFX_ETH_PPS_CONTROL_PPSCMD1_OFF (8u)
+
+/** \brief Length for Ifx_ETH_PPS_CONTROL_Bits.PPSCMD2 */
+#define IFX_ETH_PPS_CONTROL_PPSCMD2_LEN (3u)
+
+/** \brief Mask for Ifx_ETH_PPS_CONTROL_Bits.PPSCMD2 */
+#define IFX_ETH_PPS_CONTROL_PPSCMD2_MSK (0x7u)
+
+/** \brief Offset for Ifx_ETH_PPS_CONTROL_Bits.PPSCMD2 */
+#define IFX_ETH_PPS_CONTROL_PPSCMD2_OFF (16u)
+
+/** \brief Length for Ifx_ETH_PPS_CONTROL_Bits.PPSCMD3 */
+#define IFX_ETH_PPS_CONTROL_PPSCMD3_LEN (3u)
+
+/** \brief Mask for Ifx_ETH_PPS_CONTROL_Bits.PPSCMD3 */
+#define IFX_ETH_PPS_CONTROL_PPSCMD3_MSK (0x7u)
+
+/** \brief Offset for Ifx_ETH_PPS_CONTROL_Bits.PPSCMD3 */
+#define IFX_ETH_PPS_CONTROL_PPSCMD3_OFF (24u)
+
+/** \brief Length for Ifx_ETH_PPS_CONTROL_Bits.PPSCTRL_PPSCMD */
+#define IFX_ETH_PPS_CONTROL_PPSCTRL_PPSCMD_LEN (4u)
+
+/** \brief Mask for Ifx_ETH_PPS_CONTROL_Bits.PPSCTRL_PPSCMD */
+#define IFX_ETH_PPS_CONTROL_PPSCTRL_PPSCMD_MSK (0xfu)
+
+/** \brief Offset for Ifx_ETH_PPS_CONTROL_Bits.PPSCTRL_PPSCMD */
+#define IFX_ETH_PPS_CONTROL_PPSCTRL_PPSCMD_OFF (0u)
+
+/** \brief Length for Ifx_ETH_PPS_CONTROL_Bits.PPSEN0 */
+#define IFX_ETH_PPS_CONTROL_PPSEN0_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_PPS_CONTROL_Bits.PPSEN0 */
+#define IFX_ETH_PPS_CONTROL_PPSEN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_PPS_CONTROL_Bits.PPSEN0 */
+#define IFX_ETH_PPS_CONTROL_PPSEN0_OFF (4u)
+
+/** \brief Length for Ifx_ETH_PPS_CONTROL_Bits.TRGTMODSEL0 */
+#define IFX_ETH_PPS_CONTROL_TRGTMODSEL0_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_PPS_CONTROL_Bits.TRGTMODSEL0 */
+#define IFX_ETH_PPS_CONTROL_TRGTMODSEL0_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_PPS_CONTROL_Bits.TRGTMODSEL0 */
+#define IFX_ETH_PPS_CONTROL_TRGTMODSEL0_OFF (5u)
+
+/** \brief Length for Ifx_ETH_PPS_CONTROL_Bits.TRGTMODSEL1 */
+#define IFX_ETH_PPS_CONTROL_TRGTMODSEL1_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_PPS_CONTROL_Bits.TRGTMODSEL1 */
+#define IFX_ETH_PPS_CONTROL_TRGTMODSEL1_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_PPS_CONTROL_Bits.TRGTMODSEL1 */
+#define IFX_ETH_PPS_CONTROL_TRGTMODSEL1_OFF (13u)
+
+/** \brief Length for Ifx_ETH_PPS_CONTROL_Bits.TRGTMODSEL2 */
+#define IFX_ETH_PPS_CONTROL_TRGTMODSEL2_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_PPS_CONTROL_Bits.TRGTMODSEL2 */
+#define IFX_ETH_PPS_CONTROL_TRGTMODSEL2_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_PPS_CONTROL_Bits.TRGTMODSEL2 */
+#define IFX_ETH_PPS_CONTROL_TRGTMODSEL2_OFF (21u)
+
+/** \brief Length for Ifx_ETH_PPS_CONTROL_Bits.TRGTMODSEL3 */
+#define IFX_ETH_PPS_CONTROL_TRGTMODSEL3_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_PPS_CONTROL_Bits.TRGTMODSEL3 */
+#define IFX_ETH_PPS_CONTROL_TRGTMODSEL3_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_PPS_CONTROL_Bits.TRGTMODSEL3 */
+#define IFX_ETH_PPS_CONTROL_TRGTMODSEL3_OFF (29u)
+
+/** \brief Length for Ifx_ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_Bits.RDESLA */
+#define IFX_ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_LEN (30u)
+
+/** \brief Mask for Ifx_ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_Bits.RDESLA */
+#define IFX_ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_MSK (0x3fffffffu)
+
+/** \brief Offset for Ifx_ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_Bits.RDESLA */
+#define IFX_ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_OFF (2u)
+
+/** \brief Length for Ifx_ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_Bits.RIWT */
+#define IFX_ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_LEN (8u)
+
+/** \brief Mask for Ifx_ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_Bits.RIWT */
+#define IFX_ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_MSK (0xffu)
+
+/** \brief Offset for Ifx_ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_Bits.RIWT */
+#define IFX_ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RECEIVE_POLL_DEMAND_Bits.RPD */
+#define IFX_ETH_RECEIVE_POLL_DEMAND_RPD_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RECEIVE_POLL_DEMAND_Bits.RPD */
+#define IFX_ETH_RECEIVE_POLL_DEMAND_RPD_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RECEIVE_POLL_DEMAND_Bits.RPD */
+#define IFX_ETH_RECEIVE_POLL_DEMAND_RPD_OFF (0u)
+
+/** \brief Length for Ifx_ETH_REMOTE_WAKE_UP_FRAME_FILTER_Bits.WKUPFRMFTR */
+#define IFX_ETH_REMOTE_WAKE_UP_FRAME_FILTER_WKUPFRMFTR_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_REMOTE_WAKE_UP_FRAME_FILTER_Bits.WKUPFRMFTR */
+#define IFX_ETH_REMOTE_WAKE_UP_FRAME_FILTER_WKUPFRMFTR_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_REMOTE_WAKE_UP_FRAME_FILTER_Bits.WKUPFRMFTR */
+#define IFX_ETH_REMOTE_WAKE_UP_FRAME_FILTER_WKUPFRMFTR_OFF (0u)
+
+/** \brief Length for
+ * Ifx_ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_Bits.RX1024_MAXOCTGB */
+#define IFX_ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_RX1024_MAXOCTGB_LEN (32u)
+
+/** \brief Mask for
+ * Ifx_ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_Bits.RX1024_MAXOCTGB */
+#define IFX_ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_RX1024_MAXOCTGB_MSK (0xffffffffu)
+
+/** \brief Offset for
+ * Ifx_ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_Bits.RX1024_MAXOCTGB */
+#define IFX_ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_RX1024_MAXOCTGB_OFF (0u)
+
+/** \brief Length for
+ * Ifx_ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_Bits.RX128_255OCTGB */
+#define IFX_ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_RX128_255OCTGB_LEN (32u)
+
+/** \brief Mask for
+ * Ifx_ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_Bits.RX128_255OCTGB */
+#define IFX_ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_RX128_255OCTGB_MSK (0xffffffffu)
+
+/** \brief Offset for
+ * Ifx_ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_Bits.RX128_255OCTGB */
+#define IFX_ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_RX128_255OCTGB_OFF (0u)
+
+/** \brief Length for
+ * Ifx_ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_Bits.RX256_511OCTGB */
+#define IFX_ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_RX256_511OCTGB_LEN (32u)
+
+/** \brief Mask for
+ * Ifx_ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_Bits.RX256_511OCTGB */
+#define IFX_ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_RX256_511OCTGB_MSK (0xffffffffu)
+
+/** \brief Offset for
+ * Ifx_ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_Bits.RX256_511OCTGB */
+#define IFX_ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_RX256_511OCTGB_OFF (0u)
+
+/** \brief Length for
+ * Ifx_ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_Bits.RX512_1023OCTGB */
+#define IFX_ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_RX512_1023OCTGB_LEN (32u)
+
+/** \brief Mask for
+ * Ifx_ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_Bits.RX512_1023OCTGB */
+#define IFX_ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_RX512_1023OCTGB_MSK (0xffffffffu)
+
+/** \brief Offset for
+ * Ifx_ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_Bits.RX512_1023OCTGB */
+#define IFX_ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_RX512_1023OCTGB_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RX_64OCTETS_FRAMES_GOOD_BAD_Bits.RX64OCTGB */
+#define IFX_ETH_RX_64OCTETS_FRAMES_GOOD_BAD_RX64OCTGB_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RX_64OCTETS_FRAMES_GOOD_BAD_Bits.RX64OCTGB */
+#define IFX_ETH_RX_64OCTETS_FRAMES_GOOD_BAD_RX64OCTGB_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RX_64OCTETS_FRAMES_GOOD_BAD_Bits.RX64OCTGB */
+#define IFX_ETH_RX_64OCTETS_FRAMES_GOOD_BAD_RX64OCTGB_OFF (0u)
+
+/** \brief Length for
+ * Ifx_ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_Bits.RX65_127OCTGB */
+#define IFX_ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_RX65_127OCTGB_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_Bits.RX65_127OCTGB */
+#define IFX_ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_RX65_127OCTGB_MSK (0xffffffffu)
+
+/** \brief Offset for
+ * Ifx_ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_Bits.RX65_127OCTGB */
+#define IFX_ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_RX65_127OCTGB_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RX_ALIGNMENT_ERROR_FRAMES_Bits.RXALGNERR */
+#define IFX_ETH_RX_ALIGNMENT_ERROR_FRAMES_RXALGNERR_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RX_ALIGNMENT_ERROR_FRAMES_Bits.RXALGNERR */
+#define IFX_ETH_RX_ALIGNMENT_ERROR_FRAMES_RXALGNERR_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RX_ALIGNMENT_ERROR_FRAMES_Bits.RXALGNERR */
+#define IFX_ETH_RX_ALIGNMENT_ERROR_FRAMES_RXALGNERR_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RX_BROADCAST_FRAMES_GOOD_Bits.RXBCASTG */
+#define IFX_ETH_RX_BROADCAST_FRAMES_GOOD_RXBCASTG_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RX_BROADCAST_FRAMES_GOOD_Bits.RXBCASTG */
+#define IFX_ETH_RX_BROADCAST_FRAMES_GOOD_RXBCASTG_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RX_BROADCAST_FRAMES_GOOD_Bits.RXBCASTG */
+#define IFX_ETH_RX_BROADCAST_FRAMES_GOOD_RXBCASTG_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RX_CONTROL_FRAMES_GOOD_Bits.RXCTRLG */
+#define IFX_ETH_RX_CONTROL_FRAMES_GOOD_RXCTRLG_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RX_CONTROL_FRAMES_GOOD_Bits.RXCTRLG */
+#define IFX_ETH_RX_CONTROL_FRAMES_GOOD_RXCTRLG_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RX_CONTROL_FRAMES_GOOD_Bits.RXCTRLG */
+#define IFX_ETH_RX_CONTROL_FRAMES_GOOD_RXCTRLG_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RX_CRC_ERROR_FRAMES_Bits.RXCRCERR */
+#define IFX_ETH_RX_CRC_ERROR_FRAMES_RXCRCERR_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RX_CRC_ERROR_FRAMES_Bits.RXCRCERR */
+#define IFX_ETH_RX_CRC_ERROR_FRAMES_RXCRCERR_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RX_CRC_ERROR_FRAMES_Bits.RXCRCERR */
+#define IFX_ETH_RX_CRC_ERROR_FRAMES_RXCRCERR_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RX_FIFO_OVERFLOW_FRAMES_Bits.RXFIFOOVFL */
+#define IFX_ETH_RX_FIFO_OVERFLOW_FRAMES_RXFIFOOVFL_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RX_FIFO_OVERFLOW_FRAMES_Bits.RXFIFOOVFL */
+#define IFX_ETH_RX_FIFO_OVERFLOW_FRAMES_RXFIFOOVFL_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RX_FIFO_OVERFLOW_FRAMES_Bits.RXFIFOOVFL */
+#define IFX_ETH_RX_FIFO_OVERFLOW_FRAMES_RXFIFOOVFL_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RX_FRAMES_COUNT_GOOD_BAD_Bits.RXFRMGB */
+#define IFX_ETH_RX_FRAMES_COUNT_GOOD_BAD_RXFRMGB_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RX_FRAMES_COUNT_GOOD_BAD_Bits.RXFRMGB */
+#define IFX_ETH_RX_FRAMES_COUNT_GOOD_BAD_RXFRMGB_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RX_FRAMES_COUNT_GOOD_BAD_Bits.RXFRMGB */
+#define IFX_ETH_RX_FRAMES_COUNT_GOOD_BAD_RXFRMGB_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RX_JABBER_ERROR_FRAMES_Bits.RXJABERR */
+#define IFX_ETH_RX_JABBER_ERROR_FRAMES_RXJABERR_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RX_JABBER_ERROR_FRAMES_Bits.RXJABERR */
+#define IFX_ETH_RX_JABBER_ERROR_FRAMES_RXJABERR_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RX_JABBER_ERROR_FRAMES_Bits.RXJABERR */
+#define IFX_ETH_RX_JABBER_ERROR_FRAMES_RXJABERR_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RX_LENGTH_ERROR_FRAMES_Bits.RXLENERR */
+#define IFX_ETH_RX_LENGTH_ERROR_FRAMES_RXLENERR_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RX_LENGTH_ERROR_FRAMES_Bits.RXLENERR */
+#define IFX_ETH_RX_LENGTH_ERROR_FRAMES_RXLENERR_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RX_LENGTH_ERROR_FRAMES_Bits.RXLENERR */
+#define IFX_ETH_RX_LENGTH_ERROR_FRAMES_RXLENERR_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RX_MULTICAST_FRAMES_GOOD_Bits.RXMCASTG */
+#define IFX_ETH_RX_MULTICAST_FRAMES_GOOD_RXMCASTG_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RX_MULTICAST_FRAMES_GOOD_Bits.RXMCASTG */
+#define IFX_ETH_RX_MULTICAST_FRAMES_GOOD_RXMCASTG_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RX_MULTICAST_FRAMES_GOOD_Bits.RXMCASTG */
+#define IFX_ETH_RX_MULTICAST_FRAMES_GOOD_RXMCASTG_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RX_OCTET_COUNT_GOOD_BAD_Bits.RXOCTGB */
+#define IFX_ETH_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RX_OCTET_COUNT_GOOD_BAD_Bits.RXOCTGB */
+#define IFX_ETH_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RX_OCTET_COUNT_GOOD_BAD_Bits.RXOCTGB */
+#define IFX_ETH_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RX_OCTET_COUNT_GOOD_Bits.RXOCTG */
+#define IFX_ETH_RX_OCTET_COUNT_GOOD_RXOCTG_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RX_OCTET_COUNT_GOOD_Bits.RXOCTG */
+#define IFX_ETH_RX_OCTET_COUNT_GOOD_RXOCTG_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RX_OCTET_COUNT_GOOD_Bits.RXOCTG */
+#define IFX_ETH_RX_OCTET_COUNT_GOOD_RXOCTG_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_Bits.RXOUTOFRNG */
+#define IFX_ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_RXOUTOFRNG_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_Bits.RXOUTOFRNG */
+#define IFX_ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_RXOUTOFRNG_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_Bits.RXOUTOFRNG */
+#define IFX_ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_RXOUTOFRNG_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RX_OVERSIZE_FRAMES_GOOD_Bits.RXOVERSZG */
+#define IFX_ETH_RX_OVERSIZE_FRAMES_GOOD_RXOVERSZG_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RX_OVERSIZE_FRAMES_GOOD_Bits.RXOVERSZG */
+#define IFX_ETH_RX_OVERSIZE_FRAMES_GOOD_RXOVERSZG_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RX_OVERSIZE_FRAMES_GOOD_Bits.RXOVERSZG */
+#define IFX_ETH_RX_OVERSIZE_FRAMES_GOOD_RXOVERSZG_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RX_PAUSE_FRAMES_Bits.RXPAUSEFRM */
+#define IFX_ETH_RX_PAUSE_FRAMES_RXPAUSEFRM_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RX_PAUSE_FRAMES_Bits.RXPAUSEFRM */
+#define IFX_ETH_RX_PAUSE_FRAMES_RXPAUSEFRM_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RX_PAUSE_FRAMES_Bits.RXPAUSEFRM */
+#define IFX_ETH_RX_PAUSE_FRAMES_RXPAUSEFRM_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RX_RECEIVE_ERROR_FRAMES_Bits.RXRCVERR */
+#define IFX_ETH_RX_RECEIVE_ERROR_FRAMES_RXRCVERR_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RX_RECEIVE_ERROR_FRAMES_Bits.RXRCVERR */
+#define IFX_ETH_RX_RECEIVE_ERROR_FRAMES_RXRCVERR_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RX_RECEIVE_ERROR_FRAMES_Bits.RXRCVERR */
+#define IFX_ETH_RX_RECEIVE_ERROR_FRAMES_RXRCVERR_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RX_RUNT_ERROR_FRAMES_Bits.RXRUNTERR */
+#define IFX_ETH_RX_RUNT_ERROR_FRAMES_RXRUNTERR_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RX_RUNT_ERROR_FRAMES_Bits.RXRUNTERR */
+#define IFX_ETH_RX_RUNT_ERROR_FRAMES_RXRUNTERR_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RX_RUNT_ERROR_FRAMES_Bits.RXRUNTERR */
+#define IFX_ETH_RX_RUNT_ERROR_FRAMES_RXRUNTERR_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RX_UNDERSIZE_FRAMES_GOOD_Bits.RXUNDERSZG */
+#define IFX_ETH_RX_UNDERSIZE_FRAMES_GOOD_RXUNDERSZG_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RX_UNDERSIZE_FRAMES_GOOD_Bits.RXUNDERSZG */
+#define IFX_ETH_RX_UNDERSIZE_FRAMES_GOOD_RXUNDERSZG_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RX_UNDERSIZE_FRAMES_GOOD_Bits.RXUNDERSZG */
+#define IFX_ETH_RX_UNDERSIZE_FRAMES_GOOD_RXUNDERSZG_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RX_UNICAST_FRAMES_GOOD_Bits.RXUCASTG */
+#define IFX_ETH_RX_UNICAST_FRAMES_GOOD_RXUCASTG_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RX_UNICAST_FRAMES_GOOD_Bits.RXUCASTG */
+#define IFX_ETH_RX_UNICAST_FRAMES_GOOD_RXUCASTG_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RX_UNICAST_FRAMES_GOOD_Bits.RXUCASTG */
+#define IFX_ETH_RX_UNICAST_FRAMES_GOOD_RXUCASTG_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RX_VLAN_FRAMES_GOOD_BAD_Bits.RXVLANFRGB */
+#define IFX_ETH_RX_VLAN_FRAMES_GOOD_BAD_RXVLANFRGB_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RX_VLAN_FRAMES_GOOD_BAD_Bits.RXVLANFRGB */
+#define IFX_ETH_RX_VLAN_FRAMES_GOOD_BAD_RXVLANFRGB_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RX_VLAN_FRAMES_GOOD_BAD_Bits.RXVLANFRGB */
+#define IFX_ETH_RX_VLAN_FRAMES_GOOD_BAD_RXVLANFRGB_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RX_WATCHDOG_ERROR_FRAMES_Bits.RXWDGERR */
+#define IFX_ETH_RX_WATCHDOG_ERROR_FRAMES_RXWDGERR_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RX_WATCHDOG_ERROR_FRAMES_Bits.RXWDGERR */
+#define IFX_ETH_RX_WATCHDOG_ERROR_FRAMES_RXWDGERR_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RX_WATCHDOG_ERROR_FRAMES_Bits.RXWDGERR */
+#define IFX_ETH_RX_WATCHDOG_ERROR_FRAMES_RXWDGERR_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RXICMP_ERROR_FRAMES_Bits.RXICMPERRFRM */
+#define IFX_ETH_RXICMP_ERROR_FRAMES_RXICMPERRFRM_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RXICMP_ERROR_FRAMES_Bits.RXICMPERRFRM */
+#define IFX_ETH_RXICMP_ERROR_FRAMES_RXICMPERRFRM_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RXICMP_ERROR_FRAMES_Bits.RXICMPERRFRM */
+#define IFX_ETH_RXICMP_ERROR_FRAMES_RXICMPERRFRM_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RXICMP_ERROR_OCTETS_Bits.RXICMPERROCT */
+#define IFX_ETH_RXICMP_ERROR_OCTETS_RXICMPERROCT_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RXICMP_ERROR_OCTETS_Bits.RXICMPERROCT */
+#define IFX_ETH_RXICMP_ERROR_OCTETS_RXICMPERROCT_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RXICMP_ERROR_OCTETS_Bits.RXICMPERROCT */
+#define IFX_ETH_RXICMP_ERROR_OCTETS_RXICMPERROCT_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RXICMP_GOOD_FRAMES_Bits.RXICMPGDFRM */
+#define IFX_ETH_RXICMP_GOOD_FRAMES_RXICMPGDFRM_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RXICMP_GOOD_FRAMES_Bits.RXICMPGDFRM */
+#define IFX_ETH_RXICMP_GOOD_FRAMES_RXICMPGDFRM_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RXICMP_GOOD_FRAMES_Bits.RXICMPGDFRM */
+#define IFX_ETH_RXICMP_GOOD_FRAMES_RXICMPGDFRM_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RXICMP_GOOD_OCTETS_Bits.RXICMPGDOCT */
+#define IFX_ETH_RXICMP_GOOD_OCTETS_RXICMPGDOCT_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RXICMP_GOOD_OCTETS_Bits.RXICMPGDOCT */
+#define IFX_ETH_RXICMP_GOOD_OCTETS_RXICMPGDOCT_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RXICMP_GOOD_OCTETS_Bits.RXICMPGDOCT */
+#define IFX_ETH_RXICMP_GOOD_OCTETS_RXICMPGDOCT_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RXIPV4_FRAGMENTED_FRAMES_Bits.RXIPV4FRAGFRM */
+#define IFX_ETH_RXIPV4_FRAGMENTED_FRAMES_RXIPV4FRAGFRM_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RXIPV4_FRAGMENTED_FRAMES_Bits.RXIPV4FRAGFRM */
+#define IFX_ETH_RXIPV4_FRAGMENTED_FRAMES_RXIPV4FRAGFRM_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RXIPV4_FRAGMENTED_FRAMES_Bits.RXIPV4FRAGFRM */
+#define IFX_ETH_RXIPV4_FRAGMENTED_FRAMES_RXIPV4FRAGFRM_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RXIPV4_FRAGMENTED_OCTETS_Bits.RXIPV4FRAGOCT */
+#define IFX_ETH_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RXIPV4_FRAGMENTED_OCTETS_Bits.RXIPV4FRAGOCT */
+#define IFX_ETH_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RXIPV4_FRAGMENTED_OCTETS_Bits.RXIPV4FRAGOCT */
+#define IFX_ETH_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RXIPV4_GOOD_FRAMES_Bits.RXIPV4GDFRM */
+#define IFX_ETH_RXIPV4_GOOD_FRAMES_RXIPV4GDFRM_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RXIPV4_GOOD_FRAMES_Bits.RXIPV4GDFRM */
+#define IFX_ETH_RXIPV4_GOOD_FRAMES_RXIPV4GDFRM_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RXIPV4_GOOD_FRAMES_Bits.RXIPV4GDFRM */
+#define IFX_ETH_RXIPV4_GOOD_FRAMES_RXIPV4GDFRM_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RXIPV4_GOOD_OCTETS_Bits.RXIPV4GDOCT */
+#define IFX_ETH_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RXIPV4_GOOD_OCTETS_Bits.RXIPV4GDOCT */
+#define IFX_ETH_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RXIPV4_GOOD_OCTETS_Bits.RXIPV4GDOCT */
+#define IFX_ETH_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RXIPV4_HEADER_ERROR_FRAMES_Bits.RXIPV4HDRERRFRM */
+#define IFX_ETH_RXIPV4_HEADER_ERROR_FRAMES_RXIPV4HDRERRFRM_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RXIPV4_HEADER_ERROR_FRAMES_Bits.RXIPV4HDRERRFRM */
+#define IFX_ETH_RXIPV4_HEADER_ERROR_FRAMES_RXIPV4HDRERRFRM_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RXIPV4_HEADER_ERROR_FRAMES_Bits.RXIPV4HDRERRFRM */
+#define IFX_ETH_RXIPV4_HEADER_ERROR_FRAMES_RXIPV4HDRERRFRM_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RXIPV4_HEADER_ERROR_OCTETS_Bits.RXIPV4HDRERROCT */
+#define IFX_ETH_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RXIPV4_HEADER_ERROR_OCTETS_Bits.RXIPV4HDRERROCT */
+#define IFX_ETH_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RXIPV4_HEADER_ERROR_OCTETS_Bits.RXIPV4HDRERROCT */
+#define IFX_ETH_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RXIPV4_NO_PAYLOAD_FRAMES_Bits.RXIPV4NOPAYFRM */
+#define IFX_ETH_RXIPV4_NO_PAYLOAD_FRAMES_RXIPV4NOPAYFRM_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RXIPV4_NO_PAYLOAD_FRAMES_Bits.RXIPV4NOPAYFRM */
+#define IFX_ETH_RXIPV4_NO_PAYLOAD_FRAMES_RXIPV4NOPAYFRM_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RXIPV4_NO_PAYLOAD_FRAMES_Bits.RXIPV4NOPAYFRM */
+#define IFX_ETH_RXIPV4_NO_PAYLOAD_FRAMES_RXIPV4NOPAYFRM_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RXIPV4_NO_PAYLOAD_OCTETS_Bits.RXIPV4NOPAYOCT */
+#define IFX_ETH_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RXIPV4_NO_PAYLOAD_OCTETS_Bits.RXIPV4NOPAYOCT */
+#define IFX_ETH_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RXIPV4_NO_PAYLOAD_OCTETS_Bits.RXIPV4NOPAYOCT */
+#define IFX_ETH_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_OFF (0u)
+
+/** \brief Length for
+ * Ifx_ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_Bits.RXIPV4UDSBLOCT */
+#define IFX_ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_LEN (32u)
+
+/** \brief Mask for
+ * Ifx_ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_Bits.RXIPV4UDSBLOCT */
+#define IFX_ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_MSK (0xffffffffu)
+
+/** \brief Offset for
+ * Ifx_ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_Bits.RXIPV4UDSBLOCT */
+#define IFX_ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_OFF (0u)
+
+/** \brief Length for
+ * Ifx_ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_Bits.RXIPV4UDSBLFRM */
+#define IFX_ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_RXIPV4UDSBLFRM_LEN (32u)
+
+/** \brief Mask for
+ * Ifx_ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_Bits.RXIPV4UDSBLFRM */
+#define IFX_ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_RXIPV4UDSBLFRM_MSK (0xffffffffu)
+
+/** \brief Offset for
+ * Ifx_ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_Bits.RXIPV4UDSBLFRM */
+#define IFX_ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_RXIPV4UDSBLFRM_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RXIPV6_GOOD_FRAMES_Bits.RXIPV6GDFRM */
+#define IFX_ETH_RXIPV6_GOOD_FRAMES_RXIPV6GDFRM_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RXIPV6_GOOD_FRAMES_Bits.RXIPV6GDFRM */
+#define IFX_ETH_RXIPV6_GOOD_FRAMES_RXIPV6GDFRM_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RXIPV6_GOOD_FRAMES_Bits.RXIPV6GDFRM */
+#define IFX_ETH_RXIPV6_GOOD_FRAMES_RXIPV6GDFRM_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RXIPV6_GOOD_OCTETS_Bits.RXIPV6GDOCT */
+#define IFX_ETH_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RXIPV6_GOOD_OCTETS_Bits.RXIPV6GDOCT */
+#define IFX_ETH_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RXIPV6_GOOD_OCTETS_Bits.RXIPV6GDOCT */
+#define IFX_ETH_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RXIPV6_HEADER_ERROR_FRAMES_Bits.RXIPV6HDRERRFRM */
+#define IFX_ETH_RXIPV6_HEADER_ERROR_FRAMES_RXIPV6HDRERRFRM_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RXIPV6_HEADER_ERROR_FRAMES_Bits.RXIPV6HDRERRFRM */
+#define IFX_ETH_RXIPV6_HEADER_ERROR_FRAMES_RXIPV6HDRERRFRM_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RXIPV6_HEADER_ERROR_FRAMES_Bits.RXIPV6HDRERRFRM */
+#define IFX_ETH_RXIPV6_HEADER_ERROR_FRAMES_RXIPV6HDRERRFRM_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RXIPV6_HEADER_ERROR_OCTETS_Bits.RXIPV6HDRERROCT */
+#define IFX_ETH_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RXIPV6_HEADER_ERROR_OCTETS_Bits.RXIPV6HDRERROCT */
+#define IFX_ETH_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RXIPV6_HEADER_ERROR_OCTETS_Bits.RXIPV6HDRERROCT */
+#define IFX_ETH_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RXIPV6_NO_PAYLOAD_FRAMES_Bits.RXIPV6NOPAYFRM */
+#define IFX_ETH_RXIPV6_NO_PAYLOAD_FRAMES_RXIPV6NOPAYFRM_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RXIPV6_NO_PAYLOAD_FRAMES_Bits.RXIPV6NOPAYFRM */
+#define IFX_ETH_RXIPV6_NO_PAYLOAD_FRAMES_RXIPV6NOPAYFRM_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RXIPV6_NO_PAYLOAD_FRAMES_Bits.RXIPV6NOPAYFRM */
+#define IFX_ETH_RXIPV6_NO_PAYLOAD_FRAMES_RXIPV6NOPAYFRM_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RXIPV6_NO_PAYLOAD_OCTETS_Bits.RXIPV6NOPAYOCT */
+#define IFX_ETH_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RXIPV6_NO_PAYLOAD_OCTETS_Bits.RXIPV6NOPAYOCT */
+#define IFX_ETH_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RXIPV6_NO_PAYLOAD_OCTETS_Bits.RXIPV6NOPAYOCT */
+#define IFX_ETH_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RXTCP_ERROR_FRAMES_Bits.RXTCPERRFRM */
+#define IFX_ETH_RXTCP_ERROR_FRAMES_RXTCPERRFRM_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RXTCP_ERROR_FRAMES_Bits.RXTCPERRFRM */
+#define IFX_ETH_RXTCP_ERROR_FRAMES_RXTCPERRFRM_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RXTCP_ERROR_FRAMES_Bits.RXTCPERRFRM */
+#define IFX_ETH_RXTCP_ERROR_FRAMES_RXTCPERRFRM_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RXTCP_ERROR_OCTETS_Bits.RXTCPERROCT */
+#define IFX_ETH_RXTCP_ERROR_OCTETS_RXTCPERROCT_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RXTCP_ERROR_OCTETS_Bits.RXTCPERROCT */
+#define IFX_ETH_RXTCP_ERROR_OCTETS_RXTCPERROCT_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RXTCP_ERROR_OCTETS_Bits.RXTCPERROCT */
+#define IFX_ETH_RXTCP_ERROR_OCTETS_RXTCPERROCT_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RXTCP_GOOD_FRAMES_Bits.RXTCPGDFRM */
+#define IFX_ETH_RXTCP_GOOD_FRAMES_RXTCPGDFRM_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RXTCP_GOOD_FRAMES_Bits.RXTCPGDFRM */
+#define IFX_ETH_RXTCP_GOOD_FRAMES_RXTCPGDFRM_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RXTCP_GOOD_FRAMES_Bits.RXTCPGDFRM */
+#define IFX_ETH_RXTCP_GOOD_FRAMES_RXTCPGDFRM_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RXTCP_GOOD_OCTETS_Bits.RXTCPGDOCT */
+#define IFX_ETH_RXTCP_GOOD_OCTETS_RXTCPGDOCT_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RXTCP_GOOD_OCTETS_Bits.RXTCPGDOCT */
+#define IFX_ETH_RXTCP_GOOD_OCTETS_RXTCPGDOCT_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RXTCP_GOOD_OCTETS_Bits.RXTCPGDOCT */
+#define IFX_ETH_RXTCP_GOOD_OCTETS_RXTCPGDOCT_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RXUDP_ERROR_FRAMES_Bits.RXUDPERRFRM */
+#define IFX_ETH_RXUDP_ERROR_FRAMES_RXUDPERRFRM_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RXUDP_ERROR_FRAMES_Bits.RXUDPERRFRM */
+#define IFX_ETH_RXUDP_ERROR_FRAMES_RXUDPERRFRM_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RXUDP_ERROR_FRAMES_Bits.RXUDPERRFRM */
+#define IFX_ETH_RXUDP_ERROR_FRAMES_RXUDPERRFRM_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RXUDP_ERROR_OCTETS_Bits.RXUDPERROCT */
+#define IFX_ETH_RXUDP_ERROR_OCTETS_RXUDPERROCT_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RXUDP_ERROR_OCTETS_Bits.RXUDPERROCT */
+#define IFX_ETH_RXUDP_ERROR_OCTETS_RXUDPERROCT_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RXUDP_ERROR_OCTETS_Bits.RXUDPERROCT */
+#define IFX_ETH_RXUDP_ERROR_OCTETS_RXUDPERROCT_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RXUDP_GOOD_FRAMES_Bits.RXUDPGDFRM */
+#define IFX_ETH_RXUDP_GOOD_FRAMES_RXUDPGDFRM_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RXUDP_GOOD_FRAMES_Bits.RXUDPGDFRM */
+#define IFX_ETH_RXUDP_GOOD_FRAMES_RXUDPGDFRM_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RXUDP_GOOD_FRAMES_Bits.RXUDPGDFRM */
+#define IFX_ETH_RXUDP_GOOD_FRAMES_RXUDPGDFRM_OFF (0u)
+
+/** \brief Length for Ifx_ETH_RXUDP_GOOD_OCTETS_Bits.RXUDPGDOCT */
+#define IFX_ETH_RXUDP_GOOD_OCTETS_RXUDPGDOCT_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_RXUDP_GOOD_OCTETS_Bits.RXUDPGDOCT */
+#define IFX_ETH_RXUDP_GOOD_OCTETS_RXUDPGDOCT_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_RXUDP_GOOD_OCTETS_Bits.RXUDPGDOCT */
+#define IFX_ETH_RXUDP_GOOD_OCTETS_RXUDPGDOCT_OFF (0u)
+
+/** \brief Length for Ifx_ETH_STATUS_Bits.AIS */
+#define IFX_ETH_STATUS_AIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_STATUS_Bits.AIS */
+#define IFX_ETH_STATUS_AIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_STATUS_Bits.AIS */
+#define IFX_ETH_STATUS_AIS_OFF (15u)
+
+/** \brief Length for Ifx_ETH_STATUS_Bits.EB */
+#define IFX_ETH_STATUS_EB_LEN (3u)
+
+/** \brief Mask for Ifx_ETH_STATUS_Bits.EB */
+#define IFX_ETH_STATUS_EB_MSK (0x7u)
+
+/** \brief Offset for Ifx_ETH_STATUS_Bits.EB */
+#define IFX_ETH_STATUS_EB_OFF (23u)
+
+/** \brief Length for Ifx_ETH_STATUS_Bits.ERI */
+#define IFX_ETH_STATUS_ERI_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_STATUS_Bits.ERI */
+#define IFX_ETH_STATUS_ERI_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_STATUS_Bits.ERI */
+#define IFX_ETH_STATUS_ERI_OFF (14u)
+
+/** \brief Length for Ifx_ETH_STATUS_Bits.ETI */
+#define IFX_ETH_STATUS_ETI_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_STATUS_Bits.ETI */
+#define IFX_ETH_STATUS_ETI_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_STATUS_Bits.ETI */
+#define IFX_ETH_STATUS_ETI_OFF (10u)
+
+/** \brief Length for Ifx_ETH_STATUS_Bits.FBI */
+#define IFX_ETH_STATUS_FBI_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_STATUS_Bits.FBI */
+#define IFX_ETH_STATUS_FBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_STATUS_Bits.FBI */
+#define IFX_ETH_STATUS_FBI_OFF (13u)
+
+/** \brief Length for Ifx_ETH_STATUS_Bits.GLI */
+#define IFX_ETH_STATUS_GLI_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_STATUS_Bits.GLI */
+#define IFX_ETH_STATUS_GLI_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_STATUS_Bits.GLI */
+#define IFX_ETH_STATUS_GLI_OFF (26u)
+
+/** \brief Length for Ifx_ETH_STATUS_Bits.GLPII */
+#define IFX_ETH_STATUS_GLPII_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_STATUS_Bits.GLPII */
+#define IFX_ETH_STATUS_GLPII_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_STATUS_Bits.GLPII */
+#define IFX_ETH_STATUS_GLPII_OFF (30u)
+
+/** \brief Length for Ifx_ETH_STATUS_Bits.GMI */
+#define IFX_ETH_STATUS_GMI_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_STATUS_Bits.GMI */
+#define IFX_ETH_STATUS_GMI_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_STATUS_Bits.GMI */
+#define IFX_ETH_STATUS_GMI_OFF (27u)
+
+/** \brief Length for Ifx_ETH_STATUS_Bits.GPI */
+#define IFX_ETH_STATUS_GPI_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_STATUS_Bits.GPI */
+#define IFX_ETH_STATUS_GPI_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_STATUS_Bits.GPI */
+#define IFX_ETH_STATUS_GPI_OFF (28u)
+
+/** \brief Length for Ifx_ETH_STATUS_Bits.NIS */
+#define IFX_ETH_STATUS_NIS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_STATUS_Bits.NIS */
+#define IFX_ETH_STATUS_NIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_STATUS_Bits.NIS */
+#define IFX_ETH_STATUS_NIS_OFF (16u)
+
+/** \brief Length for Ifx_ETH_STATUS_Bits.OVF */
+#define IFX_ETH_STATUS_OVF_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_STATUS_Bits.OVF */
+#define IFX_ETH_STATUS_OVF_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_STATUS_Bits.OVF */
+#define IFX_ETH_STATUS_OVF_OFF (4u)
+
+/** \brief Length for Ifx_ETH_STATUS_Bits.RI */
+#define IFX_ETH_STATUS_RI_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_STATUS_Bits.RI */
+#define IFX_ETH_STATUS_RI_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_STATUS_Bits.RI */
+#define IFX_ETH_STATUS_RI_OFF (6u)
+
+/** \brief Length for Ifx_ETH_STATUS_Bits.RPS */
+#define IFX_ETH_STATUS_RPS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_STATUS_Bits.RPS */
+#define IFX_ETH_STATUS_RPS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_STATUS_Bits.RPS */
+#define IFX_ETH_STATUS_RPS_OFF (8u)
+
+/** \brief Length for Ifx_ETH_STATUS_Bits.RS */
+#define IFX_ETH_STATUS_RS_LEN (3u)
+
+/** \brief Mask for Ifx_ETH_STATUS_Bits.RS */
+#define IFX_ETH_STATUS_RS_MSK (0x7u)
+
+/** \brief Offset for Ifx_ETH_STATUS_Bits.RS */
+#define IFX_ETH_STATUS_RS_OFF (17u)
+
+/** \brief Length for Ifx_ETH_STATUS_Bits.RU */
+#define IFX_ETH_STATUS_RU_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_STATUS_Bits.RU */
+#define IFX_ETH_STATUS_RU_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_STATUS_Bits.RU */
+#define IFX_ETH_STATUS_RU_OFF (7u)
+
+/** \brief Length for Ifx_ETH_STATUS_Bits.RWT */
+#define IFX_ETH_STATUS_RWT_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_STATUS_Bits.RWT */
+#define IFX_ETH_STATUS_RWT_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_STATUS_Bits.RWT */
+#define IFX_ETH_STATUS_RWT_OFF (9u)
+
+/** \brief Length for Ifx_ETH_STATUS_Bits.TI */
+#define IFX_ETH_STATUS_TI_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_STATUS_Bits.TI */
+#define IFX_ETH_STATUS_TI_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_STATUS_Bits.TI */
+#define IFX_ETH_STATUS_TI_OFF (0u)
+
+/** \brief Length for Ifx_ETH_STATUS_Bits.TJT */
+#define IFX_ETH_STATUS_TJT_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_STATUS_Bits.TJT */
+#define IFX_ETH_STATUS_TJT_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_STATUS_Bits.TJT */
+#define IFX_ETH_STATUS_TJT_OFF (3u)
+
+/** \brief Length for Ifx_ETH_STATUS_Bits.TPS */
+#define IFX_ETH_STATUS_TPS_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_STATUS_Bits.TPS */
+#define IFX_ETH_STATUS_TPS_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_STATUS_Bits.TPS */
+#define IFX_ETH_STATUS_TPS_OFF (1u)
+
+/** \brief Length for Ifx_ETH_STATUS_Bits.TS */
+#define IFX_ETH_STATUS_TS_LEN (3u)
+
+/** \brief Mask for Ifx_ETH_STATUS_Bits.TS */
+#define IFX_ETH_STATUS_TS_MSK (0x7u)
+
+/** \brief Offset for Ifx_ETH_STATUS_Bits.TS */
+#define IFX_ETH_STATUS_TS_OFF (20u)
+
+/** \brief Length for Ifx_ETH_STATUS_Bits.TTI */
+#define IFX_ETH_STATUS_TTI_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_STATUS_Bits.TTI */
+#define IFX_ETH_STATUS_TTI_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_STATUS_Bits.TTI */
+#define IFX_ETH_STATUS_TTI_OFF (29u)
+
+/** \brief Length for Ifx_ETH_STATUS_Bits.TU */
+#define IFX_ETH_STATUS_TU_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_STATUS_Bits.TU */
+#define IFX_ETH_STATUS_TU_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_STATUS_Bits.TU */
+#define IFX_ETH_STATUS_TU_OFF (2u)
+
+/** \brief Length for Ifx_ETH_STATUS_Bits.UNF */
+#define IFX_ETH_STATUS_UNF_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_STATUS_Bits.UNF */
+#define IFX_ETH_STATUS_UNF_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_STATUS_Bits.UNF */
+#define IFX_ETH_STATUS_UNF_OFF (5u)
+
+/** \brief Length for Ifx_ETH_SUB_SECOND_INCREMENT_Bits.SSINC */
+#define IFX_ETH_SUB_SECOND_INCREMENT_SSINC_LEN (8u)
+
+/** \brief Mask for Ifx_ETH_SUB_SECOND_INCREMENT_Bits.SSINC */
+#define IFX_ETH_SUB_SECOND_INCREMENT_SSINC_MSK (0xffu)
+
+/** \brief Offset for Ifx_ETH_SUB_SECOND_INCREMENT_Bits.SSINC */
+#define IFX_ETH_SUB_SECOND_INCREMENT_SSINC_OFF (0u)
+
+/** \brief Length for Ifx_ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_Bits.TSHWR */
+#define IFX_ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_LEN (16u)
+
+/** \brief Mask for Ifx_ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_Bits.TSHWR */
+#define IFX_ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MSK (0xffffu)
+
+/** \brief Offset for Ifx_ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_Bits.TSHWR */
+#define IFX_ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_OFF (0u)
+
+/** \brief Length for Ifx_ETH_SYSTEM_TIME_NANOSECONDS_Bits.TSSS */
+#define IFX_ETH_SYSTEM_TIME_NANOSECONDS_TSSS_LEN (31u)
+
+/** \brief Mask for Ifx_ETH_SYSTEM_TIME_NANOSECONDS_Bits.TSSS */
+#define IFX_ETH_SYSTEM_TIME_NANOSECONDS_TSSS_MSK (0x7fffffffu)
+
+/** \brief Offset for Ifx_ETH_SYSTEM_TIME_NANOSECONDS_Bits.TSSS */
+#define IFX_ETH_SYSTEM_TIME_NANOSECONDS_TSSS_OFF (0u)
+
+/** \brief Length for Ifx_ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_Bits.ADDSUB */
+#define IFX_ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_Bits.ADDSUB */
+#define IFX_ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_Bits.ADDSUB */
+#define IFX_ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_OFF (31u)
+
+/** \brief Length for Ifx_ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_Bits.TSSS */
+#define IFX_ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_LEN (31u)
+
+/** \brief Mask for Ifx_ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_Bits.TSSS */
+#define IFX_ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MSK (0x7fffffffu)
+
+/** \brief Offset for Ifx_ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_Bits.TSSS */
+#define IFX_ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_OFF (0u)
+
+/** \brief Length for Ifx_ETH_SYSTEM_TIME_SECONDS_Bits.TSS */
+#define IFX_ETH_SYSTEM_TIME_SECONDS_TSS_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_SYSTEM_TIME_SECONDS_Bits.TSS */
+#define IFX_ETH_SYSTEM_TIME_SECONDS_TSS_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_SYSTEM_TIME_SECONDS_Bits.TSS */
+#define IFX_ETH_SYSTEM_TIME_SECONDS_TSS_OFF (0u)
+
+/** \brief Length for Ifx_ETH_SYSTEM_TIME_SECONDS_UPDATE_Bits.TSS */
+#define IFX_ETH_SYSTEM_TIME_SECONDS_UPDATE_TSS_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_SYSTEM_TIME_SECONDS_UPDATE_Bits.TSS */
+#define IFX_ETH_SYSTEM_TIME_SECONDS_UPDATE_TSS_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_SYSTEM_TIME_SECONDS_UPDATE_Bits.TSS */
+#define IFX_ETH_SYSTEM_TIME_SECONDS_UPDATE_TSS_OFF (0u)
+
+/** \brief Length for Ifx_ETH_TARGET_TIME_NANOSECONDS_Bits.TRGTBUSY */
+#define IFX_ETH_TARGET_TIME_NANOSECONDS_TRGTBUSY_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TARGET_TIME_NANOSECONDS_Bits.TRGTBUSY */
+#define IFX_ETH_TARGET_TIME_NANOSECONDS_TRGTBUSY_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TARGET_TIME_NANOSECONDS_Bits.TRGTBUSY */
+#define IFX_ETH_TARGET_TIME_NANOSECONDS_TRGTBUSY_OFF (31u)
+
+/** \brief Length for Ifx_ETH_TARGET_TIME_NANOSECONDS_Bits.TTSLO */
+#define IFX_ETH_TARGET_TIME_NANOSECONDS_TTSLO_LEN (31u)
+
+/** \brief Mask for Ifx_ETH_TARGET_TIME_NANOSECONDS_Bits.TTSLO */
+#define IFX_ETH_TARGET_TIME_NANOSECONDS_TTSLO_MSK (0x7fffffffu)
+
+/** \brief Offset for Ifx_ETH_TARGET_TIME_NANOSECONDS_Bits.TTSLO */
+#define IFX_ETH_TARGET_TIME_NANOSECONDS_TTSLO_OFF (0u)
+
+/** \brief Length for Ifx_ETH_TARGET_TIME_SECONDS_Bits.TSTR */
+#define IFX_ETH_TARGET_TIME_SECONDS_TSTR_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_TARGET_TIME_SECONDS_Bits.TSTR */
+#define IFX_ETH_TARGET_TIME_SECONDS_TSTR_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_TARGET_TIME_SECONDS_Bits.TSTR */
+#define IFX_ETH_TARGET_TIME_SECONDS_TSTR_OFF (0u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_ADDEND_Bits.TSAR */
+#define IFX_ETH_TIMESTAMP_ADDEND_TSAR_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_ADDEND_Bits.TSAR */
+#define IFX_ETH_TIMESTAMP_ADDEND_TSAR_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_ADDEND_Bits.TSAR */
+#define IFX_ETH_TIMESTAMP_ADDEND_TSAR_OFF (0u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_CONTROL_Bits.ATSEN0 */
+#define IFX_ETH_TIMESTAMP_CONTROL_ATSEN0_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_CONTROL_Bits.ATSEN0 */
+#define IFX_ETH_TIMESTAMP_CONTROL_ATSEN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_CONTROL_Bits.ATSEN0 */
+#define IFX_ETH_TIMESTAMP_CONTROL_ATSEN0_OFF (25u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_CONTROL_Bits.ATSEN1 */
+#define IFX_ETH_TIMESTAMP_CONTROL_ATSEN1_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_CONTROL_Bits.ATSEN1 */
+#define IFX_ETH_TIMESTAMP_CONTROL_ATSEN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_CONTROL_Bits.ATSEN1 */
+#define IFX_ETH_TIMESTAMP_CONTROL_ATSEN1_OFF (26u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_CONTROL_Bits.ATSEN2 */
+#define IFX_ETH_TIMESTAMP_CONTROL_ATSEN2_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_CONTROL_Bits.ATSEN2 */
+#define IFX_ETH_TIMESTAMP_CONTROL_ATSEN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_CONTROL_Bits.ATSEN2 */
+#define IFX_ETH_TIMESTAMP_CONTROL_ATSEN2_OFF (27u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_CONTROL_Bits.ATSEN3 */
+#define IFX_ETH_TIMESTAMP_CONTROL_ATSEN3_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_CONTROL_Bits.ATSEN3 */
+#define IFX_ETH_TIMESTAMP_CONTROL_ATSEN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_CONTROL_Bits.ATSEN3 */
+#define IFX_ETH_TIMESTAMP_CONTROL_ATSEN3_OFF (28u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_CONTROL_Bits.ATSFC */
+#define IFX_ETH_TIMESTAMP_CONTROL_ATSFC_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_CONTROL_Bits.ATSFC */
+#define IFX_ETH_TIMESTAMP_CONTROL_ATSFC_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_CONTROL_Bits.ATSFC */
+#define IFX_ETH_TIMESTAMP_CONTROL_ATSFC_OFF (24u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_CONTROL_Bits.SNAPTYPSEL */
+#define IFX_ETH_TIMESTAMP_CONTROL_SNAPTYPSEL_LEN (2u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_CONTROL_Bits.SNAPTYPSEL */
+#define IFX_ETH_TIMESTAMP_CONTROL_SNAPTYPSEL_MSK (0x3u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_CONTROL_Bits.SNAPTYPSEL */
+#define IFX_ETH_TIMESTAMP_CONTROL_SNAPTYPSEL_OFF (16u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSADDREG */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSADDREG_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSADDREG */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSADDREG_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSADDREG */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSADDREG_OFF (5u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSCFUPDT */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSCFUPDT_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSCFUPDT */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSCFUPDT_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSCFUPDT */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSCFUPDT_OFF (1u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSCTRLSSR */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSCTRLSSR_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSCTRLSSR */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSCTRLSSR_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSCTRLSSR */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSCTRLSSR_OFF (9u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSENA */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSENA_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSENA */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSENA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSENA */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSENA_OFF (0u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSENALL */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSENALL_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSENALL */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSENALL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSENALL */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSENALL_OFF (8u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSENMACADDR */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSENMACADDR_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSENMACADDR */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSENMACADDR_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSENMACADDR */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSENMACADDR_OFF (18u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSEVNTENA */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSEVNTENA_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSEVNTENA */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSEVNTENA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSEVNTENA */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSEVNTENA_OFF (14u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSINIT */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSINIT_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSINIT */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSINIT_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSINIT */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSINIT_OFF (2u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSIPENA */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSIPENA_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSIPENA */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSIPENA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSIPENA */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSIPENA_OFF (11u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSIPV4ENA */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSIPV4ENA_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSIPV4ENA */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSIPV4ENA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSIPV4ENA */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSIPV4ENA_OFF (13u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSIPV6ENA */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSIPV6ENA_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSIPV6ENA */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSIPV6ENA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSIPV6ENA */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSIPV6ENA_OFF (12u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSMSTRENA */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSMSTRENA_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSMSTRENA */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSMSTRENA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSMSTRENA */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSMSTRENA_OFF (15u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSTRIG */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSTRIG_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSTRIG */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSTRIG_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSTRIG */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSTRIG_OFF (4u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSUPDT */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSUPDT_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSUPDT */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSUPDT_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSUPDT */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSUPDT_OFF (3u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSVER2ENA */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSVER2ENA_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSVER2ENA */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSVER2ENA_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_CONTROL_Bits.TSVER2ENA */
+#define IFX_ETH_TIMESTAMP_CONTROL_TSVER2ENA_OFF (10u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_STATUS_Bits.ATSNS */
+#define IFX_ETH_TIMESTAMP_STATUS_ATSNS_LEN (5u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_STATUS_Bits.ATSNS */
+#define IFX_ETH_TIMESTAMP_STATUS_ATSNS_MSK (0x1fu)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_STATUS_Bits.ATSNS */
+#define IFX_ETH_TIMESTAMP_STATUS_ATSNS_OFF (25u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_STATUS_Bits.ATSSTM */
+#define IFX_ETH_TIMESTAMP_STATUS_ATSSTM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_STATUS_Bits.ATSSTM */
+#define IFX_ETH_TIMESTAMP_STATUS_ATSSTM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_STATUS_Bits.ATSSTM */
+#define IFX_ETH_TIMESTAMP_STATUS_ATSSTM_OFF (24u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_STATUS_Bits.ATSSTN */
+#define IFX_ETH_TIMESTAMP_STATUS_ATSSTN_LEN (4u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_STATUS_Bits.ATSSTN */
+#define IFX_ETH_TIMESTAMP_STATUS_ATSSTN_MSK (0xfu)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_STATUS_Bits.ATSSTN */
+#define IFX_ETH_TIMESTAMP_STATUS_ATSSTN_OFF (16u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_STATUS_Bits.AUXTSTRIG */
+#define IFX_ETH_TIMESTAMP_STATUS_AUXTSTRIG_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_STATUS_Bits.AUXTSTRIG */
+#define IFX_ETH_TIMESTAMP_STATUS_AUXTSTRIG_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_STATUS_Bits.AUXTSTRIG */
+#define IFX_ETH_TIMESTAMP_STATUS_AUXTSTRIG_OFF (2u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_STATUS_Bits.TSSOVF */
+#define IFX_ETH_TIMESTAMP_STATUS_TSSOVF_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_STATUS_Bits.TSSOVF */
+#define IFX_ETH_TIMESTAMP_STATUS_TSSOVF_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_STATUS_Bits.TSSOVF */
+#define IFX_ETH_TIMESTAMP_STATUS_TSSOVF_OFF (0u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_STATUS_Bits.TSTARGT1 */
+#define IFX_ETH_TIMESTAMP_STATUS_TSTARGT1_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_STATUS_Bits.TSTARGT1 */
+#define IFX_ETH_TIMESTAMP_STATUS_TSTARGT1_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_STATUS_Bits.TSTARGT1 */
+#define IFX_ETH_TIMESTAMP_STATUS_TSTARGT1_OFF (4u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_STATUS_Bits.TSTARGT2 */
+#define IFX_ETH_TIMESTAMP_STATUS_TSTARGT2_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_STATUS_Bits.TSTARGT2 */
+#define IFX_ETH_TIMESTAMP_STATUS_TSTARGT2_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_STATUS_Bits.TSTARGT2 */
+#define IFX_ETH_TIMESTAMP_STATUS_TSTARGT2_OFF (6u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_STATUS_Bits.TSTARGT3 */
+#define IFX_ETH_TIMESTAMP_STATUS_TSTARGT3_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_STATUS_Bits.TSTARGT3 */
+#define IFX_ETH_TIMESTAMP_STATUS_TSTARGT3_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_STATUS_Bits.TSTARGT3 */
+#define IFX_ETH_TIMESTAMP_STATUS_TSTARGT3_OFF (8u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_STATUS_Bits.TSTARGT */
+#define IFX_ETH_TIMESTAMP_STATUS_TSTARGT_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_STATUS_Bits.TSTARGT */
+#define IFX_ETH_TIMESTAMP_STATUS_TSTARGT_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_STATUS_Bits.TSTARGT */
+#define IFX_ETH_TIMESTAMP_STATUS_TSTARGT_OFF (1u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_STATUS_Bits.TSTRGTERR1 */
+#define IFX_ETH_TIMESTAMP_STATUS_TSTRGTERR1_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_STATUS_Bits.TSTRGTERR1 */
+#define IFX_ETH_TIMESTAMP_STATUS_TSTRGTERR1_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_STATUS_Bits.TSTRGTERR1 */
+#define IFX_ETH_TIMESTAMP_STATUS_TSTRGTERR1_OFF (5u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_STATUS_Bits.TSTRGTERR2 */
+#define IFX_ETH_TIMESTAMP_STATUS_TSTRGTERR2_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_STATUS_Bits.TSTRGTERR2 */
+#define IFX_ETH_TIMESTAMP_STATUS_TSTRGTERR2_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_STATUS_Bits.TSTRGTERR2 */
+#define IFX_ETH_TIMESTAMP_STATUS_TSTRGTERR2_OFF (7u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_STATUS_Bits.TSTRGTERR3 */
+#define IFX_ETH_TIMESTAMP_STATUS_TSTRGTERR3_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_STATUS_Bits.TSTRGTERR3 */
+#define IFX_ETH_TIMESTAMP_STATUS_TSTRGTERR3_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_STATUS_Bits.TSTRGTERR3 */
+#define IFX_ETH_TIMESTAMP_STATUS_TSTRGTERR3_OFF (9u)
+
+/** \brief Length for Ifx_ETH_TIMESTAMP_STATUS_Bits.TSTRGTERR */
+#define IFX_ETH_TIMESTAMP_STATUS_TSTRGTERR_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_TIMESTAMP_STATUS_Bits.TSTRGTERR */
+#define IFX_ETH_TIMESTAMP_STATUS_TSTRGTERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_TIMESTAMP_STATUS_Bits.TSTRGTERR */
+#define IFX_ETH_TIMESTAMP_STATUS_TSTRGTERR_OFF (3u)
+
+/** \brief Length for Ifx_ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_Bits.TDESLA */
+#define IFX_ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_LEN (30u)
+
+/** \brief Mask for Ifx_ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_Bits.TDESLA */
+#define IFX_ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_MSK (0x3fffffffu)
+
+/** \brief Offset for Ifx_ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_Bits.TDESLA */
+#define IFX_ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_OFF (2u)
+
+/** \brief Length for Ifx_ETH_TRANSMIT_POLL_DEMAND_Bits.TPD */
+#define IFX_ETH_TRANSMIT_POLL_DEMAND_TPD_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_TRANSMIT_POLL_DEMAND_Bits.TPD */
+#define IFX_ETH_TRANSMIT_POLL_DEMAND_TPD_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_TRANSMIT_POLL_DEMAND_Bits.TPD */
+#define IFX_ETH_TRANSMIT_POLL_DEMAND_TPD_OFF (0u)
+
+/** \brief Length for
+ * Ifx_ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_Bits.TX1024_MAXOCTGB */
+#define IFX_ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_TX1024_MAXOCTGB_LEN (32u)
+
+/** \brief Mask for
+ * Ifx_ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_Bits.TX1024_MAXOCTGB */
+#define IFX_ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_TX1024_MAXOCTGB_MSK (0xffffffffu)
+
+/** \brief Offset for
+ * Ifx_ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_Bits.TX1024_MAXOCTGB */
+#define IFX_ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_TX1024_MAXOCTGB_OFF (0u)
+
+/** \brief Length for
+ * Ifx_ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_Bits.TX128_255OCTGB */
+#define IFX_ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_TX128_255OCTGB_LEN (32u)
+
+/** \brief Mask for
+ * Ifx_ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_Bits.TX128_255OCTGB */
+#define IFX_ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_TX128_255OCTGB_MSK (0xffffffffu)
+
+/** \brief Offset for
+ * Ifx_ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_Bits.TX128_255OCTGB */
+#define IFX_ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_TX128_255OCTGB_OFF (0u)
+
+/** \brief Length for
+ * Ifx_ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_Bits.TX256_511OCTGB */
+#define IFX_ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_TX256_511OCTGB_LEN (32u)
+
+/** \brief Mask for
+ * Ifx_ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_Bits.TX256_511OCTGB */
+#define IFX_ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_TX256_511OCTGB_MSK (0xffffffffu)
+
+/** \brief Offset for
+ * Ifx_ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_Bits.TX256_511OCTGB */
+#define IFX_ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_TX256_511OCTGB_OFF (0u)
+
+/** \brief Length for
+ * Ifx_ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_Bits.TX512_1023OCTGB */
+#define IFX_ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_TX512_1023OCTGB_LEN (32u)
+
+/** \brief Mask for
+ * Ifx_ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_Bits.TX512_1023OCTGB */
+#define IFX_ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_TX512_1023OCTGB_MSK (0xffffffffu)
+
+/** \brief Offset for
+ * Ifx_ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_Bits.TX512_1023OCTGB */
+#define IFX_ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_TX512_1023OCTGB_OFF (0u)
+
+/** \brief Length for Ifx_ETH_TX_64OCTETS_FRAMES_GOOD_BAD_Bits.TX64OCTGB */
+#define IFX_ETH_TX_64OCTETS_FRAMES_GOOD_BAD_TX64OCTGB_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_TX_64OCTETS_FRAMES_GOOD_BAD_Bits.TX64OCTGB */
+#define IFX_ETH_TX_64OCTETS_FRAMES_GOOD_BAD_TX64OCTGB_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_TX_64OCTETS_FRAMES_GOOD_BAD_Bits.TX64OCTGB */
+#define IFX_ETH_TX_64OCTETS_FRAMES_GOOD_BAD_TX64OCTGB_OFF (0u)
+
+/** \brief Length for
+ * Ifx_ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_Bits.TX65_127OCTGB */
+#define IFX_ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_TX65_127OCTGB_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_Bits.TX65_127OCTGB */
+#define IFX_ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_TX65_127OCTGB_MSK (0xffffffffu)
+
+/** \brief Offset for
+ * Ifx_ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_Bits.TX65_127OCTGB */
+#define IFX_ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_TX65_127OCTGB_OFF (0u)
+
+/** \brief Length for Ifx_ETH_TX_BROADCAST_FRAMES_GOOD_BAD_Bits.TXBCASTGB */
+#define IFX_ETH_TX_BROADCAST_FRAMES_GOOD_BAD_TXBCASTGB_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_TX_BROADCAST_FRAMES_GOOD_BAD_Bits.TXBCASTGB */
+#define IFX_ETH_TX_BROADCAST_FRAMES_GOOD_BAD_TXBCASTGB_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_TX_BROADCAST_FRAMES_GOOD_BAD_Bits.TXBCASTGB */
+#define IFX_ETH_TX_BROADCAST_FRAMES_GOOD_BAD_TXBCASTGB_OFF (0u)
+
+/** \brief Length for Ifx_ETH_TX_BROADCAST_FRAMES_GOOD_Bits.TXBCASTG */
+#define IFX_ETH_TX_BROADCAST_FRAMES_GOOD_TXBCASTG_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_TX_BROADCAST_FRAMES_GOOD_Bits.TXBCASTG */
+#define IFX_ETH_TX_BROADCAST_FRAMES_GOOD_TXBCASTG_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_TX_BROADCAST_FRAMES_GOOD_Bits.TXBCASTG */
+#define IFX_ETH_TX_BROADCAST_FRAMES_GOOD_TXBCASTG_OFF (0u)
+
+/** \brief Length for Ifx_ETH_TX_CARRIER_ERROR_FRAMES_Bits.TXCARR */
+#define IFX_ETH_TX_CARRIER_ERROR_FRAMES_TXCARR_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_TX_CARRIER_ERROR_FRAMES_Bits.TXCARR */
+#define IFX_ETH_TX_CARRIER_ERROR_FRAMES_TXCARR_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_TX_CARRIER_ERROR_FRAMES_Bits.TXCARR */
+#define IFX_ETH_TX_CARRIER_ERROR_FRAMES_TXCARR_OFF (0u)
+
+/** \brief Length for Ifx_ETH_TX_DEFERRED_FRAMES_Bits.TXDEFRD */
+#define IFX_ETH_TX_DEFERRED_FRAMES_TXDEFRD_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_TX_DEFERRED_FRAMES_Bits.TXDEFRD */
+#define IFX_ETH_TX_DEFERRED_FRAMES_TXDEFRD_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_TX_DEFERRED_FRAMES_Bits.TXDEFRD */
+#define IFX_ETH_TX_DEFERRED_FRAMES_TXDEFRD_OFF (0u)
+
+/** \brief Length for Ifx_ETH_TX_EXCESSIVE_COLLISION_FRAMES_Bits.TXEXSCOL */
+#define IFX_ETH_TX_EXCESSIVE_COLLISION_FRAMES_TXEXSCOL_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_TX_EXCESSIVE_COLLISION_FRAMES_Bits.TXEXSCOL */
+#define IFX_ETH_TX_EXCESSIVE_COLLISION_FRAMES_TXEXSCOL_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_TX_EXCESSIVE_COLLISION_FRAMES_Bits.TXEXSCOL */
+#define IFX_ETH_TX_EXCESSIVE_COLLISION_FRAMES_TXEXSCOL_OFF (0u)
+
+/** \brief Length for Ifx_ETH_TX_EXCESSIVE_DEFERRAL_ERROR_Bits.TXEXSDEF */
+#define IFX_ETH_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_TX_EXCESSIVE_DEFERRAL_ERROR_Bits.TXEXSDEF */
+#define IFX_ETH_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_TX_EXCESSIVE_DEFERRAL_ERROR_Bits.TXEXSDEF */
+#define IFX_ETH_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_OFF (0u)
+
+/** \brief Length for Ifx_ETH_TX_FRAME_COUNT_GOOD_BAD_Bits.TXFRMGB */
+#define IFX_ETH_TX_FRAME_COUNT_GOOD_BAD_TXFRMGB_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_TX_FRAME_COUNT_GOOD_BAD_Bits.TXFRMGB */
+#define IFX_ETH_TX_FRAME_COUNT_GOOD_BAD_TXFRMGB_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_TX_FRAME_COUNT_GOOD_BAD_Bits.TXFRMGB */
+#define IFX_ETH_TX_FRAME_COUNT_GOOD_BAD_TXFRMGB_OFF (0u)
+
+/** \brief Length for Ifx_ETH_TX_FRAME_COUNT_GOOD_Bits.TXFRMG */
+#define IFX_ETH_TX_FRAME_COUNT_GOOD_TXFRMG_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_TX_FRAME_COUNT_GOOD_Bits.TXFRMG */
+#define IFX_ETH_TX_FRAME_COUNT_GOOD_TXFRMG_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_TX_FRAME_COUNT_GOOD_Bits.TXFRMG */
+#define IFX_ETH_TX_FRAME_COUNT_GOOD_TXFRMG_OFF (0u)
+
+/** \brief Length for Ifx_ETH_TX_LATE_COLLISION_FRAMES_Bits.TXLATECOL */
+#define IFX_ETH_TX_LATE_COLLISION_FRAMES_TXLATECOL_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_TX_LATE_COLLISION_FRAMES_Bits.TXLATECOL */
+#define IFX_ETH_TX_LATE_COLLISION_FRAMES_TXLATECOL_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_TX_LATE_COLLISION_FRAMES_Bits.TXLATECOL */
+#define IFX_ETH_TX_LATE_COLLISION_FRAMES_TXLATECOL_OFF (0u)
+
+/** \brief Length for Ifx_ETH_TX_MULTICAST_FRAMES_GOOD_BAD_Bits.TXMCASTGB */
+#define IFX_ETH_TX_MULTICAST_FRAMES_GOOD_BAD_TXMCASTGB_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_TX_MULTICAST_FRAMES_GOOD_BAD_Bits.TXMCASTGB */
+#define IFX_ETH_TX_MULTICAST_FRAMES_GOOD_BAD_TXMCASTGB_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_TX_MULTICAST_FRAMES_GOOD_BAD_Bits.TXMCASTGB */
+#define IFX_ETH_TX_MULTICAST_FRAMES_GOOD_BAD_TXMCASTGB_OFF (0u)
+
+/** \brief Length for Ifx_ETH_TX_MULTICAST_FRAMES_GOOD_Bits.TXMCASTG */
+#define IFX_ETH_TX_MULTICAST_FRAMES_GOOD_TXMCASTG_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_TX_MULTICAST_FRAMES_GOOD_Bits.TXMCASTG */
+#define IFX_ETH_TX_MULTICAST_FRAMES_GOOD_TXMCASTG_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_TX_MULTICAST_FRAMES_GOOD_Bits.TXMCASTG */
+#define IFX_ETH_TX_MULTICAST_FRAMES_GOOD_TXMCASTG_OFF (0u)
+
+/** \brief Length for Ifx_ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_Bits.TXMULTCOLG */
+#define IFX_ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_TXMULTCOLG_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_Bits.TXMULTCOLG */
+#define IFX_ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_TXMULTCOLG_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_Bits.TXMULTCOLG */
+#define IFX_ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_TXMULTCOLG_OFF (0u)
+
+/** \brief Length for Ifx_ETH_TX_OCTET_COUNT_GOOD_BAD_Bits.TXOCTGB */
+#define IFX_ETH_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_TX_OCTET_COUNT_GOOD_BAD_Bits.TXOCTGB */
+#define IFX_ETH_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_TX_OCTET_COUNT_GOOD_BAD_Bits.TXOCTGB */
+#define IFX_ETH_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_OFF (0u)
+
+/** \brief Length for Ifx_ETH_TX_OCTET_COUNT_GOOD_Bits.TXOCTG */
+#define IFX_ETH_TX_OCTET_COUNT_GOOD_TXOCTG_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_TX_OCTET_COUNT_GOOD_Bits.TXOCTG */
+#define IFX_ETH_TX_OCTET_COUNT_GOOD_TXOCTG_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_TX_OCTET_COUNT_GOOD_Bits.TXOCTG */
+#define IFX_ETH_TX_OCTET_COUNT_GOOD_TXOCTG_OFF (0u)
+
+/** \brief Length for Ifx_ETH_TX_OSIZE_FRAMES_GOOD_Bits.TXOSIZG */
+#define IFX_ETH_TX_OSIZE_FRAMES_GOOD_TXOSIZG_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_TX_OSIZE_FRAMES_GOOD_Bits.TXOSIZG */
+#define IFX_ETH_TX_OSIZE_FRAMES_GOOD_TXOSIZG_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_TX_OSIZE_FRAMES_GOOD_Bits.TXOSIZG */
+#define IFX_ETH_TX_OSIZE_FRAMES_GOOD_TXOSIZG_OFF (0u)
+
+/** \brief Length for Ifx_ETH_TX_PAUSE_FRAMES_Bits.TXPAUSE */
+#define IFX_ETH_TX_PAUSE_FRAMES_TXPAUSE_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_TX_PAUSE_FRAMES_Bits.TXPAUSE */
+#define IFX_ETH_TX_PAUSE_FRAMES_TXPAUSE_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_TX_PAUSE_FRAMES_Bits.TXPAUSE */
+#define IFX_ETH_TX_PAUSE_FRAMES_TXPAUSE_OFF (0u)
+
+/** \brief Length for Ifx_ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_Bits.TXSNGLCOLG */
+#define IFX_ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_TXSNGLCOLG_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_Bits.TXSNGLCOLG */
+#define IFX_ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_TXSNGLCOLG_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_Bits.TXSNGLCOLG */
+#define IFX_ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_TXSNGLCOLG_OFF (0u)
+
+/** \brief Length for Ifx_ETH_TX_UNDERFLOW_ERROR_FRAMES_Bits.TXUNDRFLW */
+#define IFX_ETH_TX_UNDERFLOW_ERROR_FRAMES_TXUNDRFLW_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_TX_UNDERFLOW_ERROR_FRAMES_Bits.TXUNDRFLW */
+#define IFX_ETH_TX_UNDERFLOW_ERROR_FRAMES_TXUNDRFLW_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_TX_UNDERFLOW_ERROR_FRAMES_Bits.TXUNDRFLW */
+#define IFX_ETH_TX_UNDERFLOW_ERROR_FRAMES_TXUNDRFLW_OFF (0u)
+
+/** \brief Length for Ifx_ETH_TX_UNICAST_FRAMES_GOOD_BAD_Bits.TXUCASTGB */
+#define IFX_ETH_TX_UNICAST_FRAMES_GOOD_BAD_TXUCASTGB_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_TX_UNICAST_FRAMES_GOOD_BAD_Bits.TXUCASTGB */
+#define IFX_ETH_TX_UNICAST_FRAMES_GOOD_BAD_TXUCASTGB_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_TX_UNICAST_FRAMES_GOOD_BAD_Bits.TXUCASTGB */
+#define IFX_ETH_TX_UNICAST_FRAMES_GOOD_BAD_TXUCASTGB_OFF (0u)
+
+/** \brief Length for Ifx_ETH_TX_VLAN_FRAMES_GOOD_Bits.TXVLANG */
+#define IFX_ETH_TX_VLAN_FRAMES_GOOD_TXVLANG_LEN (32u)
+
+/** \brief Mask for Ifx_ETH_TX_VLAN_FRAMES_GOOD_Bits.TXVLANG */
+#define IFX_ETH_TX_VLAN_FRAMES_GOOD_TXVLANG_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_ETH_TX_VLAN_FRAMES_GOOD_Bits.TXVLANG */
+#define IFX_ETH_TX_VLAN_FRAMES_GOOD_TXVLANG_OFF (0u)
+
+/** \brief Length for Ifx_ETH_VERSION_Bits.SNPSVER */
+#define IFX_ETH_VERSION_SNPSVER_LEN (8u)
+
+/** \brief Mask for Ifx_ETH_VERSION_Bits.SNPSVER */
+#define IFX_ETH_VERSION_SNPSVER_MSK (0xffu)
+
+/** \brief Offset for Ifx_ETH_VERSION_Bits.SNPSVER */
+#define IFX_ETH_VERSION_SNPSVER_OFF (0u)
+
+/** \brief Length for Ifx_ETH_VERSION_Bits.USERVER */
+#define IFX_ETH_VERSION_USERVER_LEN (8u)
+
+/** \brief Mask for Ifx_ETH_VERSION_Bits.USERVER */
+#define IFX_ETH_VERSION_USERVER_MSK (0xffu)
+
+/** \brief Offset for Ifx_ETH_VERSION_Bits.USERVER */
+#define IFX_ETH_VERSION_USERVER_OFF (8u)
+
+/** \brief Length for Ifx_ETH_VLAN_TAG_Bits.ESVL */
+#define IFX_ETH_VLAN_TAG_ESVL_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_VLAN_TAG_Bits.ESVL */
+#define IFX_ETH_VLAN_TAG_ESVL_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_VLAN_TAG_Bits.ESVL */
+#define IFX_ETH_VLAN_TAG_ESVL_OFF (18u)
+
+/** \brief Length for Ifx_ETH_VLAN_TAG_Bits.ETV */
+#define IFX_ETH_VLAN_TAG_ETV_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_VLAN_TAG_Bits.ETV */
+#define IFX_ETH_VLAN_TAG_ETV_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_VLAN_TAG_Bits.ETV */
+#define IFX_ETH_VLAN_TAG_ETV_OFF (16u)
+
+/** \brief Length for Ifx_ETH_VLAN_TAG_Bits.VL */
+#define IFX_ETH_VLAN_TAG_VL_LEN (16u)
+
+/** \brief Mask for Ifx_ETH_VLAN_TAG_Bits.VL */
+#define IFX_ETH_VLAN_TAG_VL_MSK (0xffffu)
+
+/** \brief Offset for Ifx_ETH_VLAN_TAG_Bits.VL */
+#define IFX_ETH_VLAN_TAG_VL_OFF (0u)
+
+/** \brief Length for Ifx_ETH_VLAN_TAG_Bits.VTHM */
+#define IFX_ETH_VLAN_TAG_VTHM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_VLAN_TAG_Bits.VTHM */
+#define IFX_ETH_VLAN_TAG_VTHM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_VLAN_TAG_Bits.VTHM */
+#define IFX_ETH_VLAN_TAG_VTHM_OFF (19u)
+
+/** \brief Length for Ifx_ETH_VLAN_TAG_Bits.VTIM */
+#define IFX_ETH_VLAN_TAG_VTIM_LEN (1u)
+
+/** \brief Mask for Ifx_ETH_VLAN_TAG_Bits.VTIM */
+#define IFX_ETH_VLAN_TAG_VTIM_MSK (0x1u)
+
+/** \brief Offset for Ifx_ETH_VLAN_TAG_Bits.VTIM */
+#define IFX_ETH_VLAN_TAG_VTIM_OFF (17u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXETH_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEth_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEth_reg.h
new file mode 100644
index 0000000..fe68a8e
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEth_reg.h
@@ -0,0 +1,1003 @@
+/**
+ * \file IfxEth_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Eth_Cfg Eth address
+ * \ingroup IfxLld_Eth
+ *
+ * \defgroup IfxLld_Eth_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Eth_Cfg
+ *
+ * \defgroup IfxLld_Eth_Cfg_Eth 2-ETH
+ * \ingroup IfxLld_Eth_Cfg
+ *
+ */
+#ifndef IFXETH_REG_H
+#define IFXETH_REG_H 1
+/******************************************************************************/
+#include "IfxEth_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Eth_Cfg_BaseAddress
+ * \{ */
+
+/** \brief ETH object */
+#define MODULE_ETH /*lint --e(923)*/ (*(Ifx_ETH*)0xF001D000u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Eth_Cfg_Eth
+ * \{ */
+
+/** \brief C, Access Enable Register 0 */
+#define ETH_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_ETH_ACCEN0*)0xF001D00Cu)
+
+/** \brief 10, Access Enable Register 1 */
+#define ETH_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_ETH_ACCEN1*)0xF001D010u)
+
+/** \brief 202C, Register 11 - AHB or AXI Status Register */
+#define ETH_AHB_OR_AXI_STATUS /*lint --e(923)*/ (*(volatile Ifx_ETH_AHB_OR_AXI_STATUS*)0xF001F02Cu)
+
+/** \brief 2000, Register 0 - Bus Mode Register */
+#define ETH_BUS_MODE /*lint --e(923)*/ (*(volatile Ifx_ETH_BUS_MODE*)0xF001F000u)
+
+/** \brief 0, Clock Control Register */
+#define ETH_CLC /*lint --e(923)*/ (*(volatile Ifx_ETH_CLC*)0xF001D000u)
+
+/** \brief 2054, Register 21 - Current Host Receive Buffer Address Register */
+#define ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS /*lint --e(923)*/ (*(volatile Ifx_ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS*)0xF001F054u)
+
+/** \brief 204C, Register 19 - Current Host Receive Descriptor Register */
+#define ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR /*lint --e(923)*/ (*(volatile Ifx_ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR*)0xF001F04Cu)
+
+/** \brief 2050, Register 20 - Current Host Transmit Buffer Address Register */
+#define ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS /*lint --e(923)*/ (*(volatile Ifx_ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS*)0xF001F050u)
+
+/** \brief 2048, Register 18 - Current Host Transmit Descriptor Register */
+#define ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR /*lint --e(923)*/ (*(volatile Ifx_ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR*)0xF001F048u)
+
+/** \brief 1024, Register 9 - Debug Register */
+#define ETH_DEBUG /*lint --e(923)*/ (*(volatile Ifx_ETH_DEBUG*)0xF001E024u)
+
+/** \brief 1018, Register 6 - Flow Control Register */
+#define ETH_FLOW_CONTROL /*lint --e(923)*/ (*(volatile Ifx_ETH_FLOW_CONTROL*)0xF001E018u)
+
+/** \brief 1010, Register 4 - GMII Address Register */
+#define ETH_GMII_ADDRESS /*lint --e(923)*/ (*(volatile Ifx_ETH_GMII_ADDRESS*)0xF001E010u)
+
+/** \brief 1014, Register 5 - GMII Data Register */
+#define ETH_GMII_DATA /*lint --e(923)*/ (*(volatile Ifx_ETH_GMII_DATA*)0xF001E014u)
+
+/** \brief 8, Input and Output Control Register */
+#define ETH_GPCTL /*lint --e(923)*/ (*(volatile Ifx_ETH_GPCTL*)0xF001D008u)
+
+/** \brief 1008, Register 2 - Hash Table High Register */
+#define ETH_HASH_TABLE_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_HASH_TABLE_HIGH*)0xF001E008u)
+
+/** \brief 100C, Register 3 - Hash Table Low Register */
+#define ETH_HASH_TABLE_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_HASH_TABLE_LOW*)0xF001E00Cu)
+
+/** \brief 2058, Register 22 - HW Feature Register */
+#define ETH_HW_FEATURE /*lint --e(923)*/ (*(volatile Ifx_ETH_HW_FEATURE*)0xF001F058u)
+
+/** \brief 4, Module Identification Register */
+#define ETH_ID /*lint --e(923)*/ (*(volatile Ifx_ETH_ID*)0xF001D004u)
+
+/** \brief 201C, Register 7 - Interrupt Enable Register */
+#define ETH_INTERRUPT_ENABLE /*lint --e(923)*/ (*(volatile Ifx_ETH_INTERRUPT_ENABLE*)0xF001F01Cu)
+
+/** \brief 103C, Register 15 - Interrupt Mask Register */
+#define ETH_INTERRUPT_MASK /*lint --e(923)*/ (*(volatile Ifx_ETH_INTERRUPT_MASK*)0xF001E03Cu)
+
+/** \brief 1038, Register 14 - Interrupt Register */
+#define ETH_INTERRUPT_STATUS /*lint --e(923)*/ (*(volatile Ifx_ETH_INTERRUPT_STATUS*)0xF001E038u)
+
+/** \brief 14, Kernel Reset Register 0 */
+#define ETH_KRST0 /*lint --e(923)*/ (*(volatile Ifx_ETH_KRST0*)0xF001D014u)
+
+/** \brief 18, Kernel Reset Register 1 */
+#define ETH_KRST1 /*lint --e(923)*/ (*(volatile Ifx_ETH_KRST1*)0xF001D018u)
+
+/** \brief 1C, Kernel Reset Status Clear Register */
+#define ETH_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_ETH_KRSTCLR*)0xF001D01Cu)
+
+/** \brief 1040, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G00_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E040u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G00_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G00_HIGH.
+*/
+#define ETH_MAC_ADDRESS0_HIGH (ETH_MAC_ADDRESS_G00_HIGH)
+
+/** \brief 1044, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G00_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E044u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G00_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G00_LOW.
+*/
+#define ETH_MAC_ADDRESS0_LOW (ETH_MAC_ADDRESS_G00_LOW)
+
+/** \brief 1090, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G010_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E090u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G010_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G010_HIGH.
+*/
+#define ETH_MAC_ADDRESS10_HIGH (ETH_MAC_ADDRESS_G010_HIGH)
+
+/** \brief 1094, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G010_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E094u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G010_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G010_LOW.
+*/
+#define ETH_MAC_ADDRESS10_LOW (ETH_MAC_ADDRESS_G010_LOW)
+
+/** \brief 1098, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G011_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E098u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G011_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G011_HIGH.
+*/
+#define ETH_MAC_ADDRESS11_HIGH (ETH_MAC_ADDRESS_G011_HIGH)
+
+/** \brief 109C, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G011_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E09Cu)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G011_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G011_LOW.
+*/
+#define ETH_MAC_ADDRESS11_LOW (ETH_MAC_ADDRESS_G011_LOW)
+
+/** \brief 10A0, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G012_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E0A0u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G012_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G012_HIGH.
+*/
+#define ETH_MAC_ADDRESS12_HIGH (ETH_MAC_ADDRESS_G012_HIGH)
+
+/** \brief 10A4, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G012_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E0A4u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G012_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G012_LOW.
+*/
+#define ETH_MAC_ADDRESS12_LOW (ETH_MAC_ADDRESS_G012_LOW)
+
+/** \brief 10A8, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G013_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E0A8u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G013_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G013_HIGH.
+*/
+#define ETH_MAC_ADDRESS13_HIGH (ETH_MAC_ADDRESS_G013_HIGH)
+
+/** \brief 10AC, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G013_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E0ACu)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G013_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G013_LOW.
+*/
+#define ETH_MAC_ADDRESS13_LOW (ETH_MAC_ADDRESS_G013_LOW)
+
+/** \brief 10B0, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G014_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E0B0u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G014_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G014_HIGH.
+*/
+#define ETH_MAC_ADDRESS14_HIGH (ETH_MAC_ADDRESS_G014_HIGH)
+
+/** \brief 10B4, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G014_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E0B4u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G014_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G014_LOW.
+*/
+#define ETH_MAC_ADDRESS14_LOW (ETH_MAC_ADDRESS_G014_LOW)
+
+/** \brief 10B8, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G015_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E0B8u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G015_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G015_HIGH.
+*/
+#define ETH_MAC_ADDRESS15_HIGH (ETH_MAC_ADDRESS_G015_HIGH)
+
+/** \brief 10BC, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G015_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E0BCu)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G015_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G015_LOW.
+*/
+#define ETH_MAC_ADDRESS15_LOW (ETH_MAC_ADDRESS_G015_LOW)
+
+/** \brief 1048, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G01_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E048u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G01_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G01_HIGH.
+*/
+#define ETH_MAC_ADDRESS1_HIGH (ETH_MAC_ADDRESS_G01_HIGH)
+
+/** \brief 104C, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G01_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E04Cu)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G01_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G01_LOW.
+*/
+#define ETH_MAC_ADDRESS1_LOW (ETH_MAC_ADDRESS_G01_LOW)
+
+/** \brief 1050, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G02_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E050u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G02_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G02_HIGH.
+*/
+#define ETH_MAC_ADDRESS2_HIGH (ETH_MAC_ADDRESS_G02_HIGH)
+
+/** \brief 1054, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G02_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E054u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G02_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G02_LOW.
+*/
+#define ETH_MAC_ADDRESS2_LOW (ETH_MAC_ADDRESS_G02_LOW)
+
+/** \brief 1058, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G03_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E058u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G03_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G03_HIGH.
+*/
+#define ETH_MAC_ADDRESS3_HIGH (ETH_MAC_ADDRESS_G03_HIGH)
+
+/** \brief 105C, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G03_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E05Cu)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G03_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G03_LOW.
+*/
+#define ETH_MAC_ADDRESS3_LOW (ETH_MAC_ADDRESS_G03_LOW)
+
+/** \brief 1060, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G04_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E060u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G04_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G04_HIGH.
+*/
+#define ETH_MAC_ADDRESS4_HIGH (ETH_MAC_ADDRESS_G04_HIGH)
+
+/** \brief 1064, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G04_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E064u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G04_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G04_LOW.
+*/
+#define ETH_MAC_ADDRESS4_LOW (ETH_MAC_ADDRESS_G04_LOW)
+
+/** \brief 1068, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G05_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E068u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G05_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G05_HIGH.
+*/
+#define ETH_MAC_ADDRESS5_HIGH (ETH_MAC_ADDRESS_G05_HIGH)
+
+/** \brief 106C, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G05_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E06Cu)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G05_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G05_LOW.
+*/
+#define ETH_MAC_ADDRESS5_LOW (ETH_MAC_ADDRESS_G05_LOW)
+
+/** \brief 1070, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G06_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E070u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G06_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G06_HIGH.
+*/
+#define ETH_MAC_ADDRESS6_HIGH (ETH_MAC_ADDRESS_G06_HIGH)
+
+/** \brief 1074, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G06_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E074u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G06_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G06_LOW.
+*/
+#define ETH_MAC_ADDRESS6_LOW (ETH_MAC_ADDRESS_G06_LOW)
+
+/** \brief 1078, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G07_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E078u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G07_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G07_HIGH.
+*/
+#define ETH_MAC_ADDRESS7_HIGH (ETH_MAC_ADDRESS_G07_HIGH)
+
+/** \brief 107C, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G07_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E07Cu)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G07_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G07_LOW.
+*/
+#define ETH_MAC_ADDRESS7_LOW (ETH_MAC_ADDRESS_G07_LOW)
+
+/** \brief 1080, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G08_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E080u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G08_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G08_HIGH.
+*/
+#define ETH_MAC_ADDRESS8_HIGH (ETH_MAC_ADDRESS_G08_HIGH)
+
+/** \brief 1084, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G08_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E084u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G08_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G08_LOW.
+*/
+#define ETH_MAC_ADDRESS8_LOW (ETH_MAC_ADDRESS_G08_LOW)
+
+/** \brief 1088, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G09_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E088u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G09_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G09_HIGH.
+*/
+#define ETH_MAC_ADDRESS9_HIGH (ETH_MAC_ADDRESS_G09_HIGH)
+
+/** \brief 108C, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G09_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E08Cu)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G09_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G09_LOW.
+*/
+#define ETH_MAC_ADDRESS9_LOW (ETH_MAC_ADDRESS_G09_LOW)
+
+/** \brief 1800, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G10_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E800u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G10_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G10_HIGH.
+*/
+#define ETH_MAC_ADDRESS16_HIGH (ETH_MAC_ADDRESS_G10_HIGH)
+
+/** \brief 1804, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G10_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E804u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G10_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G10_LOW.
+*/
+#define ETH_MAC_ADDRESS16_LOW (ETH_MAC_ADDRESS_G10_LOW)
+
+/** \brief 1850, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G110_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E850u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G110_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G110_HIGH.
+*/
+#define ETH_MAC_ADDRESS26_HIGH (ETH_MAC_ADDRESS_G110_HIGH)
+
+/** \brief 1854, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G110_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E854u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G110_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G110_LOW.
+*/
+#define ETH_MAC_ADDRESS26_LOW (ETH_MAC_ADDRESS_G110_LOW)
+
+/** \brief 1858, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G111_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E858u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G111_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G111_HIGH.
+*/
+#define ETH_MAC_ADDRESS27_HIGH (ETH_MAC_ADDRESS_G111_HIGH)
+
+/** \brief 185C, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G111_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E85Cu)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G111_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G111_LOW.
+*/
+#define ETH_MAC_ADDRESS27_LOW (ETH_MAC_ADDRESS_G111_LOW)
+
+/** \brief 1860, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G112_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E860u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G112_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G112_HIGH.
+*/
+#define ETH_MAC_ADDRESS28_HIGH (ETH_MAC_ADDRESS_G112_HIGH)
+
+/** \brief 1864, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G112_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E864u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G112_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G112_LOW.
+*/
+#define ETH_MAC_ADDRESS28_LOW (ETH_MAC_ADDRESS_G112_LOW)
+
+/** \brief 1868, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G113_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E868u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G113_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G113_HIGH.
+*/
+#define ETH_MAC_ADDRESS29_HIGH (ETH_MAC_ADDRESS_G113_HIGH)
+
+/** \brief 186C, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G113_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E86Cu)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G113_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G113_LOW.
+*/
+#define ETH_MAC_ADDRESS29_LOW (ETH_MAC_ADDRESS_G113_LOW)
+
+/** \brief 1870, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G114_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E870u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G114_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G114_HIGH.
+*/
+#define ETH_MAC_ADDRESS30_HIGH (ETH_MAC_ADDRESS_G114_HIGH)
+
+/** \brief 1874, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G114_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E874u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G114_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G114_LOW.
+*/
+#define ETH_MAC_ADDRESS30_LOW (ETH_MAC_ADDRESS_G114_LOW)
+
+/** \brief 1878, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G115_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E878u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G115_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G115_HIGH.
+*/
+#define ETH_MAC_ADDRESS31_HIGH (ETH_MAC_ADDRESS_G115_HIGH)
+
+/** \brief 187C, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G115_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E87Cu)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G115_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G115_LOW.
+*/
+#define ETH_MAC_ADDRESS31_LOW (ETH_MAC_ADDRESS_G115_LOW)
+
+/** \brief 1808, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G11_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E808u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G11_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G11_HIGH.
+*/
+#define ETH_MAC_ADDRESS17_HIGH (ETH_MAC_ADDRESS_G11_HIGH)
+
+/** \brief 180C, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G11_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E80Cu)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G11_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G11_LOW.
+*/
+#define ETH_MAC_ADDRESS17_LOW (ETH_MAC_ADDRESS_G11_LOW)
+
+/** \brief 1810, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G12_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E810u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G12_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G12_HIGH.
+*/
+#define ETH_MAC_ADDRESS18_HIGH (ETH_MAC_ADDRESS_G12_HIGH)
+
+/** \brief 1814, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G12_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E814u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G12_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G12_LOW.
+*/
+#define ETH_MAC_ADDRESS18_LOW (ETH_MAC_ADDRESS_G12_LOW)
+
+/** \brief 1818, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G13_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E818u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G13_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G13_HIGH.
+*/
+#define ETH_MAC_ADDRESS19_HIGH (ETH_MAC_ADDRESS_G13_HIGH)
+
+/** \brief 181C, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G13_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E81Cu)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G13_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G13_LOW.
+*/
+#define ETH_MAC_ADDRESS19_LOW (ETH_MAC_ADDRESS_G13_LOW)
+
+/** \brief 1820, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G14_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E820u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G14_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G14_HIGH.
+*/
+#define ETH_MAC_ADDRESS20_HIGH (ETH_MAC_ADDRESS_G14_HIGH)
+
+/** \brief 1824, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G14_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E824u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G14_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G14_LOW.
+*/
+#define ETH_MAC_ADDRESS20_LOW (ETH_MAC_ADDRESS_G14_LOW)
+
+/** \brief 1828, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G15_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E828u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G15_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G15_HIGH.
+*/
+#define ETH_MAC_ADDRESS21_HIGH (ETH_MAC_ADDRESS_G15_HIGH)
+
+/** \brief 182C, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G15_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E82Cu)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G15_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G15_LOW.
+*/
+#define ETH_MAC_ADDRESS21_LOW (ETH_MAC_ADDRESS_G15_LOW)
+
+/** \brief 1830, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G16_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E830u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G16_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G16_HIGH.
+*/
+#define ETH_MAC_ADDRESS22_HIGH (ETH_MAC_ADDRESS_G16_HIGH)
+
+/** \brief 1834, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G16_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E834u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G16_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G16_LOW.
+*/
+#define ETH_MAC_ADDRESS22_LOW (ETH_MAC_ADDRESS_G16_LOW)
+
+/** \brief 1838, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G17_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E838u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G17_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G17_HIGH.
+*/
+#define ETH_MAC_ADDRESS23_HIGH (ETH_MAC_ADDRESS_G17_HIGH)
+
+/** \brief 183C, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G17_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E83Cu)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G17_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G17_LOW.
+*/
+#define ETH_MAC_ADDRESS23_LOW (ETH_MAC_ADDRESS_G17_LOW)
+
+/** \brief 1840, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G18_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E840u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G18_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G18_HIGH.
+*/
+#define ETH_MAC_ADDRESS24_HIGH (ETH_MAC_ADDRESS_G18_HIGH)
+
+/** \brief 1844, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G18_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E844u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G18_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G18_LOW.
+*/
+#define ETH_MAC_ADDRESS24_LOW (ETH_MAC_ADDRESS_G18_LOW)
+
+/** \brief 1848, MAC Address High Register */
+#define ETH_MAC_ADDRESS_G19_HIGH /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_HIGH*)0xF001E848u)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G19_HIGH.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G19_HIGH.
+*/
+#define ETH_MAC_ADDRESS25_HIGH (ETH_MAC_ADDRESS_G19_HIGH)
+
+/** \brief 184C, MAC Address Low Register */
+#define ETH_MAC_ADDRESS_G19_LOW /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_ADDRESS_LOW*)0xF001E84Cu)
+
+/** Alias (User Manual Name) for ETH_MAC_ADDRESS_G19_LOW.
+* To use register names with standard convension, please use ETH_MAC_ADDRESS_G19_LOW.
+*/
+#define ETH_MAC_ADDRESS25_LOW (ETH_MAC_ADDRESS_G19_LOW)
+
+/** \brief 1000, Register 0 - MAC Configuration Register */
+#define ETH_MAC_CONFIGURATION /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_CONFIGURATION*)0xF001E000u)
+
+/** \brief 1004, Register 1 - MAC Frame Filter */
+#define ETH_MAC_FRAME_FILTER /*lint --e(923)*/ (*(volatile Ifx_ETH_MAC_FRAME_FILTER*)0xF001E004u)
+
+/** \brief 2020, Register 8 - Missed Frame and Buffer Overflow Counter Register */
+#define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER /*lint --e(923)*/ (*(volatile Ifx_ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER*)0xF001F020u)
+
+/** \brief 1100, Register 64 - MMC Control Register */
+#define ETH_MMC_CONTROL /*lint --e(923)*/ (*(volatile Ifx_ETH_MMC_CONTROL*)0xF001E100u)
+
+/** \brief 1208, Register 130 - MMC Receive Checksum Offload Interrupt Register */
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT /*lint --e(923)*/ (*(volatile Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT*)0xF001E208u)
+
+/** \brief 1200, Register 128 - MMC Receive Checksum Offload Interrupt Mask
+ * Register */
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK /*lint --e(923)*/ (*(volatile Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK*)0xF001E200u)
+
+/** \brief 1104, Register 65 - MMC Receive Interrupt Register */
+#define ETH_MMC_RECEIVE_INTERRUPT /*lint --e(923)*/ (*(volatile Ifx_ETH_MMC_RECEIVE_INTERRUPT*)0xF001E104u)
+
+/** \brief 110C, - */
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK /*lint --e(923)*/ (*(volatile Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK*)0xF001E10Cu)
+
+/** \brief 1108, Register 66 - MMC Transmit Interrupt Register */
+#define ETH_MMC_TRANSMIT_INTERRUPT /*lint --e(923)*/ (*(volatile Ifx_ETH_MMC_TRANSMIT_INTERRUPT*)0xF001E108u)
+
+/** \brief 1110, Register 68 - MMC Transmit Interrupt Mask Register */
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK /*lint --e(923)*/ (*(volatile Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK*)0xF001E110u)
+
+/** \brief 2018, Register 6 - Operation Mode Register */
+#define ETH_OPERATION_MODE /*lint --e(923)*/ (*(volatile Ifx_ETH_OPERATION_MODE*)0xF001F018u)
+
+/** \brief 102C, Register 11 - PMT Control and Status Register */
+#define ETH_PMT_CONTROL_STATUS /*lint --e(923)*/ (*(volatile Ifx_ETH_PMT_CONTROL_STATUS*)0xF001E02Cu)
+
+/** \brief 172C, Register 459 - PPS Control Register */
+#define ETH_PPS_CONTROL /*lint --e(923)*/ (*(volatile Ifx_ETH_PPS_CONTROL*)0xF001E72Cu)
+
+/** \brief 200C, Register 3 - Receive Descriptor List Address Register */
+#define ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS /*lint --e(923)*/ (*(volatile Ifx_ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS*)0xF001F00Cu)
+
+/** \brief 2024, Register 9 - Receive Interrupt Watchdog Timer Register */
+#define ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER /*lint --e(923)*/ (*(volatile Ifx_ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER*)0xF001F024u)
+
+/** \brief 2008, Register 2 - Receive Poll Demand Register */
+#define ETH_RECEIVE_POLL_DEMAND /*lint --e(923)*/ (*(volatile Ifx_ETH_RECEIVE_POLL_DEMAND*)0xF001F008u)
+
+/** \brief 1028, Register 10 - Remote Wake-Up Frame Filter Register */
+#define ETH_REMOTE_WAKE_UP_FRAME_FILTER /*lint --e(923)*/ (*(volatile Ifx_ETH_REMOTE_WAKE_UP_FRAME_FILTER*)0xF001E028u)
+
+/** \brief 11C0, Register 112 - Receive Frame Count for Good and Bad 1,024 to
+ * Maxsize Bytes Frames */
+#define ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD /*lint --e(923)*/ (*(volatile Ifx_ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD*)0xF001E1C0u)
+
+/** \brief 11B4, Register 109 - Receive Frame Count for Good and Bad 128 to 255
+ * Bytes Frames */
+#define ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD /*lint --e(923)*/ (*(volatile Ifx_ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD*)0xF001E1B4u)
+
+/** \brief 11B8, Register 110 - Receive Frame Count for Good and Bad 256 to 511
+ * Bytes Frames */
+#define ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD /*lint --e(923)*/ (*(volatile Ifx_ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD*)0xF001E1B8u)
+
+/** \brief 11BC, Register 111 - Receive Frame Count for Good and Bad 512 to
+ * 1,023 Bytes Frames */
+#define ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD /*lint --e(923)*/ (*(volatile Ifx_ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD*)0xF001E1BCu)
+
+/** \brief 11AC, Register 107 - Receive Frame Count for Good and Bad 64 Byte
+ * Frames */
+#define ETH_RX_64OCTETS_FRAMES_GOOD_BAD /*lint --e(923)*/ (*(volatile Ifx_ETH_RX_64OCTETS_FRAMES_GOOD_BAD*)0xF001E1ACu)
+
+/** \brief 11B0, Register 108 - Receive Frame Count for Good and Bad 65 to 127
+ * Bytes Frames */
+#define ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD /*lint --e(923)*/ (*(volatile Ifx_ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD*)0xF001E1B0u)
+
+/** \brief 1198, Register 102 - Receive Frame Count for Alignment Error Frames */
+#define ETH_RX_ALIGNMENT_ERROR_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_RX_ALIGNMENT_ERROR_FRAMES*)0xF001E198u)
+
+/** \brief 118C, Register 99 - Receive Frame Count for Good Broadcast Frames */
+#define ETH_RX_BROADCAST_FRAMES_GOOD /*lint --e(923)*/ (*(volatile Ifx_ETH_RX_BROADCAST_FRAMES_GOOD*)0xF001E18Cu)
+
+/** \brief 11E4, Register 121 - Receive Frame Count for Good Control Frames
+ * Frames */
+#define ETH_RX_CONTROL_FRAMES_GOOD /*lint --e(923)*/ (*(volatile Ifx_ETH_RX_CONTROL_FRAMES_GOOD*)0xF001E1E4u)
+
+/** \brief 1194, Register 101 - Receive Frame Count for CRC Error Frames */
+#define ETH_RX_CRC_ERROR_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_RX_CRC_ERROR_FRAMES*)0xF001E194u)
+
+/** \brief 11D4, Register 117 - Receive Frame Count for FIFO Overflow Frames */
+#define ETH_RX_FIFO_OVERFLOW_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_RX_FIFO_OVERFLOW_FRAMES*)0xF001E1D4u)
+
+/** \brief 1180, Register 96 - Receive Frame Count for Good and Bad Frames */
+#define ETH_RX_FRAMES_COUNT_GOOD_BAD /*lint --e(923)*/ (*(volatile Ifx_ETH_RX_FRAMES_COUNT_GOOD_BAD*)0xF001E180u)
+
+/** \brief 11A0, Register 104 - Receive Frame Count for Jabber Error Frames */
+#define ETH_RX_JABBER_ERROR_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_RX_JABBER_ERROR_FRAMES*)0xF001E1A0u)
+
+/** \brief 11C8, Register 114 - Receive Frame Count for Length Error Frames */
+#define ETH_RX_LENGTH_ERROR_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_RX_LENGTH_ERROR_FRAMES*)0xF001E1C8u)
+
+/** \brief 1190, Register 100 - Receive Frame Count for Good Multicast Frames */
+#define ETH_RX_MULTICAST_FRAMES_GOOD /*lint --e(923)*/ (*(volatile Ifx_ETH_RX_MULTICAST_FRAMES_GOOD*)0xF001E190u)
+
+/** \brief 1188, Register 98 - Receive Octet Count for Good Frames */
+#define ETH_RX_OCTET_COUNT_GOOD /*lint --e(923)*/ (*(volatile Ifx_ETH_RX_OCTET_COUNT_GOOD*)0xF001E188u)
+
+/** \brief 1184, Register 97 - Receive Octet Count for Good and Bad Frames */
+#define ETH_RX_OCTET_COUNT_GOOD_BAD /*lint --e(923)*/ (*(volatile Ifx_ETH_RX_OCTET_COUNT_GOOD_BAD*)0xF001E184u)
+
+/** \brief 11CC, Register 115 - Receive Frame Count for Out of Range Frames */
+#define ETH_RX_OUT_OF_RANGE_TYPE_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_RX_OUT_OF_RANGE_TYPE_FRAMES*)0xF001E1CCu)
+
+/** \brief 11A8, Register 106 - Receive Frame Count for Oversize Frames */
+#define ETH_RX_OVERSIZE_FRAMES_GOOD /*lint --e(923)*/ (*(volatile Ifx_ETH_RX_OVERSIZE_FRAMES_GOOD*)0xF001E1A8u)
+
+/** \brief 11D0, Register 116 - Receive Frame Count for PAUSE Frames */
+#define ETH_RX_PAUSE_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_RX_PAUSE_FRAMES*)0xF001E1D0u)
+
+/** \brief 11E0, Register 120 - Receive Frame Count for Receive Error Frames */
+#define ETH_RX_RECEIVE_ERROR_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_RX_RECEIVE_ERROR_FRAMES*)0xF001E1E0u)
+
+/** \brief 119C, Register 103 - Receive Frame Count for Runt Error Frames */
+#define ETH_RX_RUNT_ERROR_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_RX_RUNT_ERROR_FRAMES*)0xF001E19Cu)
+
+/** \brief 11A4, Register 105 - Receive Frame Count for Undersize Frames */
+#define ETH_RX_UNDERSIZE_FRAMES_GOOD /*lint --e(923)*/ (*(volatile Ifx_ETH_RX_UNDERSIZE_FRAMES_GOOD*)0xF001E1A4u)
+
+/** \brief 11C4, Register 113 - Receive Frame Count for Good Unicast Frames */
+#define ETH_RX_UNICAST_FRAMES_GOOD /*lint --e(923)*/ (*(volatile Ifx_ETH_RX_UNICAST_FRAMES_GOOD*)0xF001E1C4u)
+
+/** \brief 11D8, Register 118 - Receive Frame Count for Good and Bad VLAN
+ * Frames */
+#define ETH_RX_VLAN_FRAMES_GOOD_BAD /*lint --e(923)*/ (*(volatile Ifx_ETH_RX_VLAN_FRAMES_GOOD_BAD*)0xF001E1D8u)
+
+/** \brief 11DC, Register 119 - Receive Frame Count for Watchdog Error Frames */
+#define ETH_RX_WATCHDOG_ERROR_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_RX_WATCHDOG_ERROR_FRAMES*)0xF001E1DCu)
+
+/** \brief 1244, Register 145 - Receive ICMP Error Frame Counter Register */
+#define ETH_RXICMP_ERROR_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_RXICMP_ERROR_FRAMES*)0xF001E244u)
+
+/** \brief 1284, Register 161 - Receive ICMP Error Octet Counter Register */
+#define ETH_RXICMP_ERROR_OCTETS /*lint --e(923)*/ (*(volatile Ifx_ETH_RXICMP_ERROR_OCTETS*)0xF001E284u)
+
+/** \brief 1240, Register 144 - Receive ICMP Good Frame Counter Register */
+#define ETH_RXICMP_GOOD_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_RXICMP_GOOD_FRAMES*)0xF001E240u)
+
+/** \brief 1280, Register 160 - Receive ICMP Good Octet Counter Register */
+#define ETH_RXICMP_GOOD_OCTETS /*lint --e(923)*/ (*(volatile Ifx_ETH_RXICMP_GOOD_OCTETS*)0xF001E280u)
+
+/** \brief 121C, Register 135 - Receive IPV4 Fragmented Frame Counter Register */
+#define ETH_RXIPV4_FRAGMENTED_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_RXIPV4_FRAGMENTED_FRAMES*)0xF001E21Cu)
+
+/** \brief 125C, Register 151 - Receive IPV4 Fragmented Octet Counter Register */
+#define ETH_RXIPV4_FRAGMENTED_OCTETS /*lint --e(923)*/ (*(volatile Ifx_ETH_RXIPV4_FRAGMENTED_OCTETS*)0xF001E25Cu)
+
+/** \brief 1210, Register 132 - Receive IPV4 Good Frame Counter Register */
+#define ETH_RXIPV4_GOOD_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_RXIPV4_GOOD_FRAMES*)0xF001E210u)
+
+/** \brief 1250, Register 148 - Receive IPV4 Good Octet Counter Register */
+#define ETH_RXIPV4_GOOD_OCTETS /*lint --e(923)*/ (*(volatile Ifx_ETH_RXIPV4_GOOD_OCTETS*)0xF001E250u)
+
+/** \brief 1214, Register 133 - Receive IPV4 Header Error Frame Counter
+ * Register */
+#define ETH_RXIPV4_HEADER_ERROR_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_RXIPV4_HEADER_ERROR_FRAMES*)0xF001E214u)
+
+/** \brief 1254, Register 149 - Receive IPV4 Header Error Octet Counter
+ * Register */
+#define ETH_RXIPV4_HEADER_ERROR_OCTETS /*lint --e(923)*/ (*(volatile Ifx_ETH_RXIPV4_HEADER_ERROR_OCTETS*)0xF001E254u)
+
+/** \brief 1218, Register 134 - Receive IPV4 No Payload Frame Counter Register */
+#define ETH_RXIPV4_NO_PAYLOAD_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_RXIPV4_NO_PAYLOAD_FRAMES*)0xF001E218u)
+
+/** \brief 1258, Register 150 - Receive IPV4 No Payload Octet Counter Register */
+#define ETH_RXIPV4_NO_PAYLOAD_OCTETS /*lint --e(923)*/ (*(volatile Ifx_ETH_RXIPV4_NO_PAYLOAD_OCTETS*)0xF001E258u)
+
+/** \brief 1260, Register 152 - Receive IPV4 Fragmented Octet Counter Register */
+#define ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS /*lint --e(923)*/ (*(volatile Ifx_ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS*)0xF001E260u)
+
+/** \brief 1220, Register 136 - Receive IPV4 UDP Checksum Disabled Frame
+ * Counter Register */
+#define ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES*)0xF001E220u)
+
+/** \brief 1224, Register 137 - Receive IPV6 Good Frame Counter Register */
+#define ETH_RXIPV6_GOOD_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_RXIPV6_GOOD_FRAMES*)0xF001E224u)
+
+/** \brief 1264, Register 153 - Receive IPV6 Good Octet Counter Register */
+#define ETH_RXIPV6_GOOD_OCTETS /*lint --e(923)*/ (*(volatile Ifx_ETH_RXIPV6_GOOD_OCTETS*)0xF001E264u)
+
+/** \brief 1228, Register 138 - Receive IPV6 Header Error Frame Counter
+ * Register */
+#define ETH_RXIPV6_HEADER_ERROR_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_RXIPV6_HEADER_ERROR_FRAMES*)0xF001E228u)
+
+/** \brief 1268, Register 154 - Receive IPV6 Header Error Octet Counter
+ * Register */
+#define ETH_RXIPV6_HEADER_ERROR_OCTETS /*lint --e(923)*/ (*(volatile Ifx_ETH_RXIPV6_HEADER_ERROR_OCTETS*)0xF001E268u)
+
+/** \brief 122C, Register 139 - Receive IPV6 No Payload Frame Counter Register */
+#define ETH_RXIPV6_NO_PAYLOAD_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_RXIPV6_NO_PAYLOAD_FRAMES*)0xF001E22Cu)
+
+/** \brief 126C, Register 155 - Receive IPV6 No Payload Octet Counter Register */
+#define ETH_RXIPV6_NO_PAYLOAD_OCTETS /*lint --e(923)*/ (*(volatile Ifx_ETH_RXIPV6_NO_PAYLOAD_OCTETS*)0xF001E26Cu)
+
+/** \brief 123C, Register 143 - Receive TCP Error Frame Counter Register */
+#define ETH_RXTCP_ERROR_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_RXTCP_ERROR_FRAMES*)0xF001E23Cu)
+
+/** \brief 127C, Register 159 - Receive TCP Error Octet Counter Register */
+#define ETH_RXTCP_ERROR_OCTETS /*lint --e(923)*/ (*(volatile Ifx_ETH_RXTCP_ERROR_OCTETS*)0xF001E27Cu)
+
+/** \brief 1238, Register 142 - Receive TCP Good Frame Counter Register */
+#define ETH_RXTCP_GOOD_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_RXTCP_GOOD_FRAMES*)0xF001E238u)
+
+/** \brief 1278, Register 158 - Receive TCP Good Octet Counter Register */
+#define ETH_RXTCP_GOOD_OCTETS /*lint --e(923)*/ (*(volatile Ifx_ETH_RXTCP_GOOD_OCTETS*)0xF001E278u)
+
+/** \brief 1234, Register 141 - Receive UDP Error Frame Counter Register */
+#define ETH_RXUDP_ERROR_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_RXUDP_ERROR_FRAMES*)0xF001E234u)
+
+/** \brief 1274, Register 157 - Receive UDP Error Octet Counter Register */
+#define ETH_RXUDP_ERROR_OCTETS /*lint --e(923)*/ (*(volatile Ifx_ETH_RXUDP_ERROR_OCTETS*)0xF001E274u)
+
+/** \brief 1230, Register 140 - Receive UDP Good Frame Counter Register */
+#define ETH_RXUDP_GOOD_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_RXUDP_GOOD_FRAMES*)0xF001E230u)
+
+/** \brief 1270, Register 156 - Receive UDP Good Octet Counter Register */
+#define ETH_RXUDP_GOOD_OCTETS /*lint --e(923)*/ (*(volatile Ifx_ETH_RXUDP_GOOD_OCTETS*)0xF001E270u)
+
+/** \brief 2014, Register 5 - Status Register */
+#define ETH_STATUS /*lint --e(923)*/ (*(volatile Ifx_ETH_STATUS*)0xF001F014u)
+
+/** \brief 1704, Register 449 - Sub-Second Increment Register */
+#define ETH_SUB_SECOND_INCREMENT /*lint --e(923)*/ (*(volatile Ifx_ETH_SUB_SECOND_INCREMENT*)0xF001E704u)
+
+/** \brief 1724, Register 457 - System Time - Higher Word Seconds Register */
+#define ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS /*lint --e(923)*/ (*(volatile Ifx_ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS*)0xF001E724u)
+
+/** \brief 170C, Register 451 - System Time - Nanoseconds Register */
+#define ETH_SYSTEM_TIME_NANOSECONDS /*lint --e(923)*/ (*(volatile Ifx_ETH_SYSTEM_TIME_NANOSECONDS*)0xF001E70Cu)
+
+/** \brief 1714, Register 453 - System Time - Nanoseconds Update Register */
+#define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE /*lint --e(923)*/ (*(volatile Ifx_ETH_SYSTEM_TIME_NANOSECONDS_UPDATE*)0xF001E714u)
+
+/** \brief 1708, Register 450 - System Time - Seconds Register */
+#define ETH_SYSTEM_TIME_SECONDS /*lint --e(923)*/ (*(volatile Ifx_ETH_SYSTEM_TIME_SECONDS*)0xF001E708u)
+
+/** \brief 1710, Register 452 - System Time - Seconds Update Register */
+#define ETH_SYSTEM_TIME_SECONDS_UPDATE /*lint --e(923)*/ (*(volatile Ifx_ETH_SYSTEM_TIME_SECONDS_UPDATE*)0xF001E710u)
+
+/** \brief 1720, Register 456 - Target Time Nanoseconds Register */
+#define ETH_TARGET_TIME_NANOSECONDS /*lint --e(923)*/ (*(volatile Ifx_ETH_TARGET_TIME_NANOSECONDS*)0xF001E720u)
+
+/** \brief 171C, Register 455 - Target Time Seconds Register */
+#define ETH_TARGET_TIME_SECONDS /*lint --e(923)*/ (*(volatile Ifx_ETH_TARGET_TIME_SECONDS*)0xF001E71Cu)
+
+/** \brief 1718, Register 454 - Timestamp Addend Register */
+#define ETH_TIMESTAMP_ADDEND /*lint --e(923)*/ (*(volatile Ifx_ETH_TIMESTAMP_ADDEND*)0xF001E718u)
+
+/** \brief 1700, Register 448 - Timestamp Control Register */
+#define ETH_TIMESTAMP_CONTROL /*lint --e(923)*/ (*(volatile Ifx_ETH_TIMESTAMP_CONTROL*)0xF001E700u)
+
+/** \brief 1728, Register 458 - Timestamp Status Register */
+#define ETH_TIMESTAMP_STATUS /*lint --e(923)*/ (*(volatile Ifx_ETH_TIMESTAMP_STATUS*)0xF001E728u)
+
+/** \brief 2010, Register 4 - Transmit Descriptor List Address Register */
+#define ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS /*lint --e(923)*/ (*(volatile Ifx_ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS*)0xF001F010u)
+
+/** \brief 2004, Register 1 - Transmit Poll Demand Register */
+#define ETH_TRANSMIT_POLL_DEMAND /*lint --e(923)*/ (*(volatile Ifx_ETH_TRANSMIT_POLL_DEMAND*)0xF001F004u)
+
+/** \brief 1138, Register 78 - Transmit Octet Count for Good and Bad 1024 to
+ * Maxsize Bytes Frames */
+#define ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD /*lint --e(923)*/ (*(volatile Ifx_ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD*)0xF001E138u)
+
+/** \brief 112C, Register 75 - Transmit Octet Count for Good and Bad 128 to 255
+ * Bytes Frames */
+#define ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD /*lint --e(923)*/ (*(volatile Ifx_ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD*)0xF001E12Cu)
+
+/** \brief 1130, Register 76 - Transmit Octet Count for Good and Bad 256 to 511
+ * Bytes Frames */
+#define ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD /*lint --e(923)*/ (*(volatile Ifx_ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD*)0xF001E130u)
+
+/** \brief 1134, Register 77 - Transmit Octet Count for Good and Bad 512 to
+ * 1023 Bytes Frames */
+#define ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD /*lint --e(923)*/ (*(volatile Ifx_ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD*)0xF001E134u)
+
+/** \brief 1124, Register 73 - Transmit Octet Count for Good and Bad 64 Byte
+ * Frames */
+#define ETH_TX_64OCTETS_FRAMES_GOOD_BAD /*lint --e(923)*/ (*(volatile Ifx_ETH_TX_64OCTETS_FRAMES_GOOD_BAD*)0xF001E124u)
+
+/** \brief 1128, Register 74 - Transmit Octet Count for Good and Bad 65 to 127
+ * Bytes Frames */
+#define ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD /*lint --e(923)*/ (*(volatile Ifx_ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD*)0xF001E128u)
+
+/** \brief 111C, Register 71 - Transmit Frame Count for Good Broadcast Frames */
+#define ETH_TX_BROADCAST_FRAMES_GOOD /*lint --e(923)*/ (*(volatile Ifx_ETH_TX_BROADCAST_FRAMES_GOOD*)0xF001E11Cu)
+
+/** \brief 1144, Register 81 - Transmit Frame Count for Good and Bad Broadcast
+ * Frames */
+#define ETH_TX_BROADCAST_FRAMES_GOOD_BAD /*lint --e(923)*/ (*(volatile Ifx_ETH_TX_BROADCAST_FRAMES_GOOD_BAD*)0xF001E144u)
+
+/** \brief 1160, Register 88 - Transmit Frame Count for Carrier Sense Error
+ * Frames */
+#define ETH_TX_CARRIER_ERROR_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_TX_CARRIER_ERROR_FRAMES*)0xF001E160u)
+
+/** \brief 1154, Register 85 - Transmit Frame Count for Deferred Frames */
+#define ETH_TX_DEFERRED_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_TX_DEFERRED_FRAMES*)0xF001E154u)
+
+/** \brief 115C, Register 87 - Transmit Frame Count for Excessive Collision
+ * Error Frames */
+#define ETH_TX_EXCESSIVE_COLLISION_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_TX_EXCESSIVE_COLLISION_FRAMES*)0xF001E15Cu)
+
+/** \brief 116C, Register 91 - Transmit Frame Count for Excessive Deferral
+ * Error Frames */
+#define ETH_TX_EXCESSIVE_DEFERRAL_ERROR /*lint --e(923)*/ (*(volatile Ifx_ETH_TX_EXCESSIVE_DEFERRAL_ERROR*)0xF001E16Cu)
+
+/** \brief 1168, Register 90 - Transmit Frame Count for Good Frames */
+#define ETH_TX_FRAME_COUNT_GOOD /*lint --e(923)*/ (*(volatile Ifx_ETH_TX_FRAME_COUNT_GOOD*)0xF001E168u)
+
+/** \brief 1118, Register 70 - Transmit Frame Count for Good and Bad Frames */
+#define ETH_TX_FRAME_COUNT_GOOD_BAD /*lint --e(923)*/ (*(volatile Ifx_ETH_TX_FRAME_COUNT_GOOD_BAD*)0xF001E118u)
+
+/** \brief 1158, Register 86 - Transmit Frame Count for Late Collision Error
+ * Frames */
+#define ETH_TX_LATE_COLLISION_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_TX_LATE_COLLISION_FRAMES*)0xF001E158u)
+
+/** \brief 1120, Register 72 - Transmit Frame Count for Good Multicast Frames */
+#define ETH_TX_MULTICAST_FRAMES_GOOD /*lint --e(923)*/ (*(volatile Ifx_ETH_TX_MULTICAST_FRAMES_GOOD*)0xF001E120u)
+
+/** \brief 1140, Register 80 - Transmit Frame Count for Good and Bad Multicast
+ * Frames */
+#define ETH_TX_MULTICAST_FRAMES_GOOD_BAD /*lint --e(923)*/ (*(volatile Ifx_ETH_TX_MULTICAST_FRAMES_GOOD_BAD*)0xF001E140u)
+
+/** \brief 1150, Register 84 - Transmit Frame Count for Frames Transmitted
+ * after Multiple Collision */
+#define ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES*)0xF001E150u)
+
+/** \brief 1164, Register 89 - Transmit Octet Count for Good Frames */
+#define ETH_TX_OCTET_COUNT_GOOD /*lint --e(923)*/ (*(volatile Ifx_ETH_TX_OCTET_COUNT_GOOD*)0xF001E164u)
+
+/** \brief 1114, Register 69 - Transmit Octet Count for Good and Bad Frames */
+#define ETH_TX_OCTET_COUNT_GOOD_BAD /*lint --e(923)*/ (*(volatile Ifx_ETH_TX_OCTET_COUNT_GOOD_BAD*)0xF001E114u)
+
+/** \brief 1178, Register 94 - Transmit Frame Count for Good Oversize Frames */
+#define ETH_TX_OSIZE_FRAMES_GOOD /*lint --e(923)*/ (*(volatile Ifx_ETH_TX_OSIZE_FRAMES_GOOD*)0xF001E178u)
+
+/** \brief 1170, Register 92 - Transmit Frame Count for Good PAUSE Frames */
+#define ETH_TX_PAUSE_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_TX_PAUSE_FRAMES*)0xF001E170u)
+
+/** \brief 114C, Register 83 - Transmit Frame Count for Frames Transmitted
+ * after Single Collision */
+#define ETH_TX_SINGLE_COLLISION_GOOD_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_TX_SINGLE_COLLISION_GOOD_FRAMES*)0xF001E14Cu)
+
+/** \brief 1148, Register 82 - Transmit Frame Count for Underflow Error Frames */
+#define ETH_TX_UNDERFLOW_ERROR_FRAMES /*lint --e(923)*/ (*(volatile Ifx_ETH_TX_UNDERFLOW_ERROR_FRAMES*)0xF001E148u)
+
+/** \brief 113C, Register 79 - Transmit Frame Count for Good and Bad Unicast
+ * Frames */
+#define ETH_TX_UNICAST_FRAMES_GOOD_BAD /*lint --e(923)*/ (*(volatile Ifx_ETH_TX_UNICAST_FRAMES_GOOD_BAD*)0xF001E13Cu)
+
+/** \brief 1174, Register 93 - Transmit Frame Count for Good VLAN Frames */
+#define ETH_TX_VLAN_FRAMES_GOOD /*lint --e(923)*/ (*(volatile Ifx_ETH_TX_VLAN_FRAMES_GOOD*)0xF001E174u)
+
+/** \brief 1020, Register 8 - Version Register */
+#define ETH_VERSION /*lint --e(923)*/ (*(volatile Ifx_ETH_VERSION*)0xF001E020u)
+
+/** \brief 101C, Register 7 - VLAN Tag Register */
+#define ETH_VLAN_TAG /*lint --e(923)*/ (*(volatile Ifx_ETH_VLAN_TAG*)0xF001E01Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXETH_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEth_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEth_regdef.h
new file mode 100644
index 0000000..64e2c70
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxEth_regdef.h
@@ -0,0 +1,2712 @@
+/**
+ * \file IfxEth_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Eth Eth
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Eth_Bitfields Bitfields
+ * \ingroup IfxLld_Eth
+ *
+ * \defgroup IfxLld_Eth_union Union
+ * \ingroup IfxLld_Eth
+ *
+ * \defgroup IfxLld_Eth_struct Struct
+ * \ingroup IfxLld_Eth
+ *
+ */
+#ifndef IFXETH_REGDEF_H
+#define IFXETH_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Eth_Bitfields
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef struct _Ifx_ETH_ACCEN0_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_ETH_ACCEN0_Bits;
+
+/** \brief Access Enable Register 1 */
+typedef struct _Ifx_ETH_ACCEN1_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_ETH_ACCEN1_Bits;
+
+/** \brief Register 11 - AHB or AXI Status Register */
+typedef struct _Ifx_ETH_AHB_OR_AXI_STATUS_Bits
+{
+ unsigned int AXWHSTS:1; /**< \brief [0:0] AXI Master Write Channel or AHB Master Status (r) */
+ unsigned int AXIRDSTS:1; /**< \brief [1:1] AXI Master Read Channel Status (r) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_ETH_AHB_OR_AXI_STATUS_Bits;
+
+/** \brief Register 0 - Bus Mode Register */
+typedef struct _Ifx_ETH_BUS_MODE_Bits
+{
+ unsigned int SWR:1; /**< \brief [0:0] Software Reset (rw) */
+ unsigned int DA:1; /**< \brief [1:1] DMA Arbitration Scheme (rw) */
+ unsigned int DSL:5; /**< \brief [6:2] Descriptor Skip Length (rw) */
+ unsigned int ATDS:1; /**< \brief [7:7] Alternate Descriptor Size (rw) */
+ unsigned int PBL:6; /**< \brief [13:8] Programmable Burst Length (rw) */
+ unsigned int PR:2; /**< \brief [15:14] Priority Ratio (rw) */
+ unsigned int FB:1; /**< \brief [16:16] Fixed Burst (rw) */
+ unsigned int RPBL:6; /**< \brief [22:17] Rx DMA PBL (rw) */
+ unsigned int USP:1; /**< \brief [23:23] Use Seperate PBL (rw) */
+ unsigned int PBLx8:1; /**< \brief [24:24] PBLx8 Mode (rw) */
+ unsigned int AAL:1; /**< \brief [25:25] Address Aligned Beats (rw) */
+ unsigned int MB:1; /**< \brief [26:26] Mixed Burst (rw) */
+ unsigned int TXPR:1; /**< \brief [27:27] Transmit Priority (rw) */
+ unsigned int PRWG:2; /**< \brief [29:28] Channel Priority Weights (r) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_ETH_BUS_MODE_Bits;
+
+/** \brief Clock Control Register */
+typedef struct _Ifx_ETH_CLC_Bits
+{
+ unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
+ unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_ETH_CLC_Bits;
+
+/** \brief Register 21 - Current Host Receive Buffer Address Register */
+typedef struct _Ifx_ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_Bits
+{
+ unsigned int CURRBUFAPTR:32; /**< \brief [31:0] Host Receive Buffer Address Pointer (r) */
+} Ifx_ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_Bits;
+
+/** \brief Register 19 - Current Host Receive Descriptor Register */
+typedef struct _Ifx_ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_Bits
+{
+ unsigned int CURRDESAPTR:32; /**< \brief [31:0] Host Receive Descriptor Address Pointer (r) */
+} Ifx_ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_Bits;
+
+/** \brief Register 20 - Current Host Transmit Buffer Address Register */
+typedef struct _Ifx_ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_Bits
+{
+ unsigned int CURTBUFAPTR:32; /**< \brief [31:0] Host Transmit Buffer Address Pointer (r) */
+} Ifx_ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_Bits;
+
+/** \brief Register 18 - Current Host Transmit Descriptor Register */
+typedef struct _Ifx_ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_Bits
+{
+ unsigned int CURTDESAPTR:32; /**< \brief [31:0] Host Transmit Descriptor Address Pointer (r) */
+} Ifx_ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_Bits;
+
+/** \brief Register 9 - Debug Register */
+typedef struct _Ifx_ETH_DEBUG_Bits
+{
+ unsigned int RPESTS:1; /**< \brief [0:0] MAC GMII or MII Receive Protocol Engine Status (r) */
+ unsigned int RFCFCSTS:2; /**< \brief [2:1] MAC Receive Frame Controller FIFO Status (r) */
+ unsigned int reserved_3:1; /**< \brief \internal Reserved */
+ unsigned int RWCSTS:1; /**< \brief [4:4] MTL Rx FIFO Write Controller Active Status (r) */
+ unsigned int RRCSTS:2; /**< \brief [6:5] MTL Rx FIFO Read Controller State (r) */
+ unsigned int reserved_7:1; /**< \brief \internal Reserved */
+ unsigned int RXFSTS:2; /**< \brief [9:8] MTL Rx FIFO Fill-level Status (r) */
+ unsigned int reserved_10:6; /**< \brief \internal Reserved */
+ unsigned int TPESTS:1; /**< \brief [16:16] MAC GMII or MII Transmit Protocol Engine Status (r) */
+ unsigned int TFCSTS:2; /**< \brief [18:17] MAC Transmit Frame Controller Status (r) */
+ unsigned int TXPAUSED:1; /**< \brief [19:19] MAC transmitter in PAUSE (r) */
+ unsigned int TRCSTS:2; /**< \brief [21:20] MTL Tx FIFO Read Controller Status (r) */
+ unsigned int TWCSTS:1; /**< \brief [22:22] MTL Tx FIFO Write Controller Active Status (r) */
+ unsigned int reserved_23:1; /**< \brief \internal Reserved */
+ unsigned int TXFSTS:1; /**< \brief [24:24] MTL Tx FIFO Not Empty Status (r) */
+ unsigned int TXSTSFSTS:1; /**< \brief [25:25] MTL TxStatus FIFO Full Status (r) */
+ unsigned int reserved_26:6; /**< \brief \internal Reserved */
+} Ifx_ETH_DEBUG_Bits;
+
+/** \brief Register 6 - Flow Control Register */
+typedef struct _Ifx_ETH_FLOW_CONTROL_Bits
+{
+ unsigned int FCA_BPA:1; /**< \brief [0:0] Flow Control Busy or Backpressure Activate (rw) */
+ unsigned int TFE:1; /**< \brief [1:1] Transmit Flow Control Enable (rw) */
+ unsigned int RFE:1; /**< \brief [2:2] Receive Flow Control Enable (rw) */
+ unsigned int UP:1; /**< \brief [3:3] Unicast Pause Frame Detect (rw) */
+ unsigned int PLT:2; /**< \brief [5:4] Pause Low Threshold (rw) */
+ unsigned int reserved_6:1; /**< \brief \internal Reserved */
+ unsigned int DZPQ:1; /**< \brief [7:7] Disable Zero-Quanta Pause (rw) */
+ unsigned int reserved_8:8; /**< \brief \internal Reserved */
+ unsigned int PT:16; /**< \brief [31:16] Pause Time (rw) */
+} Ifx_ETH_FLOW_CONTROL_Bits;
+
+/** \brief Register 4 - GMII Address Register */
+typedef struct _Ifx_ETH_GMII_ADDRESS_Bits
+{
+ unsigned int GB:1; /**< \brief [0:0] GMII Busy (rw) */
+ unsigned int GW:1; /**< \brief [1:1] GMII Write (rw) */
+ unsigned int CR:4; /**< \brief [5:2] CSR Clock Range (rw) */
+ unsigned int GR:5; /**< \brief [10:6] GMII Register (rw) */
+ unsigned int PA:5; /**< \brief [15:11] Physical Layer Address (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_ETH_GMII_ADDRESS_Bits;
+
+/** \brief Register 5 - GMII Data Register */
+typedef struct _Ifx_ETH_GMII_DATA_Bits
+{
+ unsigned int GD:16; /**< \brief [15:0] GMII Data (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_ETH_GMII_DATA_Bits;
+
+/** \brief Input and Output Control Register */
+typedef struct _Ifx_ETH_GPCTL_Bits
+{
+ unsigned int ALTI0:2; /**< \brief [1:0] Alternate Input Select (rw) */
+ unsigned int ALTI1:2; /**< \brief [3:2] Alternate Input Select (rw) */
+ unsigned int ALTI2:2; /**< \brief [5:4] Alternate Input Select (rw) */
+ unsigned int ALTI3:2; /**< \brief [7:6] Alternate Input Select (rw) */
+ unsigned int ALTI4:2; /**< \brief [9:8] Alternate Input Select (rw) */
+ unsigned int ALTI5:2; /**< \brief [11:10] Alternate Input Select (rw) */
+ unsigned int ALTI6:2; /**< \brief [13:12] Alternate Input Select (rw) */
+ unsigned int ALTI7:2; /**< \brief [15:14] Alternate Input Select (rw) */
+ unsigned int ALTI8:2; /**< \brief [17:16] Alternate Input Select (rw) */
+ unsigned int ALTI9:2; /**< \brief [19:18] Alternate Input Select (rw) */
+ unsigned int ALTI10:2; /**< \brief [21:20] Alternate Input Select (rw) */
+ unsigned int reserved_22:2; /**< \brief \internal Reserved */
+ unsigned int EPR:1; /**< \brief [24:24] External Phy Interface RMMI Mode Bit (rw) */
+ unsigned int DIV:1; /**< \brief [25:25] Module Clock Divider Request Bit (rw) */
+ unsigned int reserved_26:6; /**< \brief \internal Reserved */
+} Ifx_ETH_GPCTL_Bits;
+
+/** \brief Register 2 - Hash Table High Register */
+typedef struct _Ifx_ETH_HASH_TABLE_HIGH_Bits
+{
+ unsigned int HTH:32; /**< \brief [31:0] Hash Table High (rw) */
+} Ifx_ETH_HASH_TABLE_HIGH_Bits;
+
+/** \brief Register 3 - Hash Table Low Register */
+typedef struct _Ifx_ETH_HASH_TABLE_LOW_Bits
+{
+ unsigned int HTL:32; /**< \brief [31:0] Hash Table Low (rw) */
+} Ifx_ETH_HASH_TABLE_LOW_Bits;
+
+/** \brief Register 22 - HW Feature Register */
+typedef struct _Ifx_ETH_HW_FEATURE_Bits
+{
+ unsigned int MIISEL:1; /**< \brief [0:0] MIISEL (r) */
+ unsigned int GMIISEL:1; /**< \brief [1:1] GMIISEL (r) */
+ unsigned int HDSEL:1; /**< \brief [2:2] HDSEL (r) */
+ unsigned int EXTHASHEN:1; /**< \brief [3:3] EXTHASHEN (r) */
+ unsigned int HASHSEL:1; /**< \brief [4:4] HASHSEL (r) */
+ unsigned int ADDMACADRSEL:1; /**< \brief [5:5] ADDMACADRSEL (r) */
+ unsigned int PCSSEL:1; /**< \brief [6:6] PCSSEL (r) */
+ unsigned int L3L4FLTREN:1; /**< \brief [7:7] L3L4FLTREN (r) */
+ unsigned int SMASEL:1; /**< \brief [8:8] SMASEL (r) */
+ unsigned int RWKSEL:1; /**< \brief [9:9] RWKSEL (r) */
+ unsigned int MGKSEL:1; /**< \brief [10:10] MGKSEL (r) */
+ unsigned int MMCSEL:1; /**< \brief [11:11] MMCSEL (r) */
+ unsigned int TSVER1SEL:1; /**< \brief [12:12] TSVER1SEL (r) */
+ unsigned int TSVER2SEL:1; /**< \brief [13:13] TSVER2SEL (r) */
+ unsigned int EEESEL:1; /**< \brief [14:14] EEESEL (r) */
+ unsigned int AVSEL:1; /**< \brief [15:15] AVSEL (r) */
+ unsigned int TXCOESEL:1; /**< \brief [16:16] TXCOESEL (r) */
+ unsigned int RXTYP1COE:1; /**< \brief [17:17] RXTYP1COE (r) */
+ unsigned int RXTYP2COE:1; /**< \brief [18:18] RXTYP2COE (r) */
+ unsigned int RXFIFOSIZE:1; /**< \brief [19:19] RXFIFOSIZE (rw) */
+ unsigned int RXCHCNT:2; /**< \brief [21:20] RXCHCNT (r) */
+ unsigned int TXCHCNT:2; /**< \brief [23:22] TXCHCNT (r) */
+ unsigned int ENHDESSEL:1; /**< \brief [24:24] ENHDESSEL (r) */
+ unsigned int INTTSEN:1; /**< \brief [25:25] INTTSEN (r) */
+ unsigned int FLEXIPPSEN:1; /**< \brief [26:26] FLEXIPPSEN (r) */
+ unsigned int SAVLANINS:1; /**< \brief [27:27] SAVLANINS (r) */
+ unsigned int ACTPHYIF:3; /**< \brief [30:28] Active or Selected PHY interface (r) */
+ unsigned int reserved_31:1; /**< \brief \internal Reserved */
+} Ifx_ETH_HW_FEATURE_Bits;
+
+/** \brief Module Identification Register */
+typedef struct _Ifx_ETH_ID_Bits
+{
+ unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
+ unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_ETH_ID_Bits;
+
+/** \brief Register 7 - Interrupt Enable Register */
+typedef struct _Ifx_ETH_INTERRUPT_ENABLE_Bits
+{
+ unsigned int TIE:1; /**< \brief [0:0] Transmit Interrupt Enable (rw) */
+ unsigned int TSE:1; /**< \brief [1:1] Transmit Stopped Enable (rw) */
+ unsigned int TUE:1; /**< \brief [2:2] Transmit Buffer Unvailable Enable (rw) */
+ unsigned int TJE:1; /**< \brief [3:3] Transmit Jabber Timeout Enable (rw) */
+ unsigned int OVE:1; /**< \brief [4:4] Overflow Interrupt Enable (rw) */
+ unsigned int UNE:1; /**< \brief [5:5] Underflow Interrupt Enable (rw) */
+ unsigned int RIE:1; /**< \brief [6:6] Receive Interrupt Enable (rw) */
+ unsigned int RUE:1; /**< \brief [7:7] Receive Buffer Unavailable Enable (rw) */
+ unsigned int RSE:1; /**< \brief [8:8] Receive Stopped Enable (rw) */
+ unsigned int RWE:1; /**< \brief [9:9] Receive Watchdog Timeout Enable (rw) */
+ unsigned int ETE:1; /**< \brief [10:10] Early Transmit Interrupt Enable (rw) */
+ unsigned int reserved_11:2; /**< \brief \internal Reserved */
+ unsigned int FBE:1; /**< \brief [13:13] Fatal Bus Error Enable (rw) */
+ unsigned int ERE:1; /**< \brief [14:14] Early Receive Interrupt Enable (rw) */
+ unsigned int AIE:1; /**< \brief [15:15] Abnormal Interrupt Summary Enable (rw) */
+ unsigned int NIE:1; /**< \brief [16:16] Normal Interrupt Summary Enable (rw) */
+ unsigned int reserved_17:15; /**< \brief \internal Reserved */
+} Ifx_ETH_INTERRUPT_ENABLE_Bits;
+
+/** \brief Register 15 - Interrupt Mask Register */
+typedef struct _Ifx_ETH_INTERRUPT_MASK_Bits
+{
+ unsigned int RGSMIIIM:1; /**< \brief [0:0] RGMII or SMII Interrupt Mask (r) */
+ unsigned int PCSLCHGIM:1; /**< \brief [1:1] PCS Link Status Interrupt Mask (r) */
+ unsigned int PCSANCIM:1; /**< \brief [2:2] PCS AN Completion Interrupt Mask (r) */
+ unsigned int PMTIM:1; /**< \brief [3:3] PMT Interrupt Mask (rw) */
+ unsigned int reserved_4:5; /**< \brief \internal Reserved */
+ unsigned int TSIM:1; /**< \brief [9:9] Timestamp Interrupt Mask (rw) */
+ unsigned int LPIIM:1; /**< \brief [10:10] LPI Interrupt Mask (r) */
+ unsigned int reserved_11:21; /**< \brief \internal Reserved */
+} Ifx_ETH_INTERRUPT_MASK_Bits;
+
+/** \brief Register 14 - Interrupt Register */
+typedef struct _Ifx_ETH_INTERRUPT_STATUS_Bits
+{
+ unsigned int RGSMIIIS:1; /**< \brief [0:0] RGMII or SMII Interrupt Status (r) */
+ unsigned int PCSLCHGIS:1; /**< \brief [1:1] PCS Link Status Changed (r) */
+ unsigned int PCSANCIS:1; /**< \brief [2:2] PCS Auto-Negotiation Complete (r) */
+ unsigned int PMTIS:1; /**< \brief [3:3] PMT Interrupt Status (r) */
+ unsigned int MMCIS:1; /**< \brief [4:4] MMC Interrupt Status (r) */
+ unsigned int MMCRXIS:1; /**< \brief [5:5] MMC Receive Interrupt Status (r) */
+ unsigned int MMCTXIS:1; /**< \brief [6:6] MMC Transmit Interrupt Status (r) */
+ unsigned int MMCRXIPIS:1; /**< \brief [7:7] MMC Receive Checksum Offload Interrupt Status (r) */
+ unsigned int reserved_8:1; /**< \brief \internal Reserved */
+ unsigned int TSIS:1; /**< \brief [9:9] Timestamp Interrupt Status (r) */
+ unsigned int LPIIS:1; /**< \brief [10:10] LPI Interrupt Status (r) */
+ unsigned int reserved_11:21; /**< \brief \internal Reserved */
+} Ifx_ETH_INTERRUPT_STATUS_Bits;
+
+/** \brief Kernel Reset Register 0 */
+typedef struct _Ifx_ETH_KRST0_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rh) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_ETH_KRST0_Bits;
+
+/** \brief Kernel Reset Register 1 */
+typedef struct _Ifx_ETH_KRST1_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_ETH_KRST1_Bits;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef struct _Ifx_ETH_KRSTCLR_Bits
+{
+ unsigned int CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_ETH_KRSTCLR_Bits;
+
+/** \brief MAC Address High Register */
+typedef struct _Ifx_ETH_MAC_ADDRESS_HIGH_Bits
+{
+ unsigned int ADDRHI:16; /**< \brief [15:0] (rw) */
+ unsigned int reserved_16:8; /**< \brief \internal Reserved */
+ unsigned int MBC:6; /**< \brief [29:24] (rw) */
+ unsigned int SA:1; /**< \brief [30:30] (rw) */
+ unsigned int AE:1; /**< \brief [31:31] (rw) */
+} Ifx_ETH_MAC_ADDRESS_HIGH_Bits;
+
+/** \brief MAC Address Low Register */
+typedef struct _Ifx_ETH_MAC_ADDRESS_LOW_Bits
+{
+ unsigned int ADDRLO:32; /**< \brief [31:0] (rw) */
+} Ifx_ETH_MAC_ADDRESS_LOW_Bits;
+
+/** \brief Register 0 - MAC Configuration Register */
+typedef struct _Ifx_ETH_MAC_CONFIGURATION_Bits
+{
+ unsigned int PRELEN:2; /**< \brief [1:0] Preamble Length for Transmit Frames (rw) */
+ unsigned int RE:1; /**< \brief [2:2] Receiver Enable (rw) */
+ unsigned int TE:1; /**< \brief [3:3] Transmitter Enable (rw) */
+ unsigned int DC:1; /**< \brief [4:4] Deferral Check (rw) */
+ unsigned int BL:2; /**< \brief [6:5] Back-Off Limit (rw) */
+ unsigned int ACS:1; /**< \brief [7:7] Automatic Pad or CRC Stripping (rw) */
+ unsigned int LUD:1; /**< \brief [8:8] Link Up or Down (r) */
+ unsigned int DR:1; /**< \brief [9:9] Disable Retry (rw) */
+ unsigned int IPC:1; /**< \brief [10:10] Checksum Offload (rw) */
+ unsigned int DM:1; /**< \brief [11:11] Duplex Mode (rw) */
+ unsigned int LM:1; /**< \brief [12:12] Loopback Mode (rw) */
+ unsigned int DO:1; /**< \brief [13:13] Disable Receive Own (rw) */
+ unsigned int FES:1; /**< \brief [14:14] Speed (rw) */
+ unsigned int PS:1; /**< \brief [15:15] Port Select (r) */
+ unsigned int DCRS:1; /**< \brief [16:16] Disable Carrier Sense During Transmission (rw) */
+ unsigned int IFG:3; /**< \brief [19:17] Inter-Frame Gap (rw) */
+ unsigned int JE:1; /**< \brief [20:20] Jumbo Frame Enable (rw) */
+ unsigned int BE:1; /**< \brief [21:21] Frame Burst Enable (r) */
+ unsigned int JD:1; /**< \brief [22:22] Jabber Disable (rw) */
+ unsigned int WD:1; /**< \brief [23:23] Watchdog Disable (rw) */
+ unsigned int TC:1; /**< \brief [24:24] Transmit Configuration in RGMII, SGMII, or SMII (r) */
+ unsigned int CST:1; /**< \brief [25:25] CRC Stripping of Type Frames (rw) */
+ unsigned int SFTERR:1; /**< \brief [26:26] SMII Force Transmit Error (r) */
+ unsigned int TWOKPE:1; /**< \brief [27:27] IEEE 802.3as support for 2K packets Enable (rw) */
+ unsigned int SARC:3; /**< \brief [30:28] Source Address Insertion or Replacement Control (r) */
+ unsigned int reserved_31:1; /**< \brief \internal Reserved */
+} Ifx_ETH_MAC_CONFIGURATION_Bits;
+
+/** \brief Register 1 - MAC Frame Filter */
+typedef struct _Ifx_ETH_MAC_FRAME_FILTER_Bits
+{
+ unsigned int PR:1; /**< \brief [0:0] Promiscuous Mode (rw) */
+ unsigned int HUC:1; /**< \brief [1:1] Hash Unicast (rw) */
+ unsigned int HMC:1; /**< \brief [2:2] Hash Multicast (rw) */
+ unsigned int DAIF:1; /**< \brief [3:3] DA Inverse Filtering (rw) */
+ unsigned int PM:1; /**< \brief [4:4] Pass All Multicast (rw) */
+ unsigned int DBF:1; /**< \brief [5:5] Disable Broadcast Frames (rw) */
+ unsigned int PCF:2; /**< \brief [7:6] Pass Control Frames (rw) */
+ unsigned int SAIF:1; /**< \brief [8:8] SA Inverse Filtering (rw) */
+ unsigned int SAF:1; /**< \brief [9:9] Source Address Filter Enable (rw) */
+ unsigned int HPF:1; /**< \brief [10:10] Hash or Perfect Filter (rw) */
+ unsigned int reserved_11:5; /**< \brief \internal Reserved */
+ unsigned int VTFE:1; /**< \brief [16:16] VLAN Tag Filter Enable (rw) */
+ unsigned int reserved_17:3; /**< \brief \internal Reserved */
+ unsigned int IPFE:1; /**< \brief [20:20] Layer 3 and Layer 4 Filter Enable (r) */
+ unsigned int DNTU:1; /**< \brief [21:21] Drop non-TCP/UDP over IP Frames (r) */
+ unsigned int reserved_22:9; /**< \brief \internal Reserved */
+ unsigned int RA:1; /**< \brief [31:31] Receive All (rw) */
+} Ifx_ETH_MAC_FRAME_FILTER_Bits;
+
+/** \brief Register 8 - Missed Frame and Buffer Overflow Counter Register */
+typedef struct _Ifx_ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_Bits
+{
+ unsigned int MISFRMCNT:16; /**< \brief [15:0] MISFRMCNT (r) */
+ unsigned int MISCNTOVF:1; /**< \brief [16:16] MISCNTOVF (r) */
+ unsigned int OVFFRMCNT:11; /**< \brief [27:17] OVFFRMCNT (r) */
+ unsigned int OVFCNTOVF:1; /**< \brief [28:28] OVFCNTOVF (r) */
+ unsigned int reserved_29:3; /**< \brief \internal Reserved */
+} Ifx_ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_Bits;
+
+/** \brief Register 64 - MMC Control Register */
+typedef struct _Ifx_ETH_MMC_CONTROL_Bits
+{
+ unsigned int CNTRST:1; /**< \brief [0:0] Counters Reset (rw) */
+ unsigned int CNTSTOPRO:1; /**< \brief [1:1] Counters Stop Rollover (rw) */
+ unsigned int RSTONRD:1; /**< \brief [2:2] Reset on Read (rw) */
+ unsigned int CNTFREEZ:1; /**< \brief [3:3] MMC Counter Freeze (rw) */
+ unsigned int CNTPRST:1; /**< \brief [4:4] Counters Preset (rw) */
+ unsigned int CNTPRSTLVL:1; /**< \brief [5:5] Full-Half Preset (rw) */
+ unsigned int reserved_6:2; /**< \brief \internal Reserved */
+ unsigned int UCDBC:1; /**< \brief [8:8] Update MMC Counters for Dropped Broadcast Frames (rw) */
+ unsigned int reserved_9:23; /**< \brief \internal Reserved */
+} Ifx_ETH_MMC_CONTROL_Bits;
+
+/** \brief Register 130 - MMC Receive Checksum Offload Interrupt Register */
+typedef struct _Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits
+{
+ unsigned int RXIPV4GFIS:1; /**< \brief [0:0] MMC Receive IPV4 Good Frame Counter Interrupt Status (r) */
+ unsigned int RXIPV4HERFIS:1; /**< \brief [1:1] MMC Receive IPV4 Header Error Frame Counter Interrupt Status (r) */
+ unsigned int RXIPV4NOPAYFIS:1; /**< \brief [2:2] MMC Receive IPV4 No Payload Frame Counter Interrupt Status (r) */
+ unsigned int RXIPV4FRAGFIS:1; /**< \brief [3:3] MMC Receive IPV4 Fragmented Frame Counter Interrupt Status (r) */
+ unsigned int RXIPV4UDSBLFIS:1; /**< \brief [4:4] MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status (r) */
+ unsigned int RXIPV6GFIS:1; /**< \brief [5:5] MMC Receive IPV6 Good Frame Counter Interrupt Status (r) */
+ unsigned int RXIPV6HERFIS:1; /**< \brief [6:6] MMC Receive IPV6 Header Error Frame Counter Interrupt Status (r) */
+ unsigned int RXIPV6NOPAYFIS:1; /**< \brief [7:7] MMC Receive IPV6 No Payload Frame Counter Interrupt Status (r) */
+ unsigned int RXUDPGFIS:1; /**< \brief [8:8] MMC Receive UDP Good Frame Counter Interrupt Status (r) */
+ unsigned int RXUDPERFIS:1; /**< \brief [9:9] MMC Receive UDP Error Frame Counter Interrupt Status (r) */
+ unsigned int RXTCPGFIS:1; /**< \brief [10:10] MMC Receive TCP Good Frame Counter Interrupt Status (r) */
+ unsigned int RXTCPERFIS:1; /**< \brief [11:11] MMC Receive TCP Error Frame Counter Interrupt Status (r) */
+ unsigned int RXICMPGFIS:1; /**< \brief [12:12] MMC Receive ICMP Good Frame Counter Interrupt Status (r) */
+ unsigned int RXICMPERFIS:1; /**< \brief [13:13] MMC Receive ICMP Error Frame Counter Interrupt Status (r) */
+ unsigned int reserved_14:2; /**< \brief \internal Reserved */
+ unsigned int RXIPV4GOIS:1; /**< \brief [16:16] MMC Receive IPV4 Good Octet Counter Interrupt Status (r) */
+ unsigned int RXIPV4HEROIS:1; /**< \brief [17:17] MMC Receive IPV4 Header Error Octet Counter Interrupt Status (r) */
+ unsigned int RXIPV4NOPAYOIS:1; /**< \brief [18:18] MMC Receive IPV4 No Payload Octet Counter Interrupt Status (r) */
+ unsigned int RXIPV4FRAGOIS:1; /**< \brief [19:19] MMC Receive IPV4 Fragmented Octet Counter Interrupt Status (r) */
+ unsigned int RXIPV4UDSBLOIS:1; /**< \brief [20:20] MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status (r) */
+ unsigned int RXIPV6GOIS:1; /**< \brief [21:21] MMC Receive IPV6 Good Octet Counter Interrupt Status (r) */
+ unsigned int RXIPV6HEROIS:1; /**< \brief [22:22] MMC Receive IPV6 Header Error Octet Counter Interrupt Status (r) */
+ unsigned int RXIPV6NOPAYOIS:1; /**< \brief [23:23] MMC Receive IPV6 No Payload Octet Counter Interrupt Status (r) */
+ unsigned int RXUDPGOIS:1; /**< \brief [24:24] MMC Receive UDP Good Octet Counter Interrupt Status (r) */
+ unsigned int RXUDPEROIS:1; /**< \brief [25:25] MMC Receive UDP Error Octet Counter Interrupt Status (r) */
+ unsigned int RXTCPGOIS:1; /**< \brief [26:26] MMC Receive TCP Good Octet Counter Interrupt Status (r) */
+ unsigned int RXTCPEROIS:1; /**< \brief [27:27] MMC Receive TCP Error Octet Counter Interrupt Status (r) */
+ unsigned int RXICMPGOIS:1; /**< \brief [28:28] MMC Receive ICMP Good Octet Counter Interrupt Status (r) */
+ unsigned int RXICMPEROIS:1; /**< \brief [29:29] MMC Receive ICMP Error Octet Counter Interrupt Status (r) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits;
+
+/** \brief Register 128 - MMC Receive Checksum Offload Interrupt Mask Register */
+typedef struct _Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits
+{
+ unsigned int RXIPV4GFIM:1; /**< \brief [0:0] MMC Receive IPV4 Good Frame Counter Interrupt Mask (rw) */
+ unsigned int RXIPV4HERFIM:1; /**< \brief [1:1] MMC Receive IPV4 Header Error Frame Counter Interrupt Mask (rw) */
+ unsigned int RXIPV4NOPAYFIM:1; /**< \brief [2:2] MMC Receive IPV4 No Payload Frame Counter Interrupt Mask (rw) */
+ unsigned int RXIPV4FRAGFIM:1; /**< \brief [3:3] MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask (rw) */
+ unsigned int RXIPV4UDSBLFIM:1; /**< \brief [4:4] MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask (rw) */
+ unsigned int RXIPV6GFIM:1; /**< \brief [5:5] MMC Receive IPV6 Good Frame Counter Interrupt Mask (rw) */
+ unsigned int RXIPV6HERFIM:1; /**< \brief [6:6] MMC Receive IPV6 Header Error Frame Counter Interrupt Mask (rw) */
+ unsigned int RXIPV6NOPAYFIM:1; /**< \brief [7:7] MMC Receive IPV6 No Payload Frame Counter Interrupt Mask (rw) */
+ unsigned int RXUDPGFIM:1; /**< \brief [8:8] MMC Receive UDP Good Frame Counter Interrupt Mask (rw) */
+ unsigned int RXUDPERFIM:1; /**< \brief [9:9] MMC Receive UDP Error Frame Counter Interrupt Mask (rw) */
+ unsigned int RXTCPGFIM:1; /**< \brief [10:10] MMC Receive TCP Good Frame Counter Interrupt Mask (rw) */
+ unsigned int RXTCPERFIM:1; /**< \brief [11:11] MMC Receive TCP Error Frame Counter Interrupt Mask (rw) */
+ unsigned int RXICMPGFIM:1; /**< \brief [12:12] MMC Receive ICMP Good Frame Counter Interrupt Mask (rw) */
+ unsigned int RXICMPERFIM:1; /**< \brief [13:13] MMC Receive ICMP Error Frame Counter Interrupt Mask (rw) */
+ unsigned int reserved_14:2; /**< \brief \internal Reserved */
+ unsigned int RXIPV4GOIM:1; /**< \brief [16:16] MMC Receive IPV4 Good Octet Counter Interrupt Mask (rw) */
+ unsigned int RXIPV4HEROIM:1; /**< \brief [17:17] MMC Receive IPV4 Header Error Octet Counter Interrupt Mask (rw) */
+ unsigned int RXIPV4NOPAYOIM:1; /**< \brief [18:18] MMC Receive IPV4 No Payload Octet Counter Interrupt Mask (rw) */
+ unsigned int RXIPV4FRAGOIM:1; /**< \brief [19:19] MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask (rw) */
+ unsigned int RXIPV4UDSBLOIM:1; /**< \brief [20:20] MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask (rw) */
+ unsigned int RXIPV6GOIM:1; /**< \brief [21:21] MMC Receive IPV6 Good Octet Counter Interrupt Mask (rw) */
+ unsigned int RXIPV6HEROIM:1; /**< \brief [22:22] MMC Receive IPV6 Header Error Octet Counter Interrupt Mask (rw) */
+ unsigned int RXIPV6NOPAYOIM:1; /**< \brief [23:23] MMC Receive IPV6 No Payload Octet Counter Interrupt Mask (rw) */
+ unsigned int RXUDPGOIM:1; /**< \brief [24:24] MMC Receive UDP Good Octet Counter Interrupt Mask (rw) */
+ unsigned int RXUDPEROIM:1; /**< \brief [25:25] MMC Receive UDP Error Octet Counter Interrupt Mask (rw) */
+ unsigned int RXTCPGOIM:1; /**< \brief [26:26] MMC Receive TCP Good Octet Counter Interrupt Mask (rw) */
+ unsigned int RXTCPEROIM:1; /**< \brief [27:27] MMC Receive TCP Error Octet Counter Interrupt Mask (rw) */
+ unsigned int RXICMPGOIM:1; /**< \brief [28:28] MMC Receive ICMP Good Octet Counter Interrupt Mask (rw) */
+ unsigned int RXICMPEROIM:1; /**< \brief [29:29] MMC Receive ICMP Error Octet Counter Interrupt Mask (rw) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits;
+
+/** \brief Register 65 - MMC Receive Interrupt Register */
+typedef struct _Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits
+{
+ unsigned int RXGBFRMIS:1; /**< \brief [0:0] MMC Receive Good Bad Frame Counter Interrupt Status (r) */
+ unsigned int RXGBOCTIS:1; /**< \brief [1:1] MMC Receive Good Bad Octet Counter Interrupt Status (r) */
+ unsigned int RXGOCTIS:1; /**< \brief [2:2] MMC Receive Good Octet Counter Interrupt Status. (r) */
+ unsigned int RXBCGFIS:1; /**< \brief [3:3] MMC Receive Broadcast Good Frame Counter Interrupt Status. (r) */
+ unsigned int RXMCGFIS:1; /**< \brief [4:4] MMC Receive Multicast Good Frame Counter Interrupt Status (r) */
+ unsigned int RXCRCERFIS:1; /**< \brief [5:5] MMC Receive CRC Error Frame Counter Interrupt Status (r) */
+ unsigned int RXALGNERFIS:1; /**< \brief [6:6] MMC Receive Alignment Error Frame Counter Interrupt Status (r) */
+ unsigned int RXRUNTFIS:1; /**< \brief [7:7] MMC Receive Runt Frame Counter Interrupt Status (r) */
+ unsigned int RXJABERFIS:1; /**< \brief [8:8] MMC Receive Jabber Error Frame Counter Interrupt Status (r) */
+ unsigned int RXUSIZEGFIS:1; /**< \brief [9:9] MMC Receive Undersize Good Frame Counter Interrupt Status (r) */
+ unsigned int RXOSIZEGFIS:1; /**< \brief [10:10] MMC Receive Oversize Good Frame Counter Interrupt Status (r) */
+ unsigned int RX64OCTGBFIS:1; /**< \brief [11:11] MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status (r) */
+ unsigned int RX65T127OCTGBFIS:1; /**< \brief [12:12] MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status (r) */
+ unsigned int RX128T255OCTGBFIS:1; /**< \brief [13:13] MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status (r) */
+ unsigned int RX256T511OCTGBFIS:1; /**< \brief [14:14] MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status (r) */
+ unsigned int RX512T1023OCTGBFIS:1; /**< \brief [15:15] MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status (r) */
+ unsigned int RX1024TMAXOCTGBFIS:1; /**< \brief [16:16] MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status (r) */
+ unsigned int RXUCGFIS:1; /**< \brief [17:17] MMC Receive Unicast Good Frame Counter Interrupt Status (r) */
+ unsigned int RXLENERFIS:1; /**< \brief [18:18] MMC Receive Length Error Frame Counter Interrupt Status (r) */
+ unsigned int RXORANGEFIS:1; /**< \brief [19:19] MMC Receive Out Of Range Error Frame Counter Interrupt Status (r) */
+ unsigned int RXPAUSFIS:1; /**< \brief [20:20] MMC Receive Pause Frame Counter Interrupt Status (r) */
+ unsigned int RXFOVFIS:1; /**< \brief [21:21] MMC Receive FIFO Overflow Frame Counter Interrupt Status (r) */
+ unsigned int RXVLANGBFIS:1; /**< \brief [22:22] MMC Receive VLAN Good Bad Frame Counter Interrupt Status (r) */
+ unsigned int RXWDOGFIS:1; /**< \brief [23:23] MMC Receive Watchdog Error Frame Counter Interrupt Status (r) */
+ unsigned int RXRCVERRFIS:1; /**< \brief [24:24] MMC Receive Error Frame Counter Interrupt Status (r) */
+ unsigned int RXCTRLFIS:1; /**< \brief [25:25] MMC Receive Control Frame Counter Interrupt Status (r) */
+ unsigned int reserved_26:6; /**< \brief \internal Reserved */
+} Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits;
+
+/** \brief - */
+typedef struct _Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits
+{
+ unsigned int RXGBFRMIM:1; /**< \brief [0:0] MMC Receive Good Bad Frame Counter Interrupt Mask (rw) */
+ unsigned int RXGBOCTIM:1; /**< \brief [1:1] MMC Receive Good Bad Octet Counter Interrupt Mask (rw) */
+ unsigned int RXGOCTIM:1; /**< \brief [2:2] MMC Receive Good Octet Counter Interrupt Mask (rw) */
+ unsigned int RXBCGFIM:1; /**< \brief [3:3] MMC Receive Broadcast Good Frame Counter Interrupt Mask (rw) */
+ unsigned int RXMCGFIM:1; /**< \brief [4:4] MMC Receive Multicast Good Frame Counter Interrupt Mask (rw) */
+ unsigned int RXCRCERFIM:1; /**< \brief [5:5] MMC Receive CRC Error Frame Counter Interrupt Mask (rw) */
+ unsigned int RXALGNERFIM:1; /**< \brief [6:6] MMC Receive Alignment Error Frame Counter Interrupt Mask (rw) */
+ unsigned int RXRUNTFIM:1; /**< \brief [7:7] MMC Receive Runt Frame Counter Interrupt Mask (rw) */
+ unsigned int RXJABERFIM:1; /**< \brief [8:8] MMC Receive Jabber Error Frame Counter Interrupt Mask (rw) */
+ unsigned int RXUSIZEGFIM:1; /**< \brief [9:9] MMC Receive Undersize Good Frame Counter Interrupt Mask (rw) */
+ unsigned int RXOSIZEGFIM:1; /**< \brief [10:10] MMC Receive Oversize Good Frame Counter Interrupt Mask (rw) */
+ unsigned int RX64OCTGBFIM:1; /**< \brief [11:11] MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask (rw) */
+ unsigned int RX65T127OCTGBFIM:1; /**< \brief [12:12] MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask (rw) */
+ unsigned int RX128T255OCTGBFIM:1; /**< \brief [13:13] MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask (rw) */
+ unsigned int RX256T511OCTGBFIM:1; /**< \brief [14:14] MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask (rw) */
+ unsigned int RX512T1023OCTGBFIM:1; /**< \brief [15:15] MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask (rw) */
+ unsigned int RX1024TMAXOCTGBFIM:1; /**< \brief [16:16] MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask (rw) */
+ unsigned int RXUCGFIM:1; /**< \brief [17:17] MMC Receive Unicast Good Frame Counter Interrupt Mask (rw) */
+ unsigned int RXLENERFIM:1; /**< \brief [18:18] MMC Receive Length Error Frame Counter Interrupt Mask (rw) */
+ unsigned int RXORANGEFIM:1; /**< \brief [19:19] MMC Receive Out Of Range Error Frame Counter Interrupt Mask (rw) */
+ unsigned int RXPAUSFIM:1; /**< \brief [20:20] MMC Receive Pause Frame Counter Interrupt Mask (rw) */
+ unsigned int RXFOVFIM:1; /**< \brief [21:21] MMC Receive FIFO Overflow Frame Counter Interrupt Mask (rw) */
+ unsigned int RXVLANGBFIM:1; /**< \brief [22:22] MMC Receive VLAN Good Bad Frame Counter Interrupt Mask (rw) */
+ unsigned int RXWDOGFIM:1; /**< \brief [23:23] MMC Receive Watchdog Error Frame Counter Interrupt Mask (rw) */
+ unsigned int RXRCVERRFIM:1; /**< \brief [24:24] MMC Receive Error Frame Counter Interrupt Mask (rw) */
+ unsigned int RXCTRLFIM:1; /**< \brief [25:25] MMC Receive Control Frame Counter Interrupt Mask (rw) */
+ unsigned int reserved_26:6; /**< \brief \internal Reserved */
+} Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits;
+
+/** \brief Register 66 - MMC Transmit Interrupt Register */
+typedef struct _Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits
+{
+ unsigned int TXGBOCTIS:1; /**< \brief [0:0] MMC Transmit Good Bad Octet Counter Interrupt Status (r) */
+ unsigned int TXGBFRMIS:1; /**< \brief [1:1] MMC Transmit Good Bad Frame Counter Interrupt Status (r) */
+ unsigned int TXBCGFIS:1; /**< \brief [2:2] MMC Transmit Broadcast Good Frame Counter Interrupt Status (r) */
+ unsigned int TXMCGFIS:1; /**< \brief [3:3] MMC Transmit Multicast Good Frame Counter Interrupt Status (r) */
+ unsigned int TX64OCTGBFIS:1; /**< \brief [4:4] MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status. (r) */
+ unsigned int TX65T127OCTGBFIS:1; /**< \brief [5:5] MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status (r) */
+ unsigned int TX128T255OCTGBFIS:1; /**< \brief [6:6] MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status (r) */
+ unsigned int TX256T511OCTGBFIS:1; /**< \brief [7:7] MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status (r) */
+ unsigned int TX512T1023OCTGBFIS:1; /**< \brief [8:8] MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status (r) */
+ unsigned int TX1024TMAXOCTGBFIS:1; /**< \brief [9:9] MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status (r) */
+ unsigned int TXUCGBFIS:1; /**< \brief [10:10] MMC Transmit Unicast Good Bad Frame Counter Interrupt Status (r) */
+ unsigned int TXMCGBFIS:1; /**< \brief [11:11] MMC Transmit Multicast Good Bad Frame Counter Interrupt Status (r) */
+ unsigned int TXBCGBFIS:1; /**< \brief [12:12] MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status (r) */
+ unsigned int TXUFLOWERFIS:1; /**< \brief [13:13] MMC Transmit Underflow Error Frame Counter Interrupt Status (r) */
+ unsigned int TXSCOLGFIS:1; /**< \brief [14:14] MMC Transmit Single Collision Good Frame Counter Interrupt Status (r) */
+ unsigned int TXMCOLGFIS:1; /**< \brief [15:15] MMC Transmit Multiple Collision Good Frame Counter Interrupt Status (r) */
+ unsigned int TXDEFFIS:1; /**< \brief [16:16] MMC Transmit Deferred Frame Counter Interrupt Status (r) */
+ unsigned int TXLATCOLFIS:1; /**< \brief [17:17] MMC Transmit Late Collision Frame Counter Interrupt Status (r) */
+ unsigned int TXEXCOLFIS:1; /**< \brief [18:18] MMC Transmit Excessive Collision Frame Counter Interrupt Status (r) */
+ unsigned int TXCARERFIS:1; /**< \brief [19:19] MMC Transmit Carrier Error Frame Counter Interrupt Status (r) */
+ unsigned int TXGOCTIS:1; /**< \brief [20:20] MMC Transmit Good Octet Counter Interrupt Status (r) */
+ unsigned int TXGFRMIS:1; /**< \brief [21:21] MMC Transmit Good Frame Counter Interrupt Status (r) */
+ unsigned int TXEXDEFFIS:1; /**< \brief [22:22] MMC Transmit Excessive Deferral Frame Counter Interrupt Status (r) */
+ unsigned int TXPAUSFIS:1; /**< \brief [23:23] MMC Transmit Pause Frame Counter Interrupt Status (r) */
+ unsigned int TXVLANGFIS:1; /**< \brief [24:24] MMC Transmit VLAN Good Frame Counter Interrupt Status (r) */
+ unsigned int TXOSIZEGFIS:1; /**< \brief [25:25] MMC Transmit Oversize Good Frame Counter Interrupt Status (r) */
+ unsigned int reserved_26:6; /**< \brief \internal Reserved */
+} Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits;
+
+/** \brief Register 68 - MMC Transmit Interrupt Mask Register */
+typedef struct _Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits
+{
+ unsigned int TXGBOCTIM:1; /**< \brief [0:0] MMC Transmit Good Bad Octet Counter Interrupt Mask (rw) */
+ unsigned int TXGBFRMIM:1; /**< \brief [1:1] MMC Transmit Good Bad Frame Counter Interrupt Mask (rw) */
+ unsigned int TXBCGFIM:1; /**< \brief [2:2] MMC Transmit Broadcast Good Frame Counter Interrupt Mask (rw) */
+ unsigned int TXMCGFIM:1; /**< \brief [3:3] MMC Transmit Multicast Good Frame Counter Interrupt Mask (rw) */
+ unsigned int TX64OCTGBFIM:1; /**< \brief [4:4] MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask (rw) */
+ unsigned int TX65T127OCTGBFIM:1; /**< \brief [5:5] MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask (rw) */
+ unsigned int TX128T255OCTGBFIM:1; /**< \brief [6:6] MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask (rw) */
+ unsigned int TX256T511OCTGBFIM:1; /**< \brief [7:7] MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask (rw) */
+ unsigned int TX512T1023OCTGBFIM:1; /**< \brief [8:8] MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask (rw) */
+ unsigned int TX1024TMAXOCTGBFIM:1; /**< \brief [9:9] MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask (rw) */
+ unsigned int TXUCGBFIM:1; /**< \brief [10:10] MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask (rw) */
+ unsigned int TXMCGBFIM:1; /**< \brief [11:11] MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask (rw) */
+ unsigned int TXBCGBFIM:1; /**< \brief [12:12] MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask (rw) */
+ unsigned int TXUFLOWERFIM:1; /**< \brief [13:13] MMC Transmit Underflow Error Frame Counter Interrupt Mask (rw) */
+ unsigned int TXSCOLGFIM:1; /**< \brief [14:14] MMC Transmit Single Collision Good Frame Counter Interrupt Mask (rw) */
+ unsigned int TXMCOLGFIM:1; /**< \brief [15:15] MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask (rw) */
+ unsigned int TXDEFFIM:1; /**< \brief [16:16] MMC Transmit Deferred Frame Counter Interrupt Mask (rw) */
+ unsigned int TXLATCOLFIM:1; /**< \brief [17:17] MMC Transmit Late Collision Frame Counter Interrupt Mask (rw) */
+ unsigned int TXEXCOLFIM:1; /**< \brief [18:18] MMC Transmit Excessive Collision Frame Counter Interrupt Mask (rw) */
+ unsigned int TXCARERFIM:1; /**< \brief [19:19] MMC Transmit Carrier Error Frame Counter Interrupt Mask (rw) */
+ unsigned int TXGOCTIM:1; /**< \brief [20:20] MMC Transmit Good Octet Counter Interrupt Mask (rw) */
+ unsigned int TXGFRMIM:1; /**< \brief [21:21] MMC Transmit Good Frame Counter Interrupt Mask (rw) */
+ unsigned int TXEXDEFFIM:1; /**< \brief [22:22] MMC Transmit Excessive Deferral Frame Counter Interrupt Mask (rw) */
+ unsigned int TXPAUSFIM:1; /**< \brief [23:23] MMC Transmit Pause Frame Counter Interrupt Mask (rw) */
+ unsigned int TXVLANGFIM:1; /**< \brief [24:24] MMC Transmit VLAN Good Frame Counter Interrupt Mask (rw) */
+ unsigned int TXOSIZEGFIM:1; /**< \brief [25:25] MMC Transmit Oversize Good Frame Counter Interrupt Mask (rw) */
+ unsigned int reserved_26:6; /**< \brief \internal Reserved */
+} Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits;
+
+/** \brief Register 6 - Operation Mode Register */
+typedef struct _Ifx_ETH_OPERATION_MODE_Bits
+{
+ unsigned int reserved_0:1; /**< \brief \internal Reserved */
+ unsigned int SR:1; /**< \brief [1:1] Start or Stop Receive (rw) */
+ unsigned int OSF:1; /**< \brief [2:2] Operate on Second Frame (rw) */
+ unsigned int RTC:2; /**< \brief [4:3] Receive Threshold Control (rw) */
+ unsigned int reserved_5:1; /**< \brief \internal Reserved */
+ unsigned int FUF:1; /**< \brief [6:6] Forward Undersized Good Frames (rw) */
+ unsigned int FEF:1; /**< \brief [7:7] Forward Error Frames (rw) */
+ unsigned int EFC:1; /**< \brief [8:8] Enable HW Flow Control (rw) */
+ unsigned int RFA:2; /**< \brief [10:9] Threshold for Activating Flow Control (in half-duplex and full-duplex) (rw) */
+ unsigned int RFD:2; /**< \brief [12:11] Threshold for Deactivating Flow Control (in half-duplex and full-duplex) (rw) */
+ unsigned int ST:1; /**< \brief [13:13] Start or Stop Transmission Command (rw) */
+ unsigned int TTC:3; /**< \brief [16:14] Transmit Threshold Control (rw) */
+ unsigned int reserved_17:3; /**< \brief \internal Reserved */
+ unsigned int FTF:1; /**< \brief [20:20] Flush Transmit FIFO (rw) */
+ unsigned int TSF:1; /**< \brief [21:21] Transmit Store and Forward (rw) */
+ unsigned int RFD_2:1; /**< \brief [22:22] MSB of Threshold for Deactivating Flow Control (r) */
+ unsigned int RFA_2:1; /**< \brief [23:23] MSB of Threshold for Activating Flow Control (r) */
+ unsigned int DFF:1; /**< \brief [24:24] Disable Flushing of Received Frames (rw) */
+ unsigned int RSF:1; /**< \brief [25:25] Receive Store and Forward (rw) */
+ unsigned int DT:1; /**< \brief [26:26] Disable Dropping of TCP/IP Checksum Error Frames (rw) */
+ unsigned int reserved_27:5; /**< \brief \internal Reserved */
+} Ifx_ETH_OPERATION_MODE_Bits;
+
+/** \brief Register 11 - PMT Control and Status Register */
+typedef struct _Ifx_ETH_PMT_CONTROL_STATUS_Bits
+{
+ unsigned int PWRDWN:1; /**< \brief [0:0] Power Down (rw) */
+ unsigned int MGKPKTEN:1; /**< \brief [1:1] Magic Packet Enable (rw) */
+ unsigned int RWKPKTEN:1; /**< \brief [2:2] Wake-Up Frame Enable (rw) */
+ unsigned int reserved_3:2; /**< \brief \internal Reserved */
+ unsigned int MGKPRCVD:1; /**< \brief [5:5] Magic Packet Received (r) */
+ unsigned int RWKPRCVD:1; /**< \brief [6:6] Wake-Up Frame Received (r) */
+ unsigned int reserved_7:2; /**< \brief \internal Reserved */
+ unsigned int GLBLUCAST:1; /**< \brief [9:9] Global Unicast (rw) */
+ unsigned int reserved_10:21; /**< \brief \internal Reserved */
+ unsigned int RWKFILTRST:1; /**< \brief [31:31] Wake-Up Frame Filter Register Pointer Reset (rw) */
+} Ifx_ETH_PMT_CONTROL_STATUS_Bits;
+
+/** \brief Register 459 - PPS Control Register */
+typedef struct _Ifx_ETH_PPS_CONTROL_Bits
+{
+ unsigned int PPSCTRL_PPSCMD:4; /**< \brief [3:0] PPSCTRL0 or PPSCMD0 (rw) */
+ unsigned int PPSEN0:1; /**< \brief [4:4] Flexible PPS Output Mode Enable (r) */
+ unsigned int TRGTMODSEL0:2; /**< \brief [6:5] Target Time Register Mode for PPS0 Output (r) */
+ unsigned int reserved_7:1; /**< \brief \internal Reserved */
+ unsigned int PPSCMD1:3; /**< \brief [10:8] Flexible PPS1 Output Control (r) */
+ unsigned int reserved_11:2; /**< \brief \internal Reserved */
+ unsigned int TRGTMODSEL1:2; /**< \brief [14:13] Target Time Register Mode for PPS1 Output (r) */
+ unsigned int reserved_15:1; /**< \brief \internal Reserved */
+ unsigned int PPSCMD2:3; /**< \brief [18:16] Flexible PPS2 Output Control (r) */
+ unsigned int reserved_19:2; /**< \brief \internal Reserved */
+ unsigned int TRGTMODSEL2:2; /**< \brief [22:21] Target Time Register Mode for PPS2 Output (r) */
+ unsigned int reserved_23:1; /**< \brief \internal Reserved */
+ unsigned int PPSCMD3:3; /**< \brief [26:24] Flexible PPS3 Output Control (r) */
+ unsigned int reserved_27:2; /**< \brief \internal Reserved */
+ unsigned int TRGTMODSEL3:2; /**< \brief [30:29] Target Time Register Mode for PPS3 Output (r) */
+ unsigned int reserved_31:1; /**< \brief \internal Reserved */
+} Ifx_ETH_PPS_CONTROL_Bits;
+
+/** \brief Register 3 - Receive Descriptor List Address Register */
+typedef struct _Ifx_ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_Bits
+{
+ unsigned int reserved_0:2; /**< \brief \internal Reserved */
+ unsigned int RDESLA:30; /**< \brief [31:2] Start of Receive List (rw) */
+} Ifx_ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_Bits;
+
+/** \brief Register 9 - Receive Interrupt Watchdog Timer Register */
+typedef struct _Ifx_ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_Bits
+{
+ unsigned int RIWT:8; /**< \brief [7:0] RI Watchdog Timer Count (rw) */
+ unsigned int reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_Bits;
+
+/** \brief Register 2 - Receive Poll Demand Register */
+typedef struct _Ifx_ETH_RECEIVE_POLL_DEMAND_Bits
+{
+ unsigned int RPD:32; /**< \brief [31:0] Receive Poll Demand (rw) */
+} Ifx_ETH_RECEIVE_POLL_DEMAND_Bits;
+
+/** \brief Register 10 - Remote Wake-Up Frame Filter Register */
+typedef struct _Ifx_ETH_REMOTE_WAKE_UP_FRAME_FILTER_Bits
+{
+ unsigned int WKUPFRMFTR:32; /**< \brief [31:0] WKUPFRMFTR (rw) */
+} Ifx_ETH_REMOTE_WAKE_UP_FRAME_FILTER_Bits;
+
+/** \brief Register 112 - Receive Frame Count for Good and Bad 1,024 to Maxsize
+ * Bytes Frames */
+typedef struct _Ifx_ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_Bits
+{
+ unsigned int RX1024_MAXOCTGB:32; /**< \brief [31:0] RX1024_MAXOCTGB (r) */
+} Ifx_ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_Bits;
+
+/** \brief Register 109 - Receive Frame Count for Good and Bad 128 to 255 Bytes
+ * Frames */
+typedef struct _Ifx_ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_Bits
+{
+ unsigned int RX128_255OCTGB:32; /**< \brief [31:0] RX128_255OCTGB (r) */
+} Ifx_ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_Bits;
+
+/** \brief Register 110 - Receive Frame Count for Good and Bad 256 to 511 Bytes
+ * Frames */
+typedef struct _Ifx_ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_Bits
+{
+ unsigned int RX256_511OCTGB:32; /**< \brief [31:0] RX256_511OCTGB (r) */
+} Ifx_ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_Bits;
+
+/** \brief Register 111 - Receive Frame Count for Good and Bad 512 to 1,023
+ * Bytes Frames */
+typedef struct _Ifx_ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_Bits
+{
+ unsigned int RX512_1023OCTGB:32; /**< \brief [31:0] RX512_1023OCTGB (r) */
+} Ifx_ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_Bits;
+
+/** \brief Register 107 - Receive Frame Count for Good and Bad 64 Byte Frames */
+typedef struct _Ifx_ETH_RX_64OCTETS_FRAMES_GOOD_BAD_Bits
+{
+ unsigned int RX64OCTGB:32; /**< \brief [31:0] RX64OCTGB (r) */
+} Ifx_ETH_RX_64OCTETS_FRAMES_GOOD_BAD_Bits;
+
+/** \brief Register 108 - Receive Frame Count for Good and Bad 65 to 127 Bytes
+ * Frames */
+typedef struct _Ifx_ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_Bits
+{
+ unsigned int RX65_127OCTGB:32; /**< \brief [31:0] RX65_127OCTGB (r) */
+} Ifx_ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_Bits;
+
+/** \brief Register 102 - Receive Frame Count for Alignment Error Frames */
+typedef struct _Ifx_ETH_RX_ALIGNMENT_ERROR_FRAMES_Bits
+{
+ unsigned int RXALGNERR:32; /**< \brief [31:0] RXALGNERR (r) */
+} Ifx_ETH_RX_ALIGNMENT_ERROR_FRAMES_Bits;
+
+/** \brief Register 99 - Receive Frame Count for Good Broadcast Frames */
+typedef struct _Ifx_ETH_RX_BROADCAST_FRAMES_GOOD_Bits
+{
+ unsigned int RXBCASTG:32; /**< \brief [31:0] RXBCASTG (r) */
+} Ifx_ETH_RX_BROADCAST_FRAMES_GOOD_Bits;
+
+/** \brief Register 121 - Receive Frame Count for Good Control Frames Frames */
+typedef struct _Ifx_ETH_RX_CONTROL_FRAMES_GOOD_Bits
+{
+ unsigned int RXCTRLG:32; /**< \brief [31:0] RXCTRLG (r) */
+} Ifx_ETH_RX_CONTROL_FRAMES_GOOD_Bits;
+
+/** \brief Register 101 - Receive Frame Count for CRC Error Frames */
+typedef struct _Ifx_ETH_RX_CRC_ERROR_FRAMES_Bits
+{
+ unsigned int RXCRCERR:32; /**< \brief [31:0] RXCRCERR (r) */
+} Ifx_ETH_RX_CRC_ERROR_FRAMES_Bits;
+
+/** \brief Register 117 - Receive Frame Count for FIFO Overflow Frames */
+typedef struct _Ifx_ETH_RX_FIFO_OVERFLOW_FRAMES_Bits
+{
+ unsigned int RXFIFOOVFL:32; /**< \brief [31:0] RXFIFOOVFL (r) */
+} Ifx_ETH_RX_FIFO_OVERFLOW_FRAMES_Bits;
+
+/** \brief Register 96 - Receive Frame Count for Good and Bad Frames */
+typedef struct _Ifx_ETH_RX_FRAMES_COUNT_GOOD_BAD_Bits
+{
+ unsigned int RXFRMGB:32; /**< \brief [31:0] RXFRMGB (r) */
+} Ifx_ETH_RX_FRAMES_COUNT_GOOD_BAD_Bits;
+
+/** \brief Register 104 - Receive Frame Count for Jabber Error Frames */
+typedef struct _Ifx_ETH_RX_JABBER_ERROR_FRAMES_Bits
+{
+ unsigned int RXJABERR:32; /**< \brief [31:0] RXJABERR (r) */
+} Ifx_ETH_RX_JABBER_ERROR_FRAMES_Bits;
+
+/** \brief Register 114 - Receive Frame Count for Length Error Frames */
+typedef struct _Ifx_ETH_RX_LENGTH_ERROR_FRAMES_Bits
+{
+ unsigned int RXLENERR:32; /**< \brief [31:0] RXLENERR (r) */
+} Ifx_ETH_RX_LENGTH_ERROR_FRAMES_Bits;
+
+/** \brief Register 100 - Receive Frame Count for Good Multicast Frames */
+typedef struct _Ifx_ETH_RX_MULTICAST_FRAMES_GOOD_Bits
+{
+ unsigned int RXMCASTG:32; /**< \brief [31:0] RXMCASTG (r) */
+} Ifx_ETH_RX_MULTICAST_FRAMES_GOOD_Bits;
+
+/** \brief Register 97 - Receive Octet Count for Good and Bad Frames */
+typedef struct _Ifx_ETH_RX_OCTET_COUNT_GOOD_BAD_Bits
+{
+ unsigned int RXOCTGB:32; /**< \brief [31:0] RXOCTGB (r) */
+} Ifx_ETH_RX_OCTET_COUNT_GOOD_BAD_Bits;
+
+/** \brief Register 98 - Receive Octet Count for Good Frames */
+typedef struct _Ifx_ETH_RX_OCTET_COUNT_GOOD_Bits
+{
+ unsigned int RXOCTG:32; /**< \brief [31:0] RXOCTG (r) */
+} Ifx_ETH_RX_OCTET_COUNT_GOOD_Bits;
+
+/** \brief Register 115 - Receive Frame Count for Out of Range Frames */
+typedef struct _Ifx_ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_Bits
+{
+ unsigned int RXOUTOFRNG:32; /**< \brief [31:0] RXOUTOFRNG (r) */
+} Ifx_ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_Bits;
+
+/** \brief Register 106 - Receive Frame Count for Oversize Frames */
+typedef struct _Ifx_ETH_RX_OVERSIZE_FRAMES_GOOD_Bits
+{
+ unsigned int RXOVERSZG:32; /**< \brief [31:0] RXOVERSZG (r) */
+} Ifx_ETH_RX_OVERSIZE_FRAMES_GOOD_Bits;
+
+/** \brief Register 116 - Receive Frame Count for PAUSE Frames */
+typedef struct _Ifx_ETH_RX_PAUSE_FRAMES_Bits
+{
+ unsigned int RXPAUSEFRM:32; /**< \brief [31:0] RXPAUSEFRM (r) */
+} Ifx_ETH_RX_PAUSE_FRAMES_Bits;
+
+/** \brief Register 120 - Receive Frame Count for Receive Error Frames */
+typedef struct _Ifx_ETH_RX_RECEIVE_ERROR_FRAMES_Bits
+{
+ unsigned int RXRCVERR:32; /**< \brief [31:0] RXRCVERR (r) */
+} Ifx_ETH_RX_RECEIVE_ERROR_FRAMES_Bits;
+
+/** \brief Register 103 - Receive Frame Count for Runt Error Frames */
+typedef struct _Ifx_ETH_RX_RUNT_ERROR_FRAMES_Bits
+{
+ unsigned int RXRUNTERR:32; /**< \brief [31:0] RXRUNTERR (r) */
+} Ifx_ETH_RX_RUNT_ERROR_FRAMES_Bits;
+
+/** \brief Register 105 - Receive Frame Count for Undersize Frames */
+typedef struct _Ifx_ETH_RX_UNDERSIZE_FRAMES_GOOD_Bits
+{
+ unsigned int RXUNDERSZG:32; /**< \brief [31:0] RXUNDERSZG (r) */
+} Ifx_ETH_RX_UNDERSIZE_FRAMES_GOOD_Bits;
+
+/** \brief Register 113 - Receive Frame Count for Good Unicast Frames */
+typedef struct _Ifx_ETH_RX_UNICAST_FRAMES_GOOD_Bits
+{
+ unsigned int RXUCASTG:32; /**< \brief [31:0] RXUCASTG (r) */
+} Ifx_ETH_RX_UNICAST_FRAMES_GOOD_Bits;
+
+/** \brief Register 118 - Receive Frame Count for Good and Bad VLAN Frames */
+typedef struct _Ifx_ETH_RX_VLAN_FRAMES_GOOD_BAD_Bits
+{
+ unsigned int RXVLANFRGB:32; /**< \brief [31:0] RXVLANFRGB (r) */
+} Ifx_ETH_RX_VLAN_FRAMES_GOOD_BAD_Bits;
+
+/** \brief Register 119 - Receive Frame Count for Watchdog Error Frames */
+typedef struct _Ifx_ETH_RX_WATCHDOG_ERROR_FRAMES_Bits
+{
+ unsigned int RXWDGERR:32; /**< \brief [31:0] RXWDGERR (r) */
+} Ifx_ETH_RX_WATCHDOG_ERROR_FRAMES_Bits;
+
+/** \brief Register 145 - Receive ICMP Error Frame Counter Register */
+typedef struct _Ifx_ETH_RXICMP_ERROR_FRAMES_Bits
+{
+ unsigned int RXICMPERRFRM:32; /**< \brief [31:0] RXICMPERRFRM (r) */
+} Ifx_ETH_RXICMP_ERROR_FRAMES_Bits;
+
+/** \brief Register 161 - Receive ICMP Error Octet Counter Register */
+typedef struct _Ifx_ETH_RXICMP_ERROR_OCTETS_Bits
+{
+ unsigned int RXICMPERROCT:32; /**< \brief [31:0] RXICMPERROCT (r) */
+} Ifx_ETH_RXICMP_ERROR_OCTETS_Bits;
+
+/** \brief Register 144 - Receive ICMP Good Frame Counter Register */
+typedef struct _Ifx_ETH_RXICMP_GOOD_FRAMES_Bits
+{
+ unsigned int RXICMPGDFRM:32; /**< \brief [31:0] RXICMPGDFRM (r) */
+} Ifx_ETH_RXICMP_GOOD_FRAMES_Bits;
+
+/** \brief Register 160 - Receive ICMP Good Octet Counter Register */
+typedef struct _Ifx_ETH_RXICMP_GOOD_OCTETS_Bits
+{
+ unsigned int RXICMPGDOCT:32; /**< \brief [31:0] RXICMPGDOCT (r) */
+} Ifx_ETH_RXICMP_GOOD_OCTETS_Bits;
+
+/** \brief Register 135 - Receive IPV4 Fragmented Frame Counter Register */
+typedef struct _Ifx_ETH_RXIPV4_FRAGMENTED_FRAMES_Bits
+{
+ unsigned int RXIPV4FRAGFRM:32; /**< \brief [31:0] RXIPV4FRAGFRM (r) */
+} Ifx_ETH_RXIPV4_FRAGMENTED_FRAMES_Bits;
+
+/** \brief Register 151 - Receive IPV4 Fragmented Octet Counter Register */
+typedef struct _Ifx_ETH_RXIPV4_FRAGMENTED_OCTETS_Bits
+{
+ unsigned int RXIPV4FRAGOCT:32; /**< \brief [31:0] This field indicates the number of bytes received in fragmented IPv4 datagrams. The value in the IPv4 headers Length field is used to update this counter. (r) */
+} Ifx_ETH_RXIPV4_FRAGMENTED_OCTETS_Bits;
+
+/** \brief Register 132 - Receive IPV4 Good Frame Counter Register */
+typedef struct _Ifx_ETH_RXIPV4_GOOD_FRAMES_Bits
+{
+ unsigned int RXIPV4GDFRM:32; /**< \brief [31:0] RXIPV4GDFRM (r) */
+} Ifx_ETH_RXIPV4_GOOD_FRAMES_Bits;
+
+/** \brief Register 148 - Receive IPV4 Good Octet Counter Register */
+typedef struct _Ifx_ETH_RXIPV4_GOOD_OCTETS_Bits
+{
+ unsigned int RXIPV4GDOCT:32; /**< \brief [31:0] This field indicates the number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data. The Ethernet header, FCS, pad, or IP pad (r) */
+} Ifx_ETH_RXIPV4_GOOD_OCTETS_Bits;
+
+/** \brief Register 133 - Receive IPV4 Header Error Frame Counter Register */
+typedef struct _Ifx_ETH_RXIPV4_HEADER_ERROR_FRAMES_Bits
+{
+ unsigned int RXIPV4HDRERRFRM:32; /**< \brief [31:0] RXIPV4HDRERRFRM (r) */
+} Ifx_ETH_RXIPV4_HEADER_ERROR_FRAMES_Bits;
+
+/** \brief Register 149 - Receive IPV4 Header Error Octet Counter Register */
+typedef struct _Ifx_ETH_RXIPV4_HEADER_ERROR_OCTETS_Bits
+{
+ unsigned int RXIPV4HDRERROCT:32; /**< \brief [31:0] This field indicates the number of bytes received in the IPv4 datagrams with header errors (checksum, length, or version mismatch). The value in the Length field of IPv4 header is used to update this counter. (r) */
+} Ifx_ETH_RXIPV4_HEADER_ERROR_OCTETS_Bits;
+
+/** \brief Register 134 - Receive IPV4 No Payload Frame Counter Register */
+typedef struct _Ifx_ETH_RXIPV4_NO_PAYLOAD_FRAMES_Bits
+{
+ unsigned int RXIPV4NOPAYFRM:32; /**< \brief [31:0] RXIPV4NOPAYFRM (r) */
+} Ifx_ETH_RXIPV4_NO_PAYLOAD_FRAMES_Bits;
+
+/** \brief Register 150 - Receive IPV4 No Payload Octet Counter Register */
+typedef struct _Ifx_ETH_RXIPV4_NO_PAYLOAD_OCTETS_Bits
+{
+ unsigned int RXIPV4NOPAYOCT:32; /**< \brief [31:0] This field indicates the number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv4 headers Length field is used to update this counter. (r) */
+} Ifx_ETH_RXIPV4_NO_PAYLOAD_OCTETS_Bits;
+
+/** \brief Register 152 - Receive IPV4 Fragmented Octet Counter Register */
+typedef struct _Ifx_ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_Bits
+{
+ unsigned int RXIPV4UDSBLOCT:32; /**< \brief [31:0] RXIPV4UDSBLOCT (r) */
+} Ifx_ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_Bits;
+
+/** \brief Register 136 - Receive IPV4 UDP Checksum Disabled Frame Counter
+ * Register */
+typedef struct _Ifx_ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_Bits
+{
+ unsigned int RXIPV4UDSBLFRM:32; /**< \brief [31:0] RXIPV4UDSBLFRM (r) */
+} Ifx_ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_Bits;
+
+/** \brief Register 137 - Receive IPV6 Good Frame Counter Register */
+typedef struct _Ifx_ETH_RXIPV6_GOOD_FRAMES_Bits
+{
+ unsigned int RXIPV6GDFRM:32; /**< \brief [31:0] RXIPV6GDFRM (r) */
+} Ifx_ETH_RXIPV6_GOOD_FRAMES_Bits;
+
+/** \brief Register 153 - Receive IPV6 Good Octet Counter Register */
+typedef struct _Ifx_ETH_RXIPV6_GOOD_OCTETS_Bits
+{
+ unsigned int RXIPV6GDOCT:32; /**< \brief [31:0] Thsi field indicates the number of bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6 data. (r) */
+} Ifx_ETH_RXIPV6_GOOD_OCTETS_Bits;
+
+/** \brief Register 138 - Receive IPV6 Header Error Frame Counter Register */
+typedef struct _Ifx_ETH_RXIPV6_HEADER_ERROR_FRAMES_Bits
+{
+ unsigned int RXIPV6HDRERRFRM:32; /**< \brief [31:0] RXIPV6HDRERRFRM (r) */
+} Ifx_ETH_RXIPV6_HEADER_ERROR_FRAMES_Bits;
+
+/** \brief Register 154 - Receive IPV6 Header Error Octet Counter Register */
+typedef struct _Ifx_ETH_RXIPV6_HEADER_ERROR_OCTETS_Bits
+{
+ unsigned int RXIPV6HDRERROCT:32; /**< \brief [31:0] This field indicates the number of bytes received in IPv6 datagrams with header errors (length or version mismatch). The value in the IPv6 headers Length field is used to update this counter. (r) */
+} Ifx_ETH_RXIPV6_HEADER_ERROR_OCTETS_Bits;
+
+/** \brief Register 139 - Receive IPV6 No Payload Frame Counter Register */
+typedef struct _Ifx_ETH_RXIPV6_NO_PAYLOAD_FRAMES_Bits
+{
+ unsigned int RXIPV6NOPAYFRM:32; /**< \brief [31:0] RXIPV6NOPAYFRM (r) */
+} Ifx_ETH_RXIPV6_NO_PAYLOAD_FRAMES_Bits;
+
+/** \brief Register 155 - Receive IPV6 No Payload Octet Counter Register */
+typedef struct _Ifx_ETH_RXIPV6_NO_PAYLOAD_OCTETS_Bits
+{
+ unsigned int RXIPV6NOPAYOCT:32; /**< \brief [31:0] This field indicates the number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv6 headers Length field is used to update this counter. (r) */
+} Ifx_ETH_RXIPV6_NO_PAYLOAD_OCTETS_Bits;
+
+/** \brief Register 143 - Receive TCP Error Frame Counter Register */
+typedef struct _Ifx_ETH_RXTCP_ERROR_FRAMES_Bits
+{
+ unsigned int RXTCPERRFRM:32; /**< \brief [31:0] RXTCPERRFRM (r) */
+} Ifx_ETH_RXTCP_ERROR_FRAMES_Bits;
+
+/** \brief Register 159 - Receive TCP Error Octet Counter Register */
+typedef struct _Ifx_ETH_RXTCP_ERROR_OCTETS_Bits
+{
+ unsigned int RXTCPERROCT:32; /**< \brief [31:0] RXTCPERROCT (r) */
+} Ifx_ETH_RXTCP_ERROR_OCTETS_Bits;
+
+/** \brief Register 142 - Receive TCP Good Frame Counter Register */
+typedef struct _Ifx_ETH_RXTCP_GOOD_FRAMES_Bits
+{
+ unsigned int RXTCPGDFRM:32; /**< \brief [31:0] RXTCPGDFRM (r) */
+} Ifx_ETH_RXTCP_GOOD_FRAMES_Bits;
+
+/** \brief Register 158 - Receive TCP Good Octet Counter Register */
+typedef struct _Ifx_ETH_RXTCP_GOOD_OCTETS_Bits
+{
+ unsigned int RXTCPGDOCT:32; /**< \brief [31:0] RXTCPGDOCT (r) */
+} Ifx_ETH_RXTCP_GOOD_OCTETS_Bits;
+
+/** \brief Register 141 - Receive UDP Error Frame Counter Register */
+typedef struct _Ifx_ETH_RXUDP_ERROR_FRAMES_Bits
+{
+ unsigned int RXUDPERRFRM:32; /**< \brief [31:0] RXUDPERRFRM (r) */
+} Ifx_ETH_RXUDP_ERROR_FRAMES_Bits;
+
+/** \brief Register 157 - Receive UDP Error Octet Counter Register */
+typedef struct _Ifx_ETH_RXUDP_ERROR_OCTETS_Bits
+{
+ unsigned int RXUDPERROCT:32; /**< \brief [31:0] RXUDPERROCT (r) */
+} Ifx_ETH_RXUDP_ERROR_OCTETS_Bits;
+
+/** \brief Register 140 - Receive UDP Good Frame Counter Register */
+typedef struct _Ifx_ETH_RXUDP_GOOD_FRAMES_Bits
+{
+ unsigned int RXUDPGDFRM:32; /**< \brief [31:0] RXUDPGDFRM (r) */
+} Ifx_ETH_RXUDP_GOOD_FRAMES_Bits;
+
+/** \brief Register 156 - Receive UDP Good Octet Counter Register */
+typedef struct _Ifx_ETH_RXUDP_GOOD_OCTETS_Bits
+{
+ unsigned int RXUDPGDOCT:32; /**< \brief [31:0] RXUDPGDOCT (r) */
+} Ifx_ETH_RXUDP_GOOD_OCTETS_Bits;
+
+/** \brief Register 5 - Status Register */
+typedef struct _Ifx_ETH_STATUS_Bits
+{
+ unsigned int TI:1; /**< \brief [0:0] Transmit Interrupt (rw) */
+ unsigned int TPS:1; /**< \brief [1:1] Transmit Process Stopped (rw) */
+ unsigned int TU:1; /**< \brief [2:2] Transmit Buffer Unavailable (rw) */
+ unsigned int TJT:1; /**< \brief [3:3] Transmit Jabber Timeout (rw) */
+ unsigned int OVF:1; /**< \brief [4:4] Receive Overflow (rw) */
+ unsigned int UNF:1; /**< \brief [5:5] Transmit Underflow (rw) */
+ unsigned int RI:1; /**< \brief [6:6] Receive Interrupt (rw) */
+ unsigned int RU:1; /**< \brief [7:7] Receive Buffer Unavailable (rw) */
+ unsigned int RPS:1; /**< \brief [8:8] Receive Process Stopped (rw) */
+ unsigned int RWT:1; /**< \brief [9:9] Receive Watchdog Timeout (rw) */
+ unsigned int ETI:1; /**< \brief [10:10] Early Transmit Interrupt (rw) */
+ unsigned int reserved_11:2; /**< \brief \internal Reserved */
+ unsigned int FBI:1; /**< \brief [13:13] Fatal Bus Error Interrupt (rw) */
+ unsigned int ERI:1; /**< \brief [14:14] Early Receive Interrupt (rw) */
+ unsigned int AIS:1; /**< \brief [15:15] Abnormal Interrupt Summary (rw) */
+ unsigned int NIS:1; /**< \brief [16:16] Normal Interrupt Summary (rw) */
+ unsigned int RS:3; /**< \brief [19:17] Received Process State (r) */
+ unsigned int TS:3; /**< \brief [22:20] Transmit Process State (r) */
+ unsigned int EB:3; /**< \brief [25:23] Error Bits (r) */
+ unsigned int GLI:1; /**< \brief [26:26] GMAC Line interface Interrupt (r) */
+ unsigned int GMI:1; /**< \brief [27:27] GMAC MMC Interrupt (r) */
+ unsigned int GPI:1; /**< \brief [28:28] GMAC PMT Interrupt (r) */
+ unsigned int TTI:1; /**< \brief [29:29] Timestamp Trigger Interrupt (r) */
+ unsigned int GLPII:1; /**< \brief [30:30] GMAC LPI Interrupt (for Channel 0) (r) */
+ unsigned int reserved_31:1; /**< \brief \internal Reserved */
+} Ifx_ETH_STATUS_Bits;
+
+/** \brief Register 449 - Sub-Second Increment Register */
+typedef struct _Ifx_ETH_SUB_SECOND_INCREMENT_Bits
+{
+ unsigned int SSINC:8; /**< \brief [7:0] Sub-second Increment Value (rw) */
+ unsigned int reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_ETH_SUB_SECOND_INCREMENT_Bits;
+
+/** \brief Register 457 - System Time - Higher Word Seconds Register */
+typedef struct _Ifx_ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_Bits
+{
+ unsigned int TSHWR:16; /**< \brief [15:0] Timestamp Higher Word Register (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_Bits;
+
+/** \brief Register 451 - System Time - Nanoseconds Register */
+typedef struct _Ifx_ETH_SYSTEM_TIME_NANOSECONDS_Bits
+{
+ unsigned int TSSS:31; /**< \brief [30:0] Timestamp Sub Seconds (r) */
+ unsigned int reserved_31:1; /**< \brief \internal Reserved */
+} Ifx_ETH_SYSTEM_TIME_NANOSECONDS_Bits;
+
+/** \brief Register 453 - System Time - Nanoseconds Update Register */
+typedef struct _Ifx_ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_Bits
+{
+ unsigned int TSSS:31; /**< \brief [30:0] Timestamp Sub Second (rw) */
+ unsigned int ADDSUB:1; /**< \brief [31:31] Add or subtract time (rw) */
+} Ifx_ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_Bits;
+
+/** \brief Register 450 - System Time - Seconds Register */
+typedef struct _Ifx_ETH_SYSTEM_TIME_SECONDS_Bits
+{
+ unsigned int TSS:32; /**< \brief [31:0] Timestamp Second (r) */
+} Ifx_ETH_SYSTEM_TIME_SECONDS_Bits;
+
+/** \brief Register 452 - System Time - Seconds Update Register */
+typedef struct _Ifx_ETH_SYSTEM_TIME_SECONDS_UPDATE_Bits
+{
+ unsigned int TSS:32; /**< \brief [31:0] Timestamp Second (rw) */
+} Ifx_ETH_SYSTEM_TIME_SECONDS_UPDATE_Bits;
+
+/** \brief Register 456 - Target Time Nanoseconds Register */
+typedef struct _Ifx_ETH_TARGET_TIME_NANOSECONDS_Bits
+{
+ unsigned int TTSLO:31; /**< \brief [30:0] Target Timestamp Low Register (rw) */
+ unsigned int TRGTBUSY:1; /**< \brief [31:31] Target Time Register Busy (r) */
+} Ifx_ETH_TARGET_TIME_NANOSECONDS_Bits;
+
+/** \brief Register 455 - Target Time Seconds Register */
+typedef struct _Ifx_ETH_TARGET_TIME_SECONDS_Bits
+{
+ unsigned int TSTR:32; /**< \brief [31:0] Target Time Seconds Register (rw) */
+} Ifx_ETH_TARGET_TIME_SECONDS_Bits;
+
+/** \brief Register 454 - Timestamp Addend Register */
+typedef struct _Ifx_ETH_TIMESTAMP_ADDEND_Bits
+{
+ unsigned int TSAR:32; /**< \brief [31:0] Timestamp Addend Register (rw) */
+} Ifx_ETH_TIMESTAMP_ADDEND_Bits;
+
+/** \brief Register 448 - Timestamp Control Register */
+typedef struct _Ifx_ETH_TIMESTAMP_CONTROL_Bits
+{
+ unsigned int TSENA:1; /**< \brief [0:0] Timestamp Enable (rw) */
+ unsigned int TSCFUPDT:1; /**< \brief [1:1] Timestamp Fine or Coarse Update (rw) */
+ unsigned int TSINIT:1; /**< \brief [2:2] Timestamp Initialize (rw) */
+ unsigned int TSUPDT:1; /**< \brief [3:3] Timestamp Update (rw) */
+ unsigned int TSTRIG:1; /**< \brief [4:4] Timestamp Interrupt Trigger Enable (rw) */
+ unsigned int TSADDREG:1; /**< \brief [5:5] Addend Reg Update (rw) */
+ unsigned int reserved_6:2; /**< \brief \internal Reserved */
+ unsigned int TSENALL:1; /**< \brief [8:8] Enable Timestamp for All Frames (rw) */
+ unsigned int TSCTRLSSR:1; /**< \brief [9:9] Timestamp Digital or Binary Rollover Control (rw) */
+ unsigned int TSVER2ENA:1; /**< \brief [10:10] Enable PTP packet Processing for Version 2 Format (rw) */
+ unsigned int TSIPENA:1; /**< \brief [11:11] Enable Processing of PTP over Ethernet Frames (rw) */
+ unsigned int TSIPV6ENA:1; /**< \brief [12:12] Enable Processing of PTP Frames Sent Over IPv6-UDP (rw) */
+ unsigned int TSIPV4ENA:1; /**< \brief [13:13] Enable Processing of PTP Frames Sent over IPv4-UDP (rw) */
+ unsigned int TSEVNTENA:1; /**< \brief [14:14] Enable Timestamp Snapshot for Event Messages (rw) */
+ unsigned int TSMSTRENA:1; /**< \brief [15:15] Enable Snapshot for Messages Relevant to Master (rw) */
+ unsigned int SNAPTYPSEL:2; /**< \brief [17:16] Select PTP packets for Taking Snapshots (rw) */
+ unsigned int TSENMACADDR:1; /**< \brief [18:18] Enable MAC address for PTP Frame Filtering (rw) */
+ unsigned int reserved_19:5; /**< \brief \internal Reserved */
+ unsigned int ATSFC:1; /**< \brief [24:24] Auxiliary Snapshot FIFO Clear (r) */
+ unsigned int ATSEN0:1; /**< \brief [25:25] Auxiliary Snapshot 0 Enable (r) */
+ unsigned int ATSEN1:1; /**< \brief [26:26] Auxiliary Snapshot 1 Enable (r) */
+ unsigned int ATSEN2:1; /**< \brief [27:27] Auxiliary Snapshot 2 Enable (r) */
+ unsigned int ATSEN3:1; /**< \brief [28:28] Auxiliary Snapshot 3 Enable (r) */
+ unsigned int reserved_29:3; /**< \brief \internal Reserved */
+} Ifx_ETH_TIMESTAMP_CONTROL_Bits;
+
+/** \brief Register 458 - Timestamp Status Register */
+typedef struct _Ifx_ETH_TIMESTAMP_STATUS_Bits
+{
+ unsigned int TSSOVF:1; /**< \brief [0:0] Timestamp Seconds Overflow (r) */
+ unsigned int TSTARGT:1; /**< \brief [1:1] Timestamp Target Time Reached (r) */
+ unsigned int AUXTSTRIG:1; /**< \brief [2:2] Auxiliary Timestamp Trigger Snapshot (r) */
+ unsigned int TSTRGTERR:1; /**< \brief [3:3] Timestamp Target Time Error (r) */
+ unsigned int TSTARGT1:1; /**< \brief [4:4] Timestamp Target Time Reached for Target Time PPS1 (r) */
+ unsigned int TSTRGTERR1:1; /**< \brief [5:5] Timestamp Target Time Error (r) */
+ unsigned int TSTARGT2:1; /**< \brief [6:6] Timestamp Target Time Reached for Target Time PPS2 (r) */
+ unsigned int TSTRGTERR2:1; /**< \brief [7:7] Timestamp Target Time Error (r) */
+ unsigned int TSTARGT3:1; /**< \brief [8:8] Timestamp Target Time Reached for Target Time PPS3 (r) */
+ unsigned int TSTRGTERR3:1; /**< \brief [9:9] Timestamp Target Time Error (r) */
+ unsigned int reserved_10:6; /**< \brief \internal Reserved */
+ unsigned int ATSSTN:4; /**< \brief [19:16] Auxiliary Timestamp Snapshot Trigger Identifier (r) */
+ unsigned int reserved_20:4; /**< \brief \internal Reserved */
+ unsigned int ATSSTM:1; /**< \brief [24:24] Auxiliary Timestamp Snapshot Trigger Missed (r) */
+ unsigned int ATSNS:5; /**< \brief [29:25] Number of Auxiliary Timestamp Snapshots (r) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_ETH_TIMESTAMP_STATUS_Bits;
+
+/** \brief Register 4 - Transmit Descriptor List Address Register */
+typedef struct _Ifx_ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_Bits
+{
+ unsigned int reserved_0:2; /**< \brief \internal Reserved */
+ unsigned int TDESLA:30; /**< \brief [31:2] Start of Transmit List (rw) */
+} Ifx_ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_Bits;
+
+/** \brief Register 1 - Transmit Poll Demand Register */
+typedef struct _Ifx_ETH_TRANSMIT_POLL_DEMAND_Bits
+{
+ unsigned int TPD:32; /**< \brief [31:0] Transmit Poll Demand (rw) */
+} Ifx_ETH_TRANSMIT_POLL_DEMAND_Bits;
+
+/** \brief Register 78 - Transmit Octet Count for Good and Bad 1024 to Maxsize
+ * Bytes Frames */
+typedef struct _Ifx_ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_Bits
+{
+ unsigned int TX1024_MAXOCTGB:32; /**< \brief [31:0] TX1024_MAXOCTGB (r) */
+} Ifx_ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_Bits;
+
+/** \brief Register 75 - Transmit Octet Count for Good and Bad 128 to 255 Bytes
+ * Frames */
+typedef struct _Ifx_ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_Bits
+{
+ unsigned int TX128_255OCTGB:32; /**< \brief [31:0] TX128_255OCTGB (r) */
+} Ifx_ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_Bits;
+
+/** \brief Register 76 - Transmit Octet Count for Good and Bad 256 to 511 Bytes
+ * Frames */
+typedef struct _Ifx_ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_Bits
+{
+ unsigned int TX256_511OCTGB:32; /**< \brief [31:0] TX256_511OCTGB (r) */
+} Ifx_ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_Bits;
+
+/** \brief Register 77 - Transmit Octet Count for Good and Bad 512 to 1023
+ * Bytes Frames */
+typedef struct _Ifx_ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_Bits
+{
+ unsigned int TX512_1023OCTGB:32; /**< \brief [31:0] TX512_1023OCTGB (r) */
+} Ifx_ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_Bits;
+
+/** \brief Register 73 - Transmit Octet Count for Good and Bad 64 Byte Frames */
+typedef struct _Ifx_ETH_TX_64OCTETS_FRAMES_GOOD_BAD_Bits
+{
+ unsigned int TX64OCTGB:32; /**< \brief [31:0] TX64OCTGB (r) */
+} Ifx_ETH_TX_64OCTETS_FRAMES_GOOD_BAD_Bits;
+
+/** \brief Register 74 - Transmit Octet Count for Good and Bad 65 to 127 Bytes
+ * Frames */
+typedef struct _Ifx_ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_Bits
+{
+ unsigned int TX65_127OCTGB:32; /**< \brief [31:0] TX65_127OCTGB (r) */
+} Ifx_ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_Bits;
+
+/** \brief Register 81 - Transmit Frame Count for Good and Bad Broadcast Frames */
+typedef struct _Ifx_ETH_TX_BROADCAST_FRAMES_GOOD_BAD_Bits
+{
+ unsigned int TXBCASTGB:32; /**< \brief [31:0] TXBCASTGB (r) */
+} Ifx_ETH_TX_BROADCAST_FRAMES_GOOD_BAD_Bits;
+
+/** \brief Register 71 - Transmit Frame Count for Good Broadcast Frames */
+typedef struct _Ifx_ETH_TX_BROADCAST_FRAMES_GOOD_Bits
+{
+ unsigned int TXBCASTG:32; /**< \brief [31:0] TXBCASTG (r) */
+} Ifx_ETH_TX_BROADCAST_FRAMES_GOOD_Bits;
+
+/** \brief Register 88 - Transmit Frame Count for Carrier Sense Error Frames */
+typedef struct _Ifx_ETH_TX_CARRIER_ERROR_FRAMES_Bits
+{
+ unsigned int TXCARR:32; /**< \brief [31:0] TXCARR (r) */
+} Ifx_ETH_TX_CARRIER_ERROR_FRAMES_Bits;
+
+/** \brief Register 85 - Transmit Frame Count for Deferred Frames */
+typedef struct _Ifx_ETH_TX_DEFERRED_FRAMES_Bits
+{
+ unsigned int TXDEFRD:32; /**< \brief [31:0] TXDEFRD (r) */
+} Ifx_ETH_TX_DEFERRED_FRAMES_Bits;
+
+/** \brief Register 87 - Transmit Frame Count for Excessive Collision Error
+ * Frames */
+typedef struct _Ifx_ETH_TX_EXCESSIVE_COLLISION_FRAMES_Bits
+{
+ unsigned int TXEXSCOL:32; /**< \brief [31:0] TXEXSCOL (r) */
+} Ifx_ETH_TX_EXCESSIVE_COLLISION_FRAMES_Bits;
+
+/** \brief Register 91 - Transmit Frame Count for Excessive Deferral Error
+ * Frames */
+typedef struct _Ifx_ETH_TX_EXCESSIVE_DEFERRAL_ERROR_Bits
+{
+ unsigned int TXEXSDEF:32; /**< \brief [31:0] TXEXSDEF (r) */
+} Ifx_ETH_TX_EXCESSIVE_DEFERRAL_ERROR_Bits;
+
+/** \brief Register 70 - Transmit Frame Count for Good and Bad Frames */
+typedef struct _Ifx_ETH_TX_FRAME_COUNT_GOOD_BAD_Bits
+{
+ unsigned int TXFRMGB:32; /**< \brief [31:0] TXFRMGB (r) */
+} Ifx_ETH_TX_FRAME_COUNT_GOOD_BAD_Bits;
+
+/** \brief Register 90 - Transmit Frame Count for Good Frames */
+typedef struct _Ifx_ETH_TX_FRAME_COUNT_GOOD_Bits
+{
+ unsigned int TXFRMG:32; /**< \brief [31:0] TXFRMG (r) */
+} Ifx_ETH_TX_FRAME_COUNT_GOOD_Bits;
+
+/** \brief Register 86 - Transmit Frame Count for Late Collision Error Frames */
+typedef struct _Ifx_ETH_TX_LATE_COLLISION_FRAMES_Bits
+{
+ unsigned int TXLATECOL:32; /**< \brief [31:0] TXLATECOL (r) */
+} Ifx_ETH_TX_LATE_COLLISION_FRAMES_Bits;
+
+/** \brief Register 80 - Transmit Frame Count for Good and Bad Multicast Frames */
+typedef struct _Ifx_ETH_TX_MULTICAST_FRAMES_GOOD_BAD_Bits
+{
+ unsigned int TXMCASTGB:32; /**< \brief [31:0] TXMCASTGB (r) */
+} Ifx_ETH_TX_MULTICAST_FRAMES_GOOD_BAD_Bits;
+
+/** \brief Register 72 - Transmit Frame Count for Good Multicast Frames */
+typedef struct _Ifx_ETH_TX_MULTICAST_FRAMES_GOOD_Bits
+{
+ unsigned int TXMCASTG:32; /**< \brief [31:0] TXMCASTG (r) */
+} Ifx_ETH_TX_MULTICAST_FRAMES_GOOD_Bits;
+
+/** \brief Register 84 - Transmit Frame Count for Frames Transmitted after
+ * Multiple Collision */
+typedef struct _Ifx_ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_Bits
+{
+ unsigned int TXMULTCOLG:32; /**< \brief [31:0] TXMULTCOLG (r) */
+} Ifx_ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_Bits;
+
+/** \brief Register 69 - Transmit Octet Count for Good and Bad Frames */
+typedef struct _Ifx_ETH_TX_OCTET_COUNT_GOOD_BAD_Bits
+{
+ unsigned int TXOCTGB:32; /**< \brief [31:0] TXOCTGB (r) */
+} Ifx_ETH_TX_OCTET_COUNT_GOOD_BAD_Bits;
+
+/** \brief Register 89 - Transmit Octet Count for Good Frames */
+typedef struct _Ifx_ETH_TX_OCTET_COUNT_GOOD_Bits
+{
+ unsigned int TXOCTG:32; /**< \brief [31:0] TXOCTG (r) */
+} Ifx_ETH_TX_OCTET_COUNT_GOOD_Bits;
+
+/** \brief Register 94 - Transmit Frame Count for Good Oversize Frames */
+typedef struct _Ifx_ETH_TX_OSIZE_FRAMES_GOOD_Bits
+{
+ unsigned int TXOSIZG:32; /**< \brief [31:0] TXOSIZG (r) */
+} Ifx_ETH_TX_OSIZE_FRAMES_GOOD_Bits;
+
+/** \brief Register 92 - Transmit Frame Count for Good PAUSE Frames */
+typedef struct _Ifx_ETH_TX_PAUSE_FRAMES_Bits
+{
+ unsigned int TXPAUSE:32; /**< \brief [31:0] TXPAUSE (r) */
+} Ifx_ETH_TX_PAUSE_FRAMES_Bits;
+
+/** \brief Register 83 - Transmit Frame Count for Frames Transmitted after
+ * Single Collision */
+typedef struct _Ifx_ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_Bits
+{
+ unsigned int TXSNGLCOLG:32; /**< \brief [31:0] TXSNGLCOLG (r) */
+} Ifx_ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_Bits;
+
+/** \brief Register 82 - Transmit Frame Count for Underflow Error Frames */
+typedef struct _Ifx_ETH_TX_UNDERFLOW_ERROR_FRAMES_Bits
+{
+ unsigned int TXUNDRFLW:32; /**< \brief [31:0] TXUNDRFLW (r) */
+} Ifx_ETH_TX_UNDERFLOW_ERROR_FRAMES_Bits;
+
+/** \brief Register 79 - Transmit Frame Count for Good and Bad Unicast Frames */
+typedef struct _Ifx_ETH_TX_UNICAST_FRAMES_GOOD_BAD_Bits
+{
+ unsigned int TXUCASTGB:32; /**< \brief [31:0] TXUCASTGB (r) */
+} Ifx_ETH_TX_UNICAST_FRAMES_GOOD_BAD_Bits;
+
+/** \brief Register 93 - Transmit Frame Count for Good VLAN Frames */
+typedef struct _Ifx_ETH_TX_VLAN_FRAMES_GOOD_Bits
+{
+ unsigned int TXVLANG:32; /**< \brief [31:0] TXVLANG (r) */
+} Ifx_ETH_TX_VLAN_FRAMES_GOOD_Bits;
+
+/** \brief Register 8 - Version Register */
+typedef struct _Ifx_ETH_VERSION_Bits
+{
+ unsigned int SNPSVER:8; /**< \brief [7:0] SNPSVER (r) */
+ unsigned int USERVER:8; /**< \brief [15:8] USERVER (r) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_ETH_VERSION_Bits;
+
+/** \brief Register 7 - VLAN Tag Register */
+typedef struct _Ifx_ETH_VLAN_TAG_Bits
+{
+ unsigned int VL:16; /**< \brief [15:0] VLAN Tag Identifier for Receive Frames (rw) */
+ unsigned int ETV:1; /**< \brief [16:16] Enable 12-Bit VLAN Tag Comparison (rw) */
+ unsigned int VTIM:1; /**< \brief [17:17] VLAN Tag Inverse Match Enable (rw) */
+ unsigned int ESVL:1; /**< \brief [18:18] Enable S-VLAN (rw) */
+ unsigned int VTHM:1; /**< \brief [19:19] VLAN Tag Hash Table Match Enable (r) */
+ unsigned int reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_ETH_VLAN_TAG_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Eth_union
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_ACCEN0_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_ACCEN0;
+
+/** \brief Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_ACCEN1_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_ACCEN1;
+
+/** \brief Register 11 - AHB or AXI Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_AHB_OR_AXI_STATUS_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_AHB_OR_AXI_STATUS;
+
+/** \brief Register 0 - Bus Mode Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_BUS_MODE_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_BUS_MODE;
+
+/** \brief Clock Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_CLC_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_CLC;
+
+/** \brief Register 21 - Current Host Receive Buffer Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS;
+
+/** \brief Register 19 - Current Host Receive Descriptor Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR;
+
+/** \brief Register 20 - Current Host Transmit Buffer Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS;
+
+/** \brief Register 18 - Current Host Transmit Descriptor Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR;
+
+/** \brief Register 9 - Debug Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_DEBUG_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_DEBUG;
+
+/** \brief Register 6 - Flow Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_FLOW_CONTROL_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_FLOW_CONTROL;
+
+/** \brief Register 4 - GMII Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_GMII_ADDRESS_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_GMII_ADDRESS;
+
+/** \brief Register 5 - GMII Data Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_GMII_DATA_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_GMII_DATA;
+
+/** \brief Input and Output Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_GPCTL_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_GPCTL;
+
+/** \brief Register 2 - Hash Table High Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_HASH_TABLE_HIGH_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_HASH_TABLE_HIGH;
+
+/** \brief Register 3 - Hash Table Low Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_HASH_TABLE_LOW_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_HASH_TABLE_LOW;
+
+/** \brief Register 22 - HW Feature Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_HW_FEATURE_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_HW_FEATURE;
+
+/** \brief Module Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_ID;
+
+/** \brief Register 7 - Interrupt Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_INTERRUPT_ENABLE_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_INTERRUPT_ENABLE;
+
+/** \brief Register 15 - Interrupt Mask Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_INTERRUPT_MASK_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_INTERRUPT_MASK;
+
+/** \brief Register 14 - Interrupt Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_INTERRUPT_STATUS_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_INTERRUPT_STATUS;
+
+/** \brief Kernel Reset Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_KRST0_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_KRST0;
+
+/** \brief Kernel Reset Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_KRST1_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_KRST1;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_KRSTCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_KRSTCLR;
+
+/** \brief MAC Address High Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_MAC_ADDRESS_HIGH_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_MAC_ADDRESS_HIGH;
+
+/** \brief MAC Address Low Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_MAC_ADDRESS_LOW_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_MAC_ADDRESS_LOW;
+
+/** \brief Register 0 - MAC Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_MAC_CONFIGURATION_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_MAC_CONFIGURATION;
+
+/** \brief Register 1 - MAC Frame Filter */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_MAC_FRAME_FILTER_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_MAC_FRAME_FILTER;
+
+/** \brief Register 8 - Missed Frame and Buffer Overflow Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER;
+
+/** \brief Register 64 - MMC Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_MMC_CONTROL_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_MMC_CONTROL;
+
+/** \brief Register 130 - MMC Receive Checksum Offload Interrupt Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT;
+
+/** \brief Register 128 - MMC Receive Checksum Offload Interrupt Mask Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK;
+
+/** \brief Register 65 - MMC Receive Interrupt Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_MMC_RECEIVE_INTERRUPT_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_MMC_RECEIVE_INTERRUPT;
+
+/** \brief - */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK;
+
+/** \brief Register 66 - MMC Transmit Interrupt Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_MMC_TRANSMIT_INTERRUPT_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_MMC_TRANSMIT_INTERRUPT;
+
+/** \brief Register 68 - MMC Transmit Interrupt Mask Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK;
+
+/** \brief Register 6 - Operation Mode Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_OPERATION_MODE_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_OPERATION_MODE;
+
+/** \brief Register 11 - PMT Control and Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_PMT_CONTROL_STATUS_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_PMT_CONTROL_STATUS;
+
+/** \brief Register 459 - PPS Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_PPS_CONTROL_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_PPS_CONTROL;
+
+/** \brief Register 3 - Receive Descriptor List Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS;
+
+/** \brief Register 9 - Receive Interrupt Watchdog Timer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER;
+
+/** \brief Register 2 - Receive Poll Demand Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RECEIVE_POLL_DEMAND_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RECEIVE_POLL_DEMAND;
+
+/** \brief Register 10 - Remote Wake-Up Frame Filter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_REMOTE_WAKE_UP_FRAME_FILTER_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_REMOTE_WAKE_UP_FRAME_FILTER;
+
+/** \brief Register 112 - Receive Frame Count for Good and Bad 1,024 to Maxsize
+ * Bytes Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD;
+
+/** \brief Register 109 - Receive Frame Count for Good and Bad 128 to 255 Bytes
+ * Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD;
+
+/** \brief Register 110 - Receive Frame Count for Good and Bad 256 to 511 Bytes
+ * Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD;
+
+/** \brief Register 111 - Receive Frame Count for Good and Bad 512 to 1,023
+ * Bytes Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD;
+
+/** \brief Register 107 - Receive Frame Count for Good and Bad 64 Byte Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RX_64OCTETS_FRAMES_GOOD_BAD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RX_64OCTETS_FRAMES_GOOD_BAD;
+
+/** \brief Register 108 - Receive Frame Count for Good and Bad 65 to 127 Bytes
+ * Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD;
+
+/** \brief Register 102 - Receive Frame Count for Alignment Error Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RX_ALIGNMENT_ERROR_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RX_ALIGNMENT_ERROR_FRAMES;
+
+/** \brief Register 99 - Receive Frame Count for Good Broadcast Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RX_BROADCAST_FRAMES_GOOD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RX_BROADCAST_FRAMES_GOOD;
+
+/** \brief Register 121 - Receive Frame Count for Good Control Frames Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RX_CONTROL_FRAMES_GOOD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RX_CONTROL_FRAMES_GOOD;
+
+/** \brief Register 101 - Receive Frame Count for CRC Error Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RX_CRC_ERROR_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RX_CRC_ERROR_FRAMES;
+
+/** \brief Register 117 - Receive Frame Count for FIFO Overflow Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RX_FIFO_OVERFLOW_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RX_FIFO_OVERFLOW_FRAMES;
+
+/** \brief Register 96 - Receive Frame Count for Good and Bad Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RX_FRAMES_COUNT_GOOD_BAD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RX_FRAMES_COUNT_GOOD_BAD;
+
+/** \brief Register 104 - Receive Frame Count for Jabber Error Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RX_JABBER_ERROR_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RX_JABBER_ERROR_FRAMES;
+
+/** \brief Register 114 - Receive Frame Count for Length Error Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RX_LENGTH_ERROR_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RX_LENGTH_ERROR_FRAMES;
+
+/** \brief Register 100 - Receive Frame Count for Good Multicast Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RX_MULTICAST_FRAMES_GOOD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RX_MULTICAST_FRAMES_GOOD;
+
+/** \brief Register 98 - Receive Octet Count for Good Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RX_OCTET_COUNT_GOOD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RX_OCTET_COUNT_GOOD;
+
+/** \brief Register 97 - Receive Octet Count for Good and Bad Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RX_OCTET_COUNT_GOOD_BAD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RX_OCTET_COUNT_GOOD_BAD;
+
+/** \brief Register 115 - Receive Frame Count for Out of Range Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RX_OUT_OF_RANGE_TYPE_FRAMES;
+
+/** \brief Register 106 - Receive Frame Count for Oversize Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RX_OVERSIZE_FRAMES_GOOD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RX_OVERSIZE_FRAMES_GOOD;
+
+/** \brief Register 116 - Receive Frame Count for PAUSE Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RX_PAUSE_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RX_PAUSE_FRAMES;
+
+/** \brief Register 120 - Receive Frame Count for Receive Error Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RX_RECEIVE_ERROR_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RX_RECEIVE_ERROR_FRAMES;
+
+/** \brief Register 103 - Receive Frame Count for Runt Error Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RX_RUNT_ERROR_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RX_RUNT_ERROR_FRAMES;
+
+/** \brief Register 105 - Receive Frame Count for Undersize Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RX_UNDERSIZE_FRAMES_GOOD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RX_UNDERSIZE_FRAMES_GOOD;
+
+/** \brief Register 113 - Receive Frame Count for Good Unicast Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RX_UNICAST_FRAMES_GOOD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RX_UNICAST_FRAMES_GOOD;
+
+/** \brief Register 118 - Receive Frame Count for Good and Bad VLAN Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RX_VLAN_FRAMES_GOOD_BAD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RX_VLAN_FRAMES_GOOD_BAD;
+
+/** \brief Register 119 - Receive Frame Count for Watchdog Error Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RX_WATCHDOG_ERROR_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RX_WATCHDOG_ERROR_FRAMES;
+
+/** \brief Register 145 - Receive ICMP Error Frame Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RXICMP_ERROR_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RXICMP_ERROR_FRAMES;
+
+/** \brief Register 161 - Receive ICMP Error Octet Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RXICMP_ERROR_OCTETS_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RXICMP_ERROR_OCTETS;
+
+/** \brief Register 144 - Receive ICMP Good Frame Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RXICMP_GOOD_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RXICMP_GOOD_FRAMES;
+
+/** \brief Register 160 - Receive ICMP Good Octet Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RXICMP_GOOD_OCTETS_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RXICMP_GOOD_OCTETS;
+
+/** \brief Register 135 - Receive IPV4 Fragmented Frame Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RXIPV4_FRAGMENTED_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RXIPV4_FRAGMENTED_FRAMES;
+
+/** \brief Register 151 - Receive IPV4 Fragmented Octet Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RXIPV4_FRAGMENTED_OCTETS_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RXIPV4_FRAGMENTED_OCTETS;
+
+/** \brief Register 132 - Receive IPV4 Good Frame Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RXIPV4_GOOD_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RXIPV4_GOOD_FRAMES;
+
+/** \brief Register 148 - Receive IPV4 Good Octet Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RXIPV4_GOOD_OCTETS_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RXIPV4_GOOD_OCTETS;
+
+/** \brief Register 133 - Receive IPV4 Header Error Frame Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RXIPV4_HEADER_ERROR_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RXIPV4_HEADER_ERROR_FRAMES;
+
+/** \brief Register 149 - Receive IPV4 Header Error Octet Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RXIPV4_HEADER_ERROR_OCTETS_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RXIPV4_HEADER_ERROR_OCTETS;
+
+/** \brief Register 134 - Receive IPV4 No Payload Frame Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RXIPV4_NO_PAYLOAD_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RXIPV4_NO_PAYLOAD_FRAMES;
+
+/** \brief Register 150 - Receive IPV4 No Payload Octet Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RXIPV4_NO_PAYLOAD_OCTETS_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RXIPV4_NO_PAYLOAD_OCTETS;
+
+/** \brief Register 152 - Receive IPV4 Fragmented Octet Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS;
+
+/** \brief Register 136 - Receive IPV4 UDP Checksum Disabled Frame Counter
+ * Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES;
+
+/** \brief Register 137 - Receive IPV6 Good Frame Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RXIPV6_GOOD_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RXIPV6_GOOD_FRAMES;
+
+/** \brief Register 153 - Receive IPV6 Good Octet Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RXIPV6_GOOD_OCTETS_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RXIPV6_GOOD_OCTETS;
+
+/** \brief Register 138 - Receive IPV6 Header Error Frame Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RXIPV6_HEADER_ERROR_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RXIPV6_HEADER_ERROR_FRAMES;
+
+/** \brief Register 154 - Receive IPV6 Header Error Octet Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RXIPV6_HEADER_ERROR_OCTETS_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RXIPV6_HEADER_ERROR_OCTETS;
+
+/** \brief Register 139 - Receive IPV6 No Payload Frame Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RXIPV6_NO_PAYLOAD_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RXIPV6_NO_PAYLOAD_FRAMES;
+
+/** \brief Register 155 - Receive IPV6 No Payload Octet Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RXIPV6_NO_PAYLOAD_OCTETS_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RXIPV6_NO_PAYLOAD_OCTETS;
+
+/** \brief Register 143 - Receive TCP Error Frame Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RXTCP_ERROR_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RXTCP_ERROR_FRAMES;
+
+/** \brief Register 159 - Receive TCP Error Octet Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RXTCP_ERROR_OCTETS_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RXTCP_ERROR_OCTETS;
+
+/** \brief Register 142 - Receive TCP Good Frame Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RXTCP_GOOD_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RXTCP_GOOD_FRAMES;
+
+/** \brief Register 158 - Receive TCP Good Octet Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RXTCP_GOOD_OCTETS_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RXTCP_GOOD_OCTETS;
+
+/** \brief Register 141 - Receive UDP Error Frame Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RXUDP_ERROR_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RXUDP_ERROR_FRAMES;
+
+/** \brief Register 157 - Receive UDP Error Octet Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RXUDP_ERROR_OCTETS_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RXUDP_ERROR_OCTETS;
+
+/** \brief Register 140 - Receive UDP Good Frame Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RXUDP_GOOD_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RXUDP_GOOD_FRAMES;
+
+/** \brief Register 156 - Receive UDP Good Octet Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_RXUDP_GOOD_OCTETS_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_RXUDP_GOOD_OCTETS;
+
+/** \brief Register 5 - Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_STATUS_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_STATUS;
+
+/** \brief Register 449 - Sub-Second Increment Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_SUB_SECOND_INCREMENT_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_SUB_SECOND_INCREMENT;
+
+/** \brief Register 457 - System Time - Higher Word Seconds Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS;
+
+/** \brief Register 451 - System Time - Nanoseconds Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_SYSTEM_TIME_NANOSECONDS_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_SYSTEM_TIME_NANOSECONDS;
+
+/** \brief Register 453 - System Time - Nanoseconds Update Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_SYSTEM_TIME_NANOSECONDS_UPDATE;
+
+/** \brief Register 450 - System Time - Seconds Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_SYSTEM_TIME_SECONDS_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_SYSTEM_TIME_SECONDS;
+
+/** \brief Register 452 - System Time - Seconds Update Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_SYSTEM_TIME_SECONDS_UPDATE_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_SYSTEM_TIME_SECONDS_UPDATE;
+
+/** \brief Register 456 - Target Time Nanoseconds Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TARGET_TIME_NANOSECONDS_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TARGET_TIME_NANOSECONDS;
+
+/** \brief Register 455 - Target Time Seconds Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TARGET_TIME_SECONDS_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TARGET_TIME_SECONDS;
+
+/** \brief Register 454 - Timestamp Addend Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TIMESTAMP_ADDEND_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TIMESTAMP_ADDEND;
+
+/** \brief Register 448 - Timestamp Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TIMESTAMP_CONTROL_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TIMESTAMP_CONTROL;
+
+/** \brief Register 458 - Timestamp Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TIMESTAMP_STATUS_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TIMESTAMP_STATUS;
+
+/** \brief Register 4 - Transmit Descriptor List Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS;
+
+/** \brief Register 1 - Transmit Poll Demand Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TRANSMIT_POLL_DEMAND_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TRANSMIT_POLL_DEMAND;
+
+/** \brief Register 78 - Transmit Octet Count for Good and Bad 1024 to Maxsize
+ * Bytes Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD;
+
+/** \brief Register 75 - Transmit Octet Count for Good and Bad 128 to 255 Bytes
+ * Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD;
+
+/** \brief Register 76 - Transmit Octet Count for Good and Bad 256 to 511 Bytes
+ * Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD;
+
+/** \brief Register 77 - Transmit Octet Count for Good and Bad 512 to 1023
+ * Bytes Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD;
+
+/** \brief Register 73 - Transmit Octet Count for Good and Bad 64 Byte Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TX_64OCTETS_FRAMES_GOOD_BAD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TX_64OCTETS_FRAMES_GOOD_BAD;
+
+/** \brief Register 74 - Transmit Octet Count for Good and Bad 65 to 127 Bytes
+ * Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD;
+
+/** \brief Register 71 - Transmit Frame Count for Good Broadcast Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TX_BROADCAST_FRAMES_GOOD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TX_BROADCAST_FRAMES_GOOD;
+
+/** \brief Register 81 - Transmit Frame Count for Good and Bad Broadcast Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TX_BROADCAST_FRAMES_GOOD_BAD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TX_BROADCAST_FRAMES_GOOD_BAD;
+
+/** \brief Register 88 - Transmit Frame Count for Carrier Sense Error Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TX_CARRIER_ERROR_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TX_CARRIER_ERROR_FRAMES;
+
+/** \brief Register 85 - Transmit Frame Count for Deferred Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TX_DEFERRED_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TX_DEFERRED_FRAMES;
+
+/** \brief Register 87 - Transmit Frame Count for Excessive Collision Error
+ * Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TX_EXCESSIVE_COLLISION_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TX_EXCESSIVE_COLLISION_FRAMES;
+
+/** \brief Register 91 - Transmit Frame Count for Excessive Deferral Error
+ * Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TX_EXCESSIVE_DEFERRAL_ERROR_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TX_EXCESSIVE_DEFERRAL_ERROR;
+
+/** \brief Register 90 - Transmit Frame Count for Good Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TX_FRAME_COUNT_GOOD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TX_FRAME_COUNT_GOOD;
+
+/** \brief Register 70 - Transmit Frame Count for Good and Bad Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TX_FRAME_COUNT_GOOD_BAD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TX_FRAME_COUNT_GOOD_BAD;
+
+/** \brief Register 86 - Transmit Frame Count for Late Collision Error Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TX_LATE_COLLISION_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TX_LATE_COLLISION_FRAMES;
+
+/** \brief Register 72 - Transmit Frame Count for Good Multicast Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TX_MULTICAST_FRAMES_GOOD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TX_MULTICAST_FRAMES_GOOD;
+
+/** \brief Register 80 - Transmit Frame Count for Good and Bad Multicast Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TX_MULTICAST_FRAMES_GOOD_BAD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TX_MULTICAST_FRAMES_GOOD_BAD;
+
+/** \brief Register 84 - Transmit Frame Count for Frames Transmitted after
+ * Multiple Collision */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES;
+
+/** \brief Register 89 - Transmit Octet Count for Good Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TX_OCTET_COUNT_GOOD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TX_OCTET_COUNT_GOOD;
+
+/** \brief Register 69 - Transmit Octet Count for Good and Bad Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TX_OCTET_COUNT_GOOD_BAD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TX_OCTET_COUNT_GOOD_BAD;
+
+/** \brief Register 94 - Transmit Frame Count for Good Oversize Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TX_OSIZE_FRAMES_GOOD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TX_OSIZE_FRAMES_GOOD;
+
+/** \brief Register 92 - Transmit Frame Count for Good PAUSE Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TX_PAUSE_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TX_PAUSE_FRAMES;
+
+/** \brief Register 83 - Transmit Frame Count for Frames Transmitted after
+ * Single Collision */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TX_SINGLE_COLLISION_GOOD_FRAMES;
+
+/** \brief Register 82 - Transmit Frame Count for Underflow Error Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TX_UNDERFLOW_ERROR_FRAMES_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TX_UNDERFLOW_ERROR_FRAMES;
+
+/** \brief Register 79 - Transmit Frame Count for Good and Bad Unicast Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TX_UNICAST_FRAMES_GOOD_BAD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TX_UNICAST_FRAMES_GOOD_BAD;
+
+/** \brief Register 93 - Transmit Frame Count for Good VLAN Frames */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_TX_VLAN_FRAMES_GOOD_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_TX_VLAN_FRAMES_GOOD;
+
+/** \brief Register 8 - Version Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_VERSION_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_VERSION;
+
+/** \brief Register 7 - VLAN Tag Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_ETH_VLAN_TAG_Bits B; /**< \brief Bitfield access */
+} Ifx_ETH_VLAN_TAG;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Eth_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L1
+ * \{ */
+
+/** \brief MAC Address */
+typedef volatile struct _Ifx_ETH_MAC_ADDRESS
+{
+ Ifx_ETH_MAC_ADDRESS_HIGH HIGH; /**< \brief 0, MAC Address High Register */
+ Ifx_ETH_MAC_ADDRESS_LOW LOW; /**< \brief 4, MAC Address Low Register */
+} Ifx_ETH_MAC_ADDRESS;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Eth_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief ETH object */
+typedef volatile struct _Ifx_ETH
+{
+ Ifx_ETH_CLC CLC; /**< \brief 0, Clock Control Register */
+ Ifx_ETH_ID ID; /**< \brief 4, Module Identification Register */
+ Ifx_ETH_GPCTL GPCTL; /**< \brief 8, Input and Output Control Register */
+ Ifx_ETH_ACCEN0 ACCEN0; /**< \brief C, Access Enable Register 0 */
+ Ifx_ETH_ACCEN1 ACCEN1; /**< \brief 10, Access Enable Register 1 */
+ Ifx_ETH_KRST0 KRST0; /**< \brief 14, Kernel Reset Register 0 */
+ Ifx_ETH_KRST1 KRST1; /**< \brief 18, Kernel Reset Register 1 */
+ Ifx_ETH_KRSTCLR KRSTCLR; /**< \brief 1C, Kernel Reset Status Clear Register */
+ unsigned char reserved_20[4064]; /**< \brief 20, \internal Reserved */
+ Ifx_ETH_MAC_CONFIGURATION MAC_CONFIGURATION; /**< \brief 1000, Register 0 - MAC Configuration Register */
+ Ifx_ETH_MAC_FRAME_FILTER MAC_FRAME_FILTER; /**< \brief 1004, Register 1 - MAC Frame Filter */
+ Ifx_ETH_HASH_TABLE_HIGH HASH_TABLE_HIGH; /**< \brief 1008, Register 2 - Hash Table High Register */
+ Ifx_ETH_HASH_TABLE_LOW HASH_TABLE_LOW; /**< \brief 100C, Register 3 - Hash Table Low Register */
+ Ifx_ETH_GMII_ADDRESS GMII_ADDRESS; /**< \brief 1010, Register 4 - GMII Address Register */
+ Ifx_ETH_GMII_DATA GMII_DATA; /**< \brief 1014, Register 5 - GMII Data Register */
+ Ifx_ETH_FLOW_CONTROL FLOW_CONTROL; /**< \brief 1018, Register 6 - Flow Control Register */
+ Ifx_ETH_VLAN_TAG VLAN_TAG; /**< \brief 101C, Register 7 - VLAN Tag Register */
+ Ifx_ETH_VERSION VERSION; /**< \brief 1020, Register 8 - Version Register */
+ Ifx_ETH_DEBUG DEBUG; /**< \brief 1024, Register 9 - Debug Register */
+ Ifx_ETH_REMOTE_WAKE_UP_FRAME_FILTER REMOTE_WAKE_UP_FRAME_FILTER; /**< \brief 1028, Register 10 - Remote Wake-Up Frame Filter Register */
+ Ifx_ETH_PMT_CONTROL_STATUS PMT_CONTROL_STATUS; /**< \brief 102C, Register 11 - PMT Control and Status Register */
+ unsigned char reserved_1030[8]; /**< \brief 1030, \internal Reserved */
+ Ifx_ETH_INTERRUPT_STATUS INTERRUPT_STATUS; /**< \brief 1038, Register 14 - Interrupt Register */
+ Ifx_ETH_INTERRUPT_MASK INTERRUPT_MASK; /**< \brief 103C, Register 15 - Interrupt Mask Register */
+ Ifx_ETH_MAC_ADDRESS MAC_ADDRESS_G0[16]; /**< \brief 1040, MAC Address */
+ unsigned char reserved_10C0[64]; /**< \brief 10C0, \internal Reserved */
+ Ifx_ETH_MMC_CONTROL MMC_CONTROL; /**< \brief 1100, Register 64 - MMC Control Register */
+ Ifx_ETH_MMC_RECEIVE_INTERRUPT MMC_RECEIVE_INTERRUPT; /**< \brief 1104, Register 65 - MMC Receive Interrupt Register */
+ Ifx_ETH_MMC_TRANSMIT_INTERRUPT MMC_TRANSMIT_INTERRUPT; /**< \brief 1108, Register 66 - MMC Transmit Interrupt Register */
+ Ifx_ETH_MMC_RECEIVE_INTERRUPT_MASK MMC_RECEIVE_INTERRUPT_MASK; /**< \brief 110C, - */
+ Ifx_ETH_MMC_TRANSMIT_INTERRUPT_MASK MMC_TRANSMIT_INTERRUPT_MASK; /**< \brief 1110, Register 68 - MMC Transmit Interrupt Mask Register */
+ Ifx_ETH_TX_OCTET_COUNT_GOOD_BAD TX_OCTET_COUNT_GOOD_BAD; /**< \brief 1114, Register 69 - Transmit Octet Count for Good and Bad Frames */
+ Ifx_ETH_TX_FRAME_COUNT_GOOD_BAD TX_FRAME_COUNT_GOOD_BAD; /**< \brief 1118, Register 70 - Transmit Frame Count for Good and Bad Frames */
+ Ifx_ETH_TX_BROADCAST_FRAMES_GOOD TX_BROADCAST_FRAMES_GOOD; /**< \brief 111C, Register 71 - Transmit Frame Count for Good Broadcast Frames */
+ Ifx_ETH_TX_MULTICAST_FRAMES_GOOD TX_MULTICAST_FRAMES_GOOD; /**< \brief 1120, Register 72 - Transmit Frame Count for Good Multicast Frames */
+ Ifx_ETH_TX_64OCTETS_FRAMES_GOOD_BAD TX_64OCTETS_FRAMES_GOOD_BAD; /**< \brief 1124, Register 73 - Transmit Octet Count for Good and Bad 64 Byte Frames */
+ Ifx_ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD TX_65TO127OCTETS_FRAMES_GOOD_BAD; /**< \brief 1128, Register 74 - Transmit Octet Count for Good and Bad 65 to 127 Bytes Frames */
+ Ifx_ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD TX_128TO255OCTETS_FRAMES_GOOD_BAD; /**< \brief 112C, Register 75 - Transmit Octet Count for Good and Bad 128 to 255 Bytes Frames */
+ Ifx_ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD TX_256TO511OCTETS_FRAMES_GOOD_BAD; /**< \brief 1130, Register 76 - Transmit Octet Count for Good and Bad 256 to 511 Bytes Frames */
+ Ifx_ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD TX_512TO1023OCTETS_FRAMES_GOOD_BAD; /**< \brief 1134, Register 77 - Transmit Octet Count for Good and Bad 512 to 1023 Bytes Frames */
+ Ifx_ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD; /**< \brief 1138, Register 78 - Transmit Octet Count for Good and Bad 1024 to Maxsize Bytes Frames */
+ Ifx_ETH_TX_UNICAST_FRAMES_GOOD_BAD TX_UNICAST_FRAMES_GOOD_BAD; /**< \brief 113C, Register 79 - Transmit Frame Count for Good and Bad Unicast Frames */
+ Ifx_ETH_TX_MULTICAST_FRAMES_GOOD_BAD TX_MULTICAST_FRAMES_GOOD_BAD; /**< \brief 1140, Register 80 - Transmit Frame Count for Good and Bad Multicast Frames */
+ Ifx_ETH_TX_BROADCAST_FRAMES_GOOD_BAD TX_BROADCAST_FRAMES_GOOD_BAD; /**< \brief 1144, Register 81 - Transmit Frame Count for Good and Bad Broadcast Frames */
+ Ifx_ETH_TX_UNDERFLOW_ERROR_FRAMES TX_UNDERFLOW_ERROR_FRAMES; /**< \brief 1148, Register 82 - Transmit Frame Count for Underflow Error Frames */
+ Ifx_ETH_TX_SINGLE_COLLISION_GOOD_FRAMES TX_SINGLE_COLLISION_GOOD_FRAMES; /**< \brief 114C, Register 83 - Transmit Frame Count for Frames Transmitted after Single Collision */
+ Ifx_ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES TX_MULTIPLE_COLLISION_GOOD_FRAMES; /**< \brief 1150, Register 84 - Transmit Frame Count for Frames Transmitted after Multiple Collision */
+ Ifx_ETH_TX_DEFERRED_FRAMES TX_DEFERRED_FRAMES; /**< \brief 1154, Register 85 - Transmit Frame Count for Deferred Frames */
+ Ifx_ETH_TX_LATE_COLLISION_FRAMES TX_LATE_COLLISION_FRAMES; /**< \brief 1158, Register 86 - Transmit Frame Count for Late Collision Error Frames */
+ Ifx_ETH_TX_EXCESSIVE_COLLISION_FRAMES TX_EXCESSIVE_COLLISION_FRAMES; /**< \brief 115C, Register 87 - Transmit Frame Count for Excessive Collision Error Frames */
+ Ifx_ETH_TX_CARRIER_ERROR_FRAMES TX_CARRIER_ERROR_FRAMES; /**< \brief 1160, Register 88 - Transmit Frame Count for Carrier Sense Error Frames */
+ Ifx_ETH_TX_OCTET_COUNT_GOOD TX_OCTET_COUNT_GOOD; /**< \brief 1164, Register 89 - Transmit Octet Count for Good Frames */
+ Ifx_ETH_TX_FRAME_COUNT_GOOD TX_FRAME_COUNT_GOOD; /**< \brief 1168, Register 90 - Transmit Frame Count for Good Frames */
+ Ifx_ETH_TX_EXCESSIVE_DEFERRAL_ERROR TX_EXCESSIVE_DEFERRAL_ERROR; /**< \brief 116C, Register 91 - Transmit Frame Count for Excessive Deferral Error Frames */
+ Ifx_ETH_TX_PAUSE_FRAMES TX_PAUSE_FRAMES; /**< \brief 1170, Register 92 - Transmit Frame Count for Good PAUSE Frames */
+ Ifx_ETH_TX_VLAN_FRAMES_GOOD TX_VLAN_FRAMES_GOOD; /**< \brief 1174, Register 93 - Transmit Frame Count for Good VLAN Frames */
+ Ifx_ETH_TX_OSIZE_FRAMES_GOOD TX_OSIZE_FRAMES_GOOD; /**< \brief 1178, Register 94 - Transmit Frame Count for Good Oversize Frames */
+ unsigned char reserved_117C[4]; /**< \brief 117C, \internal Reserved */
+ Ifx_ETH_RX_FRAMES_COUNT_GOOD_BAD RX_FRAMES_COUNT_GOOD_BAD; /**< \brief 1180, Register 96 - Receive Frame Count for Good and Bad Frames */
+ Ifx_ETH_RX_OCTET_COUNT_GOOD_BAD RX_OCTET_COUNT_GOOD_BAD; /**< \brief 1184, Register 97 - Receive Octet Count for Good and Bad Frames */
+ Ifx_ETH_RX_OCTET_COUNT_GOOD RX_OCTET_COUNT_GOOD; /**< \brief 1188, Register 98 - Receive Octet Count for Good Frames */
+ Ifx_ETH_RX_BROADCAST_FRAMES_GOOD RX_BROADCAST_FRAMES_GOOD; /**< \brief 118C, Register 99 - Receive Frame Count for Good Broadcast Frames */
+ Ifx_ETH_RX_MULTICAST_FRAMES_GOOD RX_MULTICAST_FRAMES_GOOD; /**< \brief 1190, Register 100 - Receive Frame Count for Good Multicast Frames */
+ Ifx_ETH_RX_CRC_ERROR_FRAMES RX_CRC_ERROR_FRAMES; /**< \brief 1194, Register 101 - Receive Frame Count for CRC Error Frames */
+ Ifx_ETH_RX_ALIGNMENT_ERROR_FRAMES RX_ALIGNMENT_ERROR_FRAMES; /**< \brief 1198, Register 102 - Receive Frame Count for Alignment Error Frames */
+ Ifx_ETH_RX_RUNT_ERROR_FRAMES RX_RUNT_ERROR_FRAMES; /**< \brief 119C, Register 103 - Receive Frame Count for Runt Error Frames */
+ Ifx_ETH_RX_JABBER_ERROR_FRAMES RX_JABBER_ERROR_FRAMES; /**< \brief 11A0, Register 104 - Receive Frame Count for Jabber Error Frames */
+ Ifx_ETH_RX_UNDERSIZE_FRAMES_GOOD RX_UNDERSIZE_FRAMES_GOOD; /**< \brief 11A4, Register 105 - Receive Frame Count for Undersize Frames */
+ Ifx_ETH_RX_OVERSIZE_FRAMES_GOOD RX_OVERSIZE_FRAMES_GOOD; /**< \brief 11A8, Register 106 - Receive Frame Count for Oversize Frames */
+ Ifx_ETH_RX_64OCTETS_FRAMES_GOOD_BAD RX_64OCTETS_FRAMES_GOOD_BAD; /**< \brief 11AC, Register 107 - Receive Frame Count for Good and Bad 64 Byte Frames */
+ Ifx_ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD RX_65TO127OCTETS_FRAMES_GOOD_BAD; /**< \brief 11B0, Register 108 - Receive Frame Count for Good and Bad 65 to 127 Bytes Frames */
+ Ifx_ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD RX_128TO255OCTETS_FRAMES_GOOD_BAD; /**< \brief 11B4, Register 109 - Receive Frame Count for Good and Bad 128 to 255 Bytes Frames */
+ Ifx_ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD RX_256TO511OCTETS_FRAMES_GOOD_BAD; /**< \brief 11B8, Register 110 - Receive Frame Count for Good and Bad 256 to 511 Bytes Frames */
+ Ifx_ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD RX_512TO1023OCTETS_FRAMES_GOOD_BAD; /**< \brief 11BC, Register 111 - Receive Frame Count for Good and Bad 512 to 1,023 Bytes Frames */
+ Ifx_ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD; /**< \brief 11C0, Register 112 - Receive Frame Count for Good and Bad 1,024 to Maxsize Bytes Frames */
+ Ifx_ETH_RX_UNICAST_FRAMES_GOOD RX_UNICAST_FRAMES_GOOD; /**< \brief 11C4, Register 113 - Receive Frame Count for Good Unicast Frames */
+ Ifx_ETH_RX_LENGTH_ERROR_FRAMES RX_LENGTH_ERROR_FRAMES; /**< \brief 11C8, Register 114 - Receive Frame Count for Length Error Frames */
+ Ifx_ETH_RX_OUT_OF_RANGE_TYPE_FRAMES RX_OUT_OF_RANGE_TYPE_FRAMES; /**< \brief 11CC, Register 115 - Receive Frame Count for Out of Range Frames */
+ Ifx_ETH_RX_PAUSE_FRAMES RX_PAUSE_FRAMES; /**< \brief 11D0, Register 116 - Receive Frame Count for PAUSE Frames */
+ Ifx_ETH_RX_FIFO_OVERFLOW_FRAMES RX_FIFO_OVERFLOW_FRAMES; /**< \brief 11D4, Register 117 - Receive Frame Count for FIFO Overflow Frames */
+ Ifx_ETH_RX_VLAN_FRAMES_GOOD_BAD RX_VLAN_FRAMES_GOOD_BAD; /**< \brief 11D8, Register 118 - Receive Frame Count for Good and Bad VLAN Frames */
+ Ifx_ETH_RX_WATCHDOG_ERROR_FRAMES RX_WATCHDOG_ERROR_FRAMES; /**< \brief 11DC, Register 119 - Receive Frame Count for Watchdog Error Frames */
+ Ifx_ETH_RX_RECEIVE_ERROR_FRAMES RX_RECEIVE_ERROR_FRAMES; /**< \brief 11E0, Register 120 - Receive Frame Count for Receive Error Frames */
+ Ifx_ETH_RX_CONTROL_FRAMES_GOOD RX_CONTROL_FRAMES_GOOD; /**< \brief 11E4, Register 121 - Receive Frame Count for Good Control Frames Frames */
+ unsigned char reserved_11E8[24]; /**< \brief 11E8, \internal Reserved */
+ Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK MMC_IPC_RECEIVE_INTERRUPT_MASK; /**< \brief 1200, Register 128 - MMC Receive Checksum Offload Interrupt Mask Register */
+ unsigned char reserved_1204[4]; /**< \brief 1204, \internal Reserved */
+ Ifx_ETH_MMC_IPC_RECEIVE_INTERRUPT MMC_IPC_RECEIVE_INTERRUPT; /**< \brief 1208, Register 130 - MMC Receive Checksum Offload Interrupt Register */
+ unsigned char reserved_120C[4]; /**< \brief 120C, \internal Reserved */
+ Ifx_ETH_RXIPV4_GOOD_FRAMES RXIPV4_GOOD_FRAMES; /**< \brief 1210, Register 132 - Receive IPV4 Good Frame Counter Register */
+ Ifx_ETH_RXIPV4_HEADER_ERROR_FRAMES RXIPV4_HEADER_ERROR_FRAMES; /**< \brief 1214, Register 133 - Receive IPV4 Header Error Frame Counter Register */
+ Ifx_ETH_RXIPV4_NO_PAYLOAD_FRAMES RXIPV4_NO_PAYLOAD_FRAMES; /**< \brief 1218, Register 134 - Receive IPV4 No Payload Frame Counter Register */
+ Ifx_ETH_RXIPV4_FRAGMENTED_FRAMES RXIPV4_FRAGMENTED_FRAMES; /**< \brief 121C, Register 135 - Receive IPV4 Fragmented Frame Counter Register */
+ Ifx_ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES; /**< \brief 1220, Register 136 - Receive IPV4 UDP Checksum Disabled Frame Counter Register */
+ Ifx_ETH_RXIPV6_GOOD_FRAMES RXIPV6_GOOD_FRAMES; /**< \brief 1224, Register 137 - Receive IPV6 Good Frame Counter Register */
+ Ifx_ETH_RXIPV6_HEADER_ERROR_FRAMES RXIPV6_HEADER_ERROR_FRAMES; /**< \brief 1228, Register 138 - Receive IPV6 Header Error Frame Counter Register */
+ Ifx_ETH_RXIPV6_NO_PAYLOAD_FRAMES RXIPV6_NO_PAYLOAD_FRAMES; /**< \brief 122C, Register 139 - Receive IPV6 No Payload Frame Counter Register */
+ Ifx_ETH_RXUDP_GOOD_FRAMES RXUDP_GOOD_FRAMES; /**< \brief 1230, Register 140 - Receive UDP Good Frame Counter Register */
+ Ifx_ETH_RXUDP_ERROR_FRAMES RXUDP_ERROR_FRAMES; /**< \brief 1234, Register 141 - Receive UDP Error Frame Counter Register */
+ Ifx_ETH_RXTCP_GOOD_FRAMES RXTCP_GOOD_FRAMES; /**< \brief 1238, Register 142 - Receive TCP Good Frame Counter Register */
+ Ifx_ETH_RXTCP_ERROR_FRAMES RXTCP_ERROR_FRAMES; /**< \brief 123C, Register 143 - Receive TCP Error Frame Counter Register */
+ Ifx_ETH_RXICMP_GOOD_FRAMES RXICMP_GOOD_FRAMES; /**< \brief 1240, Register 144 - Receive ICMP Good Frame Counter Register */
+ Ifx_ETH_RXICMP_ERROR_FRAMES RXICMP_ERROR_FRAMES; /**< \brief 1244, Register 145 - Receive ICMP Error Frame Counter Register */
+ unsigned char reserved_1248[8]; /**< \brief 1248, \internal Reserved */
+ Ifx_ETH_RXIPV4_GOOD_OCTETS RXIPV4_GOOD_OCTETS; /**< \brief 1250, Register 148 - Receive IPV4 Good Octet Counter Register */
+ Ifx_ETH_RXIPV4_HEADER_ERROR_OCTETS RXIPV4_HEADER_ERROR_OCTETS; /**< \brief 1254, Register 149 - Receive IPV4 Header Error Octet Counter Register */
+ Ifx_ETH_RXIPV4_NO_PAYLOAD_OCTETS RXIPV4_NO_PAYLOAD_OCTETS; /**< \brief 1258, Register 150 - Receive IPV4 No Payload Octet Counter Register */
+ Ifx_ETH_RXIPV4_FRAGMENTED_OCTETS RXIPV4_FRAGMENTED_OCTETS; /**< \brief 125C, Register 151 - Receive IPV4 Fragmented Octet Counter Register */
+ Ifx_ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS; /**< \brief 1260, Register 152 - Receive IPV4 Fragmented Octet Counter Register */
+ Ifx_ETH_RXIPV6_GOOD_OCTETS RXIPV6_GOOD_OCTETS; /**< \brief 1264, Register 153 - Receive IPV6 Good Octet Counter Register */
+ Ifx_ETH_RXIPV6_HEADER_ERROR_OCTETS RXIPV6_HEADER_ERROR_OCTETS; /**< \brief 1268, Register 154 - Receive IPV6 Header Error Octet Counter Register */
+ Ifx_ETH_RXIPV6_NO_PAYLOAD_OCTETS RXIPV6_NO_PAYLOAD_OCTETS; /**< \brief 126C, Register 155 - Receive IPV6 No Payload Octet Counter Register */
+ Ifx_ETH_RXUDP_GOOD_OCTETS RXUDP_GOOD_OCTETS; /**< \brief 1270, Register 156 - Receive UDP Good Octet Counter Register */
+ Ifx_ETH_RXUDP_ERROR_OCTETS RXUDP_ERROR_OCTETS; /**< \brief 1274, Register 157 - Receive UDP Error Octet Counter Register */
+ Ifx_ETH_RXTCP_GOOD_OCTETS RXTCP_GOOD_OCTETS; /**< \brief 1278, Register 158 - Receive TCP Good Octet Counter Register */
+ Ifx_ETH_RXTCP_ERROR_OCTETS RXTCP_ERROR_OCTETS; /**< \brief 127C, Register 159 - Receive TCP Error Octet Counter Register */
+ Ifx_ETH_RXICMP_GOOD_OCTETS RXICMP_GOOD_OCTETS; /**< \brief 1280, Register 160 - Receive ICMP Good Octet Counter Register */
+ Ifx_ETH_RXICMP_ERROR_OCTETS RXICMP_ERROR_OCTETS; /**< \brief 1284, Register 161 - Receive ICMP Error Octet Counter Register */
+ unsigned char reserved_1288[1144]; /**< \brief 1288, \internal Reserved */
+ Ifx_ETH_TIMESTAMP_CONTROL TIMESTAMP_CONTROL; /**< \brief 1700, Register 448 - Timestamp Control Register */
+ Ifx_ETH_SUB_SECOND_INCREMENT SUB_SECOND_INCREMENT; /**< \brief 1704, Register 449 - Sub-Second Increment Register */
+ Ifx_ETH_SYSTEM_TIME_SECONDS SYSTEM_TIME_SECONDS; /**< \brief 1708, Register 450 - System Time - Seconds Register */
+ Ifx_ETH_SYSTEM_TIME_NANOSECONDS SYSTEM_TIME_NANOSECONDS; /**< \brief 170C, Register 451 - System Time - Nanoseconds Register */
+ Ifx_ETH_SYSTEM_TIME_SECONDS_UPDATE SYSTEM_TIME_SECONDS_UPDATE; /**< \brief 1710, Register 452 - System Time - Seconds Update Register */
+ Ifx_ETH_SYSTEM_TIME_NANOSECONDS_UPDATE SYSTEM_TIME_NANOSECONDS_UPDATE; /**< \brief 1714, Register 453 - System Time - Nanoseconds Update Register */
+ Ifx_ETH_TIMESTAMP_ADDEND TIMESTAMP_ADDEND; /**< \brief 1718, Register 454 - Timestamp Addend Register */
+ Ifx_ETH_TARGET_TIME_SECONDS TARGET_TIME_SECONDS; /**< \brief 171C, Register 455 - Target Time Seconds Register */
+ Ifx_ETH_TARGET_TIME_NANOSECONDS TARGET_TIME_NANOSECONDS; /**< \brief 1720, Register 456 - Target Time Nanoseconds Register */
+ Ifx_ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS SYSTEM_TIME_HIGHER_WORD_SECONDS; /**< \brief 1724, Register 457 - System Time - Higher Word Seconds Register */
+ Ifx_ETH_TIMESTAMP_STATUS TIMESTAMP_STATUS; /**< \brief 1728, Register 458 - Timestamp Status Register */
+ Ifx_ETH_PPS_CONTROL PPS_CONTROL; /**< \brief 172C, Register 459 - PPS Control Register */
+ unsigned char reserved_1730[208]; /**< \brief 1730, \internal Reserved */
+ Ifx_ETH_MAC_ADDRESS MAC_ADDRESS_G1[16]; /**< \brief 1800, MAC Address \note Array index shifted by 16. Example: defined register MAC_ADDRESS_G1[0]/MAC_ADDRESS_G10 corresponds to user manual MAC_ADDRESS_G116, ... */
+ unsigned char reserved_1880[1920]; /**< \brief 1880, \internal Reserved */
+ Ifx_ETH_BUS_MODE BUS_MODE; /**< \brief 2000, Register 0 - Bus Mode Register */
+ Ifx_ETH_TRANSMIT_POLL_DEMAND TRANSMIT_POLL_DEMAND; /**< \brief 2004, Register 1 - Transmit Poll Demand Register */
+ Ifx_ETH_RECEIVE_POLL_DEMAND RECEIVE_POLL_DEMAND; /**< \brief 2008, Register 2 - Receive Poll Demand Register */
+ Ifx_ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS RECEIVE_DESCRIPTOR_LIST_ADDRESS; /**< \brief 200C, Register 3 - Receive Descriptor List Address Register */
+ Ifx_ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS TRANSMIT_DESCRIPTOR_LIST_ADDRESS; /**< \brief 2010, Register 4 - Transmit Descriptor List Address Register */
+ Ifx_ETH_STATUS STATUS; /**< \brief 2014, Register 5 - Status Register */
+ Ifx_ETH_OPERATION_MODE OPERATION_MODE; /**< \brief 2018, Register 6 - Operation Mode Register */
+ Ifx_ETH_INTERRUPT_ENABLE INTERRUPT_ENABLE; /**< \brief 201C, Register 7 - Interrupt Enable Register */
+ Ifx_ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER; /**< \brief 2020, Register 8 - Missed Frame and Buffer Overflow Counter Register */
+ Ifx_ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER RECEIVE_INTERRUPT_WATCHDOG_TIMER; /**< \brief 2024, Register 9 - Receive Interrupt Watchdog Timer Register */
+ unsigned char reserved_2028[4]; /**< \brief 2028, \internal Reserved */
+ Ifx_ETH_AHB_OR_AXI_STATUS AHB_OR_AXI_STATUS; /**< \brief 202C, Register 11 - AHB or AXI Status Register */
+ unsigned char reserved_2030[24]; /**< \brief 2030, \internal Reserved */
+ Ifx_ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR CURRENT_HOST_TRANSMIT_DESCRIPTOR; /**< \brief 2048, Register 18 - Current Host Transmit Descriptor Register */
+ Ifx_ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR CURRENT_HOST_RECEIVE_DESCRIPTOR; /**< \brief 204C, Register 19 - Current Host Receive Descriptor Register */
+ Ifx_ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS; /**< \brief 2050, Register 20 - Current Host Transmit Buffer Address Register */
+ Ifx_ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS CURRENT_HOST_RECEIVE_BUFFER_ADDRESS; /**< \brief 2054, Register 21 - Current Host Receive Buffer Address Register */
+ Ifx_ETH_HW_FEATURE HW_FEATURE; /**< \brief 2058, Register 22 - HW Feature Register */
+ unsigned char reserved_205C[164]; /**< \brief 205C, \internal Reserved */
+} Ifx_ETH;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXETH_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxFce_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxFce_bf.h
new file mode 100644
index 0000000..1d05012
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxFce_bf.h
@@ -0,0 +1,702 @@
+/**
+ * \file IfxFce_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Fce_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Fce
+ *
+ */
+#ifndef IFXFCE_BF_H
+#define IFXFCE_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Fce_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN0 */
+#define IFX_FCE_ACCEN0_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN0 */
+#define IFX_FCE_ACCEN0_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN0 */
+#define IFX_FCE_ACCEN0_EN0_OFF (0u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN10 */
+#define IFX_FCE_ACCEN0_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN10 */
+#define IFX_FCE_ACCEN0_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN10 */
+#define IFX_FCE_ACCEN0_EN10_OFF (10u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN11 */
+#define IFX_FCE_ACCEN0_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN11 */
+#define IFX_FCE_ACCEN0_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN11 */
+#define IFX_FCE_ACCEN0_EN11_OFF (11u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN12 */
+#define IFX_FCE_ACCEN0_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN12 */
+#define IFX_FCE_ACCEN0_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN12 */
+#define IFX_FCE_ACCEN0_EN12_OFF (12u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN13 */
+#define IFX_FCE_ACCEN0_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN13 */
+#define IFX_FCE_ACCEN0_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN13 */
+#define IFX_FCE_ACCEN0_EN13_OFF (13u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN14 */
+#define IFX_FCE_ACCEN0_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN14 */
+#define IFX_FCE_ACCEN0_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN14 */
+#define IFX_FCE_ACCEN0_EN14_OFF (14u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN15 */
+#define IFX_FCE_ACCEN0_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN15 */
+#define IFX_FCE_ACCEN0_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN15 */
+#define IFX_FCE_ACCEN0_EN15_OFF (15u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN16 */
+#define IFX_FCE_ACCEN0_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN16 */
+#define IFX_FCE_ACCEN0_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN16 */
+#define IFX_FCE_ACCEN0_EN16_OFF (16u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN17 */
+#define IFX_FCE_ACCEN0_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN17 */
+#define IFX_FCE_ACCEN0_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN17 */
+#define IFX_FCE_ACCEN0_EN17_OFF (17u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN18 */
+#define IFX_FCE_ACCEN0_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN18 */
+#define IFX_FCE_ACCEN0_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN18 */
+#define IFX_FCE_ACCEN0_EN18_OFF (18u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN19 */
+#define IFX_FCE_ACCEN0_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN19 */
+#define IFX_FCE_ACCEN0_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN19 */
+#define IFX_FCE_ACCEN0_EN19_OFF (19u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN1 */
+#define IFX_FCE_ACCEN0_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN1 */
+#define IFX_FCE_ACCEN0_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN1 */
+#define IFX_FCE_ACCEN0_EN1_OFF (1u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN20 */
+#define IFX_FCE_ACCEN0_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN20 */
+#define IFX_FCE_ACCEN0_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN20 */
+#define IFX_FCE_ACCEN0_EN20_OFF (20u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN21 */
+#define IFX_FCE_ACCEN0_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN21 */
+#define IFX_FCE_ACCEN0_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN21 */
+#define IFX_FCE_ACCEN0_EN21_OFF (21u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN22 */
+#define IFX_FCE_ACCEN0_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN22 */
+#define IFX_FCE_ACCEN0_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN22 */
+#define IFX_FCE_ACCEN0_EN22_OFF (22u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN23 */
+#define IFX_FCE_ACCEN0_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN23 */
+#define IFX_FCE_ACCEN0_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN23 */
+#define IFX_FCE_ACCEN0_EN23_OFF (23u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN24 */
+#define IFX_FCE_ACCEN0_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN24 */
+#define IFX_FCE_ACCEN0_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN24 */
+#define IFX_FCE_ACCEN0_EN24_OFF (24u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN25 */
+#define IFX_FCE_ACCEN0_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN25 */
+#define IFX_FCE_ACCEN0_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN25 */
+#define IFX_FCE_ACCEN0_EN25_OFF (25u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN26 */
+#define IFX_FCE_ACCEN0_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN26 */
+#define IFX_FCE_ACCEN0_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN26 */
+#define IFX_FCE_ACCEN0_EN26_OFF (26u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN27 */
+#define IFX_FCE_ACCEN0_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN27 */
+#define IFX_FCE_ACCEN0_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN27 */
+#define IFX_FCE_ACCEN0_EN27_OFF (27u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN28 */
+#define IFX_FCE_ACCEN0_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN28 */
+#define IFX_FCE_ACCEN0_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN28 */
+#define IFX_FCE_ACCEN0_EN28_OFF (28u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN29 */
+#define IFX_FCE_ACCEN0_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN29 */
+#define IFX_FCE_ACCEN0_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN29 */
+#define IFX_FCE_ACCEN0_EN29_OFF (29u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN2 */
+#define IFX_FCE_ACCEN0_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN2 */
+#define IFX_FCE_ACCEN0_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN2 */
+#define IFX_FCE_ACCEN0_EN2_OFF (2u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN30 */
+#define IFX_FCE_ACCEN0_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN30 */
+#define IFX_FCE_ACCEN0_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN30 */
+#define IFX_FCE_ACCEN0_EN30_OFF (30u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN31 */
+#define IFX_FCE_ACCEN0_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN31 */
+#define IFX_FCE_ACCEN0_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN31 */
+#define IFX_FCE_ACCEN0_EN31_OFF (31u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN3 */
+#define IFX_FCE_ACCEN0_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN3 */
+#define IFX_FCE_ACCEN0_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN3 */
+#define IFX_FCE_ACCEN0_EN3_OFF (3u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN4 */
+#define IFX_FCE_ACCEN0_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN4 */
+#define IFX_FCE_ACCEN0_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN4 */
+#define IFX_FCE_ACCEN0_EN4_OFF (4u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN5 */
+#define IFX_FCE_ACCEN0_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN5 */
+#define IFX_FCE_ACCEN0_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN5 */
+#define IFX_FCE_ACCEN0_EN5_OFF (5u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN6 */
+#define IFX_FCE_ACCEN0_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN6 */
+#define IFX_FCE_ACCEN0_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN6 */
+#define IFX_FCE_ACCEN0_EN6_OFF (6u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN7 */
+#define IFX_FCE_ACCEN0_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN7 */
+#define IFX_FCE_ACCEN0_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN7 */
+#define IFX_FCE_ACCEN0_EN7_OFF (7u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN8 */
+#define IFX_FCE_ACCEN0_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN8 */
+#define IFX_FCE_ACCEN0_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN8 */
+#define IFX_FCE_ACCEN0_EN8_OFF (8u)
+
+/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN9 */
+#define IFX_FCE_ACCEN0_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN9 */
+#define IFX_FCE_ACCEN0_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN9 */
+#define IFX_FCE_ACCEN0_EN9_OFF (9u)
+
+/** \brief Length for Ifx_FCE_CFG_Bits.ALR */
+#define IFX_FCE_CFG_ALR_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_CFG_Bits.ALR */
+#define IFX_FCE_CFG_ALR_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_CFG_Bits.ALR */
+#define IFX_FCE_CFG_ALR_OFF (5u)
+
+/** \brief Length for Ifx_FCE_CFG_Bits.BEI */
+#define IFX_FCE_CFG_BEI_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_CFG_Bits.BEI */
+#define IFX_FCE_CFG_BEI_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_CFG_Bits.BEI */
+#define IFX_FCE_CFG_BEI_OFF (3u)
+
+/** \brief Length for Ifx_FCE_CFG_Bits.CCE */
+#define IFX_FCE_CFG_CCE_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_CFG_Bits.CCE */
+#define IFX_FCE_CFG_CCE_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_CFG_Bits.CCE */
+#define IFX_FCE_CFG_CCE_OFF (4u)
+
+/** \brief Length for Ifx_FCE_CFG_Bits.CEI */
+#define IFX_FCE_CFG_CEI_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_CFG_Bits.CEI */
+#define IFX_FCE_CFG_CEI_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_CFG_Bits.CEI */
+#define IFX_FCE_CFG_CEI_OFF (1u)
+
+/** \brief Length for Ifx_FCE_CFG_Bits.CMI */
+#define IFX_FCE_CFG_CMI_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_CFG_Bits.CMI */
+#define IFX_FCE_CFG_CMI_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_CFG_Bits.CMI */
+#define IFX_FCE_CFG_CMI_OFF (0u)
+
+/** \brief Length for Ifx_FCE_CFG_Bits.LEI */
+#define IFX_FCE_CFG_LEI_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_CFG_Bits.LEI */
+#define IFX_FCE_CFG_LEI_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_CFG_Bits.LEI */
+#define IFX_FCE_CFG_LEI_OFF (2u)
+
+/** \brief Length for Ifx_FCE_CFG_Bits.REFIN */
+#define IFX_FCE_CFG_REFIN_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_CFG_Bits.REFIN */
+#define IFX_FCE_CFG_REFIN_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_CFG_Bits.REFIN */
+#define IFX_FCE_CFG_REFIN_OFF (8u)
+
+/** \brief Length for Ifx_FCE_CFG_Bits.REFOUT */
+#define IFX_FCE_CFG_REFOUT_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_CFG_Bits.REFOUT */
+#define IFX_FCE_CFG_REFOUT_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_CFG_Bits.REFOUT */
+#define IFX_FCE_CFG_REFOUT_OFF (9u)
+
+/** \brief Length for Ifx_FCE_CFG_Bits.XSEL */
+#define IFX_FCE_CFG_XSEL_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_CFG_Bits.XSEL */
+#define IFX_FCE_CFG_XSEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_CFG_Bits.XSEL */
+#define IFX_FCE_CFG_XSEL_OFF (10u)
+
+/** \brief Length for Ifx_FCE_CLC_Bits.DISR */
+#define IFX_FCE_CLC_DISR_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_CLC_Bits.DISR */
+#define IFX_FCE_CLC_DISR_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_CLC_Bits.DISR */
+#define IFX_FCE_CLC_DISR_OFF (0u)
+
+/** \brief Length for Ifx_FCE_CLC_Bits.DISS */
+#define IFX_FCE_CLC_DISS_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_CLC_Bits.DISS */
+#define IFX_FCE_CLC_DISS_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_CLC_Bits.DISS */
+#define IFX_FCE_CLC_DISS_OFF (1u)
+
+/** \brief Length for Ifx_FCE_CTR_Bits.FCM */
+#define IFX_FCE_CTR_FCM_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_CTR_Bits.FCM */
+#define IFX_FCE_CTR_FCM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_CTR_Bits.FCM */
+#define IFX_FCE_CTR_FCM_OFF (0u)
+
+/** \brief Length for Ifx_FCE_CTR_Bits.FRM_CFG */
+#define IFX_FCE_CTR_FRM_CFG_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_CTR_Bits.FRM_CFG */
+#define IFX_FCE_CTR_FRM_CFG_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_CTR_Bits.FRM_CFG */
+#define IFX_FCE_CTR_FRM_CFG_OFF (1u)
+
+/** \brief Length for Ifx_FCE_CTR_Bits.FRM_CHECK */
+#define IFX_FCE_CTR_FRM_CHECK_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_CTR_Bits.FRM_CHECK */
+#define IFX_FCE_CTR_FRM_CHECK_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_CTR_Bits.FRM_CHECK */
+#define IFX_FCE_CTR_FRM_CHECK_OFF (2u)
+
+/** \brief Length for Ifx_FCE_ID_Bits.MODNUMBER */
+#define IFX_FCE_ID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_FCE_ID_Bits.MODNUMBER */
+#define IFX_FCE_ID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_FCE_ID_Bits.MODNUMBER */
+#define IFX_FCE_ID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_FCE_ID_Bits.MODREV */
+#define IFX_FCE_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_FCE_ID_Bits.MODREV */
+#define IFX_FCE_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_FCE_ID_Bits.MODREV */
+#define IFX_FCE_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_FCE_ID_Bits.MODTYPE */
+#define IFX_FCE_ID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_FCE_ID_Bits.MODTYPE */
+#define IFX_FCE_ID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_FCE_ID_Bits.MODTYPE */
+#define IFX_FCE_ID_MODTYPE_OFF (8u)
+
+/** \brief Length for Ifx_FCE_IN0_CHECK_Bits.CHECK */
+#define IFX_FCE_IN0_CHECK_CHECK_LEN (32u)
+
+/** \brief Mask for Ifx_FCE_IN0_CHECK_Bits.CHECK */
+#define IFX_FCE_IN0_CHECK_CHECK_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_FCE_IN0_CHECK_Bits.CHECK */
+#define IFX_FCE_IN0_CHECK_CHECK_OFF (0u)
+
+/** \brief Length for Ifx_FCE_IN0_CRC_Bits.CRC */
+#define IFX_FCE_IN0_CRC_CRC_LEN (32u)
+
+/** \brief Mask for Ifx_FCE_IN0_CRC_Bits.CRC */
+#define IFX_FCE_IN0_CRC_CRC_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_FCE_IN0_CRC_Bits.CRC */
+#define IFX_FCE_IN0_CRC_CRC_OFF (0u)
+
+/** \brief Length for Ifx_FCE_IN0_IR_Bits.IR */
+#define IFX_FCE_IN0_IR_IR_LEN (32u)
+
+/** \brief Mask for Ifx_FCE_IN0_IR_Bits.IR */
+#define IFX_FCE_IN0_IR_IR_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_FCE_IN0_IR_Bits.IR */
+#define IFX_FCE_IN0_IR_IR_OFF (0u)
+
+/** \brief Length for Ifx_FCE_IN0_RES_Bits.RES */
+#define IFX_FCE_IN0_RES_RES_LEN (32u)
+
+/** \brief Mask for Ifx_FCE_IN0_RES_Bits.RES */
+#define IFX_FCE_IN0_RES_RES_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_FCE_IN0_RES_Bits.RES */
+#define IFX_FCE_IN0_RES_RES_OFF (0u)
+
+/** \brief Length for Ifx_FCE_IN1_CHECK_Bits.CHECK */
+#define IFX_FCE_IN1_CHECK_CHECK_LEN (32u)
+
+/** \brief Mask for Ifx_FCE_IN1_CHECK_Bits.CHECK */
+#define IFX_FCE_IN1_CHECK_CHECK_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_FCE_IN1_CHECK_Bits.CHECK */
+#define IFX_FCE_IN1_CHECK_CHECK_OFF (0u)
+
+/** \brief Length for Ifx_FCE_IN1_CRC_Bits.CRC */
+#define IFX_FCE_IN1_CRC_CRC_LEN (32u)
+
+/** \brief Mask for Ifx_FCE_IN1_CRC_Bits.CRC */
+#define IFX_FCE_IN1_CRC_CRC_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_FCE_IN1_CRC_Bits.CRC */
+#define IFX_FCE_IN1_CRC_CRC_OFF (0u)
+
+/** \brief Length for Ifx_FCE_IN1_IR_Bits.IR */
+#define IFX_FCE_IN1_IR_IR_LEN (32u)
+
+/** \brief Mask for Ifx_FCE_IN1_IR_Bits.IR */
+#define IFX_FCE_IN1_IR_IR_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_FCE_IN1_IR_Bits.IR */
+#define IFX_FCE_IN1_IR_IR_OFF (0u)
+
+/** \brief Length for Ifx_FCE_IN1_RES_Bits.RES */
+#define IFX_FCE_IN1_RES_RES_LEN (32u)
+
+/** \brief Mask for Ifx_FCE_IN1_RES_Bits.RES */
+#define IFX_FCE_IN1_RES_RES_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_FCE_IN1_RES_Bits.RES */
+#define IFX_FCE_IN1_RES_RES_OFF (0u)
+
+/** \brief Length for Ifx_FCE_IN2_CHECK_Bits.CHECK */
+#define IFX_FCE_IN2_CHECK_CHECK_LEN (16u)
+
+/** \brief Mask for Ifx_FCE_IN2_CHECK_Bits.CHECK */
+#define IFX_FCE_IN2_CHECK_CHECK_MSK (0xffffu)
+
+/** \brief Offset for Ifx_FCE_IN2_CHECK_Bits.CHECK */
+#define IFX_FCE_IN2_CHECK_CHECK_OFF (0u)
+
+/** \brief Length for Ifx_FCE_IN2_CRC_Bits.CRC */
+#define IFX_FCE_IN2_CRC_CRC_LEN (16u)
+
+/** \brief Mask for Ifx_FCE_IN2_CRC_Bits.CRC */
+#define IFX_FCE_IN2_CRC_CRC_MSK (0xffffu)
+
+/** \brief Offset for Ifx_FCE_IN2_CRC_Bits.CRC */
+#define IFX_FCE_IN2_CRC_CRC_OFF (0u)
+
+/** \brief Length for Ifx_FCE_IN2_IR_Bits.IR */
+#define IFX_FCE_IN2_IR_IR_LEN (16u)
+
+/** \brief Mask for Ifx_FCE_IN2_IR_Bits.IR */
+#define IFX_FCE_IN2_IR_IR_MSK (0xffffu)
+
+/** \brief Offset for Ifx_FCE_IN2_IR_Bits.IR */
+#define IFX_FCE_IN2_IR_IR_OFF (0u)
+
+/** \brief Length for Ifx_FCE_IN2_RES_Bits.RES */
+#define IFX_FCE_IN2_RES_RES_LEN (16u)
+
+/** \brief Mask for Ifx_FCE_IN2_RES_Bits.RES */
+#define IFX_FCE_IN2_RES_RES_MSK (0xffffu)
+
+/** \brief Offset for Ifx_FCE_IN2_RES_Bits.RES */
+#define IFX_FCE_IN2_RES_RES_OFF (0u)
+
+/** \brief Length for Ifx_FCE_IN3_CHECK_Bits.CHECK */
+#define IFX_FCE_IN3_CHECK_CHECK_LEN (8u)
+
+/** \brief Mask for Ifx_FCE_IN3_CHECK_Bits.CHECK */
+#define IFX_FCE_IN3_CHECK_CHECK_MSK (0xffu)
+
+/** \brief Offset for Ifx_FCE_IN3_CHECK_Bits.CHECK */
+#define IFX_FCE_IN3_CHECK_CHECK_OFF (0u)
+
+/** \brief Length for Ifx_FCE_IN3_CRC_Bits.CRC */
+#define IFX_FCE_IN3_CRC_CRC_LEN (8u)
+
+/** \brief Mask for Ifx_FCE_IN3_CRC_Bits.CRC */
+#define IFX_FCE_IN3_CRC_CRC_MSK (0xffu)
+
+/** \brief Offset for Ifx_FCE_IN3_CRC_Bits.CRC */
+#define IFX_FCE_IN3_CRC_CRC_OFF (0u)
+
+/** \brief Length for Ifx_FCE_IN3_IR_Bits.IR */
+#define IFX_FCE_IN3_IR_IR_LEN (8u)
+
+/** \brief Mask for Ifx_FCE_IN3_IR_Bits.IR */
+#define IFX_FCE_IN3_IR_IR_MSK (0xffu)
+
+/** \brief Offset for Ifx_FCE_IN3_IR_Bits.IR */
+#define IFX_FCE_IN3_IR_IR_OFF (0u)
+
+/** \brief Length for Ifx_FCE_IN3_RES_Bits.RES */
+#define IFX_FCE_IN3_RES_RES_LEN (8u)
+
+/** \brief Mask for Ifx_FCE_IN3_RES_Bits.RES */
+#define IFX_FCE_IN3_RES_RES_MSK (0xffu)
+
+/** \brief Offset for Ifx_FCE_IN3_RES_Bits.RES */
+#define IFX_FCE_IN3_RES_RES_OFF (0u)
+
+/** \brief Length for Ifx_FCE_KRST0_Bits.RST */
+#define IFX_FCE_KRST0_RST_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_KRST0_Bits.RST */
+#define IFX_FCE_KRST0_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_KRST0_Bits.RST */
+#define IFX_FCE_KRST0_RST_OFF (0u)
+
+/** \brief Length for Ifx_FCE_KRST0_Bits.RSTSTAT */
+#define IFX_FCE_KRST0_RSTSTAT_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_KRST0_Bits.RSTSTAT */
+#define IFX_FCE_KRST0_RSTSTAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_KRST0_Bits.RSTSTAT */
+#define IFX_FCE_KRST0_RSTSTAT_OFF (1u)
+
+/** \brief Length for Ifx_FCE_KRST1_Bits.RST */
+#define IFX_FCE_KRST1_RST_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_KRST1_Bits.RST */
+#define IFX_FCE_KRST1_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_KRST1_Bits.RST */
+#define IFX_FCE_KRST1_RST_OFF (0u)
+
+/** \brief Length for Ifx_FCE_KRSTCLR_Bits.CLR */
+#define IFX_FCE_KRSTCLR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_KRSTCLR_Bits.CLR */
+#define IFX_FCE_KRSTCLR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_KRSTCLR_Bits.CLR */
+#define IFX_FCE_KRSTCLR_CLR_OFF (0u)
+
+/** \brief Length for Ifx_FCE_LENGTH_Bits.LENGTH */
+#define IFX_FCE_LENGTH_LENGTH_LEN (16u)
+
+/** \brief Mask for Ifx_FCE_LENGTH_Bits.LENGTH */
+#define IFX_FCE_LENGTH_LENGTH_MSK (0xffffu)
+
+/** \brief Offset for Ifx_FCE_LENGTH_Bits.LENGTH */
+#define IFX_FCE_LENGTH_LENGTH_OFF (0u)
+
+/** \brief Length for Ifx_FCE_STS_Bits.BEF */
+#define IFX_FCE_STS_BEF_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_STS_Bits.BEF */
+#define IFX_FCE_STS_BEF_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_STS_Bits.BEF */
+#define IFX_FCE_STS_BEF_OFF (3u)
+
+/** \brief Length for Ifx_FCE_STS_Bits.CEF */
+#define IFX_FCE_STS_CEF_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_STS_Bits.CEF */
+#define IFX_FCE_STS_CEF_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_STS_Bits.CEF */
+#define IFX_FCE_STS_CEF_OFF (1u)
+
+/** \brief Length for Ifx_FCE_STS_Bits.CMF */
+#define IFX_FCE_STS_CMF_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_STS_Bits.CMF */
+#define IFX_FCE_STS_CMF_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_STS_Bits.CMF */
+#define IFX_FCE_STS_CMF_OFF (0u)
+
+/** \brief Length for Ifx_FCE_STS_Bits.LEF */
+#define IFX_FCE_STS_LEF_LEN (1u)
+
+/** \brief Mask for Ifx_FCE_STS_Bits.LEF */
+#define IFX_FCE_STS_LEF_MSK (0x1u)
+
+/** \brief Offset for Ifx_FCE_STS_Bits.LEF */
+#define IFX_FCE_STS_LEF_OFF (2u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXFCE_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxFce_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxFce_reg.h
new file mode 100644
index 0000000..b5c1973
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxFce_reg.h
@@ -0,0 +1,363 @@
+/**
+ * \file IfxFce_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Fce_Cfg Fce address
+ * \ingroup IfxLld_Fce
+ *
+ * \defgroup IfxLld_Fce_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Fce_Cfg
+ *
+ * \defgroup IfxLld_Fce_Cfg_Fce0 2-FCE0
+ * \ingroup IfxLld_Fce_Cfg
+ *
+ */
+#ifndef IFXFCE_REG_H
+#define IFXFCE_REG_H 1
+/******************************************************************************/
+#include "IfxFce_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Fce_Cfg_BaseAddress
+ * \{ */
+
+/** \brief FCE object */
+#define MODULE_FCE0 /*lint --e(923)*/ (*(Ifx_FCE*)0xF0003F00u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Fce_Cfg_Fce0
+ * \{ */
+
+/** \brief FC, Access Enable Register 0 */
+#define FCE0_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_FCE_ACCEN0*)0xF0003FFCu)
+
+/** Alias (User Manual Name) for FCE0_ACCEN0.
+* To use register names with standard convension, please use FCE0_ACCEN0.
+*/
+#define FCE_ACCEN0 (FCE0_ACCEN0)
+
+/** \brief F8, Access Enable Register 1 */
+#define FCE0_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_FCE_ACCEN1*)0xF0003FF8u)
+
+/** Alias (User Manual Name) for FCE0_ACCEN1.
+* To use register names with standard convension, please use FCE0_ACCEN1.
+*/
+#define FCE_ACCEN1 (FCE0_ACCEN1)
+
+/** \brief 0, Clock Control Register */
+#define FCE0_CLC /*lint --e(923)*/ (*(volatile Ifx_FCE_CLC*)0xF0003F00u)
+
+/** Alias (User Manual Name) for FCE0_CLC.
+* To use register names with standard convension, please use FCE0_CLC.
+*/
+#define FCE_CLC (FCE0_CLC)
+
+/** \brief 8, Module Identification Register */
+#define FCE0_ID /*lint --e(923)*/ (*(volatile Ifx_FCE_ID*)0xF0003F08u)
+
+/** Alias (User Manual Name) for FCE0_ID.
+* To use register names with standard convension, please use FCE0_ID.
+*/
+#define FCE_ID (FCE0_ID)
+
+/** \brief 28, CRC Configuration Register */
+#define FCE0_IN0_CFG /*lint --e(923)*/ (*(volatile Ifx_FCE_CFG*)0xF0003F28u)
+
+/** Alias (User Manual Name) for FCE0_IN0_CFG.
+* To use register names with standard convension, please use FCE0_IN0_CFG.
+*/
+#define FCE_CFG0 (FCE0_IN0_CFG)
+
+/** \brief 34, CRC Check Register */
+#define FCE0_IN0_CHECK /*lint --e(923)*/ (*(volatile Ifx_FCE_IN0_CHECK*)0xF0003F34u)
+
+/** Alias (User Manual Name) for FCE0_IN0_CHECK.
+* To use register names with standard convension, please use FCE0_IN0_CHECK.
+*/
+#define FCE_CHECK0 (FCE0_IN0_CHECK)
+
+/** \brief 38, CRC Register */
+#define FCE0_IN0_CRC /*lint --e(923)*/ (*(volatile Ifx_FCE_IN0_CRC*)0xF0003F38u)
+
+/** Alias (User Manual Name) for FCE0_IN0_CRC.
+* To use register names with standard convension, please use FCE0_IN0_CRC.
+*/
+#define FCE_CRC0 (FCE0_IN0_CRC)
+
+/** \brief 3C, CRC Test Register */
+#define FCE0_IN0_CTR /*lint --e(923)*/ (*(volatile Ifx_FCE_CTR*)0xF0003F3Cu)
+
+/** Alias (User Manual Name) for FCE0_IN0_CTR.
+* To use register names with standard convension, please use FCE0_IN0_CTR.
+*/
+#define FCE_CTR0 (FCE0_IN0_CTR)
+
+/** \brief 20, Input Register */
+#define FCE0_IN0_IR /*lint --e(923)*/ (*(volatile Ifx_FCE_IN0_IR*)0xF0003F20u)
+
+/** Alias (User Manual Name) for FCE0_IN0_IR.
+* To use register names with standard convension, please use FCE0_IN0_IR.
+*/
+#define FCE_IR0 (FCE0_IN0_IR)
+
+/** \brief 30, CRC Length Register */
+#define FCE0_IN0_LENGTH /*lint --e(923)*/ (*(volatile Ifx_FCE_LENGTH*)0xF0003F30u)
+
+/** Alias (User Manual Name) for FCE0_IN0_LENGTH.
+* To use register names with standard convension, please use FCE0_IN0_LENGTH.
+*/
+#define FCE_LENGTH0 (FCE0_IN0_LENGTH)
+
+/** \brief 24, CRC Result Register */
+#define FCE0_IN0_RES /*lint --e(923)*/ (*(volatile Ifx_FCE_IN0_RES*)0xF0003F24u)
+
+/** Alias (User Manual Name) for FCE0_IN0_RES.
+* To use register names with standard convension, please use FCE0_IN0_RES.
+*/
+#define FCE_RES0 (FCE0_IN0_RES)
+
+/** \brief 2C, CRC Status Register */
+#define FCE0_IN0_STS /*lint --e(923)*/ (*(volatile Ifx_FCE_STS*)0xF0003F2Cu)
+
+/** Alias (User Manual Name) for FCE0_IN0_STS.
+* To use register names with standard convension, please use FCE0_IN0_STS.
+*/
+#define FCE_STS0 (FCE0_IN0_STS)
+
+/** \brief 48, CRC Configuration Register */
+#define FCE0_IN1_CFG /*lint --e(923)*/ (*(volatile Ifx_FCE_CFG*)0xF0003F48u)
+
+/** Alias (User Manual Name) for FCE0_IN1_CFG.
+* To use register names with standard convension, please use FCE0_IN1_CFG.
+*/
+#define FCE_CFG1 (FCE0_IN1_CFG)
+
+/** \brief 54, CRC Check Register */
+#define FCE0_IN1_CHECK /*lint --e(923)*/ (*(volatile Ifx_FCE_IN1_CHECK*)0xF0003F54u)
+
+/** Alias (User Manual Name) for FCE0_IN1_CHECK.
+* To use register names with standard convension, please use FCE0_IN1_CHECK.
+*/
+#define FCE_CHECK1 (FCE0_IN1_CHECK)
+
+/** \brief 58, CRC Register */
+#define FCE0_IN1_CRC /*lint --e(923)*/ (*(volatile Ifx_FCE_IN1_CRC*)0xF0003F58u)
+
+/** Alias (User Manual Name) for FCE0_IN1_CRC.
+* To use register names with standard convension, please use FCE0_IN1_CRC.
+*/
+#define FCE_CRC1 (FCE0_IN1_CRC)
+
+/** \brief 5C, CRC Test Register */
+#define FCE0_IN1_CTR /*lint --e(923)*/ (*(volatile Ifx_FCE_CTR*)0xF0003F5Cu)
+
+/** Alias (User Manual Name) for FCE0_IN1_CTR.
+* To use register names with standard convension, please use FCE0_IN1_CTR.
+*/
+#define FCE_CTR1 (FCE0_IN1_CTR)
+
+/** \brief 40, Input Register */
+#define FCE0_IN1_IR /*lint --e(923)*/ (*(volatile Ifx_FCE_IN1_IR*)0xF0003F40u)
+
+/** Alias (User Manual Name) for FCE0_IN1_IR.
+* To use register names with standard convension, please use FCE0_IN1_IR.
+*/
+#define FCE_IR1 (FCE0_IN1_IR)
+
+/** \brief 50, CRC Length Register */
+#define FCE0_IN1_LENGTH /*lint --e(923)*/ (*(volatile Ifx_FCE_LENGTH*)0xF0003F50u)
+
+/** Alias (User Manual Name) for FCE0_IN1_LENGTH.
+* To use register names with standard convension, please use FCE0_IN1_LENGTH.
+*/
+#define FCE_LENGTH1 (FCE0_IN1_LENGTH)
+
+/** \brief 44, CRC Result Register */
+#define FCE0_IN1_RES /*lint --e(923)*/ (*(volatile Ifx_FCE_IN1_RES*)0xF0003F44u)
+
+/** Alias (User Manual Name) for FCE0_IN1_RES.
+* To use register names with standard convension, please use FCE0_IN1_RES.
+*/
+#define FCE_RES1 (FCE0_IN1_RES)
+
+/** \brief 4C, CRC Status Register */
+#define FCE0_IN1_STS /*lint --e(923)*/ (*(volatile Ifx_FCE_STS*)0xF0003F4Cu)
+
+/** Alias (User Manual Name) for FCE0_IN1_STS.
+* To use register names with standard convension, please use FCE0_IN1_STS.
+*/
+#define FCE_STS1 (FCE0_IN1_STS)
+
+/** \brief 68, CRC Configuration Register */
+#define FCE0_IN2_CFG /*lint --e(923)*/ (*(volatile Ifx_FCE_CFG*)0xF0003F68u)
+
+/** Alias (User Manual Name) for FCE0_IN2_CFG.
+* To use register names with standard convension, please use FCE0_IN2_CFG.
+*/
+#define FCE_CFG2 (FCE0_IN2_CFG)
+
+/** \brief 74, CRC Check Register */
+#define FCE0_IN2_CHECK /*lint --e(923)*/ (*(volatile Ifx_FCE_IN2_CHECK*)0xF0003F74u)
+
+/** Alias (User Manual Name) for FCE0_IN2_CHECK.
+* To use register names with standard convension, please use FCE0_IN2_CHECK.
+*/
+#define FCE_CHECK2 (FCE0_IN2_CHECK)
+
+/** \brief 78, CRC Register */
+#define FCE0_IN2_CRC /*lint --e(923)*/ (*(volatile Ifx_FCE_IN2_CRC*)0xF0003F78u)
+
+/** Alias (User Manual Name) for FCE0_IN2_CRC.
+* To use register names with standard convension, please use FCE0_IN2_CRC.
+*/
+#define FCE_CRC2 (FCE0_IN2_CRC)
+
+/** \brief 7C, CRC Test Register */
+#define FCE0_IN2_CTR /*lint --e(923)*/ (*(volatile Ifx_FCE_CTR*)0xF0003F7Cu)
+
+/** Alias (User Manual Name) for FCE0_IN2_CTR.
+* To use register names with standard convension, please use FCE0_IN2_CTR.
+*/
+#define FCE_CTR2 (FCE0_IN2_CTR)
+
+/** \brief 60, Input Register */
+#define FCE0_IN2_IR /*lint --e(923)*/ (*(volatile Ifx_FCE_IN2_IR*)0xF0003F60u)
+
+/** Alias (User Manual Name) for FCE0_IN2_IR.
+* To use register names with standard convension, please use FCE0_IN2_IR.
+*/
+#define FCE_IR2 (FCE0_IN2_IR)
+
+/** \brief 70, CRC Length Register */
+#define FCE0_IN2_LENGTH /*lint --e(923)*/ (*(volatile Ifx_FCE_LENGTH*)0xF0003F70u)
+
+/** Alias (User Manual Name) for FCE0_IN2_LENGTH.
+* To use register names with standard convension, please use FCE0_IN2_LENGTH.
+*/
+#define FCE_LENGTH2 (FCE0_IN2_LENGTH)
+
+/** \brief 64, CRC Result Register */
+#define FCE0_IN2_RES /*lint --e(923)*/ (*(volatile Ifx_FCE_IN2_RES*)0xF0003F64u)
+
+/** Alias (User Manual Name) for FCE0_IN2_RES.
+* To use register names with standard convension, please use FCE0_IN2_RES.
+*/
+#define FCE_RES2 (FCE0_IN2_RES)
+
+/** \brief 6C, CRC Status Register */
+#define FCE0_IN2_STS /*lint --e(923)*/ (*(volatile Ifx_FCE_STS*)0xF0003F6Cu)
+
+/** Alias (User Manual Name) for FCE0_IN2_STS.
+* To use register names with standard convension, please use FCE0_IN2_STS.
+*/
+#define FCE_STS2 (FCE0_IN2_STS)
+
+/** \brief 88, CRC Configuration Register */
+#define FCE0_IN3_CFG /*lint --e(923)*/ (*(volatile Ifx_FCE_CFG*)0xF0003F88u)
+
+/** Alias (User Manual Name) for FCE0_IN3_CFG.
+* To use register names with standard convension, please use FCE0_IN3_CFG.
+*/
+#define FCE_CFG3 (FCE0_IN3_CFG)
+
+/** \brief 94, CRC Check Register */
+#define FCE0_IN3_CHECK /*lint --e(923)*/ (*(volatile Ifx_FCE_IN3_CHECK*)0xF0003F94u)
+
+/** Alias (User Manual Name) for FCE0_IN3_CHECK.
+* To use register names with standard convension, please use FCE0_IN3_CHECK.
+*/
+#define FCE_CHECK3 (FCE0_IN3_CHECK)
+
+/** \brief 98, CRC Register */
+#define FCE0_IN3_CRC /*lint --e(923)*/ (*(volatile Ifx_FCE_IN3_CRC*)0xF0003F98u)
+
+/** Alias (User Manual Name) for FCE0_IN3_CRC.
+* To use register names with standard convension, please use FCE0_IN3_CRC.
+*/
+#define FCE_CRC3 (FCE0_IN3_CRC)
+
+/** \brief 9C, CRC Test Register */
+#define FCE0_IN3_CTR /*lint --e(923)*/ (*(volatile Ifx_FCE_CTR*)0xF0003F9Cu)
+
+/** Alias (User Manual Name) for FCE0_IN3_CTR.
+* To use register names with standard convension, please use FCE0_IN3_CTR.
+*/
+#define FCE_CTR3 (FCE0_IN3_CTR)
+
+/** \brief 80, Input Register */
+#define FCE0_IN3_IR /*lint --e(923)*/ (*(volatile Ifx_FCE_IN3_IR*)0xF0003F80u)
+
+/** Alias (User Manual Name) for FCE0_IN3_IR.
+* To use register names with standard convension, please use FCE0_IN3_IR.
+*/
+#define FCE_IR3 (FCE0_IN3_IR)
+
+/** \brief 90, CRC Length Register */
+#define FCE0_IN3_LENGTH /*lint --e(923)*/ (*(volatile Ifx_FCE_LENGTH*)0xF0003F90u)
+
+/** Alias (User Manual Name) for FCE0_IN3_LENGTH.
+* To use register names with standard convension, please use FCE0_IN3_LENGTH.
+*/
+#define FCE_LENGTH3 (FCE0_IN3_LENGTH)
+
+/** \brief 84, CRC Result Register */
+#define FCE0_IN3_RES /*lint --e(923)*/ (*(volatile Ifx_FCE_IN3_RES*)0xF0003F84u)
+
+/** Alias (User Manual Name) for FCE0_IN3_RES.
+* To use register names with standard convension, please use FCE0_IN3_RES.
+*/
+#define FCE_RES3 (FCE0_IN3_RES)
+
+/** \brief 8C, CRC Status Register */
+#define FCE0_IN3_STS /*lint --e(923)*/ (*(volatile Ifx_FCE_STS*)0xF0003F8Cu)
+
+/** Alias (User Manual Name) for FCE0_IN3_STS.
+* To use register names with standard convension, please use FCE0_IN3_STS.
+*/
+#define FCE_STS3 (FCE0_IN3_STS)
+
+/** \brief F4, Kernel Reset Register 0 */
+#define FCE0_KRST0 /*lint --e(923)*/ (*(volatile Ifx_FCE_KRST0*)0xF0003FF4u)
+
+/** Alias (User Manual Name) for FCE0_KRST0.
+* To use register names with standard convension, please use FCE0_KRST0.
+*/
+#define FCE_KRST0 (FCE0_KRST0)
+
+/** \brief F0, Kernel Reset Register 1 */
+#define FCE0_KRST1 /*lint --e(923)*/ (*(volatile Ifx_FCE_KRST1*)0xF0003FF0u)
+
+/** Alias (User Manual Name) for FCE0_KRST1.
+* To use register names with standard convension, please use FCE0_KRST1.
+*/
+#define FCE_KRST1 (FCE0_KRST1)
+
+/** \brief EC, Kernel Reset Status Clear Register */
+#define FCE0_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_FCE_KRSTCLR*)0xF0003FECu)
+
+/** Alias (User Manual Name) for FCE0_KRSTCLR.
+* To use register names with standard convension, please use FCE0_KRSTCLR.
+*/
+#define FCE_KRSTCLR (FCE0_KRSTCLR)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXFCE_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxFce_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxFce_regdef.h
new file mode 100644
index 0000000..8992d98
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxFce_regdef.h
@@ -0,0 +1,585 @@
+/**
+ * \file IfxFce_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Fce Fce
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Fce_Bitfields Bitfields
+ * \ingroup IfxLld_Fce
+ *
+ * \defgroup IfxLld_Fce_union Union
+ * \ingroup IfxLld_Fce
+ *
+ * \defgroup IfxLld_Fce_struct Struct
+ * \ingroup IfxLld_Fce
+ *
+ */
+#ifndef IFXFCE_REGDEF_H
+#define IFXFCE_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Fce_Bitfields
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef struct _Ifx_FCE_ACCEN0_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_FCE_ACCEN0_Bits;
+
+/** \brief Access Enable Register 1 */
+typedef struct _Ifx_FCE_ACCEN1_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_FCE_ACCEN1_Bits;
+
+/** \brief CRC Configuration Register */
+typedef struct _Ifx_FCE_CFG_Bits
+{
+ unsigned int CMI:1; /**< \brief [0:0] CRC Mismatch Interrupt (rw) */
+ unsigned int CEI:1; /**< \brief [1:1] Configuration Error Interrupt (rw) */
+ unsigned int LEI:1; /**< \brief [2:2] Length Error Interrupt (rw) */
+ unsigned int BEI:1; /**< \brief [3:3] Bus Error Interrupt (rw) */
+ unsigned int CCE:1; /**< \brief [4:4] CRC Check Comparison (rw) */
+ unsigned int ALR:1; /**< \brief [5:5] Automatic Length Reload (rw) */
+ unsigned int reserved_6:2; /**< \brief \internal Reserved */
+ unsigned int REFIN:1; /**< \brief [8:8] IR Byte Wise Reflection (rw) */
+ unsigned int REFOUT:1; /**< \brief [9:9] CRC 32-Bit Wise Reflection (rw) */
+ unsigned int XSEL:1; /**< \brief [10:10] Selects the value to be xored with the final CRC (rw) */
+ unsigned int reserved_11:21; /**< \brief \internal Reserved */
+} Ifx_FCE_CFG_Bits;
+
+/** \brief Clock Control Register */
+typedef struct _Ifx_FCE_CLC_Bits
+{
+ unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
+ unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_FCE_CLC_Bits;
+
+/** \brief CRC Test Register */
+typedef struct _Ifx_FCE_CTR_Bits
+{
+ unsigned int FCM:1; /**< \brief [0:0] Force CRC Mismatch (rw) */
+ unsigned int FRM_CFG:1; /**< \brief [1:1] Force CFG Register Mismatch (rw) */
+ unsigned int FRM_CHECK:1; /**< \brief [2:2] Force Check Register Mismatch (rw) */
+ unsigned int reserved_3:29; /**< \brief \internal Reserved */
+} Ifx_FCE_CTR_Bits;
+
+/** \brief Module Identification Register */
+typedef struct _Ifx_FCE_ID_Bits
+{
+ unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
+ unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_FCE_ID_Bits;
+
+/** \brief CRC Check Register */
+typedef struct _Ifx_FCE_IN0_CHECK_Bits
+{
+ unsigned int CHECK:32; /**< \brief [31:0] CHECK Register (rw) */
+} Ifx_FCE_IN0_CHECK_Bits;
+
+/** \brief CRC Register */
+typedef struct _Ifx_FCE_IN0_CRC_Bits
+{
+ unsigned int CRC:32; /**< \brief [31:0] CRC Register (rwh) */
+} Ifx_FCE_IN0_CRC_Bits;
+
+/** \brief Input Register */
+typedef struct _Ifx_FCE_IN0_IR_Bits
+{
+ unsigned int IR:32; /**< \brief [31:0] Input Register (rw) */
+} Ifx_FCE_IN0_IR_Bits;
+
+/** \brief CRC Result Register */
+typedef struct _Ifx_FCE_IN0_RES_Bits
+{
+ unsigned int RES:32; /**< \brief [31:0] Result Register (rh) */
+} Ifx_FCE_IN0_RES_Bits;
+
+/** \brief CRC Check Register */
+typedef struct _Ifx_FCE_IN1_CHECK_Bits
+{
+ unsigned int CHECK:32; /**< \brief [31:0] CHECK Register (rw) */
+} Ifx_FCE_IN1_CHECK_Bits;
+
+/** \brief CRC Register */
+typedef struct _Ifx_FCE_IN1_CRC_Bits
+{
+ unsigned int CRC:32; /**< \brief [31:0] CRC Register (rwh) */
+} Ifx_FCE_IN1_CRC_Bits;
+
+/** \brief Input Register */
+typedef struct _Ifx_FCE_IN1_IR_Bits
+{
+ unsigned int IR:32; /**< \brief [31:0] Input Register (rw) */
+} Ifx_FCE_IN1_IR_Bits;
+
+/** \brief CRC Result Register */
+typedef struct _Ifx_FCE_IN1_RES_Bits
+{
+ unsigned int RES:32; /**< \brief [31:0] Result Register (rh) */
+} Ifx_FCE_IN1_RES_Bits;
+
+/** \brief CRC Check Register */
+typedef struct _Ifx_FCE_IN2_CHECK_Bits
+{
+ unsigned int CHECK:16; /**< \brief [15:0] CHECK Register (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_FCE_IN2_CHECK_Bits;
+
+/** \brief CRC Register */
+typedef struct _Ifx_FCE_IN2_CRC_Bits
+{
+ unsigned int CRC:16; /**< \brief [15:0] CRC Register (rwh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_FCE_IN2_CRC_Bits;
+
+/** \brief Input Register */
+typedef struct _Ifx_FCE_IN2_IR_Bits
+{
+ unsigned int IR:16; /**< \brief [15:0] Input Register (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_FCE_IN2_IR_Bits;
+
+/** \brief CRC Result Register */
+typedef struct _Ifx_FCE_IN2_RES_Bits
+{
+ unsigned int RES:16; /**< \brief [15:0] Result Register (rh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_FCE_IN2_RES_Bits;
+
+/** \brief CRC Check Register */
+typedef struct _Ifx_FCE_IN3_CHECK_Bits
+{
+ unsigned int CHECK:8; /**< \brief [7:0] CHECK Register (rw) */
+ unsigned int reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_FCE_IN3_CHECK_Bits;
+
+/** \brief CRC Register */
+typedef struct _Ifx_FCE_IN3_CRC_Bits
+{
+ unsigned int CRC:8; /**< \brief [7:0] CRC Register (rwh) */
+ unsigned int reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_FCE_IN3_CRC_Bits;
+
+/** \brief Input Register */
+typedef struct _Ifx_FCE_IN3_IR_Bits
+{
+ unsigned int IR:8; /**< \brief [7:0] Input Register (rw) */
+ unsigned int reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_FCE_IN3_IR_Bits;
+
+/** \brief CRC Result Register */
+typedef struct _Ifx_FCE_IN3_RES_Bits
+{
+ unsigned int RES:8; /**< \brief [7:0] Result Register (rh) */
+ unsigned int reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_FCE_IN3_RES_Bits;
+
+/** \brief Kernel Reset Register 0 */
+typedef struct _Ifx_FCE_KRST0_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rw) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_FCE_KRST0_Bits;
+
+/** \brief Kernel Reset Register 1 */
+typedef struct _Ifx_FCE_KRST1_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_FCE_KRST1_Bits;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef struct _Ifx_FCE_KRSTCLR_Bits
+{
+ unsigned int CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_FCE_KRSTCLR_Bits;
+
+/** \brief CRC Length Register */
+typedef struct _Ifx_FCE_LENGTH_Bits
+{
+ unsigned int LENGTH:16; /**< \brief [15:0] Message Length Register (rwh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_FCE_LENGTH_Bits;
+
+/** \brief CRC Status Register */
+typedef struct _Ifx_FCE_STS_Bits
+{
+ unsigned int CMF:1; /**< \brief [0:0] CRC Mismatch Flag (rwh) */
+ unsigned int CEF:1; /**< \brief [1:1] Configuration Error Flag (rwh) */
+ unsigned int LEF:1; /**< \brief [2:2] Length Error Flag (rwh) */
+ unsigned int BEF:1; /**< \brief [3:3] Bus Error Flag (rwh) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_FCE_STS_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Fce_union
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FCE_ACCEN0_Bits B; /**< \brief Bitfield access */
+} Ifx_FCE_ACCEN0;
+
+/** \brief Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FCE_ACCEN1_Bits B; /**< \brief Bitfield access */
+} Ifx_FCE_ACCEN1;
+
+/** \brief CRC Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FCE_CFG_Bits B; /**< \brief Bitfield access */
+} Ifx_FCE_CFG;
+
+/** \brief Clock Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FCE_CLC_Bits B; /**< \brief Bitfield access */
+} Ifx_FCE_CLC;
+
+/** \brief CRC Test Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FCE_CTR_Bits B; /**< \brief Bitfield access */
+} Ifx_FCE_CTR;
+
+/** \brief Module Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FCE_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_FCE_ID;
+
+/** \brief CRC Check Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FCE_IN0_CHECK_Bits B; /**< \brief Bitfield access */
+} Ifx_FCE_IN0_CHECK;
+
+/** \brief CRC Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FCE_IN0_CRC_Bits B; /**< \brief Bitfield access */
+} Ifx_FCE_IN0_CRC;
+
+/** \brief Input Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FCE_IN0_IR_Bits B; /**< \brief Bitfield access */
+} Ifx_FCE_IN0_IR;
+
+/** \brief CRC Result Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FCE_IN0_RES_Bits B; /**< \brief Bitfield access */
+} Ifx_FCE_IN0_RES;
+
+/** \brief CRC Check Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FCE_IN1_CHECK_Bits B; /**< \brief Bitfield access */
+} Ifx_FCE_IN1_CHECK;
+
+/** \brief CRC Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FCE_IN1_CRC_Bits B; /**< \brief Bitfield access */
+} Ifx_FCE_IN1_CRC;
+
+/** \brief Input Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FCE_IN1_IR_Bits B; /**< \brief Bitfield access */
+} Ifx_FCE_IN1_IR;
+
+/** \brief CRC Result Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FCE_IN1_RES_Bits B; /**< \brief Bitfield access */
+} Ifx_FCE_IN1_RES;
+
+/** \brief CRC Check Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FCE_IN2_CHECK_Bits B; /**< \brief Bitfield access */
+} Ifx_FCE_IN2_CHECK;
+
+/** \brief CRC Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FCE_IN2_CRC_Bits B; /**< \brief Bitfield access */
+} Ifx_FCE_IN2_CRC;
+
+/** \brief Input Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FCE_IN2_IR_Bits B; /**< \brief Bitfield access */
+} Ifx_FCE_IN2_IR;
+
+/** \brief CRC Result Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FCE_IN2_RES_Bits B; /**< \brief Bitfield access */
+} Ifx_FCE_IN2_RES;
+
+/** \brief CRC Check Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FCE_IN3_CHECK_Bits B; /**< \brief Bitfield access */
+} Ifx_FCE_IN3_CHECK;
+
+/** \brief CRC Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FCE_IN3_CRC_Bits B; /**< \brief Bitfield access */
+} Ifx_FCE_IN3_CRC;
+
+/** \brief Input Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FCE_IN3_IR_Bits B; /**< \brief Bitfield access */
+} Ifx_FCE_IN3_IR;
+
+/** \brief CRC Result Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FCE_IN3_RES_Bits B; /**< \brief Bitfield access */
+} Ifx_FCE_IN3_RES;
+
+/** \brief Kernel Reset Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FCE_KRST0_Bits B; /**< \brief Bitfield access */
+} Ifx_FCE_KRST0;
+
+/** \brief Kernel Reset Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FCE_KRST1_Bits B; /**< \brief Bitfield access */
+} Ifx_FCE_KRST1;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FCE_KRSTCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_FCE_KRSTCLR;
+
+/** \brief CRC Length Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FCE_LENGTH_Bits B; /**< \brief Bitfield access */
+} Ifx_FCE_LENGTH;
+
+/** \brief CRC Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FCE_STS_Bits B; /**< \brief Bitfield access */
+} Ifx_FCE_STS;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Fce_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L1
+ * \{ */
+
+/** \brief Input */
+typedef volatile struct _Ifx_FCE_IN0
+{
+ Ifx_FCE_IN0_IR IR; /**< \brief 0, Input Register */
+ Ifx_FCE_IN0_RES RES; /**< \brief 4, CRC Result Register */
+ Ifx_FCE_CFG CFG; /**< \brief 8, CRC Configuration Register */
+ Ifx_FCE_STS STS; /**< \brief C, CRC Status Register */
+ Ifx_FCE_LENGTH LENGTH; /**< \brief 10, CRC Length Register */
+ Ifx_FCE_IN0_CHECK CHECK; /**< \brief 14, CRC Check Register */
+ Ifx_FCE_IN0_CRC CRC; /**< \brief 18, CRC Register */
+ Ifx_FCE_CTR CTR; /**< \brief 1C, CRC Test Register */
+} Ifx_FCE_IN0;
+
+/** \brief Input */
+typedef volatile struct _Ifx_FCE_IN1
+{
+ Ifx_FCE_IN1_IR IR; /**< \brief 0, Input Register */
+ Ifx_FCE_IN1_RES RES; /**< \brief 4, CRC Result Register */
+ Ifx_FCE_CFG CFG; /**< \brief 8, CRC Configuration Register */
+ Ifx_FCE_STS STS; /**< \brief C, CRC Status Register */
+ Ifx_FCE_LENGTH LENGTH; /**< \brief 10, CRC Length Register */
+ Ifx_FCE_IN1_CHECK CHECK; /**< \brief 14, CRC Check Register */
+ Ifx_FCE_IN1_CRC CRC; /**< \brief 18, CRC Register */
+ Ifx_FCE_CTR CTR; /**< \brief 1C, CRC Test Register */
+} Ifx_FCE_IN1;
+
+/** \brief Input */
+typedef volatile struct _Ifx_FCE_IN2
+{
+ Ifx_FCE_IN2_IR IR; /**< \brief 0, Input Register */
+ Ifx_FCE_IN2_RES RES; /**< \brief 4, CRC Result Register */
+ Ifx_FCE_CFG CFG; /**< \brief 8, CRC Configuration Register */
+ Ifx_FCE_STS STS; /**< \brief C, CRC Status Register */
+ Ifx_FCE_LENGTH LENGTH; /**< \brief 10, CRC Length Register */
+ Ifx_FCE_IN2_CHECK CHECK; /**< \brief 14, CRC Check Register */
+ Ifx_FCE_IN2_CRC CRC; /**< \brief 18, CRC Register */
+ Ifx_FCE_CTR CTR; /**< \brief 1C, CRC Test Register */
+} Ifx_FCE_IN2;
+
+/** \brief Input */
+typedef volatile struct _Ifx_FCE_IN3
+{
+ Ifx_FCE_IN3_IR IR; /**< \brief 0, Input Register */
+ Ifx_FCE_IN3_RES RES; /**< \brief 4, CRC Result Register */
+ Ifx_FCE_CFG CFG; /**< \brief 8, CRC Configuration Register */
+ Ifx_FCE_STS STS; /**< \brief C, CRC Status Register */
+ Ifx_FCE_LENGTH LENGTH; /**< \brief 10, CRC Length Register */
+ Ifx_FCE_IN3_CHECK CHECK; /**< \brief 14, CRC Check Register */
+ Ifx_FCE_IN3_CRC CRC; /**< \brief 18, CRC Register */
+ Ifx_FCE_CTR CTR; /**< \brief 1C, CRC Test Register */
+} Ifx_FCE_IN3;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Fce_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief FCE object */
+typedef volatile struct _Ifx_FCE
+{
+ Ifx_FCE_CLC CLC; /**< \brief 0, Clock Control Register */
+ unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
+ Ifx_FCE_ID ID; /**< \brief 8, Module Identification Register */
+ unsigned char reserved_C[20]; /**< \brief C, \internal Reserved */
+ Ifx_FCE_IN0 IN0; /**< \brief 20, Input */
+ Ifx_FCE_IN1 IN1; /**< \brief 40, Input */
+ Ifx_FCE_IN2 IN2; /**< \brief 60, Input */
+ Ifx_FCE_IN3 IN3; /**< \brief 80, Input */
+ unsigned char reserved_A0[76]; /**< \brief A0, \internal Reserved */
+ Ifx_FCE_KRSTCLR KRSTCLR; /**< \brief EC, Kernel Reset Status Clear Register */
+ Ifx_FCE_KRST1 KRST1; /**< \brief F0, Kernel Reset Register 1 */
+ Ifx_FCE_KRST0 KRST0; /**< \brief F4, Kernel Reset Register 0 */
+ Ifx_FCE_ACCEN1 ACCEN1; /**< \brief F8, Access Enable Register 1 */
+ Ifx_FCE_ACCEN0 ACCEN0; /**< \brief FC, Access Enable Register 0 */
+} Ifx_FCE;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXFCE_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxFft_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxFft_bf.h
new file mode 100644
index 0000000..1275871
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxFft_bf.h
@@ -0,0 +1,360 @@
+/**
+ * \file IfxFft_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Fft_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Fft
+ *
+ */
+#ifndef IFXFFT_BF_H
+#define IFXFFT_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Fft_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_FFT_CLC_Bits.DISR */
+#define IFX_FFT_CLC_DISR_LEN (1u)
+
+/** \brief Mask for Ifx_FFT_CLC_Bits.DISR */
+#define IFX_FFT_CLC_DISR_MSK (0x1u)
+
+/** \brief Offset for Ifx_FFT_CLC_Bits.DISR */
+#define IFX_FFT_CLC_DISR_OFF (0u)
+
+/** \brief Length for Ifx_FFT_CLC_Bits.DISS */
+#define IFX_FFT_CLC_DISS_LEN (1u)
+
+/** \brief Mask for Ifx_FFT_CLC_Bits.DISS */
+#define IFX_FFT_CLC_DISS_MSK (0x1u)
+
+/** \brief Offset for Ifx_FFT_CLC_Bits.DISS */
+#define IFX_FFT_CLC_DISS_OFF (1u)
+
+/** \brief Length for Ifx_FFT_CSR_Bits.BUSY */
+#define IFX_FFT_CSR_BUSY_LEN (1u)
+
+/** \brief Mask for Ifx_FFT_CSR_Bits.BUSY */
+#define IFX_FFT_CSR_BUSY_MSK (0x1u)
+
+/** \brief Offset for Ifx_FFT_CSR_Bits.BUSY */
+#define IFX_FFT_CSR_BUSY_OFF (19u)
+
+/** \brief Length for Ifx_FFT_CSR_Bits.IFFT */
+#define IFX_FFT_CSR_IFFT_LEN (1u)
+
+/** \brief Mask for Ifx_FFT_CSR_Bits.IFFT */
+#define IFX_FFT_CSR_IFFT_MSK (0x1u)
+
+/** \brief Offset for Ifx_FFT_CSR_Bits.IFFT */
+#define IFX_FFT_CSR_IFFT_OFF (12u)
+
+/** \brief Length for Ifx_FFT_CSR_Bits.IN_FMT */
+#define IFX_FFT_CSR_IN_FMT_LEN (2u)
+
+/** \brief Mask for Ifx_FFT_CSR_Bits.IN_FMT */
+#define IFX_FFT_CSR_IN_FMT_MSK (0x3u)
+
+/** \brief Offset for Ifx_FFT_CSR_Bits.IN_FMT */
+#define IFX_FFT_CSR_IN_FMT_OFF (16u)
+
+/** \brief Length for Ifx_FFT_CSR_Bits.LENGTH */
+#define IFX_FFT_CSR_LENGTH_LEN (4u)
+
+/** \brief Mask for Ifx_FFT_CSR_Bits.LENGTH */
+#define IFX_FFT_CSR_LENGTH_MSK (0xfu)
+
+/** \brief Offset for Ifx_FFT_CSR_Bits.LENGTH */
+#define IFX_FFT_CSR_LENGTH_OFF (8u)
+
+/** \brief Length for Ifx_FFT_CSR_Bits.OUT_FMT */
+#define IFX_FFT_CSR_OUT_FMT_LEN (1u)
+
+/** \brief Mask for Ifx_FFT_CSR_Bits.OUT_FMT */
+#define IFX_FFT_CSR_OUT_FMT_MSK (0x1u)
+
+/** \brief Offset for Ifx_FFT_CSR_Bits.OUT_FMT */
+#define IFX_FFT_CSR_OUT_FMT_OFF (18u)
+
+/** \brief Length for Ifx_FFT_CSR_Bits.RFS */
+#define IFX_FFT_CSR_RFS_LEN (1u)
+
+/** \brief Mask for Ifx_FFT_CSR_Bits.RFS */
+#define IFX_FFT_CSR_RFS_MSK (0x1u)
+
+/** \brief Offset for Ifx_FFT_CSR_Bits.RFS */
+#define IFX_FFT_CSR_RFS_OFF (20u)
+
+/** \brief Length for Ifx_FFT_CSR_Bits.START */
+#define IFX_FFT_CSR_START_LEN (1u)
+
+/** \brief Mask for Ifx_FFT_CSR_Bits.START */
+#define IFX_FFT_CSR_START_MSK (0x1u)
+
+/** \brief Offset for Ifx_FFT_CSR_Bits.START */
+#define IFX_FFT_CSR_START_OFF (0u)
+
+/** \brief Length for Ifx_FFT_CSR_Bits.WIN_BYP */
+#define IFX_FFT_CSR_WIN_BYP_LEN (1u)
+
+/** \brief Mask for Ifx_FFT_CSR_Bits.WIN_BYP */
+#define IFX_FFT_CSR_WIN_BYP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FFT_CSR_Bits.WIN_BYP */
+#define IFX_FFT_CSR_WIN_BYP_OFF (13u)
+
+/** \brief Length for Ifx_FFT_HISTORY0_Bits.BUSY */
+#define IFX_FFT_HISTORY0_BUSY_LEN (1u)
+
+/** \brief Mask for Ifx_FFT_HISTORY0_Bits.BUSY */
+#define IFX_FFT_HISTORY0_BUSY_MSK (0x1u)
+
+/** \brief Offset for Ifx_FFT_HISTORY0_Bits.BUSY */
+#define IFX_FFT_HISTORY0_BUSY_OFF (19u)
+
+/** \brief Length for Ifx_FFT_HISTORY0_Bits.IFFT */
+#define IFX_FFT_HISTORY0_IFFT_LEN (1u)
+
+/** \brief Mask for Ifx_FFT_HISTORY0_Bits.IFFT */
+#define IFX_FFT_HISTORY0_IFFT_MSK (0x1u)
+
+/** \brief Offset for Ifx_FFT_HISTORY0_Bits.IFFT */
+#define IFX_FFT_HISTORY0_IFFT_OFF (12u)
+
+/** \brief Length for Ifx_FFT_HISTORY0_Bits.IN_FMT */
+#define IFX_FFT_HISTORY0_IN_FMT_LEN (2u)
+
+/** \brief Mask for Ifx_FFT_HISTORY0_Bits.IN_FMT */
+#define IFX_FFT_HISTORY0_IN_FMT_MSK (0x3u)
+
+/** \brief Offset for Ifx_FFT_HISTORY0_Bits.IN_FMT */
+#define IFX_FFT_HISTORY0_IN_FMT_OFF (16u)
+
+/** \brief Length for Ifx_FFT_HISTORY0_Bits.LENGTH */
+#define IFX_FFT_HISTORY0_LENGTH_LEN (4u)
+
+/** \brief Mask for Ifx_FFT_HISTORY0_Bits.LENGTH */
+#define IFX_FFT_HISTORY0_LENGTH_MSK (0xfu)
+
+/** \brief Offset for Ifx_FFT_HISTORY0_Bits.LENGTH */
+#define IFX_FFT_HISTORY0_LENGTH_OFF (8u)
+
+/** \brief Length for Ifx_FFT_HISTORY0_Bits.OUT_FMT */
+#define IFX_FFT_HISTORY0_OUT_FMT_LEN (1u)
+
+/** \brief Mask for Ifx_FFT_HISTORY0_Bits.OUT_FMT */
+#define IFX_FFT_HISTORY0_OUT_FMT_MSK (0x1u)
+
+/** \brief Offset for Ifx_FFT_HISTORY0_Bits.OUT_FMT */
+#define IFX_FFT_HISTORY0_OUT_FMT_OFF (18u)
+
+/** \brief Length for Ifx_FFT_HISTORY0_Bits.RFS */
+#define IFX_FFT_HISTORY0_RFS_LEN (1u)
+
+/** \brief Mask for Ifx_FFT_HISTORY0_Bits.RFS */
+#define IFX_FFT_HISTORY0_RFS_MSK (0x1u)
+
+/** \brief Offset for Ifx_FFT_HISTORY0_Bits.RFS */
+#define IFX_FFT_HISTORY0_RFS_OFF (20u)
+
+/** \brief Length for Ifx_FFT_HISTORY0_Bits.WIN_BYP */
+#define IFX_FFT_HISTORY0_WIN_BYP_LEN (1u)
+
+/** \brief Mask for Ifx_FFT_HISTORY0_Bits.WIN_BYP */
+#define IFX_FFT_HISTORY0_WIN_BYP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FFT_HISTORY0_Bits.WIN_BYP */
+#define IFX_FFT_HISTORY0_WIN_BYP_OFF (13u)
+
+/** \brief Length for Ifx_FFT_HISTORY1_Bits.BUSY */
+#define IFX_FFT_HISTORY1_BUSY_LEN (1u)
+
+/** \brief Mask for Ifx_FFT_HISTORY1_Bits.BUSY */
+#define IFX_FFT_HISTORY1_BUSY_MSK (0x1u)
+
+/** \brief Offset for Ifx_FFT_HISTORY1_Bits.BUSY */
+#define IFX_FFT_HISTORY1_BUSY_OFF (19u)
+
+/** \brief Length for Ifx_FFT_HISTORY1_Bits.IFFT */
+#define IFX_FFT_HISTORY1_IFFT_LEN (1u)
+
+/** \brief Mask for Ifx_FFT_HISTORY1_Bits.IFFT */
+#define IFX_FFT_HISTORY1_IFFT_MSK (0x1u)
+
+/** \brief Offset for Ifx_FFT_HISTORY1_Bits.IFFT */
+#define IFX_FFT_HISTORY1_IFFT_OFF (12u)
+
+/** \brief Length for Ifx_FFT_HISTORY1_Bits.IN_FMT */
+#define IFX_FFT_HISTORY1_IN_FMT_LEN (2u)
+
+/** \brief Mask for Ifx_FFT_HISTORY1_Bits.IN_FMT */
+#define IFX_FFT_HISTORY1_IN_FMT_MSK (0x3u)
+
+/** \brief Offset for Ifx_FFT_HISTORY1_Bits.IN_FMT */
+#define IFX_FFT_HISTORY1_IN_FMT_OFF (16u)
+
+/** \brief Length for Ifx_FFT_HISTORY1_Bits.LENGTH */
+#define IFX_FFT_HISTORY1_LENGTH_LEN (4u)
+
+/** \brief Mask for Ifx_FFT_HISTORY1_Bits.LENGTH */
+#define IFX_FFT_HISTORY1_LENGTH_MSK (0xfu)
+
+/** \brief Offset for Ifx_FFT_HISTORY1_Bits.LENGTH */
+#define IFX_FFT_HISTORY1_LENGTH_OFF (8u)
+
+/** \brief Length for Ifx_FFT_HISTORY1_Bits.OUT_FMT */
+#define IFX_FFT_HISTORY1_OUT_FMT_LEN (1u)
+
+/** \brief Mask for Ifx_FFT_HISTORY1_Bits.OUT_FMT */
+#define IFX_FFT_HISTORY1_OUT_FMT_MSK (0x1u)
+
+/** \brief Offset for Ifx_FFT_HISTORY1_Bits.OUT_FMT */
+#define IFX_FFT_HISTORY1_OUT_FMT_OFF (18u)
+
+/** \brief Length for Ifx_FFT_HISTORY1_Bits.RFS */
+#define IFX_FFT_HISTORY1_RFS_LEN (1u)
+
+/** \brief Mask for Ifx_FFT_HISTORY1_Bits.RFS */
+#define IFX_FFT_HISTORY1_RFS_MSK (0x1u)
+
+/** \brief Offset for Ifx_FFT_HISTORY1_Bits.RFS */
+#define IFX_FFT_HISTORY1_RFS_OFF (20u)
+
+/** \brief Length for Ifx_FFT_HISTORY1_Bits.WIN_BYP */
+#define IFX_FFT_HISTORY1_WIN_BYP_LEN (1u)
+
+/** \brief Mask for Ifx_FFT_HISTORY1_Bits.WIN_BYP */
+#define IFX_FFT_HISTORY1_WIN_BYP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FFT_HISTORY1_Bits.WIN_BYP */
+#define IFX_FFT_HISTORY1_WIN_BYP_OFF (13u)
+
+/** \brief Length for Ifx_FFT_ID_Bits.MODNUMBER */
+#define IFX_FFT_ID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_FFT_ID_Bits.MODNUMBER */
+#define IFX_FFT_ID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_FFT_ID_Bits.MODNUMBER */
+#define IFX_FFT_ID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_FFT_ID_Bits.MODREV */
+#define IFX_FFT_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_FFT_ID_Bits.MODREV */
+#define IFX_FFT_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_FFT_ID_Bits.MODREV */
+#define IFX_FFT_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_FFT_ID_Bits.MODTYPE */
+#define IFX_FFT_ID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_FFT_ID_Bits.MODTYPE */
+#define IFX_FFT_ID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_FFT_ID_Bits.MODTYPE */
+#define IFX_FFT_ID_MODTYPE_OFF (8u)
+
+/** \brief Length for Ifx_FFT_KRST0_Bits.RST */
+#define IFX_FFT_KRST0_RST_LEN (1u)
+
+/** \brief Mask for Ifx_FFT_KRST0_Bits.RST */
+#define IFX_FFT_KRST0_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_FFT_KRST0_Bits.RST */
+#define IFX_FFT_KRST0_RST_OFF (0u)
+
+/** \brief Length for Ifx_FFT_KRST0_Bits.RSTSTAT */
+#define IFX_FFT_KRST0_RSTSTAT_LEN (1u)
+
+/** \brief Mask for Ifx_FFT_KRST0_Bits.RSTSTAT */
+#define IFX_FFT_KRST0_RSTSTAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_FFT_KRST0_Bits.RSTSTAT */
+#define IFX_FFT_KRST0_RSTSTAT_OFF (1u)
+
+/** \brief Length for Ifx_FFT_KRST1_Bits.RST */
+#define IFX_FFT_KRST1_RST_LEN (1u)
+
+/** \brief Mask for Ifx_FFT_KRST1_Bits.RST */
+#define IFX_FFT_KRST1_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_FFT_KRST1_Bits.RST */
+#define IFX_FFT_KRST1_RST_OFF (0u)
+
+/** \brief Length for Ifx_FFT_KRSTCLR_Bits.CLR */
+#define IFX_FFT_KRSTCLR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_FFT_KRSTCLR_Bits.CLR */
+#define IFX_FFT_KRSTCLR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_FFT_KRSTCLR_Bits.CLR */
+#define IFX_FFT_KRSTCLR_CLR_OFF (0u)
+
+/** \brief Length for Ifx_FFT_OCS_Bits.SUS */
+#define IFX_FFT_OCS_SUS_LEN (4u)
+
+/** \brief Mask for Ifx_FFT_OCS_Bits.SUS */
+#define IFX_FFT_OCS_SUS_MSK (0xfu)
+
+/** \brief Offset for Ifx_FFT_OCS_Bits.SUS */
+#define IFX_FFT_OCS_SUS_OFF (24u)
+
+/** \brief Length for Ifx_FFT_OCS_Bits.SUS_P */
+#define IFX_FFT_OCS_SUS_P_LEN (1u)
+
+/** \brief Mask for Ifx_FFT_OCS_Bits.SUS_P */
+#define IFX_FFT_OCS_SUS_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_FFT_OCS_Bits.SUS_P */
+#define IFX_FFT_OCS_SUS_P_OFF (28u)
+
+/** \brief Length for Ifx_FFT_OCS_Bits.SUSSTA */
+#define IFX_FFT_OCS_SUSSTA_LEN (1u)
+
+/** \brief Mask for Ifx_FFT_OCS_Bits.SUSSTA */
+#define IFX_FFT_OCS_SUSSTA_MSK (0x1u)
+
+/** \brief Offset for Ifx_FFT_OCS_Bits.SUSSTA */
+#define IFX_FFT_OCS_SUSSTA_OFF (29u)
+
+/** \brief Length for Ifx_FFT_ODA_Bits.DDREN */
+#define IFX_FFT_ODA_DDREN_LEN (1u)
+
+/** \brief Mask for Ifx_FFT_ODA_Bits.DDREN */
+#define IFX_FFT_ODA_DDREN_MSK (0x1u)
+
+/** \brief Offset for Ifx_FFT_ODA_Bits.DDREN */
+#define IFX_FFT_ODA_DDREN_OFF (0u)
+
+/** \brief Length for Ifx_FFT_ODA_Bits.DRDIS */
+#define IFX_FFT_ODA_DRDIS_LEN (1u)
+
+/** \brief Mask for Ifx_FFT_ODA_Bits.DRDIS */
+#define IFX_FFT_ODA_DRDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_FFT_ODA_Bits.DRDIS */
+#define IFX_FFT_ODA_DRDIS_OFF (1u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXFFT_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxFft_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxFft_reg.h
new file mode 100644
index 0000000..9890bf6
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxFft_reg.h
@@ -0,0 +1,81 @@
+/**
+ * \file IfxFft_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Fft_Cfg Fft address
+ * \ingroup IfxLld_Fft
+ *
+ * \defgroup IfxLld_Fft_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Fft_Cfg
+ *
+ * \defgroup IfxLld_Fft_Cfg_Fft 2-FFT
+ * \ingroup IfxLld_Fft_Cfg
+ *
+ */
+#ifndef IFXFFT_REG_H
+#define IFXFFT_REG_H 1
+/******************************************************************************/
+#include "IfxFft_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Fft_Cfg_BaseAddress
+ * \{ */
+
+/** \brief FFT object */
+#define MODULE_FFT /*lint --e(923)*/ (*(Ifx_FFT*)0xF8700C00u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Fft_Cfg_Fft
+ * \{ */
+
+/** \brief 0, FFT Clock Control Register */
+#define FFT_CLC /*lint --e(923)*/ (*(volatile Ifx_FFT_CLC*)0xF8700C00u)
+
+/** \brief 40, FFT Control and Status Register */
+#define FFT_CSR /*lint --e(923)*/ (*(volatile Ifx_FFT_CSR*)0xF8700C40u)
+
+/** \brief 60, FFT History0 Register */
+#define FFT_HISTORY0 /*lint --e(923)*/ (*(volatile Ifx_FFT_HISTORY0*)0xF8700C60u)
+
+/** \brief 70, FFT History1 Register */
+#define FFT_HISTORY1 /*lint --e(923)*/ (*(volatile Ifx_FFT_HISTORY1*)0xF8700C70u)
+
+/** \brief 8, FFT Identification Register */
+#define FFT_ID /*lint --e(923)*/ (*(volatile Ifx_FFT_ID*)0xF8700C08u)
+
+/** \brief F4, FFT Kernel Reset Register 0 */
+#define FFT_KRST0 /*lint --e(923)*/ (*(volatile Ifx_FFT_KRST0*)0xF8700CF4u)
+
+/** \brief F0, FFT Kernel Reset Register 1 */
+#define FFT_KRST1 /*lint --e(923)*/ (*(volatile Ifx_FFT_KRST1*)0xF8700CF0u)
+
+/** \brief EC, FFT Kernel Reset Status Clear Register */
+#define FFT_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_FFT_KRSTCLR*)0xF8700CECu)
+
+/** \brief E8, FFT OCDS Control and Status */
+#define FFT_OCS /*lint --e(923)*/ (*(volatile Ifx_FFT_OCS*)0xF8700CE8u)
+
+/** \brief E4, FFT OCDS Debug Access Register */
+#define FFT_ODA /*lint --e(923)*/ (*(volatile Ifx_FFT_ODA*)0xF8700CE4u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXFFT_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxFft_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxFft_regdef.h
new file mode 100644
index 0000000..46fadfc
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxFft_regdef.h
@@ -0,0 +1,264 @@
+/**
+ * \file IfxFft_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Fft Fft
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Fft_Bitfields Bitfields
+ * \ingroup IfxLld_Fft
+ *
+ * \defgroup IfxLld_Fft_union Union
+ * \ingroup IfxLld_Fft
+ *
+ * \defgroup IfxLld_Fft_struct Struct
+ * \ingroup IfxLld_Fft
+ *
+ */
+#ifndef IFXFFT_REGDEF_H
+#define IFXFFT_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Fft_Bitfields
+ * \{ */
+
+/** \brief FFT Clock Control Register */
+typedef struct _Ifx_FFT_CLC_Bits
+{
+ Ifx_Strict_32Bit DISR:1; /**< \brief [0:0] FFT Disable Request Bit (rw) */
+ Ifx_Strict_32Bit DISS:1; /**< \brief [1:1] FFT Disable Status Bit (rh) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_FFT_CLC_Bits;
+
+/** \brief FFT Control and Status Register */
+typedef struct _Ifx_FFT_CSR_Bits
+{
+ Ifx_Strict_32Bit START:1; /**< \brief [0:0] Start Transform (rwh) */
+ Ifx_Strict_32Bit reserved_1:7; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit LENGTH:4; /**< \brief [11:8] Length of Transform (rw) */
+ Ifx_Strict_32Bit IFFT:1; /**< \brief [12:12] Inverse FFT (rw) */
+ Ifx_Strict_32Bit WIN_BYP:1; /**< \brief [13:13] Window Bypass (rw) */
+ Ifx_Strict_32Bit reserved_14:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit IN_FMT:2; /**< \brief [17:16] Input Format (rw) */
+ Ifx_Strict_32Bit OUT_FMT:1; /**< \brief [18:18] Output Format (rw) */
+ Ifx_Strict_32Bit BUSY:1; /**< \brief [19:19] FFT Engine Busy (rh) */
+ Ifx_Strict_32Bit RFS:1; /**< \brief [20:20] Ready For Start (rh) */
+ Ifx_Strict_32Bit reserved_21:11; /**< \brief \internal Reserved */
+} Ifx_FFT_CSR_Bits;
+
+/** \brief FFT History0 Register */
+typedef struct _Ifx_FFT_HISTORY0_Bits
+{
+ Ifx_Strict_32Bit reserved_0:8; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit LENGTH:4; /**< \brief [11:8] Length of Transform (rh) */
+ Ifx_Strict_32Bit IFFT:1; /**< \brief [12:12] Inverse FFT (rh) */
+ Ifx_Strict_32Bit WIN_BYP:1; /**< \brief [13:13] Window Bypass (rh) */
+ Ifx_Strict_32Bit reserved_14:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit IN_FMT:2; /**< \brief [17:16] Input Format (rh) */
+ Ifx_Strict_32Bit OUT_FMT:1; /**< \brief [18:18] Output Format (rh) */
+ Ifx_Strict_32Bit BUSY:1; /**< \brief [19:19] FFT Engine Busy (rh) */
+ Ifx_Strict_32Bit RFS:1; /**< \brief [20:20] Ready For Start (rh) */
+ Ifx_Strict_32Bit reserved_21:11; /**< \brief \internal Reserved */
+} Ifx_FFT_HISTORY0_Bits;
+
+/** \brief FFT History1 Register */
+typedef struct _Ifx_FFT_HISTORY1_Bits
+{
+ Ifx_Strict_32Bit reserved_0:8; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit LENGTH:4; /**< \brief [11:8] Length of Transform (rh) */
+ Ifx_Strict_32Bit IFFT:1; /**< \brief [12:12] Inverse FFT (rh) */
+ Ifx_Strict_32Bit WIN_BYP:1; /**< \brief [13:13] Window Bypass (rh) */
+ Ifx_Strict_32Bit reserved_14:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit IN_FMT:2; /**< \brief [17:16] Input Format (rh) */
+ Ifx_Strict_32Bit OUT_FMT:1; /**< \brief [18:18] Output Format (rh) */
+ Ifx_Strict_32Bit BUSY:1; /**< \brief [19:19] FFT Engine Busy (rh) */
+ Ifx_Strict_32Bit RFS:1; /**< \brief [20:20] Ready For Start (rh) */
+ Ifx_Strict_32Bit reserved_21:11; /**< \brief \internal Reserved */
+} Ifx_FFT_HISTORY1_Bits;
+
+/** \brief FFT Identification Register */
+typedef struct _Ifx_FFT_ID_Bits
+{
+ Ifx_Strict_32Bit MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ Ifx_Strict_32Bit MODTYPE:8; /**< \brief [15:8] Module Type (r) */
+ Ifx_Strict_32Bit MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_FFT_ID_Bits;
+
+/** \brief FFT Kernel Reset Register 0 */
+typedef struct _Ifx_FFT_KRST0_Bits
+{
+ Ifx_Strict_32Bit RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ Ifx_Strict_32Bit RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rh) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_FFT_KRST0_Bits;
+
+/** \brief FFT Kernel Reset Register 1 */
+typedef struct _Ifx_FFT_KRST1_Bits
+{
+ Ifx_Strict_32Bit RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ Ifx_Strict_32Bit reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_FFT_KRST1_Bits;
+
+/** \brief FFT Kernel Reset Status Clear Register */
+typedef struct _Ifx_FFT_KRSTCLR_Bits
+{
+ Ifx_Strict_32Bit CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
+ Ifx_Strict_32Bit reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_FFT_KRSTCLR_Bits;
+
+/** \brief FFT OCDS Control and Status */
+typedef struct _Ifx_FFT_OCS_Bits
+{
+ Ifx_Strict_32Bit reserved_0:24; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SUS:4; /**< \brief [27:24] OCDS Suspend Control (rw) */
+ Ifx_Strict_32Bit SUS_P:1; /**< \brief [28:28] SUS Write Protection (w) */
+ Ifx_Strict_32Bit SUSSTA:1; /**< \brief [29:29] Suspend State (rh) */
+ Ifx_Strict_32Bit reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_FFT_OCS_Bits;
+
+/** \brief FFT OCDS Debug Access Register */
+typedef struct _Ifx_FFT_ODA_Bits
+{
+ Ifx_Strict_32Bit DDREN:1; /**< \brief [0:0] Destructive Debug Read Enable (rw) */
+ Ifx_Strict_32Bit DRDIS:1; /**< \brief [1:1] Destructive Read Disable (rw) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_FFT_ODA_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Fft_union
+ * \{ */
+
+/** \brief FFT Clock Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FFT_CLC_Bits B; /**< \brief Bitfield access */
+} Ifx_FFT_CLC;
+
+/** \brief FFT Control and Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FFT_CSR_Bits B; /**< \brief Bitfield access */
+} Ifx_FFT_CSR;
+
+/** \brief FFT History0 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FFT_HISTORY0_Bits B; /**< \brief Bitfield access */
+} Ifx_FFT_HISTORY0;
+
+/** \brief FFT History1 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FFT_HISTORY1_Bits B; /**< \brief Bitfield access */
+} Ifx_FFT_HISTORY1;
+
+/** \brief FFT Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FFT_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_FFT_ID;
+
+/** \brief FFT Kernel Reset Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FFT_KRST0_Bits B; /**< \brief Bitfield access */
+} Ifx_FFT_KRST0;
+
+/** \brief FFT Kernel Reset Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FFT_KRST1_Bits B; /**< \brief Bitfield access */
+} Ifx_FFT_KRST1;
+
+/** \brief FFT Kernel Reset Status Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FFT_KRSTCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_FFT_KRSTCLR;
+
+/** \brief FFT OCDS Control and Status */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FFT_OCS_Bits B; /**< \brief Bitfield access */
+} Ifx_FFT_OCS;
+
+/** \brief FFT OCDS Debug Access Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FFT_ODA_Bits B; /**< \brief Bitfield access */
+} Ifx_FFT_ODA;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Fft_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief FFT object */
+typedef volatile struct _Ifx_FFT
+{
+ Ifx_FFT_CLC CLC; /**< \brief 0, FFT Clock Control Register */
+ unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
+ Ifx_FFT_ID ID; /**< \brief 8, FFT Identification Register */
+ unsigned char reserved_C[52]; /**< \brief C, \internal Reserved */
+ Ifx_FFT_CSR CSR; /**< \brief 40, FFT Control and Status Register */
+ unsigned char reserved_44[28]; /**< \brief 44, \internal Reserved */
+ Ifx_FFT_HISTORY0 HISTORY0; /**< \brief 60, FFT History0 Register */
+ unsigned char reserved_64[12]; /**< \brief 64, \internal Reserved */
+ Ifx_FFT_HISTORY1 HISTORY1; /**< \brief 70, FFT History1 Register */
+ unsigned char reserved_74[112]; /**< \brief 74, \internal Reserved */
+ Ifx_FFT_ODA ODA; /**< \brief E4, FFT OCDS Debug Access Register */
+ Ifx_FFT_OCS OCS; /**< \brief E8, FFT OCDS Control and Status */
+ Ifx_FFT_KRSTCLR KRSTCLR; /**< \brief EC, FFT Kernel Reset Status Clear Register */
+ Ifx_FFT_KRST1 KRST1; /**< \brief F0, FFT Kernel Reset Register 1 */
+ Ifx_FFT_KRST0 KRST0; /**< \brief F4, FFT Kernel Reset Register 0 */
+ unsigned char reserved_F8[8]; /**< \brief F8, \internal Reserved */
+} Ifx_FFT;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXFFT_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxFlash_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxFlash_bf.h
new file mode 100644
index 0000000..7e8ec25
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxFlash_bf.h
@@ -0,0 +1,2538 @@
+/**
+ * \file IfxFlash_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Flash_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Flash
+ *
+ */
+#ifndef IFXFLASH_BF_H
+#define IFXFLASH_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Flash_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN0 */
+#define IFX_FLASH_ACCEN0_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN0 */
+#define IFX_FLASH_ACCEN0_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN0 */
+#define IFX_FLASH_ACCEN0_EN0_OFF (0u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN10 */
+#define IFX_FLASH_ACCEN0_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN10 */
+#define IFX_FLASH_ACCEN0_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN10 */
+#define IFX_FLASH_ACCEN0_EN10_OFF (10u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN11 */
+#define IFX_FLASH_ACCEN0_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN11 */
+#define IFX_FLASH_ACCEN0_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN11 */
+#define IFX_FLASH_ACCEN0_EN11_OFF (11u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN12 */
+#define IFX_FLASH_ACCEN0_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN12 */
+#define IFX_FLASH_ACCEN0_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN12 */
+#define IFX_FLASH_ACCEN0_EN12_OFF (12u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN13 */
+#define IFX_FLASH_ACCEN0_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN13 */
+#define IFX_FLASH_ACCEN0_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN13 */
+#define IFX_FLASH_ACCEN0_EN13_OFF (13u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN14 */
+#define IFX_FLASH_ACCEN0_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN14 */
+#define IFX_FLASH_ACCEN0_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN14 */
+#define IFX_FLASH_ACCEN0_EN14_OFF (14u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN15 */
+#define IFX_FLASH_ACCEN0_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN15 */
+#define IFX_FLASH_ACCEN0_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN15 */
+#define IFX_FLASH_ACCEN0_EN15_OFF (15u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN16 */
+#define IFX_FLASH_ACCEN0_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN16 */
+#define IFX_FLASH_ACCEN0_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN16 */
+#define IFX_FLASH_ACCEN0_EN16_OFF (16u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN17 */
+#define IFX_FLASH_ACCEN0_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN17 */
+#define IFX_FLASH_ACCEN0_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN17 */
+#define IFX_FLASH_ACCEN0_EN17_OFF (17u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN18 */
+#define IFX_FLASH_ACCEN0_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN18 */
+#define IFX_FLASH_ACCEN0_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN18 */
+#define IFX_FLASH_ACCEN0_EN18_OFF (18u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN19 */
+#define IFX_FLASH_ACCEN0_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN19 */
+#define IFX_FLASH_ACCEN0_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN19 */
+#define IFX_FLASH_ACCEN0_EN19_OFF (19u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN1 */
+#define IFX_FLASH_ACCEN0_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN1 */
+#define IFX_FLASH_ACCEN0_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN1 */
+#define IFX_FLASH_ACCEN0_EN1_OFF (1u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN20 */
+#define IFX_FLASH_ACCEN0_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN20 */
+#define IFX_FLASH_ACCEN0_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN20 */
+#define IFX_FLASH_ACCEN0_EN20_OFF (20u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN21 */
+#define IFX_FLASH_ACCEN0_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN21 */
+#define IFX_FLASH_ACCEN0_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN21 */
+#define IFX_FLASH_ACCEN0_EN21_OFF (21u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN22 */
+#define IFX_FLASH_ACCEN0_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN22 */
+#define IFX_FLASH_ACCEN0_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN22 */
+#define IFX_FLASH_ACCEN0_EN22_OFF (22u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN23 */
+#define IFX_FLASH_ACCEN0_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN23 */
+#define IFX_FLASH_ACCEN0_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN23 */
+#define IFX_FLASH_ACCEN0_EN23_OFF (23u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN24 */
+#define IFX_FLASH_ACCEN0_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN24 */
+#define IFX_FLASH_ACCEN0_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN24 */
+#define IFX_FLASH_ACCEN0_EN24_OFF (24u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN25 */
+#define IFX_FLASH_ACCEN0_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN25 */
+#define IFX_FLASH_ACCEN0_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN25 */
+#define IFX_FLASH_ACCEN0_EN25_OFF (25u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN26 */
+#define IFX_FLASH_ACCEN0_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN26 */
+#define IFX_FLASH_ACCEN0_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN26 */
+#define IFX_FLASH_ACCEN0_EN26_OFF (26u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN27 */
+#define IFX_FLASH_ACCEN0_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN27 */
+#define IFX_FLASH_ACCEN0_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN27 */
+#define IFX_FLASH_ACCEN0_EN27_OFF (27u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN28 */
+#define IFX_FLASH_ACCEN0_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN28 */
+#define IFX_FLASH_ACCEN0_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN28 */
+#define IFX_FLASH_ACCEN0_EN28_OFF (28u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN29 */
+#define IFX_FLASH_ACCEN0_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN29 */
+#define IFX_FLASH_ACCEN0_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN29 */
+#define IFX_FLASH_ACCEN0_EN29_OFF (29u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN2 */
+#define IFX_FLASH_ACCEN0_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN2 */
+#define IFX_FLASH_ACCEN0_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN2 */
+#define IFX_FLASH_ACCEN0_EN2_OFF (2u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN30 */
+#define IFX_FLASH_ACCEN0_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN30 */
+#define IFX_FLASH_ACCEN0_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN30 */
+#define IFX_FLASH_ACCEN0_EN30_OFF (30u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN31 */
+#define IFX_FLASH_ACCEN0_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN31 */
+#define IFX_FLASH_ACCEN0_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN31 */
+#define IFX_FLASH_ACCEN0_EN31_OFF (31u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN3 */
+#define IFX_FLASH_ACCEN0_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN3 */
+#define IFX_FLASH_ACCEN0_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN3 */
+#define IFX_FLASH_ACCEN0_EN3_OFF (3u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN4 */
+#define IFX_FLASH_ACCEN0_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN4 */
+#define IFX_FLASH_ACCEN0_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN4 */
+#define IFX_FLASH_ACCEN0_EN4_OFF (4u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN5 */
+#define IFX_FLASH_ACCEN0_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN5 */
+#define IFX_FLASH_ACCEN0_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN5 */
+#define IFX_FLASH_ACCEN0_EN5_OFF (5u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN6 */
+#define IFX_FLASH_ACCEN0_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN6 */
+#define IFX_FLASH_ACCEN0_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN6 */
+#define IFX_FLASH_ACCEN0_EN6_OFF (6u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN7 */
+#define IFX_FLASH_ACCEN0_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN7 */
+#define IFX_FLASH_ACCEN0_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN7 */
+#define IFX_FLASH_ACCEN0_EN7_OFF (7u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN8 */
+#define IFX_FLASH_ACCEN0_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN8 */
+#define IFX_FLASH_ACCEN0_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN8 */
+#define IFX_FLASH_ACCEN0_EN8_OFF (8u)
+
+/** \brief Length for Ifx_FLASH_ACCEN0_Bits.EN9 */
+#define IFX_FLASH_ACCEN0_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ACCEN0_Bits.EN9 */
+#define IFX_FLASH_ACCEN0_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ACCEN0_Bits.EN9 */
+#define IFX_FLASH_ACCEN0_EN9_OFF (9u)
+
+/** \brief Length for Ifx_FLASH_CBAB_CFG_Bits.CLR */
+#define IFX_FLASH_CBAB_CFG_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_CBAB_CFG_Bits.CLR */
+#define IFX_FLASH_CBAB_CFG_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_CBAB_CFG_Bits.CLR */
+#define IFX_FLASH_CBAB_CFG_CLR_OFF (8u)
+
+/** \brief Length for Ifx_FLASH_CBAB_CFG_Bits.DIS */
+#define IFX_FLASH_CBAB_CFG_DIS_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_CBAB_CFG_Bits.DIS */
+#define IFX_FLASH_CBAB_CFG_DIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_CBAB_CFG_Bits.DIS */
+#define IFX_FLASH_CBAB_CFG_DIS_OFF (9u)
+
+/** \brief Length for Ifx_FLASH_CBAB_CFG_Bits.SEL */
+#define IFX_FLASH_CBAB_CFG_SEL_LEN (6u)
+
+/** \brief Mask for Ifx_FLASH_CBAB_CFG_Bits.SEL */
+#define IFX_FLASH_CBAB_CFG_SEL_MSK (0x3fu)
+
+/** \brief Offset for Ifx_FLASH_CBAB_CFG_Bits.SEL */
+#define IFX_FLASH_CBAB_CFG_SEL_OFF (0u)
+
+/** \brief Length for Ifx_FLASH_CBAB_STAT_Bits.VLD0 */
+#define IFX_FLASH_CBAB_STAT_VLD0_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_CBAB_STAT_Bits.VLD0 */
+#define IFX_FLASH_CBAB_STAT_VLD0_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_CBAB_STAT_Bits.VLD0 */
+#define IFX_FLASH_CBAB_STAT_VLD0_OFF (0u)
+
+/** \brief Length for Ifx_FLASH_CBAB_STAT_Bits.VLD1 */
+#define IFX_FLASH_CBAB_STAT_VLD1_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_CBAB_STAT_Bits.VLD1 */
+#define IFX_FLASH_CBAB_STAT_VLD1_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_CBAB_STAT_Bits.VLD1 */
+#define IFX_FLASH_CBAB_STAT_VLD1_OFF (1u)
+
+/** \brief Length for Ifx_FLASH_CBAB_STAT_Bits.VLD2 */
+#define IFX_FLASH_CBAB_STAT_VLD2_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_CBAB_STAT_Bits.VLD2 */
+#define IFX_FLASH_CBAB_STAT_VLD2_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_CBAB_STAT_Bits.VLD2 */
+#define IFX_FLASH_CBAB_STAT_VLD2_OFF (2u)
+
+/** \brief Length for Ifx_FLASH_CBAB_STAT_Bits.VLD3 */
+#define IFX_FLASH_CBAB_STAT_VLD3_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_CBAB_STAT_Bits.VLD3 */
+#define IFX_FLASH_CBAB_STAT_VLD3_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_CBAB_STAT_Bits.VLD3 */
+#define IFX_FLASH_CBAB_STAT_VLD3_OFF (3u)
+
+/** \brief Length for Ifx_FLASH_CBAB_STAT_Bits.VLD4 */
+#define IFX_FLASH_CBAB_STAT_VLD4_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_CBAB_STAT_Bits.VLD4 */
+#define IFX_FLASH_CBAB_STAT_VLD4_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_CBAB_STAT_Bits.VLD4 */
+#define IFX_FLASH_CBAB_STAT_VLD4_OFF (4u)
+
+/** \brief Length for Ifx_FLASH_CBAB_STAT_Bits.VLD5 */
+#define IFX_FLASH_CBAB_STAT_VLD5_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_CBAB_STAT_Bits.VLD5 */
+#define IFX_FLASH_CBAB_STAT_VLD5_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_CBAB_STAT_Bits.VLD5 */
+#define IFX_FLASH_CBAB_STAT_VLD5_OFF (5u)
+
+/** \brief Length for Ifx_FLASH_CBAB_STAT_Bits.VLD6 */
+#define IFX_FLASH_CBAB_STAT_VLD6_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_CBAB_STAT_Bits.VLD6 */
+#define IFX_FLASH_CBAB_STAT_VLD6_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_CBAB_STAT_Bits.VLD6 */
+#define IFX_FLASH_CBAB_STAT_VLD6_OFF (6u)
+
+/** \brief Length for Ifx_FLASH_CBAB_STAT_Bits.VLD7 */
+#define IFX_FLASH_CBAB_STAT_VLD7_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_CBAB_STAT_Bits.VLD7 */
+#define IFX_FLASH_CBAB_STAT_VLD7_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_CBAB_STAT_Bits.VLD7 */
+#define IFX_FLASH_CBAB_STAT_VLD7_OFF (7u)
+
+/** \brief Length for Ifx_FLASH_CBAB_STAT_Bits.VLD8 */
+#define IFX_FLASH_CBAB_STAT_VLD8_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_CBAB_STAT_Bits.VLD8 */
+#define IFX_FLASH_CBAB_STAT_VLD8_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_CBAB_STAT_Bits.VLD8 */
+#define IFX_FLASH_CBAB_STAT_VLD8_OFF (8u)
+
+/** \brief Length for Ifx_FLASH_CBAB_STAT_Bits.VLD9 */
+#define IFX_FLASH_CBAB_STAT_VLD9_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_CBAB_STAT_Bits.VLD9 */
+#define IFX_FLASH_CBAB_STAT_VLD9_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_CBAB_STAT_Bits.VLD9 */
+#define IFX_FLASH_CBAB_STAT_VLD9_OFF (9u)
+
+/** \brief Length for Ifx_FLASH_CBAB_TOP_Bits.ADDR */
+#define IFX_FLASH_CBAB_TOP_ADDR_LEN (19u)
+
+/** \brief Mask for Ifx_FLASH_CBAB_TOP_Bits.ADDR */
+#define IFX_FLASH_CBAB_TOP_ADDR_MSK (0x7ffffu)
+
+/** \brief Offset for Ifx_FLASH_CBAB_TOP_Bits.ADDR */
+#define IFX_FLASH_CBAB_TOP_ADDR_OFF (5u)
+
+/** \brief Length for Ifx_FLASH_CBAB_TOP_Bits.CLR */
+#define IFX_FLASH_CBAB_TOP_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_CBAB_TOP_Bits.CLR */
+#define IFX_FLASH_CBAB_TOP_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_CBAB_TOP_Bits.CLR */
+#define IFX_FLASH_CBAB_TOP_CLR_OFF (31u)
+
+/** \brief Length for Ifx_FLASH_CBAB_TOP_Bits.ERR */
+#define IFX_FLASH_CBAB_TOP_ERR_LEN (6u)
+
+/** \brief Mask for Ifx_FLASH_CBAB_TOP_Bits.ERR */
+#define IFX_FLASH_CBAB_TOP_ERR_MSK (0x3fu)
+
+/** \brief Offset for Ifx_FLASH_CBAB_TOP_Bits.ERR */
+#define IFX_FLASH_CBAB_TOP_ERR_OFF (24u)
+
+/** \brief Length for Ifx_FLASH_CBAB_TOP_Bits.VLD */
+#define IFX_FLASH_CBAB_TOP_VLD_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_CBAB_TOP_Bits.VLD */
+#define IFX_FLASH_CBAB_TOP_VLD_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_CBAB_TOP_Bits.VLD */
+#define IFX_FLASH_CBAB_TOP_VLD_OFF (30u)
+
+/** \brief Length for Ifx_FLASH_COMM0_Bits.STATUS */
+#define IFX_FLASH_COMM0_STATUS_LEN (8u)
+
+/** \brief Mask for Ifx_FLASH_COMM0_Bits.STATUS */
+#define IFX_FLASH_COMM0_STATUS_MSK (0xffu)
+
+/** \brief Offset for Ifx_FLASH_COMM0_Bits.STATUS */
+#define IFX_FLASH_COMM0_STATUS_OFF (0u)
+
+/** \brief Length for Ifx_FLASH_COMM1_Bits.DATA */
+#define IFX_FLASH_COMM1_DATA_LEN (8u)
+
+/** \brief Mask for Ifx_FLASH_COMM1_Bits.DATA */
+#define IFX_FLASH_COMM1_DATA_MSK (0xffu)
+
+/** \brief Offset for Ifx_FLASH_COMM1_Bits.DATA */
+#define IFX_FLASH_COMM1_DATA_OFF (8u)
+
+/** \brief Length for Ifx_FLASH_COMM1_Bits.STATUS */
+#define IFX_FLASH_COMM1_STATUS_LEN (8u)
+
+/** \brief Mask for Ifx_FLASH_COMM1_Bits.STATUS */
+#define IFX_FLASH_COMM1_STATUS_MSK (0xffu)
+
+/** \brief Offset for Ifx_FLASH_COMM1_Bits.STATUS */
+#define IFX_FLASH_COMM1_STATUS_OFF (0u)
+
+/** \brief Length for Ifx_FLASH_COMM2_Bits.DATA */
+#define IFX_FLASH_COMM2_DATA_LEN (8u)
+
+/** \brief Mask for Ifx_FLASH_COMM2_Bits.DATA */
+#define IFX_FLASH_COMM2_DATA_MSK (0xffu)
+
+/** \brief Offset for Ifx_FLASH_COMM2_Bits.DATA */
+#define IFX_FLASH_COMM2_DATA_OFF (8u)
+
+/** \brief Length for Ifx_FLASH_COMM2_Bits.STATUS */
+#define IFX_FLASH_COMM2_STATUS_LEN (8u)
+
+/** \brief Mask for Ifx_FLASH_COMM2_Bits.STATUS */
+#define IFX_FLASH_COMM2_STATUS_MSK (0xffu)
+
+/** \brief Offset for Ifx_FLASH_COMM2_Bits.STATUS */
+#define IFX_FLASH_COMM2_STATUS_OFF (0u)
+
+/** \brief Length for Ifx_FLASH_ECCRD_Bits.ECCORDIS */
+#define IFX_FLASH_ECCRD_ECCORDIS_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ECCRD_Bits.ECCORDIS */
+#define IFX_FLASH_ECCRD_ECCORDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ECCRD_Bits.ECCORDIS */
+#define IFX_FLASH_ECCRD_ECCORDIS_OFF (31u)
+
+/** \brief Length for Ifx_FLASH_ECCRD_Bits.EDCERRINJ */
+#define IFX_FLASH_ECCRD_EDCERRINJ_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ECCRD_Bits.EDCERRINJ */
+#define IFX_FLASH_ECCRD_EDCERRINJ_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ECCRD_Bits.EDCERRINJ */
+#define IFX_FLASH_ECCRD_EDCERRINJ_OFF (30u)
+
+/** \brief Length for Ifx_FLASH_ECCRD_Bits.RCODE */
+#define IFX_FLASH_ECCRD_RCODE_LEN (22u)
+
+/** \brief Mask for Ifx_FLASH_ECCRD_Bits.RCODE */
+#define IFX_FLASH_ECCRD_RCODE_MSK (0x3fffffu)
+
+/** \brief Offset for Ifx_FLASH_ECCRD_Bits.RCODE */
+#define IFX_FLASH_ECCRD_RCODE_OFF (0u)
+
+/** \brief Length for Ifx_FLASH_ECCRP_Bits.ECCORDIS */
+#define IFX_FLASH_ECCRP_ECCORDIS_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ECCRP_Bits.ECCORDIS */
+#define IFX_FLASH_ECCRP_ECCORDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ECCRP_Bits.ECCORDIS */
+#define IFX_FLASH_ECCRP_ECCORDIS_OFF (31u)
+
+/** \brief Length for Ifx_FLASH_ECCRP_Bits.EDCERRINJ */
+#define IFX_FLASH_ECCRP_EDCERRINJ_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ECCRP_Bits.EDCERRINJ */
+#define IFX_FLASH_ECCRP_EDCERRINJ_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ECCRP_Bits.EDCERRINJ */
+#define IFX_FLASH_ECCRP_EDCERRINJ_OFF (30u)
+
+/** \brief Length for Ifx_FLASH_ECCRP_Bits.RCODE */
+#define IFX_FLASH_ECCRP_RCODE_LEN (22u)
+
+/** \brief Mask for Ifx_FLASH_ECCRP_Bits.RCODE */
+#define IFX_FLASH_ECCRP_RCODE_MSK (0x3fffffu)
+
+/** \brief Offset for Ifx_FLASH_ECCRP_Bits.RCODE */
+#define IFX_FLASH_ECCRP_RCODE_OFF (0u)
+
+/** \brief Length for Ifx_FLASH_ECCW_Bits.DECENCDIS */
+#define IFX_FLASH_ECCW_DECENCDIS_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ECCW_Bits.DECENCDIS */
+#define IFX_FLASH_ECCW_DECENCDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ECCW_Bits.DECENCDIS */
+#define IFX_FLASH_ECCW_DECENCDIS_OFF (30u)
+
+/** \brief Length for Ifx_FLASH_ECCW_Bits.PECENCDIS */
+#define IFX_FLASH_ECCW_PECENCDIS_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_ECCW_Bits.PECENCDIS */
+#define IFX_FLASH_ECCW_PECENCDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_ECCW_Bits.PECENCDIS */
+#define IFX_FLASH_ECCW_PECENCDIS_OFF (31u)
+
+/** \brief Length for Ifx_FLASH_ECCW_Bits.WCODE */
+#define IFX_FLASH_ECCW_WCODE_LEN (22u)
+
+/** \brief Mask for Ifx_FLASH_ECCW_Bits.WCODE */
+#define IFX_FLASH_ECCW_WCODE_MSK (0x3fffffu)
+
+/** \brief Offset for Ifx_FLASH_ECCW_Bits.WCODE */
+#define IFX_FLASH_ECCW_WCODE_OFF (0u)
+
+/** \brief Length for Ifx_FLASH_FCON_Bits.EOBM */
+#define IFX_FLASH_FCON_EOBM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FCON_Bits.EOBM */
+#define IFX_FLASH_FCON_EOBM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FCON_Bits.EOBM */
+#define IFX_FLASH_FCON_EOBM_OFF (31u)
+
+/** \brief Length for Ifx_FLASH_FCON_Bits.ESLDIS */
+#define IFX_FLASH_FCON_ESLDIS_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FCON_Bits.ESLDIS */
+#define IFX_FLASH_FCON_ESLDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FCON_Bits.ESLDIS */
+#define IFX_FLASH_FCON_ESLDIS_OFF (16u)
+
+/** \brief Length for Ifx_FLASH_FCON_Bits.IDLE */
+#define IFX_FLASH_FCON_IDLE_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FCON_Bits.IDLE */
+#define IFX_FLASH_FCON_IDLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FCON_Bits.IDLE */
+#define IFX_FLASH_FCON_IDLE_OFF (15u)
+
+/** \brief Length for Ifx_FLASH_FCON_Bits.NSAFECC */
+#define IFX_FLASH_FCON_NSAFECC_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FCON_Bits.NSAFECC */
+#define IFX_FLASH_FCON_NSAFECC_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FCON_Bits.NSAFECC */
+#define IFX_FLASH_FCON_NSAFECC_OFF (18u)
+
+/** \brief Length for Ifx_FLASH_FCON_Bits.PR5V */
+#define IFX_FLASH_FCON_PR5V_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FCON_Bits.PR5V */
+#define IFX_FLASH_FCON_PR5V_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FCON_Bits.PR5V */
+#define IFX_FLASH_FCON_PR5V_OFF (30u)
+
+/** \brief Length for Ifx_FLASH_FCON_Bits.PROERM */
+#define IFX_FLASH_FCON_PROERM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FCON_Bits.PROERM */
+#define IFX_FLASH_FCON_PROERM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FCON_Bits.PROERM */
+#define IFX_FLASH_FCON_PROERM_OFF (26u)
+
+/** \brief Length for Ifx_FLASH_FCON_Bits.RES21 */
+#define IFX_FLASH_FCON_RES21_LEN (2u)
+
+/** \brief Mask for Ifx_FLASH_FCON_Bits.RES21 */
+#define IFX_FLASH_FCON_RES21_MSK (0x3u)
+
+/** \brief Offset for Ifx_FLASH_FCON_Bits.RES21 */
+#define IFX_FLASH_FCON_RES21_OFF (20u)
+
+/** \brief Length for Ifx_FLASH_FCON_Bits.RES23 */
+#define IFX_FLASH_FCON_RES23_LEN (2u)
+
+/** \brief Mask for Ifx_FLASH_FCON_Bits.RES23 */
+#define IFX_FLASH_FCON_RES23_MSK (0x3u)
+
+/** \brief Offset for Ifx_FLASH_FCON_Bits.RES23 */
+#define IFX_FLASH_FCON_RES23_OFF (22u)
+
+/** \brief Length for Ifx_FLASH_FCON_Bits.SLEEP */
+#define IFX_FLASH_FCON_SLEEP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FCON_Bits.SLEEP */
+#define IFX_FLASH_FCON_SLEEP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FCON_Bits.SLEEP */
+#define IFX_FLASH_FCON_SLEEP_OFF (17u)
+
+/** \brief Length for Ifx_FLASH_FCON_Bits.SQERM */
+#define IFX_FLASH_FCON_SQERM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FCON_Bits.SQERM */
+#define IFX_FLASH_FCON_SQERM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FCON_Bits.SQERM */
+#define IFX_FLASH_FCON_SQERM_OFF (25u)
+
+/** \brief Length for Ifx_FLASH_FCON_Bits.STALL */
+#define IFX_FLASH_FCON_STALL_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FCON_Bits.STALL */
+#define IFX_FLASH_FCON_STALL_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FCON_Bits.STALL */
+#define IFX_FLASH_FCON_STALL_OFF (19u)
+
+/** \brief Length for Ifx_FLASH_FCON_Bits.VOPERM */
+#define IFX_FLASH_FCON_VOPERM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FCON_Bits.VOPERM */
+#define IFX_FLASH_FCON_VOPERM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FCON_Bits.VOPERM */
+#define IFX_FLASH_FCON_VOPERM_OFF (24u)
+
+/** \brief Length for Ifx_FLASH_FCON_Bits.WSDFLASH */
+#define IFX_FLASH_FCON_WSDFLASH_LEN (6u)
+
+/** \brief Mask for Ifx_FLASH_FCON_Bits.WSDFLASH */
+#define IFX_FLASH_FCON_WSDFLASH_MSK (0x3fu)
+
+/** \brief Offset for Ifx_FLASH_FCON_Bits.WSDFLASH */
+#define IFX_FLASH_FCON_WSDFLASH_OFF (6u)
+
+/** \brief Length for Ifx_FLASH_FCON_Bits.WSECDF */
+#define IFX_FLASH_FCON_WSECDF_LEN (3u)
+
+/** \brief Mask for Ifx_FLASH_FCON_Bits.WSECDF */
+#define IFX_FLASH_FCON_WSECDF_MSK (0x7u)
+
+/** \brief Offset for Ifx_FLASH_FCON_Bits.WSECDF */
+#define IFX_FLASH_FCON_WSECDF_OFF (12u)
+
+/** \brief Length for Ifx_FLASH_FCON_Bits.WSECPF */
+#define IFX_FLASH_FCON_WSECPF_LEN (2u)
+
+/** \brief Mask for Ifx_FLASH_FCON_Bits.WSECPF */
+#define IFX_FLASH_FCON_WSECPF_MSK (0x3u)
+
+/** \brief Offset for Ifx_FLASH_FCON_Bits.WSECPF */
+#define IFX_FLASH_FCON_WSECPF_OFF (4u)
+
+/** \brief Length for Ifx_FLASH_FCON_Bits.WSPFLASH */
+#define IFX_FLASH_FCON_WSPFLASH_LEN (4u)
+
+/** \brief Mask for Ifx_FLASH_FCON_Bits.WSPFLASH */
+#define IFX_FLASH_FCON_WSPFLASH_MSK (0xfu)
+
+/** \brief Offset for Ifx_FLASH_FCON_Bits.WSPFLASH */
+#define IFX_FLASH_FCON_WSPFLASH_OFF (0u)
+
+/** \brief Length for Ifx_FLASH_FPRO_Bits.DCFP */
+#define IFX_FLASH_FPRO_DCFP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FPRO_Bits.DCFP */
+#define IFX_FLASH_FPRO_DCFP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FPRO_Bits.DCFP */
+#define IFX_FLASH_FPRO_DCFP_OFF (16u)
+
+/** \brief Length for Ifx_FLASH_FPRO_Bits.DDFD */
+#define IFX_FLASH_FPRO_DDFD_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FPRO_Bits.DDFD */
+#define IFX_FLASH_FPRO_DDFD_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FPRO_Bits.DDFD */
+#define IFX_FLASH_FPRO_DDFD_OFF (20u)
+
+/** \brief Length for Ifx_FLASH_FPRO_Bits.DDFP */
+#define IFX_FLASH_FPRO_DDFP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FPRO_Bits.DDFP */
+#define IFX_FLASH_FPRO_DDFP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FPRO_Bits.DDFP */
+#define IFX_FLASH_FPRO_DDFP_OFF (17u)
+
+/** \brief Length for Ifx_FLASH_FPRO_Bits.DDFPX */
+#define IFX_FLASH_FPRO_DDFPX_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FPRO_Bits.DDFPX */
+#define IFX_FLASH_FPRO_DDFPX_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FPRO_Bits.DDFPX */
+#define IFX_FLASH_FPRO_DDFPX_OFF (18u)
+
+/** \brief Length for Ifx_FLASH_FPRO_Bits.ENPE */
+#define IFX_FLASH_FPRO_ENPE_LEN (2u)
+
+/** \brief Mask for Ifx_FLASH_FPRO_Bits.ENPE */
+#define IFX_FLASH_FPRO_ENPE_MSK (0x3u)
+
+/** \brief Offset for Ifx_FLASH_FPRO_Bits.ENPE */
+#define IFX_FLASH_FPRO_ENPE_OFF (22u)
+
+/** \brief Length for Ifx_FLASH_FPRO_Bits.PRODISD */
+#define IFX_FLASH_FPRO_PRODISD_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FPRO_Bits.PRODISD */
+#define IFX_FLASH_FPRO_PRODISD_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FPRO_Bits.PRODISD */
+#define IFX_FLASH_FPRO_PRODISD_OFF (3u)
+
+/** \brief Length for Ifx_FLASH_FPRO_Bits.PRODISDBG */
+#define IFX_FLASH_FPRO_PRODISDBG_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FPRO_Bits.PRODISDBG */
+#define IFX_FLASH_FPRO_PRODISDBG_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FPRO_Bits.PRODISDBG */
+#define IFX_FLASH_FPRO_PRODISDBG_OFF (9u)
+
+/** \brief Length for Ifx_FLASH_FPRO_Bits.PRODISP */
+#define IFX_FLASH_FPRO_PRODISP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FPRO_Bits.PRODISP */
+#define IFX_FLASH_FPRO_PRODISP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FPRO_Bits.PRODISP */
+#define IFX_FLASH_FPRO_PRODISP_OFF (1u)
+
+/** \brief Length for Ifx_FLASH_FPRO_Bits.PROIND */
+#define IFX_FLASH_FPRO_PROIND_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FPRO_Bits.PROIND */
+#define IFX_FLASH_FPRO_PROIND_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FPRO_Bits.PROIND */
+#define IFX_FLASH_FPRO_PROIND_OFF (2u)
+
+/** \brief Length for Ifx_FLASH_FPRO_Bits.PROINDBG */
+#define IFX_FLASH_FPRO_PROINDBG_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FPRO_Bits.PROINDBG */
+#define IFX_FLASH_FPRO_PROINDBG_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FPRO_Bits.PROINDBG */
+#define IFX_FLASH_FPRO_PROINDBG_OFF (8u)
+
+/** \brief Length for Ifx_FLASH_FPRO_Bits.PROINHSM */
+#define IFX_FLASH_FPRO_PROINHSM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FPRO_Bits.PROINHSM */
+#define IFX_FLASH_FPRO_PROINHSM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FPRO_Bits.PROINHSM */
+#define IFX_FLASH_FPRO_PROINHSM_OFF (10u)
+
+/** \brief Length for Ifx_FLASH_FPRO_Bits.PROINHSMCOTP */
+#define IFX_FLASH_FPRO_PROINHSMCOTP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FPRO_Bits.PROINHSMCOTP */
+#define IFX_FLASH_FPRO_PROINHSMCOTP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FPRO_Bits.PROINHSMCOTP */
+#define IFX_FLASH_FPRO_PROINHSMCOTP_OFF (4u)
+
+/** \brief Length for Ifx_FLASH_FPRO_Bits.PROINOTP */
+#define IFX_FLASH_FPRO_PROINOTP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FPRO_Bits.PROINOTP */
+#define IFX_FLASH_FPRO_PROINOTP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FPRO_Bits.PROINOTP */
+#define IFX_FLASH_FPRO_PROINOTP_OFF (6u)
+
+/** \brief Length for Ifx_FLASH_FPRO_Bits.PROINP */
+#define IFX_FLASH_FPRO_PROINP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FPRO_Bits.PROINP */
+#define IFX_FLASH_FPRO_PROINP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FPRO_Bits.PROINP */
+#define IFX_FLASH_FPRO_PROINP_OFF (0u)
+
+/** \brief Length for Ifx_FLASH_FPRO_Bits.RES5 */
+#define IFX_FLASH_FPRO_RES5_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FPRO_Bits.RES5 */
+#define IFX_FLASH_FPRO_RES5_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FPRO_Bits.RES5 */
+#define IFX_FLASH_FPRO_RES5_OFF (5u)
+
+/** \brief Length for Ifx_FLASH_FPRO_Bits.RES7 */
+#define IFX_FLASH_FPRO_RES7_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FPRO_Bits.RES7 */
+#define IFX_FLASH_FPRO_RES7_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FPRO_Bits.RES7 */
+#define IFX_FLASH_FPRO_RES7_OFF (7u)
+
+/** \brief Length for Ifx_FLASH_FSR_Bits.D0BUSY */
+#define IFX_FLASH_FSR_D0BUSY_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FSR_Bits.D0BUSY */
+#define IFX_FLASH_FSR_D0BUSY_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FSR_Bits.D0BUSY */
+#define IFX_FLASH_FSR_D0BUSY_OFF (1u)
+
+/** \brief Length for Ifx_FLASH_FSR_Bits.DFDBER */
+#define IFX_FLASH_FSR_DFDBER_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FSR_Bits.DFDBER */
+#define IFX_FLASH_FSR_DFDBER_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FSR_Bits.DFDBER */
+#define IFX_FLASH_FSR_DFDBER_OFF (19u)
+
+/** \brief Length for Ifx_FLASH_FSR_Bits.DFMBER */
+#define IFX_FLASH_FSR_DFMBER_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FSR_Bits.DFMBER */
+#define IFX_FLASH_FSR_DFMBER_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FSR_Bits.DFMBER */
+#define IFX_FLASH_FSR_DFMBER_OFF (21u)
+
+/** \brief Length for Ifx_FLASH_FSR_Bits.DFPAGE */
+#define IFX_FLASH_FSR_DFPAGE_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FSR_Bits.DFPAGE */
+#define IFX_FLASH_FSR_DFPAGE_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FSR_Bits.DFPAGE */
+#define IFX_FLASH_FSR_DFPAGE_OFF (10u)
+
+/** \brief Length for Ifx_FLASH_FSR_Bits.DFSBER */
+#define IFX_FLASH_FSR_DFSBER_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FSR_Bits.DFSBER */
+#define IFX_FLASH_FSR_DFSBER_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FSR_Bits.DFSBER */
+#define IFX_FLASH_FSR_DFSBER_OFF (18u)
+
+/** \brief Length for Ifx_FLASH_FSR_Bits.DFTBER */
+#define IFX_FLASH_FSR_DFTBER_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FSR_Bits.DFTBER */
+#define IFX_FLASH_FSR_DFTBER_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FSR_Bits.DFTBER */
+#define IFX_FLASH_FSR_DFTBER_OFF (20u)
+
+/** \brief Length for Ifx_FLASH_FSR_Bits.ERASE */
+#define IFX_FLASH_FSR_ERASE_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FSR_Bits.ERASE */
+#define IFX_FLASH_FSR_ERASE_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FSR_Bits.ERASE */
+#define IFX_FLASH_FSR_ERASE_OFF (8u)
+
+/** \brief Length for Ifx_FLASH_FSR_Bits.EVER */
+#define IFX_FLASH_FSR_EVER_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FSR_Bits.EVER */
+#define IFX_FLASH_FSR_EVER_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FSR_Bits.EVER */
+#define IFX_FLASH_FSR_EVER_OFF (26u)
+
+/** \brief Length for Ifx_FLASH_FSR_Bits.FABUSY */
+#define IFX_FLASH_FSR_FABUSY_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FSR_Bits.FABUSY */
+#define IFX_FLASH_FSR_FABUSY_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FSR_Bits.FABUSY */
+#define IFX_FLASH_FSR_FABUSY_OFF (0u)
+
+/** \brief Length for Ifx_FLASH_FSR_Bits.OPER */
+#define IFX_FLASH_FSR_OPER_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FSR_Bits.OPER */
+#define IFX_FLASH_FSR_OPER_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FSR_Bits.OPER */
+#define IFX_FLASH_FSR_OPER_OFF (11u)
+
+/** \brief Length for Ifx_FLASH_FSR_Bits.ORIER */
+#define IFX_FLASH_FSR_ORIER_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FSR_Bits.ORIER */
+#define IFX_FLASH_FSR_ORIER_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FSR_Bits.ORIER */
+#define IFX_FLASH_FSR_ORIER_OFF (30u)
+
+/** \brief Length for Ifx_FLASH_FSR_Bits.P0BUSY */
+#define IFX_FLASH_FSR_P0BUSY_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FSR_Bits.P0BUSY */
+#define IFX_FLASH_FSR_P0BUSY_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FSR_Bits.P0BUSY */
+#define IFX_FLASH_FSR_P0BUSY_OFF (3u)
+
+/** \brief Length for Ifx_FLASH_FSR_Bits.P1BUSY */
+#define IFX_FLASH_FSR_P1BUSY_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FSR_Bits.P1BUSY */
+#define IFX_FLASH_FSR_P1BUSY_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FSR_Bits.P1BUSY */
+#define IFX_FLASH_FSR_P1BUSY_OFF (4u)
+
+/** \brief Length for Ifx_FLASH_FSR_Bits.PFDBER */
+#define IFX_FLASH_FSR_PFDBER_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FSR_Bits.PFDBER */
+#define IFX_FLASH_FSR_PFDBER_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FSR_Bits.PFDBER */
+#define IFX_FLASH_FSR_PFDBER_OFF (15u)
+
+/** \brief Length for Ifx_FLASH_FSR_Bits.PFMBER */
+#define IFX_FLASH_FSR_PFMBER_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FSR_Bits.PFMBER */
+#define IFX_FLASH_FSR_PFMBER_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FSR_Bits.PFMBER */
+#define IFX_FLASH_FSR_PFMBER_OFF (16u)
+
+/** \brief Length for Ifx_FLASH_FSR_Bits.PFPAGE */
+#define IFX_FLASH_FSR_PFPAGE_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FSR_Bits.PFPAGE */
+#define IFX_FLASH_FSR_PFPAGE_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FSR_Bits.PFPAGE */
+#define IFX_FLASH_FSR_PFPAGE_OFF (9u)
+
+/** \brief Length for Ifx_FLASH_FSR_Bits.PFSBER */
+#define IFX_FLASH_FSR_PFSBER_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FSR_Bits.PFSBER */
+#define IFX_FLASH_FSR_PFSBER_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FSR_Bits.PFSBER */
+#define IFX_FLASH_FSR_PFSBER_OFF (14u)
+
+/** \brief Length for Ifx_FLASH_FSR_Bits.PROER */
+#define IFX_FLASH_FSR_PROER_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FSR_Bits.PROER */
+#define IFX_FLASH_FSR_PROER_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FSR_Bits.PROER */
+#define IFX_FLASH_FSR_PROER_OFF (13u)
+
+/** \brief Length for Ifx_FLASH_FSR_Bits.PROG */
+#define IFX_FLASH_FSR_PROG_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FSR_Bits.PROG */
+#define IFX_FLASH_FSR_PROG_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FSR_Bits.PROG */
+#define IFX_FLASH_FSR_PROG_OFF (7u)
+
+/** \brief Length for Ifx_FLASH_FSR_Bits.PVER */
+#define IFX_FLASH_FSR_PVER_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FSR_Bits.PVER */
+#define IFX_FLASH_FSR_PVER_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FSR_Bits.PVER */
+#define IFX_FLASH_FSR_PVER_OFF (25u)
+
+/** \brief Length for Ifx_FLASH_FSR_Bits.RES17 */
+#define IFX_FLASH_FSR_RES17_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FSR_Bits.RES17 */
+#define IFX_FLASH_FSR_RES17_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FSR_Bits.RES17 */
+#define IFX_FLASH_FSR_RES17_OFF (17u)
+
+/** \brief Length for Ifx_FLASH_FSR_Bits.RES1 */
+#define IFX_FLASH_FSR_RES1_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FSR_Bits.RES1 */
+#define IFX_FLASH_FSR_RES1_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FSR_Bits.RES1 */
+#define IFX_FLASH_FSR_RES1_OFF (2u)
+
+/** \brief Length for Ifx_FLASH_FSR_Bits.RES5 */
+#define IFX_FLASH_FSR_RES5_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FSR_Bits.RES5 */
+#define IFX_FLASH_FSR_RES5_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FSR_Bits.RES5 */
+#define IFX_FLASH_FSR_RES5_OFF (5u)
+
+/** \brief Length for Ifx_FLASH_FSR_Bits.RES6 */
+#define IFX_FLASH_FSR_RES6_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FSR_Bits.RES6 */
+#define IFX_FLASH_FSR_RES6_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FSR_Bits.RES6 */
+#define IFX_FLASH_FSR_RES6_OFF (6u)
+
+/** \brief Length for Ifx_FLASH_FSR_Bits.SLM */
+#define IFX_FLASH_FSR_SLM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FSR_Bits.SLM */
+#define IFX_FLASH_FSR_SLM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FSR_Bits.SLM */
+#define IFX_FLASH_FSR_SLM_OFF (28u)
+
+/** \brief Length for Ifx_FLASH_FSR_Bits.SPND */
+#define IFX_FLASH_FSR_SPND_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FSR_Bits.SPND */
+#define IFX_FLASH_FSR_SPND_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FSR_Bits.SPND */
+#define IFX_FLASH_FSR_SPND_OFF (27u)
+
+/** \brief Length for Ifx_FLASH_FSR_Bits.SQER */
+#define IFX_FLASH_FSR_SQER_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FSR_Bits.SQER */
+#define IFX_FLASH_FSR_SQER_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FSR_Bits.SQER */
+#define IFX_FLASH_FSR_SQER_OFF (12u)
+
+/** \brief Length for Ifx_FLASH_FSR_Bits.SRIADDERR */
+#define IFX_FLASH_FSR_SRIADDERR_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_FSR_Bits.SRIADDERR */
+#define IFX_FLASH_FSR_SRIADDERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_FSR_Bits.SRIADDERR */
+#define IFX_FLASH_FSR_SRIADDERR_OFF (22u)
+
+/** \brief Length for Ifx_FLASH_ID_Bits.MODNUMBER */
+#define IFX_FLASH_ID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_FLASH_ID_Bits.MODNUMBER */
+#define IFX_FLASH_ID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_FLASH_ID_Bits.MODNUMBER */
+#define IFX_FLASH_ID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_FLASH_ID_Bits.MODREV */
+#define IFX_FLASH_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_FLASH_ID_Bits.MODREV */
+#define IFX_FLASH_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_FLASH_ID_Bits.MODREV */
+#define IFX_FLASH_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_FLASH_ID_Bits.MODTYPE */
+#define IFX_FLASH_ID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_FLASH_ID_Bits.MODTYPE */
+#define IFX_FLASH_ID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_FLASH_ID_Bits.MODTYPE */
+#define IFX_FLASH_ID_MODTYPE_OFF (8u)
+
+/** \brief Length for Ifx_FLASH_MARD_Bits.HMARGIN */
+#define IFX_FLASH_MARD_HMARGIN_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_MARD_Bits.HMARGIN */
+#define IFX_FLASH_MARD_HMARGIN_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_MARD_Bits.HMARGIN */
+#define IFX_FLASH_MARD_HMARGIN_OFF (0u)
+
+/** \brief Length for Ifx_FLASH_MARD_Bits.SELD0 */
+#define IFX_FLASH_MARD_SELD0_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_MARD_Bits.SELD0 */
+#define IFX_FLASH_MARD_SELD0_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_MARD_Bits.SELD0 */
+#define IFX_FLASH_MARD_SELD0_OFF (1u)
+
+/** \brief Length for Ifx_FLASH_MARD_Bits.SPND */
+#define IFX_FLASH_MARD_SPND_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_MARD_Bits.SPND */
+#define IFX_FLASH_MARD_SPND_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_MARD_Bits.SPND */
+#define IFX_FLASH_MARD_SPND_OFF (3u)
+
+/** \brief Length for Ifx_FLASH_MARD_Bits.SPNDERR */
+#define IFX_FLASH_MARD_SPNDERR_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_MARD_Bits.SPNDERR */
+#define IFX_FLASH_MARD_SPNDERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_MARD_Bits.SPNDERR */
+#define IFX_FLASH_MARD_SPNDERR_OFF (4u)
+
+/** \brief Length for Ifx_FLASH_MARD_Bits.TRAPDIS */
+#define IFX_FLASH_MARD_TRAPDIS_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_MARD_Bits.TRAPDIS */
+#define IFX_FLASH_MARD_TRAPDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_MARD_Bits.TRAPDIS */
+#define IFX_FLASH_MARD_TRAPDIS_OFF (15u)
+
+/** \brief Length for Ifx_FLASH_MARP_Bits.RES2 */
+#define IFX_FLASH_MARP_RES2_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_MARP_Bits.RES2 */
+#define IFX_FLASH_MARP_RES2_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_MARP_Bits.RES2 */
+#define IFX_FLASH_MARP_RES2_OFF (2u)
+
+/** \brief Length for Ifx_FLASH_MARP_Bits.RES3 */
+#define IFX_FLASH_MARP_RES3_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_MARP_Bits.RES3 */
+#define IFX_FLASH_MARP_RES3_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_MARP_Bits.RES3 */
+#define IFX_FLASH_MARP_RES3_OFF (3u)
+
+/** \brief Length for Ifx_FLASH_MARP_Bits.SELP0 */
+#define IFX_FLASH_MARP_SELP0_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_MARP_Bits.SELP0 */
+#define IFX_FLASH_MARP_SELP0_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_MARP_Bits.SELP0 */
+#define IFX_FLASH_MARP_SELP0_OFF (0u)
+
+/** \brief Length for Ifx_FLASH_MARP_Bits.SELP1 */
+#define IFX_FLASH_MARP_SELP1_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_MARP_Bits.SELP1 */
+#define IFX_FLASH_MARP_SELP1_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_MARP_Bits.SELP1 */
+#define IFX_FLASH_MARP_SELP1_OFF (1u)
+
+/** \brief Length for Ifx_FLASH_MARP_Bits.TRAPDIS */
+#define IFX_FLASH_MARP_TRAPDIS_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_MARP_Bits.TRAPDIS */
+#define IFX_FLASH_MARP_TRAPDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_MARP_Bits.TRAPDIS */
+#define IFX_FLASH_MARP_TRAPDIS_OFF (15u)
+
+/** \brief Length for Ifx_FLASH_PROCOND_Bits.APREN */
+#define IFX_FLASH_PROCOND_APREN_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCOND_Bits.APREN */
+#define IFX_FLASH_PROCOND_APREN_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCOND_Bits.APREN */
+#define IFX_FLASH_PROCOND_APREN_OFF (11u)
+
+/** \brief Length for Ifx_FLASH_PROCOND_Bits.CAP0EN */
+#define IFX_FLASH_PROCOND_CAP0EN_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCOND_Bits.CAP0EN */
+#define IFX_FLASH_PROCOND_CAP0EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCOND_Bits.CAP0EN */
+#define IFX_FLASH_PROCOND_CAP0EN_OFF (12u)
+
+/** \brief Length for Ifx_FLASH_PROCOND_Bits.CAP1EN */
+#define IFX_FLASH_PROCOND_CAP1EN_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCOND_Bits.CAP1EN */
+#define IFX_FLASH_PROCOND_CAP1EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCOND_Bits.CAP1EN */
+#define IFX_FLASH_PROCOND_CAP1EN_OFF (13u)
+
+/** \brief Length for Ifx_FLASH_PROCOND_Bits.CAP2EN */
+#define IFX_FLASH_PROCOND_CAP2EN_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCOND_Bits.CAP2EN */
+#define IFX_FLASH_PROCOND_CAP2EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCOND_Bits.CAP2EN */
+#define IFX_FLASH_PROCOND_CAP2EN_OFF (14u)
+
+/** \brief Length for Ifx_FLASH_PROCOND_Bits.CAP3EN */
+#define IFX_FLASH_PROCOND_CAP3EN_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCOND_Bits.CAP3EN */
+#define IFX_FLASH_PROCOND_CAP3EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCOND_Bits.CAP3EN */
+#define IFX_FLASH_PROCOND_CAP3EN_OFF (15u)
+
+/** \brief Length for Ifx_FLASH_PROCOND_Bits.ESR0CNT */
+#define IFX_FLASH_PROCOND_ESR0CNT_LEN (12u)
+
+/** \brief Mask for Ifx_FLASH_PROCOND_Bits.ESR0CNT */
+#define IFX_FLASH_PROCOND_ESR0CNT_MSK (0xfffu)
+
+/** \brief Offset for Ifx_FLASH_PROCOND_Bits.ESR0CNT */
+#define IFX_FLASH_PROCOND_ESR0CNT_OFF (16u)
+
+/** \brief Length for Ifx_FLASH_PROCOND_Bits.L */
+#define IFX_FLASH_PROCOND_L_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCOND_Bits.L */
+#define IFX_FLASH_PROCOND_L_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCOND_Bits.L */
+#define IFX_FLASH_PROCOND_L_OFF (0u)
+
+/** \brief Length for Ifx_FLASH_PROCOND_Bits.MODE */
+#define IFX_FLASH_PROCOND_MODE_LEN (2u)
+
+/** \brief Mask for Ifx_FLASH_PROCOND_Bits.MODE */
+#define IFX_FLASH_PROCOND_MODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_FLASH_PROCOND_Bits.MODE */
+#define IFX_FLASH_PROCOND_MODE_OFF (9u)
+
+/** \brief Length for Ifx_FLASH_PROCOND_Bits.NSAFECC */
+#define IFX_FLASH_PROCOND_NSAFECC_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCOND_Bits.NSAFECC */
+#define IFX_FLASH_PROCOND_NSAFECC_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCOND_Bits.NSAFECC */
+#define IFX_FLASH_PROCOND_NSAFECC_OFF (1u)
+
+/** \brief Length for Ifx_FLASH_PROCOND_Bits.OSCCFG */
+#define IFX_FLASH_PROCOND_OSCCFG_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCOND_Bits.OSCCFG */
+#define IFX_FLASH_PROCOND_OSCCFG_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCOND_Bits.OSCCFG */
+#define IFX_FLASH_PROCOND_OSCCFG_OFF (8u)
+
+/** \brief Length for Ifx_FLASH_PROCOND_Bits.RAMIN */
+#define IFX_FLASH_PROCOND_RAMIN_LEN (2u)
+
+/** \brief Mask for Ifx_FLASH_PROCOND_Bits.RAMIN */
+#define IFX_FLASH_PROCOND_RAMIN_MSK (0x3u)
+
+/** \brief Offset for Ifx_FLASH_PROCOND_Bits.RAMIN */
+#define IFX_FLASH_PROCOND_RAMIN_OFF (2u)
+
+/** \brief Length for Ifx_FLASH_PROCOND_Bits.RAMINSEL */
+#define IFX_FLASH_PROCOND_RAMINSEL_LEN (4u)
+
+/** \brief Mask for Ifx_FLASH_PROCOND_Bits.RAMINSEL */
+#define IFX_FLASH_PROCOND_RAMINSEL_MSK (0xfu)
+
+/** \brief Offset for Ifx_FLASH_PROCOND_Bits.RAMINSEL */
+#define IFX_FLASH_PROCOND_RAMINSEL_OFF (4u)
+
+/** \brief Length for Ifx_FLASH_PROCOND_Bits.RES29 */
+#define IFX_FLASH_PROCOND_RES29_LEN (2u)
+
+/** \brief Mask for Ifx_FLASH_PROCOND_Bits.RES29 */
+#define IFX_FLASH_PROCOND_RES29_MSK (0x3u)
+
+/** \brief Offset for Ifx_FLASH_PROCOND_Bits.RES29 */
+#define IFX_FLASH_PROCOND_RES29_OFF (28u)
+
+/** \brief Length for Ifx_FLASH_PROCOND_Bits.RES30 */
+#define IFX_FLASH_PROCOND_RES30_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCOND_Bits.RES30 */
+#define IFX_FLASH_PROCOND_RES30_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCOND_Bits.RES30 */
+#define IFX_FLASH_PROCOND_RES30_OFF (30u)
+
+/** \brief Length for Ifx_FLASH_PROCOND_Bits.RPRO */
+#define IFX_FLASH_PROCOND_RPRO_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCOND_Bits.RPRO */
+#define IFX_FLASH_PROCOND_RPRO_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCOND_Bits.RPRO */
+#define IFX_FLASH_PROCOND_RPRO_OFF (31u)
+
+/** \brief Length for Ifx_FLASH_PROCONDBG_Bits.DBGIFLCK */
+#define IFX_FLASH_PROCONDBG_DBGIFLCK_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONDBG_Bits.DBGIFLCK */
+#define IFX_FLASH_PROCONDBG_DBGIFLCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONDBG_Bits.DBGIFLCK */
+#define IFX_FLASH_PROCONDBG_DBGIFLCK_OFF (1u)
+
+/** \brief Length for Ifx_FLASH_PROCONDBG_Bits.EDM */
+#define IFX_FLASH_PROCONDBG_EDM_LEN (2u)
+
+/** \brief Mask for Ifx_FLASH_PROCONDBG_Bits.EDM */
+#define IFX_FLASH_PROCONDBG_EDM_MSK (0x3u)
+
+/** \brief Offset for Ifx_FLASH_PROCONDBG_Bits.EDM */
+#define IFX_FLASH_PROCONDBG_EDM_OFF (2u)
+
+/** \brief Length for Ifx_FLASH_PROCONDBG_Bits.OCDSDIS */
+#define IFX_FLASH_PROCONDBG_OCDSDIS_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONDBG_Bits.OCDSDIS */
+#define IFX_FLASH_PROCONDBG_OCDSDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONDBG_Bits.OCDSDIS */
+#define IFX_FLASH_PROCONDBG_OCDSDIS_OFF (0u)
+
+/** \brief Length for Ifx_FLASH_PROCONHSM_Bits.DBGIFLCK */
+#define IFX_FLASH_PROCONHSM_DBGIFLCK_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONHSM_Bits.DBGIFLCK */
+#define IFX_FLASH_PROCONHSM_DBGIFLCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONHSM_Bits.DBGIFLCK */
+#define IFX_FLASH_PROCONHSM_DBGIFLCK_OFF (1u)
+
+/** \brief Length for Ifx_FLASH_PROCONHSM_Bits.HSMDBGDIS */
+#define IFX_FLASH_PROCONHSM_HSMDBGDIS_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONHSM_Bits.HSMDBGDIS */
+#define IFX_FLASH_PROCONHSM_HSMDBGDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONHSM_Bits.HSMDBGDIS */
+#define IFX_FLASH_PROCONHSM_HSMDBGDIS_OFF (0u)
+
+/** \brief Length for Ifx_FLASH_PROCONHSM_Bits.HSMTSTDIS */
+#define IFX_FLASH_PROCONHSM_HSMTSTDIS_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONHSM_Bits.HSMTSTDIS */
+#define IFX_FLASH_PROCONHSM_HSMTSTDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONHSM_Bits.HSMTSTDIS */
+#define IFX_FLASH_PROCONHSM_HSMTSTDIS_OFF (3u)
+
+/** \brief Length for Ifx_FLASH_PROCONHSM_Bits.RES15 */
+#define IFX_FLASH_PROCONHSM_RES15_LEN (12u)
+
+/** \brief Mask for Ifx_FLASH_PROCONHSM_Bits.RES15 */
+#define IFX_FLASH_PROCONHSM_RES15_MSK (0xfffu)
+
+/** \brief Offset for Ifx_FLASH_PROCONHSM_Bits.RES15 */
+#define IFX_FLASH_PROCONHSM_RES15_OFF (4u)
+
+/** \brief Length for Ifx_FLASH_PROCONHSM_Bits.TSTIFLCK */
+#define IFX_FLASH_PROCONHSM_TSTIFLCK_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONHSM_Bits.TSTIFLCK */
+#define IFX_FLASH_PROCONHSM_TSTIFLCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONHSM_Bits.TSTIFLCK */
+#define IFX_FLASH_PROCONHSM_TSTIFLCK_OFF (2u)
+
+/** \brief Length for Ifx_FLASH_PROCONHSMCOTP_Bits.BLKFLAN */
+#define IFX_FLASH_PROCONHSMCOTP_BLKFLAN_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.BLKFLAN */
+#define IFX_FLASH_PROCONHSMCOTP_BLKFLAN_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.BLKFLAN */
+#define IFX_FLASH_PROCONHSMCOTP_BLKFLAN_OFF (13u)
+
+/** \brief Length for Ifx_FLASH_PROCONHSMCOTP_Bits.DESTDBG */
+#define IFX_FLASH_PROCONHSMCOTP_DESTDBG_LEN (2u)
+
+/** \brief Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.DESTDBG */
+#define IFX_FLASH_PROCONHSMCOTP_DESTDBG_MSK (0x3u)
+
+/** \brief Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.DESTDBG */
+#define IFX_FLASH_PROCONHSMCOTP_DESTDBG_OFF (11u)
+
+/** \brief Length for Ifx_FLASH_PROCONHSMCOTP_Bits.HSM16X */
+#define IFX_FLASH_PROCONHSMCOTP_HSM16X_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.HSM16X */
+#define IFX_FLASH_PROCONHSMCOTP_HSM16X_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.HSM16X */
+#define IFX_FLASH_PROCONHSMCOTP_HSM16X_OFF (4u)
+
+/** \brief Length for Ifx_FLASH_PROCONHSMCOTP_Bits.HSM17X */
+#define IFX_FLASH_PROCONHSMCOTP_HSM17X_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.HSM17X */
+#define IFX_FLASH_PROCONHSMCOTP_HSM17X_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.HSM17X */
+#define IFX_FLASH_PROCONHSMCOTP_HSM17X_OFF (5u)
+
+/** \brief Length for Ifx_FLASH_PROCONHSMCOTP_Bits.HSM6X */
+#define IFX_FLASH_PROCONHSMCOTP_HSM6X_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.HSM6X */
+#define IFX_FLASH_PROCONHSMCOTP_HSM6X_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.HSM6X */
+#define IFX_FLASH_PROCONHSMCOTP_HSM6X_OFF (3u)
+
+/** \brief Length for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMBOOTEN */
+#define IFX_FLASH_PROCONHSMCOTP_HSMBOOTEN_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMBOOTEN */
+#define IFX_FLASH_PROCONHSMCOTP_HSMBOOTEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMBOOTEN */
+#define IFX_FLASH_PROCONHSMCOTP_HSMBOOTEN_OFF (0u)
+
+/** \brief Length for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMDX */
+#define IFX_FLASH_PROCONHSMCOTP_HSMDX_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMDX */
+#define IFX_FLASH_PROCONHSMCOTP_HSMDX_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMDX */
+#define IFX_FLASH_PROCONHSMCOTP_HSMDX_OFF (2u)
+
+/** \brief Length for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMENPINS */
+#define IFX_FLASH_PROCONHSMCOTP_HSMENPINS_LEN (2u)
+
+/** \brief Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMENPINS */
+#define IFX_FLASH_PROCONHSMCOTP_HSMENPINS_MSK (0x3u)
+
+/** \brief Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMENPINS */
+#define IFX_FLASH_PROCONHSMCOTP_HSMENPINS_OFF (7u)
+
+/** \brief Length for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMENRES */
+#define IFX_FLASH_PROCONHSMCOTP_HSMENRES_LEN (2u)
+
+/** \brief Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMENRES */
+#define IFX_FLASH_PROCONHSMCOTP_HSMENRES_MSK (0x3u)
+
+/** \brief Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMENRES */
+#define IFX_FLASH_PROCONHSMCOTP_HSMENRES_OFF (9u)
+
+/** \brief Length for Ifx_FLASH_PROCONHSMCOTP_Bits.S16ROM */
+#define IFX_FLASH_PROCONHSMCOTP_S16ROM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.S16ROM */
+#define IFX_FLASH_PROCONHSMCOTP_S16ROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.S16ROM */
+#define IFX_FLASH_PROCONHSMCOTP_S16ROM_OFF (16u)
+
+/** \brief Length for Ifx_FLASH_PROCONHSMCOTP_Bits.S17ROM */
+#define IFX_FLASH_PROCONHSMCOTP_S17ROM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.S17ROM */
+#define IFX_FLASH_PROCONHSMCOTP_S17ROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.S17ROM */
+#define IFX_FLASH_PROCONHSMCOTP_S17ROM_OFF (17u)
+
+/** \brief Length for Ifx_FLASH_PROCONHSMCOTP_Bits.S6ROM */
+#define IFX_FLASH_PROCONHSMCOTP_S6ROM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.S6ROM */
+#define IFX_FLASH_PROCONHSMCOTP_S6ROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.S6ROM */
+#define IFX_FLASH_PROCONHSMCOTP_S6ROM_OFF (6u)
+
+/** \brief Length for Ifx_FLASH_PROCONHSMCOTP_Bits.SSWWAIT */
+#define IFX_FLASH_PROCONHSMCOTP_SSWWAIT_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.SSWWAIT */
+#define IFX_FLASH_PROCONHSMCOTP_SSWWAIT_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.SSWWAIT */
+#define IFX_FLASH_PROCONHSMCOTP_SSWWAIT_OFF (1u)
+
+/** \brief Length for Ifx_FLASH_PROCONOTP_Bits.BML */
+#define IFX_FLASH_PROCONOTP_BML_LEN (2u)
+
+/** \brief Mask for Ifx_FLASH_PROCONOTP_Bits.BML */
+#define IFX_FLASH_PROCONOTP_BML_MSK (0x3u)
+
+/** \brief Offset for Ifx_FLASH_PROCONOTP_Bits.BML */
+#define IFX_FLASH_PROCONOTP_BML_OFF (29u)
+
+/** \brief Length for Ifx_FLASH_PROCONOTP_Bits.S0ROM */
+#define IFX_FLASH_PROCONOTP_S0ROM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONOTP_Bits.S0ROM */
+#define IFX_FLASH_PROCONOTP_S0ROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONOTP_Bits.S0ROM */
+#define IFX_FLASH_PROCONOTP_S0ROM_OFF (0u)
+
+/** \brief Length for Ifx_FLASH_PROCONOTP_Bits.S10ROM */
+#define IFX_FLASH_PROCONOTP_S10ROM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONOTP_Bits.S10ROM */
+#define IFX_FLASH_PROCONOTP_S10ROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONOTP_Bits.S10ROM */
+#define IFX_FLASH_PROCONOTP_S10ROM_OFF (10u)
+
+/** \brief Length for Ifx_FLASH_PROCONOTP_Bits.S11ROM */
+#define IFX_FLASH_PROCONOTP_S11ROM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONOTP_Bits.S11ROM */
+#define IFX_FLASH_PROCONOTP_S11ROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONOTP_Bits.S11ROM */
+#define IFX_FLASH_PROCONOTP_S11ROM_OFF (11u)
+
+/** \brief Length for Ifx_FLASH_PROCONOTP_Bits.S12ROM */
+#define IFX_FLASH_PROCONOTP_S12ROM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONOTP_Bits.S12ROM */
+#define IFX_FLASH_PROCONOTP_S12ROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONOTP_Bits.S12ROM */
+#define IFX_FLASH_PROCONOTP_S12ROM_OFF (12u)
+
+/** \brief Length for Ifx_FLASH_PROCONOTP_Bits.S13ROM */
+#define IFX_FLASH_PROCONOTP_S13ROM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONOTP_Bits.S13ROM */
+#define IFX_FLASH_PROCONOTP_S13ROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONOTP_Bits.S13ROM */
+#define IFX_FLASH_PROCONOTP_S13ROM_OFF (13u)
+
+/** \brief Length for Ifx_FLASH_PROCONOTP_Bits.S14ROM */
+#define IFX_FLASH_PROCONOTP_S14ROM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONOTP_Bits.S14ROM */
+#define IFX_FLASH_PROCONOTP_S14ROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONOTP_Bits.S14ROM */
+#define IFX_FLASH_PROCONOTP_S14ROM_OFF (14u)
+
+/** \brief Length for Ifx_FLASH_PROCONOTP_Bits.S15ROM */
+#define IFX_FLASH_PROCONOTP_S15ROM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONOTP_Bits.S15ROM */
+#define IFX_FLASH_PROCONOTP_S15ROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONOTP_Bits.S15ROM */
+#define IFX_FLASH_PROCONOTP_S15ROM_OFF (15u)
+
+/** \brief Length for Ifx_FLASH_PROCONOTP_Bits.S16ROM */
+#define IFX_FLASH_PROCONOTP_S16ROM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONOTP_Bits.S16ROM */
+#define IFX_FLASH_PROCONOTP_S16ROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONOTP_Bits.S16ROM */
+#define IFX_FLASH_PROCONOTP_S16ROM_OFF (16u)
+
+/** \brief Length for Ifx_FLASH_PROCONOTP_Bits.S17ROM */
+#define IFX_FLASH_PROCONOTP_S17ROM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONOTP_Bits.S17ROM */
+#define IFX_FLASH_PROCONOTP_S17ROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONOTP_Bits.S17ROM */
+#define IFX_FLASH_PROCONOTP_S17ROM_OFF (17u)
+
+/** \brief Length for Ifx_FLASH_PROCONOTP_Bits.S18ROM */
+#define IFX_FLASH_PROCONOTP_S18ROM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONOTP_Bits.S18ROM */
+#define IFX_FLASH_PROCONOTP_S18ROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONOTP_Bits.S18ROM */
+#define IFX_FLASH_PROCONOTP_S18ROM_OFF (18u)
+
+/** \brief Length for Ifx_FLASH_PROCONOTP_Bits.S19ROM */
+#define IFX_FLASH_PROCONOTP_S19ROM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONOTP_Bits.S19ROM */
+#define IFX_FLASH_PROCONOTP_S19ROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONOTP_Bits.S19ROM */
+#define IFX_FLASH_PROCONOTP_S19ROM_OFF (19u)
+
+/** \brief Length for Ifx_FLASH_PROCONOTP_Bits.S1ROM */
+#define IFX_FLASH_PROCONOTP_S1ROM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONOTP_Bits.S1ROM */
+#define IFX_FLASH_PROCONOTP_S1ROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONOTP_Bits.S1ROM */
+#define IFX_FLASH_PROCONOTP_S1ROM_OFF (1u)
+
+/** \brief Length for Ifx_FLASH_PROCONOTP_Bits.S20ROM */
+#define IFX_FLASH_PROCONOTP_S20ROM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONOTP_Bits.S20ROM */
+#define IFX_FLASH_PROCONOTP_S20ROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONOTP_Bits.S20ROM */
+#define IFX_FLASH_PROCONOTP_S20ROM_OFF (20u)
+
+/** \brief Length for Ifx_FLASH_PROCONOTP_Bits.S21ROM */
+#define IFX_FLASH_PROCONOTP_S21ROM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONOTP_Bits.S21ROM */
+#define IFX_FLASH_PROCONOTP_S21ROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONOTP_Bits.S21ROM */
+#define IFX_FLASH_PROCONOTP_S21ROM_OFF (21u)
+
+/** \brief Length for Ifx_FLASH_PROCONOTP_Bits.S22ROM */
+#define IFX_FLASH_PROCONOTP_S22ROM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONOTP_Bits.S22ROM */
+#define IFX_FLASH_PROCONOTP_S22ROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONOTP_Bits.S22ROM */
+#define IFX_FLASH_PROCONOTP_S22ROM_OFF (22u)
+
+/** \brief Length for Ifx_FLASH_PROCONOTP_Bits.S23ROM */
+#define IFX_FLASH_PROCONOTP_S23ROM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONOTP_Bits.S23ROM */
+#define IFX_FLASH_PROCONOTP_S23ROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONOTP_Bits.S23ROM */
+#define IFX_FLASH_PROCONOTP_S23ROM_OFF (23u)
+
+/** \brief Length for Ifx_FLASH_PROCONOTP_Bits.S24ROM */
+#define IFX_FLASH_PROCONOTP_S24ROM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONOTP_Bits.S24ROM */
+#define IFX_FLASH_PROCONOTP_S24ROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONOTP_Bits.S24ROM */
+#define IFX_FLASH_PROCONOTP_S24ROM_OFF (24u)
+
+/** \brief Length for Ifx_FLASH_PROCONOTP_Bits.S25ROM */
+#define IFX_FLASH_PROCONOTP_S25ROM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONOTP_Bits.S25ROM */
+#define IFX_FLASH_PROCONOTP_S25ROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONOTP_Bits.S25ROM */
+#define IFX_FLASH_PROCONOTP_S25ROM_OFF (25u)
+
+/** \brief Length for Ifx_FLASH_PROCONOTP_Bits.S26ROM */
+#define IFX_FLASH_PROCONOTP_S26ROM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONOTP_Bits.S26ROM */
+#define IFX_FLASH_PROCONOTP_S26ROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONOTP_Bits.S26ROM */
+#define IFX_FLASH_PROCONOTP_S26ROM_OFF (26u)
+
+/** \brief Length for Ifx_FLASH_PROCONOTP_Bits.S2ROM */
+#define IFX_FLASH_PROCONOTP_S2ROM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONOTP_Bits.S2ROM */
+#define IFX_FLASH_PROCONOTP_S2ROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONOTP_Bits.S2ROM */
+#define IFX_FLASH_PROCONOTP_S2ROM_OFF (2u)
+
+/** \brief Length for Ifx_FLASH_PROCONOTP_Bits.S3ROM */
+#define IFX_FLASH_PROCONOTP_S3ROM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONOTP_Bits.S3ROM */
+#define IFX_FLASH_PROCONOTP_S3ROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONOTP_Bits.S3ROM */
+#define IFX_FLASH_PROCONOTP_S3ROM_OFF (3u)
+
+/** \brief Length for Ifx_FLASH_PROCONOTP_Bits.S4ROM */
+#define IFX_FLASH_PROCONOTP_S4ROM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONOTP_Bits.S4ROM */
+#define IFX_FLASH_PROCONOTP_S4ROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONOTP_Bits.S4ROM */
+#define IFX_FLASH_PROCONOTP_S4ROM_OFF (4u)
+
+/** \brief Length for Ifx_FLASH_PROCONOTP_Bits.S5ROM */
+#define IFX_FLASH_PROCONOTP_S5ROM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONOTP_Bits.S5ROM */
+#define IFX_FLASH_PROCONOTP_S5ROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONOTP_Bits.S5ROM */
+#define IFX_FLASH_PROCONOTP_S5ROM_OFF (5u)
+
+/** \brief Length for Ifx_FLASH_PROCONOTP_Bits.S6ROM */
+#define IFX_FLASH_PROCONOTP_S6ROM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONOTP_Bits.S6ROM */
+#define IFX_FLASH_PROCONOTP_S6ROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONOTP_Bits.S6ROM */
+#define IFX_FLASH_PROCONOTP_S6ROM_OFF (6u)
+
+/** \brief Length for Ifx_FLASH_PROCONOTP_Bits.S7ROM */
+#define IFX_FLASH_PROCONOTP_S7ROM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONOTP_Bits.S7ROM */
+#define IFX_FLASH_PROCONOTP_S7ROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONOTP_Bits.S7ROM */
+#define IFX_FLASH_PROCONOTP_S7ROM_OFF (7u)
+
+/** \brief Length for Ifx_FLASH_PROCONOTP_Bits.S8ROM */
+#define IFX_FLASH_PROCONOTP_S8ROM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONOTP_Bits.S8ROM */
+#define IFX_FLASH_PROCONOTP_S8ROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONOTP_Bits.S8ROM */
+#define IFX_FLASH_PROCONOTP_S8ROM_OFF (8u)
+
+/** \brief Length for Ifx_FLASH_PROCONOTP_Bits.S9ROM */
+#define IFX_FLASH_PROCONOTP_S9ROM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONOTP_Bits.S9ROM */
+#define IFX_FLASH_PROCONOTP_S9ROM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONOTP_Bits.S9ROM */
+#define IFX_FLASH_PROCONOTP_S9ROM_OFF (9u)
+
+/** \brief Length for Ifx_FLASH_PROCONOTP_Bits.TP */
+#define IFX_FLASH_PROCONOTP_TP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONOTP_Bits.TP */
+#define IFX_FLASH_PROCONOTP_TP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONOTP_Bits.TP */
+#define IFX_FLASH_PROCONOTP_TP_OFF (31u)
+
+/** \brief Length for Ifx_FLASH_PROCONP_Bits.RPRO */
+#define IFX_FLASH_PROCONP_RPRO_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONP_Bits.RPRO */
+#define IFX_FLASH_PROCONP_RPRO_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONP_Bits.RPRO */
+#define IFX_FLASH_PROCONP_RPRO_OFF (31u)
+
+/** \brief Length for Ifx_FLASH_PROCONP_Bits.S0L */
+#define IFX_FLASH_PROCONP_S0L_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONP_Bits.S0L */
+#define IFX_FLASH_PROCONP_S0L_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONP_Bits.S0L */
+#define IFX_FLASH_PROCONP_S0L_OFF (0u)
+
+/** \brief Length for Ifx_FLASH_PROCONP_Bits.S10L */
+#define IFX_FLASH_PROCONP_S10L_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONP_Bits.S10L */
+#define IFX_FLASH_PROCONP_S10L_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONP_Bits.S10L */
+#define IFX_FLASH_PROCONP_S10L_OFF (10u)
+
+/** \brief Length for Ifx_FLASH_PROCONP_Bits.S11L */
+#define IFX_FLASH_PROCONP_S11L_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONP_Bits.S11L */
+#define IFX_FLASH_PROCONP_S11L_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONP_Bits.S11L */
+#define IFX_FLASH_PROCONP_S11L_OFF (11u)
+
+/** \brief Length for Ifx_FLASH_PROCONP_Bits.S12L */
+#define IFX_FLASH_PROCONP_S12L_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONP_Bits.S12L */
+#define IFX_FLASH_PROCONP_S12L_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONP_Bits.S12L */
+#define IFX_FLASH_PROCONP_S12L_OFF (12u)
+
+/** \brief Length for Ifx_FLASH_PROCONP_Bits.S13L */
+#define IFX_FLASH_PROCONP_S13L_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONP_Bits.S13L */
+#define IFX_FLASH_PROCONP_S13L_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONP_Bits.S13L */
+#define IFX_FLASH_PROCONP_S13L_OFF (13u)
+
+/** \brief Length for Ifx_FLASH_PROCONP_Bits.S14L */
+#define IFX_FLASH_PROCONP_S14L_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONP_Bits.S14L */
+#define IFX_FLASH_PROCONP_S14L_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONP_Bits.S14L */
+#define IFX_FLASH_PROCONP_S14L_OFF (14u)
+
+/** \brief Length for Ifx_FLASH_PROCONP_Bits.S15L */
+#define IFX_FLASH_PROCONP_S15L_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONP_Bits.S15L */
+#define IFX_FLASH_PROCONP_S15L_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONP_Bits.S15L */
+#define IFX_FLASH_PROCONP_S15L_OFF (15u)
+
+/** \brief Length for Ifx_FLASH_PROCONP_Bits.S16L */
+#define IFX_FLASH_PROCONP_S16L_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONP_Bits.S16L */
+#define IFX_FLASH_PROCONP_S16L_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONP_Bits.S16L */
+#define IFX_FLASH_PROCONP_S16L_OFF (16u)
+
+/** \brief Length for Ifx_FLASH_PROCONP_Bits.S17L */
+#define IFX_FLASH_PROCONP_S17L_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONP_Bits.S17L */
+#define IFX_FLASH_PROCONP_S17L_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONP_Bits.S17L */
+#define IFX_FLASH_PROCONP_S17L_OFF (17u)
+
+/** \brief Length for Ifx_FLASH_PROCONP_Bits.S18L */
+#define IFX_FLASH_PROCONP_S18L_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONP_Bits.S18L */
+#define IFX_FLASH_PROCONP_S18L_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONP_Bits.S18L */
+#define IFX_FLASH_PROCONP_S18L_OFF (18u)
+
+/** \brief Length for Ifx_FLASH_PROCONP_Bits.S19L */
+#define IFX_FLASH_PROCONP_S19L_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONP_Bits.S19L */
+#define IFX_FLASH_PROCONP_S19L_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONP_Bits.S19L */
+#define IFX_FLASH_PROCONP_S19L_OFF (19u)
+
+/** \brief Length for Ifx_FLASH_PROCONP_Bits.S1L */
+#define IFX_FLASH_PROCONP_S1L_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONP_Bits.S1L */
+#define IFX_FLASH_PROCONP_S1L_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONP_Bits.S1L */
+#define IFX_FLASH_PROCONP_S1L_OFF (1u)
+
+/** \brief Length for Ifx_FLASH_PROCONP_Bits.S20L */
+#define IFX_FLASH_PROCONP_S20L_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONP_Bits.S20L */
+#define IFX_FLASH_PROCONP_S20L_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONP_Bits.S20L */
+#define IFX_FLASH_PROCONP_S20L_OFF (20u)
+
+/** \brief Length for Ifx_FLASH_PROCONP_Bits.S21L */
+#define IFX_FLASH_PROCONP_S21L_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONP_Bits.S21L */
+#define IFX_FLASH_PROCONP_S21L_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONP_Bits.S21L */
+#define IFX_FLASH_PROCONP_S21L_OFF (21u)
+
+/** \brief Length for Ifx_FLASH_PROCONP_Bits.S22L */
+#define IFX_FLASH_PROCONP_S22L_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONP_Bits.S22L */
+#define IFX_FLASH_PROCONP_S22L_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONP_Bits.S22L */
+#define IFX_FLASH_PROCONP_S22L_OFF (22u)
+
+/** \brief Length for Ifx_FLASH_PROCONP_Bits.S23L */
+#define IFX_FLASH_PROCONP_S23L_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONP_Bits.S23L */
+#define IFX_FLASH_PROCONP_S23L_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONP_Bits.S23L */
+#define IFX_FLASH_PROCONP_S23L_OFF (23u)
+
+/** \brief Length for Ifx_FLASH_PROCONP_Bits.S24L */
+#define IFX_FLASH_PROCONP_S24L_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONP_Bits.S24L */
+#define IFX_FLASH_PROCONP_S24L_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONP_Bits.S24L */
+#define IFX_FLASH_PROCONP_S24L_OFF (24u)
+
+/** \brief Length for Ifx_FLASH_PROCONP_Bits.S25L */
+#define IFX_FLASH_PROCONP_S25L_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONP_Bits.S25L */
+#define IFX_FLASH_PROCONP_S25L_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONP_Bits.S25L */
+#define IFX_FLASH_PROCONP_S25L_OFF (25u)
+
+/** \brief Length for Ifx_FLASH_PROCONP_Bits.S26L */
+#define IFX_FLASH_PROCONP_S26L_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONP_Bits.S26L */
+#define IFX_FLASH_PROCONP_S26L_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONP_Bits.S26L */
+#define IFX_FLASH_PROCONP_S26L_OFF (26u)
+
+/** \brief Length for Ifx_FLASH_PROCONP_Bits.S2L */
+#define IFX_FLASH_PROCONP_S2L_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONP_Bits.S2L */
+#define IFX_FLASH_PROCONP_S2L_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONP_Bits.S2L */
+#define IFX_FLASH_PROCONP_S2L_OFF (2u)
+
+/** \brief Length for Ifx_FLASH_PROCONP_Bits.S3L */
+#define IFX_FLASH_PROCONP_S3L_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONP_Bits.S3L */
+#define IFX_FLASH_PROCONP_S3L_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONP_Bits.S3L */
+#define IFX_FLASH_PROCONP_S3L_OFF (3u)
+
+/** \brief Length for Ifx_FLASH_PROCONP_Bits.S4L */
+#define IFX_FLASH_PROCONP_S4L_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONP_Bits.S4L */
+#define IFX_FLASH_PROCONP_S4L_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONP_Bits.S4L */
+#define IFX_FLASH_PROCONP_S4L_OFF (4u)
+
+/** \brief Length for Ifx_FLASH_PROCONP_Bits.S5L */
+#define IFX_FLASH_PROCONP_S5L_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONP_Bits.S5L */
+#define IFX_FLASH_PROCONP_S5L_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONP_Bits.S5L */
+#define IFX_FLASH_PROCONP_S5L_OFF (5u)
+
+/** \brief Length for Ifx_FLASH_PROCONP_Bits.S6L */
+#define IFX_FLASH_PROCONP_S6L_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONP_Bits.S6L */
+#define IFX_FLASH_PROCONP_S6L_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONP_Bits.S6L */
+#define IFX_FLASH_PROCONP_S6L_OFF (6u)
+
+/** \brief Length for Ifx_FLASH_PROCONP_Bits.S7L */
+#define IFX_FLASH_PROCONP_S7L_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONP_Bits.S7L */
+#define IFX_FLASH_PROCONP_S7L_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONP_Bits.S7L */
+#define IFX_FLASH_PROCONP_S7L_OFF (7u)
+
+/** \brief Length for Ifx_FLASH_PROCONP_Bits.S8L */
+#define IFX_FLASH_PROCONP_S8L_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONP_Bits.S8L */
+#define IFX_FLASH_PROCONP_S8L_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONP_Bits.S8L */
+#define IFX_FLASH_PROCONP_S8L_OFF (8u)
+
+/** \brief Length for Ifx_FLASH_PROCONP_Bits.S9L */
+#define IFX_FLASH_PROCONP_S9L_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONP_Bits.S9L */
+#define IFX_FLASH_PROCONP_S9L_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONP_Bits.S9L */
+#define IFX_FLASH_PROCONP_S9L_OFF (9u)
+
+/** \brief Length for Ifx_FLASH_PROCONWOP_Bits.DATM */
+#define IFX_FLASH_PROCONWOP_DATM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONWOP_Bits.DATM */
+#define IFX_FLASH_PROCONWOP_DATM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONWOP_Bits.DATM */
+#define IFX_FLASH_PROCONWOP_DATM_OFF (31u)
+
+/** \brief Length for Ifx_FLASH_PROCONWOP_Bits.S0WOP */
+#define IFX_FLASH_PROCONWOP_S0WOP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONWOP_Bits.S0WOP */
+#define IFX_FLASH_PROCONWOP_S0WOP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONWOP_Bits.S0WOP */
+#define IFX_FLASH_PROCONWOP_S0WOP_OFF (0u)
+
+/** \brief Length for Ifx_FLASH_PROCONWOP_Bits.S10WOP */
+#define IFX_FLASH_PROCONWOP_S10WOP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONWOP_Bits.S10WOP */
+#define IFX_FLASH_PROCONWOP_S10WOP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONWOP_Bits.S10WOP */
+#define IFX_FLASH_PROCONWOP_S10WOP_OFF (10u)
+
+/** \brief Length for Ifx_FLASH_PROCONWOP_Bits.S11WOP */
+#define IFX_FLASH_PROCONWOP_S11WOP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONWOP_Bits.S11WOP */
+#define IFX_FLASH_PROCONWOP_S11WOP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONWOP_Bits.S11WOP */
+#define IFX_FLASH_PROCONWOP_S11WOP_OFF (11u)
+
+/** \brief Length for Ifx_FLASH_PROCONWOP_Bits.S12WOP */
+#define IFX_FLASH_PROCONWOP_S12WOP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONWOP_Bits.S12WOP */
+#define IFX_FLASH_PROCONWOP_S12WOP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONWOP_Bits.S12WOP */
+#define IFX_FLASH_PROCONWOP_S12WOP_OFF (12u)
+
+/** \brief Length for Ifx_FLASH_PROCONWOP_Bits.S13WOP */
+#define IFX_FLASH_PROCONWOP_S13WOP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONWOP_Bits.S13WOP */
+#define IFX_FLASH_PROCONWOP_S13WOP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONWOP_Bits.S13WOP */
+#define IFX_FLASH_PROCONWOP_S13WOP_OFF (13u)
+
+/** \brief Length for Ifx_FLASH_PROCONWOP_Bits.S14WOP */
+#define IFX_FLASH_PROCONWOP_S14WOP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONWOP_Bits.S14WOP */
+#define IFX_FLASH_PROCONWOP_S14WOP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONWOP_Bits.S14WOP */
+#define IFX_FLASH_PROCONWOP_S14WOP_OFF (14u)
+
+/** \brief Length for Ifx_FLASH_PROCONWOP_Bits.S15WOP */
+#define IFX_FLASH_PROCONWOP_S15WOP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONWOP_Bits.S15WOP */
+#define IFX_FLASH_PROCONWOP_S15WOP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONWOP_Bits.S15WOP */
+#define IFX_FLASH_PROCONWOP_S15WOP_OFF (15u)
+
+/** \brief Length for Ifx_FLASH_PROCONWOP_Bits.S16WOP */
+#define IFX_FLASH_PROCONWOP_S16WOP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONWOP_Bits.S16WOP */
+#define IFX_FLASH_PROCONWOP_S16WOP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONWOP_Bits.S16WOP */
+#define IFX_FLASH_PROCONWOP_S16WOP_OFF (16u)
+
+/** \brief Length for Ifx_FLASH_PROCONWOP_Bits.S17WOP */
+#define IFX_FLASH_PROCONWOP_S17WOP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONWOP_Bits.S17WOP */
+#define IFX_FLASH_PROCONWOP_S17WOP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONWOP_Bits.S17WOP */
+#define IFX_FLASH_PROCONWOP_S17WOP_OFF (17u)
+
+/** \brief Length for Ifx_FLASH_PROCONWOP_Bits.S18WOP */
+#define IFX_FLASH_PROCONWOP_S18WOP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONWOP_Bits.S18WOP */
+#define IFX_FLASH_PROCONWOP_S18WOP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONWOP_Bits.S18WOP */
+#define IFX_FLASH_PROCONWOP_S18WOP_OFF (18u)
+
+/** \brief Length for Ifx_FLASH_PROCONWOP_Bits.S19WOP */
+#define IFX_FLASH_PROCONWOP_S19WOP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONWOP_Bits.S19WOP */
+#define IFX_FLASH_PROCONWOP_S19WOP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONWOP_Bits.S19WOP */
+#define IFX_FLASH_PROCONWOP_S19WOP_OFF (19u)
+
+/** \brief Length for Ifx_FLASH_PROCONWOP_Bits.S1WOP */
+#define IFX_FLASH_PROCONWOP_S1WOP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONWOP_Bits.S1WOP */
+#define IFX_FLASH_PROCONWOP_S1WOP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONWOP_Bits.S1WOP */
+#define IFX_FLASH_PROCONWOP_S1WOP_OFF (1u)
+
+/** \brief Length for Ifx_FLASH_PROCONWOP_Bits.S20WOP */
+#define IFX_FLASH_PROCONWOP_S20WOP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONWOP_Bits.S20WOP */
+#define IFX_FLASH_PROCONWOP_S20WOP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONWOP_Bits.S20WOP */
+#define IFX_FLASH_PROCONWOP_S20WOP_OFF (20u)
+
+/** \brief Length for Ifx_FLASH_PROCONWOP_Bits.S21WOP */
+#define IFX_FLASH_PROCONWOP_S21WOP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONWOP_Bits.S21WOP */
+#define IFX_FLASH_PROCONWOP_S21WOP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONWOP_Bits.S21WOP */
+#define IFX_FLASH_PROCONWOP_S21WOP_OFF (21u)
+
+/** \brief Length for Ifx_FLASH_PROCONWOP_Bits.S22WOP */
+#define IFX_FLASH_PROCONWOP_S22WOP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONWOP_Bits.S22WOP */
+#define IFX_FLASH_PROCONWOP_S22WOP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONWOP_Bits.S22WOP */
+#define IFX_FLASH_PROCONWOP_S22WOP_OFF (22u)
+
+/** \brief Length for Ifx_FLASH_PROCONWOP_Bits.S23WOP */
+#define IFX_FLASH_PROCONWOP_S23WOP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONWOP_Bits.S23WOP */
+#define IFX_FLASH_PROCONWOP_S23WOP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONWOP_Bits.S23WOP */
+#define IFX_FLASH_PROCONWOP_S23WOP_OFF (23u)
+
+/** \brief Length for Ifx_FLASH_PROCONWOP_Bits.S24WOP */
+#define IFX_FLASH_PROCONWOP_S24WOP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONWOP_Bits.S24WOP */
+#define IFX_FLASH_PROCONWOP_S24WOP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONWOP_Bits.S24WOP */
+#define IFX_FLASH_PROCONWOP_S24WOP_OFF (24u)
+
+/** \brief Length for Ifx_FLASH_PROCONWOP_Bits.S25WOP */
+#define IFX_FLASH_PROCONWOP_S25WOP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONWOP_Bits.S25WOP */
+#define IFX_FLASH_PROCONWOP_S25WOP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONWOP_Bits.S25WOP */
+#define IFX_FLASH_PROCONWOP_S25WOP_OFF (25u)
+
+/** \brief Length for Ifx_FLASH_PROCONWOP_Bits.S26WOP */
+#define IFX_FLASH_PROCONWOP_S26WOP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONWOP_Bits.S26WOP */
+#define IFX_FLASH_PROCONWOP_S26WOP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONWOP_Bits.S26WOP */
+#define IFX_FLASH_PROCONWOP_S26WOP_OFF (26u)
+
+/** \brief Length for Ifx_FLASH_PROCONWOP_Bits.S2WOP */
+#define IFX_FLASH_PROCONWOP_S2WOP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONWOP_Bits.S2WOP */
+#define IFX_FLASH_PROCONWOP_S2WOP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONWOP_Bits.S2WOP */
+#define IFX_FLASH_PROCONWOP_S2WOP_OFF (2u)
+
+/** \brief Length for Ifx_FLASH_PROCONWOP_Bits.S3WOP */
+#define IFX_FLASH_PROCONWOP_S3WOP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONWOP_Bits.S3WOP */
+#define IFX_FLASH_PROCONWOP_S3WOP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONWOP_Bits.S3WOP */
+#define IFX_FLASH_PROCONWOP_S3WOP_OFF (3u)
+
+/** \brief Length for Ifx_FLASH_PROCONWOP_Bits.S4WOP */
+#define IFX_FLASH_PROCONWOP_S4WOP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONWOP_Bits.S4WOP */
+#define IFX_FLASH_PROCONWOP_S4WOP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONWOP_Bits.S4WOP */
+#define IFX_FLASH_PROCONWOP_S4WOP_OFF (4u)
+
+/** \brief Length for Ifx_FLASH_PROCONWOP_Bits.S5WOP */
+#define IFX_FLASH_PROCONWOP_S5WOP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONWOP_Bits.S5WOP */
+#define IFX_FLASH_PROCONWOP_S5WOP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONWOP_Bits.S5WOP */
+#define IFX_FLASH_PROCONWOP_S5WOP_OFF (5u)
+
+/** \brief Length for Ifx_FLASH_PROCONWOP_Bits.S6WOP */
+#define IFX_FLASH_PROCONWOP_S6WOP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONWOP_Bits.S6WOP */
+#define IFX_FLASH_PROCONWOP_S6WOP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONWOP_Bits.S6WOP */
+#define IFX_FLASH_PROCONWOP_S6WOP_OFF (6u)
+
+/** \brief Length for Ifx_FLASH_PROCONWOP_Bits.S7WOP */
+#define IFX_FLASH_PROCONWOP_S7WOP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONWOP_Bits.S7WOP */
+#define IFX_FLASH_PROCONWOP_S7WOP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONWOP_Bits.S7WOP */
+#define IFX_FLASH_PROCONWOP_S7WOP_OFF (7u)
+
+/** \brief Length for Ifx_FLASH_PROCONWOP_Bits.S8WOP */
+#define IFX_FLASH_PROCONWOP_S8WOP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONWOP_Bits.S8WOP */
+#define IFX_FLASH_PROCONWOP_S8WOP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONWOP_Bits.S8WOP */
+#define IFX_FLASH_PROCONWOP_S8WOP_OFF (8u)
+
+/** \brief Length for Ifx_FLASH_PROCONWOP_Bits.S9WOP */
+#define IFX_FLASH_PROCONWOP_S9WOP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_PROCONWOP_Bits.S9WOP */
+#define IFX_FLASH_PROCONWOP_S9WOP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_PROCONWOP_Bits.S9WOP */
+#define IFX_FLASH_PROCONWOP_S9WOP_OFF (9u)
+
+/** \brief Length for Ifx_FLASH_RDB_CFG0_Bits.TAG */
+#define IFX_FLASH_RDB_CFG0_TAG_LEN (6u)
+
+/** \brief Mask for Ifx_FLASH_RDB_CFG0_Bits.TAG */
+#define IFX_FLASH_RDB_CFG0_TAG_MSK (0x3fu)
+
+/** \brief Offset for Ifx_FLASH_RDB_CFG0_Bits.TAG */
+#define IFX_FLASH_RDB_CFG0_TAG_OFF (0u)
+
+/** \brief Length for Ifx_FLASH_RDB_CFG1_Bits.TAG */
+#define IFX_FLASH_RDB_CFG1_TAG_LEN (6u)
+
+/** \brief Mask for Ifx_FLASH_RDB_CFG1_Bits.TAG */
+#define IFX_FLASH_RDB_CFG1_TAG_MSK (0x3fu)
+
+/** \brief Offset for Ifx_FLASH_RDB_CFG1_Bits.TAG */
+#define IFX_FLASH_RDB_CFG1_TAG_OFF (0u)
+
+/** \brief Length for Ifx_FLASH_RDB_CFG2_Bits.TAG */
+#define IFX_FLASH_RDB_CFG2_TAG_LEN (6u)
+
+/** \brief Mask for Ifx_FLASH_RDB_CFG2_Bits.TAG */
+#define IFX_FLASH_RDB_CFG2_TAG_MSK (0x3fu)
+
+/** \brief Offset for Ifx_FLASH_RDB_CFG2_Bits.TAG */
+#define IFX_FLASH_RDB_CFG2_TAG_OFF (0u)
+
+/** \brief Length for Ifx_FLASH_RRAD_Bits.ADD */
+#define IFX_FLASH_RRAD_ADD_LEN (29u)
+
+/** \brief Mask for Ifx_FLASH_RRAD_Bits.ADD */
+#define IFX_FLASH_RRAD_ADD_MSK (0x1fffffffu)
+
+/** \brief Offset for Ifx_FLASH_RRAD_Bits.ADD */
+#define IFX_FLASH_RRAD_ADD_OFF (3u)
+
+/** \brief Length for Ifx_FLASH_RRCT_Bits.BUSY */
+#define IFX_FLASH_RRCT_BUSY_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_RRCT_Bits.BUSY */
+#define IFX_FLASH_RRCT_BUSY_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_RRCT_Bits.BUSY */
+#define IFX_FLASH_RRCT_BUSY_OFF (2u)
+
+/** \brief Length for Ifx_FLASH_RRCT_Bits.CNT */
+#define IFX_FLASH_RRCT_CNT_LEN (16u)
+
+/** \brief Mask for Ifx_FLASH_RRCT_Bits.CNT */
+#define IFX_FLASH_RRCT_CNT_MSK (0xffffu)
+
+/** \brief Offset for Ifx_FLASH_RRCT_Bits.CNT */
+#define IFX_FLASH_RRCT_CNT_OFF (16u)
+
+/** \brief Length for Ifx_FLASH_RRCT_Bits.DONE */
+#define IFX_FLASH_RRCT_DONE_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_RRCT_Bits.DONE */
+#define IFX_FLASH_RRCT_DONE_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_RRCT_Bits.DONE */
+#define IFX_FLASH_RRCT_DONE_OFF (3u)
+
+/** \brief Length for Ifx_FLASH_RRCT_Bits.EOBM */
+#define IFX_FLASH_RRCT_EOBM_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_RRCT_Bits.EOBM */
+#define IFX_FLASH_RRCT_EOBM_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_RRCT_Bits.EOBM */
+#define IFX_FLASH_RRCT_EOBM_OFF (8u)
+
+/** \brief Length for Ifx_FLASH_RRCT_Bits.ERR */
+#define IFX_FLASH_RRCT_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_RRCT_Bits.ERR */
+#define IFX_FLASH_RRCT_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_RRCT_Bits.ERR */
+#define IFX_FLASH_RRCT_ERR_OFF (4u)
+
+/** \brief Length for Ifx_FLASH_RRCT_Bits.STP */
+#define IFX_FLASH_RRCT_STP_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_RRCT_Bits.STP */
+#define IFX_FLASH_RRCT_STP_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_RRCT_Bits.STP */
+#define IFX_FLASH_RRCT_STP_OFF (1u)
+
+/** \brief Length for Ifx_FLASH_RRCT_Bits.STRT */
+#define IFX_FLASH_RRCT_STRT_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_RRCT_Bits.STRT */
+#define IFX_FLASH_RRCT_STRT_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_RRCT_Bits.STRT */
+#define IFX_FLASH_RRCT_STRT_OFF (0u)
+
+/** \brief Length for Ifx_FLASH_RRD0_Bits.DATA */
+#define IFX_FLASH_RRD0_DATA_LEN (32u)
+
+/** \brief Mask for Ifx_FLASH_RRD0_Bits.DATA */
+#define IFX_FLASH_RRD0_DATA_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_FLASH_RRD0_Bits.DATA */
+#define IFX_FLASH_RRD0_DATA_OFF (0u)
+
+/** \brief Length for Ifx_FLASH_RRD1_Bits.DATA */
+#define IFX_FLASH_RRD1_DATA_LEN (32u)
+
+/** \brief Mask for Ifx_FLASH_RRD1_Bits.DATA */
+#define IFX_FLASH_RRD1_DATA_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_FLASH_RRD1_Bits.DATA */
+#define IFX_FLASH_RRD1_DATA_OFF (0u)
+
+/** \brief Length for Ifx_FLASH_UBAB_CFG_Bits.CLR */
+#define IFX_FLASH_UBAB_CFG_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_UBAB_CFG_Bits.CLR */
+#define IFX_FLASH_UBAB_CFG_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_UBAB_CFG_Bits.CLR */
+#define IFX_FLASH_UBAB_CFG_CLR_OFF (8u)
+
+/** \brief Length for Ifx_FLASH_UBAB_CFG_Bits.DIS */
+#define IFX_FLASH_UBAB_CFG_DIS_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_UBAB_CFG_Bits.DIS */
+#define IFX_FLASH_UBAB_CFG_DIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_UBAB_CFG_Bits.DIS */
+#define IFX_FLASH_UBAB_CFG_DIS_OFF (9u)
+
+/** \brief Length for Ifx_FLASH_UBAB_CFG_Bits.SEL */
+#define IFX_FLASH_UBAB_CFG_SEL_LEN (6u)
+
+/** \brief Mask for Ifx_FLASH_UBAB_CFG_Bits.SEL */
+#define IFX_FLASH_UBAB_CFG_SEL_MSK (0x3fu)
+
+/** \brief Offset for Ifx_FLASH_UBAB_CFG_Bits.SEL */
+#define IFX_FLASH_UBAB_CFG_SEL_OFF (0u)
+
+/** \brief Length for Ifx_FLASH_UBAB_STAT_Bits.VLD0 */
+#define IFX_FLASH_UBAB_STAT_VLD0_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_UBAB_STAT_Bits.VLD0 */
+#define IFX_FLASH_UBAB_STAT_VLD0_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_UBAB_STAT_Bits.VLD0 */
+#define IFX_FLASH_UBAB_STAT_VLD0_OFF (0u)
+
+/** \brief Length for Ifx_FLASH_UBAB_TOP_Bits.ADDR */
+#define IFX_FLASH_UBAB_TOP_ADDR_LEN (19u)
+
+/** \brief Mask for Ifx_FLASH_UBAB_TOP_Bits.ADDR */
+#define IFX_FLASH_UBAB_TOP_ADDR_MSK (0x7ffffu)
+
+/** \brief Offset for Ifx_FLASH_UBAB_TOP_Bits.ADDR */
+#define IFX_FLASH_UBAB_TOP_ADDR_OFF (5u)
+
+/** \brief Length for Ifx_FLASH_UBAB_TOP_Bits.CLR */
+#define IFX_FLASH_UBAB_TOP_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_UBAB_TOP_Bits.CLR */
+#define IFX_FLASH_UBAB_TOP_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_UBAB_TOP_Bits.CLR */
+#define IFX_FLASH_UBAB_TOP_CLR_OFF (31u)
+
+/** \brief Length for Ifx_FLASH_UBAB_TOP_Bits.ERR */
+#define IFX_FLASH_UBAB_TOP_ERR_LEN (6u)
+
+/** \brief Mask for Ifx_FLASH_UBAB_TOP_Bits.ERR */
+#define IFX_FLASH_UBAB_TOP_ERR_MSK (0x3fu)
+
+/** \brief Offset for Ifx_FLASH_UBAB_TOP_Bits.ERR */
+#define IFX_FLASH_UBAB_TOP_ERR_OFF (24u)
+
+/** \brief Length for Ifx_FLASH_UBAB_TOP_Bits.VLD */
+#define IFX_FLASH_UBAB_TOP_VLD_LEN (1u)
+
+/** \brief Mask for Ifx_FLASH_UBAB_TOP_Bits.VLD */
+#define IFX_FLASH_UBAB_TOP_VLD_MSK (0x1u)
+
+/** \brief Offset for Ifx_FLASH_UBAB_TOP_Bits.VLD */
+#define IFX_FLASH_UBAB_TOP_VLD_OFF (30u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXFLASH_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxFlash_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxFlash_reg.h
new file mode 100644
index 0000000..a4a876b
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxFlash_reg.h
@@ -0,0 +1,282 @@
+/**
+ * \file IfxFlash_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Flash_Cfg Flash address
+ * \ingroup IfxLld_Flash
+ *
+ * \defgroup IfxLld_Flash_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Flash_Cfg
+ *
+ * \defgroup IfxLld_Flash_Cfg_Flash0 2-FLASH0
+ * \ingroup IfxLld_Flash_Cfg
+ *
+ */
+#ifndef IFXFLASH_REG_H
+#define IFXFLASH_REG_H 1
+/******************************************************************************/
+#include "IfxFlash_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Flash_Cfg_BaseAddress
+ * \{ */
+
+/** \brief FLASH object. */
+#define MODULE_FLASH0 /*lint --e(923)*/ (*(Ifx_FLASH*)0xF8001000u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Flash_Cfg_Flash0
+ * \{ */
+
+/** \brief 13FC, Access Enable Register 0 */
+#define FLASH0_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_ACCEN0*)0xF80023FCu)
+
+/** \brief 13F8, Access Enable Register 1 */
+#define FLASH0_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_FLASH_ACCEN1*)0xF80023F8u)
+
+/** \brief 10B4, CBAB Configuration */
+#define FLASH0_CBAB0_CFG /*lint --e(923)*/ (*(volatile Ifx_FLASH_CBAB_CFG*)0xF80020B4u)
+
+/** Alias (User Manual Name) for FLASH0_CBAB0_CFG.
+* To use register names with standard convension, please use FLASH0_CBAB0_CFG.
+*/
+#define FLASH0_CBABCFG0 (FLASH0_CBAB0_CFG)
+
+/** \brief 10B8, CBAB Status */
+#define FLASH0_CBAB0_STAT /*lint --e(923)*/ (*(volatile Ifx_FLASH_CBAB_STAT*)0xF80020B8u)
+
+/** Alias (User Manual Name) for FLASH0_CBAB0_STAT.
+* To use register names with standard convension, please use FLASH0_CBAB0_STAT.
+*/
+#define FLASH0_CBABSTAT0 (FLASH0_CBAB0_STAT)
+
+/** \brief 10BC, CBAB FIFO TOP Entry */
+#define FLASH0_CBAB0_TOP /*lint --e(923)*/ (*(volatile Ifx_FLASH_CBAB_TOP*)0xF80020BCu)
+
+/** Alias (User Manual Name) for FLASH0_CBAB0_TOP.
+* To use register names with standard convension, please use FLASH0_CBAB0_TOP.
+*/
+#define FLASH0_CBABTOP0 (FLASH0_CBAB0_TOP)
+
+/** \brief 10C0, CBAB Configuration */
+#define FLASH0_CBAB1_CFG /*lint --e(923)*/ (*(volatile Ifx_FLASH_CBAB_CFG*)0xF80020C0u)
+
+/** Alias (User Manual Name) for FLASH0_CBAB1_CFG.
+* To use register names with standard convension, please use FLASH0_CBAB1_CFG.
+*/
+#define FLASH0_CBABCFG1 (FLASH0_CBAB1_CFG)
+
+/** \brief 10C4, CBAB Status */
+#define FLASH0_CBAB1_STAT /*lint --e(923)*/ (*(volatile Ifx_FLASH_CBAB_STAT*)0xF80020C4u)
+
+/** Alias (User Manual Name) for FLASH0_CBAB1_STAT.
+* To use register names with standard convension, please use FLASH0_CBAB1_STAT.
+*/
+#define FLASH0_CBABSTAT1 (FLASH0_CBAB1_STAT)
+
+/** \brief 10C8, CBAB FIFO TOP Entry */
+#define FLASH0_CBAB1_TOP /*lint --e(923)*/ (*(volatile Ifx_FLASH_CBAB_TOP*)0xF80020C8u)
+
+/** Alias (User Manual Name) for FLASH0_CBAB1_TOP.
+* To use register names with standard convension, please use FLASH0_CBAB1_TOP.
+*/
+#define FLASH0_CBABTOP1 (FLASH0_CBAB1_TOP)
+
+/** \brief 0, FSI Communication Register 0 */
+#define FLASH0_COMM0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_COMM0*)0xF8001000u)
+
+/** \brief 4, FSI Communication Register 1 */
+#define FLASH0_COMM1 /*lint --e(923)*/ (*(volatile Ifx_FLASH_COMM1*)0xF8001004u)
+
+/** \brief 8, FSI Communication Register 2 */
+#define FLASH0_COMM2 /*lint --e(923)*/ (*(volatile Ifx_FLASH_COMM2*)0xF8001008u)
+
+/** \brief 10A4, ECC Read Register DF */
+#define FLASH0_ECCRD /*lint --e(923)*/ (*(volatile Ifx_FLASH_ECCRD*)0xF80020A4u)
+
+/** \brief 1094, ECC Read Register for ports */
+#define FLASH0_ECCRP0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_ECCRP*)0xF8002094u)
+
+/** \brief 1098, ECC Read Register for ports */
+#define FLASH0_ECCRP1 /*lint --e(923)*/ (*(volatile Ifx_FLASH_ECCRP*)0xF8002098u)
+
+/** \brief 1090, ECC Write Register */
+#define FLASH0_ECCW /*lint --e(923)*/ (*(volatile Ifx_FLASH_ECCW*)0xF8002090u)
+
+/** \brief 1014, Flash Configuration Register */
+#define FLASH0_FCON /*lint --e(923)*/ (*(volatile Ifx_FLASH_FCON*)0xF8002014u)
+
+/** \brief 101C, Flash Protection Control and Status Register */
+#define FLASH0_FPRO /*lint --e(923)*/ (*(volatile Ifx_FLASH_FPRO*)0xF800201Cu)
+
+/** \brief 1010, Flash Status Register */
+#define FLASH0_FSR /*lint --e(923)*/ (*(volatile Ifx_FLASH_FSR*)0xF8002010u)
+
+/** \brief 1008, Flash Module Identification Register */
+#define FLASH0_ID /*lint --e(923)*/ (*(volatile Ifx_FLASH_ID*)0xF8002008u)
+
+/** \brief 10AC, Margin Control Register DFlash */
+#define FLASH0_MARD /*lint --e(923)*/ (*(volatile Ifx_FLASH_MARD*)0xF80020ACu)
+
+/** \brief 10A8, Margin Control Register PFlash */
+#define FLASH0_MARP /*lint --e(923)*/ (*(volatile Ifx_FLASH_MARP*)0xF80020A8u)
+
+/** \brief 1030, DFlash Protection Configuration */
+#define FLASH0_PROCOND /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCOND*)0xF8002030u)
+
+/** \brief 1058, Debug Interface Protection Configuration */
+#define FLASH0_PROCONDBG /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCONDBG*)0xF8002058u)
+
+/** \brief 105C, HSM Interface Configuration */
+#define FLASH0_PROCONHSM /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCONHSM*)0xF800205Cu)
+
+/** \brief 1034, HSM Code Flash OTP Protection Configuration */
+#define FLASH0_PROCONHSMCOTP /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCONHSMCOTP*)0xF8002034u)
+
+/** \brief 1038, OTP Protection Configuration for ports */
+#define FLASH0_PROCONOTP0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCONOTP*)0xF8002038u)
+
+/** \brief 103C, OTP Protection Configuration for ports */
+#define FLASH0_PROCONOTP1 /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCONOTP*)0xF800203Cu)
+
+/** \brief 1020, PFlash Protection Configuration for ports */
+#define FLASH0_PROCONP0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCONP*)0xF8002020u)
+
+/** \brief 1024, PFlash Protection Configuration for ports */
+#define FLASH0_PROCONP1 /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCONP*)0xF8002024u)
+
+/** \brief 1048, Write-Once Protection Configuration for ports */
+#define FLASH0_PROCONWOP0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCONWOP*)0xF8002048u)
+
+/** \brief 104C, Write-Once Protection Configuration for ports */
+#define FLASH0_PROCONWOP1 /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCONWOP*)0xF800204Cu)
+
+/** \brief 1060, Read Buffer Cfg 0 */
+#define FLASH0_RDBCFG0_CFG0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_RDB_CFG0*)0xF8002060u)
+
+/** Alias (User Manual Name) for FLASH0_RDBCFG0_CFG0.
+* To use register names with standard convension, please use FLASH0_RDBCFG0_CFG0.
+*/
+#define FLASH0_RDBCFG00 (FLASH0_RDBCFG0_CFG0)
+
+/** \brief 1064, Read Buffer Cfg 1 */
+#define FLASH0_RDBCFG0_CFG1 /*lint --e(923)*/ (*(volatile Ifx_FLASH_RDB_CFG1*)0xF8002064u)
+
+/** Alias (User Manual Name) for FLASH0_RDBCFG0_CFG1.
+* To use register names with standard convension, please use FLASH0_RDBCFG0_CFG1.
+*/
+#define FLASH0_RDBCFG01 (FLASH0_RDBCFG0_CFG1)
+
+/** \brief 1068, Read Buffer Cfg 2 */
+#define FLASH0_RDBCFG0_CFG2 /*lint --e(923)*/ (*(volatile Ifx_FLASH_RDB_CFG2*)0xF8002068u)
+
+/** Alias (User Manual Name) for FLASH0_RDBCFG0_CFG2.
+* To use register names with standard convension, please use FLASH0_RDBCFG0_CFG2.
+*/
+#define FLASH0_RDBCFG02 (FLASH0_RDBCFG0_CFG2)
+
+/** \brief 106C, Read Buffer Cfg 0 */
+#define FLASH0_RDBCFG1_CFG0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_RDB_CFG0*)0xF800206Cu)
+
+/** Alias (User Manual Name) for FLASH0_RDBCFG1_CFG0.
+* To use register names with standard convension, please use FLASH0_RDBCFG1_CFG0.
+*/
+#define FLASH0_RDBCFG10 (FLASH0_RDBCFG1_CFG0)
+
+/** \brief 1070, Read Buffer Cfg 1 */
+#define FLASH0_RDBCFG1_CFG1 /*lint --e(923)*/ (*(volatile Ifx_FLASH_RDB_CFG1*)0xF8002070u)
+
+/** Alias (User Manual Name) for FLASH0_RDBCFG1_CFG1.
+* To use register names with standard convension, please use FLASH0_RDBCFG1_CFG1.
+*/
+#define FLASH0_RDBCFG11 (FLASH0_RDBCFG1_CFG1)
+
+/** \brief 1074, Read Buffer Cfg 2 */
+#define FLASH0_RDBCFG1_CFG2 /*lint --e(923)*/ (*(volatile Ifx_FLASH_RDB_CFG2*)0xF8002074u)
+
+/** Alias (User Manual Name) for FLASH0_RDBCFG1_CFG2.
+* To use register names with standard convension, please use FLASH0_RDBCFG1_CFG2.
+*/
+#define FLASH0_RDBCFG12 (FLASH0_RDBCFG1_CFG2)
+
+/** \brief 114C, Requested Read Address Register */
+#define FLASH0_RRAD /*lint --e(923)*/ (*(volatile Ifx_FLASH_RRAD*)0xF800214Cu)
+
+/** \brief 1140, Requested Read Control Register */
+#define FLASH0_RRCT /*lint --e(923)*/ (*(volatile Ifx_FLASH_RRCT*)0xF8002140u)
+
+/** \brief 1144, Requested Read Data Register 0 */
+#define FLASH0_RRD0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_RRD0*)0xF8002144u)
+
+/** \brief 1148, Requested Read Data Register 1 */
+#define FLASH0_RRD1 /*lint --e(923)*/ (*(volatile Ifx_FLASH_RRD1*)0xF8002148u)
+
+/** \brief 10E4, UBAB Configuration */
+#define FLASH0_UBAB0_CFG /*lint --e(923)*/ (*(volatile Ifx_FLASH_UBAB_CFG*)0xF80020E4u)
+
+/** Alias (User Manual Name) for FLASH0_UBAB0_CFG.
+* To use register names with standard convension, please use FLASH0_UBAB0_CFG.
+*/
+#define FLASH0_UBABCFG0 (FLASH0_UBAB0_CFG)
+
+/** \brief 10E8, UBAB Status */
+#define FLASH0_UBAB0_STAT /*lint --e(923)*/ (*(volatile Ifx_FLASH_UBAB_STAT*)0xF80020E8u)
+
+/** Alias (User Manual Name) for FLASH0_UBAB0_STAT.
+* To use register names with standard convension, please use FLASH0_UBAB0_STAT.
+*/
+#define FLASH0_UBABSTAT0 (FLASH0_UBAB0_STAT)
+
+/** \brief 10EC, UBAB FIFO TOP Entry */
+#define FLASH0_UBAB0_TOP /*lint --e(923)*/ (*(volatile Ifx_FLASH_UBAB_TOP*)0xF80020ECu)
+
+/** Alias (User Manual Name) for FLASH0_UBAB0_TOP.
+* To use register names with standard convension, please use FLASH0_UBAB0_TOP.
+*/
+#define FLASH0_UBABTOP0 (FLASH0_UBAB0_TOP)
+
+/** \brief 10F0, UBAB Configuration */
+#define FLASH0_UBAB1_CFG /*lint --e(923)*/ (*(volatile Ifx_FLASH_UBAB_CFG*)0xF80020F0u)
+
+/** Alias (User Manual Name) for FLASH0_UBAB1_CFG.
+* To use register names with standard convension, please use FLASH0_UBAB1_CFG.
+*/
+#define FLASH0_UBABCFG1 (FLASH0_UBAB1_CFG)
+
+/** \brief 10F4, UBAB Status */
+#define FLASH0_UBAB1_STAT /*lint --e(923)*/ (*(volatile Ifx_FLASH_UBAB_STAT*)0xF80020F4u)
+
+/** Alias (User Manual Name) for FLASH0_UBAB1_STAT.
+* To use register names with standard convension, please use FLASH0_UBAB1_STAT.
+*/
+#define FLASH0_UBABSTAT1 (FLASH0_UBAB1_STAT)
+
+/** \brief 10F8, UBAB FIFO TOP Entry */
+#define FLASH0_UBAB1_TOP /*lint --e(923)*/ (*(volatile Ifx_FLASH_UBAB_TOP*)0xF80020F8u)
+
+/** Alias (User Manual Name) for FLASH0_UBAB1_TOP.
+* To use register names with standard convension, please use FLASH0_UBAB1_TOP.
+*/
+#define FLASH0_UBABTOP1 (FLASH0_UBAB1_TOP)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXFLASH_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxFlash_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxFlash_regdef.h
new file mode 100644
index 0000000..c2eaaf8
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxFlash_regdef.h
@@ -0,0 +1,901 @@
+/**
+ * \file IfxFlash_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Flash Flash
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Flash_Bitfields Bitfields
+ * \ingroup IfxLld_Flash
+ *
+ * \defgroup IfxLld_Flash_union Union
+ * \ingroup IfxLld_Flash
+ *
+ * \defgroup IfxLld_Flash_struct Struct
+ * \ingroup IfxLld_Flash
+ *
+ */
+#ifndef IFXFLASH_REGDEF_H
+#define IFXFLASH_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Flash_Bitfields
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef struct _Ifx_FLASH_ACCEN0_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_FLASH_ACCEN0_Bits;
+
+/** \brief Access Enable Register 1 */
+typedef struct _Ifx_FLASH_ACCEN1_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_FLASH_ACCEN1_Bits;
+
+/** \brief CBAB Configuration */
+typedef struct _Ifx_FLASH_CBAB_CFG_Bits
+{
+ unsigned int SEL:6; /**< \brief [5:0] Select Bit-Errors (rw) */
+ unsigned int reserved_6:2; /**< \brief \internal Reserved */
+ unsigned int CLR:1; /**< \brief [8:8] Clear (w) */
+ unsigned int DIS:1; /**< \brief [9:9] Disable (rw) */
+ unsigned int reserved_10:22; /**< \brief \internal Reserved */
+} Ifx_FLASH_CBAB_CFG_Bits;
+
+/** \brief CBAB Status */
+typedef struct _Ifx_FLASH_CBAB_STAT_Bits
+{
+ unsigned int VLD0:1; /**< \brief [0:0] Filling Level (rh) */
+ unsigned int VLD1:1; /**< \brief [1:1] Filling Level (rh) */
+ unsigned int VLD2:1; /**< \brief [2:2] Filling Level (rh) */
+ unsigned int VLD3:1; /**< \brief [3:3] Filling Level (rh) */
+ unsigned int VLD4:1; /**< \brief [4:4] Filling Level (rh) */
+ unsigned int VLD5:1; /**< \brief [5:5] Filling Level (rh) */
+ unsigned int VLD6:1; /**< \brief [6:6] Filling Level (rh) */
+ unsigned int VLD7:1; /**< \brief [7:7] Filling Level (rh) */
+ unsigned int VLD8:1; /**< \brief [8:8] Filling Level (rh) */
+ unsigned int VLD9:1; /**< \brief [9:9] Filling Level (rh) */
+ unsigned int reserved_10:22; /**< \brief \internal Reserved */
+} Ifx_FLASH_CBAB_STAT_Bits;
+
+/** \brief CBAB FIFO TOP Entry */
+typedef struct _Ifx_FLASH_CBAB_TOP_Bits
+{
+ unsigned int reserved_0:5; /**< \brief \internal Reserved */
+ unsigned int ADDR:19; /**< \brief [23:5] Address (rh) */
+ unsigned int ERR:6; /**< \brief [29:24] Error Type (rh) */
+ unsigned int VLD:1; /**< \brief [30:30] Valid (rh) */
+ unsigned int CLR:1; /**< \brief [31:31] Clear (w) */
+} Ifx_FLASH_CBAB_TOP_Bits;
+
+/** \brief FSI Communication Register 0 */
+typedef struct _Ifx_FLASH_COMM0_Bits
+{
+ unsigned int STATUS:8; /**< \brief [7:0] Status (rh) */
+ unsigned int reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_FLASH_COMM0_Bits;
+
+/** \brief FSI Communication Register 1 */
+typedef struct _Ifx_FLASH_COMM1_Bits
+{
+ unsigned int STATUS:8; /**< \brief [7:0] Status (rh) */
+ unsigned int DATA:8; /**< \brief [15:8] Data (rwh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_FLASH_COMM1_Bits;
+
+/** \brief FSI Communication Register 2 */
+typedef struct _Ifx_FLASH_COMM2_Bits
+{
+ unsigned int STATUS:8; /**< \brief [7:0] Status (rh) */
+ unsigned int DATA:8; /**< \brief [15:8] Data (rwh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_FLASH_COMM2_Bits;
+
+/** \brief ECC Read Register DF */
+typedef struct _Ifx_FLASH_ECCRD_Bits
+{
+ unsigned int RCODE:22; /**< \brief [21:0] Error Correction Read Code (rh) */
+ unsigned int reserved_22:8; /**< \brief \internal Reserved */
+ unsigned int EDCERRINJ:1; /**< \brief [30:30] EDC Error Injection (rw) */
+ unsigned int ECCORDIS:1; /**< \brief [31:31] ECC Correction Disable (rw) */
+} Ifx_FLASH_ECCRD_Bits;
+
+/** \brief ECC Read Register */
+typedef struct _Ifx_FLASH_ECCRP_Bits
+{
+ unsigned int RCODE:22; /**< \brief [21:0] Error Correction Read Code (rh) */
+ unsigned int reserved_22:8; /**< \brief \internal Reserved */
+ unsigned int EDCERRINJ:1; /**< \brief [30:30] EDC Error Injection (rw) */
+ unsigned int ECCORDIS:1; /**< \brief [31:31] ECC Correction Disable (rw) */
+} Ifx_FLASH_ECCRP_Bits;
+
+/** \brief ECC Write Register */
+typedef struct _Ifx_FLASH_ECCW_Bits
+{
+ unsigned int WCODE:22; /**< \brief [21:0] Error Correction Write Code (rw) */
+ unsigned int reserved_22:8; /**< \brief \internal Reserved */
+ unsigned int DECENCDIS:1; /**< \brief [30:30] DF_EEPROM ECC Encoding Disable (rw) */
+ unsigned int PECENCDIS:1; /**< \brief [31:31] PFlash ECC Encoding Disable (rw) */
+} Ifx_FLASH_ECCW_Bits;
+
+/** \brief Flash Configuration Register */
+typedef struct _Ifx_FLASH_FCON_Bits
+{
+ unsigned int WSPFLASH:4; /**< \brief [3:0] Wait States for read access to PFlash (rw) */
+ unsigned int WSECPF:2; /**< \brief [5:4] Wait States for Error Correction of PFlash (rw) */
+ unsigned int WSDFLASH:6; /**< \brief [11:6] Wait States for read access to DFlash (rw) */
+ unsigned int WSECDF:3; /**< \brief [14:12] Wait State for Error Correction of DFlash (rw) */
+ unsigned int IDLE:1; /**< \brief [15:15] Dynamic Flash Idle (rw) */
+ unsigned int ESLDIS:1; /**< \brief [16:16] External Sleep Request Disable (rw) */
+ unsigned int SLEEP:1; /**< \brief [17:17] Flash SLEEP (rw) */
+ unsigned int NSAFECC:1; /**< \brief [18:18] Non-Safety PFlash ECC (rw) */
+ unsigned int STALL:1; /**< \brief [19:19] Stall SRI (rw) */
+ unsigned int RES21:2; /**< \brief [21:20] Reserved (rh) */
+ unsigned int RES23:2; /**< \brief [23:22] Reserved (rh) */
+ unsigned int VOPERM:1; /**< \brief [24:24] Verify and Operation Error Interrupt Mask (rw) */
+ unsigned int SQERM:1; /**< \brief [25:25] Command Sequence Error Interrupt Mask (rw) */
+ unsigned int PROERM:1; /**< \brief [26:26] Protection Error Interrupt Mask (rw) */
+ unsigned int reserved_27:3; /**< \brief \internal Reserved */
+ unsigned int PR5V:1; /**< \brief [30:30] Programming Supply 5V (rw) */
+ unsigned int EOBM:1; /**< \brief [31:31] End of Busy Interrupt Mask (rw) */
+} Ifx_FLASH_FCON_Bits;
+
+/** \brief Flash Protection Control and Status Register */
+typedef struct _Ifx_FLASH_FPRO_Bits
+{
+ unsigned int PROINP:1; /**< \brief [0:0] PFlash Protection (rh) */
+ unsigned int PRODISP:1; /**< \brief [1:1] PFlash Protection Disabled (rh) */
+ unsigned int PROIND:1; /**< \brief [2:2] DFlash Protection (rh) */
+ unsigned int PRODISD:1; /**< \brief [3:3] DFlash Protection Disabled (rh) */
+ unsigned int PROINHSMCOTP:1; /**< \brief [4:4] HSM OTP Protection (rh) */
+ unsigned int RES5:1; /**< \brief [5:5] Reserved (rh) */
+ unsigned int PROINOTP:1; /**< \brief [6:6] OTP and Write-Once Protection (rh) */
+ unsigned int RES7:1; /**< \brief [7:7] Reserved (rh) */
+ unsigned int PROINDBG:1; /**< \brief [8:8] Debug Interface Password Protection (rh) */
+ unsigned int PRODISDBG:1; /**< \brief [9:9] Debug Interface Password Protection Disabled (rh) */
+ unsigned int PROINHSM:1; /**< \brief [10:10] HSM Configuration (rh) */
+ unsigned int reserved_11:5; /**< \brief \internal Reserved */
+ unsigned int DCFP:1; /**< \brief [16:16] Disable Code Fetch from PFlash Memory for CPU0 PMI (rwh) */
+ unsigned int DDFP:1; /**< \brief [17:17] Disable Read from PFlash for CPU0 DMI (rwh) */
+ unsigned int DDFPX:1; /**< \brief [18:18] Disable Read from PFlash for Other Masters (rwh) */
+ unsigned int reserved_19:1; /**< \brief \internal Reserved */
+ unsigned int DDFD:1; /**< \brief [20:20] Disable Data Fetch from DFlash Memory (rwh) */
+ unsigned int reserved_21:1; /**< \brief \internal Reserved */
+ unsigned int ENPE:2; /**< \brief [23:22] Enable Program/Erase (rw) */
+ unsigned int reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_FLASH_FPRO_Bits;
+
+/** \brief Flash Status Register */
+typedef struct _Ifx_FLASH_FSR_Bits
+{
+ unsigned int FABUSY:1; /**< \brief [0:0] Flash Array Busy (rh) */
+ unsigned int D0BUSY:1; /**< \brief [1:1] Data Flash Bank 0 Busy (rh) */
+ unsigned int RES1:1; /**< \brief [2:2] Reserved for Data Flash Bank 1 Busy (rh) */
+ unsigned int P0BUSY:1; /**< \brief [3:3] Program Flash PF0 Busy (rh) */
+ unsigned int P1BUSY:1; /**< \brief [4:4] Program Flash PF1 Busy (rh) */
+ unsigned int RES5:1; /**< \brief [5:5] Reserved for Program Flash PF2 Busy (rh) */
+ unsigned int RES6:1; /**< \brief [6:6] Reserved for Program Flash PF3 Busy (rh) */
+ unsigned int PROG:1; /**< \brief [7:7] Programming State (rwh) */
+ unsigned int ERASE:1; /**< \brief [8:8] Erase State (rwh) */
+ unsigned int PFPAGE:1; /**< \brief [9:9] Program Flash in Page Mode (rh) */
+ unsigned int DFPAGE:1; /**< \brief [10:10] Data Flash in Page Mode (rh) */
+ unsigned int OPER:1; /**< \brief [11:11] Flash Operation Error (rwh) */
+ unsigned int SQER:1; /**< \brief [12:12] Command Sequence Error (rwh) */
+ unsigned int PROER:1; /**< \brief [13:13] Protection Error (rwh) */
+ unsigned int PFSBER:1; /**< \brief [14:14] PFlash Single-Bit Error and Correction (rwh) */
+ unsigned int PFDBER:1; /**< \brief [15:15] PFlash Double-Bit Error (rwh) */
+ unsigned int PFMBER:1; /**< \brief [16:16] PFlash Uncorrectable Error (rwh) */
+ unsigned int RES17:1; /**< \brief [17:17] Reserved (rwh) */
+ unsigned int DFSBER:1; /**< \brief [18:18] DFlash Single-Bit Error (rwh) */
+ unsigned int DFDBER:1; /**< \brief [19:19] DFlash Double-Bit Error (rwh) */
+ unsigned int DFTBER:1; /**< \brief [20:20] DFlash Triple-Bit Error (rwh) */
+ unsigned int DFMBER:1; /**< \brief [21:21] DFlash Uncorrectable Error (rwh) */
+ unsigned int SRIADDERR:1; /**< \brief [22:22] SRI Bus Address ECC Error (rwh) */
+ unsigned int reserved_23:2; /**< \brief \internal Reserved */
+ unsigned int PVER:1; /**< \brief [25:25] Program Verify Error (rwh) */
+ unsigned int EVER:1; /**< \brief [26:26] Erase Verify Error (rwh) */
+ unsigned int SPND:1; /**< \brief [27:27] Operation Suspended (rwh) */
+ unsigned int SLM:1; /**< \brief [28:28] Flash Sleep Mode (rh) */
+ unsigned int reserved_29:1; /**< \brief \internal Reserved */
+ unsigned int ORIER:1; /**< \brief [30:30] Original Error (rh) */
+ unsigned int reserved_31:1; /**< \brief \internal Reserved */
+} Ifx_FLASH_FSR_Bits;
+
+/** \brief Flash Module Identification Register */
+typedef struct _Ifx_FLASH_ID_Bits
+{
+ unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
+ unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_FLASH_ID_Bits;
+
+/** \brief Margin Control Register DFlash */
+typedef struct _Ifx_FLASH_MARD_Bits
+{
+ unsigned int HMARGIN:1; /**< \brief [0:0] Hard Margin Selection (rw) */
+ unsigned int SELD0:1; /**< \brief [1:1] DFLASH Bank Selection (rw) */
+ unsigned int reserved_2:1; /**< \brief \internal Reserved */
+ unsigned int SPND:1; /**< \brief [3:3] Suspend (rwh) */
+ unsigned int SPNDERR:1; /**< \brief [4:4] Suspend Error (rwh) */
+ unsigned int reserved_5:10; /**< \brief \internal Reserved */
+ unsigned int TRAPDIS:1; /**< \brief [15:15] DFLASH Uncorrectable Bit Error Trap Disable (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_FLASH_MARD_Bits;
+
+/** \brief Margin Control Register PFlash */
+typedef struct _Ifx_FLASH_MARP_Bits
+{
+ unsigned int SELP0:1; /**< \brief [0:0] PFLASH Bank PF0 Selection (rw) */
+ unsigned int SELP1:1; /**< \brief [1:1] PFLASH Bank PF1 Selection (rw) */
+ unsigned int RES2:1; /**< \brief [2:2] Reserved (rw) */
+ unsigned int RES3:1; /**< \brief [3:3] Reserved (rw) */
+ unsigned int reserved_4:11; /**< \brief \internal Reserved */
+ unsigned int TRAPDIS:1; /**< \brief [15:15] PFLASH Uncorrectable Bit Error Trap Disable (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_FLASH_MARP_Bits;
+
+/** \brief DFlash Protection Configuration */
+typedef struct _Ifx_FLASH_PROCOND_Bits
+{
+ unsigned int L:1; /**< \brief [0:0] DF_EEPROM Locked for Write Protection (rh) */
+ unsigned int NSAFECC:1; /**< \brief [1:1] Non-Safety PFlash ECC (rh) */
+ unsigned int RAMIN:2; /**< \brief [3:2] RAM Initialization by SSW Control (rh) */
+ unsigned int RAMINSEL:4; /**< \brief [7:4] RAM Initialization Selection (rh) */
+ unsigned int OSCCFG:1; /**< \brief [8:8] OSC Configuration by SSW (rh) */
+ unsigned int MODE:2; /**< \brief [10:9] OSC Mode (rh) */
+ unsigned int APREN:1; /**< \brief [11:11] OSC Amplitude Regulation Enable (rh) */
+ unsigned int CAP0EN:1; /**< \brief [12:12] OSC Capacitance 0 Enable (rh) */
+ unsigned int CAP1EN:1; /**< \brief [13:13] OSC Capacitance 1 Enable (rh) */
+ unsigned int CAP2EN:1; /**< \brief [14:14] OSC Capacitance 2 Enable (rh) */
+ unsigned int CAP3EN:1; /**< \brief [15:15] OSC Capacitance 3 Enable (rh) */
+ unsigned int ESR0CNT:12; /**< \brief [27:16] ESR0 Prolongation Counter (rh) */
+ unsigned int RES29:2; /**< \brief [29:28] Reserved (rh) */
+ unsigned int RES30:1; /**< \brief [30:30] Reserved (rh) */
+ unsigned int RPRO:1; /**< \brief [31:31] Read Protection Configuration (rh) */
+} Ifx_FLASH_PROCOND_Bits;
+
+/** \brief Debug Interface Protection Configuration */
+typedef struct _Ifx_FLASH_PROCONDBG_Bits
+{
+ unsigned int OCDSDIS:1; /**< \brief [0:0] OCDS Disabled (rh) */
+ unsigned int DBGIFLCK:1; /**< \brief [1:1] Debug Interface Locked (rh) */
+ unsigned int EDM:2; /**< \brief [3:2] Entered Debug Mode (rh) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_FLASH_PROCONDBG_Bits;
+
+/** \brief HSM Interface Configuration */
+typedef struct _Ifx_FLASH_PROCONHSM_Bits
+{
+ unsigned int HSMDBGDIS:1; /**< \brief [0:0] HSM Debug Disable (rh) */
+ unsigned int DBGIFLCK:1; /**< \brief [1:1] Debug Interface Locked (rh) */
+ unsigned int TSTIFLCK:1; /**< \brief [2:2] Test Interface Locked (rh) */
+ unsigned int HSMTSTDIS:1; /**< \brief [3:3] HSM Test Disable (rh) */
+ unsigned int RES15:12; /**< \brief [15:4] Reserved (rh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_FLASH_PROCONHSM_Bits;
+
+/** \brief HSM Code Flash OTP Protection Configuration */
+typedef struct _Ifx_FLASH_PROCONHSMCOTP_Bits
+{
+ unsigned int HSMBOOTEN:1; /**< \brief [0:0] HSM Boot Enable (rh) */
+ unsigned int SSWWAIT:1; /**< \brief [1:1] SSW Wait (rh) */
+ unsigned int HSMDX:1; /**< \brief [2:2] HSM Data Sectors Exclusive (rh) */
+ unsigned int HSM6X:1; /**< \brief [3:3] HSM Code Sector 6 Exclusive (rh) */
+ unsigned int HSM16X:1; /**< \brief [4:4] HSM Code Sector 16 Exclusive (rh) */
+ unsigned int HSM17X:1; /**< \brief [5:5] HSM Code Sector 17 Exclusive (rh) */
+ unsigned int S6ROM:1; /**< \brief [6:6] HSM Code Sector 6 Locked Forever (rh) */
+ unsigned int HSMENPINS:2; /**< \brief [8:7] Enable HSM Forcing of Pins HSM1/2 (rh) */
+ unsigned int HSMENRES:2; /**< \brief [10:9] Enable HSM Triggering Resets (rh) */
+ unsigned int DESTDBG:2; /**< \brief [12:11] Destructive Debug Entry (rh) */
+ unsigned int BLKFLAN:1; /**< \brief [13:13] Block Flash Analysis (rh) */
+ unsigned int reserved_14:2; /**< \brief \internal Reserved */
+ unsigned int S16ROM:1; /**< \brief [16:16] HSM Code Sector 16 Locked Forever (rh) */
+ unsigned int S17ROM:1; /**< \brief [17:17] HSM Code Sector 17 Locked Forever (rh) */
+ unsigned int reserved_18:14; /**< \brief \internal Reserved */
+} Ifx_FLASH_PROCONHSMCOTP_Bits;
+
+/** \brief OTP Protection Configuration */
+typedef struct _Ifx_FLASH_PROCONOTP_Bits
+{
+ unsigned int S0ROM:1; /**< \brief [0:0] PFlash p Sector 0 Locked Forever (rh) */
+ unsigned int S1ROM:1; /**< \brief [1:1] PFlash p Sector 1 Locked Forever (rh) */
+ unsigned int S2ROM:1; /**< \brief [2:2] PFlash p Sector 2 Locked Forever (rh) */
+ unsigned int S3ROM:1; /**< \brief [3:3] PFlash p Sector 3 Locked Forever (rh) */
+ unsigned int S4ROM:1; /**< \brief [4:4] PFlash p Sector 4 Locked Forever (rh) */
+ unsigned int S5ROM:1; /**< \brief [5:5] PFlash p Sector 5 Locked Forever (rh) */
+ unsigned int S6ROM:1; /**< \brief [6:6] PFlash p Sector 6 Locked Forever (rh) */
+ unsigned int S7ROM:1; /**< \brief [7:7] PFlash p Sector 7 Locked Forever (rh) */
+ unsigned int S8ROM:1; /**< \brief [8:8] PFlash p Sector 8 Locked Forever (rh) */
+ unsigned int S9ROM:1; /**< \brief [9:9] PFlash p Sector 9 Locked Forever (rh) */
+ unsigned int S10ROM:1; /**< \brief [10:10] PFlash p Sector 10 Locked Forever (rh) */
+ unsigned int S11ROM:1; /**< \brief [11:11] PFlash p Sector 11 Locked Forever (rh) */
+ unsigned int S12ROM:1; /**< \brief [12:12] PFlash p Sector 12 Locked Forever (rh) */
+ unsigned int S13ROM:1; /**< \brief [13:13] PFlash p Sector 13 Locked Forever (rh) */
+ unsigned int S14ROM:1; /**< \brief [14:14] PFlash p Sector 14 Locked Forever (rh) */
+ unsigned int S15ROM:1; /**< \brief [15:15] PFlash p Sector 15 Locked Forever (rh) */
+ unsigned int S16ROM:1; /**< \brief [16:16] PFlash p Sector 16 Locked Forever (rh) */
+ unsigned int S17ROM:1; /**< \brief [17:17] PFlash p Sector 17 Locked Forever (rh) */
+ unsigned int S18ROM:1; /**< \brief [18:18] PFlash p Sector 18 Locked Forever (rh) */
+ unsigned int S19ROM:1; /**< \brief [19:19] PFlash p Sector 19 Locked Forever (rh) */
+ unsigned int S20ROM:1; /**< \brief [20:20] PFlash p Sector 20 Locked Forever (rh) */
+ unsigned int S21ROM:1; /**< \brief [21:21] PFlash p Sector 21 Locked Forever (rh) */
+ unsigned int S22ROM:1; /**< \brief [22:22] PFlash p Sector 22 Locked Forever (rh) */
+ unsigned int S23ROM:1; /**< \brief [23:23] PFlash p Sector 23 Locked Forever (rh) */
+ unsigned int S24ROM:1; /**< \brief [24:24] PFlash p Sector 24 Locked Forever (rh) */
+ unsigned int S25ROM:1; /**< \brief [25:25] PFlash p Sector 25 Locked Forever (rh) */
+ unsigned int S26ROM:1; /**< \brief [26:26] PFlash p Sector 26 Locked Forever (rh) */
+ unsigned int reserved_27:2; /**< \brief \internal Reserved */
+ unsigned int BML:2; /**< \brief [30:29] Boot Mode Lock (rh) */
+ unsigned int TP:1; /**< \brief [31:31] Tuning Protection (rh) */
+} Ifx_FLASH_PROCONOTP_Bits;
+
+/** \brief PFlash Protection Configuration */
+typedef struct _Ifx_FLASH_PROCONP_Bits
+{
+ unsigned int S0L:1; /**< \brief [0:0] PFlash p Sector 0 Locked for Write Protection (rh) */
+ unsigned int S1L:1; /**< \brief [1:1] PFlash p Sector 1 Locked for Write Protection (rh) */
+ unsigned int S2L:1; /**< \brief [2:2] PFlash p Sector 2 Locked for Write Protection (rh) */
+ unsigned int S3L:1; /**< \brief [3:3] PFlash p Sector 3 Locked for Write Protection (rh) */
+ unsigned int S4L:1; /**< \brief [4:4] PFlash p Sector 4 Locked for Write Protection (rh) */
+ unsigned int S5L:1; /**< \brief [5:5] PFlash p Sector 5 Locked for Write Protection (rh) */
+ unsigned int S6L:1; /**< \brief [6:6] PFlash p Sector 6 Locked for Write Protection (rh) */
+ unsigned int S7L:1; /**< \brief [7:7] PFlash p Sector 7 Locked for Write Protection (rh) */
+ unsigned int S8L:1; /**< \brief [8:8] PFlash p Sector 8 Locked for Write Protection (rh) */
+ unsigned int S9L:1; /**< \brief [9:9] PFlash p Sector 9 Locked for Write Protection (rh) */
+ unsigned int S10L:1; /**< \brief [10:10] PFlash p Sector 10 Locked for Write Protection (rh) */
+ unsigned int S11L:1; /**< \brief [11:11] PFlash p Sector 11 Locked for Write Protection (rh) */
+ unsigned int S12L:1; /**< \brief [12:12] PFlash p Sector 12 Locked for Write Protection (rh) */
+ unsigned int S13L:1; /**< \brief [13:13] PFlash p Sector 13 Locked for Write Protection (rh) */
+ unsigned int S14L:1; /**< \brief [14:14] PFlash p Sector 14 Locked for Write Protection (rh) */
+ unsigned int S15L:1; /**< \brief [15:15] PFlash p Sector 15 Locked for Write Protection (rh) */
+ unsigned int S16L:1; /**< \brief [16:16] PFlash p Sector 16 Locked for Write Protection (rh) */
+ unsigned int S17L:1; /**< \brief [17:17] PFlash p Sector 17 Locked for Write Protection (rh) */
+ unsigned int S18L:1; /**< \brief [18:18] PFlash p Sector 18 Locked for Write Protection (rh) */
+ unsigned int S19L:1; /**< \brief [19:19] PFlash p Sector 19 Locked for Write Protection (rh) */
+ unsigned int S20L:1; /**< \brief [20:20] PFlash p Sector 20 Locked for Write Protection (rh) */
+ unsigned int S21L:1; /**< \brief [21:21] PFlash p Sector 21 Locked for Write Protection (rh) */
+ unsigned int S22L:1; /**< \brief [22:22] PFlash p Sector 22 Locked for Write Protection (rh) */
+ unsigned int S23L:1; /**< \brief [23:23] PFlash p Sector 23 Locked for Write Protection (rh) */
+ unsigned int S24L:1; /**< \brief [24:24] PFlash p Sector 24 Locked for Write Protection (rh) */
+ unsigned int S25L:1; /**< \brief [25:25] PFlash p Sector 25 Locked for Write Protection (rh) */
+ unsigned int S26L:1; /**< \brief [26:26] PFlash p Sector 26 Locked for Write Protection (rh) */
+ unsigned int reserved_27:4; /**< \brief \internal Reserved */
+ unsigned int RPRO:1; /**< \brief [31:31] Read Protection Configuration (rh) */
+} Ifx_FLASH_PROCONP_Bits;
+
+/** \brief Write-Once Protection Configuration */
+typedef struct _Ifx_FLASH_PROCONWOP_Bits
+{
+ unsigned int S0WOP:1; /**< \brief [0:0] PFlash p Sector 0 Configured for Write-Once Protection (rh) */
+ unsigned int S1WOP:1; /**< \brief [1:1] PFlash p Sector 1 Configured for Write-Once Protection (rh) */
+ unsigned int S2WOP:1; /**< \brief [2:2] PFlash p Sector 2 Configured for Write-Once Protection (rh) */
+ unsigned int S3WOP:1; /**< \brief [3:3] PFlash p Sector 3 Configured for Write-Once Protection (rh) */
+ unsigned int S4WOP:1; /**< \brief [4:4] PFlash p Sector 4 Configured for Write-Once Protection (rh) */
+ unsigned int S5WOP:1; /**< \brief [5:5] PFlash p Sector 5 Configured for Write-Once Protection (rh) */
+ unsigned int S6WOP:1; /**< \brief [6:6] PFlash p Sector 6 Configured for Write-Once Protection (rh) */
+ unsigned int S7WOP:1; /**< \brief [7:7] PFlash p Sector 7 Configured for Write-Once Protection (rh) */
+ unsigned int S8WOP:1; /**< \brief [8:8] PFlash p Sector 8 Configured for Write-Once Protection (rh) */
+ unsigned int S9WOP:1; /**< \brief [9:9] PFlash p Sector 9 Configured for Write-Once Protection (rh) */
+ unsigned int S10WOP:1; /**< \brief [10:10] PFlash p Sector 10 Configured for Write-Once Protection (rh) */
+ unsigned int S11WOP:1; /**< \brief [11:11] PFlash p Sector 11 Configured for Write-Once Protection (rh) */
+ unsigned int S12WOP:1; /**< \brief [12:12] PFlash p Sector 12 Configured for Write-Once Protection (rh) */
+ unsigned int S13WOP:1; /**< \brief [13:13] PFlash p Sector 13 Configured for Write-Once Protection (rh) */
+ unsigned int S14WOP:1; /**< \brief [14:14] PFlash p Sector 14 Configured for Write-Once Protection (rh) */
+ unsigned int S15WOP:1; /**< \brief [15:15] PFlash p Sector 15 Configured for Write-Once Protection (rh) */
+ unsigned int S16WOP:1; /**< \brief [16:16] PFlash p Sector 16 Configured for Write-Once Protection (rh) */
+ unsigned int S17WOP:1; /**< \brief [17:17] PFlash p Sector 17 Configured for Write-Once Protection (rh) */
+ unsigned int S18WOP:1; /**< \brief [18:18] PFlash p Sector 18 Configured for Write-Once Protection (rh) */
+ unsigned int S19WOP:1; /**< \brief [19:19] PFlash p Sector 19 Configured for Write-Once Protection (rh) */
+ unsigned int S20WOP:1; /**< \brief [20:20] PFlash p Sector 20 Configured for Write-Once Protection (rh) */
+ unsigned int S21WOP:1; /**< \brief [21:21] PFlash p Sector 21 Configured for Write-Once Protection (rh) */
+ unsigned int S22WOP:1; /**< \brief [22:22] PFlash p Sector 22 Configured for Write-Once Protection (rh) */
+ unsigned int S23WOP:1; /**< \brief [23:23] PFlash p Sector 23 Configured for Write-Once Protection (rh) */
+ unsigned int S24WOP:1; /**< \brief [24:24] PFlash p Sector 24 Configured for Write-Once Protection (rh) */
+ unsigned int S25WOP:1; /**< \brief [25:25] PFlash p Sector 25 Configured for Write-Once Protection (rh) */
+ unsigned int S26WOP:1; /**< \brief [26:26] PFlash p Sector 26 Configured for Write-Once Protection (rh) */
+ unsigned int reserved_27:4; /**< \brief \internal Reserved */
+ unsigned int DATM:1; /**< \brief [31:31] Disable ATM (rh) */
+} Ifx_FLASH_PROCONWOP_Bits;
+
+/** \brief Read Buffer Cfg 0 */
+typedef struct _Ifx_FLASH_RDB_CFG0_Bits
+{
+ unsigned int TAG:6; /**< \brief [5:0] Master Tag (rw) */
+ unsigned int reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_FLASH_RDB_CFG0_Bits;
+
+/** \brief Read Buffer Cfg 1 */
+typedef struct _Ifx_FLASH_RDB_CFG1_Bits
+{
+ unsigned int TAG:6; /**< \brief [5:0] Master Tag (rw) */
+ unsigned int reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_FLASH_RDB_CFG1_Bits;
+
+/** \brief Read Buffer Cfg 2 */
+typedef struct _Ifx_FLASH_RDB_CFG2_Bits
+{
+ unsigned int TAG:6; /**< \brief [5:0] Master Tag (rw) */
+ unsigned int reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_FLASH_RDB_CFG2_Bits;
+
+/** \brief Requested Read Address Register */
+typedef struct _Ifx_FLASH_RRAD_Bits
+{
+ unsigned int reserved_0:3; /**< \brief \internal Reserved */
+ unsigned int ADD:29; /**< \brief [31:3] Address (rwh) */
+} Ifx_FLASH_RRAD_Bits;
+
+/** \brief Requested Read Control Register */
+typedef struct _Ifx_FLASH_RRCT_Bits
+{
+ unsigned int STRT:1; /**< \brief [0:0] Start Request (rwh) */
+ unsigned int STP:1; /**< \brief [1:1] Stop (w) */
+ unsigned int BUSY:1; /**< \brief [2:2] Flash Read Busy (rh) */
+ unsigned int DONE:1; /**< \brief [3:3] Flash Read Done (rh) */
+ unsigned int ERR:1; /**< \brief [4:4] Error (rh) */
+ unsigned int reserved_5:3; /**< \brief \internal Reserved */
+ unsigned int EOBM:1; /**< \brief [8:8] End of Busy Interrupt Mask (rw) */
+ unsigned int reserved_9:7; /**< \brief \internal Reserved */
+ unsigned int CNT:16; /**< \brief [31:16] Count (rwh) */
+} Ifx_FLASH_RRCT_Bits;
+
+/** \brief Requested Read Data Register 0 */
+typedef struct _Ifx_FLASH_RRD0_Bits
+{
+ unsigned int DATA:32; /**< \brief [31:0] Read Data (rh) */
+} Ifx_FLASH_RRD0_Bits;
+
+/** \brief Requested Read Data Register 1 */
+typedef struct _Ifx_FLASH_RRD1_Bits
+{
+ unsigned int DATA:32; /**< \brief [31:0] Read Data (rh) */
+} Ifx_FLASH_RRD1_Bits;
+
+/** \brief UBAB Configuration */
+typedef struct _Ifx_FLASH_UBAB_CFG_Bits
+{
+ unsigned int SEL:6; /**< \brief [5:0] Select Bit-Errors (rw) */
+ unsigned int reserved_6:2; /**< \brief \internal Reserved */
+ unsigned int CLR:1; /**< \brief [8:8] Clear (w) */
+ unsigned int DIS:1; /**< \brief [9:9] Disable (rw) */
+ unsigned int reserved_10:22; /**< \brief \internal Reserved */
+} Ifx_FLASH_UBAB_CFG_Bits;
+
+/** \brief UBAB Status */
+typedef struct _Ifx_FLASH_UBAB_STAT_Bits
+{
+ unsigned int VLD0:1; /**< \brief [0:0] Filling Level (rh) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_FLASH_UBAB_STAT_Bits;
+
+/** \brief UBAB FIFO TOP Entry */
+typedef struct _Ifx_FLASH_UBAB_TOP_Bits
+{
+ unsigned int reserved_0:5; /**< \brief \internal Reserved */
+ unsigned int ADDR:19; /**< \brief [23:5] Address (rh) */
+ unsigned int ERR:6; /**< \brief [29:24] Error Type (rh) */
+ unsigned int VLD:1; /**< \brief [30:30] Valid (rh) */
+ unsigned int CLR:1; /**< \brief [31:31] Clear (w) */
+} Ifx_FLASH_UBAB_TOP_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Flash_union
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_ACCEN0_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_ACCEN0;
+
+/** \brief Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_ACCEN1_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_ACCEN1;
+
+/** \brief CBAB Configuration */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_CBAB_CFG_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_CBAB_CFG;
+
+/** \brief CBAB Status */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_CBAB_STAT_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_CBAB_STAT;
+
+/** \brief CBAB FIFO TOP Entry */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_CBAB_TOP_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_CBAB_TOP;
+
+/** \brief FSI Communication Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_COMM0_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_COMM0;
+
+/** \brief FSI Communication Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_COMM1_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_COMM1;
+
+/** \brief FSI Communication Register 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_COMM2_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_COMM2;
+
+/** \brief ECC Read Register DF */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_ECCRD_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_ECCRD;
+
+/** \brief ECC Read Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_ECCRP_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_ECCRP;
+
+/** \brief ECC Write Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_ECCW_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_ECCW;
+
+/** \brief Flash Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_FCON_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_FCON;
+
+/** \brief Flash Protection Control and Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_FPRO_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_FPRO;
+
+/** \brief Flash Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_FSR_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_FSR;
+
+/** \brief Flash Module Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_ID;
+
+/** \brief Margin Control Register DFlash */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_MARD_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_MARD;
+
+/** \brief Margin Control Register PFlash */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_MARP_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_MARP;
+
+/** \brief DFlash Protection Configuration */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_PROCOND_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_PROCOND;
+
+/** \brief Debug Interface Protection Configuration */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_PROCONDBG_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_PROCONDBG;
+
+/** \brief HSM Interface Configuration */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_PROCONHSM_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_PROCONHSM;
+
+/** \brief HSM Code Flash OTP Protection Configuration */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_PROCONHSMCOTP_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_PROCONHSMCOTP;
+
+/** \brief OTP Protection Configuration */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_PROCONOTP_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_PROCONOTP;
+
+/** \brief PFlash Protection Configuration */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_PROCONP_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_PROCONP;
+
+/** \brief Write-Once Protection Configuration */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_PROCONWOP_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_PROCONWOP;
+
+/** \brief Read Buffer Cfg 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_RDB_CFG0_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_RDB_CFG0;
+
+/** \brief Read Buffer Cfg 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_RDB_CFG1_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_RDB_CFG1;
+
+/** \brief Read Buffer Cfg 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_RDB_CFG2_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_RDB_CFG2;
+
+/** \brief Requested Read Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_RRAD_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_RRAD;
+
+/** \brief Requested Read Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_RRCT_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_RRCT;
+
+/** \brief Requested Read Data Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_RRD0_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_RRD0;
+
+/** \brief Requested Read Data Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_RRD1_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_RRD1;
+
+/** \brief UBAB Configuration */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_UBAB_CFG_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_UBAB_CFG;
+
+/** \brief UBAB Status */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_UBAB_STAT_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_UBAB_STAT;
+
+/** \brief UBAB FIFO TOP Entry */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_FLASH_UBAB_TOP_Bits B; /**< \brief Bitfield access */
+} Ifx_FLASH_UBAB_TOP;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Flash_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L1
+ * \{ */
+
+/** \brief Corrected Bits Address Buffer (CBAB) object */
+typedef volatile struct _Ifx_FLASH_CBAB
+{
+ Ifx_FLASH_CBAB_CFG CFG; /**< \brief 0, CBAB Configuration */
+ Ifx_FLASH_CBAB_STAT STAT; /**< \brief 4, CBAB Status */
+ Ifx_FLASH_CBAB_TOP TOP; /**< \brief 8, CBAB FIFO TOP Entry */
+} Ifx_FLASH_CBAB;
+
+/** \brief Read Buffer Configuration object */
+typedef volatile struct _Ifx_FLASH_RDB
+{
+ Ifx_FLASH_RDB_CFG0 CFG0; /**< \brief 0, Read Buffer Cfg 0 */
+ Ifx_FLASH_RDB_CFG1 CFG1; /**< \brief 4, Read Buffer Cfg 1 */
+ Ifx_FLASH_RDB_CFG2 CFG2; /**< \brief 8, Read Buffer Cfg 2 */
+} Ifx_FLASH_RDB;
+
+/** \brief Uncorrectable Bits Address Buffer (UBAB) object */
+typedef volatile struct _Ifx_FLASH_UBAB
+{
+ Ifx_FLASH_UBAB_CFG CFG; /**< \brief 0, UBAB Configuration */
+ Ifx_FLASH_UBAB_STAT STAT; /**< \brief 4, UBAB Status */
+ Ifx_FLASH_UBAB_TOP TOP; /**< \brief 8, UBAB FIFO TOP Entry */
+} Ifx_FLASH_UBAB;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Flash_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief FLASH object. */
+typedef volatile struct _Ifx_FLASH
+{
+ Ifx_FLASH_COMM0 COMM0; /**< \brief 0, FSI Communication Register 0 */
+ Ifx_FLASH_COMM1 COMM1; /**< \brief 4, FSI Communication Register 1 */
+ Ifx_FLASH_COMM2 COMM2; /**< \brief 8, FSI Communication Register 2 */
+ unsigned char reserved_C[4092]; /**< \brief C, \internal Reserved */
+ Ifx_FLASH_ID ID; /**< \brief 1008, Flash Module Identification Register */
+ unsigned char reserved_100C[4]; /**< \brief 100C, \internal Reserved */
+ Ifx_FLASH_FSR FSR; /**< \brief 1010, Flash Status Register */
+ Ifx_FLASH_FCON FCON; /**< \brief 1014, Flash Configuration Register */
+ unsigned char reserved_1018[4]; /**< \brief 1018, \internal Reserved */
+ Ifx_FLASH_FPRO FPRO; /**< \brief 101C, Flash Protection Control and Status Register */
+ Ifx_FLASH_PROCONP PROCONP[2]; /**< \brief 1020, PFlash Protection Configuration for ports */
+ unsigned char reserved_1028[8]; /**< \brief 1028, \internal Reserved */
+ Ifx_FLASH_PROCOND PROCOND; /**< \brief 1030, DFlash Protection Configuration */
+ Ifx_FLASH_PROCONHSMCOTP PROCONHSMCOTP; /**< \brief 1034, HSM Code Flash OTP Protection Configuration */
+ Ifx_FLASH_PROCONOTP PROCONOTP[2]; /**< \brief 1038, OTP Protection Configuration for ports */
+ unsigned char reserved_1040[8]; /**< \brief 1040, \internal Reserved */
+ Ifx_FLASH_PROCONWOP PROCONWOP[2]; /**< \brief 1048, Write-Once Protection Configuration for ports */
+ unsigned char reserved_1050[8]; /**< \brief 1050, \internal Reserved */
+ Ifx_FLASH_PROCONDBG PROCONDBG; /**< \brief 1058, Debug Interface Protection Configuration */
+ Ifx_FLASH_PROCONHSM PROCONHSM; /**< \brief 105C, HSM Interface Configuration */
+ Ifx_FLASH_RDB RDBCFG[2]; /**< \brief 1060, Read Buffer Configuration for ports */
+ unsigned char reserved_1078[24]; /**< \brief 1078, \internal Reserved */
+ Ifx_FLASH_ECCW ECCW; /**< \brief 1090, ECC Write Register */
+ Ifx_FLASH_ECCRP ECCRP[2]; /**< \brief 1094, ECC Read Register for ports */
+ unsigned char reserved_109C[8]; /**< \brief 109C, \internal Reserved */
+ Ifx_FLASH_ECCRD ECCRD; /**< \brief 10A4, ECC Read Register DF */
+ Ifx_FLASH_MARP MARP; /**< \brief 10A8, Margin Control Register PFlash */
+ Ifx_FLASH_MARD MARD; /**< \brief 10AC, Margin Control Register DFlash */
+ unsigned char reserved_10B0[4]; /**< \brief 10B0, \internal Reserved */
+ Ifx_FLASH_CBAB CBAB[2]; /**< \brief 10B4, Corrected Bits Address Buffer for ports */
+ unsigned char reserved_10CC[24]; /**< \brief 10CC, \internal Reserved */
+ Ifx_FLASH_UBAB UBAB[2]; /**< \brief 10E4, Uncorrectable Bits Address Buffer for ports */
+ unsigned char reserved_10FC[68]; /**< \brief 10FC, \internal Reserved */
+ Ifx_FLASH_RRCT RRCT; /**< \brief 1140, Requested Read Control Register */
+ Ifx_FLASH_RRD0 RRD0; /**< \brief 1144, Requested Read Data Register 0 */
+ Ifx_FLASH_RRD1 RRD1; /**< \brief 1148, Requested Read Data Register 1 */
+ Ifx_FLASH_RRAD RRAD; /**< \brief 114C, Requested Read Address Register */
+ unsigned char reserved_1150[680]; /**< \brief 1150, \internal Reserved */
+ Ifx_FLASH_ACCEN1 ACCEN1; /**< \brief 13F8, Access Enable Register 1 */
+ Ifx_FLASH_ACCEN0 ACCEN0; /**< \brief 13FC, Access Enable Register 0 */
+} Ifx_FLASH;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXFLASH_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxGpt12_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxGpt12_bf.h
new file mode 100644
index 0000000..f786308
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxGpt12_bf.h
@@ -0,0 +1,1071 @@
+/**
+ * \file IfxGpt12_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Gpt12_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Gpt12
+ *
+ */
+#ifndef IFXGPT12_BF_H
+#define IFXGPT12_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Gpt12_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN0 */
+#define IFX_GPT12_ACCEN0_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN0 */
+#define IFX_GPT12_ACCEN0_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN0 */
+#define IFX_GPT12_ACCEN0_EN0_OFF (0u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN10 */
+#define IFX_GPT12_ACCEN0_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN10 */
+#define IFX_GPT12_ACCEN0_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN10 */
+#define IFX_GPT12_ACCEN0_EN10_OFF (10u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN11 */
+#define IFX_GPT12_ACCEN0_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN11 */
+#define IFX_GPT12_ACCEN0_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN11 */
+#define IFX_GPT12_ACCEN0_EN11_OFF (11u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN12 */
+#define IFX_GPT12_ACCEN0_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN12 */
+#define IFX_GPT12_ACCEN0_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN12 */
+#define IFX_GPT12_ACCEN0_EN12_OFF (12u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN13 */
+#define IFX_GPT12_ACCEN0_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN13 */
+#define IFX_GPT12_ACCEN0_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN13 */
+#define IFX_GPT12_ACCEN0_EN13_OFF (13u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN14 */
+#define IFX_GPT12_ACCEN0_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN14 */
+#define IFX_GPT12_ACCEN0_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN14 */
+#define IFX_GPT12_ACCEN0_EN14_OFF (14u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN15 */
+#define IFX_GPT12_ACCEN0_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN15 */
+#define IFX_GPT12_ACCEN0_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN15 */
+#define IFX_GPT12_ACCEN0_EN15_OFF (15u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN16 */
+#define IFX_GPT12_ACCEN0_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN16 */
+#define IFX_GPT12_ACCEN0_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN16 */
+#define IFX_GPT12_ACCEN0_EN16_OFF (16u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN17 */
+#define IFX_GPT12_ACCEN0_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN17 */
+#define IFX_GPT12_ACCEN0_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN17 */
+#define IFX_GPT12_ACCEN0_EN17_OFF (17u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN18 */
+#define IFX_GPT12_ACCEN0_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN18 */
+#define IFX_GPT12_ACCEN0_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN18 */
+#define IFX_GPT12_ACCEN0_EN18_OFF (18u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN19 */
+#define IFX_GPT12_ACCEN0_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN19 */
+#define IFX_GPT12_ACCEN0_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN19 */
+#define IFX_GPT12_ACCEN0_EN19_OFF (19u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN1 */
+#define IFX_GPT12_ACCEN0_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN1 */
+#define IFX_GPT12_ACCEN0_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN1 */
+#define IFX_GPT12_ACCEN0_EN1_OFF (1u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN20 */
+#define IFX_GPT12_ACCEN0_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN20 */
+#define IFX_GPT12_ACCEN0_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN20 */
+#define IFX_GPT12_ACCEN0_EN20_OFF (20u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN21 */
+#define IFX_GPT12_ACCEN0_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN21 */
+#define IFX_GPT12_ACCEN0_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN21 */
+#define IFX_GPT12_ACCEN0_EN21_OFF (21u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN22 */
+#define IFX_GPT12_ACCEN0_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN22 */
+#define IFX_GPT12_ACCEN0_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN22 */
+#define IFX_GPT12_ACCEN0_EN22_OFF (22u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN23 */
+#define IFX_GPT12_ACCEN0_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN23 */
+#define IFX_GPT12_ACCEN0_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN23 */
+#define IFX_GPT12_ACCEN0_EN23_OFF (23u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN24 */
+#define IFX_GPT12_ACCEN0_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN24 */
+#define IFX_GPT12_ACCEN0_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN24 */
+#define IFX_GPT12_ACCEN0_EN24_OFF (24u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN25 */
+#define IFX_GPT12_ACCEN0_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN25 */
+#define IFX_GPT12_ACCEN0_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN25 */
+#define IFX_GPT12_ACCEN0_EN25_OFF (25u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN26 */
+#define IFX_GPT12_ACCEN0_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN26 */
+#define IFX_GPT12_ACCEN0_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN26 */
+#define IFX_GPT12_ACCEN0_EN26_OFF (26u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN27 */
+#define IFX_GPT12_ACCEN0_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN27 */
+#define IFX_GPT12_ACCEN0_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN27 */
+#define IFX_GPT12_ACCEN0_EN27_OFF (27u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN28 */
+#define IFX_GPT12_ACCEN0_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN28 */
+#define IFX_GPT12_ACCEN0_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN28 */
+#define IFX_GPT12_ACCEN0_EN28_OFF (28u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN29 */
+#define IFX_GPT12_ACCEN0_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN29 */
+#define IFX_GPT12_ACCEN0_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN29 */
+#define IFX_GPT12_ACCEN0_EN29_OFF (29u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN2 */
+#define IFX_GPT12_ACCEN0_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN2 */
+#define IFX_GPT12_ACCEN0_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN2 */
+#define IFX_GPT12_ACCEN0_EN2_OFF (2u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN30 */
+#define IFX_GPT12_ACCEN0_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN30 */
+#define IFX_GPT12_ACCEN0_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN30 */
+#define IFX_GPT12_ACCEN0_EN30_OFF (30u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN31 */
+#define IFX_GPT12_ACCEN0_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN31 */
+#define IFX_GPT12_ACCEN0_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN31 */
+#define IFX_GPT12_ACCEN0_EN31_OFF (31u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN3 */
+#define IFX_GPT12_ACCEN0_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN3 */
+#define IFX_GPT12_ACCEN0_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN3 */
+#define IFX_GPT12_ACCEN0_EN3_OFF (3u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN4 */
+#define IFX_GPT12_ACCEN0_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN4 */
+#define IFX_GPT12_ACCEN0_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN4 */
+#define IFX_GPT12_ACCEN0_EN4_OFF (4u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN5 */
+#define IFX_GPT12_ACCEN0_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN5 */
+#define IFX_GPT12_ACCEN0_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN5 */
+#define IFX_GPT12_ACCEN0_EN5_OFF (5u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN6 */
+#define IFX_GPT12_ACCEN0_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN6 */
+#define IFX_GPT12_ACCEN0_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN6 */
+#define IFX_GPT12_ACCEN0_EN6_OFF (6u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN7 */
+#define IFX_GPT12_ACCEN0_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN7 */
+#define IFX_GPT12_ACCEN0_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN7 */
+#define IFX_GPT12_ACCEN0_EN7_OFF (7u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN8 */
+#define IFX_GPT12_ACCEN0_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN8 */
+#define IFX_GPT12_ACCEN0_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN8 */
+#define IFX_GPT12_ACCEN0_EN8_OFF (8u)
+
+/** \brief Length for Ifx_GPT12_ACCEN0_Bits.EN9 */
+#define IFX_GPT12_ACCEN0_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_ACCEN0_Bits.EN9 */
+#define IFX_GPT12_ACCEN0_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_ACCEN0_Bits.EN9 */
+#define IFX_GPT12_ACCEN0_EN9_OFF (9u)
+
+/** \brief Length for Ifx_GPT12_CAPREL_Bits.CAPREL */
+#define IFX_GPT12_CAPREL_CAPREL_LEN (16u)
+
+/** \brief Mask for Ifx_GPT12_CAPREL_Bits.CAPREL */
+#define IFX_GPT12_CAPREL_CAPREL_MSK (0xffffu)
+
+/** \brief Offset for Ifx_GPT12_CAPREL_Bits.CAPREL */
+#define IFX_GPT12_CAPREL_CAPREL_OFF (0u)
+
+/** \brief Length for Ifx_GPT12_CLC_Bits.DISR */
+#define IFX_GPT12_CLC_DISR_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_CLC_Bits.DISR */
+#define IFX_GPT12_CLC_DISR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_CLC_Bits.DISR */
+#define IFX_GPT12_CLC_DISR_OFF (0u)
+
+/** \brief Length for Ifx_GPT12_CLC_Bits.DISS */
+#define IFX_GPT12_CLC_DISS_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_CLC_Bits.DISS */
+#define IFX_GPT12_CLC_DISS_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_CLC_Bits.DISS */
+#define IFX_GPT12_CLC_DISS_OFF (1u)
+
+/** \brief Length for Ifx_GPT12_CLC_Bits.EDIS */
+#define IFX_GPT12_CLC_EDIS_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_CLC_Bits.EDIS */
+#define IFX_GPT12_CLC_EDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_CLC_Bits.EDIS */
+#define IFX_GPT12_CLC_EDIS_OFF (3u)
+
+/** \brief Length for Ifx_GPT12_ID_Bits.MODNUMBER */
+#define IFX_GPT12_ID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_GPT12_ID_Bits.MODNUMBER */
+#define IFX_GPT12_ID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_GPT12_ID_Bits.MODNUMBER */
+#define IFX_GPT12_ID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_GPT12_ID_Bits.MODREV */
+#define IFX_GPT12_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_GPT12_ID_Bits.MODREV */
+#define IFX_GPT12_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_GPT12_ID_Bits.MODREV */
+#define IFX_GPT12_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_GPT12_ID_Bits.MODTYPE */
+#define IFX_GPT12_ID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_GPT12_ID_Bits.MODTYPE */
+#define IFX_GPT12_ID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_GPT12_ID_Bits.MODTYPE */
+#define IFX_GPT12_ID_MODTYPE_OFF (8u)
+
+/** \brief Length for Ifx_GPT12_KRST0_Bits.RST */
+#define IFX_GPT12_KRST0_RST_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_KRST0_Bits.RST */
+#define IFX_GPT12_KRST0_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_KRST0_Bits.RST */
+#define IFX_GPT12_KRST0_RST_OFF (0u)
+
+/** \brief Length for Ifx_GPT12_KRST0_Bits.RSTSTAT */
+#define IFX_GPT12_KRST0_RSTSTAT_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_KRST0_Bits.RSTSTAT */
+#define IFX_GPT12_KRST0_RSTSTAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_KRST0_Bits.RSTSTAT */
+#define IFX_GPT12_KRST0_RSTSTAT_OFF (1u)
+
+/** \brief Length for Ifx_GPT12_KRST1_Bits.RST */
+#define IFX_GPT12_KRST1_RST_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_KRST1_Bits.RST */
+#define IFX_GPT12_KRST1_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_KRST1_Bits.RST */
+#define IFX_GPT12_KRST1_RST_OFF (0u)
+
+/** \brief Length for Ifx_GPT12_KRSTCLR_Bits.CLR */
+#define IFX_GPT12_KRSTCLR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_KRSTCLR_Bits.CLR */
+#define IFX_GPT12_KRSTCLR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_KRSTCLR_Bits.CLR */
+#define IFX_GPT12_KRSTCLR_CLR_OFF (0u)
+
+/** \brief Length for Ifx_GPT12_OCS_Bits.SUS */
+#define IFX_GPT12_OCS_SUS_LEN (4u)
+
+/** \brief Mask for Ifx_GPT12_OCS_Bits.SUS */
+#define IFX_GPT12_OCS_SUS_MSK (0xfu)
+
+/** \brief Offset for Ifx_GPT12_OCS_Bits.SUS */
+#define IFX_GPT12_OCS_SUS_OFF (24u)
+
+/** \brief Length for Ifx_GPT12_OCS_Bits.SUS_P */
+#define IFX_GPT12_OCS_SUS_P_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_OCS_Bits.SUS_P */
+#define IFX_GPT12_OCS_SUS_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_OCS_Bits.SUS_P */
+#define IFX_GPT12_OCS_SUS_P_OFF (28u)
+
+/** \brief Length for Ifx_GPT12_OCS_Bits.SUSSTA */
+#define IFX_GPT12_OCS_SUSSTA_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_OCS_Bits.SUSSTA */
+#define IFX_GPT12_OCS_SUSSTA_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_OCS_Bits.SUSSTA */
+#define IFX_GPT12_OCS_SUSSTA_OFF (29u)
+
+/** \brief Length for Ifx_GPT12_PISEL_Bits.ISCAPIN */
+#define IFX_GPT12_PISEL_ISCAPIN_LEN (2u)
+
+/** \brief Mask for Ifx_GPT12_PISEL_Bits.ISCAPIN */
+#define IFX_GPT12_PISEL_ISCAPIN_MSK (0x3u)
+
+/** \brief Offset for Ifx_GPT12_PISEL_Bits.ISCAPIN */
+#define IFX_GPT12_PISEL_ISCAPIN_OFF (14u)
+
+/** \brief Length for Ifx_GPT12_PISEL_Bits.IST2EUD */
+#define IFX_GPT12_PISEL_IST2EUD_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_PISEL_Bits.IST2EUD */
+#define IFX_GPT12_PISEL_IST2EUD_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_PISEL_Bits.IST2EUD */
+#define IFX_GPT12_PISEL_IST2EUD_OFF (1u)
+
+/** \brief Length for Ifx_GPT12_PISEL_Bits.IST2IN */
+#define IFX_GPT12_PISEL_IST2IN_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_PISEL_Bits.IST2IN */
+#define IFX_GPT12_PISEL_IST2IN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_PISEL_Bits.IST2IN */
+#define IFX_GPT12_PISEL_IST2IN_OFF (0u)
+
+/** \brief Length for Ifx_GPT12_PISEL_Bits.IST3EUD */
+#define IFX_GPT12_PISEL_IST3EUD_LEN (2u)
+
+/** \brief Mask for Ifx_GPT12_PISEL_Bits.IST3EUD */
+#define IFX_GPT12_PISEL_IST3EUD_MSK (0x3u)
+
+/** \brief Offset for Ifx_GPT12_PISEL_Bits.IST3EUD */
+#define IFX_GPT12_PISEL_IST3EUD_OFF (4u)
+
+/** \brief Length for Ifx_GPT12_PISEL_Bits.IST3IN */
+#define IFX_GPT12_PISEL_IST3IN_LEN (2u)
+
+/** \brief Mask for Ifx_GPT12_PISEL_Bits.IST3IN */
+#define IFX_GPT12_PISEL_IST3IN_MSK (0x3u)
+
+/** \brief Offset for Ifx_GPT12_PISEL_Bits.IST3IN */
+#define IFX_GPT12_PISEL_IST3IN_OFF (2u)
+
+/** \brief Length for Ifx_GPT12_PISEL_Bits.IST4EUD */
+#define IFX_GPT12_PISEL_IST4EUD_LEN (2u)
+
+/** \brief Mask for Ifx_GPT12_PISEL_Bits.IST4EUD */
+#define IFX_GPT12_PISEL_IST4EUD_MSK (0x3u)
+
+/** \brief Offset for Ifx_GPT12_PISEL_Bits.IST4EUD */
+#define IFX_GPT12_PISEL_IST4EUD_OFF (8u)
+
+/** \brief Length for Ifx_GPT12_PISEL_Bits.IST4IN */
+#define IFX_GPT12_PISEL_IST4IN_LEN (2u)
+
+/** \brief Mask for Ifx_GPT12_PISEL_Bits.IST4IN */
+#define IFX_GPT12_PISEL_IST4IN_MSK (0x3u)
+
+/** \brief Offset for Ifx_GPT12_PISEL_Bits.IST4IN */
+#define IFX_GPT12_PISEL_IST4IN_OFF (6u)
+
+/** \brief Length for Ifx_GPT12_PISEL_Bits.IST5EUD */
+#define IFX_GPT12_PISEL_IST5EUD_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_PISEL_Bits.IST5EUD */
+#define IFX_GPT12_PISEL_IST5EUD_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_PISEL_Bits.IST5EUD */
+#define IFX_GPT12_PISEL_IST5EUD_OFF (11u)
+
+/** \brief Length for Ifx_GPT12_PISEL_Bits.IST5IN */
+#define IFX_GPT12_PISEL_IST5IN_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_PISEL_Bits.IST5IN */
+#define IFX_GPT12_PISEL_IST5IN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_PISEL_Bits.IST5IN */
+#define IFX_GPT12_PISEL_IST5IN_OFF (10u)
+
+/** \brief Length for Ifx_GPT12_PISEL_Bits.IST6EUD */
+#define IFX_GPT12_PISEL_IST6EUD_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_PISEL_Bits.IST6EUD */
+#define IFX_GPT12_PISEL_IST6EUD_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_PISEL_Bits.IST6EUD */
+#define IFX_GPT12_PISEL_IST6EUD_OFF (13u)
+
+/** \brief Length for Ifx_GPT12_PISEL_Bits.IST6IN */
+#define IFX_GPT12_PISEL_IST6IN_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_PISEL_Bits.IST6IN */
+#define IFX_GPT12_PISEL_IST6IN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_PISEL_Bits.IST6IN */
+#define IFX_GPT12_PISEL_IST6IN_OFF (12u)
+
+/** \brief Length for Ifx_GPT12_T2_Bits.T2 */
+#define IFX_GPT12_T2_T2_LEN (16u)
+
+/** \brief Mask for Ifx_GPT12_T2_Bits.T2 */
+#define IFX_GPT12_T2_T2_MSK (0xffffu)
+
+/** \brief Offset for Ifx_GPT12_T2_Bits.T2 */
+#define IFX_GPT12_T2_T2_OFF (0u)
+
+/** \brief Length for Ifx_GPT12_T2CON_Bits.T2CHDIR */
+#define IFX_GPT12_T2CON_T2CHDIR_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T2CON_Bits.T2CHDIR */
+#define IFX_GPT12_T2CON_T2CHDIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T2CON_Bits.T2CHDIR */
+#define IFX_GPT12_T2CON_T2CHDIR_OFF (14u)
+
+/** \brief Length for Ifx_GPT12_T2CON_Bits.T2EDGE */
+#define IFX_GPT12_T2CON_T2EDGE_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T2CON_Bits.T2EDGE */
+#define IFX_GPT12_T2CON_T2EDGE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T2CON_Bits.T2EDGE */
+#define IFX_GPT12_T2CON_T2EDGE_OFF (13u)
+
+/** \brief Length for Ifx_GPT12_T2CON_Bits.T2I */
+#define IFX_GPT12_T2CON_T2I_LEN (3u)
+
+/** \brief Mask for Ifx_GPT12_T2CON_Bits.T2I */
+#define IFX_GPT12_T2CON_T2I_MSK (0x7u)
+
+/** \brief Offset for Ifx_GPT12_T2CON_Bits.T2I */
+#define IFX_GPT12_T2CON_T2I_OFF (0u)
+
+/** \brief Length for Ifx_GPT12_T2CON_Bits.T2IRDIS */
+#define IFX_GPT12_T2CON_T2IRDIS_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T2CON_Bits.T2IRDIS */
+#define IFX_GPT12_T2CON_T2IRDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T2CON_Bits.T2IRDIS */
+#define IFX_GPT12_T2CON_T2IRDIS_OFF (12u)
+
+/** \brief Length for Ifx_GPT12_T2CON_Bits.T2M */
+#define IFX_GPT12_T2CON_T2M_LEN (3u)
+
+/** \brief Mask for Ifx_GPT12_T2CON_Bits.T2M */
+#define IFX_GPT12_T2CON_T2M_MSK (0x7u)
+
+/** \brief Offset for Ifx_GPT12_T2CON_Bits.T2M */
+#define IFX_GPT12_T2CON_T2M_OFF (3u)
+
+/** \brief Length for Ifx_GPT12_T2CON_Bits.T2R */
+#define IFX_GPT12_T2CON_T2R_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T2CON_Bits.T2R */
+#define IFX_GPT12_T2CON_T2R_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T2CON_Bits.T2R */
+#define IFX_GPT12_T2CON_T2R_OFF (6u)
+
+/** \brief Length for Ifx_GPT12_T2CON_Bits.T2RC */
+#define IFX_GPT12_T2CON_T2RC_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T2CON_Bits.T2RC */
+#define IFX_GPT12_T2CON_T2RC_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T2CON_Bits.T2RC */
+#define IFX_GPT12_T2CON_T2RC_OFF (9u)
+
+/** \brief Length for Ifx_GPT12_T2CON_Bits.T2RDIR */
+#define IFX_GPT12_T2CON_T2RDIR_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T2CON_Bits.T2RDIR */
+#define IFX_GPT12_T2CON_T2RDIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T2CON_Bits.T2RDIR */
+#define IFX_GPT12_T2CON_T2RDIR_OFF (15u)
+
+/** \brief Length for Ifx_GPT12_T2CON_Bits.T2UD */
+#define IFX_GPT12_T2CON_T2UD_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T2CON_Bits.T2UD */
+#define IFX_GPT12_T2CON_T2UD_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T2CON_Bits.T2UD */
+#define IFX_GPT12_T2CON_T2UD_OFF (7u)
+
+/** \brief Length for Ifx_GPT12_T2CON_Bits.T2UDE */
+#define IFX_GPT12_T2CON_T2UDE_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T2CON_Bits.T2UDE */
+#define IFX_GPT12_T2CON_T2UDE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T2CON_Bits.T2UDE */
+#define IFX_GPT12_T2CON_T2UDE_OFF (8u)
+
+/** \brief Length for Ifx_GPT12_T3_Bits.T3 */
+#define IFX_GPT12_T3_T3_LEN (16u)
+
+/** \brief Mask for Ifx_GPT12_T3_Bits.T3 */
+#define IFX_GPT12_T3_T3_MSK (0xffffu)
+
+/** \brief Offset for Ifx_GPT12_T3_Bits.T3 */
+#define IFX_GPT12_T3_T3_OFF (0u)
+
+/** \brief Length for Ifx_GPT12_T3CON_Bits.BPS1 */
+#define IFX_GPT12_T3CON_BPS1_LEN (2u)
+
+/** \brief Mask for Ifx_GPT12_T3CON_Bits.BPS1 */
+#define IFX_GPT12_T3CON_BPS1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GPT12_T3CON_Bits.BPS1 */
+#define IFX_GPT12_T3CON_BPS1_OFF (11u)
+
+/** \brief Length for Ifx_GPT12_T3CON_Bits.T3CHDIR */
+#define IFX_GPT12_T3CON_T3CHDIR_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T3CON_Bits.T3CHDIR */
+#define IFX_GPT12_T3CON_T3CHDIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T3CON_Bits.T3CHDIR */
+#define IFX_GPT12_T3CON_T3CHDIR_OFF (14u)
+
+/** \brief Length for Ifx_GPT12_T3CON_Bits.T3EDGE */
+#define IFX_GPT12_T3CON_T3EDGE_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T3CON_Bits.T3EDGE */
+#define IFX_GPT12_T3CON_T3EDGE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T3CON_Bits.T3EDGE */
+#define IFX_GPT12_T3CON_T3EDGE_OFF (13u)
+
+/** \brief Length for Ifx_GPT12_T3CON_Bits.T3I */
+#define IFX_GPT12_T3CON_T3I_LEN (3u)
+
+/** \brief Mask for Ifx_GPT12_T3CON_Bits.T3I */
+#define IFX_GPT12_T3CON_T3I_MSK (0x7u)
+
+/** \brief Offset for Ifx_GPT12_T3CON_Bits.T3I */
+#define IFX_GPT12_T3CON_T3I_OFF (0u)
+
+/** \brief Length for Ifx_GPT12_T3CON_Bits.T3M */
+#define IFX_GPT12_T3CON_T3M_LEN (3u)
+
+/** \brief Mask for Ifx_GPT12_T3CON_Bits.T3M */
+#define IFX_GPT12_T3CON_T3M_MSK (0x7u)
+
+/** \brief Offset for Ifx_GPT12_T3CON_Bits.T3M */
+#define IFX_GPT12_T3CON_T3M_OFF (3u)
+
+/** \brief Length for Ifx_GPT12_T3CON_Bits.T3OE */
+#define IFX_GPT12_T3CON_T3OE_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T3CON_Bits.T3OE */
+#define IFX_GPT12_T3CON_T3OE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T3CON_Bits.T3OE */
+#define IFX_GPT12_T3CON_T3OE_OFF (9u)
+
+/** \brief Length for Ifx_GPT12_T3CON_Bits.T3OTL */
+#define IFX_GPT12_T3CON_T3OTL_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T3CON_Bits.T3OTL */
+#define IFX_GPT12_T3CON_T3OTL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T3CON_Bits.T3OTL */
+#define IFX_GPT12_T3CON_T3OTL_OFF (10u)
+
+/** \brief Length for Ifx_GPT12_T3CON_Bits.T3R */
+#define IFX_GPT12_T3CON_T3R_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T3CON_Bits.T3R */
+#define IFX_GPT12_T3CON_T3R_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T3CON_Bits.T3R */
+#define IFX_GPT12_T3CON_T3R_OFF (6u)
+
+/** \brief Length for Ifx_GPT12_T3CON_Bits.T3RDIR */
+#define IFX_GPT12_T3CON_T3RDIR_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T3CON_Bits.T3RDIR */
+#define IFX_GPT12_T3CON_T3RDIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T3CON_Bits.T3RDIR */
+#define IFX_GPT12_T3CON_T3RDIR_OFF (15u)
+
+/** \brief Length for Ifx_GPT12_T3CON_Bits.T3UD */
+#define IFX_GPT12_T3CON_T3UD_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T3CON_Bits.T3UD */
+#define IFX_GPT12_T3CON_T3UD_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T3CON_Bits.T3UD */
+#define IFX_GPT12_T3CON_T3UD_OFF (7u)
+
+/** \brief Length for Ifx_GPT12_T3CON_Bits.T3UDE */
+#define IFX_GPT12_T3CON_T3UDE_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T3CON_Bits.T3UDE */
+#define IFX_GPT12_T3CON_T3UDE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T3CON_Bits.T3UDE */
+#define IFX_GPT12_T3CON_T3UDE_OFF (8u)
+
+/** \brief Length for Ifx_GPT12_T4_Bits.T4 */
+#define IFX_GPT12_T4_T4_LEN (16u)
+
+/** \brief Mask for Ifx_GPT12_T4_Bits.T4 */
+#define IFX_GPT12_T4_T4_MSK (0xffffu)
+
+/** \brief Offset for Ifx_GPT12_T4_Bits.T4 */
+#define IFX_GPT12_T4_T4_OFF (0u)
+
+/** \brief Length for Ifx_GPT12_T4CON_Bits.CLRT2EN */
+#define IFX_GPT12_T4CON_CLRT2EN_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T4CON_Bits.CLRT2EN */
+#define IFX_GPT12_T4CON_CLRT2EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T4CON_Bits.CLRT2EN */
+#define IFX_GPT12_T4CON_CLRT2EN_OFF (10u)
+
+/** \brief Length for Ifx_GPT12_T4CON_Bits.CLRT3EN */
+#define IFX_GPT12_T4CON_CLRT3EN_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T4CON_Bits.CLRT3EN */
+#define IFX_GPT12_T4CON_CLRT3EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T4CON_Bits.CLRT3EN */
+#define IFX_GPT12_T4CON_CLRT3EN_OFF (11u)
+
+/** \brief Length for Ifx_GPT12_T4CON_Bits.T4CHDIR */
+#define IFX_GPT12_T4CON_T4CHDIR_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T4CON_Bits.T4CHDIR */
+#define IFX_GPT12_T4CON_T4CHDIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T4CON_Bits.T4CHDIR */
+#define IFX_GPT12_T4CON_T4CHDIR_OFF (14u)
+
+/** \brief Length for Ifx_GPT12_T4CON_Bits.T4EDGE */
+#define IFX_GPT12_T4CON_T4EDGE_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T4CON_Bits.T4EDGE */
+#define IFX_GPT12_T4CON_T4EDGE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T4CON_Bits.T4EDGE */
+#define IFX_GPT12_T4CON_T4EDGE_OFF (13u)
+
+/** \brief Length for Ifx_GPT12_T4CON_Bits.T4I */
+#define IFX_GPT12_T4CON_T4I_LEN (3u)
+
+/** \brief Mask for Ifx_GPT12_T4CON_Bits.T4I */
+#define IFX_GPT12_T4CON_T4I_MSK (0x7u)
+
+/** \brief Offset for Ifx_GPT12_T4CON_Bits.T4I */
+#define IFX_GPT12_T4CON_T4I_OFF (0u)
+
+/** \brief Length for Ifx_GPT12_T4CON_Bits.T4IRDIS */
+#define IFX_GPT12_T4CON_T4IRDIS_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T4CON_Bits.T4IRDIS */
+#define IFX_GPT12_T4CON_T4IRDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T4CON_Bits.T4IRDIS */
+#define IFX_GPT12_T4CON_T4IRDIS_OFF (12u)
+
+/** \brief Length for Ifx_GPT12_T4CON_Bits.T4M */
+#define IFX_GPT12_T4CON_T4M_LEN (3u)
+
+/** \brief Mask for Ifx_GPT12_T4CON_Bits.T4M */
+#define IFX_GPT12_T4CON_T4M_MSK (0x7u)
+
+/** \brief Offset for Ifx_GPT12_T4CON_Bits.T4M */
+#define IFX_GPT12_T4CON_T4M_OFF (3u)
+
+/** \brief Length for Ifx_GPT12_T4CON_Bits.T4R */
+#define IFX_GPT12_T4CON_T4R_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T4CON_Bits.T4R */
+#define IFX_GPT12_T4CON_T4R_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T4CON_Bits.T4R */
+#define IFX_GPT12_T4CON_T4R_OFF (6u)
+
+/** \brief Length for Ifx_GPT12_T4CON_Bits.T4RC */
+#define IFX_GPT12_T4CON_T4RC_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T4CON_Bits.T4RC */
+#define IFX_GPT12_T4CON_T4RC_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T4CON_Bits.T4RC */
+#define IFX_GPT12_T4CON_T4RC_OFF (9u)
+
+/** \brief Length for Ifx_GPT12_T4CON_Bits.T4RDIR */
+#define IFX_GPT12_T4CON_T4RDIR_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T4CON_Bits.T4RDIR */
+#define IFX_GPT12_T4CON_T4RDIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T4CON_Bits.T4RDIR */
+#define IFX_GPT12_T4CON_T4RDIR_OFF (15u)
+
+/** \brief Length for Ifx_GPT12_T4CON_Bits.T4UD */
+#define IFX_GPT12_T4CON_T4UD_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T4CON_Bits.T4UD */
+#define IFX_GPT12_T4CON_T4UD_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T4CON_Bits.T4UD */
+#define IFX_GPT12_T4CON_T4UD_OFF (7u)
+
+/** \brief Length for Ifx_GPT12_T4CON_Bits.T4UDE */
+#define IFX_GPT12_T4CON_T4UDE_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T4CON_Bits.T4UDE */
+#define IFX_GPT12_T4CON_T4UDE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T4CON_Bits.T4UDE */
+#define IFX_GPT12_T4CON_T4UDE_OFF (8u)
+
+/** \brief Length for Ifx_GPT12_T5_Bits.T5 */
+#define IFX_GPT12_T5_T5_LEN (16u)
+
+/** \brief Mask for Ifx_GPT12_T5_Bits.T5 */
+#define IFX_GPT12_T5_T5_MSK (0xffffu)
+
+/** \brief Offset for Ifx_GPT12_T5_Bits.T5 */
+#define IFX_GPT12_T5_T5_OFF (0u)
+
+/** \brief Length for Ifx_GPT12_T5CON_Bits.CI */
+#define IFX_GPT12_T5CON_CI_LEN (2u)
+
+/** \brief Mask for Ifx_GPT12_T5CON_Bits.CI */
+#define IFX_GPT12_T5CON_CI_MSK (0x3u)
+
+/** \brief Offset for Ifx_GPT12_T5CON_Bits.CI */
+#define IFX_GPT12_T5CON_CI_OFF (12u)
+
+/** \brief Length for Ifx_GPT12_T5CON_Bits.CT3 */
+#define IFX_GPT12_T5CON_CT3_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T5CON_Bits.CT3 */
+#define IFX_GPT12_T5CON_CT3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T5CON_Bits.CT3 */
+#define IFX_GPT12_T5CON_CT3_OFF (10u)
+
+/** \brief Length for Ifx_GPT12_T5CON_Bits.T5CLR */
+#define IFX_GPT12_T5CON_T5CLR_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T5CON_Bits.T5CLR */
+#define IFX_GPT12_T5CON_T5CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T5CON_Bits.T5CLR */
+#define IFX_GPT12_T5CON_T5CLR_OFF (14u)
+
+/** \brief Length for Ifx_GPT12_T5CON_Bits.T5I */
+#define IFX_GPT12_T5CON_T5I_LEN (3u)
+
+/** \brief Mask for Ifx_GPT12_T5CON_Bits.T5I */
+#define IFX_GPT12_T5CON_T5I_MSK (0x7u)
+
+/** \brief Offset for Ifx_GPT12_T5CON_Bits.T5I */
+#define IFX_GPT12_T5CON_T5I_OFF (0u)
+
+/** \brief Length for Ifx_GPT12_T5CON_Bits.T5M */
+#define IFX_GPT12_T5CON_T5M_LEN (3u)
+
+/** \brief Mask for Ifx_GPT12_T5CON_Bits.T5M */
+#define IFX_GPT12_T5CON_T5M_MSK (0x7u)
+
+/** \brief Offset for Ifx_GPT12_T5CON_Bits.T5M */
+#define IFX_GPT12_T5CON_T5M_OFF (3u)
+
+/** \brief Length for Ifx_GPT12_T5CON_Bits.T5R */
+#define IFX_GPT12_T5CON_T5R_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T5CON_Bits.T5R */
+#define IFX_GPT12_T5CON_T5R_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T5CON_Bits.T5R */
+#define IFX_GPT12_T5CON_T5R_OFF (6u)
+
+/** \brief Length for Ifx_GPT12_T5CON_Bits.T5RC */
+#define IFX_GPT12_T5CON_T5RC_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T5CON_Bits.T5RC */
+#define IFX_GPT12_T5CON_T5RC_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T5CON_Bits.T5RC */
+#define IFX_GPT12_T5CON_T5RC_OFF (9u)
+
+/** \brief Length for Ifx_GPT12_T5CON_Bits.T5SC */
+#define IFX_GPT12_T5CON_T5SC_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T5CON_Bits.T5SC */
+#define IFX_GPT12_T5CON_T5SC_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T5CON_Bits.T5SC */
+#define IFX_GPT12_T5CON_T5SC_OFF (15u)
+
+/** \brief Length for Ifx_GPT12_T5CON_Bits.T5UD */
+#define IFX_GPT12_T5CON_T5UD_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T5CON_Bits.T5UD */
+#define IFX_GPT12_T5CON_T5UD_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T5CON_Bits.T5UD */
+#define IFX_GPT12_T5CON_T5UD_OFF (7u)
+
+/** \brief Length for Ifx_GPT12_T5CON_Bits.T5UDE */
+#define IFX_GPT12_T5CON_T5UDE_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T5CON_Bits.T5UDE */
+#define IFX_GPT12_T5CON_T5UDE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T5CON_Bits.T5UDE */
+#define IFX_GPT12_T5CON_T5UDE_OFF (8u)
+
+/** \brief Length for Ifx_GPT12_T6_Bits.T6 */
+#define IFX_GPT12_T6_T6_LEN (16u)
+
+/** \brief Mask for Ifx_GPT12_T6_Bits.T6 */
+#define IFX_GPT12_T6_T6_MSK (0xffffu)
+
+/** \brief Offset for Ifx_GPT12_T6_Bits.T6 */
+#define IFX_GPT12_T6_T6_OFF (0u)
+
+/** \brief Length for Ifx_GPT12_T6CON_Bits.BPS2 */
+#define IFX_GPT12_T6CON_BPS2_LEN (2u)
+
+/** \brief Mask for Ifx_GPT12_T6CON_Bits.BPS2 */
+#define IFX_GPT12_T6CON_BPS2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GPT12_T6CON_Bits.BPS2 */
+#define IFX_GPT12_T6CON_BPS2_OFF (11u)
+
+/** \brief Length for Ifx_GPT12_T6CON_Bits.T6CLR */
+#define IFX_GPT12_T6CON_T6CLR_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T6CON_Bits.T6CLR */
+#define IFX_GPT12_T6CON_T6CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T6CON_Bits.T6CLR */
+#define IFX_GPT12_T6CON_T6CLR_OFF (14u)
+
+/** \brief Length for Ifx_GPT12_T6CON_Bits.T6I */
+#define IFX_GPT12_T6CON_T6I_LEN (3u)
+
+/** \brief Mask for Ifx_GPT12_T6CON_Bits.T6I */
+#define IFX_GPT12_T6CON_T6I_MSK (0x7u)
+
+/** \brief Offset for Ifx_GPT12_T6CON_Bits.T6I */
+#define IFX_GPT12_T6CON_T6I_OFF (0u)
+
+/** \brief Length for Ifx_GPT12_T6CON_Bits.T6M */
+#define IFX_GPT12_T6CON_T6M_LEN (3u)
+
+/** \brief Mask for Ifx_GPT12_T6CON_Bits.T6M */
+#define IFX_GPT12_T6CON_T6M_MSK (0x7u)
+
+/** \brief Offset for Ifx_GPT12_T6CON_Bits.T6M */
+#define IFX_GPT12_T6CON_T6M_OFF (3u)
+
+/** \brief Length for Ifx_GPT12_T6CON_Bits.T6OE */
+#define IFX_GPT12_T6CON_T6OE_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T6CON_Bits.T6OE */
+#define IFX_GPT12_T6CON_T6OE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T6CON_Bits.T6OE */
+#define IFX_GPT12_T6CON_T6OE_OFF (9u)
+
+/** \brief Length for Ifx_GPT12_T6CON_Bits.T6OTL */
+#define IFX_GPT12_T6CON_T6OTL_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T6CON_Bits.T6OTL */
+#define IFX_GPT12_T6CON_T6OTL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T6CON_Bits.T6OTL */
+#define IFX_GPT12_T6CON_T6OTL_OFF (10u)
+
+/** \brief Length for Ifx_GPT12_T6CON_Bits.T6R */
+#define IFX_GPT12_T6CON_T6R_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T6CON_Bits.T6R */
+#define IFX_GPT12_T6CON_T6R_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T6CON_Bits.T6R */
+#define IFX_GPT12_T6CON_T6R_OFF (6u)
+
+/** \brief Length for Ifx_GPT12_T6CON_Bits.T6SR */
+#define IFX_GPT12_T6CON_T6SR_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T6CON_Bits.T6SR */
+#define IFX_GPT12_T6CON_T6SR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T6CON_Bits.T6SR */
+#define IFX_GPT12_T6CON_T6SR_OFF (15u)
+
+/** \brief Length for Ifx_GPT12_T6CON_Bits.T6UD */
+#define IFX_GPT12_T6CON_T6UD_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T6CON_Bits.T6UD */
+#define IFX_GPT12_T6CON_T6UD_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T6CON_Bits.T6UD */
+#define IFX_GPT12_T6CON_T6UD_OFF (7u)
+
+/** \brief Length for Ifx_GPT12_T6CON_Bits.T6UDE */
+#define IFX_GPT12_T6CON_T6UDE_LEN (1u)
+
+/** \brief Mask for Ifx_GPT12_T6CON_Bits.T6UDE */
+#define IFX_GPT12_T6CON_T6UDE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GPT12_T6CON_Bits.T6UDE */
+#define IFX_GPT12_T6CON_T6UDE_OFF (8u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXGPT12_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxGpt12_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxGpt12_reg.h
new file mode 100644
index 0000000..f329136
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxGpt12_reg.h
@@ -0,0 +1,111 @@
+/**
+ * \file IfxGpt12_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Gpt12_Cfg Gpt12 address
+ * \ingroup IfxLld_Gpt12
+ *
+ * \defgroup IfxLld_Gpt12_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Gpt12_Cfg
+ *
+ * \defgroup IfxLld_Gpt12_Cfg_Gpt120 2-GPT120
+ * \ingroup IfxLld_Gpt12_Cfg
+ *
+ */
+#ifndef IFXGPT12_REG_H
+#define IFXGPT12_REG_H 1
+/******************************************************************************/
+#include "IfxGpt12_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Gpt12_Cfg_BaseAddress
+ * \{ */
+
+/** \brief GPT12 object */
+#define MODULE_GPT120 /*lint --e(923)*/ (*(Ifx_GPT12*)0xF0002E00u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Gpt12_Cfg_Gpt120
+ * \{ */
+
+/** \brief FC, Access Enable Register 0 */
+#define GPT120_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_GPT12_ACCEN0*)0xF0002EFCu)
+
+/** \brief F8, Access Enable Register 1 */
+#define GPT120_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_GPT12_ACCEN1*)0xF0002EF8u)
+
+/** \brief 30, Capture and Reload Register */
+#define GPT120_CAPREL /*lint --e(923)*/ (*(volatile Ifx_GPT12_CAPREL*)0xF0002E30u)
+
+/** \brief 0, Clock Control Register */
+#define GPT120_CLC /*lint --e(923)*/ (*(volatile Ifx_GPT12_CLC*)0xF0002E00u)
+
+/** \brief 8, Identification Register */
+#define GPT120_ID /*lint --e(923)*/ (*(volatile Ifx_GPT12_ID*)0xF0002E08u)
+
+/** \brief F4, Kernel Reset Register 0 */
+#define GPT120_KRST0 /*lint --e(923)*/ (*(volatile Ifx_GPT12_KRST0*)0xF0002EF4u)
+
+/** \brief F0, Kernel Reset Register 1 */
+#define GPT120_KRST1 /*lint --e(923)*/ (*(volatile Ifx_GPT12_KRST1*)0xF0002EF0u)
+
+/** \brief EC, Kernel Reset Status Clear Register */
+#define GPT120_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_GPT12_KRSTCLR*)0xF0002EECu)
+
+/** \brief E8, OCDS Control and Status Register */
+#define GPT120_OCS /*lint --e(923)*/ (*(volatile Ifx_GPT12_OCS*)0xF0002EE8u)
+
+/** \brief 4, Port Input Select Register */
+#define GPT120_PISEL /*lint --e(923)*/ (*(volatile Ifx_GPT12_PISEL*)0xF0002E04u)
+
+/** \brief 34, Timer T2 Register */
+#define GPT120_T2 /*lint --e(923)*/ (*(volatile Ifx_GPT12_T2*)0xF0002E34u)
+
+/** \brief 10, Timer T2 Control Register */
+#define GPT120_T2CON /*lint --e(923)*/ (*(volatile Ifx_GPT12_T2CON*)0xF0002E10u)
+
+/** \brief 38, Timer T3 Register */
+#define GPT120_T3 /*lint --e(923)*/ (*(volatile Ifx_GPT12_T3*)0xF0002E38u)
+
+/** \brief 14, Timer T3 Control Register */
+#define GPT120_T3CON /*lint --e(923)*/ (*(volatile Ifx_GPT12_T3CON*)0xF0002E14u)
+
+/** \brief 3C, Timer T4 Register */
+#define GPT120_T4 /*lint --e(923)*/ (*(volatile Ifx_GPT12_T4*)0xF0002E3Cu)
+
+/** \brief 18, Timer T4 Control Register */
+#define GPT120_T4CON /*lint --e(923)*/ (*(volatile Ifx_GPT12_T4CON*)0xF0002E18u)
+
+/** \brief 40, Timer T5 Register */
+#define GPT120_T5 /*lint --e(923)*/ (*(volatile Ifx_GPT12_T5*)0xF0002E40u)
+
+/** \brief 1C, Timer T5 Control Register */
+#define GPT120_T5CON /*lint --e(923)*/ (*(volatile Ifx_GPT12_T5CON*)0xF0002E1Cu)
+
+/** \brief 44, Timer T6 Register */
+#define GPT120_T6 /*lint --e(923)*/ (*(volatile Ifx_GPT12_T6*)0xF0002E44u)
+
+/** \brief 20, Timer T6 Control Register */
+#define GPT120_T6CON /*lint --e(923)*/ (*(volatile Ifx_GPT12_T6CON*)0xF0002E20u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXGPT12_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxGpt12_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxGpt12_regdef.h
new file mode 100644
index 0000000..add38fa
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxGpt12_regdef.h
@@ -0,0 +1,487 @@
+/**
+ * \file IfxGpt12_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Gpt12 Gpt12
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Gpt12_Bitfields Bitfields
+ * \ingroup IfxLld_Gpt12
+ *
+ * \defgroup IfxLld_Gpt12_union Union
+ * \ingroup IfxLld_Gpt12
+ *
+ * \defgroup IfxLld_Gpt12_struct Struct
+ * \ingroup IfxLld_Gpt12
+ *
+ */
+#ifndef IFXGPT12_REGDEF_H
+#define IFXGPT12_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Gpt12_Bitfields
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef struct _Ifx_GPT12_ACCEN0_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_GPT12_ACCEN0_Bits;
+
+/** \brief Access Enable Register 1 */
+typedef struct _Ifx_GPT12_ACCEN1_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_GPT12_ACCEN1_Bits;
+
+/** \brief Capture and Reload Register */
+typedef struct _Ifx_GPT12_CAPREL_Bits
+{
+ unsigned int CAPREL:16; /**< \brief [15:0] Current reload value or Captured value (rwh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GPT12_CAPREL_Bits;
+
+/** \brief Clock Control Register */
+typedef struct _Ifx_GPT12_CLC_Bits
+{
+ unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
+ unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
+ unsigned int reserved_2:1; /**< \brief \internal Reserved */
+ unsigned int EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control (rw) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_GPT12_CLC_Bits;
+
+/** \brief Identification Register */
+typedef struct _Ifx_GPT12_ID_Bits
+{
+ unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
+ unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_GPT12_ID_Bits;
+
+/** \brief Kernel Reset Register 0 */
+typedef struct _Ifx_GPT12_KRST0_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rw) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_GPT12_KRST0_Bits;
+
+/** \brief Kernel Reset Register 1 */
+typedef struct _Ifx_GPT12_KRST1_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_GPT12_KRST1_Bits;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef struct _Ifx_GPT12_KRSTCLR_Bits
+{
+ unsigned int CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_GPT12_KRSTCLR_Bits;
+
+/** \brief OCDS Control and Status Register */
+typedef struct _Ifx_GPT12_OCS_Bits
+{
+ unsigned int reserved_0:24; /**< \brief \internal Reserved */
+ unsigned int SUS:4; /**< \brief [27:24] OCDS Suspend Control (rw) */
+ unsigned int SUS_P:1; /**< \brief [28:28] SUS Write Protection (w) */
+ unsigned int SUSSTA:1; /**< \brief [29:29] Suspend State (rh) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_GPT12_OCS_Bits;
+
+/** \brief Port Input Select Register */
+typedef struct _Ifx_GPT12_PISEL_Bits
+{
+ unsigned int IST2IN:1; /**< \brief [0:0] Input Select for T2IN (rw) */
+ unsigned int IST2EUD:1; /**< \brief [1:1] Input Select for T2EUD (rw) */
+ unsigned int IST3IN:2; /**< \brief [3:2] Input Select for T3IN (rw) */
+ unsigned int IST3EUD:2; /**< \brief [5:4] Input Select for T3EUD (rw) */
+ unsigned int IST4IN:2; /**< \brief [7:6] Input Select for T4IN (rw) */
+ unsigned int IST4EUD:2; /**< \brief [9:8] Input Select for T4EUD (rw) */
+ unsigned int IST5IN:1; /**< \brief [10:10] Input Select for T5IN (rw) */
+ unsigned int IST5EUD:1; /**< \brief [11:11] Input Select for T5EUD (rw) */
+ unsigned int IST6IN:1; /**< \brief [12:12] Input Select for T6IN (rw) */
+ unsigned int IST6EUD:1; /**< \brief [13:13] Input Select for T6EUD (rw) */
+ unsigned int ISCAPIN:2; /**< \brief [15:14] Input Select for CAPIN (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GPT12_PISEL_Bits;
+
+/** \brief Timer T2 Register */
+typedef struct _Ifx_GPT12_T2_Bits
+{
+ unsigned int T2:16; /**< \brief [15:0] Timer T2 (rwh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GPT12_T2_Bits;
+
+/** \brief Timer T2 Control Register */
+typedef struct _Ifx_GPT12_T2CON_Bits
+{
+ unsigned int T2I:3; /**< \brief [2:0] Timer T2 Input Parameter Selection (rw) */
+ unsigned int T2M:3; /**< \brief [5:3] Timer T2 Mode Control (Basic Operating Mode) (rw) */
+ unsigned int T2R:1; /**< \brief [6:6] Timer T2 Run Bit (rw) */
+ unsigned int T2UD:1; /**< \brief [7:7] Timer T2 Up/Down Control (rw) */
+ unsigned int T2UDE:1; /**< \brief [8:8] Timer T2 External Up/Down Enable (rw) */
+ unsigned int T2RC:1; /**< \brief [9:9] Timer T2 Remote Control (rw) */
+ unsigned int reserved_10:2; /**< \brief \internal Reserved */
+ unsigned int T2IRDIS:1; /**< \brief [12:12] Timer T2 Interrupt Disable (rw) */
+ unsigned int T2EDGE:1; /**< \brief [13:13] Timer T2 Edge Detection (rwh) */
+ unsigned int T2CHDIR:1; /**< \brief [14:14] Timer T2 Count Direction Change (rwh) */
+ unsigned int T2RDIR:1; /**< \brief [15:15] Timer T2 Rotation Direction (rh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GPT12_T2CON_Bits;
+
+/** \brief Timer T3 Register */
+typedef struct _Ifx_GPT12_T3_Bits
+{
+ unsigned int T3:16; /**< \brief [15:0] Timer T3 (rwh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GPT12_T3_Bits;
+
+/** \brief Timer T3 Control Register */
+typedef struct _Ifx_GPT12_T3CON_Bits
+{
+ unsigned int T3I:3; /**< \brief [2:0] Timer T3 Input Parameter Selection (rw) */
+ unsigned int T3M:3; /**< \brief [5:3] Timer T3 Mode Control (rw) */
+ unsigned int T3R:1; /**< \brief [6:6] Timer T3 Run Bit (rw) */
+ unsigned int T3UD:1; /**< \brief [7:7] Timer T3 Up/Down Control (rw) */
+ unsigned int T3UDE:1; /**< \brief [8:8] Timer T3 External Up/Down Enable (rw) */
+ unsigned int T3OE:1; /**< \brief [9:9] Overflow/Underflow Output Enable (rw) */
+ unsigned int T3OTL:1; /**< \brief [10:10] Timer T3 Overflow Toggle Latch (rwh) */
+ unsigned int BPS1:2; /**< \brief [12:11] GPT1 Block Prescaler Control (rw) */
+ unsigned int T3EDGE:1; /**< \brief [13:13] Timer T3 Edge Detection Flag (rwh) */
+ unsigned int T3CHDIR:1; /**< \brief [14:14] Timer T3 Count Direction Change Flag (rwh) */
+ unsigned int T3RDIR:1; /**< \brief [15:15] Timer T3 Rotation Direction Flag (rh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GPT12_T3CON_Bits;
+
+/** \brief Timer T4 Register */
+typedef struct _Ifx_GPT12_T4_Bits
+{
+ unsigned int T4:16; /**< \brief [15:0] Timer T4 (rwh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GPT12_T4_Bits;
+
+/** \brief Timer T4 Control Register */
+typedef struct _Ifx_GPT12_T4CON_Bits
+{
+ unsigned int T4I:3; /**< \brief [2:0] Timer T4 Input Parameter Selection (rw) */
+ unsigned int T4M:3; /**< \brief [5:3] Timer T4 Mode Control (Basic Operating Mode) (rw) */
+ unsigned int T4R:1; /**< \brief [6:6] Timer T4 Run Bit (rw) */
+ unsigned int T4UD:1; /**< \brief [7:7] Timer T4 Up/Down Control (rw) */
+ unsigned int T4UDE:1; /**< \brief [8:8] Timer T4 External Up/Down Enable (rw) */
+ unsigned int T4RC:1; /**< \brief [9:9] Timer T4 Remote Control (rw) */
+ unsigned int CLRT2EN:1; /**< \brief [10:10] Clear Timer T2 Enable (rw) */
+ unsigned int CLRT3EN:1; /**< \brief [11:11] Clear Timer T3 Enable (rw) */
+ unsigned int T4IRDIS:1; /**< \brief [12:12] Timer T4 Interrupt Disable (rw) */
+ unsigned int T4EDGE:1; /**< \brief [13:13] Timer T4 Edge Detection (rwh) */
+ unsigned int T4CHDIR:1; /**< \brief [14:14] Timer T4 Count Direction Change (rwh) */
+ unsigned int T4RDIR:1; /**< \brief [15:15] Timer T4 Rotation Direction (rh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GPT12_T4CON_Bits;
+
+/** \brief Timer T5 Register */
+typedef struct _Ifx_GPT12_T5_Bits
+{
+ unsigned int T5:16; /**< \brief [15:0] Timer T5 (rwh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GPT12_T5_Bits;
+
+/** \brief Timer T5 Control Register */
+typedef struct _Ifx_GPT12_T5CON_Bits
+{
+ unsigned int T5I:3; /**< \brief [2:0] Timer T5 Input Parameter Selection (rw) */
+ unsigned int T5M:3; /**< \brief [5:3] Timer T5 Mode Control (Basic Operating Mode) (rw) */
+ unsigned int T5R:1; /**< \brief [6:6] Timer T5 Run Bit (rw) */
+ unsigned int T5UD:1; /**< \brief [7:7] Timer T5 Up/Down Control (rw) */
+ unsigned int T5UDE:1; /**< \brief [8:8] Timer T5 External Up/Down Enable (rw) */
+ unsigned int T5RC:1; /**< \brief [9:9] Timer T5 Remote Control (rw) */
+ unsigned int CT3:1; /**< \brief [10:10] Timer T3 Capture Trigger Enable (rw) */
+ unsigned int reserved_11:1; /**< \brief \internal Reserved */
+ unsigned int CI:2; /**< \brief [13:12] Register CAPREL Capture Trigger Selection (rw) */
+ unsigned int T5CLR:1; /**< \brief [14:14] Timer T5 Clear Enable Bit (rw) */
+ unsigned int T5SC:1; /**< \brief [15:15] Timer T5 Capture Mode Enable (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GPT12_T5CON_Bits;
+
+/** \brief Timer T6 Register */
+typedef struct _Ifx_GPT12_T6_Bits
+{
+ unsigned int T6:16; /**< \brief [15:0] Timer T6 (rwh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GPT12_T6_Bits;
+
+/** \brief Timer T6 Control Register */
+typedef struct _Ifx_GPT12_T6CON_Bits
+{
+ unsigned int T6I:3; /**< \brief [2:0] Timer T6 Input Parameter Selection (rw) */
+ unsigned int T6M:3; /**< \brief [5:3] Timer T6 Mode Control (Basic Operating Mode) (rw) */
+ unsigned int T6R:1; /**< \brief [6:6] Timer T6 Run Bit (rw) */
+ unsigned int T6UD:1; /**< \brief [7:7] Timer T6 Up/Down Control (rw) */
+ unsigned int T6UDE:1; /**< \brief [8:8] Timer T6 External Up/Down Enable (rw) */
+ unsigned int T6OE:1; /**< \brief [9:9] Overflow/Underflow Output Enable (rw) */
+ unsigned int T6OTL:1; /**< \brief [10:10] Timer T6 Overflow Toggle Latch (rwh) */
+ unsigned int BPS2:2; /**< \brief [12:11] GPT2 Block Prescaler Control (rw) */
+ unsigned int reserved_13:1; /**< \brief \internal Reserved */
+ unsigned int T6CLR:1; /**< \brief [14:14] Timer T6 Clear Enable Bit (rw) */
+ unsigned int T6SR:1; /**< \brief [15:15] Timer T6 Reload Mode Enable (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GPT12_T6CON_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Gpt12_union
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GPT12_ACCEN0_Bits B; /**< \brief Bitfield access */
+} Ifx_GPT12_ACCEN0;
+
+/** \brief Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GPT12_ACCEN1_Bits B; /**< \brief Bitfield access */
+} Ifx_GPT12_ACCEN1;
+
+/** \brief Capture and Reload Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GPT12_CAPREL_Bits B; /**< \brief Bitfield access */
+} Ifx_GPT12_CAPREL;
+
+/** \brief Clock Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GPT12_CLC_Bits B; /**< \brief Bitfield access */
+} Ifx_GPT12_CLC;
+
+/** \brief Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GPT12_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_GPT12_ID;
+
+/** \brief Kernel Reset Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GPT12_KRST0_Bits B; /**< \brief Bitfield access */
+} Ifx_GPT12_KRST0;
+
+/** \brief Kernel Reset Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GPT12_KRST1_Bits B; /**< \brief Bitfield access */
+} Ifx_GPT12_KRST1;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GPT12_KRSTCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_GPT12_KRSTCLR;
+
+/** \brief OCDS Control and Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GPT12_OCS_Bits B; /**< \brief Bitfield access */
+} Ifx_GPT12_OCS;
+
+/** \brief Port Input Select Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GPT12_PISEL_Bits B; /**< \brief Bitfield access */
+} Ifx_GPT12_PISEL;
+
+/** \brief Timer T2 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GPT12_T2_Bits B; /**< \brief Bitfield access */
+} Ifx_GPT12_T2;
+
+/** \brief Timer T2 Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GPT12_T2CON_Bits B; /**< \brief Bitfield access */
+} Ifx_GPT12_T2CON;
+
+/** \brief Timer T3 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GPT12_T3_Bits B; /**< \brief Bitfield access */
+} Ifx_GPT12_T3;
+
+/** \brief Timer T3 Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GPT12_T3CON_Bits B; /**< \brief Bitfield access */
+} Ifx_GPT12_T3CON;
+
+/** \brief Timer T4 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GPT12_T4_Bits B; /**< \brief Bitfield access */
+} Ifx_GPT12_T4;
+
+/** \brief Timer T4 Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GPT12_T4CON_Bits B; /**< \brief Bitfield access */
+} Ifx_GPT12_T4CON;
+
+/** \brief Timer T5 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GPT12_T5_Bits B; /**< \brief Bitfield access */
+} Ifx_GPT12_T5;
+
+/** \brief Timer T5 Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GPT12_T5CON_Bits B; /**< \brief Bitfield access */
+} Ifx_GPT12_T5CON;
+
+/** \brief Timer T6 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GPT12_T6_Bits B; /**< \brief Bitfield access */
+} Ifx_GPT12_T6;
+
+/** \brief Timer T6 Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GPT12_T6CON_Bits B; /**< \brief Bitfield access */
+} Ifx_GPT12_T6CON;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Gpt12_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief GPT12 object */
+typedef volatile struct _Ifx_GPT12
+{
+ Ifx_GPT12_CLC CLC; /**< \brief 0, Clock Control Register */
+ Ifx_GPT12_PISEL PISEL; /**< \brief 4, Port Input Select Register */
+ Ifx_GPT12_ID ID; /**< \brief 8, Identification Register */
+ unsigned char reserved_C[4]; /**< \brief C, \internal Reserved */
+ Ifx_GPT12_T2CON T2CON; /**< \brief 10, Timer T2 Control Register */
+ Ifx_GPT12_T3CON T3CON; /**< \brief 14, Timer T3 Control Register */
+ Ifx_GPT12_T4CON T4CON; /**< \brief 18, Timer T4 Control Register */
+ Ifx_GPT12_T5CON T5CON; /**< \brief 1C, Timer T5 Control Register */
+ Ifx_GPT12_T6CON T6CON; /**< \brief 20, Timer T6 Control Register */
+ unsigned char reserved_24[12]; /**< \brief 24, \internal Reserved */
+ Ifx_GPT12_CAPREL CAPREL; /**< \brief 30, Capture and Reload Register */
+ Ifx_GPT12_T2 T2; /**< \brief 34, Timer T2 Register */
+ Ifx_GPT12_T3 T3; /**< \brief 38, Timer T3 Register */
+ Ifx_GPT12_T4 T4; /**< \brief 3C, Timer T4 Register */
+ Ifx_GPT12_T5 T5; /**< \brief 40, Timer T5 Register */
+ Ifx_GPT12_T6 T6; /**< \brief 44, Timer T6 Register */
+ unsigned char reserved_48[160]; /**< \brief 48, \internal Reserved */
+ Ifx_GPT12_OCS OCS; /**< \brief E8, OCDS Control and Status Register */
+ Ifx_GPT12_KRSTCLR KRSTCLR; /**< \brief EC, Kernel Reset Status Clear Register */
+ Ifx_GPT12_KRST1 KRST1; /**< \brief F0, Kernel Reset Register 1 */
+ Ifx_GPT12_KRST0 KRST0; /**< \brief F4, Kernel Reset Register 0 */
+ Ifx_GPT12_ACCEN1 ACCEN1; /**< \brief F8, Access Enable Register 1 */
+ Ifx_GPT12_ACCEN0 ACCEN0; /**< \brief FC, Access Enable Register 0 */
+} Ifx_GPT12;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXGPT12_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxGtm_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxGtm_bf.h
new file mode 100644
index 0000000..f3eaea2
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxGtm_bf.h
@@ -0,0 +1,18756 @@
+/**
+ * \file IfxGtm_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Gtm_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Gtm
+ *
+ */
+#ifndef IFXGTM_BF_H
+#define IFXGTM_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Gtm_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN0 */
+#define IFX_GTM_ACCEN0_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN0 */
+#define IFX_GTM_ACCEN0_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN0 */
+#define IFX_GTM_ACCEN0_EN0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN10 */
+#define IFX_GTM_ACCEN0_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN10 */
+#define IFX_GTM_ACCEN0_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN10 */
+#define IFX_GTM_ACCEN0_EN10_OFF (10u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN11 */
+#define IFX_GTM_ACCEN0_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN11 */
+#define IFX_GTM_ACCEN0_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN11 */
+#define IFX_GTM_ACCEN0_EN11_OFF (11u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN12 */
+#define IFX_GTM_ACCEN0_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN12 */
+#define IFX_GTM_ACCEN0_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN12 */
+#define IFX_GTM_ACCEN0_EN12_OFF (12u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN13 */
+#define IFX_GTM_ACCEN0_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN13 */
+#define IFX_GTM_ACCEN0_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN13 */
+#define IFX_GTM_ACCEN0_EN13_OFF (13u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN14 */
+#define IFX_GTM_ACCEN0_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN14 */
+#define IFX_GTM_ACCEN0_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN14 */
+#define IFX_GTM_ACCEN0_EN14_OFF (14u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN15 */
+#define IFX_GTM_ACCEN0_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN15 */
+#define IFX_GTM_ACCEN0_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN15 */
+#define IFX_GTM_ACCEN0_EN15_OFF (15u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN16 */
+#define IFX_GTM_ACCEN0_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN16 */
+#define IFX_GTM_ACCEN0_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN16 */
+#define IFX_GTM_ACCEN0_EN16_OFF (16u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN17 */
+#define IFX_GTM_ACCEN0_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN17 */
+#define IFX_GTM_ACCEN0_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN17 */
+#define IFX_GTM_ACCEN0_EN17_OFF (17u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN18 */
+#define IFX_GTM_ACCEN0_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN18 */
+#define IFX_GTM_ACCEN0_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN18 */
+#define IFX_GTM_ACCEN0_EN18_OFF (18u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN19 */
+#define IFX_GTM_ACCEN0_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN19 */
+#define IFX_GTM_ACCEN0_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN19 */
+#define IFX_GTM_ACCEN0_EN19_OFF (19u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN1 */
+#define IFX_GTM_ACCEN0_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN1 */
+#define IFX_GTM_ACCEN0_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN1 */
+#define IFX_GTM_ACCEN0_EN1_OFF (1u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN20 */
+#define IFX_GTM_ACCEN0_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN20 */
+#define IFX_GTM_ACCEN0_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN20 */
+#define IFX_GTM_ACCEN0_EN20_OFF (20u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN21 */
+#define IFX_GTM_ACCEN0_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN21 */
+#define IFX_GTM_ACCEN0_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN21 */
+#define IFX_GTM_ACCEN0_EN21_OFF (21u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN22 */
+#define IFX_GTM_ACCEN0_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN22 */
+#define IFX_GTM_ACCEN0_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN22 */
+#define IFX_GTM_ACCEN0_EN22_OFF (22u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN23 */
+#define IFX_GTM_ACCEN0_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN23 */
+#define IFX_GTM_ACCEN0_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN23 */
+#define IFX_GTM_ACCEN0_EN23_OFF (23u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN24 */
+#define IFX_GTM_ACCEN0_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN24 */
+#define IFX_GTM_ACCEN0_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN24 */
+#define IFX_GTM_ACCEN0_EN24_OFF (24u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN25 */
+#define IFX_GTM_ACCEN0_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN25 */
+#define IFX_GTM_ACCEN0_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN25 */
+#define IFX_GTM_ACCEN0_EN25_OFF (25u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN26 */
+#define IFX_GTM_ACCEN0_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN26 */
+#define IFX_GTM_ACCEN0_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN26 */
+#define IFX_GTM_ACCEN0_EN26_OFF (26u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN27 */
+#define IFX_GTM_ACCEN0_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN27 */
+#define IFX_GTM_ACCEN0_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN27 */
+#define IFX_GTM_ACCEN0_EN27_OFF (27u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN28 */
+#define IFX_GTM_ACCEN0_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN28 */
+#define IFX_GTM_ACCEN0_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN28 */
+#define IFX_GTM_ACCEN0_EN28_OFF (28u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN29 */
+#define IFX_GTM_ACCEN0_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN29 */
+#define IFX_GTM_ACCEN0_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN29 */
+#define IFX_GTM_ACCEN0_EN29_OFF (29u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN2 */
+#define IFX_GTM_ACCEN0_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN2 */
+#define IFX_GTM_ACCEN0_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN2 */
+#define IFX_GTM_ACCEN0_EN2_OFF (2u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN30 */
+#define IFX_GTM_ACCEN0_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN30 */
+#define IFX_GTM_ACCEN0_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN30 */
+#define IFX_GTM_ACCEN0_EN30_OFF (30u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN31 */
+#define IFX_GTM_ACCEN0_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN31 */
+#define IFX_GTM_ACCEN0_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN31 */
+#define IFX_GTM_ACCEN0_EN31_OFF (31u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN3 */
+#define IFX_GTM_ACCEN0_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN3 */
+#define IFX_GTM_ACCEN0_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN3 */
+#define IFX_GTM_ACCEN0_EN3_OFF (3u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN4 */
+#define IFX_GTM_ACCEN0_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN4 */
+#define IFX_GTM_ACCEN0_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN4 */
+#define IFX_GTM_ACCEN0_EN4_OFF (4u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN5 */
+#define IFX_GTM_ACCEN0_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN5 */
+#define IFX_GTM_ACCEN0_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN5 */
+#define IFX_GTM_ACCEN0_EN5_OFF (5u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN6 */
+#define IFX_GTM_ACCEN0_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN6 */
+#define IFX_GTM_ACCEN0_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN6 */
+#define IFX_GTM_ACCEN0_EN6_OFF (6u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN7 */
+#define IFX_GTM_ACCEN0_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN7 */
+#define IFX_GTM_ACCEN0_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN7 */
+#define IFX_GTM_ACCEN0_EN7_OFF (7u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN8 */
+#define IFX_GTM_ACCEN0_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN8 */
+#define IFX_GTM_ACCEN0_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN8 */
+#define IFX_GTM_ACCEN0_EN8_OFF (8u)
+
+/** \brief Length for Ifx_GTM_ACCEN0_Bits.EN9 */
+#define IFX_GTM_ACCEN0_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ACCEN0_Bits.EN9 */
+#define IFX_GTM_ACCEN0_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ACCEN0_Bits.EN9 */
+#define IFX_GTM_ACCEN0_EN9_OFF (9u)
+
+/** \brief Length for Ifx_GTM_ADCTRIG0OUT0_Bits.SEL0 */
+#define IFX_GTM_ADCTRIG0OUT0_SEL0_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_ADCTRIG0OUT0_Bits.SEL0 */
+#define IFX_GTM_ADCTRIG0OUT0_SEL0_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_ADCTRIG0OUT0_Bits.SEL0 */
+#define IFX_GTM_ADCTRIG0OUT0_SEL0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ADCTRIG0OUT0_Bits.SEL1 */
+#define IFX_GTM_ADCTRIG0OUT0_SEL1_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_ADCTRIG0OUT0_Bits.SEL1 */
+#define IFX_GTM_ADCTRIG0OUT0_SEL1_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_ADCTRIG0OUT0_Bits.SEL1 */
+#define IFX_GTM_ADCTRIG0OUT0_SEL1_OFF (4u)
+
+/** \brief Length for Ifx_GTM_ADCTRIG0OUT0_Bits.SEL2 */
+#define IFX_GTM_ADCTRIG0OUT0_SEL2_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_ADCTRIG0OUT0_Bits.SEL2 */
+#define IFX_GTM_ADCTRIG0OUT0_SEL2_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_ADCTRIG0OUT0_Bits.SEL2 */
+#define IFX_GTM_ADCTRIG0OUT0_SEL2_OFF (8u)
+
+/** \brief Length for Ifx_GTM_ADCTRIG0OUT0_Bits.SEL3 */
+#define IFX_GTM_ADCTRIG0OUT0_SEL3_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_ADCTRIG0OUT0_Bits.SEL3 */
+#define IFX_GTM_ADCTRIG0OUT0_SEL3_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_ADCTRIG0OUT0_Bits.SEL3 */
+#define IFX_GTM_ADCTRIG0OUT0_SEL3_OFF (12u)
+
+/** \brief Length for Ifx_GTM_ADCTRIG0OUT0_Bits.SEL4 */
+#define IFX_GTM_ADCTRIG0OUT0_SEL4_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_ADCTRIG0OUT0_Bits.SEL4 */
+#define IFX_GTM_ADCTRIG0OUT0_SEL4_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_ADCTRIG0OUT0_Bits.SEL4 */
+#define IFX_GTM_ADCTRIG0OUT0_SEL4_OFF (16u)
+
+/** \brief Length for Ifx_GTM_ADCTRIG1OUT0_Bits.SEL0 */
+#define IFX_GTM_ADCTRIG1OUT0_SEL0_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_ADCTRIG1OUT0_Bits.SEL0 */
+#define IFX_GTM_ADCTRIG1OUT0_SEL0_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_ADCTRIG1OUT0_Bits.SEL0 */
+#define IFX_GTM_ADCTRIG1OUT0_SEL0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ADCTRIG1OUT0_Bits.SEL1 */
+#define IFX_GTM_ADCTRIG1OUT0_SEL1_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_ADCTRIG1OUT0_Bits.SEL1 */
+#define IFX_GTM_ADCTRIG1OUT0_SEL1_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_ADCTRIG1OUT0_Bits.SEL1 */
+#define IFX_GTM_ADCTRIG1OUT0_SEL1_OFF (4u)
+
+/** \brief Length for Ifx_GTM_ADCTRIG1OUT0_Bits.SEL2 */
+#define IFX_GTM_ADCTRIG1OUT0_SEL2_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_ADCTRIG1OUT0_Bits.SEL2 */
+#define IFX_GTM_ADCTRIG1OUT0_SEL2_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_ADCTRIG1OUT0_Bits.SEL2 */
+#define IFX_GTM_ADCTRIG1OUT0_SEL2_OFF (8u)
+
+/** \brief Length for Ifx_GTM_ADCTRIG1OUT0_Bits.SEL3 */
+#define IFX_GTM_ADCTRIG1OUT0_SEL3_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_ADCTRIG1OUT0_Bits.SEL3 */
+#define IFX_GTM_ADCTRIG1OUT0_SEL3_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_ADCTRIG1OUT0_Bits.SEL3 */
+#define IFX_GTM_ADCTRIG1OUT0_SEL3_OFF (12u)
+
+/** \brief Length for Ifx_GTM_ADCTRIG1OUT0_Bits.SEL4 */
+#define IFX_GTM_ADCTRIG1OUT0_SEL4_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_ADCTRIG1OUT0_Bits.SEL4 */
+#define IFX_GTM_ADCTRIG1OUT0_SEL4_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_ADCTRIG1OUT0_Bits.SEL4 */
+#define IFX_GTM_ADCTRIG1OUT0_SEL4_OFF (16u)
+
+/** \brief Length for Ifx_GTM_AEI_ADDR_XPT_Bits.TO_ADDR */
+#define IFX_GTM_AEI_ADDR_XPT_TO_ADDR_LEN (20u)
+
+/** \brief Mask for Ifx_GTM_AEI_ADDR_XPT_Bits.TO_ADDR */
+#define IFX_GTM_AEI_ADDR_XPT_TO_ADDR_MSK (0xfffffu)
+
+/** \brief Offset for Ifx_GTM_AEI_ADDR_XPT_Bits.TO_ADDR */
+#define IFX_GTM_AEI_ADDR_XPT_TO_ADDR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_AEI_ADDR_XPT_Bits.TO_W1R0 */
+#define IFX_GTM_AEI_ADDR_XPT_TO_W1R0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_AEI_ADDR_XPT_Bits.TO_W1R0 */
+#define IFX_GTM_AEI_ADDR_XPT_TO_W1R0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_AEI_ADDR_XPT_Bits.TO_W1R0 */
+#define IFX_GTM_AEI_ADDR_XPT_TO_W1R0_OFF (20u)
+
+/** \brief Length for Ifx_GTM_AFD_CH_BUF_ACC_Bits.DATA */
+#define IFX_GTM_AFD_CH_BUF_ACC_DATA_LEN (29u)
+
+/** \brief Mask for Ifx_GTM_AFD_CH_BUF_ACC_Bits.DATA */
+#define IFX_GTM_AFD_CH_BUF_ACC_DATA_MSK (0x1fffffffu)
+
+/** \brief Offset for Ifx_GTM_AFD_CH_BUF_ACC_Bits.DATA */
+#define IFX_GTM_AFD_CH_BUF_ACC_DATA_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ARU_ARU_ACCESS_Bits.ADDR */
+#define IFX_GTM_ARU_ARU_ACCESS_ADDR_LEN (9u)
+
+/** \brief Mask for Ifx_GTM_ARU_ARU_ACCESS_Bits.ADDR */
+#define IFX_GTM_ARU_ARU_ACCESS_ADDR_MSK (0x1ffu)
+
+/** \brief Offset for Ifx_GTM_ARU_ARU_ACCESS_Bits.ADDR */
+#define IFX_GTM_ARU_ARU_ACCESS_ADDR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ARU_ARU_ACCESS_Bits.RREQ */
+#define IFX_GTM_ARU_ARU_ACCESS_RREQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ARU_ARU_ACCESS_Bits.RREQ */
+#define IFX_GTM_ARU_ARU_ACCESS_RREQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ARU_ARU_ACCESS_Bits.RREQ */
+#define IFX_GTM_ARU_ARU_ACCESS_RREQ_OFF (12u)
+
+/** \brief Length for Ifx_GTM_ARU_ARU_ACCESS_Bits.WREQ */
+#define IFX_GTM_ARU_ARU_ACCESS_WREQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ARU_ARU_ACCESS_Bits.WREQ */
+#define IFX_GTM_ARU_ARU_ACCESS_WREQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ARU_ARU_ACCESS_Bits.WREQ */
+#define IFX_GTM_ARU_ARU_ACCESS_WREQ_OFF (13u)
+
+/** \brief Length for Ifx_GTM_ARU_DATA_H_Bits.DATA */
+#define IFX_GTM_ARU_DATA_H_DATA_LEN (29u)
+
+/** \brief Mask for Ifx_GTM_ARU_DATA_H_Bits.DATA */
+#define IFX_GTM_ARU_DATA_H_DATA_MSK (0x1fffffffu)
+
+/** \brief Offset for Ifx_GTM_ARU_DATA_H_Bits.DATA */
+#define IFX_GTM_ARU_DATA_H_DATA_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ARU_DATA_L_Bits.DATA */
+#define IFX_GTM_ARU_DATA_L_DATA_LEN (29u)
+
+/** \brief Mask for Ifx_GTM_ARU_DATA_L_Bits.DATA */
+#define IFX_GTM_ARU_DATA_L_DATA_MSK (0x1fffffffu)
+
+/** \brief Offset for Ifx_GTM_ARU_DATA_L_Bits.DATA */
+#define IFX_GTM_ARU_DATA_L_DATA_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ARU_DBG_ACCESS0_Bits.ADDR */
+#define IFX_GTM_ARU_DBG_ACCESS0_ADDR_LEN (9u)
+
+/** \brief Mask for Ifx_GTM_ARU_DBG_ACCESS0_Bits.ADDR */
+#define IFX_GTM_ARU_DBG_ACCESS0_ADDR_MSK (0x1ffu)
+
+/** \brief Offset for Ifx_GTM_ARU_DBG_ACCESS0_Bits.ADDR */
+#define IFX_GTM_ARU_DBG_ACCESS0_ADDR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ARU_DBG_ACCESS1_Bits.ADDR */
+#define IFX_GTM_ARU_DBG_ACCESS1_ADDR_LEN (9u)
+
+/** \brief Mask for Ifx_GTM_ARU_DBG_ACCESS1_Bits.ADDR */
+#define IFX_GTM_ARU_DBG_ACCESS1_ADDR_MSK (0x1ffu)
+
+/** \brief Offset for Ifx_GTM_ARU_DBG_ACCESS1_Bits.ADDR */
+#define IFX_GTM_ARU_DBG_ACCESS1_ADDR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ARU_DBG_DATA0_H_Bits.DATA */
+#define IFX_GTM_ARU_DBG_DATA0_H_DATA_LEN (29u)
+
+/** \brief Mask for Ifx_GTM_ARU_DBG_DATA0_H_Bits.DATA */
+#define IFX_GTM_ARU_DBG_DATA0_H_DATA_MSK (0x1fffffffu)
+
+/** \brief Offset for Ifx_GTM_ARU_DBG_DATA0_H_Bits.DATA */
+#define IFX_GTM_ARU_DBG_DATA0_H_DATA_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ARU_DBG_DATA0_L_Bits.DATA */
+#define IFX_GTM_ARU_DBG_DATA0_L_DATA_LEN (29u)
+
+/** \brief Mask for Ifx_GTM_ARU_DBG_DATA0_L_Bits.DATA */
+#define IFX_GTM_ARU_DBG_DATA0_L_DATA_MSK (0x1fffffffu)
+
+/** \brief Offset for Ifx_GTM_ARU_DBG_DATA0_L_Bits.DATA */
+#define IFX_GTM_ARU_DBG_DATA0_L_DATA_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ARU_DBG_DATA1_H_Bits.DATA */
+#define IFX_GTM_ARU_DBG_DATA1_H_DATA_LEN (29u)
+
+/** \brief Mask for Ifx_GTM_ARU_DBG_DATA1_H_Bits.DATA */
+#define IFX_GTM_ARU_DBG_DATA1_H_DATA_MSK (0x1fffffffu)
+
+/** \brief Offset for Ifx_GTM_ARU_DBG_DATA1_H_Bits.DATA */
+#define IFX_GTM_ARU_DBG_DATA1_H_DATA_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ARU_DBG_DATA1_L_Bits.DATA */
+#define IFX_GTM_ARU_DBG_DATA1_L_DATA_LEN (29u)
+
+/** \brief Mask for Ifx_GTM_ARU_DBG_DATA1_L_Bits.DATA */
+#define IFX_GTM_ARU_DBG_DATA1_L_DATA_MSK (0x1fffffffu)
+
+/** \brief Offset for Ifx_GTM_ARU_DBG_DATA1_L_Bits.DATA */
+#define IFX_GTM_ARU_DBG_DATA1_L_DATA_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ARU_IRQ_EN_Bits.ACC_ACK_IRQ_EN */
+#define IFX_GTM_ARU_IRQ_EN_ACC_ACK_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ARU_IRQ_EN_Bits.ACC_ACK_IRQ_EN */
+#define IFX_GTM_ARU_IRQ_EN_ACC_ACK_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ARU_IRQ_EN_Bits.ACC_ACK_IRQ_EN */
+#define IFX_GTM_ARU_IRQ_EN_ACC_ACK_IRQ_EN_OFF (2u)
+
+/** \brief Length for Ifx_GTM_ARU_IRQ_EN_Bits.NEW_DATA0_IRQ_EN */
+#define IFX_GTM_ARU_IRQ_EN_NEW_DATA0_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ARU_IRQ_EN_Bits.NEW_DATA0_IRQ_EN */
+#define IFX_GTM_ARU_IRQ_EN_NEW_DATA0_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ARU_IRQ_EN_Bits.NEW_DATA0_IRQ_EN */
+#define IFX_GTM_ARU_IRQ_EN_NEW_DATA0_IRQ_EN_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ARU_IRQ_EN_Bits.NEW_DATA1_IRQ_EN */
+#define IFX_GTM_ARU_IRQ_EN_NEW_DATA1_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ARU_IRQ_EN_Bits.NEW_DATA1_IRQ_EN */
+#define IFX_GTM_ARU_IRQ_EN_NEW_DATA1_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ARU_IRQ_EN_Bits.NEW_DATA1_IRQ_EN */
+#define IFX_GTM_ARU_IRQ_EN_NEW_DATA1_IRQ_EN_OFF (1u)
+
+/** \brief Length for Ifx_GTM_ARU_IRQ_FORCINT_Bits.TRG_ACC_ACK */
+#define IFX_GTM_ARU_IRQ_FORCINT_TRG_ACC_ACK_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ARU_IRQ_FORCINT_Bits.TRG_ACC_ACK */
+#define IFX_GTM_ARU_IRQ_FORCINT_TRG_ACC_ACK_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ARU_IRQ_FORCINT_Bits.TRG_ACC_ACK */
+#define IFX_GTM_ARU_IRQ_FORCINT_TRG_ACC_ACK_OFF (2u)
+
+/** \brief Length for Ifx_GTM_ARU_IRQ_FORCINT_Bits.TRG_NEW_DATA0 */
+#define IFX_GTM_ARU_IRQ_FORCINT_TRG_NEW_DATA0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ARU_IRQ_FORCINT_Bits.TRG_NEW_DATA0 */
+#define IFX_GTM_ARU_IRQ_FORCINT_TRG_NEW_DATA0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ARU_IRQ_FORCINT_Bits.TRG_NEW_DATA0 */
+#define IFX_GTM_ARU_IRQ_FORCINT_TRG_NEW_DATA0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ARU_IRQ_FORCINT_Bits.TRG_NEW_DATA */
+#define IFX_GTM_ARU_IRQ_FORCINT_TRG_NEW_DATA_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ARU_IRQ_FORCINT_Bits.TRG_NEW_DATA */
+#define IFX_GTM_ARU_IRQ_FORCINT_TRG_NEW_DATA_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ARU_IRQ_FORCINT_Bits.TRG_NEW_DATA */
+#define IFX_GTM_ARU_IRQ_FORCINT_TRG_NEW_DATA_OFF (1u)
+
+/** \brief Length for Ifx_GTM_ARU_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_ARU_IRQ_MODE_IRQ_MODE_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ARU_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_ARU_IRQ_MODE_IRQ_MODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ARU_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_ARU_IRQ_MODE_IRQ_MODE_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ARU_IRQ_NOTIFY_Bits.ACC_ACK */
+#define IFX_GTM_ARU_IRQ_NOTIFY_ACC_ACK_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ARU_IRQ_NOTIFY_Bits.ACC_ACK */
+#define IFX_GTM_ARU_IRQ_NOTIFY_ACC_ACK_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ARU_IRQ_NOTIFY_Bits.ACC_ACK */
+#define IFX_GTM_ARU_IRQ_NOTIFY_ACC_ACK_OFF (2u)
+
+/** \brief Length for Ifx_GTM_ARU_IRQ_NOTIFY_Bits.NEW_DATA0 */
+#define IFX_GTM_ARU_IRQ_NOTIFY_NEW_DATA0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ARU_IRQ_NOTIFY_Bits.NEW_DATA0 */
+#define IFX_GTM_ARU_IRQ_NOTIFY_NEW_DATA0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ARU_IRQ_NOTIFY_Bits.NEW_DATA0 */
+#define IFX_GTM_ARU_IRQ_NOTIFY_NEW_DATA0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ARU_IRQ_NOTIFY_Bits.NEW_DATA1 */
+#define IFX_GTM_ARU_IRQ_NOTIFY_NEW_DATA1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ARU_IRQ_NOTIFY_Bits.NEW_DATA1 */
+#define IFX_GTM_ARU_IRQ_NOTIFY_NEW_DATA1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ARU_IRQ_NOTIFY_Bits.NEW_DATA1 */
+#define IFX_GTM_ARU_IRQ_NOTIFY_NEW_DATA1_OFF (1u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_ACT_TB_Bits.ACT_TB */
+#define IFX_GTM_ATOM_AGC_ACT_TB_ACT_TB_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_ACT_TB_Bits.ACT_TB */
+#define IFX_GTM_ATOM_AGC_ACT_TB_ACT_TB_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_ACT_TB_Bits.ACT_TB */
+#define IFX_GTM_ATOM_AGC_ACT_TB_ACT_TB_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_ACT_TB_Bits.TB_TRIG */
+#define IFX_GTM_ATOM_AGC_ACT_TB_TB_TRIG_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_ACT_TB_Bits.TB_TRIG */
+#define IFX_GTM_ATOM_AGC_ACT_TB_TB_TRIG_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_ACT_TB_Bits.TB_TRIG */
+#define IFX_GTM_ATOM_AGC_ACT_TB_TB_TRIG_OFF (24u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_ACT_TB_Bits.TBU_SEL */
+#define IFX_GTM_ATOM_AGC_ACT_TB_TBU_SEL_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_ACT_TB_Bits.TBU_SEL */
+#define IFX_GTM_ATOM_AGC_ACT_TB_TBU_SEL_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_ACT_TB_Bits.TBU_SEL */
+#define IFX_GTM_ATOM_AGC_ACT_TB_TBU_SEL_OFF (25u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL0 */
+#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL0 */
+#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL0 */
+#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL1 */
+#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL1 */
+#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL1 */
+#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL2 */
+#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL2 */
+#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL2 */
+#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL2_OFF (4u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL3 */
+#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL3 */
+#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL3 */
+#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL3_OFF (6u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL4 */
+#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL4 */
+#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL4 */
+#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL4_OFF (8u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL5 */
+#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL5 */
+#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL5 */
+#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL5_OFF (10u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL6 */
+#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL6 */
+#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL6 */
+#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL6_OFF (12u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL7 */
+#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL7 */
+#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL7 */
+#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL7_OFF (14u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT0 */
+#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT0 */
+#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT0 */
+#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT1 */
+#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT1 */
+#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT1 */
+#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT2 */
+#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT2 */
+#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT2 */
+#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT2_OFF (4u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT3 */
+#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT3 */
+#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT3 */
+#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT3_OFF (6u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT4 */
+#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT4 */
+#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT4 */
+#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT4_OFF (8u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT5 */
+#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT5 */
+#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT5 */
+#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT5_OFF (10u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT6 */
+#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT6 */
+#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT6 */
+#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT6_OFF (12u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT7 */
+#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT7 */
+#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT7 */
+#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT7_OFF (14u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL0 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL0 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL0 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL1 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL1 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL1 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL2 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL2 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL2 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL2_OFF (4u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL3 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL3 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL3 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL3_OFF (6u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL4 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL4 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL4 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL4_OFF (8u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL5 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL5 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL5 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL5_OFF (10u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL6 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL6 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL6 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL6_OFF (12u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL7 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL7 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL7 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL7_OFF (14u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH0 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH0 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH0 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH0_OFF (16u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH1 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH1 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH1 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH1_OFF (18u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH2 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH2 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH2 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH2_OFF (20u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH3 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH3 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH3 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH3_OFF (22u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH4 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH4 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH4 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH4_OFF (24u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH5 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH5 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH5 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH5_OFF (26u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH6 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH6 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH6 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH6_OFF (28u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH7 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH7 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH7 */
+#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH7_OFF (30u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.HOST_TRIG */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_HOST_TRIG_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.HOST_TRIG */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_HOST_TRIG_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.HOST_TRIG */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_HOST_TRIG_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH0 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH0 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH0 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH0_OFF (8u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH1 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH1 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH1 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH1_OFF (9u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH2 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH2 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH2 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH2_OFF (10u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH3 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH3 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH3 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH3_OFF (11u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH4 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH4 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH4 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH4_OFF (12u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH5 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH5 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH5 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH5_OFF (13u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH6 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH6 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH6 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH6_OFF (14u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH7 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH7 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH7 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH7_OFF (15u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL0 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL0 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL0 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL0_OFF (16u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL1 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL1 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL1 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL1_OFF (18u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL2 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL2 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL2 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL2_OFF (20u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL3 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL3 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL3 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL3_OFF (22u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL4 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL4 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL4 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL4_OFF (24u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL5 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL5 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL5 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL5_OFF (26u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL6 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL6 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL6 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL6_OFF (28u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL7 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL7 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL7 */
+#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL7_OFF (30u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG0 */
+#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG0 */
+#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG0 */
+#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG1 */
+#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG1 */
+#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG1 */
+#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG2 */
+#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG2 */
+#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG2 */
+#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG2_OFF (4u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG3 */
+#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG3 */
+#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG3 */
+#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG3_OFF (6u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG4 */
+#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG4 */
+#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG4 */
+#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG4_OFF (8u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG5 */
+#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG5 */
+#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG5 */
+#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG5_OFF (10u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG6 */
+#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG6 */
+#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG6 */
+#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG6_OFF (12u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG7 */
+#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG7 */
+#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG7 */
+#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG7_OFF (14u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL0 */
+#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL0 */
+#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL0 */
+#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL1 */
+#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL1 */
+#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL1 */
+#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL2 */
+#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL2 */
+#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL2 */
+#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL2_OFF (4u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL3 */
+#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL3 */
+#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL3 */
+#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL3_OFF (6u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL4 */
+#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL4 */
+#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL4 */
+#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL4_OFF (8u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL5 */
+#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL5 */
+#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL5 */
+#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL5_OFF (10u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL6 */
+#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL6 */
+#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL6 */
+#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL6_OFF (12u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL7 */
+#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL7 */
+#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL7 */
+#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL7_OFF (14u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT0 */
+#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT0 */
+#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT0 */
+#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT1 */
+#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT1 */
+#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT1 */
+#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT2 */
+#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT2 */
+#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT2 */
+#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT2_OFF (4u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT3 */
+#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT3 */
+#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT3 */
+#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT3_OFF (6u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT4 */
+#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT4 */
+#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT4 */
+#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT4_OFF (8u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT5 */
+#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT5 */
+#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT5 */
+#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT5_OFF (10u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT6 */
+#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT6 */
+#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT6 */
+#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT6_OFF (12u)
+
+/** \brief Length for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT7 */
+#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT7 */
+#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT7 */
+#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT7_OFF (14u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_CM0_Bits.CM0 */
+#define IFX_GTM_ATOM_CH_CM0_CM0_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_CM0_Bits.CM0 */
+#define IFX_GTM_ATOM_CH_CM0_CM0_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_CM0_Bits.CM0 */
+#define IFX_GTM_ATOM_CH_CM0_CM0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_CM1_Bits.CM1 */
+#define IFX_GTM_ATOM_CH_CM1_CM1_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_CM1_Bits.CM1 */
+#define IFX_GTM_ATOM_CH_CM1_CM1_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_CM1_Bits.CM1 */
+#define IFX_GTM_ATOM_CH_CM1_CM1_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_CN0_Bits.CN0 */
+#define IFX_GTM_ATOM_CH_CN0_CN0_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_CN0_Bits.CN0 */
+#define IFX_GTM_ATOM_CH_CN0_CN0_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_CN0_Bits.CN0 */
+#define IFX_GTM_ATOM_CH_CN0_CN0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_CTRL_Bits.ABM */
+#define IFX_GTM_ATOM_CH_CTRL_ABM_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_CTRL_Bits.ABM */
+#define IFX_GTM_ATOM_CH_CTRL_ABM_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_CTRL_Bits.ABM */
+#define IFX_GTM_ATOM_CH_CTRL_ABM_OFF (27u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_CTRL_Bits.ACB */
+#define IFX_GTM_ATOM_CH_CTRL_ACB_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_CTRL_Bits.ACB */
+#define IFX_GTM_ATOM_CH_CTRL_ACB_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_CTRL_Bits.ACB */
+#define IFX_GTM_ATOM_CH_CTRL_ACB_OFF (4u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_CTRL_Bits.ARU_EN */
+#define IFX_GTM_ATOM_CH_CTRL_ARU_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_CTRL_Bits.ARU_EN */
+#define IFX_GTM_ATOM_CH_CTRL_ARU_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_CTRL_Bits.ARU_EN */
+#define IFX_GTM_ATOM_CH_CTRL_ARU_EN_OFF (3u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_CTRL_Bits.CLK_SRC */
+#define IFX_GTM_ATOM_CH_CTRL_CLK_SRC_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_CTRL_Bits.CLK_SRC */
+#define IFX_GTM_ATOM_CH_CTRL_CLK_SRC_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_CTRL_Bits.CLK_SRC */
+#define IFX_GTM_ATOM_CH_CTRL_CLK_SRC_OFF (12u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_CTRL_Bits.CMP_CTRL */
+#define IFX_GTM_ATOM_CH_CTRL_CMP_CTRL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_CTRL_Bits.CMP_CTRL */
+#define IFX_GTM_ATOM_CH_CTRL_CMP_CTRL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_CTRL_Bits.CMP_CTRL */
+#define IFX_GTM_ATOM_CH_CTRL_CMP_CTRL_OFF (9u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_CTRL_Bits.MODE */
+#define IFX_GTM_ATOM_CH_CTRL_MODE_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_CTRL_Bits.MODE */
+#define IFX_GTM_ATOM_CH_CTRL_MODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_CTRL_Bits.MODE */
+#define IFX_GTM_ATOM_CH_CTRL_MODE_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_CTRL_Bits.OSM */
+#define IFX_GTM_ATOM_CH_CTRL_OSM_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_CTRL_Bits.OSM */
+#define IFX_GTM_ATOM_CH_CTRL_OSM_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_CTRL_Bits.OSM */
+#define IFX_GTM_ATOM_CH_CTRL_OSM_OFF (26u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_CTRL_Bits.RST_CCU0 */
+#define IFX_GTM_ATOM_CH_CTRL_RST_CCU0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_CTRL_Bits.RST_CCU0 */
+#define IFX_GTM_ATOM_CH_CTRL_RST_CCU0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_CTRL_Bits.RST_CCU0 */
+#define IFX_GTM_ATOM_CH_CTRL_RST_CCU0_OFF (20u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_CTRL_Bits.SL */
+#define IFX_GTM_ATOM_CH_CTRL_SL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_CTRL_Bits.SL */
+#define IFX_GTM_ATOM_CH_CTRL_SL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_CTRL_Bits.SL */
+#define IFX_GTM_ATOM_CH_CTRL_SL_OFF (11u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_CTRL_Bits.SLA */
+#define IFX_GTM_ATOM_CH_CTRL_SLA_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_CTRL_Bits.SLA */
+#define IFX_GTM_ATOM_CH_CTRL_SLA_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_CTRL_Bits.SLA */
+#define IFX_GTM_ATOM_CH_CTRL_SLA_OFF (25u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_CTRL_Bits.TB12_SEL */
+#define IFX_GTM_ATOM_CH_CTRL_TB12_SEL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_CTRL_Bits.TB12_SEL */
+#define IFX_GTM_ATOM_CH_CTRL_TB12_SEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_CTRL_Bits.TB12_SEL */
+#define IFX_GTM_ATOM_CH_CTRL_TB12_SEL_OFF (2u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_CTRL_Bits.TRIGOUT */
+#define IFX_GTM_ATOM_CH_CTRL_TRIGOUT_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_CTRL_Bits.TRIGOUT */
+#define IFX_GTM_ATOM_CH_CTRL_TRIGOUT_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_CTRL_Bits.TRIGOUT */
+#define IFX_GTM_ATOM_CH_CTRL_TRIGOUT_OFF (24u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_CTRL_Bits.WR_REQ */
+#define IFX_GTM_ATOM_CH_CTRL_WR_REQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_CTRL_Bits.WR_REQ */
+#define IFX_GTM_ATOM_CH_CTRL_WR_REQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_CTRL_Bits.WR_REQ */
+#define IFX_GTM_ATOM_CH_CTRL_WR_REQ_OFF (16u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_IRQ_EN_Bits.CCU0TC_IRQ_EN */
+#define IFX_GTM_ATOM_CH_IRQ_EN_CCU0TC_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_IRQ_EN_Bits.CCU0TC_IRQ_EN */
+#define IFX_GTM_ATOM_CH_IRQ_EN_CCU0TC_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_IRQ_EN_Bits.CCU0TC_IRQ_EN */
+#define IFX_GTM_ATOM_CH_IRQ_EN_CCU0TC_IRQ_EN_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_IRQ_EN_Bits.CCU1TC_IRQ_EN */
+#define IFX_GTM_ATOM_CH_IRQ_EN_CCU1TC_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_IRQ_EN_Bits.CCU1TC_IRQ_EN */
+#define IFX_GTM_ATOM_CH_IRQ_EN_CCU1TC_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_IRQ_EN_Bits.CCU1TC_IRQ_EN */
+#define IFX_GTM_ATOM_CH_IRQ_EN_CCU1TC_IRQ_EN_OFF (1u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_IRQ_FORCINT_Bits.TRG_CCU0TC */
+#define IFX_GTM_ATOM_CH_IRQ_FORCINT_TRG_CCU0TC_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_IRQ_FORCINT_Bits.TRG_CCU0TC */
+#define IFX_GTM_ATOM_CH_IRQ_FORCINT_TRG_CCU0TC_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_IRQ_FORCINT_Bits.TRG_CCU0TC */
+#define IFX_GTM_ATOM_CH_IRQ_FORCINT_TRG_CCU0TC_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_IRQ_FORCINT_Bits.TRG_CCU1TC */
+#define IFX_GTM_ATOM_CH_IRQ_FORCINT_TRG_CCU1TC_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_IRQ_FORCINT_Bits.TRG_CCU1TC */
+#define IFX_GTM_ATOM_CH_IRQ_FORCINT_TRG_CCU1TC_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_IRQ_FORCINT_Bits.TRG_CCU1TC */
+#define IFX_GTM_ATOM_CH_IRQ_FORCINT_TRG_CCU1TC_OFF (1u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_ATOM_CH_IRQ_MODE_IRQ_MODE_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_ATOM_CH_IRQ_MODE_IRQ_MODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_ATOM_CH_IRQ_MODE_IRQ_MODE_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_IRQ_NOTIFY_Bits.CCU0TC */
+#define IFX_GTM_ATOM_CH_IRQ_NOTIFY_CCU0TC_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_IRQ_NOTIFY_Bits.CCU0TC */
+#define IFX_GTM_ATOM_CH_IRQ_NOTIFY_CCU0TC_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_IRQ_NOTIFY_Bits.CCU0TC */
+#define IFX_GTM_ATOM_CH_IRQ_NOTIFY_CCU0TC_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_IRQ_NOTIFY_Bits.CCU1TC */
+#define IFX_GTM_ATOM_CH_IRQ_NOTIFY_CCU1TC_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_IRQ_NOTIFY_Bits.CCU1TC */
+#define IFX_GTM_ATOM_CH_IRQ_NOTIFY_CCU1TC_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_IRQ_NOTIFY_Bits.CCU1TC */
+#define IFX_GTM_ATOM_CH_IRQ_NOTIFY_CCU1TC_OFF (1u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_RDADDR_Bits.RDADDR0 */
+#define IFX_GTM_ATOM_CH_RDADDR_RDADDR0_LEN (9u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_RDADDR_Bits.RDADDR0 */
+#define IFX_GTM_ATOM_CH_RDADDR_RDADDR0_MSK (0x1ffu)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_RDADDR_Bits.RDADDR0 */
+#define IFX_GTM_ATOM_CH_RDADDR_RDADDR0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_RDADDR_Bits.RDADDR1 */
+#define IFX_GTM_ATOM_CH_RDADDR_RDADDR1_LEN (9u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_RDADDR_Bits.RDADDR1 */
+#define IFX_GTM_ATOM_CH_RDADDR_RDADDR1_MSK (0x1ffu)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_RDADDR_Bits.RDADDR1 */
+#define IFX_GTM_ATOM_CH_RDADDR_RDADDR1_OFF (16u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SOMC_Bits.ABM */
+#define IFX_GTM_ATOM_CH_SOMC_ABM_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SOMC_Bits.ABM */
+#define IFX_GTM_ATOM_CH_SOMC_ABM_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SOMC_Bits.ABM */
+#define IFX_GTM_ATOM_CH_SOMC_ABM_OFF (27u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SOMC_Bits.ACB10 */
+#define IFX_GTM_ATOM_CH_SOMC_ACB10_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SOMC_Bits.ACB10 */
+#define IFX_GTM_ATOM_CH_SOMC_ACB10_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SOMC_Bits.ACB10 */
+#define IFX_GTM_ATOM_CH_SOMC_ACB10_OFF (4u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SOMC_Bits.ACB42 */
+#define IFX_GTM_ATOM_CH_SOMC_ACB42_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SOMC_Bits.ACB42 */
+#define IFX_GTM_ATOM_CH_SOMC_ACB42_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SOMC_Bits.ACB42 */
+#define IFX_GTM_ATOM_CH_SOMC_ACB42_OFF (6u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SOMC_Bits.ARU_EN */
+#define IFX_GTM_ATOM_CH_SOMC_ARU_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SOMC_Bits.ARU_EN */
+#define IFX_GTM_ATOM_CH_SOMC_ARU_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SOMC_Bits.ARU_EN */
+#define IFX_GTM_ATOM_CH_SOMC_ARU_EN_OFF (3u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SOMC_Bits.CMP_CTRL */
+#define IFX_GTM_ATOM_CH_SOMC_CMP_CTRL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SOMC_Bits.CMP_CTRL */
+#define IFX_GTM_ATOM_CH_SOMC_CMP_CTRL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SOMC_Bits.CMP_CTRL */
+#define IFX_GTM_ATOM_CH_SOMC_CMP_CTRL_OFF (9u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SOMC_Bits.MODE */
+#define IFX_GTM_ATOM_CH_SOMC_MODE_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SOMC_Bits.MODE */
+#define IFX_GTM_ATOM_CH_SOMC_MODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SOMC_Bits.MODE */
+#define IFX_GTM_ATOM_CH_SOMC_MODE_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SOMC_Bits.SL */
+#define IFX_GTM_ATOM_CH_SOMC_SL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SOMC_Bits.SL */
+#define IFX_GTM_ATOM_CH_SOMC_SL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SOMC_Bits.SL */
+#define IFX_GTM_ATOM_CH_SOMC_SL_OFF (11u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SOMC_Bits.SLA */
+#define IFX_GTM_ATOM_CH_SOMC_SLA_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SOMC_Bits.SLA */
+#define IFX_GTM_ATOM_CH_SOMC_SLA_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SOMC_Bits.SLA */
+#define IFX_GTM_ATOM_CH_SOMC_SLA_OFF (25u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SOMC_Bits.TB12_SEL */
+#define IFX_GTM_ATOM_CH_SOMC_TB12_SEL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SOMC_Bits.TB12_SEL */
+#define IFX_GTM_ATOM_CH_SOMC_TB12_SEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SOMC_Bits.TB12_SEL */
+#define IFX_GTM_ATOM_CH_SOMC_TB12_SEL_OFF (2u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SOMC_Bits.TRIGOUT */
+#define IFX_GTM_ATOM_CH_SOMC_TRIGOUT_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SOMC_Bits.TRIGOUT */
+#define IFX_GTM_ATOM_CH_SOMC_TRIGOUT_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SOMC_Bits.TRIGOUT */
+#define IFX_GTM_ATOM_CH_SOMC_TRIGOUT_OFF (24u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SOMC_Bits.WR_REQ */
+#define IFX_GTM_ATOM_CH_SOMC_WR_REQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SOMC_Bits.WR_REQ */
+#define IFX_GTM_ATOM_CH_SOMC_WR_REQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SOMC_Bits.WR_REQ */
+#define IFX_GTM_ATOM_CH_SOMC_WR_REQ_OFF (16u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SOMI_Bits.ACB0 */
+#define IFX_GTM_ATOM_CH_SOMI_ACB0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SOMI_Bits.ACB0 */
+#define IFX_GTM_ATOM_CH_SOMI_ACB0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SOMI_Bits.ACB0 */
+#define IFX_GTM_ATOM_CH_SOMI_ACB0_OFF (4u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SOMI_Bits.ARU_EN */
+#define IFX_GTM_ATOM_CH_SOMI_ARU_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SOMI_Bits.ARU_EN */
+#define IFX_GTM_ATOM_CH_SOMI_ARU_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SOMI_Bits.ARU_EN */
+#define IFX_GTM_ATOM_CH_SOMI_ARU_EN_OFF (3u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SOMI_Bits.MODE */
+#define IFX_GTM_ATOM_CH_SOMI_MODE_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SOMI_Bits.MODE */
+#define IFX_GTM_ATOM_CH_SOMI_MODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SOMI_Bits.MODE */
+#define IFX_GTM_ATOM_CH_SOMI_MODE_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SOMI_Bits.SL */
+#define IFX_GTM_ATOM_CH_SOMI_SL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SOMI_Bits.SL */
+#define IFX_GTM_ATOM_CH_SOMI_SL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SOMI_Bits.SL */
+#define IFX_GTM_ATOM_CH_SOMI_SL_OFF (11u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SOMP_Bits.ADL */
+#define IFX_GTM_ATOM_CH_SOMP_ADL_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SOMP_Bits.ADL */
+#define IFX_GTM_ATOM_CH_SOMP_ADL_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SOMP_Bits.ADL */
+#define IFX_GTM_ATOM_CH_SOMP_ADL_OFF (4u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SOMP_Bits.ARU_EN */
+#define IFX_GTM_ATOM_CH_SOMP_ARU_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SOMP_Bits.ARU_EN */
+#define IFX_GTM_ATOM_CH_SOMP_ARU_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SOMP_Bits.ARU_EN */
+#define IFX_GTM_ATOM_CH_SOMP_ARU_EN_OFF (3u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SOMP_Bits.CLK_SRC_SR */
+#define IFX_GTM_ATOM_CH_SOMP_CLK_SRC_SR_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SOMP_Bits.CLK_SRC_SR */
+#define IFX_GTM_ATOM_CH_SOMP_CLK_SRC_SR_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SOMP_Bits.CLK_SRC_SR */
+#define IFX_GTM_ATOM_CH_SOMP_CLK_SRC_SR_OFF (12u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SOMP_Bits.MODE */
+#define IFX_GTM_ATOM_CH_SOMP_MODE_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SOMP_Bits.MODE */
+#define IFX_GTM_ATOM_CH_SOMP_MODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SOMP_Bits.MODE */
+#define IFX_GTM_ATOM_CH_SOMP_MODE_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SOMP_Bits.OSM */
+#define IFX_GTM_ATOM_CH_SOMP_OSM_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SOMP_Bits.OSM */
+#define IFX_GTM_ATOM_CH_SOMP_OSM_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SOMP_Bits.OSM */
+#define IFX_GTM_ATOM_CH_SOMP_OSM_OFF (26u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SOMP_Bits.RST_CCU0 */
+#define IFX_GTM_ATOM_CH_SOMP_RST_CCU0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SOMP_Bits.RST_CCU0 */
+#define IFX_GTM_ATOM_CH_SOMP_RST_CCU0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SOMP_Bits.RST_CCU0 */
+#define IFX_GTM_ATOM_CH_SOMP_RST_CCU0_OFF (20u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SOMP_Bits.SL */
+#define IFX_GTM_ATOM_CH_SOMP_SL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SOMP_Bits.SL */
+#define IFX_GTM_ATOM_CH_SOMP_SL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SOMP_Bits.SL */
+#define IFX_GTM_ATOM_CH_SOMP_SL_OFF (11u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SOMP_Bits.TRIGOUT */
+#define IFX_GTM_ATOM_CH_SOMP_TRIGOUT_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SOMP_Bits.TRIGOUT */
+#define IFX_GTM_ATOM_CH_SOMP_TRIGOUT_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SOMP_Bits.TRIGOUT */
+#define IFX_GTM_ATOM_CH_SOMP_TRIGOUT_OFF (24u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SOMS_Bits.ACB0 */
+#define IFX_GTM_ATOM_CH_SOMS_ACB0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SOMS_Bits.ACB0 */
+#define IFX_GTM_ATOM_CH_SOMS_ACB0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SOMS_Bits.ACB0 */
+#define IFX_GTM_ATOM_CH_SOMS_ACB0_OFF (4u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SOMS_Bits.ARU_EN */
+#define IFX_GTM_ATOM_CH_SOMS_ARU_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SOMS_Bits.ARU_EN */
+#define IFX_GTM_ATOM_CH_SOMS_ARU_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SOMS_Bits.ARU_EN */
+#define IFX_GTM_ATOM_CH_SOMS_ARU_EN_OFF (3u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SOMS_Bits.CLK_SRC */
+#define IFX_GTM_ATOM_CH_SOMS_CLK_SRC_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SOMS_Bits.CLK_SRC */
+#define IFX_GTM_ATOM_CH_SOMS_CLK_SRC_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SOMS_Bits.CLK_SRC */
+#define IFX_GTM_ATOM_CH_SOMS_CLK_SRC_OFF (12u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SOMS_Bits.MODE */
+#define IFX_GTM_ATOM_CH_SOMS_MODE_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SOMS_Bits.MODE */
+#define IFX_GTM_ATOM_CH_SOMS_MODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SOMS_Bits.MODE */
+#define IFX_GTM_ATOM_CH_SOMS_MODE_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SOMS_Bits.OSM */
+#define IFX_GTM_ATOM_CH_SOMS_OSM_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SOMS_Bits.OSM */
+#define IFX_GTM_ATOM_CH_SOMS_OSM_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SOMS_Bits.OSM */
+#define IFX_GTM_ATOM_CH_SOMS_OSM_OFF (26u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SOMS_Bits.SL */
+#define IFX_GTM_ATOM_CH_SOMS_SL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SOMS_Bits.SL */
+#define IFX_GTM_ATOM_CH_SOMS_SL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SOMS_Bits.SL */
+#define IFX_GTM_ATOM_CH_SOMS_SL_OFF (11u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SR0_Bits.SR0 */
+#define IFX_GTM_ATOM_CH_SR0_SR0_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SR0_Bits.SR0 */
+#define IFX_GTM_ATOM_CH_SR0_SR0_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SR0_Bits.SR0 */
+#define IFX_GTM_ATOM_CH_SR0_SR0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_SR1_Bits.SR1 */
+#define IFX_GTM_ATOM_CH_SR1_SR1_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_SR1_Bits.SR1 */
+#define IFX_GTM_ATOM_CH_SR1_SR1_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_SR1_Bits.SR1 */
+#define IFX_GTM_ATOM_CH_SR1_SR1_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_STAT_Bits.ACBI */
+#define IFX_GTM_ATOM_CH_STAT_ACBI_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_STAT_Bits.ACBI */
+#define IFX_GTM_ATOM_CH_STAT_ACBI_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_STAT_Bits.ACBI */
+#define IFX_GTM_ATOM_CH_STAT_ACBI_OFF (16u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_STAT_Bits.ACBO */
+#define IFX_GTM_ATOM_CH_STAT_ACBO_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_STAT_Bits.ACBO */
+#define IFX_GTM_ATOM_CH_STAT_ACBO_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_STAT_Bits.ACBO */
+#define IFX_GTM_ATOM_CH_STAT_ACBO_OFF (24u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_STAT_Bits.DV */
+#define IFX_GTM_ATOM_CH_STAT_DV_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_STAT_Bits.DV */
+#define IFX_GTM_ATOM_CH_STAT_DV_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_STAT_Bits.DV */
+#define IFX_GTM_ATOM_CH_STAT_DV_OFF (21u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_STAT_Bits.OL */
+#define IFX_GTM_ATOM_CH_STAT_OL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_STAT_Bits.OL */
+#define IFX_GTM_ATOM_CH_STAT_OL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_STAT_Bits.OL */
+#define IFX_GTM_ATOM_CH_STAT_OL_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ATOM_CH_STAT_Bits.WRF */
+#define IFX_GTM_ATOM_CH_STAT_WRF_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ATOM_CH_STAT_Bits.WRF */
+#define IFX_GTM_ATOM_CH_STAT_WRF_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ATOM_CH_STAT_Bits.WRF */
+#define IFX_GTM_ATOM_CH_STAT_WRF_OFF (22u)
+
+/** \brief Length for Ifx_GTM_BRC_EIRQ_EN_Bits.DEST_ERR_EN */
+#define IFX_GTM_BRC_EIRQ_EN_DEST_ERR_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_EIRQ_EN_Bits.DEST_ERR_EN */
+#define IFX_GTM_BRC_EIRQ_EN_DEST_ERR_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_EIRQ_EN_Bits.DEST_ERR_EN */
+#define IFX_GTM_BRC_EIRQ_EN_DEST_ERR_EN_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN0 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN0 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN0 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN0_OFF (1u)
+
+/** \brief Length for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN10 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN10 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN10 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN10_OFF (11u)
+
+/** \brief Length for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN11 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN11 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN11 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN11_OFF (12u)
+
+/** \brief Length for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN1 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN1 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN1 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN2 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN2 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN2 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN2_OFF (3u)
+
+/** \brief Length for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN3 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN3 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN3 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN3_OFF (4u)
+
+/** \brief Length for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN4 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN4 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN4 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN4_OFF (5u)
+
+/** \brief Length for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN5 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN5 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN5 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN5_OFF (6u)
+
+/** \brief Length for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN6 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN6 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN6 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN6_OFF (7u)
+
+/** \brief Length for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN7 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN7 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN7 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN7_OFF (8u)
+
+/** \brief Length for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN8 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN8 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN8 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN8_OFF (9u)
+
+/** \brief Length for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN9 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN9 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN9 */
+#define IFX_GTM_BRC_EIRQ_EN_DID_EN9_OFF (10u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_EN_Bits.DEST_ERR_EN */
+#define IFX_GTM_BRC_IRQ_EN_DEST_ERR_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_EN_Bits.DEST_ERR_EN */
+#define IFX_GTM_BRC_IRQ_EN_DEST_ERR_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_EN_Bits.DEST_ERR_EN */
+#define IFX_GTM_BRC_IRQ_EN_DEST_ERR_EN_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN0 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN0 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN0 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN0_OFF (1u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN10 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN10 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN10 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN10_OFF (11u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN11 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN11 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN11 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN11_OFF (12u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN1 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN1 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN1 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN2 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN2 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN2 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN2_OFF (3u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN3 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN3 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN3 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN3_OFF (4u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN4 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN4 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN4 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN4_OFF (5u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN5 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN5 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN5 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN5_OFF (6u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN6 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN6 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN6 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN6_OFF (7u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN7 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN7 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN7 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN7_OFF (8u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN8 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN8 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN8 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN8_OFF (9u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN9 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN9 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN9 */
+#define IFX_GTM_BRC_IRQ_EN_DID_EN9_OFF (10u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DEST_ERR */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DEST_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DEST_ERR */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DEST_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DEST_ERR */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DEST_ERR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID0 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID0 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID0 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID0_OFF (1u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID10 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID10_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID10 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID10_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID10 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID10_OFF (11u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID11 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID11_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID11 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID11_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID11 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID11_OFF (12u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID1 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID1 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID1 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID2 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID2 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID2 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID2_OFF (3u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID3 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID3 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID3 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID3_OFF (4u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID4 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID4 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID4 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID4_OFF (5u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID5 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID5 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID5 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID5_OFF (6u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID6 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID6 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID6 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID6_OFF (7u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID7 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID7 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID7 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID7_OFF (8u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID8 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID8_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID8 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID8_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID8 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID8_OFF (9u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID9 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID9_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID9 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID9_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID9 */
+#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID9_OFF (10u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_BRC_IRQ_MODE_IRQ_MODE_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_BRC_IRQ_MODE_IRQ_MODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_BRC_IRQ_MODE_IRQ_MODE_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DEST_ERR */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DEST_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DEST_ERR */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DEST_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DEST_ERR */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DEST_ERR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID0 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID0 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID0 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID0_OFF (1u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID10 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID10_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID10 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID10_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID10 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID10_OFF (11u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID11 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID11_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID11 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID11_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID11 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID11_OFF (12u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID1 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID1 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID1 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID2 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID2 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID2 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID2_OFF (3u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID3 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID3 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID3 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID3_OFF (4u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID4 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID4 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID4 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID4_OFF (5u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID5 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID5 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID5 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID5_OFF (6u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID6 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID6 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID6 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID6_OFF (7u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID7 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID7 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID7 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID7_OFF (8u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID8 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID8_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID8 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID8_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID8 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID8_OFF (9u)
+
+/** \brief Length for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID9 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID9_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID9 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID9_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID9 */
+#define IFX_GTM_BRC_IRQ_NOTIFY_DID9_OFF (10u)
+
+/** \brief Length for Ifx_GTM_BRC_RST_Bits.RST */
+#define IFX_GTM_BRC_RST_RST_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_RST_Bits.RST */
+#define IFX_GTM_BRC_RST_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_RST_Bits.RST */
+#define IFX_GTM_BRC_RST_RST_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC0_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC0_ADDR_ADDR_LEN (9u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC0_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC0_ADDR_ADDR_MSK (0x1ffu)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC0_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC0_ADDR_ADDR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC0_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC0_ADDR_BRC_MODE_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC0_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC0_ADDR_BRC_MODE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC0_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC0_ADDR_BRC_MODE_OFF (12u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST10_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST10_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST10_OFF (10u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST11_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST11_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST11_OFF (11u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST12_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST12_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST12_OFF (12u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST13_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST13_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST13_OFF (13u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST14_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST14_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST14_OFF (14u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST15_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST15_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST15_OFF (15u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST16_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST16_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST16_OFF (16u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST17_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST17_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST17_OFF (17u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST18_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST18_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST18_OFF (18u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST19_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST19_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST19_OFF (19u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST1_OFF (1u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST20_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST20_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST20_OFF (20u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST21_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST21_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST21_OFF (21u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST2_OFF (2u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST3_OFF (3u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST4_OFF (4u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST5_OFF (5u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST6_OFF (6u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST7_OFF (7u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST8_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST8_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST8_OFF (8u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST9_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST9_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC0_DEST_EN_DEST9_OFF (9u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC0_DEST_EN_TRASHBIN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC0_DEST_EN_TRASHBIN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC0_DEST_EN_TRASHBIN_OFF (22u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC10_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC10_ADDR_ADDR_LEN (9u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC10_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC10_ADDR_ADDR_MSK (0x1ffu)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC10_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC10_ADDR_ADDR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC10_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC10_ADDR_BRC_MODE_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC10_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC10_ADDR_BRC_MODE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC10_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC10_ADDR_BRC_MODE_OFF (12u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST10_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST10_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST10_OFF (10u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST11_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST11_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST11_OFF (11u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST12_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST12_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST12_OFF (12u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST13_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST13_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST13_OFF (13u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST14_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST14_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST14_OFF (14u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST15_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST15_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST15_OFF (15u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST16_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST16_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST16_OFF (16u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST17_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST17_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST17_OFF (17u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST18_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST18_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST18_OFF (18u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST19_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST19_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST19_OFF (19u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST1_OFF (1u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST20_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST20_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST20_OFF (20u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST21_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST21_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST21_OFF (21u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST2_OFF (2u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST3_OFF (3u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST4_OFF (4u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST5_OFF (5u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST6_OFF (6u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST7_OFF (7u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST8_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST8_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST8_OFF (8u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST9_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST9_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC10_DEST_EN_DEST9_OFF (9u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC10_DEST_EN_TRASHBIN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC10_DEST_EN_TRASHBIN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC10_DEST_EN_TRASHBIN_OFF (22u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC11_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC11_ADDR_ADDR_LEN (9u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC11_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC11_ADDR_ADDR_MSK (0x1ffu)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC11_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC11_ADDR_ADDR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC11_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC11_ADDR_BRC_MODE_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC11_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC11_ADDR_BRC_MODE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC11_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC11_ADDR_BRC_MODE_OFF (12u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST10_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST10_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST10_OFF (10u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST11_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST11_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST11_OFF (11u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST12_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST12_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST12_OFF (12u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST13_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST13_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST13_OFF (13u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST14_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST14_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST14_OFF (14u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST15_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST15_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST15_OFF (15u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST16_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST16_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST16_OFF (16u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST17_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST17_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST17_OFF (17u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST18_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST18_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST18_OFF (18u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST19_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST19_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST19_OFF (19u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST1_OFF (1u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST20_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST20_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST20_OFF (20u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST21_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST21_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST21_OFF (21u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST2_OFF (2u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST3_OFF (3u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST4_OFF (4u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST5_OFF (5u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST6_OFF (6u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST7_OFF (7u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST8_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST8_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST8_OFF (8u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST9_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST9_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC11_DEST_EN_DEST9_OFF (9u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC11_DEST_EN_TRASHBIN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC11_DEST_EN_TRASHBIN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC11_DEST_EN_TRASHBIN_OFF (22u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC1_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC1_ADDR_ADDR_LEN (9u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC1_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC1_ADDR_ADDR_MSK (0x1ffu)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC1_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC1_ADDR_ADDR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC1_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC1_ADDR_BRC_MODE_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC1_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC1_ADDR_BRC_MODE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC1_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC1_ADDR_BRC_MODE_OFF (12u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST10_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST10_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST10_OFF (10u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST11_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST11_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST11_OFF (11u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST12_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST12_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST12_OFF (12u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST13_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST13_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST13_OFF (13u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST14_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST14_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST14_OFF (14u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST15_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST15_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST15_OFF (15u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST16_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST16_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST16_OFF (16u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST17_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST17_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST17_OFF (17u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST18_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST18_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST18_OFF (18u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST19_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST19_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST19_OFF (19u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST1_OFF (1u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST20_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST20_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST20_OFF (20u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST21_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST21_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST21_OFF (21u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST2_OFF (2u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST3_OFF (3u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST4_OFF (4u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST5_OFF (5u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST6_OFF (6u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST7_OFF (7u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST8_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST8_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST8_OFF (8u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST9_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST9_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC1_DEST_EN_DEST9_OFF (9u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC1_DEST_EN_TRASHBIN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC1_DEST_EN_TRASHBIN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC1_DEST_EN_TRASHBIN_OFF (22u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC2_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC2_ADDR_ADDR_LEN (9u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC2_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC2_ADDR_ADDR_MSK (0x1ffu)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC2_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC2_ADDR_ADDR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC2_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC2_ADDR_BRC_MODE_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC2_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC2_ADDR_BRC_MODE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC2_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC2_ADDR_BRC_MODE_OFF (12u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST10_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST10_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST10_OFF (10u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST11_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST11_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST11_OFF (11u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST12_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST12_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST12_OFF (12u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST13_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST13_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST13_OFF (13u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST14_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST14_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST14_OFF (14u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST15_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST15_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST15_OFF (15u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST16_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST16_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST16_OFF (16u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST17_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST17_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST17_OFF (17u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST18_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST18_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST18_OFF (18u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST19_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST19_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST19_OFF (19u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST1_OFF (1u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST20_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST20_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST20_OFF (20u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST21_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST21_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST21_OFF (21u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST2_OFF (2u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST3_OFF (3u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST4_OFF (4u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST5_OFF (5u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST6_OFF (6u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST7_OFF (7u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST8_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST8_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST8_OFF (8u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST9_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST9_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC2_DEST_EN_DEST9_OFF (9u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC2_DEST_EN_TRASHBIN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC2_DEST_EN_TRASHBIN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC2_DEST_EN_TRASHBIN_OFF (22u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC3_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC3_ADDR_ADDR_LEN (9u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC3_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC3_ADDR_ADDR_MSK (0x1ffu)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC3_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC3_ADDR_ADDR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC3_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC3_ADDR_BRC_MODE_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC3_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC3_ADDR_BRC_MODE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC3_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC3_ADDR_BRC_MODE_OFF (12u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST10_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST10_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST10_OFF (10u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST11_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST11_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST11_OFF (11u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST12_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST12_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST12_OFF (12u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST13_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST13_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST13_OFF (13u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST14_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST14_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST14_OFF (14u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST15_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST15_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST15_OFF (15u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST16_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST16_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST16_OFF (16u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST17_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST17_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST17_OFF (17u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST18_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST18_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST18_OFF (18u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST19_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST19_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST19_OFF (19u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST1_OFF (1u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST20_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST20_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST20_OFF (20u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST21_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST21_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST21_OFF (21u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST2_OFF (2u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST3_OFF (3u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST4_OFF (4u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST5_OFF (5u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST6_OFF (6u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST7_OFF (7u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST8_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST8_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST8_OFF (8u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST9_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST9_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC3_DEST_EN_DEST9_OFF (9u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC3_DEST_EN_TRASHBIN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC3_DEST_EN_TRASHBIN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC3_DEST_EN_TRASHBIN_OFF (22u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC4_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC4_ADDR_ADDR_LEN (9u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC4_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC4_ADDR_ADDR_MSK (0x1ffu)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC4_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC4_ADDR_ADDR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC4_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC4_ADDR_BRC_MODE_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC4_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC4_ADDR_BRC_MODE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC4_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC4_ADDR_BRC_MODE_OFF (12u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST10_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST10_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST10_OFF (10u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST11_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST11_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST11_OFF (11u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST12_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST12_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST12_OFF (12u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST13_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST13_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST13_OFF (13u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST14_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST14_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST14_OFF (14u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST15_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST15_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST15_OFF (15u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST16_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST16_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST16_OFF (16u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST17_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST17_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST17_OFF (17u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST18_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST18_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST18_OFF (18u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST19_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST19_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST19_OFF (19u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST1_OFF (1u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST20_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST20_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST20_OFF (20u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST21_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST21_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST21_OFF (21u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST2_OFF (2u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST3_OFF (3u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST4_OFF (4u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST5_OFF (5u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST6_OFF (6u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST7_OFF (7u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST8_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST8_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST8_OFF (8u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST9_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST9_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC4_DEST_EN_DEST9_OFF (9u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC4_DEST_EN_TRASHBIN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC4_DEST_EN_TRASHBIN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC4_DEST_EN_TRASHBIN_OFF (22u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC5_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC5_ADDR_ADDR_LEN (9u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC5_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC5_ADDR_ADDR_MSK (0x1ffu)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC5_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC5_ADDR_ADDR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC5_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC5_ADDR_BRC_MODE_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC5_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC5_ADDR_BRC_MODE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC5_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC5_ADDR_BRC_MODE_OFF (12u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST10_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST10_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST10_OFF (10u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST11_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST11_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST11_OFF (11u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST12_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST12_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST12_OFF (12u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST13_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST13_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST13_OFF (13u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST14_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST14_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST14_OFF (14u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST15_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST15_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST15_OFF (15u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST16_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST16_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST16_OFF (16u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST17_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST17_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST17_OFF (17u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST18_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST18_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST18_OFF (18u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST19_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST19_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST19_OFF (19u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST1_OFF (1u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST20_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST20_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST20_OFF (20u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST21_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST21_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST21_OFF (21u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST2_OFF (2u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST3_OFF (3u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST4_OFF (4u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST5_OFF (5u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST6_OFF (6u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST7_OFF (7u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST8_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST8_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST8_OFF (8u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST9_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST9_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC5_DEST_EN_DEST9_OFF (9u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC5_DEST_EN_TRASHBIN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC5_DEST_EN_TRASHBIN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC5_DEST_EN_TRASHBIN_OFF (22u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC6_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC6_ADDR_ADDR_LEN (9u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC6_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC6_ADDR_ADDR_MSK (0x1ffu)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC6_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC6_ADDR_ADDR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC6_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC6_ADDR_BRC_MODE_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC6_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC6_ADDR_BRC_MODE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC6_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC6_ADDR_BRC_MODE_OFF (12u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST10_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST10_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST10_OFF (10u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST11_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST11_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST11_OFF (11u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST12_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST12_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST12_OFF (12u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST13_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST13_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST13_OFF (13u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST14_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST14_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST14_OFF (14u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST15_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST15_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST15_OFF (15u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST16_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST16_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST16_OFF (16u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST17_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST17_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST17_OFF (17u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST18_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST18_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST18_OFF (18u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST19_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST19_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST19_OFF (19u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST1_OFF (1u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST20_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST20_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST20_OFF (20u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST21_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST21_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST21_OFF (21u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST2_OFF (2u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST3_OFF (3u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST4_OFF (4u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST5_OFF (5u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST6_OFF (6u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST7_OFF (7u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST8_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST8_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST8_OFF (8u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST9_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST9_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC6_DEST_EN_DEST9_OFF (9u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC6_DEST_EN_TRASHBIN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC6_DEST_EN_TRASHBIN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC6_DEST_EN_TRASHBIN_OFF (22u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC7_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC7_ADDR_ADDR_LEN (9u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC7_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC7_ADDR_ADDR_MSK (0x1ffu)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC7_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC7_ADDR_ADDR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC7_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC7_ADDR_BRC_MODE_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC7_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC7_ADDR_BRC_MODE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC7_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC7_ADDR_BRC_MODE_OFF (12u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST10_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST10_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST10_OFF (10u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST11_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST11_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST11_OFF (11u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST12_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST12_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST12_OFF (12u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST13_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST13_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST13_OFF (13u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST14_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST14_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST14_OFF (14u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST15_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST15_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST15_OFF (15u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST16_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST16_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST16_OFF (16u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST17_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST17_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST17_OFF (17u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST18_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST18_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST18_OFF (18u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST19_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST19_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST19_OFF (19u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST1_OFF (1u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST20_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST20_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST20_OFF (20u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST21_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST21_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST21_OFF (21u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST2_OFF (2u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST3_OFF (3u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST4_OFF (4u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST5_OFF (5u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST6_OFF (6u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST7_OFF (7u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST8_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST8_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST8_OFF (8u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST9_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST9_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC7_DEST_EN_DEST9_OFF (9u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC7_DEST_EN_TRASHBIN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC7_DEST_EN_TRASHBIN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC7_DEST_EN_TRASHBIN_OFF (22u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC8_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC8_ADDR_ADDR_LEN (9u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC8_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC8_ADDR_ADDR_MSK (0x1ffu)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC8_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC8_ADDR_ADDR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC8_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC8_ADDR_BRC_MODE_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC8_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC8_ADDR_BRC_MODE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC8_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC8_ADDR_BRC_MODE_OFF (12u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST10_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST10_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST10_OFF (10u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST11_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST11_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST11_OFF (11u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST12_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST12_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST12_OFF (12u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST13_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST13_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST13_OFF (13u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST14_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST14_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST14_OFF (14u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST15_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST15_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST15_OFF (15u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST16_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST16_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST16_OFF (16u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST17_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST17_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST17_OFF (17u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST18_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST18_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST18_OFF (18u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST19_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST19_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST19_OFF (19u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST1_OFF (1u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST20_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST20_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST20_OFF (20u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST21_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST21_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST21_OFF (21u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST2_OFF (2u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST3_OFF (3u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST4_OFF (4u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST5_OFF (5u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST6_OFF (6u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST7_OFF (7u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST8_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST8_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST8_OFF (8u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST9_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST9_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC8_DEST_EN_DEST9_OFF (9u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC8_DEST_EN_TRASHBIN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC8_DEST_EN_TRASHBIN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC8_DEST_EN_TRASHBIN_OFF (22u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC9_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC9_ADDR_ADDR_LEN (9u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC9_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC9_ADDR_ADDR_MSK (0x1ffu)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC9_ADDR_Bits.ADDR */
+#define IFX_GTM_BRC_SRC9_ADDR_ADDR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC9_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC9_ADDR_BRC_MODE_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC9_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC9_ADDR_BRC_MODE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC9_ADDR_Bits.BRC_MODE */
+#define IFX_GTM_BRC_SRC9_ADDR_BRC_MODE_OFF (12u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST0 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST10_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST10_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST10 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST10_OFF (10u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST11_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST11_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST11 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST11_OFF (11u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST12_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST12_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST12 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST12_OFF (12u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST13_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST13_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST13 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST13_OFF (13u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST14_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST14_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST14 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST14_OFF (14u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST15_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST15_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST15 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST15_OFF (15u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST16_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST16_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST16 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST16_OFF (16u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST17_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST17_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST17 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST17_OFF (17u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST18_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST18_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST18 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST18_OFF (18u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST19_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST19_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST19 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST19_OFF (19u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST1 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST1_OFF (1u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST20_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST20_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST20 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST20_OFF (20u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST21_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST21_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST21 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST21_OFF (21u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST2 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST2_OFF (2u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST3 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST3_OFF (3u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST4 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST4_OFF (4u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST5 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST5_OFF (5u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST6 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST6_OFF (6u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST7 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST7_OFF (7u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST8_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST8_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST8 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST8_OFF (8u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST9_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST9_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST9 */
+#define IFX_GTM_BRC_SRC9_DEST_EN_DEST9_OFF (9u)
+
+/** \brief Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC9_DEST_EN_TRASHBIN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC9_DEST_EN_TRASHBIN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_TRASHBIN */
+#define IFX_GTM_BRC_SRC9_DEST_EN_TRASHBIN_OFF (22u)
+
+/** \brief Length for Ifx_GTM_BRIDGE_MODE_Bits.BRG_MODE */
+#define IFX_GTM_BRIDGE_MODE_BRG_MODE_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRIDGE_MODE_Bits.BRG_MODE */
+#define IFX_GTM_BRIDGE_MODE_BRG_MODE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRIDGE_MODE_Bits.BRG_MODE */
+#define IFX_GTM_BRIDGE_MODE_BRG_MODE_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRIDGE_MODE_Bits.BRG_RST */
+#define IFX_GTM_BRIDGE_MODE_BRG_RST_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRIDGE_MODE_Bits.BRG_RST */
+#define IFX_GTM_BRIDGE_MODE_BRG_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRIDGE_MODE_Bits.BRG_RST */
+#define IFX_GTM_BRIDGE_MODE_BRG_RST_OFF (16u)
+
+/** \brief Length for Ifx_GTM_BRIDGE_MODE_Bits.BUFF_DPT */
+#define IFX_GTM_BRIDGE_MODE_BUFF_DPT_LEN (8u)
+
+/** \brief Mask for Ifx_GTM_BRIDGE_MODE_Bits.BUFF_DPT */
+#define IFX_GTM_BRIDGE_MODE_BUFF_DPT_MSK (0xffu)
+
+/** \brief Offset for Ifx_GTM_BRIDGE_MODE_Bits.BUFF_DPT */
+#define IFX_GTM_BRIDGE_MODE_BUFF_DPT_OFF (24u)
+
+/** \brief Length for Ifx_GTM_BRIDGE_MODE_Bits.BUFF_OVL */
+#define IFX_GTM_BRIDGE_MODE_BUFF_OVL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRIDGE_MODE_Bits.BUFF_OVL */
+#define IFX_GTM_BRIDGE_MODE_BUFF_OVL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRIDGE_MODE_Bits.BUFF_OVL */
+#define IFX_GTM_BRIDGE_MODE_BUFF_OVL_OFF (9u)
+
+/** \brief Length for Ifx_GTM_BRIDGE_MODE_Bits.MODE_UP_PGR */
+#define IFX_GTM_BRIDGE_MODE_MODE_UP_PGR_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRIDGE_MODE_Bits.MODE_UP_PGR */
+#define IFX_GTM_BRIDGE_MODE_MODE_UP_PGR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRIDGE_MODE_Bits.MODE_UP_PGR */
+#define IFX_GTM_BRIDGE_MODE_MODE_UP_PGR_OFF (8u)
+
+/** \brief Length for Ifx_GTM_BRIDGE_MODE_Bits.MSK_WR_RSP */
+#define IFX_GTM_BRIDGE_MODE_MSK_WR_RSP_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRIDGE_MODE_Bits.MSK_WR_RSP */
+#define IFX_GTM_BRIDGE_MODE_MSK_WR_RSP_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRIDGE_MODE_Bits.MSK_WR_RSP */
+#define IFX_GTM_BRIDGE_MODE_MSK_WR_RSP_OFF (1u)
+
+/** \brief Length for Ifx_GTM_BRIDGE_MODE_Bits.SYNC_INPUT_REG */
+#define IFX_GTM_BRIDGE_MODE_SYNC_INPUT_REG_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_BRIDGE_MODE_Bits.SYNC_INPUT_REG */
+#define IFX_GTM_BRIDGE_MODE_SYNC_INPUT_REG_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_BRIDGE_MODE_Bits.SYNC_INPUT_REG */
+#define IFX_GTM_BRIDGE_MODE_SYNC_INPUT_REG_OFF (12u)
+
+/** \brief Length for Ifx_GTM_BRIDGE_PTR1_Bits.ABT_TRAN_PGR */
+#define IFX_GTM_BRIDGE_PTR1_ABT_TRAN_PGR_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_BRIDGE_PTR1_Bits.ABT_TRAN_PGR */
+#define IFX_GTM_BRIDGE_PTR1_ABT_TRAN_PGR_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_BRIDGE_PTR1_Bits.ABT_TRAN_PGR */
+#define IFX_GTM_BRIDGE_PTR1_ABT_TRAN_PGR_OFF (15u)
+
+/** \brief Length for Ifx_GTM_BRIDGE_PTR1_Bits.FBC */
+#define IFX_GTM_BRIDGE_PTR1_FBC_LEN (6u)
+
+/** \brief Mask for Ifx_GTM_BRIDGE_PTR1_Bits.FBC */
+#define IFX_GTM_BRIDGE_PTR1_FBC_MSK (0x3fu)
+
+/** \brief Offset for Ifx_GTM_BRIDGE_PTR1_Bits.FBC */
+#define IFX_GTM_BRIDGE_PTR1_FBC_OFF (20u)
+
+/** \brief Length for Ifx_GTM_BRIDGE_PTR1_Bits.FIRST_RSP_PTR */
+#define IFX_GTM_BRIDGE_PTR1_FIRST_RSP_PTR_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_BRIDGE_PTR1_Bits.FIRST_RSP_PTR */
+#define IFX_GTM_BRIDGE_PTR1_FIRST_RSP_PTR_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_BRIDGE_PTR1_Bits.FIRST_RSP_PTR */
+#define IFX_GTM_BRIDGE_PTR1_FIRST_RSP_PTR_OFF (5u)
+
+/** \brief Length for Ifx_GTM_BRIDGE_PTR1_Bits.NEW_TRAN_PTR */
+#define IFX_GTM_BRIDGE_PTR1_NEW_TRAN_PTR_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_BRIDGE_PTR1_Bits.NEW_TRAN_PTR */
+#define IFX_GTM_BRIDGE_PTR1_NEW_TRAN_PTR_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_BRIDGE_PTR1_Bits.NEW_TRAN_PTR */
+#define IFX_GTM_BRIDGE_PTR1_NEW_TRAN_PTR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_BRIDGE_PTR1_Bits.RSP_TRAN_RDY */
+#define IFX_GTM_BRIDGE_PTR1_RSP_TRAN_RDY_LEN (6u)
+
+/** \brief Mask for Ifx_GTM_BRIDGE_PTR1_Bits.RSP_TRAN_RDY */
+#define IFX_GTM_BRIDGE_PTR1_RSP_TRAN_RDY_MSK (0x3fu)
+
+/** \brief Offset for Ifx_GTM_BRIDGE_PTR1_Bits.RSP_TRAN_RDY */
+#define IFX_GTM_BRIDGE_PTR1_RSP_TRAN_RDY_OFF (26u)
+
+/** \brief Length for Ifx_GTM_BRIDGE_PTR1_Bits.TRAN_IN_PGR */
+#define IFX_GTM_BRIDGE_PTR1_TRAN_IN_PGR_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_BRIDGE_PTR1_Bits.TRAN_IN_PGR */
+#define IFX_GTM_BRIDGE_PTR1_TRAN_IN_PGR_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_BRIDGE_PTR1_Bits.TRAN_IN_PGR */
+#define IFX_GTM_BRIDGE_PTR1_TRAN_IN_PGR_OFF (10u)
+
+/** \brief Length for Ifx_GTM_BRIDGE_PTR2_Bits.TRAN_IN_PGR2 */
+#define IFX_GTM_BRIDGE_PTR2_TRAN_IN_PGR2_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_BRIDGE_PTR2_Bits.TRAN_IN_PGR2 */
+#define IFX_GTM_BRIDGE_PTR2_TRAN_IN_PGR2_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_BRIDGE_PTR2_Bits.TRAN_IN_PGR2 */
+#define IFX_GTM_BRIDGE_PTR2_TRAN_IN_PGR2_OFF (0u)
+
+/** \brief Length for Ifx_GTM_CLC_Bits.DISR */
+#define IFX_GTM_CLC_DISR_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CLC_Bits.DISR */
+#define IFX_GTM_CLC_DISR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CLC_Bits.DISR */
+#define IFX_GTM_CLC_DISR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_CLC_Bits.DISS */
+#define IFX_GTM_CLC_DISS_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CLC_Bits.DISS */
+#define IFX_GTM_CLC_DISS_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CLC_Bits.DISS */
+#define IFX_GTM_CLC_DISS_OFF (1u)
+
+/** \brief Length for Ifx_GTM_CLC_Bits.EDIS */
+#define IFX_GTM_CLC_EDIS_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CLC_Bits.EDIS */
+#define IFX_GTM_CLC_EDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CLC_Bits.EDIS */
+#define IFX_GTM_CLC_EDIS_OFF (3u)
+
+/** \brief Length for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC0_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC0_EN_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC0_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC0_EN_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC0_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC0_EN_EIRQ_OFF (0u)
+
+/** \brief Length for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC10_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC10_EN_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC10_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC10_EN_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC10_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC10_EN_EIRQ_OFF (10u)
+
+/** \brief Length for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC11_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC11_EN_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC11_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC11_EN_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC11_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC11_EN_EIRQ_OFF (11u)
+
+/** \brief Length for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC1_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC1_EN_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC1_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC1_EN_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC1_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC1_EN_EIRQ_OFF (1u)
+
+/** \brief Length for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC2_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC2_EN_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC2_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC2_EN_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC2_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC2_EN_EIRQ_OFF (2u)
+
+/** \brief Length for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC3_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC3_EN_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC3_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC3_EN_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC3_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC3_EN_EIRQ_OFF (3u)
+
+/** \brief Length for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC4_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC4_EN_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC4_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC4_EN_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC4_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC4_EN_EIRQ_OFF (4u)
+
+/** \brief Length for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC5_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC5_EN_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC5_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC5_EN_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC5_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC5_EN_EIRQ_OFF (5u)
+
+/** \brief Length for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC6_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC6_EN_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC6_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC6_EN_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC6_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC6_EN_EIRQ_OFF (6u)
+
+/** \brief Length for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC7_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC7_EN_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC7_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC7_EN_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC7_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC7_EN_EIRQ_OFF (7u)
+
+/** \brief Length for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC8_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC8_EN_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC8_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC8_EN_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC8_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC8_EN_EIRQ_OFF (8u)
+
+/** \brief Length for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC9_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC9_EN_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC9_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC9_EN_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC9_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_ABWC9_EN_EIRQ_OFF (9u)
+
+/** \brief Length for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC0_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC0_EN_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC0_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC0_EN_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC0_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC0_EN_EIRQ_OFF (12u)
+
+/** \brief Length for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC10_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC10_EN_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC10_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC10_EN_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC10_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC10_EN_EIRQ_OFF (22u)
+
+/** \brief Length for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC11_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC11_EN_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC11_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC11_EN_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC11_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC11_EN_EIRQ_OFF (23u)
+
+/** \brief Length for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC1_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC1_EN_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC1_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC1_EN_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC1_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC1_EN_EIRQ_OFF (13u)
+
+/** \brief Length for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC2_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC2_EN_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC2_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC2_EN_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC2_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC2_EN_EIRQ_OFF (14u)
+
+/** \brief Length for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC3_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC3_EN_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC3_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC3_EN_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC3_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC3_EN_EIRQ_OFF (15u)
+
+/** \brief Length for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC4_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC4_EN_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC4_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC4_EN_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC4_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC4_EN_EIRQ_OFF (16u)
+
+/** \brief Length for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC5_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC5_EN_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC5_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC5_EN_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC5_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC5_EN_EIRQ_OFF (17u)
+
+/** \brief Length for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC6_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC6_EN_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC6_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC6_EN_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC6_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC6_EN_EIRQ_OFF (18u)
+
+/** \brief Length for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC7_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC7_EN_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC7_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC7_EN_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC7_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC7_EN_EIRQ_OFF (19u)
+
+/** \brief Length for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC8_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC8_EN_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC8_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC8_EN_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC8_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC8_EN_EIRQ_OFF (20u)
+
+/** \brief Length for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC9_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC9_EN_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC9_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC9_EN_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC9_EN_EIRQ */
+#define IFX_GTM_CMP_EIRQ_EN_TBWC9_EN_EIRQ_OFF (21u)
+
+/** \brief Length for Ifx_GTM_CMP_EN_Bits.ABWC0_EN */
+#define IFX_GTM_CMP_EN_ABWC0_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EN_Bits.ABWC0_EN */
+#define IFX_GTM_CMP_EN_ABWC0_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EN_Bits.ABWC0_EN */
+#define IFX_GTM_CMP_EN_ABWC0_EN_OFF (0u)
+
+/** \brief Length for Ifx_GTM_CMP_EN_Bits.ABWC10_EN */
+#define IFX_GTM_CMP_EN_ABWC10_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EN_Bits.ABWC10_EN */
+#define IFX_GTM_CMP_EN_ABWC10_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EN_Bits.ABWC10_EN */
+#define IFX_GTM_CMP_EN_ABWC10_EN_OFF (10u)
+
+/** \brief Length for Ifx_GTM_CMP_EN_Bits.ABWC11_EN */
+#define IFX_GTM_CMP_EN_ABWC11_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EN_Bits.ABWC11_EN */
+#define IFX_GTM_CMP_EN_ABWC11_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EN_Bits.ABWC11_EN */
+#define IFX_GTM_CMP_EN_ABWC11_EN_OFF (11u)
+
+/** \brief Length for Ifx_GTM_CMP_EN_Bits.ABWC1_EN */
+#define IFX_GTM_CMP_EN_ABWC1_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EN_Bits.ABWC1_EN */
+#define IFX_GTM_CMP_EN_ABWC1_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EN_Bits.ABWC1_EN */
+#define IFX_GTM_CMP_EN_ABWC1_EN_OFF (1u)
+
+/** \brief Length for Ifx_GTM_CMP_EN_Bits.ABWC2_EN */
+#define IFX_GTM_CMP_EN_ABWC2_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EN_Bits.ABWC2_EN */
+#define IFX_GTM_CMP_EN_ABWC2_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EN_Bits.ABWC2_EN */
+#define IFX_GTM_CMP_EN_ABWC2_EN_OFF (2u)
+
+/** \brief Length for Ifx_GTM_CMP_EN_Bits.ABWC3_EN */
+#define IFX_GTM_CMP_EN_ABWC3_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EN_Bits.ABWC3_EN */
+#define IFX_GTM_CMP_EN_ABWC3_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EN_Bits.ABWC3_EN */
+#define IFX_GTM_CMP_EN_ABWC3_EN_OFF (3u)
+
+/** \brief Length for Ifx_GTM_CMP_EN_Bits.ABWC4_EN */
+#define IFX_GTM_CMP_EN_ABWC4_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EN_Bits.ABWC4_EN */
+#define IFX_GTM_CMP_EN_ABWC4_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EN_Bits.ABWC4_EN */
+#define IFX_GTM_CMP_EN_ABWC4_EN_OFF (4u)
+
+/** \brief Length for Ifx_GTM_CMP_EN_Bits.ABWC5_EN */
+#define IFX_GTM_CMP_EN_ABWC5_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EN_Bits.ABWC5_EN */
+#define IFX_GTM_CMP_EN_ABWC5_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EN_Bits.ABWC5_EN */
+#define IFX_GTM_CMP_EN_ABWC5_EN_OFF (5u)
+
+/** \brief Length for Ifx_GTM_CMP_EN_Bits.ABWC6_EN */
+#define IFX_GTM_CMP_EN_ABWC6_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EN_Bits.ABWC6_EN */
+#define IFX_GTM_CMP_EN_ABWC6_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EN_Bits.ABWC6_EN */
+#define IFX_GTM_CMP_EN_ABWC6_EN_OFF (6u)
+
+/** \brief Length for Ifx_GTM_CMP_EN_Bits.ABWC7_EN */
+#define IFX_GTM_CMP_EN_ABWC7_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EN_Bits.ABWC7_EN */
+#define IFX_GTM_CMP_EN_ABWC7_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EN_Bits.ABWC7_EN */
+#define IFX_GTM_CMP_EN_ABWC7_EN_OFF (7u)
+
+/** \brief Length for Ifx_GTM_CMP_EN_Bits.ABWC8_EN */
+#define IFX_GTM_CMP_EN_ABWC8_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EN_Bits.ABWC8_EN */
+#define IFX_GTM_CMP_EN_ABWC8_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EN_Bits.ABWC8_EN */
+#define IFX_GTM_CMP_EN_ABWC8_EN_OFF (8u)
+
+/** \brief Length for Ifx_GTM_CMP_EN_Bits.ABWC9_EN */
+#define IFX_GTM_CMP_EN_ABWC9_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EN_Bits.ABWC9_EN */
+#define IFX_GTM_CMP_EN_ABWC9_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EN_Bits.ABWC9_EN */
+#define IFX_GTM_CMP_EN_ABWC9_EN_OFF (9u)
+
+/** \brief Length for Ifx_GTM_CMP_EN_Bits.TBWC0_EN */
+#define IFX_GTM_CMP_EN_TBWC0_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EN_Bits.TBWC0_EN */
+#define IFX_GTM_CMP_EN_TBWC0_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EN_Bits.TBWC0_EN */
+#define IFX_GTM_CMP_EN_TBWC0_EN_OFF (12u)
+
+/** \brief Length for Ifx_GTM_CMP_EN_Bits.TBWC10_EN */
+#define IFX_GTM_CMP_EN_TBWC10_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EN_Bits.TBWC10_EN */
+#define IFX_GTM_CMP_EN_TBWC10_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EN_Bits.TBWC10_EN */
+#define IFX_GTM_CMP_EN_TBWC10_EN_OFF (22u)
+
+/** \brief Length for Ifx_GTM_CMP_EN_Bits.TBWC11_EN */
+#define IFX_GTM_CMP_EN_TBWC11_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EN_Bits.TBWC11_EN */
+#define IFX_GTM_CMP_EN_TBWC11_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EN_Bits.TBWC11_EN */
+#define IFX_GTM_CMP_EN_TBWC11_EN_OFF (23u)
+
+/** \brief Length for Ifx_GTM_CMP_EN_Bits.TBWC1_EN */
+#define IFX_GTM_CMP_EN_TBWC1_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EN_Bits.TBWC1_EN */
+#define IFX_GTM_CMP_EN_TBWC1_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EN_Bits.TBWC1_EN */
+#define IFX_GTM_CMP_EN_TBWC1_EN_OFF (13u)
+
+/** \brief Length for Ifx_GTM_CMP_EN_Bits.TBWC2_EN */
+#define IFX_GTM_CMP_EN_TBWC2_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EN_Bits.TBWC2_EN */
+#define IFX_GTM_CMP_EN_TBWC2_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EN_Bits.TBWC2_EN */
+#define IFX_GTM_CMP_EN_TBWC2_EN_OFF (14u)
+
+/** \brief Length for Ifx_GTM_CMP_EN_Bits.TBWC3_EN */
+#define IFX_GTM_CMP_EN_TBWC3_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EN_Bits.TBWC3_EN */
+#define IFX_GTM_CMP_EN_TBWC3_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EN_Bits.TBWC3_EN */
+#define IFX_GTM_CMP_EN_TBWC3_EN_OFF (15u)
+
+/** \brief Length for Ifx_GTM_CMP_EN_Bits.TBWC4_EN */
+#define IFX_GTM_CMP_EN_TBWC4_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EN_Bits.TBWC4_EN */
+#define IFX_GTM_CMP_EN_TBWC4_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EN_Bits.TBWC4_EN */
+#define IFX_GTM_CMP_EN_TBWC4_EN_OFF (16u)
+
+/** \brief Length for Ifx_GTM_CMP_EN_Bits.TBWC5_EN */
+#define IFX_GTM_CMP_EN_TBWC5_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EN_Bits.TBWC5_EN */
+#define IFX_GTM_CMP_EN_TBWC5_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EN_Bits.TBWC5_EN */
+#define IFX_GTM_CMP_EN_TBWC5_EN_OFF (17u)
+
+/** \brief Length for Ifx_GTM_CMP_EN_Bits.TBWC6_EN */
+#define IFX_GTM_CMP_EN_TBWC6_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EN_Bits.TBWC6_EN */
+#define IFX_GTM_CMP_EN_TBWC6_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EN_Bits.TBWC6_EN */
+#define IFX_GTM_CMP_EN_TBWC6_EN_OFF (18u)
+
+/** \brief Length for Ifx_GTM_CMP_EN_Bits.TBWC7_EN */
+#define IFX_GTM_CMP_EN_TBWC7_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EN_Bits.TBWC7_EN */
+#define IFX_GTM_CMP_EN_TBWC7_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EN_Bits.TBWC7_EN */
+#define IFX_GTM_CMP_EN_TBWC7_EN_OFF (19u)
+
+/** \brief Length for Ifx_GTM_CMP_EN_Bits.TBWC8_EN */
+#define IFX_GTM_CMP_EN_TBWC8_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EN_Bits.TBWC8_EN */
+#define IFX_GTM_CMP_EN_TBWC8_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EN_Bits.TBWC8_EN */
+#define IFX_GTM_CMP_EN_TBWC8_EN_OFF (20u)
+
+/** \brief Length for Ifx_GTM_CMP_EN_Bits.TBWC9_EN */
+#define IFX_GTM_CMP_EN_TBWC9_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_EN_Bits.TBWC9_EN */
+#define IFX_GTM_CMP_EN_TBWC9_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_EN_Bits.TBWC9_EN */
+#define IFX_GTM_CMP_EN_TBWC9_EN_OFF (21u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC0_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC0_EN_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC0_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC0_EN_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC0_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC0_EN_IRQ_OFF (0u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC10_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC10_EN_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC10_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC10_EN_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC10_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC10_EN_IRQ_OFF (10u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC11_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC11_EN_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC11_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC11_EN_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC11_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC11_EN_IRQ_OFF (11u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC1_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC1_EN_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC1_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC1_EN_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC1_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC1_EN_IRQ_OFF (1u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC2_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC2_EN_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC2_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC2_EN_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC2_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC2_EN_IRQ_OFF (2u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC3_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC3_EN_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC3_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC3_EN_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC3_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC3_EN_IRQ_OFF (3u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC4_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC4_EN_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC4_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC4_EN_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC4_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC4_EN_IRQ_OFF (4u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC5_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC5_EN_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC5_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC5_EN_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC5_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC5_EN_IRQ_OFF (5u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC6_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC6_EN_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC6_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC6_EN_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC6_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC6_EN_IRQ_OFF (6u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC7_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC7_EN_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC7_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC7_EN_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC7_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC7_EN_IRQ_OFF (7u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC8_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC8_EN_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC8_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC8_EN_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC8_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC8_EN_IRQ_OFF (8u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC9_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC9_EN_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC9_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC9_EN_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC9_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_ABWC9_EN_IRQ_OFF (9u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC0_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC0_EN_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC0_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC0_EN_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC0_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC0_EN_IRQ_OFF (12u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC10_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC10_EN_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC10_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC10_EN_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC10_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC10_EN_IRQ_OFF (22u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC11_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC11_EN_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC11_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC11_EN_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC11_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC11_EN_IRQ_OFF (23u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC1_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC1_EN_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC1_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC1_EN_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC1_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC1_EN_IRQ_OFF (13u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC2_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC2_EN_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC2_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC2_EN_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC2_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC2_EN_IRQ_OFF (14u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC3_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC3_EN_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC3_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC3_EN_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC3_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC3_EN_IRQ_OFF (15u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC4_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC4_EN_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC4_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC4_EN_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC4_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC4_EN_IRQ_OFF (16u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC5_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC5_EN_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC5_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC5_EN_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC5_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC5_EN_IRQ_OFF (17u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC6_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC6_EN_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC6_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC6_EN_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC6_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC6_EN_IRQ_OFF (18u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC7_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC7_EN_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC7_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC7_EN_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC7_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC7_EN_IRQ_OFF (19u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC8_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC8_EN_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC8_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC8_EN_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC8_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC8_EN_IRQ_OFF (20u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC9_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC9_EN_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC9_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC9_EN_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC9_EN_IRQ */
+#define IFX_GTM_CMP_IRQ_EN_TBWC9_EN_IRQ_OFF (21u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC0 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC0 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC0 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC10 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC10_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC10 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC10_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC10 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC10_OFF (10u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC11 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC11_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC11 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC11_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC11 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC11_OFF (11u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC1 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC1 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC1 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC1_OFF (1u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC2 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC2 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC2 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC2_OFF (2u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC3 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC3 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC3 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC3_OFF (3u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC4 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC4 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC4 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC4_OFF (4u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC5 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC5 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC5 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC5_OFF (5u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC6 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC6 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC6 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC6_OFF (6u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC7 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC7 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC7 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC7_OFF (7u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC8 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC8_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC8 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC8_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC8 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC8_OFF (8u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC9 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC9_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC9 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC9_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC9 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC9_OFF (9u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC0 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC0 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC0 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC0_OFF (12u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC10 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC10_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC10 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC10_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC10 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC10_OFF (22u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC11 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC11_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC11 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC11_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC11 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC11_OFF (23u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC1 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC1 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC1 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC1_OFF (13u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC2 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC2 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC2 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC2_OFF (14u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC3 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC3 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC3 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC3_OFF (15u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC4 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC4 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC4 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC4_OFF (16u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC5 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC5 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC5 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC5_OFF (17u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC6 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC6 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC6 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC6_OFF (18u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC7 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC7 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC7 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC7_OFF (19u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC8 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC8_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC8 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC8_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC8 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC8_OFF (20u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC9 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC9_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC9 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC9_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC9 */
+#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC9_OFF (21u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_CMP_IRQ_MODE_IRQ_MODE_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_CMP_IRQ_MODE_IRQ_MODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_CMP_IRQ_MODE_IRQ_MODE_OFF (0u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC0 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC0 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC0 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC10 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC10_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC10 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC10_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC10 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC10_OFF (10u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC11 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC11_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC11 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC11_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC11 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC11_OFF (11u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC1 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC1 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC1 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC1_OFF (1u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC2 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC2 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC2 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC2_OFF (2u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC3 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC3 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC3 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC3_OFF (3u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC4 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC4 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC4 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC4_OFF (4u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC5 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC5 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC5 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC5_OFF (5u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC6 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC6 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC6 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC6_OFF (6u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC7 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC7 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC7 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC7_OFF (7u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC8 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC8_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC8 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC8_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC8 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC8_OFF (8u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC9 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC9_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC9 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC9_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC9 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC9_OFF (9u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC0 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC0 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC0 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC0_OFF (12u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC10 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC10_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC10 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC10_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC10 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC10_OFF (22u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC11 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC11_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC11 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC11_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC11 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC11_OFF (23u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC1 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC1 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC1 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC1_OFF (13u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC2 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC2 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC2 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC2_OFF (14u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC3 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC3 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC3 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC3_OFF (15u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC4 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC4 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC4 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC4_OFF (16u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC5 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC5 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC5 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC5_OFF (17u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC6 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC6 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC6 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC6_OFF (18u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC7 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC7 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC7 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC7_OFF (19u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC8 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC8_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC8 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC8_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC8 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC8_OFF (20u)
+
+/** \brief Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC9 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC9_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC9 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC9_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC9 */
+#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC9_OFF (21u)
+
+/** \brief Length for Ifx_GTM_CMU_CLK0_5_CTRL_Bits.CLK_CNT */
+#define IFX_GTM_CMU_CLK0_5_CTRL_CLK_CNT_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_CMU_CLK0_5_CTRL_Bits.CLK_CNT */
+#define IFX_GTM_CMU_CLK0_5_CTRL_CLK_CNT_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_CMU_CLK0_5_CTRL_Bits.CLK_CNT */
+#define IFX_GTM_CMU_CLK0_5_CTRL_CLK_CNT_OFF (0u)
+
+/** \brief Length for Ifx_GTM_CMU_CLK_6_CTRL_Bits.CLK6_SEL */
+#define IFX_GTM_CMU_CLK_6_CTRL_CLK6_SEL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMU_CLK_6_CTRL_Bits.CLK6_SEL */
+#define IFX_GTM_CMU_CLK_6_CTRL_CLK6_SEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMU_CLK_6_CTRL_Bits.CLK6_SEL */
+#define IFX_GTM_CMU_CLK_6_CTRL_CLK6_SEL_OFF (24u)
+
+/** \brief Length for Ifx_GTM_CMU_CLK_6_CTRL_Bits.CLK_CNT */
+#define IFX_GTM_CMU_CLK_6_CTRL_CLK_CNT_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_CMU_CLK_6_CTRL_Bits.CLK_CNT */
+#define IFX_GTM_CMU_CLK_6_CTRL_CLK_CNT_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_CMU_CLK_6_CTRL_Bits.CLK_CNT */
+#define IFX_GTM_CMU_CLK_6_CTRL_CLK_CNT_OFF (0u)
+
+/** \brief Length for Ifx_GTM_CMU_CLK_7_CTRL_Bits.CLK7_SEL */
+#define IFX_GTM_CMU_CLK_7_CTRL_CLK7_SEL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CMU_CLK_7_CTRL_Bits.CLK7_SEL */
+#define IFX_GTM_CMU_CLK_7_CTRL_CLK7_SEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CMU_CLK_7_CTRL_Bits.CLK7_SEL */
+#define IFX_GTM_CMU_CLK_7_CTRL_CLK7_SEL_OFF (24u)
+
+/** \brief Length for Ifx_GTM_CMU_CLK_7_CTRL_Bits.CLK_CNT */
+#define IFX_GTM_CMU_CLK_7_CTRL_CLK_CNT_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_CMU_CLK_7_CTRL_Bits.CLK_CNT */
+#define IFX_GTM_CMU_CLK_7_CTRL_CLK_CNT_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_CMU_CLK_7_CTRL_Bits.CLK_CNT */
+#define IFX_GTM_CMU_CLK_7_CTRL_CLK_CNT_OFF (0u)
+
+/** \brief Length for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK0 */
+#define IFX_GTM_CMU_CLK_EN_EN_CLK0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK0 */
+#define IFX_GTM_CMU_CLK_EN_EN_CLK0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK0 */
+#define IFX_GTM_CMU_CLK_EN_EN_CLK0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK1 */
+#define IFX_GTM_CMU_CLK_EN_EN_CLK1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK1 */
+#define IFX_GTM_CMU_CLK_EN_EN_CLK1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK1 */
+#define IFX_GTM_CMU_CLK_EN_EN_CLK1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK2 */
+#define IFX_GTM_CMU_CLK_EN_EN_CLK2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK2 */
+#define IFX_GTM_CMU_CLK_EN_EN_CLK2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK2 */
+#define IFX_GTM_CMU_CLK_EN_EN_CLK2_OFF (4u)
+
+/** \brief Length for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK3 */
+#define IFX_GTM_CMU_CLK_EN_EN_CLK3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK3 */
+#define IFX_GTM_CMU_CLK_EN_EN_CLK3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK3 */
+#define IFX_GTM_CMU_CLK_EN_EN_CLK3_OFF (6u)
+
+/** \brief Length for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK4 */
+#define IFX_GTM_CMU_CLK_EN_EN_CLK4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK4 */
+#define IFX_GTM_CMU_CLK_EN_EN_CLK4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK4 */
+#define IFX_GTM_CMU_CLK_EN_EN_CLK4_OFF (8u)
+
+/** \brief Length for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK5 */
+#define IFX_GTM_CMU_CLK_EN_EN_CLK5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK5 */
+#define IFX_GTM_CMU_CLK_EN_EN_CLK5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK5 */
+#define IFX_GTM_CMU_CLK_EN_EN_CLK5_OFF (10u)
+
+/** \brief Length for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK6 */
+#define IFX_GTM_CMU_CLK_EN_EN_CLK6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK6 */
+#define IFX_GTM_CMU_CLK_EN_EN_CLK6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK6 */
+#define IFX_GTM_CMU_CLK_EN_EN_CLK6_OFF (12u)
+
+/** \brief Length for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK7 */
+#define IFX_GTM_CMU_CLK_EN_EN_CLK7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK7 */
+#define IFX_GTM_CMU_CLK_EN_EN_CLK7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK7 */
+#define IFX_GTM_CMU_CLK_EN_EN_CLK7_OFF (14u)
+
+/** \brief Length for Ifx_GTM_CMU_CLK_EN_Bits.EN_ECLK0 */
+#define IFX_GTM_CMU_CLK_EN_EN_ECLK0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_CMU_CLK_EN_Bits.EN_ECLK0 */
+#define IFX_GTM_CMU_CLK_EN_EN_ECLK0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_CMU_CLK_EN_Bits.EN_ECLK0 */
+#define IFX_GTM_CMU_CLK_EN_EN_ECLK0_OFF (16u)
+
+/** \brief Length for Ifx_GTM_CMU_CLK_EN_Bits.EN_ECLK1 */
+#define IFX_GTM_CMU_CLK_EN_EN_ECLK1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_CMU_CLK_EN_Bits.EN_ECLK1 */
+#define IFX_GTM_CMU_CLK_EN_EN_ECLK1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_CMU_CLK_EN_Bits.EN_ECLK1 */
+#define IFX_GTM_CMU_CLK_EN_EN_ECLK1_OFF (18u)
+
+/** \brief Length for Ifx_GTM_CMU_CLK_EN_Bits.EN_ECLK2 */
+#define IFX_GTM_CMU_CLK_EN_EN_ECLK2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_CMU_CLK_EN_Bits.EN_ECLK2 */
+#define IFX_GTM_CMU_CLK_EN_EN_ECLK2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_CMU_CLK_EN_Bits.EN_ECLK2 */
+#define IFX_GTM_CMU_CLK_EN_EN_ECLK2_OFF (20u)
+
+/** \brief Length for Ifx_GTM_CMU_CLK_EN_Bits.EN_FXCLK */
+#define IFX_GTM_CMU_CLK_EN_EN_FXCLK_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_CMU_CLK_EN_Bits.EN_FXCLK */
+#define IFX_GTM_CMU_CLK_EN_EN_FXCLK_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_CMU_CLK_EN_Bits.EN_FXCLK */
+#define IFX_GTM_CMU_CLK_EN_EN_FXCLK_OFF (22u)
+
+/** \brief Length for Ifx_GTM_CMU_ECLK_DEN_Bits.ECLK_DEN */
+#define IFX_GTM_CMU_ECLK_DEN_ECLK_DEN_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_CMU_ECLK_DEN_Bits.ECLK_DEN */
+#define IFX_GTM_CMU_ECLK_DEN_ECLK_DEN_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_CMU_ECLK_DEN_Bits.ECLK_DEN */
+#define IFX_GTM_CMU_ECLK_DEN_ECLK_DEN_OFF (0u)
+
+/** \brief Length for Ifx_GTM_CMU_ECLK_NUM_Bits.ECLK_NUM */
+#define IFX_GTM_CMU_ECLK_NUM_ECLK_NUM_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_CMU_ECLK_NUM_Bits.ECLK_NUM */
+#define IFX_GTM_CMU_ECLK_NUM_ECLK_NUM_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_CMU_ECLK_NUM_Bits.ECLK_NUM */
+#define IFX_GTM_CMU_ECLK_NUM_ECLK_NUM_OFF (0u)
+
+/** \brief Length for Ifx_GTM_CMU_FXCLK_CTRL_Bits.FXCLK_SEL */
+#define IFX_GTM_CMU_FXCLK_CTRL_FXCLK_SEL_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_CMU_FXCLK_CTRL_Bits.FXCLK_SEL */
+#define IFX_GTM_CMU_FXCLK_CTRL_FXCLK_SEL_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_CMU_FXCLK_CTRL_Bits.FXCLK_SEL */
+#define IFX_GTM_CMU_FXCLK_CTRL_FXCLK_SEL_OFF (0u)
+
+/** \brief Length for Ifx_GTM_CMU_GCLK_DEN_Bits.GCLK_DEN */
+#define IFX_GTM_CMU_GCLK_DEN_GCLK_DEN_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_CMU_GCLK_DEN_Bits.GCLK_DEN */
+#define IFX_GTM_CMU_GCLK_DEN_GCLK_DEN_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_CMU_GCLK_DEN_Bits.GCLK_DEN */
+#define IFX_GTM_CMU_GCLK_DEN_GCLK_DEN_OFF (0u)
+
+/** \brief Length for Ifx_GTM_CMU_GCLK_NUM_Bits.GCLK_NUM */
+#define IFX_GTM_CMU_GCLK_NUM_GCLK_NUM_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_CMU_GCLK_NUM_Bits.GCLK_NUM */
+#define IFX_GTM_CMU_GCLK_NUM_GCLK_NUM_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_CMU_GCLK_NUM_Bits.GCLK_NUM */
+#define IFX_GTM_CMU_GCLK_NUM_GCLK_NUM_OFF (0u)
+
+/** \brief Length for Ifx_GTM_CTRL_Bits.RF_PROT */
+#define IFX_GTM_CTRL_RF_PROT_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CTRL_Bits.RF_PROT */
+#define IFX_GTM_CTRL_RF_PROT_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CTRL_Bits.RF_PROT */
+#define IFX_GTM_CTRL_RF_PROT_OFF (0u)
+
+/** \brief Length for Ifx_GTM_CTRL_Bits.TO_MODE */
+#define IFX_GTM_CTRL_TO_MODE_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_CTRL_Bits.TO_MODE */
+#define IFX_GTM_CTRL_TO_MODE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_CTRL_Bits.TO_MODE */
+#define IFX_GTM_CTRL_TO_MODE_OFF (1u)
+
+/** \brief Length for Ifx_GTM_CTRL_Bits.TO_VAL */
+#define IFX_GTM_CTRL_TO_VAL_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_CTRL_Bits.TO_VAL */
+#define IFX_GTM_CTRL_TO_VAL_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_CTRL_Bits.TO_VAL */
+#define IFX_GTM_CTRL_TO_VAL_OFF (4u)
+
+/** \brief Length for Ifx_GTM_DATAIN_Bits.DATA */
+#define IFX_GTM_DATAIN_DATA_LEN (32u)
+
+/** \brief Mask for Ifx_GTM_DATAIN_Bits.DATA */
+#define IFX_GTM_DATAIN_DATA_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_GTM_DATAIN_Bits.DATA */
+#define IFX_GTM_DATAIN_DATA_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_ACB_Bits.ACB_0 */
+#define IFX_GTM_DPLL_ACB_ACB_0_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_DPLL_ACB_Bits.ACB_0 */
+#define IFX_GTM_DPLL_ACB_ACB_0_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_DPLL_ACB_Bits.ACB_0 */
+#define IFX_GTM_DPLL_ACB_ACB_0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_ACB_Bits.ACB_1 */
+#define IFX_GTM_DPLL_ACB_ACB_1_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_DPLL_ACB_Bits.ACB_1 */
+#define IFX_GTM_DPLL_ACB_ACB_1_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_DPLL_ACB_Bits.ACB_1 */
+#define IFX_GTM_DPLL_ACB_ACB_1_OFF (8u)
+
+/** \brief Length for Ifx_GTM_DPLL_ACB_Bits.ACB_2 */
+#define IFX_GTM_DPLL_ACB_ACB_2_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_DPLL_ACB_Bits.ACB_2 */
+#define IFX_GTM_DPLL_ACB_ACB_2_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_DPLL_ACB_Bits.ACB_2 */
+#define IFX_GTM_DPLL_ACB_ACB_2_OFF (16u)
+
+/** \brief Length for Ifx_GTM_DPLL_ACB_Bits.ACB_3 */
+#define IFX_GTM_DPLL_ACB_ACB_3_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_DPLL_ACB_Bits.ACB_3 */
+#define IFX_GTM_DPLL_ACB_ACB_3_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_DPLL_ACB_Bits.ACB_3 */
+#define IFX_GTM_DPLL_ACB_ACB_3_OFF (24u)
+
+/** \brief Length for Ifx_GTM_DPLL_ACT_STA_Bits.ACT_Ni */
+#define IFX_GTM_DPLL_ACT_STA_ACT_NI_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_ACT_STA_Bits.ACT_Ni */
+#define IFX_GTM_DPLL_ACT_STA_ACT_NI_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_ACT_STA_Bits.ACT_Ni */
+#define IFX_GTM_DPLL_ACT_STA_ACT_NI_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_ADD_IN_CAL1_Bits.ADD_IN_CAL_1 */
+#define IFX_GTM_DPLL_ADD_IN_CAL1_ADD_IN_CAL_1_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_ADD_IN_CAL1_Bits.ADD_IN_CAL_1 */
+#define IFX_GTM_DPLL_ADD_IN_CAL1_ADD_IN_CAL_1_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_ADD_IN_CAL1_Bits.ADD_IN_CAL_1 */
+#define IFX_GTM_DPLL_ADD_IN_CAL1_ADD_IN_CAL_1_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_ADD_IN_CAL2_Bits.ADD_IN_CAL_2 */
+#define IFX_GTM_DPLL_ADD_IN_CAL2_ADD_IN_CAL_2_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_ADD_IN_CAL2_Bits.ADD_IN_CAL_2 */
+#define IFX_GTM_DPLL_ADD_IN_CAL2_ADD_IN_CAL_2_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_ADD_IN_CAL2_Bits.ADD_IN_CAL_2 */
+#define IFX_GTM_DPLL_ADD_IN_CAL2_ADD_IN_CAL_2_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_ADD_IN_LD1_Bits.ADD_IN_LD_1 */
+#define IFX_GTM_DPLL_ADD_IN_LD1_ADD_IN_LD_1_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_ADD_IN_LD1_Bits.ADD_IN_LD_1 */
+#define IFX_GTM_DPLL_ADD_IN_LD1_ADD_IN_LD_1_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_ADD_IN_LD1_Bits.ADD_IN_LD_1 */
+#define IFX_GTM_DPLL_ADD_IN_LD1_ADD_IN_LD_1_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_ADD_IN_LD2_Bits.ADD_IN_LD_2 */
+#define IFX_GTM_DPLL_ADD_IN_LD2_ADD_IN_LD_2_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_ADD_IN_LD2_Bits.ADD_IN_LD_2 */
+#define IFX_GTM_DPLL_ADD_IN_LD2_ADD_IN_LD_2_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_ADD_IN_LD2_Bits.ADD_IN_LD_2 */
+#define IFX_GTM_DPLL_ADD_IN_LD2_ADD_IN_LD_2_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_ADT_S_Bits.NS */
+#define IFX_GTM_DPLL_ADT_S_NS_LEN (6u)
+
+/** \brief Mask for Ifx_GTM_DPLL_ADT_S_Bits.NS */
+#define IFX_GTM_DPLL_ADT_S_NS_MSK (0x3fu)
+
+/** \brief Offset for Ifx_GTM_DPLL_ADT_S_Bits.NS */
+#define IFX_GTM_DPLL_ADT_S_NS_OFF (16u)
+
+/** \brief Length for Ifx_GTM_DPLL_ADT_S_Bits.PD_S */
+#define IFX_GTM_DPLL_ADT_S_PD_S_LEN (16u)
+
+/** \brief Mask for Ifx_GTM_DPLL_ADT_S_Bits.PD_S */
+#define IFX_GTM_DPLL_ADT_S_PD_S_MSK (0xffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_ADT_S_Bits.PD_S */
+#define IFX_GTM_DPLL_ADT_S_PD_S_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_AOSV_2_Bits.AOSV_2A */
+#define IFX_GTM_DPLL_AOSV_2_AOSV_2A_LEN (8u)
+
+/** \brief Mask for Ifx_GTM_DPLL_AOSV_2_Bits.AOSV_2A */
+#define IFX_GTM_DPLL_AOSV_2_AOSV_2A_MSK (0xffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_AOSV_2_Bits.AOSV_2A */
+#define IFX_GTM_DPLL_AOSV_2_AOSV_2A_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_AOSV_2_Bits.AOSV_2B */
+#define IFX_GTM_DPLL_AOSV_2_AOSV_2B_LEN (8u)
+
+/** \brief Mask for Ifx_GTM_DPLL_AOSV_2_Bits.AOSV_2B */
+#define IFX_GTM_DPLL_AOSV_2_AOSV_2B_MSK (0xffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_AOSV_2_Bits.AOSV_2B */
+#define IFX_GTM_DPLL_AOSV_2_AOSV_2B_OFF (8u)
+
+/** \brief Length for Ifx_GTM_DPLL_AOSV_2_Bits.AOSV_2C */
+#define IFX_GTM_DPLL_AOSV_2_AOSV_2C_LEN (8u)
+
+/** \brief Mask for Ifx_GTM_DPLL_AOSV_2_Bits.AOSV_2C */
+#define IFX_GTM_DPLL_AOSV_2_AOSV_2C_MSK (0xffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_AOSV_2_Bits.AOSV_2C */
+#define IFX_GTM_DPLL_AOSV_2_AOSV_2C_OFF (16u)
+
+/** \brief Length for Ifx_GTM_DPLL_AOSV_2_Bits.AOSV_2D */
+#define IFX_GTM_DPLL_AOSV_2_AOSV_2D_LEN (8u)
+
+/** \brief Mask for Ifx_GTM_DPLL_AOSV_2_Bits.AOSV_2D */
+#define IFX_GTM_DPLL_AOSV_2_AOSV_2D_MSK (0xffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_AOSV_2_Bits.AOSV_2D */
+#define IFX_GTM_DPLL_AOSV_2_AOSV_2D_OFF (24u)
+
+/** \brief Length for Ifx_GTM_DPLL_APS_1C3_Bits.APS_1C3 */
+#define IFX_GTM_DPLL_APS_1C3_APS_1C3_LEN (6u)
+
+/** \brief Mask for Ifx_GTM_DPLL_APS_1C3_Bits.APS_1C3 */
+#define IFX_GTM_DPLL_APS_1C3_APS_1C3_MSK (0x3fu)
+
+/** \brief Offset for Ifx_GTM_DPLL_APS_1C3_Bits.APS_1C3 */
+#define IFX_GTM_DPLL_APS_1C3_APS_1C3_OFF (2u)
+
+/** \brief Length for Ifx_GTM_DPLL_APS_Bits.APS_1C2 */
+#define IFX_GTM_DPLL_APS_APS_1C2_LEN (6u)
+
+/** \brief Mask for Ifx_GTM_DPLL_APS_Bits.APS_1C2 */
+#define IFX_GTM_DPLL_APS_APS_1C2_MSK (0x3fu)
+
+/** \brief Offset for Ifx_GTM_DPLL_APS_Bits.APS_1C2 */
+#define IFX_GTM_DPLL_APS_APS_1C2_OFF (14u)
+
+/** \brief Length for Ifx_GTM_DPLL_APS_Bits.APS */
+#define IFX_GTM_DPLL_APS_APS_LEN (6u)
+
+/** \brief Mask for Ifx_GTM_DPLL_APS_Bits.APS */
+#define IFX_GTM_DPLL_APS_APS_MSK (0x3fu)
+
+/** \brief Offset for Ifx_GTM_DPLL_APS_Bits.APS */
+#define IFX_GTM_DPLL_APS_APS_OFF (2u)
+
+/** \brief Length for Ifx_GTM_DPLL_APS_SYNC_Bits.APS_1C2_EXT */
+#define IFX_GTM_DPLL_APS_SYNC_APS_1C2_EXT_LEN (6u)
+
+/** \brief Mask for Ifx_GTM_DPLL_APS_SYNC_Bits.APS_1C2_EXT */
+#define IFX_GTM_DPLL_APS_SYNC_APS_1C2_EXT_MSK (0x3fu)
+
+/** \brief Offset for Ifx_GTM_DPLL_APS_SYNC_Bits.APS_1C2_EXT */
+#define IFX_GTM_DPLL_APS_SYNC_APS_1C2_EXT_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_APS_SYNC_Bits.APS_1C2_OLD */
+#define IFX_GTM_DPLL_APS_SYNC_APS_1C2_OLD_LEN (6u)
+
+/** \brief Mask for Ifx_GTM_DPLL_APS_SYNC_Bits.APS_1C2_OLD */
+#define IFX_GTM_DPLL_APS_SYNC_APS_1C2_OLD_MSK (0x3fu)
+
+/** \brief Offset for Ifx_GTM_DPLL_APS_SYNC_Bits.APS_1C2_OLD */
+#define IFX_GTM_DPLL_APS_SYNC_APS_1C2_OLD_OFF (14u)
+
+/** \brief Length for Ifx_GTM_DPLL_APS_SYNC_Bits.APS_1C2_STATUS */
+#define IFX_GTM_DPLL_APS_SYNC_APS_1C2_STATUS_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_APS_SYNC_Bits.APS_1C2_STATUS */
+#define IFX_GTM_DPLL_APS_SYNC_APS_1C2_STATUS_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_APS_SYNC_Bits.APS_1C2_STATUS */
+#define IFX_GTM_DPLL_APS_SYNC_APS_1C2_STATUS_OFF (6u)
+
+/** \brief Length for Ifx_GTM_DPLL_APS_Bits.WAPS_1C2 */
+#define IFX_GTM_DPLL_APS_WAPS_1C2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_APS_Bits.WAPS_1C2 */
+#define IFX_GTM_DPLL_APS_WAPS_1C2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_APS_Bits.WAPS_1C2 */
+#define IFX_GTM_DPLL_APS_WAPS_1C2_OFF (13u)
+
+/** \brief Length for Ifx_GTM_DPLL_APS_Bits.WAPS */
+#define IFX_GTM_DPLL_APS_WAPS_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_APS_Bits.WAPS */
+#define IFX_GTM_DPLL_APS_WAPS_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_APS_Bits.WAPS */
+#define IFX_GTM_DPLL_APS_WAPS_OFF (1u)
+
+/** \brief Length for Ifx_GTM_DPLL_APT_2C_Bits.APT_2C */
+#define IFX_GTM_DPLL_APT_2C_APT_2C_LEN (10u)
+
+/** \brief Mask for Ifx_GTM_DPLL_APT_2C_Bits.APT_2C */
+#define IFX_GTM_DPLL_APT_2C_APT_2C_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_APT_2C_Bits.APT_2C */
+#define IFX_GTM_DPLL_APT_2C_APT_2C_OFF (2u)
+
+/** \brief Length for Ifx_GTM_DPLL_APT_Bits.APT_2B */
+#define IFX_GTM_DPLL_APT_APT_2B_LEN (10u)
+
+/** \brief Mask for Ifx_GTM_DPLL_APT_Bits.APT_2B */
+#define IFX_GTM_DPLL_APT_APT_2B_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_APT_Bits.APT_2B */
+#define IFX_GTM_DPLL_APT_APT_2B_OFF (14u)
+
+/** \brief Length for Ifx_GTM_DPLL_APT_Bits.APT */
+#define IFX_GTM_DPLL_APT_APT_LEN (10u)
+
+/** \brief Mask for Ifx_GTM_DPLL_APT_Bits.APT */
+#define IFX_GTM_DPLL_APT_APT_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_APT_Bits.APT */
+#define IFX_GTM_DPLL_APT_APT_OFF (2u)
+
+/** \brief Length for Ifx_GTM_DPLL_APT_SYNC_Bits.APT_2B_EXT */
+#define IFX_GTM_DPLL_APT_SYNC_APT_2B_EXT_LEN (6u)
+
+/** \brief Mask for Ifx_GTM_DPLL_APT_SYNC_Bits.APT_2B_EXT */
+#define IFX_GTM_DPLL_APT_SYNC_APT_2B_EXT_MSK (0x3fu)
+
+/** \brief Offset for Ifx_GTM_DPLL_APT_SYNC_Bits.APT_2B_EXT */
+#define IFX_GTM_DPLL_APT_SYNC_APT_2B_EXT_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_APT_SYNC_Bits.APT_2B_OLD */
+#define IFX_GTM_DPLL_APT_SYNC_APT_2B_OLD_LEN (10u)
+
+/** \brief Mask for Ifx_GTM_DPLL_APT_SYNC_Bits.APT_2B_OLD */
+#define IFX_GTM_DPLL_APT_SYNC_APT_2B_OLD_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_APT_SYNC_Bits.APT_2B_OLD */
+#define IFX_GTM_DPLL_APT_SYNC_APT_2B_OLD_OFF (14u)
+
+/** \brief Length for Ifx_GTM_DPLL_APT_SYNC_Bits.APT_2B_STATUS */
+#define IFX_GTM_DPLL_APT_SYNC_APT_2B_STATUS_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_APT_SYNC_Bits.APT_2B_STATUS */
+#define IFX_GTM_DPLL_APT_SYNC_APT_2B_STATUS_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_APT_SYNC_Bits.APT_2B_STATUS */
+#define IFX_GTM_DPLL_APT_SYNC_APT_2B_STATUS_OFF (6u)
+
+/** \brief Length for Ifx_GTM_DPLL_APT_Bits.WAPT_2B */
+#define IFX_GTM_DPLL_APT_WAPT_2B_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_APT_Bits.WAPT_2B */
+#define IFX_GTM_DPLL_APT_WAPT_2B_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_APT_Bits.WAPT_2B */
+#define IFX_GTM_DPLL_APT_WAPT_2B_OFF (13u)
+
+/** \brief Length for Ifx_GTM_DPLL_APT_Bits.WAPT */
+#define IFX_GTM_DPLL_APT_WAPT_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_APT_Bits.WAPT */
+#define IFX_GTM_DPLL_APT_WAPT_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_APT_Bits.WAPT */
+#define IFX_GTM_DPLL_APT_WAPT_OFF (1u)
+
+/** \brief Length for Ifx_GTM_DPLL_CDT_SX_Bits.CDT_SX */
+#define IFX_GTM_DPLL_CDT_SX_CDT_SX_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CDT_SX_Bits.CDT_SX */
+#define IFX_GTM_DPLL_CDT_SX_CDT_SX_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_CDT_SX_Bits.CDT_SX */
+#define IFX_GTM_DPLL_CDT_SX_CDT_SX_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_CDT_SX_NOM_Bits.CDT_SX_NOM */
+#define IFX_GTM_DPLL_CDT_SX_NOM_CDT_SX_NOM_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CDT_SX_NOM_Bits.CDT_SX_NOM */
+#define IFX_GTM_DPLL_CDT_SX_NOM_CDT_SX_NOM_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_CDT_SX_NOM_Bits.CDT_SX_NOM */
+#define IFX_GTM_DPLL_CDT_SX_NOM_CDT_SX_NOM_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_CDT_TX_Bits.CDT_TX */
+#define IFX_GTM_DPLL_CDT_TX_CDT_TX_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CDT_TX_Bits.CDT_TX */
+#define IFX_GTM_DPLL_CDT_TX_CDT_TX_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_CDT_TX_Bits.CDT_TX */
+#define IFX_GTM_DPLL_CDT_TX_CDT_TX_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_CDT_TX_NOM_Bits.CDT_TX_NOM */
+#define IFX_GTM_DPLL_CDT_TX_NOM_CDT_TX_NOM_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CDT_TX_NOM_Bits.CDT_TX_NOM */
+#define IFX_GTM_DPLL_CDT_TX_NOM_CDT_TX_NOM_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_CDT_TX_NOM_Bits.CDT_TX_NOM */
+#define IFX_GTM_DPLL_CDT_TX_NOM_CDT_TX_NOM_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_CNT_NUM1_Bits.CNT_NUM_1 */
+#define IFX_GTM_DPLL_CNT_NUM1_CNT_NUM_1_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CNT_NUM1_Bits.CNT_NUM_1 */
+#define IFX_GTM_DPLL_CNT_NUM1_CNT_NUM_1_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_CNT_NUM1_Bits.CNT_NUM_1 */
+#define IFX_GTM_DPLL_CNT_NUM1_CNT_NUM_1_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_CNT_NUM2_Bits.CNT_NUM_2 */
+#define IFX_GTM_DPLL_CNT_NUM2_CNT_NUM_2_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CNT_NUM2_Bits.CNT_NUM_2 */
+#define IFX_GTM_DPLL_CNT_NUM2_CNT_NUM_2_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_CNT_NUM2_Bits.CNT_NUM_2 */
+#define IFX_GTM_DPLL_CNT_NUM2_CNT_NUM_2_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.COA */
+#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_COA_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.COA */
+#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_COA_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.COA */
+#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_COA_OFF (3u)
+
+/** \brief Length for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.DLM1 */
+#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_DLM1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.DLM1 */
+#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_DLM1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.DLM1 */
+#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_DLM1_OFF (6u)
+
+/** \brief Length for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.DLM2 */
+#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_DLM2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.DLM2 */
+#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_DLM2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.DLM2 */
+#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_DLM2_OFF (9u)
+
+/** \brief Length for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.DMO */
+#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_DMO_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.DMO */
+#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_DMO_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.DMO */
+#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_DMO_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.PCM1 */
+#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_PCM1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.PCM1 */
+#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_PCM1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.PCM1 */
+#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_PCM1_OFF (7u)
+
+/** \brief Length for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.PCM2 */
+#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_PCM2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.PCM2 */
+#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_PCM2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.PCM2 */
+#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_PCM2_OFF (10u)
+
+/** \brief Length for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.PIT */
+#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_PIT_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.PIT */
+#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_PIT_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.PIT */
+#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_PIT_OFF (4u)
+
+/** \brief Length for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.SGE1 */
+#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_SGE1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.SGE1 */
+#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_SGE1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.SGE1 */
+#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_SGE1_OFF (5u)
+
+/** \brief Length for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.SGE2 */
+#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_SGE2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.SGE2 */
+#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_SGE2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.SGE2 */
+#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_SGE2_OFF (8u)
+
+/** \brief Length for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.SYN_NS */
+#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_SYN_NS_LEN (21u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.SYN_NS */
+#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_SYN_NS_MSK (0x1fffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.SYN_NS */
+#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_SYN_NS_OFF (11u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_0_Bits.AMS */
+#define IFX_GTM_DPLL_CTRL_0_AMS_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_0_Bits.AMS */
+#define IFX_GTM_DPLL_CTRL_0_AMS_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_0_Bits.AMS */
+#define IFX_GTM_DPLL_CTRL_0_AMS_OFF (25u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_0_Bits.AMT */
+#define IFX_GTM_DPLL_CTRL_0_AMT_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_0_Bits.AMT */
+#define IFX_GTM_DPLL_CTRL_0_AMT_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_0_Bits.AMT */
+#define IFX_GTM_DPLL_CTRL_0_AMT_OFF (26u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_0_Bits.IDS */
+#define IFX_GTM_DPLL_CTRL_0_IDS_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_0_Bits.IDS */
+#define IFX_GTM_DPLL_CTRL_0_IDS_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_0_Bits.IDS */
+#define IFX_GTM_DPLL_CTRL_0_IDS_OFF (27u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_0_Bits.IDT */
+#define IFX_GTM_DPLL_CTRL_0_IDT_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_0_Bits.IDT */
+#define IFX_GTM_DPLL_CTRL_0_IDT_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_0_Bits.IDT */
+#define IFX_GTM_DPLL_CTRL_0_IDT_OFF (28u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_0_Bits.IFP */
+#define IFX_GTM_DPLL_CTRL_0_IFP_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_0_Bits.IFP */
+#define IFX_GTM_DPLL_CTRL_0_IFP_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_0_Bits.IFP */
+#define IFX_GTM_DPLL_CTRL_0_IFP_OFF (10u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_0_Bits.MLT */
+#define IFX_GTM_DPLL_CTRL_0_MLT_LEN (10u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_0_Bits.MLT */
+#define IFX_GTM_DPLL_CTRL_0_MLT_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_0_Bits.MLT */
+#define IFX_GTM_DPLL_CTRL_0_MLT_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_0_Bits.RMO */
+#define IFX_GTM_DPLL_CTRL_0_RMO_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_0_Bits.RMO */
+#define IFX_GTM_DPLL_CTRL_0_RMO_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_0_Bits.RMO */
+#define IFX_GTM_DPLL_CTRL_0_RMO_OFF (31u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_0_Bits.SEN */
+#define IFX_GTM_DPLL_CTRL_0_SEN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_0_Bits.SEN */
+#define IFX_GTM_DPLL_CTRL_0_SEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_0_Bits.SEN */
+#define IFX_GTM_DPLL_CTRL_0_SEN_OFF (29u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_0_SHADOW_STATE_Bits.AMS */
+#define IFX_GTM_DPLL_CTRL_0_SHADOW_STATE_AMS_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_0_SHADOW_STATE_Bits.AMS */
+#define IFX_GTM_DPLL_CTRL_0_SHADOW_STATE_AMS_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_0_SHADOW_STATE_Bits.AMS */
+#define IFX_GTM_DPLL_CTRL_0_SHADOW_STATE_AMS_OFF (25u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_0_SHADOW_STATE_Bits.IDS */
+#define IFX_GTM_DPLL_CTRL_0_SHADOW_STATE_IDS_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_0_SHADOW_STATE_Bits.IDS */
+#define IFX_GTM_DPLL_CTRL_0_SHADOW_STATE_IDS_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_0_SHADOW_STATE_Bits.IDS */
+#define IFX_GTM_DPLL_CTRL_0_SHADOW_STATE_IDS_OFF (27u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_0_SHADOW_STATE_Bits.IFP */
+#define IFX_GTM_DPLL_CTRL_0_SHADOW_STATE_IFP_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_0_SHADOW_STATE_Bits.IFP */
+#define IFX_GTM_DPLL_CTRL_0_SHADOW_STATE_IFP_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_0_SHADOW_STATE_Bits.IFP */
+#define IFX_GTM_DPLL_CTRL_0_SHADOW_STATE_IFP_OFF (10u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_0_SHADOW_STATE_Bits.RMO */
+#define IFX_GTM_DPLL_CTRL_0_SHADOW_STATE_RMO_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_0_SHADOW_STATE_Bits.RMO */
+#define IFX_GTM_DPLL_CTRL_0_SHADOW_STATE_RMO_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_0_SHADOW_STATE_Bits.RMO */
+#define IFX_GTM_DPLL_CTRL_0_SHADOW_STATE_RMO_OFF (31u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.AMT */
+#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_AMT_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.AMT */
+#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_AMT_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.AMT */
+#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_AMT_OFF (26u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.IDS */
+#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_IDS_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.IDS */
+#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_IDS_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.IDS */
+#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_IDS_OFF (27u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.IDT */
+#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_IDT_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.IDT */
+#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_IDT_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.IDT */
+#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_IDT_OFF (28u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.IFP */
+#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_IFP_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.IFP */
+#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_IFP_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.IFP */
+#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_IFP_OFF (10u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.MLT */
+#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_MLT_LEN (10u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.MLT */
+#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_MLT_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.MLT */
+#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_MLT_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.RMO */
+#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_RMO_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.RMO */
+#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_RMO_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.RMO */
+#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_RMO_OFF (31u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_0_Bits.SNU */
+#define IFX_GTM_DPLL_CTRL_0_SNU_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_0_Bits.SNU */
+#define IFX_GTM_DPLL_CTRL_0_SNU_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_0_Bits.SNU */
+#define IFX_GTM_DPLL_CTRL_0_SNU_OFF (11u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_0_Bits.TEN */
+#define IFX_GTM_DPLL_CTRL_0_TEN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_0_Bits.TEN */
+#define IFX_GTM_DPLL_CTRL_0_TEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_0_Bits.TEN */
+#define IFX_GTM_DPLL_CTRL_0_TEN_OFF (30u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_0_Bits.TNU */
+#define IFX_GTM_DPLL_CTRL_0_TNU_LEN (9u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_0_Bits.TNU */
+#define IFX_GTM_DPLL_CTRL_0_TNU_MSK (0x1ffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_0_Bits.TNU */
+#define IFX_GTM_DPLL_CTRL_0_TNU_OFF (16u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_1_Bits.COA */
+#define IFX_GTM_DPLL_CTRL_1_COA_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_1_Bits.COA */
+#define IFX_GTM_DPLL_CTRL_1_COA_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_1_Bits.COA */
+#define IFX_GTM_DPLL_CTRL_1_COA_OFF (3u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_1_Bits.DEN */
+#define IFX_GTM_DPLL_CTRL_1_DEN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_1_Bits.DEN */
+#define IFX_GTM_DPLL_CTRL_1_DEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_1_Bits.DEN */
+#define IFX_GTM_DPLL_CTRL_1_DEN_OFF (1u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_1_Bits.DLM1 */
+#define IFX_GTM_DPLL_CTRL_1_DLM1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_1_Bits.DLM1 */
+#define IFX_GTM_DPLL_CTRL_1_DLM1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_1_Bits.DLM1 */
+#define IFX_GTM_DPLL_CTRL_1_DLM1_OFF (6u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_1_Bits.DLM2 */
+#define IFX_GTM_DPLL_CTRL_1_DLM2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_1_Bits.DLM2 */
+#define IFX_GTM_DPLL_CTRL_1_DLM2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_1_Bits.DLM2 */
+#define IFX_GTM_DPLL_CTRL_1_DLM2_OFF (9u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_1_Bits.DMO */
+#define IFX_GTM_DPLL_CTRL_1_DMO_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_1_Bits.DMO */
+#define IFX_GTM_DPLL_CTRL_1_DMO_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_1_Bits.DMO */
+#define IFX_GTM_DPLL_CTRL_1_DMO_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_1_Bits.IDDS */
+#define IFX_GTM_DPLL_CTRL_1_IDDS_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_1_Bits.IDDS */
+#define IFX_GTM_DPLL_CTRL_1_IDDS_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_1_Bits.IDDS */
+#define IFX_GTM_DPLL_CTRL_1_IDDS_OFF (2u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_1_Bits.LCD */
+#define IFX_GTM_DPLL_CTRL_1_LCD_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_1_Bits.LCD */
+#define IFX_GTM_DPLL_CTRL_1_LCD_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_1_Bits.LCD */
+#define IFX_GTM_DPLL_CTRL_1_LCD_OFF (22u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_1_Bits.PCM1 */
+#define IFX_GTM_DPLL_CTRL_1_PCM1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_1_Bits.PCM1 */
+#define IFX_GTM_DPLL_CTRL_1_PCM1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_1_Bits.PCM1 */
+#define IFX_GTM_DPLL_CTRL_1_PCM1_OFF (7u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_1_Bits.PCM2 */
+#define IFX_GTM_DPLL_CTRL_1_PCM2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_1_Bits.PCM2 */
+#define IFX_GTM_DPLL_CTRL_1_PCM2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_1_Bits.PCM2 */
+#define IFX_GTM_DPLL_CTRL_1_PCM2_OFF (10u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_1_Bits.PIT */
+#define IFX_GTM_DPLL_CTRL_1_PIT_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_1_Bits.PIT */
+#define IFX_GTM_DPLL_CTRL_1_PIT_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_1_Bits.PIT */
+#define IFX_GTM_DPLL_CTRL_1_PIT_OFF (4u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_1_Bits.SGE1 */
+#define IFX_GTM_DPLL_CTRL_1_SGE1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_1_Bits.SGE1 */
+#define IFX_GTM_DPLL_CTRL_1_SGE1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_1_Bits.SGE1 */
+#define IFX_GTM_DPLL_CTRL_1_SGE1_OFF (5u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_1_Bits.SGE2 */
+#define IFX_GTM_DPLL_CTRL_1_SGE2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_1_Bits.SGE2 */
+#define IFX_GTM_DPLL_CTRL_1_SGE2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_1_Bits.SGE2 */
+#define IFX_GTM_DPLL_CTRL_1_SGE2_OFF (8u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.COA */
+#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_COA_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.COA */
+#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_COA_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.COA */
+#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_COA_OFF (3u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.DLM1 */
+#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_DLM1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.DLM1 */
+#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_DLM1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.DLM1 */
+#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_DLM1_OFF (6u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.DMO */
+#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_DMO_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.DMO */
+#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_DMO_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.DMO */
+#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_DMO_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.PCM1 */
+#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_PCM1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.PCM1 */
+#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_PCM1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.PCM1 */
+#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_PCM1_OFF (7u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.PIT */
+#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_PIT_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.PIT */
+#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_PIT_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.PIT */
+#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_PIT_OFF (4u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.SGE1 */
+#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_SGE1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.SGE1 */
+#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_SGE1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.SGE1 */
+#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_SGE1_OFF (5u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_1_Bits.SMC */
+#define IFX_GTM_DPLL_CTRL_1_SMC_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_1_Bits.SMC */
+#define IFX_GTM_DPLL_CTRL_1_SMC_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_1_Bits.SMC */
+#define IFX_GTM_DPLL_CTRL_1_SMC_OFF (27u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_1_Bits.SSL */
+#define IFX_GTM_DPLL_CTRL_1_SSL_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_1_Bits.SSL */
+#define IFX_GTM_DPLL_CTRL_1_SSL_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_1_Bits.SSL */
+#define IFX_GTM_DPLL_CTRL_1_SSL_OFF (28u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_1_Bits.SWR */
+#define IFX_GTM_DPLL_CTRL_1_SWR_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_1_Bits.SWR */
+#define IFX_GTM_DPLL_CTRL_1_SWR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_1_Bits.SWR */
+#define IFX_GTM_DPLL_CTRL_1_SWR_OFF (23u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_1_Bits.SYN_NS */
+#define IFX_GTM_DPLL_CTRL_1_SYN_NS_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_1_Bits.SYN_NS */
+#define IFX_GTM_DPLL_CTRL_1_SYN_NS_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_1_Bits.SYN_NS */
+#define IFX_GTM_DPLL_CTRL_1_SYN_NS_OFF (11u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_1_Bits.SYN_NT */
+#define IFX_GTM_DPLL_CTRL_1_SYN_NT_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_1_Bits.SYN_NT */
+#define IFX_GTM_DPLL_CTRL_1_SYN_NT_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_1_Bits.SYN_NT */
+#define IFX_GTM_DPLL_CTRL_1_SYN_NT_OFF (16u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_1_Bits.SYSF */
+#define IFX_GTM_DPLL_CTRL_1_SYSF_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_1_Bits.SYSF */
+#define IFX_GTM_DPLL_CTRL_1_SYSF_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_1_Bits.SYSF */
+#define IFX_GTM_DPLL_CTRL_1_SYSF_OFF (24u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_1_Bits.TS0_HRS */
+#define IFX_GTM_DPLL_CTRL_1_TS0_HRS_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_1_Bits.TS0_HRS */
+#define IFX_GTM_DPLL_CTRL_1_TS0_HRS_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_1_Bits.TS0_HRS */
+#define IFX_GTM_DPLL_CTRL_1_TS0_HRS_OFF (25u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_1_Bits.TS0_HRT */
+#define IFX_GTM_DPLL_CTRL_1_TS0_HRT_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_1_Bits.TS0_HRT */
+#define IFX_GTM_DPLL_CTRL_1_TS0_HRT_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_1_Bits.TS0_HRT */
+#define IFX_GTM_DPLL_CTRL_1_TS0_HRT_OFF (26u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_1_Bits.TSL */
+#define IFX_GTM_DPLL_CTRL_1_TSL_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_1_Bits.TSL */
+#define IFX_GTM_DPLL_CTRL_1_TSL_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_1_Bits.TSL */
+#define IFX_GTM_DPLL_CTRL_1_TSL_OFF (30u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_2_Bits.AEN0 */
+#define IFX_GTM_DPLL_CTRL_2_AEN0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_2_Bits.AEN0 */
+#define IFX_GTM_DPLL_CTRL_2_AEN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_2_Bits.AEN0 */
+#define IFX_GTM_DPLL_CTRL_2_AEN0_OFF (8u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_2_Bits.AEN1 */
+#define IFX_GTM_DPLL_CTRL_2_AEN1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_2_Bits.AEN1 */
+#define IFX_GTM_DPLL_CTRL_2_AEN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_2_Bits.AEN1 */
+#define IFX_GTM_DPLL_CTRL_2_AEN1_OFF (9u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_2_Bits.AEN2 */
+#define IFX_GTM_DPLL_CTRL_2_AEN2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_2_Bits.AEN2 */
+#define IFX_GTM_DPLL_CTRL_2_AEN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_2_Bits.AEN2 */
+#define IFX_GTM_DPLL_CTRL_2_AEN2_OFF (10u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_2_Bits.AEN3 */
+#define IFX_GTM_DPLL_CTRL_2_AEN3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_2_Bits.AEN3 */
+#define IFX_GTM_DPLL_CTRL_2_AEN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_2_Bits.AEN3 */
+#define IFX_GTM_DPLL_CTRL_2_AEN3_OFF (11u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_2_Bits.AEN4 */
+#define IFX_GTM_DPLL_CTRL_2_AEN4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_2_Bits.AEN4 */
+#define IFX_GTM_DPLL_CTRL_2_AEN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_2_Bits.AEN4 */
+#define IFX_GTM_DPLL_CTRL_2_AEN4_OFF (12u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_2_Bits.AEN5 */
+#define IFX_GTM_DPLL_CTRL_2_AEN5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_2_Bits.AEN5 */
+#define IFX_GTM_DPLL_CTRL_2_AEN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_2_Bits.AEN5 */
+#define IFX_GTM_DPLL_CTRL_2_AEN5_OFF (13u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_2_Bits.AEN6 */
+#define IFX_GTM_DPLL_CTRL_2_AEN6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_2_Bits.AEN6 */
+#define IFX_GTM_DPLL_CTRL_2_AEN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_2_Bits.AEN6 */
+#define IFX_GTM_DPLL_CTRL_2_AEN6_OFF (14u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_2_Bits.AEN7 */
+#define IFX_GTM_DPLL_CTRL_2_AEN7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_2_Bits.AEN7 */
+#define IFX_GTM_DPLL_CTRL_2_AEN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_2_Bits.AEN7 */
+#define IFX_GTM_DPLL_CTRL_2_AEN7_OFF (15u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_2_Bits.WAD0 */
+#define IFX_GTM_DPLL_CTRL_2_WAD0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_2_Bits.WAD0 */
+#define IFX_GTM_DPLL_CTRL_2_WAD0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_2_Bits.WAD0 */
+#define IFX_GTM_DPLL_CTRL_2_WAD0_OFF (16u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_2_Bits.WAD1 */
+#define IFX_GTM_DPLL_CTRL_2_WAD1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_2_Bits.WAD1 */
+#define IFX_GTM_DPLL_CTRL_2_WAD1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_2_Bits.WAD1 */
+#define IFX_GTM_DPLL_CTRL_2_WAD1_OFF (17u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_2_Bits.WAD2 */
+#define IFX_GTM_DPLL_CTRL_2_WAD2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_2_Bits.WAD2 */
+#define IFX_GTM_DPLL_CTRL_2_WAD2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_2_Bits.WAD2 */
+#define IFX_GTM_DPLL_CTRL_2_WAD2_OFF (18u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_2_Bits.WAD3 */
+#define IFX_GTM_DPLL_CTRL_2_WAD3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_2_Bits.WAD3 */
+#define IFX_GTM_DPLL_CTRL_2_WAD3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_2_Bits.WAD3 */
+#define IFX_GTM_DPLL_CTRL_2_WAD3_OFF (19u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_2_Bits.WAD4 */
+#define IFX_GTM_DPLL_CTRL_2_WAD4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_2_Bits.WAD4 */
+#define IFX_GTM_DPLL_CTRL_2_WAD4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_2_Bits.WAD4 */
+#define IFX_GTM_DPLL_CTRL_2_WAD4_OFF (20u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_2_Bits.WAD5 */
+#define IFX_GTM_DPLL_CTRL_2_WAD5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_2_Bits.WAD5 */
+#define IFX_GTM_DPLL_CTRL_2_WAD5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_2_Bits.WAD5 */
+#define IFX_GTM_DPLL_CTRL_2_WAD5_OFF (21u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_2_Bits.WAD6 */
+#define IFX_GTM_DPLL_CTRL_2_WAD6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_2_Bits.WAD6 */
+#define IFX_GTM_DPLL_CTRL_2_WAD6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_2_Bits.WAD6 */
+#define IFX_GTM_DPLL_CTRL_2_WAD6_OFF (22u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_2_Bits.WAD7 */
+#define IFX_GTM_DPLL_CTRL_2_WAD7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_2_Bits.WAD7 */
+#define IFX_GTM_DPLL_CTRL_2_WAD7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_2_Bits.WAD7 */
+#define IFX_GTM_DPLL_CTRL_2_WAD7_OFF (23u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_3_Bits.AEN10 */
+#define IFX_GTM_DPLL_CTRL_3_AEN10_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_3_Bits.AEN10 */
+#define IFX_GTM_DPLL_CTRL_3_AEN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_3_Bits.AEN10 */
+#define IFX_GTM_DPLL_CTRL_3_AEN10_OFF (10u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_3_Bits.AEN11 */
+#define IFX_GTM_DPLL_CTRL_3_AEN11_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_3_Bits.AEN11 */
+#define IFX_GTM_DPLL_CTRL_3_AEN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_3_Bits.AEN11 */
+#define IFX_GTM_DPLL_CTRL_3_AEN11_OFF (11u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_3_Bits.AEN12 */
+#define IFX_GTM_DPLL_CTRL_3_AEN12_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_3_Bits.AEN12 */
+#define IFX_GTM_DPLL_CTRL_3_AEN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_3_Bits.AEN12 */
+#define IFX_GTM_DPLL_CTRL_3_AEN12_OFF (12u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_3_Bits.AEN13 */
+#define IFX_GTM_DPLL_CTRL_3_AEN13_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_3_Bits.AEN13 */
+#define IFX_GTM_DPLL_CTRL_3_AEN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_3_Bits.AEN13 */
+#define IFX_GTM_DPLL_CTRL_3_AEN13_OFF (13u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_3_Bits.AEN14 */
+#define IFX_GTM_DPLL_CTRL_3_AEN14_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_3_Bits.AEN14 */
+#define IFX_GTM_DPLL_CTRL_3_AEN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_3_Bits.AEN14 */
+#define IFX_GTM_DPLL_CTRL_3_AEN14_OFF (14u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_3_Bits.AEN15 */
+#define IFX_GTM_DPLL_CTRL_3_AEN15_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_3_Bits.AEN15 */
+#define IFX_GTM_DPLL_CTRL_3_AEN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_3_Bits.AEN15 */
+#define IFX_GTM_DPLL_CTRL_3_AEN15_OFF (15u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_3_Bits.AEN8 */
+#define IFX_GTM_DPLL_CTRL_3_AEN8_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_3_Bits.AEN8 */
+#define IFX_GTM_DPLL_CTRL_3_AEN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_3_Bits.AEN8 */
+#define IFX_GTM_DPLL_CTRL_3_AEN8_OFF (8u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_3_Bits.AEN9 */
+#define IFX_GTM_DPLL_CTRL_3_AEN9_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_3_Bits.AEN9 */
+#define IFX_GTM_DPLL_CTRL_3_AEN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_3_Bits.AEN9 */
+#define IFX_GTM_DPLL_CTRL_3_AEN9_OFF (9u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_3_Bits.WAD10 */
+#define IFX_GTM_DPLL_CTRL_3_WAD10_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_3_Bits.WAD10 */
+#define IFX_GTM_DPLL_CTRL_3_WAD10_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_3_Bits.WAD10 */
+#define IFX_GTM_DPLL_CTRL_3_WAD10_OFF (18u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_3_Bits.WAD11 */
+#define IFX_GTM_DPLL_CTRL_3_WAD11_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_3_Bits.WAD11 */
+#define IFX_GTM_DPLL_CTRL_3_WAD11_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_3_Bits.WAD11 */
+#define IFX_GTM_DPLL_CTRL_3_WAD11_OFF (19u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_3_Bits.WAD12 */
+#define IFX_GTM_DPLL_CTRL_3_WAD12_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_3_Bits.WAD12 */
+#define IFX_GTM_DPLL_CTRL_3_WAD12_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_3_Bits.WAD12 */
+#define IFX_GTM_DPLL_CTRL_3_WAD12_OFF (20u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_3_Bits.WAD13 */
+#define IFX_GTM_DPLL_CTRL_3_WAD13_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_3_Bits.WAD13 */
+#define IFX_GTM_DPLL_CTRL_3_WAD13_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_3_Bits.WAD13 */
+#define IFX_GTM_DPLL_CTRL_3_WAD13_OFF (21u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_3_Bits.WAD14 */
+#define IFX_GTM_DPLL_CTRL_3_WAD14_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_3_Bits.WAD14 */
+#define IFX_GTM_DPLL_CTRL_3_WAD14_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_3_Bits.WAD14 */
+#define IFX_GTM_DPLL_CTRL_3_WAD14_OFF (22u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_3_Bits.WAD15 */
+#define IFX_GTM_DPLL_CTRL_3_WAD15_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_3_Bits.WAD15 */
+#define IFX_GTM_DPLL_CTRL_3_WAD15_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_3_Bits.WAD15 */
+#define IFX_GTM_DPLL_CTRL_3_WAD15_OFF (23u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_3_Bits.WAD8 */
+#define IFX_GTM_DPLL_CTRL_3_WAD8_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_3_Bits.WAD8 */
+#define IFX_GTM_DPLL_CTRL_3_WAD8_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_3_Bits.WAD8 */
+#define IFX_GTM_DPLL_CTRL_3_WAD8_OFF (16u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_3_Bits.WAD9 */
+#define IFX_GTM_DPLL_CTRL_3_WAD9_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_3_Bits.WAD9 */
+#define IFX_GTM_DPLL_CTRL_3_WAD9_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_3_Bits.WAD9 */
+#define IFX_GTM_DPLL_CTRL_3_WAD9_OFF (17u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_4_Bits.AEN16 */
+#define IFX_GTM_DPLL_CTRL_4_AEN16_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_4_Bits.AEN16 */
+#define IFX_GTM_DPLL_CTRL_4_AEN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_4_Bits.AEN16 */
+#define IFX_GTM_DPLL_CTRL_4_AEN16_OFF (8u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_4_Bits.AEN17 */
+#define IFX_GTM_DPLL_CTRL_4_AEN17_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_4_Bits.AEN17 */
+#define IFX_GTM_DPLL_CTRL_4_AEN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_4_Bits.AEN17 */
+#define IFX_GTM_DPLL_CTRL_4_AEN17_OFF (9u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_4_Bits.AEN18 */
+#define IFX_GTM_DPLL_CTRL_4_AEN18_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_4_Bits.AEN18 */
+#define IFX_GTM_DPLL_CTRL_4_AEN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_4_Bits.AEN18 */
+#define IFX_GTM_DPLL_CTRL_4_AEN18_OFF (10u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_4_Bits.AEN19 */
+#define IFX_GTM_DPLL_CTRL_4_AEN19_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_4_Bits.AEN19 */
+#define IFX_GTM_DPLL_CTRL_4_AEN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_4_Bits.AEN19 */
+#define IFX_GTM_DPLL_CTRL_4_AEN19_OFF (11u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_4_Bits.AEN20 */
+#define IFX_GTM_DPLL_CTRL_4_AEN20_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_4_Bits.AEN20 */
+#define IFX_GTM_DPLL_CTRL_4_AEN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_4_Bits.AEN20 */
+#define IFX_GTM_DPLL_CTRL_4_AEN20_OFF (12u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_4_Bits.AEN21 */
+#define IFX_GTM_DPLL_CTRL_4_AEN21_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_4_Bits.AEN21 */
+#define IFX_GTM_DPLL_CTRL_4_AEN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_4_Bits.AEN21 */
+#define IFX_GTM_DPLL_CTRL_4_AEN21_OFF (13u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_4_Bits.AEN22 */
+#define IFX_GTM_DPLL_CTRL_4_AEN22_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_4_Bits.AEN22 */
+#define IFX_GTM_DPLL_CTRL_4_AEN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_4_Bits.AEN22 */
+#define IFX_GTM_DPLL_CTRL_4_AEN22_OFF (14u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_4_Bits.AEN23 */
+#define IFX_GTM_DPLL_CTRL_4_AEN23_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_4_Bits.AEN23 */
+#define IFX_GTM_DPLL_CTRL_4_AEN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_4_Bits.AEN23 */
+#define IFX_GTM_DPLL_CTRL_4_AEN23_OFF (15u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_4_Bits.WAD16 */
+#define IFX_GTM_DPLL_CTRL_4_WAD16_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_4_Bits.WAD16 */
+#define IFX_GTM_DPLL_CTRL_4_WAD16_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_4_Bits.WAD16 */
+#define IFX_GTM_DPLL_CTRL_4_WAD16_OFF (16u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_4_Bits.WAD17 */
+#define IFX_GTM_DPLL_CTRL_4_WAD17_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_4_Bits.WAD17 */
+#define IFX_GTM_DPLL_CTRL_4_WAD17_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_4_Bits.WAD17 */
+#define IFX_GTM_DPLL_CTRL_4_WAD17_OFF (17u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_4_Bits.WAD18 */
+#define IFX_GTM_DPLL_CTRL_4_WAD18_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_4_Bits.WAD18 */
+#define IFX_GTM_DPLL_CTRL_4_WAD18_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_4_Bits.WAD18 */
+#define IFX_GTM_DPLL_CTRL_4_WAD18_OFF (18u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_4_Bits.WAD19 */
+#define IFX_GTM_DPLL_CTRL_4_WAD19_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_4_Bits.WAD19 */
+#define IFX_GTM_DPLL_CTRL_4_WAD19_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_4_Bits.WAD19 */
+#define IFX_GTM_DPLL_CTRL_4_WAD19_OFF (19u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_4_Bits.WAD20 */
+#define IFX_GTM_DPLL_CTRL_4_WAD20_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_4_Bits.WAD20 */
+#define IFX_GTM_DPLL_CTRL_4_WAD20_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_4_Bits.WAD20 */
+#define IFX_GTM_DPLL_CTRL_4_WAD20_OFF (20u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_4_Bits.WAD21 */
+#define IFX_GTM_DPLL_CTRL_4_WAD21_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_4_Bits.WAD21 */
+#define IFX_GTM_DPLL_CTRL_4_WAD21_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_4_Bits.WAD21 */
+#define IFX_GTM_DPLL_CTRL_4_WAD21_OFF (21u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_4_Bits.WAD22 */
+#define IFX_GTM_DPLL_CTRL_4_WAD22_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_4_Bits.WAD22 */
+#define IFX_GTM_DPLL_CTRL_4_WAD22_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_4_Bits.WAD22 */
+#define IFX_GTM_DPLL_CTRL_4_WAD22_OFF (22u)
+
+/** \brief Length for Ifx_GTM_DPLL_CTRL_4_Bits.WAD23 */
+#define IFX_GTM_DPLL_CTRL_4_WAD23_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_CTRL_4_Bits.WAD23 */
+#define IFX_GTM_DPLL_CTRL_4_WAD23_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_CTRL_4_Bits.WAD23 */
+#define IFX_GTM_DPLL_CTRL_4_WAD23_OFF (23u)
+
+/** \brief Length for Ifx_GTM_DPLL_DLA_Bits.DLA */
+#define IFX_GTM_DPLL_DLA_DLA_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_DLA_Bits.DLA */
+#define IFX_GTM_DPLL_DLA_DLA_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_DLA_Bits.DLA */
+#define IFX_GTM_DPLL_DLA_DLA_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_DT_S_ACT_Bits.DT_S_ACT */
+#define IFX_GTM_DPLL_DT_S_ACT_DT_S_ACT_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_DT_S_ACT_Bits.DT_S_ACT */
+#define IFX_GTM_DPLL_DT_S_ACT_DT_S_ACT_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_DT_S_ACT_Bits.DT_S_ACT */
+#define IFX_GTM_DPLL_DT_S_ACT_DT_S_ACT_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_DT_S_Bits.DT_S */
+#define IFX_GTM_DPLL_DT_S_DT_S_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_DT_S_Bits.DT_S */
+#define IFX_GTM_DPLL_DT_S_DT_S_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_DT_S_Bits.DT_S */
+#define IFX_GTM_DPLL_DT_S_DT_S_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_DT_T_ACT_Bits.DT_T_ACT */
+#define IFX_GTM_DPLL_DT_T_ACT_DT_T_ACT_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_DT_T_ACT_Bits.DT_T_ACT */
+#define IFX_GTM_DPLL_DT_T_ACT_DT_T_ACT_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_DT_T_ACT_Bits.DT_T_ACT */
+#define IFX_GTM_DPLL_DT_T_ACT_DT_T_ACT_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_DTA_Bits.DTA */
+#define IFX_GTM_DPLL_DTA_DTA_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_DTA_Bits.DTA */
+#define IFX_GTM_DPLL_DTA_DTA_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_DTA_Bits.DTA */
+#define IFX_GTM_DPLL_DTA_DTA_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_EDT_S_Bits.EDT_S */
+#define IFX_GTM_DPLL_EDT_S_EDT_S_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_EDT_S_Bits.EDT_S */
+#define IFX_GTM_DPLL_EDT_S_EDT_S_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_EDT_S_Bits.EDT_S */
+#define IFX_GTM_DPLL_EDT_S_EDT_S_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_EDT_T_Bits.EDT_T */
+#define IFX_GTM_DPLL_EDT_T_EDT_T_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_EDT_T_Bits.EDT_T */
+#define IFX_GTM_DPLL_EDT_T_EDT_T_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_EDT_T_Bits.EDT_T */
+#define IFX_GTM_DPLL_EDT_T_EDT_T_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.CDSI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_CDSI_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.CDSI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_CDSI_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.CDSI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_CDSI_EIRQ_EN_OFF (24u)
+
+/** \brief Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.CDTI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_CDTI_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.CDTI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_CDTI_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.CDTI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_CDTI_EIRQ_EN_OFF (23u)
+
+/** \brief Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.DCGI */
+#define IFX_GTM_DPLL_EIRQ_EN_DCGI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.DCGI */
+#define IFX_GTM_DPLL_EIRQ_EN_DCGI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.DCGI */
+#define IFX_GTM_DPLL_EIRQ_EN_DCGI_OFF (27u)
+
+/** \brief Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.EI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_EI_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.EI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_EI_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.EI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_EI_EIRQ_EN_OFF (15u)
+
+/** \brief Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.GL1I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_GL1I_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.GL1I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_GL1I_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.GL1I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_GL1I_EIRQ_EN_OFF (13u)
+
+/** \brief Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.GL2I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_GL2I_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.GL2I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_GL2I_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.GL2I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_GL2I_EIRQ_EN_OFF (16u)
+
+/** \brief Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.LL1I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_LL1I_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.LL1I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_LL1I_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.LL1I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_LL1I_EIRQ_EN_OFF (14u)
+
+/** \brief Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.LL2I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_LL2I_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.LL2I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_LL2I_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.LL2I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_LL2I_EIRQ_EN_OFF (17u)
+
+/** \brief Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.MSI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_MSI_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.MSI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_MSI_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.MSI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_MSI_EIRQ_EN_OFF (6u)
+
+/** \brief Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.MTI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_MTI_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.MTI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_MTI_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.MTI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_MTI_EIRQ_EN_OFF (7u)
+
+/** \brief Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.PDI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_PDI_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.PDI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_PDI_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.PDI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_PDI_EIRQ_EN_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.PEI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_PEI_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.PEI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_PEI_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.PEI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_PEI_EIRQ_EN_OFF (1u)
+
+/** \brief Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.PWI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_PWI_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.PWI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_PWI_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.PWI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_PWI_EIRQ_EN_OFF (10u)
+
+/** \brief Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.SASI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_SASI_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.SASI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_SASI_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.SASI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_SASI_EIRQ_EN_OFF (8u)
+
+/** \brief Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.SISI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_SISI_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.SISI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_SISI_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.SISI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_SISI_EIRQ_EN_OFF (4u)
+
+/** \brief Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.SORI */
+#define IFX_GTM_DPLL_EIRQ_EN_SORI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.SORI */
+#define IFX_GTM_DPLL_EIRQ_EN_SORI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.SORI */
+#define IFX_GTM_DPLL_EIRQ_EN_SORI_OFF (26u)
+
+/** \brief Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.TASI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_TASI_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.TASI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_TASI_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.TASI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_TASI_EIRQ_EN_OFF (9u)
+
+/** \brief Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.TAXI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_TAXI_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.TAXI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_TAXI_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.TAXI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_TAXI_EIRQ_EN_OFF (3u)
+
+/** \brief Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.TE0I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_TE0I_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.TE0I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_TE0I_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.TE0I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_TE0I_EIRQ_EN_OFF (18u)
+
+/** \brief Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.TE1I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_TE1I_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.TE1I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_TE1I_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.TE1I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_TE1I_EIRQ_EN_OFF (19u)
+
+/** \brief Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.TE2I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_TE2I_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.TE2I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_TE2I_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.TE2I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_TE2I_EIRQ_EN_OFF (20u)
+
+/** \brief Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.TE3I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_TE3I_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.TE3I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_TE3I_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.TE3I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_TE3I_EIRQ_EN_OFF (21u)
+
+/** \brief Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.TE4I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_TE4I_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.TE4I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_TE4I_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.TE4I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_TE4I_EIRQ_EN_OFF (22u)
+
+/** \brief Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.TINI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_TINI_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.TINI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_TINI_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.TINI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_TINI_EIRQ_EN_OFF (2u)
+
+/** \brief Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.TISI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_TISI_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.TISI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_TISI_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.TISI_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_TISI_EIRQ_EN_OFF (5u)
+
+/** \brief Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.TORI */
+#define IFX_GTM_DPLL_EIRQ_EN_TORI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.TORI */
+#define IFX_GTM_DPLL_EIRQ_EN_TORI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.TORI */
+#define IFX_GTM_DPLL_EIRQ_EN_TORI_OFF (25u)
+
+/** \brief Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.W1I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_W1I_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.W1I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_W1I_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.W1I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_W1I_EIRQ_EN_OFF (12u)
+
+/** \brief Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.W2I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_W2I_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.W2I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_W2I_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.W2I_EIRQ_EN */
+#define IFX_GTM_DPLL_EIRQ_EN_W2I_EIRQ_EN_OFF (11u)
+
+/** \brief Length for Ifx_GTM_DPLL_FTV_S_Bits.STATE_FT */
+#define IFX_GTM_DPLL_FTV_S_STATE_FT_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_FTV_S_Bits.STATE_FT */
+#define IFX_GTM_DPLL_FTV_S_STATE_FT_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_FTV_S_Bits.STATE_FT */
+#define IFX_GTM_DPLL_FTV_S_STATE_FT_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_FTV_T_Bits.TRIGGER_FT */
+#define IFX_GTM_DPLL_FTV_T_TRIGGER_FT_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_FTV_T_Bits.TRIGGER_FT */
+#define IFX_GTM_DPLL_FTV_T_TRIGGER_FT_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_FTV_T_Bits.TRIGGER_FT */
+#define IFX_GTM_DPLL_FTV_T_TRIGGER_FT_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_ID_PMTR_Bits.ID_PMTR_x */
+#define IFX_GTM_DPLL_ID_PMTR_ID_PMTR_X_LEN (9u)
+
+/** \brief Mask for Ifx_GTM_DPLL_ID_PMTR_Bits.ID_PMTR_x */
+#define IFX_GTM_DPLL_ID_PMTR_ID_PMTR_X_MSK (0x1ffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_ID_PMTR_Bits.ID_PMTR_x */
+#define IFX_GTM_DPLL_ID_PMTR_ID_PMTR_X_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_INC_CNT1_Bits.INC_CNT1 */
+#define IFX_GTM_DPLL_INC_CNT1_INC_CNT1_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_INC_CNT1_Bits.INC_CNT1 */
+#define IFX_GTM_DPLL_INC_CNT1_INC_CNT1_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_INC_CNT1_Bits.INC_CNT1 */
+#define IFX_GTM_DPLL_INC_CNT1_INC_CNT1_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_INC_CNT2_Bits.INC_CNT2 */
+#define IFX_GTM_DPLL_INC_CNT2_INC_CNT2_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_INC_CNT2_Bits.INC_CNT2 */
+#define IFX_GTM_DPLL_INC_CNT2_INC_CNT2_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_INC_CNT2_Bits.INC_CNT2 */
+#define IFX_GTM_DPLL_INC_CNT2_INC_CNT2_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_EN_Bits.CDSI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_CDSI_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.CDSI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_CDSI_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.CDSI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_CDSI_IRQ_EN_OFF (24u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_EN_Bits.CDTI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_CDTI_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.CDTI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_CDTI_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.CDTI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_CDTI_IRQ_EN_OFF (23u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_EN_Bits.DCGI */
+#define IFX_GTM_DPLL_IRQ_EN_DCGI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.DCGI */
+#define IFX_GTM_DPLL_IRQ_EN_DCGI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.DCGI */
+#define IFX_GTM_DPLL_IRQ_EN_DCGI_OFF (27u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_EN_Bits.EI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_EI_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.EI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_EI_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.EI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_EI_IRQ_EN_OFF (15u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_EN_Bits.GL1I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_GL1I_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.GL1I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_GL1I_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.GL1I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_GL1I_IRQ_EN_OFF (13u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_EN_Bits.GL2I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_GL2I_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.GL2I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_GL2I_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.GL2I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_GL2I_IRQ_EN_OFF (16u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_EN_Bits.LL1I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_LL1I_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.LL1I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_LL1I_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.LL1I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_LL1I_IRQ_EN_OFF (14u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_EN_Bits.LL2I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_LL2I_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.LL2I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_LL2I_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.LL2I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_LL2I_IRQ_EN_OFF (17u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_EN_Bits.MSI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_MSI_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.MSI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_MSI_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.MSI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_MSI_IRQ_EN_OFF (6u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_EN_Bits.MTI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_MTI_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.MTI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_MTI_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.MTI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_MTI_IRQ_EN_OFF (7u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_EN_Bits.PDI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_PDI_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.PDI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_PDI_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.PDI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_PDI_IRQ_EN_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_EN_Bits.PEI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_PEI_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.PEI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_PEI_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.PEI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_PEI_IRQ_EN_OFF (1u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_EN_Bits.PWI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_PWI_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.PWI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_PWI_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.PWI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_PWI_IRQ_EN_OFF (10u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_EN_Bits.SASI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_SASI_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.SASI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_SASI_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.SASI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_SASI_IRQ_EN_OFF (8u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_EN_Bits.SISI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_SISI_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.SISI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_SISI_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.SISI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_SISI_IRQ_EN_OFF (4u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_EN_Bits.SORI */
+#define IFX_GTM_DPLL_IRQ_EN_SORI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.SORI */
+#define IFX_GTM_DPLL_IRQ_EN_SORI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.SORI */
+#define IFX_GTM_DPLL_IRQ_EN_SORI_OFF (26u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_EN_Bits.TASI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_TASI_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.TASI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_TASI_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.TASI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_TASI_IRQ_EN_OFF (9u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_EN_Bits.TAXI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_TAXI_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.TAXI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_TAXI_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.TAXI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_TAXI_IRQ_EN_OFF (3u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_EN_Bits.TE0I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_TE0I_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.TE0I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_TE0I_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.TE0I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_TE0I_IRQ_EN_OFF (18u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_EN_Bits.TE1I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_TE1I_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.TE1I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_TE1I_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.TE1I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_TE1I_IRQ_EN_OFF (19u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_EN_Bits.TE2I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_TE2I_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.TE2I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_TE2I_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.TE2I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_TE2I_IRQ_EN_OFF (20u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_EN_Bits.TE3I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_TE3I_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.TE3I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_TE3I_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.TE3I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_TE3I_IRQ_EN_OFF (21u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_EN_Bits.TE4I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_TE4I_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.TE4I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_TE4I_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.TE4I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_TE4I_IRQ_EN_OFF (22u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_EN_Bits.TINI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_TINI_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.TINI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_TINI_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.TINI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_TINI_IRQ_EN_OFF (2u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_EN_Bits.TISI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_TISI_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.TISI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_TISI_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.TISI_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_TISI_IRQ_EN_OFF (5u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_EN_Bits.TORI */
+#define IFX_GTM_DPLL_IRQ_EN_TORI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.TORI */
+#define IFX_GTM_DPLL_IRQ_EN_TORI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.TORI */
+#define IFX_GTM_DPLL_IRQ_EN_TORI_OFF (25u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_EN_Bits.W1I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_W1I_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.W1I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_W1I_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.W1I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_W1I_IRQ_EN_OFF (12u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_EN_Bits.W2I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_W2I_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.W2I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_W2I_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.W2I_IRQ_EN */
+#define IFX_GTM_DPLL_IRQ_EN_W2I_IRQ_EN_OFF (11u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_CDSI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_CDSI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_CDSI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_CDSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_CDSI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_CDSI_OFF (24u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_CDTI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_CDTI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_CDTI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_CDTI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_CDTI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_CDTI_OFF (23u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_DCGI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_DCGI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_DCGI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_DCGI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_DCGI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_DCGI_OFF (27u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_EI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_EI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_EI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_EI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_EI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_EI_OFF (15u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_GL1I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_GL1I_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_GL1I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_GL1I_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_GL1I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_GL1I_OFF (13u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_GL2I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_GL2I_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_GL2I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_GL2I_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_GL2I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_GL2I_OFF (16u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_LL1I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_LL1I_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_LL1I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_LL1I_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_LL1I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_LL1I_OFF (14u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_LL2I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_LL2I_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_LL2I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_LL2I_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_LL2I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_LL2I_OFF (17u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_MSI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_MSI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_MSI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_MSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_MSI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_MSI_OFF (6u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_MTI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_MTI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_MTI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_MTI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_MTI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_MTI_OFF (7u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_PDI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_PDI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_PDI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_PDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_PDI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_PDI_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_PEI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_PEI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_PEI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_PEI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_PEI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_PEI_OFF (1u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_PWI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_PWI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_PWI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_PWI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_PWI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_PWI_OFF (10u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_SASI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_SASI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_SASI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_SASI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_SASI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_SASI_OFF (8u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_SISI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_SISI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_SISI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_SISI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_SISI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_SISI_OFF (4u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_SORI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_SORI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_SORI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_SORI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_SORI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_SORI_OFF (26u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TASI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TASI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TASI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TASI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TASI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TASI_OFF (9u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TAXI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TAXI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TAXI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TAXI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TAXI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TAXI_OFF (3u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TE0I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TE0I_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TE0I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TE0I_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TE0I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TE0I_OFF (18u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TE1I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TE1I_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TE1I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TE1I_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TE1I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TE1I_OFF (19u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TE2I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TE2I_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TE2I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TE2I_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TE2I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TE2I_OFF (20u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TE3I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TE3I_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TE3I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TE3I_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TE3I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TE3I_OFF (21u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TE4I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TE4I_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TE4I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TE4I_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TE4I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TE4I_OFF (22u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TINI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TINI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TINI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TINI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TINI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TINI_OFF (2u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TISI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TISI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TISI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TISI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TISI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TISI_OFF (5u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TORI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TORI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TORI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TORI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TORI */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TORI_OFF (25u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_W1I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_W1I_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_W1I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_W1I_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_W1I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_W1I_OFF (12u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_W2I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_W2I_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_W2I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_W2I_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_W2I */
+#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_W2I_OFF (11u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_DPLL_IRQ_MODE_IRQ_MODE_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_DPLL_IRQ_MODE_IRQ_MODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_DPLL_IRQ_MODE_IRQ_MODE_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.CDSI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_CDSI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.CDSI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_CDSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.CDSI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_CDSI_OFF (24u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.CDTI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_CDTI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.CDTI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_CDTI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.CDTI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_CDTI_OFF (23u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.DCGI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_DCGI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.DCGI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_DCGI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.DCGI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_DCGI_OFF (27u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.EI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_EI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.EI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_EI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.EI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_EI_OFF (15u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.GL1I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_GL1I_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.GL1I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_GL1I_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.GL1I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_GL1I_OFF (13u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.GL2I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_GL2I_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.GL2I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_GL2I_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.GL2I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_GL2I_OFF (16u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.LL1I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_LL1I_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.LL1I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_LL1I_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.LL1I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_LL1I_OFF (14u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.LL2I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_LL2I_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.LL2I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_LL2I_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.LL2I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_LL2I_OFF (17u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.MSI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_MSI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.MSI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_MSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.MSI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_MSI_OFF (6u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.MTI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_MTI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.MTI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_MTI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.MTI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_MTI_OFF (7u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.PDI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_PDI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.PDI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_PDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.PDI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_PDI_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.PEI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_PEI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.PEI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_PEI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.PEI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_PEI_OFF (1u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.PWI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_PWI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.PWI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_PWI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.PWI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_PWI_OFF (10u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.SASI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_SASI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.SASI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_SASI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.SASI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_SASI_OFF (8u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.SISI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_SISI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.SISI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_SISI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.SISI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_SISI_OFF (4u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.SORI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_SORI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.SORI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_SORI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.SORI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_SORI_OFF (26u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TASI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_TASI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TASI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_TASI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TASI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_TASI_OFF (9u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TAXI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_TAXI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TAXI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_TAXI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TAXI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_TAXI_OFF (3u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TE0I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_TE0I_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TE0I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_TE0I_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TE0I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_TE0I_OFF (18u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TE1I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_TE1I_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TE1I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_TE1I_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TE1I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_TE1I_OFF (19u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TE2I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_TE2I_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TE2I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_TE2I_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TE2I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_TE2I_OFF (20u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TE3I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_TE3I_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TE3I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_TE3I_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TE3I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_TE3I_OFF (21u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TE4I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_TE4I_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TE4I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_TE4I_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TE4I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_TE4I_OFF (22u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TINI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_TINI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TINI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_TINI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TINI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_TINI_OFF (2u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TISI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_TISI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TISI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_TISI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TISI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_TISI_OFF (5u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TORI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_TORI_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TORI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_TORI_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TORI */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_TORI_OFF (25u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.W1I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_W1I_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.W1I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_W1I_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.W1I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_W1I_OFF (12u)
+
+/** \brief Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.W2I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_W2I_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.W2I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_W2I_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.W2I */
+#define IFX_GTM_DPLL_IRQ_NOTIFY_W2I_OFF (11u)
+
+/** \brief Length for Ifx_GTM_DPLL_MEDT_S_Bits.MEDT_S */
+#define IFX_GTM_DPLL_MEDT_S_MEDT_S_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_MEDT_S_Bits.MEDT_S */
+#define IFX_GTM_DPLL_MEDT_S_MEDT_S_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_MEDT_S_Bits.MEDT_S */
+#define IFX_GTM_DPLL_MEDT_S_MEDT_S_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_MEDT_T_Bits.MEDT_T */
+#define IFX_GTM_DPLL_MEDT_T_MEDT_T_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_MEDT_T_Bits.MEDT_T */
+#define IFX_GTM_DPLL_MEDT_T_MEDT_T_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_MEDT_T_Bits.MEDT_T */
+#define IFX_GTM_DPLL_MEDT_T_MEDT_T_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_MLS1_Bits.MLS1 */
+#define IFX_GTM_DPLL_MLS1_MLS1_LEN (18u)
+
+/** \brief Mask for Ifx_GTM_DPLL_MLS1_Bits.MLS1 */
+#define IFX_GTM_DPLL_MLS1_MLS1_MSK (0x3ffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_MLS1_Bits.MLS1 */
+#define IFX_GTM_DPLL_MLS1_MLS1_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_MLS2_Bits.MLS2 */
+#define IFX_GTM_DPLL_MLS2_MLS2_LEN (18u)
+
+/** \brief Mask for Ifx_GTM_DPLL_MLS2_Bits.MLS2 */
+#define IFX_GTM_DPLL_MLS2_MLS2_MSK (0x3ffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_MLS2_Bits.MLS2 */
+#define IFX_GTM_DPLL_MLS2_MLS2_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_MPVAL1_Bits.MPVAL1 */
+#define IFX_GTM_DPLL_MPVAL1_MPVAL1_LEN (16u)
+
+/** \brief Mask for Ifx_GTM_DPLL_MPVAL1_Bits.MPVAL1 */
+#define IFX_GTM_DPLL_MPVAL1_MPVAL1_MSK (0xffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_MPVAL1_Bits.MPVAL1 */
+#define IFX_GTM_DPLL_MPVAL1_MPVAL1_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_MPVAL1_Bits.SIX1 */
+#define IFX_GTM_DPLL_MPVAL1_SIX1_LEN (8u)
+
+/** \brief Mask for Ifx_GTM_DPLL_MPVAL1_Bits.SIX1 */
+#define IFX_GTM_DPLL_MPVAL1_SIX1_MSK (0xffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_MPVAL1_Bits.SIX1 */
+#define IFX_GTM_DPLL_MPVAL1_SIX1_OFF (16u)
+
+/** \brief Length for Ifx_GTM_DPLL_MPVAL2_Bits.MPVAL2 */
+#define IFX_GTM_DPLL_MPVAL2_MPVAL2_LEN (16u)
+
+/** \brief Mask for Ifx_GTM_DPLL_MPVAL2_Bits.MPVAL2 */
+#define IFX_GTM_DPLL_MPVAL2_MPVAL2_MSK (0xffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_MPVAL2_Bits.MPVAL2 */
+#define IFX_GTM_DPLL_MPVAL2_MPVAL2_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_MPVAL2_Bits.SIX2 */
+#define IFX_GTM_DPLL_MPVAL2_SIX2_LEN (8u)
+
+/** \brief Mask for Ifx_GTM_DPLL_MPVAL2_Bits.SIX2 */
+#define IFX_GTM_DPLL_MPVAL2_SIX2_MSK (0xffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_MPVAL2_Bits.SIX2 */
+#define IFX_GTM_DPLL_MPVAL2_SIX2_OFF (16u)
+
+/** \brief Length for Ifx_GTM_DPLL_NA_Bits.DB */
+#define IFX_GTM_DPLL_NA_DB_LEN (10u)
+
+/** \brief Mask for Ifx_GTM_DPLL_NA_Bits.DB */
+#define IFX_GTM_DPLL_NA_DB_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_NA_Bits.DB */
+#define IFX_GTM_DPLL_NA_DB_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_NA_Bits.DW */
+#define IFX_GTM_DPLL_NA_DW_LEN (10u)
+
+/** \brief Mask for Ifx_GTM_DPLL_NA_Bits.DW */
+#define IFX_GTM_DPLL_NA_DW_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_NA_Bits.DW */
+#define IFX_GTM_DPLL_NA_DW_OFF (10u)
+
+/** \brief Length for Ifx_GTM_DPLL_NMB_S_Bits.NMB_S */
+#define IFX_GTM_DPLL_NMB_S_NMB_S_LEN (20u)
+
+/** \brief Mask for Ifx_GTM_DPLL_NMB_S_Bits.NMB_S */
+#define IFX_GTM_DPLL_NMB_S_NMB_S_MSK (0xfffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_NMB_S_Bits.NMB_S */
+#define IFX_GTM_DPLL_NMB_S_NMB_S_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_NMB_S_TAR_Bits.NMB_S_TAR */
+#define IFX_GTM_DPLL_NMB_S_TAR_NMB_S_TAR_LEN (20u)
+
+/** \brief Mask for Ifx_GTM_DPLL_NMB_S_TAR_Bits.NMB_S_TAR */
+#define IFX_GTM_DPLL_NMB_S_TAR_NMB_S_TAR_MSK (0xfffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_NMB_S_TAR_Bits.NMB_S_TAR */
+#define IFX_GTM_DPLL_NMB_S_TAR_NMB_S_TAR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_NMB_S_TAR_OLD_Bits.NMB_S_TAR_OLD */
+#define IFX_GTM_DPLL_NMB_S_TAR_OLD_NMB_S_TAR_OLD_LEN (20u)
+
+/** \brief Mask for Ifx_GTM_DPLL_NMB_S_TAR_OLD_Bits.NMB_S_TAR_OLD */
+#define IFX_GTM_DPLL_NMB_S_TAR_OLD_NMB_S_TAR_OLD_MSK (0xfffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_NMB_S_TAR_OLD_Bits.NMB_S_TAR_OLD */
+#define IFX_GTM_DPLL_NMB_S_TAR_OLD_NMB_S_TAR_OLD_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_NMB_T_Bits.NMB_T */
+#define IFX_GTM_DPLL_NMB_T_NMB_T_LEN (16u)
+
+/** \brief Mask for Ifx_GTM_DPLL_NMB_T_Bits.NMB_T */
+#define IFX_GTM_DPLL_NMB_T_NMB_T_MSK (0xffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_NMB_T_Bits.NMB_T */
+#define IFX_GTM_DPLL_NMB_T_NMB_T_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_NMB_T_TAR_Bits.NMB_T_TAR */
+#define IFX_GTM_DPLL_NMB_T_TAR_NMB_T_TAR_LEN (16u)
+
+/** \brief Mask for Ifx_GTM_DPLL_NMB_T_TAR_Bits.NMB_T_TAR */
+#define IFX_GTM_DPLL_NMB_T_TAR_NMB_T_TAR_MSK (0xffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_NMB_T_TAR_Bits.NMB_T_TAR */
+#define IFX_GTM_DPLL_NMB_T_TAR_NMB_T_TAR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_NMB_T_TAR_OLD_Bits.NMB_T_TAR_OLD */
+#define IFX_GTM_DPLL_NMB_T_TAR_OLD_NMB_T_TAR_OLD_LEN (16u)
+
+/** \brief Mask for Ifx_GTM_DPLL_NMB_T_TAR_OLD_Bits.NMB_T_TAR_OLD */
+#define IFX_GTM_DPLL_NMB_T_TAR_OLD_NMB_T_TAR_OLD_MSK (0xffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_NMB_T_TAR_OLD_Bits.NMB_T_TAR_OLD */
+#define IFX_GTM_DPLL_NMB_T_TAR_OLD_NMB_T_TAR_OLD_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_NTI_CNT_Bits.NTI_CNT */
+#define IFX_GTM_DPLL_NTI_CNT_NTI_CNT_LEN (10u)
+
+/** \brief Mask for Ifx_GTM_DPLL_NTI_CNT_Bits.NTI_CNT */
+#define IFX_GTM_DPLL_NTI_CNT_NTI_CNT_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_NTI_CNT_Bits.NTI_CNT */
+#define IFX_GTM_DPLL_NTI_CNT_NTI_CNT_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_NUSC_Bits.FSS */
+#define IFX_GTM_DPLL_NUSC_FSS_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_NUSC_Bits.FSS */
+#define IFX_GTM_DPLL_NUSC_FSS_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_NUSC_Bits.FSS */
+#define IFX_GTM_DPLL_NUSC_FSS_OFF (6u)
+
+/** \brief Length for Ifx_GTM_DPLL_NUSC_Bits.NUSE */
+#define IFX_GTM_DPLL_NUSC_NUSE_LEN (6u)
+
+/** \brief Mask for Ifx_GTM_DPLL_NUSC_Bits.NUSE */
+#define IFX_GTM_DPLL_NUSC_NUSE_MSK (0x3fu)
+
+/** \brief Offset for Ifx_GTM_DPLL_NUSC_Bits.NUSE */
+#define IFX_GTM_DPLL_NUSC_NUSE_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_NUSC_Bits.SYN_S */
+#define IFX_GTM_DPLL_NUSC_SYN_S_LEN (6u)
+
+/** \brief Mask for Ifx_GTM_DPLL_NUSC_Bits.SYN_S */
+#define IFX_GTM_DPLL_NUSC_SYN_S_MSK (0x3fu)
+
+/** \brief Offset for Ifx_GTM_DPLL_NUSC_Bits.SYN_S */
+#define IFX_GTM_DPLL_NUSC_SYN_S_OFF (7u)
+
+/** \brief Length for Ifx_GTM_DPLL_NUSC_Bits.SYN_S_OLD */
+#define IFX_GTM_DPLL_NUSC_SYN_S_OLD_LEN (6u)
+
+/** \brief Mask for Ifx_GTM_DPLL_NUSC_Bits.SYN_S_OLD */
+#define IFX_GTM_DPLL_NUSC_SYN_S_OLD_MSK (0x3fu)
+
+/** \brief Offset for Ifx_GTM_DPLL_NUSC_Bits.SYN_S_OLD */
+#define IFX_GTM_DPLL_NUSC_SYN_S_OLD_OFF (13u)
+
+/** \brief Length for Ifx_GTM_DPLL_NUSC_Bits.VSN */
+#define IFX_GTM_DPLL_NUSC_VSN_LEN (6u)
+
+/** \brief Mask for Ifx_GTM_DPLL_NUSC_Bits.VSN */
+#define IFX_GTM_DPLL_NUSC_VSN_MSK (0x3fu)
+
+/** \brief Offset for Ifx_GTM_DPLL_NUSC_Bits.VSN */
+#define IFX_GTM_DPLL_NUSC_VSN_OFF (19u)
+
+/** \brief Length for Ifx_GTM_DPLL_NUSC_Bits.WNUS */
+#define IFX_GTM_DPLL_NUSC_WNUS_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_NUSC_Bits.WNUS */
+#define IFX_GTM_DPLL_NUSC_WNUS_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_NUSC_Bits.WNUS */
+#define IFX_GTM_DPLL_NUSC_WNUS_OFF (29u)
+
+/** \brief Length for Ifx_GTM_DPLL_NUSC_Bits.WSYN */
+#define IFX_GTM_DPLL_NUSC_WSYN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_NUSC_Bits.WSYN */
+#define IFX_GTM_DPLL_NUSC_WSYN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_NUSC_Bits.WSYN */
+#define IFX_GTM_DPLL_NUSC_WSYN_OFF (30u)
+
+/** \brief Length for Ifx_GTM_DPLL_NUSC_Bits.WVSN */
+#define IFX_GTM_DPLL_NUSC_WVSN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_NUSC_Bits.WVSN */
+#define IFX_GTM_DPLL_NUSC_WVSN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_NUSC_Bits.WVSN */
+#define IFX_GTM_DPLL_NUSC_WVSN_OFF (31u)
+
+/** \brief Length for Ifx_GTM_DPLL_NUTC_Bits.FST */
+#define IFX_GTM_DPLL_NUTC_FST_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_NUTC_Bits.FST */
+#define IFX_GTM_DPLL_NUTC_FST_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_NUTC_Bits.FST */
+#define IFX_GTM_DPLL_NUTC_FST_OFF (10u)
+
+/** \brief Length for Ifx_GTM_DPLL_NUTC_Bits.NUTE */
+#define IFX_GTM_DPLL_NUTC_NUTE_LEN (10u)
+
+/** \brief Mask for Ifx_GTM_DPLL_NUTC_Bits.NUTE */
+#define IFX_GTM_DPLL_NUTC_NUTE_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_NUTC_Bits.NUTE */
+#define IFX_GTM_DPLL_NUTC_NUTE_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_NUTC_Bits.SYN_T */
+#define IFX_GTM_DPLL_NUTC_SYN_T_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_DPLL_NUTC_Bits.SYN_T */
+#define IFX_GTM_DPLL_NUTC_SYN_T_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_DPLL_NUTC_Bits.SYN_T */
+#define IFX_GTM_DPLL_NUTC_SYN_T_OFF (13u)
+
+/** \brief Length for Ifx_GTM_DPLL_NUTC_Bits.SYN_T_OLD */
+#define IFX_GTM_DPLL_NUTC_SYN_T_OLD_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_DPLL_NUTC_Bits.SYN_T_OLD */
+#define IFX_GTM_DPLL_NUTC_SYN_T_OLD_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_DPLL_NUTC_Bits.SYN_T_OLD */
+#define IFX_GTM_DPLL_NUTC_SYN_T_OLD_OFF (16u)
+
+/** \brief Length for Ifx_GTM_DPLL_NUTC_Bits.VTN */
+#define IFX_GTM_DPLL_NUTC_VTN_LEN (6u)
+
+/** \brief Mask for Ifx_GTM_DPLL_NUTC_Bits.VTN */
+#define IFX_GTM_DPLL_NUTC_VTN_MSK (0x3fu)
+
+/** \brief Offset for Ifx_GTM_DPLL_NUTC_Bits.VTN */
+#define IFX_GTM_DPLL_NUTC_VTN_OFF (19u)
+
+/** \brief Length for Ifx_GTM_DPLL_NUTC_Bits.WNUT */
+#define IFX_GTM_DPLL_NUTC_WNUT_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_NUTC_Bits.WNUT */
+#define IFX_GTM_DPLL_NUTC_WNUT_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_NUTC_Bits.WNUT */
+#define IFX_GTM_DPLL_NUTC_WNUT_OFF (29u)
+
+/** \brief Length for Ifx_GTM_DPLL_NUTC_Bits.WSYN */
+#define IFX_GTM_DPLL_NUTC_WSYN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_NUTC_Bits.WSYN */
+#define IFX_GTM_DPLL_NUTC_WSYN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_NUTC_Bits.WSYN */
+#define IFX_GTM_DPLL_NUTC_WSYN_OFF (30u)
+
+/** \brief Length for Ifx_GTM_DPLL_NUTC_Bits.WVTN */
+#define IFX_GTM_DPLL_NUTC_WVTN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_NUTC_Bits.WVTN */
+#define IFX_GTM_DPLL_NUTC_WVTN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_NUTC_Bits.WVTN */
+#define IFX_GTM_DPLL_NUTC_WVTN_OFF (31u)
+
+/** \brief Length for Ifx_GTM_DPLL_OSW_Bits.OSS */
+#define IFX_GTM_DPLL_OSW_OSS_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_DPLL_OSW_Bits.OSS */
+#define IFX_GTM_DPLL_OSW_OSS_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_DPLL_OSW_Bits.OSS */
+#define IFX_GTM_DPLL_OSW_OSS_OFF (8u)
+
+/** \brief Length for Ifx_GTM_DPLL_OSW_Bits.SWON_S */
+#define IFX_GTM_DPLL_OSW_SWON_S_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_OSW_Bits.SWON_S */
+#define IFX_GTM_DPLL_OSW_SWON_S_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_OSW_Bits.SWON_S */
+#define IFX_GTM_DPLL_OSW_SWON_S_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_OSW_Bits.SWON_T */
+#define IFX_GTM_DPLL_OSW_SWON_T_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_OSW_Bits.SWON_T */
+#define IFX_GTM_DPLL_OSW_SWON_T_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_OSW_Bits.SWON_T */
+#define IFX_GTM_DPLL_OSW_SWON_T_OFF (1u)
+
+/** \brief Length for Ifx_GTM_DPLL_PDT_T_Bits.DB */
+#define IFX_GTM_DPLL_PDT_T_DB_LEN (14u)
+
+/** \brief Mask for Ifx_GTM_DPLL_PDT_T_Bits.DB */
+#define IFX_GTM_DPLL_PDT_T_DB_MSK (0x3fffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_PDT_T_Bits.DB */
+#define IFX_GTM_DPLL_PDT_T_DB_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_PDT_T_Bits.DW */
+#define IFX_GTM_DPLL_PDT_T_DW_LEN (10u)
+
+/** \brief Mask for Ifx_GTM_DPLL_PDT_T_Bits.DW */
+#define IFX_GTM_DPLL_PDT_T_DW_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_PDT_T_Bits.DW */
+#define IFX_GTM_DPLL_PDT_T_DW_OFF (14u)
+
+/** \brief Length for Ifx_GTM_DPLL_PSA_Bits.PSA */
+#define IFX_GTM_DPLL_PSA_PSA_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_PSA_Bits.PSA */
+#define IFX_GTM_DPLL_PSA_PSA_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_PSA_Bits.PSA */
+#define IFX_GTM_DPLL_PSA_PSA_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_PSAC_Bits.PSAC */
+#define IFX_GTM_DPLL_PSAC_PSAC_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_PSAC_Bits.PSAC */
+#define IFX_GTM_DPLL_PSAC_PSAC_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_PSAC_Bits.PSAC */
+#define IFX_GTM_DPLL_PSAC_PSAC_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_PSSC_Bits.PSSC */
+#define IFX_GTM_DPLL_PSSC_PSSC_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_PSSC_Bits.PSSC */
+#define IFX_GTM_DPLL_PSSC_PSSC_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_PSSC_Bits.PSSC */
+#define IFX_GTM_DPLL_PSSC_PSSC_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_PSSM_0_Bits.PSSM */
+#define IFX_GTM_DPLL_PSSM_0_PSSM_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_PSSM_0_Bits.PSSM */
+#define IFX_GTM_DPLL_PSSM_0_PSSM_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_PSSM_0_Bits.PSSM */
+#define IFX_GTM_DPLL_PSSM_0_PSSM_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_PSSM_1_Bits.PSSM */
+#define IFX_GTM_DPLL_PSSM_1_PSSM_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_PSSM_1_Bits.PSSM */
+#define IFX_GTM_DPLL_PSSM_1_PSSM_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_PSSM_1_Bits.PSSM */
+#define IFX_GTM_DPLL_PSSM_1_PSSM_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_PSTC_Bits.PSTC */
+#define IFX_GTM_DPLL_PSTC_PSTC_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_PSTC_Bits.PSTC */
+#define IFX_GTM_DPLL_PSTC_PSTC_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_PSTC_Bits.PSTC */
+#define IFX_GTM_DPLL_PSTC_PSTC_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_PSTM_0_Bits.PSTM */
+#define IFX_GTM_DPLL_PSTM_0_PSTM_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_PSTM_0_Bits.PSTM */
+#define IFX_GTM_DPLL_PSTM_0_PSTM_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_PSTM_0_Bits.PSTM */
+#define IFX_GTM_DPLL_PSTM_0_PSTM_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_PSTM_1_Bits.PSTM */
+#define IFX_GTM_DPLL_PSTM_1_PSTM_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_PSTM_1_Bits.PSTM */
+#define IFX_GTM_DPLL_PSTM_1_PSTM_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_PSTM_1_Bits.PSTM */
+#define IFX_GTM_DPLL_PSTM_1_PSTM_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_PVT_Bits.PVT */
+#define IFX_GTM_DPLL_PVT_PVT_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_PVT_Bits.PVT */
+#define IFX_GTM_DPLL_PVT_PVT_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_PVT_Bits.PVT */
+#define IFX_GTM_DPLL_PVT_PVT_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_RAM_INI_Bits.INIT_1A */
+#define IFX_GTM_DPLL_RAM_INI_INIT_1A_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_RAM_INI_Bits.INIT_1A */
+#define IFX_GTM_DPLL_RAM_INI_INIT_1A_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_RAM_INI_Bits.INIT_1A */
+#define IFX_GTM_DPLL_RAM_INI_INIT_1A_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_RAM_INI_Bits.INIT_1B */
+#define IFX_GTM_DPLL_RAM_INI_INIT_1B_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_RAM_INI_Bits.INIT_1B */
+#define IFX_GTM_DPLL_RAM_INI_INIT_1B_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_RAM_INI_Bits.INIT_1B */
+#define IFX_GTM_DPLL_RAM_INI_INIT_1B_OFF (1u)
+
+/** \brief Length for Ifx_GTM_DPLL_RAM_INI_Bits.INIT_2 */
+#define IFX_GTM_DPLL_RAM_INI_INIT_2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_RAM_INI_Bits.INIT_2 */
+#define IFX_GTM_DPLL_RAM_INI_INIT_2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_RAM_INI_Bits.INIT_2 */
+#define IFX_GTM_DPLL_RAM_INI_INIT_2_OFF (2u)
+
+/** \brief Length for Ifx_GTM_DPLL_RAM_INI_Bits.INIT_RAM */
+#define IFX_GTM_DPLL_RAM_INI_INIT_RAM_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_RAM_INI_Bits.INIT_RAM */
+#define IFX_GTM_DPLL_RAM_INI_INIT_RAM_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_RAM_INI_Bits.INIT_RAM */
+#define IFX_GTM_DPLL_RAM_INI_INIT_RAM_OFF (4u)
+
+/** \brief Length for Ifx_GTM_DPLL_RCDT_SX_NOM_Bits.RCDT_SX_NOM */
+#define IFX_GTM_DPLL_RCDT_SX_NOM_RCDT_SX_NOM_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_RCDT_SX_NOM_Bits.RCDT_SX_NOM */
+#define IFX_GTM_DPLL_RCDT_SX_NOM_RCDT_SX_NOM_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_RCDT_SX_NOM_Bits.RCDT_SX_NOM */
+#define IFX_GTM_DPLL_RCDT_SX_NOM_RCDT_SX_NOM_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_RCDT_SX_Bits.RCDT_SX */
+#define IFX_GTM_DPLL_RCDT_SX_RCDT_SX_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_RCDT_SX_Bits.RCDT_SX */
+#define IFX_GTM_DPLL_RCDT_SX_RCDT_SX_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_RCDT_SX_Bits.RCDT_SX */
+#define IFX_GTM_DPLL_RCDT_SX_RCDT_SX_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_RCDT_TX_NOM_Bits.RCDT_TX_NOM */
+#define IFX_GTM_DPLL_RCDT_TX_NOM_RCDT_TX_NOM_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_RCDT_TX_NOM_Bits.RCDT_TX_NOM */
+#define IFX_GTM_DPLL_RCDT_TX_NOM_RCDT_TX_NOM_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_RCDT_TX_NOM_Bits.RCDT_TX_NOM */
+#define IFX_GTM_DPLL_RCDT_TX_NOM_RCDT_TX_NOM_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_RCDT_TX_Bits.RCDT_TX */
+#define IFX_GTM_DPLL_RCDT_TX_RCDT_TX_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_RCDT_TX_Bits.RCDT_TX */
+#define IFX_GTM_DPLL_RCDT_TX_RCDT_TX_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_RCDT_TX_Bits.RCDT_TX */
+#define IFX_GTM_DPLL_RCDT_TX_RCDT_TX_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_RDT_S_ACT_Bits.RDT_S_ACT */
+#define IFX_GTM_DPLL_RDT_S_ACT_RDT_S_ACT_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_RDT_S_ACT_Bits.RDT_S_ACT */
+#define IFX_GTM_DPLL_RDT_S_ACT_RDT_S_ACT_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_RDT_S_ACT_Bits.RDT_S_ACT */
+#define IFX_GTM_DPLL_RDT_S_ACT_RDT_S_ACT_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_RDT_S_Bits.RDT_S */
+#define IFX_GTM_DPLL_RDT_S_RDT_S_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_RDT_S_Bits.RDT_S */
+#define IFX_GTM_DPLL_RDT_S_RDT_S_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_RDT_S_Bits.RDT_S */
+#define IFX_GTM_DPLL_RDT_S_RDT_S_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_RDT_T_ACT_Bits.RDT_T_ACT */
+#define IFX_GTM_DPLL_RDT_T_ACT_RDT_T_ACT_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_RDT_T_ACT_Bits.RDT_T_ACT */
+#define IFX_GTM_DPLL_RDT_T_ACT_RDT_T_ACT_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_RDT_T_ACT_Bits.RDT_T_ACT */
+#define IFX_GTM_DPLL_RDT_T_ACT_RDT_T_ACT_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_SLR_Bits.SLR */
+#define IFX_GTM_DPLL_SLR_SLR_LEN (8u)
+
+/** \brief Mask for Ifx_GTM_DPLL_SLR_Bits.SLR */
+#define IFX_GTM_DPLL_SLR_SLR_MSK (0xffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_SLR_Bits.SLR */
+#define IFX_GTM_DPLL_SLR_SLR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_STATUS_Bits.BWD1 */
+#define IFX_GTM_DPLL_STATUS_BWD1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_STATUS_Bits.BWD1 */
+#define IFX_GTM_DPLL_STATUS_BWD1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_STATUS_Bits.BWD1 */
+#define IFX_GTM_DPLL_STATUS_BWD1_OFF (23u)
+
+/** \brief Length for Ifx_GTM_DPLL_STATUS_Bits.BWD2 */
+#define IFX_GTM_DPLL_STATUS_BWD2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_STATUS_Bits.BWD2 */
+#define IFX_GTM_DPLL_STATUS_BWD2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_STATUS_Bits.BWD2 */
+#define IFX_GTM_DPLL_STATUS_BWD2_OFF (22u)
+
+/** \brief Length for Ifx_GTM_DPLL_STATUS_Bits.CAIP1 */
+#define IFX_GTM_DPLL_STATUS_CAIP1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_STATUS_Bits.CAIP1 */
+#define IFX_GTM_DPLL_STATUS_CAIP1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_STATUS_Bits.CAIP1 */
+#define IFX_GTM_DPLL_STATUS_CAIP1_OFF (19u)
+
+/** \brief Length for Ifx_GTM_DPLL_STATUS_Bits.CAIP2 */
+#define IFX_GTM_DPLL_STATUS_CAIP2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_STATUS_Bits.CAIP2 */
+#define IFX_GTM_DPLL_STATUS_CAIP2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_STATUS_Bits.CAIP2 */
+#define IFX_GTM_DPLL_STATUS_CAIP2_OFF (18u)
+
+/** \brief Length for Ifx_GTM_DPLL_STATUS_Bits.CRO */
+#define IFX_GTM_DPLL_STATUS_CRO_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_STATUS_Bits.CRO */
+#define IFX_GTM_DPLL_STATUS_CRO_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_STATUS_Bits.CRO */
+#define IFX_GTM_DPLL_STATUS_CRO_OFF (4u)
+
+/** \brief Length for Ifx_GTM_DPLL_STATUS_Bits.CSO */
+#define IFX_GTM_DPLL_STATUS_CSO_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_STATUS_Bits.CSO */
+#define IFX_GTM_DPLL_STATUS_CSO_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_STATUS_Bits.CSO */
+#define IFX_GTM_DPLL_STATUS_CSO_OFF (1u)
+
+/** \brief Length for Ifx_GTM_DPLL_STATUS_Bits.CSVS */
+#define IFX_GTM_DPLL_STATUS_CSVS_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_STATUS_Bits.CSVS */
+#define IFX_GTM_DPLL_STATUS_CSVS_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_STATUS_Bits.CSVS */
+#define IFX_GTM_DPLL_STATUS_CSVS_OFF (16u)
+
+/** \brief Length for Ifx_GTM_DPLL_STATUS_Bits.CSVT */
+#define IFX_GTM_DPLL_STATUS_CSVT_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_STATUS_Bits.CSVT */
+#define IFX_GTM_DPLL_STATUS_CSVT_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_STATUS_Bits.CSVT */
+#define IFX_GTM_DPLL_STATUS_CSVT_OFF (17u)
+
+/** \brief Length for Ifx_GTM_DPLL_STATUS_Bits.CTO */
+#define IFX_GTM_DPLL_STATUS_CTO_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_STATUS_Bits.CTO */
+#define IFX_GTM_DPLL_STATUS_CTO_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_STATUS_Bits.CTO */
+#define IFX_GTM_DPLL_STATUS_CTO_OFF (3u)
+
+/** \brief Length for Ifx_GTM_DPLL_STATUS_Bits.ERR */
+#define IFX_GTM_DPLL_STATUS_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_STATUS_Bits.ERR */
+#define IFX_GTM_DPLL_STATUS_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_STATUS_Bits.ERR */
+#define IFX_GTM_DPLL_STATUS_ERR_OFF (31u)
+
+/** \brief Length for Ifx_GTM_DPLL_STATUS_Bits.FSD */
+#define IFX_GTM_DPLL_STATUS_FSD_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_STATUS_Bits.FSD */
+#define IFX_GTM_DPLL_STATUS_FSD_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_STATUS_Bits.FSD */
+#define IFX_GTM_DPLL_STATUS_FSD_OFF (28u)
+
+/** \brief Length for Ifx_GTM_DPLL_STATUS_Bits.FTD */
+#define IFX_GTM_DPLL_STATUS_FTD_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_STATUS_Bits.FTD */
+#define IFX_GTM_DPLL_STATUS_FTD_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_STATUS_Bits.FTD */
+#define IFX_GTM_DPLL_STATUS_FTD_OFF (29u)
+
+/** \brief Length for Ifx_GTM_DPLL_STATUS_Bits.ISN */
+#define IFX_GTM_DPLL_STATUS_ISN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_STATUS_Bits.ISN */
+#define IFX_GTM_DPLL_STATUS_ISN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_STATUS_Bits.ISN */
+#define IFX_GTM_DPLL_STATUS_ISN_OFF (20u)
+
+/** \brief Length for Ifx_GTM_DPLL_STATUS_Bits.ITN */
+#define IFX_GTM_DPLL_STATUS_ITN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_STATUS_Bits.ITN */
+#define IFX_GTM_DPLL_STATUS_ITN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_STATUS_Bits.ITN */
+#define IFX_GTM_DPLL_STATUS_ITN_OFF (21u)
+
+/** \brief Length for Ifx_GTM_DPLL_STATUS_Bits.LOCK1 */
+#define IFX_GTM_DPLL_STATUS_LOCK1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_STATUS_Bits.LOCK1 */
+#define IFX_GTM_DPLL_STATUS_LOCK1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_STATUS_Bits.LOCK1 */
+#define IFX_GTM_DPLL_STATUS_LOCK1_OFF (30u)
+
+/** \brief Length for Ifx_GTM_DPLL_STATUS_Bits.LOCK2 */
+#define IFX_GTM_DPLL_STATUS_LOCK2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_STATUS_Bits.LOCK2 */
+#define IFX_GTM_DPLL_STATUS_LOCK2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_STATUS_Bits.LOCK2 */
+#define IFX_GTM_DPLL_STATUS_LOCK2_OFF (25u)
+
+/** \brief Length for Ifx_GTM_DPLL_STATUS_Bits.LOW_RES */
+#define IFX_GTM_DPLL_STATUS_LOW_RES_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_STATUS_Bits.LOW_RES */
+#define IFX_GTM_DPLL_STATUS_LOW_RES_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_STATUS_Bits.LOW_RES */
+#define IFX_GTM_DPLL_STATUS_LOW_RES_OFF (15u)
+
+/** \brief Length for Ifx_GTM_DPLL_STATUS_Bits.MS */
+#define IFX_GTM_DPLL_STATUS_MS_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_STATUS_Bits.MS */
+#define IFX_GTM_DPLL_STATUS_MS_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_STATUS_Bits.MS */
+#define IFX_GTM_DPLL_STATUS_MS_OFF (9u)
+
+/** \brief Length for Ifx_GTM_DPLL_STATUS_Bits.MT */
+#define IFX_GTM_DPLL_STATUS_MT_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_STATUS_Bits.MT */
+#define IFX_GTM_DPLL_STATUS_MT_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_STATUS_Bits.MT */
+#define IFX_GTM_DPLL_STATUS_MT_OFF (11u)
+
+/** \brief Length for Ifx_GTM_DPLL_STATUS_Bits.PSE */
+#define IFX_GTM_DPLL_STATUS_PSE_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_STATUS_Bits.PSE */
+#define IFX_GTM_DPLL_STATUS_PSE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_STATUS_Bits.PSE */
+#define IFX_GTM_DPLL_STATUS_PSE_OFF (7u)
+
+/** \brief Length for Ifx_GTM_DPLL_STATUS_Bits.RAM2_ERR */
+#define IFX_GTM_DPLL_STATUS_RAM2_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_STATUS_Bits.RAM2_ERR */
+#define IFX_GTM_DPLL_STATUS_RAM2_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_STATUS_Bits.RAM2_ERR */
+#define IFX_GTM_DPLL_STATUS_RAM2_ERR_OFF (12u)
+
+/** \brief Length for Ifx_GTM_DPLL_STATUS_Bits.RCS */
+#define IFX_GTM_DPLL_STATUS_RCS_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_STATUS_Bits.RCS */
+#define IFX_GTM_DPLL_STATUS_RCS_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_STATUS_Bits.RCS */
+#define IFX_GTM_DPLL_STATUS_RCS_OFF (5u)
+
+/** \brief Length for Ifx_GTM_DPLL_STATUS_Bits.RCT */
+#define IFX_GTM_DPLL_STATUS_RCT_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_STATUS_Bits.RCT */
+#define IFX_GTM_DPLL_STATUS_RCT_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_STATUS_Bits.RCT */
+#define IFX_GTM_DPLL_STATUS_RCT_OFF (6u)
+
+/** \brief Length for Ifx_GTM_DPLL_STATUS_Bits.SOR */
+#define IFX_GTM_DPLL_STATUS_SOR_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_STATUS_Bits.SOR */
+#define IFX_GTM_DPLL_STATUS_SOR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_STATUS_Bits.SOR */
+#define IFX_GTM_DPLL_STATUS_SOR_OFF (8u)
+
+/** \brief Length for Ifx_GTM_DPLL_STATUS_Bits.SYS */
+#define IFX_GTM_DPLL_STATUS_SYS_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_STATUS_Bits.SYS */
+#define IFX_GTM_DPLL_STATUS_SYS_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_STATUS_Bits.SYS */
+#define IFX_GTM_DPLL_STATUS_SYS_OFF (26u)
+
+/** \brief Length for Ifx_GTM_DPLL_STATUS_Bits.SYT */
+#define IFX_GTM_DPLL_STATUS_SYT_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_STATUS_Bits.SYT */
+#define IFX_GTM_DPLL_STATUS_SYT_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_STATUS_Bits.SYT */
+#define IFX_GTM_DPLL_STATUS_SYT_OFF (27u)
+
+/** \brief Length for Ifx_GTM_DPLL_STATUS_Bits.TOR */
+#define IFX_GTM_DPLL_STATUS_TOR_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DPLL_STATUS_Bits.TOR */
+#define IFX_GTM_DPLL_STATUS_TOR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DPLL_STATUS_Bits.TOR */
+#define IFX_GTM_DPLL_STATUS_TOR_OFF (10u)
+
+/** \brief Length for Ifx_GTM_DPLL_TBU_TS0_S_Bits.TBU_TS0_S */
+#define IFX_GTM_DPLL_TBU_TS0_S_TBU_TS0_S_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_TBU_TS0_S_Bits.TBU_TS0_S */
+#define IFX_GTM_DPLL_TBU_TS0_S_TBU_TS0_S_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_TBU_TS0_S_Bits.TBU_TS0_S */
+#define IFX_GTM_DPLL_TBU_TS0_S_TBU_TS0_S_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_TBU_TS0_T_Bits.TBU_TS0_T */
+#define IFX_GTM_DPLL_TBU_TS0_T_TBU_TS0_T_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_TBU_TS0_T_Bits.TBU_TS0_T */
+#define IFX_GTM_DPLL_TBU_TS0_T_TBU_TS0_T_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_TBU_TS0_T_Bits.TBU_TS0_T */
+#define IFX_GTM_DPLL_TBU_TS0_T_TBU_TS0_T_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_THMA_Bits.THMA */
+#define IFX_GTM_DPLL_THMA_THMA_LEN (16u)
+
+/** \brief Mask for Ifx_GTM_DPLL_THMA_Bits.THMA */
+#define IFX_GTM_DPLL_THMA_THMA_MSK (0xffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_THMA_Bits.THMA */
+#define IFX_GTM_DPLL_THMA_THMA_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_THMI_Bits.THMI */
+#define IFX_GTM_DPLL_THMI_THMI_LEN (16u)
+
+/** \brief Mask for Ifx_GTM_DPLL_THMI_Bits.THMI */
+#define IFX_GTM_DPLL_THMI_THMI_MSK (0xffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_THMI_Bits.THMI */
+#define IFX_GTM_DPLL_THMI_THMI_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_THVAL_Bits.THVAL */
+#define IFX_GTM_DPLL_THVAL_THVAL_LEN (16u)
+
+/** \brief Mask for Ifx_GTM_DPLL_THVAL_Bits.THVAL */
+#define IFX_GTM_DPLL_THVAL_THVAL_MSK (0xffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_THVAL_Bits.THVAL */
+#define IFX_GTM_DPLL_THVAL_THVAL_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_TLR_Bits.TLR */
+#define IFX_GTM_DPLL_TLR_TLR_LEN (8u)
+
+/** \brief Mask for Ifx_GTM_DPLL_TLR_Bits.TLR */
+#define IFX_GTM_DPLL_TLR_TLR_MSK (0xffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_TLR_Bits.TLR */
+#define IFX_GTM_DPLL_TLR_TLR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_TOV_Bits.DB */
+#define IFX_GTM_DPLL_TOV_DB_LEN (10u)
+
+/** \brief Mask for Ifx_GTM_DPLL_TOV_Bits.DB */
+#define IFX_GTM_DPLL_TOV_DB_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_TOV_Bits.DB */
+#define IFX_GTM_DPLL_TOV_DB_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_TOV_Bits.DW */
+#define IFX_GTM_DPLL_TOV_DW_LEN (6u)
+
+/** \brief Mask for Ifx_GTM_DPLL_TOV_Bits.DW */
+#define IFX_GTM_DPLL_TOV_DW_MSK (0x3fu)
+
+/** \brief Offset for Ifx_GTM_DPLL_TOV_Bits.DW */
+#define IFX_GTM_DPLL_TOV_DW_OFF (10u)
+
+/** \brief Length for Ifx_GTM_DPLL_TOV_S_Bits.DB */
+#define IFX_GTM_DPLL_TOV_S_DB_LEN (10u)
+
+/** \brief Mask for Ifx_GTM_DPLL_TOV_S_Bits.DB */
+#define IFX_GTM_DPLL_TOV_S_DB_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_TOV_S_Bits.DB */
+#define IFX_GTM_DPLL_TOV_S_DB_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_TOV_S_Bits.DW */
+#define IFX_GTM_DPLL_TOV_S_DW_LEN (6u)
+
+/** \brief Mask for Ifx_GTM_DPLL_TOV_S_Bits.DW */
+#define IFX_GTM_DPLL_TOV_S_DW_MSK (0x3fu)
+
+/** \brief Offset for Ifx_GTM_DPLL_TOV_S_Bits.DW */
+#define IFX_GTM_DPLL_TOV_S_DW_OFF (10u)
+
+/** \brief Length for Ifx_GTM_DPLL_TS_S_0_Bits.STATE_TS */
+#define IFX_GTM_DPLL_TS_S_0_STATE_TS_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_TS_S_0_Bits.STATE_TS */
+#define IFX_GTM_DPLL_TS_S_0_STATE_TS_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_TS_S_0_Bits.STATE_TS */
+#define IFX_GTM_DPLL_TS_S_0_STATE_TS_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_TS_S_1_Bits.STATE_TS */
+#define IFX_GTM_DPLL_TS_S_1_STATE_TS_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_TS_S_1_Bits.STATE_TS */
+#define IFX_GTM_DPLL_TS_S_1_STATE_TS_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_TS_S_1_Bits.STATE_TS */
+#define IFX_GTM_DPLL_TS_S_1_STATE_TS_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_TS_T_0_Bits.TRIGGER_TS */
+#define IFX_GTM_DPLL_TS_T_0_TRIGGER_TS_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_TS_T_0_Bits.TRIGGER_TS */
+#define IFX_GTM_DPLL_TS_T_0_TRIGGER_TS_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_TS_T_0_Bits.TRIGGER_TS */
+#define IFX_GTM_DPLL_TS_T_0_TRIGGER_TS_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_TS_T_1_Bits.TRIGGER_TS */
+#define IFX_GTM_DPLL_TS_T_1_TRIGGER_TS_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_TS_T_1_Bits.TRIGGER_TS */
+#define IFX_GTM_DPLL_TS_T_1_TRIGGER_TS_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_TS_T_1_Bits.TRIGGER_TS */
+#define IFX_GTM_DPLL_TS_T_1_TRIGGER_TS_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_TSAC_Bits.TSAC */
+#define IFX_GTM_DPLL_TSAC_TSAC_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_TSAC_Bits.TSAC */
+#define IFX_GTM_DPLL_TSAC_TSAC_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_TSAC_Bits.TSAC */
+#define IFX_GTM_DPLL_TSAC_TSAC_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DPLL_TSF_S_Bits.TSF_S */
+#define IFX_GTM_DPLL_TSF_S_TSF_S_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_DPLL_TSF_S_Bits.TSF_S */
+#define IFX_GTM_DPLL_TSF_S_TSF_S_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_DPLL_TSF_S_Bits.TSF_S */
+#define IFX_GTM_DPLL_TSF_S_TSF_S_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DXINCON_Bits.DSS00 */
+#define IFX_GTM_DXINCON_DSS00_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DXINCON_Bits.DSS00 */
+#define IFX_GTM_DXINCON_DSS00_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DXINCON_Bits.DSS00 */
+#define IFX_GTM_DXINCON_DSS00_OFF (16u)
+
+/** \brief Length for Ifx_GTM_DXINCON_Bits.DSS01 */
+#define IFX_GTM_DXINCON_DSS01_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DXINCON_Bits.DSS01 */
+#define IFX_GTM_DXINCON_DSS01_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DXINCON_Bits.DSS01 */
+#define IFX_GTM_DXINCON_DSS01_OFF (17u)
+
+/** \brief Length for Ifx_GTM_DXINCON_Bits.DSS02 */
+#define IFX_GTM_DXINCON_DSS02_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DXINCON_Bits.DSS02 */
+#define IFX_GTM_DXINCON_DSS02_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DXINCON_Bits.DSS02 */
+#define IFX_GTM_DXINCON_DSS02_OFF (18u)
+
+/** \brief Length for Ifx_GTM_DXINCON_Bits.DSS10 */
+#define IFX_GTM_DXINCON_DSS10_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DXINCON_Bits.DSS10 */
+#define IFX_GTM_DXINCON_DSS10_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DXINCON_Bits.DSS10 */
+#define IFX_GTM_DXINCON_DSS10_OFF (24u)
+
+/** \brief Length for Ifx_GTM_DXINCON_Bits.DSS11 */
+#define IFX_GTM_DXINCON_DSS11_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DXINCON_Bits.DSS11 */
+#define IFX_GTM_DXINCON_DSS11_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DXINCON_Bits.DSS11 */
+#define IFX_GTM_DXINCON_DSS11_OFF (25u)
+
+/** \brief Length for Ifx_GTM_DXINCON_Bits.DSS12 */
+#define IFX_GTM_DXINCON_DSS12_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DXINCON_Bits.DSS12 */
+#define IFX_GTM_DXINCON_DSS12_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DXINCON_Bits.DSS12 */
+#define IFX_GTM_DXINCON_DSS12_OFF (26u)
+
+/** \brief Length for Ifx_GTM_DXINCON_Bits.IN00 */
+#define IFX_GTM_DXINCON_IN00_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DXINCON_Bits.IN00 */
+#define IFX_GTM_DXINCON_IN00_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DXINCON_Bits.IN00 */
+#define IFX_GTM_DXINCON_IN00_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DXINCON_Bits.IN01 */
+#define IFX_GTM_DXINCON_IN01_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DXINCON_Bits.IN01 */
+#define IFX_GTM_DXINCON_IN01_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DXINCON_Bits.IN01 */
+#define IFX_GTM_DXINCON_IN01_OFF (1u)
+
+/** \brief Length for Ifx_GTM_DXINCON_Bits.IN02 */
+#define IFX_GTM_DXINCON_IN02_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DXINCON_Bits.IN02 */
+#define IFX_GTM_DXINCON_IN02_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DXINCON_Bits.IN02 */
+#define IFX_GTM_DXINCON_IN02_OFF (2u)
+
+/** \brief Length for Ifx_GTM_DXINCON_Bits.IN10 */
+#define IFX_GTM_DXINCON_IN10_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DXINCON_Bits.IN10 */
+#define IFX_GTM_DXINCON_IN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DXINCON_Bits.IN10 */
+#define IFX_GTM_DXINCON_IN10_OFF (8u)
+
+/** \brief Length for Ifx_GTM_DXINCON_Bits.IN11 */
+#define IFX_GTM_DXINCON_IN11_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DXINCON_Bits.IN11 */
+#define IFX_GTM_DXINCON_IN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DXINCON_Bits.IN11 */
+#define IFX_GTM_DXINCON_IN11_OFF (9u)
+
+/** \brief Length for Ifx_GTM_DXINCON_Bits.IN12 */
+#define IFX_GTM_DXINCON_IN12_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DXINCON_Bits.IN12 */
+#define IFX_GTM_DXINCON_IN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DXINCON_Bits.IN12 */
+#define IFX_GTM_DXINCON_IN12_OFF (10u)
+
+/** \brief Length for Ifx_GTM_DXOUTCON_Bits.OUT00 */
+#define IFX_GTM_DXOUTCON_OUT00_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DXOUTCON_Bits.OUT00 */
+#define IFX_GTM_DXOUTCON_OUT00_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DXOUTCON_Bits.OUT00 */
+#define IFX_GTM_DXOUTCON_OUT00_OFF (0u)
+
+/** \brief Length for Ifx_GTM_DXOUTCON_Bits.OUT01 */
+#define IFX_GTM_DXOUTCON_OUT01_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DXOUTCON_Bits.OUT01 */
+#define IFX_GTM_DXOUTCON_OUT01_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DXOUTCON_Bits.OUT01 */
+#define IFX_GTM_DXOUTCON_OUT01_OFF (1u)
+
+/** \brief Length for Ifx_GTM_DXOUTCON_Bits.OUT02 */
+#define IFX_GTM_DXOUTCON_OUT02_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DXOUTCON_Bits.OUT02 */
+#define IFX_GTM_DXOUTCON_OUT02_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DXOUTCON_Bits.OUT02 */
+#define IFX_GTM_DXOUTCON_OUT02_OFF (2u)
+
+/** \brief Length for Ifx_GTM_DXOUTCON_Bits.OUT10 */
+#define IFX_GTM_DXOUTCON_OUT10_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DXOUTCON_Bits.OUT10 */
+#define IFX_GTM_DXOUTCON_OUT10_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DXOUTCON_Bits.OUT10 */
+#define IFX_GTM_DXOUTCON_OUT10_OFF (8u)
+
+/** \brief Length for Ifx_GTM_DXOUTCON_Bits.OUT11 */
+#define IFX_GTM_DXOUTCON_OUT11_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DXOUTCON_Bits.OUT11 */
+#define IFX_GTM_DXOUTCON_OUT11_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DXOUTCON_Bits.OUT11 */
+#define IFX_GTM_DXOUTCON_OUT11_OFF (9u)
+
+/** \brief Length for Ifx_GTM_DXOUTCON_Bits.OUT12 */
+#define IFX_GTM_DXOUTCON_OUT12_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_DXOUTCON_Bits.OUT12 */
+#define IFX_GTM_DXOUTCON_OUT12_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_DXOUTCON_Bits.OUT12 */
+#define IFX_GTM_DXOUTCON_OUT12_OFF (10u)
+
+/** \brief Length for Ifx_GTM_EIRQ_EN_Bits.AEI_IM_ADDR_EIRQ_EN */
+#define IFX_GTM_EIRQ_EN_AEI_IM_ADDR_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_EIRQ_EN_Bits.AEI_IM_ADDR_EIRQ_EN */
+#define IFX_GTM_EIRQ_EN_AEI_IM_ADDR_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_EIRQ_EN_Bits.AEI_IM_ADDR_EIRQ_EN */
+#define IFX_GTM_EIRQ_EN_AEI_IM_ADDR_EIRQ_EN_OFF (2u)
+
+/** \brief Length for Ifx_GTM_EIRQ_EN_Bits.AEI_TO_XPT_EIRQ_EN */
+#define IFX_GTM_EIRQ_EN_AEI_TO_XPT_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_EIRQ_EN_Bits.AEI_TO_XPT_EIRQ_EN */
+#define IFX_GTM_EIRQ_EN_AEI_TO_XPT_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_EIRQ_EN_Bits.AEI_TO_XPT_EIRQ_EN */
+#define IFX_GTM_EIRQ_EN_AEI_TO_XPT_EIRQ_EN_OFF (0u)
+
+/** \brief Length for Ifx_GTM_EIRQ_EN_Bits.AEI_USP_ADDR_EIRQ_EN */
+#define IFX_GTM_EIRQ_EN_AEI_USP_ADDR_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_EIRQ_EN_Bits.AEI_USP_ADDR_EIRQ_EN */
+#define IFX_GTM_EIRQ_EN_AEI_USP_ADDR_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_EIRQ_EN_Bits.AEI_USP_ADDR_EIRQ_EN */
+#define IFX_GTM_EIRQ_EN_AEI_USP_ADDR_EIRQ_EN_OFF (1u)
+
+/** \brief Length for Ifx_GTM_EIRQ_EN_Bits.AEI_USP_BE_EIRQ_EN */
+#define IFX_GTM_EIRQ_EN_AEI_USP_BE_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_EIRQ_EN_Bits.AEI_USP_BE_EIRQ_EN */
+#define IFX_GTM_EIRQ_EN_AEI_USP_BE_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_EIRQ_EN_Bits.AEI_USP_BE_EIRQ_EN */
+#define IFX_GTM_EIRQ_EN_AEI_USP_BE_EIRQ_EN_OFF (3u)
+
+/** \brief Length for Ifx_GTM_F2A_ENABLE_Bits.STR0_EN */
+#define IFX_GTM_F2A_ENABLE_STR0_EN_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_F2A_ENABLE_Bits.STR0_EN */
+#define IFX_GTM_F2A_ENABLE_STR0_EN_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_F2A_ENABLE_Bits.STR0_EN */
+#define IFX_GTM_F2A_ENABLE_STR0_EN_OFF (0u)
+
+/** \brief Length for Ifx_GTM_F2A_ENABLE_Bits.STR1_EN */
+#define IFX_GTM_F2A_ENABLE_STR1_EN_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_F2A_ENABLE_Bits.STR1_EN */
+#define IFX_GTM_F2A_ENABLE_STR1_EN_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_F2A_ENABLE_Bits.STR1_EN */
+#define IFX_GTM_F2A_ENABLE_STR1_EN_OFF (2u)
+
+/** \brief Length for Ifx_GTM_F2A_ENABLE_Bits.STR2_EN */
+#define IFX_GTM_F2A_ENABLE_STR2_EN_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_F2A_ENABLE_Bits.STR2_EN */
+#define IFX_GTM_F2A_ENABLE_STR2_EN_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_F2A_ENABLE_Bits.STR2_EN */
+#define IFX_GTM_F2A_ENABLE_STR2_EN_OFF (4u)
+
+/** \brief Length for Ifx_GTM_F2A_ENABLE_Bits.STR3_EN */
+#define IFX_GTM_F2A_ENABLE_STR3_EN_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_F2A_ENABLE_Bits.STR3_EN */
+#define IFX_GTM_F2A_ENABLE_STR3_EN_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_F2A_ENABLE_Bits.STR3_EN */
+#define IFX_GTM_F2A_ENABLE_STR3_EN_OFF (6u)
+
+/** \brief Length for Ifx_GTM_F2A_ENABLE_Bits.STR4_EN */
+#define IFX_GTM_F2A_ENABLE_STR4_EN_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_F2A_ENABLE_Bits.STR4_EN */
+#define IFX_GTM_F2A_ENABLE_STR4_EN_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_F2A_ENABLE_Bits.STR4_EN */
+#define IFX_GTM_F2A_ENABLE_STR4_EN_OFF (8u)
+
+/** \brief Length for Ifx_GTM_F2A_ENABLE_Bits.STR5_EN */
+#define IFX_GTM_F2A_ENABLE_STR5_EN_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_F2A_ENABLE_Bits.STR5_EN */
+#define IFX_GTM_F2A_ENABLE_STR5_EN_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_F2A_ENABLE_Bits.STR5_EN */
+#define IFX_GTM_F2A_ENABLE_STR5_EN_OFF (10u)
+
+/** \brief Length for Ifx_GTM_F2A_ENABLE_Bits.STR6_EN */
+#define IFX_GTM_F2A_ENABLE_STR6_EN_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_F2A_ENABLE_Bits.STR6_EN */
+#define IFX_GTM_F2A_ENABLE_STR6_EN_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_F2A_ENABLE_Bits.STR6_EN */
+#define IFX_GTM_F2A_ENABLE_STR6_EN_OFF (12u)
+
+/** \brief Length for Ifx_GTM_F2A_ENABLE_Bits.STR7_EN */
+#define IFX_GTM_F2A_ENABLE_STR7_EN_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_F2A_ENABLE_Bits.STR7_EN */
+#define IFX_GTM_F2A_ENABLE_STR7_EN_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_F2A_ENABLE_Bits.STR7_EN */
+#define IFX_GTM_F2A_ENABLE_STR7_EN_OFF (14u)
+
+/** \brief Length for Ifx_GTM_F2A_RD_CH_ARU_RD_FIFO_Bits.ADDR */
+#define IFX_GTM_F2A_RD_CH_ARU_RD_FIFO_ADDR_LEN (9u)
+
+/** \brief Mask for Ifx_GTM_F2A_RD_CH_ARU_RD_FIFO_Bits.ADDR */
+#define IFX_GTM_F2A_RD_CH_ARU_RD_FIFO_ADDR_MSK (0x1ffu)
+
+/** \brief Offset for Ifx_GTM_F2A_RD_CH_ARU_RD_FIFO_Bits.ADDR */
+#define IFX_GTM_F2A_RD_CH_ARU_RD_FIFO_ADDR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_F2A_STR_CH_STR_CFG_Bits.DIR */
+#define IFX_GTM_F2A_STR_CH_STR_CFG_DIR_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_F2A_STR_CH_STR_CFG_Bits.DIR */
+#define IFX_GTM_F2A_STR_CH_STR_CFG_DIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_F2A_STR_CH_STR_CFG_Bits.DIR */
+#define IFX_GTM_F2A_STR_CH_STR_CFG_DIR_OFF (18u)
+
+/** \brief Length for Ifx_GTM_F2A_STR_CH_STR_CFG_Bits.TMODE */
+#define IFX_GTM_F2A_STR_CH_STR_CFG_TMODE_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_F2A_STR_CH_STR_CFG_Bits.TMODE */
+#define IFX_GTM_F2A_STR_CH_STR_CFG_TMODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_F2A_STR_CH_STR_CFG_Bits.TMODE */
+#define IFX_GTM_F2A_STR_CH_STR_CFG_TMODE_OFF (16u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_CTRL_Bits.FLUSH */
+#define IFX_GTM_FIFO_CH_CTRL_FLUSH_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_CTRL_Bits.FLUSH */
+#define IFX_GTM_FIFO_CH_CTRL_FLUSH_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_CTRL_Bits.FLUSH */
+#define IFX_GTM_FIFO_CH_CTRL_FLUSH_OFF (2u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_CTRL_Bits.RAP */
+#define IFX_GTM_FIFO_CH_CTRL_RAP_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_CTRL_Bits.RAP */
+#define IFX_GTM_FIFO_CH_CTRL_RAP_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_CTRL_Bits.RAP */
+#define IFX_GTM_FIFO_CH_CTRL_RAP_OFF (1u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_CTRL_Bits.RBM */
+#define IFX_GTM_FIFO_CH_CTRL_RBM_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_CTRL_Bits.RBM */
+#define IFX_GTM_FIFO_CH_CTRL_RBM_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_CTRL_Bits.RBM */
+#define IFX_GTM_FIFO_CH_CTRL_RBM_OFF (0u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_CTRL_Bits.WULOCK */
+#define IFX_GTM_FIFO_CH_CTRL_WULOCK_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_CTRL_Bits.WULOCK */
+#define IFX_GTM_FIFO_CH_CTRL_WULOCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_CTRL_Bits.WULOCK */
+#define IFX_GTM_FIFO_CH_CTRL_WULOCK_OFF (3u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_EIRQ_EN_Bits.FIFO_EMPTY_EIRQ_EN */
+#define IFX_GTM_FIFO_CH_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_EIRQ_EN_Bits.FIFO_EMPTY_EIRQ_EN */
+#define IFX_GTM_FIFO_CH_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_EIRQ_EN_Bits.FIFO_EMPTY_EIRQ_EN */
+#define IFX_GTM_FIFO_CH_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_OFF (0u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_EIRQ_EN_Bits.FIFO_FULL_EIRQ_EN */
+#define IFX_GTM_FIFO_CH_EIRQ_EN_FIFO_FULL_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_EIRQ_EN_Bits.FIFO_FULL_EIRQ_EN */
+#define IFX_GTM_FIFO_CH_EIRQ_EN_FIFO_FULL_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_EIRQ_EN_Bits.FIFO_FULL_EIRQ_EN */
+#define IFX_GTM_FIFO_CH_EIRQ_EN_FIFO_FULL_EIRQ_EN_OFF (1u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_EIRQ_EN_Bits.FIFO_LWM_EIRQ_EN */
+#define IFX_GTM_FIFO_CH_EIRQ_EN_FIFO_LWM_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_EIRQ_EN_Bits.FIFO_LWM_EIRQ_EN */
+#define IFX_GTM_FIFO_CH_EIRQ_EN_FIFO_LWM_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_EIRQ_EN_Bits.FIFO_LWM_EIRQ_EN */
+#define IFX_GTM_FIFO_CH_EIRQ_EN_FIFO_LWM_EIRQ_EN_OFF (2u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_EIRQ_EN_Bits.FIFO_UWM_EIRQ_EN */
+#define IFX_GTM_FIFO_CH_EIRQ_EN_FIFO_UWM_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_EIRQ_EN_Bits.FIFO_UWM_EIRQ_EN */
+#define IFX_GTM_FIFO_CH_EIRQ_EN_FIFO_UWM_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_EIRQ_EN_Bits.FIFO_UWM_EIRQ_EN */
+#define IFX_GTM_FIFO_CH_EIRQ_EN_FIFO_UWM_EIRQ_EN_OFF (3u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_EIRQ_EN_Bits.Reserved */
+#define IFX_GTM_FIFO_CH_EIRQ_EN_RESERVED_LEN (28u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_EIRQ_EN_Bits.Reserved */
+#define IFX_GTM_FIFO_CH_EIRQ_EN_RESERVED_MSK (0xfffffffu)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_EIRQ_EN_Bits.Reserved */
+#define IFX_GTM_FIFO_CH_EIRQ_EN_RESERVED_OFF (4u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_END_ADDR_Bits.ADDR */
+#define IFX_GTM_FIFO_CH_END_ADDR_ADDR_LEN (10u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_END_ADDR_Bits.ADDR */
+#define IFX_GTM_FIFO_CH_END_ADDR_ADDR_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_END_ADDR_Bits.ADDR */
+#define IFX_GTM_FIFO_CH_END_ADDR_ADDR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_FILL_LEVEL_Bits.LEVEL */
+#define IFX_GTM_FIFO_CH_FILL_LEVEL_LEVEL_LEN (11u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_FILL_LEVEL_Bits.LEVEL */
+#define IFX_GTM_FIFO_CH_FILL_LEVEL_LEVEL_MSK (0x7ffu)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_FILL_LEVEL_Bits.LEVEL */
+#define IFX_GTM_FIFO_CH_FILL_LEVEL_LEVEL_OFF (0u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_IRQ_EN_Bits.FIFO_EMPTY_IRQ_EN */
+#define IFX_GTM_FIFO_CH_IRQ_EN_FIFO_EMPTY_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_IRQ_EN_Bits.FIFO_EMPTY_IRQ_EN */
+#define IFX_GTM_FIFO_CH_IRQ_EN_FIFO_EMPTY_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_IRQ_EN_Bits.FIFO_EMPTY_IRQ_EN */
+#define IFX_GTM_FIFO_CH_IRQ_EN_FIFO_EMPTY_IRQ_EN_OFF (0u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_IRQ_EN_Bits.FIFO_FULL_IRQ_EN */
+#define IFX_GTM_FIFO_CH_IRQ_EN_FIFO_FULL_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_IRQ_EN_Bits.FIFO_FULL_IRQ_EN */
+#define IFX_GTM_FIFO_CH_IRQ_EN_FIFO_FULL_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_IRQ_EN_Bits.FIFO_FULL_IRQ_EN */
+#define IFX_GTM_FIFO_CH_IRQ_EN_FIFO_FULL_IRQ_EN_OFF (1u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_IRQ_EN_Bits.FIFO_LWM_IRQ_EN */
+#define IFX_GTM_FIFO_CH_IRQ_EN_FIFO_LWM_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_IRQ_EN_Bits.FIFO_LWM_IRQ_EN */
+#define IFX_GTM_FIFO_CH_IRQ_EN_FIFO_LWM_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_IRQ_EN_Bits.FIFO_LWM_IRQ_EN */
+#define IFX_GTM_FIFO_CH_IRQ_EN_FIFO_LWM_IRQ_EN_OFF (2u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_IRQ_EN_Bits.FIFO_UWM_IRQ_EN */
+#define IFX_GTM_FIFO_CH_IRQ_EN_FIFO_UWM_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_IRQ_EN_Bits.FIFO_UWM_IRQ_EN */
+#define IFX_GTM_FIFO_CH_IRQ_EN_FIFO_UWM_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_IRQ_EN_Bits.FIFO_UWM_IRQ_EN */
+#define IFX_GTM_FIFO_CH_IRQ_EN_FIFO_UWM_IRQ_EN_OFF (3u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_IRQ_FORCINT_Bits.TRG_FIFO_EMPTY */
+#define IFX_GTM_FIFO_CH_IRQ_FORCINT_TRG_FIFO_EMPTY_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_IRQ_FORCINT_Bits.TRG_FIFO_EMPTY */
+#define IFX_GTM_FIFO_CH_IRQ_FORCINT_TRG_FIFO_EMPTY_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_IRQ_FORCINT_Bits.TRG_FIFO_EMPTY */
+#define IFX_GTM_FIFO_CH_IRQ_FORCINT_TRG_FIFO_EMPTY_OFF (0u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_IRQ_FORCINT_Bits.TRG_FIFO_FULL */
+#define IFX_GTM_FIFO_CH_IRQ_FORCINT_TRG_FIFO_FULL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_IRQ_FORCINT_Bits.TRG_FIFO_FULL */
+#define IFX_GTM_FIFO_CH_IRQ_FORCINT_TRG_FIFO_FULL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_IRQ_FORCINT_Bits.TRG_FIFO_FULL */
+#define IFX_GTM_FIFO_CH_IRQ_FORCINT_TRG_FIFO_FULL_OFF (1u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_IRQ_FORCINT_Bits.TRG_FIFO_LWM */
+#define IFX_GTM_FIFO_CH_IRQ_FORCINT_TRG_FIFO_LWM_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_IRQ_FORCINT_Bits.TRG_FIFO_LWM */
+#define IFX_GTM_FIFO_CH_IRQ_FORCINT_TRG_FIFO_LWM_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_IRQ_FORCINT_Bits.TRG_FIFO_LWM */
+#define IFX_GTM_FIFO_CH_IRQ_FORCINT_TRG_FIFO_LWM_OFF (2u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_IRQ_FORCINT_Bits.TRG_FIFO_UWM */
+#define IFX_GTM_FIFO_CH_IRQ_FORCINT_TRG_FIFO_UWM_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_IRQ_FORCINT_Bits.TRG_FIFO_UWM */
+#define IFX_GTM_FIFO_CH_IRQ_FORCINT_TRG_FIFO_UWM_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_IRQ_FORCINT_Bits.TRG_FIFO_UWM */
+#define IFX_GTM_FIFO_CH_IRQ_FORCINT_TRG_FIFO_UWM_OFF (3u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_IRQ_MODE_Bits.DMA_HYST_DIR */
+#define IFX_GTM_FIFO_CH_IRQ_MODE_DMA_HYST_DIR_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_IRQ_MODE_Bits.DMA_HYST_DIR */
+#define IFX_GTM_FIFO_CH_IRQ_MODE_DMA_HYST_DIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_IRQ_MODE_Bits.DMA_HYST_DIR */
+#define IFX_GTM_FIFO_CH_IRQ_MODE_DMA_HYST_DIR_OFF (3u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_IRQ_MODE_Bits.DMA_HYSTERESIS */
+#define IFX_GTM_FIFO_CH_IRQ_MODE_DMA_HYSTERESIS_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_IRQ_MODE_Bits.DMA_HYSTERESIS */
+#define IFX_GTM_FIFO_CH_IRQ_MODE_DMA_HYSTERESIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_IRQ_MODE_Bits.DMA_HYSTERESIS */
+#define IFX_GTM_FIFO_CH_IRQ_MODE_DMA_HYSTERESIS_OFF (2u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_FIFO_CH_IRQ_MODE_IRQ_MODE_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_FIFO_CH_IRQ_MODE_IRQ_MODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_FIFO_CH_IRQ_MODE_IRQ_MODE_OFF (0u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_IRQ_NOTIFY_Bits.FIFO_EMPTY */
+#define IFX_GTM_FIFO_CH_IRQ_NOTIFY_FIFO_EMPTY_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_IRQ_NOTIFY_Bits.FIFO_EMPTY */
+#define IFX_GTM_FIFO_CH_IRQ_NOTIFY_FIFO_EMPTY_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_IRQ_NOTIFY_Bits.FIFO_EMPTY */
+#define IFX_GTM_FIFO_CH_IRQ_NOTIFY_FIFO_EMPTY_OFF (0u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_IRQ_NOTIFY_Bits.FIFO_FULL */
+#define IFX_GTM_FIFO_CH_IRQ_NOTIFY_FIFO_FULL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_IRQ_NOTIFY_Bits.FIFO_FULL */
+#define IFX_GTM_FIFO_CH_IRQ_NOTIFY_FIFO_FULL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_IRQ_NOTIFY_Bits.FIFO_FULL */
+#define IFX_GTM_FIFO_CH_IRQ_NOTIFY_FIFO_FULL_OFF (1u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_IRQ_NOTIFY_Bits.FIFO_LWM */
+#define IFX_GTM_FIFO_CH_IRQ_NOTIFY_FIFO_LWM_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_IRQ_NOTIFY_Bits.FIFO_LWM */
+#define IFX_GTM_FIFO_CH_IRQ_NOTIFY_FIFO_LWM_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_IRQ_NOTIFY_Bits.FIFO_LWM */
+#define IFX_GTM_FIFO_CH_IRQ_NOTIFY_FIFO_LWM_OFF (2u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_IRQ_NOTIFY_Bits.FIFO_UWM */
+#define IFX_GTM_FIFO_CH_IRQ_NOTIFY_FIFO_UWM_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_IRQ_NOTIFY_Bits.FIFO_UWM */
+#define IFX_GTM_FIFO_CH_IRQ_NOTIFY_FIFO_UWM_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_IRQ_NOTIFY_Bits.FIFO_UWM */
+#define IFX_GTM_FIFO_CH_IRQ_NOTIFY_FIFO_UWM_OFF (3u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_LOWER_WM_Bits.ADDR */
+#define IFX_GTM_FIFO_CH_LOWER_WM_ADDR_LEN (10u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_LOWER_WM_Bits.ADDR */
+#define IFX_GTM_FIFO_CH_LOWER_WM_ADDR_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_LOWER_WM_Bits.ADDR */
+#define IFX_GTM_FIFO_CH_LOWER_WM_ADDR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_RD_PTR_Bits.ADDR */
+#define IFX_GTM_FIFO_CH_RD_PTR_ADDR_LEN (10u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_RD_PTR_Bits.ADDR */
+#define IFX_GTM_FIFO_CH_RD_PTR_ADDR_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_RD_PTR_Bits.ADDR */
+#define IFX_GTM_FIFO_CH_RD_PTR_ADDR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_START_ADDR_Bits.ADDR */
+#define IFX_GTM_FIFO_CH_START_ADDR_ADDR_LEN (10u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_START_ADDR_Bits.ADDR */
+#define IFX_GTM_FIFO_CH_START_ADDR_ADDR_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_START_ADDR_Bits.ADDR */
+#define IFX_GTM_FIFO_CH_START_ADDR_ADDR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_STATUS_Bits.EMPTY */
+#define IFX_GTM_FIFO_CH_STATUS_EMPTY_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_STATUS_Bits.EMPTY */
+#define IFX_GTM_FIFO_CH_STATUS_EMPTY_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_STATUS_Bits.EMPTY */
+#define IFX_GTM_FIFO_CH_STATUS_EMPTY_OFF (0u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_STATUS_Bits.FULL */
+#define IFX_GTM_FIFO_CH_STATUS_FULL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_STATUS_Bits.FULL */
+#define IFX_GTM_FIFO_CH_STATUS_FULL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_STATUS_Bits.FULL */
+#define IFX_GTM_FIFO_CH_STATUS_FULL_OFF (1u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_STATUS_Bits.LOW_WM */
+#define IFX_GTM_FIFO_CH_STATUS_LOW_WM_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_STATUS_Bits.LOW_WM */
+#define IFX_GTM_FIFO_CH_STATUS_LOW_WM_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_STATUS_Bits.LOW_WM */
+#define IFX_GTM_FIFO_CH_STATUS_LOW_WM_OFF (2u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_STATUS_Bits.UP_WM */
+#define IFX_GTM_FIFO_CH_STATUS_UP_WM_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_STATUS_Bits.UP_WM */
+#define IFX_GTM_FIFO_CH_STATUS_UP_WM_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_STATUS_Bits.UP_WM */
+#define IFX_GTM_FIFO_CH_STATUS_UP_WM_OFF (3u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_UPPER_WM_Bits.ADDR */
+#define IFX_GTM_FIFO_CH_UPPER_WM_ADDR_LEN (10u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_UPPER_WM_Bits.ADDR */
+#define IFX_GTM_FIFO_CH_UPPER_WM_ADDR_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_UPPER_WM_Bits.ADDR */
+#define IFX_GTM_FIFO_CH_UPPER_WM_ADDR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_FIFO_CH_WR_PTR_Bits.ADDR */
+#define IFX_GTM_FIFO_CH_WR_PTR_ADDR_LEN (10u)
+
+/** \brief Mask for Ifx_GTM_FIFO_CH_WR_PTR_Bits.ADDR */
+#define IFX_GTM_FIFO_CH_WR_PTR_ADDR_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_GTM_FIFO_CH_WR_PTR_Bits.ADDR */
+#define IFX_GTM_FIFO_CH_WR_PTR_ADDR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_0_Bits.AEI_IRQ */
+#define IFX_GTM_ICM_IRQG_0_AEI_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_0_Bits.AEI_IRQ */
+#define IFX_GTM_ICM_IRQG_0_AEI_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_0_Bits.AEI_IRQ */
+#define IFX_GTM_ICM_IRQG_0_AEI_IRQ_OFF (4u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_0_Bits.ARU_ACC_ACK_IRQ */
+#define IFX_GTM_ICM_IRQG_0_ARU_ACC_ACK_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_0_Bits.ARU_ACC_ACK_IRQ */
+#define IFX_GTM_ICM_IRQG_0_ARU_ACC_ACK_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_0_Bits.ARU_ACC_ACK_IRQ */
+#define IFX_GTM_ICM_IRQG_0_ARU_ACC_ACK_IRQ_OFF (2u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_0_Bits.ARU_NEW_DATA0_IRQ */
+#define IFX_GTM_ICM_IRQG_0_ARU_NEW_DATA0_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_0_Bits.ARU_NEW_DATA0_IRQ */
+#define IFX_GTM_ICM_IRQG_0_ARU_NEW_DATA0_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_0_Bits.ARU_NEW_DATA0_IRQ */
+#define IFX_GTM_ICM_IRQG_0_ARU_NEW_DATA0_IRQ_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_0_Bits.ARU_NEW_DATA1_IRQ */
+#define IFX_GTM_ICM_IRQG_0_ARU_NEW_DATA1_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_0_Bits.ARU_NEW_DATA1_IRQ */
+#define IFX_GTM_ICM_IRQG_0_ARU_NEW_DATA1_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_0_Bits.ARU_NEW_DATA1_IRQ */
+#define IFX_GTM_ICM_IRQG_0_ARU_NEW_DATA1_IRQ_OFF (1u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_0_Bits.BRC_IRQ */
+#define IFX_GTM_ICM_IRQG_0_BRC_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_0_Bits.BRC_IRQ */
+#define IFX_GTM_ICM_IRQG_0_BRC_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_0_Bits.BRC_IRQ */
+#define IFX_GTM_ICM_IRQG_0_BRC_IRQ_OFF (3u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_0_Bits.CMP_IRQ */
+#define IFX_GTM_ICM_IRQG_0_CMP_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_0_Bits.CMP_IRQ */
+#define IFX_GTM_ICM_IRQG_0_CMP_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_0_Bits.CMP_IRQ */
+#define IFX_GTM_ICM_IRQG_0_CMP_IRQ_OFF (5u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_0_PSM0_CH0_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_0_PSM0_CH0_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_0_PSM0_CH0_IRQ_OFF (16u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_0_PSM0_CH1_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_0_PSM0_CH1_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_0_PSM0_CH1_IRQ_OFF (17u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_0_PSM0_CH2_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_0_PSM0_CH2_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_0_PSM0_CH2_IRQ_OFF (18u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_0_PSM0_CH3_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_0_PSM0_CH3_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_0_PSM0_CH3_IRQ_OFF (19u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_0_PSM0_CH4_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_0_PSM0_CH4_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_0_PSM0_CH4_IRQ_OFF (20u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_0_PSM0_CH5_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_0_PSM0_CH5_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_0_PSM0_CH5_IRQ_OFF (21u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_0_PSM0_CH6_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_0_PSM0_CH6_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_0_PSM0_CH6_IRQ_OFF (22u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_0_PSM0_CH7_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_0_PSM0_CH7_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_0_PSM0_CH7_IRQ_OFF (23u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_0_Bits.SPE0_IRQ */
+#define IFX_GTM_ICM_IRQG_0_SPE0_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_0_Bits.SPE0_IRQ */
+#define IFX_GTM_ICM_IRQG_0_SPE0_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_0_Bits.SPE0_IRQ */
+#define IFX_GTM_ICM_IRQG_0_SPE0_IRQ_OFF (6u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_0_Bits.SPE1_IRQ */
+#define IFX_GTM_ICM_IRQG_0_SPE1_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_0_Bits.SPE1_IRQ */
+#define IFX_GTM_ICM_IRQG_0_SPE1_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_0_Bits.SPE1_IRQ */
+#define IFX_GTM_ICM_IRQG_0_SPE1_IRQ_OFF (7u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_CDIS_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_CDIS_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_CDIS_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_CDIS_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_CDIS_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_CDIS_IRQ_OFF (24u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_CDIT_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_CDIT_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_CDIT_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_CDIT_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_CDIT_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_CDIT_IRQ_OFF (23u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_DCG_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_DCG_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_DCG_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_DCG_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_DCG_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_DCG_IRQ_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_EDI_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_EDI_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_EDI_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_EDI_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_EDI_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_EDI_IRQ_OFF (1u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_EI_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_EI_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_EI_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_EI_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_EI_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_EI_IRQ_OFF (15u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_GL2I_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_GL2I_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_GL2I_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_GL2I_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_GL2I_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_GL2I_IRQ_OFF (16u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_GLI_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_GLI_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_GLI_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_GLI_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_GLI_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_GLI_IRQ_OFF (13u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_LL2I_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_LL2I_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_LL2I_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_LL2I_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_LL2I_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_LL2I_IRQ_OFF (17u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_LLI_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_LLI_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_LLI_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_LLI_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_LLI_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_LLI_IRQ_OFF (14u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_MSI_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_MSI_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_MSI_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_MSI_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_MSI_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_MSI_IRQ_OFF (6u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_MTI_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_MTI_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_MTI_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_MTI_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_MTI_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_MTI_IRQ_OFF (7u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_PWI_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_PWI_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_PWI_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_PWI_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_PWI_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_PWI_IRQ_OFF (10u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_SAS_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_SAS_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_SAS_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_SAS_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_SAS_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_SAS_IRQ_OFF (8u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_SIS_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_SIS_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_SIS_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_SIS_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_SIS_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_SIS_IRQ_OFF (4u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_SORI_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_SORI_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_SORI_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_SORI_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_SORI_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_SORI_IRQ_OFF (26u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TAS_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_TAS_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TAS_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_TAS_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TAS_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_TAS_IRQ_OFF (9u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TAX_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_TAX_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TAX_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_TAX_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TAX_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_TAX_IRQ_OFF (3u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TE0_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_TE0_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TE0_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_TE0_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TE0_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_TE0_IRQ_OFF (18u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TE1_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_TE1_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TE1_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_TE1_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TE1_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_TE1_IRQ_OFF (19u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TE2_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_TE2_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TE2_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_TE2_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TE2_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_TE2_IRQ_OFF (20u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TE3_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_TE3_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TE3_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_TE3_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TE3_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_TE3_IRQ_OFF (21u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TE4_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_TE4_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TE4_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_TE4_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TE4_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_TE4_IRQ_OFF (22u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TIN_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_TIN_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TIN_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_TIN_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TIN_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_TIN_IRQ_OFF (2u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TIS_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_TIS_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TIS_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_TIS_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TIS_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_TIS_IRQ_OFF (5u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TORI_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_TORI_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TORI_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_TORI_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TORI_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_TORI_IRQ_OFF (25u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_W1I_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_W1I_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_W1I_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_W1I_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_W1I_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_W1I_IRQ_OFF (12u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_W2I_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_W2I_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_W2I_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_W2I_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_W2I_IRQ */
+#define IFX_GTM_ICM_IRQG_1_DPLL_W2I_IRQ_OFF (11u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM0_CH0_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM0_CH0_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM0_CH0_IRQ_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM0_CH1_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM0_CH1_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM0_CH1_IRQ_OFF (1u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM0_CH2_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM0_CH2_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM0_CH2_IRQ_OFF (2u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM0_CH3_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM0_CH3_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM0_CH3_IRQ_OFF (3u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM0_CH4_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM0_CH4_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM0_CH4_IRQ_OFF (4u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM0_CH5_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM0_CH5_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM0_CH5_IRQ_OFF (5u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM0_CH6_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM0_CH6_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM0_CH6_IRQ_OFF (6u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM0_CH7_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM0_CH7_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM0_CH7_IRQ_OFF (7u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM1_CH0_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM1_CH0_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM1_CH0_IRQ_OFF (8u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM1_CH1_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM1_CH1_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM1_CH1_IRQ_OFF (9u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM1_CH2_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM1_CH2_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM1_CH2_IRQ_OFF (10u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM1_CH3_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM1_CH3_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM1_CH3_IRQ_OFF (11u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM1_CH4_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM1_CH4_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM1_CH4_IRQ_OFF (12u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM1_CH5_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM1_CH5_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM1_CH5_IRQ_OFF (13u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM1_CH6_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM1_CH6_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM1_CH6_IRQ_OFF (14u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM1_CH7_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM1_CH7_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM1_CH7_IRQ_OFF (15u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM2_CH0_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM2_CH0_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM2_CH0_IRQ_OFF (16u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM2_CH1_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM2_CH1_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM2_CH1_IRQ_OFF (17u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM2_CH2_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM2_CH2_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM2_CH2_IRQ_OFF (18u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM2_CH3_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM2_CH3_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM2_CH3_IRQ_OFF (19u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM2_CH4_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM2_CH4_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM2_CH4_IRQ_OFF (20u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM2_CH5_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM2_CH5_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM2_CH5_IRQ_OFF (21u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM2_CH6_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM2_CH6_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM2_CH6_IRQ_OFF (22u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM2_CH7_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM2_CH7_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_2_TIM2_CH7_IRQ_OFF (23u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS0_CH0_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS0_CH0_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS0_CH0_IRQ_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS0_CH1_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS0_CH1_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS0_CH1_IRQ_OFF (1u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS0_CH2_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS0_CH2_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS0_CH2_IRQ_OFF (2u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS0_CH3_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS0_CH3_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS0_CH3_IRQ_OFF (3u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS0_CH4_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS0_CH4_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS0_CH4_IRQ_OFF (4u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS0_CH5_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS0_CH5_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS0_CH5_IRQ_OFF (5u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS0_CH6_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS0_CH6_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS0_CH6_IRQ_OFF (6u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS0_CH7_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS0_CH7_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS0_CH7_IRQ_OFF (7u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS1_CH0_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS1_CH0_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS1_CH0_IRQ_OFF (8u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS1_CH1_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS1_CH1_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS1_CH1_IRQ_OFF (9u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS1_CH2_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS1_CH2_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS1_CH2_IRQ_OFF (10u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS1_CH3_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS1_CH3_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS1_CH3_IRQ_OFF (11u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS1_CH4_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS1_CH4_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS1_CH4_IRQ_OFF (12u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS1_CH5_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS1_CH5_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS1_CH5_IRQ_OFF (13u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS1_CH6_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS1_CH6_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS1_CH6_IRQ_OFF (14u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS1_CH7_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS1_CH7_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS1_CH7_IRQ_OFF (15u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS2_CH0_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS2_CH0_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS2_CH0_IRQ_OFF (16u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS2_CH1_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS2_CH1_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS2_CH1_IRQ_OFF (17u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS2_CH2_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS2_CH2_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS2_CH2_IRQ_OFF (18u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS2_CH3_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS2_CH3_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS2_CH3_IRQ_OFF (19u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS2_CH4_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS2_CH4_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS2_CH4_IRQ_OFF (20u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS2_CH5_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS2_CH5_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS2_CH5_IRQ_OFF (21u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS2_CH6_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS2_CH6_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS2_CH6_IRQ_OFF (22u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS2_CH7_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS2_CH7_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_4_MCS2_CH7_IRQ_OFF (23u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH0_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH0_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH0_IRQ_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH10_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH10_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH10_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH10_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH10_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH10_IRQ_OFF (10u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH11_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH11_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH11_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH11_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH11_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH11_IRQ_OFF (11u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH12_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH12_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH12_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH12_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH12_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH12_IRQ_OFF (12u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH13_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH13_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH13_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH13_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH13_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH13_IRQ_OFF (13u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH14_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH14_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH14_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH14_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH14_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH14_IRQ_OFF (14u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH15_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH15_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH15_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH15_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH15_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH15_IRQ_OFF (15u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH1_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH1_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH1_IRQ_OFF (1u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH2_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH2_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH2_IRQ_OFF (2u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH3_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH3_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH3_IRQ_OFF (3u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH4_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH4_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH4_IRQ_OFF (4u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH5_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH5_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH5_IRQ_OFF (5u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH6_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH6_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH6_IRQ_OFF (6u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH7_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH7_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH7_IRQ_OFF (7u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH8_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH8_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH8_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH8_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH8_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH8_IRQ_OFF (8u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH9_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH9_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH9_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH9_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH9_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM0_CH9_IRQ_OFF (9u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH0_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH0_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH0_IRQ_OFF (16u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH10_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH10_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH10_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH10_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH10_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH10_IRQ_OFF (26u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH11_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH11_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH11_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH11_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH11_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH11_IRQ_OFF (27u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH12_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH12_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH12_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH12_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH12_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH12_IRQ_OFF (28u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH13_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH13_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH13_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH13_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH13_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH13_IRQ_OFF (29u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH14_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH14_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH14_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH14_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH14_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH14_IRQ_OFF (30u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH15_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH15_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH15_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH15_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH15_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH15_IRQ_OFF (31u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH1_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH1_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH1_IRQ_OFF (17u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH2_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH2_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH2_IRQ_OFF (18u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH3_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH3_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH3_IRQ_OFF (19u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH4_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH4_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH4_IRQ_OFF (20u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH5_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH5_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH5_IRQ_OFF (21u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH6_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH6_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH6_IRQ_OFF (22u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH7_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH7_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH7_IRQ_OFF (23u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH8_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH8_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH8_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH8_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH8_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH8_IRQ_OFF (24u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH9_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH9_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH9_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH9_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH9_IRQ */
+#define IFX_GTM_ICM_IRQG_6_TOM1_CH9_IRQ_OFF (25u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM0_CH0_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM0_CH0_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM0_CH0_IRQ_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM0_CH1_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM0_CH1_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM0_CH1_IRQ_OFF (1u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM0_CH2_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM0_CH2_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM0_CH2_IRQ_OFF (2u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM0_CH3_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM0_CH3_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM0_CH3_IRQ_OFF (3u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM0_CH4_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM0_CH4_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM0_CH4_IRQ_OFF (4u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM0_CH5_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM0_CH5_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM0_CH5_IRQ_OFF (5u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM0_CH6_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM0_CH6_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM0_CH6_IRQ_OFF (6u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM0_CH7_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM0_CH7_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM0_CH7_IRQ_OFF (7u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM1_CH0_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM1_CH0_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM1_CH0_IRQ_OFF (8u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM1_CH1_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM1_CH1_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM1_CH1_IRQ_OFF (9u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM1_CH2_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM1_CH2_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM1_CH2_IRQ_OFF (10u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM1_CH3_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM1_CH3_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM1_CH3_IRQ_OFF (11u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM1_CH4_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM1_CH4_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM1_CH4_IRQ_OFF (12u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM1_CH5_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM1_CH5_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM1_CH5_IRQ_OFF (13u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM1_CH6_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM1_CH6_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM1_CH6_IRQ_OFF (14u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM1_CH7_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM1_CH7_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM1_CH7_IRQ_OFF (15u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM2_CH0_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM2_CH0_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM2_CH0_IRQ_OFF (16u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM2_CH1_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM2_CH1_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM2_CH1_IRQ_OFF (17u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM2_CH2_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM2_CH2_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM2_CH2_IRQ_OFF (18u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM2_CH3_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM2_CH3_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM2_CH3_IRQ_OFF (19u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM2_CH4_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM2_CH4_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM2_CH4_IRQ_OFF (20u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM2_CH5_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM2_CH5_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM2_CH5_IRQ_OFF (21u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM2_CH6_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM2_CH6_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM2_CH6_IRQ_OFF (22u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM2_CH7_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM2_CH7_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM2_CH7_IRQ_OFF (23u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM3_CH0_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM3_CH0_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH0_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM3_CH0_IRQ_OFF (24u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM3_CH1_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM3_CH1_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH1_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM3_CH1_IRQ_OFF (25u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM3_CH2_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM3_CH2_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH2_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM3_CH2_IRQ_OFF (26u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM3_CH3_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM3_CH3_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH3_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM3_CH3_IRQ_OFF (27u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM3_CH4_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM3_CH4_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH4_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM3_CH4_IRQ_OFF (28u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM3_CH5_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM3_CH5_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH5_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM3_CH5_IRQ_OFF (29u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM3_CH6_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM3_CH6_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH6_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM3_CH6_IRQ_OFF (30u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM3_CH7_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM3_CH7_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH7_IRQ */
+#define IFX_GTM_ICM_IRQG_9_ATOM3_CH7_IRQ_OFF (31u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH0_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH0_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH0_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH0_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH0_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH0_EIRQ_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH1_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH1_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH1_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH1_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH1_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH1_EIRQ_OFF (1u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH2_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH2_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH2_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH2_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH2_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH2_EIRQ_OFF (2u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH3_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH3_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH3_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH3_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH3_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH3_EIRQ_OFF (3u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH4_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH4_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH4_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH4_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH4_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH4_EIRQ_OFF (4u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH5_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH5_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH5_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH5_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH5_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH5_EIRQ_OFF (5u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH6_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH6_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH6_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH6_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH6_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH6_EIRQ_OFF (6u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH7_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH7_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH7_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH7_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH7_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH7_EIRQ_OFF (7u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH0_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH0_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH0_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH0_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH0_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH0_EIRQ_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH1_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH1_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH1_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH1_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH1_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH1_EIRQ_OFF (1u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH2_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH2_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH2_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH2_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH2_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH2_EIRQ_OFF (2u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH3_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH3_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH3_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH3_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH3_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH3_EIRQ_OFF (3u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH4_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH4_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH4_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH4_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH4_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH4_EIRQ_OFF (4u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH5_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH5_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH5_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH5_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH5_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH5_EIRQ_OFF (5u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH6_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH6_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH6_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH6_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH6_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH6_EIRQ_OFF (6u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH7_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH7_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH7_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH7_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH7_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH7_EIRQ_OFF (7u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH0_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH0_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH0_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH0_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH0_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH0_EIRQ_OFF (8u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH1_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH1_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH1_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH1_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH1_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH1_EIRQ_OFF (9u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH2_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH2_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH2_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH2_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH2_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH2_EIRQ_OFF (10u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH3_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH3_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH3_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH3_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH3_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH3_EIRQ_OFF (11u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH4_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH4_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH4_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH4_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH4_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH4_EIRQ_OFF (12u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH5_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH5_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH5_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH5_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH5_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH5_EIRQ_OFF (13u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH6_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH6_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH6_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH6_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH6_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH6_EIRQ_OFF (14u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH7_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH7_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH7_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH7_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH7_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH7_EIRQ_OFF (15u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH0_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH0_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH0_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH0_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH0_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH0_EIRQ_OFF (16u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH1_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH1_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH1_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH1_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH1_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH1_EIRQ_OFF (17u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH2_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH2_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH2_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH2_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH2_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH2_EIRQ_OFF (18u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH3_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH3_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH3_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH3_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH3_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH3_EIRQ_OFF (19u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH4_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH4_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH4_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH4_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH4_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH4_EIRQ_OFF (20u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH5_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH5_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH5_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH5_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH5_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH5_EIRQ_OFF (21u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH6_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH6_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH6_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH6_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH6_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH6_EIRQ_OFF (22u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH7_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH7_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH7_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH7_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH7_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH7_EIRQ_OFF (23u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH0_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH0_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH0_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH0_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH0_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH0_EIRQ_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH1_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH1_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH1_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH1_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH1_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH1_EIRQ_OFF (1u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH2_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH2_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH2_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH2_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH2_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH2_EIRQ_OFF (2u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH3_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH3_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH3_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH3_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH3_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH3_EIRQ_OFF (3u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH4_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH4_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH4_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH4_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH4_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH4_EIRQ_OFF (4u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH5_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH5_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH5_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH5_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH5_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH5_EIRQ_OFF (5u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH6_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH6_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH6_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH6_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH6_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH6_EIRQ_OFF (6u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH7_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH7_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH7_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH7_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH7_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH7_EIRQ_OFF (7u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH0_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH0_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH0_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH0_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH0_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH0_EIRQ_OFF (8u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH1_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH1_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH1_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH1_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH1_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH1_EIRQ_OFF (9u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH2_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH2_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH2_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH2_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH2_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH2_EIRQ_OFF (10u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH3_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH3_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH3_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH3_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH3_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH3_EIRQ_OFF (11u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH4_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH4_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH4_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH4_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH4_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH4_EIRQ_OFF (12u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH5_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH5_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH5_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH5_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH5_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH5_EIRQ_OFF (13u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH6_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH6_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH6_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH6_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH6_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH6_EIRQ_OFF (14u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH7_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH7_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH7_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH7_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH7_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH7_EIRQ_OFF (15u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH0_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH0_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH0_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH0_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH0_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH0_EIRQ_OFF (16u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH1_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH1_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH1_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH1_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH1_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH1_EIRQ_OFF (17u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH2_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH2_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH2_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH2_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH2_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH2_EIRQ_OFF (18u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH3_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH3_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH3_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH3_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH3_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH3_EIRQ_OFF (19u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH4_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH4_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH4_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH4_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH4_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH4_EIRQ_OFF (20u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH5_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH5_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH5_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH5_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH5_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH5_EIRQ_OFF (21u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH6_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH6_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH6_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH6_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH6_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH6_EIRQ_OFF (22u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH7_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH7_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH7_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH7_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH7_EIRQ */
+#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH7_EIRQ_OFF (23u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_MEI_Bits.BRC_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_BRC_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_MEI_Bits.BRC_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_BRC_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_MEI_Bits.BRC_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_BRC_EIRQ_OFF (1u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_MEI_Bits.CMP_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_CMP_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_MEI_Bits.CMP_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_CMP_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_MEI_Bits.CMP_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_CMP_EIRQ_OFF (24u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_MEI_Bits.DPLL_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_DPLL_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_MEI_Bits.DPLL_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_DPLL_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_MEI_Bits.DPLL_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_DPLL_EIRQ_OFF (25u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_MEI_Bits.FIFO0_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_FIFO0_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_MEI_Bits.FIFO0_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_FIFO0_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_MEI_Bits.FIFO0_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_FIFO0_EIRQ_OFF (2u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_MEI_Bits.GTM_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_GTM_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_MEI_Bits.GTM_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_GTM_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_MEI_Bits.GTM_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_GTM_EIRQ_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_MEI_Bits.MCS0_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_MCS0_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_MEI_Bits.MCS0_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_MCS0_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_MEI_Bits.MCS0_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_MCS0_EIRQ_OFF (12u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_MEI_Bits.MCS1_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_MCS1_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_MEI_Bits.MCS1_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_MCS1_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_MEI_Bits.MCS1_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_MCS1_EIRQ_OFF (13u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_MEI_Bits.MCS2_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_MCS2_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_MEI_Bits.MCS2_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_MCS2_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_MEI_Bits.MCS2_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_MCS2_EIRQ_OFF (14u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_MEI_Bits.SPE0_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_SPE0_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_MEI_Bits.SPE0_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_SPE0_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_MEI_Bits.SPE0_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_SPE0_EIRQ_OFF (20u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_MEI_Bits.SPE1_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_SPE1_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_MEI_Bits.SPE1_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_SPE1_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_MEI_Bits.SPE1_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_SPE1_EIRQ_OFF (21u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_MEI_Bits.TIM0_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_TIM0_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_MEI_Bits.TIM0_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_TIM0_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_MEI_Bits.TIM0_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_TIM0_EIRQ_OFF (4u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_MEI_Bits.TIM1_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_TIM1_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_MEI_Bits.TIM1_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_TIM1_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_MEI_Bits.TIM1_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_TIM1_EIRQ_OFF (5u)
+
+/** \brief Length for Ifx_GTM_ICM_IRQG_MEI_Bits.TIM2_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_TIM2_EIRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ICM_IRQG_MEI_Bits.TIM2_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_TIM2_EIRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ICM_IRQG_MEI_Bits.TIM2_EIRQ */
+#define IFX_GTM_ICM_IRQG_MEI_TIM2_EIRQ_OFF (6u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL0 */
+#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL0_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL0 */
+#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL0_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL0 */
+#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL1 */
+#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL1_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL1 */
+#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL1_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL1 */
+#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL1_OFF (4u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL2 */
+#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL2_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL2 */
+#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL2_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL2 */
+#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL2_OFF (8u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL3 */
+#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL3_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL3 */
+#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL3_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL3 */
+#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL3_OFF (12u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL4 */
+#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL4_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL4 */
+#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL4_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL4 */
+#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL4_OFF (16u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL5 */
+#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL5_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL5 */
+#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL5_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL5 */
+#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL5_OFF (20u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL6 */
+#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL6_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL6 */
+#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL6_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL6 */
+#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL6_OFF (24u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL7 */
+#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL7_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL7 */
+#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL7_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL7 */
+#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL7_OFF (28u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL0 */
+#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL0_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL0 */
+#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL0_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL0 */
+#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL1 */
+#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL1_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL1 */
+#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL1_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL1 */
+#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL1_OFF (4u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL2 */
+#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL2_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL2 */
+#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL2_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL2 */
+#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL2_OFF (8u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL3 */
+#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL3_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL3 */
+#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL3_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL3 */
+#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL3_OFF (12u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL4 */
+#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL4_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL4 */
+#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL4_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL4 */
+#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL4_OFF (16u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL5 */
+#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL5_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL5 */
+#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL5_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL5 */
+#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL5_OFF (20u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL6 */
+#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL6_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL6 */
+#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL6_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL6 */
+#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL6_OFF (24u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL7 */
+#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL7_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL7 */
+#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL7_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL7 */
+#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL7_OFF (28u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_DSADC_OUTSEL_Bits.SEL0 */
+#define IFX_GTM_INOUTSEL_DSADC_OUTSEL_SEL0_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_DSADC_OUTSEL_Bits.SEL0 */
+#define IFX_GTM_INOUTSEL_DSADC_OUTSEL_SEL0_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_DSADC_OUTSEL_Bits.SEL0 */
+#define IFX_GTM_INOUTSEL_DSADC_OUTSEL_SEL0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_DSADC_OUTSEL_Bits.SEL2 */
+#define IFX_GTM_INOUTSEL_DSADC_OUTSEL_SEL2_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_DSADC_OUTSEL_Bits.SEL2 */
+#define IFX_GTM_INOUTSEL_DSADC_OUTSEL_SEL2_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_DSADC_OUTSEL_Bits.SEL2 */
+#define IFX_GTM_INOUTSEL_DSADC_OUTSEL_SEL2_OFF (8u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_DSADC_OUTSEL_Bits.SEL3 */
+#define IFX_GTM_INOUTSEL_DSADC_OUTSEL_SEL3_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_DSADC_OUTSEL_Bits.SEL3 */
+#define IFX_GTM_INOUTSEL_DSADC_OUTSEL_SEL3_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_DSADC_OUTSEL_Bits.SEL3 */
+#define IFX_GTM_INOUTSEL_DSADC_OUTSEL_SEL3_OFF (12u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL0 */
+#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL0_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL0 */
+#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL0_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL0 */
+#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL1 */
+#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL1_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL1 */
+#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL1_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL1 */
+#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL1_OFF (4u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL2 */
+#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL2_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL2 */
+#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL2_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL2 */
+#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL2_OFF (8u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL3 */
+#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL3_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL3 */
+#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL3_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL3 */
+#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL3_OFF (12u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL4 */
+#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL4_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL4 */
+#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL4_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL4 */
+#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL4_OFF (16u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL5 */
+#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL5_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL5 */
+#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL5_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL5 */
+#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL5_OFF (20u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL0 */
+#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL0_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL0 */
+#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL0_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL0 */
+#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL1 */
+#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL1_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL1 */
+#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL1_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL1 */
+#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL1_OFF (4u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL2 */
+#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL2_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL2 */
+#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL2_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL2 */
+#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL2_OFF (8u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL4 */
+#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL4_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL4 */
+#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL4_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL4 */
+#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL4_OFF (16u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL5 */
+#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL5_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL5 */
+#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL5_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL5 */
+#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL5_OFF (20u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL6 */
+#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL6_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL6 */
+#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL6_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL6 */
+#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL6_OFF (24u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL0 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL0 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL0 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL10 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL10_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL10 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL10_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL10 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL10_OFF (20u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL11 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL11_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL11 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL11_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL11 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL11_OFF (22u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL12 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL12_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL12 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL12_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL12 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL12_OFF (24u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL13 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL13_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL13 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL13_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL13 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL13_OFF (26u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL14 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL14_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL14 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL14_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL14 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL14_OFF (28u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL15 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL15_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL15 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL15_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL15 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL15_OFF (30u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL1 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL1 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL1 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL2 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL2 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL2 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL2_OFF (4u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL3 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL3 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL3 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL3_OFF (6u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL4 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL4 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL4 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL4_OFF (8u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL5 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL5 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL5 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL5_OFF (10u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL6 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL6 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL6 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL6_OFF (12u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL7 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL7 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL7 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL7_OFF (14u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL8 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL8_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL8 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL8_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL8 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL8_OFF (16u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL9 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL9_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL9 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL9_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL9 */
+#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL9_OFF (18u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH0SEL */
+#define IFX_GTM_INOUTSEL_TIM_INSEL_CH0SEL_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH0SEL */
+#define IFX_GTM_INOUTSEL_TIM_INSEL_CH0SEL_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH0SEL */
+#define IFX_GTM_INOUTSEL_TIM_INSEL_CH0SEL_OFF (0u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH1SEL */
+#define IFX_GTM_INOUTSEL_TIM_INSEL_CH1SEL_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH1SEL */
+#define IFX_GTM_INOUTSEL_TIM_INSEL_CH1SEL_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH1SEL */
+#define IFX_GTM_INOUTSEL_TIM_INSEL_CH1SEL_OFF (4u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH2SEL */
+#define IFX_GTM_INOUTSEL_TIM_INSEL_CH2SEL_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH2SEL */
+#define IFX_GTM_INOUTSEL_TIM_INSEL_CH2SEL_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH2SEL */
+#define IFX_GTM_INOUTSEL_TIM_INSEL_CH2SEL_OFF (8u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH3SEL */
+#define IFX_GTM_INOUTSEL_TIM_INSEL_CH3SEL_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH3SEL */
+#define IFX_GTM_INOUTSEL_TIM_INSEL_CH3SEL_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH3SEL */
+#define IFX_GTM_INOUTSEL_TIM_INSEL_CH3SEL_OFF (12u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH4SEL */
+#define IFX_GTM_INOUTSEL_TIM_INSEL_CH4SEL_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH4SEL */
+#define IFX_GTM_INOUTSEL_TIM_INSEL_CH4SEL_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH4SEL */
+#define IFX_GTM_INOUTSEL_TIM_INSEL_CH4SEL_OFF (16u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH5SEL */
+#define IFX_GTM_INOUTSEL_TIM_INSEL_CH5SEL_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH5SEL */
+#define IFX_GTM_INOUTSEL_TIM_INSEL_CH5SEL_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH5SEL */
+#define IFX_GTM_INOUTSEL_TIM_INSEL_CH5SEL_OFF (20u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH6SEL */
+#define IFX_GTM_INOUTSEL_TIM_INSEL_CH6SEL_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH6SEL */
+#define IFX_GTM_INOUTSEL_TIM_INSEL_CH6SEL_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH6SEL */
+#define IFX_GTM_INOUTSEL_TIM_INSEL_CH6SEL_OFF (24u)
+
+/** \brief Length for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH7SEL */
+#define IFX_GTM_INOUTSEL_TIM_INSEL_CH7SEL_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH7SEL */
+#define IFX_GTM_INOUTSEL_TIM_INSEL_CH7SEL_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH7SEL */
+#define IFX_GTM_INOUTSEL_TIM_INSEL_CH7SEL_OFF (28u)
+
+/** \brief Length for Ifx_GTM_IRQ_EN_Bits.AEI_IM_ADDR_IRQ_EN */
+#define IFX_GTM_IRQ_EN_AEI_IM_ADDR_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_IRQ_EN_Bits.AEI_IM_ADDR_IRQ_EN */
+#define IFX_GTM_IRQ_EN_AEI_IM_ADDR_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_IRQ_EN_Bits.AEI_IM_ADDR_IRQ_EN */
+#define IFX_GTM_IRQ_EN_AEI_IM_ADDR_IRQ_EN_OFF (2u)
+
+/** \brief Length for Ifx_GTM_IRQ_EN_Bits.AEI_TO_XPT_IRQ_EN */
+#define IFX_GTM_IRQ_EN_AEI_TO_XPT_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_IRQ_EN_Bits.AEI_TO_XPT_IRQ_EN */
+#define IFX_GTM_IRQ_EN_AEI_TO_XPT_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_IRQ_EN_Bits.AEI_TO_XPT_IRQ_EN */
+#define IFX_GTM_IRQ_EN_AEI_TO_XPT_IRQ_EN_OFF (0u)
+
+/** \brief Length for Ifx_GTM_IRQ_EN_Bits.AEI_USP_ADDR_IRQ_EN */
+#define IFX_GTM_IRQ_EN_AEI_USP_ADDR_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_IRQ_EN_Bits.AEI_USP_ADDR_IRQ_EN */
+#define IFX_GTM_IRQ_EN_AEI_USP_ADDR_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_IRQ_EN_Bits.AEI_USP_ADDR_IRQ_EN */
+#define IFX_GTM_IRQ_EN_AEI_USP_ADDR_IRQ_EN_OFF (1u)
+
+/** \brief Length for Ifx_GTM_IRQ_EN_Bits.AEI_USP_BE_IRQ_EN */
+#define IFX_GTM_IRQ_EN_AEI_USP_BE_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_IRQ_EN_Bits.AEI_USP_BE_IRQ_EN */
+#define IFX_GTM_IRQ_EN_AEI_USP_BE_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_IRQ_EN_Bits.AEI_USP_BE_IRQ_EN */
+#define IFX_GTM_IRQ_EN_AEI_USP_BE_IRQ_EN_OFF (3u)
+
+/** \brief Length for Ifx_GTM_IRQ_FORCINT_Bits.TRG_AEI_IM_ADDR */
+#define IFX_GTM_IRQ_FORCINT_TRG_AEI_IM_ADDR_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_IRQ_FORCINT_Bits.TRG_AEI_IM_ADDR */
+#define IFX_GTM_IRQ_FORCINT_TRG_AEI_IM_ADDR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_IRQ_FORCINT_Bits.TRG_AEI_IM_ADDR */
+#define IFX_GTM_IRQ_FORCINT_TRG_AEI_IM_ADDR_OFF (2u)
+
+/** \brief Length for Ifx_GTM_IRQ_FORCINT_Bits.TRG_AEI_TO_XPT */
+#define IFX_GTM_IRQ_FORCINT_TRG_AEI_TO_XPT_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_IRQ_FORCINT_Bits.TRG_AEI_TO_XPT */
+#define IFX_GTM_IRQ_FORCINT_TRG_AEI_TO_XPT_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_IRQ_FORCINT_Bits.TRG_AEI_TO_XPT */
+#define IFX_GTM_IRQ_FORCINT_TRG_AEI_TO_XPT_OFF (0u)
+
+/** \brief Length for Ifx_GTM_IRQ_FORCINT_Bits.TRG_AEI_USP_ADDR */
+#define IFX_GTM_IRQ_FORCINT_TRG_AEI_USP_ADDR_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_IRQ_FORCINT_Bits.TRG_AEI_USP_ADDR */
+#define IFX_GTM_IRQ_FORCINT_TRG_AEI_USP_ADDR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_IRQ_FORCINT_Bits.TRG_AEI_USP_ADDR */
+#define IFX_GTM_IRQ_FORCINT_TRG_AEI_USP_ADDR_OFF (1u)
+
+/** \brief Length for Ifx_GTM_IRQ_FORCINT_Bits.TRG_AEI_USP_BE */
+#define IFX_GTM_IRQ_FORCINT_TRG_AEI_USP_BE_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_IRQ_FORCINT_Bits.TRG_AEI_USP_BE */
+#define IFX_GTM_IRQ_FORCINT_TRG_AEI_USP_BE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_IRQ_FORCINT_Bits.TRG_AEI_USP_BE */
+#define IFX_GTM_IRQ_FORCINT_TRG_AEI_USP_BE_OFF (3u)
+
+/** \brief Length for Ifx_GTM_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_IRQ_MODE_IRQ_MODE_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_IRQ_MODE_IRQ_MODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_IRQ_MODE_IRQ_MODE_OFF (0u)
+
+/** \brief Length for Ifx_GTM_IRQ_NOTIFY_Bits.AEI_IM_ADDR */
+#define IFX_GTM_IRQ_NOTIFY_AEI_IM_ADDR_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_IRQ_NOTIFY_Bits.AEI_IM_ADDR */
+#define IFX_GTM_IRQ_NOTIFY_AEI_IM_ADDR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_IRQ_NOTIFY_Bits.AEI_IM_ADDR */
+#define IFX_GTM_IRQ_NOTIFY_AEI_IM_ADDR_OFF (2u)
+
+/** \brief Length for Ifx_GTM_IRQ_NOTIFY_Bits.AEI_TO_XPT */
+#define IFX_GTM_IRQ_NOTIFY_AEI_TO_XPT_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_IRQ_NOTIFY_Bits.AEI_TO_XPT */
+#define IFX_GTM_IRQ_NOTIFY_AEI_TO_XPT_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_IRQ_NOTIFY_Bits.AEI_TO_XPT */
+#define IFX_GTM_IRQ_NOTIFY_AEI_TO_XPT_OFF (0u)
+
+/** \brief Length for Ifx_GTM_IRQ_NOTIFY_Bits.AEI_USP_ADDR */
+#define IFX_GTM_IRQ_NOTIFY_AEI_USP_ADDR_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_IRQ_NOTIFY_Bits.AEI_USP_ADDR */
+#define IFX_GTM_IRQ_NOTIFY_AEI_USP_ADDR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_IRQ_NOTIFY_Bits.AEI_USP_ADDR */
+#define IFX_GTM_IRQ_NOTIFY_AEI_USP_ADDR_OFF (1u)
+
+/** \brief Length for Ifx_GTM_IRQ_NOTIFY_Bits.AEI_USP_BE */
+#define IFX_GTM_IRQ_NOTIFY_AEI_USP_BE_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_IRQ_NOTIFY_Bits.AEI_USP_BE */
+#define IFX_GTM_IRQ_NOTIFY_AEI_USP_BE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_IRQ_NOTIFY_Bits.AEI_USP_BE */
+#define IFX_GTM_IRQ_NOTIFY_AEI_USP_BE_OFF (3u)
+
+/** \brief Length for Ifx_GTM_KRST0_Bits.RST */
+#define IFX_GTM_KRST0_RST_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_KRST0_Bits.RST */
+#define IFX_GTM_KRST0_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_KRST0_Bits.RST */
+#define IFX_GTM_KRST0_RST_OFF (0u)
+
+/** \brief Length for Ifx_GTM_KRST0_Bits.RSTSTAT */
+#define IFX_GTM_KRST0_RSTSTAT_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_KRST0_Bits.RSTSTAT */
+#define IFX_GTM_KRST0_RSTSTAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_KRST0_Bits.RSTSTAT */
+#define IFX_GTM_KRST0_RSTSTAT_OFF (1u)
+
+/** \brief Length for Ifx_GTM_KRST1_Bits.RST */
+#define IFX_GTM_KRST1_RST_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_KRST1_Bits.RST */
+#define IFX_GTM_KRST1_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_KRST1_Bits.RST */
+#define IFX_GTM_KRST1_RST_OFF (0u)
+
+/** \brief Length for Ifx_GTM_KRSTCLR_Bits.CLR */
+#define IFX_GTM_KRSTCLR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_KRSTCLR_Bits.CLR */
+#define IFX_GTM_KRSTCLR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_KRSTCLR_Bits.CLR */
+#define IFX_GTM_KRSTCLR_CLR_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MAP_CTRL_Bits.LSEL */
+#define IFX_GTM_MAP_CTRL_LSEL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MAP_CTRL_Bits.LSEL */
+#define IFX_GTM_MAP_CTRL_LSEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MAP_CTRL_Bits.LSEL */
+#define IFX_GTM_MAP_CTRL_LSEL_OFF (4u)
+
+/** \brief Length for Ifx_GTM_MAP_CTRL_Bits.SSL */
+#define IFX_GTM_MAP_CTRL_SSL_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_MAP_CTRL_Bits.SSL */
+#define IFX_GTM_MAP_CTRL_SSL_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_MAP_CTRL_Bits.SSL */
+#define IFX_GTM_MAP_CTRL_SSL_OFF (1u)
+
+/** \brief Length for Ifx_GTM_MAP_CTRL_Bits.TSEL */
+#define IFX_GTM_MAP_CTRL_TSEL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MAP_CTRL_Bits.TSEL */
+#define IFX_GTM_MAP_CTRL_TSEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MAP_CTRL_Bits.TSEL */
+#define IFX_GTM_MAP_CTRL_TSEL_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MAP_CTRL_Bits.TSPP0_DLD */
+#define IFX_GTM_MAP_CTRL_TSPP0_DLD_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MAP_CTRL_Bits.TSPP0_DLD */
+#define IFX_GTM_MAP_CTRL_TSPP0_DLD_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MAP_CTRL_Bits.TSPP0_DLD */
+#define IFX_GTM_MAP_CTRL_TSPP0_DLD_OFF (17u)
+
+/** \brief Length for Ifx_GTM_MAP_CTRL_Bits.TSPP0_EN */
+#define IFX_GTM_MAP_CTRL_TSPP0_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MAP_CTRL_Bits.TSPP0_EN */
+#define IFX_GTM_MAP_CTRL_TSPP0_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MAP_CTRL_Bits.TSPP0_EN */
+#define IFX_GTM_MAP_CTRL_TSPP0_EN_OFF (16u)
+
+/** \brief Length for Ifx_GTM_MAP_CTRL_Bits.TSPP0_I0V */
+#define IFX_GTM_MAP_CTRL_TSPP0_I0V_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MAP_CTRL_Bits.TSPP0_I0V */
+#define IFX_GTM_MAP_CTRL_TSPP0_I0V_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MAP_CTRL_Bits.TSPP0_I0V */
+#define IFX_GTM_MAP_CTRL_TSPP0_I0V_OFF (20u)
+
+/** \brief Length for Ifx_GTM_MAP_CTRL_Bits.TSPP0_I1V */
+#define IFX_GTM_MAP_CTRL_TSPP0_I1V_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MAP_CTRL_Bits.TSPP0_I1V */
+#define IFX_GTM_MAP_CTRL_TSPP0_I1V_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MAP_CTRL_Bits.TSPP0_I1V */
+#define IFX_GTM_MAP_CTRL_TSPP0_I1V_OFF (21u)
+
+/** \brief Length for Ifx_GTM_MAP_CTRL_Bits.TSPP0_I2V */
+#define IFX_GTM_MAP_CTRL_TSPP0_I2V_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MAP_CTRL_Bits.TSPP0_I2V */
+#define IFX_GTM_MAP_CTRL_TSPP0_I2V_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MAP_CTRL_Bits.TSPP0_I2V */
+#define IFX_GTM_MAP_CTRL_TSPP0_I2V_OFF (22u)
+
+/** \brief Length for Ifx_GTM_MAP_CTRL_Bits.TSPP1_DLD */
+#define IFX_GTM_MAP_CTRL_TSPP1_DLD_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MAP_CTRL_Bits.TSPP1_DLD */
+#define IFX_GTM_MAP_CTRL_TSPP1_DLD_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MAP_CTRL_Bits.TSPP1_DLD */
+#define IFX_GTM_MAP_CTRL_TSPP1_DLD_OFF (25u)
+
+/** \brief Length for Ifx_GTM_MAP_CTRL_Bits.TSPP1_EN */
+#define IFX_GTM_MAP_CTRL_TSPP1_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MAP_CTRL_Bits.TSPP1_EN */
+#define IFX_GTM_MAP_CTRL_TSPP1_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MAP_CTRL_Bits.TSPP1_EN */
+#define IFX_GTM_MAP_CTRL_TSPP1_EN_OFF (24u)
+
+/** \brief Length for Ifx_GTM_MAP_CTRL_Bits.TSPP1_I0V */
+#define IFX_GTM_MAP_CTRL_TSPP1_I0V_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MAP_CTRL_Bits.TSPP1_I0V */
+#define IFX_GTM_MAP_CTRL_TSPP1_I0V_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MAP_CTRL_Bits.TSPP1_I0V */
+#define IFX_GTM_MAP_CTRL_TSPP1_I0V_OFF (28u)
+
+/** \brief Length for Ifx_GTM_MAP_CTRL_Bits.TSPP1_I1V */
+#define IFX_GTM_MAP_CTRL_TSPP1_I1V_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MAP_CTRL_Bits.TSPP1_I1V */
+#define IFX_GTM_MAP_CTRL_TSPP1_I1V_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MAP_CTRL_Bits.TSPP1_I1V */
+#define IFX_GTM_MAP_CTRL_TSPP1_I1V_OFF (29u)
+
+/** \brief Length for Ifx_GTM_MAP_CTRL_Bits.TSPP1_I2V */
+#define IFX_GTM_MAP_CTRL_TSPP1_I2V_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MAP_CTRL_Bits.TSPP1_I2V */
+#define IFX_GTM_MAP_CTRL_TSPP1_I2V_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MAP_CTRL_Bits.TSPP1_I2V */
+#define IFX_GTM_MAP_CTRL_TSPP1_I2V_OFF (30u)
+
+/** \brief Length for Ifx_GTM_MCFG_CTRL_Bits.MEM0 */
+#define IFX_GTM_MCFG_CTRL_MEM0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MCFG_CTRL_Bits.MEM0 */
+#define IFX_GTM_MCFG_CTRL_MEM0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MCFG_CTRL_Bits.MEM0 */
+#define IFX_GTM_MCFG_CTRL_MEM0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MCFG_CTRL_Bits.MEM1 */
+#define IFX_GTM_MCFG_CTRL_MEM1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MCFG_CTRL_Bits.MEM1 */
+#define IFX_GTM_MCFG_CTRL_MEM1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MCFG_CTRL_Bits.MEM1 */
+#define IFX_GTM_MCFG_CTRL_MEM1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_MCFG_CTRL_Bits.MEM2 */
+#define IFX_GTM_MCFG_CTRL_MEM2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MCFG_CTRL_Bits.MEM2 */
+#define IFX_GTM_MCFG_CTRL_MEM2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MCFG_CTRL_Bits.MEM2 */
+#define IFX_GTM_MCFG_CTRL_MEM2_OFF (4u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG0 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG0 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG0 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG10 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG10_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG10 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG10_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG10 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG10_OFF (10u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG11 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG11_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG11 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG11_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG11 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG11_OFF (11u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG12 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG12_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG12 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG12_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG12 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG12_OFF (12u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG13 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG13_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG13 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG13_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG13 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG13_OFF (13u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG14 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG14_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG14 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG14_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG14 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG14_OFF (14u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG15 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG15_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG15 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG15_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG15 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG15_OFF (15u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG1 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG1 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG1 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG1_OFF (1u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG2 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG2 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG2 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG2_OFF (2u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG3 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG3 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG3 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG3_OFF (3u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG4 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG4 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG4 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG4_OFF (4u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG5 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG5 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG5 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG5_OFF (5u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG6 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG6 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG6 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG6_OFF (6u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG7 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG7 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG7 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG7_OFF (7u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG8 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG8_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG8 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG8_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG8 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG8_OFF (8u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG9 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG9_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG9 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG9_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG9 */
+#define IFX_GTM_MCS_CH0_CTRG_TRG9_OFF (9u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG0 */
+#define IFX_GTM_MCS_CH0_STRG_TRG0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG0 */
+#define IFX_GTM_MCS_CH0_STRG_TRG0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG0 */
+#define IFX_GTM_MCS_CH0_STRG_TRG0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG10 */
+#define IFX_GTM_MCS_CH0_STRG_TRG10_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG10 */
+#define IFX_GTM_MCS_CH0_STRG_TRG10_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG10 */
+#define IFX_GTM_MCS_CH0_STRG_TRG10_OFF (10u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG11 */
+#define IFX_GTM_MCS_CH0_STRG_TRG11_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG11 */
+#define IFX_GTM_MCS_CH0_STRG_TRG11_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG11 */
+#define IFX_GTM_MCS_CH0_STRG_TRG11_OFF (11u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG12 */
+#define IFX_GTM_MCS_CH0_STRG_TRG12_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG12 */
+#define IFX_GTM_MCS_CH0_STRG_TRG12_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG12 */
+#define IFX_GTM_MCS_CH0_STRG_TRG12_OFF (12u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG13 */
+#define IFX_GTM_MCS_CH0_STRG_TRG13_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG13 */
+#define IFX_GTM_MCS_CH0_STRG_TRG13_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG13 */
+#define IFX_GTM_MCS_CH0_STRG_TRG13_OFF (13u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG14 */
+#define IFX_GTM_MCS_CH0_STRG_TRG14_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG14 */
+#define IFX_GTM_MCS_CH0_STRG_TRG14_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG14 */
+#define IFX_GTM_MCS_CH0_STRG_TRG14_OFF (14u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG15 */
+#define IFX_GTM_MCS_CH0_STRG_TRG15_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG15 */
+#define IFX_GTM_MCS_CH0_STRG_TRG15_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG15 */
+#define IFX_GTM_MCS_CH0_STRG_TRG15_OFF (15u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG1 */
+#define IFX_GTM_MCS_CH0_STRG_TRG1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG1 */
+#define IFX_GTM_MCS_CH0_STRG_TRG1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG1 */
+#define IFX_GTM_MCS_CH0_STRG_TRG1_OFF (1u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG2 */
+#define IFX_GTM_MCS_CH0_STRG_TRG2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG2 */
+#define IFX_GTM_MCS_CH0_STRG_TRG2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG2 */
+#define IFX_GTM_MCS_CH0_STRG_TRG2_OFF (2u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG3 */
+#define IFX_GTM_MCS_CH0_STRG_TRG3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG3 */
+#define IFX_GTM_MCS_CH0_STRG_TRG3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG3 */
+#define IFX_GTM_MCS_CH0_STRG_TRG3_OFF (3u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG4 */
+#define IFX_GTM_MCS_CH0_STRG_TRG4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG4 */
+#define IFX_GTM_MCS_CH0_STRG_TRG4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG4 */
+#define IFX_GTM_MCS_CH0_STRG_TRG4_OFF (4u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG5 */
+#define IFX_GTM_MCS_CH0_STRG_TRG5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG5 */
+#define IFX_GTM_MCS_CH0_STRG_TRG5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG5 */
+#define IFX_GTM_MCS_CH0_STRG_TRG5_OFF (5u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG6 */
+#define IFX_GTM_MCS_CH0_STRG_TRG6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG6 */
+#define IFX_GTM_MCS_CH0_STRG_TRG6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG6 */
+#define IFX_GTM_MCS_CH0_STRG_TRG6_OFF (6u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG7 */
+#define IFX_GTM_MCS_CH0_STRG_TRG7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG7 */
+#define IFX_GTM_MCS_CH0_STRG_TRG7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG7 */
+#define IFX_GTM_MCS_CH0_STRG_TRG7_OFF (7u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG8 */
+#define IFX_GTM_MCS_CH0_STRG_TRG8_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG8 */
+#define IFX_GTM_MCS_CH0_STRG_TRG8_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG8 */
+#define IFX_GTM_MCS_CH0_STRG_TRG8_OFF (8u)
+
+/** \brief Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG9 */
+#define IFX_GTM_MCS_CH0_STRG_TRG9_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG9 */
+#define IFX_GTM_MCS_CH0_STRG_TRG9_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG9 */
+#define IFX_GTM_MCS_CH0_STRG_TRG9_OFF (9u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_ACB_Bits.ACB0 */
+#define IFX_GTM_MCS_CH_ACB_ACB0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_ACB_Bits.ACB0 */
+#define IFX_GTM_MCS_CH_ACB_ACB0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_ACB_Bits.ACB0 */
+#define IFX_GTM_MCS_CH_ACB_ACB0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_ACB_Bits.ACB1 */
+#define IFX_GTM_MCS_CH_ACB_ACB1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_ACB_Bits.ACB1 */
+#define IFX_GTM_MCS_CH_ACB_ACB1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_ACB_Bits.ACB1 */
+#define IFX_GTM_MCS_CH_ACB_ACB1_OFF (1u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_ACB_Bits.ACB2 */
+#define IFX_GTM_MCS_CH_ACB_ACB2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_ACB_Bits.ACB2 */
+#define IFX_GTM_MCS_CH_ACB_ACB2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_ACB_Bits.ACB2 */
+#define IFX_GTM_MCS_CH_ACB_ACB2_OFF (2u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_ACB_Bits.ACB3 */
+#define IFX_GTM_MCS_CH_ACB_ACB3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_ACB_Bits.ACB3 */
+#define IFX_GTM_MCS_CH_ACB_ACB3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_ACB_Bits.ACB3 */
+#define IFX_GTM_MCS_CH_ACB_ACB3_OFF (3u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_ACB_Bits.ACB4 */
+#define IFX_GTM_MCS_CH_ACB_ACB4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_ACB_Bits.ACB4 */
+#define IFX_GTM_MCS_CH_ACB_ACB4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_ACB_Bits.ACB4 */
+#define IFX_GTM_MCS_CH_ACB_ACB4_OFF (4u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_CTRL_Bits.CAT */
+#define IFX_GTM_MCS_CH_CTRL_CAT_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_CTRL_Bits.CAT */
+#define IFX_GTM_MCS_CH_CTRL_CAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_CTRL_Bits.CAT */
+#define IFX_GTM_MCS_CH_CTRL_CAT_OFF (8u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_CTRL_Bits.CWT */
+#define IFX_GTM_MCS_CH_CTRL_CWT_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_CTRL_Bits.CWT */
+#define IFX_GTM_MCS_CH_CTRL_CWT_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_CTRL_Bits.CWT */
+#define IFX_GTM_MCS_CH_CTRL_CWT_OFF (9u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_CTRL_Bits.CY */
+#define IFX_GTM_MCS_CH_CTRL_CY_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_CTRL_Bits.CY */
+#define IFX_GTM_MCS_CH_CTRL_CY_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_CTRL_Bits.CY */
+#define IFX_GTM_MCS_CH_CTRL_CY_OFF (4u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_CTRL_Bits.EN */
+#define IFX_GTM_MCS_CH_CTRL_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_CTRL_Bits.EN */
+#define IFX_GTM_MCS_CH_CTRL_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_CTRL_Bits.EN */
+#define IFX_GTM_MCS_CH_CTRL_EN_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_CTRL_Bits.ERR */
+#define IFX_GTM_MCS_CH_CTRL_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_CTRL_Bits.ERR */
+#define IFX_GTM_MCS_CH_CTRL_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_CTRL_Bits.ERR */
+#define IFX_GTM_MCS_CH_CTRL_ERR_OFF (2u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_CTRL_Bits.IRQ */
+#define IFX_GTM_MCS_CH_CTRL_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_CTRL_Bits.IRQ */
+#define IFX_GTM_MCS_CH_CTRL_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_CTRL_Bits.IRQ */
+#define IFX_GTM_MCS_CH_CTRL_IRQ_OFF (1u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_CTRL_Bits.N */
+#define IFX_GTM_MCS_CH_CTRL_N_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_CTRL_Bits.N */
+#define IFX_GTM_MCS_CH_CTRL_N_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_CTRL_Bits.N */
+#define IFX_GTM_MCS_CH_CTRL_N_OFF (7u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_CTRL_Bits.SP_CNT */
+#define IFX_GTM_MCS_CH_CTRL_SP_CNT_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_CTRL_Bits.SP_CNT */
+#define IFX_GTM_MCS_CH_CTRL_SP_CNT_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_CTRL_Bits.SP_CNT */
+#define IFX_GTM_MCS_CH_CTRL_SP_CNT_OFF (16u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_CTRL_Bits.V */
+#define IFX_GTM_MCS_CH_CTRL_V_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_CTRL_Bits.V */
+#define IFX_GTM_MCS_CH_CTRL_V_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_CTRL_Bits.V */
+#define IFX_GTM_MCS_CH_CTRL_V_OFF (6u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_CTRL_Bits.Z */
+#define IFX_GTM_MCS_CH_CTRL_Z_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_CTRL_Bits.Z */
+#define IFX_GTM_MCS_CH_CTRL_Z_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_CTRL_Bits.Z */
+#define IFX_GTM_MCS_CH_CTRL_Z_OFF (5u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_EIRQ_EN_Bits.MCS_EIRQ_EN */
+#define IFX_GTM_MCS_CH_EIRQ_EN_MCS_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_EIRQ_EN_Bits.MCS_EIRQ_EN */
+#define IFX_GTM_MCS_CH_EIRQ_EN_MCS_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_EIRQ_EN_Bits.MCS_EIRQ_EN */
+#define IFX_GTM_MCS_CH_EIRQ_EN_MCS_EIRQ_EN_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_EIRQ_EN_Bits.MEM_ERR_EIRQ_EN */
+#define IFX_GTM_MCS_CH_EIRQ_EN_MEM_ERR_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_EIRQ_EN_Bits.MEM_ERR_EIRQ_EN */
+#define IFX_GTM_MCS_CH_EIRQ_EN_MEM_ERR_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_EIRQ_EN_Bits.MEM_ERR_EIRQ_EN */
+#define IFX_GTM_MCS_CH_EIRQ_EN_MEM_ERR_EIRQ_EN_OFF (2u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_EIRQ_EN_Bits.STK_ERR_EIRQ_EN */
+#define IFX_GTM_MCS_CH_EIRQ_EN_STK_ERR_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_EIRQ_EN_Bits.STK_ERR_EIRQ_EN */
+#define IFX_GTM_MCS_CH_EIRQ_EN_STK_ERR_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_EIRQ_EN_Bits.STK_ERR_EIRQ_EN */
+#define IFX_GTM_MCS_CH_EIRQ_EN_STK_ERR_EIRQ_EN_OFF (1u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_IRQ_EN_Bits.MCS_IRQ_EN */
+#define IFX_GTM_MCS_CH_IRQ_EN_MCS_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_IRQ_EN_Bits.MCS_IRQ_EN */
+#define IFX_GTM_MCS_CH_IRQ_EN_MCS_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_IRQ_EN_Bits.MCS_IRQ_EN */
+#define IFX_GTM_MCS_CH_IRQ_EN_MCS_IRQ_EN_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_IRQ_EN_Bits.MEM_ERR_IRQ_EN */
+#define IFX_GTM_MCS_CH_IRQ_EN_MEM_ERR_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_IRQ_EN_Bits.MEM_ERR_IRQ_EN */
+#define IFX_GTM_MCS_CH_IRQ_EN_MEM_ERR_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_IRQ_EN_Bits.MEM_ERR_IRQ_EN */
+#define IFX_GTM_MCS_CH_IRQ_EN_MEM_ERR_IRQ_EN_OFF (2u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_IRQ_EN_Bits.STK_ERR_IRQ_EN */
+#define IFX_GTM_MCS_CH_IRQ_EN_STK_ERR_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_IRQ_EN_Bits.STK_ERR_IRQ_EN */
+#define IFX_GTM_MCS_CH_IRQ_EN_STK_ERR_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_IRQ_EN_Bits.STK_ERR_IRQ_EN */
+#define IFX_GTM_MCS_CH_IRQ_EN_STK_ERR_IRQ_EN_OFF (1u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_IRQ_FORCINT_Bits.TRG_MCS_IRQ */
+#define IFX_GTM_MCS_CH_IRQ_FORCINT_TRG_MCS_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_IRQ_FORCINT_Bits.TRG_MCS_IRQ */
+#define IFX_GTM_MCS_CH_IRQ_FORCINT_TRG_MCS_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_IRQ_FORCINT_Bits.TRG_MCS_IRQ */
+#define IFX_GTM_MCS_CH_IRQ_FORCINT_TRG_MCS_IRQ_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_IRQ_FORCINT_Bits.TRG_MEM_ERR_IRQ */
+#define IFX_GTM_MCS_CH_IRQ_FORCINT_TRG_MEM_ERR_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_IRQ_FORCINT_Bits.TRG_MEM_ERR_IRQ */
+#define IFX_GTM_MCS_CH_IRQ_FORCINT_TRG_MEM_ERR_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_IRQ_FORCINT_Bits.TRG_MEM_ERR_IRQ */
+#define IFX_GTM_MCS_CH_IRQ_FORCINT_TRG_MEM_ERR_IRQ_OFF (2u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_IRQ_FORCINT_Bits.TRG_STK_ERR_IRQ */
+#define IFX_GTM_MCS_CH_IRQ_FORCINT_TRG_STK_ERR_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_IRQ_FORCINT_Bits.TRG_STK_ERR_IRQ */
+#define IFX_GTM_MCS_CH_IRQ_FORCINT_TRG_STK_ERR_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_IRQ_FORCINT_Bits.TRG_STK_ERR_IRQ */
+#define IFX_GTM_MCS_CH_IRQ_FORCINT_TRG_STK_ERR_IRQ_OFF (1u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_MCS_CH_IRQ_MODE_IRQ_MODE_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_MCS_CH_IRQ_MODE_IRQ_MODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_MCS_CH_IRQ_MODE_IRQ_MODE_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_IRQ_NOTIFY_Bits.MCS_IRQ */
+#define IFX_GTM_MCS_CH_IRQ_NOTIFY_MCS_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_IRQ_NOTIFY_Bits.MCS_IRQ */
+#define IFX_GTM_MCS_CH_IRQ_NOTIFY_MCS_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_IRQ_NOTIFY_Bits.MCS_IRQ */
+#define IFX_GTM_MCS_CH_IRQ_NOTIFY_MCS_IRQ_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_IRQ_NOTIFY_Bits.MEM_ERR_IRQ */
+#define IFX_GTM_MCS_CH_IRQ_NOTIFY_MEM_ERR_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_IRQ_NOTIFY_Bits.MEM_ERR_IRQ */
+#define IFX_GTM_MCS_CH_IRQ_NOTIFY_MEM_ERR_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_IRQ_NOTIFY_Bits.MEM_ERR_IRQ */
+#define IFX_GTM_MCS_CH_IRQ_NOTIFY_MEM_ERR_IRQ_OFF (2u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_IRQ_NOTIFY_Bits.STK_ERR_IRQ */
+#define IFX_GTM_MCS_CH_IRQ_NOTIFY_STK_ERR_IRQ_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_IRQ_NOTIFY_Bits.STK_ERR_IRQ */
+#define IFX_GTM_MCS_CH_IRQ_NOTIFY_STK_ERR_IRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_IRQ_NOTIFY_Bits.STK_ERR_IRQ */
+#define IFX_GTM_MCS_CH_IRQ_NOTIFY_STK_ERR_IRQ_OFF (1u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_PC_Bits.PC */
+#define IFX_GTM_MCS_CH_PC_PC_LEN (14u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_PC_Bits.PC */
+#define IFX_GTM_MCS_CH_PC_PC_MSK (0x3fffu)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_PC_Bits.PC */
+#define IFX_GTM_MCS_CH_PC_PC_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_R0_Bits.DATA */
+#define IFX_GTM_MCS_CH_R0_DATA_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_R0_Bits.DATA */
+#define IFX_GTM_MCS_CH_R0_DATA_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_R0_Bits.DATA */
+#define IFX_GTM_MCS_CH_R0_DATA_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_R1_Bits.DATA */
+#define IFX_GTM_MCS_CH_R1_DATA_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_R1_Bits.DATA */
+#define IFX_GTM_MCS_CH_R1_DATA_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_R1_Bits.DATA */
+#define IFX_GTM_MCS_CH_R1_DATA_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_R2_Bits.DATA */
+#define IFX_GTM_MCS_CH_R2_DATA_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_R2_Bits.DATA */
+#define IFX_GTM_MCS_CH_R2_DATA_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_R2_Bits.DATA */
+#define IFX_GTM_MCS_CH_R2_DATA_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_R3_Bits.DATA */
+#define IFX_GTM_MCS_CH_R3_DATA_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_R3_Bits.DATA */
+#define IFX_GTM_MCS_CH_R3_DATA_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_R3_Bits.DATA */
+#define IFX_GTM_MCS_CH_R3_DATA_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_R4_Bits.DATA */
+#define IFX_GTM_MCS_CH_R4_DATA_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_R4_Bits.DATA */
+#define IFX_GTM_MCS_CH_R4_DATA_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_R4_Bits.DATA */
+#define IFX_GTM_MCS_CH_R4_DATA_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_R5_Bits.DATA */
+#define IFX_GTM_MCS_CH_R5_DATA_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_R5_Bits.DATA */
+#define IFX_GTM_MCS_CH_R5_DATA_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_R5_Bits.DATA */
+#define IFX_GTM_MCS_CH_R5_DATA_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_R6_Bits.DATA */
+#define IFX_GTM_MCS_CH_R6_DATA_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_R6_Bits.DATA */
+#define IFX_GTM_MCS_CH_R6_DATA_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_R6_Bits.DATA */
+#define IFX_GTM_MCS_CH_R6_DATA_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MCS_CH_R7_Bits.DATA */
+#define IFX_GTM_MCS_CH_R7_DATA_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_MCS_CH_R7_Bits.DATA */
+#define IFX_GTM_MCS_CH_R7_DATA_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_MCS_CH_R7_Bits.DATA */
+#define IFX_GTM_MCS_CH_R7_DATA_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MCS_CTRL_Bits.HLT_SP_OFL */
+#define IFX_GTM_MCS_CTRL_HLT_SP_OFL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CTRL_Bits.HLT_SP_OFL */
+#define IFX_GTM_MCS_CTRL_HLT_SP_OFL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CTRL_Bits.HLT_SP_OFL */
+#define IFX_GTM_MCS_CTRL_HLT_SP_OFL_OFF (1u)
+
+/** \brief Length for Ifx_GTM_MCS_CTRL_Bits.RAM_RST */
+#define IFX_GTM_MCS_CTRL_RAM_RST_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CTRL_Bits.RAM_RST */
+#define IFX_GTM_MCS_CTRL_RAM_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CTRL_Bits.RAM_RST */
+#define IFX_GTM_MCS_CTRL_RAM_RST_OFF (16u)
+
+/** \brief Length for Ifx_GTM_MCS_CTRL_Bits.SCHED */
+#define IFX_GTM_MCS_CTRL_SCHED_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_CTRL_Bits.SCHED */
+#define IFX_GTM_MCS_CTRL_SCHED_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_CTRL_Bits.SCHED */
+#define IFX_GTM_MCS_CTRL_SCHED_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MCS_ERR_Bits.ERR0 */
+#define IFX_GTM_MCS_ERR_ERR0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_ERR_Bits.ERR0 */
+#define IFX_GTM_MCS_ERR_ERR0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_ERR_Bits.ERR0 */
+#define IFX_GTM_MCS_ERR_ERR0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MCS_ERR_Bits.ERR1 */
+#define IFX_GTM_MCS_ERR_ERR1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_ERR_Bits.ERR1 */
+#define IFX_GTM_MCS_ERR_ERR1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_ERR_Bits.ERR1 */
+#define IFX_GTM_MCS_ERR_ERR1_OFF (1u)
+
+/** \brief Length for Ifx_GTM_MCS_ERR_Bits.ERR2 */
+#define IFX_GTM_MCS_ERR_ERR2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_ERR_Bits.ERR2 */
+#define IFX_GTM_MCS_ERR_ERR2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_ERR_Bits.ERR2 */
+#define IFX_GTM_MCS_ERR_ERR2_OFF (2u)
+
+/** \brief Length for Ifx_GTM_MCS_ERR_Bits.ERR3 */
+#define IFX_GTM_MCS_ERR_ERR3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_ERR_Bits.ERR3 */
+#define IFX_GTM_MCS_ERR_ERR3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_ERR_Bits.ERR3 */
+#define IFX_GTM_MCS_ERR_ERR3_OFF (3u)
+
+/** \brief Length for Ifx_GTM_MCS_ERR_Bits.ERR4 */
+#define IFX_GTM_MCS_ERR_ERR4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_ERR_Bits.ERR4 */
+#define IFX_GTM_MCS_ERR_ERR4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_ERR_Bits.ERR4 */
+#define IFX_GTM_MCS_ERR_ERR4_OFF (4u)
+
+/** \brief Length for Ifx_GTM_MCS_ERR_Bits.ERR5 */
+#define IFX_GTM_MCS_ERR_ERR5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_ERR_Bits.ERR5 */
+#define IFX_GTM_MCS_ERR_ERR5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_ERR_Bits.ERR5 */
+#define IFX_GTM_MCS_ERR_ERR5_OFF (5u)
+
+/** \brief Length for Ifx_GTM_MCS_ERR_Bits.ERR6 */
+#define IFX_GTM_MCS_ERR_ERR6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_ERR_Bits.ERR6 */
+#define IFX_GTM_MCS_ERR_ERR6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_ERR_Bits.ERR6 */
+#define IFX_GTM_MCS_ERR_ERR6_OFF (6u)
+
+/** \brief Length for Ifx_GTM_MCS_ERR_Bits.ERR7 */
+#define IFX_GTM_MCS_ERR_ERR7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_ERR_Bits.ERR7 */
+#define IFX_GTM_MCS_ERR_ERR7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_ERR_Bits.ERR7 */
+#define IFX_GTM_MCS_ERR_ERR7_OFF (7u)
+
+/** \brief Length for Ifx_GTM_MCS_RST_Bits.CAT0 */
+#define IFX_GTM_MCS_RST_CAT0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_RST_Bits.CAT0 */
+#define IFX_GTM_MCS_RST_CAT0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_RST_Bits.CAT0 */
+#define IFX_GTM_MCS_RST_CAT0_OFF (8u)
+
+/** \brief Length for Ifx_GTM_MCS_RST_Bits.CAT1 */
+#define IFX_GTM_MCS_RST_CAT1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_RST_Bits.CAT1 */
+#define IFX_GTM_MCS_RST_CAT1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_RST_Bits.CAT1 */
+#define IFX_GTM_MCS_RST_CAT1_OFF (9u)
+
+/** \brief Length for Ifx_GTM_MCS_RST_Bits.CAT2 */
+#define IFX_GTM_MCS_RST_CAT2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_RST_Bits.CAT2 */
+#define IFX_GTM_MCS_RST_CAT2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_RST_Bits.CAT2 */
+#define IFX_GTM_MCS_RST_CAT2_OFF (10u)
+
+/** \brief Length for Ifx_GTM_MCS_RST_Bits.CAT3 */
+#define IFX_GTM_MCS_RST_CAT3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_RST_Bits.CAT3 */
+#define IFX_GTM_MCS_RST_CAT3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_RST_Bits.CAT3 */
+#define IFX_GTM_MCS_RST_CAT3_OFF (11u)
+
+/** \brief Length for Ifx_GTM_MCS_RST_Bits.CAT4 */
+#define IFX_GTM_MCS_RST_CAT4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_RST_Bits.CAT4 */
+#define IFX_GTM_MCS_RST_CAT4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_RST_Bits.CAT4 */
+#define IFX_GTM_MCS_RST_CAT4_OFF (12u)
+
+/** \brief Length for Ifx_GTM_MCS_RST_Bits.CAT5 */
+#define IFX_GTM_MCS_RST_CAT5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_RST_Bits.CAT5 */
+#define IFX_GTM_MCS_RST_CAT5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_RST_Bits.CAT5 */
+#define IFX_GTM_MCS_RST_CAT5_OFF (13u)
+
+/** \brief Length for Ifx_GTM_MCS_RST_Bits.CAT6 */
+#define IFX_GTM_MCS_RST_CAT6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_RST_Bits.CAT6 */
+#define IFX_GTM_MCS_RST_CAT6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_RST_Bits.CAT6 */
+#define IFX_GTM_MCS_RST_CAT6_OFF (14u)
+
+/** \brief Length for Ifx_GTM_MCS_RST_Bits.CAT7 */
+#define IFX_GTM_MCS_RST_CAT7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_RST_Bits.CAT7 */
+#define IFX_GTM_MCS_RST_CAT7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_RST_Bits.CAT7 */
+#define IFX_GTM_MCS_RST_CAT7_OFF (15u)
+
+/** \brief Length for Ifx_GTM_MCS_RST_Bits.CWT0 */
+#define IFX_GTM_MCS_RST_CWT0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_RST_Bits.CWT0 */
+#define IFX_GTM_MCS_RST_CWT0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_RST_Bits.CWT0 */
+#define IFX_GTM_MCS_RST_CWT0_OFF (16u)
+
+/** \brief Length for Ifx_GTM_MCS_RST_Bits.CWT1 */
+#define IFX_GTM_MCS_RST_CWT1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_RST_Bits.CWT1 */
+#define IFX_GTM_MCS_RST_CWT1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_RST_Bits.CWT1 */
+#define IFX_GTM_MCS_RST_CWT1_OFF (17u)
+
+/** \brief Length for Ifx_GTM_MCS_RST_Bits.CWT2 */
+#define IFX_GTM_MCS_RST_CWT2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_RST_Bits.CWT2 */
+#define IFX_GTM_MCS_RST_CWT2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_RST_Bits.CWT2 */
+#define IFX_GTM_MCS_RST_CWT2_OFF (18u)
+
+/** \brief Length for Ifx_GTM_MCS_RST_Bits.CWT3 */
+#define IFX_GTM_MCS_RST_CWT3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_RST_Bits.CWT3 */
+#define IFX_GTM_MCS_RST_CWT3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_RST_Bits.CWT3 */
+#define IFX_GTM_MCS_RST_CWT3_OFF (19u)
+
+/** \brief Length for Ifx_GTM_MCS_RST_Bits.CWT4 */
+#define IFX_GTM_MCS_RST_CWT4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_RST_Bits.CWT4 */
+#define IFX_GTM_MCS_RST_CWT4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_RST_Bits.CWT4 */
+#define IFX_GTM_MCS_RST_CWT4_OFF (20u)
+
+/** \brief Length for Ifx_GTM_MCS_RST_Bits.CWT5 */
+#define IFX_GTM_MCS_RST_CWT5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_RST_Bits.CWT5 */
+#define IFX_GTM_MCS_RST_CWT5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_RST_Bits.CWT5 */
+#define IFX_GTM_MCS_RST_CWT5_OFF (21u)
+
+/** \brief Length for Ifx_GTM_MCS_RST_Bits.CWT6 */
+#define IFX_GTM_MCS_RST_CWT6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_RST_Bits.CWT6 */
+#define IFX_GTM_MCS_RST_CWT6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_RST_Bits.CWT6 */
+#define IFX_GTM_MCS_RST_CWT6_OFF (22u)
+
+/** \brief Length for Ifx_GTM_MCS_RST_Bits.CWT7 */
+#define IFX_GTM_MCS_RST_CWT7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_RST_Bits.CWT7 */
+#define IFX_GTM_MCS_RST_CWT7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_RST_Bits.CWT7 */
+#define IFX_GTM_MCS_RST_CWT7_OFF (23u)
+
+/** \brief Length for Ifx_GTM_MCS_RST_Bits.RST0 */
+#define IFX_GTM_MCS_RST_RST0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_RST_Bits.RST0 */
+#define IFX_GTM_MCS_RST_RST0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_RST_Bits.RST0 */
+#define IFX_GTM_MCS_RST_RST0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MCS_RST_Bits.RST1 */
+#define IFX_GTM_MCS_RST_RST1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_RST_Bits.RST1 */
+#define IFX_GTM_MCS_RST_RST1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_RST_Bits.RST1 */
+#define IFX_GTM_MCS_RST_RST1_OFF (1u)
+
+/** \brief Length for Ifx_GTM_MCS_RST_Bits.RST2 */
+#define IFX_GTM_MCS_RST_RST2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_RST_Bits.RST2 */
+#define IFX_GTM_MCS_RST_RST2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_RST_Bits.RST2 */
+#define IFX_GTM_MCS_RST_RST2_OFF (2u)
+
+/** \brief Length for Ifx_GTM_MCS_RST_Bits.RST3 */
+#define IFX_GTM_MCS_RST_RST3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_RST_Bits.RST3 */
+#define IFX_GTM_MCS_RST_RST3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_RST_Bits.RST3 */
+#define IFX_GTM_MCS_RST_RST3_OFF (3u)
+
+/** \brief Length for Ifx_GTM_MCS_RST_Bits.RST4 */
+#define IFX_GTM_MCS_RST_RST4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_RST_Bits.RST4 */
+#define IFX_GTM_MCS_RST_RST4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_RST_Bits.RST4 */
+#define IFX_GTM_MCS_RST_RST4_OFF (4u)
+
+/** \brief Length for Ifx_GTM_MCS_RST_Bits.RST5 */
+#define IFX_GTM_MCS_RST_RST5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_RST_Bits.RST5 */
+#define IFX_GTM_MCS_RST_RST5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_RST_Bits.RST5 */
+#define IFX_GTM_MCS_RST_RST5_OFF (5u)
+
+/** \brief Length for Ifx_GTM_MCS_RST_Bits.RST6 */
+#define IFX_GTM_MCS_RST_RST6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_RST_Bits.RST6 */
+#define IFX_GTM_MCS_RST_RST6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_RST_Bits.RST6 */
+#define IFX_GTM_MCS_RST_RST6_OFF (6u)
+
+/** \brief Length for Ifx_GTM_MCS_RST_Bits.RST7 */
+#define IFX_GTM_MCS_RST_RST7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCS_RST_Bits.RST7 */
+#define IFX_GTM_MCS_RST_RST7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCS_RST_Bits.RST7 */
+#define IFX_GTM_MCS_RST_RST7_OFF (7u)
+
+/** \brief Length for Ifx_GTM_MCSINTCLR_Bits.MCS000 */
+#define IFX_GTM_MCSINTCLR_MCS000_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCSINTCLR_Bits.MCS000 */
+#define IFX_GTM_MCSINTCLR_MCS000_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCSINTCLR_Bits.MCS000 */
+#define IFX_GTM_MCSINTCLR_MCS000_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MCSINTCLR_Bits.MCS001 */
+#define IFX_GTM_MCSINTCLR_MCS001_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCSINTCLR_Bits.MCS001 */
+#define IFX_GTM_MCSINTCLR_MCS001_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCSINTCLR_Bits.MCS001 */
+#define IFX_GTM_MCSINTCLR_MCS001_OFF (1u)
+
+/** \brief Length for Ifx_GTM_MCSINTCLR_Bits.MCS010 */
+#define IFX_GTM_MCSINTCLR_MCS010_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCSINTCLR_Bits.MCS010 */
+#define IFX_GTM_MCSINTCLR_MCS010_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCSINTCLR_Bits.MCS010 */
+#define IFX_GTM_MCSINTCLR_MCS010_OFF (2u)
+
+/** \brief Length for Ifx_GTM_MCSINTCLR_Bits.MCS011 */
+#define IFX_GTM_MCSINTCLR_MCS011_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCSINTCLR_Bits.MCS011 */
+#define IFX_GTM_MCSINTCLR_MCS011_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCSINTCLR_Bits.MCS011 */
+#define IFX_GTM_MCSINTCLR_MCS011_OFF (3u)
+
+/** \brief Length for Ifx_GTM_MCSINTCLR_Bits.MCS100 */
+#define IFX_GTM_MCSINTCLR_MCS100_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCSINTCLR_Bits.MCS100 */
+#define IFX_GTM_MCSINTCLR_MCS100_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCSINTCLR_Bits.MCS100 */
+#define IFX_GTM_MCSINTCLR_MCS100_OFF (4u)
+
+/** \brief Length for Ifx_GTM_MCSINTCLR_Bits.MCS101 */
+#define IFX_GTM_MCSINTCLR_MCS101_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCSINTCLR_Bits.MCS101 */
+#define IFX_GTM_MCSINTCLR_MCS101_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCSINTCLR_Bits.MCS101 */
+#define IFX_GTM_MCSINTCLR_MCS101_OFF (5u)
+
+/** \brief Length for Ifx_GTM_MCSINTCLR_Bits.MCS110 */
+#define IFX_GTM_MCSINTCLR_MCS110_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCSINTCLR_Bits.MCS110 */
+#define IFX_GTM_MCSINTCLR_MCS110_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCSINTCLR_Bits.MCS110 */
+#define IFX_GTM_MCSINTCLR_MCS110_OFF (6u)
+
+/** \brief Length for Ifx_GTM_MCSINTCLR_Bits.MCS111 */
+#define IFX_GTM_MCSINTCLR_MCS111_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCSINTCLR_Bits.MCS111 */
+#define IFX_GTM_MCSINTCLR_MCS111_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCSINTCLR_Bits.MCS111 */
+#define IFX_GTM_MCSINTCLR_MCS111_OFF (7u)
+
+/** \brief Length for Ifx_GTM_MCSINTCLR_Bits.MCS200 */
+#define IFX_GTM_MCSINTCLR_MCS200_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCSINTCLR_Bits.MCS200 */
+#define IFX_GTM_MCSINTCLR_MCS200_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCSINTCLR_Bits.MCS200 */
+#define IFX_GTM_MCSINTCLR_MCS200_OFF (8u)
+
+/** \brief Length for Ifx_GTM_MCSINTCLR_Bits.MCS201 */
+#define IFX_GTM_MCSINTCLR_MCS201_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCSINTCLR_Bits.MCS201 */
+#define IFX_GTM_MCSINTCLR_MCS201_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCSINTCLR_Bits.MCS201 */
+#define IFX_GTM_MCSINTCLR_MCS201_OFF (9u)
+
+/** \brief Length for Ifx_GTM_MCSINTCLR_Bits.MCS210 */
+#define IFX_GTM_MCSINTCLR_MCS210_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCSINTCLR_Bits.MCS210 */
+#define IFX_GTM_MCSINTCLR_MCS210_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCSINTCLR_Bits.MCS210 */
+#define IFX_GTM_MCSINTCLR_MCS210_OFF (10u)
+
+/** \brief Length for Ifx_GTM_MCSINTCLR_Bits.MCS211 */
+#define IFX_GTM_MCSINTCLR_MCS211_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCSINTCLR_Bits.MCS211 */
+#define IFX_GTM_MCSINTCLR_MCS211_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCSINTCLR_Bits.MCS211 */
+#define IFX_GTM_MCSINTCLR_MCS211_OFF (11u)
+
+/** \brief Length for Ifx_GTM_MCSINTSTAT_Bits.MCS000 */
+#define IFX_GTM_MCSINTSTAT_MCS000_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCSINTSTAT_Bits.MCS000 */
+#define IFX_GTM_MCSINTSTAT_MCS000_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCSINTSTAT_Bits.MCS000 */
+#define IFX_GTM_MCSINTSTAT_MCS000_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MCSINTSTAT_Bits.MCS001 */
+#define IFX_GTM_MCSINTSTAT_MCS001_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCSINTSTAT_Bits.MCS001 */
+#define IFX_GTM_MCSINTSTAT_MCS001_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCSINTSTAT_Bits.MCS001 */
+#define IFX_GTM_MCSINTSTAT_MCS001_OFF (1u)
+
+/** \brief Length for Ifx_GTM_MCSINTSTAT_Bits.MCS010 */
+#define IFX_GTM_MCSINTSTAT_MCS010_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCSINTSTAT_Bits.MCS010 */
+#define IFX_GTM_MCSINTSTAT_MCS010_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCSINTSTAT_Bits.MCS010 */
+#define IFX_GTM_MCSINTSTAT_MCS010_OFF (2u)
+
+/** \brief Length for Ifx_GTM_MCSINTSTAT_Bits.MCS011 */
+#define IFX_GTM_MCSINTSTAT_MCS011_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCSINTSTAT_Bits.MCS011 */
+#define IFX_GTM_MCSINTSTAT_MCS011_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCSINTSTAT_Bits.MCS011 */
+#define IFX_GTM_MCSINTSTAT_MCS011_OFF (3u)
+
+/** \brief Length for Ifx_GTM_MCSINTSTAT_Bits.MCS100 */
+#define IFX_GTM_MCSINTSTAT_MCS100_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCSINTSTAT_Bits.MCS100 */
+#define IFX_GTM_MCSINTSTAT_MCS100_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCSINTSTAT_Bits.MCS100 */
+#define IFX_GTM_MCSINTSTAT_MCS100_OFF (4u)
+
+/** \brief Length for Ifx_GTM_MCSINTSTAT_Bits.MCS101 */
+#define IFX_GTM_MCSINTSTAT_MCS101_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCSINTSTAT_Bits.MCS101 */
+#define IFX_GTM_MCSINTSTAT_MCS101_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCSINTSTAT_Bits.MCS101 */
+#define IFX_GTM_MCSINTSTAT_MCS101_OFF (5u)
+
+/** \brief Length for Ifx_GTM_MCSINTSTAT_Bits.MCS110 */
+#define IFX_GTM_MCSINTSTAT_MCS110_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCSINTSTAT_Bits.MCS110 */
+#define IFX_GTM_MCSINTSTAT_MCS110_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCSINTSTAT_Bits.MCS110 */
+#define IFX_GTM_MCSINTSTAT_MCS110_OFF (6u)
+
+/** \brief Length for Ifx_GTM_MCSINTSTAT_Bits.MCS111 */
+#define IFX_GTM_MCSINTSTAT_MCS111_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCSINTSTAT_Bits.MCS111 */
+#define IFX_GTM_MCSINTSTAT_MCS111_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCSINTSTAT_Bits.MCS111 */
+#define IFX_GTM_MCSINTSTAT_MCS111_OFF (7u)
+
+/** \brief Length for Ifx_GTM_MCSINTSTAT_Bits.MCS200 */
+#define IFX_GTM_MCSINTSTAT_MCS200_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCSINTSTAT_Bits.MCS200 */
+#define IFX_GTM_MCSINTSTAT_MCS200_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCSINTSTAT_Bits.MCS200 */
+#define IFX_GTM_MCSINTSTAT_MCS200_OFF (8u)
+
+/** \brief Length for Ifx_GTM_MCSINTSTAT_Bits.MCS201 */
+#define IFX_GTM_MCSINTSTAT_MCS201_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCSINTSTAT_Bits.MCS201 */
+#define IFX_GTM_MCSINTSTAT_MCS201_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCSINTSTAT_Bits.MCS201 */
+#define IFX_GTM_MCSINTSTAT_MCS201_OFF (9u)
+
+/** \brief Length for Ifx_GTM_MCSINTSTAT_Bits.MCS210 */
+#define IFX_GTM_MCSINTSTAT_MCS210_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCSINTSTAT_Bits.MCS210 */
+#define IFX_GTM_MCSINTSTAT_MCS210_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCSINTSTAT_Bits.MCS210 */
+#define IFX_GTM_MCSINTSTAT_MCS210_OFF (10u)
+
+/** \brief Length for Ifx_GTM_MCSINTSTAT_Bits.MCS211 */
+#define IFX_GTM_MCSINTSTAT_MCS211_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MCSINTSTAT_Bits.MCS211 */
+#define IFX_GTM_MCSINTSTAT_MCS211_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MCSINTSTAT_Bits.MCS211 */
+#define IFX_GTM_MCSINTSTAT_MCS211_OFF (11u)
+
+/** \brief Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_0 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_0_0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_0 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_0_0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_0 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_0_0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_1 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_0_1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_1 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_0_1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_1 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_0_1_OFF (1u)
+
+/** \brief Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_2 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_0_2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_2 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_0_2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_2 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_0_2_OFF (2u)
+
+/** \brief Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_3 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_0_3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_3 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_0_3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_3 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_0_3_OFF (3u)
+
+/** \brief Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_4 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_0_4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_4 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_0_4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_4 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_0_4_OFF (4u)
+
+/** \brief Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_5 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_0_5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_5 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_0_5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_5 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_0_5_OFF (5u)
+
+/** \brief Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_6 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_0_6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_6 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_0_6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_6 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_0_6_OFF (6u)
+
+/** \brief Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_7 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_0_7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_7 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_0_7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_7 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_0_7_OFF (7u)
+
+/** \brief Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_0 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_1_0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_0 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_1_0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_0 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_1_0_OFF (8u)
+
+/** \brief Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_1 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_1_1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_1 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_1_1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_1 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_1_1_OFF (9u)
+
+/** \brief Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_2 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_1_2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_2 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_1_2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_2 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_1_2_OFF (10u)
+
+/** \brief Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_3 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_1_3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_3 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_1_3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_3 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_1_3_OFF (11u)
+
+/** \brief Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_4 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_1_4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_4 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_1_4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_4 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_1_4_OFF (12u)
+
+/** \brief Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_5 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_1_5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_5 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_1_5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_5 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_1_5_OFF (13u)
+
+/** \brief Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_6 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_1_6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_6 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_1_6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_6 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_1_6_OFF (14u)
+
+/** \brief Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_7 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_1_7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_7 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_1_7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_7 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_1_7_OFF (15u)
+
+/** \brief Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_0 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_2_0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_0 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_2_0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_0 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_2_0_OFF (16u)
+
+/** \brief Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_1 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_2_1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_1 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_2_1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_1 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_2_1_OFF (17u)
+
+/** \brief Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_2 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_2_2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_2 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_2_2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_2 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_2_2_OFF (18u)
+
+/** \brief Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_3 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_2_3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_3 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_2_3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_3 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_2_3_OFF (19u)
+
+/** \brief Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_4 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_2_4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_4 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_2_4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_4 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_2_4_OFF (20u)
+
+/** \brief Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_5 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_2_5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_5 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_2_5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_5 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_2_5_OFF (21u)
+
+/** \brief Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_6 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_2_6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_6 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_2_6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_6 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_2_6_OFF (22u)
+
+/** \brief Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_7 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_2_7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_7 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_2_7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_7 */
+#define IFX_GTM_MON_ACTIVITY_0_MCA_2_7_OFF (23u)
+
+/** \brief Length for Ifx_GTM_MON_STATUS_Bits.ACT_CMU0 */
+#define IFX_GTM_MON_STATUS_ACT_CMU0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_STATUS_Bits.ACT_CMU0 */
+#define IFX_GTM_MON_STATUS_ACT_CMU0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_STATUS_Bits.ACT_CMU0 */
+#define IFX_GTM_MON_STATUS_ACT_CMU0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MON_STATUS_Bits.ACT_CMU1 */
+#define IFX_GTM_MON_STATUS_ACT_CMU1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_STATUS_Bits.ACT_CMU1 */
+#define IFX_GTM_MON_STATUS_ACT_CMU1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_STATUS_Bits.ACT_CMU1 */
+#define IFX_GTM_MON_STATUS_ACT_CMU1_OFF (1u)
+
+/** \brief Length for Ifx_GTM_MON_STATUS_Bits.ACT_CMU2 */
+#define IFX_GTM_MON_STATUS_ACT_CMU2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_STATUS_Bits.ACT_CMU2 */
+#define IFX_GTM_MON_STATUS_ACT_CMU2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_STATUS_Bits.ACT_CMU2 */
+#define IFX_GTM_MON_STATUS_ACT_CMU2_OFF (2u)
+
+/** \brief Length for Ifx_GTM_MON_STATUS_Bits.ACT_CMU3 */
+#define IFX_GTM_MON_STATUS_ACT_CMU3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_STATUS_Bits.ACT_CMU3 */
+#define IFX_GTM_MON_STATUS_ACT_CMU3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_STATUS_Bits.ACT_CMU3 */
+#define IFX_GTM_MON_STATUS_ACT_CMU3_OFF (3u)
+
+/** \brief Length for Ifx_GTM_MON_STATUS_Bits.ACT_CMU4 */
+#define IFX_GTM_MON_STATUS_ACT_CMU4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_STATUS_Bits.ACT_CMU4 */
+#define IFX_GTM_MON_STATUS_ACT_CMU4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_STATUS_Bits.ACT_CMU4 */
+#define IFX_GTM_MON_STATUS_ACT_CMU4_OFF (4u)
+
+/** \brief Length for Ifx_GTM_MON_STATUS_Bits.ACT_CMU5 */
+#define IFX_GTM_MON_STATUS_ACT_CMU5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_STATUS_Bits.ACT_CMU5 */
+#define IFX_GTM_MON_STATUS_ACT_CMU5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_STATUS_Bits.ACT_CMU5 */
+#define IFX_GTM_MON_STATUS_ACT_CMU5_OFF (5u)
+
+/** \brief Length for Ifx_GTM_MON_STATUS_Bits.ACT_CMU6 */
+#define IFX_GTM_MON_STATUS_ACT_CMU6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_STATUS_Bits.ACT_CMU6 */
+#define IFX_GTM_MON_STATUS_ACT_CMU6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_STATUS_Bits.ACT_CMU6 */
+#define IFX_GTM_MON_STATUS_ACT_CMU6_OFF (6u)
+
+/** \brief Length for Ifx_GTM_MON_STATUS_Bits.ACT_CMU7 */
+#define IFX_GTM_MON_STATUS_ACT_CMU7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_STATUS_Bits.ACT_CMU7 */
+#define IFX_GTM_MON_STATUS_ACT_CMU7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_STATUS_Bits.ACT_CMU7 */
+#define IFX_GTM_MON_STATUS_ACT_CMU7_OFF (7u)
+
+/** \brief Length for Ifx_GTM_MON_STATUS_Bits.ACT_CMUFX0 */
+#define IFX_GTM_MON_STATUS_ACT_CMUFX0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_STATUS_Bits.ACT_CMUFX0 */
+#define IFX_GTM_MON_STATUS_ACT_CMUFX0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_STATUS_Bits.ACT_CMUFX0 */
+#define IFX_GTM_MON_STATUS_ACT_CMUFX0_OFF (8u)
+
+/** \brief Length for Ifx_GTM_MON_STATUS_Bits.ACT_CMUFX1 */
+#define IFX_GTM_MON_STATUS_ACT_CMUFX1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_STATUS_Bits.ACT_CMUFX1 */
+#define IFX_GTM_MON_STATUS_ACT_CMUFX1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_STATUS_Bits.ACT_CMUFX1 */
+#define IFX_GTM_MON_STATUS_ACT_CMUFX1_OFF (9u)
+
+/** \brief Length for Ifx_GTM_MON_STATUS_Bits.ACT_CMUFX2 */
+#define IFX_GTM_MON_STATUS_ACT_CMUFX2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_STATUS_Bits.ACT_CMUFX2 */
+#define IFX_GTM_MON_STATUS_ACT_CMUFX2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_STATUS_Bits.ACT_CMUFX2 */
+#define IFX_GTM_MON_STATUS_ACT_CMUFX2_OFF (10u)
+
+/** \brief Length for Ifx_GTM_MON_STATUS_Bits.ACT_CMUFX3 */
+#define IFX_GTM_MON_STATUS_ACT_CMUFX3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_STATUS_Bits.ACT_CMUFX3 */
+#define IFX_GTM_MON_STATUS_ACT_CMUFX3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_STATUS_Bits.ACT_CMUFX3 */
+#define IFX_GTM_MON_STATUS_ACT_CMUFX3_OFF (11u)
+
+/** \brief Length for Ifx_GTM_MON_STATUS_Bits.ACT_CMUFX4 */
+#define IFX_GTM_MON_STATUS_ACT_CMUFX4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_STATUS_Bits.ACT_CMUFX4 */
+#define IFX_GTM_MON_STATUS_ACT_CMUFX4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_STATUS_Bits.ACT_CMUFX4 */
+#define IFX_GTM_MON_STATUS_ACT_CMUFX4_OFF (12u)
+
+/** \brief Length for Ifx_GTM_MON_STATUS_Bits.CMP_ERR */
+#define IFX_GTM_MON_STATUS_CMP_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_STATUS_Bits.CMP_ERR */
+#define IFX_GTM_MON_STATUS_CMP_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_STATUS_Bits.CMP_ERR */
+#define IFX_GTM_MON_STATUS_CMP_ERR_OFF (16u)
+
+/** \brief Length for Ifx_GTM_MON_STATUS_Bits.MCS0_ERR */
+#define IFX_GTM_MON_STATUS_MCS0_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_STATUS_Bits.MCS0_ERR */
+#define IFX_GTM_MON_STATUS_MCS0_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_STATUS_Bits.MCS0_ERR */
+#define IFX_GTM_MON_STATUS_MCS0_ERR_OFF (20u)
+
+/** \brief Length for Ifx_GTM_MON_STATUS_Bits.MCS1_ERR */
+#define IFX_GTM_MON_STATUS_MCS1_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_STATUS_Bits.MCS1_ERR */
+#define IFX_GTM_MON_STATUS_MCS1_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_STATUS_Bits.MCS1_ERR */
+#define IFX_GTM_MON_STATUS_MCS1_ERR_OFF (21u)
+
+/** \brief Length for Ifx_GTM_MON_STATUS_Bits.MCS2_ERR */
+#define IFX_GTM_MON_STATUS_MCS2_ERR_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_MON_STATUS_Bits.MCS2_ERR */
+#define IFX_GTM_MON_STATUS_MCS2_ERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_MON_STATUS_Bits.MCS2_ERR */
+#define IFX_GTM_MON_STATUS_MCS2_ERR_OFF (22u)
+
+/** \brief Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL0 */
+#define IFX_GTM_MSC0INLEXTCON_SEL0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL0 */
+#define IFX_GTM_MSC0INLEXTCON_SEL0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL0 */
+#define IFX_GTM_MSC0INLEXTCON_SEL0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL10 */
+#define IFX_GTM_MSC0INLEXTCON_SEL10_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL10 */
+#define IFX_GTM_MSC0INLEXTCON_SEL10_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL10 */
+#define IFX_GTM_MSC0INLEXTCON_SEL10_OFF (20u)
+
+/** \brief Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL11 */
+#define IFX_GTM_MSC0INLEXTCON_SEL11_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL11 */
+#define IFX_GTM_MSC0INLEXTCON_SEL11_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL11 */
+#define IFX_GTM_MSC0INLEXTCON_SEL11_OFF (22u)
+
+/** \brief Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL12 */
+#define IFX_GTM_MSC0INLEXTCON_SEL12_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL12 */
+#define IFX_GTM_MSC0INLEXTCON_SEL12_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL12 */
+#define IFX_GTM_MSC0INLEXTCON_SEL12_OFF (24u)
+
+/** \brief Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL13 */
+#define IFX_GTM_MSC0INLEXTCON_SEL13_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL13 */
+#define IFX_GTM_MSC0INLEXTCON_SEL13_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL13 */
+#define IFX_GTM_MSC0INLEXTCON_SEL13_OFF (26u)
+
+/** \brief Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL14 */
+#define IFX_GTM_MSC0INLEXTCON_SEL14_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL14 */
+#define IFX_GTM_MSC0INLEXTCON_SEL14_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL14 */
+#define IFX_GTM_MSC0INLEXTCON_SEL14_OFF (28u)
+
+/** \brief Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL15 */
+#define IFX_GTM_MSC0INLEXTCON_SEL15_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL15 */
+#define IFX_GTM_MSC0INLEXTCON_SEL15_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL15 */
+#define IFX_GTM_MSC0INLEXTCON_SEL15_OFF (30u)
+
+/** \brief Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL1 */
+#define IFX_GTM_MSC0INLEXTCON_SEL1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL1 */
+#define IFX_GTM_MSC0INLEXTCON_SEL1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL1 */
+#define IFX_GTM_MSC0INLEXTCON_SEL1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL2 */
+#define IFX_GTM_MSC0INLEXTCON_SEL2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL2 */
+#define IFX_GTM_MSC0INLEXTCON_SEL2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL2 */
+#define IFX_GTM_MSC0INLEXTCON_SEL2_OFF (4u)
+
+/** \brief Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL3 */
+#define IFX_GTM_MSC0INLEXTCON_SEL3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL3 */
+#define IFX_GTM_MSC0INLEXTCON_SEL3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL3 */
+#define IFX_GTM_MSC0INLEXTCON_SEL3_OFF (6u)
+
+/** \brief Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL4 */
+#define IFX_GTM_MSC0INLEXTCON_SEL4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL4 */
+#define IFX_GTM_MSC0INLEXTCON_SEL4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL4 */
+#define IFX_GTM_MSC0INLEXTCON_SEL4_OFF (8u)
+
+/** \brief Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL5 */
+#define IFX_GTM_MSC0INLEXTCON_SEL5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL5 */
+#define IFX_GTM_MSC0INLEXTCON_SEL5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL5 */
+#define IFX_GTM_MSC0INLEXTCON_SEL5_OFF (10u)
+
+/** \brief Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL6 */
+#define IFX_GTM_MSC0INLEXTCON_SEL6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL6 */
+#define IFX_GTM_MSC0INLEXTCON_SEL6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL6 */
+#define IFX_GTM_MSC0INLEXTCON_SEL6_OFF (12u)
+
+/** \brief Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL7 */
+#define IFX_GTM_MSC0INLEXTCON_SEL7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL7 */
+#define IFX_GTM_MSC0INLEXTCON_SEL7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL7 */
+#define IFX_GTM_MSC0INLEXTCON_SEL7_OFF (14u)
+
+/** \brief Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL8 */
+#define IFX_GTM_MSC0INLEXTCON_SEL8_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL8 */
+#define IFX_GTM_MSC0INLEXTCON_SEL8_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL8 */
+#define IFX_GTM_MSC0INLEXTCON_SEL8_OFF (16u)
+
+/** \brief Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL9 */
+#define IFX_GTM_MSC0INLEXTCON_SEL9_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL9 */
+#define IFX_GTM_MSC0INLEXTCON_SEL9_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL9 */
+#define IFX_GTM_MSC0INLEXTCON_SEL9_OFF (18u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL0 */
+#define IFX_GTM_MSCIN_INHCON_SEL0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL0 */
+#define IFX_GTM_MSCIN_INHCON_SEL0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL0 */
+#define IFX_GTM_MSCIN_INHCON_SEL0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL10 */
+#define IFX_GTM_MSCIN_INHCON_SEL10_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL10 */
+#define IFX_GTM_MSCIN_INHCON_SEL10_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL10 */
+#define IFX_GTM_MSCIN_INHCON_SEL10_OFF (20u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL11 */
+#define IFX_GTM_MSCIN_INHCON_SEL11_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL11 */
+#define IFX_GTM_MSCIN_INHCON_SEL11_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL11 */
+#define IFX_GTM_MSCIN_INHCON_SEL11_OFF (22u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL12 */
+#define IFX_GTM_MSCIN_INHCON_SEL12_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL12 */
+#define IFX_GTM_MSCIN_INHCON_SEL12_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL12 */
+#define IFX_GTM_MSCIN_INHCON_SEL12_OFF (24u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL13 */
+#define IFX_GTM_MSCIN_INHCON_SEL13_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL13 */
+#define IFX_GTM_MSCIN_INHCON_SEL13_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL13 */
+#define IFX_GTM_MSCIN_INHCON_SEL13_OFF (26u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL14 */
+#define IFX_GTM_MSCIN_INHCON_SEL14_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL14 */
+#define IFX_GTM_MSCIN_INHCON_SEL14_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL14 */
+#define IFX_GTM_MSCIN_INHCON_SEL14_OFF (28u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL15 */
+#define IFX_GTM_MSCIN_INHCON_SEL15_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL15 */
+#define IFX_GTM_MSCIN_INHCON_SEL15_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL15 */
+#define IFX_GTM_MSCIN_INHCON_SEL15_OFF (30u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL1 */
+#define IFX_GTM_MSCIN_INHCON_SEL1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL1 */
+#define IFX_GTM_MSCIN_INHCON_SEL1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL1 */
+#define IFX_GTM_MSCIN_INHCON_SEL1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL2 */
+#define IFX_GTM_MSCIN_INHCON_SEL2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL2 */
+#define IFX_GTM_MSCIN_INHCON_SEL2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL2 */
+#define IFX_GTM_MSCIN_INHCON_SEL2_OFF (4u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL3 */
+#define IFX_GTM_MSCIN_INHCON_SEL3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL3 */
+#define IFX_GTM_MSCIN_INHCON_SEL3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL3 */
+#define IFX_GTM_MSCIN_INHCON_SEL3_OFF (6u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL4 */
+#define IFX_GTM_MSCIN_INHCON_SEL4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL4 */
+#define IFX_GTM_MSCIN_INHCON_SEL4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL4 */
+#define IFX_GTM_MSCIN_INHCON_SEL4_OFF (8u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL5 */
+#define IFX_GTM_MSCIN_INHCON_SEL5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL5 */
+#define IFX_GTM_MSCIN_INHCON_SEL5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL5 */
+#define IFX_GTM_MSCIN_INHCON_SEL5_OFF (10u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL6 */
+#define IFX_GTM_MSCIN_INHCON_SEL6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL6 */
+#define IFX_GTM_MSCIN_INHCON_SEL6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL6 */
+#define IFX_GTM_MSCIN_INHCON_SEL6_OFF (12u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL7 */
+#define IFX_GTM_MSCIN_INHCON_SEL7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL7 */
+#define IFX_GTM_MSCIN_INHCON_SEL7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL7 */
+#define IFX_GTM_MSCIN_INHCON_SEL7_OFF (14u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL8 */
+#define IFX_GTM_MSCIN_INHCON_SEL8_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL8 */
+#define IFX_GTM_MSCIN_INHCON_SEL8_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL8 */
+#define IFX_GTM_MSCIN_INHCON_SEL8_OFF (16u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL9 */
+#define IFX_GTM_MSCIN_INHCON_SEL9_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL9 */
+#define IFX_GTM_MSCIN_INHCON_SEL9_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL9 */
+#define IFX_GTM_MSCIN_INHCON_SEL9_OFF (18u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL0 */
+#define IFX_GTM_MSCIN_INLCON_SEL0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL0 */
+#define IFX_GTM_MSCIN_INLCON_SEL0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL0 */
+#define IFX_GTM_MSCIN_INLCON_SEL0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL10 */
+#define IFX_GTM_MSCIN_INLCON_SEL10_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL10 */
+#define IFX_GTM_MSCIN_INLCON_SEL10_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL10 */
+#define IFX_GTM_MSCIN_INLCON_SEL10_OFF (20u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL11 */
+#define IFX_GTM_MSCIN_INLCON_SEL11_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL11 */
+#define IFX_GTM_MSCIN_INLCON_SEL11_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL11 */
+#define IFX_GTM_MSCIN_INLCON_SEL11_OFF (22u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL12 */
+#define IFX_GTM_MSCIN_INLCON_SEL12_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL12 */
+#define IFX_GTM_MSCIN_INLCON_SEL12_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL12 */
+#define IFX_GTM_MSCIN_INLCON_SEL12_OFF (24u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL13 */
+#define IFX_GTM_MSCIN_INLCON_SEL13_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL13 */
+#define IFX_GTM_MSCIN_INLCON_SEL13_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL13 */
+#define IFX_GTM_MSCIN_INLCON_SEL13_OFF (26u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL14 */
+#define IFX_GTM_MSCIN_INLCON_SEL14_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL14 */
+#define IFX_GTM_MSCIN_INLCON_SEL14_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL14 */
+#define IFX_GTM_MSCIN_INLCON_SEL14_OFF (28u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL15 */
+#define IFX_GTM_MSCIN_INLCON_SEL15_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL15 */
+#define IFX_GTM_MSCIN_INLCON_SEL15_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL15 */
+#define IFX_GTM_MSCIN_INLCON_SEL15_OFF (30u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL1 */
+#define IFX_GTM_MSCIN_INLCON_SEL1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL1 */
+#define IFX_GTM_MSCIN_INLCON_SEL1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL1 */
+#define IFX_GTM_MSCIN_INLCON_SEL1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL2 */
+#define IFX_GTM_MSCIN_INLCON_SEL2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL2 */
+#define IFX_GTM_MSCIN_INLCON_SEL2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL2 */
+#define IFX_GTM_MSCIN_INLCON_SEL2_OFF (4u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL3 */
+#define IFX_GTM_MSCIN_INLCON_SEL3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL3 */
+#define IFX_GTM_MSCIN_INLCON_SEL3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL3 */
+#define IFX_GTM_MSCIN_INLCON_SEL3_OFF (6u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL4 */
+#define IFX_GTM_MSCIN_INLCON_SEL4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL4 */
+#define IFX_GTM_MSCIN_INLCON_SEL4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL4 */
+#define IFX_GTM_MSCIN_INLCON_SEL4_OFF (8u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL5 */
+#define IFX_GTM_MSCIN_INLCON_SEL5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL5 */
+#define IFX_GTM_MSCIN_INLCON_SEL5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL5 */
+#define IFX_GTM_MSCIN_INLCON_SEL5_OFF (10u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL6 */
+#define IFX_GTM_MSCIN_INLCON_SEL6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL6 */
+#define IFX_GTM_MSCIN_INLCON_SEL6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL6 */
+#define IFX_GTM_MSCIN_INLCON_SEL6_OFF (12u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL7 */
+#define IFX_GTM_MSCIN_INLCON_SEL7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL7 */
+#define IFX_GTM_MSCIN_INLCON_SEL7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL7 */
+#define IFX_GTM_MSCIN_INLCON_SEL7_OFF (14u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL8 */
+#define IFX_GTM_MSCIN_INLCON_SEL8_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL8 */
+#define IFX_GTM_MSCIN_INLCON_SEL8_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL8 */
+#define IFX_GTM_MSCIN_INLCON_SEL8_OFF (16u)
+
+/** \brief Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL9 */
+#define IFX_GTM_MSCIN_INLCON_SEL9_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL9 */
+#define IFX_GTM_MSCIN_INLCON_SEL9_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL9 */
+#define IFX_GTM_MSCIN_INLCON_SEL9_OFF (18u)
+
+/** \brief Length for Ifx_GTM_MSCSET_CON0_Bits.SEL0 */
+#define IFX_GTM_MSCSET_CON0_SEL0_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_MSCSET_CON0_Bits.SEL0 */
+#define IFX_GTM_MSCSET_CON0_SEL0_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_MSCSET_CON0_Bits.SEL0 */
+#define IFX_GTM_MSCSET_CON0_SEL0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MSCSET_CON0_Bits.SEL1 */
+#define IFX_GTM_MSCSET_CON0_SEL1_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_MSCSET_CON0_Bits.SEL1 */
+#define IFX_GTM_MSCSET_CON0_SEL1_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_MSCSET_CON0_Bits.SEL1 */
+#define IFX_GTM_MSCSET_CON0_SEL1_OFF (8u)
+
+/** \brief Length for Ifx_GTM_MSCSET_CON0_Bits.SEL2 */
+#define IFX_GTM_MSCSET_CON0_SEL2_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_MSCSET_CON0_Bits.SEL2 */
+#define IFX_GTM_MSCSET_CON0_SEL2_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_MSCSET_CON0_Bits.SEL2 */
+#define IFX_GTM_MSCSET_CON0_SEL2_OFF (16u)
+
+/** \brief Length for Ifx_GTM_MSCSET_CON0_Bits.SEL3 */
+#define IFX_GTM_MSCSET_CON0_SEL3_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_MSCSET_CON0_Bits.SEL3 */
+#define IFX_GTM_MSCSET_CON0_SEL3_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_MSCSET_CON0_Bits.SEL3 */
+#define IFX_GTM_MSCSET_CON0_SEL3_OFF (24u)
+
+/** \brief Length for Ifx_GTM_MSCSET_CON1_Bits.SEL4 */
+#define IFX_GTM_MSCSET_CON1_SEL4_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_MSCSET_CON1_Bits.SEL4 */
+#define IFX_GTM_MSCSET_CON1_SEL4_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_MSCSET_CON1_Bits.SEL4 */
+#define IFX_GTM_MSCSET_CON1_SEL4_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MSCSET_CON1_Bits.SEL5 */
+#define IFX_GTM_MSCSET_CON1_SEL5_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_MSCSET_CON1_Bits.SEL5 */
+#define IFX_GTM_MSCSET_CON1_SEL5_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_MSCSET_CON1_Bits.SEL5 */
+#define IFX_GTM_MSCSET_CON1_SEL5_OFF (8u)
+
+/** \brief Length for Ifx_GTM_MSCSET_CON1_Bits.SEL6 */
+#define IFX_GTM_MSCSET_CON1_SEL6_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_MSCSET_CON1_Bits.SEL6 */
+#define IFX_GTM_MSCSET_CON1_SEL6_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_MSCSET_CON1_Bits.SEL6 */
+#define IFX_GTM_MSCSET_CON1_SEL6_OFF (16u)
+
+/** \brief Length for Ifx_GTM_MSCSET_CON1_Bits.SEL7 */
+#define IFX_GTM_MSCSET_CON1_SEL7_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_MSCSET_CON1_Bits.SEL7 */
+#define IFX_GTM_MSCSET_CON1_SEL7_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_MSCSET_CON1_Bits.SEL7 */
+#define IFX_GTM_MSCSET_CON1_SEL7_OFF (24u)
+
+/** \brief Length for Ifx_GTM_MSCSET_CON2_Bits.SEL10 */
+#define IFX_GTM_MSCSET_CON2_SEL10_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_MSCSET_CON2_Bits.SEL10 */
+#define IFX_GTM_MSCSET_CON2_SEL10_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_MSCSET_CON2_Bits.SEL10 */
+#define IFX_GTM_MSCSET_CON2_SEL10_OFF (16u)
+
+/** \brief Length for Ifx_GTM_MSCSET_CON2_Bits.SEL11 */
+#define IFX_GTM_MSCSET_CON2_SEL11_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_MSCSET_CON2_Bits.SEL11 */
+#define IFX_GTM_MSCSET_CON2_SEL11_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_MSCSET_CON2_Bits.SEL11 */
+#define IFX_GTM_MSCSET_CON2_SEL11_OFF (24u)
+
+/** \brief Length for Ifx_GTM_MSCSET_CON2_Bits.SEL8 */
+#define IFX_GTM_MSCSET_CON2_SEL8_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_MSCSET_CON2_Bits.SEL8 */
+#define IFX_GTM_MSCSET_CON2_SEL8_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_MSCSET_CON2_Bits.SEL8 */
+#define IFX_GTM_MSCSET_CON2_SEL8_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MSCSET_CON2_Bits.SEL9 */
+#define IFX_GTM_MSCSET_CON2_SEL9_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_MSCSET_CON2_Bits.SEL9 */
+#define IFX_GTM_MSCSET_CON2_SEL9_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_MSCSET_CON2_Bits.SEL9 */
+#define IFX_GTM_MSCSET_CON2_SEL9_OFF (8u)
+
+/** \brief Length for Ifx_GTM_MSCSET_CON3_Bits.SEL12 */
+#define IFX_GTM_MSCSET_CON3_SEL12_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_MSCSET_CON3_Bits.SEL12 */
+#define IFX_GTM_MSCSET_CON3_SEL12_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_MSCSET_CON3_Bits.SEL12 */
+#define IFX_GTM_MSCSET_CON3_SEL12_OFF (0u)
+
+/** \brief Length for Ifx_GTM_MSCSET_CON3_Bits.SEL13 */
+#define IFX_GTM_MSCSET_CON3_SEL13_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_MSCSET_CON3_Bits.SEL13 */
+#define IFX_GTM_MSCSET_CON3_SEL13_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_MSCSET_CON3_Bits.SEL13 */
+#define IFX_GTM_MSCSET_CON3_SEL13_OFF (8u)
+
+/** \brief Length for Ifx_GTM_MSCSET_CON3_Bits.SEL14 */
+#define IFX_GTM_MSCSET_CON3_SEL14_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_MSCSET_CON3_Bits.SEL14 */
+#define IFX_GTM_MSCSET_CON3_SEL14_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_MSCSET_CON3_Bits.SEL14 */
+#define IFX_GTM_MSCSET_CON3_SEL14_OFF (16u)
+
+/** \brief Length for Ifx_GTM_MSCSET_CON3_Bits.SEL15 */
+#define IFX_GTM_MSCSET_CON3_SEL15_LEN (5u)
+
+/** \brief Mask for Ifx_GTM_MSCSET_CON3_Bits.SEL15 */
+#define IFX_GTM_MSCSET_CON3_SEL15_MSK (0x1fu)
+
+/** \brief Offset for Ifx_GTM_MSCSET_CON3_Bits.SEL15 */
+#define IFX_GTM_MSCSET_CON3_SEL15_OFF (24u)
+
+/** \brief Length for Ifx_GTM_OCS_Bits.SUS */
+#define IFX_GTM_OCS_SUS_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_OCS_Bits.SUS */
+#define IFX_GTM_OCS_SUS_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_OCS_Bits.SUS */
+#define IFX_GTM_OCS_SUS_OFF (24u)
+
+/** \brief Length for Ifx_GTM_OCS_Bits.SUS_P */
+#define IFX_GTM_OCS_SUS_P_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_OCS_Bits.SUS_P */
+#define IFX_GTM_OCS_SUS_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_OCS_Bits.SUS_P */
+#define IFX_GTM_OCS_SUS_P_OFF (28u)
+
+/** \brief Length for Ifx_GTM_OCS_Bits.SUSSTA */
+#define IFX_GTM_OCS_SUSSTA_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_OCS_Bits.SUSSTA */
+#define IFX_GTM_OCS_SUSSTA_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_OCS_Bits.SUSSTA */
+#define IFX_GTM_OCS_SUSSTA_OFF (29u)
+
+/** \brief Length for Ifx_GTM_ODA_Bits.DDREN */
+#define IFX_GTM_ODA_DDREN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ODA_Bits.DDREN */
+#define IFX_GTM_ODA_DDREN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ODA_Bits.DDREN */
+#define IFX_GTM_ODA_DDREN_OFF (0u)
+
+/** \brief Length for Ifx_GTM_ODA_Bits.DREN */
+#define IFX_GTM_ODA_DREN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_ODA_Bits.DREN */
+#define IFX_GTM_ODA_DREN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_ODA_Bits.DREN */
+#define IFX_GTM_ODA_DREN_OFF (1u)
+
+/** \brief Length for Ifx_GTM_OTBU0T_Bits.CM */
+#define IFX_GTM_OTBU0T_CM_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_OTBU0T_Bits.CM */
+#define IFX_GTM_OTBU0T_CM_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_OTBU0T_Bits.CM */
+#define IFX_GTM_OTBU0T_CM_OFF (28u)
+
+/** \brief Length for Ifx_GTM_OTBU0T_Bits.CV */
+#define IFX_GTM_OTBU0T_CV_LEN (27u)
+
+/** \brief Mask for Ifx_GTM_OTBU0T_Bits.CV */
+#define IFX_GTM_OTBU0T_CV_MSK (0x7ffffffu)
+
+/** \brief Offset for Ifx_GTM_OTBU0T_Bits.CV */
+#define IFX_GTM_OTBU0T_CV_OFF (0u)
+
+/** \brief Length for Ifx_GTM_OTBU1T_Bits.CV */
+#define IFX_GTM_OTBU1T_CV_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_OTBU1T_Bits.CV */
+#define IFX_GTM_OTBU1T_CV_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_OTBU1T_Bits.CV */
+#define IFX_GTM_OTBU1T_CV_OFF (0u)
+
+/** \brief Length for Ifx_GTM_OTBU1T_Bits.EN */
+#define IFX_GTM_OTBU1T_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_OTBU1T_Bits.EN */
+#define IFX_GTM_OTBU1T_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_OTBU1T_Bits.EN */
+#define IFX_GTM_OTBU1T_EN_OFF (28u)
+
+/** \brief Length for Ifx_GTM_OTBU2T_Bits.CV */
+#define IFX_GTM_OTBU2T_CV_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_OTBU2T_Bits.CV */
+#define IFX_GTM_OTBU2T_CV_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_OTBU2T_Bits.CV */
+#define IFX_GTM_OTBU2T_CV_OFF (0u)
+
+/** \brief Length for Ifx_GTM_OTBU2T_Bits.EN */
+#define IFX_GTM_OTBU2T_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_OTBU2T_Bits.EN */
+#define IFX_GTM_OTBU2T_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_OTBU2T_Bits.EN */
+#define IFX_GTM_OTBU2T_EN_OFF (28u)
+
+/** \brief Length for Ifx_GTM_OTSC0_Bits.B0HMI */
+#define IFX_GTM_OTSC0_B0HMI_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_OTSC0_Bits.B0HMI */
+#define IFX_GTM_OTSC0_B0HMI_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_OTSC0_Bits.B0HMI */
+#define IFX_GTM_OTSC0_B0HMI_OFF (12u)
+
+/** \brief Length for Ifx_GTM_OTSC0_Bits.B0HMT */
+#define IFX_GTM_OTSC0_B0HMT_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_OTSC0_Bits.B0HMT */
+#define IFX_GTM_OTSC0_B0HMT_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_OTSC0_Bits.B0HMT */
+#define IFX_GTM_OTSC0_B0HMT_OFF (8u)
+
+/** \brief Length for Ifx_GTM_OTSC0_Bits.B0LMI */
+#define IFX_GTM_OTSC0_B0LMI_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_OTSC0_Bits.B0LMI */
+#define IFX_GTM_OTSC0_B0LMI_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_OTSC0_Bits.B0LMI */
+#define IFX_GTM_OTSC0_B0LMI_OFF (4u)
+
+/** \brief Length for Ifx_GTM_OTSC0_Bits.B0LMT */
+#define IFX_GTM_OTSC0_B0LMT_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_OTSC0_Bits.B0LMT */
+#define IFX_GTM_OTSC0_B0LMT_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_OTSC0_Bits.B0LMT */
+#define IFX_GTM_OTSC0_B0LMT_OFF (0u)
+
+/** \brief Length for Ifx_GTM_OTSC0_Bits.B1HMI */
+#define IFX_GTM_OTSC0_B1HMI_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_OTSC0_Bits.B1HMI */
+#define IFX_GTM_OTSC0_B1HMI_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_OTSC0_Bits.B1HMI */
+#define IFX_GTM_OTSC0_B1HMI_OFF (28u)
+
+/** \brief Length for Ifx_GTM_OTSC0_Bits.B1HMT */
+#define IFX_GTM_OTSC0_B1HMT_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_OTSC0_Bits.B1HMT */
+#define IFX_GTM_OTSC0_B1HMT_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_OTSC0_Bits.B1HMT */
+#define IFX_GTM_OTSC0_B1HMT_OFF (24u)
+
+/** \brief Length for Ifx_GTM_OTSC0_Bits.B1LMI */
+#define IFX_GTM_OTSC0_B1LMI_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_OTSC0_Bits.B1LMI */
+#define IFX_GTM_OTSC0_B1LMI_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_OTSC0_Bits.B1LMI */
+#define IFX_GTM_OTSC0_B1LMI_OFF (20u)
+
+/** \brief Length for Ifx_GTM_OTSC0_Bits.B1LMT */
+#define IFX_GTM_OTSC0_B1LMT_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_OTSC0_Bits.B1LMT */
+#define IFX_GTM_OTSC0_B1LMT_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_OTSC0_Bits.B1LMT */
+#define IFX_GTM_OTSC0_B1LMT_OFF (16u)
+
+/** \brief Length for Ifx_GTM_OTSC1_Bits.MCS */
+#define IFX_GTM_OTSC1_MCS_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_OTSC1_Bits.MCS */
+#define IFX_GTM_OTSC1_MCS_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_OTSC1_Bits.MCS */
+#define IFX_GTM_OTSC1_MCS_OFF (0u)
+
+/** \brief Length for Ifx_GTM_OTSC1_Bits.MI */
+#define IFX_GTM_OTSC1_MI_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_OTSC1_Bits.MI */
+#define IFX_GTM_OTSC1_MI_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_OTSC1_Bits.MI */
+#define IFX_GTM_OTSC1_MI_OFF (4u)
+
+/** \brief Length for Ifx_GTM_OTSC1_Bits.MOE */
+#define IFX_GTM_OTSC1_MOE_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_OTSC1_Bits.MOE */
+#define IFX_GTM_OTSC1_MOE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_OTSC1_Bits.MOE */
+#define IFX_GTM_OTSC1_MOE_OFF (9u)
+
+/** \brief Length for Ifx_GTM_OTSS_Bits.OTGB0 */
+#define IFX_GTM_OTSS_OTGB0_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_OTSS_Bits.OTGB0 */
+#define IFX_GTM_OTSS_OTGB0_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_OTSS_Bits.OTGB0 */
+#define IFX_GTM_OTSS_OTGB0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_OTSS_Bits.OTGB1 */
+#define IFX_GTM_OTSS_OTGB1_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_OTSS_Bits.OTGB1 */
+#define IFX_GTM_OTSS_OTGB1_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_OTSS_Bits.OTGB1 */
+#define IFX_GTM_OTSS_OTGB1_OFF (8u)
+
+/** \brief Length for Ifx_GTM_OTSS_Bits.OTGB2 */
+#define IFX_GTM_OTSS_OTGB2_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_OTSS_Bits.OTGB2 */
+#define IFX_GTM_OTSS_OTGB2_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_OTSS_Bits.OTGB2 */
+#define IFX_GTM_OTSS_OTGB2_OFF (16u)
+
+/** \brief Length for Ifx_GTM_REV_Bits.DEV_CODE0 */
+#define IFX_GTM_REV_DEV_CODE0_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_REV_Bits.DEV_CODE0 */
+#define IFX_GTM_REV_DEV_CODE0_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_REV_Bits.DEV_CODE0 */
+#define IFX_GTM_REV_DEV_CODE0_OFF (20u)
+
+/** \brief Length for Ifx_GTM_REV_Bits.DEV_CODE1 */
+#define IFX_GTM_REV_DEV_CODE1_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_REV_Bits.DEV_CODE1 */
+#define IFX_GTM_REV_DEV_CODE1_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_REV_Bits.DEV_CODE1 */
+#define IFX_GTM_REV_DEV_CODE1_OFF (24u)
+
+/** \brief Length for Ifx_GTM_REV_Bits.DEV_CODE2 */
+#define IFX_GTM_REV_DEV_CODE2_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_REV_Bits.DEV_CODE2 */
+#define IFX_GTM_REV_DEV_CODE2_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_REV_Bits.DEV_CODE2 */
+#define IFX_GTM_REV_DEV_CODE2_OFF (28u)
+
+/** \brief Length for Ifx_GTM_REV_Bits.MAJOR */
+#define IFX_GTM_REV_MAJOR_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_REV_Bits.MAJOR */
+#define IFX_GTM_REV_MAJOR_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_REV_Bits.MAJOR */
+#define IFX_GTM_REV_MAJOR_OFF (16u)
+
+/** \brief Length for Ifx_GTM_REV_Bits.MINOR */
+#define IFX_GTM_REV_MINOR_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_REV_Bits.MINOR */
+#define IFX_GTM_REV_MINOR_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_REV_Bits.MINOR */
+#define IFX_GTM_REV_MINOR_OFF (12u)
+
+/** \brief Length for Ifx_GTM_REV_Bits.NO */
+#define IFX_GTM_REV_NO_LEN (4u)
+
+/** \brief Mask for Ifx_GTM_REV_Bits.NO */
+#define IFX_GTM_REV_NO_MSK (0xfu)
+
+/** \brief Offset for Ifx_GTM_REV_Bits.NO */
+#define IFX_GTM_REV_NO_OFF (8u)
+
+/** \brief Length for Ifx_GTM_REV_Bits.STEP */
+#define IFX_GTM_REV_STEP_LEN (8u)
+
+/** \brief Mask for Ifx_GTM_REV_Bits.STEP */
+#define IFX_GTM_REV_STEP_MSK (0xffu)
+
+/** \brief Offset for Ifx_GTM_REV_Bits.STEP */
+#define IFX_GTM_REV_STEP_OFF (0u)
+
+/** \brief Length for Ifx_GTM_RST_Bits.RST */
+#define IFX_GTM_RST_RST_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_RST_Bits.RST */
+#define IFX_GTM_RST_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_RST_Bits.RST */
+#define IFX_GTM_RST_RST_OFF (0u)
+
+/** \brief Length for Ifx_GTM_SPE_CMP_Bits.CMP */
+#define IFX_GTM_SPE_CMP_CMP_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_SPE_CMP_Bits.CMP */
+#define IFX_GTM_SPE_CMP_CMP_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_SPE_CMP_Bits.CMP */
+#define IFX_GTM_SPE_CMP_CMP_OFF (0u)
+
+/** \brief Length for Ifx_GTM_SPE_CNT_Bits.CNT */
+#define IFX_GTM_SPE_CNT_CNT_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_SPE_CNT_Bits.CNT */
+#define IFX_GTM_SPE_CNT_CNT_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_SPE_CNT_Bits.CNT */
+#define IFX_GTM_SPE_CNT_CNT_OFF (0u)
+
+/** \brief Length for Ifx_GTM_SPE_CTRL_STAT_Bits.ADIR */
+#define IFX_GTM_SPE_CTRL_STAT_ADIR_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_CTRL_STAT_Bits.ADIR */
+#define IFX_GTM_SPE_CTRL_STAT_ADIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_CTRL_STAT_Bits.ADIR */
+#define IFX_GTM_SPE_CTRL_STAT_ADIR_OFF (15u)
+
+/** \brief Length for Ifx_GTM_SPE_CTRL_STAT_Bits.AIP */
+#define IFX_GTM_SPE_CTRL_STAT_AIP_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_SPE_CTRL_STAT_Bits.AIP */
+#define IFX_GTM_SPE_CTRL_STAT_AIP_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_SPE_CTRL_STAT_Bits.AIP */
+#define IFX_GTM_SPE_CTRL_STAT_AIP_OFF (12u)
+
+/** \brief Length for Ifx_GTM_SPE_CTRL_STAT_Bits.FSOL */
+#define IFX_GTM_SPE_CTRL_STAT_FSOL_LEN (8u)
+
+/** \brief Mask for Ifx_GTM_SPE_CTRL_STAT_Bits.FSOL */
+#define IFX_GTM_SPE_CTRL_STAT_FSOL_MSK (0xffu)
+
+/** \brief Offset for Ifx_GTM_SPE_CTRL_STAT_Bits.FSOL */
+#define IFX_GTM_SPE_CTRL_STAT_FSOL_OFF (24u)
+
+/** \brief Length for Ifx_GTM_SPE_CTRL_STAT_Bits.FSOM */
+#define IFX_GTM_SPE_CTRL_STAT_FSOM_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_CTRL_STAT_Bits.FSOM */
+#define IFX_GTM_SPE_CTRL_STAT_FSOM_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_CTRL_STAT_Bits.FSOM */
+#define IFX_GTM_SPE_CTRL_STAT_FSOM_OFF (7u)
+
+/** \brief Length for Ifx_GTM_SPE_CTRL_STAT_Bits.NIP */
+#define IFX_GTM_SPE_CTRL_STAT_NIP_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_SPE_CTRL_STAT_Bits.NIP */
+#define IFX_GTM_SPE_CTRL_STAT_NIP_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_SPE_CTRL_STAT_Bits.NIP */
+#define IFX_GTM_SPE_CTRL_STAT_NIP_OFF (20u)
+
+/** \brief Length for Ifx_GTM_SPE_CTRL_STAT_Bits.PDIR */
+#define IFX_GTM_SPE_CTRL_STAT_PDIR_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_CTRL_STAT_Bits.PDIR */
+#define IFX_GTM_SPE_CTRL_STAT_PDIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_CTRL_STAT_Bits.PDIR */
+#define IFX_GTM_SPE_CTRL_STAT_PDIR_OFF (19u)
+
+/** \brief Length for Ifx_GTM_SPE_CTRL_STAT_Bits.PIP */
+#define IFX_GTM_SPE_CTRL_STAT_PIP_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_SPE_CTRL_STAT_Bits.PIP */
+#define IFX_GTM_SPE_CTRL_STAT_PIP_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_SPE_CTRL_STAT_Bits.PIP */
+#define IFX_GTM_SPE_CTRL_STAT_PIP_OFF (16u)
+
+/** \brief Length for Ifx_GTM_SPE_CTRL_STAT_Bits.SIE0 */
+#define IFX_GTM_SPE_CTRL_STAT_SIE0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_CTRL_STAT_Bits.SIE0 */
+#define IFX_GTM_SPE_CTRL_STAT_SIE0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_CTRL_STAT_Bits.SIE0 */
+#define IFX_GTM_SPE_CTRL_STAT_SIE0_OFF (1u)
+
+/** \brief Length for Ifx_GTM_SPE_CTRL_STAT_Bits.SIE1 */
+#define IFX_GTM_SPE_CTRL_STAT_SIE1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_CTRL_STAT_Bits.SIE1 */
+#define IFX_GTM_SPE_CTRL_STAT_SIE1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_CTRL_STAT_Bits.SIE1 */
+#define IFX_GTM_SPE_CTRL_STAT_SIE1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_SPE_CTRL_STAT_Bits.SIE2 */
+#define IFX_GTM_SPE_CTRL_STAT_SIE2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_CTRL_STAT_Bits.SIE2 */
+#define IFX_GTM_SPE_CTRL_STAT_SIE2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_CTRL_STAT_Bits.SIE2 */
+#define IFX_GTM_SPE_CTRL_STAT_SIE2_OFF (3u)
+
+/** \brief Length for Ifx_GTM_SPE_CTRL_STAT_Bits.SPE_EN */
+#define IFX_GTM_SPE_CTRL_STAT_SPE_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_CTRL_STAT_Bits.SPE_EN */
+#define IFX_GTM_SPE_CTRL_STAT_SPE_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_CTRL_STAT_Bits.SPE_EN */
+#define IFX_GTM_SPE_CTRL_STAT_SPE_EN_OFF (0u)
+
+/** \brief Length for Ifx_GTM_SPE_CTRL_STAT_Bits.SPE_PAT_PTR */
+#define IFX_GTM_SPE_CTRL_STAT_SPE_PAT_PTR_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_SPE_CTRL_STAT_Bits.SPE_PAT_PTR */
+#define IFX_GTM_SPE_CTRL_STAT_SPE_PAT_PTR_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_SPE_CTRL_STAT_Bits.SPE_PAT_PTR */
+#define IFX_GTM_SPE_CTRL_STAT_SPE_PAT_PTR_OFF (8u)
+
+/** \brief Length for Ifx_GTM_SPE_CTRL_STAT_Bits.TIM_SEL */
+#define IFX_GTM_SPE_CTRL_STAT_TIM_SEL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_CTRL_STAT_Bits.TIM_SEL */
+#define IFX_GTM_SPE_CTRL_STAT_TIM_SEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_CTRL_STAT_Bits.TIM_SEL */
+#define IFX_GTM_SPE_CTRL_STAT_TIM_SEL_OFF (6u)
+
+/** \brief Length for Ifx_GTM_SPE_CTRL_STAT_Bits.TRIG_SEL */
+#define IFX_GTM_SPE_CTRL_STAT_TRIG_SEL_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_SPE_CTRL_STAT_Bits.TRIG_SEL */
+#define IFX_GTM_SPE_CTRL_STAT_TRIG_SEL_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_SPE_CTRL_STAT_Bits.TRIG_SEL */
+#define IFX_GTM_SPE_CTRL_STAT_TRIG_SEL_OFF (4u)
+
+/** \brief Length for Ifx_GTM_SPE_EIRQ_EN_Bits.SPE_BIS_EIRQ_EN */
+#define IFX_GTM_SPE_EIRQ_EN_SPE_BIS_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_EIRQ_EN_Bits.SPE_BIS_EIRQ_EN */
+#define IFX_GTM_SPE_EIRQ_EN_SPE_BIS_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_EIRQ_EN_Bits.SPE_BIS_EIRQ_EN */
+#define IFX_GTM_SPE_EIRQ_EN_SPE_BIS_EIRQ_EN_OFF (3u)
+
+/** \brief Length for Ifx_GTM_SPE_EIRQ_EN_Bits.SPE_DCHG_EIRQ_EN */
+#define IFX_GTM_SPE_EIRQ_EN_SPE_DCHG_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_EIRQ_EN_Bits.SPE_DCHG_EIRQ_EN */
+#define IFX_GTM_SPE_EIRQ_EN_SPE_DCHG_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_EIRQ_EN_Bits.SPE_DCHG_EIRQ_EN */
+#define IFX_GTM_SPE_EIRQ_EN_SPE_DCHG_EIRQ_EN_OFF (1u)
+
+/** \brief Length for Ifx_GTM_SPE_EIRQ_EN_Bits.SPE_NIPD_EIRQ_EN */
+#define IFX_GTM_SPE_EIRQ_EN_SPE_NIPD_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_EIRQ_EN_Bits.SPE_NIPD_EIRQ_EN */
+#define IFX_GTM_SPE_EIRQ_EN_SPE_NIPD_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_EIRQ_EN_Bits.SPE_NIPD_EIRQ_EN */
+#define IFX_GTM_SPE_EIRQ_EN_SPE_NIPD_EIRQ_EN_OFF (0u)
+
+/** \brief Length for Ifx_GTM_SPE_EIRQ_EN_Bits.SPE_PERR_EIRQ_EN */
+#define IFX_GTM_SPE_EIRQ_EN_SPE_PERR_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_EIRQ_EN_Bits.SPE_PERR_EIRQ_EN */
+#define IFX_GTM_SPE_EIRQ_EN_SPE_PERR_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_EIRQ_EN_Bits.SPE_PERR_EIRQ_EN */
+#define IFX_GTM_SPE_EIRQ_EN_SPE_PERR_EIRQ_EN_OFF (2u)
+
+/** \brief Length for Ifx_GTM_SPE_EIRQ_EN_Bits.SPE_RCMP_EIRQ_EN */
+#define IFX_GTM_SPE_EIRQ_EN_SPE_RCMP_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_EIRQ_EN_Bits.SPE_RCMP_EIRQ_EN */
+#define IFX_GTM_SPE_EIRQ_EN_SPE_RCMP_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_EIRQ_EN_Bits.SPE_RCMP_EIRQ_EN */
+#define IFX_GTM_SPE_EIRQ_EN_SPE_RCMP_EIRQ_EN_OFF (4u)
+
+/** \brief Length for Ifx_GTM_SPE_IRQ_EN_Bits.SPE_BIS_IRQ_EN */
+#define IFX_GTM_SPE_IRQ_EN_SPE_BIS_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_IRQ_EN_Bits.SPE_BIS_IRQ_EN */
+#define IFX_GTM_SPE_IRQ_EN_SPE_BIS_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_IRQ_EN_Bits.SPE_BIS_IRQ_EN */
+#define IFX_GTM_SPE_IRQ_EN_SPE_BIS_IRQ_EN_OFF (3u)
+
+/** \brief Length for Ifx_GTM_SPE_IRQ_EN_Bits.SPE_DCHG_IRQ_EN */
+#define IFX_GTM_SPE_IRQ_EN_SPE_DCHG_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_IRQ_EN_Bits.SPE_DCHG_IRQ_EN */
+#define IFX_GTM_SPE_IRQ_EN_SPE_DCHG_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_IRQ_EN_Bits.SPE_DCHG_IRQ_EN */
+#define IFX_GTM_SPE_IRQ_EN_SPE_DCHG_IRQ_EN_OFF (1u)
+
+/** \brief Length for Ifx_GTM_SPE_IRQ_EN_Bits.SPE_NIPD_IRQ_EN */
+#define IFX_GTM_SPE_IRQ_EN_SPE_NIPD_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_IRQ_EN_Bits.SPE_NIPD_IRQ_EN */
+#define IFX_GTM_SPE_IRQ_EN_SPE_NIPD_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_IRQ_EN_Bits.SPE_NIPD_IRQ_EN */
+#define IFX_GTM_SPE_IRQ_EN_SPE_NIPD_IRQ_EN_OFF (0u)
+
+/** \brief Length for Ifx_GTM_SPE_IRQ_EN_Bits.SPE_PERR_IRQ_EN */
+#define IFX_GTM_SPE_IRQ_EN_SPE_PERR_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_IRQ_EN_Bits.SPE_PERR_IRQ_EN */
+#define IFX_GTM_SPE_IRQ_EN_SPE_PERR_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_IRQ_EN_Bits.SPE_PERR_IRQ_EN */
+#define IFX_GTM_SPE_IRQ_EN_SPE_PERR_IRQ_EN_OFF (2u)
+
+/** \brief Length for Ifx_GTM_SPE_IRQ_EN_Bits.SPE_RCMP_IRQ_EN */
+#define IFX_GTM_SPE_IRQ_EN_SPE_RCMP_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_IRQ_EN_Bits.SPE_RCMP_IRQ_EN */
+#define IFX_GTM_SPE_IRQ_EN_SPE_RCMP_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_IRQ_EN_Bits.SPE_RCMP_IRQ_EN */
+#define IFX_GTM_SPE_IRQ_EN_SPE_RCMP_IRQ_EN_OFF (4u)
+
+/** \brief Length for Ifx_GTM_SPE_IRQ_FORCINT_Bits.TRG_SPE_BIS */
+#define IFX_GTM_SPE_IRQ_FORCINT_TRG_SPE_BIS_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_IRQ_FORCINT_Bits.TRG_SPE_BIS */
+#define IFX_GTM_SPE_IRQ_FORCINT_TRG_SPE_BIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_IRQ_FORCINT_Bits.TRG_SPE_BIS */
+#define IFX_GTM_SPE_IRQ_FORCINT_TRG_SPE_BIS_OFF (3u)
+
+/** \brief Length for Ifx_GTM_SPE_IRQ_FORCINT_Bits.TRG_SPE_DCHG */
+#define IFX_GTM_SPE_IRQ_FORCINT_TRG_SPE_DCHG_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_IRQ_FORCINT_Bits.TRG_SPE_DCHG */
+#define IFX_GTM_SPE_IRQ_FORCINT_TRG_SPE_DCHG_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_IRQ_FORCINT_Bits.TRG_SPE_DCHG */
+#define IFX_GTM_SPE_IRQ_FORCINT_TRG_SPE_DCHG_OFF (1u)
+
+/** \brief Length for Ifx_GTM_SPE_IRQ_FORCINT_Bits.TRG_SPE_NIPD */
+#define IFX_GTM_SPE_IRQ_FORCINT_TRG_SPE_NIPD_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_IRQ_FORCINT_Bits.TRG_SPE_NIPD */
+#define IFX_GTM_SPE_IRQ_FORCINT_TRG_SPE_NIPD_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_IRQ_FORCINT_Bits.TRG_SPE_NIPD */
+#define IFX_GTM_SPE_IRQ_FORCINT_TRG_SPE_NIPD_OFF (0u)
+
+/** \brief Length for Ifx_GTM_SPE_IRQ_FORCINT_Bits.TRG_SPE_PERR */
+#define IFX_GTM_SPE_IRQ_FORCINT_TRG_SPE_PERR_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_IRQ_FORCINT_Bits.TRG_SPE_PERR */
+#define IFX_GTM_SPE_IRQ_FORCINT_TRG_SPE_PERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_IRQ_FORCINT_Bits.TRG_SPE_PERR */
+#define IFX_GTM_SPE_IRQ_FORCINT_TRG_SPE_PERR_OFF (2u)
+
+/** \brief Length for Ifx_GTM_SPE_IRQ_FORCINT_Bits.TRG_SPE_RCMP */
+#define IFX_GTM_SPE_IRQ_FORCINT_TRG_SPE_RCMP_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_IRQ_FORCINT_Bits.TRG_SPE_RCMP */
+#define IFX_GTM_SPE_IRQ_FORCINT_TRG_SPE_RCMP_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_IRQ_FORCINT_Bits.TRG_SPE_RCMP */
+#define IFX_GTM_SPE_IRQ_FORCINT_TRG_SPE_RCMP_OFF (4u)
+
+/** \brief Length for Ifx_GTM_SPE_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_SPE_IRQ_MODE_IRQ_MODE_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_SPE_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_SPE_IRQ_MODE_IRQ_MODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_SPE_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_SPE_IRQ_MODE_IRQ_MODE_OFF (0u)
+
+/** \brief Length for Ifx_GTM_SPE_IRQ_NOTIFY_Bits.SPE_BIS */
+#define IFX_GTM_SPE_IRQ_NOTIFY_SPE_BIS_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_IRQ_NOTIFY_Bits.SPE_BIS */
+#define IFX_GTM_SPE_IRQ_NOTIFY_SPE_BIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_IRQ_NOTIFY_Bits.SPE_BIS */
+#define IFX_GTM_SPE_IRQ_NOTIFY_SPE_BIS_OFF (3u)
+
+/** \brief Length for Ifx_GTM_SPE_IRQ_NOTIFY_Bits.SPE_DCHG */
+#define IFX_GTM_SPE_IRQ_NOTIFY_SPE_DCHG_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_IRQ_NOTIFY_Bits.SPE_DCHG */
+#define IFX_GTM_SPE_IRQ_NOTIFY_SPE_DCHG_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_IRQ_NOTIFY_Bits.SPE_DCHG */
+#define IFX_GTM_SPE_IRQ_NOTIFY_SPE_DCHG_OFF (1u)
+
+/** \brief Length for Ifx_GTM_SPE_IRQ_NOTIFY_Bits.SPE_NIPD */
+#define IFX_GTM_SPE_IRQ_NOTIFY_SPE_NIPD_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_IRQ_NOTIFY_Bits.SPE_NIPD */
+#define IFX_GTM_SPE_IRQ_NOTIFY_SPE_NIPD_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_IRQ_NOTIFY_Bits.SPE_NIPD */
+#define IFX_GTM_SPE_IRQ_NOTIFY_SPE_NIPD_OFF (0u)
+
+/** \brief Length for Ifx_GTM_SPE_IRQ_NOTIFY_Bits.SPE_PERR */
+#define IFX_GTM_SPE_IRQ_NOTIFY_SPE_PERR_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_IRQ_NOTIFY_Bits.SPE_PERR */
+#define IFX_GTM_SPE_IRQ_NOTIFY_SPE_PERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_IRQ_NOTIFY_Bits.SPE_PERR */
+#define IFX_GTM_SPE_IRQ_NOTIFY_SPE_PERR_OFF (2u)
+
+/** \brief Length for Ifx_GTM_SPE_IRQ_NOTIFY_Bits.SPE_RCMP */
+#define IFX_GTM_SPE_IRQ_NOTIFY_SPE_RCMP_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_IRQ_NOTIFY_Bits.SPE_RCMP */
+#define IFX_GTM_SPE_IRQ_NOTIFY_SPE_RCMP_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_IRQ_NOTIFY_Bits.SPE_RCMP */
+#define IFX_GTM_SPE_IRQ_NOTIFY_SPE_RCMP_OFF (4u)
+
+/** \brief Length for Ifx_GTM_SPE_OUT_CTRL_Bits.SPE_OUT_CTRL */
+#define IFX_GTM_SPE_OUT_CTRL_SPE_OUT_CTRL_LEN (16u)
+
+/** \brief Mask for Ifx_GTM_SPE_OUT_CTRL_Bits.SPE_OUT_CTRL */
+#define IFX_GTM_SPE_OUT_CTRL_SPE_OUT_CTRL_MSK (0xffffu)
+
+/** \brief Offset for Ifx_GTM_SPE_OUT_CTRL_Bits.SPE_OUT_CTRL */
+#define IFX_GTM_SPE_OUT_CTRL_SPE_OUT_CTRL_OFF (0u)
+
+/** \brief Length for Ifx_GTM_SPE_OUT_PAT_Bits.SPE_OUT_PAT */
+#define IFX_GTM_SPE_OUT_PAT_SPE_OUT_PAT_LEN (16u)
+
+/** \brief Mask for Ifx_GTM_SPE_OUT_PAT_Bits.SPE_OUT_PAT */
+#define IFX_GTM_SPE_OUT_PAT_SPE_OUT_PAT_MSK (0xffffu)
+
+/** \brief Offset for Ifx_GTM_SPE_OUT_PAT_Bits.SPE_OUT_PAT */
+#define IFX_GTM_SPE_OUT_PAT_SPE_OUT_PAT_OFF (0u)
+
+/** \brief Length for Ifx_GTM_SPE_PAT_Bits.IP0_PAT */
+#define IFX_GTM_SPE_PAT_IP0_PAT_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_SPE_PAT_Bits.IP0_PAT */
+#define IFX_GTM_SPE_PAT_IP0_PAT_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_SPE_PAT_Bits.IP0_PAT */
+#define IFX_GTM_SPE_PAT_IP0_PAT_OFF (1u)
+
+/** \brief Length for Ifx_GTM_SPE_PAT_Bits.IP0_VAL */
+#define IFX_GTM_SPE_PAT_IP0_VAL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_PAT_Bits.IP0_VAL */
+#define IFX_GTM_SPE_PAT_IP0_VAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_PAT_Bits.IP0_VAL */
+#define IFX_GTM_SPE_PAT_IP0_VAL_OFF (0u)
+
+/** \brief Length for Ifx_GTM_SPE_PAT_Bits.IP1_PAT */
+#define IFX_GTM_SPE_PAT_IP1_PAT_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_SPE_PAT_Bits.IP1_PAT */
+#define IFX_GTM_SPE_PAT_IP1_PAT_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_SPE_PAT_Bits.IP1_PAT */
+#define IFX_GTM_SPE_PAT_IP1_PAT_OFF (5u)
+
+/** \brief Length for Ifx_GTM_SPE_PAT_Bits.IP1_VAL */
+#define IFX_GTM_SPE_PAT_IP1_VAL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_PAT_Bits.IP1_VAL */
+#define IFX_GTM_SPE_PAT_IP1_VAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_PAT_Bits.IP1_VAL */
+#define IFX_GTM_SPE_PAT_IP1_VAL_OFF (4u)
+
+/** \brief Length for Ifx_GTM_SPE_PAT_Bits.IP2_PAT */
+#define IFX_GTM_SPE_PAT_IP2_PAT_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_SPE_PAT_Bits.IP2_PAT */
+#define IFX_GTM_SPE_PAT_IP2_PAT_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_SPE_PAT_Bits.IP2_PAT */
+#define IFX_GTM_SPE_PAT_IP2_PAT_OFF (9u)
+
+/** \brief Length for Ifx_GTM_SPE_PAT_Bits.IP2_VAL */
+#define IFX_GTM_SPE_PAT_IP2_VAL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_PAT_Bits.IP2_VAL */
+#define IFX_GTM_SPE_PAT_IP2_VAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_PAT_Bits.IP2_VAL */
+#define IFX_GTM_SPE_PAT_IP2_VAL_OFF (8u)
+
+/** \brief Length for Ifx_GTM_SPE_PAT_Bits.IP3_PAT */
+#define IFX_GTM_SPE_PAT_IP3_PAT_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_SPE_PAT_Bits.IP3_PAT */
+#define IFX_GTM_SPE_PAT_IP3_PAT_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_SPE_PAT_Bits.IP3_PAT */
+#define IFX_GTM_SPE_PAT_IP3_PAT_OFF (13u)
+
+/** \brief Length for Ifx_GTM_SPE_PAT_Bits.IP3_VAL */
+#define IFX_GTM_SPE_PAT_IP3_VAL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_PAT_Bits.IP3_VAL */
+#define IFX_GTM_SPE_PAT_IP3_VAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_PAT_Bits.IP3_VAL */
+#define IFX_GTM_SPE_PAT_IP3_VAL_OFF (12u)
+
+/** \brief Length for Ifx_GTM_SPE_PAT_Bits.IP4_PAT */
+#define IFX_GTM_SPE_PAT_IP4_PAT_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_SPE_PAT_Bits.IP4_PAT */
+#define IFX_GTM_SPE_PAT_IP4_PAT_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_SPE_PAT_Bits.IP4_PAT */
+#define IFX_GTM_SPE_PAT_IP4_PAT_OFF (17u)
+
+/** \brief Length for Ifx_GTM_SPE_PAT_Bits.IP4_VAL */
+#define IFX_GTM_SPE_PAT_IP4_VAL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_PAT_Bits.IP4_VAL */
+#define IFX_GTM_SPE_PAT_IP4_VAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_PAT_Bits.IP4_VAL */
+#define IFX_GTM_SPE_PAT_IP4_VAL_OFF (16u)
+
+/** \brief Length for Ifx_GTM_SPE_PAT_Bits.IP5_PAT */
+#define IFX_GTM_SPE_PAT_IP5_PAT_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_SPE_PAT_Bits.IP5_PAT */
+#define IFX_GTM_SPE_PAT_IP5_PAT_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_SPE_PAT_Bits.IP5_PAT */
+#define IFX_GTM_SPE_PAT_IP5_PAT_OFF (21u)
+
+/** \brief Length for Ifx_GTM_SPE_PAT_Bits.IP5_VAL */
+#define IFX_GTM_SPE_PAT_IP5_VAL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_PAT_Bits.IP5_VAL */
+#define IFX_GTM_SPE_PAT_IP5_VAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_PAT_Bits.IP5_VAL */
+#define IFX_GTM_SPE_PAT_IP5_VAL_OFF (20u)
+
+/** \brief Length for Ifx_GTM_SPE_PAT_Bits.IP6_PAT */
+#define IFX_GTM_SPE_PAT_IP6_PAT_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_SPE_PAT_Bits.IP6_PAT */
+#define IFX_GTM_SPE_PAT_IP6_PAT_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_SPE_PAT_Bits.IP6_PAT */
+#define IFX_GTM_SPE_PAT_IP6_PAT_OFF (25u)
+
+/** \brief Length for Ifx_GTM_SPE_PAT_Bits.IP6_VAL */
+#define IFX_GTM_SPE_PAT_IP6_VAL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_PAT_Bits.IP6_VAL */
+#define IFX_GTM_SPE_PAT_IP6_VAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_PAT_Bits.IP6_VAL */
+#define IFX_GTM_SPE_PAT_IP6_VAL_OFF (24u)
+
+/** \brief Length for Ifx_GTM_SPE_PAT_Bits.IP7_PAT */
+#define IFX_GTM_SPE_PAT_IP7_PAT_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_SPE_PAT_Bits.IP7_PAT */
+#define IFX_GTM_SPE_PAT_IP7_PAT_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_SPE_PAT_Bits.IP7_PAT */
+#define IFX_GTM_SPE_PAT_IP7_PAT_OFF (29u)
+
+/** \brief Length for Ifx_GTM_SPE_PAT_Bits.IP7_VAL */
+#define IFX_GTM_SPE_PAT_IP7_VAL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_SPE_PAT_Bits.IP7_VAL */
+#define IFX_GTM_SPE_PAT_IP7_VAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_SPE_PAT_Bits.IP7_VAL */
+#define IFX_GTM_SPE_PAT_IP7_VAL_OFF (28u)
+
+/** \brief Length for Ifx_GTM_TBU_CH0_BASE_Bits.BASE */
+#define IFX_GTM_TBU_CH0_BASE_BASE_LEN (27u)
+
+/** \brief Mask for Ifx_GTM_TBU_CH0_BASE_Bits.BASE */
+#define IFX_GTM_TBU_CH0_BASE_BASE_MSK (0x7ffffffu)
+
+/** \brief Offset for Ifx_GTM_TBU_CH0_BASE_Bits.BASE */
+#define IFX_GTM_TBU_CH0_BASE_BASE_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TBU_CH0_CTRL_Bits.CH_CLK_SRC */
+#define IFX_GTM_TBU_CH0_CTRL_CH_CLK_SRC_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_TBU_CH0_CTRL_Bits.CH_CLK_SRC */
+#define IFX_GTM_TBU_CH0_CTRL_CH_CLK_SRC_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_TBU_CH0_CTRL_Bits.CH_CLK_SRC */
+#define IFX_GTM_TBU_CH0_CTRL_CH_CLK_SRC_OFF (1u)
+
+/** \brief Length for Ifx_GTM_TBU_CH0_CTRL_Bits.LOW_RES */
+#define IFX_GTM_TBU_CH0_CTRL_LOW_RES_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TBU_CH0_CTRL_Bits.LOW_RES */
+#define IFX_GTM_TBU_CH0_CTRL_LOW_RES_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TBU_CH0_CTRL_Bits.LOW_RES */
+#define IFX_GTM_TBU_CH0_CTRL_LOW_RES_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TBU_CH1_BASE_Bits.BASE */
+#define IFX_GTM_TBU_CH1_BASE_BASE_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_TBU_CH1_BASE_Bits.BASE */
+#define IFX_GTM_TBU_CH1_BASE_BASE_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_TBU_CH1_BASE_Bits.BASE */
+#define IFX_GTM_TBU_CH1_BASE_BASE_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TBU_CH1_CTRL_Bits.CH_CLK_SRC */
+#define IFX_GTM_TBU_CH1_CTRL_CH_CLK_SRC_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_TBU_CH1_CTRL_Bits.CH_CLK_SRC */
+#define IFX_GTM_TBU_CH1_CTRL_CH_CLK_SRC_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_TBU_CH1_CTRL_Bits.CH_CLK_SRC */
+#define IFX_GTM_TBU_CH1_CTRL_CH_CLK_SRC_OFF (1u)
+
+/** \brief Length for Ifx_GTM_TBU_CH1_CTRL_Bits.CH_MODE */
+#define IFX_GTM_TBU_CH1_CTRL_CH_MODE_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TBU_CH1_CTRL_Bits.CH_MODE */
+#define IFX_GTM_TBU_CH1_CTRL_CH_MODE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TBU_CH1_CTRL_Bits.CH_MODE */
+#define IFX_GTM_TBU_CH1_CTRL_CH_MODE_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TBU_CH2_BASE_Bits.BASE */
+#define IFX_GTM_TBU_CH2_BASE_BASE_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_TBU_CH2_BASE_Bits.BASE */
+#define IFX_GTM_TBU_CH2_BASE_BASE_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_TBU_CH2_BASE_Bits.BASE */
+#define IFX_GTM_TBU_CH2_BASE_BASE_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TBU_CH2_CTRL_Bits.CH_CLK_SRC */
+#define IFX_GTM_TBU_CH2_CTRL_CH_CLK_SRC_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_TBU_CH2_CTRL_Bits.CH_CLK_SRC */
+#define IFX_GTM_TBU_CH2_CTRL_CH_CLK_SRC_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_TBU_CH2_CTRL_Bits.CH_CLK_SRC */
+#define IFX_GTM_TBU_CH2_CTRL_CH_CLK_SRC_OFF (1u)
+
+/** \brief Length for Ifx_GTM_TBU_CH2_CTRL_Bits.CH_MODE */
+#define IFX_GTM_TBU_CH2_CTRL_CH_MODE_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TBU_CH2_CTRL_Bits.CH_MODE */
+#define IFX_GTM_TBU_CH2_CTRL_CH_MODE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TBU_CH2_CTRL_Bits.CH_MODE */
+#define IFX_GTM_TBU_CH2_CTRL_CH_MODE_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TBU_CHEN_Bits.ENDIS_CH0 */
+#define IFX_GTM_TBU_CHEN_ENDIS_CH0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TBU_CHEN_Bits.ENDIS_CH0 */
+#define IFX_GTM_TBU_CHEN_ENDIS_CH0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TBU_CHEN_Bits.ENDIS_CH0 */
+#define IFX_GTM_TBU_CHEN_ENDIS_CH0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TBU_CHEN_Bits.ENDIS_CH1 */
+#define IFX_GTM_TBU_CHEN_ENDIS_CH1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TBU_CHEN_Bits.ENDIS_CH1 */
+#define IFX_GTM_TBU_CHEN_ENDIS_CH1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TBU_CHEN_Bits.ENDIS_CH1 */
+#define IFX_GTM_TBU_CHEN_ENDIS_CH1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_TBU_CHEN_Bits.ENDIS_CH2 */
+#define IFX_GTM_TBU_CHEN_ENDIS_CH2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TBU_CHEN_Bits.ENDIS_CH2 */
+#define IFX_GTM_TBU_CHEN_ENDIS_CH2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TBU_CHEN_Bits.ENDIS_CH2 */
+#define IFX_GTM_TBU_CHEN_ENDIS_CH2_OFF (4u)
+
+/** \brief Length for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH0 */
+#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH0 */
+#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH0 */
+#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH1 */
+#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH1 */
+#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH1 */
+#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH1_OFF (1u)
+
+/** \brief Length for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH2 */
+#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH2 */
+#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH2 */
+#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH2_OFF (2u)
+
+/** \brief Length for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH3 */
+#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH3 */
+#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH3 */
+#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH3_OFF (3u)
+
+/** \brief Length for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH4 */
+#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH4 */
+#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH4 */
+#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH4_OFF (4u)
+
+/** \brief Length for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH5 */
+#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH5 */
+#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH5 */
+#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH5_OFF (5u)
+
+/** \brief Length for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH6 */
+#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH6 */
+#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH6 */
+#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH6_OFF (6u)
+
+/** \brief Length for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH7 */
+#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH7 */
+#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH7 */
+#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH7_OFF (7u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_CNT_Bits.CNT */
+#define IFX_GTM_TIM_CH_CNT_CNT_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_CNT_Bits.CNT */
+#define IFX_GTM_TIM_CH_CNT_CNT_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_CNT_Bits.CNT */
+#define IFX_GTM_TIM_CH_CNT_CNT_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_CNTS_Bits.CNTS */
+#define IFX_GTM_TIM_CH_CNTS_CNTS_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_CNTS_Bits.CNTS */
+#define IFX_GTM_TIM_CH_CNTS_CNTS_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_CNTS_Bits.CNTS */
+#define IFX_GTM_TIM_CH_CNTS_CNTS_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_CNTS_Bits.ECNT */
+#define IFX_GTM_TIM_CH_CNTS_ECNT_LEN (8u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_CNTS_Bits.ECNT */
+#define IFX_GTM_TIM_CH_CNTS_ECNT_MSK (0xffu)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_CNTS_Bits.ECNT */
+#define IFX_GTM_TIM_CH_CNTS_ECNT_OFF (24u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_CTRL_Bits.ARU_EN */
+#define IFX_GTM_TIM_CH_CTRL_ARU_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_CTRL_Bits.ARU_EN */
+#define IFX_GTM_TIM_CH_CTRL_ARU_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_CTRL_Bits.ARU_EN */
+#define IFX_GTM_TIM_CH_CTRL_ARU_EN_OFF (5u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_CTRL_Bits.CICTRL */
+#define IFX_GTM_TIM_CH_CTRL_CICTRL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_CTRL_Bits.CICTRL */
+#define IFX_GTM_TIM_CH_CTRL_CICTRL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_CTRL_Bits.CICTRL */
+#define IFX_GTM_TIM_CH_CTRL_CICTRL_OFF (6u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_CTRL_Bits.CLK_SEL */
+#define IFX_GTM_TIM_CH_CTRL_CLK_SEL_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_CTRL_Bits.CLK_SEL */
+#define IFX_GTM_TIM_CH_CTRL_CLK_SEL_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_CTRL_Bits.CLK_SEL */
+#define IFX_GTM_TIM_CH_CTRL_CLK_SEL_OFF (24u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_CTRL_Bits.CNTS_SEL */
+#define IFX_GTM_TIM_CH_CTRL_CNTS_SEL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_CTRL_Bits.CNTS_SEL */
+#define IFX_GTM_TIM_CH_CTRL_CNTS_SEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_CTRL_Bits.CNTS_SEL */
+#define IFX_GTM_TIM_CH_CTRL_CNTS_SEL_OFF (12u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_CTRL_Bits.DSL */
+#define IFX_GTM_TIM_CH_CTRL_DSL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_CTRL_Bits.DSL */
+#define IFX_GTM_TIM_CH_CTRL_DSL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_CTRL_Bits.DSL */
+#define IFX_GTM_TIM_CH_CTRL_DSL_OFF (13u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_CTRL_Bits.ECNT_RESET */
+#define IFX_GTM_TIM_CH_CTRL_ECNT_RESET_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_CTRL_Bits.ECNT_RESET */
+#define IFX_GTM_TIM_CH_CTRL_ECNT_RESET_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_CTRL_Bits.ECNT_RESET */
+#define IFX_GTM_TIM_CH_CTRL_ECNT_RESET_OFF (15u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_CTRL_Bits.EGPR0_SEL */
+#define IFX_GTM_TIM_CH_CTRL_EGPR0_SEL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_CTRL_Bits.EGPR0_SEL */
+#define IFX_GTM_TIM_CH_CTRL_EGPR0_SEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_CTRL_Bits.EGPR0_SEL */
+#define IFX_GTM_TIM_CH_CTRL_EGPR0_SEL_OFF (28u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_CTRL_Bits.EGPR1_SEL */
+#define IFX_GTM_TIM_CH_CTRL_EGPR1_SEL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_CTRL_Bits.EGPR1_SEL */
+#define IFX_GTM_TIM_CH_CTRL_EGPR1_SEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_CTRL_Bits.EGPR1_SEL */
+#define IFX_GTM_TIM_CH_CTRL_EGPR1_SEL_OFF (29u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_CTRL_Bits.EXT_CAP_EN */
+#define IFX_GTM_TIM_CH_CTRL_EXT_CAP_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_CTRL_Bits.EXT_CAP_EN */
+#define IFX_GTM_TIM_CH_CTRL_EXT_CAP_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_CTRL_Bits.EXT_CAP_EN */
+#define IFX_GTM_TIM_CH_CTRL_EXT_CAP_EN_OFF (19u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_CNT_FRQ */
+#define IFX_GTM_TIM_CH_CTRL_FLT_CNT_FRQ_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_CNT_FRQ */
+#define IFX_GTM_TIM_CH_CTRL_FLT_CNT_FRQ_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_CNT_FRQ */
+#define IFX_GTM_TIM_CH_CTRL_FLT_CNT_FRQ_OFF (17u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_CTR_FE */
+#define IFX_GTM_TIM_CH_CTRL_FLT_CTR_FE_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_CTR_FE */
+#define IFX_GTM_TIM_CH_CTRL_FLT_CTR_FE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_CTR_FE */
+#define IFX_GTM_TIM_CH_CTRL_FLT_CTR_FE_OFF (23u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_CTR_RE */
+#define IFX_GTM_TIM_CH_CTRL_FLT_CTR_RE_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_CTR_RE */
+#define IFX_GTM_TIM_CH_CTRL_FLT_CTR_RE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_CTR_RE */
+#define IFX_GTM_TIM_CH_CTRL_FLT_CTR_RE_OFF (21u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_EN */
+#define IFX_GTM_TIM_CH_CTRL_FLT_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_EN */
+#define IFX_GTM_TIM_CH_CTRL_FLT_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_EN */
+#define IFX_GTM_TIM_CH_CTRL_FLT_EN_OFF (16u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_MODE_FE */
+#define IFX_GTM_TIM_CH_CTRL_FLT_MODE_FE_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_MODE_FE */
+#define IFX_GTM_TIM_CH_CTRL_FLT_MODE_FE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_MODE_FE */
+#define IFX_GTM_TIM_CH_CTRL_FLT_MODE_FE_OFF (22u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_MODE_RE */
+#define IFX_GTM_TIM_CH_CTRL_FLT_MODE_RE_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_MODE_RE */
+#define IFX_GTM_TIM_CH_CTRL_FLT_MODE_RE_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_MODE_RE */
+#define IFX_GTM_TIM_CH_CTRL_FLT_MODE_RE_OFF (20u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_CTRL_Bits.FR_ECNT_OFL */
+#define IFX_GTM_TIM_CH_CTRL_FR_ECNT_OFL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_CTRL_Bits.FR_ECNT_OFL */
+#define IFX_GTM_TIM_CH_CTRL_FR_ECNT_OFL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_CTRL_Bits.FR_ECNT_OFL */
+#define IFX_GTM_TIM_CH_CTRL_FR_ECNT_OFL_OFF (27u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_CTRL_Bits.GPR0_SEL */
+#define IFX_GTM_TIM_CH_CTRL_GPR0_SEL_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_CTRL_Bits.GPR0_SEL */
+#define IFX_GTM_TIM_CH_CTRL_GPR0_SEL_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_CTRL_Bits.GPR0_SEL */
+#define IFX_GTM_TIM_CH_CTRL_GPR0_SEL_OFF (8u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_CTRL_Bits.GPR1_SEL */
+#define IFX_GTM_TIM_CH_CTRL_GPR1_SEL_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_CTRL_Bits.GPR1_SEL */
+#define IFX_GTM_TIM_CH_CTRL_GPR1_SEL_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_CTRL_Bits.GPR1_SEL */
+#define IFX_GTM_TIM_CH_CTRL_GPR1_SEL_OFF (10u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_CTRL_Bits.ISL */
+#define IFX_GTM_TIM_CH_CTRL_ISL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_CTRL_Bits.ISL */
+#define IFX_GTM_TIM_CH_CTRL_ISL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_CTRL_Bits.ISL */
+#define IFX_GTM_TIM_CH_CTRL_ISL_OFF (14u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_CTRL_Bits.OSM */
+#define IFX_GTM_TIM_CH_CTRL_OSM_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_CTRL_Bits.OSM */
+#define IFX_GTM_TIM_CH_CTRL_OSM_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_CTRL_Bits.OSM */
+#define IFX_GTM_TIM_CH_CTRL_OSM_OFF (4u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_CTRL_Bits.TBU0_SEL */
+#define IFX_GTM_TIM_CH_CTRL_TBU0_SEL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_CTRL_Bits.TBU0_SEL */
+#define IFX_GTM_TIM_CH_CTRL_TBU0_SEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_CTRL_Bits.TBU0_SEL */
+#define IFX_GTM_TIM_CH_CTRL_TBU0_SEL_OFF (7u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_CTRL_Bits.TIM_EN */
+#define IFX_GTM_TIM_CH_CTRL_TIM_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_CTRL_Bits.TIM_EN */
+#define IFX_GTM_TIM_CH_CTRL_TIM_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_CTRL_Bits.TIM_EN */
+#define IFX_GTM_TIM_CH_CTRL_TIM_EN_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_CTRL_Bits.TIM_MODE */
+#define IFX_GTM_TIM_CH_CTRL_TIM_MODE_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_CTRL_Bits.TIM_MODE */
+#define IFX_GTM_TIM_CH_CTRL_TIM_MODE_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_CTRL_Bits.TIM_MODE */
+#define IFX_GTM_TIM_CH_CTRL_TIM_MODE_OFF (1u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_CTRL_Bits.TOCTRL */
+#define IFX_GTM_TIM_CH_CTRL_TOCTRL_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_CTRL_Bits.TOCTRL */
+#define IFX_GTM_TIM_CH_CTRL_TOCTRL_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_CTRL_Bits.TOCTRL */
+#define IFX_GTM_TIM_CH_CTRL_TOCTRL_OFF (30u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_ECNT_Bits.ECNT */
+#define IFX_GTM_TIM_CH_ECNT_ECNT_LEN (16u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_ECNT_Bits.ECNT */
+#define IFX_GTM_TIM_CH_ECNT_ECNT_MSK (0xffffu)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_ECNT_Bits.ECNT */
+#define IFX_GTM_TIM_CH_ECNT_ECNT_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_ECTRL_Bits.EXT_CAP_SRC */
+#define IFX_GTM_TIM_CH_ECTRL_EXT_CAP_SRC_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_ECTRL_Bits.EXT_CAP_SRC */
+#define IFX_GTM_TIM_CH_ECTRL_EXT_CAP_SRC_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_ECTRL_Bits.EXT_CAP_SRC */
+#define IFX_GTM_TIM_CH_ECTRL_EXT_CAP_SRC_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.CNTOFL_EIRQ_EN */
+#define IFX_GTM_TIM_CH_EIRQ_EN_CNTOFL_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.CNTOFL_EIRQ_EN */
+#define IFX_GTM_TIM_CH_EIRQ_EN_CNTOFL_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.CNTOFL_EIRQ_EN */
+#define IFX_GTM_TIM_CH_EIRQ_EN_CNTOFL_EIRQ_EN_OFF (2u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.ECNTOFL_EIRQ_EN */
+#define IFX_GTM_TIM_CH_EIRQ_EN_ECNTOFL_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.ECNTOFL_EIRQ_EN */
+#define IFX_GTM_TIM_CH_EIRQ_EN_ECNTOFL_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.ECNTOFL_EIRQ_EN */
+#define IFX_GTM_TIM_CH_EIRQ_EN_ECNTOFL_EIRQ_EN_OFF (1u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.GLITCHDET_EIRQ_EN */
+#define IFX_GTM_TIM_CH_EIRQ_EN_GLITCHDET_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.GLITCHDET_EIRQ_EN */
+#define IFX_GTM_TIM_CH_EIRQ_EN_GLITCHDET_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.GLITCHDET_EIRQ_EN */
+#define IFX_GTM_TIM_CH_EIRQ_EN_GLITCHDET_EIRQ_EN_OFF (5u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.GPROFL_EIRQ_EN */
+#define IFX_GTM_TIM_CH_EIRQ_EN_GPROFL_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.GPROFL_EIRQ_EN */
+#define IFX_GTM_TIM_CH_EIRQ_EN_GPROFL_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.GPROFL_EIRQ_EN */
+#define IFX_GTM_TIM_CH_EIRQ_EN_GPROFL_EIRQ_EN_OFF (3u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.NEWVAL_EIRQ_EN */
+#define IFX_GTM_TIM_CH_EIRQ_EN_NEWVAL_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.NEWVAL_EIRQ_EN */
+#define IFX_GTM_TIM_CH_EIRQ_EN_NEWVAL_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.NEWVAL_EIRQ_EN */
+#define IFX_GTM_TIM_CH_EIRQ_EN_NEWVAL_EIRQ_EN_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.TODET_EIRQ_EN */
+#define IFX_GTM_TIM_CH_EIRQ_EN_TODET_EIRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.TODET_EIRQ_EN */
+#define IFX_GTM_TIM_CH_EIRQ_EN_TODET_EIRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.TODET_EIRQ_EN */
+#define IFX_GTM_TIM_CH_EIRQ_EN_TODET_EIRQ_EN_OFF (4u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_FLT_FE_Bits.FLT_FE */
+#define IFX_GTM_TIM_CH_FLT_FE_FLT_FE_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_FLT_FE_Bits.FLT_FE */
+#define IFX_GTM_TIM_CH_FLT_FE_FLT_FE_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_FLT_FE_Bits.FLT_FE */
+#define IFX_GTM_TIM_CH_FLT_FE_FLT_FE_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_FLT_RE_Bits.FLT_RE */
+#define IFX_GTM_TIM_CH_FLT_RE_FLT_RE_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_FLT_RE_Bits.FLT_RE */
+#define IFX_GTM_TIM_CH_FLT_RE_FLT_RE_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_FLT_RE_Bits.FLT_RE */
+#define IFX_GTM_TIM_CH_FLT_RE_FLT_RE_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_GPR0_Bits.ECNT */
+#define IFX_GTM_TIM_CH_GPR0_ECNT_LEN (8u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_GPR0_Bits.ECNT */
+#define IFX_GTM_TIM_CH_GPR0_ECNT_MSK (0xffu)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_GPR0_Bits.ECNT */
+#define IFX_GTM_TIM_CH_GPR0_ECNT_OFF (24u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_GPR0_Bits.GPR0 */
+#define IFX_GTM_TIM_CH_GPR0_GPR0_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_GPR0_Bits.GPR0 */
+#define IFX_GTM_TIM_CH_GPR0_GPR0_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_GPR0_Bits.GPR0 */
+#define IFX_GTM_TIM_CH_GPR0_GPR0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_GPR1_Bits.ECNT */
+#define IFX_GTM_TIM_CH_GPR1_ECNT_LEN (8u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_GPR1_Bits.ECNT */
+#define IFX_GTM_TIM_CH_GPR1_ECNT_MSK (0xffu)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_GPR1_Bits.ECNT */
+#define IFX_GTM_TIM_CH_GPR1_ECNT_OFF (24u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_GPR1_Bits.GPR1 */
+#define IFX_GTM_TIM_CH_GPR1_GPR1_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_GPR1_Bits.GPR1 */
+#define IFX_GTM_TIM_CH_GPR1_GPR1_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_GPR1_Bits.GPR1 */
+#define IFX_GTM_TIM_CH_GPR1_GPR1_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_IRQ_EN_Bits.CNTOFL_IRQ_EN */
+#define IFX_GTM_TIM_CH_IRQ_EN_CNTOFL_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_IRQ_EN_Bits.CNTOFL_IRQ_EN */
+#define IFX_GTM_TIM_CH_IRQ_EN_CNTOFL_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_IRQ_EN_Bits.CNTOFL_IRQ_EN */
+#define IFX_GTM_TIM_CH_IRQ_EN_CNTOFL_IRQ_EN_OFF (2u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_IRQ_EN_Bits.ECNTOFL_IRQ_EN */
+#define IFX_GTM_TIM_CH_IRQ_EN_ECNTOFL_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_IRQ_EN_Bits.ECNTOFL_IRQ_EN */
+#define IFX_GTM_TIM_CH_IRQ_EN_ECNTOFL_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_IRQ_EN_Bits.ECNTOFL_IRQ_EN */
+#define IFX_GTM_TIM_CH_IRQ_EN_ECNTOFL_IRQ_EN_OFF (1u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_IRQ_EN_Bits.GLITCHDET_IRQ_EN */
+#define IFX_GTM_TIM_CH_IRQ_EN_GLITCHDET_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_IRQ_EN_Bits.GLITCHDET_IRQ_EN */
+#define IFX_GTM_TIM_CH_IRQ_EN_GLITCHDET_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_IRQ_EN_Bits.GLITCHDET_IRQ_EN */
+#define IFX_GTM_TIM_CH_IRQ_EN_GLITCHDET_IRQ_EN_OFF (5u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_IRQ_EN_Bits.GPROFL_IRQ_EN */
+#define IFX_GTM_TIM_CH_IRQ_EN_GPROFL_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_IRQ_EN_Bits.GPROFL_IRQ_EN */
+#define IFX_GTM_TIM_CH_IRQ_EN_GPROFL_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_IRQ_EN_Bits.GPROFL_IRQ_EN */
+#define IFX_GTM_TIM_CH_IRQ_EN_GPROFL_IRQ_EN_OFF (3u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_IRQ_EN_Bits.NEWVAL_IRQ_EN */
+#define IFX_GTM_TIM_CH_IRQ_EN_NEWVAL_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_IRQ_EN_Bits.NEWVAL_IRQ_EN */
+#define IFX_GTM_TIM_CH_IRQ_EN_NEWVAL_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_IRQ_EN_Bits.NEWVAL_IRQ_EN */
+#define IFX_GTM_TIM_CH_IRQ_EN_NEWVAL_IRQ_EN_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_IRQ_EN_Bits.TODET_IRQ_EN */
+#define IFX_GTM_TIM_CH_IRQ_EN_TODET_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_IRQ_EN_Bits.TODET_IRQ_EN */
+#define IFX_GTM_TIM_CH_IRQ_EN_TODET_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_IRQ_EN_Bits.TODET_IRQ_EN */
+#define IFX_GTM_TIM_CH_IRQ_EN_TODET_IRQ_EN_OFF (4u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_CNTOFL */
+#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_CNTOFL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_CNTOFL */
+#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_CNTOFL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_CNTOFL */
+#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_CNTOFL_OFF (2u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_ECNTOFL */
+#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_ECNTOFL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_ECNTOFL */
+#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_ECNTOFL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_ECNTOFL */
+#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_ECNTOFL_OFF (1u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_GLITCHDET */
+#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_GLITCHDET_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_GLITCHDET */
+#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_GLITCHDET_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_GLITCHDET */
+#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_GLITCHDET_OFF (5u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_GPROFL */
+#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_GPROFL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_GPROFL */
+#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_GPROFL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_GPROFL */
+#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_GPROFL_OFF (3u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_NEWVAL */
+#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_NEWVAL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_NEWVAL */
+#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_NEWVAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_NEWVAL */
+#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_NEWVAL_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_TODET */
+#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_TODET_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_TODET */
+#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_TODET_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_TODET */
+#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_TODET_OFF (4u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_TIM_CH_IRQ_MODE_IRQ_MODE_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_TIM_CH_IRQ_MODE_IRQ_MODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_TIM_CH_IRQ_MODE_IRQ_MODE_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.CNTOFL */
+#define IFX_GTM_TIM_CH_IRQ_NOTIFY_CNTOFL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.CNTOFL */
+#define IFX_GTM_TIM_CH_IRQ_NOTIFY_CNTOFL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.CNTOFL */
+#define IFX_GTM_TIM_CH_IRQ_NOTIFY_CNTOFL_OFF (2u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.ECNTOFL */
+#define IFX_GTM_TIM_CH_IRQ_NOTIFY_ECNTOFL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.ECNTOFL */
+#define IFX_GTM_TIM_CH_IRQ_NOTIFY_ECNTOFL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.ECNTOFL */
+#define IFX_GTM_TIM_CH_IRQ_NOTIFY_ECNTOFL_OFF (1u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.GLITCHDET */
+#define IFX_GTM_TIM_CH_IRQ_NOTIFY_GLITCHDET_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.GLITCHDET */
+#define IFX_GTM_TIM_CH_IRQ_NOTIFY_GLITCHDET_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.GLITCHDET */
+#define IFX_GTM_TIM_CH_IRQ_NOTIFY_GLITCHDET_OFF (5u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.GPROFL */
+#define IFX_GTM_TIM_CH_IRQ_NOTIFY_GPROFL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.GPROFL */
+#define IFX_GTM_TIM_CH_IRQ_NOTIFY_GPROFL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.GPROFL */
+#define IFX_GTM_TIM_CH_IRQ_NOTIFY_GPROFL_OFF (3u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.NEWVAL */
+#define IFX_GTM_TIM_CH_IRQ_NOTIFY_NEWVAL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.NEWVAL */
+#define IFX_GTM_TIM_CH_IRQ_NOTIFY_NEWVAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.NEWVAL */
+#define IFX_GTM_TIM_CH_IRQ_NOTIFY_NEWVAL_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.TODET */
+#define IFX_GTM_TIM_CH_IRQ_NOTIFY_TODET_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.TODET */
+#define IFX_GTM_TIM_CH_IRQ_NOTIFY_TODET_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.TODET */
+#define IFX_GTM_TIM_CH_IRQ_NOTIFY_TODET_OFF (4u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_TDUC_Bits.TO_CNT */
+#define IFX_GTM_TIM_CH_TDUC_TO_CNT_LEN (8u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_TDUC_Bits.TO_CNT */
+#define IFX_GTM_TIM_CH_TDUC_TO_CNT_MSK (0xffu)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_TDUC_Bits.TO_CNT */
+#define IFX_GTM_TIM_CH_TDUC_TO_CNT_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_TDUV_Bits.TCS */
+#define IFX_GTM_TIM_CH_TDUV_TCS_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_TDUV_Bits.TCS */
+#define IFX_GTM_TIM_CH_TDUV_TCS_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_TDUV_Bits.TCS */
+#define IFX_GTM_TIM_CH_TDUV_TCS_OFF (28u)
+
+/** \brief Length for Ifx_GTM_TIM_CH_TDUV_Bits.TOV */
+#define IFX_GTM_TIM_CH_TDUV_TOV_LEN (8u)
+
+/** \brief Mask for Ifx_GTM_TIM_CH_TDUV_Bits.TOV */
+#define IFX_GTM_TIM_CH_TDUV_TOV_MSK (0xffu)
+
+/** \brief Offset for Ifx_GTM_TIM_CH_TDUV_Bits.TOV */
+#define IFX_GTM_TIM_CH_TDUV_TOV_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TIM_IN_SRC_Bits.MODE_0 */
+#define IFX_GTM_TIM_IN_SRC_MODE_0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TIM_IN_SRC_Bits.MODE_0 */
+#define IFX_GTM_TIM_IN_SRC_MODE_0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TIM_IN_SRC_Bits.MODE_0 */
+#define IFX_GTM_TIM_IN_SRC_MODE_0_OFF (2u)
+
+/** \brief Length for Ifx_GTM_TIM_IN_SRC_Bits.MODE_1 */
+#define IFX_GTM_TIM_IN_SRC_MODE_1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TIM_IN_SRC_Bits.MODE_1 */
+#define IFX_GTM_TIM_IN_SRC_MODE_1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TIM_IN_SRC_Bits.MODE_1 */
+#define IFX_GTM_TIM_IN_SRC_MODE_1_OFF (6u)
+
+/** \brief Length for Ifx_GTM_TIM_IN_SRC_Bits.MODE_2 */
+#define IFX_GTM_TIM_IN_SRC_MODE_2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TIM_IN_SRC_Bits.MODE_2 */
+#define IFX_GTM_TIM_IN_SRC_MODE_2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TIM_IN_SRC_Bits.MODE_2 */
+#define IFX_GTM_TIM_IN_SRC_MODE_2_OFF (10u)
+
+/** \brief Length for Ifx_GTM_TIM_IN_SRC_Bits.MODE_3 */
+#define IFX_GTM_TIM_IN_SRC_MODE_3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TIM_IN_SRC_Bits.MODE_3 */
+#define IFX_GTM_TIM_IN_SRC_MODE_3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TIM_IN_SRC_Bits.MODE_3 */
+#define IFX_GTM_TIM_IN_SRC_MODE_3_OFF (14u)
+
+/** \brief Length for Ifx_GTM_TIM_IN_SRC_Bits.MODE_4 */
+#define IFX_GTM_TIM_IN_SRC_MODE_4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TIM_IN_SRC_Bits.MODE_4 */
+#define IFX_GTM_TIM_IN_SRC_MODE_4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TIM_IN_SRC_Bits.MODE_4 */
+#define IFX_GTM_TIM_IN_SRC_MODE_4_OFF (18u)
+
+/** \brief Length for Ifx_GTM_TIM_IN_SRC_Bits.MODE_5 */
+#define IFX_GTM_TIM_IN_SRC_MODE_5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TIM_IN_SRC_Bits.MODE_5 */
+#define IFX_GTM_TIM_IN_SRC_MODE_5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TIM_IN_SRC_Bits.MODE_5 */
+#define IFX_GTM_TIM_IN_SRC_MODE_5_OFF (22u)
+
+/** \brief Length for Ifx_GTM_TIM_IN_SRC_Bits.MODE_6 */
+#define IFX_GTM_TIM_IN_SRC_MODE_6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TIM_IN_SRC_Bits.MODE_6 */
+#define IFX_GTM_TIM_IN_SRC_MODE_6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TIM_IN_SRC_Bits.MODE_6 */
+#define IFX_GTM_TIM_IN_SRC_MODE_6_OFF (26u)
+
+/** \brief Length for Ifx_GTM_TIM_IN_SRC_Bits.MODE_7 */
+#define IFX_GTM_TIM_IN_SRC_MODE_7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TIM_IN_SRC_Bits.MODE_7 */
+#define IFX_GTM_TIM_IN_SRC_MODE_7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TIM_IN_SRC_Bits.MODE_7 */
+#define IFX_GTM_TIM_IN_SRC_MODE_7_OFF (30u)
+
+/** \brief Length for Ifx_GTM_TIM_IN_SRC_Bits.VAL_0 */
+#define IFX_GTM_TIM_IN_SRC_VAL_0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TIM_IN_SRC_Bits.VAL_0 */
+#define IFX_GTM_TIM_IN_SRC_VAL_0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TIM_IN_SRC_Bits.VAL_0 */
+#define IFX_GTM_TIM_IN_SRC_VAL_0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TIM_IN_SRC_Bits.VAL_1 */
+#define IFX_GTM_TIM_IN_SRC_VAL_1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TIM_IN_SRC_Bits.VAL_1 */
+#define IFX_GTM_TIM_IN_SRC_VAL_1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TIM_IN_SRC_Bits.VAL_1 */
+#define IFX_GTM_TIM_IN_SRC_VAL_1_OFF (4u)
+
+/** \brief Length for Ifx_GTM_TIM_IN_SRC_Bits.VAL_2 */
+#define IFX_GTM_TIM_IN_SRC_VAL_2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TIM_IN_SRC_Bits.VAL_2 */
+#define IFX_GTM_TIM_IN_SRC_VAL_2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TIM_IN_SRC_Bits.VAL_2 */
+#define IFX_GTM_TIM_IN_SRC_VAL_2_OFF (8u)
+
+/** \brief Length for Ifx_GTM_TIM_IN_SRC_Bits.VAL_3 */
+#define IFX_GTM_TIM_IN_SRC_VAL_3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TIM_IN_SRC_Bits.VAL_3 */
+#define IFX_GTM_TIM_IN_SRC_VAL_3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TIM_IN_SRC_Bits.VAL_3 */
+#define IFX_GTM_TIM_IN_SRC_VAL_3_OFF (12u)
+
+/** \brief Length for Ifx_GTM_TIM_IN_SRC_Bits.VAL_4 */
+#define IFX_GTM_TIM_IN_SRC_VAL_4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TIM_IN_SRC_Bits.VAL_4 */
+#define IFX_GTM_TIM_IN_SRC_VAL_4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TIM_IN_SRC_Bits.VAL_4 */
+#define IFX_GTM_TIM_IN_SRC_VAL_4_OFF (16u)
+
+/** \brief Length for Ifx_GTM_TIM_IN_SRC_Bits.VAL_5 */
+#define IFX_GTM_TIM_IN_SRC_VAL_5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TIM_IN_SRC_Bits.VAL_5 */
+#define IFX_GTM_TIM_IN_SRC_VAL_5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TIM_IN_SRC_Bits.VAL_5 */
+#define IFX_GTM_TIM_IN_SRC_VAL_5_OFF (20u)
+
+/** \brief Length for Ifx_GTM_TIM_IN_SRC_Bits.VAL_6 */
+#define IFX_GTM_TIM_IN_SRC_VAL_6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TIM_IN_SRC_Bits.VAL_6 */
+#define IFX_GTM_TIM_IN_SRC_VAL_6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TIM_IN_SRC_Bits.VAL_6 */
+#define IFX_GTM_TIM_IN_SRC_VAL_6_OFF (24u)
+
+/** \brief Length for Ifx_GTM_TIM_IN_SRC_Bits.VAL_7 */
+#define IFX_GTM_TIM_IN_SRC_VAL_7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TIM_IN_SRC_Bits.VAL_7 */
+#define IFX_GTM_TIM_IN_SRC_VAL_7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TIM_IN_SRC_Bits.VAL_7 */
+#define IFX_GTM_TIM_IN_SRC_VAL_7_OFF (28u)
+
+/** \brief Length for Ifx_GTM_TIM_RST_Bits.RST_CH0 */
+#define IFX_GTM_TIM_RST_RST_CH0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_RST_Bits.RST_CH0 */
+#define IFX_GTM_TIM_RST_RST_CH0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_RST_Bits.RST_CH0 */
+#define IFX_GTM_TIM_RST_RST_CH0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TIM_RST_Bits.RST_CH1 */
+#define IFX_GTM_TIM_RST_RST_CH1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_RST_Bits.RST_CH1 */
+#define IFX_GTM_TIM_RST_RST_CH1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_RST_Bits.RST_CH1 */
+#define IFX_GTM_TIM_RST_RST_CH1_OFF (1u)
+
+/** \brief Length for Ifx_GTM_TIM_RST_Bits.RST_CH2 */
+#define IFX_GTM_TIM_RST_RST_CH2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_RST_Bits.RST_CH2 */
+#define IFX_GTM_TIM_RST_RST_CH2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_RST_Bits.RST_CH2 */
+#define IFX_GTM_TIM_RST_RST_CH2_OFF (2u)
+
+/** \brief Length for Ifx_GTM_TIM_RST_Bits.RST_CH3 */
+#define IFX_GTM_TIM_RST_RST_CH3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_RST_Bits.RST_CH3 */
+#define IFX_GTM_TIM_RST_RST_CH3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_RST_Bits.RST_CH3 */
+#define IFX_GTM_TIM_RST_RST_CH3_OFF (3u)
+
+/** \brief Length for Ifx_GTM_TIM_RST_Bits.RST_CH4 */
+#define IFX_GTM_TIM_RST_RST_CH4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_RST_Bits.RST_CH4 */
+#define IFX_GTM_TIM_RST_RST_CH4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_RST_Bits.RST_CH4 */
+#define IFX_GTM_TIM_RST_RST_CH4_OFF (4u)
+
+/** \brief Length for Ifx_GTM_TIM_RST_Bits.RST_CH5 */
+#define IFX_GTM_TIM_RST_RST_CH5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_RST_Bits.RST_CH5 */
+#define IFX_GTM_TIM_RST_RST_CH5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_RST_Bits.RST_CH5 */
+#define IFX_GTM_TIM_RST_RST_CH5_OFF (5u)
+
+/** \brief Length for Ifx_GTM_TIM_RST_Bits.RST_CH6 */
+#define IFX_GTM_TIM_RST_RST_CH6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_RST_Bits.RST_CH6 */
+#define IFX_GTM_TIM_RST_RST_CH6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_RST_Bits.RST_CH6 */
+#define IFX_GTM_TIM_RST_RST_CH6_OFF (6u)
+
+/** \brief Length for Ifx_GTM_TIM_RST_Bits.RST_CH7 */
+#define IFX_GTM_TIM_RST_RST_CH7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TIM_RST_Bits.RST_CH7 */
+#define IFX_GTM_TIM_RST_RST_CH7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TIM_RST_Bits.RST_CH7 */
+#define IFX_GTM_TIM_RST_RST_CH7_OFF (7u)
+
+/** \brief Length for Ifx_GTM_TOM_CH_CM0_Bits.CM0 */
+#define IFX_GTM_TOM_CH_CM0_CM0_LEN (16u)
+
+/** \brief Mask for Ifx_GTM_TOM_CH_CM0_Bits.CM0 */
+#define IFX_GTM_TOM_CH_CM0_CM0_MSK (0xffffu)
+
+/** \brief Offset for Ifx_GTM_TOM_CH_CM0_Bits.CM0 */
+#define IFX_GTM_TOM_CH_CM0_CM0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TOM_CH_CM1_Bits.CM1 */
+#define IFX_GTM_TOM_CH_CM1_CM1_LEN (16u)
+
+/** \brief Mask for Ifx_GTM_TOM_CH_CM1_Bits.CM1 */
+#define IFX_GTM_TOM_CH_CM1_CM1_MSK (0xffffu)
+
+/** \brief Offset for Ifx_GTM_TOM_CH_CM1_Bits.CM1 */
+#define IFX_GTM_TOM_CH_CM1_CM1_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TOM_CH_CN0_Bits.CN0 */
+#define IFX_GTM_TOM_CH_CN0_CN0_LEN (16u)
+
+/** \brief Mask for Ifx_GTM_TOM_CH_CN0_Bits.CN0 */
+#define IFX_GTM_TOM_CH_CN0_CN0_MSK (0xffffu)
+
+/** \brief Offset for Ifx_GTM_TOM_CH_CN0_Bits.CN0 */
+#define IFX_GTM_TOM_CH_CN0_CN0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TOM_CH_CTRL_Bits.BITREV */
+#define IFX_GTM_TOM_CH_CTRL_BITREV_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_CH_CTRL_Bits.BITREV */
+#define IFX_GTM_TOM_CH_CTRL_BITREV_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_CH_CTRL_Bits.BITREV */
+#define IFX_GTM_TOM_CH_CTRL_BITREV_OFF (27u)
+
+/** \brief Length for Ifx_GTM_TOM_CH_CTRL_Bits.CLK_SRC_SR */
+#define IFX_GTM_TOM_CH_CTRL_CLK_SRC_SR_LEN (3u)
+
+/** \brief Mask for Ifx_GTM_TOM_CH_CTRL_Bits.CLK_SRC_SR */
+#define IFX_GTM_TOM_CH_CTRL_CLK_SRC_SR_MSK (0x7u)
+
+/** \brief Offset for Ifx_GTM_TOM_CH_CTRL_Bits.CLK_SRC_SR */
+#define IFX_GTM_TOM_CH_CTRL_CLK_SRC_SR_OFF (12u)
+
+/** \brief Length for Ifx_GTM_TOM_CH_CTRL_Bits.GCM */
+#define IFX_GTM_TOM_CH_CTRL_GCM_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_CH_CTRL_Bits.GCM */
+#define IFX_GTM_TOM_CH_CTRL_GCM_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_CH_CTRL_Bits.GCM */
+#define IFX_GTM_TOM_CH_CTRL_GCM_OFF (29u)
+
+/** \brief Length for Ifx_GTM_TOM_CH_CTRL_Bits.OSM */
+#define IFX_GTM_TOM_CH_CTRL_OSM_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_CH_CTRL_Bits.OSM */
+#define IFX_GTM_TOM_CH_CTRL_OSM_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_CH_CTRL_Bits.OSM */
+#define IFX_GTM_TOM_CH_CTRL_OSM_OFF (26u)
+
+/** \brief Length for Ifx_GTM_TOM_CH_CTRL_Bits.RST_CCU0 */
+#define IFX_GTM_TOM_CH_CTRL_RST_CCU0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_CH_CTRL_Bits.RST_CCU0 */
+#define IFX_GTM_TOM_CH_CTRL_RST_CCU0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_CH_CTRL_Bits.RST_CCU0 */
+#define IFX_GTM_TOM_CH_CTRL_RST_CCU0_OFF (20u)
+
+/** \brief Length for Ifx_GTM_TOM_CH_CTRL_Bits.SL */
+#define IFX_GTM_TOM_CH_CTRL_SL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_CH_CTRL_Bits.SL */
+#define IFX_GTM_TOM_CH_CTRL_SL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_CH_CTRL_Bits.SL */
+#define IFX_GTM_TOM_CH_CTRL_SL_OFF (11u)
+
+/** \brief Length for Ifx_GTM_TOM_CH_CTRL_Bits.SPEM */
+#define IFX_GTM_TOM_CH_CTRL_SPEM_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_CH_CTRL_Bits.SPEM */
+#define IFX_GTM_TOM_CH_CTRL_SPEM_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_CH_CTRL_Bits.SPEM */
+#define IFX_GTM_TOM_CH_CTRL_SPEM_OFF (28u)
+
+/** \brief Length for Ifx_GTM_TOM_CH_CTRL_Bits.TRIGOUT */
+#define IFX_GTM_TOM_CH_CTRL_TRIGOUT_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_CH_CTRL_Bits.TRIGOUT */
+#define IFX_GTM_TOM_CH_CTRL_TRIGOUT_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_CH_CTRL_Bits.TRIGOUT */
+#define IFX_GTM_TOM_CH_CTRL_TRIGOUT_OFF (24u)
+
+/** \brief Length for Ifx_GTM_TOM_CH_IRQ_EN_Bits.CCU0TC_IRQ_EN */
+#define IFX_GTM_TOM_CH_IRQ_EN_CCU0TC_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_CH_IRQ_EN_Bits.CCU0TC_IRQ_EN */
+#define IFX_GTM_TOM_CH_IRQ_EN_CCU0TC_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_CH_IRQ_EN_Bits.CCU0TC_IRQ_EN */
+#define IFX_GTM_TOM_CH_IRQ_EN_CCU0TC_IRQ_EN_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TOM_CH_IRQ_EN_Bits.CCU1TC_IRQ_EN */
+#define IFX_GTM_TOM_CH_IRQ_EN_CCU1TC_IRQ_EN_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_CH_IRQ_EN_Bits.CCU1TC_IRQ_EN */
+#define IFX_GTM_TOM_CH_IRQ_EN_CCU1TC_IRQ_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_CH_IRQ_EN_Bits.CCU1TC_IRQ_EN */
+#define IFX_GTM_TOM_CH_IRQ_EN_CCU1TC_IRQ_EN_OFF (1u)
+
+/** \brief Length for Ifx_GTM_TOM_CH_IRQ_FORCINT_Bits.TRG_CCU0TC0 */
+#define IFX_GTM_TOM_CH_IRQ_FORCINT_TRG_CCU0TC0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_CH_IRQ_FORCINT_Bits.TRG_CCU0TC0 */
+#define IFX_GTM_TOM_CH_IRQ_FORCINT_TRG_CCU0TC0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_CH_IRQ_FORCINT_Bits.TRG_CCU0TC0 */
+#define IFX_GTM_TOM_CH_IRQ_FORCINT_TRG_CCU0TC0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TOM_CH_IRQ_FORCINT_Bits.TRG_CCU1TC0 */
+#define IFX_GTM_TOM_CH_IRQ_FORCINT_TRG_CCU1TC0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_CH_IRQ_FORCINT_Bits.TRG_CCU1TC0 */
+#define IFX_GTM_TOM_CH_IRQ_FORCINT_TRG_CCU1TC0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_CH_IRQ_FORCINT_Bits.TRG_CCU1TC0 */
+#define IFX_GTM_TOM_CH_IRQ_FORCINT_TRG_CCU1TC0_OFF (1u)
+
+/** \brief Length for Ifx_GTM_TOM_CH_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_TOM_CH_IRQ_MODE_IRQ_MODE_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_CH_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_TOM_CH_IRQ_MODE_IRQ_MODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_CH_IRQ_MODE_Bits.IRQ_MODE */
+#define IFX_GTM_TOM_CH_IRQ_MODE_IRQ_MODE_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TOM_CH_IRQ_NOTIFY_Bits.CCU0TC */
+#define IFX_GTM_TOM_CH_IRQ_NOTIFY_CCU0TC_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_CH_IRQ_NOTIFY_Bits.CCU0TC */
+#define IFX_GTM_TOM_CH_IRQ_NOTIFY_CCU0TC_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_CH_IRQ_NOTIFY_Bits.CCU0TC */
+#define IFX_GTM_TOM_CH_IRQ_NOTIFY_CCU0TC_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TOM_CH_IRQ_NOTIFY_Bits.CCU1TC */
+#define IFX_GTM_TOM_CH_IRQ_NOTIFY_CCU1TC_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_CH_IRQ_NOTIFY_Bits.CCU1TC */
+#define IFX_GTM_TOM_CH_IRQ_NOTIFY_CCU1TC_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_CH_IRQ_NOTIFY_Bits.CCU1TC */
+#define IFX_GTM_TOM_CH_IRQ_NOTIFY_CCU1TC_OFF (1u)
+
+/** \brief Length for Ifx_GTM_TOM_CH_SR0_Bits.SR0 */
+#define IFX_GTM_TOM_CH_SR0_SR0_LEN (16u)
+
+/** \brief Mask for Ifx_GTM_TOM_CH_SR0_Bits.SR0 */
+#define IFX_GTM_TOM_CH_SR0_SR0_MSK (0xffffu)
+
+/** \brief Offset for Ifx_GTM_TOM_CH_SR0_Bits.SR0 */
+#define IFX_GTM_TOM_CH_SR0_SR0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TOM_CH_SR1_Bits.SR1 */
+#define IFX_GTM_TOM_CH_SR1_SR1_LEN (16u)
+
+/** \brief Mask for Ifx_GTM_TOM_CH_SR1_Bits.SR1 */
+#define IFX_GTM_TOM_CH_SR1_SR1_MSK (0xffffu)
+
+/** \brief Offset for Ifx_GTM_TOM_CH_SR1_Bits.SR1 */
+#define IFX_GTM_TOM_CH_SR1_SR1_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TOM_CH_STAT_Bits.OL */
+#define IFX_GTM_TOM_CH_STAT_OL_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_CH_STAT_Bits.OL */
+#define IFX_GTM_TOM_CH_STAT_OL_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_CH_STAT_Bits.OL */
+#define IFX_GTM_TOM_CH_STAT_OL_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_ACT_TB_Bits.ACT_TB */
+#define IFX_GTM_TOM_TGC0_ACT_TB_ACT_TB_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_ACT_TB_Bits.ACT_TB */
+#define IFX_GTM_TOM_TGC0_ACT_TB_ACT_TB_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_ACT_TB_Bits.ACT_TB */
+#define IFX_GTM_TOM_TGC0_ACT_TB_ACT_TB_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_ACT_TB_Bits.TB_TRIG */
+#define IFX_GTM_TOM_TGC0_ACT_TB_TB_TRIG_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_ACT_TB_Bits.TB_TRIG */
+#define IFX_GTM_TOM_TGC0_ACT_TB_TB_TRIG_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_ACT_TB_Bits.TB_TRIG */
+#define IFX_GTM_TOM_TGC0_ACT_TB_TB_TRIG_OFF (24u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_ACT_TB_Bits.TBU_SEL */
+#define IFX_GTM_TOM_TGC0_ACT_TB_TBU_SEL_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_ACT_TB_Bits.TBU_SEL */
+#define IFX_GTM_TOM_TGC0_ACT_TB_TBU_SEL_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_ACT_TB_Bits.TBU_SEL */
+#define IFX_GTM_TOM_TGC0_ACT_TB_TBU_SEL_OFF (25u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL0 */
+#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL0 */
+#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL0 */
+#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL1 */
+#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL1 */
+#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL1 */
+#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL2 */
+#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL2 */
+#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL2 */
+#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL2_OFF (4u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL3 */
+#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL3 */
+#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL3 */
+#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL3_OFF (6u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL4 */
+#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL4 */
+#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL4 */
+#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL4_OFF (8u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL5 */
+#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL5 */
+#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL5 */
+#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL5_OFF (10u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL6 */
+#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL6 */
+#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL6 */
+#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL6_OFF (12u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL7 */
+#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL7 */
+#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL7 */
+#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL7_OFF (14u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT0 */
+#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT0 */
+#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT0 */
+#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT1 */
+#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT1 */
+#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT1 */
+#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT2 */
+#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT2 */
+#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT2 */
+#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT2_OFF (4u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT3 */
+#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT3 */
+#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT3 */
+#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT3_OFF (6u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT4 */
+#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT4 */
+#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT4 */
+#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT4_OFF (8u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT5 */
+#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT5 */
+#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT5 */
+#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT5_OFF (10u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT6 */
+#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT6 */
+#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT6 */
+#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT6_OFF (12u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT7 */
+#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT7 */
+#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT7 */
+#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT7_OFF (14u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL0 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL0 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL0 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL1 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL1 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL1 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL2 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL2 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL2 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL2_OFF (4u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL3 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL3 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL3 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL3_OFF (6u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL4 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL4 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL4 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL4_OFF (8u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL5 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL5 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL5 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL5_OFF (10u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL6 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL6 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL6 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL6_OFF (12u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL7 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL7 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL7 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL7_OFF (14u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH0 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH0 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH0 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH0_OFF (16u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH1 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH1 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH1 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH1_OFF (18u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH2 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH2 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH2 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH2_OFF (20u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH3 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH3 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH3 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH3_OFF (22u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH4 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH4 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH4 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH4_OFF (24u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH5 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH5 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH5 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH5_OFF (26u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH6 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH6 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH6 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH6_OFF (28u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH7 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH7 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH7 */
+#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH7_OFF (30u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.HOST_TRIG */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_HOST_TRIG_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.HOST_TRIG */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_HOST_TRIG_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.HOST_TRIG */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_HOST_TRIG_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH0 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH0 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH0 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH0_OFF (8u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH1 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH1 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH1 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH1_OFF (9u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH2 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH2 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH2 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH2_OFF (10u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH3 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH3 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH3 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH3_OFF (11u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH4 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH4 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH4 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH4_OFF (12u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH5 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH5 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH5 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH5_OFF (13u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH6 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH6 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH6 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH6_OFF (14u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH7 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH7 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH7 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH7_OFF (15u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL0 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL0 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL0 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL0_OFF (16u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL1 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL1 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL1 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL1_OFF (18u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL2 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL2 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL2 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL2_OFF (20u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL3 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL3 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL3 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL3_OFF (22u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL4 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL4 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL4 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL4_OFF (24u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL5 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL5 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL5 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL5_OFF (26u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL6 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL6 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL6 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL6_OFF (28u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL7 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL7 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL7 */
+#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL7_OFF (30u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG0 */
+#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG0 */
+#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG0 */
+#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG1 */
+#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG1 */
+#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG1 */
+#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG2 */
+#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG2 */
+#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG2 */
+#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG2_OFF (4u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG3 */
+#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG3 */
+#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG3 */
+#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG3_OFF (6u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG4 */
+#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG4 */
+#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG4 */
+#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG4_OFF (8u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG5 */
+#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG5 */
+#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG5 */
+#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG5_OFF (10u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG6 */
+#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG6 */
+#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG6 */
+#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG6_OFF (12u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG7 */
+#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG7 */
+#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG7 */
+#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG7_OFF (14u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL0 */
+#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL0 */
+#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL0 */
+#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL1 */
+#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL1 */
+#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL1 */
+#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL2 */
+#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL2 */
+#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL2 */
+#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL2_OFF (4u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL3 */
+#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL3 */
+#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL3 */
+#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL3_OFF (6u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL4 */
+#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL4 */
+#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL4 */
+#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL4_OFF (8u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL5 */
+#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL5 */
+#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL5 */
+#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL5_OFF (10u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL6 */
+#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL6 */
+#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL6 */
+#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL6_OFF (12u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL7 */
+#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL7 */
+#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL7 */
+#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL7_OFF (14u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT0 */
+#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT0 */
+#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT0 */
+#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT1 */
+#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT1 */
+#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT1 */
+#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT2 */
+#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT2 */
+#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT2 */
+#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT2_OFF (4u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT3 */
+#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT3 */
+#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT3 */
+#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT3_OFF (6u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT4 */
+#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT4 */
+#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT4 */
+#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT4_OFF (8u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT5 */
+#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT5 */
+#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT5 */
+#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT5_OFF (10u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT6 */
+#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT6 */
+#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT6 */
+#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT6_OFF (12u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT7 */
+#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT7 */
+#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT7 */
+#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT7_OFF (14u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_ACT_TB_Bits.ACT_TB */
+#define IFX_GTM_TOM_TGC1_ACT_TB_ACT_TB_LEN (24u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_ACT_TB_Bits.ACT_TB */
+#define IFX_GTM_TOM_TGC1_ACT_TB_ACT_TB_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_ACT_TB_Bits.ACT_TB */
+#define IFX_GTM_TOM_TGC1_ACT_TB_ACT_TB_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_ACT_TB_Bits.TB_TRIG */
+#define IFX_GTM_TOM_TGC1_ACT_TB_TB_TRIG_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_ACT_TB_Bits.TB_TRIG */
+#define IFX_GTM_TOM_TGC1_ACT_TB_TB_TRIG_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_ACT_TB_Bits.TB_TRIG */
+#define IFX_GTM_TOM_TGC1_ACT_TB_TB_TRIG_OFF (24u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_ACT_TB_Bits.TBU_SEL */
+#define IFX_GTM_TOM_TGC1_ACT_TB_TBU_SEL_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_ACT_TB_Bits.TBU_SEL */
+#define IFX_GTM_TOM_TGC1_ACT_TB_TBU_SEL_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_ACT_TB_Bits.TBU_SEL */
+#define IFX_GTM_TOM_TGC1_ACT_TB_TBU_SEL_OFF (25u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL0 */
+#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL0 */
+#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL0 */
+#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL1 */
+#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL1 */
+#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL1 */
+#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL2 */
+#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL2 */
+#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL2 */
+#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL2_OFF (4u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL3 */
+#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL3 */
+#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL3 */
+#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL3_OFF (6u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL4 */
+#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL4 */
+#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL4 */
+#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL4_OFF (8u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL5 */
+#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL5 */
+#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL5 */
+#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL5_OFF (10u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL6 */
+#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL6 */
+#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL6 */
+#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL6_OFF (12u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL7 */
+#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL7 */
+#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL7 */
+#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL7_OFF (14u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT0 */
+#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT0 */
+#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT0 */
+#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT1 */
+#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT1 */
+#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT1 */
+#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT2 */
+#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT2 */
+#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT2 */
+#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT2_OFF (4u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT3 */
+#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT3 */
+#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT3 */
+#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT3_OFF (6u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT4 */
+#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT4 */
+#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT4 */
+#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT4_OFF (8u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT5 */
+#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT5 */
+#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT5 */
+#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT5_OFF (10u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT6 */
+#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT6 */
+#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT6 */
+#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT6_OFF (12u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT7 */
+#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT7 */
+#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT7 */
+#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT7_OFF (14u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL0 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL0 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL0 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL1 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL1 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL1 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL2 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL2 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL2 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL2_OFF (4u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL3 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL3 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL3 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL3_OFF (6u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL4 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL4 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL4 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL4_OFF (8u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL5 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL5 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL5 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL5_OFF (10u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL6 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL6 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL6 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL6_OFF (12u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL7 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL7 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL7 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL7_OFF (14u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH0 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH0 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH0 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH0_OFF (16u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH1 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH1 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH1 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH1_OFF (18u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH2 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH2 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH2 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH2_OFF (20u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH3 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH3 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH3 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH3_OFF (22u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH4 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH4 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH4 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH4_OFF (24u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH5 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH5 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH5 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH5_OFF (26u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH6 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH6 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH6 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH6_OFF (28u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH7 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH7 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH7 */
+#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH7_OFF (30u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.HOST_TRIG */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_HOST_TRIG_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.HOST_TRIG */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_HOST_TRIG_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.HOST_TRIG */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_HOST_TRIG_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH0 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH0_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH0 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH0_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH0 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH0_OFF (8u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH1 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH1_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH1 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH1_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH1 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH1_OFF (9u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH2 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH2_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH2 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH2_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH2 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH2_OFF (10u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH3 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH3_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH3 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH3_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH3 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH3_OFF (11u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH4 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH4_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH4 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH4_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH4 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH4_OFF (12u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH5 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH5_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH5 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH5_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH5 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH5_OFF (13u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH6 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH6_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH6 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH6_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH6 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH6_OFF (14u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH7 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH7_LEN (1u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH7 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH7_MSK (0x1u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH7 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH7_OFF (15u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL0 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL0 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL0 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL0_OFF (16u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL1 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL1 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL1 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL1_OFF (18u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL2 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL2 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL2 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL2_OFF (20u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL3 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL3 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL3 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL3_OFF (22u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL4 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL4 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL4 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL4_OFF (24u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL5 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL5 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL5 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL5_OFF (26u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL6 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL6 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL6 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL6_OFF (28u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL7 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL7 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL7 */
+#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL7_OFF (30u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG0 */
+#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG0 */
+#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG0 */
+#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG1 */
+#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG1 */
+#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG1 */
+#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG2 */
+#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG2 */
+#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG2 */
+#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG2_OFF (4u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG3 */
+#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG3 */
+#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG3 */
+#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG3_OFF (6u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG4 */
+#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG4 */
+#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG4 */
+#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG4_OFF (8u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG5 */
+#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG5 */
+#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG5 */
+#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG5_OFF (10u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG6 */
+#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG6 */
+#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG6 */
+#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG6_OFF (12u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG7 */
+#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG7 */
+#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG7 */
+#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG7_OFF (14u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL0 */
+#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL0 */
+#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL0 */
+#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL1 */
+#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL1 */
+#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL1 */
+#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL2 */
+#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL2 */
+#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL2 */
+#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL2_OFF (4u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL3 */
+#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL3 */
+#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL3 */
+#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL3_OFF (6u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL4 */
+#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL4 */
+#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL4 */
+#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL4_OFF (8u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL5 */
+#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL5 */
+#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL5 */
+#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL5_OFF (10u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL6 */
+#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL6 */
+#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL6 */
+#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL6_OFF (12u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL7 */
+#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL7 */
+#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL7 */
+#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL7_OFF (14u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT0 */
+#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT0 */
+#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT0 */
+#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT1 */
+#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT1 */
+#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT1 */
+#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT2 */
+#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT2 */
+#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT2 */
+#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT2_OFF (4u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT3 */
+#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT3 */
+#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT3 */
+#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT3_OFF (6u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT4 */
+#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT4 */
+#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT4 */
+#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT4_OFF (8u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT5 */
+#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT5 */
+#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT5 */
+#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT5_OFF (10u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT6 */
+#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT6_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT6 */
+#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT6_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT6 */
+#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT6_OFF (12u)
+
+/** \brief Length for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT7 */
+#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT7_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT7 */
+#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT7_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT7 */
+#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT7_OFF (14u)
+
+/** \brief Length for Ifx_GTM_TRIGOUT_Bits.INT0 */
+#define IFX_GTM_TRIGOUT_INT0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TRIGOUT_Bits.INT0 */
+#define IFX_GTM_TRIGOUT_INT0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TRIGOUT_Bits.INT0 */
+#define IFX_GTM_TRIGOUT_INT0_OFF (0u)
+
+/** \brief Length for Ifx_GTM_TRIGOUT_Bits.INT1 */
+#define IFX_GTM_TRIGOUT_INT1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TRIGOUT_Bits.INT1 */
+#define IFX_GTM_TRIGOUT_INT1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TRIGOUT_Bits.INT1 */
+#define IFX_GTM_TRIGOUT_INT1_OFF (2u)
+
+/** \brief Length for Ifx_GTM_TRIGOUT_Bits.TRIG0 */
+#define IFX_GTM_TRIGOUT_TRIG0_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TRIGOUT_Bits.TRIG0 */
+#define IFX_GTM_TRIGOUT_TRIG0_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TRIGOUT_Bits.TRIG0 */
+#define IFX_GTM_TRIGOUT_TRIG0_OFF (4u)
+
+/** \brief Length for Ifx_GTM_TRIGOUT_Bits.TRIG1 */
+#define IFX_GTM_TRIGOUT_TRIG1_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TRIGOUT_Bits.TRIG1 */
+#define IFX_GTM_TRIGOUT_TRIG1_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TRIGOUT_Bits.TRIG1 */
+#define IFX_GTM_TRIGOUT_TRIG1_OFF (6u)
+
+/** \brief Length for Ifx_GTM_TRIGOUT_Bits.TRIG2 */
+#define IFX_GTM_TRIGOUT_TRIG2_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TRIGOUT_Bits.TRIG2 */
+#define IFX_GTM_TRIGOUT_TRIG2_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TRIGOUT_Bits.TRIG2 */
+#define IFX_GTM_TRIGOUT_TRIG2_OFF (8u)
+
+/** \brief Length for Ifx_GTM_TRIGOUT_Bits.TRIG3 */
+#define IFX_GTM_TRIGOUT_TRIG3_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TRIGOUT_Bits.TRIG3 */
+#define IFX_GTM_TRIGOUT_TRIG3_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TRIGOUT_Bits.TRIG3 */
+#define IFX_GTM_TRIGOUT_TRIG3_OFF (10u)
+
+/** \brief Length for Ifx_GTM_TRIGOUT_Bits.TRIG4 */
+#define IFX_GTM_TRIGOUT_TRIG4_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TRIGOUT_Bits.TRIG4 */
+#define IFX_GTM_TRIGOUT_TRIG4_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TRIGOUT_Bits.TRIG4 */
+#define IFX_GTM_TRIGOUT_TRIG4_OFF (12u)
+
+/** \brief Length for Ifx_GTM_TRIGOUT_Bits.TRIG5 */
+#define IFX_GTM_TRIGOUT_TRIG5_LEN (2u)
+
+/** \brief Mask for Ifx_GTM_TRIGOUT_Bits.TRIG5 */
+#define IFX_GTM_TRIGOUT_TRIG5_MSK (0x3u)
+
+/** \brief Offset for Ifx_GTM_TRIGOUT_Bits.TRIG5 */
+#define IFX_GTM_TRIGOUT_TRIG5_OFF (14u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXGTM_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxGtm_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxGtm_reg.h
new file mode 100644
index 0000000..d7f3e06
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxGtm_reg.h
@@ -0,0 +1,9076 @@
+/**
+ * \file IfxGtm_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Gtm_Cfg Gtm address
+ * \ingroup IfxLld_Gtm
+ *
+ * \defgroup IfxLld_Gtm_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Gtm_Cfg
+ *
+ * \defgroup IfxLld_Gtm_Cfg_Gtm 2-GTM
+ * \ingroup IfxLld_Gtm_Cfg
+ *
+ */
+#ifndef IFXGTM_REG_H
+#define IFXGTM_REG_H 1
+/******************************************************************************/
+#include "IfxGtm_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Gtm_Cfg_BaseAddress
+ * \{ */
+
+/** \brief GTM object */
+#define MODULE_GTM /*lint --e(923)*/ (*(Ifx_GTM*)0xF0100000u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Gtm_Cfg_Gtm
+ * \{ */
+
+/** \brief 9FDFC, Access Enable Register 0 */
+#define GTM_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ACCEN0*)0xF019FDFCu)
+
+/** \brief 9FDF8, Access Enable Register 1 */
+#define GTM_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ACCEN1*)0xF019FDF8u)
+
+/** \brief 9FDB0, ADC Trigger 0 Output Select 0 Register */
+#define GTM_ADCTRIG0OUT0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ADCTRIG0OUT0*)0xF019FDB0u)
+
+/** \brief 9FDB8, ADC Trigger 1 Output Select 0 Register */
+#define GTM_ADCTRIG1OUT0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ADCTRIG1OUT0*)0xF019FDB8u)
+
+/** \brief C, GTM AEI Timeout Exception Address Register */
+#define GTM_AEI_ADDR_XPT /*lint --e(923)*/ (*(volatile Ifx_GTM_AEI_ADDR_XPT*)0xF010000Cu)
+
+/** \brief 18080, AFD0 FIFO0 Channel Buffer Access Register */
+#define GTM_AFD0_CH0_BUF_ACC /*lint --e(923)*/ (*(volatile Ifx_GTM_AFD_CH_BUF_ACC*)0xF0118080u)
+
+/** \brief 18090, AFD0 FIFO0 Channel Buffer Access Register */
+#define GTM_AFD0_CH1_BUF_ACC /*lint --e(923)*/ (*(volatile Ifx_GTM_AFD_CH_BUF_ACC*)0xF0118090u)
+
+/** \brief 180A0, AFD0 FIFO0 Channel Buffer Access Register */
+#define GTM_AFD0_CH2_BUF_ACC /*lint --e(923)*/ (*(volatile Ifx_GTM_AFD_CH_BUF_ACC*)0xF01180A0u)
+
+/** \brief 180B0, AFD0 FIFO0 Channel Buffer Access Register */
+#define GTM_AFD0_CH3_BUF_ACC /*lint --e(923)*/ (*(volatile Ifx_GTM_AFD_CH_BUF_ACC*)0xF01180B0u)
+
+/** \brief 180C0, AFD0 FIFO0 Channel Buffer Access Register */
+#define GTM_AFD0_CH4_BUF_ACC /*lint --e(923)*/ (*(volatile Ifx_GTM_AFD_CH_BUF_ACC*)0xF01180C0u)
+
+/** \brief 180D0, AFD0 FIFO0 Channel Buffer Access Register */
+#define GTM_AFD0_CH5_BUF_ACC /*lint --e(923)*/ (*(volatile Ifx_GTM_AFD_CH_BUF_ACC*)0xF01180D0u)
+
+/** \brief 180E0, AFD0 FIFO0 Channel Buffer Access Register */
+#define GTM_AFD0_CH6_BUF_ACC /*lint --e(923)*/ (*(volatile Ifx_GTM_AFD_CH_BUF_ACC*)0xF01180E0u)
+
+/** \brief 180F0, AFD0 FIFO0 Channel Buffer Access Register */
+#define GTM_AFD0_CH7_BUF_ACC /*lint --e(923)*/ (*(volatile Ifx_GTM_AFD_CH_BUF_ACC*)0xF01180F0u)
+
+/** \brief 280, ARU Access Register */
+#define GTM_ARU_ARU_ACCESS /*lint --e(923)*/ (*(volatile Ifx_GTM_ARU_ARU_ACCESS*)0xF0100280u)
+
+/** Alias (User Manual Name) for GTM_ARU_ARU_ACCESS.
+* To use register names with standard convension, please use GTM_ARU_ARU_ACCESS.
+*/
+#define GTM_ARU_ACCESS (GTM_ARU_ARU_ACCESS)
+
+/** \brief 284, ARU Access Register Upper Data Word */
+#define GTM_ARU_DATA_H /*lint --e(923)*/ (*(volatile Ifx_GTM_ARU_DATA_H*)0xF0100284u)
+
+/** \brief 288, ARU Access Register Lower Data Word */
+#define GTM_ARU_DATA_L /*lint --e(923)*/ (*(volatile Ifx_GTM_ARU_DATA_L*)0xF0100288u)
+
+/** \brief 28C, Debug Access Channel 0 */
+#define GTM_ARU_DBG_ACCESS0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ARU_DBG_ACCESS0*)0xF010028Cu)
+
+/** \brief 298, Debug Access Channel 0 */
+#define GTM_ARU_DBG_ACCESS1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ARU_DBG_ACCESS1*)0xF0100298u)
+
+/** \brief 290, Debug Access 0 Transfer Register Upper Data Word */
+#define GTM_ARU_DBG_DATA0_H /*lint --e(923)*/ (*(volatile Ifx_GTM_ARU_DBG_DATA0_H*)0xF0100290u)
+
+/** \brief 294, Debug Access 0 Transfer Register Lower Data Word */
+#define GTM_ARU_DBG_DATA0_L /*lint --e(923)*/ (*(volatile Ifx_GTM_ARU_DBG_DATA0_L*)0xF0100294u)
+
+/** \brief 29C, Debug Access 1 Transfer Register Upper Data Word */
+#define GTM_ARU_DBG_DATA1_H /*lint --e(923)*/ (*(volatile Ifx_GTM_ARU_DBG_DATA1_H*)0xF010029Cu)
+
+/** \brief 2A0, Debug Access 1 Transfer Register Lower Data Word */
+#define GTM_ARU_DBG_DATA1_L /*lint --e(923)*/ (*(volatile Ifx_GTM_ARU_DBG_DATA1_L*)0xF01002A0u)
+
+/** \brief 2A8, ARU Interrupt Enable Register */
+#define GTM_ARU_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ARU_IRQ_EN*)0xF01002A8u)
+
+/** \brief 2AC, ARU_NEW_DATA_IRQ Forcing Interrupt Register */
+#define GTM_ARU_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ARU_IRQ_FORCINT*)0xF01002ACu)
+
+/** \brief 2B0, IRQ Mode Configuration Register */
+#define GTM_ARU_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ARU_IRQ_MODE*)0xF01002B0u)
+
+/** \brief 2A4, ARU Interrupt Notification Register */
+#define GTM_ARU_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ARU_IRQ_NOTIFY*)0xF01002A4u)
+
+/** \brief D04C, TOM TGC0 Action Time Base Register */
+#define GTM_ATOM0_AGC_ACT_TB /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_ACT_TB*)0xF010D04Cu)
+
+/** \brief D044, ATOM AGC Enable/Disable Control Register */
+#define GTM_ATOM0_AGC_ENDIS_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_ENDIS_CTRL*)0xF010D044u)
+
+/** \brief D048, ATOM AGC Enable/Disable Status Register */
+#define GTM_ATOM0_AGC_ENDIS_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_ENDIS_STAT*)0xF010D048u)
+
+/** \brief D058, ATOM AGC Force Update Control Register */
+#define GTM_ATOM0_AGC_FUPD_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_FUPD_CTRL*)0xF010D058u)
+
+/** \brief D040, ATOM AGC Global control register */
+#define GTM_ATOM0_AGC_GLB_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_GLB_CTRL*)0xF010D040u)
+
+/** \brief D05C, ATOM AGC Internal Trigger Control Register */
+#define GTM_ATOM0_AGC_INT_TRIG /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_INT_TRIG*)0xF010D05Cu)
+
+/** \brief D050, ATOM AGC Output Enable Control Register */
+#define GTM_ATOM0_AGC_OUTEN_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_OUTEN_CTRL*)0xF010D050u)
+
+/** \brief D054, ATOM AGC Output Enable Status Register */
+#define GTM_ATOM0_AGC_OUTEN_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_OUTEN_STAT*)0xF010D054u)
+
+/** \brief D010, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM0_CH0_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010D010u)
+
+/** \brief D014, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM0_CH0_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010D014u)
+
+/** \brief D018, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM0_CH0_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010D018u)
+
+/** \brief D004, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH0_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010D004u)
+
+/** \brief D024, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM0_CH0_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010D024u)
+
+/** \brief D028, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM0_CH0_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010D028u)
+
+/** \brief D02C, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM0_CH0_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010D02Cu)
+
+/** \brief D020, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM0_CH0_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010D020u)
+
+/** \brief D000, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM0_CH0_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010D000u)
+
+/** \brief D004, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH0_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010D004u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH0_SOMC.
+* To use register names with standard convension, please use GTM_ATOM0_CH0_SOMC.
+*/
+#define GTM_ATOM0_CH0_CTRL_SOMC (GTM_ATOM0_CH0_SOMC)
+
+/** \brief D004, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH0_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010D004u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH0_SOMI.
+* To use register names with standard convension, please use GTM_ATOM0_CH0_SOMI.
+*/
+#define GTM_ATOM0_CH0_CTRL_SOMI (GTM_ATOM0_CH0_SOMI)
+
+/** \brief D004, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH0_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010D004u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH0_SOMP.
+* To use register names with standard convension, please use GTM_ATOM0_CH0_SOMP.
+*/
+#define GTM_ATOM0_CH0_CTRL_SOMP (GTM_ATOM0_CH0_SOMP)
+
+/** \brief D004, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH0_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010D004u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH0_SOMS.
+* To use register names with standard convension, please use GTM_ATOM0_CH0_SOMS.
+*/
+#define GTM_ATOM0_CH0_CTRL_SOMS (GTM_ATOM0_CH0_SOMS)
+
+/** \brief D008, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM0_CH0_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010D008u)
+
+/** \brief D00C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM0_CH0_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010D00Cu)
+
+/** \brief D01C, ATOM Channel Status Register */
+#define GTM_ATOM0_CH0_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010D01Cu)
+
+/** \brief D090, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM0_CH1_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010D090u)
+
+/** \brief D094, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM0_CH1_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010D094u)
+
+/** \brief D098, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM0_CH1_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010D098u)
+
+/** \brief D084, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH1_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010D084u)
+
+/** \brief D0A4, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM0_CH1_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010D0A4u)
+
+/** \brief D0A8, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM0_CH1_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010D0A8u)
+
+/** \brief D0AC, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM0_CH1_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010D0ACu)
+
+/** \brief D0A0, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM0_CH1_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010D0A0u)
+
+/** \brief D080, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM0_CH1_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010D080u)
+
+/** \brief D084, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH1_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010D084u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH1_SOMC.
+* To use register names with standard convension, please use GTM_ATOM0_CH1_SOMC.
+*/
+#define GTM_ATOM0_CH1_CTRL_SOMC (GTM_ATOM0_CH1_SOMC)
+
+/** \brief D084, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH1_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010D084u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH1_SOMI.
+* To use register names with standard convension, please use GTM_ATOM0_CH1_SOMI.
+*/
+#define GTM_ATOM0_CH1_CTRL_SOMI (GTM_ATOM0_CH1_SOMI)
+
+/** \brief D084, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH1_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010D084u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH1_SOMP.
+* To use register names with standard convension, please use GTM_ATOM0_CH1_SOMP.
+*/
+#define GTM_ATOM0_CH1_CTRL_SOMP (GTM_ATOM0_CH1_SOMP)
+
+/** \brief D084, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH1_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010D084u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH1_SOMS.
+* To use register names with standard convension, please use GTM_ATOM0_CH1_SOMS.
+*/
+#define GTM_ATOM0_CH1_CTRL_SOMS (GTM_ATOM0_CH1_SOMS)
+
+/** \brief D088, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM0_CH1_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010D088u)
+
+/** \brief D08C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM0_CH1_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010D08Cu)
+
+/** \brief D09C, ATOM Channel Status Register */
+#define GTM_ATOM0_CH1_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010D09Cu)
+
+/** \brief D110, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM0_CH2_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010D110u)
+
+/** \brief D114, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM0_CH2_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010D114u)
+
+/** \brief D118, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM0_CH2_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010D118u)
+
+/** \brief D104, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH2_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010D104u)
+
+/** \brief D124, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM0_CH2_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010D124u)
+
+/** \brief D128, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM0_CH2_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010D128u)
+
+/** \brief D12C, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM0_CH2_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010D12Cu)
+
+/** \brief D120, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM0_CH2_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010D120u)
+
+/** \brief D100, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM0_CH2_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010D100u)
+
+/** \brief D104, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH2_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010D104u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH2_SOMC.
+* To use register names with standard convension, please use GTM_ATOM0_CH2_SOMC.
+*/
+#define GTM_ATOM0_CH2_CTRL_SOMC (GTM_ATOM0_CH2_SOMC)
+
+/** \brief D104, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH2_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010D104u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH2_SOMI.
+* To use register names with standard convension, please use GTM_ATOM0_CH2_SOMI.
+*/
+#define GTM_ATOM0_CH2_CTRL_SOMI (GTM_ATOM0_CH2_SOMI)
+
+/** \brief D104, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH2_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010D104u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH2_SOMP.
+* To use register names with standard convension, please use GTM_ATOM0_CH2_SOMP.
+*/
+#define GTM_ATOM0_CH2_CTRL_SOMP (GTM_ATOM0_CH2_SOMP)
+
+/** \brief D104, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH2_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010D104u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH2_SOMS.
+* To use register names with standard convension, please use GTM_ATOM0_CH2_SOMS.
+*/
+#define GTM_ATOM0_CH2_CTRL_SOMS (GTM_ATOM0_CH2_SOMS)
+
+/** \brief D108, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM0_CH2_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010D108u)
+
+/** \brief D10C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM0_CH2_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010D10Cu)
+
+/** \brief D11C, ATOM Channel Status Register */
+#define GTM_ATOM0_CH2_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010D11Cu)
+
+/** \brief D190, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM0_CH3_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010D190u)
+
+/** \brief D194, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM0_CH3_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010D194u)
+
+/** \brief D198, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM0_CH3_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010D198u)
+
+/** \brief D184, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH3_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010D184u)
+
+/** \brief D1A4, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM0_CH3_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010D1A4u)
+
+/** \brief D1A8, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM0_CH3_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010D1A8u)
+
+/** \brief D1AC, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM0_CH3_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010D1ACu)
+
+/** \brief D1A0, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM0_CH3_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010D1A0u)
+
+/** \brief D180, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM0_CH3_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010D180u)
+
+/** \brief D184, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH3_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010D184u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH3_SOMC.
+* To use register names with standard convension, please use GTM_ATOM0_CH3_SOMC.
+*/
+#define GTM_ATOM0_CH3_CTRL_SOMC (GTM_ATOM0_CH3_SOMC)
+
+/** \brief D184, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH3_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010D184u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH3_SOMI.
+* To use register names with standard convension, please use GTM_ATOM0_CH3_SOMI.
+*/
+#define GTM_ATOM0_CH3_CTRL_SOMI (GTM_ATOM0_CH3_SOMI)
+
+/** \brief D184, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH3_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010D184u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH3_SOMP.
+* To use register names with standard convension, please use GTM_ATOM0_CH3_SOMP.
+*/
+#define GTM_ATOM0_CH3_CTRL_SOMP (GTM_ATOM0_CH3_SOMP)
+
+/** \brief D184, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH3_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010D184u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH3_SOMS.
+* To use register names with standard convension, please use GTM_ATOM0_CH3_SOMS.
+*/
+#define GTM_ATOM0_CH3_CTRL_SOMS (GTM_ATOM0_CH3_SOMS)
+
+/** \brief D188, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM0_CH3_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010D188u)
+
+/** \brief D18C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM0_CH3_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010D18Cu)
+
+/** \brief D19C, ATOM Channel Status Register */
+#define GTM_ATOM0_CH3_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010D19Cu)
+
+/** \brief D210, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM0_CH4_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010D210u)
+
+/** \brief D214, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM0_CH4_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010D214u)
+
+/** \brief D218, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM0_CH4_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010D218u)
+
+/** \brief D204, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH4_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010D204u)
+
+/** \brief D224, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM0_CH4_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010D224u)
+
+/** \brief D228, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM0_CH4_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010D228u)
+
+/** \brief D22C, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM0_CH4_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010D22Cu)
+
+/** \brief D220, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM0_CH4_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010D220u)
+
+/** \brief D200, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM0_CH4_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010D200u)
+
+/** \brief D204, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH4_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010D204u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH4_SOMC.
+* To use register names with standard convension, please use GTM_ATOM0_CH4_SOMC.
+*/
+#define GTM_ATOM0_CH4_CTRL_SOMC (GTM_ATOM0_CH4_SOMC)
+
+/** \brief D204, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH4_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010D204u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH4_SOMI.
+* To use register names with standard convension, please use GTM_ATOM0_CH4_SOMI.
+*/
+#define GTM_ATOM0_CH4_CTRL_SOMI (GTM_ATOM0_CH4_SOMI)
+
+/** \brief D204, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH4_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010D204u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH4_SOMP.
+* To use register names with standard convension, please use GTM_ATOM0_CH4_SOMP.
+*/
+#define GTM_ATOM0_CH4_CTRL_SOMP (GTM_ATOM0_CH4_SOMP)
+
+/** \brief D204, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH4_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010D204u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH4_SOMS.
+* To use register names with standard convension, please use GTM_ATOM0_CH4_SOMS.
+*/
+#define GTM_ATOM0_CH4_CTRL_SOMS (GTM_ATOM0_CH4_SOMS)
+
+/** \brief D208, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM0_CH4_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010D208u)
+
+/** \brief D20C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM0_CH4_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010D20Cu)
+
+/** \brief D21C, ATOM Channel Status Register */
+#define GTM_ATOM0_CH4_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010D21Cu)
+
+/** \brief D290, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM0_CH5_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010D290u)
+
+/** \brief D294, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM0_CH5_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010D294u)
+
+/** \brief D298, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM0_CH5_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010D298u)
+
+/** \brief D284, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH5_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010D284u)
+
+/** \brief D2A4, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM0_CH5_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010D2A4u)
+
+/** \brief D2A8, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM0_CH5_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010D2A8u)
+
+/** \brief D2AC, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM0_CH5_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010D2ACu)
+
+/** \brief D2A0, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM0_CH5_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010D2A0u)
+
+/** \brief D280, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM0_CH5_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010D280u)
+
+/** \brief D284, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH5_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010D284u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH5_SOMC.
+* To use register names with standard convension, please use GTM_ATOM0_CH5_SOMC.
+*/
+#define GTM_ATOM0_CH5_CTRL_SOMC (GTM_ATOM0_CH5_SOMC)
+
+/** \brief D284, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH5_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010D284u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH5_SOMI.
+* To use register names with standard convension, please use GTM_ATOM0_CH5_SOMI.
+*/
+#define GTM_ATOM0_CH5_CTRL_SOMI (GTM_ATOM0_CH5_SOMI)
+
+/** \brief D284, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH5_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010D284u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH5_SOMP.
+* To use register names with standard convension, please use GTM_ATOM0_CH5_SOMP.
+*/
+#define GTM_ATOM0_CH5_CTRL_SOMP (GTM_ATOM0_CH5_SOMP)
+
+/** \brief D284, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH5_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010D284u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH5_SOMS.
+* To use register names with standard convension, please use GTM_ATOM0_CH5_SOMS.
+*/
+#define GTM_ATOM0_CH5_CTRL_SOMS (GTM_ATOM0_CH5_SOMS)
+
+/** \brief D288, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM0_CH5_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010D288u)
+
+/** \brief D28C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM0_CH5_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010D28Cu)
+
+/** \brief D29C, ATOM Channel Status Register */
+#define GTM_ATOM0_CH5_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010D29Cu)
+
+/** \brief D310, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM0_CH6_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010D310u)
+
+/** \brief D314, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM0_CH6_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010D314u)
+
+/** \brief D318, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM0_CH6_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010D318u)
+
+/** \brief D304, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH6_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010D304u)
+
+/** \brief D324, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM0_CH6_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010D324u)
+
+/** \brief D328, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM0_CH6_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010D328u)
+
+/** \brief D32C, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM0_CH6_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010D32Cu)
+
+/** \brief D320, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM0_CH6_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010D320u)
+
+/** \brief D300, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM0_CH6_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010D300u)
+
+/** \brief D304, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH6_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010D304u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH6_SOMC.
+* To use register names with standard convension, please use GTM_ATOM0_CH6_SOMC.
+*/
+#define GTM_ATOM0_CH6_CTRL_SOMC (GTM_ATOM0_CH6_SOMC)
+
+/** \brief D304, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH6_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010D304u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH6_SOMI.
+* To use register names with standard convension, please use GTM_ATOM0_CH6_SOMI.
+*/
+#define GTM_ATOM0_CH6_CTRL_SOMI (GTM_ATOM0_CH6_SOMI)
+
+/** \brief D304, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH6_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010D304u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH6_SOMP.
+* To use register names with standard convension, please use GTM_ATOM0_CH6_SOMP.
+*/
+#define GTM_ATOM0_CH6_CTRL_SOMP (GTM_ATOM0_CH6_SOMP)
+
+/** \brief D304, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH6_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010D304u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH6_SOMS.
+* To use register names with standard convension, please use GTM_ATOM0_CH6_SOMS.
+*/
+#define GTM_ATOM0_CH6_CTRL_SOMS (GTM_ATOM0_CH6_SOMS)
+
+/** \brief D308, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM0_CH6_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010D308u)
+
+/** \brief D30C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM0_CH6_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010D30Cu)
+
+/** \brief D31C, ATOM Channel Status Register */
+#define GTM_ATOM0_CH6_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010D31Cu)
+
+/** \brief D390, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM0_CH7_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010D390u)
+
+/** \brief D394, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM0_CH7_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010D394u)
+
+/** \brief D398, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM0_CH7_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010D398u)
+
+/** \brief D384, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH7_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010D384u)
+
+/** \brief D3A4, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM0_CH7_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010D3A4u)
+
+/** \brief D3A8, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM0_CH7_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010D3A8u)
+
+/** \brief D3AC, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM0_CH7_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010D3ACu)
+
+/** \brief D3A0, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM0_CH7_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010D3A0u)
+
+/** \brief D380, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM0_CH7_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010D380u)
+
+/** \brief D384, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH7_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010D384u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH7_SOMC.
+* To use register names with standard convension, please use GTM_ATOM0_CH7_SOMC.
+*/
+#define GTM_ATOM0_CH7_CTRL_SOMC (GTM_ATOM0_CH7_SOMC)
+
+/** \brief D384, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH7_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010D384u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH7_SOMI.
+* To use register names with standard convension, please use GTM_ATOM0_CH7_SOMI.
+*/
+#define GTM_ATOM0_CH7_CTRL_SOMI (GTM_ATOM0_CH7_SOMI)
+
+/** \brief D384, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH7_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010D384u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH7_SOMP.
+* To use register names with standard convension, please use GTM_ATOM0_CH7_SOMP.
+*/
+#define GTM_ATOM0_CH7_CTRL_SOMP (GTM_ATOM0_CH7_SOMP)
+
+/** \brief D384, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM0_CH7_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010D384u)
+
+/** Alias (User Manual Name) for GTM_ATOM0_CH7_SOMS.
+* To use register names with standard convension, please use GTM_ATOM0_CH7_SOMS.
+*/
+#define GTM_ATOM0_CH7_CTRL_SOMS (GTM_ATOM0_CH7_SOMS)
+
+/** \brief D388, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM0_CH7_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010D388u)
+
+/** \brief D38C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM0_CH7_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010D38Cu)
+
+/** \brief D39C, ATOM Channel Status Register */
+#define GTM_ATOM0_CH7_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010D39Cu)
+
+/** \brief D84C, TOM TGC0 Action Time Base Register */
+#define GTM_ATOM1_AGC_ACT_TB /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_ACT_TB*)0xF010D84Cu)
+
+/** \brief D844, ATOM AGC Enable/Disable Control Register */
+#define GTM_ATOM1_AGC_ENDIS_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_ENDIS_CTRL*)0xF010D844u)
+
+/** \brief D848, ATOM AGC Enable/Disable Status Register */
+#define GTM_ATOM1_AGC_ENDIS_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_ENDIS_STAT*)0xF010D848u)
+
+/** \brief D858, ATOM AGC Force Update Control Register */
+#define GTM_ATOM1_AGC_FUPD_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_FUPD_CTRL*)0xF010D858u)
+
+/** \brief D840, ATOM AGC Global control register */
+#define GTM_ATOM1_AGC_GLB_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_GLB_CTRL*)0xF010D840u)
+
+/** \brief D85C, ATOM AGC Internal Trigger Control Register */
+#define GTM_ATOM1_AGC_INT_TRIG /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_INT_TRIG*)0xF010D85Cu)
+
+/** \brief D850, ATOM AGC Output Enable Control Register */
+#define GTM_ATOM1_AGC_OUTEN_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_OUTEN_CTRL*)0xF010D850u)
+
+/** \brief D854, ATOM AGC Output Enable Status Register */
+#define GTM_ATOM1_AGC_OUTEN_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_OUTEN_STAT*)0xF010D854u)
+
+/** \brief D810, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM1_CH0_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010D810u)
+
+/** \brief D814, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM1_CH0_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010D814u)
+
+/** \brief D818, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM1_CH0_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010D818u)
+
+/** \brief D804, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH0_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010D804u)
+
+/** \brief D824, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM1_CH0_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010D824u)
+
+/** \brief D828, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM1_CH0_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010D828u)
+
+/** \brief D82C, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM1_CH0_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010D82Cu)
+
+/** \brief D820, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM1_CH0_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010D820u)
+
+/** \brief D800, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM1_CH0_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010D800u)
+
+/** \brief D804, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH0_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010D804u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH0_SOMC.
+* To use register names with standard convension, please use GTM_ATOM1_CH0_SOMC.
+*/
+#define GTM_ATOM1_CH0_CTRL_SOMC (GTM_ATOM1_CH0_SOMC)
+
+/** \brief D804, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH0_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010D804u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH0_SOMI.
+* To use register names with standard convension, please use GTM_ATOM1_CH0_SOMI.
+*/
+#define GTM_ATOM1_CH0_CTRL_SOMI (GTM_ATOM1_CH0_SOMI)
+
+/** \brief D804, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH0_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010D804u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH0_SOMP.
+* To use register names with standard convension, please use GTM_ATOM1_CH0_SOMP.
+*/
+#define GTM_ATOM1_CH0_CTRL_SOMP (GTM_ATOM1_CH0_SOMP)
+
+/** \brief D804, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH0_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010D804u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH0_SOMS.
+* To use register names with standard convension, please use GTM_ATOM1_CH0_SOMS.
+*/
+#define GTM_ATOM1_CH0_CTRL_SOMS (GTM_ATOM1_CH0_SOMS)
+
+/** \brief D808, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM1_CH0_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010D808u)
+
+/** \brief D80C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM1_CH0_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010D80Cu)
+
+/** \brief D81C, ATOM Channel Status Register */
+#define GTM_ATOM1_CH0_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010D81Cu)
+
+/** \brief D890, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM1_CH1_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010D890u)
+
+/** \brief D894, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM1_CH1_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010D894u)
+
+/** \brief D898, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM1_CH1_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010D898u)
+
+/** \brief D884, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH1_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010D884u)
+
+/** \brief D8A4, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM1_CH1_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010D8A4u)
+
+/** \brief D8A8, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM1_CH1_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010D8A8u)
+
+/** \brief D8AC, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM1_CH1_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010D8ACu)
+
+/** \brief D8A0, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM1_CH1_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010D8A0u)
+
+/** \brief D880, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM1_CH1_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010D880u)
+
+/** \brief D884, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH1_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010D884u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH1_SOMC.
+* To use register names with standard convension, please use GTM_ATOM1_CH1_SOMC.
+*/
+#define GTM_ATOM1_CH1_CTRL_SOMC (GTM_ATOM1_CH1_SOMC)
+
+/** \brief D884, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH1_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010D884u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH1_SOMI.
+* To use register names with standard convension, please use GTM_ATOM1_CH1_SOMI.
+*/
+#define GTM_ATOM1_CH1_CTRL_SOMI (GTM_ATOM1_CH1_SOMI)
+
+/** \brief D884, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH1_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010D884u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH1_SOMP.
+* To use register names with standard convension, please use GTM_ATOM1_CH1_SOMP.
+*/
+#define GTM_ATOM1_CH1_CTRL_SOMP (GTM_ATOM1_CH1_SOMP)
+
+/** \brief D884, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH1_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010D884u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH1_SOMS.
+* To use register names with standard convension, please use GTM_ATOM1_CH1_SOMS.
+*/
+#define GTM_ATOM1_CH1_CTRL_SOMS (GTM_ATOM1_CH1_SOMS)
+
+/** \brief D888, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM1_CH1_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010D888u)
+
+/** \brief D88C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM1_CH1_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010D88Cu)
+
+/** \brief D89C, ATOM Channel Status Register */
+#define GTM_ATOM1_CH1_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010D89Cu)
+
+/** \brief D910, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM1_CH2_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010D910u)
+
+/** \brief D914, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM1_CH2_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010D914u)
+
+/** \brief D918, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM1_CH2_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010D918u)
+
+/** \brief D904, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH2_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010D904u)
+
+/** \brief D924, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM1_CH2_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010D924u)
+
+/** \brief D928, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM1_CH2_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010D928u)
+
+/** \brief D92C, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM1_CH2_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010D92Cu)
+
+/** \brief D920, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM1_CH2_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010D920u)
+
+/** \brief D900, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM1_CH2_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010D900u)
+
+/** \brief D904, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH2_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010D904u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH2_SOMC.
+* To use register names with standard convension, please use GTM_ATOM1_CH2_SOMC.
+*/
+#define GTM_ATOM1_CH2_CTRL_SOMC (GTM_ATOM1_CH2_SOMC)
+
+/** \brief D904, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH2_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010D904u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH2_SOMI.
+* To use register names with standard convension, please use GTM_ATOM1_CH2_SOMI.
+*/
+#define GTM_ATOM1_CH2_CTRL_SOMI (GTM_ATOM1_CH2_SOMI)
+
+/** \brief D904, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH2_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010D904u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH2_SOMP.
+* To use register names with standard convension, please use GTM_ATOM1_CH2_SOMP.
+*/
+#define GTM_ATOM1_CH2_CTRL_SOMP (GTM_ATOM1_CH2_SOMP)
+
+/** \brief D904, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH2_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010D904u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH2_SOMS.
+* To use register names with standard convension, please use GTM_ATOM1_CH2_SOMS.
+*/
+#define GTM_ATOM1_CH2_CTRL_SOMS (GTM_ATOM1_CH2_SOMS)
+
+/** \brief D908, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM1_CH2_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010D908u)
+
+/** \brief D90C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM1_CH2_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010D90Cu)
+
+/** \brief D91C, ATOM Channel Status Register */
+#define GTM_ATOM1_CH2_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010D91Cu)
+
+/** \brief D990, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM1_CH3_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010D990u)
+
+/** \brief D994, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM1_CH3_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010D994u)
+
+/** \brief D998, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM1_CH3_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010D998u)
+
+/** \brief D984, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH3_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010D984u)
+
+/** \brief D9A4, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM1_CH3_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010D9A4u)
+
+/** \brief D9A8, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM1_CH3_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010D9A8u)
+
+/** \brief D9AC, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM1_CH3_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010D9ACu)
+
+/** \brief D9A0, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM1_CH3_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010D9A0u)
+
+/** \brief D980, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM1_CH3_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010D980u)
+
+/** \brief D984, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH3_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010D984u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH3_SOMC.
+* To use register names with standard convension, please use GTM_ATOM1_CH3_SOMC.
+*/
+#define GTM_ATOM1_CH3_CTRL_SOMC (GTM_ATOM1_CH3_SOMC)
+
+/** \brief D984, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH3_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010D984u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH3_SOMI.
+* To use register names with standard convension, please use GTM_ATOM1_CH3_SOMI.
+*/
+#define GTM_ATOM1_CH3_CTRL_SOMI (GTM_ATOM1_CH3_SOMI)
+
+/** \brief D984, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH3_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010D984u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH3_SOMP.
+* To use register names with standard convension, please use GTM_ATOM1_CH3_SOMP.
+*/
+#define GTM_ATOM1_CH3_CTRL_SOMP (GTM_ATOM1_CH3_SOMP)
+
+/** \brief D984, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH3_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010D984u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH3_SOMS.
+* To use register names with standard convension, please use GTM_ATOM1_CH3_SOMS.
+*/
+#define GTM_ATOM1_CH3_CTRL_SOMS (GTM_ATOM1_CH3_SOMS)
+
+/** \brief D988, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM1_CH3_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010D988u)
+
+/** \brief D98C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM1_CH3_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010D98Cu)
+
+/** \brief D99C, ATOM Channel Status Register */
+#define GTM_ATOM1_CH3_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010D99Cu)
+
+/** \brief DA10, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM1_CH4_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010DA10u)
+
+/** \brief DA14, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM1_CH4_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010DA14u)
+
+/** \brief DA18, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM1_CH4_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010DA18u)
+
+/** \brief DA04, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH4_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010DA04u)
+
+/** \brief DA24, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM1_CH4_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010DA24u)
+
+/** \brief DA28, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM1_CH4_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010DA28u)
+
+/** \brief DA2C, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM1_CH4_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010DA2Cu)
+
+/** \brief DA20, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM1_CH4_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010DA20u)
+
+/** \brief DA00, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM1_CH4_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010DA00u)
+
+/** \brief DA04, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH4_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010DA04u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH4_SOMC.
+* To use register names with standard convension, please use GTM_ATOM1_CH4_SOMC.
+*/
+#define GTM_ATOM1_CH4_CTRL_SOMC (GTM_ATOM1_CH4_SOMC)
+
+/** \brief DA04, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH4_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010DA04u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH4_SOMI.
+* To use register names with standard convension, please use GTM_ATOM1_CH4_SOMI.
+*/
+#define GTM_ATOM1_CH4_CTRL_SOMI (GTM_ATOM1_CH4_SOMI)
+
+/** \brief DA04, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH4_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010DA04u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH4_SOMP.
+* To use register names with standard convension, please use GTM_ATOM1_CH4_SOMP.
+*/
+#define GTM_ATOM1_CH4_CTRL_SOMP (GTM_ATOM1_CH4_SOMP)
+
+/** \brief DA04, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH4_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010DA04u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH4_SOMS.
+* To use register names with standard convension, please use GTM_ATOM1_CH4_SOMS.
+*/
+#define GTM_ATOM1_CH4_CTRL_SOMS (GTM_ATOM1_CH4_SOMS)
+
+/** \brief DA08, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM1_CH4_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010DA08u)
+
+/** \brief DA0C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM1_CH4_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010DA0Cu)
+
+/** \brief DA1C, ATOM Channel Status Register */
+#define GTM_ATOM1_CH4_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010DA1Cu)
+
+/** \brief DA90, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM1_CH5_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010DA90u)
+
+/** \brief DA94, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM1_CH5_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010DA94u)
+
+/** \brief DA98, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM1_CH5_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010DA98u)
+
+/** \brief DA84, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH5_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010DA84u)
+
+/** \brief DAA4, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM1_CH5_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010DAA4u)
+
+/** \brief DAA8, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM1_CH5_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010DAA8u)
+
+/** \brief DAAC, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM1_CH5_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010DAACu)
+
+/** \brief DAA0, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM1_CH5_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010DAA0u)
+
+/** \brief DA80, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM1_CH5_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010DA80u)
+
+/** \brief DA84, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH5_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010DA84u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH5_SOMC.
+* To use register names with standard convension, please use GTM_ATOM1_CH5_SOMC.
+*/
+#define GTM_ATOM1_CH5_CTRL_SOMC (GTM_ATOM1_CH5_SOMC)
+
+/** \brief DA84, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH5_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010DA84u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH5_SOMI.
+* To use register names with standard convension, please use GTM_ATOM1_CH5_SOMI.
+*/
+#define GTM_ATOM1_CH5_CTRL_SOMI (GTM_ATOM1_CH5_SOMI)
+
+/** \brief DA84, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH5_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010DA84u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH5_SOMP.
+* To use register names with standard convension, please use GTM_ATOM1_CH5_SOMP.
+*/
+#define GTM_ATOM1_CH5_CTRL_SOMP (GTM_ATOM1_CH5_SOMP)
+
+/** \brief DA84, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH5_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010DA84u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH5_SOMS.
+* To use register names with standard convension, please use GTM_ATOM1_CH5_SOMS.
+*/
+#define GTM_ATOM1_CH5_CTRL_SOMS (GTM_ATOM1_CH5_SOMS)
+
+/** \brief DA88, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM1_CH5_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010DA88u)
+
+/** \brief DA8C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM1_CH5_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010DA8Cu)
+
+/** \brief DA9C, ATOM Channel Status Register */
+#define GTM_ATOM1_CH5_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010DA9Cu)
+
+/** \brief DB10, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM1_CH6_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010DB10u)
+
+/** \brief DB14, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM1_CH6_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010DB14u)
+
+/** \brief DB18, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM1_CH6_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010DB18u)
+
+/** \brief DB04, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH6_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010DB04u)
+
+/** \brief DB24, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM1_CH6_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010DB24u)
+
+/** \brief DB28, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM1_CH6_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010DB28u)
+
+/** \brief DB2C, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM1_CH6_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010DB2Cu)
+
+/** \brief DB20, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM1_CH6_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010DB20u)
+
+/** \brief DB00, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM1_CH6_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010DB00u)
+
+/** \brief DB04, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH6_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010DB04u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH6_SOMC.
+* To use register names with standard convension, please use GTM_ATOM1_CH6_SOMC.
+*/
+#define GTM_ATOM1_CH6_CTRL_SOMC (GTM_ATOM1_CH6_SOMC)
+
+/** \brief DB04, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH6_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010DB04u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH6_SOMI.
+* To use register names with standard convension, please use GTM_ATOM1_CH6_SOMI.
+*/
+#define GTM_ATOM1_CH6_CTRL_SOMI (GTM_ATOM1_CH6_SOMI)
+
+/** \brief DB04, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH6_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010DB04u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH6_SOMP.
+* To use register names with standard convension, please use GTM_ATOM1_CH6_SOMP.
+*/
+#define GTM_ATOM1_CH6_CTRL_SOMP (GTM_ATOM1_CH6_SOMP)
+
+/** \brief DB04, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH6_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010DB04u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH6_SOMS.
+* To use register names with standard convension, please use GTM_ATOM1_CH6_SOMS.
+*/
+#define GTM_ATOM1_CH6_CTRL_SOMS (GTM_ATOM1_CH6_SOMS)
+
+/** \brief DB08, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM1_CH6_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010DB08u)
+
+/** \brief DB0C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM1_CH6_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010DB0Cu)
+
+/** \brief DB1C, ATOM Channel Status Register */
+#define GTM_ATOM1_CH6_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010DB1Cu)
+
+/** \brief DB90, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM1_CH7_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010DB90u)
+
+/** \brief DB94, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM1_CH7_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010DB94u)
+
+/** \brief DB98, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM1_CH7_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010DB98u)
+
+/** \brief DB84, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH7_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010DB84u)
+
+/** \brief DBA4, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM1_CH7_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010DBA4u)
+
+/** \brief DBA8, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM1_CH7_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010DBA8u)
+
+/** \brief DBAC, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM1_CH7_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010DBACu)
+
+/** \brief DBA0, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM1_CH7_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010DBA0u)
+
+/** \brief DB80, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM1_CH7_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010DB80u)
+
+/** \brief DB84, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH7_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010DB84u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH7_SOMC.
+* To use register names with standard convension, please use GTM_ATOM1_CH7_SOMC.
+*/
+#define GTM_ATOM1_CH7_CTRL_SOMC (GTM_ATOM1_CH7_SOMC)
+
+/** \brief DB84, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH7_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010DB84u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH7_SOMI.
+* To use register names with standard convension, please use GTM_ATOM1_CH7_SOMI.
+*/
+#define GTM_ATOM1_CH7_CTRL_SOMI (GTM_ATOM1_CH7_SOMI)
+
+/** \brief DB84, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH7_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010DB84u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH7_SOMP.
+* To use register names with standard convension, please use GTM_ATOM1_CH7_SOMP.
+*/
+#define GTM_ATOM1_CH7_CTRL_SOMP (GTM_ATOM1_CH7_SOMP)
+
+/** \brief DB84, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM1_CH7_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010DB84u)
+
+/** Alias (User Manual Name) for GTM_ATOM1_CH7_SOMS.
+* To use register names with standard convension, please use GTM_ATOM1_CH7_SOMS.
+*/
+#define GTM_ATOM1_CH7_CTRL_SOMS (GTM_ATOM1_CH7_SOMS)
+
+/** \brief DB88, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM1_CH7_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010DB88u)
+
+/** \brief DB8C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM1_CH7_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010DB8Cu)
+
+/** \brief DB9C, ATOM Channel Status Register */
+#define GTM_ATOM1_CH7_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010DB9Cu)
+
+/** \brief E04C, TOM TGC0 Action Time Base Register */
+#define GTM_ATOM2_AGC_ACT_TB /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_ACT_TB*)0xF010E04Cu)
+
+/** \brief E044, ATOM AGC Enable/Disable Control Register */
+#define GTM_ATOM2_AGC_ENDIS_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_ENDIS_CTRL*)0xF010E044u)
+
+/** \brief E048, ATOM AGC Enable/Disable Status Register */
+#define GTM_ATOM2_AGC_ENDIS_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_ENDIS_STAT*)0xF010E048u)
+
+/** \brief E058, ATOM AGC Force Update Control Register */
+#define GTM_ATOM2_AGC_FUPD_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_FUPD_CTRL*)0xF010E058u)
+
+/** \brief E040, ATOM AGC Global control register */
+#define GTM_ATOM2_AGC_GLB_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_GLB_CTRL*)0xF010E040u)
+
+/** \brief E05C, ATOM AGC Internal Trigger Control Register */
+#define GTM_ATOM2_AGC_INT_TRIG /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_INT_TRIG*)0xF010E05Cu)
+
+/** \brief E050, ATOM AGC Output Enable Control Register */
+#define GTM_ATOM2_AGC_OUTEN_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_OUTEN_CTRL*)0xF010E050u)
+
+/** \brief E054, ATOM AGC Output Enable Status Register */
+#define GTM_ATOM2_AGC_OUTEN_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_OUTEN_STAT*)0xF010E054u)
+
+/** \brief E010, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM2_CH0_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010E010u)
+
+/** \brief E014, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM2_CH0_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010E014u)
+
+/** \brief E018, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM2_CH0_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010E018u)
+
+/** \brief E004, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH0_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010E004u)
+
+/** \brief E024, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM2_CH0_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010E024u)
+
+/** \brief E028, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM2_CH0_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010E028u)
+
+/** \brief E02C, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM2_CH0_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010E02Cu)
+
+/** \brief E020, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM2_CH0_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010E020u)
+
+/** \brief E000, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM2_CH0_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010E000u)
+
+/** \brief E004, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH0_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010E004u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH0_SOMC.
+* To use register names with standard convension, please use GTM_ATOM2_CH0_SOMC.
+*/
+#define GTM_ATOM2_CH0_CTRL_SOMC (GTM_ATOM2_CH0_SOMC)
+
+/** \brief E004, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH0_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010E004u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH0_SOMI.
+* To use register names with standard convension, please use GTM_ATOM2_CH0_SOMI.
+*/
+#define GTM_ATOM2_CH0_CTRL_SOMI (GTM_ATOM2_CH0_SOMI)
+
+/** \brief E004, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH0_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010E004u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH0_SOMP.
+* To use register names with standard convension, please use GTM_ATOM2_CH0_SOMP.
+*/
+#define GTM_ATOM2_CH0_CTRL_SOMP (GTM_ATOM2_CH0_SOMP)
+
+/** \brief E004, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH0_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010E004u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH0_SOMS.
+* To use register names with standard convension, please use GTM_ATOM2_CH0_SOMS.
+*/
+#define GTM_ATOM2_CH0_CTRL_SOMS (GTM_ATOM2_CH0_SOMS)
+
+/** \brief E008, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM2_CH0_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010E008u)
+
+/** \brief E00C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM2_CH0_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010E00Cu)
+
+/** \brief E01C, ATOM Channel Status Register */
+#define GTM_ATOM2_CH0_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010E01Cu)
+
+/** \brief E090, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM2_CH1_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010E090u)
+
+/** \brief E094, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM2_CH1_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010E094u)
+
+/** \brief E098, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM2_CH1_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010E098u)
+
+/** \brief E084, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH1_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010E084u)
+
+/** \brief E0A4, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM2_CH1_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010E0A4u)
+
+/** \brief E0A8, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM2_CH1_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010E0A8u)
+
+/** \brief E0AC, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM2_CH1_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010E0ACu)
+
+/** \brief E0A0, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM2_CH1_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010E0A0u)
+
+/** \brief E080, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM2_CH1_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010E080u)
+
+/** \brief E084, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH1_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010E084u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH1_SOMC.
+* To use register names with standard convension, please use GTM_ATOM2_CH1_SOMC.
+*/
+#define GTM_ATOM2_CH1_CTRL_SOMC (GTM_ATOM2_CH1_SOMC)
+
+/** \brief E084, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH1_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010E084u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH1_SOMI.
+* To use register names with standard convension, please use GTM_ATOM2_CH1_SOMI.
+*/
+#define GTM_ATOM2_CH1_CTRL_SOMI (GTM_ATOM2_CH1_SOMI)
+
+/** \brief E084, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH1_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010E084u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH1_SOMP.
+* To use register names with standard convension, please use GTM_ATOM2_CH1_SOMP.
+*/
+#define GTM_ATOM2_CH1_CTRL_SOMP (GTM_ATOM2_CH1_SOMP)
+
+/** \brief E084, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH1_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010E084u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH1_SOMS.
+* To use register names with standard convension, please use GTM_ATOM2_CH1_SOMS.
+*/
+#define GTM_ATOM2_CH1_CTRL_SOMS (GTM_ATOM2_CH1_SOMS)
+
+/** \brief E088, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM2_CH1_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010E088u)
+
+/** \brief E08C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM2_CH1_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010E08Cu)
+
+/** \brief E09C, ATOM Channel Status Register */
+#define GTM_ATOM2_CH1_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010E09Cu)
+
+/** \brief E110, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM2_CH2_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010E110u)
+
+/** \brief E114, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM2_CH2_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010E114u)
+
+/** \brief E118, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM2_CH2_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010E118u)
+
+/** \brief E104, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH2_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010E104u)
+
+/** \brief E124, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM2_CH2_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010E124u)
+
+/** \brief E128, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM2_CH2_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010E128u)
+
+/** \brief E12C, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM2_CH2_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010E12Cu)
+
+/** \brief E120, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM2_CH2_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010E120u)
+
+/** \brief E100, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM2_CH2_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010E100u)
+
+/** \brief E104, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH2_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010E104u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH2_SOMC.
+* To use register names with standard convension, please use GTM_ATOM2_CH2_SOMC.
+*/
+#define GTM_ATOM2_CH2_CTRL_SOMC (GTM_ATOM2_CH2_SOMC)
+
+/** \brief E104, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH2_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010E104u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH2_SOMI.
+* To use register names with standard convension, please use GTM_ATOM2_CH2_SOMI.
+*/
+#define GTM_ATOM2_CH2_CTRL_SOMI (GTM_ATOM2_CH2_SOMI)
+
+/** \brief E104, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH2_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010E104u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH2_SOMP.
+* To use register names with standard convension, please use GTM_ATOM2_CH2_SOMP.
+*/
+#define GTM_ATOM2_CH2_CTRL_SOMP (GTM_ATOM2_CH2_SOMP)
+
+/** \brief E104, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH2_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010E104u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH2_SOMS.
+* To use register names with standard convension, please use GTM_ATOM2_CH2_SOMS.
+*/
+#define GTM_ATOM2_CH2_CTRL_SOMS (GTM_ATOM2_CH2_SOMS)
+
+/** \brief E108, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM2_CH2_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010E108u)
+
+/** \brief E10C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM2_CH2_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010E10Cu)
+
+/** \brief E11C, ATOM Channel Status Register */
+#define GTM_ATOM2_CH2_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010E11Cu)
+
+/** \brief E190, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM2_CH3_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010E190u)
+
+/** \brief E194, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM2_CH3_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010E194u)
+
+/** \brief E198, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM2_CH3_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010E198u)
+
+/** \brief E184, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH3_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010E184u)
+
+/** \brief E1A4, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM2_CH3_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010E1A4u)
+
+/** \brief E1A8, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM2_CH3_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010E1A8u)
+
+/** \brief E1AC, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM2_CH3_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010E1ACu)
+
+/** \brief E1A0, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM2_CH3_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010E1A0u)
+
+/** \brief E180, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM2_CH3_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010E180u)
+
+/** \brief E184, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH3_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010E184u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH3_SOMC.
+* To use register names with standard convension, please use GTM_ATOM2_CH3_SOMC.
+*/
+#define GTM_ATOM2_CH3_CTRL_SOMC (GTM_ATOM2_CH3_SOMC)
+
+/** \brief E184, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH3_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010E184u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH3_SOMI.
+* To use register names with standard convension, please use GTM_ATOM2_CH3_SOMI.
+*/
+#define GTM_ATOM2_CH3_CTRL_SOMI (GTM_ATOM2_CH3_SOMI)
+
+/** \brief E184, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH3_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010E184u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH3_SOMP.
+* To use register names with standard convension, please use GTM_ATOM2_CH3_SOMP.
+*/
+#define GTM_ATOM2_CH3_CTRL_SOMP (GTM_ATOM2_CH3_SOMP)
+
+/** \brief E184, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH3_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010E184u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH3_SOMS.
+* To use register names with standard convension, please use GTM_ATOM2_CH3_SOMS.
+*/
+#define GTM_ATOM2_CH3_CTRL_SOMS (GTM_ATOM2_CH3_SOMS)
+
+/** \brief E188, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM2_CH3_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010E188u)
+
+/** \brief E18C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM2_CH3_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010E18Cu)
+
+/** \brief E19C, ATOM Channel Status Register */
+#define GTM_ATOM2_CH3_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010E19Cu)
+
+/** \brief E210, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM2_CH4_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010E210u)
+
+/** \brief E214, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM2_CH4_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010E214u)
+
+/** \brief E218, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM2_CH4_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010E218u)
+
+/** \brief E204, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH4_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010E204u)
+
+/** \brief E224, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM2_CH4_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010E224u)
+
+/** \brief E228, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM2_CH4_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010E228u)
+
+/** \brief E22C, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM2_CH4_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010E22Cu)
+
+/** \brief E220, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM2_CH4_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010E220u)
+
+/** \brief E200, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM2_CH4_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010E200u)
+
+/** \brief E204, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH4_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010E204u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH4_SOMC.
+* To use register names with standard convension, please use GTM_ATOM2_CH4_SOMC.
+*/
+#define GTM_ATOM2_CH4_CTRL_SOMC (GTM_ATOM2_CH4_SOMC)
+
+/** \brief E204, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH4_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010E204u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH4_SOMI.
+* To use register names with standard convension, please use GTM_ATOM2_CH4_SOMI.
+*/
+#define GTM_ATOM2_CH4_CTRL_SOMI (GTM_ATOM2_CH4_SOMI)
+
+/** \brief E204, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH4_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010E204u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH4_SOMP.
+* To use register names with standard convension, please use GTM_ATOM2_CH4_SOMP.
+*/
+#define GTM_ATOM2_CH4_CTRL_SOMP (GTM_ATOM2_CH4_SOMP)
+
+/** \brief E204, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH4_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010E204u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH4_SOMS.
+* To use register names with standard convension, please use GTM_ATOM2_CH4_SOMS.
+*/
+#define GTM_ATOM2_CH4_CTRL_SOMS (GTM_ATOM2_CH4_SOMS)
+
+/** \brief E208, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM2_CH4_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010E208u)
+
+/** \brief E20C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM2_CH4_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010E20Cu)
+
+/** \brief E21C, ATOM Channel Status Register */
+#define GTM_ATOM2_CH4_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010E21Cu)
+
+/** \brief E290, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM2_CH5_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010E290u)
+
+/** \brief E294, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM2_CH5_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010E294u)
+
+/** \brief E298, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM2_CH5_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010E298u)
+
+/** \brief E284, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH5_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010E284u)
+
+/** \brief E2A4, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM2_CH5_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010E2A4u)
+
+/** \brief E2A8, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM2_CH5_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010E2A8u)
+
+/** \brief E2AC, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM2_CH5_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010E2ACu)
+
+/** \brief E2A0, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM2_CH5_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010E2A0u)
+
+/** \brief E280, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM2_CH5_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010E280u)
+
+/** \brief E284, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH5_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010E284u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH5_SOMC.
+* To use register names with standard convension, please use GTM_ATOM2_CH5_SOMC.
+*/
+#define GTM_ATOM2_CH5_CTRL_SOMC (GTM_ATOM2_CH5_SOMC)
+
+/** \brief E284, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH5_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010E284u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH5_SOMI.
+* To use register names with standard convension, please use GTM_ATOM2_CH5_SOMI.
+*/
+#define GTM_ATOM2_CH5_CTRL_SOMI (GTM_ATOM2_CH5_SOMI)
+
+/** \brief E284, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH5_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010E284u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH5_SOMP.
+* To use register names with standard convension, please use GTM_ATOM2_CH5_SOMP.
+*/
+#define GTM_ATOM2_CH5_CTRL_SOMP (GTM_ATOM2_CH5_SOMP)
+
+/** \brief E284, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH5_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010E284u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH5_SOMS.
+* To use register names with standard convension, please use GTM_ATOM2_CH5_SOMS.
+*/
+#define GTM_ATOM2_CH5_CTRL_SOMS (GTM_ATOM2_CH5_SOMS)
+
+/** \brief E288, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM2_CH5_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010E288u)
+
+/** \brief E28C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM2_CH5_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010E28Cu)
+
+/** \brief E29C, ATOM Channel Status Register */
+#define GTM_ATOM2_CH5_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010E29Cu)
+
+/** \brief E310, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM2_CH6_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010E310u)
+
+/** \brief E314, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM2_CH6_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010E314u)
+
+/** \brief E318, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM2_CH6_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010E318u)
+
+/** \brief E304, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH6_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010E304u)
+
+/** \brief E324, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM2_CH6_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010E324u)
+
+/** \brief E328, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM2_CH6_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010E328u)
+
+/** \brief E32C, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM2_CH6_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010E32Cu)
+
+/** \brief E320, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM2_CH6_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010E320u)
+
+/** \brief E300, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM2_CH6_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010E300u)
+
+/** \brief E304, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH6_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010E304u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH6_SOMC.
+* To use register names with standard convension, please use GTM_ATOM2_CH6_SOMC.
+*/
+#define GTM_ATOM2_CH6_CTRL_SOMC (GTM_ATOM2_CH6_SOMC)
+
+/** \brief E304, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH6_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010E304u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH6_SOMI.
+* To use register names with standard convension, please use GTM_ATOM2_CH6_SOMI.
+*/
+#define GTM_ATOM2_CH6_CTRL_SOMI (GTM_ATOM2_CH6_SOMI)
+
+/** \brief E304, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH6_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010E304u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH6_SOMP.
+* To use register names with standard convension, please use GTM_ATOM2_CH6_SOMP.
+*/
+#define GTM_ATOM2_CH6_CTRL_SOMP (GTM_ATOM2_CH6_SOMP)
+
+/** \brief E304, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH6_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010E304u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH6_SOMS.
+* To use register names with standard convension, please use GTM_ATOM2_CH6_SOMS.
+*/
+#define GTM_ATOM2_CH6_CTRL_SOMS (GTM_ATOM2_CH6_SOMS)
+
+/** \brief E308, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM2_CH6_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010E308u)
+
+/** \brief E30C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM2_CH6_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010E30Cu)
+
+/** \brief E31C, ATOM Channel Status Register */
+#define GTM_ATOM2_CH6_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010E31Cu)
+
+/** \brief E390, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM2_CH7_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010E390u)
+
+/** \brief E394, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM2_CH7_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010E394u)
+
+/** \brief E398, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM2_CH7_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010E398u)
+
+/** \brief E384, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH7_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010E384u)
+
+/** \brief E3A4, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM2_CH7_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010E3A4u)
+
+/** \brief E3A8, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM2_CH7_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010E3A8u)
+
+/** \brief E3AC, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM2_CH7_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010E3ACu)
+
+/** \brief E3A0, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM2_CH7_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010E3A0u)
+
+/** \brief E380, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM2_CH7_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010E380u)
+
+/** \brief E384, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH7_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010E384u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH7_SOMC.
+* To use register names with standard convension, please use GTM_ATOM2_CH7_SOMC.
+*/
+#define GTM_ATOM2_CH7_CTRL_SOMC (GTM_ATOM2_CH7_SOMC)
+
+/** \brief E384, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH7_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010E384u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH7_SOMI.
+* To use register names with standard convension, please use GTM_ATOM2_CH7_SOMI.
+*/
+#define GTM_ATOM2_CH7_CTRL_SOMI (GTM_ATOM2_CH7_SOMI)
+
+/** \brief E384, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH7_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010E384u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH7_SOMP.
+* To use register names with standard convension, please use GTM_ATOM2_CH7_SOMP.
+*/
+#define GTM_ATOM2_CH7_CTRL_SOMP (GTM_ATOM2_CH7_SOMP)
+
+/** \brief E384, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM2_CH7_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010E384u)
+
+/** Alias (User Manual Name) for GTM_ATOM2_CH7_SOMS.
+* To use register names with standard convension, please use GTM_ATOM2_CH7_SOMS.
+*/
+#define GTM_ATOM2_CH7_CTRL_SOMS (GTM_ATOM2_CH7_SOMS)
+
+/** \brief E388, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM2_CH7_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010E388u)
+
+/** \brief E38C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM2_CH7_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010E38Cu)
+
+/** \brief E39C, ATOM Channel Status Register */
+#define GTM_ATOM2_CH7_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010E39Cu)
+
+/** \brief E84C, TOM TGC0 Action Time Base Register */
+#define GTM_ATOM3_AGC_ACT_TB /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_ACT_TB*)0xF010E84Cu)
+
+/** \brief E844, ATOM AGC Enable/Disable Control Register */
+#define GTM_ATOM3_AGC_ENDIS_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_ENDIS_CTRL*)0xF010E844u)
+
+/** \brief E848, ATOM AGC Enable/Disable Status Register */
+#define GTM_ATOM3_AGC_ENDIS_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_ENDIS_STAT*)0xF010E848u)
+
+/** \brief E858, ATOM AGC Force Update Control Register */
+#define GTM_ATOM3_AGC_FUPD_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_FUPD_CTRL*)0xF010E858u)
+
+/** \brief E840, ATOM AGC Global control register */
+#define GTM_ATOM3_AGC_GLB_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_GLB_CTRL*)0xF010E840u)
+
+/** \brief E85C, ATOM AGC Internal Trigger Control Register */
+#define GTM_ATOM3_AGC_INT_TRIG /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_INT_TRIG*)0xF010E85Cu)
+
+/** \brief E850, ATOM AGC Output Enable Control Register */
+#define GTM_ATOM3_AGC_OUTEN_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_OUTEN_CTRL*)0xF010E850u)
+
+/** \brief E854, ATOM AGC Output Enable Status Register */
+#define GTM_ATOM3_AGC_OUTEN_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_AGC_OUTEN_STAT*)0xF010E854u)
+
+/** \brief E810, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM3_CH0_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010E810u)
+
+/** \brief E814, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM3_CH0_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010E814u)
+
+/** \brief E818, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM3_CH0_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010E818u)
+
+/** \brief E804, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH0_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010E804u)
+
+/** \brief E824, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM3_CH0_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010E824u)
+
+/** \brief E828, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM3_CH0_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010E828u)
+
+/** \brief E82C, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM3_CH0_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010E82Cu)
+
+/** \brief E820, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM3_CH0_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010E820u)
+
+/** \brief E800, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM3_CH0_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010E800u)
+
+/** \brief E804, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH0_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010E804u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH0_SOMC.
+* To use register names with standard convension, please use GTM_ATOM3_CH0_SOMC.
+*/
+#define GTM_ATOM3_CH0_CTRL_SOMC (GTM_ATOM3_CH0_SOMC)
+
+/** \brief E804, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH0_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010E804u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH0_SOMI.
+* To use register names with standard convension, please use GTM_ATOM3_CH0_SOMI.
+*/
+#define GTM_ATOM3_CH0_CTRL_SOMI (GTM_ATOM3_CH0_SOMI)
+
+/** \brief E804, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH0_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010E804u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH0_SOMP.
+* To use register names with standard convension, please use GTM_ATOM3_CH0_SOMP.
+*/
+#define GTM_ATOM3_CH0_CTRL_SOMP (GTM_ATOM3_CH0_SOMP)
+
+/** \brief E804, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH0_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010E804u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH0_SOMS.
+* To use register names with standard convension, please use GTM_ATOM3_CH0_SOMS.
+*/
+#define GTM_ATOM3_CH0_CTRL_SOMS (GTM_ATOM3_CH0_SOMS)
+
+/** \brief E808, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM3_CH0_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010E808u)
+
+/** \brief E80C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM3_CH0_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010E80Cu)
+
+/** \brief E81C, ATOM Channel Status Register */
+#define GTM_ATOM3_CH0_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010E81Cu)
+
+/** \brief E890, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM3_CH1_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010E890u)
+
+/** \brief E894, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM3_CH1_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010E894u)
+
+/** \brief E898, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM3_CH1_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010E898u)
+
+/** \brief E884, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH1_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010E884u)
+
+/** \brief E8A4, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM3_CH1_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010E8A4u)
+
+/** \brief E8A8, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM3_CH1_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010E8A8u)
+
+/** \brief E8AC, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM3_CH1_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010E8ACu)
+
+/** \brief E8A0, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM3_CH1_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010E8A0u)
+
+/** \brief E880, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM3_CH1_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010E880u)
+
+/** \brief E884, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH1_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010E884u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH1_SOMC.
+* To use register names with standard convension, please use GTM_ATOM3_CH1_SOMC.
+*/
+#define GTM_ATOM3_CH1_CTRL_SOMC (GTM_ATOM3_CH1_SOMC)
+
+/** \brief E884, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH1_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010E884u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH1_SOMI.
+* To use register names with standard convension, please use GTM_ATOM3_CH1_SOMI.
+*/
+#define GTM_ATOM3_CH1_CTRL_SOMI (GTM_ATOM3_CH1_SOMI)
+
+/** \brief E884, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH1_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010E884u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH1_SOMP.
+* To use register names with standard convension, please use GTM_ATOM3_CH1_SOMP.
+*/
+#define GTM_ATOM3_CH1_CTRL_SOMP (GTM_ATOM3_CH1_SOMP)
+
+/** \brief E884, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH1_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010E884u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH1_SOMS.
+* To use register names with standard convension, please use GTM_ATOM3_CH1_SOMS.
+*/
+#define GTM_ATOM3_CH1_CTRL_SOMS (GTM_ATOM3_CH1_SOMS)
+
+/** \brief E888, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM3_CH1_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010E888u)
+
+/** \brief E88C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM3_CH1_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010E88Cu)
+
+/** \brief E89C, ATOM Channel Status Register */
+#define GTM_ATOM3_CH1_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010E89Cu)
+
+/** \brief E910, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM3_CH2_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010E910u)
+
+/** \brief E914, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM3_CH2_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010E914u)
+
+/** \brief E918, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM3_CH2_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010E918u)
+
+/** \brief E904, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH2_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010E904u)
+
+/** \brief E924, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM3_CH2_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010E924u)
+
+/** \brief E928, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM3_CH2_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010E928u)
+
+/** \brief E92C, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM3_CH2_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010E92Cu)
+
+/** \brief E920, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM3_CH2_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010E920u)
+
+/** \brief E900, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM3_CH2_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010E900u)
+
+/** \brief E904, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH2_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010E904u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH2_SOMC.
+* To use register names with standard convension, please use GTM_ATOM3_CH2_SOMC.
+*/
+#define GTM_ATOM3_CH2_CTRL_SOMC (GTM_ATOM3_CH2_SOMC)
+
+/** \brief E904, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH2_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010E904u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH2_SOMI.
+* To use register names with standard convension, please use GTM_ATOM3_CH2_SOMI.
+*/
+#define GTM_ATOM3_CH2_CTRL_SOMI (GTM_ATOM3_CH2_SOMI)
+
+/** \brief E904, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH2_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010E904u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH2_SOMP.
+* To use register names with standard convension, please use GTM_ATOM3_CH2_SOMP.
+*/
+#define GTM_ATOM3_CH2_CTRL_SOMP (GTM_ATOM3_CH2_SOMP)
+
+/** \brief E904, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH2_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010E904u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH2_SOMS.
+* To use register names with standard convension, please use GTM_ATOM3_CH2_SOMS.
+*/
+#define GTM_ATOM3_CH2_CTRL_SOMS (GTM_ATOM3_CH2_SOMS)
+
+/** \brief E908, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM3_CH2_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010E908u)
+
+/** \brief E90C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM3_CH2_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010E90Cu)
+
+/** \brief E91C, ATOM Channel Status Register */
+#define GTM_ATOM3_CH2_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010E91Cu)
+
+/** \brief E990, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM3_CH3_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010E990u)
+
+/** \brief E994, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM3_CH3_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010E994u)
+
+/** \brief E998, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM3_CH3_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010E998u)
+
+/** \brief E984, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH3_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010E984u)
+
+/** \brief E9A4, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM3_CH3_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010E9A4u)
+
+/** \brief E9A8, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM3_CH3_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010E9A8u)
+
+/** \brief E9AC, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM3_CH3_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010E9ACu)
+
+/** \brief E9A0, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM3_CH3_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010E9A0u)
+
+/** \brief E980, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM3_CH3_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010E980u)
+
+/** \brief E984, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH3_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010E984u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH3_SOMC.
+* To use register names with standard convension, please use GTM_ATOM3_CH3_SOMC.
+*/
+#define GTM_ATOM3_CH3_CTRL_SOMC (GTM_ATOM3_CH3_SOMC)
+
+/** \brief E984, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH3_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010E984u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH3_SOMI.
+* To use register names with standard convension, please use GTM_ATOM3_CH3_SOMI.
+*/
+#define GTM_ATOM3_CH3_CTRL_SOMI (GTM_ATOM3_CH3_SOMI)
+
+/** \brief E984, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH3_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010E984u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH3_SOMP.
+* To use register names with standard convension, please use GTM_ATOM3_CH3_SOMP.
+*/
+#define GTM_ATOM3_CH3_CTRL_SOMP (GTM_ATOM3_CH3_SOMP)
+
+/** \brief E984, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH3_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010E984u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH3_SOMS.
+* To use register names with standard convension, please use GTM_ATOM3_CH3_SOMS.
+*/
+#define GTM_ATOM3_CH3_CTRL_SOMS (GTM_ATOM3_CH3_SOMS)
+
+/** \brief E988, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM3_CH3_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010E988u)
+
+/** \brief E98C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM3_CH3_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010E98Cu)
+
+/** \brief E99C, ATOM Channel Status Register */
+#define GTM_ATOM3_CH3_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010E99Cu)
+
+/** \brief EA10, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM3_CH4_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010EA10u)
+
+/** \brief EA14, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM3_CH4_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010EA14u)
+
+/** \brief EA18, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM3_CH4_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010EA18u)
+
+/** \brief EA04, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH4_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010EA04u)
+
+/** \brief EA24, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM3_CH4_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010EA24u)
+
+/** \brief EA28, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM3_CH4_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010EA28u)
+
+/** \brief EA2C, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM3_CH4_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010EA2Cu)
+
+/** \brief EA20, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM3_CH4_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010EA20u)
+
+/** \brief EA00, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM3_CH4_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010EA00u)
+
+/** \brief EA04, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH4_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010EA04u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH4_SOMC.
+* To use register names with standard convension, please use GTM_ATOM3_CH4_SOMC.
+*/
+#define GTM_ATOM3_CH4_CTRL_SOMC (GTM_ATOM3_CH4_SOMC)
+
+/** \brief EA04, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH4_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010EA04u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH4_SOMI.
+* To use register names with standard convension, please use GTM_ATOM3_CH4_SOMI.
+*/
+#define GTM_ATOM3_CH4_CTRL_SOMI (GTM_ATOM3_CH4_SOMI)
+
+/** \brief EA04, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH4_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010EA04u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH4_SOMP.
+* To use register names with standard convension, please use GTM_ATOM3_CH4_SOMP.
+*/
+#define GTM_ATOM3_CH4_CTRL_SOMP (GTM_ATOM3_CH4_SOMP)
+
+/** \brief EA04, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH4_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010EA04u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH4_SOMS.
+* To use register names with standard convension, please use GTM_ATOM3_CH4_SOMS.
+*/
+#define GTM_ATOM3_CH4_CTRL_SOMS (GTM_ATOM3_CH4_SOMS)
+
+/** \brief EA08, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM3_CH4_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010EA08u)
+
+/** \brief EA0C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM3_CH4_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010EA0Cu)
+
+/** \brief EA1C, ATOM Channel Status Register */
+#define GTM_ATOM3_CH4_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010EA1Cu)
+
+/** \brief EA90, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM3_CH5_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010EA90u)
+
+/** \brief EA94, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM3_CH5_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010EA94u)
+
+/** \brief EA98, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM3_CH5_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010EA98u)
+
+/** \brief EA84, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH5_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010EA84u)
+
+/** \brief EAA4, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM3_CH5_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010EAA4u)
+
+/** \brief EAA8, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM3_CH5_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010EAA8u)
+
+/** \brief EAAC, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM3_CH5_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010EAACu)
+
+/** \brief EAA0, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM3_CH5_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010EAA0u)
+
+/** \brief EA80, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM3_CH5_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010EA80u)
+
+/** \brief EA84, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH5_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010EA84u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH5_SOMC.
+* To use register names with standard convension, please use GTM_ATOM3_CH5_SOMC.
+*/
+#define GTM_ATOM3_CH5_CTRL_SOMC (GTM_ATOM3_CH5_SOMC)
+
+/** \brief EA84, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH5_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010EA84u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH5_SOMI.
+* To use register names with standard convension, please use GTM_ATOM3_CH5_SOMI.
+*/
+#define GTM_ATOM3_CH5_CTRL_SOMI (GTM_ATOM3_CH5_SOMI)
+
+/** \brief EA84, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH5_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010EA84u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH5_SOMP.
+* To use register names with standard convension, please use GTM_ATOM3_CH5_SOMP.
+*/
+#define GTM_ATOM3_CH5_CTRL_SOMP (GTM_ATOM3_CH5_SOMP)
+
+/** \brief EA84, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH5_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010EA84u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH5_SOMS.
+* To use register names with standard convension, please use GTM_ATOM3_CH5_SOMS.
+*/
+#define GTM_ATOM3_CH5_CTRL_SOMS (GTM_ATOM3_CH5_SOMS)
+
+/** \brief EA88, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM3_CH5_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010EA88u)
+
+/** \brief EA8C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM3_CH5_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010EA8Cu)
+
+/** \brief EA9C, ATOM Channel Status Register */
+#define GTM_ATOM3_CH5_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010EA9Cu)
+
+/** \brief EB10, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM3_CH6_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010EB10u)
+
+/** \brief EB14, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM3_CH6_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010EB14u)
+
+/** \brief EB18, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM3_CH6_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010EB18u)
+
+/** \brief EB04, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH6_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010EB04u)
+
+/** \brief EB24, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM3_CH6_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010EB24u)
+
+/** \brief EB28, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM3_CH6_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010EB28u)
+
+/** \brief EB2C, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM3_CH6_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010EB2Cu)
+
+/** \brief EB20, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM3_CH6_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010EB20u)
+
+/** \brief EB00, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM3_CH6_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010EB00u)
+
+/** \brief EB04, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH6_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010EB04u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH6_SOMC.
+* To use register names with standard convension, please use GTM_ATOM3_CH6_SOMC.
+*/
+#define GTM_ATOM3_CH6_CTRL_SOMC (GTM_ATOM3_CH6_SOMC)
+
+/** \brief EB04, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH6_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010EB04u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH6_SOMI.
+* To use register names with standard convension, please use GTM_ATOM3_CH6_SOMI.
+*/
+#define GTM_ATOM3_CH6_CTRL_SOMI (GTM_ATOM3_CH6_SOMI)
+
+/** \brief EB04, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH6_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010EB04u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH6_SOMP.
+* To use register names with standard convension, please use GTM_ATOM3_CH6_SOMP.
+*/
+#define GTM_ATOM3_CH6_CTRL_SOMP (GTM_ATOM3_CH6_SOMP)
+
+/** \brief EB04, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH6_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010EB04u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH6_SOMS.
+* To use register names with standard convension, please use GTM_ATOM3_CH6_SOMS.
+*/
+#define GTM_ATOM3_CH6_CTRL_SOMS (GTM_ATOM3_CH6_SOMS)
+
+/** \brief EB08, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM3_CH6_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010EB08u)
+
+/** \brief EB0C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM3_CH6_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010EB0Cu)
+
+/** \brief EB1C, ATOM Channel Status Register */
+#define GTM_ATOM3_CH6_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010EB1Cu)
+
+/** \brief EB90, ATOM Channel CCU0 Compare Register */
+#define GTM_ATOM3_CH7_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM0*)0xF010EB90u)
+
+/** \brief EB94, ATOM Channel CCU1 Compare Register */
+#define GTM_ATOM3_CH7_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CM1*)0xF010EB94u)
+
+/** \brief EB98, ATOM Channel CCU0 Counter Register */
+#define GTM_ATOM3_CH7_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CN0*)0xF010EB98u)
+
+/** \brief EB84, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH7_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_CTRL*)0xF010EB84u)
+
+/** \brief EBA4, ATOM Channel Interrupt Enable Register */
+#define GTM_ATOM3_CH7_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_EN*)0xF010EBA4u)
+
+/** \brief EBA8, ATOM Channel Software Interrupt Generation Register */
+#define GTM_ATOM3_CH7_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_FORCINT*)0xF010EBA8u)
+
+/** \brief EBAC, ATOM IRQ Mode Configuration Register */
+#define GTM_ATOM3_CH7_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_MODE*)0xF010EBACu)
+
+/** \brief EBA0, ATOM Channel Interrupt Notification Register */
+#define GTM_ATOM3_CH7_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_IRQ_NOTIFY*)0xF010EBA0u)
+
+/** \brief EB80, ATOM Channel ARU Read Address Register */
+#define GTM_ATOM3_CH7_RDADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_RDADDR*)0xF010EB80u)
+
+/** \brief EB84, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH7_SOMC /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMC*)0xF010EB84u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH7_SOMC.
+* To use register names with standard convension, please use GTM_ATOM3_CH7_SOMC.
+*/
+#define GTM_ATOM3_CH7_CTRL_SOMC (GTM_ATOM3_CH7_SOMC)
+
+/** \brief EB84, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH7_SOMI /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMI*)0xF010EB84u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH7_SOMI.
+* To use register names with standard convension, please use GTM_ATOM3_CH7_SOMI.
+*/
+#define GTM_ATOM3_CH7_CTRL_SOMI (GTM_ATOM3_CH7_SOMI)
+
+/** \brief EB84, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH7_SOMP /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMP*)0xF010EB84u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH7_SOMP.
+* To use register names with standard convension, please use GTM_ATOM3_CH7_SOMP.
+*/
+#define GTM_ATOM3_CH7_CTRL_SOMP (GTM_ATOM3_CH7_SOMP)
+
+/** \brief EB84, ATOM Channel Control in SOMI mode Register */
+#define GTM_ATOM3_CH7_SOMS /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SOMS*)0xF010EB84u)
+
+/** Alias (User Manual Name) for GTM_ATOM3_CH7_SOMS.
+* To use register names with standard convension, please use GTM_ATOM3_CH7_SOMS.
+*/
+#define GTM_ATOM3_CH7_CTRL_SOMS (GTM_ATOM3_CH7_SOMS)
+
+/** \brief EB88, ATOM Channel CCU0 Compare Shadow Register */
+#define GTM_ATOM3_CH7_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR0*)0xF010EB88u)
+
+/** \brief EB8C, ATOM Channel CCU1 Compare Shadow Register */
+#define GTM_ATOM3_CH7_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_SR1*)0xF010EB8Cu)
+
+/** \brief EB9C, ATOM Channel Status Register */
+#define GTM_ATOM3_CH7_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_ATOM_CH_STAT*)0xF010EB9Cu)
+
+/** \brief 474, BRC Error Interrupt Enable Register */
+#define GTM_BRC_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_BRC_EIRQ_EN*)0xF0100474u)
+
+/** \brief 464, BRC Interrupt Enable Register */
+#define GTM_BRC_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_BRC_IRQ_EN*)0xF0100464u)
+
+/** \brief 468, BRC_DEST_ERR Forcing Interrupt Register */
+#define GTM_BRC_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_BRC_IRQ_FORCINT*)0xF0100468u)
+
+/** \brief 46C, BRC IRQ Mode Configuration Register */
+#define GTM_BRC_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_BRC_IRQ_MODE*)0xF010046Cu)
+
+/** \brief 460, BRC Interrupt Notification Register */
+#define GTM_BRC_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_BRC_IRQ_NOTIFY*)0xF0100460u)
+
+/** \brief 470, BRC Software Reset Register */
+#define GTM_BRC_RST /*lint --e(923)*/ (*(volatile Ifx_GTM_BRC_RST*)0xF0100470u)
+
+/** \brief 400, Read Address For Input Channel 0 */
+#define GTM_BRC_SRC0_ADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_BRC_SRC0_ADDR*)0xF0100400u)
+
+/** \brief 404, Destination Channels For Input Channel 0 */
+#define GTM_BRC_SRC0_DEST /*lint --e(923)*/ (*(volatile Ifx_GTM_BRC_SRC0_DEST*)0xF0100404u)
+
+/** \brief 450, Read Address For Input Channel 10 */
+#define GTM_BRC_SRC10_ADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_BRC_SRC10_ADDR*)0xF0100450u)
+
+/** \brief 454, Destination Channels For Input Channel 10 */
+#define GTM_BRC_SRC10_DEST /*lint --e(923)*/ (*(volatile Ifx_GTM_BRC_SRC10_DEST*)0xF0100454u)
+
+/** \brief 458, Read Address For Input Channel 11 */
+#define GTM_BRC_SRC11_ADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_BRC_SRC11_ADDR*)0xF0100458u)
+
+/** \brief 45C, Destination Channels For Input Channel 11 */
+#define GTM_BRC_SRC11_DEST /*lint --e(923)*/ (*(volatile Ifx_GTM_BRC_SRC11_DEST*)0xF010045Cu)
+
+/** \brief 408, Read Address For Input Channel 1 */
+#define GTM_BRC_SRC1_ADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_BRC_SRC1_ADDR*)0xF0100408u)
+
+/** \brief 40C, Destination Channels For Input Channel 1 */
+#define GTM_BRC_SRC1_DEST /*lint --e(923)*/ (*(volatile Ifx_GTM_BRC_SRC1_DEST*)0xF010040Cu)
+
+/** \brief 410, Read Address For Input Channel 2 */
+#define GTM_BRC_SRC2_ADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_BRC_SRC2_ADDR*)0xF0100410u)
+
+/** \brief 414, Destination Channels For Input Channel 2 */
+#define GTM_BRC_SRC2_DEST /*lint --e(923)*/ (*(volatile Ifx_GTM_BRC_SRC2_DEST*)0xF0100414u)
+
+/** \brief 418, Read Address For Input Channel 3 */
+#define GTM_BRC_SRC3_ADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_BRC_SRC3_ADDR*)0xF0100418u)
+
+/** \brief 41C, Destination Channels For Input Channel 3 */
+#define GTM_BRC_SRC3_DEST /*lint --e(923)*/ (*(volatile Ifx_GTM_BRC_SRC3_DEST*)0xF010041Cu)
+
+/** \brief 420, Read Address For Input Channel 4 */
+#define GTM_BRC_SRC4_ADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_BRC_SRC4_ADDR*)0xF0100420u)
+
+/** \brief 424, Destination Channels For Input Channel 4 */
+#define GTM_BRC_SRC4_DEST /*lint --e(923)*/ (*(volatile Ifx_GTM_BRC_SRC4_DEST*)0xF0100424u)
+
+/** \brief 428, Read Address For Input Channel 5 */
+#define GTM_BRC_SRC5_ADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_BRC_SRC5_ADDR*)0xF0100428u)
+
+/** \brief 42C, Destination Channels For Input Channel 5 */
+#define GTM_BRC_SRC5_DEST /*lint --e(923)*/ (*(volatile Ifx_GTM_BRC_SRC5_DEST*)0xF010042Cu)
+
+/** \brief 430, Read Address For Input Channel 6 */
+#define GTM_BRC_SRC6_ADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_BRC_SRC6_ADDR*)0xF0100430u)
+
+/** \brief 434, Destination Channels For Input Channel 6 */
+#define GTM_BRC_SRC6_DEST /*lint --e(923)*/ (*(volatile Ifx_GTM_BRC_SRC6_DEST*)0xF0100434u)
+
+/** \brief 438, Read Address For Input Channel 7 */
+#define GTM_BRC_SRC7_ADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_BRC_SRC7_ADDR*)0xF0100438u)
+
+/** \brief 43C, Destination Channels For Input Channel 7 */
+#define GTM_BRC_SRC7_DEST /*lint --e(923)*/ (*(volatile Ifx_GTM_BRC_SRC7_DEST*)0xF010043Cu)
+
+/** \brief 440, Read Address For Input Channel 8 */
+#define GTM_BRC_SRC8_ADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_BRC_SRC8_ADDR*)0xF0100440u)
+
+/** \brief 444, Destination Channels For Input Channel 8 */
+#define GTM_BRC_SRC8_DEST /*lint --e(923)*/ (*(volatile Ifx_GTM_BRC_SRC8_DEST*)0xF0100444u)
+
+/** \brief 448, Read Address For Input Channel 9 */
+#define GTM_BRC_SRC9_ADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_BRC_SRC9_ADDR*)0xF0100448u)
+
+/** \brief 44C, Destination Channels For Input Channel 9 */
+#define GTM_BRC_SRC9_DEST /*lint --e(923)*/ (*(volatile Ifx_GTM_BRC_SRC9_DEST*)0xF010044Cu)
+
+/** \brief 30, GTM to SPB BRIDGE MODE */
+#define GTM_BRIDGE_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_BRIDGE_MODE*)0xF0100030u)
+
+/** \brief 34, GTM to SPB BRIDGE PTR1 */
+#define GTM_BRIDGE_PTR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_BRIDGE_PTR1*)0xF0100034u)
+
+/** \brief 38, GTM to SPB BRIDGE PTR2 */
+#define GTM_BRIDGE_PTR2 /*lint --e(923)*/ (*(volatile Ifx_GTM_BRIDGE_PTR2*)0xF0100038u)
+
+/** \brief 9FD00, Clock Control Register */
+#define GTM_CLC /*lint --e(923)*/ (*(volatile Ifx_GTM_CLC*)0xF019FD00u)
+
+/** \brief 214, CMP Error Interrupt Enable Register */
+#define GTM_CMP_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_CMP_EIRQ_EN*)0xF0100214u)
+
+/** \brief 200, CMP Comparator Enable Register */
+#define GTM_CMP_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_CMP_EN*)0xF0100200u)
+
+/** \brief 208, CMP Interrupt Enable Register */
+#define GTM_CMP_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_CMP_IRQ_EN*)0xF0100208u)
+
+/** \brief 20C, CMP Interrupt Force Register */
+#define GTM_CMP_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_CMP_IRQ_FORCINT*)0xF010020Cu)
+
+/** \brief 210, CMP IRQ Mode Configuration Register */
+#define GTM_CMP_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_CMP_IRQ_MODE*)0xF0100210u)
+
+/** \brief 204, CMP Event Notification Register */
+#define GTM_CMP_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_CMP_IRQ_NOTIFY*)0xF0100204u)
+
+/** \brief 30C, CMU Control For Clock Source Register */
+#define GTM_CMU_CLK0_50_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_CMU_CLK0_5_CTRL*)0xF010030Cu)
+
+/** Alias (User Manual Name) for GTM_CMU_CLK0_50_CTRL.
+* To use register names with standard convension, please use GTM_CMU_CLK0_50_CTRL.
+*/
+#define GTM_CMU_CLK_0_CTRL (GTM_CMU_CLK0_50_CTRL)
+
+/** \brief 310, CMU Control For Clock Source Register */
+#define GTM_CMU_CLK0_51_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_CMU_CLK0_5_CTRL*)0xF0100310u)
+
+/** Alias (User Manual Name) for GTM_CMU_CLK0_51_CTRL.
+* To use register names with standard convension, please use GTM_CMU_CLK0_51_CTRL.
+*/
+#define GTM_CMU_CLK_1_CTRL (GTM_CMU_CLK0_51_CTRL)
+
+/** \brief 314, CMU Control For Clock Source Register */
+#define GTM_CMU_CLK0_52_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_CMU_CLK0_5_CTRL*)0xF0100314u)
+
+/** Alias (User Manual Name) for GTM_CMU_CLK0_52_CTRL.
+* To use register names with standard convension, please use GTM_CMU_CLK0_52_CTRL.
+*/
+#define GTM_CMU_CLK_2_CTRL (GTM_CMU_CLK0_52_CTRL)
+
+/** \brief 318, CMU Control For Clock Source Register */
+#define GTM_CMU_CLK0_53_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_CMU_CLK0_5_CTRL*)0xF0100318u)
+
+/** Alias (User Manual Name) for GTM_CMU_CLK0_53_CTRL.
+* To use register names with standard convension, please use GTM_CMU_CLK0_53_CTRL.
+*/
+#define GTM_CMU_CLK_3_CTRL (GTM_CMU_CLK0_53_CTRL)
+
+/** \brief 31C, CMU Control For Clock Source Register */
+#define GTM_CMU_CLK0_54_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_CMU_CLK0_5_CTRL*)0xF010031Cu)
+
+/** Alias (User Manual Name) for GTM_CMU_CLK0_54_CTRL.
+* To use register names with standard convension, please use GTM_CMU_CLK0_54_CTRL.
+*/
+#define GTM_CMU_CLK_4_CTRL (GTM_CMU_CLK0_54_CTRL)
+
+/** \brief 320, CMU Control For Clock Source Register */
+#define GTM_CMU_CLK0_55_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_CMU_CLK0_5_CTRL*)0xF0100320u)
+
+/** Alias (User Manual Name) for GTM_CMU_CLK0_55_CTRL.
+* To use register names with standard convension, please use GTM_CMU_CLK0_55_CTRL.
+*/
+#define GTM_CMU_CLK_5_CTRL (GTM_CMU_CLK0_55_CTRL)
+
+/** \brief 324, CMU Control For Clock Source 6 Register */
+#define GTM_CMU_CLK_6_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_CMU_CLK_6_CTRL*)0xF0100324u)
+
+/** \brief 328, CMU Control For Clock Source 7 Register */
+#define GTM_CMU_CLK_7_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_CMU_CLK_7_CTRL*)0xF0100328u)
+
+/** \brief 300, CMU Clock Enable Register */
+#define GTM_CMU_CLK_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_CMU_CLK_EN*)0xF0100300u)
+
+/** \brief 330, CMU External Clock Control Denominator Register */
+#define GTM_CMU_ECLK0_DEN /*lint --e(923)*/ (*(volatile Ifx_GTM_CMU_ECLK_DEN*)0xF0100330u)
+
+/** Alias (User Manual Name) for GTM_CMU_ECLK0_DEN.
+* To use register names with standard convension, please use GTM_CMU_ECLK0_DEN.
+*/
+#define GTM_CMU_ECLK_0_DEN (GTM_CMU_ECLK0_DEN)
+
+/** \brief 32C, CMU External Clock Control Numerator Register */
+#define GTM_CMU_ECLK0_NUM /*lint --e(923)*/ (*(volatile Ifx_GTM_CMU_ECLK_NUM*)0xF010032Cu)
+
+/** Alias (User Manual Name) for GTM_CMU_ECLK0_NUM.
+* To use register names with standard convension, please use GTM_CMU_ECLK0_NUM.
+*/
+#define GTM_CMU_ECLK_0_NUM (GTM_CMU_ECLK0_NUM)
+
+/** \brief 338, CMU External Clock Control Denominator Register */
+#define GTM_CMU_ECLK1_DEN /*lint --e(923)*/ (*(volatile Ifx_GTM_CMU_ECLK_DEN*)0xF0100338u)
+
+/** Alias (User Manual Name) for GTM_CMU_ECLK1_DEN.
+* To use register names with standard convension, please use GTM_CMU_ECLK1_DEN.
+*/
+#define GTM_CMU_ECLK_1_DEN (GTM_CMU_ECLK1_DEN)
+
+/** \brief 334, CMU External Clock Control Numerator Register */
+#define GTM_CMU_ECLK1_NUM /*lint --e(923)*/ (*(volatile Ifx_GTM_CMU_ECLK_NUM*)0xF0100334u)
+
+/** Alias (User Manual Name) for GTM_CMU_ECLK1_NUM.
+* To use register names with standard convension, please use GTM_CMU_ECLK1_NUM.
+*/
+#define GTM_CMU_ECLK_1_NUM (GTM_CMU_ECLK1_NUM)
+
+/** \brief 340, CMU External Clock Control Denominator Register */
+#define GTM_CMU_ECLK2_DEN /*lint --e(923)*/ (*(volatile Ifx_GTM_CMU_ECLK_DEN*)0xF0100340u)
+
+/** Alias (User Manual Name) for GTM_CMU_ECLK2_DEN.
+* To use register names with standard convension, please use GTM_CMU_ECLK2_DEN.
+*/
+#define GTM_CMU_ECLK_2_DEN (GTM_CMU_ECLK2_DEN)
+
+/** \brief 33C, CMU External Clock Control Numerator Register */
+#define GTM_CMU_ECLK2_NUM /*lint --e(923)*/ (*(volatile Ifx_GTM_CMU_ECLK_NUM*)0xF010033Cu)
+
+/** Alias (User Manual Name) for GTM_CMU_ECLK2_NUM.
+* To use register names with standard convension, please use GTM_CMU_ECLK2_NUM.
+*/
+#define GTM_CMU_ECLK_2_NUM (GTM_CMU_ECLK2_NUM)
+
+/** \brief 344, CMU FXCLK Control Register */
+#define GTM_CMU_FXCLK_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_CMU_FXCLK_CTRL*)0xF0100344u)
+
+/** \brief 308, CMU Global Clock Control Denominator Register */
+#define GTM_CMU_GCLK_DEN /*lint --e(923)*/ (*(volatile Ifx_GTM_CMU_GCLK_DEN*)0xF0100308u)
+
+/** \brief 304, CMU Global Clock Control Numerator Register */
+#define GTM_CMU_GCLK_NUM /*lint --e(923)*/ (*(volatile Ifx_GTM_CMU_GCLK_NUM*)0xF0100304u)
+
+/** \brief 8, GTM Global Control Register */
+#define GTM_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_CTRL*)0xF0100008u)
+
+/** \brief 9FE94, Data Input 0 0 Register */
+#define GTM_DATAIN00 /*lint --e(923)*/ (*(volatile Ifx_GTM_DATAIN*)0xF019FE94u)
+
+/** \brief 9FE98, Data Input 0 0 Register */
+#define GTM_DATAIN01 /*lint --e(923)*/ (*(volatile Ifx_GTM_DATAIN*)0xF019FE98u)
+
+/** \brief 9FE9C, Data Input 0 0 Register */
+#define GTM_DATAIN02 /*lint --e(923)*/ (*(volatile Ifx_GTM_DATAIN*)0xF019FE9Cu)
+
+/** \brief 9FED4, Data Input 0 Register */
+#define GTM_DATAIN10 /*lint --e(923)*/ (*(volatile Ifx_GTM_DATAIN*)0xF019FED4u)
+
+/** \brief 9FED8, Data Input 0 Register */
+#define GTM_DATAIN11 /*lint --e(923)*/ (*(volatile Ifx_GTM_DATAIN*)0xF019FED8u)
+
+/** \brief 9FEDC, Data Input 0 Register */
+#define GTM_DATAIN12 /*lint --e(923)*/ (*(volatile Ifx_GTM_DATAIN*)0xF019FEDCu)
+
+/** \brief 28F00, DPLL Action Control i Register */
+#define GTM_DPLL_ACB0 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ACB*)0xF0128F00u)
+
+/** \brief 28F04, DPLL Action Control i Register */
+#define GTM_DPLL_ACB1 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ACB*)0xF0128F04u)
+
+/** \brief 28F08, DPLL Action Control i Register */
+#define GTM_DPLL_ACB2 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ACB*)0xF0128F08u)
+
+/** \brief 28F0C, DPLL Action Control i Register */
+#define GTM_DPLL_ACB3 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ACB*)0xF0128F0Cu)
+
+/** \brief 28F10, DPLL Action Control i Register */
+#define GTM_DPLL_ACB4 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ACB*)0xF0128F10u)
+
+/** \brief 28F14, DPLL Action Control i Register */
+#define GTM_DPLL_ACB5 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ACB*)0xF0128F14u)
+
+/** \brief 28018, DPLL ACTION Status Register With Shadow Register */
+#define GTM_DPLL_ACT_STA /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ACT_STA*)0xF0128018u)
+
+/** \brief 28438, DPLL Calculated ADD_IN Value for SUB_INC1 Generation */
+#define GTM_DPLL_ADD_IN_CAL1 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADD_IN_CAL1*)0xF0128438u)
+
+/** \brief 2843C, DPLL Calculated ADD_IN Value for SUB_INC2 Generation */
+#define GTM_DPLL_ADD_IN_CAL2 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADD_IN_CAL2*)0xF012843Cu)
+
+/** \brief 280C8, DPLL Direct Load Input Value for SUB_INC1 */
+#define GTM_DPLL_ADD_IN_LD1 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADD_IN_LD1*)0xF01280C8u)
+
+/** \brief 280CC, DPLL Direct Load Input Value for SUB_INC1 */
+#define GTM_DPLL_ADD_IN_LD2 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADD_IN_LD2*)0xF01280CCu)
+
+/** \brief 28800, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S0 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF0128800u)
+
+/** \brief 28804, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S1 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF0128804u)
+
+/** \brief 28828, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S10 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF0128828u)
+
+/** \brief 2882C, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S11 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF012882Cu)
+
+/** \brief 28830, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S12 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF0128830u)
+
+/** \brief 28834, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S13 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF0128834u)
+
+/** \brief 28838, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S14 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF0128838u)
+
+/** \brief 2883C, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S15 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF012883Cu)
+
+/** \brief 28840, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S16 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF0128840u)
+
+/** \brief 28844, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S17 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF0128844u)
+
+/** \brief 28848, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S18 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF0128848u)
+
+/** \brief 2884C, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S19 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF012884Cu)
+
+/** \brief 28808, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S2 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF0128808u)
+
+/** \brief 28850, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S20 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF0128850u)
+
+/** \brief 28854, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S21 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF0128854u)
+
+/** \brief 28858, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S22 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF0128858u)
+
+/** \brief 2885C, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S23 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF012885Cu)
+
+/** \brief 28860, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S24 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF0128860u)
+
+/** \brief 28864, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S25 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF0128864u)
+
+/** \brief 28868, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S26 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF0128868u)
+
+/** \brief 2886C, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S27 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF012886Cu)
+
+/** \brief 28870, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S28 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF0128870u)
+
+/** \brief 28874, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S29 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF0128874u)
+
+/** \brief 2880C, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S3 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF012880Cu)
+
+/** \brief 28878, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S30 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF0128878u)
+
+/** \brief 2887C, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S31 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF012887Cu)
+
+/** \brief 28880, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S32 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF0128880u)
+
+/** \brief 28884, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S33 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF0128884u)
+
+/** \brief 28888, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S34 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF0128888u)
+
+/** \brief 2888C, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S35 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF012888Cu)
+
+/** \brief 28890, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S36 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF0128890u)
+
+/** \brief 28894, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S37 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF0128894u)
+
+/** \brief 28898, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S38 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF0128898u)
+
+/** \brief 2889C, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S39 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF012889Cu)
+
+/** \brief 28810, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S4 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF0128810u)
+
+/** \brief 288A0, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S40 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF01288A0u)
+
+/** \brief 288A4, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S41 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF01288A4u)
+
+/** \brief 288A8, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S42 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF01288A8u)
+
+/** \brief 288AC, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S43 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF01288ACu)
+
+/** \brief 288B0, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S44 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF01288B0u)
+
+/** \brief 288B4, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S45 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF01288B4u)
+
+/** \brief 288B8, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S46 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF01288B8u)
+
+/** \brief 288BC, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S47 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF01288BCu)
+
+/** \brief 288C0, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S48 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF01288C0u)
+
+/** \brief 288C4, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S49 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF01288C4u)
+
+/** \brief 28814, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S5 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF0128814u)
+
+/** \brief 288C8, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S50 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF01288C8u)
+
+/** \brief 288CC, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S51 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF01288CCu)
+
+/** \brief 288D0, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S52 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF01288D0u)
+
+/** \brief 288D4, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S53 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF01288D4u)
+
+/** \brief 288D8, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S54 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF01288D8u)
+
+/** \brief 288DC, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S55 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF01288DCu)
+
+/** \brief 288E0, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S56 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF01288E0u)
+
+/** \brief 288E4, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S57 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF01288E4u)
+
+/** \brief 288E8, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S58 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF01288E8u)
+
+/** \brief 288EC, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S59 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF01288ECu)
+
+/** \brief 28818, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S6 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF0128818u)
+
+/** \brief 288F0, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S60 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF01288F0u)
+
+/** \brief 288F4, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S61 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF01288F4u)
+
+/** \brief 288F8, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S62 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF01288F8u)
+
+/** \brief 288FC, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S63 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF01288FCu)
+
+/** \brief 2881C, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S7 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF012881Cu)
+
+/** \brief 28820, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S8 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF0128820u)
+
+/** \brief 28824, DPLL Adapt Values for All STATE Increments */
+#define GTM_DPLL_ADT_S9 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ADT_S*)0xF0128824u)
+
+/** \brief 28020, DPLL Address Offset Register For APT In RAM Region 2 */
+#define GTM_DPLL_AOSV_2 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_AOSV_2*)0xF0128020u)
+
+/** \brief 28028, DPLL Actual RAM Pointer to RAM Regions 1C1, 1C2 and 1C4 */
+#define GTM_DPLL_APS /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_APS*)0xF0128028u)
+
+/** \brief 28030, DPLL Actual RAM Pointer to RAM Region 1C3 */
+#define GTM_DPLL_APS_1C3 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_APS_1C3*)0xF0128030u)
+
+/** \brief 280BC, DPLL Old RAM Pointer and Offset Value for STATE */
+#define GTM_DPLL_APS_SYNC /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_APS_SYNC*)0xF01280BCu)
+
+/** \brief 28024, DPLL Actual RAM Pointer to RAM Regions 2A, B and D */
+#define GTM_DPLL_APT /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_APT*)0xF0128024u)
+
+/** \brief 2802C, DPLL Actual RAM Pointer to RAM Region 2C */
+#define GTM_DPLL_APT_2C /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_APT_2C*)0xF012802Cu)
+
+/** \brief 280B8, DPLL Old RAM Pointer and Offset Value for TRIGGER */
+#define GTM_DPLL_APT_SYNC /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_APT_SYNC*)0xF01280B8u)
+
+/** \brief 28494, DPLL Prediction of the actual STATE Increment */
+#define GTM_DPLL_CDT_SX /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_CDT_SX*)0xF0128494u)
+
+/** \brief 2849C, DPLL Prediction of the nominal STATE increment duration */
+#define GTM_DPLL_CDT_SX_NOM /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_CDT_SX_NOM*)0xF012849Cu)
+
+/** \brief 28490, DPLL Prediction of the actual TRIGGER Increment */
+#define GTM_DPLL_CDT_TX /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_CDT_TX*)0xF0128490u)
+
+/** \brief 28498, DPLL Prediction of the nominal TRIGGER Increment duration */
+#define GTM_DPLL_CDT_TX_NOM /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_CDT_TX_NOM*)0xF0128498u)
+
+/** \brief 285C8, DPLL Number of Sub-Pulses of SUB_INC1 in Continuous Mode */
+#define GTM_DPLL_CNT_NUM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_CNT_NUM1*)0xF01285C8u)
+
+/** \brief 285CC, DPLL Number of Sub-Pulses of SUB_INC2 in Continuous Mode */
+#define GTM_DPLL_CNT_NUM2 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_CNT_NUM2*)0xF01285CCu)
+
+/** \brief 281EC, DPLL Control 1 Shadow STATE Register */
+#define GTM_DPLL_CRTL_1_SHADOW_STATE /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE*)0xF01281ECu)
+
+/** \brief 28000, DPLL Control Register 0 */
+#define GTM_DPLL_CTRL_0 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_CTRL_0*)0xF0128000u)
+
+/** \brief 281E4, DPLL Control 0 Shadow STATE Register */
+#define GTM_DPLL_CTRL_0_SHADOW_STATE /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_CTRL_0_SHADOW_STATE*)0xF01281E4u)
+
+/** \brief 281E0, DPLL Control0 Shadow Trigger Register */
+#define GTM_DPLL_CTRL_0_SHADOW_TRIGGER /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER*)0xF01281E0u)
+
+/** \brief 28004, DPLL Control Register 1 */
+#define GTM_DPLL_CTRL_1 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_CTRL_1*)0xF0128004u)
+
+/** \brief 281E8, DPLL Control 1 Shadow TRIGGER Register */
+#define GTM_DPLL_CTRL_1_SHADOW_TRIGGER /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER*)0xF01281E8u)
+
+/** \brief 28008, DPLL Control Register 2 */
+#define GTM_DPLL_CTRL_2 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_CTRL_2*)0xF0128008u)
+
+/** \brief 2800C, DPLL Control Register 3 */
+#define GTM_DPLL_CTRL_3 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_CTRL_3*)0xF012800Cu)
+
+/** \brief 28010, DPLL Control Register 4 */
+#define GTM_DPLL_CTRL_4 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_CTRL_4*)0xF0128010u)
+
+/** \brief 28280, DPLL ACTION Time To React Before PSAi Register */
+#define GTM_DPLL_DLA0 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DLA*)0xF0128280u)
+
+/** \brief 28284, DPLL ACTION Time To React Before PSAi Register */
+#define GTM_DPLL_DLA1 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DLA*)0xF0128284u)
+
+/** \brief 282A8, DPLL ACTION Time To React Before PSAi Register */
+#define GTM_DPLL_DLA10 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DLA*)0xF01282A8u)
+
+/** \brief 282AC, DPLL ACTION Time To React Before PSAi Register */
+#define GTM_DPLL_DLA11 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DLA*)0xF01282ACu)
+
+/** \brief 282B0, DPLL ACTION Time To React Before PSAi Register */
+#define GTM_DPLL_DLA12 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DLA*)0xF01282B0u)
+
+/** \brief 282B4, DPLL ACTION Time To React Before PSAi Register */
+#define GTM_DPLL_DLA13 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DLA*)0xF01282B4u)
+
+/** \brief 282B8, DPLL ACTION Time To React Before PSAi Register */
+#define GTM_DPLL_DLA14 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DLA*)0xF01282B8u)
+
+/** \brief 282BC, DPLL ACTION Time To React Before PSAi Register */
+#define GTM_DPLL_DLA15 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DLA*)0xF01282BCu)
+
+/** \brief 282C0, DPLL ACTION Time To React Before PSAi Register */
+#define GTM_DPLL_DLA16 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DLA*)0xF01282C0u)
+
+/** \brief 282C4, DPLL ACTION Time To React Before PSAi Register */
+#define GTM_DPLL_DLA17 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DLA*)0xF01282C4u)
+
+/** \brief 282C8, DPLL ACTION Time To React Before PSAi Register */
+#define GTM_DPLL_DLA18 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DLA*)0xF01282C8u)
+
+/** \brief 282CC, DPLL ACTION Time To React Before PSAi Register */
+#define GTM_DPLL_DLA19 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DLA*)0xF01282CCu)
+
+/** \brief 28288, DPLL ACTION Time To React Before PSAi Register */
+#define GTM_DPLL_DLA2 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DLA*)0xF0128288u)
+
+/** \brief 282D0, DPLL ACTION Time To React Before PSAi Register */
+#define GTM_DPLL_DLA20 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DLA*)0xF01282D0u)
+
+/** \brief 282D4, DPLL ACTION Time To React Before PSAi Register */
+#define GTM_DPLL_DLA21 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DLA*)0xF01282D4u)
+
+/** \brief 282D8, DPLL ACTION Time To React Before PSAi Register */
+#define GTM_DPLL_DLA22 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DLA*)0xF01282D8u)
+
+/** \brief 282DC, DPLL ACTION Time To React Before PSAi Register */
+#define GTM_DPLL_DLA23 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DLA*)0xF01282DCu)
+
+/** \brief 2828C, DPLL ACTION Time To React Before PSAi Register */
+#define GTM_DPLL_DLA3 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DLA*)0xF012828Cu)
+
+/** \brief 28290, DPLL ACTION Time To React Before PSAi Register */
+#define GTM_DPLL_DLA4 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DLA*)0xF0128290u)
+
+/** \brief 28294, DPLL ACTION Time To React Before PSAi Register */
+#define GTM_DPLL_DLA5 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DLA*)0xF0128294u)
+
+/** \brief 28298, DPLL ACTION Time To React Before PSAi Register */
+#define GTM_DPLL_DLA6 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DLA*)0xF0128298u)
+
+/** \brief 2829C, DPLL ACTION Time To React Before PSAi Register */
+#define GTM_DPLL_DLA7 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DLA*)0xF012829Cu)
+
+/** \brief 282A0, DPLL ACTION Time To React Before PSAi Register */
+#define GTM_DPLL_DLA8 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DLA*)0xF01282A0u)
+
+/** \brief 282A4, DPLL ACTION Time To React Before PSAi Register */
+#define GTM_DPLL_DLA9 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DLA*)0xF01282A4u)
+
+/** \brief 28900, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S0 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF0128900u)
+
+/** \brief 28904, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S1 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF0128904u)
+
+/** \brief 28928, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S10 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF0128928u)
+
+/** \brief 2892C, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S11 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF012892Cu)
+
+/** \brief 28930, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S12 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF0128930u)
+
+/** \brief 28934, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S13 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF0128934u)
+
+/** \brief 28938, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S14 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF0128938u)
+
+/** \brief 2893C, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S15 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF012893Cu)
+
+/** \brief 28940, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S16 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF0128940u)
+
+/** \brief 28944, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S17 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF0128944u)
+
+/** \brief 28948, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S18 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF0128948u)
+
+/** \brief 2894C, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S19 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF012894Cu)
+
+/** \brief 28908, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S2 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF0128908u)
+
+/** \brief 28950, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S20 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF0128950u)
+
+/** \brief 28954, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S21 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF0128954u)
+
+/** \brief 28958, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S22 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF0128958u)
+
+/** \brief 2895C, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S23 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF012895Cu)
+
+/** \brief 28960, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S24 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF0128960u)
+
+/** \brief 28964, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S25 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF0128964u)
+
+/** \brief 28968, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S26 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF0128968u)
+
+/** \brief 2896C, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S27 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF012896Cu)
+
+/** \brief 28970, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S28 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF0128970u)
+
+/** \brief 28974, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S29 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF0128974u)
+
+/** \brief 2890C, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S3 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF012890Cu)
+
+/** \brief 28978, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S30 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF0128978u)
+
+/** \brief 2897C, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S31 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF012897Cu)
+
+/** \brief 28980, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S32 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF0128980u)
+
+/** \brief 28984, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S33 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF0128984u)
+
+/** \brief 28988, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S34 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF0128988u)
+
+/** \brief 2898C, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S35 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF012898Cu)
+
+/** \brief 28990, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S36 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF0128990u)
+
+/** \brief 28994, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S37 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF0128994u)
+
+/** \brief 28998, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S38 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF0128998u)
+
+/** \brief 2899C, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S39 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF012899Cu)
+
+/** \brief 28910, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S4 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF0128910u)
+
+/** \brief 289A0, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S40 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF01289A0u)
+
+/** \brief 289A4, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S41 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF01289A4u)
+
+/** \brief 289A8, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S42 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF01289A8u)
+
+/** \brief 289AC, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S43 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF01289ACu)
+
+/** \brief 289B0, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S44 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF01289B0u)
+
+/** \brief 289B4, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S45 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF01289B4u)
+
+/** \brief 289B8, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S46 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF01289B8u)
+
+/** \brief 289BC, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S47 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF01289BCu)
+
+/** \brief 289C0, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S48 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF01289C0u)
+
+/** \brief 289C4, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S49 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF01289C4u)
+
+/** \brief 28914, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S5 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF0128914u)
+
+/** \brief 289C8, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S50 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF01289C8u)
+
+/** \brief 289CC, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S51 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF01289CCu)
+
+/** \brief 289D0, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S52 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF01289D0u)
+
+/** \brief 289D4, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S53 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF01289D4u)
+
+/** \brief 289D8, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S54 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF01289D8u)
+
+/** \brief 289DC, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S55 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF01289DCu)
+
+/** \brief 289E0, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S56 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF01289E0u)
+
+/** \brief 289E4, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S57 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF01289E4u)
+
+/** \brief 289E8, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S58 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF01289E8u)
+
+/** \brief 289EC, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S59 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF01289ECu)
+
+/** \brief 28918, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S6 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF0128918u)
+
+/** \brief 289F0, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S60 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF01289F0u)
+
+/** \brief 289F4, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S61 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF01289F4u)
+
+/** \brief 289F8, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S62 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF01289F8u)
+
+/** \brief 289FC, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S63 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF01289FCu)
+
+/** \brief 2891C, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S7 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF012891Cu)
+
+/** \brief 28920, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S8 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF0128920u)
+
+/** \brief 28924, DPLL Nominal STATE Increment Values for FULL_SCALE */
+#define GTM_DPLL_DT_S9 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S*)0xF0128924u)
+
+/** \brief 2847C, DPLL Duration of Last STATE Increment [DT_S_ACT] */
+#define GTM_DPLL_DT_S_ACT /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_S_ACT*)0xF012847Cu)
+
+/** \brief 28478, DPLL Duration of Last TRIGGER Increment */
+#define GTM_DPLL_DT_T_ACT /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DT_T_ACT*)0xF0128478u)
+
+/** \brief 28380, DPLL Calculated Relative Time To ACTION_i Register */
+#define GTM_DPLL_DTA0 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DTA*)0xF0128380u)
+
+/** \brief 28384, DPLL Calculated Relative Time To ACTION_i Register */
+#define GTM_DPLL_DTA1 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DTA*)0xF0128384u)
+
+/** \brief 283A8, DPLL Calculated Relative Time To ACTION_i Register */
+#define GTM_DPLL_DTA10 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DTA*)0xF01283A8u)
+
+/** \brief 283AC, DPLL Calculated Relative Time To ACTION_i Register */
+#define GTM_DPLL_DTA11 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DTA*)0xF01283ACu)
+
+/** \brief 283B0, DPLL Calculated Relative Time To ACTION_i Register */
+#define GTM_DPLL_DTA12 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DTA*)0xF01283B0u)
+
+/** \brief 283B4, DPLL Calculated Relative Time To ACTION_i Register */
+#define GTM_DPLL_DTA13 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DTA*)0xF01283B4u)
+
+/** \brief 283B8, DPLL Calculated Relative Time To ACTION_i Register */
+#define GTM_DPLL_DTA14 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DTA*)0xF01283B8u)
+
+/** \brief 283BC, DPLL Calculated Relative Time To ACTION_i Register */
+#define GTM_DPLL_DTA15 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DTA*)0xF01283BCu)
+
+/** \brief 283C0, DPLL Calculated Relative Time To ACTION_i Register */
+#define GTM_DPLL_DTA16 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DTA*)0xF01283C0u)
+
+/** \brief 283C4, DPLL Calculated Relative Time To ACTION_i Register */
+#define GTM_DPLL_DTA17 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DTA*)0xF01283C4u)
+
+/** \brief 283C8, DPLL Calculated Relative Time To ACTION_i Register */
+#define GTM_DPLL_DTA18 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DTA*)0xF01283C8u)
+
+/** \brief 283CC, DPLL Calculated Relative Time To ACTION_i Register */
+#define GTM_DPLL_DTA19 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DTA*)0xF01283CCu)
+
+/** \brief 28388, DPLL Calculated Relative Time To ACTION_i Register */
+#define GTM_DPLL_DTA2 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DTA*)0xF0128388u)
+
+/** \brief 283D0, DPLL Calculated Relative Time To ACTION_i Register */
+#define GTM_DPLL_DTA20 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DTA*)0xF01283D0u)
+
+/** \brief 283D4, DPLL Calculated Relative Time To ACTION_i Register */
+#define GTM_DPLL_DTA21 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DTA*)0xF01283D4u)
+
+/** \brief 283D8, DPLL Calculated Relative Time To ACTION_i Register */
+#define GTM_DPLL_DTA22 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DTA*)0xF01283D8u)
+
+/** \brief 283DC, DPLL Calculated Relative Time To ACTION_i Register */
+#define GTM_DPLL_DTA23 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DTA*)0xF01283DCu)
+
+/** \brief 2838C, DPLL Calculated Relative Time To ACTION_i Register */
+#define GTM_DPLL_DTA3 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DTA*)0xF012838Cu)
+
+/** \brief 28390, DPLL Calculated Relative Time To ACTION_i Register */
+#define GTM_DPLL_DTA4 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DTA*)0xF0128390u)
+
+/** \brief 28394, DPLL Calculated Relative Time To ACTION_i Register */
+#define GTM_DPLL_DTA5 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DTA*)0xF0128394u)
+
+/** \brief 28398, DPLL Calculated Relative Time To ACTION_i Register */
+#define GTM_DPLL_DTA6 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DTA*)0xF0128398u)
+
+/** \brief 2839C, DPLL Calculated Relative Time To ACTION_i Register */
+#define GTM_DPLL_DTA7 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DTA*)0xF012839Cu)
+
+/** \brief 283A0, DPLL Calculated Relative Time To ACTION_i Register */
+#define GTM_DPLL_DTA8 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DTA*)0xF01283A0u)
+
+/** \brief 283A4, DPLL Calculated Relative Time To ACTION_i Register */
+#define GTM_DPLL_DTA9 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_DTA*)0xF01283A4u)
+
+/** \brief 28488, DPLL Difference of Prediction to actual value for Last STATE
+ * Increment */
+#define GTM_DPLL_EDT_S /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_EDT_S*)0xF0128488u)
+
+/** \brief 28480, DPLL Difference of prediction to actual value of the last
+ * TRIGGER increment */
+#define GTM_DPLL_EDT_T /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_EDT_T*)0xF0128480u)
+
+/** \brief 28050, DPLL Error Interrupt Enable Register */
+#define GTM_DPLL_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_EIRQ_EN*)0xF0128050u)
+
+/** \brief 28418, DPLL Actual Signal STATE Filter Value Register */
+#define GTM_DPLL_FTV_S /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_FTV_S*)0xF0128418u)
+
+/** \brief 28408, DPLL Actual Signal TRIGGER Filter Value Register */
+#define GTM_DPLL_FTV_T /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_FTV_T*)0xF0128408u)
+
+/** \brief 28100, DPLL ID Information For Input Signal PMTR n Register */
+#define GTM_DPLL_ID_PMTR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ID_PMTR*)0xF0128100u)
+
+/** Alias (User Manual Name) for GTM_DPLL_ID_PMTR0.
+* To use register names with standard convension, please use GTM_DPLL_ID_PMTR0.
+*/
+#define GTM_DPLL_ID_PMTR_0 (GTM_DPLL_ID_PMTR0)
+
+/** \brief 28104, DPLL ID Information For Input Signal PMTR n Register */
+#define GTM_DPLL_ID_PMTR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ID_PMTR*)0xF0128104u)
+
+/** Alias (User Manual Name) for GTM_DPLL_ID_PMTR1.
+* To use register names with standard convension, please use GTM_DPLL_ID_PMTR1.
+*/
+#define GTM_DPLL_ID_PMTR_1 (GTM_DPLL_ID_PMTR1)
+
+/** \brief 28128, DPLL ID Information For Input Signal PMTR n Register */
+#define GTM_DPLL_ID_PMTR10 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ID_PMTR*)0xF0128128u)
+
+/** Alias (User Manual Name) for GTM_DPLL_ID_PMTR10.
+* To use register names with standard convension, please use GTM_DPLL_ID_PMTR10.
+*/
+#define GTM_DPLL_ID_PMTR_10 (GTM_DPLL_ID_PMTR10)
+
+/** \brief 2812C, DPLL ID Information For Input Signal PMTR n Register */
+#define GTM_DPLL_ID_PMTR11 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ID_PMTR*)0xF012812Cu)
+
+/** Alias (User Manual Name) for GTM_DPLL_ID_PMTR11.
+* To use register names with standard convension, please use GTM_DPLL_ID_PMTR11.
+*/
+#define GTM_DPLL_ID_PMTR_11 (GTM_DPLL_ID_PMTR11)
+
+/** \brief 28130, DPLL ID Information For Input Signal PMTR n Register */
+#define GTM_DPLL_ID_PMTR12 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ID_PMTR*)0xF0128130u)
+
+/** Alias (User Manual Name) for GTM_DPLL_ID_PMTR12.
+* To use register names with standard convension, please use GTM_DPLL_ID_PMTR12.
+*/
+#define GTM_DPLL_ID_PMTR_12 (GTM_DPLL_ID_PMTR12)
+
+/** \brief 28134, DPLL ID Information For Input Signal PMTR n Register */
+#define GTM_DPLL_ID_PMTR13 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ID_PMTR*)0xF0128134u)
+
+/** Alias (User Manual Name) for GTM_DPLL_ID_PMTR13.
+* To use register names with standard convension, please use GTM_DPLL_ID_PMTR13.
+*/
+#define GTM_DPLL_ID_PMTR_13 (GTM_DPLL_ID_PMTR13)
+
+/** \brief 28138, DPLL ID Information For Input Signal PMTR n Register */
+#define GTM_DPLL_ID_PMTR14 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ID_PMTR*)0xF0128138u)
+
+/** Alias (User Manual Name) for GTM_DPLL_ID_PMTR14.
+* To use register names with standard convension, please use GTM_DPLL_ID_PMTR14.
+*/
+#define GTM_DPLL_ID_PMTR_14 (GTM_DPLL_ID_PMTR14)
+
+/** \brief 2813C, DPLL ID Information For Input Signal PMTR n Register */
+#define GTM_DPLL_ID_PMTR15 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ID_PMTR*)0xF012813Cu)
+
+/** Alias (User Manual Name) for GTM_DPLL_ID_PMTR15.
+* To use register names with standard convension, please use GTM_DPLL_ID_PMTR15.
+*/
+#define GTM_DPLL_ID_PMTR_15 (GTM_DPLL_ID_PMTR15)
+
+/** \brief 28140, DPLL ID Information For Input Signal PMTR n Register */
+#define GTM_DPLL_ID_PMTR16 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ID_PMTR*)0xF0128140u)
+
+/** Alias (User Manual Name) for GTM_DPLL_ID_PMTR16.
+* To use register names with standard convension, please use GTM_DPLL_ID_PMTR16.
+*/
+#define GTM_DPLL_ID_PMTR_16 (GTM_DPLL_ID_PMTR16)
+
+/** \brief 28144, DPLL ID Information For Input Signal PMTR n Register */
+#define GTM_DPLL_ID_PMTR17 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ID_PMTR*)0xF0128144u)
+
+/** Alias (User Manual Name) for GTM_DPLL_ID_PMTR17.
+* To use register names with standard convension, please use GTM_DPLL_ID_PMTR17.
+*/
+#define GTM_DPLL_ID_PMTR_17 (GTM_DPLL_ID_PMTR17)
+
+/** \brief 28148, DPLL ID Information For Input Signal PMTR n Register */
+#define GTM_DPLL_ID_PMTR18 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ID_PMTR*)0xF0128148u)
+
+/** Alias (User Manual Name) for GTM_DPLL_ID_PMTR18.
+* To use register names with standard convension, please use GTM_DPLL_ID_PMTR18.
+*/
+#define GTM_DPLL_ID_PMTR_18 (GTM_DPLL_ID_PMTR18)
+
+/** \brief 2814C, DPLL ID Information For Input Signal PMTR n Register */
+#define GTM_DPLL_ID_PMTR19 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ID_PMTR*)0xF012814Cu)
+
+/** Alias (User Manual Name) for GTM_DPLL_ID_PMTR19.
+* To use register names with standard convension, please use GTM_DPLL_ID_PMTR19.
+*/
+#define GTM_DPLL_ID_PMTR_19 (GTM_DPLL_ID_PMTR19)
+
+/** \brief 28108, DPLL ID Information For Input Signal PMTR n Register */
+#define GTM_DPLL_ID_PMTR2 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ID_PMTR*)0xF0128108u)
+
+/** Alias (User Manual Name) for GTM_DPLL_ID_PMTR2.
+* To use register names with standard convension, please use GTM_DPLL_ID_PMTR2.
+*/
+#define GTM_DPLL_ID_PMTR_2 (GTM_DPLL_ID_PMTR2)
+
+/** \brief 28150, DPLL ID Information For Input Signal PMTR n Register */
+#define GTM_DPLL_ID_PMTR20 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ID_PMTR*)0xF0128150u)
+
+/** Alias (User Manual Name) for GTM_DPLL_ID_PMTR20.
+* To use register names with standard convension, please use GTM_DPLL_ID_PMTR20.
+*/
+#define GTM_DPLL_ID_PMTR_20 (GTM_DPLL_ID_PMTR20)
+
+/** \brief 28154, DPLL ID Information For Input Signal PMTR n Register */
+#define GTM_DPLL_ID_PMTR21 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ID_PMTR*)0xF0128154u)
+
+/** Alias (User Manual Name) for GTM_DPLL_ID_PMTR21.
+* To use register names with standard convension, please use GTM_DPLL_ID_PMTR21.
+*/
+#define GTM_DPLL_ID_PMTR_21 (GTM_DPLL_ID_PMTR21)
+
+/** \brief 28158, DPLL ID Information For Input Signal PMTR n Register */
+#define GTM_DPLL_ID_PMTR22 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ID_PMTR*)0xF0128158u)
+
+/** Alias (User Manual Name) for GTM_DPLL_ID_PMTR22.
+* To use register names with standard convension, please use GTM_DPLL_ID_PMTR22.
+*/
+#define GTM_DPLL_ID_PMTR_22 (GTM_DPLL_ID_PMTR22)
+
+/** \brief 2815C, DPLL ID Information For Input Signal PMTR n Register */
+#define GTM_DPLL_ID_PMTR23 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ID_PMTR*)0xF012815Cu)
+
+/** Alias (User Manual Name) for GTM_DPLL_ID_PMTR23.
+* To use register names with standard convension, please use GTM_DPLL_ID_PMTR23.
+*/
+#define GTM_DPLL_ID_PMTR_23 (GTM_DPLL_ID_PMTR23)
+
+/** \brief 2810C, DPLL ID Information For Input Signal PMTR n Register */
+#define GTM_DPLL_ID_PMTR3 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ID_PMTR*)0xF012810Cu)
+
+/** Alias (User Manual Name) for GTM_DPLL_ID_PMTR3.
+* To use register names with standard convension, please use GTM_DPLL_ID_PMTR3.
+*/
+#define GTM_DPLL_ID_PMTR_3 (GTM_DPLL_ID_PMTR3)
+
+/** \brief 28110, DPLL ID Information For Input Signal PMTR n Register */
+#define GTM_DPLL_ID_PMTR4 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ID_PMTR*)0xF0128110u)
+
+/** Alias (User Manual Name) for GTM_DPLL_ID_PMTR4.
+* To use register names with standard convension, please use GTM_DPLL_ID_PMTR4.
+*/
+#define GTM_DPLL_ID_PMTR_4 (GTM_DPLL_ID_PMTR4)
+
+/** \brief 28114, DPLL ID Information For Input Signal PMTR n Register */
+#define GTM_DPLL_ID_PMTR5 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ID_PMTR*)0xF0128114u)
+
+/** Alias (User Manual Name) for GTM_DPLL_ID_PMTR5.
+* To use register names with standard convension, please use GTM_DPLL_ID_PMTR5.
+*/
+#define GTM_DPLL_ID_PMTR_5 (GTM_DPLL_ID_PMTR5)
+
+/** \brief 28118, DPLL ID Information For Input Signal PMTR n Register */
+#define GTM_DPLL_ID_PMTR6 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ID_PMTR*)0xF0128118u)
+
+/** Alias (User Manual Name) for GTM_DPLL_ID_PMTR6.
+* To use register names with standard convension, please use GTM_DPLL_ID_PMTR6.
+*/
+#define GTM_DPLL_ID_PMTR_6 (GTM_DPLL_ID_PMTR6)
+
+/** \brief 2811C, DPLL ID Information For Input Signal PMTR n Register */
+#define GTM_DPLL_ID_PMTR7 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ID_PMTR*)0xF012811Cu)
+
+/** Alias (User Manual Name) for GTM_DPLL_ID_PMTR7.
+* To use register names with standard convension, please use GTM_DPLL_ID_PMTR7.
+*/
+#define GTM_DPLL_ID_PMTR_7 (GTM_DPLL_ID_PMTR7)
+
+/** \brief 28120, DPLL ID Information For Input Signal PMTR n Register */
+#define GTM_DPLL_ID_PMTR8 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ID_PMTR*)0xF0128120u)
+
+/** Alias (User Manual Name) for GTM_DPLL_ID_PMTR8.
+* To use register names with standard convension, please use GTM_DPLL_ID_PMTR8.
+*/
+#define GTM_DPLL_ID_PMTR_8 (GTM_DPLL_ID_PMTR8)
+
+/** \brief 28124, DPLL ID Information For Input Signal PMTR n Register */
+#define GTM_DPLL_ID_PMTR9 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_ID_PMTR*)0xF0128124u)
+
+/** Alias (User Manual Name) for GTM_DPLL_ID_PMTR9.
+* To use register names with standard convension, please use GTM_DPLL_ID_PMTR9.
+*/
+#define GTM_DPLL_ID_PMTR_9 (GTM_DPLL_ID_PMTR9)
+
+/** \brief 280B0, DPLL Counter for Pulses for TBU_TS1 to be sent in Automatic
+ * End Mode */
+#define GTM_DPLL_INC_CNT1 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_INC_CNT1*)0xF01280B0u)
+
+/** \brief 280B4, DPLL Counter for Pulses for TBU_TS2 to be sent in Automatic
+ * End Mode when SMC=RMO=1 */
+#define GTM_DPLL_INC_CNT2 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_INC_CNT2*)0xF01280B4u)
+
+/** \brief 28044, DPLL Interrupt Enable Register */
+#define GTM_DPLL_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_IRQ_EN*)0xF0128044u)
+
+/** \brief 28048, DPLL Interrupt Force Register */
+#define GTM_DPLL_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_IRQ_FORCINT*)0xF0128048u)
+
+/** \brief 2804C, DPLL Interrupt Mode Register */
+#define GTM_DPLL_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_IRQ_MODE*)0xF012804Cu)
+
+/** \brief 28040, DPLL Interrupt Notification Register */
+#define GTM_DPLL_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_IRQ_NOTIFY*)0xF0128040u)
+
+/** \brief 2848C, DPLL Weighted difference of Prediction up to the Last STATE
+ * Increment */
+#define GTM_DPLL_MEDT_S /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_MEDT_S*)0xF012848Cu)
+
+/** \brief 28484, DPLL Weighted difference of Prediction up to the Last TRIGGER
+ * Increment */
+#define GTM_DPLL_MEDT_T /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_MEDT_T*)0xF0128484u)
+
+/** \brief 285C0, DPLL Calculated Number of Sub-Pulses between Two STATE Events */
+#define GTM_DPLL_MLS1 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_MLS1*)0xF01285C0u)
+
+/** \brief 285C4, DPLL Calculated Number of Sub-Pulses between Two STATE Events */
+#define GTM_DPLL_MLS2 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_MLS2*)0xF01285C4u)
+
+/** \brief 28440, DPLL Missing Pulses to be Added/Subtracted Directly to
+ * SUB_INC1 and INC_CNT1 Once */
+#define GTM_DPLL_MPVAL1 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_MPVAL1*)0xF0128440u)
+
+/** \brief 28444, DPLL Missing Pulses to be Added/Subtracted Directly to
+ * SUB_INC2 and INC_CNT2 Once */
+#define GTM_DPLL_MPVAL2 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_MPVAL2*)0xF0128444u)
+
+/** \brief 28300, DPLL Calculated Number Of TRIGGER/STATE Increments To ACTION */
+#define GTM_DPLL_NA0 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NA*)0xF0128300u)
+
+/** \brief 28304, DPLL Calculated Number Of TRIGGER/STATE Increments To ACTION */
+#define GTM_DPLL_NA1 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NA*)0xF0128304u)
+
+/** \brief 28328, DPLL Calculated Number Of TRIGGER/STATE Increments To ACTION */
+#define GTM_DPLL_NA10 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NA*)0xF0128328u)
+
+/** \brief 2832C, DPLL Calculated Number Of TRIGGER/STATE Increments To ACTION */
+#define GTM_DPLL_NA11 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NA*)0xF012832Cu)
+
+/** \brief 28330, DPLL Calculated Number Of TRIGGER/STATE Increments To ACTION */
+#define GTM_DPLL_NA12 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NA*)0xF0128330u)
+
+/** \brief 28334, DPLL Calculated Number Of TRIGGER/STATE Increments To ACTION */
+#define GTM_DPLL_NA13 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NA*)0xF0128334u)
+
+/** \brief 28338, DPLL Calculated Number Of TRIGGER/STATE Increments To ACTION */
+#define GTM_DPLL_NA14 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NA*)0xF0128338u)
+
+/** \brief 2833C, DPLL Calculated Number Of TRIGGER/STATE Increments To ACTION */
+#define GTM_DPLL_NA15 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NA*)0xF012833Cu)
+
+/** \brief 28340, DPLL Calculated Number Of TRIGGER/STATE Increments To ACTION */
+#define GTM_DPLL_NA16 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NA*)0xF0128340u)
+
+/** \brief 28344, DPLL Calculated Number Of TRIGGER/STATE Increments To ACTION */
+#define GTM_DPLL_NA17 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NA*)0xF0128344u)
+
+/** \brief 28348, DPLL Calculated Number Of TRIGGER/STATE Increments To ACTION */
+#define GTM_DPLL_NA18 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NA*)0xF0128348u)
+
+/** \brief 2834C, DPLL Calculated Number Of TRIGGER/STATE Increments To ACTION */
+#define GTM_DPLL_NA19 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NA*)0xF012834Cu)
+
+/** \brief 28308, DPLL Calculated Number Of TRIGGER/STATE Increments To ACTION */
+#define GTM_DPLL_NA2 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NA*)0xF0128308u)
+
+/** \brief 28350, DPLL Calculated Number Of TRIGGER/STATE Increments To ACTION */
+#define GTM_DPLL_NA20 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NA*)0xF0128350u)
+
+/** \brief 28354, DPLL Calculated Number Of TRIGGER/STATE Increments To ACTION */
+#define GTM_DPLL_NA21 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NA*)0xF0128354u)
+
+/** \brief 28358, DPLL Calculated Number Of TRIGGER/STATE Increments To ACTION */
+#define GTM_DPLL_NA22 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NA*)0xF0128358u)
+
+/** \brief 2835C, DPLL Calculated Number Of TRIGGER/STATE Increments To ACTION */
+#define GTM_DPLL_NA23 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NA*)0xF012835Cu)
+
+/** \brief 2830C, DPLL Calculated Number Of TRIGGER/STATE Increments To ACTION */
+#define GTM_DPLL_NA3 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NA*)0xF012830Cu)
+
+/** \brief 28310, DPLL Calculated Number Of TRIGGER/STATE Increments To ACTION */
+#define GTM_DPLL_NA4 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NA*)0xF0128310u)
+
+/** \brief 28314, DPLL Calculated Number Of TRIGGER/STATE Increments To ACTION */
+#define GTM_DPLL_NA5 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NA*)0xF0128314u)
+
+/** \brief 28318, DPLL Calculated Number Of TRIGGER/STATE Increments To ACTION */
+#define GTM_DPLL_NA6 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NA*)0xF0128318u)
+
+/** \brief 2831C, DPLL Calculated Number Of TRIGGER/STATE Increments To ACTION */
+#define GTM_DPLL_NA7 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NA*)0xF012831Cu)
+
+/** \brief 28320, DPLL Calculated Number Of TRIGGER/STATE Increments To ACTION */
+#define GTM_DPLL_NA8 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NA*)0xF0128320u)
+
+/** \brief 28324, DPLL Calculated Number Of TRIGGER/STATE Increments To ACTION */
+#define GTM_DPLL_NA9 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NA*)0xF0128324u)
+
+/** \brief 285FC, DPLL Number of Pulses of Current Increment in Emergency Mode */
+#define GTM_DPLL_NMB_S /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NMB_S*)0xF01285FCu)
+
+/** \brief 28450, DPLL Target Number of Pulses to be sent in emergency mode
+ * Register */
+#define GTM_DPLL_NMB_S_TAR /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NMB_S_TAR*)0xF0128450u)
+
+/** \brief 28454, DPLL Target Number of Pulses to be sent in emergency mode
+ * Register */
+#define GTM_DPLL_NMB_S_TAR_OLD /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NMB_S_TAR_OLD*)0xF0128454u)
+
+/** \brief 285F8, DPLL Number of Pulses of Current Increment in Normal Mode */
+#define GTM_DPLL_NMB_T /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NMB_T*)0xF01285F8u)
+
+/** \brief 28448, DPLL Target Number of Pulses to be sent in normal mode
+ * Register */
+#define GTM_DPLL_NMB_T_TAR /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NMB_T_TAR*)0xF0128448u)
+
+/** \brief 2844C, DPLL Target Number of Pulses to be sent in normal mode
+ * Register */
+#define GTM_DPLL_NMB_T_TAR_OLD /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NMB_T_TAR_OLD*)0xF012844Cu)
+
+/** \brief 2803C, DPLL Number of Active TRIGGER Events to Interrupt */
+#define GTM_DPLL_NTI_CNT /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NTI_CNT*)0xF012803Cu)
+
+/** \brief 28038, DPLL Number of Recent STATE Events Used for Calculations */
+#define GTM_DPLL_NUSC /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NUSC*)0xF0128038u)
+
+/** \brief 28034, DPLL Number of Recent TRIGGER Events Used for Calculations */
+#define GTM_DPLL_NUTC /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_NUTC*)0xF0128034u)
+
+/** \brief 2801C, DPLL Offset And Switch Old/New Address Register */
+#define GTM_DPLL_OSW /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_OSW*)0xF012801Cu)
+
+/** \brief 28500, DPLL Projected TRIGGER Increment Sum Relations for Action_i */
+#define GTM_DPLL_PDT_T0 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PDT_T*)0xF0128500u)
+
+/** \brief 28504, DPLL Projected TRIGGER Increment Sum Relations for Action_i */
+#define GTM_DPLL_PDT_T1 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PDT_T*)0xF0128504u)
+
+/** \brief 28528, DPLL Projected TRIGGER Increment Sum Relations for Action_i */
+#define GTM_DPLL_PDT_T10 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PDT_T*)0xF0128528u)
+
+/** \brief 2852C, DPLL Projected TRIGGER Increment Sum Relations for Action_i */
+#define GTM_DPLL_PDT_T11 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PDT_T*)0xF012852Cu)
+
+/** \brief 28530, DPLL Projected TRIGGER Increment Sum Relations for Action_i */
+#define GTM_DPLL_PDT_T12 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PDT_T*)0xF0128530u)
+
+/** \brief 28534, DPLL Projected TRIGGER Increment Sum Relations for Action_i */
+#define GTM_DPLL_PDT_T13 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PDT_T*)0xF0128534u)
+
+/** \brief 28538, DPLL Projected TRIGGER Increment Sum Relations for Action_i */
+#define GTM_DPLL_PDT_T14 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PDT_T*)0xF0128538u)
+
+/** \brief 2853C, DPLL Projected TRIGGER Increment Sum Relations for Action_i */
+#define GTM_DPLL_PDT_T15 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PDT_T*)0xF012853Cu)
+
+/** \brief 28540, DPLL Projected TRIGGER Increment Sum Relations for Action_i */
+#define GTM_DPLL_PDT_T16 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PDT_T*)0xF0128540u)
+
+/** \brief 28544, DPLL Projected TRIGGER Increment Sum Relations for Action_i */
+#define GTM_DPLL_PDT_T17 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PDT_T*)0xF0128544u)
+
+/** \brief 28548, DPLL Projected TRIGGER Increment Sum Relations for Action_i */
+#define GTM_DPLL_PDT_T18 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PDT_T*)0xF0128548u)
+
+/** \brief 2854C, DPLL Projected TRIGGER Increment Sum Relations for Action_i */
+#define GTM_DPLL_PDT_T19 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PDT_T*)0xF012854Cu)
+
+/** \brief 28508, DPLL Projected TRIGGER Increment Sum Relations for Action_i */
+#define GTM_DPLL_PDT_T2 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PDT_T*)0xF0128508u)
+
+/** \brief 28550, DPLL Projected TRIGGER Increment Sum Relations for Action_i */
+#define GTM_DPLL_PDT_T20 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PDT_T*)0xF0128550u)
+
+/** \brief 28554, DPLL Projected TRIGGER Increment Sum Relations for Action_i */
+#define GTM_DPLL_PDT_T21 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PDT_T*)0xF0128554u)
+
+/** \brief 28558, DPLL Projected TRIGGER Increment Sum Relations for Action_i */
+#define GTM_DPLL_PDT_T22 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PDT_T*)0xF0128558u)
+
+/** \brief 2855C, DPLL Projected TRIGGER Increment Sum Relations for Action_i */
+#define GTM_DPLL_PDT_T23 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PDT_T*)0xF012855Cu)
+
+/** \brief 2850C, DPLL Projected TRIGGER Increment Sum Relations for Action_i */
+#define GTM_DPLL_PDT_T3 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PDT_T*)0xF012850Cu)
+
+/** \brief 28510, DPLL Projected TRIGGER Increment Sum Relations for Action_i */
+#define GTM_DPLL_PDT_T4 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PDT_T*)0xF0128510u)
+
+/** \brief 28514, DPLL Projected TRIGGER Increment Sum Relations for Action_i */
+#define GTM_DPLL_PDT_T5 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PDT_T*)0xF0128514u)
+
+/** \brief 28518, DPLL Projected TRIGGER Increment Sum Relations for Action_i */
+#define GTM_DPLL_PDT_T6 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PDT_T*)0xF0128518u)
+
+/** \brief 2851C, DPLL Projected TRIGGER Increment Sum Relations for Action_i */
+#define GTM_DPLL_PDT_T7 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PDT_T*)0xF012851Cu)
+
+/** \brief 28520, DPLL Projected TRIGGER Increment Sum Relations for Action_i */
+#define GTM_DPLL_PDT_T8 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PDT_T*)0xF0128520u)
+
+/** \brief 28524, DPLL Projected TRIGGER Increment Sum Relations for Action_i */
+#define GTM_DPLL_PDT_T9 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PDT_T*)0xF0128524u)
+
+/** \brief 28200, DPLL ACTION Position/Value Action Request Register */
+#define GTM_DPLL_PSA0 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSA*)0xF0128200u)
+
+/** \brief 28204, DPLL ACTION Position/Value Action Request Register */
+#define GTM_DPLL_PSA1 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSA*)0xF0128204u)
+
+/** \brief 28228, DPLL ACTION Position/Value Action Request Register */
+#define GTM_DPLL_PSA10 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSA*)0xF0128228u)
+
+/** \brief 2822C, DPLL ACTION Position/Value Action Request Register */
+#define GTM_DPLL_PSA11 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSA*)0xF012822Cu)
+
+/** \brief 28230, DPLL ACTION Position/Value Action Request Register */
+#define GTM_DPLL_PSA12 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSA*)0xF0128230u)
+
+/** \brief 28234, DPLL ACTION Position/Value Action Request Register */
+#define GTM_DPLL_PSA13 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSA*)0xF0128234u)
+
+/** \brief 28238, DPLL ACTION Position/Value Action Request Register */
+#define GTM_DPLL_PSA14 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSA*)0xF0128238u)
+
+/** \brief 2823C, DPLL ACTION Position/Value Action Request Register */
+#define GTM_DPLL_PSA15 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSA*)0xF012823Cu)
+
+/** \brief 28240, DPLL ACTION Position/Value Action Request Register */
+#define GTM_DPLL_PSA16 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSA*)0xF0128240u)
+
+/** \brief 28244, DPLL ACTION Position/Value Action Request Register */
+#define GTM_DPLL_PSA17 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSA*)0xF0128244u)
+
+/** \brief 28248, DPLL ACTION Position/Value Action Request Register */
+#define GTM_DPLL_PSA18 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSA*)0xF0128248u)
+
+/** \brief 2824C, DPLL ACTION Position/Value Action Request Register */
+#define GTM_DPLL_PSA19 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSA*)0xF012824Cu)
+
+/** \brief 28208, DPLL ACTION Position/Value Action Request Register */
+#define GTM_DPLL_PSA2 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSA*)0xF0128208u)
+
+/** \brief 28250, DPLL ACTION Position/Value Action Request Register */
+#define GTM_DPLL_PSA20 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSA*)0xF0128250u)
+
+/** \brief 28254, DPLL ACTION Position/Value Action Request Register */
+#define GTM_DPLL_PSA21 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSA*)0xF0128254u)
+
+/** \brief 28258, DPLL ACTION Position/Value Action Request Register */
+#define GTM_DPLL_PSA22 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSA*)0xF0128258u)
+
+/** \brief 2825C, DPLL ACTION Position/Value Action Request Register */
+#define GTM_DPLL_PSA23 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSA*)0xF012825Cu)
+
+/** \brief 2820C, DPLL ACTION Position/Value Action Request Register */
+#define GTM_DPLL_PSA3 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSA*)0xF012820Cu)
+
+/** \brief 28210, DPLL ACTION Position/Value Action Request Register */
+#define GTM_DPLL_PSA4 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSA*)0xF0128210u)
+
+/** \brief 28214, DPLL ACTION Position/Value Action Request Register */
+#define GTM_DPLL_PSA5 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSA*)0xF0128214u)
+
+/** \brief 28218, DPLL ACTION Position/Value Action Request Register */
+#define GTM_DPLL_PSA6 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSA*)0xF0128218u)
+
+/** \brief 2821C, DPLL ACTION Position/Value Action Request Register */
+#define GTM_DPLL_PSA7 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSA*)0xF012821Cu)
+
+/** \brief 28220, DPLL ACTION Position/Value Action Request Register */
+#define GTM_DPLL_PSA8 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSA*)0xF0128220u)
+
+/** \brief 28224, DPLL ACTION Position/Value Action Request Register */
+#define GTM_DPLL_PSA9 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSA*)0xF0128224u)
+
+/** \brief 28E80, DPLL Calculated Position Value Register */
+#define GTM_DPLL_PSAC0 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSAC*)0xF0128E80u)
+
+/** \brief 28E84, DPLL Calculated Position Value Register */
+#define GTM_DPLL_PSAC1 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSAC*)0xF0128E84u)
+
+/** \brief 28EA8, DPLL Calculated Position Value Register */
+#define GTM_DPLL_PSAC10 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSAC*)0xF0128EA8u)
+
+/** \brief 28EAC, DPLL Calculated Position Value Register */
+#define GTM_DPLL_PSAC11 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSAC*)0xF0128EACu)
+
+/** \brief 28EB0, DPLL Calculated Position Value Register */
+#define GTM_DPLL_PSAC12 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSAC*)0xF0128EB0u)
+
+/** \brief 28EB4, DPLL Calculated Position Value Register */
+#define GTM_DPLL_PSAC13 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSAC*)0xF0128EB4u)
+
+/** \brief 28EB8, DPLL Calculated Position Value Register */
+#define GTM_DPLL_PSAC14 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSAC*)0xF0128EB8u)
+
+/** \brief 28EBC, DPLL Calculated Position Value Register */
+#define GTM_DPLL_PSAC15 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSAC*)0xF0128EBCu)
+
+/** \brief 28EC0, DPLL Calculated Position Value Register */
+#define GTM_DPLL_PSAC16 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSAC*)0xF0128EC0u)
+
+/** \brief 28EC4, DPLL Calculated Position Value Register */
+#define GTM_DPLL_PSAC17 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSAC*)0xF0128EC4u)
+
+/** \brief 28EC8, DPLL Calculated Position Value Register */
+#define GTM_DPLL_PSAC18 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSAC*)0xF0128EC8u)
+
+/** \brief 28ECC, DPLL Calculated Position Value Register */
+#define GTM_DPLL_PSAC19 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSAC*)0xF0128ECCu)
+
+/** \brief 28E88, DPLL Calculated Position Value Register */
+#define GTM_DPLL_PSAC2 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSAC*)0xF0128E88u)
+
+/** \brief 28ED0, DPLL Calculated Position Value Register */
+#define GTM_DPLL_PSAC20 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSAC*)0xF0128ED0u)
+
+/** \brief 28ED4, DPLL Calculated Position Value Register */
+#define GTM_DPLL_PSAC21 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSAC*)0xF0128ED4u)
+
+/** \brief 28ED8, DPLL Calculated Position Value Register */
+#define GTM_DPLL_PSAC22 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSAC*)0xF0128ED8u)
+
+/** \brief 28EDC, DPLL Calculated Position Value Register */
+#define GTM_DPLL_PSAC23 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSAC*)0xF0128EDCu)
+
+/** \brief 28E8C, DPLL Calculated Position Value Register */
+#define GTM_DPLL_PSAC3 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSAC*)0xF0128E8Cu)
+
+/** \brief 28E90, DPLL Calculated Position Value Register */
+#define GTM_DPLL_PSAC4 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSAC*)0xF0128E90u)
+
+/** \brief 28E94, DPLL Calculated Position Value Register */
+#define GTM_DPLL_PSAC5 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSAC*)0xF0128E94u)
+
+/** \brief 28E98, DPLL Calculated Position Value Register */
+#define GTM_DPLL_PSAC6 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSAC*)0xF0128E98u)
+
+/** \brief 28E9C, DPLL Calculated Position Value Register */
+#define GTM_DPLL_PSAC7 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSAC*)0xF0128E9Cu)
+
+/** \brief 28EA0, DPLL Calculated Position Value Register */
+#define GTM_DPLL_PSAC8 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSAC*)0xF0128EA0u)
+
+/** \brief 28EA4, DPLL Calculated Position Value Register */
+#define GTM_DPLL_PSAC9 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSAC*)0xF0128EA4u)
+
+/** \brief 285E4, DPLL Accurate Calculated Position Stamp of Last STATE Input */
+#define GTM_DPLL_PSSC /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSSC*)0xF01285E4u)
+
+/** \brief 285F0, DPLL Measured Position Stamp of Last STATE Input */
+#define GTM_DPLL_PSSM_0 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSSM_0*)0xF01285F0u)
+
+/** Alias (User Manual Name) for GTM_DPLL_PSSM_0.
+* To use register names with standard convension, please use GTM_DPLL_PSSM_0.
+*/
+#define GTM_DPLL_PSSM_OLD_1 (GTM_DPLL_PSSM_0)
+
+/** \brief 285F4, DPLL Measured Position Stamp of Last STATE Input */
+#define GTM_DPLL_PSSM_1 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSSM_1*)0xF01285F4u)
+
+/** Alias (User Manual Name) for GTM_DPLL_PSSM_1.
+* To use register names with standard convension, please use GTM_DPLL_PSSM_1.
+*/
+#define GTM_DPLL_PSSM_OLD_0 (GTM_DPLL_PSSM_1)
+
+/** \brief 285E0, DPLL Actual Calculated Position Stamp of Last TRIGGER Input */
+#define GTM_DPLL_PSTC /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSTC*)0xF01285E0u)
+
+/** \brief 285E8, DPLL Measured Position Stamp of Last TRIGGER Input */
+#define GTM_DPLL_PSTM_0 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSTM_0*)0xF01285E8u)
+
+/** Alias (User Manual Name) for GTM_DPLL_PSTM_0.
+* To use register names with standard convension, please use GTM_DPLL_PSTM_0.
+*/
+#define GTM_DPLL_PSTM_OLD_1 (GTM_DPLL_PSTM_0)
+
+/** \brief 285EC, DPLL Measured Position Stamp of Last TRIGGER Input */
+#define GTM_DPLL_PSTM_1 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PSTM_1*)0xF01285ECu)
+
+/** Alias (User Manual Name) for GTM_DPLL_PSTM_1.
+* To use register names with standard convension, please use GTM_DPLL_PSTM_1.
+*/
+#define GTM_DPLL_PSTM_OLD_0 (GTM_DPLL_PSTM_1)
+
+/** \brief 285D0, DPLL Plausibility Value of Next Active TRIGGER Slope */
+#define GTM_DPLL_PVT /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_PVT*)0xF01285D0u)
+
+/** \brief 281FC, DPLL RAM Initatlisation Register */
+#define GTM_DPLL_RAM_INI /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RAM_INI*)0xF01281FCu)
+
+/** \brief 28464, DPLL Reciprocal Value of Expected Increment Duration STATE */
+#define GTM_DPLL_RCDT_SX /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RCDT_SX*)0xF0128464u)
+
+/** \brief 2846C, DPLL Reciprocal Value of the Expected Nominal Increment
+ * Duration STATE */
+#define GTM_DPLL_RCDT_SX_NOM /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RCDT_SX_NOM*)0xF012846Cu)
+
+/** \brief 28460, DPLL Reciprocal Value of Expected Increment Duration TRIGGER */
+#define GTM_DPLL_RCDT_TX /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RCDT_TX*)0xF0128460u)
+
+/** \brief 28468, DPLL Reciprocal Value of the Expected Nominal Increment
+ * Duration TRIGGER */
+#define GTM_DPLL_RCDT_TX_NOM /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RCDT_TX_NOM*)0xF0128468u)
+
+/** \brief 28600, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S0 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF0128600u)
+
+/** \brief 28604, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S1 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF0128604u)
+
+/** \brief 28628, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S10 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF0128628u)
+
+/** \brief 2862C, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S11 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF012862Cu)
+
+/** \brief 28630, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S12 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF0128630u)
+
+/** \brief 28634, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S13 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF0128634u)
+
+/** \brief 28638, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S14 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF0128638u)
+
+/** \brief 2863C, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S15 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF012863Cu)
+
+/** \brief 28640, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S16 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF0128640u)
+
+/** \brief 28644, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S17 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF0128644u)
+
+/** \brief 28648, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S18 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF0128648u)
+
+/** \brief 2864C, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S19 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF012864Cu)
+
+/** \brief 28608, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S2 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF0128608u)
+
+/** \brief 28650, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S20 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF0128650u)
+
+/** \brief 28654, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S21 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF0128654u)
+
+/** \brief 28658, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S22 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF0128658u)
+
+/** \brief 2865C, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S23 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF012865Cu)
+
+/** \brief 28660, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S24 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF0128660u)
+
+/** \brief 28664, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S25 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF0128664u)
+
+/** \brief 28668, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S26 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF0128668u)
+
+/** \brief 2866C, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S27 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF012866Cu)
+
+/** \brief 28670, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S28 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF0128670u)
+
+/** \brief 28674, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S29 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF0128674u)
+
+/** \brief 2860C, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S3 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF012860Cu)
+
+/** \brief 28678, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S30 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF0128678u)
+
+/** \brief 2867C, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S31 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF012867Cu)
+
+/** \brief 28680, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S32 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF0128680u)
+
+/** \brief 28684, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S33 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF0128684u)
+
+/** \brief 28688, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S34 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF0128688u)
+
+/** \brief 2868C, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S35 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF012868Cu)
+
+/** \brief 28690, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S36 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF0128690u)
+
+/** \brief 28694, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S37 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF0128694u)
+
+/** \brief 28698, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S38 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF0128698u)
+
+/** \brief 2869C, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S39 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF012869Cu)
+
+/** \brief 28610, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S4 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF0128610u)
+
+/** \brief 286A0, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S40 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF01286A0u)
+
+/** \brief 286A4, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S41 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF01286A4u)
+
+/** \brief 286A8, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S42 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF01286A8u)
+
+/** \brief 286AC, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S43 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF01286ACu)
+
+/** \brief 286B0, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S44 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF01286B0u)
+
+/** \brief 286B4, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S45 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF01286B4u)
+
+/** \brief 286B8, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S46 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF01286B8u)
+
+/** \brief 286BC, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S47 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF01286BCu)
+
+/** \brief 286C0, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S48 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF01286C0u)
+
+/** \brief 286C4, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S49 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF01286C4u)
+
+/** \brief 28614, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S5 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF0128614u)
+
+/** \brief 286C8, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S50 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF01286C8u)
+
+/** \brief 286CC, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S51 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF01286CCu)
+
+/** \brief 286D0, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S52 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF01286D0u)
+
+/** \brief 286D4, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S53 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF01286D4u)
+
+/** \brief 286D8, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S54 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF01286D8u)
+
+/** \brief 286DC, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S55 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF01286DCu)
+
+/** \brief 286E0, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S56 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF01286E0u)
+
+/** \brief 286E4, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S57 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF01286E4u)
+
+/** \brief 286E8, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S58 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF01286E8u)
+
+/** \brief 286EC, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S59 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF01286ECu)
+
+/** \brief 28618, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S6 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF0128618u)
+
+/** \brief 286F0, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S60 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF01286F0u)
+
+/** \brief 286F4, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S61 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF01286F4u)
+
+/** \brief 286F8, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S62 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF01286F8u)
+
+/** \brief 286FC, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S63 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF01286FCu)
+
+/** \brief 2861C, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S7 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF012861Cu)
+
+/** \brief 28620, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S8 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF0128620u)
+
+/** \brief 28624, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+#define GTM_DPLL_RDT_S9 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S*)0xF0128624u)
+
+/** \brief 28474, DPLL Actual Reciprocal Value of STATE */
+#define GTM_DPLL_RDT_S_ACT /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_S_ACT*)0xF0128474u)
+
+/** \brief 28470, DPLL Actual Reciprocal Value of TRIGGER */
+#define GTM_DPLL_RDT_T_ACT /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_RDT_T_ACT*)0xF0128470u)
+
+/** \brief 284A4, DPLL STATE Locking Range */
+#define GTM_DPLL_SLR /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_SLR*)0xF01284A4u)
+
+/** \brief 280FC, DPLL Status Register */
+#define GTM_DPLL_STATUS /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_STATUS*)0xF01280FCu)
+
+/** \brief 280C4, DPLL TBU_TS0 Value at last STATE Event */
+#define GTM_DPLL_TBU_TS0_S /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TBU_TS0_S*)0xF01280C4u)
+
+/** \brief 280C0, DPLL TBU_TS0 Value at last TRIGGER Event */
+#define GTM_DPLL_TBU_TS0_T /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TBU_TS0_T*)0xF01280C0u)
+
+/** \brief 28424, DPLL TRIGGER Hold Time Max Value */
+#define GTM_DPLL_THMA /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_THMA*)0xF0128424u)
+
+/** \brief 28420, DPLL TRIGGER hold time min value */
+#define GTM_DPLL_THMI /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_THMI*)0xF0128420u)
+
+/** \brief 28428, DPLL Measured Last Pulse Time from Valid to Invalid TRIGGER
+ * Slope */
+#define GTM_DPLL_THVAL /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_THVAL*)0xF0128428u)
+
+/** \brief 284A0, DPLL TRIGGER locking range */
+#define GTM_DPLL_TLR /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TLR*)0xF01284A0u)
+
+/** \brief 28430, DPLL Time Out Value of active TRIGGER Slope */
+#define GTM_DPLL_TOV /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TOV*)0xF0128430u)
+
+/** \brief 28434, DPLL Time Out Value of active STATE Slope */
+#define GTM_DPLL_TOV_S /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TOV_S*)0xF0128434u)
+
+/** \brief 28410, DPLL Actual Signal STATE Time Stamp Register */
+#define GTM_DPLL_TS_S_0 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TS_S_0*)0xF0128410u)
+
+/** Alias (User Manual Name) for GTM_DPLL_TS_S_0.
+* To use register names with standard convension, please use GTM_DPLL_TS_S_0.
+*/
+#define GTM_DPLL_TS_S_OLD_0 (GTM_DPLL_TS_S_0)
+
+/** \brief 28414, DPLL Actual Signal STATE Time Stamp Register */
+#define GTM_DPLL_TS_S_1 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TS_S_1*)0xF0128414u)
+
+/** Alias (User Manual Name) for GTM_DPLL_TS_S_1.
+* To use register names with standard convension, please use GTM_DPLL_TS_S_1.
+*/
+#define GTM_DPLL_TS_S_OLD_1 (GTM_DPLL_TS_S_1)
+
+/** \brief 28400, DPLL Actual Signal TRIGGER Time Stamp Register */
+#define GTM_DPLL_TS_T_0 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TS_T_0*)0xF0128400u)
+
+/** Alias (User Manual Name) for GTM_DPLL_TS_T_0.
+* To use register names with standard convension, please use GTM_DPLL_TS_T_0.
+*/
+#define GTM_DPLL_TS_T_OLD_0 (GTM_DPLL_TS_T_0)
+
+/** \brief 28404, DPLL Actual Signal TRIGGER Time Stamp Register */
+#define GTM_DPLL_TS_T_1 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TS_T_1*)0xF0128404u)
+
+/** Alias (User Manual Name) for GTM_DPLL_TS_T_1.
+* To use register names with standard convension, please use GTM_DPLL_TS_T_1.
+*/
+#define GTM_DPLL_TS_T_OLD_1 (GTM_DPLL_TS_T_1)
+
+/** \brief 28E00, DPLL Calculate Time Stamp Register */
+#define GTM_DPLL_TSAC0 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSAC*)0xF0128E00u)
+
+/** \brief 28E04, DPLL Calculate Time Stamp Register */
+#define GTM_DPLL_TSAC1 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSAC*)0xF0128E04u)
+
+/** \brief 28E28, DPLL Calculate Time Stamp Register */
+#define GTM_DPLL_TSAC10 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSAC*)0xF0128E28u)
+
+/** \brief 28E2C, DPLL Calculate Time Stamp Register */
+#define GTM_DPLL_TSAC11 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSAC*)0xF0128E2Cu)
+
+/** \brief 28E30, DPLL Calculate Time Stamp Register */
+#define GTM_DPLL_TSAC12 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSAC*)0xF0128E30u)
+
+/** \brief 28E34, DPLL Calculate Time Stamp Register */
+#define GTM_DPLL_TSAC13 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSAC*)0xF0128E34u)
+
+/** \brief 28E38, DPLL Calculate Time Stamp Register */
+#define GTM_DPLL_TSAC14 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSAC*)0xF0128E38u)
+
+/** \brief 28E3C, DPLL Calculate Time Stamp Register */
+#define GTM_DPLL_TSAC15 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSAC*)0xF0128E3Cu)
+
+/** \brief 28E40, DPLL Calculate Time Stamp Register */
+#define GTM_DPLL_TSAC16 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSAC*)0xF0128E40u)
+
+/** \brief 28E44, DPLL Calculate Time Stamp Register */
+#define GTM_DPLL_TSAC17 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSAC*)0xF0128E44u)
+
+/** \brief 28E48, DPLL Calculate Time Stamp Register */
+#define GTM_DPLL_TSAC18 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSAC*)0xF0128E48u)
+
+/** \brief 28E4C, DPLL Calculate Time Stamp Register */
+#define GTM_DPLL_TSAC19 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSAC*)0xF0128E4Cu)
+
+/** \brief 28E08, DPLL Calculate Time Stamp Register */
+#define GTM_DPLL_TSAC2 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSAC*)0xF0128E08u)
+
+/** \brief 28E50, DPLL Calculate Time Stamp Register */
+#define GTM_DPLL_TSAC20 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSAC*)0xF0128E50u)
+
+/** \brief 28E54, DPLL Calculate Time Stamp Register */
+#define GTM_DPLL_TSAC21 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSAC*)0xF0128E54u)
+
+/** \brief 28E58, DPLL Calculate Time Stamp Register */
+#define GTM_DPLL_TSAC22 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSAC*)0xF0128E58u)
+
+/** \brief 28E5C, DPLL Calculate Time Stamp Register */
+#define GTM_DPLL_TSAC23 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSAC*)0xF0128E5Cu)
+
+/** \brief 28E0C, DPLL Calculate Time Stamp Register */
+#define GTM_DPLL_TSAC3 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSAC*)0xF0128E0Cu)
+
+/** \brief 28E10, DPLL Calculate Time Stamp Register */
+#define GTM_DPLL_TSAC4 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSAC*)0xF0128E10u)
+
+/** \brief 28E14, DPLL Calculate Time Stamp Register */
+#define GTM_DPLL_TSAC5 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSAC*)0xF0128E14u)
+
+/** \brief 28E18, DPLL Calculate Time Stamp Register */
+#define GTM_DPLL_TSAC6 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSAC*)0xF0128E18u)
+
+/** \brief 28E1C, DPLL Calculate Time Stamp Register */
+#define GTM_DPLL_TSAC7 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSAC*)0xF0128E1Cu)
+
+/** \brief 28E20, DPLL Calculate Time Stamp Register */
+#define GTM_DPLL_TSAC8 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSAC*)0xF0128E20u)
+
+/** \brief 28E24, DPLL Calculate Time Stamp Register */
+#define GTM_DPLL_TSAC9 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSAC*)0xF0128E24u)
+
+/** \brief 28700, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S0 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF0128700u)
+
+/** \brief 28704, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S1 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF0128704u)
+
+/** \brief 28728, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S10 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF0128728u)
+
+/** \brief 2872C, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S11 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF012872Cu)
+
+/** \brief 28730, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S12 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF0128730u)
+
+/** \brief 28734, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S13 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF0128734u)
+
+/** \brief 28738, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S14 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF0128738u)
+
+/** \brief 2873C, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S15 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF012873Cu)
+
+/** \brief 28740, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S16 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF0128740u)
+
+/** \brief 28744, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S17 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF0128744u)
+
+/** \brief 28748, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S18 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF0128748u)
+
+/** \brief 2874C, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S19 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF012874Cu)
+
+/** \brief 28708, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S2 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF0128708u)
+
+/** \brief 28750, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S20 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF0128750u)
+
+/** \brief 28754, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S21 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF0128754u)
+
+/** \brief 28758, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S22 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF0128758u)
+
+/** \brief 2875C, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S23 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF012875Cu)
+
+/** \brief 28760, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S24 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF0128760u)
+
+/** \brief 28764, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S25 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF0128764u)
+
+/** \brief 28768, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S26 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF0128768u)
+
+/** \brief 2876C, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S27 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF012876Cu)
+
+/** \brief 28770, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S28 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF0128770u)
+
+/** \brief 28774, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S29 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF0128774u)
+
+/** \brief 2870C, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S3 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF012870Cu)
+
+/** \brief 28778, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S30 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF0128778u)
+
+/** \brief 2877C, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S31 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF012877Cu)
+
+/** \brief 28780, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S32 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF0128780u)
+
+/** \brief 28784, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S33 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF0128784u)
+
+/** \brief 28788, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S34 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF0128788u)
+
+/** \brief 2878C, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S35 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF012878Cu)
+
+/** \brief 28790, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S36 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF0128790u)
+
+/** \brief 28794, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S37 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF0128794u)
+
+/** \brief 28798, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S38 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF0128798u)
+
+/** \brief 2879C, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S39 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF012879Cu)
+
+/** \brief 28710, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S4 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF0128710u)
+
+/** \brief 287A0, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S40 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF01287A0u)
+
+/** \brief 287A4, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S41 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF01287A4u)
+
+/** \brief 287A8, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S42 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF01287A8u)
+
+/** \brief 287AC, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S43 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF01287ACu)
+
+/** \brief 287B0, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S44 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF01287B0u)
+
+/** \brief 287B4, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S45 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF01287B4u)
+
+/** \brief 287B8, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S46 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF01287B8u)
+
+/** \brief 287BC, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S47 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF01287BCu)
+
+/** \brief 287C0, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S48 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF01287C0u)
+
+/** \brief 287C4, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S49 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF01287C4u)
+
+/** \brief 28714, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S5 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF0128714u)
+
+/** \brief 287C8, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S50 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF01287C8u)
+
+/** \brief 287CC, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S51 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF01287CCu)
+
+/** \brief 287D0, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S52 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF01287D0u)
+
+/** \brief 287D4, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S53 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF01287D4u)
+
+/** \brief 287D8, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S54 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF01287D8u)
+
+/** \brief 287DC, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S55 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF01287DCu)
+
+/** \brief 287E0, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S56 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF01287E0u)
+
+/** \brief 287E4, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S57 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF01287E4u)
+
+/** \brief 287E8, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S58 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF01287E8u)
+
+/** \brief 287EC, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S59 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF01287ECu)
+
+/** \brief 28718, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S6 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF0128718u)
+
+/** \brief 287F0, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S60 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF01287F0u)
+
+/** \brief 287F4, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S61 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF01287F4u)
+
+/** \brief 287F8, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S62 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF01287F8u)
+
+/** \brief 287FC, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S63 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF01287FCu)
+
+/** \brief 2871C, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S7 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF012871Cu)
+
+/** \brief 28720, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S8 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF0128720u)
+
+/** \brief 28724, DPLL Time Stamp Field of STATE Events */
+#define GTM_DPLL_TSF_S9 /*lint --e(923)*/ (*(volatile Ifx_GTM_DPLL_TSF_S*)0xF0128724u)
+
+/** \brief 9FE90, Data Exchange Input Control Register */
+#define GTM_DXINCON /*lint --e(923)*/ (*(volatile Ifx_GTM_DXINCON*)0xF019FE90u)
+
+/** \brief 9FE00, Data Exchange Output Control Register */
+#define GTM_DXOUTCON /*lint --e(923)*/ (*(volatile Ifx_GTM_DXOUTCON*)0xF019FE00u)
+
+/** \brief 20, GTM Error Interrupt Enable Register */
+#define GTM_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_EIRQ_EN*)0xF0100020u)
+
+/** \brief 18040, F2A0 Stream Activation Register */
+#define GTM_F2A0_ENABLE /*lint --e(923)*/ (*(volatile Ifx_GTM_F2A_ENABLE*)0xF0118040u)
+
+/** \brief 18000, F2A Read Channel Address Register */
+#define GTM_F2A0_RD_CH0_ARU_RD_FIFO /*lint --e(923)*/ (*(volatile Ifx_GTM_F2A_RD_CH_ARU_RD_FIFO*)0xF0118000u)
+
+/** Alias (User Manual Name) for GTM_F2A0_RD_CH0_ARU_RD_FIFO.
+* To use register names with standard convension, please use GTM_F2A0_RD_CH0_ARU_RD_FIFO.
+*/
+#define GTM_F2A0_CH0_ARU_RD_FIFO (GTM_F2A0_RD_CH0_ARU_RD_FIFO)
+
+/** \brief 18004, F2A Read Channel Address Register */
+#define GTM_F2A0_RD_CH1_ARU_RD_FIFO /*lint --e(923)*/ (*(volatile Ifx_GTM_F2A_RD_CH_ARU_RD_FIFO*)0xF0118004u)
+
+/** Alias (User Manual Name) for GTM_F2A0_RD_CH1_ARU_RD_FIFO.
+* To use register names with standard convension, please use GTM_F2A0_RD_CH1_ARU_RD_FIFO.
+*/
+#define GTM_F2A0_CH1_ARU_RD_FIFO (GTM_F2A0_RD_CH1_ARU_RD_FIFO)
+
+/** \brief 18008, F2A Read Channel Address Register */
+#define GTM_F2A0_RD_CH2_ARU_RD_FIFO /*lint --e(923)*/ (*(volatile Ifx_GTM_F2A_RD_CH_ARU_RD_FIFO*)0xF0118008u)
+
+/** Alias (User Manual Name) for GTM_F2A0_RD_CH2_ARU_RD_FIFO.
+* To use register names with standard convension, please use GTM_F2A0_RD_CH2_ARU_RD_FIFO.
+*/
+#define GTM_F2A0_CH2_ARU_RD_FIFO (GTM_F2A0_RD_CH2_ARU_RD_FIFO)
+
+/** \brief 1800C, F2A Read Channel Address Register */
+#define GTM_F2A0_RD_CH3_ARU_RD_FIFO /*lint --e(923)*/ (*(volatile Ifx_GTM_F2A_RD_CH_ARU_RD_FIFO*)0xF011800Cu)
+
+/** Alias (User Manual Name) for GTM_F2A0_RD_CH3_ARU_RD_FIFO.
+* To use register names with standard convension, please use GTM_F2A0_RD_CH3_ARU_RD_FIFO.
+*/
+#define GTM_F2A0_CH3_ARU_RD_FIFO (GTM_F2A0_RD_CH3_ARU_RD_FIFO)
+
+/** \brief 18010, F2A Read Channel Address Register */
+#define GTM_F2A0_RD_CH4_ARU_RD_FIFO /*lint --e(923)*/ (*(volatile Ifx_GTM_F2A_RD_CH_ARU_RD_FIFO*)0xF0118010u)
+
+/** Alias (User Manual Name) for GTM_F2A0_RD_CH4_ARU_RD_FIFO.
+* To use register names with standard convension, please use GTM_F2A0_RD_CH4_ARU_RD_FIFO.
+*/
+#define GTM_F2A0_CH4_ARU_RD_FIFO (GTM_F2A0_RD_CH4_ARU_RD_FIFO)
+
+/** \brief 18014, F2A Read Channel Address Register */
+#define GTM_F2A0_RD_CH5_ARU_RD_FIFO /*lint --e(923)*/ (*(volatile Ifx_GTM_F2A_RD_CH_ARU_RD_FIFO*)0xF0118014u)
+
+/** Alias (User Manual Name) for GTM_F2A0_RD_CH5_ARU_RD_FIFO.
+* To use register names with standard convension, please use GTM_F2A0_RD_CH5_ARU_RD_FIFO.
+*/
+#define GTM_F2A0_CH5_ARU_RD_FIFO (GTM_F2A0_RD_CH5_ARU_RD_FIFO)
+
+/** \brief 18018, F2A Read Channel Address Register */
+#define GTM_F2A0_RD_CH6_ARU_RD_FIFO /*lint --e(923)*/ (*(volatile Ifx_GTM_F2A_RD_CH_ARU_RD_FIFO*)0xF0118018u)
+
+/** Alias (User Manual Name) for GTM_F2A0_RD_CH6_ARU_RD_FIFO.
+* To use register names with standard convension, please use GTM_F2A0_RD_CH6_ARU_RD_FIFO.
+*/
+#define GTM_F2A0_CH6_ARU_RD_FIFO (GTM_F2A0_RD_CH6_ARU_RD_FIFO)
+
+/** \brief 1801C, F2A Read Channel Address Register */
+#define GTM_F2A0_RD_CH7_ARU_RD_FIFO /*lint --e(923)*/ (*(volatile Ifx_GTM_F2A_RD_CH_ARU_RD_FIFO*)0xF011801Cu)
+
+/** Alias (User Manual Name) for GTM_F2A0_RD_CH7_ARU_RD_FIFO.
+* To use register names with standard convension, please use GTM_F2A0_RD_CH7_ARU_RD_FIFO.
+*/
+#define GTM_F2A0_CH7_ARU_RD_FIFO (GTM_F2A0_RD_CH7_ARU_RD_FIFO)
+
+/** \brief 18020, F2A Stream Configuration Register */
+#define GTM_F2A0_STR_CH0_STR_CFG /*lint --e(923)*/ (*(volatile Ifx_GTM_F2A_STR_CH_STR_CFG*)0xF0118020u)
+
+/** Alias (User Manual Name) for GTM_F2A0_STR_CH0_STR_CFG.
+* To use register names with standard convension, please use GTM_F2A0_STR_CH0_STR_CFG.
+*/
+#define GTM_F2A0_CH0_STR_CFG (GTM_F2A0_STR_CH0_STR_CFG)
+
+/** \brief 18024, F2A Stream Configuration Register */
+#define GTM_F2A0_STR_CH1_STR_CFG /*lint --e(923)*/ (*(volatile Ifx_GTM_F2A_STR_CH_STR_CFG*)0xF0118024u)
+
+/** Alias (User Manual Name) for GTM_F2A0_STR_CH1_STR_CFG.
+* To use register names with standard convension, please use GTM_F2A0_STR_CH1_STR_CFG.
+*/
+#define GTM_F2A0_CH1_STR_CFG (GTM_F2A0_STR_CH1_STR_CFG)
+
+/** \brief 18028, F2A Stream Configuration Register */
+#define GTM_F2A0_STR_CH2_STR_CFG /*lint --e(923)*/ (*(volatile Ifx_GTM_F2A_STR_CH_STR_CFG*)0xF0118028u)
+
+/** Alias (User Manual Name) for GTM_F2A0_STR_CH2_STR_CFG.
+* To use register names with standard convension, please use GTM_F2A0_STR_CH2_STR_CFG.
+*/
+#define GTM_F2A0_CH2_STR_CFG (GTM_F2A0_STR_CH2_STR_CFG)
+
+/** \brief 1802C, F2A Stream Configuration Register */
+#define GTM_F2A0_STR_CH3_STR_CFG /*lint --e(923)*/ (*(volatile Ifx_GTM_F2A_STR_CH_STR_CFG*)0xF011802Cu)
+
+/** Alias (User Manual Name) for GTM_F2A0_STR_CH3_STR_CFG.
+* To use register names with standard convension, please use GTM_F2A0_STR_CH3_STR_CFG.
+*/
+#define GTM_F2A0_CH3_STR_CFG (GTM_F2A0_STR_CH3_STR_CFG)
+
+/** \brief 18030, F2A Stream Configuration Register */
+#define GTM_F2A0_STR_CH4_STR_CFG /*lint --e(923)*/ (*(volatile Ifx_GTM_F2A_STR_CH_STR_CFG*)0xF0118030u)
+
+/** Alias (User Manual Name) for GTM_F2A0_STR_CH4_STR_CFG.
+* To use register names with standard convension, please use GTM_F2A0_STR_CH4_STR_CFG.
+*/
+#define GTM_F2A0_CH4_STR_CFG (GTM_F2A0_STR_CH4_STR_CFG)
+
+/** \brief 18034, F2A Stream Configuration Register */
+#define GTM_F2A0_STR_CH5_STR_CFG /*lint --e(923)*/ (*(volatile Ifx_GTM_F2A_STR_CH_STR_CFG*)0xF0118034u)
+
+/** Alias (User Manual Name) for GTM_F2A0_STR_CH5_STR_CFG.
+* To use register names with standard convension, please use GTM_F2A0_STR_CH5_STR_CFG.
+*/
+#define GTM_F2A0_CH5_STR_CFG (GTM_F2A0_STR_CH5_STR_CFG)
+
+/** \brief 18038, F2A Stream Configuration Register */
+#define GTM_F2A0_STR_CH6_STR_CFG /*lint --e(923)*/ (*(volatile Ifx_GTM_F2A_STR_CH_STR_CFG*)0xF0118038u)
+
+/** Alias (User Manual Name) for GTM_F2A0_STR_CH6_STR_CFG.
+* To use register names with standard convension, please use GTM_F2A0_STR_CH6_STR_CFG.
+*/
+#define GTM_F2A0_CH6_STR_CFG (GTM_F2A0_STR_CH6_STR_CFG)
+
+/** \brief 1803C, F2A Stream Configuration Register */
+#define GTM_F2A0_STR_CH7_STR_CFG /*lint --e(923)*/ (*(volatile Ifx_GTM_F2A_STR_CH_STR_CFG*)0xF011803Cu)
+
+/** Alias (User Manual Name) for GTM_F2A0_STR_CH7_STR_CFG.
+* To use register names with standard convension, please use GTM_F2A0_STR_CH7_STR_CFG.
+*/
+#define GTM_F2A0_CH7_STR_CFG (GTM_F2A0_STR_CH7_STR_CFG)
+
+/** \brief 18400, FIFO0 Channel Control Register */
+#define GTM_FIFO0_CH0_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_CTRL*)0xF0118400u)
+
+/** \brief 18434, FIFO0 Channel Error Interrupt Enable Register */
+#define GTM_FIFO0_CH0_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_EIRQ_EN*)0xF0118434u)
+
+/** \brief 18404, FIFO0 Channel End Address Register */
+#define GTM_FIFO0_CH0_END_ADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_END_ADDR*)0xF0118404u)
+
+/** \brief 18418, FIFO0 Channel Fill Level Register */
+#define GTM_FIFO0_CH0_FILL_LEVEL /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_FILL_LEVEL*)0xF0118418u)
+
+/** \brief 18428, FIFO0 Channel Interrupt Enable Register */
+#define GTM_FIFO0_CH0_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_EN*)0xF0118428u)
+
+/** \brief 1842C, FIFO0 Channel Force Interrupt By Software Register */
+#define GTM_FIFO0_CH0_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_FORCINT*)0xF011842Cu)
+
+/** \brief 18430, FIFO0 Channel IRQ Mode Control Register */
+#define GTM_FIFO0_CH0_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_MODE*)0xF0118430u)
+
+/** \brief 18424, FIFO0 Channel Interrupt Notification Register */
+#define GTM_FIFO0_CH0_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_NOTIFY*)0xF0118424u)
+
+/** \brief 18410, FIFO0 Channel Lower Watermark Register */
+#define GTM_FIFO0_CH0_LOWER_WM /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_LOWER_WM*)0xF0118410u)
+
+/** \brief 18420, FIFO0 Channel Read Pointer Register */
+#define GTM_FIFO0_CH0_RD_PTR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_RD_PTR*)0xF0118420u)
+
+/** \brief 18408, FIFO0 Channel Start Address Register */
+#define GTM_FIFO0_CH0_START_ADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_START_ADDR*)0xF0118408u)
+
+/** \brief 18414, FIFO0 Channel Status Register */
+#define GTM_FIFO0_CH0_STATUS /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_STATUS*)0xF0118414u)
+
+/** \brief 1840C, FIFO0 Channel Upper Watermark Register */
+#define GTM_FIFO0_CH0_UPPER_WM /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_UPPER_WM*)0xF011840Cu)
+
+/** \brief 1841C, FIFO0 Channel Write Pointer Register */
+#define GTM_FIFO0_CH0_WR_PTR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_WR_PTR*)0xF011841Cu)
+
+/** \brief 18440, FIFO0 Channel Control Register */
+#define GTM_FIFO0_CH1_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_CTRL*)0xF0118440u)
+
+/** \brief 18474, FIFO0 Channel Error Interrupt Enable Register */
+#define GTM_FIFO0_CH1_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_EIRQ_EN*)0xF0118474u)
+
+/** \brief 18444, FIFO0 Channel End Address Register */
+#define GTM_FIFO0_CH1_END_ADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_END_ADDR*)0xF0118444u)
+
+/** \brief 18458, FIFO0 Channel Fill Level Register */
+#define GTM_FIFO0_CH1_FILL_LEVEL /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_FILL_LEVEL*)0xF0118458u)
+
+/** \brief 18468, FIFO0 Channel Interrupt Enable Register */
+#define GTM_FIFO0_CH1_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_EN*)0xF0118468u)
+
+/** \brief 1846C, FIFO0 Channel Force Interrupt By Software Register */
+#define GTM_FIFO0_CH1_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_FORCINT*)0xF011846Cu)
+
+/** \brief 18470, FIFO0 Channel IRQ Mode Control Register */
+#define GTM_FIFO0_CH1_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_MODE*)0xF0118470u)
+
+/** \brief 18464, FIFO0 Channel Interrupt Notification Register */
+#define GTM_FIFO0_CH1_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_NOTIFY*)0xF0118464u)
+
+/** \brief 18450, FIFO0 Channel Lower Watermark Register */
+#define GTM_FIFO0_CH1_LOWER_WM /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_LOWER_WM*)0xF0118450u)
+
+/** \brief 18460, FIFO0 Channel Read Pointer Register */
+#define GTM_FIFO0_CH1_RD_PTR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_RD_PTR*)0xF0118460u)
+
+/** \brief 18448, FIFO0 Channel Start Address Register */
+#define GTM_FIFO0_CH1_START_ADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_START_ADDR*)0xF0118448u)
+
+/** \brief 18454, FIFO0 Channel Status Register */
+#define GTM_FIFO0_CH1_STATUS /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_STATUS*)0xF0118454u)
+
+/** \brief 1844C, FIFO0 Channel Upper Watermark Register */
+#define GTM_FIFO0_CH1_UPPER_WM /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_UPPER_WM*)0xF011844Cu)
+
+/** \brief 1845C, FIFO0 Channel Write Pointer Register */
+#define GTM_FIFO0_CH1_WR_PTR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_WR_PTR*)0xF011845Cu)
+
+/** \brief 18480, FIFO0 Channel Control Register */
+#define GTM_FIFO0_CH2_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_CTRL*)0xF0118480u)
+
+/** \brief 184B4, FIFO0 Channel Error Interrupt Enable Register */
+#define GTM_FIFO0_CH2_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_EIRQ_EN*)0xF01184B4u)
+
+/** \brief 18484, FIFO0 Channel End Address Register */
+#define GTM_FIFO0_CH2_END_ADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_END_ADDR*)0xF0118484u)
+
+/** \brief 18498, FIFO0 Channel Fill Level Register */
+#define GTM_FIFO0_CH2_FILL_LEVEL /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_FILL_LEVEL*)0xF0118498u)
+
+/** \brief 184A8, FIFO0 Channel Interrupt Enable Register */
+#define GTM_FIFO0_CH2_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_EN*)0xF01184A8u)
+
+/** \brief 184AC, FIFO0 Channel Force Interrupt By Software Register */
+#define GTM_FIFO0_CH2_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_FORCINT*)0xF01184ACu)
+
+/** \brief 184B0, FIFO0 Channel IRQ Mode Control Register */
+#define GTM_FIFO0_CH2_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_MODE*)0xF01184B0u)
+
+/** \brief 184A4, FIFO0 Channel Interrupt Notification Register */
+#define GTM_FIFO0_CH2_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_NOTIFY*)0xF01184A4u)
+
+/** \brief 18490, FIFO0 Channel Lower Watermark Register */
+#define GTM_FIFO0_CH2_LOWER_WM /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_LOWER_WM*)0xF0118490u)
+
+/** \brief 184A0, FIFO0 Channel Read Pointer Register */
+#define GTM_FIFO0_CH2_RD_PTR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_RD_PTR*)0xF01184A0u)
+
+/** \brief 18488, FIFO0 Channel Start Address Register */
+#define GTM_FIFO0_CH2_START_ADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_START_ADDR*)0xF0118488u)
+
+/** \brief 18494, FIFO0 Channel Status Register */
+#define GTM_FIFO0_CH2_STATUS /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_STATUS*)0xF0118494u)
+
+/** \brief 1848C, FIFO0 Channel Upper Watermark Register */
+#define GTM_FIFO0_CH2_UPPER_WM /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_UPPER_WM*)0xF011848Cu)
+
+/** \brief 1849C, FIFO0 Channel Write Pointer Register */
+#define GTM_FIFO0_CH2_WR_PTR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_WR_PTR*)0xF011849Cu)
+
+/** \brief 184C0, FIFO0 Channel Control Register */
+#define GTM_FIFO0_CH3_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_CTRL*)0xF01184C0u)
+
+/** \brief 184F4, FIFO0 Channel Error Interrupt Enable Register */
+#define GTM_FIFO0_CH3_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_EIRQ_EN*)0xF01184F4u)
+
+/** \brief 184C4, FIFO0 Channel End Address Register */
+#define GTM_FIFO0_CH3_END_ADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_END_ADDR*)0xF01184C4u)
+
+/** \brief 184D8, FIFO0 Channel Fill Level Register */
+#define GTM_FIFO0_CH3_FILL_LEVEL /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_FILL_LEVEL*)0xF01184D8u)
+
+/** \brief 184E8, FIFO0 Channel Interrupt Enable Register */
+#define GTM_FIFO0_CH3_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_EN*)0xF01184E8u)
+
+/** \brief 184EC, FIFO0 Channel Force Interrupt By Software Register */
+#define GTM_FIFO0_CH3_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_FORCINT*)0xF01184ECu)
+
+/** \brief 184F0, FIFO0 Channel IRQ Mode Control Register */
+#define GTM_FIFO0_CH3_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_MODE*)0xF01184F0u)
+
+/** \brief 184E4, FIFO0 Channel Interrupt Notification Register */
+#define GTM_FIFO0_CH3_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_NOTIFY*)0xF01184E4u)
+
+/** \brief 184D0, FIFO0 Channel Lower Watermark Register */
+#define GTM_FIFO0_CH3_LOWER_WM /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_LOWER_WM*)0xF01184D0u)
+
+/** \brief 184E0, FIFO0 Channel Read Pointer Register */
+#define GTM_FIFO0_CH3_RD_PTR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_RD_PTR*)0xF01184E0u)
+
+/** \brief 184C8, FIFO0 Channel Start Address Register */
+#define GTM_FIFO0_CH3_START_ADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_START_ADDR*)0xF01184C8u)
+
+/** \brief 184D4, FIFO0 Channel Status Register */
+#define GTM_FIFO0_CH3_STATUS /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_STATUS*)0xF01184D4u)
+
+/** \brief 184CC, FIFO0 Channel Upper Watermark Register */
+#define GTM_FIFO0_CH3_UPPER_WM /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_UPPER_WM*)0xF01184CCu)
+
+/** \brief 184DC, FIFO0 Channel Write Pointer Register */
+#define GTM_FIFO0_CH3_WR_PTR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_WR_PTR*)0xF01184DCu)
+
+/** \brief 18500, FIFO0 Channel Control Register */
+#define GTM_FIFO0_CH4_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_CTRL*)0xF0118500u)
+
+/** \brief 18534, FIFO0 Channel Error Interrupt Enable Register */
+#define GTM_FIFO0_CH4_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_EIRQ_EN*)0xF0118534u)
+
+/** \brief 18504, FIFO0 Channel End Address Register */
+#define GTM_FIFO0_CH4_END_ADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_END_ADDR*)0xF0118504u)
+
+/** \brief 18518, FIFO0 Channel Fill Level Register */
+#define GTM_FIFO0_CH4_FILL_LEVEL /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_FILL_LEVEL*)0xF0118518u)
+
+/** \brief 18528, FIFO0 Channel Interrupt Enable Register */
+#define GTM_FIFO0_CH4_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_EN*)0xF0118528u)
+
+/** \brief 1852C, FIFO0 Channel Force Interrupt By Software Register */
+#define GTM_FIFO0_CH4_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_FORCINT*)0xF011852Cu)
+
+/** \brief 18530, FIFO0 Channel IRQ Mode Control Register */
+#define GTM_FIFO0_CH4_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_MODE*)0xF0118530u)
+
+/** \brief 18524, FIFO0 Channel Interrupt Notification Register */
+#define GTM_FIFO0_CH4_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_NOTIFY*)0xF0118524u)
+
+/** \brief 18510, FIFO0 Channel Lower Watermark Register */
+#define GTM_FIFO0_CH4_LOWER_WM /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_LOWER_WM*)0xF0118510u)
+
+/** \brief 18520, FIFO0 Channel Read Pointer Register */
+#define GTM_FIFO0_CH4_RD_PTR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_RD_PTR*)0xF0118520u)
+
+/** \brief 18508, FIFO0 Channel Start Address Register */
+#define GTM_FIFO0_CH4_START_ADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_START_ADDR*)0xF0118508u)
+
+/** \brief 18514, FIFO0 Channel Status Register */
+#define GTM_FIFO0_CH4_STATUS /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_STATUS*)0xF0118514u)
+
+/** \brief 1850C, FIFO0 Channel Upper Watermark Register */
+#define GTM_FIFO0_CH4_UPPER_WM /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_UPPER_WM*)0xF011850Cu)
+
+/** \brief 1851C, FIFO0 Channel Write Pointer Register */
+#define GTM_FIFO0_CH4_WR_PTR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_WR_PTR*)0xF011851Cu)
+
+/** \brief 18540, FIFO0 Channel Control Register */
+#define GTM_FIFO0_CH5_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_CTRL*)0xF0118540u)
+
+/** \brief 18574, FIFO0 Channel Error Interrupt Enable Register */
+#define GTM_FIFO0_CH5_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_EIRQ_EN*)0xF0118574u)
+
+/** \brief 18544, FIFO0 Channel End Address Register */
+#define GTM_FIFO0_CH5_END_ADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_END_ADDR*)0xF0118544u)
+
+/** \brief 18558, FIFO0 Channel Fill Level Register */
+#define GTM_FIFO0_CH5_FILL_LEVEL /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_FILL_LEVEL*)0xF0118558u)
+
+/** \brief 18568, FIFO0 Channel Interrupt Enable Register */
+#define GTM_FIFO0_CH5_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_EN*)0xF0118568u)
+
+/** \brief 1856C, FIFO0 Channel Force Interrupt By Software Register */
+#define GTM_FIFO0_CH5_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_FORCINT*)0xF011856Cu)
+
+/** \brief 18570, FIFO0 Channel IRQ Mode Control Register */
+#define GTM_FIFO0_CH5_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_MODE*)0xF0118570u)
+
+/** \brief 18564, FIFO0 Channel Interrupt Notification Register */
+#define GTM_FIFO0_CH5_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_NOTIFY*)0xF0118564u)
+
+/** \brief 18550, FIFO0 Channel Lower Watermark Register */
+#define GTM_FIFO0_CH5_LOWER_WM /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_LOWER_WM*)0xF0118550u)
+
+/** \brief 18560, FIFO0 Channel Read Pointer Register */
+#define GTM_FIFO0_CH5_RD_PTR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_RD_PTR*)0xF0118560u)
+
+/** \brief 18548, FIFO0 Channel Start Address Register */
+#define GTM_FIFO0_CH5_START_ADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_START_ADDR*)0xF0118548u)
+
+/** \brief 18554, FIFO0 Channel Status Register */
+#define GTM_FIFO0_CH5_STATUS /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_STATUS*)0xF0118554u)
+
+/** \brief 1854C, FIFO0 Channel Upper Watermark Register */
+#define GTM_FIFO0_CH5_UPPER_WM /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_UPPER_WM*)0xF011854Cu)
+
+/** \brief 1855C, FIFO0 Channel Write Pointer Register */
+#define GTM_FIFO0_CH5_WR_PTR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_WR_PTR*)0xF011855Cu)
+
+/** \brief 18580, FIFO0 Channel Control Register */
+#define GTM_FIFO0_CH6_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_CTRL*)0xF0118580u)
+
+/** \brief 185B4, FIFO0 Channel Error Interrupt Enable Register */
+#define GTM_FIFO0_CH6_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_EIRQ_EN*)0xF01185B4u)
+
+/** \brief 18584, FIFO0 Channel End Address Register */
+#define GTM_FIFO0_CH6_END_ADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_END_ADDR*)0xF0118584u)
+
+/** \brief 18598, FIFO0 Channel Fill Level Register */
+#define GTM_FIFO0_CH6_FILL_LEVEL /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_FILL_LEVEL*)0xF0118598u)
+
+/** \brief 185A8, FIFO0 Channel Interrupt Enable Register */
+#define GTM_FIFO0_CH6_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_EN*)0xF01185A8u)
+
+/** \brief 185AC, FIFO0 Channel Force Interrupt By Software Register */
+#define GTM_FIFO0_CH6_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_FORCINT*)0xF01185ACu)
+
+/** \brief 185B0, FIFO0 Channel IRQ Mode Control Register */
+#define GTM_FIFO0_CH6_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_MODE*)0xF01185B0u)
+
+/** \brief 185A4, FIFO0 Channel Interrupt Notification Register */
+#define GTM_FIFO0_CH6_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_NOTIFY*)0xF01185A4u)
+
+/** \brief 18590, FIFO0 Channel Lower Watermark Register */
+#define GTM_FIFO0_CH6_LOWER_WM /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_LOWER_WM*)0xF0118590u)
+
+/** \brief 185A0, FIFO0 Channel Read Pointer Register */
+#define GTM_FIFO0_CH6_RD_PTR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_RD_PTR*)0xF01185A0u)
+
+/** \brief 18588, FIFO0 Channel Start Address Register */
+#define GTM_FIFO0_CH6_START_ADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_START_ADDR*)0xF0118588u)
+
+/** \brief 18594, FIFO0 Channel Status Register */
+#define GTM_FIFO0_CH6_STATUS /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_STATUS*)0xF0118594u)
+
+/** \brief 1858C, FIFO0 Channel Upper Watermark Register */
+#define GTM_FIFO0_CH6_UPPER_WM /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_UPPER_WM*)0xF011858Cu)
+
+/** \brief 1859C, FIFO0 Channel Write Pointer Register */
+#define GTM_FIFO0_CH6_WR_PTR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_WR_PTR*)0xF011859Cu)
+
+/** \brief 185C0, FIFO0 Channel Control Register */
+#define GTM_FIFO0_CH7_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_CTRL*)0xF01185C0u)
+
+/** \brief 185F4, FIFO0 Channel Error Interrupt Enable Register */
+#define GTM_FIFO0_CH7_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_EIRQ_EN*)0xF01185F4u)
+
+/** \brief 185C4, FIFO0 Channel End Address Register */
+#define GTM_FIFO0_CH7_END_ADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_END_ADDR*)0xF01185C4u)
+
+/** \brief 185D8, FIFO0 Channel Fill Level Register */
+#define GTM_FIFO0_CH7_FILL_LEVEL /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_FILL_LEVEL*)0xF01185D8u)
+
+/** \brief 185E8, FIFO0 Channel Interrupt Enable Register */
+#define GTM_FIFO0_CH7_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_EN*)0xF01185E8u)
+
+/** \brief 185EC, FIFO0 Channel Force Interrupt By Software Register */
+#define GTM_FIFO0_CH7_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_FORCINT*)0xF01185ECu)
+
+/** \brief 185F0, FIFO0 Channel IRQ Mode Control Register */
+#define GTM_FIFO0_CH7_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_MODE*)0xF01185F0u)
+
+/** \brief 185E4, FIFO0 Channel Interrupt Notification Register */
+#define GTM_FIFO0_CH7_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_IRQ_NOTIFY*)0xF01185E4u)
+
+/** \brief 185D0, FIFO0 Channel Lower Watermark Register */
+#define GTM_FIFO0_CH7_LOWER_WM /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_LOWER_WM*)0xF01185D0u)
+
+/** \brief 185E0, FIFO0 Channel Read Pointer Register */
+#define GTM_FIFO0_CH7_RD_PTR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_RD_PTR*)0xF01185E0u)
+
+/** \brief 185C8, FIFO0 Channel Start Address Register */
+#define GTM_FIFO0_CH7_START_ADDR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_START_ADDR*)0xF01185C8u)
+
+/** \brief 185D4, FIFO0 Channel Status Register */
+#define GTM_FIFO0_CH7_STATUS /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_STATUS*)0xF01185D4u)
+
+/** \brief 185CC, FIFO0 Channel Upper Watermark Register */
+#define GTM_FIFO0_CH7_UPPER_WM /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_UPPER_WM*)0xF01185CCu)
+
+/** \brief 185DC, FIFO0 Channel Write Pointer Register */
+#define GTM_FIFO0_CH7_WR_PTR /*lint --e(923)*/ (*(volatile Ifx_GTM_FIFO_CH_WR_PTR*)0xF01185DCu)
+
+/** \brief 600, GTM Infrastructure Interrupt Group */
+#define GTM_ICM_IRQG_0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ICM_IRQG_0*)0xF0100600u)
+
+/** \brief 604, GTM DPLL Interrupt Group */
+#define GTM_ICM_IRQG_1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ICM_IRQG_1*)0xF0100604u)
+
+/** \brief 608, TIM Interrupt Group 0 */
+#define GTM_ICM_IRQG_2 /*lint --e(923)*/ (*(volatile Ifx_GTM_ICM_IRQG_2*)0xF0100608u)
+
+/** \brief 610, MCS Interrupt Group 0 */
+#define GTM_ICM_IRQG_4 /*lint --e(923)*/ (*(volatile Ifx_GTM_ICM_IRQG_4*)0xF0100610u)
+
+/** \brief 618, TOM Interrupt Group 0 */
+#define GTM_ICM_IRQG_6 /*lint --e(923)*/ (*(volatile Ifx_GTM_ICM_IRQG_6*)0xF0100618u)
+
+/** \brief 624, ATOM Interrupt Group 0 */
+#define GTM_ICM_IRQG_9 /*lint --e(923)*/ (*(volatile Ifx_GTM_ICM_IRQG_9*)0xF0100624u)
+
+/** \brief 634, ICM Channel Error Interrupt 0 Register */
+#define GTM_ICM_IRQG_CEI0 /*lint --e(923)*/ (*(volatile Ifx_GTM_ICM_IRQG_CEI0*)0xF0100634u)
+
+/** \brief 638, ICM Channel Error Interrupt 1 Register */
+#define GTM_ICM_IRQG_CEI1 /*lint --e(923)*/ (*(volatile Ifx_GTM_ICM_IRQG_CEI1*)0xF0100638u)
+
+/** \brief 640, ICM Channel Error Interrupt 3 Register */
+#define GTM_ICM_IRQG_CEI3 /*lint --e(923)*/ (*(volatile Ifx_GTM_ICM_IRQG_CEI3*)0xF0100640u)
+
+/** \brief 630, ICM Module Error Interrupt Register */
+#define GTM_ICM_IRQG_MEI /*lint --e(923)*/ (*(volatile Ifx_GTM_ICM_IRQG_MEI*)0xF0100630u)
+
+/** \brief 9FDA0, CAN Output Select Register */
+#define GTM_INOUTSEL_CAN_OUTSEL /*lint --e(923)*/ (*(volatile Ifx_GTM_INOUTSEL_CAN_OUTSEL*)0xF019FDA0u)
+
+/** Alias (User Manual Name) for GTM_INOUTSEL_CAN_OUTSEL.
+* To use register names with standard convension, please use GTM_INOUTSEL_CAN_OUTSEL.
+*/
+#define GTM_CANOUTSEL (GTM_INOUTSEL_CAN_OUTSEL)
+
+/** \brief 9FD7C, DSADC Input Select Register */
+#define GTM_INOUTSEL_DSADC_INSEL0 /*lint --e(923)*/ (*(volatile Ifx_GTM_INOUTSEL_DSADC_INSEL*)0xF019FD7Cu)
+
+/** Alias (User Manual Name) for GTM_INOUTSEL_DSADC_INSEL0.
+* To use register names with standard convension, please use GTM_INOUTSEL_DSADC_INSEL0.
+*/
+#define GTM_DSADCINSEL0 (GTM_INOUTSEL_DSADC_INSEL0)
+
+/** \brief 9FD80, DSADC Input Select Register */
+#define GTM_INOUTSEL_DSADC_INSEL1 /*lint --e(923)*/ (*(volatile Ifx_GTM_INOUTSEL_DSADC_INSEL*)0xF019FD80u)
+
+/** Alias (User Manual Name) for GTM_INOUTSEL_DSADC_INSEL1.
+* To use register names with standard convension, please use GTM_INOUTSEL_DSADC_INSEL1.
+*/
+#define GTM_DSADCINSEL1 (GTM_INOUTSEL_DSADC_INSEL1)
+
+/** \brief 9FD84, DSADC Input Select Register */
+#define GTM_INOUTSEL_DSADC_INSEL2 /*lint --e(923)*/ (*(volatile Ifx_GTM_INOUTSEL_DSADC_INSEL*)0xF019FD84u)
+
+/** Alias (User Manual Name) for GTM_INOUTSEL_DSADC_INSEL2.
+* To use register names with standard convension, please use GTM_INOUTSEL_DSADC_INSEL2.
+*/
+#define GTM_DSADCINSEL2 (GTM_INOUTSEL_DSADC_INSEL2)
+
+/** \brief 9FD88, DSADC Output Select 00 Register */
+#define GTM_INOUTSEL_DSADC_OUTSEL00 /*lint --e(923)*/ (*(volatile Ifx_GTM_INOUTSEL_DSADC_OUTSEL*)0xF019FD88u)
+
+/** Alias (User Manual Name) for GTM_INOUTSEL_DSADC_OUTSEL00.
+* To use register names with standard convension, please use GTM_INOUTSEL_DSADC_OUTSEL00.
+*/
+#define GTM_DSADCOUTSEL00 (GTM_INOUTSEL_DSADC_OUTSEL00)
+
+/** \brief 9FD90, DSADC Output Select 10 Register */
+#define GTM_INOUTSEL_DSADC_OUTSEL10 /*lint --e(923)*/ (*(volatile Ifx_GTM_INOUTSEL_DSADC_OUTSEL*)0xF019FD90u)
+
+/** Alias (User Manual Name) for GTM_INOUTSEL_DSADC_OUTSEL10.
+* To use register names with standard convension, please use GTM_INOUTSEL_DSADC_OUTSEL10.
+*/
+#define GTM_DSADCOUTSEL10 (GTM_INOUTSEL_DSADC_OUTSEL10)
+
+/** \brief 9FDA4, PSI5 Output Select 0 Register */
+#define GTM_INOUTSEL_PSI5_OUTSEL0 /*lint --e(923)*/ (*(volatile Ifx_GTM_INOUTSEL_PSI5_OUTSEL0*)0xF019FDA4u)
+
+/** Alias (User Manual Name) for GTM_INOUTSEL_PSI5_OUTSEL0.
+* To use register names with standard convension, please use GTM_INOUTSEL_PSI5_OUTSEL0.
+*/
+#define GTM_PSI5OUTSEL0 (GTM_INOUTSEL_PSI5_OUTSEL0)
+
+/** \brief 9FDA8, PSI5-S Output Select Register */
+#define GTM_INOUTSEL_PSI5S_OUTSEL /*lint --e(923)*/ (*(volatile Ifx_GTM_INOUTSEL_PSI5S_OUTSEL*)0xF019FDA8u)
+
+/** Alias (User Manual Name) for GTM_INOUTSEL_PSI5S_OUTSEL.
+* To use register names with standard convension, please use GTM_INOUTSEL_PSI5S_OUTSEL.
+*/
+#define GTM_PSI5SOUTSEL (GTM_INOUTSEL_PSI5S_OUTSEL)
+
+/** \brief 9FD30, Timer Output Select Register */
+#define GTM_INOUTSEL_T_OUTSEL0 /*lint --e(923)*/ (*(volatile Ifx_GTM_INOUTSEL_T_OUTSEL*)0xF019FD30u)
+
+/** Alias (User Manual Name) for GTM_INOUTSEL_T_OUTSEL0.
+* To use register names with standard convension, please use GTM_INOUTSEL_T_OUTSEL0.
+*/
+#define GTM_TOUTSEL0 (GTM_INOUTSEL_T_OUTSEL0)
+
+/** \brief 9FD34, Timer Output Select Register */
+#define GTM_INOUTSEL_T_OUTSEL1 /*lint --e(923)*/ (*(volatile Ifx_GTM_INOUTSEL_T_OUTSEL*)0xF019FD34u)
+
+/** Alias (User Manual Name) for GTM_INOUTSEL_T_OUTSEL1.
+* To use register names with standard convension, please use GTM_INOUTSEL_T_OUTSEL1.
+*/
+#define GTM_TOUTSEL1 (GTM_INOUTSEL_T_OUTSEL1)
+
+/** \brief 9FD38, Timer Output Select Register */
+#define GTM_INOUTSEL_T_OUTSEL2 /*lint --e(923)*/ (*(volatile Ifx_GTM_INOUTSEL_T_OUTSEL*)0xF019FD38u)
+
+/** Alias (User Manual Name) for GTM_INOUTSEL_T_OUTSEL2.
+* To use register names with standard convension, please use GTM_INOUTSEL_T_OUTSEL2.
+*/
+#define GTM_TOUTSEL2 (GTM_INOUTSEL_T_OUTSEL2)
+
+/** \brief 9FD3C, Timer Output Select Register */
+#define GTM_INOUTSEL_T_OUTSEL3 /*lint --e(923)*/ (*(volatile Ifx_GTM_INOUTSEL_T_OUTSEL*)0xF019FD3Cu)
+
+/** Alias (User Manual Name) for GTM_INOUTSEL_T_OUTSEL3.
+* To use register names with standard convension, please use GTM_INOUTSEL_T_OUTSEL3.
+*/
+#define GTM_TOUTSEL3 (GTM_INOUTSEL_T_OUTSEL3)
+
+/** \brief 9FD40, Timer Output Select Register */
+#define GTM_INOUTSEL_T_OUTSEL4 /*lint --e(923)*/ (*(volatile Ifx_GTM_INOUTSEL_T_OUTSEL*)0xF019FD40u)
+
+/** Alias (User Manual Name) for GTM_INOUTSEL_T_OUTSEL4.
+* To use register names with standard convension, please use GTM_INOUTSEL_T_OUTSEL4.
+*/
+#define GTM_TOUTSEL4 (GTM_INOUTSEL_T_OUTSEL4)
+
+/** \brief 9FD44, Timer Output Select Register */
+#define GTM_INOUTSEL_T_OUTSEL5 /*lint --e(923)*/ (*(volatile Ifx_GTM_INOUTSEL_T_OUTSEL*)0xF019FD44u)
+
+/** Alias (User Manual Name) for GTM_INOUTSEL_T_OUTSEL5.
+* To use register names with standard convension, please use GTM_INOUTSEL_T_OUTSEL5.
+*/
+#define GTM_TOUTSEL5 (GTM_INOUTSEL_T_OUTSEL5)
+
+/** \brief 9FD48, Timer Output Select Register */
+#define GTM_INOUTSEL_T_OUTSEL6 /*lint --e(923)*/ (*(volatile Ifx_GTM_INOUTSEL_T_OUTSEL*)0xF019FD48u)
+
+/** Alias (User Manual Name) for GTM_INOUTSEL_T_OUTSEL6.
+* To use register names with standard convension, please use GTM_INOUTSEL_T_OUTSEL6.
+*/
+#define GTM_TOUTSEL6 (GTM_INOUTSEL_T_OUTSEL6)
+
+/** \brief 9FD4C, Timer Output Select Register */
+#define GTM_INOUTSEL_T_OUTSEL7 /*lint --e(923)*/ (*(volatile Ifx_GTM_INOUTSEL_T_OUTSEL*)0xF019FD4Cu)
+
+/** Alias (User Manual Name) for GTM_INOUTSEL_T_OUTSEL7.
+* To use register names with standard convension, please use GTM_INOUTSEL_T_OUTSEL7.
+*/
+#define GTM_TOUTSEL7 (GTM_INOUTSEL_T_OUTSEL7)
+
+/** \brief 9FD50, Timer Output Select Register */
+#define GTM_INOUTSEL_T_OUTSEL8 /*lint --e(923)*/ (*(volatile Ifx_GTM_INOUTSEL_T_OUTSEL*)0xF019FD50u)
+
+/** Alias (User Manual Name) for GTM_INOUTSEL_T_OUTSEL8.
+* To use register names with standard convension, please use GTM_INOUTSEL_T_OUTSEL8.
+*/
+#define GTM_TOUTSEL8 (GTM_INOUTSEL_T_OUTSEL8)
+
+/** \brief 9FD54, Timer Output Select Register */
+#define GTM_INOUTSEL_T_OUTSEL9 /*lint --e(923)*/ (*(volatile Ifx_GTM_INOUTSEL_T_OUTSEL*)0xF019FD54u)
+
+/** Alias (User Manual Name) for GTM_INOUTSEL_T_OUTSEL9.
+* To use register names with standard convension, please use GTM_INOUTSEL_T_OUTSEL9.
+*/
+#define GTM_TOUTSEL9 (GTM_INOUTSEL_T_OUTSEL9)
+
+/** \brief 9FD10, TIM Input Select Register */
+#define GTM_INOUTSEL_TIM0_INSEL /*lint --e(923)*/ (*(volatile Ifx_GTM_INOUTSEL_TIM_INSEL*)0xF019FD10u)
+
+/** Alias (User Manual Name) for GTM_INOUTSEL_TIM0_INSEL.
+* To use register names with standard convension, please use GTM_INOUTSEL_TIM0_INSEL.
+*/
+#define GTM_TIM0INSEL (GTM_INOUTSEL_TIM0_INSEL)
+
+/** \brief 9FD14, TIM Input Select Register */
+#define GTM_INOUTSEL_TIM1_INSEL /*lint --e(923)*/ (*(volatile Ifx_GTM_INOUTSEL_TIM_INSEL*)0xF019FD14u)
+
+/** Alias (User Manual Name) for GTM_INOUTSEL_TIM1_INSEL.
+* To use register names with standard convension, please use GTM_INOUTSEL_TIM1_INSEL.
+*/
+#define GTM_TIM1INSEL (GTM_INOUTSEL_TIM1_INSEL)
+
+/** \brief 9FD18, TIM Input Select Register */
+#define GTM_INOUTSEL_TIM2_INSEL /*lint --e(923)*/ (*(volatile Ifx_GTM_INOUTSEL_TIM_INSEL*)0xF019FD18u)
+
+/** Alias (User Manual Name) for GTM_INOUTSEL_TIM2_INSEL.
+* To use register names with standard convension, please use GTM_INOUTSEL_TIM2_INSEL.
+*/
+#define GTM_TIM2INSEL (GTM_INOUTSEL_TIM2_INSEL)
+
+/** \brief 14, GTM Interrupt Enable Register */
+#define GTM_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_IRQ_EN*)0xF0100014u)
+
+/** \brief 18, GTM Software Interrupt Generation Register */
+#define GTM_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_IRQ_FORCINT*)0xF0100018u)
+
+/** \brief 1C, GTM Top Level Interrupts Mode Selection */
+#define GTM_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_IRQ_MODE*)0xF010001Cu)
+
+/** \brief 10, GTM Interrupt Notification Register */
+#define GTM_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_IRQ_NOTIFY*)0xF0100010u)
+
+/** \brief 9FDF4, Kernel Reset Register 0 */
+#define GTM_KRST0 /*lint --e(923)*/ (*(volatile Ifx_GTM_KRST0*)0xF019FDF4u)
+
+/** \brief 9FDF0, Kernel Reset Register 1 */
+#define GTM_KRST1 /*lint --e(923)*/ (*(volatile Ifx_GTM_KRST1*)0xF019FDF0u)
+
+/** \brief 9FDEC, Kernel Reset Status Clear Register */
+#define GTM_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_GTM_KRSTCLR*)0xF019FDECu)
+
+/** \brief F00, MAP Control Register */
+#define GTM_MAP_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_MAP_CTRL*)0xF0100F00u)
+
+/** \brief F40, Memory Layout Configuration Register */
+#define GTM_MCFG_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_MCFG_CTRL*)0xF0100F40u)
+
+/** \brief 30024, MCS Channel ACB Register */
+#define GTM_MCS0_CH0_ACB /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_ACB*)0xF0130024u)
+
+/** \brief 30028, MCS Clear Trigger Control Register */
+#define GTM_MCS0_CH0_CTRG /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH0_CTRG*)0xF0130028u)
+
+/** Alias (User Manual Name) for GTM_MCS0_CH0_CTRG.
+* To use register names with standard convension, please use GTM_MCS0_CH0_CTRG.
+*/
+#define GTM_MCS0_CTRG (GTM_MCS0_CH0_CTRG)
+
+/** \brief 30020, MCS Channel Control Register */
+#define GTM_MCS0_CH0_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_CTRL*)0xF0130020u)
+
+/** \brief 30054, MCS_Channel Error Interrupt Enable Register */
+#define GTM_MCS0_CH0_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_EIRQ_EN*)0xF0130054u)
+
+/** \brief 30048, MCS Channel Interrupt Enable Register */
+#define GTM_MCS0_CH0_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_EN*)0xF0130048u)
+
+/** \brief 3004C, MCS Channel Software Interrupt Generation Register */
+#define GTM_MCS0_CH0_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_FORCINT*)0xF013004Cu)
+
+/** \brief 30050, MCS IRQ Mode Configuration Register */
+#define GTM_MCS0_CH0_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_MODE*)0xF0130050u)
+
+/** \brief 30044, MCS Channel interrupt notification register */
+#define GTM_MCS0_CH0_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_NOTIFY*)0xF0130044u)
+
+/** \brief 30040, MCS Channel Program Counter Register */
+#define GTM_MCS0_CH0_PC /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_PC*)0xF0130040u)
+
+/** \brief 30000, MCS Channel Program Counter Register 0 */
+#define GTM_MCS0_CH0_R0 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R0*)0xF0130000u)
+
+/** \brief 30004, MCS Channel Program Counter Register 1 */
+#define GTM_MCS0_CH0_R1 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R1*)0xF0130004u)
+
+/** \brief 30008, MCS Channel Program Counter Register 2 */
+#define GTM_MCS0_CH0_R2 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R2*)0xF0130008u)
+
+/** \brief 3000C, MCS Channel Program Counter Register 3 */
+#define GTM_MCS0_CH0_R3 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R3*)0xF013000Cu)
+
+/** \brief 30010, MCS Channel Program Counter Register 4 */
+#define GTM_MCS0_CH0_R4 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R4*)0xF0130010u)
+
+/** \brief 30014, MCS Channel Program Counter Register 5 */
+#define GTM_MCS0_CH0_R5 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R5*)0xF0130014u)
+
+/** \brief 30018, MCS Channel Program Counter Register 6 */
+#define GTM_MCS0_CH0_R6 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R6*)0xF0130018u)
+
+/** \brief 3001C, MCS Channel Program Counter Register 7 */
+#define GTM_MCS0_CH0_R7 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R7*)0xF013001Cu)
+
+/** \brief 3002C, MCS Set Trigger Control Register */
+#define GTM_MCS0_CH0_STRG /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH0_STRG*)0xF013002Cu)
+
+/** Alias (User Manual Name) for GTM_MCS0_CH0_STRG.
+* To use register names with standard convension, please use GTM_MCS0_CH0_STRG.
+*/
+#define GTM_MCS0_STRG (GTM_MCS0_CH0_STRG)
+
+/** \brief 300A4, MCS Channel ACB Register */
+#define GTM_MCS0_CH1_ACB /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_ACB*)0xF01300A4u)
+
+/** \brief 300A0, MCS Channel Control Register */
+#define GTM_MCS0_CH1_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_CTRL*)0xF01300A0u)
+
+/** \brief 300D4, MCS_Channel Error Interrupt Enable Register */
+#define GTM_MCS0_CH1_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_EIRQ_EN*)0xF01300D4u)
+
+/** \brief 300C8, MCS Channel Interrupt Enable Register */
+#define GTM_MCS0_CH1_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_EN*)0xF01300C8u)
+
+/** \brief 300CC, MCS Channel Software Interrupt Generation Register */
+#define GTM_MCS0_CH1_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_FORCINT*)0xF01300CCu)
+
+/** \brief 300D0, MCS IRQ Mode Configuration Register */
+#define GTM_MCS0_CH1_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_MODE*)0xF01300D0u)
+
+/** \brief 300C4, MCS Channel interrupt notification register */
+#define GTM_MCS0_CH1_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_NOTIFY*)0xF01300C4u)
+
+/** \brief 300C0, MCS Channel Program Counter Register */
+#define GTM_MCS0_CH1_PC /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_PC*)0xF01300C0u)
+
+/** \brief 30080, MCS Channel Program Counter Register 0 */
+#define GTM_MCS0_CH1_R0 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R0*)0xF0130080u)
+
+/** \brief 30084, MCS Channel Program Counter Register 1 */
+#define GTM_MCS0_CH1_R1 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R1*)0xF0130084u)
+
+/** \brief 30088, MCS Channel Program Counter Register 2 */
+#define GTM_MCS0_CH1_R2 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R2*)0xF0130088u)
+
+/** \brief 3008C, MCS Channel Program Counter Register 3 */
+#define GTM_MCS0_CH1_R3 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R3*)0xF013008Cu)
+
+/** \brief 30090, MCS Channel Program Counter Register 4 */
+#define GTM_MCS0_CH1_R4 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R4*)0xF0130090u)
+
+/** \brief 30094, MCS Channel Program Counter Register 5 */
+#define GTM_MCS0_CH1_R5 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R5*)0xF0130094u)
+
+/** \brief 30098, MCS Channel Program Counter Register 6 */
+#define GTM_MCS0_CH1_R6 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R6*)0xF0130098u)
+
+/** \brief 3009C, MCS Channel Program Counter Register 7 */
+#define GTM_MCS0_CH1_R7 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R7*)0xF013009Cu)
+
+/** \brief 30124, MCS Channel ACB Register */
+#define GTM_MCS0_CH2_ACB /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_ACB*)0xF0130124u)
+
+/** \brief 30120, MCS Channel Control Register */
+#define GTM_MCS0_CH2_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_CTRL*)0xF0130120u)
+
+/** \brief 30154, MCS_Channel Error Interrupt Enable Register */
+#define GTM_MCS0_CH2_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_EIRQ_EN*)0xF0130154u)
+
+/** \brief 30148, MCS Channel Interrupt Enable Register */
+#define GTM_MCS0_CH2_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_EN*)0xF0130148u)
+
+/** \brief 3014C, MCS Channel Software Interrupt Generation Register */
+#define GTM_MCS0_CH2_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_FORCINT*)0xF013014Cu)
+
+/** \brief 30150, MCS IRQ Mode Configuration Register */
+#define GTM_MCS0_CH2_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_MODE*)0xF0130150u)
+
+/** \brief 30144, MCS Channel interrupt notification register */
+#define GTM_MCS0_CH2_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_NOTIFY*)0xF0130144u)
+
+/** \brief 30140, MCS Channel Program Counter Register */
+#define GTM_MCS0_CH2_PC /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_PC*)0xF0130140u)
+
+/** \brief 30100, MCS Channel Program Counter Register 0 */
+#define GTM_MCS0_CH2_R0 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R0*)0xF0130100u)
+
+/** \brief 30104, MCS Channel Program Counter Register 1 */
+#define GTM_MCS0_CH2_R1 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R1*)0xF0130104u)
+
+/** \brief 30108, MCS Channel Program Counter Register 2 */
+#define GTM_MCS0_CH2_R2 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R2*)0xF0130108u)
+
+/** \brief 3010C, MCS Channel Program Counter Register 3 */
+#define GTM_MCS0_CH2_R3 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R3*)0xF013010Cu)
+
+/** \brief 30110, MCS Channel Program Counter Register 4 */
+#define GTM_MCS0_CH2_R4 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R4*)0xF0130110u)
+
+/** \brief 30114, MCS Channel Program Counter Register 5 */
+#define GTM_MCS0_CH2_R5 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R5*)0xF0130114u)
+
+/** \brief 30118, MCS Channel Program Counter Register 6 */
+#define GTM_MCS0_CH2_R6 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R6*)0xF0130118u)
+
+/** \brief 3011C, MCS Channel Program Counter Register 7 */
+#define GTM_MCS0_CH2_R7 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R7*)0xF013011Cu)
+
+/** \brief 301A4, MCS Channel ACB Register */
+#define GTM_MCS0_CH3_ACB /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_ACB*)0xF01301A4u)
+
+/** \brief 301A0, MCS Channel Control Register */
+#define GTM_MCS0_CH3_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_CTRL*)0xF01301A0u)
+
+/** \brief 301D4, MCS_Channel Error Interrupt Enable Register */
+#define GTM_MCS0_CH3_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_EIRQ_EN*)0xF01301D4u)
+
+/** \brief 301C8, MCS Channel Interrupt Enable Register */
+#define GTM_MCS0_CH3_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_EN*)0xF01301C8u)
+
+/** \brief 301CC, MCS Channel Software Interrupt Generation Register */
+#define GTM_MCS0_CH3_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_FORCINT*)0xF01301CCu)
+
+/** \brief 301D0, MCS IRQ Mode Configuration Register */
+#define GTM_MCS0_CH3_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_MODE*)0xF01301D0u)
+
+/** \brief 301C4, MCS Channel interrupt notification register */
+#define GTM_MCS0_CH3_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_NOTIFY*)0xF01301C4u)
+
+/** \brief 301C0, MCS Channel Program Counter Register */
+#define GTM_MCS0_CH3_PC /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_PC*)0xF01301C0u)
+
+/** \brief 30180, MCS Channel Program Counter Register 0 */
+#define GTM_MCS0_CH3_R0 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R0*)0xF0130180u)
+
+/** \brief 30184, MCS Channel Program Counter Register 1 */
+#define GTM_MCS0_CH3_R1 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R1*)0xF0130184u)
+
+/** \brief 30188, MCS Channel Program Counter Register 2 */
+#define GTM_MCS0_CH3_R2 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R2*)0xF0130188u)
+
+/** \brief 3018C, MCS Channel Program Counter Register 3 */
+#define GTM_MCS0_CH3_R3 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R3*)0xF013018Cu)
+
+/** \brief 30190, MCS Channel Program Counter Register 4 */
+#define GTM_MCS0_CH3_R4 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R4*)0xF0130190u)
+
+/** \brief 30194, MCS Channel Program Counter Register 5 */
+#define GTM_MCS0_CH3_R5 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R5*)0xF0130194u)
+
+/** \brief 30198, MCS Channel Program Counter Register 6 */
+#define GTM_MCS0_CH3_R6 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R6*)0xF0130198u)
+
+/** \brief 3019C, MCS Channel Program Counter Register 7 */
+#define GTM_MCS0_CH3_R7 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R7*)0xF013019Cu)
+
+/** \brief 30224, MCS Channel ACB Register */
+#define GTM_MCS0_CH4_ACB /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_ACB*)0xF0130224u)
+
+/** \brief 30220, MCS Channel Control Register */
+#define GTM_MCS0_CH4_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_CTRL*)0xF0130220u)
+
+/** \brief 30254, MCS_Channel Error Interrupt Enable Register */
+#define GTM_MCS0_CH4_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_EIRQ_EN*)0xF0130254u)
+
+/** \brief 30248, MCS Channel Interrupt Enable Register */
+#define GTM_MCS0_CH4_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_EN*)0xF0130248u)
+
+/** \brief 3024C, MCS Channel Software Interrupt Generation Register */
+#define GTM_MCS0_CH4_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_FORCINT*)0xF013024Cu)
+
+/** \brief 30250, MCS IRQ Mode Configuration Register */
+#define GTM_MCS0_CH4_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_MODE*)0xF0130250u)
+
+/** \brief 30244, MCS Channel interrupt notification register */
+#define GTM_MCS0_CH4_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_NOTIFY*)0xF0130244u)
+
+/** \brief 30240, MCS Channel Program Counter Register */
+#define GTM_MCS0_CH4_PC /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_PC*)0xF0130240u)
+
+/** \brief 30200, MCS Channel Program Counter Register 0 */
+#define GTM_MCS0_CH4_R0 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R0*)0xF0130200u)
+
+/** \brief 30204, MCS Channel Program Counter Register 1 */
+#define GTM_MCS0_CH4_R1 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R1*)0xF0130204u)
+
+/** \brief 30208, MCS Channel Program Counter Register 2 */
+#define GTM_MCS0_CH4_R2 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R2*)0xF0130208u)
+
+/** \brief 3020C, MCS Channel Program Counter Register 3 */
+#define GTM_MCS0_CH4_R3 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R3*)0xF013020Cu)
+
+/** \brief 30210, MCS Channel Program Counter Register 4 */
+#define GTM_MCS0_CH4_R4 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R4*)0xF0130210u)
+
+/** \brief 30214, MCS Channel Program Counter Register 5 */
+#define GTM_MCS0_CH4_R5 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R5*)0xF0130214u)
+
+/** \brief 30218, MCS Channel Program Counter Register 6 */
+#define GTM_MCS0_CH4_R6 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R6*)0xF0130218u)
+
+/** \brief 3021C, MCS Channel Program Counter Register 7 */
+#define GTM_MCS0_CH4_R7 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R7*)0xF013021Cu)
+
+/** \brief 302A4, MCS Channel ACB Register */
+#define GTM_MCS0_CH5_ACB /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_ACB*)0xF01302A4u)
+
+/** \brief 302A0, MCS Channel Control Register */
+#define GTM_MCS0_CH5_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_CTRL*)0xF01302A0u)
+
+/** \brief 302D4, MCS_Channel Error Interrupt Enable Register */
+#define GTM_MCS0_CH5_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_EIRQ_EN*)0xF01302D4u)
+
+/** \brief 302C8, MCS Channel Interrupt Enable Register */
+#define GTM_MCS0_CH5_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_EN*)0xF01302C8u)
+
+/** \brief 302CC, MCS Channel Software Interrupt Generation Register */
+#define GTM_MCS0_CH5_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_FORCINT*)0xF01302CCu)
+
+/** \brief 302D0, MCS IRQ Mode Configuration Register */
+#define GTM_MCS0_CH5_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_MODE*)0xF01302D0u)
+
+/** \brief 302C4, MCS Channel interrupt notification register */
+#define GTM_MCS0_CH5_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_NOTIFY*)0xF01302C4u)
+
+/** \brief 302C0, MCS Channel Program Counter Register */
+#define GTM_MCS0_CH5_PC /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_PC*)0xF01302C0u)
+
+/** \brief 30280, MCS Channel Program Counter Register 0 */
+#define GTM_MCS0_CH5_R0 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R0*)0xF0130280u)
+
+/** \brief 30284, MCS Channel Program Counter Register 1 */
+#define GTM_MCS0_CH5_R1 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R1*)0xF0130284u)
+
+/** \brief 30288, MCS Channel Program Counter Register 2 */
+#define GTM_MCS0_CH5_R2 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R2*)0xF0130288u)
+
+/** \brief 3028C, MCS Channel Program Counter Register 3 */
+#define GTM_MCS0_CH5_R3 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R3*)0xF013028Cu)
+
+/** \brief 30290, MCS Channel Program Counter Register 4 */
+#define GTM_MCS0_CH5_R4 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R4*)0xF0130290u)
+
+/** \brief 30294, MCS Channel Program Counter Register 5 */
+#define GTM_MCS0_CH5_R5 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R5*)0xF0130294u)
+
+/** \brief 30298, MCS Channel Program Counter Register 6 */
+#define GTM_MCS0_CH5_R6 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R6*)0xF0130298u)
+
+/** \brief 3029C, MCS Channel Program Counter Register 7 */
+#define GTM_MCS0_CH5_R7 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R7*)0xF013029Cu)
+
+/** \brief 30324, MCS Channel ACB Register */
+#define GTM_MCS0_CH6_ACB /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_ACB*)0xF0130324u)
+
+/** \brief 30320, MCS Channel Control Register */
+#define GTM_MCS0_CH6_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_CTRL*)0xF0130320u)
+
+/** \brief 30354, MCS_Channel Error Interrupt Enable Register */
+#define GTM_MCS0_CH6_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_EIRQ_EN*)0xF0130354u)
+
+/** \brief 30348, MCS Channel Interrupt Enable Register */
+#define GTM_MCS0_CH6_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_EN*)0xF0130348u)
+
+/** \brief 3034C, MCS Channel Software Interrupt Generation Register */
+#define GTM_MCS0_CH6_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_FORCINT*)0xF013034Cu)
+
+/** \brief 30350, MCS IRQ Mode Configuration Register */
+#define GTM_MCS0_CH6_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_MODE*)0xF0130350u)
+
+/** \brief 30344, MCS Channel interrupt notification register */
+#define GTM_MCS0_CH6_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_NOTIFY*)0xF0130344u)
+
+/** \brief 30340, MCS Channel Program Counter Register */
+#define GTM_MCS0_CH6_PC /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_PC*)0xF0130340u)
+
+/** \brief 30300, MCS Channel Program Counter Register 0 */
+#define GTM_MCS0_CH6_R0 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R0*)0xF0130300u)
+
+/** \brief 30304, MCS Channel Program Counter Register 1 */
+#define GTM_MCS0_CH6_R1 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R1*)0xF0130304u)
+
+/** \brief 30308, MCS Channel Program Counter Register 2 */
+#define GTM_MCS0_CH6_R2 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R2*)0xF0130308u)
+
+/** \brief 3030C, MCS Channel Program Counter Register 3 */
+#define GTM_MCS0_CH6_R3 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R3*)0xF013030Cu)
+
+/** \brief 30310, MCS Channel Program Counter Register 4 */
+#define GTM_MCS0_CH6_R4 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R4*)0xF0130310u)
+
+/** \brief 30314, MCS Channel Program Counter Register 5 */
+#define GTM_MCS0_CH6_R5 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R5*)0xF0130314u)
+
+/** \brief 30318, MCS Channel Program Counter Register 6 */
+#define GTM_MCS0_CH6_R6 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R6*)0xF0130318u)
+
+/** \brief 3031C, MCS Channel Program Counter Register 7 */
+#define GTM_MCS0_CH6_R7 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R7*)0xF013031Cu)
+
+/** \brief 303A4, MCS Channel ACB Register */
+#define GTM_MCS0_CH7_ACB /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_ACB*)0xF01303A4u)
+
+/** \brief 303A0, MCS Channel Control Register */
+#define GTM_MCS0_CH7_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_CTRL*)0xF01303A0u)
+
+/** \brief 303D4, MCS_Channel Error Interrupt Enable Register */
+#define GTM_MCS0_CH7_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_EIRQ_EN*)0xF01303D4u)
+
+/** \brief 303C8, MCS Channel Interrupt Enable Register */
+#define GTM_MCS0_CH7_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_EN*)0xF01303C8u)
+
+/** \brief 303CC, MCS Channel Software Interrupt Generation Register */
+#define GTM_MCS0_CH7_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_FORCINT*)0xF01303CCu)
+
+/** \brief 303D0, MCS IRQ Mode Configuration Register */
+#define GTM_MCS0_CH7_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_MODE*)0xF01303D0u)
+
+/** \brief 303C4, MCS Channel interrupt notification register */
+#define GTM_MCS0_CH7_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_NOTIFY*)0xF01303C4u)
+
+/** \brief 303C0, MCS Channel Program Counter Register */
+#define GTM_MCS0_CH7_PC /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_PC*)0xF01303C0u)
+
+/** \brief 30380, MCS Channel Program Counter Register 0 */
+#define GTM_MCS0_CH7_R0 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R0*)0xF0130380u)
+
+/** \brief 30384, MCS Channel Program Counter Register 1 */
+#define GTM_MCS0_CH7_R1 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R1*)0xF0130384u)
+
+/** \brief 30388, MCS Channel Program Counter Register 2 */
+#define GTM_MCS0_CH7_R2 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R2*)0xF0130388u)
+
+/** \brief 3038C, MCS Channel Program Counter Register 3 */
+#define GTM_MCS0_CH7_R3 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R3*)0xF013038Cu)
+
+/** \brief 30390, MCS Channel Program Counter Register 4 */
+#define GTM_MCS0_CH7_R4 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R4*)0xF0130390u)
+
+/** \brief 30394, MCS Channel Program Counter Register 5 */
+#define GTM_MCS0_CH7_R5 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R5*)0xF0130394u)
+
+/** \brief 30398, MCS Channel Program Counter Register 6 */
+#define GTM_MCS0_CH7_R6 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R6*)0xF0130398u)
+
+/** \brief 3039C, MCS Channel Program Counter Register 7 */
+#define GTM_MCS0_CH7_R7 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R7*)0xF013039Cu)
+
+/** \brief 30074, MCS Control Register */
+#define GTM_MCS0_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CTRL*)0xF0130074u)
+
+/** \brief 3007C, MCS Error Register */
+#define GTM_MCS0_ERR /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_ERR*)0xF013007Cu)
+
+/** \brief 30078, MCS Channel Reset Register */
+#define GTM_MCS0_RST /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_RST*)0xF0130078u)
+
+/** \brief 31024, MCS Channel ACB Register */
+#define GTM_MCS1_CH0_ACB /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_ACB*)0xF0131024u)
+
+/** \brief 31028, MCS Clear Trigger Control Register */
+#define GTM_MCS1_CH0_CTRG /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH0_CTRG*)0xF0131028u)
+
+/** Alias (User Manual Name) for GTM_MCS1_CH0_CTRG.
+* To use register names with standard convension, please use GTM_MCS1_CH0_CTRG.
+*/
+#define GTM_MCS1_CTRG (GTM_MCS1_CH0_CTRG)
+
+/** \brief 31020, MCS Channel Control Register */
+#define GTM_MCS1_CH0_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_CTRL*)0xF0131020u)
+
+/** \brief 31054, MCS_Channel Error Interrupt Enable Register */
+#define GTM_MCS1_CH0_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_EIRQ_EN*)0xF0131054u)
+
+/** \brief 31048, MCS Channel Interrupt Enable Register */
+#define GTM_MCS1_CH0_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_EN*)0xF0131048u)
+
+/** \brief 3104C, MCS Channel Software Interrupt Generation Register */
+#define GTM_MCS1_CH0_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_FORCINT*)0xF013104Cu)
+
+/** \brief 31050, MCS IRQ Mode Configuration Register */
+#define GTM_MCS1_CH0_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_MODE*)0xF0131050u)
+
+/** \brief 31044, MCS Channel interrupt notification register */
+#define GTM_MCS1_CH0_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_NOTIFY*)0xF0131044u)
+
+/** \brief 31040, MCS Channel Program Counter Register */
+#define GTM_MCS1_CH0_PC /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_PC*)0xF0131040u)
+
+/** \brief 31000, MCS Channel Program Counter Register 0 */
+#define GTM_MCS1_CH0_R0 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R0*)0xF0131000u)
+
+/** \brief 31004, MCS Channel Program Counter Register 1 */
+#define GTM_MCS1_CH0_R1 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R1*)0xF0131004u)
+
+/** \brief 31008, MCS Channel Program Counter Register 2 */
+#define GTM_MCS1_CH0_R2 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R2*)0xF0131008u)
+
+/** \brief 3100C, MCS Channel Program Counter Register 3 */
+#define GTM_MCS1_CH0_R3 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R3*)0xF013100Cu)
+
+/** \brief 31010, MCS Channel Program Counter Register 4 */
+#define GTM_MCS1_CH0_R4 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R4*)0xF0131010u)
+
+/** \brief 31014, MCS Channel Program Counter Register 5 */
+#define GTM_MCS1_CH0_R5 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R5*)0xF0131014u)
+
+/** \brief 31018, MCS Channel Program Counter Register 6 */
+#define GTM_MCS1_CH0_R6 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R6*)0xF0131018u)
+
+/** \brief 3101C, MCS Channel Program Counter Register 7 */
+#define GTM_MCS1_CH0_R7 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R7*)0xF013101Cu)
+
+/** \brief 3102C, MCS Set Trigger Control Register */
+#define GTM_MCS1_CH0_STRG /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH0_STRG*)0xF013102Cu)
+
+/** Alias (User Manual Name) for GTM_MCS1_CH0_STRG.
+* To use register names with standard convension, please use GTM_MCS1_CH0_STRG.
+*/
+#define GTM_MCS1_STRG (GTM_MCS1_CH0_STRG)
+
+/** \brief 310A4, MCS Channel ACB Register */
+#define GTM_MCS1_CH1_ACB /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_ACB*)0xF01310A4u)
+
+/** \brief 310A0, MCS Channel Control Register */
+#define GTM_MCS1_CH1_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_CTRL*)0xF01310A0u)
+
+/** \brief 310D4, MCS_Channel Error Interrupt Enable Register */
+#define GTM_MCS1_CH1_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_EIRQ_EN*)0xF01310D4u)
+
+/** \brief 310C8, MCS Channel Interrupt Enable Register */
+#define GTM_MCS1_CH1_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_EN*)0xF01310C8u)
+
+/** \brief 310CC, MCS Channel Software Interrupt Generation Register */
+#define GTM_MCS1_CH1_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_FORCINT*)0xF01310CCu)
+
+/** \brief 310D0, MCS IRQ Mode Configuration Register */
+#define GTM_MCS1_CH1_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_MODE*)0xF01310D0u)
+
+/** \brief 310C4, MCS Channel interrupt notification register */
+#define GTM_MCS1_CH1_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_NOTIFY*)0xF01310C4u)
+
+/** \brief 310C0, MCS Channel Program Counter Register */
+#define GTM_MCS1_CH1_PC /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_PC*)0xF01310C0u)
+
+/** \brief 31080, MCS Channel Program Counter Register 0 */
+#define GTM_MCS1_CH1_R0 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R0*)0xF0131080u)
+
+/** \brief 31084, MCS Channel Program Counter Register 1 */
+#define GTM_MCS1_CH1_R1 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R1*)0xF0131084u)
+
+/** \brief 31088, MCS Channel Program Counter Register 2 */
+#define GTM_MCS1_CH1_R2 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R2*)0xF0131088u)
+
+/** \brief 3108C, MCS Channel Program Counter Register 3 */
+#define GTM_MCS1_CH1_R3 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R3*)0xF013108Cu)
+
+/** \brief 31090, MCS Channel Program Counter Register 4 */
+#define GTM_MCS1_CH1_R4 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R4*)0xF0131090u)
+
+/** \brief 31094, MCS Channel Program Counter Register 5 */
+#define GTM_MCS1_CH1_R5 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R5*)0xF0131094u)
+
+/** \brief 31098, MCS Channel Program Counter Register 6 */
+#define GTM_MCS1_CH1_R6 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R6*)0xF0131098u)
+
+/** \brief 3109C, MCS Channel Program Counter Register 7 */
+#define GTM_MCS1_CH1_R7 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R7*)0xF013109Cu)
+
+/** \brief 31124, MCS Channel ACB Register */
+#define GTM_MCS1_CH2_ACB /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_ACB*)0xF0131124u)
+
+/** \brief 31120, MCS Channel Control Register */
+#define GTM_MCS1_CH2_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_CTRL*)0xF0131120u)
+
+/** \brief 31154, MCS_Channel Error Interrupt Enable Register */
+#define GTM_MCS1_CH2_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_EIRQ_EN*)0xF0131154u)
+
+/** \brief 31148, MCS Channel Interrupt Enable Register */
+#define GTM_MCS1_CH2_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_EN*)0xF0131148u)
+
+/** \brief 3114C, MCS Channel Software Interrupt Generation Register */
+#define GTM_MCS1_CH2_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_FORCINT*)0xF013114Cu)
+
+/** \brief 31150, MCS IRQ Mode Configuration Register */
+#define GTM_MCS1_CH2_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_MODE*)0xF0131150u)
+
+/** \brief 31144, MCS Channel interrupt notification register */
+#define GTM_MCS1_CH2_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_NOTIFY*)0xF0131144u)
+
+/** \brief 31140, MCS Channel Program Counter Register */
+#define GTM_MCS1_CH2_PC /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_PC*)0xF0131140u)
+
+/** \brief 31100, MCS Channel Program Counter Register 0 */
+#define GTM_MCS1_CH2_R0 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R0*)0xF0131100u)
+
+/** \brief 31104, MCS Channel Program Counter Register 1 */
+#define GTM_MCS1_CH2_R1 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R1*)0xF0131104u)
+
+/** \brief 31108, MCS Channel Program Counter Register 2 */
+#define GTM_MCS1_CH2_R2 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R2*)0xF0131108u)
+
+/** \brief 3110C, MCS Channel Program Counter Register 3 */
+#define GTM_MCS1_CH2_R3 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R3*)0xF013110Cu)
+
+/** \brief 31110, MCS Channel Program Counter Register 4 */
+#define GTM_MCS1_CH2_R4 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R4*)0xF0131110u)
+
+/** \brief 31114, MCS Channel Program Counter Register 5 */
+#define GTM_MCS1_CH2_R5 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R5*)0xF0131114u)
+
+/** \brief 31118, MCS Channel Program Counter Register 6 */
+#define GTM_MCS1_CH2_R6 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R6*)0xF0131118u)
+
+/** \brief 3111C, MCS Channel Program Counter Register 7 */
+#define GTM_MCS1_CH2_R7 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R7*)0xF013111Cu)
+
+/** \brief 311A4, MCS Channel ACB Register */
+#define GTM_MCS1_CH3_ACB /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_ACB*)0xF01311A4u)
+
+/** \brief 311A0, MCS Channel Control Register */
+#define GTM_MCS1_CH3_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_CTRL*)0xF01311A0u)
+
+/** \brief 311D4, MCS_Channel Error Interrupt Enable Register */
+#define GTM_MCS1_CH3_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_EIRQ_EN*)0xF01311D4u)
+
+/** \brief 311C8, MCS Channel Interrupt Enable Register */
+#define GTM_MCS1_CH3_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_EN*)0xF01311C8u)
+
+/** \brief 311CC, MCS Channel Software Interrupt Generation Register */
+#define GTM_MCS1_CH3_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_FORCINT*)0xF01311CCu)
+
+/** \brief 311D0, MCS IRQ Mode Configuration Register */
+#define GTM_MCS1_CH3_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_MODE*)0xF01311D0u)
+
+/** \brief 311C4, MCS Channel interrupt notification register */
+#define GTM_MCS1_CH3_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_NOTIFY*)0xF01311C4u)
+
+/** \brief 311C0, MCS Channel Program Counter Register */
+#define GTM_MCS1_CH3_PC /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_PC*)0xF01311C0u)
+
+/** \brief 31180, MCS Channel Program Counter Register 0 */
+#define GTM_MCS1_CH3_R0 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R0*)0xF0131180u)
+
+/** \brief 31184, MCS Channel Program Counter Register 1 */
+#define GTM_MCS1_CH3_R1 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R1*)0xF0131184u)
+
+/** \brief 31188, MCS Channel Program Counter Register 2 */
+#define GTM_MCS1_CH3_R2 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R2*)0xF0131188u)
+
+/** \brief 3118C, MCS Channel Program Counter Register 3 */
+#define GTM_MCS1_CH3_R3 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R3*)0xF013118Cu)
+
+/** \brief 31190, MCS Channel Program Counter Register 4 */
+#define GTM_MCS1_CH3_R4 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R4*)0xF0131190u)
+
+/** \brief 31194, MCS Channel Program Counter Register 5 */
+#define GTM_MCS1_CH3_R5 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R5*)0xF0131194u)
+
+/** \brief 31198, MCS Channel Program Counter Register 6 */
+#define GTM_MCS1_CH3_R6 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R6*)0xF0131198u)
+
+/** \brief 3119C, MCS Channel Program Counter Register 7 */
+#define GTM_MCS1_CH3_R7 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R7*)0xF013119Cu)
+
+/** \brief 31224, MCS Channel ACB Register */
+#define GTM_MCS1_CH4_ACB /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_ACB*)0xF0131224u)
+
+/** \brief 31220, MCS Channel Control Register */
+#define GTM_MCS1_CH4_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_CTRL*)0xF0131220u)
+
+/** \brief 31254, MCS_Channel Error Interrupt Enable Register */
+#define GTM_MCS1_CH4_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_EIRQ_EN*)0xF0131254u)
+
+/** \brief 31248, MCS Channel Interrupt Enable Register */
+#define GTM_MCS1_CH4_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_EN*)0xF0131248u)
+
+/** \brief 3124C, MCS Channel Software Interrupt Generation Register */
+#define GTM_MCS1_CH4_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_FORCINT*)0xF013124Cu)
+
+/** \brief 31250, MCS IRQ Mode Configuration Register */
+#define GTM_MCS1_CH4_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_MODE*)0xF0131250u)
+
+/** \brief 31244, MCS Channel interrupt notification register */
+#define GTM_MCS1_CH4_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_NOTIFY*)0xF0131244u)
+
+/** \brief 31240, MCS Channel Program Counter Register */
+#define GTM_MCS1_CH4_PC /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_PC*)0xF0131240u)
+
+/** \brief 31200, MCS Channel Program Counter Register 0 */
+#define GTM_MCS1_CH4_R0 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R0*)0xF0131200u)
+
+/** \brief 31204, MCS Channel Program Counter Register 1 */
+#define GTM_MCS1_CH4_R1 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R1*)0xF0131204u)
+
+/** \brief 31208, MCS Channel Program Counter Register 2 */
+#define GTM_MCS1_CH4_R2 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R2*)0xF0131208u)
+
+/** \brief 3120C, MCS Channel Program Counter Register 3 */
+#define GTM_MCS1_CH4_R3 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R3*)0xF013120Cu)
+
+/** \brief 31210, MCS Channel Program Counter Register 4 */
+#define GTM_MCS1_CH4_R4 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R4*)0xF0131210u)
+
+/** \brief 31214, MCS Channel Program Counter Register 5 */
+#define GTM_MCS1_CH4_R5 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R5*)0xF0131214u)
+
+/** \brief 31218, MCS Channel Program Counter Register 6 */
+#define GTM_MCS1_CH4_R6 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R6*)0xF0131218u)
+
+/** \brief 3121C, MCS Channel Program Counter Register 7 */
+#define GTM_MCS1_CH4_R7 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R7*)0xF013121Cu)
+
+/** \brief 312A4, MCS Channel ACB Register */
+#define GTM_MCS1_CH5_ACB /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_ACB*)0xF01312A4u)
+
+/** \brief 312A0, MCS Channel Control Register */
+#define GTM_MCS1_CH5_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_CTRL*)0xF01312A0u)
+
+/** \brief 312D4, MCS_Channel Error Interrupt Enable Register */
+#define GTM_MCS1_CH5_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_EIRQ_EN*)0xF01312D4u)
+
+/** \brief 312C8, MCS Channel Interrupt Enable Register */
+#define GTM_MCS1_CH5_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_EN*)0xF01312C8u)
+
+/** \brief 312CC, MCS Channel Software Interrupt Generation Register */
+#define GTM_MCS1_CH5_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_FORCINT*)0xF01312CCu)
+
+/** \brief 312D0, MCS IRQ Mode Configuration Register */
+#define GTM_MCS1_CH5_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_MODE*)0xF01312D0u)
+
+/** \brief 312C4, MCS Channel interrupt notification register */
+#define GTM_MCS1_CH5_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_NOTIFY*)0xF01312C4u)
+
+/** \brief 312C0, MCS Channel Program Counter Register */
+#define GTM_MCS1_CH5_PC /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_PC*)0xF01312C0u)
+
+/** \brief 31280, MCS Channel Program Counter Register 0 */
+#define GTM_MCS1_CH5_R0 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R0*)0xF0131280u)
+
+/** \brief 31284, MCS Channel Program Counter Register 1 */
+#define GTM_MCS1_CH5_R1 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R1*)0xF0131284u)
+
+/** \brief 31288, MCS Channel Program Counter Register 2 */
+#define GTM_MCS1_CH5_R2 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R2*)0xF0131288u)
+
+/** \brief 3128C, MCS Channel Program Counter Register 3 */
+#define GTM_MCS1_CH5_R3 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R3*)0xF013128Cu)
+
+/** \brief 31290, MCS Channel Program Counter Register 4 */
+#define GTM_MCS1_CH5_R4 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R4*)0xF0131290u)
+
+/** \brief 31294, MCS Channel Program Counter Register 5 */
+#define GTM_MCS1_CH5_R5 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R5*)0xF0131294u)
+
+/** \brief 31298, MCS Channel Program Counter Register 6 */
+#define GTM_MCS1_CH5_R6 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R6*)0xF0131298u)
+
+/** \brief 3129C, MCS Channel Program Counter Register 7 */
+#define GTM_MCS1_CH5_R7 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R7*)0xF013129Cu)
+
+/** \brief 31324, MCS Channel ACB Register */
+#define GTM_MCS1_CH6_ACB /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_ACB*)0xF0131324u)
+
+/** \brief 31320, MCS Channel Control Register */
+#define GTM_MCS1_CH6_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_CTRL*)0xF0131320u)
+
+/** \brief 31354, MCS_Channel Error Interrupt Enable Register */
+#define GTM_MCS1_CH6_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_EIRQ_EN*)0xF0131354u)
+
+/** \brief 31348, MCS Channel Interrupt Enable Register */
+#define GTM_MCS1_CH6_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_EN*)0xF0131348u)
+
+/** \brief 3134C, MCS Channel Software Interrupt Generation Register */
+#define GTM_MCS1_CH6_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_FORCINT*)0xF013134Cu)
+
+/** \brief 31350, MCS IRQ Mode Configuration Register */
+#define GTM_MCS1_CH6_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_MODE*)0xF0131350u)
+
+/** \brief 31344, MCS Channel interrupt notification register */
+#define GTM_MCS1_CH6_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_NOTIFY*)0xF0131344u)
+
+/** \brief 31340, MCS Channel Program Counter Register */
+#define GTM_MCS1_CH6_PC /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_PC*)0xF0131340u)
+
+/** \brief 31300, MCS Channel Program Counter Register 0 */
+#define GTM_MCS1_CH6_R0 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R0*)0xF0131300u)
+
+/** \brief 31304, MCS Channel Program Counter Register 1 */
+#define GTM_MCS1_CH6_R1 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R1*)0xF0131304u)
+
+/** \brief 31308, MCS Channel Program Counter Register 2 */
+#define GTM_MCS1_CH6_R2 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R2*)0xF0131308u)
+
+/** \brief 3130C, MCS Channel Program Counter Register 3 */
+#define GTM_MCS1_CH6_R3 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R3*)0xF013130Cu)
+
+/** \brief 31310, MCS Channel Program Counter Register 4 */
+#define GTM_MCS1_CH6_R4 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R4*)0xF0131310u)
+
+/** \brief 31314, MCS Channel Program Counter Register 5 */
+#define GTM_MCS1_CH6_R5 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R5*)0xF0131314u)
+
+/** \brief 31318, MCS Channel Program Counter Register 6 */
+#define GTM_MCS1_CH6_R6 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R6*)0xF0131318u)
+
+/** \brief 3131C, MCS Channel Program Counter Register 7 */
+#define GTM_MCS1_CH6_R7 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R7*)0xF013131Cu)
+
+/** \brief 313A4, MCS Channel ACB Register */
+#define GTM_MCS1_CH7_ACB /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_ACB*)0xF01313A4u)
+
+/** \brief 313A0, MCS Channel Control Register */
+#define GTM_MCS1_CH7_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_CTRL*)0xF01313A0u)
+
+/** \brief 313D4, MCS_Channel Error Interrupt Enable Register */
+#define GTM_MCS1_CH7_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_EIRQ_EN*)0xF01313D4u)
+
+/** \brief 313C8, MCS Channel Interrupt Enable Register */
+#define GTM_MCS1_CH7_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_EN*)0xF01313C8u)
+
+/** \brief 313CC, MCS Channel Software Interrupt Generation Register */
+#define GTM_MCS1_CH7_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_FORCINT*)0xF01313CCu)
+
+/** \brief 313D0, MCS IRQ Mode Configuration Register */
+#define GTM_MCS1_CH7_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_MODE*)0xF01313D0u)
+
+/** \brief 313C4, MCS Channel interrupt notification register */
+#define GTM_MCS1_CH7_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_NOTIFY*)0xF01313C4u)
+
+/** \brief 313C0, MCS Channel Program Counter Register */
+#define GTM_MCS1_CH7_PC /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_PC*)0xF01313C0u)
+
+/** \brief 31380, MCS Channel Program Counter Register 0 */
+#define GTM_MCS1_CH7_R0 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R0*)0xF0131380u)
+
+/** \brief 31384, MCS Channel Program Counter Register 1 */
+#define GTM_MCS1_CH7_R1 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R1*)0xF0131384u)
+
+/** \brief 31388, MCS Channel Program Counter Register 2 */
+#define GTM_MCS1_CH7_R2 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R2*)0xF0131388u)
+
+/** \brief 3138C, MCS Channel Program Counter Register 3 */
+#define GTM_MCS1_CH7_R3 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R3*)0xF013138Cu)
+
+/** \brief 31390, MCS Channel Program Counter Register 4 */
+#define GTM_MCS1_CH7_R4 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R4*)0xF0131390u)
+
+/** \brief 31394, MCS Channel Program Counter Register 5 */
+#define GTM_MCS1_CH7_R5 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R5*)0xF0131394u)
+
+/** \brief 31398, MCS Channel Program Counter Register 6 */
+#define GTM_MCS1_CH7_R6 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R6*)0xF0131398u)
+
+/** \brief 3139C, MCS Channel Program Counter Register 7 */
+#define GTM_MCS1_CH7_R7 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R7*)0xF013139Cu)
+
+/** \brief 31074, MCS Control Register */
+#define GTM_MCS1_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CTRL*)0xF0131074u)
+
+/** \brief 3107C, MCS Error Register */
+#define GTM_MCS1_ERR /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_ERR*)0xF013107Cu)
+
+/** \brief 31078, MCS Channel Reset Register */
+#define GTM_MCS1_RST /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_RST*)0xF0131078u)
+
+/** \brief 32024, MCS Channel ACB Register */
+#define GTM_MCS2_CH0_ACB /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_ACB*)0xF0132024u)
+
+/** \brief 32028, MCS Clear Trigger Control Register */
+#define GTM_MCS2_CH0_CTRG /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH0_CTRG*)0xF0132028u)
+
+/** Alias (User Manual Name) for GTM_MCS2_CH0_CTRG.
+* To use register names with standard convension, please use GTM_MCS2_CH0_CTRG.
+*/
+#define GTM_MCS2_CTRG (GTM_MCS2_CH0_CTRG)
+
+/** \brief 32020, MCS Channel Control Register */
+#define GTM_MCS2_CH0_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_CTRL*)0xF0132020u)
+
+/** \brief 32054, MCS_Channel Error Interrupt Enable Register */
+#define GTM_MCS2_CH0_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_EIRQ_EN*)0xF0132054u)
+
+/** \brief 32048, MCS Channel Interrupt Enable Register */
+#define GTM_MCS2_CH0_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_EN*)0xF0132048u)
+
+/** \brief 3204C, MCS Channel Software Interrupt Generation Register */
+#define GTM_MCS2_CH0_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_FORCINT*)0xF013204Cu)
+
+/** \brief 32050, MCS IRQ Mode Configuration Register */
+#define GTM_MCS2_CH0_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_MODE*)0xF0132050u)
+
+/** \brief 32044, MCS Channel interrupt notification register */
+#define GTM_MCS2_CH0_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_NOTIFY*)0xF0132044u)
+
+/** \brief 32040, MCS Channel Program Counter Register */
+#define GTM_MCS2_CH0_PC /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_PC*)0xF0132040u)
+
+/** \brief 32000, MCS Channel Program Counter Register 0 */
+#define GTM_MCS2_CH0_R0 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R0*)0xF0132000u)
+
+/** \brief 32004, MCS Channel Program Counter Register 1 */
+#define GTM_MCS2_CH0_R1 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R1*)0xF0132004u)
+
+/** \brief 32008, MCS Channel Program Counter Register 2 */
+#define GTM_MCS2_CH0_R2 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R2*)0xF0132008u)
+
+/** \brief 3200C, MCS Channel Program Counter Register 3 */
+#define GTM_MCS2_CH0_R3 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R3*)0xF013200Cu)
+
+/** \brief 32010, MCS Channel Program Counter Register 4 */
+#define GTM_MCS2_CH0_R4 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R4*)0xF0132010u)
+
+/** \brief 32014, MCS Channel Program Counter Register 5 */
+#define GTM_MCS2_CH0_R5 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R5*)0xF0132014u)
+
+/** \brief 32018, MCS Channel Program Counter Register 6 */
+#define GTM_MCS2_CH0_R6 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R6*)0xF0132018u)
+
+/** \brief 3201C, MCS Channel Program Counter Register 7 */
+#define GTM_MCS2_CH0_R7 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R7*)0xF013201Cu)
+
+/** \brief 3202C, MCS Set Trigger Control Register */
+#define GTM_MCS2_CH0_STRG /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH0_STRG*)0xF013202Cu)
+
+/** Alias (User Manual Name) for GTM_MCS2_CH0_STRG.
+* To use register names with standard convension, please use GTM_MCS2_CH0_STRG.
+*/
+#define GTM_MCS2_STRG (GTM_MCS2_CH0_STRG)
+
+/** \brief 320A4, MCS Channel ACB Register */
+#define GTM_MCS2_CH1_ACB /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_ACB*)0xF01320A4u)
+
+/** \brief 320A0, MCS Channel Control Register */
+#define GTM_MCS2_CH1_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_CTRL*)0xF01320A0u)
+
+/** \brief 320D4, MCS_Channel Error Interrupt Enable Register */
+#define GTM_MCS2_CH1_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_EIRQ_EN*)0xF01320D4u)
+
+/** \brief 320C8, MCS Channel Interrupt Enable Register */
+#define GTM_MCS2_CH1_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_EN*)0xF01320C8u)
+
+/** \brief 320CC, MCS Channel Software Interrupt Generation Register */
+#define GTM_MCS2_CH1_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_FORCINT*)0xF01320CCu)
+
+/** \brief 320D0, MCS IRQ Mode Configuration Register */
+#define GTM_MCS2_CH1_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_MODE*)0xF01320D0u)
+
+/** \brief 320C4, MCS Channel interrupt notification register */
+#define GTM_MCS2_CH1_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_NOTIFY*)0xF01320C4u)
+
+/** \brief 320C0, MCS Channel Program Counter Register */
+#define GTM_MCS2_CH1_PC /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_PC*)0xF01320C0u)
+
+/** \brief 32080, MCS Channel Program Counter Register 0 */
+#define GTM_MCS2_CH1_R0 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R0*)0xF0132080u)
+
+/** \brief 32084, MCS Channel Program Counter Register 1 */
+#define GTM_MCS2_CH1_R1 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R1*)0xF0132084u)
+
+/** \brief 32088, MCS Channel Program Counter Register 2 */
+#define GTM_MCS2_CH1_R2 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R2*)0xF0132088u)
+
+/** \brief 3208C, MCS Channel Program Counter Register 3 */
+#define GTM_MCS2_CH1_R3 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R3*)0xF013208Cu)
+
+/** \brief 32090, MCS Channel Program Counter Register 4 */
+#define GTM_MCS2_CH1_R4 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R4*)0xF0132090u)
+
+/** \brief 32094, MCS Channel Program Counter Register 5 */
+#define GTM_MCS2_CH1_R5 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R5*)0xF0132094u)
+
+/** \brief 32098, MCS Channel Program Counter Register 6 */
+#define GTM_MCS2_CH1_R6 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R6*)0xF0132098u)
+
+/** \brief 3209C, MCS Channel Program Counter Register 7 */
+#define GTM_MCS2_CH1_R7 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R7*)0xF013209Cu)
+
+/** \brief 32124, MCS Channel ACB Register */
+#define GTM_MCS2_CH2_ACB /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_ACB*)0xF0132124u)
+
+/** \brief 32120, MCS Channel Control Register */
+#define GTM_MCS2_CH2_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_CTRL*)0xF0132120u)
+
+/** \brief 32154, MCS_Channel Error Interrupt Enable Register */
+#define GTM_MCS2_CH2_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_EIRQ_EN*)0xF0132154u)
+
+/** \brief 32148, MCS Channel Interrupt Enable Register */
+#define GTM_MCS2_CH2_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_EN*)0xF0132148u)
+
+/** \brief 3214C, MCS Channel Software Interrupt Generation Register */
+#define GTM_MCS2_CH2_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_FORCINT*)0xF013214Cu)
+
+/** \brief 32150, MCS IRQ Mode Configuration Register */
+#define GTM_MCS2_CH2_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_MODE*)0xF0132150u)
+
+/** \brief 32144, MCS Channel interrupt notification register */
+#define GTM_MCS2_CH2_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_NOTIFY*)0xF0132144u)
+
+/** \brief 32140, MCS Channel Program Counter Register */
+#define GTM_MCS2_CH2_PC /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_PC*)0xF0132140u)
+
+/** \brief 32100, MCS Channel Program Counter Register 0 */
+#define GTM_MCS2_CH2_R0 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R0*)0xF0132100u)
+
+/** \brief 32104, MCS Channel Program Counter Register 1 */
+#define GTM_MCS2_CH2_R1 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R1*)0xF0132104u)
+
+/** \brief 32108, MCS Channel Program Counter Register 2 */
+#define GTM_MCS2_CH2_R2 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R2*)0xF0132108u)
+
+/** \brief 3210C, MCS Channel Program Counter Register 3 */
+#define GTM_MCS2_CH2_R3 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R3*)0xF013210Cu)
+
+/** \brief 32110, MCS Channel Program Counter Register 4 */
+#define GTM_MCS2_CH2_R4 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R4*)0xF0132110u)
+
+/** \brief 32114, MCS Channel Program Counter Register 5 */
+#define GTM_MCS2_CH2_R5 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R5*)0xF0132114u)
+
+/** \brief 32118, MCS Channel Program Counter Register 6 */
+#define GTM_MCS2_CH2_R6 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R6*)0xF0132118u)
+
+/** \brief 3211C, MCS Channel Program Counter Register 7 */
+#define GTM_MCS2_CH2_R7 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R7*)0xF013211Cu)
+
+/** \brief 321A4, MCS Channel ACB Register */
+#define GTM_MCS2_CH3_ACB /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_ACB*)0xF01321A4u)
+
+/** \brief 321A0, MCS Channel Control Register */
+#define GTM_MCS2_CH3_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_CTRL*)0xF01321A0u)
+
+/** \brief 321D4, MCS_Channel Error Interrupt Enable Register */
+#define GTM_MCS2_CH3_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_EIRQ_EN*)0xF01321D4u)
+
+/** \brief 321C8, MCS Channel Interrupt Enable Register */
+#define GTM_MCS2_CH3_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_EN*)0xF01321C8u)
+
+/** \brief 321CC, MCS Channel Software Interrupt Generation Register */
+#define GTM_MCS2_CH3_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_FORCINT*)0xF01321CCu)
+
+/** \brief 321D0, MCS IRQ Mode Configuration Register */
+#define GTM_MCS2_CH3_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_MODE*)0xF01321D0u)
+
+/** \brief 321C4, MCS Channel interrupt notification register */
+#define GTM_MCS2_CH3_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_NOTIFY*)0xF01321C4u)
+
+/** \brief 321C0, MCS Channel Program Counter Register */
+#define GTM_MCS2_CH3_PC /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_PC*)0xF01321C0u)
+
+/** \brief 32180, MCS Channel Program Counter Register 0 */
+#define GTM_MCS2_CH3_R0 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R0*)0xF0132180u)
+
+/** \brief 32184, MCS Channel Program Counter Register 1 */
+#define GTM_MCS2_CH3_R1 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R1*)0xF0132184u)
+
+/** \brief 32188, MCS Channel Program Counter Register 2 */
+#define GTM_MCS2_CH3_R2 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R2*)0xF0132188u)
+
+/** \brief 3218C, MCS Channel Program Counter Register 3 */
+#define GTM_MCS2_CH3_R3 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R3*)0xF013218Cu)
+
+/** \brief 32190, MCS Channel Program Counter Register 4 */
+#define GTM_MCS2_CH3_R4 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R4*)0xF0132190u)
+
+/** \brief 32194, MCS Channel Program Counter Register 5 */
+#define GTM_MCS2_CH3_R5 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R5*)0xF0132194u)
+
+/** \brief 32198, MCS Channel Program Counter Register 6 */
+#define GTM_MCS2_CH3_R6 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R6*)0xF0132198u)
+
+/** \brief 3219C, MCS Channel Program Counter Register 7 */
+#define GTM_MCS2_CH3_R7 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R7*)0xF013219Cu)
+
+/** \brief 32224, MCS Channel ACB Register */
+#define GTM_MCS2_CH4_ACB /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_ACB*)0xF0132224u)
+
+/** \brief 32220, MCS Channel Control Register */
+#define GTM_MCS2_CH4_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_CTRL*)0xF0132220u)
+
+/** \brief 32254, MCS_Channel Error Interrupt Enable Register */
+#define GTM_MCS2_CH4_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_EIRQ_EN*)0xF0132254u)
+
+/** \brief 32248, MCS Channel Interrupt Enable Register */
+#define GTM_MCS2_CH4_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_EN*)0xF0132248u)
+
+/** \brief 3224C, MCS Channel Software Interrupt Generation Register */
+#define GTM_MCS2_CH4_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_FORCINT*)0xF013224Cu)
+
+/** \brief 32250, MCS IRQ Mode Configuration Register */
+#define GTM_MCS2_CH4_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_MODE*)0xF0132250u)
+
+/** \brief 32244, MCS Channel interrupt notification register */
+#define GTM_MCS2_CH4_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_NOTIFY*)0xF0132244u)
+
+/** \brief 32240, MCS Channel Program Counter Register */
+#define GTM_MCS2_CH4_PC /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_PC*)0xF0132240u)
+
+/** \brief 32200, MCS Channel Program Counter Register 0 */
+#define GTM_MCS2_CH4_R0 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R0*)0xF0132200u)
+
+/** \brief 32204, MCS Channel Program Counter Register 1 */
+#define GTM_MCS2_CH4_R1 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R1*)0xF0132204u)
+
+/** \brief 32208, MCS Channel Program Counter Register 2 */
+#define GTM_MCS2_CH4_R2 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R2*)0xF0132208u)
+
+/** \brief 3220C, MCS Channel Program Counter Register 3 */
+#define GTM_MCS2_CH4_R3 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R3*)0xF013220Cu)
+
+/** \brief 32210, MCS Channel Program Counter Register 4 */
+#define GTM_MCS2_CH4_R4 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R4*)0xF0132210u)
+
+/** \brief 32214, MCS Channel Program Counter Register 5 */
+#define GTM_MCS2_CH4_R5 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R5*)0xF0132214u)
+
+/** \brief 32218, MCS Channel Program Counter Register 6 */
+#define GTM_MCS2_CH4_R6 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R6*)0xF0132218u)
+
+/** \brief 3221C, MCS Channel Program Counter Register 7 */
+#define GTM_MCS2_CH4_R7 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R7*)0xF013221Cu)
+
+/** \brief 322A4, MCS Channel ACB Register */
+#define GTM_MCS2_CH5_ACB /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_ACB*)0xF01322A4u)
+
+/** \brief 322A0, MCS Channel Control Register */
+#define GTM_MCS2_CH5_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_CTRL*)0xF01322A0u)
+
+/** \brief 322D4, MCS_Channel Error Interrupt Enable Register */
+#define GTM_MCS2_CH5_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_EIRQ_EN*)0xF01322D4u)
+
+/** \brief 322C8, MCS Channel Interrupt Enable Register */
+#define GTM_MCS2_CH5_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_EN*)0xF01322C8u)
+
+/** \brief 322CC, MCS Channel Software Interrupt Generation Register */
+#define GTM_MCS2_CH5_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_FORCINT*)0xF01322CCu)
+
+/** \brief 322D0, MCS IRQ Mode Configuration Register */
+#define GTM_MCS2_CH5_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_MODE*)0xF01322D0u)
+
+/** \brief 322C4, MCS Channel interrupt notification register */
+#define GTM_MCS2_CH5_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_NOTIFY*)0xF01322C4u)
+
+/** \brief 322C0, MCS Channel Program Counter Register */
+#define GTM_MCS2_CH5_PC /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_PC*)0xF01322C0u)
+
+/** \brief 32280, MCS Channel Program Counter Register 0 */
+#define GTM_MCS2_CH5_R0 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R0*)0xF0132280u)
+
+/** \brief 32284, MCS Channel Program Counter Register 1 */
+#define GTM_MCS2_CH5_R1 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R1*)0xF0132284u)
+
+/** \brief 32288, MCS Channel Program Counter Register 2 */
+#define GTM_MCS2_CH5_R2 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R2*)0xF0132288u)
+
+/** \brief 3228C, MCS Channel Program Counter Register 3 */
+#define GTM_MCS2_CH5_R3 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R3*)0xF013228Cu)
+
+/** \brief 32290, MCS Channel Program Counter Register 4 */
+#define GTM_MCS2_CH5_R4 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R4*)0xF0132290u)
+
+/** \brief 32294, MCS Channel Program Counter Register 5 */
+#define GTM_MCS2_CH5_R5 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R5*)0xF0132294u)
+
+/** \brief 32298, MCS Channel Program Counter Register 6 */
+#define GTM_MCS2_CH5_R6 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R6*)0xF0132298u)
+
+/** \brief 3229C, MCS Channel Program Counter Register 7 */
+#define GTM_MCS2_CH5_R7 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R7*)0xF013229Cu)
+
+/** \brief 32324, MCS Channel ACB Register */
+#define GTM_MCS2_CH6_ACB /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_ACB*)0xF0132324u)
+
+/** \brief 32320, MCS Channel Control Register */
+#define GTM_MCS2_CH6_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_CTRL*)0xF0132320u)
+
+/** \brief 32354, MCS_Channel Error Interrupt Enable Register */
+#define GTM_MCS2_CH6_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_EIRQ_EN*)0xF0132354u)
+
+/** \brief 32348, MCS Channel Interrupt Enable Register */
+#define GTM_MCS2_CH6_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_EN*)0xF0132348u)
+
+/** \brief 3234C, MCS Channel Software Interrupt Generation Register */
+#define GTM_MCS2_CH6_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_FORCINT*)0xF013234Cu)
+
+/** \brief 32350, MCS IRQ Mode Configuration Register */
+#define GTM_MCS2_CH6_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_MODE*)0xF0132350u)
+
+/** \brief 32344, MCS Channel interrupt notification register */
+#define GTM_MCS2_CH6_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_NOTIFY*)0xF0132344u)
+
+/** \brief 32340, MCS Channel Program Counter Register */
+#define GTM_MCS2_CH6_PC /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_PC*)0xF0132340u)
+
+/** \brief 32300, MCS Channel Program Counter Register 0 */
+#define GTM_MCS2_CH6_R0 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R0*)0xF0132300u)
+
+/** \brief 32304, MCS Channel Program Counter Register 1 */
+#define GTM_MCS2_CH6_R1 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R1*)0xF0132304u)
+
+/** \brief 32308, MCS Channel Program Counter Register 2 */
+#define GTM_MCS2_CH6_R2 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R2*)0xF0132308u)
+
+/** \brief 3230C, MCS Channel Program Counter Register 3 */
+#define GTM_MCS2_CH6_R3 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R3*)0xF013230Cu)
+
+/** \brief 32310, MCS Channel Program Counter Register 4 */
+#define GTM_MCS2_CH6_R4 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R4*)0xF0132310u)
+
+/** \brief 32314, MCS Channel Program Counter Register 5 */
+#define GTM_MCS2_CH6_R5 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R5*)0xF0132314u)
+
+/** \brief 32318, MCS Channel Program Counter Register 6 */
+#define GTM_MCS2_CH6_R6 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R6*)0xF0132318u)
+
+/** \brief 3231C, MCS Channel Program Counter Register 7 */
+#define GTM_MCS2_CH6_R7 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R7*)0xF013231Cu)
+
+/** \brief 323A4, MCS Channel ACB Register */
+#define GTM_MCS2_CH7_ACB /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_ACB*)0xF01323A4u)
+
+/** \brief 323A0, MCS Channel Control Register */
+#define GTM_MCS2_CH7_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_CTRL*)0xF01323A0u)
+
+/** \brief 323D4, MCS_Channel Error Interrupt Enable Register */
+#define GTM_MCS2_CH7_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_EIRQ_EN*)0xF01323D4u)
+
+/** \brief 323C8, MCS Channel Interrupt Enable Register */
+#define GTM_MCS2_CH7_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_EN*)0xF01323C8u)
+
+/** \brief 323CC, MCS Channel Software Interrupt Generation Register */
+#define GTM_MCS2_CH7_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_FORCINT*)0xF01323CCu)
+
+/** \brief 323D0, MCS IRQ Mode Configuration Register */
+#define GTM_MCS2_CH7_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_MODE*)0xF01323D0u)
+
+/** \brief 323C4, MCS Channel interrupt notification register */
+#define GTM_MCS2_CH7_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_IRQ_NOTIFY*)0xF01323C4u)
+
+/** \brief 323C0, MCS Channel Program Counter Register */
+#define GTM_MCS2_CH7_PC /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_PC*)0xF01323C0u)
+
+/** \brief 32380, MCS Channel Program Counter Register 0 */
+#define GTM_MCS2_CH7_R0 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R0*)0xF0132380u)
+
+/** \brief 32384, MCS Channel Program Counter Register 1 */
+#define GTM_MCS2_CH7_R1 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R1*)0xF0132384u)
+
+/** \brief 32388, MCS Channel Program Counter Register 2 */
+#define GTM_MCS2_CH7_R2 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R2*)0xF0132388u)
+
+/** \brief 3238C, MCS Channel Program Counter Register 3 */
+#define GTM_MCS2_CH7_R3 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R3*)0xF013238Cu)
+
+/** \brief 32390, MCS Channel Program Counter Register 4 */
+#define GTM_MCS2_CH7_R4 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R4*)0xF0132390u)
+
+/** \brief 32394, MCS Channel Program Counter Register 5 */
+#define GTM_MCS2_CH7_R5 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R5*)0xF0132394u)
+
+/** \brief 32398, MCS Channel Program Counter Register 6 */
+#define GTM_MCS2_CH7_R6 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R6*)0xF0132398u)
+
+/** \brief 3239C, MCS Channel Program Counter Register 7 */
+#define GTM_MCS2_CH7_R7 /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CH_R7*)0xF013239Cu)
+
+/** \brief 32074, MCS Control Register */
+#define GTM_MCS2_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_CTRL*)0xF0132074u)
+
+/** \brief 3207C, MCS Error Register */
+#define GTM_MCS2_ERR /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_ERR*)0xF013207Cu)
+
+/** \brief 32078, MCS Channel Reset Register */
+#define GTM_MCS2_RST /*lint --e(923)*/ (*(volatile Ifx_GTM_MCS_RST*)0xF0132078u)
+
+/** \brief 9FE74, MCS Interrupt Clear Register */
+#define GTM_MCSINTCLR /*lint --e(923)*/ (*(volatile Ifx_GTM_MCSINTCLR*)0xF019FE74u)
+
+/** \brief 9FE70, MCS Interrupt Status Register */
+#define GTM_MCSINTSTAT /*lint --e(923)*/ (*(volatile Ifx_GTM_MCSINTSTAT*)0xF019FE70u)
+
+/** \brief 184, Monitor Activity Register 0 */
+#define GTM_MON_ACTIVITY_0 /*lint --e(923)*/ (*(volatile Ifx_GTM_MON_ACTIVITY_0*)0xF0100184u)
+
+/** \brief 180, Monitor Status Register */
+#define GTM_MON_STATUS /*lint --e(923)*/ (*(volatile Ifx_GTM_MON_STATUS*)0xF0100180u)
+
+/** \brief 9FF70, MSC0 Input Low Extended Control Register */
+#define GTM_MSC0INLEXTCON /*lint --e(923)*/ (*(volatile Ifx_GTM_MSC0INLEXTCON*)0xF019FF70u)
+
+/** \brief 9FF64, MSC Input High Control Register */
+#define GTM_MSCIN0_INHCON /*lint --e(923)*/ (*(volatile Ifx_GTM_MSCIN_INHCON*)0xF019FF64u)
+
+/** Alias (User Manual Name) for GTM_MSCIN0_INHCON.
+* To use register names with standard convension, please use GTM_MSCIN0_INHCON.
+*/
+#define GTM_MSC0INHCON (GTM_MSCIN0_INHCON)
+
+/** \brief 9FF60, MSC Input Low Control Register */
+#define GTM_MSCIN0_INLCON /*lint --e(923)*/ (*(volatile Ifx_GTM_MSCIN_INLCON*)0xF019FF60u)
+
+/** Alias (User Manual Name) for GTM_MSCIN0_INLCON.
+* To use register names with standard convension, please use GTM_MSCIN0_INLCON.
+*/
+#define GTM_MSC0INLCON (GTM_MSCIN0_INLCON)
+
+/** \brief 9FF6C, MSC Input High Control Register */
+#define GTM_MSCIN1_INHCON /*lint --e(923)*/ (*(volatile Ifx_GTM_MSCIN_INHCON*)0xF019FF6Cu)
+
+/** Alias (User Manual Name) for GTM_MSCIN1_INHCON.
+* To use register names with standard convension, please use GTM_MSCIN1_INHCON.
+*/
+#define GTM_MSC1INHCON (GTM_MSCIN1_INHCON)
+
+/** \brief 9FF68, MSC Input Low Control Register */
+#define GTM_MSCIN1_INLCON /*lint --e(923)*/ (*(volatile Ifx_GTM_MSCIN_INLCON*)0xF019FF68u)
+
+/** Alias (User Manual Name) for GTM_MSCIN1_INLCON.
+* To use register names with standard convension, please use GTM_MSCIN1_INLCON.
+*/
+#define GTM_MSC1INLCON (GTM_MSCIN1_INLCON)
+
+/** \brief 9FF00, MSC Set Control 0 Register */
+#define GTM_MSCSET_1S0_CON0 /*lint --e(923)*/ (*(volatile Ifx_GTM_MSCSET_CON0*)0xF019FF00u)
+
+/** Alias (User Manual Name) for GTM_MSCSET_1S0_CON0.
+* To use register names with standard convension, please use GTM_MSCSET_1S0_CON0.
+*/
+#define GTM_MSCSET1CON0 (GTM_MSCSET_1S0_CON0)
+
+/** \brief 9FF04, MSC Set Control 1 Register */
+#define GTM_MSCSET_1S0_CON1 /*lint --e(923)*/ (*(volatile Ifx_GTM_MSCSET_CON1*)0xF019FF04u)
+
+/** Alias (User Manual Name) for GTM_MSCSET_1S0_CON1.
+* To use register names with standard convension, please use GTM_MSCSET_1S0_CON1.
+*/
+#define GTM_MSCSET1CON1 (GTM_MSCSET_1S0_CON1)
+
+/** \brief 9FF08, MSC Set Control 2 Register */
+#define GTM_MSCSET_1S0_CON2 /*lint --e(923)*/ (*(volatile Ifx_GTM_MSCSET_CON2*)0xF019FF08u)
+
+/** Alias (User Manual Name) for GTM_MSCSET_1S0_CON2.
+* To use register names with standard convension, please use GTM_MSCSET_1S0_CON2.
+*/
+#define GTM_MSCSET1CON2 (GTM_MSCSET_1S0_CON2)
+
+/** \brief 9FF0C, MSC Set Control 3 Register */
+#define GTM_MSCSET_1S0_CON3 /*lint --e(923)*/ (*(volatile Ifx_GTM_MSCSET_CON3*)0xF019FF0Cu)
+
+/** Alias (User Manual Name) for GTM_MSCSET_1S0_CON3.
+* To use register names with standard convension, please use GTM_MSCSET_1S0_CON3.
+*/
+#define GTM_MSCSET1CON3 (GTM_MSCSET_1S0_CON3)
+
+/** \brief 9FF10, MSC Set Control 0 Register */
+#define GTM_MSCSET_1S1_CON0 /*lint --e(923)*/ (*(volatile Ifx_GTM_MSCSET_CON0*)0xF019FF10u)
+
+/** Alias (User Manual Name) for GTM_MSCSET_1S1_CON0.
+* To use register names with standard convension, please use GTM_MSCSET_1S1_CON0.
+*/
+#define GTM_MSCSET2CON0 (GTM_MSCSET_1S1_CON0)
+
+/** \brief 9FF14, MSC Set Control 1 Register */
+#define GTM_MSCSET_1S1_CON1 /*lint --e(923)*/ (*(volatile Ifx_GTM_MSCSET_CON1*)0xF019FF14u)
+
+/** Alias (User Manual Name) for GTM_MSCSET_1S1_CON1.
+* To use register names with standard convension, please use GTM_MSCSET_1S1_CON1.
+*/
+#define GTM_MSCSET2CON1 (GTM_MSCSET_1S1_CON1)
+
+/** \brief 9FF18, MSC Set Control 2 Register */
+#define GTM_MSCSET_1S1_CON2 /*lint --e(923)*/ (*(volatile Ifx_GTM_MSCSET_CON2*)0xF019FF18u)
+
+/** Alias (User Manual Name) for GTM_MSCSET_1S1_CON2.
+* To use register names with standard convension, please use GTM_MSCSET_1S1_CON2.
+*/
+#define GTM_MSCSET2CON2 (GTM_MSCSET_1S1_CON2)
+
+/** \brief 9FF1C, MSC Set Control 3 Register */
+#define GTM_MSCSET_1S1_CON3 /*lint --e(923)*/ (*(volatile Ifx_GTM_MSCSET_CON3*)0xF019FF1Cu)
+
+/** Alias (User Manual Name) for GTM_MSCSET_1S1_CON3.
+* To use register names with standard convension, please use GTM_MSCSET_1S1_CON3.
+*/
+#define GTM_MSCSET2CON3 (GTM_MSCSET_1S1_CON3)
+
+/** \brief 9FF20, MSC Set Control 0 Register */
+#define GTM_MSCSET_1S2_CON0 /*lint --e(923)*/ (*(volatile Ifx_GTM_MSCSET_CON0*)0xF019FF20u)
+
+/** Alias (User Manual Name) for GTM_MSCSET_1S2_CON0.
+* To use register names with standard convension, please use GTM_MSCSET_1S2_CON0.
+*/
+#define GTM_MSCSET3CON0 (GTM_MSCSET_1S2_CON0)
+
+/** \brief 9FF24, MSC Set Control 1 Register */
+#define GTM_MSCSET_1S2_CON1 /*lint --e(923)*/ (*(volatile Ifx_GTM_MSCSET_CON1*)0xF019FF24u)
+
+/** Alias (User Manual Name) for GTM_MSCSET_1S2_CON1.
+* To use register names with standard convension, please use GTM_MSCSET_1S2_CON1.
+*/
+#define GTM_MSCSET3CON1 (GTM_MSCSET_1S2_CON1)
+
+/** \brief 9FF28, MSC Set Control 2 Register */
+#define GTM_MSCSET_1S2_CON2 /*lint --e(923)*/ (*(volatile Ifx_GTM_MSCSET_CON2*)0xF019FF28u)
+
+/** Alias (User Manual Name) for GTM_MSCSET_1S2_CON2.
+* To use register names with standard convension, please use GTM_MSCSET_1S2_CON2.
+*/
+#define GTM_MSCSET3CON2 (GTM_MSCSET_1S2_CON2)
+
+/** \brief 9FF2C, MSC Set Control 3 Register */
+#define GTM_MSCSET_1S2_CON3 /*lint --e(923)*/ (*(volatile Ifx_GTM_MSCSET_CON3*)0xF019FF2Cu)
+
+/** Alias (User Manual Name) for GTM_MSCSET_1S2_CON3.
+* To use register names with standard convension, please use GTM_MSCSET_1S2_CON3.
+*/
+#define GTM_MSCSET3CON3 (GTM_MSCSET_1S2_CON3)
+
+/** \brief 9FF30, MSC Set Control 0 Register */
+#define GTM_MSCSET_1S3_CON0 /*lint --e(923)*/ (*(volatile Ifx_GTM_MSCSET_CON0*)0xF019FF30u)
+
+/** Alias (User Manual Name) for GTM_MSCSET_1S3_CON0.
+* To use register names with standard convension, please use GTM_MSCSET_1S3_CON0.
+*/
+#define GTM_MSCSET4CON0 (GTM_MSCSET_1S3_CON0)
+
+/** \brief 9FF34, MSC Set Control 1 Register */
+#define GTM_MSCSET_1S3_CON1 /*lint --e(923)*/ (*(volatile Ifx_GTM_MSCSET_CON1*)0xF019FF34u)
+
+/** Alias (User Manual Name) for GTM_MSCSET_1S3_CON1.
+* To use register names with standard convension, please use GTM_MSCSET_1S3_CON1.
+*/
+#define GTM_MSCSET4CON1 (GTM_MSCSET_1S3_CON1)
+
+/** \brief 9FF38, MSC Set Control 2 Register */
+#define GTM_MSCSET_1S3_CON2 /*lint --e(923)*/ (*(volatile Ifx_GTM_MSCSET_CON2*)0xF019FF38u)
+
+/** Alias (User Manual Name) for GTM_MSCSET_1S3_CON2.
+* To use register names with standard convension, please use GTM_MSCSET_1S3_CON2.
+*/
+#define GTM_MSCSET4CON2 (GTM_MSCSET_1S3_CON2)
+
+/** \brief 9FF3C, MSC Set Control 3 Register */
+#define GTM_MSCSET_1S3_CON3 /*lint --e(923)*/ (*(volatile Ifx_GTM_MSCSET_CON3*)0xF019FF3Cu)
+
+/** Alias (User Manual Name) for GTM_MSCSET_1S3_CON3.
+* To use register names with standard convension, please use GTM_MSCSET_1S3_CON3.
+*/
+#define GTM_MSCSET4CON3 (GTM_MSCSET_1S3_CON3)
+
+/** \brief 9FDE8, OCDS Control and Status */
+#define GTM_OCS /*lint --e(923)*/ (*(volatile Ifx_GTM_OCS*)0xF019FDE8u)
+
+/** \brief 9FDDC, OCDS Debug Access Register */
+#define GTM_ODA /*lint --e(923)*/ (*(volatile Ifx_GTM_ODA*)0xF019FDDCu)
+
+/** \brief 9FDC4, OCDS TBU0 Trigger Register */
+#define GTM_OTBU0T /*lint --e(923)*/ (*(volatile Ifx_GTM_OTBU0T*)0xF019FDC4u)
+
+/** \brief 9FDC8, OCDS TBU1 Trigger Register */
+#define GTM_OTBU1T /*lint --e(923)*/ (*(volatile Ifx_GTM_OTBU1T*)0xF019FDC8u)
+
+/** \brief 9FDCC, OCDS TBU2 Trigger Register */
+#define GTM_OTBU2T /*lint --e(923)*/ (*(volatile Ifx_GTM_OTBU2T*)0xF019FDCCu)
+
+/** \brief 9FDD4, OCDS Trigger Set Control 0 Register */
+#define GTM_OTSC0 /*lint --e(923)*/ (*(volatile Ifx_GTM_OTSC0*)0xF019FDD4u)
+
+/** \brief 9FDD8, OCDS Trigger Set Control 1 Register */
+#define GTM_OTSC1 /*lint --e(923)*/ (*(volatile Ifx_GTM_OTSC1*)0xF019FDD8u)
+
+/** \brief 9FDD0, OCDS Trigger Set Select Register */
+#define GTM_OTSS /*lint --e(923)*/ (*(volatile Ifx_GTM_OTSS*)0xF019FDD0u)
+
+/** \brief 0, GTM Version Control Register */
+#define GTM_REV /*lint --e(923)*/ (*(volatile Ifx_GTM_REV*)0xF0100000u)
+
+/** \brief 4, GTM Global Reset Register */
+#define GTM_RST /*lint --e(923)*/ (*(volatile Ifx_GTM_RST*)0xF0100004u)
+
+/** \brief 844, SPE Revolution Compare Register */
+#define GTM_SPE0_CMP /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_CMP*)0xF0100844u)
+
+/** \brief 840, SPE Revolution Counter Register */
+#define GTM_SPE0_CNT /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_CNT*)0xF0100840u)
+
+/** \brief 800, SPE Control Status Register */
+#define GTM_SPE0_CTRL_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_CTRL_STAT*)0xF0100800u)
+
+/** \brief 83C, SPE Error Interrupt Enable Register */
+#define GTM_SPE0_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_EIRQ_EN*)0xF010083Cu)
+
+/** \brief 830, SPE Interrupt Enable Register */
+#define GTM_SPE0_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_IRQ_EN*)0xF0100830u)
+
+/** \brief 834, SPE Interrupt Generation by Software */
+#define GTM_SPE0_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_IRQ_FORCINT*)0xF0100834u)
+
+/** \brief 838, SPE IRQ Mode Configuration Register */
+#define GTM_SPE0_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_IRQ_MODE*)0xF0100838u)
+
+/** \brief 82C, SPE Interrupt Notification Register */
+#define GTM_SPE0_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_IRQ_NOTIFY*)0xF010082Cu)
+
+/** \brief 828, SPE Output Control Register */
+#define GTM_SPE0_OUT_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_OUT_CTRL*)0xF0100828u)
+
+/** \brief 808, SPE Output Definition Register */
+#define GTM_SPE0_OUT_PAT0 /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_OUT_PAT*)0xF0100808u)
+
+/** \brief 80C, SPE Output Definition Register */
+#define GTM_SPE0_OUT_PAT1 /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_OUT_PAT*)0xF010080Cu)
+
+/** \brief 810, SPE Output Definition Register */
+#define GTM_SPE0_OUT_PAT2 /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_OUT_PAT*)0xF0100810u)
+
+/** \brief 814, SPE Output Definition Register */
+#define GTM_SPE0_OUT_PAT3 /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_OUT_PAT*)0xF0100814u)
+
+/** \brief 818, SPE Output Definition Register */
+#define GTM_SPE0_OUT_PAT4 /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_OUT_PAT*)0xF0100818u)
+
+/** \brief 81C, SPE Output Definition Register */
+#define GTM_SPE0_OUT_PAT5 /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_OUT_PAT*)0xF010081Cu)
+
+/** \brief 820, SPE Output Definition Register */
+#define GTM_SPE0_OUT_PAT6 /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_OUT_PAT*)0xF0100820u)
+
+/** \brief 824, SPE Output Definition Register */
+#define GTM_SPE0_OUT_PAT7 /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_OUT_PAT*)0xF0100824u)
+
+/** \brief 804, SPE Input Pattern Definition Register */
+#define GTM_SPE0_PAT /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_PAT*)0xF0100804u)
+
+/** \brief 8C4, SPE Revolution Compare Register */
+#define GTM_SPE1_CMP /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_CMP*)0xF01008C4u)
+
+/** \brief 8C0, SPE Revolution Counter Register */
+#define GTM_SPE1_CNT /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_CNT*)0xF01008C0u)
+
+/** \brief 880, SPE Control Status Register */
+#define GTM_SPE1_CTRL_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_CTRL_STAT*)0xF0100880u)
+
+/** \brief 8BC, SPE Error Interrupt Enable Register */
+#define GTM_SPE1_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_EIRQ_EN*)0xF01008BCu)
+
+/** \brief 8B0, SPE Interrupt Enable Register */
+#define GTM_SPE1_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_IRQ_EN*)0xF01008B0u)
+
+/** \brief 8B4, SPE Interrupt Generation by Software */
+#define GTM_SPE1_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_IRQ_FORCINT*)0xF01008B4u)
+
+/** \brief 8B8, SPE IRQ Mode Configuration Register */
+#define GTM_SPE1_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_IRQ_MODE*)0xF01008B8u)
+
+/** \brief 8AC, SPE Interrupt Notification Register */
+#define GTM_SPE1_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_IRQ_NOTIFY*)0xF01008ACu)
+
+/** \brief 8A8, SPE Output Control Register */
+#define GTM_SPE1_OUT_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_OUT_CTRL*)0xF01008A8u)
+
+/** \brief 888, SPE Output Definition Register */
+#define GTM_SPE1_OUT_PAT0 /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_OUT_PAT*)0xF0100888u)
+
+/** \brief 88C, SPE Output Definition Register */
+#define GTM_SPE1_OUT_PAT1 /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_OUT_PAT*)0xF010088Cu)
+
+/** \brief 890, SPE Output Definition Register */
+#define GTM_SPE1_OUT_PAT2 /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_OUT_PAT*)0xF0100890u)
+
+/** \brief 894, SPE Output Definition Register */
+#define GTM_SPE1_OUT_PAT3 /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_OUT_PAT*)0xF0100894u)
+
+/** \brief 898, SPE Output Definition Register */
+#define GTM_SPE1_OUT_PAT4 /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_OUT_PAT*)0xF0100898u)
+
+/** \brief 89C, SPE Output Definition Register */
+#define GTM_SPE1_OUT_PAT5 /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_OUT_PAT*)0xF010089Cu)
+
+/** \brief 8A0, SPE Output Definition Register */
+#define GTM_SPE1_OUT_PAT6 /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_OUT_PAT*)0xF01008A0u)
+
+/** \brief 8A4, SPE Output Definition Register */
+#define GTM_SPE1_OUT_PAT7 /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_OUT_PAT*)0xF01008A4u)
+
+/** \brief 884, SPE Input Pattern Definition Register */
+#define GTM_SPE1_PAT /*lint --e(923)*/ (*(volatile Ifx_GTM_SPE_PAT*)0xF0100884u)
+
+/** \brief 108, TBU Channel 0 Base Register */
+#define GTM_TBU_CH0_BASE /*lint --e(923)*/ (*(volatile Ifx_GTM_TBU_CH0_BASE*)0xF0100108u)
+
+/** \brief 104, TBU Channel 0 Control Register */
+#define GTM_TBU_CH0_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TBU_CH0_CTRL*)0xF0100104u)
+
+/** \brief 110, TBU Channel 1 Base Register */
+#define GTM_TBU_CH1_BASE /*lint --e(923)*/ (*(volatile Ifx_GTM_TBU_CH1_BASE*)0xF0100110u)
+
+/** \brief 10C, TBU Channel 1 Control Register */
+#define GTM_TBU_CH1_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TBU_CH1_CTRL*)0xF010010Cu)
+
+/** \brief 118, TBU Channel 2 Base Register */
+#define GTM_TBU_CH2_BASE /*lint --e(923)*/ (*(volatile Ifx_GTM_TBU_CH2_BASE*)0xF0100118u)
+
+/** \brief 114, TBU Channel 2 Control Register */
+#define GTM_TBU_CH2_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TBU_CH2_CTRL*)0xF0100114u)
+
+/** \brief 100, TBU Global Channel Enable Register */
+#define GTM_TBU_CHEN /*lint --e(923)*/ (*(volatile Ifx_GTM_TBU_CHEN*)0xF0100100u)
+
+/** \brief 1008, TIM Channel SMU Counter Register */
+#define GTM_TIM0_CH0_CNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNT*)0xF0101008u)
+
+/** \brief 1010, TIM Channel SMU Shadow Counter Register */
+#define GTM_TIM0_CH0_CNTS /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNTS*)0xF0101010u)
+
+/** \brief 1024, TIM Channel Control Register */
+#define GTM_TIM0_CH0_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CTRL*)0xF0101024u)
+
+/** \brief 100C, TIM Channel Edge Counter Register */
+#define GTM_TIM0_CH0_ECNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECNT*)0xF010100Cu)
+
+/** \brief 1028, TIM Channel External Capture Control Register */
+#define GTM_TIM0_CH0_ECTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECTRL*)0xF0101028u)
+
+/** \brief 103C, TIM Channel Error Interrupt Enable Register */
+#define GTM_TIM0_CH0_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_EIRQ_EN*)0xF010103Cu)
+
+/** \brief 1020, TIM Channel Filter Parameter 1 Register */
+#define GTM_TIM0_CH0_FLT_FE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_FE*)0xF0101020u)
+
+/** \brief 101C, GTM_TIM Channel Filter Parameter 0 Register */
+#define GTM_TIM0_CH0_FLT_RE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_RE*)0xF010101Cu)
+
+/** \brief 1000, TIM Channel General Purpose 0 Register */
+#define GTM_TIM0_CH0_GPR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR0*)0xF0101000u)
+
+/** \brief 1004, TIM Channel General Purpose 1 Register */
+#define GTM_TIM0_CH0_GPR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR1*)0xF0101004u)
+
+/** \brief 1030, TIM Channel Interrupt Enable Register */
+#define GTM_TIM0_CH0_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_EN*)0xF0101030u)
+
+/** \brief 1034, TIM Channel Software Interrupt Force Register */
+#define GTM_TIM0_CH0_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_FORCINT*)0xF0101034u)
+
+/** \brief 1038, TIM IRQ Mode Configuration Register */
+#define GTM_TIM0_CH0_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_MODE*)0xF0101038u)
+
+/** \brief 102C, TIM Channel Interrupt Notification Register */
+#define GTM_TIM0_CH0_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_NOTIFY*)0xF010102Cu)
+
+/** \brief 1014, TIM Channel TDUC Register */
+#define GTM_TIM0_CH0_TDUC /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUC*)0xF0101014u)
+
+/** \brief 1018, TIM Channel TDUV Register */
+#define GTM_TIM0_CH0_TDUV /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUV*)0xF0101018u)
+
+/** \brief 1088, TIM Channel SMU Counter Register */
+#define GTM_TIM0_CH1_CNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNT*)0xF0101088u)
+
+/** \brief 1090, TIM Channel SMU Shadow Counter Register */
+#define GTM_TIM0_CH1_CNTS /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNTS*)0xF0101090u)
+
+/** \brief 10A4, TIM Channel Control Register */
+#define GTM_TIM0_CH1_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CTRL*)0xF01010A4u)
+
+/** \brief 108C, TIM Channel Edge Counter Register */
+#define GTM_TIM0_CH1_ECNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECNT*)0xF010108Cu)
+
+/** \brief 10A8, TIM Channel External Capture Control Register */
+#define GTM_TIM0_CH1_ECTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECTRL*)0xF01010A8u)
+
+/** \brief 10BC, TIM Channel Error Interrupt Enable Register */
+#define GTM_TIM0_CH1_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_EIRQ_EN*)0xF01010BCu)
+
+/** \brief 10A0, TIM Channel Filter Parameter 1 Register */
+#define GTM_TIM0_CH1_FLT_FE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_FE*)0xF01010A0u)
+
+/** \brief 109C, GTM_TIM Channel Filter Parameter 0 Register */
+#define GTM_TIM0_CH1_FLT_RE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_RE*)0xF010109Cu)
+
+/** \brief 1080, TIM Channel General Purpose 0 Register */
+#define GTM_TIM0_CH1_GPR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR0*)0xF0101080u)
+
+/** \brief 1084, TIM Channel General Purpose 1 Register */
+#define GTM_TIM0_CH1_GPR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR1*)0xF0101084u)
+
+/** \brief 10B0, TIM Channel Interrupt Enable Register */
+#define GTM_TIM0_CH1_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_EN*)0xF01010B0u)
+
+/** \brief 10B4, TIM Channel Software Interrupt Force Register */
+#define GTM_TIM0_CH1_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_FORCINT*)0xF01010B4u)
+
+/** \brief 10B8, TIM IRQ Mode Configuration Register */
+#define GTM_TIM0_CH1_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_MODE*)0xF01010B8u)
+
+/** \brief 10AC, TIM Channel Interrupt Notification Register */
+#define GTM_TIM0_CH1_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_NOTIFY*)0xF01010ACu)
+
+/** \brief 1094, TIM Channel TDUC Register */
+#define GTM_TIM0_CH1_TDUC /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUC*)0xF0101094u)
+
+/** \brief 1098, TIM Channel TDUV Register */
+#define GTM_TIM0_CH1_TDUV /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUV*)0xF0101098u)
+
+/** \brief 1108, TIM Channel SMU Counter Register */
+#define GTM_TIM0_CH2_CNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNT*)0xF0101108u)
+
+/** \brief 1110, TIM Channel SMU Shadow Counter Register */
+#define GTM_TIM0_CH2_CNTS /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNTS*)0xF0101110u)
+
+/** \brief 1124, TIM Channel Control Register */
+#define GTM_TIM0_CH2_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CTRL*)0xF0101124u)
+
+/** \brief 110C, TIM Channel Edge Counter Register */
+#define GTM_TIM0_CH2_ECNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECNT*)0xF010110Cu)
+
+/** \brief 1128, TIM Channel External Capture Control Register */
+#define GTM_TIM0_CH2_ECTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECTRL*)0xF0101128u)
+
+/** \brief 113C, TIM Channel Error Interrupt Enable Register */
+#define GTM_TIM0_CH2_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_EIRQ_EN*)0xF010113Cu)
+
+/** \brief 1120, TIM Channel Filter Parameter 1 Register */
+#define GTM_TIM0_CH2_FLT_FE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_FE*)0xF0101120u)
+
+/** \brief 111C, GTM_TIM Channel Filter Parameter 0 Register */
+#define GTM_TIM0_CH2_FLT_RE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_RE*)0xF010111Cu)
+
+/** \brief 1100, TIM Channel General Purpose 0 Register */
+#define GTM_TIM0_CH2_GPR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR0*)0xF0101100u)
+
+/** \brief 1104, TIM Channel General Purpose 1 Register */
+#define GTM_TIM0_CH2_GPR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR1*)0xF0101104u)
+
+/** \brief 1130, TIM Channel Interrupt Enable Register */
+#define GTM_TIM0_CH2_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_EN*)0xF0101130u)
+
+/** \brief 1134, TIM Channel Software Interrupt Force Register */
+#define GTM_TIM0_CH2_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_FORCINT*)0xF0101134u)
+
+/** \brief 1138, TIM IRQ Mode Configuration Register */
+#define GTM_TIM0_CH2_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_MODE*)0xF0101138u)
+
+/** \brief 112C, TIM Channel Interrupt Notification Register */
+#define GTM_TIM0_CH2_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_NOTIFY*)0xF010112Cu)
+
+/** \brief 1114, TIM Channel TDUC Register */
+#define GTM_TIM0_CH2_TDUC /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUC*)0xF0101114u)
+
+/** \brief 1118, TIM Channel TDUV Register */
+#define GTM_TIM0_CH2_TDUV /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUV*)0xF0101118u)
+
+/** \brief 1188, TIM Channel SMU Counter Register */
+#define GTM_TIM0_CH3_CNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNT*)0xF0101188u)
+
+/** \brief 1190, TIM Channel SMU Shadow Counter Register */
+#define GTM_TIM0_CH3_CNTS /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNTS*)0xF0101190u)
+
+/** \brief 11A4, TIM Channel Control Register */
+#define GTM_TIM0_CH3_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CTRL*)0xF01011A4u)
+
+/** \brief 118C, TIM Channel Edge Counter Register */
+#define GTM_TIM0_CH3_ECNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECNT*)0xF010118Cu)
+
+/** \brief 11A8, TIM Channel External Capture Control Register */
+#define GTM_TIM0_CH3_ECTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECTRL*)0xF01011A8u)
+
+/** \brief 11BC, TIM Channel Error Interrupt Enable Register */
+#define GTM_TIM0_CH3_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_EIRQ_EN*)0xF01011BCu)
+
+/** \brief 11A0, TIM Channel Filter Parameter 1 Register */
+#define GTM_TIM0_CH3_FLT_FE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_FE*)0xF01011A0u)
+
+/** \brief 119C, GTM_TIM Channel Filter Parameter 0 Register */
+#define GTM_TIM0_CH3_FLT_RE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_RE*)0xF010119Cu)
+
+/** \brief 1180, TIM Channel General Purpose 0 Register */
+#define GTM_TIM0_CH3_GPR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR0*)0xF0101180u)
+
+/** \brief 1184, TIM Channel General Purpose 1 Register */
+#define GTM_TIM0_CH3_GPR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR1*)0xF0101184u)
+
+/** \brief 11B0, TIM Channel Interrupt Enable Register */
+#define GTM_TIM0_CH3_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_EN*)0xF01011B0u)
+
+/** \brief 11B4, TIM Channel Software Interrupt Force Register */
+#define GTM_TIM0_CH3_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_FORCINT*)0xF01011B4u)
+
+/** \brief 11B8, TIM IRQ Mode Configuration Register */
+#define GTM_TIM0_CH3_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_MODE*)0xF01011B8u)
+
+/** \brief 11AC, TIM Channel Interrupt Notification Register */
+#define GTM_TIM0_CH3_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_NOTIFY*)0xF01011ACu)
+
+/** \brief 1194, TIM Channel TDUC Register */
+#define GTM_TIM0_CH3_TDUC /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUC*)0xF0101194u)
+
+/** \brief 1198, TIM Channel TDUV Register */
+#define GTM_TIM0_CH3_TDUV /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUV*)0xF0101198u)
+
+/** \brief 1208, TIM Channel SMU Counter Register */
+#define GTM_TIM0_CH4_CNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNT*)0xF0101208u)
+
+/** \brief 1210, TIM Channel SMU Shadow Counter Register */
+#define GTM_TIM0_CH4_CNTS /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNTS*)0xF0101210u)
+
+/** \brief 1224, TIM Channel Control Register */
+#define GTM_TIM0_CH4_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CTRL*)0xF0101224u)
+
+/** \brief 120C, TIM Channel Edge Counter Register */
+#define GTM_TIM0_CH4_ECNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECNT*)0xF010120Cu)
+
+/** \brief 1228, TIM Channel External Capture Control Register */
+#define GTM_TIM0_CH4_ECTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECTRL*)0xF0101228u)
+
+/** \brief 123C, TIM Channel Error Interrupt Enable Register */
+#define GTM_TIM0_CH4_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_EIRQ_EN*)0xF010123Cu)
+
+/** \brief 1220, TIM Channel Filter Parameter 1 Register */
+#define GTM_TIM0_CH4_FLT_FE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_FE*)0xF0101220u)
+
+/** \brief 121C, GTM_TIM Channel Filter Parameter 0 Register */
+#define GTM_TIM0_CH4_FLT_RE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_RE*)0xF010121Cu)
+
+/** \brief 1200, TIM Channel General Purpose 0 Register */
+#define GTM_TIM0_CH4_GPR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR0*)0xF0101200u)
+
+/** \brief 1204, TIM Channel General Purpose 1 Register */
+#define GTM_TIM0_CH4_GPR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR1*)0xF0101204u)
+
+/** \brief 1230, TIM Channel Interrupt Enable Register */
+#define GTM_TIM0_CH4_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_EN*)0xF0101230u)
+
+/** \brief 1234, TIM Channel Software Interrupt Force Register */
+#define GTM_TIM0_CH4_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_FORCINT*)0xF0101234u)
+
+/** \brief 1238, TIM IRQ Mode Configuration Register */
+#define GTM_TIM0_CH4_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_MODE*)0xF0101238u)
+
+/** \brief 122C, TIM Channel Interrupt Notification Register */
+#define GTM_TIM0_CH4_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_NOTIFY*)0xF010122Cu)
+
+/** \brief 1214, TIM Channel TDUC Register */
+#define GTM_TIM0_CH4_TDUC /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUC*)0xF0101214u)
+
+/** \brief 1218, TIM Channel TDUV Register */
+#define GTM_TIM0_CH4_TDUV /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUV*)0xF0101218u)
+
+/** \brief 1288, TIM Channel SMU Counter Register */
+#define GTM_TIM0_CH5_CNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNT*)0xF0101288u)
+
+/** \brief 1290, TIM Channel SMU Shadow Counter Register */
+#define GTM_TIM0_CH5_CNTS /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNTS*)0xF0101290u)
+
+/** \brief 12A4, TIM Channel Control Register */
+#define GTM_TIM0_CH5_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CTRL*)0xF01012A4u)
+
+/** \brief 128C, TIM Channel Edge Counter Register */
+#define GTM_TIM0_CH5_ECNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECNT*)0xF010128Cu)
+
+/** \brief 12A8, TIM Channel External Capture Control Register */
+#define GTM_TIM0_CH5_ECTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECTRL*)0xF01012A8u)
+
+/** \brief 12BC, TIM Channel Error Interrupt Enable Register */
+#define GTM_TIM0_CH5_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_EIRQ_EN*)0xF01012BCu)
+
+/** \brief 12A0, TIM Channel Filter Parameter 1 Register */
+#define GTM_TIM0_CH5_FLT_FE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_FE*)0xF01012A0u)
+
+/** \brief 129C, GTM_TIM Channel Filter Parameter 0 Register */
+#define GTM_TIM0_CH5_FLT_RE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_RE*)0xF010129Cu)
+
+/** \brief 1280, TIM Channel General Purpose 0 Register */
+#define GTM_TIM0_CH5_GPR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR0*)0xF0101280u)
+
+/** \brief 1284, TIM Channel General Purpose 1 Register */
+#define GTM_TIM0_CH5_GPR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR1*)0xF0101284u)
+
+/** \brief 12B0, TIM Channel Interrupt Enable Register */
+#define GTM_TIM0_CH5_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_EN*)0xF01012B0u)
+
+/** \brief 12B4, TIM Channel Software Interrupt Force Register */
+#define GTM_TIM0_CH5_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_FORCINT*)0xF01012B4u)
+
+/** \brief 12B8, TIM IRQ Mode Configuration Register */
+#define GTM_TIM0_CH5_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_MODE*)0xF01012B8u)
+
+/** \brief 12AC, TIM Channel Interrupt Notification Register */
+#define GTM_TIM0_CH5_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_NOTIFY*)0xF01012ACu)
+
+/** \brief 1294, TIM Channel TDUC Register */
+#define GTM_TIM0_CH5_TDUC /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUC*)0xF0101294u)
+
+/** \brief 1298, TIM Channel TDUV Register */
+#define GTM_TIM0_CH5_TDUV /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUV*)0xF0101298u)
+
+/** \brief 1308, TIM Channel SMU Counter Register */
+#define GTM_TIM0_CH6_CNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNT*)0xF0101308u)
+
+/** \brief 1310, TIM Channel SMU Shadow Counter Register */
+#define GTM_TIM0_CH6_CNTS /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNTS*)0xF0101310u)
+
+/** \brief 1324, TIM Channel Control Register */
+#define GTM_TIM0_CH6_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CTRL*)0xF0101324u)
+
+/** \brief 130C, TIM Channel Edge Counter Register */
+#define GTM_TIM0_CH6_ECNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECNT*)0xF010130Cu)
+
+/** \brief 1328, TIM Channel External Capture Control Register */
+#define GTM_TIM0_CH6_ECTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECTRL*)0xF0101328u)
+
+/** \brief 133C, TIM Channel Error Interrupt Enable Register */
+#define GTM_TIM0_CH6_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_EIRQ_EN*)0xF010133Cu)
+
+/** \brief 1320, TIM Channel Filter Parameter 1 Register */
+#define GTM_TIM0_CH6_FLT_FE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_FE*)0xF0101320u)
+
+/** \brief 131C, GTM_TIM Channel Filter Parameter 0 Register */
+#define GTM_TIM0_CH6_FLT_RE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_RE*)0xF010131Cu)
+
+/** \brief 1300, TIM Channel General Purpose 0 Register */
+#define GTM_TIM0_CH6_GPR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR0*)0xF0101300u)
+
+/** \brief 1304, TIM Channel General Purpose 1 Register */
+#define GTM_TIM0_CH6_GPR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR1*)0xF0101304u)
+
+/** \brief 1330, TIM Channel Interrupt Enable Register */
+#define GTM_TIM0_CH6_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_EN*)0xF0101330u)
+
+/** \brief 1334, TIM Channel Software Interrupt Force Register */
+#define GTM_TIM0_CH6_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_FORCINT*)0xF0101334u)
+
+/** \brief 1338, TIM IRQ Mode Configuration Register */
+#define GTM_TIM0_CH6_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_MODE*)0xF0101338u)
+
+/** \brief 132C, TIM Channel Interrupt Notification Register */
+#define GTM_TIM0_CH6_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_NOTIFY*)0xF010132Cu)
+
+/** \brief 1314, TIM Channel TDUC Register */
+#define GTM_TIM0_CH6_TDUC /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUC*)0xF0101314u)
+
+/** \brief 1318, TIM Channel TDUV Register */
+#define GTM_TIM0_CH6_TDUV /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUV*)0xF0101318u)
+
+/** \brief 1388, TIM Channel SMU Counter Register */
+#define GTM_TIM0_CH7_CNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNT*)0xF0101388u)
+
+/** \brief 1390, TIM Channel SMU Shadow Counter Register */
+#define GTM_TIM0_CH7_CNTS /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNTS*)0xF0101390u)
+
+/** \brief 13A4, TIM Channel Control Register */
+#define GTM_TIM0_CH7_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CTRL*)0xF01013A4u)
+
+/** \brief 138C, TIM Channel Edge Counter Register */
+#define GTM_TIM0_CH7_ECNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECNT*)0xF010138Cu)
+
+/** \brief 13A8, TIM Channel External Capture Control Register */
+#define GTM_TIM0_CH7_ECTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECTRL*)0xF01013A8u)
+
+/** \brief 13BC, TIM Channel Error Interrupt Enable Register */
+#define GTM_TIM0_CH7_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_EIRQ_EN*)0xF01013BCu)
+
+/** \brief 13A0, TIM Channel Filter Parameter 1 Register */
+#define GTM_TIM0_CH7_FLT_FE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_FE*)0xF01013A0u)
+
+/** \brief 139C, GTM_TIM Channel Filter Parameter 0 Register */
+#define GTM_TIM0_CH7_FLT_RE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_RE*)0xF010139Cu)
+
+/** \brief 1380, TIM Channel General Purpose 0 Register */
+#define GTM_TIM0_CH7_GPR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR0*)0xF0101380u)
+
+/** \brief 1384, TIM Channel General Purpose 1 Register */
+#define GTM_TIM0_CH7_GPR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR1*)0xF0101384u)
+
+/** \brief 13B0, TIM Channel Interrupt Enable Register */
+#define GTM_TIM0_CH7_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_EN*)0xF01013B0u)
+
+/** \brief 13B4, TIM Channel Software Interrupt Force Register */
+#define GTM_TIM0_CH7_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_FORCINT*)0xF01013B4u)
+
+/** \brief 13B8, TIM IRQ Mode Configuration Register */
+#define GTM_TIM0_CH7_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_MODE*)0xF01013B8u)
+
+/** \brief 13AC, TIM Channel Interrupt Notification Register */
+#define GTM_TIM0_CH7_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_NOTIFY*)0xF01013ACu)
+
+/** \brief 1394, TIM Channel TDUC Register */
+#define GTM_TIM0_CH7_TDUC /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUC*)0xF0101394u)
+
+/** \brief 1398, TIM Channel TDUV Register */
+#define GTM_TIM0_CH7_TDUV /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUV*)0xF0101398u)
+
+/** \brief 1078, TIM_IN_SRC Long Name */
+#define GTM_TIM0_IN_SRC /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_IN_SRC*)0xF0101078u)
+
+/** \brief 107C, TIM Global Software Reset Register */
+#define GTM_TIM0_RST /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_RST*)0xF010107Cu)
+
+/** \brief 1808, TIM Channel SMU Counter Register */
+#define GTM_TIM1_CH0_CNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNT*)0xF0101808u)
+
+/** \brief 1810, TIM Channel SMU Shadow Counter Register */
+#define GTM_TIM1_CH0_CNTS /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNTS*)0xF0101810u)
+
+/** \brief 1824, TIM Channel Control Register */
+#define GTM_TIM1_CH0_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CTRL*)0xF0101824u)
+
+/** \brief 180C, TIM Channel Edge Counter Register */
+#define GTM_TIM1_CH0_ECNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECNT*)0xF010180Cu)
+
+/** \brief 1828, TIM Channel External Capture Control Register */
+#define GTM_TIM1_CH0_ECTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECTRL*)0xF0101828u)
+
+/** \brief 183C, TIM Channel Error Interrupt Enable Register */
+#define GTM_TIM1_CH0_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_EIRQ_EN*)0xF010183Cu)
+
+/** \brief 1820, TIM Channel Filter Parameter 1 Register */
+#define GTM_TIM1_CH0_FLT_FE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_FE*)0xF0101820u)
+
+/** \brief 181C, GTM_TIM Channel Filter Parameter 0 Register */
+#define GTM_TIM1_CH0_FLT_RE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_RE*)0xF010181Cu)
+
+/** \brief 1800, TIM Channel General Purpose 0 Register */
+#define GTM_TIM1_CH0_GPR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR0*)0xF0101800u)
+
+/** \brief 1804, TIM Channel General Purpose 1 Register */
+#define GTM_TIM1_CH0_GPR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR1*)0xF0101804u)
+
+/** \brief 1830, TIM Channel Interrupt Enable Register */
+#define GTM_TIM1_CH0_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_EN*)0xF0101830u)
+
+/** \brief 1834, TIM Channel Software Interrupt Force Register */
+#define GTM_TIM1_CH0_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_FORCINT*)0xF0101834u)
+
+/** \brief 1838, TIM IRQ Mode Configuration Register */
+#define GTM_TIM1_CH0_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_MODE*)0xF0101838u)
+
+/** \brief 182C, TIM Channel Interrupt Notification Register */
+#define GTM_TIM1_CH0_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_NOTIFY*)0xF010182Cu)
+
+/** \brief 1814, TIM Channel TDUC Register */
+#define GTM_TIM1_CH0_TDUC /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUC*)0xF0101814u)
+
+/** \brief 1818, TIM Channel TDUV Register */
+#define GTM_TIM1_CH0_TDUV /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUV*)0xF0101818u)
+
+/** \brief 1888, TIM Channel SMU Counter Register */
+#define GTM_TIM1_CH1_CNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNT*)0xF0101888u)
+
+/** \brief 1890, TIM Channel SMU Shadow Counter Register */
+#define GTM_TIM1_CH1_CNTS /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNTS*)0xF0101890u)
+
+/** \brief 18A4, TIM Channel Control Register */
+#define GTM_TIM1_CH1_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CTRL*)0xF01018A4u)
+
+/** \brief 188C, TIM Channel Edge Counter Register */
+#define GTM_TIM1_CH1_ECNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECNT*)0xF010188Cu)
+
+/** \brief 18A8, TIM Channel External Capture Control Register */
+#define GTM_TIM1_CH1_ECTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECTRL*)0xF01018A8u)
+
+/** \brief 18BC, TIM Channel Error Interrupt Enable Register */
+#define GTM_TIM1_CH1_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_EIRQ_EN*)0xF01018BCu)
+
+/** \brief 18A0, TIM Channel Filter Parameter 1 Register */
+#define GTM_TIM1_CH1_FLT_FE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_FE*)0xF01018A0u)
+
+/** \brief 189C, GTM_TIM Channel Filter Parameter 0 Register */
+#define GTM_TIM1_CH1_FLT_RE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_RE*)0xF010189Cu)
+
+/** \brief 1880, TIM Channel General Purpose 0 Register */
+#define GTM_TIM1_CH1_GPR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR0*)0xF0101880u)
+
+/** \brief 1884, TIM Channel General Purpose 1 Register */
+#define GTM_TIM1_CH1_GPR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR1*)0xF0101884u)
+
+/** \brief 18B0, TIM Channel Interrupt Enable Register */
+#define GTM_TIM1_CH1_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_EN*)0xF01018B0u)
+
+/** \brief 18B4, TIM Channel Software Interrupt Force Register */
+#define GTM_TIM1_CH1_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_FORCINT*)0xF01018B4u)
+
+/** \brief 18B8, TIM IRQ Mode Configuration Register */
+#define GTM_TIM1_CH1_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_MODE*)0xF01018B8u)
+
+/** \brief 18AC, TIM Channel Interrupt Notification Register */
+#define GTM_TIM1_CH1_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_NOTIFY*)0xF01018ACu)
+
+/** \brief 1894, TIM Channel TDUC Register */
+#define GTM_TIM1_CH1_TDUC /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUC*)0xF0101894u)
+
+/** \brief 1898, TIM Channel TDUV Register */
+#define GTM_TIM1_CH1_TDUV /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUV*)0xF0101898u)
+
+/** \brief 1908, TIM Channel SMU Counter Register */
+#define GTM_TIM1_CH2_CNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNT*)0xF0101908u)
+
+/** \brief 1910, TIM Channel SMU Shadow Counter Register */
+#define GTM_TIM1_CH2_CNTS /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNTS*)0xF0101910u)
+
+/** \brief 1924, TIM Channel Control Register */
+#define GTM_TIM1_CH2_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CTRL*)0xF0101924u)
+
+/** \brief 190C, TIM Channel Edge Counter Register */
+#define GTM_TIM1_CH2_ECNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECNT*)0xF010190Cu)
+
+/** \brief 1928, TIM Channel External Capture Control Register */
+#define GTM_TIM1_CH2_ECTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECTRL*)0xF0101928u)
+
+/** \brief 193C, TIM Channel Error Interrupt Enable Register */
+#define GTM_TIM1_CH2_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_EIRQ_EN*)0xF010193Cu)
+
+/** \brief 1920, TIM Channel Filter Parameter 1 Register */
+#define GTM_TIM1_CH2_FLT_FE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_FE*)0xF0101920u)
+
+/** \brief 191C, GTM_TIM Channel Filter Parameter 0 Register */
+#define GTM_TIM1_CH2_FLT_RE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_RE*)0xF010191Cu)
+
+/** \brief 1900, TIM Channel General Purpose 0 Register */
+#define GTM_TIM1_CH2_GPR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR0*)0xF0101900u)
+
+/** \brief 1904, TIM Channel General Purpose 1 Register */
+#define GTM_TIM1_CH2_GPR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR1*)0xF0101904u)
+
+/** \brief 1930, TIM Channel Interrupt Enable Register */
+#define GTM_TIM1_CH2_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_EN*)0xF0101930u)
+
+/** \brief 1934, TIM Channel Software Interrupt Force Register */
+#define GTM_TIM1_CH2_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_FORCINT*)0xF0101934u)
+
+/** \brief 1938, TIM IRQ Mode Configuration Register */
+#define GTM_TIM1_CH2_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_MODE*)0xF0101938u)
+
+/** \brief 192C, TIM Channel Interrupt Notification Register */
+#define GTM_TIM1_CH2_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_NOTIFY*)0xF010192Cu)
+
+/** \brief 1914, TIM Channel TDUC Register */
+#define GTM_TIM1_CH2_TDUC /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUC*)0xF0101914u)
+
+/** \brief 1918, TIM Channel TDUV Register */
+#define GTM_TIM1_CH2_TDUV /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUV*)0xF0101918u)
+
+/** \brief 1988, TIM Channel SMU Counter Register */
+#define GTM_TIM1_CH3_CNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNT*)0xF0101988u)
+
+/** \brief 1990, TIM Channel SMU Shadow Counter Register */
+#define GTM_TIM1_CH3_CNTS /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNTS*)0xF0101990u)
+
+/** \brief 19A4, TIM Channel Control Register */
+#define GTM_TIM1_CH3_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CTRL*)0xF01019A4u)
+
+/** \brief 198C, TIM Channel Edge Counter Register */
+#define GTM_TIM1_CH3_ECNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECNT*)0xF010198Cu)
+
+/** \brief 19A8, TIM Channel External Capture Control Register */
+#define GTM_TIM1_CH3_ECTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECTRL*)0xF01019A8u)
+
+/** \brief 19BC, TIM Channel Error Interrupt Enable Register */
+#define GTM_TIM1_CH3_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_EIRQ_EN*)0xF01019BCu)
+
+/** \brief 19A0, TIM Channel Filter Parameter 1 Register */
+#define GTM_TIM1_CH3_FLT_FE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_FE*)0xF01019A0u)
+
+/** \brief 199C, GTM_TIM Channel Filter Parameter 0 Register */
+#define GTM_TIM1_CH3_FLT_RE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_RE*)0xF010199Cu)
+
+/** \brief 1980, TIM Channel General Purpose 0 Register */
+#define GTM_TIM1_CH3_GPR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR0*)0xF0101980u)
+
+/** \brief 1984, TIM Channel General Purpose 1 Register */
+#define GTM_TIM1_CH3_GPR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR1*)0xF0101984u)
+
+/** \brief 19B0, TIM Channel Interrupt Enable Register */
+#define GTM_TIM1_CH3_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_EN*)0xF01019B0u)
+
+/** \brief 19B4, TIM Channel Software Interrupt Force Register */
+#define GTM_TIM1_CH3_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_FORCINT*)0xF01019B4u)
+
+/** \brief 19B8, TIM IRQ Mode Configuration Register */
+#define GTM_TIM1_CH3_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_MODE*)0xF01019B8u)
+
+/** \brief 19AC, TIM Channel Interrupt Notification Register */
+#define GTM_TIM1_CH3_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_NOTIFY*)0xF01019ACu)
+
+/** \brief 1994, TIM Channel TDUC Register */
+#define GTM_TIM1_CH3_TDUC /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUC*)0xF0101994u)
+
+/** \brief 1998, TIM Channel TDUV Register */
+#define GTM_TIM1_CH3_TDUV /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUV*)0xF0101998u)
+
+/** \brief 1A08, TIM Channel SMU Counter Register */
+#define GTM_TIM1_CH4_CNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNT*)0xF0101A08u)
+
+/** \brief 1A10, TIM Channel SMU Shadow Counter Register */
+#define GTM_TIM1_CH4_CNTS /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNTS*)0xF0101A10u)
+
+/** \brief 1A24, TIM Channel Control Register */
+#define GTM_TIM1_CH4_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CTRL*)0xF0101A24u)
+
+/** \brief 1A0C, TIM Channel Edge Counter Register */
+#define GTM_TIM1_CH4_ECNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECNT*)0xF0101A0Cu)
+
+/** \brief 1A28, TIM Channel External Capture Control Register */
+#define GTM_TIM1_CH4_ECTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECTRL*)0xF0101A28u)
+
+/** \brief 1A3C, TIM Channel Error Interrupt Enable Register */
+#define GTM_TIM1_CH4_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_EIRQ_EN*)0xF0101A3Cu)
+
+/** \brief 1A20, TIM Channel Filter Parameter 1 Register */
+#define GTM_TIM1_CH4_FLT_FE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_FE*)0xF0101A20u)
+
+/** \brief 1A1C, GTM_TIM Channel Filter Parameter 0 Register */
+#define GTM_TIM1_CH4_FLT_RE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_RE*)0xF0101A1Cu)
+
+/** \brief 1A00, TIM Channel General Purpose 0 Register */
+#define GTM_TIM1_CH4_GPR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR0*)0xF0101A00u)
+
+/** \brief 1A04, TIM Channel General Purpose 1 Register */
+#define GTM_TIM1_CH4_GPR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR1*)0xF0101A04u)
+
+/** \brief 1A30, TIM Channel Interrupt Enable Register */
+#define GTM_TIM1_CH4_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_EN*)0xF0101A30u)
+
+/** \brief 1A34, TIM Channel Software Interrupt Force Register */
+#define GTM_TIM1_CH4_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_FORCINT*)0xF0101A34u)
+
+/** \brief 1A38, TIM IRQ Mode Configuration Register */
+#define GTM_TIM1_CH4_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_MODE*)0xF0101A38u)
+
+/** \brief 1A2C, TIM Channel Interrupt Notification Register */
+#define GTM_TIM1_CH4_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_NOTIFY*)0xF0101A2Cu)
+
+/** \brief 1A14, TIM Channel TDUC Register */
+#define GTM_TIM1_CH4_TDUC /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUC*)0xF0101A14u)
+
+/** \brief 1A18, TIM Channel TDUV Register */
+#define GTM_TIM1_CH4_TDUV /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUV*)0xF0101A18u)
+
+/** \brief 1A88, TIM Channel SMU Counter Register */
+#define GTM_TIM1_CH5_CNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNT*)0xF0101A88u)
+
+/** \brief 1A90, TIM Channel SMU Shadow Counter Register */
+#define GTM_TIM1_CH5_CNTS /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNTS*)0xF0101A90u)
+
+/** \brief 1AA4, TIM Channel Control Register */
+#define GTM_TIM1_CH5_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CTRL*)0xF0101AA4u)
+
+/** \brief 1A8C, TIM Channel Edge Counter Register */
+#define GTM_TIM1_CH5_ECNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECNT*)0xF0101A8Cu)
+
+/** \brief 1AA8, TIM Channel External Capture Control Register */
+#define GTM_TIM1_CH5_ECTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECTRL*)0xF0101AA8u)
+
+/** \brief 1ABC, TIM Channel Error Interrupt Enable Register */
+#define GTM_TIM1_CH5_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_EIRQ_EN*)0xF0101ABCu)
+
+/** \brief 1AA0, TIM Channel Filter Parameter 1 Register */
+#define GTM_TIM1_CH5_FLT_FE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_FE*)0xF0101AA0u)
+
+/** \brief 1A9C, GTM_TIM Channel Filter Parameter 0 Register */
+#define GTM_TIM1_CH5_FLT_RE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_RE*)0xF0101A9Cu)
+
+/** \brief 1A80, TIM Channel General Purpose 0 Register */
+#define GTM_TIM1_CH5_GPR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR0*)0xF0101A80u)
+
+/** \brief 1A84, TIM Channel General Purpose 1 Register */
+#define GTM_TIM1_CH5_GPR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR1*)0xF0101A84u)
+
+/** \brief 1AB0, TIM Channel Interrupt Enable Register */
+#define GTM_TIM1_CH5_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_EN*)0xF0101AB0u)
+
+/** \brief 1AB4, TIM Channel Software Interrupt Force Register */
+#define GTM_TIM1_CH5_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_FORCINT*)0xF0101AB4u)
+
+/** \brief 1AB8, TIM IRQ Mode Configuration Register */
+#define GTM_TIM1_CH5_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_MODE*)0xF0101AB8u)
+
+/** \brief 1AAC, TIM Channel Interrupt Notification Register */
+#define GTM_TIM1_CH5_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_NOTIFY*)0xF0101AACu)
+
+/** \brief 1A94, TIM Channel TDUC Register */
+#define GTM_TIM1_CH5_TDUC /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUC*)0xF0101A94u)
+
+/** \brief 1A98, TIM Channel TDUV Register */
+#define GTM_TIM1_CH5_TDUV /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUV*)0xF0101A98u)
+
+/** \brief 1B08, TIM Channel SMU Counter Register */
+#define GTM_TIM1_CH6_CNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNT*)0xF0101B08u)
+
+/** \brief 1B10, TIM Channel SMU Shadow Counter Register */
+#define GTM_TIM1_CH6_CNTS /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNTS*)0xF0101B10u)
+
+/** \brief 1B24, TIM Channel Control Register */
+#define GTM_TIM1_CH6_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CTRL*)0xF0101B24u)
+
+/** \brief 1B0C, TIM Channel Edge Counter Register */
+#define GTM_TIM1_CH6_ECNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECNT*)0xF0101B0Cu)
+
+/** \brief 1B28, TIM Channel External Capture Control Register */
+#define GTM_TIM1_CH6_ECTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECTRL*)0xF0101B28u)
+
+/** \brief 1B3C, TIM Channel Error Interrupt Enable Register */
+#define GTM_TIM1_CH6_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_EIRQ_EN*)0xF0101B3Cu)
+
+/** \brief 1B20, TIM Channel Filter Parameter 1 Register */
+#define GTM_TIM1_CH6_FLT_FE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_FE*)0xF0101B20u)
+
+/** \brief 1B1C, GTM_TIM Channel Filter Parameter 0 Register */
+#define GTM_TIM1_CH6_FLT_RE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_RE*)0xF0101B1Cu)
+
+/** \brief 1B00, TIM Channel General Purpose 0 Register */
+#define GTM_TIM1_CH6_GPR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR0*)0xF0101B00u)
+
+/** \brief 1B04, TIM Channel General Purpose 1 Register */
+#define GTM_TIM1_CH6_GPR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR1*)0xF0101B04u)
+
+/** \brief 1B30, TIM Channel Interrupt Enable Register */
+#define GTM_TIM1_CH6_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_EN*)0xF0101B30u)
+
+/** \brief 1B34, TIM Channel Software Interrupt Force Register */
+#define GTM_TIM1_CH6_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_FORCINT*)0xF0101B34u)
+
+/** \brief 1B38, TIM IRQ Mode Configuration Register */
+#define GTM_TIM1_CH6_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_MODE*)0xF0101B38u)
+
+/** \brief 1B2C, TIM Channel Interrupt Notification Register */
+#define GTM_TIM1_CH6_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_NOTIFY*)0xF0101B2Cu)
+
+/** \brief 1B14, TIM Channel TDUC Register */
+#define GTM_TIM1_CH6_TDUC /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUC*)0xF0101B14u)
+
+/** \brief 1B18, TIM Channel TDUV Register */
+#define GTM_TIM1_CH6_TDUV /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUV*)0xF0101B18u)
+
+/** \brief 1B88, TIM Channel SMU Counter Register */
+#define GTM_TIM1_CH7_CNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNT*)0xF0101B88u)
+
+/** \brief 1B90, TIM Channel SMU Shadow Counter Register */
+#define GTM_TIM1_CH7_CNTS /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNTS*)0xF0101B90u)
+
+/** \brief 1BA4, TIM Channel Control Register */
+#define GTM_TIM1_CH7_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CTRL*)0xF0101BA4u)
+
+/** \brief 1B8C, TIM Channel Edge Counter Register */
+#define GTM_TIM1_CH7_ECNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECNT*)0xF0101B8Cu)
+
+/** \brief 1BA8, TIM Channel External Capture Control Register */
+#define GTM_TIM1_CH7_ECTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECTRL*)0xF0101BA8u)
+
+/** \brief 1BBC, TIM Channel Error Interrupt Enable Register */
+#define GTM_TIM1_CH7_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_EIRQ_EN*)0xF0101BBCu)
+
+/** \brief 1BA0, TIM Channel Filter Parameter 1 Register */
+#define GTM_TIM1_CH7_FLT_FE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_FE*)0xF0101BA0u)
+
+/** \brief 1B9C, GTM_TIM Channel Filter Parameter 0 Register */
+#define GTM_TIM1_CH7_FLT_RE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_RE*)0xF0101B9Cu)
+
+/** \brief 1B80, TIM Channel General Purpose 0 Register */
+#define GTM_TIM1_CH7_GPR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR0*)0xF0101B80u)
+
+/** \brief 1B84, TIM Channel General Purpose 1 Register */
+#define GTM_TIM1_CH7_GPR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR1*)0xF0101B84u)
+
+/** \brief 1BB0, TIM Channel Interrupt Enable Register */
+#define GTM_TIM1_CH7_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_EN*)0xF0101BB0u)
+
+/** \brief 1BB4, TIM Channel Software Interrupt Force Register */
+#define GTM_TIM1_CH7_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_FORCINT*)0xF0101BB4u)
+
+/** \brief 1BB8, TIM IRQ Mode Configuration Register */
+#define GTM_TIM1_CH7_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_MODE*)0xF0101BB8u)
+
+/** \brief 1BAC, TIM Channel Interrupt Notification Register */
+#define GTM_TIM1_CH7_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_NOTIFY*)0xF0101BACu)
+
+/** \brief 1B94, TIM Channel TDUC Register */
+#define GTM_TIM1_CH7_TDUC /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUC*)0xF0101B94u)
+
+/** \brief 1B98, TIM Channel TDUV Register */
+#define GTM_TIM1_CH7_TDUV /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUV*)0xF0101B98u)
+
+/** \brief 1878, TIM_IN_SRC Long Name */
+#define GTM_TIM1_IN_SRC /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_IN_SRC*)0xF0101878u)
+
+/** \brief 187C, TIM Global Software Reset Register */
+#define GTM_TIM1_RST /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_RST*)0xF010187Cu)
+
+/** \brief 2008, TIM Channel SMU Counter Register */
+#define GTM_TIM2_CH0_CNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNT*)0xF0102008u)
+
+/** \brief 2010, TIM Channel SMU Shadow Counter Register */
+#define GTM_TIM2_CH0_CNTS /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNTS*)0xF0102010u)
+
+/** \brief 2024, TIM Channel Control Register */
+#define GTM_TIM2_CH0_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CTRL*)0xF0102024u)
+
+/** \brief 200C, TIM Channel Edge Counter Register */
+#define GTM_TIM2_CH0_ECNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECNT*)0xF010200Cu)
+
+/** \brief 2028, TIM Channel External Capture Control Register */
+#define GTM_TIM2_CH0_ECTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECTRL*)0xF0102028u)
+
+/** \brief 203C, TIM Channel Error Interrupt Enable Register */
+#define GTM_TIM2_CH0_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_EIRQ_EN*)0xF010203Cu)
+
+/** \brief 2020, TIM Channel Filter Parameter 1 Register */
+#define GTM_TIM2_CH0_FLT_FE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_FE*)0xF0102020u)
+
+/** \brief 201C, GTM_TIM Channel Filter Parameter 0 Register */
+#define GTM_TIM2_CH0_FLT_RE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_RE*)0xF010201Cu)
+
+/** \brief 2000, TIM Channel General Purpose 0 Register */
+#define GTM_TIM2_CH0_GPR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR0*)0xF0102000u)
+
+/** \brief 2004, TIM Channel General Purpose 1 Register */
+#define GTM_TIM2_CH0_GPR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR1*)0xF0102004u)
+
+/** \brief 2030, TIM Channel Interrupt Enable Register */
+#define GTM_TIM2_CH0_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_EN*)0xF0102030u)
+
+/** \brief 2034, TIM Channel Software Interrupt Force Register */
+#define GTM_TIM2_CH0_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_FORCINT*)0xF0102034u)
+
+/** \brief 2038, TIM IRQ Mode Configuration Register */
+#define GTM_TIM2_CH0_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_MODE*)0xF0102038u)
+
+/** \brief 202C, TIM Channel Interrupt Notification Register */
+#define GTM_TIM2_CH0_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_NOTIFY*)0xF010202Cu)
+
+/** \brief 2014, TIM Channel TDUC Register */
+#define GTM_TIM2_CH0_TDUC /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUC*)0xF0102014u)
+
+/** \brief 2018, TIM Channel TDUV Register */
+#define GTM_TIM2_CH0_TDUV /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUV*)0xF0102018u)
+
+/** \brief 2088, TIM Channel SMU Counter Register */
+#define GTM_TIM2_CH1_CNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNT*)0xF0102088u)
+
+/** \brief 2090, TIM Channel SMU Shadow Counter Register */
+#define GTM_TIM2_CH1_CNTS /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNTS*)0xF0102090u)
+
+/** \brief 20A4, TIM Channel Control Register */
+#define GTM_TIM2_CH1_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CTRL*)0xF01020A4u)
+
+/** \brief 208C, TIM Channel Edge Counter Register */
+#define GTM_TIM2_CH1_ECNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECNT*)0xF010208Cu)
+
+/** \brief 20A8, TIM Channel External Capture Control Register */
+#define GTM_TIM2_CH1_ECTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECTRL*)0xF01020A8u)
+
+/** \brief 20BC, TIM Channel Error Interrupt Enable Register */
+#define GTM_TIM2_CH1_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_EIRQ_EN*)0xF01020BCu)
+
+/** \brief 20A0, TIM Channel Filter Parameter 1 Register */
+#define GTM_TIM2_CH1_FLT_FE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_FE*)0xF01020A0u)
+
+/** \brief 209C, GTM_TIM Channel Filter Parameter 0 Register */
+#define GTM_TIM2_CH1_FLT_RE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_RE*)0xF010209Cu)
+
+/** \brief 2080, TIM Channel General Purpose 0 Register */
+#define GTM_TIM2_CH1_GPR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR0*)0xF0102080u)
+
+/** \brief 2084, TIM Channel General Purpose 1 Register */
+#define GTM_TIM2_CH1_GPR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR1*)0xF0102084u)
+
+/** \brief 20B0, TIM Channel Interrupt Enable Register */
+#define GTM_TIM2_CH1_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_EN*)0xF01020B0u)
+
+/** \brief 20B4, TIM Channel Software Interrupt Force Register */
+#define GTM_TIM2_CH1_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_FORCINT*)0xF01020B4u)
+
+/** \brief 20B8, TIM IRQ Mode Configuration Register */
+#define GTM_TIM2_CH1_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_MODE*)0xF01020B8u)
+
+/** \brief 20AC, TIM Channel Interrupt Notification Register */
+#define GTM_TIM2_CH1_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_NOTIFY*)0xF01020ACu)
+
+/** \brief 2094, TIM Channel TDUC Register */
+#define GTM_TIM2_CH1_TDUC /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUC*)0xF0102094u)
+
+/** \brief 2098, TIM Channel TDUV Register */
+#define GTM_TIM2_CH1_TDUV /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUV*)0xF0102098u)
+
+/** \brief 2108, TIM Channel SMU Counter Register */
+#define GTM_TIM2_CH2_CNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNT*)0xF0102108u)
+
+/** \brief 2110, TIM Channel SMU Shadow Counter Register */
+#define GTM_TIM2_CH2_CNTS /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNTS*)0xF0102110u)
+
+/** \brief 2124, TIM Channel Control Register */
+#define GTM_TIM2_CH2_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CTRL*)0xF0102124u)
+
+/** \brief 210C, TIM Channel Edge Counter Register */
+#define GTM_TIM2_CH2_ECNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECNT*)0xF010210Cu)
+
+/** \brief 2128, TIM Channel External Capture Control Register */
+#define GTM_TIM2_CH2_ECTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECTRL*)0xF0102128u)
+
+/** \brief 213C, TIM Channel Error Interrupt Enable Register */
+#define GTM_TIM2_CH2_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_EIRQ_EN*)0xF010213Cu)
+
+/** \brief 2120, TIM Channel Filter Parameter 1 Register */
+#define GTM_TIM2_CH2_FLT_FE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_FE*)0xF0102120u)
+
+/** \brief 211C, GTM_TIM Channel Filter Parameter 0 Register */
+#define GTM_TIM2_CH2_FLT_RE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_RE*)0xF010211Cu)
+
+/** \brief 2100, TIM Channel General Purpose 0 Register */
+#define GTM_TIM2_CH2_GPR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR0*)0xF0102100u)
+
+/** \brief 2104, TIM Channel General Purpose 1 Register */
+#define GTM_TIM2_CH2_GPR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR1*)0xF0102104u)
+
+/** \brief 2130, TIM Channel Interrupt Enable Register */
+#define GTM_TIM2_CH2_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_EN*)0xF0102130u)
+
+/** \brief 2134, TIM Channel Software Interrupt Force Register */
+#define GTM_TIM2_CH2_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_FORCINT*)0xF0102134u)
+
+/** \brief 2138, TIM IRQ Mode Configuration Register */
+#define GTM_TIM2_CH2_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_MODE*)0xF0102138u)
+
+/** \brief 212C, TIM Channel Interrupt Notification Register */
+#define GTM_TIM2_CH2_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_NOTIFY*)0xF010212Cu)
+
+/** \brief 2114, TIM Channel TDUC Register */
+#define GTM_TIM2_CH2_TDUC /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUC*)0xF0102114u)
+
+/** \brief 2118, TIM Channel TDUV Register */
+#define GTM_TIM2_CH2_TDUV /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUV*)0xF0102118u)
+
+/** \brief 2188, TIM Channel SMU Counter Register */
+#define GTM_TIM2_CH3_CNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNT*)0xF0102188u)
+
+/** \brief 2190, TIM Channel SMU Shadow Counter Register */
+#define GTM_TIM2_CH3_CNTS /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNTS*)0xF0102190u)
+
+/** \brief 21A4, TIM Channel Control Register */
+#define GTM_TIM2_CH3_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CTRL*)0xF01021A4u)
+
+/** \brief 218C, TIM Channel Edge Counter Register */
+#define GTM_TIM2_CH3_ECNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECNT*)0xF010218Cu)
+
+/** \brief 21A8, TIM Channel External Capture Control Register */
+#define GTM_TIM2_CH3_ECTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECTRL*)0xF01021A8u)
+
+/** \brief 21BC, TIM Channel Error Interrupt Enable Register */
+#define GTM_TIM2_CH3_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_EIRQ_EN*)0xF01021BCu)
+
+/** \brief 21A0, TIM Channel Filter Parameter 1 Register */
+#define GTM_TIM2_CH3_FLT_FE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_FE*)0xF01021A0u)
+
+/** \brief 219C, GTM_TIM Channel Filter Parameter 0 Register */
+#define GTM_TIM2_CH3_FLT_RE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_RE*)0xF010219Cu)
+
+/** \brief 2180, TIM Channel General Purpose 0 Register */
+#define GTM_TIM2_CH3_GPR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR0*)0xF0102180u)
+
+/** \brief 2184, TIM Channel General Purpose 1 Register */
+#define GTM_TIM2_CH3_GPR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR1*)0xF0102184u)
+
+/** \brief 21B0, TIM Channel Interrupt Enable Register */
+#define GTM_TIM2_CH3_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_EN*)0xF01021B0u)
+
+/** \brief 21B4, TIM Channel Software Interrupt Force Register */
+#define GTM_TIM2_CH3_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_FORCINT*)0xF01021B4u)
+
+/** \brief 21B8, TIM IRQ Mode Configuration Register */
+#define GTM_TIM2_CH3_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_MODE*)0xF01021B8u)
+
+/** \brief 21AC, TIM Channel Interrupt Notification Register */
+#define GTM_TIM2_CH3_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_NOTIFY*)0xF01021ACu)
+
+/** \brief 2194, TIM Channel TDUC Register */
+#define GTM_TIM2_CH3_TDUC /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUC*)0xF0102194u)
+
+/** \brief 2198, TIM Channel TDUV Register */
+#define GTM_TIM2_CH3_TDUV /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUV*)0xF0102198u)
+
+/** \brief 2208, TIM Channel SMU Counter Register */
+#define GTM_TIM2_CH4_CNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNT*)0xF0102208u)
+
+/** \brief 2210, TIM Channel SMU Shadow Counter Register */
+#define GTM_TIM2_CH4_CNTS /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNTS*)0xF0102210u)
+
+/** \brief 2224, TIM Channel Control Register */
+#define GTM_TIM2_CH4_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CTRL*)0xF0102224u)
+
+/** \brief 220C, TIM Channel Edge Counter Register */
+#define GTM_TIM2_CH4_ECNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECNT*)0xF010220Cu)
+
+/** \brief 2228, TIM Channel External Capture Control Register */
+#define GTM_TIM2_CH4_ECTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECTRL*)0xF0102228u)
+
+/** \brief 223C, TIM Channel Error Interrupt Enable Register */
+#define GTM_TIM2_CH4_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_EIRQ_EN*)0xF010223Cu)
+
+/** \brief 2220, TIM Channel Filter Parameter 1 Register */
+#define GTM_TIM2_CH4_FLT_FE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_FE*)0xF0102220u)
+
+/** \brief 221C, GTM_TIM Channel Filter Parameter 0 Register */
+#define GTM_TIM2_CH4_FLT_RE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_RE*)0xF010221Cu)
+
+/** \brief 2200, TIM Channel General Purpose 0 Register */
+#define GTM_TIM2_CH4_GPR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR0*)0xF0102200u)
+
+/** \brief 2204, TIM Channel General Purpose 1 Register */
+#define GTM_TIM2_CH4_GPR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR1*)0xF0102204u)
+
+/** \brief 2230, TIM Channel Interrupt Enable Register */
+#define GTM_TIM2_CH4_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_EN*)0xF0102230u)
+
+/** \brief 2234, TIM Channel Software Interrupt Force Register */
+#define GTM_TIM2_CH4_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_FORCINT*)0xF0102234u)
+
+/** \brief 2238, TIM IRQ Mode Configuration Register */
+#define GTM_TIM2_CH4_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_MODE*)0xF0102238u)
+
+/** \brief 222C, TIM Channel Interrupt Notification Register */
+#define GTM_TIM2_CH4_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_NOTIFY*)0xF010222Cu)
+
+/** \brief 2214, TIM Channel TDUC Register */
+#define GTM_TIM2_CH4_TDUC /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUC*)0xF0102214u)
+
+/** \brief 2218, TIM Channel TDUV Register */
+#define GTM_TIM2_CH4_TDUV /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUV*)0xF0102218u)
+
+/** \brief 2288, TIM Channel SMU Counter Register */
+#define GTM_TIM2_CH5_CNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNT*)0xF0102288u)
+
+/** \brief 2290, TIM Channel SMU Shadow Counter Register */
+#define GTM_TIM2_CH5_CNTS /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNTS*)0xF0102290u)
+
+/** \brief 22A4, TIM Channel Control Register */
+#define GTM_TIM2_CH5_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CTRL*)0xF01022A4u)
+
+/** \brief 228C, TIM Channel Edge Counter Register */
+#define GTM_TIM2_CH5_ECNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECNT*)0xF010228Cu)
+
+/** \brief 22A8, TIM Channel External Capture Control Register */
+#define GTM_TIM2_CH5_ECTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECTRL*)0xF01022A8u)
+
+/** \brief 22BC, TIM Channel Error Interrupt Enable Register */
+#define GTM_TIM2_CH5_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_EIRQ_EN*)0xF01022BCu)
+
+/** \brief 22A0, TIM Channel Filter Parameter 1 Register */
+#define GTM_TIM2_CH5_FLT_FE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_FE*)0xF01022A0u)
+
+/** \brief 229C, GTM_TIM Channel Filter Parameter 0 Register */
+#define GTM_TIM2_CH5_FLT_RE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_RE*)0xF010229Cu)
+
+/** \brief 2280, TIM Channel General Purpose 0 Register */
+#define GTM_TIM2_CH5_GPR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR0*)0xF0102280u)
+
+/** \brief 2284, TIM Channel General Purpose 1 Register */
+#define GTM_TIM2_CH5_GPR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR1*)0xF0102284u)
+
+/** \brief 22B0, TIM Channel Interrupt Enable Register */
+#define GTM_TIM2_CH5_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_EN*)0xF01022B0u)
+
+/** \brief 22B4, TIM Channel Software Interrupt Force Register */
+#define GTM_TIM2_CH5_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_FORCINT*)0xF01022B4u)
+
+/** \brief 22B8, TIM IRQ Mode Configuration Register */
+#define GTM_TIM2_CH5_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_MODE*)0xF01022B8u)
+
+/** \brief 22AC, TIM Channel Interrupt Notification Register */
+#define GTM_TIM2_CH5_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_NOTIFY*)0xF01022ACu)
+
+/** \brief 2294, TIM Channel TDUC Register */
+#define GTM_TIM2_CH5_TDUC /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUC*)0xF0102294u)
+
+/** \brief 2298, TIM Channel TDUV Register */
+#define GTM_TIM2_CH5_TDUV /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUV*)0xF0102298u)
+
+/** \brief 2308, TIM Channel SMU Counter Register */
+#define GTM_TIM2_CH6_CNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNT*)0xF0102308u)
+
+/** \brief 2310, TIM Channel SMU Shadow Counter Register */
+#define GTM_TIM2_CH6_CNTS /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNTS*)0xF0102310u)
+
+/** \brief 2324, TIM Channel Control Register */
+#define GTM_TIM2_CH6_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CTRL*)0xF0102324u)
+
+/** \brief 230C, TIM Channel Edge Counter Register */
+#define GTM_TIM2_CH6_ECNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECNT*)0xF010230Cu)
+
+/** \brief 2328, TIM Channel External Capture Control Register */
+#define GTM_TIM2_CH6_ECTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECTRL*)0xF0102328u)
+
+/** \brief 233C, TIM Channel Error Interrupt Enable Register */
+#define GTM_TIM2_CH6_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_EIRQ_EN*)0xF010233Cu)
+
+/** \brief 2320, TIM Channel Filter Parameter 1 Register */
+#define GTM_TIM2_CH6_FLT_FE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_FE*)0xF0102320u)
+
+/** \brief 231C, GTM_TIM Channel Filter Parameter 0 Register */
+#define GTM_TIM2_CH6_FLT_RE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_RE*)0xF010231Cu)
+
+/** \brief 2300, TIM Channel General Purpose 0 Register */
+#define GTM_TIM2_CH6_GPR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR0*)0xF0102300u)
+
+/** \brief 2304, TIM Channel General Purpose 1 Register */
+#define GTM_TIM2_CH6_GPR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR1*)0xF0102304u)
+
+/** \brief 2330, TIM Channel Interrupt Enable Register */
+#define GTM_TIM2_CH6_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_EN*)0xF0102330u)
+
+/** \brief 2334, TIM Channel Software Interrupt Force Register */
+#define GTM_TIM2_CH6_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_FORCINT*)0xF0102334u)
+
+/** \brief 2338, TIM IRQ Mode Configuration Register */
+#define GTM_TIM2_CH6_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_MODE*)0xF0102338u)
+
+/** \brief 232C, TIM Channel Interrupt Notification Register */
+#define GTM_TIM2_CH6_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_NOTIFY*)0xF010232Cu)
+
+/** \brief 2314, TIM Channel TDUC Register */
+#define GTM_TIM2_CH6_TDUC /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUC*)0xF0102314u)
+
+/** \brief 2318, TIM Channel TDUV Register */
+#define GTM_TIM2_CH6_TDUV /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUV*)0xF0102318u)
+
+/** \brief 2388, TIM Channel SMU Counter Register */
+#define GTM_TIM2_CH7_CNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNT*)0xF0102388u)
+
+/** \brief 2390, TIM Channel SMU Shadow Counter Register */
+#define GTM_TIM2_CH7_CNTS /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CNTS*)0xF0102390u)
+
+/** \brief 23A4, TIM Channel Control Register */
+#define GTM_TIM2_CH7_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_CTRL*)0xF01023A4u)
+
+/** \brief 238C, TIM Channel Edge Counter Register */
+#define GTM_TIM2_CH7_ECNT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECNT*)0xF010238Cu)
+
+/** \brief 23A8, TIM Channel External Capture Control Register */
+#define GTM_TIM2_CH7_ECTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_ECTRL*)0xF01023A8u)
+
+/** \brief 23BC, TIM Channel Error Interrupt Enable Register */
+#define GTM_TIM2_CH7_EIRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_EIRQ_EN*)0xF01023BCu)
+
+/** \brief 23A0, TIM Channel Filter Parameter 1 Register */
+#define GTM_TIM2_CH7_FLT_FE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_FE*)0xF01023A0u)
+
+/** \brief 239C, GTM_TIM Channel Filter Parameter 0 Register */
+#define GTM_TIM2_CH7_FLT_RE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_FLT_RE*)0xF010239Cu)
+
+/** \brief 2380, TIM Channel General Purpose 0 Register */
+#define GTM_TIM2_CH7_GPR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR0*)0xF0102380u)
+
+/** \brief 2384, TIM Channel General Purpose 1 Register */
+#define GTM_TIM2_CH7_GPR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_GPR1*)0xF0102384u)
+
+/** \brief 23B0, TIM Channel Interrupt Enable Register */
+#define GTM_TIM2_CH7_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_EN*)0xF01023B0u)
+
+/** \brief 23B4, TIM Channel Software Interrupt Force Register */
+#define GTM_TIM2_CH7_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_FORCINT*)0xF01023B4u)
+
+/** \brief 23B8, TIM IRQ Mode Configuration Register */
+#define GTM_TIM2_CH7_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_MODE*)0xF01023B8u)
+
+/** \brief 23AC, TIM Channel Interrupt Notification Register */
+#define GTM_TIM2_CH7_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_IRQ_NOTIFY*)0xF01023ACu)
+
+/** \brief 2394, TIM Channel TDUC Register */
+#define GTM_TIM2_CH7_TDUC /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUC*)0xF0102394u)
+
+/** \brief 2398, TIM Channel TDUV Register */
+#define GTM_TIM2_CH7_TDUV /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_CH_TDUV*)0xF0102398u)
+
+/** \brief 2078, TIM_IN_SRC Long Name */
+#define GTM_TIM2_IN_SRC /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_IN_SRC*)0xF0102078u)
+
+/** \brief 207C, TIM Global Software Reset Register */
+#define GTM_TIM2_RST /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_RST*)0xF010207Cu)
+
+/** \brief 40, GTM TIM AUX_IN_SRC */
+#define GTM_TIM_AUX_IN_SRC0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_AUX_IN_SRC*)0xF0100040u)
+
+/** Alias (User Manual Name) for GTM_TIM_AUX_IN_SRC0.
+* To use register names with standard convension, please use GTM_TIM_AUX_IN_SRC0.
+*/
+#define GTM_TIM0_AUX_IN_SRC (GTM_TIM_AUX_IN_SRC0)
+
+/** \brief 44, GTM TIM AUX_IN_SRC */
+#define GTM_TIM_AUX_IN_SRC1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_AUX_IN_SRC*)0xF0100044u)
+
+/** Alias (User Manual Name) for GTM_TIM_AUX_IN_SRC1.
+* To use register names with standard convension, please use GTM_TIM_AUX_IN_SRC1.
+*/
+#define GTM_TIM1_AUX_IN_SRC (GTM_TIM_AUX_IN_SRC1)
+
+/** \brief 48, GTM TIM AUX_IN_SRC */
+#define GTM_TIM_AUX_IN_SRC2 /*lint --e(923)*/ (*(volatile Ifx_GTM_TIM_AUX_IN_SRC*)0xF0100048u)
+
+/** Alias (User Manual Name) for GTM_TIM_AUX_IN_SRC2.
+* To use register names with standard convension, please use GTM_TIM_AUX_IN_SRC2.
+*/
+#define GTM_TIM2_AUX_IN_SRC (GTM_TIM_AUX_IN_SRC2)
+
+/** \brief 800C, TOM Channel CCU0 Compare Register */
+#define GTM_TOM0_CH0_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF010800Cu)
+
+/** \brief 8010, TOM Channel CCU1 Compare Register */
+#define GTM_TOM0_CH0_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF0108010u)
+
+/** \brief 8014, TOM Channel CCU0 Counter Register */
+#define GTM_TOM0_CH0_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF0108014u)
+
+/** \brief 8000, TOM Channel Control Register’ */
+#define GTM_TOM0_CH0_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF0108000u)
+
+/** \brief 8020, TOM Channel Interrupt Enable Register */
+#define GTM_TOM0_CH0_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF0108020u)
+
+/** \brief 8024, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM0_CH0_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF0108024u)
+
+/** \brief 8028, TOM IRQ Mode Configuration Register */
+#define GTM_TOM0_CH0_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF0108028u)
+
+/** \brief 801C, TOM Channel Interrupt Notification Register */
+#define GTM_TOM0_CH0_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF010801Cu)
+
+/** \brief 8004, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM0_CH0_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF0108004u)
+
+/** \brief 8008, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM0_CH0_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF0108008u)
+
+/** \brief 8018, TOM Channel Status Register */
+#define GTM_TOM0_CH0_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF0108018u)
+
+/** \brief 828C, TOM Channel CCU0 Compare Register */
+#define GTM_TOM0_CH10_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF010828Cu)
+
+/** \brief 8290, TOM Channel CCU1 Compare Register */
+#define GTM_TOM0_CH10_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF0108290u)
+
+/** \brief 8294, TOM Channel CCU0 Counter Register */
+#define GTM_TOM0_CH10_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF0108294u)
+
+/** \brief 8280, TOM Channel Control Register’ */
+#define GTM_TOM0_CH10_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF0108280u)
+
+/** \brief 82A0, TOM Channel Interrupt Enable Register */
+#define GTM_TOM0_CH10_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF01082A0u)
+
+/** \brief 82A4, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM0_CH10_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF01082A4u)
+
+/** \brief 82A8, TOM IRQ Mode Configuration Register */
+#define GTM_TOM0_CH10_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF01082A8u)
+
+/** \brief 829C, TOM Channel Interrupt Notification Register */
+#define GTM_TOM0_CH10_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF010829Cu)
+
+/** \brief 8284, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM0_CH10_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF0108284u)
+
+/** \brief 8288, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM0_CH10_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF0108288u)
+
+/** \brief 8298, TOM Channel Status Register */
+#define GTM_TOM0_CH10_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF0108298u)
+
+/** \brief 82CC, TOM Channel CCU0 Compare Register */
+#define GTM_TOM0_CH11_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF01082CCu)
+
+/** \brief 82D0, TOM Channel CCU1 Compare Register */
+#define GTM_TOM0_CH11_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF01082D0u)
+
+/** \brief 82D4, TOM Channel CCU0 Counter Register */
+#define GTM_TOM0_CH11_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF01082D4u)
+
+/** \brief 82C0, TOM Channel Control Register’ */
+#define GTM_TOM0_CH11_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF01082C0u)
+
+/** \brief 82E0, TOM Channel Interrupt Enable Register */
+#define GTM_TOM0_CH11_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF01082E0u)
+
+/** \brief 82E4, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM0_CH11_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF01082E4u)
+
+/** \brief 82E8, TOM IRQ Mode Configuration Register */
+#define GTM_TOM0_CH11_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF01082E8u)
+
+/** \brief 82DC, TOM Channel Interrupt Notification Register */
+#define GTM_TOM0_CH11_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF01082DCu)
+
+/** \brief 82C4, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM0_CH11_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF01082C4u)
+
+/** \brief 82C8, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM0_CH11_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF01082C8u)
+
+/** \brief 82D8, TOM Channel Status Register */
+#define GTM_TOM0_CH11_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF01082D8u)
+
+/** \brief 830C, TOM Channel CCU0 Compare Register */
+#define GTM_TOM0_CH12_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF010830Cu)
+
+/** \brief 8310, TOM Channel CCU1 Compare Register */
+#define GTM_TOM0_CH12_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF0108310u)
+
+/** \brief 8314, TOM Channel CCU0 Counter Register */
+#define GTM_TOM0_CH12_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF0108314u)
+
+/** \brief 8300, TOM Channel Control Register’ */
+#define GTM_TOM0_CH12_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF0108300u)
+
+/** \brief 8320, TOM Channel Interrupt Enable Register */
+#define GTM_TOM0_CH12_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF0108320u)
+
+/** \brief 8324, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM0_CH12_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF0108324u)
+
+/** \brief 8328, TOM IRQ Mode Configuration Register */
+#define GTM_TOM0_CH12_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF0108328u)
+
+/** \brief 831C, TOM Channel Interrupt Notification Register */
+#define GTM_TOM0_CH12_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF010831Cu)
+
+/** \brief 8304, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM0_CH12_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF0108304u)
+
+/** \brief 8308, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM0_CH12_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF0108308u)
+
+/** \brief 8318, TOM Channel Status Register */
+#define GTM_TOM0_CH12_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF0108318u)
+
+/** \brief 834C, TOM Channel CCU0 Compare Register */
+#define GTM_TOM0_CH13_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF010834Cu)
+
+/** \brief 8350, TOM Channel CCU1 Compare Register */
+#define GTM_TOM0_CH13_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF0108350u)
+
+/** \brief 8354, TOM Channel CCU0 Counter Register */
+#define GTM_TOM0_CH13_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF0108354u)
+
+/** \brief 8340, TOM Channel Control Register’ */
+#define GTM_TOM0_CH13_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF0108340u)
+
+/** \brief 8360, TOM Channel Interrupt Enable Register */
+#define GTM_TOM0_CH13_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF0108360u)
+
+/** \brief 8364, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM0_CH13_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF0108364u)
+
+/** \brief 8368, TOM IRQ Mode Configuration Register */
+#define GTM_TOM0_CH13_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF0108368u)
+
+/** \brief 835C, TOM Channel Interrupt Notification Register */
+#define GTM_TOM0_CH13_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF010835Cu)
+
+/** \brief 8344, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM0_CH13_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF0108344u)
+
+/** \brief 8348, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM0_CH13_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF0108348u)
+
+/** \brief 8358, TOM Channel Status Register */
+#define GTM_TOM0_CH13_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF0108358u)
+
+/** \brief 838C, TOM Channel CCU0 Compare Register */
+#define GTM_TOM0_CH14_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF010838Cu)
+
+/** \brief 8390, TOM Channel CCU1 Compare Register */
+#define GTM_TOM0_CH14_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF0108390u)
+
+/** \brief 8394, TOM Channel CCU0 Counter Register */
+#define GTM_TOM0_CH14_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF0108394u)
+
+/** \brief 8380, TOM Channel Control Register’ */
+#define GTM_TOM0_CH14_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF0108380u)
+
+/** \brief 83A0, TOM Channel Interrupt Enable Register */
+#define GTM_TOM0_CH14_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF01083A0u)
+
+/** \brief 83A4, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM0_CH14_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF01083A4u)
+
+/** \brief 83A8, TOM IRQ Mode Configuration Register */
+#define GTM_TOM0_CH14_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF01083A8u)
+
+/** \brief 839C, TOM Channel Interrupt Notification Register */
+#define GTM_TOM0_CH14_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF010839Cu)
+
+/** \brief 8384, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM0_CH14_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF0108384u)
+
+/** \brief 8388, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM0_CH14_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF0108388u)
+
+/** \brief 8398, TOM Channel Status Register */
+#define GTM_TOM0_CH14_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF0108398u)
+
+/** \brief 83CC, TOM Channel CCU0 Compare Register */
+#define GTM_TOM0_CH15_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF01083CCu)
+
+/** \brief 83D0, TOM Channel CCU1 Compare Register */
+#define GTM_TOM0_CH15_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF01083D0u)
+
+/** \brief 83D4, TOM Channel CCU0 Counter Register */
+#define GTM_TOM0_CH15_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF01083D4u)
+
+/** \brief 83C0, TOM Channel Control Register’ */
+#define GTM_TOM0_CH15_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF01083C0u)
+
+/** \brief 83E0, TOM Channel Interrupt Enable Register */
+#define GTM_TOM0_CH15_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF01083E0u)
+
+/** \brief 83E4, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM0_CH15_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF01083E4u)
+
+/** \brief 83E8, TOM IRQ Mode Configuration Register */
+#define GTM_TOM0_CH15_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF01083E8u)
+
+/** \brief 83DC, TOM Channel Interrupt Notification Register */
+#define GTM_TOM0_CH15_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF01083DCu)
+
+/** \brief 83C4, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM0_CH15_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF01083C4u)
+
+/** \brief 83C8, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM0_CH15_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF01083C8u)
+
+/** \brief 83D8, TOM Channel Status Register */
+#define GTM_TOM0_CH15_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF01083D8u)
+
+/** \brief 804C, TOM Channel CCU0 Compare Register */
+#define GTM_TOM0_CH1_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF010804Cu)
+
+/** \brief 8050, TOM Channel CCU1 Compare Register */
+#define GTM_TOM0_CH1_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF0108050u)
+
+/** \brief 8054, TOM Channel CCU0 Counter Register */
+#define GTM_TOM0_CH1_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF0108054u)
+
+/** \brief 8040, TOM Channel Control Register’ */
+#define GTM_TOM0_CH1_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF0108040u)
+
+/** \brief 8060, TOM Channel Interrupt Enable Register */
+#define GTM_TOM0_CH1_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF0108060u)
+
+/** \brief 8064, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM0_CH1_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF0108064u)
+
+/** \brief 8068, TOM IRQ Mode Configuration Register */
+#define GTM_TOM0_CH1_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF0108068u)
+
+/** \brief 805C, TOM Channel Interrupt Notification Register */
+#define GTM_TOM0_CH1_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF010805Cu)
+
+/** \brief 8044, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM0_CH1_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF0108044u)
+
+/** \brief 8048, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM0_CH1_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF0108048u)
+
+/** \brief 8058, TOM Channel Status Register */
+#define GTM_TOM0_CH1_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF0108058u)
+
+/** \brief 808C, TOM Channel CCU0 Compare Register */
+#define GTM_TOM0_CH2_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF010808Cu)
+
+/** \brief 8090, TOM Channel CCU1 Compare Register */
+#define GTM_TOM0_CH2_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF0108090u)
+
+/** \brief 8094, TOM Channel CCU0 Counter Register */
+#define GTM_TOM0_CH2_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF0108094u)
+
+/** \brief 8080, TOM Channel Control Register’ */
+#define GTM_TOM0_CH2_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF0108080u)
+
+/** \brief 80A0, TOM Channel Interrupt Enable Register */
+#define GTM_TOM0_CH2_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF01080A0u)
+
+/** \brief 80A4, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM0_CH2_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF01080A4u)
+
+/** \brief 80A8, TOM IRQ Mode Configuration Register */
+#define GTM_TOM0_CH2_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF01080A8u)
+
+/** \brief 809C, TOM Channel Interrupt Notification Register */
+#define GTM_TOM0_CH2_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF010809Cu)
+
+/** \brief 8084, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM0_CH2_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF0108084u)
+
+/** \brief 8088, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM0_CH2_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF0108088u)
+
+/** \brief 8098, TOM Channel Status Register */
+#define GTM_TOM0_CH2_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF0108098u)
+
+/** \brief 80CC, TOM Channel CCU0 Compare Register */
+#define GTM_TOM0_CH3_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF01080CCu)
+
+/** \brief 80D0, TOM Channel CCU1 Compare Register */
+#define GTM_TOM0_CH3_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF01080D0u)
+
+/** \brief 80D4, TOM Channel CCU0 Counter Register */
+#define GTM_TOM0_CH3_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF01080D4u)
+
+/** \brief 80C0, TOM Channel Control Register’ */
+#define GTM_TOM0_CH3_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF01080C0u)
+
+/** \brief 80E0, TOM Channel Interrupt Enable Register */
+#define GTM_TOM0_CH3_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF01080E0u)
+
+/** \brief 80E4, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM0_CH3_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF01080E4u)
+
+/** \brief 80E8, TOM IRQ Mode Configuration Register */
+#define GTM_TOM0_CH3_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF01080E8u)
+
+/** \brief 80DC, TOM Channel Interrupt Notification Register */
+#define GTM_TOM0_CH3_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF01080DCu)
+
+/** \brief 80C4, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM0_CH3_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF01080C4u)
+
+/** \brief 80C8, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM0_CH3_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF01080C8u)
+
+/** \brief 80D8, TOM Channel Status Register */
+#define GTM_TOM0_CH3_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF01080D8u)
+
+/** \brief 810C, TOM Channel CCU0 Compare Register */
+#define GTM_TOM0_CH4_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF010810Cu)
+
+/** \brief 8110, TOM Channel CCU1 Compare Register */
+#define GTM_TOM0_CH4_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF0108110u)
+
+/** \brief 8114, TOM Channel CCU0 Counter Register */
+#define GTM_TOM0_CH4_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF0108114u)
+
+/** \brief 8100, TOM Channel Control Register’ */
+#define GTM_TOM0_CH4_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF0108100u)
+
+/** \brief 8120, TOM Channel Interrupt Enable Register */
+#define GTM_TOM0_CH4_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF0108120u)
+
+/** \brief 8124, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM0_CH4_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF0108124u)
+
+/** \brief 8128, TOM IRQ Mode Configuration Register */
+#define GTM_TOM0_CH4_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF0108128u)
+
+/** \brief 811C, TOM Channel Interrupt Notification Register */
+#define GTM_TOM0_CH4_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF010811Cu)
+
+/** \brief 8104, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM0_CH4_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF0108104u)
+
+/** \brief 8108, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM0_CH4_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF0108108u)
+
+/** \brief 8118, TOM Channel Status Register */
+#define GTM_TOM0_CH4_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF0108118u)
+
+/** \brief 814C, TOM Channel CCU0 Compare Register */
+#define GTM_TOM0_CH5_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF010814Cu)
+
+/** \brief 8150, TOM Channel CCU1 Compare Register */
+#define GTM_TOM0_CH5_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF0108150u)
+
+/** \brief 8154, TOM Channel CCU0 Counter Register */
+#define GTM_TOM0_CH5_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF0108154u)
+
+/** \brief 8140, TOM Channel Control Register’ */
+#define GTM_TOM0_CH5_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF0108140u)
+
+/** \brief 8160, TOM Channel Interrupt Enable Register */
+#define GTM_TOM0_CH5_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF0108160u)
+
+/** \brief 8164, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM0_CH5_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF0108164u)
+
+/** \brief 8168, TOM IRQ Mode Configuration Register */
+#define GTM_TOM0_CH5_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF0108168u)
+
+/** \brief 815C, TOM Channel Interrupt Notification Register */
+#define GTM_TOM0_CH5_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF010815Cu)
+
+/** \brief 8144, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM0_CH5_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF0108144u)
+
+/** \brief 8148, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM0_CH5_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF0108148u)
+
+/** \brief 8158, TOM Channel Status Register */
+#define GTM_TOM0_CH5_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF0108158u)
+
+/** \brief 818C, TOM Channel CCU0 Compare Register */
+#define GTM_TOM0_CH6_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF010818Cu)
+
+/** \brief 8190, TOM Channel CCU1 Compare Register */
+#define GTM_TOM0_CH6_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF0108190u)
+
+/** \brief 8194, TOM Channel CCU0 Counter Register */
+#define GTM_TOM0_CH6_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF0108194u)
+
+/** \brief 8180, TOM Channel Control Register’ */
+#define GTM_TOM0_CH6_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF0108180u)
+
+/** \brief 81A0, TOM Channel Interrupt Enable Register */
+#define GTM_TOM0_CH6_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF01081A0u)
+
+/** \brief 81A4, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM0_CH6_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF01081A4u)
+
+/** \brief 81A8, TOM IRQ Mode Configuration Register */
+#define GTM_TOM0_CH6_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF01081A8u)
+
+/** \brief 819C, TOM Channel Interrupt Notification Register */
+#define GTM_TOM0_CH6_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF010819Cu)
+
+/** \brief 8184, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM0_CH6_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF0108184u)
+
+/** \brief 8188, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM0_CH6_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF0108188u)
+
+/** \brief 8198, TOM Channel Status Register */
+#define GTM_TOM0_CH6_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF0108198u)
+
+/** \brief 81CC, TOM Channel CCU0 Compare Register */
+#define GTM_TOM0_CH7_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF01081CCu)
+
+/** \brief 81D0, TOM Channel CCU1 Compare Register */
+#define GTM_TOM0_CH7_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF01081D0u)
+
+/** \brief 81D4, TOM Channel CCU0 Counter Register */
+#define GTM_TOM0_CH7_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF01081D4u)
+
+/** \brief 81C0, TOM Channel Control Register’ */
+#define GTM_TOM0_CH7_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF01081C0u)
+
+/** \brief 81E0, TOM Channel Interrupt Enable Register */
+#define GTM_TOM0_CH7_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF01081E0u)
+
+/** \brief 81E4, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM0_CH7_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF01081E4u)
+
+/** \brief 81E8, TOM IRQ Mode Configuration Register */
+#define GTM_TOM0_CH7_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF01081E8u)
+
+/** \brief 81DC, TOM Channel Interrupt Notification Register */
+#define GTM_TOM0_CH7_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF01081DCu)
+
+/** \brief 81C4, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM0_CH7_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF01081C4u)
+
+/** \brief 81C8, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM0_CH7_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF01081C8u)
+
+/** \brief 81D8, TOM Channel Status Register */
+#define GTM_TOM0_CH7_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF01081D8u)
+
+/** \brief 820C, TOM Channel CCU0 Compare Register */
+#define GTM_TOM0_CH8_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF010820Cu)
+
+/** \brief 8210, TOM Channel CCU1 Compare Register */
+#define GTM_TOM0_CH8_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF0108210u)
+
+/** \brief 8214, TOM Channel CCU0 Counter Register */
+#define GTM_TOM0_CH8_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF0108214u)
+
+/** \brief 8200, TOM Channel Control Register’ */
+#define GTM_TOM0_CH8_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF0108200u)
+
+/** \brief 8220, TOM Channel Interrupt Enable Register */
+#define GTM_TOM0_CH8_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF0108220u)
+
+/** \brief 8224, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM0_CH8_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF0108224u)
+
+/** \brief 8228, TOM IRQ Mode Configuration Register */
+#define GTM_TOM0_CH8_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF0108228u)
+
+/** \brief 821C, TOM Channel Interrupt Notification Register */
+#define GTM_TOM0_CH8_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF010821Cu)
+
+/** \brief 8204, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM0_CH8_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF0108204u)
+
+/** \brief 8208, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM0_CH8_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF0108208u)
+
+/** \brief 8218, TOM Channel Status Register */
+#define GTM_TOM0_CH8_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF0108218u)
+
+/** \brief 824C, TOM Channel CCU0 Compare Register */
+#define GTM_TOM0_CH9_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF010824Cu)
+
+/** \brief 8250, TOM Channel CCU1 Compare Register */
+#define GTM_TOM0_CH9_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF0108250u)
+
+/** \brief 8254, TOM Channel CCU0 Counter Register */
+#define GTM_TOM0_CH9_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF0108254u)
+
+/** \brief 8240, TOM Channel Control Register’ */
+#define GTM_TOM0_CH9_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF0108240u)
+
+/** \brief 8260, TOM Channel Interrupt Enable Register */
+#define GTM_TOM0_CH9_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF0108260u)
+
+/** \brief 8264, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM0_CH9_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF0108264u)
+
+/** \brief 8268, TOM IRQ Mode Configuration Register */
+#define GTM_TOM0_CH9_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF0108268u)
+
+/** \brief 825C, TOM Channel Interrupt Notification Register */
+#define GTM_TOM0_CH9_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF010825Cu)
+
+/** \brief 8244, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM0_CH9_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF0108244u)
+
+/** \brief 8248, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM0_CH9_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF0108248u)
+
+/** \brief 8258, TOM Channel Status Register */
+#define GTM_TOM0_CH9_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF0108258u)
+
+/** \brief 8034, TOM TGC0 Action Time Base Register */
+#define GTM_TOM0_TGC0_ACT_TB /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC0_ACT_TB*)0xF0108034u)
+
+/** \brief 8070, TOM TGC0 Enable/Disable Control Register */
+#define GTM_TOM0_TGC0_ENDIS_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC0_ENDIS_CTRL*)0xF0108070u)
+
+/** \brief 8074, TOM TGC0 Enable/Disable Status Register */
+#define GTM_TOM0_TGC0_ENDIS_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC0_ENDIS_STAT*)0xF0108074u)
+
+/** \brief 8038, TOM TGC0 Force Update Control Register */
+#define GTM_TOM0_TGC0_FUPD_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC0_FUPD_CTRL*)0xF0108038u)
+
+/** \brief 8030, TOM TGC0 Global Control Register */
+#define GTM_TOM0_TGC0_GLB_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC0_GLB_CTRL*)0xF0108030u)
+
+/** \brief 803C, TOM TGC0 Internal Trigger Control Register */
+#define GTM_TOM0_TGC0_INT_TRIG /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC0_INT_TRIG*)0xF010803Cu)
+
+/** \brief 8078, TOM TGC0 Output Enable Control Register */
+#define GTM_TOM0_TGC0_OUTEN_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC0_OUTEN_CTRL*)0xF0108078u)
+
+/** \brief 807C, TOM TGC0 Output Enable Status Register */
+#define GTM_TOM0_TGC0_OUTEN_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC0_OUTEN_STAT*)0xF010807Cu)
+
+/** \brief 8234, TOM TGC1 Action Time Base Register */
+#define GTM_TOM0_TGC1_ACT_TB /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC1_ACT_TB*)0xF0108234u)
+
+/** \brief 8270, TOM TGC1 Enable/Disable Control Register */
+#define GTM_TOM0_TGC1_ENDIS_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC1_ENDIS_CTRL*)0xF0108270u)
+
+/** \brief 8274, TOM TGC1 Enable/Disable Status Register */
+#define GTM_TOM0_TGC1_ENDIS_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC1_ENDIS_STAT*)0xF0108274u)
+
+/** \brief 8238, TOM TGC1 Force Update Control Register */
+#define GTM_TOM0_TGC1_FUPD_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC1_FUPD_CTRL*)0xF0108238u)
+
+/** \brief 8230, TOM TGC1 Global Control Register */
+#define GTM_TOM0_TGC1_GLB_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC1_GLB_CTRL*)0xF0108230u)
+
+/** \brief 823C, TOM TGC1 Internal Trigger Control Register */
+#define GTM_TOM0_TGC1_INT_TRIG /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC1_INT_TRIG*)0xF010823Cu)
+
+/** \brief 8278, TOM TGC1 Output Enable Control Register */
+#define GTM_TOM0_TGC1_OUTEN_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC1_OUTEN_CTRL*)0xF0108278u)
+
+/** \brief 827C, TOM TGC1 Output Enable Status Register */
+#define GTM_TOM0_TGC1_OUTEN_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC1_OUTEN_STAT*)0xF010827Cu)
+
+/** \brief 880C, TOM Channel CCU0 Compare Register */
+#define GTM_TOM1_CH0_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF010880Cu)
+
+/** \brief 8810, TOM Channel CCU1 Compare Register */
+#define GTM_TOM1_CH0_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF0108810u)
+
+/** \brief 8814, TOM Channel CCU0 Counter Register */
+#define GTM_TOM1_CH0_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF0108814u)
+
+/** \brief 8800, TOM Channel Control Register’ */
+#define GTM_TOM1_CH0_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF0108800u)
+
+/** \brief 8820, TOM Channel Interrupt Enable Register */
+#define GTM_TOM1_CH0_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF0108820u)
+
+/** \brief 8824, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM1_CH0_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF0108824u)
+
+/** \brief 8828, TOM IRQ Mode Configuration Register */
+#define GTM_TOM1_CH0_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF0108828u)
+
+/** \brief 881C, TOM Channel Interrupt Notification Register */
+#define GTM_TOM1_CH0_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF010881Cu)
+
+/** \brief 8804, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM1_CH0_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF0108804u)
+
+/** \brief 8808, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM1_CH0_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF0108808u)
+
+/** \brief 8818, TOM Channel Status Register */
+#define GTM_TOM1_CH0_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF0108818u)
+
+/** \brief 8A8C, TOM Channel CCU0 Compare Register */
+#define GTM_TOM1_CH10_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF0108A8Cu)
+
+/** \brief 8A90, TOM Channel CCU1 Compare Register */
+#define GTM_TOM1_CH10_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF0108A90u)
+
+/** \brief 8A94, TOM Channel CCU0 Counter Register */
+#define GTM_TOM1_CH10_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF0108A94u)
+
+/** \brief 8A80, TOM Channel Control Register’ */
+#define GTM_TOM1_CH10_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF0108A80u)
+
+/** \brief 8AA0, TOM Channel Interrupt Enable Register */
+#define GTM_TOM1_CH10_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF0108AA0u)
+
+/** \brief 8AA4, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM1_CH10_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF0108AA4u)
+
+/** \brief 8AA8, TOM IRQ Mode Configuration Register */
+#define GTM_TOM1_CH10_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF0108AA8u)
+
+/** \brief 8A9C, TOM Channel Interrupt Notification Register */
+#define GTM_TOM1_CH10_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF0108A9Cu)
+
+/** \brief 8A84, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM1_CH10_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF0108A84u)
+
+/** \brief 8A88, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM1_CH10_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF0108A88u)
+
+/** \brief 8A98, TOM Channel Status Register */
+#define GTM_TOM1_CH10_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF0108A98u)
+
+/** \brief 8ACC, TOM Channel CCU0 Compare Register */
+#define GTM_TOM1_CH11_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF0108ACCu)
+
+/** \brief 8AD0, TOM Channel CCU1 Compare Register */
+#define GTM_TOM1_CH11_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF0108AD0u)
+
+/** \brief 8AD4, TOM Channel CCU0 Counter Register */
+#define GTM_TOM1_CH11_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF0108AD4u)
+
+/** \brief 8AC0, TOM Channel Control Register’ */
+#define GTM_TOM1_CH11_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF0108AC0u)
+
+/** \brief 8AE0, TOM Channel Interrupt Enable Register */
+#define GTM_TOM1_CH11_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF0108AE0u)
+
+/** \brief 8AE4, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM1_CH11_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF0108AE4u)
+
+/** \brief 8AE8, TOM IRQ Mode Configuration Register */
+#define GTM_TOM1_CH11_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF0108AE8u)
+
+/** \brief 8ADC, TOM Channel Interrupt Notification Register */
+#define GTM_TOM1_CH11_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF0108ADCu)
+
+/** \brief 8AC4, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM1_CH11_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF0108AC4u)
+
+/** \brief 8AC8, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM1_CH11_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF0108AC8u)
+
+/** \brief 8AD8, TOM Channel Status Register */
+#define GTM_TOM1_CH11_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF0108AD8u)
+
+/** \brief 8B0C, TOM Channel CCU0 Compare Register */
+#define GTM_TOM1_CH12_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF0108B0Cu)
+
+/** \brief 8B10, TOM Channel CCU1 Compare Register */
+#define GTM_TOM1_CH12_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF0108B10u)
+
+/** \brief 8B14, TOM Channel CCU0 Counter Register */
+#define GTM_TOM1_CH12_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF0108B14u)
+
+/** \brief 8B00, TOM Channel Control Register’ */
+#define GTM_TOM1_CH12_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF0108B00u)
+
+/** \brief 8B20, TOM Channel Interrupt Enable Register */
+#define GTM_TOM1_CH12_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF0108B20u)
+
+/** \brief 8B24, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM1_CH12_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF0108B24u)
+
+/** \brief 8B28, TOM IRQ Mode Configuration Register */
+#define GTM_TOM1_CH12_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF0108B28u)
+
+/** \brief 8B1C, TOM Channel Interrupt Notification Register */
+#define GTM_TOM1_CH12_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF0108B1Cu)
+
+/** \brief 8B04, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM1_CH12_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF0108B04u)
+
+/** \brief 8B08, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM1_CH12_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF0108B08u)
+
+/** \brief 8B18, TOM Channel Status Register */
+#define GTM_TOM1_CH12_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF0108B18u)
+
+/** \brief 8B4C, TOM Channel CCU0 Compare Register */
+#define GTM_TOM1_CH13_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF0108B4Cu)
+
+/** \brief 8B50, TOM Channel CCU1 Compare Register */
+#define GTM_TOM1_CH13_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF0108B50u)
+
+/** \brief 8B54, TOM Channel CCU0 Counter Register */
+#define GTM_TOM1_CH13_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF0108B54u)
+
+/** \brief 8B40, TOM Channel Control Register’ */
+#define GTM_TOM1_CH13_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF0108B40u)
+
+/** \brief 8B60, TOM Channel Interrupt Enable Register */
+#define GTM_TOM1_CH13_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF0108B60u)
+
+/** \brief 8B64, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM1_CH13_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF0108B64u)
+
+/** \brief 8B68, TOM IRQ Mode Configuration Register */
+#define GTM_TOM1_CH13_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF0108B68u)
+
+/** \brief 8B5C, TOM Channel Interrupt Notification Register */
+#define GTM_TOM1_CH13_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF0108B5Cu)
+
+/** \brief 8B44, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM1_CH13_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF0108B44u)
+
+/** \brief 8B48, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM1_CH13_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF0108B48u)
+
+/** \brief 8B58, TOM Channel Status Register */
+#define GTM_TOM1_CH13_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF0108B58u)
+
+/** \brief 8B8C, TOM Channel CCU0 Compare Register */
+#define GTM_TOM1_CH14_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF0108B8Cu)
+
+/** \brief 8B90, TOM Channel CCU1 Compare Register */
+#define GTM_TOM1_CH14_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF0108B90u)
+
+/** \brief 8B94, TOM Channel CCU0 Counter Register */
+#define GTM_TOM1_CH14_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF0108B94u)
+
+/** \brief 8B80, TOM Channel Control Register’ */
+#define GTM_TOM1_CH14_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF0108B80u)
+
+/** \brief 8BA0, TOM Channel Interrupt Enable Register */
+#define GTM_TOM1_CH14_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF0108BA0u)
+
+/** \brief 8BA4, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM1_CH14_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF0108BA4u)
+
+/** \brief 8BA8, TOM IRQ Mode Configuration Register */
+#define GTM_TOM1_CH14_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF0108BA8u)
+
+/** \brief 8B9C, TOM Channel Interrupt Notification Register */
+#define GTM_TOM1_CH14_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF0108B9Cu)
+
+/** \brief 8B84, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM1_CH14_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF0108B84u)
+
+/** \brief 8B88, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM1_CH14_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF0108B88u)
+
+/** \brief 8B98, TOM Channel Status Register */
+#define GTM_TOM1_CH14_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF0108B98u)
+
+/** \brief 8BCC, TOM Channel CCU0 Compare Register */
+#define GTM_TOM1_CH15_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF0108BCCu)
+
+/** \brief 8BD0, TOM Channel CCU1 Compare Register */
+#define GTM_TOM1_CH15_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF0108BD0u)
+
+/** \brief 8BD4, TOM Channel CCU0 Counter Register */
+#define GTM_TOM1_CH15_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF0108BD4u)
+
+/** \brief 8BC0, TOM Channel Control Register’ */
+#define GTM_TOM1_CH15_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF0108BC0u)
+
+/** \brief 8BE0, TOM Channel Interrupt Enable Register */
+#define GTM_TOM1_CH15_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF0108BE0u)
+
+/** \brief 8BE4, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM1_CH15_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF0108BE4u)
+
+/** \brief 8BE8, TOM IRQ Mode Configuration Register */
+#define GTM_TOM1_CH15_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF0108BE8u)
+
+/** \brief 8BDC, TOM Channel Interrupt Notification Register */
+#define GTM_TOM1_CH15_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF0108BDCu)
+
+/** \brief 8BC4, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM1_CH15_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF0108BC4u)
+
+/** \brief 8BC8, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM1_CH15_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF0108BC8u)
+
+/** \brief 8BD8, TOM Channel Status Register */
+#define GTM_TOM1_CH15_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF0108BD8u)
+
+/** \brief 884C, TOM Channel CCU0 Compare Register */
+#define GTM_TOM1_CH1_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF010884Cu)
+
+/** \brief 8850, TOM Channel CCU1 Compare Register */
+#define GTM_TOM1_CH1_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF0108850u)
+
+/** \brief 8854, TOM Channel CCU0 Counter Register */
+#define GTM_TOM1_CH1_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF0108854u)
+
+/** \brief 8840, TOM Channel Control Register’ */
+#define GTM_TOM1_CH1_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF0108840u)
+
+/** \brief 8860, TOM Channel Interrupt Enable Register */
+#define GTM_TOM1_CH1_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF0108860u)
+
+/** \brief 8864, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM1_CH1_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF0108864u)
+
+/** \brief 8868, TOM IRQ Mode Configuration Register */
+#define GTM_TOM1_CH1_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF0108868u)
+
+/** \brief 885C, TOM Channel Interrupt Notification Register */
+#define GTM_TOM1_CH1_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF010885Cu)
+
+/** \brief 8844, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM1_CH1_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF0108844u)
+
+/** \brief 8848, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM1_CH1_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF0108848u)
+
+/** \brief 8858, TOM Channel Status Register */
+#define GTM_TOM1_CH1_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF0108858u)
+
+/** \brief 888C, TOM Channel CCU0 Compare Register */
+#define GTM_TOM1_CH2_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF010888Cu)
+
+/** \brief 8890, TOM Channel CCU1 Compare Register */
+#define GTM_TOM1_CH2_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF0108890u)
+
+/** \brief 8894, TOM Channel CCU0 Counter Register */
+#define GTM_TOM1_CH2_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF0108894u)
+
+/** \brief 8880, TOM Channel Control Register’ */
+#define GTM_TOM1_CH2_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF0108880u)
+
+/** \brief 88A0, TOM Channel Interrupt Enable Register */
+#define GTM_TOM1_CH2_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF01088A0u)
+
+/** \brief 88A4, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM1_CH2_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF01088A4u)
+
+/** \brief 88A8, TOM IRQ Mode Configuration Register */
+#define GTM_TOM1_CH2_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF01088A8u)
+
+/** \brief 889C, TOM Channel Interrupt Notification Register */
+#define GTM_TOM1_CH2_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF010889Cu)
+
+/** \brief 8884, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM1_CH2_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF0108884u)
+
+/** \brief 8888, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM1_CH2_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF0108888u)
+
+/** \brief 8898, TOM Channel Status Register */
+#define GTM_TOM1_CH2_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF0108898u)
+
+/** \brief 88CC, TOM Channel CCU0 Compare Register */
+#define GTM_TOM1_CH3_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF01088CCu)
+
+/** \brief 88D0, TOM Channel CCU1 Compare Register */
+#define GTM_TOM1_CH3_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF01088D0u)
+
+/** \brief 88D4, TOM Channel CCU0 Counter Register */
+#define GTM_TOM1_CH3_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF01088D4u)
+
+/** \brief 88C0, TOM Channel Control Register’ */
+#define GTM_TOM1_CH3_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF01088C0u)
+
+/** \brief 88E0, TOM Channel Interrupt Enable Register */
+#define GTM_TOM1_CH3_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF01088E0u)
+
+/** \brief 88E4, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM1_CH3_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF01088E4u)
+
+/** \brief 88E8, TOM IRQ Mode Configuration Register */
+#define GTM_TOM1_CH3_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF01088E8u)
+
+/** \brief 88DC, TOM Channel Interrupt Notification Register */
+#define GTM_TOM1_CH3_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF01088DCu)
+
+/** \brief 88C4, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM1_CH3_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF01088C4u)
+
+/** \brief 88C8, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM1_CH3_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF01088C8u)
+
+/** \brief 88D8, TOM Channel Status Register */
+#define GTM_TOM1_CH3_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF01088D8u)
+
+/** \brief 890C, TOM Channel CCU0 Compare Register */
+#define GTM_TOM1_CH4_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF010890Cu)
+
+/** \brief 8910, TOM Channel CCU1 Compare Register */
+#define GTM_TOM1_CH4_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF0108910u)
+
+/** \brief 8914, TOM Channel CCU0 Counter Register */
+#define GTM_TOM1_CH4_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF0108914u)
+
+/** \brief 8900, TOM Channel Control Register’ */
+#define GTM_TOM1_CH4_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF0108900u)
+
+/** \brief 8920, TOM Channel Interrupt Enable Register */
+#define GTM_TOM1_CH4_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF0108920u)
+
+/** \brief 8924, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM1_CH4_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF0108924u)
+
+/** \brief 8928, TOM IRQ Mode Configuration Register */
+#define GTM_TOM1_CH4_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF0108928u)
+
+/** \brief 891C, TOM Channel Interrupt Notification Register */
+#define GTM_TOM1_CH4_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF010891Cu)
+
+/** \brief 8904, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM1_CH4_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF0108904u)
+
+/** \brief 8908, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM1_CH4_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF0108908u)
+
+/** \brief 8918, TOM Channel Status Register */
+#define GTM_TOM1_CH4_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF0108918u)
+
+/** \brief 894C, TOM Channel CCU0 Compare Register */
+#define GTM_TOM1_CH5_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF010894Cu)
+
+/** \brief 8950, TOM Channel CCU1 Compare Register */
+#define GTM_TOM1_CH5_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF0108950u)
+
+/** \brief 8954, TOM Channel CCU0 Counter Register */
+#define GTM_TOM1_CH5_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF0108954u)
+
+/** \brief 8940, TOM Channel Control Register’ */
+#define GTM_TOM1_CH5_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF0108940u)
+
+/** \brief 8960, TOM Channel Interrupt Enable Register */
+#define GTM_TOM1_CH5_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF0108960u)
+
+/** \brief 8964, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM1_CH5_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF0108964u)
+
+/** \brief 8968, TOM IRQ Mode Configuration Register */
+#define GTM_TOM1_CH5_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF0108968u)
+
+/** \brief 895C, TOM Channel Interrupt Notification Register */
+#define GTM_TOM1_CH5_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF010895Cu)
+
+/** \brief 8944, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM1_CH5_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF0108944u)
+
+/** \brief 8948, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM1_CH5_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF0108948u)
+
+/** \brief 8958, TOM Channel Status Register */
+#define GTM_TOM1_CH5_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF0108958u)
+
+/** \brief 898C, TOM Channel CCU0 Compare Register */
+#define GTM_TOM1_CH6_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF010898Cu)
+
+/** \brief 8990, TOM Channel CCU1 Compare Register */
+#define GTM_TOM1_CH6_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF0108990u)
+
+/** \brief 8994, TOM Channel CCU0 Counter Register */
+#define GTM_TOM1_CH6_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF0108994u)
+
+/** \brief 8980, TOM Channel Control Register’ */
+#define GTM_TOM1_CH6_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF0108980u)
+
+/** \brief 89A0, TOM Channel Interrupt Enable Register */
+#define GTM_TOM1_CH6_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF01089A0u)
+
+/** \brief 89A4, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM1_CH6_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF01089A4u)
+
+/** \brief 89A8, TOM IRQ Mode Configuration Register */
+#define GTM_TOM1_CH6_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF01089A8u)
+
+/** \brief 899C, TOM Channel Interrupt Notification Register */
+#define GTM_TOM1_CH6_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF010899Cu)
+
+/** \brief 8984, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM1_CH6_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF0108984u)
+
+/** \brief 8988, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM1_CH6_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF0108988u)
+
+/** \brief 8998, TOM Channel Status Register */
+#define GTM_TOM1_CH6_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF0108998u)
+
+/** \brief 89CC, TOM Channel CCU0 Compare Register */
+#define GTM_TOM1_CH7_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF01089CCu)
+
+/** \brief 89D0, TOM Channel CCU1 Compare Register */
+#define GTM_TOM1_CH7_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF01089D0u)
+
+/** \brief 89D4, TOM Channel CCU0 Counter Register */
+#define GTM_TOM1_CH7_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF01089D4u)
+
+/** \brief 89C0, TOM Channel Control Register’ */
+#define GTM_TOM1_CH7_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF01089C0u)
+
+/** \brief 89E0, TOM Channel Interrupt Enable Register */
+#define GTM_TOM1_CH7_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF01089E0u)
+
+/** \brief 89E4, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM1_CH7_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF01089E4u)
+
+/** \brief 89E8, TOM IRQ Mode Configuration Register */
+#define GTM_TOM1_CH7_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF01089E8u)
+
+/** \brief 89DC, TOM Channel Interrupt Notification Register */
+#define GTM_TOM1_CH7_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF01089DCu)
+
+/** \brief 89C4, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM1_CH7_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF01089C4u)
+
+/** \brief 89C8, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM1_CH7_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF01089C8u)
+
+/** \brief 89D8, TOM Channel Status Register */
+#define GTM_TOM1_CH7_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF01089D8u)
+
+/** \brief 8A0C, TOM Channel CCU0 Compare Register */
+#define GTM_TOM1_CH8_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF0108A0Cu)
+
+/** \brief 8A10, TOM Channel CCU1 Compare Register */
+#define GTM_TOM1_CH8_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF0108A10u)
+
+/** \brief 8A14, TOM Channel CCU0 Counter Register */
+#define GTM_TOM1_CH8_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF0108A14u)
+
+/** \brief 8A00, TOM Channel Control Register’ */
+#define GTM_TOM1_CH8_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF0108A00u)
+
+/** \brief 8A20, TOM Channel Interrupt Enable Register */
+#define GTM_TOM1_CH8_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF0108A20u)
+
+/** \brief 8A24, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM1_CH8_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF0108A24u)
+
+/** \brief 8A28, TOM IRQ Mode Configuration Register */
+#define GTM_TOM1_CH8_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF0108A28u)
+
+/** \brief 8A1C, TOM Channel Interrupt Notification Register */
+#define GTM_TOM1_CH8_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF0108A1Cu)
+
+/** \brief 8A04, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM1_CH8_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF0108A04u)
+
+/** \brief 8A08, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM1_CH8_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF0108A08u)
+
+/** \brief 8A18, TOM Channel Status Register */
+#define GTM_TOM1_CH8_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF0108A18u)
+
+/** \brief 8A4C, TOM Channel CCU0 Compare Register */
+#define GTM_TOM1_CH9_CM0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM0*)0xF0108A4Cu)
+
+/** \brief 8A50, TOM Channel CCU1 Compare Register */
+#define GTM_TOM1_CH9_CM1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CM1*)0xF0108A50u)
+
+/** \brief 8A54, TOM Channel CCU0 Counter Register */
+#define GTM_TOM1_CH9_CN0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CN0*)0xF0108A54u)
+
+/** \brief 8A40, TOM Channel Control Register’ */
+#define GTM_TOM1_CH9_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_CTRL*)0xF0108A40u)
+
+/** \brief 8A60, TOM Channel Interrupt Enable Register */
+#define GTM_TOM1_CH9_IRQ_EN /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_EN*)0xF0108A60u)
+
+/** \brief 8A64, TOM Channel Software Interrupt Generation Register */
+#define GTM_TOM1_CH9_IRQ_FORCINT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_FORCINT*)0xF0108A64u)
+
+/** \brief 8A68, TOM IRQ Mode Configuration Register */
+#define GTM_TOM1_CH9_IRQ_MODE /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_MODE*)0xF0108A68u)
+
+/** \brief 8A5C, TOM Channel Interrupt Notification Register */
+#define GTM_TOM1_CH9_IRQ_NOTIFY /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_IRQ_NOTIFY*)0xF0108A5Cu)
+
+/** \brief 8A44, TOM Channel CCU0 Compare Shadow Register */
+#define GTM_TOM1_CH9_SR0 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR0*)0xF0108A44u)
+
+/** \brief 8A48, TOM Channel CCU1 Compare Shadow Register */
+#define GTM_TOM1_CH9_SR1 /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_SR1*)0xF0108A48u)
+
+/** \brief 8A58, TOM Channel Status Register */
+#define GTM_TOM1_CH9_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_CH_STAT*)0xF0108A58u)
+
+/** \brief 8834, TOM TGC0 Action Time Base Register */
+#define GTM_TOM1_TGC0_ACT_TB /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC0_ACT_TB*)0xF0108834u)
+
+/** \brief 8870, TOM TGC0 Enable/Disable Control Register */
+#define GTM_TOM1_TGC0_ENDIS_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC0_ENDIS_CTRL*)0xF0108870u)
+
+/** \brief 8874, TOM TGC0 Enable/Disable Status Register */
+#define GTM_TOM1_TGC0_ENDIS_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC0_ENDIS_STAT*)0xF0108874u)
+
+/** \brief 8838, TOM TGC0 Force Update Control Register */
+#define GTM_TOM1_TGC0_FUPD_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC0_FUPD_CTRL*)0xF0108838u)
+
+/** \brief 8830, TOM TGC0 Global Control Register */
+#define GTM_TOM1_TGC0_GLB_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC0_GLB_CTRL*)0xF0108830u)
+
+/** \brief 883C, TOM TGC0 Internal Trigger Control Register */
+#define GTM_TOM1_TGC0_INT_TRIG /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC0_INT_TRIG*)0xF010883Cu)
+
+/** \brief 8878, TOM TGC0 Output Enable Control Register */
+#define GTM_TOM1_TGC0_OUTEN_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC0_OUTEN_CTRL*)0xF0108878u)
+
+/** \brief 887C, TOM TGC0 Output Enable Status Register */
+#define GTM_TOM1_TGC0_OUTEN_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC0_OUTEN_STAT*)0xF010887Cu)
+
+/** \brief 8A34, TOM TGC1 Action Time Base Register */
+#define GTM_TOM1_TGC1_ACT_TB /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC1_ACT_TB*)0xF0108A34u)
+
+/** \brief 8A70, TOM TGC1 Enable/Disable Control Register */
+#define GTM_TOM1_TGC1_ENDIS_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC1_ENDIS_CTRL*)0xF0108A70u)
+
+/** \brief 8A74, TOM TGC1 Enable/Disable Status Register */
+#define GTM_TOM1_TGC1_ENDIS_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC1_ENDIS_STAT*)0xF0108A74u)
+
+/** \brief 8A38, TOM TGC1 Force Update Control Register */
+#define GTM_TOM1_TGC1_FUPD_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC1_FUPD_CTRL*)0xF0108A38u)
+
+/** \brief 8A30, TOM TGC1 Global Control Register */
+#define GTM_TOM1_TGC1_GLB_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC1_GLB_CTRL*)0xF0108A30u)
+
+/** \brief 8A3C, TOM TGC1 Internal Trigger Control Register */
+#define GTM_TOM1_TGC1_INT_TRIG /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC1_INT_TRIG*)0xF0108A3Cu)
+
+/** \brief 8A78, TOM TGC1 Output Enable Control Register */
+#define GTM_TOM1_TGC1_OUTEN_CTRL /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC1_OUTEN_CTRL*)0xF0108A78u)
+
+/** \brief 8A7C, TOM TGC1 Output Enable Status Register */
+#define GTM_TOM1_TGC1_OUTEN_STAT /*lint --e(923)*/ (*(volatile Ifx_GTM_TOM_TGC1_OUTEN_STAT*)0xF0108A7Cu)
+
+/** \brief 9FE04, Trigger Output Register */
+#define GTM_TRIGOUT00 /*lint --e(923)*/ (*(volatile Ifx_GTM_TRIGOUT*)0xF019FE04u)
+
+/** \brief 9FE08, Trigger Output Register */
+#define GTM_TRIGOUT01 /*lint --e(923)*/ (*(volatile Ifx_GTM_TRIGOUT*)0xF019FE08u)
+
+/** \brief 9FE0C, Trigger Output Register */
+#define GTM_TRIGOUT02 /*lint --e(923)*/ (*(volatile Ifx_GTM_TRIGOUT*)0xF019FE0Cu)
+
+/** \brief 9FE44, Trigger Output Register */
+#define GTM_TRIGOUT10 /*lint --e(923)*/ (*(volatile Ifx_GTM_TRIGOUT*)0xF019FE44u)
+
+/** \brief 9FE48, Trigger Output Register */
+#define GTM_TRIGOUT11 /*lint --e(923)*/ (*(volatile Ifx_GTM_TRIGOUT*)0xF019FE48u)
+
+/** \brief 9FE4C, Trigger Output Register */
+#define GTM_TRIGOUT12 /*lint --e(923)*/ (*(volatile Ifx_GTM_TRIGOUT*)0xF019FE4Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXGTM_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxGtm_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxGtm_regdef.h
new file mode 100644
index 0000000..139a15d
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxGtm_regdef.h
@@ -0,0 +1,7844 @@
+/**
+ * \file IfxGtm_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Gtm Gtm
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Gtm_Bitfields Bitfields
+ * \ingroup IfxLld_Gtm
+ *
+ * \defgroup IfxLld_Gtm_union Union
+ * \ingroup IfxLld_Gtm
+ *
+ * \defgroup IfxLld_Gtm_struct Struct
+ * \ingroup IfxLld_Gtm
+ *
+ */
+#ifndef IFXGTM_REGDEF_H
+#define IFXGTM_REGDEF_H 1
+/******************************************************************************/
+#if defined (__TASKING__)
+#pragma warning 586
+#endif
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Gtm_Bitfields
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef struct _Ifx_GTM_ACCEN0_Bits
+{
+ Ifx_Strict_32Bit EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ Ifx_Strict_32Bit EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ Ifx_Strict_32Bit EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ Ifx_Strict_32Bit EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ Ifx_Strict_32Bit EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ Ifx_Strict_32Bit EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ Ifx_Strict_32Bit EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ Ifx_Strict_32Bit EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ Ifx_Strict_32Bit EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ Ifx_Strict_32Bit EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ Ifx_Strict_32Bit EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ Ifx_Strict_32Bit EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ Ifx_Strict_32Bit EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ Ifx_Strict_32Bit EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ Ifx_Strict_32Bit EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ Ifx_Strict_32Bit EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ Ifx_Strict_32Bit EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ Ifx_Strict_32Bit EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ Ifx_Strict_32Bit EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ Ifx_Strict_32Bit EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ Ifx_Strict_32Bit EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ Ifx_Strict_32Bit EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ Ifx_Strict_32Bit EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ Ifx_Strict_32Bit EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ Ifx_Strict_32Bit EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ Ifx_Strict_32Bit EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ Ifx_Strict_32Bit EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ Ifx_Strict_32Bit EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ Ifx_Strict_32Bit EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ Ifx_Strict_32Bit EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ Ifx_Strict_32Bit EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ Ifx_Strict_32Bit EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_GTM_ACCEN0_Bits;
+
+/** \brief Access Enable Register 1 */
+typedef struct _Ifx_GTM_ACCEN1_Bits
+{
+ Ifx_Strict_32Bit reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_GTM_ACCEN1_Bits;
+
+/** \brief ADC Trigger 0 Output Select 0 Register */
+typedef struct _Ifx_GTM_ADCTRIG0OUT0_Bits
+{
+ Ifx_Strict_32Bit SEL0:4; /**< \brief [3:0] Output Selection for ADC0 GTM connection (rw) */
+ Ifx_Strict_32Bit SEL1:4; /**< \brief [7:4] Output Selection for ADC1 GTM connection (rw) */
+ Ifx_Strict_32Bit SEL2:4; /**< \brief [11:8] Output Selection for ADC2 GTM connection (rw) */
+ Ifx_Strict_32Bit SEL3:4; /**< \brief [15:12] Output Selection for ADC3 GTM connection (rw) */
+ Ifx_Strict_32Bit SEL4:4; /**< \brief [19:16] Output Selection for ADC4 GTM connection (rw) */
+ Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_GTM_ADCTRIG0OUT0_Bits;
+
+/** \brief ADC Trigger 1 Output Select 0 Register */
+typedef struct _Ifx_GTM_ADCTRIG1OUT0_Bits
+{
+ Ifx_Strict_32Bit SEL0:4; /**< \brief [3:0] Output Selection for ADC0 GTM connection (rw) */
+ Ifx_Strict_32Bit SEL1:4; /**< \brief [7:4] Output Selection for ADC1 GTM connection (rw) */
+ Ifx_Strict_32Bit SEL2:4; /**< \brief [11:8] Output Selection for ADC2 GTM connection (rw) */
+ Ifx_Strict_32Bit SEL3:4; /**< \brief [15:12] Output Selection for ADC3 GTM connection (rw) */
+ Ifx_Strict_32Bit SEL4:4; /**< \brief [19:16] Output Selection for ADC4 GTM connection (rw) */
+ Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_GTM_ADCTRIG1OUT0_Bits;
+
+/** \brief GTM AEI Timeout Exception Address Register */
+typedef struct _Ifx_GTM_AEI_ADDR_XPT_Bits
+{
+ Ifx_Strict_32Bit TO_ADDR:20; /**< \brief [19:0] AEI Timeout address (r) */
+ Ifx_Strict_32Bit TO_W1R0:1; /**< \brief [20:20] AEI Timeout Read/Write flag (r) */
+ Ifx_Strict_32Bit reserved_21:11; /**< \brief \internal Reserved */
+} Ifx_GTM_AEI_ADDR_XPT_Bits;
+
+/** \brief AFD0 FIFO0 Channel Buffer Access Register */
+typedef struct _Ifx_GTM_AFD_CH_BUF_ACC_Bits
+{
+ Ifx_Strict_32Bit DATA:29; /**< \brief [28:0] Read/write data from/to FIFO (rw) */
+ Ifx_Strict_32Bit reserved_29:3; /**< \brief \internal Reserved */
+} Ifx_GTM_AFD_CH_BUF_ACC_Bits;
+
+/** \brief ARU Access Register */
+typedef struct _Ifx_GTM_ARU_ARU_ACCESS_Bits
+{
+ Ifx_Strict_32Bit ADDR:9; /**< \brief [8:0] ARU address (rw) */
+ Ifx_Strict_32Bit reserved_9:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit RREQ:1; /**< \brief [12:12] Initiate read request (rwh) */
+ Ifx_Strict_32Bit WREQ:1; /**< \brief [13:13] Initiate write request (rwh) */
+ Ifx_Strict_32Bit reserved_14:18; /**< \brief \internal Reserved */
+} Ifx_GTM_ARU_ARU_ACCESS_Bits;
+
+/** \brief ARU Access Register Upper Data Word */
+typedef struct _Ifx_GTM_ARU_DATA_H_Bits
+{
+ Ifx_Strict_32Bit DATA:29; /**< \brief [28:0] Upper ARU data word (rw) */
+ Ifx_Strict_32Bit reserved_29:3; /**< \brief \internal Reserved */
+} Ifx_GTM_ARU_DATA_H_Bits;
+
+/** \brief ARU Access Register Lower Data Word */
+typedef struct _Ifx_GTM_ARU_DATA_L_Bits
+{
+ Ifx_Strict_32Bit DATA:29; /**< \brief [28:0] Lower ARU data word (rw) */
+ Ifx_Strict_32Bit reserved_29:3; /**< \brief \internal Reserved */
+} Ifx_GTM_ARU_DATA_L_Bits;
+
+/** \brief Debug Access Channel 0 */
+typedef struct _Ifx_GTM_ARU_DBG_ACCESS0_Bits
+{
+ Ifx_Strict_32Bit ADDR:9; /**< \brief [8:0] ARU debugging address (rw) */
+ Ifx_Strict_32Bit reserved_9:23; /**< \brief \internal Reserved */
+} Ifx_GTM_ARU_DBG_ACCESS0_Bits;
+
+/** \brief Debug Access Channel 0 */
+typedef struct _Ifx_GTM_ARU_DBG_ACCESS1_Bits
+{
+ Ifx_Strict_32Bit ADDR:9; /**< \brief [8:0] ARU debugging address (rw) */
+ Ifx_Strict_32Bit reserved_9:23; /**< \brief \internal Reserved */
+} Ifx_GTM_ARU_DBG_ACCESS1_Bits;
+
+/** \brief Debug Access 0 Transfer Register Upper Data Word */
+typedef struct _Ifx_GTM_ARU_DBG_DATA0_H_Bits
+{
+ Ifx_Strict_32Bit DATA:29; /**< \brief [28:0] Upper debug data word (r) */
+ Ifx_Strict_32Bit reserved_29:3; /**< \brief \internal Reserved */
+} Ifx_GTM_ARU_DBG_DATA0_H_Bits;
+
+/** \brief Debug Access 0 Transfer Register Lower Data Word */
+typedef struct _Ifx_GTM_ARU_DBG_DATA0_L_Bits
+{
+ Ifx_Strict_32Bit DATA:29; /**< \brief [28:0] Lower debug data word (r) */
+ Ifx_Strict_32Bit reserved_29:3; /**< \brief \internal Reserved */
+} Ifx_GTM_ARU_DBG_DATA0_L_Bits;
+
+/** \brief Debug Access 1 Transfer Register Upper Data Word */
+typedef struct _Ifx_GTM_ARU_DBG_DATA1_H_Bits
+{
+ Ifx_Strict_32Bit DATA:29; /**< \brief [28:0] Upper debug data word (r) */
+ Ifx_Strict_32Bit reserved_29:3; /**< \brief \internal Reserved */
+} Ifx_GTM_ARU_DBG_DATA1_H_Bits;
+
+/** \brief Debug Access 1 Transfer Register Lower Data Word */
+typedef struct _Ifx_GTM_ARU_DBG_DATA1_L_Bits
+{
+ Ifx_Strict_32Bit DATA:29; /**< \brief [28:0] Lower debug data word (r) */
+ Ifx_Strict_32Bit reserved_29:3; /**< \brief \internal Reserved */
+} Ifx_GTM_ARU_DBG_DATA1_L_Bits;
+
+/** \brief ARU Interrupt Enable Register */
+typedef struct _Ifx_GTM_ARU_IRQ_EN_Bits
+{
+ Ifx_Strict_32Bit NEW_DATA0_IRQ_EN:1; /**< \brief [0:0] ARU_NEW_DATA0_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit NEW_DATA1_IRQ_EN:1; /**< \brief [1:1] ARU_NEW_DATA1_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit ACC_ACK_IRQ_EN:1; /**< \brief [2:2] ACC_ACK_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit reserved_3:29; /**< \brief \internal Reserved */
+} Ifx_GTM_ARU_IRQ_EN_Bits;
+
+/** \brief ARU_NEW_DATA_IRQ Forcing Interrupt Register */
+typedef struct _Ifx_GTM_ARU_IRQ_FORCINT_Bits
+{
+ Ifx_Strict_32Bit TRG_NEW_DATA0:1; /**< \brief [0:0] Trigger new data 0 interrupt (w) */
+ Ifx_Strict_32Bit TRG_NEW_DATA:1; /**< \brief [1:1] 1 Trigger new data 1 interrupt (w) */
+ Ifx_Strict_32Bit TRG_ACC_ACK:1; /**< \brief [2:2] Trigger ACC_ACK interrupt (w) */
+ Ifx_Strict_32Bit reserved_3:29; /**< \brief \internal Reserved */
+} Ifx_GTM_ARU_IRQ_FORCINT_Bits;
+
+/** \brief IRQ Mode Configuration Register */
+typedef struct _Ifx_GTM_ARU_IRQ_MODE_Bits
+{
+ Ifx_Strict_32Bit IRQ_MODE:2; /**< \brief [1:0] IRQ mode selection (rw) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_GTM_ARU_IRQ_MODE_Bits;
+
+/** \brief ARU Interrupt Notification Register */
+typedef struct _Ifx_GTM_ARU_IRQ_NOTIFY_Bits
+{
+ Ifx_Strict_32Bit NEW_DATA0:1; /**< \brief [0:0] Data was transferred for addr ARU_DBG_ACCESS0 (rwh) */
+ Ifx_Strict_32Bit NEW_DATA1:1; /**< \brief [1:1] Data was transferred for addr ARU_DBG_ACCESS1 (rwh) */
+ Ifx_Strict_32Bit ACC_ACK:1; /**< \brief [2:2] AEI to ARU access finished, on read access data are valid (rwh) */
+ Ifx_Strict_32Bit reserved_3:29; /**< \brief \internal Reserved */
+} Ifx_GTM_ARU_IRQ_NOTIFY_Bits;
+
+/** \brief TOM TGC0 Action Time Base Register */
+typedef struct _Ifx_GTM_ATOM_AGC_ACT_TB_Bits
+{
+ Ifx_Strict_32Bit ACT_TB:24; /**< \brief [23:0] Time base value (rw) */
+ Ifx_Strict_32Bit TB_TRIG:1; /**< \brief [24:24] Set trigger request (rwh) */
+ Ifx_Strict_32Bit TBU_SEL:2; /**< \brief [26:25] Selection of time base used for comparison (rw) */
+ Ifx_Strict_32Bit reserved_27:5; /**< \brief \internal Reserved */
+} Ifx_GTM_ATOM_AGC_ACT_TB_Bits;
+
+/** \brief ATOM AGC Enable/Disable Control Register */
+typedef struct _Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits
+{
+ Ifx_Strict_32Bit ENDIS_CTRL0:2; /**< \brief [1:0] (A)TOM channel 0 enable/disable update value (rw) */
+ Ifx_Strict_32Bit ENDIS_CTRL1:2; /**< \brief [3:2] (A)TOM channel 1 enable/disable update value (rw) */
+ Ifx_Strict_32Bit ENDIS_CTRL2:2; /**< \brief [5:4] (A)TOM channel 2 enable/disable update value (rw) */
+ Ifx_Strict_32Bit ENDIS_CTRL3:2; /**< \brief [7:6] (A)TOM channel 3 enable/disable update value (rw) */
+ Ifx_Strict_32Bit ENDIS_CTRL4:2; /**< \brief [9:8] (A)TOM channel 4 enable/disable update value (rw) */
+ Ifx_Strict_32Bit ENDIS_CTRL5:2; /**< \brief [11:10] (A)TOM channel 5 enable/disable update value (rw) */
+ Ifx_Strict_32Bit ENDIS_CTRL6:2; /**< \brief [13:12] (A)TOM channel 6 enable/disable update value (rw) */
+ Ifx_Strict_32Bit ENDIS_CTRL7:2; /**< \brief [15:14] (A)TOM channel 7 enable/disable update value (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits;
+
+/** \brief ATOM AGC Enable/Disable Status Register */
+typedef struct _Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits
+{
+ Ifx_Strict_32Bit ENDIS_STAT0:2; /**< \brief [1:0] (A)TOM channel 0 enable/disable (rw) */
+ Ifx_Strict_32Bit ENDIS_STAT1:2; /**< \brief [3:2] (A)TOM channel 1 enable/disable (rw) */
+ Ifx_Strict_32Bit ENDIS_STAT2:2; /**< \brief [5:4] (A)TOM channel 2 enable/disable (rw) */
+ Ifx_Strict_32Bit ENDIS_STAT3:2; /**< \brief [7:6] (A)TOM channel 3 enable/disable (rw) */
+ Ifx_Strict_32Bit ENDIS_STAT4:2; /**< \brief [9:8] (A)TOM channel 4 enable/disable (rw) */
+ Ifx_Strict_32Bit ENDIS_STAT5:2; /**< \brief [11:10] (A)TOM channel 5 enable/disable (rw) */
+ Ifx_Strict_32Bit ENDIS_STAT6:2; /**< \brief [13:12] (A)TOM channel 6 enable/disable (rw) */
+ Ifx_Strict_32Bit ENDIS_STAT7:2; /**< \brief [15:14] (A)TOM channel 7 enable/disable (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits;
+
+/** \brief ATOM AGC Force Update Control Register */
+typedef struct _Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits
+{
+ Ifx_Strict_32Bit FUPD_CTRL0:2; /**< \brief [1:0] Force update of (A)TOM channel 0 operation registers (rw) */
+ Ifx_Strict_32Bit FUPD_CTRL1:2; /**< \brief [3:2] Force update of (A)TOM channel 1 operation registers (rw) */
+ Ifx_Strict_32Bit FUPD_CTRL2:2; /**< \brief [5:4] Force update of (A)TOM channel 2 operation registers (rw) */
+ Ifx_Strict_32Bit FUPD_CTRL3:2; /**< \brief [7:6] Force update of (A)TOM channel 3 operation registers (rw) */
+ Ifx_Strict_32Bit FUPD_CTRL4:2; /**< \brief [9:8] Force update of (A)TOM channel 4 operation registers (rw) */
+ Ifx_Strict_32Bit FUPD_CTRL5:2; /**< \brief [11:10] Force update of (A)TOM channel 5 operation registers (rw) */
+ Ifx_Strict_32Bit FUPD_CTRL6:2; /**< \brief [13:12] Force update of (A)TOM channel 6 operation registers (rw) */
+ Ifx_Strict_32Bit FUPD_CTRL7:2; /**< \brief [15:14] Force update of (A)TOM channel 7 operation registers (rw) */
+ Ifx_Strict_32Bit RSTCN0_CH0:2; /**< \brief [17:16] Reset CN0 of channel 0 on force update event (rw) */
+ Ifx_Strict_32Bit RSTCN0_CH1:2; /**< \brief [19:18] Reset CN0 of channel 1 on force update event (rw) */
+ Ifx_Strict_32Bit RSTCN0_CH2:2; /**< \brief [21:20] Reset CN0 of channel 2 on force update event (rw) */
+ Ifx_Strict_32Bit RSTCN0_CH3:2; /**< \brief [23:22] Reset CN0 of channel 3 on force update event (rw) */
+ Ifx_Strict_32Bit RSTCN0_CH4:2; /**< \brief [25:24] Reset CN0 of channel 4 on force update event (rw) */
+ Ifx_Strict_32Bit RSTCN0_CH5:2; /**< \brief [27:26] Reset CN0 of channel 5 on force update event (rw) */
+ Ifx_Strict_32Bit RSTCN0_CH6:2; /**< \brief [29:28] Reset CN0 of channel 6 on force update event (rw) */
+ Ifx_Strict_32Bit RSTCN0_CH7:2; /**< \brief [31:30] Reset CN0 of channel 7 on force update event (rw) */
+} Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits;
+
+/** \brief ATOM AGC Global control register */
+typedef struct _Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits
+{
+ Ifx_Strict_32Bit HOST_TRIG:1; /**< \brief [0:0] Trigger request signal (see AGC) to update the register ENDIS_STAT and OUTEN_STAT (w) */
+ Ifx_Strict_32Bit reserved_1:7; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit RST_CH0:1; /**< \brief [8:8] Software reset of channel 0 (w) */
+ Ifx_Strict_32Bit RST_CH1:1; /**< \brief [9:9] Software reset of channel 1 (w) */
+ Ifx_Strict_32Bit RST_CH2:1; /**< \brief [10:10] Software reset of channel 2 (w) */
+ Ifx_Strict_32Bit RST_CH3:1; /**< \brief [11:11] Software reset of channel 3 (w) */
+ Ifx_Strict_32Bit RST_CH4:1; /**< \brief [12:12] Software reset of channel 4 (w) */
+ Ifx_Strict_32Bit RST_CH5:1; /**< \brief [13:13] Software reset of channel 5 (w) */
+ Ifx_Strict_32Bit RST_CH6:1; /**< \brief [14:14] Software reset of channel 6 (w) */
+ Ifx_Strict_32Bit RST_CH7:1; /**< \brief [15:15] Software reset of channel 7 (w) */
+ Ifx_Strict_32Bit UPEN_CTRL0:2; /**< \brief [17:16] ATOM channel 0 enable update of register CM0, CM1 and CLK_SRC from SR0, SR1 and CLK_SRC_SR (rw) */
+ Ifx_Strict_32Bit UPEN_CTRL1:2; /**< \brief [19:18] ATOM channel 1 enable update of register CM0, CM1 and CLK_SRC (rw) */
+ Ifx_Strict_32Bit UPEN_CTRL2:2; /**< \brief [21:20] ATOM channel 2 enable update of register CM0, CM1 and CLK_SRC (rw) */
+ Ifx_Strict_32Bit UPEN_CTRL3:2; /**< \brief [23:22] ATOM channel 3 enable update of register CM0, CM1 and CLK_SRC (rw) */
+ Ifx_Strict_32Bit UPEN_CTRL4:2; /**< \brief [25:24] ATOM channel 4 enable update of register CM0, CM1 and CLK_SRC (rw) */
+ Ifx_Strict_32Bit UPEN_CTRL5:2; /**< \brief [27:26] ATOM channel 5 enable update of register CM0, CM1 and CLK_SRC (rw) */
+ Ifx_Strict_32Bit UPEN_CTRL6:2; /**< \brief [29:28] ATOM channel 6 enable update of register CM0, CM1 and CLK_SRC (rw) */
+ Ifx_Strict_32Bit UPEN_CTRL7:2; /**< \brief [31:30] ATOM channel 7 enable update of register CM0, CM1 and CLK_SRC (rw) */
+} Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits;
+
+/** \brief ATOM AGC Internal Trigger Control Register */
+typedef struct _Ifx_GTM_ATOM_AGC_INT_TRIG_Bits
+{
+ Ifx_Strict_32Bit INT_TRIG0:2; /**< \brief [1:0] Select input signal TRIG_0 as a trigger source (rw) */
+ Ifx_Strict_32Bit INT_TRIG1:2; /**< \brief [3:2] Select input signal TRIG_1 as a trigger source (rw) */
+ Ifx_Strict_32Bit INT_TRIG2:2; /**< \brief [5:4] Select input signal TRIG_2 as a trigger source (rw) */
+ Ifx_Strict_32Bit INT_TRIG3:2; /**< \brief [7:6] Select input signal TRIG_3 as a trigger source (rw) */
+ Ifx_Strict_32Bit INT_TRIG4:2; /**< \brief [9:8] Select input signal TRIG_4 as a trigger source (rw) */
+ Ifx_Strict_32Bit INT_TRIG5:2; /**< \brief [11:10] Select input signal TRIG_5 as a trigger source (rw) */
+ Ifx_Strict_32Bit INT_TRIG6:2; /**< \brief [13:12] Select input signal TRIG_6 as a trigger source (rw) */
+ Ifx_Strict_32Bit INT_TRIG7:2; /**< \brief [15:14] Select input signal TRIG_7 as a trigger source (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_ATOM_AGC_INT_TRIG_Bits;
+
+/** \brief ATOM AGC Output Enable Control Register */
+typedef struct _Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits
+{
+ Ifx_Strict_32Bit OUTEN_CTRL0:2; /**< \brief [1:0] Output (A)TOM_OUT(0) enable/disable update value (rw) */
+ Ifx_Strict_32Bit OUTEN_CTRL1:2; /**< \brief [3:2] Output (A)TOM_OUT(1)enable/disable update value (rw) */
+ Ifx_Strict_32Bit OUTEN_CTRL2:2; /**< \brief [5:4] Output (A)TOM_OUT(2) enable/disable update value (rw) */
+ Ifx_Strict_32Bit OUTEN_CTRL3:2; /**< \brief [7:6] Output (A)TOM_OUT(3) enable/disable update value (rw) */
+ Ifx_Strict_32Bit OUTEN_CTRL4:2; /**< \brief [9:8] Output (A)TOM_OUT(4) enable/disable update value (rw) */
+ Ifx_Strict_32Bit OUTEN_CTRL5:2; /**< \brief [11:10] Output (A)TOM_OUT(5) enable/disable update value (rw) */
+ Ifx_Strict_32Bit OUTEN_CTRL6:2; /**< \brief [13:12] Output (A)TOM_OUT(6) enable/disable update value (rw) */
+ Ifx_Strict_32Bit OUTEN_CTRL7:2; /**< \brief [15:14] Output (A)TOM_OUT(7) enable/disable update value (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits;
+
+/** \brief ATOM AGC Output Enable Status Register */
+typedef struct _Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits
+{
+ Ifx_Strict_32Bit OUTEN_STAT0:2; /**< \brief [1:0] Control/status of output (A)TOM_OUT(0) (rw) */
+ Ifx_Strict_32Bit OUTEN_STAT1:2; /**< \brief [3:2] Control/status of output (A)TOM_OUT(1) (rw) */
+ Ifx_Strict_32Bit OUTEN_STAT2:2; /**< \brief [5:4] Control/status of output (A)TOM_OUT(2) (rw) */
+ Ifx_Strict_32Bit OUTEN_STAT3:2; /**< \brief [7:6] Control/status of output (A)TOM_OUT(3) (rw) */
+ Ifx_Strict_32Bit OUTEN_STAT4:2; /**< \brief [9:8] Control/status of output (A)TOM_OUT(4) (rw) */
+ Ifx_Strict_32Bit OUTEN_STAT5:2; /**< \brief [11:10] Control/status of output (A)TOM_OUT(5) (rw) */
+ Ifx_Strict_32Bit OUTEN_STAT6:2; /**< \brief [13:12] Control/status of output (A)TOM_OUT(6) (rw) */
+ Ifx_Strict_32Bit OUTEN_STAT7:2; /**< \brief [15:14] Control/status of output (A)TOM_OUT(7) (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits;
+
+/** \brief ATOM Channel CCU0 Compare Register */
+typedef struct _Ifx_GTM_ATOM_CH_CM0_Bits
+{
+ Ifx_Strict_32Bit CM0:24; /**< \brief [23:0] ATOM CCU0 compare register (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_ATOM_CH_CM0_Bits;
+
+/** \brief ATOM Channel CCU1 Compare Register */
+typedef struct _Ifx_GTM_ATOM_CH_CM1_Bits
+{
+ Ifx_Strict_32Bit CM1:24; /**< \brief [23:0] ATOM CCU1 compare register (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_ATOM_CH_CM1_Bits;
+
+/** \brief ATOM Channel CCU0 Counter Register */
+typedef struct _Ifx_GTM_ATOM_CH_CN0_Bits
+{
+ Ifx_Strict_32Bit CN0:24; /**< \brief [23:0] ATOM CCU0 counter register (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_ATOM_CH_CN0_Bits;
+
+/** \brief ATOM Channel Control Register */
+typedef struct _Ifx_GTM_ATOM_CH_CTRL_Bits
+{
+ Ifx_Strict_32Bit MODE:2; /**< \brief [1:0] ATOM channel mode select (rw) */
+ Ifx_Strict_32Bit TB12_SEL:1; /**< \brief [2:2] Select time base value TBU_TS1 or TBU_TS2. (rw) */
+ Ifx_Strict_32Bit ARU_EN:1; /**< \brief [3:3] ARU Input stream enable (rw) */
+ Ifx_Strict_32Bit ACB:5; /**< \brief [8:4] ATOM Mode control bits (rw) */
+ Ifx_Strict_32Bit CMP_CTRL:1; /**< \brief [9:9] CCUx compare strategy select (rw) */
+ Ifx_Strict_32Bit reserved_10:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SL:1; /**< \brief [11:11] Initial signal level (rw) */
+ Ifx_Strict_32Bit CLK_SRC:3; /**< \brief [14:12] actual CMU clock source (SOMS)/ shadow register for CMU clock source (SOMP) (rw) */
+ Ifx_Strict_32Bit reserved_15:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit WR_REQ:1; /**< \brief [16:16] CPU Write request bit for late compare register update (rw) */
+ Ifx_Strict_32Bit reserved_17:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit RST_CCU0:1; /**< \brief [20:20] Reset source of CCU0 (rw) */
+ Ifx_Strict_32Bit reserved_21:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit TRIGOUT:1; /**< \brief [24:24] Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx. (rw) */
+ Ifx_Strict_32Bit SLA:1; /**< \brief [25:25] Serve last ARU communication strategy (rw) */
+ Ifx_Strict_32Bit OSM:1; /**< \brief [26:26] One-shot mode (rw) */
+ Ifx_Strict_32Bit ABM:1; /**< \brief [27:27] ARU blocking mode (rw) */
+ Ifx_Strict_32Bit reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_GTM_ATOM_CH_CTRL_Bits;
+
+/** \brief ATOM Channel Interrupt Enable Register */
+typedef struct _Ifx_GTM_ATOM_CH_IRQ_EN_Bits
+{
+ Ifx_Strict_32Bit CCU0TC_IRQ_EN:1; /**< \brief [0:0] ATOM_CCU0TC_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit CCU1TC_IRQ_EN:1; /**< \brief [1:1] ATOM_CCU1TC_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_GTM_ATOM_CH_IRQ_EN_Bits;
+
+/** \brief ATOM Channel Software Interrupt Generation Register */
+typedef struct _Ifx_GTM_ATOM_CH_IRQ_FORCINT_Bits
+{
+ Ifx_Strict_32Bit TRG_CCU0TC:1; /**< \brief [0:0] Trigger ATOM_CCU0TC_IRQ interrupt by software (w) */
+ Ifx_Strict_32Bit TRG_CCU1TC:1; /**< \brief [1:1] Trigger ATOM_CCU1TC_IRQ interrupt by software (w) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_GTM_ATOM_CH_IRQ_FORCINT_Bits;
+
+/** \brief ATOM IRQ Mode Configuration Register */
+typedef struct _Ifx_GTM_ATOM_CH_IRQ_MODE_Bits
+{
+ Ifx_Strict_32Bit IRQ_MODE:2; /**< \brief [1:0] IRQ mode selection (rw) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_GTM_ATOM_CH_IRQ_MODE_Bits;
+
+/** \brief ATOM Channel Interrupt Notification Register */
+typedef struct _Ifx_GTM_ATOM_CH_IRQ_NOTIFY_Bits
+{
+ Ifx_Strict_32Bit CCU0TC:1; /**< \brief [0:0] CCU0 Trigger condition interrupt for channel x (rwh) */
+ Ifx_Strict_32Bit CCU1TC:1; /**< \brief [1:1] CCU1 Trigger condition interrupt for channel x (rwh) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_GTM_ATOM_CH_IRQ_NOTIFY_Bits;
+
+/** \brief ATOM Channel ARU Read Address Register */
+typedef struct _Ifx_GTM_ATOM_CH_RDADDR_Bits
+{
+ Ifx_Strict_32Bit RDADDR0:9; /**< \brief [8:0] ARU Read address 0 (rw) */
+ Ifx_Strict_32Bit reserved_9:7; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit RDADDR1:9; /**< \brief [24:16] ARU Read address 1 (rw) */
+ Ifx_Strict_32Bit reserved_25:7; /**< \brief \internal Reserved */
+} Ifx_GTM_ATOM_CH_RDADDR_Bits;
+
+/** \brief ATOM Channel Control in SOMC mode Register */
+typedef struct _Ifx_GTM_ATOM_CH_SOMC_Bits
+{
+ Ifx_Strict_32Bit MODE:2; /**< \brief [1:0] ATOM channel mode select (rw) */
+ Ifx_Strict_32Bit TB12_SEL:1; /**< \brief [2:2] Select time base value TBU_TS1 or TBU_TS2. (rw) */
+ Ifx_Strict_32Bit ARU_EN:1; /**< \brief [3:3] ARU Input stream enable (rw) */
+ Ifx_Strict_32Bit ACB10:2; /**< \brief [5:4] Signal level control bits (rw) */
+ Ifx_Strict_32Bit ACB42:3; /**< \brief [8:6] ATOM control bits ACB(4), ACB(3), ACB(2) (rw) */
+ Ifx_Strict_32Bit CMP_CTRL:1; /**< \brief [9:9] CCUx compare strategy select (rw) */
+ Ifx_Strict_32Bit reserved_10:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SL:1; /**< \brief [11:11] Initial signal level after channel enable (rw) */
+ Ifx_Strict_32Bit reserved_12:4; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit WR_REQ:1; /**< \brief [16:16] CPU write request bit (rw) */
+ Ifx_Strict_32Bit reserved_17:7; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit TRIGOUT:1; /**< \brief [24:24] Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx (rw) */
+ Ifx_Strict_32Bit SLA:1; /**< \brief [25:25] Serve last ARU communication strategy (rw) */
+ Ifx_Strict_32Bit reserved_26:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit ABM:1; /**< \brief [27:27] ARU blocking mode (rw) */
+ Ifx_Strict_32Bit reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_GTM_ATOM_CH_SOMC_Bits;
+
+/** \brief ATOM Channel Control in SOMI mode Register */
+typedef struct _Ifx_GTM_ATOM_CH_SOMI_Bits
+{
+ Ifx_Strict_32Bit MODE:2; /**< \brief [1:0] ATOM channel mode select (rw) */
+ Ifx_Strict_32Bit reserved_2:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit ARU_EN:1; /**< \brief [3:3] ARU Input stream enable (rw) */
+ Ifx_Strict_32Bit ACB0:1; /**< \brief [4:4] ACB bit 0 (rw) */
+ Ifx_Strict_32Bit reserved_5:6; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SL:1; /**< \brief [11:11] Initial signal level after channel is enabled (rw) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_GTM_ATOM_CH_SOMI_Bits;
+
+/** \brief ATOM Channel Control in SOMP mode Register */
+typedef struct _Ifx_GTM_ATOM_CH_SOMP_Bits
+{
+ Ifx_Strict_32Bit MODE:2; /**< \brief [1:0] ATOM channel mode select (rw) */
+ Ifx_Strict_32Bit reserved_2:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit ARU_EN:1; /**< \brief [3:3] ARU Input stream enable (rw) */
+ Ifx_Strict_32Bit ADL:2; /**< \brief [5:4] ARU data select for SOMP (r) */
+ Ifx_Strict_32Bit reserved_6:5; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SL:1; /**< \brief [11:11] Signal level for pulse of PWM (rw) */
+ Ifx_Strict_32Bit CLK_SRC_SR:3; /**< \brief [14:12] Shadow register for CMU clock source register CLK_SRC (rw) */
+ Ifx_Strict_32Bit reserved_15:5; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit RST_CCU0:1; /**< \brief [20:20] Reset source of CCU0 (rw) */
+ Ifx_Strict_32Bit reserved_21:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit TRIGOUT:1; /**< \brief [24:24] Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx. (rw) */
+ Ifx_Strict_32Bit reserved_25:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit OSM:1; /**< \brief [26:26] One-shot mode (rw) */
+ Ifx_Strict_32Bit reserved_27:5; /**< \brief \internal Reserved */
+} Ifx_GTM_ATOM_CH_SOMP_Bits;
+
+/** \brief ATOM Channel Control in SOMS mode Register */
+typedef struct _Ifx_GTM_ATOM_CH_SOMS_Bits
+{
+ Ifx_Strict_32Bit MODE:2; /**< \brief [1:0] ATOM channel mode select (rw) */
+ Ifx_Strict_32Bit reserved_2:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit ARU_EN:1; /**< \brief [3:3] ARU Input stream enable (rw) */
+ Ifx_Strict_32Bit ACB0:1; /**< \brief [4:4] Shift direction for CM1 register (rw) */
+ Ifx_Strict_32Bit reserved_5:6; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SL:1; /**< \brief [11:11] Defines signal level when channel and output is disable (rw) */
+ Ifx_Strict_32Bit CLK_SRC:3; /**< \brief [14:12] Shift frequency select for channel (rw) */
+ Ifx_Strict_32Bit reserved_15:11; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit OSM:1; /**< \brief [26:26] One-shot mode (rw) */
+ Ifx_Strict_32Bit reserved_27:5; /**< \brief \internal Reserved */
+} Ifx_GTM_ATOM_CH_SOMS_Bits;
+
+/** \brief ATOM Channel CCU0 Compare Shadow Register */
+typedef struct _Ifx_GTM_ATOM_CH_SR0_Bits
+{
+ Ifx_Strict_32Bit SR0:24; /**< \brief [23:0] ATOM channel x shadow register SR0 (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_ATOM_CH_SR0_Bits;
+
+/** \brief ATOM Channel CCU1 Compare Shadow Register */
+typedef struct _Ifx_GTM_ATOM_CH_SR1_Bits
+{
+ Ifx_Strict_32Bit SR1:24; /**< \brief [23:0] ATOM channel x shadow register SR0 (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_ATOM_CH_SR1_Bits;
+
+/** \brief ATOM Channel Status Register */
+typedef struct _Ifx_GTM_ATOM_CH_STAT_Bits
+{
+ Ifx_Strict_32Bit OL:1; /**< \brief [0:0] Actual output signal level of ATOM_CHx_OUT (r) */
+ Ifx_Strict_32Bit reserved_1:15; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit ACBI:5; /**< \brief [20:16] ATOM Mode control bits received through ARU (r) */
+ Ifx_Strict_32Bit DV:1; /**< \brief [21:21] Valid ARU Data stored in compare registers (r) */
+ Ifx_Strict_32Bit WRF:1; /**< \brief [22:22] Write request of CPU failed for late update (rwh) */
+ Ifx_Strict_32Bit reserved_23:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit ACBO:5; /**< \brief [28:24] ATOM Internal status bits (r) */
+ Ifx_Strict_32Bit reserved_29:3; /**< \brief \internal Reserved */
+} Ifx_GTM_ATOM_CH_STAT_Bits;
+
+/** \brief BRC Error Interrupt Enable Register */
+typedef struct _Ifx_GTM_BRC_EIRQ_EN_Bits
+{
+ Ifx_Strict_32Bit DEST_ERR_EN:1; /**< \brief [0:0] BRC_DEST_ERR_EIRQ error interrupt enable (rw) */
+ Ifx_Strict_32Bit DID_EN0:1; /**< \brief [1:1] BRC_DIDx_EIRQ error interrupt enable (rw) */
+ Ifx_Strict_32Bit DID_EN1:1; /**< \brief [2:2] BRC_DIDx_EIRQ error interrupt enable (rw) */
+ Ifx_Strict_32Bit DID_EN2:1; /**< \brief [3:3] BRC_DIDx_EIRQ error interrupt enable (rw) */
+ Ifx_Strict_32Bit DID_EN3:1; /**< \brief [4:4] BRC_DIDx_EIRQ error interrupt enable (rw) */
+ Ifx_Strict_32Bit DID_EN4:1; /**< \brief [5:5] BRC_DIDx_EIRQ error interrupt enable (rw) */
+ Ifx_Strict_32Bit DID_EN5:1; /**< \brief [6:6] BRC_DIDx_EIRQ error interrupt enable (rw) */
+ Ifx_Strict_32Bit DID_EN6:1; /**< \brief [7:7] BRC_DIDx_EIRQ error interrupt enable (rw) */
+ Ifx_Strict_32Bit DID_EN7:1; /**< \brief [8:8] BRC_DIDx_EIRQ error interrupt enable (rw) */
+ Ifx_Strict_32Bit DID_EN8:1; /**< \brief [9:9] BRC_DIDx_EIRQ error interrupt enable (rw) */
+ Ifx_Strict_32Bit DID_EN9:1; /**< \brief [10:10] BRC_DIDx_EIRQ error interrupt enable (rw) */
+ Ifx_Strict_32Bit DID_EN10:1; /**< \brief [11:11] BRC_DIDx_EIRQ error interrupt enable (rw) */
+ Ifx_Strict_32Bit DID_EN11:1; /**< \brief [12:12] BRC_DIDx_EIRQ error interrupt enable (rw) */
+ Ifx_Strict_32Bit reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_GTM_BRC_EIRQ_EN_Bits;
+
+/** \brief BRC Interrupt Enable Register */
+typedef struct _Ifx_GTM_BRC_IRQ_EN_Bits
+{
+ Ifx_Strict_32Bit DEST_ERR_EN:1; /**< \brief [0:0] BRC_DEST_ERR_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit DID_EN0:1; /**< \brief [1:1] BRC_DIDx_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit DID_EN1:1; /**< \brief [2:2] BRC_DIDx_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit DID_EN2:1; /**< \brief [3:3] BRC_DIDx_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit DID_EN3:1; /**< \brief [4:4] BRC_DIDx_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit DID_EN4:1; /**< \brief [5:5] BRC_DIDx_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit DID_EN5:1; /**< \brief [6:6] BRC_DIDx_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit DID_EN6:1; /**< \brief [7:7] BRC_DIDx_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit DID_EN7:1; /**< \brief [8:8] BRC_DIDx_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit DID_EN8:1; /**< \brief [9:9] BRC_DIDx_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit DID_EN9:1; /**< \brief [10:10] BRC_DIDx_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit DID_EN10:1; /**< \brief [11:11] BRC_DIDx_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit DID_EN11:1; /**< \brief [12:12] BRC_DIDx_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_GTM_BRC_IRQ_EN_Bits;
+
+/** \brief BRC_DEST_ERR Forcing Interrupt Register */
+typedef struct _Ifx_GTM_BRC_IRQ_FORCINT_Bits
+{
+ Ifx_Strict_32Bit TRG_DEST_ERR:1; /**< \brief [0:0] Trigger destination error interrupt (w) */
+ Ifx_Strict_32Bit TRG_DID0:1; /**< \brief [1:1] Trigger data inconsistency error interrupt (w) */
+ Ifx_Strict_32Bit TRG_DID1:1; /**< \brief [2:2] Trigger data inconsistency error interrupt (w) */
+ Ifx_Strict_32Bit TRG_DID2:1; /**< \brief [3:3] Trigger data inconsistency error interrupt (w) */
+ Ifx_Strict_32Bit TRG_DID3:1; /**< \brief [4:4] Trigger data inconsistency error interrupt (w) */
+ Ifx_Strict_32Bit TRG_DID4:1; /**< \brief [5:5] Trigger data inconsistency error interrupt (w) */
+ Ifx_Strict_32Bit TRG_DID5:1; /**< \brief [6:6] Trigger data inconsistency error interrupt (w) */
+ Ifx_Strict_32Bit TRG_DID6:1; /**< \brief [7:7] Trigger data inconsistency error interrupt (w) */
+ Ifx_Strict_32Bit TRG_DID7:1; /**< \brief [8:8] Trigger data inconsistency error interrupt (w) */
+ Ifx_Strict_32Bit TRG_DID8:1; /**< \brief [9:9] Trigger data inconsistency error interrupt (w) */
+ Ifx_Strict_32Bit TRG_DID9:1; /**< \brief [10:10] Trigger data inconsistency error interrupt (w) */
+ Ifx_Strict_32Bit TRG_DID10:1; /**< \brief [11:11] Trigger data inconsistency error interrupt (w) */
+ Ifx_Strict_32Bit TRG_DID11:1; /**< \brief [12:12] Trigger data inconsistency error interrupt (w) */
+ Ifx_Strict_32Bit reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_GTM_BRC_IRQ_FORCINT_Bits;
+
+/** \brief BRC IRQ Mode Configuration Register */
+typedef struct _Ifx_GTM_BRC_IRQ_MODE_Bits
+{
+ Ifx_Strict_32Bit IRQ_MODE:2; /**< \brief [1:0] IRQ mode selection (rw) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_GTM_BRC_IRQ_MODE_Bits;
+
+/** \brief BRC Interrupt Notification Register */
+typedef struct _Ifx_GTM_BRC_IRQ_NOTIFY_Bits
+{
+ Ifx_Strict_32Bit DEST_ERR:1; /**< \brief [0:0] Configuration error interrupt for BRC submodule (rwh) */
+ Ifx_Strict_32Bit DID0:1; /**< \brief [1:1] Data inconsistency occurred in MTM mode (rwh) */
+ Ifx_Strict_32Bit DID1:1; /**< \brief [2:2] Data inconsistency occurred in MTM mode (rwh) */
+ Ifx_Strict_32Bit DID2:1; /**< \brief [3:3] Data inconsistency occurred in MTM mode (rwh) */
+ Ifx_Strict_32Bit DID3:1; /**< \brief [4:4] Data inconsistency occurred in MTM mode (rwh) */
+ Ifx_Strict_32Bit DID4:1; /**< \brief [5:5] Data inconsistency occurred in MTM mode (rwh) */
+ Ifx_Strict_32Bit DID5:1; /**< \brief [6:6] Data inconsistency occurred in MTM mode (rwh) */
+ Ifx_Strict_32Bit DID6:1; /**< \brief [7:7] Data inconsistency occurred in MTM mode (rwh) */
+ Ifx_Strict_32Bit DID7:1; /**< \brief [8:8] Data inconsistency occurred in MTM mode (rwh) */
+ Ifx_Strict_32Bit DID8:1; /**< \brief [9:9] Data inconsistency occurred in MTM mode (rwh) */
+ Ifx_Strict_32Bit DID9:1; /**< \brief [10:10] Data inconsistency occurred in MTM mode (rwh) */
+ Ifx_Strict_32Bit DID10:1; /**< \brief [11:11] Data inconsistency occurred in MTM mode (rwh) */
+ Ifx_Strict_32Bit DID11:1; /**< \brief [12:12] Data inconsistency occurred in MTM mode (rwh) */
+ Ifx_Strict_32Bit reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_GTM_BRC_IRQ_NOTIFY_Bits;
+
+/** \brief BRC Software Reset Register */
+typedef struct _Ifx_GTM_BRC_RST_Bits
+{
+ Ifx_Strict_32Bit RST:1; /**< \brief [0:0] Software reset (w) */
+ Ifx_Strict_32Bit reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_GTM_BRC_RST_Bits;
+
+/** \brief Read Address For Input Channel 0 */
+typedef struct _Ifx_GTM_BRC_SRC0_ADDR_Bits
+{
+ Ifx_Strict_32Bit ADDR:9; /**< \brief [8:0] Source ARU address (rw) */
+ Ifx_Strict_32Bit reserved_9:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit BRC_MODE:1; /**< \brief [12:12] BRC Operation mode select (rw) */
+ Ifx_Strict_32Bit reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_GTM_BRC_SRC0_ADDR_Bits;
+
+/** \brief Destination Channels For Input Channel 0 */
+typedef struct _Ifx_GTM_BRC_SRC0_DEST_Bits
+{
+ Ifx_Strict_32Bit EN_DEST0:1; /**< \brief [0:0] Enable BRC destination address 0 (rw) */
+ Ifx_Strict_32Bit EN_DEST1:1; /**< \brief [1:1] Enable BRC destination address 1 (rw) */
+ Ifx_Strict_32Bit EN_DEST2:1; /**< \brief [2:2] Enable BRC destination address 2 (rw) */
+ Ifx_Strict_32Bit EN_DEST3:1; /**< \brief [3:3] Enable BRC destination address 3 (rw) */
+ Ifx_Strict_32Bit EN_DEST4:1; /**< \brief [4:4] Enable BRC destination address 4 (rw) */
+ Ifx_Strict_32Bit EN_DEST5:1; /**< \brief [5:5] Enable BRC destination address 5 (rw) */
+ Ifx_Strict_32Bit EN_DEST6:1; /**< \brief [6:6] Enable BRC destination address 6 (rw) */
+ Ifx_Strict_32Bit EN_DEST7:1; /**< \brief [7:7] Enable BRC destination address 7 (rw) */
+ Ifx_Strict_32Bit EN_DEST8:1; /**< \brief [8:8] Enable BRC destination address 8 (rw) */
+ Ifx_Strict_32Bit EN_DEST9:1; /**< \brief [9:9] Enable BRC destination address 9 (rw) */
+ Ifx_Strict_32Bit EN_DEST10:1; /**< \brief [10:10] Enable BRC destination address 10 (rw) */
+ Ifx_Strict_32Bit EN_DEST11:1; /**< \brief [11:11] Enable BRC destination address 11 (rw) */
+ Ifx_Strict_32Bit EN_DEST12:1; /**< \brief [12:12] Enable BRC destination address 12 (rw) */
+ Ifx_Strict_32Bit EN_DEST13:1; /**< \brief [13:13] Enable BRC destination address 13 (rw) */
+ Ifx_Strict_32Bit EN_DEST14:1; /**< \brief [14:14] Enable BRC destination address 14 (rw) */
+ Ifx_Strict_32Bit EN_DEST15:1; /**< \brief [15:15] Enable BRC destination address 15 (rw) */
+ Ifx_Strict_32Bit EN_DEST16:1; /**< \brief [16:16] Enable BRC destination address 16 (rw) */
+ Ifx_Strict_32Bit EN_DEST17:1; /**< \brief [17:17] Enable BRC destination address 17 (rw) */
+ Ifx_Strict_32Bit EN_DEST18:1; /**< \brief [18:18] Enable BRC destination address 18 (rw) */
+ Ifx_Strict_32Bit EN_DEST19:1; /**< \brief [19:19] Enable BRC destination address 19 (rw) */
+ Ifx_Strict_32Bit EN_DEST20:1; /**< \brief [20:20] Enable BRC destination address 20 (rw) */
+ Ifx_Strict_32Bit EN_DEST21:1; /**< \brief [21:21] Enable BRC destination address 21 (rw) */
+ Ifx_Strict_32Bit EN_TRASHBIN:1; /**< \brief [22:22] Control trash bin functionality (rw) */
+ Ifx_Strict_32Bit reserved_23:9; /**< \brief \internal Reserved */
+} Ifx_GTM_BRC_SRC0_DEST_Bits;
+
+/** \brief Read Address For Input Channel 10 */
+typedef struct _Ifx_GTM_BRC_SRC10_ADDR_Bits
+{
+ Ifx_Strict_32Bit ADDR:9; /**< \brief [8:0] Source ARU address (rw) */
+ Ifx_Strict_32Bit reserved_9:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit BRC_MODE:1; /**< \brief [12:12] BRC Operation mode select (rw) */
+ Ifx_Strict_32Bit reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_GTM_BRC_SRC10_ADDR_Bits;
+
+/** \brief Destination Channels For Input Channel 10 */
+typedef struct _Ifx_GTM_BRC_SRC10_DEST_Bits
+{
+ Ifx_Strict_32Bit EN_DEST0:1; /**< \brief [0:0] Enable BRC destination address 0 (rw) */
+ Ifx_Strict_32Bit EN_DEST1:1; /**< \brief [1:1] Enable BRC destination address 1 (rw) */
+ Ifx_Strict_32Bit EN_DEST2:1; /**< \brief [2:2] Enable BRC destination address 2 (rw) */
+ Ifx_Strict_32Bit EN_DEST3:1; /**< \brief [3:3] Enable BRC destination address 3 (rw) */
+ Ifx_Strict_32Bit EN_DEST4:1; /**< \brief [4:4] Enable BRC destination address 4 (rw) */
+ Ifx_Strict_32Bit EN_DEST5:1; /**< \brief [5:5] Enable BRC destination address 5 (rw) */
+ Ifx_Strict_32Bit EN_DEST6:1; /**< \brief [6:6] Enable BRC destination address 6 (rw) */
+ Ifx_Strict_32Bit EN_DEST7:1; /**< \brief [7:7] Enable BRC destination address 7 (rw) */
+ Ifx_Strict_32Bit EN_DEST8:1; /**< \brief [8:8] Enable BRC destination address 8 (rw) */
+ Ifx_Strict_32Bit EN_DEST9:1; /**< \brief [9:9] Enable BRC destination address 9 (rw) */
+ Ifx_Strict_32Bit EN_DEST10:1; /**< \brief [10:10] Enable BRC destination address 10 (rw) */
+ Ifx_Strict_32Bit EN_DEST11:1; /**< \brief [11:11] Enable BRC destination address 11 (rw) */
+ Ifx_Strict_32Bit EN_DEST12:1; /**< \brief [12:12] Enable BRC destination address 12 (rw) */
+ Ifx_Strict_32Bit EN_DEST13:1; /**< \brief [13:13] Enable BRC destination address 13 (rw) */
+ Ifx_Strict_32Bit EN_DEST14:1; /**< \brief [14:14] Enable BRC destination address 14 (rw) */
+ Ifx_Strict_32Bit EN_DEST15:1; /**< \brief [15:15] Enable BRC destination address 15 (rw) */
+ Ifx_Strict_32Bit EN_DEST16:1; /**< \brief [16:16] Enable BRC destination address 16 (rw) */
+ Ifx_Strict_32Bit EN_DEST17:1; /**< \brief [17:17] Enable BRC destination address 17 (rw) */
+ Ifx_Strict_32Bit EN_DEST18:1; /**< \brief [18:18] Enable BRC destination address 18 (rw) */
+ Ifx_Strict_32Bit EN_DEST19:1; /**< \brief [19:19] Enable BRC destination address 19 (rw) */
+ Ifx_Strict_32Bit EN_DEST20:1; /**< \brief [20:20] Enable BRC destination address 20 (rw) */
+ Ifx_Strict_32Bit EN_DEST21:1; /**< \brief [21:21] Enable BRC destination address 21 (rw) */
+ Ifx_Strict_32Bit EN_TRASHBIN:1; /**< \brief [22:22] Control trash bin functionality (rw) */
+ Ifx_Strict_32Bit reserved_23:9; /**< \brief \internal Reserved */
+} Ifx_GTM_BRC_SRC10_DEST_Bits;
+
+/** \brief Read Address For Input Channel 11 */
+typedef struct _Ifx_GTM_BRC_SRC11_ADDR_Bits
+{
+ Ifx_Strict_32Bit ADDR:9; /**< \brief [8:0] Source ARU address (rw) */
+ Ifx_Strict_32Bit reserved_9:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit BRC_MODE:1; /**< \brief [12:12] BRC Operation mode select (rw) */
+ Ifx_Strict_32Bit reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_GTM_BRC_SRC11_ADDR_Bits;
+
+/** \brief Destination Channels For Input Channel 11 */
+typedef struct _Ifx_GTM_BRC_SRC11_DEST_Bits
+{
+ Ifx_Strict_32Bit EN_DEST0:1; /**< \brief [0:0] Enable BRC destination address 0 (rw) */
+ Ifx_Strict_32Bit EN_DEST1:1; /**< \brief [1:1] Enable BRC destination address 1 (rw) */
+ Ifx_Strict_32Bit EN_DEST2:1; /**< \brief [2:2] Enable BRC destination address 2 (rw) */
+ Ifx_Strict_32Bit EN_DEST3:1; /**< \brief [3:3] Enable BRC destination address 3 (rw) */
+ Ifx_Strict_32Bit EN_DEST4:1; /**< \brief [4:4] Enable BRC destination address 4 (rw) */
+ Ifx_Strict_32Bit EN_DEST5:1; /**< \brief [5:5] Enable BRC destination address 5 (rw) */
+ Ifx_Strict_32Bit EN_DEST6:1; /**< \brief [6:6] Enable BRC destination address 6 (rw) */
+ Ifx_Strict_32Bit EN_DEST7:1; /**< \brief [7:7] Enable BRC destination address 7 (rw) */
+ Ifx_Strict_32Bit EN_DEST8:1; /**< \brief [8:8] Enable BRC destination address 8 (rw) */
+ Ifx_Strict_32Bit EN_DEST9:1; /**< \brief [9:9] Enable BRC destination address 9 (rw) */
+ Ifx_Strict_32Bit EN_DEST10:1; /**< \brief [10:10] Enable BRC destination address 10 (rw) */
+ Ifx_Strict_32Bit EN_DEST11:1; /**< \brief [11:11] Enable BRC destination address 11 (rw) */
+ Ifx_Strict_32Bit EN_DEST12:1; /**< \brief [12:12] Enable BRC destination address 12 (rw) */
+ Ifx_Strict_32Bit EN_DEST13:1; /**< \brief [13:13] Enable BRC destination address 13 (rw) */
+ Ifx_Strict_32Bit EN_DEST14:1; /**< \brief [14:14] Enable BRC destination address 14 (rw) */
+ Ifx_Strict_32Bit EN_DEST15:1; /**< \brief [15:15] Enable BRC destination address 15 (rw) */
+ Ifx_Strict_32Bit EN_DEST16:1; /**< \brief [16:16] Enable BRC destination address 16 (rw) */
+ Ifx_Strict_32Bit EN_DEST17:1; /**< \brief [17:17] Enable BRC destination address 17 (rw) */
+ Ifx_Strict_32Bit EN_DEST18:1; /**< \brief [18:18] Enable BRC destination address 18 (rw) */
+ Ifx_Strict_32Bit EN_DEST19:1; /**< \brief [19:19] Enable BRC destination address 19 (rw) */
+ Ifx_Strict_32Bit EN_DEST20:1; /**< \brief [20:20] Enable BRC destination address 20 (rw) */
+ Ifx_Strict_32Bit EN_DEST21:1; /**< \brief [21:21] Enable BRC destination address 21 (rw) */
+ Ifx_Strict_32Bit EN_TRASHBIN:1; /**< \brief [22:22] Control trash bin functionality (rw) */
+ Ifx_Strict_32Bit reserved_23:9; /**< \brief \internal Reserved */
+} Ifx_GTM_BRC_SRC11_DEST_Bits;
+
+/** \brief Read Address For Input Channel 1 */
+typedef struct _Ifx_GTM_BRC_SRC1_ADDR_Bits
+{
+ Ifx_Strict_32Bit ADDR:9; /**< \brief [8:0] Source ARU address (rw) */
+ Ifx_Strict_32Bit reserved_9:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit BRC_MODE:1; /**< \brief [12:12] BRC Operation mode select (rw) */
+ Ifx_Strict_32Bit reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_GTM_BRC_SRC1_ADDR_Bits;
+
+/** \brief Destination Channels For Input Channel 1 */
+typedef struct _Ifx_GTM_BRC_SRC1_DEST_Bits
+{
+ Ifx_Strict_32Bit EN_DEST0:1; /**< \brief [0:0] Enable BRC destination address 0 (rw) */
+ Ifx_Strict_32Bit EN_DEST1:1; /**< \brief [1:1] Enable BRC destination address 1 (rw) */
+ Ifx_Strict_32Bit EN_DEST2:1; /**< \brief [2:2] Enable BRC destination address 2 (rw) */
+ Ifx_Strict_32Bit EN_DEST3:1; /**< \brief [3:3] Enable BRC destination address 3 (rw) */
+ Ifx_Strict_32Bit EN_DEST4:1; /**< \brief [4:4] Enable BRC destination address 4 (rw) */
+ Ifx_Strict_32Bit EN_DEST5:1; /**< \brief [5:5] Enable BRC destination address 5 (rw) */
+ Ifx_Strict_32Bit EN_DEST6:1; /**< \brief [6:6] Enable BRC destination address 6 (rw) */
+ Ifx_Strict_32Bit EN_DEST7:1; /**< \brief [7:7] Enable BRC destination address 7 (rw) */
+ Ifx_Strict_32Bit EN_DEST8:1; /**< \brief [8:8] Enable BRC destination address 8 (rw) */
+ Ifx_Strict_32Bit EN_DEST9:1; /**< \brief [9:9] Enable BRC destination address 9 (rw) */
+ Ifx_Strict_32Bit EN_DEST10:1; /**< \brief [10:10] Enable BRC destination address 10 (rw) */
+ Ifx_Strict_32Bit EN_DEST11:1; /**< \brief [11:11] Enable BRC destination address 11 (rw) */
+ Ifx_Strict_32Bit EN_DEST12:1; /**< \brief [12:12] Enable BRC destination address 12 (rw) */
+ Ifx_Strict_32Bit EN_DEST13:1; /**< \brief [13:13] Enable BRC destination address 13 (rw) */
+ Ifx_Strict_32Bit EN_DEST14:1; /**< \brief [14:14] Enable BRC destination address 14 (rw) */
+ Ifx_Strict_32Bit EN_DEST15:1; /**< \brief [15:15] Enable BRC destination address 15 (rw) */
+ Ifx_Strict_32Bit EN_DEST16:1; /**< \brief [16:16] Enable BRC destination address 16 (rw) */
+ Ifx_Strict_32Bit EN_DEST17:1; /**< \brief [17:17] Enable BRC destination address 17 (rw) */
+ Ifx_Strict_32Bit EN_DEST18:1; /**< \brief [18:18] Enable BRC destination address 18 (rw) */
+ Ifx_Strict_32Bit EN_DEST19:1; /**< \brief [19:19] Enable BRC destination address 19 (rw) */
+ Ifx_Strict_32Bit EN_DEST20:1; /**< \brief [20:20] Enable BRC destination address 20 (rw) */
+ Ifx_Strict_32Bit EN_DEST21:1; /**< \brief [21:21] Enable BRC destination address 21 (rw) */
+ Ifx_Strict_32Bit EN_TRASHBIN:1; /**< \brief [22:22] Control trash bin functionality (rw) */
+ Ifx_Strict_32Bit reserved_23:9; /**< \brief \internal Reserved */
+} Ifx_GTM_BRC_SRC1_DEST_Bits;
+
+/** \brief Read Address For Input Channel 2 */
+typedef struct _Ifx_GTM_BRC_SRC2_ADDR_Bits
+{
+ Ifx_Strict_32Bit ADDR:9; /**< \brief [8:0] Source ARU address (rw) */
+ Ifx_Strict_32Bit reserved_9:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit BRC_MODE:1; /**< \brief [12:12] BRC Operation mode select (rw) */
+ Ifx_Strict_32Bit reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_GTM_BRC_SRC2_ADDR_Bits;
+
+/** \brief Destination Channels For Input Channel 2 */
+typedef struct _Ifx_GTM_BRC_SRC2_DEST_Bits
+{
+ Ifx_Strict_32Bit EN_DEST0:1; /**< \brief [0:0] Enable BRC destination address 0 (rw) */
+ Ifx_Strict_32Bit EN_DEST1:1; /**< \brief [1:1] Enable BRC destination address 1 (rw) */
+ Ifx_Strict_32Bit EN_DEST2:1; /**< \brief [2:2] Enable BRC destination address 2 (rw) */
+ Ifx_Strict_32Bit EN_DEST3:1; /**< \brief [3:3] Enable BRC destination address 3 (rw) */
+ Ifx_Strict_32Bit EN_DEST4:1; /**< \brief [4:4] Enable BRC destination address 4 (rw) */
+ Ifx_Strict_32Bit EN_DEST5:1; /**< \brief [5:5] Enable BRC destination address 5 (rw) */
+ Ifx_Strict_32Bit EN_DEST6:1; /**< \brief [6:6] Enable BRC destination address 6 (rw) */
+ Ifx_Strict_32Bit EN_DEST7:1; /**< \brief [7:7] Enable BRC destination address 7 (rw) */
+ Ifx_Strict_32Bit EN_DEST8:1; /**< \brief [8:8] Enable BRC destination address 8 (rw) */
+ Ifx_Strict_32Bit EN_DEST9:1; /**< \brief [9:9] Enable BRC destination address 9 (rw) */
+ Ifx_Strict_32Bit EN_DEST10:1; /**< \brief [10:10] Enable BRC destination address 10 (rw) */
+ Ifx_Strict_32Bit EN_DEST11:1; /**< \brief [11:11] Enable BRC destination address 11 (rw) */
+ Ifx_Strict_32Bit EN_DEST12:1; /**< \brief [12:12] Enable BRC destination address 12 (rw) */
+ Ifx_Strict_32Bit EN_DEST13:1; /**< \brief [13:13] Enable BRC destination address 13 (rw) */
+ Ifx_Strict_32Bit EN_DEST14:1; /**< \brief [14:14] Enable BRC destination address 14 (rw) */
+ Ifx_Strict_32Bit EN_DEST15:1; /**< \brief [15:15] Enable BRC destination address 15 (rw) */
+ Ifx_Strict_32Bit EN_DEST16:1; /**< \brief [16:16] Enable BRC destination address 16 (rw) */
+ Ifx_Strict_32Bit EN_DEST17:1; /**< \brief [17:17] Enable BRC destination address 17 (rw) */
+ Ifx_Strict_32Bit EN_DEST18:1; /**< \brief [18:18] Enable BRC destination address 18 (rw) */
+ Ifx_Strict_32Bit EN_DEST19:1; /**< \brief [19:19] Enable BRC destination address 19 (rw) */
+ Ifx_Strict_32Bit EN_DEST20:1; /**< \brief [20:20] Enable BRC destination address 20 (rw) */
+ Ifx_Strict_32Bit EN_DEST21:1; /**< \brief [21:21] Enable BRC destination address 21 (rw) */
+ Ifx_Strict_32Bit EN_TRASHBIN:1; /**< \brief [22:22] Control trash bin functionality (rw) */
+ Ifx_Strict_32Bit reserved_23:9; /**< \brief \internal Reserved */
+} Ifx_GTM_BRC_SRC2_DEST_Bits;
+
+/** \brief Read Address For Input Channel 3 */
+typedef struct _Ifx_GTM_BRC_SRC3_ADDR_Bits
+{
+ Ifx_Strict_32Bit ADDR:9; /**< \brief [8:0] Source ARU address (rw) */
+ Ifx_Strict_32Bit reserved_9:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit BRC_MODE:1; /**< \brief [12:12] BRC Operation mode select (rw) */
+ Ifx_Strict_32Bit reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_GTM_BRC_SRC3_ADDR_Bits;
+
+/** \brief Destination Channels For Input Channel 3 */
+typedef struct _Ifx_GTM_BRC_SRC3_DEST_Bits
+{
+ Ifx_Strict_32Bit EN_DEST0:1; /**< \brief [0:0] Enable BRC destination address 0 (rw) */
+ Ifx_Strict_32Bit EN_DEST1:1; /**< \brief [1:1] Enable BRC destination address 1 (rw) */
+ Ifx_Strict_32Bit EN_DEST2:1; /**< \brief [2:2] Enable BRC destination address 2 (rw) */
+ Ifx_Strict_32Bit EN_DEST3:1; /**< \brief [3:3] Enable BRC destination address 3 (rw) */
+ Ifx_Strict_32Bit EN_DEST4:1; /**< \brief [4:4] Enable BRC destination address 4 (rw) */
+ Ifx_Strict_32Bit EN_DEST5:1; /**< \brief [5:5] Enable BRC destination address 5 (rw) */
+ Ifx_Strict_32Bit EN_DEST6:1; /**< \brief [6:6] Enable BRC destination address 6 (rw) */
+ Ifx_Strict_32Bit EN_DEST7:1; /**< \brief [7:7] Enable BRC destination address 7 (rw) */
+ Ifx_Strict_32Bit EN_DEST8:1; /**< \brief [8:8] Enable BRC destination address 8 (rw) */
+ Ifx_Strict_32Bit EN_DEST9:1; /**< \brief [9:9] Enable BRC destination address 9 (rw) */
+ Ifx_Strict_32Bit EN_DEST10:1; /**< \brief [10:10] Enable BRC destination address 10 (rw) */
+ Ifx_Strict_32Bit EN_DEST11:1; /**< \brief [11:11] Enable BRC destination address 11 (rw) */
+ Ifx_Strict_32Bit EN_DEST12:1; /**< \brief [12:12] Enable BRC destination address 12 (rw) */
+ Ifx_Strict_32Bit EN_DEST13:1; /**< \brief [13:13] Enable BRC destination address 13 (rw) */
+ Ifx_Strict_32Bit EN_DEST14:1; /**< \brief [14:14] Enable BRC destination address 14 (rw) */
+ Ifx_Strict_32Bit EN_DEST15:1; /**< \brief [15:15] Enable BRC destination address 15 (rw) */
+ Ifx_Strict_32Bit EN_DEST16:1; /**< \brief [16:16] Enable BRC destination address 16 (rw) */
+ Ifx_Strict_32Bit EN_DEST17:1; /**< \brief [17:17] Enable BRC destination address 17 (rw) */
+ Ifx_Strict_32Bit EN_DEST18:1; /**< \brief [18:18] Enable BRC destination address 18 (rw) */
+ Ifx_Strict_32Bit EN_DEST19:1; /**< \brief [19:19] Enable BRC destination address 19 (rw) */
+ Ifx_Strict_32Bit EN_DEST20:1; /**< \brief [20:20] Enable BRC destination address 20 (rw) */
+ Ifx_Strict_32Bit EN_DEST21:1; /**< \brief [21:21] Enable BRC destination address 21 (rw) */
+ Ifx_Strict_32Bit EN_TRASHBIN:1; /**< \brief [22:22] Control trash bin functionality (rw) */
+ Ifx_Strict_32Bit reserved_23:9; /**< \brief \internal Reserved */
+} Ifx_GTM_BRC_SRC3_DEST_Bits;
+
+/** \brief Read Address For Input Channel 4 */
+typedef struct _Ifx_GTM_BRC_SRC4_ADDR_Bits
+{
+ Ifx_Strict_32Bit ADDR:9; /**< \brief [8:0] Source ARU address (rw) */
+ Ifx_Strict_32Bit reserved_9:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit BRC_MODE:1; /**< \brief [12:12] BRC Operation mode select (rw) */
+ Ifx_Strict_32Bit reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_GTM_BRC_SRC4_ADDR_Bits;
+
+/** \brief Destination Channels For Input Channel 4 */
+typedef struct _Ifx_GTM_BRC_SRC4_DEST_Bits
+{
+ Ifx_Strict_32Bit EN_DEST0:1; /**< \brief [0:0] Enable BRC destination address 0 (rw) */
+ Ifx_Strict_32Bit EN_DEST1:1; /**< \brief [1:1] Enable BRC destination address 1 (rw) */
+ Ifx_Strict_32Bit EN_DEST2:1; /**< \brief [2:2] Enable BRC destination address 2 (rw) */
+ Ifx_Strict_32Bit EN_DEST3:1; /**< \brief [3:3] Enable BRC destination address 3 (rw) */
+ Ifx_Strict_32Bit EN_DEST4:1; /**< \brief [4:4] Enable BRC destination address 4 (rw) */
+ Ifx_Strict_32Bit EN_DEST5:1; /**< \brief [5:5] Enable BRC destination address 5 (rw) */
+ Ifx_Strict_32Bit EN_DEST6:1; /**< \brief [6:6] Enable BRC destination address 6 (rw) */
+ Ifx_Strict_32Bit EN_DEST7:1; /**< \brief [7:7] Enable BRC destination address 7 (rw) */
+ Ifx_Strict_32Bit EN_DEST8:1; /**< \brief [8:8] Enable BRC destination address 8 (rw) */
+ Ifx_Strict_32Bit EN_DEST9:1; /**< \brief [9:9] Enable BRC destination address 9 (rw) */
+ Ifx_Strict_32Bit EN_DEST10:1; /**< \brief [10:10] Enable BRC destination address 10 (rw) */
+ Ifx_Strict_32Bit EN_DEST11:1; /**< \brief [11:11] Enable BRC destination address 11 (rw) */
+ Ifx_Strict_32Bit EN_DEST12:1; /**< \brief [12:12] Enable BRC destination address 12 (rw) */
+ Ifx_Strict_32Bit EN_DEST13:1; /**< \brief [13:13] Enable BRC destination address 13 (rw) */
+ Ifx_Strict_32Bit EN_DEST14:1; /**< \brief [14:14] Enable BRC destination address 14 (rw) */
+ Ifx_Strict_32Bit EN_DEST15:1; /**< \brief [15:15] Enable BRC destination address 15 (rw) */
+ Ifx_Strict_32Bit EN_DEST16:1; /**< \brief [16:16] Enable BRC destination address 16 (rw) */
+ Ifx_Strict_32Bit EN_DEST17:1; /**< \brief [17:17] Enable BRC destination address 17 (rw) */
+ Ifx_Strict_32Bit EN_DEST18:1; /**< \brief [18:18] Enable BRC destination address 18 (rw) */
+ Ifx_Strict_32Bit EN_DEST19:1; /**< \brief [19:19] Enable BRC destination address 19 (rw) */
+ Ifx_Strict_32Bit EN_DEST20:1; /**< \brief [20:20] Enable BRC destination address 20 (rw) */
+ Ifx_Strict_32Bit EN_DEST21:1; /**< \brief [21:21] Enable BRC destination address 21 (rw) */
+ Ifx_Strict_32Bit EN_TRASHBIN:1; /**< \brief [22:22] Control trash bin functionality (rw) */
+ Ifx_Strict_32Bit reserved_23:9; /**< \brief \internal Reserved */
+} Ifx_GTM_BRC_SRC4_DEST_Bits;
+
+/** \brief Read Address For Input Channel 5 */
+typedef struct _Ifx_GTM_BRC_SRC5_ADDR_Bits
+{
+ Ifx_Strict_32Bit ADDR:9; /**< \brief [8:0] Source ARU address (rw) */
+ Ifx_Strict_32Bit reserved_9:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit BRC_MODE:1; /**< \brief [12:12] BRC Operation mode select (rw) */
+ Ifx_Strict_32Bit reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_GTM_BRC_SRC5_ADDR_Bits;
+
+/** \brief Destination Channels For Input Channel 5 */
+typedef struct _Ifx_GTM_BRC_SRC5_DEST_Bits
+{
+ Ifx_Strict_32Bit EN_DEST0:1; /**< \brief [0:0] Enable BRC destination address 0 (rw) */
+ Ifx_Strict_32Bit EN_DEST1:1; /**< \brief [1:1] Enable BRC destination address 1 (rw) */
+ Ifx_Strict_32Bit EN_DEST2:1; /**< \brief [2:2] Enable BRC destination address 2 (rw) */
+ Ifx_Strict_32Bit EN_DEST3:1; /**< \brief [3:3] Enable BRC destination address 3 (rw) */
+ Ifx_Strict_32Bit EN_DEST4:1; /**< \brief [4:4] Enable BRC destination address 4 (rw) */
+ Ifx_Strict_32Bit EN_DEST5:1; /**< \brief [5:5] Enable BRC destination address 5 (rw) */
+ Ifx_Strict_32Bit EN_DEST6:1; /**< \brief [6:6] Enable BRC destination address 6 (rw) */
+ Ifx_Strict_32Bit EN_DEST7:1; /**< \brief [7:7] Enable BRC destination address 7 (rw) */
+ Ifx_Strict_32Bit EN_DEST8:1; /**< \brief [8:8] Enable BRC destination address 8 (rw) */
+ Ifx_Strict_32Bit EN_DEST9:1; /**< \brief [9:9] Enable BRC destination address 9 (rw) */
+ Ifx_Strict_32Bit EN_DEST10:1; /**< \brief [10:10] Enable BRC destination address 10 (rw) */
+ Ifx_Strict_32Bit EN_DEST11:1; /**< \brief [11:11] Enable BRC destination address 11 (rw) */
+ Ifx_Strict_32Bit EN_DEST12:1; /**< \brief [12:12] Enable BRC destination address 12 (rw) */
+ Ifx_Strict_32Bit EN_DEST13:1; /**< \brief [13:13] Enable BRC destination address 13 (rw) */
+ Ifx_Strict_32Bit EN_DEST14:1; /**< \brief [14:14] Enable BRC destination address 14 (rw) */
+ Ifx_Strict_32Bit EN_DEST15:1; /**< \brief [15:15] Enable BRC destination address 15 (rw) */
+ Ifx_Strict_32Bit EN_DEST16:1; /**< \brief [16:16] Enable BRC destination address 16 (rw) */
+ Ifx_Strict_32Bit EN_DEST17:1; /**< \brief [17:17] Enable BRC destination address 17 (rw) */
+ Ifx_Strict_32Bit EN_DEST18:1; /**< \brief [18:18] Enable BRC destination address 18 (rw) */
+ Ifx_Strict_32Bit EN_DEST19:1; /**< \brief [19:19] Enable BRC destination address 19 (rw) */
+ Ifx_Strict_32Bit EN_DEST20:1; /**< \brief [20:20] Enable BRC destination address 20 (rw) */
+ Ifx_Strict_32Bit EN_DEST21:1; /**< \brief [21:21] Enable BRC destination address 21 (rw) */
+ Ifx_Strict_32Bit EN_TRASHBIN:1; /**< \brief [22:22] Control trash bin functionality (rw) */
+ Ifx_Strict_32Bit reserved_23:9; /**< \brief \internal Reserved */
+} Ifx_GTM_BRC_SRC5_DEST_Bits;
+
+/** \brief Read Address For Input Channel 6 */
+typedef struct _Ifx_GTM_BRC_SRC6_ADDR_Bits
+{
+ Ifx_Strict_32Bit ADDR:9; /**< \brief [8:0] Source ARU address (rw) */
+ Ifx_Strict_32Bit reserved_9:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit BRC_MODE:1; /**< \brief [12:12] BRC Operation mode select (rw) */
+ Ifx_Strict_32Bit reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_GTM_BRC_SRC6_ADDR_Bits;
+
+/** \brief Destination Channels For Input Channel 6 */
+typedef struct _Ifx_GTM_BRC_SRC6_DEST_Bits
+{
+ Ifx_Strict_32Bit EN_DEST0:1; /**< \brief [0:0] Enable BRC destination address 0 (rw) */
+ Ifx_Strict_32Bit EN_DEST1:1; /**< \brief [1:1] Enable BRC destination address 1 (rw) */
+ Ifx_Strict_32Bit EN_DEST2:1; /**< \brief [2:2] Enable BRC destination address 2 (rw) */
+ Ifx_Strict_32Bit EN_DEST3:1; /**< \brief [3:3] Enable BRC destination address 3 (rw) */
+ Ifx_Strict_32Bit EN_DEST4:1; /**< \brief [4:4] Enable BRC destination address 4 (rw) */
+ Ifx_Strict_32Bit EN_DEST5:1; /**< \brief [5:5] Enable BRC destination address 5 (rw) */
+ Ifx_Strict_32Bit EN_DEST6:1; /**< \brief [6:6] Enable BRC destination address 6 (rw) */
+ Ifx_Strict_32Bit EN_DEST7:1; /**< \brief [7:7] Enable BRC destination address 7 (rw) */
+ Ifx_Strict_32Bit EN_DEST8:1; /**< \brief [8:8] Enable BRC destination address 8 (rw) */
+ Ifx_Strict_32Bit EN_DEST9:1; /**< \brief [9:9] Enable BRC destination address 9 (rw) */
+ Ifx_Strict_32Bit EN_DEST10:1; /**< \brief [10:10] Enable BRC destination address 10 (rw) */
+ Ifx_Strict_32Bit EN_DEST11:1; /**< \brief [11:11] Enable BRC destination address 11 (rw) */
+ Ifx_Strict_32Bit EN_DEST12:1; /**< \brief [12:12] Enable BRC destination address 12 (rw) */
+ Ifx_Strict_32Bit EN_DEST13:1; /**< \brief [13:13] Enable BRC destination address 13 (rw) */
+ Ifx_Strict_32Bit EN_DEST14:1; /**< \brief [14:14] Enable BRC destination address 14 (rw) */
+ Ifx_Strict_32Bit EN_DEST15:1; /**< \brief [15:15] Enable BRC destination address 15 (rw) */
+ Ifx_Strict_32Bit EN_DEST16:1; /**< \brief [16:16] Enable BRC destination address 16 (rw) */
+ Ifx_Strict_32Bit EN_DEST17:1; /**< \brief [17:17] Enable BRC destination address 17 (rw) */
+ Ifx_Strict_32Bit EN_DEST18:1; /**< \brief [18:18] Enable BRC destination address 18 (rw) */
+ Ifx_Strict_32Bit EN_DEST19:1; /**< \brief [19:19] Enable BRC destination address 19 (rw) */
+ Ifx_Strict_32Bit EN_DEST20:1; /**< \brief [20:20] Enable BRC destination address 20 (rw) */
+ Ifx_Strict_32Bit EN_DEST21:1; /**< \brief [21:21] Enable BRC destination address 21 (rw) */
+ Ifx_Strict_32Bit EN_TRASHBIN:1; /**< \brief [22:22] Control trash bin functionality (rw) */
+ Ifx_Strict_32Bit reserved_23:9; /**< \brief \internal Reserved */
+} Ifx_GTM_BRC_SRC6_DEST_Bits;
+
+/** \brief Read Address For Input Channel 7 */
+typedef struct _Ifx_GTM_BRC_SRC7_ADDR_Bits
+{
+ Ifx_Strict_32Bit ADDR:9; /**< \brief [8:0] Source ARU address (rw) */
+ Ifx_Strict_32Bit reserved_9:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit BRC_MODE:1; /**< \brief [12:12] BRC Operation mode select (rw) */
+ Ifx_Strict_32Bit reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_GTM_BRC_SRC7_ADDR_Bits;
+
+/** \brief Destination Channels For Input Channel 7 */
+typedef struct _Ifx_GTM_BRC_SRC7_DEST_Bits
+{
+ Ifx_Strict_32Bit EN_DEST0:1; /**< \brief [0:0] Enable BRC destination address 0 (rw) */
+ Ifx_Strict_32Bit EN_DEST1:1; /**< \brief [1:1] Enable BRC destination address 1 (rw) */
+ Ifx_Strict_32Bit EN_DEST2:1; /**< \brief [2:2] Enable BRC destination address 2 (rw) */
+ Ifx_Strict_32Bit EN_DEST3:1; /**< \brief [3:3] Enable BRC destination address 3 (rw) */
+ Ifx_Strict_32Bit EN_DEST4:1; /**< \brief [4:4] Enable BRC destination address 4 (rw) */
+ Ifx_Strict_32Bit EN_DEST5:1; /**< \brief [5:5] Enable BRC destination address 5 (rw) */
+ Ifx_Strict_32Bit EN_DEST6:1; /**< \brief [6:6] Enable BRC destination address 6 (rw) */
+ Ifx_Strict_32Bit EN_DEST7:1; /**< \brief [7:7] Enable BRC destination address 7 (rw) */
+ Ifx_Strict_32Bit EN_DEST8:1; /**< \brief [8:8] Enable BRC destination address 8 (rw) */
+ Ifx_Strict_32Bit EN_DEST9:1; /**< \brief [9:9] Enable BRC destination address 9 (rw) */
+ Ifx_Strict_32Bit EN_DEST10:1; /**< \brief [10:10] Enable BRC destination address 10 (rw) */
+ Ifx_Strict_32Bit EN_DEST11:1; /**< \brief [11:11] Enable BRC destination address 11 (rw) */
+ Ifx_Strict_32Bit EN_DEST12:1; /**< \brief [12:12] Enable BRC destination address 12 (rw) */
+ Ifx_Strict_32Bit EN_DEST13:1; /**< \brief [13:13] Enable BRC destination address 13 (rw) */
+ Ifx_Strict_32Bit EN_DEST14:1; /**< \brief [14:14] Enable BRC destination address 14 (rw) */
+ Ifx_Strict_32Bit EN_DEST15:1; /**< \brief [15:15] Enable BRC destination address 15 (rw) */
+ Ifx_Strict_32Bit EN_DEST16:1; /**< \brief [16:16] Enable BRC destination address 16 (rw) */
+ Ifx_Strict_32Bit EN_DEST17:1; /**< \brief [17:17] Enable BRC destination address 17 (rw) */
+ Ifx_Strict_32Bit EN_DEST18:1; /**< \brief [18:18] Enable BRC destination address 18 (rw) */
+ Ifx_Strict_32Bit EN_DEST19:1; /**< \brief [19:19] Enable BRC destination address 19 (rw) */
+ Ifx_Strict_32Bit EN_DEST20:1; /**< \brief [20:20] Enable BRC destination address 20 (rw) */
+ Ifx_Strict_32Bit EN_DEST21:1; /**< \brief [21:21] Enable BRC destination address 21 (rw) */
+ Ifx_Strict_32Bit EN_TRASHBIN:1; /**< \brief [22:22] Control trash bin functionality (rw) */
+ Ifx_Strict_32Bit reserved_23:9; /**< \brief \internal Reserved */
+} Ifx_GTM_BRC_SRC7_DEST_Bits;
+
+/** \brief Read Address For Input Channel 8 */
+typedef struct _Ifx_GTM_BRC_SRC8_ADDR_Bits
+{
+ Ifx_Strict_32Bit ADDR:9; /**< \brief [8:0] Source ARU address (rw) */
+ Ifx_Strict_32Bit reserved_9:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit BRC_MODE:1; /**< \brief [12:12] BRC Operation mode select (rw) */
+ Ifx_Strict_32Bit reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_GTM_BRC_SRC8_ADDR_Bits;
+
+/** \brief Destination Channels For Input Channel 8 */
+typedef struct _Ifx_GTM_BRC_SRC8_DEST_Bits
+{
+ Ifx_Strict_32Bit EN_DEST0:1; /**< \brief [0:0] Enable BRC destination address 0 (rw) */
+ Ifx_Strict_32Bit EN_DEST1:1; /**< \brief [1:1] Enable BRC destination address 1 (rw) */
+ Ifx_Strict_32Bit EN_DEST2:1; /**< \brief [2:2] Enable BRC destination address 2 (rw) */
+ Ifx_Strict_32Bit EN_DEST3:1; /**< \brief [3:3] Enable BRC destination address 3 (rw) */
+ Ifx_Strict_32Bit EN_DEST4:1; /**< \brief [4:4] Enable BRC destination address 4 (rw) */
+ Ifx_Strict_32Bit EN_DEST5:1; /**< \brief [5:5] Enable BRC destination address 5 (rw) */
+ Ifx_Strict_32Bit EN_DEST6:1; /**< \brief [6:6] Enable BRC destination address 6 (rw) */
+ Ifx_Strict_32Bit EN_DEST7:1; /**< \brief [7:7] Enable BRC destination address 7 (rw) */
+ Ifx_Strict_32Bit EN_DEST8:1; /**< \brief [8:8] Enable BRC destination address 8 (rw) */
+ Ifx_Strict_32Bit EN_DEST9:1; /**< \brief [9:9] Enable BRC destination address 9 (rw) */
+ Ifx_Strict_32Bit EN_DEST10:1; /**< \brief [10:10] Enable BRC destination address 10 (rw) */
+ Ifx_Strict_32Bit EN_DEST11:1; /**< \brief [11:11] Enable BRC destination address 11 (rw) */
+ Ifx_Strict_32Bit EN_DEST12:1; /**< \brief [12:12] Enable BRC destination address 12 (rw) */
+ Ifx_Strict_32Bit EN_DEST13:1; /**< \brief [13:13] Enable BRC destination address 13 (rw) */
+ Ifx_Strict_32Bit EN_DEST14:1; /**< \brief [14:14] Enable BRC destination address 14 (rw) */
+ Ifx_Strict_32Bit EN_DEST15:1; /**< \brief [15:15] Enable BRC destination address 15 (rw) */
+ Ifx_Strict_32Bit EN_DEST16:1; /**< \brief [16:16] Enable BRC destination address 16 (rw) */
+ Ifx_Strict_32Bit EN_DEST17:1; /**< \brief [17:17] Enable BRC destination address 17 (rw) */
+ Ifx_Strict_32Bit EN_DEST18:1; /**< \brief [18:18] Enable BRC destination address 18 (rw) */
+ Ifx_Strict_32Bit EN_DEST19:1; /**< \brief [19:19] Enable BRC destination address 19 (rw) */
+ Ifx_Strict_32Bit EN_DEST20:1; /**< \brief [20:20] Enable BRC destination address 20 (rw) */
+ Ifx_Strict_32Bit EN_DEST21:1; /**< \brief [21:21] Enable BRC destination address 21 (rw) */
+ Ifx_Strict_32Bit EN_TRASHBIN:1; /**< \brief [22:22] Control trash bin functionality (rw) */
+ Ifx_Strict_32Bit reserved_23:9; /**< \brief \internal Reserved */
+} Ifx_GTM_BRC_SRC8_DEST_Bits;
+
+/** \brief Read Address For Input Channel 9 */
+typedef struct _Ifx_GTM_BRC_SRC9_ADDR_Bits
+{
+ Ifx_Strict_32Bit ADDR:9; /**< \brief [8:0] Source ARU address (rw) */
+ Ifx_Strict_32Bit reserved_9:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit BRC_MODE:1; /**< \brief [12:12] BRC Operation mode select (rw) */
+ Ifx_Strict_32Bit reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_GTM_BRC_SRC9_ADDR_Bits;
+
+/** \brief Destination Channels For Input Channel 9 */
+typedef struct _Ifx_GTM_BRC_SRC9_DEST_Bits
+{
+ Ifx_Strict_32Bit EN_DEST0:1; /**< \brief [0:0] Enable BRC destination address 0 (rw) */
+ Ifx_Strict_32Bit EN_DEST1:1; /**< \brief [1:1] Enable BRC destination address 1 (rw) */
+ Ifx_Strict_32Bit EN_DEST2:1; /**< \brief [2:2] Enable BRC destination address 2 (rw) */
+ Ifx_Strict_32Bit EN_DEST3:1; /**< \brief [3:3] Enable BRC destination address 3 (rw) */
+ Ifx_Strict_32Bit EN_DEST4:1; /**< \brief [4:4] Enable BRC destination address 4 (rw) */
+ Ifx_Strict_32Bit EN_DEST5:1; /**< \brief [5:5] Enable BRC destination address 5 (rw) */
+ Ifx_Strict_32Bit EN_DEST6:1; /**< \brief [6:6] Enable BRC destination address 6 (rw) */
+ Ifx_Strict_32Bit EN_DEST7:1; /**< \brief [7:7] Enable BRC destination address 7 (rw) */
+ Ifx_Strict_32Bit EN_DEST8:1; /**< \brief [8:8] Enable BRC destination address 8 (rw) */
+ Ifx_Strict_32Bit EN_DEST9:1; /**< \brief [9:9] Enable BRC destination address 9 (rw) */
+ Ifx_Strict_32Bit EN_DEST10:1; /**< \brief [10:10] Enable BRC destination address 10 (rw) */
+ Ifx_Strict_32Bit EN_DEST11:1; /**< \brief [11:11] Enable BRC destination address 11 (rw) */
+ Ifx_Strict_32Bit EN_DEST12:1; /**< \brief [12:12] Enable BRC destination address 12 (rw) */
+ Ifx_Strict_32Bit EN_DEST13:1; /**< \brief [13:13] Enable BRC destination address 13 (rw) */
+ Ifx_Strict_32Bit EN_DEST14:1; /**< \brief [14:14] Enable BRC destination address 14 (rw) */
+ Ifx_Strict_32Bit EN_DEST15:1; /**< \brief [15:15] Enable BRC destination address 15 (rw) */
+ Ifx_Strict_32Bit EN_DEST16:1; /**< \brief [16:16] Enable BRC destination address 16 (rw) */
+ Ifx_Strict_32Bit EN_DEST17:1; /**< \brief [17:17] Enable BRC destination address 17 (rw) */
+ Ifx_Strict_32Bit EN_DEST18:1; /**< \brief [18:18] Enable BRC destination address 18 (rw) */
+ Ifx_Strict_32Bit EN_DEST19:1; /**< \brief [19:19] Enable BRC destination address 19 (rw) */
+ Ifx_Strict_32Bit EN_DEST20:1; /**< \brief [20:20] Enable BRC destination address 20 (rw) */
+ Ifx_Strict_32Bit EN_DEST21:1; /**< \brief [21:21] Enable BRC destination address 21 (rw) */
+ Ifx_Strict_32Bit EN_TRASHBIN:1; /**< \brief [22:22] Control trash bin functionality (rw) */
+ Ifx_Strict_32Bit reserved_23:9; /**< \brief \internal Reserved */
+} Ifx_GTM_BRC_SRC9_DEST_Bits;
+
+/** \brief GTM to SPB BRIDGE MODE */
+typedef struct _Ifx_GTM_BRIDGE_MODE_Bits
+{
+ Ifx_Strict_32Bit BRG_MODE:1; /**< \brief [0:0] Defines the operation mode for the AEI bridge (rw) */
+ Ifx_Strict_32Bit MSK_WR_RSP:1; /**< \brief [1:1] Mask write response (rw) */
+ Ifx_Strict_32Bit reserved_2:6; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit MODE_UP_PGR:1; /**< \brief [8:8] Mode update in progress (r) */
+ Ifx_Strict_32Bit BUFF_OVL:1; /**< \brief [9:9] Buffer overflow register (rwh) */
+ Ifx_Strict_32Bit reserved_10:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SYNC_INPUT_REG:1; /**< \brief [12:12] Additional Pipeline Stage in Synchronous Bridge Mode (rw) */
+ Ifx_Strict_32Bit reserved_13:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit BRG_RST:1; /**< \brief [16:16] Bridge software reset (w) */
+ Ifx_Strict_32Bit reserved_17:7; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit BUFF_DPT:8; /**< \brief [31:24] Buffer depth of AEI bridge (r) */
+} Ifx_GTM_BRIDGE_MODE_Bits;
+
+/** \brief GTM to SPB BRIDGE PTR1 */
+typedef struct _Ifx_GTM_BRIDGE_PTR1_Bits
+{
+ Ifx_Strict_32Bit NEW_TRAN_PTR:5; /**< \brief [4:0] New transaction pointer (r) */
+ Ifx_Strict_32Bit FIRST_RSP_PTR:5; /**< \brief [9:5] First response pointer (r) */
+ Ifx_Strict_32Bit TRAN_IN_PGR:5; /**< \brief [14:10] Transaction in progress pointer (acquire) (r) */
+ Ifx_Strict_32Bit ABT_TRAN_PGR:5; /**< \brief [19:15] Aborted transaction in progress pointer (r) */
+ Ifx_Strict_32Bit FBC:6; /**< \brief [25:20] Free buffer count (r) */
+ Ifx_Strict_32Bit RSP_TRAN_RDY:6; /**< \brief [31:26] Response transactions ready (r) */
+} Ifx_GTM_BRIDGE_PTR1_Bits;
+
+/** \brief GTM to SPB BRIDGE PTR2 */
+typedef struct _Ifx_GTM_BRIDGE_PTR2_Bits
+{
+ Ifx_Strict_32Bit TRAN_IN_PGR2:5; /**< \brief [4:0] Transaction in progress pointer (aquire2) (r) */
+ Ifx_Strict_32Bit reserved_5:27; /**< \brief \internal Reserved */
+} Ifx_GTM_BRIDGE_PTR2_Bits;
+
+/** \brief Clock Control Register */
+typedef struct _Ifx_GTM_CLC_Bits
+{
+ Ifx_Strict_32Bit DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
+ Ifx_Strict_32Bit DISS:1; /**< \brief [1:1] Module Disable Status Bit (r) */
+ Ifx_Strict_32Bit reserved_2:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control (rw) */
+ Ifx_Strict_32Bit reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_GTM_CLC_Bits;
+
+/** \brief CMP Error Interrupt Enable Register */
+typedef struct _Ifx_GTM_CMP_EIRQ_EN_Bits
+{
+ Ifx_Strict_32Bit ABWC0_EN_EIRQ:1; /**< \brief [0:0] enable ABWC0 interrupt source for CMP_EIRQ line (rw) */
+ Ifx_Strict_32Bit ABWC1_EN_EIRQ:1; /**< \brief [1:1] enable ABWC1 interrupt source for CMP_EIRQ line (rw) */
+ Ifx_Strict_32Bit ABWC2_EN_EIRQ:1; /**< \brief [2:2] enable ABWC2 interrupt source for CMP_EIRQ line (rw) */
+ Ifx_Strict_32Bit ABWC3_EN_EIRQ:1; /**< \brief [3:3] enable ABWC3 interrupt source for CMP_EIRQ line (rw) */
+ Ifx_Strict_32Bit ABWC4_EN_EIRQ:1; /**< \brief [4:4] enable ABWC4 interrupt source for CMP_EIRQ line (rw) */
+ Ifx_Strict_32Bit ABWC5_EN_EIRQ:1; /**< \brief [5:5] enable ABWC5 interrupt source for CMP_EIRQ line (rw) */
+ Ifx_Strict_32Bit ABWC6_EN_EIRQ:1; /**< \brief [6:6] enable ABWC6 interrupt source for CMP_EIRQ line. (rw) */
+ Ifx_Strict_32Bit ABWC7_EN_EIRQ:1; /**< \brief [7:7] enable ABWC7 interrupt source for CMP_EIRQ line (rw) */
+ Ifx_Strict_32Bit ABWC8_EN_EIRQ:1; /**< \brief [8:8] enable ABWC8 interrupt source for CMP_EIRQ line (rw) */
+ Ifx_Strict_32Bit ABWC9_EN_EIRQ:1; /**< \brief [9:9] enable ABWC9 interrupt source for CMP_EIRQ line (rw) */
+ Ifx_Strict_32Bit ABWC10_EN_EIRQ:1; /**< \brief [10:10] enable ABWC10 interrupt source for CMP_EIRQ line (rw) */
+ Ifx_Strict_32Bit ABWC11_EN_EIRQ:1; /**< \brief [11:11] enable ABWC11 interrupt source for CMP_EIRQ line (rw) */
+ Ifx_Strict_32Bit TBWC0_EN_EIRQ:1; /**< \brief [12:12] enable TBWC0 interrupt source for CMP_EIRQ line (rw) */
+ Ifx_Strict_32Bit TBWC1_EN_EIRQ:1; /**< \brief [13:13] enable TBWC1 interrupt source for CMP_EIRQ line (rw) */
+ Ifx_Strict_32Bit TBWC2_EN_EIRQ:1; /**< \brief [14:14] enable TBWC2 interrupt source for CMP_EIRQ line (rw) */
+ Ifx_Strict_32Bit TBWC3_EN_EIRQ:1; /**< \brief [15:15] enable TBWC3 interrupt source for CMP_EIRQ line (rw) */
+ Ifx_Strict_32Bit TBWC4_EN_EIRQ:1; /**< \brief [16:16] enable TBWC4 interrupt source for CMP_EIRQ line (rw) */
+ Ifx_Strict_32Bit TBWC5_EN_EIRQ:1; /**< \brief [17:17] enable TBWC5 interrupt source for CMP_EIRQ line (rw) */
+ Ifx_Strict_32Bit TBWC6_EN_EIRQ:1; /**< \brief [18:18] enable TBWC6 interrupt source for CMP_EIRQ line (rw) */
+ Ifx_Strict_32Bit TBWC7_EN_EIRQ:1; /**< \brief [19:19] enable TBWC7 interrupt source for CMP_EIRQ line (rw) */
+ Ifx_Strict_32Bit TBWC8_EN_EIRQ:1; /**< \brief [20:20] enable TBWC8 interrupt source for CMP_EIRQ line (rw) */
+ Ifx_Strict_32Bit TBWC9_EN_EIRQ:1; /**< \brief [21:21] enable TBWC9 interrupt source for CMP_EIRQ line (rw) */
+ Ifx_Strict_32Bit TBWC10_EN_EIRQ:1; /**< \brief [22:22] enable TBWC10 interrupt source for CMP_EIRQ line (rw) */
+ Ifx_Strict_32Bit TBWC11_EN_EIRQ:1; /**< \brief [23:23] enable TBWC11 interrupt source for CMP_EIRQ line (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_CMP_EIRQ_EN_Bits;
+
+/** \brief CMP Comparator Enable Register */
+typedef struct _Ifx_GTM_CMP_EN_Bits
+{
+ Ifx_Strict_32Bit ABWC0_EN:1; /**< \brief [0:0] Enable comparator 0 in ABWC (rw) */
+ Ifx_Strict_32Bit ABWC1_EN:1; /**< \brief [1:1] Enable comparator 1 in ABWC (rw) */
+ Ifx_Strict_32Bit ABWC2_EN:1; /**< \brief [2:2] Enable comparator 2 in ABWC (rw) */
+ Ifx_Strict_32Bit ABWC3_EN:1; /**< \brief [3:3] Enable comparator 3 in ABWC (rw) */
+ Ifx_Strict_32Bit ABWC4_EN:1; /**< \brief [4:4] Enable comparator 4 in ABWC (rw) */
+ Ifx_Strict_32Bit ABWC5_EN:1; /**< \brief [5:5] Enable comparator 5 in ABWC (rw) */
+ Ifx_Strict_32Bit ABWC6_EN:1; /**< \brief [6:6] Enable comparator 6 in ABWC (rw) */
+ Ifx_Strict_32Bit ABWC7_EN:1; /**< \brief [7:7] Enable comparator 7 in ABWC (rw) */
+ Ifx_Strict_32Bit ABWC8_EN:1; /**< \brief [8:8] Enable comparator 8 in ABWC (rw) */
+ Ifx_Strict_32Bit ABWC9_EN:1; /**< \brief [9:9] Enable comparator 9 in ABW (rw) */
+ Ifx_Strict_32Bit ABWC10_EN:1; /**< \brief [10:10] Enable comparator 10 in ABWC (rw) */
+ Ifx_Strict_32Bit ABWC11_EN:1; /**< \brief [11:11] Enable comparator 11 in ABWC (rw) */
+ Ifx_Strict_32Bit TBWC0_EN:1; /**< \brief [12:12] Enable comparator 0 in TBWC (rw) */
+ Ifx_Strict_32Bit TBWC1_EN:1; /**< \brief [13:13] Enable comparator 1 in TBWC (rw) */
+ Ifx_Strict_32Bit TBWC2_EN:1; /**< \brief [14:14] Enable comparator 2 in TBWC (rw) */
+ Ifx_Strict_32Bit TBWC3_EN:1; /**< \brief [15:15] Enable comparator 3 in TBWC (rw) */
+ Ifx_Strict_32Bit TBWC4_EN:1; /**< \brief [16:16] Enable comparator 4 in TBWC (rw) */
+ Ifx_Strict_32Bit TBWC5_EN:1; /**< \brief [17:17] Enable comparator 5 in TBWC (rw) */
+ Ifx_Strict_32Bit TBWC6_EN:1; /**< \brief [18:18] Enable comparator 6 in TBWC (rw) */
+ Ifx_Strict_32Bit TBWC7_EN:1; /**< \brief [19:19] Enable comparator 7 in TBWC (rw) */
+ Ifx_Strict_32Bit TBWC8_EN:1; /**< \brief [20:20] Enable comparator 8 in TBWC (rw) */
+ Ifx_Strict_32Bit TBWC9_EN:1; /**< \brief [21:21] Enable comparator 9 in TBWC (rw) */
+ Ifx_Strict_32Bit TBWC10_EN:1; /**< \brief [22:22] Enable comparator 10 in TBWC (rw) */
+ Ifx_Strict_32Bit TBWC11_EN:1; /**< \brief [23:23] Enable comparator 11 in TBWC (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_CMP_EN_Bits;
+
+/** \brief CMP Interrupt Enable Register */
+typedef struct _Ifx_GTM_CMP_IRQ_EN_Bits
+{
+ Ifx_Strict_32Bit ABWC0_EN_IRQ:1; /**< \brief [0:0] Enable ABWC0 interrupt source for CMP_IRQ line (rw) */
+ Ifx_Strict_32Bit ABWC1_EN_IRQ:1; /**< \brief [1:1] Enable ABWC1 interrupt source for CMP_IRQ line (rw) */
+ Ifx_Strict_32Bit ABWC2_EN_IRQ:1; /**< \brief [2:2] Enable ABWC2 interrupt source for CMP_IRQ line (rw) */
+ Ifx_Strict_32Bit ABWC3_EN_IRQ:1; /**< \brief [3:3] Enable ABWC3 interrupt source for CMP_IRQ line (rw) */
+ Ifx_Strict_32Bit ABWC4_EN_IRQ:1; /**< \brief [4:4] Enable ABWC4 interrupt source for CMP_IRQ line (rw) */
+ Ifx_Strict_32Bit ABWC5_EN_IRQ:1; /**< \brief [5:5] Enable ABWC5 interrupt source for CMP_IRQ line (rw) */
+ Ifx_Strict_32Bit ABWC6_EN_IRQ:1; /**< \brief [6:6] Enable ABWC6 interrupt source for CMP_IRQ line (rw) */
+ Ifx_Strict_32Bit ABWC7_EN_IRQ:1; /**< \brief [7:7] Enable ABWC7 interrupt source for CMP_IRQ line (rw) */
+ Ifx_Strict_32Bit ABWC8_EN_IRQ:1; /**< \brief [8:8] Enable ABWC8 interrupt source for CMP_IRQ line (rw) */
+ Ifx_Strict_32Bit ABWC9_EN_IRQ:1; /**< \brief [9:9] Enable ABWC9 interrupt source for CMP_IRQ line (rw) */
+ Ifx_Strict_32Bit ABWC10_EN_IRQ:1; /**< \brief [10:10] Enable ABWC10 interrupt source for CMP_IRQ line (rw) */
+ Ifx_Strict_32Bit ABWC11_EN_IRQ:1; /**< \brief [11:11] Enable ABWC11 interrupt source for CMP_IRQ line (rw) */
+ Ifx_Strict_32Bit TBWC0_EN_IRQ:1; /**< \brief [12:12] Enable TBWC0 interrupt source for CMP_IRQ line (rw) */
+ Ifx_Strict_32Bit TBWC1_EN_IRQ:1; /**< \brief [13:13] Enable TBWC1 interrupt source for CMP_IRQ line (rw) */
+ Ifx_Strict_32Bit TBWC2_EN_IRQ:1; /**< \brief [14:14] Enable TBWC2 interrupt source for CMP_IRQ line (rw) */
+ Ifx_Strict_32Bit TBWC3_EN_IRQ:1; /**< \brief [15:15] Enable TBWC3 interrupt source for CMP_IRQ line (rw) */
+ Ifx_Strict_32Bit TBWC4_EN_IRQ:1; /**< \brief [16:16] Enable TBWC4 interrupt source for CMP_IRQ line (rw) */
+ Ifx_Strict_32Bit TBWC5_EN_IRQ:1; /**< \brief [17:17] Enable TBWC5 interrupt source for CMP_IRQ line (rw) */
+ Ifx_Strict_32Bit TBWC6_EN_IRQ:1; /**< \brief [18:18] Enable TBWC6 interrupt source for CMP_IRQ line (rw) */
+ Ifx_Strict_32Bit TBWC7_EN_IRQ:1; /**< \brief [19:19] Enable TBWC7 interrupt source for CMP_IRQ line (rw) */
+ Ifx_Strict_32Bit TBWC8_EN_IRQ:1; /**< \brief [20:20] Enable TBWC8 interrupt source for CMP_IRQ line (rw) */
+ Ifx_Strict_32Bit TBWC9_EN_IRQ:1; /**< \brief [21:21] Enable TBWC9 interrupt source for CMP_IRQ line (rw) */
+ Ifx_Strict_32Bit TBWC10_EN_IRQ:1; /**< \brief [22:22] Enable TBWC10 interrupt source for CMP_IRQ line (rw) */
+ Ifx_Strict_32Bit TBWC11_EN_IRQ:1; /**< \brief [23:23] Enable TBWC11 interrupt source for CMP_IRQ line (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_CMP_IRQ_EN_Bits;
+
+/** \brief CMP Interrupt Force Register */
+typedef struct _Ifx_GTM_CMP_IRQ_FORCINT_Bits
+{
+ Ifx_Strict_32Bit TRG_ABWC0:1; /**< \brief [0:0] Trigger ABWC0 bit in CMP_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit TRG_ABWC1:1; /**< \brief [1:1] Trigger ABWC1 bit in CMP_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit TRG_ABWC2:1; /**< \brief [2:2] Trigger ABWC2 bit in CMP_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit TRG_ABWC3:1; /**< \brief [3:3] Trigger ABWC3 bit in CMP_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit TRG_ABWC4:1; /**< \brief [4:4] Trigger ABWC4 bit in CMP_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit TRG_ABWC5:1; /**< \brief [5:5] Trigger ABWC5 bit in CMP_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit TRG_ABWC6:1; /**< \brief [6:6] Trigger ABWC6 bit in CMP_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit TRG_ABWC7:1; /**< \brief [7:7] Trigger ABWC7 bit in CMP_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit TRG_ABWC8:1; /**< \brief [8:8] Trigger ABWC8 bit in CMP_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit TRG_ABWC9:1; /**< \brief [9:9] Trigger ABWC9 bit in CMP_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit TRG_ABWC10:1; /**< \brief [10:10] Trigger ABWC10 bit in CMP_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit TRG_ABWC11:1; /**< \brief [11:11] Trigger ABWC11 bit in CMP_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit TRG_TBWC0:1; /**< \brief [12:12] Trigger TBWC0 bit in CMP_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit TRG_TBWC1:1; /**< \brief [13:13] Trigger TBWC1 bit in CMP_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit TRG_TBWC2:1; /**< \brief [14:14] Trigger TBWC2 bit in CMP_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit TRG_TBWC3:1; /**< \brief [15:15] Trigger TBWC3 bit in CMP_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit TRG_TBWC4:1; /**< \brief [16:16] Trigger TBWC4 bit in CMP_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit TRG_TBWC5:1; /**< \brief [17:17] Trigger TBWC5 bit in CMP_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit TRG_TBWC6:1; /**< \brief [18:18] Trigger TBWC6 bit in CMP_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit TRG_TBWC7:1; /**< \brief [19:19] Trigger TBWC7 bit in CMP_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit TRG_TBWC8:1; /**< \brief [20:20] Trigger TBWC8 bit in CMP_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit TRG_TBWC9:1; /**< \brief [21:21] Trigger TBWC9 bit in CMP_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit TRG_TBWC10:1; /**< \brief [22:22] Trigger TBWC10 bit in CMP_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit TRG_TBWC11:1; /**< \brief [23:23] Trigger TBWC11 bit in CMP_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_CMP_IRQ_FORCINT_Bits;
+
+/** \brief CMP IRQ Mode Configuration Register */
+typedef struct _Ifx_GTM_CMP_IRQ_MODE_Bits
+{
+ Ifx_Strict_32Bit IRQ_MODE:2; /**< \brief [1:0] IRQ mode selection (rw) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_GTM_CMP_IRQ_MODE_Bits;
+
+/** \brief CMP Event Notification Register */
+typedef struct _Ifx_GTM_CMP_IRQ_NOTIFY_Bits
+{
+ Ifx_Strict_32Bit ABWC0:1; /**< \brief [0:0] Error indication for ABWC0 (rwh) */
+ Ifx_Strict_32Bit ABWC1:1; /**< \brief [1:1] Error indication for ABWC1 (rwh) */
+ Ifx_Strict_32Bit ABWC2:1; /**< \brief [2:2] Error indication for ABWC2 (rwh) */
+ Ifx_Strict_32Bit ABWC3:1; /**< \brief [3:3] Error indication for ABWC3 (rwh) */
+ Ifx_Strict_32Bit ABWC4:1; /**< \brief [4:4] Error indication for ABWC4 (rwh) */
+ Ifx_Strict_32Bit ABWC5:1; /**< \brief [5:5] Error indication for ABWC5 (rwh) */
+ Ifx_Strict_32Bit ABWC6:1; /**< \brief [6:6] Error indication for ABWC6 (rwh) */
+ Ifx_Strict_32Bit ABWC7:1; /**< \brief [7:7] Error indication for ABWC7 (rwh) */
+ Ifx_Strict_32Bit ABWC8:1; /**< \brief [8:8] Error indication for ABWC8 (rwh) */
+ Ifx_Strict_32Bit ABWC9:1; /**< \brief [9:9] Error indication for ABWC9 (rwh) */
+ Ifx_Strict_32Bit ABWC10:1; /**< \brief [10:10] Error indication for ABWC10 (rwh) */
+ Ifx_Strict_32Bit ABWC11:1; /**< \brief [11:11] Error indication for ABWC11 (rwh) */
+ Ifx_Strict_32Bit TBWC0:1; /**< \brief [12:12] TOM sub modules outputs bitwise comparator 0 error indication (rwh) */
+ Ifx_Strict_32Bit TBWC1:1; /**< \brief [13:13] TOM sub modules outputs bitwise comparator 1 error indication (rwh) */
+ Ifx_Strict_32Bit TBWC2:1; /**< \brief [14:14] TOM sub modules outputs bitwise comparator 2 error indication (rwh) */
+ Ifx_Strict_32Bit TBWC3:1; /**< \brief [15:15] TOM sub modules outputs bitwise comparator 3 error indication (rwh) */
+ Ifx_Strict_32Bit TBWC4:1; /**< \brief [16:16] TOM sub modules outputs bitwise comparator 4 error indication (rwh) */
+ Ifx_Strict_32Bit TBWC5:1; /**< \brief [17:17] TOM sub modules outputs bitwise comparator 5 error indication (rwh) */
+ Ifx_Strict_32Bit TBWC6:1; /**< \brief [18:18] TOM sub modules outputs bitwise comparator 6 error indication (rwh) */
+ Ifx_Strict_32Bit TBWC7:1; /**< \brief [19:19] TOM sub modules outputs bitwise comparator 7 error indication (rwh) */
+ Ifx_Strict_32Bit TBWC8:1; /**< \brief [20:20] TOM sub modules outputs bitwise comparator 8 error indication (rwh) */
+ Ifx_Strict_32Bit TBWC9:1; /**< \brief [21:21] TOM sub modules outputs bitwise comparator 9 error indication (rwh) */
+ Ifx_Strict_32Bit TBWC10:1; /**< \brief [22:22] TOM sub modules outputs bitwise comparator 10 error indication (rwh) */
+ Ifx_Strict_32Bit TBWC11:1; /**< \brief [23:23] TOM sub modules outputs bitwise comparator 11 error indication (rwh) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_CMP_IRQ_NOTIFY_Bits;
+
+/** \brief CMU Control For Clock Source Register */
+typedef struct _Ifx_GTM_CMU_CLK0_5_CTRL_Bits
+{
+ Ifx_Strict_32Bit CLK_CNT:24; /**< \brief [23:0] Clock count Defines count value for the clock divider of clock source CMU_CLK[x] (x:0...5) (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_CMU_CLK0_5_CTRL_Bits;
+
+/** \brief CMU Control For Clock Source 6 Register */
+typedef struct _Ifx_GTM_CMU_CLK_6_CTRL_Bits
+{
+ Ifx_Strict_32Bit CLK_CNT:24; /**< \brief [23:0] Clock count. Define count value for the clock divider of clock source CMU_CLK6 (rw) */
+ Ifx_Strict_32Bit CLK6_SEL:1; /**< \brief [24:24] Clock source selection for CMU_CLK6 (rw) */
+ Ifx_Strict_32Bit reserved_25:7; /**< \brief \internal Reserved */
+} Ifx_GTM_CMU_CLK_6_CTRL_Bits;
+
+/** \brief CMU Control For Clock Source 7 Register */
+typedef struct _Ifx_GTM_CMU_CLK_7_CTRL_Bits
+{
+ Ifx_Strict_32Bit CLK_CNT:24; /**< \brief [23:0] Clock count. Define count value for the clock divider of clock source CMU_CLK7 (rw) */
+ Ifx_Strict_32Bit CLK7_SEL:1; /**< \brief [24:24] Clock source selection for CMU_CLK7 (rw) */
+ Ifx_Strict_32Bit reserved_25:7; /**< \brief \internal Reserved */
+} Ifx_GTM_CMU_CLK_7_CTRL_Bits;
+
+/** \brief CMU Clock Enable Register */
+typedef struct _Ifx_GTM_CMU_CLK_EN_Bits
+{
+ Ifx_Strict_32Bit EN_CLK0:2; /**< \brief [1:0] Enable clock source 0 (rw) */
+ Ifx_Strict_32Bit EN_CLK1:2; /**< \brief [3:2] Enable clock source 1 (rw) */
+ Ifx_Strict_32Bit EN_CLK2:2; /**< \brief [5:4] Enable clock source 2 (rw) */
+ Ifx_Strict_32Bit EN_CLK3:2; /**< \brief [7:6] Enable clock source 3 (rw) */
+ Ifx_Strict_32Bit EN_CLK4:2; /**< \brief [9:8] Enable clock source 4 (rw) */
+ Ifx_Strict_32Bit EN_CLK5:2; /**< \brief [11:10] Enable clock source 5 (rw) */
+ Ifx_Strict_32Bit EN_CLK6:2; /**< \brief [13:12] Enable clock source 6 (rw) */
+ Ifx_Strict_32Bit EN_CLK7:2; /**< \brief [15:14] Enable clock source 7 (rw) */
+ Ifx_Strict_32Bit EN_ECLK0:2; /**< \brief [17:16] Enable ECLK 0 generation subunit (rw) */
+ Ifx_Strict_32Bit EN_ECLK1:2; /**< \brief [19:18] Enable ECLK 1 generation subunit (rw) */
+ Ifx_Strict_32Bit EN_ECLK2:2; /**< \brief [21:20] Enable ECLK 2 generation subunit (rw) */
+ Ifx_Strict_32Bit EN_FXCLK:2; /**< \brief [23:22] Enable all CMU_FXCLK (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_CMU_CLK_EN_Bits;
+
+/** \brief CMU External Clock Control Denominator Register */
+typedef struct _Ifx_GTM_CMU_ECLK_DEN_Bits
+{
+ Ifx_Strict_32Bit ECLK_DEN:24; /**< \brief [23:0] Denominator for external clock divider (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_CMU_ECLK_DEN_Bits;
+
+/** \brief CMU External Clock Control Numerator Register */
+typedef struct _Ifx_GTM_CMU_ECLK_NUM_Bits
+{
+ Ifx_Strict_32Bit ECLK_NUM:24; /**< \brief [23:0] Numerator for external clock divider (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_CMU_ECLK_NUM_Bits;
+
+/** \brief CMU FXCLK Control Register */
+typedef struct _Ifx_GTM_CMU_FXCLK_CTRL_Bits
+{
+ Ifx_Strict_32Bit FXCLK_SEL:4; /**< \brief [3:0] Input clock selection for EN_FXCLK line (rw) */
+ Ifx_Strict_32Bit reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_GTM_CMU_FXCLK_CTRL_Bits;
+
+/** \brief CMU Global Clock Control Denominator Register */
+typedef struct _Ifx_GTM_CMU_GCLK_DEN_Bits
+{
+ Ifx_Strict_32Bit GCLK_DEN:24; /**< \brief [23:0] Denominator for global clock divider (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_CMU_GCLK_DEN_Bits;
+
+/** \brief CMU Global Clock Control Numerator Register */
+typedef struct _Ifx_GTM_CMU_GCLK_NUM_Bits
+{
+ Ifx_Strict_32Bit GCLK_NUM:24; /**< \brief [23:0] Numerator for global clock divider (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_CMU_GCLK_NUM_Bits;
+
+/** \brief GTM Global Control Register */
+typedef struct _Ifx_GTM_CTRL_Bits
+{
+ Ifx_Strict_32Bit RF_PROT:1; /**< \brief [0:0] RST and FORCINT protection (rw) */
+ Ifx_Strict_32Bit TO_MODE:1; /**< \brief [1:1] AEI Timeout mode (rw) */
+ Ifx_Strict_32Bit reserved_2:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit TO_VAL:5; /**< \brief [8:4] AEI Timeout value (rw) */
+ Ifx_Strict_32Bit reserved_9:23; /**< \brief \internal Reserved */
+} Ifx_GTM_CTRL_Bits;
+
+/** \brief Data Input 0 0 Register */
+typedef struct _Ifx_GTM_DATAIN_Bits
+{
+ Ifx_Strict_32Bit DATA:32; /**< \brief [31:0] Data (rw) */
+} Ifx_GTM_DATAIN_Bits;
+
+/** \brief DPLL Action Control i Register */
+typedef struct _Ifx_GTM_DPLL_ACB_Bits
+{
+ Ifx_Strict_32Bit ACB_0:5; /**< \brief [4:0] Action Control Bits of ACTION_j (rw) */
+ Ifx_Strict_32Bit reserved_5:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit ACB_1:5; /**< \brief [12:8] Action Control Bits of ACTION_(j + 1) (rw) */
+ Ifx_Strict_32Bit reserved_13:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit ACB_2:5; /**< \brief [20:16] Action Control Bits of ACTION_(j + 2) (rw) */
+ Ifx_Strict_32Bit reserved_21:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit ACB_3:5; /**< \brief [28:24] Action Control Bits of ACTION_(j + 3) (rw) */
+ Ifx_Strict_32Bit reserved_29:3; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_ACB_Bits;
+
+/** \brief DPLL ACTION Status Register With Shadow Register */
+typedef struct _Ifx_GTM_DPLL_ACT_STA_Bits
+{
+ Ifx_Strict_32Bit ACT_Ni:24; /**< \brief [23:0] New output data values concerning to action i provided (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_ACT_STA_Bits;
+
+/** \brief DPLL Calculated ADD_IN Value for SUB_INC1 Generation */
+typedef struct _Ifx_GTM_DPLL_ADD_IN_CAL1_Bits
+{
+ Ifx_Strict_32Bit ADD_IN_CAL_1:24; /**< \brief [23:0] Calculated input value for SUB_INC1 generation, calculated by the DPLL (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_ADD_IN_CAL1_Bits;
+
+/** \brief DPLL Calculated ADD_IN Value for SUB_INC2 Generation */
+typedef struct _Ifx_GTM_DPLL_ADD_IN_CAL2_Bits
+{
+ Ifx_Strict_32Bit ADD_IN_CAL_2:24; /**< \brief [23:0] Input value for SUB_INC2 generation, calculated by the DPLL for SMC=RMO=1 (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_ADD_IN_CAL2_Bits;
+
+/** \brief DPLL Direct Load Input Value for SUB_INC1 */
+typedef struct _Ifx_GTM_DPLL_ADD_IN_LD1_Bits
+{
+ Ifx_Strict_32Bit ADD_IN_LD_1:24; /**< \brief [23:0] Input value for SUB_INC1 generation (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_ADD_IN_LD1_Bits;
+
+/** \brief DPLL Direct Load Input Value for SUB_INC1 */
+typedef struct _Ifx_GTM_DPLL_ADD_IN_LD2_Bits
+{
+ Ifx_Strict_32Bit ADD_IN_LD_2:24; /**< \brief [23:0] Input value for SUB_INC2 generation (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_ADD_IN_LD2_Bits;
+
+/** \brief DPLL Adapt Values for All STATE Increments */
+typedef struct _Ifx_GTM_DPLL_ADT_S_Bits
+{
+ Ifx_Strict_32Bit PD_S:16; /**< \brief [15:0] Physical deviation of STATE (rw) */
+ Ifx_Strict_32Bit NS:6; /**< \brief [21:16] Number of STATEs (rw) */
+ Ifx_Strict_32Bit reserved_22:10; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_ADT_S_Bits;
+
+/** \brief DPLL Address Offset Register For APT In RAM Region 2 */
+typedef struct _Ifx_GTM_DPLL_AOSV_2_Bits
+{
+ Ifx_Strict_32Bit AOSV_2A:8; /**< \brief [7:0] Address offset value of the RAM 2A region (r) */
+ Ifx_Strict_32Bit AOSV_2B:8; /**< \brief [15:8] Address offset value of the RAM 2B region (r) */
+ Ifx_Strict_32Bit AOSV_2C:8; /**< \brief [23:16] Address offset value of the RAM 2C region (r) */
+ Ifx_Strict_32Bit AOSV_2D:8; /**< \brief [31:24] Address offset value of the RAM 2D region (r) */
+} Ifx_GTM_DPLL_AOSV_2_Bits;
+
+/** \brief DPLL Actual RAM Pointer to RAM Region 1C3 */
+typedef struct _Ifx_GTM_DPLL_APS_1C3_Bits
+{
+ Ifx_Strict_32Bit reserved_0:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit APS_1C3:6; /**< \brief [7:2] Address pointer STATE for RAM region 1C3 (rw) */
+ Ifx_Strict_32Bit reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_APS_1C3_Bits;
+
+/** \brief DPLL Actual RAM Pointer to RAM Regions 1C1, 1C2 and 1C4 */
+typedef struct _Ifx_GTM_DPLL_APS_Bits
+{
+ Ifx_Strict_32Bit reserved_0:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit WAPS:1; /**< \brief [1:1] Write bit for address pointer APS (w) */
+ Ifx_Strict_32Bit APS:6; /**< \brief [7:2] Address pointer STATE (rw) */
+ Ifx_Strict_32Bit reserved_8:5; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit WAPS_1C2:1; /**< \brief [13:13] Write bit for address pointer APS_1C2 (w) */
+ Ifx_Strict_32Bit APS_1C2:6; /**< \brief [19:14] Address pointer STATE for RAM region 1C2 (rw) */
+ Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_APS_Bits;
+
+/** \brief DPLL Old RAM Pointer and Offset Value for STATE */
+typedef struct _Ifx_GTM_DPLL_APS_SYNC_Bits
+{
+ Ifx_Strict_32Bit APS_1C2_EXT:6; /**< \brief [5:0] Address pointer 1C2 extension (rw) */
+ Ifx_Strict_32Bit APS_1C2_STATUS:1; /**< \brief [6:6] Address pointer 1C2 status (rwh) */
+ Ifx_Strict_32Bit reserved_7:7; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit APS_1C2_OLD:6; /**< \brief [19:14] Address pointer STATE for RAM region 1C2 at synchronization time (rw) */
+ Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_APS_SYNC_Bits;
+
+/** \brief DPLL Actual RAM Pointer to RAM Region 2C */
+typedef struct _Ifx_GTM_DPLL_APT_2C_Bits
+{
+ Ifx_Strict_32Bit reserved_0:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit APT_2C:10; /**< \brief [11:2] Address pointer TRIGGER for RAM region 2C (rw) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_APT_2C_Bits;
+
+/** \brief DPLL Actual RAM Pointer to RAM Regions 2A, B and D */
+typedef struct _Ifx_GTM_DPLL_APT_Bits
+{
+ Ifx_Strict_32Bit reserved_0:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit WAPT:1; /**< \brief [1:1] Write bit for address pointer APT (w) */
+ Ifx_Strict_32Bit APT:10; /**< \brief [11:2] Address pointer TRIGGER (rw) */
+ Ifx_Strict_32Bit reserved_12:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit WAPT_2B:1; /**< \brief [13:13] Write bit for address pointer APT_2B (w) */
+ Ifx_Strict_32Bit APT_2B:10; /**< \brief [23:14] Address pointer TRIGGER for RAM region 2B (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_APT_Bits;
+
+/** \brief DPLL Old RAM Pointer and Offset Value for TRIGGER */
+typedef struct _Ifx_GTM_DPLL_APT_SYNC_Bits
+{
+ Ifx_Strict_32Bit APT_2B_EXT:6; /**< \brief [5:0] Address pointer 2B extension (rw) */
+ Ifx_Strict_32Bit APT_2B_STATUS:1; /**< \brief [6:6] Address pointer 2B status (rwh) */
+ Ifx_Strict_32Bit reserved_7:7; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit APT_2B_OLD:10; /**< \brief [23:14] Address pointer TRIGGER for RAM region 2B at synchronization time (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_APT_SYNC_Bits;
+
+/** \brief DPLL Prediction of the actual STATE Increment */
+typedef struct _Ifx_GTM_DPLL_CDT_SX_Bits
+{
+ Ifx_Strict_32Bit CDT_SX:24; /**< \brief [23:0] Calculated duration of the current STATE increment (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_CDT_SX_Bits;
+
+/** \brief DPLL Prediction of the nominal STATE increment duration */
+typedef struct _Ifx_GTM_DPLL_CDT_SX_NOM_Bits
+{
+ Ifx_Strict_32Bit CDT_SX_NOM:24; /**< \brief [23:0] Calculated duration of the current t nominal STATE event (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_CDT_SX_NOM_Bits;
+
+/** \brief DPLL Prediction of the actual TRIGGER Increment */
+typedef struct _Ifx_GTM_DPLL_CDT_TX_Bits
+{
+ Ifx_Strict_32Bit CDT_TX:24; /**< \brief [23:0] Calculated duration of the current TRIGGER increment (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_CDT_TX_Bits;
+
+/** \brief DPLL Prediction of the nominal TRIGGER Increment duration */
+typedef struct _Ifx_GTM_DPLL_CDT_TX_NOM_Bits
+{
+ Ifx_Strict_32Bit CDT_TX_NOM:24; /**< \brief [23:0] Calculated duration of the current nominal TRIGGER event (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_CDT_TX_NOM_Bits;
+
+/** \brief DPLL Number of Sub-Pulses of SUB_INC1 in Continuous Mode */
+typedef struct _Ifx_GTM_DPLL_CNT_NUM1_Bits
+{
+ Ifx_Strict_32Bit CNT_NUM_1:24; /**< \brief [23:0] Counter for number of SUB_INC1 pulses (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_CNT_NUM1_Bits;
+
+/** \brief DPLL Number of Sub-Pulses of SUB_INC2 in Continuous Mode */
+typedef struct _Ifx_GTM_DPLL_CNT_NUM2_Bits
+{
+ Ifx_Strict_32Bit CNT_NUM_2:24; /**< \brief [23:0] Counter for number of SUB_INC2 pulses (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_CNT_NUM2_Bits;
+
+/** \brief DPLL Control 1 Shadow STATE Register */
+typedef struct _Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits
+{
+ Ifx_Strict_32Bit DMO:1; /**< \brief [0:0] DPLL mode select (r) */
+ Ifx_Strict_32Bit reserved_1:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit COA:1; /**< \brief [3:3] Correction strategy in automatic end mode (DMO=0) (r) */
+ Ifx_Strict_32Bit PIT:1; /**< \brief [4:4] Plausibility (r) */
+ Ifx_Strict_32Bit SGE1:1; /**< \brief [5:5] SUB_INC1 generator enable (r) */
+ Ifx_Strict_32Bit DLM1:1; /**< \brief [6:6] Direct Load Mode (r) */
+ Ifx_Strict_32Bit PCM1:1; /**< \brief [7:7] Pulse Correction Mode (r) */
+ Ifx_Strict_32Bit SGE2:1; /**< \brief [8:8] SUB_INC2 generator enable (r) */
+ Ifx_Strict_32Bit DLM2:1; /**< \brief [9:9] Direct Load Mode (r) */
+ Ifx_Strict_32Bit PCM2:1; /**< \brief [10:10] Pulse Correction Mode (r) */
+ Ifx_Strict_32Bit SYN_NS:21; /**< \brief [31:11] Synchronization number of STATE (r) */
+} Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits;
+
+/** \brief DPLL Control Register 0 */
+typedef struct _Ifx_GTM_DPLL_CTRL_0_Bits
+{
+ Ifx_Strict_32Bit MLT:10; /**< \brief [9:0] Multiplier for TRIGGER (rw) */
+ Ifx_Strict_32Bit IFP:1; /**< \brief [10:10] Input filter position (rw) */
+ Ifx_Strict_32Bit SNU:5; /**< \brief [15:11] STATE number (rw) */
+ Ifx_Strict_32Bit TNU:9; /**< \brief [24:16] TRIGGER number (rw) */
+ Ifx_Strict_32Bit AMS:1; /**< \brief [25:25] Adapt mode STATE (rw) */
+ Ifx_Strict_32Bit AMT:1; /**< \brief [26:26] Adapt mode TRIGGER (rw) */
+ Ifx_Strict_32Bit IDS:1; /**< \brief [27:27] Input delay STATE (rw) */
+ Ifx_Strict_32Bit IDT:1; /**< \brief [28:28] Input delay TRIGGER (rw) */
+ Ifx_Strict_32Bit SEN:1; /**< \brief [29:29] STATE enable (rw) */
+ Ifx_Strict_32Bit TEN:1; /**< \brief [30:30] TRIGGER enable (rw) */
+ Ifx_Strict_32Bit RMO:1; /**< \brief [31:31] Reference mode (rw) */
+} Ifx_GTM_DPLL_CTRL_0_Bits;
+
+/** \brief DPLL Control 0 Shadow STATE Register */
+typedef struct _Ifx_GTM_DPLL_CTRL_0_SHADOW_STATE_Bits
+{
+ Ifx_Strict_32Bit reserved_0:10; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit IFP:1; /**< \brief [10:10] Input filter position (r) */
+ Ifx_Strict_32Bit reserved_11:14; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit AMS:1; /**< \brief [25:25] Adapt mode STATE (r) */
+ Ifx_Strict_32Bit reserved_26:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit IDS:1; /**< \brief [27:27] Input delay STATE (r) */
+ Ifx_Strict_32Bit reserved_28:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit RMO:1; /**< \brief [31:31] Reference mode; selection of the relevant the input signal for generation of SUB_INC1 (r) */
+} Ifx_GTM_DPLL_CTRL_0_SHADOW_STATE_Bits;
+
+/** \brief DPLL Control0 Shadow Trigger Register */
+typedef struct _Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits
+{
+ Ifx_Strict_32Bit MLT:10; /**< \brief [9:0] multiplier for TRIGGER (r) */
+ Ifx_Strict_32Bit IFP:1; /**< \brief [10:10] Input filter position (r) */
+ Ifx_Strict_32Bit reserved_11:15; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit AMT:1; /**< \brief [26:26] Adapt mode TRIGGER (r) */
+ Ifx_Strict_32Bit IDS:1; /**< \brief [27:27] Input delay STATE (r) */
+ Ifx_Strict_32Bit IDT:1; /**< \brief [28:28] Input delay TRIGGER (r) */
+ Ifx_Strict_32Bit reserved_29:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit RMO:1; /**< \brief [31:31] Reference mode; selection of the relevant the input signal for generation of SUB_INC1 (r) */
+} Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits;
+
+/** \brief DPLL Control Register 1 */
+typedef struct _Ifx_GTM_DPLL_CTRL_1_Bits
+{
+ Ifx_Strict_32Bit DMO:1; /**< \brief [0:0] DPLL mode select (rw) */
+ Ifx_Strict_32Bit DEN:1; /**< \brief [1:1] DPLL enable (rw) */
+ Ifx_Strict_32Bit IDDS:1; /**< \brief [2:2] Input direction detection strategy in case of SMC = 0 (rw) */
+ Ifx_Strict_32Bit COA:1; /**< \brief [3:3] Correction strategy in automatic end mode (DMO=0) (rw) */
+ Ifx_Strict_32Bit PIT:1; /**< \brief [4:4] Plausibility value PVT to next valid TRIGGER is time related (rw) */
+ Ifx_Strict_32Bit SGE1:1; /**< \brief [5:5] SUB_INC1 generator enable (rw) */
+ Ifx_Strict_32Bit DLM1:1; /**< \brief [6:6] Direct Load Mode for SUB_INC1 generation (rw) */
+ Ifx_Strict_32Bit PCM1:1; /**< \brief [7:7] Pulse Correction Mode for SUB_INC1 generation (rw) */
+ Ifx_Strict_32Bit SGE2:1; /**< \brief [8:8] SUB_INC2 generator enable (rw) */
+ Ifx_Strict_32Bit DLM2:1; /**< \brief [9:9] Direct Load Mode for SUB_INC2 generation (rw) */
+ Ifx_Strict_32Bit PCM2:1; /**< \brief [10:10] Pulse Correction Mode for SUB_INC2 generation (rw) */
+ Ifx_Strict_32Bit SYN_NS:5; /**< \brief [15:11] Synchronization number of STATE (rw) */
+ Ifx_Strict_32Bit SYN_NT:5; /**< \brief [20:16] Synchronization number of TRIGGER (rw) */
+ Ifx_Strict_32Bit reserved_21:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit LCD:1; /**< \brief [22:22] Locking condition definition (rw) */
+ Ifx_Strict_32Bit SWR:1; /**< \brief [23:23] Software Reset (w) */
+ Ifx_Strict_32Bit SYSF:1; /**< \brief [24:24] SYN_NS for FULL_SCALE (rw) */
+ Ifx_Strict_32Bit TS0_HRS:1; /**< \brief [25:25] TS0_HRS (rw) */
+ Ifx_Strict_32Bit TS0_HRT:1; /**< \brief [26:26] TS0_HRT (rw) */
+ Ifx_Strict_32Bit SMC:1; /**< \brief [27:27] Synchronous Motor Control (rw) */
+ Ifx_Strict_32Bit SSL:2; /**< \brief [29:28] STATE slope select (rw) */
+ Ifx_Strict_32Bit TSL:2; /**< \brief [31:30] Definition of active slope for signal TRIGGER each active slope is an event defined by TNU (rw) */
+} Ifx_GTM_DPLL_CTRL_1_Bits;
+
+/** \brief DPLL Control 1 Shadow TRIGGER Register */
+typedef struct _Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits
+{
+ Ifx_Strict_32Bit DMO:1; /**< \brief [0:0] DPLL mode select (r) */
+ Ifx_Strict_32Bit reserved_1:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit COA:1; /**< \brief [3:3] Correction strategy in automatic end mode (DMO=0) (r) */
+ Ifx_Strict_32Bit PIT:1; /**< \brief [4:4] Plausibility (r) */
+ Ifx_Strict_32Bit SGE1:1; /**< \brief [5:5] SUB_INC1 generator enable (r) */
+ Ifx_Strict_32Bit DLM1:1; /**< \brief [6:6] Direct Load Mode (r) */
+ Ifx_Strict_32Bit PCM1:1; /**< \brief [7:7] Pulse Correction Mode (r) */
+ Ifx_Strict_32Bit reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits;
+
+/** \brief DPLL Control Register 2 */
+typedef struct _Ifx_GTM_DPLL_CTRL_2_Bits
+{
+ Ifx_Strict_32Bit reserved_0:8; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit AEN0:1; /**< \brief [8:8] ACTION_0 enable (rw) */
+ Ifx_Strict_32Bit AEN1:1; /**< \brief [9:9] ACTION_1 enable (rw) */
+ Ifx_Strict_32Bit AEN2:1; /**< \brief [10:10] ACTION_2 enable (rw) */
+ Ifx_Strict_32Bit AEN3:1; /**< \brief [11:11] ACTION_3 enable (rw) */
+ Ifx_Strict_32Bit AEN4:1; /**< \brief [12:12] ACTION_4 enable (rw) */
+ Ifx_Strict_32Bit AEN5:1; /**< \brief [13:13] ACTION_5 enable (rw) */
+ Ifx_Strict_32Bit AEN6:1; /**< \brief [14:14] ACTION_6 enable (rw) */
+ Ifx_Strict_32Bit AEN7:1; /**< \brief [15:15] ACTION_7 enable (rw) */
+ Ifx_Strict_32Bit WAD0:1; /**< \brief [16:16] Write control bit of Action_0 (w) */
+ Ifx_Strict_32Bit WAD1:1; /**< \brief [17:17] Write control bit of Action_1 (w) */
+ Ifx_Strict_32Bit WAD2:1; /**< \brief [18:18] Write control bit of Action_2 (w) */
+ Ifx_Strict_32Bit WAD3:1; /**< \brief [19:19] Write control bit of Action_3 (w) */
+ Ifx_Strict_32Bit WAD4:1; /**< \brief [20:20] Write control bit of Action_4 (w) */
+ Ifx_Strict_32Bit WAD5:1; /**< \brief [21:21] Write control bit of Action_5 (w) */
+ Ifx_Strict_32Bit WAD6:1; /**< \brief [22:22] Write control bit of Action_6 (w) */
+ Ifx_Strict_32Bit WAD7:1; /**< \brief [23:23] Write control bit of Action_7 (w) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_CTRL_2_Bits;
+
+/** \brief DPLL Control Register 3 */
+typedef struct _Ifx_GTM_DPLL_CTRL_3_Bits
+{
+ Ifx_Strict_32Bit reserved_0:8; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit AEN8:1; /**< \brief [8:8] ACTION_8 enable (rw) */
+ Ifx_Strict_32Bit AEN9:1; /**< \brief [9:9] ACTION_9 enable (rw) */
+ Ifx_Strict_32Bit AEN10:1; /**< \brief [10:10] ACTION_10enable (rw) */
+ Ifx_Strict_32Bit AEN11:1; /**< \brief [11:11] ACTION_11 enable (rw) */
+ Ifx_Strict_32Bit AEN12:1; /**< \brief [12:12] ACTION_12 enable (rw) */
+ Ifx_Strict_32Bit AEN13:1; /**< \brief [13:13] ACTION_13 enable (rw) */
+ Ifx_Strict_32Bit AEN14:1; /**< \brief [14:14] ACTION_14 enable (rw) */
+ Ifx_Strict_32Bit AEN15:1; /**< \brief [15:15] ACTION_15 enable (rw) */
+ Ifx_Strict_32Bit WAD8:1; /**< \brief [16:16] Write control bit of Action_8 (w) */
+ Ifx_Strict_32Bit WAD9:1; /**< \brief [17:17] Write control bit of Action_9 (w) */
+ Ifx_Strict_32Bit WAD10:1; /**< \brief [18:18] Write control bit of Action_10 (w) */
+ Ifx_Strict_32Bit WAD11:1; /**< \brief [19:19] Write control bit of Action_11 (w) */
+ Ifx_Strict_32Bit WAD12:1; /**< \brief [20:20] Write control bit of Action_12 (w) */
+ Ifx_Strict_32Bit WAD13:1; /**< \brief [21:21] Write control bit of Action_13 (w) */
+ Ifx_Strict_32Bit WAD14:1; /**< \brief [22:22] Write control bit of Action_14 (w) */
+ Ifx_Strict_32Bit WAD15:1; /**< \brief [23:23] Write control bit of Action_15 (w) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_CTRL_3_Bits;
+
+/** \brief DPLL Control Register 4 */
+typedef struct _Ifx_GTM_DPLL_CTRL_4_Bits
+{
+ Ifx_Strict_32Bit reserved_0:8; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit AEN16:1; /**< \brief [8:8] ACTION_16 enable (rw) */
+ Ifx_Strict_32Bit AEN17:1; /**< \brief [9:9] ACTION_17 enable (rw) */
+ Ifx_Strict_32Bit AEN18:1; /**< \brief [10:10] ACTION_18 enable (rw) */
+ Ifx_Strict_32Bit AEN19:1; /**< \brief [11:11] ACTION_19 enable (rw) */
+ Ifx_Strict_32Bit AEN20:1; /**< \brief [12:12] ACTION_20 enable (rw) */
+ Ifx_Strict_32Bit AEN21:1; /**< \brief [13:13] ACTION_21 enable (rw) */
+ Ifx_Strict_32Bit AEN22:1; /**< \brief [14:14] ACTION_22 enable (rw) */
+ Ifx_Strict_32Bit AEN23:1; /**< \brief [15:15] ACTION_23 enable (rw) */
+ Ifx_Strict_32Bit WAD16:1; /**< \brief [16:16] Write control bit of Action_16 (w) */
+ Ifx_Strict_32Bit WAD17:1; /**< \brief [17:17] Write control bit of Action_17 (w) */
+ Ifx_Strict_32Bit WAD18:1; /**< \brief [18:18] Write control bit of Action_18 (w) */
+ Ifx_Strict_32Bit WAD19:1; /**< \brief [19:19] Write control bit of Action_19 (w) */
+ Ifx_Strict_32Bit WAD20:1; /**< \brief [20:20] Write control bit of Action_20 (w) */
+ Ifx_Strict_32Bit WAD21:1; /**< \brief [21:21] Write control bit of Action_21 (w) */
+ Ifx_Strict_32Bit WAD22:1; /**< \brief [22:22] Write control bit of Action_22 (w) */
+ Ifx_Strict_32Bit WAD23:1; /**< \brief [23:23] Write control bit of Action_23 (w) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_CTRL_4_Bits;
+
+/** \brief DPLL ACTION Time To React Before PSAi Register */
+typedef struct _Ifx_GTM_DPLL_DLA_Bits
+{
+ Ifx_Strict_32Bit DLA:24; /**< \brief [23:0] Time to react before the corresponding position value of a desired action is reached (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_DLA_Bits;
+
+/** \brief DPLL Duration of Last STATE Increment [DT_S_ACT] */
+typedef struct _Ifx_GTM_DPLL_DT_S_ACT_Bits
+{
+ Ifx_Strict_32Bit DT_S_ACT:24; /**< \brief [23:0] Calculated duration of the last STATE increment (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_DT_S_ACT_Bits;
+
+/** \brief DPLL Nominal STATE Increment Values for FULL_SCALE */
+typedef struct _Ifx_GTM_DPLL_DT_S_Bits
+{
+ Ifx_Strict_32Bit DT_S:24; /**< \brief [23:0] Difference time of STATE (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_DT_S_Bits;
+
+/** \brief DPLL Duration of Last TRIGGER Increment */
+typedef struct _Ifx_GTM_DPLL_DT_T_ACT_Bits
+{
+ Ifx_Strict_32Bit DT_T_ACT:24; /**< \brief [23:0] Calculated duration of the last TRIGGER increment (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_DT_T_ACT_Bits;
+
+/** \brief DPLL Calculated Relative Time To ACTION_i Register */
+typedef struct _Ifx_GTM_DPLL_DTA_Bits
+{
+ Ifx_Strict_32Bit DTA:24; /**< \brief [23:0] Calculated relative time to ACTION_i (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_DTA_Bits;
+
+/** \brief DPLL Difference of Prediction to actual value for Last STATE
+ * Increment */
+typedef struct _Ifx_GTM_DPLL_EDT_S_Bits
+{
+ Ifx_Strict_32Bit EDT_S:24; /**< \brief [23:0] Signed difference between actual value and prediction of the last STATE increment: sint24 (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_EDT_S_Bits;
+
+/** \brief DPLL Difference of prediction to actual value of the last TRIGGER
+ * increment */
+typedef struct _Ifx_GTM_DPLL_EDT_T_Bits
+{
+ Ifx_Strict_32Bit EDT_T:24; /**< \brief [23:0] Signed difference between actual value and a simple prediction of the last TRIGGER increment: sint24 (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_EDT_T_Bits;
+
+/** \brief DPLL Error Interrupt Enable Register */
+typedef struct _Ifx_GTM_DPLL_EIRQ_EN_Bits
+{
+ Ifx_Strict_32Bit PDI_EIRQ_EN:1; /**< \brief [0:0] DPLL disable interrupt enable, when switch off of the DEN bit (rw) */
+ Ifx_Strict_32Bit PEI_EIRQ_EN:1; /**< \brief [1:1] DPLL enable interrupt enable, when switch on of the DEN bit (rw) */
+ Ifx_Strict_32Bit TINI_EIRQ_EN:1; /**< \brief [2:2] TRIGGER minimum hold time violation interrupt enable bit. (rw) */
+ Ifx_Strict_32Bit TAXI_EIRQ_EN:1; /**< \brief [3:3] TRIGGER maximum hold time violation interrupt enable bit (rw) */
+ Ifx_Strict_32Bit SISI_EIRQ_EN:1; /**< \brief [4:4] STATE inactive slope interrupt enable bit (rw) */
+ Ifx_Strict_32Bit TISI_EIRQ_EN:1; /**< \brief [5:5] TRIGGER inactive slope interrupt enable bit (rw) */
+ Ifx_Strict_32Bit MSI_EIRQ_EN:1; /**< \brief [6:6] Missing STATE interrupt enable (rw) */
+ Ifx_Strict_32Bit MTI_EIRQ_EN:1; /**< \brief [7:7] Missing TRIGGER interrupt enable (rw) */
+ Ifx_Strict_32Bit SASI_EIRQ_EN:1; /**< \brief [8:8] STATE active slope interrupt enable (rw) */
+ Ifx_Strict_32Bit TASI_EIRQ_EN:1; /**< \brief [9:9] TRIGGER active slope interrupt enable (rw) */
+ Ifx_Strict_32Bit PWI_EIRQ_EN:1; /**< \brief [10:10] Plausibility window (PVT) violation interrupt of TRIGGER enable (rw) */
+ Ifx_Strict_32Bit W2I_EIRQ_EN:1; /**< \brief [11:11] RAM write access to RAM region 2 interrupt enable (rw) */
+ Ifx_Strict_32Bit W1I_EIRQ_EN:1; /**< \brief [12:12] Write access to RAM region 1B or 1C interrupt (rw) */
+ Ifx_Strict_32Bit GL1I_EIRQ_EN:1; /**< \brief [13:13] Get of lock interrupt enable, when lock arises (rw) */
+ Ifx_Strict_32Bit LL1I_EIRQ_EN:1; /**< \brief [14:14] Loss of lock interrupt enable (rw) */
+ Ifx_Strict_32Bit EI_EIRQ_EN:1; /**< \brief [15:15] Error interrupt enable (see status register) (rw) */
+ Ifx_Strict_32Bit GL2I_EIRQ_EN:1; /**< \brief [16:16] Get of lock interrupt enable for SUB_INC2 (rw) */
+ Ifx_Strict_32Bit LL2I_EIRQ_EN:1; /**< \brief [17:17] Loss of lock interrupt enable for SUB_INC2 (rw) */
+ Ifx_Strict_32Bit TE0I_EIRQ_EN:1; /**< \brief [18:18] TRIGGER event interrupt 0 enable (rw) */
+ Ifx_Strict_32Bit TE1I_EIRQ_EN:1; /**< \brief [19:19] TRIGGER event interrupt 1 enable (rw) */
+ Ifx_Strict_32Bit TE2I_EIRQ_EN:1; /**< \brief [20:20] TRIGGER event interrupt 2 enable (rw) */
+ Ifx_Strict_32Bit TE3I_EIRQ_EN:1; /**< \brief [21:21] TRIGGER event interrupt 3 enable (rw) */
+ Ifx_Strict_32Bit TE4I_EIRQ_EN:1; /**< \brief [22:22] TRIGGER event interrupt 4 enable (rw) */
+ Ifx_Strict_32Bit CDTI_EIRQ_EN:1; /**< \brief [23:23] Enable interrupt when calculation of TRIGGER duration done (rw) */
+ Ifx_Strict_32Bit CDSI_EIRQ_EN:1; /**< \brief [24:24] Enable interrupt when calculation of TRIGGER duration done (rw) */
+ Ifx_Strict_32Bit TORI:1; /**< \brief [25:25] TRIGGER out of range interrupt (rw) */
+ Ifx_Strict_32Bit SORI:1; /**< \brief [26:26] STATE out of range (rw) */
+ Ifx_Strict_32Bit DCGI:1; /**< \brief [27:27] Direction change interrupt (rw) */
+ Ifx_Strict_32Bit reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_EIRQ_EN_Bits;
+
+/** \brief DPLL Actual Signal STATE Filter Value Register */
+typedef struct _Ifx_GTM_DPLL_FTV_S_Bits
+{
+ Ifx_Strict_32Bit STATE_FT:24; /**< \brief [23:0] Filter value of the last valid STATE input (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_FTV_S_Bits;
+
+/** \brief DPLL Actual Signal TRIGGER Filter Value Register */
+typedef struct _Ifx_GTM_DPLL_FTV_T_Bits
+{
+ Ifx_Strict_32Bit TRIGGER_FT:24; /**< \brief [23:0] Filter value of the last valid TRIGGER input (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_FTV_T_Bits;
+
+/** \brief DPLL ID Information For Input Signal PMTR Register */
+typedef struct _Ifx_GTM_DPLL_ID_PMTR_Bits
+{
+ Ifx_Strict_32Bit ID_PMTR_x:9; /**< \brief [8:0] ID information to the input signal PMTR_x from the ARU (rw) */
+ Ifx_Strict_32Bit reserved_9:23; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_ID_PMTR_Bits;
+
+/** \brief DPLL Counter for Pulses for TBU_TS1 to be sent in Automatic End Mode */
+typedef struct _Ifx_GTM_DPLL_INC_CNT1_Bits
+{
+ Ifx_Strict_32Bit INC_CNT1:24; /**< \brief [23:0] Actual number of pulses to be still sent out at the current increment until the next valid input signal in automatic end mode (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_INC_CNT1_Bits;
+
+/** \brief DPLL Counter for Pulses for TBU_TS2 to be sent in Automatic End Mode
+ * when SMC=RMO=1 */
+typedef struct _Ifx_GTM_DPLL_INC_CNT2_Bits
+{
+ Ifx_Strict_32Bit INC_CNT2:24; /**< \brief [23:0] Actual number of pulses to be still sent out at the current increment until the next valid input signal in automatic end mode (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_INC_CNT2_Bits;
+
+/** \brief DPLL Interrupt Enable Register */
+typedef struct _Ifx_GTM_DPLL_IRQ_EN_Bits
+{
+ Ifx_Strict_32Bit PDI_IRQ_EN:1; /**< \brief [0:0] DPLL disable interrupt enable, when switch off of the DEN bit (rw) */
+ Ifx_Strict_32Bit PEI_IRQ_EN:1; /**< \brief [1:1] DPLL enable interrupt enable, when switch on of the DEN bit (rw) */
+ Ifx_Strict_32Bit TINI_IRQ_EN:1; /**< \brief [2:2] TRIGGER minimum hold time violation interrupt enable bit (rw) */
+ Ifx_Strict_32Bit TAXI_IRQ_EN:1; /**< \brief [3:3] TRIGGER maximum hold time violation interrupt enable bit (rw) */
+ Ifx_Strict_32Bit SISI_IRQ_EN:1; /**< \brief [4:4] STATE inactive slope interrupt enable bit (rw) */
+ Ifx_Strict_32Bit TISI_IRQ_EN:1; /**< \brief [5:5] TRIGGER inactive slope interrupt enable bit (rw) */
+ Ifx_Strict_32Bit MSI_IRQ_EN:1; /**< \brief [6:6] Missing STATE interrupt enable (rw) */
+ Ifx_Strict_32Bit MTI_IRQ_EN:1; /**< \brief [7:7] Missing TRIGGER interrupt enable (rw) */
+ Ifx_Strict_32Bit SASI_IRQ_EN:1; /**< \brief [8:8] STATE active slope interrupt enable (rw) */
+ Ifx_Strict_32Bit TASI_IRQ_EN:1; /**< \brief [9:9] TRIGGER active slope interrupt enable (rw) */
+ Ifx_Strict_32Bit PWI_IRQ_EN:1; /**< \brief [10:10] Plausibility window (PVT) violation interrupt of TRIGGER enable (rw) */
+ Ifx_Strict_32Bit W2I_IRQ_EN:1; /**< \brief [11:11] RAM write access to RAM region 2 interrupt enable (rw) */
+ Ifx_Strict_32Bit W1I_IRQ_EN:1; /**< \brief [12:12] Write access to RAM region 1B or 1C interrupt (rw) */
+ Ifx_Strict_32Bit GL1I_IRQ_EN:1; /**< \brief [13:13] Get of lock interrupt enable, when lock arises (rw) */
+ Ifx_Strict_32Bit LL1I_IRQ_EN:1; /**< \brief [14:14] Loss of lock interrupt enable (rw) */
+ Ifx_Strict_32Bit EI_IRQ_EN:1; /**< \brief [15:15] Error interrupt enable (see status register) (rw) */
+ Ifx_Strict_32Bit GL2I_IRQ_EN:1; /**< \brief [16:16] Get of lock interrupt enable for SUB_INC2 (rw) */
+ Ifx_Strict_32Bit LL2I_IRQ_EN:1; /**< \brief [17:17] Loss of lock interrupt enable for SUB_INC2 (rw) */
+ Ifx_Strict_32Bit TE0I_IRQ_EN:1; /**< \brief [18:18] TRIGGER event interrupt 0 enable (rw) */
+ Ifx_Strict_32Bit TE1I_IRQ_EN:1; /**< \brief [19:19] TRIGGER event interrupt 1 enable (rw) */
+ Ifx_Strict_32Bit TE2I_IRQ_EN:1; /**< \brief [20:20] TRIGGER event interrupt 2 enable (rw) */
+ Ifx_Strict_32Bit TE3I_IRQ_EN:1; /**< \brief [21:21] TRIGGER event interrupt 3 enable (rw) */
+ Ifx_Strict_32Bit TE4I_IRQ_EN:1; /**< \brief [22:22] TRIGGER event interrupt 4 enable (rw) */
+ Ifx_Strict_32Bit CDTI_IRQ_EN:1; /**< \brief [23:23] Enable interrupt when calculation of TRIGGER duration done (rw) */
+ Ifx_Strict_32Bit CDSI_IRQ_EN:1; /**< \brief [24:24] Enable interrupt when calculation of TRIGGER duration done (rw) */
+ Ifx_Strict_32Bit TORI:1; /**< \brief [25:25] TRIGGER out of range interrupt (rw) */
+ Ifx_Strict_32Bit SORI:1; /**< \brief [26:26] STATE out of range (rw) */
+ Ifx_Strict_32Bit DCGI:1; /**< \brief [27:27] Direction change interrupt (rw) */
+ Ifx_Strict_32Bit reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_IRQ_EN_Bits;
+
+/** \brief DPLL Interrupt Force Register */
+typedef struct _Ifx_GTM_DPLL_IRQ_FORCINT_Bits
+{
+ Ifx_Strict_32Bit TRG_PDI:1; /**< \brief [0:0] Force Interrupt PDI (w) */
+ Ifx_Strict_32Bit TRG_PEI:1; /**< \brief [1:1] Force Interrupt PEI (w) */
+ Ifx_Strict_32Bit TRG_TINI:1; /**< \brief [2:2] Force Interrupt TINI (w) */
+ Ifx_Strict_32Bit TRG_TAXI:1; /**< \brief [3:3] Force Interrupt TAXI (w) */
+ Ifx_Strict_32Bit TRG_SISI:1; /**< \brief [4:4] Force Interrupt SISI (w) */
+ Ifx_Strict_32Bit TRG_TISI:1; /**< \brief [5:5] Force Interrupt TISI (w) */
+ Ifx_Strict_32Bit TRG_MSI:1; /**< \brief [6:6] Force Interrupt MSI (w) */
+ Ifx_Strict_32Bit TRG_MTI:1; /**< \brief [7:7] Force Interrupt MTI (w) */
+ Ifx_Strict_32Bit TRG_SASI:1; /**< \brief [8:8] Force Interrupt SASI (w) */
+ Ifx_Strict_32Bit TRG_TASI:1; /**< \brief [9:9] Force Interrupt TASI (w) */
+ Ifx_Strict_32Bit TRG_PWI:1; /**< \brief [10:10] Force Interrupt PWI (w) */
+ Ifx_Strict_32Bit TRG_W2I:1; /**< \brief [11:11] Force Interrupt W2IF (w) */
+ Ifx_Strict_32Bit TRG_W1I:1; /**< \brief [12:12] Force Interrupt W1I (w) */
+ Ifx_Strict_32Bit TRG_GL1I:1; /**< \brief [13:13] Force Interrupt GL1I (w) */
+ Ifx_Strict_32Bit TRG_LL1I:1; /**< \brief [14:14] Force Interrupt LL1I (w) */
+ Ifx_Strict_32Bit TRG_EI:1; /**< \brief [15:15] Force Interrupt EI (w) */
+ Ifx_Strict_32Bit TRG_GL2I:1; /**< \brief [16:16] Force Interrupt GL2I (w) */
+ Ifx_Strict_32Bit TRG_LL2I:1; /**< \brief [17:17] Force Interrupt LL2I (w) */
+ Ifx_Strict_32Bit TRG_TE0I:1; /**< \brief [18:18] Force Interrupt TE0I (w) */
+ Ifx_Strict_32Bit TRG_TE1I:1; /**< \brief [19:19] Force Interrupt TE1I (w) */
+ Ifx_Strict_32Bit TRG_TE2I:1; /**< \brief [20:20] Force Interrupt TE2I (w) */
+ Ifx_Strict_32Bit TRG_TE3I:1; /**< \brief [21:21] Force Interrupt TE3I (w) */
+ Ifx_Strict_32Bit TRG_TE4I:1; /**< \brief [22:22] Force Interrupt TE4I (w) */
+ Ifx_Strict_32Bit TRG_CDTI:1; /**< \brief [23:23] Force Interrupt CDTI (w) */
+ Ifx_Strict_32Bit TRG_CDSI:1; /**< \brief [24:24] Force Interrupt CDSI (w) */
+ Ifx_Strict_32Bit TRG_TORI:1; /**< \brief [25:25] Force Interrupt TORI (w) */
+ Ifx_Strict_32Bit TRG_SORI:1; /**< \brief [26:26] Force Interrupt SORI (w) */
+ Ifx_Strict_32Bit TRG_DCGI:1; /**< \brief [27:27] Force Interrupt DCGI (w) */
+ Ifx_Strict_32Bit reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_IRQ_FORCINT_Bits;
+
+/** \brief DPLL Interrupt Mode Register */
+typedef struct _Ifx_GTM_DPLL_IRQ_MODE_Bits
+{
+ Ifx_Strict_32Bit IRQ_MODE:2; /**< \brief [1:0] IRQ mode selection (rw) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_IRQ_MODE_Bits;
+
+/** \brief DPLL Interrupt Notification Register */
+typedef struct _Ifx_GTM_DPLL_IRQ_NOTIFY_Bits
+{
+ Ifx_Strict_32Bit PDI:1; /**< \brief [0:0] DPLL disable interrupt (rwh) */
+ Ifx_Strict_32Bit PEI:1; /**< \brief [1:1] DPLL enable interrupt (rwh) */
+ Ifx_Strict_32Bit TINI:1; /**< \brief [2:2] TRIGGER minimum hold time violation interrupt (鈭員) (rwh) */
+ Ifx_Strict_32Bit TAXI:1; /**< \brief [3:3] TRIGGER maximum hold time violation interrupt (鈭員>THMA>0) (rwh) */
+ Ifx_Strict_32Bit SISI:1; /**< \brief [4:4] STATE inactive slope interrupt (rwh) */
+ Ifx_Strict_32Bit TISI:1; /**< \brief [5:5] TRIGGER inactive slope interrupt (rwh) */
+ Ifx_Strict_32Bit MSI:1; /**< \brief [6:6] Missing STATE interrupt (rwh) */
+ Ifx_Strict_32Bit MTI:1; /**< \brief [7:7] Missing TRIGGER interrupt (rwh) */
+ Ifx_Strict_32Bit SASI:1; /**< \brief [8:8] STATE active slope interrupt (rwh) */
+ Ifx_Strict_32Bit TASI:1; /**< \brief [9:9] TRIGGER active slope interrupt (rwh) */
+ Ifx_Strict_32Bit PWI:1; /**< \brief [10:10] Plausibility window (PVT) violation interrupt of TRIGGER (rwh) */
+ Ifx_Strict_32Bit W2I:1; /**< \brief [11:11] RAM write access to RAM region 2 interrupt (rwh) */
+ Ifx_Strict_32Bit W1I:1; /**< \brief [12:12] Write access to RAM region 1B or 1C interrupt (rwh) */
+ Ifx_Strict_32Bit GL1I:1; /**< \brief [13:13] Get of lock interrupt, for SUB_INC1 (rwh) */
+ Ifx_Strict_32Bit LL1I:1; /**< \brief [14:14] Loss of lock interrupt for SUB_INC1 (rwh) */
+ Ifx_Strict_32Bit EI:1; /**< \brief [15:15] Error interrupt (see status register bit 31) (rwh) */
+ Ifx_Strict_32Bit GL2I:1; /**< \brief [16:16] Get of lock interrupt, for SUB_INC2 (rwh) */
+ Ifx_Strict_32Bit LL2I:1; /**< \brief [17:17] Loss of lock interrupt for SUB_INC2 (rwh) */
+ Ifx_Strict_32Bit TE0I:1; /**< \brief [18:18] TRIGGER event interrupt 0 (rwh) */
+ Ifx_Strict_32Bit TE1I:1; /**< \brief [19:19] TRIGGER event interrupt 1 (rwh) */
+ Ifx_Strict_32Bit TE2I:1; /**< \brief [20:20] TRIGGER event interrupt 2 (rwh) */
+ Ifx_Strict_32Bit TE3I:1; /**< \brief [21:21] TRIGGER event interrupt 3 (rwh) */
+ Ifx_Strict_32Bit TE4I:1; /**< \brief [22:22] TRIGGER event interrupt 4 (rwh) */
+ Ifx_Strict_32Bit CDTI:1; /**< \brief [23:23] Calculation of TRIGGER duration done, only while NTI_CNT is zero (rwh) */
+ Ifx_Strict_32Bit CDSI:1; /**< \brief [24:24] Calculation of STATE duration done (rwh) */
+ Ifx_Strict_32Bit TORI:1; /**< \brief [25:25] TRIGGER out of range interrupt (rwh) */
+ Ifx_Strict_32Bit SORI:1; /**< \brief [26:26] STATE out of range (rwh) */
+ Ifx_Strict_32Bit DCGI:1; /**< \brief [27:27] Direction change interrupt (rwh) */
+ Ifx_Strict_32Bit reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_IRQ_NOTIFY_Bits;
+
+/** \brief DPLL Weighted difference of Prediction up to the Last STATE
+ * Increment */
+typedef struct _Ifx_GTM_DPLL_MEDT_S_Bits
+{
+ Ifx_Strict_32Bit MEDT_S:24; /**< \brief [23:0] Signed middle weighted difference between actual value and prediction of the last STATE increments: sint24 (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_MEDT_S_Bits;
+
+/** \brief DPLL Weighted difference of Prediction up to the Last TRIGGER
+ * Increment */
+typedef struct _Ifx_GTM_DPLL_MEDT_T_Bits
+{
+ Ifx_Strict_32Bit MEDT_T:24; /**< \brief [23:0] Signed middle weighted difference between actual value and prediction of the last TRIGGER increments: sint24 (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_MEDT_T_Bits;
+
+/** \brief DPLL Calculated Number of Sub-Pulses between Two STATE Events */
+typedef struct _Ifx_GTM_DPLL_MLS1_Bits
+{
+ Ifx_Strict_32Bit MLS1:18; /**< \brief [17:0] Number of pulses between two STATE events (to be set and updated by the CPU) (rw) */
+ Ifx_Strict_32Bit reserved_18:14; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_MLS1_Bits;
+
+/** \brief DPLL Calculated Number of Sub-Pulses between Two STATE Events */
+typedef struct _Ifx_GTM_DPLL_MLS2_Bits
+{
+ Ifx_Strict_32Bit MLS2:18; /**< \brief [17:0] Counter for number of SUB_INC2 pulses (rw) */
+ Ifx_Strict_32Bit reserved_18:14; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_MLS2_Bits;
+
+/** \brief DPLL Missing Pulses to be Added/Subtracted Directly to SUB_INC1 and
+ * INC_CNT1 Once */
+typedef struct _Ifx_GTM_DPLL_MPVAL1_Bits
+{
+ Ifx_Strict_32Bit MPVAL1:16; /**< \brief [15:0] Missing pulses for direct correction of SUB_INC1 pulses by the CPU (sint16) (rw) */
+ Ifx_Strict_32Bit SIX1:8; /**< \brief [23:16] sign extension for MPVAL1 (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_MPVAL1_Bits;
+
+/** \brief DPLL Missing Pulses to be Added/Subtracted Directly to SUB_INC2 and
+ * INC_CNT2 Once */
+typedef struct _Ifx_GTM_DPLL_MPVAL2_Bits
+{
+ Ifx_Strict_32Bit MPVAL2:16; /**< \brief [15:0] missing pulses for direct correction of SUB_INC2 pulses by the CPU (sint16) (rw) */
+ Ifx_Strict_32Bit SIX2:8; /**< \brief [23:16] sign extension for MPVAL2 (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_MPVAL2_Bits;
+
+/** \brief DPLL Calculated Number Of TRIGGER/STATE Increments To ACTION */
+typedef struct _Ifx_GTM_DPLL_NA_Bits
+{
+ Ifx_Strict_32Bit DB:10; /**< \brief [9:0] Number of events to Action_i (fractional part) (rw) */
+ Ifx_Strict_32Bit DW:10; /**< \brief [19:10] Number of events to Action_i (integer part) (w) */
+ Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_NA_Bits;
+
+/** \brief DPLL Number of Pulses of Current Increment in Emergency Mode */
+typedef struct _Ifx_GTM_DPLL_NMB_S_Bits
+{
+ Ifx_Strict_32Bit NMB_S:20; /**< \brief [19:0] Number of pulses for STATE (rw) */
+ Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_NMB_S_Bits;
+
+/** \brief DPLL Target Number of Pulses to be sent in emergency mode Register */
+typedef struct _Ifx_GTM_DPLL_NMB_S_TAR_Bits
+{
+ Ifx_Strict_32Bit NMB_S_TAR:20; /**< \brief [19:0] Target Number of pulses for STATE (rw) */
+ Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_NMB_S_TAR_Bits;
+
+/** \brief DPLL Target Number of Pulses to be sent in emergency mode Register */
+typedef struct _Ifx_GTM_DPLL_NMB_S_TAR_OLD_Bits
+{
+ Ifx_Strict_32Bit NMB_S_TAR_OLD:20; /**< \brief [19:0] Target Number of pulses for STATE (rw) */
+ Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_NMB_S_TAR_OLD_Bits;
+
+/** \brief DPLL Number of Pulses of Current Increment in Normal Mode */
+typedef struct _Ifx_GTM_DPLL_NMB_T_Bits
+{
+ Ifx_Strict_32Bit NMB_T:16; /**< \brief [15:0] Number of pulses for TRIGGER (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_NMB_T_Bits;
+
+/** \brief DPLL Target Number of Pulses to be sent in normal mode Register */
+typedef struct _Ifx_GTM_DPLL_NMB_T_TAR_Bits
+{
+ Ifx_Strict_32Bit NMB_T_TAR:16; /**< \brief [15:0] Target Number of pulses for TRIGGER (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_NMB_T_TAR_Bits;
+
+/** \brief DPLL Target Number of Pulses to be sent in normal mode Register */
+typedef struct _Ifx_GTM_DPLL_NMB_T_TAR_OLD_Bits
+{
+ Ifx_Strict_32Bit NMB_T_TAR_OLD:16; /**< \brief [15:0] Target Number of pulses for TRIGGER (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_NMB_T_TAR_OLD_Bits;
+
+/** \brief DPLL Number of Active TRIGGER Events to Interrupt */
+typedef struct _Ifx_GTM_DPLL_NTI_CNT_Bits
+{
+ Ifx_Strict_32Bit NTI_CNT:10; /**< \brief [9:0] Number of TRIGGERs to interrupt (rw) */
+ Ifx_Strict_32Bit reserved_10:22; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_NTI_CNT_Bits;
+
+/** \brief DPLL Number of Recent STATE Events Used for Calculations */
+typedef struct _Ifx_GTM_DPLL_NUSC_Bits
+{
+ Ifx_Strict_32Bit NUSE:6; /**< \brief [5:0] Number of recent STATE events used for SUB_INCx calculations modulo 2*(SNUmax+1) (rw) */
+ Ifx_Strict_32Bit FSS:1; /**< \brief [6:6] this value is to be set, when NUSE is set to FULL_SCALE (rw) */
+ Ifx_Strict_32Bit SYN_S:6; /**< \brief [12:7] Number of real and virtual events to be considered for the current increment (rw) */
+ Ifx_Strict_32Bit SYN_S_OLD:6; /**< \brief [18:13] Number of real and virtual events to be considered for the last increment (rw) */
+ Ifx_Strict_32Bit VSN:6; /**< \brief [24:19] Virtual STATE number (rw) */
+ Ifx_Strict_32Bit reserved_25:4; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit WNUS:1; /**< \brief [29:29] Write control bit for NUSE; read as zero (w) */
+ Ifx_Strict_32Bit WSYN:1; /**< \brief [30:30] Write control bit for SYN_S and SYN_S_OLD; read as zero (w) */
+ Ifx_Strict_32Bit WVSN:1; /**< \brief [31:31] Write control bit for VSN; read as zero (w) */
+} Ifx_GTM_DPLL_NUSC_Bits;
+
+/** \brief DPLL Number of Recent TRIGGER Events Used for Calculations */
+typedef struct _Ifx_GTM_DPLL_NUTC_Bits
+{
+ Ifx_Strict_32Bit NUTE:10; /**< \brief [9:0] Number of recent TRIGGER events used for SUB_INC1 and action calculations modulo 2*(TNUmax+1) (rw) */
+ Ifx_Strict_32Bit FST:1; /**< \brief [10:10] this value is to be set, when NUTE is set to FULL_SCALE (rw) */
+ Ifx_Strict_32Bit reserved_11:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SYN_T:3; /**< \brief [15:13] Number of real and virtual events to be considered for the current increment (rw) */
+ Ifx_Strict_32Bit SYN_T_OLD:3; /**< \brief [18:16] Number of real and virtual events to be considered for the last increment (rw) */
+ Ifx_Strict_32Bit VTN:6; /**< \brief [24:19] Virtual TRIGGER number (rw) */
+ Ifx_Strict_32Bit reserved_25:4; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit WNUT:1; /**< \brief [29:29] Write control bit for NUTE and FST (w) */
+ Ifx_Strict_32Bit WSYN:1; /**< \brief [30:30] Write control bit for SYN_T and SYN_T_OLD (w) */
+ Ifx_Strict_32Bit WVTN:1; /**< \brief [31:31] Write control bit for VTN (w) */
+} Ifx_GTM_DPLL_NUTC_Bits;
+
+/** \brief DPLL Offset And Switch Old/New Address Register */
+typedef struct _Ifx_GTM_DPLL_OSW_Bits
+{
+ Ifx_Strict_32Bit SWON_S:1; /**< \brief [0:0] Switch of new STATE (r) */
+ Ifx_Strict_32Bit SWON_T:1; /**< \brief [1:1] Switch of new TRIGGER (r) */
+ Ifx_Strict_32Bit reserved_2:6; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit OSS:2; /**< \brief [9:8] Offset size of RAM region 2 (rw) */
+ Ifx_Strict_32Bit reserved_10:22; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_OSW_Bits;
+
+/** \brief DPLL Projected TRIGGER Increment Sum Relations for Action_i */
+typedef struct _Ifx_GTM_DPLL_PDT_T_Bits
+{
+ Ifx_Strict_32Bit DB:14; /**< \brief [13:0] Fractional part of relation between TRIGGER or STATE increments (rw) */
+ Ifx_Strict_32Bit DW:10; /**< \brief [23:14] Integer part of relation between TRIGGER or STATE increments (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_PDT_T_Bits;
+
+/** \brief DPLL ACTION Position/Value Action Request Register */
+typedef struct _Ifx_GTM_DPLL_PSA_Bits
+{
+ Ifx_Strict_32Bit PSA:24; /**< \brief [23:0] Position information of a desired action (i=0...23) (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_PSA_Bits;
+
+/** \brief DPLL Calculated Position Value Register */
+typedef struct _Ifx_GTM_DPLL_PSAC_Bits
+{
+ Ifx_Strict_32Bit PSAC:24; /**< \brief [23:0] calculated position value for the start of ACTION_i in normal or emergency mode according to equations DPLL-17 or DPLL-20 respectively (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_PSAC_Bits;
+
+/** \brief DPLL Accurate Calculated Position Stamp of Last STATE Input */
+typedef struct _Ifx_GTM_DPLL_PSSC_Bits
+{
+ Ifx_Strict_32Bit PSSC:24; /**< \brief [23:0] Calculated position stamp for the last STATE input (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_PSSC_Bits;
+
+/** \brief DPLL Measured Position Stamp of Last STATE Input */
+typedef struct _Ifx_GTM_DPLL_PSSM_0_Bits
+{
+ Ifx_Strict_32Bit PSSM:24; /**< \brief [23:0] Position stamp of STATE, measured (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_PSSM_0_Bits;
+
+/** \brief DPLL Measured Position Stamp of Last STATE Input */
+typedef struct _Ifx_GTM_DPLL_PSSM_1_Bits
+{
+ Ifx_Strict_32Bit PSSM:24; /**< \brief [23:0] Position stamp of STATE, measured (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_PSSM_1_Bits;
+
+/** \brief DPLL Actual Calculated Position Stamp of Last TRIGGER Input */
+typedef struct _Ifx_GTM_DPLL_PSTC_Bits
+{
+ Ifx_Strict_32Bit PSTC:24; /**< \brief [23:0] Calculated position stamp of last TRIGGER input (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_PSTC_Bits;
+
+/** \brief DPLL Measured Position Stamp of Last TRIGGER Input */
+typedef struct _Ifx_GTM_DPLL_PSTM_0_Bits
+{
+ Ifx_Strict_32Bit PSTM:24; /**< \brief [23:0] Position stamp of TRIGGER, measured (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_PSTM_0_Bits;
+
+/** \brief DPLL Measured Position Stamp of Last TRIGGER Input */
+typedef struct _Ifx_GTM_DPLL_PSTM_1_Bits
+{
+ Ifx_Strict_32Bit PSTM:24; /**< \brief [23:0] Position stamp of TRIGGER, measured (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_PSTM_1_Bits;
+
+/** \brief DPLL Plausibility Value of Next Active TRIGGER Slope */
+typedef struct _Ifx_GTM_DPLL_PVT_Bits
+{
+ Ifx_Strict_32Bit PVT:24; /**< \brief [23:0] Plausibility value of next valid TRIGGER slope (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_PVT_Bits;
+
+/** \brief DPLL RAM Initatlisation Register */
+typedef struct _Ifx_GTM_DPLL_RAM_INI_Bits
+{
+ Ifx_Strict_32Bit INIT_1A:1; /**< \brief [0:0] RAM region 1A initialization in progress (r) */
+ Ifx_Strict_32Bit INIT_1B:1; /**< \brief [1:1] RAM region 1B initialization in progress (r) */
+ Ifx_Strict_32Bit INIT_2:1; /**< \brief [2:2] RAM region 2 initialization in progress (r) */
+ Ifx_Strict_32Bit reserved_3:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit INIT_RAM:1; /**< \brief [4:4] RAM regions 1A, 1B and 2 are to be initialized (w) */
+ Ifx_Strict_32Bit reserved_5:27; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_RAM_INI_Bits;
+
+/** \brief DPLL Reciprocal Value of Expected Increment Duration STATE */
+typedef struct _Ifx_GTM_DPLL_RCDT_SX_Bits
+{
+ Ifx_Strict_32Bit RCDT_SX:24; /**< \brief [23:0] Reciprocal value of expected increment duration *2 while only the lower 24 bits are used (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_RCDT_SX_Bits;
+
+/** \brief DPLL Reciprocal Value of the Expected Nominal Increment Duration
+ * STATE */
+typedef struct _Ifx_GTM_DPLL_RCDT_SX_NOM_Bits
+{
+ Ifx_Strict_32Bit RCDT_SX_NOM:24; /**< \brief [23:0] Reciprocal value of nominal increment duration *2 while only the lower 24 bits are used (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_RCDT_SX_NOM_Bits;
+
+/** \brief DPLL Reciprocal Value of Expected Increment Duration TRIGGER */
+typedef struct _Ifx_GTM_DPLL_RCDT_TX_Bits
+{
+ Ifx_Strict_32Bit RCDT_TX:24; /**< \brief [23:0] Reciprocal value of expected increment duration *2 while only the lower 24 bits are used (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_RCDT_TX_Bits;
+
+/** \brief DPLL Reciprocal Value of the Expected Nominal Increment Duration
+ * TRIGGER */
+typedef struct _Ifx_GTM_DPLL_RCDT_TX_NOM_Bits
+{
+ Ifx_Strict_32Bit RCDT_TX_NOM:24; /**< \brief [23:0] Reciprocal value of nominal increment duration *2 while only the lower 24 bits are used (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_RCDT_TX_NOM_Bits;
+
+/** \brief DPLL Actual Reciprocal Value of STATE */
+typedef struct _Ifx_GTM_DPLL_RDT_S_ACT_Bits
+{
+ Ifx_Strict_32Bit RDT_S_ACT:24; /**< \brief [23:0] Reciprocal value of last STATE increment *2 (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_RDT_S_ACT_Bits;
+
+/** \brief DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+typedef struct _Ifx_GTM_DPLL_RDT_S_Bits
+{
+ Ifx_Strict_32Bit RDT_S:24; /**< \brief [23:0] Reciprocal difference time of TRIGGER (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_RDT_S_Bits;
+
+/** \brief DPLL Actual Reciprocal Value of TRIGGER */
+typedef struct _Ifx_GTM_DPLL_RDT_T_ACT_Bits
+{
+ Ifx_Strict_32Bit RDT_T_ACT:24; /**< \brief [23:0] Reciprocal value of last TRIGGER increment *2 (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_RDT_T_ACT_Bits;
+
+/** \brief DPLL STATE Locking Range */
+typedef struct _Ifx_GTM_DPLL_SLR_Bits
+{
+ Ifx_Strict_32Bit SLR:8; /**< \brief [7:0] Value is to be multiplied with the last nominal STATE duration in order to get the range for the next STATE event without setting SOR in the DPLL_STATUS register (rw) */
+ Ifx_Strict_32Bit reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_SLR_Bits;
+
+/** \brief DPLL Status Register */
+typedef struct _Ifx_GTM_DPLL_STATUS_Bits
+{
+ Ifx_Strict_32Bit reserved_0:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit CSO:1; /**< \brief [1:1] Calculated STATE duration overflow (rwh) */
+ Ifx_Strict_32Bit reserved_2:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit CTO:1; /**< \brief [3:3] Calculated TRIGGER duration overflow (rwh) */
+ Ifx_Strict_32Bit CRO:1; /**< \brief [4:4] Calculated Reciprocal value overflow (rwh) */
+ Ifx_Strict_32Bit RCS:1; /**< \brief [5:5] RCS (rh) */
+ Ifx_Strict_32Bit RCT:1; /**< \brief [6:6] RCT (rwh) */
+ Ifx_Strict_32Bit PSE:1; /**< \brief [7:7] Prediction space configuration error (rwh) */
+ Ifx_Strict_32Bit SOR:1; /**< \brief [8:8] STATE out of range (rh) */
+ Ifx_Strict_32Bit MS:1; /**< \brief [9:9] Missing STATE detected according to TOV_S (rh) */
+ Ifx_Strict_32Bit TOR:1; /**< \brief [10:10] TRIGGER out of range (rh) */
+ Ifx_Strict_32Bit MT:1; /**< \brief [11:11] Missing TRIGGER detected according to TOV (rwh) */
+ Ifx_Strict_32Bit RAM2_ERR:1; /**< \brief [12:12] DPLL internal access to not configured RAM2 (rwh) */
+ Ifx_Strict_32Bit reserved_13:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit LOW_RES:1; /**< \brief [15:15] Low resolution of TBU_TS0 is used for DPLL input (rwh) */
+ Ifx_Strict_32Bit CSVS:1; /**< \brief [16:16] Current signal value STATE (rh) */
+ Ifx_Strict_32Bit CSVT:1; /**< \brief [17:17] Current signal value TRIGGER (rh) */
+ Ifx_Strict_32Bit CAIP2:1; /**< \brief [18:18] Calculation of actions 12 to 23 in progress (2nd part) (rh) */
+ Ifx_Strict_32Bit CAIP1:1; /**< \brief [19:19] Calculation of actions 0 to 11 in progress (1st part) (rh) */
+ Ifx_Strict_32Bit ISN:1; /**< \brief [20:20] Number of STATE is not plausible (rh) */
+ Ifx_Strict_32Bit ITN:1; /**< \brief [21:21] Increment number of TRIGGER is not plausible (rh) */
+ Ifx_Strict_32Bit BWD2:1; /**< \brief [22:22] Backwards drive of SUB_INC2 (rh) */
+ Ifx_Strict_32Bit BWD1:1; /**< \brief [23:23] Backwards drive of SUB_INC1 (rh) */
+ Ifx_Strict_32Bit reserved_24:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit LOCK2:1; /**< \brief [25:25] DPLL Lock status concerning SUB_INC2 (rh) */
+ Ifx_Strict_32Bit SYS:1; /**< \brief [26:26] Synchronization condition of STATE fixed (rh) */
+ Ifx_Strict_32Bit SYT:1; /**< \brief [27:27] Synchronization condition of TRIGGER fixed (rh) */
+ Ifx_Strict_32Bit FSD:1; /**< \brief [28:28] STATE detected (rh) */
+ Ifx_Strict_32Bit FTD:1; /**< \brief [29:29] First TRIGGER detected (rh) */
+ Ifx_Strict_32Bit LOCK1:1; /**< \brief [30:30] DPLL Lock status concerning SUB_INC1 (rh) */
+ Ifx_Strict_32Bit ERR:1; /**< \brief [31:31] Error during configuration or operation resulting in unexpected values (rh) */
+} Ifx_GTM_DPLL_STATUS_Bits;
+
+/** \brief DPLL TBU_TS0 Value at last STATE Event */
+typedef struct _Ifx_GTM_DPLL_TBU_TS0_S_Bits
+{
+ Ifx_Strict_32Bit TBU_TS0_S:24; /**< \brief [23:0] value of TBU_TS0 at the last STATE event (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_TBU_TS0_S_Bits;
+
+/** \brief DPLL TBU_TS0 Value at last TRIGGER Event */
+typedef struct _Ifx_GTM_DPLL_TBU_TS0_T_Bits
+{
+ Ifx_Strict_32Bit TBU_TS0_T:24; /**< \brief [23:0] value of TBU_TS0 at the last TRIGGER event (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_TBU_TS0_T_Bits;
+
+/** \brief DPLL TRIGGER Hold Time Max Value */
+typedef struct _Ifx_GTM_DPLL_THMA_Bits
+{
+ Ifx_Strict_32Bit THMA:16; /**< \brief [15:0] Maximal time between active and inactive TRIGGER slope (uint16) (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_THMA_Bits;
+
+/** \brief DPLL TRIGGER hold time min value */
+typedef struct _Ifx_GTM_DPLL_THMI_Bits
+{
+ Ifx_Strict_32Bit THMI:16; /**< \brief [15:0] Minimal time between active and inactive TRIGGER slope (uint16) (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_THMI_Bits;
+
+/** \brief DPLL Measured Last Pulse Time from Valid to Invalid TRIGGER Slope */
+typedef struct _Ifx_GTM_DPLL_THVAL_Bits
+{
+ Ifx_Strict_32Bit THVAL:16; /**< \brief [15:0] Measured time from the last valid slope to the next inactive TRIGGER slope in time stamp clock counts: this does mean the clock selected for the TBU_CH0_BASE (uint16) (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_THVAL_Bits;
+
+/** \brief DPLL TRIGGER locking range */
+typedef struct _Ifx_GTM_DPLL_TLR_Bits
+{
+ Ifx_Strict_32Bit TLR:8; /**< \brief [7:0] Value is to be multiplied with the last nominal TRIGGER duration in order to get the range for the next TRIGGER event without setting TOR in the DPLL_STATUS register (rw) */
+ Ifx_Strict_32Bit reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_TLR_Bits;
+
+/** \brief DPLL Time Out Value of active TRIGGER Slope */
+typedef struct _Ifx_GTM_DPLL_TOV_Bits
+{
+ Ifx_Strict_32Bit DB:10; /**< \brief [9:0] Decision value (fractional part) for missing TRIGGER interrupt (rw) */
+ Ifx_Strict_32Bit DW:6; /**< \brief [15:10] Decision value (integer part) for missing TRIGGER interrupt (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_TOV_Bits;
+
+/** \brief DPLL Time Out Value of active STATE Slope */
+typedef struct _Ifx_GTM_DPLL_TOV_S_Bits
+{
+ Ifx_Strict_32Bit DB:10; /**< \brief [9:0] Decision value (fractional part) for missing STATE interrupt (rw) */
+ Ifx_Strict_32Bit DW:6; /**< \brief [15:10] Decision value (integer part) for missing STATE interrupt (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_TOV_S_Bits;
+
+/** \brief DPLL Actual Signal STATE Time Stamp Register */
+typedef struct _Ifx_GTM_DPLL_TS_S_0_Bits
+{
+ Ifx_Strict_32Bit STATE_TS:24; /**< \brief [23:0] Time stamp value of the last valid STATE input (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_TS_S_0_Bits;
+
+/** \brief DPLL Actual Signal STATE Time Stamp Register */
+typedef struct _Ifx_GTM_DPLL_TS_S_1_Bits
+{
+ Ifx_Strict_32Bit STATE_TS:24; /**< \brief [23:0] Time stamp value of the last valid STATE input (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_TS_S_1_Bits;
+
+/** \brief DPLL Actual Signal TRIGGER Time Stamp Register */
+typedef struct _Ifx_GTM_DPLL_TS_T_0_Bits
+{
+ Ifx_Strict_32Bit TRIGGER_TS:24; /**< \brief [23:0] Time stamp value of the last valid TRIGGER input (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_TS_T_0_Bits;
+
+/** \brief DPLL Actual Signal TRIGGER Time Stamp Register */
+typedef struct _Ifx_GTM_DPLL_TS_T_1_Bits
+{
+ Ifx_Strict_32Bit TRIGGER_TS:24; /**< \brief [23:0] Time stamp value of the last valid TRIGGER input (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_TS_T_1_Bits;
+
+/** \brief DPLL Calculate Time Stamp Register */
+typedef struct _Ifx_GTM_DPLL_TSAC_Bits
+{
+ Ifx_Strict_32Bit TSAC:24; /**< \brief [23:0] calculated time stamp for ACTION_i (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_TSAC_Bits;
+
+/** \brief DPLL Time Stamp Field of STATE Events */
+typedef struct _Ifx_GTM_DPLL_TSF_S_Bits
+{
+ Ifx_Strict_32Bit TSF_S:24; /**< \brief [23:0] Time stamp field of STATE (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_DPLL_TSF_S_Bits;
+
+/** \brief Data Exchange Input Control Register */
+typedef struct _Ifx_GTM_DXINCON_Bits
+{
+ Ifx_Strict_32Bit IN00:1; /**< \brief [0:0] Input 0x Control (rw) */
+ Ifx_Strict_32Bit IN01:1; /**< \brief [1:1] Input 0x Control (rw) */
+ Ifx_Strict_32Bit IN02:1; /**< \brief [2:2] Input 0x Control (rw) */
+ Ifx_Strict_32Bit reserved_3:5; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit IN10:1; /**< \brief [8:8] Input 1x Control (rw) */
+ Ifx_Strict_32Bit IN11:1; /**< \brief [9:9] Input 1x Control (rw) */
+ Ifx_Strict_32Bit IN12:1; /**< \brief [10:10] Input 1x Control (rw) */
+ Ifx_Strict_32Bit reserved_11:5; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit DSS00:1; /**< \brief [16:16] Data Source Select 0x Control (rw) */
+ Ifx_Strict_32Bit DSS01:1; /**< \brief [17:17] Data Source Select 0x Control (rw) */
+ Ifx_Strict_32Bit DSS02:1; /**< \brief [18:18] Data Source Select 0x Control (rw) */
+ Ifx_Strict_32Bit reserved_19:5; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit DSS10:1; /**< \brief [24:24] Data Source Select 1x Control (rw) */
+ Ifx_Strict_32Bit DSS11:1; /**< \brief [25:25] Data Source Select 1x Control (rw) */
+ Ifx_Strict_32Bit DSS12:1; /**< \brief [26:26] Data Source Select 1x Control (rw) */
+ Ifx_Strict_32Bit reserved_27:5; /**< \brief \internal Reserved */
+} Ifx_GTM_DXINCON_Bits;
+
+/** \brief Data Exchange Output Control Register */
+typedef struct _Ifx_GTM_DXOUTCON_Bits
+{
+ Ifx_Strict_32Bit OUT00:1; /**< \brief [0:0] Output 0x Control (rw) */
+ Ifx_Strict_32Bit OUT01:1; /**< \brief [1:1] Output 0x Control (rw) */
+ Ifx_Strict_32Bit OUT02:1; /**< \brief [2:2] Output 0x Control (rw) */
+ Ifx_Strict_32Bit reserved_3:5; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit OUT10:1; /**< \brief [8:8] Output 1x Control (rw) */
+ Ifx_Strict_32Bit OUT11:1; /**< \brief [9:9] Output 1x Control (rw) */
+ Ifx_Strict_32Bit OUT12:1; /**< \brief [10:10] Output 1x Control (rw) */
+ Ifx_Strict_32Bit reserved_11:21; /**< \brief \internal Reserved */
+} Ifx_GTM_DXOUTCON_Bits;
+
+/** \brief GTM Error Interrupt Enable Register */
+typedef struct _Ifx_GTM_EIRQ_EN_Bits
+{
+ Ifx_Strict_32Bit AEI_TO_XPT_EIRQ_EN:1; /**< \brief [0:0] AEI_TO_XPT_EIRQ error interrupt enable (rw) */
+ Ifx_Strict_32Bit AEI_USP_ADDR_EIRQ_EN:1; /**< \brief [1:1] AEI_USP_ADDR_EIRQ error interrupt enable (rw) */
+ Ifx_Strict_32Bit AEI_IM_ADDR_EIRQ_EN:1; /**< \brief [2:2] AEI_IM_ADDR_EIRQ error interrupt enable (rw) */
+ Ifx_Strict_32Bit AEI_USP_BE_EIRQ_EN:1; /**< \brief [3:3] AEI_USP_BE_EIRQ error interrupt enable (rw) */
+ Ifx_Strict_32Bit reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_GTM_EIRQ_EN_Bits;
+
+/** \brief F2A0 Stream Activation Register */
+typedef struct _Ifx_GTM_F2A_ENABLE_Bits
+{
+ Ifx_Strict_32Bit STR0_EN:2; /**< \brief [1:0] Enable/disable stream 0 (rw) */
+ Ifx_Strict_32Bit STR1_EN:2; /**< \brief [3:2] Enable/disable stream 1 (rw) */
+ Ifx_Strict_32Bit STR2_EN:2; /**< \brief [5:4] Enable/disable stream 2 (rw) */
+ Ifx_Strict_32Bit STR3_EN:2; /**< \brief [7:6] Enable/disable stream 3 (rw) */
+ Ifx_Strict_32Bit STR4_EN:2; /**< \brief [9:8] Enable/disable stream 4 (rw) */
+ Ifx_Strict_32Bit STR5_EN:2; /**< \brief [11:10] Enable/disable stream 5 (rw) */
+ Ifx_Strict_32Bit STR6_EN:2; /**< \brief [13:12] Enable/disable stream 6 (rw) */
+ Ifx_Strict_32Bit STR7_EN:2; /**< \brief [15:14] Enable/disable stream 7 (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_F2A_ENABLE_Bits;
+
+/** \brief F2A Read Channel Address Register */
+typedef struct _Ifx_GTM_F2A_RD_CH_ARU_RD_FIFO_Bits
+{
+ Ifx_Strict_32Bit ADDR:9; /**< \brief [8:0] ARU Read address (rw) */
+ Ifx_Strict_32Bit reserved_9:23; /**< \brief \internal Reserved */
+} Ifx_GTM_F2A_RD_CH_ARU_RD_FIFO_Bits;
+
+/** \brief F2A Stream Configuration Register */
+typedef struct _Ifx_GTM_F2A_STR_CH_STR_CFG_Bits
+{
+ Ifx_Strict_32Bit reserved_0:16; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit TMODE:2; /**< \brief [17:16] Transfer mode for 53 bit ARU data from/to FIFO (rw) */
+ Ifx_Strict_32Bit DIR:1; /**< \brief [18:18] Data transfer direction (rw) */
+ Ifx_Strict_32Bit reserved_19:13; /**< \brief \internal Reserved */
+} Ifx_GTM_F2A_STR_CH_STR_CFG_Bits;
+
+/** \brief FIFO0 Channel Control Register */
+typedef struct _Ifx_GTM_FIFO_CH_CTRL_Bits
+{
+ Ifx_Strict_32Bit RBM:1; /**< \brief [0:0] Ring buffer mode enable (rw) */
+ Ifx_Strict_32Bit RAP:1; /**< \brief [1:1] RAM access priority (rw) */
+ Ifx_Strict_32Bit FLUSH:1; /**< \brief [2:2] FIFO Flush control (w) */
+ Ifx_Strict_32Bit WULOCK:1; /**< \brief [3:3] RAM write unlock Enable/disable direct RAM write access to the memory mapped FIFO region (rw) */
+ Ifx_Strict_32Bit reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_GTM_FIFO_CH_CTRL_Bits;
+
+/** \brief FIFO0 Channel Error Interrupt Enable Register */
+typedef struct _Ifx_GTM_FIFO_CH_EIRQ_EN_Bits
+{
+ Ifx_Strict_32Bit FIFO_EMPTY_EIRQ_EN:1; /**< \brief [0:0] Error interrupt enable (rw) */
+ Ifx_Strict_32Bit FIFO_FULL_EIRQ_EN:1; /**< \brief [1:1] Interrupt enable (rw) */
+ Ifx_Strict_32Bit FIFO_LWM_EIRQ_EN:1; /**< \brief [2:2] Interrupt enable (rw) */
+ Ifx_Strict_32Bit FIFO_UWM_EIRQ_EN:1; /**< \brief [3:3] Interrupt enable (rw) */
+ Ifx_Strict_32Bit Reserved:28; /**< \brief [31:4] reserved (r) */
+} Ifx_GTM_FIFO_CH_EIRQ_EN_Bits;
+
+/** \brief FIFO0 Channel End Address Register */
+typedef struct _Ifx_GTM_FIFO_CH_END_ADDR_Bits
+{
+ Ifx_Strict_32Bit ADDR:10; /**< \brief [9:0] End address for FIFOi channel x, (x:0...7) (rw) */
+ Ifx_Strict_32Bit reserved_10:22; /**< \brief \internal Reserved */
+} Ifx_GTM_FIFO_CH_END_ADDR_Bits;
+
+/** \brief FIFO0 Channel Fill Level Register */
+typedef struct _Ifx_GTM_FIFO_CH_FILL_LEVEL_Bits
+{
+ Ifx_Strict_32Bit LEVEL:11; /**< \brief [10:0] Fill level of the current FIFO (r) */
+ Ifx_Strict_32Bit reserved_11:21; /**< \brief \internal Reserved */
+} Ifx_GTM_FIFO_CH_FILL_LEVEL_Bits;
+
+/** \brief FIFO0 Channel Interrupt Enable Register */
+typedef struct _Ifx_GTM_FIFO_CH_IRQ_EN_Bits
+{
+ Ifx_Strict_32Bit FIFO_EMPTY_IRQ_EN:1; /**< \brief [0:0] interrupt enable (rw) */
+ Ifx_Strict_32Bit FIFO_FULL_IRQ_EN:1; /**< \brief [1:1] interrupt enable (rw) */
+ Ifx_Strict_32Bit FIFO_LWM_IRQ_EN:1; /**< \brief [2:2] interrupt enable (rw) */
+ Ifx_Strict_32Bit FIFO_UWM_IRQ_EN:1; /**< \brief [3:3] interrupt enable (rw) */
+ Ifx_Strict_32Bit reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_GTM_FIFO_CH_IRQ_EN_Bits;
+
+/** \brief FIFO0 Channel Force Interrupt By Software Register */
+typedef struct _Ifx_GTM_FIFO_CH_IRQ_FORCINT_Bits
+{
+ Ifx_Strict_32Bit TRG_FIFO_EMPTY:1; /**< \brief [0:0] Force interrupt of FIFO empty status (w) */
+ Ifx_Strict_32Bit TRG_FIFO_FULL:1; /**< \brief [1:1] Force interrupt of FIFO full status (w) */
+ Ifx_Strict_32Bit TRG_FIFO_LWM:1; /**< \brief [2:2] Force interrupt of lower watermark (w) */
+ Ifx_Strict_32Bit TRG_FIFO_UWM:1; /**< \brief [3:3] Force interrupt of upper watermark (w) */
+ Ifx_Strict_32Bit reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_GTM_FIFO_CH_IRQ_FORCINT_Bits;
+
+/** \brief FIFO0 Channel IRQ Mode Control Register */
+typedef struct _Ifx_GTM_FIFO_CH_IRQ_MODE_Bits
+{
+ Ifx_Strict_32Bit IRQ_MODE:2; /**< \brief [1:0] IRQ mode selection (rw) */
+ Ifx_Strict_32Bit DMA_HYSTERESIS:1; /**< \brief [2:2] Enable DMA hysteresis mode (rw) */
+ Ifx_Strict_32Bit DMA_HYST_DIR:1; /**< \brief [3:3] DMA direction in hysteresis mode (rw) */
+ Ifx_Strict_32Bit reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_GTM_FIFO_CH_IRQ_MODE_Bits;
+
+/** \brief FIFO0 Channel Interrupt Notification Register */
+typedef struct _Ifx_GTM_FIFO_CH_IRQ_NOTIFY_Bits
+{
+ Ifx_Strict_32Bit FIFO_EMPTY:1; /**< \brief [0:0] FIFO is empty (rwh) */
+ Ifx_Strict_32Bit FIFO_FULL:1; /**< \brief [1:1] FIFO is full (rwh) */
+ Ifx_Strict_32Bit FIFO_LWM:1; /**< \brief [2:2] FIFO Lower watermark was under-run (rwh) */
+ Ifx_Strict_32Bit FIFO_UWM:1; /**< \brief [3:3] FIFO Upper watermark was over-run (rwh) */
+ Ifx_Strict_32Bit reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_GTM_FIFO_CH_IRQ_NOTIFY_Bits;
+
+/** \brief FIFO0 Channel Lower Watermark Register */
+typedef struct _Ifx_GTM_FIFO_CH_LOWER_WM_Bits
+{
+ Ifx_Strict_32Bit ADDR:10; /**< \brief [9:0] Lower watermark address (rw) */
+ Ifx_Strict_32Bit reserved_10:22; /**< \brief \internal Reserved */
+} Ifx_GTM_FIFO_CH_LOWER_WM_Bits;
+
+/** \brief FIFO0 Channel Read Pointer Register */
+typedef struct _Ifx_GTM_FIFO_CH_RD_PTR_Bits
+{
+ Ifx_Strict_32Bit ADDR:10; /**< \brief [9:0] Position of the read pointer (r) */
+ Ifx_Strict_32Bit reserved_10:22; /**< \brief \internal Reserved */
+} Ifx_GTM_FIFO_CH_RD_PTR_Bits;
+
+/** \brief FIFO0 Channel Start Address Register */
+typedef struct _Ifx_GTM_FIFO_CH_START_ADDR_Bits
+{
+ Ifx_Strict_32Bit ADDR:10; /**< \brief [9:0] Start address for FIFOi channel x, (x07) (rw) */
+ Ifx_Strict_32Bit reserved_10:22; /**< \brief \internal Reserved */
+} Ifx_GTM_FIFO_CH_START_ADDR_Bits;
+
+/** \brief FIFO0 Channel Status Register */
+typedef struct _Ifx_GTM_FIFO_CH_STATUS_Bits
+{
+ Ifx_Strict_32Bit EMPTY:1; /**< \brief [0:0] FIFO is empty (r) */
+ Ifx_Strict_32Bit FULL:1; /**< \brief [1:1] FIFO is full (r) */
+ Ifx_Strict_32Bit LOW_WM:1; /**< \brief [2:2] Lower watermark reached (r) */
+ Ifx_Strict_32Bit UP_WM:1; /**< \brief [3:3] Upper watermark reached (r) */
+ Ifx_Strict_32Bit reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_GTM_FIFO_CH_STATUS_Bits;
+
+/** \brief FIFO0 Channel Upper Watermark Register */
+typedef struct _Ifx_GTM_FIFO_CH_UPPER_WM_Bits
+{
+ Ifx_Strict_32Bit ADDR:10; /**< \brief [9:0] Upper watermark address (rw) */
+ Ifx_Strict_32Bit reserved_10:22; /**< \brief \internal Reserved */
+} Ifx_GTM_FIFO_CH_UPPER_WM_Bits;
+
+/** \brief FIFO0 Channel Write Pointer Register */
+typedef struct _Ifx_GTM_FIFO_CH_WR_PTR_Bits
+{
+ Ifx_Strict_32Bit ADDR:10; /**< \brief [9:0] Position of the write pointer (r) */
+ Ifx_Strict_32Bit reserved_10:22; /**< \brief \internal Reserved */
+} Ifx_GTM_FIFO_CH_WR_PTR_Bits;
+
+/** \brief GTM Infrastructure Interrupt Group */
+typedef struct _Ifx_GTM_ICM_IRQG_0_Bits
+{
+ Ifx_Strict_32Bit ARU_NEW_DATA0_IRQ:1; /**< \brief [0:0] ARU_NEW_DATA0 interrupt (rh) */
+ Ifx_Strict_32Bit ARU_NEW_DATA1_IRQ:1; /**< \brief [1:1] ARU_NEW_DATA1 interrupt (rh) */
+ Ifx_Strict_32Bit ARU_ACC_ACK_IRQ:1; /**< \brief [2:2] ARU_ACC_ACK interrupt (rh) */
+ Ifx_Strict_32Bit BRC_IRQ:1; /**< \brief [3:3] BRC shared submodule interrupt (rh) */
+ Ifx_Strict_32Bit AEI_IRQ:1; /**< \brief [4:4] AEI_IRQ interrupt (rh) */
+ Ifx_Strict_32Bit CMP_IRQ:1; /**< \brief [5:5] CMP shared submodule interrupt (rh) */
+ Ifx_Strict_32Bit SPE0_IRQ:1; /**< \brief [6:6] SPE0 shared submodule interrupt (rh) */
+ Ifx_Strict_32Bit SPE1_IRQ:1; /**< \brief [7:7] SPE1 shared submodule interrupt (rh) */
+ Ifx_Strict_32Bit reserved_8:8; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit PSM0_CH0_IRQ:1; /**< \brief [16:16] PSM0 shared submodule channel 0 interrupt (rh) */
+ Ifx_Strict_32Bit PSM0_CH1_IRQ:1; /**< \brief [17:17] PSM0 shared submodule channel 1 interrupt (rh) */
+ Ifx_Strict_32Bit PSM0_CH2_IRQ:1; /**< \brief [18:18] PSM0 shared submodule channel 2 interrupt (rh) */
+ Ifx_Strict_32Bit PSM0_CH3_IRQ:1; /**< \brief [19:19] PSM0 shared submodule channel 3 interrupt (rh) */
+ Ifx_Strict_32Bit PSM0_CH4_IRQ:1; /**< \brief [20:20] PSM0 shared submodule channel 4 interrupt (rh) */
+ Ifx_Strict_32Bit PSM0_CH5_IRQ:1; /**< \brief [21:21] PSM0 shared submodule channel 5 interrupt (rh) */
+ Ifx_Strict_32Bit PSM0_CH6_IRQ:1; /**< \brief [22:22] PSM0 shared submodule channel 6 interrupt (rh) */
+ Ifx_Strict_32Bit PSM0_CH7_IRQ:1; /**< \brief [23:23] PSM0 shared submodule channel 7 interrupt (rh) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_ICM_IRQG_0_Bits;
+
+/** \brief GTM DPLL Interrupt Group */
+typedef struct _Ifx_GTM_ICM_IRQG_1_Bits
+{
+ Ifx_Strict_32Bit DPLL_DCG_IRQ:1; /**< \brief [0:0] TRIGGER direction change detected. (rh) */
+ Ifx_Strict_32Bit DPLL_EDI_IRQ:1; /**< \brief [1:1] DPLL enable/disable interrupt (rh) */
+ Ifx_Strict_32Bit DPLL_TIN_IRQ:1; /**< \brief [2:2] TRIGGER minimum hold time (THMI) violation detected interrupt (rh) */
+ Ifx_Strict_32Bit DPLL_TAX_IRQ:1; /**< \brief [3:3] TRIGGER maximum hold time (THMA) violation detected interrupt (rh) */
+ Ifx_Strict_32Bit DPLL_SIS_IRQ:1; /**< \brief [4:4] STATE inactive slope detected interrupt. See bit 0. (rh) */
+ Ifx_Strict_32Bit DPLL_TIS_IRQ:1; /**< \brief [5:5] TRIGGER inactive slope detected interrupt. See bit 0. (rh) */
+ Ifx_Strict_32Bit DPLL_MSI_IRQ:1; /**< \brief [6:6] Missing STATE interrupt (rh) */
+ Ifx_Strict_32Bit DPLL_MTI_IRQ:1; /**< \brief [7:7] Missing TRIGGER interrupt (rh) */
+ Ifx_Strict_32Bit DPLL_SAS_IRQ:1; /**< \brief [8:8] STATE active slope detected (rh) */
+ Ifx_Strict_32Bit DPLL_TAS_IRQ:1; /**< \brief [9:9] TRIGGER active slope detected while NTI_CNT is zero (rh) */
+ Ifx_Strict_32Bit DPLL_PWI_IRQ:1; /**< \brief [10:10] Plausibility window (PVT) violation interrupt of TRIGGER (rh) */
+ Ifx_Strict_32Bit DPLL_W2I_IRQ:1; /**< \brief [11:11] Write access to RAM region 2 interrupt (rh) */
+ Ifx_Strict_32Bit DPLL_W1I_IRQ:1; /**< \brief [12:12] Write access to RAM region 1B or 1C interrupt (rh) */
+ Ifx_Strict_32Bit DPLL_GLI_IRQ:1; /**< \brief [13:13] Get of lock interrupt for SUB_INC1 (rh) */
+ Ifx_Strict_32Bit DPLL_LLI_IRQ:1; /**< \brief [14:14] Lost of lock interrupt for SUB_INC1 (rh) */
+ Ifx_Strict_32Bit DPLL_EI_IRQ:1; /**< \brief [15:15] Error interrupt See bit 0 (rh) */
+ Ifx_Strict_32Bit DPLL_GL2I_IRQ:1; /**< \brief [16:16] Get of lock interrupt for SUB_INC2 (rh) */
+ Ifx_Strict_32Bit DPLL_LL2I_IRQ:1; /**< \brief [17:17] Lost of lock interrupt for SUB_INC2 (rh) */
+ Ifx_Strict_32Bit DPLL_TE0_IRQ:1; /**< \brief [18:18] TRIGGER event interrupt 0 (rh) */
+ Ifx_Strict_32Bit DPLL_TE1_IRQ:1; /**< \brief [19:19] TRIGGER event interrupt 1 (rh) */
+ Ifx_Strict_32Bit DPLL_TE2_IRQ:1; /**< \brief [20:20] TRIGGER event interrupt 2 (rh) */
+ Ifx_Strict_32Bit DPLL_TE3_IRQ:1; /**< \brief [21:21] TRIGGER event interrupt 3 (rh) */
+ Ifx_Strict_32Bit DPLL_TE4_IRQ:1; /**< \brief [22:22] TRIGGER event interrupt 4 (rh) */
+ Ifx_Strict_32Bit DPLL_CDIT_IRQ:1; /**< \brief [23:23] DPLL calculated duration interrupt for trigger (rh) */
+ Ifx_Strict_32Bit DPLL_CDIS_IRQ:1; /**< \brief [24:24] DPLL calculated duration interrupt for state (rh) */
+ Ifx_Strict_32Bit DPLL_TORI_IRQ:1; /**< \brief [25:25] DPLL calculated duration interrupt for state (rh) */
+ Ifx_Strict_32Bit DPLL_SORI_IRQ:1; /**< \brief [26:26] DPLL calculated duration interrupt for state (rh) */
+ Ifx_Strict_32Bit reserved_27:5; /**< \brief \internal Reserved */
+} Ifx_GTM_ICM_IRQG_1_Bits;
+
+/** \brief TIM Interrupt Group 0 */
+typedef struct _Ifx_GTM_ICM_IRQG_2_Bits
+{
+ Ifx_Strict_32Bit TIM0_CH0_IRQ:1; /**< \brief [0:0] TIM0 shared interrupt channel 0 (rh) */
+ Ifx_Strict_32Bit TIM0_CH1_IRQ:1; /**< \brief [1:1] TIM0 shared interrupt channel 1 (rh) */
+ Ifx_Strict_32Bit TIM0_CH2_IRQ:1; /**< \brief [2:2] TIM0 shared interrupt channel 2 (rh) */
+ Ifx_Strict_32Bit TIM0_CH3_IRQ:1; /**< \brief [3:3] TIM0 shared interrupt channel 3 (rh) */
+ Ifx_Strict_32Bit TIM0_CH4_IRQ:1; /**< \brief [4:4] TIM0 shared interrupt channel 4 (rh) */
+ Ifx_Strict_32Bit TIM0_CH5_IRQ:1; /**< \brief [5:5] TIM0 shared interrupt channel 5 (rh) */
+ Ifx_Strict_32Bit TIM0_CH6_IRQ:1; /**< \brief [6:6] TIM0 shared interrupt channel 6 (rh) */
+ Ifx_Strict_32Bit TIM0_CH7_IRQ:1; /**< \brief [7:7] TIM0 shared interrupt channel 7 (rh) */
+ Ifx_Strict_32Bit TIM1_CH0_IRQ:1; /**< \brief [8:8] TIM1 shared interrupt channel 0 (rh) */
+ Ifx_Strict_32Bit TIM1_CH1_IRQ:1; /**< \brief [9:9] TIM1 shared interrupt channel 1 (rh) */
+ Ifx_Strict_32Bit TIM1_CH2_IRQ:1; /**< \brief [10:10] TIM1 shared interrupt channel 2 (rh) */
+ Ifx_Strict_32Bit TIM1_CH3_IRQ:1; /**< \brief [11:11] TIM1 shared interrupt channel 3 (rh) */
+ Ifx_Strict_32Bit TIM1_CH4_IRQ:1; /**< \brief [12:12] TIM1 shared interrupt channel 4 (rh) */
+ Ifx_Strict_32Bit TIM1_CH5_IRQ:1; /**< \brief [13:13] TIM1 shared interrupt channel 5 (rh) */
+ Ifx_Strict_32Bit TIM1_CH6_IRQ:1; /**< \brief [14:14] TIM1 shared interrupt channel 6 (rh) */
+ Ifx_Strict_32Bit TIM1_CH7_IRQ:1; /**< \brief [15:15] TIM1 shared interrupt channel 7 (rh) */
+ Ifx_Strict_32Bit TIM2_CH0_IRQ:1; /**< \brief [16:16] TIM2 shared interrupt channel 0 (rh) */
+ Ifx_Strict_32Bit TIM2_CH1_IRQ:1; /**< \brief [17:17] TIM2 shared interrupt channel 1 (rh) */
+ Ifx_Strict_32Bit TIM2_CH2_IRQ:1; /**< \brief [18:18] TIM2 shared interrupt channel 2 (rh) */
+ Ifx_Strict_32Bit TIM2_CH3_IRQ:1; /**< \brief [19:19] TIM2 shared interrupt channel 3 (rh) */
+ Ifx_Strict_32Bit TIM2_CH4_IRQ:1; /**< \brief [20:20] TIM2 shared interrupt channel 4 (rh) */
+ Ifx_Strict_32Bit TIM2_CH5_IRQ:1; /**< \brief [21:21] TIM2 shared interrupt channel 5 (rh) */
+ Ifx_Strict_32Bit TIM2_CH6_IRQ:1; /**< \brief [22:22] TIM2 shared interrupt channel 6 (rh) */
+ Ifx_Strict_32Bit TIM2_CH7_IRQ:1; /**< \brief [23:23] TIM2 shared interrupt channel 7 (rh) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_ICM_IRQG_2_Bits;
+
+/** \brief MCS Interrupt Group 0 */
+typedef struct _Ifx_GTM_ICM_IRQG_4_Bits
+{
+ Ifx_Strict_32Bit MCS0_CH0_IRQ:1; /**< \brief [0:0] MCS0 channel 0 interrupt (rh) */
+ Ifx_Strict_32Bit MCS0_CH1_IRQ:1; /**< \brief [1:1] MCS0 channel 1 interrupt (rh) */
+ Ifx_Strict_32Bit MCS0_CH2_IRQ:1; /**< \brief [2:2] MCS0 channel 2 interrupt (rh) */
+ Ifx_Strict_32Bit MCS0_CH3_IRQ:1; /**< \brief [3:3] MCS0 channel 3 interrupt (rh) */
+ Ifx_Strict_32Bit MCS0_CH4_IRQ:1; /**< \brief [4:4] MCS0 channel 4 interrupt (rh) */
+ Ifx_Strict_32Bit MCS0_CH5_IRQ:1; /**< \brief [5:5] MCS0 channel 5 interrupt (rh) */
+ Ifx_Strict_32Bit MCS0_CH6_IRQ:1; /**< \brief [6:6] MCS0 channel 6 interrupt (rh) */
+ Ifx_Strict_32Bit MCS0_CH7_IRQ:1; /**< \brief [7:7] MCS0 channel 7 interrupt (rh) */
+ Ifx_Strict_32Bit MCS1_CH0_IRQ:1; /**< \brief [8:8] MCS1 channel 0 interrupt (rh) */
+ Ifx_Strict_32Bit MCS1_CH1_IRQ:1; /**< \brief [9:9] MCS1 channel 1 interrupt (rh) */
+ Ifx_Strict_32Bit MCS1_CH2_IRQ:1; /**< \brief [10:10] MCS1 channel 2 interrupt (rh) */
+ Ifx_Strict_32Bit MCS1_CH3_IRQ:1; /**< \brief [11:11] MCS1 channel 3 interrupt (rh) */
+ Ifx_Strict_32Bit MCS1_CH4_IRQ:1; /**< \brief [12:12] MCS1 channel 4 interrupt (rh) */
+ Ifx_Strict_32Bit MCS1_CH5_IRQ:1; /**< \brief [13:13] MCS1 channel 5 interrupt (rh) */
+ Ifx_Strict_32Bit MCS1_CH6_IRQ:1; /**< \brief [14:14] MCS1 channel 6 interrupt (rh) */
+ Ifx_Strict_32Bit MCS1_CH7_IRQ:1; /**< \brief [15:15] MCS1 channel 7 interrupt (rh) */
+ Ifx_Strict_32Bit MCS2_CH0_IRQ:1; /**< \brief [16:16] MCS2 channel 0 interrupt (rh) */
+ Ifx_Strict_32Bit MCS2_CH1_IRQ:1; /**< \brief [17:17] MCS2 channel 1 interrupt (rh) */
+ Ifx_Strict_32Bit MCS2_CH2_IRQ:1; /**< \brief [18:18] MCS2 channel 2 interrupt (rh) */
+ Ifx_Strict_32Bit MCS2_CH3_IRQ:1; /**< \brief [19:19] MCS2 channel 3 interrupt (rh) */
+ Ifx_Strict_32Bit MCS2_CH4_IRQ:1; /**< \brief [20:20] MCS2 channel 4 interrupt (rh) */
+ Ifx_Strict_32Bit MCS2_CH5_IRQ:1; /**< \brief [21:21] MCS2 channel 5 interrupt (rh) */
+ Ifx_Strict_32Bit MCS2_CH6_IRQ:1; /**< \brief [22:22] MCS2 channel 6 interrupt (rh) */
+ Ifx_Strict_32Bit MCS2_CH7_IRQ:1; /**< \brief [23:23] MCS2 channel 7 interrupt (rh) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_ICM_IRQG_4_Bits;
+
+/** \brief TOM Interrupt Group 0 */
+typedef struct _Ifx_GTM_ICM_IRQG_6_Bits
+{
+ Ifx_Strict_32Bit TOM0_CH0_IRQ:1; /**< \brief [0:0] TOM0 channel 0 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM0_CH1_IRQ:1; /**< \brief [1:1] TOM0 channel 1 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM0_CH2_IRQ:1; /**< \brief [2:2] TOM0 channel 2 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM0_CH3_IRQ:1; /**< \brief [3:3] TOM0 channel 3 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM0_CH4_IRQ:1; /**< \brief [4:4] TOM0 channel 4 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM0_CH5_IRQ:1; /**< \brief [5:5] TOM0 channel 5 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM0_CH6_IRQ:1; /**< \brief [6:6] TOM0 channel 6 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM0_CH7_IRQ:1; /**< \brief [7:7] TOM0 channel 7 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM0_CH8_IRQ:1; /**< \brief [8:8] TOM0 channel 8 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM0_CH9_IRQ:1; /**< \brief [9:9] TOM0 channel 9 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM0_CH10_IRQ:1; /**< \brief [10:10] TOM0 channel 10 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM0_CH11_IRQ:1; /**< \brief [11:11] TOM0 channel 11 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM0_CH12_IRQ:1; /**< \brief [12:12] TOM0 channel 12 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM0_CH13_IRQ:1; /**< \brief [13:13] TOM0 channel 13 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM0_CH14_IRQ:1; /**< \brief [14:14] TOM0 channel 14 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM0_CH15_IRQ:1; /**< \brief [15:15] TOM0 channel 15 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM1_CH0_IRQ:1; /**< \brief [16:16] TOM1 channel 0 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM1_CH1_IRQ:1; /**< \brief [17:17] TOM1 channel 1 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM1_CH2_IRQ:1; /**< \brief [18:18] TOM1 channel 2 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM1_CH3_IRQ:1; /**< \brief [19:19] TOM1 channel 3 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM1_CH4_IRQ:1; /**< \brief [20:20] TOM1 channel 4 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM1_CH5_IRQ:1; /**< \brief [21:21] TOM1 channel 5 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM1_CH6_IRQ:1; /**< \brief [22:22] TOM1 channel 6 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM1_CH7_IRQ:1; /**< \brief [23:23] TOM1 channel 7 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM1_CH8_IRQ:1; /**< \brief [24:24] TOM1 channel 8 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM1_CH9_IRQ:1; /**< \brief [25:25] TOM1 channel 9 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM1_CH10_IRQ:1; /**< \brief [26:26] TOM1 channel 10 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM1_CH11_IRQ:1; /**< \brief [27:27] TOM1 channel 11 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM1_CH12_IRQ:1; /**< \brief [28:28] TOM1 channel 12 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM1_CH13_IRQ:1; /**< \brief [29:29] TOM1 channel 13 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM1_CH14_IRQ:1; /**< \brief [30:30] TOM1 channel 14 shared interrupt (rh) */
+ Ifx_Strict_32Bit TOM1_CH15_IRQ:1; /**< \brief [31:31] TOM1 channel 15 shared interrupt (rh) */
+} Ifx_GTM_ICM_IRQG_6_Bits;
+
+/** \brief ATOM Interrupt Group 0 */
+typedef struct _Ifx_GTM_ICM_IRQG_9_Bits
+{
+ Ifx_Strict_32Bit ATOM0_CH0_IRQ:1; /**< \brief [0:0] ATOM0 channel 0 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM0_CH1_IRQ:1; /**< \brief [1:1] ATOM0 channel 1 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM0_CH2_IRQ:1; /**< \brief [2:2] ATOM0 channel 2 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM0_CH3_IRQ:1; /**< \brief [3:3] ATOM0 channel 3 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM0_CH4_IRQ:1; /**< \brief [4:4] ATOM0 channel 4 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM0_CH5_IRQ:1; /**< \brief [5:5] ATOM0 channel 5 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM0_CH6_IRQ:1; /**< \brief [6:6] ATOM0 channel 6 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM0_CH7_IRQ:1; /**< \brief [7:7] ATOM0 channel 7 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM1_CH0_IRQ:1; /**< \brief [8:8] ATOM1 channel 0 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM1_CH1_IRQ:1; /**< \brief [9:9] ATOM1 channel 1 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM1_CH2_IRQ:1; /**< \brief [10:10] ATOM1 channel 2 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM1_CH3_IRQ:1; /**< \brief [11:11] ATOM1 channel 3 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM1_CH4_IRQ:1; /**< \brief [12:12] ATOM1 channel 4 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM1_CH5_IRQ:1; /**< \brief [13:13] ATOM1 channel 5 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM1_CH6_IRQ:1; /**< \brief [14:14] ATOM1 channel 6 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM1_CH7_IRQ:1; /**< \brief [15:15] ATOM1 channel 7 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM2_CH0_IRQ:1; /**< \brief [16:16] ATOM2 channel 0 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM2_CH1_IRQ:1; /**< \brief [17:17] ATOM2 channel 1 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM2_CH2_IRQ:1; /**< \brief [18:18] ATOM2 channel 2 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM2_CH3_IRQ:1; /**< \brief [19:19] ATOM2 channel 3 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM2_CH4_IRQ:1; /**< \brief [20:20] ATOM2 channel 4 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM2_CH5_IRQ:1; /**< \brief [21:21] ATOM2 channel 5 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM2_CH6_IRQ:1; /**< \brief [22:22] ATOM2 channel 6 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM2_CH7_IRQ:1; /**< \brief [23:23] ATOM2 channel 7 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM3_CH0_IRQ:1; /**< \brief [24:24] ATOM3 channel 0 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM3_CH1_IRQ:1; /**< \brief [25:25] ATOM3 channel 1 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM3_CH2_IRQ:1; /**< \brief [26:26] ATOM3 channel 2 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM3_CH3_IRQ:1; /**< \brief [27:27] ATOM3 channel 3 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM3_CH4_IRQ:1; /**< \brief [28:28] ATOM3 channel 4 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM3_CH5_IRQ:1; /**< \brief [29:29] ATOM3 channel 5 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM3_CH6_IRQ:1; /**< \brief [30:30] ATOM3 channel 6 shared interrupt (rh) */
+ Ifx_Strict_32Bit ATOM3_CH7_IRQ:1; /**< \brief [31:31] ATOM3 channel 7 shared interrupt (rh) */
+} Ifx_GTM_ICM_IRQG_9_Bits;
+
+/** \brief ICM Channel Error Interrupt 0 Register */
+typedef struct _Ifx_GTM_ICM_IRQG_CEI0_Bits
+{
+ Ifx_Strict_32Bit FIFO0_CH0_EIRQ:1; /**< \brief [0:0] FIFO0 channel 0 error interrupt (rh) */
+ Ifx_Strict_32Bit FIFO0_CH1_EIRQ:1; /**< \brief [1:1] FIFO0 channel 1 shared interrupt (rh) */
+ Ifx_Strict_32Bit FIFO0_CH2_EIRQ:1; /**< \brief [2:2] FIFO0 channel 2 shared interrupt (rh) */
+ Ifx_Strict_32Bit FIFO0_CH3_EIRQ:1; /**< \brief [3:3] FIFO0 channel 3 shared interrupt (rh) */
+ Ifx_Strict_32Bit FIFO0_CH4_EIRQ:1; /**< \brief [4:4] FIFO0 channel 4 shared interrupt (rh) */
+ Ifx_Strict_32Bit FIFO0_CH5_EIRQ:1; /**< \brief [5:5] FIFO0 channel 5 shared interrupt (rh) */
+ Ifx_Strict_32Bit FIFO0_CH6_EIRQ:1; /**< \brief [6:6] FIFO0 channel 6 shared interrupt (rh) */
+ Ifx_Strict_32Bit FIFO0_CH7_EIRQ:1; /**< \brief [7:7] FIFO0 channel 7 shared interrupt (rh) */
+ Ifx_Strict_32Bit reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_GTM_ICM_IRQG_CEI0_Bits;
+
+/** \brief ICM Channel Error Interrupt 1 Register */
+typedef struct _Ifx_GTM_ICM_IRQG_CEI1_Bits
+{
+ Ifx_Strict_32Bit TIM0_CH0_EIRQ:1; /**< \brief [0:0] TIM0 channel 0 error interrupt (rh) */
+ Ifx_Strict_32Bit TIM0_CH1_EIRQ:1; /**< \brief [1:1] TIM0 channel 1 error interrupt (rh) */
+ Ifx_Strict_32Bit TIM0_CH2_EIRQ:1; /**< \brief [2:2] TIM0 channel 2 error interrupt (rh) */
+ Ifx_Strict_32Bit TIM0_CH3_EIRQ:1; /**< \brief [3:3] TIM0 channel 3 error interrupt (rh) */
+ Ifx_Strict_32Bit TIM0_CH4_EIRQ:1; /**< \brief [4:4] TIM0 channel 4 error interrupt (rh) */
+ Ifx_Strict_32Bit TIM0_CH5_EIRQ:1; /**< \brief [5:5] TIM0 channel 5 error interrupt (rh) */
+ Ifx_Strict_32Bit TIM0_CH6_EIRQ:1; /**< \brief [6:6] TIM0 channel 6 error interrupt (rh) */
+ Ifx_Strict_32Bit TIM0_CH7_EIRQ:1; /**< \brief [7:7] TIM0 channel 7 error interrupt (rh) */
+ Ifx_Strict_32Bit TIM1_CH0_EIRQ:1; /**< \brief [8:8] TIM1 channel 0 error interrupt (rh) */
+ Ifx_Strict_32Bit TIM1_CH1_EIRQ:1; /**< \brief [9:9] TIM1 channel 1 error interrupt (rh) */
+ Ifx_Strict_32Bit TIM1_CH2_EIRQ:1; /**< \brief [10:10] TIM1 channel 2 error interrupt (rh) */
+ Ifx_Strict_32Bit TIM1_CH3_EIRQ:1; /**< \brief [11:11] TIM1 channel 3 error interrupt (rh) */
+ Ifx_Strict_32Bit TIM1_CH4_EIRQ:1; /**< \brief [12:12] TIM1 channel 4 error interrupt (rh) */
+ Ifx_Strict_32Bit TIM1_CH5_EIRQ:1; /**< \brief [13:13] TIM1 channel 5 error interrupt (rh) */
+ Ifx_Strict_32Bit TIM1_CH6_EIRQ:1; /**< \brief [14:14] TIM1 channel 6 error interrupt (rh) */
+ Ifx_Strict_32Bit TIM1_CH7_EIRQ:1; /**< \brief [15:15] TIM1 channel 7 error interrupt (rh) */
+ Ifx_Strict_32Bit TIM2_CH0_EIRQ:1; /**< \brief [16:16] TIM2 channel 0 error interrupt (rh) */
+ Ifx_Strict_32Bit TIM2_CH1_EIRQ:1; /**< \brief [17:17] TIM2 channel 1 error interrupt (rh) */
+ Ifx_Strict_32Bit TIM2_CH2_EIRQ:1; /**< \brief [18:18] TIM2 channel 2 error interrupt (rh) */
+ Ifx_Strict_32Bit TIM2_CH3_EIRQ:1; /**< \brief [19:19] TIM2 channel 3 error interrupt (rh) */
+ Ifx_Strict_32Bit TIM2_CH4_EIRQ:1; /**< \brief [20:20] TIM2 channel 4 error interrupt (rh) */
+ Ifx_Strict_32Bit TIM2_CH5_EIRQ:1; /**< \brief [21:21] TIM2 channel 5 error interrupt (rh) */
+ Ifx_Strict_32Bit TIM2_CH6_EIRQ:1; /**< \brief [22:22] TIM2 channel 6 error interrupt (rh) */
+ Ifx_Strict_32Bit TIM2_CH7_EIRQ:1; /**< \brief [23:23] TIM2 channel 7 error interrupt (rh) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_ICM_IRQG_CEI1_Bits;
+
+/** \brief ICM Channel Error Interrupt 3 Register */
+typedef struct _Ifx_GTM_ICM_IRQG_CEI3_Bits
+{
+ Ifx_Strict_32Bit MCS0_CH0_EIRQ:1; /**< \brief [0:0] MCS0 channel 0 error interrupt (rh) */
+ Ifx_Strict_32Bit MCS0_CH1_EIRQ:1; /**< \brief [1:1] MCS0 channel 1 error interrupt (rh) */
+ Ifx_Strict_32Bit MCS0_CH2_EIRQ:1; /**< \brief [2:2] MCS0 channel 2 error interrupt (rh) */
+ Ifx_Strict_32Bit MCS0_CH3_EIRQ:1; /**< \brief [3:3] MCS0 channel 3 error interrupt (rh) */
+ Ifx_Strict_32Bit MCS0_CH4_EIRQ:1; /**< \brief [4:4] MCS0 channel 4 error interrupt (rh) */
+ Ifx_Strict_32Bit MCS0_CH5_EIRQ:1; /**< \brief [5:5] MCS0 channel 5 error interrupt (rh) */
+ Ifx_Strict_32Bit MCS0_CH6_EIRQ:1; /**< \brief [6:6] MCS0 channel 6 error interrupt (rh) */
+ Ifx_Strict_32Bit MCS0_CH7_EIRQ:1; /**< \brief [7:7] MCS0 channel 7 error interrupt (rh) */
+ Ifx_Strict_32Bit MCS1_CH0_EIRQ:1; /**< \brief [8:8] MCS1 channel 0 error interrupt (rh) */
+ Ifx_Strict_32Bit MCS1_CH1_EIRQ:1; /**< \brief [9:9] MCS1 channel 1 error interrupt (rh) */
+ Ifx_Strict_32Bit MCS1_CH2_EIRQ:1; /**< \brief [10:10] MCS1 channel 2 error interrupt (rh) */
+ Ifx_Strict_32Bit MCS1_CH3_EIRQ:1; /**< \brief [11:11] MCS1 channel 3 error interrupt (rh) */
+ Ifx_Strict_32Bit MCS1_CH4_EIRQ:1; /**< \brief [12:12] MCS1 channel 4 error interrupt (rh) */
+ Ifx_Strict_32Bit MCS1_CH5_EIRQ:1; /**< \brief [13:13] MCS1 channel 5 error interrupt (rh) */
+ Ifx_Strict_32Bit MCS1_CH6_EIRQ:1; /**< \brief [14:14] MCS1 channel 6 error interrupt (rh) */
+ Ifx_Strict_32Bit MCS1_CH7_EIRQ:1; /**< \brief [15:15] MCS1 channel 7 error interrupt (rh) */
+ Ifx_Strict_32Bit MCS2_CH0_EIRQ:1; /**< \brief [16:16] MCS2 channel 0 error interrupt (rh) */
+ Ifx_Strict_32Bit MCS2_CH1_EIRQ:1; /**< \brief [17:17] MCS2 channel 1 error interrupt (rh) */
+ Ifx_Strict_32Bit MCS2_CH2_EIRQ:1; /**< \brief [18:18] MCS2 channel 2 error interrupt (rh) */
+ Ifx_Strict_32Bit MCS2_CH3_EIRQ:1; /**< \brief [19:19] MCS2 channel 3 error interrupt (rh) */
+ Ifx_Strict_32Bit MCS2_CH4_EIRQ:1; /**< \brief [20:20] MCS2 channel 4 error interrupt (rh) */
+ Ifx_Strict_32Bit MCS2_CH5_EIRQ:1; /**< \brief [21:21] MCS2 channel 5 error interrupt (rh) */
+ Ifx_Strict_32Bit MCS2_CH6_EIRQ:1; /**< \brief [22:22] MCS2 channel 6 error interrupt (rh) */
+ Ifx_Strict_32Bit MCS2_CH7_EIRQ:1; /**< \brief [23:23] MCS2 channel 7 error interrupt (rh) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_ICM_IRQG_CEI3_Bits;
+
+/** \brief ICM Module Error Interrupt Register */
+typedef struct _Ifx_GTM_ICM_IRQG_MEI_Bits
+{
+ Ifx_Strict_32Bit GTM_EIRQ:1; /**< \brief [0:0] GTM Error interrupt request (rh) */
+ Ifx_Strict_32Bit BRC_EIRQ:1; /**< \brief [1:1] BRC error interrupt (rh) */
+ Ifx_Strict_32Bit FIFO0_EIRQ:1; /**< \brief [2:2] FIFO0 error interrupt (rh) */
+ Ifx_Strict_32Bit reserved_3:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit TIM0_EIRQ:1; /**< \brief [4:4] TIM0 error interrupt (rh) */
+ Ifx_Strict_32Bit TIM1_EIRQ:1; /**< \brief [5:5] TIM1 error interrupt (rh) */
+ Ifx_Strict_32Bit TIM2_EIRQ:1; /**< \brief [6:6] TIM2 error interrupt (rh) */
+ Ifx_Strict_32Bit reserved_7:5; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit MCS0_EIRQ:1; /**< \brief [12:12] MCS0 error interrupt (rh) */
+ Ifx_Strict_32Bit MCS1_EIRQ:1; /**< \brief [13:13] MCS1 error interrupt (rh) */
+ Ifx_Strict_32Bit MCS2_EIRQ:1; /**< \brief [14:14] MCS2 error interrupt (rh) */
+ Ifx_Strict_32Bit reserved_15:5; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SPE0_EIRQ:1; /**< \brief [20:20] SPE0 error interrupt (rh) */
+ Ifx_Strict_32Bit SPE1_EIRQ:1; /**< \brief [21:21] SPE1 error interrupt (rh) */
+ Ifx_Strict_32Bit reserved_22:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit CMP_EIRQ:1; /**< \brief [24:24] CMP error interrupt (rh) */
+ Ifx_Strict_32Bit DPLL_EIRQ:1; /**< \brief [25:25] DPLL error interrupt (rh) */
+ Ifx_Strict_32Bit reserved_26:6; /**< \brief \internal Reserved */
+} Ifx_GTM_ICM_IRQG_MEI_Bits;
+
+/** \brief CAN Output Select Register */
+typedef struct _Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits
+{
+ Ifx_Strict_32Bit SEL0:4; /**< \brief [3:0] Output Selection for CAN GTM connection (rw) */
+ Ifx_Strict_32Bit SEL1:4; /**< \brief [7:4] Output Selection for CAN GTM connection (rw) */
+ Ifx_Strict_32Bit SEL2:4; /**< \brief [11:8] Output Selection for CAN GTM connection (rw) */
+ Ifx_Strict_32Bit SEL3:4; /**< \brief [15:12] Output Selection for CAN GTM connection (rw) */
+ Ifx_Strict_32Bit SEL4:4; /**< \brief [19:16] Output Selection for CAN GTM connection (rw) */
+ Ifx_Strict_32Bit SEL5:4; /**< \brief [23:20] Output Selection for CAN GTM connection (rw) */
+ Ifx_Strict_32Bit SEL6:4; /**< \brief [27:24] Output Selection for CAN GTM connection (rw) */
+ Ifx_Strict_32Bit SEL7:4; /**< \brief [31:28] Output Selection for CAN GTM connection (rw) */
+} Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits;
+
+/** \brief DSADC Input Select Register */
+typedef struct _Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits
+{
+ Ifx_Strict_32Bit INSEL0:4; /**< \brief [3:0] In Selection for DSADCn GTM connection (rw) */
+ Ifx_Strict_32Bit INSEL1:4; /**< \brief [7:4] In Selection for DSADCn GTM connection (rw) */
+ Ifx_Strict_32Bit INSEL2:4; /**< \brief [11:8] In Selection for DSADCn GTM connection (rw) */
+ Ifx_Strict_32Bit INSEL3:4; /**< \brief [15:12] In Selection for DSADCn GTM connection (rw) */
+ Ifx_Strict_32Bit INSEL4:4; /**< \brief [19:16] In Selection for DSADCn GTM connection (rw) */
+ Ifx_Strict_32Bit INSEL5:4; /**< \brief [23:20] In Selection for DSADCn GTM connection (rw) */
+ Ifx_Strict_32Bit INSEL6:4; /**< \brief [27:24] In Selection for DSADCn GTM connection (rw) */
+ Ifx_Strict_32Bit INSEL7:4; /**< \brief [31:28] In Selection for DSADCn GTM connection (rw) */
+} Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits;
+
+/** \brief DSADC Output Select Register */
+typedef struct _Ifx_GTM_INOUTSEL_DSADC_OUTSEL_Bits
+{
+ Ifx_Strict_32Bit SEL0:3; /**< \brief [2:0] Output Selection for DSADC0 GTM connection (rw) */
+ Ifx_Strict_32Bit reserved_3:5; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SEL2:3; /**< \brief [10:8] Output Selection for DSADC2 GTM connection (rw) */
+ Ifx_Strict_32Bit reserved_11:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SEL3:3; /**< \brief [14:12] Output Selection for DSADC3 GTM connection (rw) */
+ Ifx_Strict_32Bit reserved_15:17; /**< \brief \internal Reserved */
+} Ifx_GTM_INOUTSEL_DSADC_OUTSEL_Bits;
+
+/** \brief PSI5 Output Select 0 Register */
+typedef struct _Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits
+{
+ Ifx_Strict_32Bit SEL0:4; /**< \brief [3:0] Output Selection for PSI5x GTM connection (rw) */
+ Ifx_Strict_32Bit SEL1:4; /**< \brief [7:4] Output Selection for PSI5x GTM connection (rw) */
+ Ifx_Strict_32Bit SEL2:4; /**< \brief [11:8] Output Selection for PSI5x GTM connection (rw) */
+ Ifx_Strict_32Bit SEL3:4; /**< \brief [15:12] Output Selection for PSI5x GTM connection (rw) */
+ Ifx_Strict_32Bit SEL4:4; /**< \brief [19:16] Output Selection for PSI5x GTM connection (rw) */
+ Ifx_Strict_32Bit SEL5:4; /**< \brief [23:20] Output Selection for PSI5x GTM connection (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits;
+
+/** \brief PSI5-S Output Select Register */
+typedef struct _Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits
+{
+ Ifx_Strict_32Bit SEL0:4; /**< \brief [3:0] Output Selection for PSI5x GTM connection (rw) */
+ Ifx_Strict_32Bit SEL1:4; /**< \brief [7:4] Output Selection for PSI5x GTM connection (rw) */
+ Ifx_Strict_32Bit SEL2:4; /**< \brief [11:8] Output Selection for PSI5x GTM connection (rw) */
+ Ifx_Strict_32Bit reserved_12:4; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SEL4:4; /**< \brief [19:16] Output Selection for PSI5x GTM connection (rw) */
+ Ifx_Strict_32Bit SEL5:4; /**< \brief [23:20] Output Selection for PSI5x GTM connection (rw) */
+ Ifx_Strict_32Bit SEL6:4; /**< \brief [27:24] Output Selection for PSI5x GTM connection (rw) */
+ Ifx_Strict_32Bit reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits;
+
+/** \brief Timer Output Select Register */
+typedef struct _Ifx_GTM_INOUTSEL_T_OUTSEL_Bits
+{
+ Ifx_Strict_32Bit SEL0:2; /**< \brief [1:0] TOUT(n*16+0) Output Selection (rw) */
+ Ifx_Strict_32Bit SEL1:2; /**< \brief [3:2] TOUT(n*16+1) Output Selection (rw) */
+ Ifx_Strict_32Bit SEL2:2; /**< \brief [5:4] TOUT(n*16+2) Output Selection (rw) */
+ Ifx_Strict_32Bit SEL3:2; /**< \brief [7:6] TOUT(n*16+3) Output Selection (rw) */
+ Ifx_Strict_32Bit SEL4:2; /**< \brief [9:8] TOUT(n*16+4) Output Selection (rw) */
+ Ifx_Strict_32Bit SEL5:2; /**< \brief [11:10] TOUT(n*16+5) Output Selection (rw) */
+ Ifx_Strict_32Bit SEL6:2; /**< \brief [13:12] TOUT(n*16+6) Output Selection (rw) */
+ Ifx_Strict_32Bit SEL7:2; /**< \brief [15:14] TOUT(n*16+7) Output Selection (rw) */
+ Ifx_Strict_32Bit SEL8:2; /**< \brief [17:16] TOUT(n*16+8) Output Selection (rw) */
+ Ifx_Strict_32Bit SEL9:2; /**< \brief [19:18] TOUT(n*16+9) Output Selection (rw) */
+ Ifx_Strict_32Bit SEL10:2; /**< \brief [21:20] TOUT(n*16+10) Output Selection (rw) */
+ Ifx_Strict_32Bit SEL11:2; /**< \brief [23:22] TOUT(n*16+11) Output Selection (rw) */
+ Ifx_Strict_32Bit SEL12:2; /**< \brief [25:24] TOUT(n*16+12) Output Selection (rw) */
+ Ifx_Strict_32Bit SEL13:2; /**< \brief [27:26] TOUT(n*16+13) Output Selection (rw) */
+ Ifx_Strict_32Bit SEL14:2; /**< \brief [29:28] TOUT(n*16+14) Output Selection (rw) */
+ Ifx_Strict_32Bit SEL15:2; /**< \brief [31:30] TOUT(n*16+15) Output Selection (rw) */
+} Ifx_GTM_INOUTSEL_T_OUTSEL_Bits;
+
+/** \brief TIM Input Select Register */
+typedef struct _Ifx_GTM_INOUTSEL_TIM_INSEL_Bits
+{
+ Ifx_Strict_32Bit CH0SEL:4; /**< \brief [3:0] TIM Channel 0 Input Selection (rw) */
+ Ifx_Strict_32Bit CH1SEL:4; /**< \brief [7:4] TIM Channel 1 Input Selection (rw) */
+ Ifx_Strict_32Bit CH2SEL:4; /**< \brief [11:8] TIM Channel 2 Input Selection (rw) */
+ Ifx_Strict_32Bit CH3SEL:4; /**< \brief [15:12] TIM Channel 3 Input Selection (rw) */
+ Ifx_Strict_32Bit CH4SEL:4; /**< \brief [19:16] TIM Channel 4 Input Selection (rw) */
+ Ifx_Strict_32Bit CH5SEL:4; /**< \brief [23:20] TIM Channel 5 Input Selection (rw) */
+ Ifx_Strict_32Bit CH6SEL:4; /**< \brief [27:24] TIM Channel 6 Input Selection (rw) */
+ Ifx_Strict_32Bit CH7SEL:4; /**< \brief [31:28] TIM Channel 7 Input Selection (rw) */
+} Ifx_GTM_INOUTSEL_TIM_INSEL_Bits;
+
+/** \brief GTM Interrupt Enable Register */
+typedef struct _Ifx_GTM_IRQ_EN_Bits
+{
+ Ifx_Strict_32Bit AEI_TO_XPT_IRQ_EN:1; /**< \brief [0:0] AEI_TO_XPT_IRQ interrupt enable. (rw) */
+ Ifx_Strict_32Bit AEI_USP_ADDR_IRQ_EN:1; /**< \brief [1:1] AEI_USP_ADDR_IRQ interrupt enable. (rw) */
+ Ifx_Strict_32Bit AEI_IM_ADDR_IRQ_EN:1; /**< \brief [2:2] AEI_IM_ADDR_IRQ interrupt enable. (rw) */
+ Ifx_Strict_32Bit AEI_USP_BE_IRQ_EN:1; /**< \brief [3:3] AEI_USP_BE_IRQ interrupt enable. (rw) */
+ Ifx_Strict_32Bit reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_GTM_IRQ_EN_Bits;
+
+/** \brief GTM Software Interrupt Generation Register */
+typedef struct _Ifx_GTM_IRQ_FORCINT_Bits
+{
+ Ifx_Strict_32Bit TRG_AEI_TO_XPT:1; /**< \brief [0:0] Trigger AEI_TO_XPT_IRQ interrupt by software. (w) */
+ Ifx_Strict_32Bit TRG_AEI_USP_ADDR:1; /**< \brief [1:1] Trigger AEI_USP_ADDR_IRQ interrupt by software. (w) */
+ Ifx_Strict_32Bit TRG_AEI_IM_ADDR:1; /**< \brief [2:2] Trigger AEI_IM_ADDR_IRQ interrupt by software. (w) */
+ Ifx_Strict_32Bit TRG_AEI_USP_BE:1; /**< \brief [3:3] Trigger AEI_USP_BE_IRQ interrupt by software. (w) */
+ Ifx_Strict_32Bit reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_GTM_IRQ_FORCINT_Bits;
+
+/** \brief GTM Top Level Interrupts Mode Selection */
+typedef struct _Ifx_GTM_IRQ_MODE_Bits
+{
+ Ifx_Strict_32Bit IRQ_MODE:2; /**< \brief [1:0] Interrupt strategy mode selection for the AEI timeout and address monitoring interrupts (rw) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_GTM_IRQ_MODE_Bits;
+
+/** \brief GTM Interrupt Notification Register */
+typedef struct _Ifx_GTM_IRQ_NOTIFY_Bits
+{
+ Ifx_Strict_32Bit AEI_TO_XPT:1; /**< \brief [0:0] AEI Timeout exception occurred (rwh) */
+ Ifx_Strict_32Bit AEI_USP_ADDR:1; /**< \brief [1:1] AEI Unsupported address interrupt (rwh) */
+ Ifx_Strict_32Bit AEI_IM_ADDR:1; /**< \brief [2:2] AEI Illegal Module address interrupt (rwh) */
+ Ifx_Strict_32Bit AEI_USP_BE:1; /**< \brief [3:3] AEI Unsupported byte enable interrupt (rwh) */
+ Ifx_Strict_32Bit reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_GTM_IRQ_NOTIFY_Bits;
+
+/** \brief Kernel Reset Register 0 */
+typedef struct _Ifx_GTM_KRST0_Bits
+{
+ Ifx_Strict_32Bit RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ Ifx_Strict_32Bit RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rw) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_GTM_KRST0_Bits;
+
+/** \brief Kernel Reset Register 1 */
+typedef struct _Ifx_GTM_KRST1_Bits
+{
+ Ifx_Strict_32Bit RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ Ifx_Strict_32Bit reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_GTM_KRST1_Bits;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef struct _Ifx_GTM_KRSTCLR_Bits
+{
+ Ifx_Strict_32Bit CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
+ Ifx_Strict_32Bit reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_GTM_KRSTCLR_Bits;
+
+/** \brief MAP Control Register */
+typedef struct _Ifx_GTM_MAP_CTRL_Bits
+{
+ Ifx_Strict_32Bit TSEL:1; /**< \brief [0:0] TRIGGER signal output select. (rw) */
+ Ifx_Strict_32Bit SSL:3; /**< \brief [3:1] STATE signal output select. (rw) */
+ Ifx_Strict_32Bit LSEL:1; /**< \brief [4:4] TIM0_IN6 input level selection (rw) */
+ Ifx_Strict_32Bit reserved_5:11; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit TSPP0_EN:1; /**< \brief [16:16] Enable of TSPP0 subunit (rw) */
+ Ifx_Strict_32Bit TSPP0_DLD:1; /**< \brief [17:17] DIR level definition bit (rw) */
+ Ifx_Strict_32Bit reserved_18:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit TSPP0_I0V:1; /**< \brief [20:20] Disable of TSPP0 TIM0_CHx(48) input line. (rw) */
+ Ifx_Strict_32Bit TSPP0_I1V:1; /**< \brief [21:21] Disable of TSPP0 TIM0_CHy(48) input line. (rw) */
+ Ifx_Strict_32Bit TSPP0_I2V:1; /**< \brief [22:22] Disable of TSPP0 TIM0_CHz(48) input line. (rw) */
+ Ifx_Strict_32Bit reserved_23:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit TSPP1_EN:1; /**< \brief [24:24] Enable of TSPP1 subunit (rw) */
+ Ifx_Strict_32Bit TSPP1_DLD:1; /**< \brief [25:25] DIR level definition bit (rw) */
+ Ifx_Strict_32Bit reserved_26:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit TSPP1_I0V:1; /**< \brief [28:28] Disable of TSPP1 TIM0_CHx(48) input line (rw) */
+ Ifx_Strict_32Bit TSPP1_I1V:1; /**< \brief [29:29] Disable of TSPP1 TIM0_CHy(48) input line (rw) */
+ Ifx_Strict_32Bit TSPP1_I2V:1; /**< \brief [30:30] Disable of TSPP1 TIM0_CHz(48) input line. (rw) */
+ Ifx_Strict_32Bit reserved_31:1; /**< \brief \internal Reserved */
+} Ifx_GTM_MAP_CTRL_Bits;
+
+/** \brief Memory Layout Configuration Register */
+typedef struct _Ifx_GTM_MCFG_CTRL_Bits
+{
+ Ifx_Strict_32Bit MEM0:2; /**< \brief [1:0] Configure Memory pages for MCS-instance MCS0 (rw) */
+ Ifx_Strict_32Bit MEM1:2; /**< \brief [3:2] Configure Memory pages for MCS-instance MCS1 (rw) */
+ Ifx_Strict_32Bit MEM2:2; /**< \brief [5:4] Configure Memory pages for MCS-instance MCS2 (rw) */
+ Ifx_Strict_32Bit reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_GTM_MCFG_CTRL_Bits;
+
+/** \brief MCS Clear Trigger Control Register */
+typedef struct _Ifx_GTM_MCS_CH0_CTRG_Bits
+{
+ Ifx_Strict_32Bit TRG0:1; /**< \brief [0:0] Trigger bit 0 (rw) */
+ Ifx_Strict_32Bit TRG1:1; /**< \brief [1:1] Trigger bit 1 (rw) */
+ Ifx_Strict_32Bit TRG2:1; /**< \brief [2:2] Trigger bit 2 (rw) */
+ Ifx_Strict_32Bit TRG3:1; /**< \brief [3:3] Trigger bit 3 (rw) */
+ Ifx_Strict_32Bit TRG4:1; /**< \brief [4:4] Trigger bit 4 (rw) */
+ Ifx_Strict_32Bit TRG5:1; /**< \brief [5:5] Trigger bit 5 (rw) */
+ Ifx_Strict_32Bit TRG6:1; /**< \brief [6:6] Trigger bit 6 (rw) */
+ Ifx_Strict_32Bit TRG7:1; /**< \brief [7:7] Trigger bit 7 (rw) */
+ Ifx_Strict_32Bit TRG8:1; /**< \brief [8:8] Trigger bit 8 (rw) */
+ Ifx_Strict_32Bit TRG9:1; /**< \brief [9:9] Trigger bit 9 (rw) */
+ Ifx_Strict_32Bit TRG10:1; /**< \brief [10:10] Trigger bit 10 (rw) */
+ Ifx_Strict_32Bit TRG11:1; /**< \brief [11:11] Trigger bit 11 (rw) */
+ Ifx_Strict_32Bit TRG12:1; /**< \brief [12:12] Trigger bit 12 (rw) */
+ Ifx_Strict_32Bit TRG13:1; /**< \brief [13:13] Trigger bit 13 (rw) */
+ Ifx_Strict_32Bit TRG14:1; /**< \brief [14:14] Trigger bit 14 (rw) */
+ Ifx_Strict_32Bit TRG15:1; /**< \brief [15:15] Trigger bit 15 (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_MCS_CH0_CTRG_Bits;
+
+/** \brief MCS Set Trigger Control Register */
+typedef struct _Ifx_GTM_MCS_CH0_STRG_Bits
+{
+ Ifx_Strict_32Bit TRG0:1; /**< \brief [0:0] Trigger bit 0 (rw) */
+ Ifx_Strict_32Bit TRG1:1; /**< \brief [1:1] Trigger bit 1 (rw) */
+ Ifx_Strict_32Bit TRG2:1; /**< \brief [2:2] Trigger bit 2 (rw) */
+ Ifx_Strict_32Bit TRG3:1; /**< \brief [3:3] Trigger bit 3 (rw) */
+ Ifx_Strict_32Bit TRG4:1; /**< \brief [4:4] Trigger bit 4 (rw) */
+ Ifx_Strict_32Bit TRG5:1; /**< \brief [5:5] Trigger bit 5 (rw) */
+ Ifx_Strict_32Bit TRG6:1; /**< \brief [6:6] Trigger bit 6 (rw) */
+ Ifx_Strict_32Bit TRG7:1; /**< \brief [7:7] Trigger bit 7 (rw) */
+ Ifx_Strict_32Bit TRG8:1; /**< \brief [8:8] trigger bit 8 (rw) */
+ Ifx_Strict_32Bit TRG9:1; /**< \brief [9:9] Trigger bit 9 (rw) */
+ Ifx_Strict_32Bit TRG10:1; /**< \brief [10:10] Trigger bit 10 (rw) */
+ Ifx_Strict_32Bit TRG11:1; /**< \brief [11:11] Trigger bit 11 (rw) */
+ Ifx_Strict_32Bit TRG12:1; /**< \brief [12:12] Trigger bit 12 (rw) */
+ Ifx_Strict_32Bit TRG13:1; /**< \brief [13:13] Trigger bit 13 (rw) */
+ Ifx_Strict_32Bit TRG14:1; /**< \brief [14:14] Trigger bit 14 (rw) */
+ Ifx_Strict_32Bit TRG15:1; /**< \brief [15:15] Trigger bit 15 (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_MCS_CH0_STRG_Bits;
+
+/** \brief MCS Channel ACB Register */
+typedef struct _Ifx_GTM_MCS_CH_ACB_Bits
+{
+ Ifx_Strict_32Bit ACB0:1; /**< \brief [0:0] ARU Control bit 0 (r) */
+ Ifx_Strict_32Bit ACB1:1; /**< \brief [1:1] ARU Control bit 1 (r) */
+ Ifx_Strict_32Bit ACB2:1; /**< \brief [2:2] ARU Control bit 2 (r) */
+ Ifx_Strict_32Bit ACB3:1; /**< \brief [3:3] ARU Control bit 3 (r) */
+ Ifx_Strict_32Bit ACB4:1; /**< \brief [4:4] ARU Control bit 4 (r) */
+ Ifx_Strict_32Bit reserved_5:27; /**< \brief \internal Reserved */
+} Ifx_GTM_MCS_CH_ACB_Bits;
+
+/** \brief MCS Channel Control Register */
+typedef struct _Ifx_GTM_MCS_CH_CTRL_Bits
+{
+ Ifx_Strict_32Bit EN:1; /**< \brief [0:0] Enable MCS-channel (rw) */
+ Ifx_Strict_32Bit IRQ:1; /**< \brief [1:1] Interrupt state (r) */
+ Ifx_Strict_32Bit ERR:1; /**< \brief [2:2] Error state (r) */
+ Ifx_Strict_32Bit reserved_3:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit CY:1; /**< \brief [4:4] Carry bit state (r) */
+ Ifx_Strict_32Bit Z:1; /**< \brief [5:5] Zero bit state (r) */
+ Ifx_Strict_32Bit V:1; /**< \brief [6:6] Overflow bit state (r) */
+ Ifx_Strict_32Bit N:1; /**< \brief [7:7] Negative bit state (r) */
+ Ifx_Strict_32Bit CAT:1; /**< \brief [8:8] Cancel ARU transfer state (r) */
+ Ifx_Strict_32Bit CWT:1; /**< \brief [9:9] Cancel WURM instruction state (r) */
+ Ifx_Strict_32Bit reserved_10:6; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SP_CNT:3; /**< \brief [18:16] Stack pointer counter value (r) */
+ Ifx_Strict_32Bit reserved_19:13; /**< \brief \internal Reserved */
+} Ifx_GTM_MCS_CH_CTRL_Bits;
+
+/** \brief MCS_Channel Error Interrupt Enable Register */
+typedef struct _Ifx_GTM_MCS_CH_EIRQ_EN_Bits
+{
+ Ifx_Strict_32Bit MCS_EIRQ_EN:1; /**< \brief [0:0] MCS channel x MCS_EIRQ error interrupt enable (rw) */
+ Ifx_Strict_32Bit STK_ERR_EIRQ_EN:1; /**< \brief [1:1] MCS channel x STK_ERR_IRQ error interrupt enable (rw) */
+ Ifx_Strict_32Bit MEM_ERR_EIRQ_EN:1; /**< \brief [2:2] MCS channel x MEM_ERR_EIRQ error interrupt enable (rw) */
+ Ifx_Strict_32Bit reserved_3:29; /**< \brief \internal Reserved */
+} Ifx_GTM_MCS_CH_EIRQ_EN_Bits;
+
+/** \brief MCS Channel Interrupt Enable Register */
+typedef struct _Ifx_GTM_MCS_CH_IRQ_EN_Bits
+{
+ Ifx_Strict_32Bit MCS_IRQ_EN:1; /**< \brief [0:0] MCS channel x MCS_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit STK_ERR_IRQ_EN:1; /**< \brief [1:1] MCS channel x STK_ERR_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit MEM_ERR_IRQ_EN:1; /**< \brief [2:2] MCS channel x MEM_ERR_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit reserved_3:29; /**< \brief \internal Reserved */
+} Ifx_GTM_MCS_CH_IRQ_EN_Bits;
+
+/** \brief MCS Channel Software Interrupt Generation Register */
+typedef struct _Ifx_GTM_MCS_CH_IRQ_FORCINT_Bits
+{
+ Ifx_Strict_32Bit TRG_MCS_IRQ:1; /**< \brief [0:0] Trigger IRQ bit in MCS_CH_x_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit TRG_STK_ERR_IRQ:1; /**< \brief [1:1] Trigger IRQ bit in MCS_CH_x_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit TRG_MEM_ERR_IRQ:1; /**< \brief [2:2] Trigger IRQ bit in MCS_CH_x_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit reserved_3:29; /**< \brief \internal Reserved */
+} Ifx_GTM_MCS_CH_IRQ_FORCINT_Bits;
+
+/** \brief MCS IRQ Mode Configuration Register */
+typedef struct _Ifx_GTM_MCS_CH_IRQ_MODE_Bits
+{
+ Ifx_Strict_32Bit IRQ_MODE:2; /**< \brief [1:0] IRQ mode selection (rw) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_GTM_MCS_CH_IRQ_MODE_Bits;
+
+/** \brief MCS Channel interrupt notification register */
+typedef struct _Ifx_GTM_MCS_CH_IRQ_NOTIFY_Bits
+{
+ Ifx_Strict_32Bit MCS_IRQ:1; /**< \brief [0:0] Interrupt request by MCS-channel x (rwh) */
+ Ifx_Strict_32Bit STK_ERR_IRQ:1; /**< \brief [1:1] Stack counter overflow/underflow of channel x (rwh) */
+ Ifx_Strict_32Bit MEM_ERR_IRQ:1; /**< \brief [2:2] Memory access out of range in channel x (rwh) */
+ Ifx_Strict_32Bit reserved_3:29; /**< \brief \internal Reserved */
+} Ifx_GTM_MCS_CH_IRQ_NOTIFY_Bits;
+
+/** \brief MCS Channel Program Counter Register */
+typedef struct _Ifx_GTM_MCS_CH_PC_Bits
+{
+ Ifx_Strict_32Bit PC:14; /**< \brief [13:0] Current Program Counter (rw) */
+ Ifx_Strict_32Bit reserved_14:18; /**< \brief \internal Reserved */
+} Ifx_GTM_MCS_CH_PC_Bits;
+
+/** \brief MCS Channel Program Counter Register 0 */
+typedef struct _Ifx_GTM_MCS_CH_R0_Bits
+{
+ Ifx_Strict_32Bit DATA:24; /**< \brief [23:0] Data of MCS general purpose register ry (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_MCS_CH_R0_Bits;
+
+/** \brief MCS Channel Program Counter Register 1 */
+typedef struct _Ifx_GTM_MCS_CH_R1_Bits
+{
+ Ifx_Strict_32Bit DATA:24; /**< \brief [23:0] Data of MCS general purpose register ry (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_MCS_CH_R1_Bits;
+
+/** \brief MCS Channel Program Counter Register 2 */
+typedef struct _Ifx_GTM_MCS_CH_R2_Bits
+{
+ Ifx_Strict_32Bit DATA:24; /**< \brief [23:0] Data of MCS general purpose register ry (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_MCS_CH_R2_Bits;
+
+/** \brief MCS Channel Program Counter Register 3 */
+typedef struct _Ifx_GTM_MCS_CH_R3_Bits
+{
+ Ifx_Strict_32Bit DATA:24; /**< \brief [23:0] Data of MCS general purpose register ry (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_MCS_CH_R3_Bits;
+
+/** \brief MCS Channel Program Counter Register 4 */
+typedef struct _Ifx_GTM_MCS_CH_R4_Bits
+{
+ Ifx_Strict_32Bit DATA:24; /**< \brief [23:0] Data of MCS general purpose register ry (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_MCS_CH_R4_Bits;
+
+/** \brief MCS Channel Program Counter Register 5 */
+typedef struct _Ifx_GTM_MCS_CH_R5_Bits
+{
+ Ifx_Strict_32Bit DATA:24; /**< \brief [23:0] Data of MCS general purpose register ry (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_MCS_CH_R5_Bits;
+
+/** \brief MCS Channel Program Counter Register 6 */
+typedef struct _Ifx_GTM_MCS_CH_R6_Bits
+{
+ Ifx_Strict_32Bit DATA:24; /**< \brief [23:0] Data of MCS general purpose register ry (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_MCS_CH_R6_Bits;
+
+/** \brief MCS Channel Program Counter Register 7 */
+typedef struct _Ifx_GTM_MCS_CH_R7_Bits
+{
+ Ifx_Strict_32Bit DATA:24; /**< \brief [23:0] Data of MCS general purpose register ry (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_MCS_CH_R7_Bits;
+
+/** \brief MCS Control Register */
+typedef struct _Ifx_GTM_MCS_CTRL_Bits
+{
+ Ifx_Strict_32Bit SCHED:1; /**< \brief [0:0] MCS submodule scheduling scheme (rw) */
+ Ifx_Strict_32Bit HLT_SP_OFL:1; /**< \brief [1:1] Halt on stack pointer overflow (rw) */
+ Ifx_Strict_32Bit reserved_2:14; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit RAM_RST:1; /**< \brief [16:16] RAM reset bit (r) */
+ Ifx_Strict_32Bit reserved_17:15; /**< \brief \internal Reserved */
+} Ifx_GTM_MCS_CTRL_Bits;
+
+/** \brief MCS Error Register */
+typedef struct _Ifx_GTM_MCS_ERR_Bits
+{
+ Ifx_Strict_32Bit ERR0:1; /**< \brief [0:0] Error State of MCS-channel 0 (rwh) */
+ Ifx_Strict_32Bit ERR1:1; /**< \brief [1:1] Error State of MCS-channel 1 (rwh) */
+ Ifx_Strict_32Bit ERR2:1; /**< \brief [2:2] Error State of MCS-channel 2 (rwh) */
+ Ifx_Strict_32Bit ERR3:1; /**< \brief [3:3] Error State of MCS-channel3 (rwh) */
+ Ifx_Strict_32Bit ERR4:1; /**< \brief [4:4] Error State of MCS-channel 4 (rwh) */
+ Ifx_Strict_32Bit ERR5:1; /**< \brief [5:5] Error State of MCS-channel 5 (rwh) */
+ Ifx_Strict_32Bit ERR6:1; /**< \brief [6:6] Error State of MCS-channel 6 (rwh) */
+ Ifx_Strict_32Bit ERR7:1; /**< \brief [7:7] Error State of MCS-channel 7 (rwh) */
+ Ifx_Strict_32Bit reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_GTM_MCS_ERR_Bits;
+
+/** \brief MCS Channel Reset Register */
+typedef struct _Ifx_GTM_MCS_RST_Bits
+{
+ Ifx_Strict_32Bit RST0:1; /**< \brief [0:0] Software reset of channel 0 (w) */
+ Ifx_Strict_32Bit RST1:1; /**< \brief [1:1] Software reset of channel 1 (w) */
+ Ifx_Strict_32Bit RST2:1; /**< \brief [2:2] Software reset of channel 2 (w) */
+ Ifx_Strict_32Bit RST3:1; /**< \brief [3:3] Software reset of channel 3 (w) */
+ Ifx_Strict_32Bit RST4:1; /**< \brief [4:4] Software reset of channel 4 (w) */
+ Ifx_Strict_32Bit RST5:1; /**< \brief [5:5] Software reset of channel 5 (w) */
+ Ifx_Strict_32Bit RST6:1; /**< \brief [6:6] Software reset of channel 6 (w) */
+ Ifx_Strict_32Bit RST7:1; /**< \brief [7:7] Software reset of channel 7 (w) */
+ Ifx_Strict_32Bit CAT0:1; /**< \brief [8:8] Cancel ARU transfer for channel 0 (rwh) */
+ Ifx_Strict_32Bit CAT1:1; /**< \brief [9:9] Cancel ARU transfer for channel 1 (rwh) */
+ Ifx_Strict_32Bit CAT2:1; /**< \brief [10:10] Cancel ARU transfer for channel 2 (rwh) */
+ Ifx_Strict_32Bit CAT3:1; /**< \brief [11:11] Cancel ARU transfer for channel 3 (rwh) */
+ Ifx_Strict_32Bit CAT4:1; /**< \brief [12:12] Cancel ARU transfer for channel 4 (rwh) */
+ Ifx_Strict_32Bit CAT5:1; /**< \brief [13:13] Cancel ARU transfer for channel 5 (rwh) */
+ Ifx_Strict_32Bit CAT6:1; /**< \brief [14:14] Cancel ARU transfer for channel 6 (rwh) */
+ Ifx_Strict_32Bit CAT7:1; /**< \brief [15:15] Cancel ARU transfer for channel 7 (rwh) */
+ Ifx_Strict_32Bit CWT0:1; /**< \brief [16:16] Cancel WURM instruction for channel 0 (rwh) */
+ Ifx_Strict_32Bit CWT1:1; /**< \brief [17:17] Cancel WURM instruction for channel 1 (rwh) */
+ Ifx_Strict_32Bit CWT2:1; /**< \brief [18:18] Cancel WURM instruction for channel 2 (rwh) */
+ Ifx_Strict_32Bit CWT3:1; /**< \brief [19:19] Cancel WURM instruction for channel 3 (rwh) */
+ Ifx_Strict_32Bit CWT4:1; /**< \brief [20:20] Cancel WURM instruction for channel 4 (rwh) */
+ Ifx_Strict_32Bit CWT5:1; /**< \brief [21:21] Cancel WURM instruction for channel 5 (rwh) */
+ Ifx_Strict_32Bit CWT6:1; /**< \brief [22:22] Cancel WURM instruction for channel 6 (rwh) */
+ Ifx_Strict_32Bit CWT7:1; /**< \brief [23:23] Cancel WURM instruction for channel 7 (rwh) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_MCS_RST_Bits;
+
+/** \brief MCS Interrupt Clear Register */
+typedef struct _Ifx_GTM_MCSINTCLR_Bits
+{
+ Ifx_Strict_32Bit MCS000:1; /**< \brief [0:0] MCS0 RAM0 Interrupt 0 Status Clear (w) */
+ Ifx_Strict_32Bit MCS001:1; /**< \brief [1:1] MCS0 RAM0 Interrupt 1 Status Clear (w) */
+ Ifx_Strict_32Bit MCS010:1; /**< \brief [2:2] MCS0 RAM1 Interrupt 0 Status Clear (w) */
+ Ifx_Strict_32Bit MCS011:1; /**< \brief [3:3] MCS0 RAM1 Interrupt 1 Status Clear (w) */
+ Ifx_Strict_32Bit MCS100:1; /**< \brief [4:4] MCS1 RAM0 Interrupt 0 Status Clear (w) */
+ Ifx_Strict_32Bit MCS101:1; /**< \brief [5:5] MCS1 RAM0 Interrupt 1 Status Clear (w) */
+ Ifx_Strict_32Bit MCS110:1; /**< \brief [6:6] MCS1 RAM1 Interrupt 0 Status Clear (w) */
+ Ifx_Strict_32Bit MCS111:1; /**< \brief [7:7] MCS1 RAM1 Interrupt 1 Status Clear (w) */
+ Ifx_Strict_32Bit MCS200:1; /**< \brief [8:8] MCS2 RAM0 Interrupt 0 Status Clear (w) */
+ Ifx_Strict_32Bit MCS201:1; /**< \brief [9:9] MCS2 RAM0 Interrupt 1 Status Clear (w) */
+ Ifx_Strict_32Bit MCS210:1; /**< \brief [10:10] MCS2 RAM1 Interrupt 0 Status Clear (w) */
+ Ifx_Strict_32Bit MCS211:1; /**< \brief [11:11] MCS2 RAM1 Interrupt 1 Status Clear (w) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_GTM_MCSINTCLR_Bits;
+
+/** \brief MCS Interrupt Status Register */
+typedef struct _Ifx_GTM_MCSINTSTAT_Bits
+{
+ Ifx_Strict_32Bit MCS000:1; /**< \brief [0:0] MCS0 RAM0 Interrupt 0 Status (rh) */
+ Ifx_Strict_32Bit MCS001:1; /**< \brief [1:1] MCS0 RAM0 Interrupt 1 Status (rh) */
+ Ifx_Strict_32Bit MCS010:1; /**< \brief [2:2] MCS0 RAM1 Interrupt 0 Status (rh) */
+ Ifx_Strict_32Bit MCS011:1; /**< \brief [3:3] MCS0 RAM1 Interrupt 1 Status (rh) */
+ Ifx_Strict_32Bit MCS100:1; /**< \brief [4:4] MCS1 RAM0 Interrupt 0 Status (rh) */
+ Ifx_Strict_32Bit MCS101:1; /**< \brief [5:5] MCS1 RAM0 Interrupt 1 Status (rh) */
+ Ifx_Strict_32Bit MCS110:1; /**< \brief [6:6] MCS1 RAM1 Interrupt 0 Status (rh) */
+ Ifx_Strict_32Bit MCS111:1; /**< \brief [7:7] MCS1 RAM1 Interrupt 1 Status (rh) */
+ Ifx_Strict_32Bit MCS200:1; /**< \brief [8:8] MCS2 RAM0 Interrupt 0 Status (rh) */
+ Ifx_Strict_32Bit MCS201:1; /**< \brief [9:9] MCS2 RAM0 Interrupt 1 Status (rh) */
+ Ifx_Strict_32Bit MCS210:1; /**< \brief [10:10] MCS2 RAM1 Interrupt 0 Status (rh) */
+ Ifx_Strict_32Bit MCS211:1; /**< \brief [11:11] MCS2 RAM1 Interrupt 1 Status (rh) */
+ Ifx_Strict_32Bit reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_GTM_MCSINTSTAT_Bits;
+
+/** \brief Monitor Activity Register 0 */
+typedef struct _Ifx_GTM_MON_ACTIVITY_0_Bits
+{
+ Ifx_Strict_32Bit MCA_0_0:1; /**< \brief [0:0] Activity of check performed in module MCS0 at channel 0 (rwh) */
+ Ifx_Strict_32Bit MCA_0_1:1; /**< \brief [1:1] Activity of check performed in module MCS0 at channel 1 (rwh) */
+ Ifx_Strict_32Bit MCA_0_2:1; /**< \brief [2:2] Activity of check performed in module MCS0 at channel 2 (rwh) */
+ Ifx_Strict_32Bit MCA_0_3:1; /**< \brief [3:3] Activity of check performed in module MCS0 at channel 3 (rwh) */
+ Ifx_Strict_32Bit MCA_0_4:1; /**< \brief [4:4] Activity of check performed in module MCS0 at channel 4 (rwh) */
+ Ifx_Strict_32Bit MCA_0_5:1; /**< \brief [5:5] Activity of check performed in module MCS0 at channel 5 (rwh) */
+ Ifx_Strict_32Bit MCA_0_6:1; /**< \brief [6:6] Activity of check performed in module MCS0 at channel 6 (rwh) */
+ Ifx_Strict_32Bit MCA_0_7:1; /**< \brief [7:7] Activity of check performed in module MCS0 at channel 7 (rwh) */
+ Ifx_Strict_32Bit MCA_1_0:1; /**< \brief [8:8] Activity of check performed in module MCS1 at channel 0 (rwh) */
+ Ifx_Strict_32Bit MCA_1_1:1; /**< \brief [9:9] Activity of check performed in module MCS1 at channel 1 (rwh) */
+ Ifx_Strict_32Bit MCA_1_2:1; /**< \brief [10:10] Activity of check performed in module MCS1 at channel 2 (rwh) */
+ Ifx_Strict_32Bit MCA_1_3:1; /**< \brief [11:11] Activity of check performed in module MCS1 at channel 3 (rwh) */
+ Ifx_Strict_32Bit MCA_1_4:1; /**< \brief [12:12] Activity of check performed in module MCS1 at channel 4 (rwh) */
+ Ifx_Strict_32Bit MCA_1_5:1; /**< \brief [13:13] Activity of check performed in module MCS1 at channel 5 (rwh) */
+ Ifx_Strict_32Bit MCA_1_6:1; /**< \brief [14:14] Activity of check performed in module MCS1 at channel 6 (rwh) */
+ Ifx_Strict_32Bit MCA_1_7:1; /**< \brief [15:15] Activity of check performed in module MCS1 at channel 7 (rwh) */
+ Ifx_Strict_32Bit MCA_2_0:1; /**< \brief [16:16] Activity of check performed in module MCS2 at channel 0 (rwh) */
+ Ifx_Strict_32Bit MCA_2_1:1; /**< \brief [17:17] Activity of check performed in module MCS2 at channel 1 (rwh) */
+ Ifx_Strict_32Bit MCA_2_2:1; /**< \brief [18:18] Activity of check performed in module MCS2 at channel 2 (rwh) */
+ Ifx_Strict_32Bit MCA_2_3:1; /**< \brief [19:19] Activity of check performed in module MCS2 at channel 3 (rwh) */
+ Ifx_Strict_32Bit MCA_2_4:1; /**< \brief [20:20] Activity of check performed in module MCS2 at channel 4 (rwh) */
+ Ifx_Strict_32Bit MCA_2_5:1; /**< \brief [21:21] Activity of check performed in module MCS2 at channel 5 (rwh) */
+ Ifx_Strict_32Bit MCA_2_6:1; /**< \brief [22:22] Activity of check performed in module MCS2 at channel 6 (rwh) */
+ Ifx_Strict_32Bit MCA_2_7:1; /**< \brief [23:23] Activity of check performed in module MCS2 at channel 7 (rwh) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_MON_ACTIVITY_0_Bits;
+
+/** \brief Monitor Status Register */
+typedef struct _Ifx_GTM_MON_STATUS_Bits
+{
+ Ifx_Strict_32Bit ACT_CMU0:1; /**< \brief [0:0] CMU_CLK0 activity (rwh) */
+ Ifx_Strict_32Bit ACT_CMU1:1; /**< \brief [1:1] CMU_CLK1 activity (rwh) */
+ Ifx_Strict_32Bit ACT_CMU2:1; /**< \brief [2:2] CMU_CLK2 activity (rwh) */
+ Ifx_Strict_32Bit ACT_CMU3:1; /**< \brief [3:3] CMU_CLK3 activity (rwh) */
+ Ifx_Strict_32Bit ACT_CMU4:1; /**< \brief [4:4] CMU_CLK4 activity (rwh) */
+ Ifx_Strict_32Bit ACT_CMU5:1; /**< \brief [5:5] CMU_CLK5 activity (rwh) */
+ Ifx_Strict_32Bit ACT_CMU6:1; /**< \brief [6:6] CMU_CLK6 activity (rwh) */
+ Ifx_Strict_32Bit ACT_CMU7:1; /**< \brief [7:7] CMU_CLK7 activity (rwh) */
+ Ifx_Strict_32Bit ACT_CMUFX0:1; /**< \brief [8:8] CMU_CLKFX0 activity (rwh) */
+ Ifx_Strict_32Bit ACT_CMUFX1:1; /**< \brief [9:9] CMU_CLKFX1 activity (rwh) */
+ Ifx_Strict_32Bit ACT_CMUFX2:1; /**< \brief [10:10] CMU_CLKFX2 activity (rwh) */
+ Ifx_Strict_32Bit ACT_CMUFX3:1; /**< \brief [11:11] CMU_CLKFX3 activity (rwh) */
+ Ifx_Strict_32Bit ACT_CMUFX4:1; /**< \brief [12:12] CMU_CLKFX4 activity (rwh) */
+ Ifx_Strict_32Bit reserved_13:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit CMP_ERR:1; /**< \brief [16:16] Error detected at CMP (r) */
+ Ifx_Strict_32Bit reserved_17:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit MCS0_ERR:1; /**< \brief [20:20] Error detected at MCS[0] (r) */
+ Ifx_Strict_32Bit MCS1_ERR:1; /**< \brief [21:21] Error detected at MCS[1] (r) */
+ Ifx_Strict_32Bit MCS2_ERR:1; /**< \brief [22:22] Error detected at MCS[2] (r) */
+ Ifx_Strict_32Bit reserved_23:9; /**< \brief \internal Reserved */
+} Ifx_GTM_MON_STATUS_Bits;
+
+/** \brief MSC0 Input Low Extended Control Register */
+typedef struct _Ifx_GTM_MSC0INLEXTCON_Bits
+{
+ Ifx_Strict_32Bit SEL0:2; /**< \brief [1:0] GTM MSC0 Low Extended 0 Output Selection (rw) */
+ Ifx_Strict_32Bit SEL1:2; /**< \brief [3:2] GTM MSC0 Low Extended 1 Output Selection (rw) */
+ Ifx_Strict_32Bit SEL2:2; /**< \brief [5:4] GTM MSC0 Low Extended 2 Output Selection (rw) */
+ Ifx_Strict_32Bit SEL3:2; /**< \brief [7:6] GTM MSC0 Low Extended 3 Output Selection (rw) */
+ Ifx_Strict_32Bit SEL4:2; /**< \brief [9:8] GTM MSC0 Low Extended 4 Output Selection (rw) */
+ Ifx_Strict_32Bit SEL5:2; /**< \brief [11:10] GTM MSC0 Low Extended 5 Output Selection (rw) */
+ Ifx_Strict_32Bit SEL6:2; /**< \brief [13:12] GTM MSC0 Low Extended 6 Output Selection (rw) */
+ Ifx_Strict_32Bit SEL7:2; /**< \brief [15:14] GTM MSC0 Low Extended 7 Output Selection (rw) */
+ Ifx_Strict_32Bit SEL8:2; /**< \brief [17:16] GTM MSC0 Low Extended 8 Output Selection (rw) */
+ Ifx_Strict_32Bit SEL9:2; /**< \brief [19:18] GTM MSC0 Low Extended 9 Output Selection (rw) */
+ Ifx_Strict_32Bit SEL10:2; /**< \brief [21:20] GTM MSC0 Low Extended 10 Output Selection (rw) */
+ Ifx_Strict_32Bit SEL11:2; /**< \brief [23:22] GTM MSC0 Low Extended 11 Output Selection (rw) */
+ Ifx_Strict_32Bit SEL12:2; /**< \brief [25:24] GTM MSC0 Low Extended 12 Output Selection (rw) */
+ Ifx_Strict_32Bit SEL13:2; /**< \brief [27:26] GTM MSC0 Low Extended 13 Output Selection (rw) */
+ Ifx_Strict_32Bit SEL14:2; /**< \brief [29:28] GTM MSC0 Low Extended 14 Output Selection (rw) */
+ Ifx_Strict_32Bit SEL15:2; /**< \brief [31:30] GTM MSC0 Low Extended 15 Output Selection (rw) */
+} Ifx_GTM_MSC0INLEXTCON_Bits;
+
+/** \brief MSC Input High Control Register */
+typedef struct _Ifx_GTM_MSCIN_INHCON_Bits
+{
+ Ifx_Strict_32Bit SEL0:2; /**< \brief [1:0] (rw) */
+ Ifx_Strict_32Bit SEL1:2; /**< \brief [3:2] (rw) */
+ Ifx_Strict_32Bit SEL2:2; /**< \brief [5:4] (rw) */
+ Ifx_Strict_32Bit SEL3:2; /**< \brief [7:6] (rw) */
+ Ifx_Strict_32Bit SEL4:2; /**< \brief [9:8] (rw) */
+ Ifx_Strict_32Bit SEL5:2; /**< \brief [11:10] (rw) */
+ Ifx_Strict_32Bit SEL6:2; /**< \brief [13:12] (rw) */
+ Ifx_Strict_32Bit SEL7:2; /**< \brief [15:14] (rw) */
+ Ifx_Strict_32Bit SEL8:2; /**< \brief [17:16] (rw) */
+ Ifx_Strict_32Bit SEL9:2; /**< \brief [19:18] (rw) */
+ Ifx_Strict_32Bit SEL10:2; /**< \brief [21:20] (rw) */
+ Ifx_Strict_32Bit SEL11:2; /**< \brief [23:22] (rw) */
+ Ifx_Strict_32Bit SEL12:2; /**< \brief [25:24] (rw) */
+ Ifx_Strict_32Bit SEL13:2; /**< \brief [27:26] (rw) */
+ Ifx_Strict_32Bit SEL14:2; /**< \brief [29:28] (rw) */
+ Ifx_Strict_32Bit SEL15:2; /**< \brief [31:30] (rw) */
+} Ifx_GTM_MSCIN_INHCON_Bits;
+
+/** \brief MSC Input Low Control Register */
+typedef struct _Ifx_GTM_MSCIN_INLCON_Bits
+{
+ Ifx_Strict_32Bit SEL0:2; /**< \brief [1:0] (rw) */
+ Ifx_Strict_32Bit SEL1:2; /**< \brief [3:2] (rw) */
+ Ifx_Strict_32Bit SEL2:2; /**< \brief [5:4] (rw) */
+ Ifx_Strict_32Bit SEL3:2; /**< \brief [7:6] (rw) */
+ Ifx_Strict_32Bit SEL4:2; /**< \brief [9:8] (rw) */
+ Ifx_Strict_32Bit SEL5:2; /**< \brief [11:10] (rw) */
+ Ifx_Strict_32Bit SEL6:2; /**< \brief [13:12] (rw) */
+ Ifx_Strict_32Bit SEL7:2; /**< \brief [15:14] (rw) */
+ Ifx_Strict_32Bit SEL8:2; /**< \brief [17:16] (rw) */
+ Ifx_Strict_32Bit SEL9:2; /**< \brief [19:18] (rw) */
+ Ifx_Strict_32Bit SEL10:2; /**< \brief [21:20] (rw) */
+ Ifx_Strict_32Bit SEL11:2; /**< \brief [23:22] (rw) */
+ Ifx_Strict_32Bit SEL12:2; /**< \brief [25:24] (rw) */
+ Ifx_Strict_32Bit SEL13:2; /**< \brief [27:26] (rw) */
+ Ifx_Strict_32Bit SEL14:2; /**< \brief [29:28] (rw) */
+ Ifx_Strict_32Bit SEL15:2; /**< \brief [31:30] (rw) */
+} Ifx_GTM_MSCIN_INLCON_Bits;
+
+/** \brief MSC Set Control 0 Register */
+typedef struct _Ifx_GTM_MSCSET_CON0_Bits
+{
+ Ifx_Strict_32Bit SEL0:5; /**< \brief [4:0] (rw) */
+ Ifx_Strict_32Bit reserved_5:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SEL1:5; /**< \brief [12:8] (rw) */
+ Ifx_Strict_32Bit reserved_13:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SEL2:5; /**< \brief [20:16] (rw) */
+ Ifx_Strict_32Bit reserved_21:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SEL3:5; /**< \brief [28:24] (rw) */
+ Ifx_Strict_32Bit reserved_29:3; /**< \brief \internal Reserved */
+} Ifx_GTM_MSCSET_CON0_Bits;
+
+/** \brief MSC Set Control 1 Register */
+typedef struct _Ifx_GTM_MSCSET_CON1_Bits
+{
+ Ifx_Strict_32Bit SEL4:5; /**< \brief [4:0] (rw) */
+ Ifx_Strict_32Bit reserved_5:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SEL5:5; /**< \brief [12:8] (rw) */
+ Ifx_Strict_32Bit reserved_13:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SEL6:5; /**< \brief [20:16] (rw) */
+ Ifx_Strict_32Bit reserved_21:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SEL7:5; /**< \brief [28:24] (rw) */
+ Ifx_Strict_32Bit reserved_29:3; /**< \brief \internal Reserved */
+} Ifx_GTM_MSCSET_CON1_Bits;
+
+/** \brief MSC Set Control 2 Register */
+typedef struct _Ifx_GTM_MSCSET_CON2_Bits
+{
+ Ifx_Strict_32Bit SEL8:5; /**< \brief [4:0] (rw) */
+ Ifx_Strict_32Bit reserved_5:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SEL9:5; /**< \brief [12:8] (rw) */
+ Ifx_Strict_32Bit reserved_13:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SEL10:5; /**< \brief [20:16] (rw) */
+ Ifx_Strict_32Bit reserved_21:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SEL11:5; /**< \brief [28:24] (rw) */
+ Ifx_Strict_32Bit reserved_29:3; /**< \brief \internal Reserved */
+} Ifx_GTM_MSCSET_CON2_Bits;
+
+/** \brief MSC Set Control 3 Register */
+typedef struct _Ifx_GTM_MSCSET_CON3_Bits
+{
+ Ifx_Strict_32Bit SEL12:5; /**< \brief [4:0] (rw) */
+ Ifx_Strict_32Bit reserved_5:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SEL13:5; /**< \brief [12:8] (rw) */
+ Ifx_Strict_32Bit reserved_13:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SEL14:5; /**< \brief [20:16] (rw) */
+ Ifx_Strict_32Bit reserved_21:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SEL15:5; /**< \brief [28:24] (rw) */
+ Ifx_Strict_32Bit reserved_29:3; /**< \brief \internal Reserved */
+} Ifx_GTM_MSCSET_CON3_Bits;
+
+/** \brief OCDS Control and Status */
+typedef struct _Ifx_GTM_OCS_Bits
+{
+ Ifx_Strict_32Bit reserved_0:24; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SUS:4; /**< \brief [27:24] OCDS Suspend Control (rw) */
+ Ifx_Strict_32Bit SUS_P:1; /**< \brief [28:28] SUS Write Protection (w) */
+ Ifx_Strict_32Bit SUSSTA:1; /**< \brief [29:29] Suspend State (rh) */
+ Ifx_Strict_32Bit reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_GTM_OCS_Bits;
+
+/** \brief OCDS Debug Access Register */
+typedef struct _Ifx_GTM_ODA_Bits
+{
+ Ifx_Strict_32Bit DDREN:1; /**< \brief [0:0] Detructive Debug Read Enable (rw) */
+ Ifx_Strict_32Bit DREN:1; /**< \brief [1:1] Detructive Read Enable (rw) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_GTM_ODA_Bits;
+
+/** \brief OCDS TBU0 Trigger Register */
+typedef struct _Ifx_GTM_OTBU0T_Bits
+{
+ Ifx_Strict_32Bit CV:27; /**< \brief [26:0] Compare Value (rw) */
+ Ifx_Strict_32Bit reserved_27:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit CM:2; /**< \brief [29:28] Compare Mode (rw) */
+ Ifx_Strict_32Bit reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_GTM_OTBU0T_Bits;
+
+/** \brief OCDS TBU1 Trigger Register */
+typedef struct _Ifx_GTM_OTBU1T_Bits
+{
+ Ifx_Strict_32Bit CV:24; /**< \brief [23:0] Compare Value (rw) */
+ Ifx_Strict_32Bit reserved_24:4; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit EN:1; /**< \brief [28:28] Enable (rw) */
+ Ifx_Strict_32Bit reserved_29:3; /**< \brief \internal Reserved */
+} Ifx_GTM_OTBU1T_Bits;
+
+/** \brief OCDS TBU2 Trigger Register */
+typedef struct _Ifx_GTM_OTBU2T_Bits
+{
+ Ifx_Strict_32Bit CV:24; /**< \brief [23:0] Compare Value (rw) */
+ Ifx_Strict_32Bit reserved_24:4; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit EN:1; /**< \brief [28:28] Enable (rw) */
+ Ifx_Strict_32Bit reserved_29:3; /**< \brief \internal Reserved */
+} Ifx_GTM_OTBU2T_Bits;
+
+/** \brief OCDS Trigger Set Control 0 Register */
+typedef struct _Ifx_GTM_OTSC0_Bits
+{
+ Ifx_Strict_32Bit B0LMT:3; /**< \brief [2:0] OTGB0 TS16_IOS Low Byte Module Type (rw) */
+ Ifx_Strict_32Bit reserved_3:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit B0LMI:4; /**< \brief [7:4] OTGB0 TS16_IOS Low Byte Module Instance (rw) */
+ Ifx_Strict_32Bit B0HMT:3; /**< \brief [10:8] OTGB0 TS16_IOS High Byte Module Type (rw) */
+ Ifx_Strict_32Bit reserved_11:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit B0HMI:4; /**< \brief [15:12] OTGB0 TS16_IOS High Byte Module Instance (rw) */
+ Ifx_Strict_32Bit B1LMT:3; /**< \brief [18:16] OTGB1 TS16_IOS Low Byte Module Type (rw) */
+ Ifx_Strict_32Bit reserved_19:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit B1LMI:4; /**< \brief [23:20] OTGB1 TS16_IOS Low Byte Module Instance (rw) */
+ Ifx_Strict_32Bit B1HMT:3; /**< \brief [26:24] OTGB1 TS16_IOS High Byte Module Type (rw) */
+ Ifx_Strict_32Bit reserved_27:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit B1HMI:4; /**< \brief [31:28] OTGB1 TS16_IOS High Byte Module Instance (rw) */
+} Ifx_GTM_OTSC0_Bits;
+
+/** \brief OCDS Trigger Set Control 1 Register */
+typedef struct _Ifx_GTM_OTSC1_Bits
+{
+ Ifx_Strict_32Bit MCS:4; /**< \brief [3:0] MCS Channel Select (rw) */
+ Ifx_Strict_32Bit MI:4; /**< \brief [7:4] MCS Instance (rw) */
+ Ifx_Strict_32Bit reserved_8:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit MOE:1; /**< \brief [9:9] MCS Opcode Trace Enable (rw) */
+ Ifx_Strict_32Bit reserved_10:22; /**< \brief \internal Reserved */
+} Ifx_GTM_OTSC1_Bits;
+
+/** \brief OCDS Trigger Set Select Register */
+typedef struct _Ifx_GTM_OTSS_Bits
+{
+ Ifx_Strict_32Bit OTGB0:4; /**< \brief [3:0] Trigger Set for OTGB0 (rw) */
+ Ifx_Strict_32Bit reserved_4:4; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit OTGB1:4; /**< \brief [11:8] Trigger Set for OTGB1 (rw) */
+ Ifx_Strict_32Bit reserved_12:4; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit OTGB2:4; /**< \brief [19:16] Trigger Set for OTGB2 (rw) */
+ Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_GTM_OTSS_Bits;
+
+/** \brief GTM Version Control Register */
+typedef struct _Ifx_GTM_REV_Bits
+{
+ Ifx_Strict_32Bit STEP:8; /**< \brief [7:0] Release Step (r) */
+ Ifx_Strict_32Bit NO:4; /**< \brief [11:8] Define delivery number of GTM specification (r) */
+ Ifx_Strict_32Bit MINOR:4; /**< \brief [15:12] Define minor version number of GTM specification (r) */
+ Ifx_Strict_32Bit MAJOR:4; /**< \brief [19:16] Define major version number of GTM specification (r) */
+ Ifx_Strict_32Bit DEV_CODE0:4; /**< \brief [23:20] Device encoding digit 0 (r) */
+ Ifx_Strict_32Bit DEV_CODE1:4; /**< \brief [27:24] Device encoding digit 1 (r) */
+ Ifx_Strict_32Bit DEV_CODE2:4; /**< \brief [31:28] Device encoding digit 2 (r) */
+} Ifx_GTM_REV_Bits;
+
+/** \brief GTM Global Reset Register */
+typedef struct _Ifx_GTM_RST_Bits
+{
+ Ifx_Strict_32Bit RST:1; /**< \brief [0:0] GTM Reset (w) */
+ Ifx_Strict_32Bit reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_GTM_RST_Bits;
+
+/** \brief SPE Revolution Compare Register */
+typedef struct _Ifx_GTM_SPE_CMP_Bits
+{
+ Ifx_Strict_32Bit CMP:24; /**< \brief [23:0] Input signal revolution counter compare value (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_SPE_CMP_Bits;
+
+/** \brief SPE Revolution Counter Register */
+typedef struct _Ifx_GTM_SPE_CNT_Bits
+{
+ Ifx_Strict_32Bit CNT:24; /**< \brief [23:0] Input signal revolution counter (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_SPE_CNT_Bits;
+
+/** \brief SPE Control Status Register */
+typedef struct _Ifx_GTM_SPE_CTRL_STAT_Bits
+{
+ Ifx_Strict_32Bit SPE_EN:1; /**< \brief [0:0] SPE Submodule enable (rw) */
+ Ifx_Strict_32Bit SIE0:1; /**< \brief [1:1] SPE Input enable for TIM_CHx(48) (rw) */
+ Ifx_Strict_32Bit SIE1:1; /**< \brief [2:2] SPE Input enable for TIM_CHy(48) (rw) */
+ Ifx_Strict_32Bit SIE2:1; /**< \brief [3:3] SPE Input enable for TIM_CHz(48) (rw) */
+ Ifx_Strict_32Bit TRIG_SEL:2; /**< \brief [5:4] Select trigger input signal (rw) */
+ Ifx_Strict_32Bit TIM_SEL:1; /**< \brief [6:6] select TIM input signal (rw) */
+ Ifx_Strict_32Bit FSOM:1; /**< \brief [7:7] Fast Shut-Off Mode (rw) */
+ Ifx_Strict_32Bit SPE_PAT_PTR:3; /**< \brief [10:8] Pattern selector for TOM output signals (rw) */
+ Ifx_Strict_32Bit reserved_11:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit AIP:3; /**< \brief [14:12] Actual input pattern that was detected by a regular input pattern change (rw) */
+ Ifx_Strict_32Bit ADIR:1; /**< \brief [15:15] Actual rotation direction (rw) */
+ Ifx_Strict_32Bit PIP:3; /**< \brief [18:16] Previous input pattern that was detected by a regular input pattern change (rw) */
+ Ifx_Strict_32Bit PDIR:1; /**< \brief [19:19] Previous rotation direction (rw) */
+ Ifx_Strict_32Bit NIP:3; /**< \brief [22:20] New input pattern that was detected (r) */
+ Ifx_Strict_32Bit reserved_23:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit FSOL:8; /**< \brief [31:24] Fast Shut-Off Level for TOM[i] channel 0 to 7 (rw) */
+} Ifx_GTM_SPE_CTRL_STAT_Bits;
+
+/** \brief SPE Error Interrupt Enable Register */
+typedef struct _Ifx_GTM_SPE_EIRQ_EN_Bits
+{
+ Ifx_Strict_32Bit SPE_NIPD_EIRQ_EN:1; /**< \brief [0:0] SPE_NIPD_EIRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit SPE_DCHG_EIRQ_EN:1; /**< \brief [1:1] SPE_DCHG_EIRQ error interrupt enable (rw) */
+ Ifx_Strict_32Bit SPE_PERR_EIRQ_EN:1; /**< \brief [2:2] SPE_PERR_EIRQ error interrupt enable (rw) */
+ Ifx_Strict_32Bit SPE_BIS_EIRQ_EN:1; /**< \brief [3:3] SPE_BIS_EIRQ error interrupt enable (rw) */
+ Ifx_Strict_32Bit SPE_RCMP_EIRQ_EN:1; /**< \brief [4:4] SPE_RCMP_EIRQ error interrupt enable (rw) */
+ Ifx_Strict_32Bit reserved_5:27; /**< \brief \internal Reserved */
+} Ifx_GTM_SPE_EIRQ_EN_Bits;
+
+/** \brief SPE Interrupt Enable Register */
+typedef struct _Ifx_GTM_SPE_IRQ_EN_Bits
+{
+ Ifx_Strict_32Bit SPE_NIPD_IRQ_EN:1; /**< \brief [0:0] SPE_NIPD_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit SPE_DCHG_IRQ_EN:1; /**< \brief [1:1] SPE_DCHG_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit SPE_PERR_IRQ_EN:1; /**< \brief [2:2] SPE_PERR_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit SPE_BIS_IRQ_EN:1; /**< \brief [3:3] SPE_BIS_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit SPE_RCMP_IRQ_EN:1; /**< \brief [4:4] SPE_RCMP_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit reserved_5:27; /**< \brief \internal Reserved */
+} Ifx_GTM_SPE_IRQ_EN_Bits;
+
+/** \brief SPE Interrupt Generation by Software */
+typedef struct _Ifx_GTM_SPE_IRQ_FORCINT_Bits
+{
+ Ifx_Strict_32Bit TRG_SPE_NIPD:1; /**< \brief [0:0] Force interrupt of SPE_NIPD (w) */
+ Ifx_Strict_32Bit TRG_SPE_DCHG:1; /**< \brief [1:1] Force interrupt of SPE_DCHG (w) */
+ Ifx_Strict_32Bit TRG_SPE_PERR:1; /**< \brief [2:2] Force interrupt of SPE_PERR (w) */
+ Ifx_Strict_32Bit TRG_SPE_BIS:1; /**< \brief [3:3] Force interrupt of SPE_BIS (w) */
+ Ifx_Strict_32Bit TRG_SPE_RCMP:1; /**< \brief [4:4] Force interrupt of SPE_RCMP (w) */
+ Ifx_Strict_32Bit reserved_5:27; /**< \brief \internal Reserved */
+} Ifx_GTM_SPE_IRQ_FORCINT_Bits;
+
+/** \brief SPE IRQ Mode Configuration Register */
+typedef struct _Ifx_GTM_SPE_IRQ_MODE_Bits
+{
+ Ifx_Strict_32Bit IRQ_MODE:2; /**< \brief [1:0] IRQ mode selection (rw) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_GTM_SPE_IRQ_MODE_Bits;
+
+/** \brief SPE Interrupt Notification Register */
+typedef struct _Ifx_GTM_SPE_IRQ_NOTIFY_Bits
+{
+ Ifx_Strict_32Bit SPE_NIPD:1; /**< \brief [0:0] New input pattern interrupt occurred (rwh) */
+ Ifx_Strict_32Bit SPE_DCHG:1; /**< \brief [1:1] SPE_DIR bit changed on behalf of new input pattern (rwh) */
+ Ifx_Strict_32Bit SPE_PERR:1; /**< \brief [2:2] Wrong or invalid pattern detected at input (rwh) */
+ Ifx_Strict_32Bit SPE_BIS:1; /**< \brief [3:3] Bouncing input signal detected (rwh) */
+ Ifx_Strict_32Bit SPE_RCMP:1; /**< \brief [4:4] SPE revolution counter match event (rwh) */
+ Ifx_Strict_32Bit reserved_5:27; /**< \brief \internal Reserved */
+} Ifx_GTM_SPE_IRQ_NOTIFY_Bits;
+
+/** \brief SPE Output Control Register */
+typedef struct _Ifx_GTM_SPE_OUT_CTRL_Bits
+{
+ Ifx_Strict_32Bit SPE_OUT_CTRL:16; /**< \brief [15:0] SPE output control value for TOM_CH0 to TOM_CH7 (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_SPE_OUT_CTRL_Bits;
+
+/** \brief SPE Output Definition Register */
+typedef struct _Ifx_GTM_SPE_OUT_PAT_Bits
+{
+ Ifx_Strict_32Bit SPE_OUT_PAT:16; /**< \brief [15:0] SPE output control value for TOM_CH0 to TOM_CH7 (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_SPE_OUT_PAT_Bits;
+
+/** \brief SPE Input Pattern Definition Register */
+typedef struct _Ifx_GTM_SPE_PAT_Bits
+{
+ Ifx_Strict_32Bit IP0_VAL:1; /**< \brief [0:0] Input pattern 0 is a valid pattern (rw) */
+ Ifx_Strict_32Bit IP0_PAT:3; /**< \brief [3:1] Input pattern 0 (rw) */
+ Ifx_Strict_32Bit IP1_VAL:1; /**< \brief [4:4] Input pattern 1 is a valid pattern (rw) */
+ Ifx_Strict_32Bit IP1_PAT:3; /**< \brief [7:5] Input pattern 1 (rw) */
+ Ifx_Strict_32Bit IP2_VAL:1; /**< \brief [8:8] Input pattern 2 is a valid pattern (rw) */
+ Ifx_Strict_32Bit IP2_PAT:3; /**< \brief [11:9] Input pattern 2 (rw) */
+ Ifx_Strict_32Bit IP3_VAL:1; /**< \brief [12:12] Input pattern 3 is a valid pattern (rw) */
+ Ifx_Strict_32Bit IP3_PAT:3; /**< \brief [15:13] Input pattern 3 (rw) */
+ Ifx_Strict_32Bit IP4_VAL:1; /**< \brief [16:16] Input pattern 4 is a valid pattern (rw) */
+ Ifx_Strict_32Bit IP4_PAT:3; /**< \brief [19:17] Input pattern 4 (rw) */
+ Ifx_Strict_32Bit IP5_VAL:1; /**< \brief [20:20] Input pattern 5 is a valid pattern (rw) */
+ Ifx_Strict_32Bit IP5_PAT:3; /**< \brief [23:21] Input pattern 5 (rw) */
+ Ifx_Strict_32Bit IP6_VAL:1; /**< \brief [24:24] Input pattern 6 is a valid pattern (rw) */
+ Ifx_Strict_32Bit IP6_PAT:3; /**< \brief [27:25] Input pattern 6 (rw) */
+ Ifx_Strict_32Bit IP7_VAL:1; /**< \brief [28:28] Input pattern 7 is a valid pattern (rw) */
+ Ifx_Strict_32Bit IP7_PAT:3; /**< \brief [31:29] Input pattern 7 (rw) */
+} Ifx_GTM_SPE_PAT_Bits;
+
+/** \brief TBU Channel 0 Base Register */
+typedef struct _Ifx_GTM_TBU_CH0_BASE_Bits
+{
+ Ifx_Strict_32Bit BASE:27; /**< \brief [26:0] Time base value for channel 0 (rw) */
+ Ifx_Strict_32Bit reserved_27:5; /**< \brief \internal Reserved */
+} Ifx_GTM_TBU_CH0_BASE_Bits;
+
+/** \brief TBU Channel 0 Control Register */
+typedef struct _Ifx_GTM_TBU_CH0_CTRL_Bits
+{
+ Ifx_Strict_32Bit LOW_RES:1; /**< \brief [0:0] TBU_CH0_BASE register resolution (rw) */
+ Ifx_Strict_32Bit CH_CLK_SRC:3; /**< \brief [3:1] Clock source for channel x (x:0...2) time base counter (rw) */
+ Ifx_Strict_32Bit reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_GTM_TBU_CH0_CTRL_Bits;
+
+/** \brief TBU Channel 1 Base Register */
+typedef struct _Ifx_GTM_TBU_CH1_BASE_Bits
+{
+ Ifx_Strict_32Bit BASE:24; /**< \brief [23:0] Time base value for channel x (x 1, 2) (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_TBU_CH1_BASE_Bits;
+
+/** \brief TBU Channel 1 Control Register */
+typedef struct _Ifx_GTM_TBU_CH1_CTRL_Bits
+{
+ Ifx_Strict_32Bit CH_MODE:1; /**< \brief [0:0] Channel mode (rw) */
+ Ifx_Strict_32Bit CH_CLK_SRC:3; /**< \brief [3:1] Clock source for channel x (x1...2) time base counter (rw) */
+ Ifx_Strict_32Bit reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_GTM_TBU_CH1_CTRL_Bits;
+
+/** \brief TBU Channel 2 Base Register */
+typedef struct _Ifx_GTM_TBU_CH2_BASE_Bits
+{
+ Ifx_Strict_32Bit BASE:24; /**< \brief [23:0] Time base value for channel x (x 1, 2) (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_TBU_CH2_BASE_Bits;
+
+/** \brief TBU Channel 2 Control Register */
+typedef struct _Ifx_GTM_TBU_CH2_CTRL_Bits
+{
+ Ifx_Strict_32Bit CH_MODE:1; /**< \brief [0:0] Channel mode (rw) */
+ Ifx_Strict_32Bit CH_CLK_SRC:3; /**< \brief [3:1] Clock source for channel x (x1...2) time base counter (rw) */
+ Ifx_Strict_32Bit reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_GTM_TBU_CH2_CTRL_Bits;
+
+/** \brief TBU Global Channel Enable Register */
+typedef struct _Ifx_GTM_TBU_CHEN_Bits
+{
+ Ifx_Strict_32Bit ENDIS_CH0:2; /**< \brief [1:0] TBU channel 0 enable/disable control (rw) */
+ Ifx_Strict_32Bit ENDIS_CH1:2; /**< \brief [3:2] TBU channel 1 enable/disable control (rw) */
+ Ifx_Strict_32Bit ENDIS_CH2:2; /**< \brief [5:4] TBU channel 2 enable/disable control (rw) */
+ Ifx_Strict_32Bit reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_GTM_TBU_CHEN_Bits;
+
+/** \brief GTM TIM AUX_IN_SRC */
+typedef struct _Ifx_GTM_TIM_AUX_IN_SRC_Bits
+{
+ Ifx_Strict_32Bit SRC_CH0:1; /**< \brief [0:0] Defines AUX_IN source of TIMi channel 0 x=0 (rw) */
+ Ifx_Strict_32Bit SRC_CH1:1; /**< \brief [1:1] Defines AUX_IN source of TIMi channel 1 x=1, see bit 0 (rw) */
+ Ifx_Strict_32Bit SRC_CH2:1; /**< \brief [2:2] Defines AUX_IN source of TIMi channel 2 x=2, see bit 0 (rw) */
+ Ifx_Strict_32Bit SRC_CH3:1; /**< \brief [3:3] Defines AUX_IN source of TIMi channel 3 x=3, see bit 0 (rw) */
+ Ifx_Strict_32Bit SRC_CH4:1; /**< \brief [4:4] Defines AUX_IN source of TIMi channel 4 x=4, see bit 0 (rw) */
+ Ifx_Strict_32Bit SRC_CH5:1; /**< \brief [5:5] Defines AUX_IN source of TIMi channel 5 x=5, see bit 0 (rw) */
+ Ifx_Strict_32Bit SRC_CH6:1; /**< \brief [6:6] Defines AUX_IN source of TIMi channel 6 x=6, see bit 0 (rw) */
+ Ifx_Strict_32Bit SRC_CH7:1; /**< \brief [7:7] Defines AUX_IN source of TIMi channel 7 x=7, see bit 0 (rw) */
+ Ifx_Strict_32Bit reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_GTM_TIM_AUX_IN_SRC_Bits;
+
+/** \brief TIM Channel SMU Counter Register */
+typedef struct _Ifx_GTM_TIM_CH_CNT_Bits
+{
+ Ifx_Strict_32Bit CNT:24; /**< \brief [23:0] Actual SMU counter value (r) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_TIM_CH_CNT_Bits;
+
+/** \brief TIM Channel SMU Shadow Counter Register */
+typedef struct _Ifx_GTM_TIM_CH_CNTS_Bits
+{
+ Ifx_Strict_32Bit CNTS:24; /**< \brief [23:0] Counter shadow register (rw) */
+ Ifx_Strict_32Bit ECNT:8; /**< \brief [31:24] Edge counter (r) */
+} Ifx_GTM_TIM_CH_CNTS_Bits;
+
+/** \brief TIM Channel Control Register */
+typedef struct _Ifx_GTM_TIM_CH_CTRL_Bits
+{
+ Ifx_Strict_32Bit TIM_EN:1; /**< \brief [0:0] TIM channel x (x:0...7) enable (rwh) */
+ Ifx_Strict_32Bit TIM_MODE:3; /**< \brief [3:1] TIM channel x (x:0...7) mode (rw) */
+ Ifx_Strict_32Bit OSM:1; /**< \brief [4:4] One-shot mode (rw) */
+ Ifx_Strict_32Bit ARU_EN:1; /**< \brief [5:5] GPR0 and GPR1 register values routed to ARU (rw) */
+ Ifx_Strict_32Bit CICTRL:1; /**< \brief [6:6] Channel Input Control (rw) */
+ Ifx_Strict_32Bit TBU0_SEL:1; /**< \brief [7:7] TBU_TS0 bits input select for TIM_CH[x]_GPRz (z: 0, 1) (rw) */
+ Ifx_Strict_32Bit GPR0_SEL:2; /**< \brief [9:8] Selection for GPR0 register (rw) */
+ Ifx_Strict_32Bit GPR1_SEL:2; /**< \brief [11:10] Selection for GPR1 register (rw) */
+ Ifx_Strict_32Bit CNTS_SEL:1; /**< \brief [12:12] Selection for CNTS register (rw) */
+ Ifx_Strict_32Bit DSL:1; /**< \brief [13:13] Signal level control (rw) */
+ Ifx_Strict_32Bit ISL:1; /**< \brief [14:14] Ignore signal level (rw) */
+ Ifx_Strict_32Bit ECNT_RESET:1; /**< \brief [15:15] Enables resetting the ECNT counter in periodic sampling mode (rw) */
+ Ifx_Strict_32Bit FLT_EN:1; /**< \brief [16:16] Filter enable for channel x (x:0...7) (rw) */
+ Ifx_Strict_32Bit FLT_CNT_FRQ:2; /**< \brief [18:17] Filter counter frequency select (rw) */
+ Ifx_Strict_32Bit EXT_CAP_EN:1; /**< \brief [19:19] Enables external capture mode (rw) */
+ Ifx_Strict_32Bit FLT_MODE_RE:1; /**< \brief [20:20] Filter mode for rising edge (rw) */
+ Ifx_Strict_32Bit FLT_CTR_RE:1; /**< \brief [21:21] Filter counter mode for rising edge (rw) */
+ Ifx_Strict_32Bit FLT_MODE_FE:1; /**< \brief [22:22] Filter mode for falling edge (rw) */
+ Ifx_Strict_32Bit FLT_CTR_FE:1; /**< \brief [23:23] Filter counter mode for falling edge (rw) */
+ Ifx_Strict_32Bit CLK_SEL:3; /**< \brief [26:24] CMU clock source select for channel (rw) */
+ Ifx_Strict_32Bit FR_ECNT_OFL:1; /**< \brief [27:27] Extended Edge counter overflow behaviour (rw) */
+ Ifx_Strict_32Bit EGPR0_SEL:1; /**< \brief [28:28] Extension of GPR0_SEL bit field (rw) */
+ Ifx_Strict_32Bit EGPR1_SEL:1; /**< \brief [29:29] Extension of GPR1_SEL bit field (rw) */
+ Ifx_Strict_32Bit TOCTRL:2; /**< \brief [31:30] Timeout control (rw) */
+} Ifx_GTM_TIM_CH_CTRL_Bits;
+
+/** \brief TIM Channel Edge Counter Register */
+typedef struct _Ifx_GTM_TIM_CH_ECNT_Bits
+{
+ Ifx_Strict_32Bit ECNT:16; /**< \brief [15:0] Edge counter (rh) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_TIM_CH_ECNT_Bits;
+
+/** \brief TIM Channel External Capture Control Register */
+typedef struct _Ifx_GTM_TIM_CH_ECTRL_Bits
+{
+ Ifx_Strict_32Bit EXT_CAP_SRC:3; /**< \brief [2:0] Defines selected source for triggering the EXT_CAPTURE functionality (rw) */
+ Ifx_Strict_32Bit reserved_3:29; /**< \brief \internal Reserved */
+} Ifx_GTM_TIM_CH_ECTRL_Bits;
+
+/** \brief TIM Channel Error Interrupt Enable Register */
+typedef struct _Ifx_GTM_TIM_CH_EIRQ_EN_Bits
+{
+ Ifx_Strict_32Bit NEWVAL_EIRQ_EN:1; /**< \brief [0:0] TIM_NEWVALx_EIRQ error interrupt enable (rw) */
+ Ifx_Strict_32Bit ECNTOFL_EIRQ_EN:1; /**< \brief [1:1] TIM_ECNTOFLx_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit CNTOFL_EIRQ_EN:1; /**< \brief [2:2] TIM_CNTOFLx_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit GPROFL_EIRQ_EN:1; /**< \brief [3:3] TIM_GPROFL_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit TODET_EIRQ_EN:1; /**< \brief [4:4] TIM_TODETx_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit GLITCHDET_EIRQ_EN:1; /**< \brief [5:5] TIM_GLITCHDETx_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_GTM_TIM_CH_EIRQ_EN_Bits;
+
+/** \brief TIM Channel Filter Parameter 1 Register */
+typedef struct _Ifx_GTM_TIM_CH_FLT_FE_Bits
+{
+ Ifx_Strict_32Bit FLT_FE:24; /**< \brief [23:0] Filter parameter for falling edge (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_TIM_CH_FLT_FE_Bits;
+
+/** \brief GTM_TIM Channel Filter Parameter 0 Register */
+typedef struct _Ifx_GTM_TIM_CH_FLT_RE_Bits
+{
+ Ifx_Strict_32Bit FLT_RE:24; /**< \brief [23:0] Filter parameter for rising edge (rw) */
+ Ifx_Strict_32Bit reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_GTM_TIM_CH_FLT_RE_Bits;
+
+/** \brief TIM Channel General Purpose 0 Register */
+typedef struct _Ifx_GTM_TIM_CH_GPR0_Bits
+{
+ Ifx_Strict_32Bit GPR0:24; /**< \brief [23:0] Input signal characteristic parameter 0 (r) */
+ Ifx_Strict_32Bit ECNT:8; /**< \brief [31:24] Edge counter (r) */
+} Ifx_GTM_TIM_CH_GPR0_Bits;
+
+/** \brief TIM Channel General Purpose 1 Register */
+typedef struct _Ifx_GTM_TIM_CH_GPR1_Bits
+{
+ Ifx_Strict_32Bit GPR1:24; /**< \brief [23:0] Input signal characteristic parameter 1 (r) */
+ Ifx_Strict_32Bit ECNT:8; /**< \brief [31:24] Edge counter (r) */
+} Ifx_GTM_TIM_CH_GPR1_Bits;
+
+/** \brief TIM Channel Interrupt Enable Register */
+typedef struct _Ifx_GTM_TIM_CH_IRQ_EN_Bits
+{
+ Ifx_Strict_32Bit NEWVAL_IRQ_EN:1; /**< \brief [0:0] TIM_NEWVALx_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit ECNTOFL_IRQ_EN:1; /**< \brief [1:1] TIM_ECNTOFLx_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit CNTOFL_IRQ_EN:1; /**< \brief [2:2] TIM_CNTOFLx_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit GPROFL_IRQ_EN:1; /**< \brief [3:3] TIM_GPROFLx_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit TODET_IRQ_EN:1; /**< \brief [4:4] TIM_TODETx_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit GLITCHDET_IRQ_EN:1; /**< \brief [5:5] TIM_GLITCHDETx_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_GTM_TIM_CH_IRQ_EN_Bits;
+
+/** \brief TIM Channel Software Interrupt Force Register */
+typedef struct _Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits
+{
+ Ifx_Strict_32Bit TRG_NEWVAL:1; /**< \brief [0:0] Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit TRG_ECNTOFL:1; /**< \brief [1:1] Trigger ECNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit TRG_CNTOFL:1; /**< \brief [2:2] Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit TRG_GPROFL:1; /**< \brief [3:3] Trigger GPROFL bit in TIM_CHx_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit TRG_TODET:1; /**< \brief [4:4] Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit TRG_GLITCHDET:1; /**< \brief [5:5] Trigger GLITCHDET bit in TIM_CHx_IRQ_NOTIFY register by software (w) */
+ Ifx_Strict_32Bit reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits;
+
+/** \brief TIM IRQ Mode Configuration Register */
+typedef struct _Ifx_GTM_TIM_CH_IRQ_MODE_Bits
+{
+ Ifx_Strict_32Bit IRQ_MODE:2; /**< \brief [1:0] IRQ mode selection (rw) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_GTM_TIM_CH_IRQ_MODE_Bits;
+
+/** \brief TIM Channel Interrupt Notification Register */
+typedef struct _Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits
+{
+ Ifx_Strict_32Bit NEWVAL:1; /**< \brief [0:0] New measurement value detected by in channel x (x:0...7) (rwh) */
+ Ifx_Strict_32Bit ECNTOFL:1; /**< \brief [1:1] counter overflow of channel x, (x:0...7) (rwh) */
+ Ifx_Strict_32Bit CNTOFL:1; /**< \brief [2:2] SMU CNT counter overflow of channel x, (x:0...7) (rwh) */
+ Ifx_Strict_32Bit GPROFL:1; /**< \brief [3:3] GPR0 and GPR1 data overflow, old data not read out before new data has arrived at input pin, (x:0...7) (rwh) */
+ Ifx_Strict_32Bit TODET:1; /**< \brief [4:4] Timeout reached for input signal of channel x, (x:0...7) (rwh) */
+ Ifx_Strict_32Bit GLITCHDET:1; /**< \brief [5:5] Glitch detected on channel x, (x:0...7) (rwh) */
+ Ifx_Strict_32Bit reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits;
+
+/** \brief TIM Channel TDUC Register */
+typedef struct _Ifx_GTM_TIM_CH_TDUC_Bits
+{
+ Ifx_Strict_32Bit TO_CNT:8; /**< \brief [7:0] Current Timeout value for channel x (rh) */
+ Ifx_Strict_32Bit reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_GTM_TIM_CH_TDUC_Bits;
+
+/** \brief TIM Channel TDUV Register */
+typedef struct _Ifx_GTM_TIM_CH_TDUV_Bits
+{
+ Ifx_Strict_32Bit TOV:8; /**< \brief [7:0] Time out duration for channel x (rw) */
+ Ifx_Strict_32Bit reserved_8:20; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit TCS:3; /**< \brief [30:28] Timeout Clock selection (rw) */
+ Ifx_Strict_32Bit reserved_31:1; /**< \brief \internal Reserved */
+} Ifx_GTM_TIM_CH_TDUV_Bits;
+
+/** \brief TIM_IN_SRC Long Name */
+typedef struct _Ifx_GTM_TIM_IN_SRC_Bits
+{
+ Ifx_Strict_32Bit VAL_0:2; /**< \brief [1:0] Value to be fed to Channel 0 (rw) */
+ Ifx_Strict_32Bit MODE_0:2; /**< \brief [3:2] Input source to Channel 0 (rw) */
+ Ifx_Strict_32Bit VAL_1:2; /**< \brief [5:4] Value to be fed to Channel 1 (rw) */
+ Ifx_Strict_32Bit MODE_1:2; /**< \brief [7:6] Input source to Channel 1 (rw) */
+ Ifx_Strict_32Bit VAL_2:2; /**< \brief [9:8] Value to be fed to Channel 2 (rw) */
+ Ifx_Strict_32Bit MODE_2:2; /**< \brief [11:10] Input source to Channel 2 (rw) */
+ Ifx_Strict_32Bit VAL_3:2; /**< \brief [13:12] Value to be fed to Channel 3 (rw) */
+ Ifx_Strict_32Bit MODE_3:2; /**< \brief [15:14] Input source to Channel 3 (rw) */
+ Ifx_Strict_32Bit VAL_4:2; /**< \brief [17:16] Value to be fed to Channel 4 (rw) */
+ Ifx_Strict_32Bit MODE_4:2; /**< \brief [19:18] Input source to Channel 4 (rw) */
+ Ifx_Strict_32Bit VAL_5:2; /**< \brief [21:20] Value to be fed to Channel 5 (rw) */
+ Ifx_Strict_32Bit MODE_5:2; /**< \brief [23:22] Input source to Channel 5 (rw) */
+ Ifx_Strict_32Bit VAL_6:2; /**< \brief [25:24] Value to be fed to Channel 6 (rw) */
+ Ifx_Strict_32Bit MODE_6:2; /**< \brief [27:26] Input source to Channel 6 (rw) */
+ Ifx_Strict_32Bit VAL_7:2; /**< \brief [29:28] Value to be fed to Channel 7 (rw) */
+ Ifx_Strict_32Bit MODE_7:2; /**< \brief [31:30] Input source to Channel 7 (rw) */
+} Ifx_GTM_TIM_IN_SRC_Bits;
+
+/** \brief TIM Global Software Reset Register */
+typedef struct _Ifx_GTM_TIM_RST_Bits
+{
+ Ifx_Strict_32Bit RST_CH0:1; /**< \brief [0:0] Software reset of channel 0 (w) */
+ Ifx_Strict_32Bit RST_CH1:1; /**< \brief [1:1] Software reset of channel 1 (w) */
+ Ifx_Strict_32Bit RST_CH2:1; /**< \brief [2:2] Software reset of channel 2 (w) */
+ Ifx_Strict_32Bit RST_CH3:1; /**< \brief [3:3] Software reset of channel 3 (w) */
+ Ifx_Strict_32Bit RST_CH4:1; /**< \brief [4:4] Software reset of channel 4 (w) */
+ Ifx_Strict_32Bit RST_CH5:1; /**< \brief [5:5] Software reset of channel 5 (w) */
+ Ifx_Strict_32Bit RST_CH6:1; /**< \brief [6:6] Software reset of channel 6 (w) */
+ Ifx_Strict_32Bit RST_CH7:1; /**< \brief [7:7] Software reset of channel 7 (w) */
+ Ifx_Strict_32Bit reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_GTM_TIM_RST_Bits;
+
+/** \brief TOM Channel CCU0 Compare Register */
+typedef struct _Ifx_GTM_TOM_CH_CM0_Bits
+{
+ Ifx_Strict_32Bit CM0:16; /**< \brief [15:0] TOM CCU0 compare register (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_TOM_CH_CM0_Bits;
+
+/** \brief TOM Channel CCU1 Compare Register */
+typedef struct _Ifx_GTM_TOM_CH_CM1_Bits
+{
+ Ifx_Strict_32Bit CM1:16; /**< \brief [15:0] TOM CCU1 compare register (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_TOM_CH_CM1_Bits;
+
+/** \brief TOM Channel CCU0 Counter Register */
+typedef struct _Ifx_GTM_TOM_CH_CN0_Bits
+{
+ Ifx_Strict_32Bit CN0:16; /**< \brief [15:0] TOM CCU0 counter register (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_TOM_CH_CN0_Bits;
+
+/** \brief TOM Channel Control Register鈥� */
+typedef struct _Ifx_GTM_TOM_CH_CTRL_Bits
+{
+ Ifx_Strict_32Bit reserved_0:11; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SL:1; /**< \brief [11:11] Signal level for duty cycle (rw) */
+ Ifx_Strict_32Bit CLK_SRC_SR:3; /**< \brief [14:12] Clock source select for channel (rw) */
+ Ifx_Strict_32Bit reserved_15:5; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit RST_CCU0:1; /**< \brief [20:20] Reset source of CCU0 (rw) */
+ Ifx_Strict_32Bit reserved_21:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit TRIGOUT:1; /**< \brief [24:24] Trigger output selection (output signal TRIG_[x]) of module TOM_CH[x] (rw) */
+ Ifx_Strict_32Bit reserved_25:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit OSM:1; /**< \brief [26:26] One-shot mode (rw) */
+ Ifx_Strict_32Bit BITREV:1; /**< \brief [27:27] Bit-reversing of output of counter register CN0 (rw) */
+ Ifx_Strict_32Bit SPEM:1; /**< \brief [28:28] SPE mode enable for channel (rw) */
+ Ifx_Strict_32Bit GCM:1; /**< \brief [29:29] Gated Counter Mode enable (rw) */
+ Ifx_Strict_32Bit reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_GTM_TOM_CH_CTRL_Bits;
+
+/** \brief TOM Channel Interrupt Enable Register */
+typedef struct _Ifx_GTM_TOM_CH_IRQ_EN_Bits
+{
+ Ifx_Strict_32Bit CCU0TC_IRQ_EN:1; /**< \brief [0:0] TOM_CCU0TC_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit CCU1TC_IRQ_EN:1; /**< \brief [1:1] TOM_CCU1TC_IRQ interrupt enable (rw) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_GTM_TOM_CH_IRQ_EN_Bits;
+
+/** \brief TOM Channel Software Interrupt Generation Register */
+typedef struct _Ifx_GTM_TOM_CH_IRQ_FORCINT_Bits
+{
+ Ifx_Strict_32Bit TRG_CCU0TC0:1; /**< \brief [0:0] Trigger TOM_CCU0TC0_IRQ interrupt by software (w) */
+ Ifx_Strict_32Bit TRG_CCU1TC0:1; /**< \brief [1:1] Trigger TOM_CCU1TC0_IRQ interrupt by software (w) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_GTM_TOM_CH_IRQ_FORCINT_Bits;
+
+/** \brief TOM IRQ Mode Configuration Register */
+typedef struct _Ifx_GTM_TOM_CH_IRQ_MODE_Bits
+{
+ Ifx_Strict_32Bit IRQ_MODE:2; /**< \brief [1:0] IRQ mode selection (rw) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_GTM_TOM_CH_IRQ_MODE_Bits;
+
+/** \brief TOM Channel Interrupt Notification Register */
+typedef struct _Ifx_GTM_TOM_CH_IRQ_NOTIFY_Bits
+{
+ Ifx_Strict_32Bit CCU0TC:1; /**< \brief [0:0] CCU0 Trigger condition interrupt for channel x (rwh) */
+ Ifx_Strict_32Bit CCU1TC:1; /**< \brief [1:1] CCU1 Trigger condition interrupt for channel x (rwh) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_GTM_TOM_CH_IRQ_NOTIFY_Bits;
+
+/** \brief TOM Channel CCU0 Compare Shadow Register */
+typedef struct _Ifx_GTM_TOM_CH_SR0_Bits
+{
+ Ifx_Strict_32Bit SR0:16; /**< \brief [15:0] TOM channel x shadow register SR0 for update of compare register CM0 (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_TOM_CH_SR0_Bits;
+
+/** \brief TOM Channel CCU1 Compare Shadow Register */
+typedef struct _Ifx_GTM_TOM_CH_SR1_Bits
+{
+ Ifx_Strict_32Bit SR1:16; /**< \brief [15:0] TOM channel x shadow register SR1 for update of compare register CM1 (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_TOM_CH_SR1_Bits;
+
+/** \brief TOM Channel Status Register */
+typedef struct _Ifx_GTM_TOM_CH_STAT_Bits
+{
+ Ifx_Strict_32Bit OL:1; /**< \brief [0:0] Output level of output TOM_OUT(x) (r) */
+ Ifx_Strict_32Bit reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_GTM_TOM_CH_STAT_Bits;
+
+/** \brief TOM TGC0 Action Time Base Register */
+typedef struct _Ifx_GTM_TOM_TGC0_ACT_TB_Bits
+{
+ Ifx_Strict_32Bit ACT_TB:24; /**< \brief [23:0] Time base value (rw) */
+ Ifx_Strict_32Bit TB_TRIG:1; /**< \brief [24:24] Set trigger request (rwh) */
+ Ifx_Strict_32Bit TBU_SEL:2; /**< \brief [26:25] Selection of time base used for comparison (rw) */
+ Ifx_Strict_32Bit reserved_27:5; /**< \brief \internal Reserved */
+} Ifx_GTM_TOM_TGC0_ACT_TB_Bits;
+
+/** \brief TOM TGC0 Enable/Disable Control Register */
+typedef struct _Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits
+{
+ Ifx_Strict_32Bit ENDIS_CTRL0:2; /**< \brief [1:0] (A)TOM channel 0 enable/disable update value (rw) */
+ Ifx_Strict_32Bit ENDIS_CTRL1:2; /**< \brief [3:2] (A)TOM channel 1 enable/disable update value (rw) */
+ Ifx_Strict_32Bit ENDIS_CTRL2:2; /**< \brief [5:4] (A)TOM channel 2 enable/disable update value (rw) */
+ Ifx_Strict_32Bit ENDIS_CTRL3:2; /**< \brief [7:6] (A)TOM channel 3 enable/disable update value (rw) */
+ Ifx_Strict_32Bit ENDIS_CTRL4:2; /**< \brief [9:8] (A)TOM channel 4 enable/disable update value (rw) */
+ Ifx_Strict_32Bit ENDIS_CTRL5:2; /**< \brief [11:10] (A)TOM channel 5 enable/disable update value (rw) */
+ Ifx_Strict_32Bit ENDIS_CTRL6:2; /**< \brief [13:12] (A)TOM channel 6 enable/disable update value (rw) */
+ Ifx_Strict_32Bit ENDIS_CTRL7:2; /**< \brief [15:14] (A)TOM channel 7 enable/disable update value (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits;
+
+/** \brief TOM TGC0 Enable/Disable Status Register */
+typedef struct _Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits
+{
+ Ifx_Strict_32Bit ENDIS_STAT0:2; /**< \brief [1:0] (A)TOM channel 0 enable/disable (rw) */
+ Ifx_Strict_32Bit ENDIS_STAT1:2; /**< \brief [3:2] (A)TOM channel 1 enable/disable (rw) */
+ Ifx_Strict_32Bit ENDIS_STAT2:2; /**< \brief [5:4] (A)TOM channel 2 enable/disable (rw) */
+ Ifx_Strict_32Bit ENDIS_STAT3:2; /**< \brief [7:6] (A)TOM channel 3 enable/disable (rw) */
+ Ifx_Strict_32Bit ENDIS_STAT4:2; /**< \brief [9:8] (A)TOM channel 4 enable/disable (rw) */
+ Ifx_Strict_32Bit ENDIS_STAT5:2; /**< \brief [11:10] (A)TOM channel 5 enable/disable (rw) */
+ Ifx_Strict_32Bit ENDIS_STAT6:2; /**< \brief [13:12] (A)TOM channel 6 enable/disable (rw) */
+ Ifx_Strict_32Bit ENDIS_STAT7:2; /**< \brief [15:14] (A)TOM channel 7 enable/disable (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits;
+
+/** \brief TOM TGC0 Force Update Control Register */
+typedef struct _Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits
+{
+ Ifx_Strict_32Bit FUPD_CTRL0:2; /**< \brief [1:0] Force update of (A)TOM channel 0 operation registers (rw) */
+ Ifx_Strict_32Bit FUPD_CTRL1:2; /**< \brief [3:2] Force update of (A)TOM channel 1 operation registers (rw) */
+ Ifx_Strict_32Bit FUPD_CTRL2:2; /**< \brief [5:4] Force update of (A)TOM channel 2 operation registers (rw) */
+ Ifx_Strict_32Bit FUPD_CTRL3:2; /**< \brief [7:6] Force update of (A)TOM channel 3 operation registers (rw) */
+ Ifx_Strict_32Bit FUPD_CTRL4:2; /**< \brief [9:8] Force update of (A)TOM channel 4 operation registers (rw) */
+ Ifx_Strict_32Bit FUPD_CTRL5:2; /**< \brief [11:10] Force update of (A)TOM channel 5 operation registers (rw) */
+ Ifx_Strict_32Bit FUPD_CTRL6:2; /**< \brief [13:12] Force update of (A)TOM channel 6 operation registers (rw) */
+ Ifx_Strict_32Bit FUPD_CTRL7:2; /**< \brief [15:14] Force update of (A)TOM channel 7 operation registers (rw) */
+ Ifx_Strict_32Bit RSTCN0_CH0:2; /**< \brief [17:16] Reset CN0 of channel 0 on force update event (rw) */
+ Ifx_Strict_32Bit RSTCN0_CH1:2; /**< \brief [19:18] Reset CN0 of channel 1 on force update event (rw) */
+ Ifx_Strict_32Bit RSTCN0_CH2:2; /**< \brief [21:20] Reset CN0 of channel 2 on force update event (rw) */
+ Ifx_Strict_32Bit RSTCN0_CH3:2; /**< \brief [23:22] Reset CN0 of channel 3 on force update event (rw) */
+ Ifx_Strict_32Bit RSTCN0_CH4:2; /**< \brief [25:24] Reset CN0 of channel 4 on force update event (rw) */
+ Ifx_Strict_32Bit RSTCN0_CH5:2; /**< \brief [27:26] Reset CN0 of channel 5 on force update event (rw) */
+ Ifx_Strict_32Bit RSTCN0_CH6:2; /**< \brief [29:28] Reset CN0 of channel 6 on force update event (rw) */
+ Ifx_Strict_32Bit RSTCN0_CH7:2; /**< \brief [31:30] Reset CN0 of channel 7 on force update event (rw) */
+} Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits;
+
+/** \brief TOM TGC0 Global Control Register */
+typedef struct _Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits
+{
+ Ifx_Strict_32Bit HOST_TRIG:1; /**< \brief [0:0] Trigger request signal (see TGC0, TGC1) to update the register ENDIS_STAT and OUTEN_STAT (w) */
+ Ifx_Strict_32Bit reserved_1:7; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit RST_CH0:1; /**< \brief [8:8] Software reset of channel 0 (w) */
+ Ifx_Strict_32Bit RST_CH1:1; /**< \brief [9:9] Software reset of channel 1 (w) */
+ Ifx_Strict_32Bit RST_CH2:1; /**< \brief [10:10] Software reset of channel 2 (w) */
+ Ifx_Strict_32Bit RST_CH3:1; /**< \brief [11:11] Software reset of channel 3 (w) */
+ Ifx_Strict_32Bit RST_CH4:1; /**< \brief [12:12] Software reset of channel 4 (w) */
+ Ifx_Strict_32Bit RST_CH5:1; /**< \brief [13:13] Software reset of channel 5 (w) */
+ Ifx_Strict_32Bit RST_CH6:1; /**< \brief [14:14] Software reset of channel 6 (w) */
+ Ifx_Strict_32Bit RST_CH7:1; /**< \brief [15:15] Software reset of channel 7 (w) */
+ Ifx_Strict_32Bit UPEN_CTRL0:2; /**< \brief [17:16] TOM channel 0 enable update of register CM0, CM1 and CLK_SRC from SR0, SR1 and CLK_SRC_SR (rw) */
+ Ifx_Strict_32Bit UPEN_CTRL1:2; /**< \brief [19:18] TOM channel 1 enable update of register CM0, CM1 and CLK_SRC (rw) */
+ Ifx_Strict_32Bit UPEN_CTRL2:2; /**< \brief [21:20] TOM channel 2 enable update of register CM0, CM1 and CLK_SRC (rw) */
+ Ifx_Strict_32Bit UPEN_CTRL3:2; /**< \brief [23:22] TOM channel 3 enable update of register CM0, CM1 and CLK_SRC (rw) */
+ Ifx_Strict_32Bit UPEN_CTRL4:2; /**< \brief [25:24] TOM channel 4 enable update of register CM0, CM1 and CLK_SRC (rw) */
+ Ifx_Strict_32Bit UPEN_CTRL5:2; /**< \brief [27:26] TOM channel 5 enable update of register CM0, CM1 and CLK_SRC (rw) */
+ Ifx_Strict_32Bit UPEN_CTRL6:2; /**< \brief [29:28] TOM channel 6 enable update of register CM0, CM1 and CLK_SRC (rw) */
+ Ifx_Strict_32Bit UPEN_CTRL7:2; /**< \brief [31:30] TOM channel 7 enable update of register CM0, CM1 and CLK_SRC (rw) */
+} Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits;
+
+/** \brief TOM TGC0 Internal Trigger Control Register */
+typedef struct _Ifx_GTM_TOM_TGC0_INT_TRIG_Bits
+{
+ Ifx_Strict_32Bit INT_TRIG0:2; /**< \brief [1:0] Select input signal TRIG_0 as a trigger source (rw) */
+ Ifx_Strict_32Bit INT_TRIG1:2; /**< \brief [3:2] Select input signal TRIG_1 as a trigger source (rw) */
+ Ifx_Strict_32Bit INT_TRIG2:2; /**< \brief [5:4] Select input signal TRIG_2 as a trigger source (rw) */
+ Ifx_Strict_32Bit INT_TRIG3:2; /**< \brief [7:6] Select input signal TRIG_3 as a trigger source (rw) */
+ Ifx_Strict_32Bit INT_TRIG4:2; /**< \brief [9:8] Select input signal TRIG_4 as a trigger source (rw) */
+ Ifx_Strict_32Bit INT_TRIG5:2; /**< \brief [11:10] Select input signal TRIG_5 as a trigger source (rw) */
+ Ifx_Strict_32Bit INT_TRIG6:2; /**< \brief [13:12] Select input signal TRIG_6 as a trigger source (rw) */
+ Ifx_Strict_32Bit INT_TRIG7:2; /**< \brief [15:14] Select input signal TRIG_7 as a trigger source (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_TOM_TGC0_INT_TRIG_Bits;
+
+/** \brief TOM TGC0 Output Enable Control Register */
+typedef struct _Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits
+{
+ Ifx_Strict_32Bit OUTEN_CTRL0:2; /**< \brief [1:0] Output (A)TOM_OUT(0) enable/disable update value (rw) */
+ Ifx_Strict_32Bit OUTEN_CTRL1:2; /**< \brief [3:2] Output (A)TOM_OUT(1)enable/disable update value (rw) */
+ Ifx_Strict_32Bit OUTEN_CTRL2:2; /**< \brief [5:4] Output (A)TOM_OUT(2) enable/disable update value (rw) */
+ Ifx_Strict_32Bit OUTEN_CTRL3:2; /**< \brief [7:6] Output (A)TOM_OUT(3) enable/disable update value (rw) */
+ Ifx_Strict_32Bit OUTEN_CTRL4:2; /**< \brief [9:8] Output (A)TOM_OUT(4) enable/disable update value (rw) */
+ Ifx_Strict_32Bit OUTEN_CTRL5:2; /**< \brief [11:10] Output (A)TOM_OUT(5) enable/disable update value (rw) */
+ Ifx_Strict_32Bit OUTEN_CTRL6:2; /**< \brief [13:12] Output (A)TOM_OUT(6) enable/disable update value (rw) */
+ Ifx_Strict_32Bit OUTEN_CTRL7:2; /**< \brief [15:14] Output (A)TOM_OUT(7) enable/disable update value (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits;
+
+/** \brief TOM TGC0 Output Enable Status Register */
+typedef struct _Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits
+{
+ Ifx_Strict_32Bit OUTEN_STAT0:2; /**< \brief [1:0] Control/status of output (A)TOM_OUT(0) (rw) */
+ Ifx_Strict_32Bit OUTEN_STAT1:2; /**< \brief [3:2] Control/status of output (A)TOM_OUT(1) (rw) */
+ Ifx_Strict_32Bit OUTEN_STAT2:2; /**< \brief [5:4] Control/status of output (A)TOM_OUT(2) (rw) */
+ Ifx_Strict_32Bit OUTEN_STAT3:2; /**< \brief [7:6] Control/status of output (A)TOM_OUT(3) (rw) */
+ Ifx_Strict_32Bit OUTEN_STAT4:2; /**< \brief [9:8] Control/status of output (A)TOM_OUT(4) (rw) */
+ Ifx_Strict_32Bit OUTEN_STAT5:2; /**< \brief [11:10] Control/status of output (A)TOM_OUT(5) (rw) */
+ Ifx_Strict_32Bit OUTEN_STAT6:2; /**< \brief [13:12] Control/status of output (A)TOM_OUT(6) (rw) */
+ Ifx_Strict_32Bit OUTEN_STAT7:2; /**< \brief [15:14] Control/status of output (A)TOM_OUT(7) (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits;
+
+/** \brief TOM TGC1 Action Time Base Register */
+typedef struct _Ifx_GTM_TOM_TGC1_ACT_TB_Bits
+{
+ Ifx_Strict_32Bit ACT_TB:24; /**< \brief [23:0] Time base value (rw) */
+ Ifx_Strict_32Bit TB_TRIG:1; /**< \brief [24:24] Set trigger request (rwh) */
+ Ifx_Strict_32Bit TBU_SEL:2; /**< \brief [26:25] Selection of time base used for comparison (rw) */
+ Ifx_Strict_32Bit reserved_27:5; /**< \brief \internal Reserved */
+} Ifx_GTM_TOM_TGC1_ACT_TB_Bits;
+
+/** \brief TOM TGC1 Enable/Disable Control Register */
+typedef struct _Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits
+{
+ Ifx_Strict_32Bit ENDIS_CTRL0:2; /**< \brief [1:0] (A)TOM channel 0 enable/disable update value (rw) */
+ Ifx_Strict_32Bit ENDIS_CTRL1:2; /**< \brief [3:2] (A)TOM channel 1 enable/disable update value (rw) */
+ Ifx_Strict_32Bit ENDIS_CTRL2:2; /**< \brief [5:4] (A)TOM channel 2 enable/disable update value (rw) */
+ Ifx_Strict_32Bit ENDIS_CTRL3:2; /**< \brief [7:6] (A)TOM channel 3 enable/disable update value (rw) */
+ Ifx_Strict_32Bit ENDIS_CTRL4:2; /**< \brief [9:8] (A)TOM channel 4 enable/disable update value (rw) */
+ Ifx_Strict_32Bit ENDIS_CTRL5:2; /**< \brief [11:10] (A)TOM channel 5 enable/disable update value (rw) */
+ Ifx_Strict_32Bit ENDIS_CTRL6:2; /**< \brief [13:12] (A)TOM channel 6 enable/disable update value (rw) */
+ Ifx_Strict_32Bit ENDIS_CTRL7:2; /**< \brief [15:14] (A)TOM channel 7 enable/disable update value (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits;
+
+/** \brief TOM TGC1 Enable/Disable Status Register */
+typedef struct _Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits
+{
+ Ifx_Strict_32Bit ENDIS_STAT0:2; /**< \brief [1:0] (A)TOM channel 0 enable/disable (rw) */
+ Ifx_Strict_32Bit ENDIS_STAT1:2; /**< \brief [3:2] (A)TOM channel 1 enable/disable (rw) */
+ Ifx_Strict_32Bit ENDIS_STAT2:2; /**< \brief [5:4] (A)TOM channel 2 enable/disable (rw) */
+ Ifx_Strict_32Bit ENDIS_STAT3:2; /**< \brief [7:6] (A)TOM channel 3 enable/disable (rw) */
+ Ifx_Strict_32Bit ENDIS_STAT4:2; /**< \brief [9:8] (A)TOM channel 4 enable/disable (rw) */
+ Ifx_Strict_32Bit ENDIS_STAT5:2; /**< \brief [11:10] (A)TOM channel 5 enable/disable (rw) */
+ Ifx_Strict_32Bit ENDIS_STAT6:2; /**< \brief [13:12] (A)TOM channel 6 enable/disable (rw) */
+ Ifx_Strict_32Bit ENDIS_STAT7:2; /**< \brief [15:14] (A)TOM channel 7 enable/disable (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits;
+
+/** \brief TOM TGC1 Force Update Control Register */
+typedef struct _Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits
+{
+ Ifx_Strict_32Bit FUPD_CTRL0:2; /**< \brief [1:0] Force update of (A)TOM channel 0 operation registers (rw) */
+ Ifx_Strict_32Bit FUPD_CTRL1:2; /**< \brief [3:2] Force update of (A)TOM channel 1 operation registers (rw) */
+ Ifx_Strict_32Bit FUPD_CTRL2:2; /**< \brief [5:4] Force update of (A)TOM channel 2 operation registers (rw) */
+ Ifx_Strict_32Bit FUPD_CTRL3:2; /**< \brief [7:6] Force update of (A)TOM channel 3 operation registers (rw) */
+ Ifx_Strict_32Bit FUPD_CTRL4:2; /**< \brief [9:8] Force update of (A)TOM channel 4 operation registers (rw) */
+ Ifx_Strict_32Bit FUPD_CTRL5:2; /**< \brief [11:10] Force update of (A)TOM channel 5 operation registers (rw) */
+ Ifx_Strict_32Bit FUPD_CTRL6:2; /**< \brief [13:12] Force update of (A)TOM channel 6 operation registers (rw) */
+ Ifx_Strict_32Bit FUPD_CTRL7:2; /**< \brief [15:14] Force update of (A)TOM channel 7 operation registers (rw) */
+ Ifx_Strict_32Bit RSTCN0_CH0:2; /**< \brief [17:16] Reset CN0 of channel 0 on force update event (rw) */
+ Ifx_Strict_32Bit RSTCN0_CH1:2; /**< \brief [19:18] Reset CN0 of channel 1 on force update event (rw) */
+ Ifx_Strict_32Bit RSTCN0_CH2:2; /**< \brief [21:20] Reset CN0 of channel 2 on force update event (rw) */
+ Ifx_Strict_32Bit RSTCN0_CH3:2; /**< \brief [23:22] Reset CN0 of channel 3 on force update event (rw) */
+ Ifx_Strict_32Bit RSTCN0_CH4:2; /**< \brief [25:24] Reset CN0 of channel 4 on force update event (rw) */
+ Ifx_Strict_32Bit RSTCN0_CH5:2; /**< \brief [27:26] Reset CN0 of channel 5 on force update event (rw) */
+ Ifx_Strict_32Bit RSTCN0_CH6:2; /**< \brief [29:28] Reset CN0 of channel 6 on force update event (rw) */
+ Ifx_Strict_32Bit RSTCN0_CH7:2; /**< \brief [31:30] Reset CN0 of channel 7 on force update event (rw) */
+} Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits;
+
+/** \brief TOM TGC1 Global Control Register */
+typedef struct _Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits
+{
+ Ifx_Strict_32Bit HOST_TRIG:1; /**< \brief [0:0] Trigger request signal (see TGC0, TGC1) to update the register ENDIS_STAT and OUTEN_STAT (w) */
+ Ifx_Strict_32Bit reserved_1:7; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit RST_CH0:1; /**< \brief [8:8] Software reset of channel 0 (w) */
+ Ifx_Strict_32Bit RST_CH1:1; /**< \brief [9:9] Software reset of channel 1 (w) */
+ Ifx_Strict_32Bit RST_CH2:1; /**< \brief [10:10] Software reset of channel 2 (w) */
+ Ifx_Strict_32Bit RST_CH3:1; /**< \brief [11:11] Software reset of channel 3 (w) */
+ Ifx_Strict_32Bit RST_CH4:1; /**< \brief [12:12] Software reset of channel 4 (w) */
+ Ifx_Strict_32Bit RST_CH5:1; /**< \brief [13:13] Software reset of channel 5 (w) */
+ Ifx_Strict_32Bit RST_CH6:1; /**< \brief [14:14] Software reset of channel 6 (w) */
+ Ifx_Strict_32Bit RST_CH7:1; /**< \brief [15:15] Software reset of channel 7 (w) */
+ Ifx_Strict_32Bit UPEN_CTRL0:2; /**< \brief [17:16] TOM channel 0 enable update of register CM0, CM1 and CLK_SRC from SR0, SR1 and CLK_SRC_SR (rw) */
+ Ifx_Strict_32Bit UPEN_CTRL1:2; /**< \brief [19:18] TOM channel 1 enable update of register CM0, CM1 and CLK_SRC (rw) */
+ Ifx_Strict_32Bit UPEN_CTRL2:2; /**< \brief [21:20] TOM channel 2 enable update of register CM0, CM1 and CLK_SRC (rw) */
+ Ifx_Strict_32Bit UPEN_CTRL3:2; /**< \brief [23:22] TOM channel 3 enable update of register CM0, CM1 and CLK_SRC (rw) */
+ Ifx_Strict_32Bit UPEN_CTRL4:2; /**< \brief [25:24] TOM channel 4 enable update of register CM0, CM1 and CLK_SRC (rw) */
+ Ifx_Strict_32Bit UPEN_CTRL5:2; /**< \brief [27:26] TOM channel 5 enable update of register CM0, CM1 and CLK_SRC (rw) */
+ Ifx_Strict_32Bit UPEN_CTRL6:2; /**< \brief [29:28] TOM channel 6 enable update of register CM0, CM1 and CLK_SRC (rw) */
+ Ifx_Strict_32Bit UPEN_CTRL7:2; /**< \brief [31:30] TOM channel 7 enable update of register CM0, CM1 and CLK_SRC (rw) */
+} Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits;
+
+/** \brief TOM TGC1 Internal Trigger Control Register */
+typedef struct _Ifx_GTM_TOM_TGC1_INT_TRIG_Bits
+{
+ Ifx_Strict_32Bit INT_TRIG0:2; /**< \brief [1:0] Select input signal TRIG_0 as a trigger source (rw) */
+ Ifx_Strict_32Bit INT_TRIG1:2; /**< \brief [3:2] Select input signal TRIG_1 as a trigger source (rw) */
+ Ifx_Strict_32Bit INT_TRIG2:2; /**< \brief [5:4] Select input signal TRIG_2 as a trigger source (rw) */
+ Ifx_Strict_32Bit INT_TRIG3:2; /**< \brief [7:6] Select input signal TRIG_3 as a trigger source (rw) */
+ Ifx_Strict_32Bit INT_TRIG4:2; /**< \brief [9:8] Select input signal TRIG_4 as a trigger source (rw) */
+ Ifx_Strict_32Bit INT_TRIG5:2; /**< \brief [11:10] Select input signal TRIG_5 as a trigger source (rw) */
+ Ifx_Strict_32Bit INT_TRIG6:2; /**< \brief [13:12] Select input signal TRIG_6 as a trigger source (rw) */
+ Ifx_Strict_32Bit INT_TRIG7:2; /**< \brief [15:14] Select input signal TRIG_7 as a trigger source (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_TOM_TGC1_INT_TRIG_Bits;
+
+/** \brief TOM TGC1 Output Enable Control Register */
+typedef struct _Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits
+{
+ Ifx_Strict_32Bit OUTEN_CTRL0:2; /**< \brief [1:0] Output (A)TOM_OUT(0) enable/disable update value (rw) */
+ Ifx_Strict_32Bit OUTEN_CTRL1:2; /**< \brief [3:2] Output (A)TOM_OUT(1)enable/disable update value (rw) */
+ Ifx_Strict_32Bit OUTEN_CTRL2:2; /**< \brief [5:4] Output (A)TOM_OUT(2) enable/disable update value (rw) */
+ Ifx_Strict_32Bit OUTEN_CTRL3:2; /**< \brief [7:6] Output (A)TOM_OUT(3) enable/disable update value (rw) */
+ Ifx_Strict_32Bit OUTEN_CTRL4:2; /**< \brief [9:8] Output (A)TOM_OUT(4) enable/disable update value (rw) */
+ Ifx_Strict_32Bit OUTEN_CTRL5:2; /**< \brief [11:10] Output (A)TOM_OUT(5) enable/disable update value (rw) */
+ Ifx_Strict_32Bit OUTEN_CTRL6:2; /**< \brief [13:12] Output (A)TOM_OUT(6) enable/disable update value (rw) */
+ Ifx_Strict_32Bit OUTEN_CTRL7:2; /**< \brief [15:14] Output (A)TOM_OUT(7) enable/disable update value (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits;
+
+/** \brief TOM TGC1 Output Enable Status Register */
+typedef struct _Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits
+{
+ Ifx_Strict_32Bit OUTEN_STAT0:2; /**< \brief [1:0] Control/status of output (A)TOM_OUT(0) (rw) */
+ Ifx_Strict_32Bit OUTEN_STAT1:2; /**< \brief [3:2] Control/status of output (A)TOM_OUT(1) (rw) */
+ Ifx_Strict_32Bit OUTEN_STAT2:2; /**< \brief [5:4] Control/status of output (A)TOM_OUT(2) (rw) */
+ Ifx_Strict_32Bit OUTEN_STAT3:2; /**< \brief [7:6] Control/status of output (A)TOM_OUT(3) (rw) */
+ Ifx_Strict_32Bit OUTEN_STAT4:2; /**< \brief [9:8] Control/status of output (A)TOM_OUT(4) (rw) */
+ Ifx_Strict_32Bit OUTEN_STAT5:2; /**< \brief [11:10] Control/status of output (A)TOM_OUT(5) (rw) */
+ Ifx_Strict_32Bit OUTEN_STAT6:2; /**< \brief [13:12] Control/status of output (A)TOM_OUT(6) (rw) */
+ Ifx_Strict_32Bit OUTEN_STAT7:2; /**< \brief [15:14] Control/status of output (A)TOM_OUT(7) (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits;
+
+/** \brief Trigger Output Register */
+typedef struct _Ifx_GTM_TRIGOUT_Bits
+{
+ Ifx_Strict_32Bit INT0:2; /**< \brief [1:0] Interrupt Trigger Request 0 (w) */
+ Ifx_Strict_32Bit INT1:2; /**< \brief [3:2] Interrupt Trigger Request 1 (w) */
+ Ifx_Strict_32Bit TRIG0:2; /**< \brief [5:4] Trigger 0 (w) */
+ Ifx_Strict_32Bit TRIG1:2; /**< \brief [7:6] Trigger 1 (w) */
+ Ifx_Strict_32Bit TRIG2:2; /**< \brief [9:8] Trigger 2 (w) */
+ Ifx_Strict_32Bit TRIG3:2; /**< \brief [11:10] Trigger 3 (w) */
+ Ifx_Strict_32Bit TRIG4:2; /**< \brief [13:12] Trigger 4 (w) */
+ Ifx_Strict_32Bit TRIG5:2; /**< \brief [15:14] Trigger 5 (w) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_GTM_TRIGOUT_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Gtm_union
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ACCEN0_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ACCEN0;
+
+/** \brief Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ACCEN1_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ACCEN1;
+
+/** \brief ADC Trigger 0 Output Select 0 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ADCTRIG0OUT0_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ADCTRIG0OUT0;
+
+/** \brief ADC Trigger 1 Output Select 0 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ADCTRIG1OUT0_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ADCTRIG1OUT0;
+
+/** \brief GTM AEI Timeout Exception Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_AEI_ADDR_XPT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_AEI_ADDR_XPT;
+
+/** \brief AFD0 FIFO0 Channel Buffer Access Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_AFD_CH_BUF_ACC_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_AFD_CH_BUF_ACC;
+
+/** \brief ARU Access Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ARU_ARU_ACCESS_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ARU_ARU_ACCESS;
+
+/** \brief ARU Access Register Upper Data Word */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ARU_DATA_H_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ARU_DATA_H;
+
+/** \brief ARU Access Register Lower Data Word */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ARU_DATA_L_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ARU_DATA_L;
+
+/** \brief Debug Access Channel 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ARU_DBG_ACCESS0_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ARU_DBG_ACCESS0;
+
+/** \brief Debug Access Channel 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ARU_DBG_ACCESS1_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ARU_DBG_ACCESS1;
+
+/** \brief Debug Access 0 Transfer Register Upper Data Word */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ARU_DBG_DATA0_H_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ARU_DBG_DATA0_H;
+
+/** \brief Debug Access 0 Transfer Register Lower Data Word */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ARU_DBG_DATA0_L_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ARU_DBG_DATA0_L;
+
+/** \brief Debug Access 1 Transfer Register Upper Data Word */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ARU_DBG_DATA1_H_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ARU_DBG_DATA1_H;
+
+/** \brief Debug Access 1 Transfer Register Lower Data Word */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ARU_DBG_DATA1_L_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ARU_DBG_DATA1_L;
+
+/** \brief ARU Interrupt Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ARU_IRQ_EN_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ARU_IRQ_EN;
+
+/** \brief ARU_NEW_DATA_IRQ Forcing Interrupt Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ARU_IRQ_FORCINT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ARU_IRQ_FORCINT;
+
+/** \brief IRQ Mode Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ARU_IRQ_MODE_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ARU_IRQ_MODE;
+
+/** \brief ARU Interrupt Notification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ARU_IRQ_NOTIFY_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ARU_IRQ_NOTIFY;
+
+/** \brief TOM TGC0 Action Time Base Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ATOM_AGC_ACT_TB_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ATOM_AGC_ACT_TB;
+
+/** \brief ATOM AGC Enable/Disable Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ATOM_AGC_ENDIS_CTRL;
+
+/** \brief ATOM AGC Enable/Disable Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ATOM_AGC_ENDIS_STAT;
+
+/** \brief ATOM AGC Force Update Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ATOM_AGC_FUPD_CTRL;
+
+/** \brief ATOM AGC Global control register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ATOM_AGC_GLB_CTRL;
+
+/** \brief ATOM AGC Internal Trigger Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ATOM_AGC_INT_TRIG_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ATOM_AGC_INT_TRIG;
+
+/** \brief ATOM AGC Output Enable Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ATOM_AGC_OUTEN_CTRL;
+
+/** \brief ATOM AGC Output Enable Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ATOM_AGC_OUTEN_STAT;
+
+/** \brief ATOM Channel CCU0 Compare Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ATOM_CH_CM0_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ATOM_CH_CM0;
+
+/** \brief ATOM Channel CCU1 Compare Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ATOM_CH_CM1_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ATOM_CH_CM1;
+
+/** \brief ATOM Channel CCU0 Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ATOM_CH_CN0_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ATOM_CH_CN0;
+
+/** \brief ATOM Channel Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ATOM_CH_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ATOM_CH_CTRL;
+
+/** \brief ATOM Channel Interrupt Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ATOM_CH_IRQ_EN_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ATOM_CH_IRQ_EN;
+
+/** \brief ATOM Channel Software Interrupt Generation Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ATOM_CH_IRQ_FORCINT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ATOM_CH_IRQ_FORCINT;
+
+/** \brief ATOM IRQ Mode Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ATOM_CH_IRQ_MODE_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ATOM_CH_IRQ_MODE;
+
+/** \brief ATOM Channel Interrupt Notification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ATOM_CH_IRQ_NOTIFY_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ATOM_CH_IRQ_NOTIFY;
+
+/** \brief ATOM Channel ARU Read Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ATOM_CH_RDADDR_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ATOM_CH_RDADDR;
+
+/** \brief ATOM Channel Control in SOMC mode Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ATOM_CH_SOMC_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ATOM_CH_SOMC;
+
+/** \brief ATOM Channel Control in SOMI mode Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ATOM_CH_SOMI_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ATOM_CH_SOMI;
+
+/** \brief ATOM Channel Control in SOMP mode Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ATOM_CH_SOMP_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ATOM_CH_SOMP;
+
+/** \brief ATOM Channel Control in SOMS mode Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ATOM_CH_SOMS_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ATOM_CH_SOMS;
+
+/** \brief ATOM Channel CCU0 Compare Shadow Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ATOM_CH_SR0_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ATOM_CH_SR0;
+
+/** \brief ATOM Channel CCU1 Compare Shadow Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ATOM_CH_SR1_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ATOM_CH_SR1;
+
+/** \brief ATOM Channel Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ATOM_CH_STAT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ATOM_CH_STAT;
+
+/** \brief BRC Error Interrupt Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRC_EIRQ_EN_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRC_EIRQ_EN;
+
+/** \brief BRC Interrupt Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRC_IRQ_EN_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRC_IRQ_EN;
+
+/** \brief BRC_DEST_ERR Forcing Interrupt Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRC_IRQ_FORCINT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRC_IRQ_FORCINT;
+
+/** \brief BRC IRQ Mode Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRC_IRQ_MODE_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRC_IRQ_MODE;
+
+/** \brief BRC Interrupt Notification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRC_IRQ_NOTIFY_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRC_IRQ_NOTIFY;
+
+/** \brief BRC Software Reset Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRC_RST_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRC_RST;
+
+/** \brief Read Address For Input Channel 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRC_SRC0_ADDR_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRC_SRC0_ADDR;
+
+/** \brief Destination Channels For Input Channel 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRC_SRC0_DEST_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRC_SRC0_DEST;
+
+/** \brief Read Address For Input Channel 10 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRC_SRC10_ADDR_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRC_SRC10_ADDR;
+
+/** \brief Destination Channels For Input Channel 10 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRC_SRC10_DEST_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRC_SRC10_DEST;
+
+/** \brief Read Address For Input Channel 11 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRC_SRC11_ADDR_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRC_SRC11_ADDR;
+
+/** \brief Destination Channels For Input Channel 11 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRC_SRC11_DEST_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRC_SRC11_DEST;
+
+/** \brief Read Address For Input Channel 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRC_SRC1_ADDR_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRC_SRC1_ADDR;
+
+/** \brief Destination Channels For Input Channel 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRC_SRC1_DEST_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRC_SRC1_DEST;
+
+/** \brief Read Address For Input Channel 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRC_SRC2_ADDR_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRC_SRC2_ADDR;
+
+/** \brief Destination Channels For Input Channel 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRC_SRC2_DEST_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRC_SRC2_DEST;
+
+/** \brief Read Address For Input Channel 3 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRC_SRC3_ADDR_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRC_SRC3_ADDR;
+
+/** \brief Destination Channels For Input Channel 3 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRC_SRC3_DEST_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRC_SRC3_DEST;
+
+/** \brief Read Address For Input Channel 4 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRC_SRC4_ADDR_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRC_SRC4_ADDR;
+
+/** \brief Destination Channels For Input Channel 4 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRC_SRC4_DEST_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRC_SRC4_DEST;
+
+/** \brief Read Address For Input Channel 5 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRC_SRC5_ADDR_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRC_SRC5_ADDR;
+
+/** \brief Destination Channels For Input Channel 5 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRC_SRC5_DEST_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRC_SRC5_DEST;
+
+/** \brief Read Address For Input Channel 6 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRC_SRC6_ADDR_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRC_SRC6_ADDR;
+
+/** \brief Destination Channels For Input Channel 6 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRC_SRC6_DEST_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRC_SRC6_DEST;
+
+/** \brief Read Address For Input Channel 7 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRC_SRC7_ADDR_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRC_SRC7_ADDR;
+
+/** \brief Destination Channels For Input Channel 7 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRC_SRC7_DEST_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRC_SRC7_DEST;
+
+/** \brief Read Address For Input Channel 8 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRC_SRC8_ADDR_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRC_SRC8_ADDR;
+
+/** \brief Destination Channels For Input Channel 8 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRC_SRC8_DEST_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRC_SRC8_DEST;
+
+/** \brief Read Address For Input Channel 9 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRC_SRC9_ADDR_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRC_SRC9_ADDR;
+
+/** \brief Destination Channels For Input Channel 9 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRC_SRC9_DEST_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRC_SRC9_DEST;
+
+/** \brief GTM to SPB BRIDGE MODE */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRIDGE_MODE_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRIDGE_MODE;
+
+/** \brief GTM to SPB BRIDGE PTR1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRIDGE_PTR1_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRIDGE_PTR1;
+
+/** \brief GTM to SPB BRIDGE PTR2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_BRIDGE_PTR2_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_BRIDGE_PTR2;
+
+/** \brief Clock Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_CLC_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_CLC;
+
+/** \brief CMP Error Interrupt Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_CMP_EIRQ_EN_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_CMP_EIRQ_EN;
+
+/** \brief CMP Comparator Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_CMP_EN_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_CMP_EN;
+
+/** \brief CMP Interrupt Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_CMP_IRQ_EN_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_CMP_IRQ_EN;
+
+/** \brief CMP Interrupt Force Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_CMP_IRQ_FORCINT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_CMP_IRQ_FORCINT;
+
+/** \brief CMP IRQ Mode Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_CMP_IRQ_MODE_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_CMP_IRQ_MODE;
+
+/** \brief CMP Event Notification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_CMP_IRQ_NOTIFY_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_CMP_IRQ_NOTIFY;
+
+/** \brief CMU Control For Clock Source Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_CMU_CLK0_5_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_CMU_CLK0_5_CTRL;
+
+/** \brief CMU Control For Clock Source 6 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_CMU_CLK_6_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_CMU_CLK_6_CTRL;
+
+/** \brief CMU Control For Clock Source 7 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_CMU_CLK_7_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_CMU_CLK_7_CTRL;
+
+/** \brief CMU Clock Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_CMU_CLK_EN_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_CMU_CLK_EN;
+
+/** \brief CMU External Clock Control Denominator Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_CMU_ECLK_DEN_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_CMU_ECLK_DEN;
+
+/** \brief CMU External Clock Control Numerator Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_CMU_ECLK_NUM_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_CMU_ECLK_NUM;
+
+/** \brief CMU FXCLK Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_CMU_FXCLK_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_CMU_FXCLK_CTRL;
+
+/** \brief CMU Global Clock Control Denominator Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_CMU_GCLK_DEN_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_CMU_GCLK_DEN;
+
+/** \brief CMU Global Clock Control Numerator Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_CMU_GCLK_NUM_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_CMU_GCLK_NUM;
+
+/** \brief GTM Global Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_CTRL;
+
+/** \brief Data Input 0 0 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DATAIN_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DATAIN;
+
+/** \brief DPLL Action Control i Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_ACB_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_ACB;
+
+/** \brief DPLL ACTION Status Register With Shadow Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_ACT_STA_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_ACT_STA;
+
+/** \brief DPLL Calculated ADD_IN Value for SUB_INC1 Generation */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_ADD_IN_CAL1_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_ADD_IN_CAL1;
+
+/** \brief DPLL Calculated ADD_IN Value for SUB_INC2 Generation */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_ADD_IN_CAL2_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_ADD_IN_CAL2;
+
+/** \brief DPLL Direct Load Input Value for SUB_INC1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_ADD_IN_LD1_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_ADD_IN_LD1;
+
+/** \brief DPLL Direct Load Input Value for SUB_INC1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_ADD_IN_LD2_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_ADD_IN_LD2;
+
+/** \brief DPLL Adapt Values for All STATE Increments */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_ADT_S_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_ADT_S;
+
+/** \brief DPLL Address Offset Register For APT In RAM Region 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_AOSV_2_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_AOSV_2;
+
+/** \brief DPLL Actual RAM Pointer to RAM Regions 1C1, 1C2 and 1C4 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_APS_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_APS;
+
+/** \brief DPLL Actual RAM Pointer to RAM Region 1C3 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_APS_1C3_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_APS_1C3;
+
+/** \brief DPLL Old RAM Pointer and Offset Value for STATE */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_APS_SYNC_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_APS_SYNC;
+
+/** \brief DPLL Actual RAM Pointer to RAM Regions 2A, B and D */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_APT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_APT;
+
+/** \brief DPLL Actual RAM Pointer to RAM Region 2C */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_APT_2C_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_APT_2C;
+
+/** \brief DPLL Old RAM Pointer and Offset Value for TRIGGER */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_APT_SYNC_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_APT_SYNC;
+
+/** \brief DPLL Prediction of the actual STATE Increment */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_CDT_SX_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_CDT_SX;
+
+/** \brief DPLL Prediction of the nominal STATE increment duration */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_CDT_SX_NOM_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_CDT_SX_NOM;
+
+/** \brief DPLL Prediction of the actual TRIGGER Increment */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_CDT_TX_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_CDT_TX;
+
+/** \brief DPLL Prediction of the nominal TRIGGER Increment duration */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_CDT_TX_NOM_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_CDT_TX_NOM;
+
+/** \brief DPLL Number of Sub-Pulses of SUB_INC1 in Continuous Mode */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_CNT_NUM1_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_CNT_NUM1;
+
+/** \brief DPLL Number of Sub-Pulses of SUB_INC2 in Continuous Mode */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_CNT_NUM2_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_CNT_NUM2;
+
+/** \brief DPLL Control 1 Shadow STATE Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE;
+
+/** \brief DPLL Control Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_CTRL_0_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_CTRL_0;
+
+/** \brief DPLL Control 0 Shadow STATE Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_CTRL_0_SHADOW_STATE_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_CTRL_0_SHADOW_STATE;
+
+/** \brief DPLL Control0 Shadow Trigger Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER;
+
+/** \brief DPLL Control Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_CTRL_1_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_CTRL_1;
+
+/** \brief DPLL Control 1 Shadow TRIGGER Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER;
+
+/** \brief DPLL Control Register 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_CTRL_2_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_CTRL_2;
+
+/** \brief DPLL Control Register 3 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_CTRL_3_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_CTRL_3;
+
+/** \brief DPLL Control Register 4 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_CTRL_4_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_CTRL_4;
+
+/** \brief DPLL ACTION Time To React Before PSAi Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_DLA_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_DLA;
+
+/** \brief DPLL Nominal STATE Increment Values for FULL_SCALE */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_DT_S_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_DT_S;
+
+/** \brief DPLL Duration of Last STATE Increment [DT_S_ACT] */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_DT_S_ACT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_DT_S_ACT;
+
+/** \brief DPLL Duration of Last TRIGGER Increment */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_DT_T_ACT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_DT_T_ACT;
+
+/** \brief DPLL Calculated Relative Time To ACTION_i Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_DTA_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_DTA;
+
+/** \brief DPLL Difference of Prediction to actual value for Last STATE
+ * Increment */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_EDT_S_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_EDT_S;
+
+/** \brief DPLL Difference of prediction to actual value of the last TRIGGER
+ * increment */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_EDT_T_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_EDT_T;
+
+/** \brief DPLL Error Interrupt Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_EIRQ_EN_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_EIRQ_EN;
+
+/** \brief DPLL Actual Signal STATE Filter Value Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_FTV_S_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_FTV_S;
+
+/** \brief DPLL Actual Signal TRIGGER Filter Value Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_FTV_T_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_FTV_T;
+
+/** \brief DPLL ID Information For Input Signal PMTR Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_ID_PMTR_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_ID_PMTR;
+
+/** \brief DPLL Counter for Pulses for TBU_TS1 to be sent in Automatic End Mode */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_INC_CNT1_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_INC_CNT1;
+
+/** \brief DPLL Counter for Pulses for TBU_TS2 to be sent in Automatic End Mode
+ * when SMC=RMO=1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_INC_CNT2_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_INC_CNT2;
+
+/** \brief DPLL Interrupt Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_IRQ_EN_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_IRQ_EN;
+
+/** \brief DPLL Interrupt Force Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_IRQ_FORCINT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_IRQ_FORCINT;
+
+/** \brief DPLL Interrupt Mode Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_IRQ_MODE_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_IRQ_MODE;
+
+/** \brief DPLL Interrupt Notification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_IRQ_NOTIFY_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_IRQ_NOTIFY;
+
+/** \brief DPLL Weighted difference of Prediction up to the Last STATE
+ * Increment */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_MEDT_S_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_MEDT_S;
+
+/** \brief DPLL Weighted difference of Prediction up to the Last TRIGGER
+ * Increment */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_MEDT_T_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_MEDT_T;
+
+/** \brief DPLL Calculated Number of Sub-Pulses between Two STATE Events */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_MLS1_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_MLS1;
+
+/** \brief DPLL Calculated Number of Sub-Pulses between Two STATE Events */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_MLS2_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_MLS2;
+
+/** \brief DPLL Missing Pulses to be Added/Subtracted Directly to SUB_INC1 and
+ * INC_CNT1 Once */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_MPVAL1_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_MPVAL1;
+
+/** \brief DPLL Missing Pulses to be Added/Subtracted Directly to SUB_INC2 and
+ * INC_CNT2 Once */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_MPVAL2_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_MPVAL2;
+
+/** \brief DPLL Calculated Number Of TRIGGER/STATE Increments To ACTION */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_NA_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_NA;
+
+/** \brief DPLL Number of Pulses of Current Increment in Emergency Mode */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_NMB_S_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_NMB_S;
+
+/** \brief DPLL Target Number of Pulses to be sent in emergency mode Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_NMB_S_TAR_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_NMB_S_TAR;
+
+/** \brief DPLL Target Number of Pulses to be sent in emergency mode Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_NMB_S_TAR_OLD_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_NMB_S_TAR_OLD;
+
+/** \brief DPLL Number of Pulses of Current Increment in Normal Mode */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_NMB_T_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_NMB_T;
+
+/** \brief DPLL Target Number of Pulses to be sent in normal mode Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_NMB_T_TAR_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_NMB_T_TAR;
+
+/** \brief DPLL Target Number of Pulses to be sent in normal mode Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_NMB_T_TAR_OLD_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_NMB_T_TAR_OLD;
+
+/** \brief DPLL Number of Active TRIGGER Events to Interrupt */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_NTI_CNT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_NTI_CNT;
+
+/** \brief DPLL Number of Recent STATE Events Used for Calculations */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_NUSC_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_NUSC;
+
+/** \brief DPLL Number of Recent TRIGGER Events Used for Calculations */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_NUTC_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_NUTC;
+
+/** \brief DPLL Offset And Switch Old/New Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_OSW_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_OSW;
+
+/** \brief DPLL Projected TRIGGER Increment Sum Relations for Action_i */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_PDT_T_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_PDT_T;
+
+/** \brief DPLL ACTION Position/Value Action Request Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_PSA_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_PSA;
+
+/** \brief DPLL Calculated Position Value Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_PSAC_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_PSAC;
+
+/** \brief DPLL Accurate Calculated Position Stamp of Last STATE Input */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_PSSC_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_PSSC;
+
+/** \brief DPLL Measured Position Stamp of Last STATE Input */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_PSSM_0_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_PSSM_0;
+
+/** \brief DPLL Measured Position Stamp of Last STATE Input */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_PSSM_1_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_PSSM_1;
+
+/** \brief DPLL Actual Calculated Position Stamp of Last TRIGGER Input */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_PSTC_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_PSTC;
+
+/** \brief DPLL Measured Position Stamp of Last TRIGGER Input */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_PSTM_0_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_PSTM_0;
+
+/** \brief DPLL Measured Position Stamp of Last TRIGGER Input */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_PSTM_1_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_PSTM_1;
+
+/** \brief DPLL Plausibility Value of Next Active TRIGGER Slope */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_PVT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_PVT;
+
+/** \brief DPLL RAM Initatlisation Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_RAM_INI_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_RAM_INI;
+
+/** \brief DPLL Reciprocal Value of Expected Increment Duration STATE */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_RCDT_SX_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_RCDT_SX;
+
+/** \brief DPLL Reciprocal Value of the Expected Nominal Increment Duration
+ * STATE */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_RCDT_SX_NOM_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_RCDT_SX_NOM;
+
+/** \brief DPLL Reciprocal Value of Expected Increment Duration TRIGGER */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_RCDT_TX_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_RCDT_TX;
+
+/** \brief DPLL Reciprocal Value of the Expected Nominal Increment Duration
+ * TRIGGER */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_RCDT_TX_NOM_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_RCDT_TX_NOM;
+
+/** \brief DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_RDT_S_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_RDT_S;
+
+/** \brief DPLL Actual Reciprocal Value of STATE */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_RDT_S_ACT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_RDT_S_ACT;
+
+/** \brief DPLL Actual Reciprocal Value of TRIGGER */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_RDT_T_ACT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_RDT_T_ACT;
+
+/** \brief DPLL STATE Locking Range */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_SLR_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_SLR;
+
+/** \brief DPLL Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_STATUS_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_STATUS;
+
+/** \brief DPLL TBU_TS0 Value at last STATE Event */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_TBU_TS0_S_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_TBU_TS0_S;
+
+/** \brief DPLL TBU_TS0 Value at last TRIGGER Event */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_TBU_TS0_T_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_TBU_TS0_T;
+
+/** \brief DPLL TRIGGER Hold Time Max Value */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_THMA_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_THMA;
+
+/** \brief DPLL TRIGGER hold time min value */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_THMI_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_THMI;
+
+/** \brief DPLL Measured Last Pulse Time from Valid to Invalid TRIGGER Slope */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_THVAL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_THVAL;
+
+/** \brief DPLL TRIGGER locking range */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_TLR_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_TLR;
+
+/** \brief DPLL Time Out Value of active TRIGGER Slope */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_TOV_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_TOV;
+
+/** \brief DPLL Time Out Value of active STATE Slope */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_TOV_S_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_TOV_S;
+
+/** \brief DPLL Actual Signal STATE Time Stamp Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_TS_S_0_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_TS_S_0;
+
+/** \brief DPLL Actual Signal STATE Time Stamp Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_TS_S_1_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_TS_S_1;
+
+/** \brief DPLL Actual Signal TRIGGER Time Stamp Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_TS_T_0_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_TS_T_0;
+
+/** \brief DPLL Actual Signal TRIGGER Time Stamp Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_TS_T_1_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_TS_T_1;
+
+/** \brief DPLL Calculate Time Stamp Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_TSAC_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_TSAC;
+
+/** \brief DPLL Time Stamp Field of STATE Events */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DPLL_TSF_S_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DPLL_TSF_S;
+
+/** \brief Data Exchange Input Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DXINCON_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DXINCON;
+
+/** \brief Data Exchange Output Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_DXOUTCON_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_DXOUTCON;
+
+/** \brief GTM Error Interrupt Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_EIRQ_EN_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_EIRQ_EN;
+
+/** \brief F2A0 Stream Activation Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_F2A_ENABLE_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_F2A_ENABLE;
+
+/** \brief F2A Read Channel Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_F2A_RD_CH_ARU_RD_FIFO_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_F2A_RD_CH_ARU_RD_FIFO;
+
+/** \brief F2A Stream Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_F2A_STR_CH_STR_CFG_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_F2A_STR_CH_STR_CFG;
+
+/** \brief FIFO0 Channel Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_FIFO_CH_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_FIFO_CH_CTRL;
+
+/** \brief FIFO0 Channel Error Interrupt Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_FIFO_CH_EIRQ_EN_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_FIFO_CH_EIRQ_EN;
+
+/** \brief FIFO0 Channel End Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_FIFO_CH_END_ADDR_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_FIFO_CH_END_ADDR;
+
+/** \brief FIFO0 Channel Fill Level Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_FIFO_CH_FILL_LEVEL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_FIFO_CH_FILL_LEVEL;
+
+/** \brief FIFO0 Channel Interrupt Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_FIFO_CH_IRQ_EN_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_FIFO_CH_IRQ_EN;
+
+/** \brief FIFO0 Channel Force Interrupt By Software Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_FIFO_CH_IRQ_FORCINT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_FIFO_CH_IRQ_FORCINT;
+
+/** \brief FIFO0 Channel IRQ Mode Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_FIFO_CH_IRQ_MODE_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_FIFO_CH_IRQ_MODE;
+
+/** \brief FIFO0 Channel Interrupt Notification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_FIFO_CH_IRQ_NOTIFY_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_FIFO_CH_IRQ_NOTIFY;
+
+/** \brief FIFO0 Channel Lower Watermark Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_FIFO_CH_LOWER_WM_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_FIFO_CH_LOWER_WM;
+
+/** \brief FIFO0 Channel Read Pointer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_FIFO_CH_RD_PTR_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_FIFO_CH_RD_PTR;
+
+/** \brief FIFO0 Channel Start Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_FIFO_CH_START_ADDR_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_FIFO_CH_START_ADDR;
+
+/** \brief FIFO0 Channel Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_FIFO_CH_STATUS_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_FIFO_CH_STATUS;
+
+/** \brief FIFO0 Channel Upper Watermark Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_FIFO_CH_UPPER_WM_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_FIFO_CH_UPPER_WM;
+
+/** \brief FIFO0 Channel Write Pointer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_FIFO_CH_WR_PTR_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_FIFO_CH_WR_PTR;
+
+/** \brief GTM Infrastructure Interrupt Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ICM_IRQG_0_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ICM_IRQG_0;
+
+/** \brief GTM DPLL Interrupt Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ICM_IRQG_1_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ICM_IRQG_1;
+
+/** \brief TIM Interrupt Group 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ICM_IRQG_2_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ICM_IRQG_2;
+
+/** \brief MCS Interrupt Group 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ICM_IRQG_4_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ICM_IRQG_4;
+
+/** \brief TOM Interrupt Group 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ICM_IRQG_6_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ICM_IRQG_6;
+
+/** \brief ATOM Interrupt Group 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ICM_IRQG_9_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ICM_IRQG_9;
+
+/** \brief ICM Channel Error Interrupt 0 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ICM_IRQG_CEI0_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ICM_IRQG_CEI0;
+
+/** \brief ICM Channel Error Interrupt 1 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ICM_IRQG_CEI1_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ICM_IRQG_CEI1;
+
+/** \brief ICM Channel Error Interrupt 3 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ICM_IRQG_CEI3_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ICM_IRQG_CEI3;
+
+/** \brief ICM Module Error Interrupt Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ICM_IRQG_MEI_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ICM_IRQG_MEI;
+
+/** \brief CAN Output Select Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_INOUTSEL_CAN_OUTSEL;
+
+/** \brief DSADC Input Select Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_INOUTSEL_DSADC_INSEL;
+
+/** \brief DSADC Output Select Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_INOUTSEL_DSADC_OUTSEL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_INOUTSEL_DSADC_OUTSEL;
+
+/** \brief PSI5 Output Select 0 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_INOUTSEL_PSI5_OUTSEL0;
+
+/** \brief PSI5-S Output Select Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_INOUTSEL_PSI5S_OUTSEL;
+
+/** \brief Timer Output Select Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_INOUTSEL_T_OUTSEL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_INOUTSEL_T_OUTSEL;
+
+/** \brief TIM Input Select Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_INOUTSEL_TIM_INSEL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_INOUTSEL_TIM_INSEL;
+
+/** \brief GTM Interrupt Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_IRQ_EN_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_IRQ_EN;
+
+/** \brief GTM Software Interrupt Generation Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_IRQ_FORCINT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_IRQ_FORCINT;
+
+/** \brief GTM Top Level Interrupts Mode Selection */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_IRQ_MODE_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_IRQ_MODE;
+
+/** \brief GTM Interrupt Notification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_IRQ_NOTIFY_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_IRQ_NOTIFY;
+
+/** \brief Kernel Reset Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_KRST0_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_KRST0;
+
+/** \brief Kernel Reset Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_KRST1_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_KRST1;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_KRSTCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_KRSTCLR;
+
+/** \brief MAP Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MAP_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MAP_CTRL;
+
+/** \brief Memory Layout Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MCFG_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MCFG_CTRL;
+
+/** \brief MCS Clear Trigger Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MCS_CH0_CTRG_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MCS_CH0_CTRG;
+
+/** \brief MCS Set Trigger Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MCS_CH0_STRG_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MCS_CH0_STRG;
+
+/** \brief MCS Channel ACB Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MCS_CH_ACB_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MCS_CH_ACB;
+
+/** \brief MCS Channel Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MCS_CH_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MCS_CH_CTRL;
+
+/** \brief MCS_Channel Error Interrupt Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MCS_CH_EIRQ_EN_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MCS_CH_EIRQ_EN;
+
+/** \brief MCS Channel Interrupt Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MCS_CH_IRQ_EN_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MCS_CH_IRQ_EN;
+
+/** \brief MCS Channel Software Interrupt Generation Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MCS_CH_IRQ_FORCINT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MCS_CH_IRQ_FORCINT;
+
+/** \brief MCS IRQ Mode Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MCS_CH_IRQ_MODE_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MCS_CH_IRQ_MODE;
+
+/** \brief MCS Channel interrupt notification register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MCS_CH_IRQ_NOTIFY_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MCS_CH_IRQ_NOTIFY;
+
+/** \brief MCS Channel Program Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MCS_CH_PC_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MCS_CH_PC;
+
+/** \brief MCS Channel Program Counter Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MCS_CH_R0_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MCS_CH_R0;
+
+/** \brief MCS Channel Program Counter Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MCS_CH_R1_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MCS_CH_R1;
+
+/** \brief MCS Channel Program Counter Register 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MCS_CH_R2_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MCS_CH_R2;
+
+/** \brief MCS Channel Program Counter Register 3 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MCS_CH_R3_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MCS_CH_R3;
+
+/** \brief MCS Channel Program Counter Register 4 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MCS_CH_R4_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MCS_CH_R4;
+
+/** \brief MCS Channel Program Counter Register 5 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MCS_CH_R5_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MCS_CH_R5;
+
+/** \brief MCS Channel Program Counter Register 6 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MCS_CH_R6_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MCS_CH_R6;
+
+/** \brief MCS Channel Program Counter Register 7 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MCS_CH_R7_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MCS_CH_R7;
+
+/** \brief MCS Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MCS_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MCS_CTRL;
+
+/** \brief MCS Error Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MCS_ERR_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MCS_ERR;
+
+/** \brief MCS Channel Reset Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MCS_RST_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MCS_RST;
+
+/** \brief MCS Interrupt Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MCSINTCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MCSINTCLR;
+
+/** \brief MCS Interrupt Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MCSINTSTAT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MCSINTSTAT;
+
+/** \brief Monitor Activity Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MON_ACTIVITY_0_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MON_ACTIVITY_0;
+
+/** \brief Monitor Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MON_STATUS_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MON_STATUS;
+
+/** \brief MSC0 Input Low Extended Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MSC0INLEXTCON_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MSC0INLEXTCON;
+
+/** \brief MSC Input High Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MSCIN_INHCON_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MSCIN_INHCON;
+
+/** \brief MSC Input Low Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MSCIN_INLCON_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MSCIN_INLCON;
+
+/** \brief MSC Set Control 0 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MSCSET_CON0_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MSCSET_CON0;
+
+/** \brief MSC Set Control 1 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MSCSET_CON1_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MSCSET_CON1;
+
+/** \brief MSC Set Control 2 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MSCSET_CON2_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MSCSET_CON2;
+
+/** \brief MSC Set Control 3 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_MSCSET_CON3_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_MSCSET_CON3;
+
+/** \brief OCDS Control and Status */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_OCS_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_OCS;
+
+/** \brief OCDS Debug Access Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_ODA_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_ODA;
+
+/** \brief OCDS TBU0 Trigger Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_OTBU0T_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_OTBU0T;
+
+/** \brief OCDS TBU1 Trigger Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_OTBU1T_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_OTBU1T;
+
+/** \brief OCDS TBU2 Trigger Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_OTBU2T_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_OTBU2T;
+
+/** \brief OCDS Trigger Set Control 0 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_OTSC0_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_OTSC0;
+
+/** \brief OCDS Trigger Set Control 1 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_OTSC1_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_OTSC1;
+
+/** \brief OCDS Trigger Set Select Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_OTSS_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_OTSS;
+
+/** \brief GTM Version Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_REV_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_REV;
+
+/** \brief GTM Global Reset Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_RST_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_RST;
+
+/** \brief SPE Revolution Compare Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_SPE_CMP_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_SPE_CMP;
+
+/** \brief SPE Revolution Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_SPE_CNT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_SPE_CNT;
+
+/** \brief SPE Control Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_SPE_CTRL_STAT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_SPE_CTRL_STAT;
+
+/** \brief SPE Error Interrupt Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_SPE_EIRQ_EN_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_SPE_EIRQ_EN;
+
+/** \brief SPE Interrupt Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_SPE_IRQ_EN_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_SPE_IRQ_EN;
+
+/** \brief SPE Interrupt Generation by Software */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_SPE_IRQ_FORCINT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_SPE_IRQ_FORCINT;
+
+/** \brief SPE IRQ Mode Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_SPE_IRQ_MODE_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_SPE_IRQ_MODE;
+
+/** \brief SPE Interrupt Notification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_SPE_IRQ_NOTIFY_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_SPE_IRQ_NOTIFY;
+
+/** \brief SPE Output Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_SPE_OUT_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_SPE_OUT_CTRL;
+
+/** \brief SPE Output Definition Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_SPE_OUT_PAT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_SPE_OUT_PAT;
+
+/** \brief SPE Input Pattern Definition Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_SPE_PAT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_SPE_PAT;
+
+/** \brief TBU Channel 0 Base Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TBU_CH0_BASE_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TBU_CH0_BASE;
+
+/** \brief TBU Channel 0 Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TBU_CH0_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TBU_CH0_CTRL;
+
+/** \brief TBU Channel 1 Base Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TBU_CH1_BASE_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TBU_CH1_BASE;
+
+/** \brief TBU Channel 1 Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TBU_CH1_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TBU_CH1_CTRL;
+
+/** \brief TBU Channel 2 Base Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TBU_CH2_BASE_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TBU_CH2_BASE;
+
+/** \brief TBU Channel 2 Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TBU_CH2_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TBU_CH2_CTRL;
+
+/** \brief TBU Global Channel Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TBU_CHEN_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TBU_CHEN;
+
+/** \brief GTM TIM AUX_IN_SRC */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TIM_AUX_IN_SRC_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TIM_AUX_IN_SRC;
+
+/** \brief TIM Channel SMU Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TIM_CH_CNT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TIM_CH_CNT;
+
+/** \brief TIM Channel SMU Shadow Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TIM_CH_CNTS_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TIM_CH_CNTS;
+
+/** \brief TIM Channel Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TIM_CH_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TIM_CH_CTRL;
+
+/** \brief TIM Channel Edge Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TIM_CH_ECNT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TIM_CH_ECNT;
+
+/** \brief TIM Channel External Capture Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TIM_CH_ECTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TIM_CH_ECTRL;
+
+/** \brief TIM Channel Error Interrupt Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TIM_CH_EIRQ_EN_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TIM_CH_EIRQ_EN;
+
+/** \brief TIM Channel Filter Parameter 1 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TIM_CH_FLT_FE_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TIM_CH_FLT_FE;
+
+/** \brief GTM_TIM Channel Filter Parameter 0 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TIM_CH_FLT_RE_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TIM_CH_FLT_RE;
+
+/** \brief TIM Channel General Purpose 0 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TIM_CH_GPR0_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TIM_CH_GPR0;
+
+/** \brief TIM Channel General Purpose 1 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TIM_CH_GPR1_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TIM_CH_GPR1;
+
+/** \brief TIM Channel Interrupt Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TIM_CH_IRQ_EN_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TIM_CH_IRQ_EN;
+
+/** \brief TIM Channel Software Interrupt Force Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TIM_CH_IRQ_FORCINT;
+
+/** \brief TIM IRQ Mode Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TIM_CH_IRQ_MODE_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TIM_CH_IRQ_MODE;
+
+/** \brief TIM Channel Interrupt Notification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TIM_CH_IRQ_NOTIFY;
+
+/** \brief TIM Channel TDUC Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TIM_CH_TDUC_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TIM_CH_TDUC;
+
+/** \brief TIM Channel TDUV Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TIM_CH_TDUV_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TIM_CH_TDUV;
+
+/** \brief TIM_IN_SRC Long Name */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TIM_IN_SRC_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TIM_IN_SRC;
+
+/** \brief TIM Global Software Reset Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TIM_RST_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TIM_RST;
+
+/** \brief TOM Channel CCU0 Compare Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TOM_CH_CM0_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TOM_CH_CM0;
+
+/** \brief TOM Channel CCU1 Compare Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TOM_CH_CM1_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TOM_CH_CM1;
+
+/** \brief TOM Channel CCU0 Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TOM_CH_CN0_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TOM_CH_CN0;
+
+/** \brief TOM Channel Control Register鈥� */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TOM_CH_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TOM_CH_CTRL;
+
+/** \brief TOM Channel Interrupt Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TOM_CH_IRQ_EN_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TOM_CH_IRQ_EN;
+
+/** \brief TOM Channel Software Interrupt Generation Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TOM_CH_IRQ_FORCINT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TOM_CH_IRQ_FORCINT;
+
+/** \brief TOM IRQ Mode Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TOM_CH_IRQ_MODE_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TOM_CH_IRQ_MODE;
+
+/** \brief TOM Channel Interrupt Notification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TOM_CH_IRQ_NOTIFY_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TOM_CH_IRQ_NOTIFY;
+
+/** \brief TOM Channel CCU0 Compare Shadow Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TOM_CH_SR0_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TOM_CH_SR0;
+
+/** \brief TOM Channel CCU1 Compare Shadow Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TOM_CH_SR1_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TOM_CH_SR1;
+
+/** \brief TOM Channel Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TOM_CH_STAT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TOM_CH_STAT;
+
+/** \brief TOM TGC0 Action Time Base Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TOM_TGC0_ACT_TB_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TOM_TGC0_ACT_TB;
+
+/** \brief TOM TGC0 Enable/Disable Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TOM_TGC0_ENDIS_CTRL;
+
+/** \brief TOM TGC0 Enable/Disable Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TOM_TGC0_ENDIS_STAT;
+
+/** \brief TOM TGC0 Force Update Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TOM_TGC0_FUPD_CTRL;
+
+/** \brief TOM TGC0 Global Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TOM_TGC0_GLB_CTRL;
+
+/** \brief TOM TGC0 Internal Trigger Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TOM_TGC0_INT_TRIG_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TOM_TGC0_INT_TRIG;
+
+/** \brief TOM TGC0 Output Enable Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TOM_TGC0_OUTEN_CTRL;
+
+/** \brief TOM TGC0 Output Enable Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TOM_TGC0_OUTEN_STAT;
+
+/** \brief TOM TGC1 Action Time Base Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TOM_TGC1_ACT_TB_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TOM_TGC1_ACT_TB;
+
+/** \brief TOM TGC1 Enable/Disable Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TOM_TGC1_ENDIS_CTRL;
+
+/** \brief TOM TGC1 Enable/Disable Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TOM_TGC1_ENDIS_STAT;
+
+/** \brief TOM TGC1 Force Update Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TOM_TGC1_FUPD_CTRL;
+
+/** \brief TOM TGC1 Global Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TOM_TGC1_GLB_CTRL;
+
+/** \brief TOM TGC1 Internal Trigger Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TOM_TGC1_INT_TRIG_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TOM_TGC1_INT_TRIG;
+
+/** \brief TOM TGC1 Output Enable Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TOM_TGC1_OUTEN_CTRL;
+
+/** \brief TOM TGC1 Output Enable Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TOM_TGC1_OUTEN_STAT;
+
+/** \brief Trigger Output Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_GTM_TRIGOUT_Bits B; /**< \brief Bitfield access */
+} Ifx_GTM_TRIGOUT;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Gtm_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L2
+ * \{ */
+
+/** \brief AFD FIFO channel objects */
+typedef volatile struct _Ifx_GTM_AFD_CH
+{
+ Ifx_GTM_AFD_CH_BUF_ACC BUF_ACC; /**< \brief 0, AFD0 FIFO0 Channel Buffer Access Register */
+ unsigned char reserved_4[12]; /**< \brief 4, \internal Reserved */
+} Ifx_GTM_AFD_CH;
+
+/** \brief ACG object */
+typedef volatile struct _Ifx_GTM_ATOM_AGC
+{
+ Ifx_GTM_ATOM_AGC_GLB_CTRL GLB_CTRL; /**< \brief 0, ATOM AGC Global control register */
+ Ifx_GTM_ATOM_AGC_ENDIS_CTRL ENDIS_CTRL; /**< \brief 4, ATOM AGC Enable/Disable Control Register */
+ Ifx_GTM_ATOM_AGC_ENDIS_STAT ENDIS_STAT; /**< \brief 8, ATOM AGC Enable/Disable Status Register */
+ Ifx_GTM_ATOM_AGC_ACT_TB ACT_TB; /**< \brief C, TOM TGC0 Action Time Base Register */
+ Ifx_GTM_ATOM_AGC_OUTEN_CTRL OUTEN_CTRL; /**< \brief 10, ATOM AGC Output Enable Control Register */
+ Ifx_GTM_ATOM_AGC_OUTEN_STAT OUTEN_STAT; /**< \brief 14, ATOM AGC Output Enable Status Register */
+ Ifx_GTM_ATOM_AGC_FUPD_CTRL FUPD_CTRL; /**< \brief 18, ATOM AGC Force Update Control Register */
+ Ifx_GTM_ATOM_AGC_INT_TRIG INT_TRIG; /**< \brief 1C, ATOM AGC Internal Trigger Control Register */
+ unsigned char reserved_20[32]; /**< \brief 20, \internal Reserved */
+} Ifx_GTM_ATOM_AGC;
+
+/** \brief ATOM channel objects */
+typedef volatile struct _Ifx_GTM_ATOM_CH
+{
+ Ifx_GTM_ATOM_CH_RDADDR RDADDR; /**< \brief 0, ATOM Channel ARU Read Address Register */
+ union
+ {
+ Ifx_GTM_ATOM_CH_CTRL CTRL; /**< \brief 4, ATOM Channel Control in SOMI mode Register */
+ Ifx_GTM_ATOM_CH_SOMC SOMC; /**< \brief 4, ATOM Channel Control in SOMI mode Register */
+ Ifx_GTM_ATOM_CH_SOMI SOMI; /**< \brief 4, ATOM Channel Control in SOMI mode Register */
+ Ifx_GTM_ATOM_CH_SOMP SOMP; /**< \brief 4, ATOM Channel Control in SOMI mode Register */
+ Ifx_GTM_ATOM_CH_SOMS SOMS; /**< \brief 4, ATOM Channel Control in SOMI mode Register */
+ };
+
+ Ifx_GTM_ATOM_CH_SR0 SR0; /**< \brief 8, ATOM Channel CCU0 Compare Shadow Register */
+ Ifx_GTM_ATOM_CH_SR1 SR1; /**< \brief C, ATOM Channel CCU1 Compare Shadow Register */
+ Ifx_GTM_ATOM_CH_CM0 CM0; /**< \brief 10, ATOM Channel CCU0 Compare Register */
+ Ifx_GTM_ATOM_CH_CM1 CM1; /**< \brief 14, ATOM Channel CCU1 Compare Register */
+ Ifx_GTM_ATOM_CH_CN0 CN0; /**< \brief 18, ATOM Channel CCU0 Counter Register */
+ Ifx_GTM_ATOM_CH_STAT STAT; /**< \brief 1C, ATOM Channel Status Register */
+ Ifx_GTM_ATOM_CH_IRQ_NOTIFY IRQ_NOTIFY; /**< \brief 20, ATOM Channel Interrupt Notification Register */
+ Ifx_GTM_ATOM_CH_IRQ_EN IRQ_EN; /**< \brief 24, ATOM Channel Interrupt Enable Register */
+ Ifx_GTM_ATOM_CH_IRQ_FORCINT IRQ_FORCINT; /**< \brief 28, ATOM Channel Software Interrupt Generation Register */
+ Ifx_GTM_ATOM_CH_IRQ_MODE IRQ_MODE; /**< \brief 2C, ATOM IRQ Mode Configuration Register */
+ unsigned char reserved_30[16]; /**< \brief 30, \internal Reserved */
+} Ifx_GTM_ATOM_CH;
+
+/** \brief CLK objects */
+typedef volatile struct _Ifx_GTM_CMU_CLK0_5
+{
+ Ifx_GTM_CMU_CLK0_5_CTRL CTRL; /**< \brief 0, CMU Control For Clock Source Register */
+} Ifx_GTM_CMU_CLK0_5;
+
+/** \brief CLK objects */
+typedef volatile struct _Ifx_GTM_CMU_CLK_6
+{
+ Ifx_GTM_CMU_CLK_6_CTRL CTRL; /**< \brief 0, CMU Control For Clock Source 6 Register */
+} Ifx_GTM_CMU_CLK_6;
+
+/** \brief CLK objects */
+typedef volatile struct _Ifx_GTM_CMU_CLK_7
+{
+ Ifx_GTM_CMU_CLK_7_CTRL CTRL; /**< \brief 0, CMU Control For Clock Source 7 Register */
+} Ifx_GTM_CMU_CLK_7;
+
+/** \brief ECLK objects */
+typedef volatile struct _Ifx_GTM_CMU_ECLK
+{
+ Ifx_GTM_CMU_ECLK_NUM NUM; /**< \brief 0, CMU External Clock Control Numerator Register */
+ Ifx_GTM_CMU_ECLK_DEN DEN; /**< \brief 4, CMU External Clock Control Denominator Register */
+} Ifx_GTM_CMU_ECLK;
+
+/** \brief FXCLK objects */
+typedef volatile struct _Ifx_GTM_CMU_FXCLK
+{
+ Ifx_GTM_CMU_FXCLK_CTRL CTRL; /**< \brief 0, CMU FXCLK Control Register */
+} Ifx_GTM_CMU_FXCLK;
+
+/** \brief F2A ARU RD FIFO address */
+typedef volatile struct _Ifx_GTM_F2A_RD_CH
+{
+ Ifx_GTM_F2A_RD_CH_ARU_RD_FIFO ARU_RD_FIFO; /**< \brief 0, F2A Read Channel Address Register */
+} Ifx_GTM_F2A_RD_CH;
+
+/** \brief F2A Stream configuration */
+typedef volatile struct _Ifx_GTM_F2A_STR_CH
+{
+ Ifx_GTM_F2A_STR_CH_STR_CFG STR_CFG; /**< \brief 0, F2A Stream Configuration Register */
+} Ifx_GTM_F2A_STR_CH;
+
+/** \brief FIFO channel */
+typedef volatile struct _Ifx_GTM_FIFO_CH
+{
+ Ifx_GTM_FIFO_CH_CTRL CTRL; /**< \brief 0, FIFO0 Channel Control Register */
+ Ifx_GTM_FIFO_CH_END_ADDR END_ADDR; /**< \brief 4, FIFO0 Channel End Address Register */
+ Ifx_GTM_FIFO_CH_START_ADDR START_ADDR; /**< \brief 8, FIFO0 Channel Start Address Register */
+ Ifx_GTM_FIFO_CH_UPPER_WM UPPER_WM; /**< \brief C, FIFO0 Channel Upper Watermark Register */
+ Ifx_GTM_FIFO_CH_LOWER_WM LOWER_WM; /**< \brief 10, FIFO0 Channel Lower Watermark Register */
+ Ifx_GTM_FIFO_CH_STATUS STATUS; /**< \brief 14, FIFO0 Channel Status Register */
+ Ifx_GTM_FIFO_CH_FILL_LEVEL FILL_LEVEL; /**< \brief 18, FIFO0 Channel Fill Level Register */
+ Ifx_GTM_FIFO_CH_WR_PTR WR_PTR; /**< \brief 1C, FIFO0 Channel Write Pointer Register */
+ Ifx_GTM_FIFO_CH_RD_PTR RD_PTR; /**< \brief 20, FIFO0 Channel Read Pointer Register */
+ Ifx_GTM_FIFO_CH_IRQ_NOTIFY IRQ_NOTIFY; /**< \brief 24, FIFO0 Channel Interrupt Notification Register */
+ Ifx_GTM_FIFO_CH_IRQ_EN IRQ_EN; /**< \brief 28, FIFO0 Channel Interrupt Enable Register */
+ Ifx_GTM_FIFO_CH_IRQ_FORCINT IRQ_FORCINT; /**< \brief 2C, FIFO0 Channel Force Interrupt By Software Register */
+ Ifx_GTM_FIFO_CH_IRQ_MODE IRQ_MODE; /**< \brief 30, FIFO0 Channel IRQ Mode Control Register */
+ Ifx_GTM_FIFO_CH_EIRQ_EN EIRQ_EN; /**< \brief 34, FIFO0 Channel Error Interrupt Enable Register */
+ unsigned char reserved_38[8]; /**< \brief 38, \internal Reserved */
+} Ifx_GTM_FIFO_CH;
+
+/** \brief CAN */
+typedef volatile struct _Ifx_GTM_INOUTSEL_CAN
+{
+ Ifx_GTM_INOUTSEL_CAN_OUTSEL OUTSEL; /**< \brief 0, CAN Output Select Register */
+} Ifx_GTM_INOUTSEL_CAN;
+
+/** \brief DSADC */
+typedef volatile struct _Ifx_GTM_INOUTSEL_DSADC
+{
+ Ifx_GTM_INOUTSEL_DSADC_INSEL INSEL[3]; /**< \brief 0, DSADC Input Select Register */
+ Ifx_GTM_INOUTSEL_DSADC_OUTSEL OUTSEL00; /**< \brief C, DSADC Output Select 00 Register */
+ unsigned char reserved_10[4]; /**< \brief 10, \internal Reserved */
+ Ifx_GTM_INOUTSEL_DSADC_OUTSEL OUTSEL10; /**< \brief 14, DSADC Output Select 10 Register */
+} Ifx_GTM_INOUTSEL_DSADC;
+
+/** \brief PSI5 */
+typedef volatile struct _Ifx_GTM_INOUTSEL_PSI5
+{
+ Ifx_GTM_INOUTSEL_PSI5_OUTSEL0 OUTSEL0; /**< \brief 0, PSI5 Output Select 0 Register */
+} Ifx_GTM_INOUTSEL_PSI5;
+
+/** \brief PSI5S */
+typedef volatile struct _Ifx_GTM_INOUTSEL_PSI5S
+{
+ Ifx_GTM_INOUTSEL_PSI5S_OUTSEL OUTSEL; /**< \brief 0, PSI5-S Output Select Register */
+} Ifx_GTM_INOUTSEL_PSI5S;
+
+/** \brief Timer */
+typedef volatile struct _Ifx_GTM_INOUTSEL_T
+{
+ Ifx_GTM_INOUTSEL_T_OUTSEL OUTSEL[10]; /**< \brief 0, Timer Output Select Register */
+} Ifx_GTM_INOUTSEL_T;
+
+/** \brief TIM */
+typedef volatile struct _Ifx_GTM_INOUTSEL_TIM
+{
+ Ifx_GTM_INOUTSEL_TIM_INSEL INSEL; /**< \brief 0, TIM Input Select Register */
+} Ifx_GTM_INOUTSEL_TIM;
+
+/** \brief MCS channel objects */
+typedef volatile struct _Ifx_GTM_MCS_CH
+{
+ Ifx_GTM_MCS_CH_R0 R0; /**< \brief 0, MCS Channel Program Counter Register 0 */
+ Ifx_GTM_MCS_CH_R1 R1; /**< \brief 4, MCS Channel Program Counter Register 1 */
+ Ifx_GTM_MCS_CH_R2 R2; /**< \brief 8, MCS Channel Program Counter Register 2 */
+ Ifx_GTM_MCS_CH_R3 R3; /**< \brief C, MCS Channel Program Counter Register 3 */
+ Ifx_GTM_MCS_CH_R4 R4; /**< \brief 10, MCS Channel Program Counter Register 4 */
+ Ifx_GTM_MCS_CH_R5 R5; /**< \brief 14, MCS Channel Program Counter Register 5 */
+ Ifx_GTM_MCS_CH_R6 R6; /**< \brief 18, MCS Channel Program Counter Register 6 */
+ Ifx_GTM_MCS_CH_R7 R7; /**< \brief 1C, MCS Channel Program Counter Register 7 */
+ Ifx_GTM_MCS_CH_CTRL CTRL; /**< \brief 20, MCS Channel Control Register */
+ Ifx_GTM_MCS_CH_ACB ACB; /**< \brief 24, MCS Channel ACB Register */
+ unsigned char reserved_28[24]; /**< \brief 28, \internal Reserved */
+ Ifx_GTM_MCS_CH_PC PC; /**< \brief 40, MCS Channel Program Counter Register */
+ Ifx_GTM_MCS_CH_IRQ_NOTIFY IRQ_NOTIFY; /**< \brief 44, MCS Channel interrupt notification register */
+ Ifx_GTM_MCS_CH_IRQ_EN IRQ_EN; /**< \brief 48, MCS Channel Interrupt Enable Register */
+ Ifx_GTM_MCS_CH_IRQ_FORCINT IRQ_FORCINT; /**< \brief 4C, MCS Channel Software Interrupt Generation Register */
+ Ifx_GTM_MCS_CH_IRQ_MODE IRQ_MODE; /**< \brief 50, MCS IRQ Mode Configuration Register */
+ Ifx_GTM_MCS_CH_EIRQ_EN EIRQ_EN; /**< \brief 54, MCS_Channel Error Interrupt Enable Register */
+ unsigned char reserved_58[40]; /**< \brief 58, \internal Reserved */
+} Ifx_GTM_MCS_CH;
+
+/** \brief MCS channel0 object */
+typedef volatile struct _Ifx_GTM_MCS_CH0
+{
+ Ifx_GTM_MCS_CH_R0 R0; /**< \brief 0, MCS Channel Program Counter Register 0 */
+ Ifx_GTM_MCS_CH_R1 R1; /**< \brief 4, MCS Channel Program Counter Register 1 */
+ Ifx_GTM_MCS_CH_R2 R2; /**< \brief 8, MCS Channel Program Counter Register 2 */
+ Ifx_GTM_MCS_CH_R3 R3; /**< \brief C, MCS Channel Program Counter Register 3 */
+ Ifx_GTM_MCS_CH_R4 R4; /**< \brief 10, MCS Channel Program Counter Register 4 */
+ Ifx_GTM_MCS_CH_R5 R5; /**< \brief 14, MCS Channel Program Counter Register 5 */
+ Ifx_GTM_MCS_CH_R6 R6; /**< \brief 18, MCS Channel Program Counter Register 6 */
+ Ifx_GTM_MCS_CH_R7 R7; /**< \brief 1C, MCS Channel Program Counter Register 7 */
+ Ifx_GTM_MCS_CH_CTRL CTRL; /**< \brief 20, MCS Channel Control Register */
+ Ifx_GTM_MCS_CH_ACB ACB; /**< \brief 24, MCS Channel ACB Register */
+ Ifx_GTM_MCS_CH0_CTRG CTRG; /**< \brief 28, MCS Clear Trigger Control Register */
+ Ifx_GTM_MCS_CH0_STRG STRG; /**< \brief 2C, MCS Set Trigger Control Register */
+ unsigned char reserved_30[16]; /**< \brief 30, \internal Reserved */
+ Ifx_GTM_MCS_CH_PC PC; /**< \brief 40, MCS Channel Program Counter Register */
+ Ifx_GTM_MCS_CH_IRQ_NOTIFY IRQ_NOTIFY; /**< \brief 44, MCS Channel interrupt notification register */
+ Ifx_GTM_MCS_CH_IRQ_EN IRQ_EN; /**< \brief 48, MCS Channel Interrupt Enable Register */
+ Ifx_GTM_MCS_CH_IRQ_FORCINT IRQ_FORCINT; /**< \brief 4C, MCS Channel Software Interrupt Generation Register */
+ Ifx_GTM_MCS_CH_IRQ_MODE IRQ_MODE; /**< \brief 50, MCS IRQ Mode Configuration Register */
+ Ifx_GTM_MCS_CH_EIRQ_EN EIRQ_EN; /**< \brief 54, MCS_Channel Error Interrupt Enable Register */
+} Ifx_GTM_MCS_CH0;
+
+/** \brief TIM channel objects */
+typedef volatile struct _Ifx_GTM_TIM_CH
+{
+ Ifx_GTM_TIM_CH_GPR0 GPR0; /**< \brief 0, TIM Channel General Purpose 0 Register */
+ Ifx_GTM_TIM_CH_GPR1 GPR1; /**< \brief 4, TIM Channel General Purpose 1 Register */
+ Ifx_GTM_TIM_CH_CNT CNT; /**< \brief 8, TIM Channel SMU Counter Register */
+ Ifx_GTM_TIM_CH_ECNT ECNT; /**< \brief C, TIM Channel Edge Counter Register */
+ Ifx_GTM_TIM_CH_CNTS CNTS; /**< \brief 10, TIM Channel SMU Shadow Counter Register */
+ Ifx_GTM_TIM_CH_TDUC TDUC; /**< \brief 14, TIM Channel TDUC Register */
+ Ifx_GTM_TIM_CH_TDUV TDUV; /**< \brief 18, TIM Channel TDUV Register */
+ Ifx_GTM_TIM_CH_FLT_RE FLT_RE; /**< \brief 1C, GTM_TIM Channel Filter Parameter 0 Register */
+ Ifx_GTM_TIM_CH_FLT_FE FLT_FE; /**< \brief 20, TIM Channel Filter Parameter 1 Register */
+ Ifx_GTM_TIM_CH_CTRL CTRL; /**< \brief 24, TIM Channel Control Register */
+ Ifx_GTM_TIM_CH_ECTRL ECTRL; /**< \brief 28, TIM Channel External Capture Control Register */
+ Ifx_GTM_TIM_CH_IRQ_NOTIFY IRQ_NOTIFY; /**< \brief 2C, TIM Channel Interrupt Notification Register */
+ Ifx_GTM_TIM_CH_IRQ_EN IRQ_EN; /**< \brief 30, TIM Channel Interrupt Enable Register */
+ Ifx_GTM_TIM_CH_IRQ_FORCINT IRQ_FORCINT; /**< \brief 34, TIM Channel Software Interrupt Force Register */
+ Ifx_GTM_TIM_CH_IRQ_MODE IRQ_MODE; /**< \brief 38, TIM IRQ Mode Configuration Register */
+ Ifx_GTM_TIM_CH_EIRQ_EN EIRQ_EN; /**< \brief 3C, TIM Channel Error Interrupt Enable Register */
+ unsigned char reserved_40[56]; /**< \brief 40, \internal Reserved */
+} Ifx_GTM_TIM_CH;
+
+/** \brief TOM channel objects */
+typedef volatile struct _Ifx_GTM_TOM_CH
+{
+ Ifx_GTM_TOM_CH_CTRL CTRL; /**< \brief 0, TOM Channel Control Register鈥� */
+ Ifx_GTM_TOM_CH_SR0 SR0; /**< \brief 4, TOM Channel CCU0 Compare Shadow Register */
+ Ifx_GTM_TOM_CH_SR1 SR1; /**< \brief 8, TOM Channel CCU1 Compare Shadow Register */
+ Ifx_GTM_TOM_CH_CM0 CM0; /**< \brief C, TOM Channel CCU0 Compare Register */
+ Ifx_GTM_TOM_CH_CM1 CM1; /**< \brief 10, TOM Channel CCU1 Compare Register */
+ Ifx_GTM_TOM_CH_CN0 CN0; /**< \brief 14, TOM Channel CCU0 Counter Register */
+ Ifx_GTM_TOM_CH_STAT STAT; /**< \brief 18, TOM Channel Status Register */
+ Ifx_GTM_TOM_CH_IRQ_NOTIFY IRQ_NOTIFY; /**< \brief 1C, TOM Channel Interrupt Notification Register */
+ Ifx_GTM_TOM_CH_IRQ_EN IRQ_EN; /**< \brief 20, TOM Channel Interrupt Enable Register */
+ Ifx_GTM_TOM_CH_IRQ_FORCINT IRQ_FORCINT; /**< \brief 24, TOM Channel Software Interrupt Generation Register */
+ Ifx_GTM_TOM_CH_IRQ_MODE IRQ_MODE; /**< \brief 28, TOM IRQ Mode Configuration Register */
+ unsigned char reserved_2C[4]; /**< \brief 2C, \internal Reserved */
+} Ifx_GTM_TOM_CH;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Gtm_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L1
+ * \{ */
+
+/** \brief AFD object */
+typedef volatile struct _Ifx_GTM_AFD
+{
+ Ifx_GTM_AFD_CH CH[8]; /**< \brief 0, AFD FIFO channel objects */
+} Ifx_GTM_AFD;
+
+/** \brief ARU object */
+typedef volatile struct _Ifx_GTM_ARU
+{
+ Ifx_GTM_ARU_ARU_ACCESS ARU_ACCESS; /**< \brief 0, ARU Access Register */
+ Ifx_GTM_ARU_DATA_H DATA_H; /**< \brief 4, ARU Access Register Upper Data Word */
+ Ifx_GTM_ARU_DATA_L DATA_L; /**< \brief 8, ARU Access Register Lower Data Word */
+ Ifx_GTM_ARU_DBG_ACCESS0 DBG_ACCESS0; /**< \brief C, Debug Access Channel 0 */
+ Ifx_GTM_ARU_DBG_DATA0_H DBG_DATA0_H; /**< \brief 10, Debug Access 0 Transfer Register Upper Data Word */
+ Ifx_GTM_ARU_DBG_DATA0_L DBG_DATA0_L; /**< \brief 14, Debug Access 0 Transfer Register Lower Data Word */
+ Ifx_GTM_ARU_DBG_ACCESS1 DBG_ACCESS1; /**< \brief 18, Debug Access Channel 0 */
+ Ifx_GTM_ARU_DBG_DATA1_H DBG_DATA1_H; /**< \brief 1C, Debug Access 1 Transfer Register Upper Data Word */
+ Ifx_GTM_ARU_DBG_DATA1_L DBG_DATA1_L; /**< \brief 20, Debug Access 1 Transfer Register Lower Data Word */
+ Ifx_GTM_ARU_IRQ_NOTIFY IRQ_NOTIFY; /**< \brief 24, ARU Interrupt Notification Register */
+ Ifx_GTM_ARU_IRQ_EN IRQ_EN; /**< \brief 28, ARU Interrupt Enable Register */
+ Ifx_GTM_ARU_IRQ_FORCINT IRQ_FORCINT; /**< \brief 2C, ARU_NEW_DATA_IRQ Forcing Interrupt Register */
+ Ifx_GTM_ARU_IRQ_MODE IRQ_MODE; /**< \brief 30, IRQ Mode Configuration Register */
+} Ifx_GTM_ARU;
+
+/** \brief ATOM objects */
+typedef volatile struct _Ifx_GTM_ATOM
+{
+ Ifx_GTM_ATOM_CH CH0; /**< \brief 0, ATOM channel objects */
+ Ifx_GTM_ATOM_AGC AGC; /**< \brief 40, ACG object */
+ Ifx_GTM_ATOM_CH CH1; /**< \brief 80, ATOM channel objects */
+ unsigned char reserved_C0[64]; /**< \brief C0, \internal Reserved */
+ Ifx_GTM_ATOM_CH CH2; /**< \brief 100, ATOM channel objects */
+ unsigned char reserved_140[64]; /**< \brief 140, \internal Reserved */
+ Ifx_GTM_ATOM_CH CH3; /**< \brief 180, ATOM channel objects */
+ unsigned char reserved_1C0[64]; /**< \brief 1C0, \internal Reserved */
+ Ifx_GTM_ATOM_CH CH4; /**< \brief 200, ATOM channel objects */
+ unsigned char reserved_240[64]; /**< \brief 240, \internal Reserved */
+ Ifx_GTM_ATOM_CH CH5; /**< \brief 280, ATOM channel objects */
+ unsigned char reserved_2C0[64]; /**< \brief 2C0, \internal Reserved */
+ Ifx_GTM_ATOM_CH CH6; /**< \brief 300, ATOM channel objects */
+ unsigned char reserved_340[64]; /**< \brief 340, \internal Reserved */
+ Ifx_GTM_ATOM_CH CH7; /**< \brief 380, ATOM channel objects */
+ unsigned char reserved_3C0[1088]; /**< \brief 3C0, \internal Reserved */
+} Ifx_GTM_ATOM;
+
+/** \brief BRC object */
+typedef volatile struct _Ifx_GTM_BRC
+{
+ Ifx_GTM_BRC_SRC0_ADDR SRC0_ADDR; /**< \brief 0, Read Address For Input Channel 0 */
+ Ifx_GTM_BRC_SRC0_DEST SRC0_DEST; /**< \brief 4, Destination Channels For Input Channel 0 */
+ Ifx_GTM_BRC_SRC1_ADDR SRC1_ADDR; /**< \brief 8, Read Address For Input Channel 1 */
+ Ifx_GTM_BRC_SRC1_DEST SRC1_DEST; /**< \brief C, Destination Channels For Input Channel 1 */
+ Ifx_GTM_BRC_SRC2_ADDR SRC2_ADDR; /**< \brief 10, Read Address For Input Channel 2 */
+ Ifx_GTM_BRC_SRC2_DEST SRC2_DEST; /**< \brief 14, Destination Channels For Input Channel 2 */
+ Ifx_GTM_BRC_SRC3_ADDR SRC3_ADDR; /**< \brief 18, Read Address For Input Channel 3 */
+ Ifx_GTM_BRC_SRC3_DEST SRC3_DEST; /**< \brief 1C, Destination Channels For Input Channel 3 */
+ Ifx_GTM_BRC_SRC4_ADDR SRC4_ADDR; /**< \brief 20, Read Address For Input Channel 4 */
+ Ifx_GTM_BRC_SRC4_DEST SRC4_DEST; /**< \brief 24, Destination Channels For Input Channel 4 */
+ Ifx_GTM_BRC_SRC5_ADDR SRC5_ADDR; /**< \brief 28, Read Address For Input Channel 5 */
+ Ifx_GTM_BRC_SRC5_DEST SRC5_DEST; /**< \brief 2C, Destination Channels For Input Channel 5 */
+ Ifx_GTM_BRC_SRC6_ADDR SRC6_ADDR; /**< \brief 30, Read Address For Input Channel 6 */
+ Ifx_GTM_BRC_SRC6_DEST SRC6_DEST; /**< \brief 34, Destination Channels For Input Channel 6 */
+ Ifx_GTM_BRC_SRC7_ADDR SRC7_ADDR; /**< \brief 38, Read Address For Input Channel 7 */
+ Ifx_GTM_BRC_SRC7_DEST SRC7_DEST; /**< \brief 3C, Destination Channels For Input Channel 7 */
+ Ifx_GTM_BRC_SRC8_ADDR SRC8_ADDR; /**< \brief 40, Read Address For Input Channel 8 */
+ Ifx_GTM_BRC_SRC8_DEST SRC8_DEST; /**< \brief 44, Destination Channels For Input Channel 8 */
+ Ifx_GTM_BRC_SRC9_ADDR SRC9_ADDR; /**< \brief 48, Read Address For Input Channel 9 */
+ Ifx_GTM_BRC_SRC9_DEST SRC9_DEST; /**< \brief 4C, Destination Channels For Input Channel 9 */
+ Ifx_GTM_BRC_SRC10_ADDR SRC10_ADDR; /**< \brief 50, Read Address For Input Channel 10 */
+ Ifx_GTM_BRC_SRC10_DEST SRC10_DEST; /**< \brief 54, Destination Channels For Input Channel 10 */
+ Ifx_GTM_BRC_SRC11_ADDR SRC11_ADDR; /**< \brief 58, Read Address For Input Channel 11 */
+ Ifx_GTM_BRC_SRC11_DEST SRC11_DEST; /**< \brief 5C, Destination Channels For Input Channel 11 */
+ Ifx_GTM_BRC_IRQ_NOTIFY IRQ_NOTIFY; /**< \brief 60, BRC Interrupt Notification Register */
+ Ifx_GTM_BRC_IRQ_EN IRQ_EN; /**< \brief 64, BRC Interrupt Enable Register */
+ Ifx_GTM_BRC_IRQ_FORCINT IRQ_FORCINT; /**< \brief 68, BRC_DEST_ERR Forcing Interrupt Register */
+ Ifx_GTM_BRC_IRQ_MODE IRQ_MODE; /**< \brief 6C, BRC IRQ Mode Configuration Register */
+ Ifx_GTM_BRC_RST RST; /**< \brief 70, BRC Software Reset Register */
+ Ifx_GTM_BRC_EIRQ_EN EIRQ_EN; /**< \brief 74, BRC Error Interrupt Enable Register */
+} Ifx_GTM_BRC;
+
+/** \brief BRIDGE object */
+typedef volatile struct _Ifx_GTM_BRIDGE
+{
+ Ifx_GTM_BRIDGE_MODE MODE; /**< \brief 0, GTM to SPB BRIDGE MODE */
+ Ifx_GTM_BRIDGE_PTR1 PTR1; /**< \brief 4, GTM to SPB BRIDGE PTR1 */
+ Ifx_GTM_BRIDGE_PTR2 PTR2; /**< \brief 8, GTM to SPB BRIDGE PTR2 */
+} Ifx_GTM_BRIDGE;
+
+/** \brief CMP object */
+typedef volatile struct _Ifx_GTM_CMP
+{
+ Ifx_GTM_CMP_EN EN; /**< \brief 0, CMP Comparator Enable Register */
+ Ifx_GTM_CMP_IRQ_NOTIFY IRQ_NOTIFY; /**< \brief 4, CMP Event Notification Register */
+ Ifx_GTM_CMP_IRQ_EN IRQ_EN; /**< \brief 8, CMP Interrupt Enable Register */
+ Ifx_GTM_CMP_IRQ_FORCINT IRQ_FORCINT; /**< \brief C, CMP Interrupt Force Register */
+ Ifx_GTM_CMP_IRQ_MODE IRQ_MODE; /**< \brief 10, CMP IRQ Mode Configuration Register */
+ Ifx_GTM_CMP_EIRQ_EN EIRQ_EN; /**< \brief 14, CMP Error Interrupt Enable Register */
+} Ifx_GTM_CMP;
+
+/** \brief CMU object */
+typedef volatile struct _Ifx_GTM_CMU
+{
+ Ifx_GTM_CMU_CLK_EN CLK_EN; /**< \brief 0, CMU Clock Enable Register */
+ Ifx_GTM_CMU_GCLK_NUM GCLK_NUM; /**< \brief 4, CMU Global Clock Control Numerator Register */
+ Ifx_GTM_CMU_GCLK_DEN GCLK_DEN; /**< \brief 8, CMU Global Clock Control Denominator Register */
+ Ifx_GTM_CMU_CLK0_5 CLK0_5[6]; /**< \brief C, CLK objects */
+ Ifx_GTM_CMU_CLK_6 CLK_6; /**< \brief 24, CLK objects */
+ Ifx_GTM_CMU_CLK_7 CLK_7; /**< \brief 28, CLK objects */
+ Ifx_GTM_CMU_ECLK ECLK[3]; /**< \brief 2C, ECLK objects */
+ Ifx_GTM_CMU_FXCLK FXCLK; /**< \brief 44, FXCLK objects */
+} Ifx_GTM_CMU;
+
+/** \brief DPLL object */
+typedef volatile struct _Ifx_GTM_DPLL
+{
+ Ifx_GTM_DPLL_CTRL_0 CTRL_0; /**< \brief 0, DPLL Control Register 0 */
+ Ifx_GTM_DPLL_CTRL_1 CTRL_1; /**< \brief 4, DPLL Control Register 1 */
+ Ifx_GTM_DPLL_CTRL_2 CTRL_2; /**< \brief 8, DPLL Control Register 2 */
+ Ifx_GTM_DPLL_CTRL_3 CTRL_3; /**< \brief C, DPLL Control Register 3 */
+ Ifx_GTM_DPLL_CTRL_4 CTRL_4; /**< \brief 10, DPLL Control Register 4 */
+ unsigned char reserved_14[4]; /**< \brief 14, \internal Reserved */
+ Ifx_GTM_DPLL_ACT_STA ACT_STA; /**< \brief 18, DPLL ACTION Status Register With Shadow Register */
+ Ifx_GTM_DPLL_OSW OSW; /**< \brief 1C, DPLL Offset And Switch Old/New Address Register */
+ Ifx_GTM_DPLL_AOSV_2 AOSV_2; /**< \brief 20, DPLL Address Offset Register For APT In RAM Region 2 */
+ Ifx_GTM_DPLL_APT APT; /**< \brief 24, DPLL Actual RAM Pointer to RAM Regions 2A, B and D */
+ Ifx_GTM_DPLL_APS APS; /**< \brief 28, DPLL Actual RAM Pointer to RAM Regions 1C1, 1C2 and 1C4 */
+ Ifx_GTM_DPLL_APT_2C APT_2C; /**< \brief 2C, DPLL Actual RAM Pointer to RAM Region 2C */
+ Ifx_GTM_DPLL_APS_1C3 APS_1C3; /**< \brief 30, DPLL Actual RAM Pointer to RAM Region 1C3 */
+ Ifx_GTM_DPLL_NUTC NUTC; /**< \brief 34, DPLL Number of Recent TRIGGER Events Used for Calculations */
+ Ifx_GTM_DPLL_NUSC NUSC; /**< \brief 38, DPLL Number of Recent STATE Events Used for Calculations */
+ Ifx_GTM_DPLL_NTI_CNT NTI_CNT; /**< \brief 3C, DPLL Number of Active TRIGGER Events to Interrupt */
+ Ifx_GTM_DPLL_IRQ_NOTIFY IRQ_NOTIFY; /**< \brief 40, DPLL Interrupt Notification Register */
+ Ifx_GTM_DPLL_IRQ_EN IRQ_EN; /**< \brief 44, DPLL Interrupt Enable Register */
+ Ifx_GTM_DPLL_IRQ_FORCINT IRQ_FORCINT; /**< \brief 48, DPLL Interrupt Force Register */
+ Ifx_GTM_DPLL_IRQ_MODE IRQ_MODE; /**< \brief 4C, DPLL Interrupt Mode Register */
+ Ifx_GTM_DPLL_EIRQ_EN EIRQ_EN; /**< \brief 50, DPLL Error Interrupt Enable Register */
+ unsigned char reserved_54[92]; /**< \brief 54, \internal Reserved */
+ Ifx_GTM_DPLL_INC_CNT1 INC_CNT1; /**< \brief B0, DPLL Counter for Pulses for TBU_TS1 to be sent in Automatic End Mode */
+ Ifx_GTM_DPLL_INC_CNT2 INC_CNT2; /**< \brief B4, DPLL Counter for Pulses for TBU_TS2 to be sent in Automatic End Mode when SMC=RMO=1 */
+ Ifx_GTM_DPLL_APT_SYNC APT_SYNC; /**< \brief B8, DPLL Old RAM Pointer and Offset Value for TRIGGER */
+ Ifx_GTM_DPLL_APS_SYNC APS_SYNC; /**< \brief BC, DPLL Old RAM Pointer and Offset Value for STATE */
+ Ifx_GTM_DPLL_TBU_TS0_T TBU_TS0_T; /**< \brief C0, DPLL TBU_TS0 Value at last TRIGGER Event */
+ Ifx_GTM_DPLL_TBU_TS0_S TBU_TS0_S; /**< \brief C4, DPLL TBU_TS0 Value at last STATE Event */
+ Ifx_GTM_DPLL_ADD_IN_LD1 ADD_IN_LD1; /**< \brief C8, DPLL Direct Load Input Value for SUB_INC1 */
+ Ifx_GTM_DPLL_ADD_IN_LD2 ADD_IN_LD2; /**< \brief CC, DPLL Direct Load Input Value for SUB_INC1 */
+ unsigned char reserved_D0[44]; /**< \brief D0, \internal Reserved */
+ Ifx_GTM_DPLL_STATUS STATUS; /**< \brief FC, DPLL Status Register */
+ Ifx_GTM_DPLL_ID_PMTR ID_PMTR[24]; /**< \brief 100, DPLL ID Information For Input Signal PMTR n Register */
+ unsigned char reserved_160[128]; /**< \brief 160, \internal Reserved */
+ Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER CTRL_0_SHADOW_TRIGGER; /**< \brief 1E0, DPLL Control0 Shadow Trigger Register */
+ Ifx_GTM_DPLL_CTRL_0_SHADOW_STATE CTRL_0_SHADOW_STATE; /**< \brief 1E4, DPLL Control 0 Shadow STATE Register */
+ Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER CTRL_1_SHADOW_TRIGGER; /**< \brief 1E8, DPLL Control 1 Shadow TRIGGER Register */
+ Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE CRTL_1_SHADOW_STATE; /**< \brief 1EC, DPLL Control 1 Shadow STATE Register */
+ unsigned char reserved_1F0[12]; /**< \brief 1F0, \internal Reserved */
+ Ifx_GTM_DPLL_RAM_INI RAM_INI; /**< \brief 1FC, DPLL RAM Initatlisation Register */
+ Ifx_GTM_DPLL_PSA PSA[24]; /**< \brief 200, DPLL ACTION Position/Value Action Request Register */
+ unsigned char reserved_260[32]; /**< \brief 260, \internal Reserved */
+ Ifx_GTM_DPLL_DLA DLA[24]; /**< \brief 280, DPLL ACTION Time To React Before PSAi Register */
+ unsigned char reserved_2E0[32]; /**< \brief 2E0, \internal Reserved */
+ Ifx_GTM_DPLL_NA NA[24]; /**< \brief 300, DPLL Calculated Number Of TRIGGER/STATE Increments To ACTION */
+ unsigned char reserved_360[32]; /**< \brief 360, \internal Reserved */
+ Ifx_GTM_DPLL_DTA DTA[24]; /**< \brief 380, DPLL Calculated Relative Time To ACTION_i Register */
+ unsigned char reserved_3E0[32]; /**< \brief 3E0, \internal Reserved */
+ Ifx_GTM_DPLL_TS_T_0 TS_T_0; /**< \brief 400, DPLL Actual Signal TRIGGER Time Stamp Register */
+ Ifx_GTM_DPLL_TS_T_1 TS_T_1; /**< \brief 404, DPLL Actual Signal TRIGGER Time Stamp Register */
+ Ifx_GTM_DPLL_FTV_T FTV_T; /**< \brief 408, DPLL Actual Signal TRIGGER Filter Value Register */
+ unsigned char reserved_40C[4]; /**< \brief 40C, \internal Reserved */
+ Ifx_GTM_DPLL_TS_S_0 TS_S_0; /**< \brief 410, DPLL Actual Signal STATE Time Stamp Register */
+ Ifx_GTM_DPLL_TS_S_1 TS_S_1; /**< \brief 414, DPLL Actual Signal STATE Time Stamp Register */
+ Ifx_GTM_DPLL_FTV_S FTV_S; /**< \brief 418, DPLL Actual Signal STATE Filter Value Register */
+ unsigned char reserved_41C[4]; /**< \brief 41C, \internal Reserved */
+ Ifx_GTM_DPLL_THMI THMI; /**< \brief 420, DPLL TRIGGER hold time min value */
+ Ifx_GTM_DPLL_THMA THMA; /**< \brief 424, DPLL TRIGGER Hold Time Max Value */
+ Ifx_GTM_DPLL_THVAL THVAL; /**< \brief 428, DPLL Measured Last Pulse Time from Valid to Invalid TRIGGER Slope */
+ unsigned char reserved_42C[4]; /**< \brief 42C, \internal Reserved */
+ Ifx_GTM_DPLL_TOV TOV; /**< \brief 430, DPLL Time Out Value of active TRIGGER Slope */
+ Ifx_GTM_DPLL_TOV_S TOV_S; /**< \brief 434, DPLL Time Out Value of active STATE Slope */
+ Ifx_GTM_DPLL_ADD_IN_CAL1 ADD_IN_CAL1; /**< \brief 438, DPLL Calculated ADD_IN Value for SUB_INC1 Generation */
+ Ifx_GTM_DPLL_ADD_IN_CAL2 ADD_IN_CAL2; /**< \brief 43C, DPLL Calculated ADD_IN Value for SUB_INC2 Generation */
+ Ifx_GTM_DPLL_MPVAL1 MPVAL1; /**< \brief 440, DPLL Missing Pulses to be Added/Subtracted Directly to SUB_INC1 and INC_CNT1 Once */
+ Ifx_GTM_DPLL_MPVAL2 MPVAL2; /**< \brief 444, DPLL Missing Pulses to be Added/Subtracted Directly to SUB_INC2 and INC_CNT2 Once */
+ Ifx_GTM_DPLL_NMB_T_TAR NMB_T_TAR; /**< \brief 448, DPLL Target Number of Pulses to be sent in normal mode Register */
+ Ifx_GTM_DPLL_NMB_T_TAR_OLD NMB_T_TAR_OLD; /**< \brief 44C, DPLL Target Number of Pulses to be sent in normal mode Register */
+ Ifx_GTM_DPLL_NMB_S_TAR NMB_S_TAR; /**< \brief 450, DPLL Target Number of Pulses to be sent in emergency mode Register */
+ Ifx_GTM_DPLL_NMB_S_TAR_OLD NMB_S_TAR_OLD; /**< \brief 454, DPLL Target Number of Pulses to be sent in emergency mode Register */
+ unsigned char reserved_458[8]; /**< \brief 458, \internal Reserved */
+ Ifx_GTM_DPLL_RCDT_TX RCDT_TX; /**< \brief 460, DPLL Reciprocal Value of Expected Increment Duration TRIGGER */
+ Ifx_GTM_DPLL_RCDT_SX RCDT_SX; /**< \brief 464, DPLL Reciprocal Value of Expected Increment Duration STATE */
+ Ifx_GTM_DPLL_RCDT_TX_NOM RCDT_TX_NOM; /**< \brief 468, DPLL Reciprocal Value of the Expected Nominal Increment Duration TRIGGER */
+ Ifx_GTM_DPLL_RCDT_SX_NOM RCDT_SX_NOM; /**< \brief 46C, DPLL Reciprocal Value of the Expected Nominal Increment Duration STATE */
+ Ifx_GTM_DPLL_RDT_T_ACT RDT_T_ACT; /**< \brief 470, DPLL Actual Reciprocal Value of TRIGGER */
+ Ifx_GTM_DPLL_RDT_S_ACT RDT_S_ACT; /**< \brief 474, DPLL Actual Reciprocal Value of STATE */
+ Ifx_GTM_DPLL_DT_T_ACT DT_T_ACT; /**< \brief 478, DPLL Duration of Last TRIGGER Increment */
+ Ifx_GTM_DPLL_DT_S_ACT DT_S_ACT; /**< \brief 47C, DPLL Duration of Last STATE Increment [DT_S_ACT] */
+ Ifx_GTM_DPLL_EDT_T EDT_T; /**< \brief 480, DPLL Difference of prediction to actual value of the last TRIGGER increment */
+ Ifx_GTM_DPLL_MEDT_T MEDT_T; /**< \brief 484, DPLL Weighted difference of Prediction up to the Last TRIGGER Increment */
+ Ifx_GTM_DPLL_EDT_S EDT_S; /**< \brief 488, DPLL Difference of Prediction to actual value for Last STATE Increment */
+ Ifx_GTM_DPLL_MEDT_S MEDT_S; /**< \brief 48C, DPLL Weighted difference of Prediction up to the Last STATE Increment */
+ Ifx_GTM_DPLL_CDT_TX CDT_TX; /**< \brief 490, DPLL Prediction of the actual TRIGGER Increment */
+ Ifx_GTM_DPLL_CDT_SX CDT_SX; /**< \brief 494, DPLL Prediction of the actual STATE Increment */
+ Ifx_GTM_DPLL_CDT_TX_NOM CDT_TX_NOM; /**< \brief 498, DPLL Prediction of the nominal TRIGGER Increment duration */
+ Ifx_GTM_DPLL_CDT_SX_NOM CDT_SX_NOM; /**< \brief 49C, DPLL Prediction of the nominal STATE increment duration */
+ Ifx_GTM_DPLL_TLR TLR; /**< \brief 4A0, DPLL TRIGGER locking range */
+ Ifx_GTM_DPLL_SLR SLR; /**< \brief 4A4, DPLL STATE Locking Range */
+ unsigned char reserved_4A8[88]; /**< \brief 4A8, \internal Reserved */
+ Ifx_GTM_DPLL_PDT_T PDT_T[24]; /**< \brief 500, DPLL Projected TRIGGER Increment Sum Relations for Action_i */
+ unsigned char reserved_560[96]; /**< \brief 560, \internal Reserved */
+ Ifx_GTM_DPLL_MLS1 MLS1; /**< \brief 5C0, DPLL Calculated Number of Sub-Pulses between Two STATE Events */
+ Ifx_GTM_DPLL_MLS2 MLS2; /**< \brief 5C4, DPLL Calculated Number of Sub-Pulses between Two STATE Events */
+ Ifx_GTM_DPLL_CNT_NUM1 CNT_NUM1; /**< \brief 5C8, DPLL Number of Sub-Pulses of SUB_INC1 in Continuous Mode */
+ Ifx_GTM_DPLL_CNT_NUM2 CNT_NUM2; /**< \brief 5CC, DPLL Number of Sub-Pulses of SUB_INC2 in Continuous Mode */
+ Ifx_GTM_DPLL_PVT PVT; /**< \brief 5D0, DPLL Plausibility Value of Next Active TRIGGER Slope */
+ unsigned char reserved_5D4[12]; /**< \brief 5D4, \internal Reserved */
+ Ifx_GTM_DPLL_PSTC PSTC; /**< \brief 5E0, DPLL Actual Calculated Position Stamp of Last TRIGGER Input */
+ Ifx_GTM_DPLL_PSSC PSSC; /**< \brief 5E4, DPLL Accurate Calculated Position Stamp of Last STATE Input */
+ Ifx_GTM_DPLL_PSTM_0 PSTM_0; /**< \brief 5E8, DPLL Measured Position Stamp of Last TRIGGER Input */
+ Ifx_GTM_DPLL_PSTM_1 PSTM_1; /**< \brief 5EC, DPLL Measured Position Stamp of Last TRIGGER Input */
+ Ifx_GTM_DPLL_PSSM_0 PSSM_0; /**< \brief 5F0, DPLL Measured Position Stamp of Last STATE Input */
+ Ifx_GTM_DPLL_PSSM_1 PSSM_1; /**< \brief 5F4, DPLL Measured Position Stamp of Last STATE Input */
+ Ifx_GTM_DPLL_NMB_T NMB_T; /**< \brief 5F8, DPLL Number of Pulses of Current Increment in Normal Mode */
+ Ifx_GTM_DPLL_NMB_S NMB_S; /**< \brief 5FC, DPLL Number of Pulses of Current Increment in Emergency Mode */
+ Ifx_GTM_DPLL_RDT_S RDT_S[64]; /**< \brief 600, DPLL Nominal STATE Reciprocal Values in FULL_SCALE */
+ Ifx_GTM_DPLL_TSF_S TSF_S[64]; /**< \brief 700, DPLL Time Stamp Field of STATE Events */
+ Ifx_GTM_DPLL_ADT_S ADT_S[64]; /**< \brief 800, DPLL Adapt Values for All STATE Increments */
+ Ifx_GTM_DPLL_DT_S DT_S[64]; /**< \brief 900, DPLL Nominal STATE Increment Values for FULL_SCALE */
+ unsigned char reserved_A00[1024]; /**< \brief A00, \internal Reserved */
+ Ifx_GTM_DPLL_TSAC TSAC[24]; /**< \brief E00, DPLL Calculate Time Stamp Register */
+ unsigned char reserved_E60[32]; /**< \brief E60, \internal Reserved */
+ Ifx_GTM_DPLL_PSAC PSAC[24]; /**< \brief E80, DPLL Calculated Position Value Register */
+ unsigned char reserved_EE0[32]; /**< \brief EE0, \internal Reserved */
+ Ifx_GTM_DPLL_ACB ACB[6]; /**< \brief F00, DPLL Action Control i Register */
+} Ifx_GTM_DPLL;
+
+/** \brief F2A object */
+typedef volatile struct _Ifx_GTM_F2A
+{
+ Ifx_GTM_F2A_RD_CH RD_CH[8]; /**< \brief 0, F2A ARU RD FIFO address */
+ Ifx_GTM_F2A_STR_CH STR_CH[8]; /**< \brief 20, F2A Stream configuration */
+ Ifx_GTM_F2A_ENABLE ENABLE; /**< \brief 40, F2A0 Stream Activation Register */
+} Ifx_GTM_F2A;
+
+/** \brief FIFO object */
+typedef volatile struct _Ifx_GTM_FIFO
+{
+ Ifx_GTM_FIFO_CH CH[8]; /**< \brief 0, FIFO channel */
+} Ifx_GTM_FIFO;
+
+/** \brief ICM object */
+typedef volatile struct _Ifx_GTM_ICM
+{
+ Ifx_GTM_ICM_IRQG_0 IRQG_0; /**< \brief 0, GTM Infrastructure Interrupt Group */
+ Ifx_GTM_ICM_IRQG_1 IRQG_1; /**< \brief 4, GTM DPLL Interrupt Group */
+ Ifx_GTM_ICM_IRQG_2 IRQG_2; /**< \brief 8, TIM Interrupt Group 0 */
+ unsigned char reserved_C[4]; /**< \brief C, \internal Reserved */
+ Ifx_GTM_ICM_IRQG_4 IRQG_4; /**< \brief 10, MCS Interrupt Group 0 */
+ unsigned char reserved_14[4]; /**< \brief 14, \internal Reserved */
+ Ifx_GTM_ICM_IRQG_6 IRQG_6; /**< \brief 18, TOM Interrupt Group 0 */
+ unsigned char reserved_1C[8]; /**< \brief 1C, \internal Reserved */
+ Ifx_GTM_ICM_IRQG_9 IRQG_9; /**< \brief 24, ATOM Interrupt Group 0 */
+ unsigned char reserved_28[8]; /**< \brief 28, \internal Reserved */
+ Ifx_GTM_ICM_IRQG_MEI IRQG_MEI; /**< \brief 30, ICM Module Error Interrupt Register */
+ Ifx_GTM_ICM_IRQG_CEI0 IRQG_CEI0; /**< \brief 34, ICM Channel Error Interrupt 0 Register */
+ Ifx_GTM_ICM_IRQG_CEI1 IRQG_CEI1; /**< \brief 38, ICM Channel Error Interrupt 1 Register */
+ unsigned char reserved_3C[4]; /**< \brief 3C, \internal Reserved */
+ Ifx_GTM_ICM_IRQG_CEI3 IRQG_CEI3; /**< \brief 40, ICM Channel Error Interrupt 3 Register */
+} Ifx_GTM_ICM;
+
+/** \brief INSEL / OUTSEL object */
+typedef volatile struct _Ifx_GTM_INOUTSEL
+{
+ Ifx_GTM_INOUTSEL_TIM TIM[3]; /**< \brief 0, TIM */
+ unsigned char reserved_C[20]; /**< \brief C, \internal Reserved */
+ Ifx_GTM_INOUTSEL_T T; /**< \brief 20, Timer */
+ unsigned char reserved_48[36]; /**< \brief 48, \internal Reserved */
+ Ifx_GTM_INOUTSEL_DSADC DSADC; /**< \brief 6C, DSADC */
+ unsigned char reserved_84[12]; /**< \brief 84, \internal Reserved */
+ Ifx_GTM_INOUTSEL_CAN CAN; /**< \brief 90, CAN */
+ Ifx_GTM_INOUTSEL_PSI5 PSI5; /**< \brief 94, PSI5 */
+ Ifx_GTM_INOUTSEL_PSI5S PSI5S; /**< \brief 98, PSI5S */
+} Ifx_GTM_INOUTSEL;
+
+/** \brief MCS objects */
+typedef volatile struct _Ifx_GTM_MCS
+{
+ Ifx_GTM_MCS_CH0 CH0; /**< \brief 0, MCS channel0 object */
+ unsigned char reserved_58[28]; /**< \brief 58, \internal Reserved */
+ Ifx_GTM_MCS_CTRL CTRL; /**< \brief 74, MCS Control Register */
+ Ifx_GTM_MCS_RST RST; /**< \brief 78, MCS Channel Reset Register */
+ Ifx_GTM_MCS_ERR ERR; /**< \brief 7C, MCS Error Register */
+ Ifx_GTM_MCS_CH CH1; /**< \brief 80, MCS channel objects */
+ Ifx_GTM_MCS_CH CH2; /**< \brief 100, MCS channel objects */
+ Ifx_GTM_MCS_CH CH3; /**< \brief 180, MCS channel objects */
+ Ifx_GTM_MCS_CH CH4; /**< \brief 200, MCS channel objects */
+ Ifx_GTM_MCS_CH CH5; /**< \brief 280, MCS channel objects */
+ Ifx_GTM_MCS_CH CH6; /**< \brief 300, MCS channel objects */
+ Ifx_GTM_MCS_CH CH7; /**< \brief 380, MCS channel objects */
+ unsigned char reserved_400[3072]; /**< \brief 400, \internal Reserved */
+} Ifx_GTM_MCS;
+
+/** \brief MON object */
+typedef volatile struct _Ifx_GTM_MON
+{
+ Ifx_GTM_MON_STATUS STATUS; /**< \brief 0, Monitor Status Register */
+ Ifx_GTM_MON_ACTIVITY_0 ACTIVITY_0; /**< \brief 4, Monitor Activity Register 0 */
+} Ifx_GTM_MON;
+
+/** \brief MSC input */
+typedef volatile struct _Ifx_GTM_MSCIN
+{
+ Ifx_GTM_MSCIN_INLCON INLCON; /**< \brief 0, MSC Input Low Control Register */
+ Ifx_GTM_MSCIN_INHCON INHCON; /**< \brief 4, MSC Input High Control Register */
+} Ifx_GTM_MSCIN;
+
+/** \brief MSC objects */
+typedef volatile struct _Ifx_GTM_MSCSET
+{
+ Ifx_GTM_MSCSET_CON0 CON0; /**< \brief 0, MSC Set Control 0 Register */
+ Ifx_GTM_MSCSET_CON1 CON1; /**< \brief 4, MSC Set Control 1 Register */
+ Ifx_GTM_MSCSET_CON2 CON2; /**< \brief 8, MSC Set Control 2 Register */
+ Ifx_GTM_MSCSET_CON3 CON3; /**< \brief C, MSC Set Control 3 Register */
+} Ifx_GTM_MSCSET;
+
+/** \brief SPE objects */
+typedef volatile struct _Ifx_GTM_SPE
+{
+ Ifx_GTM_SPE_CTRL_STAT CTRL_STAT; /**< \brief 0, SPE Control Status Register */
+ Ifx_GTM_SPE_PAT PAT; /**< \brief 4, SPE Input Pattern Definition Register */
+ Ifx_GTM_SPE_OUT_PAT OUT_PAT[8]; /**< \brief 8, SPE Output Definition Register */
+ Ifx_GTM_SPE_OUT_CTRL OUT_CTRL; /**< \brief 28, SPE Output Control Register */
+ Ifx_GTM_SPE_IRQ_NOTIFY IRQ_NOTIFY; /**< \brief 2C, SPE Interrupt Notification Register */
+ Ifx_GTM_SPE_IRQ_EN IRQ_EN; /**< \brief 30, SPE Interrupt Enable Register */
+ Ifx_GTM_SPE_IRQ_FORCINT IRQ_FORCINT; /**< \brief 34, SPE Interrupt Generation by Software */
+ Ifx_GTM_SPE_IRQ_MODE IRQ_MODE; /**< \brief 38, SPE IRQ Mode Configuration Register */
+ Ifx_GTM_SPE_EIRQ_EN EIRQ_EN; /**< \brief 3C, SPE Error Interrupt Enable Register */
+ Ifx_GTM_SPE_CNT CNT; /**< \brief 40, SPE Revolution Counter Register */
+ Ifx_GTM_SPE_CMP CMP; /**< \brief 44, SPE Revolution Compare Register */
+ unsigned char reserved_48[56]; /**< \brief 48, \internal Reserved */
+} Ifx_GTM_SPE;
+
+/** \brief TBU object */
+typedef volatile struct _Ifx_GTM_TBU
+{
+ Ifx_GTM_TBU_CHEN CHEN; /**< \brief 0, TBU Global Channel Enable Register */
+ Ifx_GTM_TBU_CH0_CTRL CH0_CTRL; /**< \brief 4, TBU Channel 0 Control Register */
+ Ifx_GTM_TBU_CH0_BASE CH0_BASE; /**< \brief 8, TBU Channel 0 Base Register */
+ Ifx_GTM_TBU_CH1_CTRL CH1_CTRL; /**< \brief C, TBU Channel 1 Control Register */
+ Ifx_GTM_TBU_CH1_BASE CH1_BASE; /**< \brief 10, TBU Channel 1 Base Register */
+ Ifx_GTM_TBU_CH2_CTRL CH2_CTRL; /**< \brief 14, TBU Channel 2 Control Register */
+ Ifx_GTM_TBU_CH2_BASE CH2_BASE; /**< \brief 18, TBU Channel 2 Base Register */
+} Ifx_GTM_TBU;
+
+/** \brief TIM objects */
+typedef volatile struct _Ifx_GTM_TIM
+{
+ Ifx_GTM_TIM_CH CH0; /**< \brief 0, TIM channel objects */
+ Ifx_GTM_TIM_IN_SRC IN_SRC; /**< \brief 78, TIM_IN_SRC Long Name */
+ Ifx_GTM_TIM_RST RST; /**< \brief 7C, TIM Global Software Reset Register */
+ Ifx_GTM_TIM_CH CH1; /**< \brief 80, TIM channel objects */
+ unsigned char reserved_F8[8]; /**< \brief F8, \internal Reserved */
+ Ifx_GTM_TIM_CH CH2; /**< \brief 100, TIM channel objects */
+ unsigned char reserved_178[8]; /**< \brief 178, \internal Reserved */
+ Ifx_GTM_TIM_CH CH3; /**< \brief 180, TIM channel objects */
+ unsigned char reserved_1F8[8]; /**< \brief 1F8, \internal Reserved */
+ Ifx_GTM_TIM_CH CH4; /**< \brief 200, TIM channel objects */
+ unsigned char reserved_278[8]; /**< \brief 278, \internal Reserved */
+ Ifx_GTM_TIM_CH CH5; /**< \brief 280, TIM channel objects */
+ unsigned char reserved_2F8[8]; /**< \brief 2F8, \internal Reserved */
+ Ifx_GTM_TIM_CH CH6; /**< \brief 300, TIM channel objects */
+ unsigned char reserved_378[8]; /**< \brief 378, \internal Reserved */
+ Ifx_GTM_TIM_CH CH7; /**< \brief 380, TIM channel objects */
+ unsigned char reserved_3F8[1032]; /**< \brief 3F8, \internal Reserved */
+} Ifx_GTM_TIM;
+
+/** \brief TOM objects */
+typedef volatile struct _Ifx_GTM_TOM
+{
+ Ifx_GTM_TOM_CH CH0; /**< \brief 0, TOM channel objects */
+ Ifx_GTM_TOM_TGC0_GLB_CTRL TGC0_GLB_CTRL; /**< \brief 30, TOM TGC0 Global Control Register */
+ Ifx_GTM_TOM_TGC0_ACT_TB TGC0_ACT_TB; /**< \brief 34, TOM TGC0 Action Time Base Register */
+ Ifx_GTM_TOM_TGC0_FUPD_CTRL TGC0_FUPD_CTRL; /**< \brief 38, TOM TGC0 Force Update Control Register */
+ Ifx_GTM_TOM_TGC0_INT_TRIG TGC0_INT_TRIG; /**< \brief 3C, TOM TGC0 Internal Trigger Control Register */
+ Ifx_GTM_TOM_CH CH1; /**< \brief 40, TOM channel objects */
+ Ifx_GTM_TOM_TGC0_ENDIS_CTRL TGC0_ENDIS_CTRL; /**< \brief 70, TOM TGC0 Enable/Disable Control Register */
+ Ifx_GTM_TOM_TGC0_ENDIS_STAT TGC0_ENDIS_STAT; /**< \brief 74, TOM TGC0 Enable/Disable Status Register */
+ Ifx_GTM_TOM_TGC0_OUTEN_CTRL TGC0_OUTEN_CTRL; /**< \brief 78, TOM TGC0 Output Enable Control Register */
+ Ifx_GTM_TOM_TGC0_OUTEN_STAT TGC0_OUTEN_STAT; /**< \brief 7C, TOM TGC0 Output Enable Status Register */
+ Ifx_GTM_TOM_CH CH2; /**< \brief 80, TOM channel objects */
+ unsigned char reserved_B0[16]; /**< \brief B0, \internal Reserved */
+ Ifx_GTM_TOM_CH CH3; /**< \brief C0, TOM channel objects */
+ unsigned char reserved_F0[16]; /**< \brief F0, \internal Reserved */
+ Ifx_GTM_TOM_CH CH4; /**< \brief 100, TOM channel objects */
+ unsigned char reserved_130[16]; /**< \brief 130, \internal Reserved */
+ Ifx_GTM_TOM_CH CH5; /**< \brief 140, TOM channel objects */
+ unsigned char reserved_170[16]; /**< \brief 170, \internal Reserved */
+ Ifx_GTM_TOM_CH CH6; /**< \brief 180, TOM channel objects */
+ unsigned char reserved_1B0[16]; /**< \brief 1B0, \internal Reserved */
+ Ifx_GTM_TOM_CH CH7; /**< \brief 1C0, TOM channel objects */
+ unsigned char reserved_1F0[16]; /**< \brief 1F0, \internal Reserved */
+ Ifx_GTM_TOM_CH CH8; /**< \brief 200, TOM channel objects */
+ Ifx_GTM_TOM_TGC1_GLB_CTRL TGC1_GLB_CTRL; /**< \brief 230, TOM TGC1 Global Control Register */
+ Ifx_GTM_TOM_TGC1_ACT_TB TGC1_ACT_TB; /**< \brief 234, TOM TGC1 Action Time Base Register */
+ Ifx_GTM_TOM_TGC1_FUPD_CTRL TGC1_FUPD_CTRL; /**< \brief 238, TOM TGC1 Force Update Control Register */
+ Ifx_GTM_TOM_TGC1_INT_TRIG TGC1_INT_TRIG; /**< \brief 23C, TOM TGC1 Internal Trigger Control Register */
+ Ifx_GTM_TOM_CH CH9; /**< \brief 240, TOM channel objects */
+ Ifx_GTM_TOM_TGC1_ENDIS_CTRL TGC1_ENDIS_CTRL; /**< \brief 270, TOM TGC1 Enable/Disable Control Register */
+ Ifx_GTM_TOM_TGC1_ENDIS_STAT TGC1_ENDIS_STAT; /**< \brief 274, TOM TGC1 Enable/Disable Status Register */
+ Ifx_GTM_TOM_TGC1_OUTEN_CTRL TGC1_OUTEN_CTRL; /**< \brief 278, TOM TGC1 Output Enable Control Register */
+ Ifx_GTM_TOM_TGC1_OUTEN_STAT TGC1_OUTEN_STAT; /**< \brief 27C, TOM TGC1 Output Enable Status Register */
+ Ifx_GTM_TOM_CH CH10; /**< \brief 280, TOM channel objects */
+ unsigned char reserved_2B0[16]; /**< \brief 2B0, \internal Reserved */
+ Ifx_GTM_TOM_CH CH11; /**< \brief 2C0, TOM channel objects */
+ unsigned char reserved_2F0[16]; /**< \brief 2F0, \internal Reserved */
+ Ifx_GTM_TOM_CH CH12; /**< \brief 300, TOM channel objects */
+ unsigned char reserved_330[16]; /**< \brief 330, \internal Reserved */
+ Ifx_GTM_TOM_CH CH13; /**< \brief 340, TOM channel objects */
+ unsigned char reserved_370[16]; /**< \brief 370, \internal Reserved */
+ Ifx_GTM_TOM_CH CH14; /**< \brief 380, TOM channel objects */
+ unsigned char reserved_3B0[16]; /**< \brief 3B0, \internal Reserved */
+ Ifx_GTM_TOM_CH CH15; /**< \brief 3C0, TOM channel objects */
+ unsigned char reserved_3F0[1040]; /**< \brief 3F0, \internal Reserved */
+} Ifx_GTM_TOM;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Gtm_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief GTM object */
+typedef volatile struct _Ifx_GTM
+{
+ Ifx_GTM_REV REV; /**< \brief 0, GTM Version Control Register */
+ Ifx_GTM_RST RST; /**< \brief 4, GTM Global Reset Register */
+ Ifx_GTM_CTRL CTRL; /**< \brief 8, GTM Global Control Register */
+ Ifx_GTM_AEI_ADDR_XPT AEI_ADDR_XPT; /**< \brief C, GTM AEI Timeout Exception Address Register */
+ Ifx_GTM_IRQ_NOTIFY IRQ_NOTIFY; /**< \brief 10, GTM Interrupt Notification Register */
+ Ifx_GTM_IRQ_EN IRQ_EN; /**< \brief 14, GTM Interrupt Enable Register */
+ Ifx_GTM_IRQ_FORCINT IRQ_FORCINT; /**< \brief 18, GTM Software Interrupt Generation Register */
+ Ifx_GTM_IRQ_MODE IRQ_MODE; /**< \brief 1C, GTM Top Level Interrupts Mode Selection */
+ Ifx_GTM_EIRQ_EN EIRQ_EN; /**< \brief 20, GTM Error Interrupt Enable Register */
+ unsigned char reserved_24[12]; /**< \brief 24, \internal Reserved */
+ Ifx_GTM_BRIDGE BRIDGE; /**< \brief 30, BRIDGE object */
+ unsigned char reserved_3C[4]; /**< \brief 3C, \internal Reserved */
+ Ifx_GTM_TIM_AUX_IN_SRC TIM_AUX_IN_SRC[3]; /**< \brief 40, GTM TIM AUX_IN_SRC */
+ unsigned char reserved_4C[180]; /**< \brief 4C, \internal Reserved */
+ Ifx_GTM_TBU TBU; /**< \brief 100, TBU object */
+ unsigned char reserved_11C[100]; /**< \brief 11C, \internal Reserved */
+ Ifx_GTM_MON MON; /**< \brief 180, MON object */
+ unsigned char reserved_188[120]; /**< \brief 188, \internal Reserved */
+ Ifx_GTM_CMP CMP; /**< \brief 200, CMP object */
+ unsigned char reserved_218[104]; /**< \brief 218, \internal Reserved */
+ Ifx_GTM_ARU ARU; /**< \brief 280, ARU object */
+ unsigned char reserved_2B4[76]; /**< \brief 2B4, \internal Reserved */
+ Ifx_GTM_CMU CMU; /**< \brief 300, CMU object */
+ unsigned char reserved_348[184]; /**< \brief 348, \internal Reserved */
+ Ifx_GTM_BRC BRC; /**< \brief 400, BRC object */
+ unsigned char reserved_478[392]; /**< \brief 478, \internal Reserved */
+ Ifx_GTM_ICM ICM; /**< \brief 600, ICM object */
+ unsigned char reserved_644[444]; /**< \brief 644, \internal Reserved */
+ Ifx_GTM_SPE SPE[2]; /**< \brief 800, SPE objects */
+ unsigned char reserved_900[1536]; /**< \brief 900, \internal Reserved */
+ Ifx_GTM_MAP_CTRL MAP_CTRL; /**< \brief F00, MAP Control Register */
+ unsigned char reserved_F04[60]; /**< \brief F04, \internal Reserved */
+ Ifx_GTM_MCFG_CTRL MCFG_CTRL; /**< \brief F40, Memory Layout Configuration Register */
+ unsigned char reserved_F44[188]; /**< \brief F44, \internal Reserved */
+ Ifx_GTM_TIM TIM[3]; /**< \brief 1000, TIM objects */
+ unsigned char reserved_2800[22528]; /**< \brief 2800, \internal Reserved */
+ Ifx_GTM_TOM TOM[2]; /**< \brief 8000, TOM objects */
+ unsigned char reserved_9000[16384]; /**< \brief 9000, \internal Reserved */
+ Ifx_GTM_ATOM ATOM[4]; /**< \brief D000, ATOM objects */
+ unsigned char reserved_F000[36864]; /**< \brief F000, \internal Reserved */
+ Ifx_GTM_F2A F2A0; /**< \brief 18000, F2A object */
+ unsigned char reserved_18044[60]; /**< \brief 18044, \internal Reserved */
+ Ifx_GTM_AFD AFD0; /**< \brief 18080, AFD object */
+ unsigned char reserved_18100[768]; /**< \brief 18100, \internal Reserved */
+ Ifx_GTM_FIFO FIFO0; /**< \brief 18400, FIFO object */
+ unsigned char reserved_18600[64000]; /**< \brief 18600, \internal Reserved */
+ Ifx_GTM_DPLL DPLL; /**< \brief 28000, DPLL object */
+ unsigned char reserved_28F18[28904]; /**< \brief 28F18, \internal Reserved */
+ Ifx_GTM_MCS MCS[3]; /**< \brief 30000, MCS objects */
+ unsigned char reserved_33000[445696]; /**< \brief 33000, \internal Reserved */
+ Ifx_GTM_CLC CLC; /**< \brief 9FD00, Clock Control Register */
+ unsigned char reserved_9FD04[12]; /**< \brief 9FD04, \internal Reserved */
+ Ifx_GTM_INOUTSEL INOUTSEL; /**< \brief 9FD10, INSEL / OUTSEL object */
+ unsigned char reserved_9FDAC[4]; /**< \brief 9FDAC, \internal Reserved */
+ Ifx_GTM_ADCTRIG0OUT0 ADCTRIG0OUT0; /**< \brief 9FDB0, ADC Trigger 0 Output Select 0 Register */
+ unsigned char reserved_9FDB4[4]; /**< \brief 9FDB4, \internal Reserved */
+ Ifx_GTM_ADCTRIG1OUT0 ADCTRIG1OUT0; /**< \brief 9FDB8, ADC Trigger 1 Output Select 0 Register */
+ unsigned char reserved_9FDBC[8]; /**< \brief 9FDBC, \internal Reserved */
+ Ifx_GTM_OTBU0T OTBU0T; /**< \brief 9FDC4, OCDS TBU0 Trigger Register */
+ Ifx_GTM_OTBU1T OTBU1T; /**< \brief 9FDC8, OCDS TBU1 Trigger Register */
+ Ifx_GTM_OTBU2T OTBU2T; /**< \brief 9FDCC, OCDS TBU2 Trigger Register */
+ Ifx_GTM_OTSS OTSS; /**< \brief 9FDD0, OCDS Trigger Set Select Register */
+ Ifx_GTM_OTSC0 OTSC0; /**< \brief 9FDD4, OCDS Trigger Set Control 0 Register */
+ Ifx_GTM_OTSC1 OTSC1; /**< \brief 9FDD8, OCDS Trigger Set Control 1 Register */
+ Ifx_GTM_ODA ODA; /**< \brief 9FDDC, OCDS Debug Access Register */
+ unsigned char reserved_9FDE0[8]; /**< \brief 9FDE0, \internal Reserved */
+ Ifx_GTM_OCS OCS; /**< \brief 9FDE8, OCDS Control and Status */
+ Ifx_GTM_KRSTCLR KRSTCLR; /**< \brief 9FDEC, Kernel Reset Status Clear Register */
+ Ifx_GTM_KRST1 KRST1; /**< \brief 9FDF0, Kernel Reset Register 1 */
+ Ifx_GTM_KRST0 KRST0; /**< \brief 9FDF4, Kernel Reset Register 0 */
+ Ifx_GTM_ACCEN1 ACCEN1; /**< \brief 9FDF8, Access Enable Register 1 */
+ Ifx_GTM_ACCEN0 ACCEN0; /**< \brief 9FDFC, Access Enable Register 0 */
+ Ifx_GTM_DXOUTCON DXOUTCON; /**< \brief 9FE00, Data Exchange Output Control Register */
+ Ifx_GTM_TRIGOUT TRIGOUT0[3]; /**< \brief 9FE04, Trigger Output Register */
+ unsigned char reserved_9FE10[52]; /**< \brief 9FE10, \internal Reserved */
+ Ifx_GTM_TRIGOUT TRIGOUT1[3]; /**< \brief 9FE44, Trigger Output Register */
+ unsigned char reserved_9FE50[32]; /**< \brief 9FE50, \internal Reserved */
+ Ifx_GTM_MCSINTSTAT MCSINTSTAT; /**< \brief 9FE70, MCS Interrupt Status Register */
+ Ifx_GTM_MCSINTCLR MCSINTCLR; /**< \brief 9FE74, MCS Interrupt Clear Register */
+ unsigned char reserved_9FE78[24]; /**< \brief 9FE78, \internal Reserved */
+ Ifx_GTM_DXINCON DXINCON; /**< \brief 9FE90, Data Exchange Input Control Register */
+ Ifx_GTM_DATAIN DATAIN0[3]; /**< \brief 9FE94, Data Input 0 0 Register */
+ unsigned char reserved_9FEA0[52]; /**< \brief 9FEA0, \internal Reserved */
+ Ifx_GTM_DATAIN DATAIN1[3]; /**< \brief 9FED4, Data Input 0 Register */
+ unsigned char reserved_9FEE0[32]; /**< \brief 9FEE0, \internal Reserved */
+ Ifx_GTM_MSCSET MSCSET_1S[4]; /**< \brief 9FF00, MSC objects \note Array index shifted by 1. Example: defined register MSCSET_1S[0]/MSCSET_1S0 corresponds to user manual MSCSET_1S1, ... */
+ unsigned char reserved_9FF40[32]; /**< \brief 9FF40, \internal Reserved */
+ Ifx_GTM_MSCIN MSCIN[2]; /**< \brief 9FF60, MSC input */
+ Ifx_GTM_MSC0INLEXTCON MSC0INLEXTCON; /**< \brief 9FF70, MSC0 Input Low Extended Control Register */
+ unsigned char reserved_9FF74[140]; /**< \brief 9FF74, \internal Reserved */
+} Ifx_GTM;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#if defined (__TASKING__)
+#pragma warning restore
+#endif
+/******************************************************************************/
+#endif /* IFXGTM_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxHsct_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxHsct_bf.h
new file mode 100644
index 0000000..2327628
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxHsct_bf.h
@@ -0,0 +1,1179 @@
+/**
+ * \file IfxHsct_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Hsct_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Hsct
+ *
+ */
+#ifndef IFXHSCT_BF_H
+#define IFXHSCT_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Hsct_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN0 */
+#define IFX_HSCT_ACCEN0_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN0 */
+#define IFX_HSCT_ACCEN0_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN0 */
+#define IFX_HSCT_ACCEN0_EN0_OFF (0u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN10 */
+#define IFX_HSCT_ACCEN0_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN10 */
+#define IFX_HSCT_ACCEN0_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN10 */
+#define IFX_HSCT_ACCEN0_EN10_OFF (10u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN11 */
+#define IFX_HSCT_ACCEN0_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN11 */
+#define IFX_HSCT_ACCEN0_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN11 */
+#define IFX_HSCT_ACCEN0_EN11_OFF (11u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN12 */
+#define IFX_HSCT_ACCEN0_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN12 */
+#define IFX_HSCT_ACCEN0_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN12 */
+#define IFX_HSCT_ACCEN0_EN12_OFF (12u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN13 */
+#define IFX_HSCT_ACCEN0_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN13 */
+#define IFX_HSCT_ACCEN0_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN13 */
+#define IFX_HSCT_ACCEN0_EN13_OFF (13u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN14 */
+#define IFX_HSCT_ACCEN0_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN14 */
+#define IFX_HSCT_ACCEN0_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN14 */
+#define IFX_HSCT_ACCEN0_EN14_OFF (14u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN15 */
+#define IFX_HSCT_ACCEN0_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN15 */
+#define IFX_HSCT_ACCEN0_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN15 */
+#define IFX_HSCT_ACCEN0_EN15_OFF (15u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN16 */
+#define IFX_HSCT_ACCEN0_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN16 */
+#define IFX_HSCT_ACCEN0_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN16 */
+#define IFX_HSCT_ACCEN0_EN16_OFF (16u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN17 */
+#define IFX_HSCT_ACCEN0_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN17 */
+#define IFX_HSCT_ACCEN0_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN17 */
+#define IFX_HSCT_ACCEN0_EN17_OFF (17u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN18 */
+#define IFX_HSCT_ACCEN0_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN18 */
+#define IFX_HSCT_ACCEN0_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN18 */
+#define IFX_HSCT_ACCEN0_EN18_OFF (18u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN19 */
+#define IFX_HSCT_ACCEN0_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN19 */
+#define IFX_HSCT_ACCEN0_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN19 */
+#define IFX_HSCT_ACCEN0_EN19_OFF (19u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN1 */
+#define IFX_HSCT_ACCEN0_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN1 */
+#define IFX_HSCT_ACCEN0_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN1 */
+#define IFX_HSCT_ACCEN0_EN1_OFF (1u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN20 */
+#define IFX_HSCT_ACCEN0_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN20 */
+#define IFX_HSCT_ACCEN0_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN20 */
+#define IFX_HSCT_ACCEN0_EN20_OFF (20u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN21 */
+#define IFX_HSCT_ACCEN0_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN21 */
+#define IFX_HSCT_ACCEN0_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN21 */
+#define IFX_HSCT_ACCEN0_EN21_OFF (21u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN22 */
+#define IFX_HSCT_ACCEN0_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN22 */
+#define IFX_HSCT_ACCEN0_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN22 */
+#define IFX_HSCT_ACCEN0_EN22_OFF (22u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN23 */
+#define IFX_HSCT_ACCEN0_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN23 */
+#define IFX_HSCT_ACCEN0_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN23 */
+#define IFX_HSCT_ACCEN0_EN23_OFF (23u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN24 */
+#define IFX_HSCT_ACCEN0_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN24 */
+#define IFX_HSCT_ACCEN0_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN24 */
+#define IFX_HSCT_ACCEN0_EN24_OFF (24u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN25 */
+#define IFX_HSCT_ACCEN0_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN25 */
+#define IFX_HSCT_ACCEN0_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN25 */
+#define IFX_HSCT_ACCEN0_EN25_OFF (25u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN26 */
+#define IFX_HSCT_ACCEN0_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN26 */
+#define IFX_HSCT_ACCEN0_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN26 */
+#define IFX_HSCT_ACCEN0_EN26_OFF (26u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN27 */
+#define IFX_HSCT_ACCEN0_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN27 */
+#define IFX_HSCT_ACCEN0_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN27 */
+#define IFX_HSCT_ACCEN0_EN27_OFF (27u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN28 */
+#define IFX_HSCT_ACCEN0_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN28 */
+#define IFX_HSCT_ACCEN0_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN28 */
+#define IFX_HSCT_ACCEN0_EN28_OFF (28u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN29 */
+#define IFX_HSCT_ACCEN0_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN29 */
+#define IFX_HSCT_ACCEN0_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN29 */
+#define IFX_HSCT_ACCEN0_EN29_OFF (29u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN2 */
+#define IFX_HSCT_ACCEN0_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN2 */
+#define IFX_HSCT_ACCEN0_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN2 */
+#define IFX_HSCT_ACCEN0_EN2_OFF (2u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN30 */
+#define IFX_HSCT_ACCEN0_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN30 */
+#define IFX_HSCT_ACCEN0_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN30 */
+#define IFX_HSCT_ACCEN0_EN30_OFF (30u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN31 */
+#define IFX_HSCT_ACCEN0_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN31 */
+#define IFX_HSCT_ACCEN0_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN31 */
+#define IFX_HSCT_ACCEN0_EN31_OFF (31u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN3 */
+#define IFX_HSCT_ACCEN0_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN3 */
+#define IFX_HSCT_ACCEN0_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN3 */
+#define IFX_HSCT_ACCEN0_EN3_OFF (3u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN4 */
+#define IFX_HSCT_ACCEN0_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN4 */
+#define IFX_HSCT_ACCEN0_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN4 */
+#define IFX_HSCT_ACCEN0_EN4_OFF (4u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN5 */
+#define IFX_HSCT_ACCEN0_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN5 */
+#define IFX_HSCT_ACCEN0_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN5 */
+#define IFX_HSCT_ACCEN0_EN5_OFF (5u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN6 */
+#define IFX_HSCT_ACCEN0_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN6 */
+#define IFX_HSCT_ACCEN0_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN6 */
+#define IFX_HSCT_ACCEN0_EN6_OFF (6u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN7 */
+#define IFX_HSCT_ACCEN0_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN7 */
+#define IFX_HSCT_ACCEN0_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN7 */
+#define IFX_HSCT_ACCEN0_EN7_OFF (7u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN8 */
+#define IFX_HSCT_ACCEN0_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN8 */
+#define IFX_HSCT_ACCEN0_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN8 */
+#define IFX_HSCT_ACCEN0_EN8_OFF (8u)
+
+/** \brief Length for Ifx_HSCT_ACCEN0_Bits.EN9 */
+#define IFX_HSCT_ACCEN0_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_ACCEN0_Bits.EN9 */
+#define IFX_HSCT_ACCEN0_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_ACCEN0_Bits.EN9 */
+#define IFX_HSCT_ACCEN0_EN9_OFF (9u)
+
+/** \brief Length for Ifx_HSCT_CLC_Bits.DISR */
+#define IFX_HSCT_CLC_DISR_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_CLC_Bits.DISR */
+#define IFX_HSCT_CLC_DISR_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_CLC_Bits.DISR */
+#define IFX_HSCT_CLC_DISR_OFF (0u)
+
+/** \brief Length for Ifx_HSCT_CLC_Bits.DISS */
+#define IFX_HSCT_CLC_DISS_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_CLC_Bits.DISS */
+#define IFX_HSCT_CLC_DISS_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_CLC_Bits.DISS */
+#define IFX_HSCT_CLC_DISS_OFF (1u)
+
+/** \brief Length for Ifx_HSCT_CLC_Bits.EDIS */
+#define IFX_HSCT_CLC_EDIS_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_CLC_Bits.EDIS */
+#define IFX_HSCT_CLC_EDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_CLC_Bits.EDIS */
+#define IFX_HSCT_CLC_EDIS_OFF (3u)
+
+/** \brief Length for Ifx_HSCT_CONFIGPHY_Bits.OSCCLKEN */
+#define IFX_HSCT_CONFIGPHY_OSCCLKEN_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_CONFIGPHY_Bits.OSCCLKEN */
+#define IFX_HSCT_CONFIGPHY_OSCCLKEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_CONFIGPHY_Bits.OSCCLKEN */
+#define IFX_HSCT_CONFIGPHY_OSCCLKEN_OFF (28u)
+
+/** \brief Length for Ifx_HSCT_CONFIGPHY_Bits.PHYRST */
+#define IFX_HSCT_CONFIGPHY_PHYRST_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_CONFIGPHY_Bits.PHYRST */
+#define IFX_HSCT_CONFIGPHY_PHYRST_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_CONFIGPHY_Bits.PHYRST */
+#define IFX_HSCT_CONFIGPHY_PHYRST_OFF (15u)
+
+/** \brief Length for Ifx_HSCT_CONFIGPHY_Bits.PLLIVR */
+#define IFX_HSCT_CONFIGPHY_PLLIVR_LEN (4u)
+
+/** \brief Mask for Ifx_HSCT_CONFIGPHY_Bits.PLLIVR */
+#define IFX_HSCT_CONFIGPHY_PLLIVR_MSK (0xfu)
+
+/** \brief Offset for Ifx_HSCT_CONFIGPHY_Bits.PLLIVR */
+#define IFX_HSCT_CONFIGPHY_PLLIVR_OFF (22u)
+
+/** \brief Length for Ifx_HSCT_CONFIGPHY_Bits.PLLKI */
+#define IFX_HSCT_CONFIGPHY_PLLKI_LEN (3u)
+
+/** \brief Mask for Ifx_HSCT_CONFIGPHY_Bits.PLLKI */
+#define IFX_HSCT_CONFIGPHY_PLLKI_MSK (0x7u)
+
+/** \brief Offset for Ifx_HSCT_CONFIGPHY_Bits.PLLKI */
+#define IFX_HSCT_CONFIGPHY_PLLKI_OFF (19u)
+
+/** \brief Length for Ifx_HSCT_CONFIGPHY_Bits.PLLKP */
+#define IFX_HSCT_CONFIGPHY_PLLKP_LEN (3u)
+
+/** \brief Mask for Ifx_HSCT_CONFIGPHY_Bits.PLLKP */
+#define IFX_HSCT_CONFIGPHY_PLLKP_MSK (0x7u)
+
+/** \brief Offset for Ifx_HSCT_CONFIGPHY_Bits.PLLKP */
+#define IFX_HSCT_CONFIGPHY_PLLKP_OFF (16u)
+
+/** \brief Length for Ifx_HSCT_CONFIGPHY_Bits.PLLKPKI */
+#define IFX_HSCT_CONFIGPHY_PLLKPKI_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_CONFIGPHY_Bits.PLLKPKI */
+#define IFX_HSCT_CONFIGPHY_PLLKPKI_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_CONFIGPHY_Bits.PLLKPKI */
+#define IFX_HSCT_CONFIGPHY_PLLKPKI_OFF (14u)
+
+/** \brief Length for Ifx_HSCT_CONFIGPHY_Bits.PLLPE */
+#define IFX_HSCT_CONFIGPHY_PLLPE_LEN (6u)
+
+/** \brief Mask for Ifx_HSCT_CONFIGPHY_Bits.PLLPE */
+#define IFX_HSCT_CONFIGPHY_PLLPE_MSK (0x3fu)
+
+/** \brief Offset for Ifx_HSCT_CONFIGPHY_Bits.PLLPE */
+#define IFX_HSCT_CONFIGPHY_PLLPE_OFF (2u)
+
+/** \brief Length for Ifx_HSCT_CONFIGPHY_Bits.PLLPON */
+#define IFX_HSCT_CONFIGPHY_PLLPON_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_CONFIGPHY_Bits.PLLPON */
+#define IFX_HSCT_CONFIGPHY_PLLPON_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_CONFIGPHY_Bits.PLLPON */
+#define IFX_HSCT_CONFIGPHY_PLLPON_OFF (1u)
+
+/** \brief Length for Ifx_HSCT_CONFIGPHY_Bits.PLLWMF */
+#define IFX_HSCT_CONFIGPHY_PLLWMF_LEN (6u)
+
+/** \brief Mask for Ifx_HSCT_CONFIGPHY_Bits.PLLWMF */
+#define IFX_HSCT_CONFIGPHY_PLLWMF_MSK (0x3fu)
+
+/** \brief Offset for Ifx_HSCT_CONFIGPHY_Bits.PLLWMF */
+#define IFX_HSCT_CONFIGPHY_PLLWMF_OFF (8u)
+
+/** \brief Length for Ifx_HSCT_CTSCTRL_Bits.CTS_FRAME */
+#define IFX_HSCT_CTSCTRL_CTS_FRAME_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_CTSCTRL_Bits.CTS_FRAME */
+#define IFX_HSCT_CTSCTRL_CTS_FRAME_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_CTSCTRL_Bits.CTS_FRAME */
+#define IFX_HSCT_CTSCTRL_CTS_FRAME_OFF (0u)
+
+/** \brief Length for Ifx_HSCT_CTSCTRL_Bits.CTS_RXD */
+#define IFX_HSCT_CTSCTRL_CTS_RXD_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_CTSCTRL_Bits.CTS_RXD */
+#define IFX_HSCT_CTSCTRL_CTS_RXD_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_CTSCTRL_Bits.CTS_RXD */
+#define IFX_HSCT_CTSCTRL_CTS_RXD_OFF (2u)
+
+/** \brief Length for Ifx_HSCT_CTSCTRL_Bits.CTS_TXD */
+#define IFX_HSCT_CTSCTRL_CTS_TXD_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_CTSCTRL_Bits.CTS_TXD */
+#define IFX_HSCT_CTSCTRL_CTS_TXD_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_CTSCTRL_Bits.CTS_TXD */
+#define IFX_HSCT_CTSCTRL_CTS_TXD_OFF (1u)
+
+/** \brief Length for Ifx_HSCT_CTSCTRL_Bits.HSSL_CTS_FBD */
+#define IFX_HSCT_CTSCTRL_HSSL_CTS_FBD_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_CTSCTRL_Bits.HSSL_CTS_FBD */
+#define IFX_HSCT_CTSCTRL_HSSL_CTS_FBD_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_CTSCTRL_Bits.HSSL_CTS_FBD */
+#define IFX_HSCT_CTSCTRL_HSSL_CTS_FBD_OFF (3u)
+
+/** \brief Length for Ifx_HSCT_DISABLE_Bits.RX_DIS */
+#define IFX_HSCT_DISABLE_RX_DIS_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_DISABLE_Bits.RX_DIS */
+#define IFX_HSCT_DISABLE_RX_DIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_DISABLE_Bits.RX_DIS */
+#define IFX_HSCT_DISABLE_RX_DIS_OFF (1u)
+
+/** \brief Length for Ifx_HSCT_DISABLE_Bits.RX_HEPD */
+#define IFX_HSCT_DISABLE_RX_HEPD_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_DISABLE_Bits.RX_HEPD */
+#define IFX_HSCT_DISABLE_RX_HEPD_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_DISABLE_Bits.RX_HEPD */
+#define IFX_HSCT_DISABLE_RX_HEPD_OFF (2u)
+
+/** \brief Length for Ifx_HSCT_DISABLE_Bits.TX_DIS */
+#define IFX_HSCT_DISABLE_TX_DIS_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_DISABLE_Bits.TX_DIS */
+#define IFX_HSCT_DISABLE_TX_DIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_DISABLE_Bits.TX_DIS */
+#define IFX_HSCT_DISABLE_TX_DIS_OFF (0u)
+
+/** \brief Length for Ifx_HSCT_ID_Bits.MODNUMBER */
+#define IFX_HSCT_ID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_HSCT_ID_Bits.MODNUMBER */
+#define IFX_HSCT_ID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_HSCT_ID_Bits.MODNUMBER */
+#define IFX_HSCT_ID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_HSCT_ID_Bits.MODREV */
+#define IFX_HSCT_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_HSCT_ID_Bits.MODREV */
+#define IFX_HSCT_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_HSCT_ID_Bits.MODREV */
+#define IFX_HSCT_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_HSCT_ID_Bits.MODTYPE */
+#define IFX_HSCT_ID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_HSCT_ID_Bits.MODTYPE */
+#define IFX_HSCT_ID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_HSCT_ID_Bits.MODTYPE */
+#define IFX_HSCT_ID_MODTYPE_OFF (8u)
+
+/** \brief Length for Ifx_HSCT_IFCTRL_Bits.IFCVS */
+#define IFX_HSCT_IFCTRL_IFCVS_LEN (8u)
+
+/** \brief Mask for Ifx_HSCT_IFCTRL_Bits.IFCVS */
+#define IFX_HSCT_IFCTRL_IFCVS_MSK (0xffu)
+
+/** \brief Offset for Ifx_HSCT_IFCTRL_Bits.IFCVS */
+#define IFX_HSCT_IFCTRL_IFCVS_OFF (0u)
+
+/** \brief Length for Ifx_HSCT_IFCTRL_Bits.IFTESTMD */
+#define IFX_HSCT_IFCTRL_IFTESTMD_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IFCTRL_Bits.IFTESTMD */
+#define IFX_HSCT_IFCTRL_IFTESTMD_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IFCTRL_Bits.IFTESTMD */
+#define IFX_HSCT_IFCTRL_IFTESTMD_OFF (20u)
+
+/** \brief Length for Ifx_HSCT_IFCTRL_Bits.MRXSPEED */
+#define IFX_HSCT_IFCTRL_MRXSPEED_LEN (2u)
+
+/** \brief Mask for Ifx_HSCT_IFCTRL_Bits.MRXSPEED */
+#define IFX_HSCT_IFCTRL_MRXSPEED_MSK (0x3u)
+
+/** \brief Offset for Ifx_HSCT_IFCTRL_Bits.MRXSPEED */
+#define IFX_HSCT_IFCTRL_MRXSPEED_OFF (16u)
+
+/** \brief Length for Ifx_HSCT_IFCTRL_Bits.MTXSPEED */
+#define IFX_HSCT_IFCTRL_MTXSPEED_LEN (2u)
+
+/** \brief Mask for Ifx_HSCT_IFCTRL_Bits.MTXSPEED */
+#define IFX_HSCT_IFCTRL_MTXSPEED_MSK (0x3u)
+
+/** \brief Offset for Ifx_HSCT_IFCTRL_Bits.MTXSPEED */
+#define IFX_HSCT_IFCTRL_MTXSPEED_OFF (18u)
+
+/** \brief Length for Ifx_HSCT_IFCTRL_Bits.SIFCV */
+#define IFX_HSCT_IFCTRL_SIFCV_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IFCTRL_Bits.SIFCV */
+#define IFX_HSCT_IFCTRL_SIFCV_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IFCTRL_Bits.SIFCV */
+#define IFX_HSCT_IFCTRL_SIFCV_OFF (8u)
+
+/** \brief Length for Ifx_HSCT_IFSTAT_Bits.RX_STAT */
+#define IFX_HSCT_IFSTAT_RX_STAT_LEN (3u)
+
+/** \brief Mask for Ifx_HSCT_IFSTAT_Bits.RX_STAT */
+#define IFX_HSCT_IFSTAT_RX_STAT_MSK (0x7u)
+
+/** \brief Offset for Ifx_HSCT_IFSTAT_Bits.RX_STAT */
+#define IFX_HSCT_IFSTAT_RX_STAT_OFF (0u)
+
+/** \brief Length for Ifx_HSCT_IFSTAT_Bits.TX_STAT */
+#define IFX_HSCT_IFSTAT_TX_STAT_LEN (2u)
+
+/** \brief Mask for Ifx_HSCT_IFSTAT_Bits.TX_STAT */
+#define IFX_HSCT_IFSTAT_TX_STAT_MSK (0x3u)
+
+/** \brief Offset for Ifx_HSCT_IFSTAT_Bits.TX_STAT */
+#define IFX_HSCT_IFSTAT_TX_STAT_OFF (3u)
+
+/** \brief Length for Ifx_HSCT_INIT_Bits.IFM */
+#define IFX_HSCT_INIT_IFM_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_INIT_Bits.IFM */
+#define IFX_HSCT_INIT_IFM_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_INIT_Bits.IFM */
+#define IFX_HSCT_INIT_IFM_OFF (3u)
+
+/** \brief Length for Ifx_HSCT_INIT_Bits.LHLR */
+#define IFX_HSCT_INIT_LHLR_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_INIT_Bits.LHLR */
+#define IFX_HSCT_INIT_LHLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_INIT_Bits.LHLR */
+#define IFX_HSCT_INIT_LHLR_OFF (10u)
+
+/** \brief Length for Ifx_HSCT_INIT_Bits.RXHD */
+#define IFX_HSCT_INIT_RXHD_LEN (3u)
+
+/** \brief Mask for Ifx_HSCT_INIT_Bits.RXHD */
+#define IFX_HSCT_INIT_RXHD_MSK (0x7u)
+
+/** \brief Offset for Ifx_HSCT_INIT_Bits.RXHD */
+#define IFX_HSCT_INIT_RXHD_OFF (19u)
+
+/** \brief Length for Ifx_HSCT_INIT_Bits.SRCF */
+#define IFX_HSCT_INIT_SRCF_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_INIT_Bits.SRCF */
+#define IFX_HSCT_INIT_SRCF_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_INIT_Bits.SRCF */
+#define IFX_HSCT_INIT_SRCF_OFF (2u)
+
+/** \brief Length for Ifx_HSCT_INIT_Bits.SYS_CLK_EN */
+#define IFX_HSCT_INIT_SYS_CLK_EN_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_INIT_Bits.SYS_CLK_EN */
+#define IFX_HSCT_INIT_SYS_CLK_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_INIT_Bits.SYS_CLK_EN */
+#define IFX_HSCT_INIT_SYS_CLK_EN_OFF (1u)
+
+/** \brief Length for Ifx_HSCT_INIT_Bits.TXHD */
+#define IFX_HSCT_INIT_TXHD_LEN (3u)
+
+/** \brief Mask for Ifx_HSCT_INIT_Bits.TXHD */
+#define IFX_HSCT_INIT_TXHD_MSK (0x7u)
+
+/** \brief Offset for Ifx_HSCT_INIT_Bits.TXHD */
+#define IFX_HSCT_INIT_TXHD_OFF (16u)
+
+/** \brief Length for Ifx_HSCT_IRQ_Bits.CER */
+#define IFX_HSCT_IRQ_CER_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQ_Bits.CER */
+#define IFX_HSCT_IRQ_CER_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQ_Bits.CER */
+#define IFX_HSCT_IRQ_CER_OFF (3u)
+
+/** \brief Length for Ifx_HSCT_IRQ_Bits.HER */
+#define IFX_HSCT_IRQ_HER_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQ_Bits.HER */
+#define IFX_HSCT_IRQ_HER_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQ_Bits.HER */
+#define IFX_HSCT_IRQ_HER_OFF (1u)
+
+/** \brief Length for Ifx_HSCT_IRQ_Bits.IFCFS */
+#define IFX_HSCT_IRQ_IFCFS_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQ_Bits.IFCFS */
+#define IFX_HSCT_IRQ_IFCFS_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQ_Bits.IFCFS */
+#define IFX_HSCT_IRQ_IFCFS_OFF (4u)
+
+/** \brief Length for Ifx_HSCT_IRQ_Bits.PAR */
+#define IFX_HSCT_IRQ_PAR_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQ_Bits.PAR */
+#define IFX_HSCT_IRQ_PAR_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQ_Bits.PAR */
+#define IFX_HSCT_IRQ_PAR_OFF (9u)
+
+/** \brief Length for Ifx_HSCT_IRQ_Bits.PLER */
+#define IFX_HSCT_IRQ_PLER_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQ_Bits.PLER */
+#define IFX_HSCT_IRQ_PLER_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQ_Bits.PLER */
+#define IFX_HSCT_IRQ_PLER_OFF (7u)
+
+/** \brief Length for Ifx_HSCT_IRQ_Bits.PYER */
+#define IFX_HSCT_IRQ_PYER_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQ_Bits.PYER */
+#define IFX_HSCT_IRQ_PYER_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQ_Bits.PYER */
+#define IFX_HSCT_IRQ_PYER_OFF (2u)
+
+/** \brief Length for Ifx_HSCT_IRQ_Bits.SFO */
+#define IFX_HSCT_IRQ_SFO_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQ_Bits.SFO */
+#define IFX_HSCT_IRQ_SFO_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQ_Bits.SFO */
+#define IFX_HSCT_IRQ_SFO_OFF (11u)
+
+/** \brief Length for Ifx_HSCT_IRQ_Bits.SFU */
+#define IFX_HSCT_IRQ_SFU_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQ_Bits.SFU */
+#define IFX_HSCT_IRQ_SFU_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQ_Bits.SFU */
+#define IFX_HSCT_IRQ_SFU_OFF (12u)
+
+/** \brief Length for Ifx_HSCT_IRQ_Bits.SMER */
+#define IFX_HSCT_IRQ_SMER_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQ_Bits.SMER */
+#define IFX_HSCT_IRQ_SMER_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQ_Bits.SMER */
+#define IFX_HSCT_IRQ_SMER_OFF (5u)
+
+/** \brief Length for Ifx_HSCT_IRQ_Bits.TXTE */
+#define IFX_HSCT_IRQ_TXTE_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQ_Bits.TXTE */
+#define IFX_HSCT_IRQ_TXTE_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQ_Bits.TXTE */
+#define IFX_HSCT_IRQ_TXTE_OFF (10u)
+
+/** \brief Length for Ifx_HSCT_IRQ_Bits.USM */
+#define IFX_HSCT_IRQ_USM_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQ_Bits.USM */
+#define IFX_HSCT_IRQ_USM_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQ_Bits.USM */
+#define IFX_HSCT_IRQ_USM_OFF (8u)
+
+/** \brief Length for Ifx_HSCT_IRQ_Bits.USMSF */
+#define IFX_HSCT_IRQ_USMSF_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQ_Bits.USMSF */
+#define IFX_HSCT_IRQ_USMSF_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQ_Bits.USMSF */
+#define IFX_HSCT_IRQ_USMSF_OFF (6u)
+
+/** \brief Length for Ifx_HSCT_IRQCLR_Bits.CERCLR */
+#define IFX_HSCT_IRQCLR_CERCLR_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQCLR_Bits.CERCLR */
+#define IFX_HSCT_IRQCLR_CERCLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQCLR_Bits.CERCLR */
+#define IFX_HSCT_IRQCLR_CERCLR_OFF (3u)
+
+/** \brief Length for Ifx_HSCT_IRQCLR_Bits.HERCLR */
+#define IFX_HSCT_IRQCLR_HERCLR_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQCLR_Bits.HERCLR */
+#define IFX_HSCT_IRQCLR_HERCLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQCLR_Bits.HERCLR */
+#define IFX_HSCT_IRQCLR_HERCLR_OFF (1u)
+
+/** \brief Length for Ifx_HSCT_IRQCLR_Bits.IFCFSCLR */
+#define IFX_HSCT_IRQCLR_IFCFSCLR_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQCLR_Bits.IFCFSCLR */
+#define IFX_HSCT_IRQCLR_IFCFSCLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQCLR_Bits.IFCFSCLR */
+#define IFX_HSCT_IRQCLR_IFCFSCLR_OFF (4u)
+
+/** \brief Length for Ifx_HSCT_IRQCLR_Bits.PARCLR */
+#define IFX_HSCT_IRQCLR_PARCLR_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQCLR_Bits.PARCLR */
+#define IFX_HSCT_IRQCLR_PARCLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQCLR_Bits.PARCLR */
+#define IFX_HSCT_IRQCLR_PARCLR_OFF (9u)
+
+/** \brief Length for Ifx_HSCT_IRQCLR_Bits.PLERCLR */
+#define IFX_HSCT_IRQCLR_PLERCLR_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQCLR_Bits.PLERCLR */
+#define IFX_HSCT_IRQCLR_PLERCLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQCLR_Bits.PLERCLR */
+#define IFX_HSCT_IRQCLR_PLERCLR_OFF (7u)
+
+/** \brief Length for Ifx_HSCT_IRQCLR_Bits.PYERCLR */
+#define IFX_HSCT_IRQCLR_PYERCLR_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQCLR_Bits.PYERCLR */
+#define IFX_HSCT_IRQCLR_PYERCLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQCLR_Bits.PYERCLR */
+#define IFX_HSCT_IRQCLR_PYERCLR_OFF (2u)
+
+/** \brief Length for Ifx_HSCT_IRQCLR_Bits.SFOCLR */
+#define IFX_HSCT_IRQCLR_SFOCLR_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQCLR_Bits.SFOCLR */
+#define IFX_HSCT_IRQCLR_SFOCLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQCLR_Bits.SFOCLR */
+#define IFX_HSCT_IRQCLR_SFOCLR_OFF (11u)
+
+/** \brief Length for Ifx_HSCT_IRQCLR_Bits.SFUCLR */
+#define IFX_HSCT_IRQCLR_SFUCLR_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQCLR_Bits.SFUCLR */
+#define IFX_HSCT_IRQCLR_SFUCLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQCLR_Bits.SFUCLR */
+#define IFX_HSCT_IRQCLR_SFUCLR_OFF (12u)
+
+/** \brief Length for Ifx_HSCT_IRQCLR_Bits.SMERCLR */
+#define IFX_HSCT_IRQCLR_SMERCLR_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQCLR_Bits.SMERCLR */
+#define IFX_HSCT_IRQCLR_SMERCLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQCLR_Bits.SMERCLR */
+#define IFX_HSCT_IRQCLR_SMERCLR_OFF (5u)
+
+/** \brief Length for Ifx_HSCT_IRQCLR_Bits.TXTECLR */
+#define IFX_HSCT_IRQCLR_TXTECLR_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQCLR_Bits.TXTECLR */
+#define IFX_HSCT_IRQCLR_TXTECLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQCLR_Bits.TXTECLR */
+#define IFX_HSCT_IRQCLR_TXTECLR_OFF (10u)
+
+/** \brief Length for Ifx_HSCT_IRQCLR_Bits.USMCLR */
+#define IFX_HSCT_IRQCLR_USMCLR_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQCLR_Bits.USMCLR */
+#define IFX_HSCT_IRQCLR_USMCLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQCLR_Bits.USMCLR */
+#define IFX_HSCT_IRQCLR_USMCLR_OFF (8u)
+
+/** \brief Length for Ifx_HSCT_IRQCLR_Bits.USMSFCLR */
+#define IFX_HSCT_IRQCLR_USMSFCLR_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQCLR_Bits.USMSFCLR */
+#define IFX_HSCT_IRQCLR_USMSFCLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQCLR_Bits.USMSFCLR */
+#define IFX_HSCT_IRQCLR_USMSFCLR_OFF (6u)
+
+/** \brief Length for Ifx_HSCT_IRQEN_Bits.CEREN */
+#define IFX_HSCT_IRQEN_CEREN_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQEN_Bits.CEREN */
+#define IFX_HSCT_IRQEN_CEREN_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQEN_Bits.CEREN */
+#define IFX_HSCT_IRQEN_CEREN_OFF (3u)
+
+/** \brief Length for Ifx_HSCT_IRQEN_Bits.HEREN */
+#define IFX_HSCT_IRQEN_HEREN_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQEN_Bits.HEREN */
+#define IFX_HSCT_IRQEN_HEREN_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQEN_Bits.HEREN */
+#define IFX_HSCT_IRQEN_HEREN_OFF (1u)
+
+/** \brief Length for Ifx_HSCT_IRQEN_Bits.IFCFSEN */
+#define IFX_HSCT_IRQEN_IFCFSEN_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQEN_Bits.IFCFSEN */
+#define IFX_HSCT_IRQEN_IFCFSEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQEN_Bits.IFCFSEN */
+#define IFX_HSCT_IRQEN_IFCFSEN_OFF (4u)
+
+/** \brief Length for Ifx_HSCT_IRQEN_Bits.PAREN */
+#define IFX_HSCT_IRQEN_PAREN_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQEN_Bits.PAREN */
+#define IFX_HSCT_IRQEN_PAREN_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQEN_Bits.PAREN */
+#define IFX_HSCT_IRQEN_PAREN_OFF (9u)
+
+/** \brief Length for Ifx_HSCT_IRQEN_Bits.PLEREN */
+#define IFX_HSCT_IRQEN_PLEREN_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQEN_Bits.PLEREN */
+#define IFX_HSCT_IRQEN_PLEREN_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQEN_Bits.PLEREN */
+#define IFX_HSCT_IRQEN_PLEREN_OFF (7u)
+
+/** \brief Length for Ifx_HSCT_IRQEN_Bits.PYEREN */
+#define IFX_HSCT_IRQEN_PYEREN_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQEN_Bits.PYEREN */
+#define IFX_HSCT_IRQEN_PYEREN_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQEN_Bits.PYEREN */
+#define IFX_HSCT_IRQEN_PYEREN_OFF (2u)
+
+/** \brief Length for Ifx_HSCT_IRQEN_Bits.SFOEN */
+#define IFX_HSCT_IRQEN_SFOEN_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQEN_Bits.SFOEN */
+#define IFX_HSCT_IRQEN_SFOEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQEN_Bits.SFOEN */
+#define IFX_HSCT_IRQEN_SFOEN_OFF (11u)
+
+/** \brief Length for Ifx_HSCT_IRQEN_Bits.SFUEN */
+#define IFX_HSCT_IRQEN_SFUEN_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQEN_Bits.SFUEN */
+#define IFX_HSCT_IRQEN_SFUEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQEN_Bits.SFUEN */
+#define IFX_HSCT_IRQEN_SFUEN_OFF (12u)
+
+/** \brief Length for Ifx_HSCT_IRQEN_Bits.SMEREN */
+#define IFX_HSCT_IRQEN_SMEREN_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQEN_Bits.SMEREN */
+#define IFX_HSCT_IRQEN_SMEREN_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQEN_Bits.SMEREN */
+#define IFX_HSCT_IRQEN_SMEREN_OFF (5u)
+
+/** \brief Length for Ifx_HSCT_IRQEN_Bits.TXTEEN */
+#define IFX_HSCT_IRQEN_TXTEEN_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQEN_Bits.TXTEEN */
+#define IFX_HSCT_IRQEN_TXTEEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQEN_Bits.TXTEEN */
+#define IFX_HSCT_IRQEN_TXTEEN_OFF (10u)
+
+/** \brief Length for Ifx_HSCT_IRQEN_Bits.USMEN */
+#define IFX_HSCT_IRQEN_USMEN_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQEN_Bits.USMEN */
+#define IFX_HSCT_IRQEN_USMEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQEN_Bits.USMEN */
+#define IFX_HSCT_IRQEN_USMEN_OFF (8u)
+
+/** \brief Length for Ifx_HSCT_IRQEN_Bits.USMSFEN */
+#define IFX_HSCT_IRQEN_USMSFEN_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_IRQEN_Bits.USMSFEN */
+#define IFX_HSCT_IRQEN_USMSFEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_IRQEN_Bits.USMSFEN */
+#define IFX_HSCT_IRQEN_USMSFEN_OFF (6u)
+
+/** \brief Length for Ifx_HSCT_KRST0_Bits.RST */
+#define IFX_HSCT_KRST0_RST_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_KRST0_Bits.RST */
+#define IFX_HSCT_KRST0_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_KRST0_Bits.RST */
+#define IFX_HSCT_KRST0_RST_OFF (0u)
+
+/** \brief Length for Ifx_HSCT_KRST0_Bits.RSTSTAT */
+#define IFX_HSCT_KRST0_RSTSTAT_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_KRST0_Bits.RSTSTAT */
+#define IFX_HSCT_KRST0_RSTSTAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_KRST0_Bits.RSTSTAT */
+#define IFX_HSCT_KRST0_RSTSTAT_OFF (1u)
+
+/** \brief Length for Ifx_HSCT_KRST1_Bits.RST */
+#define IFX_HSCT_KRST1_RST_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_KRST1_Bits.RST */
+#define IFX_HSCT_KRST1_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_KRST1_Bits.RST */
+#define IFX_HSCT_KRST1_RST_OFF (0u)
+
+/** \brief Length for Ifx_HSCT_KRSTCLR_Bits.CLR */
+#define IFX_HSCT_KRSTCLR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_KRSTCLR_Bits.CLR */
+#define IFX_HSCT_KRSTCLR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_KRSTCLR_Bits.CLR */
+#define IFX_HSCT_KRSTCLR_CLR_OFF (0u)
+
+/** \brief Length for Ifx_HSCT_OCS_Bits.SUS */
+#define IFX_HSCT_OCS_SUS_LEN (4u)
+
+/** \brief Mask for Ifx_HSCT_OCS_Bits.SUS */
+#define IFX_HSCT_OCS_SUS_MSK (0xfu)
+
+/** \brief Offset for Ifx_HSCT_OCS_Bits.SUS */
+#define IFX_HSCT_OCS_SUS_OFF (24u)
+
+/** \brief Length for Ifx_HSCT_OCS_Bits.SUS_P */
+#define IFX_HSCT_OCS_SUS_P_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_OCS_Bits.SUS_P */
+#define IFX_HSCT_OCS_SUS_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_OCS_Bits.SUS_P */
+#define IFX_HSCT_OCS_SUS_P_OFF (28u)
+
+/** \brief Length for Ifx_HSCT_OCS_Bits.SUSSTA */
+#define IFX_HSCT_OCS_SUSSTA_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_OCS_Bits.SUSSTA */
+#define IFX_HSCT_OCS_SUSSTA_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_OCS_Bits.SUSSTA */
+#define IFX_HSCT_OCS_SUSSTA_OFF (29u)
+
+/** \brief Length for Ifx_HSCT_OCS_Bits.TG_P */
+#define IFX_HSCT_OCS_TG_P_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_OCS_Bits.TG_P */
+#define IFX_HSCT_OCS_TG_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_OCS_Bits.TG_P */
+#define IFX_HSCT_OCS_TG_P_OFF (3u)
+
+/** \brief Length for Ifx_HSCT_OCS_Bits.TGB */
+#define IFX_HSCT_OCS_TGB_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_OCS_Bits.TGB */
+#define IFX_HSCT_OCS_TGB_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_OCS_Bits.TGB */
+#define IFX_HSCT_OCS_TGB_OFF (2u)
+
+/** \brief Length for Ifx_HSCT_OCS_Bits.TGS */
+#define IFX_HSCT_OCS_TGS_LEN (2u)
+
+/** \brief Mask for Ifx_HSCT_OCS_Bits.TGS */
+#define IFX_HSCT_OCS_TGS_MSK (0x3u)
+
+/** \brief Offset for Ifx_HSCT_OCS_Bits.TGS */
+#define IFX_HSCT_OCS_TGS_OFF (0u)
+
+/** \brief Length for Ifx_HSCT_SLEEPCTRL_Bits.SLPCLKG */
+#define IFX_HSCT_SLEEPCTRL_SLPCLKG_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_SLEEPCTRL_Bits.SLPCLKG */
+#define IFX_HSCT_SLEEPCTRL_SLPCLKG_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_SLEEPCTRL_Bits.SLPCLKG */
+#define IFX_HSCT_SLEEPCTRL_SLPCLKG_OFF (1u)
+
+/** \brief Length for Ifx_HSCT_SLEEPCTRL_Bits.SLPEN */
+#define IFX_HSCT_SLEEPCTRL_SLPEN_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_SLEEPCTRL_Bits.SLPEN */
+#define IFX_HSCT_SLEEPCTRL_SLPEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_SLEEPCTRL_Bits.SLPEN */
+#define IFX_HSCT_SLEEPCTRL_SLPEN_OFF (0u)
+
+/** \brief Length for Ifx_HSCT_STAT_Bits.LIFCCMDR */
+#define IFX_HSCT_STAT_LIFCCMDR_LEN (8u)
+
+/** \brief Mask for Ifx_HSCT_STAT_Bits.LIFCCMDR */
+#define IFX_HSCT_STAT_LIFCCMDR_MSK (0xffu)
+
+/** \brief Offset for Ifx_HSCT_STAT_Bits.LIFCCMDR */
+#define IFX_HSCT_STAT_LIFCCMDR_OFF (24u)
+
+/** \brief Length for Ifx_HSCT_STAT_Bits.RX_CHANNEL */
+#define IFX_HSCT_STAT_RX_CHANNEL_LEN (4u)
+
+/** \brief Mask for Ifx_HSCT_STAT_Bits.RX_CHANNEL */
+#define IFX_HSCT_STAT_RX_CHANNEL_MSK (0xfu)
+
+/** \brief Offset for Ifx_HSCT_STAT_Bits.RX_CHANNEL */
+#define IFX_HSCT_STAT_RX_CHANNEL_OFF (3u)
+
+/** \brief Length for Ifx_HSCT_STAT_Bits.RX_PSIZE */
+#define IFX_HSCT_STAT_RX_PSIZE_LEN (3u)
+
+/** \brief Mask for Ifx_HSCT_STAT_Bits.RX_PSIZE */
+#define IFX_HSCT_STAT_RX_PSIZE_MSK (0x7u)
+
+/** \brief Offset for Ifx_HSCT_STAT_Bits.RX_PSIZE */
+#define IFX_HSCT_STAT_RX_PSIZE_OFF (0u)
+
+/** \brief Length for Ifx_HSCT_STAT_Bits.RX_SLEEP */
+#define IFX_HSCT_STAT_RX_SLEEP_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_STAT_Bits.RX_SLEEP */
+#define IFX_HSCT_STAT_RX_SLEEP_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_STAT_Bits.RX_SLEEP */
+#define IFX_HSCT_STAT_RX_SLEEP_OFF (7u)
+
+/** \brief Length for Ifx_HSCT_STAT_Bits.TX_CHANNEL_TYPE */
+#define IFX_HSCT_STAT_TX_CHANNEL_TYPE_LEN (4u)
+
+/** \brief Mask for Ifx_HSCT_STAT_Bits.TX_CHANNEL_TYPE */
+#define IFX_HSCT_STAT_TX_CHANNEL_TYPE_MSK (0xfu)
+
+/** \brief Offset for Ifx_HSCT_STAT_Bits.TX_CHANNEL_TYPE */
+#define IFX_HSCT_STAT_TX_CHANNEL_TYPE_OFF (16u)
+
+/** \brief Length for Ifx_HSCT_STAT_Bits.TX_PSIZE */
+#define IFX_HSCT_STAT_TX_PSIZE_LEN (3u)
+
+/** \brief Mask for Ifx_HSCT_STAT_Bits.TX_PSIZE */
+#define IFX_HSCT_STAT_TX_PSIZE_MSK (0x7u)
+
+/** \brief Offset for Ifx_HSCT_STAT_Bits.TX_PSIZE */
+#define IFX_HSCT_STAT_TX_PSIZE_OFF (12u)
+
+/** \brief Length for Ifx_HSCT_STAT_Bits.TX_SLEEP */
+#define IFX_HSCT_STAT_TX_SLEEP_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_STAT_Bits.TX_SLEEP */
+#define IFX_HSCT_STAT_TX_SLEEP_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_STAT_Bits.TX_SLEEP */
+#define IFX_HSCT_STAT_TX_SLEEP_OFF (8u)
+
+/** \brief Length for Ifx_HSCT_STATPHY_Bits.PLOCK */
+#define IFX_HSCT_STATPHY_PLOCK_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_STATPHY_Bits.PLOCK */
+#define IFX_HSCT_STATPHY_PLOCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_STATPHY_Bits.PLOCK */
+#define IFX_HSCT_STATPHY_PLOCK_OFF (0u)
+
+/** \brief Length for Ifx_HSCT_STATPHY_Bits.RXLSA */
+#define IFX_HSCT_STATPHY_RXLSA_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_STATPHY_Bits.RXLSA */
+#define IFX_HSCT_STATPHY_RXLSA_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_STATPHY_Bits.RXLSA */
+#define IFX_HSCT_STATPHY_RXLSA_OFF (1u)
+
+/** \brief Length for Ifx_HSCT_STATPHY_Bits.TXLSA */
+#define IFX_HSCT_STATPHY_TXLSA_LEN (1u)
+
+/** \brief Mask for Ifx_HSCT_STATPHY_Bits.TXLSA */
+#define IFX_HSCT_STATPHY_TXLSA_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSCT_STATPHY_Bits.TXLSA */
+#define IFX_HSCT_STATPHY_TXLSA_OFF (2u)
+
+/** \brief Length for Ifx_HSCT_USMR_Bits.USMR */
+#define IFX_HSCT_USMR_USMR_LEN (32u)
+
+/** \brief Mask for Ifx_HSCT_USMR_Bits.USMR */
+#define IFX_HSCT_USMR_USMR_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_HSCT_USMR_Bits.USMR */
+#define IFX_HSCT_USMR_USMR_OFF (0u)
+
+/** \brief Length for Ifx_HSCT_USMS_Bits.USMS */
+#define IFX_HSCT_USMS_USMS_LEN (32u)
+
+/** \brief Mask for Ifx_HSCT_USMS_Bits.USMS */
+#define IFX_HSCT_USMS_USMS_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_HSCT_USMS_Bits.USMS */
+#define IFX_HSCT_USMS_USMS_OFF (0u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXHSCT_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxHsct_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxHsct_reg.h
new file mode 100644
index 0000000..087855a
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxHsct_reg.h
@@ -0,0 +1,117 @@
+/**
+ * \file IfxHsct_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Hsct_Cfg Hsct address
+ * \ingroup IfxLld_Hsct
+ *
+ * \defgroup IfxLld_Hsct_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Hsct_Cfg
+ *
+ * \defgroup IfxLld_Hsct_Cfg_Hsct 2-HSCT
+ * \ingroup IfxLld_Hsct_Cfg
+ *
+ */
+#ifndef IFXHSCT_REG_H
+#define IFXHSCT_REG_H 1
+/******************************************************************************/
+#include "IfxHsct_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Hsct_Cfg_BaseAddress
+ * \{ */
+
+/** \brief HSCT object */
+#define MODULE_HSCT /*lint --e(923)*/ (*(Ifx_HSCT*)0xF0090000u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Hsct_Cfg_Hsct
+ * \{ */
+
+/** \brief FFFC, Access Enable Register 0 */
+#define HSCT_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_HSCT_ACCEN0*)0xF009FFFCu)
+
+/** \brief FFF8, Access Enable Register 1 */
+#define HSCT_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_HSCT_ACCEN1*)0xF009FFF8u)
+
+/** \brief 0, Clock Control Register */
+#define HSCT_CLC /*lint --e(923)*/ (*(volatile Ifx_HSCT_CLC*)0xF0090000u)
+
+/** \brief 30, Configuration physical layer register */
+#define HSCT_CONFIGPHY /*lint --e(923)*/ (*(volatile Ifx_HSCT_CONFIGPHY*)0xF0090030u)
+
+/** \brief 1C, Clear To Send Control Register */
+#define HSCT_CTSCTRL /*lint --e(923)*/ (*(volatile Ifx_HSCT_CTSCTRL*)0xF009001Cu)
+
+/** \brief 20, Transmission Disable Register */
+#define HSCT_DISABLE /*lint --e(923)*/ (*(volatile Ifx_HSCT_DISABLE*)0xF0090020u)
+
+/** \brief 8, Module Identification Register */
+#define HSCT_ID /*lint --e(923)*/ (*(volatile Ifx_HSCT_ID*)0xF0090008u)
+
+/** \brief 14, CPU transfer control register */
+#define HSCT_IFCTRL /*lint --e(923)*/ (*(volatile Ifx_HSCT_IFCTRL*)0xF0090014u)
+
+/** \brief 28, Interface Status Register */
+#define HSCT_IFSTAT /*lint --e(923)*/ (*(volatile Ifx_HSCT_IFSTAT*)0xF0090028u)
+
+/** \brief 10, Initialization register */
+#define HSCT_INIT /*lint --e(923)*/ (*(volatile Ifx_HSCT_INIT*)0xF0090010u)
+
+/** \brief 40, Interrupt register */
+#define HSCT_IRQ /*lint --e(923)*/ (*(volatile Ifx_HSCT_IRQ*)0xF0090040u)
+
+/** \brief 48, Interrupt clear register */
+#define HSCT_IRQCLR /*lint --e(923)*/ (*(volatile Ifx_HSCT_IRQCLR*)0xF0090048u)
+
+/** \brief 44, Interrupt enable register */
+#define HSCT_IRQEN /*lint --e(923)*/ (*(volatile Ifx_HSCT_IRQEN*)0xF0090044u)
+
+/** \brief FFF4, Reset Register 0 */
+#define HSCT_KRST0 /*lint --e(923)*/ (*(volatile Ifx_HSCT_KRST0*)0xF009FFF4u)
+
+/** \brief FFF0, Reset Register 1 */
+#define HSCT_KRST1 /*lint --e(923)*/ (*(volatile Ifx_HSCT_KRST1*)0xF009FFF0u)
+
+/** \brief FFEC, Reset Status Clear Register */
+#define HSCT_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_HSCT_KRSTCLR*)0xF009FFECu)
+
+/** \brief FFE8, OCDS Control and Status */
+#define HSCT_OCS /*lint --e(923)*/ (*(volatile Ifx_HSCT_OCS*)0xF009FFE8u)
+
+/** \brief 18, Sleep Control Register */
+#define HSCT_SLEEPCTRL /*lint --e(923)*/ (*(volatile Ifx_HSCT_SLEEPCTRL*)0xF0090018u)
+
+/** \brief 24, Status Register */
+#define HSCT_STAT /*lint --e(923)*/ (*(volatile Ifx_HSCT_STAT*)0xF0090024u)
+
+/** \brief 34, STATPHY */
+#define HSCT_STATPHY /*lint --e(923)*/ (*(volatile Ifx_HSCT_STATPHY*)0xF0090034u)
+
+/** \brief 50, Unsolicited Status Message Received */
+#define HSCT_USMR /*lint --e(923)*/ (*(volatile Ifx_HSCT_USMR*)0xF0090050u)
+
+/** \brief 54, Unsolicited Status Message Send */
+#define HSCT_USMS /*lint --e(923)*/ (*(volatile Ifx_HSCT_USMS*)0xF0090054u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXHSCT_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxHsct_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxHsct_regdef.h
new file mode 100644
index 0000000..f3eee35
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxHsct_regdef.h
@@ -0,0 +1,538 @@
+/**
+ * \file IfxHsct_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Hsct Hsct
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Hsct_Bitfields Bitfields
+ * \ingroup IfxLld_Hsct
+ *
+ * \defgroup IfxLld_Hsct_union Union
+ * \ingroup IfxLld_Hsct
+ *
+ * \defgroup IfxLld_Hsct_struct Struct
+ * \ingroup IfxLld_Hsct
+ *
+ */
+#ifndef IFXHSCT_REGDEF_H
+#define IFXHSCT_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Hsct_Bitfields
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef struct _Ifx_HSCT_ACCEN0_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_HSCT_ACCEN0_Bits;
+
+/** \brief Access Enable Register 1 */
+typedef struct _Ifx_HSCT_ACCEN1_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_HSCT_ACCEN1_Bits;
+
+/** \brief Clock Control Register */
+typedef struct _Ifx_HSCT_CLC_Bits
+{
+ unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
+ unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (r) */
+ unsigned int reserved_2:1; /**< \brief \internal Reserved */
+ unsigned int EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control (rw) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_HSCT_CLC_Bits;
+
+/** \brief Configuration physical layer register */
+typedef struct _Ifx_HSCT_CONFIGPHY_Bits
+{
+ unsigned int reserved_0:1; /**< \brief \internal Reserved */
+ unsigned int PLLPON:1; /**< \brief [1:1] PLL Power On (Master Mode only) (rw) */
+ unsigned int PLLPE:6; /**< \brief [7:2] PLL phase enable - allows to enable/disable each of the 6 Phase outputs. (rw) */
+ unsigned int PLLWMF:6; /**< \brief [13:8] PLL frequency control word multiplication factor (rw) */
+ unsigned int PLLKPKI:1; /**< \brief [14:14] KP/KI Setting (rw) */
+ unsigned int PHYRST:1; /**< \brief [15:15] Physical Layer Reset (rw) */
+ unsigned int PLLKP:3; /**< \brief [18:16] KP of PLL - Configuration of PLL beta coefficients of proportional part of loop filter (rw) */
+ unsigned int PLLKI:3; /**< \brief [21:19] KI of PLL - Configuration of PLL alpha coefficients of integral part of loop filter (rw) */
+ unsigned int PLLIVR:4; /**< \brief [25:22] Adjustment for integrated voltage regulator (rw) */
+ unsigned int reserved_26:2; /**< \brief \internal Reserved */
+ unsigned int OSCCLKEN:1; /**< \brief [28:28] Enable Oscillator Clock as PLL reference clock (rw) */
+ unsigned int reserved_29:3; /**< \brief \internal Reserved */
+} Ifx_HSCT_CONFIGPHY_Bits;
+
+/** \brief Clear To Send Control Register */
+typedef struct _Ifx_HSCT_CTSCTRL_Bits
+{
+ unsigned int CTS_FRAME:1; /**< \brief [0:0] Transmit CTS Frame Generation (rw) */
+ unsigned int CTS_TXD:1; /**< \brief [1:1] Disable TX CTS signaling (rw) */
+ unsigned int CTS_RXD:1; /**< \brief [2:2] Disable RX CTS detection (rw) */
+ unsigned int HSSL_CTS_FBD:1; /**< \brief [3:3] Disable HSSL interface CTS Frame Blocking (rw) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_HSCT_CTSCTRL_Bits;
+
+/** \brief Transmission Disable Register */
+typedef struct _Ifx_HSCT_DISABLE_Bits
+{
+ unsigned int TX_DIS:1; /**< \brief [0:0] Disable HSCT Transmit path in Master interface (rw) */
+ unsigned int RX_DIS:1; /**< \brief [1:1] Disable HSCT Receive path in Master interface (rw) */
+ unsigned int RX_HEPD:1; /**< \brief [2:2] Disable RX Header Error Discard Payload data. (rw) */
+ unsigned int reserved_3:29; /**< \brief \internal Reserved */
+} Ifx_HSCT_DISABLE_Bits;
+
+/** \brief Module Identification Register */
+typedef struct _Ifx_HSCT_ID_Bits
+{
+ unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
+ unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_HSCT_ID_Bits;
+
+/** \brief CPU transfer control register */
+typedef struct _Ifx_HSCT_IFCTRL_Bits
+{
+ unsigned int IFCVS:8; /**< \brief [7:0] Master Mode - Interface Control Value to be send to Slave interface (rw) */
+ unsigned int SIFCV:1; /**< \brief [8:8] Master Mode - Slave IF control frame trigger (w) */
+ unsigned int reserved_9:7; /**< \brief \internal Reserved */
+ unsigned int MRXSPEED:2; /**< \brief [17:16] Master Mode RX speed (rw) */
+ unsigned int MTXSPEED:2; /**< \brief [19:18] Master Mode TX speed (rw) */
+ unsigned int IFTESTMD:1; /**< \brief [20:20] Master Mode Interface Test Mode (rw) */
+ unsigned int reserved_21:11; /**< \brief \internal Reserved */
+} Ifx_HSCT_IFCTRL_Bits;
+
+/** \brief Interface Status Register */
+typedef struct _Ifx_HSCT_IFSTAT_Bits
+{
+ unsigned int RX_STAT:3; /**< \brief [2:0] HSCT slave interface Status for RX link (rh) */
+ unsigned int TX_STAT:2; /**< \brief [4:3] HSCT slave interface Status for TX link (rh) */
+ unsigned int reserved_5:27; /**< \brief \internal Reserved */
+} Ifx_HSCT_IFSTAT_Bits;
+
+/** \brief Initialization register */
+typedef struct _Ifx_HSCT_INIT_Bits
+{
+ unsigned int reserved_0:1; /**< \brief \internal Reserved */
+ unsigned int SYS_CLK_EN:1; /**< \brief [1:1] Enable SysClk in Master interface (rw) */
+ unsigned int SRCF:1; /**< \brief [2:2] Select SysClk / Reference Clock Frequency rate (rw) */
+ unsigned int IFM:1; /**< \brief [3:3] Select Interface Mode (rw) */
+ unsigned int reserved_4:6; /**< \brief \internal Reserved */
+ unsigned int LHLR:1; /**< \brief [10:10] Loopback path at Slave interface side at higher layer system RAM. (rw) */
+ unsigned int reserved_11:5; /**< \brief \internal Reserved */
+ unsigned int TXHD:3; /**< \brief [18:16] Transmit High Speed Divider. (rw) */
+ unsigned int RXHD:3; /**< \brief [21:19] Receive High Speed Divider. (rw) */
+ unsigned int reserved_22:10; /**< \brief \internal Reserved */
+} Ifx_HSCT_INIT_Bits;
+
+/** \brief Interrupt register */
+typedef struct _Ifx_HSCT_IRQ_Bits
+{
+ unsigned int reserved_0:1; /**< \brief \internal Reserved */
+ unsigned int HER:1; /**< \brief [1:1] Header error detected (rh) */
+ unsigned int PYER:1; /**< \brief [2:2] Payload error detected (rh) */
+ unsigned int CER:1; /**< \brief [3:3] HSCT command error (rh) */
+ unsigned int IFCFS:1; /**< \brief [4:4] HSCT interface control frame send (rh) */
+ unsigned int SMER:1; /**< \brief [5:5] Speed Mode Switch Error (Master Mode only) (rh) */
+ unsigned int USMSF:1; /**< \brief [6:6] Unsolicited message frame send finished (rh) */
+ unsigned int PLER:1; /**< \brief [7:7] PLL lost lock error (rh) */
+ unsigned int USM:1; /**< \brief [8:8] Unsolicited Message Received (rh) */
+ unsigned int PAR:1; /**< \brief [9:9] PING Answer Received (rh) */
+ unsigned int TXTE:1; /**< \brief [10:10] TX transfer error occurred on a disabled TX channel. (rh) */
+ unsigned int SFO:1; /**< \brief [11:11] Synchronization FIFO overflow (in RX direction) (rh) */
+ unsigned int SFU:1; /**< \brief [12:12] Synchronization FIFO underflow (in TX direction) (rh) */
+ unsigned int reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_HSCT_IRQ_Bits;
+
+/** \brief Interrupt clear register */
+typedef struct _Ifx_HSCT_IRQCLR_Bits
+{
+ unsigned int reserved_0:1; /**< \brief \internal Reserved */
+ unsigned int HERCLR:1; /**< \brief [1:1] Header error detected interrupt clear (w) */
+ unsigned int PYERCLR:1; /**< \brief [2:2] Payload error detected interrupt clear (w) */
+ unsigned int CERCLR:1; /**< \brief [3:3] HSCT command error interrupt clear (w) */
+ unsigned int IFCFSCLR:1; /**< \brief [4:4] HSCT interface control command send interrupt clear (w) */
+ unsigned int SMERCLR:1; /**< \brief [5:5] Speed Mode Switch Error interrupt clear (w) */
+ unsigned int USMSFCLR:1; /**< \brief [6:6] Unsolicited message frame send finished interrupt clear (w) */
+ unsigned int PLERCLR:1; /**< \brief [7:7] PLL lost lock error interrupt clear (w) */
+ unsigned int USMCLR:1; /**< \brief [8:8] Unsolicited Message received clear (w) */
+ unsigned int PARCLR:1; /**< \brief [9:9] PING Answer received clear (w) */
+ unsigned int TXTECLR:1; /**< \brief [10:10] TX disable error interrupt clear (w) */
+ unsigned int SFOCLR:1; /**< \brief [11:11] Synchronization FIFO overflow (in RX direction) interrupt clear (w) */
+ unsigned int SFUCLR:1; /**< \brief [12:12] Synchronization FIFO underflow (in TX direction) interrupt clear (w) */
+ unsigned int reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_HSCT_IRQCLR_Bits;
+
+/** \brief Interrupt enable register */
+typedef struct _Ifx_HSCT_IRQEN_Bits
+{
+ unsigned int reserved_0:1; /**< \brief \internal Reserved */
+ unsigned int HEREN:1; /**< \brief [1:1] Header error detected interrupt enable (rw) */
+ unsigned int PYEREN:1; /**< \brief [2:2] Payload error detected interrupt enable (rw) */
+ unsigned int CEREN:1; /**< \brief [3:3] HSCT command error interrupt enable (rw) */
+ unsigned int IFCFSEN:1; /**< \brief [4:4] HSCT interface control command send enable (rw) */
+ unsigned int SMEREN:1; /**< \brief [5:5] Speed Mode Switch Error interrupt enable (rw) */
+ unsigned int USMSFEN:1; /**< \brief [6:6] Unsolicited message frame send finished (rw) */
+ unsigned int PLEREN:1; /**< \brief [7:7] PLL lost lock error interrupt enable (rw) */
+ unsigned int USMEN:1; /**< \brief [8:8] Unsolicited Message received enable (rw) */
+ unsigned int PAREN:1; /**< \brief [9:9] PING Answer Received enable (rw) */
+ unsigned int TXTEEN:1; /**< \brief [10:10] TX disable error interrupt enable (rw) */
+ unsigned int SFOEN:1; /**< \brief [11:11] Synchronization FIFO overflow (in RX direction) interrupt enable (rw) */
+ unsigned int SFUEN:1; /**< \brief [12:12] Synchronization FIFO underflow (in TX direction) interrupt enable (rw) */
+ unsigned int reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_HSCT_IRQEN_Bits;
+
+/** \brief Reset Register 0 */
+typedef struct _Ifx_HSCT_KRST0_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rh) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_HSCT_KRST0_Bits;
+
+/** \brief Reset Register 1 */
+typedef struct _Ifx_HSCT_KRST1_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_HSCT_KRST1_Bits;
+
+/** \brief Reset Status Clear Register */
+typedef struct _Ifx_HSCT_KRSTCLR_Bits
+{
+ unsigned int CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_HSCT_KRSTCLR_Bits;
+
+/** \brief OCDS Control and Status */
+typedef struct _Ifx_HSCT_OCS_Bits
+{
+ unsigned int TGS:2; /**< \brief [1:0] Trigger Set for OTGB0/1 (rw) */
+ unsigned int TGB:1; /**< \brief [2:2] OTGB0/1 Bus Select (rw) */
+ unsigned int TG_P:1; /**< \brief [3:3] TGS, TGB Write Protection (w) */
+ unsigned int reserved_4:20; /**< \brief \internal Reserved */
+ unsigned int SUS:4; /**< \brief [27:24] OCDS Suspend Control (rw) */
+ unsigned int SUS_P:1; /**< \brief [28:28] SUS Write Protection (w) */
+ unsigned int SUSSTA:1; /**< \brief [29:29] Suspend State (rh) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_HSCT_OCS_Bits;
+
+/** \brief Sleep Control Register */
+typedef struct _Ifx_HSCT_SLEEPCTRL_Bits
+{
+ unsigned int SLPEN:1; /**< \brief [0:0] Sleep mode enabled (rw) */
+ unsigned int SLPCLKG:1; /**< \brief [1:1] Clock Gating in Sleep Mode (rw) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_HSCT_SLEEPCTRL_Bits;
+
+/** \brief Status Register */
+typedef struct _Ifx_HSCT_STAT_Bits
+{
+ unsigned int RX_PSIZE:3; /**< \brief [2:0] RX (receiving) Payload Size (rh) */
+ unsigned int RX_CHANNEL:4; /**< \brief [6:3] RX (receiving) Logical Channel Type (rh) */
+ unsigned int RX_SLEEP:1; /**< \brief [7:7] RX (receiving) Sleep Mode Status (rh) */
+ unsigned int TX_SLEEP:1; /**< \brief [8:8] TX (transmitting) Sleep Mode Status (rh) */
+ unsigned int reserved_9:3; /**< \brief \internal Reserved */
+ unsigned int TX_PSIZE:3; /**< \brief [14:12] Transmission Payload Size (rh) */
+ unsigned int reserved_15:1; /**< \brief \internal Reserved */
+ unsigned int TX_CHANNEL_TYPE:4; /**< \brief [19:16] Transmission Logical Channel Type (rh) */
+ unsigned int reserved_20:4; /**< \brief \internal Reserved */
+ unsigned int LIFCCMDR:8; /**< \brief [31:24] Last Interface Control Command Received (rh) */
+} Ifx_HSCT_STAT_Bits;
+
+/** \brief STATPHY */
+typedef struct _Ifx_HSCT_STATPHY_Bits
+{
+ unsigned int PLOCK:1; /**< \brief [0:0] PLL locked (rh) */
+ unsigned int RXLSA:1; /**< \brief [1:1] Receiver in Low speed (rh) */
+ unsigned int TXLSA:1; /**< \brief [2:2] Transmitter in Low speed (rh) */
+ unsigned int reserved_3:29; /**< \brief \internal Reserved */
+} Ifx_HSCT_STATPHY_Bits;
+
+/** \brief Unsolicited Status Message Received */
+typedef struct _Ifx_HSCT_USMR_Bits
+{
+ unsigned int USMR:32; /**< \brief [31:0] Unsolicited status message received (rh) */
+} Ifx_HSCT_USMR_Bits;
+
+/** \brief Unsolicited Status Message Send */
+typedef struct _Ifx_HSCT_USMS_Bits
+{
+ unsigned int USMS:32; /**< \brief [31:0] Unsolicited status message send (rw) */
+} Ifx_HSCT_USMS_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Hsct_union
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSCT_ACCEN0_Bits B; /**< \brief Bitfield access */
+} Ifx_HSCT_ACCEN0;
+
+/** \brief Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSCT_ACCEN1_Bits B; /**< \brief Bitfield access */
+} Ifx_HSCT_ACCEN1;
+
+/** \brief Clock Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSCT_CLC_Bits B; /**< \brief Bitfield access */
+} Ifx_HSCT_CLC;
+
+/** \brief Configuration physical layer register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSCT_CONFIGPHY_Bits B; /**< \brief Bitfield access */
+} Ifx_HSCT_CONFIGPHY;
+
+/** \brief Clear To Send Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSCT_CTSCTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_HSCT_CTSCTRL;
+
+/** \brief Transmission Disable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSCT_DISABLE_Bits B; /**< \brief Bitfield access */
+} Ifx_HSCT_DISABLE;
+
+/** \brief Module Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSCT_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_HSCT_ID;
+
+/** \brief CPU transfer control register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSCT_IFCTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_HSCT_IFCTRL;
+
+/** \brief Interface Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSCT_IFSTAT_Bits B; /**< \brief Bitfield access */
+} Ifx_HSCT_IFSTAT;
+
+/** \brief Initialization register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSCT_INIT_Bits B; /**< \brief Bitfield access */
+} Ifx_HSCT_INIT;
+
+/** \brief Interrupt register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSCT_IRQ_Bits B; /**< \brief Bitfield access */
+} Ifx_HSCT_IRQ;
+
+/** \brief Interrupt clear register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSCT_IRQCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_HSCT_IRQCLR;
+
+/** \brief Interrupt enable register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSCT_IRQEN_Bits B; /**< \brief Bitfield access */
+} Ifx_HSCT_IRQEN;
+
+/** \brief Reset Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSCT_KRST0_Bits B; /**< \brief Bitfield access */
+} Ifx_HSCT_KRST0;
+
+/** \brief Reset Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSCT_KRST1_Bits B; /**< \brief Bitfield access */
+} Ifx_HSCT_KRST1;
+
+/** \brief Reset Status Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSCT_KRSTCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_HSCT_KRSTCLR;
+
+/** \brief OCDS Control and Status */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSCT_OCS_Bits B; /**< \brief Bitfield access */
+} Ifx_HSCT_OCS;
+
+/** \brief Sleep Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSCT_SLEEPCTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_HSCT_SLEEPCTRL;
+
+/** \brief Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSCT_STAT_Bits B; /**< \brief Bitfield access */
+} Ifx_HSCT_STAT;
+
+/** \brief STATPHY */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSCT_STATPHY_Bits B; /**< \brief Bitfield access */
+} Ifx_HSCT_STATPHY;
+
+/** \brief Unsolicited Status Message Received */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSCT_USMR_Bits B; /**< \brief Bitfield access */
+} Ifx_HSCT_USMR;
+
+/** \brief Unsolicited Status Message Send */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSCT_USMS_Bits B; /**< \brief Bitfield access */
+} Ifx_HSCT_USMS;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Hsct_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief HSCT object */
+typedef volatile struct _Ifx_HSCT
+{
+ Ifx_HSCT_CLC CLC; /**< \brief 0, Clock Control Register */
+ unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
+ Ifx_HSCT_ID ID; /**< \brief 8, Module Identification Register */
+ unsigned char reserved_C[4]; /**< \brief C, \internal Reserved */
+ Ifx_HSCT_INIT INIT; /**< \brief 10, Initialization register */
+ Ifx_HSCT_IFCTRL IFCTRL; /**< \brief 14, CPU transfer control register */
+ Ifx_HSCT_SLEEPCTRL SLEEPCTRL; /**< \brief 18, Sleep Control Register */
+ Ifx_HSCT_CTSCTRL CTSCTRL; /**< \brief 1C, Clear To Send Control Register */
+ Ifx_HSCT_DISABLE DISABLE; /**< \brief 20, Transmission Disable Register */
+ Ifx_HSCT_STAT STAT; /**< \brief 24, Status Register */
+ Ifx_HSCT_IFSTAT IFSTAT; /**< \brief 28, Interface Status Register */
+ unsigned char reserved_2C[4]; /**< \brief 2C, \internal Reserved */
+ Ifx_HSCT_CONFIGPHY CONFIGPHY; /**< \brief 30, Configuration physical layer register */
+ Ifx_HSCT_STATPHY STATPHY; /**< \brief 34, STATPHY */
+ unsigned char reserved_38[8]; /**< \brief 38, \internal Reserved */
+ Ifx_HSCT_IRQ IRQ; /**< \brief 40, Interrupt register */
+ Ifx_HSCT_IRQEN IRQEN; /**< \brief 44, Interrupt enable register */
+ Ifx_HSCT_IRQCLR IRQCLR; /**< \brief 48, Interrupt clear register */
+ unsigned char reserved_4C[4]; /**< \brief 4C, \internal Reserved */
+ Ifx_HSCT_USMR USMR; /**< \brief 50, Unsolicited Status Message Received */
+ Ifx_HSCT_USMS USMS; /**< \brief 54, Unsolicited Status Message Send */
+ unsigned char reserved_58[65424]; /**< \brief 58, \internal Reserved */
+ Ifx_HSCT_OCS OCS; /**< \brief FFE8, OCDS Control and Status */
+ Ifx_HSCT_KRSTCLR KRSTCLR; /**< \brief FFEC, Reset Status Clear Register */
+ Ifx_HSCT_KRST1 KRST1; /**< \brief FFF0, Reset Register 1 */
+ Ifx_HSCT_KRST0 KRST0; /**< \brief FFF4, Reset Register 0 */
+ Ifx_HSCT_ACCEN1 ACCEN1; /**< \brief FFF8, Access Enable Register 1 */
+ Ifx_HSCT_ACCEN0 ACCEN0; /**< \brief FFFC, Access Enable Register 0 */
+} Ifx_HSCT;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXHSCT_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxHssl_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxHssl_bf.h
new file mode 100644
index 0000000..6bd20c3
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxHssl_bf.h
@@ -0,0 +1,1521 @@
+/**
+ * \file IfxHssl_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Hssl_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Hssl
+ *
+ */
+#ifndef IFXHSSL_BF_H
+#define IFXHSSL_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Hssl_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN0 */
+#define IFX_HSSL_ACCEN0_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN0 */
+#define IFX_HSSL_ACCEN0_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN0 */
+#define IFX_HSSL_ACCEN0_EN0_OFF (0u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN10 */
+#define IFX_HSSL_ACCEN0_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN10 */
+#define IFX_HSSL_ACCEN0_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN10 */
+#define IFX_HSSL_ACCEN0_EN10_OFF (10u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN11 */
+#define IFX_HSSL_ACCEN0_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN11 */
+#define IFX_HSSL_ACCEN0_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN11 */
+#define IFX_HSSL_ACCEN0_EN11_OFF (11u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN12 */
+#define IFX_HSSL_ACCEN0_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN12 */
+#define IFX_HSSL_ACCEN0_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN12 */
+#define IFX_HSSL_ACCEN0_EN12_OFF (12u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN13 */
+#define IFX_HSSL_ACCEN0_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN13 */
+#define IFX_HSSL_ACCEN0_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN13 */
+#define IFX_HSSL_ACCEN0_EN13_OFF (13u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN14 */
+#define IFX_HSSL_ACCEN0_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN14 */
+#define IFX_HSSL_ACCEN0_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN14 */
+#define IFX_HSSL_ACCEN0_EN14_OFF (14u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN15 */
+#define IFX_HSSL_ACCEN0_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN15 */
+#define IFX_HSSL_ACCEN0_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN15 */
+#define IFX_HSSL_ACCEN0_EN15_OFF (15u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN16 */
+#define IFX_HSSL_ACCEN0_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN16 */
+#define IFX_HSSL_ACCEN0_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN16 */
+#define IFX_HSSL_ACCEN0_EN16_OFF (16u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN17 */
+#define IFX_HSSL_ACCEN0_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN17 */
+#define IFX_HSSL_ACCEN0_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN17 */
+#define IFX_HSSL_ACCEN0_EN17_OFF (17u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN18 */
+#define IFX_HSSL_ACCEN0_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN18 */
+#define IFX_HSSL_ACCEN0_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN18 */
+#define IFX_HSSL_ACCEN0_EN18_OFF (18u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN19 */
+#define IFX_HSSL_ACCEN0_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN19 */
+#define IFX_HSSL_ACCEN0_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN19 */
+#define IFX_HSSL_ACCEN0_EN19_OFF (19u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN1 */
+#define IFX_HSSL_ACCEN0_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN1 */
+#define IFX_HSSL_ACCEN0_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN1 */
+#define IFX_HSSL_ACCEN0_EN1_OFF (1u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN20 */
+#define IFX_HSSL_ACCEN0_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN20 */
+#define IFX_HSSL_ACCEN0_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN20 */
+#define IFX_HSSL_ACCEN0_EN20_OFF (20u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN21 */
+#define IFX_HSSL_ACCEN0_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN21 */
+#define IFX_HSSL_ACCEN0_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN21 */
+#define IFX_HSSL_ACCEN0_EN21_OFF (21u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN22 */
+#define IFX_HSSL_ACCEN0_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN22 */
+#define IFX_HSSL_ACCEN0_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN22 */
+#define IFX_HSSL_ACCEN0_EN22_OFF (22u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN23 */
+#define IFX_HSSL_ACCEN0_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN23 */
+#define IFX_HSSL_ACCEN0_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN23 */
+#define IFX_HSSL_ACCEN0_EN23_OFF (23u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN24 */
+#define IFX_HSSL_ACCEN0_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN24 */
+#define IFX_HSSL_ACCEN0_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN24 */
+#define IFX_HSSL_ACCEN0_EN24_OFF (24u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN25 */
+#define IFX_HSSL_ACCEN0_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN25 */
+#define IFX_HSSL_ACCEN0_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN25 */
+#define IFX_HSSL_ACCEN0_EN25_OFF (25u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN26 */
+#define IFX_HSSL_ACCEN0_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN26 */
+#define IFX_HSSL_ACCEN0_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN26 */
+#define IFX_HSSL_ACCEN0_EN26_OFF (26u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN27 */
+#define IFX_HSSL_ACCEN0_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN27 */
+#define IFX_HSSL_ACCEN0_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN27 */
+#define IFX_HSSL_ACCEN0_EN27_OFF (27u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN28 */
+#define IFX_HSSL_ACCEN0_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN28 */
+#define IFX_HSSL_ACCEN0_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN28 */
+#define IFX_HSSL_ACCEN0_EN28_OFF (28u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN29 */
+#define IFX_HSSL_ACCEN0_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN29 */
+#define IFX_HSSL_ACCEN0_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN29 */
+#define IFX_HSSL_ACCEN0_EN29_OFF (29u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN2 */
+#define IFX_HSSL_ACCEN0_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN2 */
+#define IFX_HSSL_ACCEN0_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN2 */
+#define IFX_HSSL_ACCEN0_EN2_OFF (2u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN30 */
+#define IFX_HSSL_ACCEN0_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN30 */
+#define IFX_HSSL_ACCEN0_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN30 */
+#define IFX_HSSL_ACCEN0_EN30_OFF (30u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN31 */
+#define IFX_HSSL_ACCEN0_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN31 */
+#define IFX_HSSL_ACCEN0_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN31 */
+#define IFX_HSSL_ACCEN0_EN31_OFF (31u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN3 */
+#define IFX_HSSL_ACCEN0_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN3 */
+#define IFX_HSSL_ACCEN0_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN3 */
+#define IFX_HSSL_ACCEN0_EN3_OFF (3u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN4 */
+#define IFX_HSSL_ACCEN0_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN4 */
+#define IFX_HSSL_ACCEN0_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN4 */
+#define IFX_HSSL_ACCEN0_EN4_OFF (4u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN5 */
+#define IFX_HSSL_ACCEN0_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN5 */
+#define IFX_HSSL_ACCEN0_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN5 */
+#define IFX_HSSL_ACCEN0_EN5_OFF (5u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN6 */
+#define IFX_HSSL_ACCEN0_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN6 */
+#define IFX_HSSL_ACCEN0_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN6 */
+#define IFX_HSSL_ACCEN0_EN6_OFF (6u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN7 */
+#define IFX_HSSL_ACCEN0_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN7 */
+#define IFX_HSSL_ACCEN0_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN7 */
+#define IFX_HSSL_ACCEN0_EN7_OFF (7u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN8 */
+#define IFX_HSSL_ACCEN0_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN8 */
+#define IFX_HSSL_ACCEN0_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN8 */
+#define IFX_HSSL_ACCEN0_EN8_OFF (8u)
+
+/** \brief Length for Ifx_HSSL_ACCEN0_Bits.EN9 */
+#define IFX_HSSL_ACCEN0_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_ACCEN0_Bits.EN9 */
+#define IFX_HSSL_ACCEN0_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_ACCEN0_Bits.EN9 */
+#define IFX_HSSL_ACCEN0_EN9_OFF (9u)
+
+/** \brief Length for Ifx_HSSL_AR_Bits.ARW0 */
+#define IFX_HSSL_AR_ARW0_LEN (2u)
+
+/** \brief Mask for Ifx_HSSL_AR_Bits.ARW0 */
+#define IFX_HSSL_AR_ARW0_MSK (0x3u)
+
+/** \brief Offset for Ifx_HSSL_AR_Bits.ARW0 */
+#define IFX_HSSL_AR_ARW0_OFF (0u)
+
+/** \brief Length for Ifx_HSSL_AR_Bits.ARW1 */
+#define IFX_HSSL_AR_ARW1_LEN (2u)
+
+/** \brief Mask for Ifx_HSSL_AR_Bits.ARW1 */
+#define IFX_HSSL_AR_ARW1_MSK (0x3u)
+
+/** \brief Offset for Ifx_HSSL_AR_Bits.ARW1 */
+#define IFX_HSSL_AR_ARW1_OFF (2u)
+
+/** \brief Length for Ifx_HSSL_AR_Bits.ARW2 */
+#define IFX_HSSL_AR_ARW2_LEN (2u)
+
+/** \brief Mask for Ifx_HSSL_AR_Bits.ARW2 */
+#define IFX_HSSL_AR_ARW2_MSK (0x3u)
+
+/** \brief Offset for Ifx_HSSL_AR_Bits.ARW2 */
+#define IFX_HSSL_AR_ARW2_OFF (4u)
+
+/** \brief Length for Ifx_HSSL_AR_Bits.ARW3 */
+#define IFX_HSSL_AR_ARW3_LEN (2u)
+
+/** \brief Mask for Ifx_HSSL_AR_Bits.ARW3 */
+#define IFX_HSSL_AR_ARW3_MSK (0x3u)
+
+/** \brief Offset for Ifx_HSSL_AR_Bits.ARW3 */
+#define IFX_HSSL_AR_ARW3_OFF (6u)
+
+/** \brief Length for Ifx_HSSL_AR_Bits.MAVCH */
+#define IFX_HSSL_AR_MAVCH_LEN (2u)
+
+/** \brief Mask for Ifx_HSSL_AR_Bits.MAVCH */
+#define IFX_HSSL_AR_MAVCH_MSK (0x3u)
+
+/** \brief Offset for Ifx_HSSL_AR_Bits.MAVCH */
+#define IFX_HSSL_AR_MAVCH_OFF (16u)
+
+/** \brief Length for Ifx_HSSL_AW_AWEND_Bits.AWE */
+#define IFX_HSSL_AW_AWEND_AWE_LEN (24u)
+
+/** \brief Mask for Ifx_HSSL_AW_AWEND_Bits.AWE */
+#define IFX_HSSL_AW_AWEND_AWE_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_HSSL_AW_AWEND_Bits.AWE */
+#define IFX_HSSL_AW_AWEND_AWE_OFF (8u)
+
+/** \brief Length for Ifx_HSSL_AW_AWSTART_Bits.AWS */
+#define IFX_HSSL_AW_AWSTART_AWS_LEN (24u)
+
+/** \brief Mask for Ifx_HSSL_AW_AWSTART_Bits.AWS */
+#define IFX_HSSL_AW_AWSTART_AWS_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_HSSL_AW_AWSTART_Bits.AWS */
+#define IFX_HSSL_AW_AWSTART_AWS_OFF (8u)
+
+/** \brief Length for Ifx_HSSL_CFG_Bits.CCC */
+#define IFX_HSSL_CFG_CCC_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_CFG_Bits.CCC */
+#define IFX_HSSL_CFG_CCC_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_CFG_Bits.CCC */
+#define IFX_HSSL_CFG_CCC_OFF (19u)
+
+/** \brief Length for Ifx_HSSL_CFG_Bits.PREDIV */
+#define IFX_HSSL_CFG_PREDIV_LEN (14u)
+
+/** \brief Mask for Ifx_HSSL_CFG_Bits.PREDIV */
+#define IFX_HSSL_CFG_PREDIV_MSK (0x3fffu)
+
+/** \brief Offset for Ifx_HSSL_CFG_Bits.PREDIV */
+#define IFX_HSSL_CFG_PREDIV_OFF (0u)
+
+/** \brief Length for Ifx_HSSL_CFG_Bits.SCM */
+#define IFX_HSSL_CFG_SCM_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_CFG_Bits.SCM */
+#define IFX_HSSL_CFG_SCM_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_CFG_Bits.SCM */
+#define IFX_HSSL_CFG_SCM_OFF (18u)
+
+/** \brief Length for Ifx_HSSL_CFG_Bits.SMR */
+#define IFX_HSSL_CFG_SMR_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_CFG_Bits.SMR */
+#define IFX_HSSL_CFG_SMR_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_CFG_Bits.SMR */
+#define IFX_HSSL_CFG_SMR_OFF (17u)
+
+/** \brief Length for Ifx_HSSL_CFG_Bits.SMT */
+#define IFX_HSSL_CFG_SMT_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_CFG_Bits.SMT */
+#define IFX_HSSL_CFG_SMT_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_CFG_Bits.SMT */
+#define IFX_HSSL_CFG_SMT_OFF (16u)
+
+/** \brief Length for Ifx_HSSL_CLC_Bits.DISR */
+#define IFX_HSSL_CLC_DISR_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_CLC_Bits.DISR */
+#define IFX_HSSL_CLC_DISR_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_CLC_Bits.DISR */
+#define IFX_HSSL_CLC_DISR_OFF (0u)
+
+/** \brief Length for Ifx_HSSL_CLC_Bits.DISS */
+#define IFX_HSSL_CLC_DISS_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_CLC_Bits.DISS */
+#define IFX_HSSL_CLC_DISS_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_CLC_Bits.DISS */
+#define IFX_HSSL_CLC_DISS_OFF (1u)
+
+/** \brief Length for Ifx_HSSL_CLC_Bits.EDIS */
+#define IFX_HSSL_CLC_EDIS_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_CLC_Bits.EDIS */
+#define IFX_HSSL_CLC_EDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_CLC_Bits.EDIS */
+#define IFX_HSSL_CLC_EDIS_OFF (3u)
+
+/** \brief Length for Ifx_HSSL_CRC_Bits.XEN */
+#define IFX_HSSL_CRC_XEN_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_CRC_Bits.XEN */
+#define IFX_HSSL_CRC_XEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_CRC_Bits.XEN */
+#define IFX_HSSL_CRC_XEN_OFF (16u)
+
+/** \brief Length for Ifx_HSSL_CRC_Bits.XORMASK */
+#define IFX_HSSL_CRC_XORMASK_LEN (16u)
+
+/** \brief Mask for Ifx_HSSL_CRC_Bits.XORMASK */
+#define IFX_HSSL_CRC_XORMASK_MSK (0xffffu)
+
+/** \brief Offset for Ifx_HSSL_CRC_Bits.XORMASK */
+#define IFX_HSSL_CRC_XORMASK_OFF (0u)
+
+/** \brief Length for Ifx_HSSL_I_ICON_Bits.BSY */
+#define IFX_HSSL_I_ICON_BSY_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_I_ICON_Bits.BSY */
+#define IFX_HSSL_I_ICON_BSY_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_I_ICON_Bits.BSY */
+#define IFX_HSSL_I_ICON_BSY_OFF (20u)
+
+/** \brief Length for Ifx_HSSL_I_ICON_Bits.CETT */
+#define IFX_HSSL_I_ICON_CETT_LEN (3u)
+
+/** \brief Mask for Ifx_HSSL_I_ICON_Bits.CETT */
+#define IFX_HSSL_I_ICON_CETT_MSK (0x7u)
+
+/** \brief Offset for Ifx_HSSL_I_ICON_Bits.CETT */
+#define IFX_HSSL_I_ICON_CETT_OFF (5u)
+
+/** \brief Length for Ifx_HSSL_I_ICON_Bits.DATLEN */
+#define IFX_HSSL_I_ICON_DATLEN_LEN (2u)
+
+/** \brief Mask for Ifx_HSSL_I_ICON_Bits.DATLEN */
+#define IFX_HSSL_I_ICON_DATLEN_MSK (0x3u)
+
+/** \brief Offset for Ifx_HSSL_I_ICON_Bits.DATLEN */
+#define IFX_HSSL_I_ICON_DATLEN_OFF (16u)
+
+/** \brief Length for Ifx_HSSL_I_ICON_Bits.IDQ */
+#define IFX_HSSL_I_ICON_IDQ_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_I_ICON_Bits.IDQ */
+#define IFX_HSSL_I_ICON_IDQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_I_ICON_Bits.IDQ */
+#define IFX_HSSL_I_ICON_IDQ_OFF (0u)
+
+/** \brief Length for Ifx_HSSL_I_ICON_Bits.ITTAG */
+#define IFX_HSSL_I_ICON_ITTAG_LEN (3u)
+
+/** \brief Mask for Ifx_HSSL_I_ICON_Bits.ITTAG */
+#define IFX_HSSL_I_ICON_ITTAG_MSK (0x7u)
+
+/** \brief Offset for Ifx_HSSL_I_ICON_Bits.ITTAG */
+#define IFX_HSSL_I_ICON_ITTAG_OFF (21u)
+
+/** \brief Length for Ifx_HSSL_I_ICON_Bits.LETT */
+#define IFX_HSSL_I_ICON_LETT_LEN (3u)
+
+/** \brief Mask for Ifx_HSSL_I_ICON_Bits.LETT */
+#define IFX_HSSL_I_ICON_LETT_MSK (0x7u)
+
+/** \brief Offset for Ifx_HSSL_I_ICON_Bits.LETT */
+#define IFX_HSSL_I_ICON_LETT_OFF (2u)
+
+/** \brief Length for Ifx_HSSL_I_ICON_Bits.RWT */
+#define IFX_HSSL_I_ICON_RWT_LEN (2u)
+
+/** \brief Mask for Ifx_HSSL_I_ICON_Bits.RWT */
+#define IFX_HSSL_I_ICON_RWT_MSK (0x3u)
+
+/** \brief Offset for Ifx_HSSL_I_ICON_Bits.RWT */
+#define IFX_HSSL_I_ICON_RWT_OFF (18u)
+
+/** \brief Length for Ifx_HSSL_I_ICON_Bits.TOCV */
+#define IFX_HSSL_I_ICON_TOCV_LEN (8u)
+
+/** \brief Mask for Ifx_HSSL_I_ICON_Bits.TOCV */
+#define IFX_HSSL_I_ICON_TOCV_MSK (0xffu)
+
+/** \brief Offset for Ifx_HSSL_I_ICON_Bits.TOCV */
+#define IFX_HSSL_I_ICON_TOCV_OFF (8u)
+
+/** \brief Length for Ifx_HSSL_I_ICON_Bits.TOREL */
+#define IFX_HSSL_I_ICON_TOREL_LEN (8u)
+
+/** \brief Mask for Ifx_HSSL_I_ICON_Bits.TOREL */
+#define IFX_HSSL_I_ICON_TOREL_MSK (0xffu)
+
+/** \brief Offset for Ifx_HSSL_I_ICON_Bits.TOREL */
+#define IFX_HSSL_I_ICON_TOREL_OFF (24u)
+
+/** \brief Length for Ifx_HSSL_I_ICON_Bits.TQ */
+#define IFX_HSSL_I_ICON_TQ_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_I_ICON_Bits.TQ */
+#define IFX_HSSL_I_ICON_TQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_I_ICON_Bits.TQ */
+#define IFX_HSSL_I_ICON_TQ_OFF (1u)
+
+/** \brief Length for Ifx_HSSL_I_IRD_Bits.DATA */
+#define IFX_HSSL_I_IRD_DATA_LEN (32u)
+
+/** \brief Mask for Ifx_HSSL_I_IRD_Bits.DATA */
+#define IFX_HSSL_I_IRD_DATA_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_HSSL_I_IRD_Bits.DATA */
+#define IFX_HSSL_I_IRD_DATA_OFF (0u)
+
+/** \brief Length for Ifx_HSSL_I_IRWA_Bits.ADDRESS */
+#define IFX_HSSL_I_IRWA_ADDRESS_LEN (32u)
+
+/** \brief Mask for Ifx_HSSL_I_IRWA_Bits.ADDRESS */
+#define IFX_HSSL_I_IRWA_ADDRESS_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_HSSL_I_IRWA_Bits.ADDRESS */
+#define IFX_HSSL_I_IRWA_ADDRESS_OFF (0u)
+
+/** \brief Length for Ifx_HSSL_I_IWD_Bits.DATA */
+#define IFX_HSSL_I_IWD_DATA_LEN (32u)
+
+/** \brief Mask for Ifx_HSSL_I_IWD_Bits.DATA */
+#define IFX_HSSL_I_IWD_DATA_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_HSSL_I_IWD_Bits.DATA */
+#define IFX_HSSL_I_IWD_DATA_OFF (0u)
+
+/** \brief Length for Ifx_HSSL_ID_Bits.MODNUMBER */
+#define IFX_HSSL_ID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_HSSL_ID_Bits.MODNUMBER */
+#define IFX_HSSL_ID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_HSSL_ID_Bits.MODNUMBER */
+#define IFX_HSSL_ID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_HSSL_ID_Bits.MODREV */
+#define IFX_HSSL_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_HSSL_ID_Bits.MODREV */
+#define IFX_HSSL_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_HSSL_ID_Bits.MODREV */
+#define IFX_HSSL_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_HSSL_ID_Bits.MODTYPE */
+#define IFX_HSSL_ID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_HSSL_ID_Bits.MODTYPE */
+#define IFX_HSSL_ID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_HSSL_ID_Bits.MODTYPE */
+#define IFX_HSSL_ID_MODTYPE_OFF (8u)
+
+/** \brief Length for Ifx_HSSL_IS_CA_Bits.CURR */
+#define IFX_HSSL_IS_CA_CURR_LEN (27u)
+
+/** \brief Mask for Ifx_HSSL_IS_CA_Bits.CURR */
+#define IFX_HSSL_IS_CA_CURR_MSK (0x7ffffffu)
+
+/** \brief Offset for Ifx_HSSL_IS_CA_Bits.CURR */
+#define IFX_HSSL_IS_CA_CURR_OFF (5u)
+
+/** \brief Length for Ifx_HSSL_IS_FC_Bits.CURCOUNT */
+#define IFX_HSSL_IS_FC_CURCOUNT_LEN (16u)
+
+/** \brief Mask for Ifx_HSSL_IS_FC_Bits.CURCOUNT */
+#define IFX_HSSL_IS_FC_CURCOUNT_MSK (0xffffu)
+
+/** \brief Offset for Ifx_HSSL_IS_FC_Bits.CURCOUNT */
+#define IFX_HSSL_IS_FC_CURCOUNT_OFF (16u)
+
+/** \brief Length for Ifx_HSSL_IS_FC_Bits.RELCOUNT */
+#define IFX_HSSL_IS_FC_RELCOUNT_LEN (16u)
+
+/** \brief Mask for Ifx_HSSL_IS_FC_Bits.RELCOUNT */
+#define IFX_HSSL_IS_FC_RELCOUNT_MSK (0xffffu)
+
+/** \brief Offset for Ifx_HSSL_IS_FC_Bits.RELCOUNT */
+#define IFX_HSSL_IS_FC_RELCOUNT_OFF (0u)
+
+/** \brief Length for Ifx_HSSL_ISSA_Bits.START */
+#define IFX_HSSL_ISSA_START_LEN (27u)
+
+/** \brief Mask for Ifx_HSSL_ISSA_Bits.START */
+#define IFX_HSSL_ISSA_START_MSK (0x7ffffffu)
+
+/** \brief Offset for Ifx_HSSL_ISSA_Bits.START */
+#define IFX_HSSL_ISSA_START_OFF (5u)
+
+/** \brief Length for Ifx_HSSL_KRST0_Bits.RST */
+#define IFX_HSSL_KRST0_RST_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_KRST0_Bits.RST */
+#define IFX_HSSL_KRST0_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_KRST0_Bits.RST */
+#define IFX_HSSL_KRST0_RST_OFF (0u)
+
+/** \brief Length for Ifx_HSSL_KRST0_Bits.RSTSTAT */
+#define IFX_HSSL_KRST0_RSTSTAT_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_KRST0_Bits.RSTSTAT */
+#define IFX_HSSL_KRST0_RSTSTAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_KRST0_Bits.RSTSTAT */
+#define IFX_HSSL_KRST0_RSTSTAT_OFF (1u)
+
+/** \brief Length for Ifx_HSSL_KRST1_Bits.RST */
+#define IFX_HSSL_KRST1_RST_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_KRST1_Bits.RST */
+#define IFX_HSSL_KRST1_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_KRST1_Bits.RST */
+#define IFX_HSSL_KRST1_RST_OFF (0u)
+
+/** \brief Length for Ifx_HSSL_KRSTCLR_Bits.CLR */
+#define IFX_HSSL_KRSTCLR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_KRSTCLR_Bits.CLR */
+#define IFX_HSSL_KRSTCLR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_KRSTCLR_Bits.CLR */
+#define IFX_HSSL_KRSTCLR_CLR_OFF (0u)
+
+/** \brief Length for Ifx_HSSL_MFLAGS_Bits.CRCE */
+#define IFX_HSSL_MFLAGS_CRCE_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGS_Bits.CRCE */
+#define IFX_HSSL_MFLAGS_CRCE_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGS_Bits.CRCE */
+#define IFX_HSSL_MFLAGS_CRCE_OFF (25u)
+
+/** \brief Length for Ifx_HSSL_MFLAGS_Bits.IMB */
+#define IFX_HSSL_MFLAGS_IMB_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGS_Bits.IMB */
+#define IFX_HSSL_MFLAGS_IMB_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGS_Bits.IMB */
+#define IFX_HSSL_MFLAGS_IMB_OFF (19u)
+
+/** \brief Length for Ifx_HSSL_MFLAGS_Bits.INI */
+#define IFX_HSSL_MFLAGS_INI_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGS_Bits.INI */
+#define IFX_HSSL_MFLAGS_INI_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGS_Bits.INI */
+#define IFX_HSSL_MFLAGS_INI_OFF (31u)
+
+/** \brief Length for Ifx_HSSL_MFLAGS_Bits.ISB */
+#define IFX_HSSL_MFLAGS_ISB_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGS_Bits.ISB */
+#define IFX_HSSL_MFLAGS_ISB_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGS_Bits.ISB */
+#define IFX_HSSL_MFLAGS_ISB_OFF (20u)
+
+/** \brief Length for Ifx_HSSL_MFLAGS_Bits.MAV */
+#define IFX_HSSL_MFLAGS_MAV_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGS_Bits.MAV */
+#define IFX_HSSL_MFLAGS_MAV_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGS_Bits.MAV */
+#define IFX_HSSL_MFLAGS_MAV_OFF (21u)
+
+/** \brief Length for Ifx_HSSL_MFLAGS_Bits.NACK */
+#define IFX_HSSL_MFLAGS_NACK_LEN (4u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGS_Bits.NACK */
+#define IFX_HSSL_MFLAGS_NACK_MSK (0xfu)
+
+/** \brief Offset for Ifx_HSSL_MFLAGS_Bits.NACK */
+#define IFX_HSSL_MFLAGS_NACK_OFF (0u)
+
+/** \brief Length for Ifx_HSSL_MFLAGS_Bits.PIE1 */
+#define IFX_HSSL_MFLAGS_PIE1_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGS_Bits.PIE1 */
+#define IFX_HSSL_MFLAGS_PIE1_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGS_Bits.PIE1 */
+#define IFX_HSSL_MFLAGS_PIE1_OFF (23u)
+
+/** \brief Length for Ifx_HSSL_MFLAGS_Bits.PIE2 */
+#define IFX_HSSL_MFLAGS_PIE2_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGS_Bits.PIE2 */
+#define IFX_HSSL_MFLAGS_PIE2_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGS_Bits.PIE2 */
+#define IFX_HSSL_MFLAGS_PIE2_OFF (24u)
+
+/** \brief Length for Ifx_HSSL_MFLAGS_Bits.SRIE */
+#define IFX_HSSL_MFLAGS_SRIE_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGS_Bits.SRIE */
+#define IFX_HSSL_MFLAGS_SRIE_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGS_Bits.SRIE */
+#define IFX_HSSL_MFLAGS_SRIE_OFF (22u)
+
+/** \brief Length for Ifx_HSSL_MFLAGS_Bits.TEI */
+#define IFX_HSSL_MFLAGS_TEI_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGS_Bits.TEI */
+#define IFX_HSSL_MFLAGS_TEI_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGS_Bits.TEI */
+#define IFX_HSSL_MFLAGS_TEI_OFF (29u)
+
+/** \brief Length for Ifx_HSSL_MFLAGS_Bits.TEO */
+#define IFX_HSSL_MFLAGS_TEO_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGS_Bits.TEO */
+#define IFX_HSSL_MFLAGS_TEO_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGS_Bits.TEO */
+#define IFX_HSSL_MFLAGS_TEO_OFF (30u)
+
+/** \brief Length for Ifx_HSSL_MFLAGS_Bits.TIMEOUT */
+#define IFX_HSSL_MFLAGS_TIMEOUT_LEN (4u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGS_Bits.TIMEOUT */
+#define IFX_HSSL_MFLAGS_TIMEOUT_MSK (0xfu)
+
+/** \brief Offset for Ifx_HSSL_MFLAGS_Bits.TIMEOUT */
+#define IFX_HSSL_MFLAGS_TIMEOUT_OFF (8u)
+
+/** \brief Length for Ifx_HSSL_MFLAGS_Bits.TMB */
+#define IFX_HSSL_MFLAGS_TMB_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGS_Bits.TMB */
+#define IFX_HSSL_MFLAGS_TMB_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGS_Bits.TMB */
+#define IFX_HSSL_MFLAGS_TMB_OFF (18u)
+
+/** \brief Length for Ifx_HSSL_MFLAGS_Bits.TSE */
+#define IFX_HSSL_MFLAGS_TSE_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGS_Bits.TSE */
+#define IFX_HSSL_MFLAGS_TSE_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGS_Bits.TSE */
+#define IFX_HSSL_MFLAGS_TSE_OFF (28u)
+
+/** \brief Length for Ifx_HSSL_MFLAGS_Bits.TTE */
+#define IFX_HSSL_MFLAGS_TTE_LEN (4u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGS_Bits.TTE */
+#define IFX_HSSL_MFLAGS_TTE_MSK (0xfu)
+
+/** \brief Offset for Ifx_HSSL_MFLAGS_Bits.TTE */
+#define IFX_HSSL_MFLAGS_TTE_OFF (4u)
+
+/** \brief Length for Ifx_HSSL_MFLAGS_Bits.UNEXPECTED */
+#define IFX_HSSL_MFLAGS_UNEXPECTED_LEN (4u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGS_Bits.UNEXPECTED */
+#define IFX_HSSL_MFLAGS_UNEXPECTED_MSK (0xfu)
+
+/** \brief Offset for Ifx_HSSL_MFLAGS_Bits.UNEXPECTED */
+#define IFX_HSSL_MFLAGS_UNEXPECTED_OFF (12u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSCL_Bits.CRCEC */
+#define IFX_HSSL_MFLAGSCL_CRCEC_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSCL_Bits.CRCEC */
+#define IFX_HSSL_MFLAGSCL_CRCEC_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSCL_Bits.CRCEC */
+#define IFX_HSSL_MFLAGSCL_CRCEC_OFF (25u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSCL_Bits.IMBC */
+#define IFX_HSSL_MFLAGSCL_IMBC_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSCL_Bits.IMBC */
+#define IFX_HSSL_MFLAGSCL_IMBC_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSCL_Bits.IMBC */
+#define IFX_HSSL_MFLAGSCL_IMBC_OFF (19u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSCL_Bits.INIC */
+#define IFX_HSSL_MFLAGSCL_INIC_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSCL_Bits.INIC */
+#define IFX_HSSL_MFLAGSCL_INIC_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSCL_Bits.INIC */
+#define IFX_HSSL_MFLAGSCL_INIC_OFF (31u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSCL_Bits.ISBC */
+#define IFX_HSSL_MFLAGSCL_ISBC_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSCL_Bits.ISBC */
+#define IFX_HSSL_MFLAGSCL_ISBC_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSCL_Bits.ISBC */
+#define IFX_HSSL_MFLAGSCL_ISBC_OFF (20u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSCL_Bits.MAVC */
+#define IFX_HSSL_MFLAGSCL_MAVC_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSCL_Bits.MAVC */
+#define IFX_HSSL_MFLAGSCL_MAVC_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSCL_Bits.MAVC */
+#define IFX_HSSL_MFLAGSCL_MAVC_OFF (21u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSCL_Bits.NACKC */
+#define IFX_HSSL_MFLAGSCL_NACKC_LEN (4u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSCL_Bits.NACKC */
+#define IFX_HSSL_MFLAGSCL_NACKC_MSK (0xfu)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSCL_Bits.NACKC */
+#define IFX_HSSL_MFLAGSCL_NACKC_OFF (0u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSCL_Bits.PIE1C */
+#define IFX_HSSL_MFLAGSCL_PIE1C_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSCL_Bits.PIE1C */
+#define IFX_HSSL_MFLAGSCL_PIE1C_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSCL_Bits.PIE1C */
+#define IFX_HSSL_MFLAGSCL_PIE1C_OFF (23u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSCL_Bits.PIE2C */
+#define IFX_HSSL_MFLAGSCL_PIE2C_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSCL_Bits.PIE2C */
+#define IFX_HSSL_MFLAGSCL_PIE2C_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSCL_Bits.PIE2C */
+#define IFX_HSSL_MFLAGSCL_PIE2C_OFF (24u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSCL_Bits.SRIEC */
+#define IFX_HSSL_MFLAGSCL_SRIEC_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSCL_Bits.SRIEC */
+#define IFX_HSSL_MFLAGSCL_SRIEC_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSCL_Bits.SRIEC */
+#define IFX_HSSL_MFLAGSCL_SRIEC_OFF (22u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSCL_Bits.TEOC */
+#define IFX_HSSL_MFLAGSCL_TEOC_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSCL_Bits.TEOC */
+#define IFX_HSSL_MFLAGSCL_TEOC_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSCL_Bits.TEOC */
+#define IFX_HSSL_MFLAGSCL_TEOC_OFF (30u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSCL_Bits.TIMEOUTC */
+#define IFX_HSSL_MFLAGSCL_TIMEOUTC_LEN (4u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSCL_Bits.TIMEOUTC */
+#define IFX_HSSL_MFLAGSCL_TIMEOUTC_MSK (0xfu)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSCL_Bits.TIMEOUTC */
+#define IFX_HSSL_MFLAGSCL_TIMEOUTC_OFF (8u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSCL_Bits.TMBC */
+#define IFX_HSSL_MFLAGSCL_TMBC_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSCL_Bits.TMBC */
+#define IFX_HSSL_MFLAGSCL_TMBC_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSCL_Bits.TMBC */
+#define IFX_HSSL_MFLAGSCL_TMBC_OFF (18u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSCL_Bits.TSEC */
+#define IFX_HSSL_MFLAGSCL_TSEC_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSCL_Bits.TSEC */
+#define IFX_HSSL_MFLAGSCL_TSEC_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSCL_Bits.TSEC */
+#define IFX_HSSL_MFLAGSCL_TSEC_OFF (28u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSCL_Bits.TTEC */
+#define IFX_HSSL_MFLAGSCL_TTEC_LEN (4u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSCL_Bits.TTEC */
+#define IFX_HSSL_MFLAGSCL_TTEC_MSK (0xfu)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSCL_Bits.TTEC */
+#define IFX_HSSL_MFLAGSCL_TTEC_OFF (4u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSCL_Bits.UNEXPECTEDC */
+#define IFX_HSSL_MFLAGSCL_UNEXPECTEDC_LEN (4u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSCL_Bits.UNEXPECTEDC */
+#define IFX_HSSL_MFLAGSCL_UNEXPECTEDC_MSK (0xfu)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSCL_Bits.UNEXPECTEDC */
+#define IFX_HSSL_MFLAGSCL_UNEXPECTEDC_OFF (12u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSEN_Bits.CRCEEN */
+#define IFX_HSSL_MFLAGSEN_CRCEEN_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSEN_Bits.CRCEEN */
+#define IFX_HSSL_MFLAGSEN_CRCEEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSEN_Bits.CRCEEN */
+#define IFX_HSSL_MFLAGSEN_CRCEEN_OFF (25u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSEN_Bits.MAVEN */
+#define IFX_HSSL_MFLAGSEN_MAVEN_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSEN_Bits.MAVEN */
+#define IFX_HSSL_MFLAGSEN_MAVEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSEN_Bits.MAVEN */
+#define IFX_HSSL_MFLAGSEN_MAVEN_OFF (21u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSEN_Bits.NACKEN */
+#define IFX_HSSL_MFLAGSEN_NACKEN_LEN (4u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSEN_Bits.NACKEN */
+#define IFX_HSSL_MFLAGSEN_NACKEN_MSK (0xfu)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSEN_Bits.NACKEN */
+#define IFX_HSSL_MFLAGSEN_NACKEN_OFF (0u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSEN_Bits.PIE1EN */
+#define IFX_HSSL_MFLAGSEN_PIE1EN_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSEN_Bits.PIE1EN */
+#define IFX_HSSL_MFLAGSEN_PIE1EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSEN_Bits.PIE1EN */
+#define IFX_HSSL_MFLAGSEN_PIE1EN_OFF (23u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSEN_Bits.PIE2EN */
+#define IFX_HSSL_MFLAGSEN_PIE2EN_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSEN_Bits.PIE2EN */
+#define IFX_HSSL_MFLAGSEN_PIE2EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSEN_Bits.PIE2EN */
+#define IFX_HSSL_MFLAGSEN_PIE2EN_OFF (24u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSEN_Bits.SRIEEN */
+#define IFX_HSSL_MFLAGSEN_SRIEEN_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSEN_Bits.SRIEEN */
+#define IFX_HSSL_MFLAGSEN_SRIEEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSEN_Bits.SRIEEN */
+#define IFX_HSSL_MFLAGSEN_SRIEEN_OFF (22u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSEN_Bits.TEIEN */
+#define IFX_HSSL_MFLAGSEN_TEIEN_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSEN_Bits.TEIEN */
+#define IFX_HSSL_MFLAGSEN_TEIEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSEN_Bits.TEIEN */
+#define IFX_HSSL_MFLAGSEN_TEIEN_OFF (29u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSEN_Bits.TIMEOUTEN */
+#define IFX_HSSL_MFLAGSEN_TIMEOUTEN_LEN (4u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSEN_Bits.TIMEOUTEN */
+#define IFX_HSSL_MFLAGSEN_TIMEOUTEN_MSK (0xfu)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSEN_Bits.TIMEOUTEN */
+#define IFX_HSSL_MFLAGSEN_TIMEOUTEN_OFF (8u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSEN_Bits.TTEEN */
+#define IFX_HSSL_MFLAGSEN_TTEEN_LEN (4u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSEN_Bits.TTEEN */
+#define IFX_HSSL_MFLAGSEN_TTEEN_MSK (0xfu)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSEN_Bits.TTEEN */
+#define IFX_HSSL_MFLAGSEN_TTEEN_OFF (4u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSEN_Bits.UNEXPECTEDEN */
+#define IFX_HSSL_MFLAGSEN_UNEXPECTEDEN_LEN (4u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSEN_Bits.UNEXPECTEDEN */
+#define IFX_HSSL_MFLAGSEN_UNEXPECTEDEN_MSK (0xfu)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSEN_Bits.UNEXPECTEDEN */
+#define IFX_HSSL_MFLAGSEN_UNEXPECTEDEN_OFF (12u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSSET_Bits.CRCES */
+#define IFX_HSSL_MFLAGSSET_CRCES_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSSET_Bits.CRCES */
+#define IFX_HSSL_MFLAGSSET_CRCES_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSSET_Bits.CRCES */
+#define IFX_HSSL_MFLAGSSET_CRCES_OFF (25u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSSET_Bits.IMBS */
+#define IFX_HSSL_MFLAGSSET_IMBS_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSSET_Bits.IMBS */
+#define IFX_HSSL_MFLAGSSET_IMBS_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSSET_Bits.IMBS */
+#define IFX_HSSL_MFLAGSSET_IMBS_OFF (19u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSSET_Bits.INIS */
+#define IFX_HSSL_MFLAGSSET_INIS_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSSET_Bits.INIS */
+#define IFX_HSSL_MFLAGSSET_INIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSSET_Bits.INIS */
+#define IFX_HSSL_MFLAGSSET_INIS_OFF (31u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSSET_Bits.ISBS */
+#define IFX_HSSL_MFLAGSSET_ISBS_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSSET_Bits.ISBS */
+#define IFX_HSSL_MFLAGSSET_ISBS_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSSET_Bits.ISBS */
+#define IFX_HSSL_MFLAGSSET_ISBS_OFF (20u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSSET_Bits.MAVS */
+#define IFX_HSSL_MFLAGSSET_MAVS_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSSET_Bits.MAVS */
+#define IFX_HSSL_MFLAGSSET_MAVS_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSSET_Bits.MAVS */
+#define IFX_HSSL_MFLAGSSET_MAVS_OFF (21u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSSET_Bits.NACKS */
+#define IFX_HSSL_MFLAGSSET_NACKS_LEN (4u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSSET_Bits.NACKS */
+#define IFX_HSSL_MFLAGSSET_NACKS_MSK (0xfu)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSSET_Bits.NACKS */
+#define IFX_HSSL_MFLAGSSET_NACKS_OFF (0u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSSET_Bits.PIE1S */
+#define IFX_HSSL_MFLAGSSET_PIE1S_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSSET_Bits.PIE1S */
+#define IFX_HSSL_MFLAGSSET_PIE1S_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSSET_Bits.PIE1S */
+#define IFX_HSSL_MFLAGSSET_PIE1S_OFF (23u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSSET_Bits.PIE2S */
+#define IFX_HSSL_MFLAGSSET_PIE2S_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSSET_Bits.PIE2S */
+#define IFX_HSSL_MFLAGSSET_PIE2S_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSSET_Bits.PIE2S */
+#define IFX_HSSL_MFLAGSSET_PIE2S_OFF (24u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSSET_Bits.SRIES */
+#define IFX_HSSL_MFLAGSSET_SRIES_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSSET_Bits.SRIES */
+#define IFX_HSSL_MFLAGSSET_SRIES_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSSET_Bits.SRIES */
+#define IFX_HSSL_MFLAGSSET_SRIES_OFF (22u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSSET_Bits.TEOS */
+#define IFX_HSSL_MFLAGSSET_TEOS_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSSET_Bits.TEOS */
+#define IFX_HSSL_MFLAGSSET_TEOS_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSSET_Bits.TEOS */
+#define IFX_HSSL_MFLAGSSET_TEOS_OFF (30u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSSET_Bits.TIMEOUTS */
+#define IFX_HSSL_MFLAGSSET_TIMEOUTS_LEN (4u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSSET_Bits.TIMEOUTS */
+#define IFX_HSSL_MFLAGSSET_TIMEOUTS_MSK (0xfu)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSSET_Bits.TIMEOUTS */
+#define IFX_HSSL_MFLAGSSET_TIMEOUTS_OFF (8u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSSET_Bits.TMBS */
+#define IFX_HSSL_MFLAGSSET_TMBS_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSSET_Bits.TMBS */
+#define IFX_HSSL_MFLAGSSET_TMBS_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSSET_Bits.TMBS */
+#define IFX_HSSL_MFLAGSSET_TMBS_OFF (18u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSSET_Bits.TSES */
+#define IFX_HSSL_MFLAGSSET_TSES_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSSET_Bits.TSES */
+#define IFX_HSSL_MFLAGSSET_TSES_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSSET_Bits.TSES */
+#define IFX_HSSL_MFLAGSSET_TSES_OFF (28u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSSET_Bits.TTES */
+#define IFX_HSSL_MFLAGSSET_TTES_LEN (4u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSSET_Bits.TTES */
+#define IFX_HSSL_MFLAGSSET_TTES_MSK (0xfu)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSSET_Bits.TTES */
+#define IFX_HSSL_MFLAGSSET_TTES_OFF (4u)
+
+/** \brief Length for Ifx_HSSL_MFLAGSSET_Bits.UNEXPECTEDS */
+#define IFX_HSSL_MFLAGSSET_UNEXPECTEDS_LEN (4u)
+
+/** \brief Mask for Ifx_HSSL_MFLAGSSET_Bits.UNEXPECTEDS */
+#define IFX_HSSL_MFLAGSSET_UNEXPECTEDS_MSK (0xfu)
+
+/** \brief Offset for Ifx_HSSL_MFLAGSSET_Bits.UNEXPECTEDS */
+#define IFX_HSSL_MFLAGSSET_UNEXPECTEDS_OFF (12u)
+
+/** \brief Length for Ifx_HSSL_OCS_Bits.SUS */
+#define IFX_HSSL_OCS_SUS_LEN (4u)
+
+/** \brief Mask for Ifx_HSSL_OCS_Bits.SUS */
+#define IFX_HSSL_OCS_SUS_MSK (0xfu)
+
+/** \brief Offset for Ifx_HSSL_OCS_Bits.SUS */
+#define IFX_HSSL_OCS_SUS_OFF (24u)
+
+/** \brief Length for Ifx_HSSL_OCS_Bits.SUS_P */
+#define IFX_HSSL_OCS_SUS_P_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_OCS_Bits.SUS_P */
+#define IFX_HSSL_OCS_SUS_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_OCS_Bits.SUS_P */
+#define IFX_HSSL_OCS_SUS_P_OFF (28u)
+
+/** \brief Length for Ifx_HSSL_OCS_Bits.SUSSTA */
+#define IFX_HSSL_OCS_SUSSTA_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_OCS_Bits.SUSSTA */
+#define IFX_HSSL_OCS_SUSSTA_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_OCS_Bits.SUSSTA */
+#define IFX_HSSL_OCS_SUSSTA_OFF (29u)
+
+/** \brief Length for Ifx_HSSL_OCS_Bits.TG_P */
+#define IFX_HSSL_OCS_TG_P_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_OCS_Bits.TG_P */
+#define IFX_HSSL_OCS_TG_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_OCS_Bits.TG_P */
+#define IFX_HSSL_OCS_TG_P_OFF (3u)
+
+/** \brief Length for Ifx_HSSL_OCS_Bits.TGB */
+#define IFX_HSSL_OCS_TGB_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_OCS_Bits.TGB */
+#define IFX_HSSL_OCS_TGB_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_OCS_Bits.TGB */
+#define IFX_HSSL_OCS_TGB_OFF (2u)
+
+/** \brief Length for Ifx_HSSL_OCS_Bits.TGS */
+#define IFX_HSSL_OCS_TGS_LEN (2u)
+
+/** \brief Mask for Ifx_HSSL_OCS_Bits.TGS */
+#define IFX_HSSL_OCS_TGS_MSK (0x3u)
+
+/** \brief Offset for Ifx_HSSL_OCS_Bits.TGS */
+#define IFX_HSSL_OCS_TGS_OFF (0u)
+
+/** \brief Length for Ifx_HSSL_QFLAGS_Bits.E0 */
+#define IFX_HSSL_QFLAGS_E0_LEN (2u)
+
+/** \brief Mask for Ifx_HSSL_QFLAGS_Bits.E0 */
+#define IFX_HSSL_QFLAGS_E0_MSK (0x3u)
+
+/** \brief Offset for Ifx_HSSL_QFLAGS_Bits.E0 */
+#define IFX_HSSL_QFLAGS_E0_OFF (16u)
+
+/** \brief Length for Ifx_HSSL_QFLAGS_Bits.E1 */
+#define IFX_HSSL_QFLAGS_E1_LEN (2u)
+
+/** \brief Mask for Ifx_HSSL_QFLAGS_Bits.E1 */
+#define IFX_HSSL_QFLAGS_E1_MSK (0x3u)
+
+/** \brief Offset for Ifx_HSSL_QFLAGS_Bits.E1 */
+#define IFX_HSSL_QFLAGS_E1_OFF (18u)
+
+/** \brief Length for Ifx_HSSL_QFLAGS_Bits.E2 */
+#define IFX_HSSL_QFLAGS_E2_LEN (2u)
+
+/** \brief Mask for Ifx_HSSL_QFLAGS_Bits.E2 */
+#define IFX_HSSL_QFLAGS_E2_MSK (0x3u)
+
+/** \brief Offset for Ifx_HSSL_QFLAGS_Bits.E2 */
+#define IFX_HSSL_QFLAGS_E2_OFF (20u)
+
+/** \brief Length for Ifx_HSSL_QFLAGS_Bits.E3 */
+#define IFX_HSSL_QFLAGS_E3_LEN (2u)
+
+/** \brief Mask for Ifx_HSSL_QFLAGS_Bits.E3 */
+#define IFX_HSSL_QFLAGS_E3_MSK (0x3u)
+
+/** \brief Offset for Ifx_HSSL_QFLAGS_Bits.E3 */
+#define IFX_HSSL_QFLAGS_E3_OFF (22u)
+
+/** \brief Length for Ifx_HSSL_QFLAGS_Bits.ES */
+#define IFX_HSSL_QFLAGS_ES_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_QFLAGS_Bits.ES */
+#define IFX_HSSL_QFLAGS_ES_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_QFLAGS_Bits.ES */
+#define IFX_HSSL_QFLAGS_ES_OFF (31u)
+
+/** \brief Length for Ifx_HSSL_QFLAGS_Bits.I */
+#define IFX_HSSL_QFLAGS_I_LEN (4u)
+
+/** \brief Mask for Ifx_HSSL_QFLAGS_Bits.I */
+#define IFX_HSSL_QFLAGS_I_MSK (0xfu)
+
+/** \brief Offset for Ifx_HSSL_QFLAGS_Bits.I */
+#define IFX_HSSL_QFLAGS_I_OFF (0u)
+
+/** \brief Length for Ifx_HSSL_QFLAGS_Bits.IS */
+#define IFX_HSSL_QFLAGS_IS_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_QFLAGS_Bits.IS */
+#define IFX_HSSL_QFLAGS_IS_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_QFLAGS_Bits.IS */
+#define IFX_HSSL_QFLAGS_IS_OFF (28u)
+
+/** \brief Length for Ifx_HSSL_QFLAGS_Bits.R */
+#define IFX_HSSL_QFLAGS_R_LEN (4u)
+
+/** \brief Mask for Ifx_HSSL_QFLAGS_Bits.R */
+#define IFX_HSSL_QFLAGS_R_MSK (0xfu)
+
+/** \brief Offset for Ifx_HSSL_QFLAGS_Bits.R */
+#define IFX_HSSL_QFLAGS_R_OFF (8u)
+
+/** \brief Length for Ifx_HSSL_QFLAGS_Bits.RS */
+#define IFX_HSSL_QFLAGS_RS_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_QFLAGS_Bits.RS */
+#define IFX_HSSL_QFLAGS_RS_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_QFLAGS_Bits.RS */
+#define IFX_HSSL_QFLAGS_RS_OFF (29u)
+
+/** \brief Length for Ifx_HSSL_QFLAGS_Bits.T */
+#define IFX_HSSL_QFLAGS_T_LEN (4u)
+
+/** \brief Mask for Ifx_HSSL_QFLAGS_Bits.T */
+#define IFX_HSSL_QFLAGS_T_MSK (0xfu)
+
+/** \brief Offset for Ifx_HSSL_QFLAGS_Bits.T */
+#define IFX_HSSL_QFLAGS_T_OFF (4u)
+
+/** \brief Length for Ifx_HSSL_QFLAGS_Bits.TS */
+#define IFX_HSSL_QFLAGS_TS_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_QFLAGS_Bits.TS */
+#define IFX_HSSL_QFLAGS_TS_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_QFLAGS_Bits.TS */
+#define IFX_HSSL_QFLAGS_TS_OFF (30u)
+
+/** \brief Length for Ifx_HSSL_SFSFLAGS_Bits.EXFL */
+#define IFX_HSSL_SFSFLAGS_EXFL_LEN (2u)
+
+/** \brief Mask for Ifx_HSSL_SFSFLAGS_Bits.EXFL */
+#define IFX_HSSL_SFSFLAGS_EXFL_MSK (0x3u)
+
+/** \brief Offset for Ifx_HSSL_SFSFLAGS_Bits.EXFL */
+#define IFX_HSSL_SFSFLAGS_EXFL_OFF (4u)
+
+/** \brief Length for Ifx_HSSL_SFSFLAGS_Bits.ISF */
+#define IFX_HSSL_SFSFLAGS_ISF_LEN (1u)
+
+/** \brief Mask for Ifx_HSSL_SFSFLAGS_Bits.ISF */
+#define IFX_HSSL_SFSFLAGS_ISF_MSK (0x1u)
+
+/** \brief Offset for Ifx_HSSL_SFSFLAGS_Bits.ISF */
+#define IFX_HSSL_SFSFLAGS_ISF_OFF (15u)
+
+/** \brief Length for Ifx_HSSL_SFSFLAGS_Bits.RXFL */
+#define IFX_HSSL_SFSFLAGS_RXFL_LEN (2u)
+
+/** \brief Mask for Ifx_HSSL_SFSFLAGS_Bits.RXFL */
+#define IFX_HSSL_SFSFLAGS_RXFL_MSK (0x3u)
+
+/** \brief Offset for Ifx_HSSL_SFSFLAGS_Bits.RXFL */
+#define IFX_HSSL_SFSFLAGS_RXFL_OFF (0u)
+
+/** \brief Length for Ifx_HSSL_SFSFLAGS_Bits.TXFL */
+#define IFX_HSSL_SFSFLAGS_TXFL_LEN (2u)
+
+/** \brief Mask for Ifx_HSSL_SFSFLAGS_Bits.TXFL */
+#define IFX_HSSL_SFSFLAGS_TXFL_MSK (0x3u)
+
+/** \brief Offset for Ifx_HSSL_SFSFLAGS_Bits.TXFL */
+#define IFX_HSSL_SFSFLAGS_TXFL_OFF (2u)
+
+/** \brief Length for Ifx_HSSL_T_TCA_Bits.A */
+#define IFX_HSSL_T_TCA_A_LEN (32u)
+
+/** \brief Mask for Ifx_HSSL_T_TCA_Bits.A */
+#define IFX_HSSL_T_TCA_A_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_HSSL_T_TCA_Bits.A */
+#define IFX_HSSL_T_TCA_A_OFF (0u)
+
+/** \brief Length for Ifx_HSSL_T_TCD_Bits.D */
+#define IFX_HSSL_T_TCD_D_LEN (32u)
+
+/** \brief Mask for Ifx_HSSL_T_TCD_Bits.D */
+#define IFX_HSSL_T_TCD_D_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_HSSL_T_TCD_Bits.D */
+#define IFX_HSSL_T_TCD_D_OFF (0u)
+
+/** \brief Length for Ifx_HSSL_TIDADD_Bits.A */
+#define IFX_HSSL_TIDADD_A_LEN (32u)
+
+/** \brief Mask for Ifx_HSSL_TIDADD_Bits.A */
+#define IFX_HSSL_TIDADD_A_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_HSSL_TIDADD_Bits.A */
+#define IFX_HSSL_TIDADD_A_OFF (0u)
+
+/** \brief Length for Ifx_HSSL_TS_CA_Bits.CURR */
+#define IFX_HSSL_TS_CA_CURR_LEN (27u)
+
+/** \brief Mask for Ifx_HSSL_TS_CA_Bits.CURR */
+#define IFX_HSSL_TS_CA_CURR_MSK (0x7ffffffu)
+
+/** \brief Offset for Ifx_HSSL_TS_CA_Bits.CURR */
+#define IFX_HSSL_TS_CA_CURR_OFF (5u)
+
+/** \brief Length for Ifx_HSSL_TS_FC_Bits.CURCOUNT */
+#define IFX_HSSL_TS_FC_CURCOUNT_LEN (16u)
+
+/** \brief Mask for Ifx_HSSL_TS_FC_Bits.CURCOUNT */
+#define IFX_HSSL_TS_FC_CURCOUNT_MSK (0xffffu)
+
+/** \brief Offset for Ifx_HSSL_TS_FC_Bits.CURCOUNT */
+#define IFX_HSSL_TS_FC_CURCOUNT_OFF (16u)
+
+/** \brief Length for Ifx_HSSL_TS_FC_Bits.RELCOUNT */
+#define IFX_HSSL_TS_FC_RELCOUNT_LEN (16u)
+
+/** \brief Mask for Ifx_HSSL_TS_FC_Bits.RELCOUNT */
+#define IFX_HSSL_TS_FC_RELCOUNT_MSK (0xffffu)
+
+/** \brief Offset for Ifx_HSSL_TS_FC_Bits.RELCOUNT */
+#define IFX_HSSL_TS_FC_RELCOUNT_OFF (0u)
+
+/** \brief Length for Ifx_HSSL_TSSA_Bits.ADDR */
+#define IFX_HSSL_TSSA_ADDR_LEN (27u)
+
+/** \brief Mask for Ifx_HSSL_TSSA_Bits.ADDR */
+#define IFX_HSSL_TSSA_ADDR_MSK (0x7ffffffu)
+
+/** \brief Offset for Ifx_HSSL_TSSA_Bits.ADDR */
+#define IFX_HSSL_TSSA_ADDR_OFF (5u)
+
+/** \brief Length for Ifx_HSSL_TSTAT_Bits.LASTCC0 */
+#define IFX_HSSL_TSTAT_LASTCC0_LEN (5u)
+
+/** \brief Mask for Ifx_HSSL_TSTAT_Bits.LASTCC0 */
+#define IFX_HSSL_TSTAT_LASTCC0_MSK (0x1fu)
+
+/** \brief Offset for Ifx_HSSL_TSTAT_Bits.LASTCC0 */
+#define IFX_HSSL_TSTAT_LASTCC0_OFF (0u)
+
+/** \brief Length for Ifx_HSSL_TSTAT_Bits.LASTCC1 */
+#define IFX_HSSL_TSTAT_LASTCC1_LEN (5u)
+
+/** \brief Mask for Ifx_HSSL_TSTAT_Bits.LASTCC1 */
+#define IFX_HSSL_TSTAT_LASTCC1_MSK (0x1fu)
+
+/** \brief Offset for Ifx_HSSL_TSTAT_Bits.LASTCC1 */
+#define IFX_HSSL_TSTAT_LASTCC1_OFF (8u)
+
+/** \brief Length for Ifx_HSSL_TSTAT_Bits.LASTCC2 */
+#define IFX_HSSL_TSTAT_LASTCC2_LEN (5u)
+
+/** \brief Mask for Ifx_HSSL_TSTAT_Bits.LASTCC2 */
+#define IFX_HSSL_TSTAT_LASTCC2_MSK (0x1fu)
+
+/** \brief Offset for Ifx_HSSL_TSTAT_Bits.LASTCC2 */
+#define IFX_HSSL_TSTAT_LASTCC2_OFF (16u)
+
+/** \brief Length for Ifx_HSSL_TSTAT_Bits.LASTCC3 */
+#define IFX_HSSL_TSTAT_LASTCC3_LEN (5u)
+
+/** \brief Mask for Ifx_HSSL_TSTAT_Bits.LASTCC3 */
+#define IFX_HSSL_TSTAT_LASTCC3_MSK (0x1fu)
+
+/** \brief Offset for Ifx_HSSL_TSTAT_Bits.LASTCC3 */
+#define IFX_HSSL_TSTAT_LASTCC3_OFF (24u)
+
+/** \brief Length for Ifx_HSSL_TSTAT_Bits.LASTTT0 */
+#define IFX_HSSL_TSTAT_LASTTT0_LEN (3u)
+
+/** \brief Mask for Ifx_HSSL_TSTAT_Bits.LASTTT0 */
+#define IFX_HSSL_TSTAT_LASTTT0_MSK (0x7u)
+
+/** \brief Offset for Ifx_HSSL_TSTAT_Bits.LASTTT0 */
+#define IFX_HSSL_TSTAT_LASTTT0_OFF (5u)
+
+/** \brief Length for Ifx_HSSL_TSTAT_Bits.LASTTT1 */
+#define IFX_HSSL_TSTAT_LASTTT1_LEN (3u)
+
+/** \brief Mask for Ifx_HSSL_TSTAT_Bits.LASTTT1 */
+#define IFX_HSSL_TSTAT_LASTTT1_MSK (0x7u)
+
+/** \brief Offset for Ifx_HSSL_TSTAT_Bits.LASTTT1 */
+#define IFX_HSSL_TSTAT_LASTTT1_OFF (13u)
+
+/** \brief Length for Ifx_HSSL_TSTAT_Bits.LASTTT2 */
+#define IFX_HSSL_TSTAT_LASTTT2_LEN (3u)
+
+/** \brief Mask for Ifx_HSSL_TSTAT_Bits.LASTTT2 */
+#define IFX_HSSL_TSTAT_LASTTT2_MSK (0x7u)
+
+/** \brief Offset for Ifx_HSSL_TSTAT_Bits.LASTTT2 */
+#define IFX_HSSL_TSTAT_LASTTT2_OFF (21u)
+
+/** \brief Length for Ifx_HSSL_TSTAT_Bits.LASTTT3 */
+#define IFX_HSSL_TSTAT_LASTTT3_LEN (3u)
+
+/** \brief Mask for Ifx_HSSL_TSTAT_Bits.LASTTT3 */
+#define IFX_HSSL_TSTAT_LASTTT3_MSK (0x7u)
+
+/** \brief Offset for Ifx_HSSL_TSTAT_Bits.LASTTT3 */
+#define IFX_HSSL_TSTAT_LASTTT3_OFF (29u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXHSSL_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxHssl_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxHssl_reg.h
new file mode 100644
index 0000000..ae238d7
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxHssl_reg.h
@@ -0,0 +1,428 @@
+/**
+ * \file IfxHssl_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Hssl_Cfg Hssl address
+ * \ingroup IfxLld_Hssl
+ *
+ * \defgroup IfxLld_Hssl_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Hssl_Cfg
+ *
+ * \defgroup IfxLld_Hssl_Cfg_Hssl 2-HSSL
+ * \ingroup IfxLld_Hssl_Cfg
+ *
+ */
+#ifndef IFXHSSL_REG_H
+#define IFXHSSL_REG_H 1
+/******************************************************************************/
+#include "IfxHssl_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Hssl_Cfg_BaseAddress
+ * \{ */
+
+/** \brief HSSL object */
+#define MODULE_HSSL /*lint --e(923)*/ (*(Ifx_HSSL*)0xF0080000u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Hssl_Cfg_Hssl
+ * \{ */
+
+/** \brief FC, Access Enable Register 0 */
+#define HSSL_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_HSSL_ACCEN0*)0xF00800FCu)
+
+/** \brief F8, Access Enable Register 1 */
+#define HSSL_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_HSSL_ACCEN1*)0xF00800F8u)
+
+/** \brief E0, Access Rules Register */
+#define HSSL_AR /*lint --e(923)*/ (*(volatile Ifx_HSSL_AR*)0xF00800E0u)
+
+/** \brief C4, Access Window End Register */
+#define HSSL_AW0_AWEND /*lint --e(923)*/ (*(volatile Ifx_HSSL_AW_AWEND*)0xF00800C4u)
+
+/** Alias (User Manual Name) for HSSL_AW0_AWEND.
+* To use register names with standard convension, please use HSSL_AW0_AWEND.
+*/
+#define HSSL_AWEND0 (HSSL_AW0_AWEND)
+
+/** \brief C0, Access Window Start Register */
+#define HSSL_AW0_AWSTART /*lint --e(923)*/ (*(volatile Ifx_HSSL_AW_AWSTART*)0xF00800C0u)
+
+/** Alias (User Manual Name) for HSSL_AW0_AWSTART.
+* To use register names with standard convension, please use HSSL_AW0_AWSTART.
+*/
+#define HSSL_AWSTART0 (HSSL_AW0_AWSTART)
+
+/** \brief CC, Access Window End Register */
+#define HSSL_AW1_AWEND /*lint --e(923)*/ (*(volatile Ifx_HSSL_AW_AWEND*)0xF00800CCu)
+
+/** Alias (User Manual Name) for HSSL_AW1_AWEND.
+* To use register names with standard convension, please use HSSL_AW1_AWEND.
+*/
+#define HSSL_AWEND1 (HSSL_AW1_AWEND)
+
+/** \brief C8, Access Window Start Register */
+#define HSSL_AW1_AWSTART /*lint --e(923)*/ (*(volatile Ifx_HSSL_AW_AWSTART*)0xF00800C8u)
+
+/** Alias (User Manual Name) for HSSL_AW1_AWSTART.
+* To use register names with standard convension, please use HSSL_AW1_AWSTART.
+*/
+#define HSSL_AWSTART1 (HSSL_AW1_AWSTART)
+
+/** \brief D4, Access Window End Register */
+#define HSSL_AW2_AWEND /*lint --e(923)*/ (*(volatile Ifx_HSSL_AW_AWEND*)0xF00800D4u)
+
+/** Alias (User Manual Name) for HSSL_AW2_AWEND.
+* To use register names with standard convension, please use HSSL_AW2_AWEND.
+*/
+#define HSSL_AWEND2 (HSSL_AW2_AWEND)
+
+/** \brief D0, Access Window Start Register */
+#define HSSL_AW2_AWSTART /*lint --e(923)*/ (*(volatile Ifx_HSSL_AW_AWSTART*)0xF00800D0u)
+
+/** Alias (User Manual Name) for HSSL_AW2_AWSTART.
+* To use register names with standard convension, please use HSSL_AW2_AWSTART.
+*/
+#define HSSL_AWSTART2 (HSSL_AW2_AWSTART)
+
+/** \brief DC, Access Window End Register */
+#define HSSL_AW3_AWEND /*lint --e(923)*/ (*(volatile Ifx_HSSL_AW_AWEND*)0xF00800DCu)
+
+/** Alias (User Manual Name) for HSSL_AW3_AWEND.
+* To use register names with standard convension, please use HSSL_AW3_AWEND.
+*/
+#define HSSL_AWEND3 (HSSL_AW3_AWEND)
+
+/** \brief D8, Access Window Start Register */
+#define HSSL_AW3_AWSTART /*lint --e(923)*/ (*(volatile Ifx_HSSL_AW_AWSTART*)0xF00800D8u)
+
+/** Alias (User Manual Name) for HSSL_AW3_AWSTART.
+* To use register names with standard convension, please use HSSL_AW3_AWSTART.
+*/
+#define HSSL_AWSTART3 (HSSL_AW3_AWSTART)
+
+/** \brief 10, Configuration Register */
+#define HSSL_CFG /*lint --e(923)*/ (*(volatile Ifx_HSSL_CFG*)0xF0080010u)
+
+/** \brief 0, Clock Control Register */
+#define HSSL_CLC /*lint --e(923)*/ (*(volatile Ifx_HSSL_CLC*)0xF0080000u)
+
+/** \brief C, CRC Control Register */
+#define HSSL_CRC /*lint --e(923)*/ (*(volatile Ifx_HSSL_CRC*)0xF008000Cu)
+
+/** \brief 34, Initiator Control Data Register */
+#define HSSL_I0_ICON /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_ICON*)0xF0080034u)
+
+/** Alias (User Manual Name) for HSSL_I0_ICON.
+* To use register names with standard convension, please use HSSL_I0_ICON.
+*/
+#define HSSL_ICON0 (HSSL_I0_ICON)
+
+/** \brief 3C, Initiator Read Data Register */
+#define HSSL_I0_IRD /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_IRD*)0xF008003Cu)
+
+/** Alias (User Manual Name) for HSSL_I0_IRD.
+* To use register names with standard convension, please use HSSL_I0_IRD.
+*/
+#define HSSL_IRD0 (HSSL_I0_IRD)
+
+/** \brief 38, Initiator Read Write Address Register */
+#define HSSL_I0_IRWA /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_IRWA*)0xF0080038u)
+
+/** Alias (User Manual Name) for HSSL_I0_IRWA.
+* To use register names with standard convension, please use HSSL_I0_IRWA.
+*/
+#define HSSL_IRWA0 (HSSL_I0_IRWA)
+
+/** \brief 30, Initiator Write Data Register */
+#define HSSL_I0_IWD /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_IWD*)0xF0080030u)
+
+/** Alias (User Manual Name) for HSSL_I0_IWD.
+* To use register names with standard convension, please use HSSL_I0_IWD.
+*/
+#define HSSL_IWD0 (HSSL_I0_IWD)
+
+/** \brief 44, Initiator Control Data Register */
+#define HSSL_I1_ICON /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_ICON*)0xF0080044u)
+
+/** Alias (User Manual Name) for HSSL_I1_ICON.
+* To use register names with standard convension, please use HSSL_I1_ICON.
+*/
+#define HSSL_ICON1 (HSSL_I1_ICON)
+
+/** \brief 4C, Initiator Read Data Register */
+#define HSSL_I1_IRD /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_IRD*)0xF008004Cu)
+
+/** Alias (User Manual Name) for HSSL_I1_IRD.
+* To use register names with standard convension, please use HSSL_I1_IRD.
+*/
+#define HSSL_IRD1 (HSSL_I1_IRD)
+
+/** \brief 48, Initiator Read Write Address Register */
+#define HSSL_I1_IRWA /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_IRWA*)0xF0080048u)
+
+/** Alias (User Manual Name) for HSSL_I1_IRWA.
+* To use register names with standard convension, please use HSSL_I1_IRWA.
+*/
+#define HSSL_IRWA1 (HSSL_I1_IRWA)
+
+/** \brief 40, Initiator Write Data Register */
+#define HSSL_I1_IWD /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_IWD*)0xF0080040u)
+
+/** Alias (User Manual Name) for HSSL_I1_IWD.
+* To use register names with standard convension, please use HSSL_I1_IWD.
+*/
+#define HSSL_IWD1 (HSSL_I1_IWD)
+
+/** \brief 54, Initiator Control Data Register */
+#define HSSL_I2_ICON /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_ICON*)0xF0080054u)
+
+/** Alias (User Manual Name) for HSSL_I2_ICON.
+* To use register names with standard convension, please use HSSL_I2_ICON.
+*/
+#define HSSL_ICON2 (HSSL_I2_ICON)
+
+/** \brief 5C, Initiator Read Data Register */
+#define HSSL_I2_IRD /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_IRD*)0xF008005Cu)
+
+/** Alias (User Manual Name) for HSSL_I2_IRD.
+* To use register names with standard convension, please use HSSL_I2_IRD.
+*/
+#define HSSL_IRD2 (HSSL_I2_IRD)
+
+/** \brief 58, Initiator Read Write Address Register */
+#define HSSL_I2_IRWA /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_IRWA*)0xF0080058u)
+
+/** Alias (User Manual Name) for HSSL_I2_IRWA.
+* To use register names with standard convension, please use HSSL_I2_IRWA.
+*/
+#define HSSL_IRWA2 (HSSL_I2_IRWA)
+
+/** \brief 50, Initiator Write Data Register */
+#define HSSL_I2_IWD /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_IWD*)0xF0080050u)
+
+/** Alias (User Manual Name) for HSSL_I2_IWD.
+* To use register names with standard convension, please use HSSL_I2_IWD.
+*/
+#define HSSL_IWD2 (HSSL_I2_IWD)
+
+/** \brief 64, Initiator Control Data Register */
+#define HSSL_I3_ICON /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_ICON*)0xF0080064u)
+
+/** Alias (User Manual Name) for HSSL_I3_ICON.
+* To use register names with standard convension, please use HSSL_I3_ICON.
+*/
+#define HSSL_ICON3 (HSSL_I3_ICON)
+
+/** \brief 6C, Initiator Read Data Register */
+#define HSSL_I3_IRD /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_IRD*)0xF008006Cu)
+
+/** Alias (User Manual Name) for HSSL_I3_IRD.
+* To use register names with standard convension, please use HSSL_I3_IRD.
+*/
+#define HSSL_IRD3 (HSSL_I3_IRD)
+
+/** \brief 68, Initiator Read Write Address Register */
+#define HSSL_I3_IRWA /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_IRWA*)0xF0080068u)
+
+/** Alias (User Manual Name) for HSSL_I3_IRWA.
+* To use register names with standard convension, please use HSSL_I3_IRWA.
+*/
+#define HSSL_IRWA3 (HSSL_I3_IRWA)
+
+/** \brief 60, Initiator Write Data Register */
+#define HSSL_I3_IWD /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_IWD*)0xF0080060u)
+
+/** Alias (User Manual Name) for HSSL_I3_IWD.
+* To use register names with standard convension, please use HSSL_I3_IWD.
+*/
+#define HSSL_IWD3 (HSSL_I3_IWD)
+
+/** \brief 8, Module Identification Register */
+#define HSSL_ID /*lint --e(923)*/ (*(volatile Ifx_HSSL_ID*)0xF0080008u)
+
+/** \brief A8, Initiator Stream Current Address Register */
+#define HSSL_IS_CA /*lint --e(923)*/ (*(volatile Ifx_HSSL_IS_CA*)0xF00800A8u)
+
+/** Alias (User Manual Name) for HSSL_IS_CA.
+* To use register names with standard convension, please use HSSL_IS_CA.
+*/
+#define HSSL_ISCA (HSSL_IS_CA)
+
+/** \brief AC, Initiator Stream Frame Count Register */
+#define HSSL_IS_FC /*lint --e(923)*/ (*(volatile Ifx_HSSL_IS_FC*)0xF00800ACu)
+
+/** Alias (User Manual Name) for HSSL_IS_FC.
+* To use register names with standard convension, please use HSSL_IS_FC.
+*/
+#define HSSL_ISFC (HSSL_IS_FC)
+
+/** \brief A0, Initiator Stream Start Address Register */
+#define HSSL_IS_SA0 /*lint --e(923)*/ (*(volatile Ifx_HSSL_ISSA*)0xF00800A0u)
+
+/** Alias (User Manual Name) for HSSL_IS_SA0.
+* To use register names with standard convension, please use HSSL_IS_SA0.
+*/
+#define HSSL_ISSA0 (HSSL_IS_SA0)
+
+/** \brief A4, Initiator Stream Start Address Register */
+#define HSSL_IS_SA1 /*lint --e(923)*/ (*(volatile Ifx_HSSL_ISSA*)0xF00800A4u)
+
+/** Alias (User Manual Name) for HSSL_IS_SA1.
+* To use register names with standard convension, please use HSSL_IS_SA1.
+*/
+#define HSSL_ISSA1 (HSSL_IS_SA1)
+
+/** \brief F4, Kernel Reset Register 0 */
+#define HSSL_KRST0 /*lint --e(923)*/ (*(volatile Ifx_HSSL_KRST0*)0xF00800F4u)
+
+/** \brief F0, Kernel Reset Register 1 */
+#define HSSL_KRST1 /*lint --e(923)*/ (*(volatile Ifx_HSSL_KRST1*)0xF00800F0u)
+
+/** \brief EC, Kernel Reset Status Clear Register */
+#define HSSL_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_HSSL_KRSTCLR*)0xF00800ECu)
+
+/** \brief 18, Miscellaneous Flags Register */
+#define HSSL_MFLAGS /*lint --e(923)*/ (*(volatile Ifx_HSSL_MFLAGS*)0xF0080018u)
+
+/** \brief 20, Miscellaneous Flags Clear Register */
+#define HSSL_MFLAGSCL /*lint --e(923)*/ (*(volatile Ifx_HSSL_MFLAGSCL*)0xF0080020u)
+
+/** \brief 24, Flags Enable Register */
+#define HSSL_MFLAGSEN /*lint --e(923)*/ (*(volatile Ifx_HSSL_MFLAGSEN*)0xF0080024u)
+
+/** \brief 1C, Miscellaneous Flags Set Register */
+#define HSSL_MFLAGSSET /*lint --e(923)*/ (*(volatile Ifx_HSSL_MFLAGSSET*)0xF008001Cu)
+
+/** \brief E8, OCDS Control and Status */
+#define HSSL_OCS /*lint --e(923)*/ (*(volatile Ifx_HSSL_OCS*)0xF00800E8u)
+
+/** \brief 14, Request Flags Register */
+#define HSSL_QFLAGS /*lint --e(923)*/ (*(volatile Ifx_HSSL_QFLAGS*)0xF0080014u)
+
+/** \brief 28, Stream FIFOs Status Flags Register */
+#define HSSL_SFSFLAGS /*lint --e(923)*/ (*(volatile Ifx_HSSL_SFSFLAGS*)0xF0080028u)
+
+/** \brief 74, Target Current Address Register */
+#define HSSL_T0_TCA /*lint --e(923)*/ (*(volatile Ifx_HSSL_T_TCA*)0xF0080074u)
+
+/** Alias (User Manual Name) for HSSL_T0_TCA.
+* To use register names with standard convension, please use HSSL_T0_TCA.
+*/
+#define HSSL_TCA0 (HSSL_T0_TCA)
+
+/** \brief 70, Target Current Data Register */
+#define HSSL_T0_TCD /*lint --e(923)*/ (*(volatile Ifx_HSSL_T_TCD*)0xF0080070u)
+
+/** Alias (User Manual Name) for HSSL_T0_TCD.
+* To use register names with standard convension, please use HSSL_T0_TCD.
+*/
+#define HSSL_TCD0 (HSSL_T0_TCD)
+
+/** \brief 7C, Target Current Address Register */
+#define HSSL_T1_TCA /*lint --e(923)*/ (*(volatile Ifx_HSSL_T_TCA*)0xF008007Cu)
+
+/** Alias (User Manual Name) for HSSL_T1_TCA.
+* To use register names with standard convension, please use HSSL_T1_TCA.
+*/
+#define HSSL_TCA1 (HSSL_T1_TCA)
+
+/** \brief 78, Target Current Data Register */
+#define HSSL_T1_TCD /*lint --e(923)*/ (*(volatile Ifx_HSSL_T_TCD*)0xF0080078u)
+
+/** Alias (User Manual Name) for HSSL_T1_TCD.
+* To use register names with standard convension, please use HSSL_T1_TCD.
+*/
+#define HSSL_TCD1 (HSSL_T1_TCD)
+
+/** \brief 84, Target Current Address Register */
+#define HSSL_T2_TCA /*lint --e(923)*/ (*(volatile Ifx_HSSL_T_TCA*)0xF0080084u)
+
+/** Alias (User Manual Name) for HSSL_T2_TCA.
+* To use register names with standard convension, please use HSSL_T2_TCA.
+*/
+#define HSSL_TCA2 (HSSL_T2_TCA)
+
+/** \brief 80, Target Current Data Register */
+#define HSSL_T2_TCD /*lint --e(923)*/ (*(volatile Ifx_HSSL_T_TCD*)0xF0080080u)
+
+/** Alias (User Manual Name) for HSSL_T2_TCD.
+* To use register names with standard convension, please use HSSL_T2_TCD.
+*/
+#define HSSL_TCD2 (HSSL_T2_TCD)
+
+/** \brief 8C, Target Current Address Register */
+#define HSSL_T3_TCA /*lint --e(923)*/ (*(volatile Ifx_HSSL_T_TCA*)0xF008008Cu)
+
+/** Alias (User Manual Name) for HSSL_T3_TCA.
+* To use register names with standard convension, please use HSSL_T3_TCA.
+*/
+#define HSSL_TCA3 (HSSL_T3_TCA)
+
+/** \brief 88, Target Current Data Register */
+#define HSSL_T3_TCD /*lint --e(923)*/ (*(volatile Ifx_HSSL_T_TCD*)0xF0080088u)
+
+/** Alias (User Manual Name) for HSSL_T3_TCD.
+* To use register names with standard convension, please use HSSL_T3_TCD.
+*/
+#define HSSL_TCD3 (HSSL_T3_TCD)
+
+/** \brief 94, Target ID Address Register */
+#define HSSL_TIDADD /*lint --e(923)*/ (*(volatile Ifx_HSSL_TIDADD*)0xF0080094u)
+
+/** \brief B8, Target Stream Current Address Register */
+#define HSSL_TS_CA /*lint --e(923)*/ (*(volatile Ifx_HSSL_TS_CA*)0xF00800B8u)
+
+/** Alias (User Manual Name) for HSSL_TS_CA.
+* To use register names with standard convension, please use HSSL_TS_CA.
+*/
+#define HSSL_TSCA (HSSL_TS_CA)
+
+/** \brief BC, Target Stream Frame Count Register */
+#define HSSL_TS_FC /*lint --e(923)*/ (*(volatile Ifx_HSSL_TS_FC*)0xF00800BCu)
+
+/** Alias (User Manual Name) for HSSL_TS_FC.
+* To use register names with standard convension, please use HSSL_TS_FC.
+*/
+#define HSSL_TSFC (HSSL_TS_FC)
+
+/** \brief B0, Target Stream Start Address Register */
+#define HSSL_TS_SA0 /*lint --e(923)*/ (*(volatile Ifx_HSSL_TSSA*)0xF00800B0u)
+
+/** Alias (User Manual Name) for HSSL_TS_SA0.
+* To use register names with standard convension, please use HSSL_TS_SA0.
+*/
+#define HSSL_TSSA0 (HSSL_TS_SA0)
+
+/** \brief B4, Target Stream Start Address Register */
+#define HSSL_TS_SA1 /*lint --e(923)*/ (*(volatile Ifx_HSSL_TSSA*)0xF00800B4u)
+
+/** Alias (User Manual Name) for HSSL_TS_SA1.
+* To use register names with standard convension, please use HSSL_TS_SA1.
+*/
+#define HSSL_TSSA1 (HSSL_TS_SA1)
+
+/** \brief 90, Target Status Register */
+#define HSSL_TSTAT /*lint --e(923)*/ (*(volatile Ifx_HSSL_TSTAT*)0xF0080090u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXHSSL_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxHssl_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxHssl_regdef.h
new file mode 100644
index 0000000..09384ed
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxHssl_regdef.h
@@ -0,0 +1,772 @@
+/**
+ * \file IfxHssl_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Hssl Hssl
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Hssl_Bitfields Bitfields
+ * \ingroup IfxLld_Hssl
+ *
+ * \defgroup IfxLld_Hssl_union Union
+ * \ingroup IfxLld_Hssl
+ *
+ * \defgroup IfxLld_Hssl_struct Struct
+ * \ingroup IfxLld_Hssl
+ *
+ */
+#ifndef IFXHSSL_REGDEF_H
+#define IFXHSSL_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Hssl_Bitfields
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef struct _Ifx_HSSL_ACCEN0_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_HSSL_ACCEN0_Bits;
+
+/** \brief Access Enable Register 1 */
+typedef struct _Ifx_HSSL_ACCEN1_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_HSSL_ACCEN1_Bits;
+
+/** \brief Access Rules Register */
+typedef struct _Ifx_HSSL_AR_Bits
+{
+ unsigned int ARW0:2; /**< \brief [1:0] Access Rule for Window 0 (rw) */
+ unsigned int ARW1:2; /**< \brief [3:2] Access Rule for Window 1 (rw) */
+ unsigned int ARW2:2; /**< \brief [5:4] Access Rule for Window 2 (rw) */
+ unsigned int ARW3:2; /**< \brief [7:6] Access Rule for Window 3 (rw) */
+ unsigned int reserved_8:8; /**< \brief \internal Reserved */
+ unsigned int MAVCH:2; /**< \brief [17:16] Memory Access Violation Channel (rh) */
+ unsigned int reserved_18:14; /**< \brief \internal Reserved */
+} Ifx_HSSL_AR_Bits;
+
+/** \brief Access Window End Register */
+typedef struct _Ifx_HSSL_AW_AWEND_Bits
+{
+ unsigned int reserved_0:8; /**< \brief \internal Reserved */
+ unsigned int AWE:24; /**< \brief [31:8] Access Window End Address (rw) */
+} Ifx_HSSL_AW_AWEND_Bits;
+
+/** \brief Access Window Start Register */
+typedef struct _Ifx_HSSL_AW_AWSTART_Bits
+{
+ unsigned int reserved_0:8; /**< \brief \internal Reserved */
+ unsigned int AWS:24; /**< \brief [31:8] Access Window Start Address (rw) */
+} Ifx_HSSL_AW_AWSTART_Bits;
+
+/** \brief Configuration Register */
+typedef struct _Ifx_HSSL_CFG_Bits
+{
+ unsigned int PREDIV:14; /**< \brief [13:0] Global Predivider (rw) */
+ unsigned int reserved_14:2; /**< \brief \internal Reserved */
+ unsigned int SMT:1; /**< \brief [16:16] Streaming Mode Transmitter (rw) */
+ unsigned int SMR:1; /**< \brief [17:17] Streaming Mode Receiver (rw) */
+ unsigned int SCM:1; /**< \brief [18:18] Streaming Channel Mode (rw) */
+ unsigned int CCC:1; /**< \brief [19:19] Channel Code Control (rw) */
+ unsigned int reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_HSSL_CFG_Bits;
+
+/** \brief Clock Control Register */
+typedef struct _Ifx_HSSL_CLC_Bits
+{
+ unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
+ unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
+ unsigned int reserved_2:1; /**< \brief \internal Reserved */
+ unsigned int EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control (rw) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_HSSL_CLC_Bits;
+
+/** \brief CRC Control Register */
+typedef struct _Ifx_HSSL_CRC_Bits
+{
+ unsigned int XORMASK:16; /**< \brief [15:0] Value to be XORed with the Calculated CRC (rw) */
+ unsigned int XEN:1; /**< \brief [16:16] Enable the Error Injection via XORMASK (rw) */
+ unsigned int reserved_17:15; /**< \brief \internal Reserved */
+} Ifx_HSSL_CRC_Bits;
+
+/** \brief Initiator Control Data Register */
+typedef struct _Ifx_HSSL_I_ICON_Bits
+{
+ unsigned int IDQ:1; /**< \brief [0:0] Read ID Request (w) */
+ unsigned int TQ:1; /**< \brief [1:1] Trigger Request (w) */
+ unsigned int LETT:3; /**< \brief [4:2] Last Error Transaction Tag (rh) */
+ unsigned int CETT:3; /**< \brief [7:5] Currently Expected Transaction Tag (rh) */
+ unsigned int TOCV:8; /**< \brief [15:8] Time Out Current Value (rh) */
+ unsigned int DATLEN:2; /**< \brief [17:16] Data Length (rw) */
+ unsigned int RWT:2; /**< \brief [19:18] Read Write Trigger Command Type (rw) */
+ unsigned int BSY:1; /**< \brief [20:20] Channel Busy (rh) */
+ unsigned int ITTAG:3; /**< \brief [23:21] Initiator Transaction Tag (rh) */
+ unsigned int TOREL:8; /**< \brief [31:24] Time Out Reload Value (rw) */
+} Ifx_HSSL_I_ICON_Bits;
+
+/** \brief Initiator Read Data Register */
+typedef struct _Ifx_HSSL_I_IRD_Bits
+{
+ unsigned int DATA:32; /**< \brief [31:0] Data Delivered by a Read Response Frame (rh) */
+} Ifx_HSSL_I_IRD_Bits;
+
+/** \brief Initiator Read Write Address Register */
+typedef struct _Ifx_HSSL_I_IRWA_Bits
+{
+ unsigned int ADDRESS:32; /**< \brief [31:0] Address Part of the Payload of a Write Frame (rw) */
+} Ifx_HSSL_I_IRWA_Bits;
+
+/** \brief Initiator Write Data Register */
+typedef struct _Ifx_HSSL_I_IWD_Bits
+{
+ unsigned int DATA:32; /**< \brief [31:0] Data Part of the Payload of a Write Frame (rw) */
+} Ifx_HSSL_I_IWD_Bits;
+
+/** \brief Module Identification Register */
+typedef struct _Ifx_HSSL_ID_Bits
+{
+ unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
+ unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_HSSL_ID_Bits;
+
+/** \brief Initiator Stream Current Address Register */
+typedef struct _Ifx_HSSL_IS_CA_Bits
+{
+ unsigned int reserved_0:5; /**< \brief \internal Reserved */
+ unsigned int CURR:27; /**< \brief [31:5] Address of the Memory Location for the Current Transfer (rh) */
+} Ifx_HSSL_IS_CA_Bits;
+
+/** \brief Initiator Stream Frame Count Register */
+typedef struct _Ifx_HSSL_IS_FC_Bits
+{
+ unsigned int RELCOUNT:16; /**< \brief [15:0] Reload Count Number (rw) */
+ unsigned int CURCOUNT:16; /**< \brief [31:16] Current Count Number (rh) */
+} Ifx_HSSL_IS_FC_Bits;
+
+/** \brief Initiator Stream Start Address Register */
+typedef struct _Ifx_HSSL_ISSA_Bits
+{
+ unsigned int reserved_0:5; /**< \brief \internal Reserved */
+ unsigned int START:27; /**< \brief [31:5] Start Address for the Memory Range (rw) */
+} Ifx_HSSL_ISSA_Bits;
+
+/** \brief Kernel Reset Register 0 */
+typedef struct _Ifx_HSSL_KRST0_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rh) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_HSSL_KRST0_Bits;
+
+/** \brief Kernel Reset Register 1 */
+typedef struct _Ifx_HSSL_KRST1_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_HSSL_KRST1_Bits;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef struct _Ifx_HSSL_KRSTCLR_Bits
+{
+ unsigned int CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_HSSL_KRSTCLR_Bits;
+
+/** \brief Miscellaneous Flags Register */
+typedef struct _Ifx_HSSL_MFLAGS_Bits
+{
+ unsigned int NACK:4; /**< \brief [3:0] Not Acknowledge Error - Target Error (rh) */
+ unsigned int TTE:4; /**< \brief [7:4] Transaction Tag Error (rh) */
+ unsigned int TIMEOUT:4; /**< \brief [11:8] Timeout Error (rh) */
+ unsigned int UNEXPECTED:4; /**< \brief [15:12] Unexpected Type of Frame Error (rh) */
+ unsigned int reserved_16:2; /**< \brief \internal Reserved */
+ unsigned int TMB:1; /**< \brief [18:18] Target Memory Block (rh) */
+ unsigned int IMB:1; /**< \brief [19:19] Initiator Memory Block (rh) */
+ unsigned int ISB:1; /**< \brief [20:20] Initiator Stream Block Request (rh) */
+ unsigned int MAV:1; /**< \brief [21:21] Memory Access Violation (rh) */
+ unsigned int SRIE:1; /**< \brief [22:22] SRI/SPB Bus Access Error (rh) */
+ unsigned int PIE1:1; /**< \brief [23:23] PHY Inconsistency Error 1 (rh) */
+ unsigned int PIE2:1; /**< \brief [24:24] PHY Inconsistency Error 2 (rh) */
+ unsigned int CRCE:1; /**< \brief [25:25] CRC Error (rh) */
+ unsigned int reserved_26:2; /**< \brief \internal Reserved */
+ unsigned int TSE:1; /**< \brief [28:28] Target Stream Enable (rh) */
+ unsigned int TEI:1; /**< \brief [29:29] Transmit Enable Input (rh) */
+ unsigned int TEO:1; /**< \brief [30:30] Transmit Enable Output (rh) */
+ unsigned int INI:1; /**< \brief [31:31] Initialize Mode (rh) */
+} Ifx_HSSL_MFLAGS_Bits;
+
+/** \brief Miscellaneous Flags Clear Register */
+typedef struct _Ifx_HSSL_MFLAGSCL_Bits
+{
+ unsigned int NACKC:4; /**< \brief [3:0] NACK Flags Clear (w) */
+ unsigned int TTEC:4; /**< \brief [7:4] Transaction Tag Error Flags Clear (w) */
+ unsigned int TIMEOUTC:4; /**< \brief [11:8] Timeout Error Flags Clear (w) */
+ unsigned int UNEXPECTEDC:4; /**< \brief [15:12] Unexpected Error Flags Clear (w) */
+ unsigned int reserved_16:2; /**< \brief \internal Reserved */
+ unsigned int TMBC:1; /**< \brief [18:18] Target Memory Block Flag Clear (w) */
+ unsigned int IMBC:1; /**< \brief [19:19] Initiator Memory Block Flag Clear (w) */
+ unsigned int ISBC:1; /**< \brief [20:20] Initiator Stream Block Request Clear (w) */
+ unsigned int MAVC:1; /**< \brief [21:21] MAV Flag Clear (w) */
+ unsigned int SRIEC:1; /**< \brief [22:22] SRI/SPB Bus Access Error Flag Clear (w) */
+ unsigned int PIE1C:1; /**< \brief [23:23] PIE1 Error Flag Clear (w) */
+ unsigned int PIE2C:1; /**< \brief [24:24] PIE2 Error Flag Clear (w) */
+ unsigned int CRCEC:1; /**< \brief [25:25] CRC Error Flag Clear (w) */
+ unsigned int reserved_26:2; /**< \brief \internal Reserved */
+ unsigned int TSEC:1; /**< \brief [28:28] Target Stream Enable Flag Clear (w) */
+ unsigned int reserved_29:1; /**< \brief \internal Reserved */
+ unsigned int TEOC:1; /**< \brief [30:30] Transmit Enable Flag Clear (w) */
+ unsigned int INIC:1; /**< \brief [31:31] Initialize Mode Flag Clear (w) */
+} Ifx_HSSL_MFLAGSCL_Bits;
+
+/** \brief Flags Enable Register */
+typedef struct _Ifx_HSSL_MFLAGSEN_Bits
+{
+ unsigned int NACKEN:4; /**< \brief [3:0] Not Acknowledge Error Enable Bits (rw) */
+ unsigned int TTEEN:4; /**< \brief [7:4] Transaction Tag Error Enable Bits (rw) */
+ unsigned int TIMEOUTEN:4; /**< \brief [11:8] Timeout Error Enable Bits (rw) */
+ unsigned int UNEXPECTEDEN:4; /**< \brief [15:12] Unexpected Error Enable Bits (rw) */
+ unsigned int reserved_16:5; /**< \brief \internal Reserved */
+ unsigned int MAVEN:1; /**< \brief [21:21] MAV Enable Bit (rw) */
+ unsigned int SRIEEN:1; /**< \brief [22:22] SRI/SPB Bus Access Error Enable Bit (rw) */
+ unsigned int PIE1EN:1; /**< \brief [23:23] PIE1 Error Enable Bit (rw) */
+ unsigned int PIE2EN:1; /**< \brief [24:24] PIE2 Error Enable Bit (rw) */
+ unsigned int CRCEEN:1; /**< \brief [25:25] CRC Error Enable Bit (rw) */
+ unsigned int reserved_26:3; /**< \brief \internal Reserved */
+ unsigned int TEIEN:1; /**< \brief [29:29] TEI Enable Bit (rw) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_HSSL_MFLAGSEN_Bits;
+
+/** \brief Miscellaneous Flags Set Register */
+typedef struct _Ifx_HSSL_MFLAGSSET_Bits
+{
+ unsigned int NACKS:4; /**< \brief [3:0] NACK Flags Set (w) */
+ unsigned int TTES:4; /**< \brief [7:4] Transaction Tag Error Flags Set (w) */
+ unsigned int TIMEOUTS:4; /**< \brief [11:8] Timeout Error Flags Set (w) */
+ unsigned int UNEXPECTEDS:4; /**< \brief [15:12] Unexpected Error Flags Set (w) */
+ unsigned int reserved_16:2; /**< \brief \internal Reserved */
+ unsigned int TMBS:1; /**< \brief [18:18] Target Memory Block Flag Set (w) */
+ unsigned int IMBS:1; /**< \brief [19:19] Initiator Memory Block Flag Set (w) */
+ unsigned int ISBS:1; /**< \brief [20:20] Initiator Stream Block Request Set (w) */
+ unsigned int MAVS:1; /**< \brief [21:21] MAV Flag Set (w) */
+ unsigned int SRIES:1; /**< \brief [22:22] SRI/SPB Bus Access Error Flag Set (w) */
+ unsigned int PIE1S:1; /**< \brief [23:23] PIE1 Error Flag Set (w) */
+ unsigned int PIE2S:1; /**< \brief [24:24] PIE2 Error Flag Set (w) */
+ unsigned int CRCES:1; /**< \brief [25:25] CRC Error Flag Set (w) */
+ unsigned int reserved_26:2; /**< \brief \internal Reserved */
+ unsigned int TSES:1; /**< \brief [28:28] Target Stream Enable Flag Set (w) */
+ unsigned int reserved_29:1; /**< \brief \internal Reserved */
+ unsigned int TEOS:1; /**< \brief [30:30] Transmit Enable Flag Set (w) */
+ unsigned int INIS:1; /**< \brief [31:31] Initialize Mode Flag Set (w) */
+} Ifx_HSSL_MFLAGSSET_Bits;
+
+/** \brief OCDS Control and Status */
+typedef struct _Ifx_HSSL_OCS_Bits
+{
+ unsigned int TGS:2; /**< \brief [1:0] Trigger Set for OTGB0/1 (rw) */
+ unsigned int TGB:1; /**< \brief [2:2] OTGB0/1 Bus Select (rw) */
+ unsigned int TG_P:1; /**< \brief [3:3] TGS, TGB Write Protection (w) */
+ unsigned int reserved_4:20; /**< \brief \internal Reserved */
+ unsigned int SUS:4; /**< \brief [27:24] OCDS Suspend Control (rw) */
+ unsigned int SUS_P:1; /**< \brief [28:28] SUS Write Protection (w) */
+ unsigned int SUSSTA:1; /**< \brief [29:29] Suspend State (rh) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_HSSL_OCS_Bits;
+
+/** \brief Request Flags Register */
+typedef struct _Ifx_HSSL_QFLAGS_Bits
+{
+ unsigned int I:4; /**< \brief [3:0] Request Flags for Initiated Commands (rh) */
+ unsigned int T:4; /**< \brief [7:4] Request Flags for Commands Arrived at Target (rh) */
+ unsigned int R:4; /**< \brief [11:8] Request Flags for Response Frames at the Target (rh) */
+ unsigned int reserved_12:4; /**< \brief \internal Reserved */
+ unsigned int E0:2; /**< \brief [17:16] Expect Flags for Activated Timeout Timer 0 (rh) */
+ unsigned int E1:2; /**< \brief [19:18] Expect Flags for Activated Timeout Timer 1 (rh) */
+ unsigned int E2:2; /**< \brief [21:20] Expect Flags for Activated Timeout Timer 2 (rh) */
+ unsigned int E3:2; /**< \brief [23:22] Expect Flags for Activated Timeout Timer 3 (rh) */
+ unsigned int reserved_24:4; /**< \brief \internal Reserved */
+ unsigned int IS:1; /**< \brief [28:28] I Flag for Stream Frames (rh) */
+ unsigned int RS:1; /**< \brief [29:29] R Flag for Stream Frames (rh) */
+ unsigned int TS:1; /**< \brief [30:30] T Flag for Stream Frames (rh) */
+ unsigned int ES:1; /**< \brief [31:31] E Flag for Stream Frames (rh) */
+} Ifx_HSSL_QFLAGS_Bits;
+
+/** \brief Stream FIFOs Status Flags Register */
+typedef struct _Ifx_HSSL_SFSFLAGS_Bits
+{
+ unsigned int RXFL:2; /**< \brief [1:0] Stream RxFIFO Filling Level (rh) */
+ unsigned int TXFL:2; /**< \brief [3:2] Stream TxFIFO Filling Level (rh) */
+ unsigned int EXFL:2; /**< \brief [5:4] Stream Expect FIFO Filling Level (rh) */
+ unsigned int reserved_6:9; /**< \brief \internal Reserved */
+ unsigned int ISF:1; /**< \brief [15:15] Initiator Stream Frame Request (rh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_HSSL_SFSFLAGS_Bits;
+
+/** \brief Target Current Address Register */
+typedef struct _Ifx_HSSL_T_TCA_Bits
+{
+ unsigned int A:32; /**< \brief [31:0] Address Part of the Payload of a Write Command Frame or a Read Command Frame or ID Frame (rh) */
+} Ifx_HSSL_T_TCA_Bits;
+
+/** \brief Target Current Data Register */
+typedef struct _Ifx_HSSL_T_TCD_Bits
+{
+ unsigned int D:32; /**< \brief [31:0] Data Part of the Payload of a Write Command Frame or Read Data of a Read Command Frame (rh) */
+} Ifx_HSSL_T_TCD_Bits;
+
+/** \brief Target ID Address Register */
+typedef struct _Ifx_HSSL_TIDADD_Bits
+{
+ unsigned int A:32; /**< \brief [31:0] Address Pointer (rw) */
+} Ifx_HSSL_TIDADD_Bits;
+
+/** \brief Target Stream Current Address Register */
+typedef struct _Ifx_HSSL_TS_CA_Bits
+{
+ unsigned int reserved_0:5; /**< \brief \internal Reserved */
+ unsigned int CURR:27; /**< \brief [31:5] Address of the Memory Location for the Current Transfer (rh) */
+} Ifx_HSSL_TS_CA_Bits;
+
+/** \brief Target Stream Frame Count Register */
+typedef struct _Ifx_HSSL_TS_FC_Bits
+{
+ unsigned int RELCOUNT:16; /**< \brief [15:0] Reload Count Number (rw) */
+ unsigned int CURCOUNT:16; /**< \brief [31:16] Current Count Number (rh) */
+} Ifx_HSSL_TS_FC_Bits;
+
+/** \brief Target Stream Start Address Register */
+typedef struct _Ifx_HSSL_TSSA_Bits
+{
+ unsigned int reserved_0:5; /**< \brief \internal Reserved */
+ unsigned int ADDR:27; /**< \brief [31:5] Start Address for the Memory Range (rw) */
+} Ifx_HSSL_TSSA_Bits;
+
+/** \brief Target Status Register */
+typedef struct _Ifx_HSSL_TSTAT_Bits
+{
+ unsigned int LASTCC0:5; /**< \brief [4:0] Last Command Code (rh) */
+ unsigned int LASTTT0:3; /**< \brief [7:5] Last Transaction Tag (rh) */
+ unsigned int LASTCC1:5; /**< \brief [12:8] Last Command Code (rh) */
+ unsigned int LASTTT1:3; /**< \brief [15:13] Last Transaction Tag (rh) */
+ unsigned int LASTCC2:5; /**< \brief [20:16] Last Command Code (rh) */
+ unsigned int LASTTT2:3; /**< \brief [23:21] Last Transaction Tag (rh) */
+ unsigned int LASTCC3:5; /**< \brief [28:24] Last Command Code (rh) */
+ unsigned int LASTTT3:3; /**< \brief [31:29] Last Transaction Tag (rh) */
+} Ifx_HSSL_TSTAT_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Hssl_union
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_ACCEN0_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_ACCEN0;
+
+/** \brief Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_ACCEN1_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_ACCEN1;
+
+/** \brief Access Rules Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_AR_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_AR;
+
+/** \brief Access Window End Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_AW_AWEND_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_AW_AWEND;
+
+/** \brief Access Window Start Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_AW_AWSTART_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_AW_AWSTART;
+
+/** \brief Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_CFG_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_CFG;
+
+/** \brief Clock Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_CLC_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_CLC;
+
+/** \brief CRC Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_CRC_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_CRC;
+
+/** \brief Initiator Control Data Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_I_ICON_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_I_ICON;
+
+/** \brief Initiator Read Data Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_I_IRD_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_I_IRD;
+
+/** \brief Initiator Read Write Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_I_IRWA_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_I_IRWA;
+
+/** \brief Initiator Write Data Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_I_IWD_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_I_IWD;
+
+/** \brief Module Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_ID;
+
+/** \brief Initiator Stream Current Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_IS_CA_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_IS_CA;
+
+/** \brief Initiator Stream Frame Count Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_IS_FC_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_IS_FC;
+
+/** \brief Initiator Stream Start Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_ISSA_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_ISSA;
+
+/** \brief Kernel Reset Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_KRST0_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_KRST0;
+
+/** \brief Kernel Reset Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_KRST1_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_KRST1;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_KRSTCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_KRSTCLR;
+
+/** \brief Miscellaneous Flags Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_MFLAGS_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_MFLAGS;
+
+/** \brief Miscellaneous Flags Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_MFLAGSCL_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_MFLAGSCL;
+
+/** \brief Flags Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_MFLAGSEN_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_MFLAGSEN;
+
+/** \brief Miscellaneous Flags Set Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_MFLAGSSET_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_MFLAGSSET;
+
+/** \brief OCDS Control and Status */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_OCS_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_OCS;
+
+/** \brief Request Flags Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_QFLAGS_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_QFLAGS;
+
+/** \brief Stream FIFOs Status Flags Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_SFSFLAGS_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_SFSFLAGS;
+
+/** \brief Target Current Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_T_TCA_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_T_TCA;
+
+/** \brief Target Current Data Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_T_TCD_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_T_TCD;
+
+/** \brief Target ID Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_TIDADD_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_TIDADD;
+
+/** \brief Target Stream Current Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_TS_CA_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_TS_CA;
+
+/** \brief Target Stream Frame Count Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_TS_FC_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_TS_FC;
+
+/** \brief Target Stream Start Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_TSSA_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_TSSA;
+
+/** \brief Target Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_HSSL_TSTAT_Bits B; /**< \brief Bitfield access */
+} Ifx_HSSL_TSTAT;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Hssl_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L1
+ * \{ */
+
+/** \brief Access window */
+typedef volatile struct _Ifx_HSSL_AW
+{
+ Ifx_HSSL_AW_AWSTART AWSTART; /**< \brief 0, Access Window Start Register */
+ Ifx_HSSL_AW_AWEND AWEND; /**< \brief 4, Access Window End Register */
+} Ifx_HSSL_AW;
+
+/** \brief Initiator */
+typedef volatile struct _Ifx_HSSL_I
+{
+ Ifx_HSSL_I_IWD IWD; /**< \brief 0, Initiator Write Data Register */
+ Ifx_HSSL_I_ICON ICON; /**< \brief 4, Initiator Control Data Register */
+ Ifx_HSSL_I_IRWA IRWA; /**< \brief 8, Initiator Read Write Address Register */
+ Ifx_HSSL_I_IRD IRD; /**< \brief C, Initiator Read Data Register */
+} Ifx_HSSL_I;
+
+/** \brief Initiator stream */
+typedef volatile struct _Ifx_HSSL_IS
+{
+ Ifx_HSSL_ISSA SA[2]; /**< \brief 0, Initiator Stream Start Address Register */
+ Ifx_HSSL_IS_CA CA; /**< \brief 8, Initiator Stream Current Address Register */
+ Ifx_HSSL_IS_FC FC; /**< \brief C, Initiator Stream Frame Count Register */
+} Ifx_HSSL_IS;
+
+/** \brief target */
+typedef volatile struct _Ifx_HSSL_T
+{
+ Ifx_HSSL_T_TCD TCD; /**< \brief 0, Target Current Data Register */
+ Ifx_HSSL_T_TCA TCA; /**< \brief 4, Target Current Address Register */
+} Ifx_HSSL_T;
+
+/** \brief Target stream */
+typedef volatile struct _Ifx_HSSL_TS
+{
+ Ifx_HSSL_TSSA SA[2]; /**< \brief 0, Target Stream Start Address Register */
+ Ifx_HSSL_TS_CA CA; /**< \brief 8, Target Stream Current Address Register */
+ Ifx_HSSL_TS_FC FC; /**< \brief C, Target Stream Frame Count Register */
+} Ifx_HSSL_TS;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Hssl_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief HSSL object */
+typedef volatile struct _Ifx_HSSL
+{
+ Ifx_HSSL_CLC CLC; /**< \brief 0, Clock Control Register */
+ unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
+ Ifx_HSSL_ID ID; /**< \brief 8, Module Identification Register */
+ Ifx_HSSL_CRC CRC; /**< \brief C, CRC Control Register */
+ Ifx_HSSL_CFG CFG; /**< \brief 10, Configuration Register */
+ Ifx_HSSL_QFLAGS QFLAGS; /**< \brief 14, Request Flags Register */
+ Ifx_HSSL_MFLAGS MFLAGS; /**< \brief 18, Miscellaneous Flags Register */
+ Ifx_HSSL_MFLAGSSET MFLAGSSET; /**< \brief 1C, Miscellaneous Flags Set Register */
+ Ifx_HSSL_MFLAGSCL MFLAGSCL; /**< \brief 20, Miscellaneous Flags Clear Register */
+ Ifx_HSSL_MFLAGSEN MFLAGSEN; /**< \brief 24, Flags Enable Register */
+ Ifx_HSSL_SFSFLAGS SFSFLAGS; /**< \brief 28, Stream FIFOs Status Flags Register */
+ unsigned char reserved_2C[4]; /**< \brief 2C, \internal Reserved */
+ Ifx_HSSL_I I[4]; /**< \brief 30, Initiator */
+ Ifx_HSSL_T T[4]; /**< \brief 70, target */
+ Ifx_HSSL_TSTAT TSTAT; /**< \brief 90, Target Status Register */
+ Ifx_HSSL_TIDADD TIDADD; /**< \brief 94, Target ID Address Register */
+ unsigned char reserved_98[8]; /**< \brief 98, \internal Reserved */
+ Ifx_HSSL_IS IS; /**< \brief A0, Initiator stream */
+ Ifx_HSSL_TS TS; /**< \brief B0, Target stream */
+ Ifx_HSSL_AW AW[4]; /**< \brief C0, Access window */
+ Ifx_HSSL_AR AR; /**< \brief E0, Access Rules Register */
+ unsigned char reserved_E4[4]; /**< \brief E4, \internal Reserved */
+ Ifx_HSSL_OCS OCS; /**< \brief E8, OCDS Control and Status */
+ Ifx_HSSL_KRSTCLR KRSTCLR; /**< \brief EC, Kernel Reset Status Clear Register */
+ Ifx_HSSL_KRST1 KRST1; /**< \brief F0, Kernel Reset Register 1 */
+ Ifx_HSSL_KRST0 KRST0; /**< \brief F4, Kernel Reset Register 0 */
+ Ifx_HSSL_ACCEN1 ACCEN1; /**< \brief F8, Access Enable Register 1 */
+ Ifx_HSSL_ACCEN0 ACCEN0; /**< \brief FC, Access Enable Register 0 */
+ unsigned char reserved_100[768]; /**< \brief 100, \internal Reserved */
+} Ifx_HSSL;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXHSSL_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxI2c_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxI2c_bf.h
new file mode 100644
index 0000000..2158625
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxI2c_bf.h
@@ -0,0 +1,1359 @@
+/**
+ * \file IfxI2c_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_I2c_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_I2c
+ *
+ */
+#ifndef IFXI2C_BF_H
+#define IFXI2C_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_I2c_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN0 */
+#define IFX_I2C_ACCEN0_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN0 */
+#define IFX_I2C_ACCEN0_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN0 */
+#define IFX_I2C_ACCEN0_EN0_OFF (0u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN10 */
+#define IFX_I2C_ACCEN0_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN10 */
+#define IFX_I2C_ACCEN0_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN10 */
+#define IFX_I2C_ACCEN0_EN10_OFF (10u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN11 */
+#define IFX_I2C_ACCEN0_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN11 */
+#define IFX_I2C_ACCEN0_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN11 */
+#define IFX_I2C_ACCEN0_EN11_OFF (11u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN12 */
+#define IFX_I2C_ACCEN0_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN12 */
+#define IFX_I2C_ACCEN0_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN12 */
+#define IFX_I2C_ACCEN0_EN12_OFF (12u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN13 */
+#define IFX_I2C_ACCEN0_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN13 */
+#define IFX_I2C_ACCEN0_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN13 */
+#define IFX_I2C_ACCEN0_EN13_OFF (13u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN14 */
+#define IFX_I2C_ACCEN0_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN14 */
+#define IFX_I2C_ACCEN0_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN14 */
+#define IFX_I2C_ACCEN0_EN14_OFF (14u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN15 */
+#define IFX_I2C_ACCEN0_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN15 */
+#define IFX_I2C_ACCEN0_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN15 */
+#define IFX_I2C_ACCEN0_EN15_OFF (15u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN16 */
+#define IFX_I2C_ACCEN0_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN16 */
+#define IFX_I2C_ACCEN0_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN16 */
+#define IFX_I2C_ACCEN0_EN16_OFF (16u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN17 */
+#define IFX_I2C_ACCEN0_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN17 */
+#define IFX_I2C_ACCEN0_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN17 */
+#define IFX_I2C_ACCEN0_EN17_OFF (17u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN18 */
+#define IFX_I2C_ACCEN0_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN18 */
+#define IFX_I2C_ACCEN0_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN18 */
+#define IFX_I2C_ACCEN0_EN18_OFF (18u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN19 */
+#define IFX_I2C_ACCEN0_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN19 */
+#define IFX_I2C_ACCEN0_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN19 */
+#define IFX_I2C_ACCEN0_EN19_OFF (19u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN1 */
+#define IFX_I2C_ACCEN0_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN1 */
+#define IFX_I2C_ACCEN0_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN1 */
+#define IFX_I2C_ACCEN0_EN1_OFF (1u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN20 */
+#define IFX_I2C_ACCEN0_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN20 */
+#define IFX_I2C_ACCEN0_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN20 */
+#define IFX_I2C_ACCEN0_EN20_OFF (20u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN21 */
+#define IFX_I2C_ACCEN0_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN21 */
+#define IFX_I2C_ACCEN0_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN21 */
+#define IFX_I2C_ACCEN0_EN21_OFF (21u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN22 */
+#define IFX_I2C_ACCEN0_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN22 */
+#define IFX_I2C_ACCEN0_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN22 */
+#define IFX_I2C_ACCEN0_EN22_OFF (22u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN23 */
+#define IFX_I2C_ACCEN0_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN23 */
+#define IFX_I2C_ACCEN0_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN23 */
+#define IFX_I2C_ACCEN0_EN23_OFF (23u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN24 */
+#define IFX_I2C_ACCEN0_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN24 */
+#define IFX_I2C_ACCEN0_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN24 */
+#define IFX_I2C_ACCEN0_EN24_OFF (24u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN25 */
+#define IFX_I2C_ACCEN0_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN25 */
+#define IFX_I2C_ACCEN0_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN25 */
+#define IFX_I2C_ACCEN0_EN25_OFF (25u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN26 */
+#define IFX_I2C_ACCEN0_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN26 */
+#define IFX_I2C_ACCEN0_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN26 */
+#define IFX_I2C_ACCEN0_EN26_OFF (26u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN27 */
+#define IFX_I2C_ACCEN0_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN27 */
+#define IFX_I2C_ACCEN0_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN27 */
+#define IFX_I2C_ACCEN0_EN27_OFF (27u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN28 */
+#define IFX_I2C_ACCEN0_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN28 */
+#define IFX_I2C_ACCEN0_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN28 */
+#define IFX_I2C_ACCEN0_EN28_OFF (28u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN29 */
+#define IFX_I2C_ACCEN0_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN29 */
+#define IFX_I2C_ACCEN0_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN29 */
+#define IFX_I2C_ACCEN0_EN29_OFF (29u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN2 */
+#define IFX_I2C_ACCEN0_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN2 */
+#define IFX_I2C_ACCEN0_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN2 */
+#define IFX_I2C_ACCEN0_EN2_OFF (2u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN30 */
+#define IFX_I2C_ACCEN0_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN30 */
+#define IFX_I2C_ACCEN0_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN30 */
+#define IFX_I2C_ACCEN0_EN30_OFF (30u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN31 */
+#define IFX_I2C_ACCEN0_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN31 */
+#define IFX_I2C_ACCEN0_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN31 */
+#define IFX_I2C_ACCEN0_EN31_OFF (31u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN3 */
+#define IFX_I2C_ACCEN0_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN3 */
+#define IFX_I2C_ACCEN0_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN3 */
+#define IFX_I2C_ACCEN0_EN3_OFF (3u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN4 */
+#define IFX_I2C_ACCEN0_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN4 */
+#define IFX_I2C_ACCEN0_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN4 */
+#define IFX_I2C_ACCEN0_EN4_OFF (4u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN5 */
+#define IFX_I2C_ACCEN0_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN5 */
+#define IFX_I2C_ACCEN0_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN5 */
+#define IFX_I2C_ACCEN0_EN5_OFF (5u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN6 */
+#define IFX_I2C_ACCEN0_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN6 */
+#define IFX_I2C_ACCEN0_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN6 */
+#define IFX_I2C_ACCEN0_EN6_OFF (6u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN7 */
+#define IFX_I2C_ACCEN0_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN7 */
+#define IFX_I2C_ACCEN0_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN7 */
+#define IFX_I2C_ACCEN0_EN7_OFF (7u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN8 */
+#define IFX_I2C_ACCEN0_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN8 */
+#define IFX_I2C_ACCEN0_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN8 */
+#define IFX_I2C_ACCEN0_EN8_OFF (8u)
+
+/** \brief Length for Ifx_I2C_ACCEN0_Bits.EN9 */
+#define IFX_I2C_ACCEN0_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ACCEN0_Bits.EN9 */
+#define IFX_I2C_ACCEN0_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ACCEN0_Bits.EN9 */
+#define IFX_I2C_ACCEN0_EN9_OFF (9u)
+
+/** \brief Length for Ifx_I2C_ADDRCFG_Bits.ADR */
+#define IFX_I2C_ADDRCFG_ADR_LEN (10u)
+
+/** \brief Mask for Ifx_I2C_ADDRCFG_Bits.ADR */
+#define IFX_I2C_ADDRCFG_ADR_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_I2C_ADDRCFG_Bits.ADR */
+#define IFX_I2C_ADDRCFG_ADR_OFF (0u)
+
+/** \brief Length for Ifx_I2C_ADDRCFG_Bits.GCE */
+#define IFX_I2C_ADDRCFG_GCE_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ADDRCFG_Bits.GCE */
+#define IFX_I2C_ADDRCFG_GCE_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ADDRCFG_Bits.GCE */
+#define IFX_I2C_ADDRCFG_GCE_OFF (17u)
+
+/** \brief Length for Ifx_I2C_ADDRCFG_Bits.MCE */
+#define IFX_I2C_ADDRCFG_MCE_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ADDRCFG_Bits.MCE */
+#define IFX_I2C_ADDRCFG_MCE_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ADDRCFG_Bits.MCE */
+#define IFX_I2C_ADDRCFG_MCE_OFF (18u)
+
+/** \brief Length for Ifx_I2C_ADDRCFG_Bits.MnS */
+#define IFX_I2C_ADDRCFG_MNS_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ADDRCFG_Bits.MnS */
+#define IFX_I2C_ADDRCFG_MNS_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ADDRCFG_Bits.MnS */
+#define IFX_I2C_ADDRCFG_MNS_OFF (19u)
+
+/** \brief Length for Ifx_I2C_ADDRCFG_Bits.SONA */
+#define IFX_I2C_ADDRCFG_SONA_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ADDRCFG_Bits.SONA */
+#define IFX_I2C_ADDRCFG_SONA_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ADDRCFG_Bits.SONA */
+#define IFX_I2C_ADDRCFG_SONA_OFF (20u)
+
+/** \brief Length for Ifx_I2C_ADDRCFG_Bits.SOPE */
+#define IFX_I2C_ADDRCFG_SOPE_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ADDRCFG_Bits.SOPE */
+#define IFX_I2C_ADDRCFG_SOPE_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ADDRCFG_Bits.SOPE */
+#define IFX_I2C_ADDRCFG_SOPE_OFF (21u)
+
+/** \brief Length for Ifx_I2C_ADDRCFG_Bits.TBAM */
+#define IFX_I2C_ADDRCFG_TBAM_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ADDRCFG_Bits.TBAM */
+#define IFX_I2C_ADDRCFG_TBAM_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ADDRCFG_Bits.TBAM */
+#define IFX_I2C_ADDRCFG_TBAM_OFF (16u)
+
+/** \brief Length for Ifx_I2C_BUSSTAT_Bits.BS */
+#define IFX_I2C_BUSSTAT_BS_LEN (2u)
+
+/** \brief Mask for Ifx_I2C_BUSSTAT_Bits.BS */
+#define IFX_I2C_BUSSTAT_BS_MSK (0x3u)
+
+/** \brief Offset for Ifx_I2C_BUSSTAT_Bits.BS */
+#define IFX_I2C_BUSSTAT_BS_OFF (0u)
+
+/** \brief Length for Ifx_I2C_BUSSTAT_Bits.RnW */
+#define IFX_I2C_BUSSTAT_RNW_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_BUSSTAT_Bits.RnW */
+#define IFX_I2C_BUSSTAT_RNW_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_BUSSTAT_Bits.RnW */
+#define IFX_I2C_BUSSTAT_RNW_OFF (2u)
+
+/** \brief Length for Ifx_I2C_CLC1_Bits.DISR */
+#define IFX_I2C_CLC1_DISR_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_CLC1_Bits.DISR */
+#define IFX_I2C_CLC1_DISR_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_CLC1_Bits.DISR */
+#define IFX_I2C_CLC1_DISR_OFF (0u)
+
+/** \brief Length for Ifx_I2C_CLC1_Bits.DISS */
+#define IFX_I2C_CLC1_DISS_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_CLC1_Bits.DISS */
+#define IFX_I2C_CLC1_DISS_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_CLC1_Bits.DISS */
+#define IFX_I2C_CLC1_DISS_OFF (1u)
+
+/** \brief Length for Ifx_I2C_CLC1_Bits.EDIS */
+#define IFX_I2C_CLC1_EDIS_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_CLC1_Bits.EDIS */
+#define IFX_I2C_CLC1_EDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_CLC1_Bits.EDIS */
+#define IFX_I2C_CLC1_EDIS_OFF (3u)
+
+/** \brief Length for Ifx_I2C_CLC1_Bits.FSOE */
+#define IFX_I2C_CLC1_FSOE_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_CLC1_Bits.FSOE */
+#define IFX_I2C_CLC1_FSOE_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_CLC1_Bits.FSOE */
+#define IFX_I2C_CLC1_FSOE_OFF (5u)
+
+/** \brief Length for Ifx_I2C_CLC1_Bits.RMC */
+#define IFX_I2C_CLC1_RMC_LEN (8u)
+
+/** \brief Mask for Ifx_I2C_CLC1_Bits.RMC */
+#define IFX_I2C_CLC1_RMC_MSK (0xffu)
+
+/** \brief Offset for Ifx_I2C_CLC1_Bits.RMC */
+#define IFX_I2C_CLC1_RMC_OFF (8u)
+
+/** \brief Length for Ifx_I2C_CLC1_Bits.SBWE */
+#define IFX_I2C_CLC1_SBWE_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_CLC1_Bits.SBWE */
+#define IFX_I2C_CLC1_SBWE_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_CLC1_Bits.SBWE */
+#define IFX_I2C_CLC1_SBWE_OFF (4u)
+
+/** \brief Length for Ifx_I2C_CLC1_Bits.SPEN */
+#define IFX_I2C_CLC1_SPEN_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_CLC1_Bits.SPEN */
+#define IFX_I2C_CLC1_SPEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_CLC1_Bits.SPEN */
+#define IFX_I2C_CLC1_SPEN_OFF (2u)
+
+/** \brief Length for Ifx_I2C_CLC_Bits.DISR */
+#define IFX_I2C_CLC_DISR_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_CLC_Bits.DISR */
+#define IFX_I2C_CLC_DISR_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_CLC_Bits.DISR */
+#define IFX_I2C_CLC_DISR_OFF (0u)
+
+/** \brief Length for Ifx_I2C_CLC_Bits.DISS */
+#define IFX_I2C_CLC_DISS_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_CLC_Bits.DISS */
+#define IFX_I2C_CLC_DISS_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_CLC_Bits.DISS */
+#define IFX_I2C_CLC_DISS_OFF (1u)
+
+/** \brief Length for Ifx_I2C_ENDDCTRL_Bits.SETEND */
+#define IFX_I2C_ENDDCTRL_SETEND_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ENDDCTRL_Bits.SETEND */
+#define IFX_I2C_ENDDCTRL_SETEND_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ENDDCTRL_Bits.SETEND */
+#define IFX_I2C_ENDDCTRL_SETEND_OFF (1u)
+
+/** \brief Length for Ifx_I2C_ENDDCTRL_Bits.SETRSC */
+#define IFX_I2C_ENDDCTRL_SETRSC_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ENDDCTRL_Bits.SETRSC */
+#define IFX_I2C_ENDDCTRL_SETRSC_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ENDDCTRL_Bits.SETRSC */
+#define IFX_I2C_ENDDCTRL_SETRSC_OFF (0u)
+
+/** \brief Length for Ifx_I2C_ERRIRQSC_Bits.RXF_OFL */
+#define IFX_I2C_ERRIRQSC_RXF_OFL_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ERRIRQSC_Bits.RXF_OFL */
+#define IFX_I2C_ERRIRQSC_RXF_OFL_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ERRIRQSC_Bits.RXF_OFL */
+#define IFX_I2C_ERRIRQSC_RXF_OFL_OFF (1u)
+
+/** \brief Length for Ifx_I2C_ERRIRQSC_Bits.RXF_UFL */
+#define IFX_I2C_ERRIRQSC_RXF_UFL_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ERRIRQSC_Bits.RXF_UFL */
+#define IFX_I2C_ERRIRQSC_RXF_UFL_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ERRIRQSC_Bits.RXF_UFL */
+#define IFX_I2C_ERRIRQSC_RXF_UFL_OFF (0u)
+
+/** \brief Length for Ifx_I2C_ERRIRQSC_Bits.TXF_OFL */
+#define IFX_I2C_ERRIRQSC_TXF_OFL_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ERRIRQSC_Bits.TXF_OFL */
+#define IFX_I2C_ERRIRQSC_TXF_OFL_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ERRIRQSC_Bits.TXF_OFL */
+#define IFX_I2C_ERRIRQSC_TXF_OFL_OFF (3u)
+
+/** \brief Length for Ifx_I2C_ERRIRQSC_Bits.TXF_UFL */
+#define IFX_I2C_ERRIRQSC_TXF_UFL_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ERRIRQSC_Bits.TXF_UFL */
+#define IFX_I2C_ERRIRQSC_TXF_UFL_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ERRIRQSC_Bits.TXF_UFL */
+#define IFX_I2C_ERRIRQSC_TXF_UFL_OFF (2u)
+
+/** \brief Length for Ifx_I2C_ERRIRQSM_Bits.RXF_OFL */
+#define IFX_I2C_ERRIRQSM_RXF_OFL_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ERRIRQSM_Bits.RXF_OFL */
+#define IFX_I2C_ERRIRQSM_RXF_OFL_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ERRIRQSM_Bits.RXF_OFL */
+#define IFX_I2C_ERRIRQSM_RXF_OFL_OFF (1u)
+
+/** \brief Length for Ifx_I2C_ERRIRQSM_Bits.RXF_UFL */
+#define IFX_I2C_ERRIRQSM_RXF_UFL_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ERRIRQSM_Bits.RXF_UFL */
+#define IFX_I2C_ERRIRQSM_RXF_UFL_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ERRIRQSM_Bits.RXF_UFL */
+#define IFX_I2C_ERRIRQSM_RXF_UFL_OFF (0u)
+
+/** \brief Length for Ifx_I2C_ERRIRQSM_Bits.TXF_OFL */
+#define IFX_I2C_ERRIRQSM_TXF_OFL_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ERRIRQSM_Bits.TXF_OFL */
+#define IFX_I2C_ERRIRQSM_TXF_OFL_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ERRIRQSM_Bits.TXF_OFL */
+#define IFX_I2C_ERRIRQSM_TXF_OFL_OFF (3u)
+
+/** \brief Length for Ifx_I2C_ERRIRQSM_Bits.TXF_UFL */
+#define IFX_I2C_ERRIRQSM_TXF_UFL_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ERRIRQSM_Bits.TXF_UFL */
+#define IFX_I2C_ERRIRQSM_TXF_UFL_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ERRIRQSM_Bits.TXF_UFL */
+#define IFX_I2C_ERRIRQSM_TXF_UFL_OFF (2u)
+
+/** \brief Length for Ifx_I2C_ERRIRQSS_Bits.RXF_OFL */
+#define IFX_I2C_ERRIRQSS_RXF_OFL_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ERRIRQSS_Bits.RXF_OFL */
+#define IFX_I2C_ERRIRQSS_RXF_OFL_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ERRIRQSS_Bits.RXF_OFL */
+#define IFX_I2C_ERRIRQSS_RXF_OFL_OFF (1u)
+
+/** \brief Length for Ifx_I2C_ERRIRQSS_Bits.RXF_UFL */
+#define IFX_I2C_ERRIRQSS_RXF_UFL_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ERRIRQSS_Bits.RXF_UFL */
+#define IFX_I2C_ERRIRQSS_RXF_UFL_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ERRIRQSS_Bits.RXF_UFL */
+#define IFX_I2C_ERRIRQSS_RXF_UFL_OFF (0u)
+
+/** \brief Length for Ifx_I2C_ERRIRQSS_Bits.TXF_OFL */
+#define IFX_I2C_ERRIRQSS_TXF_OFL_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ERRIRQSS_Bits.TXF_OFL */
+#define IFX_I2C_ERRIRQSS_TXF_OFL_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ERRIRQSS_Bits.TXF_OFL */
+#define IFX_I2C_ERRIRQSS_TXF_OFL_OFF (3u)
+
+/** \brief Length for Ifx_I2C_ERRIRQSS_Bits.TXF_UFL */
+#define IFX_I2C_ERRIRQSS_TXF_UFL_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ERRIRQSS_Bits.TXF_UFL */
+#define IFX_I2C_ERRIRQSS_TXF_UFL_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ERRIRQSS_Bits.TXF_UFL */
+#define IFX_I2C_ERRIRQSS_TXF_UFL_OFF (2u)
+
+/** \brief Length for Ifx_I2C_FDIVCFG_Bits.DEC */
+#define IFX_I2C_FDIVCFG_DEC_LEN (11u)
+
+/** \brief Mask for Ifx_I2C_FDIVCFG_Bits.DEC */
+#define IFX_I2C_FDIVCFG_DEC_MSK (0x7ffu)
+
+/** \brief Offset for Ifx_I2C_FDIVCFG_Bits.DEC */
+#define IFX_I2C_FDIVCFG_DEC_OFF (0u)
+
+/** \brief Length for Ifx_I2C_FDIVCFG_Bits.INC */
+#define IFX_I2C_FDIVCFG_INC_LEN (8u)
+
+/** \brief Mask for Ifx_I2C_FDIVCFG_Bits.INC */
+#define IFX_I2C_FDIVCFG_INC_MSK (0xffu)
+
+/** \brief Offset for Ifx_I2C_FDIVCFG_Bits.INC */
+#define IFX_I2C_FDIVCFG_INC_OFF (16u)
+
+/** \brief Length for Ifx_I2C_FDIVHIGHCFG_Bits.DEC */
+#define IFX_I2C_FDIVHIGHCFG_DEC_LEN (11u)
+
+/** \brief Mask for Ifx_I2C_FDIVHIGHCFG_Bits.DEC */
+#define IFX_I2C_FDIVHIGHCFG_DEC_MSK (0x7ffu)
+
+/** \brief Offset for Ifx_I2C_FDIVHIGHCFG_Bits.DEC */
+#define IFX_I2C_FDIVHIGHCFG_DEC_OFF (0u)
+
+/** \brief Length for Ifx_I2C_FDIVHIGHCFG_Bits.INC */
+#define IFX_I2C_FDIVHIGHCFG_INC_LEN (8u)
+
+/** \brief Mask for Ifx_I2C_FDIVHIGHCFG_Bits.INC */
+#define IFX_I2C_FDIVHIGHCFG_INC_MSK (0xffu)
+
+/** \brief Offset for Ifx_I2C_FDIVHIGHCFG_Bits.INC */
+#define IFX_I2C_FDIVHIGHCFG_INC_OFF (16u)
+
+/** \brief Length for Ifx_I2C_FFSSTAT_Bits.FFS */
+#define IFX_I2C_FFSSTAT_FFS_LEN (6u)
+
+/** \brief Mask for Ifx_I2C_FFSSTAT_Bits.FFS */
+#define IFX_I2C_FFSSTAT_FFS_MSK (0x3fu)
+
+/** \brief Offset for Ifx_I2C_FFSSTAT_Bits.FFS */
+#define IFX_I2C_FFSSTAT_FFS_OFF (0u)
+
+/** \brief Length for Ifx_I2C_FIFOCFG_Bits.RXBS */
+#define IFX_I2C_FIFOCFG_RXBS_LEN (2u)
+
+/** \brief Mask for Ifx_I2C_FIFOCFG_Bits.RXBS */
+#define IFX_I2C_FIFOCFG_RXBS_MSK (0x3u)
+
+/** \brief Offset for Ifx_I2C_FIFOCFG_Bits.RXBS */
+#define IFX_I2C_FIFOCFG_RXBS_OFF (0u)
+
+/** \brief Length for Ifx_I2C_FIFOCFG_Bits.RXFA */
+#define IFX_I2C_FIFOCFG_RXFA_LEN (2u)
+
+/** \brief Mask for Ifx_I2C_FIFOCFG_Bits.RXFA */
+#define IFX_I2C_FIFOCFG_RXFA_MSK (0x3u)
+
+/** \brief Offset for Ifx_I2C_FIFOCFG_Bits.RXFA */
+#define IFX_I2C_FIFOCFG_RXFA_OFF (8u)
+
+/** \brief Length for Ifx_I2C_FIFOCFG_Bits.RXFC */
+#define IFX_I2C_FIFOCFG_RXFC_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_FIFOCFG_Bits.RXFC */
+#define IFX_I2C_FIFOCFG_RXFC_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_FIFOCFG_Bits.RXFC */
+#define IFX_I2C_FIFOCFG_RXFC_OFF (16u)
+
+/** \brief Length for Ifx_I2C_FIFOCFG_Bits.TXBS */
+#define IFX_I2C_FIFOCFG_TXBS_LEN (2u)
+
+/** \brief Mask for Ifx_I2C_FIFOCFG_Bits.TXBS */
+#define IFX_I2C_FIFOCFG_TXBS_MSK (0x3u)
+
+/** \brief Offset for Ifx_I2C_FIFOCFG_Bits.TXBS */
+#define IFX_I2C_FIFOCFG_TXBS_OFF (4u)
+
+/** \brief Length for Ifx_I2C_FIFOCFG_Bits.TXFA */
+#define IFX_I2C_FIFOCFG_TXFA_LEN (2u)
+
+/** \brief Mask for Ifx_I2C_FIFOCFG_Bits.TXFA */
+#define IFX_I2C_FIFOCFG_TXFA_MSK (0x3u)
+
+/** \brief Offset for Ifx_I2C_FIFOCFG_Bits.TXFA */
+#define IFX_I2C_FIFOCFG_TXFA_OFF (12u)
+
+/** \brief Length for Ifx_I2C_FIFOCFG_Bits.TXFC */
+#define IFX_I2C_FIFOCFG_TXFC_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_FIFOCFG_Bits.TXFC */
+#define IFX_I2C_FIFOCFG_TXFC_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_FIFOCFG_Bits.TXFC */
+#define IFX_I2C_FIFOCFG_TXFC_OFF (17u)
+
+/** \brief Length for Ifx_I2C_GPCTL_Bits.PISEL */
+#define IFX_I2C_GPCTL_PISEL_LEN (3u)
+
+/** \brief Mask for Ifx_I2C_GPCTL_Bits.PISEL */
+#define IFX_I2C_GPCTL_PISEL_MSK (0x7u)
+
+/** \brief Offset for Ifx_I2C_GPCTL_Bits.PISEL */
+#define IFX_I2C_GPCTL_PISEL_OFF (0u)
+
+/** \brief Length for Ifx_I2C_ICR_Bits.BREQ_INT */
+#define IFX_I2C_ICR_BREQ_INT_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ICR_Bits.BREQ_INT */
+#define IFX_I2C_ICR_BREQ_INT_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ICR_Bits.BREQ_INT */
+#define IFX_I2C_ICR_BREQ_INT_OFF (3u)
+
+/** \brief Length for Ifx_I2C_ICR_Bits.LBREQ_INT */
+#define IFX_I2C_ICR_LBREQ_INT_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ICR_Bits.LBREQ_INT */
+#define IFX_I2C_ICR_LBREQ_INT_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ICR_Bits.LBREQ_INT */
+#define IFX_I2C_ICR_LBREQ_INT_OFF (2u)
+
+/** \brief Length for Ifx_I2C_ICR_Bits.LSREQ_INT */
+#define IFX_I2C_ICR_LSREQ_INT_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ICR_Bits.LSREQ_INT */
+#define IFX_I2C_ICR_LSREQ_INT_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ICR_Bits.LSREQ_INT */
+#define IFX_I2C_ICR_LSREQ_INT_OFF (0u)
+
+/** \brief Length for Ifx_I2C_ICR_Bits.SREQ_INT */
+#define IFX_I2C_ICR_SREQ_INT_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ICR_Bits.SREQ_INT */
+#define IFX_I2C_ICR_SREQ_INT_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ICR_Bits.SREQ_INT */
+#define IFX_I2C_ICR_SREQ_INT_OFF (1u)
+
+/** \brief Length for Ifx_I2C_ID_Bits.MODNUMBER */
+#define IFX_I2C_ID_MODNUMBER_LEN (8u)
+
+/** \brief Mask for Ifx_I2C_ID_Bits.MODNUMBER */
+#define IFX_I2C_ID_MODNUMBER_MSK (0xffu)
+
+/** \brief Offset for Ifx_I2C_ID_Bits.MODNUMBER */
+#define IFX_I2C_ID_MODNUMBER_OFF (8u)
+
+/** \brief Length for Ifx_I2C_ID_Bits.MODREV */
+#define IFX_I2C_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_I2C_ID_Bits.MODREV */
+#define IFX_I2C_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_I2C_ID_Bits.MODREV */
+#define IFX_I2C_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_I2C_IMSC_Bits.BREQ_INT */
+#define IFX_I2C_IMSC_BREQ_INT_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_IMSC_Bits.BREQ_INT */
+#define IFX_I2C_IMSC_BREQ_INT_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_IMSC_Bits.BREQ_INT */
+#define IFX_I2C_IMSC_BREQ_INT_OFF (3u)
+
+/** \brief Length for Ifx_I2C_IMSC_Bits.I2C_ERR_INT */
+#define IFX_I2C_IMSC_I2C_ERR_INT_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_IMSC_Bits.I2C_ERR_INT */
+#define IFX_I2C_IMSC_I2C_ERR_INT_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_IMSC_Bits.I2C_ERR_INT */
+#define IFX_I2C_IMSC_I2C_ERR_INT_OFF (4u)
+
+/** \brief Length for Ifx_I2C_IMSC_Bits.I2C_P_INT */
+#define IFX_I2C_IMSC_I2C_P_INT_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_IMSC_Bits.I2C_P_INT */
+#define IFX_I2C_IMSC_I2C_P_INT_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_IMSC_Bits.I2C_P_INT */
+#define IFX_I2C_IMSC_I2C_P_INT_OFF (5u)
+
+/** \brief Length for Ifx_I2C_IMSC_Bits.LBREQ_INT */
+#define IFX_I2C_IMSC_LBREQ_INT_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_IMSC_Bits.LBREQ_INT */
+#define IFX_I2C_IMSC_LBREQ_INT_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_IMSC_Bits.LBREQ_INT */
+#define IFX_I2C_IMSC_LBREQ_INT_OFF (2u)
+
+/** \brief Length for Ifx_I2C_IMSC_Bits.LSREQ_INT */
+#define IFX_I2C_IMSC_LSREQ_INT_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_IMSC_Bits.LSREQ_INT */
+#define IFX_I2C_IMSC_LSREQ_INT_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_IMSC_Bits.LSREQ_INT */
+#define IFX_I2C_IMSC_LSREQ_INT_OFF (0u)
+
+/** \brief Length for Ifx_I2C_IMSC_Bits.SREQ_INT */
+#define IFX_I2C_IMSC_SREQ_INT_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_IMSC_Bits.SREQ_INT */
+#define IFX_I2C_IMSC_SREQ_INT_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_IMSC_Bits.SREQ_INT */
+#define IFX_I2C_IMSC_SREQ_INT_OFF (1u)
+
+/** \brief Length for Ifx_I2C_ISR_Bits.BREQ_INT */
+#define IFX_I2C_ISR_BREQ_INT_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ISR_Bits.BREQ_INT */
+#define IFX_I2C_ISR_BREQ_INT_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ISR_Bits.BREQ_INT */
+#define IFX_I2C_ISR_BREQ_INT_OFF (3u)
+
+/** \brief Length for Ifx_I2C_ISR_Bits.I2C_ERR_INT */
+#define IFX_I2C_ISR_I2C_ERR_INT_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ISR_Bits.I2C_ERR_INT */
+#define IFX_I2C_ISR_I2C_ERR_INT_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ISR_Bits.I2C_ERR_INT */
+#define IFX_I2C_ISR_I2C_ERR_INT_OFF (4u)
+
+/** \brief Length for Ifx_I2C_ISR_Bits.I2C_P_INT */
+#define IFX_I2C_ISR_I2C_P_INT_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ISR_Bits.I2C_P_INT */
+#define IFX_I2C_ISR_I2C_P_INT_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ISR_Bits.I2C_P_INT */
+#define IFX_I2C_ISR_I2C_P_INT_OFF (5u)
+
+/** \brief Length for Ifx_I2C_ISR_Bits.LBREQ_INT */
+#define IFX_I2C_ISR_LBREQ_INT_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ISR_Bits.LBREQ_INT */
+#define IFX_I2C_ISR_LBREQ_INT_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ISR_Bits.LBREQ_INT */
+#define IFX_I2C_ISR_LBREQ_INT_OFF (2u)
+
+/** \brief Length for Ifx_I2C_ISR_Bits.LSREQ_INT */
+#define IFX_I2C_ISR_LSREQ_INT_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ISR_Bits.LSREQ_INT */
+#define IFX_I2C_ISR_LSREQ_INT_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ISR_Bits.LSREQ_INT */
+#define IFX_I2C_ISR_LSREQ_INT_OFF (0u)
+
+/** \brief Length for Ifx_I2C_ISR_Bits.SREQ_INT */
+#define IFX_I2C_ISR_SREQ_INT_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_ISR_Bits.SREQ_INT */
+#define IFX_I2C_ISR_SREQ_INT_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_ISR_Bits.SREQ_INT */
+#define IFX_I2C_ISR_SREQ_INT_OFF (1u)
+
+/** \brief Length for Ifx_I2C_KRST0_Bits.RST */
+#define IFX_I2C_KRST0_RST_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_KRST0_Bits.RST */
+#define IFX_I2C_KRST0_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_KRST0_Bits.RST */
+#define IFX_I2C_KRST0_RST_OFF (0u)
+
+/** \brief Length for Ifx_I2C_KRST0_Bits.RSTSTAT */
+#define IFX_I2C_KRST0_RSTSTAT_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_KRST0_Bits.RSTSTAT */
+#define IFX_I2C_KRST0_RSTSTAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_KRST0_Bits.RSTSTAT */
+#define IFX_I2C_KRST0_RSTSTAT_OFF (1u)
+
+/** \brief Length for Ifx_I2C_KRST1_Bits.RST */
+#define IFX_I2C_KRST1_RST_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_KRST1_Bits.RST */
+#define IFX_I2C_KRST1_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_KRST1_Bits.RST */
+#define IFX_I2C_KRST1_RST_OFF (0u)
+
+/** \brief Length for Ifx_I2C_KRSTCLR_Bits.CLR */
+#define IFX_I2C_KRSTCLR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_KRSTCLR_Bits.CLR */
+#define IFX_I2C_KRSTCLR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_KRSTCLR_Bits.CLR */
+#define IFX_I2C_KRSTCLR_CLR_OFF (0u)
+
+/** \brief Length for Ifx_I2C_MIS_Bits.BREQ_INT */
+#define IFX_I2C_MIS_BREQ_INT_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_MIS_Bits.BREQ_INT */
+#define IFX_I2C_MIS_BREQ_INT_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_MIS_Bits.BREQ_INT */
+#define IFX_I2C_MIS_BREQ_INT_OFF (3u)
+
+/** \brief Length for Ifx_I2C_MIS_Bits.I2C_ERR_INT */
+#define IFX_I2C_MIS_I2C_ERR_INT_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_MIS_Bits.I2C_ERR_INT */
+#define IFX_I2C_MIS_I2C_ERR_INT_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_MIS_Bits.I2C_ERR_INT */
+#define IFX_I2C_MIS_I2C_ERR_INT_OFF (4u)
+
+/** \brief Length for Ifx_I2C_MIS_Bits.I2C_P_INT */
+#define IFX_I2C_MIS_I2C_P_INT_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_MIS_Bits.I2C_P_INT */
+#define IFX_I2C_MIS_I2C_P_INT_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_MIS_Bits.I2C_P_INT */
+#define IFX_I2C_MIS_I2C_P_INT_OFF (5u)
+
+/** \brief Length for Ifx_I2C_MIS_Bits.LBREQ_INT */
+#define IFX_I2C_MIS_LBREQ_INT_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_MIS_Bits.LBREQ_INT */
+#define IFX_I2C_MIS_LBREQ_INT_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_MIS_Bits.LBREQ_INT */
+#define IFX_I2C_MIS_LBREQ_INT_OFF (2u)
+
+/** \brief Length for Ifx_I2C_MIS_Bits.LSREQ_INT */
+#define IFX_I2C_MIS_LSREQ_INT_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_MIS_Bits.LSREQ_INT */
+#define IFX_I2C_MIS_LSREQ_INT_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_MIS_Bits.LSREQ_INT */
+#define IFX_I2C_MIS_LSREQ_INT_OFF (0u)
+
+/** \brief Length for Ifx_I2C_MIS_Bits.SREQ_INT */
+#define IFX_I2C_MIS_SREQ_INT_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_MIS_Bits.SREQ_INT */
+#define IFX_I2C_MIS_SREQ_INT_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_MIS_Bits.SREQ_INT */
+#define IFX_I2C_MIS_SREQ_INT_OFF (1u)
+
+/** \brief Length for Ifx_I2C_MODID_Bits.MODNUMBER */
+#define IFX_I2C_MODID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_I2C_MODID_Bits.MODNUMBER */
+#define IFX_I2C_MODID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_I2C_MODID_Bits.MODNUMBER */
+#define IFX_I2C_MODID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_I2C_MODID_Bits.MODREV */
+#define IFX_I2C_MODID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_I2C_MODID_Bits.MODREV */
+#define IFX_I2C_MODID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_I2C_MODID_Bits.MODREV */
+#define IFX_I2C_MODID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_I2C_MODID_Bits.MODTYPE */
+#define IFX_I2C_MODID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_I2C_MODID_Bits.MODTYPE */
+#define IFX_I2C_MODID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_I2C_MODID_Bits.MODTYPE */
+#define IFX_I2C_MODID_MODTYPE_OFF (8u)
+
+/** \brief Length for Ifx_I2C_MRPSCTRL_Bits.MRPS */
+#define IFX_I2C_MRPSCTRL_MRPS_LEN (14u)
+
+/** \brief Mask for Ifx_I2C_MRPSCTRL_Bits.MRPS */
+#define IFX_I2C_MRPSCTRL_MRPS_MSK (0x3fffu)
+
+/** \brief Offset for Ifx_I2C_MRPSCTRL_Bits.MRPS */
+#define IFX_I2C_MRPSCTRL_MRPS_OFF (0u)
+
+/** \brief Length for Ifx_I2C_PIRQSC_Bits.AL */
+#define IFX_I2C_PIRQSC_AL_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_PIRQSC_Bits.AL */
+#define IFX_I2C_PIRQSC_AL_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_PIRQSC_Bits.AL */
+#define IFX_I2C_PIRQSC_AL_OFF (3u)
+
+/** \brief Length for Ifx_I2C_PIRQSC_Bits.AM */
+#define IFX_I2C_PIRQSC_AM_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_PIRQSC_Bits.AM */
+#define IFX_I2C_PIRQSC_AM_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_PIRQSC_Bits.AM */
+#define IFX_I2C_PIRQSC_AM_OFF (0u)
+
+/** \brief Length for Ifx_I2C_PIRQSC_Bits.GC */
+#define IFX_I2C_PIRQSC_GC_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_PIRQSC_Bits.GC */
+#define IFX_I2C_PIRQSC_GC_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_PIRQSC_Bits.GC */
+#define IFX_I2C_PIRQSC_GC_OFF (1u)
+
+/** \brief Length for Ifx_I2C_PIRQSC_Bits.MC */
+#define IFX_I2C_PIRQSC_MC_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_PIRQSC_Bits.MC */
+#define IFX_I2C_PIRQSC_MC_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_PIRQSC_Bits.MC */
+#define IFX_I2C_PIRQSC_MC_OFF (2u)
+
+/** \brief Length for Ifx_I2C_PIRQSC_Bits.NACK */
+#define IFX_I2C_PIRQSC_NACK_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_PIRQSC_Bits.NACK */
+#define IFX_I2C_PIRQSC_NACK_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_PIRQSC_Bits.NACK */
+#define IFX_I2C_PIRQSC_NACK_OFF (4u)
+
+/** \brief Length for Ifx_I2C_PIRQSC_Bits.RX */
+#define IFX_I2C_PIRQSC_RX_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_PIRQSC_Bits.RX */
+#define IFX_I2C_PIRQSC_RX_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_PIRQSC_Bits.RX */
+#define IFX_I2C_PIRQSC_RX_OFF (6u)
+
+/** \brief Length for Ifx_I2C_PIRQSC_Bits.TX_END */
+#define IFX_I2C_PIRQSC_TX_END_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_PIRQSC_Bits.TX_END */
+#define IFX_I2C_PIRQSC_TX_END_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_PIRQSC_Bits.TX_END */
+#define IFX_I2C_PIRQSC_TX_END_OFF (5u)
+
+/** \brief Length for Ifx_I2C_PIRQSM_Bits.AL */
+#define IFX_I2C_PIRQSM_AL_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_PIRQSM_Bits.AL */
+#define IFX_I2C_PIRQSM_AL_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_PIRQSM_Bits.AL */
+#define IFX_I2C_PIRQSM_AL_OFF (3u)
+
+/** \brief Length for Ifx_I2C_PIRQSM_Bits.AM */
+#define IFX_I2C_PIRQSM_AM_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_PIRQSM_Bits.AM */
+#define IFX_I2C_PIRQSM_AM_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_PIRQSM_Bits.AM */
+#define IFX_I2C_PIRQSM_AM_OFF (0u)
+
+/** \brief Length for Ifx_I2C_PIRQSM_Bits.GC */
+#define IFX_I2C_PIRQSM_GC_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_PIRQSM_Bits.GC */
+#define IFX_I2C_PIRQSM_GC_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_PIRQSM_Bits.GC */
+#define IFX_I2C_PIRQSM_GC_OFF (1u)
+
+/** \brief Length for Ifx_I2C_PIRQSM_Bits.MC */
+#define IFX_I2C_PIRQSM_MC_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_PIRQSM_Bits.MC */
+#define IFX_I2C_PIRQSM_MC_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_PIRQSM_Bits.MC */
+#define IFX_I2C_PIRQSM_MC_OFF (2u)
+
+/** \brief Length for Ifx_I2C_PIRQSM_Bits.NACK */
+#define IFX_I2C_PIRQSM_NACK_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_PIRQSM_Bits.NACK */
+#define IFX_I2C_PIRQSM_NACK_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_PIRQSM_Bits.NACK */
+#define IFX_I2C_PIRQSM_NACK_OFF (4u)
+
+/** \brief Length for Ifx_I2C_PIRQSM_Bits.RX */
+#define IFX_I2C_PIRQSM_RX_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_PIRQSM_Bits.RX */
+#define IFX_I2C_PIRQSM_RX_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_PIRQSM_Bits.RX */
+#define IFX_I2C_PIRQSM_RX_OFF (6u)
+
+/** \brief Length for Ifx_I2C_PIRQSM_Bits.TX_END */
+#define IFX_I2C_PIRQSM_TX_END_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_PIRQSM_Bits.TX_END */
+#define IFX_I2C_PIRQSM_TX_END_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_PIRQSM_Bits.TX_END */
+#define IFX_I2C_PIRQSM_TX_END_OFF (5u)
+
+/** \brief Length for Ifx_I2C_PIRQSS_Bits.AL */
+#define IFX_I2C_PIRQSS_AL_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_PIRQSS_Bits.AL */
+#define IFX_I2C_PIRQSS_AL_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_PIRQSS_Bits.AL */
+#define IFX_I2C_PIRQSS_AL_OFF (3u)
+
+/** \brief Length for Ifx_I2C_PIRQSS_Bits.AM */
+#define IFX_I2C_PIRQSS_AM_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_PIRQSS_Bits.AM */
+#define IFX_I2C_PIRQSS_AM_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_PIRQSS_Bits.AM */
+#define IFX_I2C_PIRQSS_AM_OFF (0u)
+
+/** \brief Length for Ifx_I2C_PIRQSS_Bits.GC */
+#define IFX_I2C_PIRQSS_GC_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_PIRQSS_Bits.GC */
+#define IFX_I2C_PIRQSS_GC_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_PIRQSS_Bits.GC */
+#define IFX_I2C_PIRQSS_GC_OFF (1u)
+
+/** \brief Length for Ifx_I2C_PIRQSS_Bits.MC */
+#define IFX_I2C_PIRQSS_MC_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_PIRQSS_Bits.MC */
+#define IFX_I2C_PIRQSS_MC_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_PIRQSS_Bits.MC */
+#define IFX_I2C_PIRQSS_MC_OFF (2u)
+
+/** \brief Length for Ifx_I2C_PIRQSS_Bits.NACK */
+#define IFX_I2C_PIRQSS_NACK_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_PIRQSS_Bits.NACK */
+#define IFX_I2C_PIRQSS_NACK_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_PIRQSS_Bits.NACK */
+#define IFX_I2C_PIRQSS_NACK_OFF (4u)
+
+/** \brief Length for Ifx_I2C_PIRQSS_Bits.RX */
+#define IFX_I2C_PIRQSS_RX_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_PIRQSS_Bits.RX */
+#define IFX_I2C_PIRQSS_RX_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_PIRQSS_Bits.RX */
+#define IFX_I2C_PIRQSS_RX_OFF (6u)
+
+/** \brief Length for Ifx_I2C_PIRQSS_Bits.TX_END */
+#define IFX_I2C_PIRQSS_TX_END_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_PIRQSS_Bits.TX_END */
+#define IFX_I2C_PIRQSS_TX_END_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_PIRQSS_Bits.TX_END */
+#define IFX_I2C_PIRQSS_TX_END_OFF (5u)
+
+/** \brief Length for Ifx_I2C_RIS_Bits.BREQ_INT */
+#define IFX_I2C_RIS_BREQ_INT_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_RIS_Bits.BREQ_INT */
+#define IFX_I2C_RIS_BREQ_INT_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_RIS_Bits.BREQ_INT */
+#define IFX_I2C_RIS_BREQ_INT_OFF (3u)
+
+/** \brief Length for Ifx_I2C_RIS_Bits.I2C_ERR_INT */
+#define IFX_I2C_RIS_I2C_ERR_INT_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_RIS_Bits.I2C_ERR_INT */
+#define IFX_I2C_RIS_I2C_ERR_INT_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_RIS_Bits.I2C_ERR_INT */
+#define IFX_I2C_RIS_I2C_ERR_INT_OFF (4u)
+
+/** \brief Length for Ifx_I2C_RIS_Bits.I2C_P_INT */
+#define IFX_I2C_RIS_I2C_P_INT_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_RIS_Bits.I2C_P_INT */
+#define IFX_I2C_RIS_I2C_P_INT_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_RIS_Bits.I2C_P_INT */
+#define IFX_I2C_RIS_I2C_P_INT_OFF (5u)
+
+/** \brief Length for Ifx_I2C_RIS_Bits.LBREQ_INT */
+#define IFX_I2C_RIS_LBREQ_INT_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_RIS_Bits.LBREQ_INT */
+#define IFX_I2C_RIS_LBREQ_INT_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_RIS_Bits.LBREQ_INT */
+#define IFX_I2C_RIS_LBREQ_INT_OFF (2u)
+
+/** \brief Length for Ifx_I2C_RIS_Bits.LSREQ_INT */
+#define IFX_I2C_RIS_LSREQ_INT_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_RIS_Bits.LSREQ_INT */
+#define IFX_I2C_RIS_LSREQ_INT_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_RIS_Bits.LSREQ_INT */
+#define IFX_I2C_RIS_LSREQ_INT_OFF (0u)
+
+/** \brief Length for Ifx_I2C_RIS_Bits.SREQ_INT */
+#define IFX_I2C_RIS_SREQ_INT_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_RIS_Bits.SREQ_INT */
+#define IFX_I2C_RIS_SREQ_INT_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_RIS_Bits.SREQ_INT */
+#define IFX_I2C_RIS_SREQ_INT_OFF (1u)
+
+/** \brief Length for Ifx_I2C_RPSSTAT_Bits.RPS */
+#define IFX_I2C_RPSSTAT_RPS_LEN (14u)
+
+/** \brief Mask for Ifx_I2C_RPSSTAT_Bits.RPS */
+#define IFX_I2C_RPSSTAT_RPS_MSK (0x3fffu)
+
+/** \brief Offset for Ifx_I2C_RPSSTAT_Bits.RPS */
+#define IFX_I2C_RPSSTAT_RPS_OFF (0u)
+
+/** \brief Length for Ifx_I2C_RUNCTRL_Bits.RUN */
+#define IFX_I2C_RUNCTRL_RUN_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_RUNCTRL_Bits.RUN */
+#define IFX_I2C_RUNCTRL_RUN_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_RUNCTRL_Bits.RUN */
+#define IFX_I2C_RUNCTRL_RUN_OFF (0u)
+
+/** \brief Length for Ifx_I2C_RXD_Bits.RXD */
+#define IFX_I2C_RXD_RXD_LEN (32u)
+
+/** \brief Mask for Ifx_I2C_RXD_Bits.RXD */
+#define IFX_I2C_RXD_RXD_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_I2C_RXD_Bits.RXD */
+#define IFX_I2C_RXD_RXD_OFF (0u)
+
+/** \brief Length for Ifx_I2C_TIMCFG_Bits.EN_SCL_LOW_LEN */
+#define IFX_I2C_TIMCFG_EN_SCL_LOW_LEN_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_TIMCFG_Bits.EN_SCL_LOW_LEN */
+#define IFX_I2C_TIMCFG_EN_SCL_LOW_LEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_TIMCFG_Bits.EN_SCL_LOW_LEN */
+#define IFX_I2C_TIMCFG_EN_SCL_LOW_LEN_OFF (14u)
+
+/** \brief Length for Ifx_I2C_TIMCFG_Bits.FS_SCL_LOW */
+#define IFX_I2C_TIMCFG_FS_SCL_LOW_LEN (1u)
+
+/** \brief Mask for Ifx_I2C_TIMCFG_Bits.FS_SCL_LOW */
+#define IFX_I2C_TIMCFG_FS_SCL_LOW_MSK (0x1u)
+
+/** \brief Offset for Ifx_I2C_TIMCFG_Bits.FS_SCL_LOW */
+#define IFX_I2C_TIMCFG_FS_SCL_LOW_OFF (15u)
+
+/** \brief Length for Ifx_I2C_TIMCFG_Bits.HS_SDA_DEL_HD_DAT */
+#define IFX_I2C_TIMCFG_HS_SDA_DEL_HD_DAT_LEN (3u)
+
+/** \brief Mask for Ifx_I2C_TIMCFG_Bits.HS_SDA_DEL_HD_DAT */
+#define IFX_I2C_TIMCFG_HS_SDA_DEL_HD_DAT_MSK (0x7u)
+
+/** \brief Offset for Ifx_I2C_TIMCFG_Bits.HS_SDA_DEL_HD_DAT */
+#define IFX_I2C_TIMCFG_HS_SDA_DEL_HD_DAT_OFF (6u)
+
+/** \brief Length for Ifx_I2C_TIMCFG_Bits.HS_SDA_DEL */
+#define IFX_I2C_TIMCFG_HS_SDA_DEL_LEN (3u)
+
+/** \brief Mask for Ifx_I2C_TIMCFG_Bits.HS_SDA_DEL */
+#define IFX_I2C_TIMCFG_HS_SDA_DEL_MSK (0x7u)
+
+/** \brief Offset for Ifx_I2C_TIMCFG_Bits.HS_SDA_DEL */
+#define IFX_I2C_TIMCFG_HS_SDA_DEL_OFF (16u)
+
+/** \brief Length for Ifx_I2C_TIMCFG_Bits.SCL_DEL_HD_STA */
+#define IFX_I2C_TIMCFG_SCL_DEL_HD_STA_LEN (3u)
+
+/** \brief Mask for Ifx_I2C_TIMCFG_Bits.SCL_DEL_HD_STA */
+#define IFX_I2C_TIMCFG_SCL_DEL_HD_STA_MSK (0x7u)
+
+/** \brief Offset for Ifx_I2C_TIMCFG_Bits.SCL_DEL_HD_STA */
+#define IFX_I2C_TIMCFG_SCL_DEL_HD_STA_OFF (9u)
+
+/** \brief Length for Ifx_I2C_TIMCFG_Bits.SCL_LOW_LEN */
+#define IFX_I2C_TIMCFG_SCL_LOW_LEN_LEN (8u)
+
+/** \brief Mask for Ifx_I2C_TIMCFG_Bits.SCL_LOW_LEN */
+#define IFX_I2C_TIMCFG_SCL_LOW_LEN_MSK (0xffu)
+
+/** \brief Offset for Ifx_I2C_TIMCFG_Bits.SCL_LOW_LEN */
+#define IFX_I2C_TIMCFG_SCL_LOW_LEN_OFF (24u)
+
+/** \brief Length for Ifx_I2C_TIMCFG_Bits.SDA_DEL_HD_DAT */
+#define IFX_I2C_TIMCFG_SDA_DEL_HD_DAT_LEN (6u)
+
+/** \brief Mask for Ifx_I2C_TIMCFG_Bits.SDA_DEL_HD_DAT */
+#define IFX_I2C_TIMCFG_SDA_DEL_HD_DAT_MSK (0x3fu)
+
+/** \brief Offset for Ifx_I2C_TIMCFG_Bits.SDA_DEL_HD_DAT */
+#define IFX_I2C_TIMCFG_SDA_DEL_HD_DAT_OFF (0u)
+
+/** \brief Length for Ifx_I2C_TPSCTRL_Bits.TPS */
+#define IFX_I2C_TPSCTRL_TPS_LEN (14u)
+
+/** \brief Mask for Ifx_I2C_TPSCTRL_Bits.TPS */
+#define IFX_I2C_TPSCTRL_TPS_MSK (0x3fffu)
+
+/** \brief Offset for Ifx_I2C_TPSCTRL_Bits.TPS */
+#define IFX_I2C_TPSCTRL_TPS_OFF (0u)
+
+/** \brief Length for Ifx_I2C_TXD_Bits.TXD */
+#define IFX_I2C_TXD_TXD_LEN (32u)
+
+/** \brief Mask for Ifx_I2C_TXD_Bits.TXD */
+#define IFX_I2C_TXD_TXD_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_I2C_TXD_Bits.TXD */
+#define IFX_I2C_TXD_TXD_OFF (0u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXI2C_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxI2c_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxI2c_reg.h
new file mode 100644
index 0000000..c82ec0f
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxI2c_reg.h
@@ -0,0 +1,156 @@
+/**
+ * \file IfxI2c_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_I2c_Cfg I2c address
+ * \ingroup IfxLld_I2c
+ *
+ * \defgroup IfxLld_I2c_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_I2c_Cfg
+ *
+ * \defgroup IfxLld_I2c_Cfg_I2c0 2-I2C0
+ * \ingroup IfxLld_I2c_Cfg
+ *
+ */
+#ifndef IFXI2C_REG_H
+#define IFXI2C_REG_H 1
+/******************************************************************************/
+#include "IfxI2c_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_I2c_Cfg_BaseAddress
+ * \{ */
+
+/** \brief I2C object */
+#define MODULE_I2C0 /*lint --e(923)*/ (*(Ifx_I2C*)0xF00C0000u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_I2c_Cfg_I2c0
+ * \{ */
+
+/** \brief 1000C, Access Enable Register 0 */
+#define I2C0_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_I2C_ACCEN0*)0xF00D000Cu)
+
+/** \brief 10010, Access Enable Register 1 */
+#define I2C0_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_I2C_ACCEN1*)0xF00D0010u)
+
+/** \brief 20, Address Configuration Register */
+#define I2C0_ADDRCFG /*lint --e(923)*/ (*(volatile Ifx_I2C_ADDRCFG*)0xF00C0020u)
+
+/** \brief 24, Bus Status Register */
+#define I2C0_BUSSTAT /*lint --e(923)*/ (*(volatile Ifx_I2C_BUSSTAT*)0xF00C0024u)
+
+/** \brief 10000, Clock Control Register */
+#define I2C0_CLC /*lint --e(923)*/ (*(volatile Ifx_I2C_CLC*)0xF00D0000u)
+
+/** \brief 0, Clock Control 1 Register */
+#define I2C0_CLC1 /*lint --e(923)*/ (*(volatile Ifx_I2C_CLC1*)0xF00C0000u)
+
+/** \brief 14, End Data Control Register */
+#define I2C0_ENDDCTRL /*lint --e(923)*/ (*(volatile Ifx_I2C_ENDDCTRL*)0xF00C0014u)
+
+/** \brief 68, Error Interrupt Request Source Clear Register */
+#define I2C0_ERRIRQSC /*lint --e(923)*/ (*(volatile Ifx_I2C_ERRIRQSC*)0xF00C0068u)
+
+/** \brief 60, Error Interrupt Request Source Mask Register */
+#define I2C0_ERRIRQSM /*lint --e(923)*/ (*(volatile Ifx_I2C_ERRIRQSM*)0xF00C0060u)
+
+/** \brief 64, Error Interrupt Request Source Status Register */
+#define I2C0_ERRIRQSS /*lint --e(923)*/ (*(volatile Ifx_I2C_ERRIRQSS*)0xF00C0064u)
+
+/** \brief 18, Fractional Divider Configuration Register */
+#define I2C0_FDIVCFG /*lint --e(923)*/ (*(volatile Ifx_I2C_FDIVCFG*)0xF00C0018u)
+
+/** \brief 1C, Fractional Divider High-speed Mode Configuration Register */
+#define I2C0_FDIVHIGHCFG /*lint --e(923)*/ (*(volatile Ifx_I2C_FDIVHIGHCFG*)0xF00C001Cu)
+
+/** \brief 38, Filled FIFO Stages Status Register */
+#define I2C0_FFSSTAT /*lint --e(923)*/ (*(volatile Ifx_I2C_FFSSTAT*)0xF00C0038u)
+
+/** \brief 28, FIFO Configuration Register */
+#define I2C0_FIFOCFG /*lint --e(923)*/ (*(volatile Ifx_I2C_FIFOCFG*)0xF00C0028u)
+
+/** \brief 10008, General Purpose Control Register */
+#define I2C0_GPCTL /*lint --e(923)*/ (*(volatile Ifx_I2C_GPCTL*)0xF00D0008u)
+
+/** \brief 8C, Interrupt Clear Register */
+#define I2C0_ICR /*lint --e(923)*/ (*(volatile Ifx_I2C_ICR*)0xF00C008Cu)
+
+/** \brief 8, Module Identification Register */
+#define I2C0_ID /*lint --e(923)*/ (*(volatile Ifx_I2C_ID*)0xF00C0008u)
+
+/** \brief 84, Interrupt Mask Control Register */
+#define I2C0_IMSC /*lint --e(923)*/ (*(volatile Ifx_I2C_IMSC*)0xF00C0084u)
+
+/** \brief 90, Interrupt Set Register */
+#define I2C0_ISR /*lint --e(923)*/ (*(volatile Ifx_I2C_ISR*)0xF00C0090u)
+
+/** \brief 10014, Kernel Reset Register 0 */
+#define I2C0_KRST0 /*lint --e(923)*/ (*(volatile Ifx_I2C_KRST0*)0xF00D0014u)
+
+/** \brief 10018, Kernel Reset Register 1 */
+#define I2C0_KRST1 /*lint --e(923)*/ (*(volatile Ifx_I2C_KRST1*)0xF00D0018u)
+
+/** \brief 1001C, Kernel Reset Status Clear Register */
+#define I2C0_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_I2C_KRSTCLR*)0xF00D001Cu)
+
+/** \brief 88, Masked Interrupt Status Register */
+#define I2C0_MIS /*lint --e(923)*/ (*(volatile Ifx_I2C_MIS*)0xF00C0088u)
+
+/** \brief 10004, Module Identification Register */
+#define I2C0_MODID /*lint --e(923)*/ (*(volatile Ifx_I2C_MODID*)0xF00D0004u)
+
+/** \brief 2C, Maximum Received Packet Size Control Register */
+#define I2C0_MRPSCTRL /*lint --e(923)*/ (*(volatile Ifx_I2C_MRPSCTRL*)0xF00C002Cu)
+
+/** \brief 78, Protocol Interrupt Request Source Clear Register */
+#define I2C0_PIRQSC /*lint --e(923)*/ (*(volatile Ifx_I2C_PIRQSC*)0xF00C0078u)
+
+/** \brief 70, Protocol Interrupt Request Source Mask Register */
+#define I2C0_PIRQSM /*lint --e(923)*/ (*(volatile Ifx_I2C_PIRQSM*)0xF00C0070u)
+
+/** \brief 74, Protocol Interrupt Request Source Status Register */
+#define I2C0_PIRQSS /*lint --e(923)*/ (*(volatile Ifx_I2C_PIRQSS*)0xF00C0074u)
+
+/** \brief 80, Raw Interrupt Status Register */
+#define I2C0_RIS /*lint --e(923)*/ (*(volatile Ifx_I2C_RIS*)0xF00C0080u)
+
+/** \brief 30, Received Packet Size Status Register */
+#define I2C0_RPSSTAT /*lint --e(923)*/ (*(volatile Ifx_I2C_RPSSTAT*)0xF00C0030u)
+
+/** \brief 10, RUN Control Register */
+#define I2C0_RUNCTRL /*lint --e(923)*/ (*(volatile Ifx_I2C_RUNCTRL*)0xF00C0010u)
+
+/** \brief C000, Reception Data Register */
+#define I2C0_RXD /*lint --e(923)*/ (*(volatile Ifx_I2C_RXD*)0xF00CC000u)
+
+/** \brief 40, Timing Configuration Register */
+#define I2C0_TIMCFG /*lint --e(923)*/ (*(volatile Ifx_I2C_TIMCFG*)0xF00C0040u)
+
+/** \brief 34, Transmit Packet Size Control Register */
+#define I2C0_TPSCTRL /*lint --e(923)*/ (*(volatile Ifx_I2C_TPSCTRL*)0xF00C0034u)
+
+/** \brief 8000, Transmission Data Register */
+#define I2C0_TXD /*lint --e(923)*/ (*(volatile Ifx_I2C_TXD*)0xF00C8000u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXI2C_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxI2c_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxI2c_regdef.h
new file mode 100644
index 0000000..944b108
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxI2c_regdef.h
@@ -0,0 +1,753 @@
+/**
+ * \file IfxI2c_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_I2c I2c
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_I2c_Bitfields Bitfields
+ * \ingroup IfxLld_I2c
+ *
+ * \defgroup IfxLld_I2c_union Union
+ * \ingroup IfxLld_I2c
+ *
+ * \defgroup IfxLld_I2c_struct Struct
+ * \ingroup IfxLld_I2c
+ *
+ */
+#ifndef IFXI2C_REGDEF_H
+#define IFXI2C_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_I2c_Bitfields
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef struct _Ifx_I2C_ACCEN0_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_I2C_ACCEN0_Bits;
+
+/** \brief Access Enable Register 1 */
+typedef struct _Ifx_I2C_ACCEN1_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_I2C_ACCEN1_Bits;
+
+/** \brief Address Configuration Register */
+typedef struct _Ifx_I2C_ADDRCFG_Bits
+{
+ unsigned int ADR:10; /**< \brief [9:0] I2C-bus Device Address (rw) */
+ unsigned int reserved_10:6; /**< \brief \internal Reserved */
+ unsigned int TBAM:1; /**< \brief [16:16] Ten Bit Address Mode (rw) */
+ unsigned int GCE:1; /**< \brief [17:17] General Call Enable (rw) */
+ unsigned int MCE:1; /**< \brief [18:18] Master Code Enable (rw) */
+ unsigned int MnS:1; /**< \brief [19:19] Master / not Slave (rw) */
+ unsigned int SONA:1; /**< \brief [20:20] Stop on Not-acknowledge (rw) */
+ unsigned int SOPE:1; /**< \brief [21:21] Stop on Packet End (rw) */
+ unsigned int reserved_22:10; /**< \brief \internal Reserved */
+} Ifx_I2C_ADDRCFG_Bits;
+
+/** \brief Bus Status Register */
+typedef struct _Ifx_I2C_BUSSTAT_Bits
+{
+ unsigned int BS:2; /**< \brief [1:0] Bus Status (rh) */
+ unsigned int RnW:1; /**< \brief [2:2] Read/not Write (rh) */
+ unsigned int reserved_3:29; /**< \brief \internal Reserved */
+} Ifx_I2C_BUSSTAT_Bits;
+
+/** \brief Clock Control 1 Register */
+typedef struct _Ifx_I2C_CLC1_Bits
+{
+ unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
+ unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
+ unsigned int SPEN:1; /**< \brief [2:2] Module Suspend Enable Bit for OCDS (rw) */
+ unsigned int EDIS:1; /**< \brief [3:3] External Request Disable (rw) */
+ unsigned int SBWE:1; /**< \brief [4:4] Module Suspend Bit Write Enable for OCDS (w) */
+ unsigned int FSOE:1; /**< \brief [5:5] Fast Switch Off Enable (rw) */
+ unsigned int reserved_6:2; /**< \brief \internal Reserved */
+ unsigned int RMC:8; /**< \brief [15:8] Clock Divider for Standard Run Mode (rwh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_I2C_CLC1_Bits;
+
+/** \brief Clock Control Register */
+typedef struct _Ifx_I2C_CLC_Bits
+{
+ unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
+ unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_I2C_CLC_Bits;
+
+/** \brief End Data Control Register */
+typedef struct _Ifx_I2C_ENDDCTRL_Bits
+{
+ unsigned int SETRSC:1; /**< \brief [0:0] Set Restart Condition (w) */
+ unsigned int SETEND:1; /**< \brief [1:1] Set End of Transmission (w) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_I2C_ENDDCTRL_Bits;
+
+/** \brief Error Interrupt Request Source Clear Register */
+typedef struct _Ifx_I2C_ERRIRQSC_Bits
+{
+ unsigned int RXF_UFL:1; /**< \brief [0:0] RX FIFO Underflow (w) */
+ unsigned int RXF_OFL:1; /**< \brief [1:1] RX FIFO Overflow (w) */
+ unsigned int TXF_UFL:1; /**< \brief [2:2] TX FIFO Underflow (w) */
+ unsigned int TXF_OFL:1; /**< \brief [3:3] TX FIFO Overflow (w) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_I2C_ERRIRQSC_Bits;
+
+/** \brief Error Interrupt Request Source Mask Register */
+typedef struct _Ifx_I2C_ERRIRQSM_Bits
+{
+ unsigned int RXF_UFL:1; /**< \brief [0:0] RX FIFO Underflow (rw) */
+ unsigned int RXF_OFL:1; /**< \brief [1:1] RX FIFO Overflow (rw) */
+ unsigned int TXF_UFL:1; /**< \brief [2:2] TX FIFO Underflow (rw) */
+ unsigned int TXF_OFL:1; /**< \brief [3:3] TX FIFO Overflow (rw) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_I2C_ERRIRQSM_Bits;
+
+/** \brief Error Interrupt Request Source Status Register */
+typedef struct _Ifx_I2C_ERRIRQSS_Bits
+{
+ unsigned int RXF_UFL:1; /**< \brief [0:0] RX FIFO Underflow (rh) */
+ unsigned int RXF_OFL:1; /**< \brief [1:1] RX FIFO Overflow (rh) */
+ unsigned int TXF_UFL:1; /**< \brief [2:2] TX FIFO Underflow (rh) */
+ unsigned int TXF_OFL:1; /**< \brief [3:3] TX FIFO Overflow (rh) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_I2C_ERRIRQSS_Bits;
+
+/** \brief Fractional Divider Configuration Register */
+typedef struct _Ifx_I2C_FDIVCFG_Bits
+{
+ unsigned int DEC:11; /**< \brief [10:0] Decrement Value of Fractional Divider (rw) */
+ unsigned int reserved_11:5; /**< \brief \internal Reserved */
+ unsigned int INC:8; /**< \brief [23:16] Increment Value of Fractional Divider (rw) */
+ unsigned int reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_I2C_FDIVCFG_Bits;
+
+/** \brief Fractional Divider High-speed Mode Configuration Register */
+typedef struct _Ifx_I2C_FDIVHIGHCFG_Bits
+{
+ unsigned int DEC:11; /**< \brief [10:0] Decrement Value of Fractional Divider (rw) */
+ unsigned int reserved_11:5; /**< \brief \internal Reserved */
+ unsigned int INC:8; /**< \brief [23:16] Increment Value of Fractional Divider (rw) */
+ unsigned int reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_I2C_FDIVHIGHCFG_Bits;
+
+/** \brief Filled FIFO Stages Status Register */
+typedef struct _Ifx_I2C_FFSSTAT_Bits
+{
+ unsigned int FFS:6; /**< \brief [5:0] Filled FIFO Stages (rh) */
+ unsigned int reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_I2C_FFSSTAT_Bits;
+
+/** \brief FIFO Configuration Register */
+typedef struct _Ifx_I2C_FIFOCFG_Bits
+{
+ unsigned int RXBS:2; /**< \brief [1:0] RX Burst Size (rw) */
+ unsigned int reserved_2:2; /**< \brief \internal Reserved */
+ unsigned int TXBS:2; /**< \brief [5:4] TX Burst Size (rw) */
+ unsigned int reserved_6:2; /**< \brief \internal Reserved */
+ unsigned int RXFA:2; /**< \brief [9:8] RX FIFO Alignment (rw) */
+ unsigned int reserved_10:2; /**< \brief \internal Reserved */
+ unsigned int TXFA:2; /**< \brief [13:12] TX FIFO Alignment (rw) */
+ unsigned int reserved_14:2; /**< \brief \internal Reserved */
+ unsigned int RXFC:1; /**< \brief [16:16] RX FIFO Flow Control (rw) */
+ unsigned int TXFC:1; /**< \brief [17:17] TX FIFO Flow Control (rw) */
+ unsigned int reserved_18:14; /**< \brief \internal Reserved */
+} Ifx_I2C_FIFOCFG_Bits;
+
+/** \brief General Purpose Control Register */
+typedef struct _Ifx_I2C_GPCTL_Bits
+{
+ unsigned int PISEL:3; /**< \brief [2:0] Port Input Select (rw) */
+ unsigned int reserved_3:29; /**< \brief \internal Reserved */
+} Ifx_I2C_GPCTL_Bits;
+
+/** \brief Interrupt Clear Register */
+typedef struct _Ifx_I2C_ICR_Bits
+{
+ unsigned int LSREQ_INT:1; /**< \brief [0:0] Last Single Request Interrupt (w) */
+ unsigned int SREQ_INT:1; /**< \brief [1:1] Single Request Interrupt (w) */
+ unsigned int LBREQ_INT:1; /**< \brief [2:2] Last Burst Request Interrupt (w) */
+ unsigned int BREQ_INT:1; /**< \brief [3:3] Burst Request Interrupt (w) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_I2C_ICR_Bits;
+
+/** \brief Module Identification Register */
+typedef struct _Ifx_I2C_ID_Bits
+{
+ unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ unsigned int MODNUMBER:8; /**< \brief [15:8] Module Number Value (r) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_I2C_ID_Bits;
+
+/** \brief Interrupt Mask Control Register */
+typedef struct _Ifx_I2C_IMSC_Bits
+{
+ unsigned int LSREQ_INT:1; /**< \brief [0:0] Last Single Request Interrupt (rw) */
+ unsigned int SREQ_INT:1; /**< \brief [1:1] Single Request Interrupt (rw) */
+ unsigned int LBREQ_INT:1; /**< \brief [2:2] Last Burst Request Interrupt (rw) */
+ unsigned int BREQ_INT:1; /**< \brief [3:3] Burst Request Interrupt (rw) */
+ unsigned int I2C_ERR_INT:1; /**< \brief [4:4] I2C Error Interrupt (rw) */
+ unsigned int I2C_P_INT:1; /**< \brief [5:5] I2C Protocol Interrupt (rw) */
+ unsigned int reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_I2C_IMSC_Bits;
+
+/** \brief Interrupt Set Register */
+typedef struct _Ifx_I2C_ISR_Bits
+{
+ unsigned int LSREQ_INT:1; /**< \brief [0:0] Last Single Request Interrupt (w) */
+ unsigned int SREQ_INT:1; /**< \brief [1:1] Single Request Interrupt (w) */
+ unsigned int LBREQ_INT:1; /**< \brief [2:2] Last Burst Request Interrupt (w) */
+ unsigned int BREQ_INT:1; /**< \brief [3:3] Burst Request Interrupt (w) */
+ unsigned int I2C_ERR_INT:1; /**< \brief [4:4] I2C Error Interrupt (w) */
+ unsigned int I2C_P_INT:1; /**< \brief [5:5] I2C Protocol Interrupt (w) */
+ unsigned int reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_I2C_ISR_Bits;
+
+/** \brief Kernel Reset Register 0 */
+typedef struct _Ifx_I2C_KRST0_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rh) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_I2C_KRST0_Bits;
+
+/** \brief Kernel Reset Register 1 */
+typedef struct _Ifx_I2C_KRST1_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_I2C_KRST1_Bits;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef struct _Ifx_I2C_KRSTCLR_Bits
+{
+ unsigned int CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_I2C_KRSTCLR_Bits;
+
+/** \brief Masked Interrupt Status Register */
+typedef struct _Ifx_I2C_MIS_Bits
+{
+ unsigned int LSREQ_INT:1; /**< \brief [0:0] Last Single Request Interrupt (rh) */
+ unsigned int SREQ_INT:1; /**< \brief [1:1] Single Request Interrupt (rh) */
+ unsigned int LBREQ_INT:1; /**< \brief [2:2] Last Burst Request Interrupt (rh) */
+ unsigned int BREQ_INT:1; /**< \brief [3:3] Burst Request Interrupt (rh) */
+ unsigned int I2C_ERR_INT:1; /**< \brief [4:4] I2C Error Interrupt (rh) */
+ unsigned int I2C_P_INT:1; /**< \brief [5:5] I2C Protocol Interrupt (rh) */
+ unsigned int reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_I2C_MIS_Bits;
+
+/** \brief Module Identification Register */
+typedef struct _Ifx_I2C_MODID_Bits
+{
+ unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
+ unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_I2C_MODID_Bits;
+
+/** \brief Maximum Received Packet Size Control Register */
+typedef struct _Ifx_I2C_MRPSCTRL_Bits
+{
+ unsigned int MRPS:14; /**< \brief [13:0] Maximum Received Packet Size (rwh) */
+ unsigned int reserved_14:18; /**< \brief \internal Reserved */
+} Ifx_I2C_MRPSCTRL_Bits;
+
+/** \brief Protocol Interrupt Request Source Clear Register */
+typedef struct _Ifx_I2C_PIRQSC_Bits
+{
+ unsigned int AM:1; /**< \brief [0:0] Address Match (w) */
+ unsigned int GC:1; /**< \brief [1:1] General Call (w) */
+ unsigned int MC:1; /**< \brief [2:2] Master Code (w) */
+ unsigned int AL:1; /**< \brief [3:3] Arbitration Lost (w) */
+ unsigned int NACK:1; /**< \brief [4:4] Not-acknowledge Received (w) */
+ unsigned int TX_END:1; /**< \brief [5:5] Transmission End (w) */
+ unsigned int RX:1; /**< \brief [6:6] Receive Mode (w) */
+ unsigned int reserved_7:25; /**< \brief \internal Reserved */
+} Ifx_I2C_PIRQSC_Bits;
+
+/** \brief Protocol Interrupt Request Source Mask Register */
+typedef struct _Ifx_I2C_PIRQSM_Bits
+{
+ unsigned int AM:1; /**< \brief [0:0] Address Match (rw) */
+ unsigned int GC:1; /**< \brief [1:1] General Call (rw) */
+ unsigned int MC:1; /**< \brief [2:2] Master Code (rw) */
+ unsigned int AL:1; /**< \brief [3:3] Arbitration Lost (rw) */
+ unsigned int NACK:1; /**< \brief [4:4] Not-acknowledge Received (rw) */
+ unsigned int TX_END:1; /**< \brief [5:5] Transmission End (rw) */
+ unsigned int RX:1; /**< \brief [6:6] Receive Mode (rw) */
+ unsigned int reserved_7:25; /**< \brief \internal Reserved */
+} Ifx_I2C_PIRQSM_Bits;
+
+/** \brief Protocol Interrupt Request Source Status Register */
+typedef struct _Ifx_I2C_PIRQSS_Bits
+{
+ unsigned int AM:1; /**< \brief [0:0] Address Match (rh) */
+ unsigned int GC:1; /**< \brief [1:1] General Call (rh) */
+ unsigned int MC:1; /**< \brief [2:2] Master Code (rh) */
+ unsigned int AL:1; /**< \brief [3:3] Arbitration Lost (rh) */
+ unsigned int NACK:1; /**< \brief [4:4] Not-acknowledge Received (rh) */
+ unsigned int TX_END:1; /**< \brief [5:5] Transmission End (rh) */
+ unsigned int RX:1; /**< \brief [6:6] Receive Mode (rh) */
+ unsigned int reserved_7:25; /**< \brief \internal Reserved */
+} Ifx_I2C_PIRQSS_Bits;
+
+/** \brief Raw Interrupt Status Register */
+typedef struct _Ifx_I2C_RIS_Bits
+{
+ unsigned int LSREQ_INT:1; /**< \brief [0:0] Last Single Request Interrupt (rh) */
+ unsigned int SREQ_INT:1; /**< \brief [1:1] Single Request Interrupt (rh) */
+ unsigned int LBREQ_INT:1; /**< \brief [2:2] Last Burst Request Interrupt (rh) */
+ unsigned int BREQ_INT:1; /**< \brief [3:3] Burst Request Interrupt (rh) */
+ unsigned int I2C_ERR_INT:1; /**< \brief [4:4] I2C Error Interrupt (rh) */
+ unsigned int I2C_P_INT:1; /**< \brief [5:5] I2C Protocol Interrupt (rh) */
+ unsigned int reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_I2C_RIS_Bits;
+
+/** \brief Received Packet Size Status Register */
+typedef struct _Ifx_I2C_RPSSTAT_Bits
+{
+ unsigned int RPS:14; /**< \brief [13:0] Received Packet Size (rh) */
+ unsigned int reserved_14:18; /**< \brief \internal Reserved */
+} Ifx_I2C_RPSSTAT_Bits;
+
+/** \brief RUN Control Register */
+typedef struct _Ifx_I2C_RUNCTRL_Bits
+{
+ unsigned int RUN:1; /**< \brief [0:0] Enable I2C-bus Interface (rw) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_I2C_RUNCTRL_Bits;
+
+/** \brief Reception Data Register */
+typedef struct _Ifx_I2C_RXD_Bits
+{
+ unsigned int RXD:32; /**< \brief [31:0] Reception Data (rh) */
+} Ifx_I2C_RXD_Bits;
+
+/** \brief Timing Configuration Register */
+typedef struct _Ifx_I2C_TIMCFG_Bits
+{
+ unsigned int SDA_DEL_HD_DAT:6; /**< \brief [5:0] SDA Delay Stages for Data Hold Time (rw) */
+ unsigned int HS_SDA_DEL_HD_DAT:3; /**< \brief [8:6] SDA Delay Stages for Data Hold Time in High-speed Mode (rw) */
+ unsigned int SCL_DEL_HD_STA:3; /**< \brief [11:9] SCL Delay Stages for Hold Time Start (Restart) Bit (rw) */
+ unsigned int reserved_12:2; /**< \brief \internal Reserved */
+ unsigned int EN_SCL_LOW_LEN:1; /**< \brief [14:14] Enable Direct Configuration of SCL Low Period Length in Fast Mode (rw) */
+ unsigned int FS_SCL_LOW:1; /**< \brief [15:15] Set Fast Mode SCL Low Period Timing (rw) */
+ unsigned int HS_SDA_DEL:3; /**< \brief [18:16] SDA Delay Stages for Start/Stop bit in High-speed Mode (rw) */
+ unsigned int reserved_19:5; /**< \brief \internal Reserved */
+ unsigned int SCL_LOW_LEN:8; /**< \brief [31:24] SCL Low Length in Fast Mode (rw) */
+} Ifx_I2C_TIMCFG_Bits;
+
+/** \brief Transmit Packet Size Control Register */
+typedef struct _Ifx_I2C_TPSCTRL_Bits
+{
+ unsigned int TPS:14; /**< \brief [13:0] Transmit Packet Size (rwh) */
+ unsigned int reserved_14:18; /**< \brief \internal Reserved */
+} Ifx_I2C_TPSCTRL_Bits;
+
+/** \brief Transmission Data Register */
+typedef struct _Ifx_I2C_TXD_Bits
+{
+ unsigned int TXD:32; /**< \brief [31:0] Transmission Data (rw) */
+} Ifx_I2C_TXD_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_I2c_union
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_ACCEN0_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_ACCEN0;
+
+/** \brief Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_ACCEN1_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_ACCEN1;
+
+/** \brief Address Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_ADDRCFG_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_ADDRCFG;
+
+/** \brief Bus Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_BUSSTAT_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_BUSSTAT;
+
+/** \brief Clock Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_CLC_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_CLC;
+
+/** \brief Clock Control 1 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_CLC1_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_CLC1;
+
+/** \brief End Data Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_ENDDCTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_ENDDCTRL;
+
+/** \brief Error Interrupt Request Source Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_ERRIRQSC_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_ERRIRQSC;
+
+/** \brief Error Interrupt Request Source Mask Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_ERRIRQSM_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_ERRIRQSM;
+
+/** \brief Error Interrupt Request Source Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_ERRIRQSS_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_ERRIRQSS;
+
+/** \brief Fractional Divider Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_FDIVCFG_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_FDIVCFG;
+
+/** \brief Fractional Divider High-speed Mode Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_FDIVHIGHCFG_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_FDIVHIGHCFG;
+
+/** \brief Filled FIFO Stages Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_FFSSTAT_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_FFSSTAT;
+
+/** \brief FIFO Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_FIFOCFG_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_FIFOCFG;
+
+/** \brief General Purpose Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_GPCTL_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_GPCTL;
+
+/** \brief Interrupt Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_ICR_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_ICR;
+
+/** \brief Module Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_ID;
+
+/** \brief Interrupt Mask Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_IMSC_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_IMSC;
+
+/** \brief Interrupt Set Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_ISR_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_ISR;
+
+/** \brief Kernel Reset Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_KRST0_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_KRST0;
+
+/** \brief Kernel Reset Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_KRST1_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_KRST1;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_KRSTCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_KRSTCLR;
+
+/** \brief Masked Interrupt Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_MIS_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_MIS;
+
+/** \brief Module Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_MODID_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_MODID;
+
+/** \brief Maximum Received Packet Size Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_MRPSCTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_MRPSCTRL;
+
+/** \brief Protocol Interrupt Request Source Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_PIRQSC_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_PIRQSC;
+
+/** \brief Protocol Interrupt Request Source Mask Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_PIRQSM_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_PIRQSM;
+
+/** \brief Protocol Interrupt Request Source Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_PIRQSS_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_PIRQSS;
+
+/** \brief Raw Interrupt Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_RIS_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_RIS;
+
+/** \brief Received Packet Size Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_RPSSTAT_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_RPSSTAT;
+
+/** \brief RUN Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_RUNCTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_RUNCTRL;
+
+/** \brief Reception Data Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_RXD_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_RXD;
+
+/** \brief Timing Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_TIMCFG_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_TIMCFG;
+
+/** \brief Transmit Packet Size Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_TPSCTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_TPSCTRL;
+
+/** \brief Transmission Data Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_I2C_TXD_Bits B; /**< \brief Bitfield access */
+} Ifx_I2C_TXD;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_I2c_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief I2C object */
+typedef volatile struct _Ifx_I2C
+{
+ Ifx_I2C_CLC1 CLC1; /**< \brief 0, Clock Control 1 Register */
+ unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
+ Ifx_I2C_ID ID; /**< \brief 8, Module Identification Register */
+ unsigned char reserved_C[4]; /**< \brief C, \internal Reserved */
+ Ifx_I2C_RUNCTRL RUNCTRL; /**< \brief 10, RUN Control Register */
+ Ifx_I2C_ENDDCTRL ENDDCTRL; /**< \brief 14, End Data Control Register */
+ Ifx_I2C_FDIVCFG FDIVCFG; /**< \brief 18, Fractional Divider Configuration Register */
+ Ifx_I2C_FDIVHIGHCFG FDIVHIGHCFG; /**< \brief 1C, Fractional Divider High-speed Mode Configuration Register */
+ Ifx_I2C_ADDRCFG ADDRCFG; /**< \brief 20, Address Configuration Register */
+ Ifx_I2C_BUSSTAT BUSSTAT; /**< \brief 24, Bus Status Register */
+ Ifx_I2C_FIFOCFG FIFOCFG; /**< \brief 28, FIFO Configuration Register */
+ Ifx_I2C_MRPSCTRL MRPSCTRL; /**< \brief 2C, Maximum Received Packet Size Control Register */
+ Ifx_I2C_RPSSTAT RPSSTAT; /**< \brief 30, Received Packet Size Status Register */
+ Ifx_I2C_TPSCTRL TPSCTRL; /**< \brief 34, Transmit Packet Size Control Register */
+ Ifx_I2C_FFSSTAT FFSSTAT; /**< \brief 38, Filled FIFO Stages Status Register */
+ unsigned char reserved_3C[4]; /**< \brief 3C, \internal Reserved */
+ Ifx_I2C_TIMCFG TIMCFG; /**< \brief 40, Timing Configuration Register */
+ unsigned char reserved_44[28]; /**< \brief 44, \internal Reserved */
+ Ifx_I2C_ERRIRQSM ERRIRQSM; /**< \brief 60, Error Interrupt Request Source Mask Register */
+ Ifx_I2C_ERRIRQSS ERRIRQSS; /**< \brief 64, Error Interrupt Request Source Status Register */
+ Ifx_I2C_ERRIRQSC ERRIRQSC; /**< \brief 68, Error Interrupt Request Source Clear Register */
+ unsigned char reserved_6C[4]; /**< \brief 6C, \internal Reserved */
+ Ifx_I2C_PIRQSM PIRQSM; /**< \brief 70, Protocol Interrupt Request Source Mask Register */
+ Ifx_I2C_PIRQSS PIRQSS; /**< \brief 74, Protocol Interrupt Request Source Status Register */
+ Ifx_I2C_PIRQSC PIRQSC; /**< \brief 78, Protocol Interrupt Request Source Clear Register */
+ unsigned char reserved_7C[4]; /**< \brief 7C, \internal Reserved */
+ Ifx_I2C_RIS RIS; /**< \brief 80, Raw Interrupt Status Register */
+ Ifx_I2C_IMSC IMSC; /**< \brief 84, Interrupt Mask Control Register */
+ Ifx_I2C_MIS MIS; /**< \brief 88, Masked Interrupt Status Register */
+ Ifx_I2C_ICR ICR; /**< \brief 8C, Interrupt Clear Register */
+ Ifx_I2C_ISR ISR; /**< \brief 90, Interrupt Set Register */
+ unsigned char reserved_94[32620]; /**< \brief 94, \internal Reserved */
+ Ifx_I2C_TXD TXD; /**< \brief 8000, Transmission Data Register */
+ unsigned char reserved_8004[16380]; /**< \brief 8004, \internal Reserved */
+ Ifx_I2C_RXD RXD; /**< \brief C000, Reception Data Register */
+ unsigned char reserved_C004[16380]; /**< \brief C004, \internal Reserved */
+ Ifx_I2C_CLC CLC; /**< \brief 10000, Clock Control Register */
+ Ifx_I2C_MODID MODID; /**< \brief 10004, Module Identification Register */
+ Ifx_I2C_GPCTL GPCTL; /**< \brief 10008, General Purpose Control Register */
+ Ifx_I2C_ACCEN0 ACCEN0; /**< \brief 1000C, Access Enable Register 0 */
+ Ifx_I2C_ACCEN1 ACCEN1; /**< \brief 10010, Access Enable Register 1 */
+ Ifx_I2C_KRST0 KRST0; /**< \brief 10014, Kernel Reset Register 0 */
+ Ifx_I2C_KRST1 KRST1; /**< \brief 10018, Kernel Reset Register 1 */
+ Ifx_I2C_KRSTCLR KRSTCLR; /**< \brief 1001C, Kernel Reset Status Clear Register */
+ unsigned char reserved_10020[224]; /**< \brief 10020, \internal Reserved */
+} Ifx_I2C;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXI2C_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxInt_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxInt_bf.h
new file mode 100644
index 0000000..8196756
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxInt_bf.h
@@ -0,0 +1,990 @@
+/**
+ * \file IfxInt_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Int_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Int
+ *
+ */
+#ifndef IFXINT_BF_H
+#define IFXINT_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Int_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN0 */
+#define IFX_INT_ACCEN00_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN0 */
+#define IFX_INT_ACCEN00_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN0 */
+#define IFX_INT_ACCEN00_EN0_OFF (0u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN10 */
+#define IFX_INT_ACCEN00_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN10 */
+#define IFX_INT_ACCEN00_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN10 */
+#define IFX_INT_ACCEN00_EN10_OFF (10u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN11 */
+#define IFX_INT_ACCEN00_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN11 */
+#define IFX_INT_ACCEN00_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN11 */
+#define IFX_INT_ACCEN00_EN11_OFF (11u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN12 */
+#define IFX_INT_ACCEN00_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN12 */
+#define IFX_INT_ACCEN00_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN12 */
+#define IFX_INT_ACCEN00_EN12_OFF (12u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN13 */
+#define IFX_INT_ACCEN00_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN13 */
+#define IFX_INT_ACCEN00_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN13 */
+#define IFX_INT_ACCEN00_EN13_OFF (13u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN14 */
+#define IFX_INT_ACCEN00_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN14 */
+#define IFX_INT_ACCEN00_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN14 */
+#define IFX_INT_ACCEN00_EN14_OFF (14u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN15 */
+#define IFX_INT_ACCEN00_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN15 */
+#define IFX_INT_ACCEN00_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN15 */
+#define IFX_INT_ACCEN00_EN15_OFF (15u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN16 */
+#define IFX_INT_ACCEN00_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN16 */
+#define IFX_INT_ACCEN00_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN16 */
+#define IFX_INT_ACCEN00_EN16_OFF (16u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN17 */
+#define IFX_INT_ACCEN00_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN17 */
+#define IFX_INT_ACCEN00_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN17 */
+#define IFX_INT_ACCEN00_EN17_OFF (17u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN18 */
+#define IFX_INT_ACCEN00_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN18 */
+#define IFX_INT_ACCEN00_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN18 */
+#define IFX_INT_ACCEN00_EN18_OFF (18u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN19 */
+#define IFX_INT_ACCEN00_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN19 */
+#define IFX_INT_ACCEN00_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN19 */
+#define IFX_INT_ACCEN00_EN19_OFF (19u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN1 */
+#define IFX_INT_ACCEN00_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN1 */
+#define IFX_INT_ACCEN00_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN1 */
+#define IFX_INT_ACCEN00_EN1_OFF (1u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN20 */
+#define IFX_INT_ACCEN00_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN20 */
+#define IFX_INT_ACCEN00_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN20 */
+#define IFX_INT_ACCEN00_EN20_OFF (20u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN21 */
+#define IFX_INT_ACCEN00_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN21 */
+#define IFX_INT_ACCEN00_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN21 */
+#define IFX_INT_ACCEN00_EN21_OFF (21u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN22 */
+#define IFX_INT_ACCEN00_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN22 */
+#define IFX_INT_ACCEN00_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN22 */
+#define IFX_INT_ACCEN00_EN22_OFF (22u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN23 */
+#define IFX_INT_ACCEN00_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN23 */
+#define IFX_INT_ACCEN00_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN23 */
+#define IFX_INT_ACCEN00_EN23_OFF (23u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN24 */
+#define IFX_INT_ACCEN00_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN24 */
+#define IFX_INT_ACCEN00_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN24 */
+#define IFX_INT_ACCEN00_EN24_OFF (24u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN25 */
+#define IFX_INT_ACCEN00_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN25 */
+#define IFX_INT_ACCEN00_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN25 */
+#define IFX_INT_ACCEN00_EN25_OFF (25u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN26 */
+#define IFX_INT_ACCEN00_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN26 */
+#define IFX_INT_ACCEN00_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN26 */
+#define IFX_INT_ACCEN00_EN26_OFF (26u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN27 */
+#define IFX_INT_ACCEN00_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN27 */
+#define IFX_INT_ACCEN00_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN27 */
+#define IFX_INT_ACCEN00_EN27_OFF (27u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN28 */
+#define IFX_INT_ACCEN00_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN28 */
+#define IFX_INT_ACCEN00_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN28 */
+#define IFX_INT_ACCEN00_EN28_OFF (28u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN29 */
+#define IFX_INT_ACCEN00_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN29 */
+#define IFX_INT_ACCEN00_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN29 */
+#define IFX_INT_ACCEN00_EN29_OFF (29u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN2 */
+#define IFX_INT_ACCEN00_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN2 */
+#define IFX_INT_ACCEN00_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN2 */
+#define IFX_INT_ACCEN00_EN2_OFF (2u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN30 */
+#define IFX_INT_ACCEN00_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN30 */
+#define IFX_INT_ACCEN00_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN30 */
+#define IFX_INT_ACCEN00_EN30_OFF (30u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN31 */
+#define IFX_INT_ACCEN00_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN31 */
+#define IFX_INT_ACCEN00_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN31 */
+#define IFX_INT_ACCEN00_EN31_OFF (31u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN3 */
+#define IFX_INT_ACCEN00_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN3 */
+#define IFX_INT_ACCEN00_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN3 */
+#define IFX_INT_ACCEN00_EN3_OFF (3u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN4 */
+#define IFX_INT_ACCEN00_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN4 */
+#define IFX_INT_ACCEN00_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN4 */
+#define IFX_INT_ACCEN00_EN4_OFF (4u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN5 */
+#define IFX_INT_ACCEN00_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN5 */
+#define IFX_INT_ACCEN00_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN5 */
+#define IFX_INT_ACCEN00_EN5_OFF (5u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN6 */
+#define IFX_INT_ACCEN00_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN6 */
+#define IFX_INT_ACCEN00_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN6 */
+#define IFX_INT_ACCEN00_EN6_OFF (6u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN7 */
+#define IFX_INT_ACCEN00_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN7 */
+#define IFX_INT_ACCEN00_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN7 */
+#define IFX_INT_ACCEN00_EN7_OFF (7u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN8 */
+#define IFX_INT_ACCEN00_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN8 */
+#define IFX_INT_ACCEN00_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN8 */
+#define IFX_INT_ACCEN00_EN8_OFF (8u)
+
+/** \brief Length for Ifx_INT_ACCEN00_Bits.EN9 */
+#define IFX_INT_ACCEN00_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN9 */
+#define IFX_INT_ACCEN00_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN9 */
+#define IFX_INT_ACCEN00_EN9_OFF (9u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN0 */
+#define IFX_INT_ACCEN10_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN0 */
+#define IFX_INT_ACCEN10_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN0 */
+#define IFX_INT_ACCEN10_EN0_OFF (0u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN10 */
+#define IFX_INT_ACCEN10_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN10 */
+#define IFX_INT_ACCEN10_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN10 */
+#define IFX_INT_ACCEN10_EN10_OFF (10u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN11 */
+#define IFX_INT_ACCEN10_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN11 */
+#define IFX_INT_ACCEN10_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN11 */
+#define IFX_INT_ACCEN10_EN11_OFF (11u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN12 */
+#define IFX_INT_ACCEN10_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN12 */
+#define IFX_INT_ACCEN10_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN12 */
+#define IFX_INT_ACCEN10_EN12_OFF (12u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN13 */
+#define IFX_INT_ACCEN10_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN13 */
+#define IFX_INT_ACCEN10_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN13 */
+#define IFX_INT_ACCEN10_EN13_OFF (13u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN14 */
+#define IFX_INT_ACCEN10_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN14 */
+#define IFX_INT_ACCEN10_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN14 */
+#define IFX_INT_ACCEN10_EN14_OFF (14u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN15 */
+#define IFX_INT_ACCEN10_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN15 */
+#define IFX_INT_ACCEN10_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN15 */
+#define IFX_INT_ACCEN10_EN15_OFF (15u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN16 */
+#define IFX_INT_ACCEN10_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN16 */
+#define IFX_INT_ACCEN10_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN16 */
+#define IFX_INT_ACCEN10_EN16_OFF (16u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN17 */
+#define IFX_INT_ACCEN10_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN17 */
+#define IFX_INT_ACCEN10_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN17 */
+#define IFX_INT_ACCEN10_EN17_OFF (17u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN18 */
+#define IFX_INT_ACCEN10_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN18 */
+#define IFX_INT_ACCEN10_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN18 */
+#define IFX_INT_ACCEN10_EN18_OFF (18u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN19 */
+#define IFX_INT_ACCEN10_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN19 */
+#define IFX_INT_ACCEN10_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN19 */
+#define IFX_INT_ACCEN10_EN19_OFF (19u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN1 */
+#define IFX_INT_ACCEN10_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN1 */
+#define IFX_INT_ACCEN10_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN1 */
+#define IFX_INT_ACCEN10_EN1_OFF (1u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN20 */
+#define IFX_INT_ACCEN10_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN20 */
+#define IFX_INT_ACCEN10_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN20 */
+#define IFX_INT_ACCEN10_EN20_OFF (20u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN21 */
+#define IFX_INT_ACCEN10_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN21 */
+#define IFX_INT_ACCEN10_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN21 */
+#define IFX_INT_ACCEN10_EN21_OFF (21u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN22 */
+#define IFX_INT_ACCEN10_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN22 */
+#define IFX_INT_ACCEN10_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN22 */
+#define IFX_INT_ACCEN10_EN22_OFF (22u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN23 */
+#define IFX_INT_ACCEN10_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN23 */
+#define IFX_INT_ACCEN10_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN23 */
+#define IFX_INT_ACCEN10_EN23_OFF (23u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN24 */
+#define IFX_INT_ACCEN10_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN24 */
+#define IFX_INT_ACCEN10_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN24 */
+#define IFX_INT_ACCEN10_EN24_OFF (24u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN25 */
+#define IFX_INT_ACCEN10_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN25 */
+#define IFX_INT_ACCEN10_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN25 */
+#define IFX_INT_ACCEN10_EN25_OFF (25u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN26 */
+#define IFX_INT_ACCEN10_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN26 */
+#define IFX_INT_ACCEN10_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN26 */
+#define IFX_INT_ACCEN10_EN26_OFF (26u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN27 */
+#define IFX_INT_ACCEN10_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN27 */
+#define IFX_INT_ACCEN10_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN27 */
+#define IFX_INT_ACCEN10_EN27_OFF (27u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN28 */
+#define IFX_INT_ACCEN10_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN28 */
+#define IFX_INT_ACCEN10_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN28 */
+#define IFX_INT_ACCEN10_EN28_OFF (28u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN29 */
+#define IFX_INT_ACCEN10_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN29 */
+#define IFX_INT_ACCEN10_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN29 */
+#define IFX_INT_ACCEN10_EN29_OFF (29u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN2 */
+#define IFX_INT_ACCEN10_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN2 */
+#define IFX_INT_ACCEN10_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN2 */
+#define IFX_INT_ACCEN10_EN2_OFF (2u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN30 */
+#define IFX_INT_ACCEN10_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN30 */
+#define IFX_INT_ACCEN10_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN30 */
+#define IFX_INT_ACCEN10_EN30_OFF (30u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN31 */
+#define IFX_INT_ACCEN10_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN31 */
+#define IFX_INT_ACCEN10_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN31 */
+#define IFX_INT_ACCEN10_EN31_OFF (31u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN3 */
+#define IFX_INT_ACCEN10_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN3 */
+#define IFX_INT_ACCEN10_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN3 */
+#define IFX_INT_ACCEN10_EN3_OFF (3u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN4 */
+#define IFX_INT_ACCEN10_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN4 */
+#define IFX_INT_ACCEN10_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN4 */
+#define IFX_INT_ACCEN10_EN4_OFF (4u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN5 */
+#define IFX_INT_ACCEN10_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN5 */
+#define IFX_INT_ACCEN10_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN5 */
+#define IFX_INT_ACCEN10_EN5_OFF (5u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN6 */
+#define IFX_INT_ACCEN10_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN6 */
+#define IFX_INT_ACCEN10_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN6 */
+#define IFX_INT_ACCEN10_EN6_OFF (6u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN7 */
+#define IFX_INT_ACCEN10_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN7 */
+#define IFX_INT_ACCEN10_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN7 */
+#define IFX_INT_ACCEN10_EN7_OFF (7u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN8 */
+#define IFX_INT_ACCEN10_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN8 */
+#define IFX_INT_ACCEN10_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN8 */
+#define IFX_INT_ACCEN10_EN8_OFF (8u)
+
+/** \brief Length for Ifx_INT_ACCEN10_Bits.EN9 */
+#define IFX_INT_ACCEN10_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN9 */
+#define IFX_INT_ACCEN10_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN9 */
+#define IFX_INT_ACCEN10_EN9_OFF (9u)
+
+/** \brief Length for Ifx_INT_ICU_ECR_Bits.ECC */
+#define IFX_INT_ICU_ECR_ECC_LEN (6u)
+
+/** \brief Mask for Ifx_INT_ICU_ECR_Bits.ECC */
+#define IFX_INT_ICU_ECR_ECC_MSK (0x3fu)
+
+/** \brief Offset for Ifx_INT_ICU_ECR_Bits.ECC */
+#define IFX_INT_ICU_ECR_ECC_OFF (10u)
+
+/** \brief Length for Ifx_INT_ICU_ECR_Bits.EOV */
+#define IFX_INT_ICU_ECR_EOV_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ICU_ECR_Bits.EOV */
+#define IFX_INT_ICU_ECR_EOV_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ICU_ECR_Bits.EOV */
+#define IFX_INT_ICU_ECR_EOV_OFF (30u)
+
+/** \brief Length for Ifx_INT_ICU_ECR_Bits.ID */
+#define IFX_INT_ICU_ECR_ID_LEN (10u)
+
+/** \brief Mask for Ifx_INT_ICU_ECR_Bits.ID */
+#define IFX_INT_ICU_ECR_ID_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_INT_ICU_ECR_Bits.ID */
+#define IFX_INT_ICU_ECR_ID_OFF (16u)
+
+/** \brief Length for Ifx_INT_ICU_ECR_Bits.PN */
+#define IFX_INT_ICU_ECR_PN_LEN (8u)
+
+/** \brief Mask for Ifx_INT_ICU_ECR_Bits.PN */
+#define IFX_INT_ICU_ECR_PN_MSK (0xffu)
+
+/** \brief Offset for Ifx_INT_ICU_ECR_Bits.PN */
+#define IFX_INT_ICU_ECR_PN_OFF (0u)
+
+/** \brief Length for Ifx_INT_ICU_ECR_Bits.STAT */
+#define IFX_INT_ICU_ECR_STAT_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ICU_ECR_Bits.STAT */
+#define IFX_INT_ICU_ECR_STAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ICU_ECR_Bits.STAT */
+#define IFX_INT_ICU_ECR_STAT_OFF (31u)
+
+/** \brief Length for Ifx_INT_ICU_LASR_Bits.ECC */
+#define IFX_INT_ICU_LASR_ECC_LEN (6u)
+
+/** \brief Mask for Ifx_INT_ICU_LASR_Bits.ECC */
+#define IFX_INT_ICU_LASR_ECC_MSK (0x3fu)
+
+/** \brief Offset for Ifx_INT_ICU_LASR_Bits.ECC */
+#define IFX_INT_ICU_LASR_ECC_OFF (10u)
+
+/** \brief Length for Ifx_INT_ICU_LASR_Bits.ID */
+#define IFX_INT_ICU_LASR_ID_LEN (10u)
+
+/** \brief Mask for Ifx_INT_ICU_LASR_Bits.ID */
+#define IFX_INT_ICU_LASR_ID_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_INT_ICU_LASR_Bits.ID */
+#define IFX_INT_ICU_LASR_ID_OFF (16u)
+
+/** \brief Length for Ifx_INT_ICU_LASR_Bits.PN */
+#define IFX_INT_ICU_LASR_PN_LEN (8u)
+
+/** \brief Mask for Ifx_INT_ICU_LASR_Bits.PN */
+#define IFX_INT_ICU_LASR_PN_MSK (0xffu)
+
+/** \brief Offset for Ifx_INT_ICU_LASR_Bits.PN */
+#define IFX_INT_ICU_LASR_PN_OFF (0u)
+
+/** \brief Length for Ifx_INT_ICU_LWSR_Bits.ECC */
+#define IFX_INT_ICU_LWSR_ECC_LEN (6u)
+
+/** \brief Mask for Ifx_INT_ICU_LWSR_Bits.ECC */
+#define IFX_INT_ICU_LWSR_ECC_MSK (0x3fu)
+
+/** \brief Offset for Ifx_INT_ICU_LWSR_Bits.ECC */
+#define IFX_INT_ICU_LWSR_ECC_OFF (10u)
+
+/** \brief Length for Ifx_INT_ICU_LWSR_Bits.ID */
+#define IFX_INT_ICU_LWSR_ID_LEN (10u)
+
+/** \brief Mask for Ifx_INT_ICU_LWSR_Bits.ID */
+#define IFX_INT_ICU_LWSR_ID_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_INT_ICU_LWSR_Bits.ID */
+#define IFX_INT_ICU_LWSR_ID_OFF (16u)
+
+/** \brief Length for Ifx_INT_ICU_LWSR_Bits.PN */
+#define IFX_INT_ICU_LWSR_PN_LEN (8u)
+
+/** \brief Mask for Ifx_INT_ICU_LWSR_Bits.PN */
+#define IFX_INT_ICU_LWSR_PN_MSK (0xffu)
+
+/** \brief Offset for Ifx_INT_ICU_LWSR_Bits.PN */
+#define IFX_INT_ICU_LWSR_PN_OFF (0u)
+
+/** \brief Length for Ifx_INT_ICU_LWSR_Bits.STAT */
+#define IFX_INT_ICU_LWSR_STAT_LEN (1u)
+
+/** \brief Mask for Ifx_INT_ICU_LWSR_Bits.STAT */
+#define IFX_INT_ICU_LWSR_STAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_ICU_LWSR_Bits.STAT */
+#define IFX_INT_ICU_LWSR_STAT_OFF (31u)
+
+/** \brief Length for Ifx_INT_ID_Bits.MODNUMBER */
+#define IFX_INT_ID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_INT_ID_Bits.MODNUMBER */
+#define IFX_INT_ID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_INT_ID_Bits.MODNUMBER */
+#define IFX_INT_ID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_INT_ID_Bits.MODREV */
+#define IFX_INT_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_INT_ID_Bits.MODREV */
+#define IFX_INT_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_INT_ID_Bits.MODREV */
+#define IFX_INT_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_INT_ID_Bits.MODTYPE */
+#define IFX_INT_ID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_INT_ID_Bits.MODTYPE */
+#define IFX_INT_ID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_INT_ID_Bits.MODTYPE */
+#define IFX_INT_ID_MODTYPE_OFF (8u)
+
+/** \brief Length for Ifx_INT_OIT_Bits.OE0 */
+#define IFX_INT_OIT_OE0_LEN (1u)
+
+/** \brief Mask for Ifx_INT_OIT_Bits.OE0 */
+#define IFX_INT_OIT_OE0_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_OIT_Bits.OE0 */
+#define IFX_INT_OIT_OE0_OFF (7u)
+
+/** \brief Length for Ifx_INT_OIT_Bits.OE1 */
+#define IFX_INT_OIT_OE1_LEN (1u)
+
+/** \brief Mask for Ifx_INT_OIT_Bits.OE1 */
+#define IFX_INT_OIT_OE1_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_OIT_Bits.OE1 */
+#define IFX_INT_OIT_OE1_OFF (15u)
+
+/** \brief Length for Ifx_INT_OIT_Bits.TOS0 */
+#define IFX_INT_OIT_TOS0_LEN (2u)
+
+/** \brief Mask for Ifx_INT_OIT_Bits.TOS0 */
+#define IFX_INT_OIT_TOS0_MSK (0x3u)
+
+/** \brief Offset for Ifx_INT_OIT_Bits.TOS0 */
+#define IFX_INT_OIT_TOS0_OFF (0u)
+
+/** \brief Length for Ifx_INT_OIT_Bits.TOS1 */
+#define IFX_INT_OIT_TOS1_LEN (2u)
+
+/** \brief Mask for Ifx_INT_OIT_Bits.TOS1 */
+#define IFX_INT_OIT_TOS1_MSK (0x3u)
+
+/** \brief Offset for Ifx_INT_OIT_Bits.TOS1 */
+#define IFX_INT_OIT_TOS1_OFF (8u)
+
+/** \brief Length for Ifx_INT_OIXMS_Bits.MIRQ */
+#define IFX_INT_OIXMS_MIRQ_LEN (10u)
+
+/** \brief Mask for Ifx_INT_OIXMS_Bits.MIRQ */
+#define IFX_INT_OIXMS_MIRQ_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_INT_OIXMS_Bits.MIRQ */
+#define IFX_INT_OIXMS_MIRQ_OFF (0u)
+
+/** \brief Length for Ifx_INT_OIXS0_Bits.IRQ0 */
+#define IFX_INT_OIXS0_IRQ0_LEN (10u)
+
+/** \brief Mask for Ifx_INT_OIXS0_Bits.IRQ0 */
+#define IFX_INT_OIXS0_IRQ0_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_INT_OIXS0_Bits.IRQ0 */
+#define IFX_INT_OIXS0_IRQ0_OFF (0u)
+
+/** \brief Length for Ifx_INT_OIXS0_Bits.IRQ1 */
+#define IFX_INT_OIXS0_IRQ1_LEN (10u)
+
+/** \brief Mask for Ifx_INT_OIXS0_Bits.IRQ1 */
+#define IFX_INT_OIXS0_IRQ1_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_INT_OIXS0_Bits.IRQ1 */
+#define IFX_INT_OIXS0_IRQ1_OFF (16u)
+
+/** \brief Length for Ifx_INT_OIXS1_Bits.IRQ2 */
+#define IFX_INT_OIXS1_IRQ2_LEN (10u)
+
+/** \brief Mask for Ifx_INT_OIXS1_Bits.IRQ2 */
+#define IFX_INT_OIXS1_IRQ2_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_INT_OIXS1_Bits.IRQ2 */
+#define IFX_INT_OIXS1_IRQ2_OFF (0u)
+
+/** \brief Length for Ifx_INT_OIXS1_Bits.IRQ3 */
+#define IFX_INT_OIXS1_IRQ3_LEN (10u)
+
+/** \brief Mask for Ifx_INT_OIXS1_Bits.IRQ3 */
+#define IFX_INT_OIXS1_IRQ3_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_INT_OIXS1_Bits.IRQ3 */
+#define IFX_INT_OIXS1_IRQ3_OFF (16u)
+
+/** \brief Length for Ifx_INT_OIXTS_Bits.OBS */
+#define IFX_INT_OIXTS_OBS_LEN (2u)
+
+/** \brief Mask for Ifx_INT_OIXTS_Bits.OBS */
+#define IFX_INT_OIXTS_OBS_MSK (0x3u)
+
+/** \brief Offset for Ifx_INT_OIXTS_Bits.OBS */
+#define IFX_INT_OIXTS_OBS_OFF (8u)
+
+/** \brief Length for Ifx_INT_OIXTS_Bits.TGS */
+#define IFX_INT_OIXTS_TGS_LEN (2u)
+
+/** \brief Mask for Ifx_INT_OIXTS_Bits.TGS */
+#define IFX_INT_OIXTS_TGS_MSK (0x3u)
+
+/** \brief Offset for Ifx_INT_OIXTS_Bits.TGS */
+#define IFX_INT_OIXTS_TGS_OFF (0u)
+
+/** \brief Length for Ifx_INT_OMISN_Bits.OTGB0 */
+#define IFX_INT_OMISN_OTGB0_LEN (16u)
+
+/** \brief Mask for Ifx_INT_OMISN_Bits.OTGB0 */
+#define IFX_INT_OMISN_OTGB0_MSK (0xffffu)
+
+/** \brief Offset for Ifx_INT_OMISN_Bits.OTGB0 */
+#define IFX_INT_OMISN_OTGB0_OFF (0u)
+
+/** \brief Length for Ifx_INT_OMISN_Bits.OTGB1 */
+#define IFX_INT_OMISN_OTGB1_LEN (16u)
+
+/** \brief Mask for Ifx_INT_OMISN_Bits.OTGB1 */
+#define IFX_INT_OMISN_OTGB1_MSK (0xffffu)
+
+/** \brief Offset for Ifx_INT_OMISN_Bits.OTGB1 */
+#define IFX_INT_OMISN_OTGB1_OFF (16u)
+
+/** \brief Length for Ifx_INT_OMISP_Bits.OTGB0 */
+#define IFX_INT_OMISP_OTGB0_LEN (16u)
+
+/** \brief Mask for Ifx_INT_OMISP_Bits.OTGB0 */
+#define IFX_INT_OMISP_OTGB0_MSK (0xffffu)
+
+/** \brief Offset for Ifx_INT_OMISP_Bits.OTGB0 */
+#define IFX_INT_OMISP_OTGB0_OFF (0u)
+
+/** \brief Length for Ifx_INT_OMISP_Bits.OTGB1 */
+#define IFX_INT_OMISP_OTGB1_LEN (16u)
+
+/** \brief Mask for Ifx_INT_OMISP_Bits.OTGB1 */
+#define IFX_INT_OMISP_OTGB1_MSK (0xffffu)
+
+/** \brief Offset for Ifx_INT_OMISP_Bits.OTGB1 */
+#define IFX_INT_OMISP_OTGB1_OFF (16u)
+
+/** \brief Length for Ifx_INT_OOBS_Bits.OTGB0 */
+#define IFX_INT_OOBS_OTGB0_LEN (16u)
+
+/** \brief Mask for Ifx_INT_OOBS_Bits.OTGB0 */
+#define IFX_INT_OOBS_OTGB0_MSK (0xffffu)
+
+/** \brief Offset for Ifx_INT_OOBS_Bits.OTGB0 */
+#define IFX_INT_OOBS_OTGB0_OFF (0u)
+
+/** \brief Length for Ifx_INT_OOBS_Bits.OTGB1 */
+#define IFX_INT_OOBS_OTGB1_LEN (16u)
+
+/** \brief Mask for Ifx_INT_OOBS_Bits.OTGB1 */
+#define IFX_INT_OOBS_OTGB1_MSK (0xffffu)
+
+/** \brief Offset for Ifx_INT_OOBS_Bits.OTGB1 */
+#define IFX_INT_OOBS_OTGB1_OFF (16u)
+
+/** \brief Length for Ifx_INT_OSSIC_Bits.TGB */
+#define IFX_INT_OSSIC_TGB_LEN (1u)
+
+/** \brief Mask for Ifx_INT_OSSIC_Bits.TGB */
+#define IFX_INT_OSSIC_TGB_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_OSSIC_Bits.TGB */
+#define IFX_INT_OSSIC_TGB_OFF (2u)
+
+/** \brief Length for Ifx_INT_OSSIC_Bits.TGS */
+#define IFX_INT_OSSIC_TGS_LEN (2u)
+
+/** \brief Mask for Ifx_INT_OSSIC_Bits.TGS */
+#define IFX_INT_OSSIC_TGS_MSK (0x3u)
+
+/** \brief Offset for Ifx_INT_OSSIC_Bits.TGS */
+#define IFX_INT_OSSIC_TGS_OFF (0u)
+
+/** \brief Length for Ifx_INT_SRB0_Bits.TRIG0 */
+#define IFX_INT_SRB0_TRIG0_LEN (1u)
+
+/** \brief Mask for Ifx_INT_SRB0_Bits.TRIG0 */
+#define IFX_INT_SRB0_TRIG0_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_SRB0_Bits.TRIG0 */
+#define IFX_INT_SRB0_TRIG0_OFF (0u)
+
+/** \brief Length for Ifx_INT_SRB0_Bits.TRIG1 */
+#define IFX_INT_SRB0_TRIG1_LEN (1u)
+
+/** \brief Mask for Ifx_INT_SRB0_Bits.TRIG1 */
+#define IFX_INT_SRB0_TRIG1_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_SRB0_Bits.TRIG1 */
+#define IFX_INT_SRB0_TRIG1_OFF (1u)
+
+/** \brief Length for Ifx_INT_SRB0_Bits.TRIG2 */
+#define IFX_INT_SRB0_TRIG2_LEN (1u)
+
+/** \brief Mask for Ifx_INT_SRB0_Bits.TRIG2 */
+#define IFX_INT_SRB0_TRIG2_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_SRB0_Bits.TRIG2 */
+#define IFX_INT_SRB0_TRIG2_OFF (2u)
+
+/** \brief Length for Ifx_INT_SRB0_Bits.TRIG3 */
+#define IFX_INT_SRB0_TRIG3_LEN (1u)
+
+/** \brief Mask for Ifx_INT_SRB0_Bits.TRIG3 */
+#define IFX_INT_SRB0_TRIG3_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_SRB0_Bits.TRIG3 */
+#define IFX_INT_SRB0_TRIG3_OFF (3u)
+
+/** \brief Length for Ifx_INT_SRB1_Bits.TRIG0 */
+#define IFX_INT_SRB1_TRIG0_LEN (1u)
+
+/** \brief Mask for Ifx_INT_SRB1_Bits.TRIG0 */
+#define IFX_INT_SRB1_TRIG0_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_SRB1_Bits.TRIG0 */
+#define IFX_INT_SRB1_TRIG0_OFF (0u)
+
+/** \brief Length for Ifx_INT_SRB1_Bits.TRIG1 */
+#define IFX_INT_SRB1_TRIG1_LEN (1u)
+
+/** \brief Mask for Ifx_INT_SRB1_Bits.TRIG1 */
+#define IFX_INT_SRB1_TRIG1_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_SRB1_Bits.TRIG1 */
+#define IFX_INT_SRB1_TRIG1_OFF (1u)
+
+/** \brief Length for Ifx_INT_SRB1_Bits.TRIG2 */
+#define IFX_INT_SRB1_TRIG2_LEN (1u)
+
+/** \brief Mask for Ifx_INT_SRB1_Bits.TRIG2 */
+#define IFX_INT_SRB1_TRIG2_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_SRB1_Bits.TRIG2 */
+#define IFX_INT_SRB1_TRIG2_OFF (2u)
+
+/** \brief Length for Ifx_INT_SRB1_Bits.TRIG3 */
+#define IFX_INT_SRB1_TRIG3_LEN (1u)
+
+/** \brief Mask for Ifx_INT_SRB1_Bits.TRIG3 */
+#define IFX_INT_SRB1_TRIG3_MSK (0x1u)
+
+/** \brief Offset for Ifx_INT_SRB1_Bits.TRIG3 */
+#define IFX_INT_SRB1_TRIG3_OFF (3u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXINT_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxInt_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxInt_reg.h
new file mode 100644
index 0000000..22aa9fa
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxInt_reg.h
@@ -0,0 +1,171 @@
+/**
+ * \file IfxInt_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Int_Cfg Int address
+ * \ingroup IfxLld_Int
+ *
+ * \defgroup IfxLld_Int_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Int_Cfg
+ *
+ * \defgroup IfxLld_Int_Cfg_Int 2-INT
+ * \ingroup IfxLld_Int_Cfg
+ *
+ */
+#ifndef IFXINT_REG_H
+#define IFXINT_REG_H 1
+/******************************************************************************/
+#include "IfxInt_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Int_Cfg_BaseAddress
+ * \{ */
+
+/** \brief Interrupt router object */
+#define MODULE_INT /*lint --e(923)*/ (*(Ifx_INT*)0xF0037000u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Int_Cfg_Int
+ * \{ */
+
+/** \brief F4, Access Enable Register 0 */
+#define INT_ACCEN00 /*lint --e(923)*/ (*(volatile Ifx_INT_ACCEN00*)0xF00370F4u)
+
+/** \brief F0, Kernel 0 Access Enable Register 1 */
+#define INT_ACCEN01 /*lint --e(923)*/ (*(volatile Ifx_INT_ACCEN01*)0xF00370F0u)
+
+/** \brief FC, Kernel 1 Access Enable Register 0 */
+#define INT_ACCEN10 /*lint --e(923)*/ (*(volatile Ifx_INT_ACCEN10*)0xF00370FCu)
+
+/** \brief F8, Kernel 1 Access Enable Register 1 */
+#define INT_ACCEN11 /*lint --e(923)*/ (*(volatile Ifx_INT_ACCEN11*)0xF00370F8u)
+
+/** \brief 108, Error Capture Register */
+#define INT_CH0_ECR /*lint --e(923)*/ (*(volatile Ifx_INT_ICU_ECR*)0xF0037108u)
+
+/** Alias (User Manual Name) for INT_CH0_ECR.
+* To use register names with standard convension, please use INT_CH0_ECR.
+*/
+#define INT_ECR0 (INT_CH0_ECR)
+
+/** \brief 104, Last Acknowledged Service Request Register */
+#define INT_CH0_LASR /*lint --e(923)*/ (*(volatile Ifx_INT_ICU_LASR*)0xF0037104u)
+
+/** Alias (User Manual Name) for INT_CH0_LASR.
+* To use register names with standard convension, please use INT_CH0_LASR.
+*/
+#define INT_LASR0 (INT_CH0_LASR)
+
+/** \brief 100, Latest Winning Service Request Register */
+#define INT_CH0_LWSR /*lint --e(923)*/ (*(volatile Ifx_INT_ICU_LWSR*)0xF0037100u)
+
+/** Alias (User Manual Name) for INT_CH0_LWSR.
+* To use register names with standard convension, please use INT_CH0_LWSR.
+*/
+#define INT_LWSR0 (INT_CH0_LWSR)
+
+/** \brief 118, Error Capture Register */
+#define INT_CH1_ECR /*lint --e(923)*/ (*(volatile Ifx_INT_ICU_ECR*)0xF0037118u)
+
+/** Alias (User Manual Name) for INT_CH1_ECR.
+* To use register names with standard convension, please use INT_CH1_ECR.
+*/
+#define INT_ECR1 (INT_CH1_ECR)
+
+/** \brief 114, Last Acknowledged Service Request Register */
+#define INT_CH1_LASR /*lint --e(923)*/ (*(volatile Ifx_INT_ICU_LASR*)0xF0037114u)
+
+/** Alias (User Manual Name) for INT_CH1_LASR.
+* To use register names with standard convension, please use INT_CH1_LASR.
+*/
+#define INT_LASR1 (INT_CH1_LASR)
+
+/** \brief 110, Latest Winning Service Request Register */
+#define INT_CH1_LWSR /*lint --e(923)*/ (*(volatile Ifx_INT_ICU_LWSR*)0xF0037110u)
+
+/** Alias (User Manual Name) for INT_CH1_LWSR.
+* To use register names with standard convension, please use INT_CH1_LWSR.
+*/
+#define INT_LWSR1 (INT_CH1_LWSR)
+
+/** \brief 138, Error Capture Register */
+#define INT_CH3_ECR /*lint --e(923)*/ (*(volatile Ifx_INT_ICU_ECR*)0xF0037138u)
+
+/** Alias (User Manual Name) for INT_CH3_ECR.
+* To use register names with standard convension, please use INT_CH3_ECR.
+*/
+#define INT_ECR3 (INT_CH3_ECR)
+
+/** \brief 134, Last Acknowledged Service Request Register */
+#define INT_CH3_LASR /*lint --e(923)*/ (*(volatile Ifx_INT_ICU_LASR*)0xF0037134u)
+
+/** Alias (User Manual Name) for INT_CH3_LASR.
+* To use register names with standard convension, please use INT_CH3_LASR.
+*/
+#define INT_LASR3 (INT_CH3_LASR)
+
+/** \brief 130, Latest Winning Service Request Register */
+#define INT_CH3_LWSR /*lint --e(923)*/ (*(volatile Ifx_INT_ICU_LWSR*)0xF0037130u)
+
+/** Alias (User Manual Name) for INT_CH3_LWSR.
+* To use register names with standard convension, please use INT_CH3_LWSR.
+*/
+#define INT_LWSR3 (INT_CH3_LWSR)
+
+/** \brief 8, Module Identification Register */
+#define INT_ID /*lint --e(923)*/ (*(volatile Ifx_INT_ID*)0xF0037008u)
+
+/** \brief A0, OTGM IRQ Trace */
+#define INT_OIT /*lint --e(923)*/ (*(volatile Ifx_INT_OIT*)0xF00370A0u)
+
+/** \brief 8C, OTGM IRQ MUX Missed IRQ Select */
+#define INT_OIXMS /*lint --e(923)*/ (*(volatile Ifx_INT_OIXMS*)0xF003708Cu)
+
+/** \brief 90, OTGM IRQ MUX Select 0 */
+#define INT_OIXS0 /*lint --e(923)*/ (*(volatile Ifx_INT_OIXS0*)0xF0037090u)
+
+/** \brief 94, OTGM IRQ MUX Select 1 */
+#define INT_OIXS1 /*lint --e(923)*/ (*(volatile Ifx_INT_OIXS1*)0xF0037094u)
+
+/** \brief 88, OTGM IRQ MUX Trigger Set Select */
+#define INT_OIXTS /*lint --e(923)*/ (*(volatile Ifx_INT_OIXTS*)0xF0037088u)
+
+/** \brief A8, OTGM MCDS I/F Sensitivity Negedge */
+#define INT_OMISN /*lint --e(923)*/ (*(volatile Ifx_INT_OMISN*)0xF00370A8u)
+
+/** \brief A4, OTGM MCDS I/F Sensitivity Posedge */
+#define INT_OMISP /*lint --e(923)*/ (*(volatile Ifx_INT_OMISP*)0xF00370A4u)
+
+/** \brief 80, OTGM OTGB0/1 Status */
+#define INT_OOBS /*lint --e(923)*/ (*(volatile Ifx_INT_OOBS*)0xF0037080u)
+
+/** \brief 84, OTGM SSI Control */
+#define INT_OSSIC /*lint --e(923)*/ (*(volatile Ifx_INT_OSSIC*)0xF0037084u)
+
+/** \brief 10, Service Request Broadcast Register 0 */
+#define INT_SRB0 /*lint --e(923)*/ (*(volatile Ifx_INT_SRB0*)0xF0037010u)
+
+/** \brief 14, Service Request Broadcast Register 1 */
+#define INT_SRB1 /*lint --e(923)*/ (*(volatile Ifx_INT_SRB1*)0xF0037014u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXINT_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxInt_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxInt_regdef.h
new file mode 100644
index 0000000..854c586
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxInt_regdef.h
@@ -0,0 +1,482 @@
+/**
+ * \file IfxInt_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Int Int
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Int_Bitfields Bitfields
+ * \ingroup IfxLld_Int
+ *
+ * \defgroup IfxLld_Int_union Union
+ * \ingroup IfxLld_Int
+ *
+ * \defgroup IfxLld_Int_struct Struct
+ * \ingroup IfxLld_Int
+ *
+ */
+#ifndef IFXINT_REGDEF_H
+#define IFXINT_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Int_Bitfields
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef struct _Ifx_INT_ACCEN00_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_INT_ACCEN00_Bits;
+
+/** \brief Kernel 0 Access Enable Register 1 */
+typedef struct _Ifx_INT_ACCEN01_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_INT_ACCEN01_Bits;
+
+/** \brief Kernel 1 Access Enable Register 0 */
+typedef struct _Ifx_INT_ACCEN10_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_INT_ACCEN10_Bits;
+
+/** \brief Kernel 1 Access Enable Register 1 */
+typedef struct _Ifx_INT_ACCEN11_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_INT_ACCEN11_Bits;
+
+/** \brief Error Capture Register */
+typedef struct _Ifx_INT_ICU_ECR_Bits
+{
+ unsigned int PN:8; /**< \brief [7:0] Service Request Priority Number (rwh) */
+ unsigned int reserved_8:2; /**< \brief \internal Reserved */
+ unsigned int ECC:6; /**< \brief [15:10] Service Request ECC (rwh) */
+ unsigned int ID:10; /**< \brief [25:16] Service Request Node Index Number (rwh) */
+ unsigned int reserved_26:4; /**< \brief \internal Reserved */
+ unsigned int EOV:1; /**< \brief [30:30] Error Overflow Bit (rwh) */
+ unsigned int STAT:1; /**< \brief [31:31] Error Status Bit (rwh) */
+} Ifx_INT_ICU_ECR_Bits;
+
+/** \brief Last Acknowledged Service Request Register */
+typedef struct _Ifx_INT_ICU_LASR_Bits
+{
+ unsigned int PN:8; /**< \brief [7:0] Last Acknowledged Service Request Priority Number (r) */
+ unsigned int reserved_8:2; /**< \brief \internal Reserved */
+ unsigned int ECC:6; /**< \brief [15:10] Last Acknowledged Interrupt ECC (r) */
+ unsigned int ID:10; /**< \brief [25:16] Last Acknowledged Interrupt SRN Index Number (r) */
+ unsigned int reserved_26:6; /**< \brief \internal Reserved */
+} Ifx_INT_ICU_LASR_Bits;
+
+/** \brief Latest Winning Service Request Register */
+typedef struct _Ifx_INT_ICU_LWSR_Bits
+{
+ unsigned int PN:8; /**< \brief [7:0] Latest Winner Priority Number (r) */
+ unsigned int reserved_8:2; /**< \brief \internal Reserved */
+ unsigned int ECC:6; /**< \brief [15:10] Latest Winner ECC (r) */
+ unsigned int ID:10; /**< \brief [25:16] Latest Winner Index Number (r) */
+ unsigned int reserved_26:5; /**< \brief \internal Reserved */
+ unsigned int STAT:1; /**< \brief [31:31] LWSR Register Status (r) */
+} Ifx_INT_ICU_LWSR_Bits;
+
+/** \brief Module Identification Register */
+typedef struct _Ifx_INT_ID_Bits
+{
+ unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
+ unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_INT_ID_Bits;
+
+/** \brief OTGM IRQ Trace */
+typedef struct _Ifx_INT_OIT_Bits
+{
+ unsigned int TOS0:2; /**< \brief [1:0] Type of Service for Observation on OTGB0 (rw) */
+ unsigned int reserved_2:5; /**< \brief \internal Reserved */
+ unsigned int OE0:1; /**< \brief [7:7] Output Enable for OTGB0 (rw) */
+ unsigned int TOS1:2; /**< \brief [9:8] Type of Service for Observation on OTGB1 (rw) */
+ unsigned int reserved_10:5; /**< \brief \internal Reserved */
+ unsigned int OE1:1; /**< \brief [15:15] Output Enable for OTGB1 (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_INT_OIT_Bits;
+
+/** \brief OTGM IRQ MUX Missed IRQ Select */
+typedef struct _Ifx_INT_OIXMS_Bits
+{
+ unsigned int MIRQ:10; /**< \brief [9:0] SRN Index for Missed Interrupt Trigger (rw) */
+ unsigned int reserved_10:22; /**< \brief \internal Reserved */
+} Ifx_INT_OIXMS_Bits;
+
+/** \brief OTGM IRQ MUX Select 0 */
+typedef struct _Ifx_INT_OIXS0_Bits
+{
+ unsigned int IRQ0:10; /**< \brief [9:0] SRN Index for Interrupt Trigger 0 (rw) */
+ unsigned int reserved_10:6; /**< \brief \internal Reserved */
+ unsigned int IRQ1:10; /**< \brief [25:16] SRN Index for Interrupt Trigger 1 (rw) */
+ unsigned int reserved_26:6; /**< \brief \internal Reserved */
+} Ifx_INT_OIXS0_Bits;
+
+/** \brief OTGM IRQ MUX Select 1 */
+typedef struct _Ifx_INT_OIXS1_Bits
+{
+ unsigned int IRQ2:10; /**< \brief [9:0] SRN Index for Interrupt Trigger 2 (rw) */
+ unsigned int reserved_10:6; /**< \brief \internal Reserved */
+ unsigned int IRQ3:10; /**< \brief [25:16] SRN Index for Interrupt Trigger 3 (rw) */
+ unsigned int reserved_26:6; /**< \brief \internal Reserved */
+} Ifx_INT_OIXS1_Bits;
+
+/** \brief OTGM IRQ MUX Trigger Set Select */
+typedef struct _Ifx_INT_OIXTS_Bits
+{
+ unsigned int TGS:2; /**< \brief [1:0] Trigger Set Select for OTGB0/1 Overlay (rw) */
+ unsigned int reserved_2:6; /**< \brief \internal Reserved */
+ unsigned int OBS:2; /**< \brief [9:8] Overlay Byte Select (rw) */
+ unsigned int reserved_10:22; /**< \brief \internal Reserved */
+} Ifx_INT_OIXTS_Bits;
+
+/** \brief OTGM MCDS I/F Sensitivity Negedge */
+typedef struct _Ifx_INT_OMISN_Bits
+{
+ unsigned int OTGB0:16; /**< \brief [15:0] Bitwise Negedge Sensitivity for OTGB0 (rw) */
+ unsigned int OTGB1:16; /**< \brief [31:16] Bitwise Negedge Sensitivity for OTGB1 (rw) */
+} Ifx_INT_OMISN_Bits;
+
+/** \brief OTGM MCDS I/F Sensitivity Posedge */
+typedef struct _Ifx_INT_OMISP_Bits
+{
+ unsigned int OTGB0:16; /**< \brief [15:0] Bitwise Posedge Sensitivity for OTGB0 (rw) */
+ unsigned int OTGB1:16; /**< \brief [31:16] Bitwise Posedge Sensitivity for OTGB1 (rw) */
+} Ifx_INT_OMISP_Bits;
+
+/** \brief OTGM OTGB0/1 Status */
+typedef struct _Ifx_INT_OOBS_Bits
+{
+ unsigned int OTGB0:16; /**< \brief [15:0] Status of OTGB0 (rh) */
+ unsigned int OTGB1:16; /**< \brief [31:16] Status of OTGB1 (rh) */
+} Ifx_INT_OOBS_Bits;
+
+/** \brief OTGM SSI Control */
+typedef struct _Ifx_INT_OSSIC_Bits
+{
+ unsigned int TGS:2; /**< \brief [1:0] Trigger Set for OTGB0/1 (rw) */
+ unsigned int TGB:1; /**< \brief [2:2] OTGB0/1 Bus Select (rw) */
+ unsigned int reserved_3:29; /**< \brief \internal Reserved */
+} Ifx_INT_OSSIC_Bits;
+
+/** \brief Service Request Broadcast Register 0 */
+typedef struct _Ifx_INT_SRB0_Bits
+{
+ unsigned int TRIG0:1; /**< \brief [0:0] General Purpose Service Request Trigger 0 (w) */
+ unsigned int TRIG1:1; /**< \brief [1:1] General Purpose Service Request Trigger 1 (w) */
+ unsigned int TRIG2:1; /**< \brief [2:2] General Purpose Service Request Trigger 2 (w) */
+ unsigned int TRIG3:1; /**< \brief [3:3] General Purpose Service Request Trigger 3 (w) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_INT_SRB0_Bits;
+
+/** \brief Service Request Broadcast Register 1 */
+typedef struct _Ifx_INT_SRB1_Bits
+{
+ unsigned int TRIG0:1; /**< \brief [0:0] General Purpose Service Request Trigger 0 (w) */
+ unsigned int TRIG1:1; /**< \brief [1:1] General Purpose Service Request Trigger 1 (w) */
+ unsigned int TRIG2:1; /**< \brief [2:2] General Purpose Service Request Trigger 2 (w) */
+ unsigned int TRIG3:1; /**< \brief [3:3] General Purpose Service Request Trigger 3 (w) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_INT_SRB1_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Int_union
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_INT_ACCEN00_Bits B; /**< \brief Bitfield access */
+} Ifx_INT_ACCEN00;
+
+/** \brief Kernel 0 Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_INT_ACCEN01_Bits B; /**< \brief Bitfield access */
+} Ifx_INT_ACCEN01;
+
+/** \brief Kernel 1 Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_INT_ACCEN10_Bits B; /**< \brief Bitfield access */
+} Ifx_INT_ACCEN10;
+
+/** \brief Kernel 1 Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_INT_ACCEN11_Bits B; /**< \brief Bitfield access */
+} Ifx_INT_ACCEN11;
+
+/** \brief Error Capture Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_INT_ICU_ECR_Bits B; /**< \brief Bitfield access */
+} Ifx_INT_ICU_ECR;
+
+/** \brief Last Acknowledged Service Request Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_INT_ICU_LASR_Bits B; /**< \brief Bitfield access */
+} Ifx_INT_ICU_LASR;
+
+/** \brief Latest Winning Service Request Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_INT_ICU_LWSR_Bits B; /**< \brief Bitfield access */
+} Ifx_INT_ICU_LWSR;
+
+/** \brief Module Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_INT_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_INT_ID;
+
+/** \brief OTGM IRQ Trace */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_INT_OIT_Bits B; /**< \brief Bitfield access */
+} Ifx_INT_OIT;
+
+/** \brief OTGM IRQ MUX Missed IRQ Select */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_INT_OIXMS_Bits B; /**< \brief Bitfield access */
+} Ifx_INT_OIXMS;
+
+/** \brief OTGM IRQ MUX Select 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_INT_OIXS0_Bits B; /**< \brief Bitfield access */
+} Ifx_INT_OIXS0;
+
+/** \brief OTGM IRQ MUX Select 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_INT_OIXS1_Bits B; /**< \brief Bitfield access */
+} Ifx_INT_OIXS1;
+
+/** \brief OTGM IRQ MUX Trigger Set Select */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_INT_OIXTS_Bits B; /**< \brief Bitfield access */
+} Ifx_INT_OIXTS;
+
+/** \brief OTGM MCDS I/F Sensitivity Negedge */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_INT_OMISN_Bits B; /**< \brief Bitfield access */
+} Ifx_INT_OMISN;
+
+/** \brief OTGM MCDS I/F Sensitivity Posedge */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_INT_OMISP_Bits B; /**< \brief Bitfield access */
+} Ifx_INT_OMISP;
+
+/** \brief OTGM OTGB0/1 Status */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_INT_OOBS_Bits B; /**< \brief Bitfield access */
+} Ifx_INT_OOBS;
+
+/** \brief OTGM SSI Control */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_INT_OSSIC_Bits B; /**< \brief Bitfield access */
+} Ifx_INT_OSSIC;
+
+/** \brief Service Request Broadcast Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_INT_SRB0_Bits B; /**< \brief Bitfield access */
+} Ifx_INT_SRB0;
+
+/** \brief Service Request Broadcast Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_INT_SRB1_Bits B; /**< \brief Bitfield access */
+} Ifx_INT_SRB1;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Int_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L1
+ * \{ */
+
+/** \brief Interrupt router channel */
+typedef volatile struct _Ifx_INT_ICU
+{
+ Ifx_INT_ICU_LWSR LWSR; /**< \brief 0, Latest Winning Service Request Register */
+ Ifx_INT_ICU_LASR LASR; /**< \brief 4, Last Acknowledged Service Request Register */
+ Ifx_INT_ICU_ECR ECR; /**< \brief 8, Error Capture Register */
+ unsigned char reserved_C[4]; /**< \brief C, \internal Reserved */
+} Ifx_INT_ICU;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Int_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief Interrupt router object */
+typedef volatile struct _Ifx_INT
+{
+ unsigned char reserved_0[8]; /**< \brief 0, \internal Reserved */
+ Ifx_INT_ID ID; /**< \brief 8, Module Identification Register */
+ unsigned char reserved_C[4]; /**< \brief C, \internal Reserved */
+ Ifx_INT_SRB0 SRB0; /**< \brief 10, Service Request Broadcast Register 0 */
+ Ifx_INT_SRB1 SRB1; /**< \brief 14, Service Request Broadcast Register 1 */
+ unsigned char reserved_18[104]; /**< \brief 18, \internal Reserved */
+ Ifx_INT_OOBS OOBS; /**< \brief 80, OTGM OTGB0/1 Status */
+ Ifx_INT_OSSIC OSSIC; /**< \brief 84, OTGM SSI Control */
+ Ifx_INT_OIXTS OIXTS; /**< \brief 88, OTGM IRQ MUX Trigger Set Select */
+ Ifx_INT_OIXMS OIXMS; /**< \brief 8C, OTGM IRQ MUX Missed IRQ Select */
+ Ifx_INT_OIXS0 OIXS0; /**< \brief 90, OTGM IRQ MUX Select 0 */
+ Ifx_INT_OIXS1 OIXS1; /**< \brief 94, OTGM IRQ MUX Select 1 */
+ unsigned char reserved_98[8]; /**< \brief 98, \internal Reserved */
+ Ifx_INT_OIT OIT; /**< \brief A0, OTGM IRQ Trace */
+ Ifx_INT_OMISP OMISP; /**< \brief A4, OTGM MCDS I/F Sensitivity Posedge */
+ Ifx_INT_OMISN OMISN; /**< \brief A8, OTGM MCDS I/F Sensitivity Negedge */
+ unsigned char reserved_AC[68]; /**< \brief AC, \internal Reserved */
+ Ifx_INT_ACCEN01 ACCEN01; /**< \brief F0, Kernel 0 Access Enable Register 1 */
+ Ifx_INT_ACCEN00 ACCEN00; /**< \brief F4, Access Enable Register 0 */
+ Ifx_INT_ACCEN11 ACCEN11; /**< \brief F8, Kernel 1 Access Enable Register 1 */
+ Ifx_INT_ACCEN10 ACCEN10; /**< \brief FC, Kernel 1 Access Enable Register 0 */
+ Ifx_INT_ICU CH[4]; /**< \brief 100, Interrupt router channel */
+ unsigned char reserved_140[3776]; /**< \brief 140, \internal Reserved */
+} Ifx_INT;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXINT_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxIom_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxIom_bf.h
new file mode 100644
index 0000000..d3d2c98
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxIom_bf.h
@@ -0,0 +1,1764 @@
+/**
+ * \file IfxIom_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Iom_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Iom
+ *
+ */
+#ifndef IFXIOM_BF_H
+#define IFXIOM_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Iom_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN0 */
+#define IFX_IOM_ACCEN0_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN0 */
+#define IFX_IOM_ACCEN0_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN0 */
+#define IFX_IOM_ACCEN0_EN0_OFF (0u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN10 */
+#define IFX_IOM_ACCEN0_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN10 */
+#define IFX_IOM_ACCEN0_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN10 */
+#define IFX_IOM_ACCEN0_EN10_OFF (10u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN11 */
+#define IFX_IOM_ACCEN0_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN11 */
+#define IFX_IOM_ACCEN0_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN11 */
+#define IFX_IOM_ACCEN0_EN11_OFF (11u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN12 */
+#define IFX_IOM_ACCEN0_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN12 */
+#define IFX_IOM_ACCEN0_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN12 */
+#define IFX_IOM_ACCEN0_EN12_OFF (12u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN13 */
+#define IFX_IOM_ACCEN0_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN13 */
+#define IFX_IOM_ACCEN0_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN13 */
+#define IFX_IOM_ACCEN0_EN13_OFF (13u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN14 */
+#define IFX_IOM_ACCEN0_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN14 */
+#define IFX_IOM_ACCEN0_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN14 */
+#define IFX_IOM_ACCEN0_EN14_OFF (14u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN15 */
+#define IFX_IOM_ACCEN0_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN15 */
+#define IFX_IOM_ACCEN0_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN15 */
+#define IFX_IOM_ACCEN0_EN15_OFF (15u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN16 */
+#define IFX_IOM_ACCEN0_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN16 */
+#define IFX_IOM_ACCEN0_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN16 */
+#define IFX_IOM_ACCEN0_EN16_OFF (16u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN17 */
+#define IFX_IOM_ACCEN0_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN17 */
+#define IFX_IOM_ACCEN0_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN17 */
+#define IFX_IOM_ACCEN0_EN17_OFF (17u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN18 */
+#define IFX_IOM_ACCEN0_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN18 */
+#define IFX_IOM_ACCEN0_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN18 */
+#define IFX_IOM_ACCEN0_EN18_OFF (18u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN19 */
+#define IFX_IOM_ACCEN0_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN19 */
+#define IFX_IOM_ACCEN0_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN19 */
+#define IFX_IOM_ACCEN0_EN19_OFF (19u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN1 */
+#define IFX_IOM_ACCEN0_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN1 */
+#define IFX_IOM_ACCEN0_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN1 */
+#define IFX_IOM_ACCEN0_EN1_OFF (1u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN20 */
+#define IFX_IOM_ACCEN0_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN20 */
+#define IFX_IOM_ACCEN0_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN20 */
+#define IFX_IOM_ACCEN0_EN20_OFF (20u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN21 */
+#define IFX_IOM_ACCEN0_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN21 */
+#define IFX_IOM_ACCEN0_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN21 */
+#define IFX_IOM_ACCEN0_EN21_OFF (21u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN22 */
+#define IFX_IOM_ACCEN0_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN22 */
+#define IFX_IOM_ACCEN0_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN22 */
+#define IFX_IOM_ACCEN0_EN22_OFF (22u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN23 */
+#define IFX_IOM_ACCEN0_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN23 */
+#define IFX_IOM_ACCEN0_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN23 */
+#define IFX_IOM_ACCEN0_EN23_OFF (23u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN24 */
+#define IFX_IOM_ACCEN0_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN24 */
+#define IFX_IOM_ACCEN0_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN24 */
+#define IFX_IOM_ACCEN0_EN24_OFF (24u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN25 */
+#define IFX_IOM_ACCEN0_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN25 */
+#define IFX_IOM_ACCEN0_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN25 */
+#define IFX_IOM_ACCEN0_EN25_OFF (25u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN26 */
+#define IFX_IOM_ACCEN0_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN26 */
+#define IFX_IOM_ACCEN0_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN26 */
+#define IFX_IOM_ACCEN0_EN26_OFF (26u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN27 */
+#define IFX_IOM_ACCEN0_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN27 */
+#define IFX_IOM_ACCEN0_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN27 */
+#define IFX_IOM_ACCEN0_EN27_OFF (27u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN28 */
+#define IFX_IOM_ACCEN0_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN28 */
+#define IFX_IOM_ACCEN0_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN28 */
+#define IFX_IOM_ACCEN0_EN28_OFF (28u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN29 */
+#define IFX_IOM_ACCEN0_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN29 */
+#define IFX_IOM_ACCEN0_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN29 */
+#define IFX_IOM_ACCEN0_EN29_OFF (29u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN2 */
+#define IFX_IOM_ACCEN0_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN2 */
+#define IFX_IOM_ACCEN0_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN2 */
+#define IFX_IOM_ACCEN0_EN2_OFF (2u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN30 */
+#define IFX_IOM_ACCEN0_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN30 */
+#define IFX_IOM_ACCEN0_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN30 */
+#define IFX_IOM_ACCEN0_EN30_OFF (30u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN31 */
+#define IFX_IOM_ACCEN0_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN31 */
+#define IFX_IOM_ACCEN0_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN31 */
+#define IFX_IOM_ACCEN0_EN31_OFF (31u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN3 */
+#define IFX_IOM_ACCEN0_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN3 */
+#define IFX_IOM_ACCEN0_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN3 */
+#define IFX_IOM_ACCEN0_EN3_OFF (3u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN4 */
+#define IFX_IOM_ACCEN0_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN4 */
+#define IFX_IOM_ACCEN0_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN4 */
+#define IFX_IOM_ACCEN0_EN4_OFF (4u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN5 */
+#define IFX_IOM_ACCEN0_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN5 */
+#define IFX_IOM_ACCEN0_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN5 */
+#define IFX_IOM_ACCEN0_EN5_OFF (5u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN6 */
+#define IFX_IOM_ACCEN0_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN6 */
+#define IFX_IOM_ACCEN0_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN6 */
+#define IFX_IOM_ACCEN0_EN6_OFF (6u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN7 */
+#define IFX_IOM_ACCEN0_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN7 */
+#define IFX_IOM_ACCEN0_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN7 */
+#define IFX_IOM_ACCEN0_EN7_OFF (7u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN8 */
+#define IFX_IOM_ACCEN0_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN8 */
+#define IFX_IOM_ACCEN0_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN8 */
+#define IFX_IOM_ACCEN0_EN8_OFF (8u)
+
+/** \brief Length for Ifx_IOM_ACCEN0_Bits.EN9 */
+#define IFX_IOM_ACCEN0_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ACCEN0_Bits.EN9 */
+#define IFX_IOM_ACCEN0_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ACCEN0_Bits.EN9 */
+#define IFX_IOM_ACCEN0_EN9_OFF (9u)
+
+/** \brief Length for Ifx_IOM_CLC_Bits.DISR */
+#define IFX_IOM_CLC_DISR_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_CLC_Bits.DISR */
+#define IFX_IOM_CLC_DISR_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_CLC_Bits.DISR */
+#define IFX_IOM_CLC_DISR_OFF (0u)
+
+/** \brief Length for Ifx_IOM_CLC_Bits.DISS */
+#define IFX_IOM_CLC_DISS_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_CLC_Bits.DISS */
+#define IFX_IOM_CLC_DISS_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_CLC_Bits.DISS */
+#define IFX_IOM_CLC_DISS_OFF (1u)
+
+/** \brief Length for Ifx_IOM_CLC_Bits.EDIS */
+#define IFX_IOM_CLC_EDIS_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_CLC_Bits.EDIS */
+#define IFX_IOM_CLC_EDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_CLC_Bits.EDIS */
+#define IFX_IOM_CLC_EDIS_OFF (3u)
+
+/** \brief Length for Ifx_IOM_CLC_Bits.RMC */
+#define IFX_IOM_CLC_RMC_LEN (8u)
+
+/** \brief Mask for Ifx_IOM_CLC_Bits.RMC */
+#define IFX_IOM_CLC_RMC_MSK (0xffu)
+
+/** \brief Offset for Ifx_IOM_CLC_Bits.RMC */
+#define IFX_IOM_CLC_RMC_OFF (8u)
+
+/** \brief Length for Ifx_IOM_ECMCCFG_Bits.SELC0 */
+#define IFX_IOM_ECMCCFG_SELC0_LEN (4u)
+
+/** \brief Mask for Ifx_IOM_ECMCCFG_Bits.SELC0 */
+#define IFX_IOM_ECMCCFG_SELC0_MSK (0xfu)
+
+/** \brief Offset for Ifx_IOM_ECMCCFG_Bits.SELC0 */
+#define IFX_IOM_ECMCCFG_SELC0_OFF (0u)
+
+/** \brief Length for Ifx_IOM_ECMCCFG_Bits.SELC1 */
+#define IFX_IOM_ECMCCFG_SELC1_LEN (4u)
+
+/** \brief Mask for Ifx_IOM_ECMCCFG_Bits.SELC1 */
+#define IFX_IOM_ECMCCFG_SELC1_MSK (0xfu)
+
+/** \brief Offset for Ifx_IOM_ECMCCFG_Bits.SELC1 */
+#define IFX_IOM_ECMCCFG_SELC1_OFF (8u)
+
+/** \brief Length for Ifx_IOM_ECMCCFG_Bits.SELC2 */
+#define IFX_IOM_ECMCCFG_SELC2_LEN (4u)
+
+/** \brief Mask for Ifx_IOM_ECMCCFG_Bits.SELC2 */
+#define IFX_IOM_ECMCCFG_SELC2_MSK (0xfu)
+
+/** \brief Offset for Ifx_IOM_ECMCCFG_Bits.SELC2 */
+#define IFX_IOM_ECMCCFG_SELC2_OFF (16u)
+
+/** \brief Length for Ifx_IOM_ECMCCFG_Bits.SELC3 */
+#define IFX_IOM_ECMCCFG_SELC3_LEN (4u)
+
+/** \brief Mask for Ifx_IOM_ECMCCFG_Bits.SELC3 */
+#define IFX_IOM_ECMCCFG_SELC3_MSK (0xfu)
+
+/** \brief Offset for Ifx_IOM_ECMCCFG_Bits.SELC3 */
+#define IFX_IOM_ECMCCFG_SELC3_OFF (24u)
+
+/** \brief Length for Ifx_IOM_ECMCCFG_Bits.THCR1 */
+#define IFX_IOM_ECMCCFG_THCR1_LEN (4u)
+
+/** \brief Mask for Ifx_IOM_ECMCCFG_Bits.THCR1 */
+#define IFX_IOM_ECMCCFG_THCR1_MSK (0xfu)
+
+/** \brief Offset for Ifx_IOM_ECMCCFG_Bits.THCR1 */
+#define IFX_IOM_ECMCCFG_THCR1_OFF (12u)
+
+/** \brief Length for Ifx_IOM_ECMCCFG_Bits.THCR2 */
+#define IFX_IOM_ECMCCFG_THCR2_LEN (4u)
+
+/** \brief Mask for Ifx_IOM_ECMCCFG_Bits.THCR2 */
+#define IFX_IOM_ECMCCFG_THCR2_MSK (0xfu)
+
+/** \brief Offset for Ifx_IOM_ECMCCFG_Bits.THCR2 */
+#define IFX_IOM_ECMCCFG_THCR2_OFF (20u)
+
+/** \brief Length for Ifx_IOM_ECMCCFG_Bits.THCR3 */
+#define IFX_IOM_ECMCCFG_THCR3_LEN (4u)
+
+/** \brief Mask for Ifx_IOM_ECMCCFG_Bits.THCR3 */
+#define IFX_IOM_ECMCCFG_THCR3_MSK (0xfu)
+
+/** \brief Offset for Ifx_IOM_ECMCCFG_Bits.THCR3 */
+#define IFX_IOM_ECMCCFG_THCR3_OFF (28u)
+
+/** \brief Length for Ifx_IOM_ECMCCFG_Bits.THRC0 */
+#define IFX_IOM_ECMCCFG_THRC0_LEN (4u)
+
+/** \brief Mask for Ifx_IOM_ECMCCFG_Bits.THRC0 */
+#define IFX_IOM_ECMCCFG_THRC0_MSK (0xfu)
+
+/** \brief Offset for Ifx_IOM_ECMCCFG_Bits.THRC0 */
+#define IFX_IOM_ECMCCFG_THRC0_OFF (4u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETA0 */
+#define IFX_IOM_ECMETH0_ETA0_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETA0 */
+#define IFX_IOM_ECMETH0_ETA0_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETA0 */
+#define IFX_IOM_ECMETH0_ETA0_OFF (0u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETA10 */
+#define IFX_IOM_ECMETH0_ETA10_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETA10 */
+#define IFX_IOM_ECMETH0_ETA10_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETA10 */
+#define IFX_IOM_ECMETH0_ETA10_OFF (10u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETA11 */
+#define IFX_IOM_ECMETH0_ETA11_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETA11 */
+#define IFX_IOM_ECMETH0_ETA11_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETA11 */
+#define IFX_IOM_ECMETH0_ETA11_OFF (11u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETA12 */
+#define IFX_IOM_ECMETH0_ETA12_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETA12 */
+#define IFX_IOM_ECMETH0_ETA12_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETA12 */
+#define IFX_IOM_ECMETH0_ETA12_OFF (12u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETA13 */
+#define IFX_IOM_ECMETH0_ETA13_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETA13 */
+#define IFX_IOM_ECMETH0_ETA13_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETA13 */
+#define IFX_IOM_ECMETH0_ETA13_OFF (13u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETA14 */
+#define IFX_IOM_ECMETH0_ETA14_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETA14 */
+#define IFX_IOM_ECMETH0_ETA14_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETA14 */
+#define IFX_IOM_ECMETH0_ETA14_OFF (14u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETA15 */
+#define IFX_IOM_ECMETH0_ETA15_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETA15 */
+#define IFX_IOM_ECMETH0_ETA15_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETA15 */
+#define IFX_IOM_ECMETH0_ETA15_OFF (15u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETA1 */
+#define IFX_IOM_ECMETH0_ETA1_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETA1 */
+#define IFX_IOM_ECMETH0_ETA1_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETA1 */
+#define IFX_IOM_ECMETH0_ETA1_OFF (1u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETA2 */
+#define IFX_IOM_ECMETH0_ETA2_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETA2 */
+#define IFX_IOM_ECMETH0_ETA2_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETA2 */
+#define IFX_IOM_ECMETH0_ETA2_OFF (2u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETA3 */
+#define IFX_IOM_ECMETH0_ETA3_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETA3 */
+#define IFX_IOM_ECMETH0_ETA3_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETA3 */
+#define IFX_IOM_ECMETH0_ETA3_OFF (3u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETA4 */
+#define IFX_IOM_ECMETH0_ETA4_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETA4 */
+#define IFX_IOM_ECMETH0_ETA4_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETA4 */
+#define IFX_IOM_ECMETH0_ETA4_OFF (4u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETA5 */
+#define IFX_IOM_ECMETH0_ETA5_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETA5 */
+#define IFX_IOM_ECMETH0_ETA5_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETA5 */
+#define IFX_IOM_ECMETH0_ETA5_OFF (5u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETA6 */
+#define IFX_IOM_ECMETH0_ETA6_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETA6 */
+#define IFX_IOM_ECMETH0_ETA6_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETA6 */
+#define IFX_IOM_ECMETH0_ETA6_OFF (6u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETA7 */
+#define IFX_IOM_ECMETH0_ETA7_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETA7 */
+#define IFX_IOM_ECMETH0_ETA7_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETA7 */
+#define IFX_IOM_ECMETH0_ETA7_OFF (7u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETA8 */
+#define IFX_IOM_ECMETH0_ETA8_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETA8 */
+#define IFX_IOM_ECMETH0_ETA8_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETA8 */
+#define IFX_IOM_ECMETH0_ETA8_OFF (8u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETA9 */
+#define IFX_IOM_ECMETH0_ETA9_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETA9 */
+#define IFX_IOM_ECMETH0_ETA9_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETA9 */
+#define IFX_IOM_ECMETH0_ETA9_OFF (9u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETB0 */
+#define IFX_IOM_ECMETH0_ETB0_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETB0 */
+#define IFX_IOM_ECMETH0_ETB0_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETB0 */
+#define IFX_IOM_ECMETH0_ETB0_OFF (16u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETB10 */
+#define IFX_IOM_ECMETH0_ETB10_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETB10 */
+#define IFX_IOM_ECMETH0_ETB10_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETB10 */
+#define IFX_IOM_ECMETH0_ETB10_OFF (26u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETB11 */
+#define IFX_IOM_ECMETH0_ETB11_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETB11 */
+#define IFX_IOM_ECMETH0_ETB11_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETB11 */
+#define IFX_IOM_ECMETH0_ETB11_OFF (27u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETB12 */
+#define IFX_IOM_ECMETH0_ETB12_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETB12 */
+#define IFX_IOM_ECMETH0_ETB12_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETB12 */
+#define IFX_IOM_ECMETH0_ETB12_OFF (28u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETB13 */
+#define IFX_IOM_ECMETH0_ETB13_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETB13 */
+#define IFX_IOM_ECMETH0_ETB13_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETB13 */
+#define IFX_IOM_ECMETH0_ETB13_OFF (29u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETB14 */
+#define IFX_IOM_ECMETH0_ETB14_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETB14 */
+#define IFX_IOM_ECMETH0_ETB14_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETB14 */
+#define IFX_IOM_ECMETH0_ETB14_OFF (30u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETB15 */
+#define IFX_IOM_ECMETH0_ETB15_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETB15 */
+#define IFX_IOM_ECMETH0_ETB15_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETB15 */
+#define IFX_IOM_ECMETH0_ETB15_OFF (31u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETB1 */
+#define IFX_IOM_ECMETH0_ETB1_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETB1 */
+#define IFX_IOM_ECMETH0_ETB1_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETB1 */
+#define IFX_IOM_ECMETH0_ETB1_OFF (17u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETB2 */
+#define IFX_IOM_ECMETH0_ETB2_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETB2 */
+#define IFX_IOM_ECMETH0_ETB2_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETB2 */
+#define IFX_IOM_ECMETH0_ETB2_OFF (18u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETB3 */
+#define IFX_IOM_ECMETH0_ETB3_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETB3 */
+#define IFX_IOM_ECMETH0_ETB3_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETB3 */
+#define IFX_IOM_ECMETH0_ETB3_OFF (19u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETB4 */
+#define IFX_IOM_ECMETH0_ETB4_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETB4 */
+#define IFX_IOM_ECMETH0_ETB4_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETB4 */
+#define IFX_IOM_ECMETH0_ETB4_OFF (20u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETB5 */
+#define IFX_IOM_ECMETH0_ETB5_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETB5 */
+#define IFX_IOM_ECMETH0_ETB5_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETB5 */
+#define IFX_IOM_ECMETH0_ETB5_OFF (21u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETB6 */
+#define IFX_IOM_ECMETH0_ETB6_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETB6 */
+#define IFX_IOM_ECMETH0_ETB6_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETB6 */
+#define IFX_IOM_ECMETH0_ETB6_OFF (22u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETB7 */
+#define IFX_IOM_ECMETH0_ETB7_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETB7 */
+#define IFX_IOM_ECMETH0_ETB7_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETB7 */
+#define IFX_IOM_ECMETH0_ETB7_OFF (23u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETB8 */
+#define IFX_IOM_ECMETH0_ETB8_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETB8 */
+#define IFX_IOM_ECMETH0_ETB8_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETB8 */
+#define IFX_IOM_ECMETH0_ETB8_OFF (24u)
+
+/** \brief Length for Ifx_IOM_ECMETH0_Bits.ETB9 */
+#define IFX_IOM_ECMETH0_ETB9_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH0_Bits.ETB9 */
+#define IFX_IOM_ECMETH0_ETB9_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH0_Bits.ETB9 */
+#define IFX_IOM_ECMETH0_ETB9_OFF (25u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETC0 */
+#define IFX_IOM_ECMETH1_ETC0_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETC0 */
+#define IFX_IOM_ECMETH1_ETC0_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETC0 */
+#define IFX_IOM_ECMETH1_ETC0_OFF (0u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETC10 */
+#define IFX_IOM_ECMETH1_ETC10_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETC10 */
+#define IFX_IOM_ECMETH1_ETC10_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETC10 */
+#define IFX_IOM_ECMETH1_ETC10_OFF (10u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETC11 */
+#define IFX_IOM_ECMETH1_ETC11_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETC11 */
+#define IFX_IOM_ECMETH1_ETC11_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETC11 */
+#define IFX_IOM_ECMETH1_ETC11_OFF (11u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETC12 */
+#define IFX_IOM_ECMETH1_ETC12_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETC12 */
+#define IFX_IOM_ECMETH1_ETC12_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETC12 */
+#define IFX_IOM_ECMETH1_ETC12_OFF (12u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETC13 */
+#define IFX_IOM_ECMETH1_ETC13_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETC13 */
+#define IFX_IOM_ECMETH1_ETC13_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETC13 */
+#define IFX_IOM_ECMETH1_ETC13_OFF (13u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETC14 */
+#define IFX_IOM_ECMETH1_ETC14_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETC14 */
+#define IFX_IOM_ECMETH1_ETC14_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETC14 */
+#define IFX_IOM_ECMETH1_ETC14_OFF (14u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETC15 */
+#define IFX_IOM_ECMETH1_ETC15_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETC15 */
+#define IFX_IOM_ECMETH1_ETC15_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETC15 */
+#define IFX_IOM_ECMETH1_ETC15_OFF (15u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETC1 */
+#define IFX_IOM_ECMETH1_ETC1_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETC1 */
+#define IFX_IOM_ECMETH1_ETC1_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETC1 */
+#define IFX_IOM_ECMETH1_ETC1_OFF (1u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETC2 */
+#define IFX_IOM_ECMETH1_ETC2_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETC2 */
+#define IFX_IOM_ECMETH1_ETC2_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETC2 */
+#define IFX_IOM_ECMETH1_ETC2_OFF (2u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETC3 */
+#define IFX_IOM_ECMETH1_ETC3_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETC3 */
+#define IFX_IOM_ECMETH1_ETC3_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETC3 */
+#define IFX_IOM_ECMETH1_ETC3_OFF (3u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETC4 */
+#define IFX_IOM_ECMETH1_ETC4_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETC4 */
+#define IFX_IOM_ECMETH1_ETC4_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETC4 */
+#define IFX_IOM_ECMETH1_ETC4_OFF (4u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETC5 */
+#define IFX_IOM_ECMETH1_ETC5_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETC5 */
+#define IFX_IOM_ECMETH1_ETC5_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETC5 */
+#define IFX_IOM_ECMETH1_ETC5_OFF (5u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETC6 */
+#define IFX_IOM_ECMETH1_ETC6_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETC6 */
+#define IFX_IOM_ECMETH1_ETC6_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETC6 */
+#define IFX_IOM_ECMETH1_ETC6_OFF (6u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETC7 */
+#define IFX_IOM_ECMETH1_ETC7_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETC7 */
+#define IFX_IOM_ECMETH1_ETC7_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETC7 */
+#define IFX_IOM_ECMETH1_ETC7_OFF (7u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETC8 */
+#define IFX_IOM_ECMETH1_ETC8_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETC8 */
+#define IFX_IOM_ECMETH1_ETC8_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETC8 */
+#define IFX_IOM_ECMETH1_ETC8_OFF (8u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETC9 */
+#define IFX_IOM_ECMETH1_ETC9_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETC9 */
+#define IFX_IOM_ECMETH1_ETC9_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETC9 */
+#define IFX_IOM_ECMETH1_ETC9_OFF (9u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETD0 */
+#define IFX_IOM_ECMETH1_ETD0_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETD0 */
+#define IFX_IOM_ECMETH1_ETD0_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETD0 */
+#define IFX_IOM_ECMETH1_ETD0_OFF (16u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETD10 */
+#define IFX_IOM_ECMETH1_ETD10_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETD10 */
+#define IFX_IOM_ECMETH1_ETD10_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETD10 */
+#define IFX_IOM_ECMETH1_ETD10_OFF (26u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETD11 */
+#define IFX_IOM_ECMETH1_ETD11_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETD11 */
+#define IFX_IOM_ECMETH1_ETD11_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETD11 */
+#define IFX_IOM_ECMETH1_ETD11_OFF (27u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETD12 */
+#define IFX_IOM_ECMETH1_ETD12_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETD12 */
+#define IFX_IOM_ECMETH1_ETD12_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETD12 */
+#define IFX_IOM_ECMETH1_ETD12_OFF (28u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETD13 */
+#define IFX_IOM_ECMETH1_ETD13_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETD13 */
+#define IFX_IOM_ECMETH1_ETD13_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETD13 */
+#define IFX_IOM_ECMETH1_ETD13_OFF (29u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETD14 */
+#define IFX_IOM_ECMETH1_ETD14_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETD14 */
+#define IFX_IOM_ECMETH1_ETD14_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETD14 */
+#define IFX_IOM_ECMETH1_ETD14_OFF (30u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETD15 */
+#define IFX_IOM_ECMETH1_ETD15_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETD15 */
+#define IFX_IOM_ECMETH1_ETD15_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETD15 */
+#define IFX_IOM_ECMETH1_ETD15_OFF (31u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETD1 */
+#define IFX_IOM_ECMETH1_ETD1_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETD1 */
+#define IFX_IOM_ECMETH1_ETD1_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETD1 */
+#define IFX_IOM_ECMETH1_ETD1_OFF (17u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETD2 */
+#define IFX_IOM_ECMETH1_ETD2_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETD2 */
+#define IFX_IOM_ECMETH1_ETD2_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETD2 */
+#define IFX_IOM_ECMETH1_ETD2_OFF (18u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETD3 */
+#define IFX_IOM_ECMETH1_ETD3_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETD3 */
+#define IFX_IOM_ECMETH1_ETD3_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETD3 */
+#define IFX_IOM_ECMETH1_ETD3_OFF (19u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETD4 */
+#define IFX_IOM_ECMETH1_ETD4_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETD4 */
+#define IFX_IOM_ECMETH1_ETD4_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETD4 */
+#define IFX_IOM_ECMETH1_ETD4_OFF (20u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETD5 */
+#define IFX_IOM_ECMETH1_ETD5_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETD5 */
+#define IFX_IOM_ECMETH1_ETD5_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETD5 */
+#define IFX_IOM_ECMETH1_ETD5_OFF (21u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETD6 */
+#define IFX_IOM_ECMETH1_ETD6_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETD6 */
+#define IFX_IOM_ECMETH1_ETD6_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETD6 */
+#define IFX_IOM_ECMETH1_ETD6_OFF (22u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETD7 */
+#define IFX_IOM_ECMETH1_ETD7_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETD7 */
+#define IFX_IOM_ECMETH1_ETD7_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETD7 */
+#define IFX_IOM_ECMETH1_ETD7_OFF (23u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETD8 */
+#define IFX_IOM_ECMETH1_ETD8_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETD8 */
+#define IFX_IOM_ECMETH1_ETD8_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETD8 */
+#define IFX_IOM_ECMETH1_ETD8_OFF (24u)
+
+/** \brief Length for Ifx_IOM_ECMETH1_Bits.ETD9 */
+#define IFX_IOM_ECMETH1_ETD9_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMETH1_Bits.ETD9 */
+#define IFX_IOM_ECMETH1_ETD9_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMETH1_Bits.ETD9 */
+#define IFX_IOM_ECMETH1_ETD9_OFF (25u)
+
+/** \brief Length for Ifx_IOM_ECMSELR_Bits.CES0 */
+#define IFX_IOM_ECMSELR_CES0_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMSELR_Bits.CES0 */
+#define IFX_IOM_ECMSELR_CES0_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMSELR_Bits.CES0 */
+#define IFX_IOM_ECMSELR_CES0_OFF (0u)
+
+/** \brief Length for Ifx_IOM_ECMSELR_Bits.CES10 */
+#define IFX_IOM_ECMSELR_CES10_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMSELR_Bits.CES10 */
+#define IFX_IOM_ECMSELR_CES10_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMSELR_Bits.CES10 */
+#define IFX_IOM_ECMSELR_CES10_OFF (10u)
+
+/** \brief Length for Ifx_IOM_ECMSELR_Bits.CES11 */
+#define IFX_IOM_ECMSELR_CES11_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMSELR_Bits.CES11 */
+#define IFX_IOM_ECMSELR_CES11_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMSELR_Bits.CES11 */
+#define IFX_IOM_ECMSELR_CES11_OFF (11u)
+
+/** \brief Length for Ifx_IOM_ECMSELR_Bits.CES12 */
+#define IFX_IOM_ECMSELR_CES12_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMSELR_Bits.CES12 */
+#define IFX_IOM_ECMSELR_CES12_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMSELR_Bits.CES12 */
+#define IFX_IOM_ECMSELR_CES12_OFF (12u)
+
+/** \brief Length for Ifx_IOM_ECMSELR_Bits.CES13 */
+#define IFX_IOM_ECMSELR_CES13_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMSELR_Bits.CES13 */
+#define IFX_IOM_ECMSELR_CES13_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMSELR_Bits.CES13 */
+#define IFX_IOM_ECMSELR_CES13_OFF (13u)
+
+/** \brief Length for Ifx_IOM_ECMSELR_Bits.CES14 */
+#define IFX_IOM_ECMSELR_CES14_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMSELR_Bits.CES14 */
+#define IFX_IOM_ECMSELR_CES14_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMSELR_Bits.CES14 */
+#define IFX_IOM_ECMSELR_CES14_OFF (14u)
+
+/** \brief Length for Ifx_IOM_ECMSELR_Bits.CES15 */
+#define IFX_IOM_ECMSELR_CES15_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMSELR_Bits.CES15 */
+#define IFX_IOM_ECMSELR_CES15_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMSELR_Bits.CES15 */
+#define IFX_IOM_ECMSELR_CES15_OFF (15u)
+
+/** \brief Length for Ifx_IOM_ECMSELR_Bits.CES1 */
+#define IFX_IOM_ECMSELR_CES1_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMSELR_Bits.CES1 */
+#define IFX_IOM_ECMSELR_CES1_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMSELR_Bits.CES1 */
+#define IFX_IOM_ECMSELR_CES1_OFF (1u)
+
+/** \brief Length for Ifx_IOM_ECMSELR_Bits.CES2 */
+#define IFX_IOM_ECMSELR_CES2_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMSELR_Bits.CES2 */
+#define IFX_IOM_ECMSELR_CES2_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMSELR_Bits.CES2 */
+#define IFX_IOM_ECMSELR_CES2_OFF (2u)
+
+/** \brief Length for Ifx_IOM_ECMSELR_Bits.CES3 */
+#define IFX_IOM_ECMSELR_CES3_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMSELR_Bits.CES3 */
+#define IFX_IOM_ECMSELR_CES3_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMSELR_Bits.CES3 */
+#define IFX_IOM_ECMSELR_CES3_OFF (3u)
+
+/** \brief Length for Ifx_IOM_ECMSELR_Bits.CES4 */
+#define IFX_IOM_ECMSELR_CES4_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMSELR_Bits.CES4 */
+#define IFX_IOM_ECMSELR_CES4_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMSELR_Bits.CES4 */
+#define IFX_IOM_ECMSELR_CES4_OFF (4u)
+
+/** \brief Length for Ifx_IOM_ECMSELR_Bits.CES5 */
+#define IFX_IOM_ECMSELR_CES5_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMSELR_Bits.CES5 */
+#define IFX_IOM_ECMSELR_CES5_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMSELR_Bits.CES5 */
+#define IFX_IOM_ECMSELR_CES5_OFF (5u)
+
+/** \brief Length for Ifx_IOM_ECMSELR_Bits.CES6 */
+#define IFX_IOM_ECMSELR_CES6_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMSELR_Bits.CES6 */
+#define IFX_IOM_ECMSELR_CES6_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMSELR_Bits.CES6 */
+#define IFX_IOM_ECMSELR_CES6_OFF (6u)
+
+/** \brief Length for Ifx_IOM_ECMSELR_Bits.CES7 */
+#define IFX_IOM_ECMSELR_CES7_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMSELR_Bits.CES7 */
+#define IFX_IOM_ECMSELR_CES7_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMSELR_Bits.CES7 */
+#define IFX_IOM_ECMSELR_CES7_OFF (7u)
+
+/** \brief Length for Ifx_IOM_ECMSELR_Bits.CES8 */
+#define IFX_IOM_ECMSELR_CES8_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMSELR_Bits.CES8 */
+#define IFX_IOM_ECMSELR_CES8_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMSELR_Bits.CES8 */
+#define IFX_IOM_ECMSELR_CES8_OFF (8u)
+
+/** \brief Length for Ifx_IOM_ECMSELR_Bits.CES9 */
+#define IFX_IOM_ECMSELR_CES9_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMSELR_Bits.CES9 */
+#define IFX_IOM_ECMSELR_CES9_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMSELR_Bits.CES9 */
+#define IFX_IOM_ECMSELR_CES9_OFF (9u)
+
+/** \brief Length for Ifx_IOM_ECMSELR_Bits.CTS0 */
+#define IFX_IOM_ECMSELR_CTS0_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMSELR_Bits.CTS0 */
+#define IFX_IOM_ECMSELR_CTS0_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMSELR_Bits.CTS0 */
+#define IFX_IOM_ECMSELR_CTS0_OFF (16u)
+
+/** \brief Length for Ifx_IOM_ECMSELR_Bits.CTS1 */
+#define IFX_IOM_ECMSELR_CTS1_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMSELR_Bits.CTS1 */
+#define IFX_IOM_ECMSELR_CTS1_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMSELR_Bits.CTS1 */
+#define IFX_IOM_ECMSELR_CTS1_OFF (17u)
+
+/** \brief Length for Ifx_IOM_ECMSELR_Bits.CTS2 */
+#define IFX_IOM_ECMSELR_CTS2_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMSELR_Bits.CTS2 */
+#define IFX_IOM_ECMSELR_CTS2_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMSELR_Bits.CTS2 */
+#define IFX_IOM_ECMSELR_CTS2_OFF (18u)
+
+/** \brief Length for Ifx_IOM_ECMSELR_Bits.CTS3 */
+#define IFX_IOM_ECMSELR_CTS3_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_ECMSELR_Bits.CTS3 */
+#define IFX_IOM_ECMSELR_CTS3_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_ECMSELR_Bits.CTS3 */
+#define IFX_IOM_ECMSELR_CTS3_OFF (19u)
+
+/** \brief Length for Ifx_IOM_FPCCTR_Bits.CMP */
+#define IFX_IOM_FPCCTR_CMP_LEN (16u)
+
+/** \brief Mask for Ifx_IOM_FPCCTR_Bits.CMP */
+#define IFX_IOM_FPCCTR_CMP_MSK (0xffffu)
+
+/** \brief Offset for Ifx_IOM_FPCCTR_Bits.CMP */
+#define IFX_IOM_FPCCTR_CMP_OFF (0u)
+
+/** \brief Length for Ifx_IOM_FPCCTR_Bits.ISM */
+#define IFX_IOM_FPCCTR_ISM_LEN (2u)
+
+/** \brief Mask for Ifx_IOM_FPCCTR_Bits.ISM */
+#define IFX_IOM_FPCCTR_ISM_MSK (0x3u)
+
+/** \brief Offset for Ifx_IOM_FPCCTR_Bits.ISM */
+#define IFX_IOM_FPCCTR_ISM_OFF (19u)
+
+/** \brief Length for Ifx_IOM_FPCCTR_Bits.ISR */
+#define IFX_IOM_FPCCTR_ISR_LEN (3u)
+
+/** \brief Mask for Ifx_IOM_FPCCTR_Bits.ISR */
+#define IFX_IOM_FPCCTR_ISR_MSK (0x7u)
+
+/** \brief Offset for Ifx_IOM_FPCCTR_Bits.ISR */
+#define IFX_IOM_FPCCTR_ISR_OFF (24u)
+
+/** \brief Length for Ifx_IOM_FPCCTR_Bits.MOD */
+#define IFX_IOM_FPCCTR_MOD_LEN (3u)
+
+/** \brief Mask for Ifx_IOM_FPCCTR_Bits.MOD */
+#define IFX_IOM_FPCCTR_MOD_MSK (0x7u)
+
+/** \brief Offset for Ifx_IOM_FPCCTR_Bits.MOD */
+#define IFX_IOM_FPCCTR_MOD_OFF (16u)
+
+/** \brief Length for Ifx_IOM_FPCCTR_Bits.RTG */
+#define IFX_IOM_FPCCTR_RTG_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCCTR_Bits.RTG */
+#define IFX_IOM_FPCCTR_RTG_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCCTR_Bits.RTG */
+#define IFX_IOM_FPCCTR_RTG_OFF (22u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.FEG0 */
+#define IFX_IOM_FPCESR_FEG0_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.FEG0 */
+#define IFX_IOM_FPCESR_FEG0_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.FEG0 */
+#define IFX_IOM_FPCESR_FEG0_OFF (0u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.FEG10 */
+#define IFX_IOM_FPCESR_FEG10_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.FEG10 */
+#define IFX_IOM_FPCESR_FEG10_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.FEG10 */
+#define IFX_IOM_FPCESR_FEG10_OFF (10u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.FEG11 */
+#define IFX_IOM_FPCESR_FEG11_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.FEG11 */
+#define IFX_IOM_FPCESR_FEG11_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.FEG11 */
+#define IFX_IOM_FPCESR_FEG11_OFF (11u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.FEG12 */
+#define IFX_IOM_FPCESR_FEG12_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.FEG12 */
+#define IFX_IOM_FPCESR_FEG12_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.FEG12 */
+#define IFX_IOM_FPCESR_FEG12_OFF (12u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.FEG13 */
+#define IFX_IOM_FPCESR_FEG13_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.FEG13 */
+#define IFX_IOM_FPCESR_FEG13_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.FEG13 */
+#define IFX_IOM_FPCESR_FEG13_OFF (13u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.FEG14 */
+#define IFX_IOM_FPCESR_FEG14_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.FEG14 */
+#define IFX_IOM_FPCESR_FEG14_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.FEG14 */
+#define IFX_IOM_FPCESR_FEG14_OFF (14u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.FEG15 */
+#define IFX_IOM_FPCESR_FEG15_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.FEG15 */
+#define IFX_IOM_FPCESR_FEG15_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.FEG15 */
+#define IFX_IOM_FPCESR_FEG15_OFF (15u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.FEG1 */
+#define IFX_IOM_FPCESR_FEG1_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.FEG1 */
+#define IFX_IOM_FPCESR_FEG1_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.FEG1 */
+#define IFX_IOM_FPCESR_FEG1_OFF (1u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.FEG2 */
+#define IFX_IOM_FPCESR_FEG2_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.FEG2 */
+#define IFX_IOM_FPCESR_FEG2_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.FEG2 */
+#define IFX_IOM_FPCESR_FEG2_OFF (2u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.FEG3 */
+#define IFX_IOM_FPCESR_FEG3_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.FEG3 */
+#define IFX_IOM_FPCESR_FEG3_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.FEG3 */
+#define IFX_IOM_FPCESR_FEG3_OFF (3u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.FEG4 */
+#define IFX_IOM_FPCESR_FEG4_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.FEG4 */
+#define IFX_IOM_FPCESR_FEG4_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.FEG4 */
+#define IFX_IOM_FPCESR_FEG4_OFF (4u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.FEG5 */
+#define IFX_IOM_FPCESR_FEG5_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.FEG5 */
+#define IFX_IOM_FPCESR_FEG5_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.FEG5 */
+#define IFX_IOM_FPCESR_FEG5_OFF (5u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.FEG6 */
+#define IFX_IOM_FPCESR_FEG6_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.FEG6 */
+#define IFX_IOM_FPCESR_FEG6_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.FEG6 */
+#define IFX_IOM_FPCESR_FEG6_OFF (6u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.FEG7 */
+#define IFX_IOM_FPCESR_FEG7_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.FEG7 */
+#define IFX_IOM_FPCESR_FEG7_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.FEG7 */
+#define IFX_IOM_FPCESR_FEG7_OFF (7u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.FEG8 */
+#define IFX_IOM_FPCESR_FEG8_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.FEG8 */
+#define IFX_IOM_FPCESR_FEG8_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.FEG8 */
+#define IFX_IOM_FPCESR_FEG8_OFF (8u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.FEG9 */
+#define IFX_IOM_FPCESR_FEG9_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.FEG9 */
+#define IFX_IOM_FPCESR_FEG9_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.FEG9 */
+#define IFX_IOM_FPCESR_FEG9_OFF (9u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.REG0 */
+#define IFX_IOM_FPCESR_REG0_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.REG0 */
+#define IFX_IOM_FPCESR_REG0_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.REG0 */
+#define IFX_IOM_FPCESR_REG0_OFF (16u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.REG10 */
+#define IFX_IOM_FPCESR_REG10_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.REG10 */
+#define IFX_IOM_FPCESR_REG10_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.REG10 */
+#define IFX_IOM_FPCESR_REG10_OFF (26u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.REG11 */
+#define IFX_IOM_FPCESR_REG11_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.REG11 */
+#define IFX_IOM_FPCESR_REG11_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.REG11 */
+#define IFX_IOM_FPCESR_REG11_OFF (27u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.REG12 */
+#define IFX_IOM_FPCESR_REG12_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.REG12 */
+#define IFX_IOM_FPCESR_REG12_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.REG12 */
+#define IFX_IOM_FPCESR_REG12_OFF (28u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.REG13 */
+#define IFX_IOM_FPCESR_REG13_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.REG13 */
+#define IFX_IOM_FPCESR_REG13_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.REG13 */
+#define IFX_IOM_FPCESR_REG13_OFF (29u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.REG14 */
+#define IFX_IOM_FPCESR_REG14_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.REG14 */
+#define IFX_IOM_FPCESR_REG14_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.REG14 */
+#define IFX_IOM_FPCESR_REG14_OFF (30u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.REG15 */
+#define IFX_IOM_FPCESR_REG15_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.REG15 */
+#define IFX_IOM_FPCESR_REG15_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.REG15 */
+#define IFX_IOM_FPCESR_REG15_OFF (31u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.REG1 */
+#define IFX_IOM_FPCESR_REG1_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.REG1 */
+#define IFX_IOM_FPCESR_REG1_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.REG1 */
+#define IFX_IOM_FPCESR_REG1_OFF (17u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.REG2 */
+#define IFX_IOM_FPCESR_REG2_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.REG2 */
+#define IFX_IOM_FPCESR_REG2_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.REG2 */
+#define IFX_IOM_FPCESR_REG2_OFF (18u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.REG3 */
+#define IFX_IOM_FPCESR_REG3_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.REG3 */
+#define IFX_IOM_FPCESR_REG3_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.REG3 */
+#define IFX_IOM_FPCESR_REG3_OFF (19u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.REG4 */
+#define IFX_IOM_FPCESR_REG4_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.REG4 */
+#define IFX_IOM_FPCESR_REG4_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.REG4 */
+#define IFX_IOM_FPCESR_REG4_OFF (20u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.REG5 */
+#define IFX_IOM_FPCESR_REG5_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.REG5 */
+#define IFX_IOM_FPCESR_REG5_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.REG5 */
+#define IFX_IOM_FPCESR_REG5_OFF (21u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.REG6 */
+#define IFX_IOM_FPCESR_REG6_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.REG6 */
+#define IFX_IOM_FPCESR_REG6_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.REG6 */
+#define IFX_IOM_FPCESR_REG6_OFF (22u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.REG7 */
+#define IFX_IOM_FPCESR_REG7_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.REG7 */
+#define IFX_IOM_FPCESR_REG7_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.REG7 */
+#define IFX_IOM_FPCESR_REG7_OFF (23u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.REG8 */
+#define IFX_IOM_FPCESR_REG8_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.REG8 */
+#define IFX_IOM_FPCESR_REG8_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.REG8 */
+#define IFX_IOM_FPCESR_REG8_OFF (24u)
+
+/** \brief Length for Ifx_IOM_FPCESR_Bits.REG9 */
+#define IFX_IOM_FPCESR_REG9_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_FPCESR_Bits.REG9 */
+#define IFX_IOM_FPCESR_REG9_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_FPCESR_Bits.REG9 */
+#define IFX_IOM_FPCESR_REG9_OFF (25u)
+
+/** \brief Length for Ifx_IOM_FPCTIM_Bits.TIM */
+#define IFX_IOM_FPCTIM_TIM_LEN (16u)
+
+/** \brief Mask for Ifx_IOM_FPCTIM_Bits.TIM */
+#define IFX_IOM_FPCTIM_TIM_MSK (0xffffu)
+
+/** \brief Offset for Ifx_IOM_FPCTIM_Bits.TIM */
+#define IFX_IOM_FPCTIM_TIM_OFF (0u)
+
+/** \brief Length for Ifx_IOM_GTMEXR_Bits.EN0 */
+#define IFX_IOM_GTMEXR_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_GTMEXR_Bits.EN0 */
+#define IFX_IOM_GTMEXR_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_GTMEXR_Bits.EN0 */
+#define IFX_IOM_GTMEXR_EN0_OFF (0u)
+
+/** \brief Length for Ifx_IOM_GTMEXR_Bits.EN1 */
+#define IFX_IOM_GTMEXR_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_GTMEXR_Bits.EN1 */
+#define IFX_IOM_GTMEXR_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_GTMEXR_Bits.EN1 */
+#define IFX_IOM_GTMEXR_EN1_OFF (1u)
+
+/** \brief Length for Ifx_IOM_GTMEXR_Bits.EN2 */
+#define IFX_IOM_GTMEXR_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_GTMEXR_Bits.EN2 */
+#define IFX_IOM_GTMEXR_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_GTMEXR_Bits.EN2 */
+#define IFX_IOM_GTMEXR_EN2_OFF (2u)
+
+/** \brief Length for Ifx_IOM_GTMEXR_Bits.EN3 */
+#define IFX_IOM_GTMEXR_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_GTMEXR_Bits.EN3 */
+#define IFX_IOM_GTMEXR_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_GTMEXR_Bits.EN3 */
+#define IFX_IOM_GTMEXR_EN3_OFF (3u)
+
+/** \brief Length for Ifx_IOM_GTMEXR_Bits.EN4 */
+#define IFX_IOM_GTMEXR_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_GTMEXR_Bits.EN4 */
+#define IFX_IOM_GTMEXR_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_GTMEXR_Bits.EN4 */
+#define IFX_IOM_GTMEXR_EN4_OFF (4u)
+
+/** \brief Length for Ifx_IOM_GTMEXR_Bits.EN5 */
+#define IFX_IOM_GTMEXR_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_GTMEXR_Bits.EN5 */
+#define IFX_IOM_GTMEXR_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_GTMEXR_Bits.EN5 */
+#define IFX_IOM_GTMEXR_EN5_OFF (5u)
+
+/** \brief Length for Ifx_IOM_GTMEXR_Bits.EN6 */
+#define IFX_IOM_GTMEXR_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_GTMEXR_Bits.EN6 */
+#define IFX_IOM_GTMEXR_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_GTMEXR_Bits.EN6 */
+#define IFX_IOM_GTMEXR_EN6_OFF (6u)
+
+/** \brief Length for Ifx_IOM_GTMEXR_Bits.EN7 */
+#define IFX_IOM_GTMEXR_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_GTMEXR_Bits.EN7 */
+#define IFX_IOM_GTMEXR_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_GTMEXR_Bits.EN7 */
+#define IFX_IOM_GTMEXR_EN7_OFF (7u)
+
+/** \brief Length for Ifx_IOM_ID_Bits.MODNUMBER */
+#define IFX_IOM_ID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_IOM_ID_Bits.MODNUMBER */
+#define IFX_IOM_ID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_IOM_ID_Bits.MODNUMBER */
+#define IFX_IOM_ID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_IOM_ID_Bits.MODREV */
+#define IFX_IOM_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_IOM_ID_Bits.MODREV */
+#define IFX_IOM_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_IOM_ID_Bits.MODREV */
+#define IFX_IOM_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_IOM_ID_Bits.MODTYPE */
+#define IFX_IOM_ID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_IOM_ID_Bits.MODTYPE */
+#define IFX_IOM_ID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_IOM_ID_Bits.MODTYPE */
+#define IFX_IOM_ID_MODTYPE_OFF (8u)
+
+/** \brief Length for Ifx_IOM_KRST0_Bits.RST */
+#define IFX_IOM_KRST0_RST_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_KRST0_Bits.RST */
+#define IFX_IOM_KRST0_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_KRST0_Bits.RST */
+#define IFX_IOM_KRST0_RST_OFF (0u)
+
+/** \brief Length for Ifx_IOM_KRST0_Bits.RSTSTAT */
+#define IFX_IOM_KRST0_RSTSTAT_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_KRST0_Bits.RSTSTAT */
+#define IFX_IOM_KRST0_RSTSTAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_KRST0_Bits.RSTSTAT */
+#define IFX_IOM_KRST0_RSTSTAT_OFF (1u)
+
+/** \brief Length for Ifx_IOM_KRST1_Bits.RST */
+#define IFX_IOM_KRST1_RST_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_KRST1_Bits.RST */
+#define IFX_IOM_KRST1_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_KRST1_Bits.RST */
+#define IFX_IOM_KRST1_RST_OFF (0u)
+
+/** \brief Length for Ifx_IOM_KRSTCLR_Bits.CLR */
+#define IFX_IOM_KRSTCLR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_KRSTCLR_Bits.CLR */
+#define IFX_IOM_KRSTCLR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_KRSTCLR_Bits.CLR */
+#define IFX_IOM_KRSTCLR_CLR_OFF (0u)
+
+/** \brief Length for Ifx_IOM_LAMCFG_Bits.EDS */
+#define IFX_IOM_LAMCFG_EDS_LEN (4u)
+
+/** \brief Mask for Ifx_IOM_LAMCFG_Bits.EDS */
+#define IFX_IOM_LAMCFG_EDS_MSK (0xfu)
+
+/** \brief Offset for Ifx_IOM_LAMCFG_Bits.EDS */
+#define IFX_IOM_LAMCFG_EDS_OFF (8u)
+
+/** \brief Length for Ifx_IOM_LAMCFG_Bits.EWS */
+#define IFX_IOM_LAMCFG_EWS_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_LAMCFG_Bits.EWS */
+#define IFX_IOM_LAMCFG_EWS_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_LAMCFG_Bits.EWS */
+#define IFX_IOM_LAMCFG_EWS_OFF (4u)
+
+/** \brief Length for Ifx_IOM_LAMCFG_Bits.IVM */
+#define IFX_IOM_LAMCFG_IVM_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_LAMCFG_Bits.IVM */
+#define IFX_IOM_LAMCFG_IVM_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_LAMCFG_Bits.IVM */
+#define IFX_IOM_LAMCFG_IVM_OFF (1u)
+
+/** \brief Length for Ifx_IOM_LAMCFG_Bits.IVR */
+#define IFX_IOM_LAMCFG_IVR_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_LAMCFG_Bits.IVR */
+#define IFX_IOM_LAMCFG_IVR_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_LAMCFG_Bits.IVR */
+#define IFX_IOM_LAMCFG_IVR_OFF (0u)
+
+/** \brief Length for Ifx_IOM_LAMCFG_Bits.IVW */
+#define IFX_IOM_LAMCFG_IVW_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_LAMCFG_Bits.IVW */
+#define IFX_IOM_LAMCFG_IVW_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_LAMCFG_Bits.IVW */
+#define IFX_IOM_LAMCFG_IVW_OFF (12u)
+
+/** \brief Length for Ifx_IOM_LAMCFG_Bits.MCS */
+#define IFX_IOM_LAMCFG_MCS_LEN (4u)
+
+/** \brief Mask for Ifx_IOM_LAMCFG_Bits.MCS */
+#define IFX_IOM_LAMCFG_MCS_MSK (0xfu)
+
+/** \brief Offset for Ifx_IOM_LAMCFG_Bits.MCS */
+#define IFX_IOM_LAMCFG_MCS_OFF (16u)
+
+/** \brief Length for Ifx_IOM_LAMCFG_Bits.MOS */
+#define IFX_IOM_LAMCFG_MOS_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_LAMCFG_Bits.MOS */
+#define IFX_IOM_LAMCFG_MOS_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_LAMCFG_Bits.MOS */
+#define IFX_IOM_LAMCFG_MOS_OFF (2u)
+
+/** \brief Length for Ifx_IOM_LAMCFG_Bits.RCS */
+#define IFX_IOM_LAMCFG_RCS_LEN (4u)
+
+/** \brief Mask for Ifx_IOM_LAMCFG_Bits.RCS */
+#define IFX_IOM_LAMCFG_RCS_MSK (0xfu)
+
+/** \brief Offset for Ifx_IOM_LAMCFG_Bits.RCS */
+#define IFX_IOM_LAMCFG_RCS_OFF (20u)
+
+/** \brief Length for Ifx_IOM_LAMCFG_Bits.RMS */
+#define IFX_IOM_LAMCFG_RMS_LEN (1u)
+
+/** \brief Mask for Ifx_IOM_LAMCFG_Bits.RMS */
+#define IFX_IOM_LAMCFG_RMS_MSK (0x1u)
+
+/** \brief Offset for Ifx_IOM_LAMCFG_Bits.RMS */
+#define IFX_IOM_LAMCFG_RMS_OFF (3u)
+
+/** \brief Length for Ifx_IOM_LAMEWC_Bits.CNT */
+#define IFX_IOM_LAMEWC_CNT_LEN (24u)
+
+/** \brief Mask for Ifx_IOM_LAMEWC_Bits.CNT */
+#define IFX_IOM_LAMEWC_CNT_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_IOM_LAMEWC_Bits.CNT */
+#define IFX_IOM_LAMEWC_CNT_OFF (0u)
+
+/** \brief Length for Ifx_IOM_LAMEWS_Bits.THR */
+#define IFX_IOM_LAMEWS_THR_LEN (24u)
+
+/** \brief Mask for Ifx_IOM_LAMEWS_Bits.THR */
+#define IFX_IOM_LAMEWS_THR_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_IOM_LAMEWS_Bits.THR */
+#define IFX_IOM_LAMEWS_THR_OFF (0u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXIOM_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxIom_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxIom_reg.h
new file mode 100644
index 0000000..39d854f
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxIom_reg.h
@@ -0,0 +1,331 @@
+/**
+ * \file IfxIom_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Iom_Cfg Iom address
+ * \ingroup IfxLld_Iom
+ *
+ * \defgroup IfxLld_Iom_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Iom_Cfg
+ *
+ * \defgroup IfxLld_Iom_Cfg_Iom 2-IOM
+ * \ingroup IfxLld_Iom_Cfg
+ *
+ */
+#ifndef IFXIOM_REG_H
+#define IFXIOM_REG_H 1
+/******************************************************************************/
+#include "IfxIom_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Iom_Cfg_BaseAddress
+ * \{ */
+
+/** \brief IOM object */
+#define MODULE_IOM /*lint --e(923)*/ (*(Ifx_IOM*)0xF0035000u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Iom_Cfg_Iom
+ * \{ */
+
+/** \brief 2C, IOM Access Enable Register 0 */
+#define IOM_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_IOM_ACCEN0*)0xF003502Cu)
+
+/** \brief 28, IOM Access Enable Register 1 */
+#define IOM_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_IOM_ACCEN1*)0xF0035028u)
+
+/** \brief 0, IOM Clock Control Register */
+#define IOM_CLC /*lint --e(923)*/ (*(volatile Ifx_IOM_CLC*)0xF0035000u)
+
+/** \brief 30, IOM Event Combiner Module Counter Configuration Register */
+#define IOM_ECMCCFG /*lint --e(923)*/ (*(volatile Ifx_IOM_ECMCCFG*)0xF0035030u)
+
+/** \brief 38, IOM Event Combiner Module Event Trigger History Register 0 */
+#define IOM_ECMETH0 /*lint --e(923)*/ (*(volatile Ifx_IOM_ECMETH0*)0xF0035038u)
+
+/** \brief 3C, IOM Event Combiner Module Event Trigger History Register 1 */
+#define IOM_ECMETH1 /*lint --e(923)*/ (*(volatile Ifx_IOM_ECMETH1*)0xF003503Cu)
+
+/** \brief 34, IOM Event Combiner Module Global Event Selection Register */
+#define IOM_ECMSELR /*lint --e(923)*/ (*(volatile Ifx_IOM_ECMSELR*)0xF0035034u)
+
+/** \brief 80, IOM Filter and Prescaler Cell Control Register */
+#define IOM_FPCCTR0 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF0035080u)
+
+/** \brief 84, IOM Filter and Prescaler Cell Control Register */
+#define IOM_FPCCTR1 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF0035084u)
+
+/** \brief A8, IOM Filter and Prescaler Cell Control Register */
+#define IOM_FPCCTR10 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF00350A8u)
+
+/** \brief AC, IOM Filter and Prescaler Cell Control Register */
+#define IOM_FPCCTR11 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF00350ACu)
+
+/** \brief B0, IOM Filter and Prescaler Cell Control Register */
+#define IOM_FPCCTR12 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF00350B0u)
+
+/** \brief B4, IOM Filter and Prescaler Cell Control Register */
+#define IOM_FPCCTR13 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF00350B4u)
+
+/** \brief B8, IOM Filter and Prescaler Cell Control Register */
+#define IOM_FPCCTR14 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF00350B8u)
+
+/** \brief BC, IOM Filter and Prescaler Cell Control Register */
+#define IOM_FPCCTR15 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF00350BCu)
+
+/** \brief 88, IOM Filter and Prescaler Cell Control Register */
+#define IOM_FPCCTR2 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF0035088u)
+
+/** \brief 8C, IOM Filter and Prescaler Cell Control Register */
+#define IOM_FPCCTR3 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF003508Cu)
+
+/** \brief 90, IOM Filter and Prescaler Cell Control Register */
+#define IOM_FPCCTR4 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF0035090u)
+
+/** \brief 94, IOM Filter and Prescaler Cell Control Register */
+#define IOM_FPCCTR5 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF0035094u)
+
+/** \brief 98, IOM Filter and Prescaler Cell Control Register */
+#define IOM_FPCCTR6 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF0035098u)
+
+/** \brief 9C, IOM Filter and Prescaler Cell Control Register */
+#define IOM_FPCCTR7 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF003509Cu)
+
+/** \brief A0, IOM Filter and Prescaler Cell Control Register */
+#define IOM_FPCCTR8 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF00350A0u)
+
+/** \brief A4, IOM Filter and Prescaler Cell Control Register */
+#define IOM_FPCCTR9 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF00350A4u)
+
+/** \brief 78, IOM Filter and Prescaler Cells Rising & Falling Edge Status
+ * Register */
+#define IOM_FPCESR /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCESR*)0xF0035078u)
+
+/** \brief C0, IOM Filter and Prescaler Cell Timer Register k */
+#define IOM_FPCTIM0 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350C0u)
+
+/** \brief C4, IOM Filter and Prescaler Cell Timer Register k */
+#define IOM_FPCTIM1 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350C4u)
+
+/** \brief E8, IOM Filter and Prescaler Cell Timer Register k */
+#define IOM_FPCTIM10 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350E8u)
+
+/** \brief EC, IOM Filter and Prescaler Cell Timer Register k */
+#define IOM_FPCTIM11 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350ECu)
+
+/** \brief F0, IOM Filter and Prescaler Cell Timer Register k */
+#define IOM_FPCTIM12 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350F0u)
+
+/** \brief F4, IOM Filter and Prescaler Cell Timer Register k */
+#define IOM_FPCTIM13 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350F4u)
+
+/** \brief F8, IOM Filter and Prescaler Cell Timer Register k */
+#define IOM_FPCTIM14 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350F8u)
+
+/** \brief FC, IOM Filter and Prescaler Cell Timer Register k */
+#define IOM_FPCTIM15 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350FCu)
+
+/** \brief C8, IOM Filter and Prescaler Cell Timer Register k */
+#define IOM_FPCTIM2 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350C8u)
+
+/** \brief CC, IOM Filter and Prescaler Cell Timer Register k */
+#define IOM_FPCTIM3 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350CCu)
+
+/** \brief D0, IOM Filter and Prescaler Cell Timer Register k */
+#define IOM_FPCTIM4 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350D0u)
+
+/** \brief D4, IOM Filter and Prescaler Cell Timer Register k */
+#define IOM_FPCTIM5 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350D4u)
+
+/** \brief D8, IOM Filter and Prescaler Cell Timer Register k */
+#define IOM_FPCTIM6 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350D8u)
+
+/** \brief DC, IOM Filter and Prescaler Cell Timer Register k */
+#define IOM_FPCTIM7 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350DCu)
+
+/** \brief E0, IOM Filter and Prescaler Cell Timer Register k */
+#define IOM_FPCTIM8 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350E0u)
+
+/** \brief E4, IOM Filter and Prescaler Cell Timer Register k */
+#define IOM_FPCTIM9 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350E4u)
+
+/** \brief 40, IOM GTM Input EXOR Combiner Selection Register */
+#define IOM_GTMEXR /*lint --e(923)*/ (*(volatile Ifx_IOM_GTMEXR*)0xF0035040u)
+
+/** \brief 8, IOM Identification Register */
+#define IOM_ID /*lint --e(923)*/ (*(volatile Ifx_IOM_ID*)0xF0035008u)
+
+/** \brief 24, IOM Kernel Reset Register 0 */
+#define IOM_KRST0 /*lint --e(923)*/ (*(volatile Ifx_IOM_KRST0*)0xF0035024u)
+
+/** \brief 20, IOM Kernel Reset Register 1 */
+#define IOM_KRST1 /*lint --e(923)*/ (*(volatile Ifx_IOM_KRST1*)0xF0035020u)
+
+/** \brief 1C, IOM Kernel Reset Status Clear Register */
+#define IOM_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_IOM_KRSTCLR*)0xF003501Cu)
+
+/** \brief 180, IOM Logic Analyzer Module Configuration Register */
+#define IOM_LAMCFG0 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF0035180u)
+
+/** \brief 184, IOM Logic Analyzer Module Configuration Register */
+#define IOM_LAMCFG1 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF0035184u)
+
+/** \brief 1A8, IOM Logic Analyzer Module Configuration Register */
+#define IOM_LAMCFG10 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF00351A8u)
+
+/** \brief 1AC, IOM Logic Analyzer Module Configuration Register */
+#define IOM_LAMCFG11 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF00351ACu)
+
+/** \brief 1B0, IOM Logic Analyzer Module Configuration Register */
+#define IOM_LAMCFG12 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF00351B0u)
+
+/** \brief 1B4, IOM Logic Analyzer Module Configuration Register */
+#define IOM_LAMCFG13 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF00351B4u)
+
+/** \brief 1B8, IOM Logic Analyzer Module Configuration Register */
+#define IOM_LAMCFG14 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF00351B8u)
+
+/** \brief 1BC, IOM Logic Analyzer Module Configuration Register */
+#define IOM_LAMCFG15 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF00351BCu)
+
+/** \brief 188, IOM Logic Analyzer Module Configuration Register */
+#define IOM_LAMCFG2 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF0035188u)
+
+/** \brief 18C, IOM Logic Analyzer Module Configuration Register */
+#define IOM_LAMCFG3 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF003518Cu)
+
+/** \brief 190, IOM Logic Analyzer Module Configuration Register */
+#define IOM_LAMCFG4 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF0035190u)
+
+/** \brief 194, IOM Logic Analyzer Module Configuration Register */
+#define IOM_LAMCFG5 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF0035194u)
+
+/** \brief 198, IOM Logic Analyzer Module Configuration Register */
+#define IOM_LAMCFG6 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF0035198u)
+
+/** \brief 19C, IOM Logic Analyzer Module Configuration Register */
+#define IOM_LAMCFG7 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF003519Cu)
+
+/** \brief 1A0, IOM Logic Analyzer Module Configuration Register */
+#define IOM_LAMCFG8 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF00351A0u)
+
+/** \brief 1A4, IOM Logic Analyzer Module Configuration Register */
+#define IOM_LAMCFG9 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF00351A4u)
+
+/** \brief 100, IOM Logic Analyzer Module Event Window Count Status Register */
+#define IOM_LAMEWC0 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF0035100u)
+
+/** \brief 104, IOM Logic Analyzer Module Event Window Count Status Register */
+#define IOM_LAMEWC1 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF0035104u)
+
+/** \brief 128, IOM Logic Analyzer Module Event Window Count Status Register */
+#define IOM_LAMEWC10 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF0035128u)
+
+/** \brief 12C, IOM Logic Analyzer Module Event Window Count Status Register */
+#define IOM_LAMEWC11 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF003512Cu)
+
+/** \brief 130, IOM Logic Analyzer Module Event Window Count Status Register */
+#define IOM_LAMEWC12 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF0035130u)
+
+/** \brief 134, IOM Logic Analyzer Module Event Window Count Status Register */
+#define IOM_LAMEWC13 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF0035134u)
+
+/** \brief 138, IOM Logic Analyzer Module Event Window Count Status Register */
+#define IOM_LAMEWC14 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF0035138u)
+
+/** \brief 13C, IOM Logic Analyzer Module Event Window Count Status Register */
+#define IOM_LAMEWC15 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF003513Cu)
+
+/** \brief 108, IOM Logic Analyzer Module Event Window Count Status Register */
+#define IOM_LAMEWC2 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF0035108u)
+
+/** \brief 10C, IOM Logic Analyzer Module Event Window Count Status Register */
+#define IOM_LAMEWC3 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF003510Cu)
+
+/** \brief 110, IOM Logic Analyzer Module Event Window Count Status Register */
+#define IOM_LAMEWC4 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF0035110u)
+
+/** \brief 114, IOM Logic Analyzer Module Event Window Count Status Register */
+#define IOM_LAMEWC5 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF0035114u)
+
+/** \brief 118, IOM Logic Analyzer Module Event Window Count Status Register */
+#define IOM_LAMEWC6 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF0035118u)
+
+/** \brief 11C, IOM Logic Analyzer Module Event Window Count Status Register */
+#define IOM_LAMEWC7 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF003511Cu)
+
+/** \brief 120, IOM Logic Analyzer Module Event Window Count Status Register */
+#define IOM_LAMEWC8 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF0035120u)
+
+/** \brief 124, IOM Logic Analyzer Module Event Window Count Status Register */
+#define IOM_LAMEWC9 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF0035124u)
+
+/** \brief 1C0, IOM Logic Analyzer Module Event Window Configuration Register */
+#define IOM_LAMEWS0 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351C0u)
+
+/** \brief 1C4, IOM Logic Analyzer Module Event Window Configuration Register */
+#define IOM_LAMEWS1 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351C4u)
+
+/** \brief 1E8, IOM Logic Analyzer Module Event Window Configuration Register */
+#define IOM_LAMEWS10 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351E8u)
+
+/** \brief 1EC, IOM Logic Analyzer Module Event Window Configuration Register */
+#define IOM_LAMEWS11 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351ECu)
+
+/** \brief 1F0, IOM Logic Analyzer Module Event Window Configuration Register */
+#define IOM_LAMEWS12 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351F0u)
+
+/** \brief 1F4, IOM Logic Analyzer Module Event Window Configuration Register */
+#define IOM_LAMEWS13 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351F4u)
+
+/** \brief 1F8, IOM Logic Analyzer Module Event Window Configuration Register */
+#define IOM_LAMEWS14 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351F8u)
+
+/** \brief 1FC, IOM Logic Analyzer Module Event Window Configuration Register */
+#define IOM_LAMEWS15 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351FCu)
+
+/** \brief 1C8, IOM Logic Analyzer Module Event Window Configuration Register */
+#define IOM_LAMEWS2 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351C8u)
+
+/** \brief 1CC, IOM Logic Analyzer Module Event Window Configuration Register */
+#define IOM_LAMEWS3 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351CCu)
+
+/** \brief 1D0, IOM Logic Analyzer Module Event Window Configuration Register */
+#define IOM_LAMEWS4 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351D0u)
+
+/** \brief 1D4, IOM Logic Analyzer Module Event Window Configuration Register */
+#define IOM_LAMEWS5 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351D4u)
+
+/** \brief 1D8, IOM Logic Analyzer Module Event Window Configuration Register */
+#define IOM_LAMEWS6 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351D8u)
+
+/** \brief 1DC, IOM Logic Analyzer Module Event Window Configuration Register */
+#define IOM_LAMEWS7 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351DCu)
+
+/** \brief 1E0, IOM Logic Analyzer Module Event Window Configuration Register */
+#define IOM_LAMEWS8 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351E0u)
+
+/** \brief 1E4, IOM Logic Analyzer Module Event Window Configuration Register */
+#define IOM_LAMEWS9 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351E4u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXIOM_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxIom_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxIom_regdef.h
new file mode 100644
index 0000000..8ab6636
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxIom_regdef.h
@@ -0,0 +1,533 @@
+/**
+ * \file IfxIom_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Iom Iom
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Iom_Bitfields Bitfields
+ * \ingroup IfxLld_Iom
+ *
+ * \defgroup IfxLld_Iom_union Union
+ * \ingroup IfxLld_Iom
+ *
+ * \defgroup IfxLld_Iom_struct Struct
+ * \ingroup IfxLld_Iom
+ *
+ */
+#ifndef IFXIOM_REGDEF_H
+#define IFXIOM_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Iom_Bitfields
+ * \{ */
+
+/** \brief IOM Access Enable Register 0 */
+typedef struct _Ifx_IOM_ACCEN0_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_IOM_ACCEN0_Bits;
+
+/** \brief IOM Access Enable Register 1 */
+typedef struct _Ifx_IOM_ACCEN1_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_IOM_ACCEN1_Bits;
+
+/** \brief IOM Clock Control Register */
+typedef struct _Ifx_IOM_CLC_Bits
+{
+ unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
+ unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
+ unsigned int reserved_2:1; /**< \brief \internal Reserved */
+ unsigned int EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control (rw) */
+ unsigned int reserved_4:4; /**< \brief \internal Reserved */
+ unsigned int RMC:8; /**< \brief [15:8] 8-bit Clock Divider Value in RUN Mode (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_IOM_CLC_Bits;
+
+/** \brief IOM Event Combiner Module Counter Configuration Register */
+typedef struct _Ifx_IOM_ECMCCFG_Bits
+{
+ unsigned int SELC0:4; /**< \brief [3:0] Event Channel Select (rw) */
+ unsigned int THRC0:4; /**< \brief [7:4] Channel Event Counter Threshold (rw) */
+ unsigned int SELC1:4; /**< \brief [11:8] Event Channel Select (rw) */
+ unsigned int THCR1:4; /**< \brief [15:12] Channel Event Counter Threshold (rw) */
+ unsigned int SELC2:4; /**< \brief [19:16] Event Channel Select (rw) */
+ unsigned int THCR2:4; /**< \brief [23:20] Channel Event Counter Threshold (rw) */
+ unsigned int SELC3:4; /**< \brief [27:24] Event Channel Select (rw) */
+ unsigned int THCR3:4; /**< \brief [31:28] Channel Event Counter Threshold (rw) */
+} Ifx_IOM_ECMCCFG_Bits;
+
+/** \brief IOM Event Combiner Module Event Trigger History Register 0 */
+typedef struct _Ifx_IOM_ECMETH0_Bits
+{
+ unsigned int ETA0:1; /**< \brief [0:0] LAM 0-15 Event Trigger Activity (last) (rwh) */
+ unsigned int ETA1:1; /**< \brief [1:1] LAM 0-15 Event Trigger Activity (last) (rwh) */
+ unsigned int ETA2:1; /**< \brief [2:2] LAM 0-15 Event Trigger Activity (last) (rwh) */
+ unsigned int ETA3:1; /**< \brief [3:3] LAM 0-15 Event Trigger Activity (last) (rwh) */
+ unsigned int ETA4:1; /**< \brief [4:4] LAM 0-15 Event Trigger Activity (last) (rwh) */
+ unsigned int ETA5:1; /**< \brief [5:5] LAM 0-15 Event Trigger Activity (last) (rwh) */
+ unsigned int ETA6:1; /**< \brief [6:6] LAM 0-15 Event Trigger Activity (last) (rwh) */
+ unsigned int ETA7:1; /**< \brief [7:7] LAM 0-15 Event Trigger Activity (last) (rwh) */
+ unsigned int ETA8:1; /**< \brief [8:8] LAM 0-15 Event Trigger Activity (last) (rwh) */
+ unsigned int ETA9:1; /**< \brief [9:9] LAM 0-15 Event Trigger Activity (last) (rwh) */
+ unsigned int ETA10:1; /**< \brief [10:10] LAM 0-15 Event Trigger Activity (last) (rwh) */
+ unsigned int ETA11:1; /**< \brief [11:11] LAM 0-15 Event Trigger Activity (last) (rwh) */
+ unsigned int ETA12:1; /**< \brief [12:12] LAM 0-15 Event Trigger Activity (last) (rwh) */
+ unsigned int ETA13:1; /**< \brief [13:13] LAM 0-15 Event Trigger Activity (last) (rwh) */
+ unsigned int ETA14:1; /**< \brief [14:14] LAM 0-15 Event Trigger Activity (last) (rwh) */
+ unsigned int ETA15:1; /**< \brief [15:15] LAM 0-15 Event Trigger Activity (last) (rwh) */
+ unsigned int ETB0:1; /**< \brief [16:16] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
+ unsigned int ETB1:1; /**< \brief [17:17] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
+ unsigned int ETB2:1; /**< \brief [18:18] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
+ unsigned int ETB3:1; /**< \brief [19:19] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
+ unsigned int ETB4:1; /**< \brief [20:20] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
+ unsigned int ETB5:1; /**< \brief [21:21] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
+ unsigned int ETB6:1; /**< \brief [22:22] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
+ unsigned int ETB7:1; /**< \brief [23:23] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
+ unsigned int ETB8:1; /**< \brief [24:24] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
+ unsigned int ETB9:1; /**< \brief [25:25] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
+ unsigned int ETB10:1; /**< \brief [26:26] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
+ unsigned int ETB11:1; /**< \brief [27:27] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
+ unsigned int ETB12:1; /**< \brief [28:28] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
+ unsigned int ETB13:1; /**< \brief [29:29] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
+ unsigned int ETB14:1; /**< \brief [30:30] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
+ unsigned int ETB15:1; /**< \brief [31:31] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
+} Ifx_IOM_ECMETH0_Bits;
+
+/** \brief IOM Event Combiner Module Event Trigger History Register 1 */
+typedef struct _Ifx_IOM_ECMETH1_Bits
+{
+ unsigned int ETC0:1; /**< \brief [0:0] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
+ unsigned int ETC1:1; /**< \brief [1:1] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
+ unsigned int ETC2:1; /**< \brief [2:2] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
+ unsigned int ETC3:1; /**< \brief [3:3] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
+ unsigned int ETC4:1; /**< \brief [4:4] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
+ unsigned int ETC5:1; /**< \brief [5:5] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
+ unsigned int ETC6:1; /**< \brief [6:6] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
+ unsigned int ETC7:1; /**< \brief [7:7] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
+ unsigned int ETC8:1; /**< \brief [8:8] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
+ unsigned int ETC9:1; /**< \brief [9:9] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
+ unsigned int ETC10:1; /**< \brief [10:10] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
+ unsigned int ETC11:1; /**< \brief [11:11] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
+ unsigned int ETC12:1; /**< \brief [12:12] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
+ unsigned int ETC13:1; /**< \brief [13:13] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
+ unsigned int ETC14:1; /**< \brief [14:14] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
+ unsigned int ETC15:1; /**< \brief [15:15] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
+ unsigned int ETD0:1; /**< \brief [16:16] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
+ unsigned int ETD1:1; /**< \brief [17:17] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
+ unsigned int ETD2:1; /**< \brief [18:18] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
+ unsigned int ETD3:1; /**< \brief [19:19] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
+ unsigned int ETD4:1; /**< \brief [20:20] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
+ unsigned int ETD5:1; /**< \brief [21:21] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
+ unsigned int ETD6:1; /**< \brief [22:22] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
+ unsigned int ETD7:1; /**< \brief [23:23] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
+ unsigned int ETD8:1; /**< \brief [24:24] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
+ unsigned int ETD9:1; /**< \brief [25:25] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
+ unsigned int ETD10:1; /**< \brief [26:26] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
+ unsigned int ETD11:1; /**< \brief [27:27] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
+ unsigned int ETD12:1; /**< \brief [28:28] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
+ unsigned int ETD13:1; /**< \brief [29:29] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
+ unsigned int ETD14:1; /**< \brief [30:30] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
+ unsigned int ETD15:1; /**< \brief [31:31] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
+} Ifx_IOM_ECMETH1_Bits;
+
+/** \brief IOM Event Combiner Module Global Event Selection Register */
+typedef struct _Ifx_IOM_ECMSELR_Bits
+{
+ unsigned int CES0:1; /**< \brief [0:0] Event Combiner Selection (rw) */
+ unsigned int CES1:1; /**< \brief [1:1] Event Combiner Selection (rw) */
+ unsigned int CES2:1; /**< \brief [2:2] Event Combiner Selection (rw) */
+ unsigned int CES3:1; /**< \brief [3:3] Event Combiner Selection (rw) */
+ unsigned int CES4:1; /**< \brief [4:4] Event Combiner Selection (rw) */
+ unsigned int CES5:1; /**< \brief [5:5] Event Combiner Selection (rw) */
+ unsigned int CES6:1; /**< \brief [6:6] Event Combiner Selection (rw) */
+ unsigned int CES7:1; /**< \brief [7:7] Event Combiner Selection (rw) */
+ unsigned int CES8:1; /**< \brief [8:8] Event Combiner Selection (rw) */
+ unsigned int CES9:1; /**< \brief [9:9] Event Combiner Selection (rw) */
+ unsigned int CES10:1; /**< \brief [10:10] Event Combiner Selection (rw) */
+ unsigned int CES11:1; /**< \brief [11:11] Event Combiner Selection (rw) */
+ unsigned int CES12:1; /**< \brief [12:12] Event Combiner Selection (rw) */
+ unsigned int CES13:1; /**< \brief [13:13] Event Combiner Selection (rw) */
+ unsigned int CES14:1; /**< \brief [14:14] Event Combiner Selection (rw) */
+ unsigned int CES15:1; /**< \brief [15:15] Event Combiner Selection (rw) */
+ unsigned int CTS0:1; /**< \brief [16:16] Accumulated (Counted) Event Combiner Selection (rw) */
+ unsigned int CTS1:1; /**< \brief [17:17] Accumulated (Counted) Event Combiner Selection (rw) */
+ unsigned int CTS2:1; /**< \brief [18:18] Accumulated (Counted) Event Combiner Selection (rw) */
+ unsigned int CTS3:1; /**< \brief [19:19] Accumulated (Counted) Event Combiner Selection (rw) */
+ unsigned int reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_IOM_ECMSELR_Bits;
+
+/** \brief IOM Filter and Prescaler Cell Control Register */
+typedef struct _Ifx_IOM_FPCCTR_Bits
+{
+ unsigned int CMP:16; /**< \brief [15:0] Threshold Value of Filter & Prescaler Cell k (rw) */
+ unsigned int MOD:3; /**< \brief [18:16] Operation Mode Selection for Filter & Prescaler Cell k (rw) */
+ unsigned int ISM:2; /**< \brief [20:19] Monitor Input Signal Selection for Filter & Prescaler Cell k (rw) */
+ unsigned int reserved_21:1; /**< \brief \internal Reserved */
+ unsigned int RTG:1; /**< \brief [22:22] Reset Timer behaviour for Filter & Prescaler Cell k on Glitch (rw) */
+ unsigned int reserved_23:1; /**< \brief \internal Reserved */
+ unsigned int ISR:3; /**< \brief [26:24] Reference Input Signal Selection for Filter & Prescaler Cell k (rw) */
+ unsigned int reserved_27:5; /**< \brief \internal Reserved */
+} Ifx_IOM_FPCCTR_Bits;
+
+/** \brief IOM Filter and Prescaler Cells Rising & Falling Edge Status Register */
+typedef struct _Ifx_IOM_FPCESR_Bits
+{
+ unsigned int FEG0:1; /**< \brief [0:0] Falling Edge Glitch Flag for FPC0 (rwh) */
+ unsigned int FEG1:1; /**< \brief [1:1] Falling Edge Glitch Flag for FPC1 (rwh) */
+ unsigned int FEG2:1; /**< \brief [2:2] Falling Edge Glitch Flag for FPC2 (rwh) */
+ unsigned int FEG3:1; /**< \brief [3:3] Falling Edge Glitch Flag for FPC3 (rwh) */
+ unsigned int FEG4:1; /**< \brief [4:4] Falling Edge Glitch Flag for FPC4 (rwh) */
+ unsigned int FEG5:1; /**< \brief [5:5] Falling Edge Glitch Flag for FPC5 (rwh) */
+ unsigned int FEG6:1; /**< \brief [6:6] Falling Edge Glitch Flag for FPC6 (rwh) */
+ unsigned int FEG7:1; /**< \brief [7:7] Falling Edge Glitch Flag for FPC7 (rwh) */
+ unsigned int FEG8:1; /**< \brief [8:8] Falling Edge Glitch Flag for FPC8 (rwh) */
+ unsigned int FEG9:1; /**< \brief [9:9] Falling Edge Glitch Flag for FPC9 (rwh) */
+ unsigned int FEG10:1; /**< \brief [10:10] Falling Edge Glitch Flag for FPC10 (rwh) */
+ unsigned int FEG11:1; /**< \brief [11:11] Falling Edge Glitch Flag for FPC11 (rwh) */
+ unsigned int FEG12:1; /**< \brief [12:12] Falling Edge Glitch Flag for FPC12 (rwh) */
+ unsigned int FEG13:1; /**< \brief [13:13] Falling Edge Glitch Flag for FPC13 (rwh) */
+ unsigned int FEG14:1; /**< \brief [14:14] Falling Edge Glitch Flag for FPC14 (rwh) */
+ unsigned int FEG15:1; /**< \brief [15:15] Falling Edge Glitch Flag for FPC15 (rwh) */
+ unsigned int REG0:1; /**< \brief [16:16] Rising Edge Glitch Flag for FPC0 (rwh) */
+ unsigned int REG1:1; /**< \brief [17:17] Rising Edge Glitch Flag for FPC1 (rwh) */
+ unsigned int REG2:1; /**< \brief [18:18] Rising Edge Glitch Flag for FPC2 (rwh) */
+ unsigned int REG3:1; /**< \brief [19:19] Rising Edge Glitch Flag for FPC3 (rwh) */
+ unsigned int REG4:1; /**< \brief [20:20] Rising Edge Glitch Flag for FPC4 (rwh) */
+ unsigned int REG5:1; /**< \brief [21:21] Rising Edge Glitch Flag for FPC5 (rwh) */
+ unsigned int REG6:1; /**< \brief [22:22] Rising Edge Glitch Flag for FPC6 (rwh) */
+ unsigned int REG7:1; /**< \brief [23:23] Rising Edge Glitch Flag for FPC7 (rwh) */
+ unsigned int REG8:1; /**< \brief [24:24] Rising Edge Glitch Flag for FPC8 (rwh) */
+ unsigned int REG9:1; /**< \brief [25:25] Rising Edge Glitch Flag for FPC9 (rwh) */
+ unsigned int REG10:1; /**< \brief [26:26] Rising Edge Glitch Flag for FPC10 (rwh) */
+ unsigned int REG11:1; /**< \brief [27:27] Rising Edge Glitch Flag for FPC11 (rwh) */
+ unsigned int REG12:1; /**< \brief [28:28] Rising Edge Glitch Flag for FPC12 (rwh) */
+ unsigned int REG13:1; /**< \brief [29:29] Rising Edge Glitch Flag for FPC13 (rwh) */
+ unsigned int REG14:1; /**< \brief [30:30] Rising Edge Glitch Flag for FPC14 (rwh) */
+ unsigned int REG15:1; /**< \brief [31:31] Rising Edge Glitch Flag for FPC15 (rwh) */
+} Ifx_IOM_FPCESR_Bits;
+
+/** \brief IOM Filter and Prescaler Cell Timer Register k */
+typedef struct _Ifx_IOM_FPCTIM_Bits
+{
+ unsigned int TIM:16; /**< \brief [15:0] Timer Value of Filter and Prescaler Cell k (rwh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_IOM_FPCTIM_Bits;
+
+/** \brief IOM GTM Input EXOR Combiner Selection Register */
+typedef struct _Ifx_IOM_GTMEXR_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] GTM input 0 selection for EXOR combiner (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] GTM input 1 selection for EXOR combiner (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] GTM input 2 selection for EXOR combiner (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] GTM input 3 selection for EXOR combiner (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] GTM input 4 selection for EXOR combiner (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] GTM input 5 selection for EXOR combiner (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] GTM input 6 selection for EXOR combiner (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] GTM input 7 selection for EXOR combiner (rw) */
+ unsigned int reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_IOM_GTMEXR_Bits;
+
+/** \brief IOM Identification Register */
+typedef struct _Ifx_IOM_ID_Bits
+{
+ unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ unsigned int MODTYPE:8; /**< \brief [15:8] Module Number Value (r) */
+ unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_IOM_ID_Bits;
+
+/** \brief IOM Kernel Reset Register 0 */
+typedef struct _Ifx_IOM_KRST0_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rh) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_IOM_KRST0_Bits;
+
+/** \brief IOM Kernel Reset Register 1 */
+typedef struct _Ifx_IOM_KRST1_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_IOM_KRST1_Bits;
+
+/** \brief IOM Kernel Reset Status Clear Register */
+typedef struct _Ifx_IOM_KRSTCLR_Bits
+{
+ unsigned int CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_IOM_KRSTCLR_Bits;
+
+/** \brief IOM Logic Analyzer Module Configuration Register */
+typedef struct _Ifx_IOM_LAMCFG_Bits
+{
+ unsigned int IVR:1; /**< \brief [0:0] Invert Reference LAM block m (rw) */
+ unsigned int IVM:1; /**< \brief [1:1] Invert Monitor LAM block m (rw) */
+ unsigned int MOS:1; /**< \brief [2:2] Monitor Source Select LAM block m (rw) */
+ unsigned int RMS:1; /**< \brief [3:3] Runmode Select LAM block m (rw) */
+ unsigned int EWS:1; /**< \brief [4:4] Event Window Select LAM block m (rw) */
+ unsigned int reserved_5:3; /**< \brief \internal Reserved */
+ unsigned int EDS:4; /**< \brief [11:8] Event Window Active Edge Selection LAM block m (rw) */
+ unsigned int IVW:1; /**< \brief [12:12] Invert Event Window LAM block m (rw) */
+ unsigned int reserved_13:3; /**< \brief \internal Reserved */
+ unsigned int MCS:4; /**< \brief [19:16] Monitor Input Signal Selection LAM block m (rw) */
+ unsigned int RCS:4; /**< \brief [23:20] Reference Input Signal Selection LAM block m (rw) */
+ unsigned int reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_IOM_LAMCFG_Bits;
+
+/** \brief IOM Logic Analyzer Module Event Window Count Status Register */
+typedef struct _Ifx_IOM_LAMEWC_Bits
+{
+ unsigned int CNT:24; /**< \brief [23:0] Event Window Count Value LAM block m (r) */
+ unsigned int reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_IOM_LAMEWC_Bits;
+
+/** \brief IOM Logic Analyzer Module Event Window Configuration Register */
+typedef struct _Ifx_IOM_LAMEWS_Bits
+{
+ unsigned int THR:24; /**< \brief [23:0] Event Window Count Threshold (rw) */
+ unsigned int reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_IOM_LAMEWS_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Iom_union
+ * \{ */
+
+/** \brief IOM Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_IOM_ACCEN0_Bits B; /**< \brief Bitfield access */
+} Ifx_IOM_ACCEN0;
+
+/** \brief IOM Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_IOM_ACCEN1_Bits B; /**< \brief Bitfield access */
+} Ifx_IOM_ACCEN1;
+
+/** \brief IOM Clock Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_IOM_CLC_Bits B; /**< \brief Bitfield access */
+} Ifx_IOM_CLC;
+
+/** \brief IOM Event Combiner Module Counter Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_IOM_ECMCCFG_Bits B; /**< \brief Bitfield access */
+} Ifx_IOM_ECMCCFG;
+
+/** \brief IOM Event Combiner Module Event Trigger History Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_IOM_ECMETH0_Bits B; /**< \brief Bitfield access */
+} Ifx_IOM_ECMETH0;
+
+/** \brief IOM Event Combiner Module Event Trigger History Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_IOM_ECMETH1_Bits B; /**< \brief Bitfield access */
+} Ifx_IOM_ECMETH1;
+
+/** \brief IOM Event Combiner Module Global Event Selection Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_IOM_ECMSELR_Bits B; /**< \brief Bitfield access */
+} Ifx_IOM_ECMSELR;
+
+/** \brief IOM Filter and Prescaler Cell Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_IOM_FPCCTR_Bits B; /**< \brief Bitfield access */
+} Ifx_IOM_FPCCTR;
+
+/** \brief IOM Filter and Prescaler Cells Rising & Falling Edge Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_IOM_FPCESR_Bits B; /**< \brief Bitfield access */
+} Ifx_IOM_FPCESR;
+
+/** \brief IOM Filter and Prescaler Cell Timer Register k */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_IOM_FPCTIM_Bits B; /**< \brief Bitfield access */
+} Ifx_IOM_FPCTIM;
+
+/** \brief IOM GTM Input EXOR Combiner Selection Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_IOM_GTMEXR_Bits B; /**< \brief Bitfield access */
+} Ifx_IOM_GTMEXR;
+
+/** \brief IOM Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_IOM_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_IOM_ID;
+
+/** \brief IOM Kernel Reset Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_IOM_KRST0_Bits B; /**< \brief Bitfield access */
+} Ifx_IOM_KRST0;
+
+/** \brief IOM Kernel Reset Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_IOM_KRST1_Bits B; /**< \brief Bitfield access */
+} Ifx_IOM_KRST1;
+
+/** \brief IOM Kernel Reset Status Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_IOM_KRSTCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_IOM_KRSTCLR;
+
+/** \brief IOM Logic Analyzer Module Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_IOM_LAMCFG_Bits B; /**< \brief Bitfield access */
+} Ifx_IOM_LAMCFG;
+
+/** \brief IOM Logic Analyzer Module Event Window Count Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_IOM_LAMEWC_Bits B; /**< \brief Bitfield access */
+} Ifx_IOM_LAMEWC;
+
+/** \brief IOM Logic Analyzer Module Event Window Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_IOM_LAMEWS_Bits B; /**< \brief Bitfield access */
+} Ifx_IOM_LAMEWS;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Iom_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief IOM object */
+typedef volatile struct _Ifx_IOM
+{
+ Ifx_IOM_CLC CLC; /**< \brief 0, IOM Clock Control Register */
+ unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
+ Ifx_IOM_ID ID; /**< \brief 8, IOM Identification Register */
+ unsigned char reserved_C[16]; /**< \brief C, \internal Reserved */
+ Ifx_IOM_KRSTCLR KRSTCLR; /**< \brief 1C, IOM Kernel Reset Status Clear Register */
+ Ifx_IOM_KRST1 KRST1; /**< \brief 20, IOM Kernel Reset Register 1 */
+ Ifx_IOM_KRST0 KRST0; /**< \brief 24, IOM Kernel Reset Register 0 */
+ Ifx_IOM_ACCEN1 ACCEN1; /**< \brief 28, IOM Access Enable Register 1 */
+ Ifx_IOM_ACCEN0 ACCEN0; /**< \brief 2C, IOM Access Enable Register 0 */
+ Ifx_IOM_ECMCCFG ECMCCFG; /**< \brief 30, IOM Event Combiner Module Counter Configuration Register */
+ Ifx_IOM_ECMSELR ECMSELR; /**< \brief 34, IOM Event Combiner Module Global Event Selection Register */
+ Ifx_IOM_ECMETH0 ECMETH0; /**< \brief 38, IOM Event Combiner Module Event Trigger History Register 0 */
+ Ifx_IOM_ECMETH1 ECMETH1; /**< \brief 3C, IOM Event Combiner Module Event Trigger History Register 1 */
+ Ifx_IOM_GTMEXR GTMEXR; /**< \brief 40, IOM GTM Input EXOR Combiner Selection Register */
+ unsigned char reserved_44[52]; /**< \brief 44, \internal Reserved */
+ Ifx_IOM_FPCESR FPCESR; /**< \brief 78, IOM Filter and Prescaler Cells Rising & Falling Edge Status Register */
+ unsigned char reserved_7C[4]; /**< \brief 7C, \internal Reserved */
+ Ifx_IOM_FPCCTR FPCCTR[16]; /**< \brief 80, IOM Filter and Prescaler Cell Control Register */
+ Ifx_IOM_FPCTIM FPCTIM[16]; /**< \brief C0, IOM Filter and Prescaler Cell Timer Register k */
+ Ifx_IOM_LAMEWC LAMEWC[16]; /**< \brief 100, IOM Logic Analyzer Module Event Window Count Status Register */
+ unsigned char reserved_140[64]; /**< \brief 140, \internal Reserved */
+ Ifx_IOM_LAMCFG LAMCFG[16]; /**< \brief 180, IOM Logic Analyzer Module Configuration Register */
+ Ifx_IOM_LAMEWS LAMEWS[16]; /**< \brief 1C0, IOM Logic Analyzer Module Event Window Configuration Register */
+} Ifx_IOM;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXIOM_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxLmu_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxLmu_bf.h
new file mode 100644
index 0000000..2db0186
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxLmu_bf.h
@@ -0,0 +1,477 @@
+/**
+ * \file IfxLmu_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Lmu_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Lmu
+ *
+ */
+#ifndef IFXLMU_BF_H
+#define IFXLMU_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Lmu_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN0 */
+#define IFX_LMU_ACCEN0_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN0 */
+#define IFX_LMU_ACCEN0_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN0 */
+#define IFX_LMU_ACCEN0_EN0_OFF (0u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN10 */
+#define IFX_LMU_ACCEN0_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN10 */
+#define IFX_LMU_ACCEN0_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN10 */
+#define IFX_LMU_ACCEN0_EN10_OFF (10u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN11 */
+#define IFX_LMU_ACCEN0_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN11 */
+#define IFX_LMU_ACCEN0_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN11 */
+#define IFX_LMU_ACCEN0_EN11_OFF (11u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN12 */
+#define IFX_LMU_ACCEN0_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN12 */
+#define IFX_LMU_ACCEN0_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN12 */
+#define IFX_LMU_ACCEN0_EN12_OFF (12u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN13 */
+#define IFX_LMU_ACCEN0_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN13 */
+#define IFX_LMU_ACCEN0_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN13 */
+#define IFX_LMU_ACCEN0_EN13_OFF (13u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN14 */
+#define IFX_LMU_ACCEN0_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN14 */
+#define IFX_LMU_ACCEN0_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN14 */
+#define IFX_LMU_ACCEN0_EN14_OFF (14u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN15 */
+#define IFX_LMU_ACCEN0_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN15 */
+#define IFX_LMU_ACCEN0_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN15 */
+#define IFX_LMU_ACCEN0_EN15_OFF (15u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN16 */
+#define IFX_LMU_ACCEN0_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN16 */
+#define IFX_LMU_ACCEN0_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN16 */
+#define IFX_LMU_ACCEN0_EN16_OFF (16u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN17 */
+#define IFX_LMU_ACCEN0_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN17 */
+#define IFX_LMU_ACCEN0_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN17 */
+#define IFX_LMU_ACCEN0_EN17_OFF (17u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN18 */
+#define IFX_LMU_ACCEN0_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN18 */
+#define IFX_LMU_ACCEN0_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN18 */
+#define IFX_LMU_ACCEN0_EN18_OFF (18u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN19 */
+#define IFX_LMU_ACCEN0_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN19 */
+#define IFX_LMU_ACCEN0_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN19 */
+#define IFX_LMU_ACCEN0_EN19_OFF (19u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN1 */
+#define IFX_LMU_ACCEN0_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN1 */
+#define IFX_LMU_ACCEN0_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN1 */
+#define IFX_LMU_ACCEN0_EN1_OFF (1u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN20 */
+#define IFX_LMU_ACCEN0_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN20 */
+#define IFX_LMU_ACCEN0_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN20 */
+#define IFX_LMU_ACCEN0_EN20_OFF (20u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN21 */
+#define IFX_LMU_ACCEN0_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN21 */
+#define IFX_LMU_ACCEN0_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN21 */
+#define IFX_LMU_ACCEN0_EN21_OFF (21u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN22 */
+#define IFX_LMU_ACCEN0_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN22 */
+#define IFX_LMU_ACCEN0_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN22 */
+#define IFX_LMU_ACCEN0_EN22_OFF (22u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN23 */
+#define IFX_LMU_ACCEN0_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN23 */
+#define IFX_LMU_ACCEN0_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN23 */
+#define IFX_LMU_ACCEN0_EN23_OFF (23u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN24 */
+#define IFX_LMU_ACCEN0_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN24 */
+#define IFX_LMU_ACCEN0_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN24 */
+#define IFX_LMU_ACCEN0_EN24_OFF (24u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN25 */
+#define IFX_LMU_ACCEN0_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN25 */
+#define IFX_LMU_ACCEN0_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN25 */
+#define IFX_LMU_ACCEN0_EN25_OFF (25u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN26 */
+#define IFX_LMU_ACCEN0_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN26 */
+#define IFX_LMU_ACCEN0_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN26 */
+#define IFX_LMU_ACCEN0_EN26_OFF (26u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN27 */
+#define IFX_LMU_ACCEN0_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN27 */
+#define IFX_LMU_ACCEN0_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN27 */
+#define IFX_LMU_ACCEN0_EN27_OFF (27u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN28 */
+#define IFX_LMU_ACCEN0_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN28 */
+#define IFX_LMU_ACCEN0_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN28 */
+#define IFX_LMU_ACCEN0_EN28_OFF (28u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN29 */
+#define IFX_LMU_ACCEN0_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN29 */
+#define IFX_LMU_ACCEN0_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN29 */
+#define IFX_LMU_ACCEN0_EN29_OFF (29u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN2 */
+#define IFX_LMU_ACCEN0_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN2 */
+#define IFX_LMU_ACCEN0_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN2 */
+#define IFX_LMU_ACCEN0_EN2_OFF (2u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN30 */
+#define IFX_LMU_ACCEN0_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN30 */
+#define IFX_LMU_ACCEN0_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN30 */
+#define IFX_LMU_ACCEN0_EN30_OFF (30u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN31 */
+#define IFX_LMU_ACCEN0_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN31 */
+#define IFX_LMU_ACCEN0_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN31 */
+#define IFX_LMU_ACCEN0_EN31_OFF (31u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN3 */
+#define IFX_LMU_ACCEN0_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN3 */
+#define IFX_LMU_ACCEN0_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN3 */
+#define IFX_LMU_ACCEN0_EN3_OFF (3u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN4 */
+#define IFX_LMU_ACCEN0_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN4 */
+#define IFX_LMU_ACCEN0_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN4 */
+#define IFX_LMU_ACCEN0_EN4_OFF (4u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN5 */
+#define IFX_LMU_ACCEN0_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN5 */
+#define IFX_LMU_ACCEN0_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN5 */
+#define IFX_LMU_ACCEN0_EN5_OFF (5u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN6 */
+#define IFX_LMU_ACCEN0_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN6 */
+#define IFX_LMU_ACCEN0_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN6 */
+#define IFX_LMU_ACCEN0_EN6_OFF (6u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN7 */
+#define IFX_LMU_ACCEN0_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN7 */
+#define IFX_LMU_ACCEN0_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN7 */
+#define IFX_LMU_ACCEN0_EN7_OFF (7u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN8 */
+#define IFX_LMU_ACCEN0_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN8 */
+#define IFX_LMU_ACCEN0_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN8 */
+#define IFX_LMU_ACCEN0_EN8_OFF (8u)
+
+/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN9 */
+#define IFX_LMU_ACCEN0_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN9 */
+#define IFX_LMU_ACCEN0_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN9 */
+#define IFX_LMU_ACCEN0_EN9_OFF (9u)
+
+/** \brief Length for Ifx_LMU_BUFCON_Bits.EN1 */
+#define IFX_LMU_BUFCON_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_BUFCON_Bits.EN1 */
+#define IFX_LMU_BUFCON_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_BUFCON_Bits.EN1 */
+#define IFX_LMU_BUFCON_EN1_OFF (30u)
+
+/** \brief Length for Ifx_LMU_BUFCON_Bits.EN2 */
+#define IFX_LMU_BUFCON_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_BUFCON_Bits.EN2 */
+#define IFX_LMU_BUFCON_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_BUFCON_Bits.EN2 */
+#define IFX_LMU_BUFCON_EN2_OFF (31u)
+
+/** \brief Length for Ifx_LMU_BUFCON_Bits.EPEN */
+#define IFX_LMU_BUFCON_EPEN_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_BUFCON_Bits.EPEN */
+#define IFX_LMU_BUFCON_EPEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_BUFCON_Bits.EPEN */
+#define IFX_LMU_BUFCON_EPEN_OFF (23u)
+
+/** \brief Length for Ifx_LMU_BUFCON_Bits.EREN */
+#define IFX_LMU_BUFCON_EREN_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_BUFCON_Bits.EREN */
+#define IFX_LMU_BUFCON_EREN_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_BUFCON_Bits.EREN */
+#define IFX_LMU_BUFCON_EREN_OFF (22u)
+
+/** \brief Length for Ifx_LMU_BUFCON_Bits.TAG1 */
+#define IFX_LMU_BUFCON_TAG1_LEN (6u)
+
+/** \brief Mask for Ifx_LMU_BUFCON_Bits.TAG1 */
+#define IFX_LMU_BUFCON_TAG1_MSK (0x3fu)
+
+/** \brief Offset for Ifx_LMU_BUFCON_Bits.TAG1 */
+#define IFX_LMU_BUFCON_TAG1_OFF (0u)
+
+/** \brief Length for Ifx_LMU_BUFCON_Bits.TAG2 */
+#define IFX_LMU_BUFCON_TAG2_LEN (6u)
+
+/** \brief Mask for Ifx_LMU_BUFCON_Bits.TAG2 */
+#define IFX_LMU_BUFCON_TAG2_MSK (0x3fu)
+
+/** \brief Offset for Ifx_LMU_BUFCON_Bits.TAG2 */
+#define IFX_LMU_BUFCON_TAG2_OFF (8u)
+
+/** \brief Length for Ifx_LMU_CLC_Bits.DISR */
+#define IFX_LMU_CLC_DISR_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_CLC_Bits.DISR */
+#define IFX_LMU_CLC_DISR_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_CLC_Bits.DISR */
+#define IFX_LMU_CLC_DISR_OFF (0u)
+
+/** \brief Length for Ifx_LMU_CLC_Bits.DISS */
+#define IFX_LMU_CLC_DISS_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_CLC_Bits.DISS */
+#define IFX_LMU_CLC_DISS_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_CLC_Bits.DISS */
+#define IFX_LMU_CLC_DISS_OFF (1u)
+
+/** \brief Length for Ifx_LMU_MEMCON_Bits.ADDERR */
+#define IFX_LMU_MEMCON_ADDERR_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_MEMCON_Bits.ADDERR */
+#define IFX_LMU_MEMCON_ADDERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_MEMCON_Bits.ADDERR */
+#define IFX_LMU_MEMCON_ADDERR_OFF (7u)
+
+/** \brief Length for Ifx_LMU_MEMCON_Bits.DATAERR */
+#define IFX_LMU_MEMCON_DATAERR_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_MEMCON_Bits.DATAERR */
+#define IFX_LMU_MEMCON_DATAERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_MEMCON_Bits.DATAERR */
+#define IFX_LMU_MEMCON_DATAERR_OFF (6u)
+
+/** \brief Length for Ifx_LMU_MEMCON_Bits.ERERR */
+#define IFX_LMU_MEMCON_ERERR_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_MEMCON_Bits.ERERR */
+#define IFX_LMU_MEMCON_ERERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_MEMCON_Bits.ERERR */
+#define IFX_LMU_MEMCON_ERERR_OFF (3u)
+
+/** \brief Length for Ifx_LMU_MEMCON_Bits.EWERR */
+#define IFX_LMU_MEMCON_EWERR_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_MEMCON_Bits.EWERR */
+#define IFX_LMU_MEMCON_EWERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_MEMCON_Bits.EWERR */
+#define IFX_LMU_MEMCON_EWERR_OFF (5u)
+
+/** \brief Length for Ifx_LMU_MEMCON_Bits.FFTPFT */
+#define IFX_LMU_MEMCON_FFTPFT_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_MEMCON_Bits.FFTPFT */
+#define IFX_LMU_MEMCON_FFTPFT_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_MEMCON_Bits.FFTPFT */
+#define IFX_LMU_MEMCON_FFTPFT_OFF (10u)
+
+/** \brief Length for Ifx_LMU_MEMCON_Bits.OLDAEN */
+#define IFX_LMU_MEMCON_OLDAEN_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_MEMCON_Bits.OLDAEN */
+#define IFX_LMU_MEMCON_OLDAEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_MEMCON_Bits.OLDAEN */
+#define IFX_LMU_MEMCON_OLDAEN_OFF (0u)
+
+/** \brief Length for Ifx_LMU_MEMCON_Bits.POLDAEN */
+#define IFX_LMU_MEMCON_POLDAEN_LEN (1u)
+
+/** \brief Mask for Ifx_LMU_MEMCON_Bits.POLDAEN */
+#define IFX_LMU_MEMCON_POLDAEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_LMU_MEMCON_Bits.POLDAEN */
+#define IFX_LMU_MEMCON_POLDAEN_OFF (1u)
+
+/** \brief Length for Ifx_LMU_MEMCON_Bits.WSTATES */
+#define IFX_LMU_MEMCON_WSTATES_LEN (4u)
+
+/** \brief Mask for Ifx_LMU_MEMCON_Bits.WSTATES */
+#define IFX_LMU_MEMCON_WSTATES_MSK (0xfu)
+
+/** \brief Offset for Ifx_LMU_MEMCON_Bits.WSTATES */
+#define IFX_LMU_MEMCON_WSTATES_OFF (12u)
+
+/** \brief Length for Ifx_LMU_MODID_Bits.ID_VALUE */
+#define IFX_LMU_MODID_ID_VALUE_LEN (32u)
+
+/** \brief Mask for Ifx_LMU_MODID_Bits.ID_VALUE */
+#define IFX_LMU_MODID_ID_VALUE_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_LMU_MODID_Bits.ID_VALUE */
+#define IFX_LMU_MODID_ID_VALUE_OFF (0u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXLMU_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxLmu_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxLmu_reg.h
new file mode 100644
index 0000000..231daea
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxLmu_reg.h
@@ -0,0 +1,75 @@
+/**
+ * \file IfxLmu_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Lmu_Cfg Lmu address
+ * \ingroup IfxLld_Lmu
+ *
+ * \defgroup IfxLld_Lmu_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Lmu_Cfg
+ *
+ * \defgroup IfxLld_Lmu_Cfg_Lmu 2-LMU
+ * \ingroup IfxLld_Lmu_Cfg
+ *
+ */
+#ifndef IFXLMU_REG_H
+#define IFXLMU_REG_H 1
+/******************************************************************************/
+#include "IfxLmu_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Lmu_Cfg_BaseAddress
+ * \{ */
+
+/** \brief LMU object */
+#define MODULE_LMU /*lint --e(923)*/ (*(Ifx_LMU*)0xF8700800u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Lmu_Cfg_Lmu
+ * \{ */
+
+/** \brief 10, LMU Access Enable Register 0 */
+#define LMU_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_LMU_ACCEN0*)0xF8700810u)
+
+/** \brief 14, LMU Access Enable Register 1 */
+#define LMU_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_LMU_ACCEN1*)0xF8700814u)
+
+/** \brief 30, LMU Buffer Control Register */
+#define LMU_BUFCON0 /*lint --e(923)*/ (*(volatile Ifx_LMU_BUFCON*)0xF8700830u)
+
+/** \brief 34, LMU Buffer Control Register */
+#define LMU_BUFCON1 /*lint --e(923)*/ (*(volatile Ifx_LMU_BUFCON*)0xF8700834u)
+
+/** \brief 38, LMU Buffer Control Register */
+#define LMU_BUFCON2 /*lint --e(923)*/ (*(volatile Ifx_LMU_BUFCON*)0xF8700838u)
+
+/** \brief 0, LMU Clock Control Register */
+#define LMU_CLC /*lint --e(923)*/ (*(volatile Ifx_LMU_CLC*)0xF8700800u)
+
+/** \brief 20, LMU Memory Control Register */
+#define LMU_MEMCON /*lint --e(923)*/ (*(volatile Ifx_LMU_MEMCON*)0xF8700820u)
+
+/** \brief 8, LMU Module ID Register */
+#define LMU_MODID /*lint --e(923)*/ (*(volatile Ifx_LMU_MODID*)0xF8700808u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXLMU_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxLmu_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxLmu_regdef.h
new file mode 100644
index 0000000..cfb124d
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxLmu_regdef.h
@@ -0,0 +1,214 @@
+/**
+ * \file IfxLmu_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Lmu Lmu
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Lmu_Bitfields Bitfields
+ * \ingroup IfxLld_Lmu
+ *
+ * \defgroup IfxLld_Lmu_union Union
+ * \ingroup IfxLld_Lmu
+ *
+ * \defgroup IfxLld_Lmu_struct Struct
+ * \ingroup IfxLld_Lmu
+ *
+ */
+#ifndef IFXLMU_REGDEF_H
+#define IFXLMU_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Lmu_Bitfields
+ * \{ */
+
+/** \brief LMU Access Enable Register 0 */
+typedef struct _Ifx_LMU_ACCEN0_Bits
+{
+ Ifx_Strict_32Bit EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ Ifx_Strict_32Bit EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ Ifx_Strict_32Bit EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ Ifx_Strict_32Bit EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ Ifx_Strict_32Bit EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ Ifx_Strict_32Bit EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ Ifx_Strict_32Bit EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ Ifx_Strict_32Bit EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ Ifx_Strict_32Bit EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ Ifx_Strict_32Bit EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ Ifx_Strict_32Bit EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ Ifx_Strict_32Bit EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ Ifx_Strict_32Bit EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ Ifx_Strict_32Bit EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ Ifx_Strict_32Bit EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ Ifx_Strict_32Bit EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ Ifx_Strict_32Bit EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ Ifx_Strict_32Bit EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ Ifx_Strict_32Bit EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ Ifx_Strict_32Bit EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ Ifx_Strict_32Bit EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ Ifx_Strict_32Bit EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ Ifx_Strict_32Bit EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ Ifx_Strict_32Bit EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ Ifx_Strict_32Bit EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ Ifx_Strict_32Bit EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ Ifx_Strict_32Bit EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ Ifx_Strict_32Bit EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ Ifx_Strict_32Bit EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ Ifx_Strict_32Bit EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ Ifx_Strict_32Bit EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ Ifx_Strict_32Bit EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_LMU_ACCEN0_Bits;
+
+/** \brief LMU Access Enable Register 1 */
+typedef struct _Ifx_LMU_ACCEN1_Bits
+{
+ Ifx_Strict_32Bit reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_LMU_ACCEN1_Bits;
+
+/** \brief LMU Buffer Control Register */
+typedef struct _Ifx_LMU_BUFCON_Bits
+{
+ Ifx_Strict_32Bit TAG1:6; /**< \brief [5:0] Master Tag ID 1 (rw) */
+ Ifx_Strict_32Bit reserved_6:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit TAG2:6; /**< \brief [13:8] Master Tag ID 2 (rw) */
+ Ifx_Strict_32Bit reserved_14:8; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit EREN:1; /**< \brief [22:22] EMEM Read Buffer Enable (rw) */
+ Ifx_Strict_32Bit EPEN:1; /**< \brief [23:23] EMEM Prefetch Enable (rw) */
+ Ifx_Strict_32Bit reserved_24:6; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit EN1:1; /**< \brief [30:30] TAG1 Field Enable (rw) */
+ Ifx_Strict_32Bit EN2:1; /**< \brief [31:31] TAG2 Field Enable (rw) */
+} Ifx_LMU_BUFCON_Bits;
+
+/** \brief LMU Clock Control Register */
+typedef struct _Ifx_LMU_CLC_Bits
+{
+ Ifx_Strict_32Bit DISR:1; /**< \brief [0:0] Module LMU Disable Request Bit (rw) */
+ Ifx_Strict_32Bit DISS:1; /**< \brief [1:1] Module LMU Disable Status Bit (rh) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_LMU_CLC_Bits;
+
+/** \brief LMU Memory Control Register */
+typedef struct _Ifx_LMU_MEMCON_Bits
+{
+ Ifx_Strict_32Bit OLDAEN:1; /**< \brief [0:0] Online Data Acquisition Enabled (rw) */
+ Ifx_Strict_32Bit POLDAEN:1; /**< \brief [1:1] Protection Bit for OLDAEN (w) */
+ Ifx_Strict_32Bit reserved_2:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit ERERR:1; /**< \brief [3:3] EMEM Read Error (rwh) */
+ Ifx_Strict_32Bit reserved_4:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit EWERR:1; /**< \brief [5:5] EMEM Write Error (rwh) */
+ Ifx_Strict_32Bit DATAERR:1; /**< \brief [6:6] SRI Data Phase ECC Error (rwh) */
+ Ifx_Strict_32Bit ADDERR:1; /**< \brief [7:7] SRI Address Phase ECC Error (rwh) */
+ Ifx_Strict_32Bit reserved_8:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit FFTPFT:1; /**< \brief [10:10] FFT Accelerator Prefetch Disable (rw) */
+ Ifx_Strict_32Bit reserved_11:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit WSTATES:4; /**< \brief [15:12] EMEM Wait States (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_LMU_MEMCON_Bits;
+
+/** \brief LMU Module ID Register */
+typedef struct _Ifx_LMU_MODID_Bits
+{
+ Ifx_Strict_32Bit ID_VALUE:32; /**< \brief [31:0] Module Identification Value (r) */
+} Ifx_LMU_MODID_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Lmu_union
+ * \{ */
+
+/** \brief LMU Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_LMU_ACCEN0_Bits B; /**< \brief Bitfield access */
+} Ifx_LMU_ACCEN0;
+
+/** \brief LMU Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_LMU_ACCEN1_Bits B; /**< \brief Bitfield access */
+} Ifx_LMU_ACCEN1;
+
+/** \brief LMU Buffer Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_LMU_BUFCON_Bits B; /**< \brief Bitfield access */
+} Ifx_LMU_BUFCON;
+
+/** \brief LMU Clock Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_LMU_CLC_Bits B; /**< \brief Bitfield access */
+} Ifx_LMU_CLC;
+
+/** \brief LMU Memory Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_LMU_MEMCON_Bits B; /**< \brief Bitfield access */
+} Ifx_LMU_MEMCON;
+
+/** \brief LMU Module ID Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_LMU_MODID_Bits B; /**< \brief Bitfield access */
+} Ifx_LMU_MODID;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Lmu_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief LMU object */
+typedef volatile struct _Ifx_LMU
+{
+ Ifx_LMU_CLC CLC; /**< \brief 0, LMU Clock Control Register */
+ unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
+ Ifx_LMU_MODID MODID; /**< \brief 8, LMU Module ID Register */
+ unsigned char reserved_C[4]; /**< \brief C, \internal Reserved */
+ Ifx_LMU_ACCEN0 ACCEN0; /**< \brief 10, LMU Access Enable Register 0 */
+ Ifx_LMU_ACCEN1 ACCEN1; /**< \brief 14, LMU Access Enable Register 1 */
+ unsigned char reserved_18[8]; /**< \brief 18, \internal Reserved */
+ Ifx_LMU_MEMCON MEMCON; /**< \brief 20, LMU Memory Control Register */
+ unsigned char reserved_24[12]; /**< \brief 24, \internal Reserved */
+ Ifx_LMU_BUFCON BUFCON[3]; /**< \brief 30, LMU Buffer Control Register */
+ unsigned char reserved_3C[196]; /**< \brief 3C, \internal Reserved */
+} Ifx_LMU;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXLMU_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxMc_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxMc_bf.h
new file mode 100644
index 0000000..da0b27f
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxMc_bf.h
@@ -0,0 +1,450 @@
+/**
+ * \file IfxMc_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Mc_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Mc
+ *
+ */
+#ifndef IFXMC_BF_H
+#define IFXMC_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_MC_CONFIG0_Bits.ACCSTYPE */
+#define IFX_MC_CONFIG0_ACCSTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_MC_CONFIG0_Bits.ACCSTYPE */
+#define IFX_MC_CONFIG0_ACCSTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_MC_CONFIG0_Bits.ACCSTYPE */
+#define IFX_MC_CONFIG0_ACCSTYPE_OFF (0u)
+
+/** \brief Length for Ifx_MC_CONFIG0_Bits.NUMACCS */
+#define IFX_MC_CONFIG0_NUMACCS_LEN (4u)
+
+/** \brief Mask for Ifx_MC_CONFIG0_Bits.NUMACCS */
+#define IFX_MC_CONFIG0_NUMACCS_MSK (0xfu)
+
+/** \brief Offset for Ifx_MC_CONFIG0_Bits.NUMACCS */
+#define IFX_MC_CONFIG0_NUMACCS_OFF (12u)
+
+/** \brief Length for Ifx_MC_CONFIG1_Bits.ACCSPAT */
+#define IFX_MC_CONFIG1_ACCSPAT_LEN (8u)
+
+/** \brief Mask for Ifx_MC_CONFIG1_Bits.ACCSPAT */
+#define IFX_MC_CONFIG1_ACCSPAT_MSK (0xffu)
+
+/** \brief Offset for Ifx_MC_CONFIG1_Bits.ACCSPAT */
+#define IFX_MC_CONFIG1_ACCSPAT_OFF (0u)
+
+/** \brief Length for Ifx_MC_CONFIG1_Bits.AG_MOD */
+#define IFX_MC_CONFIG1_AG_MOD_LEN (4u)
+
+/** \brief Mask for Ifx_MC_CONFIG1_Bits.AG_MOD */
+#define IFX_MC_CONFIG1_AG_MOD_MSK (0xfu)
+
+/** \brief Offset for Ifx_MC_CONFIG1_Bits.AG_MOD */
+#define IFX_MC_CONFIG1_AG_MOD_OFF (12u)
+
+/** \brief Length for Ifx_MC_CONFIG1_Bits.SELFASTB */
+#define IFX_MC_CONFIG1_SELFASTB_LEN (4u)
+
+/** \brief Mask for Ifx_MC_CONFIG1_Bits.SELFASTB */
+#define IFX_MC_CONFIG1_SELFASTB_MSK (0xfu)
+
+/** \brief Offset for Ifx_MC_CONFIG1_Bits.SELFASTB */
+#define IFX_MC_CONFIG1_SELFASTB_OFF (8u)
+
+/** \brief Length for Ifx_MC_ECCD_Bits.AENE */
+#define IFX_MC_ECCD_AENE_LEN (1u)
+
+/** \brief Mask for Ifx_MC_ECCD_Bits.AENE */
+#define IFX_MC_ECCD_AENE_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_ECCD_Bits.AENE */
+#define IFX_MC_ECCD_AENE_OFF (13u)
+
+/** \brief Length for Ifx_MC_ECCD_Bits.AERR */
+#define IFX_MC_ECCD_AERR_LEN (1u)
+
+/** \brief Mask for Ifx_MC_ECCD_Bits.AERR */
+#define IFX_MC_ECCD_AERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_ECCD_Bits.AERR */
+#define IFX_MC_ECCD_AERR_OFF (3u)
+
+/** \brief Length for Ifx_MC_ECCD_Bits.CENE */
+#define IFX_MC_ECCD_CENE_LEN (1u)
+
+/** \brief Mask for Ifx_MC_ECCD_Bits.CENE */
+#define IFX_MC_ECCD_CENE_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_ECCD_Bits.CENE */
+#define IFX_MC_ECCD_CENE_OFF (11u)
+
+/** \brief Length for Ifx_MC_ECCD_Bits.CERR */
+#define IFX_MC_ECCD_CERR_LEN (1u)
+
+/** \brief Mask for Ifx_MC_ECCD_Bits.CERR */
+#define IFX_MC_ECCD_CERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_ECCD_Bits.CERR */
+#define IFX_MC_ECCD_CERR_OFF (1u)
+
+/** \brief Length for Ifx_MC_ECCD_Bits.ECE */
+#define IFX_MC_ECCD_ECE_LEN (1u)
+
+/** \brief Mask for Ifx_MC_ECCD_Bits.ECE */
+#define IFX_MC_ECCD_ECE_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_ECCD_Bits.ECE */
+#define IFX_MC_ECCD_ECE_OFF (14u)
+
+/** \brief Length for Ifx_MC_ECCD_Bits.EOV */
+#define IFX_MC_ECCD_EOV_LEN (1u)
+
+/** \brief Mask for Ifx_MC_ECCD_Bits.EOV */
+#define IFX_MC_ECCD_EOV_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_ECCD_Bits.EOV */
+#define IFX_MC_ECCD_EOV_OFF (15u)
+
+/** \brief Length for Ifx_MC_ECCD_Bits.RARVAL */
+#define IFX_MC_ECCD_RARVAL_LEN (1u)
+
+/** \brief Mask for Ifx_MC_ECCD_Bits.RARVAL */
+#define IFX_MC_ECCD_RARVAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_ECCD_Bits.RARVAL */
+#define IFX_MC_ECCD_RARVAL_OFF (10u)
+
+/** \brief Length for Ifx_MC_ECCD_Bits.SERR */
+#define IFX_MC_ECCD_SERR_LEN (1u)
+
+/** \brief Mask for Ifx_MC_ECCD_Bits.SERR */
+#define IFX_MC_ECCD_SERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_ECCD_Bits.SERR */
+#define IFX_MC_ECCD_SERR_OFF (0u)
+
+/** \brief Length for Ifx_MC_ECCD_Bits.TRC */
+#define IFX_MC_ECCD_TRC_LEN (1u)
+
+/** \brief Mask for Ifx_MC_ECCD_Bits.TRC */
+#define IFX_MC_ECCD_TRC_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_ECCD_Bits.TRC */
+#define IFX_MC_ECCD_TRC_OFF (4u)
+
+/** \brief Length for Ifx_MC_ECCD_Bits.UENE */
+#define IFX_MC_ECCD_UENE_LEN (1u)
+
+/** \brief Mask for Ifx_MC_ECCD_Bits.UENE */
+#define IFX_MC_ECCD_UENE_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_ECCD_Bits.UENE */
+#define IFX_MC_ECCD_UENE_OFF (12u)
+
+/** \brief Length for Ifx_MC_ECCD_Bits.UERR */
+#define IFX_MC_ECCD_UERR_LEN (1u)
+
+/** \brief Mask for Ifx_MC_ECCD_Bits.UERR */
+#define IFX_MC_ECCD_UERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_ECCD_Bits.UERR */
+#define IFX_MC_ECCD_UERR_OFF (2u)
+
+/** \brief Length for Ifx_MC_ECCD_Bits.VAL */
+#define IFX_MC_ECCD_VAL_LEN (5u)
+
+/** \brief Mask for Ifx_MC_ECCD_Bits.VAL */
+#define IFX_MC_ECCD_VAL_MSK (0x1fu)
+
+/** \brief Offset for Ifx_MC_ECCD_Bits.VAL */
+#define IFX_MC_ECCD_VAL_OFF (5u)
+
+/** \brief Length for Ifx_MC_ECCS_Bits.AENE */
+#define IFX_MC_ECCS_AENE_LEN (1u)
+
+/** \brief Mask for Ifx_MC_ECCS_Bits.AENE */
+#define IFX_MC_ECCS_AENE_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_ECCS_Bits.AENE */
+#define IFX_MC_ECCS_AENE_OFF (2u)
+
+/** \brief Length for Ifx_MC_ECCS_Bits.BFLE */
+#define IFX_MC_ECCS_BFLE_LEN (1u)
+
+/** \brief Mask for Ifx_MC_ECCS_Bits.BFLE */
+#define IFX_MC_ECCS_BFLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_ECCS_Bits.BFLE */
+#define IFX_MC_ECCS_BFLE_OFF (5u)
+
+/** \brief Length for Ifx_MC_ECCS_Bits.CENE */
+#define IFX_MC_ECCS_CENE_LEN (1u)
+
+/** \brief Mask for Ifx_MC_ECCS_Bits.CENE */
+#define IFX_MC_ECCS_CENE_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_ECCS_Bits.CENE */
+#define IFX_MC_ECCS_CENE_OFF (0u)
+
+/** \brief Length for Ifx_MC_ECCS_Bits.ECCMAP */
+#define IFX_MC_ECCS_ECCMAP_LEN (2u)
+
+/** \brief Mask for Ifx_MC_ECCS_Bits.ECCMAP */
+#define IFX_MC_ECCS_ECCMAP_MSK (0x3u)
+
+/** \brief Offset for Ifx_MC_ECCS_Bits.ECCMAP */
+#define IFX_MC_ECCS_ECCMAP_OFF (8u)
+
+/** \brief Length for Ifx_MC_ECCS_Bits.ECE */
+#define IFX_MC_ECCS_ECE_LEN (1u)
+
+/** \brief Mask for Ifx_MC_ECCS_Bits.ECE */
+#define IFX_MC_ECCS_ECE_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_ECCS_Bits.ECE */
+#define IFX_MC_ECCS_ECE_OFF (3u)
+
+/** \brief Length for Ifx_MC_ECCS_Bits.SFLE */
+#define IFX_MC_ECCS_SFLE_LEN (2u)
+
+/** \brief Mask for Ifx_MC_ECCS_Bits.SFLE */
+#define IFX_MC_ECCS_SFLE_MSK (0x3u)
+
+/** \brief Offset for Ifx_MC_ECCS_Bits.SFLE */
+#define IFX_MC_ECCS_SFLE_OFF (6u)
+
+/** \brief Length for Ifx_MC_ECCS_Bits.TC_WAY_SEL */
+#define IFX_MC_ECCS_TC_WAY_SEL_LEN (2u)
+
+/** \brief Mask for Ifx_MC_ECCS_Bits.TC_WAY_SEL */
+#define IFX_MC_ECCS_TC_WAY_SEL_MSK (0x3u)
+
+/** \brief Offset for Ifx_MC_ECCS_Bits.TC_WAY_SEL */
+#define IFX_MC_ECCS_TC_WAY_SEL_OFF (10u)
+
+/** \brief Length for Ifx_MC_ECCS_Bits.TRE */
+#define IFX_MC_ECCS_TRE_LEN (1u)
+
+/** \brief Mask for Ifx_MC_ECCS_Bits.TRE */
+#define IFX_MC_ECCS_TRE_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_ECCS_Bits.TRE */
+#define IFX_MC_ECCS_TRE_OFF (4u)
+
+/** \brief Length for Ifx_MC_ECCS_Bits.UENE */
+#define IFX_MC_ECCS_UENE_LEN (1u)
+
+/** \brief Mask for Ifx_MC_ECCS_Bits.UENE */
+#define IFX_MC_ECCS_UENE_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_ECCS_Bits.UENE */
+#define IFX_MC_ECCS_UENE_OFF (1u)
+
+/** \brief Length for Ifx_MC_ETRR_Bits.ADDR */
+#define IFX_MC_ETRR_ADDR_LEN (13u)
+
+/** \brief Mask for Ifx_MC_ETRR_Bits.ADDR */
+#define IFX_MC_ETRR_ADDR_MSK (0x1fffu)
+
+/** \brief Offset for Ifx_MC_ETRR_Bits.ADDR */
+#define IFX_MC_ETRR_ADDR_OFF (0u)
+
+/** \brief Length for Ifx_MC_ETRR_Bits.MBI */
+#define IFX_MC_ETRR_MBI_LEN (3u)
+
+/** \brief Mask for Ifx_MC_ETRR_Bits.MBI */
+#define IFX_MC_ETRR_MBI_MSK (0x7u)
+
+/** \brief Offset for Ifx_MC_ETRR_Bits.MBI */
+#define IFX_MC_ETRR_MBI_OFF (13u)
+
+/** \brief Length for Ifx_MC_MCONTROL_Bits.BITTOG */
+#define IFX_MC_MCONTROL_BITTOG_LEN (1u)
+
+/** \brief Mask for Ifx_MC_MCONTROL_Bits.BITTOG */
+#define IFX_MC_MCONTROL_BITTOG_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_MCONTROL_Bits.BITTOG */
+#define IFX_MC_MCONTROL_BITTOG_OFF (7u)
+
+/** \brief Length for Ifx_MC_MCONTROL_Bits.DINIT */
+#define IFX_MC_MCONTROL_DINIT_LEN (1u)
+
+/** \brief Mask for Ifx_MC_MCONTROL_Bits.DINIT */
+#define IFX_MC_MCONTROL_DINIT_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_MCONTROL_Bits.DINIT */
+#define IFX_MC_MCONTROL_DINIT_OFF (4u)
+
+/** \brief Length for Ifx_MC_MCONTROL_Bits.DIR */
+#define IFX_MC_MCONTROL_DIR_LEN (1u)
+
+/** \brief Mask for Ifx_MC_MCONTROL_Bits.DIR */
+#define IFX_MC_MCONTROL_DIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_MCONTROL_Bits.DIR */
+#define IFX_MC_MCONTROL_DIR_OFF (3u)
+
+/** \brief Length for Ifx_MC_MCONTROL_Bits.ESTF */
+#define IFX_MC_MCONTROL_ESTF_LEN (1u)
+
+/** \brief Mask for Ifx_MC_MCONTROL_Bits.ESTF */
+#define IFX_MC_MCONTROL_ESTF_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_MCONTROL_Bits.ESTF */
+#define IFX_MC_MCONTROL_ESTF_OFF (2u)
+
+/** \brief Length for Ifx_MC_MCONTROL_Bits.FAILDMP */
+#define IFX_MC_MCONTROL_FAILDMP_LEN (1u)
+
+/** \brief Mask for Ifx_MC_MCONTROL_Bits.FAILDMP */
+#define IFX_MC_MCONTROL_FAILDMP_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_MCONTROL_Bits.FAILDMP */
+#define IFX_MC_MCONTROL_FAILDMP_OFF (9u)
+
+/** \brief Length for Ifx_MC_MCONTROL_Bits.GP_BASE */
+#define IFX_MC_MCONTROL_GP_BASE_LEN (1u)
+
+/** \brief Mask for Ifx_MC_MCONTROL_Bits.GP_BASE */
+#define IFX_MC_MCONTROL_GP_BASE_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_MCONTROL_Bits.GP_BASE */
+#define IFX_MC_MCONTROL_GP_BASE_OFF (8u)
+
+/** \brief Length for Ifx_MC_MCONTROL_Bits.RCADR */
+#define IFX_MC_MCONTROL_RCADR_LEN (1u)
+
+/** \brief Mask for Ifx_MC_MCONTROL_Bits.RCADR */
+#define IFX_MC_MCONTROL_RCADR_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_MCONTROL_Bits.RCADR */
+#define IFX_MC_MCONTROL_RCADR_OFF (5u)
+
+/** \brief Length for Ifx_MC_MCONTROL_Bits.RESUME */
+#define IFX_MC_MCONTROL_RESUME_LEN (1u)
+
+/** \brief Mask for Ifx_MC_MCONTROL_Bits.RESUME */
+#define IFX_MC_MCONTROL_RESUME_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_MCONTROL_Bits.RESUME */
+#define IFX_MC_MCONTROL_RESUME_OFF (1u)
+
+/** \brief Length for Ifx_MC_MCONTROL_Bits.ROWTOG */
+#define IFX_MC_MCONTROL_ROWTOG_LEN (1u)
+
+/** \brief Mask for Ifx_MC_MCONTROL_Bits.ROWTOG */
+#define IFX_MC_MCONTROL_ROWTOG_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_MCONTROL_Bits.ROWTOG */
+#define IFX_MC_MCONTROL_ROWTOG_OFF (6u)
+
+/** \brief Length for Ifx_MC_MCONTROL_Bits.START */
+#define IFX_MC_MCONTROL_START_LEN (1u)
+
+/** \brief Mask for Ifx_MC_MCONTROL_Bits.START */
+#define IFX_MC_MCONTROL_START_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_MCONTROL_Bits.START */
+#define IFX_MC_MCONTROL_START_OFF (0u)
+
+/** \brief Length for Ifx_MC_MSTATUS_Bits.DONE */
+#define IFX_MC_MSTATUS_DONE_LEN (1u)
+
+/** \brief Mask for Ifx_MC_MSTATUS_Bits.DONE */
+#define IFX_MC_MSTATUS_DONE_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_MSTATUS_Bits.DONE */
+#define IFX_MC_MSTATUS_DONE_OFF (0u)
+
+/** \brief Length for Ifx_MC_MSTATUS_Bits.FAIL */
+#define IFX_MC_MSTATUS_FAIL_LEN (1u)
+
+/** \brief Mask for Ifx_MC_MSTATUS_Bits.FAIL */
+#define IFX_MC_MSTATUS_FAIL_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_MSTATUS_Bits.FAIL */
+#define IFX_MC_MSTATUS_FAIL_OFF (1u)
+
+/** \brief Length for Ifx_MC_MSTATUS_Bits.FDA */
+#define IFX_MC_MSTATUS_FDA_LEN (1u)
+
+/** \brief Mask for Ifx_MC_MSTATUS_Bits.FDA */
+#define IFX_MC_MSTATUS_FDA_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_MSTATUS_Bits.FDA */
+#define IFX_MC_MSTATUS_FDA_OFF (2u)
+
+/** \brief Length for Ifx_MC_MSTATUS_Bits.SFAIL */
+#define IFX_MC_MSTATUS_SFAIL_LEN (1u)
+
+/** \brief Mask for Ifx_MC_MSTATUS_Bits.SFAIL */
+#define IFX_MC_MSTATUS_SFAIL_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_MSTATUS_Bits.SFAIL */
+#define IFX_MC_MSTATUS_SFAIL_OFF (3u)
+
+/** \brief Length for Ifx_MC_RANGE_Bits.ADDR */
+#define IFX_MC_RANGE_ADDR_LEN (15u)
+
+/** \brief Mask for Ifx_MC_RANGE_Bits.ADDR */
+#define IFX_MC_RANGE_ADDR_MSK (0x7fffu)
+
+/** \brief Offset for Ifx_MC_RANGE_Bits.ADDR */
+#define IFX_MC_RANGE_ADDR_OFF (0u)
+
+/** \brief Length for Ifx_MC_RANGE_Bits.RAEN */
+#define IFX_MC_RANGE_RAEN_LEN (1u)
+
+/** \brief Mask for Ifx_MC_RANGE_Bits.RAEN */
+#define IFX_MC_RANGE_RAEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MC_RANGE_Bits.RAEN */
+#define IFX_MC_RANGE_RAEN_OFF (15u)
+
+/** \brief Length for Ifx_MC_RDBFL_Bits.WDATA */
+#define IFX_MC_RDBFL_WDATA_LEN (16u)
+
+/** \brief Mask for Ifx_MC_RDBFL_Bits.WDATA */
+#define IFX_MC_RDBFL_WDATA_MSK (0xffffu)
+
+/** \brief Offset for Ifx_MC_RDBFL_Bits.WDATA */
+#define IFX_MC_RDBFL_WDATA_OFF (0u)
+
+/** \brief Length for Ifx_MC_REVID_Bits.REV_ID */
+#define IFX_MC_REVID_REV_ID_LEN (16u)
+
+/** \brief Mask for Ifx_MC_REVID_Bits.REV_ID */
+#define IFX_MC_REVID_REV_ID_MSK (0xffffu)
+
+/** \brief Offset for Ifx_MC_REVID_Bits.REV_ID */
+#define IFX_MC_REVID_REV_ID_OFF (0u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXMC_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxMc_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxMc_reg.h
new file mode 100644
index 0000000..17fe018
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxMc_reg.h
@@ -0,0 +1,15000 @@
+/**
+ * \file IfxMc_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Mc_Cfg Mc address
+ * \ingroup IfxLld_Mc
+ *
+ * \defgroup IfxLld_Mc_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc0 2-MC0
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc1 2-MC1
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc2 2-MC2
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc3 2-MC3
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc4 2-MC4
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc5 2-MC5
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc6 2-MC6
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc7 2-MC7
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc8 2-MC8
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc9 2-MC9
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc10 2-MC10
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc11 2-MC11
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc12 2-MC12
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc13 2-MC13
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc14 2-MC14
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc15 2-MC15
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc16 2-MC16
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc17 2-MC17
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc18 2-MC18
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc19 2-MC19
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc20 2-MC20
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc21 2-MC21
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc22 2-MC22
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc23 2-MC23
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc24 2-MC24
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc25 2-MC25
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc26 2-MC26
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc27 2-MC27
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc28 2-MC28
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc29 2-MC29
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc30 2-MC30
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc31 2-MC31
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc32 2-MC32
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc33 2-MC33
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc34 2-MC34
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc35 2-MC35
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc36 2-MC36
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc37 2-MC37
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc38 2-MC38
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc39 2-MC39
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc40 2-MC40
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc41 2-MC41
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc42 2-MC42
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc43 2-MC43
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc44 2-MC44
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc45 2-MC45
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc46 2-MC46
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc47 2-MC47
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc48 2-MC48
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc49 2-MC49
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc50 2-MC50
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc51 2-MC51
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc52 2-MC52
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc53 2-MC53
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc54 2-MC54
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc55 2-MC55
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc56 2-MC56
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc57 2-MC57
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc58 2-MC58
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc59 2-MC59
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc60 2-MC60
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc61 2-MC61
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc62 2-MC62
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc63 2-MC63
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc64 2-MC64
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc65 2-MC65
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc66 2-MC66
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc67 2-MC67
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc68 2-MC68
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc69 2-MC69
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc70 2-MC70
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc71 2-MC71
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc72 2-MC72
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc73 2-MC73
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc74 2-MC74
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc75 2-MC75
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc76 2-MC76
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc77 2-MC77
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc78 2-MC78
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc79 2-MC79
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc80 2-MC80
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc81 2-MC81
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc82 2-MC82
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc83 2-MC83
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc84 2-MC84
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc85 2-MC85
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc86 2-MC86
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ * \defgroup IfxLld_Mc_Cfg_Mc87 2-MC87
+ * \ingroup IfxLld_Mc_Cfg
+ *
+ */
+#ifndef IFXMC_REG_H
+#define IFXMC_REG_H 1
+/******************************************************************************/
+#include "IfxMc_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_BaseAddress
+ * \{ */
+
+/** \brief MC object */
+#define MODULE_MC0 /*lint --e(923)*/ (*(Ifx_MC*)0xF0061000u)
+
+/** \brief MC object */
+#define MODULE_MC1 /*lint --e(923)*/ (*(Ifx_MC*)0xF0061100u)
+
+/** \brief MC object */
+#define MODULE_MC10 /*lint --e(923)*/ (*(Ifx_MC*)0xF0061A00u)
+
+/** \brief MC object */
+#define MODULE_MC11 /*lint --e(923)*/ (*(Ifx_MC*)0xF0061B00u)
+
+/** \brief MC object */
+#define MODULE_MC12 /*lint --e(923)*/ (*(Ifx_MC*)0xF0061C00u)
+
+/** \brief MC object */
+#define MODULE_MC13 /*lint --e(923)*/ (*(Ifx_MC*)0xF0061D00u)
+
+/** \brief MC object */
+#define MODULE_MC14 /*lint --e(923)*/ (*(Ifx_MC*)0xF0061E00u)
+
+/** \brief MC object */
+#define MODULE_MC15 /*lint --e(923)*/ (*(Ifx_MC*)0xF0061F00u)
+
+/** \brief MC object */
+#define MODULE_MC16 /*lint --e(923)*/ (*(Ifx_MC*)0xF0062000u)
+
+/** \brief MC object */
+#define MODULE_MC17 /*lint --e(923)*/ (*(Ifx_MC*)0xF0062100u)
+
+/** \brief MC object */
+#define MODULE_MC18 /*lint --e(923)*/ (*(Ifx_MC*)0xF0062200u)
+
+/** \brief MC object */
+#define MODULE_MC19 /*lint --e(923)*/ (*(Ifx_MC*)0xF0062300u)
+
+/** \brief MC object */
+#define MODULE_MC2 /*lint --e(923)*/ (*(Ifx_MC*)0xF0061200u)
+
+/** \brief MC object */
+#define MODULE_MC20 /*lint --e(923)*/ (*(Ifx_MC*)0xF0062400u)
+
+/** \brief MC object */
+#define MODULE_MC21 /*lint --e(923)*/ (*(Ifx_MC*)0xF0062500u)
+
+/** \brief MC object */
+#define MODULE_MC22 /*lint --e(923)*/ (*(Ifx_MC*)0xF0062600u)
+
+/** \brief MC object */
+#define MODULE_MC23 /*lint --e(923)*/ (*(Ifx_MC*)0xF0062700u)
+
+/** \brief MC object */
+#define MODULE_MC24 /*lint --e(923)*/ (*(Ifx_MC*)0xF0062800u)
+
+/** \brief MC object */
+#define MODULE_MC25 /*lint --e(923)*/ (*(Ifx_MC*)0xF0062900u)
+
+/** \brief MC object */
+#define MODULE_MC26 /*lint --e(923)*/ (*(Ifx_MC*)0xF0062A00u)
+
+/** \brief MC object */
+#define MODULE_MC27 /*lint --e(923)*/ (*(Ifx_MC*)0xF0062B00u)
+
+/** \brief MC object */
+#define MODULE_MC28 /*lint --e(923)*/ (*(Ifx_MC*)0xF0062C00u)
+
+/** \brief MC object */
+#define MODULE_MC29 /*lint --e(923)*/ (*(Ifx_MC*)0xF0062D00u)
+
+/** \brief MC object */
+#define MODULE_MC3 /*lint --e(923)*/ (*(Ifx_MC*)0xF0061300u)
+
+/** \brief MC object */
+#define MODULE_MC30 /*lint --e(923)*/ (*(Ifx_MC*)0xF0062E00u)
+
+/** \brief MC object */
+#define MODULE_MC31 /*lint --e(923)*/ (*(Ifx_MC*)0xF0062F00u)
+
+/** \brief MC object */
+#define MODULE_MC32 /*lint --e(923)*/ (*(Ifx_MC*)0xF0063000u)
+
+/** \brief MC object */
+#define MODULE_MC33 /*lint --e(923)*/ (*(Ifx_MC*)0xF0063100u)
+
+/** \brief MC object */
+#define MODULE_MC34 /*lint --e(923)*/ (*(Ifx_MC*)0xF0063200u)
+
+/** \brief MC object */
+#define MODULE_MC35 /*lint --e(923)*/ (*(Ifx_MC*)0xF0063300u)
+
+/** \brief MC object */
+#define MODULE_MC36 /*lint --e(923)*/ (*(Ifx_MC*)0xF0063400u)
+
+/** \brief MC object */
+#define MODULE_MC37 /*lint --e(923)*/ (*(Ifx_MC*)0xF0063500u)
+
+/** \brief MC object */
+#define MODULE_MC38 /*lint --e(923)*/ (*(Ifx_MC*)0xF0063600u)
+
+/** \brief MC object */
+#define MODULE_MC39 /*lint --e(923)*/ (*(Ifx_MC*)0xF0063700u)
+
+/** \brief MC object */
+#define MODULE_MC4 /*lint --e(923)*/ (*(Ifx_MC*)0xF0061400u)
+
+/** \brief MC object */
+#define MODULE_MC40 /*lint --e(923)*/ (*(Ifx_MC*)0xF0063800u)
+
+/** \brief MC object */
+#define MODULE_MC41 /*lint --e(923)*/ (*(Ifx_MC*)0xF0063900u)
+
+/** \brief MC object */
+#define MODULE_MC42 /*lint --e(923)*/ (*(Ifx_MC*)0xF0063A00u)
+
+/** \brief MC object */
+#define MODULE_MC43 /*lint --e(923)*/ (*(Ifx_MC*)0xF0063B00u)
+
+/** \brief MC object */
+#define MODULE_MC44 /*lint --e(923)*/ (*(Ifx_MC*)0xF0063C00u)
+
+/** \brief MC object */
+#define MODULE_MC45 /*lint --e(923)*/ (*(Ifx_MC*)0xF0063D00u)
+
+/** \brief MC object */
+#define MODULE_MC46 /*lint --e(923)*/ (*(Ifx_MC*)0xF0063E00u)
+
+/** \brief MC object */
+#define MODULE_MC47 /*lint --e(923)*/ (*(Ifx_MC*)0xF0063F00u)
+
+/** \brief MC object */
+#define MODULE_MC48 /*lint --e(923)*/ (*(Ifx_MC*)0xF0064000u)
+
+/** \brief MC object */
+#define MODULE_MC49 /*lint --e(923)*/ (*(Ifx_MC*)0xF0064100u)
+
+/** \brief MC object */
+#define MODULE_MC5 /*lint --e(923)*/ (*(Ifx_MC*)0xF0061500u)
+
+/** \brief MC object */
+#define MODULE_MC50 /*lint --e(923)*/ (*(Ifx_MC*)0xF0064200u)
+
+/** \brief MC object */
+#define MODULE_MC51 /*lint --e(923)*/ (*(Ifx_MC*)0xF0064300u)
+
+/** \brief MC object */
+#define MODULE_MC52 /*lint --e(923)*/ (*(Ifx_MC*)0xF0064400u)
+
+/** \brief MC object */
+#define MODULE_MC53 /*lint --e(923)*/ (*(Ifx_MC*)0xF0064500u)
+
+/** \brief MC object */
+#define MODULE_MC54 /*lint --e(923)*/ (*(Ifx_MC*)0xF0064600u)
+
+/** \brief MC object */
+#define MODULE_MC55 /*lint --e(923)*/ (*(Ifx_MC*)0xF0064700u)
+
+/** \brief MC object */
+#define MODULE_MC56 /*lint --e(923)*/ (*(Ifx_MC*)0xF0064800u)
+
+/** \brief MC object */
+#define MODULE_MC57 /*lint --e(923)*/ (*(Ifx_MC*)0xF0064900u)
+
+/** \brief MC object */
+#define MODULE_MC58 /*lint --e(923)*/ (*(Ifx_MC*)0xF0064A00u)
+
+/** \brief MC object */
+#define MODULE_MC59 /*lint --e(923)*/ (*(Ifx_MC*)0xF0064B00u)
+
+/** \brief MC object */
+#define MODULE_MC6 /*lint --e(923)*/ (*(Ifx_MC*)0xF0061600u)
+
+/** \brief MC object */
+#define MODULE_MC60 /*lint --e(923)*/ (*(Ifx_MC*)0xF0064C00u)
+
+/** \brief MC object */
+#define MODULE_MC61 /*lint --e(923)*/ (*(Ifx_MC*)0xF0064D00u)
+
+/** \brief MC object */
+#define MODULE_MC62 /*lint --e(923)*/ (*(Ifx_MC*)0xF0064E00u)
+
+/** \brief MC object */
+#define MODULE_MC63 /*lint --e(923)*/ (*(Ifx_MC*)0xF0064F00u)
+
+/** \brief MC object */
+#define MODULE_MC64 /*lint --e(923)*/ (*(Ifx_MC*)0xF0065000u)
+
+/** \brief MC object */
+#define MODULE_MC65 /*lint --e(923)*/ (*(Ifx_MC*)0xF0065100u)
+
+/** \brief MC object */
+#define MODULE_MC66 /*lint --e(923)*/ (*(Ifx_MC*)0xF0065200u)
+
+/** \brief MC object */
+#define MODULE_MC67 /*lint --e(923)*/ (*(Ifx_MC*)0xF0065300u)
+
+/** \brief MC object */
+#define MODULE_MC68 /*lint --e(923)*/ (*(Ifx_MC*)0xF0065400u)
+
+/** \brief MC object */
+#define MODULE_MC69 /*lint --e(923)*/ (*(Ifx_MC*)0xF0065500u)
+
+/** \brief MC object */
+#define MODULE_MC7 /*lint --e(923)*/ (*(Ifx_MC*)0xF0061700u)
+
+/** \brief MC object */
+#define MODULE_MC70 /*lint --e(923)*/ (*(Ifx_MC*)0xF0065600u)
+
+/** \brief MC object */
+#define MODULE_MC71 /*lint --e(923)*/ (*(Ifx_MC*)0xF0065700u)
+
+/** \brief MC object */
+#define MODULE_MC72 /*lint --e(923)*/ (*(Ifx_MC*)0xF0065800u)
+
+/** \brief MC object */
+#define MODULE_MC73 /*lint --e(923)*/ (*(Ifx_MC*)0xF0065900u)
+
+/** \brief MC object */
+#define MODULE_MC74 /*lint --e(923)*/ (*(Ifx_MC*)0xF0065A00u)
+
+/** \brief MC object */
+#define MODULE_MC75 /*lint --e(923)*/ (*(Ifx_MC*)0xF0065B00u)
+
+/** \brief MC object */
+#define MODULE_MC76 /*lint --e(923)*/ (*(Ifx_MC*)0xF0065C00u)
+
+/** \brief MC object */
+#define MODULE_MC77 /*lint --e(923)*/ (*(Ifx_MC*)0xF0065D00u)
+
+/** \brief MC object */
+#define MODULE_MC78 /*lint --e(923)*/ (*(Ifx_MC*)0xF0065E00u)
+
+/** \brief MC object */
+#define MODULE_MC79 /*lint --e(923)*/ (*(Ifx_MC*)0xF0065F00u)
+
+/** \brief MC object */
+#define MODULE_MC8 /*lint --e(923)*/ (*(Ifx_MC*)0xF0061800u)
+
+/** \brief MC object */
+#define MODULE_MC80 /*lint --e(923)*/ (*(Ifx_MC*)0xF0066000u)
+
+/** \brief MC object */
+#define MODULE_MC81 /*lint --e(923)*/ (*(Ifx_MC*)0xF0066100u)
+
+/** \brief MC object */
+#define MODULE_MC82 /*lint --e(923)*/ (*(Ifx_MC*)0xF0066200u)
+
+/** \brief MC object */
+#define MODULE_MC83 /*lint --e(923)*/ (*(Ifx_MC*)0xF0066300u)
+
+/** \brief MC object */
+#define MODULE_MC84 /*lint --e(923)*/ (*(Ifx_MC*)0xF0066400u)
+
+/** \brief MC object */
+#define MODULE_MC85 /*lint --e(923)*/ (*(Ifx_MC*)0xF0066500u)
+
+/** \brief MC object */
+#define MODULE_MC86 /*lint --e(923)*/ (*(Ifx_MC*)0xF0066600u)
+
+/** \brief MC object */
+#define MODULE_MC87 /*lint --e(923)*/ (*(Ifx_MC*)0xF0066700u)
+
+/** \brief MC object */
+#define MODULE_MC9 /*lint --e(923)*/ (*(Ifx_MC*)0xF0061900u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc0
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC0_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0061000u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC0_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0061002u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC0_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0061010u)
+
+/** \brief E, ECC Safety Register */
+#define MC0_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006100Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC0_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061012u)
+
+/** \brief 14, Error Tracking Register */
+#define MC0_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061014u)
+
+/** \brief 16, Error Tracking Register */
+#define MC0_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061016u)
+
+/** \brief 18, Error Tracking Register */
+#define MC0_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061018u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC0_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006101Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC0_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0061004u)
+
+/** \brief 6, Status Register */
+#define MC0_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0061006u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC0_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0061008u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC0_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC0_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC0_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC0_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC0_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC0_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC0_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC0_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC0_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC0_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC0_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC0_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC0_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC0_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC0_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC0_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC0_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC0_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC0_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC0_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC0_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC0_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC0_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC0_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC0_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC0_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC0_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC0_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC0_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC0_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC0_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC0_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC0_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC0_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC0_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC0_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC0_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC0_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC0_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC0_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00610B2u)
+
+/** \brief C, Revision ID Register */
+#define MC0_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006100Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc1
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC1_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0061100u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC1_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0061102u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC1_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0061110u)
+
+/** \brief E, ECC Safety Register */
+#define MC1_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006110Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC1_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061112u)
+
+/** \brief 14, Error Tracking Register */
+#define MC1_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061114u)
+
+/** \brief 16, Error Tracking Register */
+#define MC1_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061116u)
+
+/** \brief 18, Error Tracking Register */
+#define MC1_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061118u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC1_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006111Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC1_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0061104u)
+
+/** \brief 6, Status Register */
+#define MC1_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0061106u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC1_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0061108u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC1_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC1_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC1_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC1_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC1_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC1_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC1_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC1_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC1_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC1_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC1_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC1_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC1_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC1_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC1_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC1_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC1_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC1_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC1_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC1_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC1_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC1_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC1_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC1_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC1_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC1_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC1_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC1_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC1_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC1_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC1_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC1_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC1_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC1_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC1_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC1_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC1_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC1_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC1_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC1_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00611B2u)
+
+/** \brief C, Revision ID Register */
+#define MC1_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006110Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc2
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC2_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0061200u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC2_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0061202u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC2_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0061210u)
+
+/** \brief E, ECC Safety Register */
+#define MC2_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006120Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC2_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061212u)
+
+/** \brief 14, Error Tracking Register */
+#define MC2_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061214u)
+
+/** \brief 16, Error Tracking Register */
+#define MC2_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061216u)
+
+/** \brief 18, Error Tracking Register */
+#define MC2_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061218u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC2_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006121Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC2_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0061204u)
+
+/** \brief 6, Status Register */
+#define MC2_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0061206u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC2_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0061208u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC2_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC2_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC2_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC2_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC2_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC2_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC2_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC2_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC2_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC2_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC2_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC2_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC2_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC2_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC2_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC2_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC2_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC2_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC2_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC2_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC2_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC2_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC2_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC2_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC2_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC2_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC2_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC2_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC2_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC2_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC2_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC2_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC2_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC2_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC2_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC2_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC2_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC2_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC2_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC2_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00612B2u)
+
+/** \brief C, Revision ID Register */
+#define MC2_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006120Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc3
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC3_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0061300u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC3_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0061302u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC3_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0061310u)
+
+/** \brief E, ECC Safety Register */
+#define MC3_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006130Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC3_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061312u)
+
+/** \brief 14, Error Tracking Register */
+#define MC3_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061314u)
+
+/** \brief 16, Error Tracking Register */
+#define MC3_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061316u)
+
+/** \brief 18, Error Tracking Register */
+#define MC3_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061318u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC3_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006131Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC3_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0061304u)
+
+/** \brief 6, Status Register */
+#define MC3_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0061306u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC3_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0061308u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC3_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC3_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC3_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC3_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC3_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC3_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC3_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC3_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC3_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC3_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC3_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC3_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC3_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC3_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC3_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC3_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC3_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC3_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC3_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC3_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC3_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC3_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC3_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC3_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC3_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC3_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC3_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC3_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC3_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC3_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC3_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC3_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC3_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC3_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC3_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC3_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC3_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC3_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC3_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC3_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00613B2u)
+
+/** \brief C, Revision ID Register */
+#define MC3_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006130Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc4
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC4_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0061400u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC4_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0061402u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC4_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0061410u)
+
+/** \brief E, ECC Safety Register */
+#define MC4_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006140Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC4_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061412u)
+
+/** \brief 14, Error Tracking Register */
+#define MC4_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061414u)
+
+/** \brief 16, Error Tracking Register */
+#define MC4_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061416u)
+
+/** \brief 18, Error Tracking Register */
+#define MC4_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061418u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC4_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006141Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC4_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0061404u)
+
+/** \brief 6, Status Register */
+#define MC4_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0061406u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC4_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0061408u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC4_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC4_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC4_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC4_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC4_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC4_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC4_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC4_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC4_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC4_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC4_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC4_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC4_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC4_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC4_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC4_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC4_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC4_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC4_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC4_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC4_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC4_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC4_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC4_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC4_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC4_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC4_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC4_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC4_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC4_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC4_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC4_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC4_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC4_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC4_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC4_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC4_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC4_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC4_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC4_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00614B2u)
+
+/** \brief C, Revision ID Register */
+#define MC4_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006140Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc5
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC5_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0061500u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC5_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0061502u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC5_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0061510u)
+
+/** \brief E, ECC Safety Register */
+#define MC5_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006150Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC5_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061512u)
+
+/** \brief 14, Error Tracking Register */
+#define MC5_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061514u)
+
+/** \brief 16, Error Tracking Register */
+#define MC5_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061516u)
+
+/** \brief 18, Error Tracking Register */
+#define MC5_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061518u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC5_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006151Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC5_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0061504u)
+
+/** \brief 6, Status Register */
+#define MC5_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0061506u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC5_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0061508u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC5_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC5_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC5_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC5_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC5_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC5_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC5_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC5_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC5_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC5_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC5_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC5_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC5_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC5_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC5_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC5_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC5_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC5_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC5_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC5_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC5_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC5_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC5_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC5_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC5_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC5_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC5_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC5_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC5_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC5_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC5_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC5_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC5_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC5_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC5_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC5_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC5_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC5_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC5_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC5_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00615B2u)
+
+/** \brief C, Revision ID Register */
+#define MC5_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006150Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc6
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC6_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0061600u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC6_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0061602u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC6_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0061610u)
+
+/** \brief E, ECC Safety Register */
+#define MC6_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006160Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC6_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061612u)
+
+/** \brief 14, Error Tracking Register */
+#define MC6_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061614u)
+
+/** \brief 16, Error Tracking Register */
+#define MC6_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061616u)
+
+/** \brief 18, Error Tracking Register */
+#define MC6_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061618u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC6_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006161Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC6_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0061604u)
+
+/** \brief 6, Status Register */
+#define MC6_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0061606u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC6_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0061608u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC6_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC6_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC6_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC6_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC6_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC6_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC6_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC6_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC6_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC6_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC6_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC6_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC6_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC6_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC6_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC6_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC6_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC6_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC6_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC6_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC6_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC6_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC6_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC6_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC6_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC6_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC6_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC6_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC6_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC6_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC6_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC6_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC6_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC6_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC6_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC6_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC6_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC6_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC6_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC6_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00616B2u)
+
+/** \brief C, Revision ID Register */
+#define MC6_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006160Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc7
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC7_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0061700u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC7_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0061702u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC7_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0061710u)
+
+/** \brief E, ECC Safety Register */
+#define MC7_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006170Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC7_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061712u)
+
+/** \brief 14, Error Tracking Register */
+#define MC7_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061714u)
+
+/** \brief 16, Error Tracking Register */
+#define MC7_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061716u)
+
+/** \brief 18, Error Tracking Register */
+#define MC7_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061718u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC7_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006171Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC7_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0061704u)
+
+/** \brief 6, Status Register */
+#define MC7_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0061706u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC7_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0061708u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC7_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC7_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC7_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC7_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC7_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC7_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC7_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC7_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC7_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC7_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC7_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC7_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC7_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC7_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC7_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC7_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC7_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC7_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC7_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC7_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC7_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC7_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC7_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC7_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC7_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC7_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC7_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC7_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC7_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC7_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC7_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC7_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC7_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC7_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC7_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC7_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC7_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC7_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC7_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC7_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00617B2u)
+
+/** \brief C, Revision ID Register */
+#define MC7_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006170Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc8
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC8_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0061800u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC8_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0061802u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC8_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0061810u)
+
+/** \brief E, ECC Safety Register */
+#define MC8_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006180Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC8_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061812u)
+
+/** \brief 14, Error Tracking Register */
+#define MC8_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061814u)
+
+/** \brief 16, Error Tracking Register */
+#define MC8_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061816u)
+
+/** \brief 18, Error Tracking Register */
+#define MC8_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061818u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC8_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006181Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC8_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0061804u)
+
+/** \brief 6, Status Register */
+#define MC8_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0061806u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC8_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0061808u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC8_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC8_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC8_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC8_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC8_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC8_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC8_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC8_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC8_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC8_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC8_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC8_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC8_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC8_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC8_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC8_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC8_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC8_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC8_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC8_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC8_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC8_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC8_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC8_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC8_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC8_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC8_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC8_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC8_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC8_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC8_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC8_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC8_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC8_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC8_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC8_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC8_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC8_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC8_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC8_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00618B2u)
+
+/** \brief C, Revision ID Register */
+#define MC8_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006180Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc9
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC9_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0061900u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC9_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0061902u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC9_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0061910u)
+
+/** \brief E, ECC Safety Register */
+#define MC9_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006190Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC9_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061912u)
+
+/** \brief 14, Error Tracking Register */
+#define MC9_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061914u)
+
+/** \brief 16, Error Tracking Register */
+#define MC9_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061916u)
+
+/** \brief 18, Error Tracking Register */
+#define MC9_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061918u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC9_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006191Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC9_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0061904u)
+
+/** \brief 6, Status Register */
+#define MC9_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0061906u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC9_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0061908u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC9_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC9_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC9_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC9_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC9_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC9_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC9_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC9_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC9_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC9_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC9_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC9_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC9_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC9_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC9_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC9_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC9_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC9_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC9_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC9_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC9_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC9_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC9_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC9_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC9_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC9_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC9_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC9_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC9_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC9_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC9_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC9_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC9_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC9_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC9_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC9_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC9_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC9_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC9_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC9_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00619B2u)
+
+/** \brief C, Revision ID Register */
+#define MC9_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006190Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc10
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC10_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0061A00u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC10_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0061A02u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC10_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0061A10u)
+
+/** \brief E, ECC Safety Register */
+#define MC10_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF0061A0Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC10_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061A12u)
+
+/** \brief 14, Error Tracking Register */
+#define MC10_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061A14u)
+
+/** \brief 16, Error Tracking Register */
+#define MC10_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061A16u)
+
+/** \brief 18, Error Tracking Register */
+#define MC10_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061A18u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC10_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061A1Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC10_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0061A04u)
+
+/** \brief 6, Status Register */
+#define MC10_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0061A06u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC10_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0061A08u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC10_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AA0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC10_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AA2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC10_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AB4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC10_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AB6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC10_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AB8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC10_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061ABAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC10_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061ABCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC10_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061ABEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC10_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AC0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC10_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AC2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC10_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AC4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC10_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AC6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC10_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AA4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC10_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AC8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC10_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061ACAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC10_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061ACCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC10_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061ACEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC10_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AD0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC10_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AD2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC10_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AD4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC10_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AD6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC10_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AD8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC10_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061ADAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC10_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AA6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC10_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061ADCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC10_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061ADEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC10_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AE0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC10_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AE2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC10_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AE4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC10_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AE6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC10_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AE8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC10_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AEAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC10_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC10_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AEEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC10_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AA8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC10_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AAAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC10_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC10_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AAEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC10_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AB0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC10_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061AB2u)
+
+/** \brief C, Revision ID Register */
+#define MC10_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF0061A0Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc11
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC11_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0061B00u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC11_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0061B02u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC11_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0061B10u)
+
+/** \brief E, ECC Safety Register */
+#define MC11_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF0061B0Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC11_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061B12u)
+
+/** \brief 14, Error Tracking Register */
+#define MC11_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061B14u)
+
+/** \brief 16, Error Tracking Register */
+#define MC11_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061B16u)
+
+/** \brief 18, Error Tracking Register */
+#define MC11_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061B18u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC11_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061B1Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC11_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0061B04u)
+
+/** \brief 6, Status Register */
+#define MC11_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0061B06u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC11_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0061B08u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC11_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BA0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC11_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BA2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC11_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BB4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC11_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BB6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC11_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BB8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC11_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BBAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC11_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BBCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC11_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BBEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC11_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BC0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC11_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BC2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC11_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BC4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC11_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BC6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC11_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BA4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC11_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BC8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC11_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BCAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC11_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BCCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC11_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BCEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC11_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BD0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC11_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BD2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC11_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BD4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC11_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BD6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC11_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BD8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC11_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BDAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC11_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BA6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC11_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BDCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC11_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BDEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC11_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BE0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC11_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BE2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC11_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BE4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC11_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BE6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC11_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BE8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC11_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BEAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC11_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC11_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BEEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC11_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BA8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC11_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BAAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC11_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC11_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BAEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC11_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BB0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC11_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061BB2u)
+
+/** \brief C, Revision ID Register */
+#define MC11_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF0061B0Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc12
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC12_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0061C00u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC12_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0061C02u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC12_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0061C10u)
+
+/** \brief E, ECC Safety Register */
+#define MC12_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF0061C0Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC12_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061C12u)
+
+/** \brief 14, Error Tracking Register */
+#define MC12_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061C14u)
+
+/** \brief 16, Error Tracking Register */
+#define MC12_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061C16u)
+
+/** \brief 18, Error Tracking Register */
+#define MC12_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061C18u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC12_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061C1Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC12_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0061C04u)
+
+/** \brief 6, Status Register */
+#define MC12_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0061C06u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC12_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0061C08u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC12_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CA0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC12_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CA2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC12_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CB4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC12_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CB6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC12_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CB8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC12_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CBAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC12_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CBCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC12_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CBEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC12_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CC0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC12_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CC2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC12_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CC4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC12_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CC6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC12_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CA4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC12_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CC8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC12_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CCAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC12_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CCCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC12_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CCEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC12_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CD0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC12_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CD2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC12_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CD4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC12_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CD6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC12_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CD8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC12_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CDAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC12_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CA6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC12_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CDCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC12_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CDEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC12_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CE0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC12_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CE2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC12_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CE4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC12_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CE6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC12_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CE8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC12_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CEAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC12_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC12_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CEEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC12_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CA8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC12_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CAAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC12_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC12_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CAEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC12_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CB0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC12_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061CB2u)
+
+/** \brief C, Revision ID Register */
+#define MC12_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF0061C0Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc13
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC13_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0061D00u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC13_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0061D02u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC13_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0061D10u)
+
+/** \brief E, ECC Safety Register */
+#define MC13_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF0061D0Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC13_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061D12u)
+
+/** \brief 14, Error Tracking Register */
+#define MC13_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061D14u)
+
+/** \brief 16, Error Tracking Register */
+#define MC13_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061D16u)
+
+/** \brief 18, Error Tracking Register */
+#define MC13_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061D18u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC13_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061D1Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC13_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0061D04u)
+
+/** \brief 6, Status Register */
+#define MC13_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0061D06u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC13_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0061D08u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC13_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DA0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC13_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DA2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC13_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DB4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC13_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DB6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC13_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DB8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC13_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DBAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC13_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DBCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC13_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DBEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC13_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DC0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC13_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DC2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC13_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DC4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC13_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DC6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC13_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DA4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC13_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DC8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC13_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DCAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC13_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DCCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC13_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DCEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC13_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DD0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC13_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DD2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC13_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DD4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC13_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DD6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC13_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DD8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC13_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DDAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC13_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DA6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC13_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DDCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC13_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DDEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC13_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DE0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC13_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DE2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC13_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DE4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC13_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DE6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC13_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DE8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC13_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DEAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC13_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC13_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DEEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC13_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DA8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC13_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DAAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC13_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC13_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DAEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC13_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DB0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC13_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061DB2u)
+
+/** \brief C, Revision ID Register */
+#define MC13_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF0061D0Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc14
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC14_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0061E00u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC14_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0061E02u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC14_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0061E10u)
+
+/** \brief E, ECC Safety Register */
+#define MC14_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF0061E0Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC14_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061E12u)
+
+/** \brief 14, Error Tracking Register */
+#define MC14_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061E14u)
+
+/** \brief 16, Error Tracking Register */
+#define MC14_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061E16u)
+
+/** \brief 18, Error Tracking Register */
+#define MC14_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061E18u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC14_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061E1Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC14_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0061E04u)
+
+/** \brief 6, Status Register */
+#define MC14_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0061E06u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC14_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0061E08u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC14_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EA0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC14_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EA2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC14_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EB4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC14_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EB6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC14_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EB8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC14_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EBAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC14_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EBCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC14_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EBEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC14_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EC0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC14_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EC2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC14_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EC4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC14_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EC6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC14_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EA4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC14_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EC8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC14_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061ECAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC14_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061ECCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC14_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061ECEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC14_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061ED0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC14_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061ED2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC14_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061ED4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC14_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061ED6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC14_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061ED8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC14_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EDAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC14_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EA6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC14_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EDCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC14_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EDEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC14_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EE0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC14_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EE2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC14_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EE4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC14_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EE6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC14_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EE8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC14_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EEAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC14_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC14_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EEEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC14_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EA8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC14_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EAAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC14_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC14_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EAEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC14_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EB0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC14_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061EB2u)
+
+/** \brief C, Revision ID Register */
+#define MC14_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF0061E0Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc15
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC15_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0061F00u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC15_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0061F02u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC15_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0061F10u)
+
+/** \brief E, ECC Safety Register */
+#define MC15_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF0061F0Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC15_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061F12u)
+
+/** \brief 14, Error Tracking Register */
+#define MC15_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061F14u)
+
+/** \brief 16, Error Tracking Register */
+#define MC15_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061F16u)
+
+/** \brief 18, Error Tracking Register */
+#define MC15_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061F18u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC15_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0061F1Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC15_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0061F04u)
+
+/** \brief 6, Status Register */
+#define MC15_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0061F06u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC15_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0061F08u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC15_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FA0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC15_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FA2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC15_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FB4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC15_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FB6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC15_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FB8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC15_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FBAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC15_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FBCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC15_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FBEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC15_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FC0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC15_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FC2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC15_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FC4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC15_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FC6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC15_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FA4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC15_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FC8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC15_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FCAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC15_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FCCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC15_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FCEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC15_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FD0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC15_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FD2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC15_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FD4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC15_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FD6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC15_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FD8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC15_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FDAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC15_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FA6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC15_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FDCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC15_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FDEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC15_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FE0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC15_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FE2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC15_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FE4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC15_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FE6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC15_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FE8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC15_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FEAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC15_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC15_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FEEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC15_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FA8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC15_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FAAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC15_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC15_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FAEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC15_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FB0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC15_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0061FB2u)
+
+/** \brief C, Revision ID Register */
+#define MC15_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF0061F0Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc16
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC16_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0062000u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC16_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0062002u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC16_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0062010u)
+
+/** \brief E, ECC Safety Register */
+#define MC16_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006200Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC16_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062012u)
+
+/** \brief 14, Error Tracking Register */
+#define MC16_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062014u)
+
+/** \brief 16, Error Tracking Register */
+#define MC16_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062016u)
+
+/** \brief 18, Error Tracking Register */
+#define MC16_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062018u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC16_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006201Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC16_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0062004u)
+
+/** \brief 6, Status Register */
+#define MC16_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0062006u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC16_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0062008u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC16_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC16_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC16_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC16_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC16_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC16_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC16_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC16_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC16_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC16_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC16_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC16_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC16_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC16_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC16_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC16_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC16_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC16_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC16_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC16_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC16_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC16_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC16_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC16_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC16_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC16_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC16_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC16_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC16_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC16_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC16_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC16_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC16_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC16_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC16_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC16_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC16_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC16_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC16_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC16_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00620B2u)
+
+/** \brief C, Revision ID Register */
+#define MC16_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006200Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc17
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC17_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0062100u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC17_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0062102u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC17_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0062110u)
+
+/** \brief E, ECC Safety Register */
+#define MC17_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006210Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC17_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062112u)
+
+/** \brief 14, Error Tracking Register */
+#define MC17_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062114u)
+
+/** \brief 16, Error Tracking Register */
+#define MC17_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062116u)
+
+/** \brief 18, Error Tracking Register */
+#define MC17_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062118u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC17_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006211Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC17_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0062104u)
+
+/** \brief 6, Status Register */
+#define MC17_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0062106u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC17_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0062108u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC17_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC17_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC17_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC17_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC17_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC17_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC17_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC17_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC17_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC17_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC17_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC17_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC17_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC17_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC17_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC17_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC17_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC17_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC17_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC17_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC17_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC17_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC17_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC17_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC17_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC17_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC17_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC17_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC17_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC17_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC17_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC17_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC17_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC17_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC17_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC17_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC17_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC17_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC17_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC17_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00621B2u)
+
+/** \brief C, Revision ID Register */
+#define MC17_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006210Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc18
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC18_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0062200u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC18_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0062202u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC18_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0062210u)
+
+/** \brief E, ECC Safety Register */
+#define MC18_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006220Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC18_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062212u)
+
+/** \brief 14, Error Tracking Register */
+#define MC18_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062214u)
+
+/** \brief 16, Error Tracking Register */
+#define MC18_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062216u)
+
+/** \brief 18, Error Tracking Register */
+#define MC18_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062218u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC18_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006221Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC18_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0062204u)
+
+/** \brief 6, Status Register */
+#define MC18_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0062206u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC18_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0062208u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC18_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC18_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC18_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC18_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC18_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC18_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC18_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC18_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC18_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC18_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC18_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC18_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC18_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC18_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC18_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC18_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC18_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC18_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC18_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC18_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC18_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC18_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC18_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC18_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC18_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC18_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC18_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC18_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC18_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC18_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC18_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC18_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC18_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC18_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC18_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC18_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC18_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC18_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC18_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC18_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00622B2u)
+
+/** \brief C, Revision ID Register */
+#define MC18_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006220Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc19
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC19_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0062300u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC19_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0062302u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC19_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0062310u)
+
+/** \brief E, ECC Safety Register */
+#define MC19_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006230Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC19_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062312u)
+
+/** \brief 14, Error Tracking Register */
+#define MC19_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062314u)
+
+/** \brief 16, Error Tracking Register */
+#define MC19_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062316u)
+
+/** \brief 18, Error Tracking Register */
+#define MC19_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062318u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC19_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006231Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC19_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0062304u)
+
+/** \brief 6, Status Register */
+#define MC19_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0062306u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC19_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0062308u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC19_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC19_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC19_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC19_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC19_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC19_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC19_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC19_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC19_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC19_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC19_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC19_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC19_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC19_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC19_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC19_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC19_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC19_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC19_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC19_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC19_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC19_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC19_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC19_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC19_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC19_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC19_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC19_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC19_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC19_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC19_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC19_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC19_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC19_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC19_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC19_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC19_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC19_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC19_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC19_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00623B2u)
+
+/** \brief C, Revision ID Register */
+#define MC19_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006230Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc20
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC20_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0062400u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC20_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0062402u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC20_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0062410u)
+
+/** \brief E, ECC Safety Register */
+#define MC20_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006240Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC20_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062412u)
+
+/** \brief 14, Error Tracking Register */
+#define MC20_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062414u)
+
+/** \brief 16, Error Tracking Register */
+#define MC20_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062416u)
+
+/** \brief 18, Error Tracking Register */
+#define MC20_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062418u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC20_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006241Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC20_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0062404u)
+
+/** \brief 6, Status Register */
+#define MC20_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0062406u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC20_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0062408u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC20_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC20_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC20_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC20_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC20_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC20_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC20_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC20_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC20_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC20_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC20_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC20_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC20_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC20_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC20_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC20_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC20_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC20_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC20_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC20_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC20_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC20_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC20_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC20_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC20_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC20_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC20_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC20_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC20_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC20_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC20_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC20_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC20_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC20_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC20_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC20_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC20_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC20_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC20_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC20_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00624B2u)
+
+/** \brief C, Revision ID Register */
+#define MC20_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006240Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc21
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC21_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0062500u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC21_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0062502u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC21_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0062510u)
+
+/** \brief E, ECC Safety Register */
+#define MC21_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006250Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC21_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062512u)
+
+/** \brief 14, Error Tracking Register */
+#define MC21_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062514u)
+
+/** \brief 16, Error Tracking Register */
+#define MC21_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062516u)
+
+/** \brief 18, Error Tracking Register */
+#define MC21_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062518u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC21_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006251Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC21_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0062504u)
+
+/** \brief 6, Status Register */
+#define MC21_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0062506u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC21_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0062508u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC21_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC21_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC21_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC21_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC21_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC21_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC21_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC21_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC21_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC21_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC21_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC21_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC21_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC21_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC21_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC21_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC21_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC21_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC21_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC21_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC21_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC21_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC21_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC21_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC21_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC21_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC21_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC21_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC21_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC21_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC21_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC21_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC21_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC21_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC21_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC21_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC21_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC21_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC21_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC21_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00625B2u)
+
+/** \brief C, Revision ID Register */
+#define MC21_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006250Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc22
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC22_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0062600u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC22_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0062602u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC22_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0062610u)
+
+/** \brief E, ECC Safety Register */
+#define MC22_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006260Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC22_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062612u)
+
+/** \brief 14, Error Tracking Register */
+#define MC22_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062614u)
+
+/** \brief 16, Error Tracking Register */
+#define MC22_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062616u)
+
+/** \brief 18, Error Tracking Register */
+#define MC22_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062618u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC22_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006261Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC22_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0062604u)
+
+/** \brief 6, Status Register */
+#define MC22_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0062606u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC22_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0062608u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC22_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC22_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC22_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC22_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC22_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC22_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC22_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC22_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC22_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC22_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC22_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC22_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC22_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC22_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC22_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC22_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC22_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC22_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC22_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC22_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC22_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC22_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC22_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC22_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC22_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC22_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC22_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC22_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC22_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC22_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC22_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC22_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC22_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC22_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC22_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC22_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC22_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC22_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC22_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC22_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00626B2u)
+
+/** \brief C, Revision ID Register */
+#define MC22_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006260Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc23
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC23_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0062700u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC23_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0062702u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC23_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0062710u)
+
+/** \brief E, ECC Safety Register */
+#define MC23_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006270Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC23_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062712u)
+
+/** \brief 14, Error Tracking Register */
+#define MC23_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062714u)
+
+/** \brief 16, Error Tracking Register */
+#define MC23_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062716u)
+
+/** \brief 18, Error Tracking Register */
+#define MC23_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062718u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC23_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006271Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC23_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0062704u)
+
+/** \brief 6, Status Register */
+#define MC23_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0062706u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC23_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0062708u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC23_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC23_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC23_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC23_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC23_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC23_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC23_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC23_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC23_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC23_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC23_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC23_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC23_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC23_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC23_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC23_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC23_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC23_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC23_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC23_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC23_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC23_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC23_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC23_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC23_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC23_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC23_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC23_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC23_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC23_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC23_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC23_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC23_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC23_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC23_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC23_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC23_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC23_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC23_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC23_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00627B2u)
+
+/** \brief C, Revision ID Register */
+#define MC23_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006270Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc24
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC24_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0062800u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC24_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0062802u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC24_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0062810u)
+
+/** \brief E, ECC Safety Register */
+#define MC24_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006280Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC24_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062812u)
+
+/** \brief 14, Error Tracking Register */
+#define MC24_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062814u)
+
+/** \brief 16, Error Tracking Register */
+#define MC24_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062816u)
+
+/** \brief 18, Error Tracking Register */
+#define MC24_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062818u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC24_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006281Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC24_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0062804u)
+
+/** \brief 6, Status Register */
+#define MC24_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0062806u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC24_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0062808u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC24_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC24_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC24_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC24_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC24_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC24_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC24_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC24_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC24_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC24_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC24_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC24_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC24_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC24_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC24_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC24_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC24_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC24_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC24_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC24_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC24_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC24_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC24_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC24_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC24_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC24_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC24_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC24_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC24_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC24_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC24_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC24_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC24_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC24_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC24_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC24_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC24_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC24_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC24_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC24_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00628B2u)
+
+/** \brief C, Revision ID Register */
+#define MC24_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006280Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc25
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC25_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0062900u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC25_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0062902u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC25_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0062910u)
+
+/** \brief E, ECC Safety Register */
+#define MC25_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006290Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC25_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062912u)
+
+/** \brief 14, Error Tracking Register */
+#define MC25_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062914u)
+
+/** \brief 16, Error Tracking Register */
+#define MC25_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062916u)
+
+/** \brief 18, Error Tracking Register */
+#define MC25_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062918u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC25_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006291Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC25_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0062904u)
+
+/** \brief 6, Status Register */
+#define MC25_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0062906u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC25_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0062908u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC25_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC25_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC25_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC25_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC25_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC25_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC25_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC25_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC25_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC25_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC25_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC25_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC25_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC25_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC25_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC25_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC25_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC25_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC25_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC25_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC25_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC25_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC25_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC25_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC25_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC25_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC25_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC25_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC25_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC25_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC25_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC25_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC25_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC25_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC25_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC25_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC25_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC25_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC25_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC25_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00629B2u)
+
+/** \brief C, Revision ID Register */
+#define MC25_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006290Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc26
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC26_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0062A00u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC26_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0062A02u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC26_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0062A10u)
+
+/** \brief E, ECC Safety Register */
+#define MC26_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF0062A0Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC26_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062A12u)
+
+/** \brief 14, Error Tracking Register */
+#define MC26_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062A14u)
+
+/** \brief 16, Error Tracking Register */
+#define MC26_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062A16u)
+
+/** \brief 18, Error Tracking Register */
+#define MC26_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062A18u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC26_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062A1Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC26_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0062A04u)
+
+/** \brief 6, Status Register */
+#define MC26_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0062A06u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC26_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0062A08u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC26_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AA0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC26_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AA2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC26_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AB4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC26_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AB6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC26_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AB8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC26_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062ABAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC26_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062ABCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC26_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062ABEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC26_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AC0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC26_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AC2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC26_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AC4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC26_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AC6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC26_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AA4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC26_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AC8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC26_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062ACAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC26_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062ACCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC26_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062ACEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC26_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AD0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC26_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AD2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC26_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AD4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC26_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AD6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC26_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AD8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC26_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062ADAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC26_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AA6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC26_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062ADCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC26_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062ADEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC26_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AE0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC26_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AE2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC26_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AE4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC26_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AE6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC26_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AE8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC26_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AEAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC26_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC26_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AEEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC26_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AA8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC26_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AAAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC26_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC26_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AAEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC26_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AB0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC26_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062AB2u)
+
+/** \brief C, Revision ID Register */
+#define MC26_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF0062A0Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc27
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC27_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0062B00u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC27_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0062B02u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC27_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0062B10u)
+
+/** \brief E, ECC Safety Register */
+#define MC27_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF0062B0Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC27_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062B12u)
+
+/** \brief 14, Error Tracking Register */
+#define MC27_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062B14u)
+
+/** \brief 16, Error Tracking Register */
+#define MC27_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062B16u)
+
+/** \brief 18, Error Tracking Register */
+#define MC27_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062B18u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC27_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062B1Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC27_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0062B04u)
+
+/** \brief 6, Status Register */
+#define MC27_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0062B06u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC27_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0062B08u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC27_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BA0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC27_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BA2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC27_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BB4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC27_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BB6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC27_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BB8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC27_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BBAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC27_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BBCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC27_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BBEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC27_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BC0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC27_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BC2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC27_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BC4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC27_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BC6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC27_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BA4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC27_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BC8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC27_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BCAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC27_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BCCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC27_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BCEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC27_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BD0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC27_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BD2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC27_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BD4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC27_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BD6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC27_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BD8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC27_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BDAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC27_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BA6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC27_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BDCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC27_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BDEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC27_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BE0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC27_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BE2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC27_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BE4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC27_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BE6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC27_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BE8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC27_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BEAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC27_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC27_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BEEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC27_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BA8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC27_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BAAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC27_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC27_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BAEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC27_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BB0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC27_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062BB2u)
+
+/** \brief C, Revision ID Register */
+#define MC27_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF0062B0Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc28
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC28_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0062C00u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC28_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0062C02u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC28_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0062C10u)
+
+/** \brief E, ECC Safety Register */
+#define MC28_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF0062C0Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC28_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062C12u)
+
+/** \brief 14, Error Tracking Register */
+#define MC28_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062C14u)
+
+/** \brief 16, Error Tracking Register */
+#define MC28_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062C16u)
+
+/** \brief 18, Error Tracking Register */
+#define MC28_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062C18u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC28_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062C1Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC28_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0062C04u)
+
+/** \brief 6, Status Register */
+#define MC28_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0062C06u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC28_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0062C08u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC28_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CA0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC28_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CA2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC28_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CB4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC28_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CB6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC28_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CB8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC28_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CBAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC28_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CBCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC28_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CBEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC28_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CC0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC28_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CC2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC28_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CC4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC28_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CC6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC28_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CA4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC28_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CC8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC28_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CCAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC28_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CCCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC28_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CCEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC28_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CD0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC28_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CD2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC28_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CD4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC28_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CD6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC28_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CD8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC28_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CDAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC28_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CA6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC28_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CDCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC28_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CDEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC28_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CE0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC28_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CE2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC28_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CE4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC28_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CE6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC28_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CE8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC28_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CEAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC28_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC28_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CEEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC28_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CA8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC28_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CAAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC28_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC28_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CAEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC28_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CB0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC28_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062CB2u)
+
+/** \brief C, Revision ID Register */
+#define MC28_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF0062C0Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc29
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC29_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0062D00u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC29_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0062D02u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC29_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0062D10u)
+
+/** \brief E, ECC Safety Register */
+#define MC29_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF0062D0Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC29_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062D12u)
+
+/** \brief 14, Error Tracking Register */
+#define MC29_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062D14u)
+
+/** \brief 16, Error Tracking Register */
+#define MC29_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062D16u)
+
+/** \brief 18, Error Tracking Register */
+#define MC29_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062D18u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC29_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062D1Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC29_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0062D04u)
+
+/** \brief 6, Status Register */
+#define MC29_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0062D06u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC29_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0062D08u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC29_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DA0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC29_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DA2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC29_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DB4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC29_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DB6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC29_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DB8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC29_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DBAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC29_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DBCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC29_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DBEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC29_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DC0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC29_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DC2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC29_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DC4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC29_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DC6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC29_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DA4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC29_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DC8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC29_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DCAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC29_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DCCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC29_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DCEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC29_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DD0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC29_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DD2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC29_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DD4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC29_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DD6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC29_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DD8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC29_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DDAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC29_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DA6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC29_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DDCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC29_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DDEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC29_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DE0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC29_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DE2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC29_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DE4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC29_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DE6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC29_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DE8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC29_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DEAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC29_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC29_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DEEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC29_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DA8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC29_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DAAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC29_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC29_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DAEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC29_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DB0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC29_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062DB2u)
+
+/** \brief C, Revision ID Register */
+#define MC29_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF0062D0Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc30
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC30_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0062E00u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC30_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0062E02u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC30_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0062E10u)
+
+/** \brief E, ECC Safety Register */
+#define MC30_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF0062E0Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC30_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062E12u)
+
+/** \brief 14, Error Tracking Register */
+#define MC30_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062E14u)
+
+/** \brief 16, Error Tracking Register */
+#define MC30_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062E16u)
+
+/** \brief 18, Error Tracking Register */
+#define MC30_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062E18u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC30_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062E1Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC30_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0062E04u)
+
+/** \brief 6, Status Register */
+#define MC30_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0062E06u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC30_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0062E08u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC30_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EA0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC30_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EA2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC30_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EB4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC30_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EB6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC30_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EB8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC30_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EBAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC30_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EBCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC30_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EBEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC30_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EC0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC30_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EC2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC30_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EC4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC30_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EC6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC30_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EA4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC30_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EC8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC30_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062ECAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC30_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062ECCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC30_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062ECEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC30_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062ED0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC30_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062ED2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC30_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062ED4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC30_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062ED6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC30_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062ED8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC30_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EDAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC30_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EA6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC30_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EDCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC30_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EDEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC30_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EE0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC30_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EE2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC30_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EE4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC30_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EE6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC30_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EE8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC30_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EEAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC30_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC30_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EEEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC30_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EA8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC30_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EAAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC30_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC30_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EAEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC30_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EB0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC30_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062EB2u)
+
+/** \brief C, Revision ID Register */
+#define MC30_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF0062E0Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc31
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC31_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0062F00u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC31_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0062F02u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC31_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0062F10u)
+
+/** \brief E, ECC Safety Register */
+#define MC31_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF0062F0Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC31_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062F12u)
+
+/** \brief 14, Error Tracking Register */
+#define MC31_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062F14u)
+
+/** \brief 16, Error Tracking Register */
+#define MC31_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062F16u)
+
+/** \brief 18, Error Tracking Register */
+#define MC31_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062F18u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC31_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0062F1Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC31_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0062F04u)
+
+/** \brief 6, Status Register */
+#define MC31_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0062F06u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC31_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0062F08u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC31_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FA0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC31_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FA2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC31_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FB4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC31_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FB6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC31_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FB8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC31_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FBAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC31_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FBCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC31_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FBEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC31_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FC0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC31_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FC2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC31_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FC4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC31_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FC6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC31_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FA4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC31_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FC8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC31_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FCAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC31_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FCCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC31_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FCEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC31_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FD0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC31_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FD2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC31_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FD4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC31_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FD6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC31_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FD8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC31_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FDAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC31_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FA6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC31_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FDCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC31_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FDEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC31_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FE0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC31_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FE2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC31_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FE4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC31_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FE6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC31_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FE8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC31_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FEAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC31_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC31_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FEEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC31_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FA8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC31_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FAAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC31_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC31_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FAEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC31_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FB0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC31_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0062FB2u)
+
+/** \brief C, Revision ID Register */
+#define MC31_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF0062F0Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc32
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC32_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0063000u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC32_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0063002u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC32_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0063010u)
+
+/** \brief E, ECC Safety Register */
+#define MC32_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006300Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC32_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063012u)
+
+/** \brief 14, Error Tracking Register */
+#define MC32_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063014u)
+
+/** \brief 16, Error Tracking Register */
+#define MC32_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063016u)
+
+/** \brief 18, Error Tracking Register */
+#define MC32_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063018u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC32_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006301Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC32_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0063004u)
+
+/** \brief 6, Status Register */
+#define MC32_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0063006u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC32_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0063008u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC32_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC32_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC32_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC32_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC32_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC32_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC32_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC32_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC32_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC32_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC32_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC32_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC32_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC32_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC32_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC32_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC32_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC32_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC32_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC32_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC32_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC32_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC32_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC32_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC32_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC32_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC32_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC32_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC32_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC32_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC32_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC32_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC32_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC32_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC32_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC32_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC32_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC32_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC32_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC32_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00630B2u)
+
+/** \brief C, Revision ID Register */
+#define MC32_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006300Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc33
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC33_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0063100u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC33_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0063102u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC33_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0063110u)
+
+/** \brief E, ECC Safety Register */
+#define MC33_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006310Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC33_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063112u)
+
+/** \brief 14, Error Tracking Register */
+#define MC33_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063114u)
+
+/** \brief 16, Error Tracking Register */
+#define MC33_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063116u)
+
+/** \brief 18, Error Tracking Register */
+#define MC33_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063118u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC33_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006311Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC33_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0063104u)
+
+/** \brief 6, Status Register */
+#define MC33_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0063106u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC33_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0063108u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC33_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC33_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC33_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC33_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC33_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC33_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC33_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC33_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC33_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC33_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC33_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC33_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC33_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC33_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC33_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC33_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC33_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC33_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC33_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC33_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC33_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC33_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC33_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC33_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC33_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC33_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC33_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC33_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC33_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC33_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC33_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC33_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC33_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC33_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC33_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC33_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC33_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC33_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC33_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC33_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00631B2u)
+
+/** \brief C, Revision ID Register */
+#define MC33_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006310Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc34
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC34_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0063200u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC34_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0063202u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC34_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0063210u)
+
+/** \brief E, ECC Safety Register */
+#define MC34_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006320Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC34_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063212u)
+
+/** \brief 14, Error Tracking Register */
+#define MC34_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063214u)
+
+/** \brief 16, Error Tracking Register */
+#define MC34_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063216u)
+
+/** \brief 18, Error Tracking Register */
+#define MC34_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063218u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC34_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006321Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC34_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0063204u)
+
+/** \brief 6, Status Register */
+#define MC34_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0063206u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC34_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0063208u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC34_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC34_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC34_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC34_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC34_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC34_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC34_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC34_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC34_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC34_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC34_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC34_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC34_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC34_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC34_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC34_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC34_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC34_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC34_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC34_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC34_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC34_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC34_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC34_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC34_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC34_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC34_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC34_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC34_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC34_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC34_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC34_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC34_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC34_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC34_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC34_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC34_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC34_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC34_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC34_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00632B2u)
+
+/** \brief C, Revision ID Register */
+#define MC34_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006320Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc35
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC35_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0063300u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC35_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0063302u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC35_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0063310u)
+
+/** \brief E, ECC Safety Register */
+#define MC35_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006330Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC35_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063312u)
+
+/** \brief 14, Error Tracking Register */
+#define MC35_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063314u)
+
+/** \brief 16, Error Tracking Register */
+#define MC35_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063316u)
+
+/** \brief 18, Error Tracking Register */
+#define MC35_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063318u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC35_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006331Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC35_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0063304u)
+
+/** \brief 6, Status Register */
+#define MC35_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0063306u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC35_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0063308u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC35_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC35_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC35_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC35_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC35_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC35_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC35_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC35_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC35_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC35_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC35_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC35_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC35_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC35_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC35_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC35_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC35_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC35_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC35_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC35_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC35_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC35_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC35_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC35_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC35_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC35_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC35_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC35_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC35_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC35_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC35_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC35_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC35_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC35_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC35_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC35_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC35_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC35_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC35_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC35_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00633B2u)
+
+/** \brief C, Revision ID Register */
+#define MC35_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006330Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc36
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC36_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0063400u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC36_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0063402u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC36_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0063410u)
+
+/** \brief E, ECC Safety Register */
+#define MC36_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006340Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC36_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063412u)
+
+/** \brief 14, Error Tracking Register */
+#define MC36_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063414u)
+
+/** \brief 16, Error Tracking Register */
+#define MC36_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063416u)
+
+/** \brief 18, Error Tracking Register */
+#define MC36_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063418u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC36_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006341Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC36_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0063404u)
+
+/** \brief 6, Status Register */
+#define MC36_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0063406u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC36_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0063408u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC36_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC36_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC36_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC36_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC36_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC36_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC36_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC36_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC36_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC36_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC36_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC36_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC36_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC36_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC36_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC36_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC36_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC36_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC36_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC36_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC36_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC36_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC36_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC36_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC36_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC36_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC36_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC36_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC36_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC36_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC36_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC36_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC36_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC36_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC36_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC36_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC36_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC36_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC36_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC36_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00634B2u)
+
+/** \brief C, Revision ID Register */
+#define MC36_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006340Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc37
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC37_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0063500u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC37_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0063502u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC37_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0063510u)
+
+/** \brief E, ECC Safety Register */
+#define MC37_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006350Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC37_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063512u)
+
+/** \brief 14, Error Tracking Register */
+#define MC37_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063514u)
+
+/** \brief 16, Error Tracking Register */
+#define MC37_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063516u)
+
+/** \brief 18, Error Tracking Register */
+#define MC37_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063518u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC37_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006351Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC37_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0063504u)
+
+/** \brief 6, Status Register */
+#define MC37_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0063506u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC37_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0063508u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC37_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC37_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC37_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC37_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC37_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC37_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC37_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC37_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC37_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC37_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC37_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC37_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC37_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC37_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC37_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC37_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC37_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC37_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC37_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC37_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC37_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC37_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC37_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC37_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC37_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC37_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC37_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC37_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC37_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC37_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC37_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC37_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC37_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC37_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC37_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC37_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC37_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC37_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC37_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC37_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00635B2u)
+
+/** \brief C, Revision ID Register */
+#define MC37_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006350Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc38
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC38_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0063600u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC38_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0063602u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC38_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0063610u)
+
+/** \brief E, ECC Safety Register */
+#define MC38_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006360Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC38_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063612u)
+
+/** \brief 14, Error Tracking Register */
+#define MC38_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063614u)
+
+/** \brief 16, Error Tracking Register */
+#define MC38_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063616u)
+
+/** \brief 18, Error Tracking Register */
+#define MC38_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063618u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC38_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006361Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC38_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0063604u)
+
+/** \brief 6, Status Register */
+#define MC38_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0063606u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC38_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0063608u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC38_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC38_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC38_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC38_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC38_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC38_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC38_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC38_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC38_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC38_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC38_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC38_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC38_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC38_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC38_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC38_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC38_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC38_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC38_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC38_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC38_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC38_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC38_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC38_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC38_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC38_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC38_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC38_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC38_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC38_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC38_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC38_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC38_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC38_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC38_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC38_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC38_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC38_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC38_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC38_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00636B2u)
+
+/** \brief C, Revision ID Register */
+#define MC38_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006360Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc39
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC39_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0063700u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC39_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0063702u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC39_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0063710u)
+
+/** \brief E, ECC Safety Register */
+#define MC39_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006370Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC39_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063712u)
+
+/** \brief 14, Error Tracking Register */
+#define MC39_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063714u)
+
+/** \brief 16, Error Tracking Register */
+#define MC39_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063716u)
+
+/** \brief 18, Error Tracking Register */
+#define MC39_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063718u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC39_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006371Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC39_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0063704u)
+
+/** \brief 6, Status Register */
+#define MC39_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0063706u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC39_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0063708u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC39_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC39_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC39_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC39_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC39_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC39_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC39_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC39_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC39_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC39_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC39_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC39_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC39_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC39_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC39_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC39_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC39_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC39_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC39_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC39_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC39_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC39_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC39_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC39_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC39_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC39_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC39_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC39_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC39_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC39_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC39_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC39_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC39_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC39_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC39_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC39_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC39_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC39_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC39_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC39_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00637B2u)
+
+/** \brief C, Revision ID Register */
+#define MC39_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006370Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc40
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC40_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0063800u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC40_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0063802u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC40_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0063810u)
+
+/** \brief E, ECC Safety Register */
+#define MC40_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006380Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC40_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063812u)
+
+/** \brief 14, Error Tracking Register */
+#define MC40_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063814u)
+
+/** \brief 16, Error Tracking Register */
+#define MC40_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063816u)
+
+/** \brief 18, Error Tracking Register */
+#define MC40_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063818u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC40_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006381Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC40_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0063804u)
+
+/** \brief 6, Status Register */
+#define MC40_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0063806u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC40_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0063808u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC40_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC40_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC40_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC40_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC40_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC40_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC40_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC40_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC40_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC40_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC40_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC40_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC40_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC40_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC40_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC40_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC40_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC40_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC40_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC40_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC40_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC40_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC40_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC40_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC40_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC40_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC40_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC40_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC40_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC40_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC40_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC40_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC40_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC40_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC40_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC40_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC40_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC40_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC40_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC40_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00638B2u)
+
+/** \brief C, Revision ID Register */
+#define MC40_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006380Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc41
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC41_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0063900u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC41_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0063902u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC41_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0063910u)
+
+/** \brief E, ECC Safety Register */
+#define MC41_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006390Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC41_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063912u)
+
+/** \brief 14, Error Tracking Register */
+#define MC41_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063914u)
+
+/** \brief 16, Error Tracking Register */
+#define MC41_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063916u)
+
+/** \brief 18, Error Tracking Register */
+#define MC41_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063918u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC41_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006391Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC41_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0063904u)
+
+/** \brief 6, Status Register */
+#define MC41_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0063906u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC41_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0063908u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC41_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC41_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC41_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC41_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC41_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC41_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC41_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC41_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC41_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC41_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC41_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC41_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC41_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC41_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC41_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC41_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC41_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC41_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC41_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC41_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC41_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC41_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC41_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC41_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC41_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC41_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC41_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC41_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC41_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC41_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC41_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC41_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC41_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC41_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC41_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC41_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC41_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC41_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC41_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC41_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00639B2u)
+
+/** \brief C, Revision ID Register */
+#define MC41_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006390Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc42
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC42_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0063A00u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC42_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0063A02u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC42_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0063A10u)
+
+/** \brief E, ECC Safety Register */
+#define MC42_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF0063A0Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC42_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063A12u)
+
+/** \brief 14, Error Tracking Register */
+#define MC42_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063A14u)
+
+/** \brief 16, Error Tracking Register */
+#define MC42_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063A16u)
+
+/** \brief 18, Error Tracking Register */
+#define MC42_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063A18u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC42_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063A1Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC42_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0063A04u)
+
+/** \brief 6, Status Register */
+#define MC42_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0063A06u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC42_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0063A08u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC42_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AA0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC42_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AA2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC42_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AB4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC42_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AB6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC42_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AB8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC42_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063ABAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC42_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063ABCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC42_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063ABEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC42_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AC0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC42_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AC2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC42_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AC4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC42_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AC6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC42_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AA4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC42_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AC8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC42_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063ACAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC42_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063ACCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC42_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063ACEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC42_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AD0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC42_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AD2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC42_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AD4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC42_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AD6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC42_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AD8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC42_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063ADAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC42_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AA6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC42_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063ADCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC42_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063ADEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC42_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AE0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC42_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AE2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC42_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AE4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC42_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AE6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC42_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AE8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC42_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AEAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC42_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC42_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AEEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC42_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AA8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC42_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AAAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC42_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC42_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AAEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC42_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AB0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC42_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063AB2u)
+
+/** \brief C, Revision ID Register */
+#define MC42_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF0063A0Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc43
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC43_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0063B00u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC43_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0063B02u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC43_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0063B10u)
+
+/** \brief E, ECC Safety Register */
+#define MC43_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF0063B0Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC43_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063B12u)
+
+/** \brief 14, Error Tracking Register */
+#define MC43_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063B14u)
+
+/** \brief 16, Error Tracking Register */
+#define MC43_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063B16u)
+
+/** \brief 18, Error Tracking Register */
+#define MC43_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063B18u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC43_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063B1Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC43_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0063B04u)
+
+/** \brief 6, Status Register */
+#define MC43_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0063B06u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC43_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0063B08u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC43_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BA0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC43_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BA2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC43_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BB4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC43_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BB6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC43_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BB8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC43_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BBAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC43_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BBCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC43_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BBEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC43_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BC0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC43_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BC2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC43_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BC4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC43_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BC6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC43_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BA4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC43_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BC8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC43_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BCAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC43_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BCCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC43_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BCEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC43_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BD0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC43_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BD2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC43_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BD4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC43_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BD6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC43_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BD8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC43_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BDAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC43_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BA6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC43_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BDCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC43_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BDEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC43_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BE0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC43_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BE2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC43_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BE4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC43_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BE6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC43_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BE8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC43_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BEAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC43_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC43_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BEEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC43_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BA8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC43_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BAAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC43_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC43_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BAEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC43_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BB0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC43_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063BB2u)
+
+/** \brief C, Revision ID Register */
+#define MC43_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF0063B0Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc44
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC44_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0063C00u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC44_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0063C02u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC44_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0063C10u)
+
+/** \brief E, ECC Safety Register */
+#define MC44_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF0063C0Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC44_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063C12u)
+
+/** \brief 14, Error Tracking Register */
+#define MC44_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063C14u)
+
+/** \brief 16, Error Tracking Register */
+#define MC44_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063C16u)
+
+/** \brief 18, Error Tracking Register */
+#define MC44_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063C18u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC44_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063C1Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC44_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0063C04u)
+
+/** \brief 6, Status Register */
+#define MC44_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0063C06u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC44_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0063C08u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC44_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CA0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC44_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CA2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC44_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CB4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC44_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CB6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC44_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CB8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC44_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CBAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC44_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CBCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC44_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CBEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC44_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CC0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC44_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CC2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC44_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CC4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC44_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CC6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC44_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CA4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC44_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CC8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC44_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CCAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC44_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CCCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC44_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CCEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC44_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CD0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC44_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CD2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC44_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CD4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC44_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CD6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC44_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CD8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC44_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CDAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC44_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CA6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC44_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CDCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC44_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CDEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC44_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CE0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC44_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CE2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC44_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CE4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC44_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CE6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC44_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CE8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC44_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CEAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC44_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC44_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CEEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC44_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CA8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC44_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CAAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC44_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC44_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CAEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC44_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CB0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC44_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063CB2u)
+
+/** \brief C, Revision ID Register */
+#define MC44_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF0063C0Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc45
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC45_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0063D00u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC45_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0063D02u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC45_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0063D10u)
+
+/** \brief E, ECC Safety Register */
+#define MC45_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF0063D0Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC45_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063D12u)
+
+/** \brief 14, Error Tracking Register */
+#define MC45_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063D14u)
+
+/** \brief 16, Error Tracking Register */
+#define MC45_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063D16u)
+
+/** \brief 18, Error Tracking Register */
+#define MC45_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063D18u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC45_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063D1Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC45_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0063D04u)
+
+/** \brief 6, Status Register */
+#define MC45_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0063D06u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC45_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0063D08u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC45_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DA0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC45_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DA2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC45_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DB4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC45_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DB6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC45_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DB8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC45_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DBAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC45_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DBCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC45_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DBEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC45_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DC0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC45_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DC2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC45_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DC4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC45_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DC6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC45_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DA4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC45_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DC8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC45_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DCAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC45_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DCCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC45_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DCEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC45_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DD0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC45_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DD2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC45_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DD4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC45_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DD6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC45_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DD8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC45_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DDAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC45_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DA6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC45_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DDCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC45_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DDEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC45_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DE0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC45_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DE2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC45_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DE4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC45_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DE6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC45_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DE8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC45_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DEAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC45_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC45_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DEEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC45_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DA8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC45_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DAAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC45_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC45_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DAEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC45_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DB0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC45_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063DB2u)
+
+/** \brief C, Revision ID Register */
+#define MC45_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF0063D0Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc46
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC46_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0063E00u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC46_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0063E02u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC46_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0063E10u)
+
+/** \brief E, ECC Safety Register */
+#define MC46_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF0063E0Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC46_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063E12u)
+
+/** \brief 14, Error Tracking Register */
+#define MC46_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063E14u)
+
+/** \brief 16, Error Tracking Register */
+#define MC46_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063E16u)
+
+/** \brief 18, Error Tracking Register */
+#define MC46_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063E18u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC46_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063E1Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC46_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0063E04u)
+
+/** \brief 6, Status Register */
+#define MC46_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0063E06u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC46_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0063E08u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC46_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EA0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC46_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EA2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC46_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EB4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC46_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EB6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC46_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EB8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC46_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EBAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC46_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EBCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC46_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EBEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC46_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EC0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC46_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EC2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC46_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EC4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC46_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EC6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC46_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EA4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC46_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EC8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC46_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063ECAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC46_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063ECCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC46_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063ECEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC46_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063ED0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC46_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063ED2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC46_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063ED4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC46_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063ED6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC46_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063ED8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC46_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EDAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC46_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EA6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC46_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EDCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC46_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EDEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC46_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EE0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC46_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EE2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC46_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EE4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC46_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EE6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC46_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EE8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC46_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EEAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC46_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC46_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EEEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC46_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EA8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC46_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EAAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC46_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC46_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EAEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC46_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EB0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC46_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063EB2u)
+
+/** \brief C, Revision ID Register */
+#define MC46_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF0063E0Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc47
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC47_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0063F00u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC47_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0063F02u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC47_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0063F10u)
+
+/** \brief E, ECC Safety Register */
+#define MC47_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF0063F0Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC47_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063F12u)
+
+/** \brief 14, Error Tracking Register */
+#define MC47_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063F14u)
+
+/** \brief 16, Error Tracking Register */
+#define MC47_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063F16u)
+
+/** \brief 18, Error Tracking Register */
+#define MC47_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063F18u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC47_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0063F1Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC47_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0063F04u)
+
+/** \brief 6, Status Register */
+#define MC47_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0063F06u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC47_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0063F08u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC47_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FA0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC47_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FA2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC47_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FB4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC47_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FB6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC47_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FB8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC47_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FBAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC47_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FBCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC47_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FBEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC47_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FC0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC47_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FC2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC47_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FC4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC47_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FC6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC47_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FA4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC47_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FC8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC47_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FCAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC47_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FCCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC47_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FCEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC47_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FD0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC47_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FD2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC47_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FD4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC47_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FD6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC47_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FD8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC47_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FDAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC47_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FA6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC47_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FDCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC47_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FDEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC47_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FE0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC47_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FE2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC47_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FE4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC47_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FE6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC47_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FE8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC47_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FEAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC47_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC47_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FEEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC47_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FA8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC47_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FAAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC47_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC47_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FAEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC47_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FB0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC47_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0063FB2u)
+
+/** \brief C, Revision ID Register */
+#define MC47_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF0063F0Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc48
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC48_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0064000u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC48_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0064002u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC48_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0064010u)
+
+/** \brief E, ECC Safety Register */
+#define MC48_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006400Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC48_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064012u)
+
+/** \brief 14, Error Tracking Register */
+#define MC48_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064014u)
+
+/** \brief 16, Error Tracking Register */
+#define MC48_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064016u)
+
+/** \brief 18, Error Tracking Register */
+#define MC48_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064018u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC48_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006401Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC48_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0064004u)
+
+/** \brief 6, Status Register */
+#define MC48_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0064006u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC48_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0064008u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC48_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC48_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC48_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC48_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC48_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC48_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC48_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC48_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC48_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC48_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC48_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC48_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC48_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC48_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC48_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC48_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC48_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC48_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC48_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC48_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC48_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC48_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC48_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC48_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC48_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC48_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC48_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC48_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC48_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC48_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC48_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC48_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC48_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC48_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC48_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC48_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC48_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC48_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC48_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC48_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00640B2u)
+
+/** \brief C, Revision ID Register */
+#define MC48_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006400Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc49
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC49_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0064100u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC49_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0064102u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC49_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0064110u)
+
+/** \brief E, ECC Safety Register */
+#define MC49_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006410Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC49_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064112u)
+
+/** \brief 14, Error Tracking Register */
+#define MC49_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064114u)
+
+/** \brief 16, Error Tracking Register */
+#define MC49_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064116u)
+
+/** \brief 18, Error Tracking Register */
+#define MC49_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064118u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC49_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006411Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC49_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0064104u)
+
+/** \brief 6, Status Register */
+#define MC49_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0064106u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC49_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0064108u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC49_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC49_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC49_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC49_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC49_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC49_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC49_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC49_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC49_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC49_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC49_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC49_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC49_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC49_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC49_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC49_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC49_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC49_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC49_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC49_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC49_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC49_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC49_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC49_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC49_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC49_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC49_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC49_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC49_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC49_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC49_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC49_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC49_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC49_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC49_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC49_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC49_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC49_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC49_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC49_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00641B2u)
+
+/** \brief C, Revision ID Register */
+#define MC49_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006410Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc50
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC50_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0064200u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC50_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0064202u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC50_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0064210u)
+
+/** \brief E, ECC Safety Register */
+#define MC50_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006420Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC50_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064212u)
+
+/** \brief 14, Error Tracking Register */
+#define MC50_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064214u)
+
+/** \brief 16, Error Tracking Register */
+#define MC50_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064216u)
+
+/** \brief 18, Error Tracking Register */
+#define MC50_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064218u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC50_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006421Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC50_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0064204u)
+
+/** \brief 6, Status Register */
+#define MC50_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0064206u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC50_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0064208u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC50_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC50_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC50_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC50_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC50_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC50_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC50_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC50_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC50_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC50_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC50_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC50_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC50_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC50_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC50_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC50_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC50_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC50_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC50_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC50_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC50_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC50_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC50_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC50_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC50_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC50_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC50_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC50_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC50_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC50_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC50_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC50_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC50_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC50_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC50_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC50_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC50_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC50_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC50_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC50_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00642B2u)
+
+/** \brief C, Revision ID Register */
+#define MC50_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006420Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc51
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC51_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0064300u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC51_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0064302u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC51_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0064310u)
+
+/** \brief E, ECC Safety Register */
+#define MC51_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006430Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC51_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064312u)
+
+/** \brief 14, Error Tracking Register */
+#define MC51_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064314u)
+
+/** \brief 16, Error Tracking Register */
+#define MC51_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064316u)
+
+/** \brief 18, Error Tracking Register */
+#define MC51_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064318u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC51_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006431Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC51_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0064304u)
+
+/** \brief 6, Status Register */
+#define MC51_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0064306u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC51_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0064308u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC51_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC51_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC51_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC51_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC51_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC51_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC51_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC51_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC51_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC51_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC51_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC51_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC51_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC51_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC51_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC51_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC51_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC51_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC51_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC51_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC51_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC51_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC51_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC51_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC51_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC51_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC51_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC51_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC51_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC51_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC51_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC51_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC51_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC51_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC51_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC51_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC51_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC51_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC51_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC51_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00643B2u)
+
+/** \brief C, Revision ID Register */
+#define MC51_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006430Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc52
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC52_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0064400u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC52_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0064402u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC52_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0064410u)
+
+/** \brief E, ECC Safety Register */
+#define MC52_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006440Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC52_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064412u)
+
+/** \brief 14, Error Tracking Register */
+#define MC52_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064414u)
+
+/** \brief 16, Error Tracking Register */
+#define MC52_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064416u)
+
+/** \brief 18, Error Tracking Register */
+#define MC52_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064418u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC52_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006441Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC52_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0064404u)
+
+/** \brief 6, Status Register */
+#define MC52_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0064406u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC52_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0064408u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC52_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC52_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC52_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC52_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC52_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC52_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC52_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC52_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC52_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC52_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC52_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC52_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC52_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC52_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC52_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC52_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC52_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC52_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC52_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC52_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC52_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC52_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC52_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC52_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC52_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC52_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC52_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC52_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC52_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC52_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC52_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC52_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC52_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC52_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC52_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC52_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC52_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC52_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC52_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC52_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00644B2u)
+
+/** \brief C, Revision ID Register */
+#define MC52_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006440Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc53
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC53_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0064500u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC53_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0064502u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC53_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0064510u)
+
+/** \brief E, ECC Safety Register */
+#define MC53_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006450Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC53_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064512u)
+
+/** \brief 14, Error Tracking Register */
+#define MC53_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064514u)
+
+/** \brief 16, Error Tracking Register */
+#define MC53_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064516u)
+
+/** \brief 18, Error Tracking Register */
+#define MC53_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064518u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC53_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006451Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC53_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0064504u)
+
+/** \brief 6, Status Register */
+#define MC53_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0064506u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC53_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0064508u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC53_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC53_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC53_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC53_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC53_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC53_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC53_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC53_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC53_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC53_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC53_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC53_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC53_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC53_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC53_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC53_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC53_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC53_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC53_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC53_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC53_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC53_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC53_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC53_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC53_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC53_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC53_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC53_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC53_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC53_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC53_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC53_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC53_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC53_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC53_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC53_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC53_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC53_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC53_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC53_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00645B2u)
+
+/** \brief C, Revision ID Register */
+#define MC53_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006450Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc54
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC54_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0064600u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC54_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0064602u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC54_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0064610u)
+
+/** \brief E, ECC Safety Register */
+#define MC54_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006460Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC54_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064612u)
+
+/** \brief 14, Error Tracking Register */
+#define MC54_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064614u)
+
+/** \brief 16, Error Tracking Register */
+#define MC54_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064616u)
+
+/** \brief 18, Error Tracking Register */
+#define MC54_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064618u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC54_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006461Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC54_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0064604u)
+
+/** \brief 6, Status Register */
+#define MC54_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0064606u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC54_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0064608u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC54_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC54_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC54_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC54_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC54_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC54_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC54_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC54_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC54_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC54_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC54_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC54_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC54_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC54_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC54_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC54_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC54_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC54_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC54_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC54_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC54_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC54_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC54_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC54_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC54_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC54_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC54_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC54_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC54_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC54_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC54_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC54_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC54_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC54_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC54_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC54_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC54_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC54_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC54_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC54_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00646B2u)
+
+/** \brief C, Revision ID Register */
+#define MC54_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006460Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc55
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC55_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0064700u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC55_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0064702u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC55_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0064710u)
+
+/** \brief E, ECC Safety Register */
+#define MC55_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006470Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC55_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064712u)
+
+/** \brief 14, Error Tracking Register */
+#define MC55_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064714u)
+
+/** \brief 16, Error Tracking Register */
+#define MC55_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064716u)
+
+/** \brief 18, Error Tracking Register */
+#define MC55_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064718u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC55_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006471Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC55_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0064704u)
+
+/** \brief 6, Status Register */
+#define MC55_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0064706u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC55_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0064708u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC55_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC55_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC55_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC55_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC55_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC55_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC55_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC55_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC55_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC55_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC55_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC55_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC55_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC55_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC55_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC55_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC55_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC55_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC55_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC55_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC55_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC55_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC55_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC55_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC55_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC55_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC55_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC55_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC55_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC55_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC55_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC55_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC55_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC55_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC55_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC55_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC55_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC55_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC55_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC55_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00647B2u)
+
+/** \brief C, Revision ID Register */
+#define MC55_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006470Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc56
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC56_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0064800u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC56_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0064802u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC56_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0064810u)
+
+/** \brief E, ECC Safety Register */
+#define MC56_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006480Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC56_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064812u)
+
+/** \brief 14, Error Tracking Register */
+#define MC56_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064814u)
+
+/** \brief 16, Error Tracking Register */
+#define MC56_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064816u)
+
+/** \brief 18, Error Tracking Register */
+#define MC56_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064818u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC56_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006481Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC56_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0064804u)
+
+/** \brief 6, Status Register */
+#define MC56_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0064806u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC56_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0064808u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC56_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC56_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC56_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC56_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC56_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC56_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC56_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC56_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC56_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC56_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC56_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC56_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC56_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC56_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC56_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC56_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC56_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC56_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC56_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC56_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC56_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC56_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC56_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC56_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC56_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC56_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC56_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC56_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC56_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC56_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC56_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC56_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC56_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC56_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC56_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC56_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC56_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC56_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC56_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC56_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00648B2u)
+
+/** \brief C, Revision ID Register */
+#define MC56_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006480Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc57
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC57_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0064900u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC57_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0064902u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC57_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0064910u)
+
+/** \brief E, ECC Safety Register */
+#define MC57_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006490Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC57_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064912u)
+
+/** \brief 14, Error Tracking Register */
+#define MC57_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064914u)
+
+/** \brief 16, Error Tracking Register */
+#define MC57_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064916u)
+
+/** \brief 18, Error Tracking Register */
+#define MC57_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064918u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC57_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006491Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC57_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0064904u)
+
+/** \brief 6, Status Register */
+#define MC57_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0064906u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC57_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0064908u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC57_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC57_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC57_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC57_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC57_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC57_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC57_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC57_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC57_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC57_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC57_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC57_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC57_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC57_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC57_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC57_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC57_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC57_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC57_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC57_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC57_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC57_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC57_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC57_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC57_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC57_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC57_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC57_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC57_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC57_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC57_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC57_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC57_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC57_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC57_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC57_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC57_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC57_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC57_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC57_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00649B2u)
+
+/** \brief C, Revision ID Register */
+#define MC57_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006490Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc58
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC58_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0064A00u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC58_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0064A02u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC58_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0064A10u)
+
+/** \brief E, ECC Safety Register */
+#define MC58_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF0064A0Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC58_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064A12u)
+
+/** \brief 14, Error Tracking Register */
+#define MC58_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064A14u)
+
+/** \brief 16, Error Tracking Register */
+#define MC58_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064A16u)
+
+/** \brief 18, Error Tracking Register */
+#define MC58_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064A18u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC58_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064A1Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC58_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0064A04u)
+
+/** \brief 6, Status Register */
+#define MC58_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0064A06u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC58_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0064A08u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC58_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AA0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC58_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AA2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC58_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AB4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC58_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AB6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC58_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AB8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC58_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064ABAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC58_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064ABCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC58_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064ABEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC58_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AC0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC58_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AC2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC58_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AC4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC58_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AC6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC58_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AA4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC58_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AC8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC58_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064ACAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC58_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064ACCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC58_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064ACEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC58_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AD0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC58_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AD2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC58_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AD4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC58_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AD6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC58_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AD8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC58_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064ADAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC58_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AA6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC58_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064ADCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC58_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064ADEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC58_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AE0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC58_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AE2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC58_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AE4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC58_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AE6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC58_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AE8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC58_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AEAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC58_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC58_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AEEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC58_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AA8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC58_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AAAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC58_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC58_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AAEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC58_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AB0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC58_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064AB2u)
+
+/** \brief C, Revision ID Register */
+#define MC58_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF0064A0Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc59
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC59_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0064B00u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC59_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0064B02u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC59_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0064B10u)
+
+/** \brief E, ECC Safety Register */
+#define MC59_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF0064B0Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC59_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064B12u)
+
+/** \brief 14, Error Tracking Register */
+#define MC59_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064B14u)
+
+/** \brief 16, Error Tracking Register */
+#define MC59_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064B16u)
+
+/** \brief 18, Error Tracking Register */
+#define MC59_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064B18u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC59_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064B1Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC59_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0064B04u)
+
+/** \brief 6, Status Register */
+#define MC59_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0064B06u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC59_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0064B08u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC59_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BA0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC59_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BA2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC59_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BB4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC59_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BB6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC59_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BB8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC59_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BBAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC59_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BBCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC59_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BBEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC59_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BC0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC59_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BC2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC59_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BC4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC59_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BC6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC59_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BA4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC59_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BC8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC59_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BCAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC59_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BCCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC59_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BCEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC59_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BD0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC59_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BD2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC59_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BD4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC59_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BD6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC59_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BD8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC59_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BDAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC59_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BA6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC59_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BDCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC59_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BDEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC59_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BE0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC59_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BE2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC59_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BE4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC59_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BE6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC59_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BE8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC59_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BEAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC59_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC59_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BEEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC59_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BA8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC59_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BAAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC59_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC59_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BAEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC59_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BB0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC59_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064BB2u)
+
+/** \brief C, Revision ID Register */
+#define MC59_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF0064B0Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc60
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC60_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0064C00u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC60_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0064C02u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC60_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0064C10u)
+
+/** \brief E, ECC Safety Register */
+#define MC60_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF0064C0Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC60_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064C12u)
+
+/** \brief 14, Error Tracking Register */
+#define MC60_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064C14u)
+
+/** \brief 16, Error Tracking Register */
+#define MC60_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064C16u)
+
+/** \brief 18, Error Tracking Register */
+#define MC60_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064C18u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC60_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064C1Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC60_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0064C04u)
+
+/** \brief 6, Status Register */
+#define MC60_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0064C06u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC60_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0064C08u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC60_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CA0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC60_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CA2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC60_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CB4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC60_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CB6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC60_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CB8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC60_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CBAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC60_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CBCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC60_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CBEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC60_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CC0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC60_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CC2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC60_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CC4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC60_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CC6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC60_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CA4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC60_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CC8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC60_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CCAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC60_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CCCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC60_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CCEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC60_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CD0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC60_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CD2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC60_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CD4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC60_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CD6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC60_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CD8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC60_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CDAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC60_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CA6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC60_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CDCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC60_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CDEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC60_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CE0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC60_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CE2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC60_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CE4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC60_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CE6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC60_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CE8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC60_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CEAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC60_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC60_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CEEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC60_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CA8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC60_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CAAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC60_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC60_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CAEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC60_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CB0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC60_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064CB2u)
+
+/** \brief C, Revision ID Register */
+#define MC60_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF0064C0Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc61
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC61_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0064D00u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC61_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0064D02u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC61_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0064D10u)
+
+/** \brief E, ECC Safety Register */
+#define MC61_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF0064D0Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC61_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064D12u)
+
+/** \brief 14, Error Tracking Register */
+#define MC61_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064D14u)
+
+/** \brief 16, Error Tracking Register */
+#define MC61_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064D16u)
+
+/** \brief 18, Error Tracking Register */
+#define MC61_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064D18u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC61_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064D1Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC61_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0064D04u)
+
+/** \brief 6, Status Register */
+#define MC61_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0064D06u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC61_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0064D08u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC61_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DA0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC61_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DA2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC61_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DB4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC61_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DB6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC61_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DB8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC61_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DBAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC61_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DBCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC61_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DBEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC61_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DC0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC61_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DC2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC61_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DC4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC61_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DC6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC61_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DA4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC61_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DC8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC61_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DCAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC61_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DCCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC61_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DCEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC61_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DD0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC61_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DD2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC61_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DD4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC61_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DD6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC61_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DD8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC61_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DDAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC61_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DA6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC61_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DDCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC61_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DDEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC61_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DE0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC61_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DE2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC61_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DE4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC61_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DE6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC61_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DE8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC61_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DEAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC61_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC61_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DEEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC61_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DA8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC61_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DAAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC61_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC61_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DAEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC61_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DB0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC61_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064DB2u)
+
+/** \brief C, Revision ID Register */
+#define MC61_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF0064D0Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc62
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC62_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0064E00u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC62_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0064E02u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC62_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0064E10u)
+
+/** \brief E, ECC Safety Register */
+#define MC62_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF0064E0Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC62_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064E12u)
+
+/** \brief 14, Error Tracking Register */
+#define MC62_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064E14u)
+
+/** \brief 16, Error Tracking Register */
+#define MC62_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064E16u)
+
+/** \brief 18, Error Tracking Register */
+#define MC62_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064E18u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC62_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064E1Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC62_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0064E04u)
+
+/** \brief 6, Status Register */
+#define MC62_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0064E06u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC62_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0064E08u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC62_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EA0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC62_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EA2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC62_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EB4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC62_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EB6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC62_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EB8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC62_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EBAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC62_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EBCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC62_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EBEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC62_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EC0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC62_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EC2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC62_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EC4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC62_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EC6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC62_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EA4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC62_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EC8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC62_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064ECAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC62_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064ECCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC62_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064ECEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC62_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064ED0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC62_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064ED2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC62_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064ED4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC62_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064ED6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC62_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064ED8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC62_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EDAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC62_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EA6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC62_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EDCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC62_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EDEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC62_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EE0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC62_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EE2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC62_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EE4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC62_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EE6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC62_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EE8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC62_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EEAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC62_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC62_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EEEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC62_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EA8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC62_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EAAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC62_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC62_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EAEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC62_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EB0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC62_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064EB2u)
+
+/** \brief C, Revision ID Register */
+#define MC62_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF0064E0Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc63
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC63_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0064F00u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC63_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0064F02u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC63_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0064F10u)
+
+/** \brief E, ECC Safety Register */
+#define MC63_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF0064F0Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC63_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064F12u)
+
+/** \brief 14, Error Tracking Register */
+#define MC63_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064F14u)
+
+/** \brief 16, Error Tracking Register */
+#define MC63_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064F16u)
+
+/** \brief 18, Error Tracking Register */
+#define MC63_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064F18u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC63_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0064F1Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC63_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0064F04u)
+
+/** \brief 6, Status Register */
+#define MC63_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0064F06u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC63_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0064F08u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC63_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FA0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC63_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FA2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC63_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FB4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC63_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FB6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC63_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FB8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC63_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FBAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC63_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FBCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC63_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FBEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC63_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FC0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC63_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FC2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC63_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FC4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC63_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FC6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC63_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FA4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC63_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FC8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC63_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FCAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC63_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FCCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC63_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FCEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC63_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FD0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC63_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FD2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC63_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FD4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC63_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FD6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC63_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FD8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC63_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FDAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC63_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FA6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC63_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FDCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC63_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FDEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC63_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FE0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC63_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FE2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC63_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FE4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC63_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FE6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC63_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FE8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC63_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FEAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC63_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC63_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FEEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC63_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FA8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC63_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FAAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC63_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC63_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FAEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC63_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FB0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC63_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0064FB2u)
+
+/** \brief C, Revision ID Register */
+#define MC63_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF0064F0Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc64
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC64_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0065000u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC64_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0065002u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC64_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0065010u)
+
+/** \brief E, ECC Safety Register */
+#define MC64_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006500Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC64_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065012u)
+
+/** \brief 14, Error Tracking Register */
+#define MC64_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065014u)
+
+/** \brief 16, Error Tracking Register */
+#define MC64_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065016u)
+
+/** \brief 18, Error Tracking Register */
+#define MC64_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065018u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC64_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006501Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC64_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0065004u)
+
+/** \brief 6, Status Register */
+#define MC64_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0065006u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC64_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0065008u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC64_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC64_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC64_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC64_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC64_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC64_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC64_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC64_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC64_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC64_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC64_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC64_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC64_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC64_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC64_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC64_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC64_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC64_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC64_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC64_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC64_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC64_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC64_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC64_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC64_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC64_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC64_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC64_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC64_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC64_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC64_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC64_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC64_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC64_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC64_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC64_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC64_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC64_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC64_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC64_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00650B2u)
+
+/** \brief C, Revision ID Register */
+#define MC64_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006500Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc65
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC65_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0065100u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC65_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0065102u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC65_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0065110u)
+
+/** \brief E, ECC Safety Register */
+#define MC65_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006510Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC65_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065112u)
+
+/** \brief 14, Error Tracking Register */
+#define MC65_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065114u)
+
+/** \brief 16, Error Tracking Register */
+#define MC65_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065116u)
+
+/** \brief 18, Error Tracking Register */
+#define MC65_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065118u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC65_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006511Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC65_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0065104u)
+
+/** \brief 6, Status Register */
+#define MC65_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0065106u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC65_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0065108u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC65_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC65_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC65_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC65_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC65_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC65_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC65_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC65_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC65_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC65_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC65_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC65_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC65_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC65_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC65_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC65_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC65_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC65_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC65_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC65_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC65_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC65_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC65_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC65_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC65_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC65_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC65_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC65_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC65_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC65_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC65_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC65_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC65_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC65_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC65_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC65_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC65_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC65_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC65_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC65_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00651B2u)
+
+/** \brief C, Revision ID Register */
+#define MC65_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006510Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc66
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC66_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0065200u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC66_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0065202u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC66_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0065210u)
+
+/** \brief E, ECC Safety Register */
+#define MC66_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006520Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC66_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065212u)
+
+/** \brief 14, Error Tracking Register */
+#define MC66_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065214u)
+
+/** \brief 16, Error Tracking Register */
+#define MC66_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065216u)
+
+/** \brief 18, Error Tracking Register */
+#define MC66_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065218u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC66_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006521Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC66_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0065204u)
+
+/** \brief 6, Status Register */
+#define MC66_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0065206u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC66_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0065208u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC66_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC66_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC66_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC66_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC66_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC66_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC66_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC66_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC66_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC66_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC66_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC66_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC66_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC66_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC66_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC66_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC66_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC66_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC66_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC66_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC66_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC66_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC66_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC66_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC66_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC66_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC66_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC66_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC66_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC66_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC66_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC66_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC66_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC66_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC66_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC66_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC66_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC66_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC66_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC66_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00652B2u)
+
+/** \brief C, Revision ID Register */
+#define MC66_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006520Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc67
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC67_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0065300u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC67_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0065302u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC67_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0065310u)
+
+/** \brief E, ECC Safety Register */
+#define MC67_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006530Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC67_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065312u)
+
+/** \brief 14, Error Tracking Register */
+#define MC67_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065314u)
+
+/** \brief 16, Error Tracking Register */
+#define MC67_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065316u)
+
+/** \brief 18, Error Tracking Register */
+#define MC67_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065318u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC67_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006531Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC67_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0065304u)
+
+/** \brief 6, Status Register */
+#define MC67_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0065306u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC67_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0065308u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC67_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC67_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC67_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC67_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC67_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC67_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC67_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC67_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC67_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC67_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC67_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC67_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC67_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC67_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC67_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC67_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC67_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC67_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC67_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC67_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC67_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC67_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC67_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC67_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC67_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC67_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC67_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC67_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC67_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC67_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC67_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC67_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC67_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC67_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC67_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC67_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC67_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC67_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC67_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC67_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00653B2u)
+
+/** \brief C, Revision ID Register */
+#define MC67_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006530Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc68
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC68_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0065400u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC68_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0065402u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC68_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0065410u)
+
+/** \brief E, ECC Safety Register */
+#define MC68_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006540Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC68_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065412u)
+
+/** \brief 14, Error Tracking Register */
+#define MC68_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065414u)
+
+/** \brief 16, Error Tracking Register */
+#define MC68_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065416u)
+
+/** \brief 18, Error Tracking Register */
+#define MC68_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065418u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC68_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006541Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC68_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0065404u)
+
+/** \brief 6, Status Register */
+#define MC68_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0065406u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC68_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0065408u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC68_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC68_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC68_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC68_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC68_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC68_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC68_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC68_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC68_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC68_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC68_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC68_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC68_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC68_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC68_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC68_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC68_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC68_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC68_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC68_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC68_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC68_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC68_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC68_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC68_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC68_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC68_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC68_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC68_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC68_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC68_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC68_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC68_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC68_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC68_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC68_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC68_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC68_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC68_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC68_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00654B2u)
+
+/** \brief C, Revision ID Register */
+#define MC68_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006540Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc69
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC69_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0065500u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC69_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0065502u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC69_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0065510u)
+
+/** \brief E, ECC Safety Register */
+#define MC69_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006550Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC69_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065512u)
+
+/** \brief 14, Error Tracking Register */
+#define MC69_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065514u)
+
+/** \brief 16, Error Tracking Register */
+#define MC69_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065516u)
+
+/** \brief 18, Error Tracking Register */
+#define MC69_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065518u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC69_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006551Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC69_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0065504u)
+
+/** \brief 6, Status Register */
+#define MC69_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0065506u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC69_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0065508u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC69_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC69_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC69_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC69_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC69_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC69_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC69_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC69_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC69_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC69_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC69_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC69_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC69_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC69_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC69_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC69_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC69_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC69_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC69_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC69_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC69_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC69_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC69_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC69_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC69_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC69_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC69_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC69_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC69_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC69_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC69_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC69_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC69_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC69_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC69_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC69_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC69_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC69_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC69_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC69_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00655B2u)
+
+/** \brief C, Revision ID Register */
+#define MC69_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006550Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc70
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC70_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0065600u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC70_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0065602u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC70_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0065610u)
+
+/** \brief E, ECC Safety Register */
+#define MC70_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006560Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC70_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065612u)
+
+/** \brief 14, Error Tracking Register */
+#define MC70_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065614u)
+
+/** \brief 16, Error Tracking Register */
+#define MC70_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065616u)
+
+/** \brief 18, Error Tracking Register */
+#define MC70_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065618u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC70_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006561Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC70_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0065604u)
+
+/** \brief 6, Status Register */
+#define MC70_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0065606u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC70_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0065608u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC70_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC70_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC70_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC70_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC70_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC70_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC70_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC70_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC70_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC70_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC70_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC70_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC70_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC70_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC70_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC70_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC70_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC70_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC70_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC70_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC70_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC70_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC70_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC70_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC70_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC70_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC70_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC70_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC70_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC70_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC70_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC70_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC70_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC70_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC70_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC70_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC70_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC70_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC70_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC70_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00656B2u)
+
+/** \brief C, Revision ID Register */
+#define MC70_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006560Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc71
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC71_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0065700u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC71_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0065702u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC71_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0065710u)
+
+/** \brief E, ECC Safety Register */
+#define MC71_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006570Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC71_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065712u)
+
+/** \brief 14, Error Tracking Register */
+#define MC71_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065714u)
+
+/** \brief 16, Error Tracking Register */
+#define MC71_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065716u)
+
+/** \brief 18, Error Tracking Register */
+#define MC71_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065718u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC71_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006571Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC71_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0065704u)
+
+/** \brief 6, Status Register */
+#define MC71_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0065706u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC71_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0065708u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC71_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC71_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC71_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC71_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC71_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC71_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC71_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC71_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC71_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC71_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC71_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC71_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC71_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC71_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC71_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC71_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC71_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC71_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC71_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC71_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC71_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC71_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC71_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC71_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC71_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC71_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC71_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC71_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC71_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC71_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC71_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC71_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC71_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC71_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC71_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC71_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC71_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC71_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC71_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC71_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00657B2u)
+
+/** \brief C, Revision ID Register */
+#define MC71_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006570Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc72
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC72_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0065800u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC72_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0065802u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC72_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0065810u)
+
+/** \brief E, ECC Safety Register */
+#define MC72_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006580Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC72_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065812u)
+
+/** \brief 14, Error Tracking Register */
+#define MC72_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065814u)
+
+/** \brief 16, Error Tracking Register */
+#define MC72_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065816u)
+
+/** \brief 18, Error Tracking Register */
+#define MC72_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065818u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC72_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006581Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC72_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0065804u)
+
+/** \brief 6, Status Register */
+#define MC72_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0065806u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC72_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0065808u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC72_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC72_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC72_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC72_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC72_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC72_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC72_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC72_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC72_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC72_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC72_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC72_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC72_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC72_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC72_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC72_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC72_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC72_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC72_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC72_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC72_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC72_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC72_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC72_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC72_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC72_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC72_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC72_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC72_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC72_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC72_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC72_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC72_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC72_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC72_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC72_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC72_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC72_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC72_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC72_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00658B2u)
+
+/** \brief C, Revision ID Register */
+#define MC72_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006580Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc73
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC73_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0065900u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC73_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0065902u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC73_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0065910u)
+
+/** \brief E, ECC Safety Register */
+#define MC73_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006590Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC73_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065912u)
+
+/** \brief 14, Error Tracking Register */
+#define MC73_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065914u)
+
+/** \brief 16, Error Tracking Register */
+#define MC73_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065916u)
+
+/** \brief 18, Error Tracking Register */
+#define MC73_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065918u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC73_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006591Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC73_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0065904u)
+
+/** \brief 6, Status Register */
+#define MC73_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0065906u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC73_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0065908u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC73_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC73_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC73_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC73_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC73_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC73_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC73_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC73_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC73_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC73_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC73_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC73_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC73_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC73_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC73_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC73_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC73_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC73_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC73_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC73_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC73_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC73_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC73_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC73_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC73_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC73_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC73_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC73_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC73_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC73_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC73_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC73_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC73_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC73_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC73_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC73_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC73_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC73_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC73_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC73_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00659B2u)
+
+/** \brief C, Revision ID Register */
+#define MC73_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006590Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc74
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC74_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0065A00u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC74_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0065A02u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC74_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0065A10u)
+
+/** \brief E, ECC Safety Register */
+#define MC74_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF0065A0Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC74_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065A12u)
+
+/** \brief 14, Error Tracking Register */
+#define MC74_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065A14u)
+
+/** \brief 16, Error Tracking Register */
+#define MC74_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065A16u)
+
+/** \brief 18, Error Tracking Register */
+#define MC74_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065A18u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC74_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065A1Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC74_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0065A04u)
+
+/** \brief 6, Status Register */
+#define MC74_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0065A06u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC74_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0065A08u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC74_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AA0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC74_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AA2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC74_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AB4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC74_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AB6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC74_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AB8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC74_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065ABAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC74_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065ABCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC74_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065ABEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC74_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AC0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC74_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AC2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC74_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AC4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC74_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AC6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC74_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AA4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC74_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AC8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC74_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065ACAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC74_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065ACCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC74_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065ACEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC74_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AD0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC74_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AD2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC74_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AD4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC74_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AD6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC74_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AD8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC74_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065ADAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC74_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AA6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC74_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065ADCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC74_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065ADEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC74_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AE0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC74_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AE2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC74_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AE4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC74_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AE6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC74_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AE8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC74_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AEAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC74_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC74_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AEEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC74_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AA8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC74_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AAAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC74_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC74_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AAEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC74_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AB0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC74_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065AB2u)
+
+/** \brief C, Revision ID Register */
+#define MC74_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF0065A0Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc75
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC75_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0065B00u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC75_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0065B02u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC75_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0065B10u)
+
+/** \brief E, ECC Safety Register */
+#define MC75_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF0065B0Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC75_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065B12u)
+
+/** \brief 14, Error Tracking Register */
+#define MC75_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065B14u)
+
+/** \brief 16, Error Tracking Register */
+#define MC75_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065B16u)
+
+/** \brief 18, Error Tracking Register */
+#define MC75_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065B18u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC75_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065B1Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC75_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0065B04u)
+
+/** \brief 6, Status Register */
+#define MC75_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0065B06u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC75_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0065B08u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC75_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BA0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC75_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BA2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC75_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BB4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC75_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BB6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC75_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BB8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC75_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BBAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC75_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BBCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC75_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BBEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC75_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BC0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC75_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BC2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC75_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BC4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC75_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BC6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC75_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BA4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC75_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BC8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC75_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BCAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC75_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BCCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC75_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BCEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC75_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BD0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC75_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BD2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC75_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BD4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC75_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BD6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC75_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BD8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC75_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BDAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC75_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BA6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC75_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BDCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC75_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BDEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC75_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BE0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC75_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BE2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC75_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BE4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC75_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BE6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC75_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BE8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC75_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BEAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC75_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC75_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BEEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC75_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BA8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC75_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BAAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC75_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC75_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BAEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC75_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BB0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC75_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065BB2u)
+
+/** \brief C, Revision ID Register */
+#define MC75_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF0065B0Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc76
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC76_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0065C00u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC76_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0065C02u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC76_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0065C10u)
+
+/** \brief E, ECC Safety Register */
+#define MC76_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF0065C0Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC76_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065C12u)
+
+/** \brief 14, Error Tracking Register */
+#define MC76_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065C14u)
+
+/** \brief 16, Error Tracking Register */
+#define MC76_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065C16u)
+
+/** \brief 18, Error Tracking Register */
+#define MC76_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065C18u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC76_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065C1Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC76_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0065C04u)
+
+/** \brief 6, Status Register */
+#define MC76_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0065C06u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC76_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0065C08u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC76_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CA0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC76_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CA2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC76_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CB4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC76_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CB6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC76_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CB8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC76_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CBAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC76_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CBCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC76_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CBEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC76_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CC0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC76_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CC2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC76_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CC4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC76_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CC6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC76_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CA4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC76_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CC8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC76_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CCAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC76_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CCCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC76_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CCEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC76_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CD0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC76_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CD2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC76_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CD4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC76_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CD6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC76_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CD8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC76_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CDAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC76_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CA6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC76_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CDCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC76_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CDEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC76_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CE0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC76_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CE2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC76_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CE4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC76_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CE6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC76_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CE8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC76_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CEAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC76_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC76_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CEEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC76_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CA8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC76_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CAAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC76_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC76_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CAEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC76_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CB0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC76_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065CB2u)
+
+/** \brief C, Revision ID Register */
+#define MC76_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF0065C0Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc77
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC77_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0065D00u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC77_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0065D02u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC77_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0065D10u)
+
+/** \brief E, ECC Safety Register */
+#define MC77_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF0065D0Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC77_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065D12u)
+
+/** \brief 14, Error Tracking Register */
+#define MC77_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065D14u)
+
+/** \brief 16, Error Tracking Register */
+#define MC77_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065D16u)
+
+/** \brief 18, Error Tracking Register */
+#define MC77_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065D18u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC77_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065D1Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC77_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0065D04u)
+
+/** \brief 6, Status Register */
+#define MC77_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0065D06u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC77_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0065D08u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC77_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DA0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC77_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DA2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC77_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DB4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC77_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DB6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC77_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DB8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC77_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DBAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC77_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DBCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC77_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DBEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC77_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DC0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC77_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DC2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC77_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DC4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC77_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DC6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC77_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DA4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC77_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DC8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC77_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DCAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC77_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DCCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC77_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DCEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC77_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DD0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC77_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DD2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC77_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DD4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC77_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DD6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC77_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DD8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC77_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DDAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC77_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DA6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC77_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DDCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC77_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DDEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC77_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DE0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC77_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DE2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC77_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DE4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC77_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DE6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC77_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DE8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC77_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DEAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC77_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC77_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DEEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC77_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DA8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC77_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DAAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC77_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC77_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DAEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC77_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DB0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC77_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065DB2u)
+
+/** \brief C, Revision ID Register */
+#define MC77_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF0065D0Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc78
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC78_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0065E00u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC78_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0065E02u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC78_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0065E10u)
+
+/** \brief E, ECC Safety Register */
+#define MC78_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF0065E0Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC78_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065E12u)
+
+/** \brief 14, Error Tracking Register */
+#define MC78_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065E14u)
+
+/** \brief 16, Error Tracking Register */
+#define MC78_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065E16u)
+
+/** \brief 18, Error Tracking Register */
+#define MC78_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065E18u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC78_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065E1Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC78_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0065E04u)
+
+/** \brief 6, Status Register */
+#define MC78_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0065E06u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC78_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0065E08u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC78_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EA0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC78_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EA2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC78_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EB4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC78_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EB6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC78_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EB8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC78_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EBAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC78_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EBCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC78_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EBEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC78_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EC0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC78_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EC2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC78_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EC4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC78_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EC6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC78_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EA4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC78_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EC8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC78_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065ECAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC78_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065ECCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC78_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065ECEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC78_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065ED0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC78_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065ED2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC78_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065ED4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC78_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065ED6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC78_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065ED8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC78_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EDAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC78_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EA6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC78_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EDCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC78_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EDEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC78_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EE0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC78_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EE2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC78_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EE4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC78_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EE6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC78_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EE8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC78_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EEAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC78_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC78_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EEEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC78_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EA8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC78_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EAAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC78_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC78_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EAEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC78_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EB0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC78_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065EB2u)
+
+/** \brief C, Revision ID Register */
+#define MC78_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF0065E0Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc79
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC79_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0065F00u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC79_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0065F02u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC79_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0065F10u)
+
+/** \brief E, ECC Safety Register */
+#define MC79_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF0065F0Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC79_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065F12u)
+
+/** \brief 14, Error Tracking Register */
+#define MC79_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065F14u)
+
+/** \brief 16, Error Tracking Register */
+#define MC79_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065F16u)
+
+/** \brief 18, Error Tracking Register */
+#define MC79_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065F18u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC79_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0065F1Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC79_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0065F04u)
+
+/** \brief 6, Status Register */
+#define MC79_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0065F06u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC79_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0065F08u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC79_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FA0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC79_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FA2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC79_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FB4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC79_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FB6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC79_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FB8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC79_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FBAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC79_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FBCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC79_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FBEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC79_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FC0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC79_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FC2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC79_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FC4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC79_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FC6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC79_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FA4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC79_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FC8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC79_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FCAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC79_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FCCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC79_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FCEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC79_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FD0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC79_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FD2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC79_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FD4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC79_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FD6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC79_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FD8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC79_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FDAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC79_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FA6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC79_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FDCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC79_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FDEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC79_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FE0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC79_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FE2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC79_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FE4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC79_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FE6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC79_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FE8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC79_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FEAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC79_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC79_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FEEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC79_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FA8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC79_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FAAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC79_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC79_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FAEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC79_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FB0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC79_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF0065FB2u)
+
+/** \brief C, Revision ID Register */
+#define MC79_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF0065F0Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc80
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC80_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0066000u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC80_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0066002u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC80_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0066010u)
+
+/** \brief E, ECC Safety Register */
+#define MC80_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006600Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC80_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066012u)
+
+/** \brief 14, Error Tracking Register */
+#define MC80_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066014u)
+
+/** \brief 16, Error Tracking Register */
+#define MC80_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066016u)
+
+/** \brief 18, Error Tracking Register */
+#define MC80_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066018u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC80_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006601Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC80_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0066004u)
+
+/** \brief 6, Status Register */
+#define MC80_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0066006u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC80_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0066008u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC80_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC80_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC80_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC80_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC80_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC80_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC80_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC80_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC80_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC80_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC80_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC80_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC80_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC80_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC80_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC80_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC80_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC80_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC80_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC80_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC80_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC80_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC80_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC80_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC80_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC80_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC80_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC80_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC80_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC80_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC80_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC80_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC80_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC80_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC80_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC80_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC80_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC80_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC80_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC80_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00660B2u)
+
+/** \brief C, Revision ID Register */
+#define MC80_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006600Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc81
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC81_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0066100u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC81_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0066102u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC81_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0066110u)
+
+/** \brief E, ECC Safety Register */
+#define MC81_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006610Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC81_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066112u)
+
+/** \brief 14, Error Tracking Register */
+#define MC81_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066114u)
+
+/** \brief 16, Error Tracking Register */
+#define MC81_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066116u)
+
+/** \brief 18, Error Tracking Register */
+#define MC81_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066118u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC81_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006611Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC81_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0066104u)
+
+/** \brief 6, Status Register */
+#define MC81_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0066106u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC81_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0066108u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC81_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC81_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC81_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC81_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC81_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC81_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC81_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC81_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC81_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC81_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC81_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC81_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC81_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC81_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC81_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC81_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC81_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC81_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC81_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC81_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC81_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC81_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC81_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC81_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC81_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC81_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC81_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC81_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC81_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC81_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC81_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC81_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC81_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC81_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC81_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC81_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC81_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC81_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC81_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC81_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00661B2u)
+
+/** \brief C, Revision ID Register */
+#define MC81_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006610Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc82
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC82_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0066200u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC82_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0066202u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC82_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0066210u)
+
+/** \brief E, ECC Safety Register */
+#define MC82_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006620Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC82_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066212u)
+
+/** \brief 14, Error Tracking Register */
+#define MC82_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066214u)
+
+/** \brief 16, Error Tracking Register */
+#define MC82_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066216u)
+
+/** \brief 18, Error Tracking Register */
+#define MC82_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066218u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC82_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006621Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC82_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0066204u)
+
+/** \brief 6, Status Register */
+#define MC82_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0066206u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC82_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0066208u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC82_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC82_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC82_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC82_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC82_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC82_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC82_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC82_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC82_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC82_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC82_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC82_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC82_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC82_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC82_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC82_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC82_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC82_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC82_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC82_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC82_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC82_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC82_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC82_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC82_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC82_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC82_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC82_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC82_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC82_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC82_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC82_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC82_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC82_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC82_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC82_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC82_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC82_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC82_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC82_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00662B2u)
+
+/** \brief C, Revision ID Register */
+#define MC82_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006620Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc83
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC83_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0066300u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC83_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0066302u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC83_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0066310u)
+
+/** \brief E, ECC Safety Register */
+#define MC83_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006630Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC83_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066312u)
+
+/** \brief 14, Error Tracking Register */
+#define MC83_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066314u)
+
+/** \brief 16, Error Tracking Register */
+#define MC83_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066316u)
+
+/** \brief 18, Error Tracking Register */
+#define MC83_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066318u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC83_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006631Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC83_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0066304u)
+
+/** \brief 6, Status Register */
+#define MC83_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0066306u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC83_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0066308u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC83_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC83_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC83_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC83_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC83_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC83_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC83_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC83_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC83_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC83_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC83_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC83_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC83_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC83_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC83_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC83_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC83_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC83_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC83_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC83_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC83_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC83_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC83_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC83_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC83_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC83_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC83_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC83_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC83_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC83_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC83_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC83_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC83_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC83_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC83_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC83_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC83_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC83_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC83_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC83_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00663B2u)
+
+/** \brief C, Revision ID Register */
+#define MC83_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006630Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc84
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC84_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0066400u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC84_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0066402u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC84_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0066410u)
+
+/** \brief E, ECC Safety Register */
+#define MC84_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006640Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC84_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066412u)
+
+/** \brief 14, Error Tracking Register */
+#define MC84_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066414u)
+
+/** \brief 16, Error Tracking Register */
+#define MC84_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066416u)
+
+/** \brief 18, Error Tracking Register */
+#define MC84_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066418u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC84_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006641Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC84_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0066404u)
+
+/** \brief 6, Status Register */
+#define MC84_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0066406u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC84_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0066408u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC84_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC84_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC84_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC84_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC84_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC84_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC84_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC84_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC84_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC84_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC84_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC84_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC84_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC84_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC84_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC84_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC84_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC84_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC84_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC84_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC84_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC84_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC84_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC84_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC84_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC84_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC84_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC84_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC84_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC84_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC84_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC84_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC84_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC84_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC84_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC84_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC84_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC84_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC84_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC84_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00664B2u)
+
+/** \brief C, Revision ID Register */
+#define MC84_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006640Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc85
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC85_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0066500u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC85_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0066502u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC85_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0066510u)
+
+/** \brief E, ECC Safety Register */
+#define MC85_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006650Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC85_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066512u)
+
+/** \brief 14, Error Tracking Register */
+#define MC85_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066514u)
+
+/** \brief 16, Error Tracking Register */
+#define MC85_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066516u)
+
+/** \brief 18, Error Tracking Register */
+#define MC85_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066518u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC85_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006651Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC85_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0066504u)
+
+/** \brief 6, Status Register */
+#define MC85_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0066506u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC85_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0066508u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC85_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC85_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC85_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC85_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC85_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC85_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC85_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC85_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC85_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC85_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC85_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC85_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC85_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC85_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC85_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC85_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC85_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC85_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC85_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC85_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC85_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC85_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC85_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC85_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC85_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC85_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC85_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC85_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC85_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC85_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC85_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC85_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC85_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC85_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC85_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC85_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC85_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC85_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC85_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC85_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00665B2u)
+
+/** \brief C, Revision ID Register */
+#define MC85_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006650Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc86
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC86_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0066600u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC86_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0066602u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC86_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0066610u)
+
+/** \brief E, ECC Safety Register */
+#define MC86_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006660Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC86_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066612u)
+
+/** \brief 14, Error Tracking Register */
+#define MC86_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066614u)
+
+/** \brief 16, Error Tracking Register */
+#define MC86_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066616u)
+
+/** \brief 18, Error Tracking Register */
+#define MC86_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066618u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC86_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006661Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC86_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0066604u)
+
+/** \brief 6, Status Register */
+#define MC86_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0066606u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC86_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0066608u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC86_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC86_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC86_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC86_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC86_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC86_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC86_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC86_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC86_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC86_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC86_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC86_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC86_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC86_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC86_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC86_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC86_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC86_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC86_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC86_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC86_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC86_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC86_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC86_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC86_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC86_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC86_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC86_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC86_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC86_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC86_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC86_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC86_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC86_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC86_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC86_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC86_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC86_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC86_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC86_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00666B2u)
+
+/** \brief C, Revision ID Register */
+#define MC86_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006660Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Cfg_Mc87
+ * \{ */
+
+/** \brief 0, Configuration Register 0 */
+#define MC87_CONFIG0 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG0*)0xF0066700u)
+
+/** \brief 2, Configuration Register 1 */
+#define MC87_CONFIG1 /*lint --e(923)*/ (*(volatile Ifx_MC_CONFIG1*)0xF0066702u)
+
+/** \brief 10, Memory ECC Detection Register */
+#define MC87_ECCD /*lint --e(923)*/ (*(volatile Ifx_MC_ECCD*)0xF0066710u)
+
+/** \brief E, ECC Safety Register */
+#define MC87_ECCS /*lint --e(923)*/ (*(volatile Ifx_MC_ECCS*)0xF006670Eu)
+
+/** \brief 12, Error Tracking Register */
+#define MC87_ETRR0 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066712u)
+
+/** \brief 14, Error Tracking Register */
+#define MC87_ETRR1 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066714u)
+
+/** \brief 16, Error Tracking Register */
+#define MC87_ETRR2 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066716u)
+
+/** \brief 18, Error Tracking Register */
+#define MC87_ETRR3 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF0066718u)
+
+/** \brief 1A, Error Tracking Register */
+#define MC87_ETRR4 /*lint --e(923)*/ (*(volatile Ifx_MC_ETRR*)0xF006671Au)
+
+/** \brief 4, MBIST Control Register */
+#define MC87_MCONTROL /*lint --e(923)*/ (*(volatile Ifx_MC_MCONTROL*)0xF0066704u)
+
+/** \brief 6, Status Register */
+#define MC87_MSTATUS /*lint --e(923)*/ (*(volatile Ifx_MC_MSTATUS*)0xF0066706u)
+
+/** \brief 8, Range Register, single address mode */
+#define MC87_RANGE /*lint --e(923)*/ (*(volatile Ifx_MC_RANGE*)0xF0066708u)
+
+/** \brief A0, Read Data and Bit Flip Register */
+#define MC87_RDBFL0 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667A0u)
+
+/** \brief A2, Read Data and Bit Flip Register */
+#define MC87_RDBFL1 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667A2u)
+
+/** \brief B4, Read Data and Bit Flip Register */
+#define MC87_RDBFL10 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667B4u)
+
+/** \brief B6, Read Data and Bit Flip Register */
+#define MC87_RDBFL11 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667B6u)
+
+/** \brief B8, Read Data and Bit Flip Register */
+#define MC87_RDBFL12 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667B8u)
+
+/** \brief BA, Read Data and Bit Flip Register */
+#define MC87_RDBFL13 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667BAu)
+
+/** \brief BC, Read Data and Bit Flip Register */
+#define MC87_RDBFL14 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667BCu)
+
+/** \brief BE, Read Data and Bit Flip Register */
+#define MC87_RDBFL15 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667BEu)
+
+/** \brief C0, Read Data and Bit Flip Register */
+#define MC87_RDBFL16 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667C0u)
+
+/** \brief C2, Read Data and Bit Flip Register */
+#define MC87_RDBFL17 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667C2u)
+
+/** \brief C4, Read Data and Bit Flip Register */
+#define MC87_RDBFL18 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667C4u)
+
+/** \brief C6, Read Data and Bit Flip Register */
+#define MC87_RDBFL19 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667C6u)
+
+/** \brief A4, Read Data and Bit Flip Register */
+#define MC87_RDBFL2 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667A4u)
+
+/** \brief C8, Read Data and Bit Flip Register */
+#define MC87_RDBFL20 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667C8u)
+
+/** \brief CA, Read Data and Bit Flip Register */
+#define MC87_RDBFL21 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667CAu)
+
+/** \brief CC, Read Data and Bit Flip Register */
+#define MC87_RDBFL22 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667CCu)
+
+/** \brief CE, Read Data and Bit Flip Register */
+#define MC87_RDBFL23 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667CEu)
+
+/** \brief D0, Read Data and Bit Flip Register */
+#define MC87_RDBFL24 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667D0u)
+
+/** \brief D2, Read Data and Bit Flip Register */
+#define MC87_RDBFL25 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667D2u)
+
+/** \brief D4, Read Data and Bit Flip Register */
+#define MC87_RDBFL26 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667D4u)
+
+/** \brief D6, Read Data and Bit Flip Register */
+#define MC87_RDBFL27 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667D6u)
+
+/** \brief D8, Read Data and Bit Flip Register */
+#define MC87_RDBFL28 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667D8u)
+
+/** \brief DA, Read Data and Bit Flip Register */
+#define MC87_RDBFL29 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667DAu)
+
+/** \brief A6, Read Data and Bit Flip Register */
+#define MC87_RDBFL3 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667A6u)
+
+/** \brief DC, Read Data and Bit Flip Register */
+#define MC87_RDBFL30 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667DCu)
+
+/** \brief DE, Read Data and Bit Flip Register */
+#define MC87_RDBFL31 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667DEu)
+
+/** \brief E0, Read Data and Bit Flip Register */
+#define MC87_RDBFL32 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667E0u)
+
+/** \brief E2, Read Data and Bit Flip Register */
+#define MC87_RDBFL33 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667E2u)
+
+/** \brief E4, Read Data and Bit Flip Register */
+#define MC87_RDBFL34 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667E4u)
+
+/** \brief E6, Read Data and Bit Flip Register */
+#define MC87_RDBFL35 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667E6u)
+
+/** \brief E8, Read Data and Bit Flip Register */
+#define MC87_RDBFL36 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667E8u)
+
+/** \brief EA, Read Data and Bit Flip Register */
+#define MC87_RDBFL37 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667EAu)
+
+/** \brief EC, Read Data and Bit Flip Register */
+#define MC87_RDBFL38 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667ECu)
+
+/** \brief EE, Read Data and Bit Flip Register */
+#define MC87_RDBFL39 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667EEu)
+
+/** \brief A8, Read Data and Bit Flip Register */
+#define MC87_RDBFL4 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667A8u)
+
+/** \brief AA, Read Data and Bit Flip Register */
+#define MC87_RDBFL5 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667AAu)
+
+/** \brief AC, Read Data and Bit Flip Register */
+#define MC87_RDBFL6 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667ACu)
+
+/** \brief AE, Read Data and Bit Flip Register */
+#define MC87_RDBFL7 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667AEu)
+
+/** \brief B0, Read Data and Bit Flip Register */
+#define MC87_RDBFL8 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667B0u)
+
+/** \brief B2, Read Data and Bit Flip Register */
+#define MC87_RDBFL9 /*lint --e(923)*/ (*(volatile Ifx_MC_RDBFL*)0xF00667B2u)
+
+/** \brief C, Revision ID Register */
+#define MC87_REVID /*lint --e(923)*/ (*(volatile Ifx_MC_REVID*)0xF006670Cu)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXMC_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxMc_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxMc_regdef.h
new file mode 100644
index 0000000..4f0749a
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxMc_regdef.h
@@ -0,0 +1,259 @@
+/**
+ * \file IfxMc_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Mc Mc
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Mc_Bitfields Bitfields
+ * \ingroup IfxLld_Mc
+ *
+ * \defgroup IfxLld_Mc_union Union
+ * \ingroup IfxLld_Mc
+ *
+ * \defgroup IfxLld_Mc_struct Struct
+ * \ingroup IfxLld_Mc
+ *
+ */
+#ifndef IFXMC_REGDEF_H
+#define IFXMC_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_Bitfields
+ * \{ */
+
+/** \brief Configuration Register 0 */
+typedef struct _Ifx_MC_CONFIG0_Bits
+{
+ Ifx_Strict_16Bit ACCSTYPE:8; /**< \brief [7:0] Access type (rw) */
+ Ifx_Strict_16Bit reserved_8:4; /**< \brief \internal Reserved */
+ Ifx_Strict_16Bit NUMACCS:4; /**< \brief [15:12] Number of accesses per address (rw) */
+} Ifx_MC_CONFIG0_Bits;
+
+/** \brief Configuration Register 1 */
+typedef struct _Ifx_MC_CONFIG1_Bits
+{
+ Ifx_Strict_16Bit ACCSPAT:8; /**< \brief [7:0] Access pattern (rw) */
+ Ifx_Strict_16Bit SELFASTB:4; /**< \brief [11:8] Select Fast Bit (rw) */
+ Ifx_Strict_16Bit AG_MOD:4; /**< \brief [15:12] Address Generator Mode (rw) */
+} Ifx_MC_CONFIG1_Bits;
+
+/** \brief Memory ECC Detection Register */
+typedef struct _Ifx_MC_ECCD_Bits
+{
+ Ifx_Strict_16Bit SERR:1; /**< \brief [0:0] Error Detected (rwh) */
+ Ifx_Strict_16Bit CERR:1; /**< \brief [1:1] Correctable Error Detected (rwh) */
+ Ifx_Strict_16Bit UERR:1; /**< \brief [2:2] Uncorrectable Error Detected (rwh) */
+ Ifx_Strict_16Bit AERR:1; /**< \brief [3:3] Address Error Detected (rwh) */
+ Ifx_Strict_16Bit TRC:1; /**< \brief [4:4] Tracking Clear (w) */
+ Ifx_Strict_16Bit VAL:5; /**< \brief [9:5] Valid Bits (rh) */
+ Ifx_Strict_16Bit RARVAL:1; /**< \brief [10:10] RAR Valid (rwh) */
+ Ifx_Strict_16Bit CENE:1; /**< \brief [11:11] Correctable Error Notification Enable (rw) */
+ Ifx_Strict_16Bit UENE:1; /**< \brief [12:12] Uncorrectable Error Notification Enable (rw) */
+ Ifx_Strict_16Bit AENE:1; /**< \brief [13:13] Address Error Notification Enable (rw) */
+ Ifx_Strict_16Bit ECE:1; /**< \brief [14:14] Error Correction Enable (rw) */
+ Ifx_Strict_16Bit EOV:1; /**< \brief [15:15] Error Overflow (rh) */
+} Ifx_MC_ECCD_Bits;
+
+/** \brief ECC Safety Register */
+typedef struct _Ifx_MC_ECCS_Bits
+{
+ Ifx_Strict_16Bit CENE:1; /**< \brief [0:0] Correctable Error Notification Enable (rw) */
+ Ifx_Strict_16Bit UENE:1; /**< \brief [1:1] Uncorrectable Error Notification Enable (rw) */
+ Ifx_Strict_16Bit AENE:1; /**< \brief [2:2] Address Error Notification Enable (rw) */
+ Ifx_Strict_16Bit ECE:1; /**< \brief [3:3] Error Correction Enable (rw) */
+ Ifx_Strict_16Bit TRE:1; /**< \brief [4:4] Tracking Enable (rw) */
+ Ifx_Strict_16Bit BFLE:1; /**< \brief [5:5] Bit Flip Enable (rw) */
+ Ifx_Strict_16Bit SFLE:2; /**< \brief [7:6] Signature Bit Flip Enables (rw) */
+ Ifx_Strict_16Bit ECCMAP:2; /**< \brief [9:8] ECC Bit Mapping Mode (rw) */
+ Ifx_Strict_16Bit TC_WAY_SEL:2; /**< \brief [11:10] TriCore Cache Way Select (rw) */
+ Ifx_Strict_16Bit reserved_12:4; /**< \brief \internal Reserved */
+} Ifx_MC_ECCS_Bits;
+
+/** \brief Error Tracking Register */
+typedef struct _Ifx_MC_ETRR_Bits
+{
+ Ifx_Strict_16Bit ADDR:13; /**< \brief [12:0] Address of Error(i) (rh) */
+ Ifx_Strict_16Bit MBI:3; /**< \brief [15:13] Memory Block Index of Error(i) (rh) */
+} Ifx_MC_ETRR_Bits;
+
+/** \brief MBIST Control Register */
+typedef struct _Ifx_MC_MCONTROL_Bits
+{
+ Ifx_Strict_16Bit START:1; /**< \brief [0:0] START (rw) */
+ Ifx_Strict_16Bit RESUME:1; /**< \brief [1:1] Resume failed test (rwh) */
+ Ifx_Strict_16Bit ESTF:1; /**< \brief [2:2] Enable Sticky Fail Bit (rw) */
+ Ifx_Strict_16Bit DIR:1; /**< \brief [3:3] Direction Select (rw) */
+ Ifx_Strict_16Bit DINIT:1; /**< \brief [4:4] Data Initialization Enable (rw) */
+ Ifx_Strict_16Bit RCADR:1; /**< \brief [5:5] Fast Row / Fast Column Addressing Scheme Select (rw) */
+ Ifx_Strict_16Bit ROWTOG:1; /**< \brief [6:6] Row toggling (rw) */
+ Ifx_Strict_16Bit BITTOG:1; /**< \brief [7:7] Bit toggling (rw) */
+ Ifx_Strict_16Bit GP_BASE:1; /**< \brief [8:8] Galpat Base (rw) */
+ Ifx_Strict_16Bit FAILDMP:1; /**< \brief [9:9] Fail bitmap dump (rw) */
+ Ifx_Strict_16Bit reserved_10:6; /**< \brief \internal Reserved */
+} Ifx_MC_MCONTROL_Bits;
+
+/** \brief Status Register */
+typedef struct _Ifx_MC_MSTATUS_Bits
+{
+ Ifx_Strict_16Bit DONE:1; /**< \brief [0:0] DONE (rh) */
+ Ifx_Strict_16Bit FAIL:1; /**< \brief [1:1] FAIL (rh) */
+ Ifx_Strict_16Bit FDA:1; /**< \brief [2:2] Fail Dump Available (rh) */
+ Ifx_Strict_16Bit SFAIL:1; /**< \brief [3:3] Sticky Fail Bit (rh) */
+ Ifx_Strict_16Bit reserved_4:12; /**< \brief \internal Reserved */
+} Ifx_MC_MSTATUS_Bits;
+
+/** \brief Range Register, single address mode */
+typedef struct _Ifx_MC_RANGE_Bits
+{
+ Ifx_Strict_16Bit ADDR:15; /**< \brief [14:0] Address (rw) */
+ Ifx_Strict_16Bit RAEN:1; /**< \brief [15:15] Range Enable (rw) */
+} Ifx_MC_RANGE_Bits;
+
+/** \brief Read Data and Bit Flip Register */
+typedef struct _Ifx_MC_RDBFL_Bits
+{
+ Ifx_Strict_16Bit WDATA:16; /**< \brief [15:0] Word Data (rwh) */
+} Ifx_MC_RDBFL_Bits;
+
+/** \brief Revision ID Register */
+typedef struct _Ifx_MC_REVID_Bits
+{
+ Ifx_Strict_16Bit REV_ID:16; /**< \brief [15:0] Revision Identifier (r) */
+} Ifx_MC_REVID_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_union
+ * \{ */
+
+/** \brief Configuration Register 0 */
+typedef union
+{
+ unsigned short U; /**< \brief Unsigned access */
+ signed short I; /**< \brief Signed access */
+ Ifx_MC_CONFIG0_Bits B; /**< \brief Bitfield access */
+} Ifx_MC_CONFIG0;
+
+/** \brief Configuration Register 1 */
+typedef union
+{
+ unsigned short U; /**< \brief Unsigned access */
+ signed short I; /**< \brief Signed access */
+ Ifx_MC_CONFIG1_Bits B; /**< \brief Bitfield access */
+} Ifx_MC_CONFIG1;
+
+/** \brief Memory ECC Detection Register */
+typedef union
+{
+ unsigned short U; /**< \brief Unsigned access */
+ signed short I; /**< \brief Signed access */
+ Ifx_MC_ECCD_Bits B; /**< \brief Bitfield access */
+} Ifx_MC_ECCD;
+
+/** \brief ECC Safety Register */
+typedef union
+{
+ unsigned short U; /**< \brief Unsigned access */
+ signed short I; /**< \brief Signed access */
+ Ifx_MC_ECCS_Bits B; /**< \brief Bitfield access */
+} Ifx_MC_ECCS;
+
+/** \brief Error Tracking Register */
+typedef union
+{
+ unsigned short U; /**< \brief Unsigned access */
+ signed short I; /**< \brief Signed access */
+ Ifx_MC_ETRR_Bits B; /**< \brief Bitfield access */
+} Ifx_MC_ETRR;
+
+/** \brief MBIST Control Register */
+typedef union
+{
+ unsigned short U; /**< \brief Unsigned access */
+ signed short I; /**< \brief Signed access */
+ Ifx_MC_MCONTROL_Bits B; /**< \brief Bitfield access */
+} Ifx_MC_MCONTROL;
+
+/** \brief Status Register */
+typedef union
+{
+ unsigned short U; /**< \brief Unsigned access */
+ signed short I; /**< \brief Signed access */
+ Ifx_MC_MSTATUS_Bits B; /**< \brief Bitfield access */
+} Ifx_MC_MSTATUS;
+
+/** \brief Range Register, single address mode */
+typedef union
+{
+ unsigned short U; /**< \brief Unsigned access */
+ signed short I; /**< \brief Signed access */
+ Ifx_MC_RANGE_Bits B; /**< \brief Bitfield access */
+} Ifx_MC_RANGE;
+
+/** \brief Read Data and Bit Flip Register */
+typedef union
+{
+ unsigned short U; /**< \brief Unsigned access */
+ signed short I; /**< \brief Signed access */
+ Ifx_MC_RDBFL_Bits B; /**< \brief Bitfield access */
+} Ifx_MC_RDBFL;
+
+/** \brief Revision ID Register */
+typedef union
+{
+ unsigned short U; /**< \brief Unsigned access */
+ signed short I; /**< \brief Signed access */
+ Ifx_MC_REVID_Bits B; /**< \brief Bitfield access */
+} Ifx_MC_REVID;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mc_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief MC object */
+typedef volatile struct _Ifx_MC
+{
+ Ifx_MC_CONFIG0 CONFIG0; /**< \brief 0, Configuration Register 0 */
+ Ifx_MC_CONFIG1 CONFIG1; /**< \brief 2, Configuration Register 1 */
+ Ifx_MC_MCONTROL MCONTROL; /**< \brief 4, MBIST Control Register */
+ Ifx_MC_MSTATUS MSTATUS; /**< \brief 6, Status Register */
+ Ifx_MC_RANGE RANGE; /**< \brief 8, Range Register, single address mode */
+ unsigned char reserved_A[2]; /**< \brief A, \internal Reserved */
+ Ifx_MC_REVID REVID; /**< \brief C, Revision ID Register */
+ Ifx_MC_ECCS ECCS; /**< \brief E, ECC Safety Register */
+ Ifx_MC_ECCD ECCD; /**< \brief 10, Memory ECC Detection Register */
+ Ifx_MC_ETRR ETRR[5]; /**< \brief 12, Error Tracking Register */
+ unsigned char reserved_1C[132]; /**< \brief 1C, \internal Reserved */
+ Ifx_MC_RDBFL RDBFL[40]; /**< \brief A0, Read Data and Bit Flip Register */
+ unsigned char reserved_F0[16]; /**< \brief F0, \internal Reserved */
+} Ifx_MC;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXMC_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxMsc_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxMsc_bf.h
new file mode 100644
index 0000000..b7ce5b1
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxMsc_bf.h
@@ -0,0 +1,2583 @@
+/**
+ * \file IfxMsc_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Msc_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Msc
+ *
+ */
+#ifndef IFXMSC_BF_H
+#define IFXMSC_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Msc_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_MSC_ABC_Bits.ABB */
+#define IFX_MSC_ABC_ABB_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ABC_Bits.ABB */
+#define IFX_MSC_ABC_ABB_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ABC_Bits.ABB */
+#define IFX_MSC_ABC_ABB_OFF (31u)
+
+/** \brief Length for Ifx_MSC_ABC_Bits.CLKSEL */
+#define IFX_MSC_ABC_CLKSEL_LEN (3u)
+
+/** \brief Mask for Ifx_MSC_ABC_Bits.CLKSEL */
+#define IFX_MSC_ABC_CLKSEL_MSK (0x7u)
+
+/** \brief Offset for Ifx_MSC_ABC_Bits.CLKSEL */
+#define IFX_MSC_ABC_CLKSEL_OFF (27u)
+
+/** \brief Length for Ifx_MSC_ABC_Bits.HIGH */
+#define IFX_MSC_ABC_HIGH_LEN (4u)
+
+/** \brief Mask for Ifx_MSC_ABC_Bits.HIGH */
+#define IFX_MSC_ABC_HIGH_MSK (0xfu)
+
+/** \brief Offset for Ifx_MSC_ABC_Bits.HIGH */
+#define IFX_MSC_ABC_HIGH_OFF (4u)
+
+/** \brief Length for Ifx_MSC_ABC_Bits.LOW */
+#define IFX_MSC_ABC_LOW_LEN (4u)
+
+/** \brief Mask for Ifx_MSC_ABC_Bits.LOW */
+#define IFX_MSC_ABC_LOW_MSK (0xfu)
+
+/** \brief Offset for Ifx_MSC_ABC_Bits.LOW */
+#define IFX_MSC_ABC_LOW_OFF (0u)
+
+/** \brief Length for Ifx_MSC_ABC_Bits.NDA */
+#define IFX_MSC_ABC_NDA_LEN (3u)
+
+/** \brief Mask for Ifx_MSC_ABC_Bits.NDA */
+#define IFX_MSC_ABC_NDA_MSK (0x7u)
+
+/** \brief Offset for Ifx_MSC_ABC_Bits.NDA */
+#define IFX_MSC_ABC_NDA_OFF (16u)
+
+/** \brief Length for Ifx_MSC_ABC_Bits.OASR */
+#define IFX_MSC_ABC_OASR_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ABC_Bits.OASR */
+#define IFX_MSC_ABC_OASR_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ABC_Bits.OASR */
+#define IFX_MSC_ABC_OASR_OFF (10u)
+
+/** \brief Length for Ifx_MSC_ABC_Bits.OFM */
+#define IFX_MSC_ABC_OFM_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_ABC_Bits.OFM */
+#define IFX_MSC_ABC_OFM_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_ABC_Bits.OFM */
+#define IFX_MSC_ABC_OFM_OFF (13u)
+
+/** \brief Length for Ifx_MSC_ABC_Bits.OIE */
+#define IFX_MSC_ABC_OIE_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ABC_Bits.OIE */
+#define IFX_MSC_ABC_OIE_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ABC_Bits.OIE */
+#define IFX_MSC_ABC_OIE_OFF (15u)
+
+/** \brief Length for Ifx_MSC_ABC_Bits.OIP */
+#define IFX_MSC_ABC_OIP_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_ABC_Bits.OIP */
+#define IFX_MSC_ABC_OIP_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_ABC_Bits.OIP */
+#define IFX_MSC_ABC_OIP_OFF (8u)
+
+/** \brief Length for Ifx_MSC_ABC_Bits.OVF */
+#define IFX_MSC_ABC_OVF_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ABC_Bits.OVF */
+#define IFX_MSC_ABC_OVF_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ABC_Bits.OVF */
+#define IFX_MSC_ABC_OVF_OFF (12u)
+
+/** \brief Length for Ifx_MSC_ABC_Bits.UASR */
+#define IFX_MSC_ABC_UASR_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ABC_Bits.UASR */
+#define IFX_MSC_ABC_UASR_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ABC_Bits.UASR */
+#define IFX_MSC_ABC_UASR_OFF (21u)
+
+/** \brief Length for Ifx_MSC_ABC_Bits.UFM */
+#define IFX_MSC_ABC_UFM_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_ABC_Bits.UFM */
+#define IFX_MSC_ABC_UFM_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_ABC_Bits.UFM */
+#define IFX_MSC_ABC_UFM_OFF (24u)
+
+/** \brief Length for Ifx_MSC_ABC_Bits.UIE */
+#define IFX_MSC_ABC_UIE_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ABC_Bits.UIE */
+#define IFX_MSC_ABC_UIE_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ABC_Bits.UIE */
+#define IFX_MSC_ABC_UIE_OFF (26u)
+
+/** \brief Length for Ifx_MSC_ABC_Bits.UIP */
+#define IFX_MSC_ABC_UIP_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_ABC_Bits.UIP */
+#define IFX_MSC_ABC_UIP_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_ABC_Bits.UIP */
+#define IFX_MSC_ABC_UIP_OFF (19u)
+
+/** \brief Length for Ifx_MSC_ABC_Bits.UNF */
+#define IFX_MSC_ABC_UNF_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ABC_Bits.UNF */
+#define IFX_MSC_ABC_UNF_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ABC_Bits.UNF */
+#define IFX_MSC_ABC_UNF_OFF (23u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN0 */
+#define IFX_MSC_ACCEN0_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN0 */
+#define IFX_MSC_ACCEN0_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN0 */
+#define IFX_MSC_ACCEN0_EN0_OFF (0u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN10 */
+#define IFX_MSC_ACCEN0_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN10 */
+#define IFX_MSC_ACCEN0_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN10 */
+#define IFX_MSC_ACCEN0_EN10_OFF (10u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN11 */
+#define IFX_MSC_ACCEN0_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN11 */
+#define IFX_MSC_ACCEN0_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN11 */
+#define IFX_MSC_ACCEN0_EN11_OFF (11u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN12 */
+#define IFX_MSC_ACCEN0_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN12 */
+#define IFX_MSC_ACCEN0_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN12 */
+#define IFX_MSC_ACCEN0_EN12_OFF (12u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN13 */
+#define IFX_MSC_ACCEN0_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN13 */
+#define IFX_MSC_ACCEN0_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN13 */
+#define IFX_MSC_ACCEN0_EN13_OFF (13u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN14 */
+#define IFX_MSC_ACCEN0_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN14 */
+#define IFX_MSC_ACCEN0_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN14 */
+#define IFX_MSC_ACCEN0_EN14_OFF (14u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN15 */
+#define IFX_MSC_ACCEN0_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN15 */
+#define IFX_MSC_ACCEN0_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN15 */
+#define IFX_MSC_ACCEN0_EN15_OFF (15u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN16 */
+#define IFX_MSC_ACCEN0_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN16 */
+#define IFX_MSC_ACCEN0_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN16 */
+#define IFX_MSC_ACCEN0_EN16_OFF (16u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN17 */
+#define IFX_MSC_ACCEN0_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN17 */
+#define IFX_MSC_ACCEN0_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN17 */
+#define IFX_MSC_ACCEN0_EN17_OFF (17u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN18 */
+#define IFX_MSC_ACCEN0_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN18 */
+#define IFX_MSC_ACCEN0_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN18 */
+#define IFX_MSC_ACCEN0_EN18_OFF (18u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN19 */
+#define IFX_MSC_ACCEN0_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN19 */
+#define IFX_MSC_ACCEN0_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN19 */
+#define IFX_MSC_ACCEN0_EN19_OFF (19u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN1 */
+#define IFX_MSC_ACCEN0_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN1 */
+#define IFX_MSC_ACCEN0_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN1 */
+#define IFX_MSC_ACCEN0_EN1_OFF (1u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN20 */
+#define IFX_MSC_ACCEN0_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN20 */
+#define IFX_MSC_ACCEN0_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN20 */
+#define IFX_MSC_ACCEN0_EN20_OFF (20u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN21 */
+#define IFX_MSC_ACCEN0_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN21 */
+#define IFX_MSC_ACCEN0_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN21 */
+#define IFX_MSC_ACCEN0_EN21_OFF (21u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN22 */
+#define IFX_MSC_ACCEN0_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN22 */
+#define IFX_MSC_ACCEN0_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN22 */
+#define IFX_MSC_ACCEN0_EN22_OFF (22u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN23 */
+#define IFX_MSC_ACCEN0_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN23 */
+#define IFX_MSC_ACCEN0_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN23 */
+#define IFX_MSC_ACCEN0_EN23_OFF (23u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN24 */
+#define IFX_MSC_ACCEN0_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN24 */
+#define IFX_MSC_ACCEN0_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN24 */
+#define IFX_MSC_ACCEN0_EN24_OFF (24u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN25 */
+#define IFX_MSC_ACCEN0_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN25 */
+#define IFX_MSC_ACCEN0_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN25 */
+#define IFX_MSC_ACCEN0_EN25_OFF (25u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN26 */
+#define IFX_MSC_ACCEN0_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN26 */
+#define IFX_MSC_ACCEN0_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN26 */
+#define IFX_MSC_ACCEN0_EN26_OFF (26u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN27 */
+#define IFX_MSC_ACCEN0_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN27 */
+#define IFX_MSC_ACCEN0_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN27 */
+#define IFX_MSC_ACCEN0_EN27_OFF (27u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN28 */
+#define IFX_MSC_ACCEN0_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN28 */
+#define IFX_MSC_ACCEN0_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN28 */
+#define IFX_MSC_ACCEN0_EN28_OFF (28u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN29 */
+#define IFX_MSC_ACCEN0_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN29 */
+#define IFX_MSC_ACCEN0_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN29 */
+#define IFX_MSC_ACCEN0_EN29_OFF (29u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN2 */
+#define IFX_MSC_ACCEN0_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN2 */
+#define IFX_MSC_ACCEN0_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN2 */
+#define IFX_MSC_ACCEN0_EN2_OFF (2u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN30 */
+#define IFX_MSC_ACCEN0_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN30 */
+#define IFX_MSC_ACCEN0_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN30 */
+#define IFX_MSC_ACCEN0_EN30_OFF (30u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN31 */
+#define IFX_MSC_ACCEN0_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN31 */
+#define IFX_MSC_ACCEN0_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN31 */
+#define IFX_MSC_ACCEN0_EN31_OFF (31u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN3 */
+#define IFX_MSC_ACCEN0_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN3 */
+#define IFX_MSC_ACCEN0_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN3 */
+#define IFX_MSC_ACCEN0_EN3_OFF (3u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN4 */
+#define IFX_MSC_ACCEN0_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN4 */
+#define IFX_MSC_ACCEN0_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN4 */
+#define IFX_MSC_ACCEN0_EN4_OFF (4u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN5 */
+#define IFX_MSC_ACCEN0_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN5 */
+#define IFX_MSC_ACCEN0_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN5 */
+#define IFX_MSC_ACCEN0_EN5_OFF (5u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN6 */
+#define IFX_MSC_ACCEN0_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN6 */
+#define IFX_MSC_ACCEN0_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN6 */
+#define IFX_MSC_ACCEN0_EN6_OFF (6u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN7 */
+#define IFX_MSC_ACCEN0_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN7 */
+#define IFX_MSC_ACCEN0_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN7 */
+#define IFX_MSC_ACCEN0_EN7_OFF (7u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN8 */
+#define IFX_MSC_ACCEN0_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN8 */
+#define IFX_MSC_ACCEN0_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN8 */
+#define IFX_MSC_ACCEN0_EN8_OFF (8u)
+
+/** \brief Length for Ifx_MSC_ACCEN0_Bits.EN9 */
+#define IFX_MSC_ACCEN0_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ACCEN0_Bits.EN9 */
+#define IFX_MSC_ACCEN0_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ACCEN0_Bits.EN9 */
+#define IFX_MSC_ACCEN0_EN9_OFF (9u)
+
+/** \brief Length for Ifx_MSC_CLC_Bits.DISR */
+#define IFX_MSC_CLC_DISR_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_CLC_Bits.DISR */
+#define IFX_MSC_CLC_DISR_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_CLC_Bits.DISR */
+#define IFX_MSC_CLC_DISR_OFF (0u)
+
+/** \brief Length for Ifx_MSC_CLC_Bits.DISS */
+#define IFX_MSC_CLC_DISS_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_CLC_Bits.DISS */
+#define IFX_MSC_CLC_DISS_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_CLC_Bits.DISS */
+#define IFX_MSC_CLC_DISS_OFF (1u)
+
+/** \brief Length for Ifx_MSC_CLC_Bits.EDIS */
+#define IFX_MSC_CLC_EDIS_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_CLC_Bits.EDIS */
+#define IFX_MSC_CLC_EDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_CLC_Bits.EDIS */
+#define IFX_MSC_CLC_EDIS_OFF (3u)
+
+/** \brief Length for Ifx_MSC_DC_Bits.DCH */
+#define IFX_MSC_DC_DCH_LEN (16u)
+
+/** \brief Mask for Ifx_MSC_DC_Bits.DCH */
+#define IFX_MSC_DC_DCH_MSK (0xffffu)
+
+/** \brief Offset for Ifx_MSC_DC_Bits.DCH */
+#define IFX_MSC_DC_DCH_OFF (16u)
+
+/** \brief Length for Ifx_MSC_DC_Bits.DCL */
+#define IFX_MSC_DC_DCL_LEN (16u)
+
+/** \brief Mask for Ifx_MSC_DC_Bits.DCL */
+#define IFX_MSC_DC_DCL_MSK (0xffffu)
+
+/** \brief Offset for Ifx_MSC_DC_Bits.DCL */
+#define IFX_MSC_DC_DCL_OFF (0u)
+
+/** \brief Length for Ifx_MSC_DD_Bits.DDH */
+#define IFX_MSC_DD_DDH_LEN (16u)
+
+/** \brief Mask for Ifx_MSC_DD_Bits.DDH */
+#define IFX_MSC_DD_DDH_MSK (0xffffu)
+
+/** \brief Offset for Ifx_MSC_DD_Bits.DDH */
+#define IFX_MSC_DD_DDH_OFF (16u)
+
+/** \brief Length for Ifx_MSC_DD_Bits.DDL */
+#define IFX_MSC_DD_DDL_LEN (16u)
+
+/** \brief Mask for Ifx_MSC_DD_Bits.DDL */
+#define IFX_MSC_DD_DDL_MSK (0xffffu)
+
+/** \brief Offset for Ifx_MSC_DD_Bits.DDL */
+#define IFX_MSC_DD_DDL_OFF (0u)
+
+/** \brief Length for Ifx_MSC_DDE_Bits.DDHE */
+#define IFX_MSC_DDE_DDHE_LEN (16u)
+
+/** \brief Mask for Ifx_MSC_DDE_Bits.DDHE */
+#define IFX_MSC_DDE_DDHE_MSK (0xffffu)
+
+/** \brief Offset for Ifx_MSC_DDE_Bits.DDHE */
+#define IFX_MSC_DDE_DDHE_OFF (16u)
+
+/** \brief Length for Ifx_MSC_DDE_Bits.DDLE */
+#define IFX_MSC_DDE_DDLE_LEN (16u)
+
+/** \brief Mask for Ifx_MSC_DDE_Bits.DDLE */
+#define IFX_MSC_DDE_DDLE_MSK (0xffffu)
+
+/** \brief Offset for Ifx_MSC_DDE_Bits.DDLE */
+#define IFX_MSC_DDE_DDLE_OFF (0u)
+
+/** \brief Length for Ifx_MSC_DDM_Bits.DDHM */
+#define IFX_MSC_DDM_DDHM_LEN (16u)
+
+/** \brief Mask for Ifx_MSC_DDM_Bits.DDHM */
+#define IFX_MSC_DDM_DDHM_MSK (0xffffu)
+
+/** \brief Offset for Ifx_MSC_DDM_Bits.DDHM */
+#define IFX_MSC_DDM_DDHM_OFF (16u)
+
+/** \brief Length for Ifx_MSC_DDM_Bits.DDLM */
+#define IFX_MSC_DDM_DDLM_LEN (16u)
+
+/** \brief Mask for Ifx_MSC_DDM_Bits.DDLM */
+#define IFX_MSC_DDM_DDLM_MSK (0xffffu)
+
+/** \brief Offset for Ifx_MSC_DDM_Bits.DDLM */
+#define IFX_MSC_DDM_DDLM_OFF (0u)
+
+/** \brief Length for Ifx_MSC_DSC_Bits.CP */
+#define IFX_MSC_DSC_CP_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_DSC_Bits.CP */
+#define IFX_MSC_DSC_CP_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_DSC_Bits.CP */
+#define IFX_MSC_DSC_CP_OFF (1u)
+
+/** \brief Length for Ifx_MSC_DSC_Bits.DP */
+#define IFX_MSC_DSC_DP_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_DSC_Bits.DP */
+#define IFX_MSC_DSC_DP_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_DSC_Bits.DP */
+#define IFX_MSC_DSC_DP_OFF (2u)
+
+/** \brief Length for Ifx_MSC_DSC_Bits.DSDIS */
+#define IFX_MSC_DSC_DSDIS_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_DSC_Bits.DSDIS */
+#define IFX_MSC_DSC_DSDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_DSC_Bits.DSDIS */
+#define IFX_MSC_DSC_DSDIS_OFF (15u)
+
+/** \brief Length for Ifx_MSC_DSC_Bits.ENSELH */
+#define IFX_MSC_DSC_ENSELH_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_DSC_Bits.ENSELH */
+#define IFX_MSC_DSC_ENSELH_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_DSC_Bits.ENSELH */
+#define IFX_MSC_DSC_ENSELH_OFF (14u)
+
+/** \brief Length for Ifx_MSC_DSC_Bits.ENSELL */
+#define IFX_MSC_DSC_ENSELL_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_DSC_Bits.ENSELL */
+#define IFX_MSC_DSC_ENSELL_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_DSC_Bits.ENSELL */
+#define IFX_MSC_DSC_ENSELL_OFF (13u)
+
+/** \brief Length for Ifx_MSC_DSC_Bits.NBC */
+#define IFX_MSC_DSC_NBC_LEN (6u)
+
+/** \brief Mask for Ifx_MSC_DSC_Bits.NBC */
+#define IFX_MSC_DSC_NBC_MSK (0x3fu)
+
+/** \brief Offset for Ifx_MSC_DSC_Bits.NBC */
+#define IFX_MSC_DSC_NBC_OFF (16u)
+
+/** \brief Length for Ifx_MSC_DSC_Bits.NDBH */
+#define IFX_MSC_DSC_NDBH_LEN (5u)
+
+/** \brief Mask for Ifx_MSC_DSC_Bits.NDBH */
+#define IFX_MSC_DSC_NDBH_MSK (0x1fu)
+
+/** \brief Offset for Ifx_MSC_DSC_Bits.NDBH */
+#define IFX_MSC_DSC_NDBH_OFF (8u)
+
+/** \brief Length for Ifx_MSC_DSC_Bits.NDBL */
+#define IFX_MSC_DSC_NDBL_LEN (5u)
+
+/** \brief Mask for Ifx_MSC_DSC_Bits.NDBL */
+#define IFX_MSC_DSC_NDBL_MSK (0x1fu)
+
+/** \brief Offset for Ifx_MSC_DSC_Bits.NDBL */
+#define IFX_MSC_DSC_NDBL_OFF (3u)
+
+/** \brief Length for Ifx_MSC_DSC_Bits.PPD */
+#define IFX_MSC_DSC_PPD_LEN (5u)
+
+/** \brief Mask for Ifx_MSC_DSC_Bits.PPD */
+#define IFX_MSC_DSC_PPD_MSK (0x1fu)
+
+/** \brief Offset for Ifx_MSC_DSC_Bits.PPD */
+#define IFX_MSC_DSC_PPD_OFF (24u)
+
+/** \brief Length for Ifx_MSC_DSC_Bits.TM */
+#define IFX_MSC_DSC_TM_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_DSC_Bits.TM */
+#define IFX_MSC_DSC_TM_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_DSC_Bits.TM */
+#define IFX_MSC_DSC_TM_OFF (0u)
+
+/** \brief Length for Ifx_MSC_DSCE_Bits.CCF */
+#define IFX_MSC_DSCE_CCF_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_DSCE_Bits.CCF */
+#define IFX_MSC_DSCE_CCF_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_DSCE_Bits.CCF */
+#define IFX_MSC_DSCE_CCF_OFF (15u)
+
+/** \brief Length for Ifx_MSC_DSCE_Bits.CDCM */
+#define IFX_MSC_DSCE_CDCM_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_DSCE_Bits.CDCM */
+#define IFX_MSC_DSCE_CDCM_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_DSCE_Bits.CDCM */
+#define IFX_MSC_DSCE_CDCM_OFF (31u)
+
+/** \brief Length for Ifx_MSC_DSCE_Bits.EXEN */
+#define IFX_MSC_DSCE_EXEN_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_DSCE_Bits.EXEN */
+#define IFX_MSC_DSCE_EXEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_DSCE_Bits.EXEN */
+#define IFX_MSC_DSCE_EXEN_OFF (14u)
+
+/** \brief Length for Ifx_MSC_DSCE_Bits.INJENP0 */
+#define IFX_MSC_DSCE_INJENP0_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_DSCE_Bits.INJENP0 */
+#define IFX_MSC_DSCE_INJENP0_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_DSCE_Bits.INJENP0 */
+#define IFX_MSC_DSCE_INJENP0_OFF (16u)
+
+/** \brief Length for Ifx_MSC_DSCE_Bits.INJENP1 */
+#define IFX_MSC_DSCE_INJENP1_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_DSCE_Bits.INJENP1 */
+#define IFX_MSC_DSCE_INJENP1_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_DSCE_Bits.INJENP1 */
+#define IFX_MSC_DSCE_INJENP1_OFF (24u)
+
+/** \brief Length for Ifx_MSC_DSCE_Bits.INJPOSP0 */
+#define IFX_MSC_DSCE_INJPOSP0_LEN (6u)
+
+/** \brief Mask for Ifx_MSC_DSCE_Bits.INJPOSP0 */
+#define IFX_MSC_DSCE_INJPOSP0_MSK (0x3fu)
+
+/** \brief Offset for Ifx_MSC_DSCE_Bits.INJPOSP0 */
+#define IFX_MSC_DSCE_INJPOSP0_OFF (17u)
+
+/** \brief Length for Ifx_MSC_DSCE_Bits.INJPOSP1 */
+#define IFX_MSC_DSCE_INJPOSP1_LEN (6u)
+
+/** \brief Mask for Ifx_MSC_DSCE_Bits.INJPOSP1 */
+#define IFX_MSC_DSCE_INJPOSP1_MSK (0x3fu)
+
+/** \brief Offset for Ifx_MSC_DSCE_Bits.INJPOSP1 */
+#define IFX_MSC_DSCE_INJPOSP1_OFF (25u)
+
+/** \brief Length for Ifx_MSC_DSCE_Bits.NDBHE */
+#define IFX_MSC_DSCE_NDBHE_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_DSCE_Bits.NDBHE */
+#define IFX_MSC_DSCE_NDBHE_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_DSCE_Bits.NDBHE */
+#define IFX_MSC_DSCE_NDBHE_OFF (0u)
+
+/** \brief Length for Ifx_MSC_DSCE_Bits.NDBLE */
+#define IFX_MSC_DSCE_NDBLE_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_DSCE_Bits.NDBLE */
+#define IFX_MSC_DSCE_NDBLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_DSCE_Bits.NDBLE */
+#define IFX_MSC_DSCE_NDBLE_OFF (1u)
+
+/** \brief Length for Ifx_MSC_DSDSH_Bits.SH0 */
+#define IFX_MSC_DSDSH_SH0_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSH_Bits.SH0 */
+#define IFX_MSC_DSDSH_SH0_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSH_Bits.SH0 */
+#define IFX_MSC_DSDSH_SH0_OFF (0u)
+
+/** \brief Length for Ifx_MSC_DSDSH_Bits.SH10 */
+#define IFX_MSC_DSDSH_SH10_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSH_Bits.SH10 */
+#define IFX_MSC_DSDSH_SH10_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSH_Bits.SH10 */
+#define IFX_MSC_DSDSH_SH10_OFF (20u)
+
+/** \brief Length for Ifx_MSC_DSDSH_Bits.SH11 */
+#define IFX_MSC_DSDSH_SH11_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSH_Bits.SH11 */
+#define IFX_MSC_DSDSH_SH11_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSH_Bits.SH11 */
+#define IFX_MSC_DSDSH_SH11_OFF (22u)
+
+/** \brief Length for Ifx_MSC_DSDSH_Bits.SH12 */
+#define IFX_MSC_DSDSH_SH12_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSH_Bits.SH12 */
+#define IFX_MSC_DSDSH_SH12_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSH_Bits.SH12 */
+#define IFX_MSC_DSDSH_SH12_OFF (24u)
+
+/** \brief Length for Ifx_MSC_DSDSH_Bits.SH13 */
+#define IFX_MSC_DSDSH_SH13_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSH_Bits.SH13 */
+#define IFX_MSC_DSDSH_SH13_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSH_Bits.SH13 */
+#define IFX_MSC_DSDSH_SH13_OFF (26u)
+
+/** \brief Length for Ifx_MSC_DSDSH_Bits.SH14 */
+#define IFX_MSC_DSDSH_SH14_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSH_Bits.SH14 */
+#define IFX_MSC_DSDSH_SH14_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSH_Bits.SH14 */
+#define IFX_MSC_DSDSH_SH14_OFF (28u)
+
+/** \brief Length for Ifx_MSC_DSDSH_Bits.SH15 */
+#define IFX_MSC_DSDSH_SH15_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSH_Bits.SH15 */
+#define IFX_MSC_DSDSH_SH15_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSH_Bits.SH15 */
+#define IFX_MSC_DSDSH_SH15_OFF (30u)
+
+/** \brief Length for Ifx_MSC_DSDSH_Bits.SH1 */
+#define IFX_MSC_DSDSH_SH1_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSH_Bits.SH1 */
+#define IFX_MSC_DSDSH_SH1_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSH_Bits.SH1 */
+#define IFX_MSC_DSDSH_SH1_OFF (2u)
+
+/** \brief Length for Ifx_MSC_DSDSH_Bits.SH2 */
+#define IFX_MSC_DSDSH_SH2_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSH_Bits.SH2 */
+#define IFX_MSC_DSDSH_SH2_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSH_Bits.SH2 */
+#define IFX_MSC_DSDSH_SH2_OFF (4u)
+
+/** \brief Length for Ifx_MSC_DSDSH_Bits.SH3 */
+#define IFX_MSC_DSDSH_SH3_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSH_Bits.SH3 */
+#define IFX_MSC_DSDSH_SH3_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSH_Bits.SH3 */
+#define IFX_MSC_DSDSH_SH3_OFF (6u)
+
+/** \brief Length for Ifx_MSC_DSDSH_Bits.SH4 */
+#define IFX_MSC_DSDSH_SH4_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSH_Bits.SH4 */
+#define IFX_MSC_DSDSH_SH4_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSH_Bits.SH4 */
+#define IFX_MSC_DSDSH_SH4_OFF (8u)
+
+/** \brief Length for Ifx_MSC_DSDSH_Bits.SH5 */
+#define IFX_MSC_DSDSH_SH5_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSH_Bits.SH5 */
+#define IFX_MSC_DSDSH_SH5_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSH_Bits.SH5 */
+#define IFX_MSC_DSDSH_SH5_OFF (10u)
+
+/** \brief Length for Ifx_MSC_DSDSH_Bits.SH6 */
+#define IFX_MSC_DSDSH_SH6_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSH_Bits.SH6 */
+#define IFX_MSC_DSDSH_SH6_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSH_Bits.SH6 */
+#define IFX_MSC_DSDSH_SH6_OFF (12u)
+
+/** \brief Length for Ifx_MSC_DSDSH_Bits.SH7 */
+#define IFX_MSC_DSDSH_SH7_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSH_Bits.SH7 */
+#define IFX_MSC_DSDSH_SH7_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSH_Bits.SH7 */
+#define IFX_MSC_DSDSH_SH7_OFF (14u)
+
+/** \brief Length for Ifx_MSC_DSDSH_Bits.SH8 */
+#define IFX_MSC_DSDSH_SH8_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSH_Bits.SH8 */
+#define IFX_MSC_DSDSH_SH8_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSH_Bits.SH8 */
+#define IFX_MSC_DSDSH_SH8_OFF (16u)
+
+/** \brief Length for Ifx_MSC_DSDSH_Bits.SH9 */
+#define IFX_MSC_DSDSH_SH9_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSH_Bits.SH9 */
+#define IFX_MSC_DSDSH_SH9_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSH_Bits.SH9 */
+#define IFX_MSC_DSDSH_SH9_OFF (18u)
+
+/** \brief Length for Ifx_MSC_DSDSHE_Bits.SH16 */
+#define IFX_MSC_DSDSHE_SH16_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSHE_Bits.SH16 */
+#define IFX_MSC_DSDSHE_SH16_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSHE_Bits.SH16 */
+#define IFX_MSC_DSDSHE_SH16_OFF (0u)
+
+/** \brief Length for Ifx_MSC_DSDSHE_Bits.SH17 */
+#define IFX_MSC_DSDSHE_SH17_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSHE_Bits.SH17 */
+#define IFX_MSC_DSDSHE_SH17_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSHE_Bits.SH17 */
+#define IFX_MSC_DSDSHE_SH17_OFF (2u)
+
+/** \brief Length for Ifx_MSC_DSDSHE_Bits.SH18 */
+#define IFX_MSC_DSDSHE_SH18_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSHE_Bits.SH18 */
+#define IFX_MSC_DSDSHE_SH18_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSHE_Bits.SH18 */
+#define IFX_MSC_DSDSHE_SH18_OFF (4u)
+
+/** \brief Length for Ifx_MSC_DSDSHE_Bits.SH19 */
+#define IFX_MSC_DSDSHE_SH19_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSHE_Bits.SH19 */
+#define IFX_MSC_DSDSHE_SH19_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSHE_Bits.SH19 */
+#define IFX_MSC_DSDSHE_SH19_OFF (6u)
+
+/** \brief Length for Ifx_MSC_DSDSHE_Bits.SH20 */
+#define IFX_MSC_DSDSHE_SH20_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSHE_Bits.SH20 */
+#define IFX_MSC_DSDSHE_SH20_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSHE_Bits.SH20 */
+#define IFX_MSC_DSDSHE_SH20_OFF (8u)
+
+/** \brief Length for Ifx_MSC_DSDSHE_Bits.SH21 */
+#define IFX_MSC_DSDSHE_SH21_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSHE_Bits.SH21 */
+#define IFX_MSC_DSDSHE_SH21_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSHE_Bits.SH21 */
+#define IFX_MSC_DSDSHE_SH21_OFF (10u)
+
+/** \brief Length for Ifx_MSC_DSDSHE_Bits.SH22 */
+#define IFX_MSC_DSDSHE_SH22_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSHE_Bits.SH22 */
+#define IFX_MSC_DSDSHE_SH22_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSHE_Bits.SH22 */
+#define IFX_MSC_DSDSHE_SH22_OFF (12u)
+
+/** \brief Length for Ifx_MSC_DSDSHE_Bits.SH23 */
+#define IFX_MSC_DSDSHE_SH23_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSHE_Bits.SH23 */
+#define IFX_MSC_DSDSHE_SH23_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSHE_Bits.SH23 */
+#define IFX_MSC_DSDSHE_SH23_OFF (14u)
+
+/** \brief Length for Ifx_MSC_DSDSHE_Bits.SH24 */
+#define IFX_MSC_DSDSHE_SH24_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSHE_Bits.SH24 */
+#define IFX_MSC_DSDSHE_SH24_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSHE_Bits.SH24 */
+#define IFX_MSC_DSDSHE_SH24_OFF (16u)
+
+/** \brief Length for Ifx_MSC_DSDSHE_Bits.SH25 */
+#define IFX_MSC_DSDSHE_SH25_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSHE_Bits.SH25 */
+#define IFX_MSC_DSDSHE_SH25_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSHE_Bits.SH25 */
+#define IFX_MSC_DSDSHE_SH25_OFF (18u)
+
+/** \brief Length for Ifx_MSC_DSDSHE_Bits.SH26 */
+#define IFX_MSC_DSDSHE_SH26_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSHE_Bits.SH26 */
+#define IFX_MSC_DSDSHE_SH26_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSHE_Bits.SH26 */
+#define IFX_MSC_DSDSHE_SH26_OFF (20u)
+
+/** \brief Length for Ifx_MSC_DSDSHE_Bits.SH27 */
+#define IFX_MSC_DSDSHE_SH27_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSHE_Bits.SH27 */
+#define IFX_MSC_DSDSHE_SH27_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSHE_Bits.SH27 */
+#define IFX_MSC_DSDSHE_SH27_OFF (22u)
+
+/** \brief Length for Ifx_MSC_DSDSHE_Bits.SH28 */
+#define IFX_MSC_DSDSHE_SH28_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSHE_Bits.SH28 */
+#define IFX_MSC_DSDSHE_SH28_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSHE_Bits.SH28 */
+#define IFX_MSC_DSDSHE_SH28_OFF (24u)
+
+/** \brief Length for Ifx_MSC_DSDSHE_Bits.SH29 */
+#define IFX_MSC_DSDSHE_SH29_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSHE_Bits.SH29 */
+#define IFX_MSC_DSDSHE_SH29_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSHE_Bits.SH29 */
+#define IFX_MSC_DSDSHE_SH29_OFF (26u)
+
+/** \brief Length for Ifx_MSC_DSDSHE_Bits.SH30 */
+#define IFX_MSC_DSDSHE_SH30_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSHE_Bits.SH30 */
+#define IFX_MSC_DSDSHE_SH30_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSHE_Bits.SH30 */
+#define IFX_MSC_DSDSHE_SH30_OFF (28u)
+
+/** \brief Length for Ifx_MSC_DSDSHE_Bits.SH31 */
+#define IFX_MSC_DSDSHE_SH31_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSHE_Bits.SH31 */
+#define IFX_MSC_DSDSHE_SH31_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSHE_Bits.SH31 */
+#define IFX_MSC_DSDSHE_SH31_OFF (30u)
+
+/** \brief Length for Ifx_MSC_DSDSL_Bits.SL0 */
+#define IFX_MSC_DSDSL_SL0_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSL_Bits.SL0 */
+#define IFX_MSC_DSDSL_SL0_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSL_Bits.SL0 */
+#define IFX_MSC_DSDSL_SL0_OFF (0u)
+
+/** \brief Length for Ifx_MSC_DSDSL_Bits.SL10 */
+#define IFX_MSC_DSDSL_SL10_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSL_Bits.SL10 */
+#define IFX_MSC_DSDSL_SL10_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSL_Bits.SL10 */
+#define IFX_MSC_DSDSL_SL10_OFF (20u)
+
+/** \brief Length for Ifx_MSC_DSDSL_Bits.SL11 */
+#define IFX_MSC_DSDSL_SL11_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSL_Bits.SL11 */
+#define IFX_MSC_DSDSL_SL11_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSL_Bits.SL11 */
+#define IFX_MSC_DSDSL_SL11_OFF (22u)
+
+/** \brief Length for Ifx_MSC_DSDSL_Bits.SL12 */
+#define IFX_MSC_DSDSL_SL12_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSL_Bits.SL12 */
+#define IFX_MSC_DSDSL_SL12_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSL_Bits.SL12 */
+#define IFX_MSC_DSDSL_SL12_OFF (24u)
+
+/** \brief Length for Ifx_MSC_DSDSL_Bits.SL13 */
+#define IFX_MSC_DSDSL_SL13_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSL_Bits.SL13 */
+#define IFX_MSC_DSDSL_SL13_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSL_Bits.SL13 */
+#define IFX_MSC_DSDSL_SL13_OFF (26u)
+
+/** \brief Length for Ifx_MSC_DSDSL_Bits.SL14 */
+#define IFX_MSC_DSDSL_SL14_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSL_Bits.SL14 */
+#define IFX_MSC_DSDSL_SL14_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSL_Bits.SL14 */
+#define IFX_MSC_DSDSL_SL14_OFF (28u)
+
+/** \brief Length for Ifx_MSC_DSDSL_Bits.SL15 */
+#define IFX_MSC_DSDSL_SL15_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSL_Bits.SL15 */
+#define IFX_MSC_DSDSL_SL15_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSL_Bits.SL15 */
+#define IFX_MSC_DSDSL_SL15_OFF (30u)
+
+/** \brief Length for Ifx_MSC_DSDSL_Bits.SL1 */
+#define IFX_MSC_DSDSL_SL1_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSL_Bits.SL1 */
+#define IFX_MSC_DSDSL_SL1_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSL_Bits.SL1 */
+#define IFX_MSC_DSDSL_SL1_OFF (2u)
+
+/** \brief Length for Ifx_MSC_DSDSL_Bits.SL2 */
+#define IFX_MSC_DSDSL_SL2_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSL_Bits.SL2 */
+#define IFX_MSC_DSDSL_SL2_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSL_Bits.SL2 */
+#define IFX_MSC_DSDSL_SL2_OFF (4u)
+
+/** \brief Length for Ifx_MSC_DSDSL_Bits.SL3 */
+#define IFX_MSC_DSDSL_SL3_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSL_Bits.SL3 */
+#define IFX_MSC_DSDSL_SL3_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSL_Bits.SL3 */
+#define IFX_MSC_DSDSL_SL3_OFF (6u)
+
+/** \brief Length for Ifx_MSC_DSDSL_Bits.SL4 */
+#define IFX_MSC_DSDSL_SL4_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSL_Bits.SL4 */
+#define IFX_MSC_DSDSL_SL4_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSL_Bits.SL4 */
+#define IFX_MSC_DSDSL_SL4_OFF (8u)
+
+/** \brief Length for Ifx_MSC_DSDSL_Bits.SL5 */
+#define IFX_MSC_DSDSL_SL5_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSL_Bits.SL5 */
+#define IFX_MSC_DSDSL_SL5_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSL_Bits.SL5 */
+#define IFX_MSC_DSDSL_SL5_OFF (10u)
+
+/** \brief Length for Ifx_MSC_DSDSL_Bits.SL6 */
+#define IFX_MSC_DSDSL_SL6_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSL_Bits.SL6 */
+#define IFX_MSC_DSDSL_SL6_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSL_Bits.SL6 */
+#define IFX_MSC_DSDSL_SL6_OFF (12u)
+
+/** \brief Length for Ifx_MSC_DSDSL_Bits.SL7 */
+#define IFX_MSC_DSDSL_SL7_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSL_Bits.SL7 */
+#define IFX_MSC_DSDSL_SL7_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSL_Bits.SL7 */
+#define IFX_MSC_DSDSL_SL7_OFF (14u)
+
+/** \brief Length for Ifx_MSC_DSDSL_Bits.SL8 */
+#define IFX_MSC_DSDSL_SL8_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSL_Bits.SL8 */
+#define IFX_MSC_DSDSL_SL8_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSL_Bits.SL8 */
+#define IFX_MSC_DSDSL_SL8_OFF (16u)
+
+/** \brief Length for Ifx_MSC_DSDSL_Bits.SL9 */
+#define IFX_MSC_DSDSL_SL9_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSL_Bits.SL9 */
+#define IFX_MSC_DSDSL_SL9_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSL_Bits.SL9 */
+#define IFX_MSC_DSDSL_SL9_OFF (18u)
+
+/** \brief Length for Ifx_MSC_DSDSLE_Bits.SL16 */
+#define IFX_MSC_DSDSLE_SL16_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSLE_Bits.SL16 */
+#define IFX_MSC_DSDSLE_SL16_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSLE_Bits.SL16 */
+#define IFX_MSC_DSDSLE_SL16_OFF (0u)
+
+/** \brief Length for Ifx_MSC_DSDSLE_Bits.SL17 */
+#define IFX_MSC_DSDSLE_SL17_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSLE_Bits.SL17 */
+#define IFX_MSC_DSDSLE_SL17_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSLE_Bits.SL17 */
+#define IFX_MSC_DSDSLE_SL17_OFF (2u)
+
+/** \brief Length for Ifx_MSC_DSDSLE_Bits.SL18 */
+#define IFX_MSC_DSDSLE_SL18_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSLE_Bits.SL18 */
+#define IFX_MSC_DSDSLE_SL18_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSLE_Bits.SL18 */
+#define IFX_MSC_DSDSLE_SL18_OFF (4u)
+
+/** \brief Length for Ifx_MSC_DSDSLE_Bits.SL19 */
+#define IFX_MSC_DSDSLE_SL19_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSLE_Bits.SL19 */
+#define IFX_MSC_DSDSLE_SL19_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSLE_Bits.SL19 */
+#define IFX_MSC_DSDSLE_SL19_OFF (6u)
+
+/** \brief Length for Ifx_MSC_DSDSLE_Bits.SL20 */
+#define IFX_MSC_DSDSLE_SL20_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSLE_Bits.SL20 */
+#define IFX_MSC_DSDSLE_SL20_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSLE_Bits.SL20 */
+#define IFX_MSC_DSDSLE_SL20_OFF (8u)
+
+/** \brief Length for Ifx_MSC_DSDSLE_Bits.SL21 */
+#define IFX_MSC_DSDSLE_SL21_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSLE_Bits.SL21 */
+#define IFX_MSC_DSDSLE_SL21_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSLE_Bits.SL21 */
+#define IFX_MSC_DSDSLE_SL21_OFF (10u)
+
+/** \brief Length for Ifx_MSC_DSDSLE_Bits.SL22 */
+#define IFX_MSC_DSDSLE_SL22_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSLE_Bits.SL22 */
+#define IFX_MSC_DSDSLE_SL22_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSLE_Bits.SL22 */
+#define IFX_MSC_DSDSLE_SL22_OFF (12u)
+
+/** \brief Length for Ifx_MSC_DSDSLE_Bits.SL23 */
+#define IFX_MSC_DSDSLE_SL23_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSLE_Bits.SL23 */
+#define IFX_MSC_DSDSLE_SL23_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSLE_Bits.SL23 */
+#define IFX_MSC_DSDSLE_SL23_OFF (14u)
+
+/** \brief Length for Ifx_MSC_DSDSLE_Bits.SL24 */
+#define IFX_MSC_DSDSLE_SL24_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSLE_Bits.SL24 */
+#define IFX_MSC_DSDSLE_SL24_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSLE_Bits.SL24 */
+#define IFX_MSC_DSDSLE_SL24_OFF (16u)
+
+/** \brief Length for Ifx_MSC_DSDSLE_Bits.SL25 */
+#define IFX_MSC_DSDSLE_SL25_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSLE_Bits.SL25 */
+#define IFX_MSC_DSDSLE_SL25_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSLE_Bits.SL25 */
+#define IFX_MSC_DSDSLE_SL25_OFF (18u)
+
+/** \brief Length for Ifx_MSC_DSDSLE_Bits.SL26 */
+#define IFX_MSC_DSDSLE_SL26_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSLE_Bits.SL26 */
+#define IFX_MSC_DSDSLE_SL26_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSLE_Bits.SL26 */
+#define IFX_MSC_DSDSLE_SL26_OFF (20u)
+
+/** \brief Length for Ifx_MSC_DSDSLE_Bits.SL27 */
+#define IFX_MSC_DSDSLE_SL27_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSLE_Bits.SL27 */
+#define IFX_MSC_DSDSLE_SL27_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSLE_Bits.SL27 */
+#define IFX_MSC_DSDSLE_SL27_OFF (22u)
+
+/** \brief Length for Ifx_MSC_DSDSLE_Bits.SL28 */
+#define IFX_MSC_DSDSLE_SL28_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSLE_Bits.SL28 */
+#define IFX_MSC_DSDSLE_SL28_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSLE_Bits.SL28 */
+#define IFX_MSC_DSDSLE_SL28_OFF (24u)
+
+/** \brief Length for Ifx_MSC_DSDSLE_Bits.SL29 */
+#define IFX_MSC_DSDSLE_SL29_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSLE_Bits.SL29 */
+#define IFX_MSC_DSDSLE_SL29_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSLE_Bits.SL29 */
+#define IFX_MSC_DSDSLE_SL29_OFF (26u)
+
+/** \brief Length for Ifx_MSC_DSDSLE_Bits.SL30 */
+#define IFX_MSC_DSDSLE_SL30_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSLE_Bits.SL30 */
+#define IFX_MSC_DSDSLE_SL30_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSLE_Bits.SL30 */
+#define IFX_MSC_DSDSLE_SL30_OFF (28u)
+
+/** \brief Length for Ifx_MSC_DSDSLE_Bits.SL31 */
+#define IFX_MSC_DSDSLE_SL31_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSDSLE_Bits.SL31 */
+#define IFX_MSC_DSDSLE_SL31_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSDSLE_Bits.SL31 */
+#define IFX_MSC_DSDSLE_SL31_OFF (30u)
+
+/** \brief Length for Ifx_MSC_DSS_Bits.CFA */
+#define IFX_MSC_DSS_CFA_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_DSS_Bits.CFA */
+#define IFX_MSC_DSS_CFA_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_DSS_Bits.CFA */
+#define IFX_MSC_DSS_CFA_OFF (25u)
+
+/** \brief Length for Ifx_MSC_DSS_Bits.DC */
+#define IFX_MSC_DSS_DC_LEN (8u)
+
+/** \brief Mask for Ifx_MSC_DSS_Bits.DC */
+#define IFX_MSC_DSS_DC_MSK (0xffu)
+
+/** \brief Offset for Ifx_MSC_DSS_Bits.DC */
+#define IFX_MSC_DSS_DC_OFF (16u)
+
+/** \brief Length for Ifx_MSC_DSS_Bits.DFA */
+#define IFX_MSC_DSS_DFA_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_DSS_Bits.DFA */
+#define IFX_MSC_DSS_DFA_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_DSS_Bits.DFA */
+#define IFX_MSC_DSS_DFA_OFF (24u)
+
+/** \brief Length for Ifx_MSC_DSS_Bits.NPTF */
+#define IFX_MSC_DSS_NPTF_LEN (4u)
+
+/** \brief Mask for Ifx_MSC_DSS_Bits.NPTF */
+#define IFX_MSC_DSS_NPTF_MSK (0xfu)
+
+/** \brief Offset for Ifx_MSC_DSS_Bits.NPTF */
+#define IFX_MSC_DSS_NPTF_OFF (8u)
+
+/** \brief Length for Ifx_MSC_DSS_Bits.PFC */
+#define IFX_MSC_DSS_PFC_LEN (4u)
+
+/** \brief Mask for Ifx_MSC_DSS_Bits.PFC */
+#define IFX_MSC_DSS_PFC_MSK (0xfu)
+
+/** \brief Offset for Ifx_MSC_DSS_Bits.PFC */
+#define IFX_MSC_DSS_PFC_OFF (0u)
+
+/** \brief Length for Ifx_MSC_DSTE_Bits.NDD */
+#define IFX_MSC_DSTE_NDD_LEN (4u)
+
+/** \brief Mask for Ifx_MSC_DSTE_Bits.NDD */
+#define IFX_MSC_DSTE_NDD_MSK (0xfu)
+
+/** \brief Offset for Ifx_MSC_DSTE_Bits.NDD */
+#define IFX_MSC_DSTE_NDD_OFF (8u)
+
+/** \brief Length for Ifx_MSC_DSTE_Bits.PPCE */
+#define IFX_MSC_DSTE_PPCE_LEN (6u)
+
+/** \brief Mask for Ifx_MSC_DSTE_Bits.PPCE */
+#define IFX_MSC_DSTE_PPCE_MSK (0x3fu)
+
+/** \brief Offset for Ifx_MSC_DSTE_Bits.PPCE */
+#define IFX_MSC_DSTE_PPCE_OFF (2u)
+
+/** \brief Length for Ifx_MSC_DSTE_Bits.PPDE */
+#define IFX_MSC_DSTE_PPDE_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_DSTE_Bits.PPDE */
+#define IFX_MSC_DSTE_PPDE_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_DSTE_Bits.PPDE */
+#define IFX_MSC_DSTE_PPDE_OFF (0u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENH0 */
+#define IFX_MSC_ESR_ENH0_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENH0 */
+#define IFX_MSC_ESR_ENH0_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENH0 */
+#define IFX_MSC_ESR_ENH0_OFF (16u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENH10 */
+#define IFX_MSC_ESR_ENH10_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENH10 */
+#define IFX_MSC_ESR_ENH10_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENH10 */
+#define IFX_MSC_ESR_ENH10_OFF (26u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENH11 */
+#define IFX_MSC_ESR_ENH11_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENH11 */
+#define IFX_MSC_ESR_ENH11_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENH11 */
+#define IFX_MSC_ESR_ENH11_OFF (27u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENH12 */
+#define IFX_MSC_ESR_ENH12_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENH12 */
+#define IFX_MSC_ESR_ENH12_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENH12 */
+#define IFX_MSC_ESR_ENH12_OFF (28u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENH13 */
+#define IFX_MSC_ESR_ENH13_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENH13 */
+#define IFX_MSC_ESR_ENH13_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENH13 */
+#define IFX_MSC_ESR_ENH13_OFF (29u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENH14 */
+#define IFX_MSC_ESR_ENH14_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENH14 */
+#define IFX_MSC_ESR_ENH14_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENH14 */
+#define IFX_MSC_ESR_ENH14_OFF (30u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENH15 */
+#define IFX_MSC_ESR_ENH15_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENH15 */
+#define IFX_MSC_ESR_ENH15_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENH15 */
+#define IFX_MSC_ESR_ENH15_OFF (31u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENH1 */
+#define IFX_MSC_ESR_ENH1_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENH1 */
+#define IFX_MSC_ESR_ENH1_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENH1 */
+#define IFX_MSC_ESR_ENH1_OFF (17u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENH2 */
+#define IFX_MSC_ESR_ENH2_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENH2 */
+#define IFX_MSC_ESR_ENH2_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENH2 */
+#define IFX_MSC_ESR_ENH2_OFF (18u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENH3 */
+#define IFX_MSC_ESR_ENH3_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENH3 */
+#define IFX_MSC_ESR_ENH3_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENH3 */
+#define IFX_MSC_ESR_ENH3_OFF (19u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENH4 */
+#define IFX_MSC_ESR_ENH4_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENH4 */
+#define IFX_MSC_ESR_ENH4_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENH4 */
+#define IFX_MSC_ESR_ENH4_OFF (20u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENH5 */
+#define IFX_MSC_ESR_ENH5_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENH5 */
+#define IFX_MSC_ESR_ENH5_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENH5 */
+#define IFX_MSC_ESR_ENH5_OFF (21u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENH6 */
+#define IFX_MSC_ESR_ENH6_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENH6 */
+#define IFX_MSC_ESR_ENH6_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENH6 */
+#define IFX_MSC_ESR_ENH6_OFF (22u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENH7 */
+#define IFX_MSC_ESR_ENH7_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENH7 */
+#define IFX_MSC_ESR_ENH7_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENH7 */
+#define IFX_MSC_ESR_ENH7_OFF (23u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENH8 */
+#define IFX_MSC_ESR_ENH8_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENH8 */
+#define IFX_MSC_ESR_ENH8_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENH8 */
+#define IFX_MSC_ESR_ENH8_OFF (24u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENH9 */
+#define IFX_MSC_ESR_ENH9_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENH9 */
+#define IFX_MSC_ESR_ENH9_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENH9 */
+#define IFX_MSC_ESR_ENH9_OFF (25u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENL0 */
+#define IFX_MSC_ESR_ENL0_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENL0 */
+#define IFX_MSC_ESR_ENL0_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENL0 */
+#define IFX_MSC_ESR_ENL0_OFF (0u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENL10 */
+#define IFX_MSC_ESR_ENL10_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENL10 */
+#define IFX_MSC_ESR_ENL10_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENL10 */
+#define IFX_MSC_ESR_ENL10_OFF (10u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENL11 */
+#define IFX_MSC_ESR_ENL11_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENL11 */
+#define IFX_MSC_ESR_ENL11_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENL11 */
+#define IFX_MSC_ESR_ENL11_OFF (11u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENL12 */
+#define IFX_MSC_ESR_ENL12_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENL12 */
+#define IFX_MSC_ESR_ENL12_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENL12 */
+#define IFX_MSC_ESR_ENL12_OFF (12u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENL13 */
+#define IFX_MSC_ESR_ENL13_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENL13 */
+#define IFX_MSC_ESR_ENL13_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENL13 */
+#define IFX_MSC_ESR_ENL13_OFF (13u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENL14 */
+#define IFX_MSC_ESR_ENL14_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENL14 */
+#define IFX_MSC_ESR_ENL14_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENL14 */
+#define IFX_MSC_ESR_ENL14_OFF (14u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENL15 */
+#define IFX_MSC_ESR_ENL15_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENL15 */
+#define IFX_MSC_ESR_ENL15_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENL15 */
+#define IFX_MSC_ESR_ENL15_OFF (15u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENL1 */
+#define IFX_MSC_ESR_ENL1_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENL1 */
+#define IFX_MSC_ESR_ENL1_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENL1 */
+#define IFX_MSC_ESR_ENL1_OFF (1u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENL2 */
+#define IFX_MSC_ESR_ENL2_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENL2 */
+#define IFX_MSC_ESR_ENL2_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENL2 */
+#define IFX_MSC_ESR_ENL2_OFF (2u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENL3 */
+#define IFX_MSC_ESR_ENL3_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENL3 */
+#define IFX_MSC_ESR_ENL3_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENL3 */
+#define IFX_MSC_ESR_ENL3_OFF (3u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENL4 */
+#define IFX_MSC_ESR_ENL4_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENL4 */
+#define IFX_MSC_ESR_ENL4_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENL4 */
+#define IFX_MSC_ESR_ENL4_OFF (4u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENL5 */
+#define IFX_MSC_ESR_ENL5_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENL5 */
+#define IFX_MSC_ESR_ENL5_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENL5 */
+#define IFX_MSC_ESR_ENL5_OFF (5u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENL6 */
+#define IFX_MSC_ESR_ENL6_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENL6 */
+#define IFX_MSC_ESR_ENL6_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENL6 */
+#define IFX_MSC_ESR_ENL6_OFF (6u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENL7 */
+#define IFX_MSC_ESR_ENL7_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENL7 */
+#define IFX_MSC_ESR_ENL7_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENL7 */
+#define IFX_MSC_ESR_ENL7_OFF (7u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENL8 */
+#define IFX_MSC_ESR_ENL8_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENL8 */
+#define IFX_MSC_ESR_ENL8_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENL8 */
+#define IFX_MSC_ESR_ENL8_OFF (8u)
+
+/** \brief Length for Ifx_MSC_ESR_Bits.ENL9 */
+#define IFX_MSC_ESR_ENL9_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESR_Bits.ENL9 */
+#define IFX_MSC_ESR_ENL9_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESR_Bits.ENL9 */
+#define IFX_MSC_ESR_ENL9_OFF (9u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENH16 */
+#define IFX_MSC_ESRE_ENH16_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENH16 */
+#define IFX_MSC_ESRE_ENH16_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENH16 */
+#define IFX_MSC_ESRE_ENH16_OFF (16u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENH17 */
+#define IFX_MSC_ESRE_ENH17_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENH17 */
+#define IFX_MSC_ESRE_ENH17_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENH17 */
+#define IFX_MSC_ESRE_ENH17_OFF (17u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENH18 */
+#define IFX_MSC_ESRE_ENH18_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENH18 */
+#define IFX_MSC_ESRE_ENH18_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENH18 */
+#define IFX_MSC_ESRE_ENH18_OFF (18u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENH19 */
+#define IFX_MSC_ESRE_ENH19_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENH19 */
+#define IFX_MSC_ESRE_ENH19_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENH19 */
+#define IFX_MSC_ESRE_ENH19_OFF (19u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENH20 */
+#define IFX_MSC_ESRE_ENH20_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENH20 */
+#define IFX_MSC_ESRE_ENH20_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENH20 */
+#define IFX_MSC_ESRE_ENH20_OFF (20u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENH21 */
+#define IFX_MSC_ESRE_ENH21_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENH21 */
+#define IFX_MSC_ESRE_ENH21_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENH21 */
+#define IFX_MSC_ESRE_ENH21_OFF (21u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENH22 */
+#define IFX_MSC_ESRE_ENH22_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENH22 */
+#define IFX_MSC_ESRE_ENH22_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENH22 */
+#define IFX_MSC_ESRE_ENH22_OFF (22u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENH23 */
+#define IFX_MSC_ESRE_ENH23_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENH23 */
+#define IFX_MSC_ESRE_ENH23_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENH23 */
+#define IFX_MSC_ESRE_ENH23_OFF (23u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENH24 */
+#define IFX_MSC_ESRE_ENH24_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENH24 */
+#define IFX_MSC_ESRE_ENH24_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENH24 */
+#define IFX_MSC_ESRE_ENH24_OFF (24u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENH25 */
+#define IFX_MSC_ESRE_ENH25_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENH25 */
+#define IFX_MSC_ESRE_ENH25_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENH25 */
+#define IFX_MSC_ESRE_ENH25_OFF (25u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENH26 */
+#define IFX_MSC_ESRE_ENH26_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENH26 */
+#define IFX_MSC_ESRE_ENH26_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENH26 */
+#define IFX_MSC_ESRE_ENH26_OFF (26u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENH27 */
+#define IFX_MSC_ESRE_ENH27_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENH27 */
+#define IFX_MSC_ESRE_ENH27_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENH27 */
+#define IFX_MSC_ESRE_ENH27_OFF (27u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENH28 */
+#define IFX_MSC_ESRE_ENH28_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENH28 */
+#define IFX_MSC_ESRE_ENH28_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENH28 */
+#define IFX_MSC_ESRE_ENH28_OFF (28u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENH29 */
+#define IFX_MSC_ESRE_ENH29_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENH29 */
+#define IFX_MSC_ESRE_ENH29_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENH29 */
+#define IFX_MSC_ESRE_ENH29_OFF (29u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENH30 */
+#define IFX_MSC_ESRE_ENH30_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENH30 */
+#define IFX_MSC_ESRE_ENH30_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENH30 */
+#define IFX_MSC_ESRE_ENH30_OFF (30u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENH31 */
+#define IFX_MSC_ESRE_ENH31_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENH31 */
+#define IFX_MSC_ESRE_ENH31_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENH31 */
+#define IFX_MSC_ESRE_ENH31_OFF (31u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENL16 */
+#define IFX_MSC_ESRE_ENL16_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENL16 */
+#define IFX_MSC_ESRE_ENL16_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENL16 */
+#define IFX_MSC_ESRE_ENL16_OFF (0u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENL17 */
+#define IFX_MSC_ESRE_ENL17_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENL17 */
+#define IFX_MSC_ESRE_ENL17_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENL17 */
+#define IFX_MSC_ESRE_ENL17_OFF (1u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENL18 */
+#define IFX_MSC_ESRE_ENL18_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENL18 */
+#define IFX_MSC_ESRE_ENL18_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENL18 */
+#define IFX_MSC_ESRE_ENL18_OFF (2u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENL19 */
+#define IFX_MSC_ESRE_ENL19_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENL19 */
+#define IFX_MSC_ESRE_ENL19_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENL19 */
+#define IFX_MSC_ESRE_ENL19_OFF (3u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENL20 */
+#define IFX_MSC_ESRE_ENL20_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENL20 */
+#define IFX_MSC_ESRE_ENL20_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENL20 */
+#define IFX_MSC_ESRE_ENL20_OFF (4u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENL21 */
+#define IFX_MSC_ESRE_ENL21_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENL21 */
+#define IFX_MSC_ESRE_ENL21_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENL21 */
+#define IFX_MSC_ESRE_ENL21_OFF (5u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENL22 */
+#define IFX_MSC_ESRE_ENL22_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENL22 */
+#define IFX_MSC_ESRE_ENL22_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENL22 */
+#define IFX_MSC_ESRE_ENL22_OFF (6u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENL23 */
+#define IFX_MSC_ESRE_ENL23_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENL23 */
+#define IFX_MSC_ESRE_ENL23_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENL23 */
+#define IFX_MSC_ESRE_ENL23_OFF (7u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENL24 */
+#define IFX_MSC_ESRE_ENL24_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENL24 */
+#define IFX_MSC_ESRE_ENL24_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENL24 */
+#define IFX_MSC_ESRE_ENL24_OFF (8u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENL25 */
+#define IFX_MSC_ESRE_ENL25_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENL25 */
+#define IFX_MSC_ESRE_ENL25_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENL25 */
+#define IFX_MSC_ESRE_ENL25_OFF (9u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENL26 */
+#define IFX_MSC_ESRE_ENL26_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENL26 */
+#define IFX_MSC_ESRE_ENL26_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENL26 */
+#define IFX_MSC_ESRE_ENL26_OFF (10u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENL27 */
+#define IFX_MSC_ESRE_ENL27_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENL27 */
+#define IFX_MSC_ESRE_ENL27_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENL27 */
+#define IFX_MSC_ESRE_ENL27_OFF (11u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENL28 */
+#define IFX_MSC_ESRE_ENL28_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENL28 */
+#define IFX_MSC_ESRE_ENL28_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENL28 */
+#define IFX_MSC_ESRE_ENL28_OFF (12u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENL29 */
+#define IFX_MSC_ESRE_ENL29_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENL29 */
+#define IFX_MSC_ESRE_ENL29_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENL29 */
+#define IFX_MSC_ESRE_ENL29_OFF (13u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENL30 */
+#define IFX_MSC_ESRE_ENL30_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENL30 */
+#define IFX_MSC_ESRE_ENL30_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENL30 */
+#define IFX_MSC_ESRE_ENL30_OFF (14u)
+
+/** \brief Length for Ifx_MSC_ESRE_Bits.ENL31 */
+#define IFX_MSC_ESRE_ENL31_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ESRE_Bits.ENL31 */
+#define IFX_MSC_ESRE_ENL31_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ESRE_Bits.ENL31 */
+#define IFX_MSC_ESRE_ENL31_OFF (15u)
+
+/** \brief Length for Ifx_MSC_FDR_Bits.DISCLK */
+#define IFX_MSC_FDR_DISCLK_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_FDR_Bits.DISCLK */
+#define IFX_MSC_FDR_DISCLK_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_FDR_Bits.DISCLK */
+#define IFX_MSC_FDR_DISCLK_OFF (31u)
+
+/** \brief Length for Ifx_MSC_FDR_Bits.DM */
+#define IFX_MSC_FDR_DM_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_FDR_Bits.DM */
+#define IFX_MSC_FDR_DM_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_FDR_Bits.DM */
+#define IFX_MSC_FDR_DM_OFF (14u)
+
+/** \brief Length for Ifx_MSC_FDR_Bits.ENHW */
+#define IFX_MSC_FDR_ENHW_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_FDR_Bits.ENHW */
+#define IFX_MSC_FDR_ENHW_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_FDR_Bits.ENHW */
+#define IFX_MSC_FDR_ENHW_OFF (30u)
+
+/** \brief Length for Ifx_MSC_FDR_Bits.RESULT */
+#define IFX_MSC_FDR_RESULT_LEN (10u)
+
+/** \brief Mask for Ifx_MSC_FDR_Bits.RESULT */
+#define IFX_MSC_FDR_RESULT_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_MSC_FDR_Bits.RESULT */
+#define IFX_MSC_FDR_RESULT_OFF (16u)
+
+/** \brief Length for Ifx_MSC_FDR_Bits.STEP */
+#define IFX_MSC_FDR_STEP_LEN (10u)
+
+/** \brief Mask for Ifx_MSC_FDR_Bits.STEP */
+#define IFX_MSC_FDR_STEP_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_MSC_FDR_Bits.STEP */
+#define IFX_MSC_FDR_STEP_OFF (0u)
+
+/** \brief Length for Ifx_MSC_ICR_Bits.ECIE */
+#define IFX_MSC_ICR_ECIE_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ICR_Bits.ECIE */
+#define IFX_MSC_ICR_ECIE_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ICR_Bits.ECIE */
+#define IFX_MSC_ICR_ECIE_OFF (7u)
+
+/** \brief Length for Ifx_MSC_ICR_Bits.ECIP */
+#define IFX_MSC_ICR_ECIP_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_ICR_Bits.ECIP */
+#define IFX_MSC_ICR_ECIP_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_ICR_Bits.ECIP */
+#define IFX_MSC_ICR_ECIP_OFF (4u)
+
+/** \brief Length for Ifx_MSC_ICR_Bits.EDIE */
+#define IFX_MSC_ICR_EDIE_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_ICR_Bits.EDIE */
+#define IFX_MSC_ICR_EDIE_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_ICR_Bits.EDIE */
+#define IFX_MSC_ICR_EDIE_OFF (2u)
+
+/** \brief Length for Ifx_MSC_ICR_Bits.EDIP */
+#define IFX_MSC_ICR_EDIP_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_ICR_Bits.EDIP */
+#define IFX_MSC_ICR_EDIP_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_ICR_Bits.EDIP */
+#define IFX_MSC_ICR_EDIP_OFF (0u)
+
+/** \brief Length for Ifx_MSC_ICR_Bits.RDIE */
+#define IFX_MSC_ICR_RDIE_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_ICR_Bits.RDIE */
+#define IFX_MSC_ICR_RDIE_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_ICR_Bits.RDIE */
+#define IFX_MSC_ICR_RDIE_OFF (14u)
+
+/** \brief Length for Ifx_MSC_ICR_Bits.RDIP */
+#define IFX_MSC_ICR_RDIP_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_ICR_Bits.RDIP */
+#define IFX_MSC_ICR_RDIP_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_ICR_Bits.RDIP */
+#define IFX_MSC_ICR_RDIP_OFF (12u)
+
+/** \brief Length for Ifx_MSC_ICR_Bits.TFIE */
+#define IFX_MSC_ICR_TFIE_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ICR_Bits.TFIE */
+#define IFX_MSC_ICR_TFIE_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ICR_Bits.TFIE */
+#define IFX_MSC_ICR_TFIE_OFF (11u)
+
+/** \brief Length for Ifx_MSC_ICR_Bits.TFIP */
+#define IFX_MSC_ICR_TFIP_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_ICR_Bits.TFIP */
+#define IFX_MSC_ICR_TFIP_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_ICR_Bits.TFIP */
+#define IFX_MSC_ICR_TFIP_OFF (8u)
+
+/** \brief Length for Ifx_MSC_ID_Bits.MODNUMBER */
+#define IFX_MSC_ID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_MSC_ID_Bits.MODNUMBER */
+#define IFX_MSC_ID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_MSC_ID_Bits.MODNUMBER */
+#define IFX_MSC_ID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_MSC_ID_Bits.MODREV */
+#define IFX_MSC_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_MSC_ID_Bits.MODREV */
+#define IFX_MSC_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_MSC_ID_Bits.MODREV */
+#define IFX_MSC_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_MSC_ID_Bits.MODTYPE */
+#define IFX_MSC_ID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_MSC_ID_Bits.MODTYPE */
+#define IFX_MSC_ID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_MSC_ID_Bits.MODTYPE */
+#define IFX_MSC_ID_MODTYPE_OFF (8u)
+
+/** \brief Length for Ifx_MSC_ISC_Bits.CCP */
+#define IFX_MSC_ISC_CCP_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ISC_Bits.CCP */
+#define IFX_MSC_ISC_CCP_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ISC_Bits.CCP */
+#define IFX_MSC_ISC_CCP_OFF (5u)
+
+/** \brief Length for Ifx_MSC_ISC_Bits.CDDIS */
+#define IFX_MSC_ISC_CDDIS_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ISC_Bits.CDDIS */
+#define IFX_MSC_ISC_CDDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ISC_Bits.CDDIS */
+#define IFX_MSC_ISC_CDDIS_OFF (6u)
+
+/** \brief Length for Ifx_MSC_ISC_Bits.CDECI */
+#define IFX_MSC_ISC_CDECI_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ISC_Bits.CDECI */
+#define IFX_MSC_ISC_CDECI_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ISC_Bits.CDECI */
+#define IFX_MSC_ISC_CDECI_OFF (1u)
+
+/** \brief Length for Ifx_MSC_ISC_Bits.CDEDI */
+#define IFX_MSC_ISC_CDEDI_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ISC_Bits.CDEDI */
+#define IFX_MSC_ISC_CDEDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ISC_Bits.CDEDI */
+#define IFX_MSC_ISC_CDEDI_OFF (0u)
+
+/** \brief Length for Ifx_MSC_ISC_Bits.CDP */
+#define IFX_MSC_ISC_CDP_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ISC_Bits.CDP */
+#define IFX_MSC_ISC_CDP_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ISC_Bits.CDP */
+#define IFX_MSC_ISC_CDP_OFF (4u)
+
+/** \brief Length for Ifx_MSC_ISC_Bits.CDTFI */
+#define IFX_MSC_ISC_CDTFI_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ISC_Bits.CDTFI */
+#define IFX_MSC_ISC_CDTFI_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ISC_Bits.CDTFI */
+#define IFX_MSC_ISC_CDTFI_OFF (2u)
+
+/** \brief Length for Ifx_MSC_ISC_Bits.CURDI */
+#define IFX_MSC_ISC_CURDI_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ISC_Bits.CURDI */
+#define IFX_MSC_ISC_CURDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ISC_Bits.CURDI */
+#define IFX_MSC_ISC_CURDI_OFF (3u)
+
+/** \brief Length for Ifx_MSC_ISC_Bits.SCP */
+#define IFX_MSC_ISC_SCP_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ISC_Bits.SCP */
+#define IFX_MSC_ISC_SCP_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ISC_Bits.SCP */
+#define IFX_MSC_ISC_SCP_OFF (21u)
+
+/** \brief Length for Ifx_MSC_ISC_Bits.SDDIS */
+#define IFX_MSC_ISC_SDDIS_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ISC_Bits.SDDIS */
+#define IFX_MSC_ISC_SDDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ISC_Bits.SDDIS */
+#define IFX_MSC_ISC_SDDIS_OFF (22u)
+
+/** \brief Length for Ifx_MSC_ISC_Bits.SDECI */
+#define IFX_MSC_ISC_SDECI_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ISC_Bits.SDECI */
+#define IFX_MSC_ISC_SDECI_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ISC_Bits.SDECI */
+#define IFX_MSC_ISC_SDECI_OFF (17u)
+
+/** \brief Length for Ifx_MSC_ISC_Bits.SDEDI */
+#define IFX_MSC_ISC_SDEDI_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ISC_Bits.SDEDI */
+#define IFX_MSC_ISC_SDEDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ISC_Bits.SDEDI */
+#define IFX_MSC_ISC_SDEDI_OFF (16u)
+
+/** \brief Length for Ifx_MSC_ISC_Bits.SDP */
+#define IFX_MSC_ISC_SDP_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ISC_Bits.SDP */
+#define IFX_MSC_ISC_SDP_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ISC_Bits.SDP */
+#define IFX_MSC_ISC_SDP_OFF (20u)
+
+/** \brief Length for Ifx_MSC_ISC_Bits.SDTFI */
+#define IFX_MSC_ISC_SDTFI_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ISC_Bits.SDTFI */
+#define IFX_MSC_ISC_SDTFI_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ISC_Bits.SDTFI */
+#define IFX_MSC_ISC_SDTFI_OFF (18u)
+
+/** \brief Length for Ifx_MSC_ISC_Bits.SURDI */
+#define IFX_MSC_ISC_SURDI_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ISC_Bits.SURDI */
+#define IFX_MSC_ISC_SURDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ISC_Bits.SURDI */
+#define IFX_MSC_ISC_SURDI_OFF (19u)
+
+/** \brief Length for Ifx_MSC_ISR_Bits.DECI */
+#define IFX_MSC_ISR_DECI_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ISR_Bits.DECI */
+#define IFX_MSC_ISR_DECI_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ISR_Bits.DECI */
+#define IFX_MSC_ISR_DECI_OFF (1u)
+
+/** \brief Length for Ifx_MSC_ISR_Bits.DEDI */
+#define IFX_MSC_ISR_DEDI_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ISR_Bits.DEDI */
+#define IFX_MSC_ISR_DEDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ISR_Bits.DEDI */
+#define IFX_MSC_ISR_DEDI_OFF (0u)
+
+/** \brief Length for Ifx_MSC_ISR_Bits.DTFI */
+#define IFX_MSC_ISR_DTFI_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ISR_Bits.DTFI */
+#define IFX_MSC_ISR_DTFI_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ISR_Bits.DTFI */
+#define IFX_MSC_ISR_DTFI_OFF (2u)
+
+/** \brief Length for Ifx_MSC_ISR_Bits.URDI */
+#define IFX_MSC_ISR_URDI_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_ISR_Bits.URDI */
+#define IFX_MSC_ISR_URDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_ISR_Bits.URDI */
+#define IFX_MSC_ISR_URDI_OFF (3u)
+
+/** \brief Length for Ifx_MSC_KRST0_Bits.RST */
+#define IFX_MSC_KRST0_RST_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_KRST0_Bits.RST */
+#define IFX_MSC_KRST0_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_KRST0_Bits.RST */
+#define IFX_MSC_KRST0_RST_OFF (0u)
+
+/** \brief Length for Ifx_MSC_KRST0_Bits.RSTSTAT */
+#define IFX_MSC_KRST0_RSTSTAT_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_KRST0_Bits.RSTSTAT */
+#define IFX_MSC_KRST0_RSTSTAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_KRST0_Bits.RSTSTAT */
+#define IFX_MSC_KRST0_RSTSTAT_OFF (1u)
+
+/** \brief Length for Ifx_MSC_KRST1_Bits.RST */
+#define IFX_MSC_KRST1_RST_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_KRST1_Bits.RST */
+#define IFX_MSC_KRST1_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_KRST1_Bits.RST */
+#define IFX_MSC_KRST1_RST_OFF (0u)
+
+/** \brief Length for Ifx_MSC_KRSTCLR_Bits.CLR */
+#define IFX_MSC_KRSTCLR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_KRSTCLR_Bits.CLR */
+#define IFX_MSC_KRSTCLR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_KRSTCLR_Bits.CLR */
+#define IFX_MSC_KRSTCLR_CLR_OFF (0u)
+
+/** \brief Length for Ifx_MSC_OCR_Bits.CLKCTRL */
+#define IFX_MSC_OCR_CLKCTRL_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_OCR_Bits.CLKCTRL */
+#define IFX_MSC_OCR_CLKCTRL_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_OCR_Bits.CLKCTRL */
+#define IFX_MSC_OCR_CLKCTRL_OFF (8u)
+
+/** \brief Length for Ifx_MSC_OCR_Bits.CLP */
+#define IFX_MSC_OCR_CLP_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_OCR_Bits.CLP */
+#define IFX_MSC_OCR_CLP_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_OCR_Bits.CLP */
+#define IFX_MSC_OCR_CLP_OFF (0u)
+
+/** \brief Length for Ifx_MSC_OCR_Bits.CSC */
+#define IFX_MSC_OCR_CSC_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_OCR_Bits.CSC */
+#define IFX_MSC_OCR_CSC_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_OCR_Bits.CSC */
+#define IFX_MSC_OCR_CSC_OFF (13u)
+
+/** \brief Length for Ifx_MSC_OCR_Bits.CSH */
+#define IFX_MSC_OCR_CSH_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_OCR_Bits.CSH */
+#define IFX_MSC_OCR_CSH_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_OCR_Bits.CSH */
+#define IFX_MSC_OCR_CSH_OFF (11u)
+
+/** \brief Length for Ifx_MSC_OCR_Bits.CSL */
+#define IFX_MSC_OCR_CSL_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_OCR_Bits.CSL */
+#define IFX_MSC_OCR_CSL_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_OCR_Bits.CSL */
+#define IFX_MSC_OCR_CSL_OFF (9u)
+
+/** \brief Length for Ifx_MSC_OCR_Bits.CSLP */
+#define IFX_MSC_OCR_CSLP_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_OCR_Bits.CSLP */
+#define IFX_MSC_OCR_CSLP_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_OCR_Bits.CSLP */
+#define IFX_MSC_OCR_CSLP_OFF (2u)
+
+/** \brief Length for Ifx_MSC_OCR_Bits.ILP */
+#define IFX_MSC_OCR_ILP_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_OCR_Bits.ILP */
+#define IFX_MSC_OCR_ILP_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_OCR_Bits.ILP */
+#define IFX_MSC_OCR_ILP_OFF (3u)
+
+/** \brief Length for Ifx_MSC_OCR_Bits.SDISEL */
+#define IFX_MSC_OCR_SDISEL_LEN (3u)
+
+/** \brief Mask for Ifx_MSC_OCR_Bits.SDISEL */
+#define IFX_MSC_OCR_SDISEL_MSK (0x7u)
+
+/** \brief Offset for Ifx_MSC_OCR_Bits.SDISEL */
+#define IFX_MSC_OCR_SDISEL_OFF (16u)
+
+/** \brief Length for Ifx_MSC_OCR_Bits.SLP */
+#define IFX_MSC_OCR_SLP_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_OCR_Bits.SLP */
+#define IFX_MSC_OCR_SLP_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_OCR_Bits.SLP */
+#define IFX_MSC_OCR_SLP_OFF (1u)
+
+/** \brief Length for Ifx_MSC_OCS_Bits.SUS */
+#define IFX_MSC_OCS_SUS_LEN (4u)
+
+/** \brief Mask for Ifx_MSC_OCS_Bits.SUS */
+#define IFX_MSC_OCS_SUS_MSK (0xfu)
+
+/** \brief Offset for Ifx_MSC_OCS_Bits.SUS */
+#define IFX_MSC_OCS_SUS_OFF (24u)
+
+/** \brief Length for Ifx_MSC_OCS_Bits.SUS_P */
+#define IFX_MSC_OCS_SUS_P_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_OCS_Bits.SUS_P */
+#define IFX_MSC_OCS_SUS_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_OCS_Bits.SUS_P */
+#define IFX_MSC_OCS_SUS_P_OFF (28u)
+
+/** \brief Length for Ifx_MSC_OCS_Bits.SUSSTA */
+#define IFX_MSC_OCS_SUSSTA_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_OCS_Bits.SUSSTA */
+#define IFX_MSC_OCS_SUSSTA_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_OCS_Bits.SUSSTA */
+#define IFX_MSC_OCS_SUSSTA_OFF (29u)
+
+/** \brief Length for Ifx_MSC_UD_Bits.C */
+#define IFX_MSC_UD_C_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_UD_Bits.C */
+#define IFX_MSC_UD_C_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_UD_Bits.C */
+#define IFX_MSC_UD_C_OFF (18u)
+
+/** \brief Length for Ifx_MSC_UD_Bits.DATA */
+#define IFX_MSC_UD_DATA_LEN (8u)
+
+/** \brief Mask for Ifx_MSC_UD_Bits.DATA */
+#define IFX_MSC_UD_DATA_MSK (0xffu)
+
+/** \brief Offset for Ifx_MSC_UD_Bits.DATA */
+#define IFX_MSC_UD_DATA_OFF (0u)
+
+/** \brief Length for Ifx_MSC_UD_Bits.IPF */
+#define IFX_MSC_UD_IPF_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_UD_Bits.IPF */
+#define IFX_MSC_UD_IPF_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_UD_Bits.IPF */
+#define IFX_MSC_UD_IPF_OFF (21u)
+
+/** \brief Length for Ifx_MSC_UD_Bits.LABF */
+#define IFX_MSC_UD_LABF_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_UD_Bits.LABF */
+#define IFX_MSC_UD_LABF_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_UD_Bits.LABF */
+#define IFX_MSC_UD_LABF_OFF (19u)
+
+/** \brief Length for Ifx_MSC_UD_Bits.P */
+#define IFX_MSC_UD_P_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_UD_Bits.P */
+#define IFX_MSC_UD_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_UD_Bits.P */
+#define IFX_MSC_UD_P_OFF (17u)
+
+/** \brief Length for Ifx_MSC_UD_Bits.PERR */
+#define IFX_MSC_UD_PERR_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_UD_Bits.PERR */
+#define IFX_MSC_UD_PERR_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_UD_Bits.PERR */
+#define IFX_MSC_UD_PERR_OFF (22u)
+
+/** \brief Length for Ifx_MSC_UD_Bits.V */
+#define IFX_MSC_UD_V_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_UD_Bits.V */
+#define IFX_MSC_UD_V_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_UD_Bits.V */
+#define IFX_MSC_UD_V_OFF (16u)
+
+/** \brief Length for Ifx_MSC_USCE_Bits.USTC */
+#define IFX_MSC_USCE_USTC_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_USCE_Bits.USTC */
+#define IFX_MSC_USCE_USTC_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_USCE_Bits.USTC */
+#define IFX_MSC_USCE_USTC_OFF (10u)
+
+/** \brief Length for Ifx_MSC_USCE_Bits.USTF */
+#define IFX_MSC_USCE_USTF_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_USCE_Bits.USTF */
+#define IFX_MSC_USCE_USTF_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_USCE_Bits.USTF */
+#define IFX_MSC_USCE_USTF_OFF (9u)
+
+/** \brief Length for Ifx_MSC_USCE_Bits.USTOEN */
+#define IFX_MSC_USCE_USTOEN_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_USCE_Bits.USTOEN */
+#define IFX_MSC_USCE_USTOEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_USCE_Bits.USTOEN */
+#define IFX_MSC_USCE_USTOEN_OFF (8u)
+
+/** \brief Length for Ifx_MSC_USCE_Bits.USTOIP */
+#define IFX_MSC_USCE_USTOIP_LEN (2u)
+
+/** \brief Mask for Ifx_MSC_USCE_Bits.USTOIP */
+#define IFX_MSC_USCE_USTOIP_MSK (0x3u)
+
+/** \brief Offset for Ifx_MSC_USCE_Bits.USTOIP */
+#define IFX_MSC_USCE_USTOIP_OFF (14u)
+
+/** \brief Length for Ifx_MSC_USCE_Bits.USTOPRE */
+#define IFX_MSC_USCE_USTOPRE_LEN (4u)
+
+/** \brief Mask for Ifx_MSC_USCE_Bits.USTOPRE */
+#define IFX_MSC_USCE_USTOPRE_MSK (0xfu)
+
+/** \brief Offset for Ifx_MSC_USCE_Bits.USTOPRE */
+#define IFX_MSC_USCE_USTOPRE_OFF (0u)
+
+/** \brief Length for Ifx_MSC_USCE_Bits.USTOVAL */
+#define IFX_MSC_USCE_USTOVAL_LEN (4u)
+
+/** \brief Mask for Ifx_MSC_USCE_Bits.USTOVAL */
+#define IFX_MSC_USCE_USTOVAL_MSK (0xfu)
+
+/** \brief Offset for Ifx_MSC_USCE_Bits.USTOVAL */
+#define IFX_MSC_USCE_USTOVAL_OFF (4u)
+
+/** \brief Length for Ifx_MSC_USCE_Bits.USTS */
+#define IFX_MSC_USCE_USTS_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_USCE_Bits.USTS */
+#define IFX_MSC_USCE_USTS_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_USCE_Bits.USTS */
+#define IFX_MSC_USCE_USTS_OFF (11u)
+
+/** \brief Length for Ifx_MSC_USCE_Bits.UTASR */
+#define IFX_MSC_USCE_UTASR_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_USCE_Bits.UTASR */
+#define IFX_MSC_USCE_UTASR_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_USCE_Bits.UTASR */
+#define IFX_MSC_USCE_UTASR_OFF (13u)
+
+/** \brief Length for Ifx_MSC_USR_Bits.PCTR */
+#define IFX_MSC_USR_PCTR_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_USR_Bits.PCTR */
+#define IFX_MSC_USR_PCTR_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_USR_Bits.PCTR */
+#define IFX_MSC_USR_PCTR_OFF (4u)
+
+/** \brief Length for Ifx_MSC_USR_Bits.SRDC */
+#define IFX_MSC_USR_SRDC_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_USR_Bits.SRDC */
+#define IFX_MSC_USR_SRDC_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_USR_Bits.SRDC */
+#define IFX_MSC_USR_SRDC_OFF (5u)
+
+/** \brief Length for Ifx_MSC_USR_Bits.UC */
+#define IFX_MSC_USR_UC_LEN (5u)
+
+/** \brief Mask for Ifx_MSC_USR_Bits.UC */
+#define IFX_MSC_USR_UC_MSK (0x1fu)
+
+/** \brief Offset for Ifx_MSC_USR_Bits.UC */
+#define IFX_MSC_USR_UC_OFF (16u)
+
+/** \brief Length for Ifx_MSC_USR_Bits.UFT */
+#define IFX_MSC_USR_UFT_LEN (1u)
+
+/** \brief Mask for Ifx_MSC_USR_Bits.UFT */
+#define IFX_MSC_USR_UFT_MSK (0x1u)
+
+/** \brief Offset for Ifx_MSC_USR_Bits.UFT */
+#define IFX_MSC_USR_UFT_OFF (0u)
+
+/** \brief Length for Ifx_MSC_USR_Bits.URR */
+#define IFX_MSC_USR_URR_LEN (3u)
+
+/** \brief Mask for Ifx_MSC_USR_Bits.URR */
+#define IFX_MSC_USR_URR_MSK (0x7u)
+
+/** \brief Offset for Ifx_MSC_USR_Bits.URR */
+#define IFX_MSC_USR_URR_OFF (1u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXMSC_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxMsc_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxMsc_reg.h
new file mode 100644
index 0000000..e855208
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxMsc_reg.h
@@ -0,0 +1,266 @@
+/**
+ * \file IfxMsc_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Msc_Cfg Msc address
+ * \ingroup IfxLld_Msc
+ *
+ * \defgroup IfxLld_Msc_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Msc_Cfg
+ *
+ * \defgroup IfxLld_Msc_Cfg_Msc0 2-MSC0
+ * \ingroup IfxLld_Msc_Cfg
+ *
+ * \defgroup IfxLld_Msc_Cfg_Msc1 2-MSC1
+ * \ingroup IfxLld_Msc_Cfg
+ *
+ */
+#ifndef IFXMSC_REG_H
+#define IFXMSC_REG_H 1
+/******************************************************************************/
+#include "IfxMsc_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Msc_Cfg_BaseAddress
+ * \{ */
+
+/** \brief MSC object */
+#define MODULE_MSC0 /*lint --e(923)*/ (*(Ifx_MSC*)0xF0002600u)
+
+/** \brief MSC object */
+#define MODULE_MSC1 /*lint --e(923)*/ (*(Ifx_MSC*)0xF0002700u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Msc_Cfg_Msc0
+ * \{ */
+
+/** \brief 80, Asynchronous Block Configuration Register */
+#define MSC0_ABC /*lint --e(923)*/ (*(volatile Ifx_MSC_ABC*)0xF0002680u)
+
+/** \brief FC, Access Enable Register 0 */
+#define MSC0_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_MSC_ACCEN0*)0xF00026FCu)
+
+/** \brief F8, Access Enable Register 1 */
+#define MSC0_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_MSC_ACCEN1*)0xF00026F8u)
+
+/** \brief 0, Clock Control Register */
+#define MSC0_CLC /*lint --e(923)*/ (*(volatile Ifx_MSC_CLC*)0xF0002600u)
+
+/** \brief 20, Downstream Command Register */
+#define MSC0_DC /*lint --e(923)*/ (*(volatile Ifx_MSC_DC*)0xF0002620u)
+
+/** \brief 1C, Downstream Data Register */
+#define MSC0_DD /*lint --e(923)*/ (*(volatile Ifx_MSC_DD*)0xF000261Cu)
+
+/** \brief 6C, Downstream Data Extension Register */
+#define MSC0_DDE /*lint --e(923)*/ (*(volatile Ifx_MSC_DDE*)0xF000266Cu)
+
+/** \brief 70, Downstream Data Mirror Register */
+#define MSC0_DDM /*lint --e(923)*/ (*(volatile Ifx_MSC_DDM*)0xF0002670u)
+
+/** \brief 14, Downstream Control Register */
+#define MSC0_DSC /*lint --e(923)*/ (*(volatile Ifx_MSC_DSC*)0xF0002614u)
+
+/** \brief 58, Downstream Control Enhanced Register 1 */
+#define MSC0_DSCE /*lint --e(923)*/ (*(volatile Ifx_MSC_DSCE*)0xF0002658u)
+
+/** \brief 28, Downstream Select Data Source High Register */
+#define MSC0_DSDSH /*lint --e(923)*/ (*(volatile Ifx_MSC_DSDSH*)0xF0002628u)
+
+/** \brief 64, Downstream Select Data Source High Register */
+#define MSC0_DSDSHE /*lint --e(923)*/ (*(volatile Ifx_MSC_DSDSHE*)0xF0002664u)
+
+/** \brief 24, Downstream Select Data Source Low Register */
+#define MSC0_DSDSL /*lint --e(923)*/ (*(volatile Ifx_MSC_DSDSL*)0xF0002624u)
+
+/** \brief 60, Downstream Select Data Source Low Extension Register */
+#define MSC0_DSDSLE /*lint --e(923)*/ (*(volatile Ifx_MSC_DSDSLE*)0xF0002660u)
+
+/** \brief 18, Downstream Status Register */
+#define MSC0_DSS /*lint --e(923)*/ (*(volatile Ifx_MSC_DSS*)0xF0002618u)
+
+/** \brief 74, Downstream Timing Extension Register */
+#define MSC0_DSTE /*lint --e(923)*/ (*(volatile Ifx_MSC_DSTE*)0xF0002674u)
+
+/** \brief 2C, Emergency Stop Register */
+#define MSC0_ESR /*lint --e(923)*/ (*(volatile Ifx_MSC_ESR*)0xF000262Cu)
+
+/** \brief 68, Emergency Stop Extension Register */
+#define MSC0_ESRE /*lint --e(923)*/ (*(volatile Ifx_MSC_ESRE*)0xF0002668u)
+
+/** \brief C, Fractional Divider Register */
+#define MSC0_FDR /*lint --e(923)*/ (*(volatile Ifx_MSC_FDR*)0xF000260Cu)
+
+/** \brief 40, Interrupt Control Register */
+#define MSC0_ICR /*lint --e(923)*/ (*(volatile Ifx_MSC_ICR*)0xF0002640u)
+
+/** \brief 8, Module Identification Register */
+#define MSC0_ID /*lint --e(923)*/ (*(volatile Ifx_MSC_ID*)0xF0002608u)
+
+/** \brief 48, Interrupt Set Clear Register */
+#define MSC0_ISC /*lint --e(923)*/ (*(volatile Ifx_MSC_ISC*)0xF0002648u)
+
+/** \brief 44, Interrupt Status Register */
+#define MSC0_ISR /*lint --e(923)*/ (*(volatile Ifx_MSC_ISR*)0xF0002644u)
+
+/** \brief F4, Kernel Reset Register 0 */
+#define MSC0_KRST0 /*lint --e(923)*/ (*(volatile Ifx_MSC_KRST0*)0xF00026F4u)
+
+/** \brief F0, Kernel Reset Register 1 */
+#define MSC0_KRST1 /*lint --e(923)*/ (*(volatile Ifx_MSC_KRST1*)0xF00026F0u)
+
+/** \brief EC, Kernel Reset Status Clear Register */
+#define MSC0_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_MSC_KRSTCLR*)0xF00026ECu)
+
+/** \brief 4C, Output Control Register */
+#define MSC0_OCR /*lint --e(923)*/ (*(volatile Ifx_MSC_OCR*)0xF000264Cu)
+
+/** \brief E8, OCDS Control and Status */
+#define MSC0_OCS /*lint --e(923)*/ (*(volatile Ifx_MSC_OCS*)0xF00026E8u)
+
+/** \brief 30, Upstream Data Register */
+#define MSC0_UD0 /*lint --e(923)*/ (*(volatile Ifx_MSC_UD*)0xF0002630u)
+
+/** \brief 34, Upstream Data Register */
+#define MSC0_UD1 /*lint --e(923)*/ (*(volatile Ifx_MSC_UD*)0xF0002634u)
+
+/** \brief 38, Upstream Data Register */
+#define MSC0_UD2 /*lint --e(923)*/ (*(volatile Ifx_MSC_UD*)0xF0002638u)
+
+/** \brief 3C, Upstream Data Register */
+#define MSC0_UD3 /*lint --e(923)*/ (*(volatile Ifx_MSC_UD*)0xF000263Cu)
+
+/** \brief 5C, Upstream Control Enhanced Register 1 */
+#define MSC0_USCE /*lint --e(923)*/ (*(volatile Ifx_MSC_USCE*)0xF000265Cu)
+
+/** \brief 10, Upstream Status Register */
+#define MSC0_USR /*lint --e(923)*/ (*(volatile Ifx_MSC_USR*)0xF0002610u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Msc_Cfg_Msc1
+ * \{ */
+
+/** \brief 80, Asynchronous Block Configuration Register */
+#define MSC1_ABC /*lint --e(923)*/ (*(volatile Ifx_MSC_ABC*)0xF0002780u)
+
+/** \brief FC, Access Enable Register 0 */
+#define MSC1_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_MSC_ACCEN0*)0xF00027FCu)
+
+/** \brief F8, Access Enable Register 1 */
+#define MSC1_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_MSC_ACCEN1*)0xF00027F8u)
+
+/** \brief 0, Clock Control Register */
+#define MSC1_CLC /*lint --e(923)*/ (*(volatile Ifx_MSC_CLC*)0xF0002700u)
+
+/** \brief 20, Downstream Command Register */
+#define MSC1_DC /*lint --e(923)*/ (*(volatile Ifx_MSC_DC*)0xF0002720u)
+
+/** \brief 1C, Downstream Data Register */
+#define MSC1_DD /*lint --e(923)*/ (*(volatile Ifx_MSC_DD*)0xF000271Cu)
+
+/** \brief 6C, Downstream Data Extension Register */
+#define MSC1_DDE /*lint --e(923)*/ (*(volatile Ifx_MSC_DDE*)0xF000276Cu)
+
+/** \brief 70, Downstream Data Mirror Register */
+#define MSC1_DDM /*lint --e(923)*/ (*(volatile Ifx_MSC_DDM*)0xF0002770u)
+
+/** \brief 14, Downstream Control Register */
+#define MSC1_DSC /*lint --e(923)*/ (*(volatile Ifx_MSC_DSC*)0xF0002714u)
+
+/** \brief 58, Downstream Control Enhanced Register 1 */
+#define MSC1_DSCE /*lint --e(923)*/ (*(volatile Ifx_MSC_DSCE*)0xF0002758u)
+
+/** \brief 28, Downstream Select Data Source High Register */
+#define MSC1_DSDSH /*lint --e(923)*/ (*(volatile Ifx_MSC_DSDSH*)0xF0002728u)
+
+/** \brief 64, Downstream Select Data Source High Register */
+#define MSC1_DSDSHE /*lint --e(923)*/ (*(volatile Ifx_MSC_DSDSHE*)0xF0002764u)
+
+/** \brief 24, Downstream Select Data Source Low Register */
+#define MSC1_DSDSL /*lint --e(923)*/ (*(volatile Ifx_MSC_DSDSL*)0xF0002724u)
+
+/** \brief 60, Downstream Select Data Source Low Extension Register */
+#define MSC1_DSDSLE /*lint --e(923)*/ (*(volatile Ifx_MSC_DSDSLE*)0xF0002760u)
+
+/** \brief 18, Downstream Status Register */
+#define MSC1_DSS /*lint --e(923)*/ (*(volatile Ifx_MSC_DSS*)0xF0002718u)
+
+/** \brief 74, Downstream Timing Extension Register */
+#define MSC1_DSTE /*lint --e(923)*/ (*(volatile Ifx_MSC_DSTE*)0xF0002774u)
+
+/** \brief 2C, Emergency Stop Register */
+#define MSC1_ESR /*lint --e(923)*/ (*(volatile Ifx_MSC_ESR*)0xF000272Cu)
+
+/** \brief 68, Emergency Stop Extension Register */
+#define MSC1_ESRE /*lint --e(923)*/ (*(volatile Ifx_MSC_ESRE*)0xF0002768u)
+
+/** \brief C, Fractional Divider Register */
+#define MSC1_FDR /*lint --e(923)*/ (*(volatile Ifx_MSC_FDR*)0xF000270Cu)
+
+/** \brief 40, Interrupt Control Register */
+#define MSC1_ICR /*lint --e(923)*/ (*(volatile Ifx_MSC_ICR*)0xF0002740u)
+
+/** \brief 8, Module Identification Register */
+#define MSC1_ID /*lint --e(923)*/ (*(volatile Ifx_MSC_ID*)0xF0002708u)
+
+/** \brief 48, Interrupt Set Clear Register */
+#define MSC1_ISC /*lint --e(923)*/ (*(volatile Ifx_MSC_ISC*)0xF0002748u)
+
+/** \brief 44, Interrupt Status Register */
+#define MSC1_ISR /*lint --e(923)*/ (*(volatile Ifx_MSC_ISR*)0xF0002744u)
+
+/** \brief F4, Kernel Reset Register 0 */
+#define MSC1_KRST0 /*lint --e(923)*/ (*(volatile Ifx_MSC_KRST0*)0xF00027F4u)
+
+/** \brief F0, Kernel Reset Register 1 */
+#define MSC1_KRST1 /*lint --e(923)*/ (*(volatile Ifx_MSC_KRST1*)0xF00027F0u)
+
+/** \brief EC, Kernel Reset Status Clear Register */
+#define MSC1_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_MSC_KRSTCLR*)0xF00027ECu)
+
+/** \brief 4C, Output Control Register */
+#define MSC1_OCR /*lint --e(923)*/ (*(volatile Ifx_MSC_OCR*)0xF000274Cu)
+
+/** \brief E8, OCDS Control and Status */
+#define MSC1_OCS /*lint --e(923)*/ (*(volatile Ifx_MSC_OCS*)0xF00027E8u)
+
+/** \brief 30, Upstream Data Register */
+#define MSC1_UD0 /*lint --e(923)*/ (*(volatile Ifx_MSC_UD*)0xF0002730u)
+
+/** \brief 34, Upstream Data Register */
+#define MSC1_UD1 /*lint --e(923)*/ (*(volatile Ifx_MSC_UD*)0xF0002734u)
+
+/** \brief 38, Upstream Data Register */
+#define MSC1_UD2 /*lint --e(923)*/ (*(volatile Ifx_MSC_UD*)0xF0002738u)
+
+/** \brief 3C, Upstream Data Register */
+#define MSC1_UD3 /*lint --e(923)*/ (*(volatile Ifx_MSC_UD*)0xF000273Cu)
+
+/** \brief 5C, Upstream Control Enhanced Register 1 */
+#define MSC1_USCE /*lint --e(923)*/ (*(volatile Ifx_MSC_USCE*)0xF000275Cu)
+
+/** \brief 10, Upstream Status Register */
+#define MSC1_USR /*lint --e(923)*/ (*(volatile Ifx_MSC_USR*)0xF0002710u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXMSC_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxMsc_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxMsc_regdef.h
new file mode 100644
index 0000000..1bf6092
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxMsc_regdef.h
@@ -0,0 +1,823 @@
+/**
+ * \file IfxMsc_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Msc Msc
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Msc_Bitfields Bitfields
+ * \ingroup IfxLld_Msc
+ *
+ * \defgroup IfxLld_Msc_union Union
+ * \ingroup IfxLld_Msc
+ *
+ * \defgroup IfxLld_Msc_struct Struct
+ * \ingroup IfxLld_Msc
+ *
+ */
+#ifndef IFXMSC_REGDEF_H
+#define IFXMSC_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Msc_Bitfields
+ * \{ */
+
+/** \brief Asynchronous Block Configuration Register */
+typedef struct _Ifx_MSC_ABC_Bits
+{
+ unsigned int LOW:4; /**< \brief [3:0] Duration of the Low Phase of the Shift Clock (rw) */
+ unsigned int HIGH:4; /**< \brief [7:4] Duration of the High Phase of the Shift Clock (rw) */
+ unsigned int OIP:2; /**< \brief [9:8] Overflow Interrupt Node Pointer (rw) */
+ unsigned int OASR:1; /**< \brief [10:10] Overflow Alternate Service Request (rw) */
+ unsigned int reserved_11:1; /**< \brief \internal Reserved */
+ unsigned int OVF:1; /**< \brief [12:12] Overflow Flag (r) */
+ unsigned int OFM:2; /**< \brief [14:13] Overflow Flag Modify (w) */
+ unsigned int OIE:1; /**< \brief [15:15] Overflow Interrupt Enable (rw) */
+ unsigned int NDA:3; /**< \brief [18:16] N Divider ABRA (rw) */
+ unsigned int UIP:2; /**< \brief [20:19] Underflow Interrupt Node Pointer (rw) */
+ unsigned int UASR:1; /**< \brief [21:21] Underflow Alternate Service Request (rw) */
+ unsigned int reserved_22:1; /**< \brief \internal Reserved */
+ unsigned int UNF:1; /**< \brief [23:23] Underflow Flag (r) */
+ unsigned int UFM:2; /**< \brief [25:24] Underflow Flag Modify (w) */
+ unsigned int UIE:1; /**< \brief [26:26] Underflow Interrupt Enable (rw) */
+ unsigned int CLKSEL:3; /**< \brief [29:27] Clock Select (rw) */
+ unsigned int reserved_30:1; /**< \brief \internal Reserved */
+ unsigned int ABB:1; /**< \brief [31:31] Asynchronous Block Bypass (rw) */
+} Ifx_MSC_ABC_Bits;
+
+/** \brief Access Enable Register 0 */
+typedef struct _Ifx_MSC_ACCEN0_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_MSC_ACCEN0_Bits;
+
+/** \brief Access Enable Register 1 */
+typedef struct _Ifx_MSC_ACCEN1_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_MSC_ACCEN1_Bits;
+
+/** \brief Clock Control Register */
+typedef struct _Ifx_MSC_CLC_Bits
+{
+ unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
+ unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
+ unsigned int reserved_2:1; /**< \brief \internal Reserved */
+ unsigned int EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control (rw) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_MSC_CLC_Bits;
+
+/** \brief Downstream Command Register */
+typedef struct _Ifx_MSC_DC_Bits
+{
+ unsigned int DCL:16; /**< \brief [15:0] Downstream Command for SRL Shift Register (rw) */
+ unsigned int DCH:16; /**< \brief [31:16] Downstream Command for SRH Shift Register (rw) */
+} Ifx_MSC_DC_Bits;
+
+/** \brief Downstream Data Register */
+typedef struct _Ifx_MSC_DD_Bits
+{
+ unsigned int DDL:16; /**< \brief [15:0] Downstream Data for SRL Shift Register (rw) */
+ unsigned int DDH:16; /**< \brief [31:16] Downstream Data for SRH Shift Register (rw) */
+} Ifx_MSC_DD_Bits;
+
+/** \brief Downstream Data Extension Register */
+typedef struct _Ifx_MSC_DDE_Bits
+{
+ unsigned int DDLE:16; /**< \brief [15:0] Downstream Data Extension for SRL Shift Register (rw) */
+ unsigned int DDHE:16; /**< \brief [31:16] Downstream Data Extension for SRH Shift Register (rw) */
+} Ifx_MSC_DDE_Bits;
+
+/** \brief Downstream Data Mirror Register */
+typedef struct _Ifx_MSC_DDM_Bits
+{
+ unsigned int DDLM:16; /**< \brief [15:0] Downstream Data Mirror for SRL Shift Register (w) */
+ unsigned int DDHM:16; /**< \brief [31:16] Downstream Data Mirror for SRH Shift Register (w) */
+} Ifx_MSC_DDM_Bits;
+
+/** \brief Downstream Control Register */
+typedef struct _Ifx_MSC_DSC_Bits
+{
+ unsigned int TM:1; /**< \brief [0:0] Transmission Mode (rw) */
+ unsigned int CP:1; /**< \brief [1:1] Command Pending (rh) */
+ unsigned int DP:1; /**< \brief [2:2] Data Pending (rh) */
+ unsigned int NDBL:5; /**< \brief [7:3] Number of SRL Bits Shifted at Data Frames (rw) */
+ unsigned int NDBH:5; /**< \brief [12:8] Number of SRH Bits Shifted at Data Frames (rw) */
+ unsigned int ENSELL:1; /**< \brief [13:13] Enable SRL Active Phase Selection Bit (rw) */
+ unsigned int ENSELH:1; /**< \brief [14:14] Enable SRH Active Phase Selection Bit (rw) */
+ unsigned int DSDIS:1; /**< \brief [15:15] Downstream Disable (rh) */
+ unsigned int NBC:6; /**< \brief [21:16] Number of Bits Shifted at Command Frames (rw) */
+ unsigned int reserved_22:2; /**< \brief \internal Reserved */
+ unsigned int PPD:5; /**< \brief [28:24] Passive Phase Length at Data Frames (rw) */
+ unsigned int reserved_29:3; /**< \brief \internal Reserved */
+} Ifx_MSC_DSC_Bits;
+
+/** \brief Downstream Control Enhanced Register 1 */
+typedef struct _Ifx_MSC_DSCE_Bits
+{
+ unsigned int NDBHE:1; /**< \brief [0:0] Number of SRH Bits Shifted at Data Frames Extension (rw) */
+ unsigned int NDBLE:1; /**< \brief [1:1] Number of SRH Bits Shifted at Data Frames Extension (rw) */
+ unsigned int reserved_2:12; /**< \brief \internal Reserved */
+ unsigned int EXEN:1; /**< \brief [14:14] Extension Enable (rw) */
+ unsigned int CCF:1; /**< \brief [15:15] Command-Comand Flag (rh) */
+ unsigned int INJENP0:1; /**< \brief [16:16] Injection Enable of the Pin 0 Signal (rw) */
+ unsigned int INJPOSP0:6; /**< \brief [22:17] Injection Position of the Pin 0 Signal (rw) */
+ unsigned int reserved_23:1; /**< \brief \internal Reserved */
+ unsigned int INJENP1:1; /**< \brief [24:24] Injection Enable of the Pin 1 Signal (rw) */
+ unsigned int INJPOSP1:6; /**< \brief [30:25] Injection Position of the Pin 1 Signal (rw) */
+ unsigned int CDCM:1; /**< \brief [31:31] Command-Data-Comand in Data Repetition Mode (rw) */
+} Ifx_MSC_DSCE_Bits;
+
+/** \brief Downstream Select Data Source High Register */
+typedef struct _Ifx_MSC_DSDSH_Bits
+{
+ unsigned int SH0:2; /**< \brief [1:0] Select Source for SRH (rw) */
+ unsigned int SH1:2; /**< \brief [3:2] Select Source for SRH (rw) */
+ unsigned int SH2:2; /**< \brief [5:4] Select Source for SRH (rw) */
+ unsigned int SH3:2; /**< \brief [7:6] Select Source for SRH (rw) */
+ unsigned int SH4:2; /**< \brief [9:8] Select Source for SRH (rw) */
+ unsigned int SH5:2; /**< \brief [11:10] Select Source for SRH (rw) */
+ unsigned int SH6:2; /**< \brief [13:12] Select Source for SRH (rw) */
+ unsigned int SH7:2; /**< \brief [15:14] Select Source for SRH (rw) */
+ unsigned int SH8:2; /**< \brief [17:16] Select Source for SRH (rw) */
+ unsigned int SH9:2; /**< \brief [19:18] Select Source for SRH (rw) */
+ unsigned int SH10:2; /**< \brief [21:20] Select Source for SRH (rw) */
+ unsigned int SH11:2; /**< \brief [23:22] Select Source for SRH (rw) */
+ unsigned int SH12:2; /**< \brief [25:24] Select Source for SRH (rw) */
+ unsigned int SH13:2; /**< \brief [27:26] Select Source for SRH (rw) */
+ unsigned int SH14:2; /**< \brief [29:28] Select Source for SRH (rw) */
+ unsigned int SH15:2; /**< \brief [31:30] Select Source for SRH (rw) */
+} Ifx_MSC_DSDSH_Bits;
+
+/** \brief Downstream Select Data Source High Register */
+typedef struct _Ifx_MSC_DSDSHE_Bits
+{
+ unsigned int SH16:2; /**< \brief [1:0] Select Source for SRH (rw) */
+ unsigned int SH17:2; /**< \brief [3:2] Select Source for SRH (rw) */
+ unsigned int SH18:2; /**< \brief [5:4] Select Source for SRH (rw) */
+ unsigned int SH19:2; /**< \brief [7:6] Select Source for SRH (rw) */
+ unsigned int SH20:2; /**< \brief [9:8] Select Source for SRH (rw) */
+ unsigned int SH21:2; /**< \brief [11:10] Select Source for SRH (rw) */
+ unsigned int SH22:2; /**< \brief [13:12] Select Source for SRH (rw) */
+ unsigned int SH23:2; /**< \brief [15:14] Select Source for SRH (rw) */
+ unsigned int SH24:2; /**< \brief [17:16] Select Source for SRH (rw) */
+ unsigned int SH25:2; /**< \brief [19:18] Select Source for SRH (rw) */
+ unsigned int SH26:2; /**< \brief [21:20] Select Source for SRH (rw) */
+ unsigned int SH27:2; /**< \brief [23:22] Select Source for SRH (rw) */
+ unsigned int SH28:2; /**< \brief [25:24] Select Source for SRH (rw) */
+ unsigned int SH29:2; /**< \brief [27:26] Select Source for SRH (rw) */
+ unsigned int SH30:2; /**< \brief [29:28] Select Source for SRH (rw) */
+ unsigned int SH31:2; /**< \brief [31:30] Select Source for SRH (rw) */
+} Ifx_MSC_DSDSHE_Bits;
+
+/** \brief Downstream Select Data Source Low Register */
+typedef struct _Ifx_MSC_DSDSL_Bits
+{
+ unsigned int SL0:2; /**< \brief [1:0] Select Source for SRL (rw) */
+ unsigned int SL1:2; /**< \brief [3:2] Select Source for SRL (rw) */
+ unsigned int SL2:2; /**< \brief [5:4] Select Source for SRL (rw) */
+ unsigned int SL3:2; /**< \brief [7:6] Select Source for SRL (rw) */
+ unsigned int SL4:2; /**< \brief [9:8] Select Source for SRL (rw) */
+ unsigned int SL5:2; /**< \brief [11:10] Select Source for SRL (rw) */
+ unsigned int SL6:2; /**< \brief [13:12] Select Source for SRL (rw) */
+ unsigned int SL7:2; /**< \brief [15:14] Select Source for SRL (rw) */
+ unsigned int SL8:2; /**< \brief [17:16] Select Source for SRL (rw) */
+ unsigned int SL9:2; /**< \brief [19:18] Select Source for SRL (rw) */
+ unsigned int SL10:2; /**< \brief [21:20] Select Source for SRL (rw) */
+ unsigned int SL11:2; /**< \brief [23:22] Select Source for SRL (rw) */
+ unsigned int SL12:2; /**< \brief [25:24] Select Source for SRL (rw) */
+ unsigned int SL13:2; /**< \brief [27:26] Select Source for SRL (rw) */
+ unsigned int SL14:2; /**< \brief [29:28] Select Source for SRL (rw) */
+ unsigned int SL15:2; /**< \brief [31:30] Select Source for SRL (rw) */
+} Ifx_MSC_DSDSL_Bits;
+
+/** \brief Downstream Select Data Source Low Extension Register */
+typedef struct _Ifx_MSC_DSDSLE_Bits
+{
+ unsigned int SL16:2; /**< \brief [1:0] Select Source for SRL (rw) */
+ unsigned int SL17:2; /**< \brief [3:2] Select Source for SRL (rw) */
+ unsigned int SL18:2; /**< \brief [5:4] Select Source for SRL (rw) */
+ unsigned int SL19:2; /**< \brief [7:6] Select Source for SRL (rw) */
+ unsigned int SL20:2; /**< \brief [9:8] Select Source for SRL (rw) */
+ unsigned int SL21:2; /**< \brief [11:10] Select Source for SRL (rw) */
+ unsigned int SL22:2; /**< \brief [13:12] Select Source for SRL (rw) */
+ unsigned int SL23:2; /**< \brief [15:14] Select Source for SRL (rw) */
+ unsigned int SL24:2; /**< \brief [17:16] Select Source for SRL (rw) */
+ unsigned int SL25:2; /**< \brief [19:18] Select Source for SRL (rw) */
+ unsigned int SL26:2; /**< \brief [21:20] Select Source for SRL (rw) */
+ unsigned int SL27:2; /**< \brief [23:22] Select Source for SRL (rw) */
+ unsigned int SL28:2; /**< \brief [25:24] Select Source for SRL (rw) */
+ unsigned int SL29:2; /**< \brief [27:26] Select Source for SRL (rw) */
+ unsigned int SL30:2; /**< \brief [29:28] Select Source for SRL (rw) */
+ unsigned int SL31:2; /**< \brief [31:30] Select Source for SRL (rw) */
+} Ifx_MSC_DSDSLE_Bits;
+
+/** \brief Downstream Status Register */
+typedef struct _Ifx_MSC_DSS_Bits
+{
+ unsigned int PFC:4; /**< \brief [3:0] Passive Time Frame Counter (rh) */
+ unsigned int reserved_4:4; /**< \brief \internal Reserved */
+ unsigned int NPTF:4; /**< \brief [11:8] Number Of Passive Time Frames (rw) */
+ unsigned int reserved_12:4; /**< \brief \internal Reserved */
+ unsigned int DC:8; /**< \brief [23:16] Downstream Counter (rh) */
+ unsigned int DFA:1; /**< \brief [24:24] Data Frame Active (rh) */
+ unsigned int CFA:1; /**< \brief [25:25] Command Frame Active (rh) */
+ unsigned int reserved_26:6; /**< \brief \internal Reserved */
+} Ifx_MSC_DSS_Bits;
+
+/** \brief Downstream Timing Extension Register */
+typedef struct _Ifx_MSC_DSTE_Bits
+{
+ unsigned int PPDE:2; /**< \brief [1:0] Passive Phase Length at Data Frames Extension (rw) */
+ unsigned int PPCE:6; /**< \brief [7:2] Passive Phase Length at Control Frames Extension (rw) */
+ unsigned int NDD:4; /**< \brief [11:8] N Divider Downstream (rw) */
+ unsigned int reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_MSC_DSTE_Bits;
+
+/** \brief Emergency Stop Register */
+typedef struct _Ifx_MSC_ESR_Bits
+{
+ unsigned int ENL0:1; /**< \brief [0:0] Emergency Stop Enable for Bit 0 in SRL (rw) */
+ unsigned int ENL1:1; /**< \brief [1:1] Emergency Stop Enable for Bit 1 in SRL (rw) */
+ unsigned int ENL2:1; /**< \brief [2:2] Emergency Stop Enable for Bit 2 in SRL (rw) */
+ unsigned int ENL3:1; /**< \brief [3:3] Emergency Stop Enable for Bit 3 in SRL (rw) */
+ unsigned int ENL4:1; /**< \brief [4:4] Emergency Stop Enable for Bit 4 in SRL (rw) */
+ unsigned int ENL5:1; /**< \brief [5:5] Emergency Stop Enable for Bit 5 in SRL (rw) */
+ unsigned int ENL6:1; /**< \brief [6:6] Emergency Stop Enable for Bit 6 in SRL (rw) */
+ unsigned int ENL7:1; /**< \brief [7:7] Emergency Stop Enable for Bit 7 in SRL (rw) */
+ unsigned int ENL8:1; /**< \brief [8:8] Emergency Stop Enable for Bit 8 in SRL (rw) */
+ unsigned int ENL9:1; /**< \brief [9:9] Emergency Stop Enable for Bit 9 in SRL (rw) */
+ unsigned int ENL10:1; /**< \brief [10:10] Emergency Stop Enable for Bit 10 in SRL (rw) */
+ unsigned int ENL11:1; /**< \brief [11:11] Emergency Stop Enable for Bit 11 in SRL (rw) */
+ unsigned int ENL12:1; /**< \brief [12:12] Emergency Stop Enable for Bit 12 in SRL (rw) */
+ unsigned int ENL13:1; /**< \brief [13:13] Emergency Stop Enable for Bit 13 in SRL (rw) */
+ unsigned int ENL14:1; /**< \brief [14:14] Emergency Stop Enable for Bit 14 in SRL (rw) */
+ unsigned int ENL15:1; /**< \brief [15:15] Emergency Stop Enable for Bit 15 in SRL (rw) */
+ unsigned int ENH0:1; /**< \brief [16:16] Emergency Stop Enable for Bit 0 in SRH (rw) */
+ unsigned int ENH1:1; /**< \brief [17:17] Emergency Stop Enable for Bit 1 in SRH (rw) */
+ unsigned int ENH2:1; /**< \brief [18:18] Emergency Stop Enable for Bit 2 in SRH (rw) */
+ unsigned int ENH3:1; /**< \brief [19:19] Emergency Stop Enable for Bit 3 in SRH (rw) */
+ unsigned int ENH4:1; /**< \brief [20:20] Emergency Stop Enable for Bit 4 in SRH (rw) */
+ unsigned int ENH5:1; /**< \brief [21:21] Emergency Stop Enable for Bit 5 in SRH (rw) */
+ unsigned int ENH6:1; /**< \brief [22:22] Emergency Stop Enable for Bit 6 in SRH (rw) */
+ unsigned int ENH7:1; /**< \brief [23:23] Emergency Stop Enable for Bit 7 in SRH (rw) */
+ unsigned int ENH8:1; /**< \brief [24:24] Emergency Stop Enable for Bit 8 in SRH (rw) */
+ unsigned int ENH9:1; /**< \brief [25:25] Emergency Stop Enable for Bit 9 in SRH (rw) */
+ unsigned int ENH10:1; /**< \brief [26:26] Emergency Stop Enable for Bit 10 in SRH (rw) */
+ unsigned int ENH11:1; /**< \brief [27:27] Emergency Stop Enable for Bit 11 in SRH (rw) */
+ unsigned int ENH12:1; /**< \brief [28:28] Emergency Stop Enable for Bit 12 in SRH (rw) */
+ unsigned int ENH13:1; /**< \brief [29:29] Emergency Stop Enable for Bit 13 in SRH (rw) */
+ unsigned int ENH14:1; /**< \brief [30:30] Emergency Stop Enable for Bit 14 in SRH (rw) */
+ unsigned int ENH15:1; /**< \brief [31:31] Emergency Stop Enable for Bit 15 in SRH (rw) */
+} Ifx_MSC_ESR_Bits;
+
+/** \brief Emergency Stop Extension Register */
+typedef struct _Ifx_MSC_ESRE_Bits
+{
+ unsigned int ENL16:1; /**< \brief [0:0] Emergency Stop Enable for Bit 16 in SRL (rw) */
+ unsigned int ENL17:1; /**< \brief [1:1] Emergency Stop Enable for Bit 17 in SRL (rw) */
+ unsigned int ENL18:1; /**< \brief [2:2] Emergency Stop Enable for Bit 18 in SRL (rw) */
+ unsigned int ENL19:1; /**< \brief [3:3] Emergency Stop Enable for Bit 19 in SRL (rw) */
+ unsigned int ENL20:1; /**< \brief [4:4] Emergency Stop Enable for Bit 20 in SRL (rw) */
+ unsigned int ENL21:1; /**< \brief [5:5] Emergency Stop Enable for Bit 21 in SRL (rw) */
+ unsigned int ENL22:1; /**< \brief [6:6] Emergency Stop Enable for Bit 22 in SRL (rw) */
+ unsigned int ENL23:1; /**< \brief [7:7] Emergency Stop Enable for Bit 23 in SRL (rw) */
+ unsigned int ENL24:1; /**< \brief [8:8] Emergency Stop Enable for Bit 24 in SRL (rw) */
+ unsigned int ENL25:1; /**< \brief [9:9] Emergency Stop Enable for Bit 25 in SRL (rw) */
+ unsigned int ENL26:1; /**< \brief [10:10] Emergency Stop Enable for Bit 26 in SRL (rw) */
+ unsigned int ENL27:1; /**< \brief [11:11] Emergency Stop Enable for Bit 27 in SRL (rw) */
+ unsigned int ENL28:1; /**< \brief [12:12] Emergency Stop Enable for Bit 28 in SRL (rw) */
+ unsigned int ENL29:1; /**< \brief [13:13] Emergency Stop Enable for Bit 29 in SRL (rw) */
+ unsigned int ENL30:1; /**< \brief [14:14] Emergency Stop Enable for Bit 30 in SRL (rw) */
+ unsigned int ENL31:1; /**< \brief [15:15] Emergency Stop Enable for Bit 31 in SRL (rw) */
+ unsigned int ENH16:1; /**< \brief [16:16] Emergency Stop Enable for Bit 16 in SRH (rw) */
+ unsigned int ENH17:1; /**< \brief [17:17] Emergency Stop Enable for Bit 17 in SRH (rw) */
+ unsigned int ENH18:1; /**< \brief [18:18] Emergency Stop Enable for Bit 18 in SRH (rw) */
+ unsigned int ENH19:1; /**< \brief [19:19] Emergency Stop Enable for Bit 19 in SRH (rw) */
+ unsigned int ENH20:1; /**< \brief [20:20] Emergency Stop Enable for Bit 20 in SRH (rw) */
+ unsigned int ENH21:1; /**< \brief [21:21] Emergency Stop Enable for Bit 21 in SRH (rw) */
+ unsigned int ENH22:1; /**< \brief [22:22] Emergency Stop Enable for Bit 22 in SRH (rw) */
+ unsigned int ENH23:1; /**< \brief [23:23] Emergency Stop Enable for Bit 23 in SRH (rw) */
+ unsigned int ENH24:1; /**< \brief [24:24] Emergency Stop Enable for Bit 24 in SRH (rw) */
+ unsigned int ENH25:1; /**< \brief [25:25] Emergency Stop Enable for Bit 25 in SRH (rw) */
+ unsigned int ENH26:1; /**< \brief [26:26] Emergency Stop Enable for Bit 26 in SRH (rw) */
+ unsigned int ENH27:1; /**< \brief [27:27] Emergency Stop Enable for Bit 27 in SRH (rw) */
+ unsigned int ENH28:1; /**< \brief [28:28] Emergency Stop Enable for Bit 28 in SRH (rw) */
+ unsigned int ENH29:1; /**< \brief [29:29] Emergency Stop Enable for Bit 29 in SRH (rw) */
+ unsigned int ENH30:1; /**< \brief [30:30] Emergency Stop Enable for Bit 30 in SRH (rw) */
+ unsigned int ENH31:1; /**< \brief [31:31] Emergency Stop Enable for Bit 31 in SRH (rw) */
+} Ifx_MSC_ESRE_Bits;
+
+/** \brief Fractional Divider Register */
+typedef struct _Ifx_MSC_FDR_Bits
+{
+ unsigned int STEP:10; /**< \brief [9:0] Step Value (rw) */
+ unsigned int reserved_10:4; /**< \brief \internal Reserved */
+ unsigned int DM:2; /**< \brief [15:14] Divider Mode (rw) */
+ unsigned int RESULT:10; /**< \brief [25:16] Result Value (rh) */
+ unsigned int reserved_26:4; /**< \brief \internal Reserved */
+ unsigned int ENHW:1; /**< \brief [30:30] Enable Hardware Clock Control (rw) */
+ unsigned int DISCLK:1; /**< \brief [31:31] Disable Clock (rwh) */
+} Ifx_MSC_FDR_Bits;
+
+/** \brief Interrupt Control Register */
+typedef struct _Ifx_MSC_ICR_Bits
+{
+ unsigned int EDIP:2; /**< \brief [1:0] Data Frame Interrupt Node Pointer (rw) */
+ unsigned int EDIE:2; /**< \brief [3:2] Data Frame Interrupt Enable (rw) */
+ unsigned int ECIP:2; /**< \brief [5:4] Command Frame Interrupt Node Pointer (rw) */
+ unsigned int reserved_6:1; /**< \brief \internal Reserved */
+ unsigned int ECIE:1; /**< \brief [7:7] Command Frame Interrupt Enable (rw) */
+ unsigned int TFIP:2; /**< \brief [9:8] Time Frame Interrupt Pointer (rw) */
+ unsigned int reserved_10:1; /**< \brief \internal Reserved */
+ unsigned int TFIE:1; /**< \brief [11:11] Time Frame Interrupt Enable (rw) */
+ unsigned int RDIP:2; /**< \brief [13:12] Receive Data Interrupt Pointer (rw) */
+ unsigned int RDIE:2; /**< \brief [15:14] Receive Data Interrupt Enable (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_MSC_ICR_Bits;
+
+/** \brief Module Identification Register */
+typedef struct _Ifx_MSC_ID_Bits
+{
+ unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
+ unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_MSC_ID_Bits;
+
+/** \brief Interrupt Set Clear Register */
+typedef struct _Ifx_MSC_ISC_Bits
+{
+ unsigned int CDEDI:1; /**< \brief [0:0] Clear DEDI Flag (w) */
+ unsigned int CDECI:1; /**< \brief [1:1] Clear DECI Flag (w) */
+ unsigned int CDTFI:1; /**< \brief [2:2] Clear DTFI Flag (w) */
+ unsigned int CURDI:1; /**< \brief [3:3] Clear URDI Flag (w) */
+ unsigned int CDP:1; /**< \brief [4:4] Clear DP Flag (w) */
+ unsigned int CCP:1; /**< \brief [5:5] Clear CP Flag (w) */
+ unsigned int CDDIS:1; /**< \brief [6:6] Clear DSDIS Flag (w) */
+ unsigned int reserved_7:9; /**< \brief \internal Reserved */
+ unsigned int SDEDI:1; /**< \brief [16:16] Set DEDI Flag (w) */
+ unsigned int SDECI:1; /**< \brief [17:17] Set DECI Flag (w) */
+ unsigned int SDTFI:1; /**< \brief [18:18] Set DTFI Flag (w) */
+ unsigned int SURDI:1; /**< \brief [19:19] Set URDI Flag (w) */
+ unsigned int SDP:1; /**< \brief [20:20] Set DP Bit (w) */
+ unsigned int SCP:1; /**< \brief [21:21] Set CP Flag (w) */
+ unsigned int SDDIS:1; /**< \brief [22:22] Set DSDIS Flag (w) */
+ unsigned int reserved_23:9; /**< \brief \internal Reserved */
+} Ifx_MSC_ISC_Bits;
+
+/** \brief Interrupt Status Register */
+typedef struct _Ifx_MSC_ISR_Bits
+{
+ unsigned int DEDI:1; /**< \brief [0:0] Data Frame Interrupt Flag (rh) */
+ unsigned int DECI:1; /**< \brief [1:1] Command Frame Interrupt Flag (rh) */
+ unsigned int DTFI:1; /**< \brief [2:2] Time Frame Interrupt Flag (rh) */
+ unsigned int URDI:1; /**< \brief [3:3] Receive Data Interrupt Flag (rh) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_MSC_ISR_Bits;
+
+/** \brief Kernel Reset Register 0 */
+typedef struct _Ifx_MSC_KRST0_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rh) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_MSC_KRST0_Bits;
+
+/** \brief Kernel Reset Register 1 */
+typedef struct _Ifx_MSC_KRST1_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_MSC_KRST1_Bits;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef struct _Ifx_MSC_KRSTCLR_Bits
+{
+ unsigned int CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_MSC_KRSTCLR_Bits;
+
+/** \brief Output Control Register */
+typedef struct _Ifx_MSC_OCR_Bits
+{
+ unsigned int CLP:1; /**< \brief [0:0] FCLP Line Polarity (rw) */
+ unsigned int SLP:1; /**< \brief [1:1] SOP Line Polarity (rw) */
+ unsigned int CSLP:1; /**< \brief [2:2] Chip Selection Lines Polarity (rw) */
+ unsigned int ILP:1; /**< \brief [3:3] SDI Line Polarity (rw) */
+ unsigned int reserved_4:4; /**< \brief \internal Reserved */
+ unsigned int CLKCTRL:1; /**< \brief [8:8] Clock Control (rw) */
+ unsigned int CSL:2; /**< \brief [10:9] Chip Enable Selection for ENL (rw) */
+ unsigned int CSH:2; /**< \brief [12:11] Chip Enable Selection for ENH (rw) */
+ unsigned int CSC:2; /**< \brief [14:13] Chip Enable Selection for ENC (rw) */
+ unsigned int reserved_15:1; /**< \brief \internal Reserved */
+ unsigned int SDISEL:3; /**< \brief [18:16] Serial Data Input Selection (rw) */
+ unsigned int reserved_19:13; /**< \brief \internal Reserved */
+} Ifx_MSC_OCR_Bits;
+
+/** \brief OCDS Control and Status */
+typedef struct _Ifx_MSC_OCS_Bits
+{
+ unsigned int reserved_0:24; /**< \brief \internal Reserved */
+ unsigned int SUS:4; /**< \brief [27:24] OCDS Suspend Control (rw) */
+ unsigned int SUS_P:1; /**< \brief [28:28] SUS Write Protection (w) */
+ unsigned int SUSSTA:1; /**< \brief [29:29] Suspend State (rh) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_MSC_OCS_Bits;
+
+/** \brief Upstream Data Register */
+typedef struct _Ifx_MSC_UD_Bits
+{
+ unsigned int DATA:8; /**< \brief [7:0] Received Data (rh) */
+ unsigned int reserved_8:8; /**< \brief \internal Reserved */
+ unsigned int V:1; /**< \brief [16:16] Valid Bit (rh) */
+ unsigned int P:1; /**< \brief [17:17] Parity Bit (rh) */
+ unsigned int C:1; /**< \brief [18:18] Clear Bit (w) */
+ unsigned int LABF:2; /**< \brief [20:19] Lower Address Bit Field (rh) */
+ unsigned int IPF:1; /**< \brief [21:21] Internal Parity Flag (rh) */
+ unsigned int PERR:1; /**< \brief [22:22] Parity Error (rh) */
+ unsigned int reserved_23:9; /**< \brief \internal Reserved */
+} Ifx_MSC_UD_Bits;
+
+/** \brief Upstream Control Enhanced Register 1 */
+typedef struct _Ifx_MSC_USCE_Bits
+{
+ unsigned int USTOPRE:4; /**< \brief [3:0] Upstream Timeout Prescaler (rw) */
+ unsigned int USTOVAL:4; /**< \brief [7:4] Upstream Timeout Value (rw) */
+ unsigned int USTOEN:1; /**< \brief [8:8] Upstream Timeout Interrupt Enable (rw) */
+ unsigned int USTF:1; /**< \brief [9:9] Upstream Timeout Flag (rh) */
+ unsigned int USTC:1; /**< \brief [10:10] Upstream Timout Clear (w) */
+ unsigned int USTS:1; /**< \brief [11:11] Upstream Timout Set (w) */
+ unsigned int reserved_12:1; /**< \brief \internal Reserved */
+ unsigned int UTASR:1; /**< \brief [13:13] Upstream Timout Alternate Service Request (rw) */
+ unsigned int USTOIP:2; /**< \brief [15:14] Upstream Timout Interrupt Node Pointer (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_MSC_USCE_Bits;
+
+/** \brief Upstream Status Register */
+typedef struct _Ifx_MSC_USR_Bits
+{
+ unsigned int UFT:1; /**< \brief [0:0] Upstream Channel Frame Type (rw) */
+ unsigned int URR:3; /**< \brief [3:1] Upstream Channel Receiving Rate (rw) */
+ unsigned int PCTR:1; /**< \brief [4:4] Parity Control (rw) */
+ unsigned int SRDC:1; /**< \brief [5:5] Service Request Delay Control (rw) */
+ unsigned int reserved_6:10; /**< \brief \internal Reserved */
+ unsigned int UC:5; /**< \brief [20:16] Upstream Counter (rh) */
+ unsigned int reserved_21:11; /**< \brief \internal Reserved */
+} Ifx_MSC_USR_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Msc_union
+ * \{ */
+
+/** \brief Asynchronous Block Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_ABC_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_ABC;
+
+/** \brief Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_ACCEN0_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_ACCEN0;
+
+/** \brief Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_ACCEN1_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_ACCEN1;
+
+/** \brief Clock Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_CLC_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_CLC;
+
+/** \brief Downstream Command Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_DC_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_DC;
+
+/** \brief Downstream Data Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_DD_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_DD;
+
+/** \brief Downstream Data Extension Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_DDE_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_DDE;
+
+/** \brief Downstream Data Mirror Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_DDM_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_DDM;
+
+/** \brief Downstream Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_DSC_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_DSC;
+
+/** \brief Downstream Control Enhanced Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_DSCE_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_DSCE;
+
+/** \brief Downstream Select Data Source High Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_DSDSH_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_DSDSH;
+
+/** \brief Downstream Select Data Source High Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_DSDSHE_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_DSDSHE;
+
+/** \brief Downstream Select Data Source Low Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_DSDSL_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_DSDSL;
+
+/** \brief Downstream Select Data Source Low Extension Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_DSDSLE_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_DSDSLE;
+
+/** \brief Downstream Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_DSS_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_DSS;
+
+/** \brief Downstream Timing Extension Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_DSTE_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_DSTE;
+
+/** \brief Emergency Stop Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_ESR_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_ESR;
+
+/** \brief Emergency Stop Extension Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_ESRE_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_ESRE;
+
+/** \brief Fractional Divider Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_FDR_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_FDR;
+
+/** \brief Interrupt Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_ICR_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_ICR;
+
+/** \brief Module Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_ID;
+
+/** \brief Interrupt Set Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_ISC_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_ISC;
+
+/** \brief Interrupt Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_ISR_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_ISR;
+
+/** \brief Kernel Reset Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_KRST0_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_KRST0;
+
+/** \brief Kernel Reset Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_KRST1_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_KRST1;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_KRSTCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_KRSTCLR;
+
+/** \brief Output Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_OCR_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_OCR;
+
+/** \brief OCDS Control and Status */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_OCS_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_OCS;
+
+/** \brief Upstream Data Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_UD_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_UD;
+
+/** \brief Upstream Control Enhanced Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_USCE_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_USCE;
+
+/** \brief Upstream Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MSC_USR_Bits B; /**< \brief Bitfield access */
+} Ifx_MSC_USR;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Msc_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief MSC object */
+typedef volatile struct _Ifx_MSC
+{
+ Ifx_MSC_CLC CLC; /**< \brief 0, Clock Control Register */
+ unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
+ Ifx_MSC_ID ID; /**< \brief 8, Module Identification Register */
+ Ifx_MSC_FDR FDR; /**< \brief C, Fractional Divider Register */
+ Ifx_MSC_USR USR; /**< \brief 10, Upstream Status Register */
+ Ifx_MSC_DSC DSC; /**< \brief 14, Downstream Control Register */
+ Ifx_MSC_DSS DSS; /**< \brief 18, Downstream Status Register */
+ Ifx_MSC_DD DD; /**< \brief 1C, Downstream Data Register */
+ Ifx_MSC_DC DC; /**< \brief 20, Downstream Command Register */
+ Ifx_MSC_DSDSL DSDSL; /**< \brief 24, Downstream Select Data Source Low Register */
+ Ifx_MSC_DSDSH DSDSH; /**< \brief 28, Downstream Select Data Source High Register */
+ Ifx_MSC_ESR ESR; /**< \brief 2C, Emergency Stop Register */
+ Ifx_MSC_UD UD[4]; /**< \brief 30, Upstream Data Register */
+ Ifx_MSC_ICR ICR; /**< \brief 40, Interrupt Control Register */
+ Ifx_MSC_ISR ISR; /**< \brief 44, Interrupt Status Register */
+ Ifx_MSC_ISC ISC; /**< \brief 48, Interrupt Set Clear Register */
+ Ifx_MSC_OCR OCR; /**< \brief 4C, Output Control Register */
+ unsigned char reserved_50[8]; /**< \brief 50, \internal Reserved */
+ Ifx_MSC_DSCE DSCE; /**< \brief 58, Downstream Control Enhanced Register 1 */
+ Ifx_MSC_USCE USCE; /**< \brief 5C, Upstream Control Enhanced Register 1 */
+ Ifx_MSC_DSDSLE DSDSLE; /**< \brief 60, Downstream Select Data Source Low Extension Register */
+ Ifx_MSC_DSDSHE DSDSHE; /**< \brief 64, Downstream Select Data Source High Register */
+ Ifx_MSC_ESRE ESRE; /**< \brief 68, Emergency Stop Extension Register */
+ Ifx_MSC_DDE DDE; /**< \brief 6C, Downstream Data Extension Register */
+ Ifx_MSC_DDM DDM; /**< \brief 70, Downstream Data Mirror Register */
+ Ifx_MSC_DSTE DSTE; /**< \brief 74, Downstream Timing Extension Register */
+ unsigned char reserved_78[8]; /**< \brief 78, \internal Reserved */
+ Ifx_MSC_ABC ABC; /**< \brief 80, Asynchronous Block Configuration Register */
+ unsigned char reserved_84[100]; /**< \brief 84, \internal Reserved */
+ Ifx_MSC_OCS OCS; /**< \brief E8, OCDS Control and Status */
+ Ifx_MSC_KRSTCLR KRSTCLR; /**< \brief EC, Kernel Reset Status Clear Register */
+ Ifx_MSC_KRST1 KRST1; /**< \brief F0, Kernel Reset Register 1 */
+ Ifx_MSC_KRST0 KRST0; /**< \brief F4, Kernel Reset Register 0 */
+ Ifx_MSC_ACCEN1 ACCEN1; /**< \brief F8, Access Enable Register 1 */
+ Ifx_MSC_ACCEN0 ACCEN0; /**< \brief FC, Access Enable Register 0 */
+} Ifx_MSC;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXMSC_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxMtu_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxMtu_bf.h
new file mode 100644
index 0000000..2274bfe
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxMtu_bf.h
@@ -0,0 +1,1107 @@
+/**
+ * \file IfxMtu_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Mtu_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Mtu
+ *
+ */
+#ifndef IFXMTU_BF_H
+#define IFXMTU_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mtu_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN0 */
+#define IFX_MTU_ACCEN0_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN0 */
+#define IFX_MTU_ACCEN0_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN0 */
+#define IFX_MTU_ACCEN0_EN0_OFF (0u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN10 */
+#define IFX_MTU_ACCEN0_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN10 */
+#define IFX_MTU_ACCEN0_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN10 */
+#define IFX_MTU_ACCEN0_EN10_OFF (10u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN11 */
+#define IFX_MTU_ACCEN0_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN11 */
+#define IFX_MTU_ACCEN0_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN11 */
+#define IFX_MTU_ACCEN0_EN11_OFF (11u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN12 */
+#define IFX_MTU_ACCEN0_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN12 */
+#define IFX_MTU_ACCEN0_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN12 */
+#define IFX_MTU_ACCEN0_EN12_OFF (12u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN13 */
+#define IFX_MTU_ACCEN0_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN13 */
+#define IFX_MTU_ACCEN0_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN13 */
+#define IFX_MTU_ACCEN0_EN13_OFF (13u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN14 */
+#define IFX_MTU_ACCEN0_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN14 */
+#define IFX_MTU_ACCEN0_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN14 */
+#define IFX_MTU_ACCEN0_EN14_OFF (14u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN15 */
+#define IFX_MTU_ACCEN0_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN15 */
+#define IFX_MTU_ACCEN0_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN15 */
+#define IFX_MTU_ACCEN0_EN15_OFF (15u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN16 */
+#define IFX_MTU_ACCEN0_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN16 */
+#define IFX_MTU_ACCEN0_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN16 */
+#define IFX_MTU_ACCEN0_EN16_OFF (16u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN17 */
+#define IFX_MTU_ACCEN0_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN17 */
+#define IFX_MTU_ACCEN0_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN17 */
+#define IFX_MTU_ACCEN0_EN17_OFF (17u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN18 */
+#define IFX_MTU_ACCEN0_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN18 */
+#define IFX_MTU_ACCEN0_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN18 */
+#define IFX_MTU_ACCEN0_EN18_OFF (18u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN19 */
+#define IFX_MTU_ACCEN0_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN19 */
+#define IFX_MTU_ACCEN0_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN19 */
+#define IFX_MTU_ACCEN0_EN19_OFF (19u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN1 */
+#define IFX_MTU_ACCEN0_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN1 */
+#define IFX_MTU_ACCEN0_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN1 */
+#define IFX_MTU_ACCEN0_EN1_OFF (1u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN20 */
+#define IFX_MTU_ACCEN0_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN20 */
+#define IFX_MTU_ACCEN0_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN20 */
+#define IFX_MTU_ACCEN0_EN20_OFF (20u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN21 */
+#define IFX_MTU_ACCEN0_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN21 */
+#define IFX_MTU_ACCEN0_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN21 */
+#define IFX_MTU_ACCEN0_EN21_OFF (21u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN22 */
+#define IFX_MTU_ACCEN0_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN22 */
+#define IFX_MTU_ACCEN0_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN22 */
+#define IFX_MTU_ACCEN0_EN22_OFF (22u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN23 */
+#define IFX_MTU_ACCEN0_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN23 */
+#define IFX_MTU_ACCEN0_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN23 */
+#define IFX_MTU_ACCEN0_EN23_OFF (23u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN24 */
+#define IFX_MTU_ACCEN0_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN24 */
+#define IFX_MTU_ACCEN0_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN24 */
+#define IFX_MTU_ACCEN0_EN24_OFF (24u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN25 */
+#define IFX_MTU_ACCEN0_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN25 */
+#define IFX_MTU_ACCEN0_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN25 */
+#define IFX_MTU_ACCEN0_EN25_OFF (25u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN26 */
+#define IFX_MTU_ACCEN0_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN26 */
+#define IFX_MTU_ACCEN0_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN26 */
+#define IFX_MTU_ACCEN0_EN26_OFF (26u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN27 */
+#define IFX_MTU_ACCEN0_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN27 */
+#define IFX_MTU_ACCEN0_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN27 */
+#define IFX_MTU_ACCEN0_EN27_OFF (27u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN28 */
+#define IFX_MTU_ACCEN0_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN28 */
+#define IFX_MTU_ACCEN0_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN28 */
+#define IFX_MTU_ACCEN0_EN28_OFF (28u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN29 */
+#define IFX_MTU_ACCEN0_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN29 */
+#define IFX_MTU_ACCEN0_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN29 */
+#define IFX_MTU_ACCEN0_EN29_OFF (29u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN2 */
+#define IFX_MTU_ACCEN0_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN2 */
+#define IFX_MTU_ACCEN0_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN2 */
+#define IFX_MTU_ACCEN0_EN2_OFF (2u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN30 */
+#define IFX_MTU_ACCEN0_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN30 */
+#define IFX_MTU_ACCEN0_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN30 */
+#define IFX_MTU_ACCEN0_EN30_OFF (30u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN31 */
+#define IFX_MTU_ACCEN0_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN31 */
+#define IFX_MTU_ACCEN0_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN31 */
+#define IFX_MTU_ACCEN0_EN31_OFF (31u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN3 */
+#define IFX_MTU_ACCEN0_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN3 */
+#define IFX_MTU_ACCEN0_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN3 */
+#define IFX_MTU_ACCEN0_EN3_OFF (3u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN4 */
+#define IFX_MTU_ACCEN0_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN4 */
+#define IFX_MTU_ACCEN0_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN4 */
+#define IFX_MTU_ACCEN0_EN4_OFF (4u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN5 */
+#define IFX_MTU_ACCEN0_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN5 */
+#define IFX_MTU_ACCEN0_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN5 */
+#define IFX_MTU_ACCEN0_EN5_OFF (5u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN6 */
+#define IFX_MTU_ACCEN0_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN6 */
+#define IFX_MTU_ACCEN0_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN6 */
+#define IFX_MTU_ACCEN0_EN6_OFF (6u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN7 */
+#define IFX_MTU_ACCEN0_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN7 */
+#define IFX_MTU_ACCEN0_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN7 */
+#define IFX_MTU_ACCEN0_EN7_OFF (7u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN8 */
+#define IFX_MTU_ACCEN0_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN8 */
+#define IFX_MTU_ACCEN0_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN8 */
+#define IFX_MTU_ACCEN0_EN8_OFF (8u)
+
+/** \brief Length for Ifx_MTU_ACCEN0_Bits.EN9 */
+#define IFX_MTU_ACCEN0_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_ACCEN0_Bits.EN9 */
+#define IFX_MTU_ACCEN0_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_ACCEN0_Bits.EN9 */
+#define IFX_MTU_ACCEN0_EN9_OFF (9u)
+
+/** \brief Length for Ifx_MTU_CLC_Bits.DISR */
+#define IFX_MTU_CLC_DISR_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_CLC_Bits.DISR */
+#define IFX_MTU_CLC_DISR_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_CLC_Bits.DISR */
+#define IFX_MTU_CLC_DISR_OFF (0u)
+
+/** \brief Length for Ifx_MTU_CLC_Bits.DISS */
+#define IFX_MTU_CLC_DISS_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_CLC_Bits.DISS */
+#define IFX_MTU_CLC_DISS_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_CLC_Bits.DISS */
+#define IFX_MTU_CLC_DISS_OFF (1u)
+
+/** \brief Length for Ifx_MTU_CLC_Bits.EDIS */
+#define IFX_MTU_CLC_EDIS_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_CLC_Bits.EDIS */
+#define IFX_MTU_CLC_EDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_CLC_Bits.EDIS */
+#define IFX_MTU_CLC_EDIS_OFF (3u)
+
+/** \brief Length for Ifx_MTU_CLC_Bits.Resvd */
+#define IFX_MTU_CLC_RESVD_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_CLC_Bits.Resvd */
+#define IFX_MTU_CLC_RESVD_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_CLC_Bits.Resvd */
+#define IFX_MTU_CLC_RESVD_OFF (2u)
+
+/** \brief Length for Ifx_MTU_ID_Bits.MODNUMBER */
+#define IFX_MTU_ID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_MTU_ID_Bits.MODNUMBER */
+#define IFX_MTU_ID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_MTU_ID_Bits.MODNUMBER */
+#define IFX_MTU_ID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_MTU_ID_Bits.MODREV */
+#define IFX_MTU_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_MTU_ID_Bits.MODREV */
+#define IFX_MTU_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_MTU_ID_Bits.MODREV */
+#define IFX_MTU_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_MTU_ID_Bits.MODTYPE */
+#define IFX_MTU_ID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_MTU_ID_Bits.MODTYPE */
+#define IFX_MTU_ID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_MTU_ID_Bits.MODTYPE */
+#define IFX_MTU_ID_MODTYPE_OFF (8u)
+
+/** \brief Length for Ifx_MTU_MEMMAP_Bits.CPU0DxMAP */
+#define IFX_MTU_MEMMAP_CPU0DXMAP_LEN (2u)
+
+/** \brief Mask for Ifx_MTU_MEMMAP_Bits.CPU0DxMAP */
+#define IFX_MTU_MEMMAP_CPU0DXMAP_MSK (0x3u)
+
+/** \brief Offset for Ifx_MTU_MEMMAP_Bits.CPU0DxMAP */
+#define IFX_MTU_MEMMAP_CPU0DXMAP_OFF (18u)
+
+/** \brief Length for Ifx_MTU_MEMMAP_Bits.CPU0PCMAP */
+#define IFX_MTU_MEMMAP_CPU0PCMAP_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMMAP_Bits.CPU0PCMAP */
+#define IFX_MTU_MEMMAP_CPU0PCMAP_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMMAP_Bits.CPU0PCMAP */
+#define IFX_MTU_MEMMAP_CPU0PCMAP_OFF (15u)
+
+/** \brief Length for Ifx_MTU_MEMMAP_Bits.CPU0PTMAP */
+#define IFX_MTU_MEMMAP_CPU0PTMAP_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMMAP_Bits.CPU0PTMAP */
+#define IFX_MTU_MEMMAP_CPU0PTMAP_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMMAP_Bits.CPU0PTMAP */
+#define IFX_MTU_MEMMAP_CPU0PTMAP_OFF (17u)
+
+/** \brief Length for Ifx_MTU_MEMMAP_Bits.CPU1DCMAP */
+#define IFX_MTU_MEMMAP_CPU1DCMAP_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMMAP_Bits.CPU1DCMAP */
+#define IFX_MTU_MEMMAP_CPU1DCMAP_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMMAP_Bits.CPU1DCMAP */
+#define IFX_MTU_MEMMAP_CPU1DCMAP_OFF (7u)
+
+/** \brief Length for Ifx_MTU_MEMMAP_Bits.CPU1DTMAP */
+#define IFX_MTU_MEMMAP_CPU1DTMAP_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMMAP_Bits.CPU1DTMAP */
+#define IFX_MTU_MEMMAP_CPU1DTMAP_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMMAP_Bits.CPU1DTMAP */
+#define IFX_MTU_MEMMAP_CPU1DTMAP_OFF (8u)
+
+/** \brief Length for Ifx_MTU_MEMMAP_Bits.CPU1PCMAP */
+#define IFX_MTU_MEMMAP_CPU1PCMAP_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMMAP_Bits.CPU1PCMAP */
+#define IFX_MTU_MEMMAP_CPU1PCMAP_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMMAP_Bits.CPU1PCMAP */
+#define IFX_MTU_MEMMAP_CPU1PCMAP_OFF (10u)
+
+/** \brief Length for Ifx_MTU_MEMMAP_Bits.CPU1PTMAP */
+#define IFX_MTU_MEMMAP_CPU1PTMAP_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMMAP_Bits.CPU1PTMAP */
+#define IFX_MTU_MEMMAP_CPU1PTMAP_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMMAP_Bits.CPU1PTMAP */
+#define IFX_MTU_MEMMAP_CPU1PTMAP_OFF (11u)
+
+/** \brief Length for Ifx_MTU_MEMMAP_Bits.CPU2DxMAP */
+#define IFX_MTU_MEMMAP_CPU2DXMAP_LEN (2u)
+
+/** \brief Mask for Ifx_MTU_MEMMAP_Bits.CPU2DxMAP */
+#define IFX_MTU_MEMMAP_CPU2DXMAP_MSK (0x3u)
+
+/** \brief Offset for Ifx_MTU_MEMMAP_Bits.CPU2DxMAP */
+#define IFX_MTU_MEMMAP_CPU2DXMAP_OFF (1u)
+
+/** \brief Length for Ifx_MTU_MEMMAP_Bits.CPU2PxMAP */
+#define IFX_MTU_MEMMAP_CPU2PXMAP_LEN (2u)
+
+/** \brief Mask for Ifx_MTU_MEMMAP_Bits.CPU2PxMAP */
+#define IFX_MTU_MEMMAP_CPU2PXMAP_MSK (0x3u)
+
+/** \brief Offset for Ifx_MTU_MEMMAP_Bits.CPU2PxMAP */
+#define IFX_MTU_MEMMAP_CPU2PXMAP_OFF (4u)
+
+/** \brief Length for Ifx_MTU_MEMSTAT0_Bits.CPU0DS2AIU */
+#define IFX_MTU_MEMSTAT0_CPU0DS2AIU_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMSTAT0_Bits.CPU0DS2AIU */
+#define IFX_MTU_MEMSTAT0_CPU0DS2AIU_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMSTAT0_Bits.CPU0DS2AIU */
+#define IFX_MTU_MEMSTAT0_CPU0DS2AIU_OFF (27u)
+
+/** \brief Length for Ifx_MTU_MEMSTAT0_Bits.CPU0DSAIU */
+#define IFX_MTU_MEMSTAT0_CPU0DSAIU_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMSTAT0_Bits.CPU0DSAIU */
+#define IFX_MTU_MEMSTAT0_CPU0DSAIU_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMSTAT0_Bits.CPU0DSAIU */
+#define IFX_MTU_MEMSTAT0_CPU0DSAIU_OFF (14u)
+
+/** \brief Length for Ifx_MTU_MEMSTAT0_Bits.CPU0DxAIU */
+#define IFX_MTU_MEMSTAT0_CPU0DXAIU_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMSTAT0_Bits.CPU0DxAIU */
+#define IFX_MTU_MEMSTAT0_CPU0DXAIU_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMSTAT0_Bits.CPU0DxAIU */
+#define IFX_MTU_MEMSTAT0_CPU0DXAIU_OFF (19u)
+
+/** \brief Length for Ifx_MTU_MEMSTAT0_Bits.CPU0PSAIU */
+#define IFX_MTU_MEMSTAT0_CPU0PSAIU_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMSTAT0_Bits.CPU0PSAIU */
+#define IFX_MTU_MEMSTAT0_CPU0PSAIU_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMSTAT0_Bits.CPU0PSAIU */
+#define IFX_MTU_MEMSTAT0_CPU0PSAIU_OFF (16u)
+
+/** \brief Length for Ifx_MTU_MEMSTAT0_Bits.CPU0PTAIU */
+#define IFX_MTU_MEMSTAT0_CPU0PTAIU_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMSTAT0_Bits.CPU0PTAIU */
+#define IFX_MTU_MEMSTAT0_CPU0PTAIU_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMSTAT0_Bits.CPU0PTAIU */
+#define IFX_MTU_MEMSTAT0_CPU0PTAIU_OFF (17u)
+
+/** \brief Length for Ifx_MTU_MEMSTAT0_Bits.CPU1DS2AIU */
+#define IFX_MTU_MEMSTAT0_CPU1DS2AIU_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMSTAT0_Bits.CPU1DS2AIU */
+#define IFX_MTU_MEMSTAT0_CPU1DS2AIU_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMSTAT0_Bits.CPU1DS2AIU */
+#define IFX_MTU_MEMSTAT0_CPU1DS2AIU_OFF (20u)
+
+/** \brief Length for Ifx_MTU_MEMSTAT0_Bits.CPU1DSAIU */
+#define IFX_MTU_MEMSTAT0_CPU1DSAIU_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMSTAT0_Bits.CPU1DSAIU */
+#define IFX_MTU_MEMSTAT0_CPU1DSAIU_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMSTAT0_Bits.CPU1DSAIU */
+#define IFX_MTU_MEMSTAT0_CPU1DSAIU_OFF (6u)
+
+/** \brief Length for Ifx_MTU_MEMSTAT0_Bits.CPU1DTAIU */
+#define IFX_MTU_MEMSTAT0_CPU1DTAIU_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMSTAT0_Bits.CPU1DTAIU */
+#define IFX_MTU_MEMSTAT0_CPU1DTAIU_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMSTAT0_Bits.CPU1DTAIU */
+#define IFX_MTU_MEMSTAT0_CPU1DTAIU_OFF (8u)
+
+/** \brief Length for Ifx_MTU_MEMSTAT0_Bits.CPU1PSAIU */
+#define IFX_MTU_MEMSTAT0_CPU1PSAIU_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMSTAT0_Bits.CPU1PSAIU */
+#define IFX_MTU_MEMSTAT0_CPU1PSAIU_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMSTAT0_Bits.CPU1PSAIU */
+#define IFX_MTU_MEMSTAT0_CPU1PSAIU_OFF (9u)
+
+/** \brief Length for Ifx_MTU_MEMSTAT0_Bits.CPU1PTAIU */
+#define IFX_MTU_MEMSTAT0_CPU1PTAIU_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMSTAT0_Bits.CPU1PTAIU */
+#define IFX_MTU_MEMSTAT0_CPU1PTAIU_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMSTAT0_Bits.CPU1PTAIU */
+#define IFX_MTU_MEMSTAT0_CPU1PTAIU_OFF (11u)
+
+/** \brief Length for Ifx_MTU_MEMSTAT0_Bits.CPU2DS2AIU */
+#define IFX_MTU_MEMSTAT0_CPU2DS2AIU_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMSTAT0_Bits.CPU2DS2AIU */
+#define IFX_MTU_MEMSTAT0_CPU2DS2AIU_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMSTAT0_Bits.CPU2DS2AIU */
+#define IFX_MTU_MEMSTAT0_CPU2DS2AIU_OFF (21u)
+
+/** \brief Length for Ifx_MTU_MEMSTAT0_Bits.CPU2DSAIU */
+#define IFX_MTU_MEMSTAT0_CPU2DSAIU_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMSTAT0_Bits.CPU2DSAIU */
+#define IFX_MTU_MEMSTAT0_CPU2DSAIU_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMSTAT0_Bits.CPU2DSAIU */
+#define IFX_MTU_MEMSTAT0_CPU2DSAIU_OFF (0u)
+
+/** \brief Length for Ifx_MTU_MEMSTAT0_Bits.CPU2DTAIU */
+#define IFX_MTU_MEMSTAT0_CPU2DTAIU_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMSTAT0_Bits.CPU2DTAIU */
+#define IFX_MTU_MEMSTAT0_CPU2DTAIU_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMSTAT0_Bits.CPU2DTAIU */
+#define IFX_MTU_MEMSTAT0_CPU2DTAIU_OFF (2u)
+
+/** \brief Length for Ifx_MTU_MEMSTAT0_Bits.CPU2PSAIU */
+#define IFX_MTU_MEMSTAT0_CPU2PSAIU_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMSTAT0_Bits.CPU2PSAIU */
+#define IFX_MTU_MEMSTAT0_CPU2PSAIU_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMSTAT0_Bits.CPU2PSAIU */
+#define IFX_MTU_MEMSTAT0_CPU2PSAIU_OFF (3u)
+
+/** \brief Length for Ifx_MTU_MEMSTAT0_Bits.CPU2PTAIU */
+#define IFX_MTU_MEMSTAT0_CPU2PTAIU_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMSTAT0_Bits.CPU2PTAIU */
+#define IFX_MTU_MEMSTAT0_CPU2PTAIU_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMSTAT0_Bits.CPU2PTAIU */
+#define IFX_MTU_MEMSTAT0_CPU2PTAIU_OFF (5u)
+
+/** \brief Length for Ifx_MTU_MEMSTAT0_Bits.FSI0AIU */
+#define IFX_MTU_MEMSTAT0_FSI0AIU_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMSTAT0_Bits.FSI0AIU */
+#define IFX_MTU_MEMSTAT0_FSI0AIU_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMSTAT0_Bits.FSI0AIU */
+#define IFX_MTU_MEMSTAT0_FSI0AIU_OFF (26u)
+
+/** \brief Length for Ifx_MTU_MEMSTAT0_Bits.HSMCAIU */
+#define IFX_MTU_MEMSTAT0_HSMCAIU_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMSTAT0_Bits.HSMCAIU */
+#define IFX_MTU_MEMSTAT0_HSMCAIU_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMSTAT0_Bits.HSMCAIU */
+#define IFX_MTU_MEMSTAT0_HSMCAIU_OFF (23u)
+
+/** \brief Length for Ifx_MTU_MEMSTAT0_Bits.HSMRAIU */
+#define IFX_MTU_MEMSTAT0_HSMRAIU_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMSTAT0_Bits.HSMRAIU */
+#define IFX_MTU_MEMSTAT0_HSMRAIU_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMSTAT0_Bits.HSMRAIU */
+#define IFX_MTU_MEMSTAT0_HSMRAIU_OFF (25u)
+
+/** \brief Length for Ifx_MTU_MEMSTAT0_Bits.HSMTAIU */
+#define IFX_MTU_MEMSTAT0_HSMTAIU_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMSTAT0_Bits.HSMTAIU */
+#define IFX_MTU_MEMSTAT0_HSMTAIU_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMSTAT0_Bits.HSMTAIU */
+#define IFX_MTU_MEMSTAT0_HSMTAIU_OFF (24u)
+
+/** \brief Length for Ifx_MTU_MEMTEST0_Bits.CPU0DS2EN */
+#define IFX_MTU_MEMTEST0_CPU0DS2EN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST0_Bits.CPU0DS2EN */
+#define IFX_MTU_MEMTEST0_CPU0DS2EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST0_Bits.CPU0DS2EN */
+#define IFX_MTU_MEMTEST0_CPU0DS2EN_OFF (27u)
+
+/** \brief Length for Ifx_MTU_MEMTEST0_Bits.CPU0DSEN */
+#define IFX_MTU_MEMTEST0_CPU0DSEN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST0_Bits.CPU0DSEN */
+#define IFX_MTU_MEMTEST0_CPU0DSEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST0_Bits.CPU0DSEN */
+#define IFX_MTU_MEMTEST0_CPU0DSEN_OFF (14u)
+
+/** \brief Length for Ifx_MTU_MEMTEST0_Bits.CPU0DTEN */
+#define IFX_MTU_MEMTEST0_CPU0DTEN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST0_Bits.CPU0DTEN */
+#define IFX_MTU_MEMTEST0_CPU0DTEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST0_Bits.CPU0DTEN */
+#define IFX_MTU_MEMTEST0_CPU0DTEN_OFF (19u)
+
+/** \brief Length for Ifx_MTU_MEMTEST0_Bits.CPU0PSEN */
+#define IFX_MTU_MEMTEST0_CPU0PSEN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST0_Bits.CPU0PSEN */
+#define IFX_MTU_MEMTEST0_CPU0PSEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST0_Bits.CPU0PSEN */
+#define IFX_MTU_MEMTEST0_CPU0PSEN_OFF (16u)
+
+/** \brief Length for Ifx_MTU_MEMTEST0_Bits.CPU0PTEN */
+#define IFX_MTU_MEMTEST0_CPU0PTEN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST0_Bits.CPU0PTEN */
+#define IFX_MTU_MEMTEST0_CPU0PTEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST0_Bits.CPU0PTEN */
+#define IFX_MTU_MEMTEST0_CPU0PTEN_OFF (17u)
+
+/** \brief Length for Ifx_MTU_MEMTEST0_Bits.CPU1DSEN */
+#define IFX_MTU_MEMTEST0_CPU1DSEN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST0_Bits.CPU1DSEN */
+#define IFX_MTU_MEMTEST0_CPU1DSEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST0_Bits.CPU1DSEN */
+#define IFX_MTU_MEMTEST0_CPU1DSEN_OFF (6u)
+
+/** \brief Length for Ifx_MTU_MEMTEST0_Bits.CPU1DTEN */
+#define IFX_MTU_MEMTEST0_CPU1DTEN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST0_Bits.CPU1DTEN */
+#define IFX_MTU_MEMTEST0_CPU1DTEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST0_Bits.CPU1DTEN */
+#define IFX_MTU_MEMTEST0_CPU1DTEN_OFF (8u)
+
+/** \brief Length for Ifx_MTU_MEMTEST0_Bits.CPU1PSEN */
+#define IFX_MTU_MEMTEST0_CPU1PSEN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST0_Bits.CPU1PSEN */
+#define IFX_MTU_MEMTEST0_CPU1PSEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST0_Bits.CPU1PSEN */
+#define IFX_MTU_MEMTEST0_CPU1PSEN_OFF (9u)
+
+/** \brief Length for Ifx_MTU_MEMTEST0_Bits.CPU1PTEN */
+#define IFX_MTU_MEMTEST0_CPU1PTEN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST0_Bits.CPU1PTEN */
+#define IFX_MTU_MEMTEST0_CPU1PTEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST0_Bits.CPU1PTEN */
+#define IFX_MTU_MEMTEST0_CPU1PTEN_OFF (11u)
+
+/** \brief Length for Ifx_MTU_MEMTEST0_Bits.CPU2XEN */
+#define IFX_MTU_MEMTEST0_CPU2XEN_LEN (6u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST0_Bits.CPU2XEN */
+#define IFX_MTU_MEMTEST0_CPU2XEN_MSK (0x3fu)
+
+/** \brief Offset for Ifx_MTU_MEMTEST0_Bits.CPU2XEN */
+#define IFX_MTU_MEMTEST0_CPU2XEN_OFF (0u)
+
+/** \brief Length for Ifx_MTU_MEMTEST0_Bits.CPUXDS2EN */
+#define IFX_MTU_MEMTEST0_CPUXDS2EN_LEN (2u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST0_Bits.CPUXDS2EN */
+#define IFX_MTU_MEMTEST0_CPUXDS2EN_MSK (0x3u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST0_Bits.CPUXDS2EN */
+#define IFX_MTU_MEMTEST0_CPUXDS2EN_OFF (20u)
+
+/** \brief Length for Ifx_MTU_MEMTEST0_Bits.ETHEN */
+#define IFX_MTU_MEMTEST0_ETHEN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST0_Bits.ETHEN */
+#define IFX_MTU_MEMTEST0_ETHEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST0_Bits.ETHEN */
+#define IFX_MTU_MEMTEST0_ETHEN_OFF (22u)
+
+/** \brief Length for Ifx_MTU_MEMTEST0_Bits.FSI0EN */
+#define IFX_MTU_MEMTEST0_FSI0EN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST0_Bits.FSI0EN */
+#define IFX_MTU_MEMTEST0_FSI0EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST0_Bits.FSI0EN */
+#define IFX_MTU_MEMTEST0_FSI0EN_OFF (26u)
+
+/** \brief Length for Ifx_MTU_MEMTEST0_Bits.GTM1AEN */
+#define IFX_MTU_MEMTEST0_GTM1AEN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST0_Bits.GTM1AEN */
+#define IFX_MTU_MEMTEST0_GTM1AEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST0_Bits.GTM1AEN */
+#define IFX_MTU_MEMTEST0_GTM1AEN_OFF (31u)
+
+/** \brief Length for Ifx_MTU_MEMTEST0_Bits.GTMFEN */
+#define IFX_MTU_MEMTEST0_GTMFEN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST0_Bits.GTMFEN */
+#define IFX_MTU_MEMTEST0_GTMFEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST0_Bits.GTMFEN */
+#define IFX_MTU_MEMTEST0_GTMFEN_OFF (28u)
+
+/** \brief Length for Ifx_MTU_MEMTEST0_Bits.GTMM0EN */
+#define IFX_MTU_MEMTEST0_GTMM0EN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST0_Bits.GTMM0EN */
+#define IFX_MTU_MEMTEST0_GTMM0EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST0_Bits.GTMM0EN */
+#define IFX_MTU_MEMTEST0_GTMM0EN_OFF (29u)
+
+/** \brief Length for Ifx_MTU_MEMTEST0_Bits.GTMM1EN */
+#define IFX_MTU_MEMTEST0_GTMM1EN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST0_Bits.GTMM1EN */
+#define IFX_MTU_MEMTEST0_GTMM1EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST0_Bits.GTMM1EN */
+#define IFX_MTU_MEMTEST0_GTMM1EN_OFF (30u)
+
+/** \brief Length for Ifx_MTU_MEMTEST0_Bits.LMUEN */
+#define IFX_MTU_MEMTEST0_LMUEN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST0_Bits.LMUEN */
+#define IFX_MTU_MEMTEST0_LMUEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST0_Bits.LMUEN */
+#define IFX_MTU_MEMTEST0_LMUEN_OFF (12u)
+
+/** \brief Length for Ifx_MTU_MEMTEST0_Bits.MMCDSEN */
+#define IFX_MTU_MEMTEST0_MMCDSEN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST0_Bits.MMCDSEN */
+#define IFX_MTU_MEMTEST0_MMCDSEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST0_Bits.MMCDSEN */
+#define IFX_MTU_MEMTEST0_MMCDSEN_OFF (13u)
+
+/** \brief Length for Ifx_MTU_MEMTEST0_Bits.Res */
+#define IFX_MTU_MEMTEST0_RES_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST0_Bits.Res */
+#define IFX_MTU_MEMTEST0_RES_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST0_Bits.Res */
+#define IFX_MTU_MEMTEST0_RES_OFF (7u)
+
+/** \brief Length for Ifx_MTU_MEMTEST1_Bits.EMEML0EN */
+#define IFX_MTU_MEMTEST1_EMEML0EN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST1_Bits.EMEML0EN */
+#define IFX_MTU_MEMTEST1_EMEML0EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST1_Bits.EMEML0EN */
+#define IFX_MTU_MEMTEST1_EMEML0EN_OFF (14u)
+
+/** \brief Length for Ifx_MTU_MEMTEST1_Bits.EMEML1EN */
+#define IFX_MTU_MEMTEST1_EMEML1EN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST1_Bits.EMEML1EN */
+#define IFX_MTU_MEMTEST1_EMEML1EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST1_Bits.EMEML1EN */
+#define IFX_MTU_MEMTEST1_EMEML1EN_OFF (15u)
+
+/** \brief Length for Ifx_MTU_MEMTEST1_Bits.EMEML2EN */
+#define IFX_MTU_MEMTEST1_EMEML2EN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST1_Bits.EMEML2EN */
+#define IFX_MTU_MEMTEST1_EMEML2EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST1_Bits.EMEML2EN */
+#define IFX_MTU_MEMTEST1_EMEML2EN_OFF (16u)
+
+/** \brief Length for Ifx_MTU_MEMTEST1_Bits.EMEML3EN */
+#define IFX_MTU_MEMTEST1_EMEML3EN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST1_Bits.EMEML3EN */
+#define IFX_MTU_MEMTEST1_EMEML3EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST1_Bits.EMEML3EN */
+#define IFX_MTU_MEMTEST1_EMEML3EN_OFF (17u)
+
+/** \brief Length for Ifx_MTU_MEMTEST1_Bits.EMEML4EN */
+#define IFX_MTU_MEMTEST1_EMEML4EN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST1_Bits.EMEML4EN */
+#define IFX_MTU_MEMTEST1_EMEML4EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST1_Bits.EMEML4EN */
+#define IFX_MTU_MEMTEST1_EMEML4EN_OFF (18u)
+
+/** \brief Length for Ifx_MTU_MEMTEST1_Bits.EMEML5EN */
+#define IFX_MTU_MEMTEST1_EMEML5EN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST1_Bits.EMEML5EN */
+#define IFX_MTU_MEMTEST1_EMEML5EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST1_Bits.EMEML5EN */
+#define IFX_MTU_MEMTEST1_EMEML5EN_OFF (19u)
+
+/** \brief Length for Ifx_MTU_MEMTEST1_Bits.EMEML6EN */
+#define IFX_MTU_MEMTEST1_EMEML6EN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST1_Bits.EMEML6EN */
+#define IFX_MTU_MEMTEST1_EMEML6EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST1_Bits.EMEML6EN */
+#define IFX_MTU_MEMTEST1_EMEML6EN_OFF (20u)
+
+/** \brief Length for Ifx_MTU_MEMTEST1_Bits.EMEML7EN */
+#define IFX_MTU_MEMTEST1_EMEML7EN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST1_Bits.EMEML7EN */
+#define IFX_MTU_MEMTEST1_EMEML7EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST1_Bits.EMEML7EN */
+#define IFX_MTU_MEMTEST1_EMEML7EN_OFF (21u)
+
+/** \brief Length for Ifx_MTU_MEMTEST1_Bits.EMEMLXEN */
+#define IFX_MTU_MEMTEST1_EMEMLXEN_LEN (8u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST1_Bits.EMEMLXEN */
+#define IFX_MTU_MEMTEST1_EMEMLXEN_MSK (0xffu)
+
+/** \brief Offset for Ifx_MTU_MEMTEST1_Bits.EMEMLXEN */
+#define IFX_MTU_MEMTEST1_EMEMLXEN_OFF (22u)
+
+/** \brief Length for Ifx_MTU_MEMTEST1_Bits.EMEMUXEN */
+#define IFX_MTU_MEMTEST1_EMEMUXEN_LEN (2u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST1_Bits.EMEMUXEN */
+#define IFX_MTU_MEMTEST1_EMEMUXEN_MSK (0x3u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST1_Bits.EMEMUXEN */
+#define IFX_MTU_MEMTEST1_EMEMUXEN_OFF (30u)
+
+/** \brief Length for Ifx_MTU_MEMTEST1_Bits.ERAY0MEN */
+#define IFX_MTU_MEMTEST1_ERAY0MEN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST1_Bits.ERAY0MEN */
+#define IFX_MTU_MEMTEST1_ERAY0MEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST1_Bits.ERAY0MEN */
+#define IFX_MTU_MEMTEST1_ERAY0MEN_OFF (8u)
+
+/** \brief Length for Ifx_MTU_MEMTEST1_Bits.ERAY0OEN */
+#define IFX_MTU_MEMTEST1_ERAY0OEN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST1_Bits.ERAY0OEN */
+#define IFX_MTU_MEMTEST1_ERAY0OEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST1_Bits.ERAY0OEN */
+#define IFX_MTU_MEMTEST1_ERAY0OEN_OFF (6u)
+
+/** \brief Length for Ifx_MTU_MEMTEST1_Bits.ERAY0TEN */
+#define IFX_MTU_MEMTEST1_ERAY0TEN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST1_Bits.ERAY0TEN */
+#define IFX_MTU_MEMTEST1_ERAY0TEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST1_Bits.ERAY0TEN */
+#define IFX_MTU_MEMTEST1_ERAY0TEN_OFF (7u)
+
+/** \brief Length for Ifx_MTU_MEMTEST1_Bits.ERAY1XEN */
+#define IFX_MTU_MEMTEST1_ERAY1XEN_LEN (3u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST1_Bits.ERAY1XEN */
+#define IFX_MTU_MEMTEST1_ERAY1XEN_MSK (0x7u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST1_Bits.ERAY1XEN */
+#define IFX_MTU_MEMTEST1_ERAY1XEN_OFF (9u)
+
+/** \brief Length for Ifx_MTU_MEMTEST1_Bits.GTM1BEN */
+#define IFX_MTU_MEMTEST1_GTM1BEN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST1_Bits.GTM1BEN */
+#define IFX_MTU_MEMTEST1_GTM1BEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST1_Bits.GTM1BEN */
+#define IFX_MTU_MEMTEST1_GTM1BEN_OFF (0u)
+
+/** \brief Length for Ifx_MTU_MEMTEST1_Bits.GTM2EN */
+#define IFX_MTU_MEMTEST1_GTM2EN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST1_Bits.GTM2EN */
+#define IFX_MTU_MEMTEST1_GTM2EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST1_Bits.GTM2EN */
+#define IFX_MTU_MEMTEST1_GTM2EN_OFF (1u)
+
+/** \brief Length for Ifx_MTU_MEMTEST1_Bits.MCAN0EN */
+#define IFX_MTU_MEMTEST1_MCAN0EN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST1_Bits.MCAN0EN */
+#define IFX_MTU_MEMTEST1_MCAN0EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST1_Bits.MCAN0EN */
+#define IFX_MTU_MEMTEST1_MCAN0EN_OFF (4u)
+
+/** \brief Length for Ifx_MTU_MEMTEST1_Bits.MCAN1EN */
+#define IFX_MTU_MEMTEST1_MCAN1EN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST1_Bits.MCAN1EN */
+#define IFX_MTU_MEMTEST1_MCAN1EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST1_Bits.MCAN1EN */
+#define IFX_MTU_MEMTEST1_MCAN1EN_OFF (5u)
+
+/** \brief Length for Ifx_MTU_MEMTEST1_Bits.MCDSEN */
+#define IFX_MTU_MEMTEST1_MCDSEN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST1_Bits.MCDSEN */
+#define IFX_MTU_MEMTEST1_MCDSEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST1_Bits.MCDSEN */
+#define IFX_MTU_MEMTEST1_MCDSEN_OFF (13u)
+
+/** \brief Length for Ifx_MTU_MEMTEST1_Bits.PSI5EN */
+#define IFX_MTU_MEMTEST1_PSI5EN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST1_Bits.PSI5EN */
+#define IFX_MTU_MEMTEST1_PSI5EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST1_Bits.PSI5EN */
+#define IFX_MTU_MEMTEST1_PSI5EN_OFF (2u)
+
+/** \brief Length for Ifx_MTU_MEMTEST1_Bits.STBY1EN */
+#define IFX_MTU_MEMTEST1_STBY1EN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST1_Bits.STBY1EN */
+#define IFX_MTU_MEMTEST1_STBY1EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST1_Bits.STBY1EN */
+#define IFX_MTU_MEMTEST1_STBY1EN_OFF (12u)
+
+/** \brief Length for Ifx_MTU_MEMTEST2_Bits.CIF0EN */
+#define IFX_MTU_MEMTEST2_CIF0EN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST2_Bits.CIF0EN */
+#define IFX_MTU_MEMTEST2_CIF0EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST2_Bits.CIF0EN */
+#define IFX_MTU_MEMTEST2_CIF0EN_OFF (14u)
+
+/** \brief Length for Ifx_MTU_MEMTEST2_Bits.CIF1EN */
+#define IFX_MTU_MEMTEST2_CIF1EN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST2_Bits.CIF1EN */
+#define IFX_MTU_MEMTEST2_CIF1EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST2_Bits.CIF1EN */
+#define IFX_MTU_MEMTEST2_CIF1EN_OFF (16u)
+
+/** \brief Length for Ifx_MTU_MEMTEST2_Bits.CIF2EN */
+#define IFX_MTU_MEMTEST2_CIF2EN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST2_Bits.CIF2EN */
+#define IFX_MTU_MEMTEST2_CIF2EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST2_Bits.CIF2EN */
+#define IFX_MTU_MEMTEST2_CIF2EN_OFF (17u)
+
+/** \brief Length for Ifx_MTU_MEMTEST2_Bits.DAMEN */
+#define IFX_MTU_MEMTEST2_DAMEN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST2_Bits.DAMEN */
+#define IFX_MTU_MEMTEST2_DAMEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST2_Bits.DAMEN */
+#define IFX_MTU_MEMTEST2_DAMEN_OFF (15u)
+
+/** \brief Length for Ifx_MTU_MEMTEST2_Bits.DMAEN */
+#define IFX_MTU_MEMTEST2_DMAEN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST2_Bits.DMAEN */
+#define IFX_MTU_MEMTEST2_DMAEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST2_Bits.DMAEN */
+#define IFX_MTU_MEMTEST2_DMAEN_OFF (19u)
+
+/** \brief Length for Ifx_MTU_MEMTEST2_Bits.EMEMUxEN */
+#define IFX_MTU_MEMTEST2_EMEMUXEN_LEN (14u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST2_Bits.EMEMUxEN */
+#define IFX_MTU_MEMTEST2_EMEMUXEN_MSK (0x3fffu)
+
+/** \brief Offset for Ifx_MTU_MEMTEST2_Bits.EMEMUxEN */
+#define IFX_MTU_MEMTEST2_EMEMUXEN_OFF (0u)
+
+/** \brief Length for Ifx_MTU_MEMTEST2_Bits.FFT0EN */
+#define IFX_MTU_MEMTEST2_FFT0EN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST2_Bits.FFT0EN */
+#define IFX_MTU_MEMTEST2_FFT0EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST2_Bits.FFT0EN */
+#define IFX_MTU_MEMTEST2_FFT0EN_OFF (22u)
+
+/** \brief Length for Ifx_MTU_MEMTEST2_Bits.FFT1EN */
+#define IFX_MTU_MEMTEST2_FFT1EN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST2_Bits.FFT1EN */
+#define IFX_MTU_MEMTEST2_FFT1EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST2_Bits.FFT1EN */
+#define IFX_MTU_MEMTEST2_FFT1EN_OFF (23u)
+
+/** \brief Length for Ifx_MTU_MEMTEST2_Bits.STBY2EN */
+#define IFX_MTU_MEMTEST2_STBY2EN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST2_Bits.STBY2EN */
+#define IFX_MTU_MEMTEST2_STBY2EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST2_Bits.STBY2EN */
+#define IFX_MTU_MEMTEST2_STBY2EN_OFF (18u)
+
+/** \brief Length for Ifx_MTU_MEMTEST2_Bits.XTM0EN */
+#define IFX_MTU_MEMTEST2_XTM0EN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST2_Bits.XTM0EN */
+#define IFX_MTU_MEMTEST2_XTM0EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST2_Bits.XTM0EN */
+#define IFX_MTU_MEMTEST2_XTM0EN_OFF (20u)
+
+/** \brief Length for Ifx_MTU_MEMTEST2_Bits.XTM1EN */
+#define IFX_MTU_MEMTEST2_XTM1EN_LEN (1u)
+
+/** \brief Mask for Ifx_MTU_MEMTEST2_Bits.XTM1EN */
+#define IFX_MTU_MEMTEST2_XTM1EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_MTU_MEMTEST2_Bits.XTM1EN */
+#define IFX_MTU_MEMTEST2_XTM1EN_OFF (21u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXMTU_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxMtu_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxMtu_reg.h
new file mode 100644
index 0000000..1f531ea
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxMtu_reg.h
@@ -0,0 +1,84 @@
+/**
+ * \file IfxMtu_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Mtu_Cfg Mtu address
+ * \ingroup IfxLld_Mtu
+ *
+ * \defgroup IfxLld_Mtu_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Mtu_Cfg
+ *
+ * \defgroup IfxLld_Mtu_Cfg_Mtu 2-MTU
+ * \ingroup IfxLld_Mtu_Cfg
+ *
+ */
+#ifndef IFXMTU_REG_H
+#define IFXMTU_REG_H 1
+/******************************************************************************/
+#include "IfxMtu_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Mtu_Cfg_BaseAddress
+ * \{ */
+
+/** \brief MTU object */
+#define MODULE_MTU /*lint --e(923)*/ (*(Ifx_MTU*)0xF0060000u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mtu_Cfg_Mtu
+ * \{ */
+
+/** \brief FC, Access Enable Register 0 */
+#define MTU_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_MTU_ACCEN0*)0xF00600FCu)
+
+/** \brief F8, Access Enable Register 1 */
+#define MTU_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_MTU_ACCEN1*)0xF00600F8u)
+
+/** \brief 0, Identification Register */
+#define MTU_CLC /*lint --e(923)*/ (*(volatile Ifx_MTU_CLC*)0xF0060000u)
+
+/** \brief 8, Identification Register */
+#define MTU_ID /*lint --e(923)*/ (*(volatile Ifx_MTU_ID*)0xF0060008u)
+
+/** \brief 1C, Memory Mapping Enable Register */
+#define MTU_MEMMAP /*lint --e(923)*/ (*(volatile Ifx_MTU_MEMMAP*)0xF006001Cu)
+
+/** \brief 38, Memory Status Register 0 */
+#define MTU_MEMSTAT0 /*lint --e(923)*/ (*(volatile Ifx_MTU_MEMSTAT0*)0xF0060038u)
+
+/** \brief 3C, Memory Status Register 1 */
+#define MTU_MEMSTAT1 /*lint --e(923)*/ (*(volatile Ifx_MTU_MEMSTAT1*)0xF006003Cu)
+
+/** \brief 40, Memory Status Register 2 */
+#define MTU_MEMSTAT2 /*lint --e(923)*/ (*(volatile Ifx_MTU_MEMSTAT2*)0xF0060040u)
+
+/** \brief 10, Memory MBISTEnable Register 0 */
+#define MTU_MEMTEST0 /*lint --e(923)*/ (*(volatile Ifx_MTU_MEMTEST0*)0xF0060010u)
+
+/** \brief 14, Memory MBISTEnable Register 1 */
+#define MTU_MEMTEST1 /*lint --e(923)*/ (*(volatile Ifx_MTU_MEMTEST1*)0xF0060014u)
+
+/** \brief 18, Memory MBISTEnable Register 2 */
+#define MTU_MEMTEST2 /*lint --e(923)*/ (*(volatile Ifx_MTU_MEMTEST2*)0xF0060018u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXMTU_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxMtu_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxMtu_regdef.h
new file mode 100644
index 0000000..0474787
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxMtu_regdef.h
@@ -0,0 +1,370 @@
+/**
+ * \file IfxMtu_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Mtu Mtu
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Mtu_Bitfields Bitfields
+ * \ingroup IfxLld_Mtu
+ *
+ * \defgroup IfxLld_Mtu_union Union
+ * \ingroup IfxLld_Mtu
+ *
+ * \defgroup IfxLld_Mtu_struct Struct
+ * \ingroup IfxLld_Mtu
+ *
+ */
+#ifndef IFXMTU_REGDEF_H
+#define IFXMTU_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Mtu_Bitfields
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef struct _Ifx_MTU_ACCEN0_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_MTU_ACCEN0_Bits;
+
+/** \brief Access Enable Register 1 */
+typedef struct _Ifx_MTU_ACCEN1_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_MTU_ACCEN1_Bits;
+
+/** \brief Identification Register */
+typedef struct _Ifx_MTU_CLC_Bits
+{
+ unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
+ unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
+ unsigned int Resvd:1; /**< \brief [2:2] Resvd (rw) */
+ unsigned int EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control (rw) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_MTU_CLC_Bits;
+
+/** \brief Identification Register */
+typedef struct _Ifx_MTU_ID_Bits
+{
+ unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
+ unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_MTU_ID_Bits;
+
+/** \brief Memory Mapping Enable Register */
+typedef struct _Ifx_MTU_MEMMAP_Bits
+{
+ unsigned int reserved_0:1; /**< \brief \internal Reserved */
+ unsigned int CPU2DxMAP:2; /**< \brief [2:1] Reserved in this product (r) */
+ unsigned int reserved_3:1; /**< \brief \internal Reserved */
+ unsigned int CPU2PxMAP:2; /**< \brief [5:4] Reserved in this product (r) */
+ unsigned int reserved_6:1; /**< \brief \internal Reserved */
+ unsigned int CPU1DCMAP:1; /**< \brief [7:7] CPU1 DCACHE Mapping (rwh) */
+ unsigned int CPU1DTMAP:1; /**< \brief [8:8] CPU1 DTAG Mapping (rh) */
+ unsigned int reserved_9:1; /**< \brief \internal Reserved */
+ unsigned int CPU1PCMAP:1; /**< \brief [10:10] CPU1 PCACHE Mapping (rwh) */
+ unsigned int CPU1PTMAP:1; /**< \brief [11:11] CPU1 PTAG Mapping (rh) */
+ unsigned int reserved_12:3; /**< \brief \internal Reserved */
+ unsigned int CPU0PCMAP:1; /**< \brief [15:15] CPU0 PCACHE Mapping (rwh) */
+ unsigned int reserved_16:1; /**< \brief \internal Reserved */
+ unsigned int CPU0PTMAP:1; /**< \brief [17:17] CPU0 PTAG Mapping (rh) */
+ unsigned int CPU0DxMAP:2; /**< \brief [19:18] Reserved in this product (r) */
+ unsigned int reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_MTU_MEMMAP_Bits;
+
+/** \brief Memory Status Register 0 */
+typedef struct _Ifx_MTU_MEMSTAT0_Bits
+{
+ unsigned int CPU2DSAIU:1; /**< \brief [0:0] Reserved in this product (r) */
+ unsigned int reserved_1:1; /**< \brief \internal Reserved */
+ unsigned int CPU2DTAIU:1; /**< \brief [2:2] Reserved in this product (r) */
+ unsigned int CPU2PSAIU:1; /**< \brief [3:3] Reserved in this product (r) */
+ unsigned int reserved_4:1; /**< \brief \internal Reserved */
+ unsigned int CPU2PTAIU:1; /**< \brief [5:5] Reserved in this product (r) */
+ unsigned int CPU1DSAIU:1; /**< \brief [6:6] CPU1 DCACHE Partial AutoInitialize Underway (rh) */
+ unsigned int reserved_7:1; /**< \brief \internal Reserved */
+ unsigned int CPU1DTAIU:1; /**< \brief [8:8] CPU1 DTAG MBIST AutoInitialize Underway (rh) */
+ unsigned int CPU1PSAIU:1; /**< \brief [9:9] CPU1 PCACHE Partial AutoInitialize Underway (rh) */
+ unsigned int reserved_10:1; /**< \brief \internal Reserved */
+ unsigned int CPU1PTAIU:1; /**< \brief [11:11] CPU1 PTAG MBIST AutoInitialize Underway (rh) */
+ unsigned int reserved_12:2; /**< \brief \internal Reserved */
+ unsigned int CPU0DSAIU:1; /**< \brief [14:14] Reserved in this product (r) */
+ unsigned int reserved_15:1; /**< \brief \internal Reserved */
+ unsigned int CPU0PSAIU:1; /**< \brief [16:16] CPU0 PCACHE Partial AutoInitialize Underway (rh) */
+ unsigned int CPU0PTAIU:1; /**< \brief [17:17] CPU0 PTAG MBIST AutoInitialize Underway (rh) */
+ unsigned int reserved_18:1; /**< \brief \internal Reserved */
+ unsigned int CPU0DxAIU:1; /**< \brief [19:19] Reserved in this product (r) */
+ unsigned int CPU1DS2AIU:1; /**< \brief [20:20] Reserved in this product (r) */
+ unsigned int CPU2DS2AIU:1; /**< \brief [21:21] Reserved in this product (r) */
+ unsigned int reserved_22:1; /**< \brief \internal Reserved */
+ unsigned int HSMCAIU:1; /**< \brief [23:23] Reserved in this product (r) */
+ unsigned int HSMTAIU:1; /**< \brief [24:24] Reserved in this product (r) */
+ unsigned int HSMRAIU:1; /**< \brief [25:25] Reserved in this product (r) */
+ unsigned int FSI0AIU:1; /**< \brief [26:26] FSI0 MBIST AutoInitialize Underway (rh) */
+ unsigned int CPU0DS2AIU:1; /**< \brief [27:27] Reserved in this product (r) */
+ unsigned int reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_MTU_MEMSTAT0_Bits;
+
+/** \brief Memory Status Register 1 */
+typedef struct _Ifx_MTU_MEMSTAT1_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_MTU_MEMSTAT1_Bits;
+
+/** \brief Memory Status Register 2 */
+typedef struct _Ifx_MTU_MEMSTAT2_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_MTU_MEMSTAT2_Bits;
+
+/** \brief Memory MBISTEnable Register 0 */
+typedef struct _Ifx_MTU_MEMTEST0_Bits
+{
+ unsigned int CPU2XEN:6; /**< \brief [5:0] Reserved in this product (r) */
+ unsigned int CPU1DSEN:1; /**< \brief [6:6] CPU1 TC1.6P DSPR MBIST Controller Memory Enable (rwh) */
+ unsigned int Res:1; /**< \brief [7:7] Reserved in this product (r) */
+ unsigned int CPU1DTEN:1; /**< \brief [8:8] CPU1 TC1.6P DTAG MBIST Controller Memory Enable (rwh) */
+ unsigned int CPU1PSEN:1; /**< \brief [9:9] CPU1 TC1.6P PSPR MBIST Controller Memory Enable (rwh) */
+ unsigned int reserved_10:1; /**< \brief \internal Reserved */
+ unsigned int CPU1PTEN:1; /**< \brief [11:11] CPU1 TC1.6P PTAG MBIST Controller Memory Enable (rwh) */
+ unsigned int LMUEN:1; /**< \brief [12:12] Reserved in this product (r) */
+ unsigned int MMCDSEN:1; /**< \brief [13:13] Reserved in this product (r) */
+ unsigned int CPU0DSEN:1; /**< \brief [14:14] CPU0 DSPR MBIST Controller Memory Enable (rwh) */
+ unsigned int reserved_15:1; /**< \brief \internal Reserved */
+ unsigned int CPU0PSEN:1; /**< \brief [16:16] CPU0 PSPR MBIST Controller Memory Enable (rwh) */
+ unsigned int CPU0PTEN:1; /**< \brief [17:17] CPU0 PTAG MBIST Controller Memory Enable (rwh) */
+ unsigned int reserved_18:1; /**< \brief \internal Reserved */
+ unsigned int CPU0DTEN:1; /**< \brief [19:19] Reserved in this product (r) */
+ unsigned int CPUXDS2EN:2; /**< \brief [21:20] Reserved in this product (r) */
+ unsigned int ETHEN:1; /**< \brief [22:22] ETHERMAC MBIST Controller Memory Enable (rwh) */
+ unsigned int reserved_23:3; /**< \brief \internal Reserved */
+ unsigned int FSI0EN:1; /**< \brief [26:26] FSI0 MBIST Controller Memory Enable (rwh) */
+ unsigned int CPU0DS2EN:1; /**< \brief [27:27] Reserved in this product (r) */
+ unsigned int GTMFEN:1; /**< \brief [28:28] GTM FIFO0 MBIST Controller Memory Enable (rwh) */
+ unsigned int GTMM0EN:1; /**< \brief [29:29] GTM MCS0 MBIST Controller Memory Enable (rwh) */
+ unsigned int GTMM1EN:1; /**< \brief [30:30] GTM RAM1 MBIST Controller Memory Enable (rwh) */
+ unsigned int GTM1AEN:1; /**< \brief [31:31] GTM RAM1A MBIST Controller Memory Enable (rwh) */
+} Ifx_MTU_MEMTEST0_Bits;
+
+/** \brief Memory MBISTEnable Register 1 */
+typedef struct _Ifx_MTU_MEMTEST1_Bits
+{
+ unsigned int GTM1BEN:1; /**< \brief [0:0] GTM RAM1B Controller Memory Enable (rwh) */
+ unsigned int GTM2EN:1; /**< \brief [1:1] GTM RAM2 Controller Memory Enable (rwh) */
+ unsigned int PSI5EN:1; /**< \brief [2:2] PSI5 Controller Memory Enable (rwh) */
+ unsigned int reserved_3:1; /**< \brief \internal Reserved */
+ unsigned int MCAN0EN:1; /**< \brief [4:4] MultiCAN0 Controller Memory Enable (rwh) */
+ unsigned int MCAN1EN:1; /**< \brief [5:5] Reserved in this product (r) */
+ unsigned int ERAY0OEN:1; /**< \brief [6:6] ERAY0 OBF Controller Memory Enable (rwh) */
+ unsigned int ERAY0TEN:1; /**< \brief [7:7] ERAY0 TBF Controller Memory Enable (rwh) */
+ unsigned int ERAY0MEN:1; /**< \brief [8:8] ERAY0 MBF Controller Memory Enable (rwh) */
+ unsigned int ERAY1XEN:3; /**< \brief [11:9] Reserved in this product (r) */
+ unsigned int STBY1EN:1; /**< \brief [12:12] 8 Bit Standby RAM Controller Memory 1 Enable (rwh) */
+ unsigned int MCDSEN:1; /**< \brief [13:13] MCDS Controller Memory Enable (ED only) (rwh) */
+ unsigned int EMEML0EN:1; /**< \brief [14:14] EMEM Lower 0 (TCM) MBIST Controller Memory Test Enable (ED only) (rwh) */
+ unsigned int EMEML1EN:1; /**< \brief [15:15] EMEM Lower 1 (TCM) MBIST Controller Memory Test Enable (ED only) (rwh) */
+ unsigned int EMEML2EN:1; /**< \brief [16:16] EMEM Lower 2 (TCM) MBIST Controller Memory Test Enable (ED only) (rwh) */
+ unsigned int EMEML3EN:1; /**< \brief [17:17] EMEM Lower 3 (TCM) MBIST Controller Memory Test Enable (ED only) (rwh) */
+ unsigned int EMEML4EN:1; /**< \brief [18:18] EMEM Lower 4 (TCM) MBIST Controller Memory Test Enable (ED only) (rwh) */
+ unsigned int EMEML5EN:1; /**< \brief [19:19] EMEM Lower 5 (TCM) MBIST Controller Memory Test Enable (ED only) (rwh) */
+ unsigned int EMEML6EN:1; /**< \brief [20:20] EMEM Lower 6 (TCM) MBIST Controller Memory Test Enable (ED only) (rwh) */
+ unsigned int EMEML7EN:1; /**< \brief [21:21] EMEM Lower 7 (TCM) MBIST Controller Memory Test Enable (ED only) (rwh) */
+ unsigned int EMEMLXEN:8; /**< \brief [29:22] Reserved in this product (r) */
+ unsigned int EMEMUXEN:2; /**< \brief [31:30] Reserved in this product (r) */
+} Ifx_MTU_MEMTEST1_Bits;
+
+/** \brief Memory MBISTEnable Register 2 */
+typedef struct _Ifx_MTU_MEMTEST2_Bits
+{
+ unsigned int EMEMUxEN:14; /**< \brief [13:0] Reserved in this product (r) */
+ unsigned int CIF0EN:1; /**< \brief [14:14] CIF JPEG1_4 Memory Enable (ED only) (rwh) */
+ unsigned int DAMEN:1; /**< \brief [15:15] Reserved in this product (r) */
+ unsigned int CIF1EN:1; /**< \brief [16:16] CIF JPEG3 Memory Enable (ADAS Product only) (rwh) */
+ unsigned int CIF2EN:1; /**< \brief [17:17] CIF Memory2 Enable (ADAS Product only) (rwh) */
+ unsigned int STBY2EN:1; /**< \brief [18:18] 8-bit Standby Controller Memory2 Enable (rwh) */
+ unsigned int DMAEN:1; /**< \brief [19:19] DMA MBIST Controller Memory Enable (rwh) */
+ unsigned int XTM0EN:1; /**< \brief [20:20] EMEM XTM0 Controller Memory Enable (ED only) (rwh) */
+ unsigned int XTM1EN:1; /**< \brief [21:21] EMEM XTM1 Controller Memory Enable (ED only) (rwh) */
+ unsigned int FFT0EN:1; /**< \brief [22:22] FFT0 Memory Controller Memory Enable (ADAS Product only) (rwh) */
+ unsigned int FFT1EN:1; /**< \brief [23:23] FFT1 Memory Controller Memory Enable (ADAS Product only) (rwh) */
+ unsigned int reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_MTU_MEMTEST2_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mtu_union
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MTU_ACCEN0_Bits B; /**< \brief Bitfield access */
+} Ifx_MTU_ACCEN0;
+
+/** \brief Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MTU_ACCEN1_Bits B; /**< \brief Bitfield access */
+} Ifx_MTU_ACCEN1;
+
+/** \brief Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MTU_CLC_Bits B; /**< \brief Bitfield access */
+} Ifx_MTU_CLC;
+
+/** \brief Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MTU_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_MTU_ID;
+
+/** \brief Memory Mapping Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MTU_MEMMAP_Bits B; /**< \brief Bitfield access */
+} Ifx_MTU_MEMMAP;
+
+/** \brief Memory Status Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MTU_MEMSTAT0_Bits B; /**< \brief Bitfield access */
+} Ifx_MTU_MEMSTAT0;
+
+/** \brief Memory Status Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MTU_MEMSTAT1_Bits B; /**< \brief Bitfield access */
+} Ifx_MTU_MEMSTAT1;
+
+/** \brief Memory Status Register 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MTU_MEMSTAT2_Bits B; /**< \brief Bitfield access */
+} Ifx_MTU_MEMSTAT2;
+
+/** \brief Memory MBISTEnable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MTU_MEMTEST0_Bits B; /**< \brief Bitfield access */
+} Ifx_MTU_MEMTEST0;
+
+/** \brief Memory MBISTEnable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MTU_MEMTEST1_Bits B; /**< \brief Bitfield access */
+} Ifx_MTU_MEMTEST1;
+
+/** \brief Memory MBISTEnable Register 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_MTU_MEMTEST2_Bits B; /**< \brief Bitfield access */
+} Ifx_MTU_MEMTEST2;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Mtu_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief MTU object */
+typedef volatile struct _Ifx_MTU
+{
+ Ifx_MTU_CLC CLC; /**< \brief 0, Identification Register */
+ unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
+ Ifx_MTU_ID ID; /**< \brief 8, Identification Register */
+ unsigned char reserved_C[4]; /**< \brief C, \internal Reserved */
+ Ifx_MTU_MEMTEST0 MEMTEST0; /**< \brief 10, Memory MBISTEnable Register 0 */
+ Ifx_MTU_MEMTEST1 MEMTEST1; /**< \brief 14, Memory MBISTEnable Register 1 */
+ Ifx_MTU_MEMTEST2 MEMTEST2; /**< \brief 18, Memory MBISTEnable Register 2 */
+ Ifx_MTU_MEMMAP MEMMAP; /**< \brief 1C, Memory Mapping Enable Register */
+ unsigned char reserved_20[24]; /**< \brief 20, \internal Reserved */
+ Ifx_MTU_MEMSTAT0 MEMSTAT0; /**< \brief 38, Memory Status Register 0 */
+ Ifx_MTU_MEMSTAT1 MEMSTAT1; /**< \brief 3C, Memory Status Register 1 */
+ Ifx_MTU_MEMSTAT2 MEMSTAT2; /**< \brief 40, Memory Status Register 2 */
+ unsigned char reserved_44[180]; /**< \brief 44, \internal Reserved */
+ Ifx_MTU_ACCEN1 ACCEN1; /**< \brief F8, Access Enable Register 1 */
+ Ifx_MTU_ACCEN0 ACCEN0; /**< \brief FC, Access Enable Register 0 */
+ unsigned char reserved_100[1]; /**< \brief 100, \internal Reserved */
+} Ifx_MTU;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXMTU_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxOvc_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxOvc_bf.h
new file mode 100644
index 0000000..12886d6
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxOvc_bf.h
@@ -0,0 +1,378 @@
+/**
+ * \file IfxOvc_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Ovc_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Ovc
+ *
+ */
+#ifndef IFXOVC_BF_H
+#define IFXOVC_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Ovc_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_OVC_BLK_OMASK_Bits.OMASK */
+#define IFX_OVC_BLK_OMASK_OMASK_LEN (12u)
+
+/** \brief Mask for Ifx_OVC_BLK_OMASK_Bits.OMASK */
+#define IFX_OVC_BLK_OMASK_OMASK_MSK (0xfffu)
+
+/** \brief Offset for Ifx_OVC_BLK_OMASK_Bits.OMASK */
+#define IFX_OVC_BLK_OMASK_OMASK_OFF (5u)
+
+/** \brief Length for Ifx_OVC_BLK_OMASK_Bits.ONE */
+#define IFX_OVC_BLK_OMASK_ONE_LEN (11u)
+
+/** \brief Mask for Ifx_OVC_BLK_OMASK_Bits.ONE */
+#define IFX_OVC_BLK_OMASK_ONE_MSK (0x7ffu)
+
+/** \brief Offset for Ifx_OVC_BLK_OMASK_Bits.ONE */
+#define IFX_OVC_BLK_OMASK_ONE_OFF (17u)
+
+/** \brief Length for Ifx_OVC_BLK_OTAR_Bits.TBASE */
+#define IFX_OVC_BLK_OTAR_TBASE_LEN (23u)
+
+/** \brief Mask for Ifx_OVC_BLK_OTAR_Bits.TBASE */
+#define IFX_OVC_BLK_OTAR_TBASE_MSK (0x7fffffu)
+
+/** \brief Offset for Ifx_OVC_BLK_OTAR_Bits.TBASE */
+#define IFX_OVC_BLK_OTAR_TBASE_OFF (5u)
+
+/** \brief Length for Ifx_OVC_BLK_RABR_Bits.OBASE */
+#define IFX_OVC_BLK_RABR_OBASE_LEN (17u)
+
+/** \brief Mask for Ifx_OVC_BLK_RABR_Bits.OBASE */
+#define IFX_OVC_BLK_RABR_OBASE_MSK (0x1ffffu)
+
+/** \brief Offset for Ifx_OVC_BLK_RABR_Bits.OBASE */
+#define IFX_OVC_BLK_RABR_OBASE_OFF (5u)
+
+/** \brief Length for Ifx_OVC_BLK_RABR_Bits.OMEM */
+#define IFX_OVC_BLK_RABR_OMEM_LEN (3u)
+
+/** \brief Mask for Ifx_OVC_BLK_RABR_Bits.OMEM */
+#define IFX_OVC_BLK_RABR_OMEM_MSK (0x7u)
+
+/** \brief Offset for Ifx_OVC_BLK_RABR_Bits.OMEM */
+#define IFX_OVC_BLK_RABR_OMEM_OFF (24u)
+
+/** \brief Length for Ifx_OVC_BLK_RABR_Bits.OVEN */
+#define IFX_OVC_BLK_RABR_OVEN_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_BLK_RABR_Bits.OVEN */
+#define IFX_OVC_BLK_RABR_OVEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_BLK_RABR_Bits.OVEN */
+#define IFX_OVC_BLK_RABR_OVEN_OFF (31u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN0 */
+#define IFX_OVC_OSEL_SHOVEN0_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN0 */
+#define IFX_OVC_OSEL_SHOVEN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN0 */
+#define IFX_OVC_OSEL_SHOVEN0_OFF (0u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN10 */
+#define IFX_OVC_OSEL_SHOVEN10_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN10 */
+#define IFX_OVC_OSEL_SHOVEN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN10 */
+#define IFX_OVC_OSEL_SHOVEN10_OFF (10u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN11 */
+#define IFX_OVC_OSEL_SHOVEN11_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN11 */
+#define IFX_OVC_OSEL_SHOVEN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN11 */
+#define IFX_OVC_OSEL_SHOVEN11_OFF (11u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN12 */
+#define IFX_OVC_OSEL_SHOVEN12_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN12 */
+#define IFX_OVC_OSEL_SHOVEN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN12 */
+#define IFX_OVC_OSEL_SHOVEN12_OFF (12u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN13 */
+#define IFX_OVC_OSEL_SHOVEN13_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN13 */
+#define IFX_OVC_OSEL_SHOVEN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN13 */
+#define IFX_OVC_OSEL_SHOVEN13_OFF (13u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN14 */
+#define IFX_OVC_OSEL_SHOVEN14_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN14 */
+#define IFX_OVC_OSEL_SHOVEN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN14 */
+#define IFX_OVC_OSEL_SHOVEN14_OFF (14u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN15 */
+#define IFX_OVC_OSEL_SHOVEN15_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN15 */
+#define IFX_OVC_OSEL_SHOVEN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN15 */
+#define IFX_OVC_OSEL_SHOVEN15_OFF (15u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN16 */
+#define IFX_OVC_OSEL_SHOVEN16_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN16 */
+#define IFX_OVC_OSEL_SHOVEN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN16 */
+#define IFX_OVC_OSEL_SHOVEN16_OFF (16u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN17 */
+#define IFX_OVC_OSEL_SHOVEN17_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN17 */
+#define IFX_OVC_OSEL_SHOVEN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN17 */
+#define IFX_OVC_OSEL_SHOVEN17_OFF (17u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN18 */
+#define IFX_OVC_OSEL_SHOVEN18_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN18 */
+#define IFX_OVC_OSEL_SHOVEN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN18 */
+#define IFX_OVC_OSEL_SHOVEN18_OFF (18u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN19 */
+#define IFX_OVC_OSEL_SHOVEN19_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN19 */
+#define IFX_OVC_OSEL_SHOVEN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN19 */
+#define IFX_OVC_OSEL_SHOVEN19_OFF (19u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN1 */
+#define IFX_OVC_OSEL_SHOVEN1_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN1 */
+#define IFX_OVC_OSEL_SHOVEN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN1 */
+#define IFX_OVC_OSEL_SHOVEN1_OFF (1u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN20 */
+#define IFX_OVC_OSEL_SHOVEN20_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN20 */
+#define IFX_OVC_OSEL_SHOVEN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN20 */
+#define IFX_OVC_OSEL_SHOVEN20_OFF (20u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN21 */
+#define IFX_OVC_OSEL_SHOVEN21_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN21 */
+#define IFX_OVC_OSEL_SHOVEN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN21 */
+#define IFX_OVC_OSEL_SHOVEN21_OFF (21u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN22 */
+#define IFX_OVC_OSEL_SHOVEN22_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN22 */
+#define IFX_OVC_OSEL_SHOVEN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN22 */
+#define IFX_OVC_OSEL_SHOVEN22_OFF (22u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN23 */
+#define IFX_OVC_OSEL_SHOVEN23_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN23 */
+#define IFX_OVC_OSEL_SHOVEN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN23 */
+#define IFX_OVC_OSEL_SHOVEN23_OFF (23u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN24 */
+#define IFX_OVC_OSEL_SHOVEN24_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN24 */
+#define IFX_OVC_OSEL_SHOVEN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN24 */
+#define IFX_OVC_OSEL_SHOVEN24_OFF (24u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN25 */
+#define IFX_OVC_OSEL_SHOVEN25_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN25 */
+#define IFX_OVC_OSEL_SHOVEN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN25 */
+#define IFX_OVC_OSEL_SHOVEN25_OFF (25u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN26 */
+#define IFX_OVC_OSEL_SHOVEN26_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN26 */
+#define IFX_OVC_OSEL_SHOVEN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN26 */
+#define IFX_OVC_OSEL_SHOVEN26_OFF (26u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN27 */
+#define IFX_OVC_OSEL_SHOVEN27_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN27 */
+#define IFX_OVC_OSEL_SHOVEN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN27 */
+#define IFX_OVC_OSEL_SHOVEN27_OFF (27u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN28 */
+#define IFX_OVC_OSEL_SHOVEN28_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN28 */
+#define IFX_OVC_OSEL_SHOVEN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN28 */
+#define IFX_OVC_OSEL_SHOVEN28_OFF (28u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN29 */
+#define IFX_OVC_OSEL_SHOVEN29_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN29 */
+#define IFX_OVC_OSEL_SHOVEN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN29 */
+#define IFX_OVC_OSEL_SHOVEN29_OFF (29u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN2 */
+#define IFX_OVC_OSEL_SHOVEN2_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN2 */
+#define IFX_OVC_OSEL_SHOVEN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN2 */
+#define IFX_OVC_OSEL_SHOVEN2_OFF (2u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN30 */
+#define IFX_OVC_OSEL_SHOVEN30_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN30 */
+#define IFX_OVC_OSEL_SHOVEN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN30 */
+#define IFX_OVC_OSEL_SHOVEN30_OFF (30u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN31 */
+#define IFX_OVC_OSEL_SHOVEN31_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN31 */
+#define IFX_OVC_OSEL_SHOVEN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN31 */
+#define IFX_OVC_OSEL_SHOVEN31_OFF (31u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN3 */
+#define IFX_OVC_OSEL_SHOVEN3_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN3 */
+#define IFX_OVC_OSEL_SHOVEN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN3 */
+#define IFX_OVC_OSEL_SHOVEN3_OFF (3u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN4 */
+#define IFX_OVC_OSEL_SHOVEN4_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN4 */
+#define IFX_OVC_OSEL_SHOVEN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN4 */
+#define IFX_OVC_OSEL_SHOVEN4_OFF (4u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN5 */
+#define IFX_OVC_OSEL_SHOVEN5_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN5 */
+#define IFX_OVC_OSEL_SHOVEN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN5 */
+#define IFX_OVC_OSEL_SHOVEN5_OFF (5u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN6 */
+#define IFX_OVC_OSEL_SHOVEN6_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN6 */
+#define IFX_OVC_OSEL_SHOVEN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN6 */
+#define IFX_OVC_OSEL_SHOVEN6_OFF (6u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN7 */
+#define IFX_OVC_OSEL_SHOVEN7_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN7 */
+#define IFX_OVC_OSEL_SHOVEN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN7 */
+#define IFX_OVC_OSEL_SHOVEN7_OFF (7u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN8 */
+#define IFX_OVC_OSEL_SHOVEN8_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN8 */
+#define IFX_OVC_OSEL_SHOVEN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN8 */
+#define IFX_OVC_OSEL_SHOVEN8_OFF (8u)
+
+/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN9 */
+#define IFX_OVC_OSEL_SHOVEN9_LEN (1u)
+
+/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN9 */
+#define IFX_OVC_OSEL_SHOVEN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN9 */
+#define IFX_OVC_OSEL_SHOVEN9_OFF (9u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXOVC_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxOvc_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxOvc_reg.h
new file mode 100644
index 0000000..979dd72
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxOvc_reg.h
@@ -0,0 +1,1604 @@
+/**
+ * \file IfxOvc_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Ovc_Cfg Ovc address
+ * \ingroup IfxLld_Ovc
+ *
+ * \defgroup IfxLld_Ovc_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Ovc_Cfg
+ *
+ * \defgroup IfxLld_Ovc_Cfg_Ovc0 2-OVC0
+ * \ingroup IfxLld_Ovc_Cfg
+ *
+ * \defgroup IfxLld_Ovc_Cfg_Ovc1 2-OVC1
+ * \ingroup IfxLld_Ovc_Cfg
+ *
+ */
+#ifndef IFXOVC_REG_H
+#define IFXOVC_REG_H 1
+/******************************************************************************/
+#include "IfxOvc_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Ovc_Cfg_BaseAddress
+ * \{ */
+
+/** \brief OVC object */
+#define MODULE_OVC0 /*lint --e(923)*/ (*(Ifx_OVC*)0xF880FB00u)
+
+/** \brief OVC object */
+#define MODULE_OVC1 /*lint --e(923)*/ (*(Ifx_OVC*)0xF882FB00u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Ovc_Cfg_Ovc0
+ * \{ */
+
+/** \brief 18, Overlay Mask Register */
+#define OVC0_BLK0_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FB18u)
+
+/** Alias (User Manual Name) for OVC0_BLK0_OMASK.
+* To use register names with standard convension, please use OVC0_BLK0_OMASK.
+*/
+#define OVC0_OMASK0 (OVC0_BLK0_OMASK)
+
+/** \brief 14, Overlay Target Address Register */
+#define OVC0_BLK0_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FB14u)
+
+/** Alias (User Manual Name) for OVC0_BLK0_OTAR.
+* To use register names with standard convension, please use OVC0_BLK0_OTAR.
+*/
+#define OVC0_OTAR0 (OVC0_BLK0_OTAR)
+
+/** \brief 10, Redirected Address Base Register */
+#define OVC0_BLK0_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FB10u)
+
+/** Alias (User Manual Name) for OVC0_BLK0_RABR.
+* To use register names with standard convension, please use OVC0_BLK0_RABR.
+*/
+#define OVC0_RABR0 (OVC0_BLK0_RABR)
+
+/** \brief 90, Overlay Mask Register */
+#define OVC0_BLK10_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FB90u)
+
+/** Alias (User Manual Name) for OVC0_BLK10_OMASK.
+* To use register names with standard convension, please use OVC0_BLK10_OMASK.
+*/
+#define OVC0_OMASK10 (OVC0_BLK10_OMASK)
+
+/** \brief 8C, Overlay Target Address Register */
+#define OVC0_BLK10_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FB8Cu)
+
+/** Alias (User Manual Name) for OVC0_BLK10_OTAR.
+* To use register names with standard convension, please use OVC0_BLK10_OTAR.
+*/
+#define OVC0_OTAR10 (OVC0_BLK10_OTAR)
+
+/** \brief 88, Redirected Address Base Register */
+#define OVC0_BLK10_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FB88u)
+
+/** Alias (User Manual Name) for OVC0_BLK10_RABR.
+* To use register names with standard convension, please use OVC0_BLK10_RABR.
+*/
+#define OVC0_RABR10 (OVC0_BLK10_RABR)
+
+/** \brief 9C, Overlay Mask Register */
+#define OVC0_BLK11_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FB9Cu)
+
+/** Alias (User Manual Name) for OVC0_BLK11_OMASK.
+* To use register names with standard convension, please use OVC0_BLK11_OMASK.
+*/
+#define OVC0_OMASK11 (OVC0_BLK11_OMASK)
+
+/** \brief 98, Overlay Target Address Register */
+#define OVC0_BLK11_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FB98u)
+
+/** Alias (User Manual Name) for OVC0_BLK11_OTAR.
+* To use register names with standard convension, please use OVC0_BLK11_OTAR.
+*/
+#define OVC0_OTAR11 (OVC0_BLK11_OTAR)
+
+/** \brief 94, Redirected Address Base Register */
+#define OVC0_BLK11_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FB94u)
+
+/** Alias (User Manual Name) for OVC0_BLK11_RABR.
+* To use register names with standard convension, please use OVC0_BLK11_RABR.
+*/
+#define OVC0_RABR11 (OVC0_BLK11_RABR)
+
+/** \brief A8, Overlay Mask Register */
+#define OVC0_BLK12_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FBA8u)
+
+/** Alias (User Manual Name) for OVC0_BLK12_OMASK.
+* To use register names with standard convension, please use OVC0_BLK12_OMASK.
+*/
+#define OVC0_OMASK12 (OVC0_BLK12_OMASK)
+
+/** \brief A4, Overlay Target Address Register */
+#define OVC0_BLK12_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FBA4u)
+
+/** Alias (User Manual Name) for OVC0_BLK12_OTAR.
+* To use register names with standard convension, please use OVC0_BLK12_OTAR.
+*/
+#define OVC0_OTAR12 (OVC0_BLK12_OTAR)
+
+/** \brief A0, Redirected Address Base Register */
+#define OVC0_BLK12_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FBA0u)
+
+/** Alias (User Manual Name) for OVC0_BLK12_RABR.
+* To use register names with standard convension, please use OVC0_BLK12_RABR.
+*/
+#define OVC0_RABR12 (OVC0_BLK12_RABR)
+
+/** \brief B4, Overlay Mask Register */
+#define OVC0_BLK13_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FBB4u)
+
+/** Alias (User Manual Name) for OVC0_BLK13_OMASK.
+* To use register names with standard convension, please use OVC0_BLK13_OMASK.
+*/
+#define OVC0_OMASK13 (OVC0_BLK13_OMASK)
+
+/** \brief B0, Overlay Target Address Register */
+#define OVC0_BLK13_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FBB0u)
+
+/** Alias (User Manual Name) for OVC0_BLK13_OTAR.
+* To use register names with standard convension, please use OVC0_BLK13_OTAR.
+*/
+#define OVC0_OTAR13 (OVC0_BLK13_OTAR)
+
+/** \brief AC, Redirected Address Base Register */
+#define OVC0_BLK13_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FBACu)
+
+/** Alias (User Manual Name) for OVC0_BLK13_RABR.
+* To use register names with standard convension, please use OVC0_BLK13_RABR.
+*/
+#define OVC0_RABR13 (OVC0_BLK13_RABR)
+
+/** \brief C0, Overlay Mask Register */
+#define OVC0_BLK14_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FBC0u)
+
+/** Alias (User Manual Name) for OVC0_BLK14_OMASK.
+* To use register names with standard convension, please use OVC0_BLK14_OMASK.
+*/
+#define OVC0_OMASK14 (OVC0_BLK14_OMASK)
+
+/** \brief BC, Overlay Target Address Register */
+#define OVC0_BLK14_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FBBCu)
+
+/** Alias (User Manual Name) for OVC0_BLK14_OTAR.
+* To use register names with standard convension, please use OVC0_BLK14_OTAR.
+*/
+#define OVC0_OTAR14 (OVC0_BLK14_OTAR)
+
+/** \brief B8, Redirected Address Base Register */
+#define OVC0_BLK14_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FBB8u)
+
+/** Alias (User Manual Name) for OVC0_BLK14_RABR.
+* To use register names with standard convension, please use OVC0_BLK14_RABR.
+*/
+#define OVC0_RABR14 (OVC0_BLK14_RABR)
+
+/** \brief CC, Overlay Mask Register */
+#define OVC0_BLK15_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FBCCu)
+
+/** Alias (User Manual Name) for OVC0_BLK15_OMASK.
+* To use register names with standard convension, please use OVC0_BLK15_OMASK.
+*/
+#define OVC0_OMASK15 (OVC0_BLK15_OMASK)
+
+/** \brief C8, Overlay Target Address Register */
+#define OVC0_BLK15_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FBC8u)
+
+/** Alias (User Manual Name) for OVC0_BLK15_OTAR.
+* To use register names with standard convension, please use OVC0_BLK15_OTAR.
+*/
+#define OVC0_OTAR15 (OVC0_BLK15_OTAR)
+
+/** \brief C4, Redirected Address Base Register */
+#define OVC0_BLK15_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FBC4u)
+
+/** Alias (User Manual Name) for OVC0_BLK15_RABR.
+* To use register names with standard convension, please use OVC0_BLK15_RABR.
+*/
+#define OVC0_RABR15 (OVC0_BLK15_RABR)
+
+/** \brief D8, Overlay Mask Register */
+#define OVC0_BLK16_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FBD8u)
+
+/** Alias (User Manual Name) for OVC0_BLK16_OMASK.
+* To use register names with standard convension, please use OVC0_BLK16_OMASK.
+*/
+#define OVC0_OMASK16 (OVC0_BLK16_OMASK)
+
+/** \brief D4, Overlay Target Address Register */
+#define OVC0_BLK16_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FBD4u)
+
+/** Alias (User Manual Name) for OVC0_BLK16_OTAR.
+* To use register names with standard convension, please use OVC0_BLK16_OTAR.
+*/
+#define OVC0_OTAR16 (OVC0_BLK16_OTAR)
+
+/** \brief D0, Redirected Address Base Register */
+#define OVC0_BLK16_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FBD0u)
+
+/** Alias (User Manual Name) for OVC0_BLK16_RABR.
+* To use register names with standard convension, please use OVC0_BLK16_RABR.
+*/
+#define OVC0_RABR16 (OVC0_BLK16_RABR)
+
+/** \brief E4, Overlay Mask Register */
+#define OVC0_BLK17_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FBE4u)
+
+/** Alias (User Manual Name) for OVC0_BLK17_OMASK.
+* To use register names with standard convension, please use OVC0_BLK17_OMASK.
+*/
+#define OVC0_OMASK17 (OVC0_BLK17_OMASK)
+
+/** \brief E0, Overlay Target Address Register */
+#define OVC0_BLK17_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FBE0u)
+
+/** Alias (User Manual Name) for OVC0_BLK17_OTAR.
+* To use register names with standard convension, please use OVC0_BLK17_OTAR.
+*/
+#define OVC0_OTAR17 (OVC0_BLK17_OTAR)
+
+/** \brief DC, Redirected Address Base Register */
+#define OVC0_BLK17_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FBDCu)
+
+/** Alias (User Manual Name) for OVC0_BLK17_RABR.
+* To use register names with standard convension, please use OVC0_BLK17_RABR.
+*/
+#define OVC0_RABR17 (OVC0_BLK17_RABR)
+
+/** \brief F0, Overlay Mask Register */
+#define OVC0_BLK18_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FBF0u)
+
+/** Alias (User Manual Name) for OVC0_BLK18_OMASK.
+* To use register names with standard convension, please use OVC0_BLK18_OMASK.
+*/
+#define OVC0_OMASK18 (OVC0_BLK18_OMASK)
+
+/** \brief EC, Overlay Target Address Register */
+#define OVC0_BLK18_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FBECu)
+
+/** Alias (User Manual Name) for OVC0_BLK18_OTAR.
+* To use register names with standard convension, please use OVC0_BLK18_OTAR.
+*/
+#define OVC0_OTAR18 (OVC0_BLK18_OTAR)
+
+/** \brief E8, Redirected Address Base Register */
+#define OVC0_BLK18_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FBE8u)
+
+/** Alias (User Manual Name) for OVC0_BLK18_RABR.
+* To use register names with standard convension, please use OVC0_BLK18_RABR.
+*/
+#define OVC0_RABR18 (OVC0_BLK18_RABR)
+
+/** \brief FC, Overlay Mask Register */
+#define OVC0_BLK19_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FBFCu)
+
+/** Alias (User Manual Name) for OVC0_BLK19_OMASK.
+* To use register names with standard convension, please use OVC0_BLK19_OMASK.
+*/
+#define OVC0_OMASK19 (OVC0_BLK19_OMASK)
+
+/** \brief F8, Overlay Target Address Register */
+#define OVC0_BLK19_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FBF8u)
+
+/** Alias (User Manual Name) for OVC0_BLK19_OTAR.
+* To use register names with standard convension, please use OVC0_BLK19_OTAR.
+*/
+#define OVC0_OTAR19 (OVC0_BLK19_OTAR)
+
+/** \brief F4, Redirected Address Base Register */
+#define OVC0_BLK19_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FBF4u)
+
+/** Alias (User Manual Name) for OVC0_BLK19_RABR.
+* To use register names with standard convension, please use OVC0_BLK19_RABR.
+*/
+#define OVC0_RABR19 (OVC0_BLK19_RABR)
+
+/** \brief 24, Overlay Mask Register */
+#define OVC0_BLK1_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FB24u)
+
+/** Alias (User Manual Name) for OVC0_BLK1_OMASK.
+* To use register names with standard convension, please use OVC0_BLK1_OMASK.
+*/
+#define OVC0_OMASK1 (OVC0_BLK1_OMASK)
+
+/** \brief 20, Overlay Target Address Register */
+#define OVC0_BLK1_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FB20u)
+
+/** Alias (User Manual Name) for OVC0_BLK1_OTAR.
+* To use register names with standard convension, please use OVC0_BLK1_OTAR.
+*/
+#define OVC0_OTAR1 (OVC0_BLK1_OTAR)
+
+/** \brief 1C, Redirected Address Base Register */
+#define OVC0_BLK1_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FB1Cu)
+
+/** Alias (User Manual Name) for OVC0_BLK1_RABR.
+* To use register names with standard convension, please use OVC0_BLK1_RABR.
+*/
+#define OVC0_RABR1 (OVC0_BLK1_RABR)
+
+/** \brief 108, Overlay Mask Register */
+#define OVC0_BLK20_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FC08u)
+
+/** Alias (User Manual Name) for OVC0_BLK20_OMASK.
+* To use register names with standard convension, please use OVC0_BLK20_OMASK.
+*/
+#define OVC0_OMASK20 (OVC0_BLK20_OMASK)
+
+/** \brief 104, Overlay Target Address Register */
+#define OVC0_BLK20_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FC04u)
+
+/** Alias (User Manual Name) for OVC0_BLK20_OTAR.
+* To use register names with standard convension, please use OVC0_BLK20_OTAR.
+*/
+#define OVC0_OTAR20 (OVC0_BLK20_OTAR)
+
+/** \brief 100, Redirected Address Base Register */
+#define OVC0_BLK20_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FC00u)
+
+/** Alias (User Manual Name) for OVC0_BLK20_RABR.
+* To use register names with standard convension, please use OVC0_BLK20_RABR.
+*/
+#define OVC0_RABR20 (OVC0_BLK20_RABR)
+
+/** \brief 114, Overlay Mask Register */
+#define OVC0_BLK21_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FC14u)
+
+/** Alias (User Manual Name) for OVC0_BLK21_OMASK.
+* To use register names with standard convension, please use OVC0_BLK21_OMASK.
+*/
+#define OVC0_OMASK21 (OVC0_BLK21_OMASK)
+
+/** \brief 110, Overlay Target Address Register */
+#define OVC0_BLK21_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FC10u)
+
+/** Alias (User Manual Name) for OVC0_BLK21_OTAR.
+* To use register names with standard convension, please use OVC0_BLK21_OTAR.
+*/
+#define OVC0_OTAR21 (OVC0_BLK21_OTAR)
+
+/** \brief 10C, Redirected Address Base Register */
+#define OVC0_BLK21_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FC0Cu)
+
+/** Alias (User Manual Name) for OVC0_BLK21_RABR.
+* To use register names with standard convension, please use OVC0_BLK21_RABR.
+*/
+#define OVC0_RABR21 (OVC0_BLK21_RABR)
+
+/** \brief 120, Overlay Mask Register */
+#define OVC0_BLK22_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FC20u)
+
+/** Alias (User Manual Name) for OVC0_BLK22_OMASK.
+* To use register names with standard convension, please use OVC0_BLK22_OMASK.
+*/
+#define OVC0_OMASK22 (OVC0_BLK22_OMASK)
+
+/** \brief 11C, Overlay Target Address Register */
+#define OVC0_BLK22_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FC1Cu)
+
+/** Alias (User Manual Name) for OVC0_BLK22_OTAR.
+* To use register names with standard convension, please use OVC0_BLK22_OTAR.
+*/
+#define OVC0_OTAR22 (OVC0_BLK22_OTAR)
+
+/** \brief 118, Redirected Address Base Register */
+#define OVC0_BLK22_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FC18u)
+
+/** Alias (User Manual Name) for OVC0_BLK22_RABR.
+* To use register names with standard convension, please use OVC0_BLK22_RABR.
+*/
+#define OVC0_RABR22 (OVC0_BLK22_RABR)
+
+/** \brief 12C, Overlay Mask Register */
+#define OVC0_BLK23_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FC2Cu)
+
+/** Alias (User Manual Name) for OVC0_BLK23_OMASK.
+* To use register names with standard convension, please use OVC0_BLK23_OMASK.
+*/
+#define OVC0_OMASK23 (OVC0_BLK23_OMASK)
+
+/** \brief 128, Overlay Target Address Register */
+#define OVC0_BLK23_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FC28u)
+
+/** Alias (User Manual Name) for OVC0_BLK23_OTAR.
+* To use register names with standard convension, please use OVC0_BLK23_OTAR.
+*/
+#define OVC0_OTAR23 (OVC0_BLK23_OTAR)
+
+/** \brief 124, Redirected Address Base Register */
+#define OVC0_BLK23_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FC24u)
+
+/** Alias (User Manual Name) for OVC0_BLK23_RABR.
+* To use register names with standard convension, please use OVC0_BLK23_RABR.
+*/
+#define OVC0_RABR23 (OVC0_BLK23_RABR)
+
+/** \brief 138, Overlay Mask Register */
+#define OVC0_BLK24_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FC38u)
+
+/** Alias (User Manual Name) for OVC0_BLK24_OMASK.
+* To use register names with standard convension, please use OVC0_BLK24_OMASK.
+*/
+#define OVC0_OMASK24 (OVC0_BLK24_OMASK)
+
+/** \brief 134, Overlay Target Address Register */
+#define OVC0_BLK24_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FC34u)
+
+/** Alias (User Manual Name) for OVC0_BLK24_OTAR.
+* To use register names with standard convension, please use OVC0_BLK24_OTAR.
+*/
+#define OVC0_OTAR24 (OVC0_BLK24_OTAR)
+
+/** \brief 130, Redirected Address Base Register */
+#define OVC0_BLK24_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FC30u)
+
+/** Alias (User Manual Name) for OVC0_BLK24_RABR.
+* To use register names with standard convension, please use OVC0_BLK24_RABR.
+*/
+#define OVC0_RABR24 (OVC0_BLK24_RABR)
+
+/** \brief 144, Overlay Mask Register */
+#define OVC0_BLK25_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FC44u)
+
+/** Alias (User Manual Name) for OVC0_BLK25_OMASK.
+* To use register names with standard convension, please use OVC0_BLK25_OMASK.
+*/
+#define OVC0_OMASK25 (OVC0_BLK25_OMASK)
+
+/** \brief 140, Overlay Target Address Register */
+#define OVC0_BLK25_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FC40u)
+
+/** Alias (User Manual Name) for OVC0_BLK25_OTAR.
+* To use register names with standard convension, please use OVC0_BLK25_OTAR.
+*/
+#define OVC0_OTAR25 (OVC0_BLK25_OTAR)
+
+/** \brief 13C, Redirected Address Base Register */
+#define OVC0_BLK25_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FC3Cu)
+
+/** Alias (User Manual Name) for OVC0_BLK25_RABR.
+* To use register names with standard convension, please use OVC0_BLK25_RABR.
+*/
+#define OVC0_RABR25 (OVC0_BLK25_RABR)
+
+/** \brief 150, Overlay Mask Register */
+#define OVC0_BLK26_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FC50u)
+
+/** Alias (User Manual Name) for OVC0_BLK26_OMASK.
+* To use register names with standard convension, please use OVC0_BLK26_OMASK.
+*/
+#define OVC0_OMASK26 (OVC0_BLK26_OMASK)
+
+/** \brief 14C, Overlay Target Address Register */
+#define OVC0_BLK26_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FC4Cu)
+
+/** Alias (User Manual Name) for OVC0_BLK26_OTAR.
+* To use register names with standard convension, please use OVC0_BLK26_OTAR.
+*/
+#define OVC0_OTAR26 (OVC0_BLK26_OTAR)
+
+/** \brief 148, Redirected Address Base Register */
+#define OVC0_BLK26_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FC48u)
+
+/** Alias (User Manual Name) for OVC0_BLK26_RABR.
+* To use register names with standard convension, please use OVC0_BLK26_RABR.
+*/
+#define OVC0_RABR26 (OVC0_BLK26_RABR)
+
+/** \brief 15C, Overlay Mask Register */
+#define OVC0_BLK27_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FC5Cu)
+
+/** Alias (User Manual Name) for OVC0_BLK27_OMASK.
+* To use register names with standard convension, please use OVC0_BLK27_OMASK.
+*/
+#define OVC0_OMASK27 (OVC0_BLK27_OMASK)
+
+/** \brief 158, Overlay Target Address Register */
+#define OVC0_BLK27_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FC58u)
+
+/** Alias (User Manual Name) for OVC0_BLK27_OTAR.
+* To use register names with standard convension, please use OVC0_BLK27_OTAR.
+*/
+#define OVC0_OTAR27 (OVC0_BLK27_OTAR)
+
+/** \brief 154, Redirected Address Base Register */
+#define OVC0_BLK27_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FC54u)
+
+/** Alias (User Manual Name) for OVC0_BLK27_RABR.
+* To use register names with standard convension, please use OVC0_BLK27_RABR.
+*/
+#define OVC0_RABR27 (OVC0_BLK27_RABR)
+
+/** \brief 168, Overlay Mask Register */
+#define OVC0_BLK28_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FC68u)
+
+/** Alias (User Manual Name) for OVC0_BLK28_OMASK.
+* To use register names with standard convension, please use OVC0_BLK28_OMASK.
+*/
+#define OVC0_OMASK28 (OVC0_BLK28_OMASK)
+
+/** \brief 164, Overlay Target Address Register */
+#define OVC0_BLK28_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FC64u)
+
+/** Alias (User Manual Name) for OVC0_BLK28_OTAR.
+* To use register names with standard convension, please use OVC0_BLK28_OTAR.
+*/
+#define OVC0_OTAR28 (OVC0_BLK28_OTAR)
+
+/** \brief 160, Redirected Address Base Register */
+#define OVC0_BLK28_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FC60u)
+
+/** Alias (User Manual Name) for OVC0_BLK28_RABR.
+* To use register names with standard convension, please use OVC0_BLK28_RABR.
+*/
+#define OVC0_RABR28 (OVC0_BLK28_RABR)
+
+/** \brief 174, Overlay Mask Register */
+#define OVC0_BLK29_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FC74u)
+
+/** Alias (User Manual Name) for OVC0_BLK29_OMASK.
+* To use register names with standard convension, please use OVC0_BLK29_OMASK.
+*/
+#define OVC0_OMASK29 (OVC0_BLK29_OMASK)
+
+/** \brief 170, Overlay Target Address Register */
+#define OVC0_BLK29_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FC70u)
+
+/** Alias (User Manual Name) for OVC0_BLK29_OTAR.
+* To use register names with standard convension, please use OVC0_BLK29_OTAR.
+*/
+#define OVC0_OTAR29 (OVC0_BLK29_OTAR)
+
+/** \brief 16C, Redirected Address Base Register */
+#define OVC0_BLK29_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FC6Cu)
+
+/** Alias (User Manual Name) for OVC0_BLK29_RABR.
+* To use register names with standard convension, please use OVC0_BLK29_RABR.
+*/
+#define OVC0_RABR29 (OVC0_BLK29_RABR)
+
+/** \brief 30, Overlay Mask Register */
+#define OVC0_BLK2_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FB30u)
+
+/** Alias (User Manual Name) for OVC0_BLK2_OMASK.
+* To use register names with standard convension, please use OVC0_BLK2_OMASK.
+*/
+#define OVC0_OMASK2 (OVC0_BLK2_OMASK)
+
+/** \brief 2C, Overlay Target Address Register */
+#define OVC0_BLK2_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FB2Cu)
+
+/** Alias (User Manual Name) for OVC0_BLK2_OTAR.
+* To use register names with standard convension, please use OVC0_BLK2_OTAR.
+*/
+#define OVC0_OTAR2 (OVC0_BLK2_OTAR)
+
+/** \brief 28, Redirected Address Base Register */
+#define OVC0_BLK2_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FB28u)
+
+/** Alias (User Manual Name) for OVC0_BLK2_RABR.
+* To use register names with standard convension, please use OVC0_BLK2_RABR.
+*/
+#define OVC0_RABR2 (OVC0_BLK2_RABR)
+
+/** \brief 180, Overlay Mask Register */
+#define OVC0_BLK30_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FC80u)
+
+/** Alias (User Manual Name) for OVC0_BLK30_OMASK.
+* To use register names with standard convension, please use OVC0_BLK30_OMASK.
+*/
+#define OVC0_OMASK30 (OVC0_BLK30_OMASK)
+
+/** \brief 17C, Overlay Target Address Register */
+#define OVC0_BLK30_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FC7Cu)
+
+/** Alias (User Manual Name) for OVC0_BLK30_OTAR.
+* To use register names with standard convension, please use OVC0_BLK30_OTAR.
+*/
+#define OVC0_OTAR30 (OVC0_BLK30_OTAR)
+
+/** \brief 178, Redirected Address Base Register */
+#define OVC0_BLK30_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FC78u)
+
+/** Alias (User Manual Name) for OVC0_BLK30_RABR.
+* To use register names with standard convension, please use OVC0_BLK30_RABR.
+*/
+#define OVC0_RABR30 (OVC0_BLK30_RABR)
+
+/** \brief 18C, Overlay Mask Register */
+#define OVC0_BLK31_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FC8Cu)
+
+/** Alias (User Manual Name) for OVC0_BLK31_OMASK.
+* To use register names with standard convension, please use OVC0_BLK31_OMASK.
+*/
+#define OVC0_OMASK31 (OVC0_BLK31_OMASK)
+
+/** \brief 188, Overlay Target Address Register */
+#define OVC0_BLK31_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FC88u)
+
+/** Alias (User Manual Name) for OVC0_BLK31_OTAR.
+* To use register names with standard convension, please use OVC0_BLK31_OTAR.
+*/
+#define OVC0_OTAR31 (OVC0_BLK31_OTAR)
+
+/** \brief 184, Redirected Address Base Register */
+#define OVC0_BLK31_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FC84u)
+
+/** Alias (User Manual Name) for OVC0_BLK31_RABR.
+* To use register names with standard convension, please use OVC0_BLK31_RABR.
+*/
+#define OVC0_RABR31 (OVC0_BLK31_RABR)
+
+/** \brief 3C, Overlay Mask Register */
+#define OVC0_BLK3_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FB3Cu)
+
+/** Alias (User Manual Name) for OVC0_BLK3_OMASK.
+* To use register names with standard convension, please use OVC0_BLK3_OMASK.
+*/
+#define OVC0_OMASK3 (OVC0_BLK3_OMASK)
+
+/** \brief 38, Overlay Target Address Register */
+#define OVC0_BLK3_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FB38u)
+
+/** Alias (User Manual Name) for OVC0_BLK3_OTAR.
+* To use register names with standard convension, please use OVC0_BLK3_OTAR.
+*/
+#define OVC0_OTAR3 (OVC0_BLK3_OTAR)
+
+/** \brief 34, Redirected Address Base Register */
+#define OVC0_BLK3_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FB34u)
+
+/** Alias (User Manual Name) for OVC0_BLK3_RABR.
+* To use register names with standard convension, please use OVC0_BLK3_RABR.
+*/
+#define OVC0_RABR3 (OVC0_BLK3_RABR)
+
+/** \brief 48, Overlay Mask Register */
+#define OVC0_BLK4_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FB48u)
+
+/** Alias (User Manual Name) for OVC0_BLK4_OMASK.
+* To use register names with standard convension, please use OVC0_BLK4_OMASK.
+*/
+#define OVC0_OMASK4 (OVC0_BLK4_OMASK)
+
+/** \brief 44, Overlay Target Address Register */
+#define OVC0_BLK4_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FB44u)
+
+/** Alias (User Manual Name) for OVC0_BLK4_OTAR.
+* To use register names with standard convension, please use OVC0_BLK4_OTAR.
+*/
+#define OVC0_OTAR4 (OVC0_BLK4_OTAR)
+
+/** \brief 40, Redirected Address Base Register */
+#define OVC0_BLK4_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FB40u)
+
+/** Alias (User Manual Name) for OVC0_BLK4_RABR.
+* To use register names with standard convension, please use OVC0_BLK4_RABR.
+*/
+#define OVC0_RABR4 (OVC0_BLK4_RABR)
+
+/** \brief 54, Overlay Mask Register */
+#define OVC0_BLK5_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FB54u)
+
+/** Alias (User Manual Name) for OVC0_BLK5_OMASK.
+* To use register names with standard convension, please use OVC0_BLK5_OMASK.
+*/
+#define OVC0_OMASK5 (OVC0_BLK5_OMASK)
+
+/** \brief 50, Overlay Target Address Register */
+#define OVC0_BLK5_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FB50u)
+
+/** Alias (User Manual Name) for OVC0_BLK5_OTAR.
+* To use register names with standard convension, please use OVC0_BLK5_OTAR.
+*/
+#define OVC0_OTAR5 (OVC0_BLK5_OTAR)
+
+/** \brief 4C, Redirected Address Base Register */
+#define OVC0_BLK5_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FB4Cu)
+
+/** Alias (User Manual Name) for OVC0_BLK5_RABR.
+* To use register names with standard convension, please use OVC0_BLK5_RABR.
+*/
+#define OVC0_RABR5 (OVC0_BLK5_RABR)
+
+/** \brief 60, Overlay Mask Register */
+#define OVC0_BLK6_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FB60u)
+
+/** Alias (User Manual Name) for OVC0_BLK6_OMASK.
+* To use register names with standard convension, please use OVC0_BLK6_OMASK.
+*/
+#define OVC0_OMASK6 (OVC0_BLK6_OMASK)
+
+/** \brief 5C, Overlay Target Address Register */
+#define OVC0_BLK6_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FB5Cu)
+
+/** Alias (User Manual Name) for OVC0_BLK6_OTAR.
+* To use register names with standard convension, please use OVC0_BLK6_OTAR.
+*/
+#define OVC0_OTAR6 (OVC0_BLK6_OTAR)
+
+/** \brief 58, Redirected Address Base Register */
+#define OVC0_BLK6_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FB58u)
+
+/** Alias (User Manual Name) for OVC0_BLK6_RABR.
+* To use register names with standard convension, please use OVC0_BLK6_RABR.
+*/
+#define OVC0_RABR6 (OVC0_BLK6_RABR)
+
+/** \brief 6C, Overlay Mask Register */
+#define OVC0_BLK7_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FB6Cu)
+
+/** Alias (User Manual Name) for OVC0_BLK7_OMASK.
+* To use register names with standard convension, please use OVC0_BLK7_OMASK.
+*/
+#define OVC0_OMASK7 (OVC0_BLK7_OMASK)
+
+/** \brief 68, Overlay Target Address Register */
+#define OVC0_BLK7_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FB68u)
+
+/** Alias (User Manual Name) for OVC0_BLK7_OTAR.
+* To use register names with standard convension, please use OVC0_BLK7_OTAR.
+*/
+#define OVC0_OTAR7 (OVC0_BLK7_OTAR)
+
+/** \brief 64, Redirected Address Base Register */
+#define OVC0_BLK7_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FB64u)
+
+/** Alias (User Manual Name) for OVC0_BLK7_RABR.
+* To use register names with standard convension, please use OVC0_BLK7_RABR.
+*/
+#define OVC0_RABR7 (OVC0_BLK7_RABR)
+
+/** \brief 78, Overlay Mask Register */
+#define OVC0_BLK8_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FB78u)
+
+/** Alias (User Manual Name) for OVC0_BLK8_OMASK.
+* To use register names with standard convension, please use OVC0_BLK8_OMASK.
+*/
+#define OVC0_OMASK8 (OVC0_BLK8_OMASK)
+
+/** \brief 74, Overlay Target Address Register */
+#define OVC0_BLK8_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FB74u)
+
+/** Alias (User Manual Name) for OVC0_BLK8_OTAR.
+* To use register names with standard convension, please use OVC0_BLK8_OTAR.
+*/
+#define OVC0_OTAR8 (OVC0_BLK8_OTAR)
+
+/** \brief 70, Redirected Address Base Register */
+#define OVC0_BLK8_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FB70u)
+
+/** Alias (User Manual Name) for OVC0_BLK8_RABR.
+* To use register names with standard convension, please use OVC0_BLK8_RABR.
+*/
+#define OVC0_RABR8 (OVC0_BLK8_RABR)
+
+/** \brief 84, Overlay Mask Register */
+#define OVC0_BLK9_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF880FB84u)
+
+/** Alias (User Manual Name) for OVC0_BLK9_OMASK.
+* To use register names with standard convension, please use OVC0_BLK9_OMASK.
+*/
+#define OVC0_OMASK9 (OVC0_BLK9_OMASK)
+
+/** \brief 80, Overlay Target Address Register */
+#define OVC0_BLK9_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF880FB80u)
+
+/** Alias (User Manual Name) for OVC0_BLK9_OTAR.
+* To use register names with standard convension, please use OVC0_BLK9_OTAR.
+*/
+#define OVC0_OTAR9 (OVC0_BLK9_OTAR)
+
+/** \brief 7C, Redirected Address Base Register */
+#define OVC0_BLK9_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF880FB7Cu)
+
+/** Alias (User Manual Name) for OVC0_BLK9_RABR.
+* To use register names with standard convension, please use OVC0_BLK9_RABR.
+*/
+#define OVC0_RABR9 (OVC0_BLK9_RABR)
+
+/** \brief 0, Overlay Range Select Register */
+#define OVC0_OSEL /*lint --e(923)*/ (*(volatile Ifx_OVC_OSEL*)0xF880FB00u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Ovc_Cfg_Ovc1
+ * \{ */
+
+/** \brief 18, Overlay Mask Register */
+#define OVC1_BLK0_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FB18u)
+
+/** Alias (User Manual Name) for OVC1_BLK0_OMASK.
+* To use register names with standard convension, please use OVC1_BLK0_OMASK.
+*/
+#define OVC1_OMASK0 (OVC1_BLK0_OMASK)
+
+/** \brief 14, Overlay Target Address Register */
+#define OVC1_BLK0_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FB14u)
+
+/** Alias (User Manual Name) for OVC1_BLK0_OTAR.
+* To use register names with standard convension, please use OVC1_BLK0_OTAR.
+*/
+#define OVC1_OTAR0 (OVC1_BLK0_OTAR)
+
+/** \brief 10, Redirected Address Base Register */
+#define OVC1_BLK0_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FB10u)
+
+/** Alias (User Manual Name) for OVC1_BLK0_RABR.
+* To use register names with standard convension, please use OVC1_BLK0_RABR.
+*/
+#define OVC1_RABR0 (OVC1_BLK0_RABR)
+
+/** \brief 90, Overlay Mask Register */
+#define OVC1_BLK10_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FB90u)
+
+/** Alias (User Manual Name) for OVC1_BLK10_OMASK.
+* To use register names with standard convension, please use OVC1_BLK10_OMASK.
+*/
+#define OVC1_OMASK10 (OVC1_BLK10_OMASK)
+
+/** \brief 8C, Overlay Target Address Register */
+#define OVC1_BLK10_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FB8Cu)
+
+/** Alias (User Manual Name) for OVC1_BLK10_OTAR.
+* To use register names with standard convension, please use OVC1_BLK10_OTAR.
+*/
+#define OVC1_OTAR10 (OVC1_BLK10_OTAR)
+
+/** \brief 88, Redirected Address Base Register */
+#define OVC1_BLK10_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FB88u)
+
+/** Alias (User Manual Name) for OVC1_BLK10_RABR.
+* To use register names with standard convension, please use OVC1_BLK10_RABR.
+*/
+#define OVC1_RABR10 (OVC1_BLK10_RABR)
+
+/** \brief 9C, Overlay Mask Register */
+#define OVC1_BLK11_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FB9Cu)
+
+/** Alias (User Manual Name) for OVC1_BLK11_OMASK.
+* To use register names with standard convension, please use OVC1_BLK11_OMASK.
+*/
+#define OVC1_OMASK11 (OVC1_BLK11_OMASK)
+
+/** \brief 98, Overlay Target Address Register */
+#define OVC1_BLK11_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FB98u)
+
+/** Alias (User Manual Name) for OVC1_BLK11_OTAR.
+* To use register names with standard convension, please use OVC1_BLK11_OTAR.
+*/
+#define OVC1_OTAR11 (OVC1_BLK11_OTAR)
+
+/** \brief 94, Redirected Address Base Register */
+#define OVC1_BLK11_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FB94u)
+
+/** Alias (User Manual Name) for OVC1_BLK11_RABR.
+* To use register names with standard convension, please use OVC1_BLK11_RABR.
+*/
+#define OVC1_RABR11 (OVC1_BLK11_RABR)
+
+/** \brief A8, Overlay Mask Register */
+#define OVC1_BLK12_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FBA8u)
+
+/** Alias (User Manual Name) for OVC1_BLK12_OMASK.
+* To use register names with standard convension, please use OVC1_BLK12_OMASK.
+*/
+#define OVC1_OMASK12 (OVC1_BLK12_OMASK)
+
+/** \brief A4, Overlay Target Address Register */
+#define OVC1_BLK12_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FBA4u)
+
+/** Alias (User Manual Name) for OVC1_BLK12_OTAR.
+* To use register names with standard convension, please use OVC1_BLK12_OTAR.
+*/
+#define OVC1_OTAR12 (OVC1_BLK12_OTAR)
+
+/** \brief A0, Redirected Address Base Register */
+#define OVC1_BLK12_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FBA0u)
+
+/** Alias (User Manual Name) for OVC1_BLK12_RABR.
+* To use register names with standard convension, please use OVC1_BLK12_RABR.
+*/
+#define OVC1_RABR12 (OVC1_BLK12_RABR)
+
+/** \brief B4, Overlay Mask Register */
+#define OVC1_BLK13_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FBB4u)
+
+/** Alias (User Manual Name) for OVC1_BLK13_OMASK.
+* To use register names with standard convension, please use OVC1_BLK13_OMASK.
+*/
+#define OVC1_OMASK13 (OVC1_BLK13_OMASK)
+
+/** \brief B0, Overlay Target Address Register */
+#define OVC1_BLK13_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FBB0u)
+
+/** Alias (User Manual Name) for OVC1_BLK13_OTAR.
+* To use register names with standard convension, please use OVC1_BLK13_OTAR.
+*/
+#define OVC1_OTAR13 (OVC1_BLK13_OTAR)
+
+/** \brief AC, Redirected Address Base Register */
+#define OVC1_BLK13_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FBACu)
+
+/** Alias (User Manual Name) for OVC1_BLK13_RABR.
+* To use register names with standard convension, please use OVC1_BLK13_RABR.
+*/
+#define OVC1_RABR13 (OVC1_BLK13_RABR)
+
+/** \brief C0, Overlay Mask Register */
+#define OVC1_BLK14_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FBC0u)
+
+/** Alias (User Manual Name) for OVC1_BLK14_OMASK.
+* To use register names with standard convension, please use OVC1_BLK14_OMASK.
+*/
+#define OVC1_OMASK14 (OVC1_BLK14_OMASK)
+
+/** \brief BC, Overlay Target Address Register */
+#define OVC1_BLK14_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FBBCu)
+
+/** Alias (User Manual Name) for OVC1_BLK14_OTAR.
+* To use register names with standard convension, please use OVC1_BLK14_OTAR.
+*/
+#define OVC1_OTAR14 (OVC1_BLK14_OTAR)
+
+/** \brief B8, Redirected Address Base Register */
+#define OVC1_BLK14_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FBB8u)
+
+/** Alias (User Manual Name) for OVC1_BLK14_RABR.
+* To use register names with standard convension, please use OVC1_BLK14_RABR.
+*/
+#define OVC1_RABR14 (OVC1_BLK14_RABR)
+
+/** \brief CC, Overlay Mask Register */
+#define OVC1_BLK15_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FBCCu)
+
+/** Alias (User Manual Name) for OVC1_BLK15_OMASK.
+* To use register names with standard convension, please use OVC1_BLK15_OMASK.
+*/
+#define OVC1_OMASK15 (OVC1_BLK15_OMASK)
+
+/** \brief C8, Overlay Target Address Register */
+#define OVC1_BLK15_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FBC8u)
+
+/** Alias (User Manual Name) for OVC1_BLK15_OTAR.
+* To use register names with standard convension, please use OVC1_BLK15_OTAR.
+*/
+#define OVC1_OTAR15 (OVC1_BLK15_OTAR)
+
+/** \brief C4, Redirected Address Base Register */
+#define OVC1_BLK15_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FBC4u)
+
+/** Alias (User Manual Name) for OVC1_BLK15_RABR.
+* To use register names with standard convension, please use OVC1_BLK15_RABR.
+*/
+#define OVC1_RABR15 (OVC1_BLK15_RABR)
+
+/** \brief D8, Overlay Mask Register */
+#define OVC1_BLK16_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FBD8u)
+
+/** Alias (User Manual Name) for OVC1_BLK16_OMASK.
+* To use register names with standard convension, please use OVC1_BLK16_OMASK.
+*/
+#define OVC1_OMASK16 (OVC1_BLK16_OMASK)
+
+/** \brief D4, Overlay Target Address Register */
+#define OVC1_BLK16_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FBD4u)
+
+/** Alias (User Manual Name) for OVC1_BLK16_OTAR.
+* To use register names with standard convension, please use OVC1_BLK16_OTAR.
+*/
+#define OVC1_OTAR16 (OVC1_BLK16_OTAR)
+
+/** \brief D0, Redirected Address Base Register */
+#define OVC1_BLK16_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FBD0u)
+
+/** Alias (User Manual Name) for OVC1_BLK16_RABR.
+* To use register names with standard convension, please use OVC1_BLK16_RABR.
+*/
+#define OVC1_RABR16 (OVC1_BLK16_RABR)
+
+/** \brief E4, Overlay Mask Register */
+#define OVC1_BLK17_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FBE4u)
+
+/** Alias (User Manual Name) for OVC1_BLK17_OMASK.
+* To use register names with standard convension, please use OVC1_BLK17_OMASK.
+*/
+#define OVC1_OMASK17 (OVC1_BLK17_OMASK)
+
+/** \brief E0, Overlay Target Address Register */
+#define OVC1_BLK17_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FBE0u)
+
+/** Alias (User Manual Name) for OVC1_BLK17_OTAR.
+* To use register names with standard convension, please use OVC1_BLK17_OTAR.
+*/
+#define OVC1_OTAR17 (OVC1_BLK17_OTAR)
+
+/** \brief DC, Redirected Address Base Register */
+#define OVC1_BLK17_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FBDCu)
+
+/** Alias (User Manual Name) for OVC1_BLK17_RABR.
+* To use register names with standard convension, please use OVC1_BLK17_RABR.
+*/
+#define OVC1_RABR17 (OVC1_BLK17_RABR)
+
+/** \brief F0, Overlay Mask Register */
+#define OVC1_BLK18_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FBF0u)
+
+/** Alias (User Manual Name) for OVC1_BLK18_OMASK.
+* To use register names with standard convension, please use OVC1_BLK18_OMASK.
+*/
+#define OVC1_OMASK18 (OVC1_BLK18_OMASK)
+
+/** \brief EC, Overlay Target Address Register */
+#define OVC1_BLK18_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FBECu)
+
+/** Alias (User Manual Name) for OVC1_BLK18_OTAR.
+* To use register names with standard convension, please use OVC1_BLK18_OTAR.
+*/
+#define OVC1_OTAR18 (OVC1_BLK18_OTAR)
+
+/** \brief E8, Redirected Address Base Register */
+#define OVC1_BLK18_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FBE8u)
+
+/** Alias (User Manual Name) for OVC1_BLK18_RABR.
+* To use register names with standard convension, please use OVC1_BLK18_RABR.
+*/
+#define OVC1_RABR18 (OVC1_BLK18_RABR)
+
+/** \brief FC, Overlay Mask Register */
+#define OVC1_BLK19_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FBFCu)
+
+/** Alias (User Manual Name) for OVC1_BLK19_OMASK.
+* To use register names with standard convension, please use OVC1_BLK19_OMASK.
+*/
+#define OVC1_OMASK19 (OVC1_BLK19_OMASK)
+
+/** \brief F8, Overlay Target Address Register */
+#define OVC1_BLK19_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FBF8u)
+
+/** Alias (User Manual Name) for OVC1_BLK19_OTAR.
+* To use register names with standard convension, please use OVC1_BLK19_OTAR.
+*/
+#define OVC1_OTAR19 (OVC1_BLK19_OTAR)
+
+/** \brief F4, Redirected Address Base Register */
+#define OVC1_BLK19_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FBF4u)
+
+/** Alias (User Manual Name) for OVC1_BLK19_RABR.
+* To use register names with standard convension, please use OVC1_BLK19_RABR.
+*/
+#define OVC1_RABR19 (OVC1_BLK19_RABR)
+
+/** \brief 24, Overlay Mask Register */
+#define OVC1_BLK1_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FB24u)
+
+/** Alias (User Manual Name) for OVC1_BLK1_OMASK.
+* To use register names with standard convension, please use OVC1_BLK1_OMASK.
+*/
+#define OVC1_OMASK1 (OVC1_BLK1_OMASK)
+
+/** \brief 20, Overlay Target Address Register */
+#define OVC1_BLK1_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FB20u)
+
+/** Alias (User Manual Name) for OVC1_BLK1_OTAR.
+* To use register names with standard convension, please use OVC1_BLK1_OTAR.
+*/
+#define OVC1_OTAR1 (OVC1_BLK1_OTAR)
+
+/** \brief 1C, Redirected Address Base Register */
+#define OVC1_BLK1_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FB1Cu)
+
+/** Alias (User Manual Name) for OVC1_BLK1_RABR.
+* To use register names with standard convension, please use OVC1_BLK1_RABR.
+*/
+#define OVC1_RABR1 (OVC1_BLK1_RABR)
+
+/** \brief 108, Overlay Mask Register */
+#define OVC1_BLK20_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FC08u)
+
+/** Alias (User Manual Name) for OVC1_BLK20_OMASK.
+* To use register names with standard convension, please use OVC1_BLK20_OMASK.
+*/
+#define OVC1_OMASK20 (OVC1_BLK20_OMASK)
+
+/** \brief 104, Overlay Target Address Register */
+#define OVC1_BLK20_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FC04u)
+
+/** Alias (User Manual Name) for OVC1_BLK20_OTAR.
+* To use register names with standard convension, please use OVC1_BLK20_OTAR.
+*/
+#define OVC1_OTAR20 (OVC1_BLK20_OTAR)
+
+/** \brief 100, Redirected Address Base Register */
+#define OVC1_BLK20_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FC00u)
+
+/** Alias (User Manual Name) for OVC1_BLK20_RABR.
+* To use register names with standard convension, please use OVC1_BLK20_RABR.
+*/
+#define OVC1_RABR20 (OVC1_BLK20_RABR)
+
+/** \brief 114, Overlay Mask Register */
+#define OVC1_BLK21_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FC14u)
+
+/** Alias (User Manual Name) for OVC1_BLK21_OMASK.
+* To use register names with standard convension, please use OVC1_BLK21_OMASK.
+*/
+#define OVC1_OMASK21 (OVC1_BLK21_OMASK)
+
+/** \brief 110, Overlay Target Address Register */
+#define OVC1_BLK21_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FC10u)
+
+/** Alias (User Manual Name) for OVC1_BLK21_OTAR.
+* To use register names with standard convension, please use OVC1_BLK21_OTAR.
+*/
+#define OVC1_OTAR21 (OVC1_BLK21_OTAR)
+
+/** \brief 10C, Redirected Address Base Register */
+#define OVC1_BLK21_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FC0Cu)
+
+/** Alias (User Manual Name) for OVC1_BLK21_RABR.
+* To use register names with standard convension, please use OVC1_BLK21_RABR.
+*/
+#define OVC1_RABR21 (OVC1_BLK21_RABR)
+
+/** \brief 120, Overlay Mask Register */
+#define OVC1_BLK22_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FC20u)
+
+/** Alias (User Manual Name) for OVC1_BLK22_OMASK.
+* To use register names with standard convension, please use OVC1_BLK22_OMASK.
+*/
+#define OVC1_OMASK22 (OVC1_BLK22_OMASK)
+
+/** \brief 11C, Overlay Target Address Register */
+#define OVC1_BLK22_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FC1Cu)
+
+/** Alias (User Manual Name) for OVC1_BLK22_OTAR.
+* To use register names with standard convension, please use OVC1_BLK22_OTAR.
+*/
+#define OVC1_OTAR22 (OVC1_BLK22_OTAR)
+
+/** \brief 118, Redirected Address Base Register */
+#define OVC1_BLK22_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FC18u)
+
+/** Alias (User Manual Name) for OVC1_BLK22_RABR.
+* To use register names with standard convension, please use OVC1_BLK22_RABR.
+*/
+#define OVC1_RABR22 (OVC1_BLK22_RABR)
+
+/** \brief 12C, Overlay Mask Register */
+#define OVC1_BLK23_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FC2Cu)
+
+/** Alias (User Manual Name) for OVC1_BLK23_OMASK.
+* To use register names with standard convension, please use OVC1_BLK23_OMASK.
+*/
+#define OVC1_OMASK23 (OVC1_BLK23_OMASK)
+
+/** \brief 128, Overlay Target Address Register */
+#define OVC1_BLK23_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FC28u)
+
+/** Alias (User Manual Name) for OVC1_BLK23_OTAR.
+* To use register names with standard convension, please use OVC1_BLK23_OTAR.
+*/
+#define OVC1_OTAR23 (OVC1_BLK23_OTAR)
+
+/** \brief 124, Redirected Address Base Register */
+#define OVC1_BLK23_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FC24u)
+
+/** Alias (User Manual Name) for OVC1_BLK23_RABR.
+* To use register names with standard convension, please use OVC1_BLK23_RABR.
+*/
+#define OVC1_RABR23 (OVC1_BLK23_RABR)
+
+/** \brief 138, Overlay Mask Register */
+#define OVC1_BLK24_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FC38u)
+
+/** Alias (User Manual Name) for OVC1_BLK24_OMASK.
+* To use register names with standard convension, please use OVC1_BLK24_OMASK.
+*/
+#define OVC1_OMASK24 (OVC1_BLK24_OMASK)
+
+/** \brief 134, Overlay Target Address Register */
+#define OVC1_BLK24_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FC34u)
+
+/** Alias (User Manual Name) for OVC1_BLK24_OTAR.
+* To use register names with standard convension, please use OVC1_BLK24_OTAR.
+*/
+#define OVC1_OTAR24 (OVC1_BLK24_OTAR)
+
+/** \brief 130, Redirected Address Base Register */
+#define OVC1_BLK24_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FC30u)
+
+/** Alias (User Manual Name) for OVC1_BLK24_RABR.
+* To use register names with standard convension, please use OVC1_BLK24_RABR.
+*/
+#define OVC1_RABR24 (OVC1_BLK24_RABR)
+
+/** \brief 144, Overlay Mask Register */
+#define OVC1_BLK25_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FC44u)
+
+/** Alias (User Manual Name) for OVC1_BLK25_OMASK.
+* To use register names with standard convension, please use OVC1_BLK25_OMASK.
+*/
+#define OVC1_OMASK25 (OVC1_BLK25_OMASK)
+
+/** \brief 140, Overlay Target Address Register */
+#define OVC1_BLK25_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FC40u)
+
+/** Alias (User Manual Name) for OVC1_BLK25_OTAR.
+* To use register names with standard convension, please use OVC1_BLK25_OTAR.
+*/
+#define OVC1_OTAR25 (OVC1_BLK25_OTAR)
+
+/** \brief 13C, Redirected Address Base Register */
+#define OVC1_BLK25_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FC3Cu)
+
+/** Alias (User Manual Name) for OVC1_BLK25_RABR.
+* To use register names with standard convension, please use OVC1_BLK25_RABR.
+*/
+#define OVC1_RABR25 (OVC1_BLK25_RABR)
+
+/** \brief 150, Overlay Mask Register */
+#define OVC1_BLK26_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FC50u)
+
+/** Alias (User Manual Name) for OVC1_BLK26_OMASK.
+* To use register names with standard convension, please use OVC1_BLK26_OMASK.
+*/
+#define OVC1_OMASK26 (OVC1_BLK26_OMASK)
+
+/** \brief 14C, Overlay Target Address Register */
+#define OVC1_BLK26_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FC4Cu)
+
+/** Alias (User Manual Name) for OVC1_BLK26_OTAR.
+* To use register names with standard convension, please use OVC1_BLK26_OTAR.
+*/
+#define OVC1_OTAR26 (OVC1_BLK26_OTAR)
+
+/** \brief 148, Redirected Address Base Register */
+#define OVC1_BLK26_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FC48u)
+
+/** Alias (User Manual Name) for OVC1_BLK26_RABR.
+* To use register names with standard convension, please use OVC1_BLK26_RABR.
+*/
+#define OVC1_RABR26 (OVC1_BLK26_RABR)
+
+/** \brief 15C, Overlay Mask Register */
+#define OVC1_BLK27_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FC5Cu)
+
+/** Alias (User Manual Name) for OVC1_BLK27_OMASK.
+* To use register names with standard convension, please use OVC1_BLK27_OMASK.
+*/
+#define OVC1_OMASK27 (OVC1_BLK27_OMASK)
+
+/** \brief 158, Overlay Target Address Register */
+#define OVC1_BLK27_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FC58u)
+
+/** Alias (User Manual Name) for OVC1_BLK27_OTAR.
+* To use register names with standard convension, please use OVC1_BLK27_OTAR.
+*/
+#define OVC1_OTAR27 (OVC1_BLK27_OTAR)
+
+/** \brief 154, Redirected Address Base Register */
+#define OVC1_BLK27_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FC54u)
+
+/** Alias (User Manual Name) for OVC1_BLK27_RABR.
+* To use register names with standard convension, please use OVC1_BLK27_RABR.
+*/
+#define OVC1_RABR27 (OVC1_BLK27_RABR)
+
+/** \brief 168, Overlay Mask Register */
+#define OVC1_BLK28_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FC68u)
+
+/** Alias (User Manual Name) for OVC1_BLK28_OMASK.
+* To use register names with standard convension, please use OVC1_BLK28_OMASK.
+*/
+#define OVC1_OMASK28 (OVC1_BLK28_OMASK)
+
+/** \brief 164, Overlay Target Address Register */
+#define OVC1_BLK28_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FC64u)
+
+/** Alias (User Manual Name) for OVC1_BLK28_OTAR.
+* To use register names with standard convension, please use OVC1_BLK28_OTAR.
+*/
+#define OVC1_OTAR28 (OVC1_BLK28_OTAR)
+
+/** \brief 160, Redirected Address Base Register */
+#define OVC1_BLK28_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FC60u)
+
+/** Alias (User Manual Name) for OVC1_BLK28_RABR.
+* To use register names with standard convension, please use OVC1_BLK28_RABR.
+*/
+#define OVC1_RABR28 (OVC1_BLK28_RABR)
+
+/** \brief 174, Overlay Mask Register */
+#define OVC1_BLK29_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FC74u)
+
+/** Alias (User Manual Name) for OVC1_BLK29_OMASK.
+* To use register names with standard convension, please use OVC1_BLK29_OMASK.
+*/
+#define OVC1_OMASK29 (OVC1_BLK29_OMASK)
+
+/** \brief 170, Overlay Target Address Register */
+#define OVC1_BLK29_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FC70u)
+
+/** Alias (User Manual Name) for OVC1_BLK29_OTAR.
+* To use register names with standard convension, please use OVC1_BLK29_OTAR.
+*/
+#define OVC1_OTAR29 (OVC1_BLK29_OTAR)
+
+/** \brief 16C, Redirected Address Base Register */
+#define OVC1_BLK29_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FC6Cu)
+
+/** Alias (User Manual Name) for OVC1_BLK29_RABR.
+* To use register names with standard convension, please use OVC1_BLK29_RABR.
+*/
+#define OVC1_RABR29 (OVC1_BLK29_RABR)
+
+/** \brief 30, Overlay Mask Register */
+#define OVC1_BLK2_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FB30u)
+
+/** Alias (User Manual Name) for OVC1_BLK2_OMASK.
+* To use register names with standard convension, please use OVC1_BLK2_OMASK.
+*/
+#define OVC1_OMASK2 (OVC1_BLK2_OMASK)
+
+/** \brief 2C, Overlay Target Address Register */
+#define OVC1_BLK2_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FB2Cu)
+
+/** Alias (User Manual Name) for OVC1_BLK2_OTAR.
+* To use register names with standard convension, please use OVC1_BLK2_OTAR.
+*/
+#define OVC1_OTAR2 (OVC1_BLK2_OTAR)
+
+/** \brief 28, Redirected Address Base Register */
+#define OVC1_BLK2_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FB28u)
+
+/** Alias (User Manual Name) for OVC1_BLK2_RABR.
+* To use register names with standard convension, please use OVC1_BLK2_RABR.
+*/
+#define OVC1_RABR2 (OVC1_BLK2_RABR)
+
+/** \brief 180, Overlay Mask Register */
+#define OVC1_BLK30_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FC80u)
+
+/** Alias (User Manual Name) for OVC1_BLK30_OMASK.
+* To use register names with standard convension, please use OVC1_BLK30_OMASK.
+*/
+#define OVC1_OMASK30 (OVC1_BLK30_OMASK)
+
+/** \brief 17C, Overlay Target Address Register */
+#define OVC1_BLK30_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FC7Cu)
+
+/** Alias (User Manual Name) for OVC1_BLK30_OTAR.
+* To use register names with standard convension, please use OVC1_BLK30_OTAR.
+*/
+#define OVC1_OTAR30 (OVC1_BLK30_OTAR)
+
+/** \brief 178, Redirected Address Base Register */
+#define OVC1_BLK30_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FC78u)
+
+/** Alias (User Manual Name) for OVC1_BLK30_RABR.
+* To use register names with standard convension, please use OVC1_BLK30_RABR.
+*/
+#define OVC1_RABR30 (OVC1_BLK30_RABR)
+
+/** \brief 18C, Overlay Mask Register */
+#define OVC1_BLK31_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FC8Cu)
+
+/** Alias (User Manual Name) for OVC1_BLK31_OMASK.
+* To use register names with standard convension, please use OVC1_BLK31_OMASK.
+*/
+#define OVC1_OMASK31 (OVC1_BLK31_OMASK)
+
+/** \brief 188, Overlay Target Address Register */
+#define OVC1_BLK31_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FC88u)
+
+/** Alias (User Manual Name) for OVC1_BLK31_OTAR.
+* To use register names with standard convension, please use OVC1_BLK31_OTAR.
+*/
+#define OVC1_OTAR31 (OVC1_BLK31_OTAR)
+
+/** \brief 184, Redirected Address Base Register */
+#define OVC1_BLK31_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FC84u)
+
+/** Alias (User Manual Name) for OVC1_BLK31_RABR.
+* To use register names with standard convension, please use OVC1_BLK31_RABR.
+*/
+#define OVC1_RABR31 (OVC1_BLK31_RABR)
+
+/** \brief 3C, Overlay Mask Register */
+#define OVC1_BLK3_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FB3Cu)
+
+/** Alias (User Manual Name) for OVC1_BLK3_OMASK.
+* To use register names with standard convension, please use OVC1_BLK3_OMASK.
+*/
+#define OVC1_OMASK3 (OVC1_BLK3_OMASK)
+
+/** \brief 38, Overlay Target Address Register */
+#define OVC1_BLK3_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FB38u)
+
+/** Alias (User Manual Name) for OVC1_BLK3_OTAR.
+* To use register names with standard convension, please use OVC1_BLK3_OTAR.
+*/
+#define OVC1_OTAR3 (OVC1_BLK3_OTAR)
+
+/** \brief 34, Redirected Address Base Register */
+#define OVC1_BLK3_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FB34u)
+
+/** Alias (User Manual Name) for OVC1_BLK3_RABR.
+* To use register names with standard convension, please use OVC1_BLK3_RABR.
+*/
+#define OVC1_RABR3 (OVC1_BLK3_RABR)
+
+/** \brief 48, Overlay Mask Register */
+#define OVC1_BLK4_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FB48u)
+
+/** Alias (User Manual Name) for OVC1_BLK4_OMASK.
+* To use register names with standard convension, please use OVC1_BLK4_OMASK.
+*/
+#define OVC1_OMASK4 (OVC1_BLK4_OMASK)
+
+/** \brief 44, Overlay Target Address Register */
+#define OVC1_BLK4_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FB44u)
+
+/** Alias (User Manual Name) for OVC1_BLK4_OTAR.
+* To use register names with standard convension, please use OVC1_BLK4_OTAR.
+*/
+#define OVC1_OTAR4 (OVC1_BLK4_OTAR)
+
+/** \brief 40, Redirected Address Base Register */
+#define OVC1_BLK4_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FB40u)
+
+/** Alias (User Manual Name) for OVC1_BLK4_RABR.
+* To use register names with standard convension, please use OVC1_BLK4_RABR.
+*/
+#define OVC1_RABR4 (OVC1_BLK4_RABR)
+
+/** \brief 54, Overlay Mask Register */
+#define OVC1_BLK5_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FB54u)
+
+/** Alias (User Manual Name) for OVC1_BLK5_OMASK.
+* To use register names with standard convension, please use OVC1_BLK5_OMASK.
+*/
+#define OVC1_OMASK5 (OVC1_BLK5_OMASK)
+
+/** \brief 50, Overlay Target Address Register */
+#define OVC1_BLK5_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FB50u)
+
+/** Alias (User Manual Name) for OVC1_BLK5_OTAR.
+* To use register names with standard convension, please use OVC1_BLK5_OTAR.
+*/
+#define OVC1_OTAR5 (OVC1_BLK5_OTAR)
+
+/** \brief 4C, Redirected Address Base Register */
+#define OVC1_BLK5_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FB4Cu)
+
+/** Alias (User Manual Name) for OVC1_BLK5_RABR.
+* To use register names with standard convension, please use OVC1_BLK5_RABR.
+*/
+#define OVC1_RABR5 (OVC1_BLK5_RABR)
+
+/** \brief 60, Overlay Mask Register */
+#define OVC1_BLK6_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FB60u)
+
+/** Alias (User Manual Name) for OVC1_BLK6_OMASK.
+* To use register names with standard convension, please use OVC1_BLK6_OMASK.
+*/
+#define OVC1_OMASK6 (OVC1_BLK6_OMASK)
+
+/** \brief 5C, Overlay Target Address Register */
+#define OVC1_BLK6_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FB5Cu)
+
+/** Alias (User Manual Name) for OVC1_BLK6_OTAR.
+* To use register names with standard convension, please use OVC1_BLK6_OTAR.
+*/
+#define OVC1_OTAR6 (OVC1_BLK6_OTAR)
+
+/** \brief 58, Redirected Address Base Register */
+#define OVC1_BLK6_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FB58u)
+
+/** Alias (User Manual Name) for OVC1_BLK6_RABR.
+* To use register names with standard convension, please use OVC1_BLK6_RABR.
+*/
+#define OVC1_RABR6 (OVC1_BLK6_RABR)
+
+/** \brief 6C, Overlay Mask Register */
+#define OVC1_BLK7_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FB6Cu)
+
+/** Alias (User Manual Name) for OVC1_BLK7_OMASK.
+* To use register names with standard convension, please use OVC1_BLK7_OMASK.
+*/
+#define OVC1_OMASK7 (OVC1_BLK7_OMASK)
+
+/** \brief 68, Overlay Target Address Register */
+#define OVC1_BLK7_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FB68u)
+
+/** Alias (User Manual Name) for OVC1_BLK7_OTAR.
+* To use register names with standard convension, please use OVC1_BLK7_OTAR.
+*/
+#define OVC1_OTAR7 (OVC1_BLK7_OTAR)
+
+/** \brief 64, Redirected Address Base Register */
+#define OVC1_BLK7_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FB64u)
+
+/** Alias (User Manual Name) for OVC1_BLK7_RABR.
+* To use register names with standard convension, please use OVC1_BLK7_RABR.
+*/
+#define OVC1_RABR7 (OVC1_BLK7_RABR)
+
+/** \brief 78, Overlay Mask Register */
+#define OVC1_BLK8_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FB78u)
+
+/** Alias (User Manual Name) for OVC1_BLK8_OMASK.
+* To use register names with standard convension, please use OVC1_BLK8_OMASK.
+*/
+#define OVC1_OMASK8 (OVC1_BLK8_OMASK)
+
+/** \brief 74, Overlay Target Address Register */
+#define OVC1_BLK8_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FB74u)
+
+/** Alias (User Manual Name) for OVC1_BLK8_OTAR.
+* To use register names with standard convension, please use OVC1_BLK8_OTAR.
+*/
+#define OVC1_OTAR8 (OVC1_BLK8_OTAR)
+
+/** \brief 70, Redirected Address Base Register */
+#define OVC1_BLK8_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FB70u)
+
+/** Alias (User Manual Name) for OVC1_BLK8_RABR.
+* To use register names with standard convension, please use OVC1_BLK8_RABR.
+*/
+#define OVC1_RABR8 (OVC1_BLK8_RABR)
+
+/** \brief 84, Overlay Mask Register */
+#define OVC1_BLK9_OMASK /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OMASK*)0xF882FB84u)
+
+/** Alias (User Manual Name) for OVC1_BLK9_OMASK.
+* To use register names with standard convension, please use OVC1_BLK9_OMASK.
+*/
+#define OVC1_OMASK9 (OVC1_BLK9_OMASK)
+
+/** \brief 80, Overlay Target Address Register */
+#define OVC1_BLK9_OTAR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_OTAR*)0xF882FB80u)
+
+/** Alias (User Manual Name) for OVC1_BLK9_OTAR.
+* To use register names with standard convension, please use OVC1_BLK9_OTAR.
+*/
+#define OVC1_OTAR9 (OVC1_BLK9_OTAR)
+
+/** \brief 7C, Redirected Address Base Register */
+#define OVC1_BLK9_RABR /*lint --e(923)*/ (*(volatile Ifx_OVC_BLK_RABR*)0xF882FB7Cu)
+
+/** Alias (User Manual Name) for OVC1_BLK9_RABR.
+* To use register names with standard convension, please use OVC1_BLK9_RABR.
+*/
+#define OVC1_RABR9 (OVC1_BLK9_RABR)
+
+/** \brief 0, Overlay Range Select Register */
+#define OVC1_OSEL /*lint --e(923)*/ (*(volatile Ifx_OVC_OSEL*)0xF882FB00u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXOVC_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxOvc_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxOvc_regdef.h
new file mode 100644
index 0000000..844d1f3
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxOvc_regdef.h
@@ -0,0 +1,185 @@
+/**
+ * \file IfxOvc_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Ovc Ovc
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Ovc_Bitfields Bitfields
+ * \ingroup IfxLld_Ovc
+ *
+ * \defgroup IfxLld_Ovc_union Union
+ * \ingroup IfxLld_Ovc
+ *
+ * \defgroup IfxLld_Ovc_struct Struct
+ * \ingroup IfxLld_Ovc
+ *
+ */
+#ifndef IFXOVC_REGDEF_H
+#define IFXOVC_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Ovc_Bitfields
+ * \{ */
+
+/** \brief Overlay Mask Register */
+typedef struct _Ifx_OVC_BLK_OMASK_Bits
+{
+ Ifx_Strict_32Bit reserved_0:5; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit OMASK:12; /**< \brief [16:5] Overlay Address Mask (rw) */
+ Ifx_Strict_32Bit ONE:11; /**< \brief [27:17] Fixed "1" Values (r) */
+ Ifx_Strict_32Bit reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_OVC_BLK_OMASK_Bits;
+
+/** \brief Overlay Target Address Register */
+typedef struct _Ifx_OVC_BLK_OTAR_Bits
+{
+ Ifx_Strict_32Bit reserved_0:5; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit TBASE:23; /**< \brief [27:5] Target Base (rw) */
+ Ifx_Strict_32Bit reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_OVC_BLK_OTAR_Bits;
+
+/** \brief Redirected Address Base Register */
+typedef struct _Ifx_OVC_BLK_RABR_Bits
+{
+ Ifx_Strict_32Bit reserved_0:5; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit OBASE:17; /**< \brief [21:5] Overlay Block Base Address (rw) */
+ Ifx_Strict_32Bit reserved_22:2; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit OMEM:3; /**< \brief [26:24] Overlay Memory Select (rw) */
+ Ifx_Strict_32Bit reserved_27:4; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit OVEN:1; /**< \brief [31:31] Overlay Enabled (rwh) */
+} Ifx_OVC_BLK_RABR_Bits;
+
+/** \brief Overlay Range Select Register */
+typedef struct _Ifx_OVC_OSEL_Bits
+{
+ Ifx_Strict_32Bit SHOVEN0:1; /**< \brief [0:0] Shadow Overlay Enable 0 (rw) */
+ Ifx_Strict_32Bit SHOVEN1:1; /**< \brief [1:1] Shadow Overlay Enable 1 (rw) */
+ Ifx_Strict_32Bit SHOVEN2:1; /**< \brief [2:2] Shadow Overlay Enable 2 (rw) */
+ Ifx_Strict_32Bit SHOVEN3:1; /**< \brief [3:3] Shadow Overlay Enable 3 (rw) */
+ Ifx_Strict_32Bit SHOVEN4:1; /**< \brief [4:4] Shadow Overlay Enable 4 (rw) */
+ Ifx_Strict_32Bit SHOVEN5:1; /**< \brief [5:5] Shadow Overlay Enable 5 (rw) */
+ Ifx_Strict_32Bit SHOVEN6:1; /**< \brief [6:6] Shadow Overlay Enable 6 (rw) */
+ Ifx_Strict_32Bit SHOVEN7:1; /**< \brief [7:7] Shadow Overlay Enable 7 (rw) */
+ Ifx_Strict_32Bit SHOVEN8:1; /**< \brief [8:8] Shadow Overlay Enable 8 (rw) */
+ Ifx_Strict_32Bit SHOVEN9:1; /**< \brief [9:9] Shadow Overlay Enable 9 (rw) */
+ Ifx_Strict_32Bit SHOVEN10:1; /**< \brief [10:10] Shadow Overlay Enable 10 (rw) */
+ Ifx_Strict_32Bit SHOVEN11:1; /**< \brief [11:11] Shadow Overlay Enable 11 (rw) */
+ Ifx_Strict_32Bit SHOVEN12:1; /**< \brief [12:12] Shadow Overlay Enable 12 (rw) */
+ Ifx_Strict_32Bit SHOVEN13:1; /**< \brief [13:13] Shadow Overlay Enable 13 (rw) */
+ Ifx_Strict_32Bit SHOVEN14:1; /**< \brief [14:14] Shadow Overlay Enable 14 (rw) */
+ Ifx_Strict_32Bit SHOVEN15:1; /**< \brief [15:15] Shadow Overlay Enable 15 (rw) */
+ Ifx_Strict_32Bit SHOVEN16:1; /**< \brief [16:16] Shadow Overlay Enable 16 (rw) */
+ Ifx_Strict_32Bit SHOVEN17:1; /**< \brief [17:17] Shadow Overlay Enable 17 (rw) */
+ Ifx_Strict_32Bit SHOVEN18:1; /**< \brief [18:18] Shadow Overlay Enable 18 (rw) */
+ Ifx_Strict_32Bit SHOVEN19:1; /**< \brief [19:19] Shadow Overlay Enable 19 (rw) */
+ Ifx_Strict_32Bit SHOVEN20:1; /**< \brief [20:20] Shadow Overlay Enable 20 (rw) */
+ Ifx_Strict_32Bit SHOVEN21:1; /**< \brief [21:21] Shadow Overlay Enable 21 (rw) */
+ Ifx_Strict_32Bit SHOVEN22:1; /**< \brief [22:22] Shadow Overlay Enable 22 (rw) */
+ Ifx_Strict_32Bit SHOVEN23:1; /**< \brief [23:23] Shadow Overlay Enable 23 (rw) */
+ Ifx_Strict_32Bit SHOVEN24:1; /**< \brief [24:24] Shadow Overlay Enable 24 (rw) */
+ Ifx_Strict_32Bit SHOVEN25:1; /**< \brief [25:25] Shadow Overlay Enable 25 (rw) */
+ Ifx_Strict_32Bit SHOVEN26:1; /**< \brief [26:26] Shadow Overlay Enable 26 (rw) */
+ Ifx_Strict_32Bit SHOVEN27:1; /**< \brief [27:27] Shadow Overlay Enable 27 (rw) */
+ Ifx_Strict_32Bit SHOVEN28:1; /**< \brief [28:28] Shadow Overlay Enable 28 (rw) */
+ Ifx_Strict_32Bit SHOVEN29:1; /**< \brief [29:29] Shadow Overlay Enable 29 (rw) */
+ Ifx_Strict_32Bit SHOVEN30:1; /**< \brief [30:30] Shadow Overlay Enable 30 (rw) */
+ Ifx_Strict_32Bit SHOVEN31:1; /**< \brief [31:31] Shadow Overlay Enable 31 (rw) */
+} Ifx_OVC_OSEL_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Ovc_union
+ * \{ */
+
+/** \brief Overlay Mask Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_OVC_BLK_OMASK_Bits B; /**< \brief Bitfield access */
+} Ifx_OVC_BLK_OMASK;
+
+/** \brief Overlay Target Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_OVC_BLK_OTAR_Bits B; /**< \brief Bitfield access */
+} Ifx_OVC_BLK_OTAR;
+
+/** \brief Redirected Address Base Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_OVC_BLK_RABR_Bits B; /**< \brief Bitfield access */
+} Ifx_OVC_BLK_RABR;
+
+/** \brief Overlay Range Select Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_OVC_OSEL_Bits B; /**< \brief Bitfield access */
+} Ifx_OVC_OSEL;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Ovc_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L1
+ * \{ */
+
+/** \brief Overlay blocks objects */
+typedef volatile struct _Ifx_OVC_BLK
+{
+ Ifx_OVC_BLK_RABR RABR; /**< \brief 0, Redirected Address Base Register */
+ Ifx_OVC_BLK_OTAR OTAR; /**< \brief 4, Overlay Target Address Register */
+ Ifx_OVC_BLK_OMASK OMASK; /**< \brief 8, Overlay Mask Register */
+} Ifx_OVC_BLK;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Ovc_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief OVC object */
+typedef volatile struct _Ifx_OVC
+{
+ Ifx_OVC_OSEL OSEL; /**< \brief 0, Overlay Range Select Register */
+ unsigned char reserved_4[12]; /**< \brief 4, \internal Reserved */
+ Ifx_OVC_BLK BLK[32]; /**< \brief 10, Overlay blocks objects */
+ unsigned char reserved_190[112]; /**< \brief 190, \internal Reserved */
+} Ifx_OVC;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXOVC_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPmu_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPmu_bf.h
new file mode 100644
index 0000000..f0c5ad7
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPmu_bf.h
@@ -0,0 +1,63 @@
+/**
+ * \file IfxPmu_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Pmu_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Pmu
+ *
+ */
+#ifndef IFXPMU_BF_H
+#define IFXPMU_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Pmu_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_PMU_ID_Bits.MODNUMBER */
+#define IFX_PMU_ID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_PMU_ID_Bits.MODNUMBER */
+#define IFX_PMU_ID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_PMU_ID_Bits.MODNUMBER */
+#define IFX_PMU_ID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_PMU_ID_Bits.MODREV */
+#define IFX_PMU_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_PMU_ID_Bits.MODREV */
+#define IFX_PMU_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_PMU_ID_Bits.MODREV */
+#define IFX_PMU_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_PMU_ID_Bits.MODTYPE */
+#define IFX_PMU_ID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_PMU_ID_Bits.MODTYPE */
+#define IFX_PMU_ID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_PMU_ID_Bits.MODTYPE */
+#define IFX_PMU_ID_MODTYPE_OFF (8u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXPMU_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPmu_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPmu_reg.h
new file mode 100644
index 0000000..84f7519
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPmu_reg.h
@@ -0,0 +1,54 @@
+/**
+ * \file IfxPmu_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Pmu_Cfg Pmu address
+ * \ingroup IfxLld_Pmu
+ *
+ * \defgroup IfxLld_Pmu_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Pmu_Cfg
+ *
+ * \defgroup IfxLld_Pmu_Cfg_Pmu0 2-PMU0
+ * \ingroup IfxLld_Pmu_Cfg
+ *
+ */
+#ifndef IFXPMU_REG_H
+#define IFXPMU_REG_H 1
+/******************************************************************************/
+#include "IfxPmu_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Pmu_Cfg_BaseAddress
+ * \{ */
+
+/** \brief PMU object */
+#define MODULE_PMU0 /*lint --e(923)*/ (*(Ifx_PMU*)0xF8000500u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Pmu_Cfg_Pmu0
+ * \{ */
+
+/** \brief 8, PMU0 Identification Register */
+#define PMU0_ID /*lint --e(923)*/ (*(volatile Ifx_PMU_ID*)0xF8000508u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXPMU_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPmu_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPmu_regdef.h
new file mode 100644
index 0000000..53ff980
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPmu_regdef.h
@@ -0,0 +1,85 @@
+/**
+ * \file IfxPmu_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Pmu Pmu
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Pmu_Bitfields Bitfields
+ * \ingroup IfxLld_Pmu
+ *
+ * \defgroup IfxLld_Pmu_union Union
+ * \ingroup IfxLld_Pmu
+ *
+ * \defgroup IfxLld_Pmu_struct Struct
+ * \ingroup IfxLld_Pmu
+ *
+ */
+#ifndef IFXPMU_REGDEF_H
+#define IFXPMU_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Pmu_Bitfields
+ * \{ */
+
+/** \brief PMU0 Identification Register */
+typedef struct _Ifx_PMU_ID_Bits
+{
+ unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
+ unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_PMU_ID_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Pmu_union
+ * \{ */
+
+/** \brief PMU0 Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PMU_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_PMU_ID;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Pmu_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief PMU object */
+typedef volatile struct _Ifx_PMU
+{
+ unsigned char reserved_0[8]; /**< \brief 0, \internal Reserved */
+ Ifx_PMU_ID ID; /**< \brief 8, PMU0 Identification Register */
+ unsigned char reserved_C[245]; /**< \brief C, \internal Reserved */
+} Ifx_PMU;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXPMU_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPort_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPort_bf.h
new file mode 100644
index 0000000..6f1e623
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPort_bf.h
@@ -0,0 +1,2430 @@
+/**
+ * \file IfxPort_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Port_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Port
+ *
+ */
+#ifndef IFXPORT_BF_H
+#define IFXPORT_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN0 */
+#define IFX_P_ACCEN0_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN0 */
+#define IFX_P_ACCEN0_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN0 */
+#define IFX_P_ACCEN0_EN0_OFF (0u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN10 */
+#define IFX_P_ACCEN0_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN10 */
+#define IFX_P_ACCEN0_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN10 */
+#define IFX_P_ACCEN0_EN10_OFF (10u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN11 */
+#define IFX_P_ACCEN0_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN11 */
+#define IFX_P_ACCEN0_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN11 */
+#define IFX_P_ACCEN0_EN11_OFF (11u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN12 */
+#define IFX_P_ACCEN0_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN12 */
+#define IFX_P_ACCEN0_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN12 */
+#define IFX_P_ACCEN0_EN12_OFF (12u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN13 */
+#define IFX_P_ACCEN0_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN13 */
+#define IFX_P_ACCEN0_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN13 */
+#define IFX_P_ACCEN0_EN13_OFF (13u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN14 */
+#define IFX_P_ACCEN0_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN14 */
+#define IFX_P_ACCEN0_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN14 */
+#define IFX_P_ACCEN0_EN14_OFF (14u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN15 */
+#define IFX_P_ACCEN0_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN15 */
+#define IFX_P_ACCEN0_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN15 */
+#define IFX_P_ACCEN0_EN15_OFF (15u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN16 */
+#define IFX_P_ACCEN0_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN16 */
+#define IFX_P_ACCEN0_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN16 */
+#define IFX_P_ACCEN0_EN16_OFF (16u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN17 */
+#define IFX_P_ACCEN0_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN17 */
+#define IFX_P_ACCEN0_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN17 */
+#define IFX_P_ACCEN0_EN17_OFF (17u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN18 */
+#define IFX_P_ACCEN0_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN18 */
+#define IFX_P_ACCEN0_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN18 */
+#define IFX_P_ACCEN0_EN18_OFF (18u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN19 */
+#define IFX_P_ACCEN0_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN19 */
+#define IFX_P_ACCEN0_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN19 */
+#define IFX_P_ACCEN0_EN19_OFF (19u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN1 */
+#define IFX_P_ACCEN0_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN1 */
+#define IFX_P_ACCEN0_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN1 */
+#define IFX_P_ACCEN0_EN1_OFF (1u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN20 */
+#define IFX_P_ACCEN0_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN20 */
+#define IFX_P_ACCEN0_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN20 */
+#define IFX_P_ACCEN0_EN20_OFF (20u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN21 */
+#define IFX_P_ACCEN0_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN21 */
+#define IFX_P_ACCEN0_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN21 */
+#define IFX_P_ACCEN0_EN21_OFF (21u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN22 */
+#define IFX_P_ACCEN0_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN22 */
+#define IFX_P_ACCEN0_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN22 */
+#define IFX_P_ACCEN0_EN22_OFF (22u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN23 */
+#define IFX_P_ACCEN0_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN23 */
+#define IFX_P_ACCEN0_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN23 */
+#define IFX_P_ACCEN0_EN23_OFF (23u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN24 */
+#define IFX_P_ACCEN0_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN24 */
+#define IFX_P_ACCEN0_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN24 */
+#define IFX_P_ACCEN0_EN24_OFF (24u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN25 */
+#define IFX_P_ACCEN0_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN25 */
+#define IFX_P_ACCEN0_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN25 */
+#define IFX_P_ACCEN0_EN25_OFF (25u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN26 */
+#define IFX_P_ACCEN0_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN26 */
+#define IFX_P_ACCEN0_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN26 */
+#define IFX_P_ACCEN0_EN26_OFF (26u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN27 */
+#define IFX_P_ACCEN0_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN27 */
+#define IFX_P_ACCEN0_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN27 */
+#define IFX_P_ACCEN0_EN27_OFF (27u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN28 */
+#define IFX_P_ACCEN0_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN28 */
+#define IFX_P_ACCEN0_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN28 */
+#define IFX_P_ACCEN0_EN28_OFF (28u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN29 */
+#define IFX_P_ACCEN0_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN29 */
+#define IFX_P_ACCEN0_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN29 */
+#define IFX_P_ACCEN0_EN29_OFF (29u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN2 */
+#define IFX_P_ACCEN0_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN2 */
+#define IFX_P_ACCEN0_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN2 */
+#define IFX_P_ACCEN0_EN2_OFF (2u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN30 */
+#define IFX_P_ACCEN0_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN30 */
+#define IFX_P_ACCEN0_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN30 */
+#define IFX_P_ACCEN0_EN30_OFF (30u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN31 */
+#define IFX_P_ACCEN0_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN31 */
+#define IFX_P_ACCEN0_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN31 */
+#define IFX_P_ACCEN0_EN31_OFF (31u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN3 */
+#define IFX_P_ACCEN0_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN3 */
+#define IFX_P_ACCEN0_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN3 */
+#define IFX_P_ACCEN0_EN3_OFF (3u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN4 */
+#define IFX_P_ACCEN0_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN4 */
+#define IFX_P_ACCEN0_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN4 */
+#define IFX_P_ACCEN0_EN4_OFF (4u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN5 */
+#define IFX_P_ACCEN0_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN5 */
+#define IFX_P_ACCEN0_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN5 */
+#define IFX_P_ACCEN0_EN5_OFF (5u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN6 */
+#define IFX_P_ACCEN0_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN6 */
+#define IFX_P_ACCEN0_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN6 */
+#define IFX_P_ACCEN0_EN6_OFF (6u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN7 */
+#define IFX_P_ACCEN0_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN7 */
+#define IFX_P_ACCEN0_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN7 */
+#define IFX_P_ACCEN0_EN7_OFF (7u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN8 */
+#define IFX_P_ACCEN0_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN8 */
+#define IFX_P_ACCEN0_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN8 */
+#define IFX_P_ACCEN0_EN8_OFF (8u)
+
+/** \brief Length for Ifx_P_ACCEN0_Bits.EN9 */
+#define IFX_P_ACCEN0_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_P_ACCEN0_Bits.EN9 */
+#define IFX_P_ACCEN0_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ACCEN0_Bits.EN9 */
+#define IFX_P_ACCEN0_EN9_OFF (9u)
+
+/** \brief Length for Ifx_P_ESR_Bits.EN0 */
+#define IFX_P_ESR_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_P_ESR_Bits.EN0 */
+#define IFX_P_ESR_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ESR_Bits.EN0 */
+#define IFX_P_ESR_EN0_OFF (0u)
+
+/** \brief Length for Ifx_P_ESR_Bits.EN10 */
+#define IFX_P_ESR_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_P_ESR_Bits.EN10 */
+#define IFX_P_ESR_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ESR_Bits.EN10 */
+#define IFX_P_ESR_EN10_OFF (10u)
+
+/** \brief Length for Ifx_P_ESR_Bits.EN11 */
+#define IFX_P_ESR_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_P_ESR_Bits.EN11 */
+#define IFX_P_ESR_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ESR_Bits.EN11 */
+#define IFX_P_ESR_EN11_OFF (11u)
+
+/** \brief Length for Ifx_P_ESR_Bits.EN12 */
+#define IFX_P_ESR_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_P_ESR_Bits.EN12 */
+#define IFX_P_ESR_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ESR_Bits.EN12 */
+#define IFX_P_ESR_EN12_OFF (12u)
+
+/** \brief Length for Ifx_P_ESR_Bits.EN13 */
+#define IFX_P_ESR_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_P_ESR_Bits.EN13 */
+#define IFX_P_ESR_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ESR_Bits.EN13 */
+#define IFX_P_ESR_EN13_OFF (13u)
+
+/** \brief Length for Ifx_P_ESR_Bits.EN14 */
+#define IFX_P_ESR_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_P_ESR_Bits.EN14 */
+#define IFX_P_ESR_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ESR_Bits.EN14 */
+#define IFX_P_ESR_EN14_OFF (14u)
+
+/** \brief Length for Ifx_P_ESR_Bits.EN15 */
+#define IFX_P_ESR_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_P_ESR_Bits.EN15 */
+#define IFX_P_ESR_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ESR_Bits.EN15 */
+#define IFX_P_ESR_EN15_OFF (15u)
+
+/** \brief Length for Ifx_P_ESR_Bits.EN1 */
+#define IFX_P_ESR_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_P_ESR_Bits.EN1 */
+#define IFX_P_ESR_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ESR_Bits.EN1 */
+#define IFX_P_ESR_EN1_OFF (1u)
+
+/** \brief Length for Ifx_P_ESR_Bits.EN2 */
+#define IFX_P_ESR_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_P_ESR_Bits.EN2 */
+#define IFX_P_ESR_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ESR_Bits.EN2 */
+#define IFX_P_ESR_EN2_OFF (2u)
+
+/** \brief Length for Ifx_P_ESR_Bits.EN3 */
+#define IFX_P_ESR_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_P_ESR_Bits.EN3 */
+#define IFX_P_ESR_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ESR_Bits.EN3 */
+#define IFX_P_ESR_EN3_OFF (3u)
+
+/** \brief Length for Ifx_P_ESR_Bits.EN4 */
+#define IFX_P_ESR_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_P_ESR_Bits.EN4 */
+#define IFX_P_ESR_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ESR_Bits.EN4 */
+#define IFX_P_ESR_EN4_OFF (4u)
+
+/** \brief Length for Ifx_P_ESR_Bits.EN5 */
+#define IFX_P_ESR_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_P_ESR_Bits.EN5 */
+#define IFX_P_ESR_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ESR_Bits.EN5 */
+#define IFX_P_ESR_EN5_OFF (5u)
+
+/** \brief Length for Ifx_P_ESR_Bits.EN6 */
+#define IFX_P_ESR_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_P_ESR_Bits.EN6 */
+#define IFX_P_ESR_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ESR_Bits.EN6 */
+#define IFX_P_ESR_EN6_OFF (6u)
+
+/** \brief Length for Ifx_P_ESR_Bits.EN7 */
+#define IFX_P_ESR_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_P_ESR_Bits.EN7 */
+#define IFX_P_ESR_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ESR_Bits.EN7 */
+#define IFX_P_ESR_EN7_OFF (7u)
+
+/** \brief Length for Ifx_P_ESR_Bits.EN8 */
+#define IFX_P_ESR_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_P_ESR_Bits.EN8 */
+#define IFX_P_ESR_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ESR_Bits.EN8 */
+#define IFX_P_ESR_EN8_OFF (8u)
+
+/** \brief Length for Ifx_P_ESR_Bits.EN9 */
+#define IFX_P_ESR_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_P_ESR_Bits.EN9 */
+#define IFX_P_ESR_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_ESR_Bits.EN9 */
+#define IFX_P_ESR_EN9_OFF (9u)
+
+/** \brief Length for Ifx_P_ID_Bits.MODNUMBER */
+#define IFX_P_ID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_P_ID_Bits.MODNUMBER */
+#define IFX_P_ID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_P_ID_Bits.MODNUMBER */
+#define IFX_P_ID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_P_ID_Bits.MODREV */
+#define IFX_P_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_P_ID_Bits.MODREV */
+#define IFX_P_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_P_ID_Bits.MODREV */
+#define IFX_P_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_P_ID_Bits.MODTYPE */
+#define IFX_P_ID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_P_ID_Bits.MODTYPE */
+#define IFX_P_ID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_P_ID_Bits.MODTYPE */
+#define IFX_P_ID_MODTYPE_OFF (8u)
+
+/** \brief Length for Ifx_P_IN_Bits.P0 */
+#define IFX_P_IN_P0_LEN (1u)
+
+/** \brief Mask for Ifx_P_IN_Bits.P0 */
+#define IFX_P_IN_P0_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_IN_Bits.P0 */
+#define IFX_P_IN_P0_OFF (0u)
+
+/** \brief Length for Ifx_P_IN_Bits.P10 */
+#define IFX_P_IN_P10_LEN (1u)
+
+/** \brief Mask for Ifx_P_IN_Bits.P10 */
+#define IFX_P_IN_P10_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_IN_Bits.P10 */
+#define IFX_P_IN_P10_OFF (10u)
+
+/** \brief Length for Ifx_P_IN_Bits.P11 */
+#define IFX_P_IN_P11_LEN (1u)
+
+/** \brief Mask for Ifx_P_IN_Bits.P11 */
+#define IFX_P_IN_P11_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_IN_Bits.P11 */
+#define IFX_P_IN_P11_OFF (11u)
+
+/** \brief Length for Ifx_P_IN_Bits.P12 */
+#define IFX_P_IN_P12_LEN (1u)
+
+/** \brief Mask for Ifx_P_IN_Bits.P12 */
+#define IFX_P_IN_P12_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_IN_Bits.P12 */
+#define IFX_P_IN_P12_OFF (12u)
+
+/** \brief Length for Ifx_P_IN_Bits.P13 */
+#define IFX_P_IN_P13_LEN (1u)
+
+/** \brief Mask for Ifx_P_IN_Bits.P13 */
+#define IFX_P_IN_P13_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_IN_Bits.P13 */
+#define IFX_P_IN_P13_OFF (13u)
+
+/** \brief Length for Ifx_P_IN_Bits.P14 */
+#define IFX_P_IN_P14_LEN (1u)
+
+/** \brief Mask for Ifx_P_IN_Bits.P14 */
+#define IFX_P_IN_P14_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_IN_Bits.P14 */
+#define IFX_P_IN_P14_OFF (14u)
+
+/** \brief Length for Ifx_P_IN_Bits.P15 */
+#define IFX_P_IN_P15_LEN (1u)
+
+/** \brief Mask for Ifx_P_IN_Bits.P15 */
+#define IFX_P_IN_P15_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_IN_Bits.P15 */
+#define IFX_P_IN_P15_OFF (15u)
+
+/** \brief Length for Ifx_P_IN_Bits.P1 */
+#define IFX_P_IN_P1_LEN (1u)
+
+/** \brief Mask for Ifx_P_IN_Bits.P1 */
+#define IFX_P_IN_P1_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_IN_Bits.P1 */
+#define IFX_P_IN_P1_OFF (1u)
+
+/** \brief Length for Ifx_P_IN_Bits.P2 */
+#define IFX_P_IN_P2_LEN (1u)
+
+/** \brief Mask for Ifx_P_IN_Bits.P2 */
+#define IFX_P_IN_P2_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_IN_Bits.P2 */
+#define IFX_P_IN_P2_OFF (2u)
+
+/** \brief Length for Ifx_P_IN_Bits.P3 */
+#define IFX_P_IN_P3_LEN (1u)
+
+/** \brief Mask for Ifx_P_IN_Bits.P3 */
+#define IFX_P_IN_P3_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_IN_Bits.P3 */
+#define IFX_P_IN_P3_OFF (3u)
+
+/** \brief Length for Ifx_P_IN_Bits.P4 */
+#define IFX_P_IN_P4_LEN (1u)
+
+/** \brief Mask for Ifx_P_IN_Bits.P4 */
+#define IFX_P_IN_P4_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_IN_Bits.P4 */
+#define IFX_P_IN_P4_OFF (4u)
+
+/** \brief Length for Ifx_P_IN_Bits.P5 */
+#define IFX_P_IN_P5_LEN (1u)
+
+/** \brief Mask for Ifx_P_IN_Bits.P5 */
+#define IFX_P_IN_P5_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_IN_Bits.P5 */
+#define IFX_P_IN_P5_OFF (5u)
+
+/** \brief Length for Ifx_P_IN_Bits.P6 */
+#define IFX_P_IN_P6_LEN (1u)
+
+/** \brief Mask for Ifx_P_IN_Bits.P6 */
+#define IFX_P_IN_P6_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_IN_Bits.P6 */
+#define IFX_P_IN_P6_OFF (6u)
+
+/** \brief Length for Ifx_P_IN_Bits.P7 */
+#define IFX_P_IN_P7_LEN (1u)
+
+/** \brief Mask for Ifx_P_IN_Bits.P7 */
+#define IFX_P_IN_P7_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_IN_Bits.P7 */
+#define IFX_P_IN_P7_OFF (7u)
+
+/** \brief Length for Ifx_P_IN_Bits.P8 */
+#define IFX_P_IN_P8_LEN (1u)
+
+/** \brief Mask for Ifx_P_IN_Bits.P8 */
+#define IFX_P_IN_P8_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_IN_Bits.P8 */
+#define IFX_P_IN_P8_OFF (8u)
+
+/** \brief Length for Ifx_P_IN_Bits.P9 */
+#define IFX_P_IN_P9_LEN (1u)
+
+/** \brief Mask for Ifx_P_IN_Bits.P9 */
+#define IFX_P_IN_P9_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_IN_Bits.P9 */
+#define IFX_P_IN_P9_OFF (9u)
+
+/** \brief Length for Ifx_P_IOCR0_Bits.PC0 */
+#define IFX_P_IOCR0_PC0_LEN (5u)
+
+/** \brief Mask for Ifx_P_IOCR0_Bits.PC0 */
+#define IFX_P_IOCR0_PC0_MSK (0x1fu)
+
+/** \brief Offset for Ifx_P_IOCR0_Bits.PC0 */
+#define IFX_P_IOCR0_PC0_OFF (3u)
+
+/** \brief Length for Ifx_P_IOCR0_Bits.PC1 */
+#define IFX_P_IOCR0_PC1_LEN (5u)
+
+/** \brief Mask for Ifx_P_IOCR0_Bits.PC1 */
+#define IFX_P_IOCR0_PC1_MSK (0x1fu)
+
+/** \brief Offset for Ifx_P_IOCR0_Bits.PC1 */
+#define IFX_P_IOCR0_PC1_OFF (11u)
+
+/** \brief Length for Ifx_P_IOCR0_Bits.PC2 */
+#define IFX_P_IOCR0_PC2_LEN (5u)
+
+/** \brief Mask for Ifx_P_IOCR0_Bits.PC2 */
+#define IFX_P_IOCR0_PC2_MSK (0x1fu)
+
+/** \brief Offset for Ifx_P_IOCR0_Bits.PC2 */
+#define IFX_P_IOCR0_PC2_OFF (19u)
+
+/** \brief Length for Ifx_P_IOCR0_Bits.PC3 */
+#define IFX_P_IOCR0_PC3_LEN (5u)
+
+/** \brief Mask for Ifx_P_IOCR0_Bits.PC3 */
+#define IFX_P_IOCR0_PC3_MSK (0x1fu)
+
+/** \brief Offset for Ifx_P_IOCR0_Bits.PC3 */
+#define IFX_P_IOCR0_PC3_OFF (27u)
+
+/** \brief Length for Ifx_P_IOCR12_Bits.PC12 */
+#define IFX_P_IOCR12_PC12_LEN (5u)
+
+/** \brief Mask for Ifx_P_IOCR12_Bits.PC12 */
+#define IFX_P_IOCR12_PC12_MSK (0x1fu)
+
+/** \brief Offset for Ifx_P_IOCR12_Bits.PC12 */
+#define IFX_P_IOCR12_PC12_OFF (3u)
+
+/** \brief Length for Ifx_P_IOCR12_Bits.PC13 */
+#define IFX_P_IOCR12_PC13_LEN (5u)
+
+/** \brief Mask for Ifx_P_IOCR12_Bits.PC13 */
+#define IFX_P_IOCR12_PC13_MSK (0x1fu)
+
+/** \brief Offset for Ifx_P_IOCR12_Bits.PC13 */
+#define IFX_P_IOCR12_PC13_OFF (11u)
+
+/** \brief Length for Ifx_P_IOCR12_Bits.PC14 */
+#define IFX_P_IOCR12_PC14_LEN (5u)
+
+/** \brief Mask for Ifx_P_IOCR12_Bits.PC14 */
+#define IFX_P_IOCR12_PC14_MSK (0x1fu)
+
+/** \brief Offset for Ifx_P_IOCR12_Bits.PC14 */
+#define IFX_P_IOCR12_PC14_OFF (19u)
+
+/** \brief Length for Ifx_P_IOCR12_Bits.PC15 */
+#define IFX_P_IOCR12_PC15_LEN (5u)
+
+/** \brief Mask for Ifx_P_IOCR12_Bits.PC15 */
+#define IFX_P_IOCR12_PC15_MSK (0x1fu)
+
+/** \brief Offset for Ifx_P_IOCR12_Bits.PC15 */
+#define IFX_P_IOCR12_PC15_OFF (27u)
+
+/** \brief Length for Ifx_P_IOCR4_Bits.PC4 */
+#define IFX_P_IOCR4_PC4_LEN (5u)
+
+/** \brief Mask for Ifx_P_IOCR4_Bits.PC4 */
+#define IFX_P_IOCR4_PC4_MSK (0x1fu)
+
+/** \brief Offset for Ifx_P_IOCR4_Bits.PC4 */
+#define IFX_P_IOCR4_PC4_OFF (3u)
+
+/** \brief Length for Ifx_P_IOCR4_Bits.PC5 */
+#define IFX_P_IOCR4_PC5_LEN (5u)
+
+/** \brief Mask for Ifx_P_IOCR4_Bits.PC5 */
+#define IFX_P_IOCR4_PC5_MSK (0x1fu)
+
+/** \brief Offset for Ifx_P_IOCR4_Bits.PC5 */
+#define IFX_P_IOCR4_PC5_OFF (11u)
+
+/** \brief Length for Ifx_P_IOCR4_Bits.PC6 */
+#define IFX_P_IOCR4_PC6_LEN (5u)
+
+/** \brief Mask for Ifx_P_IOCR4_Bits.PC6 */
+#define IFX_P_IOCR4_PC6_MSK (0x1fu)
+
+/** \brief Offset for Ifx_P_IOCR4_Bits.PC6 */
+#define IFX_P_IOCR4_PC6_OFF (19u)
+
+/** \brief Length for Ifx_P_IOCR4_Bits.PC7 */
+#define IFX_P_IOCR4_PC7_LEN (5u)
+
+/** \brief Mask for Ifx_P_IOCR4_Bits.PC7 */
+#define IFX_P_IOCR4_PC7_MSK (0x1fu)
+
+/** \brief Offset for Ifx_P_IOCR4_Bits.PC7 */
+#define IFX_P_IOCR4_PC7_OFF (27u)
+
+/** \brief Length for Ifx_P_IOCR8_Bits.PC10 */
+#define IFX_P_IOCR8_PC10_LEN (5u)
+
+/** \brief Mask for Ifx_P_IOCR8_Bits.PC10 */
+#define IFX_P_IOCR8_PC10_MSK (0x1fu)
+
+/** \brief Offset for Ifx_P_IOCR8_Bits.PC10 */
+#define IFX_P_IOCR8_PC10_OFF (19u)
+
+/** \brief Length for Ifx_P_IOCR8_Bits.PC11 */
+#define IFX_P_IOCR8_PC11_LEN (5u)
+
+/** \brief Mask for Ifx_P_IOCR8_Bits.PC11 */
+#define IFX_P_IOCR8_PC11_MSK (0x1fu)
+
+/** \brief Offset for Ifx_P_IOCR8_Bits.PC11 */
+#define IFX_P_IOCR8_PC11_OFF (27u)
+
+/** \brief Length for Ifx_P_IOCR8_Bits.PC8 */
+#define IFX_P_IOCR8_PC8_LEN (5u)
+
+/** \brief Mask for Ifx_P_IOCR8_Bits.PC8 */
+#define IFX_P_IOCR8_PC8_MSK (0x1fu)
+
+/** \brief Offset for Ifx_P_IOCR8_Bits.PC8 */
+#define IFX_P_IOCR8_PC8_OFF (3u)
+
+/** \brief Length for Ifx_P_IOCR8_Bits.PC9 */
+#define IFX_P_IOCR8_PC9_LEN (5u)
+
+/** \brief Mask for Ifx_P_IOCR8_Bits.PC9 */
+#define IFX_P_IOCR8_PC9_MSK (0x1fu)
+
+/** \brief Offset for Ifx_P_IOCR8_Bits.PC9 */
+#define IFX_P_IOCR8_PC9_OFF (11u)
+
+/** \brief Length for Ifx_P_LPCR0_Bits.PS1 */
+#define IFX_P_LPCR0_PS1_LEN (1u)
+
+/** \brief Mask for Ifx_P_LPCR0_Bits.PS1 */
+#define IFX_P_LPCR0_PS1_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_LPCR0_Bits.PS1 */
+#define IFX_P_LPCR0_PS1_OFF (1u)
+
+/** \brief Length for Ifx_P_LPCR1_P21_Bits.LRXTERM */
+#define IFX_P_LPCR1_P21_LRXTERM_LEN (5u)
+
+/** \brief Mask for Ifx_P_LPCR1_P21_Bits.LRXTERM */
+#define IFX_P_LPCR1_P21_LRXTERM_MSK (0x1fu)
+
+/** \brief Offset for Ifx_P_LPCR1_P21_Bits.LRXTERM */
+#define IFX_P_LPCR1_P21_LRXTERM_OFF (3u)
+
+/** \brief Length for Ifx_P_LPCR1_P21_Bits.RDIS_CTRL */
+#define IFX_P_LPCR1_P21_RDIS_CTRL_LEN (1u)
+
+/** \brief Mask for Ifx_P_LPCR1_P21_Bits.RDIS_CTRL */
+#define IFX_P_LPCR1_P21_RDIS_CTRL_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_LPCR1_P21_Bits.RDIS_CTRL */
+#define IFX_P_LPCR1_P21_RDIS_CTRL_OFF (0u)
+
+/** \brief Length for Ifx_P_LPCR1_P21_Bits.RX_DIS */
+#define IFX_P_LPCR1_P21_RX_DIS_LEN (1u)
+
+/** \brief Mask for Ifx_P_LPCR1_P21_Bits.RX_DIS */
+#define IFX_P_LPCR1_P21_RX_DIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_LPCR1_P21_Bits.RX_DIS */
+#define IFX_P_LPCR1_P21_RX_DIS_OFF (1u)
+
+/** \brief Length for Ifx_P_LPCR1_P21_Bits.TERM */
+#define IFX_P_LPCR1_P21_TERM_LEN (1u)
+
+/** \brief Mask for Ifx_P_LPCR1_P21_Bits.TERM */
+#define IFX_P_LPCR1_P21_TERM_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_LPCR1_P21_Bits.TERM */
+#define IFX_P_LPCR1_P21_TERM_OFF (2u)
+
+/** \brief Length for Ifx_P_LPCR1_Bits.PS1 */
+#define IFX_P_LPCR1_PS1_LEN (1u)
+
+/** \brief Mask for Ifx_P_LPCR1_Bits.PS1 */
+#define IFX_P_LPCR1_PS1_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_LPCR1_Bits.PS1 */
+#define IFX_P_LPCR1_PS1_OFF (1u)
+
+/** \brief Length for Ifx_P_LPCR2_Bits.LVDSR */
+#define IFX_P_LPCR2_LVDSR_LEN (1u)
+
+/** \brief Mask for Ifx_P_LPCR2_Bits.LVDSR */
+#define IFX_P_LPCR2_LVDSR_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_LPCR2_Bits.LVDSR */
+#define IFX_P_LPCR2_LVDSR_OFF (8u)
+
+/** \brief Length for Ifx_P_LPCR2_Bits.LVDSRL */
+#define IFX_P_LPCR2_LVDSRL_LEN (1u)
+
+/** \brief Mask for Ifx_P_LPCR2_Bits.LVDSRL */
+#define IFX_P_LPCR2_LVDSRL_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_LPCR2_Bits.LVDSRL */
+#define IFX_P_LPCR2_LVDSRL_OFF (9u)
+
+/** \brief Length for Ifx_P_LPCR2_Bits.TDIS_CTRL */
+#define IFX_P_LPCR2_TDIS_CTRL_LEN (1u)
+
+/** \brief Mask for Ifx_P_LPCR2_Bits.TDIS_CTRL */
+#define IFX_P_LPCR2_TDIS_CTRL_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_LPCR2_Bits.TDIS_CTRL */
+#define IFX_P_LPCR2_TDIS_CTRL_OFF (12u)
+
+/** \brief Length for Ifx_P_LPCR2_Bits.TX_DIS */
+#define IFX_P_LPCR2_TX_DIS_LEN (1u)
+
+/** \brief Mask for Ifx_P_LPCR2_Bits.TX_DIS */
+#define IFX_P_LPCR2_TX_DIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_LPCR2_Bits.TX_DIS */
+#define IFX_P_LPCR2_TX_DIS_OFF (13u)
+
+/** \brief Length for Ifx_P_LPCR2_Bits.TX_PD */
+#define IFX_P_LPCR2_TX_PD_LEN (1u)
+
+/** \brief Mask for Ifx_P_LPCR2_Bits.TX_PD */
+#define IFX_P_LPCR2_TX_PD_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_LPCR2_Bits.TX_PD */
+#define IFX_P_LPCR2_TX_PD_OFF (14u)
+
+/** \brief Length for Ifx_P_LPCR2_Bits.TX_PWDPD */
+#define IFX_P_LPCR2_TX_PWDPD_LEN (1u)
+
+/** \brief Mask for Ifx_P_LPCR2_Bits.TX_PWDPD */
+#define IFX_P_LPCR2_TX_PWDPD_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_LPCR2_Bits.TX_PWDPD */
+#define IFX_P_LPCR2_TX_PWDPD_OFF (15u)
+
+/** \brief Length for Ifx_P_OMCR0_Bits.PCL0 */
+#define IFX_P_OMCR0_PCL0_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR0_Bits.PCL0 */
+#define IFX_P_OMCR0_PCL0_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR0_Bits.PCL0 */
+#define IFX_P_OMCR0_PCL0_OFF (16u)
+
+/** \brief Length for Ifx_P_OMCR0_Bits.PCL1 */
+#define IFX_P_OMCR0_PCL1_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR0_Bits.PCL1 */
+#define IFX_P_OMCR0_PCL1_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR0_Bits.PCL1 */
+#define IFX_P_OMCR0_PCL1_OFF (17u)
+
+/** \brief Length for Ifx_P_OMCR0_Bits.PCL2 */
+#define IFX_P_OMCR0_PCL2_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR0_Bits.PCL2 */
+#define IFX_P_OMCR0_PCL2_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR0_Bits.PCL2 */
+#define IFX_P_OMCR0_PCL2_OFF (18u)
+
+/** \brief Length for Ifx_P_OMCR0_Bits.PCL3 */
+#define IFX_P_OMCR0_PCL3_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR0_Bits.PCL3 */
+#define IFX_P_OMCR0_PCL3_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR0_Bits.PCL3 */
+#define IFX_P_OMCR0_PCL3_OFF (19u)
+
+/** \brief Length for Ifx_P_OMCR12_Bits.PCL12 */
+#define IFX_P_OMCR12_PCL12_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR12_Bits.PCL12 */
+#define IFX_P_OMCR12_PCL12_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR12_Bits.PCL12 */
+#define IFX_P_OMCR12_PCL12_OFF (28u)
+
+/** \brief Length for Ifx_P_OMCR12_Bits.PCL13 */
+#define IFX_P_OMCR12_PCL13_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR12_Bits.PCL13 */
+#define IFX_P_OMCR12_PCL13_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR12_Bits.PCL13 */
+#define IFX_P_OMCR12_PCL13_OFF (29u)
+
+/** \brief Length for Ifx_P_OMCR12_Bits.PCL14 */
+#define IFX_P_OMCR12_PCL14_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR12_Bits.PCL14 */
+#define IFX_P_OMCR12_PCL14_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR12_Bits.PCL14 */
+#define IFX_P_OMCR12_PCL14_OFF (30u)
+
+/** \brief Length for Ifx_P_OMCR12_Bits.PCL15 */
+#define IFX_P_OMCR12_PCL15_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR12_Bits.PCL15 */
+#define IFX_P_OMCR12_PCL15_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR12_Bits.PCL15 */
+#define IFX_P_OMCR12_PCL15_OFF (31u)
+
+/** \brief Length for Ifx_P_OMCR4_Bits.PCL4 */
+#define IFX_P_OMCR4_PCL4_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR4_Bits.PCL4 */
+#define IFX_P_OMCR4_PCL4_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR4_Bits.PCL4 */
+#define IFX_P_OMCR4_PCL4_OFF (20u)
+
+/** \brief Length for Ifx_P_OMCR4_Bits.PCL5 */
+#define IFX_P_OMCR4_PCL5_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR4_Bits.PCL5 */
+#define IFX_P_OMCR4_PCL5_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR4_Bits.PCL5 */
+#define IFX_P_OMCR4_PCL5_OFF (21u)
+
+/** \brief Length for Ifx_P_OMCR4_Bits.PCL6 */
+#define IFX_P_OMCR4_PCL6_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR4_Bits.PCL6 */
+#define IFX_P_OMCR4_PCL6_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR4_Bits.PCL6 */
+#define IFX_P_OMCR4_PCL6_OFF (22u)
+
+/** \brief Length for Ifx_P_OMCR4_Bits.PCL7 */
+#define IFX_P_OMCR4_PCL7_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR4_Bits.PCL7 */
+#define IFX_P_OMCR4_PCL7_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR4_Bits.PCL7 */
+#define IFX_P_OMCR4_PCL7_OFF (23u)
+
+/** \brief Length for Ifx_P_OMCR8_Bits.PCL10 */
+#define IFX_P_OMCR8_PCL10_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR8_Bits.PCL10 */
+#define IFX_P_OMCR8_PCL10_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR8_Bits.PCL10 */
+#define IFX_P_OMCR8_PCL10_OFF (26u)
+
+/** \brief Length for Ifx_P_OMCR8_Bits.PCL11 */
+#define IFX_P_OMCR8_PCL11_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR8_Bits.PCL11 */
+#define IFX_P_OMCR8_PCL11_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR8_Bits.PCL11 */
+#define IFX_P_OMCR8_PCL11_OFF (27u)
+
+/** \brief Length for Ifx_P_OMCR8_Bits.PCL8 */
+#define IFX_P_OMCR8_PCL8_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR8_Bits.PCL8 */
+#define IFX_P_OMCR8_PCL8_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR8_Bits.PCL8 */
+#define IFX_P_OMCR8_PCL8_OFF (24u)
+
+/** \brief Length for Ifx_P_OMCR8_Bits.PCL9 */
+#define IFX_P_OMCR8_PCL9_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR8_Bits.PCL9 */
+#define IFX_P_OMCR8_PCL9_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR8_Bits.PCL9 */
+#define IFX_P_OMCR8_PCL9_OFF (25u)
+
+/** \brief Length for Ifx_P_OMCR_Bits.PCL0 */
+#define IFX_P_OMCR_PCL0_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR_Bits.PCL0 */
+#define IFX_P_OMCR_PCL0_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR_Bits.PCL0 */
+#define IFX_P_OMCR_PCL0_OFF (16u)
+
+/** \brief Length for Ifx_P_OMCR_Bits.PCL10 */
+#define IFX_P_OMCR_PCL10_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR_Bits.PCL10 */
+#define IFX_P_OMCR_PCL10_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR_Bits.PCL10 */
+#define IFX_P_OMCR_PCL10_OFF (26u)
+
+/** \brief Length for Ifx_P_OMCR_Bits.PCL11 */
+#define IFX_P_OMCR_PCL11_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR_Bits.PCL11 */
+#define IFX_P_OMCR_PCL11_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR_Bits.PCL11 */
+#define IFX_P_OMCR_PCL11_OFF (27u)
+
+/** \brief Length for Ifx_P_OMCR_Bits.PCL12 */
+#define IFX_P_OMCR_PCL12_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR_Bits.PCL12 */
+#define IFX_P_OMCR_PCL12_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR_Bits.PCL12 */
+#define IFX_P_OMCR_PCL12_OFF (28u)
+
+/** \brief Length for Ifx_P_OMCR_Bits.PCL13 */
+#define IFX_P_OMCR_PCL13_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR_Bits.PCL13 */
+#define IFX_P_OMCR_PCL13_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR_Bits.PCL13 */
+#define IFX_P_OMCR_PCL13_OFF (29u)
+
+/** \brief Length for Ifx_P_OMCR_Bits.PCL14 */
+#define IFX_P_OMCR_PCL14_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR_Bits.PCL14 */
+#define IFX_P_OMCR_PCL14_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR_Bits.PCL14 */
+#define IFX_P_OMCR_PCL14_OFF (30u)
+
+/** \brief Length for Ifx_P_OMCR_Bits.PCL15 */
+#define IFX_P_OMCR_PCL15_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR_Bits.PCL15 */
+#define IFX_P_OMCR_PCL15_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR_Bits.PCL15 */
+#define IFX_P_OMCR_PCL15_OFF (31u)
+
+/** \brief Length for Ifx_P_OMCR_Bits.PCL1 */
+#define IFX_P_OMCR_PCL1_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR_Bits.PCL1 */
+#define IFX_P_OMCR_PCL1_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR_Bits.PCL1 */
+#define IFX_P_OMCR_PCL1_OFF (17u)
+
+/** \brief Length for Ifx_P_OMCR_Bits.PCL2 */
+#define IFX_P_OMCR_PCL2_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR_Bits.PCL2 */
+#define IFX_P_OMCR_PCL2_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR_Bits.PCL2 */
+#define IFX_P_OMCR_PCL2_OFF (18u)
+
+/** \brief Length for Ifx_P_OMCR_Bits.PCL3 */
+#define IFX_P_OMCR_PCL3_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR_Bits.PCL3 */
+#define IFX_P_OMCR_PCL3_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR_Bits.PCL3 */
+#define IFX_P_OMCR_PCL3_OFF (19u)
+
+/** \brief Length for Ifx_P_OMCR_Bits.PCL4 */
+#define IFX_P_OMCR_PCL4_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR_Bits.PCL4 */
+#define IFX_P_OMCR_PCL4_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR_Bits.PCL4 */
+#define IFX_P_OMCR_PCL4_OFF (20u)
+
+/** \brief Length for Ifx_P_OMCR_Bits.PCL5 */
+#define IFX_P_OMCR_PCL5_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR_Bits.PCL5 */
+#define IFX_P_OMCR_PCL5_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR_Bits.PCL5 */
+#define IFX_P_OMCR_PCL5_OFF (21u)
+
+/** \brief Length for Ifx_P_OMCR_Bits.PCL6 */
+#define IFX_P_OMCR_PCL6_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR_Bits.PCL6 */
+#define IFX_P_OMCR_PCL6_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR_Bits.PCL6 */
+#define IFX_P_OMCR_PCL6_OFF (22u)
+
+/** \brief Length for Ifx_P_OMCR_Bits.PCL7 */
+#define IFX_P_OMCR_PCL7_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR_Bits.PCL7 */
+#define IFX_P_OMCR_PCL7_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR_Bits.PCL7 */
+#define IFX_P_OMCR_PCL7_OFF (23u)
+
+/** \brief Length for Ifx_P_OMCR_Bits.PCL8 */
+#define IFX_P_OMCR_PCL8_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR_Bits.PCL8 */
+#define IFX_P_OMCR_PCL8_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR_Bits.PCL8 */
+#define IFX_P_OMCR_PCL8_OFF (24u)
+
+/** \brief Length for Ifx_P_OMCR_Bits.PCL9 */
+#define IFX_P_OMCR_PCL9_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMCR_Bits.PCL9 */
+#define IFX_P_OMCR_PCL9_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMCR_Bits.PCL9 */
+#define IFX_P_OMCR_PCL9_OFF (25u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PCL0 */
+#define IFX_P_OMR_PCL0_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PCL0 */
+#define IFX_P_OMR_PCL0_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PCL0 */
+#define IFX_P_OMR_PCL0_OFF (16u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PCL10 */
+#define IFX_P_OMR_PCL10_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PCL10 */
+#define IFX_P_OMR_PCL10_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PCL10 */
+#define IFX_P_OMR_PCL10_OFF (26u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PCL11 */
+#define IFX_P_OMR_PCL11_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PCL11 */
+#define IFX_P_OMR_PCL11_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PCL11 */
+#define IFX_P_OMR_PCL11_OFF (27u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PCL12 */
+#define IFX_P_OMR_PCL12_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PCL12 */
+#define IFX_P_OMR_PCL12_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PCL12 */
+#define IFX_P_OMR_PCL12_OFF (28u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PCL13 */
+#define IFX_P_OMR_PCL13_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PCL13 */
+#define IFX_P_OMR_PCL13_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PCL13 */
+#define IFX_P_OMR_PCL13_OFF (29u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PCL14 */
+#define IFX_P_OMR_PCL14_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PCL14 */
+#define IFX_P_OMR_PCL14_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PCL14 */
+#define IFX_P_OMR_PCL14_OFF (30u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PCL15 */
+#define IFX_P_OMR_PCL15_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PCL15 */
+#define IFX_P_OMR_PCL15_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PCL15 */
+#define IFX_P_OMR_PCL15_OFF (31u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PCL1 */
+#define IFX_P_OMR_PCL1_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PCL1 */
+#define IFX_P_OMR_PCL1_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PCL1 */
+#define IFX_P_OMR_PCL1_OFF (17u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PCL2 */
+#define IFX_P_OMR_PCL2_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PCL2 */
+#define IFX_P_OMR_PCL2_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PCL2 */
+#define IFX_P_OMR_PCL2_OFF (18u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PCL3 */
+#define IFX_P_OMR_PCL3_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PCL3 */
+#define IFX_P_OMR_PCL3_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PCL3 */
+#define IFX_P_OMR_PCL3_OFF (19u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PCL4 */
+#define IFX_P_OMR_PCL4_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PCL4 */
+#define IFX_P_OMR_PCL4_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PCL4 */
+#define IFX_P_OMR_PCL4_OFF (20u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PCL5 */
+#define IFX_P_OMR_PCL5_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PCL5 */
+#define IFX_P_OMR_PCL5_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PCL5 */
+#define IFX_P_OMR_PCL5_OFF (21u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PCL6 */
+#define IFX_P_OMR_PCL6_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PCL6 */
+#define IFX_P_OMR_PCL6_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PCL6 */
+#define IFX_P_OMR_PCL6_OFF (22u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PCL7 */
+#define IFX_P_OMR_PCL7_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PCL7 */
+#define IFX_P_OMR_PCL7_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PCL7 */
+#define IFX_P_OMR_PCL7_OFF (23u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PCL8 */
+#define IFX_P_OMR_PCL8_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PCL8 */
+#define IFX_P_OMR_PCL8_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PCL8 */
+#define IFX_P_OMR_PCL8_OFF (24u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PCL9 */
+#define IFX_P_OMR_PCL9_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PCL9 */
+#define IFX_P_OMR_PCL9_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PCL9 */
+#define IFX_P_OMR_PCL9_OFF (25u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PS0 */
+#define IFX_P_OMR_PS0_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PS0 */
+#define IFX_P_OMR_PS0_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PS0 */
+#define IFX_P_OMR_PS0_OFF (0u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PS10 */
+#define IFX_P_OMR_PS10_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PS10 */
+#define IFX_P_OMR_PS10_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PS10 */
+#define IFX_P_OMR_PS10_OFF (10u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PS11 */
+#define IFX_P_OMR_PS11_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PS11 */
+#define IFX_P_OMR_PS11_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PS11 */
+#define IFX_P_OMR_PS11_OFF (11u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PS12 */
+#define IFX_P_OMR_PS12_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PS12 */
+#define IFX_P_OMR_PS12_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PS12 */
+#define IFX_P_OMR_PS12_OFF (12u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PS13 */
+#define IFX_P_OMR_PS13_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PS13 */
+#define IFX_P_OMR_PS13_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PS13 */
+#define IFX_P_OMR_PS13_OFF (13u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PS14 */
+#define IFX_P_OMR_PS14_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PS14 */
+#define IFX_P_OMR_PS14_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PS14 */
+#define IFX_P_OMR_PS14_OFF (14u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PS15 */
+#define IFX_P_OMR_PS15_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PS15 */
+#define IFX_P_OMR_PS15_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PS15 */
+#define IFX_P_OMR_PS15_OFF (15u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PS1 */
+#define IFX_P_OMR_PS1_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PS1 */
+#define IFX_P_OMR_PS1_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PS1 */
+#define IFX_P_OMR_PS1_OFF (1u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PS2 */
+#define IFX_P_OMR_PS2_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PS2 */
+#define IFX_P_OMR_PS2_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PS2 */
+#define IFX_P_OMR_PS2_OFF (2u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PS3 */
+#define IFX_P_OMR_PS3_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PS3 */
+#define IFX_P_OMR_PS3_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PS3 */
+#define IFX_P_OMR_PS3_OFF (3u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PS4 */
+#define IFX_P_OMR_PS4_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PS4 */
+#define IFX_P_OMR_PS4_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PS4 */
+#define IFX_P_OMR_PS4_OFF (4u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PS5 */
+#define IFX_P_OMR_PS5_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PS5 */
+#define IFX_P_OMR_PS5_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PS5 */
+#define IFX_P_OMR_PS5_OFF (5u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PS6 */
+#define IFX_P_OMR_PS6_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PS6 */
+#define IFX_P_OMR_PS6_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PS6 */
+#define IFX_P_OMR_PS6_OFF (6u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PS7 */
+#define IFX_P_OMR_PS7_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PS7 */
+#define IFX_P_OMR_PS7_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PS7 */
+#define IFX_P_OMR_PS7_OFF (7u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PS8 */
+#define IFX_P_OMR_PS8_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PS8 */
+#define IFX_P_OMR_PS8_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PS8 */
+#define IFX_P_OMR_PS8_OFF (8u)
+
+/** \brief Length for Ifx_P_OMR_Bits.PS9 */
+#define IFX_P_OMR_PS9_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMR_Bits.PS9 */
+#define IFX_P_OMR_PS9_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMR_Bits.PS9 */
+#define IFX_P_OMR_PS9_OFF (9u)
+
+/** \brief Length for Ifx_P_OMSR0_Bits.PS0 */
+#define IFX_P_OMSR0_PS0_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR0_Bits.PS0 */
+#define IFX_P_OMSR0_PS0_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR0_Bits.PS0 */
+#define IFX_P_OMSR0_PS0_OFF (0u)
+
+/** \brief Length for Ifx_P_OMSR0_Bits.PS1 */
+#define IFX_P_OMSR0_PS1_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR0_Bits.PS1 */
+#define IFX_P_OMSR0_PS1_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR0_Bits.PS1 */
+#define IFX_P_OMSR0_PS1_OFF (1u)
+
+/** \brief Length for Ifx_P_OMSR0_Bits.PS2 */
+#define IFX_P_OMSR0_PS2_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR0_Bits.PS2 */
+#define IFX_P_OMSR0_PS2_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR0_Bits.PS2 */
+#define IFX_P_OMSR0_PS2_OFF (2u)
+
+/** \brief Length for Ifx_P_OMSR0_Bits.PS3 */
+#define IFX_P_OMSR0_PS3_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR0_Bits.PS3 */
+#define IFX_P_OMSR0_PS3_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR0_Bits.PS3 */
+#define IFX_P_OMSR0_PS3_OFF (3u)
+
+/** \brief Length for Ifx_P_OMSR12_Bits.PS12 */
+#define IFX_P_OMSR12_PS12_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR12_Bits.PS12 */
+#define IFX_P_OMSR12_PS12_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR12_Bits.PS12 */
+#define IFX_P_OMSR12_PS12_OFF (12u)
+
+/** \brief Length for Ifx_P_OMSR12_Bits.PS13 */
+#define IFX_P_OMSR12_PS13_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR12_Bits.PS13 */
+#define IFX_P_OMSR12_PS13_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR12_Bits.PS13 */
+#define IFX_P_OMSR12_PS13_OFF (13u)
+
+/** \brief Length for Ifx_P_OMSR12_Bits.PS14 */
+#define IFX_P_OMSR12_PS14_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR12_Bits.PS14 */
+#define IFX_P_OMSR12_PS14_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR12_Bits.PS14 */
+#define IFX_P_OMSR12_PS14_OFF (14u)
+
+/** \brief Length for Ifx_P_OMSR12_Bits.PS15 */
+#define IFX_P_OMSR12_PS15_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR12_Bits.PS15 */
+#define IFX_P_OMSR12_PS15_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR12_Bits.PS15 */
+#define IFX_P_OMSR12_PS15_OFF (15u)
+
+/** \brief Length for Ifx_P_OMSR4_Bits.PS4 */
+#define IFX_P_OMSR4_PS4_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR4_Bits.PS4 */
+#define IFX_P_OMSR4_PS4_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR4_Bits.PS4 */
+#define IFX_P_OMSR4_PS4_OFF (4u)
+
+/** \brief Length for Ifx_P_OMSR4_Bits.PS5 */
+#define IFX_P_OMSR4_PS5_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR4_Bits.PS5 */
+#define IFX_P_OMSR4_PS5_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR4_Bits.PS5 */
+#define IFX_P_OMSR4_PS5_OFF (5u)
+
+/** \brief Length for Ifx_P_OMSR4_Bits.PS6 */
+#define IFX_P_OMSR4_PS6_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR4_Bits.PS6 */
+#define IFX_P_OMSR4_PS6_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR4_Bits.PS6 */
+#define IFX_P_OMSR4_PS6_OFF (6u)
+
+/** \brief Length for Ifx_P_OMSR4_Bits.PS7 */
+#define IFX_P_OMSR4_PS7_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR4_Bits.PS7 */
+#define IFX_P_OMSR4_PS7_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR4_Bits.PS7 */
+#define IFX_P_OMSR4_PS7_OFF (7u)
+
+/** \brief Length for Ifx_P_OMSR8_Bits.PS10 */
+#define IFX_P_OMSR8_PS10_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR8_Bits.PS10 */
+#define IFX_P_OMSR8_PS10_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR8_Bits.PS10 */
+#define IFX_P_OMSR8_PS10_OFF (10u)
+
+/** \brief Length for Ifx_P_OMSR8_Bits.PS11 */
+#define IFX_P_OMSR8_PS11_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR8_Bits.PS11 */
+#define IFX_P_OMSR8_PS11_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR8_Bits.PS11 */
+#define IFX_P_OMSR8_PS11_OFF (11u)
+
+/** \brief Length for Ifx_P_OMSR8_Bits.PS8 */
+#define IFX_P_OMSR8_PS8_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR8_Bits.PS8 */
+#define IFX_P_OMSR8_PS8_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR8_Bits.PS8 */
+#define IFX_P_OMSR8_PS8_OFF (8u)
+
+/** \brief Length for Ifx_P_OMSR8_Bits.PS9 */
+#define IFX_P_OMSR8_PS9_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR8_Bits.PS9 */
+#define IFX_P_OMSR8_PS9_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR8_Bits.PS9 */
+#define IFX_P_OMSR8_PS9_OFF (9u)
+
+/** \brief Length for Ifx_P_OMSR_Bits.PS0 */
+#define IFX_P_OMSR_PS0_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR_Bits.PS0 */
+#define IFX_P_OMSR_PS0_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR_Bits.PS0 */
+#define IFX_P_OMSR_PS0_OFF (0u)
+
+/** \brief Length for Ifx_P_OMSR_Bits.PS10 */
+#define IFX_P_OMSR_PS10_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR_Bits.PS10 */
+#define IFX_P_OMSR_PS10_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR_Bits.PS10 */
+#define IFX_P_OMSR_PS10_OFF (10u)
+
+/** \brief Length for Ifx_P_OMSR_Bits.PS11 */
+#define IFX_P_OMSR_PS11_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR_Bits.PS11 */
+#define IFX_P_OMSR_PS11_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR_Bits.PS11 */
+#define IFX_P_OMSR_PS11_OFF (11u)
+
+/** \brief Length for Ifx_P_OMSR_Bits.PS12 */
+#define IFX_P_OMSR_PS12_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR_Bits.PS12 */
+#define IFX_P_OMSR_PS12_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR_Bits.PS12 */
+#define IFX_P_OMSR_PS12_OFF (12u)
+
+/** \brief Length for Ifx_P_OMSR_Bits.PS13 */
+#define IFX_P_OMSR_PS13_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR_Bits.PS13 */
+#define IFX_P_OMSR_PS13_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR_Bits.PS13 */
+#define IFX_P_OMSR_PS13_OFF (13u)
+
+/** \brief Length for Ifx_P_OMSR_Bits.PS14 */
+#define IFX_P_OMSR_PS14_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR_Bits.PS14 */
+#define IFX_P_OMSR_PS14_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR_Bits.PS14 */
+#define IFX_P_OMSR_PS14_OFF (14u)
+
+/** \brief Length for Ifx_P_OMSR_Bits.PS15 */
+#define IFX_P_OMSR_PS15_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR_Bits.PS15 */
+#define IFX_P_OMSR_PS15_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR_Bits.PS15 */
+#define IFX_P_OMSR_PS15_OFF (15u)
+
+/** \brief Length for Ifx_P_OMSR_Bits.PS1 */
+#define IFX_P_OMSR_PS1_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR_Bits.PS1 */
+#define IFX_P_OMSR_PS1_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR_Bits.PS1 */
+#define IFX_P_OMSR_PS1_OFF (1u)
+
+/** \brief Length for Ifx_P_OMSR_Bits.PS2 */
+#define IFX_P_OMSR_PS2_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR_Bits.PS2 */
+#define IFX_P_OMSR_PS2_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR_Bits.PS2 */
+#define IFX_P_OMSR_PS2_OFF (2u)
+
+/** \brief Length for Ifx_P_OMSR_Bits.PS3 */
+#define IFX_P_OMSR_PS3_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR_Bits.PS3 */
+#define IFX_P_OMSR_PS3_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR_Bits.PS3 */
+#define IFX_P_OMSR_PS3_OFF (3u)
+
+/** \brief Length for Ifx_P_OMSR_Bits.PS4 */
+#define IFX_P_OMSR_PS4_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR_Bits.PS4 */
+#define IFX_P_OMSR_PS4_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR_Bits.PS4 */
+#define IFX_P_OMSR_PS4_OFF (4u)
+
+/** \brief Length for Ifx_P_OMSR_Bits.PS5 */
+#define IFX_P_OMSR_PS5_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR_Bits.PS5 */
+#define IFX_P_OMSR_PS5_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR_Bits.PS5 */
+#define IFX_P_OMSR_PS5_OFF (5u)
+
+/** \brief Length for Ifx_P_OMSR_Bits.PS6 */
+#define IFX_P_OMSR_PS6_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR_Bits.PS6 */
+#define IFX_P_OMSR_PS6_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR_Bits.PS6 */
+#define IFX_P_OMSR_PS6_OFF (6u)
+
+/** \brief Length for Ifx_P_OMSR_Bits.PS7 */
+#define IFX_P_OMSR_PS7_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR_Bits.PS7 */
+#define IFX_P_OMSR_PS7_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR_Bits.PS7 */
+#define IFX_P_OMSR_PS7_OFF (7u)
+
+/** \brief Length for Ifx_P_OMSR_Bits.PS8 */
+#define IFX_P_OMSR_PS8_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR_Bits.PS8 */
+#define IFX_P_OMSR_PS8_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR_Bits.PS8 */
+#define IFX_P_OMSR_PS8_OFF (8u)
+
+/** \brief Length for Ifx_P_OMSR_Bits.PS9 */
+#define IFX_P_OMSR_PS9_LEN (1u)
+
+/** \brief Mask for Ifx_P_OMSR_Bits.PS9 */
+#define IFX_P_OMSR_PS9_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OMSR_Bits.PS9 */
+#define IFX_P_OMSR_PS9_OFF (9u)
+
+/** \brief Length for Ifx_P_OUT_Bits.P0 */
+#define IFX_P_OUT_P0_LEN (1u)
+
+/** \brief Mask for Ifx_P_OUT_Bits.P0 */
+#define IFX_P_OUT_P0_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OUT_Bits.P0 */
+#define IFX_P_OUT_P0_OFF (0u)
+
+/** \brief Length for Ifx_P_OUT_Bits.P10 */
+#define IFX_P_OUT_P10_LEN (1u)
+
+/** \brief Mask for Ifx_P_OUT_Bits.P10 */
+#define IFX_P_OUT_P10_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OUT_Bits.P10 */
+#define IFX_P_OUT_P10_OFF (10u)
+
+/** \brief Length for Ifx_P_OUT_Bits.P11 */
+#define IFX_P_OUT_P11_LEN (1u)
+
+/** \brief Mask for Ifx_P_OUT_Bits.P11 */
+#define IFX_P_OUT_P11_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OUT_Bits.P11 */
+#define IFX_P_OUT_P11_OFF (11u)
+
+/** \brief Length for Ifx_P_OUT_Bits.P12 */
+#define IFX_P_OUT_P12_LEN (1u)
+
+/** \brief Mask for Ifx_P_OUT_Bits.P12 */
+#define IFX_P_OUT_P12_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OUT_Bits.P12 */
+#define IFX_P_OUT_P12_OFF (12u)
+
+/** \brief Length for Ifx_P_OUT_Bits.P13 */
+#define IFX_P_OUT_P13_LEN (1u)
+
+/** \brief Mask for Ifx_P_OUT_Bits.P13 */
+#define IFX_P_OUT_P13_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OUT_Bits.P13 */
+#define IFX_P_OUT_P13_OFF (13u)
+
+/** \brief Length for Ifx_P_OUT_Bits.P14 */
+#define IFX_P_OUT_P14_LEN (1u)
+
+/** \brief Mask for Ifx_P_OUT_Bits.P14 */
+#define IFX_P_OUT_P14_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OUT_Bits.P14 */
+#define IFX_P_OUT_P14_OFF (14u)
+
+/** \brief Length for Ifx_P_OUT_Bits.P15 */
+#define IFX_P_OUT_P15_LEN (1u)
+
+/** \brief Mask for Ifx_P_OUT_Bits.P15 */
+#define IFX_P_OUT_P15_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OUT_Bits.P15 */
+#define IFX_P_OUT_P15_OFF (15u)
+
+/** \brief Length for Ifx_P_OUT_Bits.P1 */
+#define IFX_P_OUT_P1_LEN (1u)
+
+/** \brief Mask for Ifx_P_OUT_Bits.P1 */
+#define IFX_P_OUT_P1_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OUT_Bits.P1 */
+#define IFX_P_OUT_P1_OFF (1u)
+
+/** \brief Length for Ifx_P_OUT_Bits.P2 */
+#define IFX_P_OUT_P2_LEN (1u)
+
+/** \brief Mask for Ifx_P_OUT_Bits.P2 */
+#define IFX_P_OUT_P2_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OUT_Bits.P2 */
+#define IFX_P_OUT_P2_OFF (2u)
+
+/** \brief Length for Ifx_P_OUT_Bits.P3 */
+#define IFX_P_OUT_P3_LEN (1u)
+
+/** \brief Mask for Ifx_P_OUT_Bits.P3 */
+#define IFX_P_OUT_P3_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OUT_Bits.P3 */
+#define IFX_P_OUT_P3_OFF (3u)
+
+/** \brief Length for Ifx_P_OUT_Bits.P4 */
+#define IFX_P_OUT_P4_LEN (1u)
+
+/** \brief Mask for Ifx_P_OUT_Bits.P4 */
+#define IFX_P_OUT_P4_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OUT_Bits.P4 */
+#define IFX_P_OUT_P4_OFF (4u)
+
+/** \brief Length for Ifx_P_OUT_Bits.P5 */
+#define IFX_P_OUT_P5_LEN (1u)
+
+/** \brief Mask for Ifx_P_OUT_Bits.P5 */
+#define IFX_P_OUT_P5_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OUT_Bits.P5 */
+#define IFX_P_OUT_P5_OFF (5u)
+
+/** \brief Length for Ifx_P_OUT_Bits.P6 */
+#define IFX_P_OUT_P6_LEN (1u)
+
+/** \brief Mask for Ifx_P_OUT_Bits.P6 */
+#define IFX_P_OUT_P6_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OUT_Bits.P6 */
+#define IFX_P_OUT_P6_OFF (6u)
+
+/** \brief Length for Ifx_P_OUT_Bits.P7 */
+#define IFX_P_OUT_P7_LEN (1u)
+
+/** \brief Mask for Ifx_P_OUT_Bits.P7 */
+#define IFX_P_OUT_P7_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OUT_Bits.P7 */
+#define IFX_P_OUT_P7_OFF (7u)
+
+/** \brief Length for Ifx_P_OUT_Bits.P8 */
+#define IFX_P_OUT_P8_LEN (1u)
+
+/** \brief Mask for Ifx_P_OUT_Bits.P8 */
+#define IFX_P_OUT_P8_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OUT_Bits.P8 */
+#define IFX_P_OUT_P8_OFF (8u)
+
+/** \brief Length for Ifx_P_OUT_Bits.P9 */
+#define IFX_P_OUT_P9_LEN (1u)
+
+/** \brief Mask for Ifx_P_OUT_Bits.P9 */
+#define IFX_P_OUT_P9_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_OUT_Bits.P9 */
+#define IFX_P_OUT_P9_OFF (9u)
+
+/** \brief Length for Ifx_P_PCSR_Bits.LCK */
+#define IFX_P_PCSR_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_P_PCSR_Bits.LCK */
+#define IFX_P_PCSR_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PCSR_Bits.LCK */
+#define IFX_P_PCSR_LCK_OFF (31u)
+
+/** \brief Length for Ifx_P_PCSR_Bits.SEL0 */
+#define IFX_P_PCSR_SEL0_LEN (1u)
+
+/** \brief Mask for Ifx_P_PCSR_Bits.SEL0 */
+#define IFX_P_PCSR_SEL0_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PCSR_Bits.SEL0 */
+#define IFX_P_PCSR_SEL0_OFF (0u)
+
+/** \brief Length for Ifx_P_PCSR_Bits.SEL10 */
+#define IFX_P_PCSR_SEL10_LEN (1u)
+
+/** \brief Mask for Ifx_P_PCSR_Bits.SEL10 */
+#define IFX_P_PCSR_SEL10_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PCSR_Bits.SEL10 */
+#define IFX_P_PCSR_SEL10_OFF (10u)
+
+/** \brief Length for Ifx_P_PCSR_Bits.SEL11 */
+#define IFX_P_PCSR_SEL11_LEN (1u)
+
+/** \brief Mask for Ifx_P_PCSR_Bits.SEL11 */
+#define IFX_P_PCSR_SEL11_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PCSR_Bits.SEL11 */
+#define IFX_P_PCSR_SEL11_OFF (11u)
+
+/** \brief Length for Ifx_P_PCSR_Bits.SEL1 */
+#define IFX_P_PCSR_SEL1_LEN (1u)
+
+/** \brief Mask for Ifx_P_PCSR_Bits.SEL1 */
+#define IFX_P_PCSR_SEL1_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PCSR_Bits.SEL1 */
+#define IFX_P_PCSR_SEL1_OFF (1u)
+
+/** \brief Length for Ifx_P_PCSR_Bits.SEL2 */
+#define IFX_P_PCSR_SEL2_LEN (1u)
+
+/** \brief Mask for Ifx_P_PCSR_Bits.SEL2 */
+#define IFX_P_PCSR_SEL2_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PCSR_Bits.SEL2 */
+#define IFX_P_PCSR_SEL2_OFF (2u)
+
+/** \brief Length for Ifx_P_PCSR_Bits.SEL3 */
+#define IFX_P_PCSR_SEL3_LEN (1u)
+
+/** \brief Mask for Ifx_P_PCSR_Bits.SEL3 */
+#define IFX_P_PCSR_SEL3_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PCSR_Bits.SEL3 */
+#define IFX_P_PCSR_SEL3_OFF (3u)
+
+/** \brief Length for Ifx_P_PCSR_Bits.SEL4 */
+#define IFX_P_PCSR_SEL4_LEN (1u)
+
+/** \brief Mask for Ifx_P_PCSR_Bits.SEL4 */
+#define IFX_P_PCSR_SEL4_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PCSR_Bits.SEL4 */
+#define IFX_P_PCSR_SEL4_OFF (4u)
+
+/** \brief Length for Ifx_P_PCSR_Bits.SEL5 */
+#define IFX_P_PCSR_SEL5_LEN (1u)
+
+/** \brief Mask for Ifx_P_PCSR_Bits.SEL5 */
+#define IFX_P_PCSR_SEL5_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PCSR_Bits.SEL5 */
+#define IFX_P_PCSR_SEL5_OFF (5u)
+
+/** \brief Length for Ifx_P_PCSR_Bits.SEL6 */
+#define IFX_P_PCSR_SEL6_LEN (1u)
+
+/** \brief Mask for Ifx_P_PCSR_Bits.SEL6 */
+#define IFX_P_PCSR_SEL6_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PCSR_Bits.SEL6 */
+#define IFX_P_PCSR_SEL6_OFF (6u)
+
+/** \brief Length for Ifx_P_PCSR_Bits.SEL7 */
+#define IFX_P_PCSR_SEL7_LEN (1u)
+
+/** \brief Mask for Ifx_P_PCSR_Bits.SEL7 */
+#define IFX_P_PCSR_SEL7_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PCSR_Bits.SEL7 */
+#define IFX_P_PCSR_SEL7_OFF (7u)
+
+/** \brief Length for Ifx_P_PDISC_Bits.PDIS0 */
+#define IFX_P_PDISC_PDIS0_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDISC_Bits.PDIS0 */
+#define IFX_P_PDISC_PDIS0_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDISC_Bits.PDIS0 */
+#define IFX_P_PDISC_PDIS0_OFF (0u)
+
+/** \brief Length for Ifx_P_PDISC_Bits.PDIS10 */
+#define IFX_P_PDISC_PDIS10_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDISC_Bits.PDIS10 */
+#define IFX_P_PDISC_PDIS10_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDISC_Bits.PDIS10 */
+#define IFX_P_PDISC_PDIS10_OFF (10u)
+
+/** \brief Length for Ifx_P_PDISC_Bits.PDIS11 */
+#define IFX_P_PDISC_PDIS11_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDISC_Bits.PDIS11 */
+#define IFX_P_PDISC_PDIS11_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDISC_Bits.PDIS11 */
+#define IFX_P_PDISC_PDIS11_OFF (11u)
+
+/** \brief Length for Ifx_P_PDISC_Bits.PDIS12 */
+#define IFX_P_PDISC_PDIS12_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDISC_Bits.PDIS12 */
+#define IFX_P_PDISC_PDIS12_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDISC_Bits.PDIS12 */
+#define IFX_P_PDISC_PDIS12_OFF (12u)
+
+/** \brief Length for Ifx_P_PDISC_Bits.PDIS13 */
+#define IFX_P_PDISC_PDIS13_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDISC_Bits.PDIS13 */
+#define IFX_P_PDISC_PDIS13_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDISC_Bits.PDIS13 */
+#define IFX_P_PDISC_PDIS13_OFF (13u)
+
+/** \brief Length for Ifx_P_PDISC_Bits.PDIS14 */
+#define IFX_P_PDISC_PDIS14_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDISC_Bits.PDIS14 */
+#define IFX_P_PDISC_PDIS14_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDISC_Bits.PDIS14 */
+#define IFX_P_PDISC_PDIS14_OFF (14u)
+
+/** \brief Length for Ifx_P_PDISC_Bits.PDIS15 */
+#define IFX_P_PDISC_PDIS15_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDISC_Bits.PDIS15 */
+#define IFX_P_PDISC_PDIS15_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDISC_Bits.PDIS15 */
+#define IFX_P_PDISC_PDIS15_OFF (15u)
+
+/** \brief Length for Ifx_P_PDISC_Bits.PDIS1 */
+#define IFX_P_PDISC_PDIS1_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDISC_Bits.PDIS1 */
+#define IFX_P_PDISC_PDIS1_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDISC_Bits.PDIS1 */
+#define IFX_P_PDISC_PDIS1_OFF (1u)
+
+/** \brief Length for Ifx_P_PDISC_Bits.PDIS2 */
+#define IFX_P_PDISC_PDIS2_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDISC_Bits.PDIS2 */
+#define IFX_P_PDISC_PDIS2_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDISC_Bits.PDIS2 */
+#define IFX_P_PDISC_PDIS2_OFF (2u)
+
+/** \brief Length for Ifx_P_PDISC_Bits.PDIS3 */
+#define IFX_P_PDISC_PDIS3_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDISC_Bits.PDIS3 */
+#define IFX_P_PDISC_PDIS3_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDISC_Bits.PDIS3 */
+#define IFX_P_PDISC_PDIS3_OFF (3u)
+
+/** \brief Length for Ifx_P_PDISC_Bits.PDIS4 */
+#define IFX_P_PDISC_PDIS4_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDISC_Bits.PDIS4 */
+#define IFX_P_PDISC_PDIS4_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDISC_Bits.PDIS4 */
+#define IFX_P_PDISC_PDIS4_OFF (4u)
+
+/** \brief Length for Ifx_P_PDISC_Bits.PDIS5 */
+#define IFX_P_PDISC_PDIS5_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDISC_Bits.PDIS5 */
+#define IFX_P_PDISC_PDIS5_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDISC_Bits.PDIS5 */
+#define IFX_P_PDISC_PDIS5_OFF (5u)
+
+/** \brief Length for Ifx_P_PDISC_Bits.PDIS6 */
+#define IFX_P_PDISC_PDIS6_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDISC_Bits.PDIS6 */
+#define IFX_P_PDISC_PDIS6_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDISC_Bits.PDIS6 */
+#define IFX_P_PDISC_PDIS6_OFF (6u)
+
+/** \brief Length for Ifx_P_PDISC_Bits.PDIS7 */
+#define IFX_P_PDISC_PDIS7_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDISC_Bits.PDIS7 */
+#define IFX_P_PDISC_PDIS7_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDISC_Bits.PDIS7 */
+#define IFX_P_PDISC_PDIS7_OFF (7u)
+
+/** \brief Length for Ifx_P_PDISC_Bits.PDIS8 */
+#define IFX_P_PDISC_PDIS8_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDISC_Bits.PDIS8 */
+#define IFX_P_PDISC_PDIS8_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDISC_Bits.PDIS8 */
+#define IFX_P_PDISC_PDIS8_OFF (8u)
+
+/** \brief Length for Ifx_P_PDISC_Bits.PDIS9 */
+#define IFX_P_PDISC_PDIS9_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDISC_Bits.PDIS9 */
+#define IFX_P_PDISC_PDIS9_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDISC_Bits.PDIS9 */
+#define IFX_P_PDISC_PDIS9_OFF (9u)
+
+/** \brief Length for Ifx_P_PDR0_Bits.PD0 */
+#define IFX_P_PDR0_PD0_LEN (3u)
+
+/** \brief Mask for Ifx_P_PDR0_Bits.PD0 */
+#define IFX_P_PDR0_PD0_MSK (0x7u)
+
+/** \brief Offset for Ifx_P_PDR0_Bits.PD0 */
+#define IFX_P_PDR0_PD0_OFF (0u)
+
+/** \brief Length for Ifx_P_PDR0_Bits.PD1 */
+#define IFX_P_PDR0_PD1_LEN (3u)
+
+/** \brief Mask for Ifx_P_PDR0_Bits.PD1 */
+#define IFX_P_PDR0_PD1_MSK (0x7u)
+
+/** \brief Offset for Ifx_P_PDR0_Bits.PD1 */
+#define IFX_P_PDR0_PD1_OFF (4u)
+
+/** \brief Length for Ifx_P_PDR0_Bits.PD2 */
+#define IFX_P_PDR0_PD2_LEN (3u)
+
+/** \brief Mask for Ifx_P_PDR0_Bits.PD2 */
+#define IFX_P_PDR0_PD2_MSK (0x7u)
+
+/** \brief Offset for Ifx_P_PDR0_Bits.PD2 */
+#define IFX_P_PDR0_PD2_OFF (8u)
+
+/** \brief Length for Ifx_P_PDR0_Bits.PD3 */
+#define IFX_P_PDR0_PD3_LEN (3u)
+
+/** \brief Mask for Ifx_P_PDR0_Bits.PD3 */
+#define IFX_P_PDR0_PD3_MSK (0x7u)
+
+/** \brief Offset for Ifx_P_PDR0_Bits.PD3 */
+#define IFX_P_PDR0_PD3_OFF (12u)
+
+/** \brief Length for Ifx_P_PDR0_Bits.PD4 */
+#define IFX_P_PDR0_PD4_LEN (3u)
+
+/** \brief Mask for Ifx_P_PDR0_Bits.PD4 */
+#define IFX_P_PDR0_PD4_MSK (0x7u)
+
+/** \brief Offset for Ifx_P_PDR0_Bits.PD4 */
+#define IFX_P_PDR0_PD4_OFF (16u)
+
+/** \brief Length for Ifx_P_PDR0_Bits.PD5 */
+#define IFX_P_PDR0_PD5_LEN (3u)
+
+/** \brief Mask for Ifx_P_PDR0_Bits.PD5 */
+#define IFX_P_PDR0_PD5_MSK (0x7u)
+
+/** \brief Offset for Ifx_P_PDR0_Bits.PD5 */
+#define IFX_P_PDR0_PD5_OFF (20u)
+
+/** \brief Length for Ifx_P_PDR0_Bits.PD6 */
+#define IFX_P_PDR0_PD6_LEN (3u)
+
+/** \brief Mask for Ifx_P_PDR0_Bits.PD6 */
+#define IFX_P_PDR0_PD6_MSK (0x7u)
+
+/** \brief Offset for Ifx_P_PDR0_Bits.PD6 */
+#define IFX_P_PDR0_PD6_OFF (24u)
+
+/** \brief Length for Ifx_P_PDR0_Bits.PD7 */
+#define IFX_P_PDR0_PD7_LEN (3u)
+
+/** \brief Mask for Ifx_P_PDR0_Bits.PD7 */
+#define IFX_P_PDR0_PD7_MSK (0x7u)
+
+/** \brief Offset for Ifx_P_PDR0_Bits.PD7 */
+#define IFX_P_PDR0_PD7_OFF (28u)
+
+/** \brief Length for Ifx_P_PDR0_Bits.PL0 */
+#define IFX_P_PDR0_PL0_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDR0_Bits.PL0 */
+#define IFX_P_PDR0_PL0_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDR0_Bits.PL0 */
+#define IFX_P_PDR0_PL0_OFF (3u)
+
+/** \brief Length for Ifx_P_PDR0_Bits.PL1 */
+#define IFX_P_PDR0_PL1_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDR0_Bits.PL1 */
+#define IFX_P_PDR0_PL1_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDR0_Bits.PL1 */
+#define IFX_P_PDR0_PL1_OFF (7u)
+
+/** \brief Length for Ifx_P_PDR0_Bits.PL2 */
+#define IFX_P_PDR0_PL2_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDR0_Bits.PL2 */
+#define IFX_P_PDR0_PL2_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDR0_Bits.PL2 */
+#define IFX_P_PDR0_PL2_OFF (11u)
+
+/** \brief Length for Ifx_P_PDR0_Bits.PL3 */
+#define IFX_P_PDR0_PL3_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDR0_Bits.PL3 */
+#define IFX_P_PDR0_PL3_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDR0_Bits.PL3 */
+#define IFX_P_PDR0_PL3_OFF (15u)
+
+/** \brief Length for Ifx_P_PDR0_Bits.PL4 */
+#define IFX_P_PDR0_PL4_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDR0_Bits.PL4 */
+#define IFX_P_PDR0_PL4_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDR0_Bits.PL4 */
+#define IFX_P_PDR0_PL4_OFF (19u)
+
+/** \brief Length for Ifx_P_PDR0_Bits.PL5 */
+#define IFX_P_PDR0_PL5_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDR0_Bits.PL5 */
+#define IFX_P_PDR0_PL5_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDR0_Bits.PL5 */
+#define IFX_P_PDR0_PL5_OFF (23u)
+
+/** \brief Length for Ifx_P_PDR0_Bits.PL6 */
+#define IFX_P_PDR0_PL6_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDR0_Bits.PL6 */
+#define IFX_P_PDR0_PL6_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDR0_Bits.PL6 */
+#define IFX_P_PDR0_PL6_OFF (27u)
+
+/** \brief Length for Ifx_P_PDR0_Bits.PL7 */
+#define IFX_P_PDR0_PL7_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDR0_Bits.PL7 */
+#define IFX_P_PDR0_PL7_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDR0_Bits.PL7 */
+#define IFX_P_PDR0_PL7_OFF (31u)
+
+/** \brief Length for Ifx_P_PDR1_Bits.PD10 */
+#define IFX_P_PDR1_PD10_LEN (3u)
+
+/** \brief Mask for Ifx_P_PDR1_Bits.PD10 */
+#define IFX_P_PDR1_PD10_MSK (0x7u)
+
+/** \brief Offset for Ifx_P_PDR1_Bits.PD10 */
+#define IFX_P_PDR1_PD10_OFF (8u)
+
+/** \brief Length for Ifx_P_PDR1_Bits.PD11 */
+#define IFX_P_PDR1_PD11_LEN (3u)
+
+/** \brief Mask for Ifx_P_PDR1_Bits.PD11 */
+#define IFX_P_PDR1_PD11_MSK (0x7u)
+
+/** \brief Offset for Ifx_P_PDR1_Bits.PD11 */
+#define IFX_P_PDR1_PD11_OFF (12u)
+
+/** \brief Length for Ifx_P_PDR1_Bits.PD12 */
+#define IFX_P_PDR1_PD12_LEN (3u)
+
+/** \brief Mask for Ifx_P_PDR1_Bits.PD12 */
+#define IFX_P_PDR1_PD12_MSK (0x7u)
+
+/** \brief Offset for Ifx_P_PDR1_Bits.PD12 */
+#define IFX_P_PDR1_PD12_OFF (16u)
+
+/** \brief Length for Ifx_P_PDR1_Bits.PD13 */
+#define IFX_P_PDR1_PD13_LEN (3u)
+
+/** \brief Mask for Ifx_P_PDR1_Bits.PD13 */
+#define IFX_P_PDR1_PD13_MSK (0x7u)
+
+/** \brief Offset for Ifx_P_PDR1_Bits.PD13 */
+#define IFX_P_PDR1_PD13_OFF (20u)
+
+/** \brief Length for Ifx_P_PDR1_Bits.PD14 */
+#define IFX_P_PDR1_PD14_LEN (3u)
+
+/** \brief Mask for Ifx_P_PDR1_Bits.PD14 */
+#define IFX_P_PDR1_PD14_MSK (0x7u)
+
+/** \brief Offset for Ifx_P_PDR1_Bits.PD14 */
+#define IFX_P_PDR1_PD14_OFF (24u)
+
+/** \brief Length for Ifx_P_PDR1_Bits.PD15 */
+#define IFX_P_PDR1_PD15_LEN (3u)
+
+/** \brief Mask for Ifx_P_PDR1_Bits.PD15 */
+#define IFX_P_PDR1_PD15_MSK (0x7u)
+
+/** \brief Offset for Ifx_P_PDR1_Bits.PD15 */
+#define IFX_P_PDR1_PD15_OFF (28u)
+
+/** \brief Length for Ifx_P_PDR1_Bits.PD8 */
+#define IFX_P_PDR1_PD8_LEN (3u)
+
+/** \brief Mask for Ifx_P_PDR1_Bits.PD8 */
+#define IFX_P_PDR1_PD8_MSK (0x7u)
+
+/** \brief Offset for Ifx_P_PDR1_Bits.PD8 */
+#define IFX_P_PDR1_PD8_OFF (0u)
+
+/** \brief Length for Ifx_P_PDR1_Bits.PD9 */
+#define IFX_P_PDR1_PD9_LEN (3u)
+
+/** \brief Mask for Ifx_P_PDR1_Bits.PD9 */
+#define IFX_P_PDR1_PD9_MSK (0x7u)
+
+/** \brief Offset for Ifx_P_PDR1_Bits.PD9 */
+#define IFX_P_PDR1_PD9_OFF (4u)
+
+/** \brief Length for Ifx_P_PDR1_Bits.PL10 */
+#define IFX_P_PDR1_PL10_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDR1_Bits.PL10 */
+#define IFX_P_PDR1_PL10_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDR1_Bits.PL10 */
+#define IFX_P_PDR1_PL10_OFF (11u)
+
+/** \brief Length for Ifx_P_PDR1_Bits.PL11 */
+#define IFX_P_PDR1_PL11_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDR1_Bits.PL11 */
+#define IFX_P_PDR1_PL11_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDR1_Bits.PL11 */
+#define IFX_P_PDR1_PL11_OFF (15u)
+
+/** \brief Length for Ifx_P_PDR1_Bits.PL12 */
+#define IFX_P_PDR1_PL12_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDR1_Bits.PL12 */
+#define IFX_P_PDR1_PL12_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDR1_Bits.PL12 */
+#define IFX_P_PDR1_PL12_OFF (19u)
+
+/** \brief Length for Ifx_P_PDR1_Bits.PL13 */
+#define IFX_P_PDR1_PL13_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDR1_Bits.PL13 */
+#define IFX_P_PDR1_PL13_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDR1_Bits.PL13 */
+#define IFX_P_PDR1_PL13_OFF (23u)
+
+/** \brief Length for Ifx_P_PDR1_Bits.PL14 */
+#define IFX_P_PDR1_PL14_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDR1_Bits.PL14 */
+#define IFX_P_PDR1_PL14_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDR1_Bits.PL14 */
+#define IFX_P_PDR1_PL14_OFF (27u)
+
+/** \brief Length for Ifx_P_PDR1_Bits.PL15 */
+#define IFX_P_PDR1_PL15_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDR1_Bits.PL15 */
+#define IFX_P_PDR1_PL15_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDR1_Bits.PL15 */
+#define IFX_P_PDR1_PL15_OFF (31u)
+
+/** \brief Length for Ifx_P_PDR1_Bits.PL8 */
+#define IFX_P_PDR1_PL8_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDR1_Bits.PL8 */
+#define IFX_P_PDR1_PL8_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDR1_Bits.PL8 */
+#define IFX_P_PDR1_PL8_OFF (3u)
+
+/** \brief Length for Ifx_P_PDR1_Bits.PL9 */
+#define IFX_P_PDR1_PL9_LEN (1u)
+
+/** \brief Mask for Ifx_P_PDR1_Bits.PL9 */
+#define IFX_P_PDR1_PL9_MSK (0x1u)
+
+/** \brief Offset for Ifx_P_PDR1_Bits.PL9 */
+#define IFX_P_PDR1_PL9_OFF (7u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXPORT_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPort_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPort_reg.h
new file mode 100644
index 0000000..768f041
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPort_reg.h
@@ -0,0 +1,980 @@
+/**
+ * \file IfxPort_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Port_Cfg Port address
+ * \ingroup IfxLld_Port
+ *
+ * \defgroup IfxLld_Port_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Port_Cfg
+ *
+ * \defgroup IfxLld_Port_Cfg_P00 2-P00
+ * \ingroup IfxLld_Port_Cfg
+ *
+ * \defgroup IfxLld_Port_Cfg_P02 2-P02
+ * \ingroup IfxLld_Port_Cfg
+ *
+ * \defgroup IfxLld_Port_Cfg_P10 2-P10
+ * \ingroup IfxLld_Port_Cfg
+ *
+ * \defgroup IfxLld_Port_Cfg_P11 2-P11
+ * \ingroup IfxLld_Port_Cfg
+ *
+ * \defgroup IfxLld_Port_Cfg_P13 2-P13
+ * \ingroup IfxLld_Port_Cfg
+ *
+ * \defgroup IfxLld_Port_Cfg_P14 2-P14
+ * \ingroup IfxLld_Port_Cfg
+ *
+ * \defgroup IfxLld_Port_Cfg_P15 2-P15
+ * \ingroup IfxLld_Port_Cfg
+ *
+ * \defgroup IfxLld_Port_Cfg_P20 2-P20
+ * \ingroup IfxLld_Port_Cfg
+ *
+ * \defgroup IfxLld_Port_Cfg_P21 2-P21
+ * \ingroup IfxLld_Port_Cfg
+ *
+ * \defgroup IfxLld_Port_Cfg_P22 2-P22
+ * \ingroup IfxLld_Port_Cfg
+ *
+ * \defgroup IfxLld_Port_Cfg_P23 2-P23
+ * \ingroup IfxLld_Port_Cfg
+ *
+ * \defgroup IfxLld_Port_Cfg_P32 2-P32
+ * \ingroup IfxLld_Port_Cfg
+ *
+ * \defgroup IfxLld_Port_Cfg_P33 2-P33
+ * \ingroup IfxLld_Port_Cfg
+ *
+ * \defgroup IfxLld_Port_Cfg_P40 2-P40
+ * \ingroup IfxLld_Port_Cfg
+ *
+ */
+#ifndef IFXPORT_REG_H
+#define IFXPORT_REG_H 1
+/******************************************************************************/
+#include "IfxPort_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_BaseAddress
+ * \{ */
+
+/** \brief Port object */
+#define MODULE_P00 /*lint --e(923)*/ (*(Ifx_P*)0xF003A000u)
+
+/** \brief Port object */
+#define MODULE_P02 /*lint --e(923)*/ (*(Ifx_P*)0xF003A200u)
+
+/** \brief Port object */
+#define MODULE_P10 /*lint --e(923)*/ (*(Ifx_P*)0xF003B000u)
+
+/** \brief Port object */
+#define MODULE_P11 /*lint --e(923)*/ (*(Ifx_P*)0xF003B100u)
+
+/** \brief Port object */
+#define MODULE_P13 /*lint --e(923)*/ (*(Ifx_P*)0xF003B300u)
+
+/** \brief Port object */
+#define MODULE_P14 /*lint --e(923)*/ (*(Ifx_P*)0xF003B400u)
+
+/** \brief Port object */
+#define MODULE_P15 /*lint --e(923)*/ (*(Ifx_P*)0xF003B500u)
+
+/** \brief Port object */
+#define MODULE_P20 /*lint --e(923)*/ (*(Ifx_P*)0xF003C000u)
+
+/** \brief Port object */
+#define MODULE_P21 /*lint --e(923)*/ (*(Ifx_P*)0xF003C100u)
+
+/** \brief Port object */
+#define MODULE_P22 /*lint --e(923)*/ (*(Ifx_P*)0xF003C200u)
+
+/** \brief Port object */
+#define MODULE_P23 /*lint --e(923)*/ (*(Ifx_P*)0xF003C300u)
+
+/** \brief Port object */
+#define MODULE_P32 /*lint --e(923)*/ (*(Ifx_P*)0xF003D200u)
+
+/** \brief Port object */
+#define MODULE_P33 /*lint --e(923)*/ (*(Ifx_P*)0xF003D300u)
+
+/** \brief Port object */
+#define MODULE_P40 /*lint --e(923)*/ (*(Ifx_P*)0xF003E000u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_P00
+ * \{ */
+
+/** \brief FC, Port Access Enable Register 0 */
+#define P00_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003A0FCu)
+
+/** \brief F8, Port Access Enable Register 1 */
+#define P00_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003A0F8u)
+
+/** \brief 50, Port Emergency Stop Register */
+#define P00_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003A050u)
+
+/** \brief 8, Identification Register */
+#define P00_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003A008u)
+
+/** \brief 24, Port Input Register */
+#define P00_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003A024u)
+
+/** \brief 10, Port Input/Output Control Register 0 */
+#define P00_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003A010u)
+
+/** \brief 1C, Port Input/Output Control Register 12 */
+#define P00_IOCR12 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR12*)0xF003A01Cu)
+
+/** \brief 14, Port Input/Output Control Register 4 */
+#define P00_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003A014u)
+
+/** \brief 18, Port Input/Output Control Register 8 */
+#define P00_IOCR8 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR8*)0xF003A018u)
+
+/** \brief 94, Port Output Modification Clear Register */
+#define P00_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003A094u)
+
+/** \brief 80, Port Output Modification Clear Register 0 */
+#define P00_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003A080u)
+
+/** \brief 8C, Port Output Modification Clear Register 12 */
+#define P00_OMCR12 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR12*)0xF003A08Cu)
+
+/** \brief 84, Port Output Modification Clear Register 4 */
+#define P00_OMCR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR4*)0xF003A084u)
+
+/** \brief 88, Port Output Modification Clear Register 8 */
+#define P00_OMCR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR8*)0xF003A088u)
+
+/** \brief 4, Port Output Modification Register */
+#define P00_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003A004u)
+
+/** \brief 90, Port Output Modification Set Register */
+#define P00_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003A090u)
+
+/** \brief 70, Port Output Modification Set Register 0 */
+#define P00_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003A070u)
+
+/** \brief 7C, Port Output Modification Set Register 12 */
+#define P00_OMSR12 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR12*)0xF003A07Cu)
+
+/** \brief 74, Port Output Modification Set Register 4 */
+#define P00_OMSR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR4*)0xF003A074u)
+
+/** \brief 78, Port Output Modification Set Register 8 */
+#define P00_OMSR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR8*)0xF003A078u)
+
+/** \brief 0, Port Output Register */
+#define P00_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003A000u)
+
+/** \brief 64, Port Pin Controller Select Register */
+#define P00_PCSR /*lint --e(923)*/ (*(volatile Ifx_P_PCSR*)0xF003A064u)
+
+/** \brief 40, Port Pad Driver Mode 0 Register */
+#define P00_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003A040u)
+
+/** \brief 44, Port Pad Driver Mode 1 Register */
+#define P00_PDR1 /*lint --e(923)*/ (*(volatile Ifx_P_PDR1*)0xF003A044u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_P02
+ * \{ */
+
+/** \brief FC, Port Access Enable Register 0 */
+#define P02_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003A2FCu)
+
+/** \brief F8, Port Access Enable Register 1 */
+#define P02_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003A2F8u)
+
+/** \brief 50, Port Emergency Stop Register */
+#define P02_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003A250u)
+
+/** \brief 8, Identification Register */
+#define P02_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003A208u)
+
+/** \brief 24, Port Input Register */
+#define P02_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003A224u)
+
+/** \brief 10, Port Input/Output Control Register 0 */
+#define P02_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003A210u)
+
+/** \brief 14, Port Input/Output Control Register 4 */
+#define P02_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003A214u)
+
+/** \brief 18, Port Input/Output Control Register 8 */
+#define P02_IOCR8 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR8*)0xF003A218u)
+
+/** \brief 94, Port Output Modification Clear Register */
+#define P02_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003A294u)
+
+/** \brief 80, Port Output Modification Clear Register 0 */
+#define P02_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003A280u)
+
+/** \brief 84, Port Output Modification Clear Register 4 */
+#define P02_OMCR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR4*)0xF003A284u)
+
+/** \brief 88, Port Output Modification Clear Register 8 */
+#define P02_OMCR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR8*)0xF003A288u)
+
+/** \brief 4, Port Output Modification Register */
+#define P02_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003A204u)
+
+/** \brief 90, Port Output Modification Set Register */
+#define P02_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003A290u)
+
+/** \brief 70, Port Output Modification Set Register 0 */
+#define P02_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003A270u)
+
+/** \brief 74, Port Output Modification Set Register 4 */
+#define P02_OMSR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR4*)0xF003A274u)
+
+/** \brief 78, Port Output Modification Set Register 8 */
+#define P02_OMSR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR8*)0xF003A278u)
+
+/** \brief 0, Port Output Register */
+#define P02_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003A200u)
+
+/** \brief 64, Port Pin Controller Select Register */
+#define P02_PCSR /*lint --e(923)*/ (*(volatile Ifx_P_PCSR*)0xF003A264u)
+
+/** \brief 40, Port Pad Driver Mode 0 Register */
+#define P02_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003A240u)
+
+/** \brief 44, Port Pad Driver Mode 1 Register */
+#define P02_PDR1 /*lint --e(923)*/ (*(volatile Ifx_P_PDR1*)0xF003A244u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_P10
+ * \{ */
+
+/** \brief FC, Port Access Enable Register 0 */
+#define P10_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003B0FCu)
+
+/** \brief F8, Port Access Enable Register 1 */
+#define P10_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003B0F8u)
+
+/** \brief 50, Port Emergency Stop Register */
+#define P10_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003B050u)
+
+/** \brief 8, Identification Register */
+#define P10_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003B008u)
+
+/** \brief 24, Port Input Register */
+#define P10_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003B024u)
+
+/** \brief 10, Port Input/Output Control Register 0 */
+#define P10_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003B010u)
+
+/** \brief 14, Port Input/Output Control Register 4 */
+#define P10_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003B014u)
+
+/** \brief 18, Port Input/Output Control Register 8 */
+#define P10_IOCR8 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR8*)0xF003B018u)
+
+/** \brief 94, Port Output Modification Clear Register */
+#define P10_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003B094u)
+
+/** \brief 80, Port Output Modification Clear Register 0 */
+#define P10_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003B080u)
+
+/** \brief 84, Port Output Modification Clear Register 4 */
+#define P10_OMCR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR4*)0xF003B084u)
+
+/** \brief 88, Port Output Modification Clear Register 8 */
+#define P10_OMCR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR8*)0xF003B088u)
+
+/** \brief 4, Port Output Modification Register */
+#define P10_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003B004u)
+
+/** \brief 90, Port Output Modification Set Register */
+#define P10_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003B090u)
+
+/** \brief 70, Port Output Modification Set Register 0 */
+#define P10_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003B070u)
+
+/** \brief 74, Port Output Modification Set Register 4 */
+#define P10_OMSR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR4*)0xF003B074u)
+
+/** \brief 78, Port Output Modification Set Register 8 */
+#define P10_OMSR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR8*)0xF003B078u)
+
+/** \brief 0, Port Output Register */
+#define P10_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003B000u)
+
+/** \brief 40, Port Pad Driver Mode 0 Register */
+#define P10_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003B040u)
+
+/** \brief 44, Port Pad Driver Mode 1 Register */
+#define P10_PDR1 /*lint --e(923)*/ (*(volatile Ifx_P_PDR1*)0xF003B044u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_P11
+ * \{ */
+
+/** \brief FC, Port Access Enable Register 0 */
+#define P11_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003B1FCu)
+
+/** \brief F8, Port Access Enable Register 1 */
+#define P11_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003B1F8u)
+
+/** \brief 50, Port Emergency Stop Register */
+#define P11_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003B150u)
+
+/** \brief 8, Identification Register */
+#define P11_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003B108u)
+
+/** \brief 24, Port Input Register */
+#define P11_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003B124u)
+
+/** \brief 10, Port Input/Output Control Register 0 */
+#define P11_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003B110u)
+
+/** \brief 1C, Port Input/Output Control Register 12 */
+#define P11_IOCR12 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR12*)0xF003B11Cu)
+
+/** \brief 14, Port Input/Output Control Register 4 */
+#define P11_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003B114u)
+
+/** \brief 18, Port Input/Output Control Register 8 */
+#define P11_IOCR8 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR8*)0xF003B118u)
+
+/** \brief 94, Port Output Modification Clear Register */
+#define P11_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003B194u)
+
+/** \brief 80, Port Output Modification Clear Register 0 */
+#define P11_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003B180u)
+
+/** \brief 8C, Port Output Modification Clear Register 12 */
+#define P11_OMCR12 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR12*)0xF003B18Cu)
+
+/** \brief 84, Port Output Modification Clear Register 4 */
+#define P11_OMCR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR4*)0xF003B184u)
+
+/** \brief 88, Port Output Modification Clear Register 8 */
+#define P11_OMCR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR8*)0xF003B188u)
+
+/** \brief 4, Port Output Modification Register */
+#define P11_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003B104u)
+
+/** \brief 90, Port Output Modification Set Register */
+#define P11_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003B190u)
+
+/** \brief 70, Port Output Modification Set Register 0 */
+#define P11_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003B170u)
+
+/** \brief 7C, Port Output Modification Set Register 12 */
+#define P11_OMSR12 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR12*)0xF003B17Cu)
+
+/** \brief 74, Port Output Modification Set Register 4 */
+#define P11_OMSR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR4*)0xF003B174u)
+
+/** \brief 78, Port Output Modification Set Register 8 */
+#define P11_OMSR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR8*)0xF003B178u)
+
+/** \brief 0, Port Output Register */
+#define P11_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003B100u)
+
+/** \brief 64, Port Pin Controller Select Register */
+#define P11_PCSR /*lint --e(923)*/ (*(volatile Ifx_P_PCSR*)0xF003B164u)
+
+/** \brief 40, Port Pad Driver Mode 0 Register */
+#define P11_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003B140u)
+
+/** \brief 44, Port Pad Driver Mode 1 Register */
+#define P11_PDR1 /*lint --e(923)*/ (*(volatile Ifx_P_PDR1*)0xF003B144u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_P13
+ * \{ */
+
+/** \brief FC, Port Access Enable Register 0 */
+#define P13_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003B3FCu)
+
+/** \brief F8, Port Access Enable Register 1 */
+#define P13_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003B3F8u)
+
+/** \brief 50, Port Emergency Stop Register */
+#define P13_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003B350u)
+
+/** \brief 8, Identification Register */
+#define P13_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003B308u)
+
+/** \brief 24, Port Input Register */
+#define P13_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003B324u)
+
+/** \brief 10, Port Input/Output Control Register 0 */
+#define P13_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003B310u)
+
+/** \brief A0, Port LVDS Pad Control Register 0 */
+#define P13_LPCR0 /*lint --e(923)*/ (*(volatile Ifx_P_LPCR0*)0xF003B3A0u)
+
+/** \brief A4, Port LVDS Pad Control Register 1 */
+#define P13_LPCR1 /*lint --e(923)*/ (*(volatile Ifx_P_LPCR1*)0xF003B3A4u)
+
+/** \brief 94, Port Output Modification Clear Register */
+#define P13_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003B394u)
+
+/** \brief 80, Port Output Modification Clear Register 0 */
+#define P13_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003B380u)
+
+/** \brief 4, Port Output Modification Register */
+#define P13_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003B304u)
+
+/** \brief 90, Port Output Modification Set Register */
+#define P13_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003B390u)
+
+/** \brief 70, Port Output Modification Set Register 0 */
+#define P13_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003B370u)
+
+/** \brief 0, Port Output Register */
+#define P13_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003B300u)
+
+/** \brief 40, Port Pad Driver Mode 0 Register */
+#define P13_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003B340u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_P14
+ * \{ */
+
+/** \brief FC, Port Access Enable Register 0 */
+#define P14_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003B4FCu)
+
+/** \brief F8, Port Access Enable Register 1 */
+#define P14_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003B4F8u)
+
+/** \brief 50, Port Emergency Stop Register */
+#define P14_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003B450u)
+
+/** \brief 8, Identification Register */
+#define P14_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003B408u)
+
+/** \brief 24, Port Input Register */
+#define P14_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003B424u)
+
+/** \brief 10, Port Input/Output Control Register 0 */
+#define P14_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003B410u)
+
+/** \brief 14, Port Input/Output Control Register 4 */
+#define P14_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003B414u)
+
+/** \brief 18, Port Input/Output Control Register 8 */
+#define P14_IOCR8 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR8*)0xF003B418u)
+
+/** \brief 94, Port Output Modification Clear Register */
+#define P14_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003B494u)
+
+/** \brief 80, Port Output Modification Clear Register 0 */
+#define P14_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003B480u)
+
+/** \brief 84, Port Output Modification Clear Register 4 */
+#define P14_OMCR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR4*)0xF003B484u)
+
+/** \brief 88, Port Output Modification Clear Register 8 */
+#define P14_OMCR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR8*)0xF003B488u)
+
+/** \brief 4, Port Output Modification Register */
+#define P14_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003B404u)
+
+/** \brief 90, Port Output Modification Set Register */
+#define P14_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003B490u)
+
+/** \brief 70, Port Output Modification Set Register 0 */
+#define P14_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003B470u)
+
+/** \brief 74, Port Output Modification Set Register 4 */
+#define P14_OMSR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR4*)0xF003B474u)
+
+/** \brief 78, Port Output Modification Set Register 8 */
+#define P14_OMSR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR8*)0xF003B478u)
+
+/** \brief 0, Port Output Register */
+#define P14_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003B400u)
+
+/** \brief 40, Port Pad Driver Mode 0 Register */
+#define P14_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003B440u)
+
+/** \brief 44, Port Pad Driver Mode 1 Register */
+#define P14_PDR1 /*lint --e(923)*/ (*(volatile Ifx_P_PDR1*)0xF003B444u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_P15
+ * \{ */
+
+/** \brief FC, Port Access Enable Register 0 */
+#define P15_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003B5FCu)
+
+/** \brief F8, Port Access Enable Register 1 */
+#define P15_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003B5F8u)
+
+/** \brief 50, Port Emergency Stop Register */
+#define P15_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003B550u)
+
+/** \brief 8, Identification Register */
+#define P15_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003B508u)
+
+/** \brief 24, Port Input Register */
+#define P15_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003B524u)
+
+/** \brief 10, Port Input/Output Control Register 0 */
+#define P15_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003B510u)
+
+/** \brief 14, Port Input/Output Control Register 4 */
+#define P15_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003B514u)
+
+/** \brief 18, Port Input/Output Control Register 8 */
+#define P15_IOCR8 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR8*)0xF003B518u)
+
+/** \brief 94, Port Output Modification Clear Register */
+#define P15_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003B594u)
+
+/** \brief 80, Port Output Modification Clear Register 0 */
+#define P15_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003B580u)
+
+/** \brief 84, Port Output Modification Clear Register 4 */
+#define P15_OMCR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR4*)0xF003B584u)
+
+/** \brief 88, Port Output Modification Clear Register 8 */
+#define P15_OMCR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR8*)0xF003B588u)
+
+/** \brief 4, Port Output Modification Register */
+#define P15_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003B504u)
+
+/** \brief 90, Port Output Modification Set Register */
+#define P15_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003B590u)
+
+/** \brief 70, Port Output Modification Set Register 0 */
+#define P15_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003B570u)
+
+/** \brief 74, Port Output Modification Set Register 4 */
+#define P15_OMSR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR4*)0xF003B574u)
+
+/** \brief 78, Port Output Modification Set Register 8 */
+#define P15_OMSR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR8*)0xF003B578u)
+
+/** \brief 0, Port Output Register */
+#define P15_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003B500u)
+
+/** \brief 40, Port Pad Driver Mode 0 Register */
+#define P15_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003B540u)
+
+/** \brief 44, Port Pad Driver Mode 1 Register */
+#define P15_PDR1 /*lint --e(923)*/ (*(volatile Ifx_P_PDR1*)0xF003B544u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_P20
+ * \{ */
+
+/** \brief FC, Port Access Enable Register 0 */
+#define P20_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003C0FCu)
+
+/** \brief F8, Port Access Enable Register 1 */
+#define P20_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003C0F8u)
+
+/** \brief 50, Port Emergency Stop Register */
+#define P20_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003C050u)
+
+/** \brief 8, Identification Register */
+#define P20_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003C008u)
+
+/** \brief 24, Port Input Register */
+#define P20_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003C024u)
+
+/** \brief 10, Port Input/Output Control Register 0 */
+#define P20_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003C010u)
+
+/** \brief 1C, Port Input/Output Control Register 12 */
+#define P20_IOCR12 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR12*)0xF003C01Cu)
+
+/** \brief 14, Port Input/Output Control Register 4 */
+#define P20_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003C014u)
+
+/** \brief 18, Port Input/Output Control Register 8 */
+#define P20_IOCR8 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR8*)0xF003C018u)
+
+/** \brief 94, Port Output Modification Clear Register */
+#define P20_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003C094u)
+
+/** \brief 80, Port Output Modification Clear Register 0 */
+#define P20_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003C080u)
+
+/** \brief 8C, Port Output Modification Clear Register 12 */
+#define P20_OMCR12 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR12*)0xF003C08Cu)
+
+/** \brief 84, Port Output Modification Clear Register 4 */
+#define P20_OMCR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR4*)0xF003C084u)
+
+/** \brief 88, Port Output Modification Clear Register 8 */
+#define P20_OMCR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR8*)0xF003C088u)
+
+/** \brief 4, Port Output Modification Register */
+#define P20_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003C004u)
+
+/** \brief 90, Port Output Modification Set Register */
+#define P20_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003C090u)
+
+/** \brief 70, Port Output Modification Set Register 0 */
+#define P20_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003C070u)
+
+/** \brief 7C, Port Output Modification Set Register 12 */
+#define P20_OMSR12 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR12*)0xF003C07Cu)
+
+/** \brief 74, Port Output Modification Set Register 4 */
+#define P20_OMSR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR4*)0xF003C074u)
+
+/** \brief 78, Port Output Modification Set Register 8 */
+#define P20_OMSR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR8*)0xF003C078u)
+
+/** \brief 0, Port Output Register */
+#define P20_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003C000u)
+
+/** \brief 40, Port Pad Driver Mode 0 Register */
+#define P20_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003C040u)
+
+/** \brief 44, Port Pad Driver Mode 1 Register */
+#define P20_PDR1 /*lint --e(923)*/ (*(volatile Ifx_P_PDR1*)0xF003C044u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_P21
+ * \{ */
+
+/** \brief FC, Port Access Enable Register 0 */
+#define P21_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003C1FCu)
+
+/** \brief F8, Port Access Enable Register 1 */
+#define P21_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003C1F8u)
+
+/** \brief 50, Port Emergency Stop Register */
+#define P21_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003C150u)
+
+/** \brief 8, Identification Register */
+#define P21_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003C108u)
+
+/** \brief 24, Port Input Register */
+#define P21_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003C124u)
+
+/** \brief 10, Port Input/Output Control Register 0 */
+#define P21_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003C110u)
+
+/** \brief 14, Port Input/Output Control Register 4 */
+#define P21_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003C114u)
+
+/** \brief A4, Port LVDS Pad Control Register 1 */
+#define P21_LPCR1 /*lint --e(923)*/ (*(volatile Ifx_P_LPCR1*)0xF003C1A4u)
+
+/** \brief A8, Port LVDS Pad Control Register 2 */
+#define P21_LPCR2 /*lint --e(923)*/ (*(volatile Ifx_P_LPCR2*)0xF003C1A8u)
+
+/** \brief 94, Port Output Modification Clear Register */
+#define P21_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003C194u)
+
+/** \brief 80, Port Output Modification Clear Register 0 */
+#define P21_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003C180u)
+
+/** \brief 84, Port Output Modification Clear Register 4 */
+#define P21_OMCR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR4*)0xF003C184u)
+
+/** \brief 4, Port Output Modification Register */
+#define P21_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003C104u)
+
+/** \brief 90, Port Output Modification Set Register */
+#define P21_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003C190u)
+
+/** \brief 70, Port Output Modification Set Register 0 */
+#define P21_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003C170u)
+
+/** \brief 74, Port Output Modification Set Register 4 */
+#define P21_OMSR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR4*)0xF003C174u)
+
+/** \brief 0, Port Output Register */
+#define P21_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003C100u)
+
+/** \brief 40, Port Pad Driver Mode 0 Register */
+#define P21_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003C140u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_P22
+ * \{ */
+
+/** \brief FC, Port Access Enable Register 0 */
+#define P22_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003C2FCu)
+
+/** \brief F8, Port Access Enable Register 1 */
+#define P22_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003C2F8u)
+
+/** \brief 50, Port Emergency Stop Register */
+#define P22_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003C250u)
+
+/** \brief 8, Identification Register */
+#define P22_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003C208u)
+
+/** \brief 24, Port Input Register */
+#define P22_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003C224u)
+
+/** \brief 10, Port Input/Output Control Register 0 */
+#define P22_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003C210u)
+
+/** \brief A0, Port LVDS Pad Control Register 0 */
+#define P22_LPCR0 /*lint --e(923)*/ (*(volatile Ifx_P_LPCR0*)0xF003C2A0u)
+
+/** \brief A4, Port LVDS Pad Control Register 1 */
+#define P22_LPCR1 /*lint --e(923)*/ (*(volatile Ifx_P_LPCR1*)0xF003C2A4u)
+
+/** \brief 94, Port Output Modification Clear Register */
+#define P22_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003C294u)
+
+/** \brief 80, Port Output Modification Clear Register 0 */
+#define P22_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003C280u)
+
+/** \brief 4, Port Output Modification Register */
+#define P22_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003C204u)
+
+/** \brief 90, Port Output Modification Set Register */
+#define P22_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003C290u)
+
+/** \brief 70, Port Output Modification Set Register 0 */
+#define P22_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003C270u)
+
+/** \brief 0, Port Output Register */
+#define P22_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003C200u)
+
+/** \brief 40, Port Pad Driver Mode 0 Register */
+#define P22_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003C240u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_P23
+ * \{ */
+
+/** \brief FC, Port Access Enable Register 0 */
+#define P23_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003C3FCu)
+
+/** \brief F8, Port Access Enable Register 1 */
+#define P23_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003C3F8u)
+
+/** \brief 50, Port Emergency Stop Register */
+#define P23_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003C350u)
+
+/** \brief 8, Identification Register */
+#define P23_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003C308u)
+
+/** \brief 24, Port Input Register */
+#define P23_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003C324u)
+
+/** \brief 10, Port Input/Output Control Register 0 */
+#define P23_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003C310u)
+
+/** \brief 14, Port Input/Output Control Register 4 */
+#define P23_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003C314u)
+
+/** \brief 94, Port Output Modification Clear Register */
+#define P23_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003C394u)
+
+/** \brief 80, Port Output Modification Clear Register 0 */
+#define P23_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003C380u)
+
+/** \brief 4, Port Output Modification Register */
+#define P23_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003C304u)
+
+/** \brief 90, Port Output Modification Set Register */
+#define P23_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003C390u)
+
+/** \brief 70, Port Output Modification Set Register 0 */
+#define P23_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003C370u)
+
+/** \brief 0, Port Output Register */
+#define P23_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003C300u)
+
+/** \brief 40, Port Pad Driver Mode 0 Register */
+#define P23_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003C340u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_P32
+ * \{ */
+
+/** \brief FC, Port Access Enable Register 0 */
+#define P32_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003D2FCu)
+
+/** \brief F8, Port Access Enable Register 1 */
+#define P32_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003D2F8u)
+
+/** \brief 50, Port Emergency Stop Register */
+#define P32_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003D250u)
+
+/** \brief 8, Identification Register */
+#define P32_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003D208u)
+
+/** \brief 24, Port Input Register */
+#define P32_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003D224u)
+
+/** \brief 10, Port Input/Output Control Register 0 */
+#define P32_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003D210u)
+
+/** \brief 14, Port Input/Output Control Register 4 */
+#define P32_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003D214u)
+
+/** \brief 94, Port Output Modification Clear Register */
+#define P32_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003D294u)
+
+/** \brief 80, Port Output Modification Clear Register 0 */
+#define P32_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003D280u)
+
+/** \brief 84, Port Output Modification Clear Register 4 */
+#define P32_OMCR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR4*)0xF003D284u)
+
+/** \brief 4, Port Output Modification Register */
+#define P32_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003D204u)
+
+/** \brief 90, Port Output Modification Set Register */
+#define P32_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003D290u)
+
+/** \brief 70, Port Output Modification Set Register 0 */
+#define P32_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003D270u)
+
+/** \brief 74, Port Output Modification Set Register 4 */
+#define P32_OMSR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR4*)0xF003D274u)
+
+/** \brief 0, Port Output Register */
+#define P32_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003D200u)
+
+/** \brief 40, Port Pad Driver Mode 0 Register */
+#define P32_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003D240u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_P33
+ * \{ */
+
+/** \brief FC, Port Access Enable Register 0 */
+#define P33_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003D3FCu)
+
+/** \brief F8, Port Access Enable Register 1 */
+#define P33_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003D3F8u)
+
+/** \brief 50, Port Emergency Stop Register */
+#define P33_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003D350u)
+
+/** \brief 8, Identification Register */
+#define P33_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003D308u)
+
+/** \brief 24, Port Input Register */
+#define P33_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003D324u)
+
+/** \brief 10, Port Input/Output Control Register 0 */
+#define P33_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003D310u)
+
+/** \brief 1C, Port Input/Output Control Register 12 */
+#define P33_IOCR12 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR12*)0xF003D31Cu)
+
+/** \brief 14, Port Input/Output Control Register 4 */
+#define P33_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003D314u)
+
+/** \brief 18, Port Input/Output Control Register 8 */
+#define P33_IOCR8 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR8*)0xF003D318u)
+
+/** \brief 94, Port Output Modification Clear Register */
+#define P33_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003D394u)
+
+/** \brief 80, Port Output Modification Clear Register 0 */
+#define P33_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003D380u)
+
+/** \brief 8C, Port Output Modification Clear Register 12 */
+#define P33_OMCR12 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR12*)0xF003D38Cu)
+
+/** \brief 84, Port Output Modification Clear Register 4 */
+#define P33_OMCR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR4*)0xF003D384u)
+
+/** \brief 88, Port Output Modification Clear Register 8 */
+#define P33_OMCR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR8*)0xF003D388u)
+
+/** \brief 4, Port Output Modification Register */
+#define P33_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003D304u)
+
+/** \brief 90, Port Output Modification Set Register */
+#define P33_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003D390u)
+
+/** \brief 70, Port Output Modification Set Register 0 */
+#define P33_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003D370u)
+
+/** \brief 7C, Port Output Modification Set Register 12 */
+#define P33_OMSR12 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR12*)0xF003D37Cu)
+
+/** \brief 74, Port Output Modification Set Register 4 */
+#define P33_OMSR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR4*)0xF003D374u)
+
+/** \brief 78, Port Output Modification Set Register 8 */
+#define P33_OMSR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR8*)0xF003D378u)
+
+/** \brief 0, Port Output Register */
+#define P33_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003D300u)
+
+/** \brief 40, Port Pad Driver Mode 0 Register */
+#define P33_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003D340u)
+
+/** \brief 44, Port Pad Driver Mode 1 Register */
+#define P33_PDR1 /*lint --e(923)*/ (*(volatile Ifx_P_PDR1*)0xF003D344u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_P40
+ * \{ */
+
+/** \brief FC, Port Access Enable Register 0 */
+#define P40_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003E0FCu)
+
+/** \brief F8, Port Access Enable Register 1 */
+#define P40_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003E0F8u)
+
+/** \brief 8, Identification Register */
+#define P40_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003E008u)
+
+/** \brief 24, Port Input Register */
+#define P40_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003E024u)
+
+/** \brief 10, Port Input/Output Control Register 0 */
+#define P40_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003E010u)
+
+/** \brief 14, Port Input/Output Control Register 4 */
+#define P40_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003E014u)
+
+/** \brief 18, Port Input/Output Control Register 8 */
+#define P40_IOCR8 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR8*)0xF003E018u)
+
+/** \brief 64, Port Pin Controller Select Register */
+#define P40_PCSR /*lint --e(923)*/ (*(volatile Ifx_P_PCSR*)0xF003E064u)
+
+/** \brief 60, Port Pin Function Decision Control Register */
+#define P40_PDISC /*lint --e(923)*/ (*(volatile Ifx_P_PDISC*)0xF003E060u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXPORT_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPort_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPort_regdef.h
new file mode 100644
index 0000000..eec87bb
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPort_regdef.h
@@ -0,0 +1,785 @@
+/**
+ * \file IfxPort_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Port Port
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Port_Bitfields Bitfields
+ * \ingroup IfxLld_Port
+ *
+ * \defgroup IfxLld_Port_union Union
+ * \ingroup IfxLld_Port
+ *
+ * \defgroup IfxLld_Port_struct Struct
+ * \ingroup IfxLld_Port
+ *
+ */
+#ifndef IFXPORT_REGDEF_H
+#define IFXPORT_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Bitfields
+ * \{ */
+
+/** \brief Port Access Enable Register 0 */
+typedef struct _Ifx_P_ACCEN0_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID n (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID n (rw) */
+} Ifx_P_ACCEN0_Bits;
+
+/** \brief Port Access Enable Register 1 */
+typedef struct _Ifx_P_ACCEN1_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_P_ACCEN1_Bits;
+
+/** \brief Port Emergency Stop Register */
+typedef struct _Ifx_P_ESR_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Emergency Stop Enable for Port n Pin 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Emergency Stop Enable for Port n Pin 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Emergency Stop Enable for Port n Pin 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Emergency Stop Enable for Port n Pin 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Emergency Stop Enable for Port n Pin 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Emergency Stop Enable for Port n Pin 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Emergency Stop Enable for Port n Pin 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Emergency Stop Enable for Port n Pin 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Emergency Stop Enable for Port n Pin 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Emergency Stop Enable for Port n Pin 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Emergency Stop Enable for Port n Pin 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Emergency Stop Enable for Port n Pin 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Emergency Stop Enable for Port n Pin 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Emergency Stop Enable for Port n Pin 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Emergency Stop Enable for Port n Pin 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Emergency Stop Enable for Port n Pin 15 (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_P_ESR_Bits;
+
+/** \brief Identification Register */
+typedef struct _Ifx_P_ID_Bits
+{
+ unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
+ unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_P_ID_Bits;
+
+/** \brief Port Input Register */
+typedef struct _Ifx_P_IN_Bits
+{
+ unsigned int P0:1; /**< \brief [0:0] Port n Input Bit 0 (rh) */
+ unsigned int P1:1; /**< \brief [1:1] Port n Input Bit 1 (rh) */
+ unsigned int P2:1; /**< \brief [2:2] Port n Input Bit 2 (rh) */
+ unsigned int P3:1; /**< \brief [3:3] Port n Input Bit 3 (rh) */
+ unsigned int P4:1; /**< \brief [4:4] Port n Input Bit 4 (rh) */
+ unsigned int P5:1; /**< \brief [5:5] Port n Input Bit 5 (rh) */
+ unsigned int P6:1; /**< \brief [6:6] Port n Input Bit 6 (rh) */
+ unsigned int P7:1; /**< \brief [7:7] Port n Input Bit 7 (rh) */
+ unsigned int P8:1; /**< \brief [8:8] Port n Input Bit 8 (rh) */
+ unsigned int P9:1; /**< \brief [9:9] Port n Input Bit 9 (rh) */
+ unsigned int P10:1; /**< \brief [10:10] Port n Input Bit 10 (rh) */
+ unsigned int P11:1; /**< \brief [11:11] Port n Input Bit 11 (rh) */
+ unsigned int P12:1; /**< \brief [12:12] Port n Input Bit 12 (rh) */
+ unsigned int P13:1; /**< \brief [13:13] Port n Input Bit 13 (rh) */
+ unsigned int P14:1; /**< \brief [14:14] Port n Input Bit 14 (rh) */
+ unsigned int P15:1; /**< \brief [15:15] Port n Input Bit 15 (rh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_P_IN_Bits;
+
+/** \brief Port Input/Output Control Register 0 */
+typedef struct _Ifx_P_IOCR0_Bits
+{
+ unsigned int reserved_0:3; /**< \brief \internal Reserved */
+ unsigned int PC0:5; /**< \brief [7:3] (rw) */
+ unsigned int reserved_8:3; /**< \brief \internal Reserved */
+ unsigned int PC1:5; /**< \brief [15:11] (rw) */
+ unsigned int reserved_16:3; /**< \brief \internal Reserved */
+ unsigned int PC2:5; /**< \brief [23:19] (rw) */
+ unsigned int reserved_24:3; /**< \brief \internal Reserved */
+ unsigned int PC3:5; /**< \brief [31:27] (rw) */
+} Ifx_P_IOCR0_Bits;
+
+/** \brief Port Input/Output Control Register 12 */
+typedef struct _Ifx_P_IOCR12_Bits
+{
+ unsigned int reserved_0:3; /**< \brief \internal Reserved */
+ unsigned int PC12:5; /**< \brief [7:3] (rw) */
+ unsigned int reserved_8:3; /**< \brief \internal Reserved */
+ unsigned int PC13:5; /**< \brief [15:11] (rw) */
+ unsigned int reserved_16:3; /**< \brief \internal Reserved */
+ unsigned int PC14:5; /**< \brief [23:19] (rw) */
+ unsigned int reserved_24:3; /**< \brief \internal Reserved */
+ unsigned int PC15:5; /**< \brief [31:27] (rw) */
+} Ifx_P_IOCR12_Bits;
+
+/** \brief Port Input/Output Control Register 4 */
+typedef struct _Ifx_P_IOCR4_Bits
+{
+ unsigned int reserved_0:3; /**< \brief \internal Reserved */
+ unsigned int PC4:5; /**< \brief [7:3] (rw) */
+ unsigned int reserved_8:3; /**< \brief \internal Reserved */
+ unsigned int PC5:5; /**< \brief [15:11] (rw) */
+ unsigned int reserved_16:3; /**< \brief \internal Reserved */
+ unsigned int PC6:5; /**< \brief [23:19] (rw) */
+ unsigned int reserved_24:3; /**< \brief \internal Reserved */
+ unsigned int PC7:5; /**< \brief [31:27] (rw) */
+} Ifx_P_IOCR4_Bits;
+
+/** \brief Port Input/Output Control Register 8 */
+typedef struct _Ifx_P_IOCR8_Bits
+{
+ unsigned int reserved_0:3; /**< \brief \internal Reserved */
+ unsigned int PC8:5; /**< \brief [7:3] (rw) */
+ unsigned int reserved_8:3; /**< \brief \internal Reserved */
+ unsigned int PC9:5; /**< \brief [15:11] (rw) */
+ unsigned int reserved_16:3; /**< \brief \internal Reserved */
+ unsigned int PC10:5; /**< \brief [23:19] (rw) */
+ unsigned int reserved_24:3; /**< \brief \internal Reserved */
+ unsigned int PC11:5; /**< \brief [31:27] (rw) */
+} Ifx_P_IOCR8_Bits;
+
+/** \brief Port LVDS Pad Control Register 0 */
+typedef struct _Ifx_P_LPCR0_Bits
+{
+ unsigned int reserved_0:1; /**< \brief \internal Reserved */
+ unsigned int PS1:1; /**< \brief [1:1] Pad Supply for pins [1:0] (rw) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_P_LPCR0_Bits;
+
+/** \brief Port LVDS Pad Control Register 1 */
+typedef struct _Ifx_P_LPCR1_Bits
+{
+ unsigned int reserved_0:1; /**< \brief \internal Reserved */
+ unsigned int PS1:1; /**< \brief [1:1] Pad Supply for pins [3:2] (rw) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_P_LPCR1_Bits;
+
+/** \brief Port LVDS Pad Control Register 1 */
+typedef struct _Ifx_P_LPCR1_P21_Bits
+{
+ unsigned int RDIS_CTRL:1; /**< \brief [0:0] LVDS RX_DIS controller (rw) */
+ unsigned int RX_DIS:1; /**< \brief [1:1] Disable Receive LVDS (rw) */
+ unsigned int TERM:1; /**< \brief [2:2] Select Receiver Termination Mode (rw) */
+ unsigned int LRXTERM:5; /**< \brief [7:3] LVDS RX Poly-resistor configuration value (rw) */
+ unsigned int reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_P_LPCR1_P21_Bits;
+
+/** \brief Port LVDS Pad Control Register 2 */
+typedef struct _Ifx_P_LPCR2_Bits
+{
+ unsigned int reserved_0:8; /**< \brief \internal Reserved */
+ unsigned int LVDSR:1; /**< \brief [8:8] Special reduced LVDS electrical signaling mode (rw) */
+ unsigned int LVDSRL:1; /**< \brief [9:9] LVDS IEEE electrical signaling mode (rw) */
+ unsigned int reserved_10:2; /**< \brief \internal Reserved */
+ unsigned int TDIS_CTRL:1; /**< \brief [12:12] LVDS TX_DIS controller (rw) */
+ unsigned int TX_DIS:1; /**< \brief [13:13] Disable Transmit LVDS (rw) */
+ unsigned int TX_PD:1; /**< \brief [14:14] LVDS Power Down (rw) */
+ unsigned int TX_PWDPD:1; /**< \brief [15:15] Disable TX Power down pull down. (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_P_LPCR2_Bits;
+
+/** \brief Port Output Modification Clear Register 0 */
+typedef struct _Ifx_P_OMCR0_Bits
+{
+ unsigned int reserved_0:16; /**< \brief \internal Reserved */
+ unsigned int PCL0:1; /**< \brief [16:16] Port n Clear Bit 0 (w) */
+ unsigned int PCL1:1; /**< \brief [17:17] Port n Clear Bit 1 (w) */
+ unsigned int PCL2:1; /**< \brief [18:18] Port n Clear Bit 2 (w) */
+ unsigned int PCL3:1; /**< \brief [19:19] Port n Clear Bit 3 (w) */
+ unsigned int reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_P_OMCR0_Bits;
+
+/** \brief Port Output Modification Clear Register 12 */
+typedef struct _Ifx_P_OMCR12_Bits
+{
+ unsigned int reserved_0:28; /**< \brief \internal Reserved */
+ unsigned int PCL12:1; /**< \brief [28:28] Port n Clear Bit 12 (w) */
+ unsigned int PCL13:1; /**< \brief [29:29] Port n Clear Bit 13 (w) */
+ unsigned int PCL14:1; /**< \brief [30:30] Port n Clear Bit 14 (w) */
+ unsigned int PCL15:1; /**< \brief [31:31] Port n Clear Bit 15 (w) */
+} Ifx_P_OMCR12_Bits;
+
+/** \brief Port Output Modification Clear Register 4 */
+typedef struct _Ifx_P_OMCR4_Bits
+{
+ unsigned int reserved_0:20; /**< \brief \internal Reserved */
+ unsigned int PCL4:1; /**< \brief [20:20] Port n Clear Bit 4 (w) */
+ unsigned int PCL5:1; /**< \brief [21:21] Port n Clear Bit 5 (w) */
+ unsigned int PCL6:1; /**< \brief [22:22] Port n Clear Bit 6 (w) */
+ unsigned int PCL7:1; /**< \brief [23:23] Port n Clear Bit 7 (w) */
+ unsigned int reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_P_OMCR4_Bits;
+
+/** \brief Port Output Modification Clear Register 8 */
+typedef struct _Ifx_P_OMCR8_Bits
+{
+ unsigned int reserved_0:24; /**< \brief \internal Reserved */
+ unsigned int PCL8:1; /**< \brief [24:24] Port n Clear Bit 8 (w) */
+ unsigned int PCL9:1; /**< \brief [25:25] Port n Clear Bit 9 (w) */
+ unsigned int PCL10:1; /**< \brief [26:26] Port n Clear Bit 10 (w) */
+ unsigned int PCL11:1; /**< \brief [27:27] Port n Clear Bit 11 (w) */
+ unsigned int reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_P_OMCR8_Bits;
+
+/** \brief Port Output Modification Clear Register */
+typedef struct _Ifx_P_OMCR_Bits
+{
+ unsigned int reserved_0:16; /**< \brief \internal Reserved */
+ unsigned int PCL0:1; /**< \brief [16:16] Port n Clear Bit 0 (w) */
+ unsigned int PCL1:1; /**< \brief [17:17] Port n Clear Bit 1 (w) */
+ unsigned int PCL2:1; /**< \brief [18:18] Port n Clear Bit 2 (w) */
+ unsigned int PCL3:1; /**< \brief [19:19] Port n Clear Bit 3 (w) */
+ unsigned int PCL4:1; /**< \brief [20:20] Port n Clear Bit 4 (w) */
+ unsigned int PCL5:1; /**< \brief [21:21] Port n Clear Bit 5 (w) */
+ unsigned int PCL6:1; /**< \brief [22:22] Port n Clear Bit 6 (w) */
+ unsigned int PCL7:1; /**< \brief [23:23] Port n Clear Bit 7 (w) */
+ unsigned int PCL8:1; /**< \brief [24:24] Port n Clear Bit 8 (w) */
+ unsigned int PCL9:1; /**< \brief [25:25] Port n Clear Bit 9 (w) */
+ unsigned int PCL10:1; /**< \brief [26:26] Port n Clear Bit 10 (w) */
+ unsigned int PCL11:1; /**< \brief [27:27] Port n Clear Bit 11 (w) */
+ unsigned int PCL12:1; /**< \brief [28:28] Port n Clear Bit 12 (w) */
+ unsigned int PCL13:1; /**< \brief [29:29] Port n Clear Bit 13 (w) */
+ unsigned int PCL14:1; /**< \brief [30:30] Port n Clear Bit 14 (w) */
+ unsigned int PCL15:1; /**< \brief [31:31] Port n Clear Bit 15 (w) */
+} Ifx_P_OMCR_Bits;
+
+/** \brief Port Output Modification Register */
+typedef struct _Ifx_P_OMR_Bits
+{
+ unsigned int PS0:1; /**< \brief [0:0] (w) */
+ unsigned int PS1:1; /**< \brief [1:1] (w) */
+ unsigned int PS2:1; /**< \brief [2:2] (w) */
+ unsigned int PS3:1; /**< \brief [3:3] (w) */
+ unsigned int PS4:1; /**< \brief [4:4] (w) */
+ unsigned int PS5:1; /**< \brief [5:5] (w) */
+ unsigned int PS6:1; /**< \brief [6:6] (w) */
+ unsigned int PS7:1; /**< \brief [7:7] (w) */
+ unsigned int PS8:1; /**< \brief [8:8] (w) */
+ unsigned int PS9:1; /**< \brief [9:9] (w) */
+ unsigned int PS10:1; /**< \brief [10:10] (w) */
+ unsigned int PS11:1; /**< \brief [11:11] (w) */
+ unsigned int PS12:1; /**< \brief [12:12] (w) */
+ unsigned int PS13:1; /**< \brief [13:13] (w) */
+ unsigned int PS14:1; /**< \brief [14:14] (w) */
+ unsigned int PS15:1; /**< \brief [15:15] (w) */
+ unsigned int PCL0:1; /**< \brief [16:16] (w) */
+ unsigned int PCL1:1; /**< \brief [17:17] (w) */
+ unsigned int PCL2:1; /**< \brief [18:18] (w) */
+ unsigned int PCL3:1; /**< \brief [19:19] (w) */
+ unsigned int PCL4:1; /**< \brief [20:20] (w) */
+ unsigned int PCL5:1; /**< \brief [21:21] (w) */
+ unsigned int PCL6:1; /**< \brief [22:22] (w) */
+ unsigned int PCL7:1; /**< \brief [23:23] (w) */
+ unsigned int PCL8:1; /**< \brief [24:24] (w) */
+ unsigned int PCL9:1; /**< \brief [25:25] (w) */
+ unsigned int PCL10:1; /**< \brief [26:26] (w) */
+ unsigned int PCL11:1; /**< \brief [27:27] (w) */
+ unsigned int PCL12:1; /**< \brief [28:28] (w) */
+ unsigned int PCL13:1; /**< \brief [29:29] (w) */
+ unsigned int PCL14:1; /**< \brief [30:30] (w) */
+ unsigned int PCL15:1; /**< \brief [31:31] (w) */
+} Ifx_P_OMR_Bits;
+
+/** \brief Port Output Modification Set Register 0 */
+typedef struct _Ifx_P_OMSR0_Bits
+{
+ unsigned int PS0:1; /**< \brief [0:0] Port n Set Bit 0 (w) */
+ unsigned int PS1:1; /**< \brief [1:1] Port n Set Bit 1 (w) */
+ unsigned int PS2:1; /**< \brief [2:2] Port n Set Bit 2 (w) */
+ unsigned int PS3:1; /**< \brief [3:3] Port n Set Bit 3 (w) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_P_OMSR0_Bits;
+
+/** \brief Port Output Modification Set Register 12 */
+typedef struct _Ifx_P_OMSR12_Bits
+{
+ unsigned int reserved_0:12; /**< \brief \internal Reserved */
+ unsigned int PS12:1; /**< \brief [12:12] Port n Set Bit 12 (w) */
+ unsigned int PS13:1; /**< \brief [13:13] Port n Set Bit 13 (w) */
+ unsigned int PS14:1; /**< \brief [14:14] Port n Set Bit 14 (w) */
+ unsigned int PS15:1; /**< \brief [15:15] Port n Set Bit 15 (w) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_P_OMSR12_Bits;
+
+/** \brief Port Output Modification Set Register 4 */
+typedef struct _Ifx_P_OMSR4_Bits
+{
+ unsigned int reserved_0:4; /**< \brief \internal Reserved */
+ unsigned int PS4:1; /**< \brief [4:4] Port n Set Bit 4 (w) */
+ unsigned int PS5:1; /**< \brief [5:5] Port n Set Bit 5 (w) */
+ unsigned int PS6:1; /**< \brief [6:6] Port n Set Bit 6 (w) */
+ unsigned int PS7:1; /**< \brief [7:7] Port n Set Bit 7 (w) */
+ unsigned int reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_P_OMSR4_Bits;
+
+/** \brief Port Output Modification Set Register 8 */
+typedef struct _Ifx_P_OMSR8_Bits
+{
+ unsigned int reserved_0:8; /**< \brief \internal Reserved */
+ unsigned int PS8:1; /**< \brief [8:8] Port n Set Bit 8 (w) */
+ unsigned int PS9:1; /**< \brief [9:9] Port n Set Bit 9 (w) */
+ unsigned int PS10:1; /**< \brief [10:10] Port n Set Bit 10 (w) */
+ unsigned int PS11:1; /**< \brief [11:11] Port n Set Bit 11 (w) */
+ unsigned int reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_P_OMSR8_Bits;
+
+/** \brief Port Output Modification Set Register */
+typedef struct _Ifx_P_OMSR_Bits
+{
+ unsigned int PS0:1; /**< \brief [0:0] Port n Set Bit 0 (w) */
+ unsigned int PS1:1; /**< \brief [1:1] Port n Set Bit 1 (w) */
+ unsigned int PS2:1; /**< \brief [2:2] Port n Set Bit 2 (w) */
+ unsigned int PS3:1; /**< \brief [3:3] Port n Set Bit 3 (w) */
+ unsigned int PS4:1; /**< \brief [4:4] Port n Set Bit 4 (w) */
+ unsigned int PS5:1; /**< \brief [5:5] Port n Set Bit 5 (w) */
+ unsigned int PS6:1; /**< \brief [6:6] Port n Set Bit 6 (w) */
+ unsigned int PS7:1; /**< \brief [7:7] Port n Set Bit 7 (w) */
+ unsigned int PS8:1; /**< \brief [8:8] Port n Set Bit 8 (w) */
+ unsigned int PS9:1; /**< \brief [9:9] Port n Set Bit 9 (w) */
+ unsigned int PS10:1; /**< \brief [10:10] Port n Set Bit 10 (w) */
+ unsigned int PS11:1; /**< \brief [11:11] Port n Set Bit 11 (w) */
+ unsigned int PS12:1; /**< \brief [12:12] Port n Set Bit 12 (w) */
+ unsigned int PS13:1; /**< \brief [13:13] Port n Set Bit 13 (w) */
+ unsigned int PS14:1; /**< \brief [14:14] Port n Set Bit 14 (w) */
+ unsigned int PS15:1; /**< \brief [15:15] Port n Set Bit 15 (w) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_P_OMSR_Bits;
+
+/** \brief Port Output Register */
+typedef struct _Ifx_P_OUT_Bits
+{
+ unsigned int P0:1; /**< \brief [0:0] (rwh) */
+ unsigned int P1:1; /**< \brief [1:1] (rwh) */
+ unsigned int P2:1; /**< \brief [2:2] (rwh) */
+ unsigned int P3:1; /**< \brief [3:3] (rwh) */
+ unsigned int P4:1; /**< \brief [4:4] (rwh) */
+ unsigned int P5:1; /**< \brief [5:5] (rwh) */
+ unsigned int P6:1; /**< \brief [6:6] (rwh) */
+ unsigned int P7:1; /**< \brief [7:7] (rwh) */
+ unsigned int P8:1; /**< \brief [8:8] (rwh) */
+ unsigned int P9:1; /**< \brief [9:9] (rwh) */
+ unsigned int P10:1; /**< \brief [10:10] (rwh) */
+ unsigned int P11:1; /**< \brief [11:11] (rwh) */
+ unsigned int P12:1; /**< \brief [12:12] (rwh) */
+ unsigned int P13:1; /**< \brief [13:13] (rwh) */
+ unsigned int P14:1; /**< \brief [14:14] (rwh) */
+ unsigned int P15:1; /**< \brief [15:15] (rwh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_P_OUT_Bits;
+
+/** \brief Port Pin Controller Select Register */
+typedef struct _Ifx_P_PCSR_Bits
+{
+ unsigned int SEL0:1; /**< \brief [0:0] Pin Controller Select for Pin 0 (rw) */
+ unsigned int SEL1:1; /**< \brief [1:1] Pin Controller Select for Pin 1 (rw) */
+ unsigned int SEL2:1; /**< \brief [2:2] Pin Controller Select for Pin 2 (rw) */
+ unsigned int SEL3:1; /**< \brief [3:3] Pin Controller Select for Pin 3 (rw) */
+ unsigned int SEL4:1; /**< \brief [4:4] Pin Controller Select for Pin 4 (rw) */
+ unsigned int SEL5:1; /**< \brief [5:5] Pin Controller Select for Pin 5 (rw) */
+ unsigned int SEL6:1; /**< \brief [6:6] Pin Controller Select for Pin 6 (rw) */
+ unsigned int SEL7:1; /**< \brief [7:7] Pin Controller Select for Pin 7 (rw) */
+ unsigned int reserved_8:2; /**< \brief \internal Reserved */
+ unsigned int SEL10:1; /**< \brief [10:10] Pin Controller Select for Pin 10 (rw) */
+ unsigned int SEL11:1; /**< \brief [11:11] Pin Controller Select for Pin 11 (rw) */
+ unsigned int reserved_12:19; /**< \brief \internal Reserved */
+ unsigned int LCK:1; /**< \brief [31:31] Lock Status (rh) */
+} Ifx_P_PCSR_Bits;
+
+/** \brief Port Pin Function Decision Control Register */
+typedef struct _Ifx_P_PDISC_Bits
+{
+ unsigned int PDIS0:1; /**< \brief [0:0] Pin Function Decision Control for Pin 0 (rw) */
+ unsigned int PDIS1:1; /**< \brief [1:1] Pin Function Decision Control for Pin 1 (rw) */
+ unsigned int PDIS2:1; /**< \brief [2:2] Pin Function Decision Control for Pin 2 (rw) */
+ unsigned int PDIS3:1; /**< \brief [3:3] Pin Function Decision Control for Pin 3 (rw) */
+ unsigned int PDIS4:1; /**< \brief [4:4] Pin Function Decision Control for Pin 4 (rw) */
+ unsigned int PDIS5:1; /**< \brief [5:5] Pin Function Decision Control for Pin 5 (rw) */
+ unsigned int PDIS6:1; /**< \brief [6:6] Pin Function Decision Control for Pin 6 (rw) */
+ unsigned int PDIS7:1; /**< \brief [7:7] Pin Function Decision Control for Pin 7 (rw) */
+ unsigned int PDIS8:1; /**< \brief [8:8] Pin Function Decision Control for Pin 8 (rw) */
+ unsigned int PDIS9:1; /**< \brief [9:9] Pin Function Decision Control for Pin 9 (rw) */
+ unsigned int PDIS10:1; /**< \brief [10:10] Pin Function Decision Control for Pin 10 (rw) */
+ unsigned int PDIS11:1; /**< \brief [11:11] Pin Function Decision Control for Pin 11 (rw) */
+ unsigned int PDIS12:1; /**< \brief [12:12] Pin Function Decision Control for Pin 12 (rw) */
+ unsigned int PDIS13:1; /**< \brief [13:13] Pin Function Decision Control for Pin 13 (rw) */
+ unsigned int PDIS14:1; /**< \brief [14:14] Pin Function Decision Control for Pin 14 (rw) */
+ unsigned int PDIS15:1; /**< \brief [15:15] Pin Function Decision Control for Pin 15 (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_P_PDISC_Bits;
+
+/** \brief Port Pad Driver Mode 0 Register */
+typedef struct _Ifx_P_PDR0_Bits
+{
+ unsigned int PD0:3; /**< \brief [2:0] (rw) */
+ unsigned int PL0:1; /**< \brief [3:3] (rw) */
+ unsigned int PD1:3; /**< \brief [6:4] (rw) */
+ unsigned int PL1:1; /**< \brief [7:7] (rw) */
+ unsigned int PD2:3; /**< \brief [10:8] (rw) */
+ unsigned int PL2:1; /**< \brief [11:11] (rw) */
+ unsigned int PD3:3; /**< \brief [14:12] (rw) */
+ unsigned int PL3:1; /**< \brief [15:15] (rw) */
+ unsigned int PD4:3; /**< \brief [18:16] (rw) */
+ unsigned int PL4:1; /**< \brief [19:19] (rw) */
+ unsigned int PD5:3; /**< \brief [22:20] (rw) */
+ unsigned int PL5:1; /**< \brief [23:23] (rw) */
+ unsigned int PD6:3; /**< \brief [26:24] (rw) */
+ unsigned int PL6:1; /**< \brief [27:27] (rw) */
+ unsigned int PD7:3; /**< \brief [30:28] (rw) */
+ unsigned int PL7:1; /**< \brief [31:31] (rw) */
+} Ifx_P_PDR0_Bits;
+
+/** \brief Port Pad Driver Mode 1 Register */
+typedef struct _Ifx_P_PDR1_Bits
+{
+ unsigned int PD8:3; /**< \brief [2:0] (rw) */
+ unsigned int PL8:1; /**< \brief [3:3] (rw) */
+ unsigned int PD9:3; /**< \brief [6:4] (rw) */
+ unsigned int PL9:1; /**< \brief [7:7] (rw) */
+ unsigned int PD10:3; /**< \brief [10:8] (rw) */
+ unsigned int PL10:1; /**< \brief [11:11] (rw) */
+ unsigned int PD11:3; /**< \brief [14:12] (rw) */
+ unsigned int PL11:1; /**< \brief [15:15] (rw) */
+ unsigned int PD12:3; /**< \brief [18:16] (rw) */
+ unsigned int PL12:1; /**< \brief [19:19] (rw) */
+ unsigned int PD13:3; /**< \brief [22:20] (rw) */
+ unsigned int PL13:1; /**< \brief [23:23] (rw) */
+ unsigned int PD14:3; /**< \brief [26:24] (rw) */
+ unsigned int PL14:1; /**< \brief [27:27] (rw) */
+ unsigned int PD15:3; /**< \brief [30:28] (rw) */
+ unsigned int PL15:1; /**< \brief [31:31] (rw) */
+} Ifx_P_PDR1_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_union
+ * \{ */
+
+/** \brief Port Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_P_ACCEN0_Bits B; /**< \brief Bitfield access */
+} Ifx_P_ACCEN0;
+
+/** \brief Port Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_P_ACCEN1_Bits B; /**< \brief Bitfield access */
+} Ifx_P_ACCEN1;
+
+/** \brief Port Emergency Stop Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_P_ESR_Bits B; /**< \brief Bitfield access */
+} Ifx_P_ESR;
+
+/** \brief Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_P_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_P_ID;
+
+/** \brief Port Input Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_P_IN_Bits B; /**< \brief Bitfield access */
+} Ifx_P_IN;
+
+/** \brief Port Input/Output Control Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_P_IOCR0_Bits B; /**< \brief Bitfield access */
+} Ifx_P_IOCR0;
+
+/** \brief Port Input/Output Control Register 12 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_P_IOCR12_Bits B; /**< \brief Bitfield access */
+} Ifx_P_IOCR12;
+
+/** \brief Port Input/Output Control Register 4 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_P_IOCR4_Bits B; /**< \brief Bitfield access */
+} Ifx_P_IOCR4;
+
+/** \brief Port Input/Output Control Register 8 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_P_IOCR8_Bits B; /**< \brief Bitfield access */
+} Ifx_P_IOCR8;
+
+/** \brief Port LVDS Pad Control Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_P_LPCR0_Bits B; /**< \brief Bitfield access */
+} Ifx_P_LPCR0;
+
+/** \brief Port LVDS Pad Control Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_P_LPCR1_Bits B; /**< \brief Bitfield access */
+ Ifx_P_LPCR1_P21_Bits B_P21; /**< \brief Bitfield access for P21 */
+} Ifx_P_LPCR1;
+
+/** \brief Port LVDS Pad Control Register 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_P_LPCR2_Bits B; /**< \brief Bitfield access */
+} Ifx_P_LPCR2;
+
+/** \brief Port Output Modification Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_P_OMCR_Bits B; /**< \brief Bitfield access */
+} Ifx_P_OMCR;
+
+/** \brief Port Output Modification Clear Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_P_OMCR0_Bits B; /**< \brief Bitfield access */
+} Ifx_P_OMCR0;
+
+/** \brief Port Output Modification Clear Register 12 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_P_OMCR12_Bits B; /**< \brief Bitfield access */
+} Ifx_P_OMCR12;
+
+/** \brief Port Output Modification Clear Register 4 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_P_OMCR4_Bits B; /**< \brief Bitfield access */
+} Ifx_P_OMCR4;
+
+/** \brief Port Output Modification Clear Register 8 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_P_OMCR8_Bits B; /**< \brief Bitfield access */
+} Ifx_P_OMCR8;
+
+/** \brief Port Output Modification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_P_OMR_Bits B; /**< \brief Bitfield access */
+} Ifx_P_OMR;
+
+/** \brief Port Output Modification Set Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_P_OMSR_Bits B; /**< \brief Bitfield access */
+} Ifx_P_OMSR;
+
+/** \brief Port Output Modification Set Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_P_OMSR0_Bits B; /**< \brief Bitfield access */
+} Ifx_P_OMSR0;
+
+/** \brief Port Output Modification Set Register 12 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_P_OMSR12_Bits B; /**< \brief Bitfield access */
+} Ifx_P_OMSR12;
+
+/** \brief Port Output Modification Set Register 4 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_P_OMSR4_Bits B; /**< \brief Bitfield access */
+} Ifx_P_OMSR4;
+
+/** \brief Port Output Modification Set Register 8 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_P_OMSR8_Bits B; /**< \brief Bitfield access */
+} Ifx_P_OMSR8;
+
+/** \brief Port Output Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_P_OUT_Bits B; /**< \brief Bitfield access */
+} Ifx_P_OUT;
+
+/** \brief Port Pin Controller Select Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_P_PCSR_Bits B; /**< \brief Bitfield access */
+} Ifx_P_PCSR;
+
+/** \brief Port Pin Function Decision Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_P_PDISC_Bits B; /**< \brief Bitfield access */
+} Ifx_P_PDISC;
+
+/** \brief Port Pad Driver Mode 0 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_P_PDR0_Bits B; /**< \brief Bitfield access */
+} Ifx_P_PDR0;
+
+/** \brief Port Pad Driver Mode 1 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_P_PDR1_Bits B; /**< \brief Bitfield access */
+} Ifx_P_PDR1;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief Port object */
+typedef volatile struct _Ifx_P
+{
+ Ifx_P_OUT OUT; /**< \brief 0, Port Output Register */
+ Ifx_P_OMR OMR; /**< \brief 4, Port Output Modification Register */
+ Ifx_P_ID ID; /**< \brief 8, Identification Register */
+ unsigned char reserved_C[4]; /**< \brief C, \internal Reserved */
+ Ifx_P_IOCR0 IOCR0; /**< \brief 10, Port Input/Output Control Register 0 */
+ Ifx_P_IOCR4 IOCR4; /**< \brief 14, Port Input/Output Control Register 4 */
+ Ifx_P_IOCR8 IOCR8; /**< \brief 18, Port Input/Output Control Register 8 */
+ Ifx_P_IOCR12 IOCR12; /**< \brief 1C, Port Input/Output Control Register 12 */
+ unsigned char reserved_20[4]; /**< \brief 20, \internal Reserved */
+ Ifx_P_IN IN; /**< \brief 24, Port Input Register */
+ unsigned char reserved_28[24]; /**< \brief 28, \internal Reserved */
+ Ifx_P_PDR0 PDR0; /**< \brief 40, Port Pad Driver Mode 0 Register */
+ Ifx_P_PDR1 PDR1; /**< \brief 44, Port Pad Driver Mode 1 Register */
+ unsigned char reserved_48[8]; /**< \brief 48, \internal Reserved */
+ Ifx_P_ESR ESR; /**< \brief 50, Port Emergency Stop Register */
+ unsigned char reserved_54[12]; /**< \brief 54, \internal Reserved */
+ Ifx_P_PDISC PDISC; /**< \brief 60, Port Pin Function Decision Control Register */
+ Ifx_P_PCSR PCSR; /**< \brief 64, Port Pin Controller Select Register */
+ unsigned char reserved_68[8]; /**< \brief 68, \internal Reserved */
+ Ifx_P_OMSR0 OMSR0; /**< \brief 70, Port Output Modification Set Register 0 */
+ Ifx_P_OMSR4 OMSR4; /**< \brief 74, Port Output Modification Set Register 4 */
+ Ifx_P_OMSR8 OMSR8; /**< \brief 78, Port Output Modification Set Register 8 */
+ Ifx_P_OMSR12 OMSR12; /**< \brief 7C, Port Output Modification Set Register 12 */
+ Ifx_P_OMCR0 OMCR0; /**< \brief 80, Port Output Modification Clear Register 0 */
+ Ifx_P_OMCR4 OMCR4; /**< \brief 84, Port Output Modification Clear Register 4 */
+ Ifx_P_OMCR8 OMCR8; /**< \brief 88, Port Output Modification Clear Register 8 */
+ Ifx_P_OMCR12 OMCR12; /**< \brief 8C, Port Output Modification Clear Register 12 */
+ Ifx_P_OMSR OMSR; /**< \brief 90, Port Output Modification Set Register */
+ Ifx_P_OMCR OMCR; /**< \brief 94, Port Output Modification Clear Register */
+ unsigned char reserved_98[8]; /**< \brief 98, \internal Reserved */
+ Ifx_P_LPCR0 LPCR0; /**< \brief A0, Port LVDS Pad Control Register 0 */
+ Ifx_P_LPCR1 LPCR1; /**< \brief A4, Port LVDS Pad Control Register 1 */
+ Ifx_P_LPCR2 LPCR2; /**< \brief A8, Port LVDS Pad Control Register 2 */
+ unsigned char reserved_A4[76]; /**< \brief AC, \internal Reserved */
+ Ifx_P_ACCEN1 ACCEN1; /**< \brief F8, Port Access Enable Register 1 */
+ Ifx_P_ACCEN0 ACCEN0; /**< \brief FC, Port Access Enable Register 0 */
+} Ifx_P;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXPORT_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPsi5_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPsi5_bf.h
new file mode 100644
index 0000000..6862213
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPsi5_bf.h
@@ -0,0 +1,11997 @@
+/**
+ * \file IfxPsi5_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Psi5_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Psi5
+ *
+ */
+#ifndef IFXPSI5_BF_H
+#define IFXPSI5_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Psi5_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN0 */
+#define IFX_PSI5_ACCEN0_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN0 */
+#define IFX_PSI5_ACCEN0_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN0 */
+#define IFX_PSI5_ACCEN0_EN0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN10 */
+#define IFX_PSI5_ACCEN0_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN10 */
+#define IFX_PSI5_ACCEN0_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN10 */
+#define IFX_PSI5_ACCEN0_EN10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN11 */
+#define IFX_PSI5_ACCEN0_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN11 */
+#define IFX_PSI5_ACCEN0_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN11 */
+#define IFX_PSI5_ACCEN0_EN11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN12 */
+#define IFX_PSI5_ACCEN0_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN12 */
+#define IFX_PSI5_ACCEN0_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN12 */
+#define IFX_PSI5_ACCEN0_EN12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN13 */
+#define IFX_PSI5_ACCEN0_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN13 */
+#define IFX_PSI5_ACCEN0_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN13 */
+#define IFX_PSI5_ACCEN0_EN13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN14 */
+#define IFX_PSI5_ACCEN0_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN14 */
+#define IFX_PSI5_ACCEN0_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN14 */
+#define IFX_PSI5_ACCEN0_EN14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN15 */
+#define IFX_PSI5_ACCEN0_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN15 */
+#define IFX_PSI5_ACCEN0_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN15 */
+#define IFX_PSI5_ACCEN0_EN15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN16 */
+#define IFX_PSI5_ACCEN0_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN16 */
+#define IFX_PSI5_ACCEN0_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN16 */
+#define IFX_PSI5_ACCEN0_EN16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN17 */
+#define IFX_PSI5_ACCEN0_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN17 */
+#define IFX_PSI5_ACCEN0_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN17 */
+#define IFX_PSI5_ACCEN0_EN17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN18 */
+#define IFX_PSI5_ACCEN0_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN18 */
+#define IFX_PSI5_ACCEN0_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN18 */
+#define IFX_PSI5_ACCEN0_EN18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN19 */
+#define IFX_PSI5_ACCEN0_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN19 */
+#define IFX_PSI5_ACCEN0_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN19 */
+#define IFX_PSI5_ACCEN0_EN19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN1 */
+#define IFX_PSI5_ACCEN0_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN1 */
+#define IFX_PSI5_ACCEN0_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN1 */
+#define IFX_PSI5_ACCEN0_EN1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN20 */
+#define IFX_PSI5_ACCEN0_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN20 */
+#define IFX_PSI5_ACCEN0_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN20 */
+#define IFX_PSI5_ACCEN0_EN20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN21 */
+#define IFX_PSI5_ACCEN0_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN21 */
+#define IFX_PSI5_ACCEN0_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN21 */
+#define IFX_PSI5_ACCEN0_EN21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN22 */
+#define IFX_PSI5_ACCEN0_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN22 */
+#define IFX_PSI5_ACCEN0_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN22 */
+#define IFX_PSI5_ACCEN0_EN22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN23 */
+#define IFX_PSI5_ACCEN0_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN23 */
+#define IFX_PSI5_ACCEN0_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN23 */
+#define IFX_PSI5_ACCEN0_EN23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN24 */
+#define IFX_PSI5_ACCEN0_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN24 */
+#define IFX_PSI5_ACCEN0_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN24 */
+#define IFX_PSI5_ACCEN0_EN24_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN25 */
+#define IFX_PSI5_ACCEN0_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN25 */
+#define IFX_PSI5_ACCEN0_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN25 */
+#define IFX_PSI5_ACCEN0_EN25_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN26 */
+#define IFX_PSI5_ACCEN0_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN26 */
+#define IFX_PSI5_ACCEN0_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN26 */
+#define IFX_PSI5_ACCEN0_EN26_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN27 */
+#define IFX_PSI5_ACCEN0_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN27 */
+#define IFX_PSI5_ACCEN0_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN27 */
+#define IFX_PSI5_ACCEN0_EN27_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN28 */
+#define IFX_PSI5_ACCEN0_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN28 */
+#define IFX_PSI5_ACCEN0_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN28 */
+#define IFX_PSI5_ACCEN0_EN28_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN29 */
+#define IFX_PSI5_ACCEN0_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN29 */
+#define IFX_PSI5_ACCEN0_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN29 */
+#define IFX_PSI5_ACCEN0_EN29_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN2 */
+#define IFX_PSI5_ACCEN0_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN2 */
+#define IFX_PSI5_ACCEN0_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN2 */
+#define IFX_PSI5_ACCEN0_EN2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN30 */
+#define IFX_PSI5_ACCEN0_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN30 */
+#define IFX_PSI5_ACCEN0_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN30 */
+#define IFX_PSI5_ACCEN0_EN30_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN31 */
+#define IFX_PSI5_ACCEN0_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN31 */
+#define IFX_PSI5_ACCEN0_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN31 */
+#define IFX_PSI5_ACCEN0_EN31_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN3 */
+#define IFX_PSI5_ACCEN0_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN3 */
+#define IFX_PSI5_ACCEN0_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN3 */
+#define IFX_PSI5_ACCEN0_EN3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN4 */
+#define IFX_PSI5_ACCEN0_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN4 */
+#define IFX_PSI5_ACCEN0_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN4 */
+#define IFX_PSI5_ACCEN0_EN4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN5 */
+#define IFX_PSI5_ACCEN0_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN5 */
+#define IFX_PSI5_ACCEN0_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN5 */
+#define IFX_PSI5_ACCEN0_EN5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN6 */
+#define IFX_PSI5_ACCEN0_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN6 */
+#define IFX_PSI5_ACCEN0_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN6 */
+#define IFX_PSI5_ACCEN0_EN6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN7 */
+#define IFX_PSI5_ACCEN0_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN7 */
+#define IFX_PSI5_ACCEN0_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN7 */
+#define IFX_PSI5_ACCEN0_EN7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN8 */
+#define IFX_PSI5_ACCEN0_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN8 */
+#define IFX_PSI5_ACCEN0_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN8 */
+#define IFX_PSI5_ACCEN0_EN8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_ACCEN0_Bits.EN9 */
+#define IFX_PSI5_ACCEN0_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_ACCEN0_Bits.EN9 */
+#define IFX_PSI5_ACCEN0_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_ACCEN0_Bits.EN9 */
+#define IFX_PSI5_ACCEN0_EN9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_CH_CTV_Bits.CTC */
+#define IFX_PSI5_CH_CTV_CTC_LEN (16u)
+
+/** \brief Mask for Ifx_PSI5_CH_CTV_Bits.CTC */
+#define IFX_PSI5_CH_CTV_CTC_MSK (0xffffu)
+
+/** \brief Offset for Ifx_PSI5_CH_CTV_Bits.CTC */
+#define IFX_PSI5_CH_CTV_CTC_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_CH_CTV_Bits.CTV */
+#define IFX_PSI5_CH_CTV_CTV_LEN (16u)
+
+/** \brief Mask for Ifx_PSI5_CH_CTV_Bits.CTV */
+#define IFX_PSI5_CH_CTV_CTV_MSK (0xffffu)
+
+/** \brief Offset for Ifx_PSI5_CH_CTV_Bits.CTV */
+#define IFX_PSI5_CH_CTV_CTV_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_CH_IOCR_Bits.ALTI */
+#define IFX_PSI5_CH_IOCR_ALTI_LEN (2u)
+
+/** \brief Mask for Ifx_PSI5_CH_IOCR_Bits.ALTI */
+#define IFX_PSI5_CH_IOCR_ALTI_MSK (0x3u)
+
+/** \brief Offset for Ifx_PSI5_CH_IOCR_Bits.ALTI */
+#define IFX_PSI5_CH_IOCR_ALTI_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_CH_IOCR_Bits.CFEG */
+#define IFX_PSI5_CH_IOCR_CFEG_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_IOCR_Bits.CFEG */
+#define IFX_PSI5_CH_IOCR_CFEG_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_IOCR_Bits.CFEG */
+#define IFX_PSI5_CH_IOCR_CFEG_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_CH_IOCR_Bits.CREG */
+#define IFX_PSI5_CH_IOCR_CREG_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_IOCR_Bits.CREG */
+#define IFX_PSI5_CH_IOCR_CREG_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_IOCR_Bits.CREG */
+#define IFX_PSI5_CH_IOCR_CREG_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_CH_IOCR_Bits.DEPTH */
+#define IFX_PSI5_CH_IOCR_DEPTH_LEN (4u)
+
+/** \brief Mask for Ifx_PSI5_CH_IOCR_Bits.DEPTH */
+#define IFX_PSI5_CH_IOCR_DEPTH_MSK (0xfu)
+
+/** \brief Offset for Ifx_PSI5_CH_IOCR_Bits.DEPTH */
+#define IFX_PSI5_CH_IOCR_DEPTH_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_CH_IOCR_Bits.FEG */
+#define IFX_PSI5_CH_IOCR_FEG_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_IOCR_Bits.FEG */
+#define IFX_PSI5_CH_IOCR_FEG_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_IOCR_Bits.FEG */
+#define IFX_PSI5_CH_IOCR_FEG_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_CH_IOCR_Bits.IIE */
+#define IFX_PSI5_CH_IOCR_IIE_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_IOCR_Bits.IIE */
+#define IFX_PSI5_CH_IOCR_IIE_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_IOCR_Bits.IIE */
+#define IFX_PSI5_CH_IOCR_IIE_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_CH_IOCR_Bits.OIE */
+#define IFX_PSI5_CH_IOCR_OIE_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_IOCR_Bits.OIE */
+#define IFX_PSI5_CH_IOCR_OIE_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_IOCR_Bits.OIE */
+#define IFX_PSI5_CH_IOCR_OIE_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_CH_IOCR_Bits.REG */
+#define IFX_PSI5_CH_IOCR_REG_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_IOCR_Bits.REG */
+#define IFX_PSI5_CH_IOCR_REG_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_IOCR_Bits.REG */
+#define IFX_PSI5_CH_IOCR_REG_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_CH_IOCR_Bits.RXM */
+#define IFX_PSI5_CH_IOCR_RXM_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_IOCR_Bits.RXM */
+#define IFX_PSI5_CH_IOCR_RXM_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_IOCR_Bits.RXM */
+#define IFX_PSI5_CH_IOCR_RXM_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_CH_IOCR_Bits.TXM */
+#define IFX_PSI5_CH_IOCR_TXM_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_IOCR_Bits.TXM */
+#define IFX_PSI5_CH_IOCR_TXM_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_IOCR_Bits.TXM */
+#define IFX_PSI5_CH_IOCR_TXM_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_CH_PGC_Bits.BOT */
+#define IFX_PSI5_CH_PGC_BOT_LEN (7u)
+
+/** \brief Mask for Ifx_PSI5_CH_PGC_Bits.BOT */
+#define IFX_PSI5_CH_PGC_BOT_MSK (0x7fu)
+
+/** \brief Offset for Ifx_PSI5_CH_PGC_Bits.BOT */
+#define IFX_PSI5_CH_PGC_BOT_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_CH_PGC_Bits.BYP */
+#define IFX_PSI5_CH_PGC_BYP_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_PGC_Bits.BYP */
+#define IFX_PSI5_CH_PGC_BYP_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_PGC_Bits.BYP */
+#define IFX_PSI5_CH_PGC_BYP_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_CH_PGC_Bits.DEL */
+#define IFX_PSI5_CH_PGC_DEL_LEN (6u)
+
+/** \brief Mask for Ifx_PSI5_CH_PGC_Bits.DEL */
+#define IFX_PSI5_CH_PGC_DEL_MSK (0x3fu)
+
+/** \brief Offset for Ifx_PSI5_CH_PGC_Bits.DEL */
+#define IFX_PSI5_CH_PGC_DEL_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_CH_PGC_Bits.ETB */
+#define IFX_PSI5_CH_PGC_ETB_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5_CH_PGC_Bits.ETB */
+#define IFX_PSI5_CH_PGC_ETB_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5_CH_PGC_Bits.ETB */
+#define IFX_PSI5_CH_PGC_ETB_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_CH_PGC_Bits.ETE */
+#define IFX_PSI5_CH_PGC_ETE_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_PGC_Bits.ETE */
+#define IFX_PSI5_CH_PGC_ETE_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_PGC_Bits.ETE */
+#define IFX_PSI5_CH_PGC_ETE_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_CH_PGC_Bits.ETS */
+#define IFX_PSI5_CH_PGC_ETS_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5_CH_PGC_Bits.ETS */
+#define IFX_PSI5_CH_PGC_ETS_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5_CH_PGC_Bits.ETS */
+#define IFX_PSI5_CH_PGC_ETS_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_CH_PGC_Bits.PLEN */
+#define IFX_PSI5_CH_PGC_PLEN_LEN (6u)
+
+/** \brief Mask for Ifx_PSI5_CH_PGC_Bits.PLEN */
+#define IFX_PSI5_CH_PGC_PLEN_MSK (0x3fu)
+
+/** \brief Offset for Ifx_PSI5_CH_PGC_Bits.PLEN */
+#define IFX_PSI5_CH_PGC_PLEN_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_CH_PGC_Bits.PTE */
+#define IFX_PSI5_CH_PGC_PTE_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_PGC_Bits.PTE */
+#define IFX_PSI5_CH_PGC_PTE_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_PGC_Bits.PTE */
+#define IFX_PSI5_CH_PGC_PTE_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_CH_PGC_Bits.TBS */
+#define IFX_PSI5_CH_PGC_TBS_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_PGC_Bits.TBS */
+#define IFX_PSI5_CH_PGC_TBS_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_PGC_Bits.TBS */
+#define IFX_PSI5_CH_PGC_TBS_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRA_Bits.ASYN */
+#define IFX_PSI5_CH_RCRA_ASYN_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRA_Bits.ASYN */
+#define IFX_PSI5_CH_RCRA_ASYN_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRA_Bits.ASYN */
+#define IFX_PSI5_CH_RCRA_ASYN_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRA_Bits.AVBS */
+#define IFX_PSI5_CH_RCRA_AVBS_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRA_Bits.AVBS */
+#define IFX_PSI5_CH_RCRA_AVBS_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRA_Bits.AVBS */
+#define IFX_PSI5_CH_RCRA_AVBS_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRA_Bits.PDL0 */
+#define IFX_PSI5_CH_RCRA_PDL0_LEN (5u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRA_Bits.PDL0 */
+#define IFX_PSI5_CH_RCRA_PDL0_MSK (0x1fu)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRA_Bits.PDL0 */
+#define IFX_PSI5_CH_RCRA_PDL0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRA_Bits.PDL1 */
+#define IFX_PSI5_CH_RCRA_PDL1_LEN (5u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRA_Bits.PDL1 */
+#define IFX_PSI5_CH_RCRA_PDL1_MSK (0x1fu)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRA_Bits.PDL1 */
+#define IFX_PSI5_CH_RCRA_PDL1_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRA_Bits.PDL2 */
+#define IFX_PSI5_CH_RCRA_PDL2_LEN (5u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRA_Bits.PDL2 */
+#define IFX_PSI5_CH_RCRA_PDL2_MSK (0x1fu)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRA_Bits.PDL2 */
+#define IFX_PSI5_CH_RCRA_PDL2_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRA_Bits.PDL3 */
+#define IFX_PSI5_CH_RCRA_PDL3_LEN (5u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRA_Bits.PDL3 */
+#define IFX_PSI5_CH_RCRA_PDL3_MSK (0x1fu)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRA_Bits.PDL3 */
+#define IFX_PSI5_CH_RCRA_PDL3_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRA_Bits.PDL4 */
+#define IFX_PSI5_CH_RCRA_PDL4_LEN (5u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRA_Bits.PDL4 */
+#define IFX_PSI5_CH_RCRA_PDL4_MSK (0x1fu)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRA_Bits.PDL4 */
+#define IFX_PSI5_CH_RCRA_PDL4_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRA_Bits.PDL5 */
+#define IFX_PSI5_CH_RCRA_PDL5_LEN (5u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRA_Bits.PDL5 */
+#define IFX_PSI5_CH_RCRA_PDL5_MSK (0x1fu)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRA_Bits.PDL5 */
+#define IFX_PSI5_CH_RCRA_PDL5_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRB_Bits.CRC0 */
+#define IFX_PSI5_CH_RCRB_CRC0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRB_Bits.CRC0 */
+#define IFX_PSI5_CH_RCRB_CRC0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRB_Bits.CRC0 */
+#define IFX_PSI5_CH_RCRB_CRC0_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRB_Bits.CRC1 */
+#define IFX_PSI5_CH_RCRB_CRC1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRB_Bits.CRC1 */
+#define IFX_PSI5_CH_RCRB_CRC1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRB_Bits.CRC1 */
+#define IFX_PSI5_CH_RCRB_CRC1_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRB_Bits.CRC2 */
+#define IFX_PSI5_CH_RCRB_CRC2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRB_Bits.CRC2 */
+#define IFX_PSI5_CH_RCRB_CRC2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRB_Bits.CRC2 */
+#define IFX_PSI5_CH_RCRB_CRC2_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRB_Bits.CRC3 */
+#define IFX_PSI5_CH_RCRB_CRC3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRB_Bits.CRC3 */
+#define IFX_PSI5_CH_RCRB_CRC3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRB_Bits.CRC3 */
+#define IFX_PSI5_CH_RCRB_CRC3_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRB_Bits.CRC4 */
+#define IFX_PSI5_CH_RCRB_CRC4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRB_Bits.CRC4 */
+#define IFX_PSI5_CH_RCRB_CRC4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRB_Bits.CRC4 */
+#define IFX_PSI5_CH_RCRB_CRC4_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRB_Bits.CRC5 */
+#define IFX_PSI5_CH_RCRB_CRC5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRB_Bits.CRC5 */
+#define IFX_PSI5_CH_RCRB_CRC5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRB_Bits.CRC5 */
+#define IFX_PSI5_CH_RCRB_CRC5_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRB_Bits.FEC0 */
+#define IFX_PSI5_CH_RCRB_FEC0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRB_Bits.FEC0 */
+#define IFX_PSI5_CH_RCRB_FEC0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRB_Bits.FEC0 */
+#define IFX_PSI5_CH_RCRB_FEC0_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRB_Bits.FEC1 */
+#define IFX_PSI5_CH_RCRB_FEC1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRB_Bits.FEC1 */
+#define IFX_PSI5_CH_RCRB_FEC1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRB_Bits.FEC1 */
+#define IFX_PSI5_CH_RCRB_FEC1_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRB_Bits.FEC2 */
+#define IFX_PSI5_CH_RCRB_FEC2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRB_Bits.FEC2 */
+#define IFX_PSI5_CH_RCRB_FEC2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRB_Bits.FEC2 */
+#define IFX_PSI5_CH_RCRB_FEC2_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRB_Bits.FEC3 */
+#define IFX_PSI5_CH_RCRB_FEC3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRB_Bits.FEC3 */
+#define IFX_PSI5_CH_RCRB_FEC3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRB_Bits.FEC3 */
+#define IFX_PSI5_CH_RCRB_FEC3_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRB_Bits.FEC4 */
+#define IFX_PSI5_CH_RCRB_FEC4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRB_Bits.FEC4 */
+#define IFX_PSI5_CH_RCRB_FEC4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRB_Bits.FEC4 */
+#define IFX_PSI5_CH_RCRB_FEC4_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRB_Bits.FEC5 */
+#define IFX_PSI5_CH_RCRB_FEC5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRB_Bits.FEC5 */
+#define IFX_PSI5_CH_RCRB_FEC5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRB_Bits.FEC5 */
+#define IFX_PSI5_CH_RCRB_FEC5_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRB_Bits.MSG0 */
+#define IFX_PSI5_CH_RCRB_MSG0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRB_Bits.MSG0 */
+#define IFX_PSI5_CH_RCRB_MSG0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRB_Bits.MSG0 */
+#define IFX_PSI5_CH_RCRB_MSG0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRB_Bits.MSG1 */
+#define IFX_PSI5_CH_RCRB_MSG1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRB_Bits.MSG1 */
+#define IFX_PSI5_CH_RCRB_MSG1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRB_Bits.MSG1 */
+#define IFX_PSI5_CH_RCRB_MSG1_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRB_Bits.MSG2 */
+#define IFX_PSI5_CH_RCRB_MSG2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRB_Bits.MSG2 */
+#define IFX_PSI5_CH_RCRB_MSG2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRB_Bits.MSG2 */
+#define IFX_PSI5_CH_RCRB_MSG2_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRB_Bits.MSG3 */
+#define IFX_PSI5_CH_RCRB_MSG3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRB_Bits.MSG3 */
+#define IFX_PSI5_CH_RCRB_MSG3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRB_Bits.MSG3 */
+#define IFX_PSI5_CH_RCRB_MSG3_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRB_Bits.MSG4 */
+#define IFX_PSI5_CH_RCRB_MSG4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRB_Bits.MSG4 */
+#define IFX_PSI5_CH_RCRB_MSG4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRB_Bits.MSG4 */
+#define IFX_PSI5_CH_RCRB_MSG4_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRB_Bits.MSG5 */
+#define IFX_PSI5_CH_RCRB_MSG5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRB_Bits.MSG5 */
+#define IFX_PSI5_CH_RCRB_MSG5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRB_Bits.MSG5 */
+#define IFX_PSI5_CH_RCRB_MSG5_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRB_Bits.VBS0 */
+#define IFX_PSI5_CH_RCRB_VBS0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRB_Bits.VBS0 */
+#define IFX_PSI5_CH_RCRB_VBS0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRB_Bits.VBS0 */
+#define IFX_PSI5_CH_RCRB_VBS0_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRB_Bits.VBS1 */
+#define IFX_PSI5_CH_RCRB_VBS1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRB_Bits.VBS1 */
+#define IFX_PSI5_CH_RCRB_VBS1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRB_Bits.VBS1 */
+#define IFX_PSI5_CH_RCRB_VBS1_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRB_Bits.VBS2 */
+#define IFX_PSI5_CH_RCRB_VBS2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRB_Bits.VBS2 */
+#define IFX_PSI5_CH_RCRB_VBS2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRB_Bits.VBS2 */
+#define IFX_PSI5_CH_RCRB_VBS2_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRB_Bits.VBS3 */
+#define IFX_PSI5_CH_RCRB_VBS3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRB_Bits.VBS3 */
+#define IFX_PSI5_CH_RCRB_VBS3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRB_Bits.VBS3 */
+#define IFX_PSI5_CH_RCRB_VBS3_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRB_Bits.VBS4 */
+#define IFX_PSI5_CH_RCRB_VBS4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRB_Bits.VBS4 */
+#define IFX_PSI5_CH_RCRB_VBS4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRB_Bits.VBS4 */
+#define IFX_PSI5_CH_RCRB_VBS4_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRB_Bits.VBS5 */
+#define IFX_PSI5_CH_RCRB_VBS5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRB_Bits.VBS5 */
+#define IFX_PSI5_CH_RCRB_VBS5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRB_Bits.VBS5 */
+#define IFX_PSI5_CH_RCRB_VBS5_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRC_Bits.BRS */
+#define IFX_PSI5_CH_RCRC_BRS_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRC_Bits.BRS */
+#define IFX_PSI5_CH_RCRC_BRS_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRC_Bits.BRS */
+#define IFX_PSI5_CH_RCRC_BRS_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRC_Bits.TSF */
+#define IFX_PSI5_CH_RCRC_TSF_LEN (2u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRC_Bits.TSF */
+#define IFX_PSI5_CH_RCRC_TSF_MSK (0x3u)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRC_Bits.TSF */
+#define IFX_PSI5_CH_RCRC_TSF_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRC_Bits.TSP */
+#define IFX_PSI5_CH_RCRC_TSP_LEN (2u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRC_Bits.TSP */
+#define IFX_PSI5_CH_RCRC_TSP_MSK (0x3u)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRC_Bits.TSP */
+#define IFX_PSI5_CH_RCRC_TSP_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_CH_RCRC_Bits.TSR */
+#define IFX_PSI5_CH_RCRC_TSR_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RCRC_Bits.TSR */
+#define IFX_PSI5_CH_RCRC_TSR_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RCRC_Bits.TSR */
+#define IFX_PSI5_CH_RCRC_TSR_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_CH_RDRH_Bits.MEI */
+#define IFX_PSI5_CH_RDRH_MEI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RDRH_Bits.MEI */
+#define IFX_PSI5_CH_RDRH_MEI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RDRH_Bits.MEI */
+#define IFX_PSI5_CH_RDRH_MEI_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_CH_RDRH_Bits.NBI */
+#define IFX_PSI5_CH_RDRH_NBI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RDRH_Bits.NBI */
+#define IFX_PSI5_CH_RDRH_NBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RDRH_Bits.NBI */
+#define IFX_PSI5_CH_RDRH_NBI_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_CH_RDRH_Bits.NFI */
+#define IFX_PSI5_CH_RDRH_NFI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RDRH_Bits.NFI */
+#define IFX_PSI5_CH_RDRH_NFI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RDRH_Bits.NFI */
+#define IFX_PSI5_CH_RDRH_NFI_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_CH_RDRH_Bits.RBI */
+#define IFX_PSI5_CH_RDRH_RBI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RDRH_Bits.RBI */
+#define IFX_PSI5_CH_RDRH_RBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RDRH_Bits.RBI */
+#define IFX_PSI5_CH_RDRH_RBI_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_CH_RDRH_Bits.SC */
+#define IFX_PSI5_CH_RDRH_SC_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5_CH_RDRH_Bits.SC */
+#define IFX_PSI5_CH_RDRH_SC_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5_CH_RDRH_Bits.SC */
+#define IFX_PSI5_CH_RDRH_SC_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_CH_RDRH_Bits.TEI */
+#define IFX_PSI5_CH_RDRH_TEI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RDRH_Bits.TEI */
+#define IFX_PSI5_CH_RDRH_TEI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RDRH_Bits.TEI */
+#define IFX_PSI5_CH_RDRH_TEI_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_CH_RDRH_Bits.TS */
+#define IFX_PSI5_CH_RDRH_TS_LEN (24u)
+
+/** \brief Mask for Ifx_PSI5_CH_RDRH_Bits.TS */
+#define IFX_PSI5_CH_RDRH_TS_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_PSI5_CH_RDRH_Bits.TS */
+#define IFX_PSI5_CH_RDRH_TS_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_CH_RDRL_Bits.CRC */
+#define IFX_PSI5_CH_RDRL_CRC_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5_CH_RDRL_Bits.CRC */
+#define IFX_PSI5_CH_RDRL_CRC_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5_CH_RDRL_Bits.CRC */
+#define IFX_PSI5_CH_RDRL_CRC_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_CH_RDRL_Bits.CRCI */
+#define IFX_PSI5_CH_RDRL_CRCI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_RDRL_Bits.CRCI */
+#define IFX_PSI5_CH_RDRL_CRCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_RDRL_Bits.CRCI */
+#define IFX_PSI5_CH_RDRL_CRCI_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_CH_RDRL_Bits.RD */
+#define IFX_PSI5_CH_RDRL_RD_LEN (28u)
+
+/** \brief Mask for Ifx_PSI5_CH_RDRL_Bits.RD */
+#define IFX_PSI5_CH_RDRL_RD_MSK (0xfffffffu)
+
+/** \brief Offset for Ifx_PSI5_CH_RDRL_Bits.RD */
+#define IFX_PSI5_CH_RDRL_RD_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_CH_RSR_Bits.CRC */
+#define IFX_PSI5_CH_RSR_CRC_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5_CH_RSR_Bits.CRC */
+#define IFX_PSI5_CH_RSR_CRC_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5_CH_RSR_Bits.CRC */
+#define IFX_PSI5_CH_RSR_CRC_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_CH_RSR_Bits.MSG */
+#define IFX_PSI5_CH_RSR_MSG_LEN (2u)
+
+/** \brief Mask for Ifx_PSI5_CH_RSR_Bits.MSG */
+#define IFX_PSI5_CH_RSR_MSG_MSK (0x3u)
+
+/** \brief Offset for Ifx_PSI5_CH_RSR_Bits.MSG */
+#define IFX_PSI5_CH_RSR_MSG_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_CH_SCR_Bits.BSC */
+#define IFX_PSI5_CH_SCR_BSC_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SCR_Bits.BSC */
+#define IFX_PSI5_CH_SCR_BSC_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SCR_Bits.BSC */
+#define IFX_PSI5_CH_SCR_BSC_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_CH_SCR_Bits.CRC */
+#define IFX_PSI5_CH_SCR_CRC_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SCR_Bits.CRC */
+#define IFX_PSI5_CH_SCR_CRC_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SCR_Bits.CRC */
+#define IFX_PSI5_CH_SCR_CRC_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_CH_SCR_Bits.EPS */
+#define IFX_PSI5_CH_SCR_EPS_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SCR_Bits.EPS */
+#define IFX_PSI5_CH_SCR_EPS_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SCR_Bits.EPS */
+#define IFX_PSI5_CH_SCR_EPS_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_CH_SCR_Bits.FLUO */
+#define IFX_PSI5_CH_SCR_FLUO_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SCR_Bits.FLUO */
+#define IFX_PSI5_CH_SCR_FLUO_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SCR_Bits.FLUO */
+#define IFX_PSI5_CH_SCR_FLUO_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_CH_SCR_Bits.FLUS */
+#define IFX_PSI5_CH_SCR_FLUS_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SCR_Bits.FLUS */
+#define IFX_PSI5_CH_SCR_FLUS_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SCR_Bits.FLUS */
+#define IFX_PSI5_CH_SCR_FLUS_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_CH_SCR_Bits.GO */
+#define IFX_PSI5_CH_SCR_GO_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SCR_Bits.GO */
+#define IFX_PSI5_CH_SCR_GO_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SCR_Bits.GO */
+#define IFX_PSI5_CH_SCR_GO_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_CH_SCR_Bits.INH */
+#define IFX_PSI5_CH_SCR_INH_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SCR_Bits.INH */
+#define IFX_PSI5_CH_SCR_INH_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SCR_Bits.INH */
+#define IFX_PSI5_CH_SCR_INH_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_CH_SCR_Bits.PLL */
+#define IFX_PSI5_CH_SCR_PLL_LEN (6u)
+
+/** \brief Mask for Ifx_PSI5_CH_SCR_Bits.PLL */
+#define IFX_PSI5_CH_SCR_PLL_MSK (0x3fu)
+
+/** \brief Offset for Ifx_PSI5_CH_SCR_Bits.PLL */
+#define IFX_PSI5_CH_SCR_PLL_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_CH_SCR_Bits.SOL */
+#define IFX_PSI5_CH_SCR_SOL_LEN (6u)
+
+/** \brief Mask for Ifx_PSI5_CH_SCR_Bits.SOL */
+#define IFX_PSI5_CH_SCR_SOL_MSK (0x3fu)
+
+/** \brief Offset for Ifx_PSI5_CH_SCR_Bits.SOL */
+#define IFX_PSI5_CH_SCR_SOL_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_CH_SCR_Bits.SSL */
+#define IFX_PSI5_CH_SCR_SSL_LEN (6u)
+
+/** \brief Mask for Ifx_PSI5_CH_SCR_Bits.SSL */
+#define IFX_PSI5_CH_SCR_SSL_MSK (0x3fu)
+
+/** \brief Offset for Ifx_PSI5_CH_SCR_Bits.SSL */
+#define IFX_PSI5_CH_SCR_SSL_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_CH_SCR_Bits.STA */
+#define IFX_PSI5_CH_SCR_STA_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SCR_Bits.STA */
+#define IFX_PSI5_CH_SCR_STA_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SCR_Bits.STA */
+#define IFX_PSI5_CH_SCR_STA_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_CH_SCR_Bits.TOF */
+#define IFX_PSI5_CH_SCR_TOF_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SCR_Bits.TOF */
+#define IFX_PSI5_CH_SCR_TOF_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SCR_Bits.TOF */
+#define IFX_PSI5_CH_SCR_TOF_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_CH_SCR_Bits.TPF */
+#define IFX_PSI5_CH_SCR_TPF_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SCR_Bits.TPF */
+#define IFX_PSI5_CH_SCR_TPF_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SCR_Bits.TPF */
+#define IFX_PSI5_CH_SCR_TPF_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_CH_SCR_Bits.TRQ */
+#define IFX_PSI5_CH_SCR_TRQ_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SCR_Bits.TRQ */
+#define IFX_PSI5_CH_SCR_TRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SCR_Bits.TRQ */
+#define IFX_PSI5_CH_SCR_TRQ_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_CH_SCR_Bits.TSF */
+#define IFX_PSI5_CH_SCR_TSF_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SCR_Bits.TSF */
+#define IFX_PSI5_CH_SCR_TSF_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SCR_Bits.TSF */
+#define IFX_PSI5_CH_SCR_TSF_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD32 */
+#define IFX_PSI5_CH_SDRH_SD32_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD32 */
+#define IFX_PSI5_CH_SDRH_SD32_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD32 */
+#define IFX_PSI5_CH_SDRH_SD32_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD33 */
+#define IFX_PSI5_CH_SDRH_SD33_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD33 */
+#define IFX_PSI5_CH_SDRH_SD33_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD33 */
+#define IFX_PSI5_CH_SDRH_SD33_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD34 */
+#define IFX_PSI5_CH_SDRH_SD34_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD34 */
+#define IFX_PSI5_CH_SDRH_SD34_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD34 */
+#define IFX_PSI5_CH_SDRH_SD34_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD35 */
+#define IFX_PSI5_CH_SDRH_SD35_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD35 */
+#define IFX_PSI5_CH_SDRH_SD35_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD35 */
+#define IFX_PSI5_CH_SDRH_SD35_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD36 */
+#define IFX_PSI5_CH_SDRH_SD36_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD36 */
+#define IFX_PSI5_CH_SDRH_SD36_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD36 */
+#define IFX_PSI5_CH_SDRH_SD36_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD37 */
+#define IFX_PSI5_CH_SDRH_SD37_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD37 */
+#define IFX_PSI5_CH_SDRH_SD37_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD37 */
+#define IFX_PSI5_CH_SDRH_SD37_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD38 */
+#define IFX_PSI5_CH_SDRH_SD38_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD38 */
+#define IFX_PSI5_CH_SDRH_SD38_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD38 */
+#define IFX_PSI5_CH_SDRH_SD38_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD39 */
+#define IFX_PSI5_CH_SDRH_SD39_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD39 */
+#define IFX_PSI5_CH_SDRH_SD39_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD39 */
+#define IFX_PSI5_CH_SDRH_SD39_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD40 */
+#define IFX_PSI5_CH_SDRH_SD40_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD40 */
+#define IFX_PSI5_CH_SDRH_SD40_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD40 */
+#define IFX_PSI5_CH_SDRH_SD40_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD41 */
+#define IFX_PSI5_CH_SDRH_SD41_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD41 */
+#define IFX_PSI5_CH_SDRH_SD41_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD41 */
+#define IFX_PSI5_CH_SDRH_SD41_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD42 */
+#define IFX_PSI5_CH_SDRH_SD42_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD42 */
+#define IFX_PSI5_CH_SDRH_SD42_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD42 */
+#define IFX_PSI5_CH_SDRH_SD42_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD43 */
+#define IFX_PSI5_CH_SDRH_SD43_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD43 */
+#define IFX_PSI5_CH_SDRH_SD43_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD43 */
+#define IFX_PSI5_CH_SDRH_SD43_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD44 */
+#define IFX_PSI5_CH_SDRH_SD44_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD44 */
+#define IFX_PSI5_CH_SDRH_SD44_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD44 */
+#define IFX_PSI5_CH_SDRH_SD44_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD45 */
+#define IFX_PSI5_CH_SDRH_SD45_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD45 */
+#define IFX_PSI5_CH_SDRH_SD45_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD45 */
+#define IFX_PSI5_CH_SDRH_SD45_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD46 */
+#define IFX_PSI5_CH_SDRH_SD46_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD46 */
+#define IFX_PSI5_CH_SDRH_SD46_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD46 */
+#define IFX_PSI5_CH_SDRH_SD46_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD47 */
+#define IFX_PSI5_CH_SDRH_SD47_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD47 */
+#define IFX_PSI5_CH_SDRH_SD47_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD47 */
+#define IFX_PSI5_CH_SDRH_SD47_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD48 */
+#define IFX_PSI5_CH_SDRH_SD48_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD48 */
+#define IFX_PSI5_CH_SDRH_SD48_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD48 */
+#define IFX_PSI5_CH_SDRH_SD48_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD49 */
+#define IFX_PSI5_CH_SDRH_SD49_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD49 */
+#define IFX_PSI5_CH_SDRH_SD49_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD49 */
+#define IFX_PSI5_CH_SDRH_SD49_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD50 */
+#define IFX_PSI5_CH_SDRH_SD50_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD50 */
+#define IFX_PSI5_CH_SDRH_SD50_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD50 */
+#define IFX_PSI5_CH_SDRH_SD50_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD51 */
+#define IFX_PSI5_CH_SDRH_SD51_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD51 */
+#define IFX_PSI5_CH_SDRH_SD51_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD51 */
+#define IFX_PSI5_CH_SDRH_SD51_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD52 */
+#define IFX_PSI5_CH_SDRH_SD52_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD52 */
+#define IFX_PSI5_CH_SDRH_SD52_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD52 */
+#define IFX_PSI5_CH_SDRH_SD52_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD53 */
+#define IFX_PSI5_CH_SDRH_SD53_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD53 */
+#define IFX_PSI5_CH_SDRH_SD53_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD53 */
+#define IFX_PSI5_CH_SDRH_SD53_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD54 */
+#define IFX_PSI5_CH_SDRH_SD54_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD54 */
+#define IFX_PSI5_CH_SDRH_SD54_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD54 */
+#define IFX_PSI5_CH_SDRH_SD54_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD55 */
+#define IFX_PSI5_CH_SDRH_SD55_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD55 */
+#define IFX_PSI5_CH_SDRH_SD55_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD55 */
+#define IFX_PSI5_CH_SDRH_SD55_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD56 */
+#define IFX_PSI5_CH_SDRH_SD56_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD56 */
+#define IFX_PSI5_CH_SDRH_SD56_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD56 */
+#define IFX_PSI5_CH_SDRH_SD56_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD57 */
+#define IFX_PSI5_CH_SDRH_SD57_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD57 */
+#define IFX_PSI5_CH_SDRH_SD57_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD57 */
+#define IFX_PSI5_CH_SDRH_SD57_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD58 */
+#define IFX_PSI5_CH_SDRH_SD58_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD58 */
+#define IFX_PSI5_CH_SDRH_SD58_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD58 */
+#define IFX_PSI5_CH_SDRH_SD58_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD59 */
+#define IFX_PSI5_CH_SDRH_SD59_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD59 */
+#define IFX_PSI5_CH_SDRH_SD59_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD59 */
+#define IFX_PSI5_CH_SDRH_SD59_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD60 */
+#define IFX_PSI5_CH_SDRH_SD60_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD60 */
+#define IFX_PSI5_CH_SDRH_SD60_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD60 */
+#define IFX_PSI5_CH_SDRH_SD60_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD61 */
+#define IFX_PSI5_CH_SDRH_SD61_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD61 */
+#define IFX_PSI5_CH_SDRH_SD61_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD61 */
+#define IFX_PSI5_CH_SDRH_SD61_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD62 */
+#define IFX_PSI5_CH_SDRH_SD62_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD62 */
+#define IFX_PSI5_CH_SDRH_SD62_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD62 */
+#define IFX_PSI5_CH_SDRH_SD62_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRH_Bits.SD63 */
+#define IFX_PSI5_CH_SDRH_SD63_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRH_Bits.SD63 */
+#define IFX_PSI5_CH_SDRH_SD63_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRH_Bits.SD63 */
+#define IFX_PSI5_CH_SDRH_SD63_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD0 */
+#define IFX_PSI5_CH_SDRL_SD0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD0 */
+#define IFX_PSI5_CH_SDRL_SD0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD0 */
+#define IFX_PSI5_CH_SDRL_SD0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD10 */
+#define IFX_PSI5_CH_SDRL_SD10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD10 */
+#define IFX_PSI5_CH_SDRL_SD10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD10 */
+#define IFX_PSI5_CH_SDRL_SD10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD11 */
+#define IFX_PSI5_CH_SDRL_SD11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD11 */
+#define IFX_PSI5_CH_SDRL_SD11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD11 */
+#define IFX_PSI5_CH_SDRL_SD11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD12 */
+#define IFX_PSI5_CH_SDRL_SD12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD12 */
+#define IFX_PSI5_CH_SDRL_SD12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD12 */
+#define IFX_PSI5_CH_SDRL_SD12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD13 */
+#define IFX_PSI5_CH_SDRL_SD13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD13 */
+#define IFX_PSI5_CH_SDRL_SD13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD13 */
+#define IFX_PSI5_CH_SDRL_SD13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD14 */
+#define IFX_PSI5_CH_SDRL_SD14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD14 */
+#define IFX_PSI5_CH_SDRL_SD14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD14 */
+#define IFX_PSI5_CH_SDRL_SD14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD15 */
+#define IFX_PSI5_CH_SDRL_SD15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD15 */
+#define IFX_PSI5_CH_SDRL_SD15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD15 */
+#define IFX_PSI5_CH_SDRL_SD15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD16 */
+#define IFX_PSI5_CH_SDRL_SD16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD16 */
+#define IFX_PSI5_CH_SDRL_SD16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD16 */
+#define IFX_PSI5_CH_SDRL_SD16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD17 */
+#define IFX_PSI5_CH_SDRL_SD17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD17 */
+#define IFX_PSI5_CH_SDRL_SD17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD17 */
+#define IFX_PSI5_CH_SDRL_SD17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD18 */
+#define IFX_PSI5_CH_SDRL_SD18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD18 */
+#define IFX_PSI5_CH_SDRL_SD18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD18 */
+#define IFX_PSI5_CH_SDRL_SD18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD19 */
+#define IFX_PSI5_CH_SDRL_SD19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD19 */
+#define IFX_PSI5_CH_SDRL_SD19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD19 */
+#define IFX_PSI5_CH_SDRL_SD19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD1 */
+#define IFX_PSI5_CH_SDRL_SD1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD1 */
+#define IFX_PSI5_CH_SDRL_SD1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD1 */
+#define IFX_PSI5_CH_SDRL_SD1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD20 */
+#define IFX_PSI5_CH_SDRL_SD20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD20 */
+#define IFX_PSI5_CH_SDRL_SD20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD20 */
+#define IFX_PSI5_CH_SDRL_SD20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD21 */
+#define IFX_PSI5_CH_SDRL_SD21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD21 */
+#define IFX_PSI5_CH_SDRL_SD21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD21 */
+#define IFX_PSI5_CH_SDRL_SD21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD22 */
+#define IFX_PSI5_CH_SDRL_SD22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD22 */
+#define IFX_PSI5_CH_SDRL_SD22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD22 */
+#define IFX_PSI5_CH_SDRL_SD22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD23 */
+#define IFX_PSI5_CH_SDRL_SD23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD23 */
+#define IFX_PSI5_CH_SDRL_SD23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD23 */
+#define IFX_PSI5_CH_SDRL_SD23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD24 */
+#define IFX_PSI5_CH_SDRL_SD24_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD24 */
+#define IFX_PSI5_CH_SDRL_SD24_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD24 */
+#define IFX_PSI5_CH_SDRL_SD24_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD25 */
+#define IFX_PSI5_CH_SDRL_SD25_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD25 */
+#define IFX_PSI5_CH_SDRL_SD25_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD25 */
+#define IFX_PSI5_CH_SDRL_SD25_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD26 */
+#define IFX_PSI5_CH_SDRL_SD26_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD26 */
+#define IFX_PSI5_CH_SDRL_SD26_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD26 */
+#define IFX_PSI5_CH_SDRL_SD26_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD27 */
+#define IFX_PSI5_CH_SDRL_SD27_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD27 */
+#define IFX_PSI5_CH_SDRL_SD27_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD27 */
+#define IFX_PSI5_CH_SDRL_SD27_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD28 */
+#define IFX_PSI5_CH_SDRL_SD28_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD28 */
+#define IFX_PSI5_CH_SDRL_SD28_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD28 */
+#define IFX_PSI5_CH_SDRL_SD28_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD29 */
+#define IFX_PSI5_CH_SDRL_SD29_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD29 */
+#define IFX_PSI5_CH_SDRL_SD29_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD29 */
+#define IFX_PSI5_CH_SDRL_SD29_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD2 */
+#define IFX_PSI5_CH_SDRL_SD2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD2 */
+#define IFX_PSI5_CH_SDRL_SD2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD2 */
+#define IFX_PSI5_CH_SDRL_SD2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD30 */
+#define IFX_PSI5_CH_SDRL_SD30_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD30 */
+#define IFX_PSI5_CH_SDRL_SD30_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD30 */
+#define IFX_PSI5_CH_SDRL_SD30_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD31 */
+#define IFX_PSI5_CH_SDRL_SD31_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD31 */
+#define IFX_PSI5_CH_SDRL_SD31_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD31 */
+#define IFX_PSI5_CH_SDRL_SD31_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD3 */
+#define IFX_PSI5_CH_SDRL_SD3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD3 */
+#define IFX_PSI5_CH_SDRL_SD3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD3 */
+#define IFX_PSI5_CH_SDRL_SD3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD4 */
+#define IFX_PSI5_CH_SDRL_SD4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD4 */
+#define IFX_PSI5_CH_SDRL_SD4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD4 */
+#define IFX_PSI5_CH_SDRL_SD4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD5 */
+#define IFX_PSI5_CH_SDRL_SD5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD5 */
+#define IFX_PSI5_CH_SDRL_SD5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD5 */
+#define IFX_PSI5_CH_SDRL_SD5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD6 */
+#define IFX_PSI5_CH_SDRL_SD6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD6 */
+#define IFX_PSI5_CH_SDRL_SD6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD6 */
+#define IFX_PSI5_CH_SDRL_SD6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD7 */
+#define IFX_PSI5_CH_SDRL_SD7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD7 */
+#define IFX_PSI5_CH_SDRL_SD7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD7 */
+#define IFX_PSI5_CH_SDRL_SD7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD8 */
+#define IFX_PSI5_CH_SDRL_SD8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD8 */
+#define IFX_PSI5_CH_SDRL_SD8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD8 */
+#define IFX_PSI5_CH_SDRL_SD8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_CH_SDRL_Bits.SD9 */
+#define IFX_PSI5_CH_SDRL_SD9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDRL_Bits.SD9 */
+#define IFX_PSI5_CH_SDRL_SD9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDRL_Bits.SD9 */
+#define IFX_PSI5_CH_SDRL_SD9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_CH_SDS_Bits.CON */
+#define IFX_PSI5_CH_SDS_CON_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDS_Bits.CON */
+#define IFX_PSI5_CH_SDS_CON_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDS_Bits.CON */
+#define IFX_PSI5_CH_SDS_CON_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_CH_SDS_Bits.MID */
+#define IFX_PSI5_CH_SDS_MID_LEN (8u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDS_Bits.MID */
+#define IFX_PSI5_CH_SDS_MID_MSK (0xffu)
+
+/** \brief Offset for Ifx_PSI5_CH_SDS_Bits.MID */
+#define IFX_PSI5_CH_SDS_MID_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_CH_SDS_Bits.SCRC */
+#define IFX_PSI5_CH_SDS_SCRC_LEN (6u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDS_Bits.SCRC */
+#define IFX_PSI5_CH_SDS_SCRC_MSK (0x3fu)
+
+/** \brief Offset for Ifx_PSI5_CH_SDS_Bits.SCRC */
+#define IFX_PSI5_CH_SDS_SCRC_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_CH_SDS_Bits.SCRI */
+#define IFX_PSI5_CH_SDS_SCRI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDS_Bits.SCRI */
+#define IFX_PSI5_CH_SDS_SCRI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SDS_Bits.SCRI */
+#define IFX_PSI5_CH_SDS_SCRI_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_CH_SDS_Bits.SD */
+#define IFX_PSI5_CH_SDS_SD_LEN (16u)
+
+/** \brief Mask for Ifx_PSI5_CH_SDS_Bits.SD */
+#define IFX_PSI5_CH_SDS_SD_MSK (0xffffu)
+
+/** \brief Offset for Ifx_PSI5_CH_SDS_Bits.SD */
+#define IFX_PSI5_CH_SDS_SD_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_CH_SFTSC_Bits.TS */
+#define IFX_PSI5_CH_SFTSC_TS_LEN (24u)
+
+/** \brief Mask for Ifx_PSI5_CH_SFTSC_Bits.TS */
+#define IFX_PSI5_CH_SFTSC_TS_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_PSI5_CH_SFTSC_Bits.TS */
+#define IFX_PSI5_CH_SFTSC_TS_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD32 */
+#define IFX_PSI5_CH_SORH_SD32_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD32 */
+#define IFX_PSI5_CH_SORH_SD32_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD32 */
+#define IFX_PSI5_CH_SORH_SD32_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD33 */
+#define IFX_PSI5_CH_SORH_SD33_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD33 */
+#define IFX_PSI5_CH_SORH_SD33_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD33 */
+#define IFX_PSI5_CH_SORH_SD33_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD34 */
+#define IFX_PSI5_CH_SORH_SD34_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD34 */
+#define IFX_PSI5_CH_SORH_SD34_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD34 */
+#define IFX_PSI5_CH_SORH_SD34_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD35 */
+#define IFX_PSI5_CH_SORH_SD35_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD35 */
+#define IFX_PSI5_CH_SORH_SD35_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD35 */
+#define IFX_PSI5_CH_SORH_SD35_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD36 */
+#define IFX_PSI5_CH_SORH_SD36_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD36 */
+#define IFX_PSI5_CH_SORH_SD36_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD36 */
+#define IFX_PSI5_CH_SORH_SD36_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD37 */
+#define IFX_PSI5_CH_SORH_SD37_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD37 */
+#define IFX_PSI5_CH_SORH_SD37_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD37 */
+#define IFX_PSI5_CH_SORH_SD37_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD38 */
+#define IFX_PSI5_CH_SORH_SD38_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD38 */
+#define IFX_PSI5_CH_SORH_SD38_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD38 */
+#define IFX_PSI5_CH_SORH_SD38_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD39 */
+#define IFX_PSI5_CH_SORH_SD39_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD39 */
+#define IFX_PSI5_CH_SORH_SD39_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD39 */
+#define IFX_PSI5_CH_SORH_SD39_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD40 */
+#define IFX_PSI5_CH_SORH_SD40_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD40 */
+#define IFX_PSI5_CH_SORH_SD40_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD40 */
+#define IFX_PSI5_CH_SORH_SD40_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD41 */
+#define IFX_PSI5_CH_SORH_SD41_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD41 */
+#define IFX_PSI5_CH_SORH_SD41_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD41 */
+#define IFX_PSI5_CH_SORH_SD41_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD42 */
+#define IFX_PSI5_CH_SORH_SD42_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD42 */
+#define IFX_PSI5_CH_SORH_SD42_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD42 */
+#define IFX_PSI5_CH_SORH_SD42_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD43 */
+#define IFX_PSI5_CH_SORH_SD43_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD43 */
+#define IFX_PSI5_CH_SORH_SD43_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD43 */
+#define IFX_PSI5_CH_SORH_SD43_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD44 */
+#define IFX_PSI5_CH_SORH_SD44_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD44 */
+#define IFX_PSI5_CH_SORH_SD44_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD44 */
+#define IFX_PSI5_CH_SORH_SD44_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD45 */
+#define IFX_PSI5_CH_SORH_SD45_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD45 */
+#define IFX_PSI5_CH_SORH_SD45_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD45 */
+#define IFX_PSI5_CH_SORH_SD45_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD46 */
+#define IFX_PSI5_CH_SORH_SD46_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD46 */
+#define IFX_PSI5_CH_SORH_SD46_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD46 */
+#define IFX_PSI5_CH_SORH_SD46_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD47 */
+#define IFX_PSI5_CH_SORH_SD47_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD47 */
+#define IFX_PSI5_CH_SORH_SD47_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD47 */
+#define IFX_PSI5_CH_SORH_SD47_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD48 */
+#define IFX_PSI5_CH_SORH_SD48_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD48 */
+#define IFX_PSI5_CH_SORH_SD48_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD48 */
+#define IFX_PSI5_CH_SORH_SD48_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD49 */
+#define IFX_PSI5_CH_SORH_SD49_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD49 */
+#define IFX_PSI5_CH_SORH_SD49_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD49 */
+#define IFX_PSI5_CH_SORH_SD49_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD50 */
+#define IFX_PSI5_CH_SORH_SD50_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD50 */
+#define IFX_PSI5_CH_SORH_SD50_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD50 */
+#define IFX_PSI5_CH_SORH_SD50_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD51 */
+#define IFX_PSI5_CH_SORH_SD51_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD51 */
+#define IFX_PSI5_CH_SORH_SD51_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD51 */
+#define IFX_PSI5_CH_SORH_SD51_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD52 */
+#define IFX_PSI5_CH_SORH_SD52_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD52 */
+#define IFX_PSI5_CH_SORH_SD52_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD52 */
+#define IFX_PSI5_CH_SORH_SD52_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD53 */
+#define IFX_PSI5_CH_SORH_SD53_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD53 */
+#define IFX_PSI5_CH_SORH_SD53_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD53 */
+#define IFX_PSI5_CH_SORH_SD53_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD54 */
+#define IFX_PSI5_CH_SORH_SD54_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD54 */
+#define IFX_PSI5_CH_SORH_SD54_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD54 */
+#define IFX_PSI5_CH_SORH_SD54_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD55 */
+#define IFX_PSI5_CH_SORH_SD55_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD55 */
+#define IFX_PSI5_CH_SORH_SD55_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD55 */
+#define IFX_PSI5_CH_SORH_SD55_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD56 */
+#define IFX_PSI5_CH_SORH_SD56_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD56 */
+#define IFX_PSI5_CH_SORH_SD56_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD56 */
+#define IFX_PSI5_CH_SORH_SD56_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD57 */
+#define IFX_PSI5_CH_SORH_SD57_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD57 */
+#define IFX_PSI5_CH_SORH_SD57_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD57 */
+#define IFX_PSI5_CH_SORH_SD57_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD58 */
+#define IFX_PSI5_CH_SORH_SD58_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD58 */
+#define IFX_PSI5_CH_SORH_SD58_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD58 */
+#define IFX_PSI5_CH_SORH_SD58_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD59 */
+#define IFX_PSI5_CH_SORH_SD59_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD59 */
+#define IFX_PSI5_CH_SORH_SD59_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD59 */
+#define IFX_PSI5_CH_SORH_SD59_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD60 */
+#define IFX_PSI5_CH_SORH_SD60_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD60 */
+#define IFX_PSI5_CH_SORH_SD60_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD60 */
+#define IFX_PSI5_CH_SORH_SD60_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD61 */
+#define IFX_PSI5_CH_SORH_SD61_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD61 */
+#define IFX_PSI5_CH_SORH_SD61_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD61 */
+#define IFX_PSI5_CH_SORH_SD61_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD62 */
+#define IFX_PSI5_CH_SORH_SD62_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD62 */
+#define IFX_PSI5_CH_SORH_SD62_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD62 */
+#define IFX_PSI5_CH_SORH_SD62_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_CH_SORH_Bits.SD63 */
+#define IFX_PSI5_CH_SORH_SD63_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORH_Bits.SD63 */
+#define IFX_PSI5_CH_SORH_SD63_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORH_Bits.SD63 */
+#define IFX_PSI5_CH_SORH_SD63_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD0 */
+#define IFX_PSI5_CH_SORL_SD0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD0 */
+#define IFX_PSI5_CH_SORL_SD0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD0 */
+#define IFX_PSI5_CH_SORL_SD0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD10 */
+#define IFX_PSI5_CH_SORL_SD10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD10 */
+#define IFX_PSI5_CH_SORL_SD10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD10 */
+#define IFX_PSI5_CH_SORL_SD10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD11 */
+#define IFX_PSI5_CH_SORL_SD11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD11 */
+#define IFX_PSI5_CH_SORL_SD11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD11 */
+#define IFX_PSI5_CH_SORL_SD11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD12 */
+#define IFX_PSI5_CH_SORL_SD12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD12 */
+#define IFX_PSI5_CH_SORL_SD12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD12 */
+#define IFX_PSI5_CH_SORL_SD12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD13 */
+#define IFX_PSI5_CH_SORL_SD13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD13 */
+#define IFX_PSI5_CH_SORL_SD13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD13 */
+#define IFX_PSI5_CH_SORL_SD13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD14 */
+#define IFX_PSI5_CH_SORL_SD14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD14 */
+#define IFX_PSI5_CH_SORL_SD14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD14 */
+#define IFX_PSI5_CH_SORL_SD14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD15 */
+#define IFX_PSI5_CH_SORL_SD15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD15 */
+#define IFX_PSI5_CH_SORL_SD15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD15 */
+#define IFX_PSI5_CH_SORL_SD15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD16 */
+#define IFX_PSI5_CH_SORL_SD16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD16 */
+#define IFX_PSI5_CH_SORL_SD16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD16 */
+#define IFX_PSI5_CH_SORL_SD16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD17 */
+#define IFX_PSI5_CH_SORL_SD17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD17 */
+#define IFX_PSI5_CH_SORL_SD17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD17 */
+#define IFX_PSI5_CH_SORL_SD17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD18 */
+#define IFX_PSI5_CH_SORL_SD18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD18 */
+#define IFX_PSI5_CH_SORL_SD18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD18 */
+#define IFX_PSI5_CH_SORL_SD18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD19 */
+#define IFX_PSI5_CH_SORL_SD19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD19 */
+#define IFX_PSI5_CH_SORL_SD19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD19 */
+#define IFX_PSI5_CH_SORL_SD19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD1 */
+#define IFX_PSI5_CH_SORL_SD1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD1 */
+#define IFX_PSI5_CH_SORL_SD1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD1 */
+#define IFX_PSI5_CH_SORL_SD1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD20 */
+#define IFX_PSI5_CH_SORL_SD20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD20 */
+#define IFX_PSI5_CH_SORL_SD20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD20 */
+#define IFX_PSI5_CH_SORL_SD20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD21 */
+#define IFX_PSI5_CH_SORL_SD21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD21 */
+#define IFX_PSI5_CH_SORL_SD21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD21 */
+#define IFX_PSI5_CH_SORL_SD21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD22 */
+#define IFX_PSI5_CH_SORL_SD22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD22 */
+#define IFX_PSI5_CH_SORL_SD22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD22 */
+#define IFX_PSI5_CH_SORL_SD22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD23 */
+#define IFX_PSI5_CH_SORL_SD23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD23 */
+#define IFX_PSI5_CH_SORL_SD23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD23 */
+#define IFX_PSI5_CH_SORL_SD23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD24 */
+#define IFX_PSI5_CH_SORL_SD24_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD24 */
+#define IFX_PSI5_CH_SORL_SD24_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD24 */
+#define IFX_PSI5_CH_SORL_SD24_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD25 */
+#define IFX_PSI5_CH_SORL_SD25_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD25 */
+#define IFX_PSI5_CH_SORL_SD25_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD25 */
+#define IFX_PSI5_CH_SORL_SD25_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD26 */
+#define IFX_PSI5_CH_SORL_SD26_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD26 */
+#define IFX_PSI5_CH_SORL_SD26_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD26 */
+#define IFX_PSI5_CH_SORL_SD26_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD27 */
+#define IFX_PSI5_CH_SORL_SD27_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD27 */
+#define IFX_PSI5_CH_SORL_SD27_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD27 */
+#define IFX_PSI5_CH_SORL_SD27_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD28 */
+#define IFX_PSI5_CH_SORL_SD28_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD28 */
+#define IFX_PSI5_CH_SORL_SD28_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD28 */
+#define IFX_PSI5_CH_SORL_SD28_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD29 */
+#define IFX_PSI5_CH_SORL_SD29_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD29 */
+#define IFX_PSI5_CH_SORL_SD29_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD29 */
+#define IFX_PSI5_CH_SORL_SD29_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD2 */
+#define IFX_PSI5_CH_SORL_SD2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD2 */
+#define IFX_PSI5_CH_SORL_SD2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD2 */
+#define IFX_PSI5_CH_SORL_SD2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD30 */
+#define IFX_PSI5_CH_SORL_SD30_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD30 */
+#define IFX_PSI5_CH_SORL_SD30_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD30 */
+#define IFX_PSI5_CH_SORL_SD30_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD31 */
+#define IFX_PSI5_CH_SORL_SD31_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD31 */
+#define IFX_PSI5_CH_SORL_SD31_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD31 */
+#define IFX_PSI5_CH_SORL_SD31_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD3 */
+#define IFX_PSI5_CH_SORL_SD3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD3 */
+#define IFX_PSI5_CH_SORL_SD3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD3 */
+#define IFX_PSI5_CH_SORL_SD3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD4 */
+#define IFX_PSI5_CH_SORL_SD4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD4 */
+#define IFX_PSI5_CH_SORL_SD4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD4 */
+#define IFX_PSI5_CH_SORL_SD4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD5 */
+#define IFX_PSI5_CH_SORL_SD5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD5 */
+#define IFX_PSI5_CH_SORL_SD5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD5 */
+#define IFX_PSI5_CH_SORL_SD5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD6 */
+#define IFX_PSI5_CH_SORL_SD6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD6 */
+#define IFX_PSI5_CH_SORL_SD6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD6 */
+#define IFX_PSI5_CH_SORL_SD6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD7 */
+#define IFX_PSI5_CH_SORL_SD7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD7 */
+#define IFX_PSI5_CH_SORL_SD7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD7 */
+#define IFX_PSI5_CH_SORL_SD7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD8 */
+#define IFX_PSI5_CH_SORL_SD8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD8 */
+#define IFX_PSI5_CH_SORL_SD8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD8 */
+#define IFX_PSI5_CH_SORL_SD8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_CH_SORL_Bits.SD9 */
+#define IFX_PSI5_CH_SORL_SD9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SORL_Bits.SD9 */
+#define IFX_PSI5_CH_SORL_SD9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SORL_Bits.SD9 */
+#define IFX_PSI5_CH_SORL_SD9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_CH_SPTSC_Bits.TS */
+#define IFX_PSI5_CH_SPTSC_TS_LEN (24u)
+
+/** \brief Mask for Ifx_PSI5_CH_SPTSC_Bits.TS */
+#define IFX_PSI5_CH_SPTSC_TS_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_PSI5_CH_SPTSC_Bits.TS */
+#define IFX_PSI5_CH_SPTSC_TS_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD32 */
+#define IFX_PSI5_CH_SSRH_SD32_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD32 */
+#define IFX_PSI5_CH_SSRH_SD32_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD32 */
+#define IFX_PSI5_CH_SSRH_SD32_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD33 */
+#define IFX_PSI5_CH_SSRH_SD33_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD33 */
+#define IFX_PSI5_CH_SSRH_SD33_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD33 */
+#define IFX_PSI5_CH_SSRH_SD33_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD34 */
+#define IFX_PSI5_CH_SSRH_SD34_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD34 */
+#define IFX_PSI5_CH_SSRH_SD34_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD34 */
+#define IFX_PSI5_CH_SSRH_SD34_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD35 */
+#define IFX_PSI5_CH_SSRH_SD35_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD35 */
+#define IFX_PSI5_CH_SSRH_SD35_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD35 */
+#define IFX_PSI5_CH_SSRH_SD35_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD36 */
+#define IFX_PSI5_CH_SSRH_SD36_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD36 */
+#define IFX_PSI5_CH_SSRH_SD36_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD36 */
+#define IFX_PSI5_CH_SSRH_SD36_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD37 */
+#define IFX_PSI5_CH_SSRH_SD37_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD37 */
+#define IFX_PSI5_CH_SSRH_SD37_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD37 */
+#define IFX_PSI5_CH_SSRH_SD37_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD38 */
+#define IFX_PSI5_CH_SSRH_SD38_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD38 */
+#define IFX_PSI5_CH_SSRH_SD38_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD38 */
+#define IFX_PSI5_CH_SSRH_SD38_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD39 */
+#define IFX_PSI5_CH_SSRH_SD39_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD39 */
+#define IFX_PSI5_CH_SSRH_SD39_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD39 */
+#define IFX_PSI5_CH_SSRH_SD39_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD40 */
+#define IFX_PSI5_CH_SSRH_SD40_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD40 */
+#define IFX_PSI5_CH_SSRH_SD40_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD40 */
+#define IFX_PSI5_CH_SSRH_SD40_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD41 */
+#define IFX_PSI5_CH_SSRH_SD41_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD41 */
+#define IFX_PSI5_CH_SSRH_SD41_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD41 */
+#define IFX_PSI5_CH_SSRH_SD41_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD42 */
+#define IFX_PSI5_CH_SSRH_SD42_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD42 */
+#define IFX_PSI5_CH_SSRH_SD42_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD42 */
+#define IFX_PSI5_CH_SSRH_SD42_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD43 */
+#define IFX_PSI5_CH_SSRH_SD43_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD43 */
+#define IFX_PSI5_CH_SSRH_SD43_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD43 */
+#define IFX_PSI5_CH_SSRH_SD43_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD44 */
+#define IFX_PSI5_CH_SSRH_SD44_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD44 */
+#define IFX_PSI5_CH_SSRH_SD44_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD44 */
+#define IFX_PSI5_CH_SSRH_SD44_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD45 */
+#define IFX_PSI5_CH_SSRH_SD45_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD45 */
+#define IFX_PSI5_CH_SSRH_SD45_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD45 */
+#define IFX_PSI5_CH_SSRH_SD45_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD46 */
+#define IFX_PSI5_CH_SSRH_SD46_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD46 */
+#define IFX_PSI5_CH_SSRH_SD46_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD46 */
+#define IFX_PSI5_CH_SSRH_SD46_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD47 */
+#define IFX_PSI5_CH_SSRH_SD47_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD47 */
+#define IFX_PSI5_CH_SSRH_SD47_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD47 */
+#define IFX_PSI5_CH_SSRH_SD47_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD48 */
+#define IFX_PSI5_CH_SSRH_SD48_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD48 */
+#define IFX_PSI5_CH_SSRH_SD48_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD48 */
+#define IFX_PSI5_CH_SSRH_SD48_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD49 */
+#define IFX_PSI5_CH_SSRH_SD49_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD49 */
+#define IFX_PSI5_CH_SSRH_SD49_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD49 */
+#define IFX_PSI5_CH_SSRH_SD49_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD50 */
+#define IFX_PSI5_CH_SSRH_SD50_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD50 */
+#define IFX_PSI5_CH_SSRH_SD50_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD50 */
+#define IFX_PSI5_CH_SSRH_SD50_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD51 */
+#define IFX_PSI5_CH_SSRH_SD51_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD51 */
+#define IFX_PSI5_CH_SSRH_SD51_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD51 */
+#define IFX_PSI5_CH_SSRH_SD51_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD52 */
+#define IFX_PSI5_CH_SSRH_SD52_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD52 */
+#define IFX_PSI5_CH_SSRH_SD52_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD52 */
+#define IFX_PSI5_CH_SSRH_SD52_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD53 */
+#define IFX_PSI5_CH_SSRH_SD53_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD53 */
+#define IFX_PSI5_CH_SSRH_SD53_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD53 */
+#define IFX_PSI5_CH_SSRH_SD53_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD54 */
+#define IFX_PSI5_CH_SSRH_SD54_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD54 */
+#define IFX_PSI5_CH_SSRH_SD54_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD54 */
+#define IFX_PSI5_CH_SSRH_SD54_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD55 */
+#define IFX_PSI5_CH_SSRH_SD55_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD55 */
+#define IFX_PSI5_CH_SSRH_SD55_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD55 */
+#define IFX_PSI5_CH_SSRH_SD55_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD56 */
+#define IFX_PSI5_CH_SSRH_SD56_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD56 */
+#define IFX_PSI5_CH_SSRH_SD56_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD56 */
+#define IFX_PSI5_CH_SSRH_SD56_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD57 */
+#define IFX_PSI5_CH_SSRH_SD57_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD57 */
+#define IFX_PSI5_CH_SSRH_SD57_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD57 */
+#define IFX_PSI5_CH_SSRH_SD57_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD58 */
+#define IFX_PSI5_CH_SSRH_SD58_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD58 */
+#define IFX_PSI5_CH_SSRH_SD58_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD58 */
+#define IFX_PSI5_CH_SSRH_SD58_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD59 */
+#define IFX_PSI5_CH_SSRH_SD59_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD59 */
+#define IFX_PSI5_CH_SSRH_SD59_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD59 */
+#define IFX_PSI5_CH_SSRH_SD59_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD60 */
+#define IFX_PSI5_CH_SSRH_SD60_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD60 */
+#define IFX_PSI5_CH_SSRH_SD60_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD60 */
+#define IFX_PSI5_CH_SSRH_SD60_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD61 */
+#define IFX_PSI5_CH_SSRH_SD61_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD61 */
+#define IFX_PSI5_CH_SSRH_SD61_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD61 */
+#define IFX_PSI5_CH_SSRH_SD61_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD62 */
+#define IFX_PSI5_CH_SSRH_SD62_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD62 */
+#define IFX_PSI5_CH_SSRH_SD62_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD62 */
+#define IFX_PSI5_CH_SSRH_SD62_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRH_Bits.SD63 */
+#define IFX_PSI5_CH_SSRH_SD63_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRH_Bits.SD63 */
+#define IFX_PSI5_CH_SSRH_SD63_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRH_Bits.SD63 */
+#define IFX_PSI5_CH_SSRH_SD63_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD0 */
+#define IFX_PSI5_CH_SSRL_SD0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD0 */
+#define IFX_PSI5_CH_SSRL_SD0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD0 */
+#define IFX_PSI5_CH_SSRL_SD0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD10 */
+#define IFX_PSI5_CH_SSRL_SD10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD10 */
+#define IFX_PSI5_CH_SSRL_SD10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD10 */
+#define IFX_PSI5_CH_SSRL_SD10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD11 */
+#define IFX_PSI5_CH_SSRL_SD11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD11 */
+#define IFX_PSI5_CH_SSRL_SD11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD11 */
+#define IFX_PSI5_CH_SSRL_SD11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD12 */
+#define IFX_PSI5_CH_SSRL_SD12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD12 */
+#define IFX_PSI5_CH_SSRL_SD12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD12 */
+#define IFX_PSI5_CH_SSRL_SD12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD13 */
+#define IFX_PSI5_CH_SSRL_SD13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD13 */
+#define IFX_PSI5_CH_SSRL_SD13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD13 */
+#define IFX_PSI5_CH_SSRL_SD13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD14 */
+#define IFX_PSI5_CH_SSRL_SD14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD14 */
+#define IFX_PSI5_CH_SSRL_SD14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD14 */
+#define IFX_PSI5_CH_SSRL_SD14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD15 */
+#define IFX_PSI5_CH_SSRL_SD15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD15 */
+#define IFX_PSI5_CH_SSRL_SD15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD15 */
+#define IFX_PSI5_CH_SSRL_SD15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD16 */
+#define IFX_PSI5_CH_SSRL_SD16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD16 */
+#define IFX_PSI5_CH_SSRL_SD16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD16 */
+#define IFX_PSI5_CH_SSRL_SD16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD17 */
+#define IFX_PSI5_CH_SSRL_SD17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD17 */
+#define IFX_PSI5_CH_SSRL_SD17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD17 */
+#define IFX_PSI5_CH_SSRL_SD17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD18 */
+#define IFX_PSI5_CH_SSRL_SD18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD18 */
+#define IFX_PSI5_CH_SSRL_SD18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD18 */
+#define IFX_PSI5_CH_SSRL_SD18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD19 */
+#define IFX_PSI5_CH_SSRL_SD19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD19 */
+#define IFX_PSI5_CH_SSRL_SD19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD19 */
+#define IFX_PSI5_CH_SSRL_SD19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD1 */
+#define IFX_PSI5_CH_SSRL_SD1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD1 */
+#define IFX_PSI5_CH_SSRL_SD1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD1 */
+#define IFX_PSI5_CH_SSRL_SD1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD20 */
+#define IFX_PSI5_CH_SSRL_SD20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD20 */
+#define IFX_PSI5_CH_SSRL_SD20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD20 */
+#define IFX_PSI5_CH_SSRL_SD20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD21 */
+#define IFX_PSI5_CH_SSRL_SD21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD21 */
+#define IFX_PSI5_CH_SSRL_SD21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD21 */
+#define IFX_PSI5_CH_SSRL_SD21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD22 */
+#define IFX_PSI5_CH_SSRL_SD22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD22 */
+#define IFX_PSI5_CH_SSRL_SD22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD22 */
+#define IFX_PSI5_CH_SSRL_SD22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD23 */
+#define IFX_PSI5_CH_SSRL_SD23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD23 */
+#define IFX_PSI5_CH_SSRL_SD23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD23 */
+#define IFX_PSI5_CH_SSRL_SD23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD24 */
+#define IFX_PSI5_CH_SSRL_SD24_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD24 */
+#define IFX_PSI5_CH_SSRL_SD24_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD24 */
+#define IFX_PSI5_CH_SSRL_SD24_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD25 */
+#define IFX_PSI5_CH_SSRL_SD25_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD25 */
+#define IFX_PSI5_CH_SSRL_SD25_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD25 */
+#define IFX_PSI5_CH_SSRL_SD25_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD26 */
+#define IFX_PSI5_CH_SSRL_SD26_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD26 */
+#define IFX_PSI5_CH_SSRL_SD26_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD26 */
+#define IFX_PSI5_CH_SSRL_SD26_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD27 */
+#define IFX_PSI5_CH_SSRL_SD27_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD27 */
+#define IFX_PSI5_CH_SSRL_SD27_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD27 */
+#define IFX_PSI5_CH_SSRL_SD27_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD28 */
+#define IFX_PSI5_CH_SSRL_SD28_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD28 */
+#define IFX_PSI5_CH_SSRL_SD28_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD28 */
+#define IFX_PSI5_CH_SSRL_SD28_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD29 */
+#define IFX_PSI5_CH_SSRL_SD29_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD29 */
+#define IFX_PSI5_CH_SSRL_SD29_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD29 */
+#define IFX_PSI5_CH_SSRL_SD29_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD2 */
+#define IFX_PSI5_CH_SSRL_SD2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD2 */
+#define IFX_PSI5_CH_SSRL_SD2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD2 */
+#define IFX_PSI5_CH_SSRL_SD2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD30 */
+#define IFX_PSI5_CH_SSRL_SD30_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD30 */
+#define IFX_PSI5_CH_SSRL_SD30_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD30 */
+#define IFX_PSI5_CH_SSRL_SD30_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD31 */
+#define IFX_PSI5_CH_SSRL_SD31_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD31 */
+#define IFX_PSI5_CH_SSRL_SD31_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD31 */
+#define IFX_PSI5_CH_SSRL_SD31_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD3 */
+#define IFX_PSI5_CH_SSRL_SD3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD3 */
+#define IFX_PSI5_CH_SSRL_SD3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD3 */
+#define IFX_PSI5_CH_SSRL_SD3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD4 */
+#define IFX_PSI5_CH_SSRL_SD4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD4 */
+#define IFX_PSI5_CH_SSRL_SD4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD4 */
+#define IFX_PSI5_CH_SSRL_SD4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD5 */
+#define IFX_PSI5_CH_SSRL_SD5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD5 */
+#define IFX_PSI5_CH_SSRL_SD5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD5 */
+#define IFX_PSI5_CH_SSRL_SD5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD6 */
+#define IFX_PSI5_CH_SSRL_SD6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD6 */
+#define IFX_PSI5_CH_SSRL_SD6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD6 */
+#define IFX_PSI5_CH_SSRL_SD6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD7 */
+#define IFX_PSI5_CH_SSRL_SD7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD7 */
+#define IFX_PSI5_CH_SSRL_SD7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD7 */
+#define IFX_PSI5_CH_SSRL_SD7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD8 */
+#define IFX_PSI5_CH_SSRL_SD8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD8 */
+#define IFX_PSI5_CH_SSRL_SD8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD8 */
+#define IFX_PSI5_CH_SSRL_SD8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_CH_SSRL_Bits.SD9 */
+#define IFX_PSI5_CH_SSRL_SD9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CH_SSRL_Bits.SD9 */
+#define IFX_PSI5_CH_SSRL_SD9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CH_SSRL_Bits.SD9 */
+#define IFX_PSI5_CH_SSRL_SD9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_CH_WDT_Bits.WDLxw */
+#define IFX_PSI5_CH_WDT_WDLXW_LEN (16u)
+
+/** \brief Mask for Ifx_PSI5_CH_WDT_Bits.WDLxw */
+#define IFX_PSI5_CH_WDT_WDLXW_MSK (0xffffu)
+
+/** \brief Offset for Ifx_PSI5_CH_WDT_Bits.WDLxw */
+#define IFX_PSI5_CH_WDT_WDLXW_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_CLC_Bits.DISR */
+#define IFX_PSI5_CLC_DISR_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CLC_Bits.DISR */
+#define IFX_PSI5_CLC_DISR_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CLC_Bits.DISR */
+#define IFX_PSI5_CLC_DISR_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_CLC_Bits.DISS */
+#define IFX_PSI5_CLC_DISS_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CLC_Bits.DISS */
+#define IFX_PSI5_CLC_DISS_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CLC_Bits.DISS */
+#define IFX_PSI5_CLC_DISS_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI0 */
+#define IFX_PSI5_CRCICLR_CRCI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI0 */
+#define IFX_PSI5_CRCICLR_CRCI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI0 */
+#define IFX_PSI5_CRCICLR_CRCI0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI10 */
+#define IFX_PSI5_CRCICLR_CRCI10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI10 */
+#define IFX_PSI5_CRCICLR_CRCI10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI10 */
+#define IFX_PSI5_CRCICLR_CRCI10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI11 */
+#define IFX_PSI5_CRCICLR_CRCI11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI11 */
+#define IFX_PSI5_CRCICLR_CRCI11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI11 */
+#define IFX_PSI5_CRCICLR_CRCI11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI12 */
+#define IFX_PSI5_CRCICLR_CRCI12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI12 */
+#define IFX_PSI5_CRCICLR_CRCI12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI12 */
+#define IFX_PSI5_CRCICLR_CRCI12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI13 */
+#define IFX_PSI5_CRCICLR_CRCI13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI13 */
+#define IFX_PSI5_CRCICLR_CRCI13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI13 */
+#define IFX_PSI5_CRCICLR_CRCI13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI14 */
+#define IFX_PSI5_CRCICLR_CRCI14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI14 */
+#define IFX_PSI5_CRCICLR_CRCI14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI14 */
+#define IFX_PSI5_CRCICLR_CRCI14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI15 */
+#define IFX_PSI5_CRCICLR_CRCI15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI15 */
+#define IFX_PSI5_CRCICLR_CRCI15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI15 */
+#define IFX_PSI5_CRCICLR_CRCI15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI16 */
+#define IFX_PSI5_CRCICLR_CRCI16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI16 */
+#define IFX_PSI5_CRCICLR_CRCI16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI16 */
+#define IFX_PSI5_CRCICLR_CRCI16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI17 */
+#define IFX_PSI5_CRCICLR_CRCI17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI17 */
+#define IFX_PSI5_CRCICLR_CRCI17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI17 */
+#define IFX_PSI5_CRCICLR_CRCI17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI18 */
+#define IFX_PSI5_CRCICLR_CRCI18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI18 */
+#define IFX_PSI5_CRCICLR_CRCI18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI18 */
+#define IFX_PSI5_CRCICLR_CRCI18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI19 */
+#define IFX_PSI5_CRCICLR_CRCI19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI19 */
+#define IFX_PSI5_CRCICLR_CRCI19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI19 */
+#define IFX_PSI5_CRCICLR_CRCI19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI1 */
+#define IFX_PSI5_CRCICLR_CRCI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI1 */
+#define IFX_PSI5_CRCICLR_CRCI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI1 */
+#define IFX_PSI5_CRCICLR_CRCI1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI20 */
+#define IFX_PSI5_CRCICLR_CRCI20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI20 */
+#define IFX_PSI5_CRCICLR_CRCI20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI20 */
+#define IFX_PSI5_CRCICLR_CRCI20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI21 */
+#define IFX_PSI5_CRCICLR_CRCI21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI21 */
+#define IFX_PSI5_CRCICLR_CRCI21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI21 */
+#define IFX_PSI5_CRCICLR_CRCI21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI22 */
+#define IFX_PSI5_CRCICLR_CRCI22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI22 */
+#define IFX_PSI5_CRCICLR_CRCI22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI22 */
+#define IFX_PSI5_CRCICLR_CRCI22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI23 */
+#define IFX_PSI5_CRCICLR_CRCI23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI23 */
+#define IFX_PSI5_CRCICLR_CRCI23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI23 */
+#define IFX_PSI5_CRCICLR_CRCI23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI24 */
+#define IFX_PSI5_CRCICLR_CRCI24_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI24 */
+#define IFX_PSI5_CRCICLR_CRCI24_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI24 */
+#define IFX_PSI5_CRCICLR_CRCI24_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI25 */
+#define IFX_PSI5_CRCICLR_CRCI25_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI25 */
+#define IFX_PSI5_CRCICLR_CRCI25_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI25 */
+#define IFX_PSI5_CRCICLR_CRCI25_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI26 */
+#define IFX_PSI5_CRCICLR_CRCI26_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI26 */
+#define IFX_PSI5_CRCICLR_CRCI26_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI26 */
+#define IFX_PSI5_CRCICLR_CRCI26_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI27 */
+#define IFX_PSI5_CRCICLR_CRCI27_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI27 */
+#define IFX_PSI5_CRCICLR_CRCI27_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI27 */
+#define IFX_PSI5_CRCICLR_CRCI27_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI28 */
+#define IFX_PSI5_CRCICLR_CRCI28_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI28 */
+#define IFX_PSI5_CRCICLR_CRCI28_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI28 */
+#define IFX_PSI5_CRCICLR_CRCI28_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI29 */
+#define IFX_PSI5_CRCICLR_CRCI29_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI29 */
+#define IFX_PSI5_CRCICLR_CRCI29_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI29 */
+#define IFX_PSI5_CRCICLR_CRCI29_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI2 */
+#define IFX_PSI5_CRCICLR_CRCI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI2 */
+#define IFX_PSI5_CRCICLR_CRCI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI2 */
+#define IFX_PSI5_CRCICLR_CRCI2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI30 */
+#define IFX_PSI5_CRCICLR_CRCI30_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI30 */
+#define IFX_PSI5_CRCICLR_CRCI30_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI30 */
+#define IFX_PSI5_CRCICLR_CRCI30_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI31 */
+#define IFX_PSI5_CRCICLR_CRCI31_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI31 */
+#define IFX_PSI5_CRCICLR_CRCI31_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI31 */
+#define IFX_PSI5_CRCICLR_CRCI31_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI3 */
+#define IFX_PSI5_CRCICLR_CRCI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI3 */
+#define IFX_PSI5_CRCICLR_CRCI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI3 */
+#define IFX_PSI5_CRCICLR_CRCI3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI4 */
+#define IFX_PSI5_CRCICLR_CRCI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI4 */
+#define IFX_PSI5_CRCICLR_CRCI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI4 */
+#define IFX_PSI5_CRCICLR_CRCI4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI5 */
+#define IFX_PSI5_CRCICLR_CRCI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI5 */
+#define IFX_PSI5_CRCICLR_CRCI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI5 */
+#define IFX_PSI5_CRCICLR_CRCI5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI6 */
+#define IFX_PSI5_CRCICLR_CRCI6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI6 */
+#define IFX_PSI5_CRCICLR_CRCI6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI6 */
+#define IFX_PSI5_CRCICLR_CRCI6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI7 */
+#define IFX_PSI5_CRCICLR_CRCI7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI7 */
+#define IFX_PSI5_CRCICLR_CRCI7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI7 */
+#define IFX_PSI5_CRCICLR_CRCI7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI8 */
+#define IFX_PSI5_CRCICLR_CRCI8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI8 */
+#define IFX_PSI5_CRCICLR_CRCI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI8 */
+#define IFX_PSI5_CRCICLR_CRCI8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_CRCICLR_Bits.CRCI9 */
+#define IFX_PSI5_CRCICLR_CRCI9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCICLR_Bits.CRCI9 */
+#define IFX_PSI5_CRCICLR_CRCI9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCICLR_Bits.CRCI9 */
+#define IFX_PSI5_CRCICLR_CRCI9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI0 */
+#define IFX_PSI5_CRCIOV_CRCI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI0 */
+#define IFX_PSI5_CRCIOV_CRCI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI0 */
+#define IFX_PSI5_CRCIOV_CRCI0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI10 */
+#define IFX_PSI5_CRCIOV_CRCI10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI10 */
+#define IFX_PSI5_CRCIOV_CRCI10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI10 */
+#define IFX_PSI5_CRCIOV_CRCI10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI11 */
+#define IFX_PSI5_CRCIOV_CRCI11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI11 */
+#define IFX_PSI5_CRCIOV_CRCI11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI11 */
+#define IFX_PSI5_CRCIOV_CRCI11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI12 */
+#define IFX_PSI5_CRCIOV_CRCI12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI12 */
+#define IFX_PSI5_CRCIOV_CRCI12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI12 */
+#define IFX_PSI5_CRCIOV_CRCI12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI13 */
+#define IFX_PSI5_CRCIOV_CRCI13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI13 */
+#define IFX_PSI5_CRCIOV_CRCI13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI13 */
+#define IFX_PSI5_CRCIOV_CRCI13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI14 */
+#define IFX_PSI5_CRCIOV_CRCI14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI14 */
+#define IFX_PSI5_CRCIOV_CRCI14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI14 */
+#define IFX_PSI5_CRCIOV_CRCI14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI15 */
+#define IFX_PSI5_CRCIOV_CRCI15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI15 */
+#define IFX_PSI5_CRCIOV_CRCI15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI15 */
+#define IFX_PSI5_CRCIOV_CRCI15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI16 */
+#define IFX_PSI5_CRCIOV_CRCI16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI16 */
+#define IFX_PSI5_CRCIOV_CRCI16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI16 */
+#define IFX_PSI5_CRCIOV_CRCI16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI17 */
+#define IFX_PSI5_CRCIOV_CRCI17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI17 */
+#define IFX_PSI5_CRCIOV_CRCI17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI17 */
+#define IFX_PSI5_CRCIOV_CRCI17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI18 */
+#define IFX_PSI5_CRCIOV_CRCI18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI18 */
+#define IFX_PSI5_CRCIOV_CRCI18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI18 */
+#define IFX_PSI5_CRCIOV_CRCI18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI19 */
+#define IFX_PSI5_CRCIOV_CRCI19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI19 */
+#define IFX_PSI5_CRCIOV_CRCI19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI19 */
+#define IFX_PSI5_CRCIOV_CRCI19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI1 */
+#define IFX_PSI5_CRCIOV_CRCI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI1 */
+#define IFX_PSI5_CRCIOV_CRCI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI1 */
+#define IFX_PSI5_CRCIOV_CRCI1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI20 */
+#define IFX_PSI5_CRCIOV_CRCI20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI20 */
+#define IFX_PSI5_CRCIOV_CRCI20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI20 */
+#define IFX_PSI5_CRCIOV_CRCI20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI21 */
+#define IFX_PSI5_CRCIOV_CRCI21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI21 */
+#define IFX_PSI5_CRCIOV_CRCI21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI21 */
+#define IFX_PSI5_CRCIOV_CRCI21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI22 */
+#define IFX_PSI5_CRCIOV_CRCI22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI22 */
+#define IFX_PSI5_CRCIOV_CRCI22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI22 */
+#define IFX_PSI5_CRCIOV_CRCI22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI23 */
+#define IFX_PSI5_CRCIOV_CRCI23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI23 */
+#define IFX_PSI5_CRCIOV_CRCI23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI23 */
+#define IFX_PSI5_CRCIOV_CRCI23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI24 */
+#define IFX_PSI5_CRCIOV_CRCI24_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI24 */
+#define IFX_PSI5_CRCIOV_CRCI24_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI24 */
+#define IFX_PSI5_CRCIOV_CRCI24_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI25 */
+#define IFX_PSI5_CRCIOV_CRCI25_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI25 */
+#define IFX_PSI5_CRCIOV_CRCI25_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI25 */
+#define IFX_PSI5_CRCIOV_CRCI25_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI26 */
+#define IFX_PSI5_CRCIOV_CRCI26_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI26 */
+#define IFX_PSI5_CRCIOV_CRCI26_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI26 */
+#define IFX_PSI5_CRCIOV_CRCI26_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI27 */
+#define IFX_PSI5_CRCIOV_CRCI27_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI27 */
+#define IFX_PSI5_CRCIOV_CRCI27_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI27 */
+#define IFX_PSI5_CRCIOV_CRCI27_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI28 */
+#define IFX_PSI5_CRCIOV_CRCI28_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI28 */
+#define IFX_PSI5_CRCIOV_CRCI28_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI28 */
+#define IFX_PSI5_CRCIOV_CRCI28_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI29 */
+#define IFX_PSI5_CRCIOV_CRCI29_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI29 */
+#define IFX_PSI5_CRCIOV_CRCI29_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI29 */
+#define IFX_PSI5_CRCIOV_CRCI29_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI2 */
+#define IFX_PSI5_CRCIOV_CRCI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI2 */
+#define IFX_PSI5_CRCIOV_CRCI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI2 */
+#define IFX_PSI5_CRCIOV_CRCI2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI30 */
+#define IFX_PSI5_CRCIOV_CRCI30_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI30 */
+#define IFX_PSI5_CRCIOV_CRCI30_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI30 */
+#define IFX_PSI5_CRCIOV_CRCI30_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI31 */
+#define IFX_PSI5_CRCIOV_CRCI31_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI31 */
+#define IFX_PSI5_CRCIOV_CRCI31_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI31 */
+#define IFX_PSI5_CRCIOV_CRCI31_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI3 */
+#define IFX_PSI5_CRCIOV_CRCI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI3 */
+#define IFX_PSI5_CRCIOV_CRCI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI3 */
+#define IFX_PSI5_CRCIOV_CRCI3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI4 */
+#define IFX_PSI5_CRCIOV_CRCI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI4 */
+#define IFX_PSI5_CRCIOV_CRCI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI4 */
+#define IFX_PSI5_CRCIOV_CRCI4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI5 */
+#define IFX_PSI5_CRCIOV_CRCI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI5 */
+#define IFX_PSI5_CRCIOV_CRCI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI5 */
+#define IFX_PSI5_CRCIOV_CRCI5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI6 */
+#define IFX_PSI5_CRCIOV_CRCI6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI6 */
+#define IFX_PSI5_CRCIOV_CRCI6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI6 */
+#define IFX_PSI5_CRCIOV_CRCI6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI7 */
+#define IFX_PSI5_CRCIOV_CRCI7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI7 */
+#define IFX_PSI5_CRCIOV_CRCI7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI7 */
+#define IFX_PSI5_CRCIOV_CRCI7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI8 */
+#define IFX_PSI5_CRCIOV_CRCI8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI8 */
+#define IFX_PSI5_CRCIOV_CRCI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI8 */
+#define IFX_PSI5_CRCIOV_CRCI8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_CRCIOV_Bits.CRCI9 */
+#define IFX_PSI5_CRCIOV_CRCI9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCIOV_Bits.CRCI9 */
+#define IFX_PSI5_CRCIOV_CRCI9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCIOV_Bits.CRCI9 */
+#define IFX_PSI5_CRCIOV_CRCI9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI0 */
+#define IFX_PSI5_CRCISET_CRCI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI0 */
+#define IFX_PSI5_CRCISET_CRCI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI0 */
+#define IFX_PSI5_CRCISET_CRCI0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI10 */
+#define IFX_PSI5_CRCISET_CRCI10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI10 */
+#define IFX_PSI5_CRCISET_CRCI10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI10 */
+#define IFX_PSI5_CRCISET_CRCI10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI11 */
+#define IFX_PSI5_CRCISET_CRCI11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI11 */
+#define IFX_PSI5_CRCISET_CRCI11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI11 */
+#define IFX_PSI5_CRCISET_CRCI11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI12 */
+#define IFX_PSI5_CRCISET_CRCI12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI12 */
+#define IFX_PSI5_CRCISET_CRCI12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI12 */
+#define IFX_PSI5_CRCISET_CRCI12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI13 */
+#define IFX_PSI5_CRCISET_CRCI13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI13 */
+#define IFX_PSI5_CRCISET_CRCI13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI13 */
+#define IFX_PSI5_CRCISET_CRCI13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI14 */
+#define IFX_PSI5_CRCISET_CRCI14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI14 */
+#define IFX_PSI5_CRCISET_CRCI14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI14 */
+#define IFX_PSI5_CRCISET_CRCI14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI15 */
+#define IFX_PSI5_CRCISET_CRCI15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI15 */
+#define IFX_PSI5_CRCISET_CRCI15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI15 */
+#define IFX_PSI5_CRCISET_CRCI15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI16 */
+#define IFX_PSI5_CRCISET_CRCI16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI16 */
+#define IFX_PSI5_CRCISET_CRCI16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI16 */
+#define IFX_PSI5_CRCISET_CRCI16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI17 */
+#define IFX_PSI5_CRCISET_CRCI17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI17 */
+#define IFX_PSI5_CRCISET_CRCI17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI17 */
+#define IFX_PSI5_CRCISET_CRCI17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI18 */
+#define IFX_PSI5_CRCISET_CRCI18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI18 */
+#define IFX_PSI5_CRCISET_CRCI18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI18 */
+#define IFX_PSI5_CRCISET_CRCI18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI19 */
+#define IFX_PSI5_CRCISET_CRCI19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI19 */
+#define IFX_PSI5_CRCISET_CRCI19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI19 */
+#define IFX_PSI5_CRCISET_CRCI19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI1 */
+#define IFX_PSI5_CRCISET_CRCI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI1 */
+#define IFX_PSI5_CRCISET_CRCI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI1 */
+#define IFX_PSI5_CRCISET_CRCI1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI20 */
+#define IFX_PSI5_CRCISET_CRCI20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI20 */
+#define IFX_PSI5_CRCISET_CRCI20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI20 */
+#define IFX_PSI5_CRCISET_CRCI20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI21 */
+#define IFX_PSI5_CRCISET_CRCI21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI21 */
+#define IFX_PSI5_CRCISET_CRCI21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI21 */
+#define IFX_PSI5_CRCISET_CRCI21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI22 */
+#define IFX_PSI5_CRCISET_CRCI22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI22 */
+#define IFX_PSI5_CRCISET_CRCI22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI22 */
+#define IFX_PSI5_CRCISET_CRCI22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI23 */
+#define IFX_PSI5_CRCISET_CRCI23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI23 */
+#define IFX_PSI5_CRCISET_CRCI23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI23 */
+#define IFX_PSI5_CRCISET_CRCI23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI24 */
+#define IFX_PSI5_CRCISET_CRCI24_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI24 */
+#define IFX_PSI5_CRCISET_CRCI24_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI24 */
+#define IFX_PSI5_CRCISET_CRCI24_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI25 */
+#define IFX_PSI5_CRCISET_CRCI25_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI25 */
+#define IFX_PSI5_CRCISET_CRCI25_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI25 */
+#define IFX_PSI5_CRCISET_CRCI25_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI26 */
+#define IFX_PSI5_CRCISET_CRCI26_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI26 */
+#define IFX_PSI5_CRCISET_CRCI26_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI26 */
+#define IFX_PSI5_CRCISET_CRCI26_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI27 */
+#define IFX_PSI5_CRCISET_CRCI27_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI27 */
+#define IFX_PSI5_CRCISET_CRCI27_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI27 */
+#define IFX_PSI5_CRCISET_CRCI27_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI28 */
+#define IFX_PSI5_CRCISET_CRCI28_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI28 */
+#define IFX_PSI5_CRCISET_CRCI28_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI28 */
+#define IFX_PSI5_CRCISET_CRCI28_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI29 */
+#define IFX_PSI5_CRCISET_CRCI29_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI29 */
+#define IFX_PSI5_CRCISET_CRCI29_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI29 */
+#define IFX_PSI5_CRCISET_CRCI29_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI2 */
+#define IFX_PSI5_CRCISET_CRCI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI2 */
+#define IFX_PSI5_CRCISET_CRCI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI2 */
+#define IFX_PSI5_CRCISET_CRCI2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI30 */
+#define IFX_PSI5_CRCISET_CRCI30_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI30 */
+#define IFX_PSI5_CRCISET_CRCI30_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI30 */
+#define IFX_PSI5_CRCISET_CRCI30_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI31 */
+#define IFX_PSI5_CRCISET_CRCI31_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI31 */
+#define IFX_PSI5_CRCISET_CRCI31_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI31 */
+#define IFX_PSI5_CRCISET_CRCI31_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI3 */
+#define IFX_PSI5_CRCISET_CRCI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI3 */
+#define IFX_PSI5_CRCISET_CRCI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI3 */
+#define IFX_PSI5_CRCISET_CRCI3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI4 */
+#define IFX_PSI5_CRCISET_CRCI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI4 */
+#define IFX_PSI5_CRCISET_CRCI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI4 */
+#define IFX_PSI5_CRCISET_CRCI4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI5 */
+#define IFX_PSI5_CRCISET_CRCI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI5 */
+#define IFX_PSI5_CRCISET_CRCI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI5 */
+#define IFX_PSI5_CRCISET_CRCI5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI6 */
+#define IFX_PSI5_CRCISET_CRCI6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI6 */
+#define IFX_PSI5_CRCISET_CRCI6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI6 */
+#define IFX_PSI5_CRCISET_CRCI6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI7 */
+#define IFX_PSI5_CRCISET_CRCI7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI7 */
+#define IFX_PSI5_CRCISET_CRCI7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI7 */
+#define IFX_PSI5_CRCISET_CRCI7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI8 */
+#define IFX_PSI5_CRCISET_CRCI8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI8 */
+#define IFX_PSI5_CRCISET_CRCI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI8 */
+#define IFX_PSI5_CRCISET_CRCI8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_CRCISET_Bits.CRCI9 */
+#define IFX_PSI5_CRCISET_CRCI9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_CRCISET_Bits.CRCI9 */
+#define IFX_PSI5_CRCISET_CRCI9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_CRCISET_Bits.CRCI9 */
+#define IFX_PSI5_CRCISET_CRCI9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_FDR_Bits.DM */
+#define IFX_PSI5_FDR_DM_LEN (2u)
+
+/** \brief Mask for Ifx_PSI5_FDR_Bits.DM */
+#define IFX_PSI5_FDR_DM_MSK (0x3u)
+
+/** \brief Offset for Ifx_PSI5_FDR_Bits.DM */
+#define IFX_PSI5_FDR_DM_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_FDR_Bits.RESULT */
+#define IFX_PSI5_FDR_RESULT_LEN (10u)
+
+/** \brief Mask for Ifx_PSI5_FDR_Bits.RESULT */
+#define IFX_PSI5_FDR_RESULT_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_PSI5_FDR_Bits.RESULT */
+#define IFX_PSI5_FDR_RESULT_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_FDR_Bits.STEP */
+#define IFX_PSI5_FDR_STEP_LEN (10u)
+
+/** \brief Mask for Ifx_PSI5_FDR_Bits.STEP */
+#define IFX_PSI5_FDR_STEP_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_PSI5_FDR_Bits.STEP */
+#define IFX_PSI5_FDR_STEP_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_FDRH_Bits.DM */
+#define IFX_PSI5_FDRH_DM_LEN (2u)
+
+/** \brief Mask for Ifx_PSI5_FDRH_Bits.DM */
+#define IFX_PSI5_FDRH_DM_MSK (0x3u)
+
+/** \brief Offset for Ifx_PSI5_FDRH_Bits.DM */
+#define IFX_PSI5_FDRH_DM_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_FDRH_Bits.RESULT */
+#define IFX_PSI5_FDRH_RESULT_LEN (10u)
+
+/** \brief Mask for Ifx_PSI5_FDRH_Bits.RESULT */
+#define IFX_PSI5_FDRH_RESULT_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_PSI5_FDRH_Bits.RESULT */
+#define IFX_PSI5_FDRH_RESULT_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_FDRH_Bits.STEP */
+#define IFX_PSI5_FDRH_STEP_LEN (10u)
+
+/** \brief Mask for Ifx_PSI5_FDRH_Bits.STEP */
+#define IFX_PSI5_FDRH_STEP_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_PSI5_FDRH_Bits.STEP */
+#define IFX_PSI5_FDRH_STEP_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_FDRL_Bits.DM */
+#define IFX_PSI5_FDRL_DM_LEN (2u)
+
+/** \brief Mask for Ifx_PSI5_FDRL_Bits.DM */
+#define IFX_PSI5_FDRL_DM_MSK (0x3u)
+
+/** \brief Offset for Ifx_PSI5_FDRL_Bits.DM */
+#define IFX_PSI5_FDRL_DM_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_FDRL_Bits.RESULT */
+#define IFX_PSI5_FDRL_RESULT_LEN (10u)
+
+/** \brief Mask for Ifx_PSI5_FDRL_Bits.RESULT */
+#define IFX_PSI5_FDRL_RESULT_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_PSI5_FDRL_Bits.RESULT */
+#define IFX_PSI5_FDRL_RESULT_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_FDRL_Bits.STEP */
+#define IFX_PSI5_FDRL_STEP_LEN (10u)
+
+/** \brief Mask for Ifx_PSI5_FDRL_Bits.STEP */
+#define IFX_PSI5_FDRL_STEP_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_PSI5_FDRL_Bits.STEP */
+#define IFX_PSI5_FDRL_STEP_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_FDRT_Bits.DM */
+#define IFX_PSI5_FDRT_DM_LEN (2u)
+
+/** \brief Mask for Ifx_PSI5_FDRT_Bits.DM */
+#define IFX_PSI5_FDRT_DM_MSK (0x3u)
+
+/** \brief Offset for Ifx_PSI5_FDRT_Bits.DM */
+#define IFX_PSI5_FDRT_DM_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_FDRT_Bits.ECEA */
+#define IFX_PSI5_FDRT_ECEA_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_FDRT_Bits.ECEA */
+#define IFX_PSI5_FDRT_ECEA_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_FDRT_Bits.ECEA */
+#define IFX_PSI5_FDRT_ECEA_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_FDRT_Bits.ECEB */
+#define IFX_PSI5_FDRT_ECEB_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_FDRT_Bits.ECEB */
+#define IFX_PSI5_FDRT_ECEB_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_FDRT_Bits.ECEB */
+#define IFX_PSI5_FDRT_ECEB_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_FDRT_Bits.ECEC */
+#define IFX_PSI5_FDRT_ECEC_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_FDRT_Bits.ECEC */
+#define IFX_PSI5_FDRT_ECEC_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_FDRT_Bits.ECEC */
+#define IFX_PSI5_FDRT_ECEC_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_FDRT_Bits.ECS */
+#define IFX_PSI5_FDRT_ECS_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5_FDRT_Bits.ECS */
+#define IFX_PSI5_FDRT_ECS_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5_FDRT_Bits.ECS */
+#define IFX_PSI5_FDRT_ECS_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_FDRT_Bits.RESULT */
+#define IFX_PSI5_FDRT_RESULT_LEN (10u)
+
+/** \brief Mask for Ifx_PSI5_FDRT_Bits.RESULT */
+#define IFX_PSI5_FDRT_RESULT_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_PSI5_FDRT_Bits.RESULT */
+#define IFX_PSI5_FDRT_RESULT_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_FDRT_Bits.STEP */
+#define IFX_PSI5_FDRT_STEP_LEN (10u)
+
+/** \brief Mask for Ifx_PSI5_FDRT_Bits.STEP */
+#define IFX_PSI5_FDRT_STEP_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_PSI5_FDRT_Bits.STEP */
+#define IFX_PSI5_FDRT_STEP_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_GCR_Bits.CEN0 */
+#define IFX_PSI5_GCR_CEN0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_GCR_Bits.CEN0 */
+#define IFX_PSI5_GCR_CEN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_GCR_Bits.CEN0 */
+#define IFX_PSI5_GCR_CEN0_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_GCR_Bits.CEN1 */
+#define IFX_PSI5_GCR_CEN1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_GCR_Bits.CEN1 */
+#define IFX_PSI5_GCR_CEN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_GCR_Bits.CEN1 */
+#define IFX_PSI5_GCR_CEN1_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_GCR_Bits.CEN2 */
+#define IFX_PSI5_GCR_CEN2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_GCR_Bits.CEN2 */
+#define IFX_PSI5_GCR_CEN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_GCR_Bits.CEN2 */
+#define IFX_PSI5_GCR_CEN2_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_GCR_Bits.CEN3 */
+#define IFX_PSI5_GCR_CEN3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_GCR_Bits.CEN3 */
+#define IFX_PSI5_GCR_CEN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_GCR_Bits.CEN3 */
+#define IFX_PSI5_GCR_CEN3_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_GCR_Bits.CEN4 */
+#define IFX_PSI5_GCR_CEN4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_GCR_Bits.CEN4 */
+#define IFX_PSI5_GCR_CEN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_GCR_Bits.CEN4 */
+#define IFX_PSI5_GCR_CEN4_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_GCR_Bits.CRCI */
+#define IFX_PSI5_GCR_CRCI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_GCR_Bits.CRCI */
+#define IFX_PSI5_GCR_CRCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_GCR_Bits.CRCI */
+#define IFX_PSI5_GCR_CRCI_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_GCR_Bits.ETC0 */
+#define IFX_PSI5_GCR_ETC0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_GCR_Bits.ETC0 */
+#define IFX_PSI5_GCR_ETC0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_GCR_Bits.ETC0 */
+#define IFX_PSI5_GCR_ETC0_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_GCR_Bits.ETC1 */
+#define IFX_PSI5_GCR_ETC1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_GCR_Bits.ETC1 */
+#define IFX_PSI5_GCR_ETC1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_GCR_Bits.ETC1 */
+#define IFX_PSI5_GCR_ETC1_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_GCR_Bits.ETC2 */
+#define IFX_PSI5_GCR_ETC2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_GCR_Bits.ETC2 */
+#define IFX_PSI5_GCR_ETC2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_GCR_Bits.ETC2 */
+#define IFX_PSI5_GCR_ETC2_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_GCR_Bits.ETC3 */
+#define IFX_PSI5_GCR_ETC3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_GCR_Bits.ETC3 */
+#define IFX_PSI5_GCR_ETC3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_GCR_Bits.ETC3 */
+#define IFX_PSI5_GCR_ETC3_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_GCR_Bits.ETC4 */
+#define IFX_PSI5_GCR_ETC4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_GCR_Bits.ETC4 */
+#define IFX_PSI5_GCR_ETC4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_GCR_Bits.ETC4 */
+#define IFX_PSI5_GCR_ETC4_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_GCR_Bits.MEI */
+#define IFX_PSI5_GCR_MEI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_GCR_Bits.MEI */
+#define IFX_PSI5_GCR_MEI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_GCR_Bits.MEI */
+#define IFX_PSI5_GCR_MEI_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_GCR_Bits.NBI */
+#define IFX_PSI5_GCR_NBI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_GCR_Bits.NBI */
+#define IFX_PSI5_GCR_NBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_GCR_Bits.NBI */
+#define IFX_PSI5_GCR_NBI_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_GCR_Bits.NFI */
+#define IFX_PSI5_GCR_NFI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_GCR_Bits.NFI */
+#define IFX_PSI5_GCR_NFI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_GCR_Bits.NFI */
+#define IFX_PSI5_GCR_NFI_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_GCR_Bits.TEI */
+#define IFX_PSI5_GCR_TEI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_GCR_Bits.TEI */
+#define IFX_PSI5_GCR_TEI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_GCR_Bits.TEI */
+#define IFX_PSI5_GCR_TEI_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_ID_Bits.MODNUMBER */
+#define IFX_PSI5_ID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_PSI5_ID_Bits.MODNUMBER */
+#define IFX_PSI5_ID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_PSI5_ID_Bits.MODNUMBER */
+#define IFX_PSI5_ID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_ID_Bits.MODREV */
+#define IFX_PSI5_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_PSI5_ID_Bits.MODREV */
+#define IFX_PSI5_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_PSI5_ID_Bits.MODREV */
+#define IFX_PSI5_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_ID_Bits.MODTYPE */
+#define IFX_PSI5_ID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_PSI5_ID_Bits.MODTYPE */
+#define IFX_PSI5_ID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_PSI5_ID_Bits.MODTYPE */
+#define IFX_PSI5_ID_MODTYPE_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_INP_Bits.ERRI */
+#define IFX_PSI5_INP_ERRI_LEN (4u)
+
+/** \brief Mask for Ifx_PSI5_INP_Bits.ERRI */
+#define IFX_PSI5_INP_ERRI_MSK (0xfu)
+
+/** \brief Offset for Ifx_PSI5_INP_Bits.ERRI */
+#define IFX_PSI5_INP_ERRI_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_INP_Bits.FWI */
+#define IFX_PSI5_INP_FWI_LEN (4u)
+
+/** \brief Mask for Ifx_PSI5_INP_Bits.FWI */
+#define IFX_PSI5_INP_FWI_MSK (0xfu)
+
+/** \brief Offset for Ifx_PSI5_INP_Bits.FWI */
+#define IFX_PSI5_INP_FWI_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_INP_Bits.RBI */
+#define IFX_PSI5_INP_RBI_LEN (4u)
+
+/** \brief Mask for Ifx_PSI5_INP_Bits.RBI */
+#define IFX_PSI5_INP_RBI_MSK (0xfu)
+
+/** \brief Offset for Ifx_PSI5_INP_Bits.RBI */
+#define IFX_PSI5_INP_RBI_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_INP_Bits.RDI */
+#define IFX_PSI5_INP_RDI_LEN (4u)
+
+/** \brief Mask for Ifx_PSI5_INP_Bits.RDI */
+#define IFX_PSI5_INP_RDI_MSK (0xfu)
+
+/** \brief Offset for Ifx_PSI5_INP_Bits.RDI */
+#define IFX_PSI5_INP_RDI_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_INP_Bits.RSI */
+#define IFX_PSI5_INP_RSI_LEN (4u)
+
+/** \brief Mask for Ifx_PSI5_INP_Bits.RSI */
+#define IFX_PSI5_INP_RSI_MSK (0xfu)
+
+/** \brief Offset for Ifx_PSI5_INP_Bits.RSI */
+#define IFX_PSI5_INP_RSI_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_INP_Bits.SDI */
+#define IFX_PSI5_INP_SDI_LEN (4u)
+
+/** \brief Mask for Ifx_PSI5_INP_Bits.SDI */
+#define IFX_PSI5_INP_SDI_MSK (0xfu)
+
+/** \brief Offset for Ifx_PSI5_INP_Bits.SDI */
+#define IFX_PSI5_INP_SDI_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_INP_Bits.TBI */
+#define IFX_PSI5_INP_TBI_LEN (4u)
+
+/** \brief Mask for Ifx_PSI5_INP_Bits.TBI */
+#define IFX_PSI5_INP_TBI_MSK (0xfu)
+
+/** \brief Offset for Ifx_PSI5_INP_Bits.TBI */
+#define IFX_PSI5_INP_TBI_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_INP_Bits.TDI */
+#define IFX_PSI5_INP_TDI_LEN (4u)
+
+/** \brief Mask for Ifx_PSI5_INP_Bits.TDI */
+#define IFX_PSI5_INP_TDI_MSK (0xfu)
+
+/** \brief Offset for Ifx_PSI5_INP_Bits.TDI */
+#define IFX_PSI5_INP_TDI_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_INTCLRA_Bits.CRCI */
+#define IFX_PSI5_INTCLRA_CRCI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRA_Bits.CRCI */
+#define IFX_PSI5_INTCLRA_CRCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRA_Bits.CRCI */
+#define IFX_PSI5_INTCLRA_CRCI_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_INTCLRA_Bits.FWI */
+#define IFX_PSI5_INTCLRA_FWI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRA_Bits.FWI */
+#define IFX_PSI5_INTCLRA_FWI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRA_Bits.FWI */
+#define IFX_PSI5_INTCLRA_FWI_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_INTCLRA_Bits.MEI */
+#define IFX_PSI5_INTCLRA_MEI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRA_Bits.MEI */
+#define IFX_PSI5_INTCLRA_MEI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRA_Bits.MEI */
+#define IFX_PSI5_INTCLRA_MEI_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_INTCLRA_Bits.NBI */
+#define IFX_PSI5_INTCLRA_NBI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRA_Bits.NBI */
+#define IFX_PSI5_INTCLRA_NBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRA_Bits.NBI */
+#define IFX_PSI5_INTCLRA_NBI_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_INTCLRA_Bits.NFI */
+#define IFX_PSI5_INTCLRA_NFI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRA_Bits.NFI */
+#define IFX_PSI5_INTCLRA_NFI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRA_Bits.NFI */
+#define IFX_PSI5_INTCLRA_NFI_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_INTCLRA_Bits.RBI */
+#define IFX_PSI5_INTCLRA_RBI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRA_Bits.RBI */
+#define IFX_PSI5_INTCLRA_RBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRA_Bits.RBI */
+#define IFX_PSI5_INTCLRA_RBI_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_INTCLRA_Bits.RDI */
+#define IFX_PSI5_INTCLRA_RDI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRA_Bits.RDI */
+#define IFX_PSI5_INTCLRA_RDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRA_Bits.RDI */
+#define IFX_PSI5_INTCLRA_RDI_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_INTCLRA_Bits.RMI */
+#define IFX_PSI5_INTCLRA_RMI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRA_Bits.RMI */
+#define IFX_PSI5_INTCLRA_RMI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRA_Bits.RMI */
+#define IFX_PSI5_INTCLRA_RMI_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_INTCLRA_Bits.RSI */
+#define IFX_PSI5_INTCLRA_RSI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRA_Bits.RSI */
+#define IFX_PSI5_INTCLRA_RSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRA_Bits.RSI */
+#define IFX_PSI5_INTCLRA_RSI_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_INTCLRA_Bits.RUI */
+#define IFX_PSI5_INTCLRA_RUI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRA_Bits.RUI */
+#define IFX_PSI5_INTCLRA_RUI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRA_Bits.RUI */
+#define IFX_PSI5_INTCLRA_RUI_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_INTCLRA_Bits.TEI */
+#define IFX_PSI5_INTCLRA_TEI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRA_Bits.TEI */
+#define IFX_PSI5_INTCLRA_TEI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRA_Bits.TEI */
+#define IFX_PSI5_INTCLRA_TEI_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_INTCLRA_Bits.TOI */
+#define IFX_PSI5_INTCLRA_TOI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRA_Bits.TOI */
+#define IFX_PSI5_INTCLRA_TOI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRA_Bits.TOI */
+#define IFX_PSI5_INTCLRA_TOI_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_INTCLRA_Bits.TOOI */
+#define IFX_PSI5_INTCLRA_TOOI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRA_Bits.TOOI */
+#define IFX_PSI5_INTCLRA_TOOI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRA_Bits.TOOI */
+#define IFX_PSI5_INTCLRA_TOOI_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_INTCLRA_Bits.TPI */
+#define IFX_PSI5_INTCLRA_TPI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRA_Bits.TPI */
+#define IFX_PSI5_INTCLRA_TPI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRA_Bits.TPI */
+#define IFX_PSI5_INTCLRA_TPI_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_INTCLRA_Bits.TPOI */
+#define IFX_PSI5_INTCLRA_TPOI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRA_Bits.TPOI */
+#define IFX_PSI5_INTCLRA_TPOI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRA_Bits.TPOI */
+#define IFX_PSI5_INTCLRA_TPOI_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_INTCLRA_Bits.TSI */
+#define IFX_PSI5_INTCLRA_TSI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRA_Bits.TSI */
+#define IFX_PSI5_INTCLRA_TSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRA_Bits.TSI */
+#define IFX_PSI5_INTCLRA_TSI_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_INTCLRA_Bits.TSOI */
+#define IFX_PSI5_INTCLRA_TSOI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRA_Bits.TSOI */
+#define IFX_PSI5_INTCLRA_TSOI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRA_Bits.TSOI */
+#define IFX_PSI5_INTCLRA_TSOI_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_INTCLRB_Bits.SCRI0 */
+#define IFX_PSI5_INTCLRB_SCRI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRB_Bits.SCRI0 */
+#define IFX_PSI5_INTCLRB_SCRI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRB_Bits.SCRI0 */
+#define IFX_PSI5_INTCLRB_SCRI0_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_INTCLRB_Bits.SCRI1 */
+#define IFX_PSI5_INTCLRB_SCRI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRB_Bits.SCRI1 */
+#define IFX_PSI5_INTCLRB_SCRI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRB_Bits.SCRI1 */
+#define IFX_PSI5_INTCLRB_SCRI1_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_INTCLRB_Bits.SCRI2 */
+#define IFX_PSI5_INTCLRB_SCRI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRB_Bits.SCRI2 */
+#define IFX_PSI5_INTCLRB_SCRI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRB_Bits.SCRI2 */
+#define IFX_PSI5_INTCLRB_SCRI2_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_INTCLRB_Bits.SCRI3 */
+#define IFX_PSI5_INTCLRB_SCRI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRB_Bits.SCRI3 */
+#define IFX_PSI5_INTCLRB_SCRI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRB_Bits.SCRI3 */
+#define IFX_PSI5_INTCLRB_SCRI3_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_INTCLRB_Bits.SCRI4 */
+#define IFX_PSI5_INTCLRB_SCRI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRB_Bits.SCRI4 */
+#define IFX_PSI5_INTCLRB_SCRI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRB_Bits.SCRI4 */
+#define IFX_PSI5_INTCLRB_SCRI4_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_INTCLRB_Bits.SCRI5 */
+#define IFX_PSI5_INTCLRB_SCRI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRB_Bits.SCRI5 */
+#define IFX_PSI5_INTCLRB_SCRI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRB_Bits.SCRI5 */
+#define IFX_PSI5_INTCLRB_SCRI5_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_INTCLRB_Bits.SDI0 */
+#define IFX_PSI5_INTCLRB_SDI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRB_Bits.SDI0 */
+#define IFX_PSI5_INTCLRB_SDI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRB_Bits.SDI0 */
+#define IFX_PSI5_INTCLRB_SDI0_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_INTCLRB_Bits.SDI1 */
+#define IFX_PSI5_INTCLRB_SDI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRB_Bits.SDI1 */
+#define IFX_PSI5_INTCLRB_SDI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRB_Bits.SDI1 */
+#define IFX_PSI5_INTCLRB_SDI1_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_INTCLRB_Bits.SDI2 */
+#define IFX_PSI5_INTCLRB_SDI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRB_Bits.SDI2 */
+#define IFX_PSI5_INTCLRB_SDI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRB_Bits.SDI2 */
+#define IFX_PSI5_INTCLRB_SDI2_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_INTCLRB_Bits.SDI3 */
+#define IFX_PSI5_INTCLRB_SDI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRB_Bits.SDI3 */
+#define IFX_PSI5_INTCLRB_SDI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRB_Bits.SDI3 */
+#define IFX_PSI5_INTCLRB_SDI3_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_INTCLRB_Bits.SDI4 */
+#define IFX_PSI5_INTCLRB_SDI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRB_Bits.SDI4 */
+#define IFX_PSI5_INTCLRB_SDI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRB_Bits.SDI4 */
+#define IFX_PSI5_INTCLRB_SDI4_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_INTCLRB_Bits.SDI5 */
+#define IFX_PSI5_INTCLRB_SDI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRB_Bits.SDI5 */
+#define IFX_PSI5_INTCLRB_SDI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRB_Bits.SDI5 */
+#define IFX_PSI5_INTCLRB_SDI5_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_INTCLRB_Bits.SOI0 */
+#define IFX_PSI5_INTCLRB_SOI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRB_Bits.SOI0 */
+#define IFX_PSI5_INTCLRB_SOI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRB_Bits.SOI0 */
+#define IFX_PSI5_INTCLRB_SOI0_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_INTCLRB_Bits.SOI1 */
+#define IFX_PSI5_INTCLRB_SOI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRB_Bits.SOI1 */
+#define IFX_PSI5_INTCLRB_SOI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRB_Bits.SOI1 */
+#define IFX_PSI5_INTCLRB_SOI1_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_INTCLRB_Bits.SOI2 */
+#define IFX_PSI5_INTCLRB_SOI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRB_Bits.SOI2 */
+#define IFX_PSI5_INTCLRB_SOI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRB_Bits.SOI2 */
+#define IFX_PSI5_INTCLRB_SOI2_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_INTCLRB_Bits.SOI3 */
+#define IFX_PSI5_INTCLRB_SOI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRB_Bits.SOI3 */
+#define IFX_PSI5_INTCLRB_SOI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRB_Bits.SOI3 */
+#define IFX_PSI5_INTCLRB_SOI3_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_INTCLRB_Bits.SOI4 */
+#define IFX_PSI5_INTCLRB_SOI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRB_Bits.SOI4 */
+#define IFX_PSI5_INTCLRB_SOI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRB_Bits.SOI4 */
+#define IFX_PSI5_INTCLRB_SOI4_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_INTCLRB_Bits.SOI5 */
+#define IFX_PSI5_INTCLRB_SOI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRB_Bits.SOI5 */
+#define IFX_PSI5_INTCLRB_SOI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRB_Bits.SOI5 */
+#define IFX_PSI5_INTCLRB_SOI5_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_INTCLRB_Bits.WSI0 */
+#define IFX_PSI5_INTCLRB_WSI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRB_Bits.WSI0 */
+#define IFX_PSI5_INTCLRB_WSI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRB_Bits.WSI0 */
+#define IFX_PSI5_INTCLRB_WSI0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_INTCLRB_Bits.WSI1 */
+#define IFX_PSI5_INTCLRB_WSI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRB_Bits.WSI1 */
+#define IFX_PSI5_INTCLRB_WSI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRB_Bits.WSI1 */
+#define IFX_PSI5_INTCLRB_WSI1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_INTCLRB_Bits.WSI2 */
+#define IFX_PSI5_INTCLRB_WSI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRB_Bits.WSI2 */
+#define IFX_PSI5_INTCLRB_WSI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRB_Bits.WSI2 */
+#define IFX_PSI5_INTCLRB_WSI2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_INTCLRB_Bits.WSI3 */
+#define IFX_PSI5_INTCLRB_WSI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRB_Bits.WSI3 */
+#define IFX_PSI5_INTCLRB_WSI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRB_Bits.WSI3 */
+#define IFX_PSI5_INTCLRB_WSI3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_INTCLRB_Bits.WSI4 */
+#define IFX_PSI5_INTCLRB_WSI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRB_Bits.WSI4 */
+#define IFX_PSI5_INTCLRB_WSI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRB_Bits.WSI4 */
+#define IFX_PSI5_INTCLRB_WSI4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_INTCLRB_Bits.WSI5 */
+#define IFX_PSI5_INTCLRB_WSI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTCLRB_Bits.WSI5 */
+#define IFX_PSI5_INTCLRB_WSI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTCLRB_Bits.WSI5 */
+#define IFX_PSI5_INTCLRB_WSI5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_INTENA_Bits.CRCI */
+#define IFX_PSI5_INTENA_CRCI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENA_Bits.CRCI */
+#define IFX_PSI5_INTENA_CRCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENA_Bits.CRCI */
+#define IFX_PSI5_INTENA_CRCI_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_INTENA_Bits.FWI */
+#define IFX_PSI5_INTENA_FWI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENA_Bits.FWI */
+#define IFX_PSI5_INTENA_FWI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENA_Bits.FWI */
+#define IFX_PSI5_INTENA_FWI_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_INTENA_Bits.MEI */
+#define IFX_PSI5_INTENA_MEI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENA_Bits.MEI */
+#define IFX_PSI5_INTENA_MEI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENA_Bits.MEI */
+#define IFX_PSI5_INTENA_MEI_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_INTENA_Bits.NBI */
+#define IFX_PSI5_INTENA_NBI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENA_Bits.NBI */
+#define IFX_PSI5_INTENA_NBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENA_Bits.NBI */
+#define IFX_PSI5_INTENA_NBI_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_INTENA_Bits.NFI */
+#define IFX_PSI5_INTENA_NFI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENA_Bits.NFI */
+#define IFX_PSI5_INTENA_NFI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENA_Bits.NFI */
+#define IFX_PSI5_INTENA_NFI_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_INTENA_Bits.RBI */
+#define IFX_PSI5_INTENA_RBI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENA_Bits.RBI */
+#define IFX_PSI5_INTENA_RBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENA_Bits.RBI */
+#define IFX_PSI5_INTENA_RBI_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_INTENA_Bits.RDI */
+#define IFX_PSI5_INTENA_RDI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENA_Bits.RDI */
+#define IFX_PSI5_INTENA_RDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENA_Bits.RDI */
+#define IFX_PSI5_INTENA_RDI_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_INTENA_Bits.RMI */
+#define IFX_PSI5_INTENA_RMI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENA_Bits.RMI */
+#define IFX_PSI5_INTENA_RMI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENA_Bits.RMI */
+#define IFX_PSI5_INTENA_RMI_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_INTENA_Bits.RSI */
+#define IFX_PSI5_INTENA_RSI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENA_Bits.RSI */
+#define IFX_PSI5_INTENA_RSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENA_Bits.RSI */
+#define IFX_PSI5_INTENA_RSI_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_INTENA_Bits.RUI */
+#define IFX_PSI5_INTENA_RUI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENA_Bits.RUI */
+#define IFX_PSI5_INTENA_RUI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENA_Bits.RUI */
+#define IFX_PSI5_INTENA_RUI_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_INTENA_Bits.TEI */
+#define IFX_PSI5_INTENA_TEI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENA_Bits.TEI */
+#define IFX_PSI5_INTENA_TEI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENA_Bits.TEI */
+#define IFX_PSI5_INTENA_TEI_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_INTENA_Bits.TOI */
+#define IFX_PSI5_INTENA_TOI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENA_Bits.TOI */
+#define IFX_PSI5_INTENA_TOI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENA_Bits.TOI */
+#define IFX_PSI5_INTENA_TOI_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_INTENA_Bits.TOOI */
+#define IFX_PSI5_INTENA_TOOI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENA_Bits.TOOI */
+#define IFX_PSI5_INTENA_TOOI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENA_Bits.TOOI */
+#define IFX_PSI5_INTENA_TOOI_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_INTENA_Bits.TPI */
+#define IFX_PSI5_INTENA_TPI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENA_Bits.TPI */
+#define IFX_PSI5_INTENA_TPI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENA_Bits.TPI */
+#define IFX_PSI5_INTENA_TPI_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_INTENA_Bits.TPOI */
+#define IFX_PSI5_INTENA_TPOI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENA_Bits.TPOI */
+#define IFX_PSI5_INTENA_TPOI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENA_Bits.TPOI */
+#define IFX_PSI5_INTENA_TPOI_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_INTENA_Bits.TSI */
+#define IFX_PSI5_INTENA_TSI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENA_Bits.TSI */
+#define IFX_PSI5_INTENA_TSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENA_Bits.TSI */
+#define IFX_PSI5_INTENA_TSI_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_INTENA_Bits.TSOI */
+#define IFX_PSI5_INTENA_TSOI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENA_Bits.TSOI */
+#define IFX_PSI5_INTENA_TSOI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENA_Bits.TSOI */
+#define IFX_PSI5_INTENA_TSOI_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_INTENB_Bits.SCRI0 */
+#define IFX_PSI5_INTENB_SCRI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENB_Bits.SCRI0 */
+#define IFX_PSI5_INTENB_SCRI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENB_Bits.SCRI0 */
+#define IFX_PSI5_INTENB_SCRI0_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_INTENB_Bits.SCRI1 */
+#define IFX_PSI5_INTENB_SCRI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENB_Bits.SCRI1 */
+#define IFX_PSI5_INTENB_SCRI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENB_Bits.SCRI1 */
+#define IFX_PSI5_INTENB_SCRI1_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_INTENB_Bits.SCRI2 */
+#define IFX_PSI5_INTENB_SCRI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENB_Bits.SCRI2 */
+#define IFX_PSI5_INTENB_SCRI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENB_Bits.SCRI2 */
+#define IFX_PSI5_INTENB_SCRI2_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_INTENB_Bits.SCRI3 */
+#define IFX_PSI5_INTENB_SCRI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENB_Bits.SCRI3 */
+#define IFX_PSI5_INTENB_SCRI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENB_Bits.SCRI3 */
+#define IFX_PSI5_INTENB_SCRI3_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_INTENB_Bits.SCRI4 */
+#define IFX_PSI5_INTENB_SCRI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENB_Bits.SCRI4 */
+#define IFX_PSI5_INTENB_SCRI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENB_Bits.SCRI4 */
+#define IFX_PSI5_INTENB_SCRI4_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_INTENB_Bits.SCRI5 */
+#define IFX_PSI5_INTENB_SCRI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENB_Bits.SCRI5 */
+#define IFX_PSI5_INTENB_SCRI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENB_Bits.SCRI5 */
+#define IFX_PSI5_INTENB_SCRI5_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_INTENB_Bits.SDI0 */
+#define IFX_PSI5_INTENB_SDI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENB_Bits.SDI0 */
+#define IFX_PSI5_INTENB_SDI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENB_Bits.SDI0 */
+#define IFX_PSI5_INTENB_SDI0_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_INTENB_Bits.SDI1 */
+#define IFX_PSI5_INTENB_SDI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENB_Bits.SDI1 */
+#define IFX_PSI5_INTENB_SDI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENB_Bits.SDI1 */
+#define IFX_PSI5_INTENB_SDI1_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_INTENB_Bits.SDI2 */
+#define IFX_PSI5_INTENB_SDI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENB_Bits.SDI2 */
+#define IFX_PSI5_INTENB_SDI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENB_Bits.SDI2 */
+#define IFX_PSI5_INTENB_SDI2_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_INTENB_Bits.SDI3 */
+#define IFX_PSI5_INTENB_SDI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENB_Bits.SDI3 */
+#define IFX_PSI5_INTENB_SDI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENB_Bits.SDI3 */
+#define IFX_PSI5_INTENB_SDI3_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_INTENB_Bits.SDI4 */
+#define IFX_PSI5_INTENB_SDI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENB_Bits.SDI4 */
+#define IFX_PSI5_INTENB_SDI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENB_Bits.SDI4 */
+#define IFX_PSI5_INTENB_SDI4_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_INTENB_Bits.SDI5 */
+#define IFX_PSI5_INTENB_SDI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENB_Bits.SDI5 */
+#define IFX_PSI5_INTENB_SDI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENB_Bits.SDI5 */
+#define IFX_PSI5_INTENB_SDI5_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_INTENB_Bits.SOI0 */
+#define IFX_PSI5_INTENB_SOI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENB_Bits.SOI0 */
+#define IFX_PSI5_INTENB_SOI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENB_Bits.SOI0 */
+#define IFX_PSI5_INTENB_SOI0_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_INTENB_Bits.SOI1 */
+#define IFX_PSI5_INTENB_SOI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENB_Bits.SOI1 */
+#define IFX_PSI5_INTENB_SOI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENB_Bits.SOI1 */
+#define IFX_PSI5_INTENB_SOI1_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_INTENB_Bits.SOI2 */
+#define IFX_PSI5_INTENB_SOI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENB_Bits.SOI2 */
+#define IFX_PSI5_INTENB_SOI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENB_Bits.SOI2 */
+#define IFX_PSI5_INTENB_SOI2_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_INTENB_Bits.SOI3 */
+#define IFX_PSI5_INTENB_SOI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENB_Bits.SOI3 */
+#define IFX_PSI5_INTENB_SOI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENB_Bits.SOI3 */
+#define IFX_PSI5_INTENB_SOI3_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_INTENB_Bits.SOI4 */
+#define IFX_PSI5_INTENB_SOI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENB_Bits.SOI4 */
+#define IFX_PSI5_INTENB_SOI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENB_Bits.SOI4 */
+#define IFX_PSI5_INTENB_SOI4_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_INTENB_Bits.SOI5 */
+#define IFX_PSI5_INTENB_SOI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENB_Bits.SOI5 */
+#define IFX_PSI5_INTENB_SOI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENB_Bits.SOI5 */
+#define IFX_PSI5_INTENB_SOI5_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_INTENB_Bits.WSI0 */
+#define IFX_PSI5_INTENB_WSI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENB_Bits.WSI0 */
+#define IFX_PSI5_INTENB_WSI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENB_Bits.WSI0 */
+#define IFX_PSI5_INTENB_WSI0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_INTENB_Bits.WSI1 */
+#define IFX_PSI5_INTENB_WSI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENB_Bits.WSI1 */
+#define IFX_PSI5_INTENB_WSI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENB_Bits.WSI1 */
+#define IFX_PSI5_INTENB_WSI1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_INTENB_Bits.WSI2 */
+#define IFX_PSI5_INTENB_WSI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENB_Bits.WSI2 */
+#define IFX_PSI5_INTENB_WSI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENB_Bits.WSI2 */
+#define IFX_PSI5_INTENB_WSI2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_INTENB_Bits.WSI3 */
+#define IFX_PSI5_INTENB_WSI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENB_Bits.WSI3 */
+#define IFX_PSI5_INTENB_WSI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENB_Bits.WSI3 */
+#define IFX_PSI5_INTENB_WSI3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_INTENB_Bits.WSI4 */
+#define IFX_PSI5_INTENB_WSI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENB_Bits.WSI4 */
+#define IFX_PSI5_INTENB_WSI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENB_Bits.WSI4 */
+#define IFX_PSI5_INTENB_WSI4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_INTENB_Bits.WSI5 */
+#define IFX_PSI5_INTENB_WSI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTENB_Bits.WSI5 */
+#define IFX_PSI5_INTENB_WSI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTENB_Bits.WSI5 */
+#define IFX_PSI5_INTENB_WSI5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_INTOV_Bits.ERRI */
+#define IFX_PSI5_INTOV_ERRI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTOV_Bits.ERRI */
+#define IFX_PSI5_INTOV_ERRI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTOV_Bits.ERRI */
+#define IFX_PSI5_INTOV_ERRI_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_INTOV_Bits.FWI */
+#define IFX_PSI5_INTOV_FWI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTOV_Bits.FWI */
+#define IFX_PSI5_INTOV_FWI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTOV_Bits.FWI */
+#define IFX_PSI5_INTOV_FWI_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_INTOV_Bits.RBI */
+#define IFX_PSI5_INTOV_RBI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTOV_Bits.RBI */
+#define IFX_PSI5_INTOV_RBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTOV_Bits.RBI */
+#define IFX_PSI5_INTOV_RBI_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_INTOV_Bits.RDI */
+#define IFX_PSI5_INTOV_RDI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTOV_Bits.RDI */
+#define IFX_PSI5_INTOV_RDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTOV_Bits.RDI */
+#define IFX_PSI5_INTOV_RDI_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_INTOV_Bits.RSI */
+#define IFX_PSI5_INTOV_RSI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTOV_Bits.RSI */
+#define IFX_PSI5_INTOV_RSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTOV_Bits.RSI */
+#define IFX_PSI5_INTOV_RSI_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_INTOV_Bits.SDI */
+#define IFX_PSI5_INTOV_SDI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTOV_Bits.SDI */
+#define IFX_PSI5_INTOV_SDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTOV_Bits.SDI */
+#define IFX_PSI5_INTOV_SDI_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_INTOV_Bits.TBI */
+#define IFX_PSI5_INTOV_TBI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTOV_Bits.TBI */
+#define IFX_PSI5_INTOV_TBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTOV_Bits.TBI */
+#define IFX_PSI5_INTOV_TBI_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_INTOV_Bits.TDI */
+#define IFX_PSI5_INTOV_TDI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTOV_Bits.TDI */
+#define IFX_PSI5_INTOV_TDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTOV_Bits.TDI */
+#define IFX_PSI5_INTOV_TDI_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_INTSETA_Bits.CRCI */
+#define IFX_PSI5_INTSETA_CRCI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETA_Bits.CRCI */
+#define IFX_PSI5_INTSETA_CRCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETA_Bits.CRCI */
+#define IFX_PSI5_INTSETA_CRCI_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_INTSETA_Bits.FWI */
+#define IFX_PSI5_INTSETA_FWI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETA_Bits.FWI */
+#define IFX_PSI5_INTSETA_FWI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETA_Bits.FWI */
+#define IFX_PSI5_INTSETA_FWI_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_INTSETA_Bits.MEI */
+#define IFX_PSI5_INTSETA_MEI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETA_Bits.MEI */
+#define IFX_PSI5_INTSETA_MEI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETA_Bits.MEI */
+#define IFX_PSI5_INTSETA_MEI_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_INTSETA_Bits.NBI */
+#define IFX_PSI5_INTSETA_NBI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETA_Bits.NBI */
+#define IFX_PSI5_INTSETA_NBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETA_Bits.NBI */
+#define IFX_PSI5_INTSETA_NBI_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_INTSETA_Bits.NFI */
+#define IFX_PSI5_INTSETA_NFI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETA_Bits.NFI */
+#define IFX_PSI5_INTSETA_NFI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETA_Bits.NFI */
+#define IFX_PSI5_INTSETA_NFI_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_INTSETA_Bits.RBI */
+#define IFX_PSI5_INTSETA_RBI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETA_Bits.RBI */
+#define IFX_PSI5_INTSETA_RBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETA_Bits.RBI */
+#define IFX_PSI5_INTSETA_RBI_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_INTSETA_Bits.RDI */
+#define IFX_PSI5_INTSETA_RDI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETA_Bits.RDI */
+#define IFX_PSI5_INTSETA_RDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETA_Bits.RDI */
+#define IFX_PSI5_INTSETA_RDI_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_INTSETA_Bits.RMI */
+#define IFX_PSI5_INTSETA_RMI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETA_Bits.RMI */
+#define IFX_PSI5_INTSETA_RMI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETA_Bits.RMI */
+#define IFX_PSI5_INTSETA_RMI_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_INTSETA_Bits.RSI */
+#define IFX_PSI5_INTSETA_RSI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETA_Bits.RSI */
+#define IFX_PSI5_INTSETA_RSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETA_Bits.RSI */
+#define IFX_PSI5_INTSETA_RSI_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_INTSETA_Bits.RUI */
+#define IFX_PSI5_INTSETA_RUI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETA_Bits.RUI */
+#define IFX_PSI5_INTSETA_RUI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETA_Bits.RUI */
+#define IFX_PSI5_INTSETA_RUI_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_INTSETA_Bits.TEI */
+#define IFX_PSI5_INTSETA_TEI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETA_Bits.TEI */
+#define IFX_PSI5_INTSETA_TEI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETA_Bits.TEI */
+#define IFX_PSI5_INTSETA_TEI_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_INTSETA_Bits.TOI */
+#define IFX_PSI5_INTSETA_TOI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETA_Bits.TOI */
+#define IFX_PSI5_INTSETA_TOI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETA_Bits.TOI */
+#define IFX_PSI5_INTSETA_TOI_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_INTSETA_Bits.TOOI */
+#define IFX_PSI5_INTSETA_TOOI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETA_Bits.TOOI */
+#define IFX_PSI5_INTSETA_TOOI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETA_Bits.TOOI */
+#define IFX_PSI5_INTSETA_TOOI_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_INTSETA_Bits.TPI */
+#define IFX_PSI5_INTSETA_TPI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETA_Bits.TPI */
+#define IFX_PSI5_INTSETA_TPI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETA_Bits.TPI */
+#define IFX_PSI5_INTSETA_TPI_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_INTSETA_Bits.TPOI */
+#define IFX_PSI5_INTSETA_TPOI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETA_Bits.TPOI */
+#define IFX_PSI5_INTSETA_TPOI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETA_Bits.TPOI */
+#define IFX_PSI5_INTSETA_TPOI_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_INTSETA_Bits.TSI */
+#define IFX_PSI5_INTSETA_TSI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETA_Bits.TSI */
+#define IFX_PSI5_INTSETA_TSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETA_Bits.TSI */
+#define IFX_PSI5_INTSETA_TSI_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_INTSETA_Bits.TSOI */
+#define IFX_PSI5_INTSETA_TSOI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETA_Bits.TSOI */
+#define IFX_PSI5_INTSETA_TSOI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETA_Bits.TSOI */
+#define IFX_PSI5_INTSETA_TSOI_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_INTSETB_Bits.SCRI0 */
+#define IFX_PSI5_INTSETB_SCRI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETB_Bits.SCRI0 */
+#define IFX_PSI5_INTSETB_SCRI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETB_Bits.SCRI0 */
+#define IFX_PSI5_INTSETB_SCRI0_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_INTSETB_Bits.SCRI1 */
+#define IFX_PSI5_INTSETB_SCRI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETB_Bits.SCRI1 */
+#define IFX_PSI5_INTSETB_SCRI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETB_Bits.SCRI1 */
+#define IFX_PSI5_INTSETB_SCRI1_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_INTSETB_Bits.SCRI2 */
+#define IFX_PSI5_INTSETB_SCRI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETB_Bits.SCRI2 */
+#define IFX_PSI5_INTSETB_SCRI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETB_Bits.SCRI2 */
+#define IFX_PSI5_INTSETB_SCRI2_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_INTSETB_Bits.SCRI3 */
+#define IFX_PSI5_INTSETB_SCRI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETB_Bits.SCRI3 */
+#define IFX_PSI5_INTSETB_SCRI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETB_Bits.SCRI3 */
+#define IFX_PSI5_INTSETB_SCRI3_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_INTSETB_Bits.SCRI4 */
+#define IFX_PSI5_INTSETB_SCRI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETB_Bits.SCRI4 */
+#define IFX_PSI5_INTSETB_SCRI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETB_Bits.SCRI4 */
+#define IFX_PSI5_INTSETB_SCRI4_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_INTSETB_Bits.SCRI5 */
+#define IFX_PSI5_INTSETB_SCRI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETB_Bits.SCRI5 */
+#define IFX_PSI5_INTSETB_SCRI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETB_Bits.SCRI5 */
+#define IFX_PSI5_INTSETB_SCRI5_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_INTSETB_Bits.SDI0 */
+#define IFX_PSI5_INTSETB_SDI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETB_Bits.SDI0 */
+#define IFX_PSI5_INTSETB_SDI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETB_Bits.SDI0 */
+#define IFX_PSI5_INTSETB_SDI0_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_INTSETB_Bits.SDI1 */
+#define IFX_PSI5_INTSETB_SDI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETB_Bits.SDI1 */
+#define IFX_PSI5_INTSETB_SDI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETB_Bits.SDI1 */
+#define IFX_PSI5_INTSETB_SDI1_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_INTSETB_Bits.SDI2 */
+#define IFX_PSI5_INTSETB_SDI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETB_Bits.SDI2 */
+#define IFX_PSI5_INTSETB_SDI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETB_Bits.SDI2 */
+#define IFX_PSI5_INTSETB_SDI2_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_INTSETB_Bits.SDI3 */
+#define IFX_PSI5_INTSETB_SDI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETB_Bits.SDI3 */
+#define IFX_PSI5_INTSETB_SDI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETB_Bits.SDI3 */
+#define IFX_PSI5_INTSETB_SDI3_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_INTSETB_Bits.SDI4 */
+#define IFX_PSI5_INTSETB_SDI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETB_Bits.SDI4 */
+#define IFX_PSI5_INTSETB_SDI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETB_Bits.SDI4 */
+#define IFX_PSI5_INTSETB_SDI4_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_INTSETB_Bits.SDI5 */
+#define IFX_PSI5_INTSETB_SDI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETB_Bits.SDI5 */
+#define IFX_PSI5_INTSETB_SDI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETB_Bits.SDI5 */
+#define IFX_PSI5_INTSETB_SDI5_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_INTSETB_Bits.SOI0 */
+#define IFX_PSI5_INTSETB_SOI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETB_Bits.SOI0 */
+#define IFX_PSI5_INTSETB_SOI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETB_Bits.SOI0 */
+#define IFX_PSI5_INTSETB_SOI0_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_INTSETB_Bits.SOI1 */
+#define IFX_PSI5_INTSETB_SOI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETB_Bits.SOI1 */
+#define IFX_PSI5_INTSETB_SOI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETB_Bits.SOI1 */
+#define IFX_PSI5_INTSETB_SOI1_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_INTSETB_Bits.SOI2 */
+#define IFX_PSI5_INTSETB_SOI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETB_Bits.SOI2 */
+#define IFX_PSI5_INTSETB_SOI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETB_Bits.SOI2 */
+#define IFX_PSI5_INTSETB_SOI2_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_INTSETB_Bits.SOI3 */
+#define IFX_PSI5_INTSETB_SOI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETB_Bits.SOI3 */
+#define IFX_PSI5_INTSETB_SOI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETB_Bits.SOI3 */
+#define IFX_PSI5_INTSETB_SOI3_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_INTSETB_Bits.SOI4 */
+#define IFX_PSI5_INTSETB_SOI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETB_Bits.SOI4 */
+#define IFX_PSI5_INTSETB_SOI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETB_Bits.SOI4 */
+#define IFX_PSI5_INTSETB_SOI4_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_INTSETB_Bits.SOI5 */
+#define IFX_PSI5_INTSETB_SOI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETB_Bits.SOI5 */
+#define IFX_PSI5_INTSETB_SOI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETB_Bits.SOI5 */
+#define IFX_PSI5_INTSETB_SOI5_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_INTSETB_Bits.WSI0 */
+#define IFX_PSI5_INTSETB_WSI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETB_Bits.WSI0 */
+#define IFX_PSI5_INTSETB_WSI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETB_Bits.WSI0 */
+#define IFX_PSI5_INTSETB_WSI0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_INTSETB_Bits.WSI1 */
+#define IFX_PSI5_INTSETB_WSI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETB_Bits.WSI1 */
+#define IFX_PSI5_INTSETB_WSI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETB_Bits.WSI1 */
+#define IFX_PSI5_INTSETB_WSI1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_INTSETB_Bits.WSI2 */
+#define IFX_PSI5_INTSETB_WSI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETB_Bits.WSI2 */
+#define IFX_PSI5_INTSETB_WSI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETB_Bits.WSI2 */
+#define IFX_PSI5_INTSETB_WSI2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_INTSETB_Bits.WSI3 */
+#define IFX_PSI5_INTSETB_WSI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETB_Bits.WSI3 */
+#define IFX_PSI5_INTSETB_WSI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETB_Bits.WSI3 */
+#define IFX_PSI5_INTSETB_WSI3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_INTSETB_Bits.WSI4 */
+#define IFX_PSI5_INTSETB_WSI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETB_Bits.WSI4 */
+#define IFX_PSI5_INTSETB_WSI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETB_Bits.WSI4 */
+#define IFX_PSI5_INTSETB_WSI4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_INTSETB_Bits.WSI5 */
+#define IFX_PSI5_INTSETB_WSI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSETB_Bits.WSI5 */
+#define IFX_PSI5_INTSETB_WSI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSETB_Bits.WSI5 */
+#define IFX_PSI5_INTSETB_WSI5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_INTSTATA_Bits.CRCI */
+#define IFX_PSI5_INTSTATA_CRCI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATA_Bits.CRCI */
+#define IFX_PSI5_INTSTATA_CRCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATA_Bits.CRCI */
+#define IFX_PSI5_INTSTATA_CRCI_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_INTSTATA_Bits.FWI */
+#define IFX_PSI5_INTSTATA_FWI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATA_Bits.FWI */
+#define IFX_PSI5_INTSTATA_FWI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATA_Bits.FWI */
+#define IFX_PSI5_INTSTATA_FWI_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_INTSTATA_Bits.MEI */
+#define IFX_PSI5_INTSTATA_MEI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATA_Bits.MEI */
+#define IFX_PSI5_INTSTATA_MEI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATA_Bits.MEI */
+#define IFX_PSI5_INTSTATA_MEI_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_INTSTATA_Bits.NBI */
+#define IFX_PSI5_INTSTATA_NBI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATA_Bits.NBI */
+#define IFX_PSI5_INTSTATA_NBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATA_Bits.NBI */
+#define IFX_PSI5_INTSTATA_NBI_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_INTSTATA_Bits.NFI */
+#define IFX_PSI5_INTSTATA_NFI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATA_Bits.NFI */
+#define IFX_PSI5_INTSTATA_NFI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATA_Bits.NFI */
+#define IFX_PSI5_INTSTATA_NFI_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_INTSTATA_Bits.RBI */
+#define IFX_PSI5_INTSTATA_RBI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATA_Bits.RBI */
+#define IFX_PSI5_INTSTATA_RBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATA_Bits.RBI */
+#define IFX_PSI5_INTSTATA_RBI_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_INTSTATA_Bits.RDI */
+#define IFX_PSI5_INTSTATA_RDI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATA_Bits.RDI */
+#define IFX_PSI5_INTSTATA_RDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATA_Bits.RDI */
+#define IFX_PSI5_INTSTATA_RDI_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_INTSTATA_Bits.RMI */
+#define IFX_PSI5_INTSTATA_RMI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATA_Bits.RMI */
+#define IFX_PSI5_INTSTATA_RMI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATA_Bits.RMI */
+#define IFX_PSI5_INTSTATA_RMI_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_INTSTATA_Bits.RSI */
+#define IFX_PSI5_INTSTATA_RSI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATA_Bits.RSI */
+#define IFX_PSI5_INTSTATA_RSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATA_Bits.RSI */
+#define IFX_PSI5_INTSTATA_RSI_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_INTSTATA_Bits.RUI */
+#define IFX_PSI5_INTSTATA_RUI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATA_Bits.RUI */
+#define IFX_PSI5_INTSTATA_RUI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATA_Bits.RUI */
+#define IFX_PSI5_INTSTATA_RUI_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_INTSTATA_Bits.TEI */
+#define IFX_PSI5_INTSTATA_TEI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATA_Bits.TEI */
+#define IFX_PSI5_INTSTATA_TEI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATA_Bits.TEI */
+#define IFX_PSI5_INTSTATA_TEI_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_INTSTATA_Bits.TOI */
+#define IFX_PSI5_INTSTATA_TOI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATA_Bits.TOI */
+#define IFX_PSI5_INTSTATA_TOI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATA_Bits.TOI */
+#define IFX_PSI5_INTSTATA_TOI_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_INTSTATA_Bits.TOOI */
+#define IFX_PSI5_INTSTATA_TOOI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATA_Bits.TOOI */
+#define IFX_PSI5_INTSTATA_TOOI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATA_Bits.TOOI */
+#define IFX_PSI5_INTSTATA_TOOI_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_INTSTATA_Bits.TPI */
+#define IFX_PSI5_INTSTATA_TPI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATA_Bits.TPI */
+#define IFX_PSI5_INTSTATA_TPI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATA_Bits.TPI */
+#define IFX_PSI5_INTSTATA_TPI_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_INTSTATA_Bits.TPOI */
+#define IFX_PSI5_INTSTATA_TPOI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATA_Bits.TPOI */
+#define IFX_PSI5_INTSTATA_TPOI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATA_Bits.TPOI */
+#define IFX_PSI5_INTSTATA_TPOI_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_INTSTATA_Bits.TSI */
+#define IFX_PSI5_INTSTATA_TSI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATA_Bits.TSI */
+#define IFX_PSI5_INTSTATA_TSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATA_Bits.TSI */
+#define IFX_PSI5_INTSTATA_TSI_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_INTSTATA_Bits.TSOI */
+#define IFX_PSI5_INTSTATA_TSOI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATA_Bits.TSOI */
+#define IFX_PSI5_INTSTATA_TSOI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATA_Bits.TSOI */
+#define IFX_PSI5_INTSTATA_TSOI_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_INTSTATB_Bits.SCRI0 */
+#define IFX_PSI5_INTSTATB_SCRI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATB_Bits.SCRI0 */
+#define IFX_PSI5_INTSTATB_SCRI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATB_Bits.SCRI0 */
+#define IFX_PSI5_INTSTATB_SCRI0_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_INTSTATB_Bits.SCRI1 */
+#define IFX_PSI5_INTSTATB_SCRI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATB_Bits.SCRI1 */
+#define IFX_PSI5_INTSTATB_SCRI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATB_Bits.SCRI1 */
+#define IFX_PSI5_INTSTATB_SCRI1_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_INTSTATB_Bits.SCRI2 */
+#define IFX_PSI5_INTSTATB_SCRI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATB_Bits.SCRI2 */
+#define IFX_PSI5_INTSTATB_SCRI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATB_Bits.SCRI2 */
+#define IFX_PSI5_INTSTATB_SCRI2_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_INTSTATB_Bits.SCRI3 */
+#define IFX_PSI5_INTSTATB_SCRI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATB_Bits.SCRI3 */
+#define IFX_PSI5_INTSTATB_SCRI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATB_Bits.SCRI3 */
+#define IFX_PSI5_INTSTATB_SCRI3_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_INTSTATB_Bits.SCRI4 */
+#define IFX_PSI5_INTSTATB_SCRI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATB_Bits.SCRI4 */
+#define IFX_PSI5_INTSTATB_SCRI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATB_Bits.SCRI4 */
+#define IFX_PSI5_INTSTATB_SCRI4_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_INTSTATB_Bits.SCRI5 */
+#define IFX_PSI5_INTSTATB_SCRI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATB_Bits.SCRI5 */
+#define IFX_PSI5_INTSTATB_SCRI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATB_Bits.SCRI5 */
+#define IFX_PSI5_INTSTATB_SCRI5_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_INTSTATB_Bits.SDI0 */
+#define IFX_PSI5_INTSTATB_SDI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATB_Bits.SDI0 */
+#define IFX_PSI5_INTSTATB_SDI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATB_Bits.SDI0 */
+#define IFX_PSI5_INTSTATB_SDI0_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_INTSTATB_Bits.SDI1 */
+#define IFX_PSI5_INTSTATB_SDI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATB_Bits.SDI1 */
+#define IFX_PSI5_INTSTATB_SDI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATB_Bits.SDI1 */
+#define IFX_PSI5_INTSTATB_SDI1_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_INTSTATB_Bits.SDI2 */
+#define IFX_PSI5_INTSTATB_SDI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATB_Bits.SDI2 */
+#define IFX_PSI5_INTSTATB_SDI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATB_Bits.SDI2 */
+#define IFX_PSI5_INTSTATB_SDI2_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_INTSTATB_Bits.SDI3 */
+#define IFX_PSI5_INTSTATB_SDI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATB_Bits.SDI3 */
+#define IFX_PSI5_INTSTATB_SDI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATB_Bits.SDI3 */
+#define IFX_PSI5_INTSTATB_SDI3_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_INTSTATB_Bits.SDI4 */
+#define IFX_PSI5_INTSTATB_SDI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATB_Bits.SDI4 */
+#define IFX_PSI5_INTSTATB_SDI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATB_Bits.SDI4 */
+#define IFX_PSI5_INTSTATB_SDI4_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_INTSTATB_Bits.SDI5 */
+#define IFX_PSI5_INTSTATB_SDI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATB_Bits.SDI5 */
+#define IFX_PSI5_INTSTATB_SDI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATB_Bits.SDI5 */
+#define IFX_PSI5_INTSTATB_SDI5_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_INTSTATB_Bits.SOI0 */
+#define IFX_PSI5_INTSTATB_SOI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATB_Bits.SOI0 */
+#define IFX_PSI5_INTSTATB_SOI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATB_Bits.SOI0 */
+#define IFX_PSI5_INTSTATB_SOI0_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_INTSTATB_Bits.SOI1 */
+#define IFX_PSI5_INTSTATB_SOI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATB_Bits.SOI1 */
+#define IFX_PSI5_INTSTATB_SOI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATB_Bits.SOI1 */
+#define IFX_PSI5_INTSTATB_SOI1_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_INTSTATB_Bits.SOI2 */
+#define IFX_PSI5_INTSTATB_SOI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATB_Bits.SOI2 */
+#define IFX_PSI5_INTSTATB_SOI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATB_Bits.SOI2 */
+#define IFX_PSI5_INTSTATB_SOI2_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_INTSTATB_Bits.SOI3 */
+#define IFX_PSI5_INTSTATB_SOI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATB_Bits.SOI3 */
+#define IFX_PSI5_INTSTATB_SOI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATB_Bits.SOI3 */
+#define IFX_PSI5_INTSTATB_SOI3_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_INTSTATB_Bits.SOI4 */
+#define IFX_PSI5_INTSTATB_SOI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATB_Bits.SOI4 */
+#define IFX_PSI5_INTSTATB_SOI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATB_Bits.SOI4 */
+#define IFX_PSI5_INTSTATB_SOI4_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_INTSTATB_Bits.SOI5 */
+#define IFX_PSI5_INTSTATB_SOI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATB_Bits.SOI5 */
+#define IFX_PSI5_INTSTATB_SOI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATB_Bits.SOI5 */
+#define IFX_PSI5_INTSTATB_SOI5_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_INTSTATB_Bits.WSI0 */
+#define IFX_PSI5_INTSTATB_WSI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATB_Bits.WSI0 */
+#define IFX_PSI5_INTSTATB_WSI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATB_Bits.WSI0 */
+#define IFX_PSI5_INTSTATB_WSI0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_INTSTATB_Bits.WSI1 */
+#define IFX_PSI5_INTSTATB_WSI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATB_Bits.WSI1 */
+#define IFX_PSI5_INTSTATB_WSI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATB_Bits.WSI1 */
+#define IFX_PSI5_INTSTATB_WSI1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_INTSTATB_Bits.WSI2 */
+#define IFX_PSI5_INTSTATB_WSI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATB_Bits.WSI2 */
+#define IFX_PSI5_INTSTATB_WSI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATB_Bits.WSI2 */
+#define IFX_PSI5_INTSTATB_WSI2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_INTSTATB_Bits.WSI3 */
+#define IFX_PSI5_INTSTATB_WSI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATB_Bits.WSI3 */
+#define IFX_PSI5_INTSTATB_WSI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATB_Bits.WSI3 */
+#define IFX_PSI5_INTSTATB_WSI3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_INTSTATB_Bits.WSI4 */
+#define IFX_PSI5_INTSTATB_WSI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATB_Bits.WSI4 */
+#define IFX_PSI5_INTSTATB_WSI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATB_Bits.WSI4 */
+#define IFX_PSI5_INTSTATB_WSI4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_INTSTATB_Bits.WSI5 */
+#define IFX_PSI5_INTSTATB_WSI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_INTSTATB_Bits.WSI5 */
+#define IFX_PSI5_INTSTATB_WSI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_INTSTATB_Bits.WSI5 */
+#define IFX_PSI5_INTSTATB_WSI5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_KRST0_Bits.RST */
+#define IFX_PSI5_KRST0_RST_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_KRST0_Bits.RST */
+#define IFX_PSI5_KRST0_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_KRST0_Bits.RST */
+#define IFX_PSI5_KRST0_RST_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_KRST0_Bits.RSTSTAT */
+#define IFX_PSI5_KRST0_RSTSTAT_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_KRST0_Bits.RSTSTAT */
+#define IFX_PSI5_KRST0_RSTSTAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_KRST0_Bits.RSTSTAT */
+#define IFX_PSI5_KRST0_RSTSTAT_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_KRST1_Bits.RST */
+#define IFX_PSI5_KRST1_RST_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_KRST1_Bits.RST */
+#define IFX_PSI5_KRST1_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_KRST1_Bits.RST */
+#define IFX_PSI5_KRST1_RST_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_KRSTCLR_Bits.CLR */
+#define IFX_PSI5_KRSTCLR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_KRSTCLR_Bits.CLR */
+#define IFX_PSI5_KRSTCLR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_KRSTCLR_Bits.CLR */
+#define IFX_PSI5_KRSTCLR_CLR_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI0 */
+#define IFX_PSI5_MEICLR_MEI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI0 */
+#define IFX_PSI5_MEICLR_MEI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI0 */
+#define IFX_PSI5_MEICLR_MEI0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI10 */
+#define IFX_PSI5_MEICLR_MEI10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI10 */
+#define IFX_PSI5_MEICLR_MEI10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI10 */
+#define IFX_PSI5_MEICLR_MEI10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI11 */
+#define IFX_PSI5_MEICLR_MEI11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI11 */
+#define IFX_PSI5_MEICLR_MEI11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI11 */
+#define IFX_PSI5_MEICLR_MEI11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI12 */
+#define IFX_PSI5_MEICLR_MEI12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI12 */
+#define IFX_PSI5_MEICLR_MEI12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI12 */
+#define IFX_PSI5_MEICLR_MEI12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI13 */
+#define IFX_PSI5_MEICLR_MEI13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI13 */
+#define IFX_PSI5_MEICLR_MEI13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI13 */
+#define IFX_PSI5_MEICLR_MEI13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI14 */
+#define IFX_PSI5_MEICLR_MEI14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI14 */
+#define IFX_PSI5_MEICLR_MEI14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI14 */
+#define IFX_PSI5_MEICLR_MEI14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI15 */
+#define IFX_PSI5_MEICLR_MEI15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI15 */
+#define IFX_PSI5_MEICLR_MEI15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI15 */
+#define IFX_PSI5_MEICLR_MEI15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI16 */
+#define IFX_PSI5_MEICLR_MEI16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI16 */
+#define IFX_PSI5_MEICLR_MEI16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI16 */
+#define IFX_PSI5_MEICLR_MEI16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI17 */
+#define IFX_PSI5_MEICLR_MEI17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI17 */
+#define IFX_PSI5_MEICLR_MEI17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI17 */
+#define IFX_PSI5_MEICLR_MEI17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI18 */
+#define IFX_PSI5_MEICLR_MEI18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI18 */
+#define IFX_PSI5_MEICLR_MEI18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI18 */
+#define IFX_PSI5_MEICLR_MEI18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI19 */
+#define IFX_PSI5_MEICLR_MEI19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI19 */
+#define IFX_PSI5_MEICLR_MEI19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI19 */
+#define IFX_PSI5_MEICLR_MEI19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI1 */
+#define IFX_PSI5_MEICLR_MEI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI1 */
+#define IFX_PSI5_MEICLR_MEI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI1 */
+#define IFX_PSI5_MEICLR_MEI1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI20 */
+#define IFX_PSI5_MEICLR_MEI20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI20 */
+#define IFX_PSI5_MEICLR_MEI20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI20 */
+#define IFX_PSI5_MEICLR_MEI20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI21 */
+#define IFX_PSI5_MEICLR_MEI21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI21 */
+#define IFX_PSI5_MEICLR_MEI21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI21 */
+#define IFX_PSI5_MEICLR_MEI21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI22 */
+#define IFX_PSI5_MEICLR_MEI22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI22 */
+#define IFX_PSI5_MEICLR_MEI22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI22 */
+#define IFX_PSI5_MEICLR_MEI22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI23 */
+#define IFX_PSI5_MEICLR_MEI23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI23 */
+#define IFX_PSI5_MEICLR_MEI23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI23 */
+#define IFX_PSI5_MEICLR_MEI23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI24 */
+#define IFX_PSI5_MEICLR_MEI24_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI24 */
+#define IFX_PSI5_MEICLR_MEI24_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI24 */
+#define IFX_PSI5_MEICLR_MEI24_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI25 */
+#define IFX_PSI5_MEICLR_MEI25_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI25 */
+#define IFX_PSI5_MEICLR_MEI25_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI25 */
+#define IFX_PSI5_MEICLR_MEI25_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI26 */
+#define IFX_PSI5_MEICLR_MEI26_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI26 */
+#define IFX_PSI5_MEICLR_MEI26_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI26 */
+#define IFX_PSI5_MEICLR_MEI26_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI27 */
+#define IFX_PSI5_MEICLR_MEI27_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI27 */
+#define IFX_PSI5_MEICLR_MEI27_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI27 */
+#define IFX_PSI5_MEICLR_MEI27_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI28 */
+#define IFX_PSI5_MEICLR_MEI28_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI28 */
+#define IFX_PSI5_MEICLR_MEI28_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI28 */
+#define IFX_PSI5_MEICLR_MEI28_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI29 */
+#define IFX_PSI5_MEICLR_MEI29_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI29 */
+#define IFX_PSI5_MEICLR_MEI29_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI29 */
+#define IFX_PSI5_MEICLR_MEI29_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI2 */
+#define IFX_PSI5_MEICLR_MEI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI2 */
+#define IFX_PSI5_MEICLR_MEI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI2 */
+#define IFX_PSI5_MEICLR_MEI2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI30 */
+#define IFX_PSI5_MEICLR_MEI30_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI30 */
+#define IFX_PSI5_MEICLR_MEI30_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI30 */
+#define IFX_PSI5_MEICLR_MEI30_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI31 */
+#define IFX_PSI5_MEICLR_MEI31_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI31 */
+#define IFX_PSI5_MEICLR_MEI31_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI31 */
+#define IFX_PSI5_MEICLR_MEI31_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI3 */
+#define IFX_PSI5_MEICLR_MEI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI3 */
+#define IFX_PSI5_MEICLR_MEI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI3 */
+#define IFX_PSI5_MEICLR_MEI3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI4 */
+#define IFX_PSI5_MEICLR_MEI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI4 */
+#define IFX_PSI5_MEICLR_MEI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI4 */
+#define IFX_PSI5_MEICLR_MEI4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI5 */
+#define IFX_PSI5_MEICLR_MEI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI5 */
+#define IFX_PSI5_MEICLR_MEI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI5 */
+#define IFX_PSI5_MEICLR_MEI5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI6 */
+#define IFX_PSI5_MEICLR_MEI6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI6 */
+#define IFX_PSI5_MEICLR_MEI6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI6 */
+#define IFX_PSI5_MEICLR_MEI6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI7 */
+#define IFX_PSI5_MEICLR_MEI7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI7 */
+#define IFX_PSI5_MEICLR_MEI7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI7 */
+#define IFX_PSI5_MEICLR_MEI7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI8 */
+#define IFX_PSI5_MEICLR_MEI8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI8 */
+#define IFX_PSI5_MEICLR_MEI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI8 */
+#define IFX_PSI5_MEICLR_MEI8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_MEICLR_Bits.MEI9 */
+#define IFX_PSI5_MEICLR_MEI9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEICLR_Bits.MEI9 */
+#define IFX_PSI5_MEICLR_MEI9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEICLR_Bits.MEI9 */
+#define IFX_PSI5_MEICLR_MEI9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI0 */
+#define IFX_PSI5_MEIOV_MEI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI0 */
+#define IFX_PSI5_MEIOV_MEI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI0 */
+#define IFX_PSI5_MEIOV_MEI0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI10 */
+#define IFX_PSI5_MEIOV_MEI10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI10 */
+#define IFX_PSI5_MEIOV_MEI10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI10 */
+#define IFX_PSI5_MEIOV_MEI10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI11 */
+#define IFX_PSI5_MEIOV_MEI11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI11 */
+#define IFX_PSI5_MEIOV_MEI11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI11 */
+#define IFX_PSI5_MEIOV_MEI11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI12 */
+#define IFX_PSI5_MEIOV_MEI12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI12 */
+#define IFX_PSI5_MEIOV_MEI12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI12 */
+#define IFX_PSI5_MEIOV_MEI12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI13 */
+#define IFX_PSI5_MEIOV_MEI13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI13 */
+#define IFX_PSI5_MEIOV_MEI13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI13 */
+#define IFX_PSI5_MEIOV_MEI13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI14 */
+#define IFX_PSI5_MEIOV_MEI14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI14 */
+#define IFX_PSI5_MEIOV_MEI14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI14 */
+#define IFX_PSI5_MEIOV_MEI14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI15 */
+#define IFX_PSI5_MEIOV_MEI15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI15 */
+#define IFX_PSI5_MEIOV_MEI15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI15 */
+#define IFX_PSI5_MEIOV_MEI15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI16 */
+#define IFX_PSI5_MEIOV_MEI16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI16 */
+#define IFX_PSI5_MEIOV_MEI16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI16 */
+#define IFX_PSI5_MEIOV_MEI16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI17 */
+#define IFX_PSI5_MEIOV_MEI17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI17 */
+#define IFX_PSI5_MEIOV_MEI17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI17 */
+#define IFX_PSI5_MEIOV_MEI17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI18 */
+#define IFX_PSI5_MEIOV_MEI18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI18 */
+#define IFX_PSI5_MEIOV_MEI18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI18 */
+#define IFX_PSI5_MEIOV_MEI18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI19 */
+#define IFX_PSI5_MEIOV_MEI19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI19 */
+#define IFX_PSI5_MEIOV_MEI19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI19 */
+#define IFX_PSI5_MEIOV_MEI19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI1 */
+#define IFX_PSI5_MEIOV_MEI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI1 */
+#define IFX_PSI5_MEIOV_MEI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI1 */
+#define IFX_PSI5_MEIOV_MEI1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI20 */
+#define IFX_PSI5_MEIOV_MEI20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI20 */
+#define IFX_PSI5_MEIOV_MEI20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI20 */
+#define IFX_PSI5_MEIOV_MEI20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI21 */
+#define IFX_PSI5_MEIOV_MEI21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI21 */
+#define IFX_PSI5_MEIOV_MEI21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI21 */
+#define IFX_PSI5_MEIOV_MEI21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI22 */
+#define IFX_PSI5_MEIOV_MEI22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI22 */
+#define IFX_PSI5_MEIOV_MEI22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI22 */
+#define IFX_PSI5_MEIOV_MEI22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI23 */
+#define IFX_PSI5_MEIOV_MEI23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI23 */
+#define IFX_PSI5_MEIOV_MEI23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI23 */
+#define IFX_PSI5_MEIOV_MEI23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI24 */
+#define IFX_PSI5_MEIOV_MEI24_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI24 */
+#define IFX_PSI5_MEIOV_MEI24_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI24 */
+#define IFX_PSI5_MEIOV_MEI24_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI25 */
+#define IFX_PSI5_MEIOV_MEI25_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI25 */
+#define IFX_PSI5_MEIOV_MEI25_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI25 */
+#define IFX_PSI5_MEIOV_MEI25_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI26 */
+#define IFX_PSI5_MEIOV_MEI26_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI26 */
+#define IFX_PSI5_MEIOV_MEI26_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI26 */
+#define IFX_PSI5_MEIOV_MEI26_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI27 */
+#define IFX_PSI5_MEIOV_MEI27_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI27 */
+#define IFX_PSI5_MEIOV_MEI27_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI27 */
+#define IFX_PSI5_MEIOV_MEI27_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI28 */
+#define IFX_PSI5_MEIOV_MEI28_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI28 */
+#define IFX_PSI5_MEIOV_MEI28_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI28 */
+#define IFX_PSI5_MEIOV_MEI28_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI29 */
+#define IFX_PSI5_MEIOV_MEI29_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI29 */
+#define IFX_PSI5_MEIOV_MEI29_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI29 */
+#define IFX_PSI5_MEIOV_MEI29_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI2 */
+#define IFX_PSI5_MEIOV_MEI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI2 */
+#define IFX_PSI5_MEIOV_MEI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI2 */
+#define IFX_PSI5_MEIOV_MEI2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI30 */
+#define IFX_PSI5_MEIOV_MEI30_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI30 */
+#define IFX_PSI5_MEIOV_MEI30_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI30 */
+#define IFX_PSI5_MEIOV_MEI30_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI31 */
+#define IFX_PSI5_MEIOV_MEI31_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI31 */
+#define IFX_PSI5_MEIOV_MEI31_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI31 */
+#define IFX_PSI5_MEIOV_MEI31_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI3 */
+#define IFX_PSI5_MEIOV_MEI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI3 */
+#define IFX_PSI5_MEIOV_MEI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI3 */
+#define IFX_PSI5_MEIOV_MEI3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI4 */
+#define IFX_PSI5_MEIOV_MEI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI4 */
+#define IFX_PSI5_MEIOV_MEI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI4 */
+#define IFX_PSI5_MEIOV_MEI4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI5 */
+#define IFX_PSI5_MEIOV_MEI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI5 */
+#define IFX_PSI5_MEIOV_MEI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI5 */
+#define IFX_PSI5_MEIOV_MEI5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI6 */
+#define IFX_PSI5_MEIOV_MEI6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI6 */
+#define IFX_PSI5_MEIOV_MEI6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI6 */
+#define IFX_PSI5_MEIOV_MEI6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI7 */
+#define IFX_PSI5_MEIOV_MEI7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI7 */
+#define IFX_PSI5_MEIOV_MEI7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI7 */
+#define IFX_PSI5_MEIOV_MEI7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI8 */
+#define IFX_PSI5_MEIOV_MEI8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI8 */
+#define IFX_PSI5_MEIOV_MEI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI8 */
+#define IFX_PSI5_MEIOV_MEI8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_MEIOV_Bits.MEI9 */
+#define IFX_PSI5_MEIOV_MEI9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEIOV_Bits.MEI9 */
+#define IFX_PSI5_MEIOV_MEI9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEIOV_Bits.MEI9 */
+#define IFX_PSI5_MEIOV_MEI9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI0 */
+#define IFX_PSI5_MEISET_MEI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI0 */
+#define IFX_PSI5_MEISET_MEI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI0 */
+#define IFX_PSI5_MEISET_MEI0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI10 */
+#define IFX_PSI5_MEISET_MEI10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI10 */
+#define IFX_PSI5_MEISET_MEI10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI10 */
+#define IFX_PSI5_MEISET_MEI10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI11 */
+#define IFX_PSI5_MEISET_MEI11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI11 */
+#define IFX_PSI5_MEISET_MEI11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI11 */
+#define IFX_PSI5_MEISET_MEI11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI12 */
+#define IFX_PSI5_MEISET_MEI12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI12 */
+#define IFX_PSI5_MEISET_MEI12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI12 */
+#define IFX_PSI5_MEISET_MEI12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI13 */
+#define IFX_PSI5_MEISET_MEI13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI13 */
+#define IFX_PSI5_MEISET_MEI13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI13 */
+#define IFX_PSI5_MEISET_MEI13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI14 */
+#define IFX_PSI5_MEISET_MEI14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI14 */
+#define IFX_PSI5_MEISET_MEI14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI14 */
+#define IFX_PSI5_MEISET_MEI14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI15 */
+#define IFX_PSI5_MEISET_MEI15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI15 */
+#define IFX_PSI5_MEISET_MEI15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI15 */
+#define IFX_PSI5_MEISET_MEI15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI16 */
+#define IFX_PSI5_MEISET_MEI16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI16 */
+#define IFX_PSI5_MEISET_MEI16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI16 */
+#define IFX_PSI5_MEISET_MEI16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI17 */
+#define IFX_PSI5_MEISET_MEI17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI17 */
+#define IFX_PSI5_MEISET_MEI17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI17 */
+#define IFX_PSI5_MEISET_MEI17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI18 */
+#define IFX_PSI5_MEISET_MEI18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI18 */
+#define IFX_PSI5_MEISET_MEI18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI18 */
+#define IFX_PSI5_MEISET_MEI18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI19 */
+#define IFX_PSI5_MEISET_MEI19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI19 */
+#define IFX_PSI5_MEISET_MEI19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI19 */
+#define IFX_PSI5_MEISET_MEI19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI1 */
+#define IFX_PSI5_MEISET_MEI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI1 */
+#define IFX_PSI5_MEISET_MEI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI1 */
+#define IFX_PSI5_MEISET_MEI1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI20 */
+#define IFX_PSI5_MEISET_MEI20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI20 */
+#define IFX_PSI5_MEISET_MEI20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI20 */
+#define IFX_PSI5_MEISET_MEI20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI21 */
+#define IFX_PSI5_MEISET_MEI21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI21 */
+#define IFX_PSI5_MEISET_MEI21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI21 */
+#define IFX_PSI5_MEISET_MEI21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI22 */
+#define IFX_PSI5_MEISET_MEI22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI22 */
+#define IFX_PSI5_MEISET_MEI22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI22 */
+#define IFX_PSI5_MEISET_MEI22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI23 */
+#define IFX_PSI5_MEISET_MEI23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI23 */
+#define IFX_PSI5_MEISET_MEI23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI23 */
+#define IFX_PSI5_MEISET_MEI23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI24 */
+#define IFX_PSI5_MEISET_MEI24_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI24 */
+#define IFX_PSI5_MEISET_MEI24_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI24 */
+#define IFX_PSI5_MEISET_MEI24_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI25 */
+#define IFX_PSI5_MEISET_MEI25_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI25 */
+#define IFX_PSI5_MEISET_MEI25_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI25 */
+#define IFX_PSI5_MEISET_MEI25_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI26 */
+#define IFX_PSI5_MEISET_MEI26_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI26 */
+#define IFX_PSI5_MEISET_MEI26_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI26 */
+#define IFX_PSI5_MEISET_MEI26_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI27 */
+#define IFX_PSI5_MEISET_MEI27_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI27 */
+#define IFX_PSI5_MEISET_MEI27_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI27 */
+#define IFX_PSI5_MEISET_MEI27_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI28 */
+#define IFX_PSI5_MEISET_MEI28_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI28 */
+#define IFX_PSI5_MEISET_MEI28_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI28 */
+#define IFX_PSI5_MEISET_MEI28_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI29 */
+#define IFX_PSI5_MEISET_MEI29_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI29 */
+#define IFX_PSI5_MEISET_MEI29_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI29 */
+#define IFX_PSI5_MEISET_MEI29_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI2 */
+#define IFX_PSI5_MEISET_MEI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI2 */
+#define IFX_PSI5_MEISET_MEI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI2 */
+#define IFX_PSI5_MEISET_MEI2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI30 */
+#define IFX_PSI5_MEISET_MEI30_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI30 */
+#define IFX_PSI5_MEISET_MEI30_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI30 */
+#define IFX_PSI5_MEISET_MEI30_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI31 */
+#define IFX_PSI5_MEISET_MEI31_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI31 */
+#define IFX_PSI5_MEISET_MEI31_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI31 */
+#define IFX_PSI5_MEISET_MEI31_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI3 */
+#define IFX_PSI5_MEISET_MEI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI3 */
+#define IFX_PSI5_MEISET_MEI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI3 */
+#define IFX_PSI5_MEISET_MEI3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI4 */
+#define IFX_PSI5_MEISET_MEI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI4 */
+#define IFX_PSI5_MEISET_MEI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI4 */
+#define IFX_PSI5_MEISET_MEI4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI5 */
+#define IFX_PSI5_MEISET_MEI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI5 */
+#define IFX_PSI5_MEISET_MEI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI5 */
+#define IFX_PSI5_MEISET_MEI5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI6 */
+#define IFX_PSI5_MEISET_MEI6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI6 */
+#define IFX_PSI5_MEISET_MEI6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI6 */
+#define IFX_PSI5_MEISET_MEI6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI7 */
+#define IFX_PSI5_MEISET_MEI7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI7 */
+#define IFX_PSI5_MEISET_MEI7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI7 */
+#define IFX_PSI5_MEISET_MEI7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI8 */
+#define IFX_PSI5_MEISET_MEI8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI8 */
+#define IFX_PSI5_MEISET_MEI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI8 */
+#define IFX_PSI5_MEISET_MEI8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_MEISET_Bits.MEI9 */
+#define IFX_PSI5_MEISET_MEI9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_MEISET_Bits.MEI9 */
+#define IFX_PSI5_MEISET_MEI9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_MEISET_Bits.MEI9 */
+#define IFX_PSI5_MEISET_MEI9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI0 */
+#define IFX_PSI5_NBICLR_NBI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI0 */
+#define IFX_PSI5_NBICLR_NBI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI0 */
+#define IFX_PSI5_NBICLR_NBI0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI10 */
+#define IFX_PSI5_NBICLR_NBI10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI10 */
+#define IFX_PSI5_NBICLR_NBI10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI10 */
+#define IFX_PSI5_NBICLR_NBI10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI11 */
+#define IFX_PSI5_NBICLR_NBI11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI11 */
+#define IFX_PSI5_NBICLR_NBI11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI11 */
+#define IFX_PSI5_NBICLR_NBI11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI12 */
+#define IFX_PSI5_NBICLR_NBI12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI12 */
+#define IFX_PSI5_NBICLR_NBI12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI12 */
+#define IFX_PSI5_NBICLR_NBI12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI13 */
+#define IFX_PSI5_NBICLR_NBI13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI13 */
+#define IFX_PSI5_NBICLR_NBI13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI13 */
+#define IFX_PSI5_NBICLR_NBI13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI14 */
+#define IFX_PSI5_NBICLR_NBI14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI14 */
+#define IFX_PSI5_NBICLR_NBI14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI14 */
+#define IFX_PSI5_NBICLR_NBI14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI15 */
+#define IFX_PSI5_NBICLR_NBI15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI15 */
+#define IFX_PSI5_NBICLR_NBI15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI15 */
+#define IFX_PSI5_NBICLR_NBI15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI16 */
+#define IFX_PSI5_NBICLR_NBI16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI16 */
+#define IFX_PSI5_NBICLR_NBI16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI16 */
+#define IFX_PSI5_NBICLR_NBI16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI17 */
+#define IFX_PSI5_NBICLR_NBI17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI17 */
+#define IFX_PSI5_NBICLR_NBI17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI17 */
+#define IFX_PSI5_NBICLR_NBI17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI18 */
+#define IFX_PSI5_NBICLR_NBI18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI18 */
+#define IFX_PSI5_NBICLR_NBI18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI18 */
+#define IFX_PSI5_NBICLR_NBI18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI19 */
+#define IFX_PSI5_NBICLR_NBI19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI19 */
+#define IFX_PSI5_NBICLR_NBI19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI19 */
+#define IFX_PSI5_NBICLR_NBI19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI1 */
+#define IFX_PSI5_NBICLR_NBI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI1 */
+#define IFX_PSI5_NBICLR_NBI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI1 */
+#define IFX_PSI5_NBICLR_NBI1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI20 */
+#define IFX_PSI5_NBICLR_NBI20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI20 */
+#define IFX_PSI5_NBICLR_NBI20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI20 */
+#define IFX_PSI5_NBICLR_NBI20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI21 */
+#define IFX_PSI5_NBICLR_NBI21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI21 */
+#define IFX_PSI5_NBICLR_NBI21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI21 */
+#define IFX_PSI5_NBICLR_NBI21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI22 */
+#define IFX_PSI5_NBICLR_NBI22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI22 */
+#define IFX_PSI5_NBICLR_NBI22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI22 */
+#define IFX_PSI5_NBICLR_NBI22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI23 */
+#define IFX_PSI5_NBICLR_NBI23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI23 */
+#define IFX_PSI5_NBICLR_NBI23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI23 */
+#define IFX_PSI5_NBICLR_NBI23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI24 */
+#define IFX_PSI5_NBICLR_NBI24_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI24 */
+#define IFX_PSI5_NBICLR_NBI24_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI24 */
+#define IFX_PSI5_NBICLR_NBI24_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI25 */
+#define IFX_PSI5_NBICLR_NBI25_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI25 */
+#define IFX_PSI5_NBICLR_NBI25_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI25 */
+#define IFX_PSI5_NBICLR_NBI25_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI26 */
+#define IFX_PSI5_NBICLR_NBI26_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI26 */
+#define IFX_PSI5_NBICLR_NBI26_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI26 */
+#define IFX_PSI5_NBICLR_NBI26_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI27 */
+#define IFX_PSI5_NBICLR_NBI27_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI27 */
+#define IFX_PSI5_NBICLR_NBI27_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI27 */
+#define IFX_PSI5_NBICLR_NBI27_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI28 */
+#define IFX_PSI5_NBICLR_NBI28_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI28 */
+#define IFX_PSI5_NBICLR_NBI28_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI28 */
+#define IFX_PSI5_NBICLR_NBI28_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI29 */
+#define IFX_PSI5_NBICLR_NBI29_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI29 */
+#define IFX_PSI5_NBICLR_NBI29_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI29 */
+#define IFX_PSI5_NBICLR_NBI29_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI2 */
+#define IFX_PSI5_NBICLR_NBI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI2 */
+#define IFX_PSI5_NBICLR_NBI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI2 */
+#define IFX_PSI5_NBICLR_NBI2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI30 */
+#define IFX_PSI5_NBICLR_NBI30_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI30 */
+#define IFX_PSI5_NBICLR_NBI30_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI30 */
+#define IFX_PSI5_NBICLR_NBI30_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI31 */
+#define IFX_PSI5_NBICLR_NBI31_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI31 */
+#define IFX_PSI5_NBICLR_NBI31_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI31 */
+#define IFX_PSI5_NBICLR_NBI31_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI3 */
+#define IFX_PSI5_NBICLR_NBI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI3 */
+#define IFX_PSI5_NBICLR_NBI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI3 */
+#define IFX_PSI5_NBICLR_NBI3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI4 */
+#define IFX_PSI5_NBICLR_NBI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI4 */
+#define IFX_PSI5_NBICLR_NBI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI4 */
+#define IFX_PSI5_NBICLR_NBI4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI5 */
+#define IFX_PSI5_NBICLR_NBI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI5 */
+#define IFX_PSI5_NBICLR_NBI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI5 */
+#define IFX_PSI5_NBICLR_NBI5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI6 */
+#define IFX_PSI5_NBICLR_NBI6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI6 */
+#define IFX_PSI5_NBICLR_NBI6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI6 */
+#define IFX_PSI5_NBICLR_NBI6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI7 */
+#define IFX_PSI5_NBICLR_NBI7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI7 */
+#define IFX_PSI5_NBICLR_NBI7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI7 */
+#define IFX_PSI5_NBICLR_NBI7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI8 */
+#define IFX_PSI5_NBICLR_NBI8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI8 */
+#define IFX_PSI5_NBICLR_NBI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI8 */
+#define IFX_PSI5_NBICLR_NBI8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_NBICLR_Bits.NBI9 */
+#define IFX_PSI5_NBICLR_NBI9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBICLR_Bits.NBI9 */
+#define IFX_PSI5_NBICLR_NBI9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBICLR_Bits.NBI9 */
+#define IFX_PSI5_NBICLR_NBI9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI0 */
+#define IFX_PSI5_NBIOV_NBI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI0 */
+#define IFX_PSI5_NBIOV_NBI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI0 */
+#define IFX_PSI5_NBIOV_NBI0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI10 */
+#define IFX_PSI5_NBIOV_NBI10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI10 */
+#define IFX_PSI5_NBIOV_NBI10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI10 */
+#define IFX_PSI5_NBIOV_NBI10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI11 */
+#define IFX_PSI5_NBIOV_NBI11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI11 */
+#define IFX_PSI5_NBIOV_NBI11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI11 */
+#define IFX_PSI5_NBIOV_NBI11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI12 */
+#define IFX_PSI5_NBIOV_NBI12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI12 */
+#define IFX_PSI5_NBIOV_NBI12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI12 */
+#define IFX_PSI5_NBIOV_NBI12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI13 */
+#define IFX_PSI5_NBIOV_NBI13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI13 */
+#define IFX_PSI5_NBIOV_NBI13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI13 */
+#define IFX_PSI5_NBIOV_NBI13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI14 */
+#define IFX_PSI5_NBIOV_NBI14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI14 */
+#define IFX_PSI5_NBIOV_NBI14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI14 */
+#define IFX_PSI5_NBIOV_NBI14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI15 */
+#define IFX_PSI5_NBIOV_NBI15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI15 */
+#define IFX_PSI5_NBIOV_NBI15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI15 */
+#define IFX_PSI5_NBIOV_NBI15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI16 */
+#define IFX_PSI5_NBIOV_NBI16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI16 */
+#define IFX_PSI5_NBIOV_NBI16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI16 */
+#define IFX_PSI5_NBIOV_NBI16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI17 */
+#define IFX_PSI5_NBIOV_NBI17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI17 */
+#define IFX_PSI5_NBIOV_NBI17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI17 */
+#define IFX_PSI5_NBIOV_NBI17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI18 */
+#define IFX_PSI5_NBIOV_NBI18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI18 */
+#define IFX_PSI5_NBIOV_NBI18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI18 */
+#define IFX_PSI5_NBIOV_NBI18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI19 */
+#define IFX_PSI5_NBIOV_NBI19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI19 */
+#define IFX_PSI5_NBIOV_NBI19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI19 */
+#define IFX_PSI5_NBIOV_NBI19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI1 */
+#define IFX_PSI5_NBIOV_NBI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI1 */
+#define IFX_PSI5_NBIOV_NBI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI1 */
+#define IFX_PSI5_NBIOV_NBI1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI20 */
+#define IFX_PSI5_NBIOV_NBI20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI20 */
+#define IFX_PSI5_NBIOV_NBI20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI20 */
+#define IFX_PSI5_NBIOV_NBI20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI21 */
+#define IFX_PSI5_NBIOV_NBI21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI21 */
+#define IFX_PSI5_NBIOV_NBI21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI21 */
+#define IFX_PSI5_NBIOV_NBI21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI22 */
+#define IFX_PSI5_NBIOV_NBI22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI22 */
+#define IFX_PSI5_NBIOV_NBI22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI22 */
+#define IFX_PSI5_NBIOV_NBI22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI23 */
+#define IFX_PSI5_NBIOV_NBI23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI23 */
+#define IFX_PSI5_NBIOV_NBI23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI23 */
+#define IFX_PSI5_NBIOV_NBI23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI24 */
+#define IFX_PSI5_NBIOV_NBI24_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI24 */
+#define IFX_PSI5_NBIOV_NBI24_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI24 */
+#define IFX_PSI5_NBIOV_NBI24_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI25 */
+#define IFX_PSI5_NBIOV_NBI25_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI25 */
+#define IFX_PSI5_NBIOV_NBI25_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI25 */
+#define IFX_PSI5_NBIOV_NBI25_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI26 */
+#define IFX_PSI5_NBIOV_NBI26_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI26 */
+#define IFX_PSI5_NBIOV_NBI26_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI26 */
+#define IFX_PSI5_NBIOV_NBI26_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI27 */
+#define IFX_PSI5_NBIOV_NBI27_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI27 */
+#define IFX_PSI5_NBIOV_NBI27_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI27 */
+#define IFX_PSI5_NBIOV_NBI27_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI28 */
+#define IFX_PSI5_NBIOV_NBI28_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI28 */
+#define IFX_PSI5_NBIOV_NBI28_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI28 */
+#define IFX_PSI5_NBIOV_NBI28_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI29 */
+#define IFX_PSI5_NBIOV_NBI29_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI29 */
+#define IFX_PSI5_NBIOV_NBI29_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI29 */
+#define IFX_PSI5_NBIOV_NBI29_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI2 */
+#define IFX_PSI5_NBIOV_NBI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI2 */
+#define IFX_PSI5_NBIOV_NBI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI2 */
+#define IFX_PSI5_NBIOV_NBI2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI30 */
+#define IFX_PSI5_NBIOV_NBI30_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI30 */
+#define IFX_PSI5_NBIOV_NBI30_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI30 */
+#define IFX_PSI5_NBIOV_NBI30_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI31 */
+#define IFX_PSI5_NBIOV_NBI31_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI31 */
+#define IFX_PSI5_NBIOV_NBI31_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI31 */
+#define IFX_PSI5_NBIOV_NBI31_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI3 */
+#define IFX_PSI5_NBIOV_NBI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI3 */
+#define IFX_PSI5_NBIOV_NBI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI3 */
+#define IFX_PSI5_NBIOV_NBI3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI4 */
+#define IFX_PSI5_NBIOV_NBI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI4 */
+#define IFX_PSI5_NBIOV_NBI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI4 */
+#define IFX_PSI5_NBIOV_NBI4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI5 */
+#define IFX_PSI5_NBIOV_NBI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI5 */
+#define IFX_PSI5_NBIOV_NBI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI5 */
+#define IFX_PSI5_NBIOV_NBI5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI6 */
+#define IFX_PSI5_NBIOV_NBI6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI6 */
+#define IFX_PSI5_NBIOV_NBI6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI6 */
+#define IFX_PSI5_NBIOV_NBI6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI7 */
+#define IFX_PSI5_NBIOV_NBI7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI7 */
+#define IFX_PSI5_NBIOV_NBI7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI7 */
+#define IFX_PSI5_NBIOV_NBI7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI8 */
+#define IFX_PSI5_NBIOV_NBI8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI8 */
+#define IFX_PSI5_NBIOV_NBI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI8 */
+#define IFX_PSI5_NBIOV_NBI8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_NBIOV_Bits.NBI9 */
+#define IFX_PSI5_NBIOV_NBI9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBIOV_Bits.NBI9 */
+#define IFX_PSI5_NBIOV_NBI9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBIOV_Bits.NBI9 */
+#define IFX_PSI5_NBIOV_NBI9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI0 */
+#define IFX_PSI5_NBISET_NBI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI0 */
+#define IFX_PSI5_NBISET_NBI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI0 */
+#define IFX_PSI5_NBISET_NBI0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI10 */
+#define IFX_PSI5_NBISET_NBI10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI10 */
+#define IFX_PSI5_NBISET_NBI10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI10 */
+#define IFX_PSI5_NBISET_NBI10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI11 */
+#define IFX_PSI5_NBISET_NBI11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI11 */
+#define IFX_PSI5_NBISET_NBI11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI11 */
+#define IFX_PSI5_NBISET_NBI11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI12 */
+#define IFX_PSI5_NBISET_NBI12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI12 */
+#define IFX_PSI5_NBISET_NBI12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI12 */
+#define IFX_PSI5_NBISET_NBI12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI13 */
+#define IFX_PSI5_NBISET_NBI13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI13 */
+#define IFX_PSI5_NBISET_NBI13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI13 */
+#define IFX_PSI5_NBISET_NBI13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI14 */
+#define IFX_PSI5_NBISET_NBI14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI14 */
+#define IFX_PSI5_NBISET_NBI14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI14 */
+#define IFX_PSI5_NBISET_NBI14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI15 */
+#define IFX_PSI5_NBISET_NBI15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI15 */
+#define IFX_PSI5_NBISET_NBI15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI15 */
+#define IFX_PSI5_NBISET_NBI15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI16 */
+#define IFX_PSI5_NBISET_NBI16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI16 */
+#define IFX_PSI5_NBISET_NBI16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI16 */
+#define IFX_PSI5_NBISET_NBI16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI17 */
+#define IFX_PSI5_NBISET_NBI17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI17 */
+#define IFX_PSI5_NBISET_NBI17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI17 */
+#define IFX_PSI5_NBISET_NBI17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI18 */
+#define IFX_PSI5_NBISET_NBI18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI18 */
+#define IFX_PSI5_NBISET_NBI18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI18 */
+#define IFX_PSI5_NBISET_NBI18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI19 */
+#define IFX_PSI5_NBISET_NBI19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI19 */
+#define IFX_PSI5_NBISET_NBI19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI19 */
+#define IFX_PSI5_NBISET_NBI19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI1 */
+#define IFX_PSI5_NBISET_NBI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI1 */
+#define IFX_PSI5_NBISET_NBI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI1 */
+#define IFX_PSI5_NBISET_NBI1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI20 */
+#define IFX_PSI5_NBISET_NBI20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI20 */
+#define IFX_PSI5_NBISET_NBI20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI20 */
+#define IFX_PSI5_NBISET_NBI20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI21 */
+#define IFX_PSI5_NBISET_NBI21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI21 */
+#define IFX_PSI5_NBISET_NBI21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI21 */
+#define IFX_PSI5_NBISET_NBI21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI22 */
+#define IFX_PSI5_NBISET_NBI22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI22 */
+#define IFX_PSI5_NBISET_NBI22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI22 */
+#define IFX_PSI5_NBISET_NBI22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI23 */
+#define IFX_PSI5_NBISET_NBI23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI23 */
+#define IFX_PSI5_NBISET_NBI23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI23 */
+#define IFX_PSI5_NBISET_NBI23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI24 */
+#define IFX_PSI5_NBISET_NBI24_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI24 */
+#define IFX_PSI5_NBISET_NBI24_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI24 */
+#define IFX_PSI5_NBISET_NBI24_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI25 */
+#define IFX_PSI5_NBISET_NBI25_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI25 */
+#define IFX_PSI5_NBISET_NBI25_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI25 */
+#define IFX_PSI5_NBISET_NBI25_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI26 */
+#define IFX_PSI5_NBISET_NBI26_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI26 */
+#define IFX_PSI5_NBISET_NBI26_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI26 */
+#define IFX_PSI5_NBISET_NBI26_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI27 */
+#define IFX_PSI5_NBISET_NBI27_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI27 */
+#define IFX_PSI5_NBISET_NBI27_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI27 */
+#define IFX_PSI5_NBISET_NBI27_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI28 */
+#define IFX_PSI5_NBISET_NBI28_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI28 */
+#define IFX_PSI5_NBISET_NBI28_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI28 */
+#define IFX_PSI5_NBISET_NBI28_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI29 */
+#define IFX_PSI5_NBISET_NBI29_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI29 */
+#define IFX_PSI5_NBISET_NBI29_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI29 */
+#define IFX_PSI5_NBISET_NBI29_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI2 */
+#define IFX_PSI5_NBISET_NBI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI2 */
+#define IFX_PSI5_NBISET_NBI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI2 */
+#define IFX_PSI5_NBISET_NBI2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI30 */
+#define IFX_PSI5_NBISET_NBI30_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI30 */
+#define IFX_PSI5_NBISET_NBI30_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI30 */
+#define IFX_PSI5_NBISET_NBI30_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI31 */
+#define IFX_PSI5_NBISET_NBI31_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI31 */
+#define IFX_PSI5_NBISET_NBI31_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI31 */
+#define IFX_PSI5_NBISET_NBI31_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI3 */
+#define IFX_PSI5_NBISET_NBI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI3 */
+#define IFX_PSI5_NBISET_NBI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI3 */
+#define IFX_PSI5_NBISET_NBI3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI4 */
+#define IFX_PSI5_NBISET_NBI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI4 */
+#define IFX_PSI5_NBISET_NBI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI4 */
+#define IFX_PSI5_NBISET_NBI4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI5 */
+#define IFX_PSI5_NBISET_NBI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI5 */
+#define IFX_PSI5_NBISET_NBI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI5 */
+#define IFX_PSI5_NBISET_NBI5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI6 */
+#define IFX_PSI5_NBISET_NBI6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI6 */
+#define IFX_PSI5_NBISET_NBI6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI6 */
+#define IFX_PSI5_NBISET_NBI6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI7 */
+#define IFX_PSI5_NBISET_NBI7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI7 */
+#define IFX_PSI5_NBISET_NBI7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI7 */
+#define IFX_PSI5_NBISET_NBI7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI8 */
+#define IFX_PSI5_NBISET_NBI8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI8 */
+#define IFX_PSI5_NBISET_NBI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI8 */
+#define IFX_PSI5_NBISET_NBI8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_NBISET_Bits.NBI9 */
+#define IFX_PSI5_NBISET_NBI9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NBISET_Bits.NBI9 */
+#define IFX_PSI5_NBISET_NBI9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NBISET_Bits.NBI9 */
+#define IFX_PSI5_NBISET_NBI9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI0 */
+#define IFX_PSI5_NFICLR_NFI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI0 */
+#define IFX_PSI5_NFICLR_NFI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI0 */
+#define IFX_PSI5_NFICLR_NFI0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI10 */
+#define IFX_PSI5_NFICLR_NFI10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI10 */
+#define IFX_PSI5_NFICLR_NFI10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI10 */
+#define IFX_PSI5_NFICLR_NFI10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI11 */
+#define IFX_PSI5_NFICLR_NFI11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI11 */
+#define IFX_PSI5_NFICLR_NFI11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI11 */
+#define IFX_PSI5_NFICLR_NFI11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI12 */
+#define IFX_PSI5_NFICLR_NFI12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI12 */
+#define IFX_PSI5_NFICLR_NFI12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI12 */
+#define IFX_PSI5_NFICLR_NFI12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI13 */
+#define IFX_PSI5_NFICLR_NFI13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI13 */
+#define IFX_PSI5_NFICLR_NFI13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI13 */
+#define IFX_PSI5_NFICLR_NFI13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI14 */
+#define IFX_PSI5_NFICLR_NFI14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI14 */
+#define IFX_PSI5_NFICLR_NFI14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI14 */
+#define IFX_PSI5_NFICLR_NFI14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI15 */
+#define IFX_PSI5_NFICLR_NFI15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI15 */
+#define IFX_PSI5_NFICLR_NFI15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI15 */
+#define IFX_PSI5_NFICLR_NFI15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI16 */
+#define IFX_PSI5_NFICLR_NFI16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI16 */
+#define IFX_PSI5_NFICLR_NFI16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI16 */
+#define IFX_PSI5_NFICLR_NFI16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI17 */
+#define IFX_PSI5_NFICLR_NFI17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI17 */
+#define IFX_PSI5_NFICLR_NFI17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI17 */
+#define IFX_PSI5_NFICLR_NFI17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI18 */
+#define IFX_PSI5_NFICLR_NFI18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI18 */
+#define IFX_PSI5_NFICLR_NFI18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI18 */
+#define IFX_PSI5_NFICLR_NFI18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI19 */
+#define IFX_PSI5_NFICLR_NFI19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI19 */
+#define IFX_PSI5_NFICLR_NFI19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI19 */
+#define IFX_PSI5_NFICLR_NFI19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI1 */
+#define IFX_PSI5_NFICLR_NFI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI1 */
+#define IFX_PSI5_NFICLR_NFI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI1 */
+#define IFX_PSI5_NFICLR_NFI1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI20 */
+#define IFX_PSI5_NFICLR_NFI20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI20 */
+#define IFX_PSI5_NFICLR_NFI20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI20 */
+#define IFX_PSI5_NFICLR_NFI20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI21 */
+#define IFX_PSI5_NFICLR_NFI21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI21 */
+#define IFX_PSI5_NFICLR_NFI21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI21 */
+#define IFX_PSI5_NFICLR_NFI21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI22 */
+#define IFX_PSI5_NFICLR_NFI22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI22 */
+#define IFX_PSI5_NFICLR_NFI22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI22 */
+#define IFX_PSI5_NFICLR_NFI22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI23 */
+#define IFX_PSI5_NFICLR_NFI23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI23 */
+#define IFX_PSI5_NFICLR_NFI23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI23 */
+#define IFX_PSI5_NFICLR_NFI23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI24 */
+#define IFX_PSI5_NFICLR_NFI24_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI24 */
+#define IFX_PSI5_NFICLR_NFI24_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI24 */
+#define IFX_PSI5_NFICLR_NFI24_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI25 */
+#define IFX_PSI5_NFICLR_NFI25_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI25 */
+#define IFX_PSI5_NFICLR_NFI25_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI25 */
+#define IFX_PSI5_NFICLR_NFI25_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI26 */
+#define IFX_PSI5_NFICLR_NFI26_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI26 */
+#define IFX_PSI5_NFICLR_NFI26_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI26 */
+#define IFX_PSI5_NFICLR_NFI26_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI27 */
+#define IFX_PSI5_NFICLR_NFI27_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI27 */
+#define IFX_PSI5_NFICLR_NFI27_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI27 */
+#define IFX_PSI5_NFICLR_NFI27_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI28 */
+#define IFX_PSI5_NFICLR_NFI28_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI28 */
+#define IFX_PSI5_NFICLR_NFI28_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI28 */
+#define IFX_PSI5_NFICLR_NFI28_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI29 */
+#define IFX_PSI5_NFICLR_NFI29_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI29 */
+#define IFX_PSI5_NFICLR_NFI29_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI29 */
+#define IFX_PSI5_NFICLR_NFI29_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI2 */
+#define IFX_PSI5_NFICLR_NFI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI2 */
+#define IFX_PSI5_NFICLR_NFI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI2 */
+#define IFX_PSI5_NFICLR_NFI2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI30 */
+#define IFX_PSI5_NFICLR_NFI30_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI30 */
+#define IFX_PSI5_NFICLR_NFI30_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI30 */
+#define IFX_PSI5_NFICLR_NFI30_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI31 */
+#define IFX_PSI5_NFICLR_NFI31_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI31 */
+#define IFX_PSI5_NFICLR_NFI31_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI31 */
+#define IFX_PSI5_NFICLR_NFI31_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI3 */
+#define IFX_PSI5_NFICLR_NFI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI3 */
+#define IFX_PSI5_NFICLR_NFI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI3 */
+#define IFX_PSI5_NFICLR_NFI3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI4 */
+#define IFX_PSI5_NFICLR_NFI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI4 */
+#define IFX_PSI5_NFICLR_NFI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI4 */
+#define IFX_PSI5_NFICLR_NFI4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI5 */
+#define IFX_PSI5_NFICLR_NFI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI5 */
+#define IFX_PSI5_NFICLR_NFI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI5 */
+#define IFX_PSI5_NFICLR_NFI5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI6 */
+#define IFX_PSI5_NFICLR_NFI6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI6 */
+#define IFX_PSI5_NFICLR_NFI6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI6 */
+#define IFX_PSI5_NFICLR_NFI6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI7 */
+#define IFX_PSI5_NFICLR_NFI7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI7 */
+#define IFX_PSI5_NFICLR_NFI7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI7 */
+#define IFX_PSI5_NFICLR_NFI7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI8 */
+#define IFX_PSI5_NFICLR_NFI8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI8 */
+#define IFX_PSI5_NFICLR_NFI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI8 */
+#define IFX_PSI5_NFICLR_NFI8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_NFICLR_Bits.NFI9 */
+#define IFX_PSI5_NFICLR_NFI9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFICLR_Bits.NFI9 */
+#define IFX_PSI5_NFICLR_NFI9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFICLR_Bits.NFI9 */
+#define IFX_PSI5_NFICLR_NFI9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI0 */
+#define IFX_PSI5_NFIOV_NFI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI0 */
+#define IFX_PSI5_NFIOV_NFI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI0 */
+#define IFX_PSI5_NFIOV_NFI0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI10 */
+#define IFX_PSI5_NFIOV_NFI10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI10 */
+#define IFX_PSI5_NFIOV_NFI10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI10 */
+#define IFX_PSI5_NFIOV_NFI10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI11 */
+#define IFX_PSI5_NFIOV_NFI11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI11 */
+#define IFX_PSI5_NFIOV_NFI11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI11 */
+#define IFX_PSI5_NFIOV_NFI11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI12 */
+#define IFX_PSI5_NFIOV_NFI12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI12 */
+#define IFX_PSI5_NFIOV_NFI12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI12 */
+#define IFX_PSI5_NFIOV_NFI12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI13 */
+#define IFX_PSI5_NFIOV_NFI13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI13 */
+#define IFX_PSI5_NFIOV_NFI13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI13 */
+#define IFX_PSI5_NFIOV_NFI13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI14 */
+#define IFX_PSI5_NFIOV_NFI14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI14 */
+#define IFX_PSI5_NFIOV_NFI14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI14 */
+#define IFX_PSI5_NFIOV_NFI14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI15 */
+#define IFX_PSI5_NFIOV_NFI15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI15 */
+#define IFX_PSI5_NFIOV_NFI15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI15 */
+#define IFX_PSI5_NFIOV_NFI15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI16 */
+#define IFX_PSI5_NFIOV_NFI16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI16 */
+#define IFX_PSI5_NFIOV_NFI16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI16 */
+#define IFX_PSI5_NFIOV_NFI16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI17 */
+#define IFX_PSI5_NFIOV_NFI17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI17 */
+#define IFX_PSI5_NFIOV_NFI17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI17 */
+#define IFX_PSI5_NFIOV_NFI17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI18 */
+#define IFX_PSI5_NFIOV_NFI18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI18 */
+#define IFX_PSI5_NFIOV_NFI18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI18 */
+#define IFX_PSI5_NFIOV_NFI18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI19 */
+#define IFX_PSI5_NFIOV_NFI19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI19 */
+#define IFX_PSI5_NFIOV_NFI19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI19 */
+#define IFX_PSI5_NFIOV_NFI19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI1 */
+#define IFX_PSI5_NFIOV_NFI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI1 */
+#define IFX_PSI5_NFIOV_NFI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI1 */
+#define IFX_PSI5_NFIOV_NFI1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI20 */
+#define IFX_PSI5_NFIOV_NFI20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI20 */
+#define IFX_PSI5_NFIOV_NFI20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI20 */
+#define IFX_PSI5_NFIOV_NFI20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI21 */
+#define IFX_PSI5_NFIOV_NFI21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI21 */
+#define IFX_PSI5_NFIOV_NFI21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI21 */
+#define IFX_PSI5_NFIOV_NFI21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI22 */
+#define IFX_PSI5_NFIOV_NFI22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI22 */
+#define IFX_PSI5_NFIOV_NFI22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI22 */
+#define IFX_PSI5_NFIOV_NFI22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI23 */
+#define IFX_PSI5_NFIOV_NFI23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI23 */
+#define IFX_PSI5_NFIOV_NFI23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI23 */
+#define IFX_PSI5_NFIOV_NFI23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI24 */
+#define IFX_PSI5_NFIOV_NFI24_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI24 */
+#define IFX_PSI5_NFIOV_NFI24_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI24 */
+#define IFX_PSI5_NFIOV_NFI24_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI25 */
+#define IFX_PSI5_NFIOV_NFI25_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI25 */
+#define IFX_PSI5_NFIOV_NFI25_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI25 */
+#define IFX_PSI5_NFIOV_NFI25_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI26 */
+#define IFX_PSI5_NFIOV_NFI26_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI26 */
+#define IFX_PSI5_NFIOV_NFI26_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI26 */
+#define IFX_PSI5_NFIOV_NFI26_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI27 */
+#define IFX_PSI5_NFIOV_NFI27_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI27 */
+#define IFX_PSI5_NFIOV_NFI27_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI27 */
+#define IFX_PSI5_NFIOV_NFI27_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI28 */
+#define IFX_PSI5_NFIOV_NFI28_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI28 */
+#define IFX_PSI5_NFIOV_NFI28_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI28 */
+#define IFX_PSI5_NFIOV_NFI28_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI29 */
+#define IFX_PSI5_NFIOV_NFI29_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI29 */
+#define IFX_PSI5_NFIOV_NFI29_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI29 */
+#define IFX_PSI5_NFIOV_NFI29_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI2 */
+#define IFX_PSI5_NFIOV_NFI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI2 */
+#define IFX_PSI5_NFIOV_NFI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI2 */
+#define IFX_PSI5_NFIOV_NFI2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI30 */
+#define IFX_PSI5_NFIOV_NFI30_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI30 */
+#define IFX_PSI5_NFIOV_NFI30_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI30 */
+#define IFX_PSI5_NFIOV_NFI30_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI31 */
+#define IFX_PSI5_NFIOV_NFI31_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI31 */
+#define IFX_PSI5_NFIOV_NFI31_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI31 */
+#define IFX_PSI5_NFIOV_NFI31_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI3 */
+#define IFX_PSI5_NFIOV_NFI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI3 */
+#define IFX_PSI5_NFIOV_NFI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI3 */
+#define IFX_PSI5_NFIOV_NFI3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI4 */
+#define IFX_PSI5_NFIOV_NFI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI4 */
+#define IFX_PSI5_NFIOV_NFI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI4 */
+#define IFX_PSI5_NFIOV_NFI4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI5 */
+#define IFX_PSI5_NFIOV_NFI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI5 */
+#define IFX_PSI5_NFIOV_NFI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI5 */
+#define IFX_PSI5_NFIOV_NFI5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI6 */
+#define IFX_PSI5_NFIOV_NFI6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI6 */
+#define IFX_PSI5_NFIOV_NFI6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI6 */
+#define IFX_PSI5_NFIOV_NFI6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI7 */
+#define IFX_PSI5_NFIOV_NFI7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI7 */
+#define IFX_PSI5_NFIOV_NFI7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI7 */
+#define IFX_PSI5_NFIOV_NFI7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI8 */
+#define IFX_PSI5_NFIOV_NFI8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI8 */
+#define IFX_PSI5_NFIOV_NFI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI8 */
+#define IFX_PSI5_NFIOV_NFI8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_NFIOV_Bits.NFI9 */
+#define IFX_PSI5_NFIOV_NFI9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFIOV_Bits.NFI9 */
+#define IFX_PSI5_NFIOV_NFI9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFIOV_Bits.NFI9 */
+#define IFX_PSI5_NFIOV_NFI9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI0 */
+#define IFX_PSI5_NFISET_NFI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI0 */
+#define IFX_PSI5_NFISET_NFI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI0 */
+#define IFX_PSI5_NFISET_NFI0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI10 */
+#define IFX_PSI5_NFISET_NFI10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI10 */
+#define IFX_PSI5_NFISET_NFI10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI10 */
+#define IFX_PSI5_NFISET_NFI10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI11 */
+#define IFX_PSI5_NFISET_NFI11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI11 */
+#define IFX_PSI5_NFISET_NFI11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI11 */
+#define IFX_PSI5_NFISET_NFI11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI12 */
+#define IFX_PSI5_NFISET_NFI12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI12 */
+#define IFX_PSI5_NFISET_NFI12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI12 */
+#define IFX_PSI5_NFISET_NFI12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI13 */
+#define IFX_PSI5_NFISET_NFI13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI13 */
+#define IFX_PSI5_NFISET_NFI13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI13 */
+#define IFX_PSI5_NFISET_NFI13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI14 */
+#define IFX_PSI5_NFISET_NFI14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI14 */
+#define IFX_PSI5_NFISET_NFI14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI14 */
+#define IFX_PSI5_NFISET_NFI14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI15 */
+#define IFX_PSI5_NFISET_NFI15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI15 */
+#define IFX_PSI5_NFISET_NFI15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI15 */
+#define IFX_PSI5_NFISET_NFI15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI16 */
+#define IFX_PSI5_NFISET_NFI16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI16 */
+#define IFX_PSI5_NFISET_NFI16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI16 */
+#define IFX_PSI5_NFISET_NFI16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI17 */
+#define IFX_PSI5_NFISET_NFI17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI17 */
+#define IFX_PSI5_NFISET_NFI17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI17 */
+#define IFX_PSI5_NFISET_NFI17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI18 */
+#define IFX_PSI5_NFISET_NFI18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI18 */
+#define IFX_PSI5_NFISET_NFI18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI18 */
+#define IFX_PSI5_NFISET_NFI18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI19 */
+#define IFX_PSI5_NFISET_NFI19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI19 */
+#define IFX_PSI5_NFISET_NFI19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI19 */
+#define IFX_PSI5_NFISET_NFI19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI1 */
+#define IFX_PSI5_NFISET_NFI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI1 */
+#define IFX_PSI5_NFISET_NFI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI1 */
+#define IFX_PSI5_NFISET_NFI1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI20 */
+#define IFX_PSI5_NFISET_NFI20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI20 */
+#define IFX_PSI5_NFISET_NFI20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI20 */
+#define IFX_PSI5_NFISET_NFI20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI21 */
+#define IFX_PSI5_NFISET_NFI21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI21 */
+#define IFX_PSI5_NFISET_NFI21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI21 */
+#define IFX_PSI5_NFISET_NFI21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI22 */
+#define IFX_PSI5_NFISET_NFI22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI22 */
+#define IFX_PSI5_NFISET_NFI22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI22 */
+#define IFX_PSI5_NFISET_NFI22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI23 */
+#define IFX_PSI5_NFISET_NFI23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI23 */
+#define IFX_PSI5_NFISET_NFI23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI23 */
+#define IFX_PSI5_NFISET_NFI23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI24 */
+#define IFX_PSI5_NFISET_NFI24_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI24 */
+#define IFX_PSI5_NFISET_NFI24_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI24 */
+#define IFX_PSI5_NFISET_NFI24_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI25 */
+#define IFX_PSI5_NFISET_NFI25_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI25 */
+#define IFX_PSI5_NFISET_NFI25_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI25 */
+#define IFX_PSI5_NFISET_NFI25_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI26 */
+#define IFX_PSI5_NFISET_NFI26_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI26 */
+#define IFX_PSI5_NFISET_NFI26_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI26 */
+#define IFX_PSI5_NFISET_NFI26_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI27 */
+#define IFX_PSI5_NFISET_NFI27_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI27 */
+#define IFX_PSI5_NFISET_NFI27_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI27 */
+#define IFX_PSI5_NFISET_NFI27_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI28 */
+#define IFX_PSI5_NFISET_NFI28_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI28 */
+#define IFX_PSI5_NFISET_NFI28_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI28 */
+#define IFX_PSI5_NFISET_NFI28_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI29 */
+#define IFX_PSI5_NFISET_NFI29_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI29 */
+#define IFX_PSI5_NFISET_NFI29_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI29 */
+#define IFX_PSI5_NFISET_NFI29_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI2 */
+#define IFX_PSI5_NFISET_NFI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI2 */
+#define IFX_PSI5_NFISET_NFI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI2 */
+#define IFX_PSI5_NFISET_NFI2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI30 */
+#define IFX_PSI5_NFISET_NFI30_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI30 */
+#define IFX_PSI5_NFISET_NFI30_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI30 */
+#define IFX_PSI5_NFISET_NFI30_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI31 */
+#define IFX_PSI5_NFISET_NFI31_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI31 */
+#define IFX_PSI5_NFISET_NFI31_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI31 */
+#define IFX_PSI5_NFISET_NFI31_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI3 */
+#define IFX_PSI5_NFISET_NFI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI3 */
+#define IFX_PSI5_NFISET_NFI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI3 */
+#define IFX_PSI5_NFISET_NFI3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI4 */
+#define IFX_PSI5_NFISET_NFI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI4 */
+#define IFX_PSI5_NFISET_NFI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI4 */
+#define IFX_PSI5_NFISET_NFI4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI5 */
+#define IFX_PSI5_NFISET_NFI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI5 */
+#define IFX_PSI5_NFISET_NFI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI5 */
+#define IFX_PSI5_NFISET_NFI5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI6 */
+#define IFX_PSI5_NFISET_NFI6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI6 */
+#define IFX_PSI5_NFISET_NFI6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI6 */
+#define IFX_PSI5_NFISET_NFI6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI7 */
+#define IFX_PSI5_NFISET_NFI7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI7 */
+#define IFX_PSI5_NFISET_NFI7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI7 */
+#define IFX_PSI5_NFISET_NFI7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI8 */
+#define IFX_PSI5_NFISET_NFI8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI8 */
+#define IFX_PSI5_NFISET_NFI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI8 */
+#define IFX_PSI5_NFISET_NFI8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_NFISET_Bits.NFI9 */
+#define IFX_PSI5_NFISET_NFI9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_NFISET_Bits.NFI9 */
+#define IFX_PSI5_NFISET_NFI9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_NFISET_Bits.NFI9 */
+#define IFX_PSI5_NFISET_NFI9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_OCS_Bits.SUS */
+#define IFX_PSI5_OCS_SUS_LEN (4u)
+
+/** \brief Mask for Ifx_PSI5_OCS_Bits.SUS */
+#define IFX_PSI5_OCS_SUS_MSK (0xfu)
+
+/** \brief Offset for Ifx_PSI5_OCS_Bits.SUS */
+#define IFX_PSI5_OCS_SUS_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_OCS_Bits.SUS_P */
+#define IFX_PSI5_OCS_SUS_P_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_OCS_Bits.SUS_P */
+#define IFX_PSI5_OCS_SUS_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_OCS_Bits.SUS_P */
+#define IFX_PSI5_OCS_SUS_P_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_OCS_Bits.SUSSTA */
+#define IFX_PSI5_OCS_SUSSTA_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_OCS_Bits.SUSSTA */
+#define IFX_PSI5_OCS_SUSSTA_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_OCS_Bits.SUSSTA */
+#define IFX_PSI5_OCS_SUSSTA_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_RDF_Bits.RD */
+#define IFX_PSI5_RDF_RD_LEN (32u)
+
+/** \brief Mask for Ifx_PSI5_RDF_Bits.RD */
+#define IFX_PSI5_RDF_RD_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_PSI5_RDF_Bits.RD */
+#define IFX_PSI5_RDF_RD_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI0 */
+#define IFX_PSI5_RDICLR_RDI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI0 */
+#define IFX_PSI5_RDICLR_RDI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI0 */
+#define IFX_PSI5_RDICLR_RDI0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI10 */
+#define IFX_PSI5_RDICLR_RDI10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI10 */
+#define IFX_PSI5_RDICLR_RDI10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI10 */
+#define IFX_PSI5_RDICLR_RDI10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI11 */
+#define IFX_PSI5_RDICLR_RDI11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI11 */
+#define IFX_PSI5_RDICLR_RDI11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI11 */
+#define IFX_PSI5_RDICLR_RDI11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI12 */
+#define IFX_PSI5_RDICLR_RDI12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI12 */
+#define IFX_PSI5_RDICLR_RDI12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI12 */
+#define IFX_PSI5_RDICLR_RDI12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI13 */
+#define IFX_PSI5_RDICLR_RDI13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI13 */
+#define IFX_PSI5_RDICLR_RDI13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI13 */
+#define IFX_PSI5_RDICLR_RDI13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI14 */
+#define IFX_PSI5_RDICLR_RDI14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI14 */
+#define IFX_PSI5_RDICLR_RDI14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI14 */
+#define IFX_PSI5_RDICLR_RDI14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI15 */
+#define IFX_PSI5_RDICLR_RDI15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI15 */
+#define IFX_PSI5_RDICLR_RDI15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI15 */
+#define IFX_PSI5_RDICLR_RDI15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI16 */
+#define IFX_PSI5_RDICLR_RDI16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI16 */
+#define IFX_PSI5_RDICLR_RDI16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI16 */
+#define IFX_PSI5_RDICLR_RDI16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI17 */
+#define IFX_PSI5_RDICLR_RDI17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI17 */
+#define IFX_PSI5_RDICLR_RDI17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI17 */
+#define IFX_PSI5_RDICLR_RDI17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI18 */
+#define IFX_PSI5_RDICLR_RDI18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI18 */
+#define IFX_PSI5_RDICLR_RDI18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI18 */
+#define IFX_PSI5_RDICLR_RDI18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI19 */
+#define IFX_PSI5_RDICLR_RDI19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI19 */
+#define IFX_PSI5_RDICLR_RDI19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI19 */
+#define IFX_PSI5_RDICLR_RDI19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI1 */
+#define IFX_PSI5_RDICLR_RDI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI1 */
+#define IFX_PSI5_RDICLR_RDI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI1 */
+#define IFX_PSI5_RDICLR_RDI1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI20 */
+#define IFX_PSI5_RDICLR_RDI20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI20 */
+#define IFX_PSI5_RDICLR_RDI20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI20 */
+#define IFX_PSI5_RDICLR_RDI20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI21 */
+#define IFX_PSI5_RDICLR_RDI21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI21 */
+#define IFX_PSI5_RDICLR_RDI21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI21 */
+#define IFX_PSI5_RDICLR_RDI21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI22 */
+#define IFX_PSI5_RDICLR_RDI22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI22 */
+#define IFX_PSI5_RDICLR_RDI22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI22 */
+#define IFX_PSI5_RDICLR_RDI22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI23 */
+#define IFX_PSI5_RDICLR_RDI23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI23 */
+#define IFX_PSI5_RDICLR_RDI23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI23 */
+#define IFX_PSI5_RDICLR_RDI23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI24 */
+#define IFX_PSI5_RDICLR_RDI24_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI24 */
+#define IFX_PSI5_RDICLR_RDI24_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI24 */
+#define IFX_PSI5_RDICLR_RDI24_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI25 */
+#define IFX_PSI5_RDICLR_RDI25_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI25 */
+#define IFX_PSI5_RDICLR_RDI25_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI25 */
+#define IFX_PSI5_RDICLR_RDI25_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI26 */
+#define IFX_PSI5_RDICLR_RDI26_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI26 */
+#define IFX_PSI5_RDICLR_RDI26_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI26 */
+#define IFX_PSI5_RDICLR_RDI26_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI27 */
+#define IFX_PSI5_RDICLR_RDI27_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI27 */
+#define IFX_PSI5_RDICLR_RDI27_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI27 */
+#define IFX_PSI5_RDICLR_RDI27_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI28 */
+#define IFX_PSI5_RDICLR_RDI28_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI28 */
+#define IFX_PSI5_RDICLR_RDI28_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI28 */
+#define IFX_PSI5_RDICLR_RDI28_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI29 */
+#define IFX_PSI5_RDICLR_RDI29_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI29 */
+#define IFX_PSI5_RDICLR_RDI29_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI29 */
+#define IFX_PSI5_RDICLR_RDI29_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI2 */
+#define IFX_PSI5_RDICLR_RDI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI2 */
+#define IFX_PSI5_RDICLR_RDI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI2 */
+#define IFX_PSI5_RDICLR_RDI2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI30 */
+#define IFX_PSI5_RDICLR_RDI30_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI30 */
+#define IFX_PSI5_RDICLR_RDI30_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI30 */
+#define IFX_PSI5_RDICLR_RDI30_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI31 */
+#define IFX_PSI5_RDICLR_RDI31_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI31 */
+#define IFX_PSI5_RDICLR_RDI31_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI31 */
+#define IFX_PSI5_RDICLR_RDI31_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI3 */
+#define IFX_PSI5_RDICLR_RDI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI3 */
+#define IFX_PSI5_RDICLR_RDI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI3 */
+#define IFX_PSI5_RDICLR_RDI3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI4 */
+#define IFX_PSI5_RDICLR_RDI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI4 */
+#define IFX_PSI5_RDICLR_RDI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI4 */
+#define IFX_PSI5_RDICLR_RDI4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI5 */
+#define IFX_PSI5_RDICLR_RDI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI5 */
+#define IFX_PSI5_RDICLR_RDI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI5 */
+#define IFX_PSI5_RDICLR_RDI5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI6 */
+#define IFX_PSI5_RDICLR_RDI6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI6 */
+#define IFX_PSI5_RDICLR_RDI6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI6 */
+#define IFX_PSI5_RDICLR_RDI6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI7 */
+#define IFX_PSI5_RDICLR_RDI7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI7 */
+#define IFX_PSI5_RDICLR_RDI7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI7 */
+#define IFX_PSI5_RDICLR_RDI7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI8 */
+#define IFX_PSI5_RDICLR_RDI8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI8 */
+#define IFX_PSI5_RDICLR_RDI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI8 */
+#define IFX_PSI5_RDICLR_RDI8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_RDICLR_Bits.RDI9 */
+#define IFX_PSI5_RDICLR_RDI9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDICLR_Bits.RDI9 */
+#define IFX_PSI5_RDICLR_RDI9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDICLR_Bits.RDI9 */
+#define IFX_PSI5_RDICLR_RDI9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI0 */
+#define IFX_PSI5_RDIOV_RDI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI0 */
+#define IFX_PSI5_RDIOV_RDI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI0 */
+#define IFX_PSI5_RDIOV_RDI0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI10 */
+#define IFX_PSI5_RDIOV_RDI10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI10 */
+#define IFX_PSI5_RDIOV_RDI10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI10 */
+#define IFX_PSI5_RDIOV_RDI10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI11 */
+#define IFX_PSI5_RDIOV_RDI11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI11 */
+#define IFX_PSI5_RDIOV_RDI11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI11 */
+#define IFX_PSI5_RDIOV_RDI11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI12 */
+#define IFX_PSI5_RDIOV_RDI12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI12 */
+#define IFX_PSI5_RDIOV_RDI12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI12 */
+#define IFX_PSI5_RDIOV_RDI12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI13 */
+#define IFX_PSI5_RDIOV_RDI13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI13 */
+#define IFX_PSI5_RDIOV_RDI13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI13 */
+#define IFX_PSI5_RDIOV_RDI13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI14 */
+#define IFX_PSI5_RDIOV_RDI14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI14 */
+#define IFX_PSI5_RDIOV_RDI14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI14 */
+#define IFX_PSI5_RDIOV_RDI14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI15 */
+#define IFX_PSI5_RDIOV_RDI15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI15 */
+#define IFX_PSI5_RDIOV_RDI15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI15 */
+#define IFX_PSI5_RDIOV_RDI15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI16 */
+#define IFX_PSI5_RDIOV_RDI16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI16 */
+#define IFX_PSI5_RDIOV_RDI16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI16 */
+#define IFX_PSI5_RDIOV_RDI16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI17 */
+#define IFX_PSI5_RDIOV_RDI17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI17 */
+#define IFX_PSI5_RDIOV_RDI17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI17 */
+#define IFX_PSI5_RDIOV_RDI17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI18 */
+#define IFX_PSI5_RDIOV_RDI18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI18 */
+#define IFX_PSI5_RDIOV_RDI18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI18 */
+#define IFX_PSI5_RDIOV_RDI18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI19 */
+#define IFX_PSI5_RDIOV_RDI19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI19 */
+#define IFX_PSI5_RDIOV_RDI19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI19 */
+#define IFX_PSI5_RDIOV_RDI19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI1 */
+#define IFX_PSI5_RDIOV_RDI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI1 */
+#define IFX_PSI5_RDIOV_RDI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI1 */
+#define IFX_PSI5_RDIOV_RDI1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI20 */
+#define IFX_PSI5_RDIOV_RDI20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI20 */
+#define IFX_PSI5_RDIOV_RDI20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI20 */
+#define IFX_PSI5_RDIOV_RDI20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI21 */
+#define IFX_PSI5_RDIOV_RDI21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI21 */
+#define IFX_PSI5_RDIOV_RDI21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI21 */
+#define IFX_PSI5_RDIOV_RDI21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI22 */
+#define IFX_PSI5_RDIOV_RDI22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI22 */
+#define IFX_PSI5_RDIOV_RDI22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI22 */
+#define IFX_PSI5_RDIOV_RDI22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI23 */
+#define IFX_PSI5_RDIOV_RDI23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI23 */
+#define IFX_PSI5_RDIOV_RDI23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI23 */
+#define IFX_PSI5_RDIOV_RDI23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI24 */
+#define IFX_PSI5_RDIOV_RDI24_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI24 */
+#define IFX_PSI5_RDIOV_RDI24_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI24 */
+#define IFX_PSI5_RDIOV_RDI24_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI25 */
+#define IFX_PSI5_RDIOV_RDI25_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI25 */
+#define IFX_PSI5_RDIOV_RDI25_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI25 */
+#define IFX_PSI5_RDIOV_RDI25_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI26 */
+#define IFX_PSI5_RDIOV_RDI26_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI26 */
+#define IFX_PSI5_RDIOV_RDI26_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI26 */
+#define IFX_PSI5_RDIOV_RDI26_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI27 */
+#define IFX_PSI5_RDIOV_RDI27_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI27 */
+#define IFX_PSI5_RDIOV_RDI27_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI27 */
+#define IFX_PSI5_RDIOV_RDI27_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI28 */
+#define IFX_PSI5_RDIOV_RDI28_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI28 */
+#define IFX_PSI5_RDIOV_RDI28_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI28 */
+#define IFX_PSI5_RDIOV_RDI28_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI29 */
+#define IFX_PSI5_RDIOV_RDI29_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI29 */
+#define IFX_PSI5_RDIOV_RDI29_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI29 */
+#define IFX_PSI5_RDIOV_RDI29_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI2 */
+#define IFX_PSI5_RDIOV_RDI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI2 */
+#define IFX_PSI5_RDIOV_RDI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI2 */
+#define IFX_PSI5_RDIOV_RDI2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI30 */
+#define IFX_PSI5_RDIOV_RDI30_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI30 */
+#define IFX_PSI5_RDIOV_RDI30_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI30 */
+#define IFX_PSI5_RDIOV_RDI30_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI31 */
+#define IFX_PSI5_RDIOV_RDI31_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI31 */
+#define IFX_PSI5_RDIOV_RDI31_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI31 */
+#define IFX_PSI5_RDIOV_RDI31_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI3 */
+#define IFX_PSI5_RDIOV_RDI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI3 */
+#define IFX_PSI5_RDIOV_RDI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI3 */
+#define IFX_PSI5_RDIOV_RDI3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI4 */
+#define IFX_PSI5_RDIOV_RDI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI4 */
+#define IFX_PSI5_RDIOV_RDI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI4 */
+#define IFX_PSI5_RDIOV_RDI4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI5 */
+#define IFX_PSI5_RDIOV_RDI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI5 */
+#define IFX_PSI5_RDIOV_RDI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI5 */
+#define IFX_PSI5_RDIOV_RDI5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI6 */
+#define IFX_PSI5_RDIOV_RDI6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI6 */
+#define IFX_PSI5_RDIOV_RDI6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI6 */
+#define IFX_PSI5_RDIOV_RDI6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI7 */
+#define IFX_PSI5_RDIOV_RDI7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI7 */
+#define IFX_PSI5_RDIOV_RDI7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI7 */
+#define IFX_PSI5_RDIOV_RDI7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI8 */
+#define IFX_PSI5_RDIOV_RDI8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI8 */
+#define IFX_PSI5_RDIOV_RDI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI8 */
+#define IFX_PSI5_RDIOV_RDI8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_RDIOV_Bits.RDI9 */
+#define IFX_PSI5_RDIOV_RDI9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDIOV_Bits.RDI9 */
+#define IFX_PSI5_RDIOV_RDI9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDIOV_Bits.RDI9 */
+#define IFX_PSI5_RDIOV_RDI9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI0 */
+#define IFX_PSI5_RDISET_RDI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI0 */
+#define IFX_PSI5_RDISET_RDI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI0 */
+#define IFX_PSI5_RDISET_RDI0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI10 */
+#define IFX_PSI5_RDISET_RDI10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI10 */
+#define IFX_PSI5_RDISET_RDI10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI10 */
+#define IFX_PSI5_RDISET_RDI10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI11 */
+#define IFX_PSI5_RDISET_RDI11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI11 */
+#define IFX_PSI5_RDISET_RDI11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI11 */
+#define IFX_PSI5_RDISET_RDI11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI12 */
+#define IFX_PSI5_RDISET_RDI12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI12 */
+#define IFX_PSI5_RDISET_RDI12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI12 */
+#define IFX_PSI5_RDISET_RDI12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI13 */
+#define IFX_PSI5_RDISET_RDI13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI13 */
+#define IFX_PSI5_RDISET_RDI13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI13 */
+#define IFX_PSI5_RDISET_RDI13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI14 */
+#define IFX_PSI5_RDISET_RDI14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI14 */
+#define IFX_PSI5_RDISET_RDI14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI14 */
+#define IFX_PSI5_RDISET_RDI14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI15 */
+#define IFX_PSI5_RDISET_RDI15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI15 */
+#define IFX_PSI5_RDISET_RDI15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI15 */
+#define IFX_PSI5_RDISET_RDI15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI16 */
+#define IFX_PSI5_RDISET_RDI16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI16 */
+#define IFX_PSI5_RDISET_RDI16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI16 */
+#define IFX_PSI5_RDISET_RDI16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI17 */
+#define IFX_PSI5_RDISET_RDI17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI17 */
+#define IFX_PSI5_RDISET_RDI17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI17 */
+#define IFX_PSI5_RDISET_RDI17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI18 */
+#define IFX_PSI5_RDISET_RDI18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI18 */
+#define IFX_PSI5_RDISET_RDI18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI18 */
+#define IFX_PSI5_RDISET_RDI18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI19 */
+#define IFX_PSI5_RDISET_RDI19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI19 */
+#define IFX_PSI5_RDISET_RDI19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI19 */
+#define IFX_PSI5_RDISET_RDI19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI1 */
+#define IFX_PSI5_RDISET_RDI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI1 */
+#define IFX_PSI5_RDISET_RDI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI1 */
+#define IFX_PSI5_RDISET_RDI1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI20 */
+#define IFX_PSI5_RDISET_RDI20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI20 */
+#define IFX_PSI5_RDISET_RDI20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI20 */
+#define IFX_PSI5_RDISET_RDI20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI21 */
+#define IFX_PSI5_RDISET_RDI21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI21 */
+#define IFX_PSI5_RDISET_RDI21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI21 */
+#define IFX_PSI5_RDISET_RDI21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI22 */
+#define IFX_PSI5_RDISET_RDI22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI22 */
+#define IFX_PSI5_RDISET_RDI22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI22 */
+#define IFX_PSI5_RDISET_RDI22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI23 */
+#define IFX_PSI5_RDISET_RDI23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI23 */
+#define IFX_PSI5_RDISET_RDI23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI23 */
+#define IFX_PSI5_RDISET_RDI23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI24 */
+#define IFX_PSI5_RDISET_RDI24_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI24 */
+#define IFX_PSI5_RDISET_RDI24_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI24 */
+#define IFX_PSI5_RDISET_RDI24_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI25 */
+#define IFX_PSI5_RDISET_RDI25_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI25 */
+#define IFX_PSI5_RDISET_RDI25_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI25 */
+#define IFX_PSI5_RDISET_RDI25_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI26 */
+#define IFX_PSI5_RDISET_RDI26_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI26 */
+#define IFX_PSI5_RDISET_RDI26_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI26 */
+#define IFX_PSI5_RDISET_RDI26_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI27 */
+#define IFX_PSI5_RDISET_RDI27_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI27 */
+#define IFX_PSI5_RDISET_RDI27_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI27 */
+#define IFX_PSI5_RDISET_RDI27_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI28 */
+#define IFX_PSI5_RDISET_RDI28_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI28 */
+#define IFX_PSI5_RDISET_RDI28_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI28 */
+#define IFX_PSI5_RDISET_RDI28_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI29 */
+#define IFX_PSI5_RDISET_RDI29_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI29 */
+#define IFX_PSI5_RDISET_RDI29_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI29 */
+#define IFX_PSI5_RDISET_RDI29_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI2 */
+#define IFX_PSI5_RDISET_RDI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI2 */
+#define IFX_PSI5_RDISET_RDI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI2 */
+#define IFX_PSI5_RDISET_RDI2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI30 */
+#define IFX_PSI5_RDISET_RDI30_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI30 */
+#define IFX_PSI5_RDISET_RDI30_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI30 */
+#define IFX_PSI5_RDISET_RDI30_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI31 */
+#define IFX_PSI5_RDISET_RDI31_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI31 */
+#define IFX_PSI5_RDISET_RDI31_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI31 */
+#define IFX_PSI5_RDISET_RDI31_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI3 */
+#define IFX_PSI5_RDISET_RDI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI3 */
+#define IFX_PSI5_RDISET_RDI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI3 */
+#define IFX_PSI5_RDISET_RDI3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI4 */
+#define IFX_PSI5_RDISET_RDI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI4 */
+#define IFX_PSI5_RDISET_RDI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI4 */
+#define IFX_PSI5_RDISET_RDI4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI5 */
+#define IFX_PSI5_RDISET_RDI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI5 */
+#define IFX_PSI5_RDISET_RDI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI5 */
+#define IFX_PSI5_RDISET_RDI5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI6 */
+#define IFX_PSI5_RDISET_RDI6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI6 */
+#define IFX_PSI5_RDISET_RDI6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI6 */
+#define IFX_PSI5_RDISET_RDI6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI7 */
+#define IFX_PSI5_RDISET_RDI7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI7 */
+#define IFX_PSI5_RDISET_RDI7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI7 */
+#define IFX_PSI5_RDISET_RDI7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI8 */
+#define IFX_PSI5_RDISET_RDI8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI8 */
+#define IFX_PSI5_RDISET_RDI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI8 */
+#define IFX_PSI5_RDISET_RDI8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_RDISET_Bits.RDI9 */
+#define IFX_PSI5_RDISET_RDI9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDISET_Bits.RDI9 */
+#define IFX_PSI5_RDISET_RDI9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDISET_Bits.RDI9 */
+#define IFX_PSI5_RDISET_RDI9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_RDM_H_Bits.MEI */
+#define IFX_PSI5_RDM_H_MEI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDM_H_Bits.MEI */
+#define IFX_PSI5_RDM_H_MEI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDM_H_Bits.MEI */
+#define IFX_PSI5_RDM_H_MEI_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_RDM_H_Bits.NBI */
+#define IFX_PSI5_RDM_H_NBI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDM_H_Bits.NBI */
+#define IFX_PSI5_RDM_H_NBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDM_H_Bits.NBI */
+#define IFX_PSI5_RDM_H_NBI_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_RDM_H_Bits.NFI */
+#define IFX_PSI5_RDM_H_NFI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDM_H_Bits.NFI */
+#define IFX_PSI5_RDM_H_NFI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDM_H_Bits.NFI */
+#define IFX_PSI5_RDM_H_NFI_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_RDM_H_Bits.RMI */
+#define IFX_PSI5_RDM_H_RMI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDM_H_Bits.RMI */
+#define IFX_PSI5_RDM_H_RMI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDM_H_Bits.RMI */
+#define IFX_PSI5_RDM_H_RMI_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_RDM_H_Bits.SC */
+#define IFX_PSI5_RDM_H_SC_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5_RDM_H_Bits.SC */
+#define IFX_PSI5_RDM_H_SC_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5_RDM_H_Bits.SC */
+#define IFX_PSI5_RDM_H_SC_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_RDM_H_Bits.TEI */
+#define IFX_PSI5_RDM_H_TEI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDM_H_Bits.TEI */
+#define IFX_PSI5_RDM_H_TEI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDM_H_Bits.TEI */
+#define IFX_PSI5_RDM_H_TEI_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_RDM_H_Bits.TS */
+#define IFX_PSI5_RDM_H_TS_LEN (24u)
+
+/** \brief Mask for Ifx_PSI5_RDM_H_Bits.TS */
+#define IFX_PSI5_RDM_H_TS_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_PSI5_RDM_H_Bits.TS */
+#define IFX_PSI5_RDM_H_TS_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_RDM_L_Bits.CRC */
+#define IFX_PSI5_RDM_L_CRC_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5_RDM_L_Bits.CRC */
+#define IFX_PSI5_RDM_L_CRC_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5_RDM_L_Bits.CRC */
+#define IFX_PSI5_RDM_L_CRC_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_RDM_L_Bits.CRCI */
+#define IFX_PSI5_RDM_L_CRCI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RDM_L_Bits.CRCI */
+#define IFX_PSI5_RDM_L_CRCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RDM_L_Bits.CRCI */
+#define IFX_PSI5_RDM_L_CRCI_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_RDM_L_Bits.RD */
+#define IFX_PSI5_RDM_L_RD_LEN (28u)
+
+/** \brief Mask for Ifx_PSI5_RDM_L_Bits.RD */
+#define IFX_PSI5_RDM_L_RD_MSK (0xfffffffu)
+
+/** \brief Offset for Ifx_PSI5_RDM_L_Bits.RD */
+#define IFX_PSI5_RDM_L_RD_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_RFC_Bits.FLU */
+#define IFX_PSI5_RFC_FLU_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RFC_Bits.FLU */
+#define IFX_PSI5_RFC_FLU_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RFC_Bits.FLU */
+#define IFX_PSI5_RFC_FLU_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_RFC_Bits.FRQ */
+#define IFX_PSI5_RFC_FRQ_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RFC_Bits.FRQ */
+#define IFX_PSI5_RFC_FRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RFC_Bits.FRQ */
+#define IFX_PSI5_RFC_FRQ_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_RFC_Bits.FWL */
+#define IFX_PSI5_RFC_FWL_LEN (5u)
+
+/** \brief Mask for Ifx_PSI5_RFC_Bits.FWL */
+#define IFX_PSI5_RFC_FWL_MSK (0x1fu)
+
+/** \brief Offset for Ifx_PSI5_RFC_Bits.FWL */
+#define IFX_PSI5_RFC_FWL_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_RFC_Bits.REP */
+#define IFX_PSI5_RFC_REP_LEN (6u)
+
+/** \brief Mask for Ifx_PSI5_RFC_Bits.REP */
+#define IFX_PSI5_RFC_REP_MSK (0x3fu)
+
+/** \brief Offset for Ifx_PSI5_RFC_Bits.REP */
+#define IFX_PSI5_RFC_REP_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_RFC_Bits.WRAP */
+#define IFX_PSI5_RFC_WRAP_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RFC_Bits.WRAP */
+#define IFX_PSI5_RFC_WRAP_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RFC_Bits.WRAP */
+#define IFX_PSI5_RFC_WRAP_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_RFC_Bits.WRP */
+#define IFX_PSI5_RFC_WRP_LEN (6u)
+
+/** \brief Mask for Ifx_PSI5_RFC_Bits.WRP */
+#define IFX_PSI5_RFC_WRP_MSK (0x3fu)
+
+/** \brief Offset for Ifx_PSI5_RFC_Bits.WRP */
+#define IFX_PSI5_RFC_WRP_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI0 */
+#define IFX_PSI5_RMICLR_RMI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI0 */
+#define IFX_PSI5_RMICLR_RMI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI0 */
+#define IFX_PSI5_RMICLR_RMI0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI10 */
+#define IFX_PSI5_RMICLR_RMI10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI10 */
+#define IFX_PSI5_RMICLR_RMI10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI10 */
+#define IFX_PSI5_RMICLR_RMI10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI11 */
+#define IFX_PSI5_RMICLR_RMI11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI11 */
+#define IFX_PSI5_RMICLR_RMI11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI11 */
+#define IFX_PSI5_RMICLR_RMI11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI12 */
+#define IFX_PSI5_RMICLR_RMI12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI12 */
+#define IFX_PSI5_RMICLR_RMI12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI12 */
+#define IFX_PSI5_RMICLR_RMI12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI13 */
+#define IFX_PSI5_RMICLR_RMI13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI13 */
+#define IFX_PSI5_RMICLR_RMI13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI13 */
+#define IFX_PSI5_RMICLR_RMI13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI14 */
+#define IFX_PSI5_RMICLR_RMI14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI14 */
+#define IFX_PSI5_RMICLR_RMI14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI14 */
+#define IFX_PSI5_RMICLR_RMI14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI15 */
+#define IFX_PSI5_RMICLR_RMI15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI15 */
+#define IFX_PSI5_RMICLR_RMI15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI15 */
+#define IFX_PSI5_RMICLR_RMI15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI16 */
+#define IFX_PSI5_RMICLR_RMI16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI16 */
+#define IFX_PSI5_RMICLR_RMI16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI16 */
+#define IFX_PSI5_RMICLR_RMI16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI17 */
+#define IFX_PSI5_RMICLR_RMI17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI17 */
+#define IFX_PSI5_RMICLR_RMI17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI17 */
+#define IFX_PSI5_RMICLR_RMI17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI18 */
+#define IFX_PSI5_RMICLR_RMI18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI18 */
+#define IFX_PSI5_RMICLR_RMI18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI18 */
+#define IFX_PSI5_RMICLR_RMI18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI19 */
+#define IFX_PSI5_RMICLR_RMI19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI19 */
+#define IFX_PSI5_RMICLR_RMI19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI19 */
+#define IFX_PSI5_RMICLR_RMI19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI1 */
+#define IFX_PSI5_RMICLR_RMI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI1 */
+#define IFX_PSI5_RMICLR_RMI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI1 */
+#define IFX_PSI5_RMICLR_RMI1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI20 */
+#define IFX_PSI5_RMICLR_RMI20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI20 */
+#define IFX_PSI5_RMICLR_RMI20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI20 */
+#define IFX_PSI5_RMICLR_RMI20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI21 */
+#define IFX_PSI5_RMICLR_RMI21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI21 */
+#define IFX_PSI5_RMICLR_RMI21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI21 */
+#define IFX_PSI5_RMICLR_RMI21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI22 */
+#define IFX_PSI5_RMICLR_RMI22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI22 */
+#define IFX_PSI5_RMICLR_RMI22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI22 */
+#define IFX_PSI5_RMICLR_RMI22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI23 */
+#define IFX_PSI5_RMICLR_RMI23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI23 */
+#define IFX_PSI5_RMICLR_RMI23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI23 */
+#define IFX_PSI5_RMICLR_RMI23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI24 */
+#define IFX_PSI5_RMICLR_RMI24_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI24 */
+#define IFX_PSI5_RMICLR_RMI24_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI24 */
+#define IFX_PSI5_RMICLR_RMI24_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI25 */
+#define IFX_PSI5_RMICLR_RMI25_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI25 */
+#define IFX_PSI5_RMICLR_RMI25_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI25 */
+#define IFX_PSI5_RMICLR_RMI25_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI26 */
+#define IFX_PSI5_RMICLR_RMI26_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI26 */
+#define IFX_PSI5_RMICLR_RMI26_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI26 */
+#define IFX_PSI5_RMICLR_RMI26_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI27 */
+#define IFX_PSI5_RMICLR_RMI27_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI27 */
+#define IFX_PSI5_RMICLR_RMI27_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI27 */
+#define IFX_PSI5_RMICLR_RMI27_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI28 */
+#define IFX_PSI5_RMICLR_RMI28_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI28 */
+#define IFX_PSI5_RMICLR_RMI28_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI28 */
+#define IFX_PSI5_RMICLR_RMI28_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI29 */
+#define IFX_PSI5_RMICLR_RMI29_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI29 */
+#define IFX_PSI5_RMICLR_RMI29_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI29 */
+#define IFX_PSI5_RMICLR_RMI29_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI2 */
+#define IFX_PSI5_RMICLR_RMI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI2 */
+#define IFX_PSI5_RMICLR_RMI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI2 */
+#define IFX_PSI5_RMICLR_RMI2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI30 */
+#define IFX_PSI5_RMICLR_RMI30_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI30 */
+#define IFX_PSI5_RMICLR_RMI30_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI30 */
+#define IFX_PSI5_RMICLR_RMI30_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI31 */
+#define IFX_PSI5_RMICLR_RMI31_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI31 */
+#define IFX_PSI5_RMICLR_RMI31_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI31 */
+#define IFX_PSI5_RMICLR_RMI31_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI3 */
+#define IFX_PSI5_RMICLR_RMI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI3 */
+#define IFX_PSI5_RMICLR_RMI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI3 */
+#define IFX_PSI5_RMICLR_RMI3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI4 */
+#define IFX_PSI5_RMICLR_RMI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI4 */
+#define IFX_PSI5_RMICLR_RMI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI4 */
+#define IFX_PSI5_RMICLR_RMI4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI5 */
+#define IFX_PSI5_RMICLR_RMI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI5 */
+#define IFX_PSI5_RMICLR_RMI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI5 */
+#define IFX_PSI5_RMICLR_RMI5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI6 */
+#define IFX_PSI5_RMICLR_RMI6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI6 */
+#define IFX_PSI5_RMICLR_RMI6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI6 */
+#define IFX_PSI5_RMICLR_RMI6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI7 */
+#define IFX_PSI5_RMICLR_RMI7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI7 */
+#define IFX_PSI5_RMICLR_RMI7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI7 */
+#define IFX_PSI5_RMICLR_RMI7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI8 */
+#define IFX_PSI5_RMICLR_RMI8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI8 */
+#define IFX_PSI5_RMICLR_RMI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI8 */
+#define IFX_PSI5_RMICLR_RMI8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_RMICLR_Bits.RMI9 */
+#define IFX_PSI5_RMICLR_RMI9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMICLR_Bits.RMI9 */
+#define IFX_PSI5_RMICLR_RMI9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMICLR_Bits.RMI9 */
+#define IFX_PSI5_RMICLR_RMI9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI0 */
+#define IFX_PSI5_RMIOV_RMI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI0 */
+#define IFX_PSI5_RMIOV_RMI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI0 */
+#define IFX_PSI5_RMIOV_RMI0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI10 */
+#define IFX_PSI5_RMIOV_RMI10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI10 */
+#define IFX_PSI5_RMIOV_RMI10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI10 */
+#define IFX_PSI5_RMIOV_RMI10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI11 */
+#define IFX_PSI5_RMIOV_RMI11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI11 */
+#define IFX_PSI5_RMIOV_RMI11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI11 */
+#define IFX_PSI5_RMIOV_RMI11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI12 */
+#define IFX_PSI5_RMIOV_RMI12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI12 */
+#define IFX_PSI5_RMIOV_RMI12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI12 */
+#define IFX_PSI5_RMIOV_RMI12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI13 */
+#define IFX_PSI5_RMIOV_RMI13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI13 */
+#define IFX_PSI5_RMIOV_RMI13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI13 */
+#define IFX_PSI5_RMIOV_RMI13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI14 */
+#define IFX_PSI5_RMIOV_RMI14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI14 */
+#define IFX_PSI5_RMIOV_RMI14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI14 */
+#define IFX_PSI5_RMIOV_RMI14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI15 */
+#define IFX_PSI5_RMIOV_RMI15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI15 */
+#define IFX_PSI5_RMIOV_RMI15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI15 */
+#define IFX_PSI5_RMIOV_RMI15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI16 */
+#define IFX_PSI5_RMIOV_RMI16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI16 */
+#define IFX_PSI5_RMIOV_RMI16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI16 */
+#define IFX_PSI5_RMIOV_RMI16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI17 */
+#define IFX_PSI5_RMIOV_RMI17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI17 */
+#define IFX_PSI5_RMIOV_RMI17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI17 */
+#define IFX_PSI5_RMIOV_RMI17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI18 */
+#define IFX_PSI5_RMIOV_RMI18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI18 */
+#define IFX_PSI5_RMIOV_RMI18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI18 */
+#define IFX_PSI5_RMIOV_RMI18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI19 */
+#define IFX_PSI5_RMIOV_RMI19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI19 */
+#define IFX_PSI5_RMIOV_RMI19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI19 */
+#define IFX_PSI5_RMIOV_RMI19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI1 */
+#define IFX_PSI5_RMIOV_RMI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI1 */
+#define IFX_PSI5_RMIOV_RMI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI1 */
+#define IFX_PSI5_RMIOV_RMI1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI20 */
+#define IFX_PSI5_RMIOV_RMI20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI20 */
+#define IFX_PSI5_RMIOV_RMI20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI20 */
+#define IFX_PSI5_RMIOV_RMI20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI21 */
+#define IFX_PSI5_RMIOV_RMI21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI21 */
+#define IFX_PSI5_RMIOV_RMI21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI21 */
+#define IFX_PSI5_RMIOV_RMI21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI22 */
+#define IFX_PSI5_RMIOV_RMI22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI22 */
+#define IFX_PSI5_RMIOV_RMI22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI22 */
+#define IFX_PSI5_RMIOV_RMI22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI23 */
+#define IFX_PSI5_RMIOV_RMI23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI23 */
+#define IFX_PSI5_RMIOV_RMI23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI23 */
+#define IFX_PSI5_RMIOV_RMI23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI24 */
+#define IFX_PSI5_RMIOV_RMI24_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI24 */
+#define IFX_PSI5_RMIOV_RMI24_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI24 */
+#define IFX_PSI5_RMIOV_RMI24_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI25 */
+#define IFX_PSI5_RMIOV_RMI25_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI25 */
+#define IFX_PSI5_RMIOV_RMI25_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI25 */
+#define IFX_PSI5_RMIOV_RMI25_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI26 */
+#define IFX_PSI5_RMIOV_RMI26_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI26 */
+#define IFX_PSI5_RMIOV_RMI26_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI26 */
+#define IFX_PSI5_RMIOV_RMI26_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI27 */
+#define IFX_PSI5_RMIOV_RMI27_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI27 */
+#define IFX_PSI5_RMIOV_RMI27_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI27 */
+#define IFX_PSI5_RMIOV_RMI27_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI28 */
+#define IFX_PSI5_RMIOV_RMI28_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI28 */
+#define IFX_PSI5_RMIOV_RMI28_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI28 */
+#define IFX_PSI5_RMIOV_RMI28_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI29 */
+#define IFX_PSI5_RMIOV_RMI29_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI29 */
+#define IFX_PSI5_RMIOV_RMI29_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI29 */
+#define IFX_PSI5_RMIOV_RMI29_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI2 */
+#define IFX_PSI5_RMIOV_RMI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI2 */
+#define IFX_PSI5_RMIOV_RMI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI2 */
+#define IFX_PSI5_RMIOV_RMI2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI30 */
+#define IFX_PSI5_RMIOV_RMI30_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI30 */
+#define IFX_PSI5_RMIOV_RMI30_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI30 */
+#define IFX_PSI5_RMIOV_RMI30_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI31 */
+#define IFX_PSI5_RMIOV_RMI31_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI31 */
+#define IFX_PSI5_RMIOV_RMI31_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI31 */
+#define IFX_PSI5_RMIOV_RMI31_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI3 */
+#define IFX_PSI5_RMIOV_RMI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI3 */
+#define IFX_PSI5_RMIOV_RMI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI3 */
+#define IFX_PSI5_RMIOV_RMI3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI4 */
+#define IFX_PSI5_RMIOV_RMI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI4 */
+#define IFX_PSI5_RMIOV_RMI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI4 */
+#define IFX_PSI5_RMIOV_RMI4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI5 */
+#define IFX_PSI5_RMIOV_RMI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI5 */
+#define IFX_PSI5_RMIOV_RMI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI5 */
+#define IFX_PSI5_RMIOV_RMI5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI6 */
+#define IFX_PSI5_RMIOV_RMI6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI6 */
+#define IFX_PSI5_RMIOV_RMI6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI6 */
+#define IFX_PSI5_RMIOV_RMI6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI7 */
+#define IFX_PSI5_RMIOV_RMI7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI7 */
+#define IFX_PSI5_RMIOV_RMI7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI7 */
+#define IFX_PSI5_RMIOV_RMI7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI8 */
+#define IFX_PSI5_RMIOV_RMI8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI8 */
+#define IFX_PSI5_RMIOV_RMI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI8 */
+#define IFX_PSI5_RMIOV_RMI8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_RMIOV_Bits.RMI9 */
+#define IFX_PSI5_RMIOV_RMI9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMIOV_Bits.RMI9 */
+#define IFX_PSI5_RMIOV_RMI9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMIOV_Bits.RMI9 */
+#define IFX_PSI5_RMIOV_RMI9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI0 */
+#define IFX_PSI5_RMISET_RMI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI0 */
+#define IFX_PSI5_RMISET_RMI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI0 */
+#define IFX_PSI5_RMISET_RMI0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI10 */
+#define IFX_PSI5_RMISET_RMI10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI10 */
+#define IFX_PSI5_RMISET_RMI10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI10 */
+#define IFX_PSI5_RMISET_RMI10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI11 */
+#define IFX_PSI5_RMISET_RMI11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI11 */
+#define IFX_PSI5_RMISET_RMI11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI11 */
+#define IFX_PSI5_RMISET_RMI11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI12 */
+#define IFX_PSI5_RMISET_RMI12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI12 */
+#define IFX_PSI5_RMISET_RMI12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI12 */
+#define IFX_PSI5_RMISET_RMI12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI13 */
+#define IFX_PSI5_RMISET_RMI13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI13 */
+#define IFX_PSI5_RMISET_RMI13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI13 */
+#define IFX_PSI5_RMISET_RMI13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI14 */
+#define IFX_PSI5_RMISET_RMI14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI14 */
+#define IFX_PSI5_RMISET_RMI14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI14 */
+#define IFX_PSI5_RMISET_RMI14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI15 */
+#define IFX_PSI5_RMISET_RMI15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI15 */
+#define IFX_PSI5_RMISET_RMI15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI15 */
+#define IFX_PSI5_RMISET_RMI15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI16 */
+#define IFX_PSI5_RMISET_RMI16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI16 */
+#define IFX_PSI5_RMISET_RMI16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI16 */
+#define IFX_PSI5_RMISET_RMI16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI17 */
+#define IFX_PSI5_RMISET_RMI17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI17 */
+#define IFX_PSI5_RMISET_RMI17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI17 */
+#define IFX_PSI5_RMISET_RMI17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI18 */
+#define IFX_PSI5_RMISET_RMI18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI18 */
+#define IFX_PSI5_RMISET_RMI18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI18 */
+#define IFX_PSI5_RMISET_RMI18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI19 */
+#define IFX_PSI5_RMISET_RMI19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI19 */
+#define IFX_PSI5_RMISET_RMI19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI19 */
+#define IFX_PSI5_RMISET_RMI19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI1 */
+#define IFX_PSI5_RMISET_RMI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI1 */
+#define IFX_PSI5_RMISET_RMI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI1 */
+#define IFX_PSI5_RMISET_RMI1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI20 */
+#define IFX_PSI5_RMISET_RMI20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI20 */
+#define IFX_PSI5_RMISET_RMI20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI20 */
+#define IFX_PSI5_RMISET_RMI20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI21 */
+#define IFX_PSI5_RMISET_RMI21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI21 */
+#define IFX_PSI5_RMISET_RMI21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI21 */
+#define IFX_PSI5_RMISET_RMI21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI22 */
+#define IFX_PSI5_RMISET_RMI22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI22 */
+#define IFX_PSI5_RMISET_RMI22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI22 */
+#define IFX_PSI5_RMISET_RMI22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI23 */
+#define IFX_PSI5_RMISET_RMI23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI23 */
+#define IFX_PSI5_RMISET_RMI23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI23 */
+#define IFX_PSI5_RMISET_RMI23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI24 */
+#define IFX_PSI5_RMISET_RMI24_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI24 */
+#define IFX_PSI5_RMISET_RMI24_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI24 */
+#define IFX_PSI5_RMISET_RMI24_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI25 */
+#define IFX_PSI5_RMISET_RMI25_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI25 */
+#define IFX_PSI5_RMISET_RMI25_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI25 */
+#define IFX_PSI5_RMISET_RMI25_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI26 */
+#define IFX_PSI5_RMISET_RMI26_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI26 */
+#define IFX_PSI5_RMISET_RMI26_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI26 */
+#define IFX_PSI5_RMISET_RMI26_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI27 */
+#define IFX_PSI5_RMISET_RMI27_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI27 */
+#define IFX_PSI5_RMISET_RMI27_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI27 */
+#define IFX_PSI5_RMISET_RMI27_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI28 */
+#define IFX_PSI5_RMISET_RMI28_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI28 */
+#define IFX_PSI5_RMISET_RMI28_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI28 */
+#define IFX_PSI5_RMISET_RMI28_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI29 */
+#define IFX_PSI5_RMISET_RMI29_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI29 */
+#define IFX_PSI5_RMISET_RMI29_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI29 */
+#define IFX_PSI5_RMISET_RMI29_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI2 */
+#define IFX_PSI5_RMISET_RMI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI2 */
+#define IFX_PSI5_RMISET_RMI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI2 */
+#define IFX_PSI5_RMISET_RMI2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI30 */
+#define IFX_PSI5_RMISET_RMI30_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI30 */
+#define IFX_PSI5_RMISET_RMI30_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI30 */
+#define IFX_PSI5_RMISET_RMI30_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI31 */
+#define IFX_PSI5_RMISET_RMI31_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI31 */
+#define IFX_PSI5_RMISET_RMI31_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI31 */
+#define IFX_PSI5_RMISET_RMI31_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI3 */
+#define IFX_PSI5_RMISET_RMI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI3 */
+#define IFX_PSI5_RMISET_RMI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI3 */
+#define IFX_PSI5_RMISET_RMI3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI4 */
+#define IFX_PSI5_RMISET_RMI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI4 */
+#define IFX_PSI5_RMISET_RMI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI4 */
+#define IFX_PSI5_RMISET_RMI4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI5 */
+#define IFX_PSI5_RMISET_RMI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI5 */
+#define IFX_PSI5_RMISET_RMI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI5 */
+#define IFX_PSI5_RMISET_RMI5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI6 */
+#define IFX_PSI5_RMISET_RMI6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI6 */
+#define IFX_PSI5_RMISET_RMI6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI6 */
+#define IFX_PSI5_RMISET_RMI6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI7 */
+#define IFX_PSI5_RMISET_RMI7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI7 */
+#define IFX_PSI5_RMISET_RMI7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI7 */
+#define IFX_PSI5_RMISET_RMI7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI8 */
+#define IFX_PSI5_RMISET_RMI8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI8 */
+#define IFX_PSI5_RMISET_RMI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI8 */
+#define IFX_PSI5_RMISET_RMI8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_RMISET_Bits.RMI9 */
+#define IFX_PSI5_RMISET_RMI9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RMISET_Bits.RMI9 */
+#define IFX_PSI5_RMISET_RMI9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RMISET_Bits.RMI9 */
+#define IFX_PSI5_RMISET_RMI9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI0 */
+#define IFX_PSI5_RSICLR_RSI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI0 */
+#define IFX_PSI5_RSICLR_RSI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI0 */
+#define IFX_PSI5_RSICLR_RSI0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI10 */
+#define IFX_PSI5_RSICLR_RSI10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI10 */
+#define IFX_PSI5_RSICLR_RSI10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI10 */
+#define IFX_PSI5_RSICLR_RSI10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI11 */
+#define IFX_PSI5_RSICLR_RSI11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI11 */
+#define IFX_PSI5_RSICLR_RSI11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI11 */
+#define IFX_PSI5_RSICLR_RSI11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI12 */
+#define IFX_PSI5_RSICLR_RSI12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI12 */
+#define IFX_PSI5_RSICLR_RSI12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI12 */
+#define IFX_PSI5_RSICLR_RSI12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI13 */
+#define IFX_PSI5_RSICLR_RSI13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI13 */
+#define IFX_PSI5_RSICLR_RSI13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI13 */
+#define IFX_PSI5_RSICLR_RSI13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI14 */
+#define IFX_PSI5_RSICLR_RSI14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI14 */
+#define IFX_PSI5_RSICLR_RSI14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI14 */
+#define IFX_PSI5_RSICLR_RSI14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI15 */
+#define IFX_PSI5_RSICLR_RSI15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI15 */
+#define IFX_PSI5_RSICLR_RSI15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI15 */
+#define IFX_PSI5_RSICLR_RSI15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI16 */
+#define IFX_PSI5_RSICLR_RSI16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI16 */
+#define IFX_PSI5_RSICLR_RSI16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI16 */
+#define IFX_PSI5_RSICLR_RSI16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI17 */
+#define IFX_PSI5_RSICLR_RSI17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI17 */
+#define IFX_PSI5_RSICLR_RSI17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI17 */
+#define IFX_PSI5_RSICLR_RSI17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI18 */
+#define IFX_PSI5_RSICLR_RSI18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI18 */
+#define IFX_PSI5_RSICLR_RSI18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI18 */
+#define IFX_PSI5_RSICLR_RSI18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI19 */
+#define IFX_PSI5_RSICLR_RSI19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI19 */
+#define IFX_PSI5_RSICLR_RSI19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI19 */
+#define IFX_PSI5_RSICLR_RSI19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI1 */
+#define IFX_PSI5_RSICLR_RSI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI1 */
+#define IFX_PSI5_RSICLR_RSI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI1 */
+#define IFX_PSI5_RSICLR_RSI1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI20 */
+#define IFX_PSI5_RSICLR_RSI20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI20 */
+#define IFX_PSI5_RSICLR_RSI20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI20 */
+#define IFX_PSI5_RSICLR_RSI20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI21 */
+#define IFX_PSI5_RSICLR_RSI21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI21 */
+#define IFX_PSI5_RSICLR_RSI21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI21 */
+#define IFX_PSI5_RSICLR_RSI21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI22 */
+#define IFX_PSI5_RSICLR_RSI22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI22 */
+#define IFX_PSI5_RSICLR_RSI22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI22 */
+#define IFX_PSI5_RSICLR_RSI22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI23 */
+#define IFX_PSI5_RSICLR_RSI23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI23 */
+#define IFX_PSI5_RSICLR_RSI23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI23 */
+#define IFX_PSI5_RSICLR_RSI23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI24 */
+#define IFX_PSI5_RSICLR_RSI24_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI24 */
+#define IFX_PSI5_RSICLR_RSI24_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI24 */
+#define IFX_PSI5_RSICLR_RSI24_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI25 */
+#define IFX_PSI5_RSICLR_RSI25_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI25 */
+#define IFX_PSI5_RSICLR_RSI25_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI25 */
+#define IFX_PSI5_RSICLR_RSI25_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI26 */
+#define IFX_PSI5_RSICLR_RSI26_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI26 */
+#define IFX_PSI5_RSICLR_RSI26_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI26 */
+#define IFX_PSI5_RSICLR_RSI26_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI27 */
+#define IFX_PSI5_RSICLR_RSI27_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI27 */
+#define IFX_PSI5_RSICLR_RSI27_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI27 */
+#define IFX_PSI5_RSICLR_RSI27_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI28 */
+#define IFX_PSI5_RSICLR_RSI28_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI28 */
+#define IFX_PSI5_RSICLR_RSI28_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI28 */
+#define IFX_PSI5_RSICLR_RSI28_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI29 */
+#define IFX_PSI5_RSICLR_RSI29_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI29 */
+#define IFX_PSI5_RSICLR_RSI29_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI29 */
+#define IFX_PSI5_RSICLR_RSI29_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI2 */
+#define IFX_PSI5_RSICLR_RSI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI2 */
+#define IFX_PSI5_RSICLR_RSI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI2 */
+#define IFX_PSI5_RSICLR_RSI2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI30 */
+#define IFX_PSI5_RSICLR_RSI30_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI30 */
+#define IFX_PSI5_RSICLR_RSI30_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI30 */
+#define IFX_PSI5_RSICLR_RSI30_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI31 */
+#define IFX_PSI5_RSICLR_RSI31_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI31 */
+#define IFX_PSI5_RSICLR_RSI31_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI31 */
+#define IFX_PSI5_RSICLR_RSI31_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI3 */
+#define IFX_PSI5_RSICLR_RSI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI3 */
+#define IFX_PSI5_RSICLR_RSI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI3 */
+#define IFX_PSI5_RSICLR_RSI3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI4 */
+#define IFX_PSI5_RSICLR_RSI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI4 */
+#define IFX_PSI5_RSICLR_RSI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI4 */
+#define IFX_PSI5_RSICLR_RSI4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI5 */
+#define IFX_PSI5_RSICLR_RSI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI5 */
+#define IFX_PSI5_RSICLR_RSI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI5 */
+#define IFX_PSI5_RSICLR_RSI5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI6 */
+#define IFX_PSI5_RSICLR_RSI6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI6 */
+#define IFX_PSI5_RSICLR_RSI6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI6 */
+#define IFX_PSI5_RSICLR_RSI6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI7 */
+#define IFX_PSI5_RSICLR_RSI7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI7 */
+#define IFX_PSI5_RSICLR_RSI7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI7 */
+#define IFX_PSI5_RSICLR_RSI7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI8 */
+#define IFX_PSI5_RSICLR_RSI8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI8 */
+#define IFX_PSI5_RSICLR_RSI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI8 */
+#define IFX_PSI5_RSICLR_RSI8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_RSICLR_Bits.RSI9 */
+#define IFX_PSI5_RSICLR_RSI9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSICLR_Bits.RSI9 */
+#define IFX_PSI5_RSICLR_RSI9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSICLR_Bits.RSI9 */
+#define IFX_PSI5_RSICLR_RSI9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI0 */
+#define IFX_PSI5_RSIOV_RSI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI0 */
+#define IFX_PSI5_RSIOV_RSI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI0 */
+#define IFX_PSI5_RSIOV_RSI0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI10 */
+#define IFX_PSI5_RSIOV_RSI10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI10 */
+#define IFX_PSI5_RSIOV_RSI10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI10 */
+#define IFX_PSI5_RSIOV_RSI10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI11 */
+#define IFX_PSI5_RSIOV_RSI11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI11 */
+#define IFX_PSI5_RSIOV_RSI11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI11 */
+#define IFX_PSI5_RSIOV_RSI11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI12 */
+#define IFX_PSI5_RSIOV_RSI12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI12 */
+#define IFX_PSI5_RSIOV_RSI12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI12 */
+#define IFX_PSI5_RSIOV_RSI12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI13 */
+#define IFX_PSI5_RSIOV_RSI13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI13 */
+#define IFX_PSI5_RSIOV_RSI13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI13 */
+#define IFX_PSI5_RSIOV_RSI13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI14 */
+#define IFX_PSI5_RSIOV_RSI14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI14 */
+#define IFX_PSI5_RSIOV_RSI14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI14 */
+#define IFX_PSI5_RSIOV_RSI14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI15 */
+#define IFX_PSI5_RSIOV_RSI15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI15 */
+#define IFX_PSI5_RSIOV_RSI15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI15 */
+#define IFX_PSI5_RSIOV_RSI15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI16 */
+#define IFX_PSI5_RSIOV_RSI16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI16 */
+#define IFX_PSI5_RSIOV_RSI16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI16 */
+#define IFX_PSI5_RSIOV_RSI16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI17 */
+#define IFX_PSI5_RSIOV_RSI17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI17 */
+#define IFX_PSI5_RSIOV_RSI17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI17 */
+#define IFX_PSI5_RSIOV_RSI17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI18 */
+#define IFX_PSI5_RSIOV_RSI18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI18 */
+#define IFX_PSI5_RSIOV_RSI18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI18 */
+#define IFX_PSI5_RSIOV_RSI18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI19 */
+#define IFX_PSI5_RSIOV_RSI19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI19 */
+#define IFX_PSI5_RSIOV_RSI19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI19 */
+#define IFX_PSI5_RSIOV_RSI19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI1 */
+#define IFX_PSI5_RSIOV_RSI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI1 */
+#define IFX_PSI5_RSIOV_RSI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI1 */
+#define IFX_PSI5_RSIOV_RSI1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI20 */
+#define IFX_PSI5_RSIOV_RSI20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI20 */
+#define IFX_PSI5_RSIOV_RSI20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI20 */
+#define IFX_PSI5_RSIOV_RSI20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI21 */
+#define IFX_PSI5_RSIOV_RSI21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI21 */
+#define IFX_PSI5_RSIOV_RSI21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI21 */
+#define IFX_PSI5_RSIOV_RSI21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI22 */
+#define IFX_PSI5_RSIOV_RSI22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI22 */
+#define IFX_PSI5_RSIOV_RSI22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI22 */
+#define IFX_PSI5_RSIOV_RSI22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI23 */
+#define IFX_PSI5_RSIOV_RSI23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI23 */
+#define IFX_PSI5_RSIOV_RSI23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI23 */
+#define IFX_PSI5_RSIOV_RSI23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI24 */
+#define IFX_PSI5_RSIOV_RSI24_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI24 */
+#define IFX_PSI5_RSIOV_RSI24_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI24 */
+#define IFX_PSI5_RSIOV_RSI24_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI25 */
+#define IFX_PSI5_RSIOV_RSI25_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI25 */
+#define IFX_PSI5_RSIOV_RSI25_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI25 */
+#define IFX_PSI5_RSIOV_RSI25_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI26 */
+#define IFX_PSI5_RSIOV_RSI26_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI26 */
+#define IFX_PSI5_RSIOV_RSI26_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI26 */
+#define IFX_PSI5_RSIOV_RSI26_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI27 */
+#define IFX_PSI5_RSIOV_RSI27_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI27 */
+#define IFX_PSI5_RSIOV_RSI27_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI27 */
+#define IFX_PSI5_RSIOV_RSI27_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI28 */
+#define IFX_PSI5_RSIOV_RSI28_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI28 */
+#define IFX_PSI5_RSIOV_RSI28_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI28 */
+#define IFX_PSI5_RSIOV_RSI28_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI29 */
+#define IFX_PSI5_RSIOV_RSI29_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI29 */
+#define IFX_PSI5_RSIOV_RSI29_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI29 */
+#define IFX_PSI5_RSIOV_RSI29_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI2 */
+#define IFX_PSI5_RSIOV_RSI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI2 */
+#define IFX_PSI5_RSIOV_RSI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI2 */
+#define IFX_PSI5_RSIOV_RSI2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI30 */
+#define IFX_PSI5_RSIOV_RSI30_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI30 */
+#define IFX_PSI5_RSIOV_RSI30_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI30 */
+#define IFX_PSI5_RSIOV_RSI30_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI31 */
+#define IFX_PSI5_RSIOV_RSI31_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI31 */
+#define IFX_PSI5_RSIOV_RSI31_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI31 */
+#define IFX_PSI5_RSIOV_RSI31_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI3 */
+#define IFX_PSI5_RSIOV_RSI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI3 */
+#define IFX_PSI5_RSIOV_RSI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI3 */
+#define IFX_PSI5_RSIOV_RSI3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI4 */
+#define IFX_PSI5_RSIOV_RSI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI4 */
+#define IFX_PSI5_RSIOV_RSI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI4 */
+#define IFX_PSI5_RSIOV_RSI4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI5 */
+#define IFX_PSI5_RSIOV_RSI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI5 */
+#define IFX_PSI5_RSIOV_RSI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI5 */
+#define IFX_PSI5_RSIOV_RSI5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI6 */
+#define IFX_PSI5_RSIOV_RSI6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI6 */
+#define IFX_PSI5_RSIOV_RSI6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI6 */
+#define IFX_PSI5_RSIOV_RSI6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI7 */
+#define IFX_PSI5_RSIOV_RSI7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI7 */
+#define IFX_PSI5_RSIOV_RSI7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI7 */
+#define IFX_PSI5_RSIOV_RSI7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI8 */
+#define IFX_PSI5_RSIOV_RSI8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI8 */
+#define IFX_PSI5_RSIOV_RSI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI8 */
+#define IFX_PSI5_RSIOV_RSI8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_RSIOV_Bits.RSI9 */
+#define IFX_PSI5_RSIOV_RSI9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSIOV_Bits.RSI9 */
+#define IFX_PSI5_RSIOV_RSI9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSIOV_Bits.RSI9 */
+#define IFX_PSI5_RSIOV_RSI9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI0 */
+#define IFX_PSI5_RSISET_RSI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI0 */
+#define IFX_PSI5_RSISET_RSI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI0 */
+#define IFX_PSI5_RSISET_RSI0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI10 */
+#define IFX_PSI5_RSISET_RSI10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI10 */
+#define IFX_PSI5_RSISET_RSI10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI10 */
+#define IFX_PSI5_RSISET_RSI10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI11 */
+#define IFX_PSI5_RSISET_RSI11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI11 */
+#define IFX_PSI5_RSISET_RSI11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI11 */
+#define IFX_PSI5_RSISET_RSI11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI12 */
+#define IFX_PSI5_RSISET_RSI12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI12 */
+#define IFX_PSI5_RSISET_RSI12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI12 */
+#define IFX_PSI5_RSISET_RSI12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI13 */
+#define IFX_PSI5_RSISET_RSI13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI13 */
+#define IFX_PSI5_RSISET_RSI13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI13 */
+#define IFX_PSI5_RSISET_RSI13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI14 */
+#define IFX_PSI5_RSISET_RSI14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI14 */
+#define IFX_PSI5_RSISET_RSI14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI14 */
+#define IFX_PSI5_RSISET_RSI14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI15 */
+#define IFX_PSI5_RSISET_RSI15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI15 */
+#define IFX_PSI5_RSISET_RSI15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI15 */
+#define IFX_PSI5_RSISET_RSI15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI16 */
+#define IFX_PSI5_RSISET_RSI16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI16 */
+#define IFX_PSI5_RSISET_RSI16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI16 */
+#define IFX_PSI5_RSISET_RSI16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI17 */
+#define IFX_PSI5_RSISET_RSI17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI17 */
+#define IFX_PSI5_RSISET_RSI17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI17 */
+#define IFX_PSI5_RSISET_RSI17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI18 */
+#define IFX_PSI5_RSISET_RSI18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI18 */
+#define IFX_PSI5_RSISET_RSI18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI18 */
+#define IFX_PSI5_RSISET_RSI18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI19 */
+#define IFX_PSI5_RSISET_RSI19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI19 */
+#define IFX_PSI5_RSISET_RSI19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI19 */
+#define IFX_PSI5_RSISET_RSI19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI1 */
+#define IFX_PSI5_RSISET_RSI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI1 */
+#define IFX_PSI5_RSISET_RSI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI1 */
+#define IFX_PSI5_RSISET_RSI1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI20 */
+#define IFX_PSI5_RSISET_RSI20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI20 */
+#define IFX_PSI5_RSISET_RSI20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI20 */
+#define IFX_PSI5_RSISET_RSI20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI21 */
+#define IFX_PSI5_RSISET_RSI21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI21 */
+#define IFX_PSI5_RSISET_RSI21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI21 */
+#define IFX_PSI5_RSISET_RSI21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI22 */
+#define IFX_PSI5_RSISET_RSI22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI22 */
+#define IFX_PSI5_RSISET_RSI22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI22 */
+#define IFX_PSI5_RSISET_RSI22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI23 */
+#define IFX_PSI5_RSISET_RSI23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI23 */
+#define IFX_PSI5_RSISET_RSI23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI23 */
+#define IFX_PSI5_RSISET_RSI23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI24 */
+#define IFX_PSI5_RSISET_RSI24_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI24 */
+#define IFX_PSI5_RSISET_RSI24_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI24 */
+#define IFX_PSI5_RSISET_RSI24_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI25 */
+#define IFX_PSI5_RSISET_RSI25_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI25 */
+#define IFX_PSI5_RSISET_RSI25_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI25 */
+#define IFX_PSI5_RSISET_RSI25_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI26 */
+#define IFX_PSI5_RSISET_RSI26_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI26 */
+#define IFX_PSI5_RSISET_RSI26_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI26 */
+#define IFX_PSI5_RSISET_RSI26_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI27 */
+#define IFX_PSI5_RSISET_RSI27_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI27 */
+#define IFX_PSI5_RSISET_RSI27_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI27 */
+#define IFX_PSI5_RSISET_RSI27_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI28 */
+#define IFX_PSI5_RSISET_RSI28_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI28 */
+#define IFX_PSI5_RSISET_RSI28_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI28 */
+#define IFX_PSI5_RSISET_RSI28_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI29 */
+#define IFX_PSI5_RSISET_RSI29_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI29 */
+#define IFX_PSI5_RSISET_RSI29_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI29 */
+#define IFX_PSI5_RSISET_RSI29_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI2 */
+#define IFX_PSI5_RSISET_RSI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI2 */
+#define IFX_PSI5_RSISET_RSI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI2 */
+#define IFX_PSI5_RSISET_RSI2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI30 */
+#define IFX_PSI5_RSISET_RSI30_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI30 */
+#define IFX_PSI5_RSISET_RSI30_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI30 */
+#define IFX_PSI5_RSISET_RSI30_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI31 */
+#define IFX_PSI5_RSISET_RSI31_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI31 */
+#define IFX_PSI5_RSISET_RSI31_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI31 */
+#define IFX_PSI5_RSISET_RSI31_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI3 */
+#define IFX_PSI5_RSISET_RSI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI3 */
+#define IFX_PSI5_RSISET_RSI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI3 */
+#define IFX_PSI5_RSISET_RSI3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI4 */
+#define IFX_PSI5_RSISET_RSI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI4 */
+#define IFX_PSI5_RSISET_RSI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI4 */
+#define IFX_PSI5_RSISET_RSI4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI5 */
+#define IFX_PSI5_RSISET_RSI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI5 */
+#define IFX_PSI5_RSISET_RSI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI5 */
+#define IFX_PSI5_RSISET_RSI5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI6 */
+#define IFX_PSI5_RSISET_RSI6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI6 */
+#define IFX_PSI5_RSISET_RSI6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI6 */
+#define IFX_PSI5_RSISET_RSI6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI7 */
+#define IFX_PSI5_RSISET_RSI7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI7 */
+#define IFX_PSI5_RSISET_RSI7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI7 */
+#define IFX_PSI5_RSISET_RSI7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI8 */
+#define IFX_PSI5_RSISET_RSI8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI8 */
+#define IFX_PSI5_RSISET_RSI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI8 */
+#define IFX_PSI5_RSISET_RSI8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_RSISET_Bits.RSI9 */
+#define IFX_PSI5_RSISET_RSI9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_RSISET_Bits.RSI9 */
+#define IFX_PSI5_RSISET_RSI9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_RSISET_Bits.RSI9 */
+#define IFX_PSI5_RSISET_RSI9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI0 */
+#define IFX_PSI5_TEICLR_TEI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI0 */
+#define IFX_PSI5_TEICLR_TEI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI0 */
+#define IFX_PSI5_TEICLR_TEI0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI10 */
+#define IFX_PSI5_TEICLR_TEI10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI10 */
+#define IFX_PSI5_TEICLR_TEI10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI10 */
+#define IFX_PSI5_TEICLR_TEI10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI11 */
+#define IFX_PSI5_TEICLR_TEI11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI11 */
+#define IFX_PSI5_TEICLR_TEI11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI11 */
+#define IFX_PSI5_TEICLR_TEI11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI12 */
+#define IFX_PSI5_TEICLR_TEI12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI12 */
+#define IFX_PSI5_TEICLR_TEI12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI12 */
+#define IFX_PSI5_TEICLR_TEI12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI13 */
+#define IFX_PSI5_TEICLR_TEI13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI13 */
+#define IFX_PSI5_TEICLR_TEI13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI13 */
+#define IFX_PSI5_TEICLR_TEI13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI14 */
+#define IFX_PSI5_TEICLR_TEI14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI14 */
+#define IFX_PSI5_TEICLR_TEI14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI14 */
+#define IFX_PSI5_TEICLR_TEI14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI15 */
+#define IFX_PSI5_TEICLR_TEI15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI15 */
+#define IFX_PSI5_TEICLR_TEI15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI15 */
+#define IFX_PSI5_TEICLR_TEI15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI16 */
+#define IFX_PSI5_TEICLR_TEI16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI16 */
+#define IFX_PSI5_TEICLR_TEI16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI16 */
+#define IFX_PSI5_TEICLR_TEI16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI17 */
+#define IFX_PSI5_TEICLR_TEI17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI17 */
+#define IFX_PSI5_TEICLR_TEI17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI17 */
+#define IFX_PSI5_TEICLR_TEI17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI18 */
+#define IFX_PSI5_TEICLR_TEI18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI18 */
+#define IFX_PSI5_TEICLR_TEI18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI18 */
+#define IFX_PSI5_TEICLR_TEI18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI19 */
+#define IFX_PSI5_TEICLR_TEI19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI19 */
+#define IFX_PSI5_TEICLR_TEI19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI19 */
+#define IFX_PSI5_TEICLR_TEI19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI1 */
+#define IFX_PSI5_TEICLR_TEI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI1 */
+#define IFX_PSI5_TEICLR_TEI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI1 */
+#define IFX_PSI5_TEICLR_TEI1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI20 */
+#define IFX_PSI5_TEICLR_TEI20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI20 */
+#define IFX_PSI5_TEICLR_TEI20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI20 */
+#define IFX_PSI5_TEICLR_TEI20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI21 */
+#define IFX_PSI5_TEICLR_TEI21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI21 */
+#define IFX_PSI5_TEICLR_TEI21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI21 */
+#define IFX_PSI5_TEICLR_TEI21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI22 */
+#define IFX_PSI5_TEICLR_TEI22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI22 */
+#define IFX_PSI5_TEICLR_TEI22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI22 */
+#define IFX_PSI5_TEICLR_TEI22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI23 */
+#define IFX_PSI5_TEICLR_TEI23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI23 */
+#define IFX_PSI5_TEICLR_TEI23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI23 */
+#define IFX_PSI5_TEICLR_TEI23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI24 */
+#define IFX_PSI5_TEICLR_TEI24_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI24 */
+#define IFX_PSI5_TEICLR_TEI24_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI24 */
+#define IFX_PSI5_TEICLR_TEI24_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI25 */
+#define IFX_PSI5_TEICLR_TEI25_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI25 */
+#define IFX_PSI5_TEICLR_TEI25_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI25 */
+#define IFX_PSI5_TEICLR_TEI25_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI26 */
+#define IFX_PSI5_TEICLR_TEI26_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI26 */
+#define IFX_PSI5_TEICLR_TEI26_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI26 */
+#define IFX_PSI5_TEICLR_TEI26_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI27 */
+#define IFX_PSI5_TEICLR_TEI27_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI27 */
+#define IFX_PSI5_TEICLR_TEI27_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI27 */
+#define IFX_PSI5_TEICLR_TEI27_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI28 */
+#define IFX_PSI5_TEICLR_TEI28_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI28 */
+#define IFX_PSI5_TEICLR_TEI28_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI28 */
+#define IFX_PSI5_TEICLR_TEI28_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI29 */
+#define IFX_PSI5_TEICLR_TEI29_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI29 */
+#define IFX_PSI5_TEICLR_TEI29_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI29 */
+#define IFX_PSI5_TEICLR_TEI29_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI2 */
+#define IFX_PSI5_TEICLR_TEI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI2 */
+#define IFX_PSI5_TEICLR_TEI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI2 */
+#define IFX_PSI5_TEICLR_TEI2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI30 */
+#define IFX_PSI5_TEICLR_TEI30_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI30 */
+#define IFX_PSI5_TEICLR_TEI30_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI30 */
+#define IFX_PSI5_TEICLR_TEI30_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI31 */
+#define IFX_PSI5_TEICLR_TEI31_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI31 */
+#define IFX_PSI5_TEICLR_TEI31_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI31 */
+#define IFX_PSI5_TEICLR_TEI31_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI3 */
+#define IFX_PSI5_TEICLR_TEI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI3 */
+#define IFX_PSI5_TEICLR_TEI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI3 */
+#define IFX_PSI5_TEICLR_TEI3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI4 */
+#define IFX_PSI5_TEICLR_TEI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI4 */
+#define IFX_PSI5_TEICLR_TEI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI4 */
+#define IFX_PSI5_TEICLR_TEI4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI5 */
+#define IFX_PSI5_TEICLR_TEI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI5 */
+#define IFX_PSI5_TEICLR_TEI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI5 */
+#define IFX_PSI5_TEICLR_TEI5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI6 */
+#define IFX_PSI5_TEICLR_TEI6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI6 */
+#define IFX_PSI5_TEICLR_TEI6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI6 */
+#define IFX_PSI5_TEICLR_TEI6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI7 */
+#define IFX_PSI5_TEICLR_TEI7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI7 */
+#define IFX_PSI5_TEICLR_TEI7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI7 */
+#define IFX_PSI5_TEICLR_TEI7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI8 */
+#define IFX_PSI5_TEICLR_TEI8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI8 */
+#define IFX_PSI5_TEICLR_TEI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI8 */
+#define IFX_PSI5_TEICLR_TEI8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_TEICLR_Bits.TEI9 */
+#define IFX_PSI5_TEICLR_TEI9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEICLR_Bits.TEI9 */
+#define IFX_PSI5_TEICLR_TEI9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEICLR_Bits.TEI9 */
+#define IFX_PSI5_TEICLR_TEI9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI0 */
+#define IFX_PSI5_TEIOV_TEI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI0 */
+#define IFX_PSI5_TEIOV_TEI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI0 */
+#define IFX_PSI5_TEIOV_TEI0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI10 */
+#define IFX_PSI5_TEIOV_TEI10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI10 */
+#define IFX_PSI5_TEIOV_TEI10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI10 */
+#define IFX_PSI5_TEIOV_TEI10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI11 */
+#define IFX_PSI5_TEIOV_TEI11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI11 */
+#define IFX_PSI5_TEIOV_TEI11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI11 */
+#define IFX_PSI5_TEIOV_TEI11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI12 */
+#define IFX_PSI5_TEIOV_TEI12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI12 */
+#define IFX_PSI5_TEIOV_TEI12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI12 */
+#define IFX_PSI5_TEIOV_TEI12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI13 */
+#define IFX_PSI5_TEIOV_TEI13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI13 */
+#define IFX_PSI5_TEIOV_TEI13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI13 */
+#define IFX_PSI5_TEIOV_TEI13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI14 */
+#define IFX_PSI5_TEIOV_TEI14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI14 */
+#define IFX_PSI5_TEIOV_TEI14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI14 */
+#define IFX_PSI5_TEIOV_TEI14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI15 */
+#define IFX_PSI5_TEIOV_TEI15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI15 */
+#define IFX_PSI5_TEIOV_TEI15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI15 */
+#define IFX_PSI5_TEIOV_TEI15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI16 */
+#define IFX_PSI5_TEIOV_TEI16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI16 */
+#define IFX_PSI5_TEIOV_TEI16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI16 */
+#define IFX_PSI5_TEIOV_TEI16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI17 */
+#define IFX_PSI5_TEIOV_TEI17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI17 */
+#define IFX_PSI5_TEIOV_TEI17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI17 */
+#define IFX_PSI5_TEIOV_TEI17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI18 */
+#define IFX_PSI5_TEIOV_TEI18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI18 */
+#define IFX_PSI5_TEIOV_TEI18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI18 */
+#define IFX_PSI5_TEIOV_TEI18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI19 */
+#define IFX_PSI5_TEIOV_TEI19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI19 */
+#define IFX_PSI5_TEIOV_TEI19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI19 */
+#define IFX_PSI5_TEIOV_TEI19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI1 */
+#define IFX_PSI5_TEIOV_TEI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI1 */
+#define IFX_PSI5_TEIOV_TEI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI1 */
+#define IFX_PSI5_TEIOV_TEI1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI20 */
+#define IFX_PSI5_TEIOV_TEI20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI20 */
+#define IFX_PSI5_TEIOV_TEI20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI20 */
+#define IFX_PSI5_TEIOV_TEI20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI21 */
+#define IFX_PSI5_TEIOV_TEI21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI21 */
+#define IFX_PSI5_TEIOV_TEI21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI21 */
+#define IFX_PSI5_TEIOV_TEI21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI22 */
+#define IFX_PSI5_TEIOV_TEI22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI22 */
+#define IFX_PSI5_TEIOV_TEI22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI22 */
+#define IFX_PSI5_TEIOV_TEI22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI23 */
+#define IFX_PSI5_TEIOV_TEI23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI23 */
+#define IFX_PSI5_TEIOV_TEI23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI23 */
+#define IFX_PSI5_TEIOV_TEI23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI24 */
+#define IFX_PSI5_TEIOV_TEI24_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI24 */
+#define IFX_PSI5_TEIOV_TEI24_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI24 */
+#define IFX_PSI5_TEIOV_TEI24_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI25 */
+#define IFX_PSI5_TEIOV_TEI25_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI25 */
+#define IFX_PSI5_TEIOV_TEI25_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI25 */
+#define IFX_PSI5_TEIOV_TEI25_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI26 */
+#define IFX_PSI5_TEIOV_TEI26_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI26 */
+#define IFX_PSI5_TEIOV_TEI26_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI26 */
+#define IFX_PSI5_TEIOV_TEI26_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI27 */
+#define IFX_PSI5_TEIOV_TEI27_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI27 */
+#define IFX_PSI5_TEIOV_TEI27_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI27 */
+#define IFX_PSI5_TEIOV_TEI27_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI28 */
+#define IFX_PSI5_TEIOV_TEI28_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI28 */
+#define IFX_PSI5_TEIOV_TEI28_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI28 */
+#define IFX_PSI5_TEIOV_TEI28_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI29 */
+#define IFX_PSI5_TEIOV_TEI29_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI29 */
+#define IFX_PSI5_TEIOV_TEI29_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI29 */
+#define IFX_PSI5_TEIOV_TEI29_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI2 */
+#define IFX_PSI5_TEIOV_TEI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI2 */
+#define IFX_PSI5_TEIOV_TEI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI2 */
+#define IFX_PSI5_TEIOV_TEI2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI30 */
+#define IFX_PSI5_TEIOV_TEI30_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI30 */
+#define IFX_PSI5_TEIOV_TEI30_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI30 */
+#define IFX_PSI5_TEIOV_TEI30_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI31 */
+#define IFX_PSI5_TEIOV_TEI31_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI31 */
+#define IFX_PSI5_TEIOV_TEI31_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI31 */
+#define IFX_PSI5_TEIOV_TEI31_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI3 */
+#define IFX_PSI5_TEIOV_TEI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI3 */
+#define IFX_PSI5_TEIOV_TEI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI3 */
+#define IFX_PSI5_TEIOV_TEI3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI4 */
+#define IFX_PSI5_TEIOV_TEI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI4 */
+#define IFX_PSI5_TEIOV_TEI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI4 */
+#define IFX_PSI5_TEIOV_TEI4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI5 */
+#define IFX_PSI5_TEIOV_TEI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI5 */
+#define IFX_PSI5_TEIOV_TEI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI5 */
+#define IFX_PSI5_TEIOV_TEI5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI6 */
+#define IFX_PSI5_TEIOV_TEI6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI6 */
+#define IFX_PSI5_TEIOV_TEI6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI6 */
+#define IFX_PSI5_TEIOV_TEI6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI7 */
+#define IFX_PSI5_TEIOV_TEI7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI7 */
+#define IFX_PSI5_TEIOV_TEI7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI7 */
+#define IFX_PSI5_TEIOV_TEI7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI8 */
+#define IFX_PSI5_TEIOV_TEI8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI8 */
+#define IFX_PSI5_TEIOV_TEI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI8 */
+#define IFX_PSI5_TEIOV_TEI8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_TEIOV_Bits.TEI9 */
+#define IFX_PSI5_TEIOV_TEI9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEIOV_Bits.TEI9 */
+#define IFX_PSI5_TEIOV_TEI9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEIOV_Bits.TEI9 */
+#define IFX_PSI5_TEIOV_TEI9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI0 */
+#define IFX_PSI5_TEISET_TEI0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI0 */
+#define IFX_PSI5_TEISET_TEI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI0 */
+#define IFX_PSI5_TEISET_TEI0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI10 */
+#define IFX_PSI5_TEISET_TEI10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI10 */
+#define IFX_PSI5_TEISET_TEI10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI10 */
+#define IFX_PSI5_TEISET_TEI10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI11 */
+#define IFX_PSI5_TEISET_TEI11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI11 */
+#define IFX_PSI5_TEISET_TEI11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI11 */
+#define IFX_PSI5_TEISET_TEI11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI12 */
+#define IFX_PSI5_TEISET_TEI12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI12 */
+#define IFX_PSI5_TEISET_TEI12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI12 */
+#define IFX_PSI5_TEISET_TEI12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI13 */
+#define IFX_PSI5_TEISET_TEI13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI13 */
+#define IFX_PSI5_TEISET_TEI13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI13 */
+#define IFX_PSI5_TEISET_TEI13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI14 */
+#define IFX_PSI5_TEISET_TEI14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI14 */
+#define IFX_PSI5_TEISET_TEI14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI14 */
+#define IFX_PSI5_TEISET_TEI14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI15 */
+#define IFX_PSI5_TEISET_TEI15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI15 */
+#define IFX_PSI5_TEISET_TEI15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI15 */
+#define IFX_PSI5_TEISET_TEI15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI16 */
+#define IFX_PSI5_TEISET_TEI16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI16 */
+#define IFX_PSI5_TEISET_TEI16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI16 */
+#define IFX_PSI5_TEISET_TEI16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI17 */
+#define IFX_PSI5_TEISET_TEI17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI17 */
+#define IFX_PSI5_TEISET_TEI17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI17 */
+#define IFX_PSI5_TEISET_TEI17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI18 */
+#define IFX_PSI5_TEISET_TEI18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI18 */
+#define IFX_PSI5_TEISET_TEI18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI18 */
+#define IFX_PSI5_TEISET_TEI18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI19 */
+#define IFX_PSI5_TEISET_TEI19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI19 */
+#define IFX_PSI5_TEISET_TEI19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI19 */
+#define IFX_PSI5_TEISET_TEI19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI1 */
+#define IFX_PSI5_TEISET_TEI1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI1 */
+#define IFX_PSI5_TEISET_TEI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI1 */
+#define IFX_PSI5_TEISET_TEI1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI20 */
+#define IFX_PSI5_TEISET_TEI20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI20 */
+#define IFX_PSI5_TEISET_TEI20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI20 */
+#define IFX_PSI5_TEISET_TEI20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI21 */
+#define IFX_PSI5_TEISET_TEI21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI21 */
+#define IFX_PSI5_TEISET_TEI21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI21 */
+#define IFX_PSI5_TEISET_TEI21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI22 */
+#define IFX_PSI5_TEISET_TEI22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI22 */
+#define IFX_PSI5_TEISET_TEI22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI22 */
+#define IFX_PSI5_TEISET_TEI22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI23 */
+#define IFX_PSI5_TEISET_TEI23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI23 */
+#define IFX_PSI5_TEISET_TEI23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI23 */
+#define IFX_PSI5_TEISET_TEI23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI24 */
+#define IFX_PSI5_TEISET_TEI24_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI24 */
+#define IFX_PSI5_TEISET_TEI24_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI24 */
+#define IFX_PSI5_TEISET_TEI24_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI25 */
+#define IFX_PSI5_TEISET_TEI25_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI25 */
+#define IFX_PSI5_TEISET_TEI25_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI25 */
+#define IFX_PSI5_TEISET_TEI25_OFF (25u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI26 */
+#define IFX_PSI5_TEISET_TEI26_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI26 */
+#define IFX_PSI5_TEISET_TEI26_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI26 */
+#define IFX_PSI5_TEISET_TEI26_OFF (26u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI27 */
+#define IFX_PSI5_TEISET_TEI27_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI27 */
+#define IFX_PSI5_TEISET_TEI27_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI27 */
+#define IFX_PSI5_TEISET_TEI27_OFF (27u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI28 */
+#define IFX_PSI5_TEISET_TEI28_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI28 */
+#define IFX_PSI5_TEISET_TEI28_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI28 */
+#define IFX_PSI5_TEISET_TEI28_OFF (28u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI29 */
+#define IFX_PSI5_TEISET_TEI29_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI29 */
+#define IFX_PSI5_TEISET_TEI29_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI29 */
+#define IFX_PSI5_TEISET_TEI29_OFF (29u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI2 */
+#define IFX_PSI5_TEISET_TEI2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI2 */
+#define IFX_PSI5_TEISET_TEI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI2 */
+#define IFX_PSI5_TEISET_TEI2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI30 */
+#define IFX_PSI5_TEISET_TEI30_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI30 */
+#define IFX_PSI5_TEISET_TEI30_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI30 */
+#define IFX_PSI5_TEISET_TEI30_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI31 */
+#define IFX_PSI5_TEISET_TEI31_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI31 */
+#define IFX_PSI5_TEISET_TEI31_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI31 */
+#define IFX_PSI5_TEISET_TEI31_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI3 */
+#define IFX_PSI5_TEISET_TEI3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI3 */
+#define IFX_PSI5_TEISET_TEI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI3 */
+#define IFX_PSI5_TEISET_TEI3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI4 */
+#define IFX_PSI5_TEISET_TEI4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI4 */
+#define IFX_PSI5_TEISET_TEI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI4 */
+#define IFX_PSI5_TEISET_TEI4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI5 */
+#define IFX_PSI5_TEISET_TEI5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI5 */
+#define IFX_PSI5_TEISET_TEI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI5 */
+#define IFX_PSI5_TEISET_TEI5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI6 */
+#define IFX_PSI5_TEISET_TEI6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI6 */
+#define IFX_PSI5_TEISET_TEI6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI6 */
+#define IFX_PSI5_TEISET_TEI6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI7 */
+#define IFX_PSI5_TEISET_TEI7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI7 */
+#define IFX_PSI5_TEISET_TEI7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI7 */
+#define IFX_PSI5_TEISET_TEI7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI8 */
+#define IFX_PSI5_TEISET_TEI8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI8 */
+#define IFX_PSI5_TEISET_TEI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI8 */
+#define IFX_PSI5_TEISET_TEI8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5_TEISET_Bits.TEI9 */
+#define IFX_PSI5_TEISET_TEI9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TEISET_Bits.TEI9 */
+#define IFX_PSI5_TEISET_TEI9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TEISET_Bits.TEI9 */
+#define IFX_PSI5_TEISET_TEI9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5_TSR_Bits.ACLR */
+#define IFX_PSI5_TSR_ACLR_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TSR_Bits.ACLR */
+#define IFX_PSI5_TSR_ACLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TSR_Bits.ACLR */
+#define IFX_PSI5_TSR_ACLR_OFF (30u)
+
+/** \brief Length for Ifx_PSI5_TSR_Bits.CLR */
+#define IFX_PSI5_TSR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TSR_Bits.CLR */
+#define IFX_PSI5_TSR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TSR_Bits.CLR */
+#define IFX_PSI5_TSR_CLR_OFF (31u)
+
+/** \brief Length for Ifx_PSI5_TSR_Bits.CTS */
+#define IFX_PSI5_TSR_CTS_LEN (24u)
+
+/** \brief Mask for Ifx_PSI5_TSR_Bits.CTS */
+#define IFX_PSI5_TSR_CTS_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_PSI5_TSR_Bits.CTS */
+#define IFX_PSI5_TSR_CTS_OFF (0u)
+
+/** \brief Length for Ifx_PSI5_TSR_Bits.ETB */
+#define IFX_PSI5_TSR_ETB_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5_TSR_Bits.ETB */
+#define IFX_PSI5_TSR_ETB_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5_TSR_Bits.ETB */
+#define IFX_PSI5_TSR_ETB_OFF (24u)
+
+/** \brief Length for Ifx_PSI5_TSR_Bits.TBS */
+#define IFX_PSI5_TSR_TBS_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5_TSR_Bits.TBS */
+#define IFX_PSI5_TSR_TBS_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5_TSR_Bits.TBS */
+#define IFX_PSI5_TSR_TBS_OFF (27u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXPSI5_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPsi5_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPsi5_reg.h
new file mode 100644
index 0000000..702ca23
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPsi5_reg.h
@@ -0,0 +1,1832 @@
+/**
+ * \file IfxPsi5_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Psi5_Cfg Psi5 address
+ * \ingroup IfxLld_Psi5
+ *
+ * \defgroup IfxLld_Psi5_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Psi5_Cfg
+ *
+ * \defgroup IfxLld_Psi5_Cfg_Psi5 2-PSI5
+ * \ingroup IfxLld_Psi5_Cfg
+ *
+ */
+#ifndef IFXPSI5_REG_H
+#define IFXPSI5_REG_H 1
+/******************************************************************************/
+#include "IfxPsi5_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Psi5_Cfg_BaseAddress
+ * \{ */
+
+/** \brief PSI5 object */
+#define MODULE_PSI5 /*lint --e(923)*/ (*(Ifx_PSI5*)0xF0005000u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Psi5_Cfg_Psi5
+ * \{ */
+
+/** \brief 3D0, Access Enable Register 0 */
+#define PSI5_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_ACCEN0*)0xF00053D0u)
+
+/** \brief 3D4, Access Enable Register 1 */
+#define PSI5_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_ACCEN1*)0xF00053D4u)
+
+/** \brief 8C, Channel Trigger Value Register */
+#define PSI5_CH0_CTV /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_CTV*)0xF000508Cu)
+
+/** Alias (User Manual Name) for PSI5_CH0_CTV.
+* To use register names with standard convension, please use PSI5_CH0_CTV.
+*/
+#define PSI5_CTV0 (PSI5_CH0_CTV)
+
+/** \brief 30, Input and Output Control Register */
+#define PSI5_CH0_IOCR /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_IOCR*)0xF0005030u)
+
+/** Alias (User Manual Name) for PSI5_CH0_IOCR.
+* To use register names with standard convension, please use PSI5_CH0_IOCR.
+*/
+#define PSI5_IOCR0 (PSI5_CH0_IOCR)
+
+/** \brief 88, Pulse Generation Control Register */
+#define PSI5_CH0_PGC /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_PGC*)0xF0005088u)
+
+/** Alias (User Manual Name) for PSI5_CH0_PGC.
+* To use register names with standard convension, please use PSI5_CH0_PGC.
+*/
+#define PSI5_PGC0 (PSI5_CH0_PGC)
+
+/** \brief 34, Receiver Control Register A */
+#define PSI5_CH0_RCRA /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_RCRA*)0xF0005034u)
+
+/** Alias (User Manual Name) for PSI5_CH0_RCRA.
+* To use register names with standard convension, please use PSI5_CH0_RCRA.
+*/
+#define PSI5_RCRA0 (PSI5_CH0_RCRA)
+
+/** \brief 38, Receiver Control Register B */
+#define PSI5_CH0_RCRB /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_RCRB*)0xF0005038u)
+
+/** Alias (User Manual Name) for PSI5_CH0_RCRB.
+* To use register names with standard convension, please use PSI5_CH0_RCRB.
+*/
+#define PSI5_RCRB0 (PSI5_CH0_RCRB)
+
+/** \brief 3C, Receiver Control Register C */
+#define PSI5_CH0_RCRC /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_RCRC*)0xF000503Cu)
+
+/** Alias (User Manual Name) for PSI5_CH0_RCRC.
+* To use register names with standard convension, please use PSI5_CH0_RCRC.
+*/
+#define PSI5_RCRC0 (PSI5_CH0_RCRC)
+
+/** \brief 84, Receive Data Register High */
+#define PSI5_CH0_RDRH /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_RDRH*)0xF0005084u)
+
+/** Alias (User Manual Name) for PSI5_CH0_RDRH.
+* To use register names with standard convension, please use PSI5_CH0_RDRH.
+*/
+#define PSI5_RDRH0 (PSI5_CH0_RDRH)
+
+/** \brief 80, Receive Data Register Low */
+#define PSI5_CH0_RDRL /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_RDRL*)0xF0005080u)
+
+/** Alias (User Manual Name) for PSI5_CH0_RDRL.
+* To use register names with standard convension, please use PSI5_CH0_RDRL.
+*/
+#define PSI5_RDRL0 (PSI5_CH0_RDRL)
+
+/** \brief 5C, Receive Status Register */
+#define PSI5_CH0_RSR /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_RSR*)0xF000505Cu)
+
+/** Alias (User Manual Name) for PSI5_CH0_RSR.
+* To use register names with standard convension, please use PSI5_CH0_RSR.
+*/
+#define PSI5_RSR0 (PSI5_CH0_RSR)
+
+/** \brief 90, Send Control Register */
+#define PSI5_CH0_SCR /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_SCR*)0xF0005090u)
+
+/** Alias (User Manual Name) for PSI5_CH0_SCR.
+* To use register names with standard convension, please use PSI5_CH0_SCR.
+*/
+#define PSI5_SCR0 (PSI5_CH0_SCR)
+
+/** \brief 98, Send Data Register High */
+#define PSI5_CH0_SDRH /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_SDRH*)0xF0005098u)
+
+/** Alias (User Manual Name) for PSI5_CH0_SDRH.
+* To use register names with standard convension, please use PSI5_CH0_SDRH.
+*/
+#define PSI5_SDRH0 (PSI5_CH0_SDRH)
+
+/** \brief 94, Send Data Register Low */
+#define PSI5_CH0_SDRL /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_SDRL*)0xF0005094u)
+
+/** Alias (User Manual Name) for PSI5_CH0_SDRL.
+* To use register names with standard convension, please use PSI5_CH0_SDRL.
+*/
+#define PSI5_SDRL0 (PSI5_CH0_SDRL)
+
+/** \brief 60, Serial Data and Status Register */
+#define PSI5_CH0_SDS0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_SDS*)0xF0005060u)
+
+/** Alias (User Manual Name) for PSI5_CH0_SDS0.
+* To use register names with standard convension, please use PSI5_CH0_SDS0.
+*/
+#define PSI5_SDS00 (PSI5_CH0_SDS0)
+
+/** \brief 64, Serial Data and Status Register */
+#define PSI5_CH0_SDS1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_SDS*)0xF0005064u)
+
+/** Alias (User Manual Name) for PSI5_CH0_SDS1.
+* To use register names with standard convension, please use PSI5_CH0_SDS1.
+*/
+#define PSI5_SDS01 (PSI5_CH0_SDS1)
+
+/** \brief 68, Serial Data and Status Register */
+#define PSI5_CH0_SDS2 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_SDS*)0xF0005068u)
+
+/** Alias (User Manual Name) for PSI5_CH0_SDS2.
+* To use register names with standard convension, please use PSI5_CH0_SDS2.
+*/
+#define PSI5_SDS02 (PSI5_CH0_SDS2)
+
+/** \brief 6C, Serial Data and Status Register */
+#define PSI5_CH0_SDS3 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_SDS*)0xF000506Cu)
+
+/** Alias (User Manual Name) for PSI5_CH0_SDS3.
+* To use register names with standard convension, please use PSI5_CH0_SDS3.
+*/
+#define PSI5_SDS03 (PSI5_CH0_SDS3)
+
+/** \brief 70, Serial Data and Status Register */
+#define PSI5_CH0_SDS4 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_SDS*)0xF0005070u)
+
+/** Alias (User Manual Name) for PSI5_CH0_SDS4.
+* To use register names with standard convension, please use PSI5_CH0_SDS4.
+*/
+#define PSI5_SDS04 (PSI5_CH0_SDS4)
+
+/** \brief 74, Serial Data and Status Register */
+#define PSI5_CH0_SDS5 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_SDS*)0xF0005074u)
+
+/** Alias (User Manual Name) for PSI5_CH0_SDS5.
+* To use register names with standard convension, please use PSI5_CH0_SDS5.
+*/
+#define PSI5_SDS05 (PSI5_CH0_SDS5)
+
+/** \brief 7C, SOF TS Capture Register SFTSC */
+#define PSI5_CH0_SFTSC /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_SFTSC*)0xF000507Cu)
+
+/** Alias (User Manual Name) for PSI5_CH0_SFTSC.
+* To use register names with standard convension, please use PSI5_CH0_SFTSC.
+*/
+#define PSI5_SFTSC0 (PSI5_CH0_SFTSC)
+
+/** \brief A8, Send Output Register High */
+#define PSI5_CH0_SORH /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_SORH*)0xF00050A8u)
+
+/** Alias (User Manual Name) for PSI5_CH0_SORH.
+* To use register names with standard convension, please use PSI5_CH0_SORH.
+*/
+#define PSI5_SORH0 (PSI5_CH0_SORH)
+
+/** \brief A4, Send Output Register Low */
+#define PSI5_CH0_SORL /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_SORL*)0xF00050A4u)
+
+/** Alias (User Manual Name) for PSI5_CH0_SORL.
+* To use register names with standard convension, please use PSI5_CH0_SORL.
+*/
+#define PSI5_SORL0 (PSI5_CH0_SORL)
+
+/** \brief 78, SOP TS Capture Register SPTSC */
+#define PSI5_CH0_SPTSC /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_SPTSC*)0xF0005078u)
+
+/** Alias (User Manual Name) for PSI5_CH0_SPTSC.
+* To use register names with standard convension, please use PSI5_CH0_SPTSC.
+*/
+#define PSI5_SPTSC0 (PSI5_CH0_SPTSC)
+
+/** \brief A0, Send Shift Register High */
+#define PSI5_CH0_SSRH /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_SSRH*)0xF00050A0u)
+
+/** Alias (User Manual Name) for PSI5_CH0_SSRH.
+* To use register names with standard convension, please use PSI5_CH0_SSRH.
+*/
+#define PSI5_SSRH0 (PSI5_CH0_SSRH)
+
+/** \brief 9C, Send Shift Register Low */
+#define PSI5_CH0_SSRL /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_SSRL*)0xF000509Cu)
+
+/** Alias (User Manual Name) for PSI5_CH0_SSRL.
+* To use register names with standard convension, please use PSI5_CH0_SSRL.
+*/
+#define PSI5_SSRL0 (PSI5_CH0_SSRL)
+
+/** \brief 40, Watch Dog Timer Register */
+#define PSI5_CH0_WDT0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_WDT*)0xF0005040u)
+
+/** Alias (User Manual Name) for PSI5_CH0_WDT0.
+* To use register names with standard convension, please use PSI5_CH0_WDT0.
+*/
+#define PSI5_WDT00 (PSI5_CH0_WDT0)
+
+/** \brief 44, Watch Dog Timer Register */
+#define PSI5_CH0_WDT1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_WDT*)0xF0005044u)
+
+/** Alias (User Manual Name) for PSI5_CH0_WDT1.
+* To use register names with standard convension, please use PSI5_CH0_WDT1.
+*/
+#define PSI5_WDT01 (PSI5_CH0_WDT1)
+
+/** \brief 48, Watch Dog Timer Register */
+#define PSI5_CH0_WDT2 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_WDT*)0xF0005048u)
+
+/** Alias (User Manual Name) for PSI5_CH0_WDT2.
+* To use register names with standard convension, please use PSI5_CH0_WDT2.
+*/
+#define PSI5_WDT02 (PSI5_CH0_WDT2)
+
+/** \brief 4C, Watch Dog Timer Register */
+#define PSI5_CH0_WDT3 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_WDT*)0xF000504Cu)
+
+/** Alias (User Manual Name) for PSI5_CH0_WDT3.
+* To use register names with standard convension, please use PSI5_CH0_WDT3.
+*/
+#define PSI5_WDT03 (PSI5_CH0_WDT3)
+
+/** \brief 50, Watch Dog Timer Register */
+#define PSI5_CH0_WDT4 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_WDT*)0xF0005050u)
+
+/** Alias (User Manual Name) for PSI5_CH0_WDT4.
+* To use register names with standard convension, please use PSI5_CH0_WDT4.
+*/
+#define PSI5_WDT04 (PSI5_CH0_WDT4)
+
+/** \brief 54, Watch Dog Timer Register */
+#define PSI5_CH0_WDT5 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_WDT*)0xF0005054u)
+
+/** Alias (User Manual Name) for PSI5_CH0_WDT5.
+* To use register names with standard convension, please use PSI5_CH0_WDT5.
+*/
+#define PSI5_WDT05 (PSI5_CH0_WDT5)
+
+/** \brief 58, Watch Dog Timer Register */
+#define PSI5_CH0_WDT6 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_WDT*)0xF0005058u)
+
+/** Alias (User Manual Name) for PSI5_CH0_WDT6.
+* To use register names with standard convension, please use PSI5_CH0_WDT6.
+*/
+#define PSI5_WDT06 (PSI5_CH0_WDT6)
+
+/** \brief 11C, Channel Trigger Value Register */
+#define PSI5_CH1_CTV /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_CTV*)0xF000511Cu)
+
+/** Alias (User Manual Name) for PSI5_CH1_CTV.
+* To use register names with standard convension, please use PSI5_CH1_CTV.
+*/
+#define PSI5_CTV1 (PSI5_CH1_CTV)
+
+/** \brief C0, Input and Output Control Register */
+#define PSI5_CH1_IOCR /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_IOCR*)0xF00050C0u)
+
+/** Alias (User Manual Name) for PSI5_CH1_IOCR.
+* To use register names with standard convension, please use PSI5_CH1_IOCR.
+*/
+#define PSI5_IOCR1 (PSI5_CH1_IOCR)
+
+/** \brief 118, Pulse Generation Control Register */
+#define PSI5_CH1_PGC /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_PGC*)0xF0005118u)
+
+/** Alias (User Manual Name) for PSI5_CH1_PGC.
+* To use register names with standard convension, please use PSI5_CH1_PGC.
+*/
+#define PSI5_PGC1 (PSI5_CH1_PGC)
+
+/** \brief C4, Receiver Control Register A */
+#define PSI5_CH1_RCRA /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_RCRA*)0xF00050C4u)
+
+/** Alias (User Manual Name) for PSI5_CH1_RCRA.
+* To use register names with standard convension, please use PSI5_CH1_RCRA.
+*/
+#define PSI5_RCRA1 (PSI5_CH1_RCRA)
+
+/** \brief C8, Receiver Control Register B */
+#define PSI5_CH1_RCRB /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_RCRB*)0xF00050C8u)
+
+/** Alias (User Manual Name) for PSI5_CH1_RCRB.
+* To use register names with standard convension, please use PSI5_CH1_RCRB.
+*/
+#define PSI5_RCRB1 (PSI5_CH1_RCRB)
+
+/** \brief CC, Receiver Control Register C */
+#define PSI5_CH1_RCRC /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_RCRC*)0xF00050CCu)
+
+/** Alias (User Manual Name) for PSI5_CH1_RCRC.
+* To use register names with standard convension, please use PSI5_CH1_RCRC.
+*/
+#define PSI5_RCRC1 (PSI5_CH1_RCRC)
+
+/** \brief 114, Receive Data Register High */
+#define PSI5_CH1_RDRH /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_RDRH*)0xF0005114u)
+
+/** Alias (User Manual Name) for PSI5_CH1_RDRH.
+* To use register names with standard convension, please use PSI5_CH1_RDRH.
+*/
+#define PSI5_RDRH1 (PSI5_CH1_RDRH)
+
+/** \brief 110, Receive Data Register Low */
+#define PSI5_CH1_RDRL /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_RDRL*)0xF0005110u)
+
+/** Alias (User Manual Name) for PSI5_CH1_RDRL.
+* To use register names with standard convension, please use PSI5_CH1_RDRL.
+*/
+#define PSI5_RDRL1 (PSI5_CH1_RDRL)
+
+/** \brief EC, Receive Status Register */
+#define PSI5_CH1_RSR /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_RSR*)0xF00050ECu)
+
+/** Alias (User Manual Name) for PSI5_CH1_RSR.
+* To use register names with standard convension, please use PSI5_CH1_RSR.
+*/
+#define PSI5_RSR1 (PSI5_CH1_RSR)
+
+/** \brief 120, Send Control Register */
+#define PSI5_CH1_SCR /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_SCR*)0xF0005120u)
+
+/** Alias (User Manual Name) for PSI5_CH1_SCR.
+* To use register names with standard convension, please use PSI5_CH1_SCR.
+*/
+#define PSI5_SCR1 (PSI5_CH1_SCR)
+
+/** \brief 128, Send Data Register High */
+#define PSI5_CH1_SDRH /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_SDRH*)0xF0005128u)
+
+/** Alias (User Manual Name) for PSI5_CH1_SDRH.
+* To use register names with standard convension, please use PSI5_CH1_SDRH.
+*/
+#define PSI5_SDRH1 (PSI5_CH1_SDRH)
+
+/** \brief 124, Send Data Register Low */
+#define PSI5_CH1_SDRL /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_SDRL*)0xF0005124u)
+
+/** Alias (User Manual Name) for PSI5_CH1_SDRL.
+* To use register names with standard convension, please use PSI5_CH1_SDRL.
+*/
+#define PSI5_SDRL1 (PSI5_CH1_SDRL)
+
+/** \brief F0, Serial Data and Status Register */
+#define PSI5_CH1_SDS0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_SDS*)0xF00050F0u)
+
+/** Alias (User Manual Name) for PSI5_CH1_SDS0.
+* To use register names with standard convension, please use PSI5_CH1_SDS0.
+*/
+#define PSI5_SDS10 (PSI5_CH1_SDS0)
+
+/** \brief F4, Serial Data and Status Register */
+#define PSI5_CH1_SDS1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_SDS*)0xF00050F4u)
+
+/** Alias (User Manual Name) for PSI5_CH1_SDS1.
+* To use register names with standard convension, please use PSI5_CH1_SDS1.
+*/
+#define PSI5_SDS11 (PSI5_CH1_SDS1)
+
+/** \brief F8, Serial Data and Status Register */
+#define PSI5_CH1_SDS2 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_SDS*)0xF00050F8u)
+
+/** Alias (User Manual Name) for PSI5_CH1_SDS2.
+* To use register names with standard convension, please use PSI5_CH1_SDS2.
+*/
+#define PSI5_SDS12 (PSI5_CH1_SDS2)
+
+/** \brief FC, Serial Data and Status Register */
+#define PSI5_CH1_SDS3 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_SDS*)0xF00050FCu)
+
+/** Alias (User Manual Name) for PSI5_CH1_SDS3.
+* To use register names with standard convension, please use PSI5_CH1_SDS3.
+*/
+#define PSI5_SDS13 (PSI5_CH1_SDS3)
+
+/** \brief 100, Serial Data and Status Register */
+#define PSI5_CH1_SDS4 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_SDS*)0xF0005100u)
+
+/** Alias (User Manual Name) for PSI5_CH1_SDS4.
+* To use register names with standard convension, please use PSI5_CH1_SDS4.
+*/
+#define PSI5_SDS14 (PSI5_CH1_SDS4)
+
+/** \brief 104, Serial Data and Status Register */
+#define PSI5_CH1_SDS5 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_SDS*)0xF0005104u)
+
+/** Alias (User Manual Name) for PSI5_CH1_SDS5.
+* To use register names with standard convension, please use PSI5_CH1_SDS5.
+*/
+#define PSI5_SDS15 (PSI5_CH1_SDS5)
+
+/** \brief 10C, SOF TS Capture Register SFTSC */
+#define PSI5_CH1_SFTSC /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_SFTSC*)0xF000510Cu)
+
+/** Alias (User Manual Name) for PSI5_CH1_SFTSC.
+* To use register names with standard convension, please use PSI5_CH1_SFTSC.
+*/
+#define PSI5_SFTSC1 (PSI5_CH1_SFTSC)
+
+/** \brief 138, Send Output Register High */
+#define PSI5_CH1_SORH /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_SORH*)0xF0005138u)
+
+/** Alias (User Manual Name) for PSI5_CH1_SORH.
+* To use register names with standard convension, please use PSI5_CH1_SORH.
+*/
+#define PSI5_SORH1 (PSI5_CH1_SORH)
+
+/** \brief 134, Send Output Register Low */
+#define PSI5_CH1_SORL /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_SORL*)0xF0005134u)
+
+/** Alias (User Manual Name) for PSI5_CH1_SORL.
+* To use register names with standard convension, please use PSI5_CH1_SORL.
+*/
+#define PSI5_SORL1 (PSI5_CH1_SORL)
+
+/** \brief 108, SOP TS Capture Register SPTSC */
+#define PSI5_CH1_SPTSC /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_SPTSC*)0xF0005108u)
+
+/** Alias (User Manual Name) for PSI5_CH1_SPTSC.
+* To use register names with standard convension, please use PSI5_CH1_SPTSC.
+*/
+#define PSI5_SPTSC1 (PSI5_CH1_SPTSC)
+
+/** \brief 130, Send Shift Register High */
+#define PSI5_CH1_SSRH /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_SSRH*)0xF0005130u)
+
+/** Alias (User Manual Name) for PSI5_CH1_SSRH.
+* To use register names with standard convension, please use PSI5_CH1_SSRH.
+*/
+#define PSI5_SSRH1 (PSI5_CH1_SSRH)
+
+/** \brief 12C, Send Shift Register Low */
+#define PSI5_CH1_SSRL /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_SSRL*)0xF000512Cu)
+
+/** Alias (User Manual Name) for PSI5_CH1_SSRL.
+* To use register names with standard convension, please use PSI5_CH1_SSRL.
+*/
+#define PSI5_SSRL1 (PSI5_CH1_SSRL)
+
+/** \brief D0, Watch Dog Timer Register */
+#define PSI5_CH1_WDT0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_WDT*)0xF00050D0u)
+
+/** Alias (User Manual Name) for PSI5_CH1_WDT0.
+* To use register names with standard convension, please use PSI5_CH1_WDT0.
+*/
+#define PSI5_WDT10 (PSI5_CH1_WDT0)
+
+/** \brief D4, Watch Dog Timer Register */
+#define PSI5_CH1_WDT1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_WDT*)0xF00050D4u)
+
+/** Alias (User Manual Name) for PSI5_CH1_WDT1.
+* To use register names with standard convension, please use PSI5_CH1_WDT1.
+*/
+#define PSI5_WDT11 (PSI5_CH1_WDT1)
+
+/** \brief D8, Watch Dog Timer Register */
+#define PSI5_CH1_WDT2 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_WDT*)0xF00050D8u)
+
+/** Alias (User Manual Name) for PSI5_CH1_WDT2.
+* To use register names with standard convension, please use PSI5_CH1_WDT2.
+*/
+#define PSI5_WDT12 (PSI5_CH1_WDT2)
+
+/** \brief DC, Watch Dog Timer Register */
+#define PSI5_CH1_WDT3 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_WDT*)0xF00050DCu)
+
+/** Alias (User Manual Name) for PSI5_CH1_WDT3.
+* To use register names with standard convension, please use PSI5_CH1_WDT3.
+*/
+#define PSI5_WDT13 (PSI5_CH1_WDT3)
+
+/** \brief E0, Watch Dog Timer Register */
+#define PSI5_CH1_WDT4 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_WDT*)0xF00050E0u)
+
+/** Alias (User Manual Name) for PSI5_CH1_WDT4.
+* To use register names with standard convension, please use PSI5_CH1_WDT4.
+*/
+#define PSI5_WDT14 (PSI5_CH1_WDT4)
+
+/** \brief E4, Watch Dog Timer Register */
+#define PSI5_CH1_WDT5 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_WDT*)0xF00050E4u)
+
+/** Alias (User Manual Name) for PSI5_CH1_WDT5.
+* To use register names with standard convension, please use PSI5_CH1_WDT5.
+*/
+#define PSI5_WDT15 (PSI5_CH1_WDT5)
+
+/** \brief E8, Watch Dog Timer Register */
+#define PSI5_CH1_WDT6 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CH_WDT*)0xF00050E8u)
+
+/** Alias (User Manual Name) for PSI5_CH1_WDT6.
+* To use register names with standard convension, please use PSI5_CH1_WDT6.
+*/
+#define PSI5_WDT16 (PSI5_CH1_WDT6)
+
+/** \brief 0, Clock Control Register */
+#define PSI5_CLC /*lint --e(923)*/ (*(volatile Ifx_PSI5_CLC*)0xF0005000u)
+
+/** \brief 59C, CRCIOV Clear Register */
+#define PSI5_CRCICLR0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CRCICLR*)0xF000559Cu)
+
+/** \brief 5A0, CRCIOV Clear Register */
+#define PSI5_CRCICLR1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CRCICLR*)0xF00055A0u)
+
+/** \brief 45C, CRCI Overview Register */
+#define PSI5_CRCIOV0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CRCIOV*)0xF000545Cu)
+
+/** \brief 460, CRCI Overview Register */
+#define PSI5_CRCIOV1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CRCIOV*)0xF0005460u)
+
+/** \brief 4FC, CRCIOV Set Register */
+#define PSI5_CRCISET0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CRCISET*)0xF00054FCu)
+
+/** \brief 500, CRCIOV Set Register */
+#define PSI5_CRCISET1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_CRCISET*)0xF0005500u)
+
+/** \brief C, PSI5 Fractional Divider Register */
+#define PSI5_FDR /*lint --e(923)*/ (*(volatile Ifx_PSI5_FDR*)0xF000500Cu)
+
+/** \brief 14, Fractional Divider Register for Higher Bit Rate */
+#define PSI5_FDRH /*lint --e(923)*/ (*(volatile Ifx_PSI5_FDRH*)0xF0005014u)
+
+/** \brief 10, Fractional Divider Register for Lower Bit Rate */
+#define PSI5_FDRL /*lint --e(923)*/ (*(volatile Ifx_PSI5_FDRL*)0xF0005010u)
+
+/** \brief 18, Fractional Divider Register for Time Stamp */
+#define PSI5_FDRT /*lint --e(923)*/ (*(volatile Ifx_PSI5_FDRT*)0xF0005018u)
+
+/** \brief 2C, Global Control Register */
+#define PSI5_GCR /*lint --e(923)*/ (*(volatile Ifx_PSI5_GCR*)0xF000502Cu)
+
+/** \brief 8, Module Identification Register */
+#define PSI5_ID /*lint --e(923)*/ (*(volatile Ifx_PSI5_ID*)0xF0005008u)
+
+/** \brief 2FC, Interrupt Node Pointer Register */
+#define PSI5_INP0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_INP*)0xF00052FCu)
+
+/** \brief 300, Interrupt Node Pointer Register */
+#define PSI5_INP1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_INP*)0xF0005300u)
+
+/** \brief 360, Interrupt Clear Register A */
+#define PSI5_INTCLRA0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_INTCLRA*)0xF0005360u)
+
+/** \brief 364, Interrupt Clear Register A */
+#define PSI5_INTCLRA1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_INTCLRA*)0xF0005364u)
+
+/** \brief 374, Interrupt Clear Register A */
+#define PSI5_INTCLRB0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_INTCLRB*)0xF0005374u)
+
+/** \brief 378, Interrupt Clear Register A */
+#define PSI5_INTCLRB1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_INTCLRB*)0xF0005378u)
+
+/** \brief 388, Interrupt Enable Register A */
+#define PSI5_INTENA0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_INTENA*)0xF0005388u)
+
+/** \brief 38C, Interrupt Enable Register A */
+#define PSI5_INTENA1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_INTENA*)0xF000538Cu)
+
+/** \brief 39C, Interrupt Enable Register B */
+#define PSI5_INTENB0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_INTENB*)0xF000539Cu)
+
+/** \brief 3A0, Interrupt Enable Register B */
+#define PSI5_INTENB1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_INTENB*)0xF00053A0u)
+
+/** \brief 2F8, Interrupt Overview Register */
+#define PSI5_INTOV /*lint --e(923)*/ (*(volatile Ifx_PSI5_INTOV*)0xF00052F8u)
+
+/** \brief 338, Interrupt Set Register A */
+#define PSI5_INTSETA0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_INTSETA*)0xF0005338u)
+
+/** \brief 33C, Interrupt Set Register A */
+#define PSI5_INTSETA1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_INTSETA*)0xF000533Cu)
+
+/** \brief 34C, Interrupt Set Register B */
+#define PSI5_INTSETB0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_INTSETB*)0xF000534Cu)
+
+/** \brief 350, Interrupt Set Register B */
+#define PSI5_INTSETB1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_INTSETB*)0xF0005350u)
+
+/** \brief 310, Interrupt Status Register A */
+#define PSI5_INTSTATA0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_INTSTATA*)0xF0005310u)
+
+/** \brief 314, Interrupt Status Register A */
+#define PSI5_INTSTATA1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_INTSTATA*)0xF0005314u)
+
+/** \brief 324, Interrupt Status Register B */
+#define PSI5_INTSTATB0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_INTSTATB*)0xF0005324u)
+
+/** \brief 328, Interrupt Status Register B */
+#define PSI5_INTSTATB1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_INTSTATB*)0xF0005328u)
+
+/** \brief 3D8, Kernel Reset Register 0 */
+#define PSI5_KRST0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_KRST0*)0xF00053D8u)
+
+/** \brief 3DC, Kernel Reset Register 1 */
+#define PSI5_KRST1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_KRST1*)0xF00053DCu)
+
+/** \brief 3E0, Kernel Reset Status Clear Register */
+#define PSI5_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_PSI5_KRSTCLR*)0xF00053E0u)
+
+/** \brief 5D8, MEIOV Clear Register */
+#define PSI5_MEICLR0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_MEICLR*)0xF00055D8u)
+
+/** \brief 5DC, MEIOV Clear Register */
+#define PSI5_MEICLR1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_MEICLR*)0xF00055DCu)
+
+/** \brief 498, MEI Overview Register */
+#define PSI5_MEIOV0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_MEIOV*)0xF0005498u)
+
+/** \brief 49C, MEI Overview Register */
+#define PSI5_MEIOV1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_MEIOV*)0xF000549Cu)
+
+/** \brief 538, MEIOV Set Register */
+#define PSI5_MEISET0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_MEISET*)0xF0005538u)
+
+/** \brief 53C, MEIOV Set Register */
+#define PSI5_MEISET1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_MEISET*)0xF000553Cu)
+
+/** \brief 574, NBIOV Clear Register */
+#define PSI5_NBICLR0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_NBICLR*)0xF0005574u)
+
+/** \brief 578, NBIOV Clear Register */
+#define PSI5_NBICLR1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_NBICLR*)0xF0005578u)
+
+/** \brief 434, NBI Overview Register */
+#define PSI5_NBIOV0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_NBIOV*)0xF0005434u)
+
+/** \brief 438, NBI Overview Register */
+#define PSI5_NBIOV1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_NBIOV*)0xF0005438u)
+
+/** \brief 4D4, NBIOV Set Register */
+#define PSI5_NBISET0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_NBISET*)0xF00054D4u)
+
+/** \brief 4D8, NBIOV Set Register */
+#define PSI5_NBISET1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_NBISET*)0xF00054D8u)
+
+/** \brief 5C4, NFIOV Clear Register */
+#define PSI5_NFICLR0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_NFICLR*)0xF00055C4u)
+
+/** \brief 5C8, NFIOV Clear Register */
+#define PSI5_NFICLR1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_NFICLR*)0xF00055C8u)
+
+/** \brief 484, NFI Overview Register */
+#define PSI5_NFIOV0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_NFIOV*)0xF0005484u)
+
+/** \brief 488, NFI Overview Register */
+#define PSI5_NFIOV1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_NFIOV*)0xF0005488u)
+
+/** \brief 524, NFIOV Set Register */
+#define PSI5_NFISET0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_NFISET*)0xF0005524u)
+
+/** \brief 528, NFIOV Set Register */
+#define PSI5_NFISET1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_NFISET*)0xF0005528u)
+
+/** \brief 3CC, OCDS Control and Status */
+#define PSI5_OCS /*lint --e(923)*/ (*(volatile Ifx_PSI5_OCS*)0xF00053CCu)
+
+/** \brief 3F8, Receive Data FIFO */
+#define PSI5_RDF0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDF*)0xF00053F8u)
+
+/** \brief 3FC, Receive Data FIFO */
+#define PSI5_RDF1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDF*)0xF00053FCu)
+
+/** \brief 5B0, RDIOV Clear Register */
+#define PSI5_RDICLR0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDICLR*)0xF00055B0u)
+
+/** \brief 5B4, RDIOV Clear Register */
+#define PSI5_RDICLR1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDICLR*)0xF00055B4u)
+
+/** \brief 470, RDI Overview Register */
+#define PSI5_RDIOV0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDIOV*)0xF0005470u)
+
+/** \brief 474, RDI Overview Register */
+#define PSI5_RDIOV1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDIOV*)0xF0005474u)
+
+/** \brief 510, RDIOV Set Register */
+#define PSI5_RDISET0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDISET*)0xF0005510u)
+
+/** \brief 514, RDIOV Set Register */
+#define PSI5_RDISET1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDISET*)0xF0005514u)
+
+/** \brief 604, Receive Data Memory High */
+#define PSI5_RDM0_0_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF0005604u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_0_H.
+* To use register names with standard convension, please use PSI5_RDM0_0_H.
+*/
+#define PSI5_RDMH00 (PSI5_RDM0_0_H)
+
+/** \brief 600, Receive Data Memory Low */
+#define PSI5_RDM0_0_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005600u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_0_L.
+* To use register names with standard convension, please use PSI5_RDM0_0_L.
+*/
+#define PSI5_RDML00 (PSI5_RDM0_0_L)
+
+/** \brief 654, Receive Data Memory High */
+#define PSI5_RDM0_10_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF0005654u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_10_H.
+* To use register names with standard convension, please use PSI5_RDM0_10_H.
+*/
+#define PSI5_RDMH010 (PSI5_RDM0_10_H)
+
+/** \brief 650, Receive Data Memory Low */
+#define PSI5_RDM0_10_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005650u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_10_L.
+* To use register names with standard convension, please use PSI5_RDM0_10_L.
+*/
+#define PSI5_RDML010 (PSI5_RDM0_10_L)
+
+/** \brief 65C, Receive Data Memory High */
+#define PSI5_RDM0_11_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF000565Cu)
+
+/** Alias (User Manual Name) for PSI5_RDM0_11_H.
+* To use register names with standard convension, please use PSI5_RDM0_11_H.
+*/
+#define PSI5_RDMH011 (PSI5_RDM0_11_H)
+
+/** \brief 658, Receive Data Memory Low */
+#define PSI5_RDM0_11_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005658u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_11_L.
+* To use register names with standard convension, please use PSI5_RDM0_11_L.
+*/
+#define PSI5_RDML011 (PSI5_RDM0_11_L)
+
+/** \brief 664, Receive Data Memory High */
+#define PSI5_RDM0_12_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF0005664u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_12_H.
+* To use register names with standard convension, please use PSI5_RDM0_12_H.
+*/
+#define PSI5_RDMH012 (PSI5_RDM0_12_H)
+
+/** \brief 660, Receive Data Memory Low */
+#define PSI5_RDM0_12_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005660u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_12_L.
+* To use register names with standard convension, please use PSI5_RDM0_12_L.
+*/
+#define PSI5_RDML012 (PSI5_RDM0_12_L)
+
+/** \brief 66C, Receive Data Memory High */
+#define PSI5_RDM0_13_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF000566Cu)
+
+/** Alias (User Manual Name) for PSI5_RDM0_13_H.
+* To use register names with standard convension, please use PSI5_RDM0_13_H.
+*/
+#define PSI5_RDMH013 (PSI5_RDM0_13_H)
+
+/** \brief 668, Receive Data Memory Low */
+#define PSI5_RDM0_13_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005668u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_13_L.
+* To use register names with standard convension, please use PSI5_RDM0_13_L.
+*/
+#define PSI5_RDML013 (PSI5_RDM0_13_L)
+
+/** \brief 674, Receive Data Memory High */
+#define PSI5_RDM0_14_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF0005674u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_14_H.
+* To use register names with standard convension, please use PSI5_RDM0_14_H.
+*/
+#define PSI5_RDMH014 (PSI5_RDM0_14_H)
+
+/** \brief 670, Receive Data Memory Low */
+#define PSI5_RDM0_14_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005670u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_14_L.
+* To use register names with standard convension, please use PSI5_RDM0_14_L.
+*/
+#define PSI5_RDML014 (PSI5_RDM0_14_L)
+
+/** \brief 67C, Receive Data Memory High */
+#define PSI5_RDM0_15_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF000567Cu)
+
+/** Alias (User Manual Name) for PSI5_RDM0_15_H.
+* To use register names with standard convension, please use PSI5_RDM0_15_H.
+*/
+#define PSI5_RDMH015 (PSI5_RDM0_15_H)
+
+/** \brief 678, Receive Data Memory Low */
+#define PSI5_RDM0_15_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005678u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_15_L.
+* To use register names with standard convension, please use PSI5_RDM0_15_L.
+*/
+#define PSI5_RDML015 (PSI5_RDM0_15_L)
+
+/** \brief 684, Receive Data Memory High */
+#define PSI5_RDM0_16_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF0005684u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_16_H.
+* To use register names with standard convension, please use PSI5_RDM0_16_H.
+*/
+#define PSI5_RDMH016 (PSI5_RDM0_16_H)
+
+/** \brief 680, Receive Data Memory Low */
+#define PSI5_RDM0_16_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005680u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_16_L.
+* To use register names with standard convension, please use PSI5_RDM0_16_L.
+*/
+#define PSI5_RDML016 (PSI5_RDM0_16_L)
+
+/** \brief 68C, Receive Data Memory High */
+#define PSI5_RDM0_17_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF000568Cu)
+
+/** Alias (User Manual Name) for PSI5_RDM0_17_H.
+* To use register names with standard convension, please use PSI5_RDM0_17_H.
+*/
+#define PSI5_RDMH017 (PSI5_RDM0_17_H)
+
+/** \brief 688, Receive Data Memory Low */
+#define PSI5_RDM0_17_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005688u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_17_L.
+* To use register names with standard convension, please use PSI5_RDM0_17_L.
+*/
+#define PSI5_RDML017 (PSI5_RDM0_17_L)
+
+/** \brief 694, Receive Data Memory High */
+#define PSI5_RDM0_18_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF0005694u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_18_H.
+* To use register names with standard convension, please use PSI5_RDM0_18_H.
+*/
+#define PSI5_RDMH018 (PSI5_RDM0_18_H)
+
+/** \brief 690, Receive Data Memory Low */
+#define PSI5_RDM0_18_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005690u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_18_L.
+* To use register names with standard convension, please use PSI5_RDM0_18_L.
+*/
+#define PSI5_RDML018 (PSI5_RDM0_18_L)
+
+/** \brief 69C, Receive Data Memory High */
+#define PSI5_RDM0_19_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF000569Cu)
+
+/** Alias (User Manual Name) for PSI5_RDM0_19_H.
+* To use register names with standard convension, please use PSI5_RDM0_19_H.
+*/
+#define PSI5_RDMH019 (PSI5_RDM0_19_H)
+
+/** \brief 698, Receive Data Memory Low */
+#define PSI5_RDM0_19_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005698u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_19_L.
+* To use register names with standard convension, please use PSI5_RDM0_19_L.
+*/
+#define PSI5_RDML019 (PSI5_RDM0_19_L)
+
+/** \brief 60C, Receive Data Memory High */
+#define PSI5_RDM0_1_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF000560Cu)
+
+/** Alias (User Manual Name) for PSI5_RDM0_1_H.
+* To use register names with standard convension, please use PSI5_RDM0_1_H.
+*/
+#define PSI5_RDMH01 (PSI5_RDM0_1_H)
+
+/** \brief 608, Receive Data Memory Low */
+#define PSI5_RDM0_1_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005608u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_1_L.
+* To use register names with standard convension, please use PSI5_RDM0_1_L.
+*/
+#define PSI5_RDML01 (PSI5_RDM0_1_L)
+
+/** \brief 6A4, Receive Data Memory High */
+#define PSI5_RDM0_20_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF00056A4u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_20_H.
+* To use register names with standard convension, please use PSI5_RDM0_20_H.
+*/
+#define PSI5_RDMH020 (PSI5_RDM0_20_H)
+
+/** \brief 6A0, Receive Data Memory Low */
+#define PSI5_RDM0_20_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF00056A0u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_20_L.
+* To use register names with standard convension, please use PSI5_RDM0_20_L.
+*/
+#define PSI5_RDML020 (PSI5_RDM0_20_L)
+
+/** \brief 6AC, Receive Data Memory High */
+#define PSI5_RDM0_21_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF00056ACu)
+
+/** Alias (User Manual Name) for PSI5_RDM0_21_H.
+* To use register names with standard convension, please use PSI5_RDM0_21_H.
+*/
+#define PSI5_RDMH021 (PSI5_RDM0_21_H)
+
+/** \brief 6A8, Receive Data Memory Low */
+#define PSI5_RDM0_21_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF00056A8u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_21_L.
+* To use register names with standard convension, please use PSI5_RDM0_21_L.
+*/
+#define PSI5_RDML021 (PSI5_RDM0_21_L)
+
+/** \brief 6B4, Receive Data Memory High */
+#define PSI5_RDM0_22_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF00056B4u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_22_H.
+* To use register names with standard convension, please use PSI5_RDM0_22_H.
+*/
+#define PSI5_RDMH022 (PSI5_RDM0_22_H)
+
+/** \brief 6B0, Receive Data Memory Low */
+#define PSI5_RDM0_22_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF00056B0u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_22_L.
+* To use register names with standard convension, please use PSI5_RDM0_22_L.
+*/
+#define PSI5_RDML022 (PSI5_RDM0_22_L)
+
+/** \brief 6BC, Receive Data Memory High */
+#define PSI5_RDM0_23_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF00056BCu)
+
+/** Alias (User Manual Name) for PSI5_RDM0_23_H.
+* To use register names with standard convension, please use PSI5_RDM0_23_H.
+*/
+#define PSI5_RDMH023 (PSI5_RDM0_23_H)
+
+/** \brief 6B8, Receive Data Memory Low */
+#define PSI5_RDM0_23_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF00056B8u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_23_L.
+* To use register names with standard convension, please use PSI5_RDM0_23_L.
+*/
+#define PSI5_RDML023 (PSI5_RDM0_23_L)
+
+/** \brief 6C4, Receive Data Memory High */
+#define PSI5_RDM0_24_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF00056C4u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_24_H.
+* To use register names with standard convension, please use PSI5_RDM0_24_H.
+*/
+#define PSI5_RDMH024 (PSI5_RDM0_24_H)
+
+/** \brief 6C0, Receive Data Memory Low */
+#define PSI5_RDM0_24_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF00056C0u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_24_L.
+* To use register names with standard convension, please use PSI5_RDM0_24_L.
+*/
+#define PSI5_RDML024 (PSI5_RDM0_24_L)
+
+/** \brief 6CC, Receive Data Memory High */
+#define PSI5_RDM0_25_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF00056CCu)
+
+/** Alias (User Manual Name) for PSI5_RDM0_25_H.
+* To use register names with standard convension, please use PSI5_RDM0_25_H.
+*/
+#define PSI5_RDMH025 (PSI5_RDM0_25_H)
+
+/** \brief 6C8, Receive Data Memory Low */
+#define PSI5_RDM0_25_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF00056C8u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_25_L.
+* To use register names with standard convension, please use PSI5_RDM0_25_L.
+*/
+#define PSI5_RDML025 (PSI5_RDM0_25_L)
+
+/** \brief 6D4, Receive Data Memory High */
+#define PSI5_RDM0_26_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF00056D4u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_26_H.
+* To use register names with standard convension, please use PSI5_RDM0_26_H.
+*/
+#define PSI5_RDMH026 (PSI5_RDM0_26_H)
+
+/** \brief 6D0, Receive Data Memory Low */
+#define PSI5_RDM0_26_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF00056D0u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_26_L.
+* To use register names with standard convension, please use PSI5_RDM0_26_L.
+*/
+#define PSI5_RDML026 (PSI5_RDM0_26_L)
+
+/** \brief 6DC, Receive Data Memory High */
+#define PSI5_RDM0_27_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF00056DCu)
+
+/** Alias (User Manual Name) for PSI5_RDM0_27_H.
+* To use register names with standard convension, please use PSI5_RDM0_27_H.
+*/
+#define PSI5_RDMH027 (PSI5_RDM0_27_H)
+
+/** \brief 6D8, Receive Data Memory Low */
+#define PSI5_RDM0_27_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF00056D8u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_27_L.
+* To use register names with standard convension, please use PSI5_RDM0_27_L.
+*/
+#define PSI5_RDML027 (PSI5_RDM0_27_L)
+
+/** \brief 6E4, Receive Data Memory High */
+#define PSI5_RDM0_28_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF00056E4u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_28_H.
+* To use register names with standard convension, please use PSI5_RDM0_28_H.
+*/
+#define PSI5_RDMH028 (PSI5_RDM0_28_H)
+
+/** \brief 6E0, Receive Data Memory Low */
+#define PSI5_RDM0_28_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF00056E0u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_28_L.
+* To use register names with standard convension, please use PSI5_RDM0_28_L.
+*/
+#define PSI5_RDML028 (PSI5_RDM0_28_L)
+
+/** \brief 6EC, Receive Data Memory High */
+#define PSI5_RDM0_29_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF00056ECu)
+
+/** Alias (User Manual Name) for PSI5_RDM0_29_H.
+* To use register names with standard convension, please use PSI5_RDM0_29_H.
+*/
+#define PSI5_RDMH029 (PSI5_RDM0_29_H)
+
+/** \brief 6E8, Receive Data Memory Low */
+#define PSI5_RDM0_29_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF00056E8u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_29_L.
+* To use register names with standard convension, please use PSI5_RDM0_29_L.
+*/
+#define PSI5_RDML029 (PSI5_RDM0_29_L)
+
+/** \brief 614, Receive Data Memory High */
+#define PSI5_RDM0_2_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF0005614u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_2_H.
+* To use register names with standard convension, please use PSI5_RDM0_2_H.
+*/
+#define PSI5_RDMH02 (PSI5_RDM0_2_H)
+
+/** \brief 610, Receive Data Memory Low */
+#define PSI5_RDM0_2_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005610u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_2_L.
+* To use register names with standard convension, please use PSI5_RDM0_2_L.
+*/
+#define PSI5_RDML02 (PSI5_RDM0_2_L)
+
+/** \brief 6F4, Receive Data Memory High */
+#define PSI5_RDM0_30_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF00056F4u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_30_H.
+* To use register names with standard convension, please use PSI5_RDM0_30_H.
+*/
+#define PSI5_RDMH030 (PSI5_RDM0_30_H)
+
+/** \brief 6F0, Receive Data Memory Low */
+#define PSI5_RDM0_30_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF00056F0u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_30_L.
+* To use register names with standard convension, please use PSI5_RDM0_30_L.
+*/
+#define PSI5_RDML030 (PSI5_RDM0_30_L)
+
+/** \brief 6FC, Receive Data Memory High */
+#define PSI5_RDM0_31_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF00056FCu)
+
+/** Alias (User Manual Name) for PSI5_RDM0_31_H.
+* To use register names with standard convension, please use PSI5_RDM0_31_H.
+*/
+#define PSI5_RDMH031 (PSI5_RDM0_31_H)
+
+/** \brief 6F8, Receive Data Memory Low */
+#define PSI5_RDM0_31_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF00056F8u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_31_L.
+* To use register names with standard convension, please use PSI5_RDM0_31_L.
+*/
+#define PSI5_RDML031 (PSI5_RDM0_31_L)
+
+/** \brief 61C, Receive Data Memory High */
+#define PSI5_RDM0_3_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF000561Cu)
+
+/** Alias (User Manual Name) for PSI5_RDM0_3_H.
+* To use register names with standard convension, please use PSI5_RDM0_3_H.
+*/
+#define PSI5_RDMH03 (PSI5_RDM0_3_H)
+
+/** \brief 618, Receive Data Memory Low */
+#define PSI5_RDM0_3_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005618u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_3_L.
+* To use register names with standard convension, please use PSI5_RDM0_3_L.
+*/
+#define PSI5_RDML03 (PSI5_RDM0_3_L)
+
+/** \brief 624, Receive Data Memory High */
+#define PSI5_RDM0_4_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF0005624u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_4_H.
+* To use register names with standard convension, please use PSI5_RDM0_4_H.
+*/
+#define PSI5_RDMH04 (PSI5_RDM0_4_H)
+
+/** \brief 620, Receive Data Memory Low */
+#define PSI5_RDM0_4_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005620u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_4_L.
+* To use register names with standard convension, please use PSI5_RDM0_4_L.
+*/
+#define PSI5_RDML04 (PSI5_RDM0_4_L)
+
+/** \brief 62C, Receive Data Memory High */
+#define PSI5_RDM0_5_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF000562Cu)
+
+/** Alias (User Manual Name) for PSI5_RDM0_5_H.
+* To use register names with standard convension, please use PSI5_RDM0_5_H.
+*/
+#define PSI5_RDMH05 (PSI5_RDM0_5_H)
+
+/** \brief 628, Receive Data Memory Low */
+#define PSI5_RDM0_5_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005628u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_5_L.
+* To use register names with standard convension, please use PSI5_RDM0_5_L.
+*/
+#define PSI5_RDML05 (PSI5_RDM0_5_L)
+
+/** \brief 634, Receive Data Memory High */
+#define PSI5_RDM0_6_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF0005634u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_6_H.
+* To use register names with standard convension, please use PSI5_RDM0_6_H.
+*/
+#define PSI5_RDMH06 (PSI5_RDM0_6_H)
+
+/** \brief 630, Receive Data Memory Low */
+#define PSI5_RDM0_6_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005630u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_6_L.
+* To use register names with standard convension, please use PSI5_RDM0_6_L.
+*/
+#define PSI5_RDML06 (PSI5_RDM0_6_L)
+
+/** \brief 63C, Receive Data Memory High */
+#define PSI5_RDM0_7_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF000563Cu)
+
+/** Alias (User Manual Name) for PSI5_RDM0_7_H.
+* To use register names with standard convension, please use PSI5_RDM0_7_H.
+*/
+#define PSI5_RDMH07 (PSI5_RDM0_7_H)
+
+/** \brief 638, Receive Data Memory Low */
+#define PSI5_RDM0_7_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005638u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_7_L.
+* To use register names with standard convension, please use PSI5_RDM0_7_L.
+*/
+#define PSI5_RDML07 (PSI5_RDM0_7_L)
+
+/** \brief 644, Receive Data Memory High */
+#define PSI5_RDM0_8_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF0005644u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_8_H.
+* To use register names with standard convension, please use PSI5_RDM0_8_H.
+*/
+#define PSI5_RDMH08 (PSI5_RDM0_8_H)
+
+/** \brief 640, Receive Data Memory Low */
+#define PSI5_RDM0_8_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005640u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_8_L.
+* To use register names with standard convension, please use PSI5_RDM0_8_L.
+*/
+#define PSI5_RDML08 (PSI5_RDM0_8_L)
+
+/** \brief 64C, Receive Data Memory High */
+#define PSI5_RDM0_9_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF000564Cu)
+
+/** Alias (User Manual Name) for PSI5_RDM0_9_H.
+* To use register names with standard convension, please use PSI5_RDM0_9_H.
+*/
+#define PSI5_RDMH09 (PSI5_RDM0_9_H)
+
+/** \brief 648, Receive Data Memory Low */
+#define PSI5_RDM0_9_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005648u)
+
+/** Alias (User Manual Name) for PSI5_RDM0_9_L.
+* To use register names with standard convension, please use PSI5_RDM0_9_L.
+*/
+#define PSI5_RDML09 (PSI5_RDM0_9_L)
+
+/** \brief 704, Receive Data Memory High */
+#define PSI5_RDM1_0_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF0005704u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_0_H.
+* To use register names with standard convension, please use PSI5_RDM1_0_H.
+*/
+#define PSI5_RDMH10 (PSI5_RDM1_0_H)
+
+/** \brief 700, Receive Data Memory Low */
+#define PSI5_RDM1_0_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005700u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_0_L.
+* To use register names with standard convension, please use PSI5_RDM1_0_L.
+*/
+#define PSI5_RDML10 (PSI5_RDM1_0_L)
+
+/** \brief 754, Receive Data Memory High */
+#define PSI5_RDM1_10_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF0005754u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_10_H.
+* To use register names with standard convension, please use PSI5_RDM1_10_H.
+*/
+#define PSI5_RDMH110 (PSI5_RDM1_10_H)
+
+/** \brief 750, Receive Data Memory Low */
+#define PSI5_RDM1_10_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005750u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_10_L.
+* To use register names with standard convension, please use PSI5_RDM1_10_L.
+*/
+#define PSI5_RDML110 (PSI5_RDM1_10_L)
+
+/** \brief 75C, Receive Data Memory High */
+#define PSI5_RDM1_11_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF000575Cu)
+
+/** Alias (User Manual Name) for PSI5_RDM1_11_H.
+* To use register names with standard convension, please use PSI5_RDM1_11_H.
+*/
+#define PSI5_RDMH111 (PSI5_RDM1_11_H)
+
+/** \brief 758, Receive Data Memory Low */
+#define PSI5_RDM1_11_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005758u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_11_L.
+* To use register names with standard convension, please use PSI5_RDM1_11_L.
+*/
+#define PSI5_RDML111 (PSI5_RDM1_11_L)
+
+/** \brief 764, Receive Data Memory High */
+#define PSI5_RDM1_12_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF0005764u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_12_H.
+* To use register names with standard convension, please use PSI5_RDM1_12_H.
+*/
+#define PSI5_RDMH112 (PSI5_RDM1_12_H)
+
+/** \brief 760, Receive Data Memory Low */
+#define PSI5_RDM1_12_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005760u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_12_L.
+* To use register names with standard convension, please use PSI5_RDM1_12_L.
+*/
+#define PSI5_RDML112 (PSI5_RDM1_12_L)
+
+/** \brief 76C, Receive Data Memory High */
+#define PSI5_RDM1_13_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF000576Cu)
+
+/** Alias (User Manual Name) for PSI5_RDM1_13_H.
+* To use register names with standard convension, please use PSI5_RDM1_13_H.
+*/
+#define PSI5_RDMH113 (PSI5_RDM1_13_H)
+
+/** \brief 768, Receive Data Memory Low */
+#define PSI5_RDM1_13_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005768u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_13_L.
+* To use register names with standard convension, please use PSI5_RDM1_13_L.
+*/
+#define PSI5_RDML113 (PSI5_RDM1_13_L)
+
+/** \brief 774, Receive Data Memory High */
+#define PSI5_RDM1_14_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF0005774u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_14_H.
+* To use register names with standard convension, please use PSI5_RDM1_14_H.
+*/
+#define PSI5_RDMH114 (PSI5_RDM1_14_H)
+
+/** \brief 770, Receive Data Memory Low */
+#define PSI5_RDM1_14_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005770u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_14_L.
+* To use register names with standard convension, please use PSI5_RDM1_14_L.
+*/
+#define PSI5_RDML114 (PSI5_RDM1_14_L)
+
+/** \brief 77C, Receive Data Memory High */
+#define PSI5_RDM1_15_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF000577Cu)
+
+/** Alias (User Manual Name) for PSI5_RDM1_15_H.
+* To use register names with standard convension, please use PSI5_RDM1_15_H.
+*/
+#define PSI5_RDMH115 (PSI5_RDM1_15_H)
+
+/** \brief 778, Receive Data Memory Low */
+#define PSI5_RDM1_15_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005778u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_15_L.
+* To use register names with standard convension, please use PSI5_RDM1_15_L.
+*/
+#define PSI5_RDML115 (PSI5_RDM1_15_L)
+
+/** \brief 784, Receive Data Memory High */
+#define PSI5_RDM1_16_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF0005784u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_16_H.
+* To use register names with standard convension, please use PSI5_RDM1_16_H.
+*/
+#define PSI5_RDMH116 (PSI5_RDM1_16_H)
+
+/** \brief 780, Receive Data Memory Low */
+#define PSI5_RDM1_16_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005780u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_16_L.
+* To use register names with standard convension, please use PSI5_RDM1_16_L.
+*/
+#define PSI5_RDML116 (PSI5_RDM1_16_L)
+
+/** \brief 78C, Receive Data Memory High */
+#define PSI5_RDM1_17_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF000578Cu)
+
+/** Alias (User Manual Name) for PSI5_RDM1_17_H.
+* To use register names with standard convension, please use PSI5_RDM1_17_H.
+*/
+#define PSI5_RDMH117 (PSI5_RDM1_17_H)
+
+/** \brief 788, Receive Data Memory Low */
+#define PSI5_RDM1_17_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005788u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_17_L.
+* To use register names with standard convension, please use PSI5_RDM1_17_L.
+*/
+#define PSI5_RDML117 (PSI5_RDM1_17_L)
+
+/** \brief 794, Receive Data Memory High */
+#define PSI5_RDM1_18_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF0005794u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_18_H.
+* To use register names with standard convension, please use PSI5_RDM1_18_H.
+*/
+#define PSI5_RDMH118 (PSI5_RDM1_18_H)
+
+/** \brief 790, Receive Data Memory Low */
+#define PSI5_RDM1_18_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005790u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_18_L.
+* To use register names with standard convension, please use PSI5_RDM1_18_L.
+*/
+#define PSI5_RDML118 (PSI5_RDM1_18_L)
+
+/** \brief 79C, Receive Data Memory High */
+#define PSI5_RDM1_19_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF000579Cu)
+
+/** Alias (User Manual Name) for PSI5_RDM1_19_H.
+* To use register names with standard convension, please use PSI5_RDM1_19_H.
+*/
+#define PSI5_RDMH119 (PSI5_RDM1_19_H)
+
+/** \brief 798, Receive Data Memory Low */
+#define PSI5_RDM1_19_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005798u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_19_L.
+* To use register names with standard convension, please use PSI5_RDM1_19_L.
+*/
+#define PSI5_RDML119 (PSI5_RDM1_19_L)
+
+/** \brief 70C, Receive Data Memory High */
+#define PSI5_RDM1_1_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF000570Cu)
+
+/** Alias (User Manual Name) for PSI5_RDM1_1_H.
+* To use register names with standard convension, please use PSI5_RDM1_1_H.
+*/
+#define PSI5_RDMH11 (PSI5_RDM1_1_H)
+
+/** \brief 708, Receive Data Memory Low */
+#define PSI5_RDM1_1_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005708u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_1_L.
+* To use register names with standard convension, please use PSI5_RDM1_1_L.
+*/
+#define PSI5_RDML11 (PSI5_RDM1_1_L)
+
+/** \brief 7A4, Receive Data Memory High */
+#define PSI5_RDM1_20_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF00057A4u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_20_H.
+* To use register names with standard convension, please use PSI5_RDM1_20_H.
+*/
+#define PSI5_RDMH120 (PSI5_RDM1_20_H)
+
+/** \brief 7A0, Receive Data Memory Low */
+#define PSI5_RDM1_20_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF00057A0u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_20_L.
+* To use register names with standard convension, please use PSI5_RDM1_20_L.
+*/
+#define PSI5_RDML120 (PSI5_RDM1_20_L)
+
+/** \brief 7AC, Receive Data Memory High */
+#define PSI5_RDM1_21_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF00057ACu)
+
+/** Alias (User Manual Name) for PSI5_RDM1_21_H.
+* To use register names with standard convension, please use PSI5_RDM1_21_H.
+*/
+#define PSI5_RDMH121 (PSI5_RDM1_21_H)
+
+/** \brief 7A8, Receive Data Memory Low */
+#define PSI5_RDM1_21_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF00057A8u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_21_L.
+* To use register names with standard convension, please use PSI5_RDM1_21_L.
+*/
+#define PSI5_RDML121 (PSI5_RDM1_21_L)
+
+/** \brief 7B4, Receive Data Memory High */
+#define PSI5_RDM1_22_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF00057B4u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_22_H.
+* To use register names with standard convension, please use PSI5_RDM1_22_H.
+*/
+#define PSI5_RDMH122 (PSI5_RDM1_22_H)
+
+/** \brief 7B0, Receive Data Memory Low */
+#define PSI5_RDM1_22_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF00057B0u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_22_L.
+* To use register names with standard convension, please use PSI5_RDM1_22_L.
+*/
+#define PSI5_RDML122 (PSI5_RDM1_22_L)
+
+/** \brief 7BC, Receive Data Memory High */
+#define PSI5_RDM1_23_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF00057BCu)
+
+/** Alias (User Manual Name) for PSI5_RDM1_23_H.
+* To use register names with standard convension, please use PSI5_RDM1_23_H.
+*/
+#define PSI5_RDMH123 (PSI5_RDM1_23_H)
+
+/** \brief 7B8, Receive Data Memory Low */
+#define PSI5_RDM1_23_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF00057B8u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_23_L.
+* To use register names with standard convension, please use PSI5_RDM1_23_L.
+*/
+#define PSI5_RDML123 (PSI5_RDM1_23_L)
+
+/** \brief 7C4, Receive Data Memory High */
+#define PSI5_RDM1_24_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF00057C4u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_24_H.
+* To use register names with standard convension, please use PSI5_RDM1_24_H.
+*/
+#define PSI5_RDMH124 (PSI5_RDM1_24_H)
+
+/** \brief 7C0, Receive Data Memory Low */
+#define PSI5_RDM1_24_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF00057C0u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_24_L.
+* To use register names with standard convension, please use PSI5_RDM1_24_L.
+*/
+#define PSI5_RDML124 (PSI5_RDM1_24_L)
+
+/** \brief 7CC, Receive Data Memory High */
+#define PSI5_RDM1_25_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF00057CCu)
+
+/** Alias (User Manual Name) for PSI5_RDM1_25_H.
+* To use register names with standard convension, please use PSI5_RDM1_25_H.
+*/
+#define PSI5_RDMH125 (PSI5_RDM1_25_H)
+
+/** \brief 7C8, Receive Data Memory Low */
+#define PSI5_RDM1_25_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF00057C8u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_25_L.
+* To use register names with standard convension, please use PSI5_RDM1_25_L.
+*/
+#define PSI5_RDML125 (PSI5_RDM1_25_L)
+
+/** \brief 7D4, Receive Data Memory High */
+#define PSI5_RDM1_26_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF00057D4u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_26_H.
+* To use register names with standard convension, please use PSI5_RDM1_26_H.
+*/
+#define PSI5_RDMH126 (PSI5_RDM1_26_H)
+
+/** \brief 7D0, Receive Data Memory Low */
+#define PSI5_RDM1_26_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF00057D0u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_26_L.
+* To use register names with standard convension, please use PSI5_RDM1_26_L.
+*/
+#define PSI5_RDML126 (PSI5_RDM1_26_L)
+
+/** \brief 7DC, Receive Data Memory High */
+#define PSI5_RDM1_27_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF00057DCu)
+
+/** Alias (User Manual Name) for PSI5_RDM1_27_H.
+* To use register names with standard convension, please use PSI5_RDM1_27_H.
+*/
+#define PSI5_RDMH127 (PSI5_RDM1_27_H)
+
+/** \brief 7D8, Receive Data Memory Low */
+#define PSI5_RDM1_27_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF00057D8u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_27_L.
+* To use register names with standard convension, please use PSI5_RDM1_27_L.
+*/
+#define PSI5_RDML127 (PSI5_RDM1_27_L)
+
+/** \brief 7E4, Receive Data Memory High */
+#define PSI5_RDM1_28_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF00057E4u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_28_H.
+* To use register names with standard convension, please use PSI5_RDM1_28_H.
+*/
+#define PSI5_RDMH128 (PSI5_RDM1_28_H)
+
+/** \brief 7E0, Receive Data Memory Low */
+#define PSI5_RDM1_28_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF00057E0u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_28_L.
+* To use register names with standard convension, please use PSI5_RDM1_28_L.
+*/
+#define PSI5_RDML128 (PSI5_RDM1_28_L)
+
+/** \brief 7EC, Receive Data Memory High */
+#define PSI5_RDM1_29_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF00057ECu)
+
+/** Alias (User Manual Name) for PSI5_RDM1_29_H.
+* To use register names with standard convension, please use PSI5_RDM1_29_H.
+*/
+#define PSI5_RDMH129 (PSI5_RDM1_29_H)
+
+/** \brief 7E8, Receive Data Memory Low */
+#define PSI5_RDM1_29_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF00057E8u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_29_L.
+* To use register names with standard convension, please use PSI5_RDM1_29_L.
+*/
+#define PSI5_RDML129 (PSI5_RDM1_29_L)
+
+/** \brief 714, Receive Data Memory High */
+#define PSI5_RDM1_2_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF0005714u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_2_H.
+* To use register names with standard convension, please use PSI5_RDM1_2_H.
+*/
+#define PSI5_RDMH12 (PSI5_RDM1_2_H)
+
+/** \brief 710, Receive Data Memory Low */
+#define PSI5_RDM1_2_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005710u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_2_L.
+* To use register names with standard convension, please use PSI5_RDM1_2_L.
+*/
+#define PSI5_RDML12 (PSI5_RDM1_2_L)
+
+/** \brief 7F4, Receive Data Memory High */
+#define PSI5_RDM1_30_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF00057F4u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_30_H.
+* To use register names with standard convension, please use PSI5_RDM1_30_H.
+*/
+#define PSI5_RDMH130 (PSI5_RDM1_30_H)
+
+/** \brief 7F0, Receive Data Memory Low */
+#define PSI5_RDM1_30_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF00057F0u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_30_L.
+* To use register names with standard convension, please use PSI5_RDM1_30_L.
+*/
+#define PSI5_RDML130 (PSI5_RDM1_30_L)
+
+/** \brief 7FC, Receive Data Memory High */
+#define PSI5_RDM1_31_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF00057FCu)
+
+/** Alias (User Manual Name) for PSI5_RDM1_31_H.
+* To use register names with standard convension, please use PSI5_RDM1_31_H.
+*/
+#define PSI5_RDMH131 (PSI5_RDM1_31_H)
+
+/** \brief 7F8, Receive Data Memory Low */
+#define PSI5_RDM1_31_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF00057F8u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_31_L.
+* To use register names with standard convension, please use PSI5_RDM1_31_L.
+*/
+#define PSI5_RDML131 (PSI5_RDM1_31_L)
+
+/** \brief 71C, Receive Data Memory High */
+#define PSI5_RDM1_3_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF000571Cu)
+
+/** Alias (User Manual Name) for PSI5_RDM1_3_H.
+* To use register names with standard convension, please use PSI5_RDM1_3_H.
+*/
+#define PSI5_RDMH13 (PSI5_RDM1_3_H)
+
+/** \brief 718, Receive Data Memory Low */
+#define PSI5_RDM1_3_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005718u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_3_L.
+* To use register names with standard convension, please use PSI5_RDM1_3_L.
+*/
+#define PSI5_RDML13 (PSI5_RDM1_3_L)
+
+/** \brief 724, Receive Data Memory High */
+#define PSI5_RDM1_4_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF0005724u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_4_H.
+* To use register names with standard convension, please use PSI5_RDM1_4_H.
+*/
+#define PSI5_RDMH14 (PSI5_RDM1_4_H)
+
+/** \brief 720, Receive Data Memory Low */
+#define PSI5_RDM1_4_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005720u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_4_L.
+* To use register names with standard convension, please use PSI5_RDM1_4_L.
+*/
+#define PSI5_RDML14 (PSI5_RDM1_4_L)
+
+/** \brief 72C, Receive Data Memory High */
+#define PSI5_RDM1_5_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF000572Cu)
+
+/** Alias (User Manual Name) for PSI5_RDM1_5_H.
+* To use register names with standard convension, please use PSI5_RDM1_5_H.
+*/
+#define PSI5_RDMH15 (PSI5_RDM1_5_H)
+
+/** \brief 728, Receive Data Memory Low */
+#define PSI5_RDM1_5_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005728u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_5_L.
+* To use register names with standard convension, please use PSI5_RDM1_5_L.
+*/
+#define PSI5_RDML15 (PSI5_RDM1_5_L)
+
+/** \brief 734, Receive Data Memory High */
+#define PSI5_RDM1_6_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF0005734u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_6_H.
+* To use register names with standard convension, please use PSI5_RDM1_6_H.
+*/
+#define PSI5_RDMH16 (PSI5_RDM1_6_H)
+
+/** \brief 730, Receive Data Memory Low */
+#define PSI5_RDM1_6_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005730u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_6_L.
+* To use register names with standard convension, please use PSI5_RDM1_6_L.
+*/
+#define PSI5_RDML16 (PSI5_RDM1_6_L)
+
+/** \brief 73C, Receive Data Memory High */
+#define PSI5_RDM1_7_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF000573Cu)
+
+/** Alias (User Manual Name) for PSI5_RDM1_7_H.
+* To use register names with standard convension, please use PSI5_RDM1_7_H.
+*/
+#define PSI5_RDMH17 (PSI5_RDM1_7_H)
+
+/** \brief 738, Receive Data Memory Low */
+#define PSI5_RDM1_7_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005738u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_7_L.
+* To use register names with standard convension, please use PSI5_RDM1_7_L.
+*/
+#define PSI5_RDML17 (PSI5_RDM1_7_L)
+
+/** \brief 744, Receive Data Memory High */
+#define PSI5_RDM1_8_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF0005744u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_8_H.
+* To use register names with standard convension, please use PSI5_RDM1_8_H.
+*/
+#define PSI5_RDMH18 (PSI5_RDM1_8_H)
+
+/** \brief 740, Receive Data Memory Low */
+#define PSI5_RDM1_8_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005740u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_8_L.
+* To use register names with standard convension, please use PSI5_RDM1_8_L.
+*/
+#define PSI5_RDML18 (PSI5_RDM1_8_L)
+
+/** \brief 74C, Receive Data Memory High */
+#define PSI5_RDM1_9_H /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_H*)0xF000574Cu)
+
+/** Alias (User Manual Name) for PSI5_RDM1_9_H.
+* To use register names with standard convension, please use PSI5_RDM1_9_H.
+*/
+#define PSI5_RDMH19 (PSI5_RDM1_9_H)
+
+/** \brief 748, Receive Data Memory Low */
+#define PSI5_RDM1_9_L /*lint --e(923)*/ (*(volatile Ifx_PSI5_RDM_L*)0xF0005748u)
+
+/** Alias (User Manual Name) for PSI5_RDM1_9_L.
+* To use register names with standard convension, please use PSI5_RDM1_9_L.
+*/
+#define PSI5_RDML19 (PSI5_RDM1_9_L)
+
+/** \brief 3E4, Receive FIFO Control Register */
+#define PSI5_RFC0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_RFC*)0xF00053E4u)
+
+/** \brief 3E8, Receive FIFO Control Register */
+#define PSI5_RFC1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_RFC*)0xF00053E8u)
+
+/** \brief 560, RMIOV Clear Register */
+#define PSI5_RMICLR0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_RMICLR*)0xF0005560u)
+
+/** \brief 564, RMIOV Clear Register */
+#define PSI5_RMICLR1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_RMICLR*)0xF0005564u)
+
+/** \brief 420, RMI Overview Register */
+#define PSI5_RMIOV0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_RMIOV*)0xF0005420u)
+
+/** \brief 424, RMI Overview Register */
+#define PSI5_RMIOV1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_RMIOV*)0xF0005424u)
+
+/** \brief 4C0, RMIOV Set Register */
+#define PSI5_RMISET0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_RMISET*)0xF00054C0u)
+
+/** \brief 4C4, RMIOV Set Register */
+#define PSI5_RMISET1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_RMISET*)0xF00054C4u)
+
+/** \brief 54C, RSIOV Clear Register */
+#define PSI5_RSICLR0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_RSICLR*)0xF000554Cu)
+
+/** \brief 550, RSIOV Clear Register */
+#define PSI5_RSICLR1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_RSICLR*)0xF0005550u)
+
+/** \brief 40C, RSI Overview Register */
+#define PSI5_RSIOV0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_RSIOV*)0xF000540Cu)
+
+/** \brief 410, RSI Overview Register */
+#define PSI5_RSIOV1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_RSIOV*)0xF0005410u)
+
+/** \brief 4AC, RSIOV Set Register */
+#define PSI5_RSISET0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_RSISET*)0xF00054ACu)
+
+/** \brief 4B0, RSIOV Set Register */
+#define PSI5_RSISET1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_RSISET*)0xF00054B0u)
+
+/** \brief 588, TEIOV Clear Register */
+#define PSI5_TEICLR0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_TEICLR*)0xF0005588u)
+
+/** \brief 58C, TEIOV Clear Register */
+#define PSI5_TEICLR1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_TEICLR*)0xF000558Cu)
+
+/** \brief 448, TEI Overview Register */
+#define PSI5_TEIOV0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_TEIOV*)0xF0005448u)
+
+/** \brief 44C, TEI Overview Register */
+#define PSI5_TEIOV1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_TEIOV*)0xF000544Cu)
+
+/** \brief 4E8, TEIOV Set Register */
+#define PSI5_TEISET0 /*lint --e(923)*/ (*(volatile Ifx_PSI5_TEISET*)0xF00054E8u)
+
+/** \brief 4EC, TEIOV Set Register */
+#define PSI5_TEISET1 /*lint --e(923)*/ (*(volatile Ifx_PSI5_TEISET*)0xF00054ECu)
+
+/** \brief 1C, Time Stamp Register A */
+#define PSI5_TSRA /*lint --e(923)*/ (*(volatile Ifx_PSI5_TSR*)0xF000501Cu)
+
+/** \brief 20, Time Stamp Register B */
+#define PSI5_TSRB /*lint --e(923)*/ (*(volatile Ifx_PSI5_TSR*)0xF0005020u)
+
+/** \brief 24, Time Stamp Register C */
+#define PSI5_TSRC /*lint --e(923)*/ (*(volatile Ifx_PSI5_TSR*)0xF0005024u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXPSI5_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPsi5_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPsi5_regdef.h
new file mode 100644
index 0000000..6c035ed
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPsi5_regdef.h
@@ -0,0 +1,2510 @@
+/**
+ * \file IfxPsi5_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Psi5 Psi5
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Psi5_Bitfields Bitfields
+ * \ingroup IfxLld_Psi5
+ *
+ * \defgroup IfxLld_Psi5_union Union
+ * \ingroup IfxLld_Psi5
+ *
+ * \defgroup IfxLld_Psi5_struct Struct
+ * \ingroup IfxLld_Psi5
+ *
+ */
+#ifndef IFXPSI5_REGDEF_H
+#define IFXPSI5_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Psi5_Bitfields
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef struct _Ifx_PSI5_ACCEN0_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_PSI5_ACCEN0_Bits;
+
+/** \brief Access Enable Register 1 */
+typedef struct _Ifx_PSI5_ACCEN1_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_PSI5_ACCEN1_Bits;
+
+/** \brief Channel Trigger Value Register */
+typedef struct _Ifx_PSI5_CH_CTV_Bits
+{
+ unsigned int CTV:16; /**< \brief [15:0] Channel Trigger Value CTV (rw) */
+ unsigned int CTC:16; /**< \brief [31:16] Channel Trigger Counter (rw) */
+} Ifx_PSI5_CH_CTV_Bits;
+
+/** \brief Input and Output Control Register */
+typedef struct _Ifx_PSI5_CH_IOCR_Bits
+{
+ unsigned int ALTI:2; /**< \brief [1:0] Alternate Input Select (rw) */
+ unsigned int reserved_2:2; /**< \brief \internal Reserved */
+ unsigned int DEPTH:4; /**< \brief [7:4] Digital Glitch Filter Depth (rw) */
+ unsigned int OIE:1; /**< \brief [8:8] Output Inverter Enable Channel x (rw) */
+ unsigned int IIE:1; /**< \brief [9:9] Input Inverter Enable Channel x (rw) */
+ unsigned int reserved_10:2; /**< \brief \internal Reserved */
+ unsigned int REG:1; /**< \brief [12:12] Rising Edge Glitch Flag for Channel x (rh) */
+ unsigned int FEG:1; /**< \brief [13:13] Falling Edge Glitch Flag for Channel x (rh) */
+ unsigned int CREG:1; /**< \brief [14:14] Clear Rising Edge Glitch Flag for Channel x (w) */
+ unsigned int CFEG:1; /**< \brief [15:15] Clear Falling Edge Glitch Flag for Channel x (w) */
+ unsigned int reserved_16:14; /**< \brief \internal Reserved */
+ unsigned int RXM:1; /**< \brief [30:30] Receive Monitor for Channel x (rh) */
+ unsigned int TXM:1; /**< \brief [31:31] Transmit Monitor for Channel x (rh) */
+} Ifx_PSI5_CH_IOCR_Bits;
+
+/** \brief Pulse Generation Control Register */
+typedef struct _Ifx_PSI5_CH_PGC_Bits
+{
+ unsigned int PLEN:6; /**< \brief [5:0] Pulse Length (rw) */
+ unsigned int reserved_6:2; /**< \brief \internal Reserved */
+ unsigned int DEL:6; /**< \brief [13:8] Delay Length (rw) */
+ unsigned int reserved_14:1; /**< \brief \internal Reserved */
+ unsigned int TBS:1; /**< \brief [15:15] Time Base Select (rw) */
+ unsigned int ETB:3; /**< \brief [18:16] External Time Base Select (rw) */
+ unsigned int PTE:1; /**< \brief [19:19] Periodic Trigger Enable (rw) */
+ unsigned int ETS:3; /**< \brief [22:20] External Trigger Select (rw) */
+ unsigned int ETE:1; /**< \brief [23:23] External Trigger Enable (rw) */
+ unsigned int BYP:1; /**< \brief [24:24] Bypass Enable (rw) */
+ unsigned int BOT:7; /**< \brief [31:25] Blank Out Time (rw) */
+} Ifx_PSI5_CH_PGC_Bits;
+
+/** \brief Receiver Control Register A */
+typedef struct _Ifx_PSI5_CH_RCRA_Bits
+{
+ unsigned int PDL0:5; /**< \brief [4:0] Payload Data Length (rw) */
+ unsigned int PDL1:5; /**< \brief [9:5] Payload Data Length (rw) */
+ unsigned int PDL2:5; /**< \brief [14:10] Payload Data Length (rw) */
+ unsigned int PDL3:5; /**< \brief [19:15] Payload Data Length (rw) */
+ unsigned int PDL4:5; /**< \brief [24:20] Payload Data Length (rw) */
+ unsigned int PDL5:5; /**< \brief [29:25] Payload Data Length (rw) */
+ unsigned int ASYN:1; /**< \brief [30:30] Asynchronous Mode (rw) */
+ unsigned int AVBS:1; /**< \brief [31:31] Verbose Mode for Asynchronous Mode (rw) */
+} Ifx_PSI5_CH_RCRA_Bits;
+
+/** \brief Receiver Control Register B */
+typedef struct _Ifx_PSI5_CH_RCRB_Bits
+{
+ unsigned int MSG0:1; /**< \brief [0:0] Messaging Bits (rw) */
+ unsigned int CRC0:1; /**< \brief [1:1] CRC or Parity Selection (rw) */
+ unsigned int FEC0:1; /**< \brief [2:2] Frame Expectation Control (rw) */
+ unsigned int VBS0:1; /**< \brief [3:3] Verbose Mode (rw) */
+ unsigned int MSG1:1; /**< \brief [4:4] Messaging Bits (rw) */
+ unsigned int CRC1:1; /**< \brief [5:5] CRC or Parity Selection (rw) */
+ unsigned int FEC1:1; /**< \brief [6:6] Frame Expectation Control (rw) */
+ unsigned int VBS1:1; /**< \brief [7:7] Verbose Mode (rw) */
+ unsigned int MSG2:1; /**< \brief [8:8] Messaging Bits (rw) */
+ unsigned int CRC2:1; /**< \brief [9:9] CRC or Parity Selection (rw) */
+ unsigned int FEC2:1; /**< \brief [10:10] Frame Expectation Control (rw) */
+ unsigned int VBS2:1; /**< \brief [11:11] Verbose Mode (rw) */
+ unsigned int MSG3:1; /**< \brief [12:12] Messaging Bits (rw) */
+ unsigned int CRC3:1; /**< \brief [13:13] CRC or Parity Selection (rw) */
+ unsigned int FEC3:1; /**< \brief [14:14] Frame Expectation Control (rw) */
+ unsigned int VBS3:1; /**< \brief [15:15] Verbose Mode (rw) */
+ unsigned int MSG4:1; /**< \brief [16:16] Messaging Bits (rw) */
+ unsigned int CRC4:1; /**< \brief [17:17] CRC or Parity Selection (rw) */
+ unsigned int FEC4:1; /**< \brief [18:18] Frame Expectation Control (rw) */
+ unsigned int VBS4:1; /**< \brief [19:19] Verbose Mode (rw) */
+ unsigned int MSG5:1; /**< \brief [20:20] Messaging Bits (rw) */
+ unsigned int CRC5:1; /**< \brief [21:21] CRC or Parity Selection (rw) */
+ unsigned int FEC5:1; /**< \brief [22:22] Frame Expectation Control (rw) */
+ unsigned int VBS5:1; /**< \brief [23:23] Verbose Mode (rw) */
+ unsigned int reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_PSI5_CH_RCRB_Bits;
+
+/** \brief Receiver Control Register C */
+typedef struct _Ifx_PSI5_CH_RCRC_Bits
+{
+ unsigned int BRS:1; /**< \brief [0:0] Baud Rate Select (rw) */
+ unsigned int TSP:2; /**< \brief [2:1] Time Stamp Select for Pulses (rw) */
+ unsigned int TSF:2; /**< \brief [4:3] Time Stamp Select for Start of Frame (SOF) (rw) */
+ unsigned int TSR:1; /**< \brief [5:5] Time Stamp Select for Receive Data Registers (rw) */
+ unsigned int reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_PSI5_CH_RCRC_Bits;
+
+/** \brief Receive Data Register High */
+typedef struct _Ifx_PSI5_CH_RDRH_Bits
+{
+ unsigned int TS:24; /**< \brief [23:0] Time Stamp (rh) */
+ unsigned int SC:3; /**< \brief [26:24] Slot Counter (rh) */
+ unsigned int TEI:1; /**< \brief [27:27] Time Slot Error Flag (rh) */
+ unsigned int NBI:1; /**< \brief [28:28] Number of bits Error Flag (rh) */
+ unsigned int MEI:1; /**< \brief [29:29] Error in Message Bits Flag (rh) */
+ unsigned int NFI:1; /**< \brief [30:30] No Frame Received Flag (rh) */
+ unsigned int RBI:1; /**< \brief [31:31] Receive Buffer Overflow Flag (rh) */
+} Ifx_PSI5_CH_RDRH_Bits;
+
+/** \brief Receive Data Register Low */
+typedef struct _Ifx_PSI5_CH_RDRL_Bits
+{
+ unsigned int CRCI:1; /**< \brief [0:0] CRC Error Flag (rh) */
+ unsigned int CRC:3; /**< \brief [3:1] CRC (rh) */
+ unsigned int RD:28; /**< \brief [31:4] RD (rh) */
+} Ifx_PSI5_CH_RDRL_Bits;
+
+/** \brief Receive Status Register */
+typedef struct _Ifx_PSI5_CH_RSR_Bits
+{
+ unsigned int CRC:3; /**< \brief [2:0] CRC (r) */
+ unsigned int reserved_3:5; /**< \brief \internal Reserved */
+ unsigned int MSG:2; /**< \brief [9:8] Messaging Bits (r) */
+ unsigned int reserved_10:22; /**< \brief \internal Reserved */
+} Ifx_PSI5_CH_RSR_Bits;
+
+/** \brief Send Control Register */
+typedef struct _Ifx_PSI5_CH_SCR_Bits
+{
+ unsigned int PLL:6; /**< \brief [5:0] Pay Load Length of Registers SDRL/H (rw) */
+ unsigned int EPS:1; /**< \brief [6:6] Enhanced Protocol Selection (rw) */
+ unsigned int BSC:1; /**< \brief [7:7] Bit Stuffing Control (rw) */
+ unsigned int SSL:6; /**< \brief [13:8] Pay Load Length of Registers SSRL/H (rw) */
+ unsigned int FLUS:1; /**< \brief [14:14] Flush SSRH/Lx (w) */
+ unsigned int FLUO:1; /**< \brief [15:15] Flush SORH/Lx (w) */
+ unsigned int SOL:6; /**< \brief [21:16] Pay Load Length of Registers SORL/H (rw) */
+ unsigned int CRC:1; /**< \brief [22:22] CRC Generation Control (rw) */
+ unsigned int STA:1; /**< \brief [23:23] Start Sequence Generation Control (rw) */
+ unsigned int INH:1; /**< \brief [24:24] Inhibit Transfer (rw) */
+ unsigned int GO:1; /**< \brief [25:25] Release prepared Send data (w) */
+ unsigned int TPF:1; /**< \brief [26:26] Transmit Preparation Flag (r) */
+ unsigned int TSF:1; /**< \brief [27:27] Transmit Shift Flag (r) */
+ unsigned int TOF:1; /**< \brief [28:28] Transmit Output Flag (r) */
+ unsigned int reserved_29:2; /**< \brief \internal Reserved */
+ unsigned int TRQ:1; /**< \brief [31:31] Transfer Request in Progress (r) */
+} Ifx_PSI5_CH_SCR_Bits;
+
+/** \brief Send Data Register High */
+typedef struct _Ifx_PSI5_CH_SDRH_Bits
+{
+ unsigned int SD32:1; /**< \brief [0:0] SD32 (rw) */
+ unsigned int SD33:1; /**< \brief [1:1] SD33 (rw) */
+ unsigned int SD34:1; /**< \brief [2:2] SD34 (rw) */
+ unsigned int SD35:1; /**< \brief [3:3] SD35 (rw) */
+ unsigned int SD36:1; /**< \brief [4:4] SD36 (rw) */
+ unsigned int SD37:1; /**< \brief [5:5] SD37 (rw) */
+ unsigned int SD38:1; /**< \brief [6:6] SD38 (rw) */
+ unsigned int SD39:1; /**< \brief [7:7] SD39 (rw) */
+ unsigned int SD40:1; /**< \brief [8:8] SD40 (rw) */
+ unsigned int SD41:1; /**< \brief [9:9] SD41 (rw) */
+ unsigned int SD42:1; /**< \brief [10:10] SD42 (rw) */
+ unsigned int SD43:1; /**< \brief [11:11] SD43 (rw) */
+ unsigned int SD44:1; /**< \brief [12:12] SD44 (rw) */
+ unsigned int SD45:1; /**< \brief [13:13] SD45 (rw) */
+ unsigned int SD46:1; /**< \brief [14:14] SD46 (rw) */
+ unsigned int SD47:1; /**< \brief [15:15] SD47 (rw) */
+ unsigned int SD48:1; /**< \brief [16:16] SD48 (rw) */
+ unsigned int SD49:1; /**< \brief [17:17] SD49 (rw) */
+ unsigned int SD50:1; /**< \brief [18:18] SD50 (rw) */
+ unsigned int SD51:1; /**< \brief [19:19] SD51 (rw) */
+ unsigned int SD52:1; /**< \brief [20:20] SD52 (rw) */
+ unsigned int SD53:1; /**< \brief [21:21] SD53 (rw) */
+ unsigned int SD54:1; /**< \brief [22:22] SD54 (rw) */
+ unsigned int SD55:1; /**< \brief [23:23] SD55 (rw) */
+ unsigned int SD56:1; /**< \brief [24:24] SD56 (rw) */
+ unsigned int SD57:1; /**< \brief [25:25] SD57 (rw) */
+ unsigned int SD58:1; /**< \brief [26:26] SD58 (rw) */
+ unsigned int SD59:1; /**< \brief [27:27] SD59 (rw) */
+ unsigned int SD60:1; /**< \brief [28:28] SD60 (rw) */
+ unsigned int SD61:1; /**< \brief [29:29] SD61 (rw) */
+ unsigned int SD62:1; /**< \brief [30:30] SD62 (rw) */
+ unsigned int SD63:1; /**< \brief [31:31] SD63 (rw) */
+} Ifx_PSI5_CH_SDRH_Bits;
+
+/** \brief Send Data Register Low */
+typedef struct _Ifx_PSI5_CH_SDRL_Bits
+{
+ unsigned int SD0:1; /**< \brief [0:0] SD0 (rw) */
+ unsigned int SD1:1; /**< \brief [1:1] SD1 (rw) */
+ unsigned int SD2:1; /**< \brief [2:2] SD2 (rw) */
+ unsigned int SD3:1; /**< \brief [3:3] SD3 (rw) */
+ unsigned int SD4:1; /**< \brief [4:4] SD4 (rw) */
+ unsigned int SD5:1; /**< \brief [5:5] SD5 (rw) */
+ unsigned int SD6:1; /**< \brief [6:6] SD6 (rw) */
+ unsigned int SD7:1; /**< \brief [7:7] SD7 (rw) */
+ unsigned int SD8:1; /**< \brief [8:8] SD8 (rw) */
+ unsigned int SD9:1; /**< \brief [9:9] SD9 (rw) */
+ unsigned int SD10:1; /**< \brief [10:10] SD10 (rw) */
+ unsigned int SD11:1; /**< \brief [11:11] SD11 (rw) */
+ unsigned int SD12:1; /**< \brief [12:12] SD12 (rw) */
+ unsigned int SD13:1; /**< \brief [13:13] SD13 (rw) */
+ unsigned int SD14:1; /**< \brief [14:14] SD14 (rw) */
+ unsigned int SD15:1; /**< \brief [15:15] SD15 (rw) */
+ unsigned int SD16:1; /**< \brief [16:16] SD16 (rw) */
+ unsigned int SD17:1; /**< \brief [17:17] SD17 (rw) */
+ unsigned int SD18:1; /**< \brief [18:18] SD18 (rw) */
+ unsigned int SD19:1; /**< \brief [19:19] SD19 (rw) */
+ unsigned int SD20:1; /**< \brief [20:20] SD20 (rw) */
+ unsigned int SD21:1; /**< \brief [21:21] SD21 (rw) */
+ unsigned int SD22:1; /**< \brief [22:22] SD22 (rw) */
+ unsigned int SD23:1; /**< \brief [23:23] SD23 (rw) */
+ unsigned int SD24:1; /**< \brief [24:24] SD24 (rw) */
+ unsigned int SD25:1; /**< \brief [25:25] SD25 (rw) */
+ unsigned int SD26:1; /**< \brief [26:26] SD26 (rw) */
+ unsigned int SD27:1; /**< \brief [27:27] SD27 (rw) */
+ unsigned int SD28:1; /**< \brief [28:28] SD28 (rw) */
+ unsigned int SD29:1; /**< \brief [29:29] SD29 (rw) */
+ unsigned int SD30:1; /**< \brief [30:30] SD30 (rw) */
+ unsigned int SD31:1; /**< \brief [31:31] SD31 (rw) */
+} Ifx_PSI5_CH_SDRL_Bits;
+
+/** \brief Serial Data and Status Register */
+typedef struct _Ifx_PSI5_CH_SDS_Bits
+{
+ unsigned int SD:16; /**< \brief [15:0] Serial Data (r) */
+ unsigned int MID:8; /**< \brief [23:16] Message ID (r) */
+ unsigned int SCRC:6; /**< \brief [29:24] SCRC (r) */
+ unsigned int SCRI:1; /**< \brief [30:30] CRC of Serial Message failed Interrupt Flag. (r) */
+ unsigned int CON:1; /**< \brief [31:31] Configuration bit (r) */
+} Ifx_PSI5_CH_SDS_Bits;
+
+/** \brief SOF TS Capture Register SFTSC */
+typedef struct _Ifx_PSI5_CH_SFTSC_Bits
+{
+ unsigned int TS:24; /**< \brief [23:0] Time Stamp (rh) */
+ unsigned int reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_PSI5_CH_SFTSC_Bits;
+
+/** \brief Send Output Register High */
+typedef struct _Ifx_PSI5_CH_SORH_Bits
+{
+ unsigned int SD32:1; /**< \brief [0:0] SD32 (rw) */
+ unsigned int SD33:1; /**< \brief [1:1] SD33 (rw) */
+ unsigned int SD34:1; /**< \brief [2:2] SD34 (rw) */
+ unsigned int SD35:1; /**< \brief [3:3] SD35 (rw) */
+ unsigned int SD36:1; /**< \brief [4:4] SD36 (rw) */
+ unsigned int SD37:1; /**< \brief [5:5] SD37 (rw) */
+ unsigned int SD38:1; /**< \brief [6:6] SD38 (rw) */
+ unsigned int SD39:1; /**< \brief [7:7] SD39 (rw) */
+ unsigned int SD40:1; /**< \brief [8:8] SD40 (rw) */
+ unsigned int SD41:1; /**< \brief [9:9] SD41 (rw) */
+ unsigned int SD42:1; /**< \brief [10:10] SD42 (rw) */
+ unsigned int SD43:1; /**< \brief [11:11] SD43 (rw) */
+ unsigned int SD44:1; /**< \brief [12:12] SD44 (rw) */
+ unsigned int SD45:1; /**< \brief [13:13] SD45 (rw) */
+ unsigned int SD46:1; /**< \brief [14:14] SD46 (rw) */
+ unsigned int SD47:1; /**< \brief [15:15] SD47 (rw) */
+ unsigned int SD48:1; /**< \brief [16:16] SD48 (rw) */
+ unsigned int SD49:1; /**< \brief [17:17] SD49 (rw) */
+ unsigned int SD50:1; /**< \brief [18:18] SD50 (rw) */
+ unsigned int SD51:1; /**< \brief [19:19] SD51 (rw) */
+ unsigned int SD52:1; /**< \brief [20:20] SD52 (rw) */
+ unsigned int SD53:1; /**< \brief [21:21] SD53 (rw) */
+ unsigned int SD54:1; /**< \brief [22:22] SD54 (rw) */
+ unsigned int SD55:1; /**< \brief [23:23] SD55 (rw) */
+ unsigned int SD56:1; /**< \brief [24:24] SD56 (rw) */
+ unsigned int SD57:1; /**< \brief [25:25] SD57 (rw) */
+ unsigned int SD58:1; /**< \brief [26:26] SD58 (rw) */
+ unsigned int SD59:1; /**< \brief [27:27] SD59 (rw) */
+ unsigned int SD60:1; /**< \brief [28:28] SD60 (rw) */
+ unsigned int SD61:1; /**< \brief [29:29] SD61 (rw) */
+ unsigned int SD62:1; /**< \brief [30:30] SD62 (rw) */
+ unsigned int SD63:1; /**< \brief [31:31] SD63 (rw) */
+} Ifx_PSI5_CH_SORH_Bits;
+
+/** \brief Send Output Register Low */
+typedef struct _Ifx_PSI5_CH_SORL_Bits
+{
+ unsigned int SD0:1; /**< \brief [0:0] SD0 (rw) */
+ unsigned int SD1:1; /**< \brief [1:1] SD1 (rw) */
+ unsigned int SD2:1; /**< \brief [2:2] SD2 (rw) */
+ unsigned int SD3:1; /**< \brief [3:3] SD3 (rw) */
+ unsigned int SD4:1; /**< \brief [4:4] SD4 (rw) */
+ unsigned int SD5:1; /**< \brief [5:5] SD5 (rw) */
+ unsigned int SD6:1; /**< \brief [6:6] SD6 (rw) */
+ unsigned int SD7:1; /**< \brief [7:7] SD7 (rw) */
+ unsigned int SD8:1; /**< \brief [8:8] SD8 (rw) */
+ unsigned int SD9:1; /**< \brief [9:9] SD9 (rw) */
+ unsigned int SD10:1; /**< \brief [10:10] SD10 (rw) */
+ unsigned int SD11:1; /**< \brief [11:11] SD11 (rw) */
+ unsigned int SD12:1; /**< \brief [12:12] SD12 (rw) */
+ unsigned int SD13:1; /**< \brief [13:13] SD13 (rw) */
+ unsigned int SD14:1; /**< \brief [14:14] SD14 (rw) */
+ unsigned int SD15:1; /**< \brief [15:15] SD15 (rw) */
+ unsigned int SD16:1; /**< \brief [16:16] SD16 (rw) */
+ unsigned int SD17:1; /**< \brief [17:17] SD17 (rw) */
+ unsigned int SD18:1; /**< \brief [18:18] SD18 (rw) */
+ unsigned int SD19:1; /**< \brief [19:19] SD19 (rw) */
+ unsigned int SD20:1; /**< \brief [20:20] SD20 (rw) */
+ unsigned int SD21:1; /**< \brief [21:21] SD21 (rw) */
+ unsigned int SD22:1; /**< \brief [22:22] SD22 (rw) */
+ unsigned int SD23:1; /**< \brief [23:23] SD23 (rw) */
+ unsigned int SD24:1; /**< \brief [24:24] SD24 (rw) */
+ unsigned int SD25:1; /**< \brief [25:25] SD25 (rw) */
+ unsigned int SD26:1; /**< \brief [26:26] SD26 (rw) */
+ unsigned int SD27:1; /**< \brief [27:27] SD27 (rw) */
+ unsigned int SD28:1; /**< \brief [28:28] SD28 (rw) */
+ unsigned int SD29:1; /**< \brief [29:29] SD29 (rw) */
+ unsigned int SD30:1; /**< \brief [30:30] SD30 (rw) */
+ unsigned int SD31:1; /**< \brief [31:31] SD31 (rw) */
+} Ifx_PSI5_CH_SORL_Bits;
+
+/** \brief SOP TS Capture Register SPTSC */
+typedef struct _Ifx_PSI5_CH_SPTSC_Bits
+{
+ unsigned int TS:24; /**< \brief [23:0] Time Stamp (rh) */
+ unsigned int reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_PSI5_CH_SPTSC_Bits;
+
+/** \brief Send Shift Register High */
+typedef struct _Ifx_PSI5_CH_SSRH_Bits
+{
+ unsigned int SD32:1; /**< \brief [0:0] SD32 (rw) */
+ unsigned int SD33:1; /**< \brief [1:1] SD33 (rw) */
+ unsigned int SD34:1; /**< \brief [2:2] SD34 (rw) */
+ unsigned int SD35:1; /**< \brief [3:3] SD35 (rw) */
+ unsigned int SD36:1; /**< \brief [4:4] SD36 (rw) */
+ unsigned int SD37:1; /**< \brief [5:5] SD37 (rw) */
+ unsigned int SD38:1; /**< \brief [6:6] SD38 (rw) */
+ unsigned int SD39:1; /**< \brief [7:7] SD39 (rw) */
+ unsigned int SD40:1; /**< \brief [8:8] SD40 (rw) */
+ unsigned int SD41:1; /**< \brief [9:9] SD41 (rw) */
+ unsigned int SD42:1; /**< \brief [10:10] SD42 (rw) */
+ unsigned int SD43:1; /**< \brief [11:11] SD43 (rw) */
+ unsigned int SD44:1; /**< \brief [12:12] SD44 (rw) */
+ unsigned int SD45:1; /**< \brief [13:13] SD45 (rw) */
+ unsigned int SD46:1; /**< \brief [14:14] SD46 (rw) */
+ unsigned int SD47:1; /**< \brief [15:15] SD47 (rw) */
+ unsigned int SD48:1; /**< \brief [16:16] SD48 (rw) */
+ unsigned int SD49:1; /**< \brief [17:17] SD49 (rw) */
+ unsigned int SD50:1; /**< \brief [18:18] SD50 (rw) */
+ unsigned int SD51:1; /**< \brief [19:19] SD51 (rw) */
+ unsigned int SD52:1; /**< \brief [20:20] SD52 (rw) */
+ unsigned int SD53:1; /**< \brief [21:21] SD53 (rw) */
+ unsigned int SD54:1; /**< \brief [22:22] SD54 (rw) */
+ unsigned int SD55:1; /**< \brief [23:23] SD55 (rw) */
+ unsigned int SD56:1; /**< \brief [24:24] SD56 (rw) */
+ unsigned int SD57:1; /**< \brief [25:25] SD57 (rw) */
+ unsigned int SD58:1; /**< \brief [26:26] SD58 (rw) */
+ unsigned int SD59:1; /**< \brief [27:27] SD59 (rw) */
+ unsigned int SD60:1; /**< \brief [28:28] SD60 (rw) */
+ unsigned int SD61:1; /**< \brief [29:29] SD61 (rw) */
+ unsigned int SD62:1; /**< \brief [30:30] SD62 (rw) */
+ unsigned int SD63:1; /**< \brief [31:31] SD63 (rw) */
+} Ifx_PSI5_CH_SSRH_Bits;
+
+/** \brief Send Shift Register Low */
+typedef struct _Ifx_PSI5_CH_SSRL_Bits
+{
+ unsigned int SD0:1; /**< \brief [0:0] SD0 (rw) */
+ unsigned int SD1:1; /**< \brief [1:1] SD1 (rw) */
+ unsigned int SD2:1; /**< \brief [2:2] SD2 (rw) */
+ unsigned int SD3:1; /**< \brief [3:3] SD3 (rw) */
+ unsigned int SD4:1; /**< \brief [4:4] SD4 (rw) */
+ unsigned int SD5:1; /**< \brief [5:5] SD5 (rw) */
+ unsigned int SD6:1; /**< \brief [6:6] SD6 (rw) */
+ unsigned int SD7:1; /**< \brief [7:7] SD7 (rw) */
+ unsigned int SD8:1; /**< \brief [8:8] SD8 (rw) */
+ unsigned int SD9:1; /**< \brief [9:9] SD9 (rw) */
+ unsigned int SD10:1; /**< \brief [10:10] SD10 (rw) */
+ unsigned int SD11:1; /**< \brief [11:11] SD11 (rw) */
+ unsigned int SD12:1; /**< \brief [12:12] SD12 (rw) */
+ unsigned int SD13:1; /**< \brief [13:13] SD13 (rw) */
+ unsigned int SD14:1; /**< \brief [14:14] SD14 (rw) */
+ unsigned int SD15:1; /**< \brief [15:15] SD15 (rw) */
+ unsigned int SD16:1; /**< \brief [16:16] SD16 (rw) */
+ unsigned int SD17:1; /**< \brief [17:17] SD17 (rw) */
+ unsigned int SD18:1; /**< \brief [18:18] SD18 (rw) */
+ unsigned int SD19:1; /**< \brief [19:19] SD19 (rw) */
+ unsigned int SD20:1; /**< \brief [20:20] SD20 (rw) */
+ unsigned int SD21:1; /**< \brief [21:21] SD21 (rw) */
+ unsigned int SD22:1; /**< \brief [22:22] SD22 (rw) */
+ unsigned int SD23:1; /**< \brief [23:23] SD23 (rw) */
+ unsigned int SD24:1; /**< \brief [24:24] SD24 (rw) */
+ unsigned int SD25:1; /**< \brief [25:25] SD25 (rw) */
+ unsigned int SD26:1; /**< \brief [26:26] SD26 (rw) */
+ unsigned int SD27:1; /**< \brief [27:27] SD27 (rw) */
+ unsigned int SD28:1; /**< \brief [28:28] SD28 (rw) */
+ unsigned int SD29:1; /**< \brief [29:29] SD29 (rw) */
+ unsigned int SD30:1; /**< \brief [30:30] SD30 (rw) */
+ unsigned int SD31:1; /**< \brief [31:31] SD31 (rw) */
+} Ifx_PSI5_CH_SSRL_Bits;
+
+/** \brief Watch Dog Timer Register */
+typedef struct _Ifx_PSI5_CH_WDT_Bits
+{
+ unsigned int WDLxw:16; /**< \brief [15:0] Watch Dog Timer Limit (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_PSI5_CH_WDT_Bits;
+
+/** \brief Clock Control Register */
+typedef struct _Ifx_PSI5_CLC_Bits
+{
+ unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
+ unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_PSI5_CLC_Bits;
+
+/** \brief CRCIOV Clear Register */
+typedef struct _Ifx_PSI5_CRCICLR_Bits
+{
+ unsigned int CRCI0:1; /**< \brief [0:0] Clear CRCI Flag of Buffer 0 (w) */
+ unsigned int CRCI1:1; /**< \brief [1:1] Clear CRCI Flag of Buffer 1 (w) */
+ unsigned int CRCI2:1; /**< \brief [2:2] Clear CRCI Flag of Buffer 2 (w) */
+ unsigned int CRCI3:1; /**< \brief [3:3] Clear CRCI Flag of Buffer 3 (w) */
+ unsigned int CRCI4:1; /**< \brief [4:4] Clear CRCI Flag of Buffer 4 (w) */
+ unsigned int CRCI5:1; /**< \brief [5:5] Clear CRCI Flag of Buffer 5 (w) */
+ unsigned int CRCI6:1; /**< \brief [6:6] Clear CRCI Flag of Buffer 6 (w) */
+ unsigned int CRCI7:1; /**< \brief [7:7] Clear CRCI Flag of Buffer 7 (w) */
+ unsigned int CRCI8:1; /**< \brief [8:8] Clear CRCI Flag of Buffer 8 (w) */
+ unsigned int CRCI9:1; /**< \brief [9:9] Clear CRCI Flag of Buffer 9 (w) */
+ unsigned int CRCI10:1; /**< \brief [10:10] Clear CRCI Flag of Buffer 10 (w) */
+ unsigned int CRCI11:1; /**< \brief [11:11] Clear CRCI Flag of Buffer 11 (w) */
+ unsigned int CRCI12:1; /**< \brief [12:12] Clear CRCI Flag of Buffer 12 (w) */
+ unsigned int CRCI13:1; /**< \brief [13:13] Clear CRCI Flag of Buffer 13 (w) */
+ unsigned int CRCI14:1; /**< \brief [14:14] Clear CRCI Flag of Buffer 14 (w) */
+ unsigned int CRCI15:1; /**< \brief [15:15] Clear CRCI Flag of Buffer 15 (w) */
+ unsigned int CRCI16:1; /**< \brief [16:16] Clear CRCI Flag of Buffer 16 (w) */
+ unsigned int CRCI17:1; /**< \brief [17:17] Clear CRCI Flag of Buffer 17 (w) */
+ unsigned int CRCI18:1; /**< \brief [18:18] Clear CRCI Flag of Buffer 18 (w) */
+ unsigned int CRCI19:1; /**< \brief [19:19] Clear CRCI Flag of Buffer 19 (w) */
+ unsigned int CRCI20:1; /**< \brief [20:20] Clear CRCI Flag of Buffer 20 (w) */
+ unsigned int CRCI21:1; /**< \brief [21:21] Clear CRCI Flag of Buffer 21 (w) */
+ unsigned int CRCI22:1; /**< \brief [22:22] Clear CRCI Flag of Buffer 22 (w) */
+ unsigned int CRCI23:1; /**< \brief [23:23] Clear CRCI Flag of Buffer 23 (w) */
+ unsigned int CRCI24:1; /**< \brief [24:24] Clear CRCI Flag of Buffer 24 (w) */
+ unsigned int CRCI25:1; /**< \brief [25:25] Clear CRCI Flag of Buffer 25 (w) */
+ unsigned int CRCI26:1; /**< \brief [26:26] Clear CRCI Flag of Buffer 26 (w) */
+ unsigned int CRCI27:1; /**< \brief [27:27] Clear CRCI Flag of Buffer 27 (w) */
+ unsigned int CRCI28:1; /**< \brief [28:28] Clear CRCI Flag of Buffer 28 (w) */
+ unsigned int CRCI29:1; /**< \brief [29:29] Clear CRCI Flag of Buffer 29 (w) */
+ unsigned int CRCI30:1; /**< \brief [30:30] Clear CRCI Flag of Buffer 30 (w) */
+ unsigned int CRCI31:1; /**< \brief [31:31] Clear CRCI Flag of Buffer 31 (w) */
+} Ifx_PSI5_CRCICLR_Bits;
+
+/** \brief CRCI Overview Register */
+typedef struct _Ifx_PSI5_CRCIOV_Bits
+{
+ unsigned int CRCI0:1; /**< \brief [0:0] CRCI Flag of Buffer 0 (rh) */
+ unsigned int CRCI1:1; /**< \brief [1:1] CRCI Flag of Buffer 1 (rh) */
+ unsigned int CRCI2:1; /**< \brief [2:2] CRCI Flag of Buffer 2 (rh) */
+ unsigned int CRCI3:1; /**< \brief [3:3] CRCI Flag of Buffer 3 (rh) */
+ unsigned int CRCI4:1; /**< \brief [4:4] CRCI Flag of Buffer 4 (rh) */
+ unsigned int CRCI5:1; /**< \brief [5:5] CRCI Flag of Buffer 5 (rh) */
+ unsigned int CRCI6:1; /**< \brief [6:6] CRCI Flag of Buffer 6 (rh) */
+ unsigned int CRCI7:1; /**< \brief [7:7] CRCI Flag of Buffer 7 (rh) */
+ unsigned int CRCI8:1; /**< \brief [8:8] CRCI Flag of Buffer 8 (rh) */
+ unsigned int CRCI9:1; /**< \brief [9:9] CRCI Flag of Buffer 9 (rh) */
+ unsigned int CRCI10:1; /**< \brief [10:10] CRCI Flag of Buffer 10 (rh) */
+ unsigned int CRCI11:1; /**< \brief [11:11] CRCI Flag of Buffer 11 (rh) */
+ unsigned int CRCI12:1; /**< \brief [12:12] CRCI Flag of Buffer 12 (rh) */
+ unsigned int CRCI13:1; /**< \brief [13:13] CRCI Flag of Buffer 13 (rh) */
+ unsigned int CRCI14:1; /**< \brief [14:14] CRCI Flag of Buffer 14 (rh) */
+ unsigned int CRCI15:1; /**< \brief [15:15] CRCI Flag of Buffer 15 (rh) */
+ unsigned int CRCI16:1; /**< \brief [16:16] CRCI Flag of Buffer 16 (rh) */
+ unsigned int CRCI17:1; /**< \brief [17:17] CRCI Flag of Buffer 17 (rh) */
+ unsigned int CRCI18:1; /**< \brief [18:18] CRCI Flag of Buffer 18 (rh) */
+ unsigned int CRCI19:1; /**< \brief [19:19] CRCI Flag of Buffer 19 (rh) */
+ unsigned int CRCI20:1; /**< \brief [20:20] CRCI Flag of Buffer 20 (rh) */
+ unsigned int CRCI21:1; /**< \brief [21:21] CRCI Flag of Buffer 21 (rh) */
+ unsigned int CRCI22:1; /**< \brief [22:22] CRCI Flag of Buffer 22 (rh) */
+ unsigned int CRCI23:1; /**< \brief [23:23] CRCI Flag of Buffer 23 (rh) */
+ unsigned int CRCI24:1; /**< \brief [24:24] CRCI Flag of Buffer 24 (rh) */
+ unsigned int CRCI25:1; /**< \brief [25:25] CRCI Flag of Buffer 25 (rh) */
+ unsigned int CRCI26:1; /**< \brief [26:26] CRCI Flag of Buffer 26 (rh) */
+ unsigned int CRCI27:1; /**< \brief [27:27] CRCI Flag of Buffer 27 (rh) */
+ unsigned int CRCI28:1; /**< \brief [28:28] CRCI Flag of Buffer 28 (rh) */
+ unsigned int CRCI29:1; /**< \brief [29:29] CRCI Flag of Buffer 29 (rh) */
+ unsigned int CRCI30:1; /**< \brief [30:30] CRCI Flag of Buffer 30 (rh) */
+ unsigned int CRCI31:1; /**< \brief [31:31] CRCI Flag of Buffer 31 (rh) */
+} Ifx_PSI5_CRCIOV_Bits;
+
+/** \brief CRCIOV Set Register */
+typedef struct _Ifx_PSI5_CRCISET_Bits
+{
+ unsigned int CRCI0:1; /**< \brief [0:0] Set CRCI Flag of Buffer 0 (w) */
+ unsigned int CRCI1:1; /**< \brief [1:1] Set CRCI Flag of Buffer 1 (w) */
+ unsigned int CRCI2:1; /**< \brief [2:2] Set CRCI Flag of Buffer 2 (w) */
+ unsigned int CRCI3:1; /**< \brief [3:3] Set CRCI Flag of Buffer 3 (w) */
+ unsigned int CRCI4:1; /**< \brief [4:4] Set CRCI Flag of Buffer 4 (w) */
+ unsigned int CRCI5:1; /**< \brief [5:5] Set CRCI Flag of Buffer 5 (w) */
+ unsigned int CRCI6:1; /**< \brief [6:6] Set CRCI Flag of Buffer 6 (w) */
+ unsigned int CRCI7:1; /**< \brief [7:7] Set CRCI Flag of Buffer 7 (w) */
+ unsigned int CRCI8:1; /**< \brief [8:8] Set CRCI Flag of Buffer 8 (w) */
+ unsigned int CRCI9:1; /**< \brief [9:9] Set CRCI Flag of Buffer 9 (w) */
+ unsigned int CRCI10:1; /**< \brief [10:10] Set CRCI Flag of Buffer 10 (w) */
+ unsigned int CRCI11:1; /**< \brief [11:11] Set CRCI Flag of Buffer 11 (w) */
+ unsigned int CRCI12:1; /**< \brief [12:12] Set CRCI Flag of Buffer 12 (w) */
+ unsigned int CRCI13:1; /**< \brief [13:13] Set CRCI Flag of Buffer 13 (w) */
+ unsigned int CRCI14:1; /**< \brief [14:14] Set CRCI Flag of Buffer 14 (w) */
+ unsigned int CRCI15:1; /**< \brief [15:15] Set CRCI Flag of Buffer 15 (w) */
+ unsigned int CRCI16:1; /**< \brief [16:16] Set CRCI Flag of Buffer 16 (w) */
+ unsigned int CRCI17:1; /**< \brief [17:17] Set CRCI Flag of Buffer 17 (w) */
+ unsigned int CRCI18:1; /**< \brief [18:18] Set CRCI Flag of Buffer 18 (w) */
+ unsigned int CRCI19:1; /**< \brief [19:19] Set CRCI Flag of Buffer 19 (w) */
+ unsigned int CRCI20:1; /**< \brief [20:20] Set CRCI Flag of Buffer 20 (w) */
+ unsigned int CRCI21:1; /**< \brief [21:21] Set CRCI Flag of Buffer 21 (w) */
+ unsigned int CRCI22:1; /**< \brief [22:22] Set CRCI Flag of Buffer 22 (w) */
+ unsigned int CRCI23:1; /**< \brief [23:23] Set CRCI Flag of Buffer 23 (w) */
+ unsigned int CRCI24:1; /**< \brief [24:24] Set CRCI Flag of Buffer 24 (w) */
+ unsigned int CRCI25:1; /**< \brief [25:25] Set CRCI Flag of Buffer 25 (w) */
+ unsigned int CRCI26:1; /**< \brief [26:26] Set CRCI Flag of Buffer 26 (w) */
+ unsigned int CRCI27:1; /**< \brief [27:27] Set CRCI Flag of Buffer 27 (w) */
+ unsigned int CRCI28:1; /**< \brief [28:28] Set CRCI Flag of Buffer 28 (w) */
+ unsigned int CRCI29:1; /**< \brief [29:29] Set CRCI Flag of Buffer 29 (w) */
+ unsigned int CRCI30:1; /**< \brief [30:30] Set CRCI Flag of Buffer 30 (w) */
+ unsigned int CRCI31:1; /**< \brief [31:31] Set CRCI Flag of Buffer 31 (w) */
+} Ifx_PSI5_CRCISET_Bits;
+
+/** \brief PSI5 Fractional Divider Register */
+typedef struct _Ifx_PSI5_FDR_Bits
+{
+ unsigned int STEP:10; /**< \brief [9:0] Step Value (rw) */
+ unsigned int reserved_10:4; /**< \brief \internal Reserved */
+ unsigned int DM:2; /**< \brief [15:14] Divider Mode (rw) */
+ unsigned int RESULT:10; /**< \brief [25:16] Result Value (rh) */
+ unsigned int reserved_26:6; /**< \brief \internal Reserved */
+} Ifx_PSI5_FDR_Bits;
+
+/** \brief Fractional Divider Register for Higher Bit Rate */
+typedef struct _Ifx_PSI5_FDRH_Bits
+{
+ unsigned int STEP:10; /**< \brief [9:0] Step Value (rw) */
+ unsigned int reserved_10:4; /**< \brief \internal Reserved */
+ unsigned int DM:2; /**< \brief [15:14] Divider Mode (rw) */
+ unsigned int RESULT:10; /**< \brief [25:16] Result Value (rh) */
+ unsigned int reserved_26:6; /**< \brief \internal Reserved */
+} Ifx_PSI5_FDRH_Bits;
+
+/** \brief Fractional Divider Register for Lower Bit Rate */
+typedef struct _Ifx_PSI5_FDRL_Bits
+{
+ unsigned int STEP:10; /**< \brief [9:0] Step Value (rw) */
+ unsigned int reserved_10:4; /**< \brief \internal Reserved */
+ unsigned int DM:2; /**< \brief [15:14] Divider Mode (rw) */
+ unsigned int RESULT:10; /**< \brief [25:16] Result Value (rh) */
+ unsigned int reserved_26:6; /**< \brief \internal Reserved */
+} Ifx_PSI5_FDRL_Bits;
+
+/** \brief Fractional Divider Register for Time Stamp */
+typedef struct _Ifx_PSI5_FDRT_Bits
+{
+ unsigned int STEP:10; /**< \brief [9:0] Step Value (rw) */
+ unsigned int reserved_10:4; /**< \brief \internal Reserved */
+ unsigned int DM:2; /**< \brief [15:14] Divider Mode (rw) */
+ unsigned int RESULT:10; /**< \brief [25:16] Result Value (rh) */
+ unsigned int ECS:3; /**< \brief [28:26] External Time Stamp Clear Source Select (rw) */
+ unsigned int ECEA:1; /**< \brief [29:29] External Time Stamp Clear Enable A (rw) */
+ unsigned int ECEB:1; /**< \brief [30:30] External Time Stamp Clear Enable B (rw) */
+ unsigned int ECEC:1; /**< \brief [31:31] External Time Stamp Clear Enable C (rw) */
+} Ifx_PSI5_FDRT_Bits;
+
+/** \brief Global Control Register */
+typedef struct _Ifx_PSI5_GCR_Bits
+{
+ unsigned int CRCI:1; /**< \brief [0:0] CRCI (rw) */
+ unsigned int NBI:1; /**< \brief [1:1] NBI (rw) */
+ unsigned int MEI:1; /**< \brief [2:2] MEI (rw) */
+ unsigned int NFI:1; /**< \brief [3:3] NFI (rw) */
+ unsigned int TEI:1; /**< \brief [4:4] TEI (rw) */
+ unsigned int reserved_5:3; /**< \brief \internal Reserved */
+ unsigned int ETC0:1; /**< \brief [8:8] Enable Channel Trigger Counter CTVx.CTC (rw) */
+ unsigned int ETC1:1; /**< \brief [9:9] Enable Channel Trigger Counter CTVx.CTC (rw) */
+ unsigned int ETC2:1; /**< \brief [10:10] Enable Channel Trigger Counter CTVx.CTC (rw) */
+ unsigned int ETC3:1; /**< \brief [11:11] Enable Channel Trigger Counter CTVx.CTC (rw) */
+ unsigned int ETC4:1; /**< \brief [12:12] Enable Channel Trigger Counter CTVx.CTC (rw) */
+ unsigned int reserved_13:3; /**< \brief \internal Reserved */
+ unsigned int CEN0:1; /**< \brief [16:16] Enable Channel (rw) */
+ unsigned int CEN1:1; /**< \brief [17:17] Enable Channel (rw) */
+ unsigned int CEN2:1; /**< \brief [18:18] Enable Channel (rw) */
+ unsigned int CEN3:1; /**< \brief [19:19] Enable Channel (rw) */
+ unsigned int CEN4:1; /**< \brief [20:20] Enable Channel (rw) */
+ unsigned int reserved_21:11; /**< \brief \internal Reserved */
+} Ifx_PSI5_GCR_Bits;
+
+/** \brief Module Identification Register */
+typedef struct _Ifx_PSI5_ID_Bits
+{
+ unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
+ unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_PSI5_ID_Bits;
+
+/** \brief Interrupt Node Pointer Register */
+typedef struct _Ifx_PSI5_INP_Bits
+{
+ unsigned int RSI:4; /**< \brief [3:0] Interrupt Node Pointer for Interrupt RSI (rw) */
+ unsigned int RDI:4; /**< \brief [7:4] Interrupt Node Pointer for Interrupt RDI (rw) */
+ unsigned int RBI:4; /**< \brief [11:8] Interrupt Node Pointer for Interrupt RBI (rw) */
+ unsigned int TDI:4; /**< \brief [15:12] Interrupt Node Pointer for Interrupt TDI (rw) */
+ unsigned int TBI:4; /**< \brief [19:16] Interrupt Node Pointer for Interrupt TBI (rw) */
+ unsigned int ERRI:4; /**< \brief [23:20] Interrupt Node Pointer for Interrupt ERRI (rw) */
+ unsigned int SDI:4; /**< \brief [27:24] Interrupt Node Pointer for Interrupt SDI (rw) */
+ unsigned int FWI:4; /**< \brief [31:28] Interrupt Node Pointer for FWI (rw) */
+} Ifx_PSI5_INP_Bits;
+
+/** \brief Interrupt Clear Register A */
+typedef struct _Ifx_PSI5_INTCLRA_Bits
+{
+ unsigned int RSI:1; /**< \brief [0:0] Clear Interrupt Request Flag RSI (w) */
+ unsigned int RDI:1; /**< \brief [1:1] Clear Interrupt Request Flag RDI (w) */
+ unsigned int RBI:1; /**< \brief [2:2] Clear Interrupt Request Flag RBI (w) */
+ unsigned int TEI:1; /**< \brief [3:3] Clear Interrupt Request Flag TEI (w) */
+ unsigned int NBI:1; /**< \brief [4:4] Clear Interrupt Request Flag NBI (w) */
+ unsigned int MEI:1; /**< \brief [5:5] Clear Interrupt Request Flag MEI (w) */
+ unsigned int CRCI:1; /**< \brief [6:6] Clear Interrupt Request Flag CRCI (w) */
+ unsigned int FWI:1; /**< \brief [7:7] Clear Interrupt Request Flag FWI (w) */
+ unsigned int RUI:1; /**< \brief [8:8] Clear Interrupt Request Flag RUI (w) */
+ unsigned int RMI:1; /**< \brief [9:9] Clear Interrupt Request Flag RMI (w) */
+ unsigned int TPI:1; /**< \brief [10:10] Clear Interrupt Request Flag TPI (w) */
+ unsigned int TPOI:1; /**< \brief [11:11] Clear Interrupt Request Flag TPOI (w) */
+ unsigned int TSI:1; /**< \brief [12:12] Clear Interrupt Request Flag TSI (w) */
+ unsigned int TSOI:1; /**< \brief [13:13] Clear Interrupt Request Flag TSOI (w) */
+ unsigned int TOI:1; /**< \brief [14:14] Clear Interrupt Request Flag TOI (w) */
+ unsigned int TOOI:1; /**< \brief [15:15] Clear Interrupt Request Flag TOOI (w) */
+ unsigned int NFI:1; /**< \brief [16:16] Clear Interrupt Request Flag NFI (w) */
+ unsigned int reserved_17:15; /**< \brief \internal Reserved */
+} Ifx_PSI5_INTCLRA_Bits;
+
+/** \brief Interrupt Clear Register A */
+typedef struct _Ifx_PSI5_INTCLRB_Bits
+{
+ unsigned int WSI0:1; /**< \brief [0:0] Clear Interrupt Request Flag WSI0 (w) */
+ unsigned int WSI1:1; /**< \brief [1:1] Clear Interrupt Request Flag WSI1 (w) */
+ unsigned int WSI2:1; /**< \brief [2:2] Clear Interrupt Request Flag WSI2 (w) */
+ unsigned int WSI3:1; /**< \brief [3:3] Clear Interrupt Request Flag WSI3 (w) */
+ unsigned int WSI4:1; /**< \brief [4:4] Clear Interrupt Request Flag WSI4 (w) */
+ unsigned int WSI5:1; /**< \brief [5:5] Clear Interrupt Request Flag WSI5 (w) */
+ unsigned int SDI0:1; /**< \brief [6:6] Clear Interrupt Request Flag SDI0 (w) */
+ unsigned int SDI1:1; /**< \brief [7:7] Clear Interrupt Request Flag SDI1 (w) */
+ unsigned int SDI2:1; /**< \brief [8:8] Clear Interrupt Request Flag SDI2 (w) */
+ unsigned int SDI3:1; /**< \brief [9:9] Clear Interrupt Request Flag SDI3 (w) */
+ unsigned int SDI4:1; /**< \brief [10:10] Clear Interrupt Request Flag SDI4 (w) */
+ unsigned int SDI5:1; /**< \brief [11:11] Clear Interrupt Request Flag SDI5 (w) */
+ unsigned int SOI0:1; /**< \brief [12:12] Clear Interrupt Request Flag SOI0 (w) */
+ unsigned int SOI1:1; /**< \brief [13:13] Clear Interrupt Request Flag SOI1 (w) */
+ unsigned int SOI2:1; /**< \brief [14:14] Clear Interrupt Request Flag SOI2 (w) */
+ unsigned int SOI3:1; /**< \brief [15:15] Clear Interrupt Request Flag SOI3 (w) */
+ unsigned int SOI4:1; /**< \brief [16:16] Clear Interrupt Request Flag SOI4 (w) */
+ unsigned int SOI5:1; /**< \brief [17:17] Clear Interrupt Request Flag SOI5 (w) */
+ unsigned int SCRI0:1; /**< \brief [18:18] Clear Interrupt Request Flag SCRI0 (w) */
+ unsigned int SCRI1:1; /**< \brief [19:19] Clear Interrupt Request Flag SCRI1 (w) */
+ unsigned int SCRI2:1; /**< \brief [20:20] Clear Interrupt Request Flag SCRI2 (w) */
+ unsigned int SCRI3:1; /**< \brief [21:21] Clear Interrupt Request Flag SCRI3 (w) */
+ unsigned int SCRI4:1; /**< \brief [22:22] Clear Interrupt Request Flag SCRI4 (w) */
+ unsigned int SCRI5:1; /**< \brief [23:23] Clear Interrupt Request Flag SCRI5 (w) */
+ unsigned int reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_PSI5_INTCLRB_Bits;
+
+/** \brief Interrupt Enable Register A */
+typedef struct _Ifx_PSI5_INTENA_Bits
+{
+ unsigned int RSI:1; /**< \brief [0:0] Enable Interrupt Request RSI (rw) */
+ unsigned int RDI:1; /**< \brief [1:1] Enable Interrupt Request RDI (rw) */
+ unsigned int RBI:1; /**< \brief [2:2] Enable Interrupt Request RBI (rw) */
+ unsigned int TEI:1; /**< \brief [3:3] Enable Interrupt Request TEI (rw) */
+ unsigned int NBI:1; /**< \brief [4:4] Enable Interrupt Request NBI (rw) */
+ unsigned int MEI:1; /**< \brief [5:5] Enable Interrupt Request MEII (rw) */
+ unsigned int CRCI:1; /**< \brief [6:6] Enable Interrupt Request CRCI (rw) */
+ unsigned int FWI:1; /**< \brief [7:7] Enable Interrupt Request FWI (rw) */
+ unsigned int RUI:1; /**< \brief [8:8] Enable Interrupt Request RUI (rw) */
+ unsigned int RMI:1; /**< \brief [9:9] Enable Interrupt Request RMII (rw) */
+ unsigned int TPI:1; /**< \brief [10:10] Enable Interrupt Request TPI (rw) */
+ unsigned int TPOI:1; /**< \brief [11:11] Enable Interrupt Request TPOI (rw) */
+ unsigned int TSI:1; /**< \brief [12:12] Enable Interrupt Request TSI (rw) */
+ unsigned int TSOI:1; /**< \brief [13:13] Enable Interrupt Request TSOI (rw) */
+ unsigned int TOI:1; /**< \brief [14:14] Enable Interrupt Request TOI (rw) */
+ unsigned int TOOI:1; /**< \brief [15:15] Enable Interrupt Request TOOI (rw) */
+ unsigned int NFI:1; /**< \brief [16:16] Enable Interrupt Request NFI (rw) */
+ unsigned int reserved_17:15; /**< \brief \internal Reserved */
+} Ifx_PSI5_INTENA_Bits;
+
+/** \brief Interrupt Enable Register B */
+typedef struct _Ifx_PSI5_INTENB_Bits
+{
+ unsigned int WSI0:1; /**< \brief [0:0] Enable Interrupt Request WSI0 (rw) */
+ unsigned int WSI1:1; /**< \brief [1:1] Enable Interrupt Request WSI1 (rw) */
+ unsigned int WSI2:1; /**< \brief [2:2] Enable Interrupt Request WSI2 (rw) */
+ unsigned int WSI3:1; /**< \brief [3:3] Enable Interrupt Request WSI3 (rw) */
+ unsigned int WSI4:1; /**< \brief [4:4] Enable Interrupt Request WSI4 (rw) */
+ unsigned int WSI5:1; /**< \brief [5:5] Enable Interrupt Request WSI5 (rw) */
+ unsigned int SDI0:1; /**< \brief [6:6] Enable Interrupt Request SDI0 (rw) */
+ unsigned int SDI1:1; /**< \brief [7:7] Enable Interrupt Request SDI1 (rw) */
+ unsigned int SDI2:1; /**< \brief [8:8] Enable Interrupt Request SDI2 (rw) */
+ unsigned int SDI3:1; /**< \brief [9:9] Enable Interrupt Request SDI3 (rw) */
+ unsigned int SDI4:1; /**< \brief [10:10] Enable Interrupt Request SDI4 (rw) */
+ unsigned int SDI5:1; /**< \brief [11:11] Enable Interrupt Request SDI5 (rw) */
+ unsigned int SOI0:1; /**< \brief [12:12] Enable Interrupt Request SOI0 (rw) */
+ unsigned int SOI1:1; /**< \brief [13:13] Enable Interrupt Request SOI1 (rw) */
+ unsigned int SOI2:1; /**< \brief [14:14] Enable Interrupt Request SOI2 (rw) */
+ unsigned int SOI3:1; /**< \brief [15:15] Enable Interrupt Request SOI3 (rw) */
+ unsigned int SOI4:1; /**< \brief [16:16] Enable Interrupt Request SOI4 (rw) */
+ unsigned int SOI5:1; /**< \brief [17:17] Enable Interrupt Request SOI5 (rw) */
+ unsigned int SCRI0:1; /**< \brief [18:18] Enable Interrupt Request SCRI0 (rw) */
+ unsigned int SCRI1:1; /**< \brief [19:19] Enable Interrupt Request SCRI1 (rw) */
+ unsigned int SCRI2:1; /**< \brief [20:20] Enable Interrupt Request SCRI2 (rw) */
+ unsigned int SCRI3:1; /**< \brief [21:21] Enable Interrupt Request SCRI3 (rw) */
+ unsigned int SCRI4:1; /**< \brief [22:22] Enable Interrupt Request SCRI4 (rw) */
+ unsigned int SCRI5:1; /**< \brief [23:23] Enable Interrupt Request SCRI5 (rw) */
+ unsigned int reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_PSI5_INTENB_Bits;
+
+/** \brief Interrupt Overview Register */
+typedef struct _Ifx_PSI5_INTOV_Bits
+{
+ unsigned int RSI:1; /**< \brief [0:0] Interrupt Pending on any Node Pointer RSI (rh) */
+ unsigned int RDI:1; /**< \brief [1:1] Interrupt Pending on any Node Pointer RDI (rh) */
+ unsigned int RBI:1; /**< \brief [2:2] Interrupt Pending on any Node Pointer RBI (rh) */
+ unsigned int TDI:1; /**< \brief [3:3] Interrupt Pending on any Node Pointer TDI (rh) */
+ unsigned int TBI:1; /**< \brief [4:4] Interrupt Pending on any Node Pointer TBI (rh) */
+ unsigned int ERRI:1; /**< \brief [5:5] Interrupt Pending on any Node Pointer ERRI (rh) */
+ unsigned int SDI:1; /**< \brief [6:6] Interrupt Pending on any Node Pointer SDI (rh) */
+ unsigned int FWI:1; /**< \brief [7:7] Interrupt Pending on any Node Pointer FWI (rh) */
+ unsigned int reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_PSI5_INTOV_Bits;
+
+/** \brief Interrupt Set Register A */
+typedef struct _Ifx_PSI5_INTSETA_Bits
+{
+ unsigned int RSI:1; /**< \brief [0:0] Set Interrupt Request Flag RSI (w) */
+ unsigned int RDI:1; /**< \brief [1:1] Set Interrupt Request Flag RDI (w) */
+ unsigned int RBI:1; /**< \brief [2:2] Set Interrupt Request Flag RBI (w) */
+ unsigned int TEI:1; /**< \brief [3:3] Set Interrupt Request Flag TEI (w) */
+ unsigned int NBI:1; /**< \brief [4:4] Set Interrupt Request Flag NBI (w) */
+ unsigned int MEI:1; /**< \brief [5:5] Set Interrupt Request Flag MEI (w) */
+ unsigned int CRCI:1; /**< \brief [6:6] Set Interrupt Request Flag CRCI (w) */
+ unsigned int FWI:1; /**< \brief [7:7] Set Interrupt Request Flag FWI (w) */
+ unsigned int RUI:1; /**< \brief [8:8] Set Interrupt Request Flag RUI (w) */
+ unsigned int RMI:1; /**< \brief [9:9] Set Interrupt Request Flag RMI (w) */
+ unsigned int TPI:1; /**< \brief [10:10] Set Interrupt Request Flag TPI (w) */
+ unsigned int TPOI:1; /**< \brief [11:11] Set Interrupt Request Flag TPOI (w) */
+ unsigned int TSI:1; /**< \brief [12:12] Set Interrupt Request Flag TSI (w) */
+ unsigned int TSOI:1; /**< \brief [13:13] Set Interrupt Request Flag TSOI (w) */
+ unsigned int TOI:1; /**< \brief [14:14] Set Interrupt Request Flag TOI (w) */
+ unsigned int TOOI:1; /**< \brief [15:15] Set Interrupt Request Flag TOOI (w) */
+ unsigned int NFI:1; /**< \brief [16:16] Set Interrupt Request Flag NFI (w) */
+ unsigned int reserved_17:15; /**< \brief \internal Reserved */
+} Ifx_PSI5_INTSETA_Bits;
+
+/** \brief Interrupt Set Register B */
+typedef struct _Ifx_PSI5_INTSETB_Bits
+{
+ unsigned int WSI0:1; /**< \brief [0:0] Set Interrupt Request Flag WSI0 (w) */
+ unsigned int WSI1:1; /**< \brief [1:1] Set Interrupt Request Flag WSI1 (w) */
+ unsigned int WSI2:1; /**< \brief [2:2] Set Interrupt Request Flag WSI2 (w) */
+ unsigned int WSI3:1; /**< \brief [3:3] Set Interrupt Request Flag WSI3 (w) */
+ unsigned int WSI4:1; /**< \brief [4:4] Set Interrupt Request Flag WSI4 (w) */
+ unsigned int WSI5:1; /**< \brief [5:5] Set Interrupt Request Flag WSI5 (w) */
+ unsigned int SDI0:1; /**< \brief [6:6] Set Interrupt Request Flag SDI0 (w) */
+ unsigned int SDI1:1; /**< \brief [7:7] Set Interrupt Request Flag SDI1 (w) */
+ unsigned int SDI2:1; /**< \brief [8:8] Set Interrupt Request Flag SDI2 (w) */
+ unsigned int SDI3:1; /**< \brief [9:9] Set Interrupt Request Flag SDI3 (w) */
+ unsigned int SDI4:1; /**< \brief [10:10] Set Interrupt Request Flag SDI4 (w) */
+ unsigned int SDI5:1; /**< \brief [11:11] Set Interrupt Request Flag SDI5 (w) */
+ unsigned int SOI0:1; /**< \brief [12:12] Set Interrupt Request Flag SOI0 (w) */
+ unsigned int SOI1:1; /**< \brief [13:13] Set Interrupt Request Flag SOI1 (w) */
+ unsigned int SOI2:1; /**< \brief [14:14] Set Interrupt Request Flag SOI2 (w) */
+ unsigned int SOI3:1; /**< \brief [15:15] Set Interrupt Request Flag SOI3 (w) */
+ unsigned int SOI4:1; /**< \brief [16:16] Set Interrupt Request Flag SOI4 (w) */
+ unsigned int SOI5:1; /**< \brief [17:17] Set Interrupt Request Flag SOI5 (w) */
+ unsigned int SCRI0:1; /**< \brief [18:18] Set Interrupt Request Flag SCRI0 (w) */
+ unsigned int SCRI1:1; /**< \brief [19:19] Set Interrupt Request Flag SCRI1 (w) */
+ unsigned int SCRI2:1; /**< \brief [20:20] Set Interrupt Request Flag SCRI2 (w) */
+ unsigned int SCRI3:1; /**< \brief [21:21] Set Interrupt Request Flag SCRI3 (w) */
+ unsigned int SCRI4:1; /**< \brief [22:22] Set Interrupt Request Flag SCRI4 (w) */
+ unsigned int SCRI5:1; /**< \brief [23:23] Set Interrupt Request Flag SCRI5 (w) */
+ unsigned int reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_PSI5_INTSETB_Bits;
+
+/** \brief Interrupt Status Register A */
+typedef struct _Ifx_PSI5_INTSTATA_Bits
+{
+ unsigned int RSI:1; /**< \brief [0:0] Receive Success Interrupt Request Flag (rh) */
+ unsigned int RDI:1; /**< \brief [1:1] Receive Data Interrupt Request Flag (rh) */
+ unsigned int RBI:1; /**< \brief [2:2] Receive Buffer Overflow Interrupt Request Flag (rh) */
+ unsigned int TEI:1; /**< \brief [3:3] Time Slot Error Interrupt Request Flag (rh) */
+ unsigned int NBI:1; /**< \brief [4:4] Number of Bits Wrong Request Flag (rh) */
+ unsigned int MEI:1; /**< \brief [5:5] Error in Message Bits Flag (rh) */
+ unsigned int CRCI:1; /**< \brief [6:6] CRC Error Request Flag (rh) */
+ unsigned int FWI:1; /**< \brief [7:7] FIFO Warning Level Request Flag (rh) */
+ unsigned int RUI:1; /**< \brief [8:8] Receive Memory Underrun Interrupt Request Flag (rh) */
+ unsigned int RMI:1; /**< \brief [9:9] Receive Memory Overflow Flag (rh) */
+ unsigned int TPI:1; /**< \brief [10:10] Transfer Preparation Interrupt Request Flag (rh) */
+ unsigned int TPOI:1; /**< \brief [11:11] Transmit Preparation Overflow Interrupt Request Flag (rh) */
+ unsigned int TSI:1; /**< \brief [12:12] Transfer Shift Interrupt Request Flag (rh) */
+ unsigned int TSOI:1; /**< \brief [13:13] Transmit Shift Overflow Interrupt Request Flag (rh) */
+ unsigned int TOI:1; /**< \brief [14:14] Transfer Output Interrupt Request Flag (rh) */
+ unsigned int TOOI:1; /**< \brief [15:15] Transmit Shift Overflow Interrupt Request Flag (rh) */
+ unsigned int NFI:1; /**< \brief [16:16] No Frame Received Interrupt Flag (rh) */
+ unsigned int reserved_17:15; /**< \brief \internal Reserved */
+} Ifx_PSI5_INTSTATA_Bits;
+
+/** \brief Interrupt Status Register B */
+typedef struct _Ifx_PSI5_INTSTATB_Bits
+{
+ unsigned int WSI0:1; /**< \brief [0:0] Wrong Serial Protocol Error Request Flag (rh) */
+ unsigned int WSI1:1; /**< \brief [1:1] Wrong Serial Protocol Error Request Flag (rh) */
+ unsigned int WSI2:1; /**< \brief [2:2] Wrong Serial Protocol Error Request Flag (rh) */
+ unsigned int WSI3:1; /**< \brief [3:3] Wrong Serial Protocol Error Request Flag (rh) */
+ unsigned int WSI4:1; /**< \brief [4:4] Wrong Serial Protocol Error Request Flag (rh) */
+ unsigned int WSI5:1; /**< \brief [5:5] Wrong Serial Protocol Error Request Flag (rh) */
+ unsigned int SDI0:1; /**< \brief [6:6] Serial Data Receive Interrupt Request Flag (rh) */
+ unsigned int SDI1:1; /**< \brief [7:7] Serial Data Receive Interrupt Request Flag (rh) */
+ unsigned int SDI2:1; /**< \brief [8:8] Serial Data Receive Interrupt Request Flag (rh) */
+ unsigned int SDI3:1; /**< \brief [9:9] Serial Data Receive Interrupt Request Flag (rh) */
+ unsigned int SDI4:1; /**< \brief [10:10] Serial Data Receive Interrupt Request Flag (rh) */
+ unsigned int SDI5:1; /**< \brief [11:11] Serial Data Receive Interrupt Request Flag (rh) */
+ unsigned int SOI0:1; /**< \brief [12:12] Serial Data Buffer Overrun Interrupt Request Flag (rh) */
+ unsigned int SOI1:1; /**< \brief [13:13] Serial Data Buffer Overrun Interrupt Request Flag (rh) */
+ unsigned int SOI2:1; /**< \brief [14:14] Serial Data Buffer Overrun Interrupt Request Flag (rh) */
+ unsigned int SOI3:1; /**< \brief [15:15] Serial Data Buffer Overrun Interrupt Request Flag (rh) */
+ unsigned int SOI4:1; /**< \brief [16:16] Serial Data Buffer Overrun Interrupt Request Flag (rh) */
+ unsigned int SOI5:1; /**< \brief [17:17] Serial Data Buffer Overrun Interrupt Request Flag (rh) */
+ unsigned int SCRI0:1; /**< \brief [18:18] Serial Data CRC Error Request Flag (rh) */
+ unsigned int SCRI1:1; /**< \brief [19:19] Serial Data CRC Error Request Flag (rh) */
+ unsigned int SCRI2:1; /**< \brief [20:20] Serial Data CRC Error Request Flag (rh) */
+ unsigned int SCRI3:1; /**< \brief [21:21] Serial Data CRC Error Request Flag (rh) */
+ unsigned int SCRI4:1; /**< \brief [22:22] Serial Data CRC Error Request Flag (rh) */
+ unsigned int SCRI5:1; /**< \brief [23:23] Serial Data CRC Error Request Flag (rh) */
+ unsigned int reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_PSI5_INTSTATB_Bits;
+
+/** \brief Kernel Reset Register 0 */
+typedef struct _Ifx_PSI5_KRST0_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rh) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_PSI5_KRST0_Bits;
+
+/** \brief Kernel Reset Register 1 */
+typedef struct _Ifx_PSI5_KRST1_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_PSI5_KRST1_Bits;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef struct _Ifx_PSI5_KRSTCLR_Bits
+{
+ unsigned int CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_PSI5_KRSTCLR_Bits;
+
+/** \brief MEIOV Clear Register */
+typedef struct _Ifx_PSI5_MEICLR_Bits
+{
+ unsigned int MEI0:1; /**< \brief [0:0] Clear MEI Flag of Buffer 0 (w) */
+ unsigned int MEI1:1; /**< \brief [1:1] Clear MEI Flag of Buffer 1 (w) */
+ unsigned int MEI2:1; /**< \brief [2:2] Clear MEI Flag of Buffer 2 (w) */
+ unsigned int MEI3:1; /**< \brief [3:3] Clear MEI Flag of Buffer 3 (w) */
+ unsigned int MEI4:1; /**< \brief [4:4] Clear MEI Flag of Buffer 4 (w) */
+ unsigned int MEI5:1; /**< \brief [5:5] Clear MEI Flag of Buffer 5 (w) */
+ unsigned int MEI6:1; /**< \brief [6:6] Clear MEI Flag of Buffer 6 (w) */
+ unsigned int MEI7:1; /**< \brief [7:7] Clear MEI Flag of Buffer 7 (w) */
+ unsigned int MEI8:1; /**< \brief [8:8] Clear MEI Flag of Buffer 8 (w) */
+ unsigned int MEI9:1; /**< \brief [9:9] Clear MEI Flag of Buffer 9 (w) */
+ unsigned int MEI10:1; /**< \brief [10:10] Clear MEI Flag of Buffer 10 (w) */
+ unsigned int MEI11:1; /**< \brief [11:11] Clear MEI Flag of Buffer 11 (w) */
+ unsigned int MEI12:1; /**< \brief [12:12] Clear MEI Flag of Buffer 12 (w) */
+ unsigned int MEI13:1; /**< \brief [13:13] Clear MEI Flag of Buffer 13 (w) */
+ unsigned int MEI14:1; /**< \brief [14:14] Clear MEI Flag of Buffer 14 (w) */
+ unsigned int MEI15:1; /**< \brief [15:15] Clear MEI Flag of Buffer 15 (w) */
+ unsigned int MEI16:1; /**< \brief [16:16] Clear MEI Flag of Buffer 16 (w) */
+ unsigned int MEI17:1; /**< \brief [17:17] Clear MEI Flag of Buffer 17 (w) */
+ unsigned int MEI18:1; /**< \brief [18:18] Clear MEI Flag of Buffer 18 (w) */
+ unsigned int MEI19:1; /**< \brief [19:19] Clear MEI Flag of Buffer 19 (w) */
+ unsigned int MEI20:1; /**< \brief [20:20] Clear MEI Flag of Buffer 20 (w) */
+ unsigned int MEI21:1; /**< \brief [21:21] Clear MEI Flag of Buffer 21 (w) */
+ unsigned int MEI22:1; /**< \brief [22:22] Clear MEI Flag of Buffer 22 (w) */
+ unsigned int MEI23:1; /**< \brief [23:23] Clear MEI Flag of Buffer 23 (w) */
+ unsigned int MEI24:1; /**< \brief [24:24] Clear MEI Flag of Buffer 24 (w) */
+ unsigned int MEI25:1; /**< \brief [25:25] Clear MEI Flag of Buffer 25 (w) */
+ unsigned int MEI26:1; /**< \brief [26:26] Clear MEI Flag of Buffer 26 (w) */
+ unsigned int MEI27:1; /**< \brief [27:27] Clear MEI Flag of Buffer 27 (w) */
+ unsigned int MEI28:1; /**< \brief [28:28] Clear MEI Flag of Buffer 28 (w) */
+ unsigned int MEI29:1; /**< \brief [29:29] Clear MEI Flag of Buffer 29 (w) */
+ unsigned int MEI30:1; /**< \brief [30:30] Clear MEI Flag of Buffer 30 (w) */
+ unsigned int MEI31:1; /**< \brief [31:31] Clear MEI Flag of Buffer 31 (w) */
+} Ifx_PSI5_MEICLR_Bits;
+
+/** \brief MEI Overview Register */
+typedef struct _Ifx_PSI5_MEIOV_Bits
+{
+ unsigned int MEI0:1; /**< \brief [0:0] MEI Flag of Buffer 0 (rh) */
+ unsigned int MEI1:1; /**< \brief [1:1] MEI Flag of Buffer 1 (rh) */
+ unsigned int MEI2:1; /**< \brief [2:2] MEI Flag of Buffer 2 (rh) */
+ unsigned int MEI3:1; /**< \brief [3:3] MEI Flag of Buffer 3 (rh) */
+ unsigned int MEI4:1; /**< \brief [4:4] MEI Flag of Buffer 4 (rh) */
+ unsigned int MEI5:1; /**< \brief [5:5] MEI Flag of Buffer 5 (rh) */
+ unsigned int MEI6:1; /**< \brief [6:6] MEI Flag of Buffer 6 (rh) */
+ unsigned int MEI7:1; /**< \brief [7:7] MEI Flag of Buffer 7 (rh) */
+ unsigned int MEI8:1; /**< \brief [8:8] MEI Flag of Buffer 8 (rh) */
+ unsigned int MEI9:1; /**< \brief [9:9] MEI Flag of Buffer 9 (rh) */
+ unsigned int MEI10:1; /**< \brief [10:10] MEI Flag of Buffer 10 (rh) */
+ unsigned int MEI11:1; /**< \brief [11:11] MEI Flag of Buffer 11 (rh) */
+ unsigned int MEI12:1; /**< \brief [12:12] MEI Flag of Buffer 12 (rh) */
+ unsigned int MEI13:1; /**< \brief [13:13] MEI Flag of Buffer 13 (rh) */
+ unsigned int MEI14:1; /**< \brief [14:14] MEI Flag of Buffer 14 (rh) */
+ unsigned int MEI15:1; /**< \brief [15:15] MEI Flag of Buffer 15 (rh) */
+ unsigned int MEI16:1; /**< \brief [16:16] MEI Flag of Buffer 16 (rh) */
+ unsigned int MEI17:1; /**< \brief [17:17] MEI Flag of Buffer 17 (rh) */
+ unsigned int MEI18:1; /**< \brief [18:18] MEI Flag of Buffer 18 (rh) */
+ unsigned int MEI19:1; /**< \brief [19:19] MEI Flag of Buffer 19 (rh) */
+ unsigned int MEI20:1; /**< \brief [20:20] MEI Flag of Buffer 20 (rh) */
+ unsigned int MEI21:1; /**< \brief [21:21] MEI Flag of Buffer 21 (rh) */
+ unsigned int MEI22:1; /**< \brief [22:22] MEI Flag of Buffer 22 (rh) */
+ unsigned int MEI23:1; /**< \brief [23:23] MEI Flag of Buffer 23 (rh) */
+ unsigned int MEI24:1; /**< \brief [24:24] MEI Flag of Buffer 24 (rh) */
+ unsigned int MEI25:1; /**< \brief [25:25] MEI Flag of Buffer 25 (rh) */
+ unsigned int MEI26:1; /**< \brief [26:26] MEI Flag of Buffer 26 (rh) */
+ unsigned int MEI27:1; /**< \brief [27:27] MEI Flag of Buffer 27 (rh) */
+ unsigned int MEI28:1; /**< \brief [28:28] MEI Flag of Buffer 28 (rh) */
+ unsigned int MEI29:1; /**< \brief [29:29] MEI Flag of Buffer 29 (rh) */
+ unsigned int MEI30:1; /**< \brief [30:30] MEI Flag of Buffer 30 (rh) */
+ unsigned int MEI31:1; /**< \brief [31:31] MEI Flag of Buffer 31 (rh) */
+} Ifx_PSI5_MEIOV_Bits;
+
+/** \brief MEIOV Set Register */
+typedef struct _Ifx_PSI5_MEISET_Bits
+{
+ unsigned int MEI0:1; /**< \brief [0:0] Set MEI Flag of Buffer 0 (w) */
+ unsigned int MEI1:1; /**< \brief [1:1] Set MEI Flag of Buffer 1 (w) */
+ unsigned int MEI2:1; /**< \brief [2:2] Set MEI Flag of Buffer 2 (w) */
+ unsigned int MEI3:1; /**< \brief [3:3] Set MEI Flag of Buffer 3 (w) */
+ unsigned int MEI4:1; /**< \brief [4:4] Set MEI Flag of Buffer 4 (w) */
+ unsigned int MEI5:1; /**< \brief [5:5] Set MEI Flag of Buffer 5 (w) */
+ unsigned int MEI6:1; /**< \brief [6:6] Set MEI Flag of Buffer 6 (w) */
+ unsigned int MEI7:1; /**< \brief [7:7] Set MEI Flag of Buffer 7 (w) */
+ unsigned int MEI8:1; /**< \brief [8:8] Set MEI Flag of Buffer 8 (w) */
+ unsigned int MEI9:1; /**< \brief [9:9] Set MEI Flag of Buffer 9 (w) */
+ unsigned int MEI10:1; /**< \brief [10:10] Set MEI Flag of Buffer 10 (w) */
+ unsigned int MEI11:1; /**< \brief [11:11] Set MEI Flag of Buffer 11 (w) */
+ unsigned int MEI12:1; /**< \brief [12:12] Set MEI Flag of Buffer 12 (w) */
+ unsigned int MEI13:1; /**< \brief [13:13] Set MEI Flag of Buffer 13 (w) */
+ unsigned int MEI14:1; /**< \brief [14:14] Set MEI Flag of Buffer 14 (w) */
+ unsigned int MEI15:1; /**< \brief [15:15] Set MEI Flag of Buffer 15 (w) */
+ unsigned int MEI16:1; /**< \brief [16:16] Set MEI Flag of Buffer 16 (w) */
+ unsigned int MEI17:1; /**< \brief [17:17] Set MEI Flag of Buffer 17 (w) */
+ unsigned int MEI18:1; /**< \brief [18:18] Set MEI Flag of Buffer 18 (w) */
+ unsigned int MEI19:1; /**< \brief [19:19] Set MEI Flag of Buffer 19 (w) */
+ unsigned int MEI20:1; /**< \brief [20:20] Set MEI Flag of Buffer 20 (w) */
+ unsigned int MEI21:1; /**< \brief [21:21] Set MEI Flag of Buffer 21 (w) */
+ unsigned int MEI22:1; /**< \brief [22:22] Set MEI Flag of Buffer 22 (w) */
+ unsigned int MEI23:1; /**< \brief [23:23] Set MEI Flag of Buffer 23 (w) */
+ unsigned int MEI24:1; /**< \brief [24:24] Set MEI Flag of Buffer 24 (w) */
+ unsigned int MEI25:1; /**< \brief [25:25] Set MEI Flag of Buffer 25 (w) */
+ unsigned int MEI26:1; /**< \brief [26:26] Set MEI Flag of Buffer 26 (w) */
+ unsigned int MEI27:1; /**< \brief [27:27] Set MEI Flag of Buffer 27 (w) */
+ unsigned int MEI28:1; /**< \brief [28:28] Set MEI Flag of Buffer 28 (w) */
+ unsigned int MEI29:1; /**< \brief [29:29] Set MEI Flag of Buffer 29 (w) */
+ unsigned int MEI30:1; /**< \brief [30:30] Set MEI Flag of Buffer 30 (w) */
+ unsigned int MEI31:1; /**< \brief [31:31] Set MEI Flag of Buffer 31 (w) */
+} Ifx_PSI5_MEISET_Bits;
+
+/** \brief NBIOV Clear Register */
+typedef struct _Ifx_PSI5_NBICLR_Bits
+{
+ unsigned int NBI0:1; /**< \brief [0:0] Clear NBI Flag of Buffer 0 (w) */
+ unsigned int NBI1:1; /**< \brief [1:1] Clear NBI Flag of Buffer 1 (w) */
+ unsigned int NBI2:1; /**< \brief [2:2] Clear NBI Flag of Buffer 2 (w) */
+ unsigned int NBI3:1; /**< \brief [3:3] Clear NBI Flag of Buffer 3 (w) */
+ unsigned int NBI4:1; /**< \brief [4:4] Clear NBI Flag of Buffer 4 (w) */
+ unsigned int NBI5:1; /**< \brief [5:5] Clear NBI Flag of Buffer 5 (w) */
+ unsigned int NBI6:1; /**< \brief [6:6] Clear NBI Flag of Buffer 6 (w) */
+ unsigned int NBI7:1; /**< \brief [7:7] Clear NBI Flag of Buffer 7 (w) */
+ unsigned int NBI8:1; /**< \brief [8:8] Clear NBI Flag of Buffer 8 (w) */
+ unsigned int NBI9:1; /**< \brief [9:9] Clear NBI Flag of Buffer 9 (w) */
+ unsigned int NBI10:1; /**< \brief [10:10] Clear NBI Flag of Buffer 10 (w) */
+ unsigned int NBI11:1; /**< \brief [11:11] Clear NBI Flag of Buffer 11 (w) */
+ unsigned int NBI12:1; /**< \brief [12:12] Clear NBI Flag of Buffer 12 (w) */
+ unsigned int NBI13:1; /**< \brief [13:13] Clear NBI Flag of Buffer 13 (w) */
+ unsigned int NBI14:1; /**< \brief [14:14] Clear NBI Flag of Buffer 14 (w) */
+ unsigned int NBI15:1; /**< \brief [15:15] Clear NBI Flag of Buffer 15 (w) */
+ unsigned int NBI16:1; /**< \brief [16:16] Clear NBI Flag of Buffer 16 (w) */
+ unsigned int NBI17:1; /**< \brief [17:17] Clear NBI Flag of Buffer 17 (w) */
+ unsigned int NBI18:1; /**< \brief [18:18] Clear NBI Flag of Buffer 18 (w) */
+ unsigned int NBI19:1; /**< \brief [19:19] Clear NBI Flag of Buffer 19 (w) */
+ unsigned int NBI20:1; /**< \brief [20:20] Clear NBI Flag of Buffer 20 (w) */
+ unsigned int NBI21:1; /**< \brief [21:21] Clear NBI Flag of Buffer 21 (w) */
+ unsigned int NBI22:1; /**< \brief [22:22] Clear NBI Flag of Buffer 22 (w) */
+ unsigned int NBI23:1; /**< \brief [23:23] Clear NBI Flag of Buffer 23 (w) */
+ unsigned int NBI24:1; /**< \brief [24:24] Clear NBI Flag of Buffer 24 (w) */
+ unsigned int NBI25:1; /**< \brief [25:25] Clear NBI Flag of Buffer 25 (w) */
+ unsigned int NBI26:1; /**< \brief [26:26] Clear NBI Flag of Buffer 26 (w) */
+ unsigned int NBI27:1; /**< \brief [27:27] Clear NBI Flag of Buffer 27 (w) */
+ unsigned int NBI28:1; /**< \brief [28:28] Clear NBI Flag of Buffer 28 (w) */
+ unsigned int NBI29:1; /**< \brief [29:29] Clear NBI Flag of Buffer 29 (w) */
+ unsigned int NBI30:1; /**< \brief [30:30] Clear NBI Flag of Buffer 30 (w) */
+ unsigned int NBI31:1; /**< \brief [31:31] Clear NBI Flag of Buffer 31 (w) */
+} Ifx_PSI5_NBICLR_Bits;
+
+/** \brief NBI Overview Register */
+typedef struct _Ifx_PSI5_NBIOV_Bits
+{
+ unsigned int NBI0:1; /**< \brief [0:0] NBI Flag of Buffer 0 (rh) */
+ unsigned int NBI1:1; /**< \brief [1:1] NBI Flag of Buffer 1 (rh) */
+ unsigned int NBI2:1; /**< \brief [2:2] NBI Flag of Buffer 2 (rh) */
+ unsigned int NBI3:1; /**< \brief [3:3] NBI Flag of Buffer 3 (rh) */
+ unsigned int NBI4:1; /**< \brief [4:4] NBI Flag of Buffer 4 (rh) */
+ unsigned int NBI5:1; /**< \brief [5:5] NBI Flag of Buffer 5 (rh) */
+ unsigned int NBI6:1; /**< \brief [6:6] NBI Flag of Buffer 6 (rh) */
+ unsigned int NBI7:1; /**< \brief [7:7] NBI Flag of Buffer 7 (rh) */
+ unsigned int NBI8:1; /**< \brief [8:8] NBI Flag of Buffer 8 (rh) */
+ unsigned int NBI9:1; /**< \brief [9:9] NBI Flag of Buffer 9 (rh) */
+ unsigned int NBI10:1; /**< \brief [10:10] NBI Flag of Buffer 10 (rh) */
+ unsigned int NBI11:1; /**< \brief [11:11] NBI Flag of Buffer 11 (rh) */
+ unsigned int NBI12:1; /**< \brief [12:12] NBI Flag of Buffer 12 (rh) */
+ unsigned int NBI13:1; /**< \brief [13:13] NBI Flag of Buffer 13 (rh) */
+ unsigned int NBI14:1; /**< \brief [14:14] NBI Flag of Buffer 14 (rh) */
+ unsigned int NBI15:1; /**< \brief [15:15] NBI Flag of Buffer 15 (rh) */
+ unsigned int NBI16:1; /**< \brief [16:16] NBI Flag of Buffer 16 (rh) */
+ unsigned int NBI17:1; /**< \brief [17:17] NBI Flag of Buffer 17 (rh) */
+ unsigned int NBI18:1; /**< \brief [18:18] NBI Flag of Buffer 18 (rh) */
+ unsigned int NBI19:1; /**< \brief [19:19] NBI Flag of Buffer 19 (rh) */
+ unsigned int NBI20:1; /**< \brief [20:20] NBI Flag of Buffer 20 (rh) */
+ unsigned int NBI21:1; /**< \brief [21:21] NBI Flag of Buffer 21 (rh) */
+ unsigned int NBI22:1; /**< \brief [22:22] NBI Flag of Buffer 22 (rh) */
+ unsigned int NBI23:1; /**< \brief [23:23] NBI Flag of Buffer 23 (rh) */
+ unsigned int NBI24:1; /**< \brief [24:24] NBI Flag of Buffer 24 (rh) */
+ unsigned int NBI25:1; /**< \brief [25:25] NBI Flag of Buffer 25 (rh) */
+ unsigned int NBI26:1; /**< \brief [26:26] NBI Flag of Buffer 26 (rh) */
+ unsigned int NBI27:1; /**< \brief [27:27] NBI Flag of Buffer 27 (rh) */
+ unsigned int NBI28:1; /**< \brief [28:28] NBI Flag of Buffer 28 (rh) */
+ unsigned int NBI29:1; /**< \brief [29:29] NBI Flag of Buffer 29 (rh) */
+ unsigned int NBI30:1; /**< \brief [30:30] NBI Flag of Buffer 30 (rh) */
+ unsigned int NBI31:1; /**< \brief [31:31] NBI Flag of Buffer 31 (rh) */
+} Ifx_PSI5_NBIOV_Bits;
+
+/** \brief NBIOV Set Register */
+typedef struct _Ifx_PSI5_NBISET_Bits
+{
+ unsigned int NBI0:1; /**< \brief [0:0] Set NBI Flag of Buffer 0 (w) */
+ unsigned int NBI1:1; /**< \brief [1:1] Set NBI Flag of Buffer 1 (w) */
+ unsigned int NBI2:1; /**< \brief [2:2] Set NBI Flag of Buffer 2 (w) */
+ unsigned int NBI3:1; /**< \brief [3:3] Set NBI Flag of Buffer 3 (w) */
+ unsigned int NBI4:1; /**< \brief [4:4] Set NBI Flag of Buffer 4 (w) */
+ unsigned int NBI5:1; /**< \brief [5:5] Set NBI Flag of Buffer 5 (w) */
+ unsigned int NBI6:1; /**< \brief [6:6] Set NBI Flag of Buffer 6 (w) */
+ unsigned int NBI7:1; /**< \brief [7:7] Set NBI Flag of Buffer 7 (w) */
+ unsigned int NBI8:1; /**< \brief [8:8] Set NBI Flag of Buffer 8 (w) */
+ unsigned int NBI9:1; /**< \brief [9:9] Set NBI Flag of Buffer 9 (w) */
+ unsigned int NBI10:1; /**< \brief [10:10] Set NBI Flag of Buffer 10 (w) */
+ unsigned int NBI11:1; /**< \brief [11:11] Set NBI Flag of Buffer 11 (w) */
+ unsigned int NBI12:1; /**< \brief [12:12] Set NBI Flag of Buffer 12 (w) */
+ unsigned int NBI13:1; /**< \brief [13:13] Set NBI Flag of Buffer 13 (w) */
+ unsigned int NBI14:1; /**< \brief [14:14] Set NBI Flag of Buffer 14 (w) */
+ unsigned int NBI15:1; /**< \brief [15:15] Set NBI Flag of Buffer 15 (w) */
+ unsigned int NBI16:1; /**< \brief [16:16] Set NBI Flag of Buffer 16 (w) */
+ unsigned int NBI17:1; /**< \brief [17:17] Set NBI Flag of Buffer 17 (w) */
+ unsigned int NBI18:1; /**< \brief [18:18] Set NBI Flag of Buffer 18 (w) */
+ unsigned int NBI19:1; /**< \brief [19:19] Set NBI Flag of Buffer 19 (w) */
+ unsigned int NBI20:1; /**< \brief [20:20] Set NBI Flag of Buffer 20 (w) */
+ unsigned int NBI21:1; /**< \brief [21:21] Set NBI Flag of Buffer 21 (w) */
+ unsigned int NBI22:1; /**< \brief [22:22] Set NBI Flag of Buffer 22 (w) */
+ unsigned int NBI23:1; /**< \brief [23:23] Set NBI Flag of Buffer 23 (w) */
+ unsigned int NBI24:1; /**< \brief [24:24] Set NBI Flag of Buffer 24 (w) */
+ unsigned int NBI25:1; /**< \brief [25:25] Set NBI Flag of Buffer 25 (w) */
+ unsigned int NBI26:1; /**< \brief [26:26] Set NBI Flag of Buffer 26 (w) */
+ unsigned int NBI27:1; /**< \brief [27:27] Set NBI Flag of Buffer 27 (w) */
+ unsigned int NBI28:1; /**< \brief [28:28] Set NBI Flag of Buffer 28 (w) */
+ unsigned int NBI29:1; /**< \brief [29:29] Set NBI Flag of Buffer 29 (w) */
+ unsigned int NBI30:1; /**< \brief [30:30] Set NBI Flag of Buffer 30 (w) */
+ unsigned int NBI31:1; /**< \brief [31:31] Set NBI Flag of Buffer 31 (w) */
+} Ifx_PSI5_NBISET_Bits;
+
+/** \brief NFIOV Clear Register */
+typedef struct _Ifx_PSI5_NFICLR_Bits
+{
+ unsigned int NFI0:1; /**< \brief [0:0] Clear NFI Flag of Buffer 0 (w) */
+ unsigned int NFI1:1; /**< \brief [1:1] Clear NFI Flag of Buffer 1 (w) */
+ unsigned int NFI2:1; /**< \brief [2:2] Clear NFI Flag of Buffer 2 (w) */
+ unsigned int NFI3:1; /**< \brief [3:3] Clear NFI Flag of Buffer 3 (w) */
+ unsigned int NFI4:1; /**< \brief [4:4] Clear NFI Flag of Buffer 4 (w) */
+ unsigned int NFI5:1; /**< \brief [5:5] Clear NFI Flag of Buffer 5 (w) */
+ unsigned int NFI6:1; /**< \brief [6:6] Clear NFI Flag of Buffer 6 (w) */
+ unsigned int NFI7:1; /**< \brief [7:7] Clear NFI Flag of Buffer 7 (w) */
+ unsigned int NFI8:1; /**< \brief [8:8] Clear NFI Flag of Buffer 8 (w) */
+ unsigned int NFI9:1; /**< \brief [9:9] Clear NFI Flag of Buffer 9 (w) */
+ unsigned int NFI10:1; /**< \brief [10:10] Clear NFI Flag of Buffer 10 (w) */
+ unsigned int NFI11:1; /**< \brief [11:11] Clear NFI Flag of Buffer 11 (w) */
+ unsigned int NFI12:1; /**< \brief [12:12] Clear NFI Flag of Buffer 12 (w) */
+ unsigned int NFI13:1; /**< \brief [13:13] Clear NFI Flag of Buffer 13 (w) */
+ unsigned int NFI14:1; /**< \brief [14:14] Clear NFI Flag of Buffer 14 (w) */
+ unsigned int NFI15:1; /**< \brief [15:15] Clear NFI Flag of Buffer 15 (w) */
+ unsigned int NFI16:1; /**< \brief [16:16] Clear NFI Flag of Buffer 16 (w) */
+ unsigned int NFI17:1; /**< \brief [17:17] Clear NFI Flag of Buffer 17 (w) */
+ unsigned int NFI18:1; /**< \brief [18:18] Clear NFI Flag of Buffer 18 (w) */
+ unsigned int NFI19:1; /**< \brief [19:19] Clear NFI Flag of Buffer 19 (w) */
+ unsigned int NFI20:1; /**< \brief [20:20] Clear NFI Flag of Buffer 20 (w) */
+ unsigned int NFI21:1; /**< \brief [21:21] Clear NFI Flag of Buffer 21 (w) */
+ unsigned int NFI22:1; /**< \brief [22:22] Clear NFI Flag of Buffer 22 (w) */
+ unsigned int NFI23:1; /**< \brief [23:23] Clear NFI Flag of Buffer 23 (w) */
+ unsigned int NFI24:1; /**< \brief [24:24] Clear NFI Flag of Buffer 24 (w) */
+ unsigned int NFI25:1; /**< \brief [25:25] Clear NFI Flag of Buffer 25 (w) */
+ unsigned int NFI26:1; /**< \brief [26:26] Clear NFI Flag of Buffer 26 (w) */
+ unsigned int NFI27:1; /**< \brief [27:27] Clear NFI Flag of Buffer 27 (w) */
+ unsigned int NFI28:1; /**< \brief [28:28] Clear NFI Flag of Buffer 28 (w) */
+ unsigned int NFI29:1; /**< \brief [29:29] Clear NFI Flag of Buffer 29 (w) */
+ unsigned int NFI30:1; /**< \brief [30:30] Clear NFI Flag of Buffer 30 (w) */
+ unsigned int NFI31:1; /**< \brief [31:31] Clear NFI Flag of Buffer 31 (w) */
+} Ifx_PSI5_NFICLR_Bits;
+
+/** \brief NFI Overview Register */
+typedef struct _Ifx_PSI5_NFIOV_Bits
+{
+ unsigned int NFI0:1; /**< \brief [0:0] NFI Flag of Buffer 0 (rh) */
+ unsigned int NFI1:1; /**< \brief [1:1] NFI Flag of Buffer 1 (rh) */
+ unsigned int NFI2:1; /**< \brief [2:2] NFI Flag of Buffer 2 (rh) */
+ unsigned int NFI3:1; /**< \brief [3:3] NFI Flag of Buffer 3 (rh) */
+ unsigned int NFI4:1; /**< \brief [4:4] NFI Flag of Buffer 4 (rh) */
+ unsigned int NFI5:1; /**< \brief [5:5] NFI Flag of Buffer 5 (rh) */
+ unsigned int NFI6:1; /**< \brief [6:6] NFI Flag of Buffer 6 (rh) */
+ unsigned int NFI7:1; /**< \brief [7:7] NFI Flag of Buffer 7 (rh) */
+ unsigned int NFI8:1; /**< \brief [8:8] NFI Flag of Buffer 8 (rh) */
+ unsigned int NFI9:1; /**< \brief [9:9] NFI Flag of Buffer 9 (rh) */
+ unsigned int NFI10:1; /**< \brief [10:10] NFI Flag of Buffer 10 (rh) */
+ unsigned int NFI11:1; /**< \brief [11:11] NFI Flag of Buffer 11 (rh) */
+ unsigned int NFI12:1; /**< \brief [12:12] NFI Flag of Buffer 12 (rh) */
+ unsigned int NFI13:1; /**< \brief [13:13] NFI Flag of Buffer 13 (rh) */
+ unsigned int NFI14:1; /**< \brief [14:14] NFI Flag of Buffer 14 (rh) */
+ unsigned int NFI15:1; /**< \brief [15:15] NFI Flag of Buffer 15 (rh) */
+ unsigned int NFI16:1; /**< \brief [16:16] NFI Flag of Buffer 16 (rh) */
+ unsigned int NFI17:1; /**< \brief [17:17] NFI Flag of Buffer 17 (rh) */
+ unsigned int NFI18:1; /**< \brief [18:18] NFI Flag of Buffer 18 (rh) */
+ unsigned int NFI19:1; /**< \brief [19:19] NFI Flag of Buffer 19 (rh) */
+ unsigned int NFI20:1; /**< \brief [20:20] NFI Flag of Buffer 20 (rh) */
+ unsigned int NFI21:1; /**< \brief [21:21] NFI Flag of Buffer 21 (rh) */
+ unsigned int NFI22:1; /**< \brief [22:22] NFI Flag of Buffer 22 (rh) */
+ unsigned int NFI23:1; /**< \brief [23:23] NFI Flag of Buffer 23 (rh) */
+ unsigned int NFI24:1; /**< \brief [24:24] NFI Flag of Buffer 24 (rh) */
+ unsigned int NFI25:1; /**< \brief [25:25] NFI Flag of Buffer 25 (rh) */
+ unsigned int NFI26:1; /**< \brief [26:26] NFI Flag of Buffer 26 (rh) */
+ unsigned int NFI27:1; /**< \brief [27:27] NFI Flag of Buffer 27 (rh) */
+ unsigned int NFI28:1; /**< \brief [28:28] NFI Flag of Buffer 28 (rh) */
+ unsigned int NFI29:1; /**< \brief [29:29] NFI Flag of Buffer 29 (rh) */
+ unsigned int NFI30:1; /**< \brief [30:30] NFI Flag of Buffer 30 (rh) */
+ unsigned int NFI31:1; /**< \brief [31:31] NFI Flag of Buffer 31 (rh) */
+} Ifx_PSI5_NFIOV_Bits;
+
+/** \brief NFIOV Set Register */
+typedef struct _Ifx_PSI5_NFISET_Bits
+{
+ unsigned int NFI0:1; /**< \brief [0:0] Set NFI Flag of Buffer 0 (w) */
+ unsigned int NFI1:1; /**< \brief [1:1] Set NFI Flag of Buffer 1 (w) */
+ unsigned int NFI2:1; /**< \brief [2:2] Set NFI Flag of Buffer 2 (w) */
+ unsigned int NFI3:1; /**< \brief [3:3] Set NFI Flag of Buffer 3 (w) */
+ unsigned int NFI4:1; /**< \brief [4:4] Set NFI Flag of Buffer 4 (w) */
+ unsigned int NFI5:1; /**< \brief [5:5] Set NFI Flag of Buffer 5 (w) */
+ unsigned int NFI6:1; /**< \brief [6:6] Set NFI Flag of Buffer 6 (w) */
+ unsigned int NFI7:1; /**< \brief [7:7] Set NFI Flag of Buffer 7 (w) */
+ unsigned int NFI8:1; /**< \brief [8:8] Set NFI Flag of Buffer 8 (w) */
+ unsigned int NFI9:1; /**< \brief [9:9] Set NFI Flag of Buffer 9 (w) */
+ unsigned int NFI10:1; /**< \brief [10:10] Set NFI Flag of Buffer 10 (w) */
+ unsigned int NFI11:1; /**< \brief [11:11] Set NFI Flag of Buffer 11 (w) */
+ unsigned int NFI12:1; /**< \brief [12:12] Set NFI Flag of Buffer 12 (w) */
+ unsigned int NFI13:1; /**< \brief [13:13] Set NFI Flag of Buffer 13 (w) */
+ unsigned int NFI14:1; /**< \brief [14:14] Set NFI Flag of Buffer 14 (w) */
+ unsigned int NFI15:1; /**< \brief [15:15] Set NFI Flag of Buffer 15 (w) */
+ unsigned int NFI16:1; /**< \brief [16:16] Set NFI Flag of Buffer 16 (w) */
+ unsigned int NFI17:1; /**< \brief [17:17] Set NFI Flag of Buffer 17 (w) */
+ unsigned int NFI18:1; /**< \brief [18:18] Set NFI Flag of Buffer 18 (w) */
+ unsigned int NFI19:1; /**< \brief [19:19] Set NFI Flag of Buffer 19 (w) */
+ unsigned int NFI20:1; /**< \brief [20:20] Set NFI Flag of Buffer 20 (w) */
+ unsigned int NFI21:1; /**< \brief [21:21] Set NFI Flag of Buffer 21 (w) */
+ unsigned int NFI22:1; /**< \brief [22:22] Set NFI Flag of Buffer 22 (w) */
+ unsigned int NFI23:1; /**< \brief [23:23] Set NFI Flag of Buffer 23 (w) */
+ unsigned int NFI24:1; /**< \brief [24:24] Set NFI Flag of Buffer 24 (w) */
+ unsigned int NFI25:1; /**< \brief [25:25] Set NFI Flag of Buffer 25 (w) */
+ unsigned int NFI26:1; /**< \brief [26:26] Set NFI Flag of Buffer 26 (w) */
+ unsigned int NFI27:1; /**< \brief [27:27] Set NFI Flag of Buffer 27 (w) */
+ unsigned int NFI28:1; /**< \brief [28:28] Set NFI Flag of Buffer 28 (w) */
+ unsigned int NFI29:1; /**< \brief [29:29] Set NFI Flag of Buffer 29 (w) */
+ unsigned int NFI30:1; /**< \brief [30:30] Set NFI Flag of Buffer 30 (w) */
+ unsigned int NFI31:1; /**< \brief [31:31] Set NFI Flag of Buffer 31 (w) */
+} Ifx_PSI5_NFISET_Bits;
+
+/** \brief OCDS Control and Status */
+typedef struct _Ifx_PSI5_OCS_Bits
+{
+ unsigned int reserved_0:24; /**< \brief \internal Reserved */
+ unsigned int SUS:4; /**< \brief [27:24] OCDS Suspend Control (rw) */
+ unsigned int SUS_P:1; /**< \brief [28:28] SUS Write Protection (w) */
+ unsigned int SUSSTA:1; /**< \brief [29:29] Suspend State (rh) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_PSI5_OCS_Bits;
+
+/** \brief Receive Data FIFO */
+typedef struct _Ifx_PSI5_RDF_Bits
+{
+ unsigned int RD:32; /**< \brief [31:0] RD (rh) */
+} Ifx_PSI5_RDF_Bits;
+
+/** \brief RDIOV Clear Register */
+typedef struct _Ifx_PSI5_RDICLR_Bits
+{
+ unsigned int RDI0:1; /**< \brief [0:0] Clear RDI Flag of Buffer 0 (w) */
+ unsigned int RDI1:1; /**< \brief [1:1] Clear RDI Flag of Buffer 1 (w) */
+ unsigned int RDI2:1; /**< \brief [2:2] Clear RDI Flag of Buffer 2 (w) */
+ unsigned int RDI3:1; /**< \brief [3:3] Clear RDI Flag of Buffer 3 (w) */
+ unsigned int RDI4:1; /**< \brief [4:4] Clear RDI Flag of Buffer 4 (w) */
+ unsigned int RDI5:1; /**< \brief [5:5] Clear RDI Flag of Buffer 5 (w) */
+ unsigned int RDI6:1; /**< \brief [6:6] Clear RDI Flag of Buffer 6 (w) */
+ unsigned int RDI7:1; /**< \brief [7:7] Clear RDI Flag of Buffer 7 (w) */
+ unsigned int RDI8:1; /**< \brief [8:8] Clear RDI Flag of Buffer 8 (w) */
+ unsigned int RDI9:1; /**< \brief [9:9] Clear RDI Flag of Buffer 9 (w) */
+ unsigned int RDI10:1; /**< \brief [10:10] Clear RDI Flag of Buffer 10 (w) */
+ unsigned int RDI11:1; /**< \brief [11:11] Clear RDI Flag of Buffer 11 (w) */
+ unsigned int RDI12:1; /**< \brief [12:12] Clear RDI Flag of Buffer 12 (w) */
+ unsigned int RDI13:1; /**< \brief [13:13] Clear RDI Flag of Buffer 13 (w) */
+ unsigned int RDI14:1; /**< \brief [14:14] Clear RDI Flag of Buffer 14 (w) */
+ unsigned int RDI15:1; /**< \brief [15:15] Clear RDI Flag of Buffer 15 (w) */
+ unsigned int RDI16:1; /**< \brief [16:16] Clear RDI Flag of Buffer 16 (w) */
+ unsigned int RDI17:1; /**< \brief [17:17] Clear RDI Flag of Buffer 17 (w) */
+ unsigned int RDI18:1; /**< \brief [18:18] Clear RDI Flag of Buffer 18 (w) */
+ unsigned int RDI19:1; /**< \brief [19:19] Clear RDI Flag of Buffer 19 (w) */
+ unsigned int RDI20:1; /**< \brief [20:20] Clear RDI Flag of Buffer 20 (w) */
+ unsigned int RDI21:1; /**< \brief [21:21] Clear RDI Flag of Buffer 21 (w) */
+ unsigned int RDI22:1; /**< \brief [22:22] Clear RDI Flag of Buffer 22 (w) */
+ unsigned int RDI23:1; /**< \brief [23:23] Clear RDI Flag of Buffer 23 (w) */
+ unsigned int RDI24:1; /**< \brief [24:24] Clear RDI Flag of Buffer 24 (w) */
+ unsigned int RDI25:1; /**< \brief [25:25] Clear RDI Flag of Buffer 25 (w) */
+ unsigned int RDI26:1; /**< \brief [26:26] Clear RDI Flag of Buffer 26 (w) */
+ unsigned int RDI27:1; /**< \brief [27:27] Clear RDI Flag of Buffer 27 (w) */
+ unsigned int RDI28:1; /**< \brief [28:28] Clear RDI Flag of Buffer 28 (w) */
+ unsigned int RDI29:1; /**< \brief [29:29] Clear RDI Flag of Buffer 29 (w) */
+ unsigned int RDI30:1; /**< \brief [30:30] Clear RDI Flag of Buffer 30 (w) */
+ unsigned int RDI31:1; /**< \brief [31:31] Clear RDI Flag of Buffer 31 (w) */
+} Ifx_PSI5_RDICLR_Bits;
+
+/** \brief RDI Overview Register */
+typedef struct _Ifx_PSI5_RDIOV_Bits
+{
+ unsigned int RDI0:1; /**< \brief [0:0] RDI Flag of Buffer 0 (rh) */
+ unsigned int RDI1:1; /**< \brief [1:1] RDI Flag of Buffer 1 (rh) */
+ unsigned int RDI2:1; /**< \brief [2:2] RDI Flag of Buffer 2 (rh) */
+ unsigned int RDI3:1; /**< \brief [3:3] RDI Flag of Buffer 3 (rh) */
+ unsigned int RDI4:1; /**< \brief [4:4] RDI Flag of Buffer 4 (rh) */
+ unsigned int RDI5:1; /**< \brief [5:5] RDI Flag of Buffer 5 (rh) */
+ unsigned int RDI6:1; /**< \brief [6:6] RDI Flag of Buffer 6 (rh) */
+ unsigned int RDI7:1; /**< \brief [7:7] RDI Flag of Buffer 7 (rh) */
+ unsigned int RDI8:1; /**< \brief [8:8] RDI Flag of Buffer 8 (rh) */
+ unsigned int RDI9:1; /**< \brief [9:9] RDI Flag of Buffer 9 (rh) */
+ unsigned int RDI10:1; /**< \brief [10:10] RDI Flag of Buffer 10 (rh) */
+ unsigned int RDI11:1; /**< \brief [11:11] RDI Flag of Buffer 11 (rh) */
+ unsigned int RDI12:1; /**< \brief [12:12] RDI Flag of Buffer 12 (rh) */
+ unsigned int RDI13:1; /**< \brief [13:13] RDI Flag of Buffer 13 (rh) */
+ unsigned int RDI14:1; /**< \brief [14:14] RDI Flag of Buffer 14 (rh) */
+ unsigned int RDI15:1; /**< \brief [15:15] RDI Flag of Buffer 15 (rh) */
+ unsigned int RDI16:1; /**< \brief [16:16] RDI Flag of Buffer 16 (rh) */
+ unsigned int RDI17:1; /**< \brief [17:17] RDI Flag of Buffer 17 (rh) */
+ unsigned int RDI18:1; /**< \brief [18:18] RDI Flag of Buffer 18 (rh) */
+ unsigned int RDI19:1; /**< \brief [19:19] RDI Flag of Buffer 19 (rh) */
+ unsigned int RDI20:1; /**< \brief [20:20] RDI Flag of Buffer 20 (rh) */
+ unsigned int RDI21:1; /**< \brief [21:21] RDI Flag of Buffer 21 (rh) */
+ unsigned int RDI22:1; /**< \brief [22:22] RDI Flag of Buffer 22 (rh) */
+ unsigned int RDI23:1; /**< \brief [23:23] RDI Flag of Buffer 23 (rh) */
+ unsigned int RDI24:1; /**< \brief [24:24] RDI Flag of Buffer 24 (rh) */
+ unsigned int RDI25:1; /**< \brief [25:25] RDI Flag of Buffer 25 (rh) */
+ unsigned int RDI26:1; /**< \brief [26:26] RDI Flag of Buffer 26 (rh) */
+ unsigned int RDI27:1; /**< \brief [27:27] RDI Flag of Buffer 27 (rh) */
+ unsigned int RDI28:1; /**< \brief [28:28] RDI Flag of Buffer 28 (rh) */
+ unsigned int RDI29:1; /**< \brief [29:29] RDI Flag of Buffer 29 (rh) */
+ unsigned int RDI30:1; /**< \brief [30:30] RDI Flag of Buffer 30 (rh) */
+ unsigned int RDI31:1; /**< \brief [31:31] RDI Flag of Buffer 31 (rh) */
+} Ifx_PSI5_RDIOV_Bits;
+
+/** \brief RDIOV Set Register */
+typedef struct _Ifx_PSI5_RDISET_Bits
+{
+ unsigned int RDI0:1; /**< \brief [0:0] Set RDI Flag of Buffer 0 (w) */
+ unsigned int RDI1:1; /**< \brief [1:1] Set RDI Flag of Buffer 1 (w) */
+ unsigned int RDI2:1; /**< \brief [2:2] Set RDI Flag of Buffer 2 (w) */
+ unsigned int RDI3:1; /**< \brief [3:3] Set RDI Flag of Buffer 3 (w) */
+ unsigned int RDI4:1; /**< \brief [4:4] Set RDI Flag of Buffer 4 (w) */
+ unsigned int RDI5:1; /**< \brief [5:5] Set RDI Flag of Buffer 5 (w) */
+ unsigned int RDI6:1; /**< \brief [6:6] Set RDI Flag of Buffer 6 (w) */
+ unsigned int RDI7:1; /**< \brief [7:7] Set RDI Flag of Buffer 7 (w) */
+ unsigned int RDI8:1; /**< \brief [8:8] Set RDI Flag of Buffer 8 (w) */
+ unsigned int RDI9:1; /**< \brief [9:9] Set RDI Flag of Buffer 9 (w) */
+ unsigned int RDI10:1; /**< \brief [10:10] Set RDI Flag of Buffer 10 (w) */
+ unsigned int RDI11:1; /**< \brief [11:11] Set RDI Flag of Buffer 11 (w) */
+ unsigned int RDI12:1; /**< \brief [12:12] Set RDI Flag of Buffer 12 (w) */
+ unsigned int RDI13:1; /**< \brief [13:13] Set RDI Flag of Buffer 13 (w) */
+ unsigned int RDI14:1; /**< \brief [14:14] Set RDI Flag of Buffer 14 (w) */
+ unsigned int RDI15:1; /**< \brief [15:15] Set RDI Flag of Buffer 15 (w) */
+ unsigned int RDI16:1; /**< \brief [16:16] Set RDI Flag of Buffer 16 (w) */
+ unsigned int RDI17:1; /**< \brief [17:17] Set RDI Flag of Buffer 17 (w) */
+ unsigned int RDI18:1; /**< \brief [18:18] Set RDI Flag of Buffer 18 (w) */
+ unsigned int RDI19:1; /**< \brief [19:19] Set RDI Flag of Buffer 19 (w) */
+ unsigned int RDI20:1; /**< \brief [20:20] Set RDI Flag of Buffer 20 (w) */
+ unsigned int RDI21:1; /**< \brief [21:21] Set RDI Flag of Buffer 21 (w) */
+ unsigned int RDI22:1; /**< \brief [22:22] Set RDI Flag of Buffer 22 (w) */
+ unsigned int RDI23:1; /**< \brief [23:23] Set RDI Flag of Buffer 23 (w) */
+ unsigned int RDI24:1; /**< \brief [24:24] Set RDI Flag of Buffer 24 (w) */
+ unsigned int RDI25:1; /**< \brief [25:25] Set RDI Flag of Buffer 25 (w) */
+ unsigned int RDI26:1; /**< \brief [26:26] Set RDI Flag of Buffer 26 (w) */
+ unsigned int RDI27:1; /**< \brief [27:27] Set RDI Flag of Buffer 27 (w) */
+ unsigned int RDI28:1; /**< \brief [28:28] Set RDI Flag of Buffer 28 (w) */
+ unsigned int RDI29:1; /**< \brief [29:29] Set RDI Flag of Buffer 29 (w) */
+ unsigned int RDI30:1; /**< \brief [30:30] Set RDI Flag of Buffer 30 (w) */
+ unsigned int RDI31:1; /**< \brief [31:31] Set RDI Flag of Buffer 31 (w) */
+} Ifx_PSI5_RDISET_Bits;
+
+/** \brief Receive Data Memory High */
+typedef struct _Ifx_PSI5_RDM_H_Bits
+{
+ unsigned int TS:24; /**< \brief [23:0] Time Stamp (rh) */
+ unsigned int SC:3; /**< \brief [26:24] Slot Counter (rh) */
+ unsigned int TEI:1; /**< \brief [27:27] Time Slot Error Flag (rh) */
+ unsigned int NBI:1; /**< \brief [28:28] Number of bits Error Flag (rh) */
+ unsigned int MEI:1; /**< \brief [29:29] Error in Messaging Bits Flag (rh) */
+ unsigned int NFI:1; /**< \brief [30:30] No Frame Received Flag (rh) */
+ unsigned int RMI:1; /**< \brief [31:31] Receive Memory Overflow Flag (rh) */
+} Ifx_PSI5_RDM_H_Bits;
+
+/** \brief Receive Data Memory Low */
+typedef struct _Ifx_PSI5_RDM_L_Bits
+{
+ unsigned int CRCI:1; /**< \brief [0:0] CRC Error Flag (rh) */
+ unsigned int CRC:3; /**< \brief [3:1] CRC (rh) */
+ unsigned int RD:28; /**< \brief [31:4] RD (rh) */
+} Ifx_PSI5_RDM_L_Bits;
+
+/** \brief Receive FIFO Control Register */
+typedef struct _Ifx_PSI5_RFC_Bits
+{
+ unsigned int REP:6; /**< \brief [5:0] FIFO Read Pointer (r) */
+ unsigned int reserved_6:2; /**< \brief \internal Reserved */
+ unsigned int WRP:6; /**< \brief [13:8] FIFO/Ring Buffer Write Pointer (r) */
+ unsigned int reserved_14:2; /**< \brief \internal Reserved */
+ unsigned int FWL:5; /**< \brief [20:16] FIFO Warning Level (rw) */
+ unsigned int reserved_21:8; /**< \brief \internal Reserved */
+ unsigned int WRAP:1; /**< \brief [29:29] Write Pointer WRAP Indicator (r) */
+ unsigned int FRQ:1; /**< \brief [30:30] Flush Request (r) */
+ unsigned int FLU:1; /**< \brief [31:31] Flush (w) */
+} Ifx_PSI5_RFC_Bits;
+
+/** \brief RMIOV Clear Register */
+typedef struct _Ifx_PSI5_RMICLR_Bits
+{
+ unsigned int RMI0:1; /**< \brief [0:0] Clear RMI Flag of Buffer 0 (w) */
+ unsigned int RMI1:1; /**< \brief [1:1] Clear RMI Flag of Buffer 1 (w) */
+ unsigned int RMI2:1; /**< \brief [2:2] Clear RMI Flag of Buffer 2 (w) */
+ unsigned int RMI3:1; /**< \brief [3:3] Clear RMI Flag of Buffer 3 (w) */
+ unsigned int RMI4:1; /**< \brief [4:4] Clear RMI Flag of Buffer 4 (w) */
+ unsigned int RMI5:1; /**< \brief [5:5] Clear RMI Flag of Buffer 5 (w) */
+ unsigned int RMI6:1; /**< \brief [6:6] Clear RMI Flag of Buffer 6 (w) */
+ unsigned int RMI7:1; /**< \brief [7:7] Clear RMI Flag of Buffer 7 (w) */
+ unsigned int RMI8:1; /**< \brief [8:8] Clear RMI Flag of Buffer 8 (w) */
+ unsigned int RMI9:1; /**< \brief [9:9] Clear RMI Flag of Buffer 9 (w) */
+ unsigned int RMI10:1; /**< \brief [10:10] Clear RMI Flag of Buffer 10 (w) */
+ unsigned int RMI11:1; /**< \brief [11:11] Clear RMI Flag of Buffer 11 (w) */
+ unsigned int RMI12:1; /**< \brief [12:12] Clear RMI Flag of Buffer 12 (w) */
+ unsigned int RMI13:1; /**< \brief [13:13] Clear RMI Flag of Buffer 13 (w) */
+ unsigned int RMI14:1; /**< \brief [14:14] Clear RMI Flag of Buffer 14 (w) */
+ unsigned int RMI15:1; /**< \brief [15:15] Clear RMI Flag of Buffer 15 (w) */
+ unsigned int RMI16:1; /**< \brief [16:16] Clear RMI Flag of Buffer 16 (w) */
+ unsigned int RMI17:1; /**< \brief [17:17] Clear RMI Flag of Buffer 17 (w) */
+ unsigned int RMI18:1; /**< \brief [18:18] Clear RMI Flag of Buffer 18 (w) */
+ unsigned int RMI19:1; /**< \brief [19:19] Clear RMI Flag of Buffer 19 (w) */
+ unsigned int RMI20:1; /**< \brief [20:20] Clear RMI Flag of Buffer 20 (w) */
+ unsigned int RMI21:1; /**< \brief [21:21] Clear RMI Flag of Buffer 21 (w) */
+ unsigned int RMI22:1; /**< \brief [22:22] Clear RMI Flag of Buffer 22 (w) */
+ unsigned int RMI23:1; /**< \brief [23:23] Clear RMI Flag of Buffer 23 (w) */
+ unsigned int RMI24:1; /**< \brief [24:24] Clear RMI Flag of Buffer 24 (w) */
+ unsigned int RMI25:1; /**< \brief [25:25] Clear RMI Flag of Buffer 25 (w) */
+ unsigned int RMI26:1; /**< \brief [26:26] Clear RMI Flag of Buffer 26 (w) */
+ unsigned int RMI27:1; /**< \brief [27:27] Clear RMI Flag of Buffer 27 (w) */
+ unsigned int RMI28:1; /**< \brief [28:28] Clear RMI Flag of Buffer 28 (w) */
+ unsigned int RMI29:1; /**< \brief [29:29] Clear RMI Flag of Buffer 29 (w) */
+ unsigned int RMI30:1; /**< \brief [30:30] Clear RMI Flag of Buffer 30 (w) */
+ unsigned int RMI31:1; /**< \brief [31:31] Clear RMI Flag of Buffer 31 (w) */
+} Ifx_PSI5_RMICLR_Bits;
+
+/** \brief RMI Overview Register */
+typedef struct _Ifx_PSI5_RMIOV_Bits
+{
+ unsigned int RMI0:1; /**< \brief [0:0] RMI Flag of Buffer 0 (rh) */
+ unsigned int RMI1:1; /**< \brief [1:1] RMI Flag of Buffer 1 (rh) */
+ unsigned int RMI2:1; /**< \brief [2:2] RMI Flag of Buffer 2 (rh) */
+ unsigned int RMI3:1; /**< \brief [3:3] RMI Flag of Buffer 3 (rh) */
+ unsigned int RMI4:1; /**< \brief [4:4] RMI Flag of Buffer 4 (rh) */
+ unsigned int RMI5:1; /**< \brief [5:5] RMI Flag of Buffer 5 (rh) */
+ unsigned int RMI6:1; /**< \brief [6:6] RMI Flag of Buffer 6 (rh) */
+ unsigned int RMI7:1; /**< \brief [7:7] RMI Flag of Buffer 7 (rh) */
+ unsigned int RMI8:1; /**< \brief [8:8] RMI Flag of Buffer 8 (rh) */
+ unsigned int RMI9:1; /**< \brief [9:9] RMI Flag of Buffer 9 (rh) */
+ unsigned int RMI10:1; /**< \brief [10:10] RMI Flag of Buffer 10 (rh) */
+ unsigned int RMI11:1; /**< \brief [11:11] RMI Flag of Buffer 11 (rh) */
+ unsigned int RMI12:1; /**< \brief [12:12] RMI Flag of Buffer 12 (rh) */
+ unsigned int RMI13:1; /**< \brief [13:13] RMI Flag of Buffer 13 (rh) */
+ unsigned int RMI14:1; /**< \brief [14:14] RMI Flag of Buffer 14 (rh) */
+ unsigned int RMI15:1; /**< \brief [15:15] RMI Flag of Buffer 15 (rh) */
+ unsigned int RMI16:1; /**< \brief [16:16] RMI Flag of Buffer 16 (rh) */
+ unsigned int RMI17:1; /**< \brief [17:17] RMI Flag of Buffer 17 (rh) */
+ unsigned int RMI18:1; /**< \brief [18:18] RMI Flag of Buffer 18 (rh) */
+ unsigned int RMI19:1; /**< \brief [19:19] RMI Flag of Buffer 19 (rh) */
+ unsigned int RMI20:1; /**< \brief [20:20] RMI Flag of Buffer 20 (rh) */
+ unsigned int RMI21:1; /**< \brief [21:21] RMI Flag of Buffer 21 (rh) */
+ unsigned int RMI22:1; /**< \brief [22:22] RMI Flag of Buffer 22 (rh) */
+ unsigned int RMI23:1; /**< \brief [23:23] RMI Flag of Buffer 23 (rh) */
+ unsigned int RMI24:1; /**< \brief [24:24] RMI Flag of Buffer 24 (rh) */
+ unsigned int RMI25:1; /**< \brief [25:25] RMI Flag of Buffer 25 (rh) */
+ unsigned int RMI26:1; /**< \brief [26:26] RMI Flag of Buffer 26 (rh) */
+ unsigned int RMI27:1; /**< \brief [27:27] RMI Flag of Buffer 27 (rh) */
+ unsigned int RMI28:1; /**< \brief [28:28] RMI Flag of Buffer 28 (rh) */
+ unsigned int RMI29:1; /**< \brief [29:29] RMI Flag of Buffer 29 (rh) */
+ unsigned int RMI30:1; /**< \brief [30:30] RMI Flag of Buffer 30 (rh) */
+ unsigned int RMI31:1; /**< \brief [31:31] RMI Flag of Buffer 31 (rh) */
+} Ifx_PSI5_RMIOV_Bits;
+
+/** \brief RMIOV Set Register */
+typedef struct _Ifx_PSI5_RMISET_Bits
+{
+ unsigned int RMI0:1; /**< \brief [0:0] Set RMI Flag of Buffer 0 (w) */
+ unsigned int RMI1:1; /**< \brief [1:1] Set RMI Flag of Buffer 1 (w) */
+ unsigned int RMI2:1; /**< \brief [2:2] Set RMI Flag of Buffer 2 (w) */
+ unsigned int RMI3:1; /**< \brief [3:3] Set RMI Flag of Buffer 3 (w) */
+ unsigned int RMI4:1; /**< \brief [4:4] Set RMI Flag of Buffer 4 (w) */
+ unsigned int RMI5:1; /**< \brief [5:5] Set RMI Flag of Buffer 5 (w) */
+ unsigned int RMI6:1; /**< \brief [6:6] Set RMI Flag of Buffer 6 (w) */
+ unsigned int RMI7:1; /**< \brief [7:7] Set RMI Flag of Buffer 7 (w) */
+ unsigned int RMI8:1; /**< \brief [8:8] Set RMI Flag of Buffer 8 (w) */
+ unsigned int RMI9:1; /**< \brief [9:9] Set RMI Flag of Buffer 9 (w) */
+ unsigned int RMI10:1; /**< \brief [10:10] Set RMI Flag of Buffer 10 (w) */
+ unsigned int RMI11:1; /**< \brief [11:11] Set RMI Flag of Buffer 11 (w) */
+ unsigned int RMI12:1; /**< \brief [12:12] Set RMI Flag of Buffer 12 (w) */
+ unsigned int RMI13:1; /**< \brief [13:13] Set RMI Flag of Buffer 13 (w) */
+ unsigned int RMI14:1; /**< \brief [14:14] Set RMI Flag of Buffer 14 (w) */
+ unsigned int RMI15:1; /**< \brief [15:15] Set RMI Flag of Buffer 15 (w) */
+ unsigned int RMI16:1; /**< \brief [16:16] Set RMI Flag of Buffer 16 (w) */
+ unsigned int RMI17:1; /**< \brief [17:17] Set RMI Flag of Buffer 17 (w) */
+ unsigned int RMI18:1; /**< \brief [18:18] Set RMI Flag of Buffer 18 (w) */
+ unsigned int RMI19:1; /**< \brief [19:19] Set RMI Flag of Buffer 19 (w) */
+ unsigned int RMI20:1; /**< \brief [20:20] Set RMI Flag of Buffer 20 (w) */
+ unsigned int RMI21:1; /**< \brief [21:21] Set RMI Flag of Buffer 21 (w) */
+ unsigned int RMI22:1; /**< \brief [22:22] Set RMI Flag of Buffer 22 (w) */
+ unsigned int RMI23:1; /**< \brief [23:23] Set RMI Flag of Buffer 23 (w) */
+ unsigned int RMI24:1; /**< \brief [24:24] Set RMI Flag of Buffer 24 (w) */
+ unsigned int RMI25:1; /**< \brief [25:25] Set RMI Flag of Buffer 25 (w) */
+ unsigned int RMI26:1; /**< \brief [26:26] Set RMI Flag of Buffer 26 (w) */
+ unsigned int RMI27:1; /**< \brief [27:27] Set RMI Flag of Buffer 27 (w) */
+ unsigned int RMI28:1; /**< \brief [28:28] Set RMI Flag of Buffer 28 (w) */
+ unsigned int RMI29:1; /**< \brief [29:29] Set RMI Flag of Buffer 29 (w) */
+ unsigned int RMI30:1; /**< \brief [30:30] Set RMI Flag of Buffer 30 (w) */
+ unsigned int RMI31:1; /**< \brief [31:31] Set RMI Flag of Buffer 31 (w) */
+} Ifx_PSI5_RMISET_Bits;
+
+/** \brief RSIOV Clear Register */
+typedef struct _Ifx_PSI5_RSICLR_Bits
+{
+ unsigned int RSI0:1; /**< \brief [0:0] Clear RSI Flag of Buffer 0 (w) */
+ unsigned int RSI1:1; /**< \brief [1:1] Clear RSI Flag of Buffer 1 (w) */
+ unsigned int RSI2:1; /**< \brief [2:2] Clear RSI Flag of Buffer 2 (w) */
+ unsigned int RSI3:1; /**< \brief [3:3] Clear RSI Flag of Buffer 3 (w) */
+ unsigned int RSI4:1; /**< \brief [4:4] Clear RSI Flag of Buffer 4 (w) */
+ unsigned int RSI5:1; /**< \brief [5:5] Clear RSI Flag of Buffer 5 (w) */
+ unsigned int RSI6:1; /**< \brief [6:6] Clear RSI Flag of Buffer 6 (w) */
+ unsigned int RSI7:1; /**< \brief [7:7] Clear RSI Flag of Buffer 7 (w) */
+ unsigned int RSI8:1; /**< \brief [8:8] Clear RSI Flag of Buffer 8 (w) */
+ unsigned int RSI9:1; /**< \brief [9:9] Clear RSI Flag of Buffer 9 (w) */
+ unsigned int RSI10:1; /**< \brief [10:10] Clear RSI Flag of Buffer 10 (w) */
+ unsigned int RSI11:1; /**< \brief [11:11] Clear RSI Flag of Buffer 11 (w) */
+ unsigned int RSI12:1; /**< \brief [12:12] Clear RSI Flag of Buffer 12 (w) */
+ unsigned int RSI13:1; /**< \brief [13:13] Clear RSI Flag of Buffer 13 (w) */
+ unsigned int RSI14:1; /**< \brief [14:14] Clear RSI Flag of Buffer 14 (w) */
+ unsigned int RSI15:1; /**< \brief [15:15] Clear RSI Flag of Buffer 15 (w) */
+ unsigned int RSI16:1; /**< \brief [16:16] Clear RSI Flag of Buffer 16 (w) */
+ unsigned int RSI17:1; /**< \brief [17:17] Clear RSI Flag of Buffer 17 (w) */
+ unsigned int RSI18:1; /**< \brief [18:18] Clear RSI Flag of Buffer 18 (w) */
+ unsigned int RSI19:1; /**< \brief [19:19] Clear RSI Flag of Buffer 19 (w) */
+ unsigned int RSI20:1; /**< \brief [20:20] Clear RSI Flag of Buffer 20 (w) */
+ unsigned int RSI21:1; /**< \brief [21:21] Clear RSI Flag of Buffer 21 (w) */
+ unsigned int RSI22:1; /**< \brief [22:22] Clear RSI Flag of Buffer 22 (w) */
+ unsigned int RSI23:1; /**< \brief [23:23] Clear RSI Flag of Buffer 23 (w) */
+ unsigned int RSI24:1; /**< \brief [24:24] Clear RSI Flag of Buffer 24 (w) */
+ unsigned int RSI25:1; /**< \brief [25:25] Clear RSI Flag of Buffer 25 (w) */
+ unsigned int RSI26:1; /**< \brief [26:26] Clear RSI Flag of Buffer 26 (w) */
+ unsigned int RSI27:1; /**< \brief [27:27] Clear RSI Flag of Buffer 27 (w) */
+ unsigned int RSI28:1; /**< \brief [28:28] Clear RSI Flag of Buffer 28 (w) */
+ unsigned int RSI29:1; /**< \brief [29:29] Clear RSI Flag of Buffer 29 (w) */
+ unsigned int RSI30:1; /**< \brief [30:30] Clear RSI Flag of Buffer 30 (w) */
+ unsigned int RSI31:1; /**< \brief [31:31] Clear RSI Flag of Buffer 31 (w) */
+} Ifx_PSI5_RSICLR_Bits;
+
+/** \brief RSI Overview Register */
+typedef struct _Ifx_PSI5_RSIOV_Bits
+{
+ unsigned int RSI0:1; /**< \brief [0:0] RSI Flag of Buffer 0 (rh) */
+ unsigned int RSI1:1; /**< \brief [1:1] RSI Flag of Buffer 1 (rh) */
+ unsigned int RSI2:1; /**< \brief [2:2] RSI Flag of Buffer 2 (rh) */
+ unsigned int RSI3:1; /**< \brief [3:3] RSI Flag of Buffer 3 (rh) */
+ unsigned int RSI4:1; /**< \brief [4:4] RSI Flag of Buffer 4 (rh) */
+ unsigned int RSI5:1; /**< \brief [5:5] RSI Flag of Buffer 5 (rh) */
+ unsigned int RSI6:1; /**< \brief [6:6] RSI Flag of Buffer 6 (rh) */
+ unsigned int RSI7:1; /**< \brief [7:7] RSI Flag of Buffer 7 (rh) */
+ unsigned int RSI8:1; /**< \brief [8:8] RSI Flag of Buffer 8 (rh) */
+ unsigned int RSI9:1; /**< \brief [9:9] RSI Flag of Buffer 9 (rh) */
+ unsigned int RSI10:1; /**< \brief [10:10] RSI Flag of Buffer 10 (rh) */
+ unsigned int RSI11:1; /**< \brief [11:11] RSI Flag of Buffer 11 (rh) */
+ unsigned int RSI12:1; /**< \brief [12:12] RSI Flag of Buffer 12 (rh) */
+ unsigned int RSI13:1; /**< \brief [13:13] RSI Flag of Buffer 13 (rh) */
+ unsigned int RSI14:1; /**< \brief [14:14] RSI Flag of Buffer 14 (rh) */
+ unsigned int RSI15:1; /**< \brief [15:15] RSI Flag of Buffer 15 (rh) */
+ unsigned int RSI16:1; /**< \brief [16:16] RSI Flag of Buffer 16 (rh) */
+ unsigned int RSI17:1; /**< \brief [17:17] RSI Flag of Buffer 17 (rh) */
+ unsigned int RSI18:1; /**< \brief [18:18] RSI Flag of Buffer 18 (rh) */
+ unsigned int RSI19:1; /**< \brief [19:19] RSI Flag of Buffer 19 (rh) */
+ unsigned int RSI20:1; /**< \brief [20:20] RSI Flag of Buffer 20 (rh) */
+ unsigned int RSI21:1; /**< \brief [21:21] RSI Flag of Buffer 21 (rh) */
+ unsigned int RSI22:1; /**< \brief [22:22] RSI Flag of Buffer 22 (rh) */
+ unsigned int RSI23:1; /**< \brief [23:23] RSI Flag of Buffer 23 (rh) */
+ unsigned int RSI24:1; /**< \brief [24:24] RSI Flag of Buffer 24 (rh) */
+ unsigned int RSI25:1; /**< \brief [25:25] RSI Flag of Buffer 25 (rh) */
+ unsigned int RSI26:1; /**< \brief [26:26] RSI Flag of Buffer 26 (rh) */
+ unsigned int RSI27:1; /**< \brief [27:27] RSI Flag of Buffer 27 (rh) */
+ unsigned int RSI28:1; /**< \brief [28:28] RSI Flag of Buffer 28 (rh) */
+ unsigned int RSI29:1; /**< \brief [29:29] RSI Flag of Buffer 29 (rh) */
+ unsigned int RSI30:1; /**< \brief [30:30] RSI Flag of Buffer 30 (rh) */
+ unsigned int RSI31:1; /**< \brief [31:31] RSI Flag of Buffer 31 (rh) */
+} Ifx_PSI5_RSIOV_Bits;
+
+/** \brief RSIOV Set Register */
+typedef struct _Ifx_PSI5_RSISET_Bits
+{
+ unsigned int RSI0:1; /**< \brief [0:0] Set RSI Flag of Buffer 0 (w) */
+ unsigned int RSI1:1; /**< \brief [1:1] Set RSI Flag of Buffer 1 (w) */
+ unsigned int RSI2:1; /**< \brief [2:2] Set RSI Flag of Buffer 2 (w) */
+ unsigned int RSI3:1; /**< \brief [3:3] Set RSI Flag of Buffer 3 (w) */
+ unsigned int RSI4:1; /**< \brief [4:4] Set RSI Flag of Buffer 4 (w) */
+ unsigned int RSI5:1; /**< \brief [5:5] Set RSI Flag of Buffer 5 (w) */
+ unsigned int RSI6:1; /**< \brief [6:6] Set RSI Flag of Buffer 6 (w) */
+ unsigned int RSI7:1; /**< \brief [7:7] Set RSI Flag of Buffer 7 (w) */
+ unsigned int RSI8:1; /**< \brief [8:8] Set RSI Flag of Buffer 8 (w) */
+ unsigned int RSI9:1; /**< \brief [9:9] Set RSI Flag of Buffer 9 (w) */
+ unsigned int RSI10:1; /**< \brief [10:10] Set RSI Flag of Buffer 10 (w) */
+ unsigned int RSI11:1; /**< \brief [11:11] Set RSI Flag of Buffer 11 (w) */
+ unsigned int RSI12:1; /**< \brief [12:12] Set RSI Flag of Buffer 12 (w) */
+ unsigned int RSI13:1; /**< \brief [13:13] Set RSI Flag of Buffer 13 (w) */
+ unsigned int RSI14:1; /**< \brief [14:14] Set RSI Flag of Buffer 14 (w) */
+ unsigned int RSI15:1; /**< \brief [15:15] Set RSI Flag of Buffer 15 (w) */
+ unsigned int RSI16:1; /**< \brief [16:16] Set RSI Flag of Buffer 16 (w) */
+ unsigned int RSI17:1; /**< \brief [17:17] Set RSI Flag of Buffer 17 (w) */
+ unsigned int RSI18:1; /**< \brief [18:18] Set RSI Flag of Buffer 18 (w) */
+ unsigned int RSI19:1; /**< \brief [19:19] Set RSI Flag of Buffer 19 (w) */
+ unsigned int RSI20:1; /**< \brief [20:20] Set RSI Flag of Buffer 20 (w) */
+ unsigned int RSI21:1; /**< \brief [21:21] Set RSI Flag of Buffer 21 (w) */
+ unsigned int RSI22:1; /**< \brief [22:22] Set RSI Flag of Buffer 22 (w) */
+ unsigned int RSI23:1; /**< \brief [23:23] Set RSI Flag of Buffer 23 (w) */
+ unsigned int RSI24:1; /**< \brief [24:24] Set RSI Flag of Buffer 24 (w) */
+ unsigned int RSI25:1; /**< \brief [25:25] Set RSI Flag of Buffer 25 (w) */
+ unsigned int RSI26:1; /**< \brief [26:26] Set RSI Flag of Buffer 26 (w) */
+ unsigned int RSI27:1; /**< \brief [27:27] Set RSI Flag of Buffer 27 (w) */
+ unsigned int RSI28:1; /**< \brief [28:28] Set RSI Flag of Buffer 28 (w) */
+ unsigned int RSI29:1; /**< \brief [29:29] Set RSI Flag of Buffer 29 (w) */
+ unsigned int RSI30:1; /**< \brief [30:30] Set RSI Flag of Buffer 30 (w) */
+ unsigned int RSI31:1; /**< \brief [31:31] Set RSI Flag of Buffer 31 (w) */
+} Ifx_PSI5_RSISET_Bits;
+
+/** \brief TEIOV Clear Register */
+typedef struct _Ifx_PSI5_TEICLR_Bits
+{
+ unsigned int TEI0:1; /**< \brief [0:0] Clear TEI Flag of Buffer 0 (w) */
+ unsigned int TEI1:1; /**< \brief [1:1] Clear TEI Flag of Buffer 1 (w) */
+ unsigned int TEI2:1; /**< \brief [2:2] Clear TEI Flag of Buffer 2 (w) */
+ unsigned int TEI3:1; /**< \brief [3:3] Clear TEI Flag of Buffer 3 (w) */
+ unsigned int TEI4:1; /**< \brief [4:4] Clear TEI Flag of Buffer 4 (w) */
+ unsigned int TEI5:1; /**< \brief [5:5] Clear TEI Flag of Buffer 5 (w) */
+ unsigned int TEI6:1; /**< \brief [6:6] Clear TEI Flag of Buffer 6 (w) */
+ unsigned int TEI7:1; /**< \brief [7:7] Clear TEI Flag of Buffer 7 (w) */
+ unsigned int TEI8:1; /**< \brief [8:8] Clear TEI Flag of Buffer 8 (w) */
+ unsigned int TEI9:1; /**< \brief [9:9] Clear TEI Flag of Buffer 9 (w) */
+ unsigned int TEI10:1; /**< \brief [10:10] Clear TEI Flag of Buffer 10 (w) */
+ unsigned int TEI11:1; /**< \brief [11:11] Clear TEI Flag of Buffer 11 (w) */
+ unsigned int TEI12:1; /**< \brief [12:12] Clear TEI Flag of Buffer 12 (w) */
+ unsigned int TEI13:1; /**< \brief [13:13] Clear TEI Flag of Buffer 13 (w) */
+ unsigned int TEI14:1; /**< \brief [14:14] Clear TEI Flag of Buffer 14 (w) */
+ unsigned int TEI15:1; /**< \brief [15:15] Clear TEI Flag of Buffer 15 (w) */
+ unsigned int TEI16:1; /**< \brief [16:16] Clear TEI Flag of Buffer 16 (w) */
+ unsigned int TEI17:1; /**< \brief [17:17] Clear TEI Flag of Buffer 17 (w) */
+ unsigned int TEI18:1; /**< \brief [18:18] Clear TEI Flag of Buffer 18 (w) */
+ unsigned int TEI19:1; /**< \brief [19:19] Clear TEI Flag of Buffer 19 (w) */
+ unsigned int TEI20:1; /**< \brief [20:20] Clear TEI Flag of Buffer 20 (w) */
+ unsigned int TEI21:1; /**< \brief [21:21] Clear TEI Flag of Buffer 21 (w) */
+ unsigned int TEI22:1; /**< \brief [22:22] Clear TEI Flag of Buffer 22 (w) */
+ unsigned int TEI23:1; /**< \brief [23:23] Clear TEI Flag of Buffer 23 (w) */
+ unsigned int TEI24:1; /**< \brief [24:24] Clear TEI Flag of Buffer 24 (w) */
+ unsigned int TEI25:1; /**< \brief [25:25] Clear TEI Flag of Buffer 25 (w) */
+ unsigned int TEI26:1; /**< \brief [26:26] Clear TEI Flag of Buffer 26 (w) */
+ unsigned int TEI27:1; /**< \brief [27:27] Clear TEI Flag of Buffer 27 (w) */
+ unsigned int TEI28:1; /**< \brief [28:28] Clear TEI Flag of Buffer 28 (w) */
+ unsigned int TEI29:1; /**< \brief [29:29] Clear TEI Flag of Buffer 29 (w) */
+ unsigned int TEI30:1; /**< \brief [30:30] Clear TEI Flag of Buffer 30 (w) */
+ unsigned int TEI31:1; /**< \brief [31:31] Clear TEI Flag of Buffer 31 (w) */
+} Ifx_PSI5_TEICLR_Bits;
+
+/** \brief TEI Overview Register */
+typedef struct _Ifx_PSI5_TEIOV_Bits
+{
+ unsigned int TEI0:1; /**< \brief [0:0] TEI Flag of Buffer 0 (rh) */
+ unsigned int TEI1:1; /**< \brief [1:1] TEI Flag of Buffer 1 (rh) */
+ unsigned int TEI2:1; /**< \brief [2:2] TEI Flag of Buffer 2 (rh) */
+ unsigned int TEI3:1; /**< \brief [3:3] TEI Flag of Buffer 3 (rh) */
+ unsigned int TEI4:1; /**< \brief [4:4] TEI Flag of Buffer 4 (rh) */
+ unsigned int TEI5:1; /**< \brief [5:5] TEI Flag of Buffer 5 (rh) */
+ unsigned int TEI6:1; /**< \brief [6:6] TEI Flag of Buffer 6 (rh) */
+ unsigned int TEI7:1; /**< \brief [7:7] TEI Flag of Buffer 7 (rh) */
+ unsigned int TEI8:1; /**< \brief [8:8] TEI Flag of Buffer 8 (rh) */
+ unsigned int TEI9:1; /**< \brief [9:9] TEI Flag of Buffer 9 (rh) */
+ unsigned int TEI10:1; /**< \brief [10:10] TEI Flag of Buffer 10 (rh) */
+ unsigned int TEI11:1; /**< \brief [11:11] TEI Flag of Buffer 11 (rh) */
+ unsigned int TEI12:1; /**< \brief [12:12] TEI Flag of Buffer 12 (rh) */
+ unsigned int TEI13:1; /**< \brief [13:13] TEI Flag of Buffer 13 (rh) */
+ unsigned int TEI14:1; /**< \brief [14:14] TEI Flag of Buffer 14 (rh) */
+ unsigned int TEI15:1; /**< \brief [15:15] TEI Flag of Buffer 15 (rh) */
+ unsigned int TEI16:1; /**< \brief [16:16] TEI Flag of Buffer 16 (rh) */
+ unsigned int TEI17:1; /**< \brief [17:17] TEI Flag of Buffer 17 (rh) */
+ unsigned int TEI18:1; /**< \brief [18:18] TEI Flag of Buffer 18 (rh) */
+ unsigned int TEI19:1; /**< \brief [19:19] TEI Flag of Buffer 19 (rh) */
+ unsigned int TEI20:1; /**< \brief [20:20] TEI Flag of Buffer 20 (rh) */
+ unsigned int TEI21:1; /**< \brief [21:21] TEI Flag of Buffer 21 (rh) */
+ unsigned int TEI22:1; /**< \brief [22:22] TEI Flag of Buffer 22 (rh) */
+ unsigned int TEI23:1; /**< \brief [23:23] TEI Flag of Buffer 23 (rh) */
+ unsigned int TEI24:1; /**< \brief [24:24] TEI Flag of Buffer 24 (rh) */
+ unsigned int TEI25:1; /**< \brief [25:25] TEI Flag of Buffer 25 (rh) */
+ unsigned int TEI26:1; /**< \brief [26:26] TEI Flag of Buffer 26 (rh) */
+ unsigned int TEI27:1; /**< \brief [27:27] TEI Flag of Buffer 27 (rh) */
+ unsigned int TEI28:1; /**< \brief [28:28] TEI Flag of Buffer 28 (rh) */
+ unsigned int TEI29:1; /**< \brief [29:29] TEI Flag of Buffer 29 (rh) */
+ unsigned int TEI30:1; /**< \brief [30:30] TEI Flag of Buffer 30 (rh) */
+ unsigned int TEI31:1; /**< \brief [31:31] TEI Flag of Buffer 31 (rh) */
+} Ifx_PSI5_TEIOV_Bits;
+
+/** \brief TEIOV Set Register */
+typedef struct _Ifx_PSI5_TEISET_Bits
+{
+ unsigned int TEI0:1; /**< \brief [0:0] Set TEI Flag of Buffer 0 (w) */
+ unsigned int TEI1:1; /**< \brief [1:1] Set TEI Flag of Buffer 1 (w) */
+ unsigned int TEI2:1; /**< \brief [2:2] Set TEI Flag of Buffer 2 (w) */
+ unsigned int TEI3:1; /**< \brief [3:3] Set TEI Flag of Buffer 3 (w) */
+ unsigned int TEI4:1; /**< \brief [4:4] Set TEI Flag of Buffer 4 (w) */
+ unsigned int TEI5:1; /**< \brief [5:5] Set TEI Flag of Buffer 5 (w) */
+ unsigned int TEI6:1; /**< \brief [6:6] Set TEI Flag of Buffer 6 (w) */
+ unsigned int TEI7:1; /**< \brief [7:7] Set TEI Flag of Buffer 7 (w) */
+ unsigned int TEI8:1; /**< \brief [8:8] Set TEI Flag of Buffer 8 (w) */
+ unsigned int TEI9:1; /**< \brief [9:9] Set TEI Flag of Buffer 9 (w) */
+ unsigned int TEI10:1; /**< \brief [10:10] Set TEI Flag of Buffer 10 (w) */
+ unsigned int TEI11:1; /**< \brief [11:11] Set TEI Flag of Buffer 11 (w) */
+ unsigned int TEI12:1; /**< \brief [12:12] Set TEI Flag of Buffer 12 (w) */
+ unsigned int TEI13:1; /**< \brief [13:13] Set TEI Flag of Buffer 13 (w) */
+ unsigned int TEI14:1; /**< \brief [14:14] Set TEI Flag of Buffer 14 (w) */
+ unsigned int TEI15:1; /**< \brief [15:15] Set TEI Flag of Buffer 15 (w) */
+ unsigned int TEI16:1; /**< \brief [16:16] Set TEI Flag of Buffer 16 (w) */
+ unsigned int TEI17:1; /**< \brief [17:17] Set TEI Flag of Buffer 17 (w) */
+ unsigned int TEI18:1; /**< \brief [18:18] Set TEI Flag of Buffer 18 (w) */
+ unsigned int TEI19:1; /**< \brief [19:19] Set TEI Flag of Buffer 19 (w) */
+ unsigned int TEI20:1; /**< \brief [20:20] Set TEI Flag of Buffer 20 (w) */
+ unsigned int TEI21:1; /**< \brief [21:21] Set TEI Flag of Buffer 21 (w) */
+ unsigned int TEI22:1; /**< \brief [22:22] Set TEI Flag of Buffer 22 (w) */
+ unsigned int TEI23:1; /**< \brief [23:23] Set TEI Flag of Buffer 23 (w) */
+ unsigned int TEI24:1; /**< \brief [24:24] Set TEI Flag of Buffer 24 (w) */
+ unsigned int TEI25:1; /**< \brief [25:25] Set TEI Flag of Buffer 25 (w) */
+ unsigned int TEI26:1; /**< \brief [26:26] Set TEI Flag of Buffer 26 (w) */
+ unsigned int TEI27:1; /**< \brief [27:27] Set TEI Flag of Buffer 27 (w) */
+ unsigned int TEI28:1; /**< \brief [28:28] Set TEI Flag of Buffer 28 (w) */
+ unsigned int TEI29:1; /**< \brief [29:29] Set TEI Flag of Buffer 29 (w) */
+ unsigned int TEI30:1; /**< \brief [30:30] Set TEI Flag of Buffer 30 (w) */
+ unsigned int TEI31:1; /**< \brief [31:31] Set TEI Flag of Buffer 31 (w) */
+} Ifx_PSI5_TEISET_Bits;
+
+/** \brief Time Stamp Register */
+typedef struct _Ifx_PSI5_TSR_Bits
+{
+ unsigned int CTS:24; /**< \brief [23:0] Current Time Stamp for the Module (r) */
+ unsigned int ETB:3; /**< \brief [26:24] External Time Base Select (rw) */
+ unsigned int TBS:1; /**< \brief [27:27] Time Base Select (rw) */
+ unsigned int reserved_28:2; /**< \brief \internal Reserved */
+ unsigned int ACLR:1; /**< \brief [30:30] Clear All Current Time Stamp Counters (w) */
+ unsigned int CLR:1; /**< \brief [31:31] Clear Current Time Stamp for the Module (w) */
+} Ifx_PSI5_TSR_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Psi5_union
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_ACCEN0_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_ACCEN0;
+
+/** \brief Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_ACCEN1_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_ACCEN1;
+
+/** \brief Channel Trigger Value Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_CH_CTV_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_CH_CTV;
+
+/** \brief Input and Output Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_CH_IOCR_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_CH_IOCR;
+
+/** \brief Pulse Generation Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_CH_PGC_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_CH_PGC;
+
+/** \brief Receiver Control Register A */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_CH_RCRA_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_CH_RCRA;
+
+/** \brief Receiver Control Register B */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_CH_RCRB_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_CH_RCRB;
+
+/** \brief Receiver Control Register C */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_CH_RCRC_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_CH_RCRC;
+
+/** \brief Receive Data Register High */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_CH_RDRH_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_CH_RDRH;
+
+/** \brief Receive Data Register Low */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_CH_RDRL_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_CH_RDRL;
+
+/** \brief Receive Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_CH_RSR_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_CH_RSR;
+
+/** \brief Send Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_CH_SCR_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_CH_SCR;
+
+/** \brief Send Data Register High */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_CH_SDRH_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_CH_SDRH;
+
+/** \brief Send Data Register Low */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_CH_SDRL_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_CH_SDRL;
+
+/** \brief Serial Data and Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_CH_SDS_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_CH_SDS;
+
+/** \brief SOF TS Capture Register SFTSC */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_CH_SFTSC_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_CH_SFTSC;
+
+/** \brief Send Output Register High */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_CH_SORH_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_CH_SORH;
+
+/** \brief Send Output Register Low */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_CH_SORL_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_CH_SORL;
+
+/** \brief SOP TS Capture Register SPTSC */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_CH_SPTSC_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_CH_SPTSC;
+
+/** \brief Send Shift Register High */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_CH_SSRH_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_CH_SSRH;
+
+/** \brief Send Shift Register Low */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_CH_SSRL_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_CH_SSRL;
+
+/** \brief Watch Dog Timer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_CH_WDT_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_CH_WDT;
+
+/** \brief Clock Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_CLC_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_CLC;
+
+/** \brief CRCIOV Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_CRCICLR_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_CRCICLR;
+
+/** \brief CRCI Overview Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_CRCIOV_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_CRCIOV;
+
+/** \brief CRCIOV Set Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_CRCISET_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_CRCISET;
+
+/** \brief PSI5 Fractional Divider Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_FDR_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_FDR;
+
+/** \brief Fractional Divider Register for Higher Bit Rate */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_FDRH_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_FDRH;
+
+/** \brief Fractional Divider Register for Lower Bit Rate */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_FDRL_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_FDRL;
+
+/** \brief Fractional Divider Register for Time Stamp */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_FDRT_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_FDRT;
+
+/** \brief Global Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_GCR_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_GCR;
+
+/** \brief Module Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_ID;
+
+/** \brief Interrupt Node Pointer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_INP_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_INP;
+
+/** \brief Interrupt Clear Register A */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_INTCLRA_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_INTCLRA;
+
+/** \brief Interrupt Clear Register A */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_INTCLRB_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_INTCLRB;
+
+/** \brief Interrupt Enable Register A */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_INTENA_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_INTENA;
+
+/** \brief Interrupt Enable Register B */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_INTENB_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_INTENB;
+
+/** \brief Interrupt Overview Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_INTOV_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_INTOV;
+
+/** \brief Interrupt Set Register A */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_INTSETA_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_INTSETA;
+
+/** \brief Interrupt Set Register B */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_INTSETB_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_INTSETB;
+
+/** \brief Interrupt Status Register A */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_INTSTATA_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_INTSTATA;
+
+/** \brief Interrupt Status Register B */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_INTSTATB_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_INTSTATB;
+
+/** \brief Kernel Reset Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_KRST0_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_KRST0;
+
+/** \brief Kernel Reset Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_KRST1_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_KRST1;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_KRSTCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_KRSTCLR;
+
+/** \brief MEIOV Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_MEICLR_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_MEICLR;
+
+/** \brief MEI Overview Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_MEIOV_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_MEIOV;
+
+/** \brief MEIOV Set Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_MEISET_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_MEISET;
+
+/** \brief NBIOV Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_NBICLR_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_NBICLR;
+
+/** \brief NBI Overview Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_NBIOV_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_NBIOV;
+
+/** \brief NBIOV Set Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_NBISET_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_NBISET;
+
+/** \brief NFIOV Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_NFICLR_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_NFICLR;
+
+/** \brief NFI Overview Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_NFIOV_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_NFIOV;
+
+/** \brief NFIOV Set Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_NFISET_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_NFISET;
+
+/** \brief OCDS Control and Status */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_OCS_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_OCS;
+
+/** \brief Receive Data FIFO */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_RDF_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_RDF;
+
+/** \brief RDIOV Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_RDICLR_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_RDICLR;
+
+/** \brief RDI Overview Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_RDIOV_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_RDIOV;
+
+/** \brief RDIOV Set Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_RDISET_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_RDISET;
+
+/** \brief Receive Data Memory High */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_RDM_H_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_RDM_H;
+
+/** \brief Receive Data Memory Low */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_RDM_L_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_RDM_L;
+
+/** \brief Receive FIFO Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_RFC_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_RFC;
+
+/** \brief RMIOV Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_RMICLR_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_RMICLR;
+
+/** \brief RMI Overview Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_RMIOV_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_RMIOV;
+
+/** \brief RMIOV Set Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_RMISET_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_RMISET;
+
+/** \brief RSIOV Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_RSICLR_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_RSICLR;
+
+/** \brief RSI Overview Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_RSIOV_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_RSIOV;
+
+/** \brief RSIOV Set Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_RSISET_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_RSISET;
+
+/** \brief TEIOV Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_TEICLR_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_TEICLR;
+
+/** \brief TEI Overview Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_TEIOV_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_TEIOV;
+
+/** \brief TEIOV Set Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_TEISET_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_TEISET;
+
+/** \brief Time Stamp Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5_TSR_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5_TSR;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Psi5_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L1
+ * \{ */
+
+/** \brief Protection range */
+typedef volatile struct _Ifx_PSI5_CH
+{
+ Ifx_PSI5_CH_IOCR IOCR; /**< \brief 0, Input and Output Control Register */
+ Ifx_PSI5_CH_RCRA RCRA; /**< \brief 4, Receiver Control Register A */
+ Ifx_PSI5_CH_RCRB RCRB; /**< \brief 8, Receiver Control Register B */
+ Ifx_PSI5_CH_RCRC RCRC; /**< \brief C, Receiver Control Register C */
+ Ifx_PSI5_CH_WDT WDT[7]; /**< \brief 10, Watch Dog Timer Register */
+ Ifx_PSI5_CH_RSR RSR; /**< \brief 2C, Receive Status Register */
+ Ifx_PSI5_CH_SDS SDS[6]; /**< \brief 30, Serial Data and Status Register */
+ Ifx_PSI5_CH_SPTSC SPTSC; /**< \brief 48, SOP TS Capture Register SPTSC */
+ Ifx_PSI5_CH_SFTSC SFTSC; /**< \brief 4C, SOF TS Capture Register SFTSC */
+ Ifx_PSI5_CH_RDRL RDRL; /**< \brief 50, Receive Data Register Low */
+ Ifx_PSI5_CH_RDRH RDRH; /**< \brief 54, Receive Data Register High */
+ Ifx_PSI5_CH_PGC PGC; /**< \brief 58, Pulse Generation Control Register */
+ Ifx_PSI5_CH_CTV CTV; /**< \brief 5C, Channel Trigger Value Register */
+ Ifx_PSI5_CH_SCR SCR; /**< \brief 60, Send Control Register */
+ Ifx_PSI5_CH_SDRL SDRL; /**< \brief 64, Send Data Register Low */
+ Ifx_PSI5_CH_SDRH SDRH; /**< \brief 68, Send Data Register High */
+ Ifx_PSI5_CH_SSRL SSRL; /**< \brief 6C, Send Shift Register Low */
+ Ifx_PSI5_CH_SSRH SSRH; /**< \brief 70, Send Shift Register High */
+ Ifx_PSI5_CH_SORL SORL; /**< \brief 74, Send Output Register Low */
+ Ifx_PSI5_CH_SORH SORH; /**< \brief 78, Send Output Register High */
+ unsigned char reserved_7C[20]; /**< \brief 7C, \internal Reserved */
+} Ifx_PSI5_CH;
+
+/** \brief Receive data memory */
+typedef volatile struct _Ifx_PSI5_RDM
+{
+ Ifx_PSI5_RDM_L L; /**< \brief 0, Receive Data Memory Low */
+ Ifx_PSI5_RDM_H H; /**< \brief 4, Receive Data Memory High */
+} Ifx_PSI5_RDM;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Psi5_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief PSI5 object */
+typedef volatile struct _Ifx_PSI5
+{
+ Ifx_PSI5_CLC CLC; /**< \brief 0, Clock Control Register */
+ unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
+ Ifx_PSI5_ID ID; /**< \brief 8, Module Identification Register */
+ Ifx_PSI5_FDR FDR; /**< \brief C, PSI5 Fractional Divider Register */
+ Ifx_PSI5_FDRL FDRL; /**< \brief 10, Fractional Divider Register for Lower Bit Rate */
+ Ifx_PSI5_FDRH FDRH; /**< \brief 14, Fractional Divider Register for Higher Bit Rate */
+ Ifx_PSI5_FDRT FDRT; /**< \brief 18, Fractional Divider Register for Time Stamp */
+ Ifx_PSI5_TSR TSRA; /**< \brief 1C, Time Stamp Register A */
+ Ifx_PSI5_TSR TSRB; /**< \brief 20, Time Stamp Register B */
+ Ifx_PSI5_TSR TSRC; /**< \brief 24, Time Stamp Register C */
+ unsigned char reserved_28[4]; /**< \brief 28, \internal Reserved */
+ Ifx_PSI5_GCR GCR; /**< \brief 2C, Global Control Register */
+ Ifx_PSI5_CH CH[2]; /**< \brief 30, Protection range */
+ unsigned char reserved_150[424]; /**< \brief 150, \internal Reserved */
+ Ifx_PSI5_INTOV INTOV; /**< \brief 2F8, Interrupt Overview Register */
+ Ifx_PSI5_INP INP[2]; /**< \brief 2FC, Interrupt Node Pointer Register */
+ unsigned char reserved_304[12]; /**< \brief 304, \internal Reserved */
+ Ifx_PSI5_INTSTATA INTSTATA[2]; /**< \brief 310, Interrupt Status Register A */
+ unsigned char reserved_318[12]; /**< \brief 318, \internal Reserved */
+ Ifx_PSI5_INTSTATB INTSTATB[2]; /**< \brief 324, Interrupt Status Register B */
+ unsigned char reserved_32C[12]; /**< \brief 32C, \internal Reserved */
+ Ifx_PSI5_INTSETA INTSETA[2]; /**< \brief 338, Interrupt Set Register A */
+ unsigned char reserved_340[12]; /**< \brief 340, \internal Reserved */
+ Ifx_PSI5_INTSETB INTSETB[2]; /**< \brief 34C, Interrupt Set Register B */
+ unsigned char reserved_354[12]; /**< \brief 354, \internal Reserved */
+ Ifx_PSI5_INTCLRA INTCLRA[2]; /**< \brief 360, Interrupt Clear Register A */
+ unsigned char reserved_368[12]; /**< \brief 368, \internal Reserved */
+ Ifx_PSI5_INTCLRB INTCLRB[2]; /**< \brief 374, Interrupt Clear Register A */
+ unsigned char reserved_37C[12]; /**< \brief 37C, \internal Reserved */
+ Ifx_PSI5_INTENA INTENA[2]; /**< \brief 388, Interrupt Enable Register A */
+ unsigned char reserved_390[12]; /**< \brief 390, \internal Reserved */
+ Ifx_PSI5_INTENB INTENB[2]; /**< \brief 39C, Interrupt Enable Register B */
+ unsigned char reserved_3A4[40]; /**< \brief 3A4, \internal Reserved */
+ Ifx_PSI5_OCS OCS; /**< \brief 3CC, OCDS Control and Status */
+ Ifx_PSI5_ACCEN0 ACCEN0; /**< \brief 3D0, Access Enable Register 0 */
+ Ifx_PSI5_ACCEN1 ACCEN1; /**< \brief 3D4, Access Enable Register 1 */
+ Ifx_PSI5_KRST0 KRST0; /**< \brief 3D8, Kernel Reset Register 0 */
+ Ifx_PSI5_KRST1 KRST1; /**< \brief 3DC, Kernel Reset Register 1 */
+ Ifx_PSI5_KRSTCLR KRSTCLR; /**< \brief 3E0, Kernel Reset Status Clear Register */
+ Ifx_PSI5_RFC RFC[2]; /**< \brief 3E4, Receive FIFO Control Register */
+ unsigned char reserved_3EC[12]; /**< \brief 3EC, \internal Reserved */
+ Ifx_PSI5_RDF RDF[2]; /**< \brief 3F8, Receive Data FIFO */
+ unsigned char reserved_400[12]; /**< \brief 400, \internal Reserved */
+ Ifx_PSI5_RSIOV RSIOV[2]; /**< \brief 40C, RSI Overview Register */
+ unsigned char reserved_414[12]; /**< \brief 414, \internal Reserved */
+ Ifx_PSI5_RMIOV RMIOV[2]; /**< \brief 420, RMI Overview Register */
+ unsigned char reserved_428[12]; /**< \brief 428, \internal Reserved */
+ Ifx_PSI5_NBIOV NBIOV[2]; /**< \brief 434, NBI Overview Register */
+ unsigned char reserved_43C[12]; /**< \brief 43C, \internal Reserved */
+ Ifx_PSI5_TEIOV TEIOV[2]; /**< \brief 448, TEI Overview Register */
+ unsigned char reserved_450[12]; /**< \brief 450, \internal Reserved */
+ Ifx_PSI5_CRCIOV CRCIOV[2]; /**< \brief 45C, CRCI Overview Register */
+ unsigned char reserved_464[12]; /**< \brief 464, \internal Reserved */
+ Ifx_PSI5_RDIOV RDIOV[2]; /**< \brief 470, RDI Overview Register */
+ unsigned char reserved_478[12]; /**< \brief 478, \internal Reserved */
+ Ifx_PSI5_NFIOV NFIOV[2]; /**< \brief 484, NFI Overview Register */
+ unsigned char reserved_48C[12]; /**< \brief 48C, \internal Reserved */
+ Ifx_PSI5_MEIOV MEIOV[2]; /**< \brief 498, MEI Overview Register */
+ unsigned char reserved_4A0[12]; /**< \brief 4A0, \internal Reserved */
+ Ifx_PSI5_RSISET RSISET[2]; /**< \brief 4AC, RSIOV Set Register */
+ unsigned char reserved_4B4[12]; /**< \brief 4B4, \internal Reserved */
+ Ifx_PSI5_RMISET RMISET[2]; /**< \brief 4C0, RMIOV Set Register */
+ unsigned char reserved_4C8[12]; /**< \brief 4C8, \internal Reserved */
+ Ifx_PSI5_NBISET NBISET[2]; /**< \brief 4D4, NBIOV Set Register */
+ unsigned char reserved_4DC[12]; /**< \brief 4DC, \internal Reserved */
+ Ifx_PSI5_TEISET TEISET[2]; /**< \brief 4E8, TEIOV Set Register */
+ unsigned char reserved_4F0[12]; /**< \brief 4F0, \internal Reserved */
+ Ifx_PSI5_CRCISET CRCISET[2]; /**< \brief 4FC, CRCIOV Set Register */
+ unsigned char reserved_504[12]; /**< \brief 504, \internal Reserved */
+ Ifx_PSI5_RDISET RDISET[2]; /**< \brief 510, RDIOV Set Register */
+ unsigned char reserved_518[12]; /**< \brief 518, \internal Reserved */
+ Ifx_PSI5_NFISET NFISET[2]; /**< \brief 524, NFIOV Set Register */
+ unsigned char reserved_52C[12]; /**< \brief 52C, \internal Reserved */
+ Ifx_PSI5_MEISET MEISET[2]; /**< \brief 538, MEIOV Set Register */
+ unsigned char reserved_540[12]; /**< \brief 540, \internal Reserved */
+ Ifx_PSI5_RSICLR RSICLR[2]; /**< \brief 54C, RSIOV Clear Register */
+ unsigned char reserved_554[12]; /**< \brief 554, \internal Reserved */
+ Ifx_PSI5_RMICLR RMICLR[2]; /**< \brief 560, RMIOV Clear Register */
+ unsigned char reserved_568[12]; /**< \brief 568, \internal Reserved */
+ Ifx_PSI5_NBICLR NBICLR[2]; /**< \brief 574, NBIOV Clear Register */
+ unsigned char reserved_57C[12]; /**< \brief 57C, \internal Reserved */
+ Ifx_PSI5_TEICLR TEICLR[2]; /**< \brief 588, TEIOV Clear Register */
+ unsigned char reserved_590[12]; /**< \brief 590, \internal Reserved */
+ Ifx_PSI5_CRCICLR CRCICLR[2]; /**< \brief 59C, CRCIOV Clear Register */
+ unsigned char reserved_5A4[12]; /**< \brief 5A4, \internal Reserved */
+ Ifx_PSI5_RDICLR RDICLR[2]; /**< \brief 5B0, RDIOV Clear Register */
+ unsigned char reserved_5B8[12]; /**< \brief 5B8, \internal Reserved */
+ Ifx_PSI5_NFICLR NFICLR[2]; /**< \brief 5C4, NFIOV Clear Register */
+ unsigned char reserved_5CC[12]; /**< \brief 5CC, \internal Reserved */
+ Ifx_PSI5_MEICLR MEICLR[2]; /**< \brief 5D8, MEIOV Clear Register */
+ unsigned char reserved_5E0[32]; /**< \brief 5E0, \internal Reserved */
+ Ifx_PSI5_RDM RDM[2][32]; /**< \brief 600, Receive data memory */
+ unsigned char reserved_800[768]; /**< \brief 800, \internal Reserved */
+} Ifx_PSI5;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXPSI5_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPsi5s_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPsi5s_bf.h
new file mode 100644
index 0000000..a9dc787
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPsi5s_bf.h
@@ -0,0 +1,3321 @@
+/**
+ * \file IfxPsi5s_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Psi5s_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Psi5s
+ *
+ */
+#ifndef IFXPSI5S_BF_H
+#define IFXPSI5S_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Psi5s_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN0 */
+#define IFX_PSI5S_ACCEN0_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN0 */
+#define IFX_PSI5S_ACCEN0_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN0 */
+#define IFX_PSI5S_ACCEN0_EN0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN10 */
+#define IFX_PSI5S_ACCEN0_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN10 */
+#define IFX_PSI5S_ACCEN0_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN10 */
+#define IFX_PSI5S_ACCEN0_EN10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN11 */
+#define IFX_PSI5S_ACCEN0_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN11 */
+#define IFX_PSI5S_ACCEN0_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN11 */
+#define IFX_PSI5S_ACCEN0_EN11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN12 */
+#define IFX_PSI5S_ACCEN0_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN12 */
+#define IFX_PSI5S_ACCEN0_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN12 */
+#define IFX_PSI5S_ACCEN0_EN12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN13 */
+#define IFX_PSI5S_ACCEN0_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN13 */
+#define IFX_PSI5S_ACCEN0_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN13 */
+#define IFX_PSI5S_ACCEN0_EN13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN14 */
+#define IFX_PSI5S_ACCEN0_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN14 */
+#define IFX_PSI5S_ACCEN0_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN14 */
+#define IFX_PSI5S_ACCEN0_EN14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN15 */
+#define IFX_PSI5S_ACCEN0_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN15 */
+#define IFX_PSI5S_ACCEN0_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN15 */
+#define IFX_PSI5S_ACCEN0_EN15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN16 */
+#define IFX_PSI5S_ACCEN0_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN16 */
+#define IFX_PSI5S_ACCEN0_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN16 */
+#define IFX_PSI5S_ACCEN0_EN16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN17 */
+#define IFX_PSI5S_ACCEN0_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN17 */
+#define IFX_PSI5S_ACCEN0_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN17 */
+#define IFX_PSI5S_ACCEN0_EN17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN18 */
+#define IFX_PSI5S_ACCEN0_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN18 */
+#define IFX_PSI5S_ACCEN0_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN18 */
+#define IFX_PSI5S_ACCEN0_EN18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN19 */
+#define IFX_PSI5S_ACCEN0_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN19 */
+#define IFX_PSI5S_ACCEN0_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN19 */
+#define IFX_PSI5S_ACCEN0_EN19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN1 */
+#define IFX_PSI5S_ACCEN0_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN1 */
+#define IFX_PSI5S_ACCEN0_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN1 */
+#define IFX_PSI5S_ACCEN0_EN1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN20 */
+#define IFX_PSI5S_ACCEN0_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN20 */
+#define IFX_PSI5S_ACCEN0_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN20 */
+#define IFX_PSI5S_ACCEN0_EN20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN21 */
+#define IFX_PSI5S_ACCEN0_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN21 */
+#define IFX_PSI5S_ACCEN0_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN21 */
+#define IFX_PSI5S_ACCEN0_EN21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN22 */
+#define IFX_PSI5S_ACCEN0_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN22 */
+#define IFX_PSI5S_ACCEN0_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN22 */
+#define IFX_PSI5S_ACCEN0_EN22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN23 */
+#define IFX_PSI5S_ACCEN0_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN23 */
+#define IFX_PSI5S_ACCEN0_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN23 */
+#define IFX_PSI5S_ACCEN0_EN23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN24 */
+#define IFX_PSI5S_ACCEN0_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN24 */
+#define IFX_PSI5S_ACCEN0_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN24 */
+#define IFX_PSI5S_ACCEN0_EN24_OFF (24u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN25 */
+#define IFX_PSI5S_ACCEN0_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN25 */
+#define IFX_PSI5S_ACCEN0_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN25 */
+#define IFX_PSI5S_ACCEN0_EN25_OFF (25u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN26 */
+#define IFX_PSI5S_ACCEN0_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN26 */
+#define IFX_PSI5S_ACCEN0_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN26 */
+#define IFX_PSI5S_ACCEN0_EN26_OFF (26u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN27 */
+#define IFX_PSI5S_ACCEN0_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN27 */
+#define IFX_PSI5S_ACCEN0_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN27 */
+#define IFX_PSI5S_ACCEN0_EN27_OFF (27u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN28 */
+#define IFX_PSI5S_ACCEN0_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN28 */
+#define IFX_PSI5S_ACCEN0_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN28 */
+#define IFX_PSI5S_ACCEN0_EN28_OFF (28u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN29 */
+#define IFX_PSI5S_ACCEN0_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN29 */
+#define IFX_PSI5S_ACCEN0_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN29 */
+#define IFX_PSI5S_ACCEN0_EN29_OFF (29u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN2 */
+#define IFX_PSI5S_ACCEN0_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN2 */
+#define IFX_PSI5S_ACCEN0_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN2 */
+#define IFX_PSI5S_ACCEN0_EN2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN30 */
+#define IFX_PSI5S_ACCEN0_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN30 */
+#define IFX_PSI5S_ACCEN0_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN30 */
+#define IFX_PSI5S_ACCEN0_EN30_OFF (30u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN31 */
+#define IFX_PSI5S_ACCEN0_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN31 */
+#define IFX_PSI5S_ACCEN0_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN31 */
+#define IFX_PSI5S_ACCEN0_EN31_OFF (31u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN3 */
+#define IFX_PSI5S_ACCEN0_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN3 */
+#define IFX_PSI5S_ACCEN0_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN3 */
+#define IFX_PSI5S_ACCEN0_EN3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN4 */
+#define IFX_PSI5S_ACCEN0_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN4 */
+#define IFX_PSI5S_ACCEN0_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN4 */
+#define IFX_PSI5S_ACCEN0_EN4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN5 */
+#define IFX_PSI5S_ACCEN0_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN5 */
+#define IFX_PSI5S_ACCEN0_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN5 */
+#define IFX_PSI5S_ACCEN0_EN5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN6 */
+#define IFX_PSI5S_ACCEN0_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN6 */
+#define IFX_PSI5S_ACCEN0_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN6 */
+#define IFX_PSI5S_ACCEN0_EN6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN7 */
+#define IFX_PSI5S_ACCEN0_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN7 */
+#define IFX_PSI5S_ACCEN0_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN7 */
+#define IFX_PSI5S_ACCEN0_EN7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN8 */
+#define IFX_PSI5S_ACCEN0_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN8 */
+#define IFX_PSI5S_ACCEN0_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN8 */
+#define IFX_PSI5S_ACCEN0_EN8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5S_ACCEN0_Bits.EN9 */
+#define IFX_PSI5S_ACCEN0_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_ACCEN0_Bits.EN9 */
+#define IFX_PSI5S_ACCEN0_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_ACCEN0_Bits.EN9 */
+#define IFX_PSI5S_ACCEN0_EN9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5S_BAR_Bits.BA */
+#define IFX_PSI5S_BAR_BA_LEN (30u)
+
+/** \brief Mask for Ifx_PSI5S_BAR_Bits.BA */
+#define IFX_PSI5S_BAR_BA_MSK (0x3fffffffu)
+
+/** \brief Offset for Ifx_PSI5S_BAR_Bits.BA */
+#define IFX_PSI5S_BAR_BA_OFF (2u)
+
+/** \brief Length for Ifx_PSI5S_BG_Bits.BR_VALUE */
+#define IFX_PSI5S_BG_BR_VALUE_LEN (13u)
+
+/** \brief Mask for Ifx_PSI5S_BG_Bits.BR_VALUE */
+#define IFX_PSI5S_BG_BR_VALUE_MSK (0x1fffu)
+
+/** \brief Offset for Ifx_PSI5S_BG_Bits.BR_VALUE */
+#define IFX_PSI5S_BG_BR_VALUE_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_CDW_Bits.SD0 */
+#define IFX_PSI5S_CDW_SD0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_CDW_Bits.SD0 */
+#define IFX_PSI5S_CDW_SD0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_CDW_Bits.SD0 */
+#define IFX_PSI5S_CDW_SD0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_CDW_Bits.SD1 */
+#define IFX_PSI5S_CDW_SD1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_CDW_Bits.SD1 */
+#define IFX_PSI5S_CDW_SD1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_CDW_Bits.SD1 */
+#define IFX_PSI5S_CDW_SD1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5S_CDW_Bits.SD2 */
+#define IFX_PSI5S_CDW_SD2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_CDW_Bits.SD2 */
+#define IFX_PSI5S_CDW_SD2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_CDW_Bits.SD2 */
+#define IFX_PSI5S_CDW_SD2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5S_CDW_Bits.SD3 */
+#define IFX_PSI5S_CDW_SD3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_CDW_Bits.SD3 */
+#define IFX_PSI5S_CDW_SD3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_CDW_Bits.SD3 */
+#define IFX_PSI5S_CDW_SD3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5S_CDW_Bits.SD4 */
+#define IFX_PSI5S_CDW_SD4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_CDW_Bits.SD4 */
+#define IFX_PSI5S_CDW_SD4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_CDW_Bits.SD4 */
+#define IFX_PSI5S_CDW_SD4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5S_CDW_Bits.SD5 */
+#define IFX_PSI5S_CDW_SD5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_CDW_Bits.SD5 */
+#define IFX_PSI5S_CDW_SD5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_CDW_Bits.SD5 */
+#define IFX_PSI5S_CDW_SD5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5S_CDW_Bits.SD6 */
+#define IFX_PSI5S_CDW_SD6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_CDW_Bits.SD6 */
+#define IFX_PSI5S_CDW_SD6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_CDW_Bits.SD6 */
+#define IFX_PSI5S_CDW_SD6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5S_CDW_Bits.SD7 */
+#define IFX_PSI5S_CDW_SD7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_CDW_Bits.SD7 */
+#define IFX_PSI5S_CDW_SD7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_CDW_Bits.SD7 */
+#define IFX_PSI5S_CDW_SD7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5S_CDW_Bits.TSI */
+#define IFX_PSI5S_CDW_TSI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_CDW_Bits.TSI */
+#define IFX_PSI5S_CDW_TSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_CDW_Bits.TSI */
+#define IFX_PSI5S_CDW_TSI_OFF (8u)
+
+/** \brief Length for Ifx_PSI5S_CLC_Bits.DISR */
+#define IFX_PSI5S_CLC_DISR_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_CLC_Bits.DISR */
+#define IFX_PSI5S_CLC_DISR_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_CLC_Bits.DISR */
+#define IFX_PSI5S_CLC_DISR_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_CLC_Bits.DISS */
+#define IFX_PSI5S_CLC_DISS_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_CLC_Bits.DISS */
+#define IFX_PSI5S_CLC_DISS_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_CLC_Bits.DISS */
+#define IFX_PSI5S_CLC_DISS_OFF (1u)
+
+/** \brief Length for Ifx_PSI5S_CLC_Bits.EDIS */
+#define IFX_PSI5S_CLC_EDIS_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_CLC_Bits.EDIS */
+#define IFX_PSI5S_CLC_EDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_CLC_Bits.EDIS */
+#define IFX_PSI5S_CLC_EDIS_OFF (3u)
+
+/** \brief Length for Ifx_PSI5S_CON_Bits.BRS */
+#define IFX_PSI5S_CON_BRS_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_CON_Bits.BRS */
+#define IFX_PSI5S_CON_BRS_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_CON_Bits.BRS */
+#define IFX_PSI5S_CON_BRS_OFF (13u)
+
+/** \brief Length for Ifx_PSI5S_CON_Bits.FDE */
+#define IFX_PSI5S_CON_FDE_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_CON_Bits.FDE */
+#define IFX_PSI5S_CON_FDE_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_CON_Bits.FDE */
+#define IFX_PSI5S_CON_FDE_OFF (11u)
+
+/** \brief Length for Ifx_PSI5S_CON_Bits.FE */
+#define IFX_PSI5S_CON_FE_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_CON_Bits.FE */
+#define IFX_PSI5S_CON_FE_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_CON_Bits.FE */
+#define IFX_PSI5S_CON_FE_OFF (9u)
+
+/** \brief Length for Ifx_PSI5S_CON_Bits.FEN */
+#define IFX_PSI5S_CON_FEN_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_CON_Bits.FEN */
+#define IFX_PSI5S_CON_FEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_CON_Bits.FEN */
+#define IFX_PSI5S_CON_FEN_OFF (6u)
+
+/** \brief Length for Ifx_PSI5S_CON_Bits.LB */
+#define IFX_PSI5S_CON_LB_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_CON_Bits.LB */
+#define IFX_PSI5S_CON_LB_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_CON_Bits.LB */
+#define IFX_PSI5S_CON_LB_OFF (14u)
+
+/** \brief Length for Ifx_PSI5S_CON_Bits.M */
+#define IFX_PSI5S_CON_M_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_CON_Bits.M */
+#define IFX_PSI5S_CON_M_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_CON_Bits.M */
+#define IFX_PSI5S_CON_M_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_CON_Bits.MTX */
+#define IFX_PSI5S_CON_MTX_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_CON_Bits.MTX */
+#define IFX_PSI5S_CON_MTX_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_CON_Bits.MTX */
+#define IFX_PSI5S_CON_MTX_OFF (16u)
+
+/** \brief Length for Ifx_PSI5S_CON_Bits.ODD */
+#define IFX_PSI5S_CON_ODD_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_CON_Bits.ODD */
+#define IFX_PSI5S_CON_ODD_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_CON_Bits.ODD */
+#define IFX_PSI5S_CON_ODD_OFF (12u)
+
+/** \brief Length for Ifx_PSI5S_CON_Bits.ODDTX */
+#define IFX_PSI5S_CON_ODDTX_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_CON_Bits.ODDTX */
+#define IFX_PSI5S_CON_ODDTX_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_CON_Bits.ODDTX */
+#define IFX_PSI5S_CON_ODDTX_OFF (28u)
+
+/** \brief Length for Ifx_PSI5S_CON_Bits.OE */
+#define IFX_PSI5S_CON_OE_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_CON_Bits.OE */
+#define IFX_PSI5S_CON_OE_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_CON_Bits.OE */
+#define IFX_PSI5S_CON_OE_OFF (10u)
+
+/** \brief Length for Ifx_PSI5S_CON_Bits.OEN */
+#define IFX_PSI5S_CON_OEN_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_CON_Bits.OEN */
+#define IFX_PSI5S_CON_OEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_CON_Bits.OEN */
+#define IFX_PSI5S_CON_OEN_OFF (7u)
+
+/** \brief Length for Ifx_PSI5S_CON_Bits.PE */
+#define IFX_PSI5S_CON_PE_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_CON_Bits.PE */
+#define IFX_PSI5S_CON_PE_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_CON_Bits.PE */
+#define IFX_PSI5S_CON_PE_OFF (8u)
+
+/** \brief Length for Ifx_PSI5S_CON_Bits.PEN */
+#define IFX_PSI5S_CON_PEN_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_CON_Bits.PEN */
+#define IFX_PSI5S_CON_PEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_CON_Bits.PEN */
+#define IFX_PSI5S_CON_PEN_OFF (5u)
+
+/** \brief Length for Ifx_PSI5S_CON_Bits.R */
+#define IFX_PSI5S_CON_R_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_CON_Bits.R */
+#define IFX_PSI5S_CON_R_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_CON_Bits.R */
+#define IFX_PSI5S_CON_R_OFF (15u)
+
+/** \brief Length for Ifx_PSI5S_CON_Bits.REN */
+#define IFX_PSI5S_CON_REN_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_CON_Bits.REN */
+#define IFX_PSI5S_CON_REN_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_CON_Bits.REN */
+#define IFX_PSI5S_CON_REN_OFF (4u)
+
+/** \brief Length for Ifx_PSI5S_CON_Bits.STP */
+#define IFX_PSI5S_CON_STP_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_CON_Bits.STP */
+#define IFX_PSI5S_CON_STP_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_CON_Bits.STP */
+#define IFX_PSI5S_CON_STP_OFF (3u)
+
+/** \brief Length for Ifx_PSI5S_CTV_Bits.CTC */
+#define IFX_PSI5S_CTV_CTC_LEN (16u)
+
+/** \brief Mask for Ifx_PSI5S_CTV_Bits.CTC */
+#define IFX_PSI5S_CTV_CTC_MSK (0xffffu)
+
+/** \brief Offset for Ifx_PSI5S_CTV_Bits.CTC */
+#define IFX_PSI5S_CTV_CTC_OFF (16u)
+
+/** \brief Length for Ifx_PSI5S_CTV_Bits.CTV */
+#define IFX_PSI5S_CTV_CTV_LEN (16u)
+
+/** \brief Mask for Ifx_PSI5S_CTV_Bits.CTV */
+#define IFX_PSI5S_CTV_CTV_MSK (0xffffu)
+
+/** \brief Offset for Ifx_PSI5S_CTV_Bits.CTV */
+#define IFX_PSI5S_CTV_CTV_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_FCNT_Bits.FC0 */
+#define IFX_PSI5S_FCNT_FC0_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_FCNT_Bits.FC0 */
+#define IFX_PSI5S_FCNT_FC0_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_FCNT_Bits.FC0 */
+#define IFX_PSI5S_FCNT_FC0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_FCNT_Bits.FC1 */
+#define IFX_PSI5S_FCNT_FC1_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_FCNT_Bits.FC1 */
+#define IFX_PSI5S_FCNT_FC1_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_FCNT_Bits.FC1 */
+#define IFX_PSI5S_FCNT_FC1_OFF (3u)
+
+/** \brief Length for Ifx_PSI5S_FCNT_Bits.FC2 */
+#define IFX_PSI5S_FCNT_FC2_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_FCNT_Bits.FC2 */
+#define IFX_PSI5S_FCNT_FC2_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_FCNT_Bits.FC2 */
+#define IFX_PSI5S_FCNT_FC2_OFF (6u)
+
+/** \brief Length for Ifx_PSI5S_FCNT_Bits.FC3 */
+#define IFX_PSI5S_FCNT_FC3_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_FCNT_Bits.FC3 */
+#define IFX_PSI5S_FCNT_FC3_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_FCNT_Bits.FC3 */
+#define IFX_PSI5S_FCNT_FC3_OFF (9u)
+
+/** \brief Length for Ifx_PSI5S_FCNT_Bits.FC4 */
+#define IFX_PSI5S_FCNT_FC4_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_FCNT_Bits.FC4 */
+#define IFX_PSI5S_FCNT_FC4_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_FCNT_Bits.FC4 */
+#define IFX_PSI5S_FCNT_FC4_OFF (12u)
+
+/** \brief Length for Ifx_PSI5S_FCNT_Bits.FC5 */
+#define IFX_PSI5S_FCNT_FC5_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_FCNT_Bits.FC5 */
+#define IFX_PSI5S_FCNT_FC5_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_FCNT_Bits.FC5 */
+#define IFX_PSI5S_FCNT_FC5_OFF (15u)
+
+/** \brief Length for Ifx_PSI5S_FCNT_Bits.FC6 */
+#define IFX_PSI5S_FCNT_FC6_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_FCNT_Bits.FC6 */
+#define IFX_PSI5S_FCNT_FC6_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_FCNT_Bits.FC6 */
+#define IFX_PSI5S_FCNT_FC6_OFF (18u)
+
+/** \brief Length for Ifx_PSI5S_FCNT_Bits.FC7 */
+#define IFX_PSI5S_FCNT_FC7_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_FCNT_Bits.FC7 */
+#define IFX_PSI5S_FCNT_FC7_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_FCNT_Bits.FC7 */
+#define IFX_PSI5S_FCNT_FC7_OFF (21u)
+
+/** \brief Length for Ifx_PSI5S_FCNT_Bits.NFCLR0 */
+#define IFX_PSI5S_FCNT_NFCLR0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_FCNT_Bits.NFCLR0 */
+#define IFX_PSI5S_FCNT_NFCLR0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_FCNT_Bits.NFCLR0 */
+#define IFX_PSI5S_FCNT_NFCLR0_OFF (24u)
+
+/** \brief Length for Ifx_PSI5S_FCNT_Bits.NFCLR1 */
+#define IFX_PSI5S_FCNT_NFCLR1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_FCNT_Bits.NFCLR1 */
+#define IFX_PSI5S_FCNT_NFCLR1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_FCNT_Bits.NFCLR1 */
+#define IFX_PSI5S_FCNT_NFCLR1_OFF (25u)
+
+/** \brief Length for Ifx_PSI5S_FCNT_Bits.NFCLR2 */
+#define IFX_PSI5S_FCNT_NFCLR2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_FCNT_Bits.NFCLR2 */
+#define IFX_PSI5S_FCNT_NFCLR2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_FCNT_Bits.NFCLR2 */
+#define IFX_PSI5S_FCNT_NFCLR2_OFF (26u)
+
+/** \brief Length for Ifx_PSI5S_FCNT_Bits.NFCLR3 */
+#define IFX_PSI5S_FCNT_NFCLR3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_FCNT_Bits.NFCLR3 */
+#define IFX_PSI5S_FCNT_NFCLR3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_FCNT_Bits.NFCLR3 */
+#define IFX_PSI5S_FCNT_NFCLR3_OFF (27u)
+
+/** \brief Length for Ifx_PSI5S_FCNT_Bits.NFCLR4 */
+#define IFX_PSI5S_FCNT_NFCLR4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_FCNT_Bits.NFCLR4 */
+#define IFX_PSI5S_FCNT_NFCLR4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_FCNT_Bits.NFCLR4 */
+#define IFX_PSI5S_FCNT_NFCLR4_OFF (28u)
+
+/** \brief Length for Ifx_PSI5S_FCNT_Bits.NFCLR5 */
+#define IFX_PSI5S_FCNT_NFCLR5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_FCNT_Bits.NFCLR5 */
+#define IFX_PSI5S_FCNT_NFCLR5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_FCNT_Bits.NFCLR5 */
+#define IFX_PSI5S_FCNT_NFCLR5_OFF (29u)
+
+/** \brief Length for Ifx_PSI5S_FCNT_Bits.NFCLR6 */
+#define IFX_PSI5S_FCNT_NFCLR6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_FCNT_Bits.NFCLR6 */
+#define IFX_PSI5S_FCNT_NFCLR6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_FCNT_Bits.NFCLR6 */
+#define IFX_PSI5S_FCNT_NFCLR6_OFF (30u)
+
+/** \brief Length for Ifx_PSI5S_FCNT_Bits.NFCLR7 */
+#define IFX_PSI5S_FCNT_NFCLR7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_FCNT_Bits.NFCLR7 */
+#define IFX_PSI5S_FCNT_NFCLR7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_FCNT_Bits.NFCLR7 */
+#define IFX_PSI5S_FCNT_NFCLR7_OFF (31u)
+
+/** \brief Length for Ifx_PSI5S_FDO_Bits.DM */
+#define IFX_PSI5S_FDO_DM_LEN (2u)
+
+/** \brief Mask for Ifx_PSI5S_FDO_Bits.DM */
+#define IFX_PSI5S_FDO_DM_MSK (0x3u)
+
+/** \brief Offset for Ifx_PSI5S_FDO_Bits.DM */
+#define IFX_PSI5S_FDO_DM_OFF (14u)
+
+/** \brief Length for Ifx_PSI5S_FDO_Bits.STEP */
+#define IFX_PSI5S_FDO_STEP_LEN (11u)
+
+/** \brief Mask for Ifx_PSI5S_FDO_Bits.STEP */
+#define IFX_PSI5S_FDO_STEP_MSK (0x7ffu)
+
+/** \brief Offset for Ifx_PSI5S_FDO_Bits.STEP */
+#define IFX_PSI5S_FDO_STEP_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_FDR_Bits.DM */
+#define IFX_PSI5S_FDR_DM_LEN (2u)
+
+/** \brief Mask for Ifx_PSI5S_FDR_Bits.DM */
+#define IFX_PSI5S_FDR_DM_MSK (0x3u)
+
+/** \brief Offset for Ifx_PSI5S_FDR_Bits.DM */
+#define IFX_PSI5S_FDR_DM_OFF (14u)
+
+/** \brief Length for Ifx_PSI5S_FDR_Bits.RESULT */
+#define IFX_PSI5S_FDR_RESULT_LEN (10u)
+
+/** \brief Mask for Ifx_PSI5S_FDR_Bits.RESULT */
+#define IFX_PSI5S_FDR_RESULT_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_PSI5S_FDR_Bits.RESULT */
+#define IFX_PSI5S_FDR_RESULT_OFF (16u)
+
+/** \brief Length for Ifx_PSI5S_FDR_Bits.STEP */
+#define IFX_PSI5S_FDR_STEP_LEN (10u)
+
+/** \brief Mask for Ifx_PSI5S_FDR_Bits.STEP */
+#define IFX_PSI5S_FDR_STEP_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_PSI5S_FDR_Bits.STEP */
+#define IFX_PSI5S_FDR_STEP_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_FDRT_Bits.DM */
+#define IFX_PSI5S_FDRT_DM_LEN (2u)
+
+/** \brief Mask for Ifx_PSI5S_FDRT_Bits.DM */
+#define IFX_PSI5S_FDRT_DM_MSK (0x3u)
+
+/** \brief Offset for Ifx_PSI5S_FDRT_Bits.DM */
+#define IFX_PSI5S_FDRT_DM_OFF (14u)
+
+/** \brief Length for Ifx_PSI5S_FDRT_Bits.ECEA */
+#define IFX_PSI5S_FDRT_ECEA_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_FDRT_Bits.ECEA */
+#define IFX_PSI5S_FDRT_ECEA_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_FDRT_Bits.ECEA */
+#define IFX_PSI5S_FDRT_ECEA_OFF (29u)
+
+/** \brief Length for Ifx_PSI5S_FDRT_Bits.ECEB */
+#define IFX_PSI5S_FDRT_ECEB_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_FDRT_Bits.ECEB */
+#define IFX_PSI5S_FDRT_ECEB_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_FDRT_Bits.ECEB */
+#define IFX_PSI5S_FDRT_ECEB_OFF (30u)
+
+/** \brief Length for Ifx_PSI5S_FDRT_Bits.ECS */
+#define IFX_PSI5S_FDRT_ECS_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_FDRT_Bits.ECS */
+#define IFX_PSI5S_FDRT_ECS_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_FDRT_Bits.ECS */
+#define IFX_PSI5S_FDRT_ECS_OFF (26u)
+
+/** \brief Length for Ifx_PSI5S_FDRT_Bits.RESULT */
+#define IFX_PSI5S_FDRT_RESULT_LEN (10u)
+
+/** \brief Mask for Ifx_PSI5S_FDRT_Bits.RESULT */
+#define IFX_PSI5S_FDRT_RESULT_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_PSI5S_FDRT_Bits.RESULT */
+#define IFX_PSI5S_FDRT_RESULT_OFF (16u)
+
+/** \brief Length for Ifx_PSI5S_FDRT_Bits.STEP */
+#define IFX_PSI5S_FDRT_STEP_LEN (10u)
+
+/** \brief Mask for Ifx_PSI5S_FDRT_Bits.STEP */
+#define IFX_PSI5S_FDRT_STEP_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_PSI5S_FDRT_Bits.STEP */
+#define IFX_PSI5S_FDRT_STEP_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_FDV_Bits.FD_VALUE */
+#define IFX_PSI5S_FDV_FD_VALUE_LEN (11u)
+
+/** \brief Mask for Ifx_PSI5S_FDV_Bits.FD_VALUE */
+#define IFX_PSI5S_FDV_FD_VALUE_MSK (0x7ffu)
+
+/** \brief Offset for Ifx_PSI5S_FDV_Bits.FD_VALUE */
+#define IFX_PSI5S_FDV_FD_VALUE_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_GCR_Bits.ASC */
+#define IFX_PSI5S_GCR_ASC_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_GCR_Bits.ASC */
+#define IFX_PSI5S_GCR_ASC_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_GCR_Bits.ASC */
+#define IFX_PSI5S_GCR_ASC_OFF (31u)
+
+/** \brief Length for Ifx_PSI5S_GCR_Bits.CEN0 */
+#define IFX_PSI5S_GCR_CEN0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_GCR_Bits.CEN0 */
+#define IFX_PSI5S_GCR_CEN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_GCR_Bits.CEN0 */
+#define IFX_PSI5S_GCR_CEN0_OFF (16u)
+
+/** \brief Length for Ifx_PSI5S_GCR_Bits.CEN1 */
+#define IFX_PSI5S_GCR_CEN1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_GCR_Bits.CEN1 */
+#define IFX_PSI5S_GCR_CEN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_GCR_Bits.CEN1 */
+#define IFX_PSI5S_GCR_CEN1_OFF (17u)
+
+/** \brief Length for Ifx_PSI5S_GCR_Bits.CEN2 */
+#define IFX_PSI5S_GCR_CEN2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_GCR_Bits.CEN2 */
+#define IFX_PSI5S_GCR_CEN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_GCR_Bits.CEN2 */
+#define IFX_PSI5S_GCR_CEN2_OFF (18u)
+
+/** \brief Length for Ifx_PSI5S_GCR_Bits.CEN3 */
+#define IFX_PSI5S_GCR_CEN3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_GCR_Bits.CEN3 */
+#define IFX_PSI5S_GCR_CEN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_GCR_Bits.CEN3 */
+#define IFX_PSI5S_GCR_CEN3_OFF (19u)
+
+/** \brief Length for Ifx_PSI5S_GCR_Bits.CEN4 */
+#define IFX_PSI5S_GCR_CEN4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_GCR_Bits.CEN4 */
+#define IFX_PSI5S_GCR_CEN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_GCR_Bits.CEN4 */
+#define IFX_PSI5S_GCR_CEN4_OFF (20u)
+
+/** \brief Length for Ifx_PSI5S_GCR_Bits.CEN5 */
+#define IFX_PSI5S_GCR_CEN5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_GCR_Bits.CEN5 */
+#define IFX_PSI5S_GCR_CEN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_GCR_Bits.CEN5 */
+#define IFX_PSI5S_GCR_CEN5_OFF (21u)
+
+/** \brief Length for Ifx_PSI5S_GCR_Bits.CEN6 */
+#define IFX_PSI5S_GCR_CEN6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_GCR_Bits.CEN6 */
+#define IFX_PSI5S_GCR_CEN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_GCR_Bits.CEN6 */
+#define IFX_PSI5S_GCR_CEN6_OFF (22u)
+
+/** \brief Length for Ifx_PSI5S_GCR_Bits.CEN7 */
+#define IFX_PSI5S_GCR_CEN7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_GCR_Bits.CEN7 */
+#define IFX_PSI5S_GCR_CEN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_GCR_Bits.CEN7 */
+#define IFX_PSI5S_GCR_CEN7_OFF (23u)
+
+/** \brief Length for Ifx_PSI5S_GCR_Bits.CRCI */
+#define IFX_PSI5S_GCR_CRCI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_GCR_Bits.CRCI */
+#define IFX_PSI5S_GCR_CRCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_GCR_Bits.CRCI */
+#define IFX_PSI5S_GCR_CRCI_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_GCR_Bits.ETC0 */
+#define IFX_PSI5S_GCR_ETC0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_GCR_Bits.ETC0 */
+#define IFX_PSI5S_GCR_ETC0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_GCR_Bits.ETC0 */
+#define IFX_PSI5S_GCR_ETC0_OFF (8u)
+
+/** \brief Length for Ifx_PSI5S_GCR_Bits.ETC1 */
+#define IFX_PSI5S_GCR_ETC1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_GCR_Bits.ETC1 */
+#define IFX_PSI5S_GCR_ETC1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_GCR_Bits.ETC1 */
+#define IFX_PSI5S_GCR_ETC1_OFF (9u)
+
+/** \brief Length for Ifx_PSI5S_GCR_Bits.ETC2 */
+#define IFX_PSI5S_GCR_ETC2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_GCR_Bits.ETC2 */
+#define IFX_PSI5S_GCR_ETC2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_GCR_Bits.ETC2 */
+#define IFX_PSI5S_GCR_ETC2_OFF (10u)
+
+/** \brief Length for Ifx_PSI5S_GCR_Bits.ETC3 */
+#define IFX_PSI5S_GCR_ETC3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_GCR_Bits.ETC3 */
+#define IFX_PSI5S_GCR_ETC3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_GCR_Bits.ETC3 */
+#define IFX_PSI5S_GCR_ETC3_OFF (11u)
+
+/** \brief Length for Ifx_PSI5S_GCR_Bits.ETC4 */
+#define IFX_PSI5S_GCR_ETC4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_GCR_Bits.ETC4 */
+#define IFX_PSI5S_GCR_ETC4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_GCR_Bits.ETC4 */
+#define IFX_PSI5S_GCR_ETC4_OFF (12u)
+
+/** \brief Length for Ifx_PSI5S_GCR_Bits.ETC5 */
+#define IFX_PSI5S_GCR_ETC5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_GCR_Bits.ETC5 */
+#define IFX_PSI5S_GCR_ETC5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_GCR_Bits.ETC5 */
+#define IFX_PSI5S_GCR_ETC5_OFF (13u)
+
+/** \brief Length for Ifx_PSI5S_GCR_Bits.ETC6 */
+#define IFX_PSI5S_GCR_ETC6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_GCR_Bits.ETC6 */
+#define IFX_PSI5S_GCR_ETC6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_GCR_Bits.ETC6 */
+#define IFX_PSI5S_GCR_ETC6_OFF (14u)
+
+/** \brief Length for Ifx_PSI5S_GCR_Bits.ETC7 */
+#define IFX_PSI5S_GCR_ETC7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_GCR_Bits.ETC7 */
+#define IFX_PSI5S_GCR_ETC7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_GCR_Bits.ETC7 */
+#define IFX_PSI5S_GCR_ETC7_OFF (15u)
+
+/** \brief Length for Ifx_PSI5S_GCR_Bits.FE */
+#define IFX_PSI5S_GCR_FE_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_GCR_Bits.FE */
+#define IFX_PSI5S_GCR_FE_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_GCR_Bits.FE */
+#define IFX_PSI5S_GCR_FE_OFF (4u)
+
+/** \brief Length for Ifx_PSI5S_GCR_Bits.HDI */
+#define IFX_PSI5S_GCR_HDI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_GCR_Bits.HDI */
+#define IFX_PSI5S_GCR_HDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_GCR_Bits.HDI */
+#define IFX_PSI5S_GCR_HDI_OFF (7u)
+
+/** \brief Length for Ifx_PSI5S_GCR_Bits.IDT */
+#define IFX_PSI5S_GCR_IDT_LEN (4u)
+
+/** \brief Mask for Ifx_PSI5S_GCR_Bits.IDT */
+#define IFX_PSI5S_GCR_IDT_MSK (0xfu)
+
+/** \brief Offset for Ifx_PSI5S_GCR_Bits.IDT */
+#define IFX_PSI5S_GCR_IDT_OFF (24u)
+
+/** \brief Length for Ifx_PSI5S_GCR_Bits.OE */
+#define IFX_PSI5S_GCR_OE_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_GCR_Bits.OE */
+#define IFX_PSI5S_GCR_OE_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_GCR_Bits.OE */
+#define IFX_PSI5S_GCR_OE_OFF (5u)
+
+/** \brief Length for Ifx_PSI5S_GCR_Bits.PE */
+#define IFX_PSI5S_GCR_PE_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_GCR_Bits.PE */
+#define IFX_PSI5S_GCR_PE_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_GCR_Bits.PE */
+#define IFX_PSI5S_GCR_PE_OFF (3u)
+
+/** \brief Length for Ifx_PSI5S_GCR_Bits.RBI */
+#define IFX_PSI5S_GCR_RBI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_GCR_Bits.RBI */
+#define IFX_PSI5S_GCR_RBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_GCR_Bits.RBI */
+#define IFX_PSI5S_GCR_RBI_OFF (6u)
+
+/** \brief Length for Ifx_PSI5S_GCR_Bits.TEI */
+#define IFX_PSI5S_GCR_TEI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_GCR_Bits.TEI */
+#define IFX_PSI5S_GCR_TEI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_GCR_Bits.TEI */
+#define IFX_PSI5S_GCR_TEI_OFF (2u)
+
+/** \brief Length for Ifx_PSI5S_GCR_Bits.XCRCI */
+#define IFX_PSI5S_GCR_XCRCI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_GCR_Bits.XCRCI */
+#define IFX_PSI5S_GCR_XCRCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_GCR_Bits.XCRCI */
+#define IFX_PSI5S_GCR_XCRCI_OFF (1u)
+
+/** \brief Length for Ifx_PSI5S_ID_Bits.MODNUMBER */
+#define IFX_PSI5S_ID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_PSI5S_ID_Bits.MODNUMBER */
+#define IFX_PSI5S_ID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_PSI5S_ID_Bits.MODNUMBER */
+#define IFX_PSI5S_ID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_PSI5S_ID_Bits.MODREV */
+#define IFX_PSI5S_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_PSI5S_ID_Bits.MODREV */
+#define IFX_PSI5S_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_PSI5S_ID_Bits.MODREV */
+#define IFX_PSI5S_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_ID_Bits.MODTYPE */
+#define IFX_PSI5S_ID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_PSI5S_ID_Bits.MODTYPE */
+#define IFX_PSI5S_ID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_PSI5S_ID_Bits.MODTYPE */
+#define IFX_PSI5S_ID_MODTYPE_OFF (8u)
+
+/** \brief Length for Ifx_PSI5S_INP_Bits.CHCI */
+#define IFX_PSI5S_INP_CHCI_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_INP_Bits.CHCI */
+#define IFX_PSI5S_INP_CHCI_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_INP_Bits.CHCI */
+#define IFX_PSI5S_INP_CHCI_OFF (12u)
+
+/** \brief Length for Ifx_PSI5S_INP_Bits.CRCI */
+#define IFX_PSI5S_INP_CRCI_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_INP_Bits.CRCI */
+#define IFX_PSI5S_INP_CRCI_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_INP_Bits.CRCI */
+#define IFX_PSI5S_INP_CRCI_OFF (15u)
+
+/** \brief Length for Ifx_PSI5S_INP_Bits.HDI */
+#define IFX_PSI5S_INP_HDI_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_INP_Bits.HDI */
+#define IFX_PSI5S_INP_HDI_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_INP_Bits.HDI */
+#define IFX_PSI5S_INP_HDI_OFF (24u)
+
+/** \brief Length for Ifx_PSI5S_INP_Bits.RBI */
+#define IFX_PSI5S_INP_RBI_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_INP_Bits.RBI */
+#define IFX_PSI5S_INP_RBI_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_INP_Bits.RBI */
+#define IFX_PSI5S_INP_RBI_OFF (6u)
+
+/** \brief Length for Ifx_PSI5S_INP_Bits.RDI */
+#define IFX_PSI5S_INP_RDI_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_INP_Bits.RDI */
+#define IFX_PSI5S_INP_RDI_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_INP_Bits.RDI */
+#define IFX_PSI5S_INP_RDI_OFF (3u)
+
+/** \brief Length for Ifx_PSI5S_INP_Bits.RSI */
+#define IFX_PSI5S_INP_RSI_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_INP_Bits.RSI */
+#define IFX_PSI5S_INP_RSI_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_INP_Bits.RSI */
+#define IFX_PSI5S_INP_RSI_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_INP_Bits.TEI */
+#define IFX_PSI5S_INP_TEI_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_INP_Bits.TEI */
+#define IFX_PSI5S_INP_TEI_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_INP_Bits.TEI */
+#define IFX_PSI5S_INP_TEI_OFF (9u)
+
+/** \brief Length for Ifx_PSI5S_INP_Bits.TPI */
+#define IFX_PSI5S_INP_TPI_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_INP_Bits.TPI */
+#define IFX_PSI5S_INP_TPI_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_INP_Bits.TPI */
+#define IFX_PSI5S_INP_TPI_OFF (18u)
+
+/** \brief Length for Ifx_PSI5S_INP_Bits.TPOI */
+#define IFX_PSI5S_INP_TPOI_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_INP_Bits.TPOI */
+#define IFX_PSI5S_INP_TPOI_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_INP_Bits.TPOI */
+#define IFX_PSI5S_INP_TPOI_OFF (21u)
+
+/** \brief Length for Ifx_PSI5S_INPG_Bits.EIR */
+#define IFX_PSI5S_INPG_EIR_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_INPG_Bits.EIR */
+#define IFX_PSI5S_INPG_EIR_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_INPG_Bits.EIR */
+#define IFX_PSI5S_INPG_EIR_OFF (6u)
+
+/** \brief Length for Ifx_PSI5S_INPG_Bits.FOI */
+#define IFX_PSI5S_INPG_FOI_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_INPG_Bits.FOI */
+#define IFX_PSI5S_INPG_FOI_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_INPG_Bits.FOI */
+#define IFX_PSI5S_INPG_FOI_OFF (15u)
+
+/** \brief Length for Ifx_PSI5S_INPG_Bits.RIR */
+#define IFX_PSI5S_INPG_RIR_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_INPG_Bits.RIR */
+#define IFX_PSI5S_INPG_RIR_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_INPG_Bits.RIR */
+#define IFX_PSI5S_INPG_RIR_OFF (3u)
+
+/** \brief Length for Ifx_PSI5S_INPG_Bits.TBIR */
+#define IFX_PSI5S_INPG_TBIR_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_INPG_Bits.TBIR */
+#define IFX_PSI5S_INPG_TBIR_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_INPG_Bits.TBIR */
+#define IFX_PSI5S_INPG_TBIR_OFF (9u)
+
+/** \brief Length for Ifx_PSI5S_INPG_Bits.TIR */
+#define IFX_PSI5S_INPG_TIR_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_INPG_Bits.TIR */
+#define IFX_PSI5S_INPG_TIR_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_INPG_Bits.TIR */
+#define IFX_PSI5S_INPG_TIR_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_INPG_Bits.XCRCI */
+#define IFX_PSI5S_INPG_XCRCI_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_INPG_Bits.XCRCI */
+#define IFX_PSI5S_INPG_XCRCI_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_INPG_Bits.XCRCI */
+#define IFX_PSI5S_INPG_XCRCI_OFF (12u)
+
+/** \brief Length for Ifx_PSI5S_INTCLR_Bits.CHCI */
+#define IFX_PSI5S_INTCLR_CHCI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTCLR_Bits.CHCI */
+#define IFX_PSI5S_INTCLR_CHCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTCLR_Bits.CHCI */
+#define IFX_PSI5S_INTCLR_CHCI_OFF (4u)
+
+/** \brief Length for Ifx_PSI5S_INTCLR_Bits.CRCI */
+#define IFX_PSI5S_INTCLR_CRCI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTCLR_Bits.CRCI */
+#define IFX_PSI5S_INTCLR_CRCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTCLR_Bits.CRCI */
+#define IFX_PSI5S_INTCLR_CRCI_OFF (5u)
+
+/** \brief Length for Ifx_PSI5S_INTCLR_Bits.HDI */
+#define IFX_PSI5S_INTCLR_HDI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTCLR_Bits.HDI */
+#define IFX_PSI5S_INTCLR_HDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTCLR_Bits.HDI */
+#define IFX_PSI5S_INTCLR_HDI_OFF (8u)
+
+/** \brief Length for Ifx_PSI5S_INTCLR_Bits.RBI */
+#define IFX_PSI5S_INTCLR_RBI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTCLR_Bits.RBI */
+#define IFX_PSI5S_INTCLR_RBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTCLR_Bits.RBI */
+#define IFX_PSI5S_INTCLR_RBI_OFF (2u)
+
+/** \brief Length for Ifx_PSI5S_INTCLR_Bits.RDI */
+#define IFX_PSI5S_INTCLR_RDI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTCLR_Bits.RDI */
+#define IFX_PSI5S_INTCLR_RDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTCLR_Bits.RDI */
+#define IFX_PSI5S_INTCLR_RDI_OFF (1u)
+
+/** \brief Length for Ifx_PSI5S_INTCLR_Bits.RSI */
+#define IFX_PSI5S_INTCLR_RSI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTCLR_Bits.RSI */
+#define IFX_PSI5S_INTCLR_RSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTCLR_Bits.RSI */
+#define IFX_PSI5S_INTCLR_RSI_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_INTCLR_Bits.TEI */
+#define IFX_PSI5S_INTCLR_TEI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTCLR_Bits.TEI */
+#define IFX_PSI5S_INTCLR_TEI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTCLR_Bits.TEI */
+#define IFX_PSI5S_INTCLR_TEI_OFF (3u)
+
+/** \brief Length for Ifx_PSI5S_INTCLR_Bits.TPI */
+#define IFX_PSI5S_INTCLR_TPI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTCLR_Bits.TPI */
+#define IFX_PSI5S_INTCLR_TPI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTCLR_Bits.TPI */
+#define IFX_PSI5S_INTCLR_TPI_OFF (6u)
+
+/** \brief Length for Ifx_PSI5S_INTCLR_Bits.TPOI */
+#define IFX_PSI5S_INTCLR_TPOI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTCLR_Bits.TPOI */
+#define IFX_PSI5S_INTCLR_TPOI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTCLR_Bits.TPOI */
+#define IFX_PSI5S_INTCLR_TPOI_OFF (7u)
+
+/** \brief Length for Ifx_PSI5S_INTCLRG_Bits.EIR */
+#define IFX_PSI5S_INTCLRG_EIR_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTCLRG_Bits.EIR */
+#define IFX_PSI5S_INTCLRG_EIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTCLRG_Bits.EIR */
+#define IFX_PSI5S_INTCLRG_EIR_OFF (2u)
+
+/** \brief Length for Ifx_PSI5S_INTCLRG_Bits.FOI */
+#define IFX_PSI5S_INTCLRG_FOI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTCLRG_Bits.FOI */
+#define IFX_PSI5S_INTCLRG_FOI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTCLRG_Bits.FOI */
+#define IFX_PSI5S_INTCLRG_FOI_OFF (5u)
+
+/** \brief Length for Ifx_PSI5S_INTCLRG_Bits.RIR */
+#define IFX_PSI5S_INTCLRG_RIR_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTCLRG_Bits.RIR */
+#define IFX_PSI5S_INTCLRG_RIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTCLRG_Bits.RIR */
+#define IFX_PSI5S_INTCLRG_RIR_OFF (1u)
+
+/** \brief Length for Ifx_PSI5S_INTCLRG_Bits.TBIR */
+#define IFX_PSI5S_INTCLRG_TBIR_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTCLRG_Bits.TBIR */
+#define IFX_PSI5S_INTCLRG_TBIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTCLRG_Bits.TBIR */
+#define IFX_PSI5S_INTCLRG_TBIR_OFF (3u)
+
+/** \brief Length for Ifx_PSI5S_INTCLRG_Bits.TIR */
+#define IFX_PSI5S_INTCLRG_TIR_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTCLRG_Bits.TIR */
+#define IFX_PSI5S_INTCLRG_TIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTCLRG_Bits.TIR */
+#define IFX_PSI5S_INTCLRG_TIR_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_INTCLRG_Bits.XCRCI */
+#define IFX_PSI5S_INTCLRG_XCRCI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTCLRG_Bits.XCRCI */
+#define IFX_PSI5S_INTCLRG_XCRCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTCLRG_Bits.XCRCI */
+#define IFX_PSI5S_INTCLRG_XCRCI_OFF (4u)
+
+/** \brief Length for Ifx_PSI5S_INTEN_Bits.CHCI */
+#define IFX_PSI5S_INTEN_CHCI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTEN_Bits.CHCI */
+#define IFX_PSI5S_INTEN_CHCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTEN_Bits.CHCI */
+#define IFX_PSI5S_INTEN_CHCI_OFF (4u)
+
+/** \brief Length for Ifx_PSI5S_INTEN_Bits.CRCI */
+#define IFX_PSI5S_INTEN_CRCI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTEN_Bits.CRCI */
+#define IFX_PSI5S_INTEN_CRCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTEN_Bits.CRCI */
+#define IFX_PSI5S_INTEN_CRCI_OFF (5u)
+
+/** \brief Length for Ifx_PSI5S_INTEN_Bits.HDI */
+#define IFX_PSI5S_INTEN_HDI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTEN_Bits.HDI */
+#define IFX_PSI5S_INTEN_HDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTEN_Bits.HDI */
+#define IFX_PSI5S_INTEN_HDI_OFF (8u)
+
+/** \brief Length for Ifx_PSI5S_INTEN_Bits.RBI */
+#define IFX_PSI5S_INTEN_RBI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTEN_Bits.RBI */
+#define IFX_PSI5S_INTEN_RBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTEN_Bits.RBI */
+#define IFX_PSI5S_INTEN_RBI_OFF (2u)
+
+/** \brief Length for Ifx_PSI5S_INTEN_Bits.RDI */
+#define IFX_PSI5S_INTEN_RDI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTEN_Bits.RDI */
+#define IFX_PSI5S_INTEN_RDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTEN_Bits.RDI */
+#define IFX_PSI5S_INTEN_RDI_OFF (1u)
+
+/** \brief Length for Ifx_PSI5S_INTEN_Bits.RSI */
+#define IFX_PSI5S_INTEN_RSI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTEN_Bits.RSI */
+#define IFX_PSI5S_INTEN_RSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTEN_Bits.RSI */
+#define IFX_PSI5S_INTEN_RSI_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_INTEN_Bits.TEI */
+#define IFX_PSI5S_INTEN_TEI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTEN_Bits.TEI */
+#define IFX_PSI5S_INTEN_TEI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTEN_Bits.TEI */
+#define IFX_PSI5S_INTEN_TEI_OFF (3u)
+
+/** \brief Length for Ifx_PSI5S_INTEN_Bits.TPI */
+#define IFX_PSI5S_INTEN_TPI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTEN_Bits.TPI */
+#define IFX_PSI5S_INTEN_TPI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTEN_Bits.TPI */
+#define IFX_PSI5S_INTEN_TPI_OFF (6u)
+
+/** \brief Length for Ifx_PSI5S_INTEN_Bits.TPOI */
+#define IFX_PSI5S_INTEN_TPOI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTEN_Bits.TPOI */
+#define IFX_PSI5S_INTEN_TPOI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTEN_Bits.TPOI */
+#define IFX_PSI5S_INTEN_TPOI_OFF (7u)
+
+/** \brief Length for Ifx_PSI5S_INTENG_Bits.EIR */
+#define IFX_PSI5S_INTENG_EIR_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTENG_Bits.EIR */
+#define IFX_PSI5S_INTENG_EIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTENG_Bits.EIR */
+#define IFX_PSI5S_INTENG_EIR_OFF (2u)
+
+/** \brief Length for Ifx_PSI5S_INTENG_Bits.FOI */
+#define IFX_PSI5S_INTENG_FOI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTENG_Bits.FOI */
+#define IFX_PSI5S_INTENG_FOI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTENG_Bits.FOI */
+#define IFX_PSI5S_INTENG_FOI_OFF (5u)
+
+/** \brief Length for Ifx_PSI5S_INTENG_Bits.RIR */
+#define IFX_PSI5S_INTENG_RIR_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTENG_Bits.RIR */
+#define IFX_PSI5S_INTENG_RIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTENG_Bits.RIR */
+#define IFX_PSI5S_INTENG_RIR_OFF (1u)
+
+/** \brief Length for Ifx_PSI5S_INTENG_Bits.TBIR */
+#define IFX_PSI5S_INTENG_TBIR_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTENG_Bits.TBIR */
+#define IFX_PSI5S_INTENG_TBIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTENG_Bits.TBIR */
+#define IFX_PSI5S_INTENG_TBIR_OFF (3u)
+
+/** \brief Length for Ifx_PSI5S_INTENG_Bits.TIR */
+#define IFX_PSI5S_INTENG_TIR_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTENG_Bits.TIR */
+#define IFX_PSI5S_INTENG_TIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTENG_Bits.TIR */
+#define IFX_PSI5S_INTENG_TIR_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_INTENG_Bits.XCRCI */
+#define IFX_PSI5S_INTENG_XCRCI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTENG_Bits.XCRCI */
+#define IFX_PSI5S_INTENG_XCRCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTENG_Bits.XCRCI */
+#define IFX_PSI5S_INTENG_XCRCI_OFF (4u)
+
+/** \brief Length for Ifx_PSI5S_INTOV_Bits.CHCI */
+#define IFX_PSI5S_INTOV_CHCI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTOV_Bits.CHCI */
+#define IFX_PSI5S_INTOV_CHCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTOV_Bits.CHCI */
+#define IFX_PSI5S_INTOV_CHCI_OFF (4u)
+
+/** \brief Length for Ifx_PSI5S_INTOV_Bits.CRCI */
+#define IFX_PSI5S_INTOV_CRCI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTOV_Bits.CRCI */
+#define IFX_PSI5S_INTOV_CRCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTOV_Bits.CRCI */
+#define IFX_PSI5S_INTOV_CRCI_OFF (5u)
+
+/** \brief Length for Ifx_PSI5S_INTOV_Bits.EIR */
+#define IFX_PSI5S_INTOV_EIR_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTOV_Bits.EIR */
+#define IFX_PSI5S_INTOV_EIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTOV_Bits.EIR */
+#define IFX_PSI5S_INTOV_EIR_OFF (11u)
+
+/** \brief Length for Ifx_PSI5S_INTOV_Bits.FOI */
+#define IFX_PSI5S_INTOV_FOI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTOV_Bits.FOI */
+#define IFX_PSI5S_INTOV_FOI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTOV_Bits.FOI */
+#define IFX_PSI5S_INTOV_FOI_OFF (14u)
+
+/** \brief Length for Ifx_PSI5S_INTOV_Bits.HDI */
+#define IFX_PSI5S_INTOV_HDI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTOV_Bits.HDI */
+#define IFX_PSI5S_INTOV_HDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTOV_Bits.HDI */
+#define IFX_PSI5S_INTOV_HDI_OFF (8u)
+
+/** \brief Length for Ifx_PSI5S_INTOV_Bits.RBI */
+#define IFX_PSI5S_INTOV_RBI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTOV_Bits.RBI */
+#define IFX_PSI5S_INTOV_RBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTOV_Bits.RBI */
+#define IFX_PSI5S_INTOV_RBI_OFF (2u)
+
+/** \brief Length for Ifx_PSI5S_INTOV_Bits.RDI */
+#define IFX_PSI5S_INTOV_RDI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTOV_Bits.RDI */
+#define IFX_PSI5S_INTOV_RDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTOV_Bits.RDI */
+#define IFX_PSI5S_INTOV_RDI_OFF (1u)
+
+/** \brief Length for Ifx_PSI5S_INTOV_Bits.RIR */
+#define IFX_PSI5S_INTOV_RIR_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTOV_Bits.RIR */
+#define IFX_PSI5S_INTOV_RIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTOV_Bits.RIR */
+#define IFX_PSI5S_INTOV_RIR_OFF (10u)
+
+/** \brief Length for Ifx_PSI5S_INTOV_Bits.RSI */
+#define IFX_PSI5S_INTOV_RSI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTOV_Bits.RSI */
+#define IFX_PSI5S_INTOV_RSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTOV_Bits.RSI */
+#define IFX_PSI5S_INTOV_RSI_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_INTOV_Bits.TBIR */
+#define IFX_PSI5S_INTOV_TBIR_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTOV_Bits.TBIR */
+#define IFX_PSI5S_INTOV_TBIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTOV_Bits.TBIR */
+#define IFX_PSI5S_INTOV_TBIR_OFF (12u)
+
+/** \brief Length for Ifx_PSI5S_INTOV_Bits.TEI */
+#define IFX_PSI5S_INTOV_TEI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTOV_Bits.TEI */
+#define IFX_PSI5S_INTOV_TEI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTOV_Bits.TEI */
+#define IFX_PSI5S_INTOV_TEI_OFF (3u)
+
+/** \brief Length for Ifx_PSI5S_INTOV_Bits.TIR */
+#define IFX_PSI5S_INTOV_TIR_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTOV_Bits.TIR */
+#define IFX_PSI5S_INTOV_TIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTOV_Bits.TIR */
+#define IFX_PSI5S_INTOV_TIR_OFF (9u)
+
+/** \brief Length for Ifx_PSI5S_INTOV_Bits.TPI */
+#define IFX_PSI5S_INTOV_TPI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTOV_Bits.TPI */
+#define IFX_PSI5S_INTOV_TPI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTOV_Bits.TPI */
+#define IFX_PSI5S_INTOV_TPI_OFF (6u)
+
+/** \brief Length for Ifx_PSI5S_INTOV_Bits.TPOI */
+#define IFX_PSI5S_INTOV_TPOI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTOV_Bits.TPOI */
+#define IFX_PSI5S_INTOV_TPOI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTOV_Bits.TPOI */
+#define IFX_PSI5S_INTOV_TPOI_OFF (7u)
+
+/** \brief Length for Ifx_PSI5S_INTOV_Bits.XCRCI */
+#define IFX_PSI5S_INTOV_XCRCI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTOV_Bits.XCRCI */
+#define IFX_PSI5S_INTOV_XCRCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTOV_Bits.XCRCI */
+#define IFX_PSI5S_INTOV_XCRCI_OFF (13u)
+
+/** \brief Length for Ifx_PSI5S_INTSET_Bits.CHCI */
+#define IFX_PSI5S_INTSET_CHCI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTSET_Bits.CHCI */
+#define IFX_PSI5S_INTSET_CHCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTSET_Bits.CHCI */
+#define IFX_PSI5S_INTSET_CHCI_OFF (4u)
+
+/** \brief Length for Ifx_PSI5S_INTSET_Bits.CRCI */
+#define IFX_PSI5S_INTSET_CRCI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTSET_Bits.CRCI */
+#define IFX_PSI5S_INTSET_CRCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTSET_Bits.CRCI */
+#define IFX_PSI5S_INTSET_CRCI_OFF (5u)
+
+/** \brief Length for Ifx_PSI5S_INTSET_Bits.HDI */
+#define IFX_PSI5S_INTSET_HDI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTSET_Bits.HDI */
+#define IFX_PSI5S_INTSET_HDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTSET_Bits.HDI */
+#define IFX_PSI5S_INTSET_HDI_OFF (8u)
+
+/** \brief Length for Ifx_PSI5S_INTSET_Bits.RBI */
+#define IFX_PSI5S_INTSET_RBI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTSET_Bits.RBI */
+#define IFX_PSI5S_INTSET_RBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTSET_Bits.RBI */
+#define IFX_PSI5S_INTSET_RBI_OFF (2u)
+
+/** \brief Length for Ifx_PSI5S_INTSET_Bits.RDI */
+#define IFX_PSI5S_INTSET_RDI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTSET_Bits.RDI */
+#define IFX_PSI5S_INTSET_RDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTSET_Bits.RDI */
+#define IFX_PSI5S_INTSET_RDI_OFF (1u)
+
+/** \brief Length for Ifx_PSI5S_INTSET_Bits.RSI */
+#define IFX_PSI5S_INTSET_RSI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTSET_Bits.RSI */
+#define IFX_PSI5S_INTSET_RSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTSET_Bits.RSI */
+#define IFX_PSI5S_INTSET_RSI_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_INTSET_Bits.TEI */
+#define IFX_PSI5S_INTSET_TEI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTSET_Bits.TEI */
+#define IFX_PSI5S_INTSET_TEI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTSET_Bits.TEI */
+#define IFX_PSI5S_INTSET_TEI_OFF (3u)
+
+/** \brief Length for Ifx_PSI5S_INTSET_Bits.TPI */
+#define IFX_PSI5S_INTSET_TPI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTSET_Bits.TPI */
+#define IFX_PSI5S_INTSET_TPI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTSET_Bits.TPI */
+#define IFX_PSI5S_INTSET_TPI_OFF (6u)
+
+/** \brief Length for Ifx_PSI5S_INTSET_Bits.TPOI */
+#define IFX_PSI5S_INTSET_TPOI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTSET_Bits.TPOI */
+#define IFX_PSI5S_INTSET_TPOI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTSET_Bits.TPOI */
+#define IFX_PSI5S_INTSET_TPOI_OFF (7u)
+
+/** \brief Length for Ifx_PSI5S_INTSETG_Bits.EIR */
+#define IFX_PSI5S_INTSETG_EIR_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTSETG_Bits.EIR */
+#define IFX_PSI5S_INTSETG_EIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTSETG_Bits.EIR */
+#define IFX_PSI5S_INTSETG_EIR_OFF (2u)
+
+/** \brief Length for Ifx_PSI5S_INTSETG_Bits.FOI */
+#define IFX_PSI5S_INTSETG_FOI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTSETG_Bits.FOI */
+#define IFX_PSI5S_INTSETG_FOI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTSETG_Bits.FOI */
+#define IFX_PSI5S_INTSETG_FOI_OFF (5u)
+
+/** \brief Length for Ifx_PSI5S_INTSETG_Bits.RIR */
+#define IFX_PSI5S_INTSETG_RIR_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTSETG_Bits.RIR */
+#define IFX_PSI5S_INTSETG_RIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTSETG_Bits.RIR */
+#define IFX_PSI5S_INTSETG_RIR_OFF (1u)
+
+/** \brief Length for Ifx_PSI5S_INTSETG_Bits.TBIR */
+#define IFX_PSI5S_INTSETG_TBIR_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTSETG_Bits.TBIR */
+#define IFX_PSI5S_INTSETG_TBIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTSETG_Bits.TBIR */
+#define IFX_PSI5S_INTSETG_TBIR_OFF (3u)
+
+/** \brief Length for Ifx_PSI5S_INTSETG_Bits.TIR */
+#define IFX_PSI5S_INTSETG_TIR_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTSETG_Bits.TIR */
+#define IFX_PSI5S_INTSETG_TIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTSETG_Bits.TIR */
+#define IFX_PSI5S_INTSETG_TIR_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_INTSETG_Bits.XCRCI */
+#define IFX_PSI5S_INTSETG_XCRCI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTSETG_Bits.XCRCI */
+#define IFX_PSI5S_INTSETG_XCRCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTSETG_Bits.XCRCI */
+#define IFX_PSI5S_INTSETG_XCRCI_OFF (4u)
+
+/** \brief Length for Ifx_PSI5S_INTSTAT_Bits.CHCI */
+#define IFX_PSI5S_INTSTAT_CHCI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTSTAT_Bits.CHCI */
+#define IFX_PSI5S_INTSTAT_CHCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTSTAT_Bits.CHCI */
+#define IFX_PSI5S_INTSTAT_CHCI_OFF (4u)
+
+/** \brief Length for Ifx_PSI5S_INTSTAT_Bits.CRCI */
+#define IFX_PSI5S_INTSTAT_CRCI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTSTAT_Bits.CRCI */
+#define IFX_PSI5S_INTSTAT_CRCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTSTAT_Bits.CRCI */
+#define IFX_PSI5S_INTSTAT_CRCI_OFF (5u)
+
+/** \brief Length for Ifx_PSI5S_INTSTAT_Bits.HDI */
+#define IFX_PSI5S_INTSTAT_HDI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTSTAT_Bits.HDI */
+#define IFX_PSI5S_INTSTAT_HDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTSTAT_Bits.HDI */
+#define IFX_PSI5S_INTSTAT_HDI_OFF (8u)
+
+/** \brief Length for Ifx_PSI5S_INTSTAT_Bits.RBI */
+#define IFX_PSI5S_INTSTAT_RBI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTSTAT_Bits.RBI */
+#define IFX_PSI5S_INTSTAT_RBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTSTAT_Bits.RBI */
+#define IFX_PSI5S_INTSTAT_RBI_OFF (2u)
+
+/** \brief Length for Ifx_PSI5S_INTSTAT_Bits.RDI */
+#define IFX_PSI5S_INTSTAT_RDI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTSTAT_Bits.RDI */
+#define IFX_PSI5S_INTSTAT_RDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTSTAT_Bits.RDI */
+#define IFX_PSI5S_INTSTAT_RDI_OFF (1u)
+
+/** \brief Length for Ifx_PSI5S_INTSTAT_Bits.RSI */
+#define IFX_PSI5S_INTSTAT_RSI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTSTAT_Bits.RSI */
+#define IFX_PSI5S_INTSTAT_RSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTSTAT_Bits.RSI */
+#define IFX_PSI5S_INTSTAT_RSI_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_INTSTAT_Bits.TEI */
+#define IFX_PSI5S_INTSTAT_TEI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTSTAT_Bits.TEI */
+#define IFX_PSI5S_INTSTAT_TEI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTSTAT_Bits.TEI */
+#define IFX_PSI5S_INTSTAT_TEI_OFF (3u)
+
+/** \brief Length for Ifx_PSI5S_INTSTAT_Bits.TPI */
+#define IFX_PSI5S_INTSTAT_TPI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTSTAT_Bits.TPI */
+#define IFX_PSI5S_INTSTAT_TPI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTSTAT_Bits.TPI */
+#define IFX_PSI5S_INTSTAT_TPI_OFF (6u)
+
+/** \brief Length for Ifx_PSI5S_INTSTAT_Bits.TPOI */
+#define IFX_PSI5S_INTSTAT_TPOI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTSTAT_Bits.TPOI */
+#define IFX_PSI5S_INTSTAT_TPOI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTSTAT_Bits.TPOI */
+#define IFX_PSI5S_INTSTAT_TPOI_OFF (7u)
+
+/** \brief Length for Ifx_PSI5S_INTSTATG_Bits.EIR */
+#define IFX_PSI5S_INTSTATG_EIR_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTSTATG_Bits.EIR */
+#define IFX_PSI5S_INTSTATG_EIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTSTATG_Bits.EIR */
+#define IFX_PSI5S_INTSTATG_EIR_OFF (2u)
+
+/** \brief Length for Ifx_PSI5S_INTSTATG_Bits.FOI */
+#define IFX_PSI5S_INTSTATG_FOI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTSTATG_Bits.FOI */
+#define IFX_PSI5S_INTSTATG_FOI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTSTATG_Bits.FOI */
+#define IFX_PSI5S_INTSTATG_FOI_OFF (5u)
+
+/** \brief Length for Ifx_PSI5S_INTSTATG_Bits.RIR */
+#define IFX_PSI5S_INTSTATG_RIR_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTSTATG_Bits.RIR */
+#define IFX_PSI5S_INTSTATG_RIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTSTATG_Bits.RIR */
+#define IFX_PSI5S_INTSTATG_RIR_OFF (1u)
+
+/** \brief Length for Ifx_PSI5S_INTSTATG_Bits.TBIR */
+#define IFX_PSI5S_INTSTATG_TBIR_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTSTATG_Bits.TBIR */
+#define IFX_PSI5S_INTSTATG_TBIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTSTATG_Bits.TBIR */
+#define IFX_PSI5S_INTSTATG_TBIR_OFF (3u)
+
+/** \brief Length for Ifx_PSI5S_INTSTATG_Bits.TIR */
+#define IFX_PSI5S_INTSTATG_TIR_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTSTATG_Bits.TIR */
+#define IFX_PSI5S_INTSTATG_TIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTSTATG_Bits.TIR */
+#define IFX_PSI5S_INTSTATG_TIR_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_INTSTATG_Bits.XCRCI */
+#define IFX_PSI5S_INTSTATG_XCRCI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_INTSTATG_Bits.XCRCI */
+#define IFX_PSI5S_INTSTATG_XCRCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_INTSTATG_Bits.XCRCI */
+#define IFX_PSI5S_INTSTATG_XCRCI_OFF (4u)
+
+/** \brief Length for Ifx_PSI5S_IOCR_Bits.ALTI */
+#define IFX_PSI5S_IOCR_ALTI_LEN (2u)
+
+/** \brief Mask for Ifx_PSI5S_IOCR_Bits.ALTI */
+#define IFX_PSI5S_IOCR_ALTI_MSK (0x3u)
+
+/** \brief Offset for Ifx_PSI5S_IOCR_Bits.ALTI */
+#define IFX_PSI5S_IOCR_ALTI_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_KRST0_Bits.RST */
+#define IFX_PSI5S_KRST0_RST_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_KRST0_Bits.RST */
+#define IFX_PSI5S_KRST0_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_KRST0_Bits.RST */
+#define IFX_PSI5S_KRST0_RST_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_KRST0_Bits.RSTSTAT */
+#define IFX_PSI5S_KRST0_RSTSTAT_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_KRST0_Bits.RSTSTAT */
+#define IFX_PSI5S_KRST0_RSTSTAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_KRST0_Bits.RSTSTAT */
+#define IFX_PSI5S_KRST0_RSTSTAT_OFF (1u)
+
+/** \brief Length for Ifx_PSI5S_KRST1_Bits.RST */
+#define IFX_PSI5S_KRST1_RST_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_KRST1_Bits.RST */
+#define IFX_PSI5S_KRST1_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_KRST1_Bits.RST */
+#define IFX_PSI5S_KRST1_RST_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_KRSTCLR_Bits.CLR */
+#define IFX_PSI5S_KRSTCLR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_KRSTCLR_Bits.CLR */
+#define IFX_PSI5S_KRSTCLR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_KRSTCLR_Bits.CLR */
+#define IFX_PSI5S_KRSTCLR_CLR_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_NFC_Bits.NF0 */
+#define IFX_PSI5S_NFC_NF0_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_NFC_Bits.NF0 */
+#define IFX_PSI5S_NFC_NF0_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_NFC_Bits.NF0 */
+#define IFX_PSI5S_NFC_NF0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_NFC_Bits.NF1 */
+#define IFX_PSI5S_NFC_NF1_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_NFC_Bits.NF1 */
+#define IFX_PSI5S_NFC_NF1_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_NFC_Bits.NF1 */
+#define IFX_PSI5S_NFC_NF1_OFF (3u)
+
+/** \brief Length for Ifx_PSI5S_NFC_Bits.NF2 */
+#define IFX_PSI5S_NFC_NF2_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_NFC_Bits.NF2 */
+#define IFX_PSI5S_NFC_NF2_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_NFC_Bits.NF2 */
+#define IFX_PSI5S_NFC_NF2_OFF (6u)
+
+/** \brief Length for Ifx_PSI5S_NFC_Bits.NF3 */
+#define IFX_PSI5S_NFC_NF3_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_NFC_Bits.NF3 */
+#define IFX_PSI5S_NFC_NF3_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_NFC_Bits.NF3 */
+#define IFX_PSI5S_NFC_NF3_OFF (9u)
+
+/** \brief Length for Ifx_PSI5S_NFC_Bits.NF4 */
+#define IFX_PSI5S_NFC_NF4_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_NFC_Bits.NF4 */
+#define IFX_PSI5S_NFC_NF4_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_NFC_Bits.NF4 */
+#define IFX_PSI5S_NFC_NF4_OFF (12u)
+
+/** \brief Length for Ifx_PSI5S_NFC_Bits.NF5 */
+#define IFX_PSI5S_NFC_NF5_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_NFC_Bits.NF5 */
+#define IFX_PSI5S_NFC_NF5_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_NFC_Bits.NF5 */
+#define IFX_PSI5S_NFC_NF5_OFF (15u)
+
+/** \brief Length for Ifx_PSI5S_NFC_Bits.NF6 */
+#define IFX_PSI5S_NFC_NF6_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_NFC_Bits.NF6 */
+#define IFX_PSI5S_NFC_NF6_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_NFC_Bits.NF6 */
+#define IFX_PSI5S_NFC_NF6_OFF (18u)
+
+/** \brief Length for Ifx_PSI5S_NFC_Bits.NF7 */
+#define IFX_PSI5S_NFC_NF7_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_NFC_Bits.NF7 */
+#define IFX_PSI5S_NFC_NF7_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_NFC_Bits.NF7 */
+#define IFX_PSI5S_NFC_NF7_OFF (21u)
+
+/** \brief Length for Ifx_PSI5S_OCS_Bits.SUS */
+#define IFX_PSI5S_OCS_SUS_LEN (4u)
+
+/** \brief Mask for Ifx_PSI5S_OCS_Bits.SUS */
+#define IFX_PSI5S_OCS_SUS_MSK (0xfu)
+
+/** \brief Offset for Ifx_PSI5S_OCS_Bits.SUS */
+#define IFX_PSI5S_OCS_SUS_OFF (24u)
+
+/** \brief Length for Ifx_PSI5S_OCS_Bits.SUS_P */
+#define IFX_PSI5S_OCS_SUS_P_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_OCS_Bits.SUS_P */
+#define IFX_PSI5S_OCS_SUS_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_OCS_Bits.SUS_P */
+#define IFX_PSI5S_OCS_SUS_P_OFF (28u)
+
+/** \brief Length for Ifx_PSI5S_OCS_Bits.SUSSTA */
+#define IFX_PSI5S_OCS_SUSSTA_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_OCS_Bits.SUSSTA */
+#define IFX_PSI5S_OCS_SUSSTA_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_OCS_Bits.SUSSTA */
+#define IFX_PSI5S_OCS_SUSSTA_OFF (29u)
+
+/** \brief Length for Ifx_PSI5S_PGC_Bits.ATXCMD */
+#define IFX_PSI5S_PGC_ATXCMD_LEN (5u)
+
+/** \brief Mask for Ifx_PSI5S_PGC_Bits.ATXCMD */
+#define IFX_PSI5S_PGC_ATXCMD_MSK (0x1fu)
+
+/** \brief Offset for Ifx_PSI5S_PGC_Bits.ATXCMD */
+#define IFX_PSI5S_PGC_ATXCMD_OFF (8u)
+
+/** \brief Length for Ifx_PSI5S_PGC_Bits.ETB */
+#define IFX_PSI5S_PGC_ETB_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_PGC_Bits.ETB */
+#define IFX_PSI5S_PGC_ETB_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_PGC_Bits.ETB */
+#define IFX_PSI5S_PGC_ETB_OFF (16u)
+
+/** \brief Length for Ifx_PSI5S_PGC_Bits.ETE */
+#define IFX_PSI5S_PGC_ETE_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_PGC_Bits.ETE */
+#define IFX_PSI5S_PGC_ETE_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_PGC_Bits.ETE */
+#define IFX_PSI5S_PGC_ETE_OFF (23u)
+
+/** \brief Length for Ifx_PSI5S_PGC_Bits.ETS */
+#define IFX_PSI5S_PGC_ETS_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_PGC_Bits.ETS */
+#define IFX_PSI5S_PGC_ETS_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_PGC_Bits.ETS */
+#define IFX_PSI5S_PGC_ETS_OFF (20u)
+
+/** \brief Length for Ifx_PSI5S_PGC_Bits.PTE */
+#define IFX_PSI5S_PGC_PTE_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_PGC_Bits.PTE */
+#define IFX_PSI5S_PGC_PTE_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_PGC_Bits.PTE */
+#define IFX_PSI5S_PGC_PTE_OFF (19u)
+
+/** \brief Length for Ifx_PSI5S_PGC_Bits.TBS */
+#define IFX_PSI5S_PGC_TBS_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_PGC_Bits.TBS */
+#define IFX_PSI5S_PGC_TBS_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_PGC_Bits.TBS */
+#define IFX_PSI5S_PGC_TBS_OFF (15u)
+
+/** \brief Length for Ifx_PSI5S_PGC_Bits.TXCMD */
+#define IFX_PSI5S_PGC_TXCMD_LEN (5u)
+
+/** \brief Mask for Ifx_PSI5S_PGC_Bits.TXCMD */
+#define IFX_PSI5S_PGC_TXCMD_MSK (0x1fu)
+
+/** \brief Offset for Ifx_PSI5S_PGC_Bits.TXCMD */
+#define IFX_PSI5S_PGC_TXCMD_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_RBUF_Bits.RD_VALUE */
+#define IFX_PSI5S_RBUF_RD_VALUE_LEN (9u)
+
+/** \brief Mask for Ifx_PSI5S_RBUF_Bits.RD_VALUE */
+#define IFX_PSI5S_RBUF_RD_VALUE_MSK (0x1ffu)
+
+/** \brief Offset for Ifx_PSI5S_RBUF_Bits.RD_VALUE */
+#define IFX_PSI5S_RBUF_RD_VALUE_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_RCRA_Bits.CRC0 */
+#define IFX_PSI5S_RCRA_CRC0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RCRA_Bits.CRC0 */
+#define IFX_PSI5S_RCRA_CRC0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RCRA_Bits.CRC0 */
+#define IFX_PSI5S_RCRA_CRC0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_RCRA_Bits.CRC1 */
+#define IFX_PSI5S_RCRA_CRC1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RCRA_Bits.CRC1 */
+#define IFX_PSI5S_RCRA_CRC1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RCRA_Bits.CRC1 */
+#define IFX_PSI5S_RCRA_CRC1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5S_RCRA_Bits.CRC2 */
+#define IFX_PSI5S_RCRA_CRC2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RCRA_Bits.CRC2 */
+#define IFX_PSI5S_RCRA_CRC2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RCRA_Bits.CRC2 */
+#define IFX_PSI5S_RCRA_CRC2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5S_RCRA_Bits.CRC3 */
+#define IFX_PSI5S_RCRA_CRC3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RCRA_Bits.CRC3 */
+#define IFX_PSI5S_RCRA_CRC3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RCRA_Bits.CRC3 */
+#define IFX_PSI5S_RCRA_CRC3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5S_RCRA_Bits.CRC4 */
+#define IFX_PSI5S_RCRA_CRC4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RCRA_Bits.CRC4 */
+#define IFX_PSI5S_RCRA_CRC4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RCRA_Bits.CRC4 */
+#define IFX_PSI5S_RCRA_CRC4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5S_RCRA_Bits.CRC5 */
+#define IFX_PSI5S_RCRA_CRC5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RCRA_Bits.CRC5 */
+#define IFX_PSI5S_RCRA_CRC5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RCRA_Bits.CRC5 */
+#define IFX_PSI5S_RCRA_CRC5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5S_RCRA_Bits.FIDS */
+#define IFX_PSI5S_RCRA_FIDS_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RCRA_Bits.FIDS */
+#define IFX_PSI5S_RCRA_FIDS_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RCRA_Bits.FIDS */
+#define IFX_PSI5S_RCRA_FIDS_OFF (9u)
+
+/** \brief Length for Ifx_PSI5S_RCRA_Bits.TSEN */
+#define IFX_PSI5S_RCRA_TSEN_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RCRA_Bits.TSEN */
+#define IFX_PSI5S_RCRA_TSEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RCRA_Bits.TSEN */
+#define IFX_PSI5S_RCRA_TSEN_OFF (6u)
+
+/** \brief Length for Ifx_PSI5S_RCRA_Bits.TSP */
+#define IFX_PSI5S_RCRA_TSP_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RCRA_Bits.TSP */
+#define IFX_PSI5S_RCRA_TSP_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RCRA_Bits.TSP */
+#define IFX_PSI5S_RCRA_TSP_OFF (7u)
+
+/** \brief Length for Ifx_PSI5S_RCRA_Bits.TSTS */
+#define IFX_PSI5S_RCRA_TSTS_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RCRA_Bits.TSTS */
+#define IFX_PSI5S_RCRA_TSTS_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RCRA_Bits.TSTS */
+#define IFX_PSI5S_RCRA_TSTS_OFF (8u)
+
+/** \brief Length for Ifx_PSI5S_RCRA_Bits.UFC0 */
+#define IFX_PSI5S_RCRA_UFC0_LEN (2u)
+
+/** \brief Mask for Ifx_PSI5S_RCRA_Bits.UFC0 */
+#define IFX_PSI5S_RCRA_UFC0_MSK (0x3u)
+
+/** \brief Offset for Ifx_PSI5S_RCRA_Bits.UFC0 */
+#define IFX_PSI5S_RCRA_UFC0_OFF (16u)
+
+/** \brief Length for Ifx_PSI5S_RCRA_Bits.UFC1 */
+#define IFX_PSI5S_RCRA_UFC1_LEN (2u)
+
+/** \brief Mask for Ifx_PSI5S_RCRA_Bits.UFC1 */
+#define IFX_PSI5S_RCRA_UFC1_MSK (0x3u)
+
+/** \brief Offset for Ifx_PSI5S_RCRA_Bits.UFC1 */
+#define IFX_PSI5S_RCRA_UFC1_OFF (18u)
+
+/** \brief Length for Ifx_PSI5S_RCRA_Bits.UFC2 */
+#define IFX_PSI5S_RCRA_UFC2_LEN (2u)
+
+/** \brief Mask for Ifx_PSI5S_RCRA_Bits.UFC2 */
+#define IFX_PSI5S_RCRA_UFC2_MSK (0x3u)
+
+/** \brief Offset for Ifx_PSI5S_RCRA_Bits.UFC2 */
+#define IFX_PSI5S_RCRA_UFC2_OFF (20u)
+
+/** \brief Length for Ifx_PSI5S_RCRA_Bits.UFC3 */
+#define IFX_PSI5S_RCRA_UFC3_LEN (2u)
+
+/** \brief Mask for Ifx_PSI5S_RCRA_Bits.UFC3 */
+#define IFX_PSI5S_RCRA_UFC3_MSK (0x3u)
+
+/** \brief Offset for Ifx_PSI5S_RCRA_Bits.UFC3 */
+#define IFX_PSI5S_RCRA_UFC3_OFF (22u)
+
+/** \brief Length for Ifx_PSI5S_RCRA_Bits.UFC4 */
+#define IFX_PSI5S_RCRA_UFC4_LEN (2u)
+
+/** \brief Mask for Ifx_PSI5S_RCRA_Bits.UFC4 */
+#define IFX_PSI5S_RCRA_UFC4_MSK (0x3u)
+
+/** \brief Offset for Ifx_PSI5S_RCRA_Bits.UFC4 */
+#define IFX_PSI5S_RCRA_UFC4_OFF (24u)
+
+/** \brief Length for Ifx_PSI5S_RCRA_Bits.UFC5 */
+#define IFX_PSI5S_RCRA_UFC5_LEN (2u)
+
+/** \brief Mask for Ifx_PSI5S_RCRA_Bits.UFC5 */
+#define IFX_PSI5S_RCRA_UFC5_MSK (0x3u)
+
+/** \brief Offset for Ifx_PSI5S_RCRA_Bits.UFC5 */
+#define IFX_PSI5S_RCRA_UFC5_OFF (26u)
+
+/** \brief Length for Ifx_PSI5S_RCRA_Bits.WDMS */
+#define IFX_PSI5S_RCRA_WDMS_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RCRA_Bits.WDMS */
+#define IFX_PSI5S_RCRA_WDMS_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RCRA_Bits.WDMS */
+#define IFX_PSI5S_RCRA_WDMS_OFF (10u)
+
+/** \brief Length for Ifx_PSI5S_RCRB_Bits.PDL0 */
+#define IFX_PSI5S_RCRB_PDL0_LEN (5u)
+
+/** \brief Mask for Ifx_PSI5S_RCRB_Bits.PDL0 */
+#define IFX_PSI5S_RCRB_PDL0_MSK (0x1fu)
+
+/** \brief Offset for Ifx_PSI5S_RCRB_Bits.PDL0 */
+#define IFX_PSI5S_RCRB_PDL0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_RCRB_Bits.PDL1 */
+#define IFX_PSI5S_RCRB_PDL1_LEN (5u)
+
+/** \brief Mask for Ifx_PSI5S_RCRB_Bits.PDL1 */
+#define IFX_PSI5S_RCRB_PDL1_MSK (0x1fu)
+
+/** \brief Offset for Ifx_PSI5S_RCRB_Bits.PDL1 */
+#define IFX_PSI5S_RCRB_PDL1_OFF (5u)
+
+/** \brief Length for Ifx_PSI5S_RCRB_Bits.PDL2 */
+#define IFX_PSI5S_RCRB_PDL2_LEN (5u)
+
+/** \brief Mask for Ifx_PSI5S_RCRB_Bits.PDL2 */
+#define IFX_PSI5S_RCRB_PDL2_MSK (0x1fu)
+
+/** \brief Offset for Ifx_PSI5S_RCRB_Bits.PDL2 */
+#define IFX_PSI5S_RCRB_PDL2_OFF (10u)
+
+/** \brief Length for Ifx_PSI5S_RCRB_Bits.PDL3 */
+#define IFX_PSI5S_RCRB_PDL3_LEN (5u)
+
+/** \brief Mask for Ifx_PSI5S_RCRB_Bits.PDL3 */
+#define IFX_PSI5S_RCRB_PDL3_MSK (0x1fu)
+
+/** \brief Offset for Ifx_PSI5S_RCRB_Bits.PDL3 */
+#define IFX_PSI5S_RCRB_PDL3_OFF (15u)
+
+/** \brief Length for Ifx_PSI5S_RCRB_Bits.PDL4 */
+#define IFX_PSI5S_RCRB_PDL4_LEN (5u)
+
+/** \brief Mask for Ifx_PSI5S_RCRB_Bits.PDL4 */
+#define IFX_PSI5S_RCRB_PDL4_MSK (0x1fu)
+
+/** \brief Offset for Ifx_PSI5S_RCRB_Bits.PDL4 */
+#define IFX_PSI5S_RCRB_PDL4_OFF (20u)
+
+/** \brief Length for Ifx_PSI5S_RCRB_Bits.PDL5 */
+#define IFX_PSI5S_RCRB_PDL5_LEN (5u)
+
+/** \brief Mask for Ifx_PSI5S_RCRB_Bits.PDL5 */
+#define IFX_PSI5S_RCRB_PDL5_MSK (0x1fu)
+
+/** \brief Offset for Ifx_PSI5S_RCRB_Bits.PDL5 */
+#define IFX_PSI5S_RCRB_PDL5_OFF (25u)
+
+/** \brief Length for Ifx_PSI5S_RDR_Bits.PFC */
+#define IFX_PSI5S_RDR_PFC_LEN (4u)
+
+/** \brief Mask for Ifx_PSI5S_RDR_Bits.PFC */
+#define IFX_PSI5S_RDR_PFC_MSK (0xfu)
+
+/** \brief Offset for Ifx_PSI5S_RDR_Bits.PFC */
+#define IFX_PSI5S_RDR_PFC_OFF (28u)
+
+/** \brief Length for Ifx_PSI5S_RDR_Bits.RD0 */
+#define IFX_PSI5S_RDR_RD0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDR_Bits.RD0 */
+#define IFX_PSI5S_RDR_RD0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDR_Bits.RD0 */
+#define IFX_PSI5S_RDR_RD0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_RDR_Bits.RD10 */
+#define IFX_PSI5S_RDR_RD10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDR_Bits.RD10 */
+#define IFX_PSI5S_RDR_RD10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDR_Bits.RD10 */
+#define IFX_PSI5S_RDR_RD10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5S_RDR_Bits.RD11 */
+#define IFX_PSI5S_RDR_RD11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDR_Bits.RD11 */
+#define IFX_PSI5S_RDR_RD11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDR_Bits.RD11 */
+#define IFX_PSI5S_RDR_RD11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5S_RDR_Bits.RD12 */
+#define IFX_PSI5S_RDR_RD12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDR_Bits.RD12 */
+#define IFX_PSI5S_RDR_RD12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDR_Bits.RD12 */
+#define IFX_PSI5S_RDR_RD12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5S_RDR_Bits.RD13 */
+#define IFX_PSI5S_RDR_RD13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDR_Bits.RD13 */
+#define IFX_PSI5S_RDR_RD13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDR_Bits.RD13 */
+#define IFX_PSI5S_RDR_RD13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5S_RDR_Bits.RD14 */
+#define IFX_PSI5S_RDR_RD14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDR_Bits.RD14 */
+#define IFX_PSI5S_RDR_RD14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDR_Bits.RD14 */
+#define IFX_PSI5S_RDR_RD14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5S_RDR_Bits.RD15 */
+#define IFX_PSI5S_RDR_RD15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDR_Bits.RD15 */
+#define IFX_PSI5S_RDR_RD15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDR_Bits.RD15 */
+#define IFX_PSI5S_RDR_RD15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5S_RDR_Bits.RD16 */
+#define IFX_PSI5S_RDR_RD16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDR_Bits.RD16 */
+#define IFX_PSI5S_RDR_RD16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDR_Bits.RD16 */
+#define IFX_PSI5S_RDR_RD16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5S_RDR_Bits.RD17 */
+#define IFX_PSI5S_RDR_RD17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDR_Bits.RD17 */
+#define IFX_PSI5S_RDR_RD17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDR_Bits.RD17 */
+#define IFX_PSI5S_RDR_RD17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5S_RDR_Bits.RD18 */
+#define IFX_PSI5S_RDR_RD18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDR_Bits.RD18 */
+#define IFX_PSI5S_RDR_RD18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDR_Bits.RD18 */
+#define IFX_PSI5S_RDR_RD18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5S_RDR_Bits.RD19 */
+#define IFX_PSI5S_RDR_RD19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDR_Bits.RD19 */
+#define IFX_PSI5S_RDR_RD19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDR_Bits.RD19 */
+#define IFX_PSI5S_RDR_RD19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5S_RDR_Bits.RD1 */
+#define IFX_PSI5S_RDR_RD1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDR_Bits.RD1 */
+#define IFX_PSI5S_RDR_RD1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDR_Bits.RD1 */
+#define IFX_PSI5S_RDR_RD1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5S_RDR_Bits.RD20 */
+#define IFX_PSI5S_RDR_RD20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDR_Bits.RD20 */
+#define IFX_PSI5S_RDR_RD20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDR_Bits.RD20 */
+#define IFX_PSI5S_RDR_RD20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5S_RDR_Bits.RD21 */
+#define IFX_PSI5S_RDR_RD21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDR_Bits.RD21 */
+#define IFX_PSI5S_RDR_RD21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDR_Bits.RD21 */
+#define IFX_PSI5S_RDR_RD21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5S_RDR_Bits.RD22 */
+#define IFX_PSI5S_RDR_RD22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDR_Bits.RD22 */
+#define IFX_PSI5S_RDR_RD22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDR_Bits.RD22 */
+#define IFX_PSI5S_RDR_RD22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5S_RDR_Bits.RD23 */
+#define IFX_PSI5S_RDR_RD23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDR_Bits.RD23 */
+#define IFX_PSI5S_RDR_RD23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDR_Bits.RD23 */
+#define IFX_PSI5S_RDR_RD23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5S_RDR_Bits.RD24 */
+#define IFX_PSI5S_RDR_RD24_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDR_Bits.RD24 */
+#define IFX_PSI5S_RDR_RD24_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDR_Bits.RD24 */
+#define IFX_PSI5S_RDR_RD24_OFF (24u)
+
+/** \brief Length for Ifx_PSI5S_RDR_Bits.RD25 */
+#define IFX_PSI5S_RDR_RD25_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDR_Bits.RD25 */
+#define IFX_PSI5S_RDR_RD25_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDR_Bits.RD25 */
+#define IFX_PSI5S_RDR_RD25_OFF (25u)
+
+/** \brief Length for Ifx_PSI5S_RDR_Bits.RD26 */
+#define IFX_PSI5S_RDR_RD26_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDR_Bits.RD26 */
+#define IFX_PSI5S_RDR_RD26_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDR_Bits.RD26 */
+#define IFX_PSI5S_RDR_RD26_OFF (26u)
+
+/** \brief Length for Ifx_PSI5S_RDR_Bits.RD27 */
+#define IFX_PSI5S_RDR_RD27_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDR_Bits.RD27 */
+#define IFX_PSI5S_RDR_RD27_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDR_Bits.RD27 */
+#define IFX_PSI5S_RDR_RD27_OFF (27u)
+
+/** \brief Length for Ifx_PSI5S_RDR_Bits.RD2 */
+#define IFX_PSI5S_RDR_RD2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDR_Bits.RD2 */
+#define IFX_PSI5S_RDR_RD2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDR_Bits.RD2 */
+#define IFX_PSI5S_RDR_RD2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5S_RDR_Bits.RD3 */
+#define IFX_PSI5S_RDR_RD3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDR_Bits.RD3 */
+#define IFX_PSI5S_RDR_RD3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDR_Bits.RD3 */
+#define IFX_PSI5S_RDR_RD3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5S_RDR_Bits.RD4 */
+#define IFX_PSI5S_RDR_RD4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDR_Bits.RD4 */
+#define IFX_PSI5S_RDR_RD4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDR_Bits.RD4 */
+#define IFX_PSI5S_RDR_RD4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5S_RDR_Bits.RD5 */
+#define IFX_PSI5S_RDR_RD5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDR_Bits.RD5 */
+#define IFX_PSI5S_RDR_RD5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDR_Bits.RD5 */
+#define IFX_PSI5S_RDR_RD5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5S_RDR_Bits.RD6 */
+#define IFX_PSI5S_RDR_RD6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDR_Bits.RD6 */
+#define IFX_PSI5S_RDR_RD6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDR_Bits.RD6 */
+#define IFX_PSI5S_RDR_RD6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5S_RDR_Bits.RD7 */
+#define IFX_PSI5S_RDR_RD7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDR_Bits.RD7 */
+#define IFX_PSI5S_RDR_RD7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDR_Bits.RD7 */
+#define IFX_PSI5S_RDR_RD7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5S_RDR_Bits.RD8 */
+#define IFX_PSI5S_RDR_RD8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDR_Bits.RD8 */
+#define IFX_PSI5S_RDR_RD8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDR_Bits.RD8 */
+#define IFX_PSI5S_RDR_RD8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5S_RDR_Bits.RD9 */
+#define IFX_PSI5S_RDR_RD9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDR_Bits.RD9 */
+#define IFX_PSI5S_RDR_RD9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDR_Bits.RD9 */
+#define IFX_PSI5S_RDR_RD9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5S_RDS_Bits.AFC */
+#define IFX_PSI5S_RDS_AFC_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_RDS_Bits.AFC */
+#define IFX_PSI5S_RDS_AFC_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_RDS_Bits.AFC */
+#define IFX_PSI5S_RDS_AFC_OFF (25u)
+
+/** \brief Length for Ifx_PSI5S_RDS_Bits.CID */
+#define IFX_PSI5S_RDS_CID_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_RDS_Bits.CID */
+#define IFX_PSI5S_RDS_CID_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_RDS_Bits.CID */
+#define IFX_PSI5S_RDS_CID_OFF (22u)
+
+/** \brief Length for Ifx_PSI5S_RDS_Bits.CRC0 */
+#define IFX_PSI5S_RDS_CRC0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDS_Bits.CRC0 */
+#define IFX_PSI5S_RDS_CRC0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDS_Bits.CRC0 */
+#define IFX_PSI5S_RDS_CRC0_OFF (7u)
+
+/** \brief Length for Ifx_PSI5S_RDS_Bits.CRC1 */
+#define IFX_PSI5S_RDS_CRC1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDS_Bits.CRC1 */
+#define IFX_PSI5S_RDS_CRC1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDS_Bits.CRC1 */
+#define IFX_PSI5S_RDS_CRC1_OFF (8u)
+
+/** \brief Length for Ifx_PSI5S_RDS_Bits.CRC2 */
+#define IFX_PSI5S_RDS_CRC2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDS_Bits.CRC2 */
+#define IFX_PSI5S_RDS_CRC2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDS_Bits.CRC2 */
+#define IFX_PSI5S_RDS_CRC2_OFF (9u)
+
+/** \brief Length for Ifx_PSI5S_RDS_Bits.CRCI */
+#define IFX_PSI5S_RDS_CRCI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDS_Bits.CRCI */
+#define IFX_PSI5S_RDS_CRCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDS_Bits.CRCI */
+#define IFX_PSI5S_RDS_CRCI_OFF (10u)
+
+/** \brief Length for Ifx_PSI5S_RDS_Bits.ERR0 */
+#define IFX_PSI5S_RDS_ERR0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDS_Bits.ERR0 */
+#define IFX_PSI5S_RDS_ERR0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDS_Bits.ERR0 */
+#define IFX_PSI5S_RDS_ERR0_OFF (11u)
+
+/** \brief Length for Ifx_PSI5S_RDS_Bits.ERR1 */
+#define IFX_PSI5S_RDS_ERR1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDS_Bits.ERR1 */
+#define IFX_PSI5S_RDS_ERR1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDS_Bits.ERR1 */
+#define IFX_PSI5S_RDS_ERR1_OFF (12u)
+
+/** \brief Length for Ifx_PSI5S_RDS_Bits.FE */
+#define IFX_PSI5S_RDS_FE_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDS_Bits.FE */
+#define IFX_PSI5S_RDS_FE_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDS_Bits.FE */
+#define IFX_PSI5S_RDS_FE_OFF (15u)
+
+/** \brief Length for Ifx_PSI5S_RDS_Bits.FID */
+#define IFX_PSI5S_RDS_FID_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_RDS_Bits.FID */
+#define IFX_PSI5S_RDS_FID_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_RDS_Bits.FID */
+#define IFX_PSI5S_RDS_FID_OFF (19u)
+
+/** \brief Length for Ifx_PSI5S_RDS_Bits.HDI */
+#define IFX_PSI5S_RDS_HDI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDS_Bits.HDI */
+#define IFX_PSI5S_RDS_HDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDS_Bits.HDI */
+#define IFX_PSI5S_RDS_HDI_OFF (13u)
+
+/** \brief Length for Ifx_PSI5S_RDS_Bits.OE */
+#define IFX_PSI5S_RDS_OE_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDS_Bits.OE */
+#define IFX_PSI5S_RDS_OE_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDS_Bits.OE */
+#define IFX_PSI5S_RDS_OE_OFF (16u)
+
+/** \brief Length for Ifx_PSI5S_RDS_Bits.PE */
+#define IFX_PSI5S_RDS_PE_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDS_Bits.PE */
+#define IFX_PSI5S_RDS_PE_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDS_Bits.PE */
+#define IFX_PSI5S_RDS_PE_OFF (14u)
+
+/** \brief Length for Ifx_PSI5S_RDS_Bits.PFC */
+#define IFX_PSI5S_RDS_PFC_LEN (4u)
+
+/** \brief Mask for Ifx_PSI5S_RDS_Bits.PFC */
+#define IFX_PSI5S_RDS_PFC_MSK (0xfu)
+
+/** \brief Offset for Ifx_PSI5S_RDS_Bits.PFC */
+#define IFX_PSI5S_RDS_PFC_OFF (28u)
+
+/** \brief Length for Ifx_PSI5S_RDS_Bits.RBI */
+#define IFX_PSI5S_RDS_RBI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDS_Bits.RBI */
+#define IFX_PSI5S_RDS_RBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDS_Bits.RBI */
+#define IFX_PSI5S_RDS_RBI_OFF (18u)
+
+/** \brief Length for Ifx_PSI5S_RDS_Bits.TEI */
+#define IFX_PSI5S_RDS_TEI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDS_Bits.TEI */
+#define IFX_PSI5S_RDS_TEI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDS_Bits.TEI */
+#define IFX_PSI5S_RDS_TEI_OFF (17u)
+
+/** \brief Length for Ifx_PSI5S_RDS_Bits.XCRC0 */
+#define IFX_PSI5S_RDS_XCRC0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDS_Bits.XCRC0 */
+#define IFX_PSI5S_RDS_XCRC0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDS_Bits.XCRC0 */
+#define IFX_PSI5S_RDS_XCRC0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_RDS_Bits.XCRC1 */
+#define IFX_PSI5S_RDS_XCRC1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDS_Bits.XCRC1 */
+#define IFX_PSI5S_RDS_XCRC1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDS_Bits.XCRC1 */
+#define IFX_PSI5S_RDS_XCRC1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5S_RDS_Bits.XCRC2 */
+#define IFX_PSI5S_RDS_XCRC2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDS_Bits.XCRC2 */
+#define IFX_PSI5S_RDS_XCRC2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDS_Bits.XCRC2 */
+#define IFX_PSI5S_RDS_XCRC2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5S_RDS_Bits.XCRC3 */
+#define IFX_PSI5S_RDS_XCRC3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDS_Bits.XCRC3 */
+#define IFX_PSI5S_RDS_XCRC3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDS_Bits.XCRC3 */
+#define IFX_PSI5S_RDS_XCRC3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5S_RDS_Bits.XCRC4 */
+#define IFX_PSI5S_RDS_XCRC4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDS_Bits.XCRC4 */
+#define IFX_PSI5S_RDS_XCRC4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDS_Bits.XCRC4 */
+#define IFX_PSI5S_RDS_XCRC4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5S_RDS_Bits.XCRC5 */
+#define IFX_PSI5S_RDS_XCRC5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDS_Bits.XCRC5 */
+#define IFX_PSI5S_RDS_XCRC5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDS_Bits.XCRC5 */
+#define IFX_PSI5S_RDS_XCRC5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5S_RDS_Bits.XCRCI */
+#define IFX_PSI5S_RDS_XCRCI_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_RDS_Bits.XCRCI */
+#define IFX_PSI5S_RDS_XCRCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_RDS_Bits.XCRCI */
+#define IFX_PSI5S_RDS_XCRCI_OFF (6u)
+
+/** \brief Length for Ifx_PSI5S_SCR_Bits.BSC */
+#define IFX_PSI5S_SCR_BSC_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_SCR_Bits.BSC */
+#define IFX_PSI5S_SCR_BSC_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_SCR_Bits.BSC */
+#define IFX_PSI5S_SCR_BSC_OFF (8u)
+
+/** \brief Length for Ifx_PSI5S_SCR_Bits.CRC */
+#define IFX_PSI5S_SCR_CRC_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_SCR_Bits.CRC */
+#define IFX_PSI5S_SCR_CRC_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_SCR_Bits.CRC */
+#define IFX_PSI5S_SCR_CRC_OFF (22u)
+
+/** \brief Length for Ifx_PSI5S_SCR_Bits.EPS */
+#define IFX_PSI5S_SCR_EPS_LEN (2u)
+
+/** \brief Mask for Ifx_PSI5S_SCR_Bits.EPS */
+#define IFX_PSI5S_SCR_EPS_MSK (0x3u)
+
+/** \brief Offset for Ifx_PSI5S_SCR_Bits.EPS */
+#define IFX_PSI5S_SCR_EPS_OFF (6u)
+
+/** \brief Length for Ifx_PSI5S_SCR_Bits.FLUS */
+#define IFX_PSI5S_SCR_FLUS_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_SCR_Bits.FLUS */
+#define IFX_PSI5S_SCR_FLUS_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_SCR_Bits.FLUS */
+#define IFX_PSI5S_SCR_FLUS_OFF (14u)
+
+/** \brief Length for Ifx_PSI5S_SCR_Bits.PLL */
+#define IFX_PSI5S_SCR_PLL_LEN (5u)
+
+/** \brief Mask for Ifx_PSI5S_SCR_Bits.PLL */
+#define IFX_PSI5S_SCR_PLL_MSK (0x1fu)
+
+/** \brief Offset for Ifx_PSI5S_SCR_Bits.PLL */
+#define IFX_PSI5S_SCR_PLL_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_SCR_Bits.STA */
+#define IFX_PSI5S_SCR_STA_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_SCR_Bits.STA */
+#define IFX_PSI5S_SCR_STA_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_SCR_Bits.STA */
+#define IFX_PSI5S_SCR_STA_OFF (23u)
+
+/** \brief Length for Ifx_PSI5S_SCR_Bits.TPF */
+#define IFX_PSI5S_SCR_TPF_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_SCR_Bits.TPF */
+#define IFX_PSI5S_SCR_TPF_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_SCR_Bits.TPF */
+#define IFX_PSI5S_SCR_TPF_OFF (26u)
+
+/** \brief Length for Ifx_PSI5S_SDR_Bits.SD0 */
+#define IFX_PSI5S_SDR_SD0_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_SDR_Bits.SD0 */
+#define IFX_PSI5S_SDR_SD0_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_SDR_Bits.SD0 */
+#define IFX_PSI5S_SDR_SD0_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_SDR_Bits.SD10 */
+#define IFX_PSI5S_SDR_SD10_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_SDR_Bits.SD10 */
+#define IFX_PSI5S_SDR_SD10_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_SDR_Bits.SD10 */
+#define IFX_PSI5S_SDR_SD10_OFF (10u)
+
+/** \brief Length for Ifx_PSI5S_SDR_Bits.SD11 */
+#define IFX_PSI5S_SDR_SD11_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_SDR_Bits.SD11 */
+#define IFX_PSI5S_SDR_SD11_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_SDR_Bits.SD11 */
+#define IFX_PSI5S_SDR_SD11_OFF (11u)
+
+/** \brief Length for Ifx_PSI5S_SDR_Bits.SD12 */
+#define IFX_PSI5S_SDR_SD12_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_SDR_Bits.SD12 */
+#define IFX_PSI5S_SDR_SD12_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_SDR_Bits.SD12 */
+#define IFX_PSI5S_SDR_SD12_OFF (12u)
+
+/** \brief Length for Ifx_PSI5S_SDR_Bits.SD13 */
+#define IFX_PSI5S_SDR_SD13_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_SDR_Bits.SD13 */
+#define IFX_PSI5S_SDR_SD13_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_SDR_Bits.SD13 */
+#define IFX_PSI5S_SDR_SD13_OFF (13u)
+
+/** \brief Length for Ifx_PSI5S_SDR_Bits.SD14 */
+#define IFX_PSI5S_SDR_SD14_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_SDR_Bits.SD14 */
+#define IFX_PSI5S_SDR_SD14_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_SDR_Bits.SD14 */
+#define IFX_PSI5S_SDR_SD14_OFF (14u)
+
+/** \brief Length for Ifx_PSI5S_SDR_Bits.SD15 */
+#define IFX_PSI5S_SDR_SD15_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_SDR_Bits.SD15 */
+#define IFX_PSI5S_SDR_SD15_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_SDR_Bits.SD15 */
+#define IFX_PSI5S_SDR_SD15_OFF (15u)
+
+/** \brief Length for Ifx_PSI5S_SDR_Bits.SD16 */
+#define IFX_PSI5S_SDR_SD16_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_SDR_Bits.SD16 */
+#define IFX_PSI5S_SDR_SD16_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_SDR_Bits.SD16 */
+#define IFX_PSI5S_SDR_SD16_OFF (16u)
+
+/** \brief Length for Ifx_PSI5S_SDR_Bits.SD17 */
+#define IFX_PSI5S_SDR_SD17_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_SDR_Bits.SD17 */
+#define IFX_PSI5S_SDR_SD17_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_SDR_Bits.SD17 */
+#define IFX_PSI5S_SDR_SD17_OFF (17u)
+
+/** \brief Length for Ifx_PSI5S_SDR_Bits.SD18 */
+#define IFX_PSI5S_SDR_SD18_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_SDR_Bits.SD18 */
+#define IFX_PSI5S_SDR_SD18_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_SDR_Bits.SD18 */
+#define IFX_PSI5S_SDR_SD18_OFF (18u)
+
+/** \brief Length for Ifx_PSI5S_SDR_Bits.SD19 */
+#define IFX_PSI5S_SDR_SD19_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_SDR_Bits.SD19 */
+#define IFX_PSI5S_SDR_SD19_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_SDR_Bits.SD19 */
+#define IFX_PSI5S_SDR_SD19_OFF (19u)
+
+/** \brief Length for Ifx_PSI5S_SDR_Bits.SD1 */
+#define IFX_PSI5S_SDR_SD1_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_SDR_Bits.SD1 */
+#define IFX_PSI5S_SDR_SD1_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_SDR_Bits.SD1 */
+#define IFX_PSI5S_SDR_SD1_OFF (1u)
+
+/** \brief Length for Ifx_PSI5S_SDR_Bits.SD20 */
+#define IFX_PSI5S_SDR_SD20_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_SDR_Bits.SD20 */
+#define IFX_PSI5S_SDR_SD20_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_SDR_Bits.SD20 */
+#define IFX_PSI5S_SDR_SD20_OFF (20u)
+
+/** \brief Length for Ifx_PSI5S_SDR_Bits.SD21 */
+#define IFX_PSI5S_SDR_SD21_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_SDR_Bits.SD21 */
+#define IFX_PSI5S_SDR_SD21_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_SDR_Bits.SD21 */
+#define IFX_PSI5S_SDR_SD21_OFF (21u)
+
+/** \brief Length for Ifx_PSI5S_SDR_Bits.SD22 */
+#define IFX_PSI5S_SDR_SD22_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_SDR_Bits.SD22 */
+#define IFX_PSI5S_SDR_SD22_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_SDR_Bits.SD22 */
+#define IFX_PSI5S_SDR_SD22_OFF (22u)
+
+/** \brief Length for Ifx_PSI5S_SDR_Bits.SD23 */
+#define IFX_PSI5S_SDR_SD23_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_SDR_Bits.SD23 */
+#define IFX_PSI5S_SDR_SD23_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_SDR_Bits.SD23 */
+#define IFX_PSI5S_SDR_SD23_OFF (23u)
+
+/** \brief Length for Ifx_PSI5S_SDR_Bits.SD2 */
+#define IFX_PSI5S_SDR_SD2_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_SDR_Bits.SD2 */
+#define IFX_PSI5S_SDR_SD2_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_SDR_Bits.SD2 */
+#define IFX_PSI5S_SDR_SD2_OFF (2u)
+
+/** \brief Length for Ifx_PSI5S_SDR_Bits.SD3 */
+#define IFX_PSI5S_SDR_SD3_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_SDR_Bits.SD3 */
+#define IFX_PSI5S_SDR_SD3_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_SDR_Bits.SD3 */
+#define IFX_PSI5S_SDR_SD3_OFF (3u)
+
+/** \brief Length for Ifx_PSI5S_SDR_Bits.SD4 */
+#define IFX_PSI5S_SDR_SD4_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_SDR_Bits.SD4 */
+#define IFX_PSI5S_SDR_SD4_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_SDR_Bits.SD4 */
+#define IFX_PSI5S_SDR_SD4_OFF (4u)
+
+/** \brief Length for Ifx_PSI5S_SDR_Bits.SD5 */
+#define IFX_PSI5S_SDR_SD5_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_SDR_Bits.SD5 */
+#define IFX_PSI5S_SDR_SD5_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_SDR_Bits.SD5 */
+#define IFX_PSI5S_SDR_SD5_OFF (5u)
+
+/** \brief Length for Ifx_PSI5S_SDR_Bits.SD6 */
+#define IFX_PSI5S_SDR_SD6_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_SDR_Bits.SD6 */
+#define IFX_PSI5S_SDR_SD6_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_SDR_Bits.SD6 */
+#define IFX_PSI5S_SDR_SD6_OFF (6u)
+
+/** \brief Length for Ifx_PSI5S_SDR_Bits.SD7 */
+#define IFX_PSI5S_SDR_SD7_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_SDR_Bits.SD7 */
+#define IFX_PSI5S_SDR_SD7_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_SDR_Bits.SD7 */
+#define IFX_PSI5S_SDR_SD7_OFF (7u)
+
+/** \brief Length for Ifx_PSI5S_SDR_Bits.SD8 */
+#define IFX_PSI5S_SDR_SD8_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_SDR_Bits.SD8 */
+#define IFX_PSI5S_SDR_SD8_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_SDR_Bits.SD8 */
+#define IFX_PSI5S_SDR_SD8_OFF (8u)
+
+/** \brief Length for Ifx_PSI5S_SDR_Bits.SD9 */
+#define IFX_PSI5S_SDR_SD9_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_SDR_Bits.SD9 */
+#define IFX_PSI5S_SDR_SD9_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_SDR_Bits.SD9 */
+#define IFX_PSI5S_SDR_SD9_OFF (9u)
+
+/** \brief Length for Ifx_PSI5S_TAR_Bits.TA */
+#define IFX_PSI5S_TAR_TA_LEN (30u)
+
+/** \brief Mask for Ifx_PSI5S_TAR_Bits.TA */
+#define IFX_PSI5S_TAR_TA_MSK (0x3fffffffu)
+
+/** \brief Offset for Ifx_PSI5S_TAR_Bits.TA */
+#define IFX_PSI5S_TAR_TA_OFF (2u)
+
+/** \brief Length for Ifx_PSI5S_TBUF_Bits.TD_VALUE */
+#define IFX_PSI5S_TBUF_TD_VALUE_LEN (9u)
+
+/** \brief Mask for Ifx_PSI5S_TBUF_Bits.TD_VALUE */
+#define IFX_PSI5S_TBUF_TD_VALUE_MSK (0x1ffu)
+
+/** \brief Offset for Ifx_PSI5S_TBUF_Bits.TD_VALUE */
+#define IFX_PSI5S_TBUF_TD_VALUE_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_TSCNTA_Bits.CLRA */
+#define IFX_PSI5S_TSCNTA_CLRA_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_TSCNTA_Bits.CLRA */
+#define IFX_PSI5S_TSCNTA_CLRA_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_TSCNTA_Bits.CLRA */
+#define IFX_PSI5S_TSCNTA_CLRA_OFF (30u)
+
+/** \brief Length for Ifx_PSI5S_TSCNTA_Bits.CLRB */
+#define IFX_PSI5S_TSCNTA_CLRB_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_TSCNTA_Bits.CLRB */
+#define IFX_PSI5S_TSCNTA_CLRB_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_TSCNTA_Bits.CLRB */
+#define IFX_PSI5S_TSCNTA_CLRB_OFF (31u)
+
+/** \brief Length for Ifx_PSI5S_TSCNTA_Bits.CTS */
+#define IFX_PSI5S_TSCNTA_CTS_LEN (24u)
+
+/** \brief Mask for Ifx_PSI5S_TSCNTA_Bits.CTS */
+#define IFX_PSI5S_TSCNTA_CTS_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_PSI5S_TSCNTA_Bits.CTS */
+#define IFX_PSI5S_TSCNTA_CTS_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_TSCNTA_Bits.ETB */
+#define IFX_PSI5S_TSCNTA_ETB_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_TSCNTA_Bits.ETB */
+#define IFX_PSI5S_TSCNTA_ETB_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_TSCNTA_Bits.ETB */
+#define IFX_PSI5S_TSCNTA_ETB_OFF (24u)
+
+/** \brief Length for Ifx_PSI5S_TSCNTA_Bits.TBEA */
+#define IFX_PSI5S_TSCNTA_TBEA_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_TSCNTA_Bits.TBEA */
+#define IFX_PSI5S_TSCNTA_TBEA_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_TSCNTA_Bits.TBEA */
+#define IFX_PSI5S_TSCNTA_TBEA_OFF (28u)
+
+/** \brief Length for Ifx_PSI5S_TSCNTA_Bits.TBEB */
+#define IFX_PSI5S_TSCNTA_TBEB_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_TSCNTA_Bits.TBEB */
+#define IFX_PSI5S_TSCNTA_TBEB_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_TSCNTA_Bits.TBEB */
+#define IFX_PSI5S_TSCNTA_TBEB_OFF (29u)
+
+/** \brief Length for Ifx_PSI5S_TSCNTA_Bits.TBS */
+#define IFX_PSI5S_TSCNTA_TBS_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_TSCNTA_Bits.TBS */
+#define IFX_PSI5S_TSCNTA_TBS_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_TSCNTA_Bits.TBS */
+#define IFX_PSI5S_TSCNTA_TBS_OFF (27u)
+
+/** \brief Length for Ifx_PSI5S_TSCNTB_Bits.CTS */
+#define IFX_PSI5S_TSCNTB_CTS_LEN (24u)
+
+/** \brief Mask for Ifx_PSI5S_TSCNTB_Bits.CTS */
+#define IFX_PSI5S_TSCNTB_CTS_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_PSI5S_TSCNTB_Bits.CTS */
+#define IFX_PSI5S_TSCNTB_CTS_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_TSCNTB_Bits.ETB */
+#define IFX_PSI5S_TSCNTB_ETB_LEN (3u)
+
+/** \brief Mask for Ifx_PSI5S_TSCNTB_Bits.ETB */
+#define IFX_PSI5S_TSCNTB_ETB_MSK (0x7u)
+
+/** \brief Offset for Ifx_PSI5S_TSCNTB_Bits.ETB */
+#define IFX_PSI5S_TSCNTB_ETB_OFF (24u)
+
+/** \brief Length for Ifx_PSI5S_TSCNTB_Bits.TBS */
+#define IFX_PSI5S_TSCNTB_TBS_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_TSCNTB_Bits.TBS */
+#define IFX_PSI5S_TSCNTB_TBS_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_TSCNTB_Bits.TBS */
+#define IFX_PSI5S_TSCNTB_TBS_OFF (27u)
+
+/** \brief Length for Ifx_PSI5S_TSCR_Bits.TS */
+#define IFX_PSI5S_TSCR_TS_LEN (24u)
+
+/** \brief Mask for Ifx_PSI5S_TSCR_Bits.TS */
+#define IFX_PSI5S_TSCR_TS_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_PSI5S_TSCR_Bits.TS */
+#define IFX_PSI5S_TSCR_TS_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_TSM_Bits.PFC */
+#define IFX_PSI5S_TSM_PFC_LEN (4u)
+
+/** \brief Mask for Ifx_PSI5S_TSM_Bits.PFC */
+#define IFX_PSI5S_TSM_PFC_MSK (0xfu)
+
+/** \brief Offset for Ifx_PSI5S_TSM_Bits.PFC */
+#define IFX_PSI5S_TSM_PFC_OFF (28u)
+
+/** \brief Length for Ifx_PSI5S_TSM_Bits.TS */
+#define IFX_PSI5S_TSM_TS_LEN (24u)
+
+/** \brief Mask for Ifx_PSI5S_TSM_Bits.TS */
+#define IFX_PSI5S_TSM_TS_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_PSI5S_TSM_Bits.TS */
+#define IFX_PSI5S_TSM_TS_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_WDT_Bits.WDL */
+#define IFX_PSI5S_WDT_WDL_LEN (24u)
+
+/** \brief Mask for Ifx_PSI5S_WDT_Bits.WDL */
+#define IFX_PSI5S_WDT_WDL_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_PSI5S_WDT_Bits.WDL */
+#define IFX_PSI5S_WDT_WDL_OFF (0u)
+
+/** \brief Length for Ifx_PSI5S_WHBCON_Bits.CLRFE */
+#define IFX_PSI5S_WHBCON_CLRFE_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_WHBCON_Bits.CLRFE */
+#define IFX_PSI5S_WHBCON_CLRFE_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_WHBCON_Bits.CLRFE */
+#define IFX_PSI5S_WHBCON_CLRFE_OFF (9u)
+
+/** \brief Length for Ifx_PSI5S_WHBCON_Bits.CLROE */
+#define IFX_PSI5S_WHBCON_CLROE_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_WHBCON_Bits.CLROE */
+#define IFX_PSI5S_WHBCON_CLROE_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_WHBCON_Bits.CLROE */
+#define IFX_PSI5S_WHBCON_CLROE_OFF (10u)
+
+/** \brief Length for Ifx_PSI5S_WHBCON_Bits.CLRPE */
+#define IFX_PSI5S_WHBCON_CLRPE_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_WHBCON_Bits.CLRPE */
+#define IFX_PSI5S_WHBCON_CLRPE_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_WHBCON_Bits.CLRPE */
+#define IFX_PSI5S_WHBCON_CLRPE_OFF (8u)
+
+/** \brief Length for Ifx_PSI5S_WHBCON_Bits.CLRREN */
+#define IFX_PSI5S_WHBCON_CLRREN_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_WHBCON_Bits.CLRREN */
+#define IFX_PSI5S_WHBCON_CLRREN_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_WHBCON_Bits.CLRREN */
+#define IFX_PSI5S_WHBCON_CLRREN_OFF (4u)
+
+/** \brief Length for Ifx_PSI5S_WHBCON_Bits.SETFE */
+#define IFX_PSI5S_WHBCON_SETFE_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_WHBCON_Bits.SETFE */
+#define IFX_PSI5S_WHBCON_SETFE_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_WHBCON_Bits.SETFE */
+#define IFX_PSI5S_WHBCON_SETFE_OFF (12u)
+
+/** \brief Length for Ifx_PSI5S_WHBCON_Bits.SETOE */
+#define IFX_PSI5S_WHBCON_SETOE_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_WHBCON_Bits.SETOE */
+#define IFX_PSI5S_WHBCON_SETOE_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_WHBCON_Bits.SETOE */
+#define IFX_PSI5S_WHBCON_SETOE_OFF (13u)
+
+/** \brief Length for Ifx_PSI5S_WHBCON_Bits.SETPE */
+#define IFX_PSI5S_WHBCON_SETPE_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_WHBCON_Bits.SETPE */
+#define IFX_PSI5S_WHBCON_SETPE_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_WHBCON_Bits.SETPE */
+#define IFX_PSI5S_WHBCON_SETPE_OFF (11u)
+
+/** \brief Length for Ifx_PSI5S_WHBCON_Bits.SETREN */
+#define IFX_PSI5S_WHBCON_SETREN_LEN (1u)
+
+/** \brief Mask for Ifx_PSI5S_WHBCON_Bits.SETREN */
+#define IFX_PSI5S_WHBCON_SETREN_MSK (0x1u)
+
+/** \brief Offset for Ifx_PSI5S_WHBCON_Bits.SETREN */
+#define IFX_PSI5S_WHBCON_SETREN_OFF (5u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXPSI5S_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPsi5s_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPsi5s_reg.h
new file mode 100644
index 0000000..556b280
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPsi5s_reg.h
@@ -0,0 +1,468 @@
+/**
+ * \file IfxPsi5s_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Psi5s_Cfg Psi5s address
+ * \ingroup IfxLld_Psi5s
+ *
+ * \defgroup IfxLld_Psi5s_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Psi5s_Cfg
+ *
+ * \defgroup IfxLld_Psi5s_Cfg_Psi5s 2-PSI5S
+ * \ingroup IfxLld_Psi5s_Cfg
+ *
+ */
+#ifndef IFXPSI5S_REG_H
+#define IFXPSI5S_REG_H 1
+/******************************************************************************/
+#include "IfxPsi5s_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Psi5s_Cfg_BaseAddress
+ * \{ */
+
+/** \brief PSI5S object */
+#define MODULE_PSI5S /*lint --e(923)*/ (*(Ifx_PSI5S*)0xF0007000u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Psi5s_Cfg_Psi5s
+ * \{ */
+
+/** \brief 3D0, Access Enable Register 0 */
+#define PSI5S_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_ACCEN0*)0xF00073D0u)
+
+/** \brief 3D4, Access Enable Register 1 */
+#define PSI5S_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_ACCEN1*)0xF00073D4u)
+
+/** \brief D4, Base Address Register */
+#define PSI5S_BAR /*lint --e(923)*/ (*(volatile Ifx_PSI5S_BAR*)0xF00070D4u)
+
+/** \brief 214, Baud Rate Timer/Reload Register */
+#define PSI5S_BG /*lint --e(923)*/ (*(volatile Ifx_PSI5S_BG*)0xF0007214u)
+
+/** \brief 170, CPU Direct Write Register */
+#define PSI5S_CDW /*lint --e(923)*/ (*(volatile Ifx_PSI5S_CDW*)0xF0007170u)
+
+/** \brief 0, Clock Control Register */
+#define PSI5S_CLC /*lint --e(923)*/ (*(volatile Ifx_PSI5S_CLC*)0xF0007000u)
+
+/** \brief 210, Control Register */
+#define PSI5S_CON /*lint --e(923)*/ (*(volatile Ifx_PSI5S_CON*)0xF0007210u)
+
+/** \brief 110, Channel Trigger Value Register */
+#define PSI5S_CTV0 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_CTV*)0xF0007110u)
+
+/** \brief 114, Channel Trigger Value Register */
+#define PSI5S_CTV1 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_CTV*)0xF0007114u)
+
+/** \brief 118, Channel Trigger Value Register */
+#define PSI5S_CTV2 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_CTV*)0xF0007118u)
+
+/** \brief 11C, Channel Trigger Value Register */
+#define PSI5S_CTV3 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_CTV*)0xF000711Cu)
+
+/** \brief 120, Channel Trigger Value Register */
+#define PSI5S_CTV4 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_CTV*)0xF0007120u)
+
+/** \brief 124, Channel Trigger Value Register */
+#define PSI5S_CTV5 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_CTV*)0xF0007124u)
+
+/** \brief 128, Channel Trigger Value Register */
+#define PSI5S_CTV6 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_CTV*)0xF0007128u)
+
+/** \brief 12C, Channel Trigger Value Register */
+#define PSI5S_CTV7 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_CTV*)0xF000712Cu)
+
+/** \brief 24, Frame Counter Register */
+#define PSI5S_FCNT /*lint --e(923)*/ (*(volatile Ifx_PSI5S_FCNT*)0xF0007024u)
+
+/** \brief 21C, Fractional Divider for Output CLK Register */
+#define PSI5S_FDO /*lint --e(923)*/ (*(volatile Ifx_PSI5S_FDO*)0xF000721Cu)
+
+/** \brief C, PSI5-S Fractional Divider Register */
+#define PSI5S_FDR /*lint --e(923)*/ (*(volatile Ifx_PSI5S_FDR*)0xF000700Cu)
+
+/** \brief 10, Fractional Divider Register for Time Stamp */
+#define PSI5S_FDRT /*lint --e(923)*/ (*(volatile Ifx_PSI5S_FDRT*)0xF0007010u)
+
+/** \brief 218, Fractional Divider Register */
+#define PSI5S_FDV /*lint --e(923)*/ (*(volatile Ifx_PSI5S_FDV*)0xF0007218u)
+
+/** \brief 1C, Global Control Register */
+#define PSI5S_GCR /*lint --e(923)*/ (*(volatile Ifx_PSI5S_GCR*)0xF000701Cu)
+
+/** \brief 8, Module Identification Register */
+#define PSI5S_ID /*lint --e(923)*/ (*(volatile Ifx_PSI5S_ID*)0xF0007008u)
+
+/** \brief 2E0, Interrupt Node Pointer Register */
+#define PSI5S_INP0 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INP*)0xF00072E0u)
+
+/** \brief 2E4, Interrupt Node Pointer Register */
+#define PSI5S_INP1 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INP*)0xF00072E4u)
+
+/** \brief 2E8, Interrupt Node Pointer Register */
+#define PSI5S_INP2 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INP*)0xF00072E8u)
+
+/** \brief 2EC, Interrupt Node Pointer Register */
+#define PSI5S_INP3 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INP*)0xF00072ECu)
+
+/** \brief 2F0, Interrupt Node Pointer Register */
+#define PSI5S_INP4 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INP*)0xF00072F0u)
+
+/** \brief 2F4, Interrupt Node Pointer Register */
+#define PSI5S_INP5 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INP*)0xF00072F4u)
+
+/** \brief 2F8, Interrupt Node Pointer Register */
+#define PSI5S_INP6 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INP*)0xF00072F8u)
+
+/** \brief 2FC, Interrupt Node Pointer Register */
+#define PSI5S_INP7 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INP*)0xF00072FCu)
+
+/** \brief 314, Interrupt Node Pointer G Register */
+#define PSI5S_INPG /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INPG*)0xF0007314u)
+
+/** \brief 2A0, Interrupt Clear Register */
+#define PSI5S_INTCLR0 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTCLR*)0xF00072A0u)
+
+/** \brief 2A4, Interrupt Clear Register */
+#define PSI5S_INTCLR1 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTCLR*)0xF00072A4u)
+
+/** \brief 2A8, Interrupt Clear Register */
+#define PSI5S_INTCLR2 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTCLR*)0xF00072A8u)
+
+/** \brief 2AC, Interrupt Clear Register */
+#define PSI5S_INTCLR3 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTCLR*)0xF00072ACu)
+
+/** \brief 2B0, Interrupt Clear Register */
+#define PSI5S_INTCLR4 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTCLR*)0xF00072B0u)
+
+/** \brief 2B4, Interrupt Clear Register */
+#define PSI5S_INTCLR5 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTCLR*)0xF00072B4u)
+
+/** \brief 2B8, Interrupt Clear Register */
+#define PSI5S_INTCLR6 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTCLR*)0xF00072B8u)
+
+/** \brief 2BC, Interrupt Clear Register */
+#define PSI5S_INTCLR7 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTCLR*)0xF00072BCu)
+
+/** \brief 30C, Interrupt Clear Register G */
+#define PSI5S_INTCLRG /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTCLRG*)0xF000730Cu)
+
+/** \brief 2C0, Interrupt Enable Register */
+#define PSI5S_INTEN0 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTEN*)0xF00072C0u)
+
+/** \brief 2C4, Interrupt Enable Register */
+#define PSI5S_INTEN1 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTEN*)0xF00072C4u)
+
+/** \brief 2C8, Interrupt Enable Register */
+#define PSI5S_INTEN2 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTEN*)0xF00072C8u)
+
+/** \brief 2CC, Interrupt Enable Register */
+#define PSI5S_INTEN3 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTEN*)0xF00072CCu)
+
+/** \brief 2D0, Interrupt Enable Register */
+#define PSI5S_INTEN4 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTEN*)0xF00072D0u)
+
+/** \brief 2D4, Interrupt Enable Register */
+#define PSI5S_INTEN5 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTEN*)0xF00072D4u)
+
+/** \brief 2D8, Interrupt Enable Register */
+#define PSI5S_INTEN6 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTEN*)0xF00072D8u)
+
+/** \brief 2DC, Interrupt Enable Register */
+#define PSI5S_INTEN7 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTEN*)0xF00072DCu)
+
+/** \brief 310, Interrupt Enable Register G */
+#define PSI5S_INTENG /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTENG*)0xF0007310u)
+
+/** \brief 300, Interrupt Overview Register */
+#define PSI5S_INTOV /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTOV*)0xF0007300u)
+
+/** \brief 280, Interrupt Set Register */
+#define PSI5S_INTSET0 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTSET*)0xF0007280u)
+
+/** \brief 284, Interrupt Set Register */
+#define PSI5S_INTSET1 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTSET*)0xF0007284u)
+
+/** \brief 288, Interrupt Set Register */
+#define PSI5S_INTSET2 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTSET*)0xF0007288u)
+
+/** \brief 28C, Interrupt Set Register */
+#define PSI5S_INTSET3 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTSET*)0xF000728Cu)
+
+/** \brief 290, Interrupt Set Register */
+#define PSI5S_INTSET4 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTSET*)0xF0007290u)
+
+/** \brief 294, Interrupt Set Register */
+#define PSI5S_INTSET5 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTSET*)0xF0007294u)
+
+/** \brief 298, Interrupt Set Register */
+#define PSI5S_INTSET6 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTSET*)0xF0007298u)
+
+/** \brief 29C, Interrupt Set Register */
+#define PSI5S_INTSET7 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTSET*)0xF000729Cu)
+
+/** \brief 308, Interrupt Set Register G */
+#define PSI5S_INTSETG /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTSETG*)0xF0007308u)
+
+/** \brief 260, Interrupt Status Register */
+#define PSI5S_INTSTAT0 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTSTAT*)0xF0007260u)
+
+/** \brief 264, Interrupt Status Register */
+#define PSI5S_INTSTAT1 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTSTAT*)0xF0007264u)
+
+/** \brief 268, Interrupt Status Register */
+#define PSI5S_INTSTAT2 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTSTAT*)0xF0007268u)
+
+/** \brief 26C, Interrupt Status Register */
+#define PSI5S_INTSTAT3 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTSTAT*)0xF000726Cu)
+
+/** \brief 270, Interrupt Status Register */
+#define PSI5S_INTSTAT4 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTSTAT*)0xF0007270u)
+
+/** \brief 274, Interrupt Status Register */
+#define PSI5S_INTSTAT5 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTSTAT*)0xF0007274u)
+
+/** \brief 278, Interrupt Status Register */
+#define PSI5S_INTSTAT6 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTSTAT*)0xF0007278u)
+
+/** \brief 27C, Interrupt Status Register */
+#define PSI5S_INTSTAT7 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTSTAT*)0xF000727Cu)
+
+/** \brief 304, Interrupt Status Register G */
+#define PSI5S_INTSTATG /*lint --e(923)*/ (*(volatile Ifx_PSI5S_INTSTATG*)0xF0007304u)
+
+/** \brief 28, Input and Output Control Register */
+#define PSI5S_IOCR /*lint --e(923)*/ (*(volatile Ifx_PSI5S_IOCR*)0xF0007028u)
+
+/** \brief 3D8, Kernel Reset Register 0 */
+#define PSI5S_KRST0 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_KRST0*)0xF00073D8u)
+
+/** \brief 3DC, Kernel Reset Register 1 */
+#define PSI5S_KRST1 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_KRST1*)0xF00073DCu)
+
+/** \brief 3E0, Kernel Reset Status Clear Register */
+#define PSI5S_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_PSI5S_KRSTCLR*)0xF00073E0u)
+
+/** \brief 20, Number of Frames Control Register */
+#define PSI5S_NFC /*lint --e(923)*/ (*(volatile Ifx_PSI5S_NFC*)0xF0007020u)
+
+/** \brief 3CC, OCDS Control and Status */
+#define PSI5S_OCS /*lint --e(923)*/ (*(volatile Ifx_PSI5S_OCS*)0xF00073CCu)
+
+/** \brief F0, Pulse Generation Control Register */
+#define PSI5S_PGC0 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_PGC*)0xF00070F0u)
+
+/** \brief F4, Pulse Generation Control Register */
+#define PSI5S_PGC1 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_PGC*)0xF00070F4u)
+
+/** \brief F8, Pulse Generation Control Register */
+#define PSI5S_PGC2 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_PGC*)0xF00070F8u)
+
+/** \brief FC, Pulse Generation Control Register */
+#define PSI5S_PGC3 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_PGC*)0xF00070FCu)
+
+/** \brief 100, Pulse Generation Control Register */
+#define PSI5S_PGC4 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_PGC*)0xF0007100u)
+
+/** \brief 104, Pulse Generation Control Register */
+#define PSI5S_PGC5 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_PGC*)0xF0007104u)
+
+/** \brief 108, Pulse Generation Control Register */
+#define PSI5S_PGC6 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_PGC*)0xF0007108u)
+
+/** \brief 10C, Pulse Generation Control Register */
+#define PSI5S_PGC7 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_PGC*)0xF000710Cu)
+
+/** \brief 224, Receive Buffer Register */
+#define PSI5S_RBUF /*lint --e(923)*/ (*(volatile Ifx_PSI5S_RBUF*)0xF0007224u)
+
+/** \brief 30, Receiver Control Register A */
+#define PSI5S_RCRA0 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_RCRA*)0xF0007030u)
+
+/** \brief 34, Receiver Control Register A */
+#define PSI5S_RCRA1 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_RCRA*)0xF0007034u)
+
+/** \brief 38, Receiver Control Register A */
+#define PSI5S_RCRA2 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_RCRA*)0xF0007038u)
+
+/** \brief 3C, Receiver Control Register A */
+#define PSI5S_RCRA3 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_RCRA*)0xF000703Cu)
+
+/** \brief 40, Receiver Control Register A */
+#define PSI5S_RCRA4 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_RCRA*)0xF0007040u)
+
+/** \brief 44, Receiver Control Register A */
+#define PSI5S_RCRA5 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_RCRA*)0xF0007044u)
+
+/** \brief 48, Receiver Control Register A */
+#define PSI5S_RCRA6 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_RCRA*)0xF0007048u)
+
+/** \brief 4C, Receiver Control Register A */
+#define PSI5S_RCRA7 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_RCRA*)0xF000704Cu)
+
+/** \brief 50, Receiver Control Register B */
+#define PSI5S_RCRB0 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_RCRB*)0xF0007050u)
+
+/** \brief 54, Receiver Control Register B */
+#define PSI5S_RCRB1 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_RCRB*)0xF0007054u)
+
+/** \brief 58, Receiver Control Register B */
+#define PSI5S_RCRB2 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_RCRB*)0xF0007058u)
+
+/** \brief 5C, Receiver Control Register B */
+#define PSI5S_RCRB3 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_RCRB*)0xF000705Cu)
+
+/** \brief 60, Receiver Control Register B */
+#define PSI5S_RCRB4 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_RCRB*)0xF0007060u)
+
+/** \brief 64, Receiver Control Register B */
+#define PSI5S_RCRB5 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_RCRB*)0xF0007064u)
+
+/** \brief 68, Receiver Control Register B */
+#define PSI5S_RCRB6 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_RCRB*)0xF0007068u)
+
+/** \brief 6C, Receiver Control Register B */
+#define PSI5S_RCRB7 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_RCRB*)0xF000706Cu)
+
+/** \brief B4, Receive Data Register */
+#define PSI5S_RDR /*lint --e(923)*/ (*(volatile Ifx_PSI5S_RDR*)0xF00070B4u)
+
+/** \brief B0, Receive Status Register */
+#define PSI5S_RDS /*lint --e(923)*/ (*(volatile Ifx_PSI5S_RDS*)0xF00070B0u)
+
+/** \brief 130, Send Control Register */
+#define PSI5S_SCR0 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_SCR*)0xF0007130u)
+
+/** \brief 134, Send Control Register */
+#define PSI5S_SCR1 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_SCR*)0xF0007134u)
+
+/** \brief 138, Send Control Register */
+#define PSI5S_SCR2 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_SCR*)0xF0007138u)
+
+/** \brief 13C, Send Control Register */
+#define PSI5S_SCR3 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_SCR*)0xF000713Cu)
+
+/** \brief 140, Send Control Register */
+#define PSI5S_SCR4 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_SCR*)0xF0007140u)
+
+/** \brief 144, Send Control Register */
+#define PSI5S_SCR5 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_SCR*)0xF0007144u)
+
+/** \brief 148, Send Control Register */
+#define PSI5S_SCR6 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_SCR*)0xF0007148u)
+
+/** \brief 14C, Send Control Register */
+#define PSI5S_SCR7 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_SCR*)0xF000714Cu)
+
+/** \brief 150, Send Data Register */
+#define PSI5S_SDR0 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_SDR*)0xF0007150u)
+
+/** \brief 154, Send Data Register */
+#define PSI5S_SDR1 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_SDR*)0xF0007154u)
+
+/** \brief 158, Send Data Register */
+#define PSI5S_SDR2 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_SDR*)0xF0007158u)
+
+/** \brief 15C, Send Data Register */
+#define PSI5S_SDR3 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_SDR*)0xF000715Cu)
+
+/** \brief 160, Send Data Register */
+#define PSI5S_SDR4 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_SDR*)0xF0007160u)
+
+/** \brief 164, Send Data Register */
+#define PSI5S_SDR5 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_SDR*)0xF0007164u)
+
+/** \brief 168, Send Data Register */
+#define PSI5S_SDR6 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_SDR*)0xF0007168u)
+
+/** \brief 16C, Send Data Register */
+#define PSI5S_SDR7 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_SDR*)0xF000716Cu)
+
+/** \brief D0, Target Address Register */
+#define PSI5S_TAR /*lint --e(923)*/ (*(volatile Ifx_PSI5S_TAR*)0xF00070D0u)
+
+/** \brief 220, Transmit Buffer Register */
+#define PSI5S_TBUF /*lint --e(923)*/ (*(volatile Ifx_PSI5S_TBUF*)0xF0007220u)
+
+/** \brief 14, Time Stamp Count Register A */
+#define PSI5S_TSCNTA /*lint --e(923)*/ (*(volatile Ifx_PSI5S_TSCNTA*)0xF0007014u)
+
+/** \brief 18, Time Stamp Count Register B */
+#define PSI5S_TSCNTB /*lint --e(923)*/ (*(volatile Ifx_PSI5S_TSCNTB*)0xF0007018u)
+
+/** \brief 90, Capture Register */
+#define PSI5S_TSCR0 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_TSCR*)0xF0007090u)
+
+/** \brief 94, Capture Register */
+#define PSI5S_TSCR1 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_TSCR*)0xF0007094u)
+
+/** \brief 98, Capture Register */
+#define PSI5S_TSCR2 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_TSCR*)0xF0007098u)
+
+/** \brief 9C, Capture Register */
+#define PSI5S_TSCR3 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_TSCR*)0xF000709Cu)
+
+/** \brief A0, Capture Register */
+#define PSI5S_TSCR4 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_TSCR*)0xF00070A0u)
+
+/** \brief A4, Capture Register */
+#define PSI5S_TSCR5 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_TSCR*)0xF00070A4u)
+
+/** \brief A8, Capture Register */
+#define PSI5S_TSCR6 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_TSCR*)0xF00070A8u)
+
+/** \brief AC, Capture Register */
+#define PSI5S_TSCR7 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_TSCR*)0xF00070ACu)
+
+/** \brief B8, Time Stamp Mirror Register TSM */
+#define PSI5S_TSM /*lint --e(923)*/ (*(volatile Ifx_PSI5S_TSM*)0xF00070B8u)
+
+/** \brief 70, Watch Dog Timer Register */
+#define PSI5S_WDT0 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_WDT*)0xF0007070u)
+
+/** \brief 74, Watch Dog Timer Register */
+#define PSI5S_WDT1 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_WDT*)0xF0007074u)
+
+/** \brief 78, Watch Dog Timer Register */
+#define PSI5S_WDT2 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_WDT*)0xF0007078u)
+
+/** \brief 7C, Watch Dog Timer Register */
+#define PSI5S_WDT3 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_WDT*)0xF000707Cu)
+
+/** \brief 80, Watch Dog Timer Register */
+#define PSI5S_WDT4 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_WDT*)0xF0007080u)
+
+/** \brief 84, Watch Dog Timer Register */
+#define PSI5S_WDT5 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_WDT*)0xF0007084u)
+
+/** \brief 88, Watch Dog Timer Register */
+#define PSI5S_WDT6 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_WDT*)0xF0007088u)
+
+/** \brief 8C, Watch Dog Timer Register */
+#define PSI5S_WDT7 /*lint --e(923)*/ (*(volatile Ifx_PSI5S_WDT*)0xF000708Cu)
+
+/** \brief 250, Write Hardware Bits Control Register */
+#define PSI5S_WHBCON /*lint --e(923)*/ (*(volatile Ifx_PSI5S_WHBCON*)0xF0007250u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXPSI5S_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPsi5s_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPsi5s_regdef.h
new file mode 100644
index 0000000..72998c8
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxPsi5s_regdef.h
@@ -0,0 +1,1168 @@
+/**
+ * \file IfxPsi5s_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Psi5s Psi5s
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Psi5s_Bitfields Bitfields
+ * \ingroup IfxLld_Psi5s
+ *
+ * \defgroup IfxLld_Psi5s_union Union
+ * \ingroup IfxLld_Psi5s
+ *
+ * \defgroup IfxLld_Psi5s_struct Struct
+ * \ingroup IfxLld_Psi5s
+ *
+ */
+#ifndef IFXPSI5S_REGDEF_H
+#define IFXPSI5S_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Psi5s_Bitfields
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef struct _Ifx_PSI5S_ACCEN0_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_PSI5S_ACCEN0_Bits;
+
+/** \brief Access Enable Register 1 */
+typedef struct _Ifx_PSI5S_ACCEN1_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_PSI5S_ACCEN1_Bits;
+
+/** \brief Base Address Register */
+typedef struct _Ifx_PSI5S_BAR_Bits
+{
+ unsigned int reserved_0:2; /**< \brief \internal Reserved */
+ unsigned int BA:30; /**< \brief [31:2] Base Address (rw) */
+} Ifx_PSI5S_BAR_Bits;
+
+/** \brief Baud Rate Timer/Reload Register */
+typedef struct _Ifx_PSI5S_BG_Bits
+{
+ unsigned int BR_VALUE:13; /**< \brief [12:0] Baud Rate Timer/Reload Register Value (rwh) */
+ unsigned int reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_PSI5S_BG_Bits;
+
+/** \brief CPU Direct Write Register */
+typedef struct _Ifx_PSI5S_CDW_Bits
+{
+ unsigned int SD0:1; /**< \brief [0:0] SD0 (rw) */
+ unsigned int SD1:1; /**< \brief [1:1] SD1 (rw) */
+ unsigned int SD2:1; /**< \brief [2:2] SD2 (rw) */
+ unsigned int SD3:1; /**< \brief [3:3] SD3 (rw) */
+ unsigned int SD4:1; /**< \brief [4:4] SD4 (rw) */
+ unsigned int SD5:1; /**< \brief [5:5] SD5 (rw) */
+ unsigned int SD6:1; /**< \brief [6:6] SD6 (rw) */
+ unsigned int SD7:1; /**< \brief [7:7] SD7 (rw) */
+ unsigned int TSI:1; /**< \brief [8:8] Trigger Pulse Indicator (rw) */
+ unsigned int reserved_9:23; /**< \brief \internal Reserved */
+} Ifx_PSI5S_CDW_Bits;
+
+/** \brief Clock Control Register */
+typedef struct _Ifx_PSI5S_CLC_Bits
+{
+ unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
+ unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
+ unsigned int reserved_2:1; /**< \brief \internal Reserved */
+ unsigned int EDIS:1; /**< \brief [3:3] External Sleep Mode Request Disable Bit (rw) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_PSI5S_CLC_Bits;
+
+/** \brief Control Register */
+typedef struct _Ifx_PSI5S_CON_Bits
+{
+ unsigned int M:3; /**< \brief [2:0] Mode Selection (rw) */
+ unsigned int STP:1; /**< \brief [3:3] Number of Stop Bit Selection (rw) */
+ unsigned int REN:1; /**< \brief [4:4] Receiver Enable Control (r) */
+ unsigned int PEN:1; /**< \brief [5:5] Parity Check Enable (asynchronous mode only) (rw) */
+ unsigned int FEN:1; /**< \brief [6:6] Framing Check Enable (asynchronous mode only) (rw) */
+ unsigned int OEN:1; /**< \brief [7:7] Overrun Check Enable (rw) */
+ unsigned int PE:1; /**< \brief [8:8] ASC Parity Error Flag (r) */
+ unsigned int FE:1; /**< \brief [9:9] ASC Framing Error Flag (r) */
+ unsigned int OE:1; /**< \brief [10:10] ASC Overrun Error Flag (r) */
+ unsigned int FDE:1; /**< \brief [11:11] Fractional Divider Enable (rw) */
+ unsigned int ODD:1; /**< \brief [12:12] Parity Selection (rw) */
+ unsigned int BRS:1; /**< \brief [13:13] Baud Rate Selection (rw) */
+ unsigned int LB:1; /**< \brief [14:14] Loop-back Mode Enable (rw) */
+ unsigned int R:1; /**< \brief [15:15] Baud Rate Generator Run Control (rw) */
+ unsigned int MTX:3; /**< \brief [18:16] Mode Selection TX direction (rw) */
+ unsigned int reserved_19:9; /**< \brief \internal Reserved */
+ unsigned int ODDTX:1; /**< \brief [28:28] Parity Selection TX direction (rw) */
+ unsigned int reserved_29:3; /**< \brief \internal Reserved */
+} Ifx_PSI5S_CON_Bits;
+
+/** \brief Channel Trigger Value Register */
+typedef struct _Ifx_PSI5S_CTV_Bits
+{
+ unsigned int CTV:16; /**< \brief [15:0] Channel Trigger Value CTV (rw) */
+ unsigned int CTC:16; /**< \brief [31:16] Channel Trigger Counter (rw) */
+} Ifx_PSI5S_CTV_Bits;
+
+/** \brief Frame Counter Register */
+typedef struct _Ifx_PSI5S_FCNT_Bits
+{
+ unsigned int FC0:3; /**< \brief [2:0] Frame Counter for Channel 0 (r) */
+ unsigned int FC1:3; /**< \brief [5:3] Frame Counter for Channel 1 (r) */
+ unsigned int FC2:3; /**< \brief [8:6] Frame Counter for Channel 2 (r) */
+ unsigned int FC3:3; /**< \brief [11:9] Frame Counter for Channel 3 (r) */
+ unsigned int FC4:3; /**< \brief [14:12] Frame Counter for Channel 4 (r) */
+ unsigned int FC5:3; /**< \brief [17:15] Frame Counter for Channel 5 (r) */
+ unsigned int FC6:3; /**< \brief [20:18] Frame Counter for Channel 6 (r) */
+ unsigned int FC7:3; /**< \brief [23:21] Frame Counter for Channel 7 (r) */
+ unsigned int NFCLR0:1; /**< \brief [24:24] Clear Number of Frame Counter for Channel 0 (w) */
+ unsigned int NFCLR1:1; /**< \brief [25:25] Clear Number of Frame Counter for Channel 1 (w) */
+ unsigned int NFCLR2:1; /**< \brief [26:26] Clear Number of Frame Counter for Channel 2 (w) */
+ unsigned int NFCLR3:1; /**< \brief [27:27] Clear Number of Frame Counter for Channel 3 (w) */
+ unsigned int NFCLR4:1; /**< \brief [28:28] Clear Number of Frame Counter for Channel 4 (w) */
+ unsigned int NFCLR5:1; /**< \brief [29:29] Clear Number of Frame Counter for Channel 5 (w) */
+ unsigned int NFCLR6:1; /**< \brief [30:30] Clear Number of Frame Counter for Channel 6 (w) */
+ unsigned int NFCLR7:1; /**< \brief [31:31] Clear Number of Frame Counter for Channel 7 (w) */
+} Ifx_PSI5S_FCNT_Bits;
+
+/** \brief Fractional Divider for Output CLK Register */
+typedef struct _Ifx_PSI5S_FDO_Bits
+{
+ unsigned int STEP:11; /**< \brief [10:0] Step Value (rw) */
+ unsigned int reserved_11:3; /**< \brief \internal Reserved */
+ unsigned int DM:2; /**< \brief [15:14] Divider Mode (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_PSI5S_FDO_Bits;
+
+/** \brief PSI5-S Fractional Divider Register */
+typedef struct _Ifx_PSI5S_FDR_Bits
+{
+ unsigned int STEP:10; /**< \brief [9:0] Step Value (rw) */
+ unsigned int reserved_10:4; /**< \brief \internal Reserved */
+ unsigned int DM:2; /**< \brief [15:14] Divider Mode (rw) */
+ unsigned int RESULT:10; /**< \brief [25:16] Result Value (rh) */
+ unsigned int reserved_26:6; /**< \brief \internal Reserved */
+} Ifx_PSI5S_FDR_Bits;
+
+/** \brief Fractional Divider Register for Time Stamp */
+typedef struct _Ifx_PSI5S_FDRT_Bits
+{
+ unsigned int STEP:10; /**< \brief [9:0] Step Value (rw) */
+ unsigned int reserved_10:4; /**< \brief \internal Reserved */
+ unsigned int DM:2; /**< \brief [15:14] Divider Mode (rw) */
+ unsigned int RESULT:10; /**< \brief [25:16] Result Value (rh) */
+ unsigned int ECS:3; /**< \brief [28:26] External Time Stamp Clear Source Select (rw) */
+ unsigned int ECEA:1; /**< \brief [29:29] External Time Stamp Clear Enable A (rw) */
+ unsigned int ECEB:1; /**< \brief [30:30] External Time Stamp Clear Enable B (rw) */
+ unsigned int reserved_31:1; /**< \brief \internal Reserved */
+} Ifx_PSI5S_FDRT_Bits;
+
+/** \brief Fractional Divider Register */
+typedef struct _Ifx_PSI5S_FDV_Bits
+{
+ unsigned int FD_VALUE:11; /**< \brief [10:0] Fractional Divider Register Value (rw) */
+ unsigned int reserved_11:21; /**< \brief \internal Reserved */
+} Ifx_PSI5S_FDV_Bits;
+
+/** \brief Global Control Register */
+typedef struct _Ifx_PSI5S_GCR_Bits
+{
+ unsigned int CRCI:1; /**< \brief [0:0] CRCI (rw) */
+ unsigned int XCRCI:1; /**< \brief [1:1] XCRCI (rw) */
+ unsigned int TEI:1; /**< \brief [2:2] TEI (rw) */
+ unsigned int PE:1; /**< \brief [3:3] PE (rw) */
+ unsigned int FE:1; /**< \brief [4:4] FE (rw) */
+ unsigned int OE:1; /**< \brief [5:5] OE (rw) */
+ unsigned int RBI:1; /**< \brief [6:6] RBI (rw) */
+ unsigned int HDI:1; /**< \brief [7:7] HDI (rw) */
+ unsigned int ETC0:1; /**< \brief [8:8] Enable Channel Trigger Counter CTVx.CTC (rw) */
+ unsigned int ETC1:1; /**< \brief [9:9] Enable Channel Trigger Counter CTVx.CTC (rw) */
+ unsigned int ETC2:1; /**< \brief [10:10] Enable Channel Trigger Counter CTVx.CTC (rw) */
+ unsigned int ETC3:1; /**< \brief [11:11] Enable Channel Trigger Counter CTVx.CTC (rw) */
+ unsigned int ETC4:1; /**< \brief [12:12] Enable Channel Trigger Counter CTVx.CTC (rw) */
+ unsigned int ETC5:1; /**< \brief [13:13] Enable Channel Trigger Counter CTVx.CTC (rw) */
+ unsigned int ETC6:1; /**< \brief [14:14] Enable Channel Trigger Counter CTVx.CTC (rw) */
+ unsigned int ETC7:1; /**< \brief [15:15] Enable Channel Trigger Counter CTVx.CTC (rw) */
+ unsigned int CEN0:1; /**< \brief [16:16] Enable Channel 0 (rw) */
+ unsigned int CEN1:1; /**< \brief [17:17] Enable Channel 1 (rw) */
+ unsigned int CEN2:1; /**< \brief [18:18] Enable Channel 2 (rw) */
+ unsigned int CEN3:1; /**< \brief [19:19] Enable Channel 3 (rw) */
+ unsigned int CEN4:1; /**< \brief [20:20] Enable Channel 4 (rw) */
+ unsigned int CEN5:1; /**< \brief [21:21] Enable Channel 5 (rw) */
+ unsigned int CEN6:1; /**< \brief [22:22] Enable Channel 6 (rw) */
+ unsigned int CEN7:1; /**< \brief [23:23] Enable Channel 7 (rw) */
+ unsigned int IDT:4; /**< \brief [27:24] Idle Time (GLOBAL VALUE FOR ALL CHANNELS) (rw) */
+ unsigned int reserved_28:3; /**< \brief \internal Reserved */
+ unsigned int ASC:1; /**< \brief [31:31] ASC only Mode (rw) */
+} Ifx_PSI5S_GCR_Bits;
+
+/** \brief Module Identification Register */
+typedef struct _Ifx_PSI5S_ID_Bits
+{
+ unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
+ unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_PSI5S_ID_Bits;
+
+/** \brief Interrupt Node Pointer Register */
+typedef struct _Ifx_PSI5S_INP_Bits
+{
+ unsigned int RSI:3; /**< \brief [2:0] Interrupt Node Pointer for Interrupt RSI (rw) */
+ unsigned int RDI:3; /**< \brief [5:3] Interrupt Node Pointer for Interrupt RDI (rw) */
+ unsigned int RBI:3; /**< \brief [8:6] Interrupt Node Pointer for Interrupt RBI (rw) */
+ unsigned int TEI:3; /**< \brief [11:9] Interrupt Node Pointer for Interrupt TEI (rw) */
+ unsigned int CHCI:3; /**< \brief [14:12] Interrupt Node Pointer for Interrupt CHCI (rw) */
+ unsigned int CRCI:3; /**< \brief [17:15] Interrupt Node Pointer for Interrupt CRCI (rw) */
+ unsigned int TPI:3; /**< \brief [20:18] Interrupt Node Pointer for Interrupt TOI (rw) */
+ unsigned int TPOI:3; /**< \brief [23:21] Interrupt Node Pointer for TPOI (rw) */
+ unsigned int HDI:3; /**< \brief [26:24] Interrupt Node Pointer for HDI (rw) */
+ unsigned int reserved_27:5; /**< \brief \internal Reserved */
+} Ifx_PSI5S_INP_Bits;
+
+/** \brief Interrupt Node Pointer G Register */
+typedef struct _Ifx_PSI5S_INPG_Bits
+{
+ unsigned int TIR:3; /**< \brief [2:0] Interrupt Node Pointer for Interrupt TIR (rw) */
+ unsigned int RIR:3; /**< \brief [5:3] Interrupt Node Pointer for Interrupt RIR (rw) */
+ unsigned int EIR:3; /**< \brief [8:6] Interrupt Node Pointer for Interrupt EIR (rw) */
+ unsigned int TBIR:3; /**< \brief [11:9] Interrupt Node Pointer for Interrupt TBIR (rw) */
+ unsigned int XCRCI:3; /**< \brief [14:12] Interrupt Node Pointer for Interrupt XCRCI (rw) */
+ unsigned int FOI:3; /**< \brief [17:15] Interrupt Node Pointer for Interrupt FOI (rw) */
+ unsigned int reserved_18:14; /**< \brief \internal Reserved */
+} Ifx_PSI5S_INPG_Bits;
+
+/** \brief Interrupt Clear Register */
+typedef struct _Ifx_PSI5S_INTCLR_Bits
+{
+ unsigned int RSI:1; /**< \brief [0:0] Clear Interrupt Request Flag RSI (w) */
+ unsigned int RDI:1; /**< \brief [1:1] Clear Interrupt Request Flag RDI (w) */
+ unsigned int RBI:1; /**< \brief [2:2] Clear Interrupt Request Flag RBI (w) */
+ unsigned int TEI:1; /**< \brief [3:3] Clear Interrupt Request Flag TEI (w) */
+ unsigned int CHCI:1; /**< \brief [4:4] Clear Interrupt Request Flag CHCI (w) */
+ unsigned int CRCI:1; /**< \brief [5:5] Clear Interrupt Request Flag CRCI (w) */
+ unsigned int TPI:1; /**< \brief [6:6] Clear Interrupt Request Flag TPI (w) */
+ unsigned int TPOI:1; /**< \brief [7:7] Clear Interrupt Request Flag TPOI (w) */
+ unsigned int HDI:1; /**< \brief [8:8] Clear Interrupt Request Flag HDI (w) */
+ unsigned int reserved_9:23; /**< \brief \internal Reserved */
+} Ifx_PSI5S_INTCLR_Bits;
+
+/** \brief Interrupt Clear Register G */
+typedef struct _Ifx_PSI5S_INTCLRG_Bits
+{
+ unsigned int TIR:1; /**< \brief [0:0] Clear Interrupt Request Flag TIR (w) */
+ unsigned int RIR:1; /**< \brief [1:1] Clear Interrupt Request Flag RIR (w) */
+ unsigned int EIR:1; /**< \brief [2:2] Clear Interrupt Request Flag EIR (w) */
+ unsigned int TBIR:1; /**< \brief [3:3] Clear Interrupt Request Flag TBIR (w) */
+ unsigned int XCRCI:1; /**< \brief [4:4] Clear Interrupt Request Flag XCRCI (w) */
+ unsigned int FOI:1; /**< \brief [5:5] Clear Interrupt Request Flag FOI (w) */
+ unsigned int reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_PSI5S_INTCLRG_Bits;
+
+/** \brief Interrupt Enable Register */
+typedef struct _Ifx_PSI5S_INTEN_Bits
+{
+ unsigned int RSI:1; /**< \brief [0:0] Enable Interrupt Request RSI (rw) */
+ unsigned int RDI:1; /**< \brief [1:1] Enable Interrupt Request RDI (rw) */
+ unsigned int RBI:1; /**< \brief [2:2] Enable Interrupt Request RBI (rw) */
+ unsigned int TEI:1; /**< \brief [3:3] Enable Interrupt Request TEI (rw) */
+ unsigned int CHCI:1; /**< \brief [4:4] Enable Interrupt Request CHCI (rw) */
+ unsigned int CRCI:1; /**< \brief [5:5] Enable Interrupt Request CRCI (rw) */
+ unsigned int TPI:1; /**< \brief [6:6] Enable Interrupt Request TPI (rw) */
+ unsigned int TPOI:1; /**< \brief [7:7] Enable Interrupt Request TPOI (rw) */
+ unsigned int HDI:1; /**< \brief [8:8] Enable Interrupt Request HDI (rw) */
+ unsigned int reserved_9:23; /**< \brief \internal Reserved */
+} Ifx_PSI5S_INTEN_Bits;
+
+/** \brief Interrupt Enable Register G */
+typedef struct _Ifx_PSI5S_INTENG_Bits
+{
+ unsigned int TIR:1; /**< \brief [0:0] Enable Interrupt Request TIR (rw) */
+ unsigned int RIR:1; /**< \brief [1:1] Enable Interrupt Request RIR (rw) */
+ unsigned int EIR:1; /**< \brief [2:2] Enable Interrupt Request EIR (rw) */
+ unsigned int TBIR:1; /**< \brief [3:3] Enable Interrupt Request TBIR (rw) */
+ unsigned int XCRCI:1; /**< \brief [4:4] Enable Interrupt Request XCRCI (rw) */
+ unsigned int FOI:1; /**< \brief [5:5] Enable Interrupt Request FOI (rw) */
+ unsigned int reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_PSI5S_INTENG_Bits;
+
+/** \brief Interrupt Overview Register */
+typedef struct _Ifx_PSI5S_INTOV_Bits
+{
+ unsigned int RSI:1; /**< \brief [0:0] Interrupt Pending on Node Pointer RSI (rh) */
+ unsigned int RDI:1; /**< \brief [1:1] Interrupt Pending on Node Pointer RDI (rh) */
+ unsigned int RBI:1; /**< \brief [2:2] Interrupt Pending on Node Pointer RBI (rh) */
+ unsigned int TEI:1; /**< \brief [3:3] Interrupt Pending on Node Pointer TEI (rh) */
+ unsigned int CHCI:1; /**< \brief [4:4] Interrupt Pending on Node Pointer CHCI (rh) */
+ unsigned int CRCI:1; /**< \brief [5:5] Interrupt Pending on Node Pointer CRCI (rh) */
+ unsigned int TPI:1; /**< \brief [6:6] Interrupt Pending on Node Pointer TPI (rh) */
+ unsigned int TPOI:1; /**< \brief [7:7] Interrupt Pending on Node Pointer TPOI (rh) */
+ unsigned int HDI:1; /**< \brief [8:8] Interrupt Pending on Node Pointer HDI (rh) */
+ unsigned int TIR:1; /**< \brief [9:9] Interrupt Pending on Node Pointer TIR (rh) */
+ unsigned int RIR:1; /**< \brief [10:10] Interrupt Pending on Node Pointer RIR (rh) */
+ unsigned int EIR:1; /**< \brief [11:11] Interrupt Pending on Node Pointer EIR (rh) */
+ unsigned int TBIR:1; /**< \brief [12:12] Interrupt Pending on Node Pointer TBIR (rh) */
+ unsigned int XCRCI:1; /**< \brief [13:13] Interrupt Pending on Node Pointer XCRCI (rh) */
+ unsigned int FOI:1; /**< \brief [14:14] Interrupt Pending on Node Pointer FOI (rh) */
+ unsigned int reserved_15:17; /**< \brief \internal Reserved */
+} Ifx_PSI5S_INTOV_Bits;
+
+/** \brief Interrupt Set Register */
+typedef struct _Ifx_PSI5S_INTSET_Bits
+{
+ unsigned int RSI:1; /**< \brief [0:0] Set Interrupt Request Flag RSI (w) */
+ unsigned int RDI:1; /**< \brief [1:1] Set Interrupt Request Flag RDI (w) */
+ unsigned int RBI:1; /**< \brief [2:2] Set Interrupt Request Flag RBI (w) */
+ unsigned int TEI:1; /**< \brief [3:3] Set Interrupt Request Flag TEI (w) */
+ unsigned int CHCI:1; /**< \brief [4:4] Set Interrupt Request Flag CHCI (w) */
+ unsigned int CRCI:1; /**< \brief [5:5] Set Interrupt Request Flag CRCI (w) */
+ unsigned int TPI:1; /**< \brief [6:6] Set Interrupt Request Flag TPI (w) */
+ unsigned int TPOI:1; /**< \brief [7:7] Set Interrupt Request Flag TPOI (w) */
+ unsigned int HDI:1; /**< \brief [8:8] Set Interrupt Request Flag HDI (w) */
+ unsigned int reserved_9:23; /**< \brief \internal Reserved */
+} Ifx_PSI5S_INTSET_Bits;
+
+/** \brief Interrupt Set Register G */
+typedef struct _Ifx_PSI5S_INTSETG_Bits
+{
+ unsigned int TIR:1; /**< \brief [0:0] Set Interrupt Request Flag TIR (w) */
+ unsigned int RIR:1; /**< \brief [1:1] Set Interrupt Request Flag RIR (w) */
+ unsigned int EIR:1; /**< \brief [2:2] Set Interrupt Request Flag EIR (w) */
+ unsigned int TBIR:1; /**< \brief [3:3] Set Interrupt Request Flag TBIR (w) */
+ unsigned int XCRCI:1; /**< \brief [4:4] Set Interrupt Request Flag XCRCI (w) */
+ unsigned int FOI:1; /**< \brief [5:5] Set Interrupt Request Flag FOI (w) */
+ unsigned int reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_PSI5S_INTSETG_Bits;
+
+/** \brief Interrupt Status Register */
+typedef struct _Ifx_PSI5S_INTSTAT_Bits
+{
+ unsigned int RSI:1; /**< \brief [0:0] Receive Success Interrupt Request Flag (rh) */
+ unsigned int RDI:1; /**< \brief [1:1] Receive Data Interrupt Request Flag (rh) */
+ unsigned int RBI:1; /**< \brief [2:2] Receive Buffer Overflow Interrupt Request Flag (rh) */
+ unsigned int TEI:1; /**< \brief [3:3] Timing Error Interrupt Request Flag (rh) */
+ unsigned int CHCI:1; /**< \brief [4:4] Channel Completed Interrupt Request Flag (rh) */
+ unsigned int CRCI:1; /**< \brief [5:5] CRC Error Request Flag (rh) */
+ unsigned int TPI:1; /**< \brief [6:6] Transfer Preparation Interrupt Request Flag (rh) */
+ unsigned int TPOI:1; /**< \brief [7:7] Transmit Preparation Overflow Interrupt Request Flag (rh) */
+ unsigned int HDI:1; /**< \brief [8:8] Header Error Signalled Flag (rh) */
+ unsigned int reserved_9:23; /**< \brief \internal Reserved */
+} Ifx_PSI5S_INTSTAT_Bits;
+
+/** \brief Interrupt Status Register G */
+typedef struct _Ifx_PSI5S_INTSTATG_Bits
+{
+ unsigned int TIR:1; /**< \brief [0:0] Transmit Interrupt Request Flag (rh) */
+ unsigned int RIR:1; /**< \brief [1:1] Receive Interrupt Request Flag (rh) */
+ unsigned int EIR:1; /**< \brief [2:2] Error Interrupt Request Flag (rh) */
+ unsigned int TBIR:1; /**< \brief [3:3] Transmit Buffer Interrupt Request Flag (rh) */
+ unsigned int XCRCI:1; /**< \brief [4:4] XCRC Error Request Flag (rh) */
+ unsigned int FOI:1; /**< \brief [5:5] FIFO Error Request Flag (rh) */
+ unsigned int reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_PSI5S_INTSTATG_Bits;
+
+/** \brief Input and Output Control Register */
+typedef struct _Ifx_PSI5S_IOCR_Bits
+{
+ unsigned int ALTI:2; /**< \brief [1:0] Alternate Input Select (rw) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_PSI5S_IOCR_Bits;
+
+/** \brief Kernel Reset Register 0 */
+typedef struct _Ifx_PSI5S_KRST0_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rh) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_PSI5S_KRST0_Bits;
+
+/** \brief Kernel Reset Register 1 */
+typedef struct _Ifx_PSI5S_KRST1_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_PSI5S_KRST1_Bits;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef struct _Ifx_PSI5S_KRSTCLR_Bits
+{
+ unsigned int CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_PSI5S_KRSTCLR_Bits;
+
+/** \brief Number of Frames Control Register */
+typedef struct _Ifx_PSI5S_NFC_Bits
+{
+ unsigned int NF0:3; /**< \brief [2:0] Number of expected Frames on Channel 0 (rw) */
+ unsigned int NF1:3; /**< \brief [5:3] Number of expected Frames on Channel 1 (rw) */
+ unsigned int NF2:3; /**< \brief [8:6] Number of expected Frames on Channel 2 (rw) */
+ unsigned int NF3:3; /**< \brief [11:9] Number of expected Frames on Channel 3 (rw) */
+ unsigned int NF4:3; /**< \brief [14:12] Number of expected Frames on Channel 4 (rw) */
+ unsigned int NF5:3; /**< \brief [17:15] Number of expected Frames on Channel 5 (rw) */
+ unsigned int NF6:3; /**< \brief [20:18] Number of expected Frames on Channel 6 (rw) */
+ unsigned int NF7:3; /**< \brief [23:21] Number of expected Frames on Channel 7 (rw) */
+ unsigned int reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_PSI5S_NFC_Bits;
+
+/** \brief OCDS Control and Status */
+typedef struct _Ifx_PSI5S_OCS_Bits
+{
+ unsigned int reserved_0:24; /**< \brief \internal Reserved */
+ unsigned int SUS:4; /**< \brief [27:24] OCDS Suspend Control (rw) */
+ unsigned int SUS_P:1; /**< \brief [28:28] SUS Write Protection (w) */
+ unsigned int SUSSTA:1; /**< \brief [29:29] Suspend State (rh) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_PSI5S_OCS_Bits;
+
+/** \brief Pulse Generation Control Register */
+typedef struct _Ifx_PSI5S_PGC_Bits
+{
+ unsigned int TXCMD:5; /**< \brief [4:0] TX Command (rw) */
+ unsigned int reserved_5:3; /**< \brief \internal Reserved */
+ unsigned int ATXCMD:5; /**< \brief [12:8] Alternate TX Command (rw) */
+ unsigned int reserved_13:2; /**< \brief \internal Reserved */
+ unsigned int TBS:1; /**< \brief [15:15] Time Base Select (rw) */
+ unsigned int ETB:3; /**< \brief [18:16] External Time Base Select (rw) */
+ unsigned int PTE:1; /**< \brief [19:19] Periodic Trigger Enable (rw) */
+ unsigned int ETS:3; /**< \brief [22:20] External Trigger Select (rw) */
+ unsigned int ETE:1; /**< \brief [23:23] External Trigger Enable (rw) */
+ unsigned int reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_PSI5S_PGC_Bits;
+
+/** \brief Receive Buffer Register */
+typedef struct _Ifx_PSI5S_RBUF_Bits
+{
+ unsigned int RD_VALUE:9; /**< \brief [8:0] Receive Data Register Value (rh) */
+ unsigned int reserved_9:23; /**< \brief \internal Reserved */
+} Ifx_PSI5S_RBUF_Bits;
+
+/** \brief Receiver Control Register A */
+typedef struct _Ifx_PSI5S_RCRA_Bits
+{
+ unsigned int CRC0:1; /**< \brief [0:0] CRC or Parity Selection (rw) */
+ unsigned int CRC1:1; /**< \brief [1:1] CRC or Parity Selection (rw) */
+ unsigned int CRC2:1; /**< \brief [2:2] CRC or Parity Selection (rw) */
+ unsigned int CRC3:1; /**< \brief [3:3] CRC or Parity Selection (rw) */
+ unsigned int CRC4:1; /**< \brief [4:4] CRC or Parity Selection (rw) */
+ unsigned int CRC5:1; /**< \brief [5:5] CRC or Parity Selection (rw) */
+ unsigned int TSEN:1; /**< \brief [6:6] Time Stamp Enable (rw) */
+ unsigned int TSP:1; /**< \brief [7:7] Time Stamp Select (rw) */
+ unsigned int TSTS:1; /**< \brief [8:8] Time Stamp Trigger Select (rw) */
+ unsigned int FIDS:1; /**< \brief [9:9] Frame ID Select (rw) */
+ unsigned int WDMS:1; /**< \brief [10:10] Watch Dog Timer Mode Select (rw) */
+ unsigned int reserved_11:5; /**< \brief \internal Reserved */
+ unsigned int UFC0:2; /**< \brief [17:16] UART Frame Count per Packet Frame in Slot 0 (rw) */
+ unsigned int UFC1:2; /**< \brief [19:18] UART Frame Count per Packet Frame in Slot 1 (rw) */
+ unsigned int UFC2:2; /**< \brief [21:20] UART Frame Count per Packet Frame in Slot 2 (rw) */
+ unsigned int UFC3:2; /**< \brief [23:22] UART Frame Count per Packet Frame in Slot 3 (rw) */
+ unsigned int UFC4:2; /**< \brief [25:24] UART Frame Count per Packet Frame in Slot 4 (rw) */
+ unsigned int UFC5:2; /**< \brief [27:26] UART Frame Count per Packet Frame in Slot 5 (rw) */
+ unsigned int reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_PSI5S_RCRA_Bits;
+
+/** \brief Receiver Control Register B */
+typedef struct _Ifx_PSI5S_RCRB_Bits
+{
+ unsigned int PDL0:5; /**< \brief [4:0] Payload Data Length (rw) */
+ unsigned int PDL1:5; /**< \brief [9:5] Payload Data Length (rw) */
+ unsigned int PDL2:5; /**< \brief [14:10] Payload Data Length (rw) */
+ unsigned int PDL3:5; /**< \brief [19:15] Payload Data Length (rw) */
+ unsigned int PDL4:5; /**< \brief [24:20] Payload Data Length (rw) */
+ unsigned int PDL5:5; /**< \brief [29:25] Payload Data Length (rw) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_PSI5S_RCRB_Bits;
+
+/** \brief Receive Data Register */
+typedef struct _Ifx_PSI5S_RDR_Bits
+{
+ unsigned int RD0:1; /**< \brief [0:0] PSI5 Receive Data (r) */
+ unsigned int RD1:1; /**< \brief [1:1] PSI5 Receive Data (r) */
+ unsigned int RD2:1; /**< \brief [2:2] PSI5 Receive Data (r) */
+ unsigned int RD3:1; /**< \brief [3:3] PSI5 Receive Data (r) */
+ unsigned int RD4:1; /**< \brief [4:4] PSI5 Receive Data (r) */
+ unsigned int RD5:1; /**< \brief [5:5] PSI5 Receive Data (r) */
+ unsigned int RD6:1; /**< \brief [6:6] PSI5 Receive Data (r) */
+ unsigned int RD7:1; /**< \brief [7:7] PSI5 Receive Data (r) */
+ unsigned int RD8:1; /**< \brief [8:8] PSI5 Receive Data (r) */
+ unsigned int RD9:1; /**< \brief [9:9] PSI5 Receive Data (r) */
+ unsigned int RD10:1; /**< \brief [10:10] PSI5 Receive Data (r) */
+ unsigned int RD11:1; /**< \brief [11:11] PSI5 Receive Data (r) */
+ unsigned int RD12:1; /**< \brief [12:12] PSI5 Receive Data (r) */
+ unsigned int RD13:1; /**< \brief [13:13] PSI5 Receive Data (r) */
+ unsigned int RD14:1; /**< \brief [14:14] PSI5 Receive Data (r) */
+ unsigned int RD15:1; /**< \brief [15:15] PSI5 Receive Data (r) */
+ unsigned int RD16:1; /**< \brief [16:16] PSI5 Receive Data (r) */
+ unsigned int RD17:1; /**< \brief [17:17] PSI5 Receive Data (r) */
+ unsigned int RD18:1; /**< \brief [18:18] PSI5 Receive Data (r) */
+ unsigned int RD19:1; /**< \brief [19:19] PSI5 Receive Data (r) */
+ unsigned int RD20:1; /**< \brief [20:20] PSI5 Receive Data (r) */
+ unsigned int RD21:1; /**< \brief [21:21] PSI5 Receive Data (r) */
+ unsigned int RD22:1; /**< \brief [22:22] PSI5 Receive Data (r) */
+ unsigned int RD23:1; /**< \brief [23:23] PSI5 Receive Data (r) */
+ unsigned int RD24:1; /**< \brief [24:24] PSI5 Receive Data (r) */
+ unsigned int RD25:1; /**< \brief [25:25] PSI5 Receive Data (r) */
+ unsigned int RD26:1; /**< \brief [26:26] PSI5 Receive Data (r) */
+ unsigned int RD27:1; /**< \brief [27:27] PSI5 Receive Data (r) */
+ unsigned int PFC:4; /**< \brief [31:28] Packet Frame Count (r) */
+} Ifx_PSI5S_RDR_Bits;
+
+/** \brief Receive Status Register */
+typedef struct _Ifx_PSI5S_RDS_Bits
+{
+ unsigned int XCRC0:1; /**< \brief [0:0] XCRC (r) */
+ unsigned int XCRC1:1; /**< \brief [1:1] XCRC (r) */
+ unsigned int XCRC2:1; /**< \brief [2:2] XCRC (r) */
+ unsigned int XCRC3:1; /**< \brief [3:3] XCRC (r) */
+ unsigned int XCRC4:1; /**< \brief [4:4] XCRC (r) */
+ unsigned int XCRC5:1; /**< \brief [5:5] XCRC (r) */
+ unsigned int XCRCI:1; /**< \brief [6:6] XCRC Error Flag (r) */
+ unsigned int CRC0:1; /**< \brief [7:7] CRC (r) */
+ unsigned int CRC1:1; /**< \brief [8:8] CRC (r) */
+ unsigned int CRC2:1; /**< \brief [9:9] CRC (r) */
+ unsigned int CRCI:1; /**< \brief [10:10] CRC Error Flag (r) */
+ unsigned int ERR0:1; /**< \brief [11:11] Error signalling Flag 0 (r) */
+ unsigned int ERR1:1; /**< \brief [12:12] Error signalling Flag 1 (r) */
+ unsigned int HDI:1; /**< \brief [13:13] Header Error Signalled Flag (r) */
+ unsigned int PE:1; /**< \brief [14:14] ASC Parity Error Flag (r) */
+ unsigned int FE:1; /**< \brief [15:15] ASC Framing Error Flag (r) */
+ unsigned int OE:1; /**< \brief [16:16] ASC Overrun Error Flag (r) */
+ unsigned int TEI:1; /**< \brief [17:17] Time Error Flag (r) */
+ unsigned int RBI:1; /**< \brief [18:18] Receive Buffer Overflow Flag (r) */
+ unsigned int FID:3; /**< \brief [21:19] Frame ID (Frame Number) (r) */
+ unsigned int CID:3; /**< \brief [24:22] Channel ID (Channel Number) (r) */
+ unsigned int AFC:3; /**< \brief [27:25] Actual UART Frame Count (r) */
+ unsigned int PFC:4; /**< \brief [31:28] Packet Frame Count (r) */
+} Ifx_PSI5S_RDS_Bits;
+
+/** \brief Send Control Register */
+typedef struct _Ifx_PSI5S_SCR_Bits
+{
+ unsigned int PLL:5; /**< \brief [4:0] Pay Load Length of Registers SDRx (rw) */
+ unsigned int reserved_5:1; /**< \brief \internal Reserved */
+ unsigned int EPS:2; /**< \brief [7:6] Enhanced Protocol Selection (rw) */
+ unsigned int BSC:1; /**< \brief [8:8] Bit Stuffing Control (rw) */
+ unsigned int reserved_9:5; /**< \brief \internal Reserved */
+ unsigned int FLUS:1; /**< \brief [14:14] Flush SDRx (w) */
+ unsigned int reserved_15:7; /**< \brief \internal Reserved */
+ unsigned int CRC:1; /**< \brief [22:22] CRC Generation Control (rw) */
+ unsigned int STA:1; /**< \brief [23:23] Start Sequence Generation Control (rw) */
+ unsigned int reserved_24:2; /**< \brief \internal Reserved */
+ unsigned int TPF:1; /**< \brief [26:26] Transmit in Progress Flag (r) */
+ unsigned int reserved_27:5; /**< \brief \internal Reserved */
+} Ifx_PSI5S_SCR_Bits;
+
+/** \brief Send Data Register */
+typedef struct _Ifx_PSI5S_SDR_Bits
+{
+ unsigned int SD0:1; /**< \brief [0:0] SD0 (rw) */
+ unsigned int SD1:1; /**< \brief [1:1] SD1 (rw) */
+ unsigned int SD2:1; /**< \brief [2:2] SD2 (rw) */
+ unsigned int SD3:1; /**< \brief [3:3] SD3 (rw) */
+ unsigned int SD4:1; /**< \brief [4:4] SD4 (rw) */
+ unsigned int SD5:1; /**< \brief [5:5] SD5 (rw) */
+ unsigned int SD6:1; /**< \brief [6:6] SD6 (rw) */
+ unsigned int SD7:1; /**< \brief [7:7] SD7 (rw) */
+ unsigned int SD8:1; /**< \brief [8:8] SD8 (rw) */
+ unsigned int SD9:1; /**< \brief [9:9] SD9 (rw) */
+ unsigned int SD10:1; /**< \brief [10:10] SD10 (rw) */
+ unsigned int SD11:1; /**< \brief [11:11] SD11 (rw) */
+ unsigned int SD12:1; /**< \brief [12:12] SD12 (rw) */
+ unsigned int SD13:1; /**< \brief [13:13] SD13 (rw) */
+ unsigned int SD14:1; /**< \brief [14:14] SD14 (rw) */
+ unsigned int SD15:1; /**< \brief [15:15] SD15 (rw) */
+ unsigned int SD16:1; /**< \brief [16:16] SD16 (rw) */
+ unsigned int SD17:1; /**< \brief [17:17] SD17 (rw) */
+ unsigned int SD18:1; /**< \brief [18:18] SD18 (rw) */
+ unsigned int SD19:1; /**< \brief [19:19] SD19 (rw) */
+ unsigned int SD20:1; /**< \brief [20:20] SD20 (rw) */
+ unsigned int SD21:1; /**< \brief [21:21] SD21 (rw) */
+ unsigned int SD22:1; /**< \brief [22:22] SD22 (rw) */
+ unsigned int SD23:1; /**< \brief [23:23] SD23 (rw) */
+ unsigned int reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_PSI5S_SDR_Bits;
+
+/** \brief Target Address Register */
+typedef struct _Ifx_PSI5S_TAR_Bits
+{
+ unsigned int reserved_0:2; /**< \brief \internal Reserved */
+ unsigned int TA:30; /**< \brief [31:2] Target Address (r) */
+} Ifx_PSI5S_TAR_Bits;
+
+/** \brief Transmit Buffer Register */
+typedef struct _Ifx_PSI5S_TBUF_Bits
+{
+ unsigned int TD_VALUE:9; /**< \brief [8:0] Transmit Data Register Value (rw) */
+ unsigned int reserved_9:23; /**< \brief \internal Reserved */
+} Ifx_PSI5S_TBUF_Bits;
+
+/** \brief Time Stamp Count Register A */
+typedef struct _Ifx_PSI5S_TSCNTA_Bits
+{
+ unsigned int CTS:24; /**< \brief [23:0] Current Time Stamp for the Module (r) */
+ unsigned int ETB:3; /**< \brief [26:24] External Time Base Select (rw) */
+ unsigned int TBS:1; /**< \brief [27:27] Time Base Select (rw) */
+ unsigned int TBEA:1; /**< \brief [28:28] Time Base Enable TSCNTA (rw) */
+ unsigned int TBEB:1; /**< \brief [29:29] Time Base Enable TSCNTB (rw) */
+ unsigned int CLRA:1; /**< \brief [30:30] Clear Time Stamp Counter A (w) */
+ unsigned int CLRB:1; /**< \brief [31:31] Clear Time Stamp Counter B (w) */
+} Ifx_PSI5S_TSCNTA_Bits;
+
+/** \brief Time Stamp Count Register B */
+typedef struct _Ifx_PSI5S_TSCNTB_Bits
+{
+ unsigned int CTS:24; /**< \brief [23:0] Current Time Stamp for the Module (r) */
+ unsigned int ETB:3; /**< \brief [26:24] External Time Base Select (rw) */
+ unsigned int TBS:1; /**< \brief [27:27] Time Base Select (rw) */
+ unsigned int reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_PSI5S_TSCNTB_Bits;
+
+/** \brief Capture Register */
+typedef struct _Ifx_PSI5S_TSCR_Bits
+{
+ unsigned int TS:24; /**< \brief [23:0] Time Stamp (r) */
+ unsigned int reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_PSI5S_TSCR_Bits;
+
+/** \brief Time Stamp Mirror Register TSM */
+typedef struct _Ifx_PSI5S_TSM_Bits
+{
+ unsigned int TS:24; /**< \brief [23:0] Time Stamp (r) */
+ unsigned int reserved_24:4; /**< \brief \internal Reserved */
+ unsigned int PFC:4; /**< \brief [31:28] Packet Frame Count (r) */
+} Ifx_PSI5S_TSM_Bits;
+
+/** \brief Watch Dog Timer Register */
+typedef struct _Ifx_PSI5S_WDT_Bits
+{
+ unsigned int WDL:24; /**< \brief [23:0] Watch Dog Timer Limit (rw) */
+ unsigned int reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_PSI5S_WDT_Bits;
+
+/** \brief Write Hardware Bits Control Register */
+typedef struct _Ifx_PSI5S_WHBCON_Bits
+{
+ unsigned int reserved_0:4; /**< \brief \internal Reserved */
+ unsigned int CLRREN:1; /**< \brief [4:4] Clear Receiver Enable Bit (w) */
+ unsigned int SETREN:1; /**< \brief [5:5] Set Receiver Enable Bit (w) */
+ unsigned int reserved_6:2; /**< \brief \internal Reserved */
+ unsigned int CLRPE:1; /**< \brief [8:8] Clear Parity Error Flag (w) */
+ unsigned int CLRFE:1; /**< \brief [9:9] Clear Framing Error Flag (w) */
+ unsigned int CLROE:1; /**< \brief [10:10] Clear Overrun Error Flag (w) */
+ unsigned int SETPE:1; /**< \brief [11:11] Set Parity Error Flag (w) */
+ unsigned int SETFE:1; /**< \brief [12:12] Set Framing Error Flag (w) */
+ unsigned int SETOE:1; /**< \brief [13:13] Set Overrun Error Flag (w) */
+ unsigned int reserved_14:18; /**< \brief \internal Reserved */
+} Ifx_PSI5S_WHBCON_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Psi5s_union
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_ACCEN0_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_ACCEN0;
+
+/** \brief Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_ACCEN1_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_ACCEN1;
+
+/** \brief Base Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_BAR_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_BAR;
+
+/** \brief Baud Rate Timer/Reload Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_BG_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_BG;
+
+/** \brief CPU Direct Write Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_CDW_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_CDW;
+
+/** \brief Clock Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_CLC_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_CLC;
+
+/** \brief Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_CON_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_CON;
+
+/** \brief Channel Trigger Value Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_CTV_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_CTV;
+
+/** \brief Frame Counter Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_FCNT_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_FCNT;
+
+/** \brief Fractional Divider for Output CLK Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_FDO_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_FDO;
+
+/** \brief PSI5-S Fractional Divider Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_FDR_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_FDR;
+
+/** \brief Fractional Divider Register for Time Stamp */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_FDRT_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_FDRT;
+
+/** \brief Fractional Divider Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_FDV_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_FDV;
+
+/** \brief Global Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_GCR_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_GCR;
+
+/** \brief Module Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_ID;
+
+/** \brief Interrupt Node Pointer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_INP_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_INP;
+
+/** \brief Interrupt Node Pointer G Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_INPG_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_INPG;
+
+/** \brief Interrupt Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_INTCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_INTCLR;
+
+/** \brief Interrupt Clear Register G */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_INTCLRG_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_INTCLRG;
+
+/** \brief Interrupt Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_INTEN_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_INTEN;
+
+/** \brief Interrupt Enable Register G */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_INTENG_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_INTENG;
+
+/** \brief Interrupt Overview Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_INTOV_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_INTOV;
+
+/** \brief Interrupt Set Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_INTSET_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_INTSET;
+
+/** \brief Interrupt Set Register G */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_INTSETG_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_INTSETG;
+
+/** \brief Interrupt Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_INTSTAT_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_INTSTAT;
+
+/** \brief Interrupt Status Register G */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_INTSTATG_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_INTSTATG;
+
+/** \brief Input and Output Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_IOCR_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_IOCR;
+
+/** \brief Kernel Reset Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_KRST0_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_KRST0;
+
+/** \brief Kernel Reset Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_KRST1_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_KRST1;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_KRSTCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_KRSTCLR;
+
+/** \brief Number of Frames Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_NFC_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_NFC;
+
+/** \brief OCDS Control and Status */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_OCS_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_OCS;
+
+/** \brief Pulse Generation Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_PGC_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_PGC;
+
+/** \brief Receive Buffer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_RBUF_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_RBUF;
+
+/** \brief Receiver Control Register A */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_RCRA_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_RCRA;
+
+/** \brief Receiver Control Register B */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_RCRB_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_RCRB;
+
+/** \brief Receive Data Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_RDR_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_RDR;
+
+/** \brief Receive Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_RDS_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_RDS;
+
+/** \brief Send Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_SCR_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_SCR;
+
+/** \brief Send Data Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_SDR_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_SDR;
+
+/** \brief Target Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_TAR_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_TAR;
+
+/** \brief Transmit Buffer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_TBUF_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_TBUF;
+
+/** \brief Time Stamp Count Register A */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_TSCNTA_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_TSCNTA;
+
+/** \brief Time Stamp Count Register B */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_TSCNTB_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_TSCNTB;
+
+/** \brief Capture Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_TSCR_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_TSCR;
+
+/** \brief Time Stamp Mirror Register TSM */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_TSM_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_TSM;
+
+/** \brief Watch Dog Timer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_WDT_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_WDT;
+
+/** \brief Write Hardware Bits Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_PSI5S_WHBCON_Bits B; /**< \brief Bitfield access */
+} Ifx_PSI5S_WHBCON;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Psi5s_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief PSI5S object */
+typedef volatile struct _Ifx_PSI5S
+{
+ Ifx_PSI5S_CLC CLC; /**< \brief 0, Clock Control Register */
+ unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
+ Ifx_PSI5S_ID ID; /**< \brief 8, Module Identification Register */
+ Ifx_PSI5S_FDR FDR; /**< \brief C, PSI5-S Fractional Divider Register */
+ Ifx_PSI5S_FDRT FDRT; /**< \brief 10, Fractional Divider Register for Time Stamp */
+ Ifx_PSI5S_TSCNTA TSCNTA; /**< \brief 14, Time Stamp Count Register A */
+ Ifx_PSI5S_TSCNTB TSCNTB; /**< \brief 18, Time Stamp Count Register B */
+ Ifx_PSI5S_GCR GCR; /**< \brief 1C, Global Control Register */
+ Ifx_PSI5S_NFC NFC; /**< \brief 20, Number of Frames Control Register */
+ Ifx_PSI5S_FCNT FCNT; /**< \brief 24, Frame Counter Register */
+ Ifx_PSI5S_IOCR IOCR; /**< \brief 28, Input and Output Control Register */
+ unsigned char reserved_2C[4]; /**< \brief 2C, \internal Reserved */
+ Ifx_PSI5S_RCRA RCRA[8]; /**< \brief 30, Receiver Control Register A */
+ Ifx_PSI5S_RCRB RCRB[8]; /**< \brief 50, Receiver Control Register B */
+ Ifx_PSI5S_WDT WDT[8]; /**< \brief 70, Watch Dog Timer Register */
+ Ifx_PSI5S_TSCR TSCR[8]; /**< \brief 90, Capture Register */
+ Ifx_PSI5S_RDS RDS; /**< \brief B0, Receive Status Register */
+ Ifx_PSI5S_RDR RDR; /**< \brief B4, Receive Data Register */
+ Ifx_PSI5S_TSM TSM; /**< \brief B8, Time Stamp Mirror Register TSM */
+ unsigned char reserved_BC[20]; /**< \brief BC, \internal Reserved */
+ Ifx_PSI5S_TAR TAR; /**< \brief D0, Target Address Register */
+ Ifx_PSI5S_BAR BAR; /**< \brief D4, Base Address Register */
+ unsigned char reserved_D8[24]; /**< \brief D8, \internal Reserved */
+ Ifx_PSI5S_PGC PGC[8]; /**< \brief F0, Pulse Generation Control Register */
+ Ifx_PSI5S_CTV CTV[8]; /**< \brief 110, Channel Trigger Value Register */
+ Ifx_PSI5S_SCR SCR[8]; /**< \brief 130, Send Control Register */
+ Ifx_PSI5S_SDR SDR[8]; /**< \brief 150, Send Data Register */
+ Ifx_PSI5S_CDW CDW; /**< \brief 170, CPU Direct Write Register */
+ unsigned char reserved_174[156]; /**< \brief 174, \internal Reserved */
+ Ifx_PSI5S_CON CON; /**< \brief 210, Control Register */
+ Ifx_PSI5S_BG BG; /**< \brief 214, Baud Rate Timer/Reload Register */
+ Ifx_PSI5S_FDV FDV; /**< \brief 218, Fractional Divider Register */
+ Ifx_PSI5S_FDO FDO; /**< \brief 21C, Fractional Divider for Output CLK Register */
+ Ifx_PSI5S_TBUF TBUF; /**< \brief 220, Transmit Buffer Register */
+ Ifx_PSI5S_RBUF RBUF; /**< \brief 224, Receive Buffer Register */
+ unsigned char reserved_228[40]; /**< \brief 228, \internal Reserved */
+ Ifx_PSI5S_WHBCON WHBCON; /**< \brief 250, Write Hardware Bits Control Register */
+ unsigned char reserved_254[12]; /**< \brief 254, \internal Reserved */
+ Ifx_PSI5S_INTSTAT INTSTAT[8]; /**< \brief 260, Interrupt Status Register */
+ Ifx_PSI5S_INTSET INTSET[8]; /**< \brief 280, Interrupt Set Register */
+ Ifx_PSI5S_INTCLR INTCLR[8]; /**< \brief 2A0, Interrupt Clear Register */
+ Ifx_PSI5S_INTEN INTEN[8]; /**< \brief 2C0, Interrupt Enable Register */
+ Ifx_PSI5S_INP INP[8]; /**< \brief 2E0, Interrupt Node Pointer Register */
+ Ifx_PSI5S_INTOV INTOV; /**< \brief 300, Interrupt Overview Register */
+ Ifx_PSI5S_INTSTATG INTSTATG; /**< \brief 304, Interrupt Status Register G */
+ Ifx_PSI5S_INTSETG INTSETG; /**< \brief 308, Interrupt Set Register G */
+ Ifx_PSI5S_INTCLRG INTCLRG; /**< \brief 30C, Interrupt Clear Register G */
+ Ifx_PSI5S_INTENG INTENG; /**< \brief 310, Interrupt Enable Register G */
+ Ifx_PSI5S_INPG INPG; /**< \brief 314, Interrupt Node Pointer G Register */
+ unsigned char reserved_318[180]; /**< \brief 318, \internal Reserved */
+ Ifx_PSI5S_OCS OCS; /**< \brief 3CC, OCDS Control and Status */
+ Ifx_PSI5S_ACCEN0 ACCEN0; /**< \brief 3D0, Access Enable Register 0 */
+ Ifx_PSI5S_ACCEN1 ACCEN1; /**< \brief 3D4, Access Enable Register 1 */
+ Ifx_PSI5S_KRST0 KRST0; /**< \brief 3D8, Kernel Reset Register 0 */
+ Ifx_PSI5S_KRST1 KRST1; /**< \brief 3DC, Kernel Reset Register 1 */
+ Ifx_PSI5S_KRSTCLR KRSTCLR; /**< \brief 3E0, Kernel Reset Status Clear Register */
+ unsigned char reserved_3E4[3100]; /**< \brief 3E4, \internal Reserved */
+} Ifx_PSI5S;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXPSI5S_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxQspi_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxQspi_bf.h
new file mode 100644
index 0000000..ee9094a
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxQspi_bf.h
@@ -0,0 +1,1251 @@
+/**
+ * \file IfxQspi_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Qspi_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Qspi
+ *
+ */
+#ifndef IFXQSPI_BF_H
+#define IFXQSPI_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Qspi_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN0 */
+#define IFX_QSPI_ACCEN0_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN0 */
+#define IFX_QSPI_ACCEN0_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN0 */
+#define IFX_QSPI_ACCEN0_EN0_OFF (0u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN10 */
+#define IFX_QSPI_ACCEN0_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN10 */
+#define IFX_QSPI_ACCEN0_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN10 */
+#define IFX_QSPI_ACCEN0_EN10_OFF (10u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN11 */
+#define IFX_QSPI_ACCEN0_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN11 */
+#define IFX_QSPI_ACCEN0_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN11 */
+#define IFX_QSPI_ACCEN0_EN11_OFF (11u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN12 */
+#define IFX_QSPI_ACCEN0_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN12 */
+#define IFX_QSPI_ACCEN0_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN12 */
+#define IFX_QSPI_ACCEN0_EN12_OFF (12u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN13 */
+#define IFX_QSPI_ACCEN0_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN13 */
+#define IFX_QSPI_ACCEN0_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN13 */
+#define IFX_QSPI_ACCEN0_EN13_OFF (13u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN14 */
+#define IFX_QSPI_ACCEN0_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN14 */
+#define IFX_QSPI_ACCEN0_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN14 */
+#define IFX_QSPI_ACCEN0_EN14_OFF (14u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN15 */
+#define IFX_QSPI_ACCEN0_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN15 */
+#define IFX_QSPI_ACCEN0_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN15 */
+#define IFX_QSPI_ACCEN0_EN15_OFF (15u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN16 */
+#define IFX_QSPI_ACCEN0_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN16 */
+#define IFX_QSPI_ACCEN0_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN16 */
+#define IFX_QSPI_ACCEN0_EN16_OFF (16u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN17 */
+#define IFX_QSPI_ACCEN0_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN17 */
+#define IFX_QSPI_ACCEN0_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN17 */
+#define IFX_QSPI_ACCEN0_EN17_OFF (17u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN18 */
+#define IFX_QSPI_ACCEN0_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN18 */
+#define IFX_QSPI_ACCEN0_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN18 */
+#define IFX_QSPI_ACCEN0_EN18_OFF (18u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN19 */
+#define IFX_QSPI_ACCEN0_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN19 */
+#define IFX_QSPI_ACCEN0_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN19 */
+#define IFX_QSPI_ACCEN0_EN19_OFF (19u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN1 */
+#define IFX_QSPI_ACCEN0_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN1 */
+#define IFX_QSPI_ACCEN0_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN1 */
+#define IFX_QSPI_ACCEN0_EN1_OFF (1u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN20 */
+#define IFX_QSPI_ACCEN0_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN20 */
+#define IFX_QSPI_ACCEN0_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN20 */
+#define IFX_QSPI_ACCEN0_EN20_OFF (20u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN21 */
+#define IFX_QSPI_ACCEN0_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN21 */
+#define IFX_QSPI_ACCEN0_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN21 */
+#define IFX_QSPI_ACCEN0_EN21_OFF (21u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN22 */
+#define IFX_QSPI_ACCEN0_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN22 */
+#define IFX_QSPI_ACCEN0_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN22 */
+#define IFX_QSPI_ACCEN0_EN22_OFF (22u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN23 */
+#define IFX_QSPI_ACCEN0_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN23 */
+#define IFX_QSPI_ACCEN0_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN23 */
+#define IFX_QSPI_ACCEN0_EN23_OFF (23u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN24 */
+#define IFX_QSPI_ACCEN0_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN24 */
+#define IFX_QSPI_ACCEN0_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN24 */
+#define IFX_QSPI_ACCEN0_EN24_OFF (24u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN25 */
+#define IFX_QSPI_ACCEN0_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN25 */
+#define IFX_QSPI_ACCEN0_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN25 */
+#define IFX_QSPI_ACCEN0_EN25_OFF (25u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN26 */
+#define IFX_QSPI_ACCEN0_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN26 */
+#define IFX_QSPI_ACCEN0_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN26 */
+#define IFX_QSPI_ACCEN0_EN26_OFF (26u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN27 */
+#define IFX_QSPI_ACCEN0_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN27 */
+#define IFX_QSPI_ACCEN0_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN27 */
+#define IFX_QSPI_ACCEN0_EN27_OFF (27u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN28 */
+#define IFX_QSPI_ACCEN0_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN28 */
+#define IFX_QSPI_ACCEN0_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN28 */
+#define IFX_QSPI_ACCEN0_EN28_OFF (28u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN29 */
+#define IFX_QSPI_ACCEN0_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN29 */
+#define IFX_QSPI_ACCEN0_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN29 */
+#define IFX_QSPI_ACCEN0_EN29_OFF (29u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN2 */
+#define IFX_QSPI_ACCEN0_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN2 */
+#define IFX_QSPI_ACCEN0_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN2 */
+#define IFX_QSPI_ACCEN0_EN2_OFF (2u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN30 */
+#define IFX_QSPI_ACCEN0_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN30 */
+#define IFX_QSPI_ACCEN0_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN30 */
+#define IFX_QSPI_ACCEN0_EN30_OFF (30u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN31 */
+#define IFX_QSPI_ACCEN0_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN31 */
+#define IFX_QSPI_ACCEN0_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN31 */
+#define IFX_QSPI_ACCEN0_EN31_OFF (31u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN3 */
+#define IFX_QSPI_ACCEN0_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN3 */
+#define IFX_QSPI_ACCEN0_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN3 */
+#define IFX_QSPI_ACCEN0_EN3_OFF (3u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN4 */
+#define IFX_QSPI_ACCEN0_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN4 */
+#define IFX_QSPI_ACCEN0_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN4 */
+#define IFX_QSPI_ACCEN0_EN4_OFF (4u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN5 */
+#define IFX_QSPI_ACCEN0_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN5 */
+#define IFX_QSPI_ACCEN0_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN5 */
+#define IFX_QSPI_ACCEN0_EN5_OFF (5u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN6 */
+#define IFX_QSPI_ACCEN0_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN6 */
+#define IFX_QSPI_ACCEN0_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN6 */
+#define IFX_QSPI_ACCEN0_EN6_OFF (6u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN7 */
+#define IFX_QSPI_ACCEN0_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN7 */
+#define IFX_QSPI_ACCEN0_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN7 */
+#define IFX_QSPI_ACCEN0_EN7_OFF (7u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN8 */
+#define IFX_QSPI_ACCEN0_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN8 */
+#define IFX_QSPI_ACCEN0_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN8 */
+#define IFX_QSPI_ACCEN0_EN8_OFF (8u)
+
+/** \brief Length for Ifx_QSPI_ACCEN0_Bits.EN9 */
+#define IFX_QSPI_ACCEN0_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ACCEN0_Bits.EN9 */
+#define IFX_QSPI_ACCEN0_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ACCEN0_Bits.EN9 */
+#define IFX_QSPI_ACCEN0_EN9_OFF (9u)
+
+/** \brief Length for Ifx_QSPI_BACON_Bits.BYTE */
+#define IFX_QSPI_BACON_BYTE_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_BACON_Bits.BYTE */
+#define IFX_QSPI_BACON_BYTE_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_BACON_Bits.BYTE */
+#define IFX_QSPI_BACON_BYTE_OFF (22u)
+
+/** \brief Length for Ifx_QSPI_BACON_Bits.CS */
+#define IFX_QSPI_BACON_CS_LEN (4u)
+
+/** \brief Mask for Ifx_QSPI_BACON_Bits.CS */
+#define IFX_QSPI_BACON_CS_MSK (0xfu)
+
+/** \brief Offset for Ifx_QSPI_BACON_Bits.CS */
+#define IFX_QSPI_BACON_CS_OFF (28u)
+
+/** \brief Length for Ifx_QSPI_BACON_Bits.DL */
+#define IFX_QSPI_BACON_DL_LEN (5u)
+
+/** \brief Mask for Ifx_QSPI_BACON_Bits.DL */
+#define IFX_QSPI_BACON_DL_MSK (0x1fu)
+
+/** \brief Offset for Ifx_QSPI_BACON_Bits.DL */
+#define IFX_QSPI_BACON_DL_OFF (23u)
+
+/** \brief Length for Ifx_QSPI_BACON_Bits.IDLE */
+#define IFX_QSPI_BACON_IDLE_LEN (3u)
+
+/** \brief Mask for Ifx_QSPI_BACON_Bits.IDLE */
+#define IFX_QSPI_BACON_IDLE_MSK (0x7u)
+
+/** \brief Offset for Ifx_QSPI_BACON_Bits.IDLE */
+#define IFX_QSPI_BACON_IDLE_OFF (4u)
+
+/** \brief Length for Ifx_QSPI_BACON_Bits.IPRE */
+#define IFX_QSPI_BACON_IPRE_LEN (3u)
+
+/** \brief Mask for Ifx_QSPI_BACON_Bits.IPRE */
+#define IFX_QSPI_BACON_IPRE_MSK (0x7u)
+
+/** \brief Offset for Ifx_QSPI_BACON_Bits.IPRE */
+#define IFX_QSPI_BACON_IPRE_OFF (1u)
+
+/** \brief Length for Ifx_QSPI_BACON_Bits.LAST */
+#define IFX_QSPI_BACON_LAST_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_BACON_Bits.LAST */
+#define IFX_QSPI_BACON_LAST_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_BACON_Bits.LAST */
+#define IFX_QSPI_BACON_LAST_OFF (0u)
+
+/** \brief Length for Ifx_QSPI_BACON_Bits.LEAD */
+#define IFX_QSPI_BACON_LEAD_LEN (3u)
+
+/** \brief Mask for Ifx_QSPI_BACON_Bits.LEAD */
+#define IFX_QSPI_BACON_LEAD_MSK (0x7u)
+
+/** \brief Offset for Ifx_QSPI_BACON_Bits.LEAD */
+#define IFX_QSPI_BACON_LEAD_OFF (10u)
+
+/** \brief Length for Ifx_QSPI_BACON_Bits.LPRE */
+#define IFX_QSPI_BACON_LPRE_LEN (3u)
+
+/** \brief Mask for Ifx_QSPI_BACON_Bits.LPRE */
+#define IFX_QSPI_BACON_LPRE_MSK (0x7u)
+
+/** \brief Offset for Ifx_QSPI_BACON_Bits.LPRE */
+#define IFX_QSPI_BACON_LPRE_OFF (7u)
+
+/** \brief Length for Ifx_QSPI_BACON_Bits.MSB */
+#define IFX_QSPI_BACON_MSB_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_BACON_Bits.MSB */
+#define IFX_QSPI_BACON_MSB_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_BACON_Bits.MSB */
+#define IFX_QSPI_BACON_MSB_OFF (21u)
+
+/** \brief Length for Ifx_QSPI_BACON_Bits.PARTYP */
+#define IFX_QSPI_BACON_PARTYP_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_BACON_Bits.PARTYP */
+#define IFX_QSPI_BACON_PARTYP_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_BACON_Bits.PARTYP */
+#define IFX_QSPI_BACON_PARTYP_OFF (19u)
+
+/** \brief Length for Ifx_QSPI_BACON_Bits.TPRE */
+#define IFX_QSPI_BACON_TPRE_LEN (3u)
+
+/** \brief Mask for Ifx_QSPI_BACON_Bits.TPRE */
+#define IFX_QSPI_BACON_TPRE_MSK (0x7u)
+
+/** \brief Offset for Ifx_QSPI_BACON_Bits.TPRE */
+#define IFX_QSPI_BACON_TPRE_OFF (13u)
+
+/** \brief Length for Ifx_QSPI_BACON_Bits.TRAIL */
+#define IFX_QSPI_BACON_TRAIL_LEN (3u)
+
+/** \brief Mask for Ifx_QSPI_BACON_Bits.TRAIL */
+#define IFX_QSPI_BACON_TRAIL_MSK (0x7u)
+
+/** \brief Offset for Ifx_QSPI_BACON_Bits.TRAIL */
+#define IFX_QSPI_BACON_TRAIL_OFF (16u)
+
+/** \brief Length for Ifx_QSPI_BACON_Bits.UINT */
+#define IFX_QSPI_BACON_UINT_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_BACON_Bits.UINT */
+#define IFX_QSPI_BACON_UINT_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_BACON_Bits.UINT */
+#define IFX_QSPI_BACON_UINT_OFF (20u)
+
+/** \brief Length for Ifx_QSPI_BACONENTRY_Bits.E */
+#define IFX_QSPI_BACONENTRY_E_LEN (32u)
+
+/** \brief Mask for Ifx_QSPI_BACONENTRY_Bits.E */
+#define IFX_QSPI_BACONENTRY_E_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_QSPI_BACONENTRY_Bits.E */
+#define IFX_QSPI_BACONENTRY_E_OFF (0u)
+
+/** \brief Length for Ifx_QSPI_CAPCON_Bits.CAP */
+#define IFX_QSPI_CAPCON_CAP_LEN (15u)
+
+/** \brief Mask for Ifx_QSPI_CAPCON_Bits.CAP */
+#define IFX_QSPI_CAPCON_CAP_MSK (0x7fffu)
+
+/** \brief Offset for Ifx_QSPI_CAPCON_Bits.CAP */
+#define IFX_QSPI_CAPCON_CAP_OFF (0u)
+
+/** \brief Length for Ifx_QSPI_CAPCON_Bits.CAPC */
+#define IFX_QSPI_CAPCON_CAPC_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_CAPCON_Bits.CAPC */
+#define IFX_QSPI_CAPCON_CAPC_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_CAPCON_Bits.CAPC */
+#define IFX_QSPI_CAPCON_CAPC_OFF (28u)
+
+/** \brief Length for Ifx_QSPI_CAPCON_Bits.CAPF */
+#define IFX_QSPI_CAPCON_CAPF_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_CAPCON_Bits.CAPF */
+#define IFX_QSPI_CAPCON_CAPF_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_CAPCON_Bits.CAPF */
+#define IFX_QSPI_CAPCON_CAPF_OFF (30u)
+
+/** \brief Length for Ifx_QSPI_CAPCON_Bits.CAPS */
+#define IFX_QSPI_CAPCON_CAPS_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_CAPCON_Bits.CAPS */
+#define IFX_QSPI_CAPCON_CAPS_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_CAPCON_Bits.CAPS */
+#define IFX_QSPI_CAPCON_CAPS_OFF (29u)
+
+/** \brief Length for Ifx_QSPI_CAPCON_Bits.CAPSEL */
+#define IFX_QSPI_CAPCON_CAPSEL_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_CAPCON_Bits.CAPSEL */
+#define IFX_QSPI_CAPCON_CAPSEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_CAPCON_Bits.CAPSEL */
+#define IFX_QSPI_CAPCON_CAPSEL_OFF (31u)
+
+/** \brief Length for Ifx_QSPI_CAPCON_Bits.EDGECON */
+#define IFX_QSPI_CAPCON_EDGECON_LEN (2u)
+
+/** \brief Mask for Ifx_QSPI_CAPCON_Bits.EDGECON */
+#define IFX_QSPI_CAPCON_EDGECON_MSK (0x3u)
+
+/** \brief Offset for Ifx_QSPI_CAPCON_Bits.EDGECON */
+#define IFX_QSPI_CAPCON_EDGECON_OFF (16u)
+
+/** \brief Length for Ifx_QSPI_CAPCON_Bits.EN */
+#define IFX_QSPI_CAPCON_EN_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_CAPCON_Bits.EN */
+#define IFX_QSPI_CAPCON_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_CAPCON_Bits.EN */
+#define IFX_QSPI_CAPCON_EN_OFF (20u)
+
+/** \brief Length for Ifx_QSPI_CAPCON_Bits.INS */
+#define IFX_QSPI_CAPCON_INS_LEN (2u)
+
+/** \brief Mask for Ifx_QSPI_CAPCON_Bits.INS */
+#define IFX_QSPI_CAPCON_INS_MSK (0x3u)
+
+/** \brief Offset for Ifx_QSPI_CAPCON_Bits.INS */
+#define IFX_QSPI_CAPCON_INS_OFF (18u)
+
+/** \brief Length for Ifx_QSPI_CAPCON_Bits.OVF */
+#define IFX_QSPI_CAPCON_OVF_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_CAPCON_Bits.OVF */
+#define IFX_QSPI_CAPCON_OVF_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_CAPCON_Bits.OVF */
+#define IFX_QSPI_CAPCON_OVF_OFF (15u)
+
+/** \brief Length for Ifx_QSPI_CLC_Bits.DISR */
+#define IFX_QSPI_CLC_DISR_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_CLC_Bits.DISR */
+#define IFX_QSPI_CLC_DISR_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_CLC_Bits.DISR */
+#define IFX_QSPI_CLC_DISR_OFF (0u)
+
+/** \brief Length for Ifx_QSPI_CLC_Bits.DISS */
+#define IFX_QSPI_CLC_DISS_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_CLC_Bits.DISS */
+#define IFX_QSPI_CLC_DISS_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_CLC_Bits.DISS */
+#define IFX_QSPI_CLC_DISS_OFF (1u)
+
+/** \brief Length for Ifx_QSPI_CLC_Bits.EDIS */
+#define IFX_QSPI_CLC_EDIS_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_CLC_Bits.EDIS */
+#define IFX_QSPI_CLC_EDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_CLC_Bits.EDIS */
+#define IFX_QSPI_CLC_EDIS_OFF (3u)
+
+/** \brief Length for Ifx_QSPI_DATAENTRY_Bits.E */
+#define IFX_QSPI_DATAENTRY_E_LEN (32u)
+
+/** \brief Mask for Ifx_QSPI_DATAENTRY_Bits.E */
+#define IFX_QSPI_DATAENTRY_E_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_QSPI_DATAENTRY_Bits.E */
+#define IFX_QSPI_DATAENTRY_E_OFF (0u)
+
+/** \brief Length for Ifx_QSPI_ECON_Bits.A */
+#define IFX_QSPI_ECON_A_LEN (2u)
+
+/** \brief Mask for Ifx_QSPI_ECON_Bits.A */
+#define IFX_QSPI_ECON_A_MSK (0x3u)
+
+/** \brief Offset for Ifx_QSPI_ECON_Bits.A */
+#define IFX_QSPI_ECON_A_OFF (6u)
+
+/** \brief Length for Ifx_QSPI_ECON_Bits.B */
+#define IFX_QSPI_ECON_B_LEN (2u)
+
+/** \brief Mask for Ifx_QSPI_ECON_Bits.B */
+#define IFX_QSPI_ECON_B_MSK (0x3u)
+
+/** \brief Offset for Ifx_QSPI_ECON_Bits.B */
+#define IFX_QSPI_ECON_B_OFF (8u)
+
+/** \brief Length for Ifx_QSPI_ECON_Bits.BE */
+#define IFX_QSPI_ECON_BE_LEN (2u)
+
+/** \brief Mask for Ifx_QSPI_ECON_Bits.BE */
+#define IFX_QSPI_ECON_BE_MSK (0x3u)
+
+/** \brief Offset for Ifx_QSPI_ECON_Bits.BE */
+#define IFX_QSPI_ECON_BE_OFF (30u)
+
+/** \brief Length for Ifx_QSPI_ECON_Bits.C */
+#define IFX_QSPI_ECON_C_LEN (2u)
+
+/** \brief Mask for Ifx_QSPI_ECON_Bits.C */
+#define IFX_QSPI_ECON_C_MSK (0x3u)
+
+/** \brief Offset for Ifx_QSPI_ECON_Bits.C */
+#define IFX_QSPI_ECON_C_OFF (10u)
+
+/** \brief Length for Ifx_QSPI_ECON_Bits.CPH */
+#define IFX_QSPI_ECON_CPH_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ECON_Bits.CPH */
+#define IFX_QSPI_ECON_CPH_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ECON_Bits.CPH */
+#define IFX_QSPI_ECON_CPH_OFF (12u)
+
+/** \brief Length for Ifx_QSPI_ECON_Bits.CPOL */
+#define IFX_QSPI_ECON_CPOL_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ECON_Bits.CPOL */
+#define IFX_QSPI_ECON_CPOL_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ECON_Bits.CPOL */
+#define IFX_QSPI_ECON_CPOL_OFF (13u)
+
+/** \brief Length for Ifx_QSPI_ECON_Bits.PAREN */
+#define IFX_QSPI_ECON_PAREN_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_ECON_Bits.PAREN */
+#define IFX_QSPI_ECON_PAREN_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_ECON_Bits.PAREN */
+#define IFX_QSPI_ECON_PAREN_OFF (14u)
+
+/** \brief Length for Ifx_QSPI_ECON_Bits.Q */
+#define IFX_QSPI_ECON_Q_LEN (6u)
+
+/** \brief Mask for Ifx_QSPI_ECON_Bits.Q */
+#define IFX_QSPI_ECON_Q_MSK (0x3fu)
+
+/** \brief Offset for Ifx_QSPI_ECON_Bits.Q */
+#define IFX_QSPI_ECON_Q_OFF (0u)
+
+/** \brief Length for Ifx_QSPI_FLAGSCLEAR_Bits.ERRORCLEARS */
+#define IFX_QSPI_FLAGSCLEAR_ERRORCLEARS_LEN (9u)
+
+/** \brief Mask for Ifx_QSPI_FLAGSCLEAR_Bits.ERRORCLEARS */
+#define IFX_QSPI_FLAGSCLEAR_ERRORCLEARS_MSK (0x1ffu)
+
+/** \brief Offset for Ifx_QSPI_FLAGSCLEAR_Bits.ERRORCLEARS */
+#define IFX_QSPI_FLAGSCLEAR_ERRORCLEARS_OFF (0u)
+
+/** \brief Length for Ifx_QSPI_FLAGSCLEAR_Bits.PT1C */
+#define IFX_QSPI_FLAGSCLEAR_PT1C_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_FLAGSCLEAR_Bits.PT1C */
+#define IFX_QSPI_FLAGSCLEAR_PT1C_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_FLAGSCLEAR_Bits.PT1C */
+#define IFX_QSPI_FLAGSCLEAR_PT1C_OFF (11u)
+
+/** \brief Length for Ifx_QSPI_FLAGSCLEAR_Bits.PT2C */
+#define IFX_QSPI_FLAGSCLEAR_PT2C_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_FLAGSCLEAR_Bits.PT2C */
+#define IFX_QSPI_FLAGSCLEAR_PT2C_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_FLAGSCLEAR_Bits.PT2C */
+#define IFX_QSPI_FLAGSCLEAR_PT2C_OFF (12u)
+
+/** \brief Length for Ifx_QSPI_FLAGSCLEAR_Bits.RXC */
+#define IFX_QSPI_FLAGSCLEAR_RXC_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_FLAGSCLEAR_Bits.RXC */
+#define IFX_QSPI_FLAGSCLEAR_RXC_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_FLAGSCLEAR_Bits.RXC */
+#define IFX_QSPI_FLAGSCLEAR_RXC_OFF (10u)
+
+/** \brief Length for Ifx_QSPI_FLAGSCLEAR_Bits.TXC */
+#define IFX_QSPI_FLAGSCLEAR_TXC_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_FLAGSCLEAR_Bits.TXC */
+#define IFX_QSPI_FLAGSCLEAR_TXC_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_FLAGSCLEAR_Bits.TXC */
+#define IFX_QSPI_FLAGSCLEAR_TXC_OFF (9u)
+
+/** \brief Length for Ifx_QSPI_FLAGSCLEAR_Bits.USRC */
+#define IFX_QSPI_FLAGSCLEAR_USRC_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_FLAGSCLEAR_Bits.USRC */
+#define IFX_QSPI_FLAGSCLEAR_USRC_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_FLAGSCLEAR_Bits.USRC */
+#define IFX_QSPI_FLAGSCLEAR_USRC_OFF (15u)
+
+/** \brief Length for Ifx_QSPI_GLOBALCON1_Bits.ERRORENS */
+#define IFX_QSPI_GLOBALCON1_ERRORENS_LEN (9u)
+
+/** \brief Mask for Ifx_QSPI_GLOBALCON1_Bits.ERRORENS */
+#define IFX_QSPI_GLOBALCON1_ERRORENS_MSK (0x1ffu)
+
+/** \brief Offset for Ifx_QSPI_GLOBALCON1_Bits.ERRORENS */
+#define IFX_QSPI_GLOBALCON1_ERRORENS_OFF (0u)
+
+/** \brief Length for Ifx_QSPI_GLOBALCON1_Bits.PT1 */
+#define IFX_QSPI_GLOBALCON1_PT1_LEN (3u)
+
+/** \brief Mask for Ifx_QSPI_GLOBALCON1_Bits.PT1 */
+#define IFX_QSPI_GLOBALCON1_PT1_MSK (0x7u)
+
+/** \brief Offset for Ifx_QSPI_GLOBALCON1_Bits.PT1 */
+#define IFX_QSPI_GLOBALCON1_PT1_OFF (20u)
+
+/** \brief Length for Ifx_QSPI_GLOBALCON1_Bits.PT1EN */
+#define IFX_QSPI_GLOBALCON1_PT1EN_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_GLOBALCON1_Bits.PT1EN */
+#define IFX_QSPI_GLOBALCON1_PT1EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_GLOBALCON1_Bits.PT1EN */
+#define IFX_QSPI_GLOBALCON1_PT1EN_OFF (11u)
+
+/** \brief Length for Ifx_QSPI_GLOBALCON1_Bits.PT2 */
+#define IFX_QSPI_GLOBALCON1_PT2_LEN (3u)
+
+/** \brief Mask for Ifx_QSPI_GLOBALCON1_Bits.PT2 */
+#define IFX_QSPI_GLOBALCON1_PT2_MSK (0x7u)
+
+/** \brief Offset for Ifx_QSPI_GLOBALCON1_Bits.PT2 */
+#define IFX_QSPI_GLOBALCON1_PT2_OFF (23u)
+
+/** \brief Length for Ifx_QSPI_GLOBALCON1_Bits.PT2EN */
+#define IFX_QSPI_GLOBALCON1_PT2EN_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_GLOBALCON1_Bits.PT2EN */
+#define IFX_QSPI_GLOBALCON1_PT2EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_GLOBALCON1_Bits.PT2EN */
+#define IFX_QSPI_GLOBALCON1_PT2EN_OFF (12u)
+
+/** \brief Length for Ifx_QSPI_GLOBALCON1_Bits.RXEN */
+#define IFX_QSPI_GLOBALCON1_RXEN_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_GLOBALCON1_Bits.RXEN */
+#define IFX_QSPI_GLOBALCON1_RXEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_GLOBALCON1_Bits.RXEN */
+#define IFX_QSPI_GLOBALCON1_RXEN_OFF (10u)
+
+/** \brief Length for Ifx_QSPI_GLOBALCON1_Bits.RXFIFOINT */
+#define IFX_QSPI_GLOBALCON1_RXFIFOINT_LEN (2u)
+
+/** \brief Mask for Ifx_QSPI_GLOBALCON1_Bits.RXFIFOINT */
+#define IFX_QSPI_GLOBALCON1_RXFIFOINT_MSK (0x3u)
+
+/** \brief Offset for Ifx_QSPI_GLOBALCON1_Bits.RXFIFOINT */
+#define IFX_QSPI_GLOBALCON1_RXFIFOINT_OFF (18u)
+
+/** \brief Length for Ifx_QSPI_GLOBALCON1_Bits.RXFM */
+#define IFX_QSPI_GLOBALCON1_RXFM_LEN (2u)
+
+/** \brief Mask for Ifx_QSPI_GLOBALCON1_Bits.RXFM */
+#define IFX_QSPI_GLOBALCON1_RXFM_MSK (0x3u)
+
+/** \brief Offset for Ifx_QSPI_GLOBALCON1_Bits.RXFM */
+#define IFX_QSPI_GLOBALCON1_RXFM_OFF (28u)
+
+/** \brief Length for Ifx_QSPI_GLOBALCON1_Bits.TXEN */
+#define IFX_QSPI_GLOBALCON1_TXEN_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_GLOBALCON1_Bits.TXEN */
+#define IFX_QSPI_GLOBALCON1_TXEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_GLOBALCON1_Bits.TXEN */
+#define IFX_QSPI_GLOBALCON1_TXEN_OFF (9u)
+
+/** \brief Length for Ifx_QSPI_GLOBALCON1_Bits.TXFIFOINT */
+#define IFX_QSPI_GLOBALCON1_TXFIFOINT_LEN (2u)
+
+/** \brief Mask for Ifx_QSPI_GLOBALCON1_Bits.TXFIFOINT */
+#define IFX_QSPI_GLOBALCON1_TXFIFOINT_MSK (0x3u)
+
+/** \brief Offset for Ifx_QSPI_GLOBALCON1_Bits.TXFIFOINT */
+#define IFX_QSPI_GLOBALCON1_TXFIFOINT_OFF (16u)
+
+/** \brief Length for Ifx_QSPI_GLOBALCON1_Bits.TXFM */
+#define IFX_QSPI_GLOBALCON1_TXFM_LEN (2u)
+
+/** \brief Mask for Ifx_QSPI_GLOBALCON1_Bits.TXFM */
+#define IFX_QSPI_GLOBALCON1_TXFM_MSK (0x3u)
+
+/** \brief Offset for Ifx_QSPI_GLOBALCON1_Bits.TXFM */
+#define IFX_QSPI_GLOBALCON1_TXFM_OFF (26u)
+
+/** \brief Length for Ifx_QSPI_GLOBALCON1_Bits.USREN */
+#define IFX_QSPI_GLOBALCON1_USREN_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_GLOBALCON1_Bits.USREN */
+#define IFX_QSPI_GLOBALCON1_USREN_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_GLOBALCON1_Bits.USREN */
+#define IFX_QSPI_GLOBALCON1_USREN_OFF (15u)
+
+/** \brief Length for Ifx_QSPI_GLOBALCON_Bits.AREN */
+#define IFX_QSPI_GLOBALCON_AREN_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_GLOBALCON_Bits.AREN */
+#define IFX_QSPI_GLOBALCON_AREN_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_GLOBALCON_Bits.AREN */
+#define IFX_QSPI_GLOBALCON_AREN_OFF (27u)
+
+/** \brief Length for Ifx_QSPI_GLOBALCON_Bits.DEL0 */
+#define IFX_QSPI_GLOBALCON_DEL0_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_GLOBALCON_Bits.DEL0 */
+#define IFX_QSPI_GLOBALCON_DEL0_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_GLOBALCON_Bits.DEL0 */
+#define IFX_QSPI_GLOBALCON_DEL0_OFF (15u)
+
+/** \brief Length for Ifx_QSPI_GLOBALCON_Bits.EN */
+#define IFX_QSPI_GLOBALCON_EN_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_GLOBALCON_Bits.EN */
+#define IFX_QSPI_GLOBALCON_EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_GLOBALCON_Bits.EN */
+#define IFX_QSPI_GLOBALCON_EN_OFF (24u)
+
+/** \brief Length for Ifx_QSPI_GLOBALCON_Bits.EXPECT */
+#define IFX_QSPI_GLOBALCON_EXPECT_LEN (4u)
+
+/** \brief Mask for Ifx_QSPI_GLOBALCON_Bits.EXPECT */
+#define IFX_QSPI_GLOBALCON_EXPECT_MSK (0xfu)
+
+/** \brief Offset for Ifx_QSPI_GLOBALCON_Bits.EXPECT */
+#define IFX_QSPI_GLOBALCON_EXPECT_OFF (10u)
+
+/** \brief Length for Ifx_QSPI_GLOBALCON_Bits.LB */
+#define IFX_QSPI_GLOBALCON_LB_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_GLOBALCON_Bits.LB */
+#define IFX_QSPI_GLOBALCON_LB_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_GLOBALCON_Bits.LB */
+#define IFX_QSPI_GLOBALCON_LB_OFF (14u)
+
+/** \brief Length for Ifx_QSPI_GLOBALCON_Bits.MS */
+#define IFX_QSPI_GLOBALCON_MS_LEN (2u)
+
+/** \brief Mask for Ifx_QSPI_GLOBALCON_Bits.MS */
+#define IFX_QSPI_GLOBALCON_MS_MSK (0x3u)
+
+/** \brief Offset for Ifx_QSPI_GLOBALCON_Bits.MS */
+#define IFX_QSPI_GLOBALCON_MS_OFF (25u)
+
+/** \brief Length for Ifx_QSPI_GLOBALCON_Bits.RESETS */
+#define IFX_QSPI_GLOBALCON_RESETS_LEN (4u)
+
+/** \brief Mask for Ifx_QSPI_GLOBALCON_Bits.RESETS */
+#define IFX_QSPI_GLOBALCON_RESETS_MSK (0xfu)
+
+/** \brief Offset for Ifx_QSPI_GLOBALCON_Bits.RESETS */
+#define IFX_QSPI_GLOBALCON_RESETS_OFF (28u)
+
+/** \brief Length for Ifx_QSPI_GLOBALCON_Bits.SI */
+#define IFX_QSPI_GLOBALCON_SI_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_GLOBALCON_Bits.SI */
+#define IFX_QSPI_GLOBALCON_SI_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_GLOBALCON_Bits.SI */
+#define IFX_QSPI_GLOBALCON_SI_OFF (9u)
+
+/** \brief Length for Ifx_QSPI_GLOBALCON_Bits.SRF */
+#define IFX_QSPI_GLOBALCON_SRF_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_GLOBALCON_Bits.SRF */
+#define IFX_QSPI_GLOBALCON_SRF_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_GLOBALCON_Bits.SRF */
+#define IFX_QSPI_GLOBALCON_SRF_OFF (21u)
+
+/** \brief Length for Ifx_QSPI_GLOBALCON_Bits.STIP */
+#define IFX_QSPI_GLOBALCON_STIP_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_GLOBALCON_Bits.STIP */
+#define IFX_QSPI_GLOBALCON_STIP_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_GLOBALCON_Bits.STIP */
+#define IFX_QSPI_GLOBALCON_STIP_OFF (22u)
+
+/** \brief Length for Ifx_QSPI_GLOBALCON_Bits.STROBE */
+#define IFX_QSPI_GLOBALCON_STROBE_LEN (5u)
+
+/** \brief Mask for Ifx_QSPI_GLOBALCON_Bits.STROBE */
+#define IFX_QSPI_GLOBALCON_STROBE_MSK (0x1fu)
+
+/** \brief Offset for Ifx_QSPI_GLOBALCON_Bits.STROBE */
+#define IFX_QSPI_GLOBALCON_STROBE_OFF (16u)
+
+/** \brief Length for Ifx_QSPI_GLOBALCON_Bits.TQ */
+#define IFX_QSPI_GLOBALCON_TQ_LEN (8u)
+
+/** \brief Mask for Ifx_QSPI_GLOBALCON_Bits.TQ */
+#define IFX_QSPI_GLOBALCON_TQ_MSK (0xffu)
+
+/** \brief Offset for Ifx_QSPI_GLOBALCON_Bits.TQ */
+#define IFX_QSPI_GLOBALCON_TQ_OFF (0u)
+
+/** \brief Length for Ifx_QSPI_ID_Bits.MODNUMBER */
+#define IFX_QSPI_ID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_QSPI_ID_Bits.MODNUMBER */
+#define IFX_QSPI_ID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_QSPI_ID_Bits.MODNUMBER */
+#define IFX_QSPI_ID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_QSPI_ID_Bits.MODREV */
+#define IFX_QSPI_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_QSPI_ID_Bits.MODREV */
+#define IFX_QSPI_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_QSPI_ID_Bits.MODREV */
+#define IFX_QSPI_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_QSPI_ID_Bits.MODTYPE */
+#define IFX_QSPI_ID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_QSPI_ID_Bits.MODTYPE */
+#define IFX_QSPI_ID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_QSPI_ID_Bits.MODTYPE */
+#define IFX_QSPI_ID_MODTYPE_OFF (8u)
+
+/** \brief Length for Ifx_QSPI_KRST0_Bits.RST */
+#define IFX_QSPI_KRST0_RST_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_KRST0_Bits.RST */
+#define IFX_QSPI_KRST0_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_KRST0_Bits.RST */
+#define IFX_QSPI_KRST0_RST_OFF (0u)
+
+/** \brief Length for Ifx_QSPI_KRST0_Bits.RSTSTAT */
+#define IFX_QSPI_KRST0_RSTSTAT_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_KRST0_Bits.RSTSTAT */
+#define IFX_QSPI_KRST0_RSTSTAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_KRST0_Bits.RSTSTAT */
+#define IFX_QSPI_KRST0_RSTSTAT_OFF (1u)
+
+/** \brief Length for Ifx_QSPI_KRST1_Bits.RST */
+#define IFX_QSPI_KRST1_RST_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_KRST1_Bits.RST */
+#define IFX_QSPI_KRST1_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_KRST1_Bits.RST */
+#define IFX_QSPI_KRST1_RST_OFF (0u)
+
+/** \brief Length for Ifx_QSPI_KRSTCLR_Bits.CLR */
+#define IFX_QSPI_KRSTCLR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_KRSTCLR_Bits.CLR */
+#define IFX_QSPI_KRSTCLR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_KRSTCLR_Bits.CLR */
+#define IFX_QSPI_KRSTCLR_CLR_OFF (0u)
+
+/** \brief Length for Ifx_QSPI_MIXENTRY_Bits.E */
+#define IFX_QSPI_MIXENTRY_E_LEN (32u)
+
+/** \brief Mask for Ifx_QSPI_MIXENTRY_Bits.E */
+#define IFX_QSPI_MIXENTRY_E_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_QSPI_MIXENTRY_Bits.E */
+#define IFX_QSPI_MIXENTRY_E_OFF (0u)
+
+/** \brief Length for Ifx_QSPI_OCS_Bits.SUS */
+#define IFX_QSPI_OCS_SUS_LEN (4u)
+
+/** \brief Mask for Ifx_QSPI_OCS_Bits.SUS */
+#define IFX_QSPI_OCS_SUS_MSK (0xfu)
+
+/** \brief Offset for Ifx_QSPI_OCS_Bits.SUS */
+#define IFX_QSPI_OCS_SUS_OFF (24u)
+
+/** \brief Length for Ifx_QSPI_OCS_Bits.SUS_P */
+#define IFX_QSPI_OCS_SUS_P_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_OCS_Bits.SUS_P */
+#define IFX_QSPI_OCS_SUS_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_OCS_Bits.SUS_P */
+#define IFX_QSPI_OCS_SUS_P_OFF (28u)
+
+/** \brief Length for Ifx_QSPI_OCS_Bits.SUSSTA */
+#define IFX_QSPI_OCS_SUSSTA_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_OCS_Bits.SUSSTA */
+#define IFX_QSPI_OCS_SUSSTA_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_OCS_Bits.SUSSTA */
+#define IFX_QSPI_OCS_SUSSTA_OFF (29u)
+
+/** \brief Length for Ifx_QSPI_PISEL_Bits.MRIS */
+#define IFX_QSPI_PISEL_MRIS_LEN (3u)
+
+/** \brief Mask for Ifx_QSPI_PISEL_Bits.MRIS */
+#define IFX_QSPI_PISEL_MRIS_MSK (0x7u)
+
+/** \brief Offset for Ifx_QSPI_PISEL_Bits.MRIS */
+#define IFX_QSPI_PISEL_MRIS_OFF (0u)
+
+/** \brief Length for Ifx_QSPI_PISEL_Bits.SCIS */
+#define IFX_QSPI_PISEL_SCIS_LEN (3u)
+
+/** \brief Mask for Ifx_QSPI_PISEL_Bits.SCIS */
+#define IFX_QSPI_PISEL_SCIS_MSK (0x7u)
+
+/** \brief Offset for Ifx_QSPI_PISEL_Bits.SCIS */
+#define IFX_QSPI_PISEL_SCIS_OFF (8u)
+
+/** \brief Length for Ifx_QSPI_PISEL_Bits.SLSIS */
+#define IFX_QSPI_PISEL_SLSIS_LEN (3u)
+
+/** \brief Mask for Ifx_QSPI_PISEL_Bits.SLSIS */
+#define IFX_QSPI_PISEL_SLSIS_MSK (0x7u)
+
+/** \brief Offset for Ifx_QSPI_PISEL_Bits.SLSIS */
+#define IFX_QSPI_PISEL_SLSIS_OFF (12u)
+
+/** \brief Length for Ifx_QSPI_PISEL_Bits.SRIS */
+#define IFX_QSPI_PISEL_SRIS_LEN (3u)
+
+/** \brief Mask for Ifx_QSPI_PISEL_Bits.SRIS */
+#define IFX_QSPI_PISEL_SRIS_MSK (0x7u)
+
+/** \brief Offset for Ifx_QSPI_PISEL_Bits.SRIS */
+#define IFX_QSPI_PISEL_SRIS_OFF (4u)
+
+/** \brief Length for Ifx_QSPI_RXEXIT_Bits.E */
+#define IFX_QSPI_RXEXIT_E_LEN (32u)
+
+/** \brief Mask for Ifx_QSPI_RXEXIT_Bits.E */
+#define IFX_QSPI_RXEXIT_E_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_QSPI_RXEXIT_Bits.E */
+#define IFX_QSPI_RXEXIT_E_OFF (0u)
+
+/** \brief Length for Ifx_QSPI_RXEXITD_Bits.E */
+#define IFX_QSPI_RXEXITD_E_LEN (32u)
+
+/** \brief Mask for Ifx_QSPI_RXEXITD_Bits.E */
+#define IFX_QSPI_RXEXITD_E_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_QSPI_RXEXITD_Bits.E */
+#define IFX_QSPI_RXEXITD_E_OFF (0u)
+
+/** \brief Length for Ifx_QSPI_SSOC_Bits.AOL */
+#define IFX_QSPI_SSOC_AOL_LEN (16u)
+
+/** \brief Mask for Ifx_QSPI_SSOC_Bits.AOL */
+#define IFX_QSPI_SSOC_AOL_MSK (0xffffu)
+
+/** \brief Offset for Ifx_QSPI_SSOC_Bits.AOL */
+#define IFX_QSPI_SSOC_AOL_OFF (0u)
+
+/** \brief Length for Ifx_QSPI_SSOC_Bits.OEN */
+#define IFX_QSPI_SSOC_OEN_LEN (16u)
+
+/** \brief Mask for Ifx_QSPI_SSOC_Bits.OEN */
+#define IFX_QSPI_SSOC_OEN_MSK (0xffffu)
+
+/** \brief Offset for Ifx_QSPI_SSOC_Bits.OEN */
+#define IFX_QSPI_SSOC_OEN_OFF (16u)
+
+/** \brief Length for Ifx_QSPI_STATUS1_Bits.BITCOUNT */
+#define IFX_QSPI_STATUS1_BITCOUNT_LEN (8u)
+
+/** \brief Mask for Ifx_QSPI_STATUS1_Bits.BITCOUNT */
+#define IFX_QSPI_STATUS1_BITCOUNT_MSK (0xffu)
+
+/** \brief Offset for Ifx_QSPI_STATUS1_Bits.BITCOUNT */
+#define IFX_QSPI_STATUS1_BITCOUNT_OFF (0u)
+
+/** \brief Length for Ifx_QSPI_STATUS1_Bits.BRD */
+#define IFX_QSPI_STATUS1_BRD_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_STATUS1_Bits.BRD */
+#define IFX_QSPI_STATUS1_BRD_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_STATUS1_Bits.BRD */
+#define IFX_QSPI_STATUS1_BRD_OFF (29u)
+
+/** \brief Length for Ifx_QSPI_STATUS1_Bits.BRDEN */
+#define IFX_QSPI_STATUS1_BRDEN_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_STATUS1_Bits.BRDEN */
+#define IFX_QSPI_STATUS1_BRDEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_STATUS1_Bits.BRDEN */
+#define IFX_QSPI_STATUS1_BRDEN_OFF (28u)
+
+/** \brief Length for Ifx_QSPI_STATUS1_Bits.SPD */
+#define IFX_QSPI_STATUS1_SPD_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_STATUS1_Bits.SPD */
+#define IFX_QSPI_STATUS1_SPD_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_STATUS1_Bits.SPD */
+#define IFX_QSPI_STATUS1_SPD_OFF (31u)
+
+/** \brief Length for Ifx_QSPI_STATUS1_Bits.SPDEN */
+#define IFX_QSPI_STATUS1_SPDEN_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_STATUS1_Bits.SPDEN */
+#define IFX_QSPI_STATUS1_SPDEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_STATUS1_Bits.SPDEN */
+#define IFX_QSPI_STATUS1_SPDEN_OFF (30u)
+
+/** \brief Length for Ifx_QSPI_STATUS_Bits.ERRORFLAGS */
+#define IFX_QSPI_STATUS_ERRORFLAGS_LEN (9u)
+
+/** \brief Mask for Ifx_QSPI_STATUS_Bits.ERRORFLAGS */
+#define IFX_QSPI_STATUS_ERRORFLAGS_MSK (0x1ffu)
+
+/** \brief Offset for Ifx_QSPI_STATUS_Bits.ERRORFLAGS */
+#define IFX_QSPI_STATUS_ERRORFLAGS_OFF (0u)
+
+/** \brief Length for Ifx_QSPI_STATUS_Bits.PHASE */
+#define IFX_QSPI_STATUS_PHASE_LEN (4u)
+
+/** \brief Mask for Ifx_QSPI_STATUS_Bits.PHASE */
+#define IFX_QSPI_STATUS_PHASE_MSK (0xfu)
+
+/** \brief Offset for Ifx_QSPI_STATUS_Bits.PHASE */
+#define IFX_QSPI_STATUS_PHASE_OFF (28u)
+
+/** \brief Length for Ifx_QSPI_STATUS_Bits.PT1F */
+#define IFX_QSPI_STATUS_PT1F_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_STATUS_Bits.PT1F */
+#define IFX_QSPI_STATUS_PT1F_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_STATUS_Bits.PT1F */
+#define IFX_QSPI_STATUS_PT1F_OFF (11u)
+
+/** \brief Length for Ifx_QSPI_STATUS_Bits.PT2F */
+#define IFX_QSPI_STATUS_PT2F_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_STATUS_Bits.PT2F */
+#define IFX_QSPI_STATUS_PT2F_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_STATUS_Bits.PT2F */
+#define IFX_QSPI_STATUS_PT2F_OFF (12u)
+
+/** \brief Length for Ifx_QSPI_STATUS_Bits.RPV */
+#define IFX_QSPI_STATUS_RPV_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_STATUS_Bits.RPV */
+#define IFX_QSPI_STATUS_RPV_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_STATUS_Bits.RPV */
+#define IFX_QSPI_STATUS_RPV_OFF (26u)
+
+/** \brief Length for Ifx_QSPI_STATUS_Bits.RXF */
+#define IFX_QSPI_STATUS_RXF_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_STATUS_Bits.RXF */
+#define IFX_QSPI_STATUS_RXF_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_STATUS_Bits.RXF */
+#define IFX_QSPI_STATUS_RXF_OFF (10u)
+
+/** \brief Length for Ifx_QSPI_STATUS_Bits.RXFIFOLEVEL */
+#define IFX_QSPI_STATUS_RXFIFOLEVEL_LEN (3u)
+
+/** \brief Mask for Ifx_QSPI_STATUS_Bits.RXFIFOLEVEL */
+#define IFX_QSPI_STATUS_RXFIFOLEVEL_MSK (0x7u)
+
+/** \brief Offset for Ifx_QSPI_STATUS_Bits.RXFIFOLEVEL */
+#define IFX_QSPI_STATUS_RXFIFOLEVEL_OFF (19u)
+
+/** \brief Length for Ifx_QSPI_STATUS_Bits.SLAVESEL */
+#define IFX_QSPI_STATUS_SLAVESEL_LEN (4u)
+
+/** \brief Mask for Ifx_QSPI_STATUS_Bits.SLAVESEL */
+#define IFX_QSPI_STATUS_SLAVESEL_MSK (0xfu)
+
+/** \brief Offset for Ifx_QSPI_STATUS_Bits.SLAVESEL */
+#define IFX_QSPI_STATUS_SLAVESEL_OFF (22u)
+
+/** \brief Length for Ifx_QSPI_STATUS_Bits.TPV */
+#define IFX_QSPI_STATUS_TPV_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_STATUS_Bits.TPV */
+#define IFX_QSPI_STATUS_TPV_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_STATUS_Bits.TPV */
+#define IFX_QSPI_STATUS_TPV_OFF (27u)
+
+/** \brief Length for Ifx_QSPI_STATUS_Bits.TXF */
+#define IFX_QSPI_STATUS_TXF_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_STATUS_Bits.TXF */
+#define IFX_QSPI_STATUS_TXF_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_STATUS_Bits.TXF */
+#define IFX_QSPI_STATUS_TXF_OFF (9u)
+
+/** \brief Length for Ifx_QSPI_STATUS_Bits.TXFIFOLEVEL */
+#define IFX_QSPI_STATUS_TXFIFOLEVEL_LEN (3u)
+
+/** \brief Mask for Ifx_QSPI_STATUS_Bits.TXFIFOLEVEL */
+#define IFX_QSPI_STATUS_TXFIFOLEVEL_MSK (0x7u)
+
+/** \brief Offset for Ifx_QSPI_STATUS_Bits.TXFIFOLEVEL */
+#define IFX_QSPI_STATUS_TXFIFOLEVEL_OFF (16u)
+
+/** \brief Length for Ifx_QSPI_STATUS_Bits.USRF */
+#define IFX_QSPI_STATUS_USRF_LEN (1u)
+
+/** \brief Mask for Ifx_QSPI_STATUS_Bits.USRF */
+#define IFX_QSPI_STATUS_USRF_MSK (0x1u)
+
+/** \brief Offset for Ifx_QSPI_STATUS_Bits.USRF */
+#define IFX_QSPI_STATUS_USRF_OFF (15u)
+
+/** \brief Length for Ifx_QSPI_XXLCON_Bits.BYTECOUNT */
+#define IFX_QSPI_XXLCON_BYTECOUNT_LEN (16u)
+
+/** \brief Mask for Ifx_QSPI_XXLCON_Bits.BYTECOUNT */
+#define IFX_QSPI_XXLCON_BYTECOUNT_MSK (0xffffu)
+
+/** \brief Offset for Ifx_QSPI_XXLCON_Bits.BYTECOUNT */
+#define IFX_QSPI_XXLCON_BYTECOUNT_OFF (16u)
+
+/** \brief Length for Ifx_QSPI_XXLCON_Bits.XDL */
+#define IFX_QSPI_XXLCON_XDL_LEN (16u)
+
+/** \brief Mask for Ifx_QSPI_XXLCON_Bits.XDL */
+#define IFX_QSPI_XXLCON_XDL_MSK (0xffffu)
+
+/** \brief Offset for Ifx_QSPI_XXLCON_Bits.XDL */
+#define IFX_QSPI_XXLCON_XDL_OFF (0u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXQSPI_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxQspi_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxQspi_reg.h
new file mode 100644
index 0000000..6201cf8
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxQspi_reg.h
@@ -0,0 +1,534 @@
+/**
+ * \file IfxQspi_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Qspi_Cfg Qspi address
+ * \ingroup IfxLld_Qspi
+ *
+ * \defgroup IfxLld_Qspi_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Qspi_Cfg
+ *
+ * \defgroup IfxLld_Qspi_Cfg_Qspi0 2-QSPI0
+ * \ingroup IfxLld_Qspi_Cfg
+ *
+ * \defgroup IfxLld_Qspi_Cfg_Qspi1 2-QSPI1
+ * \ingroup IfxLld_Qspi_Cfg
+ *
+ * \defgroup IfxLld_Qspi_Cfg_Qspi2 2-QSPI2
+ * \ingroup IfxLld_Qspi_Cfg
+ *
+ * \defgroup IfxLld_Qspi_Cfg_Qspi3 2-QSPI3
+ * \ingroup IfxLld_Qspi_Cfg
+ *
+ */
+#ifndef IFXQSPI_REG_H
+#define IFXQSPI_REG_H 1
+/******************************************************************************/
+#include "IfxQspi_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Qspi_Cfg_BaseAddress
+ * \{ */
+
+/** \brief QSPI object */
+#define MODULE_QSPI0 /*lint --e(923)*/ (*(Ifx_QSPI*)0xF0001C00u)
+
+/** \brief QSPI object */
+#define MODULE_QSPI1 /*lint --e(923)*/ (*(Ifx_QSPI*)0xF0001D00u)
+
+/** \brief QSPI object */
+#define MODULE_QSPI2 /*lint --e(923)*/ (*(Ifx_QSPI*)0xF0001E00u)
+
+/** \brief QSPI object */
+#define MODULE_QSPI3 /*lint --e(923)*/ (*(Ifx_QSPI*)0xF0001F00u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Qspi_Cfg_Qspi0
+ * \{ */
+
+/** \brief FC, Access Enable Register 0 */
+#define QSPI0_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ACCEN0*)0xF0001CFCu)
+
+/** \brief F8, Access Enable Register 1 */
+#define QSPI0_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ACCEN1*)0xF0001CF8u)
+
+/** \brief 18, Basic Configuration Register */
+#define QSPI0_BACON /*lint --e(923)*/ (*(volatile Ifx_QSPI_BACON*)0xF0001C18u)
+
+/** \brief 60, BACON_ENTRY Register */
+#define QSPI0_BACONENTRY /*lint --e(923)*/ (*(volatile Ifx_QSPI_BACONENTRY*)0xF0001C60u)
+
+/** \brief 0, Clock Control Register */
+#define QSPI0_CLC /*lint --e(923)*/ (*(volatile Ifx_QSPI_CLC*)0xF0001C00u)
+
+/** \brief 64, DATA_ENTRY Register */
+#define QSPI0_DATAENTRY0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001C64u)
+
+/** \brief 68, DATA_ENTRY Register */
+#define QSPI0_DATAENTRY1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001C68u)
+
+/** \brief 6C, DATA_ENTRY Register */
+#define QSPI0_DATAENTRY2 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001C6Cu)
+
+/** \brief 70, DATA_ENTRY Register */
+#define QSPI0_DATAENTRY3 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001C70u)
+
+/** \brief 74, DATA_ENTRY Register */
+#define QSPI0_DATAENTRY4 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001C74u)
+
+/** \brief 78, DATA_ENTRY Register */
+#define QSPI0_DATAENTRY5 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001C78u)
+
+/** \brief 7C, DATA_ENTRY Register */
+#define QSPI0_DATAENTRY6 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001C7Cu)
+
+/** \brief 80, DATA_ENTRY Register */
+#define QSPI0_DATAENTRY7 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001C80u)
+
+/** \brief 20, Configuration Extension */
+#define QSPI0_ECON0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001C20u)
+
+/** \brief 24, Configuration Extension */
+#define QSPI0_ECON1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001C24u)
+
+/** \brief 28, Configuration Extension */
+#define QSPI0_ECON2 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001C28u)
+
+/** \brief 2C, Configuration Extension */
+#define QSPI0_ECON3 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001C2Cu)
+
+/** \brief 30, Configuration Extension */
+#define QSPI0_ECON4 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001C30u)
+
+/** \brief 34, Configuration Extension */
+#define QSPI0_ECON5 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001C34u)
+
+/** \brief 38, Configuration Extension */
+#define QSPI0_ECON6 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001C38u)
+
+/** \brief 3C, Configuration Extension */
+#define QSPI0_ECON7 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001C3Cu)
+
+/** \brief 54, Flags Clear Register */
+#define QSPI0_FLAGSCLEAR /*lint --e(923)*/ (*(volatile Ifx_QSPI_FLAGSCLEAR*)0xF0001C54u)
+
+/** \brief 10, Global Configuration Register */
+#define QSPI0_GLOBALCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_GLOBALCON*)0xF0001C10u)
+
+/** \brief 14, Global Configuration Register 1 */
+#define QSPI0_GLOBALCON1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_GLOBALCON1*)0xF0001C14u)
+
+/** \brief 8, Module Identification Register */
+#define QSPI0_ID /*lint --e(923)*/ (*(volatile Ifx_QSPI_ID*)0xF0001C08u)
+
+/** \brief F4, Kernel Reset Register 0 */
+#define QSPI0_KRST0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRST0*)0xF0001CF4u)
+
+/** \brief F0, Kernel Reset Register 1 */
+#define QSPI0_KRST1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRST1*)0xF0001CF0u)
+
+/** \brief EC, Kernel Reset Status Clear Register */
+#define QSPI0_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRSTCLR*)0xF0001CECu)
+
+/** \brief 5C, MIX_ENTRY Register */
+#define QSPI0_MIXENTRY /*lint --e(923)*/ (*(volatile Ifx_QSPI_MIXENTRY*)0xF0001C5Cu)
+
+/** \brief E8, OCDS Control and Status */
+#define QSPI0_OCS /*lint --e(923)*/ (*(volatile Ifx_QSPI_OCS*)0xF0001CE8u)
+
+/** \brief 4, Port Input Select Register */
+#define QSPI0_PISEL /*lint --e(923)*/ (*(volatile Ifx_QSPI_PISEL*)0xF0001C04u)
+
+/** \brief 90, RX_EXIT Register */
+#define QSPI0_RXEXIT /*lint --e(923)*/ (*(volatile Ifx_QSPI_RXEXIT*)0xF0001C90u)
+
+/** \brief 94, RX_EXIT Debug Register */
+#define QSPI0_RXEXITD /*lint --e(923)*/ (*(volatile Ifx_QSPI_RXEXITD*)0xF0001C94u)
+
+/** \brief 48, Slave Select Output Control Register */
+#define QSPI0_SSOC /*lint --e(923)*/ (*(volatile Ifx_QSPI_SSOC*)0xF0001C48u)
+
+/** \brief 40, Status Register */
+#define QSPI0_STATUS /*lint --e(923)*/ (*(volatile Ifx_QSPI_STATUS*)0xF0001C40u)
+
+/** \brief 44, Status Register 1 */
+#define QSPI0_STATUS1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_STATUS1*)0xF0001C44u)
+
+/** \brief 58, Extra Large Data Configuration Register */
+#define QSPI0_XXLCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_XXLCON*)0xF0001C58u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Qspi_Cfg_Qspi1
+ * \{ */
+
+/** \brief FC, Access Enable Register 0 */
+#define QSPI1_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ACCEN0*)0xF0001DFCu)
+
+/** \brief F8, Access Enable Register 1 */
+#define QSPI1_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ACCEN1*)0xF0001DF8u)
+
+/** \brief 18, Basic Configuration Register */
+#define QSPI1_BACON /*lint --e(923)*/ (*(volatile Ifx_QSPI_BACON*)0xF0001D18u)
+
+/** \brief 60, BACON_ENTRY Register */
+#define QSPI1_BACONENTRY /*lint --e(923)*/ (*(volatile Ifx_QSPI_BACONENTRY*)0xF0001D60u)
+
+/** \brief 0, Clock Control Register */
+#define QSPI1_CLC /*lint --e(923)*/ (*(volatile Ifx_QSPI_CLC*)0xF0001D00u)
+
+/** \brief 64, DATA_ENTRY Register */
+#define QSPI1_DATAENTRY0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001D64u)
+
+/** \brief 68, DATA_ENTRY Register */
+#define QSPI1_DATAENTRY1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001D68u)
+
+/** \brief 6C, DATA_ENTRY Register */
+#define QSPI1_DATAENTRY2 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001D6Cu)
+
+/** \brief 70, DATA_ENTRY Register */
+#define QSPI1_DATAENTRY3 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001D70u)
+
+/** \brief 74, DATA_ENTRY Register */
+#define QSPI1_DATAENTRY4 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001D74u)
+
+/** \brief 78, DATA_ENTRY Register */
+#define QSPI1_DATAENTRY5 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001D78u)
+
+/** \brief 7C, DATA_ENTRY Register */
+#define QSPI1_DATAENTRY6 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001D7Cu)
+
+/** \brief 80, DATA_ENTRY Register */
+#define QSPI1_DATAENTRY7 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001D80u)
+
+/** \brief 20, Configuration Extension */
+#define QSPI1_ECON0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001D20u)
+
+/** \brief 24, Configuration Extension */
+#define QSPI1_ECON1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001D24u)
+
+/** \brief 28, Configuration Extension */
+#define QSPI1_ECON2 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001D28u)
+
+/** \brief 2C, Configuration Extension */
+#define QSPI1_ECON3 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001D2Cu)
+
+/** \brief 30, Configuration Extension */
+#define QSPI1_ECON4 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001D30u)
+
+/** \brief 34, Configuration Extension */
+#define QSPI1_ECON5 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001D34u)
+
+/** \brief 38, Configuration Extension */
+#define QSPI1_ECON6 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001D38u)
+
+/** \brief 3C, Configuration Extension */
+#define QSPI1_ECON7 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001D3Cu)
+
+/** \brief 54, Flags Clear Register */
+#define QSPI1_FLAGSCLEAR /*lint --e(923)*/ (*(volatile Ifx_QSPI_FLAGSCLEAR*)0xF0001D54u)
+
+/** \brief 10, Global Configuration Register */
+#define QSPI1_GLOBALCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_GLOBALCON*)0xF0001D10u)
+
+/** \brief 14, Global Configuration Register 1 */
+#define QSPI1_GLOBALCON1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_GLOBALCON1*)0xF0001D14u)
+
+/** \brief 8, Module Identification Register */
+#define QSPI1_ID /*lint --e(923)*/ (*(volatile Ifx_QSPI_ID*)0xF0001D08u)
+
+/** \brief F4, Kernel Reset Register 0 */
+#define QSPI1_KRST0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRST0*)0xF0001DF4u)
+
+/** \brief F0, Kernel Reset Register 1 */
+#define QSPI1_KRST1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRST1*)0xF0001DF0u)
+
+/** \brief EC, Kernel Reset Status Clear Register */
+#define QSPI1_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRSTCLR*)0xF0001DECu)
+
+/** \brief 5C, MIX_ENTRY Register */
+#define QSPI1_MIXENTRY /*lint --e(923)*/ (*(volatile Ifx_QSPI_MIXENTRY*)0xF0001D5Cu)
+
+/** \brief E8, OCDS Control and Status */
+#define QSPI1_OCS /*lint --e(923)*/ (*(volatile Ifx_QSPI_OCS*)0xF0001DE8u)
+
+/** \brief 4, Port Input Select Register */
+#define QSPI1_PISEL /*lint --e(923)*/ (*(volatile Ifx_QSPI_PISEL*)0xF0001D04u)
+
+/** \brief 90, RX_EXIT Register */
+#define QSPI1_RXEXIT /*lint --e(923)*/ (*(volatile Ifx_QSPI_RXEXIT*)0xF0001D90u)
+
+/** \brief 94, RX_EXIT Debug Register */
+#define QSPI1_RXEXITD /*lint --e(923)*/ (*(volatile Ifx_QSPI_RXEXITD*)0xF0001D94u)
+
+/** \brief 48, Slave Select Output Control Register */
+#define QSPI1_SSOC /*lint --e(923)*/ (*(volatile Ifx_QSPI_SSOC*)0xF0001D48u)
+
+/** \brief 40, Status Register */
+#define QSPI1_STATUS /*lint --e(923)*/ (*(volatile Ifx_QSPI_STATUS*)0xF0001D40u)
+
+/** \brief 44, Status Register 1 */
+#define QSPI1_STATUS1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_STATUS1*)0xF0001D44u)
+
+/** \brief 58, Extra Large Data Configuration Register */
+#define QSPI1_XXLCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_XXLCON*)0xF0001D58u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Qspi_Cfg_Qspi2
+ * \{ */
+
+/** \brief FC, Access Enable Register 0 */
+#define QSPI2_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ACCEN0*)0xF0001EFCu)
+
+/** \brief F8, Access Enable Register 1 */
+#define QSPI2_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ACCEN1*)0xF0001EF8u)
+
+/** \brief 18, Basic Configuration Register */
+#define QSPI2_BACON /*lint --e(923)*/ (*(volatile Ifx_QSPI_BACON*)0xF0001E18u)
+
+/** \brief 60, BACON_ENTRY Register */
+#define QSPI2_BACONENTRY /*lint --e(923)*/ (*(volatile Ifx_QSPI_BACONENTRY*)0xF0001E60u)
+
+/** \brief A0, Capture Control Register */
+#define QSPI2_CAPCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_CAPCON*)0xF0001EA0u)
+
+/** \brief 0, Clock Control Register */
+#define QSPI2_CLC /*lint --e(923)*/ (*(volatile Ifx_QSPI_CLC*)0xF0001E00u)
+
+/** \brief 64, DATA_ENTRY Register */
+#define QSPI2_DATAENTRY0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001E64u)
+
+/** \brief 68, DATA_ENTRY Register */
+#define QSPI2_DATAENTRY1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001E68u)
+
+/** \brief 6C, DATA_ENTRY Register */
+#define QSPI2_DATAENTRY2 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001E6Cu)
+
+/** \brief 70, DATA_ENTRY Register */
+#define QSPI2_DATAENTRY3 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001E70u)
+
+/** \brief 74, DATA_ENTRY Register */
+#define QSPI2_DATAENTRY4 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001E74u)
+
+/** \brief 78, DATA_ENTRY Register */
+#define QSPI2_DATAENTRY5 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001E78u)
+
+/** \brief 7C, DATA_ENTRY Register */
+#define QSPI2_DATAENTRY6 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001E7Cu)
+
+/** \brief 80, DATA_ENTRY Register */
+#define QSPI2_DATAENTRY7 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001E80u)
+
+/** \brief 20, Configuration Extension */
+#define QSPI2_ECON0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001E20u)
+
+/** \brief 24, Configuration Extension */
+#define QSPI2_ECON1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001E24u)
+
+/** \brief 28, Configuration Extension */
+#define QSPI2_ECON2 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001E28u)
+
+/** \brief 2C, Configuration Extension */
+#define QSPI2_ECON3 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001E2Cu)
+
+/** \brief 30, Configuration Extension */
+#define QSPI2_ECON4 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001E30u)
+
+/** \brief 34, Configuration Extension */
+#define QSPI2_ECON5 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001E34u)
+
+/** \brief 38, Configuration Extension */
+#define QSPI2_ECON6 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001E38u)
+
+/** \brief 3C, Configuration Extension */
+#define QSPI2_ECON7 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001E3Cu)
+
+/** \brief 54, Flags Clear Register */
+#define QSPI2_FLAGSCLEAR /*lint --e(923)*/ (*(volatile Ifx_QSPI_FLAGSCLEAR*)0xF0001E54u)
+
+/** \brief 10, Global Configuration Register */
+#define QSPI2_GLOBALCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_GLOBALCON*)0xF0001E10u)
+
+/** \brief 14, Global Configuration Register 1 */
+#define QSPI2_GLOBALCON1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_GLOBALCON1*)0xF0001E14u)
+
+/** \brief 8, Module Identification Register */
+#define QSPI2_ID /*lint --e(923)*/ (*(volatile Ifx_QSPI_ID*)0xF0001E08u)
+
+/** \brief F4, Kernel Reset Register 0 */
+#define QSPI2_KRST0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRST0*)0xF0001EF4u)
+
+/** \brief F0, Kernel Reset Register 1 */
+#define QSPI2_KRST1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRST1*)0xF0001EF0u)
+
+/** \brief EC, Kernel Reset Status Clear Register */
+#define QSPI2_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRSTCLR*)0xF0001EECu)
+
+/** \brief 5C, MIX_ENTRY Register */
+#define QSPI2_MIXENTRY /*lint --e(923)*/ (*(volatile Ifx_QSPI_MIXENTRY*)0xF0001E5Cu)
+
+/** \brief E8, OCDS Control and Status */
+#define QSPI2_OCS /*lint --e(923)*/ (*(volatile Ifx_QSPI_OCS*)0xF0001EE8u)
+
+/** \brief 4, Port Input Select Register */
+#define QSPI2_PISEL /*lint --e(923)*/ (*(volatile Ifx_QSPI_PISEL*)0xF0001E04u)
+
+/** \brief 90, RX_EXIT Register */
+#define QSPI2_RXEXIT /*lint --e(923)*/ (*(volatile Ifx_QSPI_RXEXIT*)0xF0001E90u)
+
+/** \brief 94, RX_EXIT Debug Register */
+#define QSPI2_RXEXITD /*lint --e(923)*/ (*(volatile Ifx_QSPI_RXEXITD*)0xF0001E94u)
+
+/** \brief 48, Slave Select Output Control Register */
+#define QSPI2_SSOC /*lint --e(923)*/ (*(volatile Ifx_QSPI_SSOC*)0xF0001E48u)
+
+/** \brief 40, Status Register */
+#define QSPI2_STATUS /*lint --e(923)*/ (*(volatile Ifx_QSPI_STATUS*)0xF0001E40u)
+
+/** \brief 44, Status Register 1 */
+#define QSPI2_STATUS1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_STATUS1*)0xF0001E44u)
+
+/** \brief 58, Extra Large Data Configuration Register */
+#define QSPI2_XXLCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_XXLCON*)0xF0001E58u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Qspi_Cfg_Qspi3
+ * \{ */
+
+/** \brief FC, Access Enable Register 0 */
+#define QSPI3_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ACCEN0*)0xF0001FFCu)
+
+/** \brief F8, Access Enable Register 1 */
+#define QSPI3_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ACCEN1*)0xF0001FF8u)
+
+/** \brief 18, Basic Configuration Register */
+#define QSPI3_BACON /*lint --e(923)*/ (*(volatile Ifx_QSPI_BACON*)0xF0001F18u)
+
+/** \brief 60, BACON_ENTRY Register */
+#define QSPI3_BACONENTRY /*lint --e(923)*/ (*(volatile Ifx_QSPI_BACONENTRY*)0xF0001F60u)
+
+/** \brief A0, Capture Control Register */
+#define QSPI3_CAPCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_CAPCON*)0xF0001FA0u)
+
+/** \brief 0, Clock Control Register */
+#define QSPI3_CLC /*lint --e(923)*/ (*(volatile Ifx_QSPI_CLC*)0xF0001F00u)
+
+/** \brief 64, DATA_ENTRY Register */
+#define QSPI3_DATAENTRY0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001F64u)
+
+/** \brief 68, DATA_ENTRY Register */
+#define QSPI3_DATAENTRY1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001F68u)
+
+/** \brief 6C, DATA_ENTRY Register */
+#define QSPI3_DATAENTRY2 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001F6Cu)
+
+/** \brief 70, DATA_ENTRY Register */
+#define QSPI3_DATAENTRY3 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001F70u)
+
+/** \brief 74, DATA_ENTRY Register */
+#define QSPI3_DATAENTRY4 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001F74u)
+
+/** \brief 78, DATA_ENTRY Register */
+#define QSPI3_DATAENTRY5 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001F78u)
+
+/** \brief 7C, DATA_ENTRY Register */
+#define QSPI3_DATAENTRY6 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001F7Cu)
+
+/** \brief 80, DATA_ENTRY Register */
+#define QSPI3_DATAENTRY7 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001F80u)
+
+/** \brief 20, Configuration Extension */
+#define QSPI3_ECON0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001F20u)
+
+/** \brief 24, Configuration Extension */
+#define QSPI3_ECON1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001F24u)
+
+/** \brief 28, Configuration Extension */
+#define QSPI3_ECON2 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001F28u)
+
+/** \brief 2C, Configuration Extension */
+#define QSPI3_ECON3 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001F2Cu)
+
+/** \brief 30, Configuration Extension */
+#define QSPI3_ECON4 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001F30u)
+
+/** \brief 34, Configuration Extension */
+#define QSPI3_ECON5 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001F34u)
+
+/** \brief 38, Configuration Extension */
+#define QSPI3_ECON6 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001F38u)
+
+/** \brief 3C, Configuration Extension */
+#define QSPI3_ECON7 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001F3Cu)
+
+/** \brief 54, Flags Clear Register */
+#define QSPI3_FLAGSCLEAR /*lint --e(923)*/ (*(volatile Ifx_QSPI_FLAGSCLEAR*)0xF0001F54u)
+
+/** \brief 10, Global Configuration Register */
+#define QSPI3_GLOBALCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_GLOBALCON*)0xF0001F10u)
+
+/** \brief 14, Global Configuration Register 1 */
+#define QSPI3_GLOBALCON1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_GLOBALCON1*)0xF0001F14u)
+
+/** \brief 8, Module Identification Register */
+#define QSPI3_ID /*lint --e(923)*/ (*(volatile Ifx_QSPI_ID*)0xF0001F08u)
+
+/** \brief F4, Kernel Reset Register 0 */
+#define QSPI3_KRST0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRST0*)0xF0001FF4u)
+
+/** \brief F0, Kernel Reset Register 1 */
+#define QSPI3_KRST1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRST1*)0xF0001FF0u)
+
+/** \brief EC, Kernel Reset Status Clear Register */
+#define QSPI3_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRSTCLR*)0xF0001FECu)
+
+/** \brief 5C, MIX_ENTRY Register */
+#define QSPI3_MIXENTRY /*lint --e(923)*/ (*(volatile Ifx_QSPI_MIXENTRY*)0xF0001F5Cu)
+
+/** \brief E8, OCDS Control and Status */
+#define QSPI3_OCS /*lint --e(923)*/ (*(volatile Ifx_QSPI_OCS*)0xF0001FE8u)
+
+/** \brief 4, Port Input Select Register */
+#define QSPI3_PISEL /*lint --e(923)*/ (*(volatile Ifx_QSPI_PISEL*)0xF0001F04u)
+
+/** \brief 90, RX_EXIT Register */
+#define QSPI3_RXEXIT /*lint --e(923)*/ (*(volatile Ifx_QSPI_RXEXIT*)0xF0001F90u)
+
+/** \brief 94, RX_EXIT Debug Register */
+#define QSPI3_RXEXITD /*lint --e(923)*/ (*(volatile Ifx_QSPI_RXEXITD*)0xF0001F94u)
+
+/** \brief 48, Slave Select Output Control Register */
+#define QSPI3_SSOC /*lint --e(923)*/ (*(volatile Ifx_QSPI_SSOC*)0xF0001F48u)
+
+/** \brief 40, Status Register */
+#define QSPI3_STATUS /*lint --e(923)*/ (*(volatile Ifx_QSPI_STATUS*)0xF0001F40u)
+
+/** \brief 44, Status Register 1 */
+#define QSPI3_STATUS1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_STATUS1*)0xF0001F44u)
+
+/** \brief 58, Extra Large Data Configuration Register */
+#define QSPI3_XXLCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_XXLCON*)0xF0001F58u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXQSPI_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxQspi_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxQspi_regdef.h
new file mode 100644
index 0000000..e4fedca
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxQspi_regdef.h
@@ -0,0 +1,565 @@
+/**
+ * \file IfxQspi_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Qspi Qspi
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Qspi_Bitfields Bitfields
+ * \ingroup IfxLld_Qspi
+ *
+ * \defgroup IfxLld_Qspi_union Union
+ * \ingroup IfxLld_Qspi
+ *
+ * \defgroup IfxLld_Qspi_struct Struct
+ * \ingroup IfxLld_Qspi
+ *
+ */
+#ifndef IFXQSPI_REGDEF_H
+#define IFXQSPI_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Qspi_Bitfields
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef struct _Ifx_QSPI_ACCEN0_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_QSPI_ACCEN0_Bits;
+
+/** \brief Access Enable Register 1 */
+typedef struct _Ifx_QSPI_ACCEN1_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_QSPI_ACCEN1_Bits;
+
+/** \brief Basic Configuration Register */
+typedef struct _Ifx_QSPI_BACON_Bits
+{
+ unsigned int LAST:1; /**< \brief [0:0] Last Word in a Frame (rh) */
+ unsigned int IPRE:3; /**< \brief [3:1] Prescaler for the Idle Delay (rh) */
+ unsigned int IDLE:3; /**< \brief [6:4] Idle Delay Length (rh) */
+ unsigned int LPRE:3; /**< \brief [9:7] Prescaler for the Leading Delay (rh) */
+ unsigned int LEAD:3; /**< \brief [12:10] Leading Delay Length (rh) */
+ unsigned int TPRE:3; /**< \brief [15:13] Prescaler for the Trailing Delay (rh) */
+ unsigned int TRAIL:3; /**< \brief [18:16] Trailing Delay Length (rh) */
+ unsigned int PARTYP:1; /**< \brief [19:19] Parity Type (rh) */
+ unsigned int UINT:1; /**< \brief [20:20] User Interrupt at the PT1 Event in the Subsequent Frames (rh) */
+ unsigned int MSB:1; /**< \brief [21:21] Shift MSB or LSB First (rh) */
+ unsigned int BYTE:1; /**< \brief [22:22] Byte (rh) */
+ unsigned int DL:5; /**< \brief [27:23] Data Length (rh) */
+ unsigned int CS:4; /**< \brief [31:28] Channel Select (rh) */
+} Ifx_QSPI_BACON_Bits;
+
+/** \brief BACON_ENTRY Register */
+typedef struct _Ifx_QSPI_BACONENTRY_Bits
+{
+ unsigned int E:32; /**< \brief [31:0] Entry Point to the TxFIFO (w) */
+} Ifx_QSPI_BACONENTRY_Bits;
+
+/** \brief Capture Control Register */
+typedef struct _Ifx_QSPI_CAPCON_Bits
+{
+ unsigned int CAP:15; /**< \brief [14:0] Captured Value (rh) */
+ unsigned int OVF:1; /**< \brief [15:15] Overflow Flag (rh) */
+ unsigned int EDGECON:2; /**< \brief [17:16] Edge Configuration (rw) */
+ unsigned int INS:2; /**< \brief [19:18] Input Selection (rw) */
+ unsigned int EN:1; /**< \brief [20:20] Enable Bit of the Capture Timer (rw) */
+ unsigned int reserved_21:7; /**< \brief \internal Reserved */
+ unsigned int CAPC:1; /**< \brief [28:28] Capture Flag Clear (w) */
+ unsigned int CAPS:1; /**< \brief [29:29] Capture Flag Set (w) */
+ unsigned int CAPF:1; /**< \brief [30:30] Capture Flag (rh) */
+ unsigned int CAPSEL:1; /**< \brief [31:31] Capture Interrupt Select Bit (rw) */
+} Ifx_QSPI_CAPCON_Bits;
+
+/** \brief Clock Control Register */
+typedef struct _Ifx_QSPI_CLC_Bits
+{
+ unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
+ unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
+ unsigned int reserved_2:1; /**< \brief \internal Reserved */
+ unsigned int EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control (rw) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_QSPI_CLC_Bits;
+
+/** \brief DATA_ENTRY Register */
+typedef struct _Ifx_QSPI_DATAENTRY_Bits
+{
+ unsigned int E:32; /**< \brief [31:0] Entry Point to the TxFIFO (w) */
+} Ifx_QSPI_DATAENTRY_Bits;
+
+/** \brief Configuration Extension */
+typedef struct _Ifx_QSPI_ECON_Bits
+{
+ unsigned int Q:6; /**< \brief [5:0] Time Quantum (rw) */
+ unsigned int A:2; /**< \brief [7:6] Bit Segment 1 (rw) */
+ unsigned int B:2; /**< \brief [9:8] Bit Segment 2 (rw) */
+ unsigned int C:2; /**< \brief [11:10] Bit Segment 3 (rw) */
+ unsigned int CPH:1; /**< \brief [12:12] Clock Phase (rw) */
+ unsigned int CPOL:1; /**< \brief [13:13] Clock Polarity (rw) */
+ unsigned int PAREN:1; /**< \brief [14:14] Enable Parity Check (rw) */
+ unsigned int reserved_15:15; /**< \brief \internal Reserved */
+ unsigned int BE:2; /**< \brief [31:30] Permutate bytes to / from Big Endian (rw) */
+} Ifx_QSPI_ECON_Bits;
+
+/** \brief Flags Clear Register */
+typedef struct _Ifx_QSPI_FLAGSCLEAR_Bits
+{
+ unsigned int ERRORCLEARS:9; /**< \brief [8:0] Write Only Bits for Clearing the Error Flags (w) */
+ unsigned int TXC:1; /**< \brief [9:9] Transmit Event Flag Clear (w) */
+ unsigned int RXC:1; /**< \brief [10:10] Receive Event Flag Clear (w) */
+ unsigned int PT1C:1; /**< \brief [11:11] PT1 Event Flag Clear (w) */
+ unsigned int PT2C:1; /**< \brief [12:12] PT2 Event Flag Clear (w) */
+ unsigned int reserved_13:2; /**< \brief \internal Reserved */
+ unsigned int USRC:1; /**< \brief [15:15] User Event Flag Clear (w) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_QSPI_FLAGSCLEAR_Bits;
+
+/** \brief Global Configuration Register 1 */
+typedef struct _Ifx_QSPI_GLOBALCON1_Bits
+{
+ unsigned int ERRORENS:9; /**< \brief [8:0] Error Enable Bits (rw) */
+ unsigned int TXEN:1; /**< \brief [9:9] Tx Interrupt Event Enable (rw) */
+ unsigned int RXEN:1; /**< \brief [10:10] RX Interrupt Event Enable (rw) */
+ unsigned int PT1EN:1; /**< \brief [11:11] Interrupt on PT1 Event Enable (rw) */
+ unsigned int PT2EN:1; /**< \brief [12:12] Interrupt on PT2 Event Enable (rw) */
+ unsigned int reserved_13:2; /**< \brief \internal Reserved */
+ unsigned int USREN:1; /**< \brief [15:15] Interrupt on USR Event Enable (rw) */
+ unsigned int TXFIFOINT:2; /**< \brief [17:16] Transmit FIFO Interrupt Threshold (rw) */
+ unsigned int RXFIFOINT:2; /**< \brief [19:18] Receive FIFO Interrupt Threshold (rw) */
+ unsigned int PT1:3; /**< \brief [22:20] Phase Transition Event 1 (rw) */
+ unsigned int PT2:3; /**< \brief [25:23] Phase Transition Event 2 (rw) */
+ unsigned int TXFM:2; /**< \brief [27:26] TXFIFO Mode (rw) */
+ unsigned int RXFM:2; /**< \brief [29:28] RXFIFO Mode (rw) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_QSPI_GLOBALCON1_Bits;
+
+/** \brief Global Configuration Register */
+typedef struct _Ifx_QSPI_GLOBALCON_Bits
+{
+ unsigned int TQ:8; /**< \brief [7:0] Global Time Quantum Length (rw) */
+ unsigned int reserved_8:1; /**< \brief \internal Reserved */
+ unsigned int SI:1; /**< \brief [9:9] Status Injection (rw) */
+ unsigned int EXPECT:4; /**< \brief [13:10] Time-Out Value for the Expect Phase (rw) */
+ unsigned int LB:1; /**< \brief [14:14] Loop-Back Control (rw) */
+ unsigned int DEL0:1; /**< \brief [15:15] Delayed Mode for SLSO0 (rw) */
+ unsigned int STROBE:5; /**< \brief [20:16] Strobe Delay for SLSO0 in Delayed Mode (rw) */
+ unsigned int SRF:1; /**< \brief [21:21] Stop on RxFIFO Full (rw) */
+ unsigned int STIP:1; /**< \brief [22:22] Slave Transmit Idle State Polarity (rw) */
+ unsigned int reserved_23:1; /**< \brief \internal Reserved */
+ unsigned int EN:1; /**< \brief [24:24] Enable Bit (rwh) */
+ unsigned int MS:2; /**< \brief [26:25] Master Slave Mode (rw) */
+ unsigned int AREN:1; /**< \brief [27:27] Automatic Reset Enable (rw) */
+ unsigned int RESETS:4; /**< \brief [31:28] Bits for resetting sub-modules per software (w) */
+} Ifx_QSPI_GLOBALCON_Bits;
+
+/** \brief Module Identification Register */
+typedef struct _Ifx_QSPI_ID_Bits
+{
+ unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
+ unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_QSPI_ID_Bits;
+
+/** \brief Kernel Reset Register 0 */
+typedef struct _Ifx_QSPI_KRST0_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rh) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_QSPI_KRST0_Bits;
+
+/** \brief Kernel Reset Register 1 */
+typedef struct _Ifx_QSPI_KRST1_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_QSPI_KRST1_Bits;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef struct _Ifx_QSPI_KRSTCLR_Bits
+{
+ unsigned int CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_QSPI_KRSTCLR_Bits;
+
+/** \brief MIX_ENTRY Register */
+typedef struct _Ifx_QSPI_MIXENTRY_Bits
+{
+ unsigned int E:32; /**< \brief [31:0] Entry Point to the TxFIFO (w) */
+} Ifx_QSPI_MIXENTRY_Bits;
+
+/** \brief OCDS Control and Status */
+typedef struct _Ifx_QSPI_OCS_Bits
+{
+ unsigned int reserved_0:24; /**< \brief \internal Reserved */
+ unsigned int SUS:4; /**< \brief [27:24] OCDS Suspend Control (rw) */
+ unsigned int SUS_P:1; /**< \brief [28:28] SUS Write Protection (w) */
+ unsigned int SUSSTA:1; /**< \brief [29:29] Suspend State (rh) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_QSPI_OCS_Bits;
+
+/** \brief Port Input Select Register */
+typedef struct _Ifx_QSPI_PISEL_Bits
+{
+ unsigned int MRIS:3; /**< \brief [2:0] Master Mode Receive Input Select (rw) */
+ unsigned int reserved_3:1; /**< \brief \internal Reserved */
+ unsigned int SRIS:3; /**< \brief [6:4] Slave Mode Receive Input Select (rw) */
+ unsigned int reserved_7:1; /**< \brief \internal Reserved */
+ unsigned int SCIS:3; /**< \brief [10:8] Slave Mode Clock Input Select (rw) */
+ unsigned int reserved_11:1; /**< \brief \internal Reserved */
+ unsigned int SLSIS:3; /**< \brief [14:12] Slave Mode Slave Select Input Selection (rw) */
+ unsigned int reserved_15:17; /**< \brief \internal Reserved */
+} Ifx_QSPI_PISEL_Bits;
+
+/** \brief RX_EXIT Register */
+typedef struct _Ifx_QSPI_RXEXIT_Bits
+{
+ unsigned int E:32; /**< \brief [31:0] Read Point from the RxFIFO (r) */
+} Ifx_QSPI_RXEXIT_Bits;
+
+/** \brief RX_EXIT Debug Register */
+typedef struct _Ifx_QSPI_RXEXITD_Bits
+{
+ unsigned int E:32; /**< \brief [31:0] Read Point from the RxFIFO (r) */
+} Ifx_QSPI_RXEXITD_Bits;
+
+/** \brief Slave Select Output Control Register */
+typedef struct _Ifx_QSPI_SSOC_Bits
+{
+ unsigned int AOL:16; /**< \brief [15:0] Active Output Level for the SLSO Outputs (rw) */
+ unsigned int OEN:16; /**< \brief [31:16] Enable Bits for the SLSO Outputs (rw) */
+} Ifx_QSPI_SSOC_Bits;
+
+/** \brief Status Register 1 */
+typedef struct _Ifx_QSPI_STATUS1_Bits
+{
+ unsigned int BITCOUNT:8; /**< \brief [7:0] Number of the bit shifted out (r) */
+ unsigned int reserved_8:20; /**< \brief \internal Reserved */
+ unsigned int BRDEN:1; /**< \brief [28:28] Baud Rate Deviation Enable (rw) */
+ unsigned int BRD:1; /**< \brief [29:29] Baud Rate Deviation Flag (rwh) */
+ unsigned int SPDEN:1; /**< \brief [30:30] Spike Detection Enable (rw) */
+ unsigned int SPD:1; /**< \brief [31:31] Spike Detection Flag (rwh) */
+} Ifx_QSPI_STATUS1_Bits;
+
+/** \brief Status Register */
+typedef struct _Ifx_QSPI_STATUS_Bits
+{
+ unsigned int ERRORFLAGS:9; /**< \brief [8:0] Sticky Flags Signalling Errors (rwh) */
+ unsigned int TXF:1; /**< \brief [9:9] Transmit Interrupt Request Flag (rwh) */
+ unsigned int RXF:1; /**< \brief [10:10] Receive Interrupt Request Flag (rwh) */
+ unsigned int PT1F:1; /**< \brief [11:11] Phase Transition 1 Flag (rwh) */
+ unsigned int PT2F:1; /**< \brief [12:12] Phase Transition 2 Flag (rwh) */
+ unsigned int reserved_13:2; /**< \brief \internal Reserved */
+ unsigned int USRF:1; /**< \brief [15:15] User Interrupt Request Flag (rwh) */
+ unsigned int TXFIFOLEVEL:3; /**< \brief [18:16] TXFIFO Filling Level (rh) */
+ unsigned int RXFIFOLEVEL:3; /**< \brief [21:19] RXFIFO Filling Level (rh) */
+ unsigned int SLAVESEL:4; /**< \brief [25:22] Currently Active Slave Select Flag (rh) */
+ unsigned int RPV:1; /**< \brief [26:26] Received Parity Value (rh) */
+ unsigned int TPV:1; /**< \brief [27:27] Transmitted Parity Value (rh) */
+ unsigned int PHASE:4; /**< \brief [31:28] Flags the ongoing phase (rh) */
+} Ifx_QSPI_STATUS_Bits;
+
+/** \brief Extra Large Data Configuration Register */
+typedef struct _Ifx_QSPI_XXLCON_Bits
+{
+ unsigned int XDL:16; /**< \brief [15:0] Extended Data Length (rw) */
+ unsigned int BYTECOUNT:16; /**< \brief [31:16] Extended Data Length (r) */
+} Ifx_QSPI_XXLCON_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Qspi_union
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_QSPI_ACCEN0_Bits B; /**< \brief Bitfield access */
+} Ifx_QSPI_ACCEN0;
+
+/** \brief Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_QSPI_ACCEN1_Bits B; /**< \brief Bitfield access */
+} Ifx_QSPI_ACCEN1;
+
+/** \brief Basic Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_QSPI_BACON_Bits B; /**< \brief Bitfield access */
+} Ifx_QSPI_BACON;
+
+/** \brief BACON_ENTRY Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_QSPI_BACONENTRY_Bits B; /**< \brief Bitfield access */
+} Ifx_QSPI_BACONENTRY;
+
+/** \brief Capture Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_QSPI_CAPCON_Bits B; /**< \brief Bitfield access */
+} Ifx_QSPI_CAPCON;
+
+/** \brief Clock Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_QSPI_CLC_Bits B; /**< \brief Bitfield access */
+} Ifx_QSPI_CLC;
+
+/** \brief DATA_ENTRY Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_QSPI_DATAENTRY_Bits B; /**< \brief Bitfield access */
+} Ifx_QSPI_DATAENTRY;
+
+/** \brief Configuration Extension */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_QSPI_ECON_Bits B; /**< \brief Bitfield access */
+} Ifx_QSPI_ECON;
+
+/** \brief Flags Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_QSPI_FLAGSCLEAR_Bits B; /**< \brief Bitfield access */
+} Ifx_QSPI_FLAGSCLEAR;
+
+/** \brief Global Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_QSPI_GLOBALCON_Bits B; /**< \brief Bitfield access */
+} Ifx_QSPI_GLOBALCON;
+
+/** \brief Global Configuration Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_QSPI_GLOBALCON1_Bits B; /**< \brief Bitfield access */
+} Ifx_QSPI_GLOBALCON1;
+
+/** \brief Module Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_QSPI_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_QSPI_ID;
+
+/** \brief Kernel Reset Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_QSPI_KRST0_Bits B; /**< \brief Bitfield access */
+} Ifx_QSPI_KRST0;
+
+/** \brief Kernel Reset Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_QSPI_KRST1_Bits B; /**< \brief Bitfield access */
+} Ifx_QSPI_KRST1;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_QSPI_KRSTCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_QSPI_KRSTCLR;
+
+/** \brief MIX_ENTRY Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_QSPI_MIXENTRY_Bits B; /**< \brief Bitfield access */
+} Ifx_QSPI_MIXENTRY;
+
+/** \brief OCDS Control and Status */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_QSPI_OCS_Bits B; /**< \brief Bitfield access */
+} Ifx_QSPI_OCS;
+
+/** \brief Port Input Select Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_QSPI_PISEL_Bits B; /**< \brief Bitfield access */
+} Ifx_QSPI_PISEL;
+
+/** \brief RX_EXIT Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_QSPI_RXEXIT_Bits B; /**< \brief Bitfield access */
+} Ifx_QSPI_RXEXIT;
+
+/** \brief RX_EXIT Debug Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_QSPI_RXEXITD_Bits B; /**< \brief Bitfield access */
+} Ifx_QSPI_RXEXITD;
+
+/** \brief Slave Select Output Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_QSPI_SSOC_Bits B; /**< \brief Bitfield access */
+} Ifx_QSPI_SSOC;
+
+/** \brief Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_QSPI_STATUS_Bits B; /**< \brief Bitfield access */
+} Ifx_QSPI_STATUS;
+
+/** \brief Status Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_QSPI_STATUS1_Bits B; /**< \brief Bitfield access */
+} Ifx_QSPI_STATUS1;
+
+/** \brief Extra Large Data Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_QSPI_XXLCON_Bits B; /**< \brief Bitfield access */
+} Ifx_QSPI_XXLCON;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Qspi_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief QSPI object */
+typedef volatile struct _Ifx_QSPI
+{
+ Ifx_QSPI_CLC CLC; /**< \brief 0, Clock Control Register */
+ Ifx_QSPI_PISEL PISEL; /**< \brief 4, Port Input Select Register */
+ Ifx_QSPI_ID ID; /**< \brief 8, Module Identification Register */
+ unsigned char reserved_C[4]; /**< \brief C, \internal Reserved */
+ Ifx_QSPI_GLOBALCON GLOBALCON; /**< \brief 10, Global Configuration Register */
+ Ifx_QSPI_GLOBALCON1 GLOBALCON1; /**< \brief 14, Global Configuration Register 1 */
+ Ifx_QSPI_BACON BACON; /**< \brief 18, Basic Configuration Register */
+ unsigned char reserved_1C[4]; /**< \brief 1C, \internal Reserved */
+ Ifx_QSPI_ECON ECON[8]; /**< \brief 20, Configuration Extension */
+ Ifx_QSPI_STATUS STATUS; /**< \brief 40, Status Register */
+ Ifx_QSPI_STATUS1 STATUS1; /**< \brief 44, Status Register 1 */
+ Ifx_QSPI_SSOC SSOC; /**< \brief 48, Slave Select Output Control Register */
+ unsigned char reserved_4C[8]; /**< \brief 4C, \internal Reserved */
+ Ifx_QSPI_FLAGSCLEAR FLAGSCLEAR; /**< \brief 54, Flags Clear Register */
+ Ifx_QSPI_XXLCON XXLCON; /**< \brief 58, Extra Large Data Configuration Register */
+ Ifx_QSPI_MIXENTRY MIXENTRY; /**< \brief 5C, MIX_ENTRY Register */
+ Ifx_QSPI_BACONENTRY BACONENTRY; /**< \brief 60, BACON_ENTRY Register */
+ Ifx_QSPI_DATAENTRY DATAENTRY[8]; /**< \brief 64, DATA_ENTRY Register */
+ unsigned char reserved_84[12]; /**< \brief 84, \internal Reserved */
+ Ifx_QSPI_RXEXIT RXEXIT; /**< \brief 90, RX_EXIT Register */
+ Ifx_QSPI_RXEXITD RXEXITD; /**< \brief 94, RX_EXIT Debug Register */
+ unsigned char reserved_98[8]; /**< \brief 98, \internal Reserved */
+ Ifx_QSPI_CAPCON CAPCON; /**< \brief A0, Capture Control Register */
+ unsigned char reserved_A4[68]; /**< \brief A4, \internal Reserved */
+ Ifx_QSPI_OCS OCS; /**< \brief E8, OCDS Control and Status */
+ Ifx_QSPI_KRSTCLR KRSTCLR; /**< \brief EC, Kernel Reset Status Clear Register */
+ Ifx_QSPI_KRST1 KRST1; /**< \brief F0, Kernel Reset Register 1 */
+ Ifx_QSPI_KRST0 KRST0; /**< \brief F4, Kernel Reset Register 0 */
+ Ifx_QSPI_ACCEN1 ACCEN1; /**< \brief F8, Access Enable Register 1 */
+ Ifx_QSPI_ACCEN0 ACCEN0; /**< \brief FC, Access Enable Register 0 */
+} Ifx_QSPI;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXQSPI_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSbcu_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSbcu_bf.h
new file mode 100644
index 0000000..c14a1e1
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSbcu_bf.h
@@ -0,0 +1,1143 @@
+/**
+ * \file IfxSbcu_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Sbcu_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Sbcu
+ *
+ */
+#ifndef IFXSBCU_BF_H
+#define IFXSBCU_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Sbcu_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN0 */
+#define IFX_SBCU_ACCEN0_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN0 */
+#define IFX_SBCU_ACCEN0_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN0 */
+#define IFX_SBCU_ACCEN0_EN0_OFF (0u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN10 */
+#define IFX_SBCU_ACCEN0_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN10 */
+#define IFX_SBCU_ACCEN0_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN10 */
+#define IFX_SBCU_ACCEN0_EN10_OFF (10u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN11 */
+#define IFX_SBCU_ACCEN0_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN11 */
+#define IFX_SBCU_ACCEN0_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN11 */
+#define IFX_SBCU_ACCEN0_EN11_OFF (11u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN12 */
+#define IFX_SBCU_ACCEN0_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN12 */
+#define IFX_SBCU_ACCEN0_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN12 */
+#define IFX_SBCU_ACCEN0_EN12_OFF (12u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN13 */
+#define IFX_SBCU_ACCEN0_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN13 */
+#define IFX_SBCU_ACCEN0_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN13 */
+#define IFX_SBCU_ACCEN0_EN13_OFF (13u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN14 */
+#define IFX_SBCU_ACCEN0_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN14 */
+#define IFX_SBCU_ACCEN0_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN14 */
+#define IFX_SBCU_ACCEN0_EN14_OFF (14u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN15 */
+#define IFX_SBCU_ACCEN0_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN15 */
+#define IFX_SBCU_ACCEN0_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN15 */
+#define IFX_SBCU_ACCEN0_EN15_OFF (15u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN16 */
+#define IFX_SBCU_ACCEN0_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN16 */
+#define IFX_SBCU_ACCEN0_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN16 */
+#define IFX_SBCU_ACCEN0_EN16_OFF (16u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN17 */
+#define IFX_SBCU_ACCEN0_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN17 */
+#define IFX_SBCU_ACCEN0_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN17 */
+#define IFX_SBCU_ACCEN0_EN17_OFF (17u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN18 */
+#define IFX_SBCU_ACCEN0_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN18 */
+#define IFX_SBCU_ACCEN0_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN18 */
+#define IFX_SBCU_ACCEN0_EN18_OFF (18u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN19 */
+#define IFX_SBCU_ACCEN0_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN19 */
+#define IFX_SBCU_ACCEN0_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN19 */
+#define IFX_SBCU_ACCEN0_EN19_OFF (19u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN1 */
+#define IFX_SBCU_ACCEN0_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN1 */
+#define IFX_SBCU_ACCEN0_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN1 */
+#define IFX_SBCU_ACCEN0_EN1_OFF (1u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN20 */
+#define IFX_SBCU_ACCEN0_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN20 */
+#define IFX_SBCU_ACCEN0_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN20 */
+#define IFX_SBCU_ACCEN0_EN20_OFF (20u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN21 */
+#define IFX_SBCU_ACCEN0_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN21 */
+#define IFX_SBCU_ACCEN0_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN21 */
+#define IFX_SBCU_ACCEN0_EN21_OFF (21u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN22 */
+#define IFX_SBCU_ACCEN0_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN22 */
+#define IFX_SBCU_ACCEN0_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN22 */
+#define IFX_SBCU_ACCEN0_EN22_OFF (22u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN23 */
+#define IFX_SBCU_ACCEN0_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN23 */
+#define IFX_SBCU_ACCEN0_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN23 */
+#define IFX_SBCU_ACCEN0_EN23_OFF (23u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN24 */
+#define IFX_SBCU_ACCEN0_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN24 */
+#define IFX_SBCU_ACCEN0_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN24 */
+#define IFX_SBCU_ACCEN0_EN24_OFF (24u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN25 */
+#define IFX_SBCU_ACCEN0_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN25 */
+#define IFX_SBCU_ACCEN0_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN25 */
+#define IFX_SBCU_ACCEN0_EN25_OFF (25u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN26 */
+#define IFX_SBCU_ACCEN0_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN26 */
+#define IFX_SBCU_ACCEN0_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN26 */
+#define IFX_SBCU_ACCEN0_EN26_OFF (26u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN27 */
+#define IFX_SBCU_ACCEN0_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN27 */
+#define IFX_SBCU_ACCEN0_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN27 */
+#define IFX_SBCU_ACCEN0_EN27_OFF (27u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN28 */
+#define IFX_SBCU_ACCEN0_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN28 */
+#define IFX_SBCU_ACCEN0_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN28 */
+#define IFX_SBCU_ACCEN0_EN28_OFF (28u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN29 */
+#define IFX_SBCU_ACCEN0_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN29 */
+#define IFX_SBCU_ACCEN0_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN29 */
+#define IFX_SBCU_ACCEN0_EN29_OFF (29u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN2 */
+#define IFX_SBCU_ACCEN0_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN2 */
+#define IFX_SBCU_ACCEN0_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN2 */
+#define IFX_SBCU_ACCEN0_EN2_OFF (2u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN30 */
+#define IFX_SBCU_ACCEN0_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN30 */
+#define IFX_SBCU_ACCEN0_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN30 */
+#define IFX_SBCU_ACCEN0_EN30_OFF (30u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN31 */
+#define IFX_SBCU_ACCEN0_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN31 */
+#define IFX_SBCU_ACCEN0_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN31 */
+#define IFX_SBCU_ACCEN0_EN31_OFF (31u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN3 */
+#define IFX_SBCU_ACCEN0_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN3 */
+#define IFX_SBCU_ACCEN0_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN3 */
+#define IFX_SBCU_ACCEN0_EN3_OFF (3u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN4 */
+#define IFX_SBCU_ACCEN0_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN4 */
+#define IFX_SBCU_ACCEN0_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN4 */
+#define IFX_SBCU_ACCEN0_EN4_OFF (4u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN5 */
+#define IFX_SBCU_ACCEN0_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN5 */
+#define IFX_SBCU_ACCEN0_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN5 */
+#define IFX_SBCU_ACCEN0_EN5_OFF (5u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN6 */
+#define IFX_SBCU_ACCEN0_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN6 */
+#define IFX_SBCU_ACCEN0_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN6 */
+#define IFX_SBCU_ACCEN0_EN6_OFF (6u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN7 */
+#define IFX_SBCU_ACCEN0_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN7 */
+#define IFX_SBCU_ACCEN0_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN7 */
+#define IFX_SBCU_ACCEN0_EN7_OFF (7u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN8 */
+#define IFX_SBCU_ACCEN0_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN8 */
+#define IFX_SBCU_ACCEN0_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN8 */
+#define IFX_SBCU_ACCEN0_EN8_OFF (8u)
+
+/** \brief Length for Ifx_SBCU_ACCEN0_Bits.EN9 */
+#define IFX_SBCU_ACCEN0_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ACCEN0_Bits.EN9 */
+#define IFX_SBCU_ACCEN0_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ACCEN0_Bits.EN9 */
+#define IFX_SBCU_ACCEN0_EN9_OFF (9u)
+
+/** \brief Length for Ifx_SBCU_CON_Bits.DBG */
+#define IFX_SBCU_CON_DBG_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_CON_Bits.DBG */
+#define IFX_SBCU_CON_DBG_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_CON_Bits.DBG */
+#define IFX_SBCU_CON_DBG_OFF (16u)
+
+/** \brief Length for Ifx_SBCU_CON_Bits.SPC */
+#define IFX_SBCU_CON_SPC_LEN (8u)
+
+/** \brief Mask for Ifx_SBCU_CON_Bits.SPC */
+#define IFX_SBCU_CON_SPC_MSK (0xffu)
+
+/** \brief Offset for Ifx_SBCU_CON_Bits.SPC */
+#define IFX_SBCU_CON_SPC_OFF (24u)
+
+/** \brief Length for Ifx_SBCU_CON_Bits.TOUT */
+#define IFX_SBCU_CON_TOUT_LEN (16u)
+
+/** \brief Mask for Ifx_SBCU_CON_Bits.TOUT */
+#define IFX_SBCU_CON_TOUT_MSK (0xffffu)
+
+/** \brief Offset for Ifx_SBCU_CON_Bits.TOUT */
+#define IFX_SBCU_CON_TOUT_OFF (0u)
+
+/** \brief Length for Ifx_SBCU_DBADR1_Bits.ADR1 */
+#define IFX_SBCU_DBADR1_ADR1_LEN (32u)
+
+/** \brief Mask for Ifx_SBCU_DBADR1_Bits.ADR1 */
+#define IFX_SBCU_DBADR1_ADR1_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_SBCU_DBADR1_Bits.ADR1 */
+#define IFX_SBCU_DBADR1_ADR1_OFF (0u)
+
+/** \brief Length for Ifx_SBCU_DBADR2_Bits.ADR2 */
+#define IFX_SBCU_DBADR2_ADR2_LEN (32u)
+
+/** \brief Mask for Ifx_SBCU_DBADR2_Bits.ADR2 */
+#define IFX_SBCU_DBADR2_ADR2_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_SBCU_DBADR2_Bits.ADR2 */
+#define IFX_SBCU_DBADR2_ADR2_OFF (0u)
+
+/** \brief Length for Ifx_SBCU_DBADRT_Bits.FPIADR */
+#define IFX_SBCU_DBADRT_FPIADR_LEN (32u)
+
+/** \brief Mask for Ifx_SBCU_DBADRT_Bits.FPIADR */
+#define IFX_SBCU_DBADRT_FPIADR_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_SBCU_DBADRT_Bits.FPIADR */
+#define IFX_SBCU_DBADRT_FPIADR_OFF (0u)
+
+/** \brief Length for Ifx_SBCU_DBBOS_Bits.OPC */
+#define IFX_SBCU_DBBOS_OPC_LEN (4u)
+
+/** \brief Mask for Ifx_SBCU_DBBOS_Bits.OPC */
+#define IFX_SBCU_DBBOS_OPC_MSK (0xfu)
+
+/** \brief Offset for Ifx_SBCU_DBBOS_Bits.OPC */
+#define IFX_SBCU_DBBOS_OPC_OFF (0u)
+
+/** \brief Length for Ifx_SBCU_DBBOS_Bits.RD */
+#define IFX_SBCU_DBBOS_RD_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBBOS_Bits.RD */
+#define IFX_SBCU_DBBOS_RD_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBBOS_Bits.RD */
+#define IFX_SBCU_DBBOS_RD_OFF (12u)
+
+/** \brief Length for Ifx_SBCU_DBBOS_Bits.SVM */
+#define IFX_SBCU_DBBOS_SVM_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBBOS_Bits.SVM */
+#define IFX_SBCU_DBBOS_SVM_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBBOS_Bits.SVM */
+#define IFX_SBCU_DBBOS_SVM_OFF (4u)
+
+/** \brief Length for Ifx_SBCU_DBBOS_Bits.WR */
+#define IFX_SBCU_DBBOS_WR_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBBOS_Bits.WR */
+#define IFX_SBCU_DBBOS_WR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBBOS_Bits.WR */
+#define IFX_SBCU_DBBOS_WR_OFF (8u)
+
+/** \brief Length for Ifx_SBCU_DBBOST_Bits.ENDINIT */
+#define IFX_SBCU_DBBOST_ENDINIT_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBBOST_Bits.ENDINIT */
+#define IFX_SBCU_DBBOST_ENDINIT_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBBOST_Bits.ENDINIT */
+#define IFX_SBCU_DBBOST_ENDINIT_OFF (15u)
+
+/** \brief Length for Ifx_SBCU_DBBOST_Bits.FPIABORT */
+#define IFX_SBCU_DBBOST_FPIABORT_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBBOST_Bits.FPIABORT */
+#define IFX_SBCU_DBBOST_FPIABORT_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBBOST_Bits.FPIABORT */
+#define IFX_SBCU_DBBOST_FPIABORT_OFF (13u)
+
+/** \brief Length for Ifx_SBCU_DBBOST_Bits.FPIACK */
+#define IFX_SBCU_DBBOST_FPIACK_LEN (2u)
+
+/** \brief Mask for Ifx_SBCU_DBBOST_Bits.FPIACK */
+#define IFX_SBCU_DBBOST_FPIACK_MSK (0x3u)
+
+/** \brief Offset for Ifx_SBCU_DBBOST_Bits.FPIACK */
+#define IFX_SBCU_DBBOST_FPIACK_OFF (5u)
+
+/** \brief Length for Ifx_SBCU_DBBOST_Bits.FPIOPC */
+#define IFX_SBCU_DBBOST_FPIOPC_LEN (4u)
+
+/** \brief Mask for Ifx_SBCU_DBBOST_Bits.FPIOPC */
+#define IFX_SBCU_DBBOST_FPIOPC_MSK (0xfu)
+
+/** \brief Offset for Ifx_SBCU_DBBOST_Bits.FPIOPC */
+#define IFX_SBCU_DBBOST_FPIOPC_OFF (0u)
+
+/** \brief Length for Ifx_SBCU_DBBOST_Bits.FPIOPS */
+#define IFX_SBCU_DBBOST_FPIOPS_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBBOST_Bits.FPIOPS */
+#define IFX_SBCU_DBBOST_FPIOPS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBBOST_Bits.FPIOPS */
+#define IFX_SBCU_DBBOST_FPIOPS_OFF (11u)
+
+/** \brief Length for Ifx_SBCU_DBBOST_Bits.FPIRD */
+#define IFX_SBCU_DBBOST_FPIRD_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBBOST_Bits.FPIRD */
+#define IFX_SBCU_DBBOST_FPIRD_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBBOST_Bits.FPIRD */
+#define IFX_SBCU_DBBOST_FPIRD_OFF (12u)
+
+/** \brief Length for Ifx_SBCU_DBBOST_Bits.FPIRDY */
+#define IFX_SBCU_DBBOST_FPIRDY_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBBOST_Bits.FPIRDY */
+#define IFX_SBCU_DBBOST_FPIRDY_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBBOST_Bits.FPIRDY */
+#define IFX_SBCU_DBBOST_FPIRDY_OFF (7u)
+
+/** \brief Length for Ifx_SBCU_DBBOST_Bits.FPIRST */
+#define IFX_SBCU_DBBOST_FPIRST_LEN (2u)
+
+/** \brief Mask for Ifx_SBCU_DBBOST_Bits.FPIRST */
+#define IFX_SBCU_DBBOST_FPIRST_MSK (0x3u)
+
+/** \brief Offset for Ifx_SBCU_DBBOST_Bits.FPIRST */
+#define IFX_SBCU_DBBOST_FPIRST_OFF (9u)
+
+/** \brief Length for Ifx_SBCU_DBBOST_Bits.FPISVM */
+#define IFX_SBCU_DBBOST_FPISVM_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBBOST_Bits.FPISVM */
+#define IFX_SBCU_DBBOST_FPISVM_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBBOST_Bits.FPISVM */
+#define IFX_SBCU_DBBOST_FPISVM_OFF (4u)
+
+/** \brief Length for Ifx_SBCU_DBBOST_Bits.FPITAG */
+#define IFX_SBCU_DBBOST_FPITAG_LEN (6u)
+
+/** \brief Mask for Ifx_SBCU_DBBOST_Bits.FPITAG */
+#define IFX_SBCU_DBBOST_FPITAG_MSK (0x3fu)
+
+/** \brief Offset for Ifx_SBCU_DBBOST_Bits.FPITAG */
+#define IFX_SBCU_DBBOST_FPITAG_OFF (16u)
+
+/** \brief Length for Ifx_SBCU_DBBOST_Bits.FPITOUT */
+#define IFX_SBCU_DBBOST_FPITOUT_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBBOST_Bits.FPITOUT */
+#define IFX_SBCU_DBBOST_FPITOUT_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBBOST_Bits.FPITOUT */
+#define IFX_SBCU_DBBOST_FPITOUT_OFF (14u)
+
+/** \brief Length for Ifx_SBCU_DBBOST_Bits.FPIWR */
+#define IFX_SBCU_DBBOST_FPIWR_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBBOST_Bits.FPIWR */
+#define IFX_SBCU_DBBOST_FPIWR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBBOST_Bits.FPIWR */
+#define IFX_SBCU_DBBOST_FPIWR_OFF (8u)
+
+/** \brief Length for Ifx_SBCU_DBCNTL_Bits.CONCOM0 */
+#define IFX_SBCU_DBCNTL_CONCOM0_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBCNTL_Bits.CONCOM0 */
+#define IFX_SBCU_DBCNTL_CONCOM0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBCNTL_Bits.CONCOM0 */
+#define IFX_SBCU_DBCNTL_CONCOM0_OFF (12u)
+
+/** \brief Length for Ifx_SBCU_DBCNTL_Bits.CONCOM1 */
+#define IFX_SBCU_DBCNTL_CONCOM1_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBCNTL_Bits.CONCOM1 */
+#define IFX_SBCU_DBCNTL_CONCOM1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBCNTL_Bits.CONCOM1 */
+#define IFX_SBCU_DBCNTL_CONCOM1_OFF (13u)
+
+/** \brief Length for Ifx_SBCU_DBCNTL_Bits.CONCOM2 */
+#define IFX_SBCU_DBCNTL_CONCOM2_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBCNTL_Bits.CONCOM2 */
+#define IFX_SBCU_DBCNTL_CONCOM2_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBCNTL_Bits.CONCOM2 */
+#define IFX_SBCU_DBCNTL_CONCOM2_OFF (14u)
+
+/** \brief Length for Ifx_SBCU_DBCNTL_Bits.EO */
+#define IFX_SBCU_DBCNTL_EO_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBCNTL_Bits.EO */
+#define IFX_SBCU_DBCNTL_EO_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBCNTL_Bits.EO */
+#define IFX_SBCU_DBCNTL_EO_OFF (0u)
+
+/** \brief Length for Ifx_SBCU_DBCNTL_Bits.OA */
+#define IFX_SBCU_DBCNTL_OA_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBCNTL_Bits.OA */
+#define IFX_SBCU_DBCNTL_OA_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBCNTL_Bits.OA */
+#define IFX_SBCU_DBCNTL_OA_OFF (1u)
+
+/** \brief Length for Ifx_SBCU_DBCNTL_Bits.ONA1 */
+#define IFX_SBCU_DBCNTL_ONA1_LEN (2u)
+
+/** \brief Mask for Ifx_SBCU_DBCNTL_Bits.ONA1 */
+#define IFX_SBCU_DBCNTL_ONA1_MSK (0x3u)
+
+/** \brief Offset for Ifx_SBCU_DBCNTL_Bits.ONA1 */
+#define IFX_SBCU_DBCNTL_ONA1_OFF (20u)
+
+/** \brief Length for Ifx_SBCU_DBCNTL_Bits.ONA2 */
+#define IFX_SBCU_DBCNTL_ONA2_LEN (2u)
+
+/** \brief Mask for Ifx_SBCU_DBCNTL_Bits.ONA2 */
+#define IFX_SBCU_DBCNTL_ONA2_MSK (0x3u)
+
+/** \brief Offset for Ifx_SBCU_DBCNTL_Bits.ONA2 */
+#define IFX_SBCU_DBCNTL_ONA2_OFF (24u)
+
+/** \brief Length for Ifx_SBCU_DBCNTL_Bits.ONBOS0 */
+#define IFX_SBCU_DBCNTL_ONBOS0_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBCNTL_Bits.ONBOS0 */
+#define IFX_SBCU_DBCNTL_ONBOS0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBCNTL_Bits.ONBOS0 */
+#define IFX_SBCU_DBCNTL_ONBOS0_OFF (28u)
+
+/** \brief Length for Ifx_SBCU_DBCNTL_Bits.ONBOS1 */
+#define IFX_SBCU_DBCNTL_ONBOS1_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBCNTL_Bits.ONBOS1 */
+#define IFX_SBCU_DBCNTL_ONBOS1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBCNTL_Bits.ONBOS1 */
+#define IFX_SBCU_DBCNTL_ONBOS1_OFF (29u)
+
+/** \brief Length for Ifx_SBCU_DBCNTL_Bits.ONBOS2 */
+#define IFX_SBCU_DBCNTL_ONBOS2_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBCNTL_Bits.ONBOS2 */
+#define IFX_SBCU_DBCNTL_ONBOS2_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBCNTL_Bits.ONBOS2 */
+#define IFX_SBCU_DBCNTL_ONBOS2_OFF (30u)
+
+/** \brief Length for Ifx_SBCU_DBCNTL_Bits.ONBOS3 */
+#define IFX_SBCU_DBCNTL_ONBOS3_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBCNTL_Bits.ONBOS3 */
+#define IFX_SBCU_DBCNTL_ONBOS3_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBCNTL_Bits.ONBOS3 */
+#define IFX_SBCU_DBCNTL_ONBOS3_OFF (31u)
+
+/** \brief Length for Ifx_SBCU_DBCNTL_Bits.ONG */
+#define IFX_SBCU_DBCNTL_ONG_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBCNTL_Bits.ONG */
+#define IFX_SBCU_DBCNTL_ONG_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBCNTL_Bits.ONG */
+#define IFX_SBCU_DBCNTL_ONG_OFF (16u)
+
+/** \brief Length for Ifx_SBCU_DBCNTL_Bits.RA */
+#define IFX_SBCU_DBCNTL_RA_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBCNTL_Bits.RA */
+#define IFX_SBCU_DBCNTL_RA_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBCNTL_Bits.RA */
+#define IFX_SBCU_DBCNTL_RA_OFF (4u)
+
+/** \brief Length for Ifx_SBCU_DBDAT_Bits.FPIDATA */
+#define IFX_SBCU_DBDAT_FPIDATA_LEN (32u)
+
+/** \brief Mask for Ifx_SBCU_DBDAT_Bits.FPIDATA */
+#define IFX_SBCU_DBDAT_FPIDATA_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_SBCU_DBDAT_Bits.FPIDATA */
+#define IFX_SBCU_DBDAT_FPIDATA_OFF (0u)
+
+/** \brief Length for Ifx_SBCU_DBGNTT_Bits.CPU0 */
+#define IFX_SBCU_DBGNTT_CPU0_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBGNTT_Bits.CPU0 */
+#define IFX_SBCU_DBGNTT_CPU0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBGNTT_Bits.CPU0 */
+#define IFX_SBCU_DBGNTT_CPU0_OFF (7u)
+
+/** \brief Length for Ifx_SBCU_DBGNTT_Bits.CPU1 */
+#define IFX_SBCU_DBGNTT_CPU1_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBGNTT_Bits.CPU1 */
+#define IFX_SBCU_DBGNTT_CPU1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBGNTT_Bits.CPU1 */
+#define IFX_SBCU_DBGNTT_CPU1_OFF (8u)
+
+/** \brief Length for Ifx_SBCU_DBGNTT_Bits.DMACHNR */
+#define IFX_SBCU_DBGNTT_DMACHNR_LEN (8u)
+
+/** \brief Mask for Ifx_SBCU_DBGNTT_Bits.DMACHNR */
+#define IFX_SBCU_DBGNTT_DMACHNR_MSK (0xffu)
+
+/** \brief Offset for Ifx_SBCU_DBGNTT_Bits.DMACHNR */
+#define IFX_SBCU_DBGNTT_DMACHNR_OFF (16u)
+
+/** \brief Length for Ifx_SBCU_DBGNTT_Bits.DMAH */
+#define IFX_SBCU_DBGNTT_DMAH_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBGNTT_Bits.DMAH */
+#define IFX_SBCU_DBGNTT_DMAH_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBGNTT_Bits.DMAH */
+#define IFX_SBCU_DBGNTT_DMAH_OFF (0u)
+
+/** \brief Length for Ifx_SBCU_DBGNTT_Bits.DMAL */
+#define IFX_SBCU_DBGNTT_DMAL_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBGNTT_Bits.DMAL */
+#define IFX_SBCU_DBGNTT_DMAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBGNTT_Bits.DMAL */
+#define IFX_SBCU_DBGNTT_DMAL_OFF (15u)
+
+/** \brief Length for Ifx_SBCU_DBGNTT_Bits.DMAM */
+#define IFX_SBCU_DBGNTT_DMAM_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBGNTT_Bits.DMAM */
+#define IFX_SBCU_DBGNTT_DMAM_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBGNTT_Bits.DMAM */
+#define IFX_SBCU_DBGNTT_DMAM_OFF (5u)
+
+/** \brief Length for Ifx_SBCU_DBGNTT_Bits.ETH */
+#define IFX_SBCU_DBGNTT_ETH_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBGNTT_Bits.ETH */
+#define IFX_SBCU_DBGNTT_ETH_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBGNTT_Bits.ETH */
+#define IFX_SBCU_DBGNTT_ETH_OFF (2u)
+
+/** \brief Length for Ifx_SBCU_DBGNTT_Bits.HSSL */
+#define IFX_SBCU_DBGNTT_HSSL_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBGNTT_Bits.HSSL */
+#define IFX_SBCU_DBGNTT_HSSL_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBGNTT_Bits.HSSL */
+#define IFX_SBCU_DBGNTT_HSSL_OFF (3u)
+
+/** \brief Length for Ifx_SBCU_DBGNTT_Bits.ONE0 */
+#define IFX_SBCU_DBGNTT_ONE0_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBGNTT_Bits.ONE0 */
+#define IFX_SBCU_DBGNTT_ONE0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBGNTT_Bits.ONE0 */
+#define IFX_SBCU_DBGNTT_ONE0_OFF (1u)
+
+/** \brief Length for Ifx_SBCU_DBGNTT_Bits.ONE1 */
+#define IFX_SBCU_DBGNTT_ONE1_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBGNTT_Bits.ONE1 */
+#define IFX_SBCU_DBGNTT_ONE1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBGNTT_Bits.ONE1 */
+#define IFX_SBCU_DBGNTT_ONE1_OFF (4u)
+
+/** \brief Length for Ifx_SBCU_DBGNTT_Bits.ONE2 */
+#define IFX_SBCU_DBGNTT_ONE2_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBGNTT_Bits.ONE2 */
+#define IFX_SBCU_DBGNTT_ONE2_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBGNTT_Bits.ONE2 */
+#define IFX_SBCU_DBGNTT_ONE2_OFF (6u)
+
+/** \brief Length for Ifx_SBCU_DBGNTT_Bits.ONE3 */
+#define IFX_SBCU_DBGNTT_ONE3_LEN (6u)
+
+/** \brief Mask for Ifx_SBCU_DBGNTT_Bits.ONE3 */
+#define IFX_SBCU_DBGNTT_ONE3_MSK (0x3fu)
+
+/** \brief Offset for Ifx_SBCU_DBGNTT_Bits.ONE3 */
+#define IFX_SBCU_DBGNTT_ONE3_OFF (9u)
+
+/** \brief Length for Ifx_SBCU_DBGNTT_Bits.ONE4 */
+#define IFX_SBCU_DBGNTT_ONE4_LEN (8u)
+
+/** \brief Mask for Ifx_SBCU_DBGNTT_Bits.ONE4 */
+#define IFX_SBCU_DBGNTT_ONE4_MSK (0xffu)
+
+/** \brief Offset for Ifx_SBCU_DBGNTT_Bits.ONE4 */
+#define IFX_SBCU_DBGNTT_ONE4_OFF (24u)
+
+/** \brief Length for Ifx_SBCU_DBGRNT_Bits.CPU0 */
+#define IFX_SBCU_DBGRNT_CPU0_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBGRNT_Bits.CPU0 */
+#define IFX_SBCU_DBGRNT_CPU0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBGRNT_Bits.CPU0 */
+#define IFX_SBCU_DBGRNT_CPU0_OFF (7u)
+
+/** \brief Length for Ifx_SBCU_DBGRNT_Bits.CPU1 */
+#define IFX_SBCU_DBGRNT_CPU1_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBGRNT_Bits.CPU1 */
+#define IFX_SBCU_DBGRNT_CPU1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBGRNT_Bits.CPU1 */
+#define IFX_SBCU_DBGRNT_CPU1_OFF (8u)
+
+/** \brief Length for Ifx_SBCU_DBGRNT_Bits.DMAH */
+#define IFX_SBCU_DBGRNT_DMAH_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBGRNT_Bits.DMAH */
+#define IFX_SBCU_DBGRNT_DMAH_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBGRNT_Bits.DMAH */
+#define IFX_SBCU_DBGRNT_DMAH_OFF (0u)
+
+/** \brief Length for Ifx_SBCU_DBGRNT_Bits.DMAL */
+#define IFX_SBCU_DBGRNT_DMAL_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBGRNT_Bits.DMAL */
+#define IFX_SBCU_DBGRNT_DMAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBGRNT_Bits.DMAL */
+#define IFX_SBCU_DBGRNT_DMAL_OFF (15u)
+
+/** \brief Length for Ifx_SBCU_DBGRNT_Bits.DMAM */
+#define IFX_SBCU_DBGRNT_DMAM_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBGRNT_Bits.DMAM */
+#define IFX_SBCU_DBGRNT_DMAM_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBGRNT_Bits.DMAM */
+#define IFX_SBCU_DBGRNT_DMAM_OFF (5u)
+
+/** \brief Length for Ifx_SBCU_DBGRNT_Bits.ETH */
+#define IFX_SBCU_DBGRNT_ETH_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBGRNT_Bits.ETH */
+#define IFX_SBCU_DBGRNT_ETH_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBGRNT_Bits.ETH */
+#define IFX_SBCU_DBGRNT_ETH_OFF (2u)
+
+/** \brief Length for Ifx_SBCU_DBGRNT_Bits.HSSL */
+#define IFX_SBCU_DBGRNT_HSSL_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBGRNT_Bits.HSSL */
+#define IFX_SBCU_DBGRNT_HSSL_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBGRNT_Bits.HSSL */
+#define IFX_SBCU_DBGRNT_HSSL_OFF (3u)
+
+/** \brief Length for Ifx_SBCU_DBGRNT_Bits.ONE0 */
+#define IFX_SBCU_DBGRNT_ONE0_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBGRNT_Bits.ONE0 */
+#define IFX_SBCU_DBGRNT_ONE0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBGRNT_Bits.ONE0 */
+#define IFX_SBCU_DBGRNT_ONE0_OFF (1u)
+
+/** \brief Length for Ifx_SBCU_DBGRNT_Bits.ONE1 */
+#define IFX_SBCU_DBGRNT_ONE1_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBGRNT_Bits.ONE1 */
+#define IFX_SBCU_DBGRNT_ONE1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBGRNT_Bits.ONE1 */
+#define IFX_SBCU_DBGRNT_ONE1_OFF (4u)
+
+/** \brief Length for Ifx_SBCU_DBGRNT_Bits.ONE2 */
+#define IFX_SBCU_DBGRNT_ONE2_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBGRNT_Bits.ONE2 */
+#define IFX_SBCU_DBGRNT_ONE2_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBGRNT_Bits.ONE2 */
+#define IFX_SBCU_DBGRNT_ONE2_OFF (6u)
+
+/** \brief Length for Ifx_SBCU_DBGRNT_Bits.ONE3 */
+#define IFX_SBCU_DBGRNT_ONE3_LEN (5u)
+
+/** \brief Mask for Ifx_SBCU_DBGRNT_Bits.ONE3 */
+#define IFX_SBCU_DBGRNT_ONE3_MSK (0x1fu)
+
+/** \brief Offset for Ifx_SBCU_DBGRNT_Bits.ONE3 */
+#define IFX_SBCU_DBGRNT_ONE3_OFF (9u)
+
+/** \brief Length for Ifx_SBCU_DBGRNT_Bits.ONE4 */
+#define IFX_SBCU_DBGRNT_ONE4_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_DBGRNT_Bits.ONE4 */
+#define IFX_SBCU_DBGRNT_ONE4_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_DBGRNT_Bits.ONE4 */
+#define IFX_SBCU_DBGRNT_ONE4_OFF (14u)
+
+/** \brief Length for Ifx_SBCU_EADD_Bits.FPIADR */
+#define IFX_SBCU_EADD_FPIADR_LEN (32u)
+
+/** \brief Mask for Ifx_SBCU_EADD_Bits.FPIADR */
+#define IFX_SBCU_EADD_FPIADR_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_SBCU_EADD_Bits.FPIADR */
+#define IFX_SBCU_EADD_FPIADR_OFF (0u)
+
+/** \brief Length for Ifx_SBCU_ECON_Bits.ABT */
+#define IFX_SBCU_ECON_ABT_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ECON_Bits.ABT */
+#define IFX_SBCU_ECON_ABT_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ECON_Bits.ABT */
+#define IFX_SBCU_ECON_ABT_OFF (16u)
+
+/** \brief Length for Ifx_SBCU_ECON_Bits.ACK */
+#define IFX_SBCU_ECON_ACK_LEN (2u)
+
+/** \brief Mask for Ifx_SBCU_ECON_Bits.ACK */
+#define IFX_SBCU_ECON_ACK_MSK (0x3u)
+
+/** \brief Offset for Ifx_SBCU_ECON_Bits.ACK */
+#define IFX_SBCU_ECON_ACK_OFF (17u)
+
+/** \brief Length for Ifx_SBCU_ECON_Bits.ERRCNT */
+#define IFX_SBCU_ECON_ERRCNT_LEN (14u)
+
+/** \brief Mask for Ifx_SBCU_ECON_Bits.ERRCNT */
+#define IFX_SBCU_ECON_ERRCNT_MSK (0x3fffu)
+
+/** \brief Offset for Ifx_SBCU_ECON_Bits.ERRCNT */
+#define IFX_SBCU_ECON_ERRCNT_OFF (0u)
+
+/** \brief Length for Ifx_SBCU_ECON_Bits.OPC */
+#define IFX_SBCU_ECON_OPC_LEN (4u)
+
+/** \brief Mask for Ifx_SBCU_ECON_Bits.OPC */
+#define IFX_SBCU_ECON_OPC_MSK (0xfu)
+
+/** \brief Offset for Ifx_SBCU_ECON_Bits.OPC */
+#define IFX_SBCU_ECON_OPC_OFF (28u)
+
+/** \brief Length for Ifx_SBCU_ECON_Bits.RDN */
+#define IFX_SBCU_ECON_RDN_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ECON_Bits.RDN */
+#define IFX_SBCU_ECON_RDN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ECON_Bits.RDN */
+#define IFX_SBCU_ECON_RDN_OFF (21u)
+
+/** \brief Length for Ifx_SBCU_ECON_Bits.RDY */
+#define IFX_SBCU_ECON_RDY_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ECON_Bits.RDY */
+#define IFX_SBCU_ECON_RDY_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ECON_Bits.RDY */
+#define IFX_SBCU_ECON_RDY_OFF (15u)
+
+/** \brief Length for Ifx_SBCU_ECON_Bits.SVM */
+#define IFX_SBCU_ECON_SVM_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ECON_Bits.SVM */
+#define IFX_SBCU_ECON_SVM_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ECON_Bits.SVM */
+#define IFX_SBCU_ECON_SVM_OFF (19u)
+
+/** \brief Length for Ifx_SBCU_ECON_Bits.TAG */
+#define IFX_SBCU_ECON_TAG_LEN (6u)
+
+/** \brief Mask for Ifx_SBCU_ECON_Bits.TAG */
+#define IFX_SBCU_ECON_TAG_MSK (0x3fu)
+
+/** \brief Offset for Ifx_SBCU_ECON_Bits.TAG */
+#define IFX_SBCU_ECON_TAG_OFF (22u)
+
+/** \brief Length for Ifx_SBCU_ECON_Bits.TOUT */
+#define IFX_SBCU_ECON_TOUT_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ECON_Bits.TOUT */
+#define IFX_SBCU_ECON_TOUT_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ECON_Bits.TOUT */
+#define IFX_SBCU_ECON_TOUT_OFF (14u)
+
+/** \brief Length for Ifx_SBCU_ECON_Bits.WRN */
+#define IFX_SBCU_ECON_WRN_LEN (1u)
+
+/** \brief Mask for Ifx_SBCU_ECON_Bits.WRN */
+#define IFX_SBCU_ECON_WRN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SBCU_ECON_Bits.WRN */
+#define IFX_SBCU_ECON_WRN_OFF (20u)
+
+/** \brief Length for Ifx_SBCU_EDAT_Bits.FPIDAT */
+#define IFX_SBCU_EDAT_FPIDAT_LEN (32u)
+
+/** \brief Mask for Ifx_SBCU_EDAT_Bits.FPIDAT */
+#define IFX_SBCU_EDAT_FPIDAT_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_SBCU_EDAT_Bits.FPIDAT */
+#define IFX_SBCU_EDAT_FPIDAT_OFF (0u)
+
+/** \brief Length for Ifx_SBCU_ID_Bits.MODNUMBER */
+#define IFX_SBCU_ID_MODNUMBER_LEN (8u)
+
+/** \brief Mask for Ifx_SBCU_ID_Bits.MODNUMBER */
+#define IFX_SBCU_ID_MODNUMBER_MSK (0xffu)
+
+/** \brief Offset for Ifx_SBCU_ID_Bits.MODNUMBER */
+#define IFX_SBCU_ID_MODNUMBER_OFF (8u)
+
+/** \brief Length for Ifx_SBCU_ID_Bits.MODREV */
+#define IFX_SBCU_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_SBCU_ID_Bits.MODREV */
+#define IFX_SBCU_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_SBCU_ID_Bits.MODREV */
+#define IFX_SBCU_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_SBCU_PRIOH_Bits.CPU1 */
+#define IFX_SBCU_PRIOH_CPU1_LEN (4u)
+
+/** \brief Mask for Ifx_SBCU_PRIOH_Bits.CPU1 */
+#define IFX_SBCU_PRIOH_CPU1_MSK (0xfu)
+
+/** \brief Offset for Ifx_SBCU_PRIOH_Bits.CPU1 */
+#define IFX_SBCU_PRIOH_CPU1_OFF (0u)
+
+/** \brief Length for Ifx_SBCU_PRIOH_Bits.DMAL */
+#define IFX_SBCU_PRIOH_DMAL_LEN (4u)
+
+/** \brief Mask for Ifx_SBCU_PRIOH_Bits.DMAL */
+#define IFX_SBCU_PRIOH_DMAL_MSK (0xfu)
+
+/** \brief Offset for Ifx_SBCU_PRIOH_Bits.DMAL */
+#define IFX_SBCU_PRIOH_DMAL_OFF (28u)
+
+/** \brief Length for Ifx_SBCU_PRIOH_Bits.RESERVED9 */
+#define IFX_SBCU_PRIOH_RESERVED9_LEN (4u)
+
+/** \brief Mask for Ifx_SBCU_PRIOH_Bits.RESERVED9 */
+#define IFX_SBCU_PRIOH_RESERVED9_MSK (0xfu)
+
+/** \brief Offset for Ifx_SBCU_PRIOH_Bits.RESERVED9 */
+#define IFX_SBCU_PRIOH_RESERVED9_OFF (4u)
+
+/** \brief Length for Ifx_SBCU_PRIOH_Bits.RESERVEDA */
+#define IFX_SBCU_PRIOH_RESERVEDA_LEN (4u)
+
+/** \brief Mask for Ifx_SBCU_PRIOH_Bits.RESERVEDA */
+#define IFX_SBCU_PRIOH_RESERVEDA_MSK (0xfu)
+
+/** \brief Offset for Ifx_SBCU_PRIOH_Bits.RESERVEDA */
+#define IFX_SBCU_PRIOH_RESERVEDA_OFF (8u)
+
+/** \brief Length for Ifx_SBCU_PRIOH_Bits.RESERVEDB */
+#define IFX_SBCU_PRIOH_RESERVEDB_LEN (4u)
+
+/** \brief Mask for Ifx_SBCU_PRIOH_Bits.RESERVEDB */
+#define IFX_SBCU_PRIOH_RESERVEDB_MSK (0xfu)
+
+/** \brief Offset for Ifx_SBCU_PRIOH_Bits.RESERVEDB */
+#define IFX_SBCU_PRIOH_RESERVEDB_OFF (12u)
+
+/** \brief Length for Ifx_SBCU_PRIOH_Bits.RESERVEDC */
+#define IFX_SBCU_PRIOH_RESERVEDC_LEN (4u)
+
+/** \brief Mask for Ifx_SBCU_PRIOH_Bits.RESERVEDC */
+#define IFX_SBCU_PRIOH_RESERVEDC_MSK (0xfu)
+
+/** \brief Offset for Ifx_SBCU_PRIOH_Bits.RESERVEDC */
+#define IFX_SBCU_PRIOH_RESERVEDC_OFF (16u)
+
+/** \brief Length for Ifx_SBCU_PRIOH_Bits.RESERVEDD */
+#define IFX_SBCU_PRIOH_RESERVEDD_LEN (4u)
+
+/** \brief Mask for Ifx_SBCU_PRIOH_Bits.RESERVEDD */
+#define IFX_SBCU_PRIOH_RESERVEDD_MSK (0xfu)
+
+/** \brief Offset for Ifx_SBCU_PRIOH_Bits.RESERVEDD */
+#define IFX_SBCU_PRIOH_RESERVEDD_OFF (20u)
+
+/** \brief Length for Ifx_SBCU_PRIOH_Bits.RESERVEDE */
+#define IFX_SBCU_PRIOH_RESERVEDE_LEN (4u)
+
+/** \brief Mask for Ifx_SBCU_PRIOH_Bits.RESERVEDE */
+#define IFX_SBCU_PRIOH_RESERVEDE_MSK (0xfu)
+
+/** \brief Offset for Ifx_SBCU_PRIOH_Bits.RESERVEDE */
+#define IFX_SBCU_PRIOH_RESERVEDE_OFF (24u)
+
+/** \brief Length for Ifx_SBCU_PRIOL_Bits.CPU0 */
+#define IFX_SBCU_PRIOL_CPU0_LEN (4u)
+
+/** \brief Mask for Ifx_SBCU_PRIOL_Bits.CPU0 */
+#define IFX_SBCU_PRIOL_CPU0_MSK (0xfu)
+
+/** \brief Offset for Ifx_SBCU_PRIOL_Bits.CPU0 */
+#define IFX_SBCU_PRIOL_CPU0_OFF (28u)
+
+/** \brief Length for Ifx_SBCU_PRIOL_Bits.DMAH */
+#define IFX_SBCU_PRIOL_DMAH_LEN (4u)
+
+/** \brief Mask for Ifx_SBCU_PRIOL_Bits.DMAH */
+#define IFX_SBCU_PRIOL_DMAH_MSK (0xfu)
+
+/** \brief Offset for Ifx_SBCU_PRIOL_Bits.DMAH */
+#define IFX_SBCU_PRIOL_DMAH_OFF (0u)
+
+/** \brief Length for Ifx_SBCU_PRIOL_Bits.DMAM */
+#define IFX_SBCU_PRIOL_DMAM_LEN (4u)
+
+/** \brief Mask for Ifx_SBCU_PRIOL_Bits.DMAM */
+#define IFX_SBCU_PRIOL_DMAM_MSK (0xfu)
+
+/** \brief Offset for Ifx_SBCU_PRIOL_Bits.DMAM */
+#define IFX_SBCU_PRIOL_DMAM_OFF (20u)
+
+/** \brief Length for Ifx_SBCU_PRIOL_Bits.ETH */
+#define IFX_SBCU_PRIOL_ETH_LEN (4u)
+
+/** \brief Mask for Ifx_SBCU_PRIOL_Bits.ETH */
+#define IFX_SBCU_PRIOL_ETH_MSK (0xfu)
+
+/** \brief Offset for Ifx_SBCU_PRIOL_Bits.ETH */
+#define IFX_SBCU_PRIOL_ETH_OFF (8u)
+
+/** \brief Length for Ifx_SBCU_PRIOL_Bits.HSSL */
+#define IFX_SBCU_PRIOL_HSSL_LEN (4u)
+
+/** \brief Mask for Ifx_SBCU_PRIOL_Bits.HSSL */
+#define IFX_SBCU_PRIOL_HSSL_MSK (0xfu)
+
+/** \brief Offset for Ifx_SBCU_PRIOL_Bits.HSSL */
+#define IFX_SBCU_PRIOL_HSSL_OFF (12u)
+
+/** \brief Length for Ifx_SBCU_PRIOL_Bits.RESERVED1 */
+#define IFX_SBCU_PRIOL_RESERVED1_LEN (4u)
+
+/** \brief Mask for Ifx_SBCU_PRIOL_Bits.RESERVED1 */
+#define IFX_SBCU_PRIOL_RESERVED1_MSK (0xfu)
+
+/** \brief Offset for Ifx_SBCU_PRIOL_Bits.RESERVED1 */
+#define IFX_SBCU_PRIOL_RESERVED1_OFF (4u)
+
+/** \brief Length for Ifx_SBCU_PRIOL_Bits.RESERVED4 */
+#define IFX_SBCU_PRIOL_RESERVED4_LEN (4u)
+
+/** \brief Mask for Ifx_SBCU_PRIOL_Bits.RESERVED4 */
+#define IFX_SBCU_PRIOL_RESERVED4_MSK (0xfu)
+
+/** \brief Offset for Ifx_SBCU_PRIOL_Bits.RESERVED4 */
+#define IFX_SBCU_PRIOL_RESERVED4_OFF (16u)
+
+/** \brief Length for Ifx_SBCU_PRIOL_Bits.RESERVED6 */
+#define IFX_SBCU_PRIOL_RESERVED6_LEN (4u)
+
+/** \brief Mask for Ifx_SBCU_PRIOL_Bits.RESERVED6 */
+#define IFX_SBCU_PRIOL_RESERVED6_MSK (0xfu)
+
+/** \brief Offset for Ifx_SBCU_PRIOL_Bits.RESERVED6 */
+#define IFX_SBCU_PRIOL_RESERVED6_OFF (24u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXSBCU_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSbcu_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSbcu_reg.h
new file mode 100644
index 0000000..8f58f66
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSbcu_reg.h
@@ -0,0 +1,195 @@
+/**
+ * \file IfxSbcu_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Sbcu_Cfg Sbcu address
+ * \ingroup IfxLld_Sbcu
+ *
+ * \defgroup IfxLld_Sbcu_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Sbcu_Cfg
+ *
+ * \defgroup IfxLld_Sbcu_Cfg_Sbcu0 2-SBCU0
+ * \ingroup IfxLld_Sbcu_Cfg
+ *
+ */
+#ifndef IFXSBCU_REG_H
+#define IFXSBCU_REG_H 1
+/******************************************************************************/
+#include "IfxSbcu_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Sbcu_Cfg_BaseAddress
+ * \{ */
+
+/** \brief SBCU object */
+#define MODULE_SBCU0 /*lint --e(923)*/ (*(Ifx_SBCU*)0xF0030000u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Sbcu_Cfg_Sbcu0
+ * \{ */
+
+/** \brief FC, Access Enable Register 0 */
+#define SBCU0_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_SBCU_ACCEN0*)0xF00300FCu)
+
+/** Alias (User Manual Name) for SBCU0_ACCEN0.
+* To use register names with standard convension, please use SBCU0_ACCEN0.
+*/
+#define SBCU_ACCEN0 (SBCU0_ACCEN0)
+
+/** \brief F8, Access Enable Register 1 */
+#define SBCU0_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_SBCU_ACCEN1*)0xF00300F8u)
+
+/** Alias (User Manual Name) for SBCU0_ACCEN1.
+* To use register names with standard convension, please use SBCU0_ACCEN1.
+*/
+#define SBCU_ACCEN1 (SBCU0_ACCEN1)
+
+/** \brief 10, SBCU Control Register */
+#define SBCU0_CON /*lint --e(923)*/ (*(volatile Ifx_SBCU_CON*)0xF0030010u)
+
+/** Alias (User Manual Name) for SBCU0_CON.
+* To use register names with standard convension, please use SBCU0_CON.
+*/
+#define SBCU_CON (SBCU0_CON)
+
+/** \brief 38, SBCU Debug Address 1 Register */
+#define SBCU0_DBADR1 /*lint --e(923)*/ (*(volatile Ifx_SBCU_DBADR1*)0xF0030038u)
+
+/** Alias (User Manual Name) for SBCU0_DBADR1.
+* To use register names with standard convension, please use SBCU0_DBADR1.
+*/
+#define SBCU_DBADR1 (SBCU0_DBADR1)
+
+/** \brief 3C, SBCU Debug Address 2 Register */
+#define SBCU0_DBADR2 /*lint --e(923)*/ (*(volatile Ifx_SBCU_DBADR2*)0xF003003Cu)
+
+/** Alias (User Manual Name) for SBCU0_DBADR2.
+* To use register names with standard convension, please use SBCU0_DBADR2.
+*/
+#define SBCU_DBADR2 (SBCU0_DBADR2)
+
+/** \brief 48, SBCU Debug Trapped Address Register */
+#define SBCU0_DBADRT /*lint --e(923)*/ (*(volatile Ifx_SBCU_DBADRT*)0xF0030048u)
+
+/** Alias (User Manual Name) for SBCU0_DBADRT.
+* To use register names with standard convension, please use SBCU0_DBADRT.
+*/
+#define SBCU_DBADRT (SBCU0_DBADRT)
+
+/** \brief 40, SBCU Debug Bus Operation Signals Register */
+#define SBCU0_DBBOS /*lint --e(923)*/ (*(volatile Ifx_SBCU_DBBOS*)0xF0030040u)
+
+/** Alias (User Manual Name) for SBCU0_DBBOS.
+* To use register names with standard convension, please use SBCU0_DBBOS.
+*/
+#define SBCU_DBBOS (SBCU0_DBBOS)
+
+/** \brief 4C, SBCU Debug Trapped Bus Operation Signals Register */
+#define SBCU0_DBBOST /*lint --e(923)*/ (*(volatile Ifx_SBCU_DBBOST*)0xF003004Cu)
+
+/** Alias (User Manual Name) for SBCU0_DBBOST.
+* To use register names with standard convension, please use SBCU0_DBBOST.
+*/
+#define SBCU_DBBOST (SBCU0_DBBOST)
+
+/** \brief 30, SBCU Debug Control Register */
+#define SBCU0_DBCNTL /*lint --e(923)*/ (*(volatile Ifx_SBCU_DBCNTL*)0xF0030030u)
+
+/** Alias (User Manual Name) for SBCU0_DBCNTL.
+* To use register names with standard convension, please use SBCU0_DBCNTL.
+*/
+#define SBCU_DBCNTL (SBCU0_DBCNTL)
+
+/** \brief 50, SBCU Debug Data Status Register */
+#define SBCU0_DBDAT /*lint --e(923)*/ (*(volatile Ifx_SBCU_DBDAT*)0xF0030050u)
+
+/** Alias (User Manual Name) for SBCU0_DBDAT.
+* To use register names with standard convension, please use SBCU0_DBDAT.
+*/
+#define SBCU_DBDAT (SBCU0_DBDAT)
+
+/** \brief 44, SBCU Debug Trapped Master Register */
+#define SBCU0_DBGNTT /*lint --e(923)*/ (*(volatile Ifx_SBCU_DBGNTT*)0xF0030044u)
+
+/** Alias (User Manual Name) for SBCU0_DBGNTT.
+* To use register names with standard convension, please use SBCU0_DBGNTT.
+*/
+#define SBCU_DBGNTT (SBCU0_DBGNTT)
+
+/** \brief 34, SBCU Debug Grant Mask Register */
+#define SBCU0_DBGRNT /*lint --e(923)*/ (*(volatile Ifx_SBCU_DBGRNT*)0xF0030034u)
+
+/** Alias (User Manual Name) for SBCU0_DBGRNT.
+* To use register names with standard convension, please use SBCU0_DBGRNT.
+*/
+#define SBCU_DBGRNT (SBCU0_DBGRNT)
+
+/** \brief 24, SBCU Error Address Capture Register */
+#define SBCU0_EADD /*lint --e(923)*/ (*(volatile Ifx_SBCU_EADD*)0xF0030024u)
+
+/** Alias (User Manual Name) for SBCU0_EADD.
+* To use register names with standard convension, please use SBCU0_EADD.
+*/
+#define SBCU_EADD (SBCU0_EADD)
+
+/** \brief 20, SBCU Error Control Capture Register */
+#define SBCU0_ECON /*lint --e(923)*/ (*(volatile Ifx_SBCU_ECON*)0xF0030020u)
+
+/** Alias (User Manual Name) for SBCU0_ECON.
+* To use register names with standard convension, please use SBCU0_ECON.
+*/
+#define SBCU_ECON (SBCU0_ECON)
+
+/** \brief 28, SBCU Error Data Capture Register */
+#define SBCU0_EDAT /*lint --e(923)*/ (*(volatile Ifx_SBCU_EDAT*)0xF0030028u)
+
+/** Alias (User Manual Name) for SBCU0_EDAT.
+* To use register names with standard convension, please use SBCU0_EDAT.
+*/
+#define SBCU_EDAT (SBCU0_EDAT)
+
+/** \brief 8, Module Identification Register */
+#define SBCU0_ID /*lint --e(923)*/ (*(volatile Ifx_SBCU_ID*)0xF0030008u)
+
+/** Alias (User Manual Name) for SBCU0_ID.
+* To use register names with standard convension, please use SBCU0_ID.
+*/
+#define SBCU_ID (SBCU0_ID)
+
+/** \brief 14, Arbiter Priority Register High */
+#define SBCU0_PRIOH /*lint --e(923)*/ (*(volatile Ifx_SBCU_PRIOH*)0xF0030014u)
+
+/** Alias (User Manual Name) for SBCU0_PRIOH.
+* To use register names with standard convension, please use SBCU0_PRIOH.
+*/
+#define SBCU_PRIOH (SBCU0_PRIOH)
+
+/** \brief 18, Arbiter Priority Register Low */
+#define SBCU0_PRIOL /*lint --e(923)*/ (*(volatile Ifx_SBCU_PRIOL*)0xF0030018u)
+
+/** Alias (User Manual Name) for SBCU0_PRIOL.
+* To use register names with standard convension, please use SBCU0_PRIOL.
+*/
+#define SBCU_PRIOL (SBCU0_PRIOL)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXSBCU_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSbcu_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSbcu_regdef.h
new file mode 100644
index 0000000..08f4f66
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSbcu_regdef.h
@@ -0,0 +1,460 @@
+/**
+ * \file IfxSbcu_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Sbcu Sbcu
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Sbcu_Bitfields Bitfields
+ * \ingroup IfxLld_Sbcu
+ *
+ * \defgroup IfxLld_Sbcu_union Union
+ * \ingroup IfxLld_Sbcu
+ *
+ * \defgroup IfxLld_Sbcu_struct Struct
+ * \ingroup IfxLld_Sbcu
+ *
+ */
+#ifndef IFXSBCU_REGDEF_H
+#define IFXSBCU_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Sbcu_Bitfields
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef struct _Ifx_SBCU_ACCEN0_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_SBCU_ACCEN0_Bits;
+
+/** \brief Access Enable Register 1 */
+typedef struct _Ifx_SBCU_ACCEN1_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_SBCU_ACCEN1_Bits;
+
+/** \brief SBCU Control Register */
+typedef struct _Ifx_SBCU_CON_Bits
+{
+ unsigned int TOUT:16; /**< \brief [15:0] SBCU Bus Time-Out Value (rw) */
+ unsigned int DBG:1; /**< \brief [16:16] SBCU Debug Trace Enable (rw) */
+ unsigned int reserved_17:7; /**< \brief \internal Reserved */
+ unsigned int SPC:8; /**< \brief [31:24] Starvation Period Control (rw) */
+} Ifx_SBCU_CON_Bits;
+
+/** \brief SBCU Debug Address 1 Register */
+typedef struct _Ifx_SBCU_DBADR1_Bits
+{
+ unsigned int ADR1:32; /**< \brief [31:0] Debug Trigger Address 1 (rw) */
+} Ifx_SBCU_DBADR1_Bits;
+
+/** \brief SBCU Debug Address 2 Register */
+typedef struct _Ifx_SBCU_DBADR2_Bits
+{
+ unsigned int ADR2:32; /**< \brief [31:0] Debug Trigger Address 2 (rw) */
+} Ifx_SBCU_DBADR2_Bits;
+
+/** \brief SBCU Debug Trapped Address Register */
+typedef struct _Ifx_SBCU_DBADRT_Bits
+{
+ unsigned int FPIADR:32; /**< \brief [31:0] FPI Bus Address Status (rh) */
+} Ifx_SBCU_DBADRT_Bits;
+
+/** \brief SBCU Debug Bus Operation Signals Register */
+typedef struct _Ifx_SBCU_DBBOS_Bits
+{
+ unsigned int OPC:4; /**< \brief [3:0] Opcode for Signal Status Debug Trigger (rw) */
+ unsigned int SVM:1; /**< \brief [4:4] SVM Signal for Status Debug Trigger (rw) */
+ unsigned int reserved_5:3; /**< \brief \internal Reserved */
+ unsigned int WR:1; /**< \brief [8:8] Write Signal for Status Debug Trigger (rw) */
+ unsigned int reserved_9:3; /**< \brief \internal Reserved */
+ unsigned int RD:1; /**< \brief [12:12] Write Signal for Status Debug Trigger (rw) */
+ unsigned int reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_SBCU_DBBOS_Bits;
+
+/** \brief SBCU Debug Trapped Bus Operation Signals Register */
+typedef struct _Ifx_SBCU_DBBOST_Bits
+{
+ unsigned int FPIOPC:4; /**< \brief [3:0] FPI Bus Opcode Status (rh) */
+ unsigned int FPISVM:1; /**< \brief [4:4] FPI Bus Supervisor Mode Status (rh) */
+ unsigned int FPIACK:2; /**< \brief [6:5] FPI Bus Acknowledge Status (rh) */
+ unsigned int FPIRDY:1; /**< \brief [7:7] FPI Bus Ready Status (rh) */
+ unsigned int FPIWR:1; /**< \brief [8:8] FPI Bus Write Indication Status (rh) */
+ unsigned int FPIRST:2; /**< \brief [10:9] FPI Bus Reset Status (rh) */
+ unsigned int FPIOPS:1; /**< \brief [11:11] FPI Bus OCDS Suspend Status (rh) */
+ unsigned int FPIRD:1; /**< \brief [12:12] FPI Bus Read Indication Status (rh) */
+ unsigned int FPIABORT:1; /**< \brief [13:13] FPI Bus Abort Status (rh) */
+ unsigned int FPITOUT:1; /**< \brief [14:14] FPI Bus Time-out Status (rh) */
+ unsigned int ENDINIT:1; /**< \brief [15:15] FPI Bus Endinit Status (rh) */
+ unsigned int FPITAG:6; /**< \brief [21:16] FPI Bus Master TAG Status (rh) */
+ unsigned int reserved_22:10; /**< \brief \internal Reserved */
+} Ifx_SBCU_DBBOST_Bits;
+
+/** \brief SBCU Debug Control Register */
+typedef struct _Ifx_SBCU_DBCNTL_Bits
+{
+ unsigned int EO:1; /**< \brief [0:0] Status of SBCU Debug Support Enable (r) */
+ unsigned int OA:1; /**< \brief [1:1] Status of SBCU Breakpoint Logic (r) */
+ unsigned int reserved_2:2; /**< \brief \internal Reserved */
+ unsigned int RA:1; /**< \brief [4:4] Rearm SBCU Breakpoint Logic (w) */
+ unsigned int reserved_5:7; /**< \brief \internal Reserved */
+ unsigned int CONCOM0:1; /**< \brief [12:12] Grant and Address Trigger Relation (rw) */
+ unsigned int CONCOM1:1; /**< \brief [13:13] Address 1 and Address 2 Trigger Relation (rw) */
+ unsigned int CONCOM2:1; /**< \brief [14:14] Address and Signal Trigger Relation (rw) */
+ unsigned int reserved_15:1; /**< \brief \internal Reserved */
+ unsigned int ONG:1; /**< \brief [16:16] Grant Trigger Enable (rw) */
+ unsigned int reserved_17:3; /**< \brief \internal Reserved */
+ unsigned int ONA1:2; /**< \brief [21:20] Address 1 Trigger Control (rw) */
+ unsigned int reserved_22:2; /**< \brief \internal Reserved */
+ unsigned int ONA2:2; /**< \brief [25:24] Address 2 Trigger Control (rw) */
+ unsigned int reserved_26:2; /**< \brief \internal Reserved */
+ unsigned int ONBOS0:1; /**< \brief [28:28] Opcode Signal Status Trigger Condition (rw) */
+ unsigned int ONBOS1:1; /**< \brief [29:29] Supervisor Mode Signal Trigger Condition (rw) */
+ unsigned int ONBOS2:1; /**< \brief [30:30] Write Signal Trigger Condition (rw) */
+ unsigned int ONBOS3:1; /**< \brief [31:31] Read Signal Trigger Condition (rw) */
+} Ifx_SBCU_DBCNTL_Bits;
+
+/** \brief SBCU Debug Data Status Register */
+typedef struct _Ifx_SBCU_DBDAT_Bits
+{
+ unsigned int FPIDATA:32; /**< \brief [31:0] FPI Bus Data Status (rh) */
+} Ifx_SBCU_DBDAT_Bits;
+
+/** \brief SBCU Debug Trapped Master Register */
+typedef struct _Ifx_SBCU_DBGNTT_Bits
+{
+ unsigned int DMAH:1; /**< \brief [0:0] High-Priority DMA FPI Bus Master Status (rw) */
+ unsigned int ONE0:1; /**< \brief [1:1] Reserved (rw) */
+ unsigned int ETH:1; /**< \brief [2:2] Ethernet FPI Bus Master Status (rw) */
+ unsigned int HSSL:1; /**< \brief [3:3] HSSL FPI Bus Master Status (rw) */
+ unsigned int ONE1:1; /**< \brief [4:4] Reserved (rw) */
+ unsigned int DMAM:1; /**< \brief [5:5] Medium-Priority DMA FPI Bus Master Status (rw) */
+ unsigned int ONE2:1; /**< \brief [6:6] Reserved (rw) */
+ unsigned int CPU0:1; /**< \brief [7:7] CPU0 FPI Bus Master Status (rw) */
+ unsigned int CPU1:1; /**< \brief [8:8] CPU1 FPI Bus Master Status (rw) */
+ unsigned int ONE3:6; /**< \brief [14:9] Reserved (rw) */
+ unsigned int DMAL:1; /**< \brief [15:15] Low-Priority DMA FPI Bus Master Status (rw) */
+ unsigned int DMACHNR:8; /**< \brief [23:16] DMA-FPI Channel Grant Status (rw) */
+ unsigned int ONE4:8; /**< \brief [31:24] Reserved (rw) */
+} Ifx_SBCU_DBGNTT_Bits;
+
+/** \brief SBCU Debug Grant Mask Register */
+typedef struct _Ifx_SBCU_DBGRNT_Bits
+{
+ unsigned int DMAH:1; /**< \brief [0:0] DMA High Priority Trigger Enable (rw) */
+ unsigned int ONE0:1; /**< \brief [1:1] Reserved (rw) */
+ unsigned int ETH:1; /**< \brief [2:2] Ethernet Trigger Enable (rw) */
+ unsigned int HSSL:1; /**< \brief [3:3] HSSL Trigger Enable (rw) */
+ unsigned int ONE1:1; /**< \brief [4:4] Reserved (rw) */
+ unsigned int DMAM:1; /**< \brief [5:5] DMA Grant Trigger Enable, Medium Priority (rw) */
+ unsigned int ONE2:1; /**< \brief [6:6] Reserved (rw) */
+ unsigned int CPU0:1; /**< \brief [7:7] CPU0 Grant Trigger Enable (rw) */
+ unsigned int CPU1:1; /**< \brief [8:8] CPU1 Grant Trigger Enable (rw) */
+ unsigned int ONE3:5; /**< \brief [13:9] Reserved (rw) */
+ unsigned int ONE4:1; /**< \brief [14:14] Reserved (rw) */
+ unsigned int DMAL:1; /**< \brief [15:15] DMA Grant Trigger Enable, Low Priority (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_SBCU_DBGRNT_Bits;
+
+/** \brief SBCU Error Address Capture Register */
+typedef struct _Ifx_SBCU_EADD_Bits
+{
+ unsigned int FPIADR:32; /**< \brief [31:0] Captured FPI Bus Address (rwh) */
+} Ifx_SBCU_EADD_Bits;
+
+/** \brief SBCU Error Control Capture Register */
+typedef struct _Ifx_SBCU_ECON_Bits
+{
+ unsigned int ERRCNT:14; /**< \brief [13:0] FPI Bus Error Counter (rwh) */
+ unsigned int TOUT:1; /**< \brief [14:14] State of FPI Bus Time-Out Signal (rwh) */
+ unsigned int RDY:1; /**< \brief [15:15] State of FPI Bus Ready Signal (rwh) */
+ unsigned int ABT:1; /**< \brief [16:16] State of FPI Bus Abort Signal (rwh) */
+ unsigned int ACK:2; /**< \brief [18:17] State of FPI Bus Acknowledge Signals (rwh) */
+ unsigned int SVM:1; /**< \brief [19:19] State of FPI Bus Supervisor Mode Signal (rwh) */
+ unsigned int WRN:1; /**< \brief [20:20] State of FPI Bus Write Signal (rwh) */
+ unsigned int RDN:1; /**< \brief [21:21] State of FPI Bus Read Signal (rwh) */
+ unsigned int TAG:6; /**< \brief [27:22] FPI Bus Master Tag Number Signals (rwh) */
+ unsigned int OPC:4; /**< \brief [31:28] FPI Bus Operation Code Signals (rwh) */
+} Ifx_SBCU_ECON_Bits;
+
+/** \brief SBCU Error Data Capture Register */
+typedef struct _Ifx_SBCU_EDAT_Bits
+{
+ unsigned int FPIDAT:32; /**< \brief [31:0] Captured FPI Bus Data (rwh) */
+} Ifx_SBCU_EDAT_Bits;
+
+/** \brief Module Identification Register */
+typedef struct _Ifx_SBCU_ID_Bits
+{
+ unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ unsigned int MODNUMBER:8; /**< \brief [15:8] Module Number Value (r) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_SBCU_ID_Bits;
+
+/** \brief Arbiter Priority Register High */
+typedef struct _Ifx_SBCU_PRIOH_Bits
+{
+ unsigned int CPU1:4; /**< \brief [3:0] Master 8 Priority (rw) */
+ unsigned int RESERVED9:4; /**< \brief [7:4] Reserved (rw) */
+ unsigned int RESERVEDA:4; /**< \brief [11:8] Reserved (rw) */
+ unsigned int RESERVEDB:4; /**< \brief [15:12] Reserved (rw) */
+ unsigned int RESERVEDC:4; /**< \brief [19:16] Reserved (rw) */
+ unsigned int RESERVEDD:4; /**< \brief [23:20] Reserved (rw) */
+ unsigned int RESERVEDE:4; /**< \brief [27:24] Reserved (rw) */
+ unsigned int DMAL:4; /**< \brief [31:28] Master 15 Priority (rw) */
+} Ifx_SBCU_PRIOH_Bits;
+
+/** \brief Arbiter Priority Register Low */
+typedef struct _Ifx_SBCU_PRIOL_Bits
+{
+ unsigned int DMAH:4; /**< \brief [3:0] Master 0 Priority (rw) */
+ unsigned int RESERVED1:4; /**< \brief [7:4] Reserved (rw) */
+ unsigned int ETH:4; /**< \brief [11:8] Master 2 Priority (rw) */
+ unsigned int HSSL:4; /**< \brief [15:12] Master 3 Priority (rw) */
+ unsigned int RESERVED4:4; /**< \brief [19:16] Reserved (rw) */
+ unsigned int DMAM:4; /**< \brief [23:20] Master 5 Priority (rw) */
+ unsigned int RESERVED6:4; /**< \brief [27:24] Reserved (rw) */
+ unsigned int CPU0:4; /**< \brief [31:28] Master 7 Priority (rw) */
+} Ifx_SBCU_PRIOL_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Sbcu_union
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SBCU_ACCEN0_Bits B; /**< \brief Bitfield access */
+} Ifx_SBCU_ACCEN0;
+
+/** \brief Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SBCU_ACCEN1_Bits B; /**< \brief Bitfield access */
+} Ifx_SBCU_ACCEN1;
+
+/** \brief SBCU Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SBCU_CON_Bits B; /**< \brief Bitfield access */
+} Ifx_SBCU_CON;
+
+/** \brief SBCU Debug Address 1 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SBCU_DBADR1_Bits B; /**< \brief Bitfield access */
+} Ifx_SBCU_DBADR1;
+
+/** \brief SBCU Debug Address 2 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SBCU_DBADR2_Bits B; /**< \brief Bitfield access */
+} Ifx_SBCU_DBADR2;
+
+/** \brief SBCU Debug Trapped Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SBCU_DBADRT_Bits B; /**< \brief Bitfield access */
+} Ifx_SBCU_DBADRT;
+
+/** \brief SBCU Debug Bus Operation Signals Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SBCU_DBBOS_Bits B; /**< \brief Bitfield access */
+} Ifx_SBCU_DBBOS;
+
+/** \brief SBCU Debug Trapped Bus Operation Signals Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SBCU_DBBOST_Bits B; /**< \brief Bitfield access */
+} Ifx_SBCU_DBBOST;
+
+/** \brief SBCU Debug Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SBCU_DBCNTL_Bits B; /**< \brief Bitfield access */
+} Ifx_SBCU_DBCNTL;
+
+/** \brief SBCU Debug Data Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SBCU_DBDAT_Bits B; /**< \brief Bitfield access */
+} Ifx_SBCU_DBDAT;
+
+/** \brief SBCU Debug Trapped Master Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SBCU_DBGNTT_Bits B; /**< \brief Bitfield access */
+} Ifx_SBCU_DBGNTT;
+
+/** \brief SBCU Debug Grant Mask Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SBCU_DBGRNT_Bits B; /**< \brief Bitfield access */
+} Ifx_SBCU_DBGRNT;
+
+/** \brief SBCU Error Address Capture Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SBCU_EADD_Bits B; /**< \brief Bitfield access */
+} Ifx_SBCU_EADD;
+
+/** \brief SBCU Error Control Capture Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SBCU_ECON_Bits B; /**< \brief Bitfield access */
+} Ifx_SBCU_ECON;
+
+/** \brief SBCU Error Data Capture Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SBCU_EDAT_Bits B; /**< \brief Bitfield access */
+} Ifx_SBCU_EDAT;
+
+/** \brief Module Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SBCU_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_SBCU_ID;
+
+/** \brief Arbiter Priority Register High */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SBCU_PRIOH_Bits B; /**< \brief Bitfield access */
+} Ifx_SBCU_PRIOH;
+
+/** \brief Arbiter Priority Register Low */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SBCU_PRIOL_Bits B; /**< \brief Bitfield access */
+} Ifx_SBCU_PRIOL;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Sbcu_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief SBCU object */
+typedef volatile struct _Ifx_SBCU
+{
+ unsigned char reserved_0[8]; /**< \brief 0, \internal Reserved */
+ Ifx_SBCU_ID ID; /**< \brief 8, Module Identification Register */
+ unsigned char reserved_C[4]; /**< \brief C, \internal Reserved */
+ Ifx_SBCU_CON CON; /**< \brief 10, SBCU Control Register */
+ Ifx_SBCU_PRIOH PRIOH; /**< \brief 14, Arbiter Priority Register High */
+ Ifx_SBCU_PRIOL PRIOL; /**< \brief 18, Arbiter Priority Register Low */
+ unsigned char reserved_1C[4]; /**< \brief 1C, \internal Reserved */
+ Ifx_SBCU_ECON ECON; /**< \brief 20, SBCU Error Control Capture Register */
+ Ifx_SBCU_EADD EADD; /**< \brief 24, SBCU Error Address Capture Register */
+ Ifx_SBCU_EDAT EDAT; /**< \brief 28, SBCU Error Data Capture Register */
+ unsigned char reserved_2C[4]; /**< \brief 2C, \internal Reserved */
+ Ifx_SBCU_DBCNTL DBCNTL; /**< \brief 30, SBCU Debug Control Register */
+ Ifx_SBCU_DBGRNT DBGRNT; /**< \brief 34, SBCU Debug Grant Mask Register */
+ Ifx_SBCU_DBADR1 DBADR1; /**< \brief 38, SBCU Debug Address 1 Register */
+ Ifx_SBCU_DBADR2 DBADR2; /**< \brief 3C, SBCU Debug Address 2 Register */
+ Ifx_SBCU_DBBOS DBBOS; /**< \brief 40, SBCU Debug Bus Operation Signals Register */
+ Ifx_SBCU_DBGNTT DBGNTT; /**< \brief 44, SBCU Debug Trapped Master Register */
+ Ifx_SBCU_DBADRT DBADRT; /**< \brief 48, SBCU Debug Trapped Address Register */
+ Ifx_SBCU_DBBOST DBBOST; /**< \brief 4C, SBCU Debug Trapped Bus Operation Signals Register */
+ Ifx_SBCU_DBDAT DBDAT; /**< \brief 50, SBCU Debug Data Status Register */
+ unsigned char reserved_54[164]; /**< \brief 54, \internal Reserved */
+ Ifx_SBCU_ACCEN1 ACCEN1; /**< \brief F8, Access Enable Register 1 */
+ Ifx_SBCU_ACCEN0 ACCEN0; /**< \brief FC, Access Enable Register 0 */
+} Ifx_SBCU;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXSBCU_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxScu_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxScu_bf.h
new file mode 100644
index 0000000..33d54e4
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxScu_bf.h
@@ -0,0 +1,4932 @@
+/**
+ * \file IfxScu_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Scu_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Scu
+ *
+ */
+#ifndef IFXSCU_BF_H
+#define IFXSCU_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Scu_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN0 */
+#define IFX_SCU_ACCEN0_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN0 */
+#define IFX_SCU_ACCEN0_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN0 */
+#define IFX_SCU_ACCEN0_EN0_OFF (0u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN10 */
+#define IFX_SCU_ACCEN0_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN10 */
+#define IFX_SCU_ACCEN0_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN10 */
+#define IFX_SCU_ACCEN0_EN10_OFF (10u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN11 */
+#define IFX_SCU_ACCEN0_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN11 */
+#define IFX_SCU_ACCEN0_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN11 */
+#define IFX_SCU_ACCEN0_EN11_OFF (11u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN12 */
+#define IFX_SCU_ACCEN0_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN12 */
+#define IFX_SCU_ACCEN0_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN12 */
+#define IFX_SCU_ACCEN0_EN12_OFF (12u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN13 */
+#define IFX_SCU_ACCEN0_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN13 */
+#define IFX_SCU_ACCEN0_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN13 */
+#define IFX_SCU_ACCEN0_EN13_OFF (13u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN14 */
+#define IFX_SCU_ACCEN0_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN14 */
+#define IFX_SCU_ACCEN0_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN14 */
+#define IFX_SCU_ACCEN0_EN14_OFF (14u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN15 */
+#define IFX_SCU_ACCEN0_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN15 */
+#define IFX_SCU_ACCEN0_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN15 */
+#define IFX_SCU_ACCEN0_EN15_OFF (15u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN16 */
+#define IFX_SCU_ACCEN0_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN16 */
+#define IFX_SCU_ACCEN0_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN16 */
+#define IFX_SCU_ACCEN0_EN16_OFF (16u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN17 */
+#define IFX_SCU_ACCEN0_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN17 */
+#define IFX_SCU_ACCEN0_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN17 */
+#define IFX_SCU_ACCEN0_EN17_OFF (17u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN18 */
+#define IFX_SCU_ACCEN0_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN18 */
+#define IFX_SCU_ACCEN0_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN18 */
+#define IFX_SCU_ACCEN0_EN18_OFF (18u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN19 */
+#define IFX_SCU_ACCEN0_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN19 */
+#define IFX_SCU_ACCEN0_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN19 */
+#define IFX_SCU_ACCEN0_EN19_OFF (19u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN1 */
+#define IFX_SCU_ACCEN0_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN1 */
+#define IFX_SCU_ACCEN0_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN1 */
+#define IFX_SCU_ACCEN0_EN1_OFF (1u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN20 */
+#define IFX_SCU_ACCEN0_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN20 */
+#define IFX_SCU_ACCEN0_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN20 */
+#define IFX_SCU_ACCEN0_EN20_OFF (20u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN21 */
+#define IFX_SCU_ACCEN0_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN21 */
+#define IFX_SCU_ACCEN0_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN21 */
+#define IFX_SCU_ACCEN0_EN21_OFF (21u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN22 */
+#define IFX_SCU_ACCEN0_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN22 */
+#define IFX_SCU_ACCEN0_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN22 */
+#define IFX_SCU_ACCEN0_EN22_OFF (22u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN23 */
+#define IFX_SCU_ACCEN0_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN23 */
+#define IFX_SCU_ACCEN0_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN23 */
+#define IFX_SCU_ACCEN0_EN23_OFF (23u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN24 */
+#define IFX_SCU_ACCEN0_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN24 */
+#define IFX_SCU_ACCEN0_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN24 */
+#define IFX_SCU_ACCEN0_EN24_OFF (24u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN25 */
+#define IFX_SCU_ACCEN0_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN25 */
+#define IFX_SCU_ACCEN0_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN25 */
+#define IFX_SCU_ACCEN0_EN25_OFF (25u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN26 */
+#define IFX_SCU_ACCEN0_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN26 */
+#define IFX_SCU_ACCEN0_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN26 */
+#define IFX_SCU_ACCEN0_EN26_OFF (26u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN27 */
+#define IFX_SCU_ACCEN0_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN27 */
+#define IFX_SCU_ACCEN0_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN27 */
+#define IFX_SCU_ACCEN0_EN27_OFF (27u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN28 */
+#define IFX_SCU_ACCEN0_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN28 */
+#define IFX_SCU_ACCEN0_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN28 */
+#define IFX_SCU_ACCEN0_EN28_OFF (28u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN29 */
+#define IFX_SCU_ACCEN0_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN29 */
+#define IFX_SCU_ACCEN0_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN29 */
+#define IFX_SCU_ACCEN0_EN29_OFF (29u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN2 */
+#define IFX_SCU_ACCEN0_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN2 */
+#define IFX_SCU_ACCEN0_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN2 */
+#define IFX_SCU_ACCEN0_EN2_OFF (2u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN30 */
+#define IFX_SCU_ACCEN0_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN30 */
+#define IFX_SCU_ACCEN0_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN30 */
+#define IFX_SCU_ACCEN0_EN30_OFF (30u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN31 */
+#define IFX_SCU_ACCEN0_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN31 */
+#define IFX_SCU_ACCEN0_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN31 */
+#define IFX_SCU_ACCEN0_EN31_OFF (31u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN3 */
+#define IFX_SCU_ACCEN0_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN3 */
+#define IFX_SCU_ACCEN0_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN3 */
+#define IFX_SCU_ACCEN0_EN3_OFF (3u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN4 */
+#define IFX_SCU_ACCEN0_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN4 */
+#define IFX_SCU_ACCEN0_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN4 */
+#define IFX_SCU_ACCEN0_EN4_OFF (4u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN5 */
+#define IFX_SCU_ACCEN0_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN5 */
+#define IFX_SCU_ACCEN0_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN5 */
+#define IFX_SCU_ACCEN0_EN5_OFF (5u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN6 */
+#define IFX_SCU_ACCEN0_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN6 */
+#define IFX_SCU_ACCEN0_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN6 */
+#define IFX_SCU_ACCEN0_EN6_OFF (6u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN7 */
+#define IFX_SCU_ACCEN0_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN7 */
+#define IFX_SCU_ACCEN0_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN7 */
+#define IFX_SCU_ACCEN0_EN7_OFF (7u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN8 */
+#define IFX_SCU_ACCEN0_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN8 */
+#define IFX_SCU_ACCEN0_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN8 */
+#define IFX_SCU_ACCEN0_EN8_OFF (8u)
+
+/** \brief Length for Ifx_SCU_ACCEN0_Bits.EN9 */
+#define IFX_SCU_ACCEN0_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ACCEN0_Bits.EN9 */
+#define IFX_SCU_ACCEN0_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ACCEN0_Bits.EN9 */
+#define IFX_SCU_ACCEN0_EN9_OFF (9u)
+
+/** \brief Length for Ifx_SCU_ARSTDIS_Bits.STM0DIS */
+#define IFX_SCU_ARSTDIS_STM0DIS_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ARSTDIS_Bits.STM0DIS */
+#define IFX_SCU_ARSTDIS_STM0DIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ARSTDIS_Bits.STM0DIS */
+#define IFX_SCU_ARSTDIS_STM0DIS_OFF (0u)
+
+/** \brief Length for Ifx_SCU_ARSTDIS_Bits.STM1DIS */
+#define IFX_SCU_ARSTDIS_STM1DIS_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ARSTDIS_Bits.STM1DIS */
+#define IFX_SCU_ARSTDIS_STM1DIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ARSTDIS_Bits.STM1DIS */
+#define IFX_SCU_ARSTDIS_STM1DIS_OFF (1u)
+
+/** \brief Length for Ifx_SCU_ARSTDIS_Bits.STM2DIS */
+#define IFX_SCU_ARSTDIS_STM2DIS_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ARSTDIS_Bits.STM2DIS */
+#define IFX_SCU_ARSTDIS_STM2DIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ARSTDIS_Bits.STM2DIS */
+#define IFX_SCU_ARSTDIS_STM2DIS_OFF (2u)
+
+/** \brief Length for Ifx_SCU_CCUCON0_Bits.BAUD1DIV */
+#define IFX_SCU_CCUCON0_BAUD1DIV_LEN (4u)
+
+/** \brief Mask for Ifx_SCU_CCUCON0_Bits.BAUD1DIV */
+#define IFX_SCU_CCUCON0_BAUD1DIV_MSK (0xfu)
+
+/** \brief Offset for Ifx_SCU_CCUCON0_Bits.BAUD1DIV */
+#define IFX_SCU_CCUCON0_BAUD1DIV_OFF (0u)
+
+/** \brief Length for Ifx_SCU_CCUCON0_Bits.BAUD2DIV */
+#define IFX_SCU_CCUCON0_BAUD2DIV_LEN (4u)
+
+/** \brief Mask for Ifx_SCU_CCUCON0_Bits.BAUD2DIV */
+#define IFX_SCU_CCUCON0_BAUD2DIV_MSK (0xfu)
+
+/** \brief Offset for Ifx_SCU_CCUCON0_Bits.BAUD2DIV */
+#define IFX_SCU_CCUCON0_BAUD2DIV_OFF (4u)
+
+/** \brief Length for Ifx_SCU_CCUCON0_Bits.CLKSEL */
+#define IFX_SCU_CCUCON0_CLKSEL_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_CCUCON0_Bits.CLKSEL */
+#define IFX_SCU_CCUCON0_CLKSEL_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_CCUCON0_Bits.CLKSEL */
+#define IFX_SCU_CCUCON0_CLKSEL_OFF (28u)
+
+/** \brief Length for Ifx_SCU_CCUCON0_Bits.FSI2DIV */
+#define IFX_SCU_CCUCON0_FSI2DIV_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_CCUCON0_Bits.FSI2DIV */
+#define IFX_SCU_CCUCON0_FSI2DIV_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_CCUCON0_Bits.FSI2DIV */
+#define IFX_SCU_CCUCON0_FSI2DIV_OFF (20u)
+
+/** \brief Length for Ifx_SCU_CCUCON0_Bits.FSIDIV */
+#define IFX_SCU_CCUCON0_FSIDIV_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_CCUCON0_Bits.FSIDIV */
+#define IFX_SCU_CCUCON0_FSIDIV_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_CCUCON0_Bits.FSIDIV */
+#define IFX_SCU_CCUCON0_FSIDIV_OFF (24u)
+
+/** \brief Length for Ifx_SCU_CCUCON0_Bits.LCK */
+#define IFX_SCU_CCUCON0_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_CCUCON0_Bits.LCK */
+#define IFX_SCU_CCUCON0_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_CCUCON0_Bits.LCK */
+#define IFX_SCU_CCUCON0_LCK_OFF (31u)
+
+/** \brief Length for Ifx_SCU_CCUCON0_Bits.LPDIV */
+#define IFX_SCU_CCUCON0_LPDIV_LEN (4u)
+
+/** \brief Mask for Ifx_SCU_CCUCON0_Bits.LPDIV */
+#define IFX_SCU_CCUCON0_LPDIV_MSK (0xfu)
+
+/** \brief Offset for Ifx_SCU_CCUCON0_Bits.LPDIV */
+#define IFX_SCU_CCUCON0_LPDIV_OFF (12u)
+
+/** \brief Length for Ifx_SCU_CCUCON0_Bits.SPBDIV */
+#define IFX_SCU_CCUCON0_SPBDIV_LEN (4u)
+
+/** \brief Mask for Ifx_SCU_CCUCON0_Bits.SPBDIV */
+#define IFX_SCU_CCUCON0_SPBDIV_MSK (0xfu)
+
+/** \brief Offset for Ifx_SCU_CCUCON0_Bits.SPBDIV */
+#define IFX_SCU_CCUCON0_SPBDIV_OFF (16u)
+
+/** \brief Length for Ifx_SCU_CCUCON0_Bits.SRIDIV */
+#define IFX_SCU_CCUCON0_SRIDIV_LEN (4u)
+
+/** \brief Mask for Ifx_SCU_CCUCON0_Bits.SRIDIV */
+#define IFX_SCU_CCUCON0_SRIDIV_MSK (0xfu)
+
+/** \brief Offset for Ifx_SCU_CCUCON0_Bits.SRIDIV */
+#define IFX_SCU_CCUCON0_SRIDIV_OFF (8u)
+
+/** \brief Length for Ifx_SCU_CCUCON0_Bits.UP */
+#define IFX_SCU_CCUCON0_UP_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_CCUCON0_Bits.UP */
+#define IFX_SCU_CCUCON0_UP_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_CCUCON0_Bits.UP */
+#define IFX_SCU_CCUCON0_UP_OFF (30u)
+
+/** \brief Length for Ifx_SCU_CCUCON1_Bits.ASCLINFDIV */
+#define IFX_SCU_CCUCON1_ASCLINFDIV_LEN (4u)
+
+/** \brief Mask for Ifx_SCU_CCUCON1_Bits.ASCLINFDIV */
+#define IFX_SCU_CCUCON1_ASCLINFDIV_MSK (0xfu)
+
+/** \brief Offset for Ifx_SCU_CCUCON1_Bits.ASCLINFDIV */
+#define IFX_SCU_CCUCON1_ASCLINFDIV_OFF (20u)
+
+/** \brief Length for Ifx_SCU_CCUCON1_Bits.ASCLINSDIV */
+#define IFX_SCU_CCUCON1_ASCLINSDIV_LEN (4u)
+
+/** \brief Mask for Ifx_SCU_CCUCON1_Bits.ASCLINSDIV */
+#define IFX_SCU_CCUCON1_ASCLINSDIV_MSK (0xfu)
+
+/** \brief Offset for Ifx_SCU_CCUCON1_Bits.ASCLINSDIV */
+#define IFX_SCU_CCUCON1_ASCLINSDIV_OFF (24u)
+
+/** \brief Length for Ifx_SCU_CCUCON1_Bits.CANDIV */
+#define IFX_SCU_CCUCON1_CANDIV_LEN (4u)
+
+/** \brief Mask for Ifx_SCU_CCUCON1_Bits.CANDIV */
+#define IFX_SCU_CCUCON1_CANDIV_MSK (0xfu)
+
+/** \brief Offset for Ifx_SCU_CCUCON1_Bits.CANDIV */
+#define IFX_SCU_CCUCON1_CANDIV_OFF (0u)
+
+/** \brief Length for Ifx_SCU_CCUCON1_Bits.ERAYDIV */
+#define IFX_SCU_CCUCON1_ERAYDIV_LEN (4u)
+
+/** \brief Mask for Ifx_SCU_CCUCON1_Bits.ERAYDIV */
+#define IFX_SCU_CCUCON1_ERAYDIV_MSK (0xfu)
+
+/** \brief Offset for Ifx_SCU_CCUCON1_Bits.ERAYDIV */
+#define IFX_SCU_CCUCON1_ERAYDIV_OFF (4u)
+
+/** \brief Length for Ifx_SCU_CCUCON1_Bits.ETHDIV */
+#define IFX_SCU_CCUCON1_ETHDIV_LEN (4u)
+
+/** \brief Mask for Ifx_SCU_CCUCON1_Bits.ETHDIV */
+#define IFX_SCU_CCUCON1_ETHDIV_MSK (0xfu)
+
+/** \brief Offset for Ifx_SCU_CCUCON1_Bits.ETHDIV */
+#define IFX_SCU_CCUCON1_ETHDIV_OFF (16u)
+
+/** \brief Length for Ifx_SCU_CCUCON1_Bits.GTMDIV */
+#define IFX_SCU_CCUCON1_GTMDIV_LEN (4u)
+
+/** \brief Mask for Ifx_SCU_CCUCON1_Bits.GTMDIV */
+#define IFX_SCU_CCUCON1_GTMDIV_MSK (0xfu)
+
+/** \brief Offset for Ifx_SCU_CCUCON1_Bits.GTMDIV */
+#define IFX_SCU_CCUCON1_GTMDIV_OFF (12u)
+
+/** \brief Length for Ifx_SCU_CCUCON1_Bits.INSEL */
+#define IFX_SCU_CCUCON1_INSEL_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_CCUCON1_Bits.INSEL */
+#define IFX_SCU_CCUCON1_INSEL_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_CCUCON1_Bits.INSEL */
+#define IFX_SCU_CCUCON1_INSEL_OFF (28u)
+
+/** \brief Length for Ifx_SCU_CCUCON1_Bits.LCK */
+#define IFX_SCU_CCUCON1_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_CCUCON1_Bits.LCK */
+#define IFX_SCU_CCUCON1_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_CCUCON1_Bits.LCK */
+#define IFX_SCU_CCUCON1_LCK_OFF (31u)
+
+/** \brief Length for Ifx_SCU_CCUCON1_Bits.STMDIV */
+#define IFX_SCU_CCUCON1_STMDIV_LEN (4u)
+
+/** \brief Mask for Ifx_SCU_CCUCON1_Bits.STMDIV */
+#define IFX_SCU_CCUCON1_STMDIV_MSK (0xfu)
+
+/** \brief Offset for Ifx_SCU_CCUCON1_Bits.STMDIV */
+#define IFX_SCU_CCUCON1_STMDIV_OFF (8u)
+
+/** \brief Length for Ifx_SCU_CCUCON1_Bits.UP */
+#define IFX_SCU_CCUCON1_UP_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_CCUCON1_Bits.UP */
+#define IFX_SCU_CCUCON1_UP_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_CCUCON1_Bits.UP */
+#define IFX_SCU_CCUCON1_UP_OFF (30u)
+
+/** \brief Length for Ifx_SCU_CCUCON2_Bits.BBBDIV */
+#define IFX_SCU_CCUCON2_BBBDIV_LEN (4u)
+
+/** \brief Mask for Ifx_SCU_CCUCON2_Bits.BBBDIV */
+#define IFX_SCU_CCUCON2_BBBDIV_MSK (0xfu)
+
+/** \brief Offset for Ifx_SCU_CCUCON2_Bits.BBBDIV */
+#define IFX_SCU_CCUCON2_BBBDIV_OFF (0u)
+
+/** \brief Length for Ifx_SCU_CCUCON2_Bits.LCK */
+#define IFX_SCU_CCUCON2_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_CCUCON2_Bits.LCK */
+#define IFX_SCU_CCUCON2_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_CCUCON2_Bits.LCK */
+#define IFX_SCU_CCUCON2_LCK_OFF (31u)
+
+/** \brief Length for Ifx_SCU_CCUCON2_Bits.UP */
+#define IFX_SCU_CCUCON2_UP_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_CCUCON2_Bits.UP */
+#define IFX_SCU_CCUCON2_UP_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_CCUCON2_Bits.UP */
+#define IFX_SCU_CCUCON2_UP_OFF (30u)
+
+/** \brief Length for Ifx_SCU_CCUCON3_Bits.LCK */
+#define IFX_SCU_CCUCON3_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_CCUCON3_Bits.LCK */
+#define IFX_SCU_CCUCON3_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_CCUCON3_Bits.LCK */
+#define IFX_SCU_CCUCON3_LCK_OFF (31u)
+
+/** \brief Length for Ifx_SCU_CCUCON3_Bits.PLLDIV */
+#define IFX_SCU_CCUCON3_PLLDIV_LEN (6u)
+
+/** \brief Mask for Ifx_SCU_CCUCON3_Bits.PLLDIV */
+#define IFX_SCU_CCUCON3_PLLDIV_MSK (0x3fu)
+
+/** \brief Offset for Ifx_SCU_CCUCON3_Bits.PLLDIV */
+#define IFX_SCU_CCUCON3_PLLDIV_OFF (0u)
+
+/** \brief Length for Ifx_SCU_CCUCON3_Bits.PLLERAYDIV */
+#define IFX_SCU_CCUCON3_PLLERAYDIV_LEN (6u)
+
+/** \brief Mask for Ifx_SCU_CCUCON3_Bits.PLLERAYDIV */
+#define IFX_SCU_CCUCON3_PLLERAYDIV_MSK (0x3fu)
+
+/** \brief Offset for Ifx_SCU_CCUCON3_Bits.PLLERAYDIV */
+#define IFX_SCU_CCUCON3_PLLERAYDIV_OFF (8u)
+
+/** \brief Length for Ifx_SCU_CCUCON3_Bits.PLLERAYSEL */
+#define IFX_SCU_CCUCON3_PLLERAYSEL_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_CCUCON3_Bits.PLLERAYSEL */
+#define IFX_SCU_CCUCON3_PLLERAYSEL_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_CCUCON3_Bits.PLLERAYSEL */
+#define IFX_SCU_CCUCON3_PLLERAYSEL_OFF (14u)
+
+/** \brief Length for Ifx_SCU_CCUCON3_Bits.PLLSEL */
+#define IFX_SCU_CCUCON3_PLLSEL_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_CCUCON3_Bits.PLLSEL */
+#define IFX_SCU_CCUCON3_PLLSEL_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_CCUCON3_Bits.PLLSEL */
+#define IFX_SCU_CCUCON3_PLLSEL_OFF (6u)
+
+/** \brief Length for Ifx_SCU_CCUCON3_Bits.SLCK */
+#define IFX_SCU_CCUCON3_SLCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_CCUCON3_Bits.SLCK */
+#define IFX_SCU_CCUCON3_SLCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_CCUCON3_Bits.SLCK */
+#define IFX_SCU_CCUCON3_SLCK_OFF (29u)
+
+/** \brief Length for Ifx_SCU_CCUCON3_Bits.SRIDIV */
+#define IFX_SCU_CCUCON3_SRIDIV_LEN (6u)
+
+/** \brief Mask for Ifx_SCU_CCUCON3_Bits.SRIDIV */
+#define IFX_SCU_CCUCON3_SRIDIV_MSK (0x3fu)
+
+/** \brief Offset for Ifx_SCU_CCUCON3_Bits.SRIDIV */
+#define IFX_SCU_CCUCON3_SRIDIV_OFF (16u)
+
+/** \brief Length for Ifx_SCU_CCUCON3_Bits.SRISEL */
+#define IFX_SCU_CCUCON3_SRISEL_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_CCUCON3_Bits.SRISEL */
+#define IFX_SCU_CCUCON3_SRISEL_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_CCUCON3_Bits.SRISEL */
+#define IFX_SCU_CCUCON3_SRISEL_OFF (22u)
+
+/** \brief Length for Ifx_SCU_CCUCON3_Bits.UP */
+#define IFX_SCU_CCUCON3_UP_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_CCUCON3_Bits.UP */
+#define IFX_SCU_CCUCON3_UP_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_CCUCON3_Bits.UP */
+#define IFX_SCU_CCUCON3_UP_OFF (30u)
+
+/** \brief Length for Ifx_SCU_CCUCON4_Bits.GTMDIV */
+#define IFX_SCU_CCUCON4_GTMDIV_LEN (6u)
+
+/** \brief Mask for Ifx_SCU_CCUCON4_Bits.GTMDIV */
+#define IFX_SCU_CCUCON4_GTMDIV_MSK (0x3fu)
+
+/** \brief Offset for Ifx_SCU_CCUCON4_Bits.GTMDIV */
+#define IFX_SCU_CCUCON4_GTMDIV_OFF (8u)
+
+/** \brief Length for Ifx_SCU_CCUCON4_Bits.GTMSEL */
+#define IFX_SCU_CCUCON4_GTMSEL_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_CCUCON4_Bits.GTMSEL */
+#define IFX_SCU_CCUCON4_GTMSEL_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_CCUCON4_Bits.GTMSEL */
+#define IFX_SCU_CCUCON4_GTMSEL_OFF (14u)
+
+/** \brief Length for Ifx_SCU_CCUCON4_Bits.LCK */
+#define IFX_SCU_CCUCON4_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_CCUCON4_Bits.LCK */
+#define IFX_SCU_CCUCON4_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_CCUCON4_Bits.LCK */
+#define IFX_SCU_CCUCON4_LCK_OFF (31u)
+
+/** \brief Length for Ifx_SCU_CCUCON4_Bits.SLCK */
+#define IFX_SCU_CCUCON4_SLCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_CCUCON4_Bits.SLCK */
+#define IFX_SCU_CCUCON4_SLCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_CCUCON4_Bits.SLCK */
+#define IFX_SCU_CCUCON4_SLCK_OFF (29u)
+
+/** \brief Length for Ifx_SCU_CCUCON4_Bits.SPBDIV */
+#define IFX_SCU_CCUCON4_SPBDIV_LEN (6u)
+
+/** \brief Mask for Ifx_SCU_CCUCON4_Bits.SPBDIV */
+#define IFX_SCU_CCUCON4_SPBDIV_MSK (0x3fu)
+
+/** \brief Offset for Ifx_SCU_CCUCON4_Bits.SPBDIV */
+#define IFX_SCU_CCUCON4_SPBDIV_OFF (0u)
+
+/** \brief Length for Ifx_SCU_CCUCON4_Bits.SPBSEL */
+#define IFX_SCU_CCUCON4_SPBSEL_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_CCUCON4_Bits.SPBSEL */
+#define IFX_SCU_CCUCON4_SPBSEL_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_CCUCON4_Bits.SPBSEL */
+#define IFX_SCU_CCUCON4_SPBSEL_OFF (6u)
+
+/** \brief Length for Ifx_SCU_CCUCON4_Bits.STMDIV */
+#define IFX_SCU_CCUCON4_STMDIV_LEN (6u)
+
+/** \brief Mask for Ifx_SCU_CCUCON4_Bits.STMDIV */
+#define IFX_SCU_CCUCON4_STMDIV_MSK (0x3fu)
+
+/** \brief Offset for Ifx_SCU_CCUCON4_Bits.STMDIV */
+#define IFX_SCU_CCUCON4_STMDIV_OFF (16u)
+
+/** \brief Length for Ifx_SCU_CCUCON4_Bits.STMSEL */
+#define IFX_SCU_CCUCON4_STMSEL_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_CCUCON4_Bits.STMSEL */
+#define IFX_SCU_CCUCON4_STMSEL_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_CCUCON4_Bits.STMSEL */
+#define IFX_SCU_CCUCON4_STMSEL_OFF (22u)
+
+/** \brief Length for Ifx_SCU_CCUCON4_Bits.UP */
+#define IFX_SCU_CCUCON4_UP_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_CCUCON4_Bits.UP */
+#define IFX_SCU_CCUCON4_UP_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_CCUCON4_Bits.UP */
+#define IFX_SCU_CCUCON4_UP_OFF (30u)
+
+/** \brief Length for Ifx_SCU_CCUCON5_Bits.LCK */
+#define IFX_SCU_CCUCON5_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_CCUCON5_Bits.LCK */
+#define IFX_SCU_CCUCON5_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_CCUCON5_Bits.LCK */
+#define IFX_SCU_CCUCON5_LCK_OFF (31u)
+
+/** \brief Length for Ifx_SCU_CCUCON5_Bits.MAXDIV */
+#define IFX_SCU_CCUCON5_MAXDIV_LEN (4u)
+
+/** \brief Mask for Ifx_SCU_CCUCON5_Bits.MAXDIV */
+#define IFX_SCU_CCUCON5_MAXDIV_MSK (0xfu)
+
+/** \brief Offset for Ifx_SCU_CCUCON5_Bits.MAXDIV */
+#define IFX_SCU_CCUCON5_MAXDIV_OFF (0u)
+
+/** \brief Length for Ifx_SCU_CCUCON5_Bits.UP */
+#define IFX_SCU_CCUCON5_UP_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_CCUCON5_Bits.UP */
+#define IFX_SCU_CCUCON5_UP_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_CCUCON5_Bits.UP */
+#define IFX_SCU_CCUCON5_UP_OFF (30u)
+
+/** \brief Length for Ifx_SCU_CCUCON6_Bits.CPU0DIV */
+#define IFX_SCU_CCUCON6_CPU0DIV_LEN (6u)
+
+/** \brief Mask for Ifx_SCU_CCUCON6_Bits.CPU0DIV */
+#define IFX_SCU_CCUCON6_CPU0DIV_MSK (0x3fu)
+
+/** \brief Offset for Ifx_SCU_CCUCON6_Bits.CPU0DIV */
+#define IFX_SCU_CCUCON6_CPU0DIV_OFF (0u)
+
+/** \brief Length for Ifx_SCU_CCUCON7_Bits.CPU1DIV */
+#define IFX_SCU_CCUCON7_CPU1DIV_LEN (6u)
+
+/** \brief Mask for Ifx_SCU_CCUCON7_Bits.CPU1DIV */
+#define IFX_SCU_CCUCON7_CPU1DIV_MSK (0x3fu)
+
+/** \brief Offset for Ifx_SCU_CCUCON7_Bits.CPU1DIV */
+#define IFX_SCU_CCUCON7_CPU1DIV_OFF (0u)
+
+/** \brief Length for Ifx_SCU_CHIPID_Bits.CHID */
+#define IFX_SCU_CHIPID_CHID_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_CHIPID_Bits.CHID */
+#define IFX_SCU_CHIPID_CHID_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_CHIPID_Bits.CHID */
+#define IFX_SCU_CHIPID_CHID_OFF (8u)
+
+/** \brief Length for Ifx_SCU_CHIPID_Bits.CHREV */
+#define IFX_SCU_CHIPID_CHREV_LEN (6u)
+
+/** \brief Mask for Ifx_SCU_CHIPID_Bits.CHREV */
+#define IFX_SCU_CHIPID_CHREV_MSK (0x3fu)
+
+/** \brief Offset for Ifx_SCU_CHIPID_Bits.CHREV */
+#define IFX_SCU_CHIPID_CHREV_OFF (0u)
+
+/** \brief Length for Ifx_SCU_CHIPID_Bits.CHTEC */
+#define IFX_SCU_CHIPID_CHTEC_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_CHIPID_Bits.CHTEC */
+#define IFX_SCU_CHIPID_CHTEC_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_CHIPID_Bits.CHTEC */
+#define IFX_SCU_CHIPID_CHTEC_OFF (6u)
+
+/** \brief Length for Ifx_SCU_CHIPID_Bits.EEA */
+#define IFX_SCU_CHIPID_EEA_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_CHIPID_Bits.EEA */
+#define IFX_SCU_CHIPID_EEA_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_CHIPID_Bits.EEA */
+#define IFX_SCU_CHIPID_EEA_OFF (16u)
+
+/** \brief Length for Ifx_SCU_CHIPID_Bits.FSIZE */
+#define IFX_SCU_CHIPID_FSIZE_LEN (4u)
+
+/** \brief Mask for Ifx_SCU_CHIPID_Bits.FSIZE */
+#define IFX_SCU_CHIPID_FSIZE_MSK (0xfu)
+
+/** \brief Offset for Ifx_SCU_CHIPID_Bits.FSIZE */
+#define IFX_SCU_CHIPID_FSIZE_OFF (24u)
+
+/** \brief Length for Ifx_SCU_CHIPID_Bits.SEC */
+#define IFX_SCU_CHIPID_SEC_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_CHIPID_Bits.SEC */
+#define IFX_SCU_CHIPID_SEC_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_CHIPID_Bits.SEC */
+#define IFX_SCU_CHIPID_SEC_OFF (30u)
+
+/** \brief Length for Ifx_SCU_CHIPID_Bits.SP */
+#define IFX_SCU_CHIPID_SP_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_CHIPID_Bits.SP */
+#define IFX_SCU_CHIPID_SP_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_CHIPID_Bits.SP */
+#define IFX_SCU_CHIPID_SP_OFF (28u)
+
+/** \brief Length for Ifx_SCU_CHIPID_Bits.UCODE */
+#define IFX_SCU_CHIPID_UCODE_LEN (7u)
+
+/** \brief Mask for Ifx_SCU_CHIPID_Bits.UCODE */
+#define IFX_SCU_CHIPID_UCODE_MSK (0x7fu)
+
+/** \brief Offset for Ifx_SCU_CHIPID_Bits.UCODE */
+#define IFX_SCU_CHIPID_UCODE_OFF (17u)
+
+/** \brief Length for Ifx_SCU_DTSCON_Bits.CAL */
+#define IFX_SCU_DTSCON_CAL_LEN (20u)
+
+/** \brief Mask for Ifx_SCU_DTSCON_Bits.CAL */
+#define IFX_SCU_DTSCON_CAL_MSK (0xfffffu)
+
+/** \brief Offset for Ifx_SCU_DTSCON_Bits.CAL */
+#define IFX_SCU_DTSCON_CAL_OFF (4u)
+
+/** \brief Length for Ifx_SCU_DTSCON_Bits.PWD */
+#define IFX_SCU_DTSCON_PWD_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_DTSCON_Bits.PWD */
+#define IFX_SCU_DTSCON_PWD_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_DTSCON_Bits.PWD */
+#define IFX_SCU_DTSCON_PWD_OFF (0u)
+
+/** \brief Length for Ifx_SCU_DTSCON_Bits.SLCK */
+#define IFX_SCU_DTSCON_SLCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_DTSCON_Bits.SLCK */
+#define IFX_SCU_DTSCON_SLCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_DTSCON_Bits.SLCK */
+#define IFX_SCU_DTSCON_SLCK_OFF (31u)
+
+/** \brief Length for Ifx_SCU_DTSCON_Bits.START */
+#define IFX_SCU_DTSCON_START_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_DTSCON_Bits.START */
+#define IFX_SCU_DTSCON_START_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_DTSCON_Bits.START */
+#define IFX_SCU_DTSCON_START_OFF (1u)
+
+/** \brief Length for Ifx_SCU_DTSLIM_Bits.LLU */
+#define IFX_SCU_DTSLIM_LLU_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_DTSLIM_Bits.LLU */
+#define IFX_SCU_DTSLIM_LLU_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_DTSLIM_Bits.LLU */
+#define IFX_SCU_DTSLIM_LLU_OFF (15u)
+
+/** \brief Length for Ifx_SCU_DTSLIM_Bits.LOWER */
+#define IFX_SCU_DTSLIM_LOWER_LEN (10u)
+
+/** \brief Mask for Ifx_SCU_DTSLIM_Bits.LOWER */
+#define IFX_SCU_DTSLIM_LOWER_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_SCU_DTSLIM_Bits.LOWER */
+#define IFX_SCU_DTSLIM_LOWER_OFF (0u)
+
+/** \brief Length for Ifx_SCU_DTSLIM_Bits.SLCK */
+#define IFX_SCU_DTSLIM_SLCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_DTSLIM_Bits.SLCK */
+#define IFX_SCU_DTSLIM_SLCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_DTSLIM_Bits.SLCK */
+#define IFX_SCU_DTSLIM_SLCK_OFF (30u)
+
+/** \brief Length for Ifx_SCU_DTSLIM_Bits.UOF */
+#define IFX_SCU_DTSLIM_UOF_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_DTSLIM_Bits.UOF */
+#define IFX_SCU_DTSLIM_UOF_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_DTSLIM_Bits.UOF */
+#define IFX_SCU_DTSLIM_UOF_OFF (31u)
+
+/** \brief Length for Ifx_SCU_DTSLIM_Bits.UPPER */
+#define IFX_SCU_DTSLIM_UPPER_LEN (10u)
+
+/** \brief Mask for Ifx_SCU_DTSLIM_Bits.UPPER */
+#define IFX_SCU_DTSLIM_UPPER_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_SCU_DTSLIM_Bits.UPPER */
+#define IFX_SCU_DTSLIM_UPPER_OFF (16u)
+
+/** \brief Length for Ifx_SCU_DTSSTAT_Bits.BUSY */
+#define IFX_SCU_DTSSTAT_BUSY_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_DTSSTAT_Bits.BUSY */
+#define IFX_SCU_DTSSTAT_BUSY_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_DTSSTAT_Bits.BUSY */
+#define IFX_SCU_DTSSTAT_BUSY_OFF (15u)
+
+/** \brief Length for Ifx_SCU_DTSSTAT_Bits.RDY */
+#define IFX_SCU_DTSSTAT_RDY_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_DTSSTAT_Bits.RDY */
+#define IFX_SCU_DTSSTAT_RDY_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_DTSSTAT_Bits.RDY */
+#define IFX_SCU_DTSSTAT_RDY_OFF (14u)
+
+/** \brief Length for Ifx_SCU_DTSSTAT_Bits.RESULT */
+#define IFX_SCU_DTSSTAT_RESULT_LEN (10u)
+
+/** \brief Mask for Ifx_SCU_DTSSTAT_Bits.RESULT */
+#define IFX_SCU_DTSSTAT_RESULT_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_SCU_DTSSTAT_Bits.RESULT */
+#define IFX_SCU_DTSSTAT_RESULT_OFF (0u)
+
+/** \brief Length for Ifx_SCU_EICR_Bits.EIEN0 */
+#define IFX_SCU_EICR_EIEN0_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EICR_Bits.EIEN0 */
+#define IFX_SCU_EICR_EIEN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EICR_Bits.EIEN0 */
+#define IFX_SCU_EICR_EIEN0_OFF (11u)
+
+/** \brief Length for Ifx_SCU_EICR_Bits.EIEN1 */
+#define IFX_SCU_EICR_EIEN1_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EICR_Bits.EIEN1 */
+#define IFX_SCU_EICR_EIEN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EICR_Bits.EIEN1 */
+#define IFX_SCU_EICR_EIEN1_OFF (27u)
+
+/** \brief Length for Ifx_SCU_EICR_Bits.EXIS0 */
+#define IFX_SCU_EICR_EXIS0_LEN (3u)
+
+/** \brief Mask for Ifx_SCU_EICR_Bits.EXIS0 */
+#define IFX_SCU_EICR_EXIS0_MSK (0x7u)
+
+/** \brief Offset for Ifx_SCU_EICR_Bits.EXIS0 */
+#define IFX_SCU_EICR_EXIS0_OFF (4u)
+
+/** \brief Length for Ifx_SCU_EICR_Bits.EXIS1 */
+#define IFX_SCU_EICR_EXIS1_LEN (3u)
+
+/** \brief Mask for Ifx_SCU_EICR_Bits.EXIS1 */
+#define IFX_SCU_EICR_EXIS1_MSK (0x7u)
+
+/** \brief Offset for Ifx_SCU_EICR_Bits.EXIS1 */
+#define IFX_SCU_EICR_EXIS1_OFF (20u)
+
+/** \brief Length for Ifx_SCU_EICR_Bits.FEN0 */
+#define IFX_SCU_EICR_FEN0_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EICR_Bits.FEN0 */
+#define IFX_SCU_EICR_FEN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EICR_Bits.FEN0 */
+#define IFX_SCU_EICR_FEN0_OFF (8u)
+
+/** \brief Length for Ifx_SCU_EICR_Bits.FEN1 */
+#define IFX_SCU_EICR_FEN1_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EICR_Bits.FEN1 */
+#define IFX_SCU_EICR_FEN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EICR_Bits.FEN1 */
+#define IFX_SCU_EICR_FEN1_OFF (24u)
+
+/** \brief Length for Ifx_SCU_EICR_Bits.INP0 */
+#define IFX_SCU_EICR_INP0_LEN (3u)
+
+/** \brief Mask for Ifx_SCU_EICR_Bits.INP0 */
+#define IFX_SCU_EICR_INP0_MSK (0x7u)
+
+/** \brief Offset for Ifx_SCU_EICR_Bits.INP0 */
+#define IFX_SCU_EICR_INP0_OFF (12u)
+
+/** \brief Length for Ifx_SCU_EICR_Bits.INP1 */
+#define IFX_SCU_EICR_INP1_LEN (3u)
+
+/** \brief Mask for Ifx_SCU_EICR_Bits.INP1 */
+#define IFX_SCU_EICR_INP1_MSK (0x7u)
+
+/** \brief Offset for Ifx_SCU_EICR_Bits.INP1 */
+#define IFX_SCU_EICR_INP1_OFF (28u)
+
+/** \brief Length for Ifx_SCU_EICR_Bits.LDEN0 */
+#define IFX_SCU_EICR_LDEN0_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EICR_Bits.LDEN0 */
+#define IFX_SCU_EICR_LDEN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EICR_Bits.LDEN0 */
+#define IFX_SCU_EICR_LDEN0_OFF (10u)
+
+/** \brief Length for Ifx_SCU_EICR_Bits.LDEN1 */
+#define IFX_SCU_EICR_LDEN1_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EICR_Bits.LDEN1 */
+#define IFX_SCU_EICR_LDEN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EICR_Bits.LDEN1 */
+#define IFX_SCU_EICR_LDEN1_OFF (26u)
+
+/** \brief Length for Ifx_SCU_EICR_Bits.REN0 */
+#define IFX_SCU_EICR_REN0_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EICR_Bits.REN0 */
+#define IFX_SCU_EICR_REN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EICR_Bits.REN0 */
+#define IFX_SCU_EICR_REN0_OFF (9u)
+
+/** \brief Length for Ifx_SCU_EICR_Bits.REN1 */
+#define IFX_SCU_EICR_REN1_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EICR_Bits.REN1 */
+#define IFX_SCU_EICR_REN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EICR_Bits.REN1 */
+#define IFX_SCU_EICR_REN1_OFF (25u)
+
+/** \brief Length for Ifx_SCU_EIFR_Bits.INTF0 */
+#define IFX_SCU_EIFR_INTF0_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EIFR_Bits.INTF0 */
+#define IFX_SCU_EIFR_INTF0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EIFR_Bits.INTF0 */
+#define IFX_SCU_EIFR_INTF0_OFF (0u)
+
+/** \brief Length for Ifx_SCU_EIFR_Bits.INTF1 */
+#define IFX_SCU_EIFR_INTF1_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EIFR_Bits.INTF1 */
+#define IFX_SCU_EIFR_INTF1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EIFR_Bits.INTF1 */
+#define IFX_SCU_EIFR_INTF1_OFF (1u)
+
+/** \brief Length for Ifx_SCU_EIFR_Bits.INTF2 */
+#define IFX_SCU_EIFR_INTF2_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EIFR_Bits.INTF2 */
+#define IFX_SCU_EIFR_INTF2_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EIFR_Bits.INTF2 */
+#define IFX_SCU_EIFR_INTF2_OFF (2u)
+
+/** \brief Length for Ifx_SCU_EIFR_Bits.INTF3 */
+#define IFX_SCU_EIFR_INTF3_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EIFR_Bits.INTF3 */
+#define IFX_SCU_EIFR_INTF3_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EIFR_Bits.INTF3 */
+#define IFX_SCU_EIFR_INTF3_OFF (3u)
+
+/** \brief Length for Ifx_SCU_EIFR_Bits.INTF4 */
+#define IFX_SCU_EIFR_INTF4_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EIFR_Bits.INTF4 */
+#define IFX_SCU_EIFR_INTF4_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EIFR_Bits.INTF4 */
+#define IFX_SCU_EIFR_INTF4_OFF (4u)
+
+/** \brief Length for Ifx_SCU_EIFR_Bits.INTF5 */
+#define IFX_SCU_EIFR_INTF5_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EIFR_Bits.INTF5 */
+#define IFX_SCU_EIFR_INTF5_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EIFR_Bits.INTF5 */
+#define IFX_SCU_EIFR_INTF5_OFF (5u)
+
+/** \brief Length for Ifx_SCU_EIFR_Bits.INTF6 */
+#define IFX_SCU_EIFR_INTF6_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EIFR_Bits.INTF6 */
+#define IFX_SCU_EIFR_INTF6_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EIFR_Bits.INTF6 */
+#define IFX_SCU_EIFR_INTF6_OFF (6u)
+
+/** \brief Length for Ifx_SCU_EIFR_Bits.INTF7 */
+#define IFX_SCU_EIFR_INTF7_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EIFR_Bits.INTF7 */
+#define IFX_SCU_EIFR_INTF7_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EIFR_Bits.INTF7 */
+#define IFX_SCU_EIFR_INTF7_OFF (7u)
+
+/** \brief Length for Ifx_SCU_EMSR_Bits.EMSF */
+#define IFX_SCU_EMSR_EMSF_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EMSR_Bits.EMSF */
+#define IFX_SCU_EMSR_EMSF_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EMSR_Bits.EMSF */
+#define IFX_SCU_EMSR_EMSF_OFF (16u)
+
+/** \brief Length for Ifx_SCU_EMSR_Bits.EMSFM */
+#define IFX_SCU_EMSR_EMSFM_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_EMSR_Bits.EMSFM */
+#define IFX_SCU_EMSR_EMSFM_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_EMSR_Bits.EMSFM */
+#define IFX_SCU_EMSR_EMSFM_OFF (24u)
+
+/** \brief Length for Ifx_SCU_EMSR_Bits.ENON */
+#define IFX_SCU_EMSR_ENON_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EMSR_Bits.ENON */
+#define IFX_SCU_EMSR_ENON_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EMSR_Bits.ENON */
+#define IFX_SCU_EMSR_ENON_OFF (2u)
+
+/** \brief Length for Ifx_SCU_EMSR_Bits.MODE */
+#define IFX_SCU_EMSR_MODE_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EMSR_Bits.MODE */
+#define IFX_SCU_EMSR_MODE_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EMSR_Bits.MODE */
+#define IFX_SCU_EMSR_MODE_OFF (1u)
+
+/** \brief Length for Ifx_SCU_EMSR_Bits.POL */
+#define IFX_SCU_EMSR_POL_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EMSR_Bits.POL */
+#define IFX_SCU_EMSR_POL_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EMSR_Bits.POL */
+#define IFX_SCU_EMSR_POL_OFF (0u)
+
+/** \brief Length for Ifx_SCU_EMSR_Bits.PSEL */
+#define IFX_SCU_EMSR_PSEL_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EMSR_Bits.PSEL */
+#define IFX_SCU_EMSR_PSEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EMSR_Bits.PSEL */
+#define IFX_SCU_EMSR_PSEL_OFF (3u)
+
+/** \brief Length for Ifx_SCU_EMSR_Bits.SEMSF */
+#define IFX_SCU_EMSR_SEMSF_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EMSR_Bits.SEMSF */
+#define IFX_SCU_EMSR_SEMSF_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EMSR_Bits.SEMSF */
+#define IFX_SCU_EMSR_SEMSF_OFF (17u)
+
+/** \brief Length for Ifx_SCU_EMSR_Bits.SEMSFM */
+#define IFX_SCU_EMSR_SEMSFM_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_EMSR_Bits.SEMSFM */
+#define IFX_SCU_EMSR_SEMSFM_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_EMSR_Bits.SEMSFM */
+#define IFX_SCU_EMSR_SEMSFM_OFF (26u)
+
+/** \brief Length for Ifx_SCU_ESRCFG_Bits.EDCON */
+#define IFX_SCU_ESRCFG_EDCON_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_ESRCFG_Bits.EDCON */
+#define IFX_SCU_ESRCFG_EDCON_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_ESRCFG_Bits.EDCON */
+#define IFX_SCU_ESRCFG_EDCON_OFF (7u)
+
+/** \brief Length for Ifx_SCU_ESROCFG_Bits.ARC */
+#define IFX_SCU_ESROCFG_ARC_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ESROCFG_Bits.ARC */
+#define IFX_SCU_ESROCFG_ARC_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ESROCFG_Bits.ARC */
+#define IFX_SCU_ESROCFG_ARC_OFF (1u)
+
+/** \brief Length for Ifx_SCU_ESROCFG_Bits.ARI */
+#define IFX_SCU_ESROCFG_ARI_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_ESROCFG_Bits.ARI */
+#define IFX_SCU_ESROCFG_ARI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_ESROCFG_Bits.ARI */
+#define IFX_SCU_ESROCFG_ARI_OFF (0u)
+
+/** \brief Length for Ifx_SCU_EVR13CON_Bits.BPEVR13OFF */
+#define IFX_SCU_EVR13CON_BPEVR13OFF_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVR13CON_Bits.BPEVR13OFF */
+#define IFX_SCU_EVR13CON_BPEVR13OFF_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVR13CON_Bits.BPEVR13OFF */
+#define IFX_SCU_EVR13CON_BPEVR13OFF_OFF (29u)
+
+/** \brief Length for Ifx_SCU_EVR13CON_Bits.EVR13OFF */
+#define IFX_SCU_EVR13CON_EVR13OFF_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVR13CON_Bits.EVR13OFF */
+#define IFX_SCU_EVR13CON_EVR13OFF_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVR13CON_Bits.EVR13OFF */
+#define IFX_SCU_EVR13CON_EVR13OFF_OFF (28u)
+
+/** \brief Length for Ifx_SCU_EVR13CON_Bits.LCK */
+#define IFX_SCU_EVR13CON_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVR13CON_Bits.LCK */
+#define IFX_SCU_EVR13CON_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVR13CON_Bits.LCK */
+#define IFX_SCU_EVR13CON_LCK_OFF (31u)
+
+/** \brief Length for Ifx_SCU_EVR33CON_Bits.BPEVR33OFF */
+#define IFX_SCU_EVR33CON_BPEVR33OFF_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVR33CON_Bits.BPEVR33OFF */
+#define IFX_SCU_EVR33CON_BPEVR33OFF_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVR33CON_Bits.BPEVR33OFF */
+#define IFX_SCU_EVR33CON_BPEVR33OFF_OFF (29u)
+
+/** \brief Length for Ifx_SCU_EVR33CON_Bits.EVR33OFF */
+#define IFX_SCU_EVR33CON_EVR33OFF_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVR33CON_Bits.EVR33OFF */
+#define IFX_SCU_EVR33CON_EVR33OFF_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVR33CON_Bits.EVR33OFF */
+#define IFX_SCU_EVR33CON_EVR33OFF_OFF (28u)
+
+/** \brief Length for Ifx_SCU_EVR33CON_Bits.LCK */
+#define IFX_SCU_EVR33CON_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVR33CON_Bits.LCK */
+#define IFX_SCU_EVR33CON_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVR33CON_Bits.LCK */
+#define IFX_SCU_EVR33CON_LCK_OFF (31u)
+
+/** \brief Length for Ifx_SCU_EVRADCSTAT_Bits.ADC13V */
+#define IFX_SCU_EVRADCSTAT_ADC13V_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRADCSTAT_Bits.ADC13V */
+#define IFX_SCU_EVRADCSTAT_ADC13V_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRADCSTAT_Bits.ADC13V */
+#define IFX_SCU_EVRADCSTAT_ADC13V_OFF (0u)
+
+/** \brief Length for Ifx_SCU_EVRADCSTAT_Bits.ADC33V */
+#define IFX_SCU_EVRADCSTAT_ADC33V_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRADCSTAT_Bits.ADC33V */
+#define IFX_SCU_EVRADCSTAT_ADC33V_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRADCSTAT_Bits.ADC33V */
+#define IFX_SCU_EVRADCSTAT_ADC33V_OFF (8u)
+
+/** \brief Length for Ifx_SCU_EVRADCSTAT_Bits.ADCSWDV */
+#define IFX_SCU_EVRADCSTAT_ADCSWDV_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRADCSTAT_Bits.ADCSWDV */
+#define IFX_SCU_EVRADCSTAT_ADCSWDV_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRADCSTAT_Bits.ADCSWDV */
+#define IFX_SCU_EVRADCSTAT_ADCSWDV_OFF (16u)
+
+/** \brief Length for Ifx_SCU_EVRADCSTAT_Bits.VAL */
+#define IFX_SCU_EVRADCSTAT_VAL_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRADCSTAT_Bits.VAL */
+#define IFX_SCU_EVRADCSTAT_VAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRADCSTAT_Bits.VAL */
+#define IFX_SCU_EVRADCSTAT_VAL_OFF (31u)
+
+/** \brief Length for Ifx_SCU_EVRDVSTAT_Bits.DVS13TRIM */
+#define IFX_SCU_EVRDVSTAT_DVS13TRIM_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRDVSTAT_Bits.DVS13TRIM */
+#define IFX_SCU_EVRDVSTAT_DVS13TRIM_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRDVSTAT_Bits.DVS13TRIM */
+#define IFX_SCU_EVRDVSTAT_DVS13TRIM_OFF (0u)
+
+/** \brief Length for Ifx_SCU_EVRDVSTAT_Bits.DVS33TRIM */
+#define IFX_SCU_EVRDVSTAT_DVS33TRIM_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRDVSTAT_Bits.DVS33TRIM */
+#define IFX_SCU_EVRDVSTAT_DVS33TRIM_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRDVSTAT_Bits.DVS33TRIM */
+#define IFX_SCU_EVRDVSTAT_DVS33TRIM_OFF (16u)
+
+/** \brief Length for Ifx_SCU_EVRDVSTAT_Bits.VAL */
+#define IFX_SCU_EVRDVSTAT_VAL_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRDVSTAT_Bits.VAL */
+#define IFX_SCU_EVRDVSTAT_VAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRDVSTAT_Bits.VAL */
+#define IFX_SCU_EVRDVSTAT_VAL_OFF (31u)
+
+/** \brief Length for Ifx_SCU_EVRMONCTRL_Bits.EVR13OVMOD */
+#define IFX_SCU_EVRMONCTRL_EVR13OVMOD_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_EVRMONCTRL_Bits.EVR13OVMOD */
+#define IFX_SCU_EVRMONCTRL_EVR13OVMOD_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_EVRMONCTRL_Bits.EVR13OVMOD */
+#define IFX_SCU_EVRMONCTRL_EVR13OVMOD_OFF (0u)
+
+/** \brief Length for Ifx_SCU_EVRMONCTRL_Bits.EVR13UVMOD */
+#define IFX_SCU_EVRMONCTRL_EVR13UVMOD_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_EVRMONCTRL_Bits.EVR13UVMOD */
+#define IFX_SCU_EVRMONCTRL_EVR13UVMOD_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_EVRMONCTRL_Bits.EVR13UVMOD */
+#define IFX_SCU_EVRMONCTRL_EVR13UVMOD_OFF (4u)
+
+/** \brief Length for Ifx_SCU_EVRMONCTRL_Bits.EVR33OVMOD */
+#define IFX_SCU_EVRMONCTRL_EVR33OVMOD_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_EVRMONCTRL_Bits.EVR33OVMOD */
+#define IFX_SCU_EVRMONCTRL_EVR33OVMOD_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_EVRMONCTRL_Bits.EVR33OVMOD */
+#define IFX_SCU_EVRMONCTRL_EVR33OVMOD_OFF (8u)
+
+/** \brief Length for Ifx_SCU_EVRMONCTRL_Bits.EVR33UVMOD */
+#define IFX_SCU_EVRMONCTRL_EVR33UVMOD_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_EVRMONCTRL_Bits.EVR33UVMOD */
+#define IFX_SCU_EVRMONCTRL_EVR33UVMOD_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_EVRMONCTRL_Bits.EVR33UVMOD */
+#define IFX_SCU_EVRMONCTRL_EVR33UVMOD_OFF (12u)
+
+/** \brief Length for Ifx_SCU_EVRMONCTRL_Bits.SWDOVMOD */
+#define IFX_SCU_EVRMONCTRL_SWDOVMOD_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_EVRMONCTRL_Bits.SWDOVMOD */
+#define IFX_SCU_EVRMONCTRL_SWDOVMOD_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_EVRMONCTRL_Bits.SWDOVMOD */
+#define IFX_SCU_EVRMONCTRL_SWDOVMOD_OFF (16u)
+
+/** \brief Length for Ifx_SCU_EVRMONCTRL_Bits.SWDUVMOD */
+#define IFX_SCU_EVRMONCTRL_SWDUVMOD_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_EVRMONCTRL_Bits.SWDUVMOD */
+#define IFX_SCU_EVRMONCTRL_SWDUVMOD_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_EVRMONCTRL_Bits.SWDUVMOD */
+#define IFX_SCU_EVRMONCTRL_SWDUVMOD_OFF (20u)
+
+/** \brief Length for Ifx_SCU_EVROSCCTRL_Bits.HPBGCLKEN */
+#define IFX_SCU_EVROSCCTRL_HPBGCLKEN_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVROSCCTRL_Bits.HPBGCLKEN */
+#define IFX_SCU_EVROSCCTRL_HPBGCLKEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVROSCCTRL_Bits.HPBGCLKEN */
+#define IFX_SCU_EVROSCCTRL_HPBGCLKEN_OFF (27u)
+
+/** \brief Length for Ifx_SCU_EVROSCCTRL_Bits.HPBGTRIM */
+#define IFX_SCU_EVROSCCTRL_HPBGTRIM_LEN (7u)
+
+/** \brief Mask for Ifx_SCU_EVROSCCTRL_Bits.HPBGTRIM */
+#define IFX_SCU_EVROSCCTRL_HPBGTRIM_MSK (0x7fu)
+
+/** \brief Offset for Ifx_SCU_EVROSCCTRL_Bits.HPBGTRIM */
+#define IFX_SCU_EVROSCCTRL_HPBGTRIM_OFF (20u)
+
+/** \brief Length for Ifx_SCU_EVROSCCTRL_Bits.LCK */
+#define IFX_SCU_EVROSCCTRL_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVROSCCTRL_Bits.LCK */
+#define IFX_SCU_EVROSCCTRL_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVROSCCTRL_Bits.LCK */
+#define IFX_SCU_EVROSCCTRL_LCK_OFF (31u)
+
+/** \brief Length for Ifx_SCU_EVROSCCTRL_Bits.OSC3V3 */
+#define IFX_SCU_EVROSCCTRL_OSC3V3_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVROSCCTRL_Bits.OSC3V3 */
+#define IFX_SCU_EVROSCCTRL_OSC3V3_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVROSCCTRL_Bits.OSC3V3 */
+#define IFX_SCU_EVROSCCTRL_OSC3V3_OFF (28u)
+
+/** \brief Length for Ifx_SCU_EVROSCCTRL_Bits.OSCANASEL */
+#define IFX_SCU_EVROSCCTRL_OSCANASEL_LEN (4u)
+
+/** \brief Mask for Ifx_SCU_EVROSCCTRL_Bits.OSCANASEL */
+#define IFX_SCU_EVROSCCTRL_OSCANASEL_MSK (0xfu)
+
+/** \brief Offset for Ifx_SCU_EVROSCCTRL_Bits.OSCANASEL */
+#define IFX_SCU_EVROSCCTRL_OSCANASEL_OFF (16u)
+
+/** \brief Length for Ifx_SCU_EVROSCCTRL_Bits.OSCPTAT */
+#define IFX_SCU_EVROSCCTRL_OSCPTAT_LEN (6u)
+
+/** \brief Mask for Ifx_SCU_EVROSCCTRL_Bits.OSCPTAT */
+#define IFX_SCU_EVROSCCTRL_OSCPTAT_MSK (0x3fu)
+
+/** \brief Offset for Ifx_SCU_EVROSCCTRL_Bits.OSCPTAT */
+#define IFX_SCU_EVROSCCTRL_OSCPTAT_OFF (10u)
+
+/** \brief Length for Ifx_SCU_EVROSCCTRL_Bits.OSCTRIM */
+#define IFX_SCU_EVROSCCTRL_OSCTRIM_LEN (10u)
+
+/** \brief Mask for Ifx_SCU_EVROSCCTRL_Bits.OSCTRIM */
+#define IFX_SCU_EVROSCCTRL_OSCTRIM_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_SCU_EVROSCCTRL_Bits.OSCTRIM */
+#define IFX_SCU_EVROSCCTRL_OSCTRIM_OFF (0u)
+
+/** \brief Length for Ifx_SCU_EVROVMON_Bits.EVR13OVVAL */
+#define IFX_SCU_EVROVMON_EVR13OVVAL_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVROVMON_Bits.EVR13OVVAL */
+#define IFX_SCU_EVROVMON_EVR13OVVAL_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVROVMON_Bits.EVR13OVVAL */
+#define IFX_SCU_EVROVMON_EVR13OVVAL_OFF (0u)
+
+/** \brief Length for Ifx_SCU_EVROVMON_Bits.EVR33OVVAL */
+#define IFX_SCU_EVROVMON_EVR33OVVAL_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVROVMON_Bits.EVR33OVVAL */
+#define IFX_SCU_EVROVMON_EVR33OVVAL_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVROVMON_Bits.EVR33OVVAL */
+#define IFX_SCU_EVROVMON_EVR33OVVAL_OFF (8u)
+
+/** \brief Length for Ifx_SCU_EVROVMON_Bits.LCK */
+#define IFX_SCU_EVROVMON_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVROVMON_Bits.LCK */
+#define IFX_SCU_EVROVMON_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVROVMON_Bits.LCK */
+#define IFX_SCU_EVROVMON_LCK_OFF (31u)
+
+/** \brief Length for Ifx_SCU_EVROVMON_Bits.SWDOVVAL */
+#define IFX_SCU_EVROVMON_SWDOVVAL_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVROVMON_Bits.SWDOVVAL */
+#define IFX_SCU_EVROVMON_SWDOVVAL_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVROVMON_Bits.SWDOVVAL */
+#define IFX_SCU_EVROVMON_SWDOVVAL_OFF (16u)
+
+/** \brief Length for Ifx_SCU_EVRRSTCON_Bits.BPRST13OFF */
+#define IFX_SCU_EVRRSTCON_BPRST13OFF_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRRSTCON_Bits.BPRST13OFF */
+#define IFX_SCU_EVRRSTCON_BPRST13OFF_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRRSTCON_Bits.BPRST13OFF */
+#define IFX_SCU_EVRRSTCON_BPRST13OFF_OFF (25u)
+
+/** \brief Length for Ifx_SCU_EVRRSTCON_Bits.BPRST33OFF */
+#define IFX_SCU_EVRRSTCON_BPRST33OFF_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRRSTCON_Bits.BPRST33OFF */
+#define IFX_SCU_EVRRSTCON_BPRST33OFF_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRRSTCON_Bits.BPRST33OFF */
+#define IFX_SCU_EVRRSTCON_BPRST33OFF_OFF (27u)
+
+/** \brief Length for Ifx_SCU_EVRRSTCON_Bits.BPRSTSWDOFF */
+#define IFX_SCU_EVRRSTCON_BPRSTSWDOFF_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRRSTCON_Bits.BPRSTSWDOFF */
+#define IFX_SCU_EVRRSTCON_BPRSTSWDOFF_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRRSTCON_Bits.BPRSTSWDOFF */
+#define IFX_SCU_EVRRSTCON_BPRSTSWDOFF_OFF (29u)
+
+/** \brief Length for Ifx_SCU_EVRRSTCON_Bits.LCK */
+#define IFX_SCU_EVRRSTCON_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRRSTCON_Bits.LCK */
+#define IFX_SCU_EVRRSTCON_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRRSTCON_Bits.LCK */
+#define IFX_SCU_EVRRSTCON_LCK_OFF (31u)
+
+/** \brief Length for Ifx_SCU_EVRRSTCON_Bits.RST13OFF */
+#define IFX_SCU_EVRRSTCON_RST13OFF_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRRSTCON_Bits.RST13OFF */
+#define IFX_SCU_EVRRSTCON_RST13OFF_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRRSTCON_Bits.RST13OFF */
+#define IFX_SCU_EVRRSTCON_RST13OFF_OFF (24u)
+
+/** \brief Length for Ifx_SCU_EVRRSTCON_Bits.RST13TRIM */
+#define IFX_SCU_EVRRSTCON_RST13TRIM_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRRSTCON_Bits.RST13TRIM */
+#define IFX_SCU_EVRRSTCON_RST13TRIM_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRRSTCON_Bits.RST13TRIM */
+#define IFX_SCU_EVRRSTCON_RST13TRIM_OFF (0u)
+
+/** \brief Length for Ifx_SCU_EVRRSTCON_Bits.RST33OFF */
+#define IFX_SCU_EVRRSTCON_RST33OFF_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRRSTCON_Bits.RST33OFF */
+#define IFX_SCU_EVRRSTCON_RST33OFF_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRRSTCON_Bits.RST33OFF */
+#define IFX_SCU_EVRRSTCON_RST33OFF_OFF (26u)
+
+/** \brief Length for Ifx_SCU_EVRRSTCON_Bits.RSTSWDOFF */
+#define IFX_SCU_EVRRSTCON_RSTSWDOFF_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRRSTCON_Bits.RSTSWDOFF */
+#define IFX_SCU_EVRRSTCON_RSTSWDOFF_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRRSTCON_Bits.RSTSWDOFF */
+#define IFX_SCU_EVRRSTCON_RSTSWDOFF_OFF (28u)
+
+/** \brief Length for Ifx_SCU_EVRSDCOEFF1_Bits.LCK */
+#define IFX_SCU_EVRSDCOEFF1_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCOEFF1_Bits.LCK */
+#define IFX_SCU_EVRSDCOEFF1_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRSDCOEFF1_Bits.LCK */
+#define IFX_SCU_EVRSDCOEFF1_LCK_OFF (31u)
+
+/** \brief Length for Ifx_SCU_EVRSDCOEFF1_Bits.SD5D */
+#define IFX_SCU_EVRSDCOEFF1_SD5D_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCOEFF1_Bits.SD5D */
+#define IFX_SCU_EVRSDCOEFF1_SD5D_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRSDCOEFF1_Bits.SD5D */
+#define IFX_SCU_EVRSDCOEFF1_SD5D_OFF (16u)
+
+/** \brief Length for Ifx_SCU_EVRSDCOEFF1_Bits.SD5I */
+#define IFX_SCU_EVRSDCOEFF1_SD5I_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCOEFF1_Bits.SD5I */
+#define IFX_SCU_EVRSDCOEFF1_SD5I_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRSDCOEFF1_Bits.SD5I */
+#define IFX_SCU_EVRSDCOEFF1_SD5I_OFF (8u)
+
+/** \brief Length for Ifx_SCU_EVRSDCOEFF1_Bits.SD5P */
+#define IFX_SCU_EVRSDCOEFF1_SD5P_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCOEFF1_Bits.SD5P */
+#define IFX_SCU_EVRSDCOEFF1_SD5P_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRSDCOEFF1_Bits.SD5P */
+#define IFX_SCU_EVRSDCOEFF1_SD5P_OFF (0u)
+
+/** \brief Length for Ifx_SCU_EVRSDCOEFF2_Bits.LCK */
+#define IFX_SCU_EVRSDCOEFF2_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCOEFF2_Bits.LCK */
+#define IFX_SCU_EVRSDCOEFF2_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRSDCOEFF2_Bits.LCK */
+#define IFX_SCU_EVRSDCOEFF2_LCK_OFF (31u)
+
+/** \brief Length for Ifx_SCU_EVRSDCOEFF2_Bits.SD33D */
+#define IFX_SCU_EVRSDCOEFF2_SD33D_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCOEFF2_Bits.SD33D */
+#define IFX_SCU_EVRSDCOEFF2_SD33D_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRSDCOEFF2_Bits.SD33D */
+#define IFX_SCU_EVRSDCOEFF2_SD33D_OFF (16u)
+
+/** \brief Length for Ifx_SCU_EVRSDCOEFF2_Bits.SD33I */
+#define IFX_SCU_EVRSDCOEFF2_SD33I_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCOEFF2_Bits.SD33I */
+#define IFX_SCU_EVRSDCOEFF2_SD33I_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRSDCOEFF2_Bits.SD33I */
+#define IFX_SCU_EVRSDCOEFF2_SD33I_OFF (8u)
+
+/** \brief Length for Ifx_SCU_EVRSDCOEFF2_Bits.SD33P */
+#define IFX_SCU_EVRSDCOEFF2_SD33P_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCOEFF2_Bits.SD33P */
+#define IFX_SCU_EVRSDCOEFF2_SD33P_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRSDCOEFF2_Bits.SD33P */
+#define IFX_SCU_EVRSDCOEFF2_SD33P_OFF (0u)
+
+/** \brief Length for Ifx_SCU_EVRSDCOEFF3_Bits.CT5REG0 */
+#define IFX_SCU_EVRSDCOEFF3_CT5REG0_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCOEFF3_Bits.CT5REG0 */
+#define IFX_SCU_EVRSDCOEFF3_CT5REG0_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRSDCOEFF3_Bits.CT5REG0 */
+#define IFX_SCU_EVRSDCOEFF3_CT5REG0_OFF (0u)
+
+/** \brief Length for Ifx_SCU_EVRSDCOEFF3_Bits.CT5REG1 */
+#define IFX_SCU_EVRSDCOEFF3_CT5REG1_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCOEFF3_Bits.CT5REG1 */
+#define IFX_SCU_EVRSDCOEFF3_CT5REG1_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRSDCOEFF3_Bits.CT5REG1 */
+#define IFX_SCU_EVRSDCOEFF3_CT5REG1_OFF (8u)
+
+/** \brief Length for Ifx_SCU_EVRSDCOEFF3_Bits.CT5REG2 */
+#define IFX_SCU_EVRSDCOEFF3_CT5REG2_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCOEFF3_Bits.CT5REG2 */
+#define IFX_SCU_EVRSDCOEFF3_CT5REG2_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRSDCOEFF3_Bits.CT5REG2 */
+#define IFX_SCU_EVRSDCOEFF3_CT5REG2_OFF (16u)
+
+/** \brief Length for Ifx_SCU_EVRSDCOEFF3_Bits.LCK */
+#define IFX_SCU_EVRSDCOEFF3_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCOEFF3_Bits.LCK */
+#define IFX_SCU_EVRSDCOEFF3_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRSDCOEFF3_Bits.LCK */
+#define IFX_SCU_EVRSDCOEFF3_LCK_OFF (31u)
+
+/** \brief Length for Ifx_SCU_EVRSDCOEFF4_Bits.CT5REG3 */
+#define IFX_SCU_EVRSDCOEFF4_CT5REG3_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCOEFF4_Bits.CT5REG3 */
+#define IFX_SCU_EVRSDCOEFF4_CT5REG3_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRSDCOEFF4_Bits.CT5REG3 */
+#define IFX_SCU_EVRSDCOEFF4_CT5REG3_OFF (0u)
+
+/** \brief Length for Ifx_SCU_EVRSDCOEFF4_Bits.CT5REG4 */
+#define IFX_SCU_EVRSDCOEFF4_CT5REG4_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCOEFF4_Bits.CT5REG4 */
+#define IFX_SCU_EVRSDCOEFF4_CT5REG4_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRSDCOEFF4_Bits.CT5REG4 */
+#define IFX_SCU_EVRSDCOEFF4_CT5REG4_OFF (8u)
+
+/** \brief Length for Ifx_SCU_EVRSDCOEFF4_Bits.LCK */
+#define IFX_SCU_EVRSDCOEFF4_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCOEFF4_Bits.LCK */
+#define IFX_SCU_EVRSDCOEFF4_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRSDCOEFF4_Bits.LCK */
+#define IFX_SCU_EVRSDCOEFF4_LCK_OFF (31u)
+
+/** \brief Length for Ifx_SCU_EVRSDCOEFF5_Bits.CT33REG0 */
+#define IFX_SCU_EVRSDCOEFF5_CT33REG0_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCOEFF5_Bits.CT33REG0 */
+#define IFX_SCU_EVRSDCOEFF5_CT33REG0_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRSDCOEFF5_Bits.CT33REG0 */
+#define IFX_SCU_EVRSDCOEFF5_CT33REG0_OFF (0u)
+
+/** \brief Length for Ifx_SCU_EVRSDCOEFF5_Bits.CT33REG1 */
+#define IFX_SCU_EVRSDCOEFF5_CT33REG1_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCOEFF5_Bits.CT33REG1 */
+#define IFX_SCU_EVRSDCOEFF5_CT33REG1_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRSDCOEFF5_Bits.CT33REG1 */
+#define IFX_SCU_EVRSDCOEFF5_CT33REG1_OFF (8u)
+
+/** \brief Length for Ifx_SCU_EVRSDCOEFF5_Bits.CT33REG2 */
+#define IFX_SCU_EVRSDCOEFF5_CT33REG2_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCOEFF5_Bits.CT33REG2 */
+#define IFX_SCU_EVRSDCOEFF5_CT33REG2_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRSDCOEFF5_Bits.CT33REG2 */
+#define IFX_SCU_EVRSDCOEFF5_CT33REG2_OFF (16u)
+
+/** \brief Length for Ifx_SCU_EVRSDCOEFF5_Bits.LCK */
+#define IFX_SCU_EVRSDCOEFF5_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCOEFF5_Bits.LCK */
+#define IFX_SCU_EVRSDCOEFF5_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRSDCOEFF5_Bits.LCK */
+#define IFX_SCU_EVRSDCOEFF5_LCK_OFF (31u)
+
+/** \brief Length for Ifx_SCU_EVRSDCOEFF6_Bits.CT33REG3 */
+#define IFX_SCU_EVRSDCOEFF6_CT33REG3_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCOEFF6_Bits.CT33REG3 */
+#define IFX_SCU_EVRSDCOEFF6_CT33REG3_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRSDCOEFF6_Bits.CT33REG3 */
+#define IFX_SCU_EVRSDCOEFF6_CT33REG3_OFF (0u)
+
+/** \brief Length for Ifx_SCU_EVRSDCOEFF6_Bits.CT33REG4 */
+#define IFX_SCU_EVRSDCOEFF6_CT33REG4_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCOEFF6_Bits.CT33REG4 */
+#define IFX_SCU_EVRSDCOEFF6_CT33REG4_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRSDCOEFF6_Bits.CT33REG4 */
+#define IFX_SCU_EVRSDCOEFF6_CT33REG4_OFF (8u)
+
+/** \brief Length for Ifx_SCU_EVRSDCOEFF6_Bits.LCK */
+#define IFX_SCU_EVRSDCOEFF6_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCOEFF6_Bits.LCK */
+#define IFX_SCU_EVRSDCOEFF6_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRSDCOEFF6_Bits.LCK */
+#define IFX_SCU_EVRSDCOEFF6_LCK_OFF (31u)
+
+/** \brief Length for Ifx_SCU_EVRSDCTRL1_Bits.LCK */
+#define IFX_SCU_EVRSDCTRL1_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCTRL1_Bits.LCK */
+#define IFX_SCU_EVRSDCTRL1_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRSDCTRL1_Bits.LCK */
+#define IFX_SCU_EVRSDCTRL1_LCK_OFF (31u)
+
+/** \brief Length for Ifx_SCU_EVRSDCTRL1_Bits.SDFREQ */
+#define IFX_SCU_EVRSDCTRL1_SDFREQ_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCTRL1_Bits.SDFREQ */
+#define IFX_SCU_EVRSDCTRL1_SDFREQ_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRSDCTRL1_Bits.SDFREQ */
+#define IFX_SCU_EVRSDCTRL1_SDFREQ_OFF (16u)
+
+/** \brief Length for Ifx_SCU_EVRSDCTRL1_Bits.SDFREQSPRD */
+#define IFX_SCU_EVRSDCTRL1_SDFREQSPRD_LEN (16u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCTRL1_Bits.SDFREQSPRD */
+#define IFX_SCU_EVRSDCTRL1_SDFREQSPRD_MSK (0xffffu)
+
+/** \brief Offset for Ifx_SCU_EVRSDCTRL1_Bits.SDFREQSPRD */
+#define IFX_SCU_EVRSDCTRL1_SDFREQSPRD_OFF (0u)
+
+/** \brief Length for Ifx_SCU_EVRSDCTRL1_Bits.SDSAMPLE */
+#define IFX_SCU_EVRSDCTRL1_SDSAMPLE_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCTRL1_Bits.SDSAMPLE */
+#define IFX_SCU_EVRSDCTRL1_SDSAMPLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRSDCTRL1_Bits.SDSAMPLE */
+#define IFX_SCU_EVRSDCTRL1_SDSAMPLE_OFF (30u)
+
+/** \brief Length for Ifx_SCU_EVRSDCTRL1_Bits.SDSTEP */
+#define IFX_SCU_EVRSDCTRL1_SDSTEP_LEN (4u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCTRL1_Bits.SDSTEP */
+#define IFX_SCU_EVRSDCTRL1_SDSTEP_MSK (0xfu)
+
+/** \brief Offset for Ifx_SCU_EVRSDCTRL1_Bits.SDSTEP */
+#define IFX_SCU_EVRSDCTRL1_SDSTEP_OFF (24u)
+
+/** \brief Length for Ifx_SCU_EVRSDCTRL2_Bits.DRVN */
+#define IFX_SCU_EVRSDCTRL2_DRVN_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCTRL2_Bits.DRVN */
+#define IFX_SCU_EVRSDCTRL2_DRVN_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRSDCTRL2_Bits.DRVN */
+#define IFX_SCU_EVRSDCTRL2_DRVN_OFF (16u)
+
+/** \brief Length for Ifx_SCU_EVRSDCTRL2_Bits.DRVP */
+#define IFX_SCU_EVRSDCTRL2_DRVP_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCTRL2_Bits.DRVP */
+#define IFX_SCU_EVRSDCTRL2_DRVP_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRSDCTRL2_Bits.DRVP */
+#define IFX_SCU_EVRSDCTRL2_DRVP_OFF (0u)
+
+/** \brief Length for Ifx_SCU_EVRSDCTRL2_Bits.LCK */
+#define IFX_SCU_EVRSDCTRL2_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCTRL2_Bits.LCK */
+#define IFX_SCU_EVRSDCTRL2_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRSDCTRL2_Bits.LCK */
+#define IFX_SCU_EVRSDCTRL2_LCK_OFF (31u)
+
+/** \brief Length for Ifx_SCU_EVRSDCTRL2_Bits.SDLUT */
+#define IFX_SCU_EVRSDCTRL2_SDLUT_LEN (6u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCTRL2_Bits.SDLUT */
+#define IFX_SCU_EVRSDCTRL2_SDLUT_MSK (0x3fu)
+
+/** \brief Offset for Ifx_SCU_EVRSDCTRL2_Bits.SDLUT */
+#define IFX_SCU_EVRSDCTRL2_SDLUT_OFF (24u)
+
+/** \brief Length for Ifx_SCU_EVRSDCTRL2_Bits.SDMINMAXDC */
+#define IFX_SCU_EVRSDCTRL2_SDMINMAXDC_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCTRL2_Bits.SDMINMAXDC */
+#define IFX_SCU_EVRSDCTRL2_SDMINMAXDC_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRSDCTRL2_Bits.SDMINMAXDC */
+#define IFX_SCU_EVRSDCTRL2_SDMINMAXDC_OFF (8u)
+
+/** \brief Length for Ifx_SCU_EVRSDCTRL3_Bits.LCK */
+#define IFX_SCU_EVRSDCTRL3_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCTRL3_Bits.LCK */
+#define IFX_SCU_EVRSDCTRL3_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRSDCTRL3_Bits.LCK */
+#define IFX_SCU_EVRSDCTRL3_LCK_OFF (31u)
+
+/** \brief Length for Ifx_SCU_EVRSDCTRL3_Bits.SDPID */
+#define IFX_SCU_EVRSDCTRL3_SDPID_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCTRL3_Bits.SDPID */
+#define IFX_SCU_EVRSDCTRL3_SDPID_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRSDCTRL3_Bits.SDPID */
+#define IFX_SCU_EVRSDCTRL3_SDPID_OFF (8u)
+
+/** \brief Length for Ifx_SCU_EVRSDCTRL3_Bits.SDPWMPRE */
+#define IFX_SCU_EVRSDCTRL3_SDPWMPRE_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCTRL3_Bits.SDPWMPRE */
+#define IFX_SCU_EVRSDCTRL3_SDPWMPRE_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRSDCTRL3_Bits.SDPWMPRE */
+#define IFX_SCU_EVRSDCTRL3_SDPWMPRE_OFF (0u)
+
+/** \brief Length for Ifx_SCU_EVRSDCTRL3_Bits.SDVOKLVL */
+#define IFX_SCU_EVRSDCTRL3_SDVOKLVL_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCTRL3_Bits.SDVOKLVL */
+#define IFX_SCU_EVRSDCTRL3_SDVOKLVL_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRSDCTRL3_Bits.SDVOKLVL */
+#define IFX_SCU_EVRSDCTRL3_SDVOKLVL_OFF (16u)
+
+/** \brief Length for Ifx_SCU_EVRSDCTRL4_Bits.LCK */
+#define IFX_SCU_EVRSDCTRL4_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCTRL4_Bits.LCK */
+#define IFX_SCU_EVRSDCTRL4_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRSDCTRL4_Bits.LCK */
+#define IFX_SCU_EVRSDCTRL4_LCK_OFF (31u)
+
+/** \brief Length for Ifx_SCU_EVRSDCTRL4_Bits.SYNCDIV */
+#define IFX_SCU_EVRSDCTRL4_SYNCDIV_LEN (3u)
+
+/** \brief Mask for Ifx_SCU_EVRSDCTRL4_Bits.SYNCDIV */
+#define IFX_SCU_EVRSDCTRL4_SYNCDIV_MSK (0x7u)
+
+/** \brief Offset for Ifx_SCU_EVRSDCTRL4_Bits.SYNCDIV */
+#define IFX_SCU_EVRSDCTRL4_SYNCDIV_OFF (8u)
+
+/** \brief Length for Ifx_SCU_EVRSTAT_Bits.BGPROK */
+#define IFX_SCU_EVRSTAT_BGPROK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRSTAT_Bits.BGPROK */
+#define IFX_SCU_EVRSTAT_BGPROK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRSTAT_Bits.BGPROK */
+#define IFX_SCU_EVRSTAT_BGPROK_OFF (10u)
+
+/** \brief Length for Ifx_SCU_EVRSTAT_Bits.EVR13 */
+#define IFX_SCU_EVRSTAT_EVR13_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRSTAT_Bits.EVR13 */
+#define IFX_SCU_EVRSTAT_EVR13_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRSTAT_Bits.EVR13 */
+#define IFX_SCU_EVRSTAT_EVR13_OFF (0u)
+
+/** \brief Length for Ifx_SCU_EVRSTAT_Bits.EVR33 */
+#define IFX_SCU_EVRSTAT_EVR33_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRSTAT_Bits.EVR33 */
+#define IFX_SCU_EVRSTAT_EVR33_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRSTAT_Bits.EVR33 */
+#define IFX_SCU_EVRSTAT_EVR33_OFF (2u)
+
+/** \brief Length for Ifx_SCU_EVRSTAT_Bits.EXTPASS13 */
+#define IFX_SCU_EVRSTAT_EXTPASS13_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRSTAT_Bits.EXTPASS13 */
+#define IFX_SCU_EVRSTAT_EXTPASS13_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRSTAT_Bits.EXTPASS13 */
+#define IFX_SCU_EVRSTAT_EXTPASS13_OFF (8u)
+
+/** \brief Length for Ifx_SCU_EVRSTAT_Bits.EXTPASS33 */
+#define IFX_SCU_EVRSTAT_EXTPASS33_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRSTAT_Bits.EXTPASS33 */
+#define IFX_SCU_EVRSTAT_EXTPASS33_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRSTAT_Bits.EXTPASS33 */
+#define IFX_SCU_EVRSTAT_EXTPASS33_OFF (9u)
+
+/** \brief Length for Ifx_SCU_EVRSTAT_Bits.OV13 */
+#define IFX_SCU_EVRSTAT_OV13_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRSTAT_Bits.OV13 */
+#define IFX_SCU_EVRSTAT_OV13_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRSTAT_Bits.OV13 */
+#define IFX_SCU_EVRSTAT_OV13_OFF (1u)
+
+/** \brief Length for Ifx_SCU_EVRSTAT_Bits.OV33 */
+#define IFX_SCU_EVRSTAT_OV33_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRSTAT_Bits.OV33 */
+#define IFX_SCU_EVRSTAT_OV33_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRSTAT_Bits.OV33 */
+#define IFX_SCU_EVRSTAT_OV33_OFF (3u)
+
+/** \brief Length for Ifx_SCU_EVRSTAT_Bits.OVSWD */
+#define IFX_SCU_EVRSTAT_OVSWD_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRSTAT_Bits.OVSWD */
+#define IFX_SCU_EVRSTAT_OVSWD_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRSTAT_Bits.OVSWD */
+#define IFX_SCU_EVRSTAT_OVSWD_OFF (4u)
+
+/** \brief Length for Ifx_SCU_EVRSTAT_Bits.UV13 */
+#define IFX_SCU_EVRSTAT_UV13_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRSTAT_Bits.UV13 */
+#define IFX_SCU_EVRSTAT_UV13_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRSTAT_Bits.UV13 */
+#define IFX_SCU_EVRSTAT_UV13_OFF (5u)
+
+/** \brief Length for Ifx_SCU_EVRSTAT_Bits.UV33 */
+#define IFX_SCU_EVRSTAT_UV33_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRSTAT_Bits.UV33 */
+#define IFX_SCU_EVRSTAT_UV33_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRSTAT_Bits.UV33 */
+#define IFX_SCU_EVRSTAT_UV33_OFF (6u)
+
+/** \brief Length for Ifx_SCU_EVRSTAT_Bits.UVSWD */
+#define IFX_SCU_EVRSTAT_UVSWD_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRSTAT_Bits.UVSWD */
+#define IFX_SCU_EVRSTAT_UVSWD_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRSTAT_Bits.UVSWD */
+#define IFX_SCU_EVRSTAT_UVSWD_OFF (7u)
+
+/** \brief Length for Ifx_SCU_EVRTRIM_Bits.EVR13TRIM */
+#define IFX_SCU_EVRTRIM_EVR13TRIM_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRTRIM_Bits.EVR13TRIM */
+#define IFX_SCU_EVRTRIM_EVR13TRIM_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRTRIM_Bits.EVR13TRIM */
+#define IFX_SCU_EVRTRIM_EVR13TRIM_OFF (0u)
+
+/** \brief Length for Ifx_SCU_EVRTRIM_Bits.LCK */
+#define IFX_SCU_EVRTRIM_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRTRIM_Bits.LCK */
+#define IFX_SCU_EVRTRIM_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRTRIM_Bits.LCK */
+#define IFX_SCU_EVRTRIM_LCK_OFF (31u)
+
+/** \brief Length for Ifx_SCU_EVRTRIM_Bits.SDVOUTSEL */
+#define IFX_SCU_EVRTRIM_SDVOUTSEL_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRTRIM_Bits.SDVOUTSEL */
+#define IFX_SCU_EVRTRIM_SDVOUTSEL_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRTRIM_Bits.SDVOUTSEL */
+#define IFX_SCU_EVRTRIM_SDVOUTSEL_OFF (8u)
+
+/** \brief Length for Ifx_SCU_EVRUVMON_Bits.EVR13UVVAL */
+#define IFX_SCU_EVRUVMON_EVR13UVVAL_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRUVMON_Bits.EVR13UVVAL */
+#define IFX_SCU_EVRUVMON_EVR13UVVAL_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRUVMON_Bits.EVR13UVVAL */
+#define IFX_SCU_EVRUVMON_EVR13UVVAL_OFF (0u)
+
+/** \brief Length for Ifx_SCU_EVRUVMON_Bits.EVR33UVVAL */
+#define IFX_SCU_EVRUVMON_EVR33UVVAL_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRUVMON_Bits.EVR33UVVAL */
+#define IFX_SCU_EVRUVMON_EVR33UVVAL_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRUVMON_Bits.EVR33UVVAL */
+#define IFX_SCU_EVRUVMON_EVR33UVVAL_OFF (8u)
+
+/** \brief Length for Ifx_SCU_EVRUVMON_Bits.LCK */
+#define IFX_SCU_EVRUVMON_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EVRUVMON_Bits.LCK */
+#define IFX_SCU_EVRUVMON_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EVRUVMON_Bits.LCK */
+#define IFX_SCU_EVRUVMON_LCK_OFF (31u)
+
+/** \brief Length for Ifx_SCU_EVRUVMON_Bits.SWDUVVAL */
+#define IFX_SCU_EVRUVMON_SWDUVVAL_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EVRUVMON_Bits.SWDUVVAL */
+#define IFX_SCU_EVRUVMON_SWDUVVAL_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EVRUVMON_Bits.SWDUVVAL */
+#define IFX_SCU_EVRUVMON_SWDUVVAL_OFF (16u)
+
+/** \brief Length for Ifx_SCU_EXTCON_Bits.DIV1 */
+#define IFX_SCU_EXTCON_DIV1_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_EXTCON_Bits.DIV1 */
+#define IFX_SCU_EXTCON_DIV1_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_EXTCON_Bits.DIV1 */
+#define IFX_SCU_EXTCON_DIV1_OFF (24u)
+
+/** \brief Length for Ifx_SCU_EXTCON_Bits.EN0 */
+#define IFX_SCU_EXTCON_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EXTCON_Bits.EN0 */
+#define IFX_SCU_EXTCON_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EXTCON_Bits.EN0 */
+#define IFX_SCU_EXTCON_EN0_OFF (0u)
+
+/** \brief Length for Ifx_SCU_EXTCON_Bits.EN1 */
+#define IFX_SCU_EXTCON_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EXTCON_Bits.EN1 */
+#define IFX_SCU_EXTCON_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EXTCON_Bits.EN1 */
+#define IFX_SCU_EXTCON_EN1_OFF (16u)
+
+/** \brief Length for Ifx_SCU_EXTCON_Bits.NSEL */
+#define IFX_SCU_EXTCON_NSEL_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_EXTCON_Bits.NSEL */
+#define IFX_SCU_EXTCON_NSEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_EXTCON_Bits.NSEL */
+#define IFX_SCU_EXTCON_NSEL_OFF (17u)
+
+/** \brief Length for Ifx_SCU_EXTCON_Bits.SEL0 */
+#define IFX_SCU_EXTCON_SEL0_LEN (4u)
+
+/** \brief Mask for Ifx_SCU_EXTCON_Bits.SEL0 */
+#define IFX_SCU_EXTCON_SEL0_MSK (0xfu)
+
+/** \brief Offset for Ifx_SCU_EXTCON_Bits.SEL0 */
+#define IFX_SCU_EXTCON_SEL0_OFF (2u)
+
+/** \brief Length for Ifx_SCU_EXTCON_Bits.SEL1 */
+#define IFX_SCU_EXTCON_SEL1_LEN (4u)
+
+/** \brief Mask for Ifx_SCU_EXTCON_Bits.SEL1 */
+#define IFX_SCU_EXTCON_SEL1_MSK (0xfu)
+
+/** \brief Offset for Ifx_SCU_EXTCON_Bits.SEL1 */
+#define IFX_SCU_EXTCON_SEL1_OFF (18u)
+
+/** \brief Length for Ifx_SCU_FDR_Bits.DISCLK */
+#define IFX_SCU_FDR_DISCLK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_FDR_Bits.DISCLK */
+#define IFX_SCU_FDR_DISCLK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_FDR_Bits.DISCLK */
+#define IFX_SCU_FDR_DISCLK_OFF (31u)
+
+/** \brief Length for Ifx_SCU_FDR_Bits.DM */
+#define IFX_SCU_FDR_DM_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_FDR_Bits.DM */
+#define IFX_SCU_FDR_DM_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_FDR_Bits.DM */
+#define IFX_SCU_FDR_DM_OFF (14u)
+
+/** \brief Length for Ifx_SCU_FDR_Bits.RESULT */
+#define IFX_SCU_FDR_RESULT_LEN (10u)
+
+/** \brief Mask for Ifx_SCU_FDR_Bits.RESULT */
+#define IFX_SCU_FDR_RESULT_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_SCU_FDR_Bits.RESULT */
+#define IFX_SCU_FDR_RESULT_OFF (16u)
+
+/** \brief Length for Ifx_SCU_FDR_Bits.STEP */
+#define IFX_SCU_FDR_STEP_LEN (10u)
+
+/** \brief Mask for Ifx_SCU_FDR_Bits.STEP */
+#define IFX_SCU_FDR_STEP_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_SCU_FDR_Bits.STEP */
+#define IFX_SCU_FDR_STEP_OFF (0u)
+
+/** \brief Length for Ifx_SCU_FMR_Bits.FC0 */
+#define IFX_SCU_FMR_FC0_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_FMR_Bits.FC0 */
+#define IFX_SCU_FMR_FC0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_FMR_Bits.FC0 */
+#define IFX_SCU_FMR_FC0_OFF (16u)
+
+/** \brief Length for Ifx_SCU_FMR_Bits.FC1 */
+#define IFX_SCU_FMR_FC1_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_FMR_Bits.FC1 */
+#define IFX_SCU_FMR_FC1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_FMR_Bits.FC1 */
+#define IFX_SCU_FMR_FC1_OFF (17u)
+
+/** \brief Length for Ifx_SCU_FMR_Bits.FC2 */
+#define IFX_SCU_FMR_FC2_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_FMR_Bits.FC2 */
+#define IFX_SCU_FMR_FC2_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_FMR_Bits.FC2 */
+#define IFX_SCU_FMR_FC2_OFF (18u)
+
+/** \brief Length for Ifx_SCU_FMR_Bits.FC3 */
+#define IFX_SCU_FMR_FC3_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_FMR_Bits.FC3 */
+#define IFX_SCU_FMR_FC3_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_FMR_Bits.FC3 */
+#define IFX_SCU_FMR_FC3_OFF (19u)
+
+/** \brief Length for Ifx_SCU_FMR_Bits.FC4 */
+#define IFX_SCU_FMR_FC4_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_FMR_Bits.FC4 */
+#define IFX_SCU_FMR_FC4_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_FMR_Bits.FC4 */
+#define IFX_SCU_FMR_FC4_OFF (20u)
+
+/** \brief Length for Ifx_SCU_FMR_Bits.FC5 */
+#define IFX_SCU_FMR_FC5_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_FMR_Bits.FC5 */
+#define IFX_SCU_FMR_FC5_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_FMR_Bits.FC5 */
+#define IFX_SCU_FMR_FC5_OFF (21u)
+
+/** \brief Length for Ifx_SCU_FMR_Bits.FC6 */
+#define IFX_SCU_FMR_FC6_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_FMR_Bits.FC6 */
+#define IFX_SCU_FMR_FC6_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_FMR_Bits.FC6 */
+#define IFX_SCU_FMR_FC6_OFF (22u)
+
+/** \brief Length for Ifx_SCU_FMR_Bits.FC7 */
+#define IFX_SCU_FMR_FC7_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_FMR_Bits.FC7 */
+#define IFX_SCU_FMR_FC7_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_FMR_Bits.FC7 */
+#define IFX_SCU_FMR_FC7_OFF (23u)
+
+/** \brief Length for Ifx_SCU_FMR_Bits.FS0 */
+#define IFX_SCU_FMR_FS0_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_FMR_Bits.FS0 */
+#define IFX_SCU_FMR_FS0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_FMR_Bits.FS0 */
+#define IFX_SCU_FMR_FS0_OFF (0u)
+
+/** \brief Length for Ifx_SCU_FMR_Bits.FS1 */
+#define IFX_SCU_FMR_FS1_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_FMR_Bits.FS1 */
+#define IFX_SCU_FMR_FS1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_FMR_Bits.FS1 */
+#define IFX_SCU_FMR_FS1_OFF (1u)
+
+/** \brief Length for Ifx_SCU_FMR_Bits.FS2 */
+#define IFX_SCU_FMR_FS2_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_FMR_Bits.FS2 */
+#define IFX_SCU_FMR_FS2_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_FMR_Bits.FS2 */
+#define IFX_SCU_FMR_FS2_OFF (2u)
+
+/** \brief Length for Ifx_SCU_FMR_Bits.FS3 */
+#define IFX_SCU_FMR_FS3_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_FMR_Bits.FS3 */
+#define IFX_SCU_FMR_FS3_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_FMR_Bits.FS3 */
+#define IFX_SCU_FMR_FS3_OFF (3u)
+
+/** \brief Length for Ifx_SCU_FMR_Bits.FS4 */
+#define IFX_SCU_FMR_FS4_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_FMR_Bits.FS4 */
+#define IFX_SCU_FMR_FS4_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_FMR_Bits.FS4 */
+#define IFX_SCU_FMR_FS4_OFF (4u)
+
+/** \brief Length for Ifx_SCU_FMR_Bits.FS5 */
+#define IFX_SCU_FMR_FS5_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_FMR_Bits.FS5 */
+#define IFX_SCU_FMR_FS5_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_FMR_Bits.FS5 */
+#define IFX_SCU_FMR_FS5_OFF (5u)
+
+/** \brief Length for Ifx_SCU_FMR_Bits.FS6 */
+#define IFX_SCU_FMR_FS6_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_FMR_Bits.FS6 */
+#define IFX_SCU_FMR_FS6_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_FMR_Bits.FS6 */
+#define IFX_SCU_FMR_FS6_OFF (6u)
+
+/** \brief Length for Ifx_SCU_FMR_Bits.FS7 */
+#define IFX_SCU_FMR_FS7_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_FMR_Bits.FS7 */
+#define IFX_SCU_FMR_FS7_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_FMR_Bits.FS7 */
+#define IFX_SCU_FMR_FS7_OFF (7u)
+
+/** \brief Length for Ifx_SCU_ID_Bits.MODNUMBER */
+#define IFX_SCU_ID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_SCU_ID_Bits.MODNUMBER */
+#define IFX_SCU_ID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_SCU_ID_Bits.MODNUMBER */
+#define IFX_SCU_ID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_SCU_ID_Bits.MODREV */
+#define IFX_SCU_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_ID_Bits.MODREV */
+#define IFX_SCU_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_ID_Bits.MODREV */
+#define IFX_SCU_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_SCU_ID_Bits.MODTYPE */
+#define IFX_SCU_ID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_ID_Bits.MODTYPE */
+#define IFX_SCU_ID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_ID_Bits.MODTYPE */
+#define IFX_SCU_ID_MODTYPE_OFF (8u)
+
+/** \brief Length for Ifx_SCU_IGCR_Bits.GEEN0 */
+#define IFX_SCU_IGCR_GEEN0_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_IGCR_Bits.GEEN0 */
+#define IFX_SCU_IGCR_GEEN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_IGCR_Bits.GEEN0 */
+#define IFX_SCU_IGCR_GEEN0_OFF (13u)
+
+/** \brief Length for Ifx_SCU_IGCR_Bits.GEEN1 */
+#define IFX_SCU_IGCR_GEEN1_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_IGCR_Bits.GEEN1 */
+#define IFX_SCU_IGCR_GEEN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_IGCR_Bits.GEEN1 */
+#define IFX_SCU_IGCR_GEEN1_OFF (29u)
+
+/** \brief Length for Ifx_SCU_IGCR_Bits.IGP0 */
+#define IFX_SCU_IGCR_IGP0_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_IGCR_Bits.IGP0 */
+#define IFX_SCU_IGCR_IGP0_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_IGCR_Bits.IGP0 */
+#define IFX_SCU_IGCR_IGP0_OFF (14u)
+
+/** \brief Length for Ifx_SCU_IGCR_Bits.IGP1 */
+#define IFX_SCU_IGCR_IGP1_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_IGCR_Bits.IGP1 */
+#define IFX_SCU_IGCR_IGP1_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_IGCR_Bits.IGP1 */
+#define IFX_SCU_IGCR_IGP1_OFF (30u)
+
+/** \brief Length for Ifx_SCU_IGCR_Bits.IPEN00 */
+#define IFX_SCU_IGCR_IPEN00_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_IGCR_Bits.IPEN00 */
+#define IFX_SCU_IGCR_IPEN00_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_IGCR_Bits.IPEN00 */
+#define IFX_SCU_IGCR_IPEN00_OFF (0u)
+
+/** \brief Length for Ifx_SCU_IGCR_Bits.IPEN01 */
+#define IFX_SCU_IGCR_IPEN01_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_IGCR_Bits.IPEN01 */
+#define IFX_SCU_IGCR_IPEN01_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_IGCR_Bits.IPEN01 */
+#define IFX_SCU_IGCR_IPEN01_OFF (1u)
+
+/** \brief Length for Ifx_SCU_IGCR_Bits.IPEN02 */
+#define IFX_SCU_IGCR_IPEN02_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_IGCR_Bits.IPEN02 */
+#define IFX_SCU_IGCR_IPEN02_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_IGCR_Bits.IPEN02 */
+#define IFX_SCU_IGCR_IPEN02_OFF (2u)
+
+/** \brief Length for Ifx_SCU_IGCR_Bits.IPEN03 */
+#define IFX_SCU_IGCR_IPEN03_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_IGCR_Bits.IPEN03 */
+#define IFX_SCU_IGCR_IPEN03_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_IGCR_Bits.IPEN03 */
+#define IFX_SCU_IGCR_IPEN03_OFF (3u)
+
+/** \brief Length for Ifx_SCU_IGCR_Bits.IPEN04 */
+#define IFX_SCU_IGCR_IPEN04_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_IGCR_Bits.IPEN04 */
+#define IFX_SCU_IGCR_IPEN04_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_IGCR_Bits.IPEN04 */
+#define IFX_SCU_IGCR_IPEN04_OFF (4u)
+
+/** \brief Length for Ifx_SCU_IGCR_Bits.IPEN05 */
+#define IFX_SCU_IGCR_IPEN05_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_IGCR_Bits.IPEN05 */
+#define IFX_SCU_IGCR_IPEN05_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_IGCR_Bits.IPEN05 */
+#define IFX_SCU_IGCR_IPEN05_OFF (5u)
+
+/** \brief Length for Ifx_SCU_IGCR_Bits.IPEN06 */
+#define IFX_SCU_IGCR_IPEN06_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_IGCR_Bits.IPEN06 */
+#define IFX_SCU_IGCR_IPEN06_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_IGCR_Bits.IPEN06 */
+#define IFX_SCU_IGCR_IPEN06_OFF (6u)
+
+/** \brief Length for Ifx_SCU_IGCR_Bits.IPEN07 */
+#define IFX_SCU_IGCR_IPEN07_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_IGCR_Bits.IPEN07 */
+#define IFX_SCU_IGCR_IPEN07_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_IGCR_Bits.IPEN07 */
+#define IFX_SCU_IGCR_IPEN07_OFF (7u)
+
+/** \brief Length for Ifx_SCU_IGCR_Bits.IPEN10 */
+#define IFX_SCU_IGCR_IPEN10_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_IGCR_Bits.IPEN10 */
+#define IFX_SCU_IGCR_IPEN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_IGCR_Bits.IPEN10 */
+#define IFX_SCU_IGCR_IPEN10_OFF (16u)
+
+/** \brief Length for Ifx_SCU_IGCR_Bits.IPEN11 */
+#define IFX_SCU_IGCR_IPEN11_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_IGCR_Bits.IPEN11 */
+#define IFX_SCU_IGCR_IPEN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_IGCR_Bits.IPEN11 */
+#define IFX_SCU_IGCR_IPEN11_OFF (17u)
+
+/** \brief Length for Ifx_SCU_IGCR_Bits.IPEN12 */
+#define IFX_SCU_IGCR_IPEN12_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_IGCR_Bits.IPEN12 */
+#define IFX_SCU_IGCR_IPEN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_IGCR_Bits.IPEN12 */
+#define IFX_SCU_IGCR_IPEN12_OFF (18u)
+
+/** \brief Length for Ifx_SCU_IGCR_Bits.IPEN13 */
+#define IFX_SCU_IGCR_IPEN13_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_IGCR_Bits.IPEN13 */
+#define IFX_SCU_IGCR_IPEN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_IGCR_Bits.IPEN13 */
+#define IFX_SCU_IGCR_IPEN13_OFF (19u)
+
+/** \brief Length for Ifx_SCU_IGCR_Bits.IPEN14 */
+#define IFX_SCU_IGCR_IPEN14_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_IGCR_Bits.IPEN14 */
+#define IFX_SCU_IGCR_IPEN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_IGCR_Bits.IPEN14 */
+#define IFX_SCU_IGCR_IPEN14_OFF (20u)
+
+/** \brief Length for Ifx_SCU_IGCR_Bits.IPEN15 */
+#define IFX_SCU_IGCR_IPEN15_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_IGCR_Bits.IPEN15 */
+#define IFX_SCU_IGCR_IPEN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_IGCR_Bits.IPEN15 */
+#define IFX_SCU_IGCR_IPEN15_OFF (21u)
+
+/** \brief Length for Ifx_SCU_IGCR_Bits.IPEN16 */
+#define IFX_SCU_IGCR_IPEN16_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_IGCR_Bits.IPEN16 */
+#define IFX_SCU_IGCR_IPEN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_IGCR_Bits.IPEN16 */
+#define IFX_SCU_IGCR_IPEN16_OFF (22u)
+
+/** \brief Length for Ifx_SCU_IGCR_Bits.IPEN17 */
+#define IFX_SCU_IGCR_IPEN17_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_IGCR_Bits.IPEN17 */
+#define IFX_SCU_IGCR_IPEN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_IGCR_Bits.IPEN17 */
+#define IFX_SCU_IGCR_IPEN17_OFF (23u)
+
+/** \brief Length for Ifx_SCU_IN_Bits.P0 */
+#define IFX_SCU_IN_P0_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_IN_Bits.P0 */
+#define IFX_SCU_IN_P0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_IN_Bits.P0 */
+#define IFX_SCU_IN_P0_OFF (0u)
+
+/** \brief Length for Ifx_SCU_IN_Bits.P1 */
+#define IFX_SCU_IN_P1_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_IN_Bits.P1 */
+#define IFX_SCU_IN_P1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_IN_Bits.P1 */
+#define IFX_SCU_IN_P1_OFF (1u)
+
+/** \brief Length for Ifx_SCU_IOCR_Bits.PC0 */
+#define IFX_SCU_IOCR_PC0_LEN (4u)
+
+/** \brief Mask for Ifx_SCU_IOCR_Bits.PC0 */
+#define IFX_SCU_IOCR_PC0_MSK (0xfu)
+
+/** \brief Offset for Ifx_SCU_IOCR_Bits.PC0 */
+#define IFX_SCU_IOCR_PC0_OFF (4u)
+
+/** \brief Length for Ifx_SCU_IOCR_Bits.PC1 */
+#define IFX_SCU_IOCR_PC1_LEN (4u)
+
+/** \brief Mask for Ifx_SCU_IOCR_Bits.PC1 */
+#define IFX_SCU_IOCR_PC1_MSK (0xfu)
+
+/** \brief Offset for Ifx_SCU_IOCR_Bits.PC1 */
+#define IFX_SCU_IOCR_PC1_OFF (12u)
+
+/** \brief Length for Ifx_SCU_LBISTCTRL0_Bits.LBISTREQ */
+#define IFX_SCU_LBISTCTRL0_LBISTREQ_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_LBISTCTRL0_Bits.LBISTREQ */
+#define IFX_SCU_LBISTCTRL0_LBISTREQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_LBISTCTRL0_Bits.LBISTREQ */
+#define IFX_SCU_LBISTCTRL0_LBISTREQ_OFF (0u)
+
+/** \brief Length for Ifx_SCU_LBISTCTRL0_Bits.LBISTREQP */
+#define IFX_SCU_LBISTCTRL0_LBISTREQP_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_LBISTCTRL0_Bits.LBISTREQP */
+#define IFX_SCU_LBISTCTRL0_LBISTREQP_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_LBISTCTRL0_Bits.LBISTREQP */
+#define IFX_SCU_LBISTCTRL0_LBISTREQP_OFF (1u)
+
+/** \brief Length for Ifx_SCU_LBISTCTRL0_Bits.PATTERNS */
+#define IFX_SCU_LBISTCTRL0_PATTERNS_LEN (14u)
+
+/** \brief Mask for Ifx_SCU_LBISTCTRL0_Bits.PATTERNS */
+#define IFX_SCU_LBISTCTRL0_PATTERNS_MSK (0x3fffu)
+
+/** \brief Offset for Ifx_SCU_LBISTCTRL0_Bits.PATTERNS */
+#define IFX_SCU_LBISTCTRL0_PATTERNS_OFF (2u)
+
+/** \brief Length for Ifx_SCU_LBISTCTRL1_Bits.BODY */
+#define IFX_SCU_LBISTCTRL1_BODY_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_LBISTCTRL1_Bits.BODY */
+#define IFX_SCU_LBISTCTRL1_BODY_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_LBISTCTRL1_Bits.BODY */
+#define IFX_SCU_LBISTCTRL1_BODY_OFF (27u)
+
+/** \brief Length for Ifx_SCU_LBISTCTRL1_Bits.LBISTFREQU */
+#define IFX_SCU_LBISTCTRL1_LBISTFREQU_LEN (4u)
+
+/** \brief Mask for Ifx_SCU_LBISTCTRL1_Bits.LBISTFREQU */
+#define IFX_SCU_LBISTCTRL1_LBISTFREQU_MSK (0xfu)
+
+/** \brief Offset for Ifx_SCU_LBISTCTRL1_Bits.LBISTFREQU */
+#define IFX_SCU_LBISTCTRL1_LBISTFREQU_OFF (28u)
+
+/** \brief Length for Ifx_SCU_LBISTCTRL1_Bits.SEED */
+#define IFX_SCU_LBISTCTRL1_SEED_LEN (23u)
+
+/** \brief Mask for Ifx_SCU_LBISTCTRL1_Bits.SEED */
+#define IFX_SCU_LBISTCTRL1_SEED_MSK (0x7fffffu)
+
+/** \brief Offset for Ifx_SCU_LBISTCTRL1_Bits.SEED */
+#define IFX_SCU_LBISTCTRL1_SEED_OFF (0u)
+
+/** \brief Length for Ifx_SCU_LBISTCTRL1_Bits.SPLITSH */
+#define IFX_SCU_LBISTCTRL1_SPLITSH_LEN (3u)
+
+/** \brief Mask for Ifx_SCU_LBISTCTRL1_Bits.SPLITSH */
+#define IFX_SCU_LBISTCTRL1_SPLITSH_MSK (0x7u)
+
+/** \brief Offset for Ifx_SCU_LBISTCTRL1_Bits.SPLITSH */
+#define IFX_SCU_LBISTCTRL1_SPLITSH_OFF (24u)
+
+/** \brief Length for Ifx_SCU_LBISTCTRL2_Bits.LBISTDONE */
+#define IFX_SCU_LBISTCTRL2_LBISTDONE_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_LBISTCTRL2_Bits.LBISTDONE */
+#define IFX_SCU_LBISTCTRL2_LBISTDONE_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_LBISTCTRL2_Bits.LBISTDONE */
+#define IFX_SCU_LBISTCTRL2_LBISTDONE_OFF (31u)
+
+/** \brief Length for Ifx_SCU_LBISTCTRL2_Bits.SIGNATURE */
+#define IFX_SCU_LBISTCTRL2_SIGNATURE_LEN (24u)
+
+/** \brief Mask for Ifx_SCU_LBISTCTRL2_Bits.SIGNATURE */
+#define IFX_SCU_LBISTCTRL2_SIGNATURE_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_SCU_LBISTCTRL2_Bits.SIGNATURE */
+#define IFX_SCU_LBISTCTRL2_SIGNATURE_OFF (0u)
+
+/** \brief Length for Ifx_SCU_LCLCON_Bits.LS */
+#define IFX_SCU_LCLCON_LS_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_LCLCON_Bits.LS */
+#define IFX_SCU_LCLCON_LS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_LCLCON_Bits.LS */
+#define IFX_SCU_LCLCON_LS_OFF (16u)
+
+/** \brief Length for Ifx_SCU_LCLCON_Bits.LSEN */
+#define IFX_SCU_LCLCON_LSEN_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_LCLCON_Bits.LSEN */
+#define IFX_SCU_LCLCON_LSEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_LCLCON_Bits.LSEN */
+#define IFX_SCU_LCLCON_LSEN_OFF (31u)
+
+/** \brief Length for Ifx_SCU_LCLTEST_Bits.LCLT0 */
+#define IFX_SCU_LCLTEST_LCLT0_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_LCLTEST_Bits.LCLT0 */
+#define IFX_SCU_LCLTEST_LCLT0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_LCLTEST_Bits.LCLT0 */
+#define IFX_SCU_LCLTEST_LCLT0_OFF (0u)
+
+/** \brief Length for Ifx_SCU_LCLTEST_Bits.LCLT1 */
+#define IFX_SCU_LCLTEST_LCLT1_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_LCLTEST_Bits.LCLT1 */
+#define IFX_SCU_LCLTEST_LCLT1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_LCLTEST_Bits.LCLT1 */
+#define IFX_SCU_LCLTEST_LCLT1_OFF (1u)
+
+/** \brief Length for Ifx_SCU_MANID_Bits.DEPT */
+#define IFX_SCU_MANID_DEPT_LEN (5u)
+
+/** \brief Mask for Ifx_SCU_MANID_Bits.DEPT */
+#define IFX_SCU_MANID_DEPT_MSK (0x1fu)
+
+/** \brief Offset for Ifx_SCU_MANID_Bits.DEPT */
+#define IFX_SCU_MANID_DEPT_OFF (0u)
+
+/** \brief Length for Ifx_SCU_MANID_Bits.MANUF */
+#define IFX_SCU_MANID_MANUF_LEN (11u)
+
+/** \brief Mask for Ifx_SCU_MANID_Bits.MANUF */
+#define IFX_SCU_MANID_MANUF_MSK (0x7ffu)
+
+/** \brief Offset for Ifx_SCU_MANID_Bits.MANUF */
+#define IFX_SCU_MANID_MANUF_OFF (5u)
+
+/** \brief Length for Ifx_SCU_OMR_Bits.PCL0 */
+#define IFX_SCU_OMR_PCL0_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_OMR_Bits.PCL0 */
+#define IFX_SCU_OMR_PCL0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_OMR_Bits.PCL0 */
+#define IFX_SCU_OMR_PCL0_OFF (16u)
+
+/** \brief Length for Ifx_SCU_OMR_Bits.PCL1 */
+#define IFX_SCU_OMR_PCL1_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_OMR_Bits.PCL1 */
+#define IFX_SCU_OMR_PCL1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_OMR_Bits.PCL1 */
+#define IFX_SCU_OMR_PCL1_OFF (17u)
+
+/** \brief Length for Ifx_SCU_OMR_Bits.PS0 */
+#define IFX_SCU_OMR_PS0_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_OMR_Bits.PS0 */
+#define IFX_SCU_OMR_PS0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_OMR_Bits.PS0 */
+#define IFX_SCU_OMR_PS0_OFF (0u)
+
+/** \brief Length for Ifx_SCU_OMR_Bits.PS1 */
+#define IFX_SCU_OMR_PS1_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_OMR_Bits.PS1 */
+#define IFX_SCU_OMR_PS1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_OMR_Bits.PS1 */
+#define IFX_SCU_OMR_PS1_OFF (1u)
+
+/** \brief Length for Ifx_SCU_OSCCON_Bits.APREN */
+#define IFX_SCU_OSCCON_APREN_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_OSCCON_Bits.APREN */
+#define IFX_SCU_OSCCON_APREN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_OSCCON_Bits.APREN */
+#define IFX_SCU_OSCCON_APREN_OFF (23u)
+
+/** \brief Length for Ifx_SCU_OSCCON_Bits.CAP0EN */
+#define IFX_SCU_OSCCON_CAP0EN_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_OSCCON_Bits.CAP0EN */
+#define IFX_SCU_OSCCON_CAP0EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_OSCCON_Bits.CAP0EN */
+#define IFX_SCU_OSCCON_CAP0EN_OFF (24u)
+
+/** \brief Length for Ifx_SCU_OSCCON_Bits.CAP1EN */
+#define IFX_SCU_OSCCON_CAP1EN_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_OSCCON_Bits.CAP1EN */
+#define IFX_SCU_OSCCON_CAP1EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_OSCCON_Bits.CAP1EN */
+#define IFX_SCU_OSCCON_CAP1EN_OFF (25u)
+
+/** \brief Length for Ifx_SCU_OSCCON_Bits.CAP2EN */
+#define IFX_SCU_OSCCON_CAP2EN_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_OSCCON_Bits.CAP2EN */
+#define IFX_SCU_OSCCON_CAP2EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_OSCCON_Bits.CAP2EN */
+#define IFX_SCU_OSCCON_CAP2EN_OFF (26u)
+
+/** \brief Length for Ifx_SCU_OSCCON_Bits.CAP3EN */
+#define IFX_SCU_OSCCON_CAP3EN_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_OSCCON_Bits.CAP3EN */
+#define IFX_SCU_OSCCON_CAP3EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_OSCCON_Bits.CAP3EN */
+#define IFX_SCU_OSCCON_CAP3EN_OFF (27u)
+
+/** \brief Length for Ifx_SCU_OSCCON_Bits.GAINSEL */
+#define IFX_SCU_OSCCON_GAINSEL_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_OSCCON_Bits.GAINSEL */
+#define IFX_SCU_OSCCON_GAINSEL_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_OSCCON_Bits.GAINSEL */
+#define IFX_SCU_OSCCON_GAINSEL_OFF (3u)
+
+/** \brief Length for Ifx_SCU_OSCCON_Bits.MODE */
+#define IFX_SCU_OSCCON_MODE_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_OSCCON_Bits.MODE */
+#define IFX_SCU_OSCCON_MODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_OSCCON_Bits.MODE */
+#define IFX_SCU_OSCCON_MODE_OFF (5u)
+
+/** \brief Length for Ifx_SCU_OSCCON_Bits.OSCRES */
+#define IFX_SCU_OSCCON_OSCRES_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_OSCCON_Bits.OSCRES */
+#define IFX_SCU_OSCCON_OSCRES_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_OSCCON_Bits.OSCRES */
+#define IFX_SCU_OSCCON_OSCRES_OFF (2u)
+
+/** \brief Length for Ifx_SCU_OSCCON_Bits.OSCVAL */
+#define IFX_SCU_OSCCON_OSCVAL_LEN (5u)
+
+/** \brief Mask for Ifx_SCU_OSCCON_Bits.OSCVAL */
+#define IFX_SCU_OSCCON_OSCVAL_MSK (0x1fu)
+
+/** \brief Offset for Ifx_SCU_OSCCON_Bits.OSCVAL */
+#define IFX_SCU_OSCCON_OSCVAL_OFF (16u)
+
+/** \brief Length for Ifx_SCU_OSCCON_Bits.PLLHV */
+#define IFX_SCU_OSCCON_PLLHV_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_OSCCON_Bits.PLLHV */
+#define IFX_SCU_OSCCON_PLLHV_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_OSCCON_Bits.PLLHV */
+#define IFX_SCU_OSCCON_PLLHV_OFF (8u)
+
+/** \brief Length for Ifx_SCU_OSCCON_Bits.PLLLV */
+#define IFX_SCU_OSCCON_PLLLV_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_OSCCON_Bits.PLLLV */
+#define IFX_SCU_OSCCON_PLLLV_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_OSCCON_Bits.PLLLV */
+#define IFX_SCU_OSCCON_PLLLV_OFF (1u)
+
+/** \brief Length for Ifx_SCU_OSCCON_Bits.SHBY */
+#define IFX_SCU_OSCCON_SHBY_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_OSCCON_Bits.SHBY */
+#define IFX_SCU_OSCCON_SHBY_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_OSCCON_Bits.SHBY */
+#define IFX_SCU_OSCCON_SHBY_OFF (7u)
+
+/** \brief Length for Ifx_SCU_OSCCON_Bits.X1D */
+#define IFX_SCU_OSCCON_X1D_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_OSCCON_Bits.X1D */
+#define IFX_SCU_OSCCON_X1D_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_OSCCON_Bits.X1D */
+#define IFX_SCU_OSCCON_X1D_OFF (10u)
+
+/** \brief Length for Ifx_SCU_OSCCON_Bits.X1DEN */
+#define IFX_SCU_OSCCON_X1DEN_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_OSCCON_Bits.X1DEN */
+#define IFX_SCU_OSCCON_X1DEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_OSCCON_Bits.X1DEN */
+#define IFX_SCU_OSCCON_X1DEN_OFF (11u)
+
+/** \brief Length for Ifx_SCU_OUT_Bits.P0 */
+#define IFX_SCU_OUT_P0_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_OUT_Bits.P0 */
+#define IFX_SCU_OUT_P0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_OUT_Bits.P0 */
+#define IFX_SCU_OUT_P0_OFF (0u)
+
+/** \brief Length for Ifx_SCU_OUT_Bits.P1 */
+#define IFX_SCU_OUT_P1_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_OUT_Bits.P1 */
+#define IFX_SCU_OUT_P1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_OUT_Bits.P1 */
+#define IFX_SCU_OUT_P1_OFF (1u)
+
+/** \brief Length for Ifx_SCU_OVCCON_Bits.CSEL0 */
+#define IFX_SCU_OVCCON_CSEL0_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_OVCCON_Bits.CSEL0 */
+#define IFX_SCU_OVCCON_CSEL0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_OVCCON_Bits.CSEL0 */
+#define IFX_SCU_OVCCON_CSEL0_OFF (0u)
+
+/** \brief Length for Ifx_SCU_OVCCON_Bits.CSEL1 */
+#define IFX_SCU_OVCCON_CSEL1_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_OVCCON_Bits.CSEL1 */
+#define IFX_SCU_OVCCON_CSEL1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_OVCCON_Bits.CSEL1 */
+#define IFX_SCU_OVCCON_CSEL1_OFF (1u)
+
+/** \brief Length for Ifx_SCU_OVCCON_Bits.CSEL2 */
+#define IFX_SCU_OVCCON_CSEL2_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_OVCCON_Bits.CSEL2 */
+#define IFX_SCU_OVCCON_CSEL2_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_OVCCON_Bits.CSEL2 */
+#define IFX_SCU_OVCCON_CSEL2_OFF (2u)
+
+/** \brief Length for Ifx_SCU_OVCCON_Bits.DCINVAL */
+#define IFX_SCU_OVCCON_DCINVAL_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_OVCCON_Bits.DCINVAL */
+#define IFX_SCU_OVCCON_DCINVAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_OVCCON_Bits.DCINVAL */
+#define IFX_SCU_OVCCON_DCINVAL_OFF (18u)
+
+/** \brief Length for Ifx_SCU_OVCCON_Bits.OVCONF */
+#define IFX_SCU_OVCCON_OVCONF_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_OVCCON_Bits.OVCONF */
+#define IFX_SCU_OVCCON_OVCONF_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_OVCCON_Bits.OVCONF */
+#define IFX_SCU_OVCCON_OVCONF_OFF (24u)
+
+/** \brief Length for Ifx_SCU_OVCCON_Bits.OVSTP */
+#define IFX_SCU_OVCCON_OVSTP_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_OVCCON_Bits.OVSTP */
+#define IFX_SCU_OVCCON_OVSTP_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_OVCCON_Bits.OVSTP */
+#define IFX_SCU_OVCCON_OVSTP_OFF (17u)
+
+/** \brief Length for Ifx_SCU_OVCCON_Bits.OVSTRT */
+#define IFX_SCU_OVCCON_OVSTRT_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_OVCCON_Bits.OVSTRT */
+#define IFX_SCU_OVCCON_OVSTRT_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_OVCCON_Bits.OVSTRT */
+#define IFX_SCU_OVCCON_OVSTRT_OFF (16u)
+
+/** \brief Length for Ifx_SCU_OVCCON_Bits.POVCONF */
+#define IFX_SCU_OVCCON_POVCONF_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_OVCCON_Bits.POVCONF */
+#define IFX_SCU_OVCCON_POVCONF_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_OVCCON_Bits.POVCONF */
+#define IFX_SCU_OVCCON_POVCONF_OFF (25u)
+
+/** \brief Length for Ifx_SCU_OVCENABLE_Bits.OVEN0 */
+#define IFX_SCU_OVCENABLE_OVEN0_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_OVCENABLE_Bits.OVEN0 */
+#define IFX_SCU_OVCENABLE_OVEN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_OVCENABLE_Bits.OVEN0 */
+#define IFX_SCU_OVCENABLE_OVEN0_OFF (0u)
+
+/** \brief Length for Ifx_SCU_OVCENABLE_Bits.OVEN1 */
+#define IFX_SCU_OVCENABLE_OVEN1_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_OVCENABLE_Bits.OVEN1 */
+#define IFX_SCU_OVCENABLE_OVEN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_OVCENABLE_Bits.OVEN1 */
+#define IFX_SCU_OVCENABLE_OVEN1_OFF (1u)
+
+/** \brief Length for Ifx_SCU_OVCENABLE_Bits.OVEN2 */
+#define IFX_SCU_OVCENABLE_OVEN2_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_OVCENABLE_Bits.OVEN2 */
+#define IFX_SCU_OVCENABLE_OVEN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_OVCENABLE_Bits.OVEN2 */
+#define IFX_SCU_OVCENABLE_OVEN2_OFF (2u)
+
+/** \brief Length for Ifx_SCU_PDISC_Bits.PDIS0 */
+#define IFX_SCU_PDISC_PDIS0_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PDISC_Bits.PDIS0 */
+#define IFX_SCU_PDISC_PDIS0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PDISC_Bits.PDIS0 */
+#define IFX_SCU_PDISC_PDIS0_OFF (0u)
+
+/** \brief Length for Ifx_SCU_PDISC_Bits.PDIS1 */
+#define IFX_SCU_PDISC_PDIS1_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PDISC_Bits.PDIS1 */
+#define IFX_SCU_PDISC_PDIS1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PDISC_Bits.PDIS1 */
+#define IFX_SCU_PDISC_PDIS1_OFF (1u)
+
+/** \brief Length for Ifx_SCU_PDR_Bits.PD0 */
+#define IFX_SCU_PDR_PD0_LEN (3u)
+
+/** \brief Mask for Ifx_SCU_PDR_Bits.PD0 */
+#define IFX_SCU_PDR_PD0_MSK (0x7u)
+
+/** \brief Offset for Ifx_SCU_PDR_Bits.PD0 */
+#define IFX_SCU_PDR_PD0_OFF (0u)
+
+/** \brief Length for Ifx_SCU_PDR_Bits.PD1 */
+#define IFX_SCU_PDR_PD1_LEN (3u)
+
+/** \brief Mask for Ifx_SCU_PDR_Bits.PD1 */
+#define IFX_SCU_PDR_PD1_MSK (0x7u)
+
+/** \brief Offset for Ifx_SCU_PDR_Bits.PD1 */
+#define IFX_SCU_PDR_PD1_OFF (4u)
+
+/** \brief Length for Ifx_SCU_PDR_Bits.PL0 */
+#define IFX_SCU_PDR_PL0_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PDR_Bits.PL0 */
+#define IFX_SCU_PDR_PL0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PDR_Bits.PL0 */
+#define IFX_SCU_PDR_PL0_OFF (3u)
+
+/** \brief Length for Ifx_SCU_PDR_Bits.PL1 */
+#define IFX_SCU_PDR_PL1_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PDR_Bits.PL1 */
+#define IFX_SCU_PDR_PL1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PDR_Bits.PL1 */
+#define IFX_SCU_PDR_PL1_OFF (7u)
+
+/** \brief Length for Ifx_SCU_PDRR_Bits.PDR0 */
+#define IFX_SCU_PDRR_PDR0_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PDRR_Bits.PDR0 */
+#define IFX_SCU_PDRR_PDR0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PDRR_Bits.PDR0 */
+#define IFX_SCU_PDRR_PDR0_OFF (0u)
+
+/** \brief Length for Ifx_SCU_PDRR_Bits.PDR1 */
+#define IFX_SCU_PDRR_PDR1_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PDRR_Bits.PDR1 */
+#define IFX_SCU_PDRR_PDR1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PDRR_Bits.PDR1 */
+#define IFX_SCU_PDRR_PDR1_OFF (1u)
+
+/** \brief Length for Ifx_SCU_PDRR_Bits.PDR2 */
+#define IFX_SCU_PDRR_PDR2_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PDRR_Bits.PDR2 */
+#define IFX_SCU_PDRR_PDR2_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PDRR_Bits.PDR2 */
+#define IFX_SCU_PDRR_PDR2_OFF (2u)
+
+/** \brief Length for Ifx_SCU_PDRR_Bits.PDR3 */
+#define IFX_SCU_PDRR_PDR3_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PDRR_Bits.PDR3 */
+#define IFX_SCU_PDRR_PDR3_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PDRR_Bits.PDR3 */
+#define IFX_SCU_PDRR_PDR3_OFF (3u)
+
+/** \brief Length for Ifx_SCU_PDRR_Bits.PDR4 */
+#define IFX_SCU_PDRR_PDR4_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PDRR_Bits.PDR4 */
+#define IFX_SCU_PDRR_PDR4_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PDRR_Bits.PDR4 */
+#define IFX_SCU_PDRR_PDR4_OFF (4u)
+
+/** \brief Length for Ifx_SCU_PDRR_Bits.PDR5 */
+#define IFX_SCU_PDRR_PDR5_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PDRR_Bits.PDR5 */
+#define IFX_SCU_PDRR_PDR5_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PDRR_Bits.PDR5 */
+#define IFX_SCU_PDRR_PDR5_OFF (5u)
+
+/** \brief Length for Ifx_SCU_PDRR_Bits.PDR6 */
+#define IFX_SCU_PDRR_PDR6_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PDRR_Bits.PDR6 */
+#define IFX_SCU_PDRR_PDR6_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PDRR_Bits.PDR6 */
+#define IFX_SCU_PDRR_PDR6_OFF (6u)
+
+/** \brief Length for Ifx_SCU_PDRR_Bits.PDR7 */
+#define IFX_SCU_PDRR_PDR7_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PDRR_Bits.PDR7 */
+#define IFX_SCU_PDRR_PDR7_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PDRR_Bits.PDR7 */
+#define IFX_SCU_PDRR_PDR7_OFF (7u)
+
+/** \brief Length for Ifx_SCU_PLLCON0_Bits.CLRFINDIS */
+#define IFX_SCU_PLLCON0_CLRFINDIS_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PLLCON0_Bits.CLRFINDIS */
+#define IFX_SCU_PLLCON0_CLRFINDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PLLCON0_Bits.CLRFINDIS */
+#define IFX_SCU_PLLCON0_CLRFINDIS_OFF (5u)
+
+/** \brief Length for Ifx_SCU_PLLCON0_Bits.MODEN */
+#define IFX_SCU_PLLCON0_MODEN_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PLLCON0_Bits.MODEN */
+#define IFX_SCU_PLLCON0_MODEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PLLCON0_Bits.MODEN */
+#define IFX_SCU_PLLCON0_MODEN_OFF (2u)
+
+/** \brief Length for Ifx_SCU_PLLCON0_Bits.NDIV */
+#define IFX_SCU_PLLCON0_NDIV_LEN (7u)
+
+/** \brief Mask for Ifx_SCU_PLLCON0_Bits.NDIV */
+#define IFX_SCU_PLLCON0_NDIV_MSK (0x7fu)
+
+/** \brief Offset for Ifx_SCU_PLLCON0_Bits.NDIV */
+#define IFX_SCU_PLLCON0_NDIV_OFF (9u)
+
+/** \brief Length for Ifx_SCU_PLLCON0_Bits.OSCDISCDIS */
+#define IFX_SCU_PLLCON0_OSCDISCDIS_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PLLCON0_Bits.OSCDISCDIS */
+#define IFX_SCU_PLLCON0_OSCDISCDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PLLCON0_Bits.OSCDISCDIS */
+#define IFX_SCU_PLLCON0_OSCDISCDIS_OFF (6u)
+
+/** \brief Length for Ifx_SCU_PLLCON0_Bits.PDIV */
+#define IFX_SCU_PLLCON0_PDIV_LEN (4u)
+
+/** \brief Mask for Ifx_SCU_PLLCON0_Bits.PDIV */
+#define IFX_SCU_PLLCON0_PDIV_MSK (0xfu)
+
+/** \brief Offset for Ifx_SCU_PLLCON0_Bits.PDIV */
+#define IFX_SCU_PLLCON0_PDIV_OFF (24u)
+
+/** \brief Length for Ifx_SCU_PLLCON0_Bits.PLLPWD */
+#define IFX_SCU_PLLCON0_PLLPWD_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PLLCON0_Bits.PLLPWD */
+#define IFX_SCU_PLLCON0_PLLPWD_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PLLCON0_Bits.PLLPWD */
+#define IFX_SCU_PLLCON0_PLLPWD_OFF (16u)
+
+/** \brief Length for Ifx_SCU_PLLCON0_Bits.RESLD */
+#define IFX_SCU_PLLCON0_RESLD_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PLLCON0_Bits.RESLD */
+#define IFX_SCU_PLLCON0_RESLD_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PLLCON0_Bits.RESLD */
+#define IFX_SCU_PLLCON0_RESLD_OFF (18u)
+
+/** \brief Length for Ifx_SCU_PLLCON0_Bits.SETFINDIS */
+#define IFX_SCU_PLLCON0_SETFINDIS_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PLLCON0_Bits.SETFINDIS */
+#define IFX_SCU_PLLCON0_SETFINDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PLLCON0_Bits.SETFINDIS */
+#define IFX_SCU_PLLCON0_SETFINDIS_OFF (4u)
+
+/** \brief Length for Ifx_SCU_PLLCON0_Bits.VCOBYP */
+#define IFX_SCU_PLLCON0_VCOBYP_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PLLCON0_Bits.VCOBYP */
+#define IFX_SCU_PLLCON0_VCOBYP_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PLLCON0_Bits.VCOBYP */
+#define IFX_SCU_PLLCON0_VCOBYP_OFF (0u)
+
+/** \brief Length for Ifx_SCU_PLLCON0_Bits.VCOPWD */
+#define IFX_SCU_PLLCON0_VCOPWD_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PLLCON0_Bits.VCOPWD */
+#define IFX_SCU_PLLCON0_VCOPWD_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PLLCON0_Bits.VCOPWD */
+#define IFX_SCU_PLLCON0_VCOPWD_OFF (1u)
+
+/** \brief Length for Ifx_SCU_PLLCON1_Bits.K1DIV */
+#define IFX_SCU_PLLCON1_K1DIV_LEN (7u)
+
+/** \brief Mask for Ifx_SCU_PLLCON1_Bits.K1DIV */
+#define IFX_SCU_PLLCON1_K1DIV_MSK (0x7fu)
+
+/** \brief Offset for Ifx_SCU_PLLCON1_Bits.K1DIV */
+#define IFX_SCU_PLLCON1_K1DIV_OFF (16u)
+
+/** \brief Length for Ifx_SCU_PLLCON1_Bits.K2DIV */
+#define IFX_SCU_PLLCON1_K2DIV_LEN (7u)
+
+/** \brief Mask for Ifx_SCU_PLLCON1_Bits.K2DIV */
+#define IFX_SCU_PLLCON1_K2DIV_MSK (0x7fu)
+
+/** \brief Offset for Ifx_SCU_PLLCON1_Bits.K2DIV */
+#define IFX_SCU_PLLCON1_K2DIV_OFF (0u)
+
+/** \brief Length for Ifx_SCU_PLLCON1_Bits.K3DIV */
+#define IFX_SCU_PLLCON1_K3DIV_LEN (7u)
+
+/** \brief Mask for Ifx_SCU_PLLCON1_Bits.K3DIV */
+#define IFX_SCU_PLLCON1_K3DIV_MSK (0x7fu)
+
+/** \brief Offset for Ifx_SCU_PLLCON1_Bits.K3DIV */
+#define IFX_SCU_PLLCON1_K3DIV_OFF (8u)
+
+/** \brief Length for Ifx_SCU_PLLCON2_Bits.MODCFG */
+#define IFX_SCU_PLLCON2_MODCFG_LEN (16u)
+
+/** \brief Mask for Ifx_SCU_PLLCON2_Bits.MODCFG */
+#define IFX_SCU_PLLCON2_MODCFG_MSK (0xffffu)
+
+/** \brief Offset for Ifx_SCU_PLLCON2_Bits.MODCFG */
+#define IFX_SCU_PLLCON2_MODCFG_OFF (0u)
+
+/** \brief Length for Ifx_SCU_PLLERAYCON0_Bits.CLRFINDIS */
+#define IFX_SCU_PLLERAYCON0_CLRFINDIS_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PLLERAYCON0_Bits.CLRFINDIS */
+#define IFX_SCU_PLLERAYCON0_CLRFINDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PLLERAYCON0_Bits.CLRFINDIS */
+#define IFX_SCU_PLLERAYCON0_CLRFINDIS_OFF (5u)
+
+/** \brief Length for Ifx_SCU_PLLERAYCON0_Bits.NDIV */
+#define IFX_SCU_PLLERAYCON0_NDIV_LEN (5u)
+
+/** \brief Mask for Ifx_SCU_PLLERAYCON0_Bits.NDIV */
+#define IFX_SCU_PLLERAYCON0_NDIV_MSK (0x1fu)
+
+/** \brief Offset for Ifx_SCU_PLLERAYCON0_Bits.NDIV */
+#define IFX_SCU_PLLERAYCON0_NDIV_OFF (9u)
+
+/** \brief Length for Ifx_SCU_PLLERAYCON0_Bits.OSCDISCDIS */
+#define IFX_SCU_PLLERAYCON0_OSCDISCDIS_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PLLERAYCON0_Bits.OSCDISCDIS */
+#define IFX_SCU_PLLERAYCON0_OSCDISCDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PLLERAYCON0_Bits.OSCDISCDIS */
+#define IFX_SCU_PLLERAYCON0_OSCDISCDIS_OFF (6u)
+
+/** \brief Length for Ifx_SCU_PLLERAYCON0_Bits.PDIV */
+#define IFX_SCU_PLLERAYCON0_PDIV_LEN (4u)
+
+/** \brief Mask for Ifx_SCU_PLLERAYCON0_Bits.PDIV */
+#define IFX_SCU_PLLERAYCON0_PDIV_MSK (0xfu)
+
+/** \brief Offset for Ifx_SCU_PLLERAYCON0_Bits.PDIV */
+#define IFX_SCU_PLLERAYCON0_PDIV_OFF (24u)
+
+/** \brief Length for Ifx_SCU_PLLERAYCON0_Bits.PLLPWD */
+#define IFX_SCU_PLLERAYCON0_PLLPWD_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PLLERAYCON0_Bits.PLLPWD */
+#define IFX_SCU_PLLERAYCON0_PLLPWD_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PLLERAYCON0_Bits.PLLPWD */
+#define IFX_SCU_PLLERAYCON0_PLLPWD_OFF (16u)
+
+/** \brief Length for Ifx_SCU_PLLERAYCON0_Bits.RESLD */
+#define IFX_SCU_PLLERAYCON0_RESLD_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PLLERAYCON0_Bits.RESLD */
+#define IFX_SCU_PLLERAYCON0_RESLD_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PLLERAYCON0_Bits.RESLD */
+#define IFX_SCU_PLLERAYCON0_RESLD_OFF (18u)
+
+/** \brief Length for Ifx_SCU_PLLERAYCON0_Bits.SETFINDIS */
+#define IFX_SCU_PLLERAYCON0_SETFINDIS_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PLLERAYCON0_Bits.SETFINDIS */
+#define IFX_SCU_PLLERAYCON0_SETFINDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PLLERAYCON0_Bits.SETFINDIS */
+#define IFX_SCU_PLLERAYCON0_SETFINDIS_OFF (4u)
+
+/** \brief Length for Ifx_SCU_PLLERAYCON0_Bits.VCOBYP */
+#define IFX_SCU_PLLERAYCON0_VCOBYP_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PLLERAYCON0_Bits.VCOBYP */
+#define IFX_SCU_PLLERAYCON0_VCOBYP_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PLLERAYCON0_Bits.VCOBYP */
+#define IFX_SCU_PLLERAYCON0_VCOBYP_OFF (0u)
+
+/** \brief Length for Ifx_SCU_PLLERAYCON0_Bits.VCOPWD */
+#define IFX_SCU_PLLERAYCON0_VCOPWD_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PLLERAYCON0_Bits.VCOPWD */
+#define IFX_SCU_PLLERAYCON0_VCOPWD_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PLLERAYCON0_Bits.VCOPWD */
+#define IFX_SCU_PLLERAYCON0_VCOPWD_OFF (1u)
+
+/** \brief Length for Ifx_SCU_PLLERAYCON1_Bits.K1DIV */
+#define IFX_SCU_PLLERAYCON1_K1DIV_LEN (7u)
+
+/** \brief Mask for Ifx_SCU_PLLERAYCON1_Bits.K1DIV */
+#define IFX_SCU_PLLERAYCON1_K1DIV_MSK (0x7fu)
+
+/** \brief Offset for Ifx_SCU_PLLERAYCON1_Bits.K1DIV */
+#define IFX_SCU_PLLERAYCON1_K1DIV_OFF (16u)
+
+/** \brief Length for Ifx_SCU_PLLERAYCON1_Bits.K2DIV */
+#define IFX_SCU_PLLERAYCON1_K2DIV_LEN (7u)
+
+/** \brief Mask for Ifx_SCU_PLLERAYCON1_Bits.K2DIV */
+#define IFX_SCU_PLLERAYCON1_K2DIV_MSK (0x7fu)
+
+/** \brief Offset for Ifx_SCU_PLLERAYCON1_Bits.K2DIV */
+#define IFX_SCU_PLLERAYCON1_K2DIV_OFF (0u)
+
+/** \brief Length for Ifx_SCU_PLLERAYCON1_Bits.K3DIV */
+#define IFX_SCU_PLLERAYCON1_K3DIV_LEN (4u)
+
+/** \brief Mask for Ifx_SCU_PLLERAYCON1_Bits.K3DIV */
+#define IFX_SCU_PLLERAYCON1_K3DIV_MSK (0xfu)
+
+/** \brief Offset for Ifx_SCU_PLLERAYCON1_Bits.K3DIV */
+#define IFX_SCU_PLLERAYCON1_K3DIV_OFF (8u)
+
+/** \brief Length for Ifx_SCU_PLLERAYSTAT_Bits.FINDIS */
+#define IFX_SCU_PLLERAYSTAT_FINDIS_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PLLERAYSTAT_Bits.FINDIS */
+#define IFX_SCU_PLLERAYSTAT_FINDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PLLERAYSTAT_Bits.FINDIS */
+#define IFX_SCU_PLLERAYSTAT_FINDIS_OFF (3u)
+
+/** \brief Length for Ifx_SCU_PLLERAYSTAT_Bits.K1RDY */
+#define IFX_SCU_PLLERAYSTAT_K1RDY_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PLLERAYSTAT_Bits.K1RDY */
+#define IFX_SCU_PLLERAYSTAT_K1RDY_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PLLERAYSTAT_Bits.K1RDY */
+#define IFX_SCU_PLLERAYSTAT_K1RDY_OFF (4u)
+
+/** \brief Length for Ifx_SCU_PLLERAYSTAT_Bits.K2RDY */
+#define IFX_SCU_PLLERAYSTAT_K2RDY_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PLLERAYSTAT_Bits.K2RDY */
+#define IFX_SCU_PLLERAYSTAT_K2RDY_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PLLERAYSTAT_Bits.K2RDY */
+#define IFX_SCU_PLLERAYSTAT_K2RDY_OFF (5u)
+
+/** \brief Length for Ifx_SCU_PLLERAYSTAT_Bits.PWDSTAT */
+#define IFX_SCU_PLLERAYSTAT_PWDSTAT_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PLLERAYSTAT_Bits.PWDSTAT */
+#define IFX_SCU_PLLERAYSTAT_PWDSTAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PLLERAYSTAT_Bits.PWDSTAT */
+#define IFX_SCU_PLLERAYSTAT_PWDSTAT_OFF (1u)
+
+/** \brief Length for Ifx_SCU_PLLERAYSTAT_Bits.VCOBYST */
+#define IFX_SCU_PLLERAYSTAT_VCOBYST_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PLLERAYSTAT_Bits.VCOBYST */
+#define IFX_SCU_PLLERAYSTAT_VCOBYST_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PLLERAYSTAT_Bits.VCOBYST */
+#define IFX_SCU_PLLERAYSTAT_VCOBYST_OFF (0u)
+
+/** \brief Length for Ifx_SCU_PLLERAYSTAT_Bits.VCOLOCK */
+#define IFX_SCU_PLLERAYSTAT_VCOLOCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PLLERAYSTAT_Bits.VCOLOCK */
+#define IFX_SCU_PLLERAYSTAT_VCOLOCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PLLERAYSTAT_Bits.VCOLOCK */
+#define IFX_SCU_PLLERAYSTAT_VCOLOCK_OFF (2u)
+
+/** \brief Length for Ifx_SCU_PLLSTAT_Bits.FINDIS */
+#define IFX_SCU_PLLSTAT_FINDIS_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PLLSTAT_Bits.FINDIS */
+#define IFX_SCU_PLLSTAT_FINDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PLLSTAT_Bits.FINDIS */
+#define IFX_SCU_PLLSTAT_FINDIS_OFF (3u)
+
+/** \brief Length for Ifx_SCU_PLLSTAT_Bits.K1RDY */
+#define IFX_SCU_PLLSTAT_K1RDY_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PLLSTAT_Bits.K1RDY */
+#define IFX_SCU_PLLSTAT_K1RDY_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PLLSTAT_Bits.K1RDY */
+#define IFX_SCU_PLLSTAT_K1RDY_OFF (4u)
+
+/** \brief Length for Ifx_SCU_PLLSTAT_Bits.K2RDY */
+#define IFX_SCU_PLLSTAT_K2RDY_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PLLSTAT_Bits.K2RDY */
+#define IFX_SCU_PLLSTAT_K2RDY_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PLLSTAT_Bits.K2RDY */
+#define IFX_SCU_PLLSTAT_K2RDY_OFF (5u)
+
+/** \brief Length for Ifx_SCU_PLLSTAT_Bits.MODRUN */
+#define IFX_SCU_PLLSTAT_MODRUN_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PLLSTAT_Bits.MODRUN */
+#define IFX_SCU_PLLSTAT_MODRUN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PLLSTAT_Bits.MODRUN */
+#define IFX_SCU_PLLSTAT_MODRUN_OFF (7u)
+
+/** \brief Length for Ifx_SCU_PLLSTAT_Bits.VCOBYST */
+#define IFX_SCU_PLLSTAT_VCOBYST_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PLLSTAT_Bits.VCOBYST */
+#define IFX_SCU_PLLSTAT_VCOBYST_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PLLSTAT_Bits.VCOBYST */
+#define IFX_SCU_PLLSTAT_VCOBYST_OFF (0u)
+
+/** \brief Length for Ifx_SCU_PLLSTAT_Bits.VCOLOCK */
+#define IFX_SCU_PLLSTAT_VCOLOCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PLLSTAT_Bits.VCOLOCK */
+#define IFX_SCU_PLLSTAT_VCOLOCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PLLSTAT_Bits.VCOLOCK */
+#define IFX_SCU_PLLSTAT_VCOLOCK_OFF (2u)
+
+/** \brief Length for Ifx_SCU_PMCSR_Bits.PMST */
+#define IFX_SCU_PMCSR_PMST_LEN (3u)
+
+/** \brief Mask for Ifx_SCU_PMCSR_Bits.PMST */
+#define IFX_SCU_PMCSR_PMST_MSK (0x7u)
+
+/** \brief Offset for Ifx_SCU_PMCSR_Bits.PMST */
+#define IFX_SCU_PMCSR_PMST_OFF (8u)
+
+/** \brief Length for Ifx_SCU_PMCSR_Bits.REQSLP */
+#define IFX_SCU_PMCSR_REQSLP_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_PMCSR_Bits.REQSLP */
+#define IFX_SCU_PMCSR_REQSLP_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_PMCSR_Bits.REQSLP */
+#define IFX_SCU_PMCSR_REQSLP_OFF (0u)
+
+/** \brief Length for Ifx_SCU_PMCSR_Bits.SMUSLP */
+#define IFX_SCU_PMCSR_SMUSLP_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMCSR_Bits.SMUSLP */
+#define IFX_SCU_PMCSR_SMUSLP_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMCSR_Bits.SMUSLP */
+#define IFX_SCU_PMCSR_SMUSLP_OFF (2u)
+
+/** \brief Length for Ifx_SCU_PMSWCR0_Bits.DCDCSYNC */
+#define IFX_SCU_PMSWCR0_DCDCSYNC_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR0_Bits.DCDCSYNC */
+#define IFX_SCU_PMSWCR0_DCDCSYNC_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR0_Bits.DCDCSYNC */
+#define IFX_SCU_PMSWCR0_DCDCSYNC_OFF (25u)
+
+/** \brief Length for Ifx_SCU_PMSWCR0_Bits.ESR0DFEN */
+#define IFX_SCU_PMSWCR0_ESR0DFEN_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR0_Bits.ESR0DFEN */
+#define IFX_SCU_PMSWCR0_ESR0DFEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR0_Bits.ESR0DFEN */
+#define IFX_SCU_PMSWCR0_ESR0DFEN_OFF (4u)
+
+/** \brief Length for Ifx_SCU_PMSWCR0_Bits.ESR0EDCON */
+#define IFX_SCU_PMSWCR0_ESR0EDCON_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR0_Bits.ESR0EDCON */
+#define IFX_SCU_PMSWCR0_ESR0EDCON_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR0_Bits.ESR0EDCON */
+#define IFX_SCU_PMSWCR0_ESR0EDCON_OFF (5u)
+
+/** \brief Length for Ifx_SCU_PMSWCR0_Bits.ESR0TRIST */
+#define IFX_SCU_PMSWCR0_ESR0TRIST_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR0_Bits.ESR0TRIST */
+#define IFX_SCU_PMSWCR0_ESR0TRIST_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR0_Bits.ESR0TRIST */
+#define IFX_SCU_PMSWCR0_ESR0TRIST_OFF (29u)
+
+/** \brief Length for Ifx_SCU_PMSWCR0_Bits.ESR1DFEN */
+#define IFX_SCU_PMSWCR0_ESR1DFEN_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR0_Bits.ESR1DFEN */
+#define IFX_SCU_PMSWCR0_ESR1DFEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR0_Bits.ESR1DFEN */
+#define IFX_SCU_PMSWCR0_ESR1DFEN_OFF (7u)
+
+/** \brief Length for Ifx_SCU_PMSWCR0_Bits.ESR1EDCON */
+#define IFX_SCU_PMSWCR0_ESR1EDCON_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR0_Bits.ESR1EDCON */
+#define IFX_SCU_PMSWCR0_ESR1EDCON_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR0_Bits.ESR1EDCON */
+#define IFX_SCU_PMSWCR0_ESR1EDCON_OFF (8u)
+
+/** \brief Length for Ifx_SCU_PMSWCR0_Bits.ESR1WKEN */
+#define IFX_SCU_PMSWCR0_ESR1WKEN_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR0_Bits.ESR1WKEN */
+#define IFX_SCU_PMSWCR0_ESR1WKEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR0_Bits.ESR1WKEN */
+#define IFX_SCU_PMSWCR0_ESR1WKEN_OFF (1u)
+
+/** \brief Length for Ifx_SCU_PMSWCR0_Bits.LCK */
+#define IFX_SCU_PMSWCR0_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR0_Bits.LCK */
+#define IFX_SCU_PMSWCR0_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR0_Bits.LCK */
+#define IFX_SCU_PMSWCR0_LCK_OFF (31u)
+
+/** \brief Length for Ifx_SCU_PMSWCR0_Bits.PINADFEN */
+#define IFX_SCU_PMSWCR0_PINADFEN_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR0_Bits.PINADFEN */
+#define IFX_SCU_PMSWCR0_PINADFEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR0_Bits.PINADFEN */
+#define IFX_SCU_PMSWCR0_PINADFEN_OFF (10u)
+
+/** \brief Length for Ifx_SCU_PMSWCR0_Bits.PINAEDCON */
+#define IFX_SCU_PMSWCR0_PINAEDCON_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR0_Bits.PINAEDCON */
+#define IFX_SCU_PMSWCR0_PINAEDCON_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR0_Bits.PINAEDCON */
+#define IFX_SCU_PMSWCR0_PINAEDCON_OFF (11u)
+
+/** \brief Length for Ifx_SCU_PMSWCR0_Bits.PINAWKEN */
+#define IFX_SCU_PMSWCR0_PINAWKEN_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR0_Bits.PINAWKEN */
+#define IFX_SCU_PMSWCR0_PINAWKEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR0_Bits.PINAWKEN */
+#define IFX_SCU_PMSWCR0_PINAWKEN_OFF (2u)
+
+/** \brief Length for Ifx_SCU_PMSWCR0_Bits.PINBDFEN */
+#define IFX_SCU_PMSWCR0_PINBDFEN_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR0_Bits.PINBDFEN */
+#define IFX_SCU_PMSWCR0_PINBDFEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR0_Bits.PINBDFEN */
+#define IFX_SCU_PMSWCR0_PINBDFEN_OFF (13u)
+
+/** \brief Length for Ifx_SCU_PMSWCR0_Bits.PINBEDCON */
+#define IFX_SCU_PMSWCR0_PINBEDCON_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR0_Bits.PINBEDCON */
+#define IFX_SCU_PMSWCR0_PINBEDCON_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR0_Bits.PINBEDCON */
+#define IFX_SCU_PMSWCR0_PINBEDCON_OFF (14u)
+
+/** \brief Length for Ifx_SCU_PMSWCR0_Bits.PINBWKEN */
+#define IFX_SCU_PMSWCR0_PINBWKEN_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR0_Bits.PINBWKEN */
+#define IFX_SCU_PMSWCR0_PINBWKEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR0_Bits.PINBWKEN */
+#define IFX_SCU_PMSWCR0_PINBWKEN_OFF (3u)
+
+/** \brief Length for Ifx_SCU_PMSWCR0_Bits.PORSTDF */
+#define IFX_SCU_PMSWCR0_PORSTDF_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR0_Bits.PORSTDF */
+#define IFX_SCU_PMSWCR0_PORSTDF_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR0_Bits.PORSTDF */
+#define IFX_SCU_PMSWCR0_PORSTDF_OFF (23u)
+
+/** \brief Length for Ifx_SCU_PMSWCR0_Bits.SCRCLKSEL */
+#define IFX_SCU_PMSWCR0_SCRCLKSEL_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR0_Bits.SCRCLKSEL */
+#define IFX_SCU_PMSWCR0_SCRCLKSEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR0_Bits.SCRCLKSEL */
+#define IFX_SCU_PMSWCR0_SCRCLKSEL_OFF (19u)
+
+/** \brief Length for Ifx_SCU_PMSWCR0_Bits.SCREN */
+#define IFX_SCU_PMSWCR0_SCREN_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR0_Bits.SCREN */
+#define IFX_SCU_PMSWCR0_SCREN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR0_Bits.SCREN */
+#define IFX_SCU_PMSWCR0_SCREN_OFF (16u)
+
+/** \brief Length for Ifx_SCU_PMSWCR0_Bits.SCRWKEN */
+#define IFX_SCU_PMSWCR0_SCRWKEN_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR0_Bits.SCRWKEN */
+#define IFX_SCU_PMSWCR0_SCRWKEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR0_Bits.SCRWKEN */
+#define IFX_SCU_PMSWCR0_SCRWKEN_OFF (20u)
+
+/** \brief Length for Ifx_SCU_PMSWCR0_Bits.STBYRAMSEL */
+#define IFX_SCU_PMSWCR0_STBYRAMSEL_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR0_Bits.STBYRAMSEL */
+#define IFX_SCU_PMSWCR0_STBYRAMSEL_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR0_Bits.STBYRAMSEL */
+#define IFX_SCU_PMSWCR0_STBYRAMSEL_OFF (17u)
+
+/** \brief Length for Ifx_SCU_PMSWCR0_Bits.TRISTEN */
+#define IFX_SCU_PMSWCR0_TRISTEN_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR0_Bits.TRISTEN */
+#define IFX_SCU_PMSWCR0_TRISTEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR0_Bits.TRISTEN */
+#define IFX_SCU_PMSWCR0_TRISTEN_OFF (21u)
+
+/** \brief Length for Ifx_SCU_PMSWCR0_Bits.TRISTREQ */
+#define IFX_SCU_PMSWCR0_TRISTREQ_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR0_Bits.TRISTREQ */
+#define IFX_SCU_PMSWCR0_TRISTREQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR0_Bits.TRISTREQ */
+#define IFX_SCU_PMSWCR0_TRISTREQ_OFF (22u)
+
+/** \brief Length for Ifx_SCU_PMSWCR1_Bits.CPUIDLSEL */
+#define IFX_SCU_PMSWCR1_CPUIDLSEL_LEN (3u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR1_Bits.CPUIDLSEL */
+#define IFX_SCU_PMSWCR1_CPUIDLSEL_MSK (0x7u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR1_Bits.CPUIDLSEL */
+#define IFX_SCU_PMSWCR1_CPUIDLSEL_OFF (8u)
+
+/** \brief Length for Ifx_SCU_PMSWCR1_Bits.CPUSEL */
+#define IFX_SCU_PMSWCR1_CPUSEL_LEN (3u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR1_Bits.CPUSEL */
+#define IFX_SCU_PMSWCR1_CPUSEL_MSK (0x7u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR1_Bits.CPUSEL */
+#define IFX_SCU_PMSWCR1_CPUSEL_OFF (24u)
+
+/** \brief Length for Ifx_SCU_PMSWCR1_Bits.IRADIS */
+#define IFX_SCU_PMSWCR1_IRADIS_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR1_Bits.IRADIS */
+#define IFX_SCU_PMSWCR1_IRADIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR1_Bits.IRADIS */
+#define IFX_SCU_PMSWCR1_IRADIS_OFF (12u)
+
+/** \brief Length for Ifx_SCU_PMSWCR1_Bits.LCK */
+#define IFX_SCU_PMSWCR1_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR1_Bits.LCK */
+#define IFX_SCU_PMSWCR1_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR1_Bits.LCK */
+#define IFX_SCU_PMSWCR1_LCK_OFF (31u)
+
+/** \brief Length for Ifx_SCU_PMSWCR1_Bits.SCRCFG */
+#define IFX_SCU_PMSWCR1_SCRCFG_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR1_Bits.SCRCFG */
+#define IFX_SCU_PMSWCR1_SCRCFG_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_PMSWCR1_Bits.SCRCFG */
+#define IFX_SCU_PMSWCR1_SCRCFG_OFF (16u)
+
+/** \brief Length for Ifx_SCU_PMSWCR1_Bits.SCRSTEN */
+#define IFX_SCU_PMSWCR1_SCRSTEN_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR1_Bits.SCRSTEN */
+#define IFX_SCU_PMSWCR1_SCRSTEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR1_Bits.SCRSTEN */
+#define IFX_SCU_PMSWCR1_SCRSTEN_OFF (0u)
+
+/** \brief Length for Ifx_SCU_PMSWCR1_Bits.SCRSTREQ */
+#define IFX_SCU_PMSWCR1_SCRSTREQ_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR1_Bits.SCRSTREQ */
+#define IFX_SCU_PMSWCR1_SCRSTREQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR1_Bits.SCRSTREQ */
+#define IFX_SCU_PMSWCR1_SCRSTREQ_OFF (1u)
+
+/** \brief Length for Ifx_SCU_PMSWCR1_Bits.STBYEV */
+#define IFX_SCU_PMSWCR1_STBYEV_LEN (3u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR1_Bits.STBYEV */
+#define IFX_SCU_PMSWCR1_STBYEV_MSK (0x7u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR1_Bits.STBYEV */
+#define IFX_SCU_PMSWCR1_STBYEV_OFF (28u)
+
+/** \brief Length for Ifx_SCU_PMSWCR1_Bits.STBYEVEN */
+#define IFX_SCU_PMSWCR1_STBYEVEN_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR1_Bits.STBYEVEN */
+#define IFX_SCU_PMSWCR1_STBYEVEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR1_Bits.STBYEVEN */
+#define IFX_SCU_PMSWCR1_STBYEVEN_OFF (27u)
+
+/** \brief Length for Ifx_SCU_PMSWCR2_Bits.BUSY */
+#define IFX_SCU_PMSWCR2_BUSY_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR2_Bits.BUSY */
+#define IFX_SCU_PMSWCR2_BUSY_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR2_Bits.BUSY */
+#define IFX_SCU_PMSWCR2_BUSY_OFF (8u)
+
+/** \brief Length for Ifx_SCU_PMSWCR2_Bits.LCK */
+#define IFX_SCU_PMSWCR2_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR2_Bits.LCK */
+#define IFX_SCU_PMSWCR2_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR2_Bits.LCK */
+#define IFX_SCU_PMSWCR2_LCK_OFF (31u)
+
+/** \brief Length for Ifx_SCU_PMSWCR2_Bits.RST */
+#define IFX_SCU_PMSWCR2_RST_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR2_Bits.RST */
+#define IFX_SCU_PMSWCR2_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR2_Bits.RST */
+#define IFX_SCU_PMSWCR2_RST_OFF (26u)
+
+/** \brief Length for Ifx_SCU_PMSWCR2_Bits.SCRECC */
+#define IFX_SCU_PMSWCR2_SCRECC_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR2_Bits.SCRECC */
+#define IFX_SCU_PMSWCR2_SCRECC_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR2_Bits.SCRECC */
+#define IFX_SCU_PMSWCR2_SCRECC_OFF (9u)
+
+/** \brief Length for Ifx_SCU_PMSWCR2_Bits.SCRINT */
+#define IFX_SCU_PMSWCR2_SCRINT_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR2_Bits.SCRINT */
+#define IFX_SCU_PMSWCR2_SCRINT_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_PMSWCR2_Bits.SCRINT */
+#define IFX_SCU_PMSWCR2_SCRINT_OFF (0u)
+
+/** \brief Length for Ifx_SCU_PMSWCR2_Bits.SCRRST */
+#define IFX_SCU_PMSWCR2_SCRRST_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR2_Bits.SCRRST */
+#define IFX_SCU_PMSWCR2_SCRRST_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR2_Bits.SCRRST */
+#define IFX_SCU_PMSWCR2_SCRRST_OFF (11u)
+
+/** \brief Length for Ifx_SCU_PMSWCR2_Bits.SCRWDT */
+#define IFX_SCU_PMSWCR2_SCRWDT_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR2_Bits.SCRWDT */
+#define IFX_SCU_PMSWCR2_SCRWDT_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR2_Bits.SCRWDT */
+#define IFX_SCU_PMSWCR2_SCRWDT_OFF (10u)
+
+/** \brief Length for Ifx_SCU_PMSWCR2_Bits.SMURST */
+#define IFX_SCU_PMSWCR2_SMURST_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR2_Bits.SMURST */
+#define IFX_SCU_PMSWCR2_SMURST_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR2_Bits.SMURST */
+#define IFX_SCU_PMSWCR2_SMURST_OFF (25u)
+
+/** \brief Length for Ifx_SCU_PMSWCR2_Bits.TCINT */
+#define IFX_SCU_PMSWCR2_TCINT_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR2_Bits.TCINT */
+#define IFX_SCU_PMSWCR2_TCINT_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_PMSWCR2_Bits.TCINT */
+#define IFX_SCU_PMSWCR2_TCINT_OFF (16u)
+
+/** \brief Length for Ifx_SCU_PMSWCR2_Bits.TCINTREQ */
+#define IFX_SCU_PMSWCR2_TCINTREQ_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWCR2_Bits.TCINTREQ */
+#define IFX_SCU_PMSWCR2_TCINTREQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWCR2_Bits.TCINTREQ */
+#define IFX_SCU_PMSWCR2_TCINTREQ_OFF (24u)
+
+/** \brief Length for Ifx_SCU_PMSWSTAT_Bits.ESR0TRIST */
+#define IFX_SCU_PMSWSTAT_ESR0TRIST_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWSTAT_Bits.ESR0TRIST */
+#define IFX_SCU_PMSWSTAT_ESR0TRIST_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWSTAT_Bits.ESR0TRIST */
+#define IFX_SCU_PMSWSTAT_ESR0TRIST_OFF (27u)
+
+/** \brief Length for Ifx_SCU_PMSWSTAT_Bits.ESR1OVRUN */
+#define IFX_SCU_PMSWSTAT_ESR1OVRUN_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWSTAT_Bits.ESR1OVRUN */
+#define IFX_SCU_PMSWSTAT_ESR1OVRUN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWSTAT_Bits.ESR1OVRUN */
+#define IFX_SCU_PMSWSTAT_ESR1OVRUN_OFF (3u)
+
+/** \brief Length for Ifx_SCU_PMSWSTAT_Bits.ESR1WKEN */
+#define IFX_SCU_PMSWSTAT_ESR1WKEN_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWSTAT_Bits.ESR1WKEN */
+#define IFX_SCU_PMSWSTAT_ESR1WKEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWSTAT_Bits.ESR1WKEN */
+#define IFX_SCU_PMSWSTAT_ESR1WKEN_OFF (20u)
+
+/** \brief Length for Ifx_SCU_PMSWSTAT_Bits.ESR1WKP */
+#define IFX_SCU_PMSWSTAT_ESR1WKP_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWSTAT_Bits.ESR1WKP */
+#define IFX_SCU_PMSWSTAT_ESR1WKP_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWSTAT_Bits.ESR1WKP */
+#define IFX_SCU_PMSWSTAT_ESR1WKP_OFF (2u)
+
+/** \brief Length for Ifx_SCU_PMSWSTAT_Bits.HWCFGEVR */
+#define IFX_SCU_PMSWSTAT_HWCFGEVR_LEN (3u)
+
+/** \brief Mask for Ifx_SCU_PMSWSTAT_Bits.HWCFGEVR */
+#define IFX_SCU_PMSWSTAT_HWCFGEVR_MSK (0x7u)
+
+/** \brief Offset for Ifx_SCU_PMSWSTAT_Bits.HWCFGEVR */
+#define IFX_SCU_PMSWSTAT_HWCFGEVR_OFF (10u)
+
+/** \brief Length for Ifx_SCU_PMSWSTAT_Bits.PINAOVRUN */
+#define IFX_SCU_PMSWSTAT_PINAOVRUN_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWSTAT_Bits.PINAOVRUN */
+#define IFX_SCU_PMSWSTAT_PINAOVRUN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWSTAT_Bits.PINAOVRUN */
+#define IFX_SCU_PMSWSTAT_PINAOVRUN_OFF (5u)
+
+/** \brief Length for Ifx_SCU_PMSWSTAT_Bits.PINAWKEN */
+#define IFX_SCU_PMSWSTAT_PINAWKEN_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWSTAT_Bits.PINAWKEN */
+#define IFX_SCU_PMSWSTAT_PINAWKEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWSTAT_Bits.PINAWKEN */
+#define IFX_SCU_PMSWSTAT_PINAWKEN_OFF (21u)
+
+/** \brief Length for Ifx_SCU_PMSWSTAT_Bits.PINAWKP */
+#define IFX_SCU_PMSWSTAT_PINAWKP_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWSTAT_Bits.PINAWKP */
+#define IFX_SCU_PMSWSTAT_PINAWKP_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWSTAT_Bits.PINAWKP */
+#define IFX_SCU_PMSWSTAT_PINAWKP_OFF (4u)
+
+/** \brief Length for Ifx_SCU_PMSWSTAT_Bits.PINBOVRUN */
+#define IFX_SCU_PMSWSTAT_PINBOVRUN_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWSTAT_Bits.PINBOVRUN */
+#define IFX_SCU_PMSWSTAT_PINBOVRUN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWSTAT_Bits.PINBOVRUN */
+#define IFX_SCU_PMSWSTAT_PINBOVRUN_OFF (7u)
+
+/** \brief Length for Ifx_SCU_PMSWSTAT_Bits.PINBWKEN */
+#define IFX_SCU_PMSWSTAT_PINBWKEN_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWSTAT_Bits.PINBWKEN */
+#define IFX_SCU_PMSWSTAT_PINBWKEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWSTAT_Bits.PINBWKEN */
+#define IFX_SCU_PMSWSTAT_PINBWKEN_OFF (22u)
+
+/** \brief Length for Ifx_SCU_PMSWSTAT_Bits.PINBWKP */
+#define IFX_SCU_PMSWSTAT_PINBWKP_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWSTAT_Bits.PINBWKP */
+#define IFX_SCU_PMSWSTAT_PINBWKP_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWSTAT_Bits.PINBWKP */
+#define IFX_SCU_PMSWSTAT_PINBWKP_OFF (6u)
+
+/** \brief Length for Ifx_SCU_PMSWSTAT_Bits.PORSTDF */
+#define IFX_SCU_PMSWSTAT_PORSTDF_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWSTAT_Bits.PORSTDF */
+#define IFX_SCU_PMSWSTAT_PORSTDF_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWSTAT_Bits.PORSTDF */
+#define IFX_SCU_PMSWSTAT_PORSTDF_OFF (9u)
+
+/** \brief Length for Ifx_SCU_PMSWSTAT_Bits.SCR */
+#define IFX_SCU_PMSWSTAT_SCR_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWSTAT_Bits.SCR */
+#define IFX_SCU_PMSWSTAT_SCR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWSTAT_Bits.SCR */
+#define IFX_SCU_PMSWSTAT_SCR_OFF (18u)
+
+/** \brief Length for Ifx_SCU_PMSWSTAT_Bits.SCRST */
+#define IFX_SCU_PMSWSTAT_SCRST_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWSTAT_Bits.SCRST */
+#define IFX_SCU_PMSWSTAT_SCRST_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWSTAT_Bits.SCRST */
+#define IFX_SCU_PMSWSTAT_SCRST_OFF (16u)
+
+/** \brief Length for Ifx_SCU_PMSWSTAT_Bits.SCRWKEN */
+#define IFX_SCU_PMSWSTAT_SCRWKEN_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWSTAT_Bits.SCRWKEN */
+#define IFX_SCU_PMSWSTAT_SCRWKEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWSTAT_Bits.SCRWKEN */
+#define IFX_SCU_PMSWSTAT_SCRWKEN_OFF (19u)
+
+/** \brief Length for Ifx_SCU_PMSWSTAT_Bits.SCRWKP */
+#define IFX_SCU_PMSWSTAT_SCRWKP_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWSTAT_Bits.SCRWKP */
+#define IFX_SCU_PMSWSTAT_SCRWKP_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWSTAT_Bits.SCRWKP */
+#define IFX_SCU_PMSWSTAT_SCRWKP_OFF (17u)
+
+/** \brief Length for Ifx_SCU_PMSWSTAT_Bits.STBYRAM */
+#define IFX_SCU_PMSWSTAT_STBYRAM_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_PMSWSTAT_Bits.STBYRAM */
+#define IFX_SCU_PMSWSTAT_STBYRAM_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_PMSWSTAT_Bits.STBYRAM */
+#define IFX_SCU_PMSWSTAT_STBYRAM_OFF (13u)
+
+/** \brief Length for Ifx_SCU_PMSWSTAT_Bits.TRIST */
+#define IFX_SCU_PMSWSTAT_TRIST_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWSTAT_Bits.TRIST */
+#define IFX_SCU_PMSWSTAT_TRIST_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWSTAT_Bits.TRIST */
+#define IFX_SCU_PMSWSTAT_TRIST_OFF (15u)
+
+/** \brief Length for Ifx_SCU_PMSWSTATCLR_Bits.ESR1OVRUNCLR */
+#define IFX_SCU_PMSWSTATCLR_ESR1OVRUNCLR_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWSTATCLR_Bits.ESR1OVRUNCLR */
+#define IFX_SCU_PMSWSTATCLR_ESR1OVRUNCLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWSTATCLR_Bits.ESR1OVRUNCLR */
+#define IFX_SCU_PMSWSTATCLR_ESR1OVRUNCLR_OFF (3u)
+
+/** \brief Length for Ifx_SCU_PMSWSTATCLR_Bits.ESR1WKPCLR */
+#define IFX_SCU_PMSWSTATCLR_ESR1WKPCLR_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWSTATCLR_Bits.ESR1WKPCLR */
+#define IFX_SCU_PMSWSTATCLR_ESR1WKPCLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWSTATCLR_Bits.ESR1WKPCLR */
+#define IFX_SCU_PMSWSTATCLR_ESR1WKPCLR_OFF (2u)
+
+/** \brief Length for Ifx_SCU_PMSWSTATCLR_Bits.PINAOVRUNCLR */
+#define IFX_SCU_PMSWSTATCLR_PINAOVRUNCLR_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWSTATCLR_Bits.PINAOVRUNCLR */
+#define IFX_SCU_PMSWSTATCLR_PINAOVRUNCLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWSTATCLR_Bits.PINAOVRUNCLR */
+#define IFX_SCU_PMSWSTATCLR_PINAOVRUNCLR_OFF (5u)
+
+/** \brief Length for Ifx_SCU_PMSWSTATCLR_Bits.PINAWKPCLR */
+#define IFX_SCU_PMSWSTATCLR_PINAWKPCLR_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWSTATCLR_Bits.PINAWKPCLR */
+#define IFX_SCU_PMSWSTATCLR_PINAWKPCLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWSTATCLR_Bits.PINAWKPCLR */
+#define IFX_SCU_PMSWSTATCLR_PINAWKPCLR_OFF (4u)
+
+/** \brief Length for Ifx_SCU_PMSWSTATCLR_Bits.PINBOVRUNCLR */
+#define IFX_SCU_PMSWSTATCLR_PINBOVRUNCLR_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWSTATCLR_Bits.PINBOVRUNCLR */
+#define IFX_SCU_PMSWSTATCLR_PINBOVRUNCLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWSTATCLR_Bits.PINBOVRUNCLR */
+#define IFX_SCU_PMSWSTATCLR_PINBOVRUNCLR_OFF (7u)
+
+/** \brief Length for Ifx_SCU_PMSWSTATCLR_Bits.PINBWKPCLR */
+#define IFX_SCU_PMSWSTATCLR_PINBWKPCLR_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWSTATCLR_Bits.PINBWKPCLR */
+#define IFX_SCU_PMSWSTATCLR_PINBWKPCLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWSTATCLR_Bits.PINBWKPCLR */
+#define IFX_SCU_PMSWSTATCLR_PINBWKPCLR_OFF (6u)
+
+/** \brief Length for Ifx_SCU_PMSWSTATCLR_Bits.SCRSTCLR */
+#define IFX_SCU_PMSWSTATCLR_SCRSTCLR_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWSTATCLR_Bits.SCRSTCLR */
+#define IFX_SCU_PMSWSTATCLR_SCRSTCLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWSTATCLR_Bits.SCRSTCLR */
+#define IFX_SCU_PMSWSTATCLR_SCRSTCLR_OFF (16u)
+
+/** \brief Length for Ifx_SCU_PMSWSTATCLR_Bits.SCRWKPCLR */
+#define IFX_SCU_PMSWSTATCLR_SCRWKPCLR_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_PMSWSTATCLR_Bits.SCRWKPCLR */
+#define IFX_SCU_PMSWSTATCLR_SCRWKPCLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_PMSWSTATCLR_Bits.SCRWKPCLR */
+#define IFX_SCU_PMSWSTATCLR_SCRWKPCLR_OFF (17u)
+
+/** \brief Length for Ifx_SCU_RSTCON2_Bits.CLRC */
+#define IFX_SCU_RSTCON2_CLRC_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_RSTCON2_Bits.CLRC */
+#define IFX_SCU_RSTCON2_CLRC_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_RSTCON2_Bits.CLRC */
+#define IFX_SCU_RSTCON2_CLRC_OFF (1u)
+
+/** \brief Length for Ifx_SCU_RSTCON2_Bits.CSS0 */
+#define IFX_SCU_RSTCON2_CSS0_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_RSTCON2_Bits.CSS0 */
+#define IFX_SCU_RSTCON2_CSS0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_RSTCON2_Bits.CSS0 */
+#define IFX_SCU_RSTCON2_CSS0_OFF (12u)
+
+/** \brief Length for Ifx_SCU_RSTCON2_Bits.CSS1 */
+#define IFX_SCU_RSTCON2_CSS1_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_RSTCON2_Bits.CSS1 */
+#define IFX_SCU_RSTCON2_CSS1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_RSTCON2_Bits.CSS1 */
+#define IFX_SCU_RSTCON2_CSS1_OFF (13u)
+
+/** \brief Length for Ifx_SCU_RSTCON2_Bits.CSS2 */
+#define IFX_SCU_RSTCON2_CSS2_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_RSTCON2_Bits.CSS2 */
+#define IFX_SCU_RSTCON2_CSS2_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_RSTCON2_Bits.CSS2 */
+#define IFX_SCU_RSTCON2_CSS2_OFF (14u)
+
+/** \brief Length for Ifx_SCU_RSTCON2_Bits.USRINFO */
+#define IFX_SCU_RSTCON2_USRINFO_LEN (16u)
+
+/** \brief Mask for Ifx_SCU_RSTCON2_Bits.USRINFO */
+#define IFX_SCU_RSTCON2_USRINFO_MSK (0xffffu)
+
+/** \brief Offset for Ifx_SCU_RSTCON2_Bits.USRINFO */
+#define IFX_SCU_RSTCON2_USRINFO_OFF (16u)
+
+/** \brief Length for Ifx_SCU_RSTCON_Bits.ESR0 */
+#define IFX_SCU_RSTCON_ESR0_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_RSTCON_Bits.ESR0 */
+#define IFX_SCU_RSTCON_ESR0_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_RSTCON_Bits.ESR0 */
+#define IFX_SCU_RSTCON_ESR0_OFF (0u)
+
+/** \brief Length for Ifx_SCU_RSTCON_Bits.ESR1 */
+#define IFX_SCU_RSTCON_ESR1_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_RSTCON_Bits.ESR1 */
+#define IFX_SCU_RSTCON_ESR1_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_RSTCON_Bits.ESR1 */
+#define IFX_SCU_RSTCON_ESR1_OFF (2u)
+
+/** \brief Length for Ifx_SCU_RSTCON_Bits.SMU */
+#define IFX_SCU_RSTCON_SMU_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_RSTCON_Bits.SMU */
+#define IFX_SCU_RSTCON_SMU_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_RSTCON_Bits.SMU */
+#define IFX_SCU_RSTCON_SMU_OFF (6u)
+
+/** \brief Length for Ifx_SCU_RSTCON_Bits.STM0 */
+#define IFX_SCU_RSTCON_STM0_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_RSTCON_Bits.STM0 */
+#define IFX_SCU_RSTCON_STM0_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_RSTCON_Bits.STM0 */
+#define IFX_SCU_RSTCON_STM0_OFF (10u)
+
+/** \brief Length for Ifx_SCU_RSTCON_Bits.STM1 */
+#define IFX_SCU_RSTCON_STM1_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_RSTCON_Bits.STM1 */
+#define IFX_SCU_RSTCON_STM1_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_RSTCON_Bits.STM1 */
+#define IFX_SCU_RSTCON_STM1_OFF (12u)
+
+/** \brief Length for Ifx_SCU_RSTCON_Bits.STM2 */
+#define IFX_SCU_RSTCON_STM2_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_RSTCON_Bits.STM2 */
+#define IFX_SCU_RSTCON_STM2_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_RSTCON_Bits.STM2 */
+#define IFX_SCU_RSTCON_STM2_OFF (14u)
+
+/** \brief Length for Ifx_SCU_RSTCON_Bits.SW */
+#define IFX_SCU_RSTCON_SW_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_RSTCON_Bits.SW */
+#define IFX_SCU_RSTCON_SW_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_RSTCON_Bits.SW */
+#define IFX_SCU_RSTCON_SW_OFF (8u)
+
+/** \brief Length for Ifx_SCU_RSTSTAT_Bits.CB0 */
+#define IFX_SCU_RSTSTAT_CB0_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_RSTSTAT_Bits.CB0 */
+#define IFX_SCU_RSTSTAT_CB0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_RSTSTAT_Bits.CB0 */
+#define IFX_SCU_RSTSTAT_CB0_OFF (18u)
+
+/** \brief Length for Ifx_SCU_RSTSTAT_Bits.CB1 */
+#define IFX_SCU_RSTSTAT_CB1_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_RSTSTAT_Bits.CB1 */
+#define IFX_SCU_RSTSTAT_CB1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_RSTSTAT_Bits.CB1 */
+#define IFX_SCU_RSTSTAT_CB1_OFF (19u)
+
+/** \brief Length for Ifx_SCU_RSTSTAT_Bits.CB3 */
+#define IFX_SCU_RSTSTAT_CB3_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_RSTSTAT_Bits.CB3 */
+#define IFX_SCU_RSTSTAT_CB3_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_RSTSTAT_Bits.CB3 */
+#define IFX_SCU_RSTSTAT_CB3_OFF (20u)
+
+/** \brief Length for Ifx_SCU_RSTSTAT_Bits.ESR0 */
+#define IFX_SCU_RSTSTAT_ESR0_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_RSTSTAT_Bits.ESR0 */
+#define IFX_SCU_RSTSTAT_ESR0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_RSTSTAT_Bits.ESR0 */
+#define IFX_SCU_RSTSTAT_ESR0_OFF (0u)
+
+/** \brief Length for Ifx_SCU_RSTSTAT_Bits.ESR1 */
+#define IFX_SCU_RSTSTAT_ESR1_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_RSTSTAT_Bits.ESR1 */
+#define IFX_SCU_RSTSTAT_ESR1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_RSTSTAT_Bits.ESR1 */
+#define IFX_SCU_RSTSTAT_ESR1_OFF (1u)
+
+/** \brief Length for Ifx_SCU_RSTSTAT_Bits.EVR13 */
+#define IFX_SCU_RSTSTAT_EVR13_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_RSTSTAT_Bits.EVR13 */
+#define IFX_SCU_RSTSTAT_EVR13_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_RSTSTAT_Bits.EVR13 */
+#define IFX_SCU_RSTSTAT_EVR13_OFF (23u)
+
+/** \brief Length for Ifx_SCU_RSTSTAT_Bits.EVR33 */
+#define IFX_SCU_RSTSTAT_EVR33_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_RSTSTAT_Bits.EVR33 */
+#define IFX_SCU_RSTSTAT_EVR33_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_RSTSTAT_Bits.EVR33 */
+#define IFX_SCU_RSTSTAT_EVR33_OFF (24u)
+
+/** \brief Length for Ifx_SCU_RSTSTAT_Bits.PORST */
+#define IFX_SCU_RSTSTAT_PORST_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_RSTSTAT_Bits.PORST */
+#define IFX_SCU_RSTSTAT_PORST_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_RSTSTAT_Bits.PORST */
+#define IFX_SCU_RSTSTAT_PORST_OFF (16u)
+
+/** \brief Length for Ifx_SCU_RSTSTAT_Bits.SMU */
+#define IFX_SCU_RSTSTAT_SMU_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_RSTSTAT_Bits.SMU */
+#define IFX_SCU_RSTSTAT_SMU_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_RSTSTAT_Bits.SMU */
+#define IFX_SCU_RSTSTAT_SMU_OFF (3u)
+
+/** \brief Length for Ifx_SCU_RSTSTAT_Bits.STBYR */
+#define IFX_SCU_RSTSTAT_STBYR_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_RSTSTAT_Bits.STBYR */
+#define IFX_SCU_RSTSTAT_STBYR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_RSTSTAT_Bits.STBYR */
+#define IFX_SCU_RSTSTAT_STBYR_OFF (28u)
+
+/** \brief Length for Ifx_SCU_RSTSTAT_Bits.STM0 */
+#define IFX_SCU_RSTSTAT_STM0_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_RSTSTAT_Bits.STM0 */
+#define IFX_SCU_RSTSTAT_STM0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_RSTSTAT_Bits.STM0 */
+#define IFX_SCU_RSTSTAT_STM0_OFF (5u)
+
+/** \brief Length for Ifx_SCU_RSTSTAT_Bits.STM1 */
+#define IFX_SCU_RSTSTAT_STM1_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_RSTSTAT_Bits.STM1 */
+#define IFX_SCU_RSTSTAT_STM1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_RSTSTAT_Bits.STM1 */
+#define IFX_SCU_RSTSTAT_STM1_OFF (6u)
+
+/** \brief Length for Ifx_SCU_RSTSTAT_Bits.STM2 */
+#define IFX_SCU_RSTSTAT_STM2_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_RSTSTAT_Bits.STM2 */
+#define IFX_SCU_RSTSTAT_STM2_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_RSTSTAT_Bits.STM2 */
+#define IFX_SCU_RSTSTAT_STM2_OFF (7u)
+
+/** \brief Length for Ifx_SCU_RSTSTAT_Bits.SW */
+#define IFX_SCU_RSTSTAT_SW_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_RSTSTAT_Bits.SW */
+#define IFX_SCU_RSTSTAT_SW_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_RSTSTAT_Bits.SW */
+#define IFX_SCU_RSTSTAT_SW_OFF (4u)
+
+/** \brief Length for Ifx_SCU_RSTSTAT_Bits.SWD */
+#define IFX_SCU_RSTSTAT_SWD_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_RSTSTAT_Bits.SWD */
+#define IFX_SCU_RSTSTAT_SWD_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_RSTSTAT_Bits.SWD */
+#define IFX_SCU_RSTSTAT_SWD_OFF (25u)
+
+/** \brief Length for Ifx_SCU_SAFECON_Bits.HBT */
+#define IFX_SCU_SAFECON_HBT_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_SAFECON_Bits.HBT */
+#define IFX_SCU_SAFECON_HBT_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_SAFECON_Bits.HBT */
+#define IFX_SCU_SAFECON_HBT_OFF (0u)
+
+/** \brief Length for Ifx_SCU_STSTAT_Bits.FCBAE */
+#define IFX_SCU_STSTAT_FCBAE_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_STSTAT_Bits.FCBAE */
+#define IFX_SCU_STSTAT_FCBAE_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_STSTAT_Bits.FCBAE */
+#define IFX_SCU_STSTAT_FCBAE_OFF (16u)
+
+/** \brief Length for Ifx_SCU_STSTAT_Bits.FTM */
+#define IFX_SCU_STSTAT_FTM_LEN (7u)
+
+/** \brief Mask for Ifx_SCU_STSTAT_Bits.FTM */
+#define IFX_SCU_STSTAT_FTM_MSK (0x7fu)
+
+/** \brief Offset for Ifx_SCU_STSTAT_Bits.FTM */
+#define IFX_SCU_STSTAT_FTM_OFF (8u)
+
+/** \brief Length for Ifx_SCU_STSTAT_Bits.HWCFG */
+#define IFX_SCU_STSTAT_HWCFG_LEN (8u)
+
+/** \brief Mask for Ifx_SCU_STSTAT_Bits.HWCFG */
+#define IFX_SCU_STSTAT_HWCFG_MSK (0xffu)
+
+/** \brief Offset for Ifx_SCU_STSTAT_Bits.HWCFG */
+#define IFX_SCU_STSTAT_HWCFG_OFF (0u)
+
+/** \brief Length for Ifx_SCU_STSTAT_Bits.LUDIS */
+#define IFX_SCU_STSTAT_LUDIS_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_STSTAT_Bits.LUDIS */
+#define IFX_SCU_STSTAT_LUDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_STSTAT_Bits.LUDIS */
+#define IFX_SCU_STSTAT_LUDIS_OFF (17u)
+
+/** \brief Length for Ifx_SCU_STSTAT_Bits.MODE */
+#define IFX_SCU_STSTAT_MODE_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_STSTAT_Bits.MODE */
+#define IFX_SCU_STSTAT_MODE_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_STSTAT_Bits.MODE */
+#define IFX_SCU_STSTAT_MODE_OFF (15u)
+
+/** \brief Length for Ifx_SCU_STSTAT_Bits.RAMINT */
+#define IFX_SCU_STSTAT_RAMINT_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_STSTAT_Bits.RAMINT */
+#define IFX_SCU_STSTAT_RAMINT_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_STSTAT_Bits.RAMINT */
+#define IFX_SCU_STSTAT_RAMINT_OFF (24u)
+
+/** \brief Length for Ifx_SCU_STSTAT_Bits.SPDEN */
+#define IFX_SCU_STSTAT_SPDEN_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_STSTAT_Bits.SPDEN */
+#define IFX_SCU_STSTAT_SPDEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_STSTAT_Bits.SPDEN */
+#define IFX_SCU_STSTAT_SPDEN_OFF (20u)
+
+/** \brief Length for Ifx_SCU_STSTAT_Bits.TRSTL */
+#define IFX_SCU_STSTAT_TRSTL_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_STSTAT_Bits.TRSTL */
+#define IFX_SCU_STSTAT_TRSTL_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_STSTAT_Bits.TRSTL */
+#define IFX_SCU_STSTAT_TRSTL_OFF (19u)
+
+/** \brief Length for Ifx_SCU_SWRSTCON_Bits.SWRSTREQ */
+#define IFX_SCU_SWRSTCON_SWRSTREQ_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_SWRSTCON_Bits.SWRSTREQ */
+#define IFX_SCU_SWRSTCON_SWRSTREQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_SWRSTCON_Bits.SWRSTREQ */
+#define IFX_SCU_SWRSTCON_SWRSTREQ_OFF (1u)
+
+/** \brief Length for Ifx_SCU_SYSCON_Bits.CCTRIG0 */
+#define IFX_SCU_SYSCON_CCTRIG0_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_SYSCON_Bits.CCTRIG0 */
+#define IFX_SCU_SYSCON_CCTRIG0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_SYSCON_Bits.CCTRIG0 */
+#define IFX_SCU_SYSCON_CCTRIG0_OFF (0u)
+
+/** \brief Length for Ifx_SCU_SYSCON_Bits.DATM */
+#define IFX_SCU_SYSCON_DATM_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_SYSCON_Bits.DATM */
+#define IFX_SCU_SYSCON_DATM_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_SYSCON_Bits.DATM */
+#define IFX_SCU_SYSCON_DATM_OFF (8u)
+
+/** \brief Length for Ifx_SCU_SYSCON_Bits.RAMINTM */
+#define IFX_SCU_SYSCON_RAMINTM_LEN (2u)
+
+/** \brief Mask for Ifx_SCU_SYSCON_Bits.RAMINTM */
+#define IFX_SCU_SYSCON_RAMINTM_MSK (0x3u)
+
+/** \brief Offset for Ifx_SCU_SYSCON_Bits.RAMINTM */
+#define IFX_SCU_SYSCON_RAMINTM_OFF (2u)
+
+/** \brief Length for Ifx_SCU_SYSCON_Bits.SETLUDIS */
+#define IFX_SCU_SYSCON_SETLUDIS_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_SYSCON_Bits.SETLUDIS */
+#define IFX_SCU_SYSCON_SETLUDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_SYSCON_Bits.SETLUDIS */
+#define IFX_SCU_SYSCON_SETLUDIS_OFF (4u)
+
+/** \brief Length for Ifx_SCU_TRAPCLR_Bits.ESR0T */
+#define IFX_SCU_TRAPCLR_ESR0T_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_TRAPCLR_Bits.ESR0T */
+#define IFX_SCU_TRAPCLR_ESR0T_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_TRAPCLR_Bits.ESR0T */
+#define IFX_SCU_TRAPCLR_ESR0T_OFF (0u)
+
+/** \brief Length for Ifx_SCU_TRAPCLR_Bits.ESR1T */
+#define IFX_SCU_TRAPCLR_ESR1T_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_TRAPCLR_Bits.ESR1T */
+#define IFX_SCU_TRAPCLR_ESR1T_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_TRAPCLR_Bits.ESR1T */
+#define IFX_SCU_TRAPCLR_ESR1T_OFF (1u)
+
+/** \brief Length for Ifx_SCU_TRAPCLR_Bits.SMUT */
+#define IFX_SCU_TRAPCLR_SMUT_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_TRAPCLR_Bits.SMUT */
+#define IFX_SCU_TRAPCLR_SMUT_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_TRAPCLR_Bits.SMUT */
+#define IFX_SCU_TRAPCLR_SMUT_OFF (3u)
+
+/** \brief Length for Ifx_SCU_TRAPDIS_Bits.ESR0T */
+#define IFX_SCU_TRAPDIS_ESR0T_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_TRAPDIS_Bits.ESR0T */
+#define IFX_SCU_TRAPDIS_ESR0T_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_TRAPDIS_Bits.ESR0T */
+#define IFX_SCU_TRAPDIS_ESR0T_OFF (0u)
+
+/** \brief Length for Ifx_SCU_TRAPDIS_Bits.ESR1T */
+#define IFX_SCU_TRAPDIS_ESR1T_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_TRAPDIS_Bits.ESR1T */
+#define IFX_SCU_TRAPDIS_ESR1T_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_TRAPDIS_Bits.ESR1T */
+#define IFX_SCU_TRAPDIS_ESR1T_OFF (1u)
+
+/** \brief Length for Ifx_SCU_TRAPDIS_Bits.SMUT */
+#define IFX_SCU_TRAPDIS_SMUT_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_TRAPDIS_Bits.SMUT */
+#define IFX_SCU_TRAPDIS_SMUT_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_TRAPDIS_Bits.SMUT */
+#define IFX_SCU_TRAPDIS_SMUT_OFF (3u)
+
+/** \brief Length for Ifx_SCU_TRAPSET_Bits.ESR0T */
+#define IFX_SCU_TRAPSET_ESR0T_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_TRAPSET_Bits.ESR0T */
+#define IFX_SCU_TRAPSET_ESR0T_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_TRAPSET_Bits.ESR0T */
+#define IFX_SCU_TRAPSET_ESR0T_OFF (0u)
+
+/** \brief Length for Ifx_SCU_TRAPSET_Bits.ESR1T */
+#define IFX_SCU_TRAPSET_ESR1T_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_TRAPSET_Bits.ESR1T */
+#define IFX_SCU_TRAPSET_ESR1T_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_TRAPSET_Bits.ESR1T */
+#define IFX_SCU_TRAPSET_ESR1T_OFF (1u)
+
+/** \brief Length for Ifx_SCU_TRAPSET_Bits.SMUT */
+#define IFX_SCU_TRAPSET_SMUT_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_TRAPSET_Bits.SMUT */
+#define IFX_SCU_TRAPSET_SMUT_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_TRAPSET_Bits.SMUT */
+#define IFX_SCU_TRAPSET_SMUT_OFF (3u)
+
+/** \brief Length for Ifx_SCU_TRAPSTAT_Bits.ESR0T */
+#define IFX_SCU_TRAPSTAT_ESR0T_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_TRAPSTAT_Bits.ESR0T */
+#define IFX_SCU_TRAPSTAT_ESR0T_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_TRAPSTAT_Bits.ESR0T */
+#define IFX_SCU_TRAPSTAT_ESR0T_OFF (0u)
+
+/** \brief Length for Ifx_SCU_TRAPSTAT_Bits.ESR1T */
+#define IFX_SCU_TRAPSTAT_ESR1T_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_TRAPSTAT_Bits.ESR1T */
+#define IFX_SCU_TRAPSTAT_ESR1T_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_TRAPSTAT_Bits.ESR1T */
+#define IFX_SCU_TRAPSTAT_ESR1T_OFF (1u)
+
+/** \brief Length for Ifx_SCU_TRAPSTAT_Bits.SMUT */
+#define IFX_SCU_TRAPSTAT_SMUT_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_TRAPSTAT_Bits.SMUT */
+#define IFX_SCU_TRAPSTAT_SMUT_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_TRAPSTAT_Bits.SMUT */
+#define IFX_SCU_TRAPSTAT_SMUT_OFF (3u)
+
+/** \brief Length for Ifx_SCU_WDTCPU_CON0_Bits.ENDINIT */
+#define IFX_SCU_WDTCPU_CON0_ENDINIT_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTCPU_CON0_Bits.ENDINIT */
+#define IFX_SCU_WDTCPU_CON0_ENDINIT_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTCPU_CON0_Bits.ENDINIT */
+#define IFX_SCU_WDTCPU_CON0_ENDINIT_OFF (0u)
+
+/** \brief Length for Ifx_SCU_WDTCPU_CON0_Bits.LCK */
+#define IFX_SCU_WDTCPU_CON0_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTCPU_CON0_Bits.LCK */
+#define IFX_SCU_WDTCPU_CON0_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTCPU_CON0_Bits.LCK */
+#define IFX_SCU_WDTCPU_CON0_LCK_OFF (1u)
+
+/** \brief Length for Ifx_SCU_WDTCPU_CON0_Bits.PW */
+#define IFX_SCU_WDTCPU_CON0_PW_LEN (14u)
+
+/** \brief Mask for Ifx_SCU_WDTCPU_CON0_Bits.PW */
+#define IFX_SCU_WDTCPU_CON0_PW_MSK (0x3fffu)
+
+/** \brief Offset for Ifx_SCU_WDTCPU_CON0_Bits.PW */
+#define IFX_SCU_WDTCPU_CON0_PW_OFF (2u)
+
+/** \brief Length for Ifx_SCU_WDTCPU_CON0_Bits.REL */
+#define IFX_SCU_WDTCPU_CON0_REL_LEN (16u)
+
+/** \brief Mask for Ifx_SCU_WDTCPU_CON0_Bits.REL */
+#define IFX_SCU_WDTCPU_CON0_REL_MSK (0xffffu)
+
+/** \brief Offset for Ifx_SCU_WDTCPU_CON0_Bits.REL */
+#define IFX_SCU_WDTCPU_CON0_REL_OFF (16u)
+
+/** \brief Length for Ifx_SCU_WDTCPU_CON1_Bits.DR */
+#define IFX_SCU_WDTCPU_CON1_DR_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTCPU_CON1_Bits.DR */
+#define IFX_SCU_WDTCPU_CON1_DR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTCPU_CON1_Bits.DR */
+#define IFX_SCU_WDTCPU_CON1_DR_OFF (3u)
+
+/** \brief Length for Ifx_SCU_WDTCPU_CON1_Bits.IR0 */
+#define IFX_SCU_WDTCPU_CON1_IR0_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTCPU_CON1_Bits.IR0 */
+#define IFX_SCU_WDTCPU_CON1_IR0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTCPU_CON1_Bits.IR0 */
+#define IFX_SCU_WDTCPU_CON1_IR0_OFF (2u)
+
+/** \brief Length for Ifx_SCU_WDTCPU_CON1_Bits.IR1 */
+#define IFX_SCU_WDTCPU_CON1_IR1_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTCPU_CON1_Bits.IR1 */
+#define IFX_SCU_WDTCPU_CON1_IR1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTCPU_CON1_Bits.IR1 */
+#define IFX_SCU_WDTCPU_CON1_IR1_OFF (5u)
+
+/** \brief Length for Ifx_SCU_WDTCPU_CON1_Bits.PAR */
+#define IFX_SCU_WDTCPU_CON1_PAR_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTCPU_CON1_Bits.PAR */
+#define IFX_SCU_WDTCPU_CON1_PAR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTCPU_CON1_Bits.PAR */
+#define IFX_SCU_WDTCPU_CON1_PAR_OFF (7u)
+
+/** \brief Length for Ifx_SCU_WDTCPU_CON1_Bits.TCR */
+#define IFX_SCU_WDTCPU_CON1_TCR_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTCPU_CON1_Bits.TCR */
+#define IFX_SCU_WDTCPU_CON1_TCR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTCPU_CON1_Bits.TCR */
+#define IFX_SCU_WDTCPU_CON1_TCR_OFF (8u)
+
+/** \brief Length for Ifx_SCU_WDTCPU_CON1_Bits.TCTR */
+#define IFX_SCU_WDTCPU_CON1_TCTR_LEN (7u)
+
+/** \brief Mask for Ifx_SCU_WDTCPU_CON1_Bits.TCTR */
+#define IFX_SCU_WDTCPU_CON1_TCTR_MSK (0x7fu)
+
+/** \brief Offset for Ifx_SCU_WDTCPU_CON1_Bits.TCTR */
+#define IFX_SCU_WDTCPU_CON1_TCTR_OFF (9u)
+
+/** \brief Length for Ifx_SCU_WDTCPU_CON1_Bits.UR */
+#define IFX_SCU_WDTCPU_CON1_UR_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTCPU_CON1_Bits.UR */
+#define IFX_SCU_WDTCPU_CON1_UR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTCPU_CON1_Bits.UR */
+#define IFX_SCU_WDTCPU_CON1_UR_OFF (6u)
+
+/** \brief Length for Ifx_SCU_WDTCPU_SR_Bits.AE */
+#define IFX_SCU_WDTCPU_SR_AE_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTCPU_SR_Bits.AE */
+#define IFX_SCU_WDTCPU_SR_AE_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTCPU_SR_Bits.AE */
+#define IFX_SCU_WDTCPU_SR_AE_OFF (0u)
+
+/** \brief Length for Ifx_SCU_WDTCPU_SR_Bits.DS */
+#define IFX_SCU_WDTCPU_SR_DS_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTCPU_SR_Bits.DS */
+#define IFX_SCU_WDTCPU_SR_DS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTCPU_SR_Bits.DS */
+#define IFX_SCU_WDTCPU_SR_DS_OFF (3u)
+
+/** \brief Length for Ifx_SCU_WDTCPU_SR_Bits.IS0 */
+#define IFX_SCU_WDTCPU_SR_IS0_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTCPU_SR_Bits.IS0 */
+#define IFX_SCU_WDTCPU_SR_IS0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTCPU_SR_Bits.IS0 */
+#define IFX_SCU_WDTCPU_SR_IS0_OFF (2u)
+
+/** \brief Length for Ifx_SCU_WDTCPU_SR_Bits.IS1 */
+#define IFX_SCU_WDTCPU_SR_IS1_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTCPU_SR_Bits.IS1 */
+#define IFX_SCU_WDTCPU_SR_IS1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTCPU_SR_Bits.IS1 */
+#define IFX_SCU_WDTCPU_SR_IS1_OFF (5u)
+
+/** \brief Length for Ifx_SCU_WDTCPU_SR_Bits.OE */
+#define IFX_SCU_WDTCPU_SR_OE_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTCPU_SR_Bits.OE */
+#define IFX_SCU_WDTCPU_SR_OE_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTCPU_SR_Bits.OE */
+#define IFX_SCU_WDTCPU_SR_OE_OFF (1u)
+
+/** \brief Length for Ifx_SCU_WDTCPU_SR_Bits.PAS */
+#define IFX_SCU_WDTCPU_SR_PAS_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTCPU_SR_Bits.PAS */
+#define IFX_SCU_WDTCPU_SR_PAS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTCPU_SR_Bits.PAS */
+#define IFX_SCU_WDTCPU_SR_PAS_OFF (7u)
+
+/** \brief Length for Ifx_SCU_WDTCPU_SR_Bits.TCS */
+#define IFX_SCU_WDTCPU_SR_TCS_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTCPU_SR_Bits.TCS */
+#define IFX_SCU_WDTCPU_SR_TCS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTCPU_SR_Bits.TCS */
+#define IFX_SCU_WDTCPU_SR_TCS_OFF (8u)
+
+/** \brief Length for Ifx_SCU_WDTCPU_SR_Bits.TCT */
+#define IFX_SCU_WDTCPU_SR_TCT_LEN (7u)
+
+/** \brief Mask for Ifx_SCU_WDTCPU_SR_Bits.TCT */
+#define IFX_SCU_WDTCPU_SR_TCT_MSK (0x7fu)
+
+/** \brief Offset for Ifx_SCU_WDTCPU_SR_Bits.TCT */
+#define IFX_SCU_WDTCPU_SR_TCT_OFF (9u)
+
+/** \brief Length for Ifx_SCU_WDTCPU_SR_Bits.TIM */
+#define IFX_SCU_WDTCPU_SR_TIM_LEN (16u)
+
+/** \brief Mask for Ifx_SCU_WDTCPU_SR_Bits.TIM */
+#define IFX_SCU_WDTCPU_SR_TIM_MSK (0xffffu)
+
+/** \brief Offset for Ifx_SCU_WDTCPU_SR_Bits.TIM */
+#define IFX_SCU_WDTCPU_SR_TIM_OFF (16u)
+
+/** \brief Length for Ifx_SCU_WDTCPU_SR_Bits.TO */
+#define IFX_SCU_WDTCPU_SR_TO_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTCPU_SR_Bits.TO */
+#define IFX_SCU_WDTCPU_SR_TO_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTCPU_SR_Bits.TO */
+#define IFX_SCU_WDTCPU_SR_TO_OFF (4u)
+
+/** \brief Length for Ifx_SCU_WDTCPU_SR_Bits.US */
+#define IFX_SCU_WDTCPU_SR_US_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTCPU_SR_Bits.US */
+#define IFX_SCU_WDTCPU_SR_US_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTCPU_SR_Bits.US */
+#define IFX_SCU_WDTCPU_SR_US_OFF (6u)
+
+/** \brief Length for Ifx_SCU_WDTS_CON0_Bits.ENDINIT */
+#define IFX_SCU_WDTS_CON0_ENDINIT_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTS_CON0_Bits.ENDINIT */
+#define IFX_SCU_WDTS_CON0_ENDINIT_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTS_CON0_Bits.ENDINIT */
+#define IFX_SCU_WDTS_CON0_ENDINIT_OFF (0u)
+
+/** \brief Length for Ifx_SCU_WDTS_CON0_Bits.LCK */
+#define IFX_SCU_WDTS_CON0_LCK_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTS_CON0_Bits.LCK */
+#define IFX_SCU_WDTS_CON0_LCK_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTS_CON0_Bits.LCK */
+#define IFX_SCU_WDTS_CON0_LCK_OFF (1u)
+
+/** \brief Length for Ifx_SCU_WDTS_CON0_Bits.PW */
+#define IFX_SCU_WDTS_CON0_PW_LEN (14u)
+
+/** \brief Mask for Ifx_SCU_WDTS_CON0_Bits.PW */
+#define IFX_SCU_WDTS_CON0_PW_MSK (0x3fffu)
+
+/** \brief Offset for Ifx_SCU_WDTS_CON0_Bits.PW */
+#define IFX_SCU_WDTS_CON0_PW_OFF (2u)
+
+/** \brief Length for Ifx_SCU_WDTS_CON0_Bits.REL */
+#define IFX_SCU_WDTS_CON0_REL_LEN (16u)
+
+/** \brief Mask for Ifx_SCU_WDTS_CON0_Bits.REL */
+#define IFX_SCU_WDTS_CON0_REL_MSK (0xffffu)
+
+/** \brief Offset for Ifx_SCU_WDTS_CON0_Bits.REL */
+#define IFX_SCU_WDTS_CON0_REL_OFF (16u)
+
+/** \brief Length for Ifx_SCU_WDTS_CON1_Bits.CLRIRF */
+#define IFX_SCU_WDTS_CON1_CLRIRF_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTS_CON1_Bits.CLRIRF */
+#define IFX_SCU_WDTS_CON1_CLRIRF_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTS_CON1_Bits.CLRIRF */
+#define IFX_SCU_WDTS_CON1_CLRIRF_OFF (0u)
+
+/** \brief Length for Ifx_SCU_WDTS_CON1_Bits.DR */
+#define IFX_SCU_WDTS_CON1_DR_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTS_CON1_Bits.DR */
+#define IFX_SCU_WDTS_CON1_DR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTS_CON1_Bits.DR */
+#define IFX_SCU_WDTS_CON1_DR_OFF (3u)
+
+/** \brief Length for Ifx_SCU_WDTS_CON1_Bits.IR0 */
+#define IFX_SCU_WDTS_CON1_IR0_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTS_CON1_Bits.IR0 */
+#define IFX_SCU_WDTS_CON1_IR0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTS_CON1_Bits.IR0 */
+#define IFX_SCU_WDTS_CON1_IR0_OFF (2u)
+
+/** \brief Length for Ifx_SCU_WDTS_CON1_Bits.IR1 */
+#define IFX_SCU_WDTS_CON1_IR1_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTS_CON1_Bits.IR1 */
+#define IFX_SCU_WDTS_CON1_IR1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTS_CON1_Bits.IR1 */
+#define IFX_SCU_WDTS_CON1_IR1_OFF (5u)
+
+/** \brief Length for Ifx_SCU_WDTS_CON1_Bits.PAR */
+#define IFX_SCU_WDTS_CON1_PAR_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTS_CON1_Bits.PAR */
+#define IFX_SCU_WDTS_CON1_PAR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTS_CON1_Bits.PAR */
+#define IFX_SCU_WDTS_CON1_PAR_OFF (7u)
+
+/** \brief Length for Ifx_SCU_WDTS_CON1_Bits.TCR */
+#define IFX_SCU_WDTS_CON1_TCR_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTS_CON1_Bits.TCR */
+#define IFX_SCU_WDTS_CON1_TCR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTS_CON1_Bits.TCR */
+#define IFX_SCU_WDTS_CON1_TCR_OFF (8u)
+
+/** \brief Length for Ifx_SCU_WDTS_CON1_Bits.TCTR */
+#define IFX_SCU_WDTS_CON1_TCTR_LEN (7u)
+
+/** \brief Mask for Ifx_SCU_WDTS_CON1_Bits.TCTR */
+#define IFX_SCU_WDTS_CON1_TCTR_MSK (0x7fu)
+
+/** \brief Offset for Ifx_SCU_WDTS_CON1_Bits.TCTR */
+#define IFX_SCU_WDTS_CON1_TCTR_OFF (9u)
+
+/** \brief Length for Ifx_SCU_WDTS_CON1_Bits.UR */
+#define IFX_SCU_WDTS_CON1_UR_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTS_CON1_Bits.UR */
+#define IFX_SCU_WDTS_CON1_UR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTS_CON1_Bits.UR */
+#define IFX_SCU_WDTS_CON1_UR_OFF (6u)
+
+/** \brief Length for Ifx_SCU_WDTS_SR_Bits.AE */
+#define IFX_SCU_WDTS_SR_AE_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTS_SR_Bits.AE */
+#define IFX_SCU_WDTS_SR_AE_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTS_SR_Bits.AE */
+#define IFX_SCU_WDTS_SR_AE_OFF (0u)
+
+/** \brief Length for Ifx_SCU_WDTS_SR_Bits.DS */
+#define IFX_SCU_WDTS_SR_DS_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTS_SR_Bits.DS */
+#define IFX_SCU_WDTS_SR_DS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTS_SR_Bits.DS */
+#define IFX_SCU_WDTS_SR_DS_OFF (3u)
+
+/** \brief Length for Ifx_SCU_WDTS_SR_Bits.IS0 */
+#define IFX_SCU_WDTS_SR_IS0_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTS_SR_Bits.IS0 */
+#define IFX_SCU_WDTS_SR_IS0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTS_SR_Bits.IS0 */
+#define IFX_SCU_WDTS_SR_IS0_OFF (2u)
+
+/** \brief Length for Ifx_SCU_WDTS_SR_Bits.IS1 */
+#define IFX_SCU_WDTS_SR_IS1_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTS_SR_Bits.IS1 */
+#define IFX_SCU_WDTS_SR_IS1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTS_SR_Bits.IS1 */
+#define IFX_SCU_WDTS_SR_IS1_OFF (5u)
+
+/** \brief Length for Ifx_SCU_WDTS_SR_Bits.OE */
+#define IFX_SCU_WDTS_SR_OE_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTS_SR_Bits.OE */
+#define IFX_SCU_WDTS_SR_OE_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTS_SR_Bits.OE */
+#define IFX_SCU_WDTS_SR_OE_OFF (1u)
+
+/** \brief Length for Ifx_SCU_WDTS_SR_Bits.PAS */
+#define IFX_SCU_WDTS_SR_PAS_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTS_SR_Bits.PAS */
+#define IFX_SCU_WDTS_SR_PAS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTS_SR_Bits.PAS */
+#define IFX_SCU_WDTS_SR_PAS_OFF (7u)
+
+/** \brief Length for Ifx_SCU_WDTS_SR_Bits.TCS */
+#define IFX_SCU_WDTS_SR_TCS_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTS_SR_Bits.TCS */
+#define IFX_SCU_WDTS_SR_TCS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTS_SR_Bits.TCS */
+#define IFX_SCU_WDTS_SR_TCS_OFF (8u)
+
+/** \brief Length for Ifx_SCU_WDTS_SR_Bits.TCT */
+#define IFX_SCU_WDTS_SR_TCT_LEN (7u)
+
+/** \brief Mask for Ifx_SCU_WDTS_SR_Bits.TCT */
+#define IFX_SCU_WDTS_SR_TCT_MSK (0x7fu)
+
+/** \brief Offset for Ifx_SCU_WDTS_SR_Bits.TCT */
+#define IFX_SCU_WDTS_SR_TCT_OFF (9u)
+
+/** \brief Length for Ifx_SCU_WDTS_SR_Bits.TIM */
+#define IFX_SCU_WDTS_SR_TIM_LEN (16u)
+
+/** \brief Mask for Ifx_SCU_WDTS_SR_Bits.TIM */
+#define IFX_SCU_WDTS_SR_TIM_MSK (0xffffu)
+
+/** \brief Offset for Ifx_SCU_WDTS_SR_Bits.TIM */
+#define IFX_SCU_WDTS_SR_TIM_OFF (16u)
+
+/** \brief Length for Ifx_SCU_WDTS_SR_Bits.TO */
+#define IFX_SCU_WDTS_SR_TO_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTS_SR_Bits.TO */
+#define IFX_SCU_WDTS_SR_TO_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTS_SR_Bits.TO */
+#define IFX_SCU_WDTS_SR_TO_OFF (4u)
+
+/** \brief Length for Ifx_SCU_WDTS_SR_Bits.US */
+#define IFX_SCU_WDTS_SR_US_LEN (1u)
+
+/** \brief Mask for Ifx_SCU_WDTS_SR_Bits.US */
+#define IFX_SCU_WDTS_SR_US_MSK (0x1u)
+
+/** \brief Offset for Ifx_SCU_WDTS_SR_Bits.US */
+#define IFX_SCU_WDTS_SR_US_OFF (6u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXSCU_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxScu_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxScu_reg.h
new file mode 100644
index 0000000..7389598
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxScu_reg.h
@@ -0,0 +1,405 @@
+/**
+ * \file IfxScu_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Scu_Cfg Scu address
+ * \ingroup IfxLld_Scu
+ *
+ * \defgroup IfxLld_Scu_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Scu_Cfg
+ *
+ * \defgroup IfxLld_Scu_Cfg_Scu 2-SCU
+ * \ingroup IfxLld_Scu_Cfg
+ *
+ */
+#ifndef IFXSCU_REG_H
+#define IFXSCU_REG_H 1
+/******************************************************************************/
+#include "IfxScu_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Scu_Cfg_BaseAddress
+ * \{ */
+
+/** \brief SCU object */
+#define MODULE_SCU /*lint --e(923)*/ (*(Ifx_SCU*)0xF0036000u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Scu_Cfg_Scu
+ * \{ */
+
+/** \brief 3FC, Access Enable Register 0 */
+#define SCU_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_SCU_ACCEN0*)0xF00363FCu)
+
+/** \brief 3F8, Access Enable Register 1 */
+#define SCU_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_SCU_ACCEN1*)0xF00363F8u)
+
+/** \brief 5C, Application Reset Disable Register */
+#define SCU_ARSTDIS /*lint --e(923)*/ (*(volatile Ifx_SCU_ARSTDIS*)0xF003605Cu)
+
+/** \brief 30, CCU Clock Control Register 0 */
+#define SCU_CCUCON0 /*lint --e(923)*/ (*(volatile Ifx_SCU_CCUCON0*)0xF0036030u)
+
+/** \brief 34, CCU Clock Control Register 1 */
+#define SCU_CCUCON1 /*lint --e(923)*/ (*(volatile Ifx_SCU_CCUCON1*)0xF0036034u)
+
+/** \brief 40, CCU Clock Control Register 2 */
+#define SCU_CCUCON2 /*lint --e(923)*/ (*(volatile Ifx_SCU_CCUCON2*)0xF0036040u)
+
+/** \brief 44, CCU Clock Control Register 3 */
+#define SCU_CCUCON3 /*lint --e(923)*/ (*(volatile Ifx_SCU_CCUCON3*)0xF0036044u)
+
+/** \brief 48, CCU Clock Control Register 4 */
+#define SCU_CCUCON4 /*lint --e(923)*/ (*(volatile Ifx_SCU_CCUCON4*)0xF0036048u)
+
+/** \brief 4C, CCU Clock Control Register 5 */
+#define SCU_CCUCON5 /*lint --e(923)*/ (*(volatile Ifx_SCU_CCUCON5*)0xF003604Cu)
+
+/** \brief 80, CCU Clock Control Register 6 */
+#define SCU_CCUCON6 /*lint --e(923)*/ (*(volatile Ifx_SCU_CCUCON6*)0xF0036080u)
+
+/** \brief 84, CCU Clock Control Register 7 */
+#define SCU_CCUCON7 /*lint --e(923)*/ (*(volatile Ifx_SCU_CCUCON7*)0xF0036084u)
+
+/** \brief 140, Chip Identification Register */
+#define SCU_CHIPID /*lint --e(923)*/ (*(volatile Ifx_SCU_CHIPID*)0xF0036140u)
+
+/** \brief E4, Die Temperature Sensor Control Register */
+#define SCU_DTSCON /*lint --e(923)*/ (*(volatile Ifx_SCU_DTSCON*)0xF00360E4u)
+
+/** \brief 240, Die Temperature Sensor Limit Register */
+#define SCU_DTSLIM /*lint --e(923)*/ (*(volatile Ifx_SCU_DTSLIM*)0xF0036240u)
+
+/** \brief E0, Die Temperature Sensor Status Register */
+#define SCU_DTSSTAT /*lint --e(923)*/ (*(volatile Ifx_SCU_DTSSTAT*)0xF00360E0u)
+
+/** \brief 210, External Input Channel Register */
+#define SCU_EICR0 /*lint --e(923)*/ (*(volatile Ifx_SCU_EICR*)0xF0036210u)
+
+/** \brief 214, External Input Channel Register */
+#define SCU_EICR1 /*lint --e(923)*/ (*(volatile Ifx_SCU_EICR*)0xF0036214u)
+
+/** \brief 218, External Input Channel Register */
+#define SCU_EICR2 /*lint --e(923)*/ (*(volatile Ifx_SCU_EICR*)0xF0036218u)
+
+/** \brief 21C, External Input Channel Register */
+#define SCU_EICR3 /*lint --e(923)*/ (*(volatile Ifx_SCU_EICR*)0xF003621Cu)
+
+/** \brief 220, External Input Flag Register */
+#define SCU_EIFR /*lint --e(923)*/ (*(volatile Ifx_SCU_EIFR*)0xF0036220u)
+
+/** \brief FC, Emergency Stop Register */
+#define SCU_EMSR /*lint --e(923)*/ (*(volatile Ifx_SCU_EMSR*)0xF00360FCu)
+
+/** \brief 70, ESR Input Configuration Register */
+#define SCU_ESRCFG0 /*lint --e(923)*/ (*(volatile Ifx_SCU_ESRCFG*)0xF0036070u)
+
+/** \brief 74, ESR Input Configuration Register */
+#define SCU_ESRCFG1 /*lint --e(923)*/ (*(volatile Ifx_SCU_ESRCFG*)0xF0036074u)
+
+/** \brief 78, ESR Output Configuration Register */
+#define SCU_ESROCFG /*lint --e(923)*/ (*(volatile Ifx_SCU_ESROCFG*)0xF0036078u)
+
+/** \brief B8, EVR13 Control Register */
+#define SCU_EVR13CON /*lint --e(923)*/ (*(volatile Ifx_SCU_EVR13CON*)0xF00360B8u)
+
+/** \brief BC, EVR33 Control Register */
+#define SCU_EVR33CON /*lint --e(923)*/ (*(volatile Ifx_SCU_EVR33CON*)0xF00360BCu)
+
+/** \brief 19C, EVR ADC Status Register */
+#define SCU_EVRADCSTAT /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRADCSTAT*)0xF003619Cu)
+
+/** \brief B4, EVR Status Register for Voltage Scaling */
+#define SCU_EVRDVSTAT /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRDVSTAT*)0xF00360B4u)
+
+/** \brief 1A8, EVR Monitor Control Register */
+#define SCU_EVRMONCTRL /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRMONCTRL*)0xF00361A8u)
+
+/** \brief 1D8, EVR Oscillator & Bandgap Register */
+#define SCU_EVROSCCTRL /*lint --e(923)*/ (*(volatile Ifx_SCU_EVROSCCTRL*)0xF00361D8u)
+
+/** \brief 1A4, EVR Over-voltage Configuration Register */
+#define SCU_EVROVMON /*lint --e(923)*/ (*(volatile Ifx_SCU_EVROVMON*)0xF00361A4u)
+
+/** \brief 6C, EVR Reset Control Register */
+#define SCU_EVRRSTCON /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRRSTCON*)0xF003606Cu)
+
+/** \brief 1C0, EVR13 SD Coefficient Register 1 */
+#define SCU_EVRSDCOEFF1 /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRSDCOEFF1*)0xF00361C0u)
+
+/** \brief 1C4, EVR13 SD Coefficient Register 2 */
+#define SCU_EVRSDCOEFF2 /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRSDCOEFF2*)0xF00361C4u)
+
+/** \brief 1C8, EVR13 SD Coefficient Register 3 */
+#define SCU_EVRSDCOEFF3 /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRSDCOEFF3*)0xF00361C8u)
+
+/** \brief 1CC, EVR13 SD Coefficient Register 4 */
+#define SCU_EVRSDCOEFF4 /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRSDCOEFF4*)0xF00361CCu)
+
+/** \brief 1D0, EVR13 SD Coefficient Register 5 */
+#define SCU_EVRSDCOEFF5 /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRSDCOEFF5*)0xF00361D0u)
+
+/** \brief 1D4, EVR13 SD Coefficient Register 6 */
+#define SCU_EVRSDCOEFF6 /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRSDCOEFF6*)0xF00361D4u)
+
+/** \brief 1B0, EVR13 SD Control Register 1 */
+#define SCU_EVRSDCTRL1 /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRSDCTRL1*)0xF00361B0u)
+
+/** \brief 1B4, EVR13 SD Control Register 2 */
+#define SCU_EVRSDCTRL2 /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRSDCTRL2*)0xF00361B4u)
+
+/** \brief 1B8, EVR13 SD Control Register 3 */
+#define SCU_EVRSDCTRL3 /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRSDCTRL3*)0xF00361B8u)
+
+/** \brief 1BC, EVR13 SD Control Register 4 */
+#define SCU_EVRSDCTRL4 /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRSDCTRL4*)0xF00361BCu)
+
+/** \brief B0, EVR Status Register */
+#define SCU_EVRSTAT /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRSTAT*)0xF00360B0u)
+
+/** \brief 198, EVR Trim Register */
+#define SCU_EVRTRIM /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRTRIM*)0xF0036198u)
+
+/** \brief 1A0, EVR Under-voltage Configuration Register */
+#define SCU_EVRUVMON /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRUVMON*)0xF00361A0u)
+
+/** \brief 3C, External Clock Control Register */
+#define SCU_EXTCON /*lint --e(923)*/ (*(volatile Ifx_SCU_EXTCON*)0xF003603Cu)
+
+/** \brief 38, Fractional Divider Register */
+#define SCU_FDR /*lint --e(923)*/ (*(volatile Ifx_SCU_FDR*)0xF0036038u)
+
+/** \brief 224, Flag Modification Register */
+#define SCU_FMR /*lint --e(923)*/ (*(volatile Ifx_SCU_FMR*)0xF0036224u)
+
+/** \brief 8, Identification Register */
+#define SCU_ID /*lint --e(923)*/ (*(volatile Ifx_SCU_ID*)0xF0036008u)
+
+/** \brief 22C, Flag Gating Register */
+#define SCU_IGCR0 /*lint --e(923)*/ (*(volatile Ifx_SCU_IGCR*)0xF003622Cu)
+
+/** \brief 230, Flag Gating Register */
+#define SCU_IGCR1 /*lint --e(923)*/ (*(volatile Ifx_SCU_IGCR*)0xF0036230u)
+
+/** \brief 234, Flag Gating Register */
+#define SCU_IGCR2 /*lint --e(923)*/ (*(volatile Ifx_SCU_IGCR*)0xF0036234u)
+
+/** \brief 238, Flag Gating Register */
+#define SCU_IGCR3 /*lint --e(923)*/ (*(volatile Ifx_SCU_IGCR*)0xF0036238u)
+
+/** \brief AC, ESR Input Register */
+#define SCU_IN /*lint --e(923)*/ (*(volatile Ifx_SCU_IN*)0xF00360ACu)
+
+/** \brief A0, Input/Output Control Register */
+#define SCU_IOCR /*lint --e(923)*/ (*(volatile Ifx_SCU_IOCR*)0xF00360A0u)
+
+/** \brief 164, Logic BIST Control 0 Register */
+#define SCU_LBISTCTRL0 /*lint --e(923)*/ (*(volatile Ifx_SCU_LBISTCTRL0*)0xF0036164u)
+
+/** \brief 168, Logic BIST Control 1 Register */
+#define SCU_LBISTCTRL1 /*lint --e(923)*/ (*(volatile Ifx_SCU_LBISTCTRL1*)0xF0036168u)
+
+/** \brief 16C, Logic BIST Control 2 Register */
+#define SCU_LBISTCTRL2 /*lint --e(923)*/ (*(volatile Ifx_SCU_LBISTCTRL2*)0xF003616Cu)
+
+/** \brief 138, LCL CPU1 Control Register */
+#define SCU_LCLCON1 /*lint --e(923)*/ (*(volatile Ifx_SCU_LCLCON*)0xF0036138u)
+
+/** \brief 13C, LCL Test Register */
+#define SCU_LCLTEST /*lint --e(923)*/ (*(volatile Ifx_SCU_LCLTEST*)0xF003613Cu)
+
+/** \brief 144, Manufacturer Identification Register */
+#define SCU_MANID /*lint --e(923)*/ (*(volatile Ifx_SCU_MANID*)0xF0036144u)
+
+/** \brief A8, ESR Output Modification Register */
+#define SCU_OMR /*lint --e(923)*/ (*(volatile Ifx_SCU_OMR*)0xF00360A8u)
+
+/** \brief 10, OSC Control Register */
+#define SCU_OSCCON /*lint --e(923)*/ (*(volatile Ifx_SCU_OSCCON*)0xF0036010u)
+
+/** \brief A4, ESR Output Register */
+#define SCU_OUT /*lint --e(923)*/ (*(volatile Ifx_SCU_OUT*)0xF00360A4u)
+
+/** \brief 1E4, Overlay Control Register */
+#define SCU_OVCCON /*lint --e(923)*/ (*(volatile Ifx_SCU_OVCCON*)0xF00361E4u)
+
+/** \brief 1E0, Overlay Enable Register */
+#define SCU_OVCENABLE /*lint --e(923)*/ (*(volatile Ifx_SCU_OVCENABLE*)0xF00361E0u)
+
+/** \brief 18C, Pad Disable Control Register */
+#define SCU_PDISC /*lint --e(923)*/ (*(volatile Ifx_SCU_PDISC*)0xF003618Cu)
+
+/** \brief 9C, ESR Pad Driver Mode Register */
+#define SCU_PDR /*lint --e(923)*/ (*(volatile Ifx_SCU_PDR*)0xF003609Cu)
+
+/** \brief 228, Pattern Detection Result Register */
+#define SCU_PDRR /*lint --e(923)*/ (*(volatile Ifx_SCU_PDRR*)0xF0036228u)
+
+/** \brief 18, PLL Configuration 0 Register */
+#define SCU_PLLCON0 /*lint --e(923)*/ (*(volatile Ifx_SCU_PLLCON0*)0xF0036018u)
+
+/** \brief 1C, PLL Configuration 1 Register */
+#define SCU_PLLCON1 /*lint --e(923)*/ (*(volatile Ifx_SCU_PLLCON1*)0xF003601Cu)
+
+/** \brief 20, PLL Configuration 2 Register */
+#define SCU_PLLCON2 /*lint --e(923)*/ (*(volatile Ifx_SCU_PLLCON2*)0xF0036020u)
+
+/** \brief 28, PLL_ERAY Configuration 0 Register */
+#define SCU_PLLERAYCON0 /*lint --e(923)*/ (*(volatile Ifx_SCU_PLLERAYCON0*)0xF0036028u)
+
+/** \brief 2C, PLL_ERAY Configuration 1 Register */
+#define SCU_PLLERAYCON1 /*lint --e(923)*/ (*(volatile Ifx_SCU_PLLERAYCON1*)0xF003602Cu)
+
+/** \brief 24, PLL_ERAY Status Register */
+#define SCU_PLLERAYSTAT /*lint --e(923)*/ (*(volatile Ifx_SCU_PLLERAYSTAT*)0xF0036024u)
+
+/** \brief 14, PLL Status Register */
+#define SCU_PLLSTAT /*lint --e(923)*/ (*(volatile Ifx_SCU_PLLSTAT*)0xF0036014u)
+
+/** \brief D4, Power Management Control and Status Register */
+#define SCU_PMCSR0 /*lint --e(923)*/ (*(volatile Ifx_SCU_PMCSR*)0xF00360D4u)
+
+/** \brief D8, Power Management Control and Status Register */
+#define SCU_PMCSR1 /*lint --e(923)*/ (*(volatile Ifx_SCU_PMCSR*)0xF00360D8u)
+
+/** \brief C8, Standby and Wake-up Control Register 0 */
+#define SCU_PMSWCR0 /*lint --e(923)*/ (*(volatile Ifx_SCU_PMSWCR0*)0xF00360C8u)
+
+/** \brief E8, Standby and Wake-up Control Register 1 */
+#define SCU_PMSWCR1 /*lint --e(923)*/ (*(volatile Ifx_SCU_PMSWCR1*)0xF00360E8u)
+
+/** \brief EC, Standby and Wake-up Control Register 2 */
+#define SCU_PMSWCR2 /*lint --e(923)*/ (*(volatile Ifx_SCU_PMSWCR2*)0xF00360ECu)
+
+/** \brief CC, Standby and Wake-up Status Flag Register */
+#define SCU_PMSWSTAT /*lint --e(923)*/ (*(volatile Ifx_SCU_PMSWSTAT*)0xF00360CCu)
+
+/** \brief D0, Standby and Wake-up Status Clear Register */
+#define SCU_PMSWSTATCLR /*lint --e(923)*/ (*(volatile Ifx_SCU_PMSWSTATCLR*)0xF00360D0u)
+
+/** \brief 58, Reset Configuration Register */
+#define SCU_RSTCON /*lint --e(923)*/ (*(volatile Ifx_SCU_RSTCON*)0xF0036058u)
+
+/** \brief 64, Additional Reset Control Register */
+#define SCU_RSTCON2 /*lint --e(923)*/ (*(volatile Ifx_SCU_RSTCON2*)0xF0036064u)
+
+/** \brief 50, Reset Status Register */
+#define SCU_RSTSTAT /*lint --e(923)*/ (*(volatile Ifx_SCU_RSTSTAT*)0xF0036050u)
+
+/** \brief 150, Safety Heartbeat Register */
+#define SCU_SAFECON /*lint --e(923)*/ (*(volatile Ifx_SCU_SAFECON*)0xF0036150u)
+
+/** \brief C0, Start-up Status Register */
+#define SCU_STSTAT /*lint --e(923)*/ (*(volatile Ifx_SCU_STSTAT*)0xF00360C0u)
+
+/** \brief 60, Software Reset Configuration Register */
+#define SCU_SWRSTCON /*lint --e(923)*/ (*(volatile Ifx_SCU_SWRSTCON*)0xF0036060u)
+
+/** \brief 7C, System Control Register */
+#define SCU_SYSCON /*lint --e(923)*/ (*(volatile Ifx_SCU_SYSCON*)0xF003607Cu)
+
+/** \brief 12C, Trap Clear Register */
+#define SCU_TRAPCLR /*lint --e(923)*/ (*(volatile Ifx_SCU_TRAPCLR*)0xF003612Cu)
+
+/** \brief 130, Trap Disable Register */
+#define SCU_TRAPDIS /*lint --e(923)*/ (*(volatile Ifx_SCU_TRAPDIS*)0xF0036130u)
+
+/** \brief 128, Trap Set Register */
+#define SCU_TRAPSET /*lint --e(923)*/ (*(volatile Ifx_SCU_TRAPSET*)0xF0036128u)
+
+/** \brief 124, Trap Status Register */
+#define SCU_TRAPSTAT /*lint --e(923)*/ (*(volatile Ifx_SCU_TRAPSTAT*)0xF0036124u)
+
+/** \brief 100, CPU WDT Control Register 0 */
+#define SCU_WDTCPU0_CON0 /*lint --e(923)*/ (*(volatile Ifx_SCU_WDTCPU_CON0*)0xF0036100u)
+
+/** Alias (User Manual Name) for SCU_WDTCPU0_CON0.
+* To use register names with standard convension, please use SCU_WDTCPU0_CON0.
+*/
+#define SCU_WDTCPU0CON0 (SCU_WDTCPU0_CON0)
+
+/** \brief 104, CPU WDT Control Register 1 */
+#define SCU_WDTCPU0_CON1 /*lint --e(923)*/ (*(volatile Ifx_SCU_WDTCPU_CON1*)0xF0036104u)
+
+/** Alias (User Manual Name) for SCU_WDTCPU0_CON1.
+* To use register names with standard convension, please use SCU_WDTCPU0_CON1.
+*/
+#define SCU_WDTCPU0CON1 (SCU_WDTCPU0_CON1)
+
+/** \brief 108, CPU WDT Status Register */
+#define SCU_WDTCPU0_SR /*lint --e(923)*/ (*(volatile Ifx_SCU_WDTCPU_SR*)0xF0036108u)
+
+/** Alias (User Manual Name) for SCU_WDTCPU0_SR.
+* To use register names with standard convension, please use SCU_WDTCPU0_SR.
+*/
+#define SCU_WDTCPU0SR (SCU_WDTCPU0_SR)
+
+/** \brief 10C, CPU WDT Control Register 0 */
+#define SCU_WDTCPU1_CON0 /*lint --e(923)*/ (*(volatile Ifx_SCU_WDTCPU_CON0*)0xF003610Cu)
+
+/** Alias (User Manual Name) for SCU_WDTCPU1_CON0.
+* To use register names with standard convension, please use SCU_WDTCPU1_CON0.
+*/
+#define SCU_WDTCPU1CON0 (SCU_WDTCPU1_CON0)
+
+/** \brief 110, CPU WDT Control Register 1 */
+#define SCU_WDTCPU1_CON1 /*lint --e(923)*/ (*(volatile Ifx_SCU_WDTCPU_CON1*)0xF0036110u)
+
+/** Alias (User Manual Name) for SCU_WDTCPU1_CON1.
+* To use register names with standard convension, please use SCU_WDTCPU1_CON1.
+*/
+#define SCU_WDTCPU1CON1 (SCU_WDTCPU1_CON1)
+
+/** \brief 114, CPU WDT Status Register */
+#define SCU_WDTCPU1_SR /*lint --e(923)*/ (*(volatile Ifx_SCU_WDTCPU_SR*)0xF0036114u)
+
+/** Alias (User Manual Name) for SCU_WDTCPU1_SR.
+* To use register names with standard convension, please use SCU_WDTCPU1_SR.
+*/
+#define SCU_WDTCPU1SR (SCU_WDTCPU1_SR)
+
+/** \brief F0, Safety WDT Control Register 0 */
+#define SCU_WDTS_CON0 /*lint --e(923)*/ (*(volatile Ifx_SCU_WDTS_CON0*)0xF00360F0u)
+
+/** Alias (User Manual Name) for SCU_WDTS_CON0.
+* To use register names with standard convension, please use SCU_WDTS_CON0.
+*/
+#define SCU_WDTSCON0 (SCU_WDTS_CON0)
+
+/** \brief F4, Safety WDT Control Register 1 */
+#define SCU_WDTS_CON1 /*lint --e(923)*/ (*(volatile Ifx_SCU_WDTS_CON1*)0xF00360F4u)
+
+/** Alias (User Manual Name) for SCU_WDTS_CON1.
+* To use register names with standard convension, please use SCU_WDTS_CON1.
+*/
+#define SCU_WDTSCON1 (SCU_WDTS_CON1)
+
+/** \brief F8, Safety WDT Status Register */
+#define SCU_WDTS_SR /*lint --e(923)*/ (*(volatile Ifx_SCU_WDTS_SR*)0xF00360F8u)
+
+/** Alias (User Manual Name) for SCU_WDTS_SR.
+* To use register names with standard convension, please use SCU_WDTS_SR.
+*/
+#define SCU_WDTSSR (SCU_WDTS_SR)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXSCU_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxScu_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxScu_regdef.h
new file mode 100644
index 0000000..9eeeeda
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxScu_regdef.h
@@ -0,0 +1,2107 @@
+/**
+ * \file IfxScu_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Scu Scu
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Scu_Bitfields Bitfields
+ * \ingroup IfxLld_Scu
+ *
+ * \defgroup IfxLld_Scu_union Union
+ * \ingroup IfxLld_Scu
+ *
+ * \defgroup IfxLld_Scu_struct Struct
+ * \ingroup IfxLld_Scu
+ *
+ */
+#ifndef IFXSCU_REGDEF_H
+#define IFXSCU_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Scu_Bitfields
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef struct _Ifx_SCU_ACCEN0_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_SCU_ACCEN0_Bits;
+
+/** \brief Access Enable Register 1 */
+typedef struct _Ifx_SCU_ACCEN1_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_SCU_ACCEN1_Bits;
+
+/** \brief Application Reset Disable Register */
+typedef struct _Ifx_SCU_ARSTDIS_Bits
+{
+ unsigned int STM0DIS:1; /**< \brief [0:0] STM0 Disable Reset (rw) */
+ unsigned int STM1DIS:1; /**< \brief [1:1] STM1 Disable Reset (If Product has STM1) (rw) */
+ unsigned int STM2DIS:1; /**< \brief [2:2] STM2 Disable Reset (If Product has STM2) (rw) */
+ unsigned int reserved_3:29; /**< \brief \internal Reserved */
+} Ifx_SCU_ARSTDIS_Bits;
+
+/** \brief CCU Clock Control Register 0 */
+typedef struct _Ifx_SCU_CCUCON0_Bits
+{
+ unsigned int BAUD1DIV:4; /**< \brief [3:0] Baud1 Divider Reload Value (rw) */
+ unsigned int BAUD2DIV:4; /**< \brief [7:4] Baud2 Divider Reload Value (rw) */
+ unsigned int SRIDIV:4; /**< \brief [11:8] SRI Divider Reload Value (rw) */
+ unsigned int LPDIV:4; /**< \brief [15:12] Low Power Divider Reload Value (rw) */
+ unsigned int SPBDIV:4; /**< \brief [19:16] SPB Divider Reload Value (rw) */
+ unsigned int FSI2DIV:2; /**< \brief [21:20] FSI2 Divider Reload Value (rw) */
+ unsigned int reserved_22:2; /**< \brief \internal Reserved */
+ unsigned int FSIDIV:2; /**< \brief [25:24] FSI Divider Reload Value (rw) */
+ unsigned int reserved_26:2; /**< \brief \internal Reserved */
+ unsigned int CLKSEL:2; /**< \brief [29:28] Clock Selection (rw) */
+ unsigned int UP:1; /**< \brief [30:30] Update Request (w) */
+ unsigned int LCK:1; /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_CCUCON0_Bits;
+
+/** \brief CCU Clock Control Register 1 */
+typedef struct _Ifx_SCU_CCUCON1_Bits
+{
+ unsigned int CANDIV:4; /**< \brief [3:0] MultiCAN Divider Reload Value (rw) */
+ unsigned int ERAYDIV:4; /**< \brief [7:4] ERAY Divider Reload Value (rw) */
+ unsigned int STMDIV:4; /**< \brief [11:8] STM Divider Reload Value (rw) */
+ unsigned int GTMDIV:4; /**< \brief [15:12] GTM Divider Reload Value (rw) */
+ unsigned int ETHDIV:4; /**< \brief [19:16] Ethernet Divider Reload Value (rw) */
+ unsigned int ASCLINFDIV:4; /**< \brief [23:20] ASCLIN Fast Divider Reload Value (rw) */
+ unsigned int ASCLINSDIV:4; /**< \brief [27:24] ASCLIN Slow Divider Reload Value (rw) */
+ unsigned int INSEL:2; /**< \brief [29:28] Input Selection (rw) */
+ unsigned int UP:1; /**< \brief [30:30] Update Request (w) */
+ unsigned int LCK:1; /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_CCUCON1_Bits;
+
+/** \brief CCU Clock Control Register 2 */
+typedef struct _Ifx_SCU_CCUCON2_Bits
+{
+ unsigned int BBBDIV:4; /**< \brief [3:0] BBB Divider Reload Value (rw) */
+ unsigned int reserved_4:26; /**< \brief \internal Reserved */
+ unsigned int UP:1; /**< \brief [30:30] Update Request (w) */
+ unsigned int LCK:1; /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_CCUCON2_Bits;
+
+/** \brief CCU Clock Control Register 3 */
+typedef struct _Ifx_SCU_CCUCON3_Bits
+{
+ unsigned int PLLDIV:6; /**< \brief [5:0] PLL Divider Value (rw) */
+ unsigned int PLLSEL:2; /**< \brief [7:6] PLL Target Monitoring Frequency Selection (rw) */
+ unsigned int PLLERAYDIV:6; /**< \brief [13:8] PLL_ERAY Divider Value (rw) */
+ unsigned int PLLERAYSEL:2; /**< \brief [15:14] PLL_ERAY Target Monitoring Frequency Selection (rw) */
+ unsigned int SRIDIV:6; /**< \brief [21:16] SRI Divider Value (rw) */
+ unsigned int SRISEL:2; /**< \brief [23:22] SRI Target Monitoring Frequency Selection (rw) */
+ unsigned int reserved_24:5; /**< \brief \internal Reserved */
+ unsigned int SLCK:1; /**< \brief [29:29] Security Lock (r) */
+ unsigned int UP:1; /**< \brief [30:30] Update Request (w) */
+ unsigned int LCK:1; /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_CCUCON3_Bits;
+
+/** \brief CCU Clock Control Register 4 */
+typedef struct _Ifx_SCU_CCUCON4_Bits
+{
+ unsigned int SPBDIV:6; /**< \brief [5:0] SPB Divider Value (rw) */
+ unsigned int SPBSEL:2; /**< \brief [7:6] SPB Target Monitoring Frequency Selection (rw) */
+ unsigned int GTMDIV:6; /**< \brief [13:8] GTM Divider Value (rw) */
+ unsigned int GTMSEL:2; /**< \brief [15:14] GTM Target Monitoring Frequency Selection (rw) */
+ unsigned int STMDIV:6; /**< \brief [21:16] STM Divider Value (rw) */
+ unsigned int STMSEL:2; /**< \brief [23:22] STM Target Monitoring Frequency Selection (rw) */
+ unsigned int reserved_24:5; /**< \brief \internal Reserved */
+ unsigned int SLCK:1; /**< \brief [29:29] Security Lock (rw) */
+ unsigned int UP:1; /**< \brief [30:30] Update Request (w) */
+ unsigned int LCK:1; /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_CCUCON4_Bits;
+
+/** \brief CCU Clock Control Register 5 */
+typedef struct _Ifx_SCU_CCUCON5_Bits
+{
+ unsigned int MAXDIV:4; /**< \brief [3:0] Max Divider Reload Value (rw) */
+ unsigned int reserved_4:26; /**< \brief \internal Reserved */
+ unsigned int UP:1; /**< \brief [30:30] Update Request (w) */
+ unsigned int LCK:1; /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_CCUCON5_Bits;
+
+/** \brief CCU Clock Control Register 6 */
+typedef struct _Ifx_SCU_CCUCON6_Bits
+{
+ unsigned int CPU0DIV:6; /**< \brief [5:0] CPU0 Divider Reload Value (rw) */
+ unsigned int reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_SCU_CCUCON6_Bits;
+
+/** \brief CCU Clock Control Register 7 */
+typedef struct _Ifx_SCU_CCUCON7_Bits
+{
+ unsigned int CPU1DIV:6; /**< \brief [5:0] CPU1 Divider Reload Value (rw) */
+ unsigned int reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_SCU_CCUCON7_Bits;
+
+/** \brief Chip Identification Register */
+typedef struct _Ifx_SCU_CHIPID_Bits
+{
+ unsigned int CHREV:6; /**< \brief [5:0] Chip Revision Number (r) */
+ unsigned int CHTEC:2; /**< \brief [7:6] Chip Family (r) */
+ unsigned int CHID:8; /**< \brief [15:8] Chip Identification Number (rw) */
+ unsigned int EEA:1; /**< \brief [16:16] Emulation Extension Available (rh) */
+ unsigned int UCODE:7; /**< \brief [23:17] µCode Version (rw) */
+ unsigned int FSIZE:4; /**< \brief [27:24] Program Flash Size (rw) */
+ unsigned int SP:2; /**< \brief [29:28] Speed (rw) */
+ unsigned int SEC:1; /**< \brief [30:30] Security Device (rw) */
+ unsigned int reserved_31:1; /**< \brief \internal Reserved */
+} Ifx_SCU_CHIPID_Bits;
+
+/** \brief Die Temperature Sensor Control Register */
+typedef struct _Ifx_SCU_DTSCON_Bits
+{
+ unsigned int PWD:1; /**< \brief [0:0] Sensor Power Down (rw) */
+ unsigned int START:1; /**< \brief [1:1] Sensor Measurement Start (w) */
+ unsigned int reserved_2:2; /**< \brief \internal Reserved */
+ unsigned int CAL:20; /**< \brief [23:4] Calibration Value (rw) */
+ unsigned int reserved_24:7; /**< \brief \internal Reserved */
+ unsigned int SLCK:1; /**< \brief [31:31] Security Lock (rw) */
+} Ifx_SCU_DTSCON_Bits;
+
+/** \brief Die Temperature Sensor Limit Register */
+typedef struct _Ifx_SCU_DTSLIM_Bits
+{
+ unsigned int LOWER:10; /**< \brief [9:0] Lower Limit (rw) */
+ unsigned int reserved_10:5; /**< \brief \internal Reserved */
+ unsigned int LLU:1; /**< \brief [15:15] Lower Limit Underflow (rwh) */
+ unsigned int UPPER:10; /**< \brief [25:16] Upper Limit (rw) */
+ unsigned int reserved_26:4; /**< \brief \internal Reserved */
+ unsigned int SLCK:1; /**< \brief [30:30] Security Lock (rw) */
+ unsigned int UOF:1; /**< \brief [31:31] Upper Limit Overflow (rh) */
+} Ifx_SCU_DTSLIM_Bits;
+
+/** \brief Die Temperature Sensor Status Register */
+typedef struct _Ifx_SCU_DTSSTAT_Bits
+{
+ unsigned int RESULT:10; /**< \brief [9:0] Result of the DTS Measurement (rh) */
+ unsigned int reserved_10:4; /**< \brief \internal Reserved */
+ unsigned int RDY:1; /**< \brief [14:14] Sensor Ready Status (rh) */
+ unsigned int BUSY:1; /**< \brief [15:15] Sensor Busy Status (rh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_SCU_DTSSTAT_Bits;
+
+/** \brief External Input Channel Register */
+typedef struct _Ifx_SCU_EICR_Bits
+{
+ unsigned int reserved_0:4; /**< \brief \internal Reserved */
+ unsigned int EXIS0:3; /**< \brief [6:4] External Input Selection 0 (rw) */
+ unsigned int reserved_7:1; /**< \brief \internal Reserved */
+ unsigned int FEN0:1; /**< \brief [8:8] Falling Edge Enable 0 (rw) */
+ unsigned int REN0:1; /**< \brief [9:9] Rising Edge Enable 0 (rw) */
+ unsigned int LDEN0:1; /**< \brief [10:10] Level Detection Enable 0 (rw) */
+ unsigned int EIEN0:1; /**< \brief [11:11] External Input Enable 0 (rw) */
+ unsigned int INP0:3; /**< \brief [14:12] Input Node Pointer (rw) */
+ unsigned int reserved_15:5; /**< \brief \internal Reserved */
+ unsigned int EXIS1:3; /**< \brief [22:20] External Input Selection 1 (rw) */
+ unsigned int reserved_23:1; /**< \brief \internal Reserved */
+ unsigned int FEN1:1; /**< \brief [24:24] Falling Edge Enable 1 (rw) */
+ unsigned int REN1:1; /**< \brief [25:25] Rising Edge Enable 1 (rw) */
+ unsigned int LDEN1:1; /**< \brief [26:26] Level Detection Enable 1 (rw) */
+ unsigned int EIEN1:1; /**< \brief [27:27] External Input Enable 1 (rw) */
+ unsigned int INP1:3; /**< \brief [30:28] Input Node Pointer (rw) */
+ unsigned int reserved_31:1; /**< \brief \internal Reserved */
+} Ifx_SCU_EICR_Bits;
+
+/** \brief External Input Flag Register */
+typedef struct _Ifx_SCU_EIFR_Bits
+{
+ unsigned int INTF0:1; /**< \brief [0:0] External Event Flag of Channel 0 (rh) */
+ unsigned int INTF1:1; /**< \brief [1:1] External Event Flag of Channel 1 (rh) */
+ unsigned int INTF2:1; /**< \brief [2:2] External Event Flag of Channel 2 (rh) */
+ unsigned int INTF3:1; /**< \brief [3:3] External Event Flag of Channel 3 (rh) */
+ unsigned int INTF4:1; /**< \brief [4:4] External Event Flag of Channel 4 (rh) */
+ unsigned int INTF5:1; /**< \brief [5:5] External Event Flag of Channel 5 (rh) */
+ unsigned int INTF6:1; /**< \brief [6:6] External Event Flag of Channel 6 (rh) */
+ unsigned int INTF7:1; /**< \brief [7:7] External Event Flag of Channel 7 (rh) */
+ unsigned int reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_SCU_EIFR_Bits;
+
+/** \brief Emergency Stop Register */
+typedef struct _Ifx_SCU_EMSR_Bits
+{
+ unsigned int POL:1; /**< \brief [0:0] Input Polarity (rw) */
+ unsigned int MODE:1; /**< \brief [1:1] Mode Selection (rw) */
+ unsigned int ENON:1; /**< \brief [2:2] Enable ON (rw) */
+ unsigned int PSEL:1; /**< \brief [3:3] PORT Select (rw) */
+ unsigned int reserved_4:12; /**< \brief \internal Reserved */
+ unsigned int EMSF:1; /**< \brief [16:16] Emergency Stop Flag (rh) */
+ unsigned int SEMSF:1; /**< \brief [17:17] SMU Emergency Stop Flag (rh) */
+ unsigned int reserved_18:6; /**< \brief \internal Reserved */
+ unsigned int EMSFM:2; /**< \brief [25:24] Emergency Stop Flag Modification (w) */
+ unsigned int SEMSFM:2; /**< \brief [27:26] SMU Emergency Stop Flag Modification (w) */
+ unsigned int reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_SCU_EMSR_Bits;
+
+/** \brief ESR Input Configuration Register */
+typedef struct _Ifx_SCU_ESRCFG_Bits
+{
+ unsigned int reserved_0:7; /**< \brief \internal Reserved */
+ unsigned int EDCON:2; /**< \brief [8:7] Edge Detection Control (rw) */
+ unsigned int reserved_9:23; /**< \brief \internal Reserved */
+} Ifx_SCU_ESRCFG_Bits;
+
+/** \brief ESR Output Configuration Register */
+typedef struct _Ifx_SCU_ESROCFG_Bits
+{
+ unsigned int ARI:1; /**< \brief [0:0] Application Reset Indicator (rh) */
+ unsigned int ARC:1; /**< \brief [1:1] Application Reset Indicator Clear (w) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_SCU_ESROCFG_Bits;
+
+/** \brief EVR13 Control Register */
+typedef struct _Ifx_SCU_EVR13CON_Bits
+{
+ unsigned int reserved_0:28; /**< \brief \internal Reserved */
+ unsigned int EVR13OFF:1; /**< \brief [28:28] EVR13 Regulator Enable (rw) */
+ unsigned int BPEVR13OFF:1; /**< \brief [29:29] Bit Protection EVR13OFF (w) */
+ unsigned int reserved_30:1; /**< \brief \internal Reserved */
+ unsigned int LCK:1; /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_EVR13CON_Bits;
+
+/** \brief EVR33 Control Register */
+typedef struct _Ifx_SCU_EVR33CON_Bits
+{
+ unsigned int reserved_0:28; /**< \brief \internal Reserved */
+ unsigned int EVR33OFF:1; /**< \brief [28:28] EVR33 Regulator Enable (rw) */
+ unsigned int BPEVR33OFF:1; /**< \brief [29:29] Bit Protection EVR33OFF (w) */
+ unsigned int reserved_30:1; /**< \brief \internal Reserved */
+ unsigned int LCK:1; /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_EVR33CON_Bits;
+
+/** \brief EVR ADC Status Register */
+typedef struct _Ifx_SCU_EVRADCSTAT_Bits
+{
+ unsigned int ADC13V:8; /**< \brief [7:0] ADC 1.3 V Conversion Result (rh) */
+ unsigned int ADC33V:8; /**< \brief [15:8] ADC 3.3 V Conversion Result (rh) */
+ unsigned int ADCSWDV:8; /**< \brief [23:16] ADC External Supply Conversion Result (rh) */
+ unsigned int reserved_24:7; /**< \brief \internal Reserved */
+ unsigned int VAL:1; /**< \brief [31:31] Valid Status (rh) */
+} Ifx_SCU_EVRADCSTAT_Bits;
+
+/** \brief EVR Status Register for Voltage Scaling */
+typedef struct _Ifx_SCU_EVRDVSTAT_Bits
+{
+ unsigned int DVS13TRIM:8; /**< \brief [7:0] 1.3 V Regulator Voltage Trim Status (rh) */
+ unsigned int reserved_8:8; /**< \brief \internal Reserved */
+ unsigned int DVS33TRIM:8; /**< \brief [23:16] 3.3 V Regulator Voltage Trim Status (rh) */
+ unsigned int reserved_24:7; /**< \brief \internal Reserved */
+ unsigned int VAL:1; /**< \brief [31:31] Valid Status (rh) */
+} Ifx_SCU_EVRDVSTAT_Bits;
+
+/** \brief EVR Monitor Control Register */
+typedef struct _Ifx_SCU_EVRMONCTRL_Bits
+{
+ unsigned int EVR13OVMOD:2; /**< \brief [1:0] 1.3 V Regulator Over-voltage monitoring mode (rw) */
+ unsigned int reserved_2:2; /**< \brief \internal Reserved */
+ unsigned int EVR13UVMOD:2; /**< \brief [5:4] 1.3 V Regulator Under-voltage monitoring mode (rw) */
+ unsigned int reserved_6:2; /**< \brief \internal Reserved */
+ unsigned int EVR33OVMOD:2; /**< \brief [9:8] 3.3 V Regulator Over-voltage monitoring mode (rw) */
+ unsigned int reserved_10:2; /**< \brief \internal Reserved */
+ unsigned int EVR33UVMOD:2; /**< \brief [13:12] 3.3 V Regulator Under-voltage monitoring mode (rw) */
+ unsigned int reserved_14:2; /**< \brief \internal Reserved */
+ unsigned int SWDOVMOD:2; /**< \brief [17:16] Supply monitor (SWD) Over-voltage monitoring mode (rw) */
+ unsigned int reserved_18:2; /**< \brief \internal Reserved */
+ unsigned int SWDUVMOD:2; /**< \brief [21:20] Supply monitor (SWD) Under-voltage monitoring mode (rw) */
+ unsigned int reserved_22:10; /**< \brief \internal Reserved */
+} Ifx_SCU_EVRMONCTRL_Bits;
+
+/** \brief EVR Oscillator & Bandgap Register */
+typedef struct _Ifx_SCU_EVROSCCTRL_Bits
+{
+ unsigned int OSCTRIM:10; /**< \brief [9:0] OSC Trim Value (rw) */
+ unsigned int OSCPTAT:6; /**< \brief [15:10] OSC PTAT Trim Value (rw) */
+ unsigned int OSCANASEL:4; /**< \brief [19:16] OSC ANASEL Value (rw) */
+ unsigned int HPBGTRIM:7; /**< \brief [26:20] High Precision Bandgap Trim Value (rw) */
+ unsigned int HPBGCLKEN:1; /**< \brief [27:27] High Precision Bandgap Clock Enable (rw) */
+ unsigned int OSC3V3:1; /**< \brief [28:28] Oscillator 3V3 Mode (rw) */
+ unsigned int reserved_29:2; /**< \brief \internal Reserved */
+ unsigned int LCK:1; /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_EVROSCCTRL_Bits;
+
+/** \brief EVR Over-voltage Configuration Register */
+typedef struct _Ifx_SCU_EVROVMON_Bits
+{
+ unsigned int EVR13OVVAL:8; /**< \brief [7:0] 1.3 V Regulator Over-voltage threshold (rw) */
+ unsigned int EVR33OVVAL:8; /**< \brief [15:8] 3.3 V Regulator Over-voltage threshold (rw) */
+ unsigned int SWDOVVAL:8; /**< \brief [23:16] Supply monitor (SWD) Over-voltage threshold value (rw) */
+ unsigned int reserved_24:7; /**< \brief \internal Reserved */
+ unsigned int LCK:1; /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_EVROVMON_Bits;
+
+/** \brief EVR Reset Control Register */
+typedef struct _Ifx_SCU_EVRRSTCON_Bits
+{
+ unsigned int RST13TRIM:8; /**< \brief [7:0] 1.3 V Regulator Reset Trim Value (rw) */
+ unsigned int reserved_8:16; /**< \brief \internal Reserved */
+ unsigned int RST13OFF:1; /**< \brief [24:24] EVR13 Reset Enable (rw) */
+ unsigned int BPRST13OFF:1; /**< \brief [25:25] Bit Protection RST13OFF (w) */
+ unsigned int RST33OFF:1; /**< \brief [26:26] EVR33 Reset Enable (rw) */
+ unsigned int BPRST33OFF:1; /**< \brief [27:27] Bit Protection RST33OFF (w) */
+ unsigned int RSTSWDOFF:1; /**< \brief [28:28] EVR SWD Reset Enable (rw) */
+ unsigned int BPRSTSWDOFF:1; /**< \brief [29:29] Bit Protection RSTSWDOFF (w) */
+ unsigned int reserved_30:1; /**< \brief \internal Reserved */
+ unsigned int LCK:1; /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_EVRRSTCON_Bits;
+
+/** \brief EVR13 SD Coefficient Register 1 */
+typedef struct _Ifx_SCU_EVRSDCOEFF1_Bits
+{
+ unsigned int SD5P:8; /**< \brief [7:0] P Coefficient (rw) */
+ unsigned int SD5I:8; /**< \brief [15:8] I Coefficient (rw) */
+ unsigned int SD5D:8; /**< \brief [23:16] D Coefficient (rw) */
+ unsigned int reserved_24:7; /**< \brief \internal Reserved */
+ unsigned int LCK:1; /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_EVRSDCOEFF1_Bits;
+
+/** \brief EVR13 SD Coefficient Register 2 */
+typedef struct _Ifx_SCU_EVRSDCOEFF2_Bits
+{
+ unsigned int SD33P:8; /**< \brief [7:0] P Coefficient (rw) */
+ unsigned int SD33I:8; /**< \brief [15:8] I Coefficient (rw) */
+ unsigned int SD33D:8; /**< \brief [23:16] D Coefficient (rw) */
+ unsigned int reserved_24:7; /**< \brief \internal Reserved */
+ unsigned int LCK:1; /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_EVRSDCOEFF2_Bits;
+
+/** \brief EVR13 SD Coefficient Register 3 */
+typedef struct _Ifx_SCU_EVRSDCOEFF3_Bits
+{
+ unsigned int CT5REG0:8; /**< \brief [7:0] Commutation trimming (rw) */
+ unsigned int CT5REG1:8; /**< \brief [15:8] Commutation trimming (rw) */
+ unsigned int CT5REG2:8; /**< \brief [23:16] Commutation trimming (rw) */
+ unsigned int reserved_24:7; /**< \brief \internal Reserved */
+ unsigned int LCK:1; /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_EVRSDCOEFF3_Bits;
+
+/** \brief EVR13 SD Coefficient Register 4 */
+typedef struct _Ifx_SCU_EVRSDCOEFF4_Bits
+{
+ unsigned int CT5REG3:8; /**< \brief [7:0] Commutation trimming (rw) */
+ unsigned int CT5REG4:8; /**< \brief [15:8] Commutation trimming (rw) */
+ unsigned int reserved_16:15; /**< \brief \internal Reserved */
+ unsigned int LCK:1; /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_EVRSDCOEFF4_Bits;
+
+/** \brief EVR13 SD Coefficient Register 5 */
+typedef struct _Ifx_SCU_EVRSDCOEFF5_Bits
+{
+ unsigned int CT33REG0:8; /**< \brief [7:0] Commutation trimming (rw) */
+ unsigned int CT33REG1:8; /**< \brief [15:8] Commutation trimming (rw) */
+ unsigned int CT33REG2:8; /**< \brief [23:16] Commutation trimming (rw) */
+ unsigned int reserved_24:7; /**< \brief \internal Reserved */
+ unsigned int LCK:1; /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_EVRSDCOEFF5_Bits;
+
+/** \brief EVR13 SD Coefficient Register 6 */
+typedef struct _Ifx_SCU_EVRSDCOEFF6_Bits
+{
+ unsigned int CT33REG3:8; /**< \brief [7:0] Commutation trimming (rw) */
+ unsigned int CT33REG4:8; /**< \brief [15:8] Commutation trimming (rw) */
+ unsigned int reserved_16:15; /**< \brief \internal Reserved */
+ unsigned int LCK:1; /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_EVRSDCOEFF6_Bits;
+
+/** \brief EVR13 SD Control Register 1 */
+typedef struct _Ifx_SCU_EVRSDCTRL1_Bits
+{
+ unsigned int SDFREQSPRD:16; /**< \brief [15:0] Frequency Spread Threshold (rw) */
+ unsigned int SDFREQ:8; /**< \brief [23:16] Regulator Switching Frequency (rw) */
+ unsigned int SDSTEP:4; /**< \brief [27:24] Droop Voltage Step (rw) */
+ unsigned int reserved_28:2; /**< \brief \internal Reserved */
+ unsigned int SDSAMPLE:1; /**< \brief [30:30] ADC Sampling Scheme (rw) */
+ unsigned int LCK:1; /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_EVRSDCTRL1_Bits;
+
+/** \brief EVR13 SD Control Register 2 */
+typedef struct _Ifx_SCU_EVRSDCTRL2_Bits
+{
+ unsigned int DRVP:8; /**< \brief [7:0] P-Driver Setting (rw) */
+ unsigned int SDMINMAXDC:8; /**< \brief [15:8] Minimum Duty Cycle (rw) */
+ unsigned int DRVN:8; /**< \brief [23:16] N-Driver Setting (rw) */
+ unsigned int SDLUT:6; /**< \brief [29:24] Non-linear Starting Point (rw) */
+ unsigned int reserved_30:1; /**< \brief \internal Reserved */
+ unsigned int LCK:1; /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_EVRSDCTRL2_Bits;
+
+/** \brief EVR13 SD Control Register 3 */
+typedef struct _Ifx_SCU_EVRSDCTRL3_Bits
+{
+ unsigned int SDPWMPRE:8; /**< \brief [7:0] PWM Preset Value (rw) */
+ unsigned int SDPID:8; /**< \brief [15:8] PID Control (rw) */
+ unsigned int SDVOKLVL:8; /**< \brief [23:16] Configuration of Voltage OK Signal (rw) */
+ unsigned int reserved_24:7; /**< \brief \internal Reserved */
+ unsigned int LCK:1; /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_EVRSDCTRL3_Bits;
+
+/** \brief EVR13 SD Control Register 4 */
+typedef struct _Ifx_SCU_EVRSDCTRL4_Bits
+{
+ unsigned int reserved_0:8; /**< \brief \internal Reserved */
+ unsigned int SYNCDIV:3; /**< \brief [10:8] Clock Divider Ratio for external DCDC SYNC signal (rw) */
+ unsigned int reserved_11:20; /**< \brief \internal Reserved */
+ unsigned int LCK:1; /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_EVRSDCTRL4_Bits;
+
+/** \brief EVR Status Register */
+typedef struct _Ifx_SCU_EVRSTAT_Bits
+{
+ unsigned int EVR13:1; /**< \brief [0:0] EVR13 status (rh) */
+ unsigned int OV13:1; /**< \brief [1:1] EVR13 Regulator Over-voltage event flag (rh) */
+ unsigned int EVR33:1; /**< \brief [2:2] EVR33 status (rh) */
+ unsigned int OV33:1; /**< \brief [3:3] EVR33 Regulator Over-voltage event flag (rh) */
+ unsigned int OVSWD:1; /**< \brief [4:4] Supply Watchdog (SWD) Over-voltage event flag (rh) */
+ unsigned int UV13:1; /**< \brief [5:5] EVR13 Regulator Under-voltage event flag (rh) */
+ unsigned int UV33:1; /**< \brief [6:6] EVR33 Regulator Under-voltage event flag (rh) */
+ unsigned int UVSWD:1; /**< \brief [7:7] Supply Watchdog (SWD) Under-voltage event flag (rh) */
+ unsigned int EXTPASS13:1; /**< \brief [8:8] External Pass Device for EVR13 (rh) */
+ unsigned int EXTPASS33:1; /**< \brief [9:9] External Pass Device for EVR33 (rh) */
+ unsigned int BGPROK:1; /**< \brief [10:10] Primary Bandgap status (rh) */
+ unsigned int reserved_11:21; /**< \brief \internal Reserved */
+} Ifx_SCU_EVRSTAT_Bits;
+
+/** \brief EVR Trim Register */
+typedef struct _Ifx_SCU_EVRTRIM_Bits
+{
+ unsigned int EVR13TRIM:8; /**< \brief [7:0] 1.3 V Regulator Voltage Trim Value (rw) */
+ unsigned int SDVOUTSEL:8; /**< \brief [15:8] SD Regulator Voltage selection (rw) */
+ unsigned int reserved_16:15; /**< \brief \internal Reserved */
+ unsigned int LCK:1; /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_EVRTRIM_Bits;
+
+/** \brief EVR Under-voltage Configuration Register */
+typedef struct _Ifx_SCU_EVRUVMON_Bits
+{
+ unsigned int EVR13UVVAL:8; /**< \brief [7:0] 1.3 V Regulator Under-voltage threshold (rw) */
+ unsigned int EVR33UVVAL:8; /**< \brief [15:8] 3.3 V Regulator Under-voltage threshold (rw) */
+ unsigned int SWDUVVAL:8; /**< \brief [23:16] Supply monitor (SWD) Under-voltage threshold value (rw) */
+ unsigned int reserved_24:7; /**< \brief \internal Reserved */
+ unsigned int LCK:1; /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_EVRUVMON_Bits;
+
+/** \brief External Clock Control Register */
+typedef struct _Ifx_SCU_EXTCON_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] External Clock Enable for EXTCLK0 (rw) */
+ unsigned int reserved_1:1; /**< \brief \internal Reserved */
+ unsigned int SEL0:4; /**< \brief [5:2] External Clock Select for EXTCLK0 (rw) */
+ unsigned int reserved_6:10; /**< \brief \internal Reserved */
+ unsigned int EN1:1; /**< \brief [16:16] External Clock Enable for EXTCLK1 (rw) */
+ unsigned int NSEL:1; /**< \brief [17:17] Negation Selection (rw) */
+ unsigned int SEL1:4; /**< \brief [21:18] External Clock Select for EXTCLK1 (rw) */
+ unsigned int reserved_22:2; /**< \brief \internal Reserved */
+ unsigned int DIV1:8; /**< \brief [31:24] External Clock Divider for EXTCLK1 (rw) */
+} Ifx_SCU_EXTCON_Bits;
+
+/** \brief Fractional Divider Register */
+typedef struct _Ifx_SCU_FDR_Bits
+{
+ unsigned int STEP:10; /**< \brief [9:0] Step Value (rw) */
+ unsigned int reserved_10:4; /**< \brief \internal Reserved */
+ unsigned int DM:2; /**< \brief [15:14] Divider Mode (rw) */
+ unsigned int RESULT:10; /**< \brief [25:16] Result Value (rh) */
+ unsigned int reserved_26:5; /**< \brief \internal Reserved */
+ unsigned int DISCLK:1; /**< \brief [31:31] Disable Clock (rwh) */
+} Ifx_SCU_FDR_Bits;
+
+/** \brief Flag Modification Register */
+typedef struct _Ifx_SCU_FMR_Bits
+{
+ unsigned int FS0:1; /**< \brief [0:0] Set Flag INTF0 for Channel 0 (w) */
+ unsigned int FS1:1; /**< \brief [1:1] Set Flag INTF1 for Channel 1 (w) */
+ unsigned int FS2:1; /**< \brief [2:2] Set Flag INTF2 for Channel 2 (w) */
+ unsigned int FS3:1; /**< \brief [3:3] Set Flag INTF3 for Channel 3 (w) */
+ unsigned int FS4:1; /**< \brief [4:4] Set Flag INTF4 for Channel 4 (w) */
+ unsigned int FS5:1; /**< \brief [5:5] Set Flag INTF5 for Channel 5 (w) */
+ unsigned int FS6:1; /**< \brief [6:6] Set Flag INTF6 for Channel 6 (w) */
+ unsigned int FS7:1; /**< \brief [7:7] Set Flag INTF7 for Channel 7 (w) */
+ unsigned int reserved_8:8; /**< \brief \internal Reserved */
+ unsigned int FC0:1; /**< \brief [16:16] Clear Flag INTF0 for Channel 0 (w) */
+ unsigned int FC1:1; /**< \brief [17:17] Clear Flag INTF1 for Channel 1 (w) */
+ unsigned int FC2:1; /**< \brief [18:18] Clear Flag INTF2 for Channel 2 (w) */
+ unsigned int FC3:1; /**< \brief [19:19] Clear Flag INTF3 for Channel 3 (w) */
+ unsigned int FC4:1; /**< \brief [20:20] Clear Flag INTF4 for Channel 4 (w) */
+ unsigned int FC5:1; /**< \brief [21:21] Clear Flag INTF5 for Channel 5 (w) */
+ unsigned int FC6:1; /**< \brief [22:22] Clear Flag INTF6 for Channel 6 (w) */
+ unsigned int FC7:1; /**< \brief [23:23] Clear Flag INTF7 for Channel 7 (w) */
+ unsigned int reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_SCU_FMR_Bits;
+
+/** \brief Identification Register */
+typedef struct _Ifx_SCU_ID_Bits
+{
+ unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
+ unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_SCU_ID_Bits;
+
+/** \brief Flag Gating Register */
+typedef struct _Ifx_SCU_IGCR_Bits
+{
+ unsigned int IPEN00:1; /**< \brief [0:0] Flag Pattern Enable for Channel 0 (rw) */
+ unsigned int IPEN01:1; /**< \brief [1:1] Flag Pattern Enable for Channel 0 (rw) */
+ unsigned int IPEN02:1; /**< \brief [2:2] Flag Pattern Enable for Channel 0 (rw) */
+ unsigned int IPEN03:1; /**< \brief [3:3] Flag Pattern Enable for Channel 0 (rw) */
+ unsigned int IPEN04:1; /**< \brief [4:4] Flag Pattern Enable for Channel 0 (rw) */
+ unsigned int IPEN05:1; /**< \brief [5:5] Flag Pattern Enable for Channel 0 (rw) */
+ unsigned int IPEN06:1; /**< \brief [6:6] Flag Pattern Enable for Channel 0 (rw) */
+ unsigned int IPEN07:1; /**< \brief [7:7] Flag Pattern Enable for Channel 0 (rw) */
+ unsigned int reserved_8:5; /**< \brief \internal Reserved */
+ unsigned int GEEN0:1; /**< \brief [13:13] Generate Event Enable 0 (rw) */
+ unsigned int IGP0:2; /**< \brief [15:14] Interrupt Gating Pattern 0 (rw) */
+ unsigned int IPEN10:1; /**< \brief [16:16] Interrupt Pattern Enable for Channel 1 (rw) */
+ unsigned int IPEN11:1; /**< \brief [17:17] Interrupt Pattern Enable for Channel 1 (rw) */
+ unsigned int IPEN12:1; /**< \brief [18:18] Interrupt Pattern Enable for Channel 1 (rw) */
+ unsigned int IPEN13:1; /**< \brief [19:19] Interrupt Pattern Enable for Channel 1 (rw) */
+ unsigned int IPEN14:1; /**< \brief [20:20] Interrupt Pattern Enable for Channel 1 (rw) */
+ unsigned int IPEN15:1; /**< \brief [21:21] Interrupt Pattern Enable for Channel 1 (rw) */
+ unsigned int IPEN16:1; /**< \brief [22:22] Interrupt Pattern Enable for Channel 1 (rw) */
+ unsigned int IPEN17:1; /**< \brief [23:23] Interrupt Pattern Enable for Channel 1 (rw) */
+ unsigned int reserved_24:5; /**< \brief \internal Reserved */
+ unsigned int GEEN1:1; /**< \brief [29:29] Generate Event Enable 1 (rw) */
+ unsigned int IGP1:2; /**< \brief [31:30] Interrupt Gating Pattern 1 (rw) */
+} Ifx_SCU_IGCR_Bits;
+
+/** \brief ESR Input Register */
+typedef struct _Ifx_SCU_IN_Bits
+{
+ unsigned int P0:1; /**< \brief [0:0] Input Bit 0 (rh) */
+ unsigned int P1:1; /**< \brief [1:1] Input Bit 1 (rh) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_SCU_IN_Bits;
+
+/** \brief Input/Output Control Register */
+typedef struct _Ifx_SCU_IOCR_Bits
+{
+ unsigned int reserved_0:4; /**< \brief \internal Reserved */
+ unsigned int PC0:4; /**< \brief [7:4] Control for ESR Pin x (rw) */
+ unsigned int reserved_8:4; /**< \brief \internal Reserved */
+ unsigned int PC1:4; /**< \brief [15:12] Control for ESR Pin x (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_SCU_IOCR_Bits;
+
+/** \brief Logic BIST Control 0 Register */
+typedef struct _Ifx_SCU_LBISTCTRL0_Bits
+{
+ unsigned int LBISTREQ:1; /**< \brief [0:0] LBIST Request (w) */
+ unsigned int LBISTREQP:1; /**< \brief [1:1] LBIST Request Protection Bit (w) */
+ unsigned int PATTERNS:14; /**< \brief [15:2] LBIST Pattern Number (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_SCU_LBISTCTRL0_Bits;
+
+/** \brief Logic BIST Control 1 Register */
+typedef struct _Ifx_SCU_LBISTCTRL1_Bits
+{
+ unsigned int SEED:23; /**< \brief [22:0] LBIST Seed (rw) */
+ unsigned int reserved_23:1; /**< \brief \internal Reserved */
+ unsigned int SPLITSH:3; /**< \brief [26:24] LBIST Split-Shift Selection (rw) */
+ unsigned int BODY:1; /**< \brief [27:27] Body Application Indicator (rw) */
+ unsigned int LBISTFREQU:4; /**< \brief [31:28] LBIST Frequency Selection (rw) */
+} Ifx_SCU_LBISTCTRL1_Bits;
+
+/** \brief Logic BIST Control 2 Register */
+typedef struct _Ifx_SCU_LBISTCTRL2_Bits
+{
+ unsigned int SIGNATURE:24; /**< \brief [23:0] LBIST Signature (rh) */
+ unsigned int reserved_24:7; /**< \brief \internal Reserved */
+ unsigned int LBISTDONE:1; /**< \brief [31:31] LBIST Execution Indicator (rh) */
+} Ifx_SCU_LBISTCTRL2_Bits;
+
+/** \brief LCL CPU Control Register */
+typedef struct _Ifx_SCU_LCLCON_Bits
+{
+ unsigned int reserved_0:16; /**< \brief \internal Reserved */
+ unsigned int LS:1; /**< \brief [16:16] Lockstep Mode Status (rh) */
+ unsigned int reserved_17:14; /**< \brief \internal Reserved */
+ unsigned int LSEN:1; /**< \brief [31:31] Lockstep Enable (rw) */
+} Ifx_SCU_LCLCON_Bits;
+
+/** \brief LCL Test Register */
+typedef struct _Ifx_SCU_LCLTEST_Bits
+{
+ unsigned int LCLT0:1; /**< \brief [0:0] Reserved in this product (r) */
+ unsigned int LCLT1:1; /**< \brief [1:1] LCL1 Lockstep Test (rwh) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_SCU_LCLTEST_Bits;
+
+/** \brief Manufacturer Identification Register */
+typedef struct _Ifx_SCU_MANID_Bits
+{
+ unsigned int DEPT:5; /**< \brief [4:0] Department Identification Number (r) */
+ unsigned int MANUF:11; /**< \brief [15:5] Manufacturer Identification Number (r) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_SCU_MANID_Bits;
+
+/** \brief ESR Output Modification Register */
+typedef struct _Ifx_SCU_OMR_Bits
+{
+ unsigned int PS0:1; /**< \brief [0:0] ESR0 Pin Set Bit 0 (w) */
+ unsigned int PS1:1; /**< \brief [1:1] ESR1 Pin Set Bit 1 (w) */
+ unsigned int reserved_2:14; /**< \brief \internal Reserved */
+ unsigned int PCL0:1; /**< \brief [16:16] ESR0 Pin Clear Bit 0 (w) */
+ unsigned int PCL1:1; /**< \brief [17:17] ESR1 Pin Clear Bit 1 (w) */
+ unsigned int reserved_18:14; /**< \brief \internal Reserved */
+} Ifx_SCU_OMR_Bits;
+
+/** \brief OSC Control Register */
+typedef struct _Ifx_SCU_OSCCON_Bits
+{
+ unsigned int reserved_0:1; /**< \brief \internal Reserved */
+ unsigned int PLLLV:1; /**< \brief [1:1] Oscillator for PLL Valid Low Status Bit (rh) */
+ unsigned int OSCRES:1; /**< \brief [2:2] Oscillator Watchdog Reset (w) */
+ unsigned int GAINSEL:2; /**< \brief [4:3] Oscillator Gain Selection (rw) */
+ unsigned int MODE:2; /**< \brief [6:5] Oscillator Mode (rw) */
+ unsigned int SHBY:1; /**< \brief [7:7] Shaper Bypass (rw) */
+ unsigned int PLLHV:1; /**< \brief [8:8] Oscillator for PLL Valid High Status Bit (rh) */
+ unsigned int reserved_9:1; /**< \brief \internal Reserved */
+ unsigned int X1D:1; /**< \brief [10:10] XTAL1 Data Value (rh) */
+ unsigned int X1DEN:1; /**< \brief [11:11] XTAL1 Data Enable (rw) */
+ unsigned int reserved_12:4; /**< \brief \internal Reserved */
+ unsigned int OSCVAL:5; /**< \brief [20:16] OSC Frequency Value (rw) */
+ unsigned int reserved_21:2; /**< \brief \internal Reserved */
+ unsigned int APREN:1; /**< \brief [23:23] Amplitude Regulation Enable (rw) */
+ unsigned int CAP0EN:1; /**< \brief [24:24] Capacitance 0 Enable (rw) */
+ unsigned int CAP1EN:1; /**< \brief [25:25] Capacitance 1 Enable (rw) */
+ unsigned int CAP2EN:1; /**< \brief [26:26] Capacitance 2 Enable (rw) */
+ unsigned int CAP3EN:1; /**< \brief [27:27] Capacitance 3 Enable (rw) */
+ unsigned int reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_SCU_OSCCON_Bits;
+
+/** \brief ESR Output Register */
+typedef struct _Ifx_SCU_OUT_Bits
+{
+ unsigned int P0:1; /**< \brief [0:0] Output Bit 0 (rwh) */
+ unsigned int P1:1; /**< \brief [1:1] Output Bit 1 (rwh) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_SCU_OUT_Bits;
+
+/** \brief Overlay Control Register */
+typedef struct _Ifx_SCU_OVCCON_Bits
+{
+ unsigned int CSEL0:1; /**< \brief [0:0] CPU Select 0 (w) */
+ unsigned int CSEL1:1; /**< \brief [1:1] CPU Select 1 (w) */
+ unsigned int CSEL2:1; /**< \brief [2:2] Reserved in this Product (r) */
+ unsigned int reserved_3:13; /**< \brief \internal Reserved */
+ unsigned int OVSTRT:1; /**< \brief [16:16] Overlay Start (w) */
+ unsigned int OVSTP:1; /**< \brief [17:17] Overlay Stop (w) */
+ unsigned int DCINVAL:1; /**< \brief [18:18] Data Cache Invalidate (w) */
+ unsigned int reserved_19:5; /**< \brief \internal Reserved */
+ unsigned int OVCONF:1; /**< \brief [24:24] Overlay Configured (rw) */
+ unsigned int POVCONF:1; /**< \brief [25:25] Write Protection for OVCONF (w) */
+ unsigned int reserved_26:6; /**< \brief \internal Reserved */
+} Ifx_SCU_OVCCON_Bits;
+
+/** \brief Overlay Enable Register */
+typedef struct _Ifx_SCU_OVCENABLE_Bits
+{
+ unsigned int OVEN0:1; /**< \brief [0:0] Overlay Enable 0 (rw) */
+ unsigned int OVEN1:1; /**< \brief [1:1] Overlay Enable 1 (rw) */
+ unsigned int OVEN2:1; /**< \brief [2:2] Reserved in this Product (rw) */
+ unsigned int reserved_3:29; /**< \brief \internal Reserved */
+} Ifx_SCU_OVCENABLE_Bits;
+
+/** \brief Pad Disable Control Register */
+typedef struct _Ifx_SCU_PDISC_Bits
+{
+ unsigned int PDIS0:1; /**< \brief [0:0] Pad Disable for ESR Pin 0 (rw) */
+ unsigned int PDIS1:1; /**< \brief [1:1] Pad Disable for ESR Pin 1 (rw) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_SCU_PDISC_Bits;
+
+/** \brief ESR Pad Driver Mode Register */
+typedef struct _Ifx_SCU_PDR_Bits
+{
+ unsigned int PD0:3; /**< \brief [2:0] Pad Driver Mode for ESR Pins 0 and 1 (rw) */
+ unsigned int PL0:1; /**< \brief [3:3] Pad Level Selection for ESR Pins 0 and 1 (rw) */
+ unsigned int PD1:3; /**< \brief [6:4] Pad Driver Mode for ESR Pins 0 and 1 (rw) */
+ unsigned int PL1:1; /**< \brief [7:7] Pad Level Selection for ESR Pins 0 and 1 (rw) */
+ unsigned int reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_SCU_PDR_Bits;
+
+/** \brief Pattern Detection Result Register */
+typedef struct _Ifx_SCU_PDRR_Bits
+{
+ unsigned int PDR0:1; /**< \brief [0:0] Pattern Detection Result of Channel 0 (rh) */
+ unsigned int PDR1:1; /**< \brief [1:1] Pattern Detection Result of Channel 1 (rh) */
+ unsigned int PDR2:1; /**< \brief [2:2] Pattern Detection Result of Channel 2 (rh) */
+ unsigned int PDR3:1; /**< \brief [3:3] Pattern Detection Result of Channel 3 (rh) */
+ unsigned int PDR4:1; /**< \brief [4:4] Pattern Detection Result of Channel 4 (rh) */
+ unsigned int PDR5:1; /**< \brief [5:5] Pattern Detection Result of Channel 5 (rh) */
+ unsigned int PDR6:1; /**< \brief [6:6] Pattern Detection Result of Channel 6 (rh) */
+ unsigned int PDR7:1; /**< \brief [7:7] Pattern Detection Result of Channel 7 (rh) */
+ unsigned int reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_SCU_PDRR_Bits;
+
+/** \brief PLL Configuration 0 Register */
+typedef struct _Ifx_SCU_PLLCON0_Bits
+{
+ unsigned int VCOBYP:1; /**< \brief [0:0] VCO Bypass (rw) */
+ unsigned int VCOPWD:1; /**< \brief [1:1] VCO Power Saving Mode (rw) */
+ unsigned int MODEN:1; /**< \brief [2:2] Modulation Enable (rw) */
+ unsigned int reserved_3:1; /**< \brief \internal Reserved */
+ unsigned int SETFINDIS:1; /**< \brief [4:4] Set Status Bit PLLSTAT.FINDIS (w) */
+ unsigned int CLRFINDIS:1; /**< \brief [5:5] Clear Status Bit PLLSTAT.FINDIS (w) */
+ unsigned int OSCDISCDIS:1; /**< \brief [6:6] Oscillator Disconnect Disable (rw) */
+ unsigned int reserved_7:2; /**< \brief \internal Reserved */
+ unsigned int NDIV:7; /**< \brief [15:9] N-Divider Value (rw) */
+ unsigned int PLLPWD:1; /**< \brief [16:16] PLL Power Saving Mode (rw) */
+ unsigned int reserved_17:1; /**< \brief \internal Reserved */
+ unsigned int RESLD:1; /**< \brief [18:18] Restart VCO Lock Detection (w) */
+ unsigned int reserved_19:5; /**< \brief \internal Reserved */
+ unsigned int PDIV:4; /**< \brief [27:24] P-Divider Value (rw) */
+ unsigned int reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_SCU_PLLCON0_Bits;
+
+/** \brief PLL Configuration 1 Register */
+typedef struct _Ifx_SCU_PLLCON1_Bits
+{
+ unsigned int K2DIV:7; /**< \brief [6:0] K2-Divider Value (rw) */
+ unsigned int reserved_7:1; /**< \brief \internal Reserved */
+ unsigned int K3DIV:7; /**< \brief [14:8] K3-Divider Value (rw) */
+ unsigned int reserved_15:1; /**< \brief \internal Reserved */
+ unsigned int K1DIV:7; /**< \brief [22:16] K1-Divider Value (rw) */
+ unsigned int reserved_23:9; /**< \brief \internal Reserved */
+} Ifx_SCU_PLLCON1_Bits;
+
+/** \brief PLL Configuration 2 Register */
+typedef struct _Ifx_SCU_PLLCON2_Bits
+{
+ unsigned int MODCFG:16; /**< \brief [15:0] Modulation Configuration (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_SCU_PLLCON2_Bits;
+
+/** \brief PLL_ERAY Configuration 0 Register */
+typedef struct _Ifx_SCU_PLLERAYCON0_Bits
+{
+ unsigned int VCOBYP:1; /**< \brief [0:0] VCO Bypass (rw) */
+ unsigned int VCOPWD:1; /**< \brief [1:1] VCO Power Saving Mode (rw) */
+ unsigned int reserved_2:2; /**< \brief \internal Reserved */
+ unsigned int SETFINDIS:1; /**< \brief [4:4] Set Status Bit PLLERAYSTAT.FINDIS (w) */
+ unsigned int CLRFINDIS:1; /**< \brief [5:5] Clear Status Bit PLLERAYSTAT.FINDIS (w) */
+ unsigned int OSCDISCDIS:1; /**< \brief [6:6] Oscillator Disconnect Disable (rw) */
+ unsigned int reserved_7:2; /**< \brief \internal Reserved */
+ unsigned int NDIV:5; /**< \brief [13:9] N-Divider Value (rw) */
+ unsigned int reserved_14:2; /**< \brief \internal Reserved */
+ unsigned int PLLPWD:1; /**< \brief [16:16] PLL Power Saving Mode (rw) */
+ unsigned int reserved_17:1; /**< \brief \internal Reserved */
+ unsigned int RESLD:1; /**< \brief [18:18] Restart VCO Lock Detection (w) */
+ unsigned int reserved_19:5; /**< \brief \internal Reserved */
+ unsigned int PDIV:4; /**< \brief [27:24] P-Divider Value (rw) */
+ unsigned int reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_SCU_PLLERAYCON0_Bits;
+
+/** \brief PLL_ERAY Configuration 1 Register */
+typedef struct _Ifx_SCU_PLLERAYCON1_Bits
+{
+ unsigned int K2DIV:7; /**< \brief [6:0] K2-Divider Value (rw) */
+ unsigned int reserved_7:1; /**< \brief \internal Reserved */
+ unsigned int K3DIV:4; /**< \brief [11:8] K3-Divider Value (rw) */
+ unsigned int reserved_12:4; /**< \brief \internal Reserved */
+ unsigned int K1DIV:7; /**< \brief [22:16] K1-Divider Value (rw) */
+ unsigned int reserved_23:9; /**< \brief \internal Reserved */
+} Ifx_SCU_PLLERAYCON1_Bits;
+
+/** \brief PLL_ERAY Status Register */
+typedef struct _Ifx_SCU_PLLERAYSTAT_Bits
+{
+ unsigned int VCOBYST:1; /**< \brief [0:0] VCO Bypass Status (rh) */
+ unsigned int PWDSTAT:1; /**< \brief [1:1] PLL_ERAY Power-saving Mode Status (rh) */
+ unsigned int VCOLOCK:1; /**< \brief [2:2] PLL VCO Lock Status (rh) */
+ unsigned int FINDIS:1; /**< \brief [3:3] Input Clock Disconnect Select Status (rh) */
+ unsigned int K1RDY:1; /**< \brief [4:4] K1 Divider Ready Status (rh) */
+ unsigned int K2RDY:1; /**< \brief [5:5] K2 Divider Ready Status (rh) */
+ unsigned int reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_SCU_PLLERAYSTAT_Bits;
+
+/** \brief PLL Status Register */
+typedef struct _Ifx_SCU_PLLSTAT_Bits
+{
+ unsigned int VCOBYST:1; /**< \brief [0:0] VCO Bypass Status (rh) */
+ unsigned int reserved_1:1; /**< \brief \internal Reserved */
+ unsigned int VCOLOCK:1; /**< \brief [2:2] PLL VCO Lock Status (rh) */
+ unsigned int FINDIS:1; /**< \brief [3:3] Input Clock Disconnect Select Status (rh) */
+ unsigned int K1RDY:1; /**< \brief [4:4] K1 Divider Ready Status (rh) */
+ unsigned int K2RDY:1; /**< \brief [5:5] K2 Divider Ready Status (rh) */
+ unsigned int reserved_6:1; /**< \brief \internal Reserved */
+ unsigned int MODRUN:1; /**< \brief [7:7] Modulation Run (rh) */
+ unsigned int reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_SCU_PLLSTAT_Bits;
+
+/** \brief Power Management Control and Status Register */
+typedef struct _Ifx_SCU_PMCSR_Bits
+{
+ unsigned int REQSLP:2; /**< \brief [1:0] Idle Mode and Sleep Mode Request (rwh) */
+ unsigned int SMUSLP:1; /**< \brief [2:2] SMU CPU Idle Request (rwh) */
+ unsigned int reserved_3:5; /**< \brief \internal Reserved */
+ unsigned int PMST:3; /**< \brief [10:8] Power management Status (rh) */
+ unsigned int reserved_11:21; /**< \brief \internal Reserved */
+} Ifx_SCU_PMCSR_Bits;
+
+/** \brief Standby and Wake-up Control Register 0 */
+typedef struct _Ifx_SCU_PMSWCR0_Bits
+{
+ unsigned int reserved_0:1; /**< \brief \internal Reserved */
+ unsigned int ESR1WKEN:1; /**< \brief [1:1] ESR1 Wake-up enable from Standby (rw) */
+ unsigned int PINAWKEN:1; /**< \brief [2:2] Pin A Wake-up enable from Standby (rw) */
+ unsigned int PINBWKEN:1; /**< \brief [3:3] Pin B Wake-up enable from Standby (rw) */
+ unsigned int ESR0DFEN:1; /**< \brief [4:4] Digital Filter Enable (rw) */
+ unsigned int ESR0EDCON:2; /**< \brief [6:5] Edge Detection Control (rw) */
+ unsigned int ESR1DFEN:1; /**< \brief [7:7] Digital Filter Enable (rw) */
+ unsigned int ESR1EDCON:2; /**< \brief [9:8] Edge Detection Control (rw) */
+ unsigned int PINADFEN:1; /**< \brief [10:10] Digital Filter Enable (rw) */
+ unsigned int PINAEDCON:2; /**< \brief [12:11] Edge Detection Control (rw) */
+ unsigned int PINBDFEN:1; /**< \brief [13:13] Digital Filter Enable (rw) */
+ unsigned int PINBEDCON:2; /**< \brief [15:14] Edge Detection Control (rw) */
+ unsigned int SCREN:1; /**< \brief [16:16] Standby Controller Enable request (rw) */
+ unsigned int STBYRAMSEL:2; /**< \brief [18:17] Standby RAM supply in Standby Mode (rw) */
+ unsigned int SCRCLKSEL:1; /**< \brief [19:19] Default Clock selection on Standby Mode Entry (rw) */
+ unsigned int SCRWKEN:1; /**< \brief [20:20] Standby Controller Wake-up enable from Standby (rw) */
+ unsigned int TRISTEN:1; /**< \brief [21:21] Bit protection for Tristate request bit (TRISTREQ) (w) */
+ unsigned int TRISTREQ:1; /**< \brief [22:22] Tristate enable (rw) */
+ unsigned int PORSTDF:1; /**< \brief [23:23] PORST Digital Filter enable (rw) */
+ unsigned int reserved_24:1; /**< \brief \internal Reserved */
+ unsigned int DCDCSYNC:1; /**< \brief [25:25] DC-DC Synchronisation Enable (rw) */
+ unsigned int reserved_26:3; /**< \brief \internal Reserved */
+ unsigned int ESR0TRIST:1; /**< \brief [29:29] ESR0 Tristate enable (rw) */
+ unsigned int reserved_30:1; /**< \brief \internal Reserved */
+ unsigned int LCK:1; /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_PMSWCR0_Bits;
+
+/** \brief Standby and Wake-up Control Register 1 */
+typedef struct _Ifx_SCU_PMSWCR1_Bits
+{
+ unsigned int SCRSTEN:1; /**< \brief [0:0] Standby Controller Reset request enable (w) */
+ unsigned int SCRSTREQ:1; /**< \brief [1:1] Standby Controller Reset request (w) */
+ unsigned int reserved_2:6; /**< \brief \internal Reserved */
+ unsigned int CPUIDLSEL:3; /**< \brief [10:8] CPU selection for Idle mode (rw) */
+ unsigned int reserved_11:1; /**< \brief \internal Reserved */
+ unsigned int IRADIS:1; /**< \brief [12:12] Idle-Request-Acknowledge Sequence Disable (rw) */
+ unsigned int reserved_13:3; /**< \brief \internal Reserved */
+ unsigned int SCRCFG:8; /**< \brief [23:16] Hardware configuration of the 8 bit controller. (rw) */
+ unsigned int CPUSEL:3; /**< \brief [26:24] CPU selection for Sleep and Standby mode (rw) */
+ unsigned int STBYEVEN:1; /**< \brief [27:27] Standby Entry Event configuration enable (w) */
+ unsigned int STBYEV:3; /**< \brief [30:28] Standby Entry Event Configuration (rw) */
+ unsigned int LCK:1; /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_PMSWCR1_Bits;
+
+/** \brief Standby and Wake-up Control Register 2 */
+typedef struct _Ifx_SCU_PMSWCR2_Bits
+{
+ unsigned int SCRINT:8; /**< \brief [7:0] Data exchange from Standby Controller to SCU. (r) */
+ unsigned int BUSY:1; /**< \brief [8:8] SCR Arbiter Busy status flag (rh) */
+ unsigned int SCRECC:1; /**< \brief [9:9] SCR RAM ECC error / reset flag (rh) */
+ unsigned int SCRWDT:1; /**< \brief [10:10] SCR Watchdog Timer error / reset flag (rh) */
+ unsigned int SCRRST:1; /**< \brief [11:11] SCR Software reset flag (rh) */
+ unsigned int reserved_12:4; /**< \brief \internal Reserved */
+ unsigned int TCINT:8; /**< \brief [23:16] Data exchange from SCU to Standby Controller. (rw) */
+ unsigned int TCINTREQ:1; /**< \brief [24:24] SW Interrupt request from SCU to Standby Controller. (rw) */
+ unsigned int SMURST:1; /**< \brief [25:25] SMU Reset indication flag (rh) */
+ unsigned int RST:1; /**< \brief [26:26] Application or System Reset indication flag (rh) */
+ unsigned int reserved_27:4; /**< \brief \internal Reserved */
+ unsigned int LCK:1; /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_PMSWCR2_Bits;
+
+/** \brief Standby and Wake-up Status Flag Register */
+typedef struct _Ifx_SCU_PMSWSTAT_Bits
+{
+ unsigned int reserved_0:2; /**< \brief \internal Reserved */
+ unsigned int ESR1WKP:1; /**< \brief [2:2] ESR1 Wake-up flag (rh) */
+ unsigned int ESR1OVRUN:1; /**< \brief [3:3] ESR1 Overrun status flag (rh) */
+ unsigned int PINAWKP:1; /**< \brief [4:4] Pin A (P14.1) Wake-up flag (rh) */
+ unsigned int PINAOVRUN:1; /**< \brief [5:5] Pin A Overrun status flag (rh) */
+ unsigned int PINBWKP:1; /**< \brief [6:6] Pin B (P15.1) Wake-up flag (rh) */
+ unsigned int PINBOVRUN:1; /**< \brief [7:7] Pin B Overrun status flag (rh) */
+ unsigned int reserved_8:1; /**< \brief \internal Reserved */
+ unsigned int PORSTDF:1; /**< \brief [9:9] PORST Digital Filter status (rh) */
+ unsigned int HWCFGEVR:3; /**< \brief [12:10] EVR Hardware Configuration (rh) */
+ unsigned int STBYRAM:2; /**< \brief [14:13] Standby RAM Supply status (rh) */
+ unsigned int TRIST:1; /**< \brief [15:15] Pad Tristate / Pull-up status (rh) */
+ unsigned int SCRST:1; /**< \brief [16:16] Standby Controller Reset Indication flag (rh) */
+ unsigned int SCRWKP:1; /**< \brief [17:17] SCR Wake-up flag (rh) */
+ unsigned int SCR:1; /**< \brief [18:18] Standby Controller status (rh) */
+ unsigned int SCRWKEN:1; /**< \brief [19:19] Standby Controller Wake-up Enable status (rh) */
+ unsigned int ESR1WKEN:1; /**< \brief [20:20] ESR1 Wake-up enable status (rh) */
+ unsigned int PINAWKEN:1; /**< \brief [21:21] Pin A Wake-up enable status (rh) */
+ unsigned int PINBWKEN:1; /**< \brief [22:22] Pin B Wake-up enable status (rh) */
+ unsigned int reserved_23:4; /**< \brief \internal Reserved */
+ unsigned int ESR0TRIST:1; /**< \brief [27:27] ESR0 pin status during Standby (rh) */
+ unsigned int reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_SCU_PMSWSTAT_Bits;
+
+/** \brief Standby and Wake-up Status Clear Register */
+typedef struct _Ifx_SCU_PMSWSTATCLR_Bits
+{
+ unsigned int reserved_0:2; /**< \brief \internal Reserved */
+ unsigned int ESR1WKPCLR:1; /**< \brief [2:2] ESR1 Wake-up indication flag clear (w) */
+ unsigned int ESR1OVRUNCLR:1; /**< \brief [3:3] ESR1 Overrun status indication flag clear (w) */
+ unsigned int PINAWKPCLR:1; /**< \brief [4:4] PINA Wake-up indication flag clear (w) */
+ unsigned int PINAOVRUNCLR:1; /**< \brief [5:5] PINA Overrun status indication flag clear (w) */
+ unsigned int PINBWKPCLR:1; /**< \brief [6:6] PINB Wake-up indication flag clear (w) */
+ unsigned int PINBOVRUNCLR:1; /**< \brief [7:7] PINB Overrun status indication flag clear (w) */
+ unsigned int reserved_8:8; /**< \brief \internal Reserved */
+ unsigned int SCRSTCLR:1; /**< \brief [16:16] Standby controller SCRST indication flag clear (w) */
+ unsigned int SCRWKPCLR:1; /**< \brief [17:17] SCR Wake-up indication flag clear (w) */
+ unsigned int reserved_18:14; /**< \brief \internal Reserved */
+} Ifx_SCU_PMSWSTATCLR_Bits;
+
+/** \brief Additional Reset Control Register */
+typedef struct _Ifx_SCU_RSTCON2_Bits
+{
+ unsigned int reserved_0:1; /**< \brief \internal Reserved */
+ unsigned int CLRC:1; /**< \brief [1:1] Clear Cold Reset Status (w) */
+ unsigned int reserved_2:10; /**< \brief \internal Reserved */
+ unsigned int CSS0:1; /**< \brief [12:12] CPU0 Safe State Reached (rh) */
+ unsigned int CSS1:1; /**< \brief [13:13] CPU1 Safe State Reached (rh) */
+ unsigned int CSS2:1; /**< \brief [14:14] Reserved in this product (r) */
+ unsigned int reserved_15:1; /**< \brief \internal Reserved */
+ unsigned int USRINFO:16; /**< \brief [31:16] User Information (rw) */
+} Ifx_SCU_RSTCON2_Bits;
+
+/** \brief Reset Configuration Register */
+typedef struct _Ifx_SCU_RSTCON_Bits
+{
+ unsigned int ESR0:2; /**< \brief [1:0] ESR0 Reset Request Trigger Reset Configuration (rw) */
+ unsigned int ESR1:2; /**< \brief [3:2] ESR1 Reset Request Trigger Reset Configuration (rw) */
+ unsigned int reserved_4:2; /**< \brief \internal Reserved */
+ unsigned int SMU:2; /**< \brief [7:6] SMU Reset Request Trigger Reset Configuration (rw) */
+ unsigned int SW:2; /**< \brief [9:8] SW Reset Request Trigger Reset Configuration (rw) */
+ unsigned int STM0:2; /**< \brief [11:10] STM0 Reset Request Trigger Reset Configuration (rw) */
+ unsigned int STM1:2; /**< \brief [13:12] STM1 Reset Request Trigger Reset Configuration (If Product has STM1) (rw) */
+ unsigned int STM2:2; /**< \brief [15:14] STM2 Reset Request Trigger Reset Configuration (If Product has STM2) (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_SCU_RSTCON_Bits;
+
+/** \brief Reset Status Register */
+typedef struct _Ifx_SCU_RSTSTAT_Bits
+{
+ unsigned int ESR0:1; /**< \brief [0:0] Reset Request Trigger Reset Status for ESR0 (rh) */
+ unsigned int ESR1:1; /**< \brief [1:1] Reset Request Trigger Reset Status for ESR1 (rh) */
+ unsigned int reserved_2:1; /**< \brief \internal Reserved */
+ unsigned int SMU:1; /**< \brief [3:3] Reset Request Trigger Reset Status for SMU (rh) */
+ unsigned int SW:1; /**< \brief [4:4] Reset Request Trigger Reset Status for SW (rh) */
+ unsigned int STM0:1; /**< \brief [5:5] Reset Request Trigger Reset Status for STM0 Compare Match (rh) */
+ unsigned int STM1:1; /**< \brief [6:6] Reset Request Trigger Reset Status for STM1 Compare Match (If Product has STM1) (rh) */
+ unsigned int STM2:1; /**< \brief [7:7] Reset Request Trigger Reset Status for STM2 Compare Match (If Product has STM2) (rh) */
+ unsigned int reserved_8:8; /**< \brief \internal Reserved */
+ unsigned int PORST:1; /**< \brief [16:16] Reset Request Trigger Reset Status for PORST (rh) */
+ unsigned int reserved_17:1; /**< \brief \internal Reserved */
+ unsigned int CB0:1; /**< \brief [18:18] Reset Request Trigger Reset Status for Cerberus System Reset (rh) */
+ unsigned int CB1:1; /**< \brief [19:19] Reset Request Trigger Reset Status for Cerberus Debug Reset (rh) */
+ unsigned int CB3:1; /**< \brief [20:20] Reset Request Trigger Reset Status for Cerberus Application Reset (rh) */
+ unsigned int reserved_21:2; /**< \brief \internal Reserved */
+ unsigned int EVR13:1; /**< \brief [23:23] Reset Request Trigger Reset Status for EVR13 (rh) */
+ unsigned int EVR33:1; /**< \brief [24:24] Reset Request Trigger Reset Status for EVR33 (rh) */
+ unsigned int SWD:1; /**< \brief [25:25] Reset Request Trigger Reset Status for Supply Watchdog (SWD) (rh) */
+ unsigned int reserved_26:2; /**< \brief \internal Reserved */
+ unsigned int STBYR:1; /**< \brief [28:28] Reset Request Trigger Reset Status for Standby Regulator Watchdog (STBYR) (rh) */
+ unsigned int reserved_29:3; /**< \brief \internal Reserved */
+} Ifx_SCU_RSTSTAT_Bits;
+
+/** \brief Safety Heartbeat Register */
+typedef struct _Ifx_SCU_SAFECON_Bits
+{
+ unsigned int HBT:1; /**< \brief [0:0] Heartbeat (rw) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_SCU_SAFECON_Bits;
+
+/** \brief Start-up Status Register */
+typedef struct _Ifx_SCU_STSTAT_Bits
+{
+ unsigned int HWCFG:8; /**< \brief [7:0] Hardware Configuration Setting (rh) */
+ unsigned int FTM:7; /**< \brief [14:8] Firmware Test Setting (rh) */
+ unsigned int MODE:1; /**< \brief [15:15] MODE (rh) */
+ unsigned int FCBAE:1; /**< \brief [16:16] Flash Config. Sector Access Enable (rh) */
+ unsigned int LUDIS:1; /**< \brief [17:17] Latch Update Disable (rh) */
+ unsigned int reserved_18:1; /**< \brief \internal Reserved */
+ unsigned int TRSTL:1; /**< \brief [19:19] TRSTL Status (rh) */
+ unsigned int SPDEN:1; /**< \brief [20:20] Single Pin DAP Mode Enable (rh) */
+ unsigned int reserved_21:3; /**< \brief \internal Reserved */
+ unsigned int RAMINT:1; /**< \brief [24:24] RAM Content Security Integrity (rh) */
+ unsigned int reserved_25:7; /**< \brief \internal Reserved */
+} Ifx_SCU_STSTAT_Bits;
+
+/** \brief Software Reset Configuration Register */
+typedef struct _Ifx_SCU_SWRSTCON_Bits
+{
+ unsigned int reserved_0:1; /**< \brief \internal Reserved */
+ unsigned int SWRSTREQ:1; /**< \brief [1:1] Software Reset Request (w) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_SCU_SWRSTCON_Bits;
+
+/** \brief System Control Register */
+typedef struct _Ifx_SCU_SYSCON_Bits
+{
+ unsigned int CCTRIG0:1; /**< \brief [0:0] Capture Compare Trigger 0 (rw) */
+ unsigned int reserved_1:1; /**< \brief \internal Reserved */
+ unsigned int RAMINTM:2; /**< \brief [3:2] RAM Integrity Modify (w) */
+ unsigned int SETLUDIS:1; /**< \brief [4:4] Set Latch Update Disable (w) */
+ unsigned int reserved_5:3; /**< \brief \internal Reserved */
+ unsigned int DATM:1; /**< \brief [8:8] Disable Application Test Mode (ATM) (rw) */
+ unsigned int reserved_9:23; /**< \brief \internal Reserved */
+} Ifx_SCU_SYSCON_Bits;
+
+/** \brief Trap Clear Register */
+typedef struct _Ifx_SCU_TRAPCLR_Bits
+{
+ unsigned int ESR0T:1; /**< \brief [0:0] Clear Trap Request Flag ESR0T (w) */
+ unsigned int ESR1T:1; /**< \brief [1:1] Clear Trap Request Flag ESR1T (w) */
+ unsigned int reserved_2:1; /**< \brief \internal Reserved */
+ unsigned int SMUT:1; /**< \brief [3:3] Clear Trap Request Flag SMUT (w) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_SCU_TRAPCLR_Bits;
+
+/** \brief Trap Disable Register */
+typedef struct _Ifx_SCU_TRAPDIS_Bits
+{
+ unsigned int ESR0T:1; /**< \brief [0:0] Disable Trap Request ESR0T (rw) */
+ unsigned int ESR1T:1; /**< \brief [1:1] Disable Trap Request ESR1T (rw) */
+ unsigned int reserved_2:1; /**< \brief \internal Reserved */
+ unsigned int SMUT:1; /**< \brief [3:3] Disable Trap Request SMUT (rw) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_SCU_TRAPDIS_Bits;
+
+/** \brief Trap Set Register */
+typedef struct _Ifx_SCU_TRAPSET_Bits
+{
+ unsigned int ESR0T:1; /**< \brief [0:0] Set Trap Request Flag ESR0T (w) */
+ unsigned int ESR1T:1; /**< \brief [1:1] Set Trap Request Flag ESR1T (w) */
+ unsigned int reserved_2:1; /**< \brief \internal Reserved */
+ unsigned int SMUT:1; /**< \brief [3:3] Set Trap Request Flag SMUT (w) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_SCU_TRAPSET_Bits;
+
+/** \brief Trap Status Register */
+typedef struct _Ifx_SCU_TRAPSTAT_Bits
+{
+ unsigned int ESR0T:1; /**< \brief [0:0] ESR0 Trap Request Flag (rh) */
+ unsigned int ESR1T:1; /**< \brief [1:1] ESR1 Trap Request Flag (rh) */
+ unsigned int reserved_2:1; /**< \brief \internal Reserved */
+ unsigned int SMUT:1; /**< \brief [3:3] SMU Alarm Trap Request Flag (rh) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_SCU_TRAPSTAT_Bits;
+
+/** \brief CPU WDT Control Register 0 */
+typedef struct _Ifx_SCU_WDTCPU_CON0_Bits
+{
+ Ifx_Strict_32Bit ENDINIT:1; /**< \brief [0:0] End-of-Initialization Control Bit (rwh) */
+ Ifx_Strict_32Bit LCK:1; /**< \brief [1:1] Lock Bit to Control Access to WDTxCON0 (rwh) */
+ Ifx_Strict_32Bit PW:14; /**< \brief [15:2] User-Definable Password Field for Access to WDTxCON0 (rwh) */
+ Ifx_Strict_32Bit REL:16; /**< \brief [31:16] Reload Value for the WDT (also Time Check Value) (rw) */
+} Ifx_SCU_WDTCPU_CON0_Bits;
+
+/** \brief CPU WDT Control Register 1 */
+typedef struct _Ifx_SCU_WDTCPU_CON1_Bits
+{
+ unsigned int reserved_0:2; /**< \brief \internal Reserved */
+ unsigned int IR0:1; /**< \brief [2:2] Input Frequency Request Control (rw) */
+ unsigned int DR:1; /**< \brief [3:3] Disable Request Control Bit (rw) */
+ unsigned int reserved_4:1; /**< \brief \internal Reserved */
+ unsigned int IR1:1; /**< \brief [5:5] Input Frequency Request Control (rw) */
+ unsigned int UR:1; /**< \brief [6:6] Unlock Restriction Request Control Bit (rw) */
+ unsigned int PAR:1; /**< \brief [7:7] Password Auto-sequence Request Bit (rw) */
+ unsigned int TCR:1; /**< \brief [8:8] Counter Check Request Bit (rw) */
+ unsigned int TCTR:7; /**< \brief [15:9] Timer Check Tolerance Request (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_SCU_WDTCPU_CON1_Bits;
+
+/** \brief CPU WDT Status Register */
+typedef struct _Ifx_SCU_WDTCPU_SR_Bits
+{
+ unsigned int AE:1; /**< \brief [0:0] Watchdog Access Error Status Flag (rh) */
+ unsigned int OE:1; /**< \brief [1:1] Watchdog Overflow Error Status Flag (rh) */
+ unsigned int IS0:1; /**< \brief [2:2] Watchdog Input Clock Status (rh) */
+ unsigned int DS:1; /**< \brief [3:3] Watchdog Enable/Disable Status Flag (rh) */
+ unsigned int TO:1; /**< \brief [4:4] Watchdog Time-Out Mode Flag (rh) */
+ unsigned int IS1:1; /**< \brief [5:5] Watchdog Input Clock Status (rh) */
+ unsigned int US:1; /**< \brief [6:6] SMU Unlock Restriction Status Flag (rh) */
+ unsigned int PAS:1; /**< \brief [7:7] Password Auto-sequence Status Flag (rh) */
+ unsigned int TCS:1; /**< \brief [8:8] Timer Check Status Flag (rh) */
+ unsigned int TCT:7; /**< \brief [15:9] Timer Check Tolerance (rh) */
+ unsigned int TIM:16; /**< \brief [31:16] Timer Value (rh) */
+} Ifx_SCU_WDTCPU_SR_Bits;
+
+/** \brief Safety WDT Control Register 0 */
+typedef struct _Ifx_SCU_WDTS_CON0_Bits
+{
+ Ifx_Strict_32Bit ENDINIT:1; /**< \brief [0:0] End-of-Initialization Control Bit (rwh) */
+ Ifx_Strict_32Bit LCK:1; /**< \brief [1:1] Lock Bit to Control Access to WDTxCON0 (rwh) */
+ Ifx_Strict_32Bit PW:14; /**< \brief [15:2] User-Definable Password Field for Access to WDTxCON0 (rwh) */
+ Ifx_Strict_32Bit REL:16; /**< \brief [31:16] Reload Value for the WDT (also Time Check Value) (rw) */
+} Ifx_SCU_WDTS_CON0_Bits;
+
+/** \brief Safety WDT Control Register 1 */
+typedef struct _Ifx_SCU_WDTS_CON1_Bits
+{
+ unsigned int CLRIRF:1; /**< \brief [0:0] Clear Internal Reset Flag (rwh) */
+ unsigned int reserved_1:1; /**< \brief \internal Reserved */
+ unsigned int IR0:1; /**< \brief [2:2] Input Frequency Request Control (rw) */
+ unsigned int DR:1; /**< \brief [3:3] Disable Request Control Bit (rw) */
+ unsigned int reserved_4:1; /**< \brief \internal Reserved */
+ unsigned int IR1:1; /**< \brief [5:5] Input Frequency Request Control (rw) */
+ unsigned int UR:1; /**< \brief [6:6] Unlock Restriction Request Control Bit (rw) */
+ unsigned int PAR:1; /**< \brief [7:7] Password Auto-sequence Request Bit (rw) */
+ unsigned int TCR:1; /**< \brief [8:8] Counter Check Request Bit (rw) */
+ unsigned int TCTR:7; /**< \brief [15:9] Timer Check Tolerance Request (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_SCU_WDTS_CON1_Bits;
+
+/** \brief Safety WDT Status Register */
+typedef struct _Ifx_SCU_WDTS_SR_Bits
+{
+ unsigned int AE:1; /**< \brief [0:0] Watchdog Access Error Status Flag (rh) */
+ unsigned int OE:1; /**< \brief [1:1] Watchdog Overflow Error Status Flag (rh) */
+ unsigned int IS0:1; /**< \brief [2:2] Watchdog Input Clock Status (rh) */
+ unsigned int DS:1; /**< \brief [3:3] Watchdog Enable/Disable Status Flag (rh) */
+ unsigned int TO:1; /**< \brief [4:4] Watchdog Time-Out Mode Flag (rh) */
+ unsigned int IS1:1; /**< \brief [5:5] Watchdog Input Clock Status (rh) */
+ unsigned int US:1; /**< \brief [6:6] SMU Unlock Restriction Status Flag (rh) */
+ unsigned int PAS:1; /**< \brief [7:7] Password Auto-sequence Status Flag (rh) */
+ unsigned int TCS:1; /**< \brief [8:8] Timer Check Status Flag (rh) */
+ unsigned int TCT:7; /**< \brief [15:9] Timer Check Tolerance (rh) */
+ unsigned int TIM:16; /**< \brief [31:16] Timer Value (rh) */
+} Ifx_SCU_WDTS_SR_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Scu_union
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_ACCEN0_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_ACCEN0;
+
+/** \brief Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_ACCEN1_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_ACCEN1;
+
+/** \brief Application Reset Disable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_ARSTDIS_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_ARSTDIS;
+
+/** \brief CCU Clock Control Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_CCUCON0_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_CCUCON0;
+
+/** \brief CCU Clock Control Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_CCUCON1_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_CCUCON1;
+
+/** \brief CCU Clock Control Register 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_CCUCON2_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_CCUCON2;
+
+/** \brief CCU Clock Control Register 3 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_CCUCON3_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_CCUCON3;
+
+/** \brief CCU Clock Control Register 4 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_CCUCON4_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_CCUCON4;
+
+/** \brief CCU Clock Control Register 5 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_CCUCON5_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_CCUCON5;
+
+/** \brief CCU Clock Control Register 6 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_CCUCON6_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_CCUCON6;
+
+/** \brief CCU Clock Control Register 7 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_CCUCON7_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_CCUCON7;
+
+/** \brief Chip Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_CHIPID_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_CHIPID;
+
+/** \brief Die Temperature Sensor Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_DTSCON_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_DTSCON;
+
+/** \brief Die Temperature Sensor Limit Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_DTSLIM_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_DTSLIM;
+
+/** \brief Die Temperature Sensor Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_DTSSTAT_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_DTSSTAT;
+
+/** \brief External Input Channel Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_EICR_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_EICR;
+
+/** \brief External Input Flag Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_EIFR_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_EIFR;
+
+/** \brief Emergency Stop Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_EMSR_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_EMSR;
+
+/** \brief ESR Input Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_ESRCFG_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_ESRCFG;
+
+/** \brief ESR Output Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_ESROCFG_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_ESROCFG;
+
+/** \brief EVR13 Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_EVR13CON_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_EVR13CON;
+
+/** \brief EVR33 Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_EVR33CON_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_EVR33CON;
+
+/** \brief EVR ADC Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_EVRADCSTAT_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_EVRADCSTAT;
+
+/** \brief EVR Status Register for Voltage Scaling */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_EVRDVSTAT_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_EVRDVSTAT;
+
+/** \brief EVR Monitor Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_EVRMONCTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_EVRMONCTRL;
+
+/** \brief EVR Oscillator & Bandgap Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_EVROSCCTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_EVROSCCTRL;
+
+/** \brief EVR Over-voltage Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_EVROVMON_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_EVROVMON;
+
+/** \brief EVR Reset Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_EVRRSTCON_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_EVRRSTCON;
+
+/** \brief EVR13 SD Coefficient Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_EVRSDCOEFF1_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_EVRSDCOEFF1;
+
+/** \brief EVR13 SD Coefficient Register 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_EVRSDCOEFF2_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_EVRSDCOEFF2;
+
+/** \brief EVR13 SD Coefficient Register 3 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_EVRSDCOEFF3_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_EVRSDCOEFF3;
+
+/** \brief EVR13 SD Coefficient Register 4 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_EVRSDCOEFF4_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_EVRSDCOEFF4;
+
+/** \brief EVR13 SD Coefficient Register 5 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_EVRSDCOEFF5_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_EVRSDCOEFF5;
+
+/** \brief EVR13 SD Coefficient Register 6 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_EVRSDCOEFF6_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_EVRSDCOEFF6;
+
+/** \brief EVR13 SD Control Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_EVRSDCTRL1_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_EVRSDCTRL1;
+
+/** \brief EVR13 SD Control Register 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_EVRSDCTRL2_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_EVRSDCTRL2;
+
+/** \brief EVR13 SD Control Register 3 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_EVRSDCTRL3_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_EVRSDCTRL3;
+
+/** \brief EVR13 SD Control Register 4 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_EVRSDCTRL4_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_EVRSDCTRL4;
+
+/** \brief EVR Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_EVRSTAT_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_EVRSTAT;
+
+/** \brief EVR Trim Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_EVRTRIM_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_EVRTRIM;
+
+/** \brief EVR Under-voltage Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_EVRUVMON_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_EVRUVMON;
+
+/** \brief External Clock Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_EXTCON_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_EXTCON;
+
+/** \brief Fractional Divider Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_FDR_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_FDR;
+
+/** \brief Flag Modification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_FMR_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_FMR;
+
+/** \brief Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_ID;
+
+/** \brief Flag Gating Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_IGCR_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_IGCR;
+
+/** \brief ESR Input Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_IN_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_IN;
+
+/** \brief Input/Output Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_IOCR_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_IOCR;
+
+/** \brief Logic BIST Control 0 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_LBISTCTRL0_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_LBISTCTRL0;
+
+/** \brief Logic BIST Control 1 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_LBISTCTRL1_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_LBISTCTRL1;
+
+/** \brief Logic BIST Control 2 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_LBISTCTRL2_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_LBISTCTRL2;
+
+/** \brief LCL CPU Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_LCLCON_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_LCLCON;
+
+/** \brief LCL Test Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_LCLTEST_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_LCLTEST;
+
+/** \brief Manufacturer Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_MANID_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_MANID;
+
+/** \brief ESR Output Modification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_OMR_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_OMR;
+
+/** \brief OSC Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_OSCCON_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_OSCCON;
+
+/** \brief ESR Output Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_OUT_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_OUT;
+
+/** \brief Overlay Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_OVCCON_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_OVCCON;
+
+/** \brief Overlay Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_OVCENABLE_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_OVCENABLE;
+
+/** \brief Pad Disable Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_PDISC_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_PDISC;
+
+/** \brief ESR Pad Driver Mode Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_PDR_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_PDR;
+
+/** \brief Pattern Detection Result Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_PDRR_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_PDRR;
+
+/** \brief PLL Configuration 0 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_PLLCON0_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_PLLCON0;
+
+/** \brief PLL Configuration 1 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_PLLCON1_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_PLLCON1;
+
+/** \brief PLL Configuration 2 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_PLLCON2_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_PLLCON2;
+
+/** \brief PLL_ERAY Configuration 0 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_PLLERAYCON0_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_PLLERAYCON0;
+
+/** \brief PLL_ERAY Configuration 1 Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_PLLERAYCON1_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_PLLERAYCON1;
+
+/** \brief PLL_ERAY Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_PLLERAYSTAT_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_PLLERAYSTAT;
+
+/** \brief PLL Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_PLLSTAT_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_PLLSTAT;
+
+/** \brief Power Management Control and Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_PMCSR_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_PMCSR;
+
+/** \brief Standby and Wake-up Control Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_PMSWCR0_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_PMSWCR0;
+
+/** \brief Standby and Wake-up Control Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_PMSWCR1_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_PMSWCR1;
+
+/** \brief Standby and Wake-up Control Register 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_PMSWCR2_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_PMSWCR2;
+
+/** \brief Standby and Wake-up Status Flag Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_PMSWSTAT_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_PMSWSTAT;
+
+/** \brief Standby and Wake-up Status Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_PMSWSTATCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_PMSWSTATCLR;
+
+/** \brief Reset Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_RSTCON_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_RSTCON;
+
+/** \brief Additional Reset Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_RSTCON2_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_RSTCON2;
+
+/** \brief Reset Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_RSTSTAT_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_RSTSTAT;
+
+/** \brief Safety Heartbeat Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_SAFECON_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_SAFECON;
+
+/** \brief Start-up Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_STSTAT_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_STSTAT;
+
+/** \brief Software Reset Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_SWRSTCON_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_SWRSTCON;
+
+/** \brief System Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_SYSCON_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_SYSCON;
+
+/** \brief Trap Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_TRAPCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_TRAPCLR;
+
+/** \brief Trap Disable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_TRAPDIS_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_TRAPDIS;
+
+/** \brief Trap Set Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_TRAPSET_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_TRAPSET;
+
+/** \brief Trap Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_TRAPSTAT_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_TRAPSTAT;
+
+/** \brief CPU WDT Control Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_WDTCPU_CON0_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_WDTCPU_CON0;
+
+/** \brief CPU WDT Control Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_WDTCPU_CON1_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_WDTCPU_CON1;
+
+/** \brief CPU WDT Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_WDTCPU_SR_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_WDTCPU_SR;
+
+/** \brief Safety WDT Control Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_WDTS_CON0_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_WDTS_CON0;
+
+/** \brief Safety WDT Control Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_WDTS_CON1_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_WDTS_CON1;
+
+/** \brief Safety WDT Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SCU_WDTS_SR_Bits B; /**< \brief Bitfield access */
+} Ifx_SCU_WDTS_SR;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Scu_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L1
+ * \{ */
+
+/** \brief CPU watchdog */
+typedef volatile struct _Ifx_SCU_WDTCPU
+{
+ Ifx_SCU_WDTCPU_CON0 CON0; /**< \brief 0, CPU WDT Control Register 0 */
+ Ifx_SCU_WDTCPU_CON1 CON1; /**< \brief 4, CPU WDT Control Register 1 */
+ Ifx_SCU_WDTCPU_SR SR; /**< \brief 8, CPU WDT Status Register */
+} Ifx_SCU_WDTCPU;
+
+/** \brief Safety watchdog */
+typedef volatile struct _Ifx_SCU_WDTS
+{
+ Ifx_SCU_WDTS_CON0 CON0; /**< \brief 0, Safety WDT Control Register 0 */
+ Ifx_SCU_WDTS_CON1 CON1; /**< \brief 4, Safety WDT Control Register 1 */
+ Ifx_SCU_WDTS_SR SR; /**< \brief 8, Safety WDT Status Register */
+} Ifx_SCU_WDTS;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Scu_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief SCU object */
+typedef volatile struct _Ifx_SCU
+{
+ unsigned char reserved_0[8]; /**< \brief 0, \internal Reserved */
+ Ifx_SCU_ID ID; /**< \brief 8, Identification Register */
+ unsigned char reserved_C[4]; /**< \brief C, \internal Reserved */
+ Ifx_SCU_OSCCON OSCCON; /**< \brief 10, OSC Control Register */
+ Ifx_SCU_PLLSTAT PLLSTAT; /**< \brief 14, PLL Status Register */
+ Ifx_SCU_PLLCON0 PLLCON0; /**< \brief 18, PLL Configuration 0 Register */
+ Ifx_SCU_PLLCON1 PLLCON1; /**< \brief 1C, PLL Configuration 1 Register */
+ Ifx_SCU_PLLCON2 PLLCON2; /**< \brief 20, PLL Configuration 2 Register */
+ Ifx_SCU_PLLERAYSTAT PLLERAYSTAT; /**< \brief 24, PLL_ERAY Status Register */
+ Ifx_SCU_PLLERAYCON0 PLLERAYCON0; /**< \brief 28, PLL_ERAY Configuration 0 Register */
+ Ifx_SCU_PLLERAYCON1 PLLERAYCON1; /**< \brief 2C, PLL_ERAY Configuration 1 Register */
+ Ifx_SCU_CCUCON0 CCUCON0; /**< \brief 30, CCU Clock Control Register 0 */
+ Ifx_SCU_CCUCON1 CCUCON1; /**< \brief 34, CCU Clock Control Register 1 */
+ Ifx_SCU_FDR FDR; /**< \brief 38, Fractional Divider Register */
+ Ifx_SCU_EXTCON EXTCON; /**< \brief 3C, External Clock Control Register */
+ Ifx_SCU_CCUCON2 CCUCON2; /**< \brief 40, CCU Clock Control Register 2 */
+ Ifx_SCU_CCUCON3 CCUCON3; /**< \brief 44, CCU Clock Control Register 3 */
+ Ifx_SCU_CCUCON4 CCUCON4; /**< \brief 48, CCU Clock Control Register 4 */
+ Ifx_SCU_CCUCON5 CCUCON5; /**< \brief 4C, CCU Clock Control Register 5 */
+ Ifx_SCU_RSTSTAT RSTSTAT; /**< \brief 50, Reset Status Register */
+ unsigned char reserved_54[4]; /**< \brief 54, \internal Reserved */
+ Ifx_SCU_RSTCON RSTCON; /**< \brief 58, Reset Configuration Register */
+ Ifx_SCU_ARSTDIS ARSTDIS; /**< \brief 5C, Application Reset Disable Register */
+ Ifx_SCU_SWRSTCON SWRSTCON; /**< \brief 60, Software Reset Configuration Register */
+ Ifx_SCU_RSTCON2 RSTCON2; /**< \brief 64, Additional Reset Control Register */
+ unsigned char reserved_68[4]; /**< \brief 68, \internal Reserved */
+ Ifx_SCU_EVRRSTCON EVRRSTCON; /**< \brief 6C, EVR Reset Control Register */
+ Ifx_SCU_ESRCFG ESRCFG[2]; /**< \brief 70, ESR Input Configuration Register */
+ Ifx_SCU_ESROCFG ESROCFG; /**< \brief 78, ESR Output Configuration Register */
+ Ifx_SCU_SYSCON SYSCON; /**< \brief 7C, System Control Register */
+ Ifx_SCU_CCUCON6 CCUCON6; /**< \brief 80, CCU Clock Control Register 6 */
+ Ifx_SCU_CCUCON7 CCUCON7; /**< \brief 84, CCU Clock Control Register 7 */
+ unsigned char reserved_88[20]; /**< \brief 88, \internal Reserved */
+ Ifx_SCU_PDR PDR; /**< \brief 9C, ESR Pad Driver Mode Register */
+ Ifx_SCU_IOCR IOCR; /**< \brief A0, Input/Output Control Register */
+ Ifx_SCU_OUT OUT; /**< \brief A4, ESR Output Register */
+ Ifx_SCU_OMR OMR; /**< \brief A8, ESR Output Modification Register */
+ Ifx_SCU_IN IN; /**< \brief AC, ESR Input Register */
+ Ifx_SCU_EVRSTAT EVRSTAT; /**< \brief B0, EVR Status Register */
+ Ifx_SCU_EVRDVSTAT EVRDVSTAT; /**< \brief B4, EVR Status Register for Voltage Scaling */
+ Ifx_SCU_EVR13CON EVR13CON; /**< \brief B8, EVR13 Control Register */
+ Ifx_SCU_EVR33CON EVR33CON; /**< \brief BC, EVR33 Control Register */
+ Ifx_SCU_STSTAT STSTAT; /**< \brief C0, Start-up Status Register */
+ unsigned char reserved_C4[4]; /**< \brief C4, \internal Reserved */
+ Ifx_SCU_PMSWCR0 PMSWCR0; /**< \brief C8, Standby and Wake-up Control Register 0 */
+ Ifx_SCU_PMSWSTAT PMSWSTAT; /**< \brief CC, Standby and Wake-up Status Flag Register */
+ Ifx_SCU_PMSWSTATCLR PMSWSTATCLR; /**< \brief D0, Standby and Wake-up Status Clear Register */
+ Ifx_SCU_PMCSR PMCSR[2]; /**< \brief D4, Power Management Control and Status Register */
+ unsigned char reserved_DC[4]; /**< \brief DC, \internal Reserved */
+ Ifx_SCU_DTSSTAT DTSSTAT; /**< \brief E0, Die Temperature Sensor Status Register */
+ Ifx_SCU_DTSCON DTSCON; /**< \brief E4, Die Temperature Sensor Control Register */
+ Ifx_SCU_PMSWCR1 PMSWCR1; /**< \brief E8, Standby and Wake-up Control Register 1 */
+ Ifx_SCU_PMSWCR2 PMSWCR2; /**< \brief EC, Standby and Wake-up Control Register 2 */
+ Ifx_SCU_WDTS WDTS; /**< \brief F0, Safety watchdog */
+ Ifx_SCU_EMSR EMSR; /**< \brief FC, Emergency Stop Register */
+ Ifx_SCU_WDTCPU WDTCPU[2]; /**< \brief 100, CPU watchdogs */
+ unsigned char reserved_118[12]; /**< \brief 118, \internal Reserved */
+ Ifx_SCU_TRAPSTAT TRAPSTAT; /**< \brief 124, Trap Status Register */
+ Ifx_SCU_TRAPSET TRAPSET; /**< \brief 128, Trap Set Register */
+ Ifx_SCU_TRAPCLR TRAPCLR; /**< \brief 12C, Trap Clear Register */
+ Ifx_SCU_TRAPDIS TRAPDIS; /**< \brief 130, Trap Disable Register */
+ unsigned char reserved_134[4]; /**< \brief 134, \internal Reserved */
+ Ifx_SCU_LCLCON LCLCON1; /**< \brief 138, LCL CPU1 Control Register */
+ Ifx_SCU_LCLTEST LCLTEST; /**< \brief 13C, LCL Test Register */
+ Ifx_SCU_CHIPID CHIPID; /**< \brief 140, Chip Identification Register */
+ Ifx_SCU_MANID MANID; /**< \brief 144, Manufacturer Identification Register */
+ unsigned char reserved_148[8]; /**< \brief 148, \internal Reserved */
+ Ifx_SCU_SAFECON SAFECON; /**< \brief 150, Safety Heartbeat Register */
+ unsigned char reserved_154[16]; /**< \brief 154, \internal Reserved */
+ Ifx_SCU_LBISTCTRL0 LBISTCTRL0; /**< \brief 164, Logic BIST Control 0 Register */
+ Ifx_SCU_LBISTCTRL1 LBISTCTRL1; /**< \brief 168, Logic BIST Control 1 Register */
+ Ifx_SCU_LBISTCTRL2 LBISTCTRL2; /**< \brief 16C, Logic BIST Control 2 Register */
+ unsigned char reserved_170[28]; /**< \brief 170, \internal Reserved */
+ Ifx_SCU_PDISC PDISC; /**< \brief 18C, Pad Disable Control Register */
+ unsigned char reserved_190[8]; /**< \brief 190, \internal Reserved */
+ Ifx_SCU_EVRTRIM EVRTRIM; /**< \brief 198, EVR Trim Register */
+ Ifx_SCU_EVRADCSTAT EVRADCSTAT; /**< \brief 19C, EVR ADC Status Register */
+ Ifx_SCU_EVRUVMON EVRUVMON; /**< \brief 1A0, EVR Under-voltage Configuration Register */
+ Ifx_SCU_EVROVMON EVROVMON; /**< \brief 1A4, EVR Over-voltage Configuration Register */
+ Ifx_SCU_EVRMONCTRL EVRMONCTRL; /**< \brief 1A8, EVR Monitor Control Register */
+ unsigned char reserved_1AC[4]; /**< \brief 1AC, \internal Reserved */
+ Ifx_SCU_EVRSDCTRL1 EVRSDCTRL1; /**< \brief 1B0, EVR13 SD Control Register 1 */
+ Ifx_SCU_EVRSDCTRL2 EVRSDCTRL2; /**< \brief 1B4, EVR13 SD Control Register 2 */
+ Ifx_SCU_EVRSDCTRL3 EVRSDCTRL3; /**< \brief 1B8, EVR13 SD Control Register 3 */
+ Ifx_SCU_EVRSDCTRL4 EVRSDCTRL4; /**< \brief 1BC, EVR13 SD Control Register 4 */
+ Ifx_SCU_EVRSDCOEFF1 EVRSDCOEFF1; /**< \brief 1C0, EVR13 SD Coefficient Register 1 */
+ Ifx_SCU_EVRSDCOEFF2 EVRSDCOEFF2; /**< \brief 1C4, EVR13 SD Coefficient Register 2 */
+ Ifx_SCU_EVRSDCOEFF3 EVRSDCOEFF3; /**< \brief 1C8, EVR13 SD Coefficient Register 3 */
+ Ifx_SCU_EVRSDCOEFF4 EVRSDCOEFF4; /**< \brief 1CC, EVR13 SD Coefficient Register 4 */
+ Ifx_SCU_EVRSDCOEFF5 EVRSDCOEFF5; /**< \brief 1D0, EVR13 SD Coefficient Register 5 */
+ Ifx_SCU_EVRSDCOEFF6 EVRSDCOEFF6; /**< \brief 1D4, EVR13 SD Coefficient Register 6 */
+ Ifx_SCU_EVROSCCTRL EVROSCCTRL; /**< \brief 1D8, EVR Oscillator & Bandgap Register */
+ unsigned char reserved_1DC[4]; /**< \brief 1DC, \internal Reserved */
+ Ifx_SCU_OVCENABLE OVCENABLE; /**< \brief 1E0, Overlay Enable Register */
+ Ifx_SCU_OVCCON OVCCON; /**< \brief 1E4, Overlay Control Register */
+ unsigned char reserved_1E8[40]; /**< \brief 1E8, \internal Reserved */
+ Ifx_SCU_EICR EICR[4]; /**< \brief 210, External Input Channel Register */
+ Ifx_SCU_EIFR EIFR; /**< \brief 220, External Input Flag Register */
+ Ifx_SCU_FMR FMR; /**< \brief 224, Flag Modification Register */
+ Ifx_SCU_PDRR PDRR; /**< \brief 228, Pattern Detection Result Register */
+ Ifx_SCU_IGCR IGCR[4]; /**< \brief 22C, Flag Gating Register */
+ unsigned char reserved_23C[4]; /**< \brief 23C, \internal Reserved */
+ Ifx_SCU_DTSLIM DTSLIM; /**< \brief 240, Die Temperature Sensor Limit Register */
+ unsigned char reserved_244[436]; /**< \brief 244, \internal Reserved */
+ Ifx_SCU_ACCEN1 ACCEN1; /**< \brief 3F8, Access Enable Register 1 */
+ Ifx_SCU_ACCEN0 ACCEN0; /**< \brief 3FC, Access Enable Register 0 */
+} Ifx_SCU;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXSCU_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSent_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSent_bf.h
new file mode 100644
index 0000000..97b58ed
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSent_bf.h
@@ -0,0 +1,1674 @@
+/**
+ * \file IfxSent_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Sent_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Sent
+ *
+ */
+#ifndef IFXSENT_BF_H
+#define IFXSENT_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Sent_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN0 */
+#define IFX_SENT_ACCEN0_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN0 */
+#define IFX_SENT_ACCEN0_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN0 */
+#define IFX_SENT_ACCEN0_EN0_OFF (0u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN10 */
+#define IFX_SENT_ACCEN0_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN10 */
+#define IFX_SENT_ACCEN0_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN10 */
+#define IFX_SENT_ACCEN0_EN10_OFF (10u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN11 */
+#define IFX_SENT_ACCEN0_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN11 */
+#define IFX_SENT_ACCEN0_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN11 */
+#define IFX_SENT_ACCEN0_EN11_OFF (11u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN12 */
+#define IFX_SENT_ACCEN0_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN12 */
+#define IFX_SENT_ACCEN0_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN12 */
+#define IFX_SENT_ACCEN0_EN12_OFF (12u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN13 */
+#define IFX_SENT_ACCEN0_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN13 */
+#define IFX_SENT_ACCEN0_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN13 */
+#define IFX_SENT_ACCEN0_EN13_OFF (13u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN14 */
+#define IFX_SENT_ACCEN0_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN14 */
+#define IFX_SENT_ACCEN0_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN14 */
+#define IFX_SENT_ACCEN0_EN14_OFF (14u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN15 */
+#define IFX_SENT_ACCEN0_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN15 */
+#define IFX_SENT_ACCEN0_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN15 */
+#define IFX_SENT_ACCEN0_EN15_OFF (15u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN16 */
+#define IFX_SENT_ACCEN0_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN16 */
+#define IFX_SENT_ACCEN0_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN16 */
+#define IFX_SENT_ACCEN0_EN16_OFF (16u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN17 */
+#define IFX_SENT_ACCEN0_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN17 */
+#define IFX_SENT_ACCEN0_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN17 */
+#define IFX_SENT_ACCEN0_EN17_OFF (17u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN18 */
+#define IFX_SENT_ACCEN0_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN18 */
+#define IFX_SENT_ACCEN0_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN18 */
+#define IFX_SENT_ACCEN0_EN18_OFF (18u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN19 */
+#define IFX_SENT_ACCEN0_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN19 */
+#define IFX_SENT_ACCEN0_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN19 */
+#define IFX_SENT_ACCEN0_EN19_OFF (19u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN1 */
+#define IFX_SENT_ACCEN0_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN1 */
+#define IFX_SENT_ACCEN0_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN1 */
+#define IFX_SENT_ACCEN0_EN1_OFF (1u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN20 */
+#define IFX_SENT_ACCEN0_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN20 */
+#define IFX_SENT_ACCEN0_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN20 */
+#define IFX_SENT_ACCEN0_EN20_OFF (20u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN21 */
+#define IFX_SENT_ACCEN0_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN21 */
+#define IFX_SENT_ACCEN0_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN21 */
+#define IFX_SENT_ACCEN0_EN21_OFF (21u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN22 */
+#define IFX_SENT_ACCEN0_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN22 */
+#define IFX_SENT_ACCEN0_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN22 */
+#define IFX_SENT_ACCEN0_EN22_OFF (22u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN23 */
+#define IFX_SENT_ACCEN0_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN23 */
+#define IFX_SENT_ACCEN0_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN23 */
+#define IFX_SENT_ACCEN0_EN23_OFF (23u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN24 */
+#define IFX_SENT_ACCEN0_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN24 */
+#define IFX_SENT_ACCEN0_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN24 */
+#define IFX_SENT_ACCEN0_EN24_OFF (24u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN25 */
+#define IFX_SENT_ACCEN0_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN25 */
+#define IFX_SENT_ACCEN0_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN25 */
+#define IFX_SENT_ACCEN0_EN25_OFF (25u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN26 */
+#define IFX_SENT_ACCEN0_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN26 */
+#define IFX_SENT_ACCEN0_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN26 */
+#define IFX_SENT_ACCEN0_EN26_OFF (26u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN27 */
+#define IFX_SENT_ACCEN0_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN27 */
+#define IFX_SENT_ACCEN0_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN27 */
+#define IFX_SENT_ACCEN0_EN27_OFF (27u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN28 */
+#define IFX_SENT_ACCEN0_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN28 */
+#define IFX_SENT_ACCEN0_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN28 */
+#define IFX_SENT_ACCEN0_EN28_OFF (28u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN29 */
+#define IFX_SENT_ACCEN0_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN29 */
+#define IFX_SENT_ACCEN0_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN29 */
+#define IFX_SENT_ACCEN0_EN29_OFF (29u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN2 */
+#define IFX_SENT_ACCEN0_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN2 */
+#define IFX_SENT_ACCEN0_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN2 */
+#define IFX_SENT_ACCEN0_EN2_OFF (2u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN30 */
+#define IFX_SENT_ACCEN0_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN30 */
+#define IFX_SENT_ACCEN0_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN30 */
+#define IFX_SENT_ACCEN0_EN30_OFF (30u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN31 */
+#define IFX_SENT_ACCEN0_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN31 */
+#define IFX_SENT_ACCEN0_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN31 */
+#define IFX_SENT_ACCEN0_EN31_OFF (31u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN3 */
+#define IFX_SENT_ACCEN0_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN3 */
+#define IFX_SENT_ACCEN0_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN3 */
+#define IFX_SENT_ACCEN0_EN3_OFF (3u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN4 */
+#define IFX_SENT_ACCEN0_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN4 */
+#define IFX_SENT_ACCEN0_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN4 */
+#define IFX_SENT_ACCEN0_EN4_OFF (4u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN5 */
+#define IFX_SENT_ACCEN0_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN5 */
+#define IFX_SENT_ACCEN0_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN5 */
+#define IFX_SENT_ACCEN0_EN5_OFF (5u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN6 */
+#define IFX_SENT_ACCEN0_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN6 */
+#define IFX_SENT_ACCEN0_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN6 */
+#define IFX_SENT_ACCEN0_EN6_OFF (6u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN7 */
+#define IFX_SENT_ACCEN0_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN7 */
+#define IFX_SENT_ACCEN0_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN7 */
+#define IFX_SENT_ACCEN0_EN7_OFF (7u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN8 */
+#define IFX_SENT_ACCEN0_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN8 */
+#define IFX_SENT_ACCEN0_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN8 */
+#define IFX_SENT_ACCEN0_EN8_OFF (8u)
+
+/** \brief Length for Ifx_SENT_ACCEN0_Bits.EN9 */
+#define IFX_SENT_ACCEN0_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_ACCEN0_Bits.EN9 */
+#define IFX_SENT_ACCEN0_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_ACCEN0_Bits.EN9 */
+#define IFX_SENT_ACCEN0_EN9_OFF (9u)
+
+/** \brief Length for Ifx_SENT_CH_CFDR_Bits.DIV */
+#define IFX_SENT_CH_CFDR_DIV_LEN (12u)
+
+/** \brief Mask for Ifx_SENT_CH_CFDR_Bits.DIV */
+#define IFX_SENT_CH_CFDR_DIV_MSK (0xfffu)
+
+/** \brief Offset for Ifx_SENT_CH_CFDR_Bits.DIV */
+#define IFX_SENT_CH_CFDR_DIV_OFF (0u)
+
+/** \brief Length for Ifx_SENT_CH_CFDR_Bits.DIVM */
+#define IFX_SENT_CH_CFDR_DIVM_LEN (12u)
+
+/** \brief Mask for Ifx_SENT_CH_CFDR_Bits.DIVM */
+#define IFX_SENT_CH_CFDR_DIVM_MSK (0xfffu)
+
+/** \brief Offset for Ifx_SENT_CH_CFDR_Bits.DIVM */
+#define IFX_SENT_CH_CFDR_DIVM_OFF (16u)
+
+/** \brief Length for Ifx_SENT_CH_CPDR_Bits.PDIV */
+#define IFX_SENT_CH_CPDR_PDIV_LEN (12u)
+
+/** \brief Mask for Ifx_SENT_CH_CPDR_Bits.PDIV */
+#define IFX_SENT_CH_CPDR_PDIV_MSK (0xfffu)
+
+/** \brief Offset for Ifx_SENT_CH_CPDR_Bits.PDIV */
+#define IFX_SENT_CH_CPDR_PDIV_OFF (0u)
+
+/** \brief Length for Ifx_SENT_CH_INP_Bits.ERRI */
+#define IFX_SENT_CH_INP_ERRI_LEN (4u)
+
+/** \brief Mask for Ifx_SENT_CH_INP_Bits.ERRI */
+#define IFX_SENT_CH_INP_ERRI_MSK (0xfu)
+
+/** \brief Offset for Ifx_SENT_CH_INP_Bits.ERRI */
+#define IFX_SENT_CH_INP_ERRI_OFF (20u)
+
+/** \brief Length for Ifx_SENT_CH_INP_Bits.RBI */
+#define IFX_SENT_CH_INP_RBI_LEN (4u)
+
+/** \brief Mask for Ifx_SENT_CH_INP_Bits.RBI */
+#define IFX_SENT_CH_INP_RBI_MSK (0xfu)
+
+/** \brief Offset for Ifx_SENT_CH_INP_Bits.RBI */
+#define IFX_SENT_CH_INP_RBI_OFF (8u)
+
+/** \brief Length for Ifx_SENT_CH_INP_Bits.RDI */
+#define IFX_SENT_CH_INP_RDI_LEN (4u)
+
+/** \brief Mask for Ifx_SENT_CH_INP_Bits.RDI */
+#define IFX_SENT_CH_INP_RDI_MSK (0xfu)
+
+/** \brief Offset for Ifx_SENT_CH_INP_Bits.RDI */
+#define IFX_SENT_CH_INP_RDI_OFF (4u)
+
+/** \brief Length for Ifx_SENT_CH_INP_Bits.RSI */
+#define IFX_SENT_CH_INP_RSI_LEN (4u)
+
+/** \brief Mask for Ifx_SENT_CH_INP_Bits.RSI */
+#define IFX_SENT_CH_INP_RSI_MSK (0xfu)
+
+/** \brief Offset for Ifx_SENT_CH_INP_Bits.RSI */
+#define IFX_SENT_CH_INP_RSI_OFF (0u)
+
+/** \brief Length for Ifx_SENT_CH_INP_Bits.SDI */
+#define IFX_SENT_CH_INP_SDI_LEN (4u)
+
+/** \brief Mask for Ifx_SENT_CH_INP_Bits.SDI */
+#define IFX_SENT_CH_INP_SDI_MSK (0xfu)
+
+/** \brief Offset for Ifx_SENT_CH_INP_Bits.SDI */
+#define IFX_SENT_CH_INP_SDI_OFF (24u)
+
+/** \brief Length for Ifx_SENT_CH_INP_Bits.TBI */
+#define IFX_SENT_CH_INP_TBI_LEN (4u)
+
+/** \brief Mask for Ifx_SENT_CH_INP_Bits.TBI */
+#define IFX_SENT_CH_INP_TBI_MSK (0xfu)
+
+/** \brief Offset for Ifx_SENT_CH_INP_Bits.TBI */
+#define IFX_SENT_CH_INP_TBI_OFF (16u)
+
+/** \brief Length for Ifx_SENT_CH_INP_Bits.TDI */
+#define IFX_SENT_CH_INP_TDI_LEN (4u)
+
+/** \brief Mask for Ifx_SENT_CH_INP_Bits.TDI */
+#define IFX_SENT_CH_INP_TDI_MSK (0xfu)
+
+/** \brief Offset for Ifx_SENT_CH_INP_Bits.TDI */
+#define IFX_SENT_CH_INP_TDI_OFF (12u)
+
+/** \brief Length for Ifx_SENT_CH_INP_Bits.WDI */
+#define IFX_SENT_CH_INP_WDI_LEN (4u)
+
+/** \brief Mask for Ifx_SENT_CH_INP_Bits.WDI */
+#define IFX_SENT_CH_INP_WDI_MSK (0xfu)
+
+/** \brief Offset for Ifx_SENT_CH_INP_Bits.WDI */
+#define IFX_SENT_CH_INP_WDI_OFF (28u)
+
+/** \brief Length for Ifx_SENT_CH_INTCLR_Bits.CRCI */
+#define IFX_SENT_CH_INTCLR_CRCI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTCLR_Bits.CRCI */
+#define IFX_SENT_CH_INTCLR_CRCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTCLR_Bits.CRCI */
+#define IFX_SENT_CH_INTCLR_CRCI_OFF (9u)
+
+/** \brief Length for Ifx_SENT_CH_INTCLR_Bits.FDI */
+#define IFX_SENT_CH_INTCLR_FDI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTCLR_Bits.FDI */
+#define IFX_SENT_CH_INTCLR_FDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTCLR_Bits.FDI */
+#define IFX_SENT_CH_INTCLR_FDI_OFF (6u)
+
+/** \brief Length for Ifx_SENT_CH_INTCLR_Bits.FRI */
+#define IFX_SENT_CH_INTCLR_FRI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTCLR_Bits.FRI */
+#define IFX_SENT_CH_INTCLR_FRI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTCLR_Bits.FRI */
+#define IFX_SENT_CH_INTCLR_FRI_OFF (5u)
+
+/** \brief Length for Ifx_SENT_CH_INTCLR_Bits.NNI */
+#define IFX_SENT_CH_INTCLR_NNI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTCLR_Bits.NNI */
+#define IFX_SENT_CH_INTCLR_NNI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTCLR_Bits.NNI */
+#define IFX_SENT_CH_INTCLR_NNI_OFF (7u)
+
+/** \brief Length for Ifx_SENT_CH_INTCLR_Bits.NVI */
+#define IFX_SENT_CH_INTCLR_NVI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTCLR_Bits.NVI */
+#define IFX_SENT_CH_INTCLR_NVI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTCLR_Bits.NVI */
+#define IFX_SENT_CH_INTCLR_NVI_OFF (8u)
+
+/** \brief Length for Ifx_SENT_CH_INTCLR_Bits.RBI */
+#define IFX_SENT_CH_INTCLR_RBI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTCLR_Bits.RBI */
+#define IFX_SENT_CH_INTCLR_RBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTCLR_Bits.RBI */
+#define IFX_SENT_CH_INTCLR_RBI_OFF (2u)
+
+/** \brief Length for Ifx_SENT_CH_INTCLR_Bits.RDI */
+#define IFX_SENT_CH_INTCLR_RDI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTCLR_Bits.RDI */
+#define IFX_SENT_CH_INTCLR_RDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTCLR_Bits.RDI */
+#define IFX_SENT_CH_INTCLR_RDI_OFF (1u)
+
+/** \brief Length for Ifx_SENT_CH_INTCLR_Bits.RSI */
+#define IFX_SENT_CH_INTCLR_RSI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTCLR_Bits.RSI */
+#define IFX_SENT_CH_INTCLR_RSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTCLR_Bits.RSI */
+#define IFX_SENT_CH_INTCLR_RSI_OFF (0u)
+
+/** \brief Length for Ifx_SENT_CH_INTCLR_Bits.SCRI */
+#define IFX_SENT_CH_INTCLR_SCRI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTCLR_Bits.SCRI */
+#define IFX_SENT_CH_INTCLR_SCRI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTCLR_Bits.SCRI */
+#define IFX_SENT_CH_INTCLR_SCRI_OFF (12u)
+
+/** \brief Length for Ifx_SENT_CH_INTCLR_Bits.SDI */
+#define IFX_SENT_CH_INTCLR_SDI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTCLR_Bits.SDI */
+#define IFX_SENT_CH_INTCLR_SDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTCLR_Bits.SDI */
+#define IFX_SENT_CH_INTCLR_SDI_OFF (11u)
+
+/** \brief Length for Ifx_SENT_CH_INTCLR_Bits.TBI */
+#define IFX_SENT_CH_INTCLR_TBI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTCLR_Bits.TBI */
+#define IFX_SENT_CH_INTCLR_TBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTCLR_Bits.TBI */
+#define IFX_SENT_CH_INTCLR_TBI_OFF (4u)
+
+/** \brief Length for Ifx_SENT_CH_INTCLR_Bits.TDI */
+#define IFX_SENT_CH_INTCLR_TDI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTCLR_Bits.TDI */
+#define IFX_SENT_CH_INTCLR_TDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTCLR_Bits.TDI */
+#define IFX_SENT_CH_INTCLR_TDI_OFF (3u)
+
+/** \brief Length for Ifx_SENT_CH_INTCLR_Bits.WDI */
+#define IFX_SENT_CH_INTCLR_WDI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTCLR_Bits.WDI */
+#define IFX_SENT_CH_INTCLR_WDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTCLR_Bits.WDI */
+#define IFX_SENT_CH_INTCLR_WDI_OFF (13u)
+
+/** \brief Length for Ifx_SENT_CH_INTCLR_Bits.WSI */
+#define IFX_SENT_CH_INTCLR_WSI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTCLR_Bits.WSI */
+#define IFX_SENT_CH_INTCLR_WSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTCLR_Bits.WSI */
+#define IFX_SENT_CH_INTCLR_WSI_OFF (10u)
+
+/** \brief Length for Ifx_SENT_CH_INTEN_Bits.CRCI */
+#define IFX_SENT_CH_INTEN_CRCI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTEN_Bits.CRCI */
+#define IFX_SENT_CH_INTEN_CRCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTEN_Bits.CRCI */
+#define IFX_SENT_CH_INTEN_CRCI_OFF (9u)
+
+/** \brief Length for Ifx_SENT_CH_INTEN_Bits.FDI */
+#define IFX_SENT_CH_INTEN_FDI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTEN_Bits.FDI */
+#define IFX_SENT_CH_INTEN_FDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTEN_Bits.FDI */
+#define IFX_SENT_CH_INTEN_FDI_OFF (6u)
+
+/** \brief Length for Ifx_SENT_CH_INTEN_Bits.FRI */
+#define IFX_SENT_CH_INTEN_FRI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTEN_Bits.FRI */
+#define IFX_SENT_CH_INTEN_FRI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTEN_Bits.FRI */
+#define IFX_SENT_CH_INTEN_FRI_OFF (5u)
+
+/** \brief Length for Ifx_SENT_CH_INTEN_Bits.NNI */
+#define IFX_SENT_CH_INTEN_NNI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTEN_Bits.NNI */
+#define IFX_SENT_CH_INTEN_NNI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTEN_Bits.NNI */
+#define IFX_SENT_CH_INTEN_NNI_OFF (7u)
+
+/** \brief Length for Ifx_SENT_CH_INTEN_Bits.NVI */
+#define IFX_SENT_CH_INTEN_NVI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTEN_Bits.NVI */
+#define IFX_SENT_CH_INTEN_NVI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTEN_Bits.NVI */
+#define IFX_SENT_CH_INTEN_NVI_OFF (8u)
+
+/** \brief Length for Ifx_SENT_CH_INTEN_Bits.RBI */
+#define IFX_SENT_CH_INTEN_RBI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTEN_Bits.RBI */
+#define IFX_SENT_CH_INTEN_RBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTEN_Bits.RBI */
+#define IFX_SENT_CH_INTEN_RBI_OFF (2u)
+
+/** \brief Length for Ifx_SENT_CH_INTEN_Bits.RDI */
+#define IFX_SENT_CH_INTEN_RDI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTEN_Bits.RDI */
+#define IFX_SENT_CH_INTEN_RDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTEN_Bits.RDI */
+#define IFX_SENT_CH_INTEN_RDI_OFF (1u)
+
+/** \brief Length for Ifx_SENT_CH_INTEN_Bits.RSI */
+#define IFX_SENT_CH_INTEN_RSI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTEN_Bits.RSI */
+#define IFX_SENT_CH_INTEN_RSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTEN_Bits.RSI */
+#define IFX_SENT_CH_INTEN_RSI_OFF (0u)
+
+/** \brief Length for Ifx_SENT_CH_INTEN_Bits.SCRI */
+#define IFX_SENT_CH_INTEN_SCRI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTEN_Bits.SCRI */
+#define IFX_SENT_CH_INTEN_SCRI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTEN_Bits.SCRI */
+#define IFX_SENT_CH_INTEN_SCRI_OFF (12u)
+
+/** \brief Length for Ifx_SENT_CH_INTEN_Bits.SDI */
+#define IFX_SENT_CH_INTEN_SDI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTEN_Bits.SDI */
+#define IFX_SENT_CH_INTEN_SDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTEN_Bits.SDI */
+#define IFX_SENT_CH_INTEN_SDI_OFF (11u)
+
+/** \brief Length for Ifx_SENT_CH_INTEN_Bits.TBI */
+#define IFX_SENT_CH_INTEN_TBI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTEN_Bits.TBI */
+#define IFX_SENT_CH_INTEN_TBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTEN_Bits.TBI */
+#define IFX_SENT_CH_INTEN_TBI_OFF (4u)
+
+/** \brief Length for Ifx_SENT_CH_INTEN_Bits.TDI */
+#define IFX_SENT_CH_INTEN_TDI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTEN_Bits.TDI */
+#define IFX_SENT_CH_INTEN_TDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTEN_Bits.TDI */
+#define IFX_SENT_CH_INTEN_TDI_OFF (3u)
+
+/** \brief Length for Ifx_SENT_CH_INTEN_Bits.WDI */
+#define IFX_SENT_CH_INTEN_WDI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTEN_Bits.WDI */
+#define IFX_SENT_CH_INTEN_WDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTEN_Bits.WDI */
+#define IFX_SENT_CH_INTEN_WDI_OFF (13u)
+
+/** \brief Length for Ifx_SENT_CH_INTEN_Bits.WSI */
+#define IFX_SENT_CH_INTEN_WSI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTEN_Bits.WSI */
+#define IFX_SENT_CH_INTEN_WSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTEN_Bits.WSI */
+#define IFX_SENT_CH_INTEN_WSI_OFF (10u)
+
+/** \brief Length for Ifx_SENT_CH_INTSET_Bits.CRCI */
+#define IFX_SENT_CH_INTSET_CRCI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTSET_Bits.CRCI */
+#define IFX_SENT_CH_INTSET_CRCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTSET_Bits.CRCI */
+#define IFX_SENT_CH_INTSET_CRCI_OFF (9u)
+
+/** \brief Length for Ifx_SENT_CH_INTSET_Bits.FDI */
+#define IFX_SENT_CH_INTSET_FDI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTSET_Bits.FDI */
+#define IFX_SENT_CH_INTSET_FDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTSET_Bits.FDI */
+#define IFX_SENT_CH_INTSET_FDI_OFF (6u)
+
+/** \brief Length for Ifx_SENT_CH_INTSET_Bits.FRI */
+#define IFX_SENT_CH_INTSET_FRI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTSET_Bits.FRI */
+#define IFX_SENT_CH_INTSET_FRI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTSET_Bits.FRI */
+#define IFX_SENT_CH_INTSET_FRI_OFF (5u)
+
+/** \brief Length for Ifx_SENT_CH_INTSET_Bits.NNI */
+#define IFX_SENT_CH_INTSET_NNI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTSET_Bits.NNI */
+#define IFX_SENT_CH_INTSET_NNI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTSET_Bits.NNI */
+#define IFX_SENT_CH_INTSET_NNI_OFF (7u)
+
+/** \brief Length for Ifx_SENT_CH_INTSET_Bits.NVI */
+#define IFX_SENT_CH_INTSET_NVI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTSET_Bits.NVI */
+#define IFX_SENT_CH_INTSET_NVI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTSET_Bits.NVI */
+#define IFX_SENT_CH_INTSET_NVI_OFF (8u)
+
+/** \brief Length for Ifx_SENT_CH_INTSET_Bits.RBI */
+#define IFX_SENT_CH_INTSET_RBI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTSET_Bits.RBI */
+#define IFX_SENT_CH_INTSET_RBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTSET_Bits.RBI */
+#define IFX_SENT_CH_INTSET_RBI_OFF (2u)
+
+/** \brief Length for Ifx_SENT_CH_INTSET_Bits.RDI */
+#define IFX_SENT_CH_INTSET_RDI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTSET_Bits.RDI */
+#define IFX_SENT_CH_INTSET_RDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTSET_Bits.RDI */
+#define IFX_SENT_CH_INTSET_RDI_OFF (1u)
+
+/** \brief Length for Ifx_SENT_CH_INTSET_Bits.RSI */
+#define IFX_SENT_CH_INTSET_RSI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTSET_Bits.RSI */
+#define IFX_SENT_CH_INTSET_RSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTSET_Bits.RSI */
+#define IFX_SENT_CH_INTSET_RSI_OFF (0u)
+
+/** \brief Length for Ifx_SENT_CH_INTSET_Bits.SCRI */
+#define IFX_SENT_CH_INTSET_SCRI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTSET_Bits.SCRI */
+#define IFX_SENT_CH_INTSET_SCRI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTSET_Bits.SCRI */
+#define IFX_SENT_CH_INTSET_SCRI_OFF (12u)
+
+/** \brief Length for Ifx_SENT_CH_INTSET_Bits.SDI */
+#define IFX_SENT_CH_INTSET_SDI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTSET_Bits.SDI */
+#define IFX_SENT_CH_INTSET_SDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTSET_Bits.SDI */
+#define IFX_SENT_CH_INTSET_SDI_OFF (11u)
+
+/** \brief Length for Ifx_SENT_CH_INTSET_Bits.TBI */
+#define IFX_SENT_CH_INTSET_TBI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTSET_Bits.TBI */
+#define IFX_SENT_CH_INTSET_TBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTSET_Bits.TBI */
+#define IFX_SENT_CH_INTSET_TBI_OFF (4u)
+
+/** \brief Length for Ifx_SENT_CH_INTSET_Bits.TDI */
+#define IFX_SENT_CH_INTSET_TDI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTSET_Bits.TDI */
+#define IFX_SENT_CH_INTSET_TDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTSET_Bits.TDI */
+#define IFX_SENT_CH_INTSET_TDI_OFF (3u)
+
+/** \brief Length for Ifx_SENT_CH_INTSET_Bits.WDI */
+#define IFX_SENT_CH_INTSET_WDI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTSET_Bits.WDI */
+#define IFX_SENT_CH_INTSET_WDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTSET_Bits.WDI */
+#define IFX_SENT_CH_INTSET_WDI_OFF (13u)
+
+/** \brief Length for Ifx_SENT_CH_INTSET_Bits.WSI */
+#define IFX_SENT_CH_INTSET_WSI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTSET_Bits.WSI */
+#define IFX_SENT_CH_INTSET_WSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTSET_Bits.WSI */
+#define IFX_SENT_CH_INTSET_WSI_OFF (10u)
+
+/** \brief Length for Ifx_SENT_CH_INTSTAT_Bits.CRCI */
+#define IFX_SENT_CH_INTSTAT_CRCI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTSTAT_Bits.CRCI */
+#define IFX_SENT_CH_INTSTAT_CRCI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTSTAT_Bits.CRCI */
+#define IFX_SENT_CH_INTSTAT_CRCI_OFF (9u)
+
+/** \brief Length for Ifx_SENT_CH_INTSTAT_Bits.FDI */
+#define IFX_SENT_CH_INTSTAT_FDI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTSTAT_Bits.FDI */
+#define IFX_SENT_CH_INTSTAT_FDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTSTAT_Bits.FDI */
+#define IFX_SENT_CH_INTSTAT_FDI_OFF (6u)
+
+/** \brief Length for Ifx_SENT_CH_INTSTAT_Bits.FRI */
+#define IFX_SENT_CH_INTSTAT_FRI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTSTAT_Bits.FRI */
+#define IFX_SENT_CH_INTSTAT_FRI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTSTAT_Bits.FRI */
+#define IFX_SENT_CH_INTSTAT_FRI_OFF (5u)
+
+/** \brief Length for Ifx_SENT_CH_INTSTAT_Bits.NNI */
+#define IFX_SENT_CH_INTSTAT_NNI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTSTAT_Bits.NNI */
+#define IFX_SENT_CH_INTSTAT_NNI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTSTAT_Bits.NNI */
+#define IFX_SENT_CH_INTSTAT_NNI_OFF (7u)
+
+/** \brief Length for Ifx_SENT_CH_INTSTAT_Bits.NVI */
+#define IFX_SENT_CH_INTSTAT_NVI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTSTAT_Bits.NVI */
+#define IFX_SENT_CH_INTSTAT_NVI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTSTAT_Bits.NVI */
+#define IFX_SENT_CH_INTSTAT_NVI_OFF (8u)
+
+/** \brief Length for Ifx_SENT_CH_INTSTAT_Bits.RBI */
+#define IFX_SENT_CH_INTSTAT_RBI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTSTAT_Bits.RBI */
+#define IFX_SENT_CH_INTSTAT_RBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTSTAT_Bits.RBI */
+#define IFX_SENT_CH_INTSTAT_RBI_OFF (2u)
+
+/** \brief Length for Ifx_SENT_CH_INTSTAT_Bits.RDI */
+#define IFX_SENT_CH_INTSTAT_RDI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTSTAT_Bits.RDI */
+#define IFX_SENT_CH_INTSTAT_RDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTSTAT_Bits.RDI */
+#define IFX_SENT_CH_INTSTAT_RDI_OFF (1u)
+
+/** \brief Length for Ifx_SENT_CH_INTSTAT_Bits.RSI */
+#define IFX_SENT_CH_INTSTAT_RSI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTSTAT_Bits.RSI */
+#define IFX_SENT_CH_INTSTAT_RSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTSTAT_Bits.RSI */
+#define IFX_SENT_CH_INTSTAT_RSI_OFF (0u)
+
+/** \brief Length for Ifx_SENT_CH_INTSTAT_Bits.SCRI */
+#define IFX_SENT_CH_INTSTAT_SCRI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTSTAT_Bits.SCRI */
+#define IFX_SENT_CH_INTSTAT_SCRI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTSTAT_Bits.SCRI */
+#define IFX_SENT_CH_INTSTAT_SCRI_OFF (12u)
+
+/** \brief Length for Ifx_SENT_CH_INTSTAT_Bits.SDI */
+#define IFX_SENT_CH_INTSTAT_SDI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTSTAT_Bits.SDI */
+#define IFX_SENT_CH_INTSTAT_SDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTSTAT_Bits.SDI */
+#define IFX_SENT_CH_INTSTAT_SDI_OFF (11u)
+
+/** \brief Length for Ifx_SENT_CH_INTSTAT_Bits.TBI */
+#define IFX_SENT_CH_INTSTAT_TBI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTSTAT_Bits.TBI */
+#define IFX_SENT_CH_INTSTAT_TBI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTSTAT_Bits.TBI */
+#define IFX_SENT_CH_INTSTAT_TBI_OFF (4u)
+
+/** \brief Length for Ifx_SENT_CH_INTSTAT_Bits.TDI */
+#define IFX_SENT_CH_INTSTAT_TDI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTSTAT_Bits.TDI */
+#define IFX_SENT_CH_INTSTAT_TDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTSTAT_Bits.TDI */
+#define IFX_SENT_CH_INTSTAT_TDI_OFF (3u)
+
+/** \brief Length for Ifx_SENT_CH_INTSTAT_Bits.WDI */
+#define IFX_SENT_CH_INTSTAT_WDI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTSTAT_Bits.WDI */
+#define IFX_SENT_CH_INTSTAT_WDI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTSTAT_Bits.WDI */
+#define IFX_SENT_CH_INTSTAT_WDI_OFF (13u)
+
+/** \brief Length for Ifx_SENT_CH_INTSTAT_Bits.WSI */
+#define IFX_SENT_CH_INTSTAT_WSI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_INTSTAT_Bits.WSI */
+#define IFX_SENT_CH_INTSTAT_WSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_INTSTAT_Bits.WSI */
+#define IFX_SENT_CH_INTSTAT_WSI_OFF (10u)
+
+/** \brief Length for Ifx_SENT_CH_IOCR_Bits.ALTI */
+#define IFX_SENT_CH_IOCR_ALTI_LEN (2u)
+
+/** \brief Mask for Ifx_SENT_CH_IOCR_Bits.ALTI */
+#define IFX_SENT_CH_IOCR_ALTI_MSK (0x3u)
+
+/** \brief Offset for Ifx_SENT_CH_IOCR_Bits.ALTI */
+#define IFX_SENT_CH_IOCR_ALTI_OFF (0u)
+
+/** \brief Length for Ifx_SENT_CH_IOCR_Bits.CEC */
+#define IFX_SENT_CH_IOCR_CEC_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_IOCR_Bits.CEC */
+#define IFX_SENT_CH_IOCR_CEC_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_IOCR_Bits.CEC */
+#define IFX_SENT_CH_IOCR_CEC_OFF (10u)
+
+/** \brief Length for Ifx_SENT_CH_IOCR_Bits.CFEG */
+#define IFX_SENT_CH_IOCR_CFEG_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_IOCR_Bits.CFEG */
+#define IFX_SENT_CH_IOCR_CFEG_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_IOCR_Bits.CFEG */
+#define IFX_SENT_CH_IOCR_CFEG_OFF (15u)
+
+/** \brief Length for Ifx_SENT_CH_IOCR_Bits.CREG */
+#define IFX_SENT_CH_IOCR_CREG_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_IOCR_Bits.CREG */
+#define IFX_SENT_CH_IOCR_CREG_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_IOCR_Bits.CREG */
+#define IFX_SENT_CH_IOCR_CREG_OFF (14u)
+
+/** \brief Length for Ifx_SENT_CH_IOCR_Bits.CTR */
+#define IFX_SENT_CH_IOCR_CTR_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_IOCR_Bits.CTR */
+#define IFX_SENT_CH_IOCR_CTR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_IOCR_Bits.CTR */
+#define IFX_SENT_CH_IOCR_CTR_OFF (28u)
+
+/** \brief Length for Ifx_SENT_CH_IOCR_Bits.DEPTH */
+#define IFX_SENT_CH_IOCR_DEPTH_LEN (4u)
+
+/** \brief Mask for Ifx_SENT_CH_IOCR_Bits.DEPTH */
+#define IFX_SENT_CH_IOCR_DEPTH_MSK (0xfu)
+
+/** \brief Offset for Ifx_SENT_CH_IOCR_Bits.DEPTH */
+#define IFX_SENT_CH_IOCR_DEPTH_OFF (4u)
+
+/** \brief Length for Ifx_SENT_CH_IOCR_Bits.EC */
+#define IFX_SENT_CH_IOCR_EC_LEN (8u)
+
+/** \brief Mask for Ifx_SENT_CH_IOCR_Bits.EC */
+#define IFX_SENT_CH_IOCR_EC_MSK (0xffu)
+
+/** \brief Offset for Ifx_SENT_CH_IOCR_Bits.EC */
+#define IFX_SENT_CH_IOCR_EC_OFF (20u)
+
+/** \brief Length for Ifx_SENT_CH_IOCR_Bits.ETS */
+#define IFX_SENT_CH_IOCR_ETS_LEN (4u)
+
+/** \brief Mask for Ifx_SENT_CH_IOCR_Bits.ETS */
+#define IFX_SENT_CH_IOCR_ETS_MSK (0xfu)
+
+/** \brief Offset for Ifx_SENT_CH_IOCR_Bits.ETS */
+#define IFX_SENT_CH_IOCR_ETS_OFF (16u)
+
+/** \brief Length for Ifx_SENT_CH_IOCR_Bits.FEG */
+#define IFX_SENT_CH_IOCR_FEG_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_IOCR_Bits.FEG */
+#define IFX_SENT_CH_IOCR_FEG_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_IOCR_Bits.FEG */
+#define IFX_SENT_CH_IOCR_FEG_OFF (13u)
+
+/** \brief Length for Ifx_SENT_CH_IOCR_Bits.IIE */
+#define IFX_SENT_CH_IOCR_IIE_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_IOCR_Bits.IIE */
+#define IFX_SENT_CH_IOCR_IIE_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_IOCR_Bits.IIE */
+#define IFX_SENT_CH_IOCR_IIE_OFF (9u)
+
+/** \brief Length for Ifx_SENT_CH_IOCR_Bits.OIE */
+#define IFX_SENT_CH_IOCR_OIE_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_IOCR_Bits.OIE */
+#define IFX_SENT_CH_IOCR_OIE_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_IOCR_Bits.OIE */
+#define IFX_SENT_CH_IOCR_OIE_OFF (8u)
+
+/** \brief Length for Ifx_SENT_CH_IOCR_Bits.REG */
+#define IFX_SENT_CH_IOCR_REG_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_IOCR_Bits.REG */
+#define IFX_SENT_CH_IOCR_REG_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_IOCR_Bits.REG */
+#define IFX_SENT_CH_IOCR_REG_OFF (12u)
+
+/** \brief Length for Ifx_SENT_CH_IOCR_Bits.RXM */
+#define IFX_SENT_CH_IOCR_RXM_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_IOCR_Bits.RXM */
+#define IFX_SENT_CH_IOCR_RXM_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_IOCR_Bits.RXM */
+#define IFX_SENT_CH_IOCR_RXM_OFF (30u)
+
+/** \brief Length for Ifx_SENT_CH_IOCR_Bits.TRM */
+#define IFX_SENT_CH_IOCR_TRM_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_IOCR_Bits.TRM */
+#define IFX_SENT_CH_IOCR_TRM_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_IOCR_Bits.TRM */
+#define IFX_SENT_CH_IOCR_TRM_OFF (29u)
+
+/** \brief Length for Ifx_SENT_CH_IOCR_Bits.TXM */
+#define IFX_SENT_CH_IOCR_TXM_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_IOCR_Bits.TXM */
+#define IFX_SENT_CH_IOCR_TXM_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_IOCR_Bits.TXM */
+#define IFX_SENT_CH_IOCR_TXM_OFF (31u)
+
+/** \brief Length for Ifx_SENT_CH_RCR_Bits.ACE */
+#define IFX_SENT_CH_RCR_ACE_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_RCR_Bits.ACE */
+#define IFX_SENT_CH_RCR_ACE_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_RCR_Bits.ACE */
+#define IFX_SENT_CH_RCR_ACE_OFF (2u)
+
+/** \brief Length for Ifx_SENT_CH_RCR_Bits.CDIS */
+#define IFX_SENT_CH_RCR_CDIS_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_RCR_Bits.CDIS */
+#define IFX_SENT_CH_RCR_CDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_RCR_Bits.CDIS */
+#define IFX_SENT_CH_RCR_CDIS_OFF (6u)
+
+/** \brief Length for Ifx_SENT_CH_RCR_Bits.CEN */
+#define IFX_SENT_CH_RCR_CEN_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_RCR_Bits.CEN */
+#define IFX_SENT_CH_RCR_CEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_RCR_Bits.CEN */
+#define IFX_SENT_CH_RCR_CEN_OFF (0u)
+
+/** \brief Length for Ifx_SENT_CH_RCR_Bits.CFC */
+#define IFX_SENT_CH_RCR_CFC_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_RCR_Bits.CFC */
+#define IFX_SENT_CH_RCR_CFC_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_RCR_Bits.CFC */
+#define IFX_SENT_CH_RCR_CFC_OFF (7u)
+
+/** \brief Length for Ifx_SENT_CH_RCR_Bits.CRZ */
+#define IFX_SENT_CH_RCR_CRZ_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_RCR_Bits.CRZ */
+#define IFX_SENT_CH_RCR_CRZ_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_RCR_Bits.CRZ */
+#define IFX_SENT_CH_RCR_CRZ_OFF (16u)
+
+/** \brief Length for Ifx_SENT_CH_RCR_Bits.ESF */
+#define IFX_SENT_CH_RCR_ESF_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_RCR_Bits.ESF */
+#define IFX_SENT_CH_RCR_ESF_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_RCR_Bits.ESF */
+#define IFX_SENT_CH_RCR_ESF_OFF (17u)
+
+/** \brief Length for Ifx_SENT_CH_RCR_Bits.FRL */
+#define IFX_SENT_CH_RCR_FRL_LEN (8u)
+
+/** \brief Mask for Ifx_SENT_CH_RCR_Bits.FRL */
+#define IFX_SENT_CH_RCR_FRL_MSK (0xffu)
+
+/** \brief Offset for Ifx_SENT_CH_RCR_Bits.FRL */
+#define IFX_SENT_CH_RCR_FRL_OFF (8u)
+
+/** \brief Length for Ifx_SENT_CH_RCR_Bits.IDE */
+#define IFX_SENT_CH_RCR_IDE_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_RCR_Bits.IDE */
+#define IFX_SENT_CH_RCR_IDE_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_RCR_Bits.IDE */
+#define IFX_SENT_CH_RCR_IDE_OFF (18u)
+
+/** \brief Length for Ifx_SENT_CH_RCR_Bits.IEP */
+#define IFX_SENT_CH_RCR_IEP_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_RCR_Bits.IEP */
+#define IFX_SENT_CH_RCR_IEP_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_RCR_Bits.IEP */
+#define IFX_SENT_CH_RCR_IEP_OFF (1u)
+
+/** \brief Length for Ifx_SENT_CH_RCR_Bits.SCDIS */
+#define IFX_SENT_CH_RCR_SCDIS_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_RCR_Bits.SCDIS */
+#define IFX_SENT_CH_RCR_SCDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_RCR_Bits.SCDIS */
+#define IFX_SENT_CH_RCR_SCDIS_OFF (5u)
+
+/** \brief Length for Ifx_SENT_CH_RCR_Bits.SDP */
+#define IFX_SENT_CH_RCR_SDP_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_RCR_Bits.SDP */
+#define IFX_SENT_CH_RCR_SDP_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_RCR_Bits.SDP */
+#define IFX_SENT_CH_RCR_SDP_OFF (4u)
+
+/** \brief Length for Ifx_SENT_CH_RCR_Bits.SNI */
+#define IFX_SENT_CH_RCR_SNI_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_RCR_Bits.SNI */
+#define IFX_SENT_CH_RCR_SNI_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_RCR_Bits.SNI */
+#define IFX_SENT_CH_RCR_SNI_OFF (3u)
+
+/** \brief Length for Ifx_SENT_CH_RCR_Bits.SUSEN */
+#define IFX_SENT_CH_RCR_SUSEN_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_RCR_Bits.SUSEN */
+#define IFX_SENT_CH_RCR_SUSEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_RCR_Bits.SUSEN */
+#define IFX_SENT_CH_RCR_SUSEN_OFF (19u)
+
+/** \brief Length for Ifx_SENT_CH_RSR_Bits.CRC */
+#define IFX_SENT_CH_RSR_CRC_LEN (4u)
+
+/** \brief Mask for Ifx_SENT_CH_RSR_Bits.CRC */
+#define IFX_SENT_CH_RSR_CRC_MSK (0xfu)
+
+/** \brief Offset for Ifx_SENT_CH_RSR_Bits.CRC */
+#define IFX_SENT_CH_RSR_CRC_OFF (0u)
+
+/** \brief Length for Ifx_SENT_CH_RSR_Bits.CST */
+#define IFX_SENT_CH_RSR_CST_LEN (2u)
+
+/** \brief Mask for Ifx_SENT_CH_RSR_Bits.CST */
+#define IFX_SENT_CH_RSR_CST_MSK (0x3u)
+
+/** \brief Offset for Ifx_SENT_CH_RSR_Bits.CST */
+#define IFX_SENT_CH_RSR_CST_OFF (4u)
+
+/** \brief Length for Ifx_SENT_CH_RSR_Bits.SCN */
+#define IFX_SENT_CH_RSR_SCN_LEN (4u)
+
+/** \brief Mask for Ifx_SENT_CH_RSR_Bits.SCN */
+#define IFX_SENT_CH_RSR_SCN_MSK (0xfu)
+
+/** \brief Offset for Ifx_SENT_CH_RSR_Bits.SCN */
+#define IFX_SENT_CH_RSR_SCN_OFF (8u)
+
+/** \brief Length for Ifx_SENT_CH_SCR_Bits.BASE */
+#define IFX_SENT_CH_SCR_BASE_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_SCR_Bits.BASE */
+#define IFX_SENT_CH_SCR_BASE_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_SCR_Bits.BASE */
+#define IFX_SENT_CH_SCR_BASE_OFF (14u)
+
+/** \brief Length for Ifx_SENT_CH_SCR_Bits.DEL */
+#define IFX_SENT_CH_SCR_DEL_LEN (6u)
+
+/** \brief Mask for Ifx_SENT_CH_SCR_Bits.DEL */
+#define IFX_SENT_CH_SCR_DEL_MSK (0x3fu)
+
+/** \brief Offset for Ifx_SENT_CH_SCR_Bits.DEL */
+#define IFX_SENT_CH_SCR_DEL_OFF (8u)
+
+/** \brief Length for Ifx_SENT_CH_SCR_Bits.PLEN */
+#define IFX_SENT_CH_SCR_PLEN_LEN (6u)
+
+/** \brief Mask for Ifx_SENT_CH_SCR_Bits.PLEN */
+#define IFX_SENT_CH_SCR_PLEN_MSK (0x3fu)
+
+/** \brief Offset for Ifx_SENT_CH_SCR_Bits.PLEN */
+#define IFX_SENT_CH_SCR_PLEN_OFF (0u)
+
+/** \brief Length for Ifx_SENT_CH_SCR_Bits.TRIG */
+#define IFX_SENT_CH_SCR_TRIG_LEN (2u)
+
+/** \brief Mask for Ifx_SENT_CH_SCR_Bits.TRIG */
+#define IFX_SENT_CH_SCR_TRIG_MSK (0x3u)
+
+/** \brief Offset for Ifx_SENT_CH_SCR_Bits.TRIG */
+#define IFX_SENT_CH_SCR_TRIG_OFF (6u)
+
+/** \brief Length for Ifx_SENT_CH_SCR_Bits.TRQ */
+#define IFX_SENT_CH_SCR_TRQ_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_SCR_Bits.TRQ */
+#define IFX_SENT_CH_SCR_TRQ_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_SCR_Bits.TRQ */
+#define IFX_SENT_CH_SCR_TRQ_OFF (15u)
+
+/** \brief Length for Ifx_SENT_CH_SDS_Bits.CON */
+#define IFX_SENT_CH_SDS_CON_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CH_SDS_Bits.CON */
+#define IFX_SENT_CH_SDS_CON_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CH_SDS_Bits.CON */
+#define IFX_SENT_CH_SDS_CON_OFF (31u)
+
+/** \brief Length for Ifx_SENT_CH_SDS_Bits.MID */
+#define IFX_SENT_CH_SDS_MID_LEN (8u)
+
+/** \brief Mask for Ifx_SENT_CH_SDS_Bits.MID */
+#define IFX_SENT_CH_SDS_MID_MSK (0xffu)
+
+/** \brief Offset for Ifx_SENT_CH_SDS_Bits.MID */
+#define IFX_SENT_CH_SDS_MID_OFF (16u)
+
+/** \brief Length for Ifx_SENT_CH_SDS_Bits.SCRC */
+#define IFX_SENT_CH_SDS_SCRC_LEN (6u)
+
+/** \brief Mask for Ifx_SENT_CH_SDS_Bits.SCRC */
+#define IFX_SENT_CH_SDS_SCRC_MSK (0x3fu)
+
+/** \brief Offset for Ifx_SENT_CH_SDS_Bits.SCRC */
+#define IFX_SENT_CH_SDS_SCRC_OFF (24u)
+
+/** \brief Length for Ifx_SENT_CH_SDS_Bits.SD */
+#define IFX_SENT_CH_SDS_SD_LEN (16u)
+
+/** \brief Mask for Ifx_SENT_CH_SDS_Bits.SD */
+#define IFX_SENT_CH_SDS_SD_MSK (0xffffu)
+
+/** \brief Offset for Ifx_SENT_CH_SDS_Bits.SD */
+#define IFX_SENT_CH_SDS_SD_OFF (0u)
+
+/** \brief Length for Ifx_SENT_CH_VIEW_Bits.RDNP0 */
+#define IFX_SENT_CH_VIEW_RDNP0_LEN (3u)
+
+/** \brief Mask for Ifx_SENT_CH_VIEW_Bits.RDNP0 */
+#define IFX_SENT_CH_VIEW_RDNP0_MSK (0x7u)
+
+/** \brief Offset for Ifx_SENT_CH_VIEW_Bits.RDNP0 */
+#define IFX_SENT_CH_VIEW_RDNP0_OFF (0u)
+
+/** \brief Length for Ifx_SENT_CH_VIEW_Bits.RDNP1 */
+#define IFX_SENT_CH_VIEW_RDNP1_LEN (3u)
+
+/** \brief Mask for Ifx_SENT_CH_VIEW_Bits.RDNP1 */
+#define IFX_SENT_CH_VIEW_RDNP1_MSK (0x7u)
+
+/** \brief Offset for Ifx_SENT_CH_VIEW_Bits.RDNP1 */
+#define IFX_SENT_CH_VIEW_RDNP1_OFF (4u)
+
+/** \brief Length for Ifx_SENT_CH_VIEW_Bits.RDNP2 */
+#define IFX_SENT_CH_VIEW_RDNP2_LEN (3u)
+
+/** \brief Mask for Ifx_SENT_CH_VIEW_Bits.RDNP2 */
+#define IFX_SENT_CH_VIEW_RDNP2_MSK (0x7u)
+
+/** \brief Offset for Ifx_SENT_CH_VIEW_Bits.RDNP2 */
+#define IFX_SENT_CH_VIEW_RDNP2_OFF (8u)
+
+/** \brief Length for Ifx_SENT_CH_VIEW_Bits.RDNP3 */
+#define IFX_SENT_CH_VIEW_RDNP3_LEN (3u)
+
+/** \brief Mask for Ifx_SENT_CH_VIEW_Bits.RDNP3 */
+#define IFX_SENT_CH_VIEW_RDNP3_MSK (0x7u)
+
+/** \brief Offset for Ifx_SENT_CH_VIEW_Bits.RDNP3 */
+#define IFX_SENT_CH_VIEW_RDNP3_OFF (12u)
+
+/** \brief Length for Ifx_SENT_CH_VIEW_Bits.RDNP4 */
+#define IFX_SENT_CH_VIEW_RDNP4_LEN (3u)
+
+/** \brief Mask for Ifx_SENT_CH_VIEW_Bits.RDNP4 */
+#define IFX_SENT_CH_VIEW_RDNP4_MSK (0x7u)
+
+/** \brief Offset for Ifx_SENT_CH_VIEW_Bits.RDNP4 */
+#define IFX_SENT_CH_VIEW_RDNP4_OFF (16u)
+
+/** \brief Length for Ifx_SENT_CH_VIEW_Bits.RDNP5 */
+#define IFX_SENT_CH_VIEW_RDNP5_LEN (3u)
+
+/** \brief Mask for Ifx_SENT_CH_VIEW_Bits.RDNP5 */
+#define IFX_SENT_CH_VIEW_RDNP5_MSK (0x7u)
+
+/** \brief Offset for Ifx_SENT_CH_VIEW_Bits.RDNP5 */
+#define IFX_SENT_CH_VIEW_RDNP5_OFF (20u)
+
+/** \brief Length for Ifx_SENT_CH_VIEW_Bits.RDNP6 */
+#define IFX_SENT_CH_VIEW_RDNP6_LEN (3u)
+
+/** \brief Mask for Ifx_SENT_CH_VIEW_Bits.RDNP6 */
+#define IFX_SENT_CH_VIEW_RDNP6_MSK (0x7u)
+
+/** \brief Offset for Ifx_SENT_CH_VIEW_Bits.RDNP6 */
+#define IFX_SENT_CH_VIEW_RDNP6_OFF (24u)
+
+/** \brief Length for Ifx_SENT_CH_VIEW_Bits.RDNP7 */
+#define IFX_SENT_CH_VIEW_RDNP7_LEN (3u)
+
+/** \brief Mask for Ifx_SENT_CH_VIEW_Bits.RDNP7 */
+#define IFX_SENT_CH_VIEW_RDNP7_MSK (0x7u)
+
+/** \brief Offset for Ifx_SENT_CH_VIEW_Bits.RDNP7 */
+#define IFX_SENT_CH_VIEW_RDNP7_OFF (28u)
+
+/** \brief Length for Ifx_SENT_CH_WDT_Bits.WDLx */
+#define IFX_SENT_CH_WDT_WDLX_LEN (16u)
+
+/** \brief Mask for Ifx_SENT_CH_WDT_Bits.WDLx */
+#define IFX_SENT_CH_WDT_WDLX_MSK (0xffffu)
+
+/** \brief Offset for Ifx_SENT_CH_WDT_Bits.WDLx */
+#define IFX_SENT_CH_WDT_WDLX_OFF (0u)
+
+/** \brief Length for Ifx_SENT_CLC_Bits.DISR */
+#define IFX_SENT_CLC_DISR_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CLC_Bits.DISR */
+#define IFX_SENT_CLC_DISR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CLC_Bits.DISR */
+#define IFX_SENT_CLC_DISR_OFF (0u)
+
+/** \brief Length for Ifx_SENT_CLC_Bits.DISS */
+#define IFX_SENT_CLC_DISS_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CLC_Bits.DISS */
+#define IFX_SENT_CLC_DISS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CLC_Bits.DISS */
+#define IFX_SENT_CLC_DISS_OFF (1u)
+
+/** \brief Length for Ifx_SENT_CLC_Bits.EDIS */
+#define IFX_SENT_CLC_EDIS_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_CLC_Bits.EDIS */
+#define IFX_SENT_CLC_EDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_CLC_Bits.EDIS */
+#define IFX_SENT_CLC_EDIS_OFF (3u)
+
+/** \brief Length for Ifx_SENT_CLC_Bits.RMC */
+#define IFX_SENT_CLC_RMC_LEN (8u)
+
+/** \brief Mask for Ifx_SENT_CLC_Bits.RMC */
+#define IFX_SENT_CLC_RMC_MSK (0xffu)
+
+/** \brief Offset for Ifx_SENT_CLC_Bits.RMC */
+#define IFX_SENT_CLC_RMC_OFF (8u)
+
+/** \brief Length for Ifx_SENT_FDR_Bits.DM */
+#define IFX_SENT_FDR_DM_LEN (2u)
+
+/** \brief Mask for Ifx_SENT_FDR_Bits.DM */
+#define IFX_SENT_FDR_DM_MSK (0x3u)
+
+/** \brief Offset for Ifx_SENT_FDR_Bits.DM */
+#define IFX_SENT_FDR_DM_OFF (14u)
+
+/** \brief Length for Ifx_SENT_FDR_Bits.RESULT */
+#define IFX_SENT_FDR_RESULT_LEN (10u)
+
+/** \brief Mask for Ifx_SENT_FDR_Bits.RESULT */
+#define IFX_SENT_FDR_RESULT_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_SENT_FDR_Bits.RESULT */
+#define IFX_SENT_FDR_RESULT_OFF (16u)
+
+/** \brief Length for Ifx_SENT_FDR_Bits.STEP */
+#define IFX_SENT_FDR_STEP_LEN (10u)
+
+/** \brief Mask for Ifx_SENT_FDR_Bits.STEP */
+#define IFX_SENT_FDR_STEP_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_SENT_FDR_Bits.STEP */
+#define IFX_SENT_FDR_STEP_OFF (0u)
+
+/** \brief Length for Ifx_SENT_ID_Bits.MODNUMBER */
+#define IFX_SENT_ID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_SENT_ID_Bits.MODNUMBER */
+#define IFX_SENT_ID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_SENT_ID_Bits.MODNUMBER */
+#define IFX_SENT_ID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_SENT_ID_Bits.MODREV */
+#define IFX_SENT_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_SENT_ID_Bits.MODREV */
+#define IFX_SENT_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_SENT_ID_Bits.MODREV */
+#define IFX_SENT_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_SENT_ID_Bits.MODTYPE */
+#define IFX_SENT_ID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_SENT_ID_Bits.MODTYPE */
+#define IFX_SENT_ID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_SENT_ID_Bits.MODTYPE */
+#define IFX_SENT_ID_MODTYPE_OFF (8u)
+
+/** \brief Length for Ifx_SENT_INTOV_Bits.IPC0 */
+#define IFX_SENT_INTOV_IPC0_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_INTOV_Bits.IPC0 */
+#define IFX_SENT_INTOV_IPC0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_INTOV_Bits.IPC0 */
+#define IFX_SENT_INTOV_IPC0_OFF (0u)
+
+/** \brief Length for Ifx_SENT_INTOV_Bits.IPC1 */
+#define IFX_SENT_INTOV_IPC1_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_INTOV_Bits.IPC1 */
+#define IFX_SENT_INTOV_IPC1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_INTOV_Bits.IPC1 */
+#define IFX_SENT_INTOV_IPC1_OFF (1u)
+
+/** \brief Length for Ifx_SENT_INTOV_Bits.IPC2 */
+#define IFX_SENT_INTOV_IPC2_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_INTOV_Bits.IPC2 */
+#define IFX_SENT_INTOV_IPC2_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_INTOV_Bits.IPC2 */
+#define IFX_SENT_INTOV_IPC2_OFF (2u)
+
+/** \brief Length for Ifx_SENT_INTOV_Bits.IPC3 */
+#define IFX_SENT_INTOV_IPC3_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_INTOV_Bits.IPC3 */
+#define IFX_SENT_INTOV_IPC3_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_INTOV_Bits.IPC3 */
+#define IFX_SENT_INTOV_IPC3_OFF (3u)
+
+/** \brief Length for Ifx_SENT_INTOV_Bits.IPC4 */
+#define IFX_SENT_INTOV_IPC4_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_INTOV_Bits.IPC4 */
+#define IFX_SENT_INTOV_IPC4_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_INTOV_Bits.IPC4 */
+#define IFX_SENT_INTOV_IPC4_OFF (4u)
+
+/** \brief Length for Ifx_SENT_INTOV_Bits.IPC5 */
+#define IFX_SENT_INTOV_IPC5_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_INTOV_Bits.IPC5 */
+#define IFX_SENT_INTOV_IPC5_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_INTOV_Bits.IPC5 */
+#define IFX_SENT_INTOV_IPC5_OFF (5u)
+
+/** \brief Length for Ifx_SENT_KRST0_Bits.RST */
+#define IFX_SENT_KRST0_RST_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_KRST0_Bits.RST */
+#define IFX_SENT_KRST0_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_KRST0_Bits.RST */
+#define IFX_SENT_KRST0_RST_OFF (0u)
+
+/** \brief Length for Ifx_SENT_KRST0_Bits.RSTSTAT */
+#define IFX_SENT_KRST0_RSTSTAT_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_KRST0_Bits.RSTSTAT */
+#define IFX_SENT_KRST0_RSTSTAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_KRST0_Bits.RSTSTAT */
+#define IFX_SENT_KRST0_RSTSTAT_OFF (1u)
+
+/** \brief Length for Ifx_SENT_KRST1_Bits.RST */
+#define IFX_SENT_KRST1_RST_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_KRST1_Bits.RST */
+#define IFX_SENT_KRST1_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_KRST1_Bits.RST */
+#define IFX_SENT_KRST1_RST_OFF (0u)
+
+/** \brief Length for Ifx_SENT_KRSTCLR_Bits.CLR */
+#define IFX_SENT_KRSTCLR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_KRSTCLR_Bits.CLR */
+#define IFX_SENT_KRSTCLR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_KRSTCLR_Bits.CLR */
+#define IFX_SENT_KRSTCLR_CLR_OFF (0u)
+
+/** \brief Length for Ifx_SENT_OCS_Bits.SUS */
+#define IFX_SENT_OCS_SUS_LEN (4u)
+
+/** \brief Mask for Ifx_SENT_OCS_Bits.SUS */
+#define IFX_SENT_OCS_SUS_MSK (0xfu)
+
+/** \brief Offset for Ifx_SENT_OCS_Bits.SUS */
+#define IFX_SENT_OCS_SUS_OFF (24u)
+
+/** \brief Length for Ifx_SENT_OCS_Bits.SUS_P */
+#define IFX_SENT_OCS_SUS_P_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_OCS_Bits.SUS_P */
+#define IFX_SENT_OCS_SUS_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_OCS_Bits.SUS_P */
+#define IFX_SENT_OCS_SUS_P_OFF (28u)
+
+/** \brief Length for Ifx_SENT_OCS_Bits.SUSSTA */
+#define IFX_SENT_OCS_SUSSTA_LEN (1u)
+
+/** \brief Mask for Ifx_SENT_OCS_Bits.SUSSTA */
+#define IFX_SENT_OCS_SUSSTA_MSK (0x1u)
+
+/** \brief Offset for Ifx_SENT_OCS_Bits.SUSSTA */
+#define IFX_SENT_OCS_SUSSTA_OFF (29u)
+
+/** \brief Length for Ifx_SENT_RDR_Bits.RD0 */
+#define IFX_SENT_RDR_RD0_LEN (4u)
+
+/** \brief Mask for Ifx_SENT_RDR_Bits.RD0 */
+#define IFX_SENT_RDR_RD0_MSK (0xfu)
+
+/** \brief Offset for Ifx_SENT_RDR_Bits.RD0 */
+#define IFX_SENT_RDR_RD0_OFF (0u)
+
+/** \brief Length for Ifx_SENT_RDR_Bits.RD1 */
+#define IFX_SENT_RDR_RD1_LEN (4u)
+
+/** \brief Mask for Ifx_SENT_RDR_Bits.RD1 */
+#define IFX_SENT_RDR_RD1_MSK (0xfu)
+
+/** \brief Offset for Ifx_SENT_RDR_Bits.RD1 */
+#define IFX_SENT_RDR_RD1_OFF (4u)
+
+/** \brief Length for Ifx_SENT_RDR_Bits.RD2 */
+#define IFX_SENT_RDR_RD2_LEN (4u)
+
+/** \brief Mask for Ifx_SENT_RDR_Bits.RD2 */
+#define IFX_SENT_RDR_RD2_MSK (0xfu)
+
+/** \brief Offset for Ifx_SENT_RDR_Bits.RD2 */
+#define IFX_SENT_RDR_RD2_OFF (8u)
+
+/** \brief Length for Ifx_SENT_RDR_Bits.RD3 */
+#define IFX_SENT_RDR_RD3_LEN (4u)
+
+/** \brief Mask for Ifx_SENT_RDR_Bits.RD3 */
+#define IFX_SENT_RDR_RD3_MSK (0xfu)
+
+/** \brief Offset for Ifx_SENT_RDR_Bits.RD3 */
+#define IFX_SENT_RDR_RD3_OFF (12u)
+
+/** \brief Length for Ifx_SENT_RDR_Bits.RD4 */
+#define IFX_SENT_RDR_RD4_LEN (4u)
+
+/** \brief Mask for Ifx_SENT_RDR_Bits.RD4 */
+#define IFX_SENT_RDR_RD4_MSK (0xfu)
+
+/** \brief Offset for Ifx_SENT_RDR_Bits.RD4 */
+#define IFX_SENT_RDR_RD4_OFF (16u)
+
+/** \brief Length for Ifx_SENT_RDR_Bits.RD5 */
+#define IFX_SENT_RDR_RD5_LEN (4u)
+
+/** \brief Mask for Ifx_SENT_RDR_Bits.RD5 */
+#define IFX_SENT_RDR_RD5_MSK (0xfu)
+
+/** \brief Offset for Ifx_SENT_RDR_Bits.RD5 */
+#define IFX_SENT_RDR_RD5_OFF (20u)
+
+/** \brief Length for Ifx_SENT_RDR_Bits.RD6 */
+#define IFX_SENT_RDR_RD6_LEN (4u)
+
+/** \brief Mask for Ifx_SENT_RDR_Bits.RD6 */
+#define IFX_SENT_RDR_RD6_MSK (0xfu)
+
+/** \brief Offset for Ifx_SENT_RDR_Bits.RD6 */
+#define IFX_SENT_RDR_RD6_OFF (24u)
+
+/** \brief Length for Ifx_SENT_RDR_Bits.RD7 */
+#define IFX_SENT_RDR_RD7_LEN (4u)
+
+/** \brief Mask for Ifx_SENT_RDR_Bits.RD7 */
+#define IFX_SENT_RDR_RD7_MSK (0xfu)
+
+/** \brief Offset for Ifx_SENT_RDR_Bits.RD7 */
+#define IFX_SENT_RDR_RD7_OFF (28u)
+
+/** \brief Length for Ifx_SENT_RTS_Bits.LTS */
+#define IFX_SENT_RTS_LTS_LEN (32u)
+
+/** \brief Mask for Ifx_SENT_RTS_Bits.LTS */
+#define IFX_SENT_RTS_LTS_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_SENT_RTS_Bits.LTS */
+#define IFX_SENT_RTS_LTS_OFF (0u)
+
+/** \brief Length for Ifx_SENT_TPD_Bits.TDIV */
+#define IFX_SENT_TPD_TDIV_LEN (20u)
+
+/** \brief Mask for Ifx_SENT_TPD_Bits.TDIV */
+#define IFX_SENT_TPD_TDIV_MSK (0xfffffu)
+
+/** \brief Offset for Ifx_SENT_TPD_Bits.TDIV */
+#define IFX_SENT_TPD_TDIV_OFF (0u)
+
+/** \brief Length for Ifx_SENT_TSR_Bits.CTS */
+#define IFX_SENT_TSR_CTS_LEN (32u)
+
+/** \brief Mask for Ifx_SENT_TSR_Bits.CTS */
+#define IFX_SENT_TSR_CTS_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_SENT_TSR_Bits.CTS */
+#define IFX_SENT_TSR_CTS_OFF (0u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXSENT_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSent_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSent_reg.h
new file mode 100644
index 0000000..5a26cbd
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSent_reg.h
@@ -0,0 +1,795 @@
+/**
+ * \file IfxSent_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Sent_Cfg Sent address
+ * \ingroup IfxLld_Sent
+ *
+ * \defgroup IfxLld_Sent_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Sent_Cfg
+ *
+ * \defgroup IfxLld_Sent_Cfg_Sent 2-SENT
+ * \ingroup IfxLld_Sent_Cfg
+ *
+ */
+#ifndef IFXSENT_REG_H
+#define IFXSENT_REG_H 1
+/******************************************************************************/
+#include "IfxSent_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Sent_Cfg_BaseAddress
+ * \{ */
+
+/** \brief SENT object */
+#define MODULE_SENT /*lint --e(923)*/ (*(Ifx_SENT*)0xF0003000u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Sent_Cfg_Sent
+ * \{ */
+
+/** \brief FC, Access Enable Register 0 */
+#define SENT_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_SENT_ACCEN0*)0xF00030FCu)
+
+/** \brief F8, Access Enable Register 1 */
+#define SENT_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_SENT_ACCEN1*)0xF00030F8u)
+
+/** \brief 104, Channel Fractional Divider Register */
+#define SENT_CH0_CFDR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_CFDR*)0xF0003104u)
+
+/** Alias (User Manual Name) for SENT_CH0_CFDR.
+* To use register names with standard convension, please use SENT_CH0_CFDR.
+*/
+#define SENT_CFDR0 (SENT_CH0_CFDR)
+
+/** \brief 100, Channel Pre Divider Register */
+#define SENT_CH0_CPDR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_CPDR*)0xF0003100u)
+
+/** Alias (User Manual Name) for SENT_CH0_CPDR.
+* To use register names with standard convension, please use SENT_CH0_CPDR.
+*/
+#define SENT_CPDR0 (SENT_CH0_CPDR)
+
+/** \brief 130, Interrupt Node Pointer Register */
+#define SENT_CH0_INP /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_INP*)0xF0003130u)
+
+/** Alias (User Manual Name) for SENT_CH0_INP.
+* To use register names with standard convension, please use SENT_CH0_INP.
+*/
+#define SENT_INP0 (SENT_CH0_INP)
+
+/** \brief 128, Interrupt Clear Register */
+#define SENT_CH0_INTCLR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_INTCLR*)0xF0003128u)
+
+/** Alias (User Manual Name) for SENT_CH0_INTCLR.
+* To use register names with standard convension, please use SENT_CH0_INTCLR.
+*/
+#define SENT_INTCLR0 (SENT_CH0_INTCLR)
+
+/** \brief 12C, Interrupt Enable Register */
+#define SENT_CH0_INTEN /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_INTEN*)0xF000312Cu)
+
+/** Alias (User Manual Name) for SENT_CH0_INTEN.
+* To use register names with standard convension, please use SENT_CH0_INTEN.
+*/
+#define SENT_INTEN0 (SENT_CH0_INTEN)
+
+/** \brief 124, Interrupt Set Register */
+#define SENT_CH0_INTSET /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_INTSET*)0xF0003124u)
+
+/** Alias (User Manual Name) for SENT_CH0_INTSET.
+* To use register names with standard convension, please use SENT_CH0_INTSET.
+*/
+#define SENT_INTSET0 (SENT_CH0_INTSET)
+
+/** \brief 120, Interrupt Status Register */
+#define SENT_CH0_INTSTAT /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_INTSTAT*)0xF0003120u)
+
+/** Alias (User Manual Name) for SENT_CH0_INTSTAT.
+* To use register names with standard convension, please use SENT_CH0_INTSTAT.
+*/
+#define SENT_INTSTAT0 (SENT_CH0_INTSTAT)
+
+/** \brief 114, Input and Output Control Register */
+#define SENT_CH0_IOCR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_IOCR*)0xF0003114u)
+
+/** Alias (User Manual Name) for SENT_CH0_IOCR.
+* To use register names with standard convension, please use SENT_CH0_IOCR.
+*/
+#define SENT_IOCR0 (SENT_CH0_IOCR)
+
+/** \brief 108, Receiver Control Register */
+#define SENT_CH0_RCR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_RCR*)0xF0003108u)
+
+/** Alias (User Manual Name) for SENT_CH0_RCR.
+* To use register names with standard convension, please use SENT_CH0_RCR.
+*/
+#define SENT_RCR0 (SENT_CH0_RCR)
+
+/** \brief 10C, Receive Status Register */
+#define SENT_CH0_RSR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_RSR*)0xF000310Cu)
+
+/** Alias (User Manual Name) for SENT_CH0_RSR.
+* To use register names with standard convension, please use SENT_CH0_RSR.
+*/
+#define SENT_RSR0 (SENT_CH0_RSR)
+
+/** \brief 118, SPC Control Register */
+#define SENT_CH0_SCR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_SCR*)0xF0003118u)
+
+/** Alias (User Manual Name) for SENT_CH0_SCR.
+* To use register names with standard convension, please use SENT_CH0_SCR.
+*/
+#define SENT_SCR0 (SENT_CH0_SCR)
+
+/** \brief 110, Serial Data and Status Register */
+#define SENT_CH0_SDS /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_SDS*)0xF0003110u)
+
+/** Alias (User Manual Name) for SENT_CH0_SDS.
+* To use register names with standard convension, please use SENT_CH0_SDS.
+*/
+#define SENT_SDS0 (SENT_CH0_SDS)
+
+/** \brief 11C, Receive Data View Register */
+#define SENT_CH0_VIEW /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_VIEW*)0xF000311Cu)
+
+/** Alias (User Manual Name) for SENT_CH0_VIEW.
+* To use register names with standard convension, please use SENT_CH0_VIEW.
+*/
+#define SENT_VIEW0 (SENT_CH0_VIEW)
+
+/** \brief 134, Watch Dog Timer Register */
+#define SENT_CH0_WDT /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_WDT*)0xF0003134u)
+
+/** Alias (User Manual Name) for SENT_CH0_WDT.
+* To use register names with standard convension, please use SENT_CH0_WDT.
+*/
+#define SENT_WDT0 (SENT_CH0_WDT)
+
+/** \brief 144, Channel Fractional Divider Register */
+#define SENT_CH1_CFDR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_CFDR*)0xF0003144u)
+
+/** Alias (User Manual Name) for SENT_CH1_CFDR.
+* To use register names with standard convension, please use SENT_CH1_CFDR.
+*/
+#define SENT_CFDR1 (SENT_CH1_CFDR)
+
+/** \brief 140, Channel Pre Divider Register */
+#define SENT_CH1_CPDR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_CPDR*)0xF0003140u)
+
+/** Alias (User Manual Name) for SENT_CH1_CPDR.
+* To use register names with standard convension, please use SENT_CH1_CPDR.
+*/
+#define SENT_CPDR1 (SENT_CH1_CPDR)
+
+/** \brief 170, Interrupt Node Pointer Register */
+#define SENT_CH1_INP /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_INP*)0xF0003170u)
+
+/** Alias (User Manual Name) for SENT_CH1_INP.
+* To use register names with standard convension, please use SENT_CH1_INP.
+*/
+#define SENT_INP1 (SENT_CH1_INP)
+
+/** \brief 168, Interrupt Clear Register */
+#define SENT_CH1_INTCLR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_INTCLR*)0xF0003168u)
+
+/** Alias (User Manual Name) for SENT_CH1_INTCLR.
+* To use register names with standard convension, please use SENT_CH1_INTCLR.
+*/
+#define SENT_INTCLR1 (SENT_CH1_INTCLR)
+
+/** \brief 16C, Interrupt Enable Register */
+#define SENT_CH1_INTEN /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_INTEN*)0xF000316Cu)
+
+/** Alias (User Manual Name) for SENT_CH1_INTEN.
+* To use register names with standard convension, please use SENT_CH1_INTEN.
+*/
+#define SENT_INTEN1 (SENT_CH1_INTEN)
+
+/** \brief 164, Interrupt Set Register */
+#define SENT_CH1_INTSET /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_INTSET*)0xF0003164u)
+
+/** Alias (User Manual Name) for SENT_CH1_INTSET.
+* To use register names with standard convension, please use SENT_CH1_INTSET.
+*/
+#define SENT_INTSET1 (SENT_CH1_INTSET)
+
+/** \brief 160, Interrupt Status Register */
+#define SENT_CH1_INTSTAT /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_INTSTAT*)0xF0003160u)
+
+/** Alias (User Manual Name) for SENT_CH1_INTSTAT.
+* To use register names with standard convension, please use SENT_CH1_INTSTAT.
+*/
+#define SENT_INTSTAT1 (SENT_CH1_INTSTAT)
+
+/** \brief 154, Input and Output Control Register */
+#define SENT_CH1_IOCR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_IOCR*)0xF0003154u)
+
+/** Alias (User Manual Name) for SENT_CH1_IOCR.
+* To use register names with standard convension, please use SENT_CH1_IOCR.
+*/
+#define SENT_IOCR1 (SENT_CH1_IOCR)
+
+/** \brief 148, Receiver Control Register */
+#define SENT_CH1_RCR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_RCR*)0xF0003148u)
+
+/** Alias (User Manual Name) for SENT_CH1_RCR.
+* To use register names with standard convension, please use SENT_CH1_RCR.
+*/
+#define SENT_RCR1 (SENT_CH1_RCR)
+
+/** \brief 14C, Receive Status Register */
+#define SENT_CH1_RSR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_RSR*)0xF000314Cu)
+
+/** Alias (User Manual Name) for SENT_CH1_RSR.
+* To use register names with standard convension, please use SENT_CH1_RSR.
+*/
+#define SENT_RSR1 (SENT_CH1_RSR)
+
+/** \brief 158, SPC Control Register */
+#define SENT_CH1_SCR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_SCR*)0xF0003158u)
+
+/** Alias (User Manual Name) for SENT_CH1_SCR.
+* To use register names with standard convension, please use SENT_CH1_SCR.
+*/
+#define SENT_SCR1 (SENT_CH1_SCR)
+
+/** \brief 150, Serial Data and Status Register */
+#define SENT_CH1_SDS /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_SDS*)0xF0003150u)
+
+/** Alias (User Manual Name) for SENT_CH1_SDS.
+* To use register names with standard convension, please use SENT_CH1_SDS.
+*/
+#define SENT_SDS1 (SENT_CH1_SDS)
+
+/** \brief 15C, Receive Data View Register */
+#define SENT_CH1_VIEW /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_VIEW*)0xF000315Cu)
+
+/** Alias (User Manual Name) for SENT_CH1_VIEW.
+* To use register names with standard convension, please use SENT_CH1_VIEW.
+*/
+#define SENT_VIEW1 (SENT_CH1_VIEW)
+
+/** \brief 174, Watch Dog Timer Register */
+#define SENT_CH1_WDT /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_WDT*)0xF0003174u)
+
+/** Alias (User Manual Name) for SENT_CH1_WDT.
+* To use register names with standard convension, please use SENT_CH1_WDT.
+*/
+#define SENT_WDT1 (SENT_CH1_WDT)
+
+/** \brief 184, Channel Fractional Divider Register */
+#define SENT_CH2_CFDR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_CFDR*)0xF0003184u)
+
+/** Alias (User Manual Name) for SENT_CH2_CFDR.
+* To use register names with standard convension, please use SENT_CH2_CFDR.
+*/
+#define SENT_CFDR2 (SENT_CH2_CFDR)
+
+/** \brief 180, Channel Pre Divider Register */
+#define SENT_CH2_CPDR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_CPDR*)0xF0003180u)
+
+/** Alias (User Manual Name) for SENT_CH2_CPDR.
+* To use register names with standard convension, please use SENT_CH2_CPDR.
+*/
+#define SENT_CPDR2 (SENT_CH2_CPDR)
+
+/** \brief 1B0, Interrupt Node Pointer Register */
+#define SENT_CH2_INP /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_INP*)0xF00031B0u)
+
+/** Alias (User Manual Name) for SENT_CH2_INP.
+* To use register names with standard convension, please use SENT_CH2_INP.
+*/
+#define SENT_INP2 (SENT_CH2_INP)
+
+/** \brief 1A8, Interrupt Clear Register */
+#define SENT_CH2_INTCLR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_INTCLR*)0xF00031A8u)
+
+/** Alias (User Manual Name) for SENT_CH2_INTCLR.
+* To use register names with standard convension, please use SENT_CH2_INTCLR.
+*/
+#define SENT_INTCLR2 (SENT_CH2_INTCLR)
+
+/** \brief 1AC, Interrupt Enable Register */
+#define SENT_CH2_INTEN /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_INTEN*)0xF00031ACu)
+
+/** Alias (User Manual Name) for SENT_CH2_INTEN.
+* To use register names with standard convension, please use SENT_CH2_INTEN.
+*/
+#define SENT_INTEN2 (SENT_CH2_INTEN)
+
+/** \brief 1A4, Interrupt Set Register */
+#define SENT_CH2_INTSET /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_INTSET*)0xF00031A4u)
+
+/** Alias (User Manual Name) for SENT_CH2_INTSET.
+* To use register names with standard convension, please use SENT_CH2_INTSET.
+*/
+#define SENT_INTSET2 (SENT_CH2_INTSET)
+
+/** \brief 1A0, Interrupt Status Register */
+#define SENT_CH2_INTSTAT /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_INTSTAT*)0xF00031A0u)
+
+/** Alias (User Manual Name) for SENT_CH2_INTSTAT.
+* To use register names with standard convension, please use SENT_CH2_INTSTAT.
+*/
+#define SENT_INTSTAT2 (SENT_CH2_INTSTAT)
+
+/** \brief 194, Input and Output Control Register */
+#define SENT_CH2_IOCR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_IOCR*)0xF0003194u)
+
+/** Alias (User Manual Name) for SENT_CH2_IOCR.
+* To use register names with standard convension, please use SENT_CH2_IOCR.
+*/
+#define SENT_IOCR2 (SENT_CH2_IOCR)
+
+/** \brief 188, Receiver Control Register */
+#define SENT_CH2_RCR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_RCR*)0xF0003188u)
+
+/** Alias (User Manual Name) for SENT_CH2_RCR.
+* To use register names with standard convension, please use SENT_CH2_RCR.
+*/
+#define SENT_RCR2 (SENT_CH2_RCR)
+
+/** \brief 18C, Receive Status Register */
+#define SENT_CH2_RSR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_RSR*)0xF000318Cu)
+
+/** Alias (User Manual Name) for SENT_CH2_RSR.
+* To use register names with standard convension, please use SENT_CH2_RSR.
+*/
+#define SENT_RSR2 (SENT_CH2_RSR)
+
+/** \brief 198, SPC Control Register */
+#define SENT_CH2_SCR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_SCR*)0xF0003198u)
+
+/** Alias (User Manual Name) for SENT_CH2_SCR.
+* To use register names with standard convension, please use SENT_CH2_SCR.
+*/
+#define SENT_SCR2 (SENT_CH2_SCR)
+
+/** \brief 190, Serial Data and Status Register */
+#define SENT_CH2_SDS /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_SDS*)0xF0003190u)
+
+/** Alias (User Manual Name) for SENT_CH2_SDS.
+* To use register names with standard convension, please use SENT_CH2_SDS.
+*/
+#define SENT_SDS2 (SENT_CH2_SDS)
+
+/** \brief 19C, Receive Data View Register */
+#define SENT_CH2_VIEW /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_VIEW*)0xF000319Cu)
+
+/** Alias (User Manual Name) for SENT_CH2_VIEW.
+* To use register names with standard convension, please use SENT_CH2_VIEW.
+*/
+#define SENT_VIEW2 (SENT_CH2_VIEW)
+
+/** \brief 1B4, Watch Dog Timer Register */
+#define SENT_CH2_WDT /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_WDT*)0xF00031B4u)
+
+/** Alias (User Manual Name) for SENT_CH2_WDT.
+* To use register names with standard convension, please use SENT_CH2_WDT.
+*/
+#define SENT_WDT2 (SENT_CH2_WDT)
+
+/** \brief 1C4, Channel Fractional Divider Register */
+#define SENT_CH3_CFDR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_CFDR*)0xF00031C4u)
+
+/** Alias (User Manual Name) for SENT_CH3_CFDR.
+* To use register names with standard convension, please use SENT_CH3_CFDR.
+*/
+#define SENT_CFDR3 (SENT_CH3_CFDR)
+
+/** \brief 1C0, Channel Pre Divider Register */
+#define SENT_CH3_CPDR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_CPDR*)0xF00031C0u)
+
+/** Alias (User Manual Name) for SENT_CH3_CPDR.
+* To use register names with standard convension, please use SENT_CH3_CPDR.
+*/
+#define SENT_CPDR3 (SENT_CH3_CPDR)
+
+/** \brief 1F0, Interrupt Node Pointer Register */
+#define SENT_CH3_INP /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_INP*)0xF00031F0u)
+
+/** Alias (User Manual Name) for SENT_CH3_INP.
+* To use register names with standard convension, please use SENT_CH3_INP.
+*/
+#define SENT_INP3 (SENT_CH3_INP)
+
+/** \brief 1E8, Interrupt Clear Register */
+#define SENT_CH3_INTCLR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_INTCLR*)0xF00031E8u)
+
+/** Alias (User Manual Name) for SENT_CH3_INTCLR.
+* To use register names with standard convension, please use SENT_CH3_INTCLR.
+*/
+#define SENT_INTCLR3 (SENT_CH3_INTCLR)
+
+/** \brief 1EC, Interrupt Enable Register */
+#define SENT_CH3_INTEN /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_INTEN*)0xF00031ECu)
+
+/** Alias (User Manual Name) for SENT_CH3_INTEN.
+* To use register names with standard convension, please use SENT_CH3_INTEN.
+*/
+#define SENT_INTEN3 (SENT_CH3_INTEN)
+
+/** \brief 1E4, Interrupt Set Register */
+#define SENT_CH3_INTSET /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_INTSET*)0xF00031E4u)
+
+/** Alias (User Manual Name) for SENT_CH3_INTSET.
+* To use register names with standard convension, please use SENT_CH3_INTSET.
+*/
+#define SENT_INTSET3 (SENT_CH3_INTSET)
+
+/** \brief 1E0, Interrupt Status Register */
+#define SENT_CH3_INTSTAT /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_INTSTAT*)0xF00031E0u)
+
+/** Alias (User Manual Name) for SENT_CH3_INTSTAT.
+* To use register names with standard convension, please use SENT_CH3_INTSTAT.
+*/
+#define SENT_INTSTAT3 (SENT_CH3_INTSTAT)
+
+/** \brief 1D4, Input and Output Control Register */
+#define SENT_CH3_IOCR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_IOCR*)0xF00031D4u)
+
+/** Alias (User Manual Name) for SENT_CH3_IOCR.
+* To use register names with standard convension, please use SENT_CH3_IOCR.
+*/
+#define SENT_IOCR3 (SENT_CH3_IOCR)
+
+/** \brief 1C8, Receiver Control Register */
+#define SENT_CH3_RCR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_RCR*)0xF00031C8u)
+
+/** Alias (User Manual Name) for SENT_CH3_RCR.
+* To use register names with standard convension, please use SENT_CH3_RCR.
+*/
+#define SENT_RCR3 (SENT_CH3_RCR)
+
+/** \brief 1CC, Receive Status Register */
+#define SENT_CH3_RSR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_RSR*)0xF00031CCu)
+
+/** Alias (User Manual Name) for SENT_CH3_RSR.
+* To use register names with standard convension, please use SENT_CH3_RSR.
+*/
+#define SENT_RSR3 (SENT_CH3_RSR)
+
+/** \brief 1D8, SPC Control Register */
+#define SENT_CH3_SCR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_SCR*)0xF00031D8u)
+
+/** Alias (User Manual Name) for SENT_CH3_SCR.
+* To use register names with standard convension, please use SENT_CH3_SCR.
+*/
+#define SENT_SCR3 (SENT_CH3_SCR)
+
+/** \brief 1D0, Serial Data and Status Register */
+#define SENT_CH3_SDS /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_SDS*)0xF00031D0u)
+
+/** Alias (User Manual Name) for SENT_CH3_SDS.
+* To use register names with standard convension, please use SENT_CH3_SDS.
+*/
+#define SENT_SDS3 (SENT_CH3_SDS)
+
+/** \brief 1DC, Receive Data View Register */
+#define SENT_CH3_VIEW /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_VIEW*)0xF00031DCu)
+
+/** Alias (User Manual Name) for SENT_CH3_VIEW.
+* To use register names with standard convension, please use SENT_CH3_VIEW.
+*/
+#define SENT_VIEW3 (SENT_CH3_VIEW)
+
+/** \brief 1F4, Watch Dog Timer Register */
+#define SENT_CH3_WDT /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_WDT*)0xF00031F4u)
+
+/** Alias (User Manual Name) for SENT_CH3_WDT.
+* To use register names with standard convension, please use SENT_CH3_WDT.
+*/
+#define SENT_WDT3 (SENT_CH3_WDT)
+
+/** \brief 204, Channel Fractional Divider Register */
+#define SENT_CH4_CFDR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_CFDR*)0xF0003204u)
+
+/** Alias (User Manual Name) for SENT_CH4_CFDR.
+* To use register names with standard convension, please use SENT_CH4_CFDR.
+*/
+#define SENT_CFDR4 (SENT_CH4_CFDR)
+
+/** \brief 200, Channel Pre Divider Register */
+#define SENT_CH4_CPDR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_CPDR*)0xF0003200u)
+
+/** Alias (User Manual Name) for SENT_CH4_CPDR.
+* To use register names with standard convension, please use SENT_CH4_CPDR.
+*/
+#define SENT_CPDR4 (SENT_CH4_CPDR)
+
+/** \brief 230, Interrupt Node Pointer Register */
+#define SENT_CH4_INP /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_INP*)0xF0003230u)
+
+/** Alias (User Manual Name) for SENT_CH4_INP.
+* To use register names with standard convension, please use SENT_CH4_INP.
+*/
+#define SENT_INP4 (SENT_CH4_INP)
+
+/** \brief 228, Interrupt Clear Register */
+#define SENT_CH4_INTCLR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_INTCLR*)0xF0003228u)
+
+/** Alias (User Manual Name) for SENT_CH4_INTCLR.
+* To use register names with standard convension, please use SENT_CH4_INTCLR.
+*/
+#define SENT_INTCLR4 (SENT_CH4_INTCLR)
+
+/** \brief 22C, Interrupt Enable Register */
+#define SENT_CH4_INTEN /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_INTEN*)0xF000322Cu)
+
+/** Alias (User Manual Name) for SENT_CH4_INTEN.
+* To use register names with standard convension, please use SENT_CH4_INTEN.
+*/
+#define SENT_INTEN4 (SENT_CH4_INTEN)
+
+/** \brief 224, Interrupt Set Register */
+#define SENT_CH4_INTSET /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_INTSET*)0xF0003224u)
+
+/** Alias (User Manual Name) for SENT_CH4_INTSET.
+* To use register names with standard convension, please use SENT_CH4_INTSET.
+*/
+#define SENT_INTSET4 (SENT_CH4_INTSET)
+
+/** \brief 220, Interrupt Status Register */
+#define SENT_CH4_INTSTAT /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_INTSTAT*)0xF0003220u)
+
+/** Alias (User Manual Name) for SENT_CH4_INTSTAT.
+* To use register names with standard convension, please use SENT_CH4_INTSTAT.
+*/
+#define SENT_INTSTAT4 (SENT_CH4_INTSTAT)
+
+/** \brief 214, Input and Output Control Register */
+#define SENT_CH4_IOCR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_IOCR*)0xF0003214u)
+
+/** Alias (User Manual Name) for SENT_CH4_IOCR.
+* To use register names with standard convension, please use SENT_CH4_IOCR.
+*/
+#define SENT_IOCR4 (SENT_CH4_IOCR)
+
+/** \brief 208, Receiver Control Register */
+#define SENT_CH4_RCR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_RCR*)0xF0003208u)
+
+/** Alias (User Manual Name) for SENT_CH4_RCR.
+* To use register names with standard convension, please use SENT_CH4_RCR.
+*/
+#define SENT_RCR4 (SENT_CH4_RCR)
+
+/** \brief 20C, Receive Status Register */
+#define SENT_CH4_RSR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_RSR*)0xF000320Cu)
+
+/** Alias (User Manual Name) for SENT_CH4_RSR.
+* To use register names with standard convension, please use SENT_CH4_RSR.
+*/
+#define SENT_RSR4 (SENT_CH4_RSR)
+
+/** \brief 218, SPC Control Register */
+#define SENT_CH4_SCR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_SCR*)0xF0003218u)
+
+/** Alias (User Manual Name) for SENT_CH4_SCR.
+* To use register names with standard convension, please use SENT_CH4_SCR.
+*/
+#define SENT_SCR4 (SENT_CH4_SCR)
+
+/** \brief 210, Serial Data and Status Register */
+#define SENT_CH4_SDS /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_SDS*)0xF0003210u)
+
+/** Alias (User Manual Name) for SENT_CH4_SDS.
+* To use register names with standard convension, please use SENT_CH4_SDS.
+*/
+#define SENT_SDS4 (SENT_CH4_SDS)
+
+/** \brief 21C, Receive Data View Register */
+#define SENT_CH4_VIEW /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_VIEW*)0xF000321Cu)
+
+/** Alias (User Manual Name) for SENT_CH4_VIEW.
+* To use register names with standard convension, please use SENT_CH4_VIEW.
+*/
+#define SENT_VIEW4 (SENT_CH4_VIEW)
+
+/** \brief 234, Watch Dog Timer Register */
+#define SENT_CH4_WDT /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_WDT*)0xF0003234u)
+
+/** Alias (User Manual Name) for SENT_CH4_WDT.
+* To use register names with standard convension, please use SENT_CH4_WDT.
+*/
+#define SENT_WDT4 (SENT_CH4_WDT)
+
+/** \brief 244, Channel Fractional Divider Register */
+#define SENT_CH5_CFDR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_CFDR*)0xF0003244u)
+
+/** Alias (User Manual Name) for SENT_CH5_CFDR.
+* To use register names with standard convension, please use SENT_CH5_CFDR.
+*/
+#define SENT_CFDR5 (SENT_CH5_CFDR)
+
+/** \brief 240, Channel Pre Divider Register */
+#define SENT_CH5_CPDR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_CPDR*)0xF0003240u)
+
+/** Alias (User Manual Name) for SENT_CH5_CPDR.
+* To use register names with standard convension, please use SENT_CH5_CPDR.
+*/
+#define SENT_CPDR5 (SENT_CH5_CPDR)
+
+/** \brief 270, Interrupt Node Pointer Register */
+#define SENT_CH5_INP /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_INP*)0xF0003270u)
+
+/** Alias (User Manual Name) for SENT_CH5_INP.
+* To use register names with standard convension, please use SENT_CH5_INP.
+*/
+#define SENT_INP5 (SENT_CH5_INP)
+
+/** \brief 268, Interrupt Clear Register */
+#define SENT_CH5_INTCLR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_INTCLR*)0xF0003268u)
+
+/** Alias (User Manual Name) for SENT_CH5_INTCLR.
+* To use register names with standard convension, please use SENT_CH5_INTCLR.
+*/
+#define SENT_INTCLR5 (SENT_CH5_INTCLR)
+
+/** \brief 26C, Interrupt Enable Register */
+#define SENT_CH5_INTEN /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_INTEN*)0xF000326Cu)
+
+/** Alias (User Manual Name) for SENT_CH5_INTEN.
+* To use register names with standard convension, please use SENT_CH5_INTEN.
+*/
+#define SENT_INTEN5 (SENT_CH5_INTEN)
+
+/** \brief 264, Interrupt Set Register */
+#define SENT_CH5_INTSET /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_INTSET*)0xF0003264u)
+
+/** Alias (User Manual Name) for SENT_CH5_INTSET.
+* To use register names with standard convension, please use SENT_CH5_INTSET.
+*/
+#define SENT_INTSET5 (SENT_CH5_INTSET)
+
+/** \brief 260, Interrupt Status Register */
+#define SENT_CH5_INTSTAT /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_INTSTAT*)0xF0003260u)
+
+/** Alias (User Manual Name) for SENT_CH5_INTSTAT.
+* To use register names with standard convension, please use SENT_CH5_INTSTAT.
+*/
+#define SENT_INTSTAT5 (SENT_CH5_INTSTAT)
+
+/** \brief 254, Input and Output Control Register */
+#define SENT_CH5_IOCR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_IOCR*)0xF0003254u)
+
+/** Alias (User Manual Name) for SENT_CH5_IOCR.
+* To use register names with standard convension, please use SENT_CH5_IOCR.
+*/
+#define SENT_IOCR5 (SENT_CH5_IOCR)
+
+/** \brief 248, Receiver Control Register */
+#define SENT_CH5_RCR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_RCR*)0xF0003248u)
+
+/** Alias (User Manual Name) for SENT_CH5_RCR.
+* To use register names with standard convension, please use SENT_CH5_RCR.
+*/
+#define SENT_RCR5 (SENT_CH5_RCR)
+
+/** \brief 24C, Receive Status Register */
+#define SENT_CH5_RSR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_RSR*)0xF000324Cu)
+
+/** Alias (User Manual Name) for SENT_CH5_RSR.
+* To use register names with standard convension, please use SENT_CH5_RSR.
+*/
+#define SENT_RSR5 (SENT_CH5_RSR)
+
+/** \brief 258, SPC Control Register */
+#define SENT_CH5_SCR /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_SCR*)0xF0003258u)
+
+/** Alias (User Manual Name) for SENT_CH5_SCR.
+* To use register names with standard convension, please use SENT_CH5_SCR.
+*/
+#define SENT_SCR5 (SENT_CH5_SCR)
+
+/** \brief 250, Serial Data and Status Register */
+#define SENT_CH5_SDS /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_SDS*)0xF0003250u)
+
+/** Alias (User Manual Name) for SENT_CH5_SDS.
+* To use register names with standard convension, please use SENT_CH5_SDS.
+*/
+#define SENT_SDS5 (SENT_CH5_SDS)
+
+/** \brief 25C, Receive Data View Register */
+#define SENT_CH5_VIEW /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_VIEW*)0xF000325Cu)
+
+/** Alias (User Manual Name) for SENT_CH5_VIEW.
+* To use register names with standard convension, please use SENT_CH5_VIEW.
+*/
+#define SENT_VIEW5 (SENT_CH5_VIEW)
+
+/** \brief 274, Watch Dog Timer Register */
+#define SENT_CH5_WDT /*lint --e(923)*/ (*(volatile Ifx_SENT_CH_WDT*)0xF0003274u)
+
+/** Alias (User Manual Name) for SENT_CH5_WDT.
+* To use register names with standard convension, please use SENT_CH5_WDT.
+*/
+#define SENT_WDT5 (SENT_CH5_WDT)
+
+/** \brief 0, Clock Control Register */
+#define SENT_CLC /*lint --e(923)*/ (*(volatile Ifx_SENT_CLC*)0xF0003000u)
+
+/** \brief C, SENT Fractional Divider Register */
+#define SENT_FDR /*lint --e(923)*/ (*(volatile Ifx_SENT_FDR*)0xF000300Cu)
+
+/** \brief 8, Module Identification Register */
+#define SENT_ID /*lint --e(923)*/ (*(volatile Ifx_SENT_ID*)0xF0003008u)
+
+/** \brief 14, Interrupt Overview Register */
+#define SENT_INTOV /*lint --e(923)*/ (*(volatile Ifx_SENT_INTOV*)0xF0003014u)
+
+/** \brief F4, Kernel Reset Register 0 */
+#define SENT_KRST0 /*lint --e(923)*/ (*(volatile Ifx_SENT_KRST0*)0xF00030F4u)
+
+/** \brief F0, Kernel Reset Register 1 */
+#define SENT_KRST1 /*lint --e(923)*/ (*(volatile Ifx_SENT_KRST1*)0xF00030F0u)
+
+/** \brief EC, Kernel Reset Status Clear Register */
+#define SENT_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_SENT_KRSTCLR*)0xF00030ECu)
+
+/** \brief E8, OCDS Control and Status */
+#define SENT_OCS /*lint --e(923)*/ (*(volatile Ifx_SENT_OCS*)0xF00030E8u)
+
+/** \brief 80, Receive Data Register */
+#define SENT_RDR0 /*lint --e(923)*/ (*(volatile Ifx_SENT_RDR*)0xF0003080u)
+
+/** \brief 84, Receive Data Register */
+#define SENT_RDR1 /*lint --e(923)*/ (*(volatile Ifx_SENT_RDR*)0xF0003084u)
+
+/** \brief 88, Receive Data Register */
+#define SENT_RDR2 /*lint --e(923)*/ (*(volatile Ifx_SENT_RDR*)0xF0003088u)
+
+/** \brief 8C, Receive Data Register */
+#define SENT_RDR3 /*lint --e(923)*/ (*(volatile Ifx_SENT_RDR*)0xF000308Cu)
+
+/** \brief 90, Receive Data Register */
+#define SENT_RDR4 /*lint --e(923)*/ (*(volatile Ifx_SENT_RDR*)0xF0003090u)
+
+/** \brief 94, Receive Data Register */
+#define SENT_RDR5 /*lint --e(923)*/ (*(volatile Ifx_SENT_RDR*)0xF0003094u)
+
+/** \brief A80, Receive Time Stamp Register */
+#define SENT_RTS0 /*lint --e(923)*/ (*(volatile Ifx_SENT_RTS*)0xF0003A80u)
+
+/** \brief A84, Receive Time Stamp Register */
+#define SENT_RTS1 /*lint --e(923)*/ (*(volatile Ifx_SENT_RTS*)0xF0003A84u)
+
+/** \brief A88, Receive Time Stamp Register */
+#define SENT_RTS2 /*lint --e(923)*/ (*(volatile Ifx_SENT_RTS*)0xF0003A88u)
+
+/** \brief A8C, Receive Time Stamp Register */
+#define SENT_RTS3 /*lint --e(923)*/ (*(volatile Ifx_SENT_RTS*)0xF0003A8Cu)
+
+/** \brief A90, Receive Time Stamp Register */
+#define SENT_RTS4 /*lint --e(923)*/ (*(volatile Ifx_SENT_RTS*)0xF0003A90u)
+
+/** \brief A94, Receive Time Stamp Register */
+#define SENT_RTS5 /*lint --e(923)*/ (*(volatile Ifx_SENT_RTS*)0xF0003A94u)
+
+/** \brief 1C, Time Stamp Predivider Register */
+#define SENT_TPD /*lint --e(923)*/ (*(volatile Ifx_SENT_TPD*)0xF000301Cu)
+
+/** \brief 18, Time Stamp Register */
+#define SENT_TSR /*lint --e(923)*/ (*(volatile Ifx_SENT_TSR*)0xF0003018u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXSENT_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSent_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSent_regdef.h
new file mode 100644
index 0000000..41000a6
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSent_regdef.h
@@ -0,0 +1,699 @@
+/**
+ * \file IfxSent_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Sent Sent
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Sent_Bitfields Bitfields
+ * \ingroup IfxLld_Sent
+ *
+ * \defgroup IfxLld_Sent_union Union
+ * \ingroup IfxLld_Sent
+ *
+ * \defgroup IfxLld_Sent_struct Struct
+ * \ingroup IfxLld_Sent
+ *
+ */
+#ifndef IFXSENT_REGDEF_H
+#define IFXSENT_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Sent_Bitfields
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef struct _Ifx_SENT_ACCEN0_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_SENT_ACCEN0_Bits;
+
+/** \brief Access Enable Register 1 */
+typedef struct _Ifx_SENT_ACCEN1_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_SENT_ACCEN1_Bits;
+
+/** \brief Channel Fractional Divider Register */
+typedef struct _Ifx_SENT_CH_CFDR_Bits
+{
+ unsigned int DIV:12; /**< \brief [11:0] Divider Value (rw) */
+ unsigned int reserved_12:4; /**< \brief \internal Reserved */
+ unsigned int DIVM:12; /**< \brief [27:16] Measured Divider Value (rh) */
+ unsigned int reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_SENT_CH_CFDR_Bits;
+
+/** \brief Channel Pre Divider Register */
+typedef struct _Ifx_SENT_CH_CPDR_Bits
+{
+ unsigned int PDIV:12; /**< \brief [11:0] Divider Factor of Pre Divider for Channel x (rw) */
+ unsigned int reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_SENT_CH_CPDR_Bits;
+
+/** \brief Interrupt Node Pointer Register */
+typedef struct _Ifx_SENT_CH_INP_Bits
+{
+ unsigned int RSI:4; /**< \brief [3:0] Interrupt Node Pointer for Interrupt RSI (rw) */
+ unsigned int RDI:4; /**< \brief [7:4] Interrupt Node Pointer for Interrupt RDI (rw) */
+ unsigned int RBI:4; /**< \brief [11:8] Interrupt Node Pointer for Interrupt RBI (rw) */
+ unsigned int TDI:4; /**< \brief [15:12] Interrupt Node Pointer for Interrupt TDI (rw) */
+ unsigned int TBI:4; /**< \brief [19:16] Interrupt Node Pointer for Interrupt TBI (rw) */
+ unsigned int ERRI:4; /**< \brief [23:20] Interrupt Node Pointer for Interrupt FRI, FDI, NNI, NVI, CRCI, WSI, SCRI (rw) */
+ unsigned int SDI:4; /**< \brief [27:24] Interrupt Node Pointer for Interrupt SDI (rw) */
+ unsigned int WDI:4; /**< \brief [31:28] Interrupt Node Pointer for Interrupt WDI (rw) */
+} Ifx_SENT_CH_INP_Bits;
+
+/** \brief Interrupt Clear Register */
+typedef struct _Ifx_SENT_CH_INTCLR_Bits
+{
+ unsigned int RSI:1; /**< \brief [0:0] Clear Interrupt Request Flag RSI (w) */
+ unsigned int RDI:1; /**< \brief [1:1] Clear Interrupt Request Flag RDI (w) */
+ unsigned int RBI:1; /**< \brief [2:2] Clear Interrupt Request Flag RBI (w) */
+ unsigned int TDI:1; /**< \brief [3:3] Clear Interrupt Request Flag TDI (w) */
+ unsigned int TBI:1; /**< \brief [4:4] Clear Interrupt Request Flag TBI (w) */
+ unsigned int FRI:1; /**< \brief [5:5] Clear Interrupt Request Flag FRI (w) */
+ unsigned int FDI:1; /**< \brief [6:6] Clear Interrupt Request Flag FDI (w) */
+ unsigned int NNI:1; /**< \brief [7:7] Clear Interrupt Request Flag NMI (w) */
+ unsigned int NVI:1; /**< \brief [8:8] Clear Interrupt Request Flag NVI (w) */
+ unsigned int CRCI:1; /**< \brief [9:9] Clear Interrupt Request Flag CRCI (w) */
+ unsigned int WSI:1; /**< \brief [10:10] Clear Interrupt Request Flag WSI (w) */
+ unsigned int SDI:1; /**< \brief [11:11] Clear Interrupt Request Flag SDI (w) */
+ unsigned int SCRI:1; /**< \brief [12:12] Clear Interrupt Request Flag SCRI (w) */
+ unsigned int WDI:1; /**< \brief [13:13] Clear Interrupt Request Flag WDI (w) */
+ unsigned int reserved_14:18; /**< \brief \internal Reserved */
+} Ifx_SENT_CH_INTCLR_Bits;
+
+/** \brief Interrupt Enable Register */
+typedef struct _Ifx_SENT_CH_INTEN_Bits
+{
+ unsigned int RSI:1; /**< \brief [0:0] Enable Interrupt Request RSI (rw) */
+ unsigned int RDI:1; /**< \brief [1:1] Enable Interrupt Request RDI (rw) */
+ unsigned int RBI:1; /**< \brief [2:2] Enable Interrupt Request RBI (rw) */
+ unsigned int TDI:1; /**< \brief [3:3] Enable Interrupt Request TDI (rw) */
+ unsigned int TBI:1; /**< \brief [4:4] Enable Interrupt Request TBI (rw) */
+ unsigned int FRI:1; /**< \brief [5:5] Enable Interrupt Request FRI (rw) */
+ unsigned int FDI:1; /**< \brief [6:6] Enable Interrupt Request FDI (rw) */
+ unsigned int NNI:1; /**< \brief [7:7] Enable Interrupt Request NNI (rw) */
+ unsigned int NVI:1; /**< \brief [8:8] Enable Interrupt Request NVI (rw) */
+ unsigned int CRCI:1; /**< \brief [9:9] Enable Interrupt Request CRCI (rw) */
+ unsigned int WSI:1; /**< \brief [10:10] Enable Interrupt Request WSI (rw) */
+ unsigned int SDI:1; /**< \brief [11:11] Enable Interrupt Request SDI (rw) */
+ unsigned int SCRI:1; /**< \brief [12:12] Enable Interrupt Request SCRI (rw) */
+ unsigned int WDI:1; /**< \brief [13:13] Enable Interrupt Request WDI (rw) */
+ unsigned int reserved_14:18; /**< \brief \internal Reserved */
+} Ifx_SENT_CH_INTEN_Bits;
+
+/** \brief Interrupt Set Register */
+typedef struct _Ifx_SENT_CH_INTSET_Bits
+{
+ unsigned int RSI:1; /**< \brief [0:0] Set Interrupt Request Flag RSI (w) */
+ unsigned int RDI:1; /**< \brief [1:1] Set Interrupt Request Flag RDI (w) */
+ unsigned int RBI:1; /**< \brief [2:2] Set Interrupt Request Flag RBI (w) */
+ unsigned int TDI:1; /**< \brief [3:3] Set Interrupt Request Flag TDI (w) */
+ unsigned int TBI:1; /**< \brief [4:4] Set Interrupt Request Flag TBI (w) */
+ unsigned int FRI:1; /**< \brief [5:5] Set Interrupt Request Flag FRI (w) */
+ unsigned int FDI:1; /**< \brief [6:6] Set Interrupt Request Flag FDI (w) */
+ unsigned int NNI:1; /**< \brief [7:7] Set Interrupt Request Flag NNI (w) */
+ unsigned int NVI:1; /**< \brief [8:8] Set Interrupt Request Flag NVI (w) */
+ unsigned int CRCI:1; /**< \brief [9:9] Set Interrupt Request Flag CRCI (w) */
+ unsigned int WSI:1; /**< \brief [10:10] Set Interrupt Request Flag WSI (w) */
+ unsigned int SDI:1; /**< \brief [11:11] Set Interrupt Request Flag SDI (w) */
+ unsigned int SCRI:1; /**< \brief [12:12] Set Interrupt Request Flag SCRI (w) */
+ unsigned int WDI:1; /**< \brief [13:13] Set Interrupt Request Flag WDI (w) */
+ unsigned int reserved_14:18; /**< \brief \internal Reserved */
+} Ifx_SENT_CH_INTSET_Bits;
+
+/** \brief Interrupt Status Register */
+typedef struct _Ifx_SENT_CH_INTSTAT_Bits
+{
+ unsigned int RSI:1; /**< \brief [0:0] Receive Success Interrupt Request Flag (rh) */
+ unsigned int RDI:1; /**< \brief [1:1] Receive Data Interrupt Request Flag (rh) */
+ unsigned int RBI:1; /**< \brief [2:2] Receive Buffer Overflow Interrupt Request Flag (rh) */
+ unsigned int TDI:1; /**< \brief [3:3] Transfer Data Interrupt Request Flag (rh) */
+ unsigned int TBI:1; /**< \brief [4:4] Transmit Buffer Underflow Interrupt Request Flag (rh) */
+ unsigned int FRI:1; /**< \brief [5:5] Frequency Range Interrupt Request Flag (rh) */
+ unsigned int FDI:1; /**< \brief [6:6] Frequency Drift Interrupt Request Flag (rh) */
+ unsigned int NNI:1; /**< \brief [7:7] Number of Nibbles Wrong Request Flag (rh) */
+ unsigned int NVI:1; /**< \brief [8:8] Nibbles Value out of Range Request Flag (rh) */
+ unsigned int CRCI:1; /**< \brief [9:9] CRC Error Request Flag (rh) */
+ unsigned int WSI:1; /**< \brief [10:10] Wrong Status and Communication Nibble Error Request Flag (rh) */
+ unsigned int SDI:1; /**< \brief [11:11] Serial Data Receive Interrupt Request Flag (rh) */
+ unsigned int SCRI:1; /**< \brief [12:12] Serial Data CRC Error Request Flag (rh) */
+ unsigned int WDI:1; /**< \brief [13:13] Watch Dog Error Request Flag (rh) */
+ unsigned int reserved_14:18; /**< \brief \internal Reserved */
+} Ifx_SENT_CH_INTSTAT_Bits;
+
+/** \brief Input and Output Control Register */
+typedef struct _Ifx_SENT_CH_IOCR_Bits
+{
+ unsigned int ALTI:2; /**< \brief [1:0] Alternate Input Select (rw) */
+ unsigned int reserved_2:2; /**< \brief \internal Reserved */
+ unsigned int DEPTH:4; /**< \brief [7:4] Digital Glitch Filter Depth (rw) */
+ unsigned int OIE:1; /**< \brief [8:8] Output Inverter Enable Channel x (rw) */
+ unsigned int IIE:1; /**< \brief [9:9] Input Inverter Enable Channel x (rw) */
+ unsigned int CEC:1; /**< \brief [10:10] Clear Edge Counter (w) */
+ unsigned int reserved_11:1; /**< \brief \internal Reserved */
+ unsigned int REG:1; /**< \brief [12:12] Rising Edge Glitch Flag for Channel x (rh) */
+ unsigned int FEG:1; /**< \brief [13:13] Falling Edge Glitch Flag for Channel x (rh) */
+ unsigned int CREG:1; /**< \brief [14:14] Clear Rising Edge Glitch Flag for Channel x (rw) */
+ unsigned int CFEG:1; /**< \brief [15:15] Clear Falling Edge Glitch Flag for Channel x (rw) */
+ unsigned int ETS:4; /**< \brief [19:16] External Trigger Select (rw) */
+ unsigned int EC:8; /**< \brief [27:20] Edge Counter (rh) */
+ unsigned int CTR:1; /**< \brief [28:28] Clear Trigger Monitor Flag for Channel x (rw) */
+ unsigned int TRM:1; /**< \brief [29:29] Trigger Monitor Flag for Channel x (rh) */
+ unsigned int RXM:1; /**< \brief [30:30] Receive Monitor for Channel x (rh) */
+ unsigned int TXM:1; /**< \brief [31:31] Transmit Monitor for Channel x (rh) */
+} Ifx_SENT_CH_IOCR_Bits;
+
+/** \brief Receiver Control Register */
+typedef struct _Ifx_SENT_CH_RCR_Bits
+{
+ unsigned int CEN:1; /**< \brief [0:0] Channel Enable (rw) */
+ unsigned int IEP:1; /**< \brief [1:1] Ignore End Pulse (rw) */
+ unsigned int ACE:1; /**< \brief [2:2] Alternative CRC Mode Enable (rw) */
+ unsigned int SNI:1; /**< \brief [3:3] Status Nibble Included in CRC (rw) */
+ unsigned int SDP:1; /**< \brief [4:4] Serial Data Processing Mode (rw) */
+ unsigned int SCDIS:1; /**< \brief [5:5] CRC for Serial Data Disabled Mode (rw) */
+ unsigned int CDIS:1; /**< \brief [6:6] CRC Disabled Mode (rw) */
+ unsigned int CFC:1; /**< \brief [7:7] Consecutive Frame Check (rw) */
+ unsigned int FRL:8; /**< \brief [15:8] Frame Length (rw) */
+ unsigned int CRZ:1; /**< \brief [16:16] CRC with Zero Nibble for Serial Data (rw) */
+ unsigned int ESF:1; /**< \brief [17:17] Extended Serial Frame Mode (rw) */
+ unsigned int IDE:1; /**< \brief [18:18] Ignore Drift Error Mode (rw) */
+ unsigned int SUSEN:1; /**< \brief [19:19] Suspend Enable (rw) */
+ unsigned int reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_SENT_CH_RCR_Bits;
+
+/** \brief Receive Status Register */
+typedef struct _Ifx_SENT_CH_RSR_Bits
+{
+ unsigned int CRC:4; /**< \brief [3:0] CRC (r) */
+ unsigned int CST:2; /**< \brief [5:4] Channel Status (r) */
+ unsigned int reserved_6:2; /**< \brief \internal Reserved */
+ unsigned int SCN:4; /**< \brief [11:8] Status and Communication Nibble (r) */
+ unsigned int reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_SENT_CH_RSR_Bits;
+
+/** \brief SPC Control Register */
+typedef struct _Ifx_SENT_CH_SCR_Bits
+{
+ unsigned int PLEN:6; /**< \brief [5:0] Pulse Length (rw) */
+ unsigned int TRIG:2; /**< \brief [7:6] Trigger Source and Mode Selection (rw) */
+ unsigned int DEL:6; /**< \brief [13:8] Delay Length (rw) */
+ unsigned int BASE:1; /**< \brief [14:14] Time Base (rw) */
+ unsigned int TRQ:1; /**< \brief [15:15] Transfer Request in Progress (r) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_SENT_CH_SCR_Bits;
+
+/** \brief Serial Data and Status Register */
+typedef struct _Ifx_SENT_CH_SDS_Bits
+{
+ unsigned int SD:16; /**< \brief [15:0] Serial Data (r) */
+ unsigned int MID:8; /**< \brief [23:16] Message ID (r) */
+ unsigned int SCRC:6; /**< \brief [29:24] SCRC (r) */
+ unsigned int reserved_30:1; /**< \brief \internal Reserved */
+ unsigned int CON:1; /**< \brief [31:31] Configuration bit (r) */
+} Ifx_SENT_CH_SDS_Bits;
+
+/** \brief Receive Data View Register */
+typedef struct _Ifx_SENT_CH_VIEW_Bits
+{
+ unsigned int RDNP0:3; /**< \brief [2:0] Receive Data Target Nibble Pointer 0 (rw) */
+ unsigned int reserved_3:1; /**< \brief \internal Reserved */
+ unsigned int RDNP1:3; /**< \brief [6:4] Receive Data Target Nibble Pointer 1 (rw) */
+ unsigned int reserved_7:1; /**< \brief \internal Reserved */
+ unsigned int RDNP2:3; /**< \brief [10:8] Receive Data Target Nibble Pointer 2 (rw) */
+ unsigned int reserved_11:1; /**< \brief \internal Reserved */
+ unsigned int RDNP3:3; /**< \brief [14:12] Receive Data Target Nibble Pointer 3 (rw) */
+ unsigned int reserved_15:1; /**< \brief \internal Reserved */
+ unsigned int RDNP4:3; /**< \brief [18:16] Receive Data Target Nibble Pointer 4 (rw) */
+ unsigned int reserved_19:1; /**< \brief \internal Reserved */
+ unsigned int RDNP5:3; /**< \brief [22:20] Receive Data Target Nibble Pointer 5 (rw) */
+ unsigned int reserved_23:1; /**< \brief \internal Reserved */
+ unsigned int RDNP6:3; /**< \brief [26:24] Receive Data Target Nibble Pointer 6 (rw) */
+ unsigned int reserved_27:1; /**< \brief \internal Reserved */
+ unsigned int RDNP7:3; /**< \brief [30:28] Receive Data Target Nibble Pointer 7 (rw) */
+ unsigned int reserved_31:1; /**< \brief \internal Reserved */
+} Ifx_SENT_CH_VIEW_Bits;
+
+/** \brief Watch Dog Timer Register */
+typedef struct _Ifx_SENT_CH_WDT_Bits
+{
+ unsigned int WDLx:16; /**< \brief [15:0] Watch Dog Timer Limit (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_SENT_CH_WDT_Bits;
+
+/** \brief Clock Control Register */
+typedef struct _Ifx_SENT_CLC_Bits
+{
+ unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
+ unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
+ unsigned int reserved_2:1; /**< \brief \internal Reserved */
+ unsigned int EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control (rw) */
+ unsigned int reserved_4:4; /**< \brief \internal Reserved */
+ unsigned int RMC:8; /**< \brief [15:8] 8-bit Clock Divider Value in RUN Mode (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_SENT_CLC_Bits;
+
+/** \brief SENT Fractional Divider Register */
+typedef struct _Ifx_SENT_FDR_Bits
+{
+ unsigned int STEP:10; /**< \brief [9:0] Step Value (rw) */
+ unsigned int reserved_10:4; /**< \brief \internal Reserved */
+ unsigned int DM:2; /**< \brief [15:14] Divider Mode (rw) */
+ unsigned int RESULT:10; /**< \brief [25:16] Result Value (rh) */
+ unsigned int reserved_26:6; /**< \brief \internal Reserved */
+} Ifx_SENT_FDR_Bits;
+
+/** \brief Module Identification Register */
+typedef struct _Ifx_SENT_ID_Bits
+{
+ unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
+ unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_SENT_ID_Bits;
+
+/** \brief Interrupt Overview Register */
+typedef struct _Ifx_SENT_INTOV_Bits
+{
+ unsigned int IPC0:1; /**< \brief [0:0] Interrupt Pending on Channel 0 (rh) */
+ unsigned int IPC1:1; /**< \brief [1:1] Interrupt Pending on Channel 1 (rh) */
+ unsigned int IPC2:1; /**< \brief [2:2] Interrupt Pending on Channel 2 (rh) */
+ unsigned int IPC3:1; /**< \brief [3:3] Interrupt Pending on Channel 3 (rh) */
+ unsigned int IPC4:1; /**< \brief [4:4] Interrupt Pending on Channel 4 (rh) */
+ unsigned int IPC5:1; /**< \brief [5:5] Interrupt Pending on Channel 5 (rh) */
+ unsigned int reserved_6:26; /**< \brief \internal Reserved */
+} Ifx_SENT_INTOV_Bits;
+
+/** \brief Kernel Reset Register 0 */
+typedef struct _Ifx_SENT_KRST0_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rh) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_SENT_KRST0_Bits;
+
+/** \brief Kernel Reset Register 1 */
+typedef struct _Ifx_SENT_KRST1_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_SENT_KRST1_Bits;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef struct _Ifx_SENT_KRSTCLR_Bits
+{
+ unsigned int CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_SENT_KRSTCLR_Bits;
+
+/** \brief OCDS Control and Status */
+typedef struct _Ifx_SENT_OCS_Bits
+{
+ unsigned int reserved_0:24; /**< \brief \internal Reserved */
+ unsigned int SUS:4; /**< \brief [27:24] OCDS Suspend Control (rw) */
+ unsigned int SUS_P:1; /**< \brief [28:28] SUS Write Protection (w) */
+ unsigned int SUSSTA:1; /**< \brief [29:29] Suspend State (rh) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_SENT_OCS_Bits;
+
+/** \brief Receive Data Register */
+typedef struct _Ifx_SENT_RDR_Bits
+{
+ unsigned int RD0:4; /**< \brief [3:0] Receive Data Nibble 0 (rh) */
+ unsigned int RD1:4; /**< \brief [7:4] Receive Data Nibble 1 (rh) */
+ unsigned int RD2:4; /**< \brief [11:8] Receive Data Nibble 2 (rh) */
+ unsigned int RD3:4; /**< \brief [15:12] Receive Data Nibble 3 (rh) */
+ unsigned int RD4:4; /**< \brief [19:16] Receive Data Nibble 4 (rh) */
+ unsigned int RD5:4; /**< \brief [23:20] Receive Data Nibble 5 (rh) */
+ unsigned int RD6:4; /**< \brief [27:24] Receive Data Nibble 6 (rh) */
+ unsigned int RD7:4; /**< \brief [31:28] Receive Data Nibble 7 (rh) */
+} Ifx_SENT_RDR_Bits;
+
+/** \brief Receive Time Stamp Register */
+typedef struct _Ifx_SENT_RTS_Bits
+{
+ unsigned int LTS:32; /**< \brief [31:0] Last Receive Time Stamp for Channel x (r) */
+} Ifx_SENT_RTS_Bits;
+
+/** \brief Time Stamp Predivider Register */
+typedef struct _Ifx_SENT_TPD_Bits
+{
+ unsigned int TDIV:20; /**< \brief [19:0] Divider Factor of Pre Divider for TSR (rw) */
+ unsigned int reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_SENT_TPD_Bits;
+
+/** \brief Time Stamp Register */
+typedef struct _Ifx_SENT_TSR_Bits
+{
+ unsigned int CTS:32; /**< \brief [31:0] Current Time Stamp for the Module (r) */
+} Ifx_SENT_TSR_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Sent_union
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SENT_ACCEN0_Bits B; /**< \brief Bitfield access */
+} Ifx_SENT_ACCEN0;
+
+/** \brief Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SENT_ACCEN1_Bits B; /**< \brief Bitfield access */
+} Ifx_SENT_ACCEN1;
+
+/** \brief Channel Fractional Divider Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SENT_CH_CFDR_Bits B; /**< \brief Bitfield access */
+} Ifx_SENT_CH_CFDR;
+
+/** \brief Channel Pre Divider Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SENT_CH_CPDR_Bits B; /**< \brief Bitfield access */
+} Ifx_SENT_CH_CPDR;
+
+/** \brief Interrupt Node Pointer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SENT_CH_INP_Bits B; /**< \brief Bitfield access */
+} Ifx_SENT_CH_INP;
+
+/** \brief Interrupt Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SENT_CH_INTCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_SENT_CH_INTCLR;
+
+/** \brief Interrupt Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SENT_CH_INTEN_Bits B; /**< \brief Bitfield access */
+} Ifx_SENT_CH_INTEN;
+
+/** \brief Interrupt Set Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SENT_CH_INTSET_Bits B; /**< \brief Bitfield access */
+} Ifx_SENT_CH_INTSET;
+
+/** \brief Interrupt Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SENT_CH_INTSTAT_Bits B; /**< \brief Bitfield access */
+} Ifx_SENT_CH_INTSTAT;
+
+/** \brief Input and Output Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SENT_CH_IOCR_Bits B; /**< \brief Bitfield access */
+} Ifx_SENT_CH_IOCR;
+
+/** \brief Receiver Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SENT_CH_RCR_Bits B; /**< \brief Bitfield access */
+} Ifx_SENT_CH_RCR;
+
+/** \brief Receive Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SENT_CH_RSR_Bits B; /**< \brief Bitfield access */
+} Ifx_SENT_CH_RSR;
+
+/** \brief SPC Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SENT_CH_SCR_Bits B; /**< \brief Bitfield access */
+} Ifx_SENT_CH_SCR;
+
+/** \brief Serial Data and Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SENT_CH_SDS_Bits B; /**< \brief Bitfield access */
+} Ifx_SENT_CH_SDS;
+
+/** \brief Receive Data View Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SENT_CH_VIEW_Bits B; /**< \brief Bitfield access */
+} Ifx_SENT_CH_VIEW;
+
+/** \brief Watch Dog Timer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SENT_CH_WDT_Bits B; /**< \brief Bitfield access */
+} Ifx_SENT_CH_WDT;
+
+/** \brief Clock Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SENT_CLC_Bits B; /**< \brief Bitfield access */
+} Ifx_SENT_CLC;
+
+/** \brief SENT Fractional Divider Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SENT_FDR_Bits B; /**< \brief Bitfield access */
+} Ifx_SENT_FDR;
+
+/** \brief Module Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SENT_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_SENT_ID;
+
+/** \brief Interrupt Overview Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SENT_INTOV_Bits B; /**< \brief Bitfield access */
+} Ifx_SENT_INTOV;
+
+/** \brief Kernel Reset Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SENT_KRST0_Bits B; /**< \brief Bitfield access */
+} Ifx_SENT_KRST0;
+
+/** \brief Kernel Reset Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SENT_KRST1_Bits B; /**< \brief Bitfield access */
+} Ifx_SENT_KRST1;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SENT_KRSTCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_SENT_KRSTCLR;
+
+/** \brief OCDS Control and Status */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SENT_OCS_Bits B; /**< \brief Bitfield access */
+} Ifx_SENT_OCS;
+
+/** \brief Receive Data Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SENT_RDR_Bits B; /**< \brief Bitfield access */
+} Ifx_SENT_RDR;
+
+/** \brief Receive Time Stamp Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SENT_RTS_Bits B; /**< \brief Bitfield access */
+} Ifx_SENT_RTS;
+
+/** \brief Time Stamp Predivider Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SENT_TPD_Bits B; /**< \brief Bitfield access */
+} Ifx_SENT_TPD;
+
+/** \brief Time Stamp Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SENT_TSR_Bits B; /**< \brief Bitfield access */
+} Ifx_SENT_TSR;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Sent_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L1
+ * \{ */
+
+/** \brief Channel objects */
+typedef volatile struct _Ifx_SENT_CH
+{
+ Ifx_SENT_CH_CPDR CPDR; /**< \brief 0, Channel Pre Divider Register */
+ Ifx_SENT_CH_CFDR CFDR; /**< \brief 4, Channel Fractional Divider Register */
+ Ifx_SENT_CH_RCR RCR; /**< \brief 8, Receiver Control Register */
+ Ifx_SENT_CH_RSR RSR; /**< \brief C, Receive Status Register */
+ Ifx_SENT_CH_SDS SDS; /**< \brief 10, Serial Data and Status Register */
+ Ifx_SENT_CH_IOCR IOCR; /**< \brief 14, Input and Output Control Register */
+ Ifx_SENT_CH_SCR SCR; /**< \brief 18, SPC Control Register */
+ Ifx_SENT_CH_VIEW VIEW; /**< \brief 1C, Receive Data View Register */
+ Ifx_SENT_CH_INTSTAT INTSTAT; /**< \brief 20, Interrupt Status Register */
+ Ifx_SENT_CH_INTSET INTSET; /**< \brief 24, Interrupt Set Register */
+ Ifx_SENT_CH_INTCLR INTCLR; /**< \brief 28, Interrupt Clear Register */
+ Ifx_SENT_CH_INTEN INTEN; /**< \brief 2C, Interrupt Enable Register */
+ Ifx_SENT_CH_INP INP; /**< \brief 30, Interrupt Node Pointer Register */
+ Ifx_SENT_CH_WDT WDT; /**< \brief 34, Watch Dog Timer Register */
+ unsigned char reserved_38[8]; /**< \brief 38, \internal Reserved */
+} Ifx_SENT_CH;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Sent_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief SENT object */
+typedef volatile struct _Ifx_SENT
+{
+ Ifx_SENT_CLC CLC; /**< \brief 0, Clock Control Register */
+ unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
+ Ifx_SENT_ID ID; /**< \brief 8, Module Identification Register */
+ Ifx_SENT_FDR FDR; /**< \brief C, SENT Fractional Divider Register */
+ unsigned char reserved_10[4]; /**< \brief 10, \internal Reserved */
+ Ifx_SENT_INTOV INTOV; /**< \brief 14, Interrupt Overview Register */
+ Ifx_SENT_TSR TSR; /**< \brief 18, Time Stamp Register */
+ Ifx_SENT_TPD TPD; /**< \brief 1C, Time Stamp Predivider Register */
+ unsigned char reserved_20[96]; /**< \brief 20, \internal Reserved */
+ Ifx_SENT_RDR RDR[6]; /**< \brief 80, Receive Data Register */
+ unsigned char reserved_98[80]; /**< \brief 98, \internal Reserved */
+ Ifx_SENT_OCS OCS; /**< \brief E8, OCDS Control and Status */
+ Ifx_SENT_KRSTCLR KRSTCLR; /**< \brief EC, Kernel Reset Status Clear Register */
+ Ifx_SENT_KRST1 KRST1; /**< \brief F0, Kernel Reset Register 1 */
+ Ifx_SENT_KRST0 KRST0; /**< \brief F4, Kernel Reset Register 0 */
+ Ifx_SENT_ACCEN1 ACCEN1; /**< \brief F8, Access Enable Register 1 */
+ Ifx_SENT_ACCEN0 ACCEN0; /**< \brief FC, Access Enable Register 0 */
+ Ifx_SENT_CH CH[6]; /**< \brief 100, Channel objects */
+ unsigned char reserved_280[2048]; /**< \brief 280, \internal Reserved */
+ Ifx_SENT_RTS RTS[6]; /**< \brief A80, Receive Time Stamp Register */
+ unsigned char reserved_A98[104]; /**< \brief A98, \internal Reserved */
+} Ifx_SENT;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXSENT_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSmu_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSmu_bf.h
new file mode 100644
index 0000000..1643ed1
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSmu_bf.h
@@ -0,0 +1,2700 @@
+/**
+ * \file IfxSmu_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Smu_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Smu
+ *
+ */
+#ifndef IFXSMU_BF_H
+#define IFXSMU_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Smu_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN0 */
+#define IFX_SMU_ACCEN0_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN0 */
+#define IFX_SMU_ACCEN0_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN0 */
+#define IFX_SMU_ACCEN0_EN0_OFF (0u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN10 */
+#define IFX_SMU_ACCEN0_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN10 */
+#define IFX_SMU_ACCEN0_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN10 */
+#define IFX_SMU_ACCEN0_EN10_OFF (10u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN11 */
+#define IFX_SMU_ACCEN0_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN11 */
+#define IFX_SMU_ACCEN0_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN11 */
+#define IFX_SMU_ACCEN0_EN11_OFF (11u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN12 */
+#define IFX_SMU_ACCEN0_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN12 */
+#define IFX_SMU_ACCEN0_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN12 */
+#define IFX_SMU_ACCEN0_EN12_OFF (12u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN13 */
+#define IFX_SMU_ACCEN0_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN13 */
+#define IFX_SMU_ACCEN0_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN13 */
+#define IFX_SMU_ACCEN0_EN13_OFF (13u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN14 */
+#define IFX_SMU_ACCEN0_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN14 */
+#define IFX_SMU_ACCEN0_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN14 */
+#define IFX_SMU_ACCEN0_EN14_OFF (14u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN15 */
+#define IFX_SMU_ACCEN0_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN15 */
+#define IFX_SMU_ACCEN0_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN15 */
+#define IFX_SMU_ACCEN0_EN15_OFF (15u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN16 */
+#define IFX_SMU_ACCEN0_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN16 */
+#define IFX_SMU_ACCEN0_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN16 */
+#define IFX_SMU_ACCEN0_EN16_OFF (16u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN17 */
+#define IFX_SMU_ACCEN0_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN17 */
+#define IFX_SMU_ACCEN0_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN17 */
+#define IFX_SMU_ACCEN0_EN17_OFF (17u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN18 */
+#define IFX_SMU_ACCEN0_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN18 */
+#define IFX_SMU_ACCEN0_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN18 */
+#define IFX_SMU_ACCEN0_EN18_OFF (18u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN19 */
+#define IFX_SMU_ACCEN0_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN19 */
+#define IFX_SMU_ACCEN0_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN19 */
+#define IFX_SMU_ACCEN0_EN19_OFF (19u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN1 */
+#define IFX_SMU_ACCEN0_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN1 */
+#define IFX_SMU_ACCEN0_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN1 */
+#define IFX_SMU_ACCEN0_EN1_OFF (1u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN20 */
+#define IFX_SMU_ACCEN0_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN20 */
+#define IFX_SMU_ACCEN0_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN20 */
+#define IFX_SMU_ACCEN0_EN20_OFF (20u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN21 */
+#define IFX_SMU_ACCEN0_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN21 */
+#define IFX_SMU_ACCEN0_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN21 */
+#define IFX_SMU_ACCEN0_EN21_OFF (21u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN22 */
+#define IFX_SMU_ACCEN0_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN22 */
+#define IFX_SMU_ACCEN0_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN22 */
+#define IFX_SMU_ACCEN0_EN22_OFF (22u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN23 */
+#define IFX_SMU_ACCEN0_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN23 */
+#define IFX_SMU_ACCEN0_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN23 */
+#define IFX_SMU_ACCEN0_EN23_OFF (23u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN24 */
+#define IFX_SMU_ACCEN0_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN24 */
+#define IFX_SMU_ACCEN0_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN24 */
+#define IFX_SMU_ACCEN0_EN24_OFF (24u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN25 */
+#define IFX_SMU_ACCEN0_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN25 */
+#define IFX_SMU_ACCEN0_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN25 */
+#define IFX_SMU_ACCEN0_EN25_OFF (25u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN26 */
+#define IFX_SMU_ACCEN0_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN26 */
+#define IFX_SMU_ACCEN0_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN26 */
+#define IFX_SMU_ACCEN0_EN26_OFF (26u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN27 */
+#define IFX_SMU_ACCEN0_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN27 */
+#define IFX_SMU_ACCEN0_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN27 */
+#define IFX_SMU_ACCEN0_EN27_OFF (27u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN28 */
+#define IFX_SMU_ACCEN0_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN28 */
+#define IFX_SMU_ACCEN0_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN28 */
+#define IFX_SMU_ACCEN0_EN28_OFF (28u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN29 */
+#define IFX_SMU_ACCEN0_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN29 */
+#define IFX_SMU_ACCEN0_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN29 */
+#define IFX_SMU_ACCEN0_EN29_OFF (29u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN2 */
+#define IFX_SMU_ACCEN0_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN2 */
+#define IFX_SMU_ACCEN0_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN2 */
+#define IFX_SMU_ACCEN0_EN2_OFF (2u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN30 */
+#define IFX_SMU_ACCEN0_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN30 */
+#define IFX_SMU_ACCEN0_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN30 */
+#define IFX_SMU_ACCEN0_EN30_OFF (30u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN31 */
+#define IFX_SMU_ACCEN0_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN31 */
+#define IFX_SMU_ACCEN0_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN31 */
+#define IFX_SMU_ACCEN0_EN31_OFF (31u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN3 */
+#define IFX_SMU_ACCEN0_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN3 */
+#define IFX_SMU_ACCEN0_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN3 */
+#define IFX_SMU_ACCEN0_EN3_OFF (3u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN4 */
+#define IFX_SMU_ACCEN0_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN4 */
+#define IFX_SMU_ACCEN0_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN4 */
+#define IFX_SMU_ACCEN0_EN4_OFF (4u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN5 */
+#define IFX_SMU_ACCEN0_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN5 */
+#define IFX_SMU_ACCEN0_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN5 */
+#define IFX_SMU_ACCEN0_EN5_OFF (5u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN6 */
+#define IFX_SMU_ACCEN0_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN6 */
+#define IFX_SMU_ACCEN0_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN6 */
+#define IFX_SMU_ACCEN0_EN6_OFF (6u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN7 */
+#define IFX_SMU_ACCEN0_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN7 */
+#define IFX_SMU_ACCEN0_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN7 */
+#define IFX_SMU_ACCEN0_EN7_OFF (7u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN8 */
+#define IFX_SMU_ACCEN0_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN8 */
+#define IFX_SMU_ACCEN0_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN8 */
+#define IFX_SMU_ACCEN0_EN8_OFF (8u)
+
+/** \brief Length for Ifx_SMU_ACCEN0_Bits.EN9 */
+#define IFX_SMU_ACCEN0_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_ACCEN0_Bits.EN9 */
+#define IFX_SMU_ACCEN0_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_ACCEN0_Bits.EN9 */
+#define IFX_SMU_ACCEN0_EN9_OFF (9u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF0 */
+#define IFX_SMU_AD_DF0_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF0 */
+#define IFX_SMU_AD_DF0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF0 */
+#define IFX_SMU_AD_DF0_OFF (0u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF10 */
+#define IFX_SMU_AD_DF10_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF10 */
+#define IFX_SMU_AD_DF10_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF10 */
+#define IFX_SMU_AD_DF10_OFF (10u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF11 */
+#define IFX_SMU_AD_DF11_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF11 */
+#define IFX_SMU_AD_DF11_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF11 */
+#define IFX_SMU_AD_DF11_OFF (11u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF12 */
+#define IFX_SMU_AD_DF12_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF12 */
+#define IFX_SMU_AD_DF12_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF12 */
+#define IFX_SMU_AD_DF12_OFF (12u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF13 */
+#define IFX_SMU_AD_DF13_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF13 */
+#define IFX_SMU_AD_DF13_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF13 */
+#define IFX_SMU_AD_DF13_OFF (13u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF14 */
+#define IFX_SMU_AD_DF14_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF14 */
+#define IFX_SMU_AD_DF14_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF14 */
+#define IFX_SMU_AD_DF14_OFF (14u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF15 */
+#define IFX_SMU_AD_DF15_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF15 */
+#define IFX_SMU_AD_DF15_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF15 */
+#define IFX_SMU_AD_DF15_OFF (15u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF16 */
+#define IFX_SMU_AD_DF16_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF16 */
+#define IFX_SMU_AD_DF16_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF16 */
+#define IFX_SMU_AD_DF16_OFF (16u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF17 */
+#define IFX_SMU_AD_DF17_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF17 */
+#define IFX_SMU_AD_DF17_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF17 */
+#define IFX_SMU_AD_DF17_OFF (17u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF18 */
+#define IFX_SMU_AD_DF18_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF18 */
+#define IFX_SMU_AD_DF18_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF18 */
+#define IFX_SMU_AD_DF18_OFF (18u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF19 */
+#define IFX_SMU_AD_DF19_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF19 */
+#define IFX_SMU_AD_DF19_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF19 */
+#define IFX_SMU_AD_DF19_OFF (19u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF1 */
+#define IFX_SMU_AD_DF1_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF1 */
+#define IFX_SMU_AD_DF1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF1 */
+#define IFX_SMU_AD_DF1_OFF (1u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF20 */
+#define IFX_SMU_AD_DF20_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF20 */
+#define IFX_SMU_AD_DF20_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF20 */
+#define IFX_SMU_AD_DF20_OFF (20u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF21 */
+#define IFX_SMU_AD_DF21_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF21 */
+#define IFX_SMU_AD_DF21_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF21 */
+#define IFX_SMU_AD_DF21_OFF (21u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF22 */
+#define IFX_SMU_AD_DF22_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF22 */
+#define IFX_SMU_AD_DF22_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF22 */
+#define IFX_SMU_AD_DF22_OFF (22u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF23 */
+#define IFX_SMU_AD_DF23_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF23 */
+#define IFX_SMU_AD_DF23_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF23 */
+#define IFX_SMU_AD_DF23_OFF (23u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF24 */
+#define IFX_SMU_AD_DF24_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF24 */
+#define IFX_SMU_AD_DF24_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF24 */
+#define IFX_SMU_AD_DF24_OFF (24u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF25 */
+#define IFX_SMU_AD_DF25_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF25 */
+#define IFX_SMU_AD_DF25_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF25 */
+#define IFX_SMU_AD_DF25_OFF (25u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF26 */
+#define IFX_SMU_AD_DF26_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF26 */
+#define IFX_SMU_AD_DF26_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF26 */
+#define IFX_SMU_AD_DF26_OFF (26u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF27 */
+#define IFX_SMU_AD_DF27_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF27 */
+#define IFX_SMU_AD_DF27_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF27 */
+#define IFX_SMU_AD_DF27_OFF (27u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF28 */
+#define IFX_SMU_AD_DF28_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF28 */
+#define IFX_SMU_AD_DF28_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF28 */
+#define IFX_SMU_AD_DF28_OFF (28u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF29 */
+#define IFX_SMU_AD_DF29_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF29 */
+#define IFX_SMU_AD_DF29_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF29 */
+#define IFX_SMU_AD_DF29_OFF (29u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF2 */
+#define IFX_SMU_AD_DF2_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF2 */
+#define IFX_SMU_AD_DF2_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF2 */
+#define IFX_SMU_AD_DF2_OFF (2u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF30 */
+#define IFX_SMU_AD_DF30_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF30 */
+#define IFX_SMU_AD_DF30_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF30 */
+#define IFX_SMU_AD_DF30_OFF (30u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF31 */
+#define IFX_SMU_AD_DF31_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF31 */
+#define IFX_SMU_AD_DF31_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF31 */
+#define IFX_SMU_AD_DF31_OFF (31u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF3 */
+#define IFX_SMU_AD_DF3_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF3 */
+#define IFX_SMU_AD_DF3_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF3 */
+#define IFX_SMU_AD_DF3_OFF (3u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF4 */
+#define IFX_SMU_AD_DF4_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF4 */
+#define IFX_SMU_AD_DF4_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF4 */
+#define IFX_SMU_AD_DF4_OFF (4u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF5 */
+#define IFX_SMU_AD_DF5_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF5 */
+#define IFX_SMU_AD_DF5_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF5 */
+#define IFX_SMU_AD_DF5_OFF (5u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF6 */
+#define IFX_SMU_AD_DF6_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF6 */
+#define IFX_SMU_AD_DF6_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF6 */
+#define IFX_SMU_AD_DF6_OFF (6u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF7 */
+#define IFX_SMU_AD_DF7_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF7 */
+#define IFX_SMU_AD_DF7_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF7 */
+#define IFX_SMU_AD_DF7_OFF (7u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF8 */
+#define IFX_SMU_AD_DF8_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF8 */
+#define IFX_SMU_AD_DF8_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF8 */
+#define IFX_SMU_AD_DF8_OFF (8u)
+
+/** \brief Length for Ifx_SMU_AD_Bits.DF9 */
+#define IFX_SMU_AD_DF9_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AD_Bits.DF9 */
+#define IFX_SMU_AD_DF9_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AD_Bits.DF9 */
+#define IFX_SMU_AD_DF9_OFF (9u)
+
+/** \brief Length for Ifx_SMU_AFCNT_Bits.ACNT */
+#define IFX_SMU_AFCNT_ACNT_LEN (8u)
+
+/** \brief Mask for Ifx_SMU_AFCNT_Bits.ACNT */
+#define IFX_SMU_AFCNT_ACNT_MSK (0xffu)
+
+/** \brief Offset for Ifx_SMU_AFCNT_Bits.ACNT */
+#define IFX_SMU_AFCNT_ACNT_OFF (8u)
+
+/** \brief Length for Ifx_SMU_AFCNT_Bits.ACO */
+#define IFX_SMU_AFCNT_ACO_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AFCNT_Bits.ACO */
+#define IFX_SMU_AFCNT_ACO_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AFCNT_Bits.ACO */
+#define IFX_SMU_AFCNT_ACO_OFF (31u)
+
+/** \brief Length for Ifx_SMU_AFCNT_Bits.FCNT */
+#define IFX_SMU_AFCNT_FCNT_LEN (4u)
+
+/** \brief Mask for Ifx_SMU_AFCNT_Bits.FCNT */
+#define IFX_SMU_AFCNT_FCNT_MSK (0xfu)
+
+/** \brief Offset for Ifx_SMU_AFCNT_Bits.FCNT */
+#define IFX_SMU_AFCNT_FCNT_OFF (0u)
+
+/** \brief Length for Ifx_SMU_AFCNT_Bits.FCO */
+#define IFX_SMU_AFCNT_FCO_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AFCNT_Bits.FCO */
+#define IFX_SMU_AFCNT_FCO_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AFCNT_Bits.FCO */
+#define IFX_SMU_AFCNT_FCO_OFF (30u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF0 */
+#define IFX_SMU_AG_SF0_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF0 */
+#define IFX_SMU_AG_SF0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF0 */
+#define IFX_SMU_AG_SF0_OFF (0u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF10 */
+#define IFX_SMU_AG_SF10_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF10 */
+#define IFX_SMU_AG_SF10_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF10 */
+#define IFX_SMU_AG_SF10_OFF (10u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF11 */
+#define IFX_SMU_AG_SF11_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF11 */
+#define IFX_SMU_AG_SF11_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF11 */
+#define IFX_SMU_AG_SF11_OFF (11u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF12 */
+#define IFX_SMU_AG_SF12_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF12 */
+#define IFX_SMU_AG_SF12_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF12 */
+#define IFX_SMU_AG_SF12_OFF (12u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF13 */
+#define IFX_SMU_AG_SF13_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF13 */
+#define IFX_SMU_AG_SF13_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF13 */
+#define IFX_SMU_AG_SF13_OFF (13u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF14 */
+#define IFX_SMU_AG_SF14_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF14 */
+#define IFX_SMU_AG_SF14_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF14 */
+#define IFX_SMU_AG_SF14_OFF (14u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF15 */
+#define IFX_SMU_AG_SF15_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF15 */
+#define IFX_SMU_AG_SF15_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF15 */
+#define IFX_SMU_AG_SF15_OFF (15u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF16 */
+#define IFX_SMU_AG_SF16_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF16 */
+#define IFX_SMU_AG_SF16_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF16 */
+#define IFX_SMU_AG_SF16_OFF (16u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF17 */
+#define IFX_SMU_AG_SF17_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF17 */
+#define IFX_SMU_AG_SF17_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF17 */
+#define IFX_SMU_AG_SF17_OFF (17u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF18 */
+#define IFX_SMU_AG_SF18_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF18 */
+#define IFX_SMU_AG_SF18_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF18 */
+#define IFX_SMU_AG_SF18_OFF (18u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF19 */
+#define IFX_SMU_AG_SF19_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF19 */
+#define IFX_SMU_AG_SF19_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF19 */
+#define IFX_SMU_AG_SF19_OFF (19u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF1 */
+#define IFX_SMU_AG_SF1_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF1 */
+#define IFX_SMU_AG_SF1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF1 */
+#define IFX_SMU_AG_SF1_OFF (1u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF20 */
+#define IFX_SMU_AG_SF20_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF20 */
+#define IFX_SMU_AG_SF20_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF20 */
+#define IFX_SMU_AG_SF20_OFF (20u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF21 */
+#define IFX_SMU_AG_SF21_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF21 */
+#define IFX_SMU_AG_SF21_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF21 */
+#define IFX_SMU_AG_SF21_OFF (21u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF22 */
+#define IFX_SMU_AG_SF22_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF22 */
+#define IFX_SMU_AG_SF22_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF22 */
+#define IFX_SMU_AG_SF22_OFF (22u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF23 */
+#define IFX_SMU_AG_SF23_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF23 */
+#define IFX_SMU_AG_SF23_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF23 */
+#define IFX_SMU_AG_SF23_OFF (23u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF24 */
+#define IFX_SMU_AG_SF24_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF24 */
+#define IFX_SMU_AG_SF24_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF24 */
+#define IFX_SMU_AG_SF24_OFF (24u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF25 */
+#define IFX_SMU_AG_SF25_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF25 */
+#define IFX_SMU_AG_SF25_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF25 */
+#define IFX_SMU_AG_SF25_OFF (25u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF26 */
+#define IFX_SMU_AG_SF26_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF26 */
+#define IFX_SMU_AG_SF26_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF26 */
+#define IFX_SMU_AG_SF26_OFF (26u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF27 */
+#define IFX_SMU_AG_SF27_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF27 */
+#define IFX_SMU_AG_SF27_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF27 */
+#define IFX_SMU_AG_SF27_OFF (27u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF28 */
+#define IFX_SMU_AG_SF28_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF28 */
+#define IFX_SMU_AG_SF28_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF28 */
+#define IFX_SMU_AG_SF28_OFF (28u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF29 */
+#define IFX_SMU_AG_SF29_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF29 */
+#define IFX_SMU_AG_SF29_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF29 */
+#define IFX_SMU_AG_SF29_OFF (29u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF2 */
+#define IFX_SMU_AG_SF2_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF2 */
+#define IFX_SMU_AG_SF2_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF2 */
+#define IFX_SMU_AG_SF2_OFF (2u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF30 */
+#define IFX_SMU_AG_SF30_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF30 */
+#define IFX_SMU_AG_SF30_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF30 */
+#define IFX_SMU_AG_SF30_OFF (30u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF31 */
+#define IFX_SMU_AG_SF31_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF31 */
+#define IFX_SMU_AG_SF31_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF31 */
+#define IFX_SMU_AG_SF31_OFF (31u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF3 */
+#define IFX_SMU_AG_SF3_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF3 */
+#define IFX_SMU_AG_SF3_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF3 */
+#define IFX_SMU_AG_SF3_OFF (3u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF4 */
+#define IFX_SMU_AG_SF4_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF4 */
+#define IFX_SMU_AG_SF4_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF4 */
+#define IFX_SMU_AG_SF4_OFF (4u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF5 */
+#define IFX_SMU_AG_SF5_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF5 */
+#define IFX_SMU_AG_SF5_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF5 */
+#define IFX_SMU_AG_SF5_OFF (5u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF6 */
+#define IFX_SMU_AG_SF6_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF6 */
+#define IFX_SMU_AG_SF6_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF6 */
+#define IFX_SMU_AG_SF6_OFF (6u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF7 */
+#define IFX_SMU_AG_SF7_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF7 */
+#define IFX_SMU_AG_SF7_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF7 */
+#define IFX_SMU_AG_SF7_OFF (7u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF8 */
+#define IFX_SMU_AG_SF8_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF8 */
+#define IFX_SMU_AG_SF8_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF8 */
+#define IFX_SMU_AG_SF8_OFF (8u)
+
+/** \brief Length for Ifx_SMU_AG_Bits.SF9 */
+#define IFX_SMU_AG_SF9_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AG_Bits.SF9 */
+#define IFX_SMU_AG_SF9_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AG_Bits.SF9 */
+#define IFX_SMU_AG_SF9_OFF (9u)
+
+/** \brief Length for Ifx_SMU_AGC_Bits.EFRST */
+#define IFX_SMU_AGC_EFRST_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGC_Bits.EFRST */
+#define IFX_SMU_AGC_EFRST_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGC_Bits.EFRST */
+#define IFX_SMU_AGC_EFRST_OFF (29u)
+
+/** \brief Length for Ifx_SMU_AGC_Bits.ICS */
+#define IFX_SMU_AGC_ICS_LEN (3u)
+
+/** \brief Mask for Ifx_SMU_AGC_Bits.ICS */
+#define IFX_SMU_AGC_ICS_MSK (0x7u)
+
+/** \brief Offset for Ifx_SMU_AGC_Bits.ICS */
+#define IFX_SMU_AGC_ICS_OFF (16u)
+
+/** \brief Length for Ifx_SMU_AGC_Bits.IGCS0 */
+#define IFX_SMU_AGC_IGCS0_LEN (3u)
+
+/** \brief Mask for Ifx_SMU_AGC_Bits.IGCS0 */
+#define IFX_SMU_AGC_IGCS0_MSK (0x7u)
+
+/** \brief Offset for Ifx_SMU_AGC_Bits.IGCS0 */
+#define IFX_SMU_AGC_IGCS0_OFF (0u)
+
+/** \brief Length for Ifx_SMU_AGC_Bits.IGCS1 */
+#define IFX_SMU_AGC_IGCS1_LEN (3u)
+
+/** \brief Mask for Ifx_SMU_AGC_Bits.IGCS1 */
+#define IFX_SMU_AGC_IGCS1_MSK (0x7u)
+
+/** \brief Offset for Ifx_SMU_AGC_Bits.IGCS1 */
+#define IFX_SMU_AGC_IGCS1_OFF (4u)
+
+/** \brief Length for Ifx_SMU_AGC_Bits.IGCS2 */
+#define IFX_SMU_AGC_IGCS2_LEN (3u)
+
+/** \brief Mask for Ifx_SMU_AGC_Bits.IGCS2 */
+#define IFX_SMU_AGC_IGCS2_MSK (0x7u)
+
+/** \brief Offset for Ifx_SMU_AGC_Bits.IGCS2 */
+#define IFX_SMU_AGC_IGCS2_OFF (8u)
+
+/** \brief Length for Ifx_SMU_AGC_Bits.PES */
+#define IFX_SMU_AGC_PES_LEN (5u)
+
+/** \brief Mask for Ifx_SMU_AGC_Bits.PES */
+#define IFX_SMU_AGC_PES_MSK (0x1fu)
+
+/** \brief Offset for Ifx_SMU_AGC_Bits.PES */
+#define IFX_SMU_AGC_PES_OFF (24u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF0 */
+#define IFX_SMU_AGCF_CF0_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF0 */
+#define IFX_SMU_AGCF_CF0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF0 */
+#define IFX_SMU_AGCF_CF0_OFF (0u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF10 */
+#define IFX_SMU_AGCF_CF10_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF10 */
+#define IFX_SMU_AGCF_CF10_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF10 */
+#define IFX_SMU_AGCF_CF10_OFF (10u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF11 */
+#define IFX_SMU_AGCF_CF11_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF11 */
+#define IFX_SMU_AGCF_CF11_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF11 */
+#define IFX_SMU_AGCF_CF11_OFF (11u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF12 */
+#define IFX_SMU_AGCF_CF12_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF12 */
+#define IFX_SMU_AGCF_CF12_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF12 */
+#define IFX_SMU_AGCF_CF12_OFF (12u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF13 */
+#define IFX_SMU_AGCF_CF13_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF13 */
+#define IFX_SMU_AGCF_CF13_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF13 */
+#define IFX_SMU_AGCF_CF13_OFF (13u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF14 */
+#define IFX_SMU_AGCF_CF14_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF14 */
+#define IFX_SMU_AGCF_CF14_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF14 */
+#define IFX_SMU_AGCF_CF14_OFF (14u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF15 */
+#define IFX_SMU_AGCF_CF15_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF15 */
+#define IFX_SMU_AGCF_CF15_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF15 */
+#define IFX_SMU_AGCF_CF15_OFF (15u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF16 */
+#define IFX_SMU_AGCF_CF16_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF16 */
+#define IFX_SMU_AGCF_CF16_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF16 */
+#define IFX_SMU_AGCF_CF16_OFF (16u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF17 */
+#define IFX_SMU_AGCF_CF17_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF17 */
+#define IFX_SMU_AGCF_CF17_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF17 */
+#define IFX_SMU_AGCF_CF17_OFF (17u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF18 */
+#define IFX_SMU_AGCF_CF18_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF18 */
+#define IFX_SMU_AGCF_CF18_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF18 */
+#define IFX_SMU_AGCF_CF18_OFF (18u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF19 */
+#define IFX_SMU_AGCF_CF19_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF19 */
+#define IFX_SMU_AGCF_CF19_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF19 */
+#define IFX_SMU_AGCF_CF19_OFF (19u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF1 */
+#define IFX_SMU_AGCF_CF1_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF1 */
+#define IFX_SMU_AGCF_CF1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF1 */
+#define IFX_SMU_AGCF_CF1_OFF (1u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF20 */
+#define IFX_SMU_AGCF_CF20_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF20 */
+#define IFX_SMU_AGCF_CF20_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF20 */
+#define IFX_SMU_AGCF_CF20_OFF (20u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF21 */
+#define IFX_SMU_AGCF_CF21_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF21 */
+#define IFX_SMU_AGCF_CF21_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF21 */
+#define IFX_SMU_AGCF_CF21_OFF (21u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF22 */
+#define IFX_SMU_AGCF_CF22_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF22 */
+#define IFX_SMU_AGCF_CF22_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF22 */
+#define IFX_SMU_AGCF_CF22_OFF (22u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF23 */
+#define IFX_SMU_AGCF_CF23_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF23 */
+#define IFX_SMU_AGCF_CF23_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF23 */
+#define IFX_SMU_AGCF_CF23_OFF (23u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF24 */
+#define IFX_SMU_AGCF_CF24_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF24 */
+#define IFX_SMU_AGCF_CF24_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF24 */
+#define IFX_SMU_AGCF_CF24_OFF (24u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF25 */
+#define IFX_SMU_AGCF_CF25_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF25 */
+#define IFX_SMU_AGCF_CF25_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF25 */
+#define IFX_SMU_AGCF_CF25_OFF (25u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF26 */
+#define IFX_SMU_AGCF_CF26_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF26 */
+#define IFX_SMU_AGCF_CF26_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF26 */
+#define IFX_SMU_AGCF_CF26_OFF (26u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF27 */
+#define IFX_SMU_AGCF_CF27_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF27 */
+#define IFX_SMU_AGCF_CF27_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF27 */
+#define IFX_SMU_AGCF_CF27_OFF (27u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF28 */
+#define IFX_SMU_AGCF_CF28_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF28 */
+#define IFX_SMU_AGCF_CF28_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF28 */
+#define IFX_SMU_AGCF_CF28_OFF (28u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF29 */
+#define IFX_SMU_AGCF_CF29_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF29 */
+#define IFX_SMU_AGCF_CF29_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF29 */
+#define IFX_SMU_AGCF_CF29_OFF (29u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF2 */
+#define IFX_SMU_AGCF_CF2_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF2 */
+#define IFX_SMU_AGCF_CF2_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF2 */
+#define IFX_SMU_AGCF_CF2_OFF (2u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF30 */
+#define IFX_SMU_AGCF_CF30_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF30 */
+#define IFX_SMU_AGCF_CF30_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF30 */
+#define IFX_SMU_AGCF_CF30_OFF (30u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF31 */
+#define IFX_SMU_AGCF_CF31_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF31 */
+#define IFX_SMU_AGCF_CF31_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF31 */
+#define IFX_SMU_AGCF_CF31_OFF (31u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF3 */
+#define IFX_SMU_AGCF_CF3_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF3 */
+#define IFX_SMU_AGCF_CF3_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF3 */
+#define IFX_SMU_AGCF_CF3_OFF (3u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF4 */
+#define IFX_SMU_AGCF_CF4_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF4 */
+#define IFX_SMU_AGCF_CF4_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF4 */
+#define IFX_SMU_AGCF_CF4_OFF (4u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF5 */
+#define IFX_SMU_AGCF_CF5_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF5 */
+#define IFX_SMU_AGCF_CF5_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF5 */
+#define IFX_SMU_AGCF_CF5_OFF (5u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF6 */
+#define IFX_SMU_AGCF_CF6_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF6 */
+#define IFX_SMU_AGCF_CF6_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF6 */
+#define IFX_SMU_AGCF_CF6_OFF (6u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF7 */
+#define IFX_SMU_AGCF_CF7_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF7 */
+#define IFX_SMU_AGCF_CF7_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF7 */
+#define IFX_SMU_AGCF_CF7_OFF (7u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF8 */
+#define IFX_SMU_AGCF_CF8_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF8 */
+#define IFX_SMU_AGCF_CF8_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF8 */
+#define IFX_SMU_AGCF_CF8_OFF (8u)
+
+/** \brief Length for Ifx_SMU_AGCF_Bits.CF9 */
+#define IFX_SMU_AGCF_CF9_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGCF_Bits.CF9 */
+#define IFX_SMU_AGCF_CF9_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGCF_Bits.CF9 */
+#define IFX_SMU_AGCF_CF9_OFF (9u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE0 */
+#define IFX_SMU_AGFSP_FE0_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE0 */
+#define IFX_SMU_AGFSP_FE0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE0 */
+#define IFX_SMU_AGFSP_FE0_OFF (0u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE10 */
+#define IFX_SMU_AGFSP_FE10_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE10 */
+#define IFX_SMU_AGFSP_FE10_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE10 */
+#define IFX_SMU_AGFSP_FE10_OFF (10u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE11 */
+#define IFX_SMU_AGFSP_FE11_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE11 */
+#define IFX_SMU_AGFSP_FE11_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE11 */
+#define IFX_SMU_AGFSP_FE11_OFF (11u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE12 */
+#define IFX_SMU_AGFSP_FE12_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE12 */
+#define IFX_SMU_AGFSP_FE12_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE12 */
+#define IFX_SMU_AGFSP_FE12_OFF (12u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE13 */
+#define IFX_SMU_AGFSP_FE13_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE13 */
+#define IFX_SMU_AGFSP_FE13_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE13 */
+#define IFX_SMU_AGFSP_FE13_OFF (13u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE14 */
+#define IFX_SMU_AGFSP_FE14_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE14 */
+#define IFX_SMU_AGFSP_FE14_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE14 */
+#define IFX_SMU_AGFSP_FE14_OFF (14u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE15 */
+#define IFX_SMU_AGFSP_FE15_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE15 */
+#define IFX_SMU_AGFSP_FE15_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE15 */
+#define IFX_SMU_AGFSP_FE15_OFF (15u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE16 */
+#define IFX_SMU_AGFSP_FE16_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE16 */
+#define IFX_SMU_AGFSP_FE16_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE16 */
+#define IFX_SMU_AGFSP_FE16_OFF (16u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE17 */
+#define IFX_SMU_AGFSP_FE17_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE17 */
+#define IFX_SMU_AGFSP_FE17_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE17 */
+#define IFX_SMU_AGFSP_FE17_OFF (17u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE18 */
+#define IFX_SMU_AGFSP_FE18_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE18 */
+#define IFX_SMU_AGFSP_FE18_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE18 */
+#define IFX_SMU_AGFSP_FE18_OFF (18u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE19 */
+#define IFX_SMU_AGFSP_FE19_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE19 */
+#define IFX_SMU_AGFSP_FE19_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE19 */
+#define IFX_SMU_AGFSP_FE19_OFF (19u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE1 */
+#define IFX_SMU_AGFSP_FE1_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE1 */
+#define IFX_SMU_AGFSP_FE1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE1 */
+#define IFX_SMU_AGFSP_FE1_OFF (1u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE20 */
+#define IFX_SMU_AGFSP_FE20_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE20 */
+#define IFX_SMU_AGFSP_FE20_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE20 */
+#define IFX_SMU_AGFSP_FE20_OFF (20u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE21 */
+#define IFX_SMU_AGFSP_FE21_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE21 */
+#define IFX_SMU_AGFSP_FE21_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE21 */
+#define IFX_SMU_AGFSP_FE21_OFF (21u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE22 */
+#define IFX_SMU_AGFSP_FE22_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE22 */
+#define IFX_SMU_AGFSP_FE22_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE22 */
+#define IFX_SMU_AGFSP_FE22_OFF (22u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE23 */
+#define IFX_SMU_AGFSP_FE23_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE23 */
+#define IFX_SMU_AGFSP_FE23_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE23 */
+#define IFX_SMU_AGFSP_FE23_OFF (23u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE24 */
+#define IFX_SMU_AGFSP_FE24_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE24 */
+#define IFX_SMU_AGFSP_FE24_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE24 */
+#define IFX_SMU_AGFSP_FE24_OFF (24u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE25 */
+#define IFX_SMU_AGFSP_FE25_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE25 */
+#define IFX_SMU_AGFSP_FE25_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE25 */
+#define IFX_SMU_AGFSP_FE25_OFF (25u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE26 */
+#define IFX_SMU_AGFSP_FE26_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE26 */
+#define IFX_SMU_AGFSP_FE26_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE26 */
+#define IFX_SMU_AGFSP_FE26_OFF (26u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE27 */
+#define IFX_SMU_AGFSP_FE27_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE27 */
+#define IFX_SMU_AGFSP_FE27_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE27 */
+#define IFX_SMU_AGFSP_FE27_OFF (27u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE28 */
+#define IFX_SMU_AGFSP_FE28_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE28 */
+#define IFX_SMU_AGFSP_FE28_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE28 */
+#define IFX_SMU_AGFSP_FE28_OFF (28u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE29 */
+#define IFX_SMU_AGFSP_FE29_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE29 */
+#define IFX_SMU_AGFSP_FE29_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE29 */
+#define IFX_SMU_AGFSP_FE29_OFF (29u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE2 */
+#define IFX_SMU_AGFSP_FE2_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE2 */
+#define IFX_SMU_AGFSP_FE2_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE2 */
+#define IFX_SMU_AGFSP_FE2_OFF (2u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE30 */
+#define IFX_SMU_AGFSP_FE30_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE30 */
+#define IFX_SMU_AGFSP_FE30_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE30 */
+#define IFX_SMU_AGFSP_FE30_OFF (30u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE31 */
+#define IFX_SMU_AGFSP_FE31_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE31 */
+#define IFX_SMU_AGFSP_FE31_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE31 */
+#define IFX_SMU_AGFSP_FE31_OFF (31u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE3 */
+#define IFX_SMU_AGFSP_FE3_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE3 */
+#define IFX_SMU_AGFSP_FE3_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE3 */
+#define IFX_SMU_AGFSP_FE3_OFF (3u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE4 */
+#define IFX_SMU_AGFSP_FE4_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE4 */
+#define IFX_SMU_AGFSP_FE4_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE4 */
+#define IFX_SMU_AGFSP_FE4_OFF (4u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE5 */
+#define IFX_SMU_AGFSP_FE5_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE5 */
+#define IFX_SMU_AGFSP_FE5_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE5 */
+#define IFX_SMU_AGFSP_FE5_OFF (5u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE6 */
+#define IFX_SMU_AGFSP_FE6_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE6 */
+#define IFX_SMU_AGFSP_FE6_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE6 */
+#define IFX_SMU_AGFSP_FE6_OFF (6u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE7 */
+#define IFX_SMU_AGFSP_FE7_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE7 */
+#define IFX_SMU_AGFSP_FE7_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE7 */
+#define IFX_SMU_AGFSP_FE7_OFF (7u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE8 */
+#define IFX_SMU_AGFSP_FE8_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE8 */
+#define IFX_SMU_AGFSP_FE8_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE8 */
+#define IFX_SMU_AGFSP_FE8_OFF (8u)
+
+/** \brief Length for Ifx_SMU_AGFSP_Bits.FE9 */
+#define IFX_SMU_AGFSP_FE9_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_AGFSP_Bits.FE9 */
+#define IFX_SMU_AGFSP_FE9_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_AGFSP_Bits.FE9 */
+#define IFX_SMU_AGFSP_FE9_OFF (9u)
+
+/** \brief Length for Ifx_SMU_CLC_Bits.DISR */
+#define IFX_SMU_CLC_DISR_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_CLC_Bits.DISR */
+#define IFX_SMU_CLC_DISR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_CLC_Bits.DISR */
+#define IFX_SMU_CLC_DISR_OFF (0u)
+
+/** \brief Length for Ifx_SMU_CLC_Bits.DISS */
+#define IFX_SMU_CLC_DISS_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_CLC_Bits.DISS */
+#define IFX_SMU_CLC_DISS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_CLC_Bits.DISS */
+#define IFX_SMU_CLC_DISS_OFF (1u)
+
+/** \brief Length for Ifx_SMU_CLC_Bits.EDIS */
+#define IFX_SMU_CLC_EDIS_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_CLC_Bits.EDIS */
+#define IFX_SMU_CLC_EDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_CLC_Bits.EDIS */
+#define IFX_SMU_CLC_EDIS_OFF (3u)
+
+/** \brief Length for Ifx_SMU_CLC_Bits.FDIS */
+#define IFX_SMU_CLC_FDIS_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_CLC_Bits.FDIS */
+#define IFX_SMU_CLC_FDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_CLC_Bits.FDIS */
+#define IFX_SMU_CLC_FDIS_OFF (2u)
+
+/** \brief Length for Ifx_SMU_CMD_Bits.ARG */
+#define IFX_SMU_CMD_ARG_LEN (4u)
+
+/** \brief Mask for Ifx_SMU_CMD_Bits.ARG */
+#define IFX_SMU_CMD_ARG_MSK (0xfu)
+
+/** \brief Offset for Ifx_SMU_CMD_Bits.ARG */
+#define IFX_SMU_CMD_ARG_OFF (4u)
+
+/** \brief Length for Ifx_SMU_CMD_Bits.CMD */
+#define IFX_SMU_CMD_CMD_LEN (4u)
+
+/** \brief Mask for Ifx_SMU_CMD_Bits.CMD */
+#define IFX_SMU_CMD_CMD_MSK (0xfu)
+
+/** \brief Offset for Ifx_SMU_CMD_Bits.CMD */
+#define IFX_SMU_CMD_CMD_OFF (0u)
+
+/** \brief Length for Ifx_SMU_DBG_Bits.SSM */
+#define IFX_SMU_DBG_SSM_LEN (2u)
+
+/** \brief Mask for Ifx_SMU_DBG_Bits.SSM */
+#define IFX_SMU_DBG_SSM_MSK (0x3u)
+
+/** \brief Offset for Ifx_SMU_DBG_Bits.SSM */
+#define IFX_SMU_DBG_SSM_OFF (0u)
+
+/** \brief Length for Ifx_SMU_FSP_Bits.MODE */
+#define IFX_SMU_FSP_MODE_LEN (2u)
+
+/** \brief Mask for Ifx_SMU_FSP_Bits.MODE */
+#define IFX_SMU_FSP_MODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_SMU_FSP_Bits.MODE */
+#define IFX_SMU_FSP_MODE_OFF (5u)
+
+/** \brief Length for Ifx_SMU_FSP_Bits.PES */
+#define IFX_SMU_FSP_PES_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_FSP_Bits.PES */
+#define IFX_SMU_FSP_PES_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_FSP_Bits.PES */
+#define IFX_SMU_FSP_PES_OFF (7u)
+
+/** \brief Length for Ifx_SMU_FSP_Bits.PRE1 */
+#define IFX_SMU_FSP_PRE1_LEN (3u)
+
+/** \brief Mask for Ifx_SMU_FSP_Bits.PRE1 */
+#define IFX_SMU_FSP_PRE1_MSK (0x7u)
+
+/** \brief Offset for Ifx_SMU_FSP_Bits.PRE1 */
+#define IFX_SMU_FSP_PRE1_OFF (0u)
+
+/** \brief Length for Ifx_SMU_FSP_Bits.PRE2 */
+#define IFX_SMU_FSP_PRE2_LEN (2u)
+
+/** \brief Mask for Ifx_SMU_FSP_Bits.PRE2 */
+#define IFX_SMU_FSP_PRE2_MSK (0x3u)
+
+/** \brief Offset for Ifx_SMU_FSP_Bits.PRE2 */
+#define IFX_SMU_FSP_PRE2_OFF (3u)
+
+/** \brief Length for Ifx_SMU_FSP_Bits.TFSP_HIGH */
+#define IFX_SMU_FSP_TFSP_HIGH_LEN (10u)
+
+/** \brief Mask for Ifx_SMU_FSP_Bits.TFSP_HIGH */
+#define IFX_SMU_FSP_TFSP_HIGH_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_SMU_FSP_Bits.TFSP_HIGH */
+#define IFX_SMU_FSP_TFSP_HIGH_OFF (22u)
+
+/** \brief Length for Ifx_SMU_FSP_Bits.TFSP_LOW */
+#define IFX_SMU_FSP_TFSP_LOW_LEN (14u)
+
+/** \brief Mask for Ifx_SMU_FSP_Bits.TFSP_LOW */
+#define IFX_SMU_FSP_TFSP_LOW_MSK (0x3fffu)
+
+/** \brief Offset for Ifx_SMU_FSP_Bits.TFSP_LOW */
+#define IFX_SMU_FSP_TFSP_LOW_OFF (8u)
+
+/** \brief Length for Ifx_SMU_ID_Bits.MODNUMBER */
+#define IFX_SMU_ID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_SMU_ID_Bits.MODNUMBER */
+#define IFX_SMU_ID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_SMU_ID_Bits.MODNUMBER */
+#define IFX_SMU_ID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_SMU_ID_Bits.MODREV */
+#define IFX_SMU_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_SMU_ID_Bits.MODREV */
+#define IFX_SMU_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_SMU_ID_Bits.MODREV */
+#define IFX_SMU_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_SMU_ID_Bits.MODTYPE */
+#define IFX_SMU_ID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_SMU_ID_Bits.MODTYPE */
+#define IFX_SMU_ID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_SMU_ID_Bits.MODTYPE */
+#define IFX_SMU_ID_MODTYPE_OFF (8u)
+
+/** \brief Length for Ifx_SMU_KEYS_Bits.CFGLCK */
+#define IFX_SMU_KEYS_CFGLCK_LEN (8u)
+
+/** \brief Mask for Ifx_SMU_KEYS_Bits.CFGLCK */
+#define IFX_SMU_KEYS_CFGLCK_MSK (0xffu)
+
+/** \brief Offset for Ifx_SMU_KEYS_Bits.CFGLCK */
+#define IFX_SMU_KEYS_CFGLCK_OFF (0u)
+
+/** \brief Length for Ifx_SMU_KEYS_Bits.PERLCK */
+#define IFX_SMU_KEYS_PERLCK_LEN (8u)
+
+/** \brief Mask for Ifx_SMU_KEYS_Bits.PERLCK */
+#define IFX_SMU_KEYS_PERLCK_MSK (0xffu)
+
+/** \brief Offset for Ifx_SMU_KEYS_Bits.PERLCK */
+#define IFX_SMU_KEYS_PERLCK_OFF (8u)
+
+/** \brief Length for Ifx_SMU_KRST0_Bits.RST */
+#define IFX_SMU_KRST0_RST_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_KRST0_Bits.RST */
+#define IFX_SMU_KRST0_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_KRST0_Bits.RST */
+#define IFX_SMU_KRST0_RST_OFF (0u)
+
+/** \brief Length for Ifx_SMU_KRST0_Bits.RSTSTAT */
+#define IFX_SMU_KRST0_RSTSTAT_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_KRST0_Bits.RSTSTAT */
+#define IFX_SMU_KRST0_RSTSTAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_KRST0_Bits.RSTSTAT */
+#define IFX_SMU_KRST0_RSTSTAT_OFF (1u)
+
+/** \brief Length for Ifx_SMU_KRST1_Bits.RST */
+#define IFX_SMU_KRST1_RST_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_KRST1_Bits.RST */
+#define IFX_SMU_KRST1_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_KRST1_Bits.RST */
+#define IFX_SMU_KRST1_RST_OFF (0u)
+
+/** \brief Length for Ifx_SMU_KRSTCLR_Bits.CLR */
+#define IFX_SMU_KRSTCLR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_KRSTCLR_Bits.CLR */
+#define IFX_SMU_KRSTCLR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_KRSTCLR_Bits.CLR */
+#define IFX_SMU_KRSTCLR_CLR_OFF (0u)
+
+/** \brief Length for Ifx_SMU_OCS_Bits.SUS */
+#define IFX_SMU_OCS_SUS_LEN (4u)
+
+/** \brief Mask for Ifx_SMU_OCS_Bits.SUS */
+#define IFX_SMU_OCS_SUS_MSK (0xfu)
+
+/** \brief Offset for Ifx_SMU_OCS_Bits.SUS */
+#define IFX_SMU_OCS_SUS_OFF (24u)
+
+/** \brief Length for Ifx_SMU_OCS_Bits.SUS_P */
+#define IFX_SMU_OCS_SUS_P_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_OCS_Bits.SUS_P */
+#define IFX_SMU_OCS_SUS_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_OCS_Bits.SUS_P */
+#define IFX_SMU_OCS_SUS_P_OFF (28u)
+
+/** \brief Length for Ifx_SMU_OCS_Bits.SUSSTA */
+#define IFX_SMU_OCS_SUSSTA_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_OCS_Bits.SUSSTA */
+#define IFX_SMU_OCS_SUSSTA_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_OCS_Bits.SUSSTA */
+#define IFX_SMU_OCS_SUSSTA_OFF (29u)
+
+/** \brief Length for Ifx_SMU_OCS_Bits.TG_P */
+#define IFX_SMU_OCS_TG_P_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_OCS_Bits.TG_P */
+#define IFX_SMU_OCS_TG_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_OCS_Bits.TG_P */
+#define IFX_SMU_OCS_TG_P_OFF (3u)
+
+/** \brief Length for Ifx_SMU_OCS_Bits.TGB */
+#define IFX_SMU_OCS_TGB_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_OCS_Bits.TGB */
+#define IFX_SMU_OCS_TGB_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_OCS_Bits.TGB */
+#define IFX_SMU_OCS_TGB_OFF (2u)
+
+/** \brief Length for Ifx_SMU_OCS_Bits.TGS */
+#define IFX_SMU_OCS_TGS_LEN (2u)
+
+/** \brief Mask for Ifx_SMU_OCS_Bits.TGS */
+#define IFX_SMU_OCS_TGS_MSK (0x3u)
+
+/** \brief Offset for Ifx_SMU_OCS_Bits.TGS */
+#define IFX_SMU_OCS_TGS_OFF (0u)
+
+/** \brief Length for Ifx_SMU_PCTL_Bits.HWDIR */
+#define IFX_SMU_PCTL_HWDIR_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_PCTL_Bits.HWDIR */
+#define IFX_SMU_PCTL_HWDIR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_PCTL_Bits.HWDIR */
+#define IFX_SMU_PCTL_HWDIR_OFF (0u)
+
+/** \brief Length for Ifx_SMU_PCTL_Bits.HWEN */
+#define IFX_SMU_PCTL_HWEN_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_PCTL_Bits.HWEN */
+#define IFX_SMU_PCTL_HWEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_PCTL_Bits.HWEN */
+#define IFX_SMU_PCTL_HWEN_OFF (1u)
+
+/** \brief Length for Ifx_SMU_PCTL_Bits.PCFG */
+#define IFX_SMU_PCTL_PCFG_LEN (16u)
+
+/** \brief Mask for Ifx_SMU_PCTL_Bits.PCFG */
+#define IFX_SMU_PCTL_PCFG_MSK (0xffffu)
+
+/** \brief Offset for Ifx_SMU_PCTL_Bits.PCFG */
+#define IFX_SMU_PCTL_PCFG_OFF (16u)
+
+/** \brief Length for Ifx_SMU_PCTL_Bits.PCS */
+#define IFX_SMU_PCTL_PCS_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_PCTL_Bits.PCS */
+#define IFX_SMU_PCTL_PCS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_PCTL_Bits.PCS */
+#define IFX_SMU_PCTL_PCS_OFF (7u)
+
+/** \brief Length for Ifx_SMU_RMCTL_Bits.TE */
+#define IFX_SMU_RMCTL_TE_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMCTL_Bits.TE */
+#define IFX_SMU_RMCTL_TE_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMCTL_Bits.TE */
+#define IFX_SMU_RMCTL_TE_OFF (0u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF0 */
+#define IFX_SMU_RMEF_EF0_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF0 */
+#define IFX_SMU_RMEF_EF0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF0 */
+#define IFX_SMU_RMEF_EF0_OFF (0u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF10 */
+#define IFX_SMU_RMEF_EF10_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF10 */
+#define IFX_SMU_RMEF_EF10_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF10 */
+#define IFX_SMU_RMEF_EF10_OFF (10u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF11 */
+#define IFX_SMU_RMEF_EF11_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF11 */
+#define IFX_SMU_RMEF_EF11_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF11 */
+#define IFX_SMU_RMEF_EF11_OFF (11u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF12 */
+#define IFX_SMU_RMEF_EF12_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF12 */
+#define IFX_SMU_RMEF_EF12_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF12 */
+#define IFX_SMU_RMEF_EF12_OFF (12u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF13 */
+#define IFX_SMU_RMEF_EF13_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF13 */
+#define IFX_SMU_RMEF_EF13_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF13 */
+#define IFX_SMU_RMEF_EF13_OFF (13u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF14 */
+#define IFX_SMU_RMEF_EF14_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF14 */
+#define IFX_SMU_RMEF_EF14_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF14 */
+#define IFX_SMU_RMEF_EF14_OFF (14u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF15 */
+#define IFX_SMU_RMEF_EF15_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF15 */
+#define IFX_SMU_RMEF_EF15_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF15 */
+#define IFX_SMU_RMEF_EF15_OFF (15u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF16 */
+#define IFX_SMU_RMEF_EF16_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF16 */
+#define IFX_SMU_RMEF_EF16_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF16 */
+#define IFX_SMU_RMEF_EF16_OFF (16u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF17 */
+#define IFX_SMU_RMEF_EF17_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF17 */
+#define IFX_SMU_RMEF_EF17_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF17 */
+#define IFX_SMU_RMEF_EF17_OFF (17u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF18 */
+#define IFX_SMU_RMEF_EF18_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF18 */
+#define IFX_SMU_RMEF_EF18_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF18 */
+#define IFX_SMU_RMEF_EF18_OFF (18u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF19 */
+#define IFX_SMU_RMEF_EF19_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF19 */
+#define IFX_SMU_RMEF_EF19_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF19 */
+#define IFX_SMU_RMEF_EF19_OFF (19u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF1 */
+#define IFX_SMU_RMEF_EF1_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF1 */
+#define IFX_SMU_RMEF_EF1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF1 */
+#define IFX_SMU_RMEF_EF1_OFF (1u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF20 */
+#define IFX_SMU_RMEF_EF20_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF20 */
+#define IFX_SMU_RMEF_EF20_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF20 */
+#define IFX_SMU_RMEF_EF20_OFF (20u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF21 */
+#define IFX_SMU_RMEF_EF21_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF21 */
+#define IFX_SMU_RMEF_EF21_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF21 */
+#define IFX_SMU_RMEF_EF21_OFF (21u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF22 */
+#define IFX_SMU_RMEF_EF22_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF22 */
+#define IFX_SMU_RMEF_EF22_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF22 */
+#define IFX_SMU_RMEF_EF22_OFF (22u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF23 */
+#define IFX_SMU_RMEF_EF23_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF23 */
+#define IFX_SMU_RMEF_EF23_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF23 */
+#define IFX_SMU_RMEF_EF23_OFF (23u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF24 */
+#define IFX_SMU_RMEF_EF24_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF24 */
+#define IFX_SMU_RMEF_EF24_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF24 */
+#define IFX_SMU_RMEF_EF24_OFF (24u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF25 */
+#define IFX_SMU_RMEF_EF25_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF25 */
+#define IFX_SMU_RMEF_EF25_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF25 */
+#define IFX_SMU_RMEF_EF25_OFF (25u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF26 */
+#define IFX_SMU_RMEF_EF26_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF26 */
+#define IFX_SMU_RMEF_EF26_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF26 */
+#define IFX_SMU_RMEF_EF26_OFF (26u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF27 */
+#define IFX_SMU_RMEF_EF27_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF27 */
+#define IFX_SMU_RMEF_EF27_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF27 */
+#define IFX_SMU_RMEF_EF27_OFF (27u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF28 */
+#define IFX_SMU_RMEF_EF28_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF28 */
+#define IFX_SMU_RMEF_EF28_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF28 */
+#define IFX_SMU_RMEF_EF28_OFF (28u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF29 */
+#define IFX_SMU_RMEF_EF29_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF29 */
+#define IFX_SMU_RMEF_EF29_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF29 */
+#define IFX_SMU_RMEF_EF29_OFF (29u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF2 */
+#define IFX_SMU_RMEF_EF2_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF2 */
+#define IFX_SMU_RMEF_EF2_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF2 */
+#define IFX_SMU_RMEF_EF2_OFF (2u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF30 */
+#define IFX_SMU_RMEF_EF30_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF30 */
+#define IFX_SMU_RMEF_EF30_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF30 */
+#define IFX_SMU_RMEF_EF30_OFF (30u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF31 */
+#define IFX_SMU_RMEF_EF31_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF31 */
+#define IFX_SMU_RMEF_EF31_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF31 */
+#define IFX_SMU_RMEF_EF31_OFF (31u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF3 */
+#define IFX_SMU_RMEF_EF3_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF3 */
+#define IFX_SMU_RMEF_EF3_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF3 */
+#define IFX_SMU_RMEF_EF3_OFF (3u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF4 */
+#define IFX_SMU_RMEF_EF4_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF4 */
+#define IFX_SMU_RMEF_EF4_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF4 */
+#define IFX_SMU_RMEF_EF4_OFF (4u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF5 */
+#define IFX_SMU_RMEF_EF5_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF5 */
+#define IFX_SMU_RMEF_EF5_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF5 */
+#define IFX_SMU_RMEF_EF5_OFF (5u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF6 */
+#define IFX_SMU_RMEF_EF6_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF6 */
+#define IFX_SMU_RMEF_EF6_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF6 */
+#define IFX_SMU_RMEF_EF6_OFF (6u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF7 */
+#define IFX_SMU_RMEF_EF7_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF7 */
+#define IFX_SMU_RMEF_EF7_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF7 */
+#define IFX_SMU_RMEF_EF7_OFF (7u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF8 */
+#define IFX_SMU_RMEF_EF8_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF8 */
+#define IFX_SMU_RMEF_EF8_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF8 */
+#define IFX_SMU_RMEF_EF8_OFF (8u)
+
+/** \brief Length for Ifx_SMU_RMEF_Bits.EF9 */
+#define IFX_SMU_RMEF_EF9_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMEF_Bits.EF9 */
+#define IFX_SMU_RMEF_EF9_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMEF_Bits.EF9 */
+#define IFX_SMU_RMEF_EF9_OFF (9u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS0 */
+#define IFX_SMU_RMSTS_STS0_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS0 */
+#define IFX_SMU_RMSTS_STS0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS0 */
+#define IFX_SMU_RMSTS_STS0_OFF (0u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS10 */
+#define IFX_SMU_RMSTS_STS10_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS10 */
+#define IFX_SMU_RMSTS_STS10_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS10 */
+#define IFX_SMU_RMSTS_STS10_OFF (10u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS11 */
+#define IFX_SMU_RMSTS_STS11_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS11 */
+#define IFX_SMU_RMSTS_STS11_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS11 */
+#define IFX_SMU_RMSTS_STS11_OFF (11u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS12 */
+#define IFX_SMU_RMSTS_STS12_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS12 */
+#define IFX_SMU_RMSTS_STS12_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS12 */
+#define IFX_SMU_RMSTS_STS12_OFF (12u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS13 */
+#define IFX_SMU_RMSTS_STS13_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS13 */
+#define IFX_SMU_RMSTS_STS13_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS13 */
+#define IFX_SMU_RMSTS_STS13_OFF (13u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS14 */
+#define IFX_SMU_RMSTS_STS14_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS14 */
+#define IFX_SMU_RMSTS_STS14_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS14 */
+#define IFX_SMU_RMSTS_STS14_OFF (14u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS15 */
+#define IFX_SMU_RMSTS_STS15_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS15 */
+#define IFX_SMU_RMSTS_STS15_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS15 */
+#define IFX_SMU_RMSTS_STS15_OFF (15u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS16 */
+#define IFX_SMU_RMSTS_STS16_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS16 */
+#define IFX_SMU_RMSTS_STS16_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS16 */
+#define IFX_SMU_RMSTS_STS16_OFF (16u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS17 */
+#define IFX_SMU_RMSTS_STS17_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS17 */
+#define IFX_SMU_RMSTS_STS17_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS17 */
+#define IFX_SMU_RMSTS_STS17_OFF (17u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS18 */
+#define IFX_SMU_RMSTS_STS18_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS18 */
+#define IFX_SMU_RMSTS_STS18_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS18 */
+#define IFX_SMU_RMSTS_STS18_OFF (18u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS19 */
+#define IFX_SMU_RMSTS_STS19_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS19 */
+#define IFX_SMU_RMSTS_STS19_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS19 */
+#define IFX_SMU_RMSTS_STS19_OFF (19u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS1 */
+#define IFX_SMU_RMSTS_STS1_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS1 */
+#define IFX_SMU_RMSTS_STS1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS1 */
+#define IFX_SMU_RMSTS_STS1_OFF (1u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS20 */
+#define IFX_SMU_RMSTS_STS20_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS20 */
+#define IFX_SMU_RMSTS_STS20_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS20 */
+#define IFX_SMU_RMSTS_STS20_OFF (20u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS21 */
+#define IFX_SMU_RMSTS_STS21_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS21 */
+#define IFX_SMU_RMSTS_STS21_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS21 */
+#define IFX_SMU_RMSTS_STS21_OFF (21u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS22 */
+#define IFX_SMU_RMSTS_STS22_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS22 */
+#define IFX_SMU_RMSTS_STS22_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS22 */
+#define IFX_SMU_RMSTS_STS22_OFF (22u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS23 */
+#define IFX_SMU_RMSTS_STS23_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS23 */
+#define IFX_SMU_RMSTS_STS23_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS23 */
+#define IFX_SMU_RMSTS_STS23_OFF (23u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS24 */
+#define IFX_SMU_RMSTS_STS24_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS24 */
+#define IFX_SMU_RMSTS_STS24_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS24 */
+#define IFX_SMU_RMSTS_STS24_OFF (24u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS25 */
+#define IFX_SMU_RMSTS_STS25_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS25 */
+#define IFX_SMU_RMSTS_STS25_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS25 */
+#define IFX_SMU_RMSTS_STS25_OFF (25u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS26 */
+#define IFX_SMU_RMSTS_STS26_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS26 */
+#define IFX_SMU_RMSTS_STS26_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS26 */
+#define IFX_SMU_RMSTS_STS26_OFF (26u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS27 */
+#define IFX_SMU_RMSTS_STS27_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS27 */
+#define IFX_SMU_RMSTS_STS27_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS27 */
+#define IFX_SMU_RMSTS_STS27_OFF (27u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS28 */
+#define IFX_SMU_RMSTS_STS28_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS28 */
+#define IFX_SMU_RMSTS_STS28_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS28 */
+#define IFX_SMU_RMSTS_STS28_OFF (28u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS29 */
+#define IFX_SMU_RMSTS_STS29_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS29 */
+#define IFX_SMU_RMSTS_STS29_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS29 */
+#define IFX_SMU_RMSTS_STS29_OFF (29u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS2 */
+#define IFX_SMU_RMSTS_STS2_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS2 */
+#define IFX_SMU_RMSTS_STS2_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS2 */
+#define IFX_SMU_RMSTS_STS2_OFF (2u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS30 */
+#define IFX_SMU_RMSTS_STS30_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS30 */
+#define IFX_SMU_RMSTS_STS30_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS30 */
+#define IFX_SMU_RMSTS_STS30_OFF (30u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS31 */
+#define IFX_SMU_RMSTS_STS31_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS31 */
+#define IFX_SMU_RMSTS_STS31_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS31 */
+#define IFX_SMU_RMSTS_STS31_OFF (31u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS3 */
+#define IFX_SMU_RMSTS_STS3_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS3 */
+#define IFX_SMU_RMSTS_STS3_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS3 */
+#define IFX_SMU_RMSTS_STS3_OFF (3u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS4 */
+#define IFX_SMU_RMSTS_STS4_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS4 */
+#define IFX_SMU_RMSTS_STS4_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS4 */
+#define IFX_SMU_RMSTS_STS4_OFF (4u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS5 */
+#define IFX_SMU_RMSTS_STS5_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS5 */
+#define IFX_SMU_RMSTS_STS5_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS5 */
+#define IFX_SMU_RMSTS_STS5_OFF (5u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS6 */
+#define IFX_SMU_RMSTS_STS6_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS6 */
+#define IFX_SMU_RMSTS_STS6_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS6 */
+#define IFX_SMU_RMSTS_STS6_OFF (6u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS7 */
+#define IFX_SMU_RMSTS_STS7_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS7 */
+#define IFX_SMU_RMSTS_STS7_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS7 */
+#define IFX_SMU_RMSTS_STS7_OFF (7u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS8 */
+#define IFX_SMU_RMSTS_STS8_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS8 */
+#define IFX_SMU_RMSTS_STS8_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS8 */
+#define IFX_SMU_RMSTS_STS8_OFF (8u)
+
+/** \brief Length for Ifx_SMU_RMSTS_Bits.STS9 */
+#define IFX_SMU_RMSTS_STS9_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RMSTS_Bits.STS9 */
+#define IFX_SMU_RMSTS_STS9_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RMSTS_Bits.STS9 */
+#define IFX_SMU_RMSTS_STS9_OFF (9u)
+
+/** \brief Length for Ifx_SMU_RTAC0_Bits.ALID0 */
+#define IFX_SMU_RTAC0_ALID0_LEN (5u)
+
+/** \brief Mask for Ifx_SMU_RTAC0_Bits.ALID0 */
+#define IFX_SMU_RTAC0_ALID0_MSK (0x1fu)
+
+/** \brief Offset for Ifx_SMU_RTAC0_Bits.ALID0 */
+#define IFX_SMU_RTAC0_ALID0_OFF (3u)
+
+/** \brief Length for Ifx_SMU_RTAC0_Bits.ALID1 */
+#define IFX_SMU_RTAC0_ALID1_LEN (5u)
+
+/** \brief Mask for Ifx_SMU_RTAC0_Bits.ALID1 */
+#define IFX_SMU_RTAC0_ALID1_MSK (0x1fu)
+
+/** \brief Offset for Ifx_SMU_RTAC0_Bits.ALID1 */
+#define IFX_SMU_RTAC0_ALID1_OFF (11u)
+
+/** \brief Length for Ifx_SMU_RTAC0_Bits.ALID2 */
+#define IFX_SMU_RTAC0_ALID2_LEN (5u)
+
+/** \brief Mask for Ifx_SMU_RTAC0_Bits.ALID2 */
+#define IFX_SMU_RTAC0_ALID2_MSK (0x1fu)
+
+/** \brief Offset for Ifx_SMU_RTAC0_Bits.ALID2 */
+#define IFX_SMU_RTAC0_ALID2_OFF (19u)
+
+/** \brief Length for Ifx_SMU_RTAC0_Bits.ALID3 */
+#define IFX_SMU_RTAC0_ALID3_LEN (5u)
+
+/** \brief Mask for Ifx_SMU_RTAC0_Bits.ALID3 */
+#define IFX_SMU_RTAC0_ALID3_MSK (0x1fu)
+
+/** \brief Offset for Ifx_SMU_RTAC0_Bits.ALID3 */
+#define IFX_SMU_RTAC0_ALID3_OFF (27u)
+
+/** \brief Length for Ifx_SMU_RTAC0_Bits.GID0 */
+#define IFX_SMU_RTAC0_GID0_LEN (3u)
+
+/** \brief Mask for Ifx_SMU_RTAC0_Bits.GID0 */
+#define IFX_SMU_RTAC0_GID0_MSK (0x7u)
+
+/** \brief Offset for Ifx_SMU_RTAC0_Bits.GID0 */
+#define IFX_SMU_RTAC0_GID0_OFF (0u)
+
+/** \brief Length for Ifx_SMU_RTAC0_Bits.GID1 */
+#define IFX_SMU_RTAC0_GID1_LEN (3u)
+
+/** \brief Mask for Ifx_SMU_RTAC0_Bits.GID1 */
+#define IFX_SMU_RTAC0_GID1_MSK (0x7u)
+
+/** \brief Offset for Ifx_SMU_RTAC0_Bits.GID1 */
+#define IFX_SMU_RTAC0_GID1_OFF (8u)
+
+/** \brief Length for Ifx_SMU_RTAC0_Bits.GID2 */
+#define IFX_SMU_RTAC0_GID2_LEN (3u)
+
+/** \brief Mask for Ifx_SMU_RTAC0_Bits.GID2 */
+#define IFX_SMU_RTAC0_GID2_MSK (0x7u)
+
+/** \brief Offset for Ifx_SMU_RTAC0_Bits.GID2 */
+#define IFX_SMU_RTAC0_GID2_OFF (16u)
+
+/** \brief Length for Ifx_SMU_RTAC0_Bits.GID3 */
+#define IFX_SMU_RTAC0_GID3_LEN (3u)
+
+/** \brief Mask for Ifx_SMU_RTAC0_Bits.GID3 */
+#define IFX_SMU_RTAC0_GID3_MSK (0x7u)
+
+/** \brief Offset for Ifx_SMU_RTAC0_Bits.GID3 */
+#define IFX_SMU_RTAC0_GID3_OFF (24u)
+
+/** \brief Length for Ifx_SMU_RTAC1_Bits.ALID0 */
+#define IFX_SMU_RTAC1_ALID0_LEN (5u)
+
+/** \brief Mask for Ifx_SMU_RTAC1_Bits.ALID0 */
+#define IFX_SMU_RTAC1_ALID0_MSK (0x1fu)
+
+/** \brief Offset for Ifx_SMU_RTAC1_Bits.ALID0 */
+#define IFX_SMU_RTAC1_ALID0_OFF (3u)
+
+/** \brief Length for Ifx_SMU_RTAC1_Bits.ALID1 */
+#define IFX_SMU_RTAC1_ALID1_LEN (5u)
+
+/** \brief Mask for Ifx_SMU_RTAC1_Bits.ALID1 */
+#define IFX_SMU_RTAC1_ALID1_MSK (0x1fu)
+
+/** \brief Offset for Ifx_SMU_RTAC1_Bits.ALID1 */
+#define IFX_SMU_RTAC1_ALID1_OFF (11u)
+
+/** \brief Length for Ifx_SMU_RTAC1_Bits.ALID2 */
+#define IFX_SMU_RTAC1_ALID2_LEN (5u)
+
+/** \brief Mask for Ifx_SMU_RTAC1_Bits.ALID2 */
+#define IFX_SMU_RTAC1_ALID2_MSK (0x1fu)
+
+/** \brief Offset for Ifx_SMU_RTAC1_Bits.ALID2 */
+#define IFX_SMU_RTAC1_ALID2_OFF (19u)
+
+/** \brief Length for Ifx_SMU_RTAC1_Bits.ALID3 */
+#define IFX_SMU_RTAC1_ALID3_LEN (5u)
+
+/** \brief Mask for Ifx_SMU_RTAC1_Bits.ALID3 */
+#define IFX_SMU_RTAC1_ALID3_MSK (0x1fu)
+
+/** \brief Offset for Ifx_SMU_RTAC1_Bits.ALID3 */
+#define IFX_SMU_RTAC1_ALID3_OFF (27u)
+
+/** \brief Length for Ifx_SMU_RTAC1_Bits.GID0 */
+#define IFX_SMU_RTAC1_GID0_LEN (3u)
+
+/** \brief Mask for Ifx_SMU_RTAC1_Bits.GID0 */
+#define IFX_SMU_RTAC1_GID0_MSK (0x7u)
+
+/** \brief Offset for Ifx_SMU_RTAC1_Bits.GID0 */
+#define IFX_SMU_RTAC1_GID0_OFF (0u)
+
+/** \brief Length for Ifx_SMU_RTAC1_Bits.GID1 */
+#define IFX_SMU_RTAC1_GID1_LEN (3u)
+
+/** \brief Mask for Ifx_SMU_RTAC1_Bits.GID1 */
+#define IFX_SMU_RTAC1_GID1_MSK (0x7u)
+
+/** \brief Offset for Ifx_SMU_RTAC1_Bits.GID1 */
+#define IFX_SMU_RTAC1_GID1_OFF (8u)
+
+/** \brief Length for Ifx_SMU_RTAC1_Bits.GID2 */
+#define IFX_SMU_RTAC1_GID2_LEN (3u)
+
+/** \brief Mask for Ifx_SMU_RTAC1_Bits.GID2 */
+#define IFX_SMU_RTAC1_GID2_MSK (0x7u)
+
+/** \brief Offset for Ifx_SMU_RTAC1_Bits.GID2 */
+#define IFX_SMU_RTAC1_GID2_OFF (16u)
+
+/** \brief Length for Ifx_SMU_RTAC1_Bits.GID3 */
+#define IFX_SMU_RTAC1_GID3_LEN (3u)
+
+/** \brief Mask for Ifx_SMU_RTAC1_Bits.GID3 */
+#define IFX_SMU_RTAC1_GID3_MSK (0x7u)
+
+/** \brief Offset for Ifx_SMU_RTAC1_Bits.GID3 */
+#define IFX_SMU_RTAC1_GID3_OFF (24u)
+
+/** \brief Length for Ifx_SMU_RTC_Bits.RT0E */
+#define IFX_SMU_RTC_RT0E_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RTC_Bits.RT0E */
+#define IFX_SMU_RTC_RT0E_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RTC_Bits.RT0E */
+#define IFX_SMU_RTC_RT0E_OFF (0u)
+
+/** \brief Length for Ifx_SMU_RTC_Bits.RT1E */
+#define IFX_SMU_RTC_RT1E_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_RTC_Bits.RT1E */
+#define IFX_SMU_RTC_RT1E_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_RTC_Bits.RT1E */
+#define IFX_SMU_RTC_RT1E_OFF (1u)
+
+/** \brief Length for Ifx_SMU_RTC_Bits.RTD */
+#define IFX_SMU_RTC_RTD_LEN (24u)
+
+/** \brief Mask for Ifx_SMU_RTC_Bits.RTD */
+#define IFX_SMU_RTC_RTD_MSK (0xffffffu)
+
+/** \brief Offset for Ifx_SMU_RTC_Bits.RTD */
+#define IFX_SMU_RTC_RTD_OFF (8u)
+
+/** \brief Length for Ifx_SMU_STS_Bits.ARG */
+#define IFX_SMU_STS_ARG_LEN (4u)
+
+/** \brief Mask for Ifx_SMU_STS_Bits.ARG */
+#define IFX_SMU_STS_ARG_MSK (0xfu)
+
+/** \brief Offset for Ifx_SMU_STS_Bits.ARG */
+#define IFX_SMU_STS_ARG_OFF (4u)
+
+/** \brief Length for Ifx_SMU_STS_Bits.ASCE */
+#define IFX_SMU_STS_ASCE_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_STS_Bits.ASCE */
+#define IFX_SMU_STS_ASCE_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_STS_Bits.ASCE */
+#define IFX_SMU_STS_ASCE_OFF (9u)
+
+/** \brief Length for Ifx_SMU_STS_Bits.CMD */
+#define IFX_SMU_STS_CMD_LEN (4u)
+
+/** \brief Mask for Ifx_SMU_STS_Bits.CMD */
+#define IFX_SMU_STS_CMD_MSK (0xfu)
+
+/** \brief Offset for Ifx_SMU_STS_Bits.CMD */
+#define IFX_SMU_STS_CMD_OFF (0u)
+
+/** \brief Length for Ifx_SMU_STS_Bits.FSP */
+#define IFX_SMU_STS_FSP_LEN (2u)
+
+/** \brief Mask for Ifx_SMU_STS_Bits.FSP */
+#define IFX_SMU_STS_FSP_MSK (0x3u)
+
+/** \brief Offset for Ifx_SMU_STS_Bits.FSP */
+#define IFX_SMU_STS_FSP_OFF (10u)
+
+/** \brief Length for Ifx_SMU_STS_Bits.FSTS */
+#define IFX_SMU_STS_FSTS_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_STS_Bits.FSTS */
+#define IFX_SMU_STS_FSTS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_STS_Bits.FSTS */
+#define IFX_SMU_STS_FSTS_OFF (12u)
+
+/** \brief Length for Ifx_SMU_STS_Bits.RES */
+#define IFX_SMU_STS_RES_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_STS_Bits.RES */
+#define IFX_SMU_STS_RES_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_STS_Bits.RES */
+#define IFX_SMU_STS_RES_OFF (8u)
+
+/** \brief Length for Ifx_SMU_STS_Bits.RTME0 */
+#define IFX_SMU_STS_RTME0_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_STS_Bits.RTME0 */
+#define IFX_SMU_STS_RTME0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_STS_Bits.RTME0 */
+#define IFX_SMU_STS_RTME0_OFF (17u)
+
+/** \brief Length for Ifx_SMU_STS_Bits.RTME1 */
+#define IFX_SMU_STS_RTME1_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_STS_Bits.RTME1 */
+#define IFX_SMU_STS_RTME1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_STS_Bits.RTME1 */
+#define IFX_SMU_STS_RTME1_OFF (19u)
+
+/** \brief Length for Ifx_SMU_STS_Bits.RTS0 */
+#define IFX_SMU_STS_RTS0_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_STS_Bits.RTS0 */
+#define IFX_SMU_STS_RTS0_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_STS_Bits.RTS0 */
+#define IFX_SMU_STS_RTS0_OFF (16u)
+
+/** \brief Length for Ifx_SMU_STS_Bits.RTS1 */
+#define IFX_SMU_STS_RTS1_LEN (1u)
+
+/** \brief Mask for Ifx_SMU_STS_Bits.RTS1 */
+#define IFX_SMU_STS_RTS1_MSK (0x1u)
+
+/** \brief Offset for Ifx_SMU_STS_Bits.RTS1 */
+#define IFX_SMU_STS_RTS1_OFF (18u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXSMU_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSmu_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSmu_reg.h
new file mode 100644
index 0000000..1123dd6
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSmu_reg.h
@@ -0,0 +1,383 @@
+/**
+ * \file IfxSmu_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Smu_Cfg Smu address
+ * \ingroup IfxLld_Smu
+ *
+ * \defgroup IfxLld_Smu_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Smu_Cfg
+ *
+ * \defgroup IfxLld_Smu_Cfg_Smu 2-SMU
+ * \ingroup IfxLld_Smu_Cfg
+ *
+ */
+#ifndef IFXSMU_REG_H
+#define IFXSMU_REG_H 1
+/******************************************************************************/
+#include "IfxSmu_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Smu_Cfg_BaseAddress
+ * \{ */
+
+/** \brief SMU object */
+#define MODULE_SMU /*lint --e(923)*/ (*(Ifx_SMU*)0xF0036800u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Smu_Cfg_Smu
+ * \{ */
+
+/** \brief 7FC, SMU Access Enable Register 0 */
+#define SMU_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_SMU_ACCEN0*)0xF0036FFCu)
+
+/** \brief 7F8, SMU Access Enable Register 1 */
+#define SMU_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_SMU_ACCEN1*)0xF0036FF8u)
+
+/** \brief 200, Alarm Status Register */
+#define SMU_AD0 /*lint --e(923)*/ (*(volatile Ifx_SMU_AD*)0xF0036A00u)
+
+/** \brief 204, Alarm Status Register */
+#define SMU_AD1 /*lint --e(923)*/ (*(volatile Ifx_SMU_AD*)0xF0036A04u)
+
+/** \brief 208, Alarm Status Register */
+#define SMU_AD2 /*lint --e(923)*/ (*(volatile Ifx_SMU_AD*)0xF0036A08u)
+
+/** \brief 20C, Alarm Status Register */
+#define SMU_AD3 /*lint --e(923)*/ (*(volatile Ifx_SMU_AD*)0xF0036A0Cu)
+
+/** \brief 210, Alarm Status Register */
+#define SMU_AD4 /*lint --e(923)*/ (*(volatile Ifx_SMU_AD*)0xF0036A10u)
+
+/** \brief 214, Alarm Status Register */
+#define SMU_AD5 /*lint --e(923)*/ (*(volatile Ifx_SMU_AD*)0xF0036A14u)
+
+/** \brief 218, Alarm Status Register */
+#define SMU_AD6 /*lint --e(923)*/ (*(volatile Ifx_SMU_AD*)0xF0036A18u)
+
+/** \brief 40, Alarm and Fault Counter */
+#define SMU_AFCNT /*lint --e(923)*/ (*(volatile Ifx_SMU_AFCNT*)0xF0036840u)
+
+/** \brief 1C0, Alarm Status Register */
+#define SMU_AG0 /*lint --e(923)*/ (*(volatile Ifx_SMU_AG*)0xF00369C0u)
+
+/** \brief 1C4, Alarm Status Register */
+#define SMU_AG1 /*lint --e(923)*/ (*(volatile Ifx_SMU_AG*)0xF00369C4u)
+
+/** \brief 1C8, Alarm Status Register */
+#define SMU_AG2 /*lint --e(923)*/ (*(volatile Ifx_SMU_AG*)0xF00369C8u)
+
+/** \brief 1CC, Alarm Status Register */
+#define SMU_AG3 /*lint --e(923)*/ (*(volatile Ifx_SMU_AG*)0xF00369CCu)
+
+/** \brief 1D0, Alarm Status Register */
+#define SMU_AG4 /*lint --e(923)*/ (*(volatile Ifx_SMU_AG*)0xF00369D0u)
+
+/** \brief 1D4, Alarm Status Register */
+#define SMU_AG5 /*lint --e(923)*/ (*(volatile Ifx_SMU_AG*)0xF00369D4u)
+
+/** \brief 1D8, Alarm Status Register */
+#define SMU_AG6 /*lint --e(923)*/ (*(volatile Ifx_SMU_AG*)0xF00369D8u)
+
+/** \brief 2C, Alarm Global Configuration */
+#define SMU_AGC /*lint --e(923)*/ (*(volatile Ifx_SMU_AGC*)0xF003682Cu)
+
+/** \brief 100, Alarm Configuration Register */
+#define SMU_AGCF0_0 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036900u)
+
+/** Alias (User Manual Name) for SMU_AGCF0_0.
+* To use register names with standard convension, please use SMU_AGCF0_0.
+*/
+#define SMU_AG0CF0 (SMU_AGCF0_0)
+
+/** \brief 104, Alarm Configuration Register */
+#define SMU_AGCF0_1 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036904u)
+
+/** Alias (User Manual Name) for SMU_AGCF0_1.
+* To use register names with standard convension, please use SMU_AGCF0_1.
+*/
+#define SMU_AG0CF1 (SMU_AGCF0_1)
+
+/** \brief 108, Alarm Configuration Register */
+#define SMU_AGCF0_2 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036908u)
+
+/** Alias (User Manual Name) for SMU_AGCF0_2.
+* To use register names with standard convension, please use SMU_AGCF0_2.
+*/
+#define SMU_AG0CF2 (SMU_AGCF0_2)
+
+/** \brief 10C, Alarm Configuration Register */
+#define SMU_AGCF1_0 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF003690Cu)
+
+/** Alias (User Manual Name) for SMU_AGCF1_0.
+* To use register names with standard convension, please use SMU_AGCF1_0.
+*/
+#define SMU_AG1CF0 (SMU_AGCF1_0)
+
+/** \brief 110, Alarm Configuration Register */
+#define SMU_AGCF1_1 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036910u)
+
+/** Alias (User Manual Name) for SMU_AGCF1_1.
+* To use register names with standard convension, please use SMU_AGCF1_1.
+*/
+#define SMU_AG1CF1 (SMU_AGCF1_1)
+
+/** \brief 114, Alarm Configuration Register */
+#define SMU_AGCF1_2 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036914u)
+
+/** Alias (User Manual Name) for SMU_AGCF1_2.
+* To use register names with standard convension, please use SMU_AGCF1_2.
+*/
+#define SMU_AG1CF2 (SMU_AGCF1_2)
+
+/** \brief 118, Alarm Configuration Register */
+#define SMU_AGCF2_0 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036918u)
+
+/** Alias (User Manual Name) for SMU_AGCF2_0.
+* To use register names with standard convension, please use SMU_AGCF2_0.
+*/
+#define SMU_AG2CF0 (SMU_AGCF2_0)
+
+/** \brief 11C, Alarm Configuration Register */
+#define SMU_AGCF2_1 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF003691Cu)
+
+/** Alias (User Manual Name) for SMU_AGCF2_1.
+* To use register names with standard convension, please use SMU_AGCF2_1.
+*/
+#define SMU_AG2CF1 (SMU_AGCF2_1)
+
+/** \brief 120, Alarm Configuration Register */
+#define SMU_AGCF2_2 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036920u)
+
+/** Alias (User Manual Name) for SMU_AGCF2_2.
+* To use register names with standard convension, please use SMU_AGCF2_2.
+*/
+#define SMU_AG2CF2 (SMU_AGCF2_2)
+
+/** \brief 124, Alarm Configuration Register */
+#define SMU_AGCF3_0 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036924u)
+
+/** Alias (User Manual Name) for SMU_AGCF3_0.
+* To use register names with standard convension, please use SMU_AGCF3_0.
+*/
+#define SMU_AG3CF0 (SMU_AGCF3_0)
+
+/** \brief 128, Alarm Configuration Register */
+#define SMU_AGCF3_1 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036928u)
+
+/** Alias (User Manual Name) for SMU_AGCF3_1.
+* To use register names with standard convension, please use SMU_AGCF3_1.
+*/
+#define SMU_AG3CF1 (SMU_AGCF3_1)
+
+/** \brief 12C, Alarm Configuration Register */
+#define SMU_AGCF3_2 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF003692Cu)
+
+/** Alias (User Manual Name) for SMU_AGCF3_2.
+* To use register names with standard convension, please use SMU_AGCF3_2.
+*/
+#define SMU_AG3CF2 (SMU_AGCF3_2)
+
+/** \brief 130, Alarm Configuration Register */
+#define SMU_AGCF4_0 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036930u)
+
+/** Alias (User Manual Name) for SMU_AGCF4_0.
+* To use register names with standard convension, please use SMU_AGCF4_0.
+*/
+#define SMU_AG4CF0 (SMU_AGCF4_0)
+
+/** \brief 134, Alarm Configuration Register */
+#define SMU_AGCF4_1 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036934u)
+
+/** Alias (User Manual Name) for SMU_AGCF4_1.
+* To use register names with standard convension, please use SMU_AGCF4_1.
+*/
+#define SMU_AG4CF1 (SMU_AGCF4_1)
+
+/** \brief 138, Alarm Configuration Register */
+#define SMU_AGCF4_2 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036938u)
+
+/** Alias (User Manual Name) for SMU_AGCF4_2.
+* To use register names with standard convension, please use SMU_AGCF4_2.
+*/
+#define SMU_AG4CF2 (SMU_AGCF4_2)
+
+/** \brief 13C, Alarm Configuration Register */
+#define SMU_AGCF5_0 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF003693Cu)
+
+/** Alias (User Manual Name) for SMU_AGCF5_0.
+* To use register names with standard convension, please use SMU_AGCF5_0.
+*/
+#define SMU_AG5CF0 (SMU_AGCF5_0)
+
+/** \brief 140, Alarm Configuration Register */
+#define SMU_AGCF5_1 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036940u)
+
+/** Alias (User Manual Name) for SMU_AGCF5_1.
+* To use register names with standard convension, please use SMU_AGCF5_1.
+*/
+#define SMU_AG5CF1 (SMU_AGCF5_1)
+
+/** \brief 144, Alarm Configuration Register */
+#define SMU_AGCF5_2 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036944u)
+
+/** Alias (User Manual Name) for SMU_AGCF5_2.
+* To use register names with standard convension, please use SMU_AGCF5_2.
+*/
+#define SMU_AG5CF2 (SMU_AGCF5_2)
+
+/** \brief 148, Alarm Configuration Register */
+#define SMU_AGCF6_0 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036948u)
+
+/** Alias (User Manual Name) for SMU_AGCF6_0.
+* To use register names with standard convension, please use SMU_AGCF6_0.
+*/
+#define SMU_AG6CF0 (SMU_AGCF6_0)
+
+/** \brief 14C, Alarm Configuration Register */
+#define SMU_AGCF6_1 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF003694Cu)
+
+/** Alias (User Manual Name) for SMU_AGCF6_1.
+* To use register names with standard convension, please use SMU_AGCF6_1.
+*/
+#define SMU_AG6CF1 (SMU_AGCF6_1)
+
+/** \brief 150, Alarm Configuration Register */
+#define SMU_AGCF6_2 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036950u)
+
+/** Alias (User Manual Name) for SMU_AGCF6_2.
+* To use register names with standard convension, please use SMU_AGCF6_2.
+*/
+#define SMU_AG6CF2 (SMU_AGCF6_2)
+
+/** \brief 180, FSP Configuration Register */
+#define SMU_AGFSP0 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGFSP*)0xF0036980u)
+
+/** Alias (User Manual Name) for SMU_AGFSP0.
+* To use register names with standard convension, please use SMU_AGFSP0.
+*/
+#define SMU_AG0FSP (SMU_AGFSP0)
+
+/** \brief 184, FSP Configuration Register */
+#define SMU_AGFSP1 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGFSP*)0xF0036984u)
+
+/** Alias (User Manual Name) for SMU_AGFSP1.
+* To use register names with standard convension, please use SMU_AGFSP1.
+*/
+#define SMU_AG1FSP (SMU_AGFSP1)
+
+/** \brief 188, FSP Configuration Register */
+#define SMU_AGFSP2 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGFSP*)0xF0036988u)
+
+/** Alias (User Manual Name) for SMU_AGFSP2.
+* To use register names with standard convension, please use SMU_AGFSP2.
+*/
+#define SMU_AG2FSP (SMU_AGFSP2)
+
+/** \brief 18C, FSP Configuration Register */
+#define SMU_AGFSP3 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGFSP*)0xF003698Cu)
+
+/** Alias (User Manual Name) for SMU_AGFSP3.
+* To use register names with standard convension, please use SMU_AGFSP3.
+*/
+#define SMU_AG3FSP (SMU_AGFSP3)
+
+/** \brief 190, FSP Configuration Register */
+#define SMU_AGFSP4 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGFSP*)0xF0036990u)
+
+/** Alias (User Manual Name) for SMU_AGFSP4.
+* To use register names with standard convension, please use SMU_AGFSP4.
+*/
+#define SMU_AG4FSP (SMU_AGFSP4)
+
+/** \brief 194, FSP Configuration Register */
+#define SMU_AGFSP5 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGFSP*)0xF0036994u)
+
+/** Alias (User Manual Name) for SMU_AGFSP5.
+* To use register names with standard convension, please use SMU_AGFSP5.
+*/
+#define SMU_AG5FSP (SMU_AGFSP5)
+
+/** \brief 198, FSP Configuration Register */
+#define SMU_AGFSP6 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGFSP*)0xF0036998u)
+
+/** Alias (User Manual Name) for SMU_AGFSP6.
+* To use register names with standard convension, please use SMU_AGFSP6.
+*/
+#define SMU_AG6FSP (SMU_AGFSP6)
+
+/** \brief 0, Clock Control Register */
+#define SMU_CLC /*lint --e(923)*/ (*(volatile Ifx_SMU_CLC*)0xF0036800u)
+
+/** \brief 20, Command Register */
+#define SMU_CMD /*lint --e(923)*/ (*(volatile Ifx_SMU_CMD*)0xF0036820u)
+
+/** \brief 38, Debug Register */
+#define SMU_DBG /*lint --e(923)*/ (*(volatile Ifx_SMU_DBG*)0xF0036838u)
+
+/** \brief 28, Fault Signaling Protocol */
+#define SMU_FSP /*lint --e(923)*/ (*(volatile Ifx_SMU_FSP*)0xF0036828u)
+
+/** \brief 8, Module Identification Register */
+#define SMU_ID /*lint --e(923)*/ (*(volatile Ifx_SMU_ID*)0xF0036808u)
+
+/** \brief 34, Key Register */
+#define SMU_KEYS /*lint --e(923)*/ (*(volatile Ifx_SMU_KEYS*)0xF0036834u)
+
+/** \brief 7F4, SMU Reset Register 0 */
+#define SMU_KRST0 /*lint --e(923)*/ (*(volatile Ifx_SMU_KRST0*)0xF0036FF4u)
+
+/** \brief 7F0, SMU Reset Register 1 */
+#define SMU_KRST1 /*lint --e(923)*/ (*(volatile Ifx_SMU_KRST1*)0xF0036FF0u)
+
+/** \brief 7EC, SMU Reset Status Clear Register */
+#define SMU_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_SMU_KRSTCLR*)0xF0036FECu)
+
+/** \brief 7E8, OCDS Control and Status */
+#define SMU_OCS /*lint --e(923)*/ (*(volatile Ifx_SMU_OCS*)0xF0036FE8u)
+
+/** \brief 3C, Port Control */
+#define SMU_PCTL /*lint --e(923)*/ (*(volatile Ifx_SMU_PCTL*)0xF003683Cu)
+
+/** \brief 300, Register Monitor Control */
+#define SMU_RMCTL /*lint --e(923)*/ (*(volatile Ifx_SMU_RMCTL*)0xF0036B00u)
+
+/** \brief 304, Register Monitor Error Flags */
+#define SMU_RMEF /*lint --e(923)*/ (*(volatile Ifx_SMU_RMEF*)0xF0036B04u)
+
+/** \brief 308, Register Monitor Self Test Status */
+#define SMU_RMSTS /*lint --e(923)*/ (*(volatile Ifx_SMU_RMSTS*)0xF0036B08u)
+
+/** \brief 60, Recovery Timer Alarm Configuration */
+#define SMU_RTAC0 /*lint --e(923)*/ (*(volatile Ifx_SMU_RTAC0*)0xF0036860u)
+
+/** \brief 64, Recovery Timer Alarm Configuration */
+#define SMU_RTAC1 /*lint --e(923)*/ (*(volatile Ifx_SMU_RTAC1*)0xF0036864u)
+
+/** \brief 30, Fault Signaling Protocol */
+#define SMU_RTC /*lint --e(923)*/ (*(volatile Ifx_SMU_RTC*)0xF0036830u)
+
+/** \brief 24, Status Register */
+#define SMU_STS /*lint --e(923)*/ (*(volatile Ifx_SMU_STS*)0xF0036824u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXSMU_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSmu_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSmu_regdef.h
new file mode 100644
index 0000000..ba00ff5
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSmu_regdef.h
@@ -0,0 +1,758 @@
+/**
+ * \file IfxSmu_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Smu Smu
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Smu_Bitfields Bitfields
+ * \ingroup IfxLld_Smu
+ *
+ * \defgroup IfxLld_Smu_union Union
+ * \ingroup IfxLld_Smu
+ *
+ * \defgroup IfxLld_Smu_struct Struct
+ * \ingroup IfxLld_Smu
+ *
+ */
+#ifndef IFXSMU_REGDEF_H
+#define IFXSMU_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Smu_Bitfields
+ * \{ */
+
+/** \brief SMU Access Enable Register 0 */
+typedef struct _Ifx_SMU_ACCEN0_Bits
+{
+ Ifx_Strict_32Bit EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ Ifx_Strict_32Bit EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ Ifx_Strict_32Bit EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ Ifx_Strict_32Bit EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ Ifx_Strict_32Bit EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ Ifx_Strict_32Bit EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ Ifx_Strict_32Bit EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ Ifx_Strict_32Bit EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ Ifx_Strict_32Bit EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ Ifx_Strict_32Bit EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ Ifx_Strict_32Bit EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ Ifx_Strict_32Bit EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ Ifx_Strict_32Bit EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ Ifx_Strict_32Bit EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ Ifx_Strict_32Bit EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ Ifx_Strict_32Bit EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ Ifx_Strict_32Bit EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ Ifx_Strict_32Bit EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ Ifx_Strict_32Bit EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ Ifx_Strict_32Bit EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ Ifx_Strict_32Bit EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ Ifx_Strict_32Bit EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ Ifx_Strict_32Bit EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ Ifx_Strict_32Bit EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ Ifx_Strict_32Bit EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ Ifx_Strict_32Bit EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ Ifx_Strict_32Bit EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ Ifx_Strict_32Bit EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ Ifx_Strict_32Bit EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ Ifx_Strict_32Bit EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ Ifx_Strict_32Bit EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ Ifx_Strict_32Bit EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_SMU_ACCEN0_Bits;
+
+/** \brief SMU Access Enable Register 1 */
+typedef struct _Ifx_SMU_ACCEN1_Bits
+{
+ Ifx_Strict_32Bit reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_SMU_ACCEN1_Bits;
+
+/** \brief Alarm Status Register */
+typedef struct _Ifx_SMU_AD_Bits
+{
+ Ifx_Strict_32Bit DF0:1; /**< \brief [0:0] Debug flag for alarm 0 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF1:1; /**< \brief [1:1] Debug flag for alarm 1 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF2:1; /**< \brief [2:2] Debug flag for alarm 2 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF3:1; /**< \brief [3:3] Debug flag for alarm 3 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF4:1; /**< \brief [4:4] Debug flag for alarm 4 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF5:1; /**< \brief [5:5] Debug flag for alarm 5 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF6:1; /**< \brief [6:6] Debug flag for alarm 6 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF7:1; /**< \brief [7:7] Debug flag for alarm 7 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF8:1; /**< \brief [8:8] Debug flag for alarm 8 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF9:1; /**< \brief [9:9] Debug flag for alarm 9 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF10:1; /**< \brief [10:10] Debug flag for alarm 10 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF11:1; /**< \brief [11:11] Debug flag for alarm 11 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF12:1; /**< \brief [12:12] Debug flag for alarm 12 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF13:1; /**< \brief [13:13] Debug flag for alarm 13 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF14:1; /**< \brief [14:14] Debug flag for alarm 14 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF15:1; /**< \brief [15:15] Debug flag for alarm 15 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF16:1; /**< \brief [16:16] Debug flag for alarm 16 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF17:1; /**< \brief [17:17] Debug flag for alarm 17 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF18:1; /**< \brief [18:18] Debug flag for alarm 18 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF19:1; /**< \brief [19:19] Debug flag for alarm 19 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF20:1; /**< \brief [20:20] Debug flag for alarm 20 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF21:1; /**< \brief [21:21] Debug flag for alarm 21 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF22:1; /**< \brief [22:22] Debug flag for alarm 22 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF23:1; /**< \brief [23:23] Debug flag for alarm 23 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF24:1; /**< \brief [24:24] Debug flag for alarm 24 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF25:1; /**< \brief [25:25] Debug flag for alarm 25 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF26:1; /**< \brief [26:26] Debug flag for alarm 26 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF27:1; /**< \brief [27:27] Debug flag for alarm 27 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF28:1; /**< \brief [28:28] Debug flag for alarm 28 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF29:1; /**< \brief [29:29] Debug flag for alarm 29 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF30:1; /**< \brief [30:30] Debug flag for alarm 30 belonging to alarm group x (x=0-6). (rh) */
+ Ifx_Strict_32Bit DF31:1; /**< \brief [31:31] Debug flag for alarm 31 belonging to alarm group x (x=0-6). (rh) */
+} Ifx_SMU_AD_Bits;
+
+/** \brief Alarm and Fault Counter */
+typedef struct _Ifx_SMU_AFCNT_Bits
+{
+ Ifx_Strict_32Bit FCNT:4; /**< \brief [3:0] Fault Counter. (rh) */
+ Ifx_Strict_32Bit reserved_4:4; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit ACNT:8; /**< \brief [15:8] Alarm Counter. (rh) */
+ Ifx_Strict_32Bit reserved_16:14; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit FCO:1; /**< \brief [30:30] Fault Counter Overflow. (rh) */
+ Ifx_Strict_32Bit ACO:1; /**< \brief [31:31] Alarm Counter Overflow. (rh) */
+} Ifx_SMU_AFCNT_Bits;
+
+/** \brief Alarm Status Register */
+typedef struct _Ifx_SMU_AG_Bits
+{
+ Ifx_Strict_32Bit SF0:1; /**< \brief [0:0] Status flag for alarm 0 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF1:1; /**< \brief [1:1] Status flag for alarm 1 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF2:1; /**< \brief [2:2] Status flag for alarm 2 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF3:1; /**< \brief [3:3] Status flag for alarm 3 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF4:1; /**< \brief [4:4] Status flag for alarm 4 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF5:1; /**< \brief [5:5] Status flag for alarm 5 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF6:1; /**< \brief [6:6] Status flag for alarm 6 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF7:1; /**< \brief [7:7] Status flag for alarm 7 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF8:1; /**< \brief [8:8] Status flag for alarm 8 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF9:1; /**< \brief [9:9] Status flag for alarm 9 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF10:1; /**< \brief [10:10] Status flag for alarm 10 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF11:1; /**< \brief [11:11] Status flag for alarm 11 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF12:1; /**< \brief [12:12] Status flag for alarm 12 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF13:1; /**< \brief [13:13] Status flag for alarm 13 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF14:1; /**< \brief [14:14] Status flag for alarm 14 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF15:1; /**< \brief [15:15] Status flag for alarm 15 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF16:1; /**< \brief [16:16] Status flag for alarm 16 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF17:1; /**< \brief [17:17] Status flag for alarm 17 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF18:1; /**< \brief [18:18] Status flag for alarm 18 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF19:1; /**< \brief [19:19] Status flag for alarm 19 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF20:1; /**< \brief [20:20] Status flag for alarm 20 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF21:1; /**< \brief [21:21] Status flag for alarm 21 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF22:1; /**< \brief [22:22] Status flag for alarm 22 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF23:1; /**< \brief [23:23] Status flag for alarm 23 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF24:1; /**< \brief [24:24] Status flag for alarm 24 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF25:1; /**< \brief [25:25] Status flag for alarm 25 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF26:1; /**< \brief [26:26] Status flag for alarm 26 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF27:1; /**< \brief [27:27] Status flag for alarm 27 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF28:1; /**< \brief [28:28] Status flag for alarm 28 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF29:1; /**< \brief [29:29] Status flag for alarm 29 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF30:1; /**< \brief [30:30] Status flag for alarm 30 belonging to alarm group x (x=0-6). (rwh) */
+ Ifx_Strict_32Bit SF31:1; /**< \brief [31:31] Status flag for alarm 31 belonging to alarm group x (x=0-6). (rwh) */
+} Ifx_SMU_AG_Bits;
+
+/** \brief Alarm Global Configuration */
+typedef struct _Ifx_SMU_AGC_Bits
+{
+ Ifx_Strict_32Bit IGCS0:3; /**< \brief [2:0] Interrupt Generation Configuration Set 0 (rw) */
+ Ifx_Strict_32Bit reserved_3:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit IGCS1:3; /**< \brief [6:4] Interrupt Generation Configuration Set 1 (rw) */
+ Ifx_Strict_32Bit reserved_7:1; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit IGCS2:3; /**< \brief [10:8] Interrupt Generation Configuration Set 2 (rw) */
+ Ifx_Strict_32Bit reserved_11:5; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit ICS:3; /**< \brief [18:16] Idle Configuration Set (rw) */
+ Ifx_Strict_32Bit reserved_19:5; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit PES:5; /**< \brief [28:24] Port Emergency Stop (rw) */
+ Ifx_Strict_32Bit EFRST:1; /**< \brief [29:29] Enable FAULT to RUN State Transition (rw) */
+ Ifx_Strict_32Bit reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_SMU_AGC_Bits;
+
+/** \brief Alarm Configuration Register */
+typedef struct _Ifx_SMU_AGCF_Bits
+{
+ Ifx_Strict_32Bit CF0:1; /**< \brief [0:0] (rw) */
+ Ifx_Strict_32Bit CF1:1; /**< \brief [1:1] (rw) */
+ Ifx_Strict_32Bit CF2:1; /**< \brief [2:2] (rw) */
+ Ifx_Strict_32Bit CF3:1; /**< \brief [3:3] (rw) */
+ Ifx_Strict_32Bit CF4:1; /**< \brief [4:4] (rw) */
+ Ifx_Strict_32Bit CF5:1; /**< \brief [5:5] (rw) */
+ Ifx_Strict_32Bit CF6:1; /**< \brief [6:6] (rw) */
+ Ifx_Strict_32Bit CF7:1; /**< \brief [7:7] (rw) */
+ Ifx_Strict_32Bit CF8:1; /**< \brief [8:8] (rw) */
+ Ifx_Strict_32Bit CF9:1; /**< \brief [9:9] (rw) */
+ Ifx_Strict_32Bit CF10:1; /**< \brief [10:10] (rw) */
+ Ifx_Strict_32Bit CF11:1; /**< \brief [11:11] (rw) */
+ Ifx_Strict_32Bit CF12:1; /**< \brief [12:12] (rw) */
+ Ifx_Strict_32Bit CF13:1; /**< \brief [13:13] (rw) */
+ Ifx_Strict_32Bit CF14:1; /**< \brief [14:14] (rw) */
+ Ifx_Strict_32Bit CF15:1; /**< \brief [15:15] (rw) */
+ Ifx_Strict_32Bit CF16:1; /**< \brief [16:16] (rw) */
+ Ifx_Strict_32Bit CF17:1; /**< \brief [17:17] (rw) */
+ Ifx_Strict_32Bit CF18:1; /**< \brief [18:18] (rw) */
+ Ifx_Strict_32Bit CF19:1; /**< \brief [19:19] (rw) */
+ Ifx_Strict_32Bit CF20:1; /**< \brief [20:20] (rw) */
+ Ifx_Strict_32Bit CF21:1; /**< \brief [21:21] (rw) */
+ Ifx_Strict_32Bit CF22:1; /**< \brief [22:22] (rw) */
+ Ifx_Strict_32Bit CF23:1; /**< \brief [23:23] (rw) */
+ Ifx_Strict_32Bit CF24:1; /**< \brief [24:24] (rw) */
+ Ifx_Strict_32Bit CF25:1; /**< \brief [25:25] (rw) */
+ Ifx_Strict_32Bit CF26:1; /**< \brief [26:26] (rw) */
+ Ifx_Strict_32Bit CF27:1; /**< \brief [27:27] (rw) */
+ Ifx_Strict_32Bit CF28:1; /**< \brief [28:28] (rw) */
+ Ifx_Strict_32Bit CF29:1; /**< \brief [29:29] (rw) */
+ Ifx_Strict_32Bit CF30:1; /**< \brief [30:30] (rw) */
+ Ifx_Strict_32Bit CF31:1; /**< \brief [31:31] (rw) */
+} Ifx_SMU_AGCF_Bits;
+
+/** \brief FSP Configuration Register */
+typedef struct _Ifx_SMU_AGFSP_Bits
+{
+ Ifx_Strict_32Bit FE0:1; /**< \brief [0:0] (rw) */
+ Ifx_Strict_32Bit FE1:1; /**< \brief [1:1] (rw) */
+ Ifx_Strict_32Bit FE2:1; /**< \brief [2:2] (rw) */
+ Ifx_Strict_32Bit FE3:1; /**< \brief [3:3] (rw) */
+ Ifx_Strict_32Bit FE4:1; /**< \brief [4:4] (rw) */
+ Ifx_Strict_32Bit FE5:1; /**< \brief [5:5] (rw) */
+ Ifx_Strict_32Bit FE6:1; /**< \brief [6:6] (rw) */
+ Ifx_Strict_32Bit FE7:1; /**< \brief [7:7] (rw) */
+ Ifx_Strict_32Bit FE8:1; /**< \brief [8:8] (rw) */
+ Ifx_Strict_32Bit FE9:1; /**< \brief [9:9] (rw) */
+ Ifx_Strict_32Bit FE10:1; /**< \brief [10:10] (rw) */
+ Ifx_Strict_32Bit FE11:1; /**< \brief [11:11] (rw) */
+ Ifx_Strict_32Bit FE12:1; /**< \brief [12:12] (rw) */
+ Ifx_Strict_32Bit FE13:1; /**< \brief [13:13] (rw) */
+ Ifx_Strict_32Bit FE14:1; /**< \brief [14:14] (rw) */
+ Ifx_Strict_32Bit FE15:1; /**< \brief [15:15] (rw) */
+ Ifx_Strict_32Bit FE16:1; /**< \brief [16:16] (rw) */
+ Ifx_Strict_32Bit FE17:1; /**< \brief [17:17] (rw) */
+ Ifx_Strict_32Bit FE18:1; /**< \brief [18:18] (rw) */
+ Ifx_Strict_32Bit FE19:1; /**< \brief [19:19] (rw) */
+ Ifx_Strict_32Bit FE20:1; /**< \brief [20:20] (rw) */
+ Ifx_Strict_32Bit FE21:1; /**< \brief [21:21] (rw) */
+ Ifx_Strict_32Bit FE22:1; /**< \brief [22:22] (rw) */
+ Ifx_Strict_32Bit FE23:1; /**< \brief [23:23] (rw) */
+ Ifx_Strict_32Bit FE24:1; /**< \brief [24:24] (rw) */
+ Ifx_Strict_32Bit FE25:1; /**< \brief [25:25] (rw) */
+ Ifx_Strict_32Bit FE26:1; /**< \brief [26:26] (rw) */
+ Ifx_Strict_32Bit FE27:1; /**< \brief [27:27] (rw) */
+ Ifx_Strict_32Bit FE28:1; /**< \brief [28:28] (rw) */
+ Ifx_Strict_32Bit FE29:1; /**< \brief [29:29] (rw) */
+ Ifx_Strict_32Bit FE30:1; /**< \brief [30:30] (rw) */
+ Ifx_Strict_32Bit FE31:1; /**< \brief [31:31] (rw) */
+} Ifx_SMU_AGFSP_Bits;
+
+/** \brief Clock Control Register */
+typedef struct _Ifx_SMU_CLC_Bits
+{
+ Ifx_Strict_32Bit DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
+ Ifx_Strict_32Bit DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
+ Ifx_Strict_32Bit FDIS:1; /**< \brief [2:2] Force Disable (rw) */
+ Ifx_Strict_32Bit EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control (rw) */
+ Ifx_Strict_32Bit reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_SMU_CLC_Bits;
+
+/** \brief Command Register */
+typedef struct _Ifx_SMU_CMD_Bits
+{
+ Ifx_Strict_32Bit CMD:4; /**< \brief [3:0] Implements the SMU Command Interface. (w) */
+ Ifx_Strict_32Bit ARG:4; /**< \brief [7:4] Implements the SMU Command Interface. (w) */
+ Ifx_Strict_32Bit reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_SMU_CMD_Bits;
+
+/** \brief Debug Register */
+typedef struct _Ifx_SMU_DBG_Bits
+{
+ Ifx_Strict_32Bit SSM:2; /**< \brief [1:0] Running state of the SMU State Machine (rh) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_SMU_DBG_Bits;
+
+/** \brief Fault Signaling Protocol */
+typedef struct _Ifx_SMU_FSP_Bits
+{
+ Ifx_Strict_32Bit PRE1:3; /**< \brief [2:0] Prescaler1 (rw) */
+ Ifx_Strict_32Bit PRE2:2; /**< \brief [4:3] Prescaler2 (rw) */
+ Ifx_Strict_32Bit MODE:2; /**< \brief [6:5] Fault Signaling Protocol configuration (rw) */
+ Ifx_Strict_32Bit PES:1; /**< \brief [7:7] Port Emergency Stop (PES) (rw) */
+ Ifx_Strict_32Bit TFSP_LOW:14; /**< \brief [21:8] Specifies the FSP fault state duration (r) */
+ Ifx_Strict_32Bit TFSP_HIGH:10; /**< \brief [31:22] Specifies the FSP fault state duration (rw) */
+} Ifx_SMU_FSP_Bits;
+
+/** \brief Module Identification Register */
+typedef struct _Ifx_SMU_ID_Bits
+{
+ Ifx_Strict_32Bit MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ Ifx_Strict_32Bit MODTYPE:8; /**< \brief [15:8] Module Type (r) */
+ Ifx_Strict_32Bit MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_SMU_ID_Bits;
+
+/** \brief Key Register */
+typedef struct _Ifx_SMU_KEYS_Bits
+{
+ Ifx_Strict_32Bit CFGLCK:8; /**< \brief [7:0] Configuration Lock (rw) */
+ Ifx_Strict_32Bit PERLCK:8; /**< \brief [15:8] Permanent Lock (rw) */
+ Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_SMU_KEYS_Bits;
+
+/** \brief SMU Reset Register 0 */
+typedef struct _Ifx_SMU_KRST0_Bits
+{
+ Ifx_Strict_32Bit RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ Ifx_Strict_32Bit RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rh) */
+ Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_SMU_KRST0_Bits;
+
+/** \brief SMU Reset Register 1 */
+typedef struct _Ifx_SMU_KRST1_Bits
+{
+ Ifx_Strict_32Bit RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ Ifx_Strict_32Bit reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_SMU_KRST1_Bits;
+
+/** \brief SMU Reset Status Clear Register */
+typedef struct _Ifx_SMU_KRSTCLR_Bits
+{
+ Ifx_Strict_32Bit CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
+ Ifx_Strict_32Bit reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_SMU_KRSTCLR_Bits;
+
+/** \brief OCDS Control and Status */
+typedef struct _Ifx_SMU_OCS_Bits
+{
+ Ifx_Strict_32Bit TGS:2; /**< \brief [1:0] Trigger Set for OTGB0/1 (rw) */
+ Ifx_Strict_32Bit TGB:1; /**< \brief [2:2] OTGB0/1 Bus Select (rw) */
+ Ifx_Strict_32Bit TG_P:1; /**< \brief [3:3] TGS, TGB Write Protection (w) */
+ Ifx_Strict_32Bit reserved_4:20; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit SUS:4; /**< \brief [27:24] OCDS Suspend Control (rw) */
+ Ifx_Strict_32Bit SUS_P:1; /**< \brief [28:28] SUS Write Protection (w) */
+ Ifx_Strict_32Bit SUSSTA:1; /**< \brief [29:29] Suspend State (rh) */
+ Ifx_Strict_32Bit reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_SMU_OCS_Bits;
+
+/** \brief Port Control */
+typedef struct _Ifx_SMU_PCTL_Bits
+{
+ Ifx_Strict_32Bit HWDIR:1; /**< \brief [0:0] Port Direction. (rw) */
+ Ifx_Strict_32Bit HWEN:1; /**< \brief [1:1] Port Enable. (rw) */
+ Ifx_Strict_32Bit reserved_2:5; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit PCS:1; /**< \brief [7:7] PAD Configuration Select (rw) */
+ Ifx_Strict_32Bit reserved_8:8; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit PCFG:16; /**< \brief [31:16] PAD Configuration (rh) */
+} Ifx_SMU_PCTL_Bits;
+
+/** \brief Register Monitor Control */
+typedef struct _Ifx_SMU_RMCTL_Bits
+{
+ Ifx_Strict_32Bit TE:1; /**< \brief [0:0] Test Enable. (rw) */
+ Ifx_Strict_32Bit reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_SMU_RMCTL_Bits;
+
+/** \brief Register Monitor Error Flags */
+typedef struct _Ifx_SMU_RMEF_Bits
+{
+ Ifx_Strict_32Bit EF0:1; /**< \brief [0:0] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF1:1; /**< \brief [1:1] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF2:1; /**< \brief [2:2] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF3:1; /**< \brief [3:3] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF4:1; /**< \brief [4:4] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF5:1; /**< \brief [5:5] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF6:1; /**< \brief [6:6] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF7:1; /**< \brief [7:7] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF8:1; /**< \brief [8:8] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF9:1; /**< \brief [9:9] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF10:1; /**< \brief [10:10] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF11:1; /**< \brief [11:11] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF12:1; /**< \brief [12:12] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF13:1; /**< \brief [13:13] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF14:1; /**< \brief [14:14] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF15:1; /**< \brief [15:15] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF16:1; /**< \brief [16:16] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF17:1; /**< \brief [17:17] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF18:1; /**< \brief [18:18] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF19:1; /**< \brief [19:19] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF20:1; /**< \brief [20:20] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF21:1; /**< \brief [21:21] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF22:1; /**< \brief [22:22] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF23:1; /**< \brief [23:23] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF24:1; /**< \brief [24:24] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF25:1; /**< \brief [25:25] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF26:1; /**< \brief [26:26] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF27:1; /**< \brief [27:27] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF28:1; /**< \brief [28:28] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF29:1; /**< \brief [29:29] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF30:1; /**< \brief [30:30] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit EF31:1; /**< \brief [31:31] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+} Ifx_SMU_RMEF_Bits;
+
+/** \brief Register Monitor Self Test Status */
+typedef struct _Ifx_SMU_RMSTS_Bits
+{
+ Ifx_Strict_32Bit STS0:1; /**< \brief [0:0] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS1:1; /**< \brief [1:1] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS2:1; /**< \brief [2:2] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS3:1; /**< \brief [3:3] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS4:1; /**< \brief [4:4] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS5:1; /**< \brief [5:5] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS6:1; /**< \brief [6:6] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS7:1; /**< \brief [7:7] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS8:1; /**< \brief [8:8] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS9:1; /**< \brief [9:9] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS10:1; /**< \brief [10:10] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS11:1; /**< \brief [11:11] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS12:1; /**< \brief [12:12] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS13:1; /**< \brief [13:13] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS14:1; /**< \brief [14:14] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS15:1; /**< \brief [15:15] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS16:1; /**< \brief [16:16] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS17:1; /**< \brief [17:17] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS18:1; /**< \brief [18:18] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS19:1; /**< \brief [19:19] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS20:1; /**< \brief [20:20] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS21:1; /**< \brief [21:21] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS22:1; /**< \brief [22:22] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS23:1; /**< \brief [23:23] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS24:1; /**< \brief [24:24] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS25:1; /**< \brief [25:25] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS26:1; /**< \brief [26:26] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS27:1; /**< \brief [27:27] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS28:1; /**< \brief [28:28] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS29:1; /**< \brief [29:29] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS30:1; /**< \brief [30:30] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+ Ifx_Strict_32Bit STS31:1; /**< \brief [31:31] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+} Ifx_SMU_RMSTS_Bits;
+
+/** \brief Recovery Timer Alarm Configuration */
+typedef struct _Ifx_SMU_RTAC0_Bits
+{
+ Ifx_Strict_32Bit GID0:3; /**< \brief [2:0] Group Index 0. (rw) */
+ Ifx_Strict_32Bit ALID0:5; /**< \brief [7:3] Alarm Identifier 0. (rw) */
+ Ifx_Strict_32Bit GID1:3; /**< \brief [10:8] Group Index 1. (rw) */
+ Ifx_Strict_32Bit ALID1:5; /**< \brief [15:11] Alarm Identifier 1. (rw) */
+ Ifx_Strict_32Bit GID2:3; /**< \brief [18:16] Group Index 2. (rw) */
+ Ifx_Strict_32Bit ALID2:5; /**< \brief [23:19] Alarm Identifier 2. (rw) */
+ Ifx_Strict_32Bit GID3:3; /**< \brief [26:24] Group Index 3. (rw) */
+ Ifx_Strict_32Bit ALID3:5; /**< \brief [31:27] Alarm Identifier 3. (rw) */
+} Ifx_SMU_RTAC0_Bits;
+
+/** \brief Recovery Timer Alarm Configuration */
+typedef struct _Ifx_SMU_RTAC1_Bits
+{
+ Ifx_Strict_32Bit GID0:3; /**< \brief [2:0] Group Index 0. (rw) */
+ Ifx_Strict_32Bit ALID0:5; /**< \brief [7:3] Alarm Identifier 0. (rw) */
+ Ifx_Strict_32Bit GID1:3; /**< \brief [10:8] Group Index 1. (rw) */
+ Ifx_Strict_32Bit ALID1:5; /**< \brief [15:11] Alarm Identifier 1. (rw) */
+ Ifx_Strict_32Bit GID2:3; /**< \brief [18:16] Group Index 2. (rw) */
+ Ifx_Strict_32Bit ALID2:5; /**< \brief [23:19] Alarm Identifier 2. (rw) */
+ Ifx_Strict_32Bit GID3:3; /**< \brief [26:24] Group Index 3. (rw) */
+ Ifx_Strict_32Bit ALID3:5; /**< \brief [31:27] Alarm Identifier 3. (rw) */
+} Ifx_SMU_RTAC1_Bits;
+
+/** \brief Fault Signaling Protocol */
+typedef struct _Ifx_SMU_RTC_Bits
+{
+ Ifx_Strict_32Bit RT0E:1; /**< \brief [0:0] RT0 Enable Bit (rw) */
+ Ifx_Strict_32Bit RT1E:1; /**< \brief [1:1] RT1 Enable Bit (rw) */
+ Ifx_Strict_32Bit reserved_2:6; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit RTD:24; /**< \brief [31:8] Recovery Timer Duration (rw) */
+} Ifx_SMU_RTC_Bits;
+
+/** \brief Status Register */
+typedef struct _Ifx_SMU_STS_Bits
+{
+ Ifx_Strict_32Bit CMD:4; /**< \brief [3:0] Last command received (rwh) */
+ Ifx_Strict_32Bit ARG:4; /**< \brief [7:4] Last command argument received (rwh) */
+ Ifx_Strict_32Bit RES:1; /**< \brief [8:8] Result of last received command (rwh) */
+ Ifx_Strict_32Bit ASCE:1; /**< \brief [9:9] Alarm Status Clear Enable (rwh) */
+ Ifx_Strict_32Bit FSP:2; /**< \brief [11:10] Fault Signaling Protocol status (rh) */
+ Ifx_Strict_32Bit FSTS:1; /**< \brief [12:12] Fault State Timing Status (rwh) */
+ Ifx_Strict_32Bit reserved_13:3; /**< \brief \internal Reserved */
+ Ifx_Strict_32Bit RTS0:1; /**< \brief [16:16] Recovery Timer 0 Status (rwh) */
+ Ifx_Strict_32Bit RTME0:1; /**< \brief [17:17] Recovery Timer 0 Missed Event (rwh) */
+ Ifx_Strict_32Bit RTS1:1; /**< \brief [18:18] Recovery Timer 1 Status (rwh) */
+ Ifx_Strict_32Bit RTME1:1; /**< \brief [19:19] Recovery Timer 1 Missed Event (rwh) */
+ Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_SMU_STS_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Smu_union
+ * \{ */
+
+/** \brief SMU Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SMU_ACCEN0_Bits B; /**< \brief Bitfield access */
+} Ifx_SMU_ACCEN0;
+
+/** \brief SMU Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SMU_ACCEN1_Bits B; /**< \brief Bitfield access */
+} Ifx_SMU_ACCEN1;
+
+/** \brief Alarm Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SMU_AD_Bits B; /**< \brief Bitfield access */
+} Ifx_SMU_AD;
+
+/** \brief Alarm and Fault Counter */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SMU_AFCNT_Bits B; /**< \brief Bitfield access */
+} Ifx_SMU_AFCNT;
+
+/** \brief Alarm Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SMU_AG_Bits B; /**< \brief Bitfield access */
+} Ifx_SMU_AG;
+
+/** \brief Alarm Global Configuration */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SMU_AGC_Bits B; /**< \brief Bitfield access */
+} Ifx_SMU_AGC;
+
+/** \brief Alarm Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SMU_AGCF_Bits B; /**< \brief Bitfield access */
+} Ifx_SMU_AGCF;
+
+/** \brief FSP Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SMU_AGFSP_Bits B; /**< \brief Bitfield access */
+} Ifx_SMU_AGFSP;
+
+/** \brief Clock Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SMU_CLC_Bits B; /**< \brief Bitfield access */
+} Ifx_SMU_CLC;
+
+/** \brief Command Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SMU_CMD_Bits B; /**< \brief Bitfield access */
+} Ifx_SMU_CMD;
+
+/** \brief Debug Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SMU_DBG_Bits B; /**< \brief Bitfield access */
+} Ifx_SMU_DBG;
+
+/** \brief Fault Signaling Protocol */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SMU_FSP_Bits B; /**< \brief Bitfield access */
+} Ifx_SMU_FSP;
+
+/** \brief Module Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SMU_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_SMU_ID;
+
+/** \brief Key Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SMU_KEYS_Bits B; /**< \brief Bitfield access */
+} Ifx_SMU_KEYS;
+
+/** \brief SMU Reset Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SMU_KRST0_Bits B; /**< \brief Bitfield access */
+} Ifx_SMU_KRST0;
+
+/** \brief SMU Reset Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SMU_KRST1_Bits B; /**< \brief Bitfield access */
+} Ifx_SMU_KRST1;
+
+/** \brief SMU Reset Status Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SMU_KRSTCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_SMU_KRSTCLR;
+
+/** \brief OCDS Control and Status */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SMU_OCS_Bits B; /**< \brief Bitfield access */
+} Ifx_SMU_OCS;
+
+/** \brief Port Control */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SMU_PCTL_Bits B; /**< \brief Bitfield access */
+} Ifx_SMU_PCTL;
+
+/** \brief Register Monitor Control */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SMU_RMCTL_Bits B; /**< \brief Bitfield access */
+} Ifx_SMU_RMCTL;
+
+/** \brief Register Monitor Error Flags */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SMU_RMEF_Bits B; /**< \brief Bitfield access */
+} Ifx_SMU_RMEF;
+
+/** \brief Register Monitor Self Test Status */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SMU_RMSTS_Bits B; /**< \brief Bitfield access */
+} Ifx_SMU_RMSTS;
+
+/** \brief Recovery Timer Alarm Configuration */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SMU_RTAC0_Bits B; /**< \brief Bitfield access */
+} Ifx_SMU_RTAC0;
+
+/** \brief Recovery Timer Alarm Configuration */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SMU_RTAC1_Bits B; /**< \brief Bitfield access */
+} Ifx_SMU_RTAC1;
+
+/** \brief Fault Signaling Protocol */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SMU_RTC_Bits B; /**< \brief Bitfield access */
+} Ifx_SMU_RTC;
+
+/** \brief Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SMU_STS_Bits B; /**< \brief Bitfield access */
+} Ifx_SMU_STS;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Smu_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief SMU object */
+typedef volatile struct _Ifx_SMU
+{
+ Ifx_SMU_CLC CLC; /**< \brief 0, Clock Control Register */
+ unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
+ Ifx_SMU_ID ID; /**< \brief 8, Module Identification Register */
+ unsigned char reserved_C[20]; /**< \brief C, \internal Reserved */
+ Ifx_SMU_CMD CMD; /**< \brief 20, Command Register */
+ Ifx_SMU_STS STS; /**< \brief 24, Status Register */
+ Ifx_SMU_FSP FSP; /**< \brief 28, Fault Signaling Protocol */
+ Ifx_SMU_AGC AGC; /**< \brief 2C, Alarm Global Configuration */
+ Ifx_SMU_RTC RTC; /**< \brief 30, Fault Signaling Protocol */
+ Ifx_SMU_KEYS KEYS; /**< \brief 34, Key Register */
+ Ifx_SMU_DBG DBG; /**< \brief 38, Debug Register */
+ Ifx_SMU_PCTL PCTL; /**< \brief 3C, Port Control */
+ Ifx_SMU_AFCNT AFCNT; /**< \brief 40, Alarm and Fault Counter */
+ unsigned char reserved_44[28]; /**< \brief 44, \internal Reserved */
+ Ifx_SMU_RTAC0 RTAC0; /**< \brief 60, Recovery Timer Alarm Configuration */
+ Ifx_SMU_RTAC1 RTAC1; /**< \brief 64, Recovery Timer Alarm Configuration */
+ unsigned char reserved_68[152]; /**< \brief 68, \internal Reserved */
+ Ifx_SMU_AGCF AGCF[7][3]; /**< \brief 100, Alarm Configuration Register */
+ unsigned char reserved_154[44]; /**< \brief 154, \internal Reserved */
+ Ifx_SMU_AGFSP AGFSP[7]; /**< \brief 180, FSP Configuration Register */
+ unsigned char reserved_19C[36]; /**< \brief 19C, \internal Reserved */
+ Ifx_SMU_AG AG[7]; /**< \brief 1C0, Alarm Status Register */
+ unsigned char reserved_1DC[36]; /**< \brief 1DC, \internal Reserved */
+ Ifx_SMU_AD AD[7]; /**< \brief 200, Alarm Status Register */
+ unsigned char reserved_21C[228]; /**< \brief 21C, \internal Reserved */
+ Ifx_SMU_RMCTL RMCTL; /**< \brief 300, Register Monitor Control */
+ Ifx_SMU_RMEF RMEF; /**< \brief 304, Register Monitor Error Flags */
+ Ifx_SMU_RMSTS RMSTS; /**< \brief 308, Register Monitor Self Test Status */
+ unsigned char reserved_30C[1244]; /**< \brief 30C, \internal Reserved */
+ Ifx_SMU_OCS OCS; /**< \brief 7E8, OCDS Control and Status */
+ Ifx_SMU_KRSTCLR KRSTCLR; /**< \brief 7EC, SMU Reset Status Clear Register */
+ Ifx_SMU_KRST1 KRST1; /**< \brief 7F0, SMU Reset Register 1 */
+ Ifx_SMU_KRST0 KRST0; /**< \brief 7F4, SMU Reset Register 0 */
+ Ifx_SMU_ACCEN1 ACCEN1; /**< \brief 7F8, SMU Access Enable Register 1 */
+ Ifx_SMU_ACCEN0 ACCEN0; /**< \brief 7FC, SMU Access Enable Register 0 */
+} Ifx_SMU;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXSMU_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSrc_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSrc_bf.h
new file mode 100644
index 0000000..ee45a16
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSrc_bf.h
@@ -0,0 +1,135 @@
+/**
+ * \file IfxSrc_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Src_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Src
+ *
+ */
+#ifndef IFXSRC_BF_H
+#define IFXSRC_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Src_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_SRC_SRCR_Bits.CLRR */
+#define IFX_SRC_SRCR_CLRR_LEN (1u)
+
+/** \brief Mask for Ifx_SRC_SRCR_Bits.CLRR */
+#define IFX_SRC_SRCR_CLRR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SRC_SRCR_Bits.CLRR */
+#define IFX_SRC_SRCR_CLRR_OFF (25u)
+
+/** \brief Length for Ifx_SRC_SRCR_Bits.ECC */
+#define IFX_SRC_SRCR_ECC_LEN (6u)
+
+/** \brief Mask for Ifx_SRC_SRCR_Bits.ECC */
+#define IFX_SRC_SRCR_ECC_MSK (0x3fu)
+
+/** \brief Offset for Ifx_SRC_SRCR_Bits.ECC */
+#define IFX_SRC_SRCR_ECC_OFF (16u)
+
+/** \brief Length for Ifx_SRC_SRCR_Bits.IOV */
+#define IFX_SRC_SRCR_IOV_LEN (1u)
+
+/** \brief Mask for Ifx_SRC_SRCR_Bits.IOV */
+#define IFX_SRC_SRCR_IOV_MSK (0x1u)
+
+/** \brief Offset for Ifx_SRC_SRCR_Bits.IOV */
+#define IFX_SRC_SRCR_IOV_OFF (27u)
+
+/** \brief Length for Ifx_SRC_SRCR_Bits.IOVCLR */
+#define IFX_SRC_SRCR_IOVCLR_LEN (1u)
+
+/** \brief Mask for Ifx_SRC_SRCR_Bits.IOVCLR */
+#define IFX_SRC_SRCR_IOVCLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SRC_SRCR_Bits.IOVCLR */
+#define IFX_SRC_SRCR_IOVCLR_OFF (28u)
+
+/** \brief Length for Ifx_SRC_SRCR_Bits.SETR */
+#define IFX_SRC_SRCR_SETR_LEN (1u)
+
+/** \brief Mask for Ifx_SRC_SRCR_Bits.SETR */
+#define IFX_SRC_SRCR_SETR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SRC_SRCR_Bits.SETR */
+#define IFX_SRC_SRCR_SETR_OFF (26u)
+
+/** \brief Length for Ifx_SRC_SRCR_Bits.SRE */
+#define IFX_SRC_SRCR_SRE_LEN (1u)
+
+/** \brief Mask for Ifx_SRC_SRCR_Bits.SRE */
+#define IFX_SRC_SRCR_SRE_MSK (0x1u)
+
+/** \brief Offset for Ifx_SRC_SRCR_Bits.SRE */
+#define IFX_SRC_SRCR_SRE_OFF (10u)
+
+/** \brief Length for Ifx_SRC_SRCR_Bits.SRPN */
+#define IFX_SRC_SRCR_SRPN_LEN (8u)
+
+/** \brief Mask for Ifx_SRC_SRCR_Bits.SRPN */
+#define IFX_SRC_SRCR_SRPN_MSK (0xffu)
+
+/** \brief Offset for Ifx_SRC_SRCR_Bits.SRPN */
+#define IFX_SRC_SRCR_SRPN_OFF (0u)
+
+/** \brief Length for Ifx_SRC_SRCR_Bits.SRR */
+#define IFX_SRC_SRCR_SRR_LEN (1u)
+
+/** \brief Mask for Ifx_SRC_SRCR_Bits.SRR */
+#define IFX_SRC_SRCR_SRR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SRC_SRCR_Bits.SRR */
+#define IFX_SRC_SRCR_SRR_OFF (24u)
+
+/** \brief Length for Ifx_SRC_SRCR_Bits.SWS */
+#define IFX_SRC_SRCR_SWS_LEN (1u)
+
+/** \brief Mask for Ifx_SRC_SRCR_Bits.SWS */
+#define IFX_SRC_SRCR_SWS_MSK (0x1u)
+
+/** \brief Offset for Ifx_SRC_SRCR_Bits.SWS */
+#define IFX_SRC_SRCR_SWS_OFF (29u)
+
+/** \brief Length for Ifx_SRC_SRCR_Bits.SWSCLR */
+#define IFX_SRC_SRCR_SWSCLR_LEN (1u)
+
+/** \brief Mask for Ifx_SRC_SRCR_Bits.SWSCLR */
+#define IFX_SRC_SRCR_SWSCLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_SRC_SRCR_Bits.SWSCLR */
+#define IFX_SRC_SRCR_SWSCLR_OFF (30u)
+
+/** \brief Length for Ifx_SRC_SRCR_Bits.TOS */
+#define IFX_SRC_SRCR_TOS_LEN (2u)
+
+/** \brief Mask for Ifx_SRC_SRCR_Bits.TOS */
+#define IFX_SRC_SRCR_TOS_MSK (0x3u)
+
+/** \brief Offset for Ifx_SRC_SRCR_Bits.TOS */
+#define IFX_SRC_SRCR_TOS_OFF (11u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXSRC_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSrc_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSrc_reg.h
new file mode 100644
index 0000000..427ba6f
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSrc_reg.h
@@ -0,0 +1,3107 @@
+/**
+ * \file IfxSrc_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Src_Cfg Src address
+ * \ingroup IfxLld_Src
+ *
+ * \defgroup IfxLld_Src_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Src_Cfg
+ *
+ * \defgroup IfxLld_Src_Cfg_Src 2-SRC
+ * \ingroup IfxLld_Src_Cfg
+ *
+ */
+#ifndef IFXSRC_REG_H
+#define IFXSRC_REG_H 1
+/******************************************************************************/
+#include "IfxSrc_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Src_Cfg_BaseAddress
+ * \{ */
+
+/** \brief SRC object */
+#define MODULE_SRC /*lint --e(923)*/ (*(Ifx_SRC*)0xF0038000u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Src_Cfg_Src
+ * \{ */
+
+/** \brief 24, AGBT Service Request */
+#define SRC_AGBT_AGBT0_SR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038024u)
+
+/** Alias (User Manual Name) for SRC_AGBT_AGBT0_SR.
+* To use register names with standard convension, please use SRC_AGBT_AGBT0_SR.
+*/
+#define SRC_AGBT (SRC_AGBT_AGBT0_SR)
+
+/** \brief 88, ASCLIN Error Service Request */
+#define SRC_ASCLIN_ASCLIN0_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038088u)
+
+/** Alias (User Manual Name) for SRC_ASCLIN_ASCLIN0_ERR.
+* To use register names with standard convension, please use SRC_ASCLIN_ASCLIN0_ERR.
+*/
+#define SRC_ASCLIN0ERR (SRC_ASCLIN_ASCLIN0_ERR)
+
+/** \brief 84, ASCLIN Receive Service Request */
+#define SRC_ASCLIN_ASCLIN0_RX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038084u)
+
+/** Alias (User Manual Name) for SRC_ASCLIN_ASCLIN0_RX.
+* To use register names with standard convension, please use SRC_ASCLIN_ASCLIN0_RX.
+*/
+#define SRC_ASCLIN0RX (SRC_ASCLIN_ASCLIN0_RX)
+
+/** \brief 80, ASCLIN Transmit Service Request */
+#define SRC_ASCLIN_ASCLIN0_TX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038080u)
+
+/** Alias (User Manual Name) for SRC_ASCLIN_ASCLIN0_TX.
+* To use register names with standard convension, please use SRC_ASCLIN_ASCLIN0_TX.
+*/
+#define SRC_ASCLIN0TX (SRC_ASCLIN_ASCLIN0_TX)
+
+/** \brief 94, ASCLIN Error Service Request */
+#define SRC_ASCLIN_ASCLIN1_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038094u)
+
+/** Alias (User Manual Name) for SRC_ASCLIN_ASCLIN1_ERR.
+* To use register names with standard convension, please use SRC_ASCLIN_ASCLIN1_ERR.
+*/
+#define SRC_ASCLIN1ERR (SRC_ASCLIN_ASCLIN1_ERR)
+
+/** \brief 90, ASCLIN Receive Service Request */
+#define SRC_ASCLIN_ASCLIN1_RX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038090u)
+
+/** Alias (User Manual Name) for SRC_ASCLIN_ASCLIN1_RX.
+* To use register names with standard convension, please use SRC_ASCLIN_ASCLIN1_RX.
+*/
+#define SRC_ASCLIN1RX (SRC_ASCLIN_ASCLIN1_RX)
+
+/** \brief 8C, ASCLIN Transmit Service Request */
+#define SRC_ASCLIN_ASCLIN1_TX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003808Cu)
+
+/** Alias (User Manual Name) for SRC_ASCLIN_ASCLIN1_TX.
+* To use register names with standard convension, please use SRC_ASCLIN_ASCLIN1_TX.
+*/
+#define SRC_ASCLIN1TX (SRC_ASCLIN_ASCLIN1_TX)
+
+/** \brief A0, ASCLIN Error Service Request */
+#define SRC_ASCLIN_ASCLIN2_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00380A0u)
+
+/** Alias (User Manual Name) for SRC_ASCLIN_ASCLIN2_ERR.
+* To use register names with standard convension, please use SRC_ASCLIN_ASCLIN2_ERR.
+*/
+#define SRC_ASCLIN2ERR (SRC_ASCLIN_ASCLIN2_ERR)
+
+/** \brief 9C, ASCLIN Receive Service Request */
+#define SRC_ASCLIN_ASCLIN2_RX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003809Cu)
+
+/** Alias (User Manual Name) for SRC_ASCLIN_ASCLIN2_RX.
+* To use register names with standard convension, please use SRC_ASCLIN_ASCLIN2_RX.
+*/
+#define SRC_ASCLIN2RX (SRC_ASCLIN_ASCLIN2_RX)
+
+/** \brief 98, ASCLIN Transmit Service Request */
+#define SRC_ASCLIN_ASCLIN2_TX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038098u)
+
+/** Alias (User Manual Name) for SRC_ASCLIN_ASCLIN2_TX.
+* To use register names with standard convension, please use SRC_ASCLIN_ASCLIN2_TX.
+*/
+#define SRC_ASCLIN2TX (SRC_ASCLIN_ASCLIN2_TX)
+
+/** \brief AC, ASCLIN Error Service Request */
+#define SRC_ASCLIN_ASCLIN3_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00380ACu)
+
+/** Alias (User Manual Name) for SRC_ASCLIN_ASCLIN3_ERR.
+* To use register names with standard convension, please use SRC_ASCLIN_ASCLIN3_ERR.
+*/
+#define SRC_ASCLIN3ERR (SRC_ASCLIN_ASCLIN3_ERR)
+
+/** \brief A8, ASCLIN Receive Service Request */
+#define SRC_ASCLIN_ASCLIN3_RX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00380A8u)
+
+/** Alias (User Manual Name) for SRC_ASCLIN_ASCLIN3_RX.
+* To use register names with standard convension, please use SRC_ASCLIN_ASCLIN3_RX.
+*/
+#define SRC_ASCLIN3RX (SRC_ASCLIN_ASCLIN3_RX)
+
+/** \brief A4, ASCLIN Transmit Service Request */
+#define SRC_ASCLIN_ASCLIN3_TX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00380A4u)
+
+/** Alias (User Manual Name) for SRC_ASCLIN_ASCLIN3_TX.
+* To use register names with standard convension, please use SRC_ASCLIN_ASCLIN3_TX.
+*/
+#define SRC_ASCLIN3TX (SRC_ASCLIN_ASCLIN3_TX)
+
+/** \brief 40, Bus Control Unit SPB Service Request */
+#define SRC_BCU_SPB_SBSRC /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038040u)
+
+/** Alias (User Manual Name) for SRC_BCU_SPB_SBSRC.
+* To use register names with standard convension, please use SRC_BCU_SPB_SBSRC.
+*/
+#define SRC_BCUSPBSBSRC (SRC_BCU_SPB_SBSRC)
+
+/** \brief 900, MULTICAN+ Service Request */
+#define SRC_CAN_CAN0_INT0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038900u)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT0.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT0.
+*/
+#define SRC_CANINT0 (SRC_CAN_CAN0_INT0)
+
+/** \brief 904, MULTICAN+ Service Request */
+#define SRC_CAN_CAN0_INT1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038904u)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT1.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT1.
+*/
+#define SRC_CANINT1 (SRC_CAN_CAN0_INT1)
+
+/** \brief 928, MULTICAN+ Service Request */
+#define SRC_CAN_CAN0_INT10 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038928u)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT10.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT10.
+*/
+#define SRC_CANINT10 (SRC_CAN_CAN0_INT10)
+
+/** \brief 92C, MULTICAN+ Service Request */
+#define SRC_CAN_CAN0_INT11 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003892Cu)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT11.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT11.
+*/
+#define SRC_CANINT11 (SRC_CAN_CAN0_INT11)
+
+/** \brief 930, MULTICAN+ Service Request */
+#define SRC_CAN_CAN0_INT12 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038930u)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT12.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT12.
+*/
+#define SRC_CANINT12 (SRC_CAN_CAN0_INT12)
+
+/** \brief 934, MULTICAN+ Service Request */
+#define SRC_CAN_CAN0_INT13 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038934u)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT13.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT13.
+*/
+#define SRC_CANINT13 (SRC_CAN_CAN0_INT13)
+
+/** \brief 938, MULTICAN+ Service Request */
+#define SRC_CAN_CAN0_INT14 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038938u)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT14.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT14.
+*/
+#define SRC_CANINT14 (SRC_CAN_CAN0_INT14)
+
+/** \brief 93C, MULTICAN+ Service Request */
+#define SRC_CAN_CAN0_INT15 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003893Cu)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT15.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT15.
+*/
+#define SRC_CANINT15 (SRC_CAN_CAN0_INT15)
+
+/** \brief 908, MULTICAN+ Service Request */
+#define SRC_CAN_CAN0_INT2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038908u)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT2.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT2.
+*/
+#define SRC_CANINT2 (SRC_CAN_CAN0_INT2)
+
+/** \brief 90C, MULTICAN+ Service Request */
+#define SRC_CAN_CAN0_INT3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003890Cu)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT3.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT3.
+*/
+#define SRC_CANINT3 (SRC_CAN_CAN0_INT3)
+
+/** \brief 910, MULTICAN+ Service Request */
+#define SRC_CAN_CAN0_INT4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038910u)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT4.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT4.
+*/
+#define SRC_CANINT4 (SRC_CAN_CAN0_INT4)
+
+/** \brief 914, MULTICAN+ Service Request */
+#define SRC_CAN_CAN0_INT5 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038914u)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT5.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT5.
+*/
+#define SRC_CANINT5 (SRC_CAN_CAN0_INT5)
+
+/** \brief 918, MULTICAN+ Service Request */
+#define SRC_CAN_CAN0_INT6 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038918u)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT6.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT6.
+*/
+#define SRC_CANINT6 (SRC_CAN_CAN0_INT6)
+
+/** \brief 91C, MULTICAN+ Service Request */
+#define SRC_CAN_CAN0_INT7 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003891Cu)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT7.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT7.
+*/
+#define SRC_CANINT7 (SRC_CAN_CAN0_INT7)
+
+/** \brief 920, MULTICAN+ Service Request */
+#define SRC_CAN_CAN0_INT8 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038920u)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT8.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT8.
+*/
+#define SRC_CANINT8 (SRC_CAN_CAN0_INT8)
+
+/** \brief 924, MULTICAN+ Service Request */
+#define SRC_CAN_CAN0_INT9 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038924u)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT9.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT9.
+*/
+#define SRC_CANINT9 (SRC_CAN_CAN0_INT9)
+
+/** \brief 420, CCU6 Service Request 0 */
+#define SRC_CCU6_CCU60_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038420u)
+
+/** Alias (User Manual Name) for SRC_CCU6_CCU60_SR0.
+* To use register names with standard convension, please use SRC_CCU6_CCU60_SR0.
+*/
+#define SRC_CCU60SR0 (SRC_CCU6_CCU60_SR0)
+
+/** \brief 424, CCU6 Service Request 1 */
+#define SRC_CCU6_CCU60_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038424u)
+
+/** Alias (User Manual Name) for SRC_CCU6_CCU60_SR1.
+* To use register names with standard convension, please use SRC_CCU6_CCU60_SR1.
+*/
+#define SRC_CCU60SR1 (SRC_CCU6_CCU60_SR1)
+
+/** \brief 428, CCU6 Service Request 2 */
+#define SRC_CCU6_CCU60_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038428u)
+
+/** Alias (User Manual Name) for SRC_CCU6_CCU60_SR2.
+* To use register names with standard convension, please use SRC_CCU6_CCU60_SR2.
+*/
+#define SRC_CCU60SR2 (SRC_CCU6_CCU60_SR2)
+
+/** \brief 42C, CCU6 Service Request 3 */
+#define SRC_CCU6_CCU60_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003842Cu)
+
+/** Alias (User Manual Name) for SRC_CCU6_CCU60_SR3.
+* To use register names with standard convension, please use SRC_CCU6_CCU60_SR3.
+*/
+#define SRC_CCU60SR3 (SRC_CCU6_CCU60_SR3)
+
+/** \brief 430, CCU6 Service Request 0 */
+#define SRC_CCU6_CCU61_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038430u)
+
+/** Alias (User Manual Name) for SRC_CCU6_CCU61_SR0.
+* To use register names with standard convension, please use SRC_CCU6_CCU61_SR0.
+*/
+#define SRC_CCU61SR0 (SRC_CCU6_CCU61_SR0)
+
+/** \brief 434, CCU6 Service Request 1 */
+#define SRC_CCU6_CCU61_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038434u)
+
+/** Alias (User Manual Name) for SRC_CCU6_CCU61_SR1.
+* To use register names with standard convension, please use SRC_CCU6_CCU61_SR1.
+*/
+#define SRC_CCU61SR1 (SRC_CCU6_CCU61_SR1)
+
+/** \brief 438, CCU6 Service Request 2 */
+#define SRC_CCU6_CCU61_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038438u)
+
+/** Alias (User Manual Name) for SRC_CCU6_CCU61_SR2.
+* To use register names with standard convension, please use SRC_CCU6_CCU61_SR2.
+*/
+#define SRC_CCU61SR2 (SRC_CCU6_CCU61_SR2)
+
+/** \brief 43C, CCU6 Service Request 3 */
+#define SRC_CCU6_CCU61_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003843Cu)
+
+/** Alias (User Manual Name) for SRC_CCU6_CCU61_SR3.
+* To use register names with standard convension, please use SRC_CCU6_CCU61_SR3.
+*/
+#define SRC_CCU61SR3 (SRC_CCU6_CCU61_SR3)
+
+/** \brief 50, Cerberus Service Request */
+#define SRC_CERBERUS_CERBERUS_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038050u)
+
+/** Alias (User Manual Name) for SRC_CERBERUS_CERBERUS_SR0.
+* To use register names with standard convension, please use SRC_CERBERUS_CERBERUS_SR0.
+*/
+#define SRC_CERBERUS0 (SRC_CERBERUS_CERBERUS_SR0)
+
+/** \brief 54, Cerberus Service Request */
+#define SRC_CERBERUS_CERBERUS_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038054u)
+
+/** Alias (User Manual Name) for SRC_CERBERUS_CERBERUS_SR1.
+* To use register names with standard convension, please use SRC_CERBERUS_CERBERUS_SR1.
+*/
+#define SRC_CERBERUS1 (SRC_CERBERUS_CERBERUS_SR1)
+
+/** \brief DA8, CIF ISP Service Request */
+#define SRC_CIF_CIF0_ISP /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038DA8u)
+
+/** Alias (User Manual Name) for SRC_CIF_CIF0_ISP.
+* To use register names with standard convension, please use SRC_CIF_CIF0_ISP.
+*/
+#define SRC_CIFISP (SRC_CIF_CIF0_ISP)
+
+/** \brief DA0, CIF MI Service Request */
+#define SRC_CIF_CIF0_MI /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038DA0u)
+
+/** Alias (User Manual Name) for SRC_CIF_CIF0_MI.
+* To use register names with standard convension, please use SRC_CIF_CIF0_MI.
+*/
+#define SRC_CIFMI (SRC_CIF_CIF0_MI)
+
+/** \brief DA4, CIF MI EP Service Request */
+#define SRC_CIF_CIF0_MIEP /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038DA4u)
+
+/** Alias (User Manual Name) for SRC_CIF_CIF0_MIEP.
+* To use register names with standard convension, please use SRC_CIF_CIF0_MIEP.
+*/
+#define SRC_CIFMIEP (SRC_CIF_CIF0_MIEP)
+
+/** \brief DAC, CIF MJPEG Service Request */
+#define SRC_CIF_CIF0_MJPEG /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038DACu)
+
+/** Alias (User Manual Name) for SRC_CIF_CIF0_MJPEG.
+* To use register names with standard convension, please use SRC_CIF_CIF0_MJPEG.
+*/
+#define SRC_CIFMJPEG (SRC_CIF_CIF0_MJPEG)
+
+/** \brief 0, CPU Software Breakpoint Service Request */
+#define SRC_CPU_CPU0_SBSRC /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038000u)
+
+/** Alias (User Manual Name) for SRC_CPU_CPU0_SBSRC.
+* To use register names with standard convension, please use SRC_CPU_CPU0_SBSRC.
+*/
+#define SRC_CPU0SBSRC (SRC_CPU_CPU0_SBSRC)
+
+/** \brief 4, CPU Software Breakpoint Service Request */
+#define SRC_CPU_CPU1_SBSRC /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038004u)
+
+/** Alias (User Manual Name) for SRC_CPU_CPU1_SBSRC.
+* To use register names with standard convension, please use SRC_CPU_CPU1_SBSRC.
+*/
+#define SRC_CPU1SBSRC (SRC_CPU_CPU1_SBSRC)
+
+/** \brief 500, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038500u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH0.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH0.
+*/
+#define SRC_DMACH0 (SRC_DMA_DMA0_CH0)
+
+/** \brief 504, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038504u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH1.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH1.
+*/
+#define SRC_DMACH1 (SRC_DMA_DMA0_CH1)
+
+/** \brief 528, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH10 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038528u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH10.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH10.
+*/
+#define SRC_DMACH10 (SRC_DMA_DMA0_CH10)
+
+/** \brief 52C, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH11 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003852Cu)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH11.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH11.
+*/
+#define SRC_DMACH11 (SRC_DMA_DMA0_CH11)
+
+/** \brief 530, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH12 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038530u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH12.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH12.
+*/
+#define SRC_DMACH12 (SRC_DMA_DMA0_CH12)
+
+/** \brief 534, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH13 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038534u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH13.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH13.
+*/
+#define SRC_DMACH13 (SRC_DMA_DMA0_CH13)
+
+/** \brief 538, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH14 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038538u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH14.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH14.
+*/
+#define SRC_DMACH14 (SRC_DMA_DMA0_CH14)
+
+/** \brief 53C, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH15 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003853Cu)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH15.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH15.
+*/
+#define SRC_DMACH15 (SRC_DMA_DMA0_CH15)
+
+/** \brief 540, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH16 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038540u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH16.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH16.
+*/
+#define SRC_DMACH16 (SRC_DMA_DMA0_CH16)
+
+/** \brief 544, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH17 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038544u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH17.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH17.
+*/
+#define SRC_DMACH17 (SRC_DMA_DMA0_CH17)
+
+/** \brief 548, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH18 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038548u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH18.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH18.
+*/
+#define SRC_DMACH18 (SRC_DMA_DMA0_CH18)
+
+/** \brief 54C, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH19 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003854Cu)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH19.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH19.
+*/
+#define SRC_DMACH19 (SRC_DMA_DMA0_CH19)
+
+/** \brief 508, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038508u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH2.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH2.
+*/
+#define SRC_DMACH2 (SRC_DMA_DMA0_CH2)
+
+/** \brief 550, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH20 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038550u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH20.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH20.
+*/
+#define SRC_DMACH20 (SRC_DMA_DMA0_CH20)
+
+/** \brief 554, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH21 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038554u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH21.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH21.
+*/
+#define SRC_DMACH21 (SRC_DMA_DMA0_CH21)
+
+/** \brief 558, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH22 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038558u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH22.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH22.
+*/
+#define SRC_DMACH22 (SRC_DMA_DMA0_CH22)
+
+/** \brief 55C, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH23 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003855Cu)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH23.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH23.
+*/
+#define SRC_DMACH23 (SRC_DMA_DMA0_CH23)
+
+/** \brief 560, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH24 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038560u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH24.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH24.
+*/
+#define SRC_DMACH24 (SRC_DMA_DMA0_CH24)
+
+/** \brief 564, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH25 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038564u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH25.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH25.
+*/
+#define SRC_DMACH25 (SRC_DMA_DMA0_CH25)
+
+/** \brief 568, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH26 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038568u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH26.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH26.
+*/
+#define SRC_DMACH26 (SRC_DMA_DMA0_CH26)
+
+/** \brief 56C, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH27 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003856Cu)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH27.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH27.
+*/
+#define SRC_DMACH27 (SRC_DMA_DMA0_CH27)
+
+/** \brief 570, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH28 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038570u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH28.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH28.
+*/
+#define SRC_DMACH28 (SRC_DMA_DMA0_CH28)
+
+/** \brief 574, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH29 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038574u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH29.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH29.
+*/
+#define SRC_DMACH29 (SRC_DMA_DMA0_CH29)
+
+/** \brief 50C, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003850Cu)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH3.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH3.
+*/
+#define SRC_DMACH3 (SRC_DMA_DMA0_CH3)
+
+/** \brief 578, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH30 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038578u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH30.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH30.
+*/
+#define SRC_DMACH30 (SRC_DMA_DMA0_CH30)
+
+/** \brief 57C, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH31 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003857Cu)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH31.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH31.
+*/
+#define SRC_DMACH31 (SRC_DMA_DMA0_CH31)
+
+/** \brief 580, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH32 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038580u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH32.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH32.
+*/
+#define SRC_DMACH32 (SRC_DMA_DMA0_CH32)
+
+/** \brief 584, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH33 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038584u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH33.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH33.
+*/
+#define SRC_DMACH33 (SRC_DMA_DMA0_CH33)
+
+/** \brief 588, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH34 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038588u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH34.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH34.
+*/
+#define SRC_DMACH34 (SRC_DMA_DMA0_CH34)
+
+/** \brief 58C, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH35 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003858Cu)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH35.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH35.
+*/
+#define SRC_DMACH35 (SRC_DMA_DMA0_CH35)
+
+/** \brief 590, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH36 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038590u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH36.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH36.
+*/
+#define SRC_DMACH36 (SRC_DMA_DMA0_CH36)
+
+/** \brief 594, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH37 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038594u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH37.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH37.
+*/
+#define SRC_DMACH37 (SRC_DMA_DMA0_CH37)
+
+/** \brief 598, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH38 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038598u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH38.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH38.
+*/
+#define SRC_DMACH38 (SRC_DMA_DMA0_CH38)
+
+/** \brief 59C, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH39 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003859Cu)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH39.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH39.
+*/
+#define SRC_DMACH39 (SRC_DMA_DMA0_CH39)
+
+/** \brief 510, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038510u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH4.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH4.
+*/
+#define SRC_DMACH4 (SRC_DMA_DMA0_CH4)
+
+/** \brief 5A0, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH40 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00385A0u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH40.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH40.
+*/
+#define SRC_DMACH40 (SRC_DMA_DMA0_CH40)
+
+/** \brief 5A4, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH41 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00385A4u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH41.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH41.
+*/
+#define SRC_DMACH41 (SRC_DMA_DMA0_CH41)
+
+/** \brief 5A8, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH42 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00385A8u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH42.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH42.
+*/
+#define SRC_DMACH42 (SRC_DMA_DMA0_CH42)
+
+/** \brief 5AC, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH43 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00385ACu)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH43.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH43.
+*/
+#define SRC_DMACH43 (SRC_DMA_DMA0_CH43)
+
+/** \brief 5B0, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH44 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00385B0u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH44.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH44.
+*/
+#define SRC_DMACH44 (SRC_DMA_DMA0_CH44)
+
+/** \brief 5B4, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH45 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00385B4u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH45.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH45.
+*/
+#define SRC_DMACH45 (SRC_DMA_DMA0_CH45)
+
+/** \brief 5B8, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH46 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00385B8u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH46.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH46.
+*/
+#define SRC_DMACH46 (SRC_DMA_DMA0_CH46)
+
+/** \brief 5BC, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH47 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00385BCu)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH47.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH47.
+*/
+#define SRC_DMACH47 (SRC_DMA_DMA0_CH47)
+
+/** \brief 514, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH5 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038514u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH5.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH5.
+*/
+#define SRC_DMACH5 (SRC_DMA_DMA0_CH5)
+
+/** \brief 518, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH6 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038518u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH6.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH6.
+*/
+#define SRC_DMACH6 (SRC_DMA_DMA0_CH6)
+
+/** \brief 51C, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH7 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003851Cu)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH7.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH7.
+*/
+#define SRC_DMACH7 (SRC_DMA_DMA0_CH7)
+
+/** \brief 520, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH8 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038520u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH8.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH8.
+*/
+#define SRC_DMACH8 (SRC_DMA_DMA0_CH8)
+
+/** \brief 524, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH9 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038524u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH9.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH9.
+*/
+#define SRC_DMACH9 (SRC_DMA_DMA0_CH9)
+
+/** \brief 4F0, DMA Error Service Request */
+#define SRC_DMA_DMA0_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00384F0u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_ERR.
+* To use register names with standard convension, please use SRC_DMA_DMA0_ERR.
+*/
+#define SRC_DMAERR (SRC_DMA_DMA0_ERR)
+
+/** \brief B54, DSADC SRA Service Request */
+#define SRC_DSADC_DSADC0_SRA /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038B54u)
+
+/** Alias (User Manual Name) for SRC_DSADC_DSADC0_SRA.
+* To use register names with standard convension, please use SRC_DSADC_DSADC0_SRA.
+*/
+#define SRC_DSADCSRA0 (SRC_DSADC_DSADC0_SRA)
+
+/** \brief B50, DSADC SRM Service Request */
+#define SRC_DSADC_DSADC0_SRM /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038B50u)
+
+/** Alias (User Manual Name) for SRC_DSADC_DSADC0_SRM.
+* To use register names with standard convension, please use SRC_DSADC_DSADC0_SRM.
+*/
+#define SRC_DSADCSRM0 (SRC_DSADC_DSADC0_SRM)
+
+/** \brief B64, DSADC SRA Service Request */
+#define SRC_DSADC_DSADC2_SRA /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038B64u)
+
+/** Alias (User Manual Name) for SRC_DSADC_DSADC2_SRA.
+* To use register names with standard convension, please use SRC_DSADC_DSADC2_SRA.
+*/
+#define SRC_DSADCSRA2 (SRC_DSADC_DSADC2_SRA)
+
+/** \brief B60, DSADC SRM Service Request */
+#define SRC_DSADC_DSADC2_SRM /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038B60u)
+
+/** Alias (User Manual Name) for SRC_DSADC_DSADC2_SRM.
+* To use register names with standard convension, please use SRC_DSADC_DSADC2_SRM.
+*/
+#define SRC_DSADCSRM2 (SRC_DSADC_DSADC2_SRM)
+
+/** \brief B6C, DSADC SRA Service Request */
+#define SRC_DSADC_DSADC3_SRA /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038B6Cu)
+
+/** Alias (User Manual Name) for SRC_DSADC_DSADC3_SRA.
+* To use register names with standard convension, please use SRC_DSADC_DSADC3_SRA.
+*/
+#define SRC_DSADCSRA3 (SRC_DSADC_DSADC3_SRA)
+
+/** \brief B68, DSADC SRM Service Request */
+#define SRC_DSADC_DSADC3_SRM /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038B68u)
+
+/** Alias (User Manual Name) for SRC_DSADC_DSADC3_SRM.
+* To use register names with standard convension, please use SRC_DSADC_DSADC3_SRM.
+*/
+#define SRC_DSADCSRM3 (SRC_DSADC_DSADC3_SRM)
+
+/** \brief 20, Emulation Memory Service Request */
+#define SRC_EMEM_EMEM0_SR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038020u)
+
+/** Alias (User Manual Name) for SRC_EMEM_EMEM0_SR.
+* To use register names with standard convension, please use SRC_EMEM_EMEM0_SR.
+*/
+#define SRC_EMEM (SRC_EMEM_EMEM0_SR)
+
+/** \brief C04, E-RAY Input Buffer Busy Service Request */
+#define SRC_ERAY_ERAY0_IBUSY /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038C04u)
+
+/** Alias (User Manual Name) for SRC_ERAY_ERAY0_IBUSY.
+* To use register names with standard convension, please use SRC_ERAY_ERAY0_IBUSY.
+*/
+#define SRC_ERAYIBUSY (SRC_ERAY_ERAY0_IBUSY)
+
+/** \brief BE0, E-RAY Service Request */
+#define SRC_ERAY_ERAY0_INT0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038BE0u)
+
+/** Alias (User Manual Name) for SRC_ERAY_ERAY0_INT0.
+* To use register names with standard convension, please use SRC_ERAY_ERAY0_INT0.
+*/
+#define SRC_ERAYINT0 (SRC_ERAY_ERAY0_INT0)
+
+/** \brief BE4, E-RAY Service Request */
+#define SRC_ERAY_ERAY0_INT1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038BE4u)
+
+/** Alias (User Manual Name) for SRC_ERAY_ERAY0_INT1.
+* To use register names with standard convension, please use SRC_ERAY_ERAY0_INT1.
+*/
+#define SRC_ERAYINT1 (SRC_ERAY_ERAY0_INT1)
+
+/** \brief BF8, E-RAY Message Buffer Status Changed Service Request */
+#define SRC_ERAY_ERAY0_MBSC0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038BF8u)
+
+/** Alias (User Manual Name) for SRC_ERAY_ERAY0_MBSC0.
+* To use register names with standard convension, please use SRC_ERAY_ERAY0_MBSC0.
+*/
+#define SRC_ERAYMBSC0 (SRC_ERAY_ERAY0_MBSC0)
+
+/** \brief BFC, E-RAY Message Buffer Status Changed Service Request */
+#define SRC_ERAY_ERAY0_MBSC1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038BFCu)
+
+/** Alias (User Manual Name) for SRC_ERAY_ERAY0_MBSC1.
+* To use register names with standard convension, please use SRC_ERAY_ERAY0_MBSC1.
+*/
+#define SRC_ERAYMBSC1 (SRC_ERAY_ERAY0_MBSC1)
+
+/** \brief BF0, E-RAY New Data Service Request */
+#define SRC_ERAY_ERAY0_NDAT0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038BF0u)
+
+/** Alias (User Manual Name) for SRC_ERAY_ERAY0_NDAT0.
+* To use register names with standard convension, please use SRC_ERAY_ERAY0_NDAT0.
+*/
+#define SRC_ERAYNDAT0 (SRC_ERAY_ERAY0_NDAT0)
+
+/** \brief BF4, E-RAY New Data Service Request */
+#define SRC_ERAY_ERAY0_NDAT1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038BF4u)
+
+/** Alias (User Manual Name) for SRC_ERAY_ERAY0_NDAT1.
+* To use register names with standard convension, please use SRC_ERAY_ERAY0_NDAT1.
+*/
+#define SRC_ERAYNDAT1 (SRC_ERAY_ERAY0_NDAT1)
+
+/** \brief C00, E-RAY Output Buffer Busy Service Request */
+#define SRC_ERAY_ERAY0_OBUSY /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038C00u)
+
+/** Alias (User Manual Name) for SRC_ERAY_ERAY0_OBUSY.
+* To use register names with standard convension, please use SRC_ERAY_ERAY0_OBUSY.
+*/
+#define SRC_ERAYOBUSY (SRC_ERAY_ERAY0_OBUSY)
+
+/** \brief BE8, E-RAY Timer Interrupt Service Request */
+#define SRC_ERAY_ERAY0_TINT0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038BE8u)
+
+/** Alias (User Manual Name) for SRC_ERAY_ERAY0_TINT0.
+* To use register names with standard convension, please use SRC_ERAY_ERAY0_TINT0.
+*/
+#define SRC_ERAYTINT0 (SRC_ERAY_ERAY0_TINT0)
+
+/** \brief BEC, E-RAY Timer Interrupt Service Request */
+#define SRC_ERAY_ERAY0_TINT1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038BECu)
+
+/** Alias (User Manual Name) for SRC_ERAY_ERAY0_TINT1.
+* To use register names with standard convension, please use SRC_ERAY_ERAY0_TINT1.
+*/
+#define SRC_ERAYTINT1 (SRC_ERAY_ERAY0_TINT1)
+
+/** \brief 8F0, Ethernet Service Request */
+#define SRC_ETH_ETH0_SR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00388F0u)
+
+/** Alias (User Manual Name) for SRC_ETH_ETH0_SR.
+* To use register names with standard convension, please use SRC_ETH_ETH0_SR.
+*/
+#define SRC_ETH (SRC_ETH_ETH0_SR)
+
+/** \brief 4B0, FCE Error Service Request */
+#define SRC_FCE_FCE0_SR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00384B0u)
+
+/** Alias (User Manual Name) for SRC_FCE_FCE0_SR.
+* To use register names with standard convension, please use SRC_FCE_FCE0_SR.
+*/
+#define SRC_FCE (SRC_FCE_FCE0_SR)
+
+/** \brief FC0, FFT Done Service Request */
+#define SRC_FFT_FFT0_DONE /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038FC0u)
+
+/** Alias (User Manual Name) for SRC_FFT_FFT0_DONE.
+* To use register names with standard convension, please use SRC_FFT_FFT0_DONE.
+*/
+#define SRC_FFTDONE (SRC_FFT_FFT0_DONE)
+
+/** \brief FC4, FFT Error Service Request */
+#define SRC_FFT_FFT0_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038FC4u)
+
+/** Alias (User Manual Name) for SRC_FFT_FFT0_ERR.
+* To use register names with standard convension, please use SRC_FFT_FFT0_ERR.
+*/
+#define SRC_FFTERR (SRC_FFT_FFT0_ERR)
+
+/** \brief FC8, FFT Ready For Start Service Request */
+#define SRC_FFT_FFT0_RFS /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038FC8u)
+
+/** Alias (User Manual Name) for SRC_FFT_FFT0_RFS.
+* To use register names with standard convension, please use SRC_FFT_FFT0_RFS.
+*/
+#define SRC_FFTRFS (SRC_FFT_FFT0_RFS)
+
+/** \brief 1000, General Purpose Service Request 0 */
+#define SRC_GPSR_GPSR0_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039000u)
+
+/** Alias (User Manual Name) for SRC_GPSR_GPSR0_SR0.
+* To use register names with standard convension, please use SRC_GPSR_GPSR0_SR0.
+*/
+#define SRC_GPSR00 (SRC_GPSR_GPSR0_SR0)
+
+/** \brief 1004, General Purpose Service Request 1 */
+#define SRC_GPSR_GPSR0_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039004u)
+
+/** Alias (User Manual Name) for SRC_GPSR_GPSR0_SR1.
+* To use register names with standard convension, please use SRC_GPSR_GPSR0_SR1.
+*/
+#define SRC_GPSR01 (SRC_GPSR_GPSR0_SR1)
+
+/** \brief 1008, General Purpose Service Request 2 */
+#define SRC_GPSR_GPSR0_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039008u)
+
+/** Alias (User Manual Name) for SRC_GPSR_GPSR0_SR2.
+* To use register names with standard convension, please use SRC_GPSR_GPSR0_SR2.
+*/
+#define SRC_GPSR02 (SRC_GPSR_GPSR0_SR2)
+
+/** \brief 100C, General Purpose Service Request 3 */
+#define SRC_GPSR_GPSR0_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003900Cu)
+
+/** Alias (User Manual Name) for SRC_GPSR_GPSR0_SR3.
+* To use register names with standard convension, please use SRC_GPSR_GPSR0_SR3.
+*/
+#define SRC_GPSR03 (SRC_GPSR_GPSR0_SR3)
+
+/** \brief 1020, General Purpose Service Request 0 */
+#define SRC_GPSR_GPSR1_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039020u)
+
+/** Alias (User Manual Name) for SRC_GPSR_GPSR1_SR0.
+* To use register names with standard convension, please use SRC_GPSR_GPSR1_SR0.
+*/
+#define SRC_GPSR10 (SRC_GPSR_GPSR1_SR0)
+
+/** \brief 1024, General Purpose Service Request 1 */
+#define SRC_GPSR_GPSR1_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039024u)
+
+/** Alias (User Manual Name) for SRC_GPSR_GPSR1_SR1.
+* To use register names with standard convension, please use SRC_GPSR_GPSR1_SR1.
+*/
+#define SRC_GPSR11 (SRC_GPSR_GPSR1_SR1)
+
+/** \brief 1028, General Purpose Service Request 2 */
+#define SRC_GPSR_GPSR1_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039028u)
+
+/** Alias (User Manual Name) for SRC_GPSR_GPSR1_SR2.
+* To use register names with standard convension, please use SRC_GPSR_GPSR1_SR2.
+*/
+#define SRC_GPSR12 (SRC_GPSR_GPSR1_SR2)
+
+/** \brief 102C, General Purpose Service Request 3 */
+#define SRC_GPSR_GPSR1_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003902Cu)
+
+/** Alias (User Manual Name) for SRC_GPSR_GPSR1_SR3.
+* To use register names with standard convension, please use SRC_GPSR_GPSR1_SR3.
+*/
+#define SRC_GPSR13 (SRC_GPSR_GPSR1_SR3)
+
+/** \brief 460, GPT12 CAPREL Service Request */
+#define SRC_GPT12_GPT120_CIRQ /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038460u)
+
+/** Alias (User Manual Name) for SRC_GPT12_GPT120_CIRQ.
+* To use register names with standard convension, please use SRC_GPT12_GPT120_CIRQ.
+*/
+#define SRC_GPT120CIRQ (SRC_GPT12_GPT120_CIRQ)
+
+/** \brief 464, GPT12 T2 Overflow/Underflow Service Request */
+#define SRC_GPT12_GPT120_T2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038464u)
+
+/** Alias (User Manual Name) for SRC_GPT12_GPT120_T2.
+* To use register names with standard convension, please use SRC_GPT12_GPT120_T2.
+*/
+#define SRC_GPT120T2 (SRC_GPT12_GPT120_T2)
+
+/** \brief 468, GPT12 T3 Overflow/Underflow Service Request */
+#define SRC_GPT12_GPT120_T3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038468u)
+
+/** Alias (User Manual Name) for SRC_GPT12_GPT120_T3.
+* To use register names with standard convension, please use SRC_GPT12_GPT120_T3.
+*/
+#define SRC_GPT120T3 (SRC_GPT12_GPT120_T3)
+
+/** \brief 46C, GPT12 T4 Overflow/Underflow Service Request */
+#define SRC_GPT12_GPT120_T4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003846Cu)
+
+/** Alias (User Manual Name) for SRC_GPT12_GPT120_T4.
+* To use register names with standard convension, please use SRC_GPT12_GPT120_T4.
+*/
+#define SRC_GPT120T4 (SRC_GPT12_GPT120_T4)
+
+/** \brief 470, GPT12 T5 Overflow/Underflow Service Request */
+#define SRC_GPT12_GPT120_T5 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038470u)
+
+/** Alias (User Manual Name) for SRC_GPT12_GPT120_T5.
+* To use register names with standard convension, please use SRC_GPT12_GPT120_T5.
+*/
+#define SRC_GPT120T5 (SRC_GPT12_GPT120_T5)
+
+/** \brief 474, GPT12 T6 Overflow/Underflow Service Request */
+#define SRC_GPT12_GPT120_T6 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038474u)
+
+/** Alias (User Manual Name) for SRC_GPT12_GPT120_T6.
+* To use register names with standard convension, please use SRC_GPT12_GPT120_T6.
+*/
+#define SRC_GPT120T6 (SRC_GPT12_GPT120_T6)
+
+/** \brief 1600, GTM AEI Shared Service Request */
+#define SRC_GTM_GTM0_AEIIRQ /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039600u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_AEIIRQ.
+* To use register names with standard convension, please use SRC_GTM_GTM0_AEIIRQ.
+*/
+#define SRC_GTMAEIIRQ (SRC_GTM_GTM0_AEIIRQ)
+
+/** \brief 1604, GTM ARU Shared Service Request */
+#define SRC_GTM_GTM0_ARUIRQ0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039604u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_ARUIRQ0.
+* To use register names with standard convension, please use SRC_GTM_GTM0_ARUIRQ0.
+*/
+#define SRC_GTMARUIRQ0 (SRC_GTM_GTM0_ARUIRQ0)
+
+/** \brief 1608, GTM ARU Shared Service Request */
+#define SRC_GTM_GTM0_ARUIRQ1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039608u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_ARUIRQ1.
+* To use register names with standard convension, please use SRC_GTM_GTM0_ARUIRQ1.
+*/
+#define SRC_GTMARUIRQ1 (SRC_GTM_GTM0_ARUIRQ1)
+
+/** \brief 160C, GTM ARU Shared Service Request */
+#define SRC_GTM_GTM0_ARUIRQ2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003960Cu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_ARUIRQ2.
+* To use register names with standard convension, please use SRC_GTM_GTM0_ARUIRQ2.
+*/
+#define SRC_GTMARUIRQ2 (SRC_GTM_GTM0_ARUIRQ2)
+
+/** \brief 1D80, GTM ATOM Shared Service Request */
+#define SRC_GTM_GTM0_ATOM0_0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039D80u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_ATOM0_0.
+* To use register names with standard convension, please use SRC_GTM_GTM0_ATOM0_0.
+*/
+#define SRC_GTMATOM00 (SRC_GTM_GTM0_ATOM0_0)
+
+/** \brief 1D84, GTM ATOM Shared Service Request */
+#define SRC_GTM_GTM0_ATOM0_1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039D84u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_ATOM0_1.
+* To use register names with standard convension, please use SRC_GTM_GTM0_ATOM0_1.
+*/
+#define SRC_GTMATOM01 (SRC_GTM_GTM0_ATOM0_1)
+
+/** \brief 1D88, GTM ATOM Shared Service Request */
+#define SRC_GTM_GTM0_ATOM0_2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039D88u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_ATOM0_2.
+* To use register names with standard convension, please use SRC_GTM_GTM0_ATOM0_2.
+*/
+#define SRC_GTMATOM02 (SRC_GTM_GTM0_ATOM0_2)
+
+/** \brief 1D8C, GTM ATOM Shared Service Request */
+#define SRC_GTM_GTM0_ATOM0_3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039D8Cu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_ATOM0_3.
+* To use register names with standard convension, please use SRC_GTM_GTM0_ATOM0_3.
+*/
+#define SRC_GTMATOM03 (SRC_GTM_GTM0_ATOM0_3)
+
+/** \brief 1D90, GTM ATOM Shared Service Request */
+#define SRC_GTM_GTM0_ATOM1_0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039D90u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_ATOM1_0.
+* To use register names with standard convension, please use SRC_GTM_GTM0_ATOM1_0.
+*/
+#define SRC_GTMATOM10 (SRC_GTM_GTM0_ATOM1_0)
+
+/** \brief 1D94, GTM ATOM Shared Service Request */
+#define SRC_GTM_GTM0_ATOM1_1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039D94u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_ATOM1_1.
+* To use register names with standard convension, please use SRC_GTM_GTM0_ATOM1_1.
+*/
+#define SRC_GTMATOM11 (SRC_GTM_GTM0_ATOM1_1)
+
+/** \brief 1D98, GTM ATOM Shared Service Request */
+#define SRC_GTM_GTM0_ATOM1_2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039D98u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_ATOM1_2.
+* To use register names with standard convension, please use SRC_GTM_GTM0_ATOM1_2.
+*/
+#define SRC_GTMATOM12 (SRC_GTM_GTM0_ATOM1_2)
+
+/** \brief 1D9C, GTM ATOM Shared Service Request */
+#define SRC_GTM_GTM0_ATOM1_3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039D9Cu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_ATOM1_3.
+* To use register names with standard convension, please use SRC_GTM_GTM0_ATOM1_3.
+*/
+#define SRC_GTMATOM13 (SRC_GTM_GTM0_ATOM1_3)
+
+/** \brief 1DA0, GTM ATOM Shared Service Request */
+#define SRC_GTM_GTM0_ATOM2_0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039DA0u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_ATOM2_0.
+* To use register names with standard convension, please use SRC_GTM_GTM0_ATOM2_0.
+*/
+#define SRC_GTMATOM20 (SRC_GTM_GTM0_ATOM2_0)
+
+/** \brief 1DA4, GTM ATOM Shared Service Request */
+#define SRC_GTM_GTM0_ATOM2_1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039DA4u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_ATOM2_1.
+* To use register names with standard convension, please use SRC_GTM_GTM0_ATOM2_1.
+*/
+#define SRC_GTMATOM21 (SRC_GTM_GTM0_ATOM2_1)
+
+/** \brief 1DA8, GTM ATOM Shared Service Request */
+#define SRC_GTM_GTM0_ATOM2_2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039DA8u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_ATOM2_2.
+* To use register names with standard convension, please use SRC_GTM_GTM0_ATOM2_2.
+*/
+#define SRC_GTMATOM22 (SRC_GTM_GTM0_ATOM2_2)
+
+/** \brief 1DAC, GTM ATOM Shared Service Request */
+#define SRC_GTM_GTM0_ATOM2_3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039DACu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_ATOM2_3.
+* To use register names with standard convension, please use SRC_GTM_GTM0_ATOM2_3.
+*/
+#define SRC_GTMATOM23 (SRC_GTM_GTM0_ATOM2_3)
+
+/** \brief 1DB0, GTM ATOM Shared Service Request */
+#define SRC_GTM_GTM0_ATOM3_0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039DB0u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_ATOM3_0.
+* To use register names with standard convension, please use SRC_GTM_GTM0_ATOM3_0.
+*/
+#define SRC_GTMATOM30 (SRC_GTM_GTM0_ATOM3_0)
+
+/** \brief 1DB4, GTM ATOM Shared Service Request */
+#define SRC_GTM_GTM0_ATOM3_1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039DB4u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_ATOM3_1.
+* To use register names with standard convension, please use SRC_GTM_GTM0_ATOM3_1.
+*/
+#define SRC_GTMATOM31 (SRC_GTM_GTM0_ATOM3_1)
+
+/** \brief 1DB8, GTM ATOM Shared Service Request */
+#define SRC_GTM_GTM0_ATOM3_2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039DB8u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_ATOM3_2.
+* To use register names with standard convension, please use SRC_GTM_GTM0_ATOM3_2.
+*/
+#define SRC_GTMATOM32 (SRC_GTM_GTM0_ATOM3_2)
+
+/** \brief 1DBC, GTM ATOM Shared Service Request */
+#define SRC_GTM_GTM0_ATOM3_3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039DBCu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_ATOM3_3.
+* To use register names with standard convension, please use SRC_GTM_GTM0_ATOM3_3.
+*/
+#define SRC_GTMATOM33 (SRC_GTM_GTM0_ATOM3_3)
+
+/** \brief 1614, GTM BRC Shared Service Request */
+#define SRC_GTM_GTM0_BRCIRQ /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039614u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_BRCIRQ.
+* To use register names with standard convension, please use SRC_GTM_GTM0_BRCIRQ.
+*/
+#define SRC_GTMBRCIRQ (SRC_GTM_GTM0_BRCIRQ)
+
+/** \brief 1618, GTM CMP Shared Service Request */
+#define SRC_GTM_GTM0_CMPIRQ /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039618u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_CMPIRQ.
+* To use register names with standard convension, please use SRC_GTM_GTM0_CMPIRQ.
+*/
+#define SRC_GTMCMPIRQ (SRC_GTM_GTM0_CMPIRQ)
+
+/** \brief 16A4, GTM DPLL Service Request */
+#define SRC_GTM_GTM0_DPLL0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00396A4u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_DPLL0.
+* To use register names with standard convension, please use SRC_GTM_GTM0_DPLL0.
+*/
+#define SRC_GTMDPLL0 (SRC_GTM_GTM0_DPLL0)
+
+/** \brief 16A8, GTM DPLL Service Request */
+#define SRC_GTM_GTM0_DPLL1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00396A8u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_DPLL1.
+* To use register names with standard convension, please use SRC_GTM_GTM0_DPLL1.
+*/
+#define SRC_GTMDPLL1 (SRC_GTM_GTM0_DPLL1)
+
+/** \brief 16CC, GTM DPLL Service Request */
+#define SRC_GTM_GTM0_DPLL10 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00396CCu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_DPLL10.
+* To use register names with standard convension, please use SRC_GTM_GTM0_DPLL10.
+*/
+#define SRC_GTMDPLL10 (SRC_GTM_GTM0_DPLL10)
+
+/** \brief 16D0, GTM DPLL Service Request */
+#define SRC_GTM_GTM0_DPLL11 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00396D0u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_DPLL11.
+* To use register names with standard convension, please use SRC_GTM_GTM0_DPLL11.
+*/
+#define SRC_GTMDPLL11 (SRC_GTM_GTM0_DPLL11)
+
+/** \brief 16D4, GTM DPLL Service Request */
+#define SRC_GTM_GTM0_DPLL12 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00396D4u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_DPLL12.
+* To use register names with standard convension, please use SRC_GTM_GTM0_DPLL12.
+*/
+#define SRC_GTMDPLL12 (SRC_GTM_GTM0_DPLL12)
+
+/** \brief 16D8, GTM DPLL Service Request */
+#define SRC_GTM_GTM0_DPLL13 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00396D8u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_DPLL13.
+* To use register names with standard convension, please use SRC_GTM_GTM0_DPLL13.
+*/
+#define SRC_GTMDPLL13 (SRC_GTM_GTM0_DPLL13)
+
+/** \brief 16DC, GTM DPLL Service Request */
+#define SRC_GTM_GTM0_DPLL14 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00396DCu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_DPLL14.
+* To use register names with standard convension, please use SRC_GTM_GTM0_DPLL14.
+*/
+#define SRC_GTMDPLL14 (SRC_GTM_GTM0_DPLL14)
+
+/** \brief 16E0, GTM DPLL Service Request */
+#define SRC_GTM_GTM0_DPLL15 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00396E0u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_DPLL15.
+* To use register names with standard convension, please use SRC_GTM_GTM0_DPLL15.
+*/
+#define SRC_GTMDPLL15 (SRC_GTM_GTM0_DPLL15)
+
+/** \brief 16E4, GTM DPLL Service Request */
+#define SRC_GTM_GTM0_DPLL16 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00396E4u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_DPLL16.
+* To use register names with standard convension, please use SRC_GTM_GTM0_DPLL16.
+*/
+#define SRC_GTMDPLL16 (SRC_GTM_GTM0_DPLL16)
+
+/** \brief 16E8, GTM DPLL Service Request */
+#define SRC_GTM_GTM0_DPLL17 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00396E8u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_DPLL17.
+* To use register names with standard convension, please use SRC_GTM_GTM0_DPLL17.
+*/
+#define SRC_GTMDPLL17 (SRC_GTM_GTM0_DPLL17)
+
+/** \brief 16EC, GTM DPLL Service Request */
+#define SRC_GTM_GTM0_DPLL18 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00396ECu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_DPLL18.
+* To use register names with standard convension, please use SRC_GTM_GTM0_DPLL18.
+*/
+#define SRC_GTMDPLL18 (SRC_GTM_GTM0_DPLL18)
+
+/** \brief 16F0, GTM DPLL Service Request */
+#define SRC_GTM_GTM0_DPLL19 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00396F0u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_DPLL19.
+* To use register names with standard convension, please use SRC_GTM_GTM0_DPLL19.
+*/
+#define SRC_GTMDPLL19 (SRC_GTM_GTM0_DPLL19)
+
+/** \brief 16AC, GTM DPLL Service Request */
+#define SRC_GTM_GTM0_DPLL2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00396ACu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_DPLL2.
+* To use register names with standard convension, please use SRC_GTM_GTM0_DPLL2.
+*/
+#define SRC_GTMDPLL2 (SRC_GTM_GTM0_DPLL2)
+
+/** \brief 16F4, GTM DPLL Service Request */
+#define SRC_GTM_GTM0_DPLL20 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00396F4u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_DPLL20.
+* To use register names with standard convension, please use SRC_GTM_GTM0_DPLL20.
+*/
+#define SRC_GTMDPLL20 (SRC_GTM_GTM0_DPLL20)
+
+/** \brief 16F8, GTM DPLL Service Request */
+#define SRC_GTM_GTM0_DPLL21 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00396F8u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_DPLL21.
+* To use register names with standard convension, please use SRC_GTM_GTM0_DPLL21.
+*/
+#define SRC_GTMDPLL21 (SRC_GTM_GTM0_DPLL21)
+
+/** \brief 16FC, GTM DPLL Service Request */
+#define SRC_GTM_GTM0_DPLL22 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00396FCu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_DPLL22.
+* To use register names with standard convension, please use SRC_GTM_GTM0_DPLL22.
+*/
+#define SRC_GTMDPLL22 (SRC_GTM_GTM0_DPLL22)
+
+/** \brief 1700, GTM DPLL Service Request */
+#define SRC_GTM_GTM0_DPLL23 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039700u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_DPLL23.
+* To use register names with standard convension, please use SRC_GTM_GTM0_DPLL23.
+*/
+#define SRC_GTMDPLL23 (SRC_GTM_GTM0_DPLL23)
+
+/** \brief 1704, GTM DPLL Service Request */
+#define SRC_GTM_GTM0_DPLL24 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039704u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_DPLL24.
+* To use register names with standard convension, please use SRC_GTM_GTM0_DPLL24.
+*/
+#define SRC_GTMDPLL24 (SRC_GTM_GTM0_DPLL24)
+
+/** \brief 1708, GTM DPLL Service Request */
+#define SRC_GTM_GTM0_DPLL25 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039708u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_DPLL25.
+* To use register names with standard convension, please use SRC_GTM_GTM0_DPLL25.
+*/
+#define SRC_GTMDPLL25 (SRC_GTM_GTM0_DPLL25)
+
+/** \brief 170C, GTM DPLL Service Request */
+#define SRC_GTM_GTM0_DPLL26 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003970Cu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_DPLL26.
+* To use register names with standard convension, please use SRC_GTM_GTM0_DPLL26.
+*/
+#define SRC_GTMDPLL26 (SRC_GTM_GTM0_DPLL26)
+
+/** \brief 16B0, GTM DPLL Service Request */
+#define SRC_GTM_GTM0_DPLL3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00396B0u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_DPLL3.
+* To use register names with standard convension, please use SRC_GTM_GTM0_DPLL3.
+*/
+#define SRC_GTMDPLL3 (SRC_GTM_GTM0_DPLL3)
+
+/** \brief 16B4, GTM DPLL Service Request */
+#define SRC_GTM_GTM0_DPLL4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00396B4u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_DPLL4.
+* To use register names with standard convension, please use SRC_GTM_GTM0_DPLL4.
+*/
+#define SRC_GTMDPLL4 (SRC_GTM_GTM0_DPLL4)
+
+/** \brief 16B8, GTM DPLL Service Request */
+#define SRC_GTM_GTM0_DPLL5 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00396B8u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_DPLL5.
+* To use register names with standard convension, please use SRC_GTM_GTM0_DPLL5.
+*/
+#define SRC_GTMDPLL5 (SRC_GTM_GTM0_DPLL5)
+
+/** \brief 16BC, GTM DPLL Service Request */
+#define SRC_GTM_GTM0_DPLL6 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00396BCu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_DPLL6.
+* To use register names with standard convension, please use SRC_GTM_GTM0_DPLL6.
+*/
+#define SRC_GTMDPLL6 (SRC_GTM_GTM0_DPLL6)
+
+/** \brief 16C0, GTM DPLL Service Request */
+#define SRC_GTM_GTM0_DPLL7 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00396C0u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_DPLL7.
+* To use register names with standard convension, please use SRC_GTM_GTM0_DPLL7.
+*/
+#define SRC_GTMDPLL7 (SRC_GTM_GTM0_DPLL7)
+
+/** \brief 16C4, GTM DPLL Service Request */
+#define SRC_GTM_GTM0_DPLL8 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00396C4u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_DPLL8.
+* To use register names with standard convension, please use SRC_GTM_GTM0_DPLL8.
+*/
+#define SRC_GTMDPLL8 (SRC_GTM_GTM0_DPLL8)
+
+/** \brief 16C8, GTM DPLL Service Request */
+#define SRC_GTM_GTM0_DPLL9 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00396C8u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_DPLL9.
+* To use register names with standard convension, please use SRC_GTM_GTM0_DPLL9.
+*/
+#define SRC_GTMDPLL9 (SRC_GTM_GTM0_DPLL9)
+
+/** \brief 1770, GTM Error Service Request */
+#define SRC_GTM_GTM0_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039770u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_ERR.
+* To use register names with standard convension, please use SRC_GTM_GTM0_ERR.
+*/
+#define SRC_GTMERR (SRC_GTM_GTM0_ERR)
+
+/** \brief 1980, GTM MCS Shared Service Request */
+#define SRC_GTM_GTM0_MCS0_0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039980u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_MCS0_0.
+* To use register names with standard convension, please use SRC_GTM_GTM0_MCS0_0.
+*/
+#define SRC_GTMMCS00 (SRC_GTM_GTM0_MCS0_0)
+
+/** \brief 1984, GTM MCS Shared Service Request */
+#define SRC_GTM_GTM0_MCS0_1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039984u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_MCS0_1.
+* To use register names with standard convension, please use SRC_GTM_GTM0_MCS0_1.
+*/
+#define SRC_GTMMCS01 (SRC_GTM_GTM0_MCS0_1)
+
+/** \brief 1988, GTM MCS Shared Service Request */
+#define SRC_GTM_GTM0_MCS0_2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039988u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_MCS0_2.
+* To use register names with standard convension, please use SRC_GTM_GTM0_MCS0_2.
+*/
+#define SRC_GTMMCS02 (SRC_GTM_GTM0_MCS0_2)
+
+/** \brief 198C, GTM MCS Shared Service Request */
+#define SRC_GTM_GTM0_MCS0_3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003998Cu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_MCS0_3.
+* To use register names with standard convension, please use SRC_GTM_GTM0_MCS0_3.
+*/
+#define SRC_GTMMCS03 (SRC_GTM_GTM0_MCS0_3)
+
+/** \brief 1990, GTM MCS Shared Service Request */
+#define SRC_GTM_GTM0_MCS0_4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039990u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_MCS0_4.
+* To use register names with standard convension, please use SRC_GTM_GTM0_MCS0_4.
+*/
+#define SRC_GTMMCS04 (SRC_GTM_GTM0_MCS0_4)
+
+/** \brief 1994, GTM MCS Shared Service Request */
+#define SRC_GTM_GTM0_MCS0_5 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039994u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_MCS0_5.
+* To use register names with standard convension, please use SRC_GTM_GTM0_MCS0_5.
+*/
+#define SRC_GTMMCS05 (SRC_GTM_GTM0_MCS0_5)
+
+/** \brief 1998, GTM MCS Shared Service Request */
+#define SRC_GTM_GTM0_MCS0_6 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039998u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_MCS0_6.
+* To use register names with standard convension, please use SRC_GTM_GTM0_MCS0_6.
+*/
+#define SRC_GTMMCS06 (SRC_GTM_GTM0_MCS0_6)
+
+/** \brief 199C, GTM MCS Shared Service Request */
+#define SRC_GTM_GTM0_MCS0_7 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003999Cu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_MCS0_7.
+* To use register names with standard convension, please use SRC_GTM_GTM0_MCS0_7.
+*/
+#define SRC_GTMMCS07 (SRC_GTM_GTM0_MCS0_7)
+
+/** \brief 19A0, GTM MCS Shared Service Request */
+#define SRC_GTM_GTM0_MCS1_0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00399A0u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_MCS1_0.
+* To use register names with standard convension, please use SRC_GTM_GTM0_MCS1_0.
+*/
+#define SRC_GTMMCS10 (SRC_GTM_GTM0_MCS1_0)
+
+/** \brief 19A4, GTM MCS Shared Service Request */
+#define SRC_GTM_GTM0_MCS1_1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00399A4u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_MCS1_1.
+* To use register names with standard convension, please use SRC_GTM_GTM0_MCS1_1.
+*/
+#define SRC_GTMMCS11 (SRC_GTM_GTM0_MCS1_1)
+
+/** \brief 19A8, GTM MCS Shared Service Request */
+#define SRC_GTM_GTM0_MCS1_2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00399A8u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_MCS1_2.
+* To use register names with standard convension, please use SRC_GTM_GTM0_MCS1_2.
+*/
+#define SRC_GTMMCS12 (SRC_GTM_GTM0_MCS1_2)
+
+/** \brief 19AC, GTM MCS Shared Service Request */
+#define SRC_GTM_GTM0_MCS1_3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00399ACu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_MCS1_3.
+* To use register names with standard convension, please use SRC_GTM_GTM0_MCS1_3.
+*/
+#define SRC_GTMMCS13 (SRC_GTM_GTM0_MCS1_3)
+
+/** \brief 19B0, GTM MCS Shared Service Request */
+#define SRC_GTM_GTM0_MCS1_4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00399B0u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_MCS1_4.
+* To use register names with standard convension, please use SRC_GTM_GTM0_MCS1_4.
+*/
+#define SRC_GTMMCS14 (SRC_GTM_GTM0_MCS1_4)
+
+/** \brief 19B4, GTM MCS Shared Service Request */
+#define SRC_GTM_GTM0_MCS1_5 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00399B4u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_MCS1_5.
+* To use register names with standard convension, please use SRC_GTM_GTM0_MCS1_5.
+*/
+#define SRC_GTMMCS15 (SRC_GTM_GTM0_MCS1_5)
+
+/** \brief 19B8, GTM MCS Shared Service Request */
+#define SRC_GTM_GTM0_MCS1_6 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00399B8u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_MCS1_6.
+* To use register names with standard convension, please use SRC_GTM_GTM0_MCS1_6.
+*/
+#define SRC_GTMMCS16 (SRC_GTM_GTM0_MCS1_6)
+
+/** \brief 19BC, GTM MCS Shared Service Request */
+#define SRC_GTM_GTM0_MCS1_7 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00399BCu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_MCS1_7.
+* To use register names with standard convension, please use SRC_GTM_GTM0_MCS1_7.
+*/
+#define SRC_GTMMCS17 (SRC_GTM_GTM0_MCS1_7)
+
+/** \brief 19C0, GTM MCS Shared Service Request */
+#define SRC_GTM_GTM0_MCS2_0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00399C0u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_MCS2_0.
+* To use register names with standard convension, please use SRC_GTM_GTM0_MCS2_0.
+*/
+#define SRC_GTMMCS20 (SRC_GTM_GTM0_MCS2_0)
+
+/** \brief 19C4, GTM MCS Shared Service Request */
+#define SRC_GTM_GTM0_MCS2_1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00399C4u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_MCS2_1.
+* To use register names with standard convension, please use SRC_GTM_GTM0_MCS2_1.
+*/
+#define SRC_GTMMCS21 (SRC_GTM_GTM0_MCS2_1)
+
+/** \brief 19C8, GTM MCS Shared Service Request */
+#define SRC_GTM_GTM0_MCS2_2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00399C8u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_MCS2_2.
+* To use register names with standard convension, please use SRC_GTM_GTM0_MCS2_2.
+*/
+#define SRC_GTMMCS22 (SRC_GTM_GTM0_MCS2_2)
+
+/** \brief 19CC, GTM MCS Shared Service Request */
+#define SRC_GTM_GTM0_MCS2_3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00399CCu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_MCS2_3.
+* To use register names with standard convension, please use SRC_GTM_GTM0_MCS2_3.
+*/
+#define SRC_GTMMCS23 (SRC_GTM_GTM0_MCS2_3)
+
+/** \brief 19D0, GTM MCS Shared Service Request */
+#define SRC_GTM_GTM0_MCS2_4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00399D0u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_MCS2_4.
+* To use register names with standard convension, please use SRC_GTM_GTM0_MCS2_4.
+*/
+#define SRC_GTMMCS24 (SRC_GTM_GTM0_MCS2_4)
+
+/** \brief 19D4, GTM MCS Shared Service Request */
+#define SRC_GTM_GTM0_MCS2_5 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00399D4u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_MCS2_5.
+* To use register names with standard convension, please use SRC_GTM_GTM0_MCS2_5.
+*/
+#define SRC_GTMMCS25 (SRC_GTM_GTM0_MCS2_5)
+
+/** \brief 19D8, GTM MCS Shared Service Request */
+#define SRC_GTM_GTM0_MCS2_6 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00399D8u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_MCS2_6.
+* To use register names with standard convension, please use SRC_GTM_GTM0_MCS2_6.
+*/
+#define SRC_GTMMCS26 (SRC_GTM_GTM0_MCS2_6)
+
+/** \brief 19DC, GTM MCS Shared Service Request */
+#define SRC_GTM_GTM0_MCS2_7 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00399DCu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_MCS2_7.
+* To use register names with standard convension, please use SRC_GTM_GTM0_MCS2_7.
+*/
+#define SRC_GTMMCS27 (SRC_GTM_GTM0_MCS2_7)
+
+/** \brief 1F00, GTM Multi Channel Sequencer 0 Service Request */
+#define SRC_GTM_GTM0_MCSW00 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039F00u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_MCSW00.
+* To use register names with standard convension, please use SRC_GTM_GTM0_MCSW00.
+*/
+#define SRC_GTMMCSW00 (SRC_GTM_GTM0_MCSW00)
+
+/** \brief 1F04, GTM Multi Channel Sequencer 0 Service Request */
+#define SRC_GTM_GTM0_MCSW01 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039F04u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_MCSW01.
+* To use register names with standard convension, please use SRC_GTM_GTM0_MCSW01.
+*/
+#define SRC_GTMMCSW01 (SRC_GTM_GTM0_MCSW01)
+
+/** \brief 1F08, GTM Multi Channel Sequencer 0 Service Request */
+#define SRC_GTM_GTM0_MCSW02 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039F08u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_MCSW02.
+* To use register names with standard convension, please use SRC_GTM_GTM0_MCSW02.
+*/
+#define SRC_GTMMCSW02 (SRC_GTM_GTM0_MCSW02)
+
+/** \brief 1F40, GTM Multi Channel Sequencer 1 Service Request */
+#define SRC_GTM_GTM0_MCSW10 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039F40u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_MCSW10.
+* To use register names with standard convension, please use SRC_GTM_GTM0_MCSW10.
+*/
+#define SRC_GTMMCSW10 (SRC_GTM_GTM0_MCSW10)
+
+/** \brief 1F44, GTM Multi Channel Sequencer 1 Service Request */
+#define SRC_GTM_GTM0_MCSW11 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039F44u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_MCSW11.
+* To use register names with standard convension, please use SRC_GTM_GTM0_MCSW11.
+*/
+#define SRC_GTMMCSW11 (SRC_GTM_GTM0_MCSW11)
+
+/** \brief 1F48, GTM Multi Channel Sequencer 1 Service Request */
+#define SRC_GTM_GTM0_MCSW12 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039F48u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_MCSW12.
+* To use register names with standard convension, please use SRC_GTM_GTM0_MCSW12.
+*/
+#define SRC_GTMMCSW12 (SRC_GTM_GTM0_MCSW12)
+
+/** \brief 162C, GTM PSM Shared Service Request */
+#define SRC_GTM_GTM0_PSM0_0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003962Cu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_PSM0_0.
+* To use register names with standard convension, please use SRC_GTM_GTM0_PSM0_0.
+*/
+#define SRC_GTMPSM00 (SRC_GTM_GTM0_PSM0_0)
+
+/** \brief 1630, GTM PSM Shared Service Request */
+#define SRC_GTM_GTM0_PSM0_1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039630u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_PSM0_1.
+* To use register names with standard convension, please use SRC_GTM_GTM0_PSM0_1.
+*/
+#define SRC_GTMPSM01 (SRC_GTM_GTM0_PSM0_1)
+
+/** \brief 1634, GTM PSM Shared Service Request */
+#define SRC_GTM_GTM0_PSM0_2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039634u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_PSM0_2.
+* To use register names with standard convension, please use SRC_GTM_GTM0_PSM0_2.
+*/
+#define SRC_GTMPSM02 (SRC_GTM_GTM0_PSM0_2)
+
+/** \brief 1638, GTM PSM Shared Service Request */
+#define SRC_GTM_GTM0_PSM0_3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039638u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_PSM0_3.
+* To use register names with standard convension, please use SRC_GTM_GTM0_PSM0_3.
+*/
+#define SRC_GTMPSM03 (SRC_GTM_GTM0_PSM0_3)
+
+/** \brief 163C, GTM PSM Shared Service Request */
+#define SRC_GTM_GTM0_PSM0_4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003963Cu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_PSM0_4.
+* To use register names with standard convension, please use SRC_GTM_GTM0_PSM0_4.
+*/
+#define SRC_GTMPSM04 (SRC_GTM_GTM0_PSM0_4)
+
+/** \brief 1640, GTM PSM Shared Service Request */
+#define SRC_GTM_GTM0_PSM0_5 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039640u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_PSM0_5.
+* To use register names with standard convension, please use SRC_GTM_GTM0_PSM0_5.
+*/
+#define SRC_GTMPSM05 (SRC_GTM_GTM0_PSM0_5)
+
+/** \brief 1644, GTM PSM Shared Service Request */
+#define SRC_GTM_GTM0_PSM0_6 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039644u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_PSM0_6.
+* To use register names with standard convension, please use SRC_GTM_GTM0_PSM0_6.
+*/
+#define SRC_GTMPSM06 (SRC_GTM_GTM0_PSM0_6)
+
+/** \brief 1648, GTM PSM Shared Service Request */
+#define SRC_GTM_GTM0_PSM0_7 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039648u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_PSM0_7.
+* To use register names with standard convension, please use SRC_GTM_GTM0_PSM0_7.
+*/
+#define SRC_GTMPSM07 (SRC_GTM_GTM0_PSM0_7)
+
+/** \brief 161C, GTM SPE Shared Service Request */
+#define SRC_GTM_GTM0_SPEIRQ0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003961Cu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_SPEIRQ0.
+* To use register names with standard convension, please use SRC_GTM_GTM0_SPEIRQ0.
+*/
+#define SRC_GTMSPE0IRQ (SRC_GTM_GTM0_SPEIRQ0)
+
+/** \brief 1620, GTM SPE Shared Service Request */
+#define SRC_GTM_GTM0_SPEIRQ1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039620u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_SPEIRQ1.
+* To use register names with standard convension, please use SRC_GTM_GTM0_SPEIRQ1.
+*/
+#define SRC_GTMSPE1IRQ (SRC_GTM_GTM0_SPEIRQ1)
+
+/** \brief 1780, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM0_0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039780u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM0_0.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM0_0.
+*/
+#define SRC_GTMTIM00 (SRC_GTM_GTM0_TIM0_0)
+
+/** \brief 1784, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM0_1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039784u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM0_1.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM0_1.
+*/
+#define SRC_GTMTIM01 (SRC_GTM_GTM0_TIM0_1)
+
+/** \brief 1788, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM0_2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039788u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM0_2.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM0_2.
+*/
+#define SRC_GTMTIM02 (SRC_GTM_GTM0_TIM0_2)
+
+/** \brief 178C, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM0_3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003978Cu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM0_3.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM0_3.
+*/
+#define SRC_GTMTIM03 (SRC_GTM_GTM0_TIM0_3)
+
+/** \brief 1790, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM0_4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039790u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM0_4.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM0_4.
+*/
+#define SRC_GTMTIM04 (SRC_GTM_GTM0_TIM0_4)
+
+/** \brief 1794, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM0_5 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039794u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM0_5.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM0_5.
+*/
+#define SRC_GTMTIM05 (SRC_GTM_GTM0_TIM0_5)
+
+/** \brief 1798, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM0_6 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039798u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM0_6.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM0_6.
+*/
+#define SRC_GTMTIM06 (SRC_GTM_GTM0_TIM0_6)
+
+/** \brief 179C, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM0_7 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003979Cu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM0_7.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM0_7.
+*/
+#define SRC_GTMTIM07 (SRC_GTM_GTM0_TIM0_7)
+
+/** \brief 17A0, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM1_0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00397A0u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM1_0.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM1_0.
+*/
+#define SRC_GTMTIM10 (SRC_GTM_GTM0_TIM1_0)
+
+/** \brief 17A4, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM1_1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00397A4u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM1_1.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM1_1.
+*/
+#define SRC_GTMTIM11 (SRC_GTM_GTM0_TIM1_1)
+
+/** \brief 17A8, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM1_2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00397A8u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM1_2.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM1_2.
+*/
+#define SRC_GTMTIM12 (SRC_GTM_GTM0_TIM1_2)
+
+/** \brief 17AC, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM1_3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00397ACu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM1_3.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM1_3.
+*/
+#define SRC_GTMTIM13 (SRC_GTM_GTM0_TIM1_3)
+
+/** \brief 17B0, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM1_4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00397B0u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM1_4.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM1_4.
+*/
+#define SRC_GTMTIM14 (SRC_GTM_GTM0_TIM1_4)
+
+/** \brief 17B4, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM1_5 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00397B4u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM1_5.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM1_5.
+*/
+#define SRC_GTMTIM15 (SRC_GTM_GTM0_TIM1_5)
+
+/** \brief 17B8, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM1_6 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00397B8u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM1_6.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM1_6.
+*/
+#define SRC_GTMTIM16 (SRC_GTM_GTM0_TIM1_6)
+
+/** \brief 17BC, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM1_7 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00397BCu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM1_7.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM1_7.
+*/
+#define SRC_GTMTIM17 (SRC_GTM_GTM0_TIM1_7)
+
+/** \brief 17C0, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM2_0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00397C0u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM2_0.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM2_0.
+*/
+#define SRC_GTMTIM20 (SRC_GTM_GTM0_TIM2_0)
+
+/** \brief 17C4, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM2_1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00397C4u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM2_1.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM2_1.
+*/
+#define SRC_GTMTIM21 (SRC_GTM_GTM0_TIM2_1)
+
+/** \brief 17C8, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM2_2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00397C8u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM2_2.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM2_2.
+*/
+#define SRC_GTMTIM22 (SRC_GTM_GTM0_TIM2_2)
+
+/** \brief 17CC, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM2_3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00397CCu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM2_3.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM2_3.
+*/
+#define SRC_GTMTIM23 (SRC_GTM_GTM0_TIM2_3)
+
+/** \brief 17D0, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM2_4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00397D0u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM2_4.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM2_4.
+*/
+#define SRC_GTMTIM24 (SRC_GTM_GTM0_TIM2_4)
+
+/** \brief 17D4, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM2_5 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00397D4u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM2_5.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM2_5.
+*/
+#define SRC_GTMTIM25 (SRC_GTM_GTM0_TIM2_5)
+
+/** \brief 17D8, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM2_6 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00397D8u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM2_6.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM2_6.
+*/
+#define SRC_GTMTIM26 (SRC_GTM_GTM0_TIM2_6)
+
+/** \brief 17DC, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM2_7 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00397DCu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM2_7.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM2_7.
+*/
+#define SRC_GTMTIM27 (SRC_GTM_GTM0_TIM2_7)
+
+/** \brief 1B80, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM0_0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039B80u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM0_0.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM0_0.
+*/
+#define SRC_GTMTOM00 (SRC_GTM_GTM0_TOM0_0)
+
+/** \brief 1B84, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM0_1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039B84u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM0_1.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM0_1.
+*/
+#define SRC_GTMTOM01 (SRC_GTM_GTM0_TOM0_1)
+
+/** \brief 1B88, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM0_2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039B88u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM0_2.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM0_2.
+*/
+#define SRC_GTMTOM02 (SRC_GTM_GTM0_TOM0_2)
+
+/** \brief 1B8C, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM0_3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039B8Cu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM0_3.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM0_3.
+*/
+#define SRC_GTMTOM03 (SRC_GTM_GTM0_TOM0_3)
+
+/** \brief 1B90, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM0_4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039B90u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM0_4.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM0_4.
+*/
+#define SRC_GTMTOM04 (SRC_GTM_GTM0_TOM0_4)
+
+/** \brief 1B94, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM0_5 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039B94u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM0_5.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM0_5.
+*/
+#define SRC_GTMTOM05 (SRC_GTM_GTM0_TOM0_5)
+
+/** \brief 1B98, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM0_6 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039B98u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM0_6.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM0_6.
+*/
+#define SRC_GTMTOM06 (SRC_GTM_GTM0_TOM0_6)
+
+/** \brief 1B9C, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM0_7 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039B9Cu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM0_7.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM0_7.
+*/
+#define SRC_GTMTOM07 (SRC_GTM_GTM0_TOM0_7)
+
+/** \brief 1BA0, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM1_0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039BA0u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM1_0.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM1_0.
+*/
+#define SRC_GTMTOM10 (SRC_GTM_GTM0_TOM1_0)
+
+/** \brief 1BA4, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM1_1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039BA4u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM1_1.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM1_1.
+*/
+#define SRC_GTMTOM11 (SRC_GTM_GTM0_TOM1_1)
+
+/** \brief 1BA8, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM1_2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039BA8u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM1_2.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM1_2.
+*/
+#define SRC_GTMTOM12 (SRC_GTM_GTM0_TOM1_2)
+
+/** \brief 1BAC, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM1_3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039BACu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM1_3.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM1_3.
+*/
+#define SRC_GTMTOM13 (SRC_GTM_GTM0_TOM1_3)
+
+/** \brief 1BB0, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM1_4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039BB0u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM1_4.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM1_4.
+*/
+#define SRC_GTMTOM14 (SRC_GTM_GTM0_TOM1_4)
+
+/** \brief 1BB4, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM1_5 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039BB4u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM1_5.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM1_5.
+*/
+#define SRC_GTMTOM15 (SRC_GTM_GTM0_TOM1_5)
+
+/** \brief 1BB8, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM1_6 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039BB8u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM1_6.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM1_6.
+*/
+#define SRC_GTMTOM16 (SRC_GTM_GTM0_TOM1_6)
+
+/** \brief 1BBC, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM1_7 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039BBCu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM1_7.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM1_7.
+*/
+#define SRC_GTMTOM17 (SRC_GTM_GTM0_TOM1_7)
+
+/** \brief 290, HSCT Service Request */
+#define SRC_HSCT_HSCT0_SR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038290u)
+
+/** Alias (User Manual Name) for SRC_HSCT_HSCT0_SR.
+* To use register names with standard convension, please use SRC_HSCT_HSCT0_SR.
+*/
+#define SRC_HSCT (SRC_HSCT_HSCT0_SR)
+
+/** \brief 2E0, Exception Service Request */
+#define SRC_HSSL_EXI /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00382E0u)
+
+/** Alias (User Manual Name) for SRC_HSSL_EXI.
+* To use register names with standard convension, please use SRC_HSSL_EXI.
+*/
+#define SRC_HSSLEXI (SRC_HSSL_EXI)
+
+/** \brief 2A0, Channel OK Service Request m */
+#define SRC_HSSL_HSSL0_COK /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00382A0u)
+
+/** Alias (User Manual Name) for SRC_HSSL_HSSL0_COK.
+* To use register names with standard convension, please use SRC_HSSL_HSSL0_COK.
+*/
+#define SRC_HSSLCOK0 (SRC_HSSL_HSSL0_COK)
+
+/** \brief 2A8, Channel Error ServiceRequest m */
+#define SRC_HSSL_HSSL0_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00382A8u)
+
+/** Alias (User Manual Name) for SRC_HSSL_HSSL0_ERR.
+* To use register names with standard convension, please use SRC_HSSL_HSSL0_ERR.
+*/
+#define SRC_HSSLERR0 (SRC_HSSL_HSSL0_ERR)
+
+/** \brief 2A4, Channel Read Data Service Request m */
+#define SRC_HSSL_HSSL0_RDI /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00382A4u)
+
+/** Alias (User Manual Name) for SRC_HSSL_HSSL0_RDI.
+* To use register names with standard convension, please use SRC_HSSL_HSSL0_RDI.
+*/
+#define SRC_HSSLRDI0 (SRC_HSSL_HSSL0_RDI)
+
+/** \brief 2AC, Channel Trigger Service Request m */
+#define SRC_HSSL_HSSL0_TRG /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00382ACu)
+
+/** Alias (User Manual Name) for SRC_HSSL_HSSL0_TRG.
+* To use register names with standard convension, please use SRC_HSSL_HSSL0_TRG.
+*/
+#define SRC_HSSLTRG0 (SRC_HSSL_HSSL0_TRG)
+
+/** \brief 2B0, Channel OK Service Request m */
+#define SRC_HSSL_HSSL1_COK /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00382B0u)
+
+/** Alias (User Manual Name) for SRC_HSSL_HSSL1_COK.
+* To use register names with standard convension, please use SRC_HSSL_HSSL1_COK.
+*/
+#define SRC_HSSLCOK1 (SRC_HSSL_HSSL1_COK)
+
+/** \brief 2B8, Channel Error ServiceRequest m */
+#define SRC_HSSL_HSSL1_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00382B8u)
+
+/** Alias (User Manual Name) for SRC_HSSL_HSSL1_ERR.
+* To use register names with standard convension, please use SRC_HSSL_HSSL1_ERR.
+*/
+#define SRC_HSSLERR1 (SRC_HSSL_HSSL1_ERR)
+
+/** \brief 2B4, Channel Read Data Service Request m */
+#define SRC_HSSL_HSSL1_RDI /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00382B4u)
+
+/** Alias (User Manual Name) for SRC_HSSL_HSSL1_RDI.
+* To use register names with standard convension, please use SRC_HSSL_HSSL1_RDI.
+*/
+#define SRC_HSSLRDI1 (SRC_HSSL_HSSL1_RDI)
+
+/** \brief 2BC, Channel Trigger Service Request m */
+#define SRC_HSSL_HSSL1_TRG /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00382BCu)
+
+/** Alias (User Manual Name) for SRC_HSSL_HSSL1_TRG.
+* To use register names with standard convension, please use SRC_HSSL_HSSL1_TRG.
+*/
+#define SRC_HSSLTRG1 (SRC_HSSL_HSSL1_TRG)
+
+/** \brief 2C0, Channel OK Service Request m */
+#define SRC_HSSL_HSSL2_COK /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00382C0u)
+
+/** Alias (User Manual Name) for SRC_HSSL_HSSL2_COK.
+* To use register names with standard convension, please use SRC_HSSL_HSSL2_COK.
+*/
+#define SRC_HSSLCOK2 (SRC_HSSL_HSSL2_COK)
+
+/** \brief 2C8, Channel Error ServiceRequest m */
+#define SRC_HSSL_HSSL2_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00382C8u)
+
+/** Alias (User Manual Name) for SRC_HSSL_HSSL2_ERR.
+* To use register names with standard convension, please use SRC_HSSL_HSSL2_ERR.
+*/
+#define SRC_HSSLERR2 (SRC_HSSL_HSSL2_ERR)
+
+/** \brief 2C4, Channel Read Data Service Request m */
+#define SRC_HSSL_HSSL2_RDI /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00382C4u)
+
+/** Alias (User Manual Name) for SRC_HSSL_HSSL2_RDI.
+* To use register names with standard convension, please use SRC_HSSL_HSSL2_RDI.
+*/
+#define SRC_HSSLRDI2 (SRC_HSSL_HSSL2_RDI)
+
+/** \brief 2CC, Channel Trigger Service Request m */
+#define SRC_HSSL_HSSL2_TRG /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00382CCu)
+
+/** Alias (User Manual Name) for SRC_HSSL_HSSL2_TRG.
+* To use register names with standard convension, please use SRC_HSSL_HSSL2_TRG.
+*/
+#define SRC_HSSLTRG2 (SRC_HSSL_HSSL2_TRG)
+
+/** \brief 2D0, Channel OK Service Request m */
+#define SRC_HSSL_HSSL3_COK /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00382D0u)
+
+/** Alias (User Manual Name) for SRC_HSSL_HSSL3_COK.
+* To use register names with standard convension, please use SRC_HSSL_HSSL3_COK.
+*/
+#define SRC_HSSLCOK3 (SRC_HSSL_HSSL3_COK)
+
+/** \brief 2D8, Channel Error ServiceRequest m */
+#define SRC_HSSL_HSSL3_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00382D8u)
+
+/** Alias (User Manual Name) for SRC_HSSL_HSSL3_ERR.
+* To use register names with standard convension, please use SRC_HSSL_HSSL3_ERR.
+*/
+#define SRC_HSSLERR3 (SRC_HSSL_HSSL3_ERR)
+
+/** \brief 2D4, Channel Read Data Service Request m */
+#define SRC_HSSL_HSSL3_RDI /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00382D4u)
+
+/** Alias (User Manual Name) for SRC_HSSL_HSSL3_RDI.
+* To use register names with standard convension, please use SRC_HSSL_HSSL3_RDI.
+*/
+#define SRC_HSSLRDI3 (SRC_HSSL_HSSL3_RDI)
+
+/** \brief 2DC, Channel Trigger Service Request m */
+#define SRC_HSSL_HSSL3_TRG /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00382DCu)
+
+/** Alias (User Manual Name) for SRC_HSSL_HSSL3_TRG.
+* To use register names with standard convension, please use SRC_HSSL_HSSL3_TRG.
+*/
+#define SRC_HSSLTRG3 (SRC_HSSL_HSSL3_TRG)
+
+/** \brief 300, I2C Burst Data Transfer Request */
+#define SRC_I2C_I2C0_BREQ /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038300u)
+
+/** Alias (User Manual Name) for SRC_I2C_I2C0_BREQ.
+* To use register names with standard convension, please use SRC_I2C_I2C0_BREQ.
+*/
+#define SRC_I2C0BREQ (SRC_I2C_I2C0_BREQ)
+
+/** \brief 310, I2C Error Service Request */
+#define SRC_I2C_I2C0_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038310u)
+
+/** Alias (User Manual Name) for SRC_I2C_I2C0_ERR.
+* To use register names with standard convension, please use SRC_I2C_I2C0_ERR.
+*/
+#define SRC_I2C0ERR (SRC_I2C_I2C0_ERR)
+
+/** \brief 304, I2C Last Burst Data Transfer Service Request */
+#define SRC_I2C_I2C0_LBREQ /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038304u)
+
+/** Alias (User Manual Name) for SRC_I2C_I2C0_LBREQ.
+* To use register names with standard convension, please use SRC_I2C_I2C0_LBREQ.
+*/
+#define SRC_I2C0LBREQ (SRC_I2C_I2C0_LBREQ)
+
+/** \brief 30C, I2C Last Single Data Transfer Service Request */
+#define SRC_I2C_I2C0_LSREQ /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003830Cu)
+
+/** Alias (User Manual Name) for SRC_I2C_I2C0_LSREQ.
+* To use register names with standard convension, please use SRC_I2C_I2C0_LSREQ.
+*/
+#define SRC_I2C0LSREQ (SRC_I2C_I2C0_LSREQ)
+
+/** \brief 314, I2C Kernel Service Request */
+#define SRC_I2C_I2C0_P /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038314u)
+
+/** Alias (User Manual Name) for SRC_I2C_I2C0_P.
+* To use register names with standard convension, please use SRC_I2C_I2C0_P.
+*/
+#define SRC_I2C0P (SRC_I2C_I2C0_P)
+
+/** \brief 308, I2C Single Data Transfer Service Request */
+#define SRC_I2C_I2C0_SREQ /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038308u)
+
+/** Alias (User Manual Name) for SRC_I2C_I2C0_SREQ.
+* To use register names with standard convension, please use SRC_I2C_I2C0_SREQ.
+*/
+#define SRC_I2C0SREQ (SRC_I2C_I2C0_SREQ)
+
+/** \brief DE0, LMU Service Request */
+#define SRC_LMU_LMU0_SR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038DE0u)
+
+/** Alias (User Manual Name) for SRC_LMU_LMU0_SR.
+* To use register names with standard convension, please use SRC_LMU_LMU0_SR.
+*/
+#define SRC_LMU (SRC_LMU_LMU0_SR)
+
+/** \brief 3E0, MSC Service Request 0 */
+#define SRC_MSC_MSC0_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00383E0u)
+
+/** Alias (User Manual Name) for SRC_MSC_MSC0_SR0.
+* To use register names with standard convension, please use SRC_MSC_MSC0_SR0.
+*/
+#define SRC_MSC0SR0 (SRC_MSC_MSC0_SR0)
+
+/** \brief 3E4, MSC Service Request 1 */
+#define SRC_MSC_MSC0_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00383E4u)
+
+/** Alias (User Manual Name) for SRC_MSC_MSC0_SR1.
+* To use register names with standard convension, please use SRC_MSC_MSC0_SR1.
+*/
+#define SRC_MSC0SR1 (SRC_MSC_MSC0_SR1)
+
+/** \brief 3E8, MSC Service Request 2 */
+#define SRC_MSC_MSC0_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00383E8u)
+
+/** Alias (User Manual Name) for SRC_MSC_MSC0_SR2.
+* To use register names with standard convension, please use SRC_MSC_MSC0_SR2.
+*/
+#define SRC_MSC0SR2 (SRC_MSC_MSC0_SR2)
+
+/** \brief 3EC, MSC Service Request 3 */
+#define SRC_MSC_MSC0_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00383ECu)
+
+/** Alias (User Manual Name) for SRC_MSC_MSC0_SR3.
+* To use register names with standard convension, please use SRC_MSC_MSC0_SR3.
+*/
+#define SRC_MSC0SR3 (SRC_MSC_MSC0_SR3)
+
+/** \brief 3F0, MSC Service Request 4 */
+#define SRC_MSC_MSC0_SR4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00383F0u)
+
+/** Alias (User Manual Name) for SRC_MSC_MSC0_SR4.
+* To use register names with standard convension, please use SRC_MSC_MSC0_SR4.
+*/
+#define SRC_MSC0SR4 (SRC_MSC_MSC0_SR4)
+
+/** \brief 3F4, MSC Service Request 0 */
+#define SRC_MSC_MSC1_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00383F4u)
+
+/** Alias (User Manual Name) for SRC_MSC_MSC1_SR0.
+* To use register names with standard convension, please use SRC_MSC_MSC1_SR0.
+*/
+#define SRC_MSC1SR0 (SRC_MSC_MSC1_SR0)
+
+/** \brief 3F8, MSC Service Request 1 */
+#define SRC_MSC_MSC1_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00383F8u)
+
+/** Alias (User Manual Name) for SRC_MSC_MSC1_SR1.
+* To use register names with standard convension, please use SRC_MSC_MSC1_SR1.
+*/
+#define SRC_MSC1SR1 (SRC_MSC_MSC1_SR1)
+
+/** \brief 3FC, MSC Service Request 2 */
+#define SRC_MSC_MSC1_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00383FCu)
+
+/** Alias (User Manual Name) for SRC_MSC_MSC1_SR2.
+* To use register names with standard convension, please use SRC_MSC_MSC1_SR2.
+*/
+#define SRC_MSC1SR2 (SRC_MSC_MSC1_SR2)
+
+/** \brief 400, MSC Service Request 3 */
+#define SRC_MSC_MSC1_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038400u)
+
+/** Alias (User Manual Name) for SRC_MSC_MSC1_SR3.
+* To use register names with standard convension, please use SRC_MSC_MSC1_SR3.
+*/
+#define SRC_MSC1SR3 (SRC_MSC_MSC1_SR3)
+
+/** \brief 404, MSC Service Request 4 */
+#define SRC_MSC_MSC1_SR4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038404u)
+
+/** Alias (User Manual Name) for SRC_MSC_MSC1_SR4.
+* To use register names with standard convension, please use SRC_MSC_MSC1_SR4.
+*/
+#define SRC_MSC1SR4 (SRC_MSC_MSC1_SR4)
+
+/** \brief C30, PMU Service Request */
+#define SRC_PMU_PMU0_SR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038C30u)
+
+/** Alias (User Manual Name) for SRC_PMU_PMU0_SR.
+* To use register names with standard convension, please use SRC_PMU_PMU0_SR.
+*/
+#define SRC_PMU00 (SRC_PMU_PMU0_SR)
+
+/** \brief C34, PMU Service Request */
+#define SRC_PMU_PMU1_SR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038C34u)
+
+/** Alias (User Manual Name) for SRC_PMU_PMU1_SR.
+* To use register names with standard convension, please use SRC_PMU_PMU1_SR.
+*/
+#define SRC_PMU01 (SRC_PMU_PMU1_SR)
+
+/** \brief D30, PSI5 Service Request */
+#define SRC_PSI5_PSI50_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038D30u)
+
+/** Alias (User Manual Name) for SRC_PSI5_PSI50_SR0.
+* To use register names with standard convension, please use SRC_PSI5_PSI50_SR0.
+*/
+#define SRC_PSI50 (SRC_PSI5_PSI50_SR0)
+
+/** \brief D34, PSI5 Service Request */
+#define SRC_PSI5_PSI50_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038D34u)
+
+/** Alias (User Manual Name) for SRC_PSI5_PSI50_SR1.
+* To use register names with standard convension, please use SRC_PSI5_PSI50_SR1.
+*/
+#define SRC_PSI51 (SRC_PSI5_PSI50_SR1)
+
+/** \brief D38, PSI5 Service Request */
+#define SRC_PSI5_PSI50_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038D38u)
+
+/** Alias (User Manual Name) for SRC_PSI5_PSI50_SR2.
+* To use register names with standard convension, please use SRC_PSI5_PSI50_SR2.
+*/
+#define SRC_PSI52 (SRC_PSI5_PSI50_SR2)
+
+/** \brief D3C, PSI5 Service Request */
+#define SRC_PSI5_PSI50_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038D3Cu)
+
+/** Alias (User Manual Name) for SRC_PSI5_PSI50_SR3.
+* To use register names with standard convension, please use SRC_PSI5_PSI50_SR3.
+*/
+#define SRC_PSI53 (SRC_PSI5_PSI50_SR3)
+
+/** \brief D40, PSI5 Service Request */
+#define SRC_PSI5_PSI50_SR4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038D40u)
+
+/** Alias (User Manual Name) for SRC_PSI5_PSI50_SR4.
+* To use register names with standard convension, please use SRC_PSI5_PSI50_SR4.
+*/
+#define SRC_PSI54 (SRC_PSI5_PSI50_SR4)
+
+/** \brief D44, PSI5 Service Request */
+#define SRC_PSI5_PSI50_SR5 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038D44u)
+
+/** Alias (User Manual Name) for SRC_PSI5_PSI50_SR5.
+* To use register names with standard convension, please use SRC_PSI5_PSI50_SR5.
+*/
+#define SRC_PSI55 (SRC_PSI5_PSI50_SR5)
+
+/** \brief D48, PSI5 Service Request */
+#define SRC_PSI5_PSI50_SR6 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038D48u)
+
+/** Alias (User Manual Name) for SRC_PSI5_PSI50_SR6.
+* To use register names with standard convension, please use SRC_PSI5_PSI50_SR6.
+*/
+#define SRC_PSI56 (SRC_PSI5_PSI50_SR6)
+
+/** \brief D4C, PSI5 Service Request */
+#define SRC_PSI5_PSI50_SR7 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038D4Cu)
+
+/** Alias (User Manual Name) for SRC_PSI5_PSI50_SR7.
+* To use register names with standard convension, please use SRC_PSI5_PSI50_SR7.
+*/
+#define SRC_PSI57 (SRC_PSI5_PSI50_SR7)
+
+/** \brief DF0, PSI5-S Service Request */
+#define SRC_PSI5S_PSI5S0_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038DF0u)
+
+/** Alias (User Manual Name) for SRC_PSI5S_PSI5S0_SR0.
+* To use register names with standard convension, please use SRC_PSI5S_PSI5S0_SR0.
+*/
+#define SRC_PSI5S0 (SRC_PSI5S_PSI5S0_SR0)
+
+/** \brief DF4, PSI5-S Service Request */
+#define SRC_PSI5S_PSI5S0_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038DF4u)
+
+/** Alias (User Manual Name) for SRC_PSI5S_PSI5S0_SR1.
+* To use register names with standard convension, please use SRC_PSI5S_PSI5S0_SR1.
+*/
+#define SRC_PSI5S1 (SRC_PSI5S_PSI5S0_SR1)
+
+/** \brief DF8, PSI5-S Service Request */
+#define SRC_PSI5S_PSI5S0_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038DF8u)
+
+/** Alias (User Manual Name) for SRC_PSI5S_PSI5S0_SR2.
+* To use register names with standard convension, please use SRC_PSI5S_PSI5S0_SR2.
+*/
+#define SRC_PSI5S2 (SRC_PSI5S_PSI5S0_SR2)
+
+/** \brief DFC, PSI5-S Service Request */
+#define SRC_PSI5S_PSI5S0_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038DFCu)
+
+/** Alias (User Manual Name) for SRC_PSI5S_PSI5S0_SR3.
+* To use register names with standard convension, please use SRC_PSI5S_PSI5S0_SR3.
+*/
+#define SRC_PSI5S3 (SRC_PSI5S_PSI5S0_SR3)
+
+/** \brief E00, PSI5-S Service Request */
+#define SRC_PSI5S_PSI5S0_SR4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038E00u)
+
+/** Alias (User Manual Name) for SRC_PSI5S_PSI5S0_SR4.
+* To use register names with standard convension, please use SRC_PSI5S_PSI5S0_SR4.
+*/
+#define SRC_PSI5S4 (SRC_PSI5S_PSI5S0_SR4)
+
+/** \brief E04, PSI5-S Service Request */
+#define SRC_PSI5S_PSI5S0_SR5 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038E04u)
+
+/** Alias (User Manual Name) for SRC_PSI5S_PSI5S0_SR5.
+* To use register names with standard convension, please use SRC_PSI5S_PSI5S0_SR5.
+*/
+#define SRC_PSI5S5 (SRC_PSI5S_PSI5S0_SR5)
+
+/** \brief E08, PSI5-S Service Request */
+#define SRC_PSI5S_PSI5S0_SR6 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038E08u)
+
+/** Alias (User Manual Name) for SRC_PSI5S_PSI5S0_SR6.
+* To use register names with standard convension, please use SRC_PSI5S_PSI5S0_SR6.
+*/
+#define SRC_PSI5S6 (SRC_PSI5S_PSI5S0_SR6)
+
+/** \brief E0C, PSI5-S Service Request */
+#define SRC_PSI5S_PSI5S0_SR7 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038E0Cu)
+
+/** Alias (User Manual Name) for SRC_PSI5S_PSI5S0_SR7.
+* To use register names with standard convension, please use SRC_PSI5S_PSI5S0_SR7.
+*/
+#define SRC_PSI5S7 (SRC_PSI5S_PSI5S0_SR7)
+
+/** \brief 198, QSPI Error Service Request */
+#define SRC_QSPI_QSPI0_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038198u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI0_ERR.
+* To use register names with standard convension, please use SRC_QSPI_QSPI0_ERR.
+*/
+#define SRC_QSPI0ERR (SRC_QSPI_QSPI0_ERR)
+
+/** \brief 1A0, QSPI High Speed Capture Service Request */
+#define SRC_QSPI_QSPI0_HC /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381A0u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI0_HC.
+* To use register names with standard convension, please use SRC_QSPI_QSPI0_HC.
+*/
+#define SRC_RESERVED10 (SRC_QSPI_QSPI0_HC)
+
+/** \brief 19C, QSPI Phase Transition Service Request */
+#define SRC_QSPI_QSPI0_PT /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003819Cu)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI0_PT.
+* To use register names with standard convension, please use SRC_QSPI_QSPI0_PT.
+*/
+#define SRC_QSPI0PT (SRC_QSPI_QSPI0_PT)
+
+/** \brief 194, QSPI Receive Service Request */
+#define SRC_QSPI_QSPI0_RX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038194u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI0_RX.
+* To use register names with standard convension, please use SRC_QSPI_QSPI0_RX.
+*/
+#define SRC_QSPI0RX (SRC_QSPI_QSPI0_RX)
+
+/** \brief 190, QSPI Transmit Service Request */
+#define SRC_QSPI_QSPI0_TX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038190u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI0_TX.
+* To use register names with standard convension, please use SRC_QSPI_QSPI0_TX.
+*/
+#define SRC_QSPI0TX (SRC_QSPI_QSPI0_TX)
+
+/** \brief 1A4, QSPI User Defined Service Request */
+#define SRC_QSPI_QSPI0_U /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381A4u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI0_U.
+* To use register names with standard convension, please use SRC_QSPI_QSPI0_U.
+*/
+#define SRC_QSPI0U (SRC_QSPI_QSPI0_U)
+
+/** \brief 1B0, QSPI Error Service Request */
+#define SRC_QSPI_QSPI1_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381B0u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI1_ERR.
+* To use register names with standard convension, please use SRC_QSPI_QSPI1_ERR.
+*/
+#define SRC_QSPI1ERR (SRC_QSPI_QSPI1_ERR)
+
+/** \brief 1B8, QSPI High Speed Capture Service Request */
+#define SRC_QSPI_QSPI1_HC /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381B8u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI1_HC.
+* To use register names with standard convension, please use SRC_QSPI_QSPI1_HC.
+*/
+#define SRC_RESERVED11 (SRC_QSPI_QSPI1_HC)
+
+/** \brief 1B4, QSPI Phase Transition Service Request */
+#define SRC_QSPI_QSPI1_PT /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381B4u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI1_PT.
+* To use register names with standard convension, please use SRC_QSPI_QSPI1_PT.
+*/
+#define SRC_QSPI1PT (SRC_QSPI_QSPI1_PT)
+
+/** \brief 1AC, QSPI Receive Service Request */
+#define SRC_QSPI_QSPI1_RX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381ACu)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI1_RX.
+* To use register names with standard convension, please use SRC_QSPI_QSPI1_RX.
+*/
+#define SRC_QSPI1RX (SRC_QSPI_QSPI1_RX)
+
+/** \brief 1A8, QSPI Transmit Service Request */
+#define SRC_QSPI_QSPI1_TX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381A8u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI1_TX.
+* To use register names with standard convension, please use SRC_QSPI_QSPI1_TX.
+*/
+#define SRC_QSPI1TX (SRC_QSPI_QSPI1_TX)
+
+/** \brief 1BC, QSPI User Defined Service Request */
+#define SRC_QSPI_QSPI1_U /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381BCu)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI1_U.
+* To use register names with standard convension, please use SRC_QSPI_QSPI1_U.
+*/
+#define SRC_QSPI1U (SRC_QSPI_QSPI1_U)
+
+/** \brief 1C8, QSPI Error Service Request */
+#define SRC_QSPI_QSPI2_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381C8u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI2_ERR.
+* To use register names with standard convension, please use SRC_QSPI_QSPI2_ERR.
+*/
+#define SRC_QSPI2ERR (SRC_QSPI_QSPI2_ERR)
+
+/** \brief 1D0, QSPI High Speed Capture Service Request */
+#define SRC_QSPI_QSPI2_HC /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381D0u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI2_HC.
+* To use register names with standard convension, please use SRC_QSPI_QSPI2_HC.
+*/
+#define SRC_QSPI2HC (SRC_QSPI_QSPI2_HC)
+
+/** \brief 1CC, QSPI Phase Transition Service Request */
+#define SRC_QSPI_QSPI2_PT /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381CCu)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI2_PT.
+* To use register names with standard convension, please use SRC_QSPI_QSPI2_PT.
+*/
+#define SRC_QSPI2PT (SRC_QSPI_QSPI2_PT)
+
+/** \brief 1C4, QSPI Receive Service Request */
+#define SRC_QSPI_QSPI2_RX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381C4u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI2_RX.
+* To use register names with standard convension, please use SRC_QSPI_QSPI2_RX.
+*/
+#define SRC_QSPI2RX (SRC_QSPI_QSPI2_RX)
+
+/** \brief 1C0, QSPI Transmit Service Request */
+#define SRC_QSPI_QSPI2_TX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381C0u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI2_TX.
+* To use register names with standard convension, please use SRC_QSPI_QSPI2_TX.
+*/
+#define SRC_QSPI2TX (SRC_QSPI_QSPI2_TX)
+
+/** \brief 1D4, QSPI User Defined Service Request */
+#define SRC_QSPI_QSPI2_U /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381D4u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI2_U.
+* To use register names with standard convension, please use SRC_QSPI_QSPI2_U.
+*/
+#define SRC_QSPI2U (SRC_QSPI_QSPI2_U)
+
+/** \brief 1E0, QSPI Error Service Request */
+#define SRC_QSPI_QSPI3_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381E0u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI3_ERR.
+* To use register names with standard convension, please use SRC_QSPI_QSPI3_ERR.
+*/
+#define SRC_QSPI3ERR (SRC_QSPI_QSPI3_ERR)
+
+/** \brief 1E8, QSPI High Speed Capture Service Request */
+#define SRC_QSPI_QSPI3_HC /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381E8u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI3_HC.
+* To use register names with standard convension, please use SRC_QSPI_QSPI3_HC.
+*/
+#define SRC_QSPI3HC (SRC_QSPI_QSPI3_HC)
+
+/** \brief 1E4, QSPI Phase Transition Service Request */
+#define SRC_QSPI_QSPI3_PT /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381E4u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI3_PT.
+* To use register names with standard convension, please use SRC_QSPI_QSPI3_PT.
+*/
+#define SRC_QSPI3PT (SRC_QSPI_QSPI3_PT)
+
+/** \brief 1DC, QSPI Receive Service Request */
+#define SRC_QSPI_QSPI3_RX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381DCu)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI3_RX.
+* To use register names with standard convension, please use SRC_QSPI_QSPI3_RX.
+*/
+#define SRC_QSPI3RX (SRC_QSPI_QSPI3_RX)
+
+/** \brief 1D8, QSPI Transmit Service Request */
+#define SRC_QSPI_QSPI3_TX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381D8u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI3_TX.
+* To use register names with standard convension, please use SRC_QSPI_QSPI3_TX.
+*/
+#define SRC_QSPI3TX (SRC_QSPI_QSPI3_TX)
+
+/** \brief 1EC, QSPI User Defined Service Request */
+#define SRC_QSPI_QSPI3_U /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381ECu)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI3_U.
+* To use register names with standard convension, please use SRC_QSPI_QSPI3_U.
+*/
+#define SRC_QSPI3U (SRC_QSPI_QSPI3_U)
+
+/** \brief D00, Stand By Controller Service Request */
+#define SRC_SCR_SCR0_SR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038D00u)
+
+/** Alias (User Manual Name) for SRC_SCR_SCR0_SR.
+* To use register names with standard convension, please use SRC_SCR_SCR0_SR.
+*/
+#define SRC_SCR (SRC_SCR_SCR0_SR)
+
+/** \brief CD0, SCU DTS Busy Service Request */
+#define SRC_SCU_SCU_DTS /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038CD0u)
+
+/** Alias (User Manual Name) for SRC_SCU_SCU_DTS.
+* To use register names with standard convension, please use SRC_SCU_SCU_DTS.
+*/
+#define SRC_SCUDTS (SRC_SCU_SCU_DTS)
+
+/** \brief CD4, SCU ERU Service Request */
+#define SRC_SCU_SCU_ERU0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038CD4u)
+
+/** Alias (User Manual Name) for SRC_SCU_SCU_ERU0.
+* To use register names with standard convension, please use SRC_SCU_SCU_ERU0.
+*/
+#define SRC_SCUERU0 (SRC_SCU_SCU_ERU0)
+
+/** \brief CD8, SCU ERU Service Request */
+#define SRC_SCU_SCU_ERU1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038CD8u)
+
+/** Alias (User Manual Name) for SRC_SCU_SCU_ERU1.
+* To use register names with standard convension, please use SRC_SCU_SCU_ERU1.
+*/
+#define SRC_SCUERU1 (SRC_SCU_SCU_ERU1)
+
+/** \brief CDC, SCU ERU Service Request */
+#define SRC_SCU_SCU_ERU2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038CDCu)
+
+/** Alias (User Manual Name) for SRC_SCU_SCU_ERU2.
+* To use register names with standard convension, please use SRC_SCU_SCU_ERU2.
+*/
+#define SRC_SCUERU2 (SRC_SCU_SCU_ERU2)
+
+/** \brief CE0, SCU ERU Service Request */
+#define SRC_SCU_SCU_ERU3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038CE0u)
+
+/** Alias (User Manual Name) for SRC_SCU_SCU_ERU3.
+* To use register names with standard convension, please use SRC_SCU_SCU_ERU3.
+*/
+#define SRC_SCUERU3 (SRC_SCU_SCU_ERU3)
+
+/** \brief 350, SENT TRIG Service Request */
+#define SRC_SENT_SENT0_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038350u)
+
+/** Alias (User Manual Name) for SRC_SENT_SENT0_SR0.
+* To use register names with standard convension, please use SRC_SENT_SENT0_SR0.
+*/
+#define SRC_SENT0 (SRC_SENT_SENT0_SR0)
+
+/** \brief 354, SENT TRIG Service Request */
+#define SRC_SENT_SENT0_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038354u)
+
+/** Alias (User Manual Name) for SRC_SENT_SENT0_SR1.
+* To use register names with standard convension, please use SRC_SENT_SENT0_SR1.
+*/
+#define SRC_SENT1 (SRC_SENT_SENT0_SR1)
+
+/** \brief 358, SENT TRIG Service Request */
+#define SRC_SENT_SENT0_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038358u)
+
+/** Alias (User Manual Name) for SRC_SENT_SENT0_SR2.
+* To use register names with standard convension, please use SRC_SENT_SENT0_SR2.
+*/
+#define SRC_SENT2 (SRC_SENT_SENT0_SR2)
+
+/** \brief 35C, SENT TRIG Service Request */
+#define SRC_SENT_SENT0_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003835Cu)
+
+/** Alias (User Manual Name) for SRC_SENT_SENT0_SR3.
+* To use register names with standard convension, please use SRC_SENT_SENT0_SR3.
+*/
+#define SRC_SENT3 (SRC_SENT_SENT0_SR3)
+
+/** \brief 360, SENT TRIG Service Request */
+#define SRC_SENT_SENT0_SR4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038360u)
+
+/** Alias (User Manual Name) for SRC_SENT_SENT0_SR4.
+* To use register names with standard convension, please use SRC_SENT_SENT0_SR4.
+*/
+#define SRC_SENT4 (SRC_SENT_SENT0_SR4)
+
+/** \brief 364, SENT TRIG Service Request */
+#define SRC_SENT_SENT0_SR5 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038364u)
+
+/** Alias (User Manual Name) for SRC_SENT_SENT0_SR5.
+* To use register names with standard convension, please use SRC_SENT_SENT0_SR5.
+*/
+#define SRC_SENT5 (SRC_SENT_SENT0_SR5)
+
+/** \brief D10, SMU Service Request */
+#define SRC_SMU_SMU0_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038D10u)
+
+/** Alias (User Manual Name) for SRC_SMU_SMU0_SR0.
+* To use register names with standard convension, please use SRC_SMU_SMU0_SR0.
+*/
+#define SRC_SMU0 (SRC_SMU_SMU0_SR0)
+
+/** \brief D14, SMU Service Request */
+#define SRC_SMU_SMU0_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038D14u)
+
+/** Alias (User Manual Name) for SRC_SMU_SMU0_SR1.
+* To use register names with standard convension, please use SRC_SMU_SMU0_SR1.
+*/
+#define SRC_SMU1 (SRC_SMU_SMU0_SR1)
+
+/** \brief D18, SMU Service Request */
+#define SRC_SMU_SMU0_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038D18u)
+
+/** Alias (User Manual Name) for SRC_SMU_SMU0_SR2.
+* To use register names with standard convension, please use SRC_SMU_SMU0_SR2.
+*/
+#define SRC_SMU2 (SRC_SMU_SMU0_SR2)
+
+/** \brief 490, System Timer Service Request 0 */
+#define SRC_STM_STM0_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038490u)
+
+/** Alias (User Manual Name) for SRC_STM_STM0_SR0.
+* To use register names with standard convension, please use SRC_STM_STM0_SR0.
+*/
+#define SRC_STM0SR0 (SRC_STM_STM0_SR0)
+
+/** \brief 494, System Timer Service Request 1 */
+#define SRC_STM_STM0_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038494u)
+
+/** Alias (User Manual Name) for SRC_STM_STM0_SR1.
+* To use register names with standard convension, please use SRC_STM_STM0_SR1.
+*/
+#define SRC_STM0SR1 (SRC_STM_STM0_SR1)
+
+/** \brief 498, System Timer Service Request 0 */
+#define SRC_STM_STM1_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038498u)
+
+/** Alias (User Manual Name) for SRC_STM_STM1_SR0.
+* To use register names with standard convension, please use SRC_STM_STM1_SR0.
+*/
+#define SRC_STM1SR0 (SRC_STM_STM1_SR0)
+
+/** \brief 49C, System Timer Service Request 1 */
+#define SRC_STM_STM1_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003849Cu)
+
+/** Alias (User Manual Name) for SRC_STM_STM1_SR1.
+* To use register names with standard convension, please use SRC_STM_STM1_SR1.
+*/
+#define SRC_STM1SR1 (SRC_STM_STM1_SR1)
+
+/** \brief AA0, VADC Common Group Service Request 0 */
+#define SRC_VADC_CG0_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038AA0u)
+
+/** Alias (User Manual Name) for SRC_VADC_CG0_SR0.
+* To use register names with standard convension, please use SRC_VADC_CG0_SR0.
+*/
+#define SRC_VADCCG0SR0 (SRC_VADC_CG0_SR0)
+
+/** \brief AA4, VADC Common Group Service Request 1 */
+#define SRC_VADC_CG0_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038AA4u)
+
+/** Alias (User Manual Name) for SRC_VADC_CG0_SR1.
+* To use register names with standard convension, please use SRC_VADC_CG0_SR1.
+*/
+#define SRC_VADCCG0SR1 (SRC_VADC_CG0_SR1)
+
+/** \brief AA8, VADC Common Group Service Request 2 */
+#define SRC_VADC_CG0_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038AA8u)
+
+/** Alias (User Manual Name) for SRC_VADC_CG0_SR2.
+* To use register names with standard convension, please use SRC_VADC_CG0_SR2.
+*/
+#define SRC_VADCCG0SR2 (SRC_VADC_CG0_SR2)
+
+/** \brief AAC, VADC Common Group Service Request 3 */
+#define SRC_VADC_CG0_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038AACu)
+
+/** Alias (User Manual Name) for SRC_VADC_CG0_SR3.
+* To use register names with standard convension, please use SRC_VADC_CG0_SR3.
+*/
+#define SRC_VADCCG0SR3 (SRC_VADC_CG0_SR3)
+
+/** \brief AB0, VADC Common Group Service Request 0 */
+#define SRC_VADC_CG1_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038AB0u)
+
+/** Alias (User Manual Name) for SRC_VADC_CG1_SR0.
+* To use register names with standard convension, please use SRC_VADC_CG1_SR0.
+*/
+#define SRC_VADCCG1SR0 (SRC_VADC_CG1_SR0)
+
+/** \brief AB4, VADC Common Group Service Request 1 */
+#define SRC_VADC_CG1_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038AB4u)
+
+/** Alias (User Manual Name) for SRC_VADC_CG1_SR1.
+* To use register names with standard convension, please use SRC_VADC_CG1_SR1.
+*/
+#define SRC_VADCCG1SR1 (SRC_VADC_CG1_SR1)
+
+/** \brief AB8, VADC Common Group Service Request 2 */
+#define SRC_VADC_CG1_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038AB8u)
+
+/** Alias (User Manual Name) for SRC_VADC_CG1_SR2.
+* To use register names with standard convension, please use SRC_VADC_CG1_SR2.
+*/
+#define SRC_VADCCG1SR2 (SRC_VADC_CG1_SR2)
+
+/** \brief ABC, VADC Common Group Service Request 3 */
+#define SRC_VADC_CG1_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038ABCu)
+
+/** Alias (User Manual Name) for SRC_VADC_CG1_SR3.
+* To use register names with standard convension, please use SRC_VADC_CG1_SR3.
+*/
+#define SRC_VADCCG1SR3 (SRC_VADC_CG1_SR3)
+
+/** \brief 980, VADC Group Service Request 0 */
+#define SRC_VADC_G0_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038980u)
+
+/** Alias (User Manual Name) for SRC_VADC_G0_SR0.
+* To use register names with standard convension, please use SRC_VADC_G0_SR0.
+*/
+#define SRC_VADCG0SR0 (SRC_VADC_G0_SR0)
+
+/** \brief 984, VADC Group Service Request 1 */
+#define SRC_VADC_G0_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038984u)
+
+/** Alias (User Manual Name) for SRC_VADC_G0_SR1.
+* To use register names with standard convension, please use SRC_VADC_G0_SR1.
+*/
+#define SRC_VADCG0SR1 (SRC_VADC_G0_SR1)
+
+/** \brief 988, VADC Group Service Request 2 */
+#define SRC_VADC_G0_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038988u)
+
+/** Alias (User Manual Name) for SRC_VADC_G0_SR2.
+* To use register names with standard convension, please use SRC_VADC_G0_SR2.
+*/
+#define SRC_VADCG0SR2 (SRC_VADC_G0_SR2)
+
+/** \brief 98C, VADC Group Service Request 3 */
+#define SRC_VADC_G0_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003898Cu)
+
+/** Alias (User Manual Name) for SRC_VADC_G0_SR3.
+* To use register names with standard convension, please use SRC_VADC_G0_SR3.
+*/
+#define SRC_VADCG0SR3 (SRC_VADC_G0_SR3)
+
+/** \brief 990, VADC Group Service Request 0 */
+#define SRC_VADC_G1_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038990u)
+
+/** Alias (User Manual Name) for SRC_VADC_G1_SR0.
+* To use register names with standard convension, please use SRC_VADC_G1_SR0.
+*/
+#define SRC_VADCG1SR0 (SRC_VADC_G1_SR0)
+
+/** \brief 994, VADC Group Service Request 1 */
+#define SRC_VADC_G1_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038994u)
+
+/** Alias (User Manual Name) for SRC_VADC_G1_SR1.
+* To use register names with standard convension, please use SRC_VADC_G1_SR1.
+*/
+#define SRC_VADCG1SR1 (SRC_VADC_G1_SR1)
+
+/** \brief 998, VADC Group Service Request 2 */
+#define SRC_VADC_G1_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038998u)
+
+/** Alias (User Manual Name) for SRC_VADC_G1_SR2.
+* To use register names with standard convension, please use SRC_VADC_G1_SR2.
+*/
+#define SRC_VADCG1SR2 (SRC_VADC_G1_SR2)
+
+/** \brief 99C, VADC Group Service Request 3 */
+#define SRC_VADC_G1_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003899Cu)
+
+/** Alias (User Manual Name) for SRC_VADC_G1_SR3.
+* To use register names with standard convension, please use SRC_VADC_G1_SR3.
+*/
+#define SRC_VADCG1SR3 (SRC_VADC_G1_SR3)
+
+/** \brief 9A0, VADC Group Service Request 0 */
+#define SRC_VADC_G2_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00389A0u)
+
+/** Alias (User Manual Name) for SRC_VADC_G2_SR0.
+* To use register names with standard convension, please use SRC_VADC_G2_SR0.
+*/
+#define SRC_VADCG2SR0 (SRC_VADC_G2_SR0)
+
+/** \brief 9A4, VADC Group Service Request 1 */
+#define SRC_VADC_G2_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00389A4u)
+
+/** Alias (User Manual Name) for SRC_VADC_G2_SR1.
+* To use register names with standard convension, please use SRC_VADC_G2_SR1.
+*/
+#define SRC_VADCG2SR1 (SRC_VADC_G2_SR1)
+
+/** \brief 9A8, VADC Group Service Request 2 */
+#define SRC_VADC_G2_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00389A8u)
+
+/** Alias (User Manual Name) for SRC_VADC_G2_SR2.
+* To use register names with standard convension, please use SRC_VADC_G2_SR2.
+*/
+#define SRC_VADCG2SR2 (SRC_VADC_G2_SR2)
+
+/** \brief 9AC, VADC Group Service Request 3 */
+#define SRC_VADC_G2_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00389ACu)
+
+/** Alias (User Manual Name) for SRC_VADC_G2_SR3.
+* To use register names with standard convension, please use SRC_VADC_G2_SR3.
+*/
+#define SRC_VADCG2SR3 (SRC_VADC_G2_SR3)
+
+/** \brief 9B0, VADC Group Service Request 0 */
+#define SRC_VADC_G3_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00389B0u)
+
+/** Alias (User Manual Name) for SRC_VADC_G3_SR0.
+* To use register names with standard convension, please use SRC_VADC_G3_SR0.
+*/
+#define SRC_VADCG3SR0 (SRC_VADC_G3_SR0)
+
+/** \brief 9B4, VADC Group Service Request 1 */
+#define SRC_VADC_G3_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00389B4u)
+
+/** Alias (User Manual Name) for SRC_VADC_G3_SR1.
+* To use register names with standard convension, please use SRC_VADC_G3_SR1.
+*/
+#define SRC_VADCG3SR1 (SRC_VADC_G3_SR1)
+
+/** \brief 9B8, VADC Group Service Request 2 */
+#define SRC_VADC_G3_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00389B8u)
+
+/** Alias (User Manual Name) for SRC_VADC_G3_SR2.
+* To use register names with standard convension, please use SRC_VADC_G3_SR2.
+*/
+#define SRC_VADCG3SR2 (SRC_VADC_G3_SR2)
+
+/** \brief 9BC, VADC Group Service Request 3 */
+#define SRC_VADC_G3_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00389BCu)
+
+/** Alias (User Manual Name) for SRC_VADC_G3_SR3.
+* To use register names with standard convension, please use SRC_VADC_G3_SR3.
+*/
+#define SRC_VADCG3SR3 (SRC_VADC_G3_SR3)
+
+/** \brief 48, XBAR_SRI Service Request */
+#define SRC_XBAR_XBAR_SRC /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038048u)
+
+/** Alias (User Manual Name) for SRC_XBAR_XBAR_SRC.
+* To use register names with standard convension, please use SRC_XBAR_XBAR_SRC.
+*/
+#define SRC_XBARSRC (SRC_XBAR_XBAR_SRC)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXSRC_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSrc_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSrc_regdef.h
new file mode 100644
index 0000000..5e059e4
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxSrc_regdef.h
@@ -0,0 +1,676 @@
+/**
+ * \file IfxSrc_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Src Src
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Src_Bitfields Bitfields
+ * \ingroup IfxLld_Src
+ *
+ * \defgroup IfxLld_Src_union Union
+ * \ingroup IfxLld_Src
+ *
+ * \defgroup IfxLld_Src_struct Struct
+ * \ingroup IfxLld_Src
+ *
+ */
+#ifndef IFXSRC_REGDEF_H
+#define IFXSRC_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Src_Bitfields
+ * \{ */
+
+/** \brief Service request register */
+typedef struct _Ifx_SRC_SRCR_Bits
+{
+ unsigned int SRPN:8; /**< \brief [7:0] Service Request Priority Number (rw) */
+ unsigned int reserved_8:2; /**< \brief \internal Reserved */
+ unsigned int SRE:1; /**< \brief [10:10] Service Request Enable (rw) */
+ unsigned int TOS:2; /**< \brief [12:11] Type of Service Control (rw) */
+ unsigned int reserved_13:3; /**< \brief \internal Reserved */
+ unsigned int ECC:6; /**< \brief [21:16] ECC (rwh) */
+ unsigned int reserved_22:2; /**< \brief \internal Reserved */
+ unsigned int SRR:1; /**< \brief [24:24] Service Request Flag (rh) */
+ unsigned int CLRR:1; /**< \brief [25:25] Request Clear Bit (w) */
+ unsigned int SETR:1; /**< \brief [26:26] Request Set Bit (w) */
+ unsigned int IOV:1; /**< \brief [27:27] Interrupt Trigger Overflow Bit (rh) */
+ unsigned int IOVCLR:1; /**< \brief [28:28] Interrupt Trigger Overflow Clear Bit (w) */
+ unsigned int SWS:1; /**< \brief [29:29] SW Sticky Bit (rh) */
+ unsigned int SWSCLR:1; /**< \brief [30:30] SW Sticky Clear Bit (w) */
+ unsigned int reserved_31:1; /**< \brief \internal Reserved */
+} Ifx_SRC_SRCR_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Src_union
+ * \{ */
+
+/** \brief Service request register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_SRC_SRCR_Bits B; /**< \brief Bitfield access */
+} Ifx_SRC_SRCR;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Src_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L2
+ * \{ */
+
+/** \brief AGBT Service requests */
+typedef volatile struct _Ifx_SRC_AGBT
+{
+ Ifx_SRC_SRCR SR; /**< \brief 0, AGBT Service Request */
+} Ifx_SRC_AGBT;
+
+/** \brief ASCLIN Service requests */
+typedef volatile struct _Ifx_SRC_ASCLIN
+{
+ Ifx_SRC_SRCR TX; /**< \brief 0, ASCLIN Transmit Service Request */
+ Ifx_SRC_SRCR RX; /**< \brief 4, ASCLIN Receive Service Request */
+ Ifx_SRC_SRCR ERR; /**< \brief 8, ASCLIN Error Service Request */
+} Ifx_SRC_ASCLIN;
+
+/** \brief SPB Service requests */
+typedef volatile struct _Ifx_SRC_BCUSPB
+{
+ Ifx_SRC_SRCR SBSRC; /**< \brief 0, Bus Control Unit SPB Service Request */
+} Ifx_SRC_BCUSPB;
+
+/** \brief CAN Service requests */
+typedef volatile struct _Ifx_SRC_CAN
+{
+ Ifx_SRC_SRCR INT[16]; /**< \brief 0, MULTICAN+ Service Request */
+} Ifx_SRC_CAN;
+
+/** \brief CCU6 Service requests */
+typedef volatile struct _Ifx_SRC_CCU6
+{
+ Ifx_SRC_SRCR SR0; /**< \brief 0, CCU6 Service Request 0 */
+ Ifx_SRC_SRCR SR1; /**< \brief 4, CCU6 Service Request 1 */
+ Ifx_SRC_SRCR SR2; /**< \brief 8, CCU6 Service Request 2 */
+ Ifx_SRC_SRCR SR3; /**< \brief C, CCU6 Service Request 3 */
+} Ifx_SRC_CCU6;
+
+/** \brief CERBERUS Service requests */
+typedef volatile struct _Ifx_SRC_CERBERUS
+{
+ Ifx_SRC_SRCR SR[2]; /**< \brief 0, Cerberus Service Request */
+} Ifx_SRC_CERBERUS;
+
+/** \brief CIF Service requests */
+typedef volatile struct _Ifx_SRC_CIF
+{
+ Ifx_SRC_SRCR MI; /**< \brief 0, CIF MI Service Request */
+ Ifx_SRC_SRCR MIEP; /**< \brief 4, CIF MI EP Service Request */
+ Ifx_SRC_SRCR ISP; /**< \brief 8, CIF ISP Service Request */
+ Ifx_SRC_SRCR MJPEG; /**< \brief C, CIF MJPEG Service Request */
+} Ifx_SRC_CIF;
+
+/** \brief CPU Service requests */
+typedef volatile struct _Ifx_SRC_CPU
+{
+ Ifx_SRC_SRCR SBSRC; /**< \brief 0, CPU Software Breakpoint Service Request */
+} Ifx_SRC_CPU;
+
+/** \brief DMA Service requests */
+typedef volatile struct _Ifx_SRC_DMA
+{
+ Ifx_SRC_SRCR ERR; /**< \brief 0, DMA Error Service Request */
+ unsigned char reserved_4[12]; /**< \brief 4, \internal Reserved */
+ Ifx_SRC_SRCR CH[48]; /**< \brief 10, DMA Channel Service Request */
+} Ifx_SRC_DMA;
+
+/** \brief DSADC Service requests */
+typedef volatile struct _Ifx_SRC_DSADC
+{
+ Ifx_SRC_SRCR SRM; /**< \brief 0, DSADC SRM Service Request */
+ Ifx_SRC_SRCR SRA; /**< \brief 4, DSADC SRA Service Request */
+} Ifx_SRC_DSADC;
+
+/** \brief EMEM Service requests */
+typedef volatile struct _Ifx_SRC_EMEM
+{
+ Ifx_SRC_SRCR SR; /**< \brief 0, Emulation Memory Service Request */
+} Ifx_SRC_EMEM;
+
+/** \brief ERAY Service requests */
+typedef volatile struct _Ifx_SRC_ERAY
+{
+ Ifx_SRC_SRCR INT[2]; /**< \brief 0, E-RAY Service Request */
+ Ifx_SRC_SRCR TINT[2]; /**< \brief 8, E-RAY Timer Interrupt Service Request */
+ Ifx_SRC_SRCR NDAT[2]; /**< \brief 10, E-RAY New Data Service Request */
+ Ifx_SRC_SRCR MBSC[2]; /**< \brief 18, E-RAY Message Buffer Status Changed Service Request */
+ Ifx_SRC_SRCR OBUSY; /**< \brief 20, E-RAY Output Buffer Busy Service Request */
+ Ifx_SRC_SRCR IBUSY; /**< \brief 24, E-RAY Input Buffer Busy Service Request */
+ unsigned char reserved_28[40]; /**< \brief 28, \internal Reserved */
+} Ifx_SRC_ERAY;
+
+/** \brief ETH Service requests */
+typedef volatile struct _Ifx_SRC_ETH
+{
+ Ifx_SRC_SRCR SR; /**< \brief 0, Ethernet Service Request */
+} Ifx_SRC_ETH;
+
+/** \brief FCE Service requests */
+typedef volatile struct _Ifx_SRC_FCE
+{
+ Ifx_SRC_SRCR SR; /**< \brief 0, FCE Error Service Request */
+} Ifx_SRC_FCE;
+
+/** \brief FFT Service requests */
+typedef volatile struct _Ifx_SRC_FFT
+{
+ Ifx_SRC_SRCR DONE; /**< \brief 0, FFT Done Service Request */
+ Ifx_SRC_SRCR ERR; /**< \brief 4, FFT Error Service Request */
+ Ifx_SRC_SRCR RFS; /**< \brief 8, FFT Ready For Start Service Request */
+} Ifx_SRC_FFT;
+
+/** \brief GPSR Service requests */
+typedef volatile struct _Ifx_SRC_GPSR
+{
+ Ifx_SRC_SRCR SR0; /**< \brief 0, General Purpose Service Request 0 */
+ Ifx_SRC_SRCR SR1; /**< \brief 4, General Purpose Service Request 1 */
+ Ifx_SRC_SRCR SR2; /**< \brief 8, General Purpose Service Request 2 */
+ Ifx_SRC_SRCR SR3; /**< \brief C, General Purpose Service Request 3 */
+ unsigned char reserved_10[16]; /**< \brief 10, \internal Reserved */
+} Ifx_SRC_GPSR;
+
+/** \brief GPT12 Service requests */
+typedef volatile struct _Ifx_SRC_GPT12
+{
+ Ifx_SRC_SRCR CIRQ; /**< \brief 0, GPT12 CAPREL Service Request */
+ Ifx_SRC_SRCR T2; /**< \brief 4, GPT12 T2 Overflow/Underflow Service Request */
+ Ifx_SRC_SRCR T3; /**< \brief 8, GPT12 T3 Overflow/Underflow Service Request */
+ Ifx_SRC_SRCR T4; /**< \brief C, GPT12 T4 Overflow/Underflow Service Request */
+ Ifx_SRC_SRCR T5; /**< \brief 10, GPT12 T5 Overflow/Underflow Service Request */
+ Ifx_SRC_SRCR T6; /**< \brief 14, GPT12 T6 Overflow/Underflow Service Request */
+ unsigned char reserved_18[24]; /**< \brief 18, \internal Reserved */
+} Ifx_SRC_GPT12;
+
+/** \brief GTM Service requests */
+typedef volatile struct _Ifx_SRC_GTM
+{
+ Ifx_SRC_SRCR AEIIRQ; /**< \brief 0, GTM AEI Shared Service Request */
+ Ifx_SRC_SRCR ARUIRQ[3]; /**< \brief 4, GTM ARU Shared Service Request */
+ unsigned char reserved_10[4]; /**< \brief 10, \internal Reserved */
+ Ifx_SRC_SRCR BRCIRQ; /**< \brief 14, GTM BRC Shared Service Request */
+ Ifx_SRC_SRCR CMPIRQ; /**< \brief 18, GTM CMP Shared Service Request */
+ Ifx_SRC_SRCR SPEIRQ[2]; /**< \brief 1C, GTM SPE Shared Service Request */
+ unsigned char reserved_24[8]; /**< \brief 24, \internal Reserved */
+ Ifx_SRC_SRCR PSM[1][8]; /**< \brief 2C, GTM PSM Shared Service Request */
+ unsigned char reserved_4C[88]; /**< \brief 4C, \internal Reserved */
+ Ifx_SRC_SRCR DPLL[27]; /**< \brief A4, GTM DPLL Service Request */
+ unsigned char reserved_110[96]; /**< \brief 110, \internal Reserved */
+ Ifx_SRC_SRCR ERR; /**< \brief 170, GTM Error Service Request */
+ unsigned char reserved_174[12]; /**< \brief 174, \internal Reserved */
+ Ifx_SRC_SRCR TIM[3][8]; /**< \brief 180, GTM TIM Shared Service Request */
+ unsigned char reserved_1E0[416]; /**< \brief 1E0, \internal Reserved */
+ Ifx_SRC_SRCR MCS[3][8]; /**< \brief 380, GTM MCS Shared Service Request */
+ unsigned char reserved_3E0[416]; /**< \brief 3E0, \internal Reserved */
+ Ifx_SRC_SRCR TOM[2][8]; /**< \brief 580, GTM TOM Shared Service Request */
+ unsigned char reserved_5C0[448]; /**< \brief 5C0, \internal Reserved */
+ Ifx_SRC_SRCR ATOM[4][4]; /**< \brief 780, GTM ATOM Shared Service Request */
+ unsigned char reserved_7C0[320]; /**< \brief 7C0, \internal Reserved */
+ Ifx_SRC_SRCR MCSW0[3]; /**< \brief 900, GTM Multi Channel Sequencer 0 Service Request */
+ unsigned char reserved_90C[52]; /**< \brief 90C, \internal Reserved */
+ Ifx_SRC_SRCR MCSW1[3]; /**< \brief 940, GTM Multi Channel Sequencer 1 Service Request */
+} Ifx_SRC_GTM;
+
+/** \brief HSCT Service requests */
+typedef volatile struct _Ifx_SRC_HSCT
+{
+ Ifx_SRC_SRCR SR; /**< \brief 0, HSCT Service Request */
+} Ifx_SRC_HSCT;
+
+/** \brief HSSL Service requests */
+typedef volatile struct _Ifx_SRC_HSSL
+{
+ Ifx_SRC_SRCR COK; /**< \brief 0, Channel OK Service Request m */
+ Ifx_SRC_SRCR RDI; /**< \brief 4, Channel Read Data Service Request m */
+ Ifx_SRC_SRCR ERR; /**< \brief 8, Channel Error ServiceRequest m */
+ Ifx_SRC_SRCR TRG; /**< \brief C, Channel Trigger Service Request m */
+} Ifx_SRC_HSSL;
+
+/** \brief I2C Service requests */
+typedef volatile struct _Ifx_SRC_I2C
+{
+ Ifx_SRC_SRCR BREQ; /**< \brief 0, I2C Burst Data Transfer Request */
+ Ifx_SRC_SRCR LBREQ; /**< \brief 4, I2C Last Burst Data Transfer Service Request */
+ Ifx_SRC_SRCR SREQ; /**< \brief 8, I2C Single Data Transfer Service Request */
+ Ifx_SRC_SRCR LSREQ; /**< \brief C, I2C Last Single Data Transfer Service Request */
+ Ifx_SRC_SRCR ERR; /**< \brief 10, I2C Error Service Request */
+ Ifx_SRC_SRCR P; /**< \brief 14, I2C Kernel Service Request */
+ unsigned char reserved_18[56]; /**< \brief 18, \internal Reserved */
+} Ifx_SRC_I2C;
+
+/** \brief LMU Service requests */
+typedef volatile struct _Ifx_SRC_LMU
+{
+ Ifx_SRC_SRCR SR; /**< \brief 0, LMU Service Request */
+} Ifx_SRC_LMU;
+
+/** \brief MSC Service requests */
+typedef volatile struct _Ifx_SRC_MSC
+{
+ Ifx_SRC_SRCR SR0; /**< \brief 0, MSC Service Request 0 */
+ Ifx_SRC_SRCR SR1; /**< \brief 4, MSC Service Request 1 */
+ Ifx_SRC_SRCR SR2; /**< \brief 8, MSC Service Request 2 */
+ Ifx_SRC_SRCR SR3; /**< \brief C, MSC Service Request 3 */
+ Ifx_SRC_SRCR SR4; /**< \brief 10, MSC Service Request 4 */
+} Ifx_SRC_MSC;
+
+/** \brief PMU Service requests */
+typedef volatile struct _Ifx_SRC_PMU
+{
+ Ifx_SRC_SRCR SR; /**< \brief 0, PMU Service Request */
+} Ifx_SRC_PMU;
+
+/** \brief PSI5 Service requests */
+typedef volatile struct _Ifx_SRC_PSI5
+{
+ Ifx_SRC_SRCR SR[8]; /**< \brief 0, PSI5 Service Request */
+} Ifx_SRC_PSI5;
+
+/** \brief PSI5S Service requests */
+typedef volatile struct _Ifx_SRC_PSI5S
+{
+ Ifx_SRC_SRCR SR[8]; /**< \brief 0, PSI5-S Service Request */
+} Ifx_SRC_PSI5S;
+
+/** \brief QSPI Service requests */
+typedef volatile struct _Ifx_SRC_QSPI
+{
+ Ifx_SRC_SRCR TX; /**< \brief 0, QSPI Transmit Service Request */
+ Ifx_SRC_SRCR RX; /**< \brief 4, QSPI Receive Service Request */
+ Ifx_SRC_SRCR ERR; /**< \brief 8, QSPI Error Service Request */
+ Ifx_SRC_SRCR PT; /**< \brief C, QSPI Phase Transition Service Request */
+ Ifx_SRC_SRCR HC; /**< \brief 10, QSPI High Speed Capture Service Request */
+ Ifx_SRC_SRCR U; /**< \brief 14, QSPI User Defined Service Request */
+} Ifx_SRC_QSPI;
+
+/** \brief SCR Service requests */
+typedef volatile struct _Ifx_SRC_SCR
+{
+ Ifx_SRC_SRCR SR; /**< \brief 0, Stand By Controller Service Request */
+} Ifx_SRC_SCR;
+
+/** \brief SCU Service requests */
+typedef volatile struct _Ifx_SRC_SCU
+{
+ Ifx_SRC_SRCR DTS; /**< \brief 0, SCU DTS Busy Service Request */
+ Ifx_SRC_SRCR ERU[4]; /**< \brief 4, SCU ERU Service Request */
+} Ifx_SRC_SCU;
+
+/** \brief SENT Service requests */
+typedef volatile struct _Ifx_SRC_SENT
+{
+ Ifx_SRC_SRCR SR[6]; /**< \brief 0, SENT TRIG Service Request */
+} Ifx_SRC_SENT;
+
+/** \brief SMU Service requests */
+typedef volatile struct _Ifx_SRC_SMU
+{
+ Ifx_SRC_SRCR SR[3]; /**< \brief 0, SMU Service Request */
+} Ifx_SRC_SMU;
+
+/** \brief STM Service requests */
+typedef volatile struct _Ifx_SRC_STM
+{
+ Ifx_SRC_SRCR SR0; /**< \brief 0, System Timer Service Request 0 */
+ Ifx_SRC_SRCR SR1; /**< \brief 4, System Timer Service Request 1 */
+} Ifx_SRC_STM;
+
+/** \brief VADCCG Service requests */
+typedef volatile struct _Ifx_SRC_VADCCG
+{
+ Ifx_SRC_SRCR SR0; /**< \brief 0, VADC Common Group Service Request 0 */
+ Ifx_SRC_SRCR SR1; /**< \brief 4, VADC Common Group Service Request 1 */
+ Ifx_SRC_SRCR SR2; /**< \brief 8, VADC Common Group Service Request 2 */
+ Ifx_SRC_SRCR SR3; /**< \brief C, VADC Common Group Service Request 3 */
+} Ifx_SRC_VADCCG;
+
+/** \brief VADCG Service requests */
+typedef volatile struct _Ifx_SRC_VADCG
+{
+ Ifx_SRC_SRCR SR0; /**< \brief 0, VADC Group Service Request 0 */
+ Ifx_SRC_SRCR SR1; /**< \brief 4, VADC Group Service Request 1 */
+ Ifx_SRC_SRCR SR2; /**< \brief 8, VADC Group Service Request 2 */
+ Ifx_SRC_SRCR SR3; /**< \brief C, VADC Group Service Request 3 */
+} Ifx_SRC_VADCG;
+
+/** \brief XBAR Service requests */
+typedef volatile struct _Ifx_SRC_XBAR
+{
+ Ifx_SRC_SRCR SRC; /**< \brief 0, XBAR_SRI Service Request */
+} Ifx_SRC_XBAR;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Src_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L1
+ * \{ */
+
+/** \brief AGBT Service requests */
+typedef volatile struct _Ifx_SRC_GAGBT
+{
+ Ifx_SRC_AGBT AGBT[1]; /**< \brief 0, AGBT Service requests */
+} Ifx_SRC_GAGBT;
+
+/** \brief ASCLIN Service requests */
+typedef volatile struct _Ifx_SRC_GASCLIN
+{
+ Ifx_SRC_ASCLIN ASCLIN[4]; /**< \brief 0, ASCLIN Service requests */
+} Ifx_SRC_GASCLIN;
+
+/** \brief BCU Service requests */
+typedef volatile struct _Ifx_SRC_GBCU
+{
+ Ifx_SRC_BCUSPB SPB; /**< \brief 0, SPB Service requests */
+} Ifx_SRC_GBCU;
+
+/** \brief CAN Service requests */
+typedef volatile struct _Ifx_SRC_GCAN
+{
+ Ifx_SRC_CAN CAN[1]; /**< \brief 0, CAN Service requests */
+} Ifx_SRC_GCAN;
+
+/** \brief CCU6 Service requests */
+typedef volatile struct _Ifx_SRC_GCCU6
+{
+ Ifx_SRC_CCU6 CCU6[2]; /**< \brief 0, CCU6 Service requests */
+} Ifx_SRC_GCCU6;
+
+/** \brief CERBERUS Service requests */
+typedef volatile struct _Ifx_SRC_GCERBERUS
+{
+ Ifx_SRC_CERBERUS CERBERUS; /**< \brief 0, CERBERUS Service requests */
+} Ifx_SRC_GCERBERUS;
+
+/** \brief CIF Service requests */
+typedef volatile struct _Ifx_SRC_GCIF
+{
+ Ifx_SRC_CIF CIF[1]; /**< \brief 0, CIF Service requests */
+} Ifx_SRC_GCIF;
+
+/** \brief CPU Service requests */
+typedef volatile struct _Ifx_SRC_GCPU
+{
+ Ifx_SRC_CPU CPU[2]; /**< \brief 0, CPU Service requests */
+} Ifx_SRC_GCPU;
+
+/** \brief DMA Service requests */
+typedef volatile struct _Ifx_SRC_GDMA
+{
+ Ifx_SRC_DMA DMA[1]; /**< \brief 0, DMA Service requests */
+} Ifx_SRC_GDMA;
+
+/** \brief DSADC Service requests */
+typedef volatile struct _Ifx_SRC_GDSADC
+{
+ Ifx_SRC_DSADC DSADC0; /**< \brief 0, DSADC Service requests */
+ unsigned char reserved_8[8]; /**< \brief 8, \internal Reserved */
+ Ifx_SRC_DSADC DSADC2; /**< \brief 10, DSADC Service requests */
+ Ifx_SRC_DSADC DSADC3; /**< \brief 18, DSADC Service requests */
+} Ifx_SRC_GDSADC;
+
+/** \brief EMEM Service requests */
+typedef volatile struct _Ifx_SRC_GEMEM
+{
+ Ifx_SRC_EMEM EMEM[1]; /**< \brief 0, EMEM Service requests */
+} Ifx_SRC_GEMEM;
+
+/** \brief ERAY Service requests */
+typedef volatile struct _Ifx_SRC_GERAY
+{
+ Ifx_SRC_ERAY ERAY[1]; /**< \brief 0, ERAY Service requests */
+} Ifx_SRC_GERAY;
+
+/** \brief ETH Service requests */
+typedef volatile struct _Ifx_SRC_GETH
+{
+ Ifx_SRC_ETH ETH[1]; /**< \brief 0, ETH Service requests */
+} Ifx_SRC_GETH;
+
+/** \brief FCE Service requests */
+typedef volatile struct _Ifx_SRC_GFCE
+{
+ Ifx_SRC_FCE FCE[1]; /**< \brief 0, FCE Service requests */
+} Ifx_SRC_GFCE;
+
+/** \brief FFT Service requests */
+typedef volatile struct _Ifx_SRC_GFFT
+{
+ Ifx_SRC_FFT FFT[1]; /**< \brief 0, FFT Service requests */
+} Ifx_SRC_GFFT;
+
+/** \brief GPSR Service requests */
+typedef volatile struct _Ifx_SRC_GGPSR
+{
+ Ifx_SRC_GPSR GPSR[2]; /**< \brief 0, GPSR Service requests */
+} Ifx_SRC_GGPSR;
+
+/** \brief GPT12 Service requests */
+typedef volatile struct _Ifx_SRC_GGPT12
+{
+ Ifx_SRC_GPT12 GPT12[1]; /**< \brief 0, GPT12 Service requests */
+} Ifx_SRC_GGPT12;
+
+/** \brief GTM Service requests */
+typedef volatile struct _Ifx_SRC_GGTM
+{
+ Ifx_SRC_GTM GTM[1]; /**< \brief 0, GTM Service requests */
+} Ifx_SRC_GGTM;
+
+/** \brief HSCT Service requests */
+typedef volatile struct _Ifx_SRC_GHSCT
+{
+ Ifx_SRC_HSCT HSCT[1]; /**< \brief 0, HSCT Service requests */
+} Ifx_SRC_GHSCT;
+
+/** \brief HSSL Service requests */
+typedef volatile struct _Ifx_SRC_GHSSL
+{
+ Ifx_SRC_HSSL HSSL[4]; /**< \brief 0, HSSL Service requests */
+ Ifx_SRC_SRCR EXI; /**< \brief 40, Exception Service Request */
+} Ifx_SRC_GHSSL;
+
+/** \brief I2C Service requests */
+typedef volatile struct _Ifx_SRC_GI2C
+{
+ Ifx_SRC_I2C I2C[1]; /**< \brief 0, I2C Service requests */
+} Ifx_SRC_GI2C;
+
+/** \brief LMU Service requests */
+typedef volatile struct _Ifx_SRC_GLMU
+{
+ Ifx_SRC_LMU LMU[1]; /**< \brief 0, LMU Service requests */
+} Ifx_SRC_GLMU;
+
+/** \brief MSC Service requests */
+typedef volatile struct _Ifx_SRC_GMSC
+{
+ Ifx_SRC_MSC MSC[2]; /**< \brief 0, MSC Service requests */
+} Ifx_SRC_GMSC;
+
+/** \brief PMU Service requests */
+typedef volatile struct _Ifx_SRC_GPMU
+{
+ Ifx_SRC_PMU PMU[2]; /**< \brief 0, PMU Service requests */
+} Ifx_SRC_GPMU;
+
+/** \brief PSI5 Service requests */
+typedef volatile struct _Ifx_SRC_GPSI5
+{
+ Ifx_SRC_PSI5 PSI5[1]; /**< \brief 0, PSI5 Service requests */
+} Ifx_SRC_GPSI5;
+
+/** \brief PSI5S Service requests */
+typedef volatile struct _Ifx_SRC_GPSI5S
+{
+ Ifx_SRC_PSI5S PSI5S[1]; /**< \brief 0, PSI5S Service requests */
+} Ifx_SRC_GPSI5S;
+
+/** \brief QSPI Service requests */
+typedef volatile struct _Ifx_SRC_GQSPI
+{
+ Ifx_SRC_QSPI QSPI[4]; /**< \brief 0, QSPI Service requests */
+} Ifx_SRC_GQSPI;
+
+/** \brief SCR Service requests */
+typedef volatile struct _Ifx_SRC_GSCR
+{
+ Ifx_SRC_SCR SCR[1]; /**< \brief 0, SCR Service requests */
+} Ifx_SRC_GSCR;
+
+/** \brief SCU Service requests */
+typedef volatile struct _Ifx_SRC_GSCU
+{
+ Ifx_SRC_SCU SCU; /**< \brief 0, SCU Service requests */
+} Ifx_SRC_GSCU;
+
+/** \brief SENT Service requests */
+typedef volatile struct _Ifx_SRC_GSENT
+{
+ Ifx_SRC_SENT SENT[1]; /**< \brief 0, SENT Service requests */
+} Ifx_SRC_GSENT;
+
+/** \brief SMU Service requests */
+typedef volatile struct _Ifx_SRC_GSMU
+{
+ Ifx_SRC_SMU SMU[1]; /**< \brief 0, SMU Service requests */
+} Ifx_SRC_GSMU;
+
+/** \brief STM Service requests */
+typedef volatile struct _Ifx_SRC_GSTM
+{
+ Ifx_SRC_STM STM[2]; /**< \brief 0, STM Service requests */
+} Ifx_SRC_GSTM;
+
+/** \brief VADC Service requests */
+typedef volatile struct _Ifx_SRC_GVADC
+{
+ Ifx_SRC_VADCG G[4]; /**< \brief 0, VADCG Service requests */
+ unsigned char reserved_40[224]; /**< \brief 40, \internal Reserved */
+ Ifx_SRC_VADCCG CG[2]; /**< \brief 120, VADCCG Service requests */
+} Ifx_SRC_GVADC;
+
+/** \brief XBAR Service requests */
+typedef volatile struct _Ifx_SRC_GXBAR
+{
+ Ifx_SRC_XBAR XBAR; /**< \brief 0, XBAR Service requests */
+} Ifx_SRC_GXBAR;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Src_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief SRC object */
+typedef volatile struct _Ifx_SRC
+{
+ Ifx_SRC_GCPU CPU; /**< \brief 0, CPU Service requests */
+ unsigned char reserved_8[24]; /**< \brief 8, \internal Reserved */
+ Ifx_SRC_GEMEM EMEM; /**< \brief 20, EMEM Service requests */
+ Ifx_SRC_GAGBT AGBT; /**< \brief 24, AGBT Service requests */
+ unsigned char reserved_28[24]; /**< \brief 28, \internal Reserved */
+ Ifx_SRC_GBCU BCU; /**< \brief 40, BCU Service requests */
+ unsigned char reserved_44[4]; /**< \brief 44, \internal Reserved */
+ Ifx_SRC_GXBAR XBAR; /**< \brief 48, XBAR Service requests */
+ unsigned char reserved_4C[4]; /**< \brief 4C, \internal Reserved */
+ Ifx_SRC_GCERBERUS CERBERUS; /**< \brief 50, CERBERUS Service requests */
+ unsigned char reserved_58[40]; /**< \brief 58, \internal Reserved */
+ Ifx_SRC_GASCLIN ASCLIN; /**< \brief 80, ASCLIN Service requests */
+ unsigned char reserved_B0[224]; /**< \brief B0, \internal Reserved */
+ Ifx_SRC_GQSPI QSPI; /**< \brief 190, QSPI Service requests */
+ unsigned char reserved_1F0[160]; /**< \brief 1F0, \internal Reserved */
+ Ifx_SRC_GHSCT HSCT; /**< \brief 290, HSCT Service requests */
+ unsigned char reserved_294[12]; /**< \brief 294, \internal Reserved */
+ Ifx_SRC_GHSSL HSSL; /**< \brief 2A0, HSSL Service requests */
+ unsigned char reserved_2E4[28]; /**< \brief 2E4, \internal Reserved */
+ Ifx_SRC_GI2C I2C; /**< \brief 300, I2C Service requests */
+ Ifx_SRC_GSENT SENT; /**< \brief 350, SENT Service requests */
+ unsigned char reserved_368[120]; /**< \brief 368, \internal Reserved */
+ Ifx_SRC_GMSC MSC; /**< \brief 3E0, MSC Service requests */
+ unsigned char reserved_408[24]; /**< \brief 408, \internal Reserved */
+ Ifx_SRC_GCCU6 CCU6; /**< \brief 420, CCU6 Service requests */
+ unsigned char reserved_440[32]; /**< \brief 440, \internal Reserved */
+ Ifx_SRC_GGPT12 GPT12; /**< \brief 460, GPT12 Service requests */
+ Ifx_SRC_GSTM STM; /**< \brief 490, STM Service requests */
+ unsigned char reserved_4A0[16]; /**< \brief 4A0, \internal Reserved */
+ Ifx_SRC_GFCE FCE; /**< \brief 4B0, FCE Service requests */
+ unsigned char reserved_4B4[60]; /**< \brief 4B4, \internal Reserved */
+ Ifx_SRC_GDMA DMA; /**< \brief 4F0, DMA Service requests */
+ unsigned char reserved_5C0[816]; /**< \brief 5C0, \internal Reserved */
+ Ifx_SRC_GETH ETH; /**< \brief 8F0, ETH Service requests */
+ unsigned char reserved_8F4[12]; /**< \brief 8F4, \internal Reserved */
+ Ifx_SRC_GCAN CAN; /**< \brief 900, CAN Service requests */
+ unsigned char reserved_940[64]; /**< \brief 940, \internal Reserved */
+ Ifx_SRC_GVADC VADC; /**< \brief 980, VADC Service requests */
+ unsigned char reserved_AC0[144]; /**< \brief AC0, \internal Reserved */
+ Ifx_SRC_GDSADC DSADC; /**< \brief B50, DSADC Service requests */
+ unsigned char reserved_B70[112]; /**< \brief B70, \internal Reserved */
+ Ifx_SRC_GERAY ERAY; /**< \brief BE0, ERAY Service requests */
+ Ifx_SRC_GPMU PMU; /**< \brief C30, PMU Service requests */
+ unsigned char reserved_C38[152]; /**< \brief C38, \internal Reserved */
+ Ifx_SRC_GSCU SCU; /**< \brief CD0, SCU Service requests */
+ unsigned char reserved_CE4[28]; /**< \brief CE4, \internal Reserved */
+ Ifx_SRC_GSCR SCR; /**< \brief D00, SCR Service requests */
+ unsigned char reserved_D04[12]; /**< \brief D04, \internal Reserved */
+ Ifx_SRC_GSMU SMU; /**< \brief D10, SMU Service requests */
+ unsigned char reserved_D1C[20]; /**< \brief D1C, \internal Reserved */
+ Ifx_SRC_GPSI5 PSI5; /**< \brief D30, PSI5 Service requests */
+ unsigned char reserved_D50[80]; /**< \brief D50, \internal Reserved */
+ Ifx_SRC_GCIF CIF; /**< \brief DA0, CIF Service requests */
+ unsigned char reserved_DB0[48]; /**< \brief DB0, \internal Reserved */
+ Ifx_SRC_GLMU LMU; /**< \brief DE0, LMU Service requests */
+ unsigned char reserved_DE4[12]; /**< \brief DE4, \internal Reserved */
+ Ifx_SRC_GPSI5S PSI5S; /**< \brief DF0, PSI5S Service requests */
+ unsigned char reserved_E10[432]; /**< \brief E10, \internal Reserved */
+ Ifx_SRC_GFFT FFT; /**< \brief FC0, FFT Service requests */
+ unsigned char reserved_FCC[52]; /**< \brief FCC, \internal Reserved */
+ Ifx_SRC_GGPSR GPSR; /**< \brief 1000, GPSR Service requests */
+ unsigned char reserved_1040[1472]; /**< \brief 1040, \internal Reserved */
+ Ifx_SRC_GGTM GTM; /**< \brief 1600, GTM Service requests */
+ unsigned char reserved_1F4C[180]; /**< \brief 1F4C, \internal Reserved */
+} Ifx_SRC;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXSRC_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxStm_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxStm_bf.h
new file mode 100644
index 0000000..42496c7
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxStm_bf.h
@@ -0,0 +1,666 @@
+/**
+ * \file IfxStm_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Stm_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Stm
+ *
+ */
+#ifndef IFXSTM_BF_H
+#define IFXSTM_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Stm_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN0 */
+#define IFX_STM_ACCEN0_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN0 */
+#define IFX_STM_ACCEN0_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN0 */
+#define IFX_STM_ACCEN0_EN0_OFF (0u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN10 */
+#define IFX_STM_ACCEN0_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN10 */
+#define IFX_STM_ACCEN0_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN10 */
+#define IFX_STM_ACCEN0_EN10_OFF (10u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN11 */
+#define IFX_STM_ACCEN0_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN11 */
+#define IFX_STM_ACCEN0_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN11 */
+#define IFX_STM_ACCEN0_EN11_OFF (11u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN12 */
+#define IFX_STM_ACCEN0_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN12 */
+#define IFX_STM_ACCEN0_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN12 */
+#define IFX_STM_ACCEN0_EN12_OFF (12u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN13 */
+#define IFX_STM_ACCEN0_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN13 */
+#define IFX_STM_ACCEN0_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN13 */
+#define IFX_STM_ACCEN0_EN13_OFF (13u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN14 */
+#define IFX_STM_ACCEN0_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN14 */
+#define IFX_STM_ACCEN0_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN14 */
+#define IFX_STM_ACCEN0_EN14_OFF (14u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN15 */
+#define IFX_STM_ACCEN0_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN15 */
+#define IFX_STM_ACCEN0_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN15 */
+#define IFX_STM_ACCEN0_EN15_OFF (15u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN16 */
+#define IFX_STM_ACCEN0_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN16 */
+#define IFX_STM_ACCEN0_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN16 */
+#define IFX_STM_ACCEN0_EN16_OFF (16u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN17 */
+#define IFX_STM_ACCEN0_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN17 */
+#define IFX_STM_ACCEN0_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN17 */
+#define IFX_STM_ACCEN0_EN17_OFF (17u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN18 */
+#define IFX_STM_ACCEN0_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN18 */
+#define IFX_STM_ACCEN0_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN18 */
+#define IFX_STM_ACCEN0_EN18_OFF (18u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN19 */
+#define IFX_STM_ACCEN0_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN19 */
+#define IFX_STM_ACCEN0_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN19 */
+#define IFX_STM_ACCEN0_EN19_OFF (19u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN1 */
+#define IFX_STM_ACCEN0_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN1 */
+#define IFX_STM_ACCEN0_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN1 */
+#define IFX_STM_ACCEN0_EN1_OFF (1u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN20 */
+#define IFX_STM_ACCEN0_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN20 */
+#define IFX_STM_ACCEN0_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN20 */
+#define IFX_STM_ACCEN0_EN20_OFF (20u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN21 */
+#define IFX_STM_ACCEN0_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN21 */
+#define IFX_STM_ACCEN0_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN21 */
+#define IFX_STM_ACCEN0_EN21_OFF (21u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN22 */
+#define IFX_STM_ACCEN0_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN22 */
+#define IFX_STM_ACCEN0_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN22 */
+#define IFX_STM_ACCEN0_EN22_OFF (22u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN23 */
+#define IFX_STM_ACCEN0_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN23 */
+#define IFX_STM_ACCEN0_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN23 */
+#define IFX_STM_ACCEN0_EN23_OFF (23u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN24 */
+#define IFX_STM_ACCEN0_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN24 */
+#define IFX_STM_ACCEN0_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN24 */
+#define IFX_STM_ACCEN0_EN24_OFF (24u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN25 */
+#define IFX_STM_ACCEN0_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN25 */
+#define IFX_STM_ACCEN0_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN25 */
+#define IFX_STM_ACCEN0_EN25_OFF (25u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN26 */
+#define IFX_STM_ACCEN0_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN26 */
+#define IFX_STM_ACCEN0_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN26 */
+#define IFX_STM_ACCEN0_EN26_OFF (26u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN27 */
+#define IFX_STM_ACCEN0_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN27 */
+#define IFX_STM_ACCEN0_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN27 */
+#define IFX_STM_ACCEN0_EN27_OFF (27u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN28 */
+#define IFX_STM_ACCEN0_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN28 */
+#define IFX_STM_ACCEN0_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN28 */
+#define IFX_STM_ACCEN0_EN28_OFF (28u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN29 */
+#define IFX_STM_ACCEN0_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN29 */
+#define IFX_STM_ACCEN0_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN29 */
+#define IFX_STM_ACCEN0_EN29_OFF (29u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN2 */
+#define IFX_STM_ACCEN0_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN2 */
+#define IFX_STM_ACCEN0_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN2 */
+#define IFX_STM_ACCEN0_EN2_OFF (2u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN30 */
+#define IFX_STM_ACCEN0_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN30 */
+#define IFX_STM_ACCEN0_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN30 */
+#define IFX_STM_ACCEN0_EN30_OFF (30u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN31 */
+#define IFX_STM_ACCEN0_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN31 */
+#define IFX_STM_ACCEN0_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN31 */
+#define IFX_STM_ACCEN0_EN31_OFF (31u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN3 */
+#define IFX_STM_ACCEN0_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN3 */
+#define IFX_STM_ACCEN0_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN3 */
+#define IFX_STM_ACCEN0_EN3_OFF (3u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN4 */
+#define IFX_STM_ACCEN0_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN4 */
+#define IFX_STM_ACCEN0_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN4 */
+#define IFX_STM_ACCEN0_EN4_OFF (4u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN5 */
+#define IFX_STM_ACCEN0_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN5 */
+#define IFX_STM_ACCEN0_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN5 */
+#define IFX_STM_ACCEN0_EN5_OFF (5u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN6 */
+#define IFX_STM_ACCEN0_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN6 */
+#define IFX_STM_ACCEN0_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN6 */
+#define IFX_STM_ACCEN0_EN6_OFF (6u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN7 */
+#define IFX_STM_ACCEN0_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN7 */
+#define IFX_STM_ACCEN0_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN7 */
+#define IFX_STM_ACCEN0_EN7_OFF (7u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN8 */
+#define IFX_STM_ACCEN0_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN8 */
+#define IFX_STM_ACCEN0_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN8 */
+#define IFX_STM_ACCEN0_EN8_OFF (8u)
+
+/** \brief Length for Ifx_STM_ACCEN0_Bits.EN9 */
+#define IFX_STM_ACCEN0_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ACCEN0_Bits.EN9 */
+#define IFX_STM_ACCEN0_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ACCEN0_Bits.EN9 */
+#define IFX_STM_ACCEN0_EN9_OFF (9u)
+
+/** \brief Length for Ifx_STM_CAP_Bits.STMCAP63_32 */
+#define IFX_STM_CAP_STMCAP63_32_LEN (32u)
+
+/** \brief Mask for Ifx_STM_CAP_Bits.STMCAP63_32 */
+#define IFX_STM_CAP_STMCAP63_32_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_STM_CAP_Bits.STMCAP63_32 */
+#define IFX_STM_CAP_STMCAP63_32_OFF (0u)
+
+/** \brief Length for Ifx_STM_CAPSV_Bits.STMCAP63_32 */
+#define IFX_STM_CAPSV_STMCAP63_32_LEN (32u)
+
+/** \brief Mask for Ifx_STM_CAPSV_Bits.STMCAP63_32 */
+#define IFX_STM_CAPSV_STMCAP63_32_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_STM_CAPSV_Bits.STMCAP63_32 */
+#define IFX_STM_CAPSV_STMCAP63_32_OFF (0u)
+
+/** \brief Length for Ifx_STM_CLC_Bits.DISR */
+#define IFX_STM_CLC_DISR_LEN (1u)
+
+/** \brief Mask for Ifx_STM_CLC_Bits.DISR */
+#define IFX_STM_CLC_DISR_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_CLC_Bits.DISR */
+#define IFX_STM_CLC_DISR_OFF (0u)
+
+/** \brief Length for Ifx_STM_CLC_Bits.DISS */
+#define IFX_STM_CLC_DISS_LEN (1u)
+
+/** \brief Mask for Ifx_STM_CLC_Bits.DISS */
+#define IFX_STM_CLC_DISS_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_CLC_Bits.DISS */
+#define IFX_STM_CLC_DISS_OFF (1u)
+
+/** \brief Length for Ifx_STM_CLC_Bits.EDIS */
+#define IFX_STM_CLC_EDIS_LEN (1u)
+
+/** \brief Mask for Ifx_STM_CLC_Bits.EDIS */
+#define IFX_STM_CLC_EDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_CLC_Bits.EDIS */
+#define IFX_STM_CLC_EDIS_OFF (3u)
+
+/** \brief Length for Ifx_STM_CMCON_Bits.MSIZE0 */
+#define IFX_STM_CMCON_MSIZE0_LEN (5u)
+
+/** \brief Mask for Ifx_STM_CMCON_Bits.MSIZE0 */
+#define IFX_STM_CMCON_MSIZE0_MSK (0x1fu)
+
+/** \brief Offset for Ifx_STM_CMCON_Bits.MSIZE0 */
+#define IFX_STM_CMCON_MSIZE0_OFF (0u)
+
+/** \brief Length for Ifx_STM_CMCON_Bits.MSIZE1 */
+#define IFX_STM_CMCON_MSIZE1_LEN (5u)
+
+/** \brief Mask for Ifx_STM_CMCON_Bits.MSIZE1 */
+#define IFX_STM_CMCON_MSIZE1_MSK (0x1fu)
+
+/** \brief Offset for Ifx_STM_CMCON_Bits.MSIZE1 */
+#define IFX_STM_CMCON_MSIZE1_OFF (16u)
+
+/** \brief Length for Ifx_STM_CMCON_Bits.MSTART0 */
+#define IFX_STM_CMCON_MSTART0_LEN (5u)
+
+/** \brief Mask for Ifx_STM_CMCON_Bits.MSTART0 */
+#define IFX_STM_CMCON_MSTART0_MSK (0x1fu)
+
+/** \brief Offset for Ifx_STM_CMCON_Bits.MSTART0 */
+#define IFX_STM_CMCON_MSTART0_OFF (8u)
+
+/** \brief Length for Ifx_STM_CMCON_Bits.MSTART1 */
+#define IFX_STM_CMCON_MSTART1_LEN (5u)
+
+/** \brief Mask for Ifx_STM_CMCON_Bits.MSTART1 */
+#define IFX_STM_CMCON_MSTART1_MSK (0x1fu)
+
+/** \brief Offset for Ifx_STM_CMCON_Bits.MSTART1 */
+#define IFX_STM_CMCON_MSTART1_OFF (24u)
+
+/** \brief Length for Ifx_STM_CMP_Bits.CMPVAL */
+#define IFX_STM_CMP_CMPVAL_LEN (32u)
+
+/** \brief Mask for Ifx_STM_CMP_Bits.CMPVAL */
+#define IFX_STM_CMP_CMPVAL_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_STM_CMP_Bits.CMPVAL */
+#define IFX_STM_CMP_CMPVAL_OFF (0u)
+
+/** \brief Length for Ifx_STM_ICR_Bits.CMP0EN */
+#define IFX_STM_ICR_CMP0EN_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ICR_Bits.CMP0EN */
+#define IFX_STM_ICR_CMP0EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ICR_Bits.CMP0EN */
+#define IFX_STM_ICR_CMP0EN_OFF (0u)
+
+/** \brief Length for Ifx_STM_ICR_Bits.CMP0IR */
+#define IFX_STM_ICR_CMP0IR_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ICR_Bits.CMP0IR */
+#define IFX_STM_ICR_CMP0IR_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ICR_Bits.CMP0IR */
+#define IFX_STM_ICR_CMP0IR_OFF (1u)
+
+/** \brief Length for Ifx_STM_ICR_Bits.CMP0OS */
+#define IFX_STM_ICR_CMP0OS_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ICR_Bits.CMP0OS */
+#define IFX_STM_ICR_CMP0OS_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ICR_Bits.CMP0OS */
+#define IFX_STM_ICR_CMP0OS_OFF (2u)
+
+/** \brief Length for Ifx_STM_ICR_Bits.CMP1EN */
+#define IFX_STM_ICR_CMP1EN_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ICR_Bits.CMP1EN */
+#define IFX_STM_ICR_CMP1EN_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ICR_Bits.CMP1EN */
+#define IFX_STM_ICR_CMP1EN_OFF (4u)
+
+/** \brief Length for Ifx_STM_ICR_Bits.CMP1IR */
+#define IFX_STM_ICR_CMP1IR_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ICR_Bits.CMP1IR */
+#define IFX_STM_ICR_CMP1IR_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ICR_Bits.CMP1IR */
+#define IFX_STM_ICR_CMP1IR_OFF (5u)
+
+/** \brief Length for Ifx_STM_ICR_Bits.CMP1OS */
+#define IFX_STM_ICR_CMP1OS_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ICR_Bits.CMP1OS */
+#define IFX_STM_ICR_CMP1OS_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ICR_Bits.CMP1OS */
+#define IFX_STM_ICR_CMP1OS_OFF (6u)
+
+/** \brief Length for Ifx_STM_ID_Bits.MODNUMBER */
+#define IFX_STM_ID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_STM_ID_Bits.MODNUMBER */
+#define IFX_STM_ID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_STM_ID_Bits.MODNUMBER */
+#define IFX_STM_ID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_STM_ID_Bits.MODREV */
+#define IFX_STM_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_STM_ID_Bits.MODREV */
+#define IFX_STM_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_STM_ID_Bits.MODREV */
+#define IFX_STM_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_STM_ID_Bits.MODTYPE */
+#define IFX_STM_ID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_STM_ID_Bits.MODTYPE */
+#define IFX_STM_ID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_STM_ID_Bits.MODTYPE */
+#define IFX_STM_ID_MODTYPE_OFF (8u)
+
+/** \brief Length for Ifx_STM_ISCR_Bits.CMP0IRR */
+#define IFX_STM_ISCR_CMP0IRR_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ISCR_Bits.CMP0IRR */
+#define IFX_STM_ISCR_CMP0IRR_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ISCR_Bits.CMP0IRR */
+#define IFX_STM_ISCR_CMP0IRR_OFF (0u)
+
+/** \brief Length for Ifx_STM_ISCR_Bits.CMP0IRS */
+#define IFX_STM_ISCR_CMP0IRS_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ISCR_Bits.CMP0IRS */
+#define IFX_STM_ISCR_CMP0IRS_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ISCR_Bits.CMP0IRS */
+#define IFX_STM_ISCR_CMP0IRS_OFF (1u)
+
+/** \brief Length for Ifx_STM_ISCR_Bits.CMP1IRR */
+#define IFX_STM_ISCR_CMP1IRR_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ISCR_Bits.CMP1IRR */
+#define IFX_STM_ISCR_CMP1IRR_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ISCR_Bits.CMP1IRR */
+#define IFX_STM_ISCR_CMP1IRR_OFF (2u)
+
+/** \brief Length for Ifx_STM_ISCR_Bits.CMP1IRS */
+#define IFX_STM_ISCR_CMP1IRS_LEN (1u)
+
+/** \brief Mask for Ifx_STM_ISCR_Bits.CMP1IRS */
+#define IFX_STM_ISCR_CMP1IRS_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_ISCR_Bits.CMP1IRS */
+#define IFX_STM_ISCR_CMP1IRS_OFF (3u)
+
+/** \brief Length for Ifx_STM_KRST0_Bits.RST */
+#define IFX_STM_KRST0_RST_LEN (1u)
+
+/** \brief Mask for Ifx_STM_KRST0_Bits.RST */
+#define IFX_STM_KRST0_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_KRST0_Bits.RST */
+#define IFX_STM_KRST0_RST_OFF (0u)
+
+/** \brief Length for Ifx_STM_KRST0_Bits.RSTSTAT */
+#define IFX_STM_KRST0_RSTSTAT_LEN (1u)
+
+/** \brief Mask for Ifx_STM_KRST0_Bits.RSTSTAT */
+#define IFX_STM_KRST0_RSTSTAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_KRST0_Bits.RSTSTAT */
+#define IFX_STM_KRST0_RSTSTAT_OFF (1u)
+
+/** \brief Length for Ifx_STM_KRST1_Bits.RST */
+#define IFX_STM_KRST1_RST_LEN (1u)
+
+/** \brief Mask for Ifx_STM_KRST1_Bits.RST */
+#define IFX_STM_KRST1_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_KRST1_Bits.RST */
+#define IFX_STM_KRST1_RST_OFF (0u)
+
+/** \brief Length for Ifx_STM_KRSTCLR_Bits.CLR */
+#define IFX_STM_KRSTCLR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_STM_KRSTCLR_Bits.CLR */
+#define IFX_STM_KRSTCLR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_KRSTCLR_Bits.CLR */
+#define IFX_STM_KRSTCLR_CLR_OFF (0u)
+
+/** \brief Length for Ifx_STM_OCS_Bits.SUS */
+#define IFX_STM_OCS_SUS_LEN (4u)
+
+/** \brief Mask for Ifx_STM_OCS_Bits.SUS */
+#define IFX_STM_OCS_SUS_MSK (0xfu)
+
+/** \brief Offset for Ifx_STM_OCS_Bits.SUS */
+#define IFX_STM_OCS_SUS_OFF (24u)
+
+/** \brief Length for Ifx_STM_OCS_Bits.SUS_P */
+#define IFX_STM_OCS_SUS_P_LEN (1u)
+
+/** \brief Mask for Ifx_STM_OCS_Bits.SUS_P */
+#define IFX_STM_OCS_SUS_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_OCS_Bits.SUS_P */
+#define IFX_STM_OCS_SUS_P_OFF (28u)
+
+/** \brief Length for Ifx_STM_OCS_Bits.SUSSTA */
+#define IFX_STM_OCS_SUSSTA_LEN (1u)
+
+/** \brief Mask for Ifx_STM_OCS_Bits.SUSSTA */
+#define IFX_STM_OCS_SUSSTA_MSK (0x1u)
+
+/** \brief Offset for Ifx_STM_OCS_Bits.SUSSTA */
+#define IFX_STM_OCS_SUSSTA_OFF (29u)
+
+/** \brief Length for Ifx_STM_TIM0_Bits.STM31_0 */
+#define IFX_STM_TIM0_STM31_0_LEN (32u)
+
+/** \brief Mask for Ifx_STM_TIM0_Bits.STM31_0 */
+#define IFX_STM_TIM0_STM31_0_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_STM_TIM0_Bits.STM31_0 */
+#define IFX_STM_TIM0_STM31_0_OFF (0u)
+
+/** \brief Length for Ifx_STM_TIM0SV_Bits.STM31_0 */
+#define IFX_STM_TIM0SV_STM31_0_LEN (32u)
+
+/** \brief Mask for Ifx_STM_TIM0SV_Bits.STM31_0 */
+#define IFX_STM_TIM0SV_STM31_0_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_STM_TIM0SV_Bits.STM31_0 */
+#define IFX_STM_TIM0SV_STM31_0_OFF (0u)
+
+/** \brief Length for Ifx_STM_TIM1_Bits.STM35_4 */
+#define IFX_STM_TIM1_STM35_4_LEN (32u)
+
+/** \brief Mask for Ifx_STM_TIM1_Bits.STM35_4 */
+#define IFX_STM_TIM1_STM35_4_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_STM_TIM1_Bits.STM35_4 */
+#define IFX_STM_TIM1_STM35_4_OFF (0u)
+
+/** \brief Length for Ifx_STM_TIM2_Bits.STM39_8 */
+#define IFX_STM_TIM2_STM39_8_LEN (32u)
+
+/** \brief Mask for Ifx_STM_TIM2_Bits.STM39_8 */
+#define IFX_STM_TIM2_STM39_8_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_STM_TIM2_Bits.STM39_8 */
+#define IFX_STM_TIM2_STM39_8_OFF (0u)
+
+/** \brief Length for Ifx_STM_TIM3_Bits.STM43_12 */
+#define IFX_STM_TIM3_STM43_12_LEN (32u)
+
+/** \brief Mask for Ifx_STM_TIM3_Bits.STM43_12 */
+#define IFX_STM_TIM3_STM43_12_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_STM_TIM3_Bits.STM43_12 */
+#define IFX_STM_TIM3_STM43_12_OFF (0u)
+
+/** \brief Length for Ifx_STM_TIM4_Bits.STM47_16 */
+#define IFX_STM_TIM4_STM47_16_LEN (32u)
+
+/** \brief Mask for Ifx_STM_TIM4_Bits.STM47_16 */
+#define IFX_STM_TIM4_STM47_16_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_STM_TIM4_Bits.STM47_16 */
+#define IFX_STM_TIM4_STM47_16_OFF (0u)
+
+/** \brief Length for Ifx_STM_TIM5_Bits.STM51_20 */
+#define IFX_STM_TIM5_STM51_20_LEN (32u)
+
+/** \brief Mask for Ifx_STM_TIM5_Bits.STM51_20 */
+#define IFX_STM_TIM5_STM51_20_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_STM_TIM5_Bits.STM51_20 */
+#define IFX_STM_TIM5_STM51_20_OFF (0u)
+
+/** \brief Length for Ifx_STM_TIM6_Bits.STM63_32 */
+#define IFX_STM_TIM6_STM63_32_LEN (32u)
+
+/** \brief Mask for Ifx_STM_TIM6_Bits.STM63_32 */
+#define IFX_STM_TIM6_STM63_32_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_STM_TIM6_Bits.STM63_32 */
+#define IFX_STM_TIM6_STM63_32_OFF (0u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXSTM_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxStm_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxStm_reg.h
new file mode 100644
index 0000000..e9a9040
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxStm_reg.h
@@ -0,0 +1,200 @@
+/**
+ * \file IfxStm_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Stm_Cfg Stm address
+ * \ingroup IfxLld_Stm
+ *
+ * \defgroup IfxLld_Stm_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Stm_Cfg
+ *
+ * \defgroup IfxLld_Stm_Cfg_Stm0 2-STM0
+ * \ingroup IfxLld_Stm_Cfg
+ *
+ * \defgroup IfxLld_Stm_Cfg_Stm1 2-STM1
+ * \ingroup IfxLld_Stm_Cfg
+ *
+ */
+#ifndef IFXSTM_REG_H
+#define IFXSTM_REG_H 1
+/******************************************************************************/
+#include "IfxStm_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Stm_Cfg_BaseAddress
+ * \{ */
+
+/** \brief STM object */
+#define MODULE_STM0 /*lint --e(923)*/ (*(Ifx_STM*)0xF0000000u)
+
+/** \brief STM object */
+#define MODULE_STM1 /*lint --e(923)*/ (*(Ifx_STM*)0xF0000100u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Stm_Cfg_Stm0
+ * \{ */
+
+/** \brief FC, Access Enable Register 0 */
+#define STM0_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_STM_ACCEN0*)0xF00000FCu)
+
+/** \brief F8, Access Enable Register 1 */
+#define STM0_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_STM_ACCEN1*)0xF00000F8u)
+
+/** \brief 2C, Timer Capture Register */
+#define STM0_CAP /*lint --e(923)*/ (*(volatile Ifx_STM_CAP*)0xF000002Cu)
+
+/** \brief 54, Timer Capture Register Second View */
+#define STM0_CAPSV /*lint --e(923)*/ (*(volatile Ifx_STM_CAPSV*)0xF0000054u)
+
+/** \brief 0, Clock Control Register */
+#define STM0_CLC /*lint --e(923)*/ (*(volatile Ifx_STM_CLC*)0xF0000000u)
+
+/** \brief 38, Compare Match Control Register */
+#define STM0_CMCON /*lint --e(923)*/ (*(volatile Ifx_STM_CMCON*)0xF0000038u)
+
+/** \brief 30, Compare Register */
+#define STM0_CMP0 /*lint --e(923)*/ (*(volatile Ifx_STM_CMP*)0xF0000030u)
+
+/** \brief 34, Compare Register */
+#define STM0_CMP1 /*lint --e(923)*/ (*(volatile Ifx_STM_CMP*)0xF0000034u)
+
+/** \brief 3C, Interrupt Control Register */
+#define STM0_ICR /*lint --e(923)*/ (*(volatile Ifx_STM_ICR*)0xF000003Cu)
+
+/** \brief 8, Module Identification Register */
+#define STM0_ID /*lint --e(923)*/ (*(volatile Ifx_STM_ID*)0xF0000008u)
+
+/** \brief 40, Interrupt Set/Clear Register */
+#define STM0_ISCR /*lint --e(923)*/ (*(volatile Ifx_STM_ISCR*)0xF0000040u)
+
+/** \brief F4, Kernel Reset Register 0 */
+#define STM0_KRST0 /*lint --e(923)*/ (*(volatile Ifx_STM_KRST0*)0xF00000F4u)
+
+/** \brief F0, Kernel Reset Register 1 */
+#define STM0_KRST1 /*lint --e(923)*/ (*(volatile Ifx_STM_KRST1*)0xF00000F0u)
+
+/** \brief EC, Kernel Reset Status Clear Register */
+#define STM0_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_STM_KRSTCLR*)0xF00000ECu)
+
+/** \brief E8, OCDS Control and Status */
+#define STM0_OCS /*lint --e(923)*/ (*(volatile Ifx_STM_OCS*)0xF00000E8u)
+
+/** \brief 10, Timer Register 0 */
+#define STM0_TIM0 /*lint --e(923)*/ (*(volatile Ifx_STM_TIM0*)0xF0000010u)
+
+/** \brief 50, Timer Register 0 Second View */
+#define STM0_TIM0SV /*lint --e(923)*/ (*(volatile Ifx_STM_TIM0SV*)0xF0000050u)
+
+/** \brief 14, Timer Register 1 */
+#define STM0_TIM1 /*lint --e(923)*/ (*(volatile Ifx_STM_TIM1*)0xF0000014u)
+
+/** \brief 18, Timer Register 2 */
+#define STM0_TIM2 /*lint --e(923)*/ (*(volatile Ifx_STM_TIM2*)0xF0000018u)
+
+/** \brief 1C, Timer Register 3 */
+#define STM0_TIM3 /*lint --e(923)*/ (*(volatile Ifx_STM_TIM3*)0xF000001Cu)
+
+/** \brief 20, Timer Register 4 */
+#define STM0_TIM4 /*lint --e(923)*/ (*(volatile Ifx_STM_TIM4*)0xF0000020u)
+
+/** \brief 24, Timer Register 5 */
+#define STM0_TIM5 /*lint --e(923)*/ (*(volatile Ifx_STM_TIM5*)0xF0000024u)
+
+/** \brief 28, Timer Register 6 */
+#define STM0_TIM6 /*lint --e(923)*/ (*(volatile Ifx_STM_TIM6*)0xF0000028u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Stm_Cfg_Stm1
+ * \{ */
+
+/** \brief FC, Access Enable Register 0 */
+#define STM1_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_STM_ACCEN0*)0xF00001FCu)
+
+/** \brief F8, Access Enable Register 1 */
+#define STM1_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_STM_ACCEN1*)0xF00001F8u)
+
+/** \brief 2C, Timer Capture Register */
+#define STM1_CAP /*lint --e(923)*/ (*(volatile Ifx_STM_CAP*)0xF000012Cu)
+
+/** \brief 54, Timer Capture Register Second View */
+#define STM1_CAPSV /*lint --e(923)*/ (*(volatile Ifx_STM_CAPSV*)0xF0000154u)
+
+/** \brief 0, Clock Control Register */
+#define STM1_CLC /*lint --e(923)*/ (*(volatile Ifx_STM_CLC*)0xF0000100u)
+
+/** \brief 38, Compare Match Control Register */
+#define STM1_CMCON /*lint --e(923)*/ (*(volatile Ifx_STM_CMCON*)0xF0000138u)
+
+/** \brief 30, Compare Register */
+#define STM1_CMP0 /*lint --e(923)*/ (*(volatile Ifx_STM_CMP*)0xF0000130u)
+
+/** \brief 34, Compare Register */
+#define STM1_CMP1 /*lint --e(923)*/ (*(volatile Ifx_STM_CMP*)0xF0000134u)
+
+/** \brief 3C, Interrupt Control Register */
+#define STM1_ICR /*lint --e(923)*/ (*(volatile Ifx_STM_ICR*)0xF000013Cu)
+
+/** \brief 8, Module Identification Register */
+#define STM1_ID /*lint --e(923)*/ (*(volatile Ifx_STM_ID*)0xF0000108u)
+
+/** \brief 40, Interrupt Set/Clear Register */
+#define STM1_ISCR /*lint --e(923)*/ (*(volatile Ifx_STM_ISCR*)0xF0000140u)
+
+/** \brief F4, Kernel Reset Register 0 */
+#define STM1_KRST0 /*lint --e(923)*/ (*(volatile Ifx_STM_KRST0*)0xF00001F4u)
+
+/** \brief F0, Kernel Reset Register 1 */
+#define STM1_KRST1 /*lint --e(923)*/ (*(volatile Ifx_STM_KRST1*)0xF00001F0u)
+
+/** \brief EC, Kernel Reset Status Clear Register */
+#define STM1_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_STM_KRSTCLR*)0xF00001ECu)
+
+/** \brief E8, OCDS Control and Status */
+#define STM1_OCS /*lint --e(923)*/ (*(volatile Ifx_STM_OCS*)0xF00001E8u)
+
+/** \brief 10, Timer Register 0 */
+#define STM1_TIM0 /*lint --e(923)*/ (*(volatile Ifx_STM_TIM0*)0xF0000110u)
+
+/** \brief 50, Timer Register 0 Second View */
+#define STM1_TIM0SV /*lint --e(923)*/ (*(volatile Ifx_STM_TIM0SV*)0xF0000150u)
+
+/** \brief 14, Timer Register 1 */
+#define STM1_TIM1 /*lint --e(923)*/ (*(volatile Ifx_STM_TIM1*)0xF0000114u)
+
+/** \brief 18, Timer Register 2 */
+#define STM1_TIM2 /*lint --e(923)*/ (*(volatile Ifx_STM_TIM2*)0xF0000118u)
+
+/** \brief 1C, Timer Register 3 */
+#define STM1_TIM3 /*lint --e(923)*/ (*(volatile Ifx_STM_TIM3*)0xF000011Cu)
+
+/** \brief 20, Timer Register 4 */
+#define STM1_TIM4 /*lint --e(923)*/ (*(volatile Ifx_STM_TIM4*)0xF0000120u)
+
+/** \brief 24, Timer Register 5 */
+#define STM1_TIM5 /*lint --e(923)*/ (*(volatile Ifx_STM_TIM5*)0xF0000124u)
+
+/** \brief 28, Timer Register 6 */
+#define STM1_TIM6 /*lint --e(923)*/ (*(volatile Ifx_STM_TIM6*)0xF0000128u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXSTM_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxStm_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxStm_regdef.h
new file mode 100644
index 0000000..d7703ac
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxStm_regdef.h
@@ -0,0 +1,463 @@
+/**
+ * \file IfxStm_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Stm Stm
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Stm_Bitfields Bitfields
+ * \ingroup IfxLld_Stm
+ *
+ * \defgroup IfxLld_Stm_union Union
+ * \ingroup IfxLld_Stm
+ *
+ * \defgroup IfxLld_Stm_struct Struct
+ * \ingroup IfxLld_Stm
+ *
+ */
+#ifndef IFXSTM_REGDEF_H
+#define IFXSTM_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Stm_Bitfields
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef struct _Ifx_STM_ACCEN0_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_STM_ACCEN0_Bits;
+
+/** \brief Access Enable Register 1 */
+typedef struct _Ifx_STM_ACCEN1_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_STM_ACCEN1_Bits;
+
+/** \brief Timer Capture Register */
+typedef struct _Ifx_STM_CAP_Bits
+{
+ unsigned int STMCAP63_32:32; /**< \brief [31:0] Captured System Timer Bits [63:32] (rh) */
+} Ifx_STM_CAP_Bits;
+
+/** \brief Timer Capture Register Second View */
+typedef struct _Ifx_STM_CAPSV_Bits
+{
+ unsigned int STMCAP63_32:32; /**< \brief [31:0] Captured System Timer Bits [63:32] (rh) */
+} Ifx_STM_CAPSV_Bits;
+
+/** \brief Clock Control Register */
+typedef struct _Ifx_STM_CLC_Bits
+{
+ unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
+ unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (r) */
+ unsigned int reserved_2:1; /**< \brief \internal Reserved */
+ unsigned int EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control (rw) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_STM_CLC_Bits;
+
+/** \brief Compare Match Control Register */
+typedef struct _Ifx_STM_CMCON_Bits
+{
+ unsigned int MSIZE0:5; /**< \brief [4:0] Compare Register Size for CMP0 (rw) */
+ unsigned int reserved_5:3; /**< \brief \internal Reserved */
+ unsigned int MSTART0:5; /**< \brief [12:8] Start Bit Location for CMP0 (rw) */
+ unsigned int reserved_13:3; /**< \brief \internal Reserved */
+ unsigned int MSIZE1:5; /**< \brief [20:16] Compare Register Size for CMP1 (rw) */
+ unsigned int reserved_21:3; /**< \brief \internal Reserved */
+ unsigned int MSTART1:5; /**< \brief [28:24] Start Bit Location for CMP1 (rw) */
+ unsigned int reserved_29:3; /**< \brief \internal Reserved */
+} Ifx_STM_CMCON_Bits;
+
+/** \brief Compare Register */
+typedef struct _Ifx_STM_CMP_Bits
+{
+ unsigned int CMPVAL:32; /**< \brief [31:0] Compare Value of Compare Register x (rw) */
+} Ifx_STM_CMP_Bits;
+
+/** \brief Interrupt Control Register */
+typedef struct _Ifx_STM_ICR_Bits
+{
+ unsigned int CMP0EN:1; /**< \brief [0:0] Compare Register CMP0 Interrupt Enable Control (rw) */
+ unsigned int CMP0IR:1; /**< \brief [1:1] Compare Register CMP0 Interrupt Request Flag (rh) */
+ unsigned int CMP0OS:1; /**< \brief [2:2] Compare Register CMP0 Interrupt Output Selection (rw) */
+ unsigned int reserved_3:1; /**< \brief \internal Reserved */
+ unsigned int CMP1EN:1; /**< \brief [4:4] Compare Register CMP1 Interrupt Enable Control (rw) */
+ unsigned int CMP1IR:1; /**< \brief [5:5] Compare Register CMP1 Interrupt Request Flag (rh) */
+ unsigned int CMP1OS:1; /**< \brief [6:6] Compare Register CMP1 Interrupt Output Selection (rw) */
+ unsigned int reserved_7:25; /**< \brief \internal Reserved */
+} Ifx_STM_ICR_Bits;
+
+/** \brief Module Identification Register */
+typedef struct _Ifx_STM_ID_Bits
+{
+ unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
+ unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_STM_ID_Bits;
+
+/** \brief Interrupt Set/Clear Register */
+typedef struct _Ifx_STM_ISCR_Bits
+{
+ unsigned int CMP0IRR:1; /**< \brief [0:0] Reset Compare Register CMP0 Interrupt Flag (w) */
+ unsigned int CMP0IRS:1; /**< \brief [1:1] Set Compare Register CMP0 Interrupt Flag (w) */
+ unsigned int CMP1IRR:1; /**< \brief [2:2] Reset Compare Register CMP1 Interrupt Flag (w) */
+ unsigned int CMP1IRS:1; /**< \brief [3:3] Set Compare Register CMP1 Interrupt Flag (w) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_STM_ISCR_Bits;
+
+/** \brief Kernel Reset Register 0 */
+typedef struct _Ifx_STM_KRST0_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rw) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_STM_KRST0_Bits;
+
+/** \brief Kernel Reset Register 1 */
+typedef struct _Ifx_STM_KRST1_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_STM_KRST1_Bits;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef struct _Ifx_STM_KRSTCLR_Bits
+{
+ unsigned int CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_STM_KRSTCLR_Bits;
+
+/** \brief OCDS Control and Status */
+typedef struct _Ifx_STM_OCS_Bits
+{
+ unsigned int reserved_0:24; /**< \brief \internal Reserved */
+ unsigned int SUS:4; /**< \brief [27:24] OCDS Suspend Control (rw) */
+ unsigned int SUS_P:1; /**< \brief [28:28] SUS Write Protection (w) */
+ unsigned int SUSSTA:1; /**< \brief [29:29] Suspend State (rh) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_STM_OCS_Bits;
+
+/** \brief Timer Register 0 */
+typedef struct _Ifx_STM_TIM0_Bits
+{
+ unsigned int STM31_0:32; /**< \brief [31:0] System Timer Bits [31:0] (r) */
+} Ifx_STM_TIM0_Bits;
+
+/** \brief Timer Register 0 Second View */
+typedef struct _Ifx_STM_TIM0SV_Bits
+{
+ unsigned int STM31_0:32; /**< \brief [31:0] System Timer Bits [31:0] (r) */
+} Ifx_STM_TIM0SV_Bits;
+
+/** \brief Timer Register 1 */
+typedef struct _Ifx_STM_TIM1_Bits
+{
+ unsigned int STM35_4:32; /**< \brief [31:0] System Timer Bits [35:4] (r) */
+} Ifx_STM_TIM1_Bits;
+
+/** \brief Timer Register 2 */
+typedef struct _Ifx_STM_TIM2_Bits
+{
+ unsigned int STM39_8:32; /**< \brief [31:0] System Timer Bits [39:8] (r) */
+} Ifx_STM_TIM2_Bits;
+
+/** \brief Timer Register 3 */
+typedef struct _Ifx_STM_TIM3_Bits
+{
+ unsigned int STM43_12:32; /**< \brief [31:0] System Timer Bits [43:12] (r) */
+} Ifx_STM_TIM3_Bits;
+
+/** \brief Timer Register 4 */
+typedef struct _Ifx_STM_TIM4_Bits
+{
+ unsigned int STM47_16:32; /**< \brief [31:0] System Timer Bits [47:16] (r) */
+} Ifx_STM_TIM4_Bits;
+
+/** \brief Timer Register 5 */
+typedef struct _Ifx_STM_TIM5_Bits
+{
+ unsigned int STM51_20:32; /**< \brief [31:0] System Timer Bits [51:20] (r) */
+} Ifx_STM_TIM5_Bits;
+
+/** \brief Timer Register 6 */
+typedef struct _Ifx_STM_TIM6_Bits
+{
+ unsigned int STM63_32:32; /**< \brief [31:0] System Timer Bits [63:32] (r) */
+} Ifx_STM_TIM6_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Stm_union
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_STM_ACCEN0_Bits B; /**< \brief Bitfield access */
+} Ifx_STM_ACCEN0;
+
+/** \brief Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_STM_ACCEN1_Bits B; /**< \brief Bitfield access */
+} Ifx_STM_ACCEN1;
+
+/** \brief Timer Capture Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_STM_CAP_Bits B; /**< \brief Bitfield access */
+} Ifx_STM_CAP;
+
+/** \brief Timer Capture Register Second View */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_STM_CAPSV_Bits B; /**< \brief Bitfield access */
+} Ifx_STM_CAPSV;
+
+/** \brief Clock Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_STM_CLC_Bits B; /**< \brief Bitfield access */
+} Ifx_STM_CLC;
+
+/** \brief Compare Match Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_STM_CMCON_Bits B; /**< \brief Bitfield access */
+} Ifx_STM_CMCON;
+
+/** \brief Compare Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_STM_CMP_Bits B; /**< \brief Bitfield access */
+} Ifx_STM_CMP;
+
+/** \brief Interrupt Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_STM_ICR_Bits B; /**< \brief Bitfield access */
+} Ifx_STM_ICR;
+
+/** \brief Module Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_STM_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_STM_ID;
+
+/** \brief Interrupt Set/Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_STM_ISCR_Bits B; /**< \brief Bitfield access */
+} Ifx_STM_ISCR;
+
+/** \brief Kernel Reset Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_STM_KRST0_Bits B; /**< \brief Bitfield access */
+} Ifx_STM_KRST0;
+
+/** \brief Kernel Reset Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_STM_KRST1_Bits B; /**< \brief Bitfield access */
+} Ifx_STM_KRST1;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_STM_KRSTCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_STM_KRSTCLR;
+
+/** \brief OCDS Control and Status */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_STM_OCS_Bits B; /**< \brief Bitfield access */
+} Ifx_STM_OCS;
+
+/** \brief Timer Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_STM_TIM0_Bits B; /**< \brief Bitfield access */
+} Ifx_STM_TIM0;
+
+/** \brief Timer Register 0 Second View */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_STM_TIM0SV_Bits B; /**< \brief Bitfield access */
+} Ifx_STM_TIM0SV;
+
+/** \brief Timer Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_STM_TIM1_Bits B; /**< \brief Bitfield access */
+} Ifx_STM_TIM1;
+
+/** \brief Timer Register 2 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_STM_TIM2_Bits B; /**< \brief Bitfield access */
+} Ifx_STM_TIM2;
+
+/** \brief Timer Register 3 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_STM_TIM3_Bits B; /**< \brief Bitfield access */
+} Ifx_STM_TIM3;
+
+/** \brief Timer Register 4 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_STM_TIM4_Bits B; /**< \brief Bitfield access */
+} Ifx_STM_TIM4;
+
+/** \brief Timer Register 5 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_STM_TIM5_Bits B; /**< \brief Bitfield access */
+} Ifx_STM_TIM5;
+
+/** \brief Timer Register 6 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_STM_TIM6_Bits B; /**< \brief Bitfield access */
+} Ifx_STM_TIM6;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Stm_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief STM object */
+typedef volatile struct _Ifx_STM
+{
+ Ifx_STM_CLC CLC; /**< \brief 0, Clock Control Register */
+ unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
+ Ifx_STM_ID ID; /**< \brief 8, Module Identification Register */
+ unsigned char reserved_C[4]; /**< \brief C, \internal Reserved */
+ Ifx_STM_TIM0 TIM0; /**< \brief 10, Timer Register 0 */
+ Ifx_STM_TIM1 TIM1; /**< \brief 14, Timer Register 1 */
+ Ifx_STM_TIM2 TIM2; /**< \brief 18, Timer Register 2 */
+ Ifx_STM_TIM3 TIM3; /**< \brief 1C, Timer Register 3 */
+ Ifx_STM_TIM4 TIM4; /**< \brief 20, Timer Register 4 */
+ Ifx_STM_TIM5 TIM5; /**< \brief 24, Timer Register 5 */
+ Ifx_STM_TIM6 TIM6; /**< \brief 28, Timer Register 6 */
+ Ifx_STM_CAP CAP; /**< \brief 2C, Timer Capture Register */
+ Ifx_STM_CMP CMP[2]; /**< \brief 30, Compare Register */
+ Ifx_STM_CMCON CMCON; /**< \brief 38, Compare Match Control Register */
+ Ifx_STM_ICR ICR; /**< \brief 3C, Interrupt Control Register */
+ Ifx_STM_ISCR ISCR; /**< \brief 40, Interrupt Set/Clear Register */
+ unsigned char reserved_44[12]; /**< \brief 44, \internal Reserved */
+ Ifx_STM_TIM0SV TIM0SV; /**< \brief 50, Timer Register 0 Second View */
+ Ifx_STM_CAPSV CAPSV; /**< \brief 54, Timer Capture Register Second View */
+ unsigned char reserved_58[144]; /**< \brief 58, \internal Reserved */
+ Ifx_STM_OCS OCS; /**< \brief E8, OCDS Control and Status */
+ Ifx_STM_KRSTCLR KRSTCLR; /**< \brief EC, Kernel Reset Status Clear Register */
+ Ifx_STM_KRST1 KRST1; /**< \brief F0, Kernel Reset Register 1 */
+ Ifx_STM_KRST0 KRST0; /**< \brief F4, Kernel Reset Register 0 */
+ Ifx_STM_ACCEN1 ACCEN1; /**< \brief F8, Access Enable Register 1 */
+ Ifx_STM_ACCEN0 ACCEN0; /**< \brief FC, Access Enable Register 0 */
+} Ifx_STM;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXSTM_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxVadc_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxVadc_bf.h
new file mode 100644
index 0000000..7e62930
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxVadc_bf.h
@@ -0,0 +1,4194 @@
+/**
+ * \file IfxVadc_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Vadc_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Vadc
+ *
+ */
+#ifndef IFXVADC_BF_H
+#define IFXVADC_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Vadc_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN0 */
+#define IFX_VADC_ACCEN0_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN0 */
+#define IFX_VADC_ACCEN0_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN0 */
+#define IFX_VADC_ACCEN0_EN0_OFF (0u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN10 */
+#define IFX_VADC_ACCEN0_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN10 */
+#define IFX_VADC_ACCEN0_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN10 */
+#define IFX_VADC_ACCEN0_EN10_OFF (10u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN11 */
+#define IFX_VADC_ACCEN0_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN11 */
+#define IFX_VADC_ACCEN0_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN11 */
+#define IFX_VADC_ACCEN0_EN11_OFF (11u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN12 */
+#define IFX_VADC_ACCEN0_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN12 */
+#define IFX_VADC_ACCEN0_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN12 */
+#define IFX_VADC_ACCEN0_EN12_OFF (12u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN13 */
+#define IFX_VADC_ACCEN0_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN13 */
+#define IFX_VADC_ACCEN0_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN13 */
+#define IFX_VADC_ACCEN0_EN13_OFF (13u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN14 */
+#define IFX_VADC_ACCEN0_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN14 */
+#define IFX_VADC_ACCEN0_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN14 */
+#define IFX_VADC_ACCEN0_EN14_OFF (14u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN15 */
+#define IFX_VADC_ACCEN0_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN15 */
+#define IFX_VADC_ACCEN0_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN15 */
+#define IFX_VADC_ACCEN0_EN15_OFF (15u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN16 */
+#define IFX_VADC_ACCEN0_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN16 */
+#define IFX_VADC_ACCEN0_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN16 */
+#define IFX_VADC_ACCEN0_EN16_OFF (16u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN17 */
+#define IFX_VADC_ACCEN0_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN17 */
+#define IFX_VADC_ACCEN0_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN17 */
+#define IFX_VADC_ACCEN0_EN17_OFF (17u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN18 */
+#define IFX_VADC_ACCEN0_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN18 */
+#define IFX_VADC_ACCEN0_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN18 */
+#define IFX_VADC_ACCEN0_EN18_OFF (18u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN19 */
+#define IFX_VADC_ACCEN0_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN19 */
+#define IFX_VADC_ACCEN0_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN19 */
+#define IFX_VADC_ACCEN0_EN19_OFF (19u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN1 */
+#define IFX_VADC_ACCEN0_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN1 */
+#define IFX_VADC_ACCEN0_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN1 */
+#define IFX_VADC_ACCEN0_EN1_OFF (1u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN20 */
+#define IFX_VADC_ACCEN0_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN20 */
+#define IFX_VADC_ACCEN0_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN20 */
+#define IFX_VADC_ACCEN0_EN20_OFF (20u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN21 */
+#define IFX_VADC_ACCEN0_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN21 */
+#define IFX_VADC_ACCEN0_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN21 */
+#define IFX_VADC_ACCEN0_EN21_OFF (21u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN22 */
+#define IFX_VADC_ACCEN0_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN22 */
+#define IFX_VADC_ACCEN0_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN22 */
+#define IFX_VADC_ACCEN0_EN22_OFF (22u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN23 */
+#define IFX_VADC_ACCEN0_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN23 */
+#define IFX_VADC_ACCEN0_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN23 */
+#define IFX_VADC_ACCEN0_EN23_OFF (23u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN24 */
+#define IFX_VADC_ACCEN0_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN24 */
+#define IFX_VADC_ACCEN0_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN24 */
+#define IFX_VADC_ACCEN0_EN24_OFF (24u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN25 */
+#define IFX_VADC_ACCEN0_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN25 */
+#define IFX_VADC_ACCEN0_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN25 */
+#define IFX_VADC_ACCEN0_EN25_OFF (25u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN26 */
+#define IFX_VADC_ACCEN0_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN26 */
+#define IFX_VADC_ACCEN0_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN26 */
+#define IFX_VADC_ACCEN0_EN26_OFF (26u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN27 */
+#define IFX_VADC_ACCEN0_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN27 */
+#define IFX_VADC_ACCEN0_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN27 */
+#define IFX_VADC_ACCEN0_EN27_OFF (27u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN28 */
+#define IFX_VADC_ACCEN0_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN28 */
+#define IFX_VADC_ACCEN0_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN28 */
+#define IFX_VADC_ACCEN0_EN28_OFF (28u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN29 */
+#define IFX_VADC_ACCEN0_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN29 */
+#define IFX_VADC_ACCEN0_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN29 */
+#define IFX_VADC_ACCEN0_EN29_OFF (29u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN2 */
+#define IFX_VADC_ACCEN0_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN2 */
+#define IFX_VADC_ACCEN0_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN2 */
+#define IFX_VADC_ACCEN0_EN2_OFF (2u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN30 */
+#define IFX_VADC_ACCEN0_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN30 */
+#define IFX_VADC_ACCEN0_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN30 */
+#define IFX_VADC_ACCEN0_EN30_OFF (30u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN31 */
+#define IFX_VADC_ACCEN0_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN31 */
+#define IFX_VADC_ACCEN0_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN31 */
+#define IFX_VADC_ACCEN0_EN31_OFF (31u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN3 */
+#define IFX_VADC_ACCEN0_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN3 */
+#define IFX_VADC_ACCEN0_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN3 */
+#define IFX_VADC_ACCEN0_EN3_OFF (3u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN4 */
+#define IFX_VADC_ACCEN0_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN4 */
+#define IFX_VADC_ACCEN0_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN4 */
+#define IFX_VADC_ACCEN0_EN4_OFF (4u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN5 */
+#define IFX_VADC_ACCEN0_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN5 */
+#define IFX_VADC_ACCEN0_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN5 */
+#define IFX_VADC_ACCEN0_EN5_OFF (5u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN6 */
+#define IFX_VADC_ACCEN0_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN6 */
+#define IFX_VADC_ACCEN0_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN6 */
+#define IFX_VADC_ACCEN0_EN6_OFF (6u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN7 */
+#define IFX_VADC_ACCEN0_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN7 */
+#define IFX_VADC_ACCEN0_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN7 */
+#define IFX_VADC_ACCEN0_EN7_OFF (7u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN8 */
+#define IFX_VADC_ACCEN0_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN8 */
+#define IFX_VADC_ACCEN0_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN8 */
+#define IFX_VADC_ACCEN0_EN8_OFF (8u)
+
+/** \brief Length for Ifx_VADC_ACCEN0_Bits.EN9 */
+#define IFX_VADC_ACCEN0_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCEN0_Bits.EN9 */
+#define IFX_VADC_ACCEN0_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCEN0_Bits.EN9 */
+#define IFX_VADC_ACCEN0_EN9_OFF (9u)
+
+/** \brief Length for Ifx_VADC_ACCPROT0_Bits.APC0 */
+#define IFX_VADC_ACCPROT0_APC0_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCPROT0_Bits.APC0 */
+#define IFX_VADC_ACCPROT0_APC0_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCPROT0_Bits.APC0 */
+#define IFX_VADC_ACCPROT0_APC0_OFF (0u)
+
+/** \brief Length for Ifx_VADC_ACCPROT0_Bits.APC1 */
+#define IFX_VADC_ACCPROT0_APC1_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCPROT0_Bits.APC1 */
+#define IFX_VADC_ACCPROT0_APC1_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCPROT0_Bits.APC1 */
+#define IFX_VADC_ACCPROT0_APC1_OFF (1u)
+
+/** \brief Length for Ifx_VADC_ACCPROT0_Bits.APC2 */
+#define IFX_VADC_ACCPROT0_APC2_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCPROT0_Bits.APC2 */
+#define IFX_VADC_ACCPROT0_APC2_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCPROT0_Bits.APC2 */
+#define IFX_VADC_ACCPROT0_APC2_OFF (2u)
+
+/** \brief Length for Ifx_VADC_ACCPROT0_Bits.APC3 */
+#define IFX_VADC_ACCPROT0_APC3_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCPROT0_Bits.APC3 */
+#define IFX_VADC_ACCPROT0_APC3_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCPROT0_Bits.APC3 */
+#define IFX_VADC_ACCPROT0_APC3_OFF (3u)
+
+/** \brief Length for Ifx_VADC_ACCPROT0_Bits.APEM */
+#define IFX_VADC_ACCPROT0_APEM_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCPROT0_Bits.APEM */
+#define IFX_VADC_ACCPROT0_APEM_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCPROT0_Bits.APEM */
+#define IFX_VADC_ACCPROT0_APEM_OFF (15u)
+
+/** \brief Length for Ifx_VADC_ACCPROT0_Bits.APGC */
+#define IFX_VADC_ACCPROT0_APGC_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCPROT0_Bits.APGC */
+#define IFX_VADC_ACCPROT0_APGC_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCPROT0_Bits.APGC */
+#define IFX_VADC_ACCPROT0_APGC_OFF (31u)
+
+/** \brief Length for Ifx_VADC_ACCPROT0_Bits.API0 */
+#define IFX_VADC_ACCPROT0_API0_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCPROT0_Bits.API0 */
+#define IFX_VADC_ACCPROT0_API0_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCPROT0_Bits.API0 */
+#define IFX_VADC_ACCPROT0_API0_OFF (16u)
+
+/** \brief Length for Ifx_VADC_ACCPROT0_Bits.API1 */
+#define IFX_VADC_ACCPROT0_API1_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCPROT0_Bits.API1 */
+#define IFX_VADC_ACCPROT0_API1_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCPROT0_Bits.API1 */
+#define IFX_VADC_ACCPROT0_API1_OFF (17u)
+
+/** \brief Length for Ifx_VADC_ACCPROT0_Bits.API2 */
+#define IFX_VADC_ACCPROT0_API2_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCPROT0_Bits.API2 */
+#define IFX_VADC_ACCPROT0_API2_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCPROT0_Bits.API2 */
+#define IFX_VADC_ACCPROT0_API2_OFF (18u)
+
+/** \brief Length for Ifx_VADC_ACCPROT0_Bits.API3 */
+#define IFX_VADC_ACCPROT0_API3_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCPROT0_Bits.API3 */
+#define IFX_VADC_ACCPROT0_API3_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCPROT0_Bits.API3 */
+#define IFX_VADC_ACCPROT0_API3_OFF (19u)
+
+/** \brief Length for Ifx_VADC_ACCPROT1_Bits.APR0 */
+#define IFX_VADC_ACCPROT1_APR0_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCPROT1_Bits.APR0 */
+#define IFX_VADC_ACCPROT1_APR0_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCPROT1_Bits.APR0 */
+#define IFX_VADC_ACCPROT1_APR0_OFF (16u)
+
+/** \brief Length for Ifx_VADC_ACCPROT1_Bits.APR1 */
+#define IFX_VADC_ACCPROT1_APR1_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCPROT1_Bits.APR1 */
+#define IFX_VADC_ACCPROT1_APR1_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCPROT1_Bits.APR1 */
+#define IFX_VADC_ACCPROT1_APR1_OFF (17u)
+
+/** \brief Length for Ifx_VADC_ACCPROT1_Bits.APR2 */
+#define IFX_VADC_ACCPROT1_APR2_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCPROT1_Bits.APR2 */
+#define IFX_VADC_ACCPROT1_APR2_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCPROT1_Bits.APR2 */
+#define IFX_VADC_ACCPROT1_APR2_OFF (18u)
+
+/** \brief Length for Ifx_VADC_ACCPROT1_Bits.APR3 */
+#define IFX_VADC_ACCPROT1_APR3_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCPROT1_Bits.APR3 */
+#define IFX_VADC_ACCPROT1_APR3_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCPROT1_Bits.APR3 */
+#define IFX_VADC_ACCPROT1_APR3_OFF (19u)
+
+/** \brief Length for Ifx_VADC_ACCPROT1_Bits.APS0 */
+#define IFX_VADC_ACCPROT1_APS0_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCPROT1_Bits.APS0 */
+#define IFX_VADC_ACCPROT1_APS0_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCPROT1_Bits.APS0 */
+#define IFX_VADC_ACCPROT1_APS0_OFF (0u)
+
+/** \brief Length for Ifx_VADC_ACCPROT1_Bits.APS1 */
+#define IFX_VADC_ACCPROT1_APS1_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCPROT1_Bits.APS1 */
+#define IFX_VADC_ACCPROT1_APS1_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCPROT1_Bits.APS1 */
+#define IFX_VADC_ACCPROT1_APS1_OFF (1u)
+
+/** \brief Length for Ifx_VADC_ACCPROT1_Bits.APS2 */
+#define IFX_VADC_ACCPROT1_APS2_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCPROT1_Bits.APS2 */
+#define IFX_VADC_ACCPROT1_APS2_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCPROT1_Bits.APS2 */
+#define IFX_VADC_ACCPROT1_APS2_OFF (2u)
+
+/** \brief Length for Ifx_VADC_ACCPROT1_Bits.APS3 */
+#define IFX_VADC_ACCPROT1_APS3_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCPROT1_Bits.APS3 */
+#define IFX_VADC_ACCPROT1_APS3_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCPROT1_Bits.APS3 */
+#define IFX_VADC_ACCPROT1_APS3_OFF (3u)
+
+/** \brief Length for Ifx_VADC_ACCPROT1_Bits.APTF */
+#define IFX_VADC_ACCPROT1_APTF_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_ACCPROT1_Bits.APTF */
+#define IFX_VADC_ACCPROT1_APTF_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_ACCPROT1_Bits.APTF */
+#define IFX_VADC_ACCPROT1_APTF_OFF (15u)
+
+/** \brief Length for Ifx_VADC_BRSCTRL_Bits.GTLVL */
+#define IFX_VADC_BRSCTRL_GTLVL_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_BRSCTRL_Bits.GTLVL */
+#define IFX_VADC_BRSCTRL_GTLVL_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_BRSCTRL_Bits.GTLVL */
+#define IFX_VADC_BRSCTRL_GTLVL_OFF (20u)
+
+/** \brief Length for Ifx_VADC_BRSCTRL_Bits.GTSEL */
+#define IFX_VADC_BRSCTRL_GTSEL_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_BRSCTRL_Bits.GTSEL */
+#define IFX_VADC_BRSCTRL_GTSEL_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_BRSCTRL_Bits.GTSEL */
+#define IFX_VADC_BRSCTRL_GTSEL_OFF (16u)
+
+/** \brief Length for Ifx_VADC_BRSCTRL_Bits.GTWC */
+#define IFX_VADC_BRSCTRL_GTWC_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_BRSCTRL_Bits.GTWC */
+#define IFX_VADC_BRSCTRL_GTWC_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_BRSCTRL_Bits.GTWC */
+#define IFX_VADC_BRSCTRL_GTWC_OFF (23u)
+
+/** \brief Length for Ifx_VADC_BRSCTRL_Bits.SRCRESREG */
+#define IFX_VADC_BRSCTRL_SRCRESREG_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_BRSCTRL_Bits.SRCRESREG */
+#define IFX_VADC_BRSCTRL_SRCRESREG_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_BRSCTRL_Bits.SRCRESREG */
+#define IFX_VADC_BRSCTRL_SRCRESREG_OFF (0u)
+
+/** \brief Length for Ifx_VADC_BRSCTRL_Bits.XTLVL */
+#define IFX_VADC_BRSCTRL_XTLVL_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_BRSCTRL_Bits.XTLVL */
+#define IFX_VADC_BRSCTRL_XTLVL_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_BRSCTRL_Bits.XTLVL */
+#define IFX_VADC_BRSCTRL_XTLVL_OFF (12u)
+
+/** \brief Length for Ifx_VADC_BRSCTRL_Bits.XTMODE */
+#define IFX_VADC_BRSCTRL_XTMODE_LEN (2u)
+
+/** \brief Mask for Ifx_VADC_BRSCTRL_Bits.XTMODE */
+#define IFX_VADC_BRSCTRL_XTMODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_VADC_BRSCTRL_Bits.XTMODE */
+#define IFX_VADC_BRSCTRL_XTMODE_OFF (13u)
+
+/** \brief Length for Ifx_VADC_BRSCTRL_Bits.XTSEL */
+#define IFX_VADC_BRSCTRL_XTSEL_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_BRSCTRL_Bits.XTSEL */
+#define IFX_VADC_BRSCTRL_XTSEL_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_BRSCTRL_Bits.XTSEL */
+#define IFX_VADC_BRSCTRL_XTSEL_OFF (8u)
+
+/** \brief Length for Ifx_VADC_BRSCTRL_Bits.XTWC */
+#define IFX_VADC_BRSCTRL_XTWC_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_BRSCTRL_Bits.XTWC */
+#define IFX_VADC_BRSCTRL_XTWC_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_BRSCTRL_Bits.XTWC */
+#define IFX_VADC_BRSCTRL_XTWC_OFF (15u)
+
+/** \brief Length for Ifx_VADC_BRSMR_Bits.CLRPND */
+#define IFX_VADC_BRSMR_CLRPND_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_BRSMR_Bits.CLRPND */
+#define IFX_VADC_BRSMR_CLRPND_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_BRSMR_Bits.CLRPND */
+#define IFX_VADC_BRSMR_CLRPND_OFF (8u)
+
+/** \brief Length for Ifx_VADC_BRSMR_Bits.ENGT */
+#define IFX_VADC_BRSMR_ENGT_LEN (2u)
+
+/** \brief Mask for Ifx_VADC_BRSMR_Bits.ENGT */
+#define IFX_VADC_BRSMR_ENGT_MSK (0x3u)
+
+/** \brief Offset for Ifx_VADC_BRSMR_Bits.ENGT */
+#define IFX_VADC_BRSMR_ENGT_OFF (0u)
+
+/** \brief Length for Ifx_VADC_BRSMR_Bits.ENSI */
+#define IFX_VADC_BRSMR_ENSI_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_BRSMR_Bits.ENSI */
+#define IFX_VADC_BRSMR_ENSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_BRSMR_Bits.ENSI */
+#define IFX_VADC_BRSMR_ENSI_OFF (3u)
+
+/** \brief Length for Ifx_VADC_BRSMR_Bits.ENTR */
+#define IFX_VADC_BRSMR_ENTR_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_BRSMR_Bits.ENTR */
+#define IFX_VADC_BRSMR_ENTR_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_BRSMR_Bits.ENTR */
+#define IFX_VADC_BRSMR_ENTR_OFF (2u)
+
+/** \brief Length for Ifx_VADC_BRSMR_Bits.LDEV */
+#define IFX_VADC_BRSMR_LDEV_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_BRSMR_Bits.LDEV */
+#define IFX_VADC_BRSMR_LDEV_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_BRSMR_Bits.LDEV */
+#define IFX_VADC_BRSMR_LDEV_OFF (9u)
+
+/** \brief Length for Ifx_VADC_BRSMR_Bits.LDM */
+#define IFX_VADC_BRSMR_LDM_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_BRSMR_Bits.LDM */
+#define IFX_VADC_BRSMR_LDM_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_BRSMR_Bits.LDM */
+#define IFX_VADC_BRSMR_LDM_OFF (5u)
+
+/** \brief Length for Ifx_VADC_BRSMR_Bits.REQGT */
+#define IFX_VADC_BRSMR_REQGT_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_BRSMR_Bits.REQGT */
+#define IFX_VADC_BRSMR_REQGT_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_BRSMR_Bits.REQGT */
+#define IFX_VADC_BRSMR_REQGT_OFF (7u)
+
+/** \brief Length for Ifx_VADC_BRSMR_Bits.RPTDIS */
+#define IFX_VADC_BRSMR_RPTDIS_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_BRSMR_Bits.RPTDIS */
+#define IFX_VADC_BRSMR_RPTDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_BRSMR_Bits.RPTDIS */
+#define IFX_VADC_BRSMR_RPTDIS_OFF (16u)
+
+/** \brief Length for Ifx_VADC_BRSMR_Bits.SCAN */
+#define IFX_VADC_BRSMR_SCAN_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_BRSMR_Bits.SCAN */
+#define IFX_VADC_BRSMR_SCAN_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_BRSMR_Bits.SCAN */
+#define IFX_VADC_BRSMR_SCAN_OFF (4u)
+
+/** \brief Length for Ifx_VADC_BRSPND_Bits.CHPNDGy */
+#define IFX_VADC_BRSPND_CHPNDGY_LEN (32u)
+
+/** \brief Mask for Ifx_VADC_BRSPND_Bits.CHPNDGy */
+#define IFX_VADC_BRSPND_CHPNDGY_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_VADC_BRSPND_Bits.CHPNDGy */
+#define IFX_VADC_BRSPND_CHPNDGY_OFF (0u)
+
+/** \brief Length for Ifx_VADC_BRSSEL_Bits.CHSELGy */
+#define IFX_VADC_BRSSEL_CHSELGY_LEN (32u)
+
+/** \brief Mask for Ifx_VADC_BRSSEL_Bits.CHSELGy */
+#define IFX_VADC_BRSSEL_CHSELGY_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_VADC_BRSSEL_Bits.CHSELGy */
+#define IFX_VADC_BRSSEL_CHSELGY_OFF (0u)
+
+/** \brief Length for Ifx_VADC_CLC_Bits.DISR */
+#define IFX_VADC_CLC_DISR_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_CLC_Bits.DISR */
+#define IFX_VADC_CLC_DISR_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_CLC_Bits.DISR */
+#define IFX_VADC_CLC_DISR_OFF (0u)
+
+/** \brief Length for Ifx_VADC_CLC_Bits.DISS */
+#define IFX_VADC_CLC_DISS_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_CLC_Bits.DISS */
+#define IFX_VADC_CLC_DISS_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_CLC_Bits.DISS */
+#define IFX_VADC_CLC_DISS_OFF (1u)
+
+/** \brief Length for Ifx_VADC_CLC_Bits.EDIS */
+#define IFX_VADC_CLC_EDIS_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_CLC_Bits.EDIS */
+#define IFX_VADC_CLC_EDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_CLC_Bits.EDIS */
+#define IFX_VADC_CLC_EDIS_OFF (3u)
+
+/** \brief Length for Ifx_VADC_EMUXSEL_Bits.EMUXGRP0 */
+#define IFX_VADC_EMUXSEL_EMUXGRP0_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_EMUXSEL_Bits.EMUXGRP0 */
+#define IFX_VADC_EMUXSEL_EMUXGRP0_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_EMUXSEL_Bits.EMUXGRP0 */
+#define IFX_VADC_EMUXSEL_EMUXGRP0_OFF (0u)
+
+/** \brief Length for Ifx_VADC_EMUXSEL_Bits.EMUXGRP1 */
+#define IFX_VADC_EMUXSEL_EMUXGRP1_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_EMUXSEL_Bits.EMUXGRP1 */
+#define IFX_VADC_EMUXSEL_EMUXGRP1_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_EMUXSEL_Bits.EMUXGRP1 */
+#define IFX_VADC_EMUXSEL_EMUXGRP1_OFF (4u)
+
+/** \brief Length for Ifx_VADC_G_ALIAS_Bits.ALIAS0 */
+#define IFX_VADC_G_ALIAS_ALIAS0_LEN (5u)
+
+/** \brief Mask for Ifx_VADC_G_ALIAS_Bits.ALIAS0 */
+#define IFX_VADC_G_ALIAS_ALIAS0_MSK (0x1fu)
+
+/** \brief Offset for Ifx_VADC_G_ALIAS_Bits.ALIAS0 */
+#define IFX_VADC_G_ALIAS_ALIAS0_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_ALIAS_Bits.ALIAS1 */
+#define IFX_VADC_G_ALIAS_ALIAS1_LEN (5u)
+
+/** \brief Mask for Ifx_VADC_G_ALIAS_Bits.ALIAS1 */
+#define IFX_VADC_G_ALIAS_ALIAS1_MSK (0x1fu)
+
+/** \brief Offset for Ifx_VADC_G_ALIAS_Bits.ALIAS1 */
+#define IFX_VADC_G_ALIAS_ALIAS1_OFF (8u)
+
+/** \brief Length for Ifx_VADC_G_ARBCFG_Bits.ANONC */
+#define IFX_VADC_G_ARBCFG_ANONC_LEN (2u)
+
+/** \brief Mask for Ifx_VADC_G_ARBCFG_Bits.ANONC */
+#define IFX_VADC_G_ARBCFG_ANONC_MSK (0x3u)
+
+/** \brief Offset for Ifx_VADC_G_ARBCFG_Bits.ANONC */
+#define IFX_VADC_G_ARBCFG_ANONC_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_ARBCFG_Bits.ANONS */
+#define IFX_VADC_G_ARBCFG_ANONS_LEN (2u)
+
+/** \brief Mask for Ifx_VADC_G_ARBCFG_Bits.ANONS */
+#define IFX_VADC_G_ARBCFG_ANONS_MSK (0x3u)
+
+/** \brief Offset for Ifx_VADC_G_ARBCFG_Bits.ANONS */
+#define IFX_VADC_G_ARBCFG_ANONS_OFF (16u)
+
+/** \brief Length for Ifx_VADC_G_ARBCFG_Bits.ARBM */
+#define IFX_VADC_G_ARBCFG_ARBM_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_ARBCFG_Bits.ARBM */
+#define IFX_VADC_G_ARBCFG_ARBM_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_ARBCFG_Bits.ARBM */
+#define IFX_VADC_G_ARBCFG_ARBM_OFF (7u)
+
+/** \brief Length for Ifx_VADC_G_ARBCFG_Bits.ARBRND */
+#define IFX_VADC_G_ARBCFG_ARBRND_LEN (2u)
+
+/** \brief Mask for Ifx_VADC_G_ARBCFG_Bits.ARBRND */
+#define IFX_VADC_G_ARBCFG_ARBRND_MSK (0x3u)
+
+/** \brief Offset for Ifx_VADC_G_ARBCFG_Bits.ARBRND */
+#define IFX_VADC_G_ARBCFG_ARBRND_OFF (4u)
+
+/** \brief Length for Ifx_VADC_G_ARBCFG_Bits.BUSY */
+#define IFX_VADC_G_ARBCFG_BUSY_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_ARBCFG_Bits.BUSY */
+#define IFX_VADC_G_ARBCFG_BUSY_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_ARBCFG_Bits.BUSY */
+#define IFX_VADC_G_ARBCFG_BUSY_OFF (30u)
+
+/** \brief Length for Ifx_VADC_G_ARBCFG_Bits.CAL */
+#define IFX_VADC_G_ARBCFG_CAL_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_ARBCFG_Bits.CAL */
+#define IFX_VADC_G_ARBCFG_CAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_ARBCFG_Bits.CAL */
+#define IFX_VADC_G_ARBCFG_CAL_OFF (28u)
+
+/** \brief Length for Ifx_VADC_G_ARBCFG_Bits.CALS */
+#define IFX_VADC_G_ARBCFG_CALS_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_ARBCFG_Bits.CALS */
+#define IFX_VADC_G_ARBCFG_CALS_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_ARBCFG_Bits.CALS */
+#define IFX_VADC_G_ARBCFG_CALS_OFF (29u)
+
+/** \brief Length for Ifx_VADC_G_ARBCFG_Bits.CHNR */
+#define IFX_VADC_G_ARBCFG_CHNR_LEN (5u)
+
+/** \brief Mask for Ifx_VADC_G_ARBCFG_Bits.CHNR */
+#define IFX_VADC_G_ARBCFG_CHNR_MSK (0x1fu)
+
+/** \brief Offset for Ifx_VADC_G_ARBCFG_Bits.CHNR */
+#define IFX_VADC_G_ARBCFG_CHNR_OFF (20u)
+
+/** \brief Length for Ifx_VADC_G_ARBCFG_Bits.CSRC */
+#define IFX_VADC_G_ARBCFG_CSRC_LEN (2u)
+
+/** \brief Mask for Ifx_VADC_G_ARBCFG_Bits.CSRC */
+#define IFX_VADC_G_ARBCFG_CSRC_MSK (0x3u)
+
+/** \brief Offset for Ifx_VADC_G_ARBCFG_Bits.CSRC */
+#define IFX_VADC_G_ARBCFG_CSRC_OFF (18u)
+
+/** \brief Length for Ifx_VADC_G_ARBCFG_Bits.SAMPLE */
+#define IFX_VADC_G_ARBCFG_SAMPLE_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_ARBCFG_Bits.SAMPLE */
+#define IFX_VADC_G_ARBCFG_SAMPLE_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_ARBCFG_Bits.SAMPLE */
+#define IFX_VADC_G_ARBCFG_SAMPLE_OFF (31u)
+
+/** \brief Length for Ifx_VADC_G_ARBCFG_Bits.SYNRUN */
+#define IFX_VADC_G_ARBCFG_SYNRUN_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_ARBCFG_Bits.SYNRUN */
+#define IFX_VADC_G_ARBCFG_SYNRUN_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_ARBCFG_Bits.SYNRUN */
+#define IFX_VADC_G_ARBCFG_SYNRUN_OFF (25u)
+
+/** \brief Length for Ifx_VADC_G_ARBPR_Bits.ASEN0 */
+#define IFX_VADC_G_ARBPR_ASEN0_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_ARBPR_Bits.ASEN0 */
+#define IFX_VADC_G_ARBPR_ASEN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_ARBPR_Bits.ASEN0 */
+#define IFX_VADC_G_ARBPR_ASEN0_OFF (24u)
+
+/** \brief Length for Ifx_VADC_G_ARBPR_Bits.ASEN1 */
+#define IFX_VADC_G_ARBPR_ASEN1_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_ARBPR_Bits.ASEN1 */
+#define IFX_VADC_G_ARBPR_ASEN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_ARBPR_Bits.ASEN1 */
+#define IFX_VADC_G_ARBPR_ASEN1_OFF (25u)
+
+/** \brief Length for Ifx_VADC_G_ARBPR_Bits.ASEN2 */
+#define IFX_VADC_G_ARBPR_ASEN2_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_ARBPR_Bits.ASEN2 */
+#define IFX_VADC_G_ARBPR_ASEN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_ARBPR_Bits.ASEN2 */
+#define IFX_VADC_G_ARBPR_ASEN2_OFF (26u)
+
+/** \brief Length for Ifx_VADC_G_ARBPR_Bits.CSM0 */
+#define IFX_VADC_G_ARBPR_CSM0_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_ARBPR_Bits.CSM0 */
+#define IFX_VADC_G_ARBPR_CSM0_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_ARBPR_Bits.CSM0 */
+#define IFX_VADC_G_ARBPR_CSM0_OFF (3u)
+
+/** \brief Length for Ifx_VADC_G_ARBPR_Bits.CSM1 */
+#define IFX_VADC_G_ARBPR_CSM1_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_ARBPR_Bits.CSM1 */
+#define IFX_VADC_G_ARBPR_CSM1_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_ARBPR_Bits.CSM1 */
+#define IFX_VADC_G_ARBPR_CSM1_OFF (7u)
+
+/** \brief Length for Ifx_VADC_G_ARBPR_Bits.CSM2 */
+#define IFX_VADC_G_ARBPR_CSM2_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_ARBPR_Bits.CSM2 */
+#define IFX_VADC_G_ARBPR_CSM2_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_ARBPR_Bits.CSM2 */
+#define IFX_VADC_G_ARBPR_CSM2_OFF (11u)
+
+/** \brief Length for Ifx_VADC_G_ARBPR_Bits.PRIO0 */
+#define IFX_VADC_G_ARBPR_PRIO0_LEN (2u)
+
+/** \brief Mask for Ifx_VADC_G_ARBPR_Bits.PRIO0 */
+#define IFX_VADC_G_ARBPR_PRIO0_MSK (0x3u)
+
+/** \brief Offset for Ifx_VADC_G_ARBPR_Bits.PRIO0 */
+#define IFX_VADC_G_ARBPR_PRIO0_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_ARBPR_Bits.PRIO1 */
+#define IFX_VADC_G_ARBPR_PRIO1_LEN (2u)
+
+/** \brief Mask for Ifx_VADC_G_ARBPR_Bits.PRIO1 */
+#define IFX_VADC_G_ARBPR_PRIO1_MSK (0x3u)
+
+/** \brief Offset for Ifx_VADC_G_ARBPR_Bits.PRIO1 */
+#define IFX_VADC_G_ARBPR_PRIO1_OFF (4u)
+
+/** \brief Length for Ifx_VADC_G_ARBPR_Bits.PRIO2 */
+#define IFX_VADC_G_ARBPR_PRIO2_LEN (2u)
+
+/** \brief Mask for Ifx_VADC_G_ARBPR_Bits.PRIO2 */
+#define IFX_VADC_G_ARBPR_PRIO2_MSK (0x3u)
+
+/** \brief Offset for Ifx_VADC_G_ARBPR_Bits.PRIO2 */
+#define IFX_VADC_G_ARBPR_PRIO2_OFF (8u)
+
+/** \brief Length for Ifx_VADC_G_ASCTRL_Bits.GTLVL */
+#define IFX_VADC_G_ASCTRL_GTLVL_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_ASCTRL_Bits.GTLVL */
+#define IFX_VADC_G_ASCTRL_GTLVL_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_ASCTRL_Bits.GTLVL */
+#define IFX_VADC_G_ASCTRL_GTLVL_OFF (20u)
+
+/** \brief Length for Ifx_VADC_G_ASCTRL_Bits.GTSEL */
+#define IFX_VADC_G_ASCTRL_GTSEL_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_ASCTRL_Bits.GTSEL */
+#define IFX_VADC_G_ASCTRL_GTSEL_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_ASCTRL_Bits.GTSEL */
+#define IFX_VADC_G_ASCTRL_GTSEL_OFF (16u)
+
+/** \brief Length for Ifx_VADC_G_ASCTRL_Bits.GTWC */
+#define IFX_VADC_G_ASCTRL_GTWC_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_ASCTRL_Bits.GTWC */
+#define IFX_VADC_G_ASCTRL_GTWC_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_ASCTRL_Bits.GTWC */
+#define IFX_VADC_G_ASCTRL_GTWC_OFF (23u)
+
+/** \brief Length for Ifx_VADC_G_ASCTRL_Bits.SRCRESREG */
+#define IFX_VADC_G_ASCTRL_SRCRESREG_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_ASCTRL_Bits.SRCRESREG */
+#define IFX_VADC_G_ASCTRL_SRCRESREG_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_ASCTRL_Bits.SRCRESREG */
+#define IFX_VADC_G_ASCTRL_SRCRESREG_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_ASCTRL_Bits.TMEN */
+#define IFX_VADC_G_ASCTRL_TMEN_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_ASCTRL_Bits.TMEN */
+#define IFX_VADC_G_ASCTRL_TMEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_ASCTRL_Bits.TMEN */
+#define IFX_VADC_G_ASCTRL_TMEN_OFF (28u)
+
+/** \brief Length for Ifx_VADC_G_ASCTRL_Bits.TMWC */
+#define IFX_VADC_G_ASCTRL_TMWC_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_ASCTRL_Bits.TMWC */
+#define IFX_VADC_G_ASCTRL_TMWC_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_ASCTRL_Bits.TMWC */
+#define IFX_VADC_G_ASCTRL_TMWC_OFF (31u)
+
+/** \brief Length for Ifx_VADC_G_ASCTRL_Bits.XTLVL */
+#define IFX_VADC_G_ASCTRL_XTLVL_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_ASCTRL_Bits.XTLVL */
+#define IFX_VADC_G_ASCTRL_XTLVL_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_ASCTRL_Bits.XTLVL */
+#define IFX_VADC_G_ASCTRL_XTLVL_OFF (12u)
+
+/** \brief Length for Ifx_VADC_G_ASCTRL_Bits.XTMODE */
+#define IFX_VADC_G_ASCTRL_XTMODE_LEN (2u)
+
+/** \brief Mask for Ifx_VADC_G_ASCTRL_Bits.XTMODE */
+#define IFX_VADC_G_ASCTRL_XTMODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_VADC_G_ASCTRL_Bits.XTMODE */
+#define IFX_VADC_G_ASCTRL_XTMODE_OFF (13u)
+
+/** \brief Length for Ifx_VADC_G_ASCTRL_Bits.XTSEL */
+#define IFX_VADC_G_ASCTRL_XTSEL_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_ASCTRL_Bits.XTSEL */
+#define IFX_VADC_G_ASCTRL_XTSEL_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_ASCTRL_Bits.XTSEL */
+#define IFX_VADC_G_ASCTRL_XTSEL_OFF (8u)
+
+/** \brief Length for Ifx_VADC_G_ASCTRL_Bits.XTWC */
+#define IFX_VADC_G_ASCTRL_XTWC_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_ASCTRL_Bits.XTWC */
+#define IFX_VADC_G_ASCTRL_XTWC_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_ASCTRL_Bits.XTWC */
+#define IFX_VADC_G_ASCTRL_XTWC_OFF (15u)
+
+/** \brief Length for Ifx_VADC_G_ASMR_Bits.CLRPND */
+#define IFX_VADC_G_ASMR_CLRPND_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_ASMR_Bits.CLRPND */
+#define IFX_VADC_G_ASMR_CLRPND_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_ASMR_Bits.CLRPND */
+#define IFX_VADC_G_ASMR_CLRPND_OFF (8u)
+
+/** \brief Length for Ifx_VADC_G_ASMR_Bits.ENGT */
+#define IFX_VADC_G_ASMR_ENGT_LEN (2u)
+
+/** \brief Mask for Ifx_VADC_G_ASMR_Bits.ENGT */
+#define IFX_VADC_G_ASMR_ENGT_MSK (0x3u)
+
+/** \brief Offset for Ifx_VADC_G_ASMR_Bits.ENGT */
+#define IFX_VADC_G_ASMR_ENGT_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_ASMR_Bits.ENSI */
+#define IFX_VADC_G_ASMR_ENSI_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_ASMR_Bits.ENSI */
+#define IFX_VADC_G_ASMR_ENSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_ASMR_Bits.ENSI */
+#define IFX_VADC_G_ASMR_ENSI_OFF (3u)
+
+/** \brief Length for Ifx_VADC_G_ASMR_Bits.ENTR */
+#define IFX_VADC_G_ASMR_ENTR_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_ASMR_Bits.ENTR */
+#define IFX_VADC_G_ASMR_ENTR_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_ASMR_Bits.ENTR */
+#define IFX_VADC_G_ASMR_ENTR_OFF (2u)
+
+/** \brief Length for Ifx_VADC_G_ASMR_Bits.LDEV */
+#define IFX_VADC_G_ASMR_LDEV_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_ASMR_Bits.LDEV */
+#define IFX_VADC_G_ASMR_LDEV_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_ASMR_Bits.LDEV */
+#define IFX_VADC_G_ASMR_LDEV_OFF (9u)
+
+/** \brief Length for Ifx_VADC_G_ASMR_Bits.LDM */
+#define IFX_VADC_G_ASMR_LDM_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_ASMR_Bits.LDM */
+#define IFX_VADC_G_ASMR_LDM_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_ASMR_Bits.LDM */
+#define IFX_VADC_G_ASMR_LDM_OFF (5u)
+
+/** \brief Length for Ifx_VADC_G_ASMR_Bits.REQGT */
+#define IFX_VADC_G_ASMR_REQGT_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_ASMR_Bits.REQGT */
+#define IFX_VADC_G_ASMR_REQGT_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_ASMR_Bits.REQGT */
+#define IFX_VADC_G_ASMR_REQGT_OFF (7u)
+
+/** \brief Length for Ifx_VADC_G_ASMR_Bits.RPTDIS */
+#define IFX_VADC_G_ASMR_RPTDIS_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_ASMR_Bits.RPTDIS */
+#define IFX_VADC_G_ASMR_RPTDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_ASMR_Bits.RPTDIS */
+#define IFX_VADC_G_ASMR_RPTDIS_OFF (16u)
+
+/** \brief Length for Ifx_VADC_G_ASMR_Bits.SCAN */
+#define IFX_VADC_G_ASMR_SCAN_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_ASMR_Bits.SCAN */
+#define IFX_VADC_G_ASMR_SCAN_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_ASMR_Bits.SCAN */
+#define IFX_VADC_G_ASMR_SCAN_OFF (4u)
+
+/** \brief Length for Ifx_VADC_G_ASPND_Bits.CHPND */
+#define IFX_VADC_G_ASPND_CHPND_LEN (32u)
+
+/** \brief Mask for Ifx_VADC_G_ASPND_Bits.CHPND */
+#define IFX_VADC_G_ASPND_CHPND_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_VADC_G_ASPND_Bits.CHPND */
+#define IFX_VADC_G_ASPND_CHPND_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_ASSEL_Bits.CHSEL */
+#define IFX_VADC_G_ASSEL_CHSEL_LEN (32u)
+
+/** \brief Mask for Ifx_VADC_G_ASSEL_Bits.CHSEL */
+#define IFX_VADC_G_ASSEL_CHSEL_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_VADC_G_ASSEL_Bits.CHSEL */
+#define IFX_VADC_G_ASSEL_CHSEL_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_BFL_Bits.BFA0 */
+#define IFX_VADC_G_BFL_BFA0_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_BFL_Bits.BFA0 */
+#define IFX_VADC_G_BFL_BFA0_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_BFL_Bits.BFA0 */
+#define IFX_VADC_G_BFL_BFA0_OFF (8u)
+
+/** \brief Length for Ifx_VADC_G_BFL_Bits.BFA1 */
+#define IFX_VADC_G_BFL_BFA1_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_BFL_Bits.BFA1 */
+#define IFX_VADC_G_BFL_BFA1_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_BFL_Bits.BFA1 */
+#define IFX_VADC_G_BFL_BFA1_OFF (9u)
+
+/** \brief Length for Ifx_VADC_G_BFL_Bits.BFA2 */
+#define IFX_VADC_G_BFL_BFA2_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_BFL_Bits.BFA2 */
+#define IFX_VADC_G_BFL_BFA2_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_BFL_Bits.BFA2 */
+#define IFX_VADC_G_BFL_BFA2_OFF (10u)
+
+/** \brief Length for Ifx_VADC_G_BFL_Bits.BFA3 */
+#define IFX_VADC_G_BFL_BFA3_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_BFL_Bits.BFA3 */
+#define IFX_VADC_G_BFL_BFA3_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_BFL_Bits.BFA3 */
+#define IFX_VADC_G_BFL_BFA3_OFF (11u)
+
+/** \brief Length for Ifx_VADC_G_BFL_Bits.BFI0 */
+#define IFX_VADC_G_BFL_BFI0_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_BFL_Bits.BFI0 */
+#define IFX_VADC_G_BFL_BFI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_BFL_Bits.BFI0 */
+#define IFX_VADC_G_BFL_BFI0_OFF (16u)
+
+/** \brief Length for Ifx_VADC_G_BFL_Bits.BFI1 */
+#define IFX_VADC_G_BFL_BFI1_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_BFL_Bits.BFI1 */
+#define IFX_VADC_G_BFL_BFI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_BFL_Bits.BFI1 */
+#define IFX_VADC_G_BFL_BFI1_OFF (17u)
+
+/** \brief Length for Ifx_VADC_G_BFL_Bits.BFI2 */
+#define IFX_VADC_G_BFL_BFI2_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_BFL_Bits.BFI2 */
+#define IFX_VADC_G_BFL_BFI2_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_BFL_Bits.BFI2 */
+#define IFX_VADC_G_BFL_BFI2_OFF (18u)
+
+/** \brief Length for Ifx_VADC_G_BFL_Bits.BFI3 */
+#define IFX_VADC_G_BFL_BFI3_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_BFL_Bits.BFI3 */
+#define IFX_VADC_G_BFL_BFI3_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_BFL_Bits.BFI3 */
+#define IFX_VADC_G_BFL_BFI3_OFF (19u)
+
+/** \brief Length for Ifx_VADC_G_BFL_Bits.BFL0 */
+#define IFX_VADC_G_BFL_BFL0_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_BFL_Bits.BFL0 */
+#define IFX_VADC_G_BFL_BFL0_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_BFL_Bits.BFL0 */
+#define IFX_VADC_G_BFL_BFL0_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_BFL_Bits.BFL1 */
+#define IFX_VADC_G_BFL_BFL1_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_BFL_Bits.BFL1 */
+#define IFX_VADC_G_BFL_BFL1_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_BFL_Bits.BFL1 */
+#define IFX_VADC_G_BFL_BFL1_OFF (1u)
+
+/** \brief Length for Ifx_VADC_G_BFL_Bits.BFL2 */
+#define IFX_VADC_G_BFL_BFL2_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_BFL_Bits.BFL2 */
+#define IFX_VADC_G_BFL_BFL2_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_BFL_Bits.BFL2 */
+#define IFX_VADC_G_BFL_BFL2_OFF (2u)
+
+/** \brief Length for Ifx_VADC_G_BFL_Bits.BFL3 */
+#define IFX_VADC_G_BFL_BFL3_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_BFL_Bits.BFL3 */
+#define IFX_VADC_G_BFL_BFL3_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_BFL_Bits.BFL3 */
+#define IFX_VADC_G_BFL_BFL3_OFF (3u)
+
+/** \brief Length for Ifx_VADC_G_BFLC_Bits.BFM0 */
+#define IFX_VADC_G_BFLC_BFM0_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_BFLC_Bits.BFM0 */
+#define IFX_VADC_G_BFLC_BFM0_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_BFLC_Bits.BFM0 */
+#define IFX_VADC_G_BFLC_BFM0_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_BFLC_Bits.BFM1 */
+#define IFX_VADC_G_BFLC_BFM1_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_BFLC_Bits.BFM1 */
+#define IFX_VADC_G_BFLC_BFM1_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_BFLC_Bits.BFM1 */
+#define IFX_VADC_G_BFLC_BFM1_OFF (4u)
+
+/** \brief Length for Ifx_VADC_G_BFLC_Bits.BFM2 */
+#define IFX_VADC_G_BFLC_BFM2_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_BFLC_Bits.BFM2 */
+#define IFX_VADC_G_BFLC_BFM2_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_BFLC_Bits.BFM2 */
+#define IFX_VADC_G_BFLC_BFM2_OFF (8u)
+
+/** \brief Length for Ifx_VADC_G_BFLC_Bits.BFM3 */
+#define IFX_VADC_G_BFLC_BFM3_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_BFLC_Bits.BFM3 */
+#define IFX_VADC_G_BFLC_BFM3_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_BFLC_Bits.BFM3 */
+#define IFX_VADC_G_BFLC_BFM3_OFF (12u)
+
+/** \brief Length for Ifx_VADC_G_BFLNP_Bits.BFL0NP */
+#define IFX_VADC_G_BFLNP_BFL0NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_BFLNP_Bits.BFL0NP */
+#define IFX_VADC_G_BFLNP_BFL0NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_BFLNP_Bits.BFL0NP */
+#define IFX_VADC_G_BFLNP_BFL0NP_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_BFLNP_Bits.BFL1NP */
+#define IFX_VADC_G_BFLNP_BFL1NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_BFLNP_Bits.BFL1NP */
+#define IFX_VADC_G_BFLNP_BFL1NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_BFLNP_Bits.BFL1NP */
+#define IFX_VADC_G_BFLNP_BFL1NP_OFF (4u)
+
+/** \brief Length for Ifx_VADC_G_BFLNP_Bits.BFL2NP */
+#define IFX_VADC_G_BFLNP_BFL2NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_BFLNP_Bits.BFL2NP */
+#define IFX_VADC_G_BFLNP_BFL2NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_BFLNP_Bits.BFL2NP */
+#define IFX_VADC_G_BFLNP_BFL2NP_OFF (8u)
+
+/** \brief Length for Ifx_VADC_G_BFLNP_Bits.BFL3NP */
+#define IFX_VADC_G_BFLNP_BFL3NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_BFLNP_Bits.BFL3NP */
+#define IFX_VADC_G_BFLNP_BFL3NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_BFLNP_Bits.BFL3NP */
+#define IFX_VADC_G_BFLNP_BFL3NP_OFF (12u)
+
+/** \brief Length for Ifx_VADC_G_BFLS_Bits.BFC0 */
+#define IFX_VADC_G_BFLS_BFC0_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_BFLS_Bits.BFC0 */
+#define IFX_VADC_G_BFLS_BFC0_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_BFLS_Bits.BFC0 */
+#define IFX_VADC_G_BFLS_BFC0_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_BFLS_Bits.BFC1 */
+#define IFX_VADC_G_BFLS_BFC1_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_BFLS_Bits.BFC1 */
+#define IFX_VADC_G_BFLS_BFC1_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_BFLS_Bits.BFC1 */
+#define IFX_VADC_G_BFLS_BFC1_OFF (1u)
+
+/** \brief Length for Ifx_VADC_G_BFLS_Bits.BFC2 */
+#define IFX_VADC_G_BFLS_BFC2_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_BFLS_Bits.BFC2 */
+#define IFX_VADC_G_BFLS_BFC2_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_BFLS_Bits.BFC2 */
+#define IFX_VADC_G_BFLS_BFC2_OFF (2u)
+
+/** \brief Length for Ifx_VADC_G_BFLS_Bits.BFC3 */
+#define IFX_VADC_G_BFLS_BFC3_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_BFLS_Bits.BFC3 */
+#define IFX_VADC_G_BFLS_BFC3_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_BFLS_Bits.BFC3 */
+#define IFX_VADC_G_BFLS_BFC3_OFF (3u)
+
+/** \brief Length for Ifx_VADC_G_BFLS_Bits.BFS0 */
+#define IFX_VADC_G_BFLS_BFS0_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_BFLS_Bits.BFS0 */
+#define IFX_VADC_G_BFLS_BFS0_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_BFLS_Bits.BFS0 */
+#define IFX_VADC_G_BFLS_BFS0_OFF (16u)
+
+/** \brief Length for Ifx_VADC_G_BFLS_Bits.BFS1 */
+#define IFX_VADC_G_BFLS_BFS1_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_BFLS_Bits.BFS1 */
+#define IFX_VADC_G_BFLS_BFS1_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_BFLS_Bits.BFS1 */
+#define IFX_VADC_G_BFLS_BFS1_OFF (17u)
+
+/** \brief Length for Ifx_VADC_G_BFLS_Bits.BFS2 */
+#define IFX_VADC_G_BFLS_BFS2_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_BFLS_Bits.BFS2 */
+#define IFX_VADC_G_BFLS_BFS2_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_BFLS_Bits.BFS2 */
+#define IFX_VADC_G_BFLS_BFS2_OFF (18u)
+
+/** \brief Length for Ifx_VADC_G_BFLS_Bits.BFS3 */
+#define IFX_VADC_G_BFLS_BFS3_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_BFLS_Bits.BFS3 */
+#define IFX_VADC_G_BFLS_BFS3_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_BFLS_Bits.BFS3 */
+#define IFX_VADC_G_BFLS_BFS3_OFF (19u)
+
+/** \brief Length for Ifx_VADC_G_BOUND_Bits.BOUNDARY0 */
+#define IFX_VADC_G_BOUND_BOUNDARY0_LEN (12u)
+
+/** \brief Mask for Ifx_VADC_G_BOUND_Bits.BOUNDARY0 */
+#define IFX_VADC_G_BOUND_BOUNDARY0_MSK (0xfffu)
+
+/** \brief Offset for Ifx_VADC_G_BOUND_Bits.BOUNDARY0 */
+#define IFX_VADC_G_BOUND_BOUNDARY0_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_BOUND_Bits.BOUNDARY1 */
+#define IFX_VADC_G_BOUND_BOUNDARY1_LEN (12u)
+
+/** \brief Mask for Ifx_VADC_G_BOUND_Bits.BOUNDARY1 */
+#define IFX_VADC_G_BOUND_BOUNDARY1_MSK (0xfffu)
+
+/** \brief Offset for Ifx_VADC_G_BOUND_Bits.BOUNDARY1 */
+#define IFX_VADC_G_BOUND_BOUNDARY1_OFF (16u)
+
+/** \brief Length for Ifx_VADC_G_CEFCLR_Bits.CEV0 */
+#define IFX_VADC_G_CEFCLR_CEV0_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFCLR_Bits.CEV0 */
+#define IFX_VADC_G_CEFCLR_CEV0_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFCLR_Bits.CEV0 */
+#define IFX_VADC_G_CEFCLR_CEV0_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_CEFCLR_Bits.CEV10 */
+#define IFX_VADC_G_CEFCLR_CEV10_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFCLR_Bits.CEV10 */
+#define IFX_VADC_G_CEFCLR_CEV10_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFCLR_Bits.CEV10 */
+#define IFX_VADC_G_CEFCLR_CEV10_OFF (10u)
+
+/** \brief Length for Ifx_VADC_G_CEFCLR_Bits.CEV11 */
+#define IFX_VADC_G_CEFCLR_CEV11_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFCLR_Bits.CEV11 */
+#define IFX_VADC_G_CEFCLR_CEV11_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFCLR_Bits.CEV11 */
+#define IFX_VADC_G_CEFCLR_CEV11_OFF (11u)
+
+/** \brief Length for Ifx_VADC_G_CEFCLR_Bits.CEV12 */
+#define IFX_VADC_G_CEFCLR_CEV12_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFCLR_Bits.CEV12 */
+#define IFX_VADC_G_CEFCLR_CEV12_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFCLR_Bits.CEV12 */
+#define IFX_VADC_G_CEFCLR_CEV12_OFF (12u)
+
+/** \brief Length for Ifx_VADC_G_CEFCLR_Bits.CEV13 */
+#define IFX_VADC_G_CEFCLR_CEV13_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFCLR_Bits.CEV13 */
+#define IFX_VADC_G_CEFCLR_CEV13_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFCLR_Bits.CEV13 */
+#define IFX_VADC_G_CEFCLR_CEV13_OFF (13u)
+
+/** \brief Length for Ifx_VADC_G_CEFCLR_Bits.CEV14 */
+#define IFX_VADC_G_CEFCLR_CEV14_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFCLR_Bits.CEV14 */
+#define IFX_VADC_G_CEFCLR_CEV14_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFCLR_Bits.CEV14 */
+#define IFX_VADC_G_CEFCLR_CEV14_OFF (14u)
+
+/** \brief Length for Ifx_VADC_G_CEFCLR_Bits.CEV15 */
+#define IFX_VADC_G_CEFCLR_CEV15_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFCLR_Bits.CEV15 */
+#define IFX_VADC_G_CEFCLR_CEV15_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFCLR_Bits.CEV15 */
+#define IFX_VADC_G_CEFCLR_CEV15_OFF (15u)
+
+/** \brief Length for Ifx_VADC_G_CEFCLR_Bits.CEV1 */
+#define IFX_VADC_G_CEFCLR_CEV1_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFCLR_Bits.CEV1 */
+#define IFX_VADC_G_CEFCLR_CEV1_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFCLR_Bits.CEV1 */
+#define IFX_VADC_G_CEFCLR_CEV1_OFF (1u)
+
+/** \brief Length for Ifx_VADC_G_CEFCLR_Bits.CEV2 */
+#define IFX_VADC_G_CEFCLR_CEV2_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFCLR_Bits.CEV2 */
+#define IFX_VADC_G_CEFCLR_CEV2_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFCLR_Bits.CEV2 */
+#define IFX_VADC_G_CEFCLR_CEV2_OFF (2u)
+
+/** \brief Length for Ifx_VADC_G_CEFCLR_Bits.CEV3 */
+#define IFX_VADC_G_CEFCLR_CEV3_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFCLR_Bits.CEV3 */
+#define IFX_VADC_G_CEFCLR_CEV3_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFCLR_Bits.CEV3 */
+#define IFX_VADC_G_CEFCLR_CEV3_OFF (3u)
+
+/** \brief Length for Ifx_VADC_G_CEFCLR_Bits.CEV4 */
+#define IFX_VADC_G_CEFCLR_CEV4_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFCLR_Bits.CEV4 */
+#define IFX_VADC_G_CEFCLR_CEV4_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFCLR_Bits.CEV4 */
+#define IFX_VADC_G_CEFCLR_CEV4_OFF (4u)
+
+/** \brief Length for Ifx_VADC_G_CEFCLR_Bits.CEV5 */
+#define IFX_VADC_G_CEFCLR_CEV5_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFCLR_Bits.CEV5 */
+#define IFX_VADC_G_CEFCLR_CEV5_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFCLR_Bits.CEV5 */
+#define IFX_VADC_G_CEFCLR_CEV5_OFF (5u)
+
+/** \brief Length for Ifx_VADC_G_CEFCLR_Bits.CEV6 */
+#define IFX_VADC_G_CEFCLR_CEV6_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFCLR_Bits.CEV6 */
+#define IFX_VADC_G_CEFCLR_CEV6_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFCLR_Bits.CEV6 */
+#define IFX_VADC_G_CEFCLR_CEV6_OFF (6u)
+
+/** \brief Length for Ifx_VADC_G_CEFCLR_Bits.CEV7 */
+#define IFX_VADC_G_CEFCLR_CEV7_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFCLR_Bits.CEV7 */
+#define IFX_VADC_G_CEFCLR_CEV7_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFCLR_Bits.CEV7 */
+#define IFX_VADC_G_CEFCLR_CEV7_OFF (7u)
+
+/** \brief Length for Ifx_VADC_G_CEFCLR_Bits.CEV8 */
+#define IFX_VADC_G_CEFCLR_CEV8_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFCLR_Bits.CEV8 */
+#define IFX_VADC_G_CEFCLR_CEV8_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFCLR_Bits.CEV8 */
+#define IFX_VADC_G_CEFCLR_CEV8_OFF (8u)
+
+/** \brief Length for Ifx_VADC_G_CEFCLR_Bits.CEV9 */
+#define IFX_VADC_G_CEFCLR_CEV9_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFCLR_Bits.CEV9 */
+#define IFX_VADC_G_CEFCLR_CEV9_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFCLR_Bits.CEV9 */
+#define IFX_VADC_G_CEFCLR_CEV9_OFF (9u)
+
+/** \brief Length for Ifx_VADC_G_CEFLAG_Bits.CEV0 */
+#define IFX_VADC_G_CEFLAG_CEV0_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFLAG_Bits.CEV0 */
+#define IFX_VADC_G_CEFLAG_CEV0_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFLAG_Bits.CEV0 */
+#define IFX_VADC_G_CEFLAG_CEV0_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_CEFLAG_Bits.CEV10 */
+#define IFX_VADC_G_CEFLAG_CEV10_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFLAG_Bits.CEV10 */
+#define IFX_VADC_G_CEFLAG_CEV10_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFLAG_Bits.CEV10 */
+#define IFX_VADC_G_CEFLAG_CEV10_OFF (10u)
+
+/** \brief Length for Ifx_VADC_G_CEFLAG_Bits.CEV11 */
+#define IFX_VADC_G_CEFLAG_CEV11_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFLAG_Bits.CEV11 */
+#define IFX_VADC_G_CEFLAG_CEV11_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFLAG_Bits.CEV11 */
+#define IFX_VADC_G_CEFLAG_CEV11_OFF (11u)
+
+/** \brief Length for Ifx_VADC_G_CEFLAG_Bits.CEV12 */
+#define IFX_VADC_G_CEFLAG_CEV12_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFLAG_Bits.CEV12 */
+#define IFX_VADC_G_CEFLAG_CEV12_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFLAG_Bits.CEV12 */
+#define IFX_VADC_G_CEFLAG_CEV12_OFF (12u)
+
+/** \brief Length for Ifx_VADC_G_CEFLAG_Bits.CEV13 */
+#define IFX_VADC_G_CEFLAG_CEV13_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFLAG_Bits.CEV13 */
+#define IFX_VADC_G_CEFLAG_CEV13_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFLAG_Bits.CEV13 */
+#define IFX_VADC_G_CEFLAG_CEV13_OFF (13u)
+
+/** \brief Length for Ifx_VADC_G_CEFLAG_Bits.CEV14 */
+#define IFX_VADC_G_CEFLAG_CEV14_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFLAG_Bits.CEV14 */
+#define IFX_VADC_G_CEFLAG_CEV14_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFLAG_Bits.CEV14 */
+#define IFX_VADC_G_CEFLAG_CEV14_OFF (14u)
+
+/** \brief Length for Ifx_VADC_G_CEFLAG_Bits.CEV15 */
+#define IFX_VADC_G_CEFLAG_CEV15_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFLAG_Bits.CEV15 */
+#define IFX_VADC_G_CEFLAG_CEV15_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFLAG_Bits.CEV15 */
+#define IFX_VADC_G_CEFLAG_CEV15_OFF (15u)
+
+/** \brief Length for Ifx_VADC_G_CEFLAG_Bits.CEV1 */
+#define IFX_VADC_G_CEFLAG_CEV1_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFLAG_Bits.CEV1 */
+#define IFX_VADC_G_CEFLAG_CEV1_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFLAG_Bits.CEV1 */
+#define IFX_VADC_G_CEFLAG_CEV1_OFF (1u)
+
+/** \brief Length for Ifx_VADC_G_CEFLAG_Bits.CEV2 */
+#define IFX_VADC_G_CEFLAG_CEV2_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFLAG_Bits.CEV2 */
+#define IFX_VADC_G_CEFLAG_CEV2_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFLAG_Bits.CEV2 */
+#define IFX_VADC_G_CEFLAG_CEV2_OFF (2u)
+
+/** \brief Length for Ifx_VADC_G_CEFLAG_Bits.CEV3 */
+#define IFX_VADC_G_CEFLAG_CEV3_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFLAG_Bits.CEV3 */
+#define IFX_VADC_G_CEFLAG_CEV3_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFLAG_Bits.CEV3 */
+#define IFX_VADC_G_CEFLAG_CEV3_OFF (3u)
+
+/** \brief Length for Ifx_VADC_G_CEFLAG_Bits.CEV4 */
+#define IFX_VADC_G_CEFLAG_CEV4_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFLAG_Bits.CEV4 */
+#define IFX_VADC_G_CEFLAG_CEV4_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFLAG_Bits.CEV4 */
+#define IFX_VADC_G_CEFLAG_CEV4_OFF (4u)
+
+/** \brief Length for Ifx_VADC_G_CEFLAG_Bits.CEV5 */
+#define IFX_VADC_G_CEFLAG_CEV5_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFLAG_Bits.CEV5 */
+#define IFX_VADC_G_CEFLAG_CEV5_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFLAG_Bits.CEV5 */
+#define IFX_VADC_G_CEFLAG_CEV5_OFF (5u)
+
+/** \brief Length for Ifx_VADC_G_CEFLAG_Bits.CEV6 */
+#define IFX_VADC_G_CEFLAG_CEV6_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFLAG_Bits.CEV6 */
+#define IFX_VADC_G_CEFLAG_CEV6_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFLAG_Bits.CEV6 */
+#define IFX_VADC_G_CEFLAG_CEV6_OFF (6u)
+
+/** \brief Length for Ifx_VADC_G_CEFLAG_Bits.CEV7 */
+#define IFX_VADC_G_CEFLAG_CEV7_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFLAG_Bits.CEV7 */
+#define IFX_VADC_G_CEFLAG_CEV7_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFLAG_Bits.CEV7 */
+#define IFX_VADC_G_CEFLAG_CEV7_OFF (7u)
+
+/** \brief Length for Ifx_VADC_G_CEFLAG_Bits.CEV8 */
+#define IFX_VADC_G_CEFLAG_CEV8_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFLAG_Bits.CEV8 */
+#define IFX_VADC_G_CEFLAG_CEV8_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFLAG_Bits.CEV8 */
+#define IFX_VADC_G_CEFLAG_CEV8_OFF (8u)
+
+/** \brief Length for Ifx_VADC_G_CEFLAG_Bits.CEV9 */
+#define IFX_VADC_G_CEFLAG_CEV9_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CEFLAG_Bits.CEV9 */
+#define IFX_VADC_G_CEFLAG_CEV9_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CEFLAG_Bits.CEV9 */
+#define IFX_VADC_G_CEFLAG_CEV9_OFF (9u)
+
+/** \brief Length for Ifx_VADC_G_CEVNP0_Bits.CEV0NP */
+#define IFX_VADC_G_CEVNP0_CEV0NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_CEVNP0_Bits.CEV0NP */
+#define IFX_VADC_G_CEVNP0_CEV0NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_CEVNP0_Bits.CEV0NP */
+#define IFX_VADC_G_CEVNP0_CEV0NP_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_CEVNP0_Bits.CEV1NP */
+#define IFX_VADC_G_CEVNP0_CEV1NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_CEVNP0_Bits.CEV1NP */
+#define IFX_VADC_G_CEVNP0_CEV1NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_CEVNP0_Bits.CEV1NP */
+#define IFX_VADC_G_CEVNP0_CEV1NP_OFF (4u)
+
+/** \brief Length for Ifx_VADC_G_CEVNP0_Bits.CEV2NP */
+#define IFX_VADC_G_CEVNP0_CEV2NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_CEVNP0_Bits.CEV2NP */
+#define IFX_VADC_G_CEVNP0_CEV2NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_CEVNP0_Bits.CEV2NP */
+#define IFX_VADC_G_CEVNP0_CEV2NP_OFF (8u)
+
+/** \brief Length for Ifx_VADC_G_CEVNP0_Bits.CEV3NP */
+#define IFX_VADC_G_CEVNP0_CEV3NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_CEVNP0_Bits.CEV3NP */
+#define IFX_VADC_G_CEVNP0_CEV3NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_CEVNP0_Bits.CEV3NP */
+#define IFX_VADC_G_CEVNP0_CEV3NP_OFF (12u)
+
+/** \brief Length for Ifx_VADC_G_CEVNP0_Bits.CEV4NP */
+#define IFX_VADC_G_CEVNP0_CEV4NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_CEVNP0_Bits.CEV4NP */
+#define IFX_VADC_G_CEVNP0_CEV4NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_CEVNP0_Bits.CEV4NP */
+#define IFX_VADC_G_CEVNP0_CEV4NP_OFF (16u)
+
+/** \brief Length for Ifx_VADC_G_CEVNP0_Bits.CEV5NP */
+#define IFX_VADC_G_CEVNP0_CEV5NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_CEVNP0_Bits.CEV5NP */
+#define IFX_VADC_G_CEVNP0_CEV5NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_CEVNP0_Bits.CEV5NP */
+#define IFX_VADC_G_CEVNP0_CEV5NP_OFF (20u)
+
+/** \brief Length for Ifx_VADC_G_CEVNP0_Bits.CEV6NP */
+#define IFX_VADC_G_CEVNP0_CEV6NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_CEVNP0_Bits.CEV6NP */
+#define IFX_VADC_G_CEVNP0_CEV6NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_CEVNP0_Bits.CEV6NP */
+#define IFX_VADC_G_CEVNP0_CEV6NP_OFF (24u)
+
+/** \brief Length for Ifx_VADC_G_CEVNP0_Bits.CEV7NP */
+#define IFX_VADC_G_CEVNP0_CEV7NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_CEVNP0_Bits.CEV7NP */
+#define IFX_VADC_G_CEVNP0_CEV7NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_CEVNP0_Bits.CEV7NP */
+#define IFX_VADC_G_CEVNP0_CEV7NP_OFF (28u)
+
+/** \brief Length for Ifx_VADC_G_CEVNP1_Bits.CEV10NP */
+#define IFX_VADC_G_CEVNP1_CEV10NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_CEVNP1_Bits.CEV10NP */
+#define IFX_VADC_G_CEVNP1_CEV10NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_CEVNP1_Bits.CEV10NP */
+#define IFX_VADC_G_CEVNP1_CEV10NP_OFF (8u)
+
+/** \brief Length for Ifx_VADC_G_CEVNP1_Bits.CEV11NP */
+#define IFX_VADC_G_CEVNP1_CEV11NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_CEVNP1_Bits.CEV11NP */
+#define IFX_VADC_G_CEVNP1_CEV11NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_CEVNP1_Bits.CEV11NP */
+#define IFX_VADC_G_CEVNP1_CEV11NP_OFF (12u)
+
+/** \brief Length for Ifx_VADC_G_CEVNP1_Bits.CEV12NP */
+#define IFX_VADC_G_CEVNP1_CEV12NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_CEVNP1_Bits.CEV12NP */
+#define IFX_VADC_G_CEVNP1_CEV12NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_CEVNP1_Bits.CEV12NP */
+#define IFX_VADC_G_CEVNP1_CEV12NP_OFF (16u)
+
+/** \brief Length for Ifx_VADC_G_CEVNP1_Bits.CEV13NP */
+#define IFX_VADC_G_CEVNP1_CEV13NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_CEVNP1_Bits.CEV13NP */
+#define IFX_VADC_G_CEVNP1_CEV13NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_CEVNP1_Bits.CEV13NP */
+#define IFX_VADC_G_CEVNP1_CEV13NP_OFF (20u)
+
+/** \brief Length for Ifx_VADC_G_CEVNP1_Bits.CEV14NP */
+#define IFX_VADC_G_CEVNP1_CEV14NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_CEVNP1_Bits.CEV14NP */
+#define IFX_VADC_G_CEVNP1_CEV14NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_CEVNP1_Bits.CEV14NP */
+#define IFX_VADC_G_CEVNP1_CEV14NP_OFF (24u)
+
+/** \brief Length for Ifx_VADC_G_CEVNP1_Bits.CEV15NP */
+#define IFX_VADC_G_CEVNP1_CEV15NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_CEVNP1_Bits.CEV15NP */
+#define IFX_VADC_G_CEVNP1_CEV15NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_CEVNP1_Bits.CEV15NP */
+#define IFX_VADC_G_CEVNP1_CEV15NP_OFF (28u)
+
+/** \brief Length for Ifx_VADC_G_CEVNP1_Bits.CEV8NP */
+#define IFX_VADC_G_CEVNP1_CEV8NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_CEVNP1_Bits.CEV8NP */
+#define IFX_VADC_G_CEVNP1_CEV8NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_CEVNP1_Bits.CEV8NP */
+#define IFX_VADC_G_CEVNP1_CEV8NP_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_CEVNP1_Bits.CEV9NP */
+#define IFX_VADC_G_CEVNP1_CEV9NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_CEVNP1_Bits.CEV9NP */
+#define IFX_VADC_G_CEVNP1_CEV9NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_CEVNP1_Bits.CEV9NP */
+#define IFX_VADC_G_CEVNP1_CEV9NP_OFF (4u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH0 */
+#define IFX_VADC_G_CHASS_ASSCH0_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH0 */
+#define IFX_VADC_G_CHASS_ASSCH0_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH0 */
+#define IFX_VADC_G_CHASS_ASSCH0_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH10 */
+#define IFX_VADC_G_CHASS_ASSCH10_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH10 */
+#define IFX_VADC_G_CHASS_ASSCH10_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH10 */
+#define IFX_VADC_G_CHASS_ASSCH10_OFF (10u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH11 */
+#define IFX_VADC_G_CHASS_ASSCH11_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH11 */
+#define IFX_VADC_G_CHASS_ASSCH11_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH11 */
+#define IFX_VADC_G_CHASS_ASSCH11_OFF (11u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH12 */
+#define IFX_VADC_G_CHASS_ASSCH12_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH12 */
+#define IFX_VADC_G_CHASS_ASSCH12_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH12 */
+#define IFX_VADC_G_CHASS_ASSCH12_OFF (12u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH13 */
+#define IFX_VADC_G_CHASS_ASSCH13_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH13 */
+#define IFX_VADC_G_CHASS_ASSCH13_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH13 */
+#define IFX_VADC_G_CHASS_ASSCH13_OFF (13u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH14 */
+#define IFX_VADC_G_CHASS_ASSCH14_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH14 */
+#define IFX_VADC_G_CHASS_ASSCH14_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH14 */
+#define IFX_VADC_G_CHASS_ASSCH14_OFF (14u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH15 */
+#define IFX_VADC_G_CHASS_ASSCH15_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH15 */
+#define IFX_VADC_G_CHASS_ASSCH15_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH15 */
+#define IFX_VADC_G_CHASS_ASSCH15_OFF (15u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH16 */
+#define IFX_VADC_G_CHASS_ASSCH16_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH16 */
+#define IFX_VADC_G_CHASS_ASSCH16_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH16 */
+#define IFX_VADC_G_CHASS_ASSCH16_OFF (16u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH17 */
+#define IFX_VADC_G_CHASS_ASSCH17_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH17 */
+#define IFX_VADC_G_CHASS_ASSCH17_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH17 */
+#define IFX_VADC_G_CHASS_ASSCH17_OFF (17u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH18 */
+#define IFX_VADC_G_CHASS_ASSCH18_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH18 */
+#define IFX_VADC_G_CHASS_ASSCH18_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH18 */
+#define IFX_VADC_G_CHASS_ASSCH18_OFF (18u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH19 */
+#define IFX_VADC_G_CHASS_ASSCH19_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH19 */
+#define IFX_VADC_G_CHASS_ASSCH19_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH19 */
+#define IFX_VADC_G_CHASS_ASSCH19_OFF (19u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH1 */
+#define IFX_VADC_G_CHASS_ASSCH1_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH1 */
+#define IFX_VADC_G_CHASS_ASSCH1_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH1 */
+#define IFX_VADC_G_CHASS_ASSCH1_OFF (1u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH20 */
+#define IFX_VADC_G_CHASS_ASSCH20_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH20 */
+#define IFX_VADC_G_CHASS_ASSCH20_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH20 */
+#define IFX_VADC_G_CHASS_ASSCH20_OFF (20u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH21 */
+#define IFX_VADC_G_CHASS_ASSCH21_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH21 */
+#define IFX_VADC_G_CHASS_ASSCH21_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH21 */
+#define IFX_VADC_G_CHASS_ASSCH21_OFF (21u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH22 */
+#define IFX_VADC_G_CHASS_ASSCH22_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH22 */
+#define IFX_VADC_G_CHASS_ASSCH22_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH22 */
+#define IFX_VADC_G_CHASS_ASSCH22_OFF (22u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH23 */
+#define IFX_VADC_G_CHASS_ASSCH23_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH23 */
+#define IFX_VADC_G_CHASS_ASSCH23_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH23 */
+#define IFX_VADC_G_CHASS_ASSCH23_OFF (23u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH24 */
+#define IFX_VADC_G_CHASS_ASSCH24_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH24 */
+#define IFX_VADC_G_CHASS_ASSCH24_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH24 */
+#define IFX_VADC_G_CHASS_ASSCH24_OFF (24u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH25 */
+#define IFX_VADC_G_CHASS_ASSCH25_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH25 */
+#define IFX_VADC_G_CHASS_ASSCH25_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH25 */
+#define IFX_VADC_G_CHASS_ASSCH25_OFF (25u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH26 */
+#define IFX_VADC_G_CHASS_ASSCH26_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH26 */
+#define IFX_VADC_G_CHASS_ASSCH26_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH26 */
+#define IFX_VADC_G_CHASS_ASSCH26_OFF (26u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH27 */
+#define IFX_VADC_G_CHASS_ASSCH27_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH27 */
+#define IFX_VADC_G_CHASS_ASSCH27_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH27 */
+#define IFX_VADC_G_CHASS_ASSCH27_OFF (27u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH28 */
+#define IFX_VADC_G_CHASS_ASSCH28_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH28 */
+#define IFX_VADC_G_CHASS_ASSCH28_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH28 */
+#define IFX_VADC_G_CHASS_ASSCH28_OFF (28u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH29 */
+#define IFX_VADC_G_CHASS_ASSCH29_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH29 */
+#define IFX_VADC_G_CHASS_ASSCH29_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH29 */
+#define IFX_VADC_G_CHASS_ASSCH29_OFF (29u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH2 */
+#define IFX_VADC_G_CHASS_ASSCH2_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH2 */
+#define IFX_VADC_G_CHASS_ASSCH2_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH2 */
+#define IFX_VADC_G_CHASS_ASSCH2_OFF (2u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH30 */
+#define IFX_VADC_G_CHASS_ASSCH30_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH30 */
+#define IFX_VADC_G_CHASS_ASSCH30_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH30 */
+#define IFX_VADC_G_CHASS_ASSCH30_OFF (30u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH31 */
+#define IFX_VADC_G_CHASS_ASSCH31_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH31 */
+#define IFX_VADC_G_CHASS_ASSCH31_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH31 */
+#define IFX_VADC_G_CHASS_ASSCH31_OFF (31u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH3 */
+#define IFX_VADC_G_CHASS_ASSCH3_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH3 */
+#define IFX_VADC_G_CHASS_ASSCH3_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH3 */
+#define IFX_VADC_G_CHASS_ASSCH3_OFF (3u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH4 */
+#define IFX_VADC_G_CHASS_ASSCH4_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH4 */
+#define IFX_VADC_G_CHASS_ASSCH4_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH4 */
+#define IFX_VADC_G_CHASS_ASSCH4_OFF (4u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH5 */
+#define IFX_VADC_G_CHASS_ASSCH5_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH5 */
+#define IFX_VADC_G_CHASS_ASSCH5_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH5 */
+#define IFX_VADC_G_CHASS_ASSCH5_OFF (5u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH6 */
+#define IFX_VADC_G_CHASS_ASSCH6_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH6 */
+#define IFX_VADC_G_CHASS_ASSCH6_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH6 */
+#define IFX_VADC_G_CHASS_ASSCH6_OFF (6u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH7 */
+#define IFX_VADC_G_CHASS_ASSCH7_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH7 */
+#define IFX_VADC_G_CHASS_ASSCH7_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH7 */
+#define IFX_VADC_G_CHASS_ASSCH7_OFF (7u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH8 */
+#define IFX_VADC_G_CHASS_ASSCH8_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH8 */
+#define IFX_VADC_G_CHASS_ASSCH8_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH8 */
+#define IFX_VADC_G_CHASS_ASSCH8_OFF (8u)
+
+/** \brief Length for Ifx_VADC_G_CHASS_Bits.ASSCH9 */
+#define IFX_VADC_G_CHASS_ASSCH9_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHASS_Bits.ASSCH9 */
+#define IFX_VADC_G_CHASS_ASSCH9_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHASS_Bits.ASSCH9 */
+#define IFX_VADC_G_CHASS_ASSCH9_OFF (9u)
+
+/** \brief Length for Ifx_VADC_G_CHCTR_Bits.BNDSELL */
+#define IFX_VADC_G_CHCTR_BNDSELL_LEN (2u)
+
+/** \brief Mask for Ifx_VADC_G_CHCTR_Bits.BNDSELL */
+#define IFX_VADC_G_CHCTR_BNDSELL_MSK (0x3u)
+
+/** \brief Offset for Ifx_VADC_G_CHCTR_Bits.BNDSELL */
+#define IFX_VADC_G_CHCTR_BNDSELL_OFF (4u)
+
+/** \brief Length for Ifx_VADC_G_CHCTR_Bits.BNDSELU */
+#define IFX_VADC_G_CHCTR_BNDSELU_LEN (2u)
+
+/** \brief Mask for Ifx_VADC_G_CHCTR_Bits.BNDSELU */
+#define IFX_VADC_G_CHCTR_BNDSELU_MSK (0x3u)
+
+/** \brief Offset for Ifx_VADC_G_CHCTR_Bits.BNDSELU */
+#define IFX_VADC_G_CHCTR_BNDSELU_OFF (6u)
+
+/** \brief Length for Ifx_VADC_G_CHCTR_Bits.BNDSELX */
+#define IFX_VADC_G_CHCTR_BNDSELX_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_CHCTR_Bits.BNDSELX */
+#define IFX_VADC_G_CHCTR_BNDSELX_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_CHCTR_Bits.BNDSELX */
+#define IFX_VADC_G_CHCTR_BNDSELX_OFF (12u)
+
+/** \brief Length for Ifx_VADC_G_CHCTR_Bits.BWDCH */
+#define IFX_VADC_G_CHCTR_BWDCH_LEN (2u)
+
+/** \brief Mask for Ifx_VADC_G_CHCTR_Bits.BWDCH */
+#define IFX_VADC_G_CHCTR_BWDCH_MSK (0x3u)
+
+/** \brief Offset for Ifx_VADC_G_CHCTR_Bits.BWDCH */
+#define IFX_VADC_G_CHCTR_BWDCH_OFF (28u)
+
+/** \brief Length for Ifx_VADC_G_CHCTR_Bits.BWDEN */
+#define IFX_VADC_G_CHCTR_BWDEN_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHCTR_Bits.BWDEN */
+#define IFX_VADC_G_CHCTR_BWDEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHCTR_Bits.BWDEN */
+#define IFX_VADC_G_CHCTR_BWDEN_OFF (30u)
+
+/** \brief Length for Ifx_VADC_G_CHCTR_Bits.CHEVMODE */
+#define IFX_VADC_G_CHCTR_CHEVMODE_LEN (2u)
+
+/** \brief Mask for Ifx_VADC_G_CHCTR_Bits.CHEVMODE */
+#define IFX_VADC_G_CHCTR_CHEVMODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_VADC_G_CHCTR_Bits.CHEVMODE */
+#define IFX_VADC_G_CHCTR_CHEVMODE_OFF (8u)
+
+/** \brief Length for Ifx_VADC_G_CHCTR_Bits.ICLSEL */
+#define IFX_VADC_G_CHCTR_ICLSEL_LEN (2u)
+
+/** \brief Mask for Ifx_VADC_G_CHCTR_Bits.ICLSEL */
+#define IFX_VADC_G_CHCTR_ICLSEL_MSK (0x3u)
+
+/** \brief Offset for Ifx_VADC_G_CHCTR_Bits.ICLSEL */
+#define IFX_VADC_G_CHCTR_ICLSEL_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_CHCTR_Bits.REFSEL */
+#define IFX_VADC_G_CHCTR_REFSEL_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHCTR_Bits.REFSEL */
+#define IFX_VADC_G_CHCTR_REFSEL_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHCTR_Bits.REFSEL */
+#define IFX_VADC_G_CHCTR_REFSEL_OFF (11u)
+
+/** \brief Length for Ifx_VADC_G_CHCTR_Bits.RESPOS */
+#define IFX_VADC_G_CHCTR_RESPOS_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHCTR_Bits.RESPOS */
+#define IFX_VADC_G_CHCTR_RESPOS_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHCTR_Bits.RESPOS */
+#define IFX_VADC_G_CHCTR_RESPOS_OFF (21u)
+
+/** \brief Length for Ifx_VADC_G_CHCTR_Bits.RESREG */
+#define IFX_VADC_G_CHCTR_RESREG_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_CHCTR_Bits.RESREG */
+#define IFX_VADC_G_CHCTR_RESREG_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_CHCTR_Bits.RESREG */
+#define IFX_VADC_G_CHCTR_RESREG_OFF (16u)
+
+/** \brief Length for Ifx_VADC_G_CHCTR_Bits.RESTBS */
+#define IFX_VADC_G_CHCTR_RESTBS_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHCTR_Bits.RESTBS */
+#define IFX_VADC_G_CHCTR_RESTBS_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHCTR_Bits.RESTBS */
+#define IFX_VADC_G_CHCTR_RESTBS_OFF (20u)
+
+/** \brief Length for Ifx_VADC_G_CHCTR_Bits.SYNC */
+#define IFX_VADC_G_CHCTR_SYNC_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_CHCTR_Bits.SYNC */
+#define IFX_VADC_G_CHCTR_SYNC_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_CHCTR_Bits.SYNC */
+#define IFX_VADC_G_CHCTR_SYNC_OFF (10u)
+
+/** \brief Length for Ifx_VADC_G_EMUXCTR_Bits.EMUXACT */
+#define IFX_VADC_G_EMUXCTR_EMUXACT_LEN (3u)
+
+/** \brief Mask for Ifx_VADC_G_EMUXCTR_Bits.EMUXACT */
+#define IFX_VADC_G_EMUXCTR_EMUXACT_MSK (0x7u)
+
+/** \brief Offset for Ifx_VADC_G_EMUXCTR_Bits.EMUXACT */
+#define IFX_VADC_G_EMUXCTR_EMUXACT_OFF (8u)
+
+/** \brief Length for Ifx_VADC_G_EMUXCTR_Bits.EMUXCH */
+#define IFX_VADC_G_EMUXCTR_EMUXCH_LEN (10u)
+
+/** \brief Mask for Ifx_VADC_G_EMUXCTR_Bits.EMUXCH */
+#define IFX_VADC_G_EMUXCTR_EMUXCH_MSK (0x3ffu)
+
+/** \brief Offset for Ifx_VADC_G_EMUXCTR_Bits.EMUXCH */
+#define IFX_VADC_G_EMUXCTR_EMUXCH_OFF (16u)
+
+/** \brief Length for Ifx_VADC_G_EMUXCTR_Bits.EMUXMODE */
+#define IFX_VADC_G_EMUXCTR_EMUXMODE_LEN (2u)
+
+/** \brief Mask for Ifx_VADC_G_EMUXCTR_Bits.EMUXMODE */
+#define IFX_VADC_G_EMUXCTR_EMUXMODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_VADC_G_EMUXCTR_Bits.EMUXMODE */
+#define IFX_VADC_G_EMUXCTR_EMUXMODE_OFF (26u)
+
+/** \brief Length for Ifx_VADC_G_EMUXCTR_Bits.EMUXSET */
+#define IFX_VADC_G_EMUXCTR_EMUXSET_LEN (3u)
+
+/** \brief Mask for Ifx_VADC_G_EMUXCTR_Bits.EMUXSET */
+#define IFX_VADC_G_EMUXCTR_EMUXSET_MSK (0x7u)
+
+/** \brief Offset for Ifx_VADC_G_EMUXCTR_Bits.EMUXSET */
+#define IFX_VADC_G_EMUXCTR_EMUXSET_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_EMUXCTR_Bits.EMXCOD */
+#define IFX_VADC_G_EMUXCTR_EMXCOD_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_EMUXCTR_Bits.EMXCOD */
+#define IFX_VADC_G_EMUXCTR_EMXCOD_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_EMUXCTR_Bits.EMXCOD */
+#define IFX_VADC_G_EMUXCTR_EMXCOD_OFF (28u)
+
+/** \brief Length for Ifx_VADC_G_EMUXCTR_Bits.EMXCSS */
+#define IFX_VADC_G_EMUXCTR_EMXCSS_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_EMUXCTR_Bits.EMXCSS */
+#define IFX_VADC_G_EMUXCTR_EMXCSS_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_EMUXCTR_Bits.EMXCSS */
+#define IFX_VADC_G_EMUXCTR_EMXCSS_OFF (30u)
+
+/** \brief Length for Ifx_VADC_G_EMUXCTR_Bits.EMXST */
+#define IFX_VADC_G_EMUXCTR_EMXST_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_EMUXCTR_Bits.EMXST */
+#define IFX_VADC_G_EMUXCTR_EMXST_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_EMUXCTR_Bits.EMXST */
+#define IFX_VADC_G_EMUXCTR_EMXST_OFF (29u)
+
+/** \brief Length for Ifx_VADC_G_EMUXCTR_Bits.EMXWC */
+#define IFX_VADC_G_EMUXCTR_EMXWC_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_EMUXCTR_Bits.EMXWC */
+#define IFX_VADC_G_EMUXCTR_EMXWC_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_EMUXCTR_Bits.EMXWC */
+#define IFX_VADC_G_EMUXCTR_EMXWC_OFF (31u)
+
+/** \brief Length for Ifx_VADC_G_Q0R0_Bits.ENSI */
+#define IFX_VADC_G_Q0R0_ENSI_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_Q0R0_Bits.ENSI */
+#define IFX_VADC_G_Q0R0_ENSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_Q0R0_Bits.ENSI */
+#define IFX_VADC_G_Q0R0_ENSI_OFF (6u)
+
+/** \brief Length for Ifx_VADC_G_Q0R0_Bits.EXTR */
+#define IFX_VADC_G_Q0R0_EXTR_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_Q0R0_Bits.EXTR */
+#define IFX_VADC_G_Q0R0_EXTR_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_Q0R0_Bits.EXTR */
+#define IFX_VADC_G_Q0R0_EXTR_OFF (7u)
+
+/** \brief Length for Ifx_VADC_G_Q0R0_Bits.REQCHNR */
+#define IFX_VADC_G_Q0R0_REQCHNR_LEN (5u)
+
+/** \brief Mask for Ifx_VADC_G_Q0R0_Bits.REQCHNR */
+#define IFX_VADC_G_Q0R0_REQCHNR_MSK (0x1fu)
+
+/** \brief Offset for Ifx_VADC_G_Q0R0_Bits.REQCHNR */
+#define IFX_VADC_G_Q0R0_REQCHNR_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_Q0R0_Bits.RF */
+#define IFX_VADC_G_Q0R0_RF_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_Q0R0_Bits.RF */
+#define IFX_VADC_G_Q0R0_RF_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_Q0R0_Bits.RF */
+#define IFX_VADC_G_Q0R0_RF_OFF (5u)
+
+/** \brief Length for Ifx_VADC_G_Q0R0_Bits.V */
+#define IFX_VADC_G_Q0R0_V_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_Q0R0_Bits.V */
+#define IFX_VADC_G_Q0R0_V_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_Q0R0_Bits.V */
+#define IFX_VADC_G_Q0R0_V_OFF (8u)
+
+/** \brief Length for Ifx_VADC_G_QBUR0_Bits.ENSI */
+#define IFX_VADC_G_QBUR0_ENSI_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_QBUR0_Bits.ENSI */
+#define IFX_VADC_G_QBUR0_ENSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_QBUR0_Bits.ENSI */
+#define IFX_VADC_G_QBUR0_ENSI_OFF (6u)
+
+/** \brief Length for Ifx_VADC_G_QBUR0_Bits.EXTR */
+#define IFX_VADC_G_QBUR0_EXTR_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_QBUR0_Bits.EXTR */
+#define IFX_VADC_G_QBUR0_EXTR_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_QBUR0_Bits.EXTR */
+#define IFX_VADC_G_QBUR0_EXTR_OFF (7u)
+
+/** \brief Length for Ifx_VADC_G_QBUR0_Bits.REQCHNR */
+#define IFX_VADC_G_QBUR0_REQCHNR_LEN (5u)
+
+/** \brief Mask for Ifx_VADC_G_QBUR0_Bits.REQCHNR */
+#define IFX_VADC_G_QBUR0_REQCHNR_MSK (0x1fu)
+
+/** \brief Offset for Ifx_VADC_G_QBUR0_Bits.REQCHNR */
+#define IFX_VADC_G_QBUR0_REQCHNR_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_QBUR0_Bits.RF */
+#define IFX_VADC_G_QBUR0_RF_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_QBUR0_Bits.RF */
+#define IFX_VADC_G_QBUR0_RF_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_QBUR0_Bits.RF */
+#define IFX_VADC_G_QBUR0_RF_OFF (5u)
+
+/** \brief Length for Ifx_VADC_G_QBUR0_Bits.V */
+#define IFX_VADC_G_QBUR0_V_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_QBUR0_Bits.V */
+#define IFX_VADC_G_QBUR0_V_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_QBUR0_Bits.V */
+#define IFX_VADC_G_QBUR0_V_OFF (8u)
+
+/** \brief Length for Ifx_VADC_G_QCTRL0_Bits.GTLVL */
+#define IFX_VADC_G_QCTRL0_GTLVL_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_QCTRL0_Bits.GTLVL */
+#define IFX_VADC_G_QCTRL0_GTLVL_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_QCTRL0_Bits.GTLVL */
+#define IFX_VADC_G_QCTRL0_GTLVL_OFF (20u)
+
+/** \brief Length for Ifx_VADC_G_QCTRL0_Bits.GTSEL */
+#define IFX_VADC_G_QCTRL0_GTSEL_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_QCTRL0_Bits.GTSEL */
+#define IFX_VADC_G_QCTRL0_GTSEL_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_QCTRL0_Bits.GTSEL */
+#define IFX_VADC_G_QCTRL0_GTSEL_OFF (16u)
+
+/** \brief Length for Ifx_VADC_G_QCTRL0_Bits.GTWC */
+#define IFX_VADC_G_QCTRL0_GTWC_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_QCTRL0_Bits.GTWC */
+#define IFX_VADC_G_QCTRL0_GTWC_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_QCTRL0_Bits.GTWC */
+#define IFX_VADC_G_QCTRL0_GTWC_OFF (23u)
+
+/** \brief Length for Ifx_VADC_G_QCTRL0_Bits.SRCRESREG */
+#define IFX_VADC_G_QCTRL0_SRCRESREG_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_QCTRL0_Bits.SRCRESREG */
+#define IFX_VADC_G_QCTRL0_SRCRESREG_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_QCTRL0_Bits.SRCRESREG */
+#define IFX_VADC_G_QCTRL0_SRCRESREG_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_QCTRL0_Bits.TMEN */
+#define IFX_VADC_G_QCTRL0_TMEN_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_QCTRL0_Bits.TMEN */
+#define IFX_VADC_G_QCTRL0_TMEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_QCTRL0_Bits.TMEN */
+#define IFX_VADC_G_QCTRL0_TMEN_OFF (28u)
+
+/** \brief Length for Ifx_VADC_G_QCTRL0_Bits.TMWC */
+#define IFX_VADC_G_QCTRL0_TMWC_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_QCTRL0_Bits.TMWC */
+#define IFX_VADC_G_QCTRL0_TMWC_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_QCTRL0_Bits.TMWC */
+#define IFX_VADC_G_QCTRL0_TMWC_OFF (31u)
+
+/** \brief Length for Ifx_VADC_G_QCTRL0_Bits.XTLVL */
+#define IFX_VADC_G_QCTRL0_XTLVL_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_QCTRL0_Bits.XTLVL */
+#define IFX_VADC_G_QCTRL0_XTLVL_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_QCTRL0_Bits.XTLVL */
+#define IFX_VADC_G_QCTRL0_XTLVL_OFF (12u)
+
+/** \brief Length for Ifx_VADC_G_QCTRL0_Bits.XTMODE */
+#define IFX_VADC_G_QCTRL0_XTMODE_LEN (2u)
+
+/** \brief Mask for Ifx_VADC_G_QCTRL0_Bits.XTMODE */
+#define IFX_VADC_G_QCTRL0_XTMODE_MSK (0x3u)
+
+/** \brief Offset for Ifx_VADC_G_QCTRL0_Bits.XTMODE */
+#define IFX_VADC_G_QCTRL0_XTMODE_OFF (13u)
+
+/** \brief Length for Ifx_VADC_G_QCTRL0_Bits.XTSEL */
+#define IFX_VADC_G_QCTRL0_XTSEL_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_QCTRL0_Bits.XTSEL */
+#define IFX_VADC_G_QCTRL0_XTSEL_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_QCTRL0_Bits.XTSEL */
+#define IFX_VADC_G_QCTRL0_XTSEL_OFF (8u)
+
+/** \brief Length for Ifx_VADC_G_QCTRL0_Bits.XTWC */
+#define IFX_VADC_G_QCTRL0_XTWC_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_QCTRL0_Bits.XTWC */
+#define IFX_VADC_G_QCTRL0_XTWC_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_QCTRL0_Bits.XTWC */
+#define IFX_VADC_G_QCTRL0_XTWC_OFF (15u)
+
+/** \brief Length for Ifx_VADC_G_QINR0_Bits.ENSI */
+#define IFX_VADC_G_QINR0_ENSI_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_QINR0_Bits.ENSI */
+#define IFX_VADC_G_QINR0_ENSI_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_QINR0_Bits.ENSI */
+#define IFX_VADC_G_QINR0_ENSI_OFF (6u)
+
+/** \brief Length for Ifx_VADC_G_QINR0_Bits.EXTR */
+#define IFX_VADC_G_QINR0_EXTR_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_QINR0_Bits.EXTR */
+#define IFX_VADC_G_QINR0_EXTR_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_QINR0_Bits.EXTR */
+#define IFX_VADC_G_QINR0_EXTR_OFF (7u)
+
+/** \brief Length for Ifx_VADC_G_QINR0_Bits.REQCHNR */
+#define IFX_VADC_G_QINR0_REQCHNR_LEN (5u)
+
+/** \brief Mask for Ifx_VADC_G_QINR0_Bits.REQCHNR */
+#define IFX_VADC_G_QINR0_REQCHNR_MSK (0x1fu)
+
+/** \brief Offset for Ifx_VADC_G_QINR0_Bits.REQCHNR */
+#define IFX_VADC_G_QINR0_REQCHNR_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_QINR0_Bits.RF */
+#define IFX_VADC_G_QINR0_RF_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_QINR0_Bits.RF */
+#define IFX_VADC_G_QINR0_RF_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_QINR0_Bits.RF */
+#define IFX_VADC_G_QINR0_RF_OFF (5u)
+
+/** \brief Length for Ifx_VADC_G_QMR0_Bits.CEV */
+#define IFX_VADC_G_QMR0_CEV_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_QMR0_Bits.CEV */
+#define IFX_VADC_G_QMR0_CEV_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_QMR0_Bits.CEV */
+#define IFX_VADC_G_QMR0_CEV_OFF (11u)
+
+/** \brief Length for Ifx_VADC_G_QMR0_Bits.CLRV */
+#define IFX_VADC_G_QMR0_CLRV_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_QMR0_Bits.CLRV */
+#define IFX_VADC_G_QMR0_CLRV_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_QMR0_Bits.CLRV */
+#define IFX_VADC_G_QMR0_CLRV_OFF (8u)
+
+/** \brief Length for Ifx_VADC_G_QMR0_Bits.ENGT */
+#define IFX_VADC_G_QMR0_ENGT_LEN (2u)
+
+/** \brief Mask for Ifx_VADC_G_QMR0_Bits.ENGT */
+#define IFX_VADC_G_QMR0_ENGT_MSK (0x3u)
+
+/** \brief Offset for Ifx_VADC_G_QMR0_Bits.ENGT */
+#define IFX_VADC_G_QMR0_ENGT_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_QMR0_Bits.ENTR */
+#define IFX_VADC_G_QMR0_ENTR_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_QMR0_Bits.ENTR */
+#define IFX_VADC_G_QMR0_ENTR_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_QMR0_Bits.ENTR */
+#define IFX_VADC_G_QMR0_ENTR_OFF (2u)
+
+/** \brief Length for Ifx_VADC_G_QMR0_Bits.FLUSH */
+#define IFX_VADC_G_QMR0_FLUSH_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_QMR0_Bits.FLUSH */
+#define IFX_VADC_G_QMR0_FLUSH_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_QMR0_Bits.FLUSH */
+#define IFX_VADC_G_QMR0_FLUSH_OFF (10u)
+
+/** \brief Length for Ifx_VADC_G_QMR0_Bits.RPTDIS */
+#define IFX_VADC_G_QMR0_RPTDIS_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_QMR0_Bits.RPTDIS */
+#define IFX_VADC_G_QMR0_RPTDIS_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_QMR0_Bits.RPTDIS */
+#define IFX_VADC_G_QMR0_RPTDIS_OFF (16u)
+
+/** \brief Length for Ifx_VADC_G_QMR0_Bits.TREV */
+#define IFX_VADC_G_QMR0_TREV_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_QMR0_Bits.TREV */
+#define IFX_VADC_G_QMR0_TREV_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_QMR0_Bits.TREV */
+#define IFX_VADC_G_QMR0_TREV_OFF (9u)
+
+/** \brief Length for Ifx_VADC_G_QSR0_Bits.EMPTY */
+#define IFX_VADC_G_QSR0_EMPTY_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_QSR0_Bits.EMPTY */
+#define IFX_VADC_G_QSR0_EMPTY_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_QSR0_Bits.EMPTY */
+#define IFX_VADC_G_QSR0_EMPTY_OFF (5u)
+
+/** \brief Length for Ifx_VADC_G_QSR0_Bits.EV */
+#define IFX_VADC_G_QSR0_EV_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_QSR0_Bits.EV */
+#define IFX_VADC_G_QSR0_EV_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_QSR0_Bits.EV */
+#define IFX_VADC_G_QSR0_EV_OFF (8u)
+
+/** \brief Length for Ifx_VADC_G_QSR0_Bits.FILL */
+#define IFX_VADC_G_QSR0_FILL_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_QSR0_Bits.FILL */
+#define IFX_VADC_G_QSR0_FILL_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_QSR0_Bits.FILL */
+#define IFX_VADC_G_QSR0_FILL_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_QSR0_Bits.REQGT */
+#define IFX_VADC_G_QSR0_REQGT_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_QSR0_Bits.REQGT */
+#define IFX_VADC_G_QSR0_REQGT_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_QSR0_Bits.REQGT */
+#define IFX_VADC_G_QSR0_REQGT_OFF (7u)
+
+/** \brief Length for Ifx_VADC_G_RCR_Bits.DMM */
+#define IFX_VADC_G_RCR_DMM_LEN (2u)
+
+/** \brief Mask for Ifx_VADC_G_RCR_Bits.DMM */
+#define IFX_VADC_G_RCR_DMM_MSK (0x3u)
+
+/** \brief Offset for Ifx_VADC_G_RCR_Bits.DMM */
+#define IFX_VADC_G_RCR_DMM_OFF (20u)
+
+/** \brief Length for Ifx_VADC_G_RCR_Bits.DRCTR */
+#define IFX_VADC_G_RCR_DRCTR_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_RCR_Bits.DRCTR */
+#define IFX_VADC_G_RCR_DRCTR_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_RCR_Bits.DRCTR */
+#define IFX_VADC_G_RCR_DRCTR_OFF (16u)
+
+/** \brief Length for Ifx_VADC_G_RCR_Bits.FEN */
+#define IFX_VADC_G_RCR_FEN_LEN (2u)
+
+/** \brief Mask for Ifx_VADC_G_RCR_Bits.FEN */
+#define IFX_VADC_G_RCR_FEN_MSK (0x3u)
+
+/** \brief Offset for Ifx_VADC_G_RCR_Bits.FEN */
+#define IFX_VADC_G_RCR_FEN_OFF (25u)
+
+/** \brief Length for Ifx_VADC_G_RCR_Bits.SRGEN */
+#define IFX_VADC_G_RCR_SRGEN_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_RCR_Bits.SRGEN */
+#define IFX_VADC_G_RCR_SRGEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_RCR_Bits.SRGEN */
+#define IFX_VADC_G_RCR_SRGEN_OFF (31u)
+
+/** \brief Length for Ifx_VADC_G_RCR_Bits.WFR */
+#define IFX_VADC_G_RCR_WFR_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_RCR_Bits.WFR */
+#define IFX_VADC_G_RCR_WFR_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_RCR_Bits.WFR */
+#define IFX_VADC_G_RCR_WFR_OFF (24u)
+
+/** \brief Length for Ifx_VADC_G_REFCLR_Bits.REV0 */
+#define IFX_VADC_G_REFCLR_REV0_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFCLR_Bits.REV0 */
+#define IFX_VADC_G_REFCLR_REV0_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFCLR_Bits.REV0 */
+#define IFX_VADC_G_REFCLR_REV0_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_REFCLR_Bits.REV10 */
+#define IFX_VADC_G_REFCLR_REV10_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFCLR_Bits.REV10 */
+#define IFX_VADC_G_REFCLR_REV10_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFCLR_Bits.REV10 */
+#define IFX_VADC_G_REFCLR_REV10_OFF (10u)
+
+/** \brief Length for Ifx_VADC_G_REFCLR_Bits.REV11 */
+#define IFX_VADC_G_REFCLR_REV11_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFCLR_Bits.REV11 */
+#define IFX_VADC_G_REFCLR_REV11_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFCLR_Bits.REV11 */
+#define IFX_VADC_G_REFCLR_REV11_OFF (11u)
+
+/** \brief Length for Ifx_VADC_G_REFCLR_Bits.REV12 */
+#define IFX_VADC_G_REFCLR_REV12_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFCLR_Bits.REV12 */
+#define IFX_VADC_G_REFCLR_REV12_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFCLR_Bits.REV12 */
+#define IFX_VADC_G_REFCLR_REV12_OFF (12u)
+
+/** \brief Length for Ifx_VADC_G_REFCLR_Bits.REV13 */
+#define IFX_VADC_G_REFCLR_REV13_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFCLR_Bits.REV13 */
+#define IFX_VADC_G_REFCLR_REV13_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFCLR_Bits.REV13 */
+#define IFX_VADC_G_REFCLR_REV13_OFF (13u)
+
+/** \brief Length for Ifx_VADC_G_REFCLR_Bits.REV14 */
+#define IFX_VADC_G_REFCLR_REV14_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFCLR_Bits.REV14 */
+#define IFX_VADC_G_REFCLR_REV14_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFCLR_Bits.REV14 */
+#define IFX_VADC_G_REFCLR_REV14_OFF (14u)
+
+/** \brief Length for Ifx_VADC_G_REFCLR_Bits.REV15 */
+#define IFX_VADC_G_REFCLR_REV15_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFCLR_Bits.REV15 */
+#define IFX_VADC_G_REFCLR_REV15_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFCLR_Bits.REV15 */
+#define IFX_VADC_G_REFCLR_REV15_OFF (15u)
+
+/** \brief Length for Ifx_VADC_G_REFCLR_Bits.REV1 */
+#define IFX_VADC_G_REFCLR_REV1_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFCLR_Bits.REV1 */
+#define IFX_VADC_G_REFCLR_REV1_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFCLR_Bits.REV1 */
+#define IFX_VADC_G_REFCLR_REV1_OFF (1u)
+
+/** \brief Length for Ifx_VADC_G_REFCLR_Bits.REV2 */
+#define IFX_VADC_G_REFCLR_REV2_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFCLR_Bits.REV2 */
+#define IFX_VADC_G_REFCLR_REV2_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFCLR_Bits.REV2 */
+#define IFX_VADC_G_REFCLR_REV2_OFF (2u)
+
+/** \brief Length for Ifx_VADC_G_REFCLR_Bits.REV3 */
+#define IFX_VADC_G_REFCLR_REV3_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFCLR_Bits.REV3 */
+#define IFX_VADC_G_REFCLR_REV3_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFCLR_Bits.REV3 */
+#define IFX_VADC_G_REFCLR_REV3_OFF (3u)
+
+/** \brief Length for Ifx_VADC_G_REFCLR_Bits.REV4 */
+#define IFX_VADC_G_REFCLR_REV4_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFCLR_Bits.REV4 */
+#define IFX_VADC_G_REFCLR_REV4_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFCLR_Bits.REV4 */
+#define IFX_VADC_G_REFCLR_REV4_OFF (4u)
+
+/** \brief Length for Ifx_VADC_G_REFCLR_Bits.REV5 */
+#define IFX_VADC_G_REFCLR_REV5_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFCLR_Bits.REV5 */
+#define IFX_VADC_G_REFCLR_REV5_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFCLR_Bits.REV5 */
+#define IFX_VADC_G_REFCLR_REV5_OFF (5u)
+
+/** \brief Length for Ifx_VADC_G_REFCLR_Bits.REV6 */
+#define IFX_VADC_G_REFCLR_REV6_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFCLR_Bits.REV6 */
+#define IFX_VADC_G_REFCLR_REV6_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFCLR_Bits.REV6 */
+#define IFX_VADC_G_REFCLR_REV6_OFF (6u)
+
+/** \brief Length for Ifx_VADC_G_REFCLR_Bits.REV7 */
+#define IFX_VADC_G_REFCLR_REV7_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFCLR_Bits.REV7 */
+#define IFX_VADC_G_REFCLR_REV7_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFCLR_Bits.REV7 */
+#define IFX_VADC_G_REFCLR_REV7_OFF (7u)
+
+/** \brief Length for Ifx_VADC_G_REFCLR_Bits.REV8 */
+#define IFX_VADC_G_REFCLR_REV8_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFCLR_Bits.REV8 */
+#define IFX_VADC_G_REFCLR_REV8_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFCLR_Bits.REV8 */
+#define IFX_VADC_G_REFCLR_REV8_OFF (8u)
+
+/** \brief Length for Ifx_VADC_G_REFCLR_Bits.REV9 */
+#define IFX_VADC_G_REFCLR_REV9_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFCLR_Bits.REV9 */
+#define IFX_VADC_G_REFCLR_REV9_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFCLR_Bits.REV9 */
+#define IFX_VADC_G_REFCLR_REV9_OFF (9u)
+
+/** \brief Length for Ifx_VADC_G_REFLAG_Bits.REV0 */
+#define IFX_VADC_G_REFLAG_REV0_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFLAG_Bits.REV0 */
+#define IFX_VADC_G_REFLAG_REV0_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFLAG_Bits.REV0 */
+#define IFX_VADC_G_REFLAG_REV0_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_REFLAG_Bits.REV10 */
+#define IFX_VADC_G_REFLAG_REV10_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFLAG_Bits.REV10 */
+#define IFX_VADC_G_REFLAG_REV10_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFLAG_Bits.REV10 */
+#define IFX_VADC_G_REFLAG_REV10_OFF (10u)
+
+/** \brief Length for Ifx_VADC_G_REFLAG_Bits.REV11 */
+#define IFX_VADC_G_REFLAG_REV11_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFLAG_Bits.REV11 */
+#define IFX_VADC_G_REFLAG_REV11_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFLAG_Bits.REV11 */
+#define IFX_VADC_G_REFLAG_REV11_OFF (11u)
+
+/** \brief Length for Ifx_VADC_G_REFLAG_Bits.REV12 */
+#define IFX_VADC_G_REFLAG_REV12_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFLAG_Bits.REV12 */
+#define IFX_VADC_G_REFLAG_REV12_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFLAG_Bits.REV12 */
+#define IFX_VADC_G_REFLAG_REV12_OFF (12u)
+
+/** \brief Length for Ifx_VADC_G_REFLAG_Bits.REV13 */
+#define IFX_VADC_G_REFLAG_REV13_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFLAG_Bits.REV13 */
+#define IFX_VADC_G_REFLAG_REV13_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFLAG_Bits.REV13 */
+#define IFX_VADC_G_REFLAG_REV13_OFF (13u)
+
+/** \brief Length for Ifx_VADC_G_REFLAG_Bits.REV14 */
+#define IFX_VADC_G_REFLAG_REV14_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFLAG_Bits.REV14 */
+#define IFX_VADC_G_REFLAG_REV14_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFLAG_Bits.REV14 */
+#define IFX_VADC_G_REFLAG_REV14_OFF (14u)
+
+/** \brief Length for Ifx_VADC_G_REFLAG_Bits.REV15 */
+#define IFX_VADC_G_REFLAG_REV15_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFLAG_Bits.REV15 */
+#define IFX_VADC_G_REFLAG_REV15_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFLAG_Bits.REV15 */
+#define IFX_VADC_G_REFLAG_REV15_OFF (15u)
+
+/** \brief Length for Ifx_VADC_G_REFLAG_Bits.REV1 */
+#define IFX_VADC_G_REFLAG_REV1_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFLAG_Bits.REV1 */
+#define IFX_VADC_G_REFLAG_REV1_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFLAG_Bits.REV1 */
+#define IFX_VADC_G_REFLAG_REV1_OFF (1u)
+
+/** \brief Length for Ifx_VADC_G_REFLAG_Bits.REV2 */
+#define IFX_VADC_G_REFLAG_REV2_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFLAG_Bits.REV2 */
+#define IFX_VADC_G_REFLAG_REV2_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFLAG_Bits.REV2 */
+#define IFX_VADC_G_REFLAG_REV2_OFF (2u)
+
+/** \brief Length for Ifx_VADC_G_REFLAG_Bits.REV3 */
+#define IFX_VADC_G_REFLAG_REV3_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFLAG_Bits.REV3 */
+#define IFX_VADC_G_REFLAG_REV3_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFLAG_Bits.REV3 */
+#define IFX_VADC_G_REFLAG_REV3_OFF (3u)
+
+/** \brief Length for Ifx_VADC_G_REFLAG_Bits.REV4 */
+#define IFX_VADC_G_REFLAG_REV4_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFLAG_Bits.REV4 */
+#define IFX_VADC_G_REFLAG_REV4_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFLAG_Bits.REV4 */
+#define IFX_VADC_G_REFLAG_REV4_OFF (4u)
+
+/** \brief Length for Ifx_VADC_G_REFLAG_Bits.REV5 */
+#define IFX_VADC_G_REFLAG_REV5_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFLAG_Bits.REV5 */
+#define IFX_VADC_G_REFLAG_REV5_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFLAG_Bits.REV5 */
+#define IFX_VADC_G_REFLAG_REV5_OFF (5u)
+
+/** \brief Length for Ifx_VADC_G_REFLAG_Bits.REV6 */
+#define IFX_VADC_G_REFLAG_REV6_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFLAG_Bits.REV6 */
+#define IFX_VADC_G_REFLAG_REV6_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFLAG_Bits.REV6 */
+#define IFX_VADC_G_REFLAG_REV6_OFF (6u)
+
+/** \brief Length for Ifx_VADC_G_REFLAG_Bits.REV7 */
+#define IFX_VADC_G_REFLAG_REV7_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFLAG_Bits.REV7 */
+#define IFX_VADC_G_REFLAG_REV7_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFLAG_Bits.REV7 */
+#define IFX_VADC_G_REFLAG_REV7_OFF (7u)
+
+/** \brief Length for Ifx_VADC_G_REFLAG_Bits.REV8 */
+#define IFX_VADC_G_REFLAG_REV8_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFLAG_Bits.REV8 */
+#define IFX_VADC_G_REFLAG_REV8_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFLAG_Bits.REV8 */
+#define IFX_VADC_G_REFLAG_REV8_OFF (8u)
+
+/** \brief Length for Ifx_VADC_G_REFLAG_Bits.REV9 */
+#define IFX_VADC_G_REFLAG_REV9_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_REFLAG_Bits.REV9 */
+#define IFX_VADC_G_REFLAG_REV9_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_REFLAG_Bits.REV9 */
+#define IFX_VADC_G_REFLAG_REV9_OFF (9u)
+
+/** \brief Length for Ifx_VADC_G_RES_Bits.CHNR */
+#define IFX_VADC_G_RES_CHNR_LEN (5u)
+
+/** \brief Mask for Ifx_VADC_G_RES_Bits.CHNR */
+#define IFX_VADC_G_RES_CHNR_MSK (0x1fu)
+
+/** \brief Offset for Ifx_VADC_G_RES_Bits.CHNR */
+#define IFX_VADC_G_RES_CHNR_OFF (20u)
+
+/** \brief Length for Ifx_VADC_G_RES_Bits.CRS */
+#define IFX_VADC_G_RES_CRS_LEN (2u)
+
+/** \brief Mask for Ifx_VADC_G_RES_Bits.CRS */
+#define IFX_VADC_G_RES_CRS_MSK (0x3u)
+
+/** \brief Offset for Ifx_VADC_G_RES_Bits.CRS */
+#define IFX_VADC_G_RES_CRS_OFF (28u)
+
+/** \brief Length for Ifx_VADC_G_RES_Bits.DRC */
+#define IFX_VADC_G_RES_DRC_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_RES_Bits.DRC */
+#define IFX_VADC_G_RES_DRC_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_RES_Bits.DRC */
+#define IFX_VADC_G_RES_DRC_OFF (16u)
+
+/** \brief Length for Ifx_VADC_G_RES_Bits.EMUX */
+#define IFX_VADC_G_RES_EMUX_LEN (3u)
+
+/** \brief Mask for Ifx_VADC_G_RES_Bits.EMUX */
+#define IFX_VADC_G_RES_EMUX_MSK (0x7u)
+
+/** \brief Offset for Ifx_VADC_G_RES_Bits.EMUX */
+#define IFX_VADC_G_RES_EMUX_OFF (25u)
+
+/** \brief Length for Ifx_VADC_G_RES_Bits.FCR */
+#define IFX_VADC_G_RES_FCR_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_RES_Bits.FCR */
+#define IFX_VADC_G_RES_FCR_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_RES_Bits.FCR */
+#define IFX_VADC_G_RES_FCR_OFF (30u)
+
+/** \brief Length for Ifx_VADC_G_RES_Bits.RESULT */
+#define IFX_VADC_G_RES_RESULT_LEN (16u)
+
+/** \brief Mask for Ifx_VADC_G_RES_Bits.RESULT */
+#define IFX_VADC_G_RES_RESULT_MSK (0xffffu)
+
+/** \brief Offset for Ifx_VADC_G_RES_Bits.RESULT */
+#define IFX_VADC_G_RES_RESULT_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_RES_Bits.VF */
+#define IFX_VADC_G_RES_VF_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_RES_Bits.VF */
+#define IFX_VADC_G_RES_VF_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_RES_Bits.VF */
+#define IFX_VADC_G_RES_VF_OFF (31u)
+
+/** \brief Length for Ifx_VADC_G_RESD_Bits.CHNR */
+#define IFX_VADC_G_RESD_CHNR_LEN (5u)
+
+/** \brief Mask for Ifx_VADC_G_RESD_Bits.CHNR */
+#define IFX_VADC_G_RESD_CHNR_MSK (0x1fu)
+
+/** \brief Offset for Ifx_VADC_G_RESD_Bits.CHNR */
+#define IFX_VADC_G_RESD_CHNR_OFF (20u)
+
+/** \brief Length for Ifx_VADC_G_RESD_Bits.CRS */
+#define IFX_VADC_G_RESD_CRS_LEN (2u)
+
+/** \brief Mask for Ifx_VADC_G_RESD_Bits.CRS */
+#define IFX_VADC_G_RESD_CRS_MSK (0x3u)
+
+/** \brief Offset for Ifx_VADC_G_RESD_Bits.CRS */
+#define IFX_VADC_G_RESD_CRS_OFF (28u)
+
+/** \brief Length for Ifx_VADC_G_RESD_Bits.DRC */
+#define IFX_VADC_G_RESD_DRC_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_RESD_Bits.DRC */
+#define IFX_VADC_G_RESD_DRC_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_RESD_Bits.DRC */
+#define IFX_VADC_G_RESD_DRC_OFF (16u)
+
+/** \brief Length for Ifx_VADC_G_RESD_Bits.EMUX */
+#define IFX_VADC_G_RESD_EMUX_LEN (3u)
+
+/** \brief Mask for Ifx_VADC_G_RESD_Bits.EMUX */
+#define IFX_VADC_G_RESD_EMUX_MSK (0x7u)
+
+/** \brief Offset for Ifx_VADC_G_RESD_Bits.EMUX */
+#define IFX_VADC_G_RESD_EMUX_OFF (25u)
+
+/** \brief Length for Ifx_VADC_G_RESD_Bits.FCR */
+#define IFX_VADC_G_RESD_FCR_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_RESD_Bits.FCR */
+#define IFX_VADC_G_RESD_FCR_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_RESD_Bits.FCR */
+#define IFX_VADC_G_RESD_FCR_OFF (30u)
+
+/** \brief Length for Ifx_VADC_G_RESD_Bits.RESULT */
+#define IFX_VADC_G_RESD_RESULT_LEN (16u)
+
+/** \brief Mask for Ifx_VADC_G_RESD_Bits.RESULT */
+#define IFX_VADC_G_RESD_RESULT_MSK (0xffffu)
+
+/** \brief Offset for Ifx_VADC_G_RESD_Bits.RESULT */
+#define IFX_VADC_G_RESD_RESULT_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_RESD_Bits.VF */
+#define IFX_VADC_G_RESD_VF_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_RESD_Bits.VF */
+#define IFX_VADC_G_RESD_VF_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_RESD_Bits.VF */
+#define IFX_VADC_G_RESD_VF_OFF (31u)
+
+/** \brief Length for Ifx_VADC_G_REVNP0_Bits.REV0NP */
+#define IFX_VADC_G_REVNP0_REV0NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_REVNP0_Bits.REV0NP */
+#define IFX_VADC_G_REVNP0_REV0NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_REVNP0_Bits.REV0NP */
+#define IFX_VADC_G_REVNP0_REV0NP_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_REVNP0_Bits.REV1NP */
+#define IFX_VADC_G_REVNP0_REV1NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_REVNP0_Bits.REV1NP */
+#define IFX_VADC_G_REVNP0_REV1NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_REVNP0_Bits.REV1NP */
+#define IFX_VADC_G_REVNP0_REV1NP_OFF (4u)
+
+/** \brief Length for Ifx_VADC_G_REVNP0_Bits.REV2NP */
+#define IFX_VADC_G_REVNP0_REV2NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_REVNP0_Bits.REV2NP */
+#define IFX_VADC_G_REVNP0_REV2NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_REVNP0_Bits.REV2NP */
+#define IFX_VADC_G_REVNP0_REV2NP_OFF (8u)
+
+/** \brief Length for Ifx_VADC_G_REVNP0_Bits.REV3NP */
+#define IFX_VADC_G_REVNP0_REV3NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_REVNP0_Bits.REV3NP */
+#define IFX_VADC_G_REVNP0_REV3NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_REVNP0_Bits.REV3NP */
+#define IFX_VADC_G_REVNP0_REV3NP_OFF (12u)
+
+/** \brief Length for Ifx_VADC_G_REVNP0_Bits.REV4NP */
+#define IFX_VADC_G_REVNP0_REV4NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_REVNP0_Bits.REV4NP */
+#define IFX_VADC_G_REVNP0_REV4NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_REVNP0_Bits.REV4NP */
+#define IFX_VADC_G_REVNP0_REV4NP_OFF (16u)
+
+/** \brief Length for Ifx_VADC_G_REVNP0_Bits.REV5NP */
+#define IFX_VADC_G_REVNP0_REV5NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_REVNP0_Bits.REV5NP */
+#define IFX_VADC_G_REVNP0_REV5NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_REVNP0_Bits.REV5NP */
+#define IFX_VADC_G_REVNP0_REV5NP_OFF (20u)
+
+/** \brief Length for Ifx_VADC_G_REVNP0_Bits.REV6NP */
+#define IFX_VADC_G_REVNP0_REV6NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_REVNP0_Bits.REV6NP */
+#define IFX_VADC_G_REVNP0_REV6NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_REVNP0_Bits.REV6NP */
+#define IFX_VADC_G_REVNP0_REV6NP_OFF (24u)
+
+/** \brief Length for Ifx_VADC_G_REVNP0_Bits.REV7NP */
+#define IFX_VADC_G_REVNP0_REV7NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_REVNP0_Bits.REV7NP */
+#define IFX_VADC_G_REVNP0_REV7NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_REVNP0_Bits.REV7NP */
+#define IFX_VADC_G_REVNP0_REV7NP_OFF (28u)
+
+/** \brief Length for Ifx_VADC_G_REVNP1_Bits.REV10NP */
+#define IFX_VADC_G_REVNP1_REV10NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_REVNP1_Bits.REV10NP */
+#define IFX_VADC_G_REVNP1_REV10NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_REVNP1_Bits.REV10NP */
+#define IFX_VADC_G_REVNP1_REV10NP_OFF (8u)
+
+/** \brief Length for Ifx_VADC_G_REVNP1_Bits.REV11NP */
+#define IFX_VADC_G_REVNP1_REV11NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_REVNP1_Bits.REV11NP */
+#define IFX_VADC_G_REVNP1_REV11NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_REVNP1_Bits.REV11NP */
+#define IFX_VADC_G_REVNP1_REV11NP_OFF (12u)
+
+/** \brief Length for Ifx_VADC_G_REVNP1_Bits.REV12NP */
+#define IFX_VADC_G_REVNP1_REV12NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_REVNP1_Bits.REV12NP */
+#define IFX_VADC_G_REVNP1_REV12NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_REVNP1_Bits.REV12NP */
+#define IFX_VADC_G_REVNP1_REV12NP_OFF (16u)
+
+/** \brief Length for Ifx_VADC_G_REVNP1_Bits.REV13NP */
+#define IFX_VADC_G_REVNP1_REV13NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_REVNP1_Bits.REV13NP */
+#define IFX_VADC_G_REVNP1_REV13NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_REVNP1_Bits.REV13NP */
+#define IFX_VADC_G_REVNP1_REV13NP_OFF (20u)
+
+/** \brief Length for Ifx_VADC_G_REVNP1_Bits.REV14NP */
+#define IFX_VADC_G_REVNP1_REV14NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_REVNP1_Bits.REV14NP */
+#define IFX_VADC_G_REVNP1_REV14NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_REVNP1_Bits.REV14NP */
+#define IFX_VADC_G_REVNP1_REV14NP_OFF (24u)
+
+/** \brief Length for Ifx_VADC_G_REVNP1_Bits.REV15NP */
+#define IFX_VADC_G_REVNP1_REV15NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_REVNP1_Bits.REV15NP */
+#define IFX_VADC_G_REVNP1_REV15NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_REVNP1_Bits.REV15NP */
+#define IFX_VADC_G_REVNP1_REV15NP_OFF (28u)
+
+/** \brief Length for Ifx_VADC_G_REVNP1_Bits.REV8NP */
+#define IFX_VADC_G_REVNP1_REV8NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_REVNP1_Bits.REV8NP */
+#define IFX_VADC_G_REVNP1_REV8NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_REVNP1_Bits.REV8NP */
+#define IFX_VADC_G_REVNP1_REV8NP_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_REVNP1_Bits.REV9NP */
+#define IFX_VADC_G_REVNP1_REV9NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_REVNP1_Bits.REV9NP */
+#define IFX_VADC_G_REVNP1_REV9NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_REVNP1_Bits.REV9NP */
+#define IFX_VADC_G_REVNP1_REV9NP_OFF (4u)
+
+/** \brief Length for Ifx_VADC_G_RRASS_Bits.ASSRR0 */
+#define IFX_VADC_G_RRASS_ASSRR0_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_RRASS_Bits.ASSRR0 */
+#define IFX_VADC_G_RRASS_ASSRR0_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_RRASS_Bits.ASSRR0 */
+#define IFX_VADC_G_RRASS_ASSRR0_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_RRASS_Bits.ASSRR10 */
+#define IFX_VADC_G_RRASS_ASSRR10_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_RRASS_Bits.ASSRR10 */
+#define IFX_VADC_G_RRASS_ASSRR10_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_RRASS_Bits.ASSRR10 */
+#define IFX_VADC_G_RRASS_ASSRR10_OFF (10u)
+
+/** \brief Length for Ifx_VADC_G_RRASS_Bits.ASSRR11 */
+#define IFX_VADC_G_RRASS_ASSRR11_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_RRASS_Bits.ASSRR11 */
+#define IFX_VADC_G_RRASS_ASSRR11_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_RRASS_Bits.ASSRR11 */
+#define IFX_VADC_G_RRASS_ASSRR11_OFF (11u)
+
+/** \brief Length for Ifx_VADC_G_RRASS_Bits.ASSRR12 */
+#define IFX_VADC_G_RRASS_ASSRR12_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_RRASS_Bits.ASSRR12 */
+#define IFX_VADC_G_RRASS_ASSRR12_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_RRASS_Bits.ASSRR12 */
+#define IFX_VADC_G_RRASS_ASSRR12_OFF (12u)
+
+/** \brief Length for Ifx_VADC_G_RRASS_Bits.ASSRR13 */
+#define IFX_VADC_G_RRASS_ASSRR13_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_RRASS_Bits.ASSRR13 */
+#define IFX_VADC_G_RRASS_ASSRR13_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_RRASS_Bits.ASSRR13 */
+#define IFX_VADC_G_RRASS_ASSRR13_OFF (13u)
+
+/** \brief Length for Ifx_VADC_G_RRASS_Bits.ASSRR14 */
+#define IFX_VADC_G_RRASS_ASSRR14_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_RRASS_Bits.ASSRR14 */
+#define IFX_VADC_G_RRASS_ASSRR14_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_RRASS_Bits.ASSRR14 */
+#define IFX_VADC_G_RRASS_ASSRR14_OFF (14u)
+
+/** \brief Length for Ifx_VADC_G_RRASS_Bits.ASSRR15 */
+#define IFX_VADC_G_RRASS_ASSRR15_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_RRASS_Bits.ASSRR15 */
+#define IFX_VADC_G_RRASS_ASSRR15_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_RRASS_Bits.ASSRR15 */
+#define IFX_VADC_G_RRASS_ASSRR15_OFF (15u)
+
+/** \brief Length for Ifx_VADC_G_RRASS_Bits.ASSRR1 */
+#define IFX_VADC_G_RRASS_ASSRR1_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_RRASS_Bits.ASSRR1 */
+#define IFX_VADC_G_RRASS_ASSRR1_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_RRASS_Bits.ASSRR1 */
+#define IFX_VADC_G_RRASS_ASSRR1_OFF (1u)
+
+/** \brief Length for Ifx_VADC_G_RRASS_Bits.ASSRR2 */
+#define IFX_VADC_G_RRASS_ASSRR2_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_RRASS_Bits.ASSRR2 */
+#define IFX_VADC_G_RRASS_ASSRR2_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_RRASS_Bits.ASSRR2 */
+#define IFX_VADC_G_RRASS_ASSRR2_OFF (2u)
+
+/** \brief Length for Ifx_VADC_G_RRASS_Bits.ASSRR3 */
+#define IFX_VADC_G_RRASS_ASSRR3_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_RRASS_Bits.ASSRR3 */
+#define IFX_VADC_G_RRASS_ASSRR3_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_RRASS_Bits.ASSRR3 */
+#define IFX_VADC_G_RRASS_ASSRR3_OFF (3u)
+
+/** \brief Length for Ifx_VADC_G_RRASS_Bits.ASSRR4 */
+#define IFX_VADC_G_RRASS_ASSRR4_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_RRASS_Bits.ASSRR4 */
+#define IFX_VADC_G_RRASS_ASSRR4_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_RRASS_Bits.ASSRR4 */
+#define IFX_VADC_G_RRASS_ASSRR4_OFF (4u)
+
+/** \brief Length for Ifx_VADC_G_RRASS_Bits.ASSRR5 */
+#define IFX_VADC_G_RRASS_ASSRR5_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_RRASS_Bits.ASSRR5 */
+#define IFX_VADC_G_RRASS_ASSRR5_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_RRASS_Bits.ASSRR5 */
+#define IFX_VADC_G_RRASS_ASSRR5_OFF (5u)
+
+/** \brief Length for Ifx_VADC_G_RRASS_Bits.ASSRR6 */
+#define IFX_VADC_G_RRASS_ASSRR6_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_RRASS_Bits.ASSRR6 */
+#define IFX_VADC_G_RRASS_ASSRR6_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_RRASS_Bits.ASSRR6 */
+#define IFX_VADC_G_RRASS_ASSRR6_OFF (6u)
+
+/** \brief Length for Ifx_VADC_G_RRASS_Bits.ASSRR7 */
+#define IFX_VADC_G_RRASS_ASSRR7_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_RRASS_Bits.ASSRR7 */
+#define IFX_VADC_G_RRASS_ASSRR7_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_RRASS_Bits.ASSRR7 */
+#define IFX_VADC_G_RRASS_ASSRR7_OFF (7u)
+
+/** \brief Length for Ifx_VADC_G_RRASS_Bits.ASSRR8 */
+#define IFX_VADC_G_RRASS_ASSRR8_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_RRASS_Bits.ASSRR8 */
+#define IFX_VADC_G_RRASS_ASSRR8_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_RRASS_Bits.ASSRR8 */
+#define IFX_VADC_G_RRASS_ASSRR8_OFF (8u)
+
+/** \brief Length for Ifx_VADC_G_RRASS_Bits.ASSRR9 */
+#define IFX_VADC_G_RRASS_ASSRR9_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_RRASS_Bits.ASSRR9 */
+#define IFX_VADC_G_RRASS_ASSRR9_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_RRASS_Bits.ASSRR9 */
+#define IFX_VADC_G_RRASS_ASSRR9_OFF (9u)
+
+/** \brief Length for Ifx_VADC_G_SEFCLR_Bits.SEV0 */
+#define IFX_VADC_G_SEFCLR_SEV0_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_SEFCLR_Bits.SEV0 */
+#define IFX_VADC_G_SEFCLR_SEV0_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_SEFCLR_Bits.SEV0 */
+#define IFX_VADC_G_SEFCLR_SEV0_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_SEFCLR_Bits.SEV1 */
+#define IFX_VADC_G_SEFCLR_SEV1_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_SEFCLR_Bits.SEV1 */
+#define IFX_VADC_G_SEFCLR_SEV1_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_SEFCLR_Bits.SEV1 */
+#define IFX_VADC_G_SEFCLR_SEV1_OFF (1u)
+
+/** \brief Length for Ifx_VADC_G_SEFLAG_Bits.SEV0 */
+#define IFX_VADC_G_SEFLAG_SEV0_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_SEFLAG_Bits.SEV0 */
+#define IFX_VADC_G_SEFLAG_SEV0_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_SEFLAG_Bits.SEV0 */
+#define IFX_VADC_G_SEFLAG_SEV0_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_SEFLAG_Bits.SEV1 */
+#define IFX_VADC_G_SEFLAG_SEV1_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_SEFLAG_Bits.SEV1 */
+#define IFX_VADC_G_SEFLAG_SEV1_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_SEFLAG_Bits.SEV1 */
+#define IFX_VADC_G_SEFLAG_SEV1_OFF (1u)
+
+/** \brief Length for Ifx_VADC_G_SEVNP_Bits.SEV0NP */
+#define IFX_VADC_G_SEVNP_SEV0NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_SEVNP_Bits.SEV0NP */
+#define IFX_VADC_G_SEVNP_SEV0NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_SEVNP_Bits.SEV0NP */
+#define IFX_VADC_G_SEVNP_SEV0NP_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_SEVNP_Bits.SEV1NP */
+#define IFX_VADC_G_SEVNP_SEV1NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_G_SEVNP_Bits.SEV1NP */
+#define IFX_VADC_G_SEVNP_SEV1NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_G_SEVNP_Bits.SEV1NP */
+#define IFX_VADC_G_SEVNP_SEV1NP_OFF (4u)
+
+/** \brief Length for Ifx_VADC_G_SRACT_Bits.AGSR0 */
+#define IFX_VADC_G_SRACT_AGSR0_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_SRACT_Bits.AGSR0 */
+#define IFX_VADC_G_SRACT_AGSR0_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_SRACT_Bits.AGSR0 */
+#define IFX_VADC_G_SRACT_AGSR0_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_SRACT_Bits.AGSR1 */
+#define IFX_VADC_G_SRACT_AGSR1_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_SRACT_Bits.AGSR1 */
+#define IFX_VADC_G_SRACT_AGSR1_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_SRACT_Bits.AGSR1 */
+#define IFX_VADC_G_SRACT_AGSR1_OFF (1u)
+
+/** \brief Length for Ifx_VADC_G_SRACT_Bits.AGSR2 */
+#define IFX_VADC_G_SRACT_AGSR2_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_SRACT_Bits.AGSR2 */
+#define IFX_VADC_G_SRACT_AGSR2_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_SRACT_Bits.AGSR2 */
+#define IFX_VADC_G_SRACT_AGSR2_OFF (2u)
+
+/** \brief Length for Ifx_VADC_G_SRACT_Bits.AGSR3 */
+#define IFX_VADC_G_SRACT_AGSR3_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_SRACT_Bits.AGSR3 */
+#define IFX_VADC_G_SRACT_AGSR3_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_SRACT_Bits.AGSR3 */
+#define IFX_VADC_G_SRACT_AGSR3_OFF (3u)
+
+/** \brief Length for Ifx_VADC_G_SRACT_Bits.ASSR0 */
+#define IFX_VADC_G_SRACT_ASSR0_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_SRACT_Bits.ASSR0 */
+#define IFX_VADC_G_SRACT_ASSR0_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_SRACT_Bits.ASSR0 */
+#define IFX_VADC_G_SRACT_ASSR0_OFF (8u)
+
+/** \brief Length for Ifx_VADC_G_SRACT_Bits.ASSR1 */
+#define IFX_VADC_G_SRACT_ASSR1_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_SRACT_Bits.ASSR1 */
+#define IFX_VADC_G_SRACT_ASSR1_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_SRACT_Bits.ASSR1 */
+#define IFX_VADC_G_SRACT_ASSR1_OFF (9u)
+
+/** \brief Length for Ifx_VADC_G_SRACT_Bits.ASSR2 */
+#define IFX_VADC_G_SRACT_ASSR2_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_SRACT_Bits.ASSR2 */
+#define IFX_VADC_G_SRACT_ASSR2_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_SRACT_Bits.ASSR2 */
+#define IFX_VADC_G_SRACT_ASSR2_OFF (10u)
+
+/** \brief Length for Ifx_VADC_G_SRACT_Bits.ASSR3 */
+#define IFX_VADC_G_SRACT_ASSR3_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_SRACT_Bits.ASSR3 */
+#define IFX_VADC_G_SRACT_ASSR3_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_SRACT_Bits.ASSR3 */
+#define IFX_VADC_G_SRACT_ASSR3_OFF (11u)
+
+/** \brief Length for Ifx_VADC_G_SYNCTR_Bits.EVALR1 */
+#define IFX_VADC_G_SYNCTR_EVALR1_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_SYNCTR_Bits.EVALR1 */
+#define IFX_VADC_G_SYNCTR_EVALR1_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_SYNCTR_Bits.EVALR1 */
+#define IFX_VADC_G_SYNCTR_EVALR1_OFF (4u)
+
+/** \brief Length for Ifx_VADC_G_SYNCTR_Bits.EVALR2 */
+#define IFX_VADC_G_SYNCTR_EVALR2_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_SYNCTR_Bits.EVALR2 */
+#define IFX_VADC_G_SYNCTR_EVALR2_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_SYNCTR_Bits.EVALR2 */
+#define IFX_VADC_G_SYNCTR_EVALR2_OFF (5u)
+
+/** \brief Length for Ifx_VADC_G_SYNCTR_Bits.EVALR3 */
+#define IFX_VADC_G_SYNCTR_EVALR3_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_SYNCTR_Bits.EVALR3 */
+#define IFX_VADC_G_SYNCTR_EVALR3_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_SYNCTR_Bits.EVALR3 */
+#define IFX_VADC_G_SYNCTR_EVALR3_OFF (6u)
+
+/** \brief Length for Ifx_VADC_G_SYNCTR_Bits.STSEL */
+#define IFX_VADC_G_SYNCTR_STSEL_LEN (2u)
+
+/** \brief Mask for Ifx_VADC_G_SYNCTR_Bits.STSEL */
+#define IFX_VADC_G_SYNCTR_STSEL_MSK (0x3u)
+
+/** \brief Offset for Ifx_VADC_G_SYNCTR_Bits.STSEL */
+#define IFX_VADC_G_SYNCTR_STSEL_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_VFR_Bits.VF0 */
+#define IFX_VADC_G_VFR_VF0_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_VFR_Bits.VF0 */
+#define IFX_VADC_G_VFR_VF0_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_VFR_Bits.VF0 */
+#define IFX_VADC_G_VFR_VF0_OFF (0u)
+
+/** \brief Length for Ifx_VADC_G_VFR_Bits.VF10 */
+#define IFX_VADC_G_VFR_VF10_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_VFR_Bits.VF10 */
+#define IFX_VADC_G_VFR_VF10_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_VFR_Bits.VF10 */
+#define IFX_VADC_G_VFR_VF10_OFF (10u)
+
+/** \brief Length for Ifx_VADC_G_VFR_Bits.VF11 */
+#define IFX_VADC_G_VFR_VF11_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_VFR_Bits.VF11 */
+#define IFX_VADC_G_VFR_VF11_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_VFR_Bits.VF11 */
+#define IFX_VADC_G_VFR_VF11_OFF (11u)
+
+/** \brief Length for Ifx_VADC_G_VFR_Bits.VF12 */
+#define IFX_VADC_G_VFR_VF12_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_VFR_Bits.VF12 */
+#define IFX_VADC_G_VFR_VF12_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_VFR_Bits.VF12 */
+#define IFX_VADC_G_VFR_VF12_OFF (12u)
+
+/** \brief Length for Ifx_VADC_G_VFR_Bits.VF13 */
+#define IFX_VADC_G_VFR_VF13_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_VFR_Bits.VF13 */
+#define IFX_VADC_G_VFR_VF13_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_VFR_Bits.VF13 */
+#define IFX_VADC_G_VFR_VF13_OFF (13u)
+
+/** \brief Length for Ifx_VADC_G_VFR_Bits.VF14 */
+#define IFX_VADC_G_VFR_VF14_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_VFR_Bits.VF14 */
+#define IFX_VADC_G_VFR_VF14_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_VFR_Bits.VF14 */
+#define IFX_VADC_G_VFR_VF14_OFF (14u)
+
+/** \brief Length for Ifx_VADC_G_VFR_Bits.VF15 */
+#define IFX_VADC_G_VFR_VF15_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_VFR_Bits.VF15 */
+#define IFX_VADC_G_VFR_VF15_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_VFR_Bits.VF15 */
+#define IFX_VADC_G_VFR_VF15_OFF (15u)
+
+/** \brief Length for Ifx_VADC_G_VFR_Bits.VF1 */
+#define IFX_VADC_G_VFR_VF1_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_VFR_Bits.VF1 */
+#define IFX_VADC_G_VFR_VF1_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_VFR_Bits.VF1 */
+#define IFX_VADC_G_VFR_VF1_OFF (1u)
+
+/** \brief Length for Ifx_VADC_G_VFR_Bits.VF2 */
+#define IFX_VADC_G_VFR_VF2_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_VFR_Bits.VF2 */
+#define IFX_VADC_G_VFR_VF2_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_VFR_Bits.VF2 */
+#define IFX_VADC_G_VFR_VF2_OFF (2u)
+
+/** \brief Length for Ifx_VADC_G_VFR_Bits.VF3 */
+#define IFX_VADC_G_VFR_VF3_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_VFR_Bits.VF3 */
+#define IFX_VADC_G_VFR_VF3_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_VFR_Bits.VF3 */
+#define IFX_VADC_G_VFR_VF3_OFF (3u)
+
+/** \brief Length for Ifx_VADC_G_VFR_Bits.VF4 */
+#define IFX_VADC_G_VFR_VF4_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_VFR_Bits.VF4 */
+#define IFX_VADC_G_VFR_VF4_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_VFR_Bits.VF4 */
+#define IFX_VADC_G_VFR_VF4_OFF (4u)
+
+/** \brief Length for Ifx_VADC_G_VFR_Bits.VF5 */
+#define IFX_VADC_G_VFR_VF5_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_VFR_Bits.VF5 */
+#define IFX_VADC_G_VFR_VF5_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_VFR_Bits.VF5 */
+#define IFX_VADC_G_VFR_VF5_OFF (5u)
+
+/** \brief Length for Ifx_VADC_G_VFR_Bits.VF6 */
+#define IFX_VADC_G_VFR_VF6_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_VFR_Bits.VF6 */
+#define IFX_VADC_G_VFR_VF6_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_VFR_Bits.VF6 */
+#define IFX_VADC_G_VFR_VF6_OFF (6u)
+
+/** \brief Length for Ifx_VADC_G_VFR_Bits.VF7 */
+#define IFX_VADC_G_VFR_VF7_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_VFR_Bits.VF7 */
+#define IFX_VADC_G_VFR_VF7_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_VFR_Bits.VF7 */
+#define IFX_VADC_G_VFR_VF7_OFF (7u)
+
+/** \brief Length for Ifx_VADC_G_VFR_Bits.VF8 */
+#define IFX_VADC_G_VFR_VF8_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_VFR_Bits.VF8 */
+#define IFX_VADC_G_VFR_VF8_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_VFR_Bits.VF8 */
+#define IFX_VADC_G_VFR_VF8_OFF (8u)
+
+/** \brief Length for Ifx_VADC_G_VFR_Bits.VF9 */
+#define IFX_VADC_G_VFR_VF9_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_G_VFR_Bits.VF9 */
+#define IFX_VADC_G_VFR_VF9_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_G_VFR_Bits.VF9 */
+#define IFX_VADC_G_VFR_VF9_OFF (9u)
+
+/** \brief Length for Ifx_VADC_GLOBBOUND_Bits.BOUNDARY0 */
+#define IFX_VADC_GLOBBOUND_BOUNDARY0_LEN (12u)
+
+/** \brief Mask for Ifx_VADC_GLOBBOUND_Bits.BOUNDARY0 */
+#define IFX_VADC_GLOBBOUND_BOUNDARY0_MSK (0xfffu)
+
+/** \brief Offset for Ifx_VADC_GLOBBOUND_Bits.BOUNDARY0 */
+#define IFX_VADC_GLOBBOUND_BOUNDARY0_OFF (0u)
+
+/** \brief Length for Ifx_VADC_GLOBBOUND_Bits.BOUNDARY1 */
+#define IFX_VADC_GLOBBOUND_BOUNDARY1_LEN (12u)
+
+/** \brief Mask for Ifx_VADC_GLOBBOUND_Bits.BOUNDARY1 */
+#define IFX_VADC_GLOBBOUND_BOUNDARY1_MSK (0xfffu)
+
+/** \brief Offset for Ifx_VADC_GLOBBOUND_Bits.BOUNDARY1 */
+#define IFX_VADC_GLOBBOUND_BOUNDARY1_OFF (16u)
+
+/** \brief Length for Ifx_VADC_GLOBCFG_Bits.DCMSB */
+#define IFX_VADC_GLOBCFG_DCMSB_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_GLOBCFG_Bits.DCMSB */
+#define IFX_VADC_GLOBCFG_DCMSB_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_GLOBCFG_Bits.DCMSB */
+#define IFX_VADC_GLOBCFG_DCMSB_OFF (7u)
+
+/** \brief Length for Ifx_VADC_GLOBCFG_Bits.DIVA */
+#define IFX_VADC_GLOBCFG_DIVA_LEN (5u)
+
+/** \brief Mask for Ifx_VADC_GLOBCFG_Bits.DIVA */
+#define IFX_VADC_GLOBCFG_DIVA_MSK (0x1fu)
+
+/** \brief Offset for Ifx_VADC_GLOBCFG_Bits.DIVA */
+#define IFX_VADC_GLOBCFG_DIVA_OFF (0u)
+
+/** \brief Length for Ifx_VADC_GLOBCFG_Bits.DIVD */
+#define IFX_VADC_GLOBCFG_DIVD_LEN (2u)
+
+/** \brief Mask for Ifx_VADC_GLOBCFG_Bits.DIVD */
+#define IFX_VADC_GLOBCFG_DIVD_MSK (0x3u)
+
+/** \brief Offset for Ifx_VADC_GLOBCFG_Bits.DIVD */
+#define IFX_VADC_GLOBCFG_DIVD_OFF (8u)
+
+/** \brief Length for Ifx_VADC_GLOBCFG_Bits.DIVWC */
+#define IFX_VADC_GLOBCFG_DIVWC_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_GLOBCFG_Bits.DIVWC */
+#define IFX_VADC_GLOBCFG_DIVWC_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_GLOBCFG_Bits.DIVWC */
+#define IFX_VADC_GLOBCFG_DIVWC_OFF (15u)
+
+/** \brief Length for Ifx_VADC_GLOBCFG_Bits.DPCAL0 */
+#define IFX_VADC_GLOBCFG_DPCAL0_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_GLOBCFG_Bits.DPCAL0 */
+#define IFX_VADC_GLOBCFG_DPCAL0_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_GLOBCFG_Bits.DPCAL0 */
+#define IFX_VADC_GLOBCFG_DPCAL0_OFF (16u)
+
+/** \brief Length for Ifx_VADC_GLOBCFG_Bits.DPCAL1 */
+#define IFX_VADC_GLOBCFG_DPCAL1_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_GLOBCFG_Bits.DPCAL1 */
+#define IFX_VADC_GLOBCFG_DPCAL1_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_GLOBCFG_Bits.DPCAL1 */
+#define IFX_VADC_GLOBCFG_DPCAL1_OFF (17u)
+
+/** \brief Length for Ifx_VADC_GLOBCFG_Bits.DPCAL2 */
+#define IFX_VADC_GLOBCFG_DPCAL2_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_GLOBCFG_Bits.DPCAL2 */
+#define IFX_VADC_GLOBCFG_DPCAL2_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_GLOBCFG_Bits.DPCAL2 */
+#define IFX_VADC_GLOBCFG_DPCAL2_OFF (18u)
+
+/** \brief Length for Ifx_VADC_GLOBCFG_Bits.DPCAL3 */
+#define IFX_VADC_GLOBCFG_DPCAL3_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_GLOBCFG_Bits.DPCAL3 */
+#define IFX_VADC_GLOBCFG_DPCAL3_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_GLOBCFG_Bits.DPCAL3 */
+#define IFX_VADC_GLOBCFG_DPCAL3_OFF (19u)
+
+/** \brief Length for Ifx_VADC_GLOBCFG_Bits.LOSUP */
+#define IFX_VADC_GLOBCFG_LOSUP_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_GLOBCFG_Bits.LOSUP */
+#define IFX_VADC_GLOBCFG_LOSUP_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_GLOBCFG_Bits.LOSUP */
+#define IFX_VADC_GLOBCFG_LOSUP_OFF (14u)
+
+/** \brief Length for Ifx_VADC_GLOBCFG_Bits.REFPC */
+#define IFX_VADC_GLOBCFG_REFPC_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_GLOBCFG_Bits.REFPC */
+#define IFX_VADC_GLOBCFG_REFPC_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_GLOBCFG_Bits.REFPC */
+#define IFX_VADC_GLOBCFG_REFPC_OFF (12u)
+
+/** \brief Length for Ifx_VADC_GLOBCFG_Bits.SUCAL */
+#define IFX_VADC_GLOBCFG_SUCAL_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_GLOBCFG_Bits.SUCAL */
+#define IFX_VADC_GLOBCFG_SUCAL_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_GLOBCFG_Bits.SUCAL */
+#define IFX_VADC_GLOBCFG_SUCAL_OFF (31u)
+
+/** \brief Length for Ifx_VADC_GLOBEFLAG_Bits.REVGLB */
+#define IFX_VADC_GLOBEFLAG_REVGLB_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_GLOBEFLAG_Bits.REVGLB */
+#define IFX_VADC_GLOBEFLAG_REVGLB_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_GLOBEFLAG_Bits.REVGLB */
+#define IFX_VADC_GLOBEFLAG_REVGLB_OFF (8u)
+
+/** \brief Length for Ifx_VADC_GLOBEFLAG_Bits.REVGLBCLR */
+#define IFX_VADC_GLOBEFLAG_REVGLBCLR_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_GLOBEFLAG_Bits.REVGLBCLR */
+#define IFX_VADC_GLOBEFLAG_REVGLBCLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_GLOBEFLAG_Bits.REVGLBCLR */
+#define IFX_VADC_GLOBEFLAG_REVGLBCLR_OFF (24u)
+
+/** \brief Length for Ifx_VADC_GLOBEFLAG_Bits.SEVGLB */
+#define IFX_VADC_GLOBEFLAG_SEVGLB_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_GLOBEFLAG_Bits.SEVGLB */
+#define IFX_VADC_GLOBEFLAG_SEVGLB_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_GLOBEFLAG_Bits.SEVGLB */
+#define IFX_VADC_GLOBEFLAG_SEVGLB_OFF (0u)
+
+/** \brief Length for Ifx_VADC_GLOBEFLAG_Bits.SEVGLBCLR */
+#define IFX_VADC_GLOBEFLAG_SEVGLBCLR_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_GLOBEFLAG_Bits.SEVGLBCLR */
+#define IFX_VADC_GLOBEFLAG_SEVGLBCLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_GLOBEFLAG_Bits.SEVGLBCLR */
+#define IFX_VADC_GLOBEFLAG_SEVGLBCLR_OFF (16u)
+
+/** \brief Length for Ifx_VADC_GLOBEVNP_Bits.REV0NP */
+#define IFX_VADC_GLOBEVNP_REV0NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_GLOBEVNP_Bits.REV0NP */
+#define IFX_VADC_GLOBEVNP_REV0NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_GLOBEVNP_Bits.REV0NP */
+#define IFX_VADC_GLOBEVNP_REV0NP_OFF (16u)
+
+/** \brief Length for Ifx_VADC_GLOBEVNP_Bits.SEV0NP */
+#define IFX_VADC_GLOBEVNP_SEV0NP_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_GLOBEVNP_Bits.SEV0NP */
+#define IFX_VADC_GLOBEVNP_SEV0NP_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_GLOBEVNP_Bits.SEV0NP */
+#define IFX_VADC_GLOBEVNP_SEV0NP_OFF (0u)
+
+/** \brief Length for Ifx_VADC_GLOBRCR_Bits.DRCTR */
+#define IFX_VADC_GLOBRCR_DRCTR_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_GLOBRCR_Bits.DRCTR */
+#define IFX_VADC_GLOBRCR_DRCTR_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_GLOBRCR_Bits.DRCTR */
+#define IFX_VADC_GLOBRCR_DRCTR_OFF (16u)
+
+/** \brief Length for Ifx_VADC_GLOBRCR_Bits.SRGEN */
+#define IFX_VADC_GLOBRCR_SRGEN_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_GLOBRCR_Bits.SRGEN */
+#define IFX_VADC_GLOBRCR_SRGEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_GLOBRCR_Bits.SRGEN */
+#define IFX_VADC_GLOBRCR_SRGEN_OFF (31u)
+
+/** \brief Length for Ifx_VADC_GLOBRCR_Bits.WFR */
+#define IFX_VADC_GLOBRCR_WFR_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_GLOBRCR_Bits.WFR */
+#define IFX_VADC_GLOBRCR_WFR_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_GLOBRCR_Bits.WFR */
+#define IFX_VADC_GLOBRCR_WFR_OFF (24u)
+
+/** \brief Length for Ifx_VADC_GLOBRES_Bits.CHNR */
+#define IFX_VADC_GLOBRES_CHNR_LEN (5u)
+
+/** \brief Mask for Ifx_VADC_GLOBRES_Bits.CHNR */
+#define IFX_VADC_GLOBRES_CHNR_MSK (0x1fu)
+
+/** \brief Offset for Ifx_VADC_GLOBRES_Bits.CHNR */
+#define IFX_VADC_GLOBRES_CHNR_OFF (20u)
+
+/** \brief Length for Ifx_VADC_GLOBRES_Bits.CRS */
+#define IFX_VADC_GLOBRES_CRS_LEN (2u)
+
+/** \brief Mask for Ifx_VADC_GLOBRES_Bits.CRS */
+#define IFX_VADC_GLOBRES_CRS_MSK (0x3u)
+
+/** \brief Offset for Ifx_VADC_GLOBRES_Bits.CRS */
+#define IFX_VADC_GLOBRES_CRS_OFF (28u)
+
+/** \brief Length for Ifx_VADC_GLOBRES_Bits.EMUX */
+#define IFX_VADC_GLOBRES_EMUX_LEN (3u)
+
+/** \brief Mask for Ifx_VADC_GLOBRES_Bits.EMUX */
+#define IFX_VADC_GLOBRES_EMUX_MSK (0x7u)
+
+/** \brief Offset for Ifx_VADC_GLOBRES_Bits.EMUX */
+#define IFX_VADC_GLOBRES_EMUX_OFF (25u)
+
+/** \brief Length for Ifx_VADC_GLOBRES_Bits.FCR */
+#define IFX_VADC_GLOBRES_FCR_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_GLOBRES_Bits.FCR */
+#define IFX_VADC_GLOBRES_FCR_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_GLOBRES_Bits.FCR */
+#define IFX_VADC_GLOBRES_FCR_OFF (30u)
+
+/** \brief Length for Ifx_VADC_GLOBRES_Bits.GNR */
+#define IFX_VADC_GLOBRES_GNR_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_GLOBRES_Bits.GNR */
+#define IFX_VADC_GLOBRES_GNR_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_GLOBRES_Bits.GNR */
+#define IFX_VADC_GLOBRES_GNR_OFF (16u)
+
+/** \brief Length for Ifx_VADC_GLOBRES_Bits.RESULT */
+#define IFX_VADC_GLOBRES_RESULT_LEN (16u)
+
+/** \brief Mask for Ifx_VADC_GLOBRES_Bits.RESULT */
+#define IFX_VADC_GLOBRES_RESULT_MSK (0xffffu)
+
+/** \brief Offset for Ifx_VADC_GLOBRES_Bits.RESULT */
+#define IFX_VADC_GLOBRES_RESULT_OFF (0u)
+
+/** \brief Length for Ifx_VADC_GLOBRES_Bits.VF */
+#define IFX_VADC_GLOBRES_VF_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_GLOBRES_Bits.VF */
+#define IFX_VADC_GLOBRES_VF_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_GLOBRES_Bits.VF */
+#define IFX_VADC_GLOBRES_VF_OFF (31u)
+
+/** \brief Length for Ifx_VADC_GLOBRESD_Bits.CHNR */
+#define IFX_VADC_GLOBRESD_CHNR_LEN (5u)
+
+/** \brief Mask for Ifx_VADC_GLOBRESD_Bits.CHNR */
+#define IFX_VADC_GLOBRESD_CHNR_MSK (0x1fu)
+
+/** \brief Offset for Ifx_VADC_GLOBRESD_Bits.CHNR */
+#define IFX_VADC_GLOBRESD_CHNR_OFF (20u)
+
+/** \brief Length for Ifx_VADC_GLOBRESD_Bits.CRS */
+#define IFX_VADC_GLOBRESD_CRS_LEN (2u)
+
+/** \brief Mask for Ifx_VADC_GLOBRESD_Bits.CRS */
+#define IFX_VADC_GLOBRESD_CRS_MSK (0x3u)
+
+/** \brief Offset for Ifx_VADC_GLOBRESD_Bits.CRS */
+#define IFX_VADC_GLOBRESD_CRS_OFF (28u)
+
+/** \brief Length for Ifx_VADC_GLOBRESD_Bits.EMUX */
+#define IFX_VADC_GLOBRESD_EMUX_LEN (3u)
+
+/** \brief Mask for Ifx_VADC_GLOBRESD_Bits.EMUX */
+#define IFX_VADC_GLOBRESD_EMUX_MSK (0x7u)
+
+/** \brief Offset for Ifx_VADC_GLOBRESD_Bits.EMUX */
+#define IFX_VADC_GLOBRESD_EMUX_OFF (25u)
+
+/** \brief Length for Ifx_VADC_GLOBRESD_Bits.FCR */
+#define IFX_VADC_GLOBRESD_FCR_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_GLOBRESD_Bits.FCR */
+#define IFX_VADC_GLOBRESD_FCR_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_GLOBRESD_Bits.FCR */
+#define IFX_VADC_GLOBRESD_FCR_OFF (30u)
+
+/** \brief Length for Ifx_VADC_GLOBRESD_Bits.GNR */
+#define IFX_VADC_GLOBRESD_GNR_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_GLOBRESD_Bits.GNR */
+#define IFX_VADC_GLOBRESD_GNR_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_GLOBRESD_Bits.GNR */
+#define IFX_VADC_GLOBRESD_GNR_OFF (16u)
+
+/** \brief Length for Ifx_VADC_GLOBRESD_Bits.RESULT */
+#define IFX_VADC_GLOBRESD_RESULT_LEN (16u)
+
+/** \brief Mask for Ifx_VADC_GLOBRESD_Bits.RESULT */
+#define IFX_VADC_GLOBRESD_RESULT_MSK (0xffffu)
+
+/** \brief Offset for Ifx_VADC_GLOBRESD_Bits.RESULT */
+#define IFX_VADC_GLOBRESD_RESULT_OFF (0u)
+
+/** \brief Length for Ifx_VADC_GLOBRESD_Bits.VF */
+#define IFX_VADC_GLOBRESD_VF_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_GLOBRESD_Bits.VF */
+#define IFX_VADC_GLOBRESD_VF_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_GLOBRESD_Bits.VF */
+#define IFX_VADC_GLOBRESD_VF_OFF (31u)
+
+/** \brief Length for Ifx_VADC_GLOBTF_Bits.CDCH */
+#define IFX_VADC_GLOBTF_CDCH_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_GLOBTF_Bits.CDCH */
+#define IFX_VADC_GLOBTF_CDCH_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_GLOBTF_Bits.CDCH */
+#define IFX_VADC_GLOBTF_CDCH_OFF (0u)
+
+/** \brief Length for Ifx_VADC_GLOBTF_Bits.CDEN */
+#define IFX_VADC_GLOBTF_CDEN_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_GLOBTF_Bits.CDEN */
+#define IFX_VADC_GLOBTF_CDEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_GLOBTF_Bits.CDEN */
+#define IFX_VADC_GLOBTF_CDEN_OFF (8u)
+
+/** \brief Length for Ifx_VADC_GLOBTF_Bits.CDGR */
+#define IFX_VADC_GLOBTF_CDGR_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_GLOBTF_Bits.CDGR */
+#define IFX_VADC_GLOBTF_CDGR_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_GLOBTF_Bits.CDGR */
+#define IFX_VADC_GLOBTF_CDGR_OFF (4u)
+
+/** \brief Length for Ifx_VADC_GLOBTF_Bits.CDSEL */
+#define IFX_VADC_GLOBTF_CDSEL_LEN (2u)
+
+/** \brief Mask for Ifx_VADC_GLOBTF_Bits.CDSEL */
+#define IFX_VADC_GLOBTF_CDSEL_MSK (0x3u)
+
+/** \brief Offset for Ifx_VADC_GLOBTF_Bits.CDSEL */
+#define IFX_VADC_GLOBTF_CDSEL_OFF (9u)
+
+/** \brief Length for Ifx_VADC_GLOBTF_Bits.CDWC */
+#define IFX_VADC_GLOBTF_CDWC_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_GLOBTF_Bits.CDWC */
+#define IFX_VADC_GLOBTF_CDWC_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_GLOBTF_Bits.CDWC */
+#define IFX_VADC_GLOBTF_CDWC_OFF (15u)
+
+/** \brief Length for Ifx_VADC_GLOBTF_Bits.MDPD */
+#define IFX_VADC_GLOBTF_MDPD_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_GLOBTF_Bits.MDPD */
+#define IFX_VADC_GLOBTF_MDPD_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_GLOBTF_Bits.MDPD */
+#define IFX_VADC_GLOBTF_MDPD_OFF (17u)
+
+/** \brief Length for Ifx_VADC_GLOBTF_Bits.MDPU */
+#define IFX_VADC_GLOBTF_MDPU_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_GLOBTF_Bits.MDPU */
+#define IFX_VADC_GLOBTF_MDPU_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_GLOBTF_Bits.MDPU */
+#define IFX_VADC_GLOBTF_MDPU_OFF (18u)
+
+/** \brief Length for Ifx_VADC_GLOBTF_Bits.MDWC */
+#define IFX_VADC_GLOBTF_MDWC_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_GLOBTF_Bits.MDWC */
+#define IFX_VADC_GLOBTF_MDWC_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_GLOBTF_Bits.MDWC */
+#define IFX_VADC_GLOBTF_MDWC_OFF (23u)
+
+/** \brief Length for Ifx_VADC_GLOBTF_Bits.PDD */
+#define IFX_VADC_GLOBTF_PDD_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_GLOBTF_Bits.PDD */
+#define IFX_VADC_GLOBTF_PDD_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_GLOBTF_Bits.PDD */
+#define IFX_VADC_GLOBTF_PDD_OFF (16u)
+
+/** \brief Length for Ifx_VADC_ICLASS_Bits.CME */
+#define IFX_VADC_ICLASS_CME_LEN (3u)
+
+/** \brief Mask for Ifx_VADC_ICLASS_Bits.CME */
+#define IFX_VADC_ICLASS_CME_MSK (0x7u)
+
+/** \brief Offset for Ifx_VADC_ICLASS_Bits.CME */
+#define IFX_VADC_ICLASS_CME_OFF (24u)
+
+/** \brief Length for Ifx_VADC_ICLASS_Bits.CMS */
+#define IFX_VADC_ICLASS_CMS_LEN (3u)
+
+/** \brief Mask for Ifx_VADC_ICLASS_Bits.CMS */
+#define IFX_VADC_ICLASS_CMS_MSK (0x7u)
+
+/** \brief Offset for Ifx_VADC_ICLASS_Bits.CMS */
+#define IFX_VADC_ICLASS_CMS_OFF (8u)
+
+/** \brief Length for Ifx_VADC_ICLASS_Bits.STCE */
+#define IFX_VADC_ICLASS_STCE_LEN (5u)
+
+/** \brief Mask for Ifx_VADC_ICLASS_Bits.STCE */
+#define IFX_VADC_ICLASS_STCE_MSK (0x1fu)
+
+/** \brief Offset for Ifx_VADC_ICLASS_Bits.STCE */
+#define IFX_VADC_ICLASS_STCE_OFF (16u)
+
+/** \brief Length for Ifx_VADC_ICLASS_Bits.STCS */
+#define IFX_VADC_ICLASS_STCS_LEN (5u)
+
+/** \brief Mask for Ifx_VADC_ICLASS_Bits.STCS */
+#define IFX_VADC_ICLASS_STCS_MSK (0x1fu)
+
+/** \brief Offset for Ifx_VADC_ICLASS_Bits.STCS */
+#define IFX_VADC_ICLASS_STCS_OFF (0u)
+
+/** \brief Length for Ifx_VADC_ID_Bits.MODNUMBER */
+#define IFX_VADC_ID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_VADC_ID_Bits.MODNUMBER */
+#define IFX_VADC_ID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_VADC_ID_Bits.MODNUMBER */
+#define IFX_VADC_ID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_VADC_ID_Bits.MODREV */
+#define IFX_VADC_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_VADC_ID_Bits.MODREV */
+#define IFX_VADC_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_VADC_ID_Bits.MODREV */
+#define IFX_VADC_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_VADC_ID_Bits.MODTYPE */
+#define IFX_VADC_ID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_VADC_ID_Bits.MODTYPE */
+#define IFX_VADC_ID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_VADC_ID_Bits.MODTYPE */
+#define IFX_VADC_ID_MODTYPE_OFF (8u)
+
+/** \brief Length for Ifx_VADC_KRST0_Bits.RST */
+#define IFX_VADC_KRST0_RST_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_KRST0_Bits.RST */
+#define IFX_VADC_KRST0_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_KRST0_Bits.RST */
+#define IFX_VADC_KRST0_RST_OFF (0u)
+
+/** \brief Length for Ifx_VADC_KRST0_Bits.RSTSTAT */
+#define IFX_VADC_KRST0_RSTSTAT_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_KRST0_Bits.RSTSTAT */
+#define IFX_VADC_KRST0_RSTSTAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_KRST0_Bits.RSTSTAT */
+#define IFX_VADC_KRST0_RSTSTAT_OFF (1u)
+
+/** \brief Length for Ifx_VADC_KRST1_Bits.RST */
+#define IFX_VADC_KRST1_RST_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_KRST1_Bits.RST */
+#define IFX_VADC_KRST1_RST_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_KRST1_Bits.RST */
+#define IFX_VADC_KRST1_RST_OFF (0u)
+
+/** \brief Length for Ifx_VADC_KRSTCLR_Bits.CLR */
+#define IFX_VADC_KRSTCLR_CLR_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_KRSTCLR_Bits.CLR */
+#define IFX_VADC_KRSTCLR_CLR_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_KRSTCLR_Bits.CLR */
+#define IFX_VADC_KRSTCLR_CLR_OFF (0u)
+
+/** \brief Length for Ifx_VADC_OCS_Bits.SUS */
+#define IFX_VADC_OCS_SUS_LEN (4u)
+
+/** \brief Mask for Ifx_VADC_OCS_Bits.SUS */
+#define IFX_VADC_OCS_SUS_MSK (0xfu)
+
+/** \brief Offset for Ifx_VADC_OCS_Bits.SUS */
+#define IFX_VADC_OCS_SUS_OFF (24u)
+
+/** \brief Length for Ifx_VADC_OCS_Bits.SUS_P */
+#define IFX_VADC_OCS_SUS_P_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_OCS_Bits.SUS_P */
+#define IFX_VADC_OCS_SUS_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_OCS_Bits.SUS_P */
+#define IFX_VADC_OCS_SUS_P_OFF (28u)
+
+/** \brief Length for Ifx_VADC_OCS_Bits.SUSSTA */
+#define IFX_VADC_OCS_SUSSTA_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_OCS_Bits.SUSSTA */
+#define IFX_VADC_OCS_SUSSTA_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_OCS_Bits.SUSSTA */
+#define IFX_VADC_OCS_SUSSTA_OFF (29u)
+
+/** \brief Length for Ifx_VADC_OCS_Bits.TG_P */
+#define IFX_VADC_OCS_TG_P_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_OCS_Bits.TG_P */
+#define IFX_VADC_OCS_TG_P_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_OCS_Bits.TG_P */
+#define IFX_VADC_OCS_TG_P_OFF (3u)
+
+/** \brief Length for Ifx_VADC_OCS_Bits.TGB */
+#define IFX_VADC_OCS_TGB_LEN (1u)
+
+/** \brief Mask for Ifx_VADC_OCS_Bits.TGB */
+#define IFX_VADC_OCS_TGB_MSK (0x1u)
+
+/** \brief Offset for Ifx_VADC_OCS_Bits.TGB */
+#define IFX_VADC_OCS_TGB_OFF (2u)
+
+/** \brief Length for Ifx_VADC_OCS_Bits.TGS */
+#define IFX_VADC_OCS_TGS_LEN (2u)
+
+/** \brief Mask for Ifx_VADC_OCS_Bits.TGS */
+#define IFX_VADC_OCS_TGS_MSK (0x3u)
+
+/** \brief Offset for Ifx_VADC_OCS_Bits.TGS */
+#define IFX_VADC_OCS_TGS_OFF (0u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXVADC_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxVadc_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxVadc_reg.h
new file mode 100644
index 0000000..dfcc4b7
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxVadc_reg.h
@@ -0,0 +1,3341 @@
+/**
+ * \file IfxVadc_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Vadc_Cfg Vadc address
+ * \ingroup IfxLld_Vadc
+ *
+ * \defgroup IfxLld_Vadc_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Vadc_Cfg
+ *
+ * \defgroup IfxLld_Vadc_Cfg_Vadc 2-VADC
+ * \ingroup IfxLld_Vadc_Cfg
+ *
+ */
+#ifndef IFXVADC_REG_H
+#define IFXVADC_REG_H 1
+/******************************************************************************/
+#include "IfxVadc_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Vadc_Cfg_BaseAddress
+ * \{ */
+
+/** \brief VADC object */
+#define MODULE_VADC /*lint --e(923)*/ (*(Ifx_VADC*)0xF0020000u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Vadc_Cfg_Vadc
+ * \{ */
+
+/** \brief 3C, Access Enable Register 0 */
+#define VADC_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_VADC_ACCEN0*)0xF002003Cu)
+
+/** \brief 88, Access Protection Register */
+#define VADC_ACCPROT0 /*lint --e(923)*/ (*(volatile Ifx_VADC_ACCPROT0*)0xF0020088u)
+
+/** \brief 8C, Access Protection Register */
+#define VADC_ACCPROT1 /*lint --e(923)*/ (*(volatile Ifx_VADC_ACCPROT1*)0xF002008Cu)
+
+/** \brief 200, Background Request Source Control Register */
+#define VADC_BRSCTRL /*lint --e(923)*/ (*(volatile Ifx_VADC_BRSCTRL*)0xF0020200u)
+
+/** \brief 204, Background Request Source Mode Register */
+#define VADC_BRSMR /*lint --e(923)*/ (*(volatile Ifx_VADC_BRSMR*)0xF0020204u)
+
+/** \brief 1C0, Background Request Source Pending Register, Group */
+#define VADC_BRSPND0 /*lint --e(923)*/ (*(volatile Ifx_VADC_BRSPND*)0xF00201C0u)
+
+/** \brief 1C4, Background Request Source Pending Register, Group */
+#define VADC_BRSPND1 /*lint --e(923)*/ (*(volatile Ifx_VADC_BRSPND*)0xF00201C4u)
+
+/** \brief 1C8, Background Request Source Pending Register, Group */
+#define VADC_BRSPND2 /*lint --e(923)*/ (*(volatile Ifx_VADC_BRSPND*)0xF00201C8u)
+
+/** \brief 1CC, Background Request Source Pending Register, Group */
+#define VADC_BRSPND3 /*lint --e(923)*/ (*(volatile Ifx_VADC_BRSPND*)0xF00201CCu)
+
+/** \brief 180, Background Request Source Channel Select Register, Group */
+#define VADC_BRSSEL0 /*lint --e(923)*/ (*(volatile Ifx_VADC_BRSSEL*)0xF0020180u)
+
+/** \brief 184, Background Request Source Channel Select Register, Group */
+#define VADC_BRSSEL1 /*lint --e(923)*/ (*(volatile Ifx_VADC_BRSSEL*)0xF0020184u)
+
+/** \brief 188, Background Request Source Channel Select Register, Group */
+#define VADC_BRSSEL2 /*lint --e(923)*/ (*(volatile Ifx_VADC_BRSSEL*)0xF0020188u)
+
+/** \brief 18C, Background Request Source Channel Select Register, Group */
+#define VADC_BRSSEL3 /*lint --e(923)*/ (*(volatile Ifx_VADC_BRSSEL*)0xF002018Cu)
+
+/** \brief 0, Clock Control Register */
+#define VADC_CLC /*lint --e(923)*/ (*(volatile Ifx_VADC_CLC*)0xF0020000u)
+
+/** \brief 3F0, External Multiplexer Select Register */
+#define VADC_EMUXSEL /*lint --e(923)*/ (*(volatile Ifx_VADC_EMUXSEL*)0xF00203F0u)
+
+/** \brief 4B0, Alias Register, Group */
+#define VADC_G0_ALIAS /*lint --e(923)*/ (*(volatile Ifx_VADC_G_ALIAS*)0xF00204B0u)
+
+/** Alias (User Manual Name) for VADC_G0_ALIAS.
+* To use register names with standard convension, please use VADC_G0_ALIAS.
+*/
+#define VADC_G0ALIAS (VADC_G0_ALIAS)
+
+/** \brief 480, Arbitration Configuration Register, Group */
+#define VADC_G0_ARBCFG /*lint --e(923)*/ (*(volatile Ifx_VADC_G_ARBCFG*)0xF0020480u)
+
+/** Alias (User Manual Name) for VADC_G0_ARBCFG.
+* To use register names with standard convension, please use VADC_G0_ARBCFG.
+*/
+#define VADC_G0ARBCFG (VADC_G0_ARBCFG)
+
+/** \brief 484, Arbitration Priority Register, Group */
+#define VADC_G0_ARBPR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_ARBPR*)0xF0020484u)
+
+/** Alias (User Manual Name) for VADC_G0_ARBPR.
+* To use register names with standard convension, please use VADC_G0_ARBPR.
+*/
+#define VADC_G0ARBPR (VADC_G0_ARBPR)
+
+/** \brief 520, Autoscan Source Control Register, Group */
+#define VADC_G0_ASCTRL /*lint --e(923)*/ (*(volatile Ifx_VADC_G_ASCTRL*)0xF0020520u)
+
+/** Alias (User Manual Name) for VADC_G0_ASCTRL.
+* To use register names with standard convension, please use VADC_G0_ASCTRL.
+*/
+#define VADC_G0ASCTRL (VADC_G0_ASCTRL)
+
+/** \brief 524, Autoscan Source Mode Register, Group */
+#define VADC_G0_ASMR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_ASMR*)0xF0020524u)
+
+/** Alias (User Manual Name) for VADC_G0_ASMR.
+* To use register names with standard convension, please use VADC_G0_ASMR.
+*/
+#define VADC_G0ASMR (VADC_G0_ASMR)
+
+/** \brief 52C, Autoscan Source Pending Register, Group */
+#define VADC_G0_ASPND /*lint --e(923)*/ (*(volatile Ifx_VADC_G_ASPND*)0xF002052Cu)
+
+/** Alias (User Manual Name) for VADC_G0_ASPND.
+* To use register names with standard convension, please use VADC_G0_ASPND.
+*/
+#define VADC_G0ASPND (VADC_G0_ASPND)
+
+/** \brief 528, Autoscan Source Channel Select Register, Group */
+#define VADC_G0_ASSEL /*lint --e(923)*/ (*(volatile Ifx_VADC_G_ASSEL*)0xF0020528u)
+
+/** Alias (User Manual Name) for VADC_G0_ASSEL.
+* To use register names with standard convension, please use VADC_G0_ASSEL.
+*/
+#define VADC_G0ASSEL (VADC_G0_ASSEL)
+
+/** \brief 4C8, Boundary Flag Register, Group */
+#define VADC_G0_BFL /*lint --e(923)*/ (*(volatile Ifx_VADC_G_BFL*)0xF00204C8u)
+
+/** Alias (User Manual Name) for VADC_G0_BFL.
+* To use register names with standard convension, please use VADC_G0_BFL.
+*/
+#define VADC_G0BFL (VADC_G0_BFL)
+
+/** \brief 4D0, Boundary Flag Control Register, Group */
+#define VADC_G0_BFLC /*lint --e(923)*/ (*(volatile Ifx_VADC_G_BFLC*)0xF00204D0u)
+
+/** Alias (User Manual Name) for VADC_G0_BFLC.
+* To use register names with standard convension, please use VADC_G0_BFLC.
+*/
+#define VADC_G0BFLC (VADC_G0_BFLC)
+
+/** \brief 4D4, Boundary Flag Node Pointer Register, Group */
+#define VADC_G0_BFLNP /*lint --e(923)*/ (*(volatile Ifx_VADC_G_BFLNP*)0xF00204D4u)
+
+/** Alias (User Manual Name) for VADC_G0_BFLNP.
+* To use register names with standard convension, please use VADC_G0_BFLNP.
+*/
+#define VADC_G0BFLNP (VADC_G0_BFLNP)
+
+/** \brief 4CC, Boundary Flag Software Register, Group */
+#define VADC_G0_BFLS /*lint --e(923)*/ (*(volatile Ifx_VADC_G_BFLS*)0xF00204CCu)
+
+/** Alias (User Manual Name) for VADC_G0_BFLS.
+* To use register names with standard convension, please use VADC_G0_BFLS.
+*/
+#define VADC_G0BFLS (VADC_G0_BFLS)
+
+/** \brief 4B8, Boundary Select Register, Group */
+#define VADC_G0_BOUND /*lint --e(923)*/ (*(volatile Ifx_VADC_G_BOUND*)0xF00204B8u)
+
+/** Alias (User Manual Name) for VADC_G0_BOUND.
+* To use register names with standard convension, please use VADC_G0_BOUND.
+*/
+#define VADC_G0BOUND (VADC_G0_BOUND)
+
+/** \brief 590, Channel Event Flag Clear Register, Group */
+#define VADC_G0_CEFCLR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CEFCLR*)0xF0020590u)
+
+/** Alias (User Manual Name) for VADC_G0_CEFCLR.
+* To use register names with standard convension, please use VADC_G0_CEFCLR.
+*/
+#define VADC_G0CEFCLR (VADC_G0_CEFCLR)
+
+/** \brief 580, Channel Event Flag Register, Group */
+#define VADC_G0_CEFLAG /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CEFLAG*)0xF0020580u)
+
+/** Alias (User Manual Name) for VADC_G0_CEFLAG.
+* To use register names with standard convension, please use VADC_G0_CEFLAG.
+*/
+#define VADC_G0CEFLAG (VADC_G0_CEFLAG)
+
+/** \brief 5A0, Channel Event Node Pointer Register 0, Group */
+#define VADC_G0_CEVNP0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CEVNP0*)0xF00205A0u)
+
+/** Alias (User Manual Name) for VADC_G0_CEVNP0.
+* To use register names with standard convension, please use VADC_G0_CEVNP0.
+*/
+#define VADC_G0CEVNP0 (VADC_G0_CEVNP0)
+
+/** \brief 5A4, Channel Event Node Pointer Register 1, Group */
+#define VADC_G0_CEVNP1 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CEVNP1*)0xF00205A4u)
+
+/** Alias (User Manual Name) for VADC_G0_CEVNP1.
+* To use register names with standard convension, please use VADC_G0_CEVNP1.
+*/
+#define VADC_G0CEVNP1 (VADC_G0_CEVNP1)
+
+/** \brief 488, Channel Assignment Register, Group */
+#define VADC_G0_CHASS /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHASS*)0xF0020488u)
+
+/** Alias (User Manual Name) for VADC_G0_CHASS.
+* To use register names with standard convension, please use VADC_G0_CHASS.
+*/
+#define VADC_G0CHASS (VADC_G0_CHASS)
+
+/** \brief 600, Group, Channel Ctrl. Reg. */
+#define VADC_G0_CHCTR0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020600u)
+
+/** Alias (User Manual Name) for VADC_G0_CHCTR0.
+* To use register names with standard convension, please use VADC_G0_CHCTR0.
+*/
+#define VADC_G0CHCTR0 (VADC_G0_CHCTR0)
+
+/** \brief 604, Group, Channel Ctrl. Reg. */
+#define VADC_G0_CHCTR1 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020604u)
+
+/** Alias (User Manual Name) for VADC_G0_CHCTR1.
+* To use register names with standard convension, please use VADC_G0_CHCTR1.
+*/
+#define VADC_G0CHCTR1 (VADC_G0_CHCTR1)
+
+/** \brief 628, Group, Channel Ctrl. Reg. */
+#define VADC_G0_CHCTR10 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020628u)
+
+/** Alias (User Manual Name) for VADC_G0_CHCTR10.
+* To use register names with standard convension, please use VADC_G0_CHCTR10.
+*/
+#define VADC_G0CHCTR10 (VADC_G0_CHCTR10)
+
+/** \brief 62C, Group, Channel Ctrl. Reg. */
+#define VADC_G0_CHCTR11 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF002062Cu)
+
+/** Alias (User Manual Name) for VADC_G0_CHCTR11.
+* To use register names with standard convension, please use VADC_G0_CHCTR11.
+*/
+#define VADC_G0CHCTR11 (VADC_G0_CHCTR11)
+
+/** \brief 630, Group, Channel Ctrl. Reg. */
+#define VADC_G0_CHCTR12 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020630u)
+
+/** Alias (User Manual Name) for VADC_G0_CHCTR12.
+* To use register names with standard convension, please use VADC_G0_CHCTR12.
+*/
+#define VADC_G0CHCTR12 (VADC_G0_CHCTR12)
+
+/** \brief 634, Group, Channel Ctrl. Reg. */
+#define VADC_G0_CHCTR13 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020634u)
+
+/** Alias (User Manual Name) for VADC_G0_CHCTR13.
+* To use register names with standard convension, please use VADC_G0_CHCTR13.
+*/
+#define VADC_G0CHCTR13 (VADC_G0_CHCTR13)
+
+/** \brief 638, Group, Channel Ctrl. Reg. */
+#define VADC_G0_CHCTR14 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020638u)
+
+/** Alias (User Manual Name) for VADC_G0_CHCTR14.
+* To use register names with standard convension, please use VADC_G0_CHCTR14.
+*/
+#define VADC_G0CHCTR14 (VADC_G0_CHCTR14)
+
+/** \brief 63C, Group, Channel Ctrl. Reg. */
+#define VADC_G0_CHCTR15 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF002063Cu)
+
+/** Alias (User Manual Name) for VADC_G0_CHCTR15.
+* To use register names with standard convension, please use VADC_G0_CHCTR15.
+*/
+#define VADC_G0CHCTR15 (VADC_G0_CHCTR15)
+
+/** \brief 608, Group, Channel Ctrl. Reg. */
+#define VADC_G0_CHCTR2 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020608u)
+
+/** Alias (User Manual Name) for VADC_G0_CHCTR2.
+* To use register names with standard convension, please use VADC_G0_CHCTR2.
+*/
+#define VADC_G0CHCTR2 (VADC_G0_CHCTR2)
+
+/** \brief 60C, Group, Channel Ctrl. Reg. */
+#define VADC_G0_CHCTR3 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF002060Cu)
+
+/** Alias (User Manual Name) for VADC_G0_CHCTR3.
+* To use register names with standard convension, please use VADC_G0_CHCTR3.
+*/
+#define VADC_G0CHCTR3 (VADC_G0_CHCTR3)
+
+/** \brief 610, Group, Channel Ctrl. Reg. */
+#define VADC_G0_CHCTR4 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020610u)
+
+/** Alias (User Manual Name) for VADC_G0_CHCTR4.
+* To use register names with standard convension, please use VADC_G0_CHCTR4.
+*/
+#define VADC_G0CHCTR4 (VADC_G0_CHCTR4)
+
+/** \brief 614, Group, Channel Ctrl. Reg. */
+#define VADC_G0_CHCTR5 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020614u)
+
+/** Alias (User Manual Name) for VADC_G0_CHCTR5.
+* To use register names with standard convension, please use VADC_G0_CHCTR5.
+*/
+#define VADC_G0CHCTR5 (VADC_G0_CHCTR5)
+
+/** \brief 618, Group, Channel Ctrl. Reg. */
+#define VADC_G0_CHCTR6 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020618u)
+
+/** Alias (User Manual Name) for VADC_G0_CHCTR6.
+* To use register names with standard convension, please use VADC_G0_CHCTR6.
+*/
+#define VADC_G0CHCTR6 (VADC_G0_CHCTR6)
+
+/** \brief 61C, Group, Channel Ctrl. Reg. */
+#define VADC_G0_CHCTR7 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF002061Cu)
+
+/** Alias (User Manual Name) for VADC_G0_CHCTR7.
+* To use register names with standard convension, please use VADC_G0_CHCTR7.
+*/
+#define VADC_G0CHCTR7 (VADC_G0_CHCTR7)
+
+/** \brief 620, Group, Channel Ctrl. Reg. */
+#define VADC_G0_CHCTR8 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020620u)
+
+/** Alias (User Manual Name) for VADC_G0_CHCTR8.
+* To use register names with standard convension, please use VADC_G0_CHCTR8.
+*/
+#define VADC_G0CHCTR8 (VADC_G0_CHCTR8)
+
+/** \brief 624, Group, Channel Ctrl. Reg. */
+#define VADC_G0_CHCTR9 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020624u)
+
+/** Alias (User Manual Name) for VADC_G0_CHCTR9.
+* To use register names with standard convension, please use VADC_G0_CHCTR9.
+*/
+#define VADC_G0CHCTR9 (VADC_G0_CHCTR9)
+
+/** \brief 5F0, External Multiplexer Control Register, Group x */
+#define VADC_G0_EMUXCTR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_EMUXCTR*)0xF00205F0u)
+
+/** Alias (User Manual Name) for VADC_G0_EMUXCTR.
+* To use register names with standard convension, please use VADC_G0_EMUXCTR.
+*/
+#define VADC_G0EMUXCTR (VADC_G0_EMUXCTR)
+
+/** \brief 4A0, Input Class Register */
+#define VADC_G0_ICLASS0 /*lint --e(923)*/ (*(volatile Ifx_VADC_ICLASS*)0xF00204A0u)
+
+/** Alias (User Manual Name) for VADC_G0_ICLASS0.
+* To use register names with standard convension, please use VADC_G0_ICLASS0.
+*/
+#define VADC_G0ICLASS0 (VADC_G0_ICLASS0)
+
+/** \brief 4A4, Input Class Register */
+#define VADC_G0_ICLASS1 /*lint --e(923)*/ (*(volatile Ifx_VADC_ICLASS*)0xF00204A4u)
+
+/** Alias (User Manual Name) for VADC_G0_ICLASS1.
+* To use register names with standard convension, please use VADC_G0_ICLASS1.
+*/
+#define VADC_G0ICLASS1 (VADC_G0_ICLASS1)
+
+/** \brief 50C, Queue 0 Register 0, Group */
+#define VADC_G0_Q0R0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_Q0R0*)0xF002050Cu)
+
+/** Alias (User Manual Name) for VADC_G0_Q0R0.
+* To use register names with standard convension, please use VADC_G0_Q0R0.
+*/
+#define VADC_G0Q0R0 (VADC_G0_Q0R0)
+
+/** \brief 510, Queue 0 Input Register, Group */
+#define VADC_G0_QBUR0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_QBUR0*)0xF0020510u)
+
+/** Alias (User Manual Name) for VADC_G0_QBUR0.
+* To use register names with standard convension, please use VADC_G0_QBUR0.
+*/
+#define VADC_G0QBUR0 (VADC_G0_QBUR0)
+
+/** \brief 500, Queue 0 Source Control Register, Group */
+#define VADC_G0_QCTRL0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_QCTRL0*)0xF0020500u)
+
+/** Alias (User Manual Name) for VADC_G0_QCTRL0.
+* To use register names with standard convension, please use VADC_G0_QCTRL0.
+*/
+#define VADC_G0QCTRL0 (VADC_G0_QCTRL0)
+
+/** \brief 510, Queue 0 Input Register, Group */
+#define VADC_G0_QINR0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_QINR0*)0xF0020510u)
+
+/** Alias (User Manual Name) for VADC_G0_QINR0.
+* To use register names with standard convension, please use VADC_G0_QINR0.
+*/
+#define VADC_G0QINR0 (VADC_G0_QINR0)
+
+/** \brief 504, Queue 0 Mode Register, Group */
+#define VADC_G0_QMR0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_QMR0*)0xF0020504u)
+
+/** Alias (User Manual Name) for VADC_G0_QMR0.
+* To use register names with standard convension, please use VADC_G0_QMR0.
+*/
+#define VADC_G0QMR0 (VADC_G0_QMR0)
+
+/** \brief 508, Queue 0 Status Register, Group */
+#define VADC_G0_QSR0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_QSR0*)0xF0020508u)
+
+/** Alias (User Manual Name) for VADC_G0_QSR0.
+* To use register names with standard convension, please use VADC_G0_QSR0.
+*/
+#define VADC_G0QSR0 (VADC_G0_QSR0)
+
+/** \brief 680, Group Result Control Reg. */
+#define VADC_G0_RCR0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020680u)
+
+/** Alias (User Manual Name) for VADC_G0_RCR0.
+* To use register names with standard convension, please use VADC_G0_RCR0.
+*/
+#define VADC_G0RCR0 (VADC_G0_RCR0)
+
+/** \brief 684, Group Result Control Reg. */
+#define VADC_G0_RCR1 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020684u)
+
+/** Alias (User Manual Name) for VADC_G0_RCR1.
+* To use register names with standard convension, please use VADC_G0_RCR1.
+*/
+#define VADC_G0RCR1 (VADC_G0_RCR1)
+
+/** \brief 6A8, Group Result Control Reg. */
+#define VADC_G0_RCR10 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF00206A8u)
+
+/** Alias (User Manual Name) for VADC_G0_RCR10.
+* To use register names with standard convension, please use VADC_G0_RCR10.
+*/
+#define VADC_G0RCR10 (VADC_G0_RCR10)
+
+/** \brief 6AC, Group Result Control Reg. */
+#define VADC_G0_RCR11 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF00206ACu)
+
+/** Alias (User Manual Name) for VADC_G0_RCR11.
+* To use register names with standard convension, please use VADC_G0_RCR11.
+*/
+#define VADC_G0RCR11 (VADC_G0_RCR11)
+
+/** \brief 6B0, Group Result Control Reg. */
+#define VADC_G0_RCR12 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF00206B0u)
+
+/** Alias (User Manual Name) for VADC_G0_RCR12.
+* To use register names with standard convension, please use VADC_G0_RCR12.
+*/
+#define VADC_G0RCR12 (VADC_G0_RCR12)
+
+/** \brief 6B4, Group Result Control Reg. */
+#define VADC_G0_RCR13 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF00206B4u)
+
+/** Alias (User Manual Name) for VADC_G0_RCR13.
+* To use register names with standard convension, please use VADC_G0_RCR13.
+*/
+#define VADC_G0RCR13 (VADC_G0_RCR13)
+
+/** \brief 6B8, Group Result Control Reg. */
+#define VADC_G0_RCR14 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF00206B8u)
+
+/** Alias (User Manual Name) for VADC_G0_RCR14.
+* To use register names with standard convension, please use VADC_G0_RCR14.
+*/
+#define VADC_G0RCR14 (VADC_G0_RCR14)
+
+/** \brief 6BC, Group Result Control Reg. */
+#define VADC_G0_RCR15 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF00206BCu)
+
+/** Alias (User Manual Name) for VADC_G0_RCR15.
+* To use register names with standard convension, please use VADC_G0_RCR15.
+*/
+#define VADC_G0RCR15 (VADC_G0_RCR15)
+
+/** \brief 688, Group Result Control Reg. */
+#define VADC_G0_RCR2 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020688u)
+
+/** Alias (User Manual Name) for VADC_G0_RCR2.
+* To use register names with standard convension, please use VADC_G0_RCR2.
+*/
+#define VADC_G0RCR2 (VADC_G0_RCR2)
+
+/** \brief 68C, Group Result Control Reg. */
+#define VADC_G0_RCR3 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF002068Cu)
+
+/** Alias (User Manual Name) for VADC_G0_RCR3.
+* To use register names with standard convension, please use VADC_G0_RCR3.
+*/
+#define VADC_G0RCR3 (VADC_G0_RCR3)
+
+/** \brief 690, Group Result Control Reg. */
+#define VADC_G0_RCR4 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020690u)
+
+/** Alias (User Manual Name) for VADC_G0_RCR4.
+* To use register names with standard convension, please use VADC_G0_RCR4.
+*/
+#define VADC_G0RCR4 (VADC_G0_RCR4)
+
+/** \brief 694, Group Result Control Reg. */
+#define VADC_G0_RCR5 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020694u)
+
+/** Alias (User Manual Name) for VADC_G0_RCR5.
+* To use register names with standard convension, please use VADC_G0_RCR5.
+*/
+#define VADC_G0RCR5 (VADC_G0_RCR5)
+
+/** \brief 698, Group Result Control Reg. */
+#define VADC_G0_RCR6 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020698u)
+
+/** Alias (User Manual Name) for VADC_G0_RCR6.
+* To use register names with standard convension, please use VADC_G0_RCR6.
+*/
+#define VADC_G0RCR6 (VADC_G0_RCR6)
+
+/** \brief 69C, Group Result Control Reg. */
+#define VADC_G0_RCR7 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF002069Cu)
+
+/** Alias (User Manual Name) for VADC_G0_RCR7.
+* To use register names with standard convension, please use VADC_G0_RCR7.
+*/
+#define VADC_G0RCR7 (VADC_G0_RCR7)
+
+/** \brief 6A0, Group Result Control Reg. */
+#define VADC_G0_RCR8 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF00206A0u)
+
+/** Alias (User Manual Name) for VADC_G0_RCR8.
+* To use register names with standard convension, please use VADC_G0_RCR8.
+*/
+#define VADC_G0RCR8 (VADC_G0_RCR8)
+
+/** \brief 6A4, Group Result Control Reg. */
+#define VADC_G0_RCR9 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF00206A4u)
+
+/** Alias (User Manual Name) for VADC_G0_RCR9.
+* To use register names with standard convension, please use VADC_G0_RCR9.
+*/
+#define VADC_G0RCR9 (VADC_G0_RCR9)
+
+/** \brief 594, Result Event Flag Clear Register, Group */
+#define VADC_G0_REFCLR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_REFCLR*)0xF0020594u)
+
+/** Alias (User Manual Name) for VADC_G0_REFCLR.
+* To use register names with standard convension, please use VADC_G0_REFCLR.
+*/
+#define VADC_G0REFCLR (VADC_G0_REFCLR)
+
+/** \brief 584, Result Event Flag Register, Group */
+#define VADC_G0_REFLAG /*lint --e(923)*/ (*(volatile Ifx_VADC_G_REFLAG*)0xF0020584u)
+
+/** Alias (User Manual Name) for VADC_G0_REFLAG.
+* To use register names with standard convension, please use VADC_G0_REFLAG.
+*/
+#define VADC_G0REFLAG (VADC_G0_REFLAG)
+
+/** \brief 700, Group Result Register */
+#define VADC_G0_RES0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020700u)
+
+/** Alias (User Manual Name) for VADC_G0_RES0.
+* To use register names with standard convension, please use VADC_G0_RES0.
+*/
+#define VADC_G0RES0 (VADC_G0_RES0)
+
+/** \brief 704, Group Result Register */
+#define VADC_G0_RES1 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020704u)
+
+/** Alias (User Manual Name) for VADC_G0_RES1.
+* To use register names with standard convension, please use VADC_G0_RES1.
+*/
+#define VADC_G0RES1 (VADC_G0_RES1)
+
+/** \brief 728, Group Result Register */
+#define VADC_G0_RES10 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020728u)
+
+/** Alias (User Manual Name) for VADC_G0_RES10.
+* To use register names with standard convension, please use VADC_G0_RES10.
+*/
+#define VADC_G0RES10 (VADC_G0_RES10)
+
+/** \brief 72C, Group Result Register */
+#define VADC_G0_RES11 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF002072Cu)
+
+/** Alias (User Manual Name) for VADC_G0_RES11.
+* To use register names with standard convension, please use VADC_G0_RES11.
+*/
+#define VADC_G0RES11 (VADC_G0_RES11)
+
+/** \brief 730, Group Result Register */
+#define VADC_G0_RES12 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020730u)
+
+/** Alias (User Manual Name) for VADC_G0_RES12.
+* To use register names with standard convension, please use VADC_G0_RES12.
+*/
+#define VADC_G0RES12 (VADC_G0_RES12)
+
+/** \brief 734, Group Result Register */
+#define VADC_G0_RES13 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020734u)
+
+/** Alias (User Manual Name) for VADC_G0_RES13.
+* To use register names with standard convension, please use VADC_G0_RES13.
+*/
+#define VADC_G0RES13 (VADC_G0_RES13)
+
+/** \brief 738, Group Result Register */
+#define VADC_G0_RES14 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020738u)
+
+/** Alias (User Manual Name) for VADC_G0_RES14.
+* To use register names with standard convension, please use VADC_G0_RES14.
+*/
+#define VADC_G0RES14 (VADC_G0_RES14)
+
+/** \brief 73C, Group Result Register */
+#define VADC_G0_RES15 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF002073Cu)
+
+/** Alias (User Manual Name) for VADC_G0_RES15.
+* To use register names with standard convension, please use VADC_G0_RES15.
+*/
+#define VADC_G0RES15 (VADC_G0_RES15)
+
+/** \brief 708, Group Result Register */
+#define VADC_G0_RES2 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020708u)
+
+/** Alias (User Manual Name) for VADC_G0_RES2.
+* To use register names with standard convension, please use VADC_G0_RES2.
+*/
+#define VADC_G0RES2 (VADC_G0_RES2)
+
+/** \brief 70C, Group Result Register */
+#define VADC_G0_RES3 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF002070Cu)
+
+/** Alias (User Manual Name) for VADC_G0_RES3.
+* To use register names with standard convension, please use VADC_G0_RES3.
+*/
+#define VADC_G0RES3 (VADC_G0_RES3)
+
+/** \brief 710, Group Result Register */
+#define VADC_G0_RES4 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020710u)
+
+/** Alias (User Manual Name) for VADC_G0_RES4.
+* To use register names with standard convension, please use VADC_G0_RES4.
+*/
+#define VADC_G0RES4 (VADC_G0_RES4)
+
+/** \brief 714, Group Result Register */
+#define VADC_G0_RES5 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020714u)
+
+/** Alias (User Manual Name) for VADC_G0_RES5.
+* To use register names with standard convension, please use VADC_G0_RES5.
+*/
+#define VADC_G0RES5 (VADC_G0_RES5)
+
+/** \brief 718, Group Result Register */
+#define VADC_G0_RES6 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020718u)
+
+/** Alias (User Manual Name) for VADC_G0_RES6.
+* To use register names with standard convension, please use VADC_G0_RES6.
+*/
+#define VADC_G0RES6 (VADC_G0_RES6)
+
+/** \brief 71C, Group Result Register */
+#define VADC_G0_RES7 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF002071Cu)
+
+/** Alias (User Manual Name) for VADC_G0_RES7.
+* To use register names with standard convension, please use VADC_G0_RES7.
+*/
+#define VADC_G0RES7 (VADC_G0_RES7)
+
+/** \brief 720, Group Result Register */
+#define VADC_G0_RES8 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020720u)
+
+/** Alias (User Manual Name) for VADC_G0_RES8.
+* To use register names with standard convension, please use VADC_G0_RES8.
+*/
+#define VADC_G0RES8 (VADC_G0_RES8)
+
+/** \brief 724, Group Result Register */
+#define VADC_G0_RES9 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020724u)
+
+/** Alias (User Manual Name) for VADC_G0_RES9.
+* To use register names with standard convension, please use VADC_G0_RES9.
+*/
+#define VADC_G0RES9 (VADC_G0_RES9)
+
+/** \brief 780, Group Result Reg., Debug */
+#define VADC_G0_RESD0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020780u)
+
+/** Alias (User Manual Name) for VADC_G0_RESD0.
+* To use register names with standard convension, please use VADC_G0_RESD0.
+*/
+#define VADC_G0RESD0 (VADC_G0_RESD0)
+
+/** \brief 784, Group Result Reg., Debug */
+#define VADC_G0_RESD1 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020784u)
+
+/** Alias (User Manual Name) for VADC_G0_RESD1.
+* To use register names with standard convension, please use VADC_G0_RESD1.
+*/
+#define VADC_G0RESD1 (VADC_G0_RESD1)
+
+/** \brief 7A8, Group Result Reg., Debug */
+#define VADC_G0_RESD10 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF00207A8u)
+
+/** Alias (User Manual Name) for VADC_G0_RESD10.
+* To use register names with standard convension, please use VADC_G0_RESD10.
+*/
+#define VADC_G0RESD10 (VADC_G0_RESD10)
+
+/** \brief 7AC, Group Result Reg., Debug */
+#define VADC_G0_RESD11 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF00207ACu)
+
+/** Alias (User Manual Name) for VADC_G0_RESD11.
+* To use register names with standard convension, please use VADC_G0_RESD11.
+*/
+#define VADC_G0RESD11 (VADC_G0_RESD11)
+
+/** \brief 7B0, Group Result Reg., Debug */
+#define VADC_G0_RESD12 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF00207B0u)
+
+/** Alias (User Manual Name) for VADC_G0_RESD12.
+* To use register names with standard convension, please use VADC_G0_RESD12.
+*/
+#define VADC_G0RESD12 (VADC_G0_RESD12)
+
+/** \brief 7B4, Group Result Reg., Debug */
+#define VADC_G0_RESD13 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF00207B4u)
+
+/** Alias (User Manual Name) for VADC_G0_RESD13.
+* To use register names with standard convension, please use VADC_G0_RESD13.
+*/
+#define VADC_G0RESD13 (VADC_G0_RESD13)
+
+/** \brief 7B8, Group Result Reg., Debug */
+#define VADC_G0_RESD14 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF00207B8u)
+
+/** Alias (User Manual Name) for VADC_G0_RESD14.
+* To use register names with standard convension, please use VADC_G0_RESD14.
+*/
+#define VADC_G0RESD14 (VADC_G0_RESD14)
+
+/** \brief 7BC, Group Result Reg., Debug */
+#define VADC_G0_RESD15 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF00207BCu)
+
+/** Alias (User Manual Name) for VADC_G0_RESD15.
+* To use register names with standard convension, please use VADC_G0_RESD15.
+*/
+#define VADC_G0RESD15 (VADC_G0_RESD15)
+
+/** \brief 788, Group Result Reg., Debug */
+#define VADC_G0_RESD2 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020788u)
+
+/** Alias (User Manual Name) for VADC_G0_RESD2.
+* To use register names with standard convension, please use VADC_G0_RESD2.
+*/
+#define VADC_G0RESD2 (VADC_G0_RESD2)
+
+/** \brief 78C, Group Result Reg., Debug */
+#define VADC_G0_RESD3 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF002078Cu)
+
+/** Alias (User Manual Name) for VADC_G0_RESD3.
+* To use register names with standard convension, please use VADC_G0_RESD3.
+*/
+#define VADC_G0RESD3 (VADC_G0_RESD3)
+
+/** \brief 790, Group Result Reg., Debug */
+#define VADC_G0_RESD4 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020790u)
+
+/** Alias (User Manual Name) for VADC_G0_RESD4.
+* To use register names with standard convension, please use VADC_G0_RESD4.
+*/
+#define VADC_G0RESD4 (VADC_G0_RESD4)
+
+/** \brief 794, Group Result Reg., Debug */
+#define VADC_G0_RESD5 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020794u)
+
+/** Alias (User Manual Name) for VADC_G0_RESD5.
+* To use register names with standard convension, please use VADC_G0_RESD5.
+*/
+#define VADC_G0RESD5 (VADC_G0_RESD5)
+
+/** \brief 798, Group Result Reg., Debug */
+#define VADC_G0_RESD6 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020798u)
+
+/** Alias (User Manual Name) for VADC_G0_RESD6.
+* To use register names with standard convension, please use VADC_G0_RESD6.
+*/
+#define VADC_G0RESD6 (VADC_G0_RESD6)
+
+/** \brief 79C, Group Result Reg., Debug */
+#define VADC_G0_RESD7 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF002079Cu)
+
+/** Alias (User Manual Name) for VADC_G0_RESD7.
+* To use register names with standard convension, please use VADC_G0_RESD7.
+*/
+#define VADC_G0RESD7 (VADC_G0_RESD7)
+
+/** \brief 7A0, Group Result Reg., Debug */
+#define VADC_G0_RESD8 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF00207A0u)
+
+/** Alias (User Manual Name) for VADC_G0_RESD8.
+* To use register names with standard convension, please use VADC_G0_RESD8.
+*/
+#define VADC_G0RESD8 (VADC_G0_RESD8)
+
+/** \brief 7A4, Group Result Reg., Debug */
+#define VADC_G0_RESD9 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF00207A4u)
+
+/** Alias (User Manual Name) for VADC_G0_RESD9.
+* To use register names with standard convension, please use VADC_G0_RESD9.
+*/
+#define VADC_G0RESD9 (VADC_G0_RESD9)
+
+/** \brief 5B0, Result Event Node Pointer Register 0, Group */
+#define VADC_G0_REVNP0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_REVNP0*)0xF00205B0u)
+
+/** Alias (User Manual Name) for VADC_G0_REVNP0.
+* To use register names with standard convension, please use VADC_G0_REVNP0.
+*/
+#define VADC_G0REVNP0 (VADC_G0_REVNP0)
+
+/** \brief 5B4, Result Event Node Pointer Register 1, Group */
+#define VADC_G0_REVNP1 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_REVNP1*)0xF00205B4u)
+
+/** Alias (User Manual Name) for VADC_G0_REVNP1.
+* To use register names with standard convension, please use VADC_G0_REVNP1.
+*/
+#define VADC_G0REVNP1 (VADC_G0_REVNP1)
+
+/** \brief 48C, Result Assignment Register, Group */
+#define VADC_G0_RRASS /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RRASS*)0xF002048Cu)
+
+/** Alias (User Manual Name) for VADC_G0_RRASS.
+* To use register names with standard convension, please use VADC_G0_RRASS.
+*/
+#define VADC_G0RRASS (VADC_G0_RRASS)
+
+/** \brief 598, Source Event Flag Clear Register, Group */
+#define VADC_G0_SEFCLR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_SEFCLR*)0xF0020598u)
+
+/** Alias (User Manual Name) for VADC_G0_SEFCLR.
+* To use register names with standard convension, please use VADC_G0_SEFCLR.
+*/
+#define VADC_G0SEFCLR (VADC_G0_SEFCLR)
+
+/** \brief 588, Source Event Flag Register, Group */
+#define VADC_G0_SEFLAG /*lint --e(923)*/ (*(volatile Ifx_VADC_G_SEFLAG*)0xF0020588u)
+
+/** Alias (User Manual Name) for VADC_G0_SEFLAG.
+* To use register names with standard convension, please use VADC_G0_SEFLAG.
+*/
+#define VADC_G0SEFLAG (VADC_G0_SEFLAG)
+
+/** \brief 5C0, Source Event Node Pointer Register, Group */
+#define VADC_G0_SEVNP /*lint --e(923)*/ (*(volatile Ifx_VADC_G_SEVNP*)0xF00205C0u)
+
+/** Alias (User Manual Name) for VADC_G0_SEVNP.
+* To use register names with standard convension, please use VADC_G0_SEVNP.
+*/
+#define VADC_G0SEVNP (VADC_G0_SEVNP)
+
+/** \brief 5C8, Service Request Software Activation Trigger, Group */
+#define VADC_G0_SRACT /*lint --e(923)*/ (*(volatile Ifx_VADC_G_SRACT*)0xF00205C8u)
+
+/** Alias (User Manual Name) for VADC_G0_SRACT.
+* To use register names with standard convension, please use VADC_G0_SRACT.
+*/
+#define VADC_G0SRACT (VADC_G0_SRACT)
+
+/** \brief 4C0, Synchronization Control Register, Group */
+#define VADC_G0_SYNCTR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_SYNCTR*)0xF00204C0u)
+
+/** Alias (User Manual Name) for VADC_G0_SYNCTR.
+* To use register names with standard convension, please use VADC_G0_SYNCTR.
+*/
+#define VADC_G0SYNCTR (VADC_G0_SYNCTR)
+
+/** \brief 5F8, Valid Flag Register, Group */
+#define VADC_G0_VFR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_VFR*)0xF00205F8u)
+
+/** Alias (User Manual Name) for VADC_G0_VFR.
+* To use register names with standard convension, please use VADC_G0_VFR.
+*/
+#define VADC_G0VFR (VADC_G0_VFR)
+
+/** \brief 8B0, Alias Register, Group */
+#define VADC_G1_ALIAS /*lint --e(923)*/ (*(volatile Ifx_VADC_G_ALIAS*)0xF00208B0u)
+
+/** Alias (User Manual Name) for VADC_G1_ALIAS.
+* To use register names with standard convension, please use VADC_G1_ALIAS.
+*/
+#define VADC_G1ALIAS (VADC_G1_ALIAS)
+
+/** \brief 880, Arbitration Configuration Register, Group */
+#define VADC_G1_ARBCFG /*lint --e(923)*/ (*(volatile Ifx_VADC_G_ARBCFG*)0xF0020880u)
+
+/** Alias (User Manual Name) for VADC_G1_ARBCFG.
+* To use register names with standard convension, please use VADC_G1_ARBCFG.
+*/
+#define VADC_G1ARBCFG (VADC_G1_ARBCFG)
+
+/** \brief 884, Arbitration Priority Register, Group */
+#define VADC_G1_ARBPR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_ARBPR*)0xF0020884u)
+
+/** Alias (User Manual Name) for VADC_G1_ARBPR.
+* To use register names with standard convension, please use VADC_G1_ARBPR.
+*/
+#define VADC_G1ARBPR (VADC_G1_ARBPR)
+
+/** \brief 920, Autoscan Source Control Register, Group */
+#define VADC_G1_ASCTRL /*lint --e(923)*/ (*(volatile Ifx_VADC_G_ASCTRL*)0xF0020920u)
+
+/** Alias (User Manual Name) for VADC_G1_ASCTRL.
+* To use register names with standard convension, please use VADC_G1_ASCTRL.
+*/
+#define VADC_G1ASCTRL (VADC_G1_ASCTRL)
+
+/** \brief 924, Autoscan Source Mode Register, Group */
+#define VADC_G1_ASMR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_ASMR*)0xF0020924u)
+
+/** Alias (User Manual Name) for VADC_G1_ASMR.
+* To use register names with standard convension, please use VADC_G1_ASMR.
+*/
+#define VADC_G1ASMR (VADC_G1_ASMR)
+
+/** \brief 92C, Autoscan Source Pending Register, Group */
+#define VADC_G1_ASPND /*lint --e(923)*/ (*(volatile Ifx_VADC_G_ASPND*)0xF002092Cu)
+
+/** Alias (User Manual Name) for VADC_G1_ASPND.
+* To use register names with standard convension, please use VADC_G1_ASPND.
+*/
+#define VADC_G1ASPND (VADC_G1_ASPND)
+
+/** \brief 928, Autoscan Source Channel Select Register, Group */
+#define VADC_G1_ASSEL /*lint --e(923)*/ (*(volatile Ifx_VADC_G_ASSEL*)0xF0020928u)
+
+/** Alias (User Manual Name) for VADC_G1_ASSEL.
+* To use register names with standard convension, please use VADC_G1_ASSEL.
+*/
+#define VADC_G1ASSEL (VADC_G1_ASSEL)
+
+/** \brief 8C8, Boundary Flag Register, Group */
+#define VADC_G1_BFL /*lint --e(923)*/ (*(volatile Ifx_VADC_G_BFL*)0xF00208C8u)
+
+/** Alias (User Manual Name) for VADC_G1_BFL.
+* To use register names with standard convension, please use VADC_G1_BFL.
+*/
+#define VADC_G1BFL (VADC_G1_BFL)
+
+/** \brief 8D0, Boundary Flag Control Register, Group */
+#define VADC_G1_BFLC /*lint --e(923)*/ (*(volatile Ifx_VADC_G_BFLC*)0xF00208D0u)
+
+/** Alias (User Manual Name) for VADC_G1_BFLC.
+* To use register names with standard convension, please use VADC_G1_BFLC.
+*/
+#define VADC_G1BFLC (VADC_G1_BFLC)
+
+/** \brief 8D4, Boundary Flag Node Pointer Register, Group */
+#define VADC_G1_BFLNP /*lint --e(923)*/ (*(volatile Ifx_VADC_G_BFLNP*)0xF00208D4u)
+
+/** Alias (User Manual Name) for VADC_G1_BFLNP.
+* To use register names with standard convension, please use VADC_G1_BFLNP.
+*/
+#define VADC_G1BFLNP (VADC_G1_BFLNP)
+
+/** \brief 8CC, Boundary Flag Software Register, Group */
+#define VADC_G1_BFLS /*lint --e(923)*/ (*(volatile Ifx_VADC_G_BFLS*)0xF00208CCu)
+
+/** Alias (User Manual Name) for VADC_G1_BFLS.
+* To use register names with standard convension, please use VADC_G1_BFLS.
+*/
+#define VADC_G1BFLS (VADC_G1_BFLS)
+
+/** \brief 8B8, Boundary Select Register, Group */
+#define VADC_G1_BOUND /*lint --e(923)*/ (*(volatile Ifx_VADC_G_BOUND*)0xF00208B8u)
+
+/** Alias (User Manual Name) for VADC_G1_BOUND.
+* To use register names with standard convension, please use VADC_G1_BOUND.
+*/
+#define VADC_G1BOUND (VADC_G1_BOUND)
+
+/** \brief 990, Channel Event Flag Clear Register, Group */
+#define VADC_G1_CEFCLR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CEFCLR*)0xF0020990u)
+
+/** Alias (User Manual Name) for VADC_G1_CEFCLR.
+* To use register names with standard convension, please use VADC_G1_CEFCLR.
+*/
+#define VADC_G1CEFCLR (VADC_G1_CEFCLR)
+
+/** \brief 980, Channel Event Flag Register, Group */
+#define VADC_G1_CEFLAG /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CEFLAG*)0xF0020980u)
+
+/** Alias (User Manual Name) for VADC_G1_CEFLAG.
+* To use register names with standard convension, please use VADC_G1_CEFLAG.
+*/
+#define VADC_G1CEFLAG (VADC_G1_CEFLAG)
+
+/** \brief 9A0, Channel Event Node Pointer Register 0, Group */
+#define VADC_G1_CEVNP0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CEVNP0*)0xF00209A0u)
+
+/** Alias (User Manual Name) for VADC_G1_CEVNP0.
+* To use register names with standard convension, please use VADC_G1_CEVNP0.
+*/
+#define VADC_G1CEVNP0 (VADC_G1_CEVNP0)
+
+/** \brief 9A4, Channel Event Node Pointer Register 1, Group */
+#define VADC_G1_CEVNP1 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CEVNP1*)0xF00209A4u)
+
+/** Alias (User Manual Name) for VADC_G1_CEVNP1.
+* To use register names with standard convension, please use VADC_G1_CEVNP1.
+*/
+#define VADC_G1CEVNP1 (VADC_G1_CEVNP1)
+
+/** \brief 888, Channel Assignment Register, Group */
+#define VADC_G1_CHASS /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHASS*)0xF0020888u)
+
+/** Alias (User Manual Name) for VADC_G1_CHASS.
+* To use register names with standard convension, please use VADC_G1_CHASS.
+*/
+#define VADC_G1CHASS (VADC_G1_CHASS)
+
+/** \brief A00, Group, Channel Ctrl. Reg. */
+#define VADC_G1_CHCTR0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020A00u)
+
+/** Alias (User Manual Name) for VADC_G1_CHCTR0.
+* To use register names with standard convension, please use VADC_G1_CHCTR0.
+*/
+#define VADC_G1CHCTR0 (VADC_G1_CHCTR0)
+
+/** \brief A04, Group, Channel Ctrl. Reg. */
+#define VADC_G1_CHCTR1 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020A04u)
+
+/** Alias (User Manual Name) for VADC_G1_CHCTR1.
+* To use register names with standard convension, please use VADC_G1_CHCTR1.
+*/
+#define VADC_G1CHCTR1 (VADC_G1_CHCTR1)
+
+/** \brief A28, Group, Channel Ctrl. Reg. */
+#define VADC_G1_CHCTR10 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020A28u)
+
+/** Alias (User Manual Name) for VADC_G1_CHCTR10.
+* To use register names with standard convension, please use VADC_G1_CHCTR10.
+*/
+#define VADC_G1CHCTR10 (VADC_G1_CHCTR10)
+
+/** \brief A2C, Group, Channel Ctrl. Reg. */
+#define VADC_G1_CHCTR11 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020A2Cu)
+
+/** Alias (User Manual Name) for VADC_G1_CHCTR11.
+* To use register names with standard convension, please use VADC_G1_CHCTR11.
+*/
+#define VADC_G1CHCTR11 (VADC_G1_CHCTR11)
+
+/** \brief A30, Group, Channel Ctrl. Reg. */
+#define VADC_G1_CHCTR12 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020A30u)
+
+/** Alias (User Manual Name) for VADC_G1_CHCTR12.
+* To use register names with standard convension, please use VADC_G1_CHCTR12.
+*/
+#define VADC_G1CHCTR12 (VADC_G1_CHCTR12)
+
+/** \brief A34, Group, Channel Ctrl. Reg. */
+#define VADC_G1_CHCTR13 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020A34u)
+
+/** Alias (User Manual Name) for VADC_G1_CHCTR13.
+* To use register names with standard convension, please use VADC_G1_CHCTR13.
+*/
+#define VADC_G1CHCTR13 (VADC_G1_CHCTR13)
+
+/** \brief A38, Group, Channel Ctrl. Reg. */
+#define VADC_G1_CHCTR14 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020A38u)
+
+/** Alias (User Manual Name) for VADC_G1_CHCTR14.
+* To use register names with standard convension, please use VADC_G1_CHCTR14.
+*/
+#define VADC_G1CHCTR14 (VADC_G1_CHCTR14)
+
+/** \brief A3C, Group, Channel Ctrl. Reg. */
+#define VADC_G1_CHCTR15 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020A3Cu)
+
+/** Alias (User Manual Name) for VADC_G1_CHCTR15.
+* To use register names with standard convension, please use VADC_G1_CHCTR15.
+*/
+#define VADC_G1CHCTR15 (VADC_G1_CHCTR15)
+
+/** \brief A08, Group, Channel Ctrl. Reg. */
+#define VADC_G1_CHCTR2 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020A08u)
+
+/** Alias (User Manual Name) for VADC_G1_CHCTR2.
+* To use register names with standard convension, please use VADC_G1_CHCTR2.
+*/
+#define VADC_G1CHCTR2 (VADC_G1_CHCTR2)
+
+/** \brief A0C, Group, Channel Ctrl. Reg. */
+#define VADC_G1_CHCTR3 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020A0Cu)
+
+/** Alias (User Manual Name) for VADC_G1_CHCTR3.
+* To use register names with standard convension, please use VADC_G1_CHCTR3.
+*/
+#define VADC_G1CHCTR3 (VADC_G1_CHCTR3)
+
+/** \brief A10, Group, Channel Ctrl. Reg. */
+#define VADC_G1_CHCTR4 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020A10u)
+
+/** Alias (User Manual Name) for VADC_G1_CHCTR4.
+* To use register names with standard convension, please use VADC_G1_CHCTR4.
+*/
+#define VADC_G1CHCTR4 (VADC_G1_CHCTR4)
+
+/** \brief A14, Group, Channel Ctrl. Reg. */
+#define VADC_G1_CHCTR5 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020A14u)
+
+/** Alias (User Manual Name) for VADC_G1_CHCTR5.
+* To use register names with standard convension, please use VADC_G1_CHCTR5.
+*/
+#define VADC_G1CHCTR5 (VADC_G1_CHCTR5)
+
+/** \brief A18, Group, Channel Ctrl. Reg. */
+#define VADC_G1_CHCTR6 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020A18u)
+
+/** Alias (User Manual Name) for VADC_G1_CHCTR6.
+* To use register names with standard convension, please use VADC_G1_CHCTR6.
+*/
+#define VADC_G1CHCTR6 (VADC_G1_CHCTR6)
+
+/** \brief A1C, Group, Channel Ctrl. Reg. */
+#define VADC_G1_CHCTR7 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020A1Cu)
+
+/** Alias (User Manual Name) for VADC_G1_CHCTR7.
+* To use register names with standard convension, please use VADC_G1_CHCTR7.
+*/
+#define VADC_G1CHCTR7 (VADC_G1_CHCTR7)
+
+/** \brief A20, Group, Channel Ctrl. Reg. */
+#define VADC_G1_CHCTR8 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020A20u)
+
+/** Alias (User Manual Name) for VADC_G1_CHCTR8.
+* To use register names with standard convension, please use VADC_G1_CHCTR8.
+*/
+#define VADC_G1CHCTR8 (VADC_G1_CHCTR8)
+
+/** \brief A24, Group, Channel Ctrl. Reg. */
+#define VADC_G1_CHCTR9 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020A24u)
+
+/** Alias (User Manual Name) for VADC_G1_CHCTR9.
+* To use register names with standard convension, please use VADC_G1_CHCTR9.
+*/
+#define VADC_G1CHCTR9 (VADC_G1_CHCTR9)
+
+/** \brief 9F0, External Multiplexer Control Register, Group x */
+#define VADC_G1_EMUXCTR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_EMUXCTR*)0xF00209F0u)
+
+/** Alias (User Manual Name) for VADC_G1_EMUXCTR.
+* To use register names with standard convension, please use VADC_G1_EMUXCTR.
+*/
+#define VADC_G1EMUXCTR (VADC_G1_EMUXCTR)
+
+/** \brief 8A0, Input Class Register */
+#define VADC_G1_ICLASS0 /*lint --e(923)*/ (*(volatile Ifx_VADC_ICLASS*)0xF00208A0u)
+
+/** Alias (User Manual Name) for VADC_G1_ICLASS0.
+* To use register names with standard convension, please use VADC_G1_ICLASS0.
+*/
+#define VADC_G1ICLASS0 (VADC_G1_ICLASS0)
+
+/** \brief 8A4, Input Class Register */
+#define VADC_G1_ICLASS1 /*lint --e(923)*/ (*(volatile Ifx_VADC_ICLASS*)0xF00208A4u)
+
+/** Alias (User Manual Name) for VADC_G1_ICLASS1.
+* To use register names with standard convension, please use VADC_G1_ICLASS1.
+*/
+#define VADC_G1ICLASS1 (VADC_G1_ICLASS1)
+
+/** \brief 90C, Queue 0 Register 0, Group */
+#define VADC_G1_Q0R0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_Q0R0*)0xF002090Cu)
+
+/** Alias (User Manual Name) for VADC_G1_Q0R0.
+* To use register names with standard convension, please use VADC_G1_Q0R0.
+*/
+#define VADC_G1Q0R0 (VADC_G1_Q0R0)
+
+/** \brief 910, Queue 0 Input Register, Group */
+#define VADC_G1_QBUR0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_QBUR0*)0xF0020910u)
+
+/** Alias (User Manual Name) for VADC_G1_QBUR0.
+* To use register names with standard convension, please use VADC_G1_QBUR0.
+*/
+#define VADC_G1QBUR0 (VADC_G1_QBUR0)
+
+/** \brief 900, Queue 0 Source Control Register, Group */
+#define VADC_G1_QCTRL0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_QCTRL0*)0xF0020900u)
+
+/** Alias (User Manual Name) for VADC_G1_QCTRL0.
+* To use register names with standard convension, please use VADC_G1_QCTRL0.
+*/
+#define VADC_G1QCTRL0 (VADC_G1_QCTRL0)
+
+/** \brief 910, Queue 0 Input Register, Group */
+#define VADC_G1_QINR0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_QINR0*)0xF0020910u)
+
+/** Alias (User Manual Name) for VADC_G1_QINR0.
+* To use register names with standard convension, please use VADC_G1_QINR0.
+*/
+#define VADC_G1QINR0 (VADC_G1_QINR0)
+
+/** \brief 904, Queue 0 Mode Register, Group */
+#define VADC_G1_QMR0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_QMR0*)0xF0020904u)
+
+/** Alias (User Manual Name) for VADC_G1_QMR0.
+* To use register names with standard convension, please use VADC_G1_QMR0.
+*/
+#define VADC_G1QMR0 (VADC_G1_QMR0)
+
+/** \brief 908, Queue 0 Status Register, Group */
+#define VADC_G1_QSR0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_QSR0*)0xF0020908u)
+
+/** Alias (User Manual Name) for VADC_G1_QSR0.
+* To use register names with standard convension, please use VADC_G1_QSR0.
+*/
+#define VADC_G1QSR0 (VADC_G1_QSR0)
+
+/** \brief A80, Group Result Control Reg. */
+#define VADC_G1_RCR0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020A80u)
+
+/** Alias (User Manual Name) for VADC_G1_RCR0.
+* To use register names with standard convension, please use VADC_G1_RCR0.
+*/
+#define VADC_G1RCR0 (VADC_G1_RCR0)
+
+/** \brief A84, Group Result Control Reg. */
+#define VADC_G1_RCR1 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020A84u)
+
+/** Alias (User Manual Name) for VADC_G1_RCR1.
+* To use register names with standard convension, please use VADC_G1_RCR1.
+*/
+#define VADC_G1RCR1 (VADC_G1_RCR1)
+
+/** \brief AA8, Group Result Control Reg. */
+#define VADC_G1_RCR10 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020AA8u)
+
+/** Alias (User Manual Name) for VADC_G1_RCR10.
+* To use register names with standard convension, please use VADC_G1_RCR10.
+*/
+#define VADC_G1RCR10 (VADC_G1_RCR10)
+
+/** \brief AAC, Group Result Control Reg. */
+#define VADC_G1_RCR11 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020AACu)
+
+/** Alias (User Manual Name) for VADC_G1_RCR11.
+* To use register names with standard convension, please use VADC_G1_RCR11.
+*/
+#define VADC_G1RCR11 (VADC_G1_RCR11)
+
+/** \brief AB0, Group Result Control Reg. */
+#define VADC_G1_RCR12 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020AB0u)
+
+/** Alias (User Manual Name) for VADC_G1_RCR12.
+* To use register names with standard convension, please use VADC_G1_RCR12.
+*/
+#define VADC_G1RCR12 (VADC_G1_RCR12)
+
+/** \brief AB4, Group Result Control Reg. */
+#define VADC_G1_RCR13 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020AB4u)
+
+/** Alias (User Manual Name) for VADC_G1_RCR13.
+* To use register names with standard convension, please use VADC_G1_RCR13.
+*/
+#define VADC_G1RCR13 (VADC_G1_RCR13)
+
+/** \brief AB8, Group Result Control Reg. */
+#define VADC_G1_RCR14 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020AB8u)
+
+/** Alias (User Manual Name) for VADC_G1_RCR14.
+* To use register names with standard convension, please use VADC_G1_RCR14.
+*/
+#define VADC_G1RCR14 (VADC_G1_RCR14)
+
+/** \brief ABC, Group Result Control Reg. */
+#define VADC_G1_RCR15 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020ABCu)
+
+/** Alias (User Manual Name) for VADC_G1_RCR15.
+* To use register names with standard convension, please use VADC_G1_RCR15.
+*/
+#define VADC_G1RCR15 (VADC_G1_RCR15)
+
+/** \brief A88, Group Result Control Reg. */
+#define VADC_G1_RCR2 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020A88u)
+
+/** Alias (User Manual Name) for VADC_G1_RCR2.
+* To use register names with standard convension, please use VADC_G1_RCR2.
+*/
+#define VADC_G1RCR2 (VADC_G1_RCR2)
+
+/** \brief A8C, Group Result Control Reg. */
+#define VADC_G1_RCR3 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020A8Cu)
+
+/** Alias (User Manual Name) for VADC_G1_RCR3.
+* To use register names with standard convension, please use VADC_G1_RCR3.
+*/
+#define VADC_G1RCR3 (VADC_G1_RCR3)
+
+/** \brief A90, Group Result Control Reg. */
+#define VADC_G1_RCR4 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020A90u)
+
+/** Alias (User Manual Name) for VADC_G1_RCR4.
+* To use register names with standard convension, please use VADC_G1_RCR4.
+*/
+#define VADC_G1RCR4 (VADC_G1_RCR4)
+
+/** \brief A94, Group Result Control Reg. */
+#define VADC_G1_RCR5 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020A94u)
+
+/** Alias (User Manual Name) for VADC_G1_RCR5.
+* To use register names with standard convension, please use VADC_G1_RCR5.
+*/
+#define VADC_G1RCR5 (VADC_G1_RCR5)
+
+/** \brief A98, Group Result Control Reg. */
+#define VADC_G1_RCR6 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020A98u)
+
+/** Alias (User Manual Name) for VADC_G1_RCR6.
+* To use register names with standard convension, please use VADC_G1_RCR6.
+*/
+#define VADC_G1RCR6 (VADC_G1_RCR6)
+
+/** \brief A9C, Group Result Control Reg. */
+#define VADC_G1_RCR7 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020A9Cu)
+
+/** Alias (User Manual Name) for VADC_G1_RCR7.
+* To use register names with standard convension, please use VADC_G1_RCR7.
+*/
+#define VADC_G1RCR7 (VADC_G1_RCR7)
+
+/** \brief AA0, Group Result Control Reg. */
+#define VADC_G1_RCR8 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020AA0u)
+
+/** Alias (User Manual Name) for VADC_G1_RCR8.
+* To use register names with standard convension, please use VADC_G1_RCR8.
+*/
+#define VADC_G1RCR8 (VADC_G1_RCR8)
+
+/** \brief AA4, Group Result Control Reg. */
+#define VADC_G1_RCR9 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020AA4u)
+
+/** Alias (User Manual Name) for VADC_G1_RCR9.
+* To use register names with standard convension, please use VADC_G1_RCR9.
+*/
+#define VADC_G1RCR9 (VADC_G1_RCR9)
+
+/** \brief 994, Result Event Flag Clear Register, Group */
+#define VADC_G1_REFCLR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_REFCLR*)0xF0020994u)
+
+/** Alias (User Manual Name) for VADC_G1_REFCLR.
+* To use register names with standard convension, please use VADC_G1_REFCLR.
+*/
+#define VADC_G1REFCLR (VADC_G1_REFCLR)
+
+/** \brief 984, Result Event Flag Register, Group */
+#define VADC_G1_REFLAG /*lint --e(923)*/ (*(volatile Ifx_VADC_G_REFLAG*)0xF0020984u)
+
+/** Alias (User Manual Name) for VADC_G1_REFLAG.
+* To use register names with standard convension, please use VADC_G1_REFLAG.
+*/
+#define VADC_G1REFLAG (VADC_G1_REFLAG)
+
+/** \brief B00, Group Result Register */
+#define VADC_G1_RES0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020B00u)
+
+/** Alias (User Manual Name) for VADC_G1_RES0.
+* To use register names with standard convension, please use VADC_G1_RES0.
+*/
+#define VADC_G1RES0 (VADC_G1_RES0)
+
+/** \brief B04, Group Result Register */
+#define VADC_G1_RES1 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020B04u)
+
+/** Alias (User Manual Name) for VADC_G1_RES1.
+* To use register names with standard convension, please use VADC_G1_RES1.
+*/
+#define VADC_G1RES1 (VADC_G1_RES1)
+
+/** \brief B28, Group Result Register */
+#define VADC_G1_RES10 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020B28u)
+
+/** Alias (User Manual Name) for VADC_G1_RES10.
+* To use register names with standard convension, please use VADC_G1_RES10.
+*/
+#define VADC_G1RES10 (VADC_G1_RES10)
+
+/** \brief B2C, Group Result Register */
+#define VADC_G1_RES11 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020B2Cu)
+
+/** Alias (User Manual Name) for VADC_G1_RES11.
+* To use register names with standard convension, please use VADC_G1_RES11.
+*/
+#define VADC_G1RES11 (VADC_G1_RES11)
+
+/** \brief B30, Group Result Register */
+#define VADC_G1_RES12 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020B30u)
+
+/** Alias (User Manual Name) for VADC_G1_RES12.
+* To use register names with standard convension, please use VADC_G1_RES12.
+*/
+#define VADC_G1RES12 (VADC_G1_RES12)
+
+/** \brief B34, Group Result Register */
+#define VADC_G1_RES13 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020B34u)
+
+/** Alias (User Manual Name) for VADC_G1_RES13.
+* To use register names with standard convension, please use VADC_G1_RES13.
+*/
+#define VADC_G1RES13 (VADC_G1_RES13)
+
+/** \brief B38, Group Result Register */
+#define VADC_G1_RES14 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020B38u)
+
+/** Alias (User Manual Name) for VADC_G1_RES14.
+* To use register names with standard convension, please use VADC_G1_RES14.
+*/
+#define VADC_G1RES14 (VADC_G1_RES14)
+
+/** \brief B3C, Group Result Register */
+#define VADC_G1_RES15 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020B3Cu)
+
+/** Alias (User Manual Name) for VADC_G1_RES15.
+* To use register names with standard convension, please use VADC_G1_RES15.
+*/
+#define VADC_G1RES15 (VADC_G1_RES15)
+
+/** \brief B08, Group Result Register */
+#define VADC_G1_RES2 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020B08u)
+
+/** Alias (User Manual Name) for VADC_G1_RES2.
+* To use register names with standard convension, please use VADC_G1_RES2.
+*/
+#define VADC_G1RES2 (VADC_G1_RES2)
+
+/** \brief B0C, Group Result Register */
+#define VADC_G1_RES3 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020B0Cu)
+
+/** Alias (User Manual Name) for VADC_G1_RES3.
+* To use register names with standard convension, please use VADC_G1_RES3.
+*/
+#define VADC_G1RES3 (VADC_G1_RES3)
+
+/** \brief B10, Group Result Register */
+#define VADC_G1_RES4 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020B10u)
+
+/** Alias (User Manual Name) for VADC_G1_RES4.
+* To use register names with standard convension, please use VADC_G1_RES4.
+*/
+#define VADC_G1RES4 (VADC_G1_RES4)
+
+/** \brief B14, Group Result Register */
+#define VADC_G1_RES5 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020B14u)
+
+/** Alias (User Manual Name) for VADC_G1_RES5.
+* To use register names with standard convension, please use VADC_G1_RES5.
+*/
+#define VADC_G1RES5 (VADC_G1_RES5)
+
+/** \brief B18, Group Result Register */
+#define VADC_G1_RES6 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020B18u)
+
+/** Alias (User Manual Name) for VADC_G1_RES6.
+* To use register names with standard convension, please use VADC_G1_RES6.
+*/
+#define VADC_G1RES6 (VADC_G1_RES6)
+
+/** \brief B1C, Group Result Register */
+#define VADC_G1_RES7 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020B1Cu)
+
+/** Alias (User Manual Name) for VADC_G1_RES7.
+* To use register names with standard convension, please use VADC_G1_RES7.
+*/
+#define VADC_G1RES7 (VADC_G1_RES7)
+
+/** \brief B20, Group Result Register */
+#define VADC_G1_RES8 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020B20u)
+
+/** Alias (User Manual Name) for VADC_G1_RES8.
+* To use register names with standard convension, please use VADC_G1_RES8.
+*/
+#define VADC_G1RES8 (VADC_G1_RES8)
+
+/** \brief B24, Group Result Register */
+#define VADC_G1_RES9 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020B24u)
+
+/** Alias (User Manual Name) for VADC_G1_RES9.
+* To use register names with standard convension, please use VADC_G1_RES9.
+*/
+#define VADC_G1RES9 (VADC_G1_RES9)
+
+/** \brief B80, Group Result Reg., Debug */
+#define VADC_G1_RESD0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020B80u)
+
+/** Alias (User Manual Name) for VADC_G1_RESD0.
+* To use register names with standard convension, please use VADC_G1_RESD0.
+*/
+#define VADC_G1RESD0 (VADC_G1_RESD0)
+
+/** \brief B84, Group Result Reg., Debug */
+#define VADC_G1_RESD1 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020B84u)
+
+/** Alias (User Manual Name) for VADC_G1_RESD1.
+* To use register names with standard convension, please use VADC_G1_RESD1.
+*/
+#define VADC_G1RESD1 (VADC_G1_RESD1)
+
+/** \brief BA8, Group Result Reg., Debug */
+#define VADC_G1_RESD10 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020BA8u)
+
+/** Alias (User Manual Name) for VADC_G1_RESD10.
+* To use register names with standard convension, please use VADC_G1_RESD10.
+*/
+#define VADC_G1RESD10 (VADC_G1_RESD10)
+
+/** \brief BAC, Group Result Reg., Debug */
+#define VADC_G1_RESD11 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020BACu)
+
+/** Alias (User Manual Name) for VADC_G1_RESD11.
+* To use register names with standard convension, please use VADC_G1_RESD11.
+*/
+#define VADC_G1RESD11 (VADC_G1_RESD11)
+
+/** \brief BB0, Group Result Reg., Debug */
+#define VADC_G1_RESD12 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020BB0u)
+
+/** Alias (User Manual Name) for VADC_G1_RESD12.
+* To use register names with standard convension, please use VADC_G1_RESD12.
+*/
+#define VADC_G1RESD12 (VADC_G1_RESD12)
+
+/** \brief BB4, Group Result Reg., Debug */
+#define VADC_G1_RESD13 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020BB4u)
+
+/** Alias (User Manual Name) for VADC_G1_RESD13.
+* To use register names with standard convension, please use VADC_G1_RESD13.
+*/
+#define VADC_G1RESD13 (VADC_G1_RESD13)
+
+/** \brief BB8, Group Result Reg., Debug */
+#define VADC_G1_RESD14 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020BB8u)
+
+/** Alias (User Manual Name) for VADC_G1_RESD14.
+* To use register names with standard convension, please use VADC_G1_RESD14.
+*/
+#define VADC_G1RESD14 (VADC_G1_RESD14)
+
+/** \brief BBC, Group Result Reg., Debug */
+#define VADC_G1_RESD15 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020BBCu)
+
+/** Alias (User Manual Name) for VADC_G1_RESD15.
+* To use register names with standard convension, please use VADC_G1_RESD15.
+*/
+#define VADC_G1RESD15 (VADC_G1_RESD15)
+
+/** \brief B88, Group Result Reg., Debug */
+#define VADC_G1_RESD2 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020B88u)
+
+/** Alias (User Manual Name) for VADC_G1_RESD2.
+* To use register names with standard convension, please use VADC_G1_RESD2.
+*/
+#define VADC_G1RESD2 (VADC_G1_RESD2)
+
+/** \brief B8C, Group Result Reg., Debug */
+#define VADC_G1_RESD3 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020B8Cu)
+
+/** Alias (User Manual Name) for VADC_G1_RESD3.
+* To use register names with standard convension, please use VADC_G1_RESD3.
+*/
+#define VADC_G1RESD3 (VADC_G1_RESD3)
+
+/** \brief B90, Group Result Reg., Debug */
+#define VADC_G1_RESD4 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020B90u)
+
+/** Alias (User Manual Name) for VADC_G1_RESD4.
+* To use register names with standard convension, please use VADC_G1_RESD4.
+*/
+#define VADC_G1RESD4 (VADC_G1_RESD4)
+
+/** \brief B94, Group Result Reg., Debug */
+#define VADC_G1_RESD5 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020B94u)
+
+/** Alias (User Manual Name) for VADC_G1_RESD5.
+* To use register names with standard convension, please use VADC_G1_RESD5.
+*/
+#define VADC_G1RESD5 (VADC_G1_RESD5)
+
+/** \brief B98, Group Result Reg., Debug */
+#define VADC_G1_RESD6 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020B98u)
+
+/** Alias (User Manual Name) for VADC_G1_RESD6.
+* To use register names with standard convension, please use VADC_G1_RESD6.
+*/
+#define VADC_G1RESD6 (VADC_G1_RESD6)
+
+/** \brief B9C, Group Result Reg., Debug */
+#define VADC_G1_RESD7 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020B9Cu)
+
+/** Alias (User Manual Name) for VADC_G1_RESD7.
+* To use register names with standard convension, please use VADC_G1_RESD7.
+*/
+#define VADC_G1RESD7 (VADC_G1_RESD7)
+
+/** \brief BA0, Group Result Reg., Debug */
+#define VADC_G1_RESD8 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020BA0u)
+
+/** Alias (User Manual Name) for VADC_G1_RESD8.
+* To use register names with standard convension, please use VADC_G1_RESD8.
+*/
+#define VADC_G1RESD8 (VADC_G1_RESD8)
+
+/** \brief BA4, Group Result Reg., Debug */
+#define VADC_G1_RESD9 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020BA4u)
+
+/** Alias (User Manual Name) for VADC_G1_RESD9.
+* To use register names with standard convension, please use VADC_G1_RESD9.
+*/
+#define VADC_G1RESD9 (VADC_G1_RESD9)
+
+/** \brief 9B0, Result Event Node Pointer Register 0, Group */
+#define VADC_G1_REVNP0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_REVNP0*)0xF00209B0u)
+
+/** Alias (User Manual Name) for VADC_G1_REVNP0.
+* To use register names with standard convension, please use VADC_G1_REVNP0.
+*/
+#define VADC_G1REVNP0 (VADC_G1_REVNP0)
+
+/** \brief 9B4, Result Event Node Pointer Register 1, Group */
+#define VADC_G1_REVNP1 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_REVNP1*)0xF00209B4u)
+
+/** Alias (User Manual Name) for VADC_G1_REVNP1.
+* To use register names with standard convension, please use VADC_G1_REVNP1.
+*/
+#define VADC_G1REVNP1 (VADC_G1_REVNP1)
+
+/** \brief 88C, Result Assignment Register, Group */
+#define VADC_G1_RRASS /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RRASS*)0xF002088Cu)
+
+/** Alias (User Manual Name) for VADC_G1_RRASS.
+* To use register names with standard convension, please use VADC_G1_RRASS.
+*/
+#define VADC_G1RRASS (VADC_G1_RRASS)
+
+/** \brief 998, Source Event Flag Clear Register, Group */
+#define VADC_G1_SEFCLR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_SEFCLR*)0xF0020998u)
+
+/** Alias (User Manual Name) for VADC_G1_SEFCLR.
+* To use register names with standard convension, please use VADC_G1_SEFCLR.
+*/
+#define VADC_G1SEFCLR (VADC_G1_SEFCLR)
+
+/** \brief 988, Source Event Flag Register, Group */
+#define VADC_G1_SEFLAG /*lint --e(923)*/ (*(volatile Ifx_VADC_G_SEFLAG*)0xF0020988u)
+
+/** Alias (User Manual Name) for VADC_G1_SEFLAG.
+* To use register names with standard convension, please use VADC_G1_SEFLAG.
+*/
+#define VADC_G1SEFLAG (VADC_G1_SEFLAG)
+
+/** \brief 9C0, Source Event Node Pointer Register, Group */
+#define VADC_G1_SEVNP /*lint --e(923)*/ (*(volatile Ifx_VADC_G_SEVNP*)0xF00209C0u)
+
+/** Alias (User Manual Name) for VADC_G1_SEVNP.
+* To use register names with standard convension, please use VADC_G1_SEVNP.
+*/
+#define VADC_G1SEVNP (VADC_G1_SEVNP)
+
+/** \brief 9C8, Service Request Software Activation Trigger, Group */
+#define VADC_G1_SRACT /*lint --e(923)*/ (*(volatile Ifx_VADC_G_SRACT*)0xF00209C8u)
+
+/** Alias (User Manual Name) for VADC_G1_SRACT.
+* To use register names with standard convension, please use VADC_G1_SRACT.
+*/
+#define VADC_G1SRACT (VADC_G1_SRACT)
+
+/** \brief 8C0, Synchronization Control Register, Group */
+#define VADC_G1_SYNCTR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_SYNCTR*)0xF00208C0u)
+
+/** Alias (User Manual Name) for VADC_G1_SYNCTR.
+* To use register names with standard convension, please use VADC_G1_SYNCTR.
+*/
+#define VADC_G1SYNCTR (VADC_G1_SYNCTR)
+
+/** \brief 9F8, Valid Flag Register, Group */
+#define VADC_G1_VFR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_VFR*)0xF00209F8u)
+
+/** Alias (User Manual Name) for VADC_G1_VFR.
+* To use register names with standard convension, please use VADC_G1_VFR.
+*/
+#define VADC_G1VFR (VADC_G1_VFR)
+
+/** \brief CB0, Alias Register, Group */
+#define VADC_G2_ALIAS /*lint --e(923)*/ (*(volatile Ifx_VADC_G_ALIAS*)0xF0020CB0u)
+
+/** Alias (User Manual Name) for VADC_G2_ALIAS.
+* To use register names with standard convension, please use VADC_G2_ALIAS.
+*/
+#define VADC_G2ALIAS (VADC_G2_ALIAS)
+
+/** \brief C80, Arbitration Configuration Register, Group */
+#define VADC_G2_ARBCFG /*lint --e(923)*/ (*(volatile Ifx_VADC_G_ARBCFG*)0xF0020C80u)
+
+/** Alias (User Manual Name) for VADC_G2_ARBCFG.
+* To use register names with standard convension, please use VADC_G2_ARBCFG.
+*/
+#define VADC_G2ARBCFG (VADC_G2_ARBCFG)
+
+/** \brief C84, Arbitration Priority Register, Group */
+#define VADC_G2_ARBPR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_ARBPR*)0xF0020C84u)
+
+/** Alias (User Manual Name) for VADC_G2_ARBPR.
+* To use register names with standard convension, please use VADC_G2_ARBPR.
+*/
+#define VADC_G2ARBPR (VADC_G2_ARBPR)
+
+/** \brief D20, Autoscan Source Control Register, Group */
+#define VADC_G2_ASCTRL /*lint --e(923)*/ (*(volatile Ifx_VADC_G_ASCTRL*)0xF0020D20u)
+
+/** Alias (User Manual Name) for VADC_G2_ASCTRL.
+* To use register names with standard convension, please use VADC_G2_ASCTRL.
+*/
+#define VADC_G2ASCTRL (VADC_G2_ASCTRL)
+
+/** \brief D24, Autoscan Source Mode Register, Group */
+#define VADC_G2_ASMR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_ASMR*)0xF0020D24u)
+
+/** Alias (User Manual Name) for VADC_G2_ASMR.
+* To use register names with standard convension, please use VADC_G2_ASMR.
+*/
+#define VADC_G2ASMR (VADC_G2_ASMR)
+
+/** \brief D2C, Autoscan Source Pending Register, Group */
+#define VADC_G2_ASPND /*lint --e(923)*/ (*(volatile Ifx_VADC_G_ASPND*)0xF0020D2Cu)
+
+/** Alias (User Manual Name) for VADC_G2_ASPND.
+* To use register names with standard convension, please use VADC_G2_ASPND.
+*/
+#define VADC_G2ASPND (VADC_G2_ASPND)
+
+/** \brief D28, Autoscan Source Channel Select Register, Group */
+#define VADC_G2_ASSEL /*lint --e(923)*/ (*(volatile Ifx_VADC_G_ASSEL*)0xF0020D28u)
+
+/** Alias (User Manual Name) for VADC_G2_ASSEL.
+* To use register names with standard convension, please use VADC_G2_ASSEL.
+*/
+#define VADC_G2ASSEL (VADC_G2_ASSEL)
+
+/** \brief CC8, Boundary Flag Register, Group */
+#define VADC_G2_BFL /*lint --e(923)*/ (*(volatile Ifx_VADC_G_BFL*)0xF0020CC8u)
+
+/** Alias (User Manual Name) for VADC_G2_BFL.
+* To use register names with standard convension, please use VADC_G2_BFL.
+*/
+#define VADC_G2BFL (VADC_G2_BFL)
+
+/** \brief CD0, Boundary Flag Control Register, Group */
+#define VADC_G2_BFLC /*lint --e(923)*/ (*(volatile Ifx_VADC_G_BFLC*)0xF0020CD0u)
+
+/** Alias (User Manual Name) for VADC_G2_BFLC.
+* To use register names with standard convension, please use VADC_G2_BFLC.
+*/
+#define VADC_G2BFLC (VADC_G2_BFLC)
+
+/** \brief CD4, Boundary Flag Node Pointer Register, Group */
+#define VADC_G2_BFLNP /*lint --e(923)*/ (*(volatile Ifx_VADC_G_BFLNP*)0xF0020CD4u)
+
+/** Alias (User Manual Name) for VADC_G2_BFLNP.
+* To use register names with standard convension, please use VADC_G2_BFLNP.
+*/
+#define VADC_G2BFLNP (VADC_G2_BFLNP)
+
+/** \brief CCC, Boundary Flag Software Register, Group */
+#define VADC_G2_BFLS /*lint --e(923)*/ (*(volatile Ifx_VADC_G_BFLS*)0xF0020CCCu)
+
+/** Alias (User Manual Name) for VADC_G2_BFLS.
+* To use register names with standard convension, please use VADC_G2_BFLS.
+*/
+#define VADC_G2BFLS (VADC_G2_BFLS)
+
+/** \brief CB8, Boundary Select Register, Group */
+#define VADC_G2_BOUND /*lint --e(923)*/ (*(volatile Ifx_VADC_G_BOUND*)0xF0020CB8u)
+
+/** Alias (User Manual Name) for VADC_G2_BOUND.
+* To use register names with standard convension, please use VADC_G2_BOUND.
+*/
+#define VADC_G2BOUND (VADC_G2_BOUND)
+
+/** \brief D90, Channel Event Flag Clear Register, Group */
+#define VADC_G2_CEFCLR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CEFCLR*)0xF0020D90u)
+
+/** Alias (User Manual Name) for VADC_G2_CEFCLR.
+* To use register names with standard convension, please use VADC_G2_CEFCLR.
+*/
+#define VADC_G2CEFCLR (VADC_G2_CEFCLR)
+
+/** \brief D80, Channel Event Flag Register, Group */
+#define VADC_G2_CEFLAG /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CEFLAG*)0xF0020D80u)
+
+/** Alias (User Manual Name) for VADC_G2_CEFLAG.
+* To use register names with standard convension, please use VADC_G2_CEFLAG.
+*/
+#define VADC_G2CEFLAG (VADC_G2_CEFLAG)
+
+/** \brief DA0, Channel Event Node Pointer Register 0, Group */
+#define VADC_G2_CEVNP0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CEVNP0*)0xF0020DA0u)
+
+/** Alias (User Manual Name) for VADC_G2_CEVNP0.
+* To use register names with standard convension, please use VADC_G2_CEVNP0.
+*/
+#define VADC_G2CEVNP0 (VADC_G2_CEVNP0)
+
+/** \brief DA4, Channel Event Node Pointer Register 1, Group */
+#define VADC_G2_CEVNP1 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CEVNP1*)0xF0020DA4u)
+
+/** Alias (User Manual Name) for VADC_G2_CEVNP1.
+* To use register names with standard convension, please use VADC_G2_CEVNP1.
+*/
+#define VADC_G2CEVNP1 (VADC_G2_CEVNP1)
+
+/** \brief C88, Channel Assignment Register, Group */
+#define VADC_G2_CHASS /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHASS*)0xF0020C88u)
+
+/** Alias (User Manual Name) for VADC_G2_CHASS.
+* To use register names with standard convension, please use VADC_G2_CHASS.
+*/
+#define VADC_G2CHASS (VADC_G2_CHASS)
+
+/** \brief E00, Group, Channel Ctrl. Reg. */
+#define VADC_G2_CHCTR0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020E00u)
+
+/** Alias (User Manual Name) for VADC_G2_CHCTR0.
+* To use register names with standard convension, please use VADC_G2_CHCTR0.
+*/
+#define VADC_G2CHCTR0 (VADC_G2_CHCTR0)
+
+/** \brief E04, Group, Channel Ctrl. Reg. */
+#define VADC_G2_CHCTR1 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020E04u)
+
+/** Alias (User Manual Name) for VADC_G2_CHCTR1.
+* To use register names with standard convension, please use VADC_G2_CHCTR1.
+*/
+#define VADC_G2CHCTR1 (VADC_G2_CHCTR1)
+
+/** \brief E28, Group, Channel Ctrl. Reg. */
+#define VADC_G2_CHCTR10 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020E28u)
+
+/** Alias (User Manual Name) for VADC_G2_CHCTR10.
+* To use register names with standard convension, please use VADC_G2_CHCTR10.
+*/
+#define VADC_G2CHCTR10 (VADC_G2_CHCTR10)
+
+/** \brief E2C, Group, Channel Ctrl. Reg. */
+#define VADC_G2_CHCTR11 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020E2Cu)
+
+/** Alias (User Manual Name) for VADC_G2_CHCTR11.
+* To use register names with standard convension, please use VADC_G2_CHCTR11.
+*/
+#define VADC_G2CHCTR11 (VADC_G2_CHCTR11)
+
+/** \brief E30, Group, Channel Ctrl. Reg. */
+#define VADC_G2_CHCTR12 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020E30u)
+
+/** Alias (User Manual Name) for VADC_G2_CHCTR12.
+* To use register names with standard convension, please use VADC_G2_CHCTR12.
+*/
+#define VADC_G2CHCTR12 (VADC_G2_CHCTR12)
+
+/** \brief E34, Group, Channel Ctrl. Reg. */
+#define VADC_G2_CHCTR13 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020E34u)
+
+/** Alias (User Manual Name) for VADC_G2_CHCTR13.
+* To use register names with standard convension, please use VADC_G2_CHCTR13.
+*/
+#define VADC_G2CHCTR13 (VADC_G2_CHCTR13)
+
+/** \brief E38, Group, Channel Ctrl. Reg. */
+#define VADC_G2_CHCTR14 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020E38u)
+
+/** Alias (User Manual Name) for VADC_G2_CHCTR14.
+* To use register names with standard convension, please use VADC_G2_CHCTR14.
+*/
+#define VADC_G2CHCTR14 (VADC_G2_CHCTR14)
+
+/** \brief E3C, Group, Channel Ctrl. Reg. */
+#define VADC_G2_CHCTR15 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020E3Cu)
+
+/** Alias (User Manual Name) for VADC_G2_CHCTR15.
+* To use register names with standard convension, please use VADC_G2_CHCTR15.
+*/
+#define VADC_G2CHCTR15 (VADC_G2_CHCTR15)
+
+/** \brief E08, Group, Channel Ctrl. Reg. */
+#define VADC_G2_CHCTR2 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020E08u)
+
+/** Alias (User Manual Name) for VADC_G2_CHCTR2.
+* To use register names with standard convension, please use VADC_G2_CHCTR2.
+*/
+#define VADC_G2CHCTR2 (VADC_G2_CHCTR2)
+
+/** \brief E0C, Group, Channel Ctrl. Reg. */
+#define VADC_G2_CHCTR3 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020E0Cu)
+
+/** Alias (User Manual Name) for VADC_G2_CHCTR3.
+* To use register names with standard convension, please use VADC_G2_CHCTR3.
+*/
+#define VADC_G2CHCTR3 (VADC_G2_CHCTR3)
+
+/** \brief E10, Group, Channel Ctrl. Reg. */
+#define VADC_G2_CHCTR4 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020E10u)
+
+/** Alias (User Manual Name) for VADC_G2_CHCTR4.
+* To use register names with standard convension, please use VADC_G2_CHCTR4.
+*/
+#define VADC_G2CHCTR4 (VADC_G2_CHCTR4)
+
+/** \brief E14, Group, Channel Ctrl. Reg. */
+#define VADC_G2_CHCTR5 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020E14u)
+
+/** Alias (User Manual Name) for VADC_G2_CHCTR5.
+* To use register names with standard convension, please use VADC_G2_CHCTR5.
+*/
+#define VADC_G2CHCTR5 (VADC_G2_CHCTR5)
+
+/** \brief E18, Group, Channel Ctrl. Reg. */
+#define VADC_G2_CHCTR6 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020E18u)
+
+/** Alias (User Manual Name) for VADC_G2_CHCTR6.
+* To use register names with standard convension, please use VADC_G2_CHCTR6.
+*/
+#define VADC_G2CHCTR6 (VADC_G2_CHCTR6)
+
+/** \brief E1C, Group, Channel Ctrl. Reg. */
+#define VADC_G2_CHCTR7 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020E1Cu)
+
+/** Alias (User Manual Name) for VADC_G2_CHCTR7.
+* To use register names with standard convension, please use VADC_G2_CHCTR7.
+*/
+#define VADC_G2CHCTR7 (VADC_G2_CHCTR7)
+
+/** \brief E20, Group, Channel Ctrl. Reg. */
+#define VADC_G2_CHCTR8 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020E20u)
+
+/** Alias (User Manual Name) for VADC_G2_CHCTR8.
+* To use register names with standard convension, please use VADC_G2_CHCTR8.
+*/
+#define VADC_G2CHCTR8 (VADC_G2_CHCTR8)
+
+/** \brief E24, Group, Channel Ctrl. Reg. */
+#define VADC_G2_CHCTR9 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0020E24u)
+
+/** Alias (User Manual Name) for VADC_G2_CHCTR9.
+* To use register names with standard convension, please use VADC_G2_CHCTR9.
+*/
+#define VADC_G2CHCTR9 (VADC_G2_CHCTR9)
+
+/** \brief DF0, External Multiplexer Control Register, Group x */
+#define VADC_G2_EMUXCTR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_EMUXCTR*)0xF0020DF0u)
+
+/** Alias (User Manual Name) for VADC_G2_EMUXCTR.
+* To use register names with standard convension, please use VADC_G2_EMUXCTR.
+*/
+#define VADC_G2EMUXCTR (VADC_G2_EMUXCTR)
+
+/** \brief CA0, Input Class Register */
+#define VADC_G2_ICLASS0 /*lint --e(923)*/ (*(volatile Ifx_VADC_ICLASS*)0xF0020CA0u)
+
+/** Alias (User Manual Name) for VADC_G2_ICLASS0.
+* To use register names with standard convension, please use VADC_G2_ICLASS0.
+*/
+#define VADC_G2ICLASS0 (VADC_G2_ICLASS0)
+
+/** \brief CA4, Input Class Register */
+#define VADC_G2_ICLASS1 /*lint --e(923)*/ (*(volatile Ifx_VADC_ICLASS*)0xF0020CA4u)
+
+/** Alias (User Manual Name) for VADC_G2_ICLASS1.
+* To use register names with standard convension, please use VADC_G2_ICLASS1.
+*/
+#define VADC_G2ICLASS1 (VADC_G2_ICLASS1)
+
+/** \brief D0C, Queue 0 Register 0, Group */
+#define VADC_G2_Q0R0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_Q0R0*)0xF0020D0Cu)
+
+/** Alias (User Manual Name) for VADC_G2_Q0R0.
+* To use register names with standard convension, please use VADC_G2_Q0R0.
+*/
+#define VADC_G2Q0R0 (VADC_G2_Q0R0)
+
+/** \brief D10, Queue 0 Input Register, Group */
+#define VADC_G2_QBUR0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_QBUR0*)0xF0020D10u)
+
+/** Alias (User Manual Name) for VADC_G2_QBUR0.
+* To use register names with standard convension, please use VADC_G2_QBUR0.
+*/
+#define VADC_G2QBUR0 (VADC_G2_QBUR0)
+
+/** \brief D00, Queue 0 Source Control Register, Group */
+#define VADC_G2_QCTRL0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_QCTRL0*)0xF0020D00u)
+
+/** Alias (User Manual Name) for VADC_G2_QCTRL0.
+* To use register names with standard convension, please use VADC_G2_QCTRL0.
+*/
+#define VADC_G2QCTRL0 (VADC_G2_QCTRL0)
+
+/** \brief D10, Queue 0 Input Register, Group */
+#define VADC_G2_QINR0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_QINR0*)0xF0020D10u)
+
+/** Alias (User Manual Name) for VADC_G2_QINR0.
+* To use register names with standard convension, please use VADC_G2_QINR0.
+*/
+#define VADC_G2QINR0 (VADC_G2_QINR0)
+
+/** \brief D04, Queue 0 Mode Register, Group */
+#define VADC_G2_QMR0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_QMR0*)0xF0020D04u)
+
+/** Alias (User Manual Name) for VADC_G2_QMR0.
+* To use register names with standard convension, please use VADC_G2_QMR0.
+*/
+#define VADC_G2QMR0 (VADC_G2_QMR0)
+
+/** \brief D08, Queue 0 Status Register, Group */
+#define VADC_G2_QSR0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_QSR0*)0xF0020D08u)
+
+/** Alias (User Manual Name) for VADC_G2_QSR0.
+* To use register names with standard convension, please use VADC_G2_QSR0.
+*/
+#define VADC_G2QSR0 (VADC_G2_QSR0)
+
+/** \brief E80, Group Result Control Reg. */
+#define VADC_G2_RCR0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020E80u)
+
+/** Alias (User Manual Name) for VADC_G2_RCR0.
+* To use register names with standard convension, please use VADC_G2_RCR0.
+*/
+#define VADC_G2RCR0 (VADC_G2_RCR0)
+
+/** \brief E84, Group Result Control Reg. */
+#define VADC_G2_RCR1 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020E84u)
+
+/** Alias (User Manual Name) for VADC_G2_RCR1.
+* To use register names with standard convension, please use VADC_G2_RCR1.
+*/
+#define VADC_G2RCR1 (VADC_G2_RCR1)
+
+/** \brief EA8, Group Result Control Reg. */
+#define VADC_G2_RCR10 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020EA8u)
+
+/** Alias (User Manual Name) for VADC_G2_RCR10.
+* To use register names with standard convension, please use VADC_G2_RCR10.
+*/
+#define VADC_G2RCR10 (VADC_G2_RCR10)
+
+/** \brief EAC, Group Result Control Reg. */
+#define VADC_G2_RCR11 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020EACu)
+
+/** Alias (User Manual Name) for VADC_G2_RCR11.
+* To use register names with standard convension, please use VADC_G2_RCR11.
+*/
+#define VADC_G2RCR11 (VADC_G2_RCR11)
+
+/** \brief EB0, Group Result Control Reg. */
+#define VADC_G2_RCR12 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020EB0u)
+
+/** Alias (User Manual Name) for VADC_G2_RCR12.
+* To use register names with standard convension, please use VADC_G2_RCR12.
+*/
+#define VADC_G2RCR12 (VADC_G2_RCR12)
+
+/** \brief EB4, Group Result Control Reg. */
+#define VADC_G2_RCR13 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020EB4u)
+
+/** Alias (User Manual Name) for VADC_G2_RCR13.
+* To use register names with standard convension, please use VADC_G2_RCR13.
+*/
+#define VADC_G2RCR13 (VADC_G2_RCR13)
+
+/** \brief EB8, Group Result Control Reg. */
+#define VADC_G2_RCR14 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020EB8u)
+
+/** Alias (User Manual Name) for VADC_G2_RCR14.
+* To use register names with standard convension, please use VADC_G2_RCR14.
+*/
+#define VADC_G2RCR14 (VADC_G2_RCR14)
+
+/** \brief EBC, Group Result Control Reg. */
+#define VADC_G2_RCR15 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020EBCu)
+
+/** Alias (User Manual Name) for VADC_G2_RCR15.
+* To use register names with standard convension, please use VADC_G2_RCR15.
+*/
+#define VADC_G2RCR15 (VADC_G2_RCR15)
+
+/** \brief E88, Group Result Control Reg. */
+#define VADC_G2_RCR2 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020E88u)
+
+/** Alias (User Manual Name) for VADC_G2_RCR2.
+* To use register names with standard convension, please use VADC_G2_RCR2.
+*/
+#define VADC_G2RCR2 (VADC_G2_RCR2)
+
+/** \brief E8C, Group Result Control Reg. */
+#define VADC_G2_RCR3 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020E8Cu)
+
+/** Alias (User Manual Name) for VADC_G2_RCR3.
+* To use register names with standard convension, please use VADC_G2_RCR3.
+*/
+#define VADC_G2RCR3 (VADC_G2_RCR3)
+
+/** \brief E90, Group Result Control Reg. */
+#define VADC_G2_RCR4 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020E90u)
+
+/** Alias (User Manual Name) for VADC_G2_RCR4.
+* To use register names with standard convension, please use VADC_G2_RCR4.
+*/
+#define VADC_G2RCR4 (VADC_G2_RCR4)
+
+/** \brief E94, Group Result Control Reg. */
+#define VADC_G2_RCR5 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020E94u)
+
+/** Alias (User Manual Name) for VADC_G2_RCR5.
+* To use register names with standard convension, please use VADC_G2_RCR5.
+*/
+#define VADC_G2RCR5 (VADC_G2_RCR5)
+
+/** \brief E98, Group Result Control Reg. */
+#define VADC_G2_RCR6 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020E98u)
+
+/** Alias (User Manual Name) for VADC_G2_RCR6.
+* To use register names with standard convension, please use VADC_G2_RCR6.
+*/
+#define VADC_G2RCR6 (VADC_G2_RCR6)
+
+/** \brief E9C, Group Result Control Reg. */
+#define VADC_G2_RCR7 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020E9Cu)
+
+/** Alias (User Manual Name) for VADC_G2_RCR7.
+* To use register names with standard convension, please use VADC_G2_RCR7.
+*/
+#define VADC_G2RCR7 (VADC_G2_RCR7)
+
+/** \brief EA0, Group Result Control Reg. */
+#define VADC_G2_RCR8 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020EA0u)
+
+/** Alias (User Manual Name) for VADC_G2_RCR8.
+* To use register names with standard convension, please use VADC_G2_RCR8.
+*/
+#define VADC_G2RCR8 (VADC_G2_RCR8)
+
+/** \brief EA4, Group Result Control Reg. */
+#define VADC_G2_RCR9 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0020EA4u)
+
+/** Alias (User Manual Name) for VADC_G2_RCR9.
+* To use register names with standard convension, please use VADC_G2_RCR9.
+*/
+#define VADC_G2RCR9 (VADC_G2_RCR9)
+
+/** \brief D94, Result Event Flag Clear Register, Group */
+#define VADC_G2_REFCLR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_REFCLR*)0xF0020D94u)
+
+/** Alias (User Manual Name) for VADC_G2_REFCLR.
+* To use register names with standard convension, please use VADC_G2_REFCLR.
+*/
+#define VADC_G2REFCLR (VADC_G2_REFCLR)
+
+/** \brief D84, Result Event Flag Register, Group */
+#define VADC_G2_REFLAG /*lint --e(923)*/ (*(volatile Ifx_VADC_G_REFLAG*)0xF0020D84u)
+
+/** Alias (User Manual Name) for VADC_G2_REFLAG.
+* To use register names with standard convension, please use VADC_G2_REFLAG.
+*/
+#define VADC_G2REFLAG (VADC_G2_REFLAG)
+
+/** \brief F00, Group Result Register */
+#define VADC_G2_RES0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020F00u)
+
+/** Alias (User Manual Name) for VADC_G2_RES0.
+* To use register names with standard convension, please use VADC_G2_RES0.
+*/
+#define VADC_G2RES0 (VADC_G2_RES0)
+
+/** \brief F04, Group Result Register */
+#define VADC_G2_RES1 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020F04u)
+
+/** Alias (User Manual Name) for VADC_G2_RES1.
+* To use register names with standard convension, please use VADC_G2_RES1.
+*/
+#define VADC_G2RES1 (VADC_G2_RES1)
+
+/** \brief F28, Group Result Register */
+#define VADC_G2_RES10 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020F28u)
+
+/** Alias (User Manual Name) for VADC_G2_RES10.
+* To use register names with standard convension, please use VADC_G2_RES10.
+*/
+#define VADC_G2RES10 (VADC_G2_RES10)
+
+/** \brief F2C, Group Result Register */
+#define VADC_G2_RES11 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020F2Cu)
+
+/** Alias (User Manual Name) for VADC_G2_RES11.
+* To use register names with standard convension, please use VADC_G2_RES11.
+*/
+#define VADC_G2RES11 (VADC_G2_RES11)
+
+/** \brief F30, Group Result Register */
+#define VADC_G2_RES12 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020F30u)
+
+/** Alias (User Manual Name) for VADC_G2_RES12.
+* To use register names with standard convension, please use VADC_G2_RES12.
+*/
+#define VADC_G2RES12 (VADC_G2_RES12)
+
+/** \brief F34, Group Result Register */
+#define VADC_G2_RES13 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020F34u)
+
+/** Alias (User Manual Name) for VADC_G2_RES13.
+* To use register names with standard convension, please use VADC_G2_RES13.
+*/
+#define VADC_G2RES13 (VADC_G2_RES13)
+
+/** \brief F38, Group Result Register */
+#define VADC_G2_RES14 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020F38u)
+
+/** Alias (User Manual Name) for VADC_G2_RES14.
+* To use register names with standard convension, please use VADC_G2_RES14.
+*/
+#define VADC_G2RES14 (VADC_G2_RES14)
+
+/** \brief F3C, Group Result Register */
+#define VADC_G2_RES15 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020F3Cu)
+
+/** Alias (User Manual Name) for VADC_G2_RES15.
+* To use register names with standard convension, please use VADC_G2_RES15.
+*/
+#define VADC_G2RES15 (VADC_G2_RES15)
+
+/** \brief F08, Group Result Register */
+#define VADC_G2_RES2 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020F08u)
+
+/** Alias (User Manual Name) for VADC_G2_RES2.
+* To use register names with standard convension, please use VADC_G2_RES2.
+*/
+#define VADC_G2RES2 (VADC_G2_RES2)
+
+/** \brief F0C, Group Result Register */
+#define VADC_G2_RES3 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020F0Cu)
+
+/** Alias (User Manual Name) for VADC_G2_RES3.
+* To use register names with standard convension, please use VADC_G2_RES3.
+*/
+#define VADC_G2RES3 (VADC_G2_RES3)
+
+/** \brief F10, Group Result Register */
+#define VADC_G2_RES4 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020F10u)
+
+/** Alias (User Manual Name) for VADC_G2_RES4.
+* To use register names with standard convension, please use VADC_G2_RES4.
+*/
+#define VADC_G2RES4 (VADC_G2_RES4)
+
+/** \brief F14, Group Result Register */
+#define VADC_G2_RES5 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020F14u)
+
+/** Alias (User Manual Name) for VADC_G2_RES5.
+* To use register names with standard convension, please use VADC_G2_RES5.
+*/
+#define VADC_G2RES5 (VADC_G2_RES5)
+
+/** \brief F18, Group Result Register */
+#define VADC_G2_RES6 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020F18u)
+
+/** Alias (User Manual Name) for VADC_G2_RES6.
+* To use register names with standard convension, please use VADC_G2_RES6.
+*/
+#define VADC_G2RES6 (VADC_G2_RES6)
+
+/** \brief F1C, Group Result Register */
+#define VADC_G2_RES7 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020F1Cu)
+
+/** Alias (User Manual Name) for VADC_G2_RES7.
+* To use register names with standard convension, please use VADC_G2_RES7.
+*/
+#define VADC_G2RES7 (VADC_G2_RES7)
+
+/** \brief F20, Group Result Register */
+#define VADC_G2_RES8 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020F20u)
+
+/** Alias (User Manual Name) for VADC_G2_RES8.
+* To use register names with standard convension, please use VADC_G2_RES8.
+*/
+#define VADC_G2RES8 (VADC_G2_RES8)
+
+/** \brief F24, Group Result Register */
+#define VADC_G2_RES9 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0020F24u)
+
+/** Alias (User Manual Name) for VADC_G2_RES9.
+* To use register names with standard convension, please use VADC_G2_RES9.
+*/
+#define VADC_G2RES9 (VADC_G2_RES9)
+
+/** \brief F80, Group Result Reg., Debug */
+#define VADC_G2_RESD0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020F80u)
+
+/** Alias (User Manual Name) for VADC_G2_RESD0.
+* To use register names with standard convension, please use VADC_G2_RESD0.
+*/
+#define VADC_G2RESD0 (VADC_G2_RESD0)
+
+/** \brief F84, Group Result Reg., Debug */
+#define VADC_G2_RESD1 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020F84u)
+
+/** Alias (User Manual Name) for VADC_G2_RESD1.
+* To use register names with standard convension, please use VADC_G2_RESD1.
+*/
+#define VADC_G2RESD1 (VADC_G2_RESD1)
+
+/** \brief FA8, Group Result Reg., Debug */
+#define VADC_G2_RESD10 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020FA8u)
+
+/** Alias (User Manual Name) for VADC_G2_RESD10.
+* To use register names with standard convension, please use VADC_G2_RESD10.
+*/
+#define VADC_G2RESD10 (VADC_G2_RESD10)
+
+/** \brief FAC, Group Result Reg., Debug */
+#define VADC_G2_RESD11 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020FACu)
+
+/** Alias (User Manual Name) for VADC_G2_RESD11.
+* To use register names with standard convension, please use VADC_G2_RESD11.
+*/
+#define VADC_G2RESD11 (VADC_G2_RESD11)
+
+/** \brief FB0, Group Result Reg., Debug */
+#define VADC_G2_RESD12 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020FB0u)
+
+/** Alias (User Manual Name) for VADC_G2_RESD12.
+* To use register names with standard convension, please use VADC_G2_RESD12.
+*/
+#define VADC_G2RESD12 (VADC_G2_RESD12)
+
+/** \brief FB4, Group Result Reg., Debug */
+#define VADC_G2_RESD13 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020FB4u)
+
+/** Alias (User Manual Name) for VADC_G2_RESD13.
+* To use register names with standard convension, please use VADC_G2_RESD13.
+*/
+#define VADC_G2RESD13 (VADC_G2_RESD13)
+
+/** \brief FB8, Group Result Reg., Debug */
+#define VADC_G2_RESD14 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020FB8u)
+
+/** Alias (User Manual Name) for VADC_G2_RESD14.
+* To use register names with standard convension, please use VADC_G2_RESD14.
+*/
+#define VADC_G2RESD14 (VADC_G2_RESD14)
+
+/** \brief FBC, Group Result Reg., Debug */
+#define VADC_G2_RESD15 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020FBCu)
+
+/** Alias (User Manual Name) for VADC_G2_RESD15.
+* To use register names with standard convension, please use VADC_G2_RESD15.
+*/
+#define VADC_G2RESD15 (VADC_G2_RESD15)
+
+/** \brief F88, Group Result Reg., Debug */
+#define VADC_G2_RESD2 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020F88u)
+
+/** Alias (User Manual Name) for VADC_G2_RESD2.
+* To use register names with standard convension, please use VADC_G2_RESD2.
+*/
+#define VADC_G2RESD2 (VADC_G2_RESD2)
+
+/** \brief F8C, Group Result Reg., Debug */
+#define VADC_G2_RESD3 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020F8Cu)
+
+/** Alias (User Manual Name) for VADC_G2_RESD3.
+* To use register names with standard convension, please use VADC_G2_RESD3.
+*/
+#define VADC_G2RESD3 (VADC_G2_RESD3)
+
+/** \brief F90, Group Result Reg., Debug */
+#define VADC_G2_RESD4 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020F90u)
+
+/** Alias (User Manual Name) for VADC_G2_RESD4.
+* To use register names with standard convension, please use VADC_G2_RESD4.
+*/
+#define VADC_G2RESD4 (VADC_G2_RESD4)
+
+/** \brief F94, Group Result Reg., Debug */
+#define VADC_G2_RESD5 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020F94u)
+
+/** Alias (User Manual Name) for VADC_G2_RESD5.
+* To use register names with standard convension, please use VADC_G2_RESD5.
+*/
+#define VADC_G2RESD5 (VADC_G2_RESD5)
+
+/** \brief F98, Group Result Reg., Debug */
+#define VADC_G2_RESD6 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020F98u)
+
+/** Alias (User Manual Name) for VADC_G2_RESD6.
+* To use register names with standard convension, please use VADC_G2_RESD6.
+*/
+#define VADC_G2RESD6 (VADC_G2_RESD6)
+
+/** \brief F9C, Group Result Reg., Debug */
+#define VADC_G2_RESD7 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020F9Cu)
+
+/** Alias (User Manual Name) for VADC_G2_RESD7.
+* To use register names with standard convension, please use VADC_G2_RESD7.
+*/
+#define VADC_G2RESD7 (VADC_G2_RESD7)
+
+/** \brief FA0, Group Result Reg., Debug */
+#define VADC_G2_RESD8 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020FA0u)
+
+/** Alias (User Manual Name) for VADC_G2_RESD8.
+* To use register names with standard convension, please use VADC_G2_RESD8.
+*/
+#define VADC_G2RESD8 (VADC_G2_RESD8)
+
+/** \brief FA4, Group Result Reg., Debug */
+#define VADC_G2_RESD9 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0020FA4u)
+
+/** Alias (User Manual Name) for VADC_G2_RESD9.
+* To use register names with standard convension, please use VADC_G2_RESD9.
+*/
+#define VADC_G2RESD9 (VADC_G2_RESD9)
+
+/** \brief DB0, Result Event Node Pointer Register 0, Group */
+#define VADC_G2_REVNP0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_REVNP0*)0xF0020DB0u)
+
+/** Alias (User Manual Name) for VADC_G2_REVNP0.
+* To use register names with standard convension, please use VADC_G2_REVNP0.
+*/
+#define VADC_G2REVNP0 (VADC_G2_REVNP0)
+
+/** \brief DB4, Result Event Node Pointer Register 1, Group */
+#define VADC_G2_REVNP1 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_REVNP1*)0xF0020DB4u)
+
+/** Alias (User Manual Name) for VADC_G2_REVNP1.
+* To use register names with standard convension, please use VADC_G2_REVNP1.
+*/
+#define VADC_G2REVNP1 (VADC_G2_REVNP1)
+
+/** \brief C8C, Result Assignment Register, Group */
+#define VADC_G2_RRASS /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RRASS*)0xF0020C8Cu)
+
+/** Alias (User Manual Name) for VADC_G2_RRASS.
+* To use register names with standard convension, please use VADC_G2_RRASS.
+*/
+#define VADC_G2RRASS (VADC_G2_RRASS)
+
+/** \brief D98, Source Event Flag Clear Register, Group */
+#define VADC_G2_SEFCLR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_SEFCLR*)0xF0020D98u)
+
+/** Alias (User Manual Name) for VADC_G2_SEFCLR.
+* To use register names with standard convension, please use VADC_G2_SEFCLR.
+*/
+#define VADC_G2SEFCLR (VADC_G2_SEFCLR)
+
+/** \brief D88, Source Event Flag Register, Group */
+#define VADC_G2_SEFLAG /*lint --e(923)*/ (*(volatile Ifx_VADC_G_SEFLAG*)0xF0020D88u)
+
+/** Alias (User Manual Name) for VADC_G2_SEFLAG.
+* To use register names with standard convension, please use VADC_G2_SEFLAG.
+*/
+#define VADC_G2SEFLAG (VADC_G2_SEFLAG)
+
+/** \brief DC0, Source Event Node Pointer Register, Group */
+#define VADC_G2_SEVNP /*lint --e(923)*/ (*(volatile Ifx_VADC_G_SEVNP*)0xF0020DC0u)
+
+/** Alias (User Manual Name) for VADC_G2_SEVNP.
+* To use register names with standard convension, please use VADC_G2_SEVNP.
+*/
+#define VADC_G2SEVNP (VADC_G2_SEVNP)
+
+/** \brief DC8, Service Request Software Activation Trigger, Group */
+#define VADC_G2_SRACT /*lint --e(923)*/ (*(volatile Ifx_VADC_G_SRACT*)0xF0020DC8u)
+
+/** Alias (User Manual Name) for VADC_G2_SRACT.
+* To use register names with standard convension, please use VADC_G2_SRACT.
+*/
+#define VADC_G2SRACT (VADC_G2_SRACT)
+
+/** \brief CC0, Synchronization Control Register, Group */
+#define VADC_G2_SYNCTR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_SYNCTR*)0xF0020CC0u)
+
+/** Alias (User Manual Name) for VADC_G2_SYNCTR.
+* To use register names with standard convension, please use VADC_G2_SYNCTR.
+*/
+#define VADC_G2SYNCTR (VADC_G2_SYNCTR)
+
+/** \brief DF8, Valid Flag Register, Group */
+#define VADC_G2_VFR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_VFR*)0xF0020DF8u)
+
+/** Alias (User Manual Name) for VADC_G2_VFR.
+* To use register names with standard convension, please use VADC_G2_VFR.
+*/
+#define VADC_G2VFR (VADC_G2_VFR)
+
+/** \brief 10B0, Alias Register, Group */
+#define VADC_G3_ALIAS /*lint --e(923)*/ (*(volatile Ifx_VADC_G_ALIAS*)0xF00210B0u)
+
+/** Alias (User Manual Name) for VADC_G3_ALIAS.
+* To use register names with standard convension, please use VADC_G3_ALIAS.
+*/
+#define VADC_G3ALIAS (VADC_G3_ALIAS)
+
+/** \brief 1080, Arbitration Configuration Register, Group */
+#define VADC_G3_ARBCFG /*lint --e(923)*/ (*(volatile Ifx_VADC_G_ARBCFG*)0xF0021080u)
+
+/** Alias (User Manual Name) for VADC_G3_ARBCFG.
+* To use register names with standard convension, please use VADC_G3_ARBCFG.
+*/
+#define VADC_G3ARBCFG (VADC_G3_ARBCFG)
+
+/** \brief 1084, Arbitration Priority Register, Group */
+#define VADC_G3_ARBPR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_ARBPR*)0xF0021084u)
+
+/** Alias (User Manual Name) for VADC_G3_ARBPR.
+* To use register names with standard convension, please use VADC_G3_ARBPR.
+*/
+#define VADC_G3ARBPR (VADC_G3_ARBPR)
+
+/** \brief 1120, Autoscan Source Control Register, Group */
+#define VADC_G3_ASCTRL /*lint --e(923)*/ (*(volatile Ifx_VADC_G_ASCTRL*)0xF0021120u)
+
+/** Alias (User Manual Name) for VADC_G3_ASCTRL.
+* To use register names with standard convension, please use VADC_G3_ASCTRL.
+*/
+#define VADC_G3ASCTRL (VADC_G3_ASCTRL)
+
+/** \brief 1124, Autoscan Source Mode Register, Group */
+#define VADC_G3_ASMR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_ASMR*)0xF0021124u)
+
+/** Alias (User Manual Name) for VADC_G3_ASMR.
+* To use register names with standard convension, please use VADC_G3_ASMR.
+*/
+#define VADC_G3ASMR (VADC_G3_ASMR)
+
+/** \brief 112C, Autoscan Source Pending Register, Group */
+#define VADC_G3_ASPND /*lint --e(923)*/ (*(volatile Ifx_VADC_G_ASPND*)0xF002112Cu)
+
+/** Alias (User Manual Name) for VADC_G3_ASPND.
+* To use register names with standard convension, please use VADC_G3_ASPND.
+*/
+#define VADC_G3ASPND (VADC_G3_ASPND)
+
+/** \brief 1128, Autoscan Source Channel Select Register, Group */
+#define VADC_G3_ASSEL /*lint --e(923)*/ (*(volatile Ifx_VADC_G_ASSEL*)0xF0021128u)
+
+/** Alias (User Manual Name) for VADC_G3_ASSEL.
+* To use register names with standard convension, please use VADC_G3_ASSEL.
+*/
+#define VADC_G3ASSEL (VADC_G3_ASSEL)
+
+/** \brief 10C8, Boundary Flag Register, Group */
+#define VADC_G3_BFL /*lint --e(923)*/ (*(volatile Ifx_VADC_G_BFL*)0xF00210C8u)
+
+/** Alias (User Manual Name) for VADC_G3_BFL.
+* To use register names with standard convension, please use VADC_G3_BFL.
+*/
+#define VADC_G3BFL (VADC_G3_BFL)
+
+/** \brief 10D0, Boundary Flag Control Register, Group */
+#define VADC_G3_BFLC /*lint --e(923)*/ (*(volatile Ifx_VADC_G_BFLC*)0xF00210D0u)
+
+/** Alias (User Manual Name) for VADC_G3_BFLC.
+* To use register names with standard convension, please use VADC_G3_BFLC.
+*/
+#define VADC_G3BFLC (VADC_G3_BFLC)
+
+/** \brief 10D4, Boundary Flag Node Pointer Register, Group */
+#define VADC_G3_BFLNP /*lint --e(923)*/ (*(volatile Ifx_VADC_G_BFLNP*)0xF00210D4u)
+
+/** Alias (User Manual Name) for VADC_G3_BFLNP.
+* To use register names with standard convension, please use VADC_G3_BFLNP.
+*/
+#define VADC_G3BFLNP (VADC_G3_BFLNP)
+
+/** \brief 10CC, Boundary Flag Software Register, Group */
+#define VADC_G3_BFLS /*lint --e(923)*/ (*(volatile Ifx_VADC_G_BFLS*)0xF00210CCu)
+
+/** Alias (User Manual Name) for VADC_G3_BFLS.
+* To use register names with standard convension, please use VADC_G3_BFLS.
+*/
+#define VADC_G3BFLS (VADC_G3_BFLS)
+
+/** \brief 10B8, Boundary Select Register, Group */
+#define VADC_G3_BOUND /*lint --e(923)*/ (*(volatile Ifx_VADC_G_BOUND*)0xF00210B8u)
+
+/** Alias (User Manual Name) for VADC_G3_BOUND.
+* To use register names with standard convension, please use VADC_G3_BOUND.
+*/
+#define VADC_G3BOUND (VADC_G3_BOUND)
+
+/** \brief 1190, Channel Event Flag Clear Register, Group */
+#define VADC_G3_CEFCLR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CEFCLR*)0xF0021190u)
+
+/** Alias (User Manual Name) for VADC_G3_CEFCLR.
+* To use register names with standard convension, please use VADC_G3_CEFCLR.
+*/
+#define VADC_G3CEFCLR (VADC_G3_CEFCLR)
+
+/** \brief 1180, Channel Event Flag Register, Group */
+#define VADC_G3_CEFLAG /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CEFLAG*)0xF0021180u)
+
+/** Alias (User Manual Name) for VADC_G3_CEFLAG.
+* To use register names with standard convension, please use VADC_G3_CEFLAG.
+*/
+#define VADC_G3CEFLAG (VADC_G3_CEFLAG)
+
+/** \brief 11A0, Channel Event Node Pointer Register 0, Group */
+#define VADC_G3_CEVNP0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CEVNP0*)0xF00211A0u)
+
+/** Alias (User Manual Name) for VADC_G3_CEVNP0.
+* To use register names with standard convension, please use VADC_G3_CEVNP0.
+*/
+#define VADC_G3CEVNP0 (VADC_G3_CEVNP0)
+
+/** \brief 11A4, Channel Event Node Pointer Register 1, Group */
+#define VADC_G3_CEVNP1 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CEVNP1*)0xF00211A4u)
+
+/** Alias (User Manual Name) for VADC_G3_CEVNP1.
+* To use register names with standard convension, please use VADC_G3_CEVNP1.
+*/
+#define VADC_G3CEVNP1 (VADC_G3_CEVNP1)
+
+/** \brief 1088, Channel Assignment Register, Group */
+#define VADC_G3_CHASS /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHASS*)0xF0021088u)
+
+/** Alias (User Manual Name) for VADC_G3_CHASS.
+* To use register names with standard convension, please use VADC_G3_CHASS.
+*/
+#define VADC_G3CHASS (VADC_G3_CHASS)
+
+/** \brief 1200, Group, Channel Ctrl. Reg. */
+#define VADC_G3_CHCTR0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0021200u)
+
+/** Alias (User Manual Name) for VADC_G3_CHCTR0.
+* To use register names with standard convension, please use VADC_G3_CHCTR0.
+*/
+#define VADC_G3CHCTR0 (VADC_G3_CHCTR0)
+
+/** \brief 1204, Group, Channel Ctrl. Reg. */
+#define VADC_G3_CHCTR1 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0021204u)
+
+/** Alias (User Manual Name) for VADC_G3_CHCTR1.
+* To use register names with standard convension, please use VADC_G3_CHCTR1.
+*/
+#define VADC_G3CHCTR1 (VADC_G3_CHCTR1)
+
+/** \brief 1228, Group, Channel Ctrl. Reg. */
+#define VADC_G3_CHCTR10 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0021228u)
+
+/** Alias (User Manual Name) for VADC_G3_CHCTR10.
+* To use register names with standard convension, please use VADC_G3_CHCTR10.
+*/
+#define VADC_G3CHCTR10 (VADC_G3_CHCTR10)
+
+/** \brief 122C, Group, Channel Ctrl. Reg. */
+#define VADC_G3_CHCTR11 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF002122Cu)
+
+/** Alias (User Manual Name) for VADC_G3_CHCTR11.
+* To use register names with standard convension, please use VADC_G3_CHCTR11.
+*/
+#define VADC_G3CHCTR11 (VADC_G3_CHCTR11)
+
+/** \brief 1208, Group, Channel Ctrl. Reg. */
+#define VADC_G3_CHCTR2 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0021208u)
+
+/** Alias (User Manual Name) for VADC_G3_CHCTR2.
+* To use register names with standard convension, please use VADC_G3_CHCTR2.
+*/
+#define VADC_G3CHCTR2 (VADC_G3_CHCTR2)
+
+/** \brief 120C, Group, Channel Ctrl. Reg. */
+#define VADC_G3_CHCTR3 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF002120Cu)
+
+/** Alias (User Manual Name) for VADC_G3_CHCTR3.
+* To use register names with standard convension, please use VADC_G3_CHCTR3.
+*/
+#define VADC_G3CHCTR3 (VADC_G3_CHCTR3)
+
+/** \brief 1210, Group, Channel Ctrl. Reg. */
+#define VADC_G3_CHCTR4 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0021210u)
+
+/** Alias (User Manual Name) for VADC_G3_CHCTR4.
+* To use register names with standard convension, please use VADC_G3_CHCTR4.
+*/
+#define VADC_G3CHCTR4 (VADC_G3_CHCTR4)
+
+/** \brief 1214, Group, Channel Ctrl. Reg. */
+#define VADC_G3_CHCTR5 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0021214u)
+
+/** Alias (User Manual Name) for VADC_G3_CHCTR5.
+* To use register names with standard convension, please use VADC_G3_CHCTR5.
+*/
+#define VADC_G3CHCTR5 (VADC_G3_CHCTR5)
+
+/** \brief 1218, Group, Channel Ctrl. Reg. */
+#define VADC_G3_CHCTR6 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0021218u)
+
+/** Alias (User Manual Name) for VADC_G3_CHCTR6.
+* To use register names with standard convension, please use VADC_G3_CHCTR6.
+*/
+#define VADC_G3CHCTR6 (VADC_G3_CHCTR6)
+
+/** \brief 121C, Group, Channel Ctrl. Reg. */
+#define VADC_G3_CHCTR7 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF002121Cu)
+
+/** Alias (User Manual Name) for VADC_G3_CHCTR7.
+* To use register names with standard convension, please use VADC_G3_CHCTR7.
+*/
+#define VADC_G3CHCTR7 (VADC_G3_CHCTR7)
+
+/** \brief 1220, Group, Channel Ctrl. Reg. */
+#define VADC_G3_CHCTR8 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0021220u)
+
+/** Alias (User Manual Name) for VADC_G3_CHCTR8.
+* To use register names with standard convension, please use VADC_G3_CHCTR8.
+*/
+#define VADC_G3CHCTR8 (VADC_G3_CHCTR8)
+
+/** \brief 1224, Group, Channel Ctrl. Reg. */
+#define VADC_G3_CHCTR9 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_CHCTR*)0xF0021224u)
+
+/** Alias (User Manual Name) for VADC_G3_CHCTR9.
+* To use register names with standard convension, please use VADC_G3_CHCTR9.
+*/
+#define VADC_G3CHCTR9 (VADC_G3_CHCTR9)
+
+/** \brief 11F0, External Multiplexer Control Register, Group x */
+#define VADC_G3_EMUXCTR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_EMUXCTR*)0xF00211F0u)
+
+/** Alias (User Manual Name) for VADC_G3_EMUXCTR.
+* To use register names with standard convension, please use VADC_G3_EMUXCTR.
+*/
+#define VADC_G3EMUXCTR (VADC_G3_EMUXCTR)
+
+/** \brief 10A0, Input Class Register */
+#define VADC_G3_ICLASS0 /*lint --e(923)*/ (*(volatile Ifx_VADC_ICLASS*)0xF00210A0u)
+
+/** Alias (User Manual Name) for VADC_G3_ICLASS0.
+* To use register names with standard convension, please use VADC_G3_ICLASS0.
+*/
+#define VADC_G3ICLASS0 (VADC_G3_ICLASS0)
+
+/** \brief 10A4, Input Class Register */
+#define VADC_G3_ICLASS1 /*lint --e(923)*/ (*(volatile Ifx_VADC_ICLASS*)0xF00210A4u)
+
+/** Alias (User Manual Name) for VADC_G3_ICLASS1.
+* To use register names with standard convension, please use VADC_G3_ICLASS1.
+*/
+#define VADC_G3ICLASS1 (VADC_G3_ICLASS1)
+
+/** \brief 110C, Queue 0 Register 0, Group */
+#define VADC_G3_Q0R0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_Q0R0*)0xF002110Cu)
+
+/** Alias (User Manual Name) for VADC_G3_Q0R0.
+* To use register names with standard convension, please use VADC_G3_Q0R0.
+*/
+#define VADC_G3Q0R0 (VADC_G3_Q0R0)
+
+/** \brief 1110, Queue 0 Input Register, Group */
+#define VADC_G3_QBUR0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_QBUR0*)0xF0021110u)
+
+/** Alias (User Manual Name) for VADC_G3_QBUR0.
+* To use register names with standard convension, please use VADC_G3_QBUR0.
+*/
+#define VADC_G3QBUR0 (VADC_G3_QBUR0)
+
+/** \brief 1100, Queue 0 Source Control Register, Group */
+#define VADC_G3_QCTRL0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_QCTRL0*)0xF0021100u)
+
+/** Alias (User Manual Name) for VADC_G3_QCTRL0.
+* To use register names with standard convension, please use VADC_G3_QCTRL0.
+*/
+#define VADC_G3QCTRL0 (VADC_G3_QCTRL0)
+
+/** \brief 1110, Queue 0 Input Register, Group */
+#define VADC_G3_QINR0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_QINR0*)0xF0021110u)
+
+/** Alias (User Manual Name) for VADC_G3_QINR0.
+* To use register names with standard convension, please use VADC_G3_QINR0.
+*/
+#define VADC_G3QINR0 (VADC_G3_QINR0)
+
+/** \brief 1104, Queue 0 Mode Register, Group */
+#define VADC_G3_QMR0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_QMR0*)0xF0021104u)
+
+/** Alias (User Manual Name) for VADC_G3_QMR0.
+* To use register names with standard convension, please use VADC_G3_QMR0.
+*/
+#define VADC_G3QMR0 (VADC_G3_QMR0)
+
+/** \brief 1108, Queue 0 Status Register, Group */
+#define VADC_G3_QSR0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_QSR0*)0xF0021108u)
+
+/** Alias (User Manual Name) for VADC_G3_QSR0.
+* To use register names with standard convension, please use VADC_G3_QSR0.
+*/
+#define VADC_G3QSR0 (VADC_G3_QSR0)
+
+/** \brief 1280, Group Result Control Reg. */
+#define VADC_G3_RCR0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0021280u)
+
+/** Alias (User Manual Name) for VADC_G3_RCR0.
+* To use register names with standard convension, please use VADC_G3_RCR0.
+*/
+#define VADC_G3RCR0 (VADC_G3_RCR0)
+
+/** \brief 1284, Group Result Control Reg. */
+#define VADC_G3_RCR1 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0021284u)
+
+/** Alias (User Manual Name) for VADC_G3_RCR1.
+* To use register names with standard convension, please use VADC_G3_RCR1.
+*/
+#define VADC_G3RCR1 (VADC_G3_RCR1)
+
+/** \brief 12A8, Group Result Control Reg. */
+#define VADC_G3_RCR10 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF00212A8u)
+
+/** Alias (User Manual Name) for VADC_G3_RCR10.
+* To use register names with standard convension, please use VADC_G3_RCR10.
+*/
+#define VADC_G3RCR10 (VADC_G3_RCR10)
+
+/** \brief 12AC, Group Result Control Reg. */
+#define VADC_G3_RCR11 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF00212ACu)
+
+/** Alias (User Manual Name) for VADC_G3_RCR11.
+* To use register names with standard convension, please use VADC_G3_RCR11.
+*/
+#define VADC_G3RCR11 (VADC_G3_RCR11)
+
+/** \brief 12B0, Group Result Control Reg. */
+#define VADC_G3_RCR12 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF00212B0u)
+
+/** Alias (User Manual Name) for VADC_G3_RCR12.
+* To use register names with standard convension, please use VADC_G3_RCR12.
+*/
+#define VADC_G3RCR12 (VADC_G3_RCR12)
+
+/** \brief 12B4, Group Result Control Reg. */
+#define VADC_G3_RCR13 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF00212B4u)
+
+/** Alias (User Manual Name) for VADC_G3_RCR13.
+* To use register names with standard convension, please use VADC_G3_RCR13.
+*/
+#define VADC_G3RCR13 (VADC_G3_RCR13)
+
+/** \brief 12B8, Group Result Control Reg. */
+#define VADC_G3_RCR14 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF00212B8u)
+
+/** Alias (User Manual Name) for VADC_G3_RCR14.
+* To use register names with standard convension, please use VADC_G3_RCR14.
+*/
+#define VADC_G3RCR14 (VADC_G3_RCR14)
+
+/** \brief 12BC, Group Result Control Reg. */
+#define VADC_G3_RCR15 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF00212BCu)
+
+/** Alias (User Manual Name) for VADC_G3_RCR15.
+* To use register names with standard convension, please use VADC_G3_RCR15.
+*/
+#define VADC_G3RCR15 (VADC_G3_RCR15)
+
+/** \brief 1288, Group Result Control Reg. */
+#define VADC_G3_RCR2 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0021288u)
+
+/** Alias (User Manual Name) for VADC_G3_RCR2.
+* To use register names with standard convension, please use VADC_G3_RCR2.
+*/
+#define VADC_G3RCR2 (VADC_G3_RCR2)
+
+/** \brief 128C, Group Result Control Reg. */
+#define VADC_G3_RCR3 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF002128Cu)
+
+/** Alias (User Manual Name) for VADC_G3_RCR3.
+* To use register names with standard convension, please use VADC_G3_RCR3.
+*/
+#define VADC_G3RCR3 (VADC_G3_RCR3)
+
+/** \brief 1290, Group Result Control Reg. */
+#define VADC_G3_RCR4 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0021290u)
+
+/** Alias (User Manual Name) for VADC_G3_RCR4.
+* To use register names with standard convension, please use VADC_G3_RCR4.
+*/
+#define VADC_G3RCR4 (VADC_G3_RCR4)
+
+/** \brief 1294, Group Result Control Reg. */
+#define VADC_G3_RCR5 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0021294u)
+
+/** Alias (User Manual Name) for VADC_G3_RCR5.
+* To use register names with standard convension, please use VADC_G3_RCR5.
+*/
+#define VADC_G3RCR5 (VADC_G3_RCR5)
+
+/** \brief 1298, Group Result Control Reg. */
+#define VADC_G3_RCR6 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF0021298u)
+
+/** Alias (User Manual Name) for VADC_G3_RCR6.
+* To use register names with standard convension, please use VADC_G3_RCR6.
+*/
+#define VADC_G3RCR6 (VADC_G3_RCR6)
+
+/** \brief 129C, Group Result Control Reg. */
+#define VADC_G3_RCR7 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF002129Cu)
+
+/** Alias (User Manual Name) for VADC_G3_RCR7.
+* To use register names with standard convension, please use VADC_G3_RCR7.
+*/
+#define VADC_G3RCR7 (VADC_G3_RCR7)
+
+/** \brief 12A0, Group Result Control Reg. */
+#define VADC_G3_RCR8 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF00212A0u)
+
+/** Alias (User Manual Name) for VADC_G3_RCR8.
+* To use register names with standard convension, please use VADC_G3_RCR8.
+*/
+#define VADC_G3RCR8 (VADC_G3_RCR8)
+
+/** \brief 12A4, Group Result Control Reg. */
+#define VADC_G3_RCR9 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RCR*)0xF00212A4u)
+
+/** Alias (User Manual Name) for VADC_G3_RCR9.
+* To use register names with standard convension, please use VADC_G3_RCR9.
+*/
+#define VADC_G3RCR9 (VADC_G3_RCR9)
+
+/** \brief 1194, Result Event Flag Clear Register, Group */
+#define VADC_G3_REFCLR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_REFCLR*)0xF0021194u)
+
+/** Alias (User Manual Name) for VADC_G3_REFCLR.
+* To use register names with standard convension, please use VADC_G3_REFCLR.
+*/
+#define VADC_G3REFCLR (VADC_G3_REFCLR)
+
+/** \brief 1184, Result Event Flag Register, Group */
+#define VADC_G3_REFLAG /*lint --e(923)*/ (*(volatile Ifx_VADC_G_REFLAG*)0xF0021184u)
+
+/** Alias (User Manual Name) for VADC_G3_REFLAG.
+* To use register names with standard convension, please use VADC_G3_REFLAG.
+*/
+#define VADC_G3REFLAG (VADC_G3_REFLAG)
+
+/** \brief 1300, Group Result Register */
+#define VADC_G3_RES0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0021300u)
+
+/** Alias (User Manual Name) for VADC_G3_RES0.
+* To use register names with standard convension, please use VADC_G3_RES0.
+*/
+#define VADC_G3RES0 (VADC_G3_RES0)
+
+/** \brief 1304, Group Result Register */
+#define VADC_G3_RES1 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0021304u)
+
+/** Alias (User Manual Name) for VADC_G3_RES1.
+* To use register names with standard convension, please use VADC_G3_RES1.
+*/
+#define VADC_G3RES1 (VADC_G3_RES1)
+
+/** \brief 1328, Group Result Register */
+#define VADC_G3_RES10 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0021328u)
+
+/** Alias (User Manual Name) for VADC_G3_RES10.
+* To use register names with standard convension, please use VADC_G3_RES10.
+*/
+#define VADC_G3RES10 (VADC_G3_RES10)
+
+/** \brief 132C, Group Result Register */
+#define VADC_G3_RES11 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF002132Cu)
+
+/** Alias (User Manual Name) for VADC_G3_RES11.
+* To use register names with standard convension, please use VADC_G3_RES11.
+*/
+#define VADC_G3RES11 (VADC_G3_RES11)
+
+/** \brief 1330, Group Result Register */
+#define VADC_G3_RES12 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0021330u)
+
+/** Alias (User Manual Name) for VADC_G3_RES12.
+* To use register names with standard convension, please use VADC_G3_RES12.
+*/
+#define VADC_G3RES12 (VADC_G3_RES12)
+
+/** \brief 1334, Group Result Register */
+#define VADC_G3_RES13 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0021334u)
+
+/** Alias (User Manual Name) for VADC_G3_RES13.
+* To use register names with standard convension, please use VADC_G3_RES13.
+*/
+#define VADC_G3RES13 (VADC_G3_RES13)
+
+/** \brief 1338, Group Result Register */
+#define VADC_G3_RES14 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0021338u)
+
+/** Alias (User Manual Name) for VADC_G3_RES14.
+* To use register names with standard convension, please use VADC_G3_RES14.
+*/
+#define VADC_G3RES14 (VADC_G3_RES14)
+
+/** \brief 133C, Group Result Register */
+#define VADC_G3_RES15 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF002133Cu)
+
+/** Alias (User Manual Name) for VADC_G3_RES15.
+* To use register names with standard convension, please use VADC_G3_RES15.
+*/
+#define VADC_G3RES15 (VADC_G3_RES15)
+
+/** \brief 1308, Group Result Register */
+#define VADC_G3_RES2 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0021308u)
+
+/** Alias (User Manual Name) for VADC_G3_RES2.
+* To use register names with standard convension, please use VADC_G3_RES2.
+*/
+#define VADC_G3RES2 (VADC_G3_RES2)
+
+/** \brief 130C, Group Result Register */
+#define VADC_G3_RES3 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF002130Cu)
+
+/** Alias (User Manual Name) for VADC_G3_RES3.
+* To use register names with standard convension, please use VADC_G3_RES3.
+*/
+#define VADC_G3RES3 (VADC_G3_RES3)
+
+/** \brief 1310, Group Result Register */
+#define VADC_G3_RES4 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0021310u)
+
+/** Alias (User Manual Name) for VADC_G3_RES4.
+* To use register names with standard convension, please use VADC_G3_RES4.
+*/
+#define VADC_G3RES4 (VADC_G3_RES4)
+
+/** \brief 1314, Group Result Register */
+#define VADC_G3_RES5 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0021314u)
+
+/** Alias (User Manual Name) for VADC_G3_RES5.
+* To use register names with standard convension, please use VADC_G3_RES5.
+*/
+#define VADC_G3RES5 (VADC_G3_RES5)
+
+/** \brief 1318, Group Result Register */
+#define VADC_G3_RES6 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0021318u)
+
+/** Alias (User Manual Name) for VADC_G3_RES6.
+* To use register names with standard convension, please use VADC_G3_RES6.
+*/
+#define VADC_G3RES6 (VADC_G3_RES6)
+
+/** \brief 131C, Group Result Register */
+#define VADC_G3_RES7 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF002131Cu)
+
+/** Alias (User Manual Name) for VADC_G3_RES7.
+* To use register names with standard convension, please use VADC_G3_RES7.
+*/
+#define VADC_G3RES7 (VADC_G3_RES7)
+
+/** \brief 1320, Group Result Register */
+#define VADC_G3_RES8 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0021320u)
+
+/** Alias (User Manual Name) for VADC_G3_RES8.
+* To use register names with standard convension, please use VADC_G3_RES8.
+*/
+#define VADC_G3RES8 (VADC_G3_RES8)
+
+/** \brief 1324, Group Result Register */
+#define VADC_G3_RES9 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RES*)0xF0021324u)
+
+/** Alias (User Manual Name) for VADC_G3_RES9.
+* To use register names with standard convension, please use VADC_G3_RES9.
+*/
+#define VADC_G3RES9 (VADC_G3_RES9)
+
+/** \brief 1380, Group Result Reg., Debug */
+#define VADC_G3_RESD0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0021380u)
+
+/** Alias (User Manual Name) for VADC_G3_RESD0.
+* To use register names with standard convension, please use VADC_G3_RESD0.
+*/
+#define VADC_G3RESD0 (VADC_G3_RESD0)
+
+/** \brief 1384, Group Result Reg., Debug */
+#define VADC_G3_RESD1 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0021384u)
+
+/** Alias (User Manual Name) for VADC_G3_RESD1.
+* To use register names with standard convension, please use VADC_G3_RESD1.
+*/
+#define VADC_G3RESD1 (VADC_G3_RESD1)
+
+/** \brief 13A8, Group Result Reg., Debug */
+#define VADC_G3_RESD10 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF00213A8u)
+
+/** Alias (User Manual Name) for VADC_G3_RESD10.
+* To use register names with standard convension, please use VADC_G3_RESD10.
+*/
+#define VADC_G3RESD10 (VADC_G3_RESD10)
+
+/** \brief 13AC, Group Result Reg., Debug */
+#define VADC_G3_RESD11 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF00213ACu)
+
+/** Alias (User Manual Name) for VADC_G3_RESD11.
+* To use register names with standard convension, please use VADC_G3_RESD11.
+*/
+#define VADC_G3RESD11 (VADC_G3_RESD11)
+
+/** \brief 13B0, Group Result Reg., Debug */
+#define VADC_G3_RESD12 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF00213B0u)
+
+/** Alias (User Manual Name) for VADC_G3_RESD12.
+* To use register names with standard convension, please use VADC_G3_RESD12.
+*/
+#define VADC_G3RESD12 (VADC_G3_RESD12)
+
+/** \brief 13B4, Group Result Reg., Debug */
+#define VADC_G3_RESD13 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF00213B4u)
+
+/** Alias (User Manual Name) for VADC_G3_RESD13.
+* To use register names with standard convension, please use VADC_G3_RESD13.
+*/
+#define VADC_G3RESD13 (VADC_G3_RESD13)
+
+/** \brief 13B8, Group Result Reg., Debug */
+#define VADC_G3_RESD14 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF00213B8u)
+
+/** Alias (User Manual Name) for VADC_G3_RESD14.
+* To use register names with standard convension, please use VADC_G3_RESD14.
+*/
+#define VADC_G3RESD14 (VADC_G3_RESD14)
+
+/** \brief 13BC, Group Result Reg., Debug */
+#define VADC_G3_RESD15 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF00213BCu)
+
+/** Alias (User Manual Name) for VADC_G3_RESD15.
+* To use register names with standard convension, please use VADC_G3_RESD15.
+*/
+#define VADC_G3RESD15 (VADC_G3_RESD15)
+
+/** \brief 1388, Group Result Reg., Debug */
+#define VADC_G3_RESD2 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0021388u)
+
+/** Alias (User Manual Name) for VADC_G3_RESD2.
+* To use register names with standard convension, please use VADC_G3_RESD2.
+*/
+#define VADC_G3RESD2 (VADC_G3_RESD2)
+
+/** \brief 138C, Group Result Reg., Debug */
+#define VADC_G3_RESD3 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF002138Cu)
+
+/** Alias (User Manual Name) for VADC_G3_RESD3.
+* To use register names with standard convension, please use VADC_G3_RESD3.
+*/
+#define VADC_G3RESD3 (VADC_G3_RESD3)
+
+/** \brief 1390, Group Result Reg., Debug */
+#define VADC_G3_RESD4 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0021390u)
+
+/** Alias (User Manual Name) for VADC_G3_RESD4.
+* To use register names with standard convension, please use VADC_G3_RESD4.
+*/
+#define VADC_G3RESD4 (VADC_G3_RESD4)
+
+/** \brief 1394, Group Result Reg., Debug */
+#define VADC_G3_RESD5 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0021394u)
+
+/** Alias (User Manual Name) for VADC_G3_RESD5.
+* To use register names with standard convension, please use VADC_G3_RESD5.
+*/
+#define VADC_G3RESD5 (VADC_G3_RESD5)
+
+/** \brief 1398, Group Result Reg., Debug */
+#define VADC_G3_RESD6 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF0021398u)
+
+/** Alias (User Manual Name) for VADC_G3_RESD6.
+* To use register names with standard convension, please use VADC_G3_RESD6.
+*/
+#define VADC_G3RESD6 (VADC_G3_RESD6)
+
+/** \brief 139C, Group Result Reg., Debug */
+#define VADC_G3_RESD7 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF002139Cu)
+
+/** Alias (User Manual Name) for VADC_G3_RESD7.
+* To use register names with standard convension, please use VADC_G3_RESD7.
+*/
+#define VADC_G3RESD7 (VADC_G3_RESD7)
+
+/** \brief 13A0, Group Result Reg., Debug */
+#define VADC_G3_RESD8 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF00213A0u)
+
+/** Alias (User Manual Name) for VADC_G3_RESD8.
+* To use register names with standard convension, please use VADC_G3_RESD8.
+*/
+#define VADC_G3RESD8 (VADC_G3_RESD8)
+
+/** \brief 13A4, Group Result Reg., Debug */
+#define VADC_G3_RESD9 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RESD*)0xF00213A4u)
+
+/** Alias (User Manual Name) for VADC_G3_RESD9.
+* To use register names with standard convension, please use VADC_G3_RESD9.
+*/
+#define VADC_G3RESD9 (VADC_G3_RESD9)
+
+/** \brief 11B0, Result Event Node Pointer Register 0, Group */
+#define VADC_G3_REVNP0 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_REVNP0*)0xF00211B0u)
+
+/** Alias (User Manual Name) for VADC_G3_REVNP0.
+* To use register names with standard convension, please use VADC_G3_REVNP0.
+*/
+#define VADC_G3REVNP0 (VADC_G3_REVNP0)
+
+/** \brief 11B4, Result Event Node Pointer Register 1, Group */
+#define VADC_G3_REVNP1 /*lint --e(923)*/ (*(volatile Ifx_VADC_G_REVNP1*)0xF00211B4u)
+
+/** Alias (User Manual Name) for VADC_G3_REVNP1.
+* To use register names with standard convension, please use VADC_G3_REVNP1.
+*/
+#define VADC_G3REVNP1 (VADC_G3_REVNP1)
+
+/** \brief 108C, Result Assignment Register, Group */
+#define VADC_G3_RRASS /*lint --e(923)*/ (*(volatile Ifx_VADC_G_RRASS*)0xF002108Cu)
+
+/** Alias (User Manual Name) for VADC_G3_RRASS.
+* To use register names with standard convension, please use VADC_G3_RRASS.
+*/
+#define VADC_G3RRASS (VADC_G3_RRASS)
+
+/** \brief 1198, Source Event Flag Clear Register, Group */
+#define VADC_G3_SEFCLR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_SEFCLR*)0xF0021198u)
+
+/** Alias (User Manual Name) for VADC_G3_SEFCLR.
+* To use register names with standard convension, please use VADC_G3_SEFCLR.
+*/
+#define VADC_G3SEFCLR (VADC_G3_SEFCLR)
+
+/** \brief 1188, Source Event Flag Register, Group */
+#define VADC_G3_SEFLAG /*lint --e(923)*/ (*(volatile Ifx_VADC_G_SEFLAG*)0xF0021188u)
+
+/** Alias (User Manual Name) for VADC_G3_SEFLAG.
+* To use register names with standard convension, please use VADC_G3_SEFLAG.
+*/
+#define VADC_G3SEFLAG (VADC_G3_SEFLAG)
+
+/** \brief 11C0, Source Event Node Pointer Register, Group */
+#define VADC_G3_SEVNP /*lint --e(923)*/ (*(volatile Ifx_VADC_G_SEVNP*)0xF00211C0u)
+
+/** Alias (User Manual Name) for VADC_G3_SEVNP.
+* To use register names with standard convension, please use VADC_G3_SEVNP.
+*/
+#define VADC_G3SEVNP (VADC_G3_SEVNP)
+
+/** \brief 11C8, Service Request Software Activation Trigger, Group */
+#define VADC_G3_SRACT /*lint --e(923)*/ (*(volatile Ifx_VADC_G_SRACT*)0xF00211C8u)
+
+/** Alias (User Manual Name) for VADC_G3_SRACT.
+* To use register names with standard convension, please use VADC_G3_SRACT.
+*/
+#define VADC_G3SRACT (VADC_G3_SRACT)
+
+/** \brief 10C0, Synchronization Control Register, Group */
+#define VADC_G3_SYNCTR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_SYNCTR*)0xF00210C0u)
+
+/** Alias (User Manual Name) for VADC_G3_SYNCTR.
+* To use register names with standard convension, please use VADC_G3_SYNCTR.
+*/
+#define VADC_G3SYNCTR (VADC_G3_SYNCTR)
+
+/** \brief 11F8, Valid Flag Register, Group */
+#define VADC_G3_VFR /*lint --e(923)*/ (*(volatile Ifx_VADC_G_VFR*)0xF00211F8u)
+
+/** Alias (User Manual Name) for VADC_G3_VFR.
+* To use register names with standard convension, please use VADC_G3_VFR.
+*/
+#define VADC_G3VFR (VADC_G3_VFR)
+
+/** \brief B8, Global Boundary Select Register */
+#define VADC_GLOBBOUND /*lint --e(923)*/ (*(volatile Ifx_VADC_GLOBBOUND*)0xF00200B8u)
+
+/** \brief 80, Global Configuration Register */
+#define VADC_GLOBCFG /*lint --e(923)*/ (*(volatile Ifx_VADC_GLOBCFG*)0xF0020080u)
+
+/** \brief E0, Global Event Flag Register */
+#define VADC_GLOBEFLAG /*lint --e(923)*/ (*(volatile Ifx_VADC_GLOBEFLAG*)0xF00200E0u)
+
+/** \brief 140, Global Event Node Pointer Register */
+#define VADC_GLOBEVNP /*lint --e(923)*/ (*(volatile Ifx_VADC_GLOBEVNP*)0xF0020140u)
+
+/** \brief A0, Input Class Register */
+#define VADC_GLOBICLASS0 /*lint --e(923)*/ (*(volatile Ifx_VADC_ICLASS*)0xF00200A0u)
+
+/** \brief A4, Input Class Register */
+#define VADC_GLOBICLASS1 /*lint --e(923)*/ (*(volatile Ifx_VADC_ICLASS*)0xF00200A4u)
+
+/** \brief 280, Global Result Control Register */
+#define VADC_GLOBRCR /*lint --e(923)*/ (*(volatile Ifx_VADC_GLOBRCR*)0xF0020280u)
+
+/** \brief 300, Global Result Register */
+#define VADC_GLOBRES /*lint --e(923)*/ (*(volatile Ifx_VADC_GLOBRES*)0xF0020300u)
+
+/** \brief 380, Global Result Register, Debug */
+#define VADC_GLOBRESD /*lint --e(923)*/ (*(volatile Ifx_VADC_GLOBRESD*)0xF0020380u)
+
+/** \brief 160, Global Test Functions Register */
+#define VADC_GLOBTF /*lint --e(923)*/ (*(volatile Ifx_VADC_GLOBTF*)0xF0020160u)
+
+/** \brief 8, Module Identification Register */
+#define VADC_ID /*lint --e(923)*/ (*(volatile Ifx_VADC_ID*)0xF0020008u)
+
+/** \brief 34, Kernel Reset Register 0 */
+#define VADC_KRST0 /*lint --e(923)*/ (*(volatile Ifx_VADC_KRST0*)0xF0020034u)
+
+/** \brief 30, Kernel Reset Register 1 */
+#define VADC_KRST1 /*lint --e(923)*/ (*(volatile Ifx_VADC_KRST1*)0xF0020030u)
+
+/** \brief 2C, Kernel Reset Status Clear Register */
+#define VADC_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_VADC_KRSTCLR*)0xF002002Cu)
+
+/** \brief 28, OCDS Control and Status Register */
+#define VADC_OCS /*lint --e(923)*/ (*(volatile Ifx_VADC_OCS*)0xF0020028u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXVADC_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxVadc_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxVadc_regdef.h
new file mode 100644
index 0000000..f6b5be5
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxVadc_regdef.h
@@ -0,0 +1,1565 @@
+/**
+ * \file IfxVadc_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Vadc Vadc
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Vadc_Bitfields Bitfields
+ * \ingroup IfxLld_Vadc
+ *
+ * \defgroup IfxLld_Vadc_union Union
+ * \ingroup IfxLld_Vadc
+ *
+ * \defgroup IfxLld_Vadc_struct Struct
+ * \ingroup IfxLld_Vadc
+ *
+ */
+#ifndef IFXVADC_REGDEF_H
+#define IFXVADC_REGDEF_H 1
+/******************************************************************************/
+#if defined (__TASKING__)
+#pragma warning 586
+#endif
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Vadc_Bitfields
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef struct _Ifx_VADC_ACCEN0_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_VADC_ACCEN0_Bits;
+
+/** \brief Access Protection Register */
+typedef struct _Ifx_VADC_ACCPROT0_Bits
+{
+ unsigned int APC0:1; /**< \brief [0:0] Access Protection Channel Control, Group 0 - 3 (rw) */
+ unsigned int APC1:1; /**< \brief [1:1] Access Protection Channel Control, Group 0 - 3 (rw) */
+ unsigned int APC2:1; /**< \brief [2:2] Access Protection Channel Control, Group 0 - 3 (rw) */
+ unsigned int APC3:1; /**< \brief [3:3] Access Protection Channel Control, Group 0 - 3 (rw) */
+ unsigned int reserved_4:11; /**< \brief \internal Reserved */
+ unsigned int APEM:1; /**< \brief [15:15] Access Protection External Multiplexer (rw) */
+ unsigned int API0:1; /**< \brief [16:16] Access Protection Initialization, Group 0 - 3 (rw) */
+ unsigned int API1:1; /**< \brief [17:17] Access Protection Initialization, Group 0 - 3 (rw) */
+ unsigned int API2:1; /**< \brief [18:18] Access Protection Initialization, Group 0 - 3 (rw) */
+ unsigned int API3:1; /**< \brief [19:19] Access Protection Initialization, Group 0 - 3 (rw) */
+ unsigned int reserved_20:11; /**< \brief \internal Reserved */
+ unsigned int APGC:1; /**< \brief [31:31] Access Protection Global Configuration (rw) */
+} Ifx_VADC_ACCPROT0_Bits;
+
+/** \brief Access Protection Register */
+typedef struct _Ifx_VADC_ACCPROT1_Bits
+{
+ unsigned int APS0:1; /**< \brief [0:0] Access Protection Service Request, Group 0 - 3 (rw) */
+ unsigned int APS1:1; /**< \brief [1:1] Access Protection Service Request, Group 0 - 3 (rw) */
+ unsigned int APS2:1; /**< \brief [2:2] Access Protection Service Request, Group 0 - 3 (rw) */
+ unsigned int APS3:1; /**< \brief [3:3] Access Protection Service Request, Group 0 - 3 (rw) */
+ unsigned int reserved_4:11; /**< \brief \internal Reserved */
+ unsigned int APTF:1; /**< \brief [15:15] Access Protection Test Function (rw) */
+ unsigned int APR0:1; /**< \brief [16:16] Access Protection Result Registers, Group 0 - 3 (rw) */
+ unsigned int APR1:1; /**< \brief [17:17] Access Protection Result Registers, Group 0 - 3 (rw) */
+ unsigned int APR2:1; /**< \brief [18:18] Access Protection Result Registers, Group 0 - 3 (rw) */
+ unsigned int APR3:1; /**< \brief [19:19] Access Protection Result Registers, Group 0 - 3 (rw) */
+ unsigned int reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_VADC_ACCPROT1_Bits;
+
+/** \brief Background Request Source Control Register */
+typedef struct _Ifx_VADC_BRSCTRL_Bits
+{
+ unsigned int SRCRESREG:4; /**< \brief [3:0] Source-specific Result Register (rw) */
+ unsigned int reserved_4:4; /**< \brief \internal Reserved */
+ unsigned int XTSEL:4; /**< \brief [11:8] External Trigger Input Selection (rw) */
+ unsigned int XTLVL:1; /**< \brief [12:12] External Trigger Level (rh) */
+ unsigned int XTMODE:2; /**< \brief [14:13] Trigger Operating Mode (rw) */
+ unsigned int XTWC:1; /**< \brief [15:15] Write Control for Trigger Configuration (w) */
+ unsigned int GTSEL:4; /**< \brief [19:16] Gate Input Selection (rw) */
+ unsigned int GTLVL:1; /**< \brief [20:20] Gate Input Level (rh) */
+ unsigned int reserved_21:2; /**< \brief \internal Reserved */
+ unsigned int GTWC:1; /**< \brief [23:23] Write Control for Gate Configuration (w) */
+ unsigned int reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_VADC_BRSCTRL_Bits;
+
+/** \brief Background Request Source Mode Register */
+typedef struct _Ifx_VADC_BRSMR_Bits
+{
+ unsigned int ENGT:2; /**< \brief [1:0] Enable Gate (rw) */
+ unsigned int ENTR:1; /**< \brief [2:2] Enable External Trigger (rw) */
+ unsigned int ENSI:1; /**< \brief [3:3] Enable Source Interrupt (rw) */
+ unsigned int SCAN:1; /**< \brief [4:4] Autoscan Enable (rw) */
+ unsigned int LDM:1; /**< \brief [5:5] Autoscan Source Load Event Mode (rw) */
+ unsigned int reserved_6:1; /**< \brief \internal Reserved */
+ unsigned int REQGT:1; /**< \brief [7:7] Request Gate Level (rh) */
+ unsigned int CLRPND:1; /**< \brief [8:8] Clear Pending Bits (w) */
+ unsigned int LDEV:1; /**< \brief [9:9] Generate Load Event (w) */
+ unsigned int reserved_10:6; /**< \brief \internal Reserved */
+ unsigned int RPTDIS:1; /**< \brief [16:16] Repeat Disable (rw) */
+ unsigned int reserved_17:15; /**< \brief \internal Reserved */
+} Ifx_VADC_BRSMR_Bits;
+
+/** \brief Background Request Source Pending Register, Group */
+typedef struct _Ifx_VADC_BRSPND_Bits
+{
+ unsigned int CHPNDGy:32; /**< \brief [31:0] Channels Pending Group x (rwh) */
+} Ifx_VADC_BRSPND_Bits;
+
+/** \brief Background Request Source Channel Select Register, Group */
+typedef struct _Ifx_VADC_BRSSEL_Bits
+{
+ unsigned int CHSELGy:32; /**< \brief [31:0] Channel Selection Group x (rwh) */
+} Ifx_VADC_BRSSEL_Bits;
+
+/** \brief Clock Control Register */
+typedef struct _Ifx_VADC_CLC_Bits
+{
+ unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
+ unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (r) */
+ unsigned int reserved_2:1; /**< \brief \internal Reserved */
+ unsigned int EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control (rw) */
+ unsigned int reserved_4:28; /**< \brief \internal Reserved */
+} Ifx_VADC_CLC_Bits;
+
+/** \brief External Multiplexer Select Register */
+typedef struct _Ifx_VADC_EMUXSEL_Bits
+{
+ unsigned int EMUXGRP0:4; /**< \brief [3:0] External Multiplexer Group for Interface x (rw) */
+ unsigned int EMUXGRP1:4; /**< \brief [7:4] External Multiplexer Group for Interface x (rw) */
+ unsigned int reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_VADC_EMUXSEL_Bits;
+
+/** \brief Alias Register, Group */
+typedef struct _Ifx_VADC_G_ALIAS_Bits
+{
+ unsigned int ALIAS0:5; /**< \brief [4:0] Alias Value for CH0 Conversion Requests (rw) */
+ unsigned int reserved_5:3; /**< \brief \internal Reserved */
+ unsigned int ALIAS1:5; /**< \brief [12:8] Alias Value for CH1 Conversion Requests (rw) */
+ unsigned int reserved_13:19; /**< \brief \internal Reserved */
+} Ifx_VADC_G_ALIAS_Bits;
+
+/** \brief Arbitration Configuration Register, Group */
+typedef struct _Ifx_VADC_G_ARBCFG_Bits
+{
+ unsigned int ANONC:2; /**< \brief [1:0] Analog Converter Control (rw) */
+ unsigned int reserved_2:2; /**< \brief \internal Reserved */
+ unsigned int ARBRND:2; /**< \brief [5:4] Arbitration Round Length (rw) */
+ unsigned int reserved_6:1; /**< \brief \internal Reserved */
+ unsigned int ARBM:1; /**< \brief [7:7] Arbitration Mode (rw) */
+ unsigned int reserved_8:8; /**< \brief \internal Reserved */
+ unsigned int ANONS:2; /**< \brief [17:16] Analog Converter Control Status (rh) */
+ unsigned int CSRC:2; /**< \brief [19:18] Currently Converted Request Source (rh) */
+ unsigned int CHNR:5; /**< \brief [24:20] Channel Number (rh) */
+ unsigned int SYNRUN:1; /**< \brief [25:25] Synchronous Conversion Running (rh) */
+ unsigned int reserved_26:2; /**< \brief \internal Reserved */
+ unsigned int CAL:1; /**< \brief [28:28] Start-Up Calibration Active Indication (rh) */
+ unsigned int CALS:1; /**< \brief [29:29] Start-Up Calibration Started (rh) */
+ unsigned int BUSY:1; /**< \brief [30:30] Converter Busy Flag (rh) */
+ unsigned int SAMPLE:1; /**< \brief [31:31] Sample Phase Flag (rh) */
+} Ifx_VADC_G_ARBCFG_Bits;
+
+/** \brief Arbitration Priority Register, Group */
+typedef struct _Ifx_VADC_G_ARBPR_Bits
+{
+ unsigned int PRIO0:2; /**< \brief [1:0] Priority of Request Source x (rw) */
+ unsigned int reserved_2:1; /**< \brief \internal Reserved */
+ unsigned int CSM0:1; /**< \brief [3:3] Conversion Start Mode of Request Source x (rw) */
+ unsigned int PRIO1:2; /**< \brief [5:4] Priority of Request Source x (rw) */
+ unsigned int reserved_6:1; /**< \brief \internal Reserved */
+ unsigned int CSM1:1; /**< \brief [7:7] Conversion Start Mode of Request Source x (rw) */
+ unsigned int PRIO2:2; /**< \brief [9:8] Priority of Request Source x (rw) */
+ unsigned int reserved_10:1; /**< \brief \internal Reserved */
+ unsigned int CSM2:1; /**< \brief [11:11] Conversion Start Mode of Request Source x (rw) */
+ unsigned int reserved_12:12; /**< \brief \internal Reserved */
+ unsigned int ASEN0:1; /**< \brief [24:24] Arbitration Slot 0 Enable (rw) */
+ unsigned int ASEN1:1; /**< \brief [25:25] Arbitration Slot 1 Enable (rw) */
+ unsigned int ASEN2:1; /**< \brief [26:26] Arbitration Slot 2 Enable (rw) */
+ unsigned int reserved_27:5; /**< \brief \internal Reserved */
+} Ifx_VADC_G_ARBPR_Bits;
+
+/** \brief Autoscan Source Control Register, Group */
+typedef struct _Ifx_VADC_G_ASCTRL_Bits
+{
+ unsigned int SRCRESREG:4; /**< \brief [3:0] Source-specific Result Register (rw) */
+ unsigned int reserved_4:4; /**< \brief \internal Reserved */
+ unsigned int XTSEL:4; /**< \brief [11:8] External Trigger Input Selection (rw) */
+ unsigned int XTLVL:1; /**< \brief [12:12] External Trigger Level (rh) */
+ unsigned int XTMODE:2; /**< \brief [14:13] Trigger Operating Mode (rw) */
+ unsigned int XTWC:1; /**< \brief [15:15] Write Control for Trigger Configuration (w) */
+ unsigned int GTSEL:4; /**< \brief [19:16] Gate Input Selection (rw) */
+ unsigned int GTLVL:1; /**< \brief [20:20] Gate Input Level (rh) */
+ unsigned int reserved_21:2; /**< \brief \internal Reserved */
+ unsigned int GTWC:1; /**< \brief [23:23] Write Control for Gate Configuration (w) */
+ unsigned int reserved_24:4; /**< \brief \internal Reserved */
+ unsigned int TMEN:1; /**< \brief [28:28] Timer Mode Enable (rw) */
+ unsigned int reserved_29:2; /**< \brief \internal Reserved */
+ unsigned int TMWC:1; /**< \brief [31:31] Write Control for Timer Mode (w) */
+} Ifx_VADC_G_ASCTRL_Bits;
+
+/** \brief Autoscan Source Mode Register, Group */
+typedef struct _Ifx_VADC_G_ASMR_Bits
+{
+ unsigned int ENGT:2; /**< \brief [1:0] Enable Gate (rw) */
+ unsigned int ENTR:1; /**< \brief [2:2] Enable External Trigger (rw) */
+ unsigned int ENSI:1; /**< \brief [3:3] Enable Source Interrupt (rw) */
+ unsigned int SCAN:1; /**< \brief [4:4] Autoscan Enable (rw) */
+ unsigned int LDM:1; /**< \brief [5:5] Autoscan Source Load Event Mode (rw) */
+ unsigned int reserved_6:1; /**< \brief \internal Reserved */
+ unsigned int REQGT:1; /**< \brief [7:7] Request Gate Level (rh) */
+ unsigned int CLRPND:1; /**< \brief [8:8] Clear Pending Bits (w) */
+ unsigned int LDEV:1; /**< \brief [9:9] Generate Load Event (w) */
+ unsigned int reserved_10:6; /**< \brief \internal Reserved */
+ unsigned int RPTDIS:1; /**< \brief [16:16] Repeat Disable (rw) */
+ unsigned int reserved_17:15; /**< \brief \internal Reserved */
+} Ifx_VADC_G_ASMR_Bits;
+
+/** \brief Autoscan Source Pending Register, Group */
+typedef struct _Ifx_VADC_G_ASPND_Bits
+{
+ unsigned int CHPND:32; /**< \brief [31:0] Channels Pending (rwh) */
+} Ifx_VADC_G_ASPND_Bits;
+
+/** \brief Autoscan Source Channel Select Register, Group */
+typedef struct _Ifx_VADC_G_ASSEL_Bits
+{
+ unsigned int CHSEL:32; /**< \brief [31:0] Channel Selection (rwh) */
+} Ifx_VADC_G_ASSEL_Bits;
+
+/** \brief Boundary Flag Register, Group */
+typedef struct _Ifx_VADC_G_BFL_Bits
+{
+ unsigned int BFL0:1; /**< \brief [0:0] Boundary Flag 0 (rh) */
+ unsigned int BFL1:1; /**< \brief [1:1] Boundary Flag 1 (rh) */
+ unsigned int BFL2:1; /**< \brief [2:2] Boundary Flag 2 (rh) */
+ unsigned int BFL3:1; /**< \brief [3:3] Boundary Flag 3 (rh) */
+ unsigned int reserved_4:4; /**< \brief \internal Reserved */
+ unsigned int BFA0:1; /**< \brief [8:8] Boundary Flag 0 Activation Select (rw) */
+ unsigned int BFA1:1; /**< \brief [9:9] Boundary Flag 1 Activation Select (rw) */
+ unsigned int BFA2:1; /**< \brief [10:10] Boundary Flag 2 Activation Select (rw) */
+ unsigned int BFA3:1; /**< \brief [11:11] Boundary Flag 3 Activation Select (rw) */
+ unsigned int reserved_12:4; /**< \brief \internal Reserved */
+ unsigned int BFI0:1; /**< \brief [16:16] Boundary Flag 0 Inversion Control (rw) */
+ unsigned int BFI1:1; /**< \brief [17:17] Boundary Flag 1 Inversion Control (rw) */
+ unsigned int BFI2:1; /**< \brief [18:18] Boundary Flag 2 Inversion Control (rw) */
+ unsigned int BFI3:1; /**< \brief [19:19] Boundary Flag 3 Inversion Control (rw) */
+ unsigned int reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_VADC_G_BFL_Bits;
+
+/** \brief Boundary Flag Control Register, Group */
+typedef struct _Ifx_VADC_G_BFLC_Bits
+{
+ unsigned int BFM0:4; /**< \brief [3:0] Boundary Flag y Mode Control (rw) */
+ unsigned int BFM1:4; /**< \brief [7:4] Boundary Flag y Mode Control (rw) */
+ unsigned int BFM2:4; /**< \brief [11:8] Boundary Flag y Mode Control (rw) */
+ unsigned int BFM3:4; /**< \brief [15:12] Boundary Flag y Mode Control (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_VADC_G_BFLC_Bits;
+
+/** \brief Boundary Flag Node Pointer Register, Group */
+typedef struct _Ifx_VADC_G_BFLNP_Bits
+{
+ unsigned int BFL0NP:4; /**< \brief [3:0] Boundary Flag y Node Pointer (rw) */
+ unsigned int BFL1NP:4; /**< \brief [7:4] Boundary Flag y Node Pointer (rw) */
+ unsigned int BFL2NP:4; /**< \brief [11:8] Boundary Flag y Node Pointer (rw) */
+ unsigned int BFL3NP:4; /**< \brief [15:12] Boundary Flag y Node Pointer (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_VADC_G_BFLNP_Bits;
+
+/** \brief Boundary Flag Software Register, Group */
+typedef struct _Ifx_VADC_G_BFLS_Bits
+{
+ unsigned int BFC0:1; /**< \brief [0:0] Boundary Flag 0 Clear (w) */
+ unsigned int BFC1:1; /**< \brief [1:1] Boundary Flag 1 Clear (w) */
+ unsigned int BFC2:1; /**< \brief [2:2] Boundary Flag 2 Clear (w) */
+ unsigned int BFC3:1; /**< \brief [3:3] Boundary Flag 3 Clear (w) */
+ unsigned int reserved_4:12; /**< \brief \internal Reserved */
+ unsigned int BFS0:1; /**< \brief [16:16] Boundary Flag 0 Set (w) */
+ unsigned int BFS1:1; /**< \brief [17:17] Boundary Flag 1 Set (w) */
+ unsigned int BFS2:1; /**< \brief [18:18] Boundary Flag 2 Set (w) */
+ unsigned int BFS3:1; /**< \brief [19:19] Boundary Flag 3 Set (w) */
+ unsigned int reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_VADC_G_BFLS_Bits;
+
+/** \brief Boundary Select Register, Group */
+typedef struct _Ifx_VADC_G_BOUND_Bits
+{
+ unsigned int BOUNDARY0:12; /**< \brief [11:0] Boundary Value 0 for Limit Checking (rw) */
+ unsigned int reserved_12:4; /**< \brief \internal Reserved */
+ unsigned int BOUNDARY1:12; /**< \brief [27:16] Boundary Value 1 for Limit Checking (rw) */
+ unsigned int reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_VADC_G_BOUND_Bits;
+
+/** \brief Channel Event Flag Clear Register, Group */
+typedef struct _Ifx_VADC_G_CEFCLR_Bits
+{
+ unsigned int CEV0:1; /**< \brief [0:0] Clear Channel Event for Channel 0 (w) */
+ unsigned int CEV1:1; /**< \brief [1:1] Clear Channel Event for Channel 1 (w) */
+ unsigned int CEV2:1; /**< \brief [2:2] Clear Channel Event for Channel 2 (w) */
+ unsigned int CEV3:1; /**< \brief [3:3] Clear Channel Event for Channel 3 (w) */
+ unsigned int CEV4:1; /**< \brief [4:4] Clear Channel Event for Channel 4 (w) */
+ unsigned int CEV5:1; /**< \brief [5:5] Clear Channel Event for Channel 5 (w) */
+ unsigned int CEV6:1; /**< \brief [6:6] Clear Channel Event for Channel 6 (w) */
+ unsigned int CEV7:1; /**< \brief [7:7] Clear Channel Event for Channel 7 (w) */
+ unsigned int CEV8:1; /**< \brief [8:8] Clear Channel Event for Channel 8 (w) */
+ unsigned int CEV9:1; /**< \brief [9:9] Clear Channel Event for Channel 9 (w) */
+ unsigned int CEV10:1; /**< \brief [10:10] Clear Channel Event for Channel 10 (w) */
+ unsigned int CEV11:1; /**< \brief [11:11] Clear Channel Event for Channel 11 (w) */
+ unsigned int CEV12:1; /**< \brief [12:12] Clear Channel Event for Channel 12 (w) */
+ unsigned int CEV13:1; /**< \brief [13:13] Clear Channel Event for Channel 13 (w) */
+ unsigned int CEV14:1; /**< \brief [14:14] Clear Channel Event for Channel 14 (w) */
+ unsigned int CEV15:1; /**< \brief [15:15] Clear Channel Event for Channel 15 (w) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_VADC_G_CEFCLR_Bits;
+
+/** \brief Channel Event Flag Register, Group */
+typedef struct _Ifx_VADC_G_CEFLAG_Bits
+{
+ unsigned int CEV0:1; /**< \brief [0:0] Channel Event for Channel 0 (rwh) */
+ unsigned int CEV1:1; /**< \brief [1:1] Channel Event for Channel 1 (rwh) */
+ unsigned int CEV2:1; /**< \brief [2:2] Channel Event for Channel 2 (rwh) */
+ unsigned int CEV3:1; /**< \brief [3:3] Channel Event for Channel 3 (rwh) */
+ unsigned int CEV4:1; /**< \brief [4:4] Channel Event for Channel 4 (rwh) */
+ unsigned int CEV5:1; /**< \brief [5:5] Channel Event for Channel 5 (rwh) */
+ unsigned int CEV6:1; /**< \brief [6:6] Channel Event for Channel 6 (rwh) */
+ unsigned int CEV7:1; /**< \brief [7:7] Channel Event for Channel 7 (rwh) */
+ unsigned int CEV8:1; /**< \brief [8:8] Channel Event for Channel 8 (rwh) */
+ unsigned int CEV9:1; /**< \brief [9:9] Channel Event for Channel 9 (rwh) */
+ unsigned int CEV10:1; /**< \brief [10:10] Channel Event for Channel 10 (rwh) */
+ unsigned int CEV11:1; /**< \brief [11:11] Channel Event for Channel 11 (rwh) */
+ unsigned int CEV12:1; /**< \brief [12:12] Channel Event for Channel 12 (rwh) */
+ unsigned int CEV13:1; /**< \brief [13:13] Channel Event for Channel 13 (rwh) */
+ unsigned int CEV14:1; /**< \brief [14:14] Channel Event for Channel 14 (rwh) */
+ unsigned int CEV15:1; /**< \brief [15:15] Channel Event for Channel 15 (rwh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_VADC_G_CEFLAG_Bits;
+
+/** \brief Channel Event Node Pointer Register 0, Group */
+typedef struct _Ifx_VADC_G_CEVNP0_Bits
+{
+ unsigned int CEV0NP:4; /**< \brief [3:0] Service Request Node Pointer Channel Event i (rw) */
+ unsigned int CEV1NP:4; /**< \brief [7:4] Service Request Node Pointer Channel Event i (rw) */
+ unsigned int CEV2NP:4; /**< \brief [11:8] Service Request Node Pointer Channel Event i (rw) */
+ unsigned int CEV3NP:4; /**< \brief [15:12] Service Request Node Pointer Channel Event i (rw) */
+ unsigned int CEV4NP:4; /**< \brief [19:16] Service Request Node Pointer Channel Event i (rw) */
+ unsigned int CEV5NP:4; /**< \brief [23:20] Service Request Node Pointer Channel Event i (rw) */
+ unsigned int CEV6NP:4; /**< \brief [27:24] Service Request Node Pointer Channel Event i (rw) */
+ unsigned int CEV7NP:4; /**< \brief [31:28] Service Request Node Pointer Channel Event i (rw) */
+} Ifx_VADC_G_CEVNP0_Bits;
+
+/** \brief Channel Event Node Pointer Register 1, Group */
+typedef struct _Ifx_VADC_G_CEVNP1_Bits
+{
+ unsigned int CEV8NP:4; /**< \brief [3:0] Service Request Node Pointer Channel Event i (rw) */
+ unsigned int CEV9NP:4; /**< \brief [7:4] Service Request Node Pointer Channel Event i (rw) */
+ unsigned int CEV10NP:4; /**< \brief [11:8] Service Request Node Pointer Channel Event i (rw) */
+ unsigned int CEV11NP:4; /**< \brief [15:12] Service Request Node Pointer Channel Event i (rw) */
+ unsigned int CEV12NP:4; /**< \brief [19:16] Service Request Node Pointer Channel Event i (rw) */
+ unsigned int CEV13NP:4; /**< \brief [23:20] Service Request Node Pointer Channel Event i (rw) */
+ unsigned int CEV14NP:4; /**< \brief [27:24] Service Request Node Pointer Channel Event i (rw) */
+ unsigned int CEV15NP:4; /**< \brief [31:28] Service Request Node Pointer Channel Event i (rw) */
+} Ifx_VADC_G_CEVNP1_Bits;
+
+/** \brief Channel Assignment Register, Group */
+typedef struct _Ifx_VADC_G_CHASS_Bits
+{
+ unsigned int ASSCH0:1; /**< \brief [0:0] Assignment for Channel 0 (rw) */
+ unsigned int ASSCH1:1; /**< \brief [1:1] Assignment for Channel 1 (rw) */
+ unsigned int ASSCH2:1; /**< \brief [2:2] Assignment for Channel 2 (rw) */
+ unsigned int ASSCH3:1; /**< \brief [3:3] Assignment for Channel 3 (rw) */
+ unsigned int ASSCH4:1; /**< \brief [4:4] Assignment for Channel 4 (rw) */
+ unsigned int ASSCH5:1; /**< \brief [5:5] Assignment for Channel 5 (rw) */
+ unsigned int ASSCH6:1; /**< \brief [6:6] Assignment for Channel 6 (rw) */
+ unsigned int ASSCH7:1; /**< \brief [7:7] Assignment for Channel 7 (rw) */
+ unsigned int ASSCH8:1; /**< \brief [8:8] Assignment for Channel 8 (rw) */
+ unsigned int ASSCH9:1; /**< \brief [9:9] Assignment for Channel 9 (rw) */
+ unsigned int ASSCH10:1; /**< \brief [10:10] Assignment for Channel 10 (rw) */
+ unsigned int ASSCH11:1; /**< \brief [11:11] Assignment for Channel 11 (rw) */
+ unsigned int ASSCH12:1; /**< \brief [12:12] Assignment for Channel 12 (rw) */
+ unsigned int ASSCH13:1; /**< \brief [13:13] Assignment for Channel 13 (rw) */
+ unsigned int ASSCH14:1; /**< \brief [14:14] Assignment for Channel 14 (rw) */
+ unsigned int ASSCH15:1; /**< \brief [15:15] Assignment for Channel 15 (rw) */
+ unsigned int ASSCH16:1; /**< \brief [16:16] Assignment for Channel 16 (rw) */
+ unsigned int ASSCH17:1; /**< \brief [17:17] Assignment for Channel 17 (rw) */
+ unsigned int ASSCH18:1; /**< \brief [18:18] Assignment for Channel 18 (rw) */
+ unsigned int ASSCH19:1; /**< \brief [19:19] Assignment for Channel 19 (rw) */
+ unsigned int ASSCH20:1; /**< \brief [20:20] Assignment for Channel 20 (rw) */
+ unsigned int ASSCH21:1; /**< \brief [21:21] Assignment for Channel 21 (rw) */
+ unsigned int ASSCH22:1; /**< \brief [22:22] Assignment for Channel 22 (rw) */
+ unsigned int ASSCH23:1; /**< \brief [23:23] Assignment for Channel 23 (rw) */
+ unsigned int ASSCH24:1; /**< \brief [24:24] Assignment for Channel 24 (rw) */
+ unsigned int ASSCH25:1; /**< \brief [25:25] Assignment for Channel 25 (rw) */
+ unsigned int ASSCH26:1; /**< \brief [26:26] Assignment for Channel 26 (rw) */
+ unsigned int ASSCH27:1; /**< \brief [27:27] Assignment for Channel 27 (rw) */
+ unsigned int ASSCH28:1; /**< \brief [28:28] Assignment for Channel 28 (rw) */
+ unsigned int ASSCH29:1; /**< \brief [29:29] Assignment for Channel 29 (rw) */
+ unsigned int ASSCH30:1; /**< \brief [30:30] Assignment for Channel 30 (rw) */
+ unsigned int ASSCH31:1; /**< \brief [31:31] Assignment for Channel 31 (rw) */
+} Ifx_VADC_G_CHASS_Bits;
+
+/** \brief Group, Channel Ctrl. Reg. */
+typedef struct _Ifx_VADC_G_CHCTR_Bits
+{
+ unsigned int ICLSEL:2; /**< \brief [1:0] Input Class Select (rw) */
+ unsigned int reserved_2:2; /**< \brief \internal Reserved */
+ unsigned int BNDSELL:2; /**< \brief [5:4] Lower Boundary Select (rw) */
+ unsigned int BNDSELU:2; /**< \brief [7:6] Upper Boundary Select (rw) */
+ unsigned int CHEVMODE:2; /**< \brief [9:8] Channel Event Mode (rw) */
+ unsigned int SYNC:1; /**< \brief [10:10] Synchronization Request (rw) */
+ unsigned int REFSEL:1; /**< \brief [11:11] Reference Input Selection (rw) */
+ unsigned int BNDSELX:4; /**< \brief [15:12] BoundaryExtension (rw) */
+ unsigned int RESREG:4; /**< \brief [19:16] Result Register (rw) */
+ unsigned int RESTBS:1; /**< \brief [20:20] Result Target for Background Source (rw) */
+ unsigned int RESPOS:1; /**< \brief [21:21] Result Position (rw) */
+ unsigned int reserved_22:6; /**< \brief \internal Reserved */
+ unsigned int BWDCH:2; /**< \brief [29:28] Broken Wire Detection Channel (rw) */
+ unsigned int BWDEN:1; /**< \brief [30:30] Broken Wire Detection Enable (rw) */
+ unsigned int reserved_31:1; /**< \brief \internal Reserved */
+} Ifx_VADC_G_CHCTR_Bits;
+
+/** \brief External Multiplexer Control Register, Group x */
+typedef struct _Ifx_VADC_G_EMUXCTR_Bits
+{
+ unsigned int EMUXSET:3; /**< \brief [2:0] External Multiplexer Start Selection (rw) */
+ unsigned int reserved_3:5; /**< \brief \internal Reserved */
+ unsigned int EMUXACT:3; /**< \brief [10:8] External Multiplexer Actual Selection (rh) */
+ unsigned int reserved_11:5; /**< \brief \internal Reserved */
+ unsigned int EMUXCH:10; /**< \brief [25:16] External Multiplexer Channel Select (rw) */
+ unsigned int EMUXMODE:2; /**< \brief [27:26] External Multiplexer Mode (rw) */
+ unsigned int EMXCOD:1; /**< \brief [28:28] External Multiplexer Coding Scheme (rw) */
+ unsigned int EMXST:1; /**< \brief [29:29] External Multiplexer Sample Time Control (rw) */
+ unsigned int EMXCSS:1; /**< \brief [30:30] External Multiplexer Channel Selection Style (r) */
+ unsigned int EMXWC:1; /**< \brief [31:31] Write Control for EMUX Configuration (w) */
+} Ifx_VADC_G_EMUXCTR_Bits;
+
+/** \brief Queue 0 Register 0, Group */
+typedef struct _Ifx_VADC_G_Q0R0_Bits
+{
+ unsigned int REQCHNR:5; /**< \brief [4:0] Request Channel Number (rh) */
+ unsigned int RF:1; /**< \brief [5:5] Refill (rh) */
+ unsigned int ENSI:1; /**< \brief [6:6] Enable Source Interrupt (rh) */
+ unsigned int EXTR:1; /**< \brief [7:7] External Trigger (rh) */
+ unsigned int V:1; /**< \brief [8:8] Request Channel Number Valid (rh) */
+ unsigned int reserved_9:23; /**< \brief \internal Reserved */
+} Ifx_VADC_G_Q0R0_Bits;
+
+/** \brief Queue 0 Backup Register, Group */
+typedef struct _Ifx_VADC_G_QBUR0_Bits
+{
+ unsigned int REQCHNR:5; /**< \brief [4:0] Request Channel Number (rh) */
+ unsigned int RF:1; /**< \brief [5:5] Refill (rh) */
+ unsigned int ENSI:1; /**< \brief [6:6] Enable Source Interrupt (rh) */
+ unsigned int EXTR:1; /**< \brief [7:7] External Trigger (rh) */
+ unsigned int V:1; /**< \brief [8:8] Request Channel Number Valid (rh) */
+ unsigned int reserved_9:23; /**< \brief \internal Reserved */
+} Ifx_VADC_G_QBUR0_Bits;
+
+/** \brief Queue 0 Source Control Register, Group */
+typedef struct _Ifx_VADC_G_QCTRL0_Bits
+{
+ unsigned int SRCRESREG:4; /**< \brief [3:0] Source-specific Result Register (rw) */
+ unsigned int reserved_4:4; /**< \brief \internal Reserved */
+ unsigned int XTSEL:4; /**< \brief [11:8] External Trigger Input Selection (rw) */
+ unsigned int XTLVL:1; /**< \brief [12:12] External Trigger Level (rh) */
+ unsigned int XTMODE:2; /**< \brief [14:13] Trigger Operating Mode (rw) */
+ unsigned int XTWC:1; /**< \brief [15:15] Write Control for Trigger Configuration (w) */
+ unsigned int GTSEL:4; /**< \brief [19:16] Gate Input Selection (rw) */
+ unsigned int GTLVL:1; /**< \brief [20:20] Gate Input Level (rh) */
+ unsigned int reserved_21:2; /**< \brief \internal Reserved */
+ unsigned int GTWC:1; /**< \brief [23:23] Write Control for Gate Configuration (w) */
+ unsigned int reserved_24:4; /**< \brief \internal Reserved */
+ unsigned int TMEN:1; /**< \brief [28:28] Timer Mode Enable (rw) */
+ unsigned int reserved_29:2; /**< \brief \internal Reserved */
+ unsigned int TMWC:1; /**< \brief [31:31] Write Control for Timer Mode (w) */
+} Ifx_VADC_G_QCTRL0_Bits;
+
+/** \brief Queue 0 Input Register, Group */
+typedef struct _Ifx_VADC_G_QINR0_Bits
+{
+ unsigned int REQCHNR:5; /**< \brief [4:0] Request Channel Number (w) */
+ unsigned int RF:1; /**< \brief [5:5] Refill (w) */
+ unsigned int ENSI:1; /**< \brief [6:6] Enable Source Interrupt (w) */
+ unsigned int EXTR:1; /**< \brief [7:7] External Trigger (w) */
+ unsigned int reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_VADC_G_QINR0_Bits;
+
+/** \brief Queue 0 Mode Register, Group */
+typedef struct _Ifx_VADC_G_QMR0_Bits
+{
+ unsigned int ENGT:2; /**< \brief [1:0] Enable Gate (rw) */
+ unsigned int ENTR:1; /**< \brief [2:2] Enable External Trigger (rw) */
+ unsigned int reserved_3:5; /**< \brief \internal Reserved */
+ unsigned int CLRV:1; /**< \brief [8:8] Clear Valid Bit (w) */
+ unsigned int TREV:1; /**< \brief [9:9] Trigger Event (w) */
+ unsigned int FLUSH:1; /**< \brief [10:10] Flush Queue (w) */
+ unsigned int CEV:1; /**< \brief [11:11] Clear Event Flag (w) */
+ unsigned int reserved_12:4; /**< \brief \internal Reserved */
+ unsigned int RPTDIS:1; /**< \brief [16:16] Repeat Disable (rw) */
+ unsigned int reserved_17:15; /**< \brief \internal Reserved */
+} Ifx_VADC_G_QMR0_Bits;
+
+/** \brief Queue 0 Status Register, Group */
+typedef struct _Ifx_VADC_G_QSR0_Bits
+{
+ unsigned int FILL:4; /**< \brief [3:0] Filling Level for Queue 0 (rh) */
+ unsigned int reserved_4:1; /**< \brief \internal Reserved */
+ unsigned int EMPTY:1; /**< \brief [5:5] Queue Empty (rh) */
+ unsigned int reserved_6:1; /**< \brief \internal Reserved */
+ unsigned int REQGT:1; /**< \brief [7:7] Request Gate Level (rh) */
+ unsigned int EV:1; /**< \brief [8:8] Event Detected (rh) */
+ unsigned int reserved_9:23; /**< \brief \internal Reserved */
+} Ifx_VADC_G_QSR0_Bits;
+
+/** \brief Group Result Control Reg. */
+typedef struct _Ifx_VADC_G_RCR_Bits
+{
+ unsigned int reserved_0:16; /**< \brief \internal Reserved */
+ unsigned int DRCTR:4; /**< \brief [19:16] Data Reduction Control (rw) */
+ unsigned int DMM:2; /**< \brief [21:20] Data Modification Mode (rw) */
+ unsigned int reserved_22:2; /**< \brief \internal Reserved */
+ unsigned int WFR:1; /**< \brief [24:24] Wait-for-Read Mode Enable (rw) */
+ unsigned int FEN:2; /**< \brief [26:25] FIFO Mode Enable (rw) */
+ unsigned int reserved_27:4; /**< \brief \internal Reserved */
+ unsigned int SRGEN:1; /**< \brief [31:31] Service Request Generation Enable (rw) */
+} Ifx_VADC_G_RCR_Bits;
+
+/** \brief Result Event Flag Clear Register, Group */
+typedef struct _Ifx_VADC_G_REFCLR_Bits
+{
+ unsigned int REV0:1; /**< \brief [0:0] Clear Result Event for Result Register 0 (w) */
+ unsigned int REV1:1; /**< \brief [1:1] Clear Result Event for Result Register 1 (w) */
+ unsigned int REV2:1; /**< \brief [2:2] Clear Result Event for Result Register 2 (w) */
+ unsigned int REV3:1; /**< \brief [3:3] Clear Result Event for Result Register 3 (w) */
+ unsigned int REV4:1; /**< \brief [4:4] Clear Result Event for Result Register 4 (w) */
+ unsigned int REV5:1; /**< \brief [5:5] Clear Result Event for Result Register 5 (w) */
+ unsigned int REV6:1; /**< \brief [6:6] Clear Result Event for Result Register 6 (w) */
+ unsigned int REV7:1; /**< \brief [7:7] Clear Result Event for Result Register 7 (w) */
+ unsigned int REV8:1; /**< \brief [8:8] Clear Result Event for Result Register 8 (w) */
+ unsigned int REV9:1; /**< \brief [9:9] Clear Result Event for Result Register 9 (w) */
+ unsigned int REV10:1; /**< \brief [10:10] Clear Result Event for Result Register 10 (w) */
+ unsigned int REV11:1; /**< \brief [11:11] Clear Result Event for Result Register 11 (w) */
+ unsigned int REV12:1; /**< \brief [12:12] Clear Result Event for Result Register 12 (w) */
+ unsigned int REV13:1; /**< \brief [13:13] Clear Result Event for Result Register 13 (w) */
+ unsigned int REV14:1; /**< \brief [14:14] Clear Result Event for Result Register 14 (w) */
+ unsigned int REV15:1; /**< \brief [15:15] Clear Result Event for Result Register 15 (w) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_VADC_G_REFCLR_Bits;
+
+/** \brief Result Event Flag Register, Group */
+typedef struct _Ifx_VADC_G_REFLAG_Bits
+{
+ unsigned int REV0:1; /**< \brief [0:0] Result Event for Result Register 0 (rwh) */
+ unsigned int REV1:1; /**< \brief [1:1] Result Event for Result Register 1 (rwh) */
+ unsigned int REV2:1; /**< \brief [2:2] Result Event for Result Register 2 (rwh) */
+ unsigned int REV3:1; /**< \brief [3:3] Result Event for Result Register 3 (rwh) */
+ unsigned int REV4:1; /**< \brief [4:4] Result Event for Result Register 4 (rwh) */
+ unsigned int REV5:1; /**< \brief [5:5] Result Event for Result Register 5 (rwh) */
+ unsigned int REV6:1; /**< \brief [6:6] Result Event for Result Register 6 (rwh) */
+ unsigned int REV7:1; /**< \brief [7:7] Result Event for Result Register 7 (rwh) */
+ unsigned int REV8:1; /**< \brief [8:8] Result Event for Result Register 8 (rwh) */
+ unsigned int REV9:1; /**< \brief [9:9] Result Event for Result Register 9 (rwh) */
+ unsigned int REV10:1; /**< \brief [10:10] Result Event for Result Register 10 (rwh) */
+ unsigned int REV11:1; /**< \brief [11:11] Result Event for Result Register 11 (rwh) */
+ unsigned int REV12:1; /**< \brief [12:12] Result Event for Result Register 12 (rwh) */
+ unsigned int REV13:1; /**< \brief [13:13] Result Event for Result Register 13 (rwh) */
+ unsigned int REV14:1; /**< \brief [14:14] Result Event for Result Register 14 (rwh) */
+ unsigned int REV15:1; /**< \brief [15:15] Result Event for Result Register 15 (rwh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_VADC_G_REFLAG_Bits;
+
+/** \brief Group Result Register */
+typedef struct _Ifx_VADC_G_RES_Bits
+{
+ unsigned int RESULT:16; /**< \brief [15:0] Result of Most Recent Conversion (rwh) */
+ unsigned int DRC:4; /**< \brief [19:16] Data Reduction Counter (rh) */
+ unsigned int CHNR:5; /**< \brief [24:20] Channel Number (rh) */
+ unsigned int EMUX:3; /**< \brief [27:25] External Multiplexer Setting (rh) */
+ unsigned int CRS:2; /**< \brief [29:28] Converted Request Source (rh) */
+ unsigned int FCR:1; /**< \brief [30:30] Fast Compare Result (rh) */
+ unsigned int VF:1; /**< \brief [31:31] Valid Flag (rh) */
+} Ifx_VADC_G_RES_Bits;
+
+/** \brief Group Result Reg., Debug */
+typedef struct _Ifx_VADC_G_RESD_Bits
+{
+ unsigned int RESULT:16; /**< \brief [15:0] Result of Most Recent Conversion (rh) */
+ unsigned int DRC:4; /**< \brief [19:16] Data Reduction Counter (rh) */
+ unsigned int CHNR:5; /**< \brief [24:20] Channel Number (rh) */
+ unsigned int EMUX:3; /**< \brief [27:25] External Multiplexer Setting (rh) */
+ unsigned int CRS:2; /**< \brief [29:28] Converted Request Source (rh) */
+ unsigned int FCR:1; /**< \brief [30:30] Fast Compare Result (rh) */
+ unsigned int VF:1; /**< \brief [31:31] Valid Flag (rh) */
+} Ifx_VADC_G_RESD_Bits;
+
+/** \brief Result Event Node Pointer Register 0, Group */
+typedef struct _Ifx_VADC_G_REVNP0_Bits
+{
+ unsigned int REV0NP:4; /**< \brief [3:0] Service Request Node Pointer Result Event i (rw) */
+ unsigned int REV1NP:4; /**< \brief [7:4] Service Request Node Pointer Result Event i (rw) */
+ unsigned int REV2NP:4; /**< \brief [11:8] Service Request Node Pointer Result Event i (rw) */
+ unsigned int REV3NP:4; /**< \brief [15:12] Service Request Node Pointer Result Event i (rw) */
+ unsigned int REV4NP:4; /**< \brief [19:16] Service Request Node Pointer Result Event i (rw) */
+ unsigned int REV5NP:4; /**< \brief [23:20] Service Request Node Pointer Result Event i (rw) */
+ unsigned int REV6NP:4; /**< \brief [27:24] Service Request Node Pointer Result Event i (rw) */
+ unsigned int REV7NP:4; /**< \brief [31:28] Service Request Node Pointer Result Event i (rw) */
+} Ifx_VADC_G_REVNP0_Bits;
+
+/** \brief Result Event Node Pointer Register 1, Group */
+typedef struct _Ifx_VADC_G_REVNP1_Bits
+{
+ unsigned int REV8NP:4; /**< \brief [3:0] Service Request Node Pointer Result Event i (rw) */
+ unsigned int REV9NP:4; /**< \brief [7:4] Service Request Node Pointer Result Event i (rw) */
+ unsigned int REV10NP:4; /**< \brief [11:8] Service Request Node Pointer Result Event i (rw) */
+ unsigned int REV11NP:4; /**< \brief [15:12] Service Request Node Pointer Result Event i (rw) */
+ unsigned int REV12NP:4; /**< \brief [19:16] Service Request Node Pointer Result Event i (rw) */
+ unsigned int REV13NP:4; /**< \brief [23:20] Service Request Node Pointer Result Event i (rw) */
+ unsigned int REV14NP:4; /**< \brief [27:24] Service Request Node Pointer Result Event i (rw) */
+ unsigned int REV15NP:4; /**< \brief [31:28] Service Request Node Pointer Result Event i (rw) */
+} Ifx_VADC_G_REVNP1_Bits;
+
+/** \brief Result Assignment Register, Group */
+typedef struct _Ifx_VADC_G_RRASS_Bits
+{
+ unsigned int ASSRR0:1; /**< \brief [0:0] Assignment for Result Register 0 (rw) */
+ unsigned int ASSRR1:1; /**< \brief [1:1] Assignment for Result Register 1 (rw) */
+ unsigned int ASSRR2:1; /**< \brief [2:2] Assignment for Result Register 2 (rw) */
+ unsigned int ASSRR3:1; /**< \brief [3:3] Assignment for Result Register 3 (rw) */
+ unsigned int ASSRR4:1; /**< \brief [4:4] Assignment for Result Register 4 (rw) */
+ unsigned int ASSRR5:1; /**< \brief [5:5] Assignment for Result Register 5 (rw) */
+ unsigned int ASSRR6:1; /**< \brief [6:6] Assignment for Result Register 6 (rw) */
+ unsigned int ASSRR7:1; /**< \brief [7:7] Assignment for Result Register 7 (rw) */
+ unsigned int ASSRR8:1; /**< \brief [8:8] Assignment for Result Register 8 (rw) */
+ unsigned int ASSRR9:1; /**< \brief [9:9] Assignment for Result Register 9 (rw) */
+ unsigned int ASSRR10:1; /**< \brief [10:10] Assignment for Result Register 10 (rw) */
+ unsigned int ASSRR11:1; /**< \brief [11:11] Assignment for Result Register 11 (rw) */
+ unsigned int ASSRR12:1; /**< \brief [12:12] Assignment for Result Register 12 (rw) */
+ unsigned int ASSRR13:1; /**< \brief [13:13] Assignment for Result Register 13 (rw) */
+ unsigned int ASSRR14:1; /**< \brief [14:14] Assignment for Result Register 14 (rw) */
+ unsigned int ASSRR15:1; /**< \brief [15:15] Assignment for Result Register 15 (rw) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_VADC_G_RRASS_Bits;
+
+/** \brief Source Event Flag Clear Register, Group */
+typedef struct _Ifx_VADC_G_SEFCLR_Bits
+{
+ unsigned int SEV0:1; /**< \brief [0:0] Clear Source Event 0/1 (w) */
+ unsigned int SEV1:1; /**< \brief [1:1] Clear Source Event 0/1 (w) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_VADC_G_SEFCLR_Bits;
+
+/** \brief Source Event Flag Register, Group */
+typedef struct _Ifx_VADC_G_SEFLAG_Bits
+{
+ unsigned int SEV0:1; /**< \brief [0:0] Source Event 0/1 (rwh) */
+ unsigned int SEV1:1; /**< \brief [1:1] Source Event 0/1 (rwh) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_VADC_G_SEFLAG_Bits;
+
+/** \brief Source Event Node Pointer Register, Group */
+typedef struct _Ifx_VADC_G_SEVNP_Bits
+{
+ unsigned int SEV0NP:4; /**< \brief [3:0] Service Request Node Pointer Source Event i (rw) */
+ unsigned int SEV1NP:4; /**< \brief [7:4] Service Request Node Pointer Source Event i (rw) */
+ unsigned int reserved_8:24; /**< \brief \internal Reserved */
+} Ifx_VADC_G_SEVNP_Bits;
+
+/** \brief Service Request Software Activation Trigger, Group */
+typedef struct _Ifx_VADC_G_SRACT_Bits
+{
+ unsigned int AGSR0:1; /**< \brief [0:0] Activate Group Service Request Node 0 (w) */
+ unsigned int AGSR1:1; /**< \brief [1:1] Activate Group Service Request Node 1 (w) */
+ unsigned int AGSR2:1; /**< \brief [2:2] Activate Group Service Request Node 2 (w) */
+ unsigned int AGSR3:1; /**< \brief [3:3] Activate Group Service Request Node 3 (w) */
+ unsigned int reserved_4:4; /**< \brief \internal Reserved */
+ unsigned int ASSR0:1; /**< \brief [8:8] Activate Shared Service Request Node 0 (w) */
+ unsigned int ASSR1:1; /**< \brief [9:9] Activate Shared Service Request Node 1 (w) */
+ unsigned int ASSR2:1; /**< \brief [10:10] Activate Shared Service Request Node 2 (w) */
+ unsigned int ASSR3:1; /**< \brief [11:11] Activate Shared Service Request Node 3 (w) */
+ unsigned int reserved_12:20; /**< \brief \internal Reserved */
+} Ifx_VADC_G_SRACT_Bits;
+
+/** \brief Synchronization Control Register, Group */
+typedef struct _Ifx_VADC_G_SYNCTR_Bits
+{
+ unsigned int STSEL:2; /**< \brief [1:0] Start Selection (rw) */
+ unsigned int reserved_2:2; /**< \brief \internal Reserved */
+ unsigned int EVALR1:1; /**< \brief [4:4] Evaluate Ready Input Rx (rw) */
+ unsigned int EVALR2:1; /**< \brief [5:5] Evaluate Ready Input Rx (rw) */
+ unsigned int EVALR3:1; /**< \brief [6:6] Evaluate Ready Input Rx (rw) */
+ unsigned int reserved_7:25; /**< \brief \internal Reserved */
+} Ifx_VADC_G_SYNCTR_Bits;
+
+/** \brief Valid Flag Register, Group */
+typedef struct _Ifx_VADC_G_VFR_Bits
+{
+ unsigned int VF0:1; /**< \brief [0:0] Valid Flag of Result Register x (rwh) */
+ unsigned int VF1:1; /**< \brief [1:1] Valid Flag of Result Register x (rwh) */
+ unsigned int VF2:1; /**< \brief [2:2] Valid Flag of Result Register x (rwh) */
+ unsigned int VF3:1; /**< \brief [3:3] Valid Flag of Result Register x (rwh) */
+ unsigned int VF4:1; /**< \brief [4:4] Valid Flag of Result Register x (rwh) */
+ unsigned int VF5:1; /**< \brief [5:5] Valid Flag of Result Register x (rwh) */
+ unsigned int VF6:1; /**< \brief [6:6] Valid Flag of Result Register x (rwh) */
+ unsigned int VF7:1; /**< \brief [7:7] Valid Flag of Result Register x (rwh) */
+ unsigned int VF8:1; /**< \brief [8:8] Valid Flag of Result Register x (rwh) */
+ unsigned int VF9:1; /**< \brief [9:9] Valid Flag of Result Register x (rwh) */
+ unsigned int VF10:1; /**< \brief [10:10] Valid Flag of Result Register x (rwh) */
+ unsigned int VF11:1; /**< \brief [11:11] Valid Flag of Result Register x (rwh) */
+ unsigned int VF12:1; /**< \brief [12:12] Valid Flag of Result Register x (rwh) */
+ unsigned int VF13:1; /**< \brief [13:13] Valid Flag of Result Register x (rwh) */
+ unsigned int VF14:1; /**< \brief [14:14] Valid Flag of Result Register x (rwh) */
+ unsigned int VF15:1; /**< \brief [15:15] Valid Flag of Result Register x (rwh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_VADC_G_VFR_Bits;
+
+/** \brief Global Boundary Select Register */
+typedef struct _Ifx_VADC_GLOBBOUND_Bits
+{
+ unsigned int BOUNDARY0:12; /**< \brief [11:0] Boundary Value 0 for Limit Checking (rw) */
+ unsigned int reserved_12:4; /**< \brief \internal Reserved */
+ unsigned int BOUNDARY1:12; /**< \brief [27:16] Boundary Value 1 for Limit Checking (rw) */
+ unsigned int reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_VADC_GLOBBOUND_Bits;
+
+/** \brief Global Configuration Register */
+typedef struct _Ifx_VADC_GLOBCFG_Bits
+{
+ unsigned int DIVA:5; /**< \brief [4:0] Divider Factor for the Analog Internal Clock (rw) */
+ unsigned int reserved_5:2; /**< \brief \internal Reserved */
+ unsigned int DCMSB:1; /**< \brief [7:7] Double Clock for the MSB Conversion (rw) */
+ unsigned int DIVD:2; /**< \brief [9:8] Divider Factor for the Arbiter Clock (rw) */
+ unsigned int reserved_10:2; /**< \brief \internal Reserved */
+ unsigned int REFPC:1; /**< \brief [12:12] Reference Precharge Control (rw) */
+ unsigned int reserved_13:1; /**< \brief \internal Reserved */
+ unsigned int LOSUP:1; /**< \brief [14:14] Low Power Supply Voltage Select (rw) */
+ unsigned int DIVWC:1; /**< \brief [15:15] Write Control for Divider Parameters (w) */
+ unsigned int DPCAL0:1; /**< \brief [16:16] Disable Post-Calibration (rw) */
+ unsigned int DPCAL1:1; /**< \brief [17:17] Disable Post-Calibration (rw) */
+ unsigned int DPCAL2:1; /**< \brief [18:18] Disable Post-Calibration (rw) */
+ unsigned int DPCAL3:1; /**< \brief [19:19] Disable Post-Calibration (rw) */
+ unsigned int reserved_20:11; /**< \brief \internal Reserved */
+ unsigned int SUCAL:1; /**< \brief [31:31] Start-Up Calibration (w) */
+} Ifx_VADC_GLOBCFG_Bits;
+
+/** \brief Global Event Flag Register */
+typedef struct _Ifx_VADC_GLOBEFLAG_Bits
+{
+ unsigned int SEVGLB:1; /**< \brief [0:0] Source Event (Background) (rwh) */
+ unsigned int reserved_1:7; /**< \brief \internal Reserved */
+ unsigned int REVGLB:1; /**< \brief [8:8] Global Result Event (rwh) */
+ unsigned int reserved_9:7; /**< \brief \internal Reserved */
+ unsigned int SEVGLBCLR:1; /**< \brief [16:16] Clear Source Event (Background) (w) */
+ unsigned int reserved_17:7; /**< \brief \internal Reserved */
+ unsigned int REVGLBCLR:1; /**< \brief [24:24] Clear Global Result Event (w) */
+ unsigned int reserved_25:7; /**< \brief \internal Reserved */
+} Ifx_VADC_GLOBEFLAG_Bits;
+
+/** \brief Global Event Node Pointer Register */
+typedef struct _Ifx_VADC_GLOBEVNP_Bits
+{
+ unsigned int SEV0NP:4; /**< \brief [3:0] Service Request Node Pointer Backgr. Source (rw) */
+ unsigned int reserved_4:12; /**< \brief \internal Reserved */
+ unsigned int REV0NP:4; /**< \brief [19:16] Service Request Node Pointer Backgr. Result (rw) */
+ unsigned int reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_VADC_GLOBEVNP_Bits;
+
+/** \brief Global Result Control Register */
+typedef struct _Ifx_VADC_GLOBRCR_Bits
+{
+ unsigned int reserved_0:16; /**< \brief \internal Reserved */
+ unsigned int DRCTR:4; /**< \brief [19:16] Data Reduction Control (rw) */
+ unsigned int reserved_20:4; /**< \brief \internal Reserved */
+ unsigned int WFR:1; /**< \brief [24:24] Wait-for-Read Mode Enable (rw) */
+ unsigned int reserved_25:6; /**< \brief \internal Reserved */
+ unsigned int SRGEN:1; /**< \brief [31:31] Service Request Generation Enable (rw) */
+} Ifx_VADC_GLOBRCR_Bits;
+
+/** \brief Global Result Register */
+typedef struct _Ifx_VADC_GLOBRES_Bits
+{
+ unsigned int RESULT:16; /**< \brief [15:0] Result of most recent conversion (rwh) */
+ unsigned int GNR:4; /**< \brief [19:16] Group Number (rh) */
+ unsigned int CHNR:5; /**< \brief [24:20] Channel Number (rh) */
+ unsigned int EMUX:3; /**< \brief [27:25] External Multiplexer Setting (rh) */
+ unsigned int CRS:2; /**< \brief [29:28] Converted Request Source (rh) */
+ unsigned int FCR:1; /**< \brief [30:30] Fast Compare Result (rh) */
+ unsigned int VF:1; /**< \brief [31:31] Valid Flag (rwh) */
+} Ifx_VADC_GLOBRES_Bits;
+
+/** \brief Global Result Register, Debug */
+typedef struct _Ifx_VADC_GLOBRESD_Bits
+{
+ unsigned int RESULT:16; /**< \brief [15:0] Result of most recent conversion (rwh) */
+ unsigned int GNR:4; /**< \brief [19:16] Group Number (rh) */
+ unsigned int CHNR:5; /**< \brief [24:20] Channel Number (rh) */
+ unsigned int EMUX:3; /**< \brief [27:25] External Multiplexer Setting (rh) */
+ unsigned int CRS:2; /**< \brief [29:28] Converted Request Source (rh) */
+ unsigned int FCR:1; /**< \brief [30:30] Fast Compare Result (rh) */
+ unsigned int VF:1; /**< \brief [31:31] Valid Flag (rwh) */
+} Ifx_VADC_GLOBRESD_Bits;
+
+/** \brief Global Test Functions Register */
+typedef struct _Ifx_VADC_GLOBTF_Bits
+{
+ unsigned int CDCH:4; /**< \brief [3:0] Control Diagnostics Channel (rw) */
+ unsigned int CDGR:4; /**< \brief [7:4] Control Diagnostics Group (rw) */
+ unsigned int CDEN:1; /**< \brief [8:8] Converter Diagnostics Enable (rw) */
+ unsigned int CDSEL:2; /**< \brief [10:9] Converter Diagnostics Pull-Devices Select (rw) */
+ unsigned int reserved_11:4; /**< \brief \internal Reserved */
+ unsigned int CDWC:1; /**< \brief [15:15] Write Control for Conversion Diagnostics (w) */
+ unsigned int PDD:1; /**< \brief [16:16] Pull-Down Diagnostics Enable (rw) */
+ unsigned int MDPD:1; /**< \brief [17:17] Multiplexer Diagnostics Pull-Devices Enable (rw) */
+ unsigned int MDPU:1; /**< \brief [18:18] Multiplexer Diagnostics Pull-Devices Enable (rw) */
+ unsigned int reserved_19:4; /**< \brief \internal Reserved */
+ unsigned int MDWC:1; /**< \brief [23:23] Write Control for Multiplexer Diagnostics (w) */
+ unsigned int reserved_24:8; /**< \brief \internal Reserved */
+} Ifx_VADC_GLOBTF_Bits;
+
+/** \brief Input Class Register */
+typedef struct _Ifx_VADC_ICLASS_Bits
+{
+ unsigned int STCS:5; /**< \brief [4:0] Sample Time Control for Standard Conversions (rw) */
+ unsigned int reserved_5:3; /**< \brief \internal Reserved */
+ unsigned int CMS:3; /**< \brief [10:8] Conversion Mode for Standard Conversions (rw) */
+ unsigned int reserved_11:5; /**< \brief \internal Reserved */
+ unsigned int STCE:5; /**< \brief [20:16] Sample Time Control for EMUX Conversions (rw) */
+ unsigned int reserved_21:3; /**< \brief \internal Reserved */
+ unsigned int CME:3; /**< \brief [26:24] Conversion Mode for EMUX Conversions (rw) */
+ unsigned int reserved_27:5; /**< \brief \internal Reserved */
+} Ifx_VADC_ICLASS_Bits;
+
+/** \brief Module Identification Register */
+typedef struct _Ifx_VADC_ID_Bits
+{
+ unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
+ unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_VADC_ID_Bits;
+
+/** \brief Kernel Reset Register 0 */
+typedef struct _Ifx_VADC_KRST0_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rh) */
+ unsigned int reserved_2:30; /**< \brief \internal Reserved */
+} Ifx_VADC_KRST0_Bits;
+
+/** \brief Kernel Reset Register 1 */
+typedef struct _Ifx_VADC_KRST1_Bits
+{
+ unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_VADC_KRST1_Bits;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef struct _Ifx_VADC_KRSTCLR_Bits
+{
+ unsigned int CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
+ unsigned int reserved_1:31; /**< \brief \internal Reserved */
+} Ifx_VADC_KRSTCLR_Bits;
+
+/** \brief OCDS Control and Status Register */
+typedef struct _Ifx_VADC_OCS_Bits
+{
+ unsigned int TGS:2; /**< \brief [1:0] Trigger Set for OTGB0/1 (rw) */
+ unsigned int TGB:1; /**< \brief [2:2] OTGB0/1 Bus Select (rw) */
+ unsigned int TG_P:1; /**< \brief [3:3] TGS, TGB Write Protection (w) */
+ unsigned int reserved_4:20; /**< \brief \internal Reserved */
+ unsigned int SUS:4; /**< \brief [27:24] OCDS Suspend Control (rw) */
+ unsigned int SUS_P:1; /**< \brief [28:28] SUS Write Protection (w) */
+ unsigned int SUSSTA:1; /**< \brief [29:29] Suspend State (rh) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_VADC_OCS_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Vadc_union
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_ACCEN0_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_ACCEN0;
+
+/** \brief Access Protection Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_ACCPROT0_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_ACCPROT0;
+
+/** \brief Access Protection Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_ACCPROT1_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_ACCPROT1;
+
+/** \brief Background Request Source Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_BRSCTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_BRSCTRL;
+
+/** \brief Background Request Source Mode Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_BRSMR_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_BRSMR;
+
+/** \brief Background Request Source Pending Register, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_BRSPND_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_BRSPND;
+
+/** \brief Background Request Source Channel Select Register, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_BRSSEL_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_BRSSEL;
+
+/** \brief Clock Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_CLC_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_CLC;
+
+/** \brief External Multiplexer Select Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_EMUXSEL_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_EMUXSEL;
+
+/** \brief Alias Register, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_ALIAS_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_ALIAS;
+
+/** \brief Arbitration Configuration Register, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_ARBCFG_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_ARBCFG;
+
+/** \brief Arbitration Priority Register, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_ARBPR_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_ARBPR;
+
+/** \brief Autoscan Source Control Register, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_ASCTRL_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_ASCTRL;
+
+/** \brief Autoscan Source Mode Register, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_ASMR_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_ASMR;
+
+/** \brief Autoscan Source Pending Register, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_ASPND_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_ASPND;
+
+/** \brief Autoscan Source Channel Select Register, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_ASSEL_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_ASSEL;
+
+/** \brief Boundary Flag Register, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_BFL_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_BFL;
+
+/** \brief Boundary Flag Control Register, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_BFLC_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_BFLC;
+
+/** \brief Boundary Flag Node Pointer Register, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_BFLNP_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_BFLNP;
+
+/** \brief Boundary Flag Software Register, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_BFLS_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_BFLS;
+
+/** \brief Boundary Select Register, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_BOUND_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_BOUND;
+
+/** \brief Channel Event Flag Clear Register, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_CEFCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_CEFCLR;
+
+/** \brief Channel Event Flag Register, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_CEFLAG_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_CEFLAG;
+
+/** \brief Channel Event Node Pointer Register 0, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_CEVNP0_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_CEVNP0;
+
+/** \brief Channel Event Node Pointer Register 1, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_CEVNP1_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_CEVNP1;
+
+/** \brief Channel Assignment Register, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_CHASS_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_CHASS;
+
+/** \brief Group, Channel Ctrl. Reg. */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_CHCTR_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_CHCTR;
+
+/** \brief External Multiplexer Control Register, Group x */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_EMUXCTR_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_EMUXCTR;
+
+/** \brief Queue 0 Register 0, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_Q0R0_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_Q0R0;
+
+/** \brief Queue 0 Backup Register, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_QBUR0_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_QBUR0;
+
+/** \brief Queue 0 Source Control Register, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_QCTRL0_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_QCTRL0;
+
+/** \brief Queue 0 Input Register, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_QINR0_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_QINR0;
+
+/** \brief Queue 0 Mode Register, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_QMR0_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_QMR0;
+
+/** \brief Queue 0 Status Register, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_QSR0_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_QSR0;
+
+/** \brief Group Result Control Reg. */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_RCR_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_RCR;
+
+/** \brief Result Event Flag Clear Register, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_REFCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_REFCLR;
+
+/** \brief Result Event Flag Register, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_REFLAG_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_REFLAG;
+
+/** \brief Group Result Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_RES_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_RES;
+
+/** \brief Group Result Reg., Debug */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_RESD_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_RESD;
+
+/** \brief Result Event Node Pointer Register 0, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_REVNP0_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_REVNP0;
+
+/** \brief Result Event Node Pointer Register 1, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_REVNP1_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_REVNP1;
+
+/** \brief Result Assignment Register, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_RRASS_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_RRASS;
+
+/** \brief Source Event Flag Clear Register, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_SEFCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_SEFCLR;
+
+/** \brief Source Event Flag Register, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_SEFLAG_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_SEFLAG;
+
+/** \brief Source Event Node Pointer Register, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_SEVNP_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_SEVNP;
+
+/** \brief Service Request Software Activation Trigger, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_SRACT_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_SRACT;
+
+/** \brief Synchronization Control Register, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_SYNCTR_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_SYNCTR;
+
+/** \brief Valid Flag Register, Group */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_G_VFR_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_G_VFR;
+
+/** \brief Global Boundary Select Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_GLOBBOUND_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_GLOBBOUND;
+
+/** \brief Global Configuration Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_GLOBCFG_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_GLOBCFG;
+
+/** \brief Global Event Flag Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_GLOBEFLAG_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_GLOBEFLAG;
+
+/** \brief Global Event Node Pointer Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_GLOBEVNP_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_GLOBEVNP;
+
+/** \brief Global Result Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_GLOBRCR_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_GLOBRCR;
+
+/** \brief Global Result Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_GLOBRES_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_GLOBRES;
+
+/** \brief Global Result Register, Debug */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_GLOBRESD_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_GLOBRESD;
+
+/** \brief Global Test Functions Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_GLOBTF_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_GLOBTF;
+
+/** \brief Input Class Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_ICLASS_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_ICLASS;
+
+/** \brief Module Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_ID;
+
+/** \brief Kernel Reset Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_KRST0_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_KRST0;
+
+/** \brief Kernel Reset Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_KRST1_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_KRST1;
+
+/** \brief Kernel Reset Status Clear Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_KRSTCLR_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_KRSTCLR;
+
+/** \brief OCDS Control and Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_VADC_OCS_Bits B; /**< \brief Bitfield access */
+} Ifx_VADC_OCS;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Vadc_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L1
+ * \{ */
+
+/** \brief Group objects */
+typedef volatile struct _Ifx_VADC_G
+{
+ Ifx_VADC_G_ARBCFG ARBCFG; /**< \brief 0, Arbitration Configuration Register, Group */
+ Ifx_VADC_G_ARBPR ARBPR; /**< \brief 4, Arbitration Priority Register, Group */
+ Ifx_VADC_G_CHASS CHASS; /**< \brief 8, Channel Assignment Register, Group */
+ Ifx_VADC_G_RRASS RRASS; /**< \brief C, Result Assignment Register, Group */
+ unsigned char reserved_10[16]; /**< \brief 10, \internal Reserved */
+ Ifx_VADC_ICLASS ICLASS[2]; /**< \brief 20, Input Class Register */
+ unsigned char reserved_28[8]; /**< \brief 28, \internal Reserved */
+ Ifx_VADC_G_ALIAS ALIAS; /**< \brief 30, Alias Register, Group */
+ unsigned char reserved_34[4]; /**< \brief 34, \internal Reserved */
+ Ifx_VADC_G_BOUND BOUND; /**< \brief 38, Boundary Select Register, Group */
+ unsigned char reserved_3C[4]; /**< \brief 3C, \internal Reserved */
+ Ifx_VADC_G_SYNCTR SYNCTR; /**< \brief 40, Synchronization Control Register, Group */
+ unsigned char reserved_44[4]; /**< \brief 44, \internal Reserved */
+ Ifx_VADC_G_BFL BFL; /**< \brief 48, Boundary Flag Register, Group */
+ Ifx_VADC_G_BFLS BFLS; /**< \brief 4C, Boundary Flag Software Register, Group */
+ Ifx_VADC_G_BFLC BFLC; /**< \brief 50, Boundary Flag Control Register, Group */
+ Ifx_VADC_G_BFLNP BFLNP; /**< \brief 54, Boundary Flag Node Pointer Register, Group */
+ unsigned char reserved_58[40]; /**< \brief 58, \internal Reserved */
+ Ifx_VADC_G_QCTRL0 QCTRL0; /**< \brief 80, Queue 0 Source Control Register, Group */
+ Ifx_VADC_G_QMR0 QMR0; /**< \brief 84, Queue 0 Mode Register, Group */
+ Ifx_VADC_G_QSR0 QSR0; /**< \brief 88, Queue 0 Status Register, Group */
+ Ifx_VADC_G_Q0R0 Q0R0; /**< \brief 8C, Queue 0 Register 0, Group */
+ union
+ {
+ Ifx_VADC_G_QBUR0 QBUR0; /**< \brief 90, Queue 0 Input Register, Group */
+ Ifx_VADC_G_QINR0 QINR0; /**< \brief 90, Queue 0 Input Register, Group */
+ };
+
+ unsigned char reserved_94[12]; /**< \brief 94, \internal Reserved */
+ Ifx_VADC_G_ASCTRL ASCTRL; /**< \brief A0, Autoscan Source Control Register, Group */
+ Ifx_VADC_G_ASMR ASMR; /**< \brief A4, Autoscan Source Mode Register, Group */
+ Ifx_VADC_G_ASSEL ASSEL; /**< \brief A8, Autoscan Source Channel Select Register, Group */
+ Ifx_VADC_G_ASPND ASPND; /**< \brief AC, Autoscan Source Pending Register, Group */
+ unsigned char reserved_B0[80]; /**< \brief B0, \internal Reserved */
+ Ifx_VADC_G_CEFLAG CEFLAG; /**< \brief 100, Channel Event Flag Register, Group */
+ Ifx_VADC_G_REFLAG REFLAG; /**< \brief 104, Result Event Flag Register, Group */
+ Ifx_VADC_G_SEFLAG SEFLAG; /**< \brief 108, Source Event Flag Register, Group */
+ unsigned char reserved_10C[4]; /**< \brief 10C, \internal Reserved */
+ Ifx_VADC_G_CEFCLR CEFCLR; /**< \brief 110, Channel Event Flag Clear Register, Group */
+ Ifx_VADC_G_REFCLR REFCLR; /**< \brief 114, Result Event Flag Clear Register, Group */
+ Ifx_VADC_G_SEFCLR SEFCLR; /**< \brief 118, Source Event Flag Clear Register, Group */
+ unsigned char reserved_11C[4]; /**< \brief 11C, \internal Reserved */
+ Ifx_VADC_G_CEVNP0 CEVNP0; /**< \brief 120, Channel Event Node Pointer Register 0, Group */
+ Ifx_VADC_G_CEVNP1 CEVNP1; /**< \brief 124, Channel Event Node Pointer Register 1, Group */
+ unsigned char reserved_128[8]; /**< \brief 128, \internal Reserved */
+ Ifx_VADC_G_REVNP0 REVNP0; /**< \brief 130, Result Event Node Pointer Register 0, Group */
+ Ifx_VADC_G_REVNP1 REVNP1; /**< \brief 134, Result Event Node Pointer Register 1, Group */
+ unsigned char reserved_138[8]; /**< \brief 138, \internal Reserved */
+ Ifx_VADC_G_SEVNP SEVNP; /**< \brief 140, Source Event Node Pointer Register, Group */
+ unsigned char reserved_144[4]; /**< \brief 144, \internal Reserved */
+ Ifx_VADC_G_SRACT SRACT; /**< \brief 148, Service Request Software Activation Trigger, Group */
+ unsigned char reserved_14C[36]; /**< \brief 14C, \internal Reserved */
+ Ifx_VADC_G_EMUXCTR EMUXCTR; /**< \brief 170, External Multiplexer Control Register, Group x */
+ unsigned char reserved_174[4]; /**< \brief 174, \internal Reserved */
+ Ifx_VADC_G_VFR VFR; /**< \brief 178, Valid Flag Register, Group */
+ unsigned char reserved_17C[4]; /**< \brief 17C, \internal Reserved */
+ Ifx_VADC_G_CHCTR CHCTR[16]; /**< \brief 180, Group, Channel Ctrl. Reg. */
+ unsigned char reserved_1C0[64]; /**< \brief 1C0, \internal Reserved */
+ Ifx_VADC_G_RCR RCR[16]; /**< \brief 200, Group Result Control Reg. */
+ unsigned char reserved_240[64]; /**< \brief 240, \internal Reserved */
+ Ifx_VADC_G_RES RES[16]; /**< \brief 280, Group Result Register */
+ unsigned char reserved_2C0[64]; /**< \brief 2C0, \internal Reserved */
+ Ifx_VADC_G_RESD RESD[16]; /**< \brief 300, Group Result Reg., Debug */
+ unsigned char reserved_340[192]; /**< \brief 340, \internal Reserved */
+} Ifx_VADC_G;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Vadc_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief VADC object */
+typedef volatile struct _Ifx_VADC
+{
+ Ifx_VADC_CLC CLC; /**< \brief 0, Clock Control Register */
+ unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
+ Ifx_VADC_ID ID; /**< \brief 8, Module Identification Register */
+ unsigned char reserved_C[28]; /**< \brief C, \internal Reserved */
+ Ifx_VADC_OCS OCS; /**< \brief 28, OCDS Control and Status Register */
+ Ifx_VADC_KRSTCLR KRSTCLR; /**< \brief 2C, Kernel Reset Status Clear Register */
+ Ifx_VADC_KRST1 KRST1; /**< \brief 30, Kernel Reset Register 1 */
+ Ifx_VADC_KRST0 KRST0; /**< \brief 34, Kernel Reset Register 0 */
+ unsigned char reserved_38[4]; /**< \brief 38, \internal Reserved */
+ Ifx_VADC_ACCEN0 ACCEN0; /**< \brief 3C, Access Enable Register 0 */
+ unsigned char reserved_40[64]; /**< \brief 40, \internal Reserved */
+ Ifx_VADC_GLOBCFG GLOBCFG; /**< \brief 80, Global Configuration Register */
+ unsigned char reserved_84[4]; /**< \brief 84, \internal Reserved */
+ Ifx_VADC_ACCPROT0 ACCPROT0; /**< \brief 88, Access Protection Register */
+ Ifx_VADC_ACCPROT1 ACCPROT1; /**< \brief 8C, Access Protection Register */
+ unsigned char reserved_90[16]; /**< \brief 90, \internal Reserved */
+ Ifx_VADC_ICLASS GLOBICLASS[2]; /**< \brief A0, Input Class Register */
+ unsigned char reserved_A8[16]; /**< \brief A8, \internal Reserved */
+ Ifx_VADC_GLOBBOUND GLOBBOUND; /**< \brief B8, Global Boundary Select Register */
+ unsigned char reserved_BC[36]; /**< \brief BC, \internal Reserved */
+ Ifx_VADC_GLOBEFLAG GLOBEFLAG; /**< \brief E0, Global Event Flag Register */
+ unsigned char reserved_E4[92]; /**< \brief E4, \internal Reserved */
+ Ifx_VADC_GLOBEVNP GLOBEVNP; /**< \brief 140, Global Event Node Pointer Register */
+ unsigned char reserved_144[28]; /**< \brief 144, \internal Reserved */
+ Ifx_VADC_GLOBTF GLOBTF; /**< \brief 160, Global Test Functions Register */
+ unsigned char reserved_164[28]; /**< \brief 164, \internal Reserved */
+ Ifx_VADC_BRSSEL BRSSEL[4]; /**< \brief 180, Background Request Source Channel Select Register, Group */
+ unsigned char reserved_190[48]; /**< \brief 190, \internal Reserved */
+ Ifx_VADC_BRSPND BRSPND[4]; /**< \brief 1C0, Background Request Source Pending Register, Group */
+ unsigned char reserved_1D0[48]; /**< \brief 1D0, \internal Reserved */
+ Ifx_VADC_BRSCTRL BRSCTRL; /**< \brief 200, Background Request Source Control Register */
+ Ifx_VADC_BRSMR BRSMR; /**< \brief 204, Background Request Source Mode Register */
+ unsigned char reserved_208[120]; /**< \brief 208, \internal Reserved */
+ Ifx_VADC_GLOBRCR GLOBRCR; /**< \brief 280, Global Result Control Register */
+ unsigned char reserved_284[124]; /**< \brief 284, \internal Reserved */
+ Ifx_VADC_GLOBRES GLOBRES; /**< \brief 300, Global Result Register */
+ unsigned char reserved_304[124]; /**< \brief 304, \internal Reserved */
+ Ifx_VADC_GLOBRESD GLOBRESD; /**< \brief 380, Global Result Register, Debug */
+ unsigned char reserved_384[108]; /**< \brief 384, \internal Reserved */
+ Ifx_VADC_EMUXSEL EMUXSEL; /**< \brief 3F0, External Multiplexer Select Register */
+ unsigned char reserved_3F4[140]; /**< \brief 3F4, \internal Reserved */
+ Ifx_VADC_G G[4]; /**< \brief 480, Group objects */
+ unsigned char reserved_1480[11136]; /**< \brief 1480, \internal Reserved */
+} Ifx_VADC;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#if defined (__TASKING__)
+#pragma warning restore
+#endif
+/******************************************************************************/
+#endif /* IFXVADC_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxXbar_bf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxXbar_bf.h
new file mode 100644
index 0000000..22f5e66
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxXbar_bf.h
@@ -0,0 +1,1251 @@
+/**
+ * \file IfxXbar_bf.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Xbar_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Xbar
+ *
+ */
+#ifndef IFXXBAR_BF_H
+#define IFXXBAR_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Xbar_BitfieldsMask
+ * \{ */
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN0 */
+#define IFX_XBAR_ACCEN0_EN0_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN0 */
+#define IFX_XBAR_ACCEN0_EN0_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN0 */
+#define IFX_XBAR_ACCEN0_EN0_OFF (0u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN10 */
+#define IFX_XBAR_ACCEN0_EN10_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN10 */
+#define IFX_XBAR_ACCEN0_EN10_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN10 */
+#define IFX_XBAR_ACCEN0_EN10_OFF (10u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN11 */
+#define IFX_XBAR_ACCEN0_EN11_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN11 */
+#define IFX_XBAR_ACCEN0_EN11_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN11 */
+#define IFX_XBAR_ACCEN0_EN11_OFF (11u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN12 */
+#define IFX_XBAR_ACCEN0_EN12_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN12 */
+#define IFX_XBAR_ACCEN0_EN12_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN12 */
+#define IFX_XBAR_ACCEN0_EN12_OFF (12u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN13 */
+#define IFX_XBAR_ACCEN0_EN13_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN13 */
+#define IFX_XBAR_ACCEN0_EN13_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN13 */
+#define IFX_XBAR_ACCEN0_EN13_OFF (13u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN14 */
+#define IFX_XBAR_ACCEN0_EN14_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN14 */
+#define IFX_XBAR_ACCEN0_EN14_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN14 */
+#define IFX_XBAR_ACCEN0_EN14_OFF (14u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN15 */
+#define IFX_XBAR_ACCEN0_EN15_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN15 */
+#define IFX_XBAR_ACCEN0_EN15_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN15 */
+#define IFX_XBAR_ACCEN0_EN15_OFF (15u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN16 */
+#define IFX_XBAR_ACCEN0_EN16_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN16 */
+#define IFX_XBAR_ACCEN0_EN16_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN16 */
+#define IFX_XBAR_ACCEN0_EN16_OFF (16u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN17 */
+#define IFX_XBAR_ACCEN0_EN17_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN17 */
+#define IFX_XBAR_ACCEN0_EN17_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN17 */
+#define IFX_XBAR_ACCEN0_EN17_OFF (17u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN18 */
+#define IFX_XBAR_ACCEN0_EN18_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN18 */
+#define IFX_XBAR_ACCEN0_EN18_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN18 */
+#define IFX_XBAR_ACCEN0_EN18_OFF (18u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN19 */
+#define IFX_XBAR_ACCEN0_EN19_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN19 */
+#define IFX_XBAR_ACCEN0_EN19_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN19 */
+#define IFX_XBAR_ACCEN0_EN19_OFF (19u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN1 */
+#define IFX_XBAR_ACCEN0_EN1_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN1 */
+#define IFX_XBAR_ACCEN0_EN1_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN1 */
+#define IFX_XBAR_ACCEN0_EN1_OFF (1u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN20 */
+#define IFX_XBAR_ACCEN0_EN20_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN20 */
+#define IFX_XBAR_ACCEN0_EN20_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN20 */
+#define IFX_XBAR_ACCEN0_EN20_OFF (20u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN21 */
+#define IFX_XBAR_ACCEN0_EN21_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN21 */
+#define IFX_XBAR_ACCEN0_EN21_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN21 */
+#define IFX_XBAR_ACCEN0_EN21_OFF (21u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN22 */
+#define IFX_XBAR_ACCEN0_EN22_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN22 */
+#define IFX_XBAR_ACCEN0_EN22_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN22 */
+#define IFX_XBAR_ACCEN0_EN22_OFF (22u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN23 */
+#define IFX_XBAR_ACCEN0_EN23_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN23 */
+#define IFX_XBAR_ACCEN0_EN23_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN23 */
+#define IFX_XBAR_ACCEN0_EN23_OFF (23u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN24 */
+#define IFX_XBAR_ACCEN0_EN24_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN24 */
+#define IFX_XBAR_ACCEN0_EN24_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN24 */
+#define IFX_XBAR_ACCEN0_EN24_OFF (24u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN25 */
+#define IFX_XBAR_ACCEN0_EN25_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN25 */
+#define IFX_XBAR_ACCEN0_EN25_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN25 */
+#define IFX_XBAR_ACCEN0_EN25_OFF (25u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN26 */
+#define IFX_XBAR_ACCEN0_EN26_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN26 */
+#define IFX_XBAR_ACCEN0_EN26_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN26 */
+#define IFX_XBAR_ACCEN0_EN26_OFF (26u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN27 */
+#define IFX_XBAR_ACCEN0_EN27_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN27 */
+#define IFX_XBAR_ACCEN0_EN27_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN27 */
+#define IFX_XBAR_ACCEN0_EN27_OFF (27u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN28 */
+#define IFX_XBAR_ACCEN0_EN28_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN28 */
+#define IFX_XBAR_ACCEN0_EN28_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN28 */
+#define IFX_XBAR_ACCEN0_EN28_OFF (28u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN29 */
+#define IFX_XBAR_ACCEN0_EN29_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN29 */
+#define IFX_XBAR_ACCEN0_EN29_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN29 */
+#define IFX_XBAR_ACCEN0_EN29_OFF (29u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN2 */
+#define IFX_XBAR_ACCEN0_EN2_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN2 */
+#define IFX_XBAR_ACCEN0_EN2_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN2 */
+#define IFX_XBAR_ACCEN0_EN2_OFF (2u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN30 */
+#define IFX_XBAR_ACCEN0_EN30_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN30 */
+#define IFX_XBAR_ACCEN0_EN30_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN30 */
+#define IFX_XBAR_ACCEN0_EN30_OFF (30u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN31 */
+#define IFX_XBAR_ACCEN0_EN31_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN31 */
+#define IFX_XBAR_ACCEN0_EN31_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN31 */
+#define IFX_XBAR_ACCEN0_EN31_OFF (31u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN3 */
+#define IFX_XBAR_ACCEN0_EN3_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN3 */
+#define IFX_XBAR_ACCEN0_EN3_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN3 */
+#define IFX_XBAR_ACCEN0_EN3_OFF (3u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN4 */
+#define IFX_XBAR_ACCEN0_EN4_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN4 */
+#define IFX_XBAR_ACCEN0_EN4_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN4 */
+#define IFX_XBAR_ACCEN0_EN4_OFF (4u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN5 */
+#define IFX_XBAR_ACCEN0_EN5_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN5 */
+#define IFX_XBAR_ACCEN0_EN5_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN5 */
+#define IFX_XBAR_ACCEN0_EN5_OFF (5u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN6 */
+#define IFX_XBAR_ACCEN0_EN6_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN6 */
+#define IFX_XBAR_ACCEN0_EN6_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN6 */
+#define IFX_XBAR_ACCEN0_EN6_OFF (6u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN7 */
+#define IFX_XBAR_ACCEN0_EN7_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN7 */
+#define IFX_XBAR_ACCEN0_EN7_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN7 */
+#define IFX_XBAR_ACCEN0_EN7_OFF (7u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN8 */
+#define IFX_XBAR_ACCEN0_EN8_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN8 */
+#define IFX_XBAR_ACCEN0_EN8_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN8 */
+#define IFX_XBAR_ACCEN0_EN8_OFF (8u)
+
+/** \brief Length for Ifx_XBAR_ACCEN0_Bits.EN9 */
+#define IFX_XBAR_ACCEN0_EN9_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ACCEN0_Bits.EN9 */
+#define IFX_XBAR_ACCEN0_EN9_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ACCEN0_Bits.EN9 */
+#define IFX_XBAR_ACCEN0_EN9_OFF (9u)
+
+/** \brief Length for Ifx_XBAR_ARBCON_Bits.INTACK */
+#define IFX_XBAR_ARBCON_INTACK_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ARBCON_Bits.INTACK */
+#define IFX_XBAR_ARBCON_INTACK_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ARBCON_Bits.INTACK */
+#define IFX_XBAR_ARBCON_INTACK_OFF (4u)
+
+/** \brief Length for Ifx_XBAR_ARBCON_Bits.PRERREN */
+#define IFX_XBAR_ARBCON_PRERREN_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ARBCON_Bits.PRERREN */
+#define IFX_XBAR_ARBCON_PRERREN_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ARBCON_Bits.PRERREN */
+#define IFX_XBAR_ARBCON_PRERREN_OFF (0u)
+
+/** \brief Length for Ifx_XBAR_ARBCON_Bits.SCERREN */
+#define IFX_XBAR_ARBCON_SCERREN_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ARBCON_Bits.SCERREN */
+#define IFX_XBAR_ARBCON_SCERREN_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ARBCON_Bits.SCERREN */
+#define IFX_XBAR_ARBCON_SCERREN_OFF (1u)
+
+/** \brief Length for Ifx_XBAR_ARBCON_Bits.SETPRINT */
+#define IFX_XBAR_ARBCON_SETPRINT_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ARBCON_Bits.SETPRINT */
+#define IFX_XBAR_ARBCON_SETPRINT_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ARBCON_Bits.SETPRINT */
+#define IFX_XBAR_ARBCON_SETPRINT_OFF (2u)
+
+/** \brief Length for Ifx_XBAR_ARBCON_Bits.SETSCINT */
+#define IFX_XBAR_ARBCON_SETSCINT_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ARBCON_Bits.SETSCINT */
+#define IFX_XBAR_ARBCON_SETSCINT_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ARBCON_Bits.SETSCINT */
+#define IFX_XBAR_ARBCON_SETSCINT_OFF (3u)
+
+/** \brief Length for Ifx_XBAR_ARBCON_Bits.SPC */
+#define IFX_XBAR_ARBCON_SPC_LEN (12u)
+
+/** \brief Mask for Ifx_XBAR_ARBCON_Bits.SPC */
+#define IFX_XBAR_ARBCON_SPC_MSK (0xfffu)
+
+/** \brief Offset for Ifx_XBAR_ARBCON_Bits.SPC */
+#define IFX_XBAR_ARBCON_SPC_OFF (20u)
+
+/** \brief Length for Ifx_XBAR_ARBITER0_DBADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER0_DBADD_ADDRESS_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ARBITER0_DBADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER0_DBADD_ADDRESS_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ARBITER0_DBADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER0_DBADD_ADDRESS_OFF (27u)
+
+/** \brief Length for Ifx_XBAR_ARBITER0_DBMADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER0_DBMADD_ADDRESS_LEN (19u)
+
+/** \brief Mask for Ifx_XBAR_ARBITER0_DBMADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER0_DBMADD_ADDRESS_MSK (0x7ffffu)
+
+/** \brief Offset for Ifx_XBAR_ARBITER0_DBMADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER0_DBMADD_ADDRESS_OFF (2u)
+
+/** \brief Length for Ifx_XBAR_ARBITER1_DBADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER1_DBADD_ADDRESS_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ARBITER1_DBADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER1_DBADD_ADDRESS_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ARBITER1_DBADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER1_DBADD_ADDRESS_OFF (31u)
+
+/** \brief Length for Ifx_XBAR_ARBITER1_DBMADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER1_DBMADD_ADDRESS_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ARBITER1_DBMADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER1_DBMADD_ADDRESS_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ARBITER1_DBMADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER1_DBMADD_ADDRESS_OFF (31u)
+
+/** \brief Length for Ifx_XBAR_ARBITER4_DBADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER4_DBADD_ADDRESS_LEN (29u)
+
+/** \brief Mask for Ifx_XBAR_ARBITER4_DBADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER4_DBADD_ADDRESS_MSK (0x1fffffffu)
+
+/** \brief Offset for Ifx_XBAR_ARBITER4_DBADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER4_DBADD_ADDRESS_OFF (2u)
+
+/** \brief Length for Ifx_XBAR_ARBITER4_DBMADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER4_DBMADD_ADDRESS_LEN (29u)
+
+/** \brief Mask for Ifx_XBAR_ARBITER4_DBMADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER4_DBMADD_ADDRESS_MSK (0x1fffffffu)
+
+/** \brief Offset for Ifx_XBAR_ARBITER4_DBMADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER4_DBMADD_ADDRESS_OFF (2u)
+
+/** \brief Length for Ifx_XBAR_ARBITER6_DBADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER6_DBADD_ADDRESS_LEN (3u)
+
+/** \brief Mask for Ifx_XBAR_ARBITER6_DBADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER6_DBADD_ADDRESS_MSK (0x7u)
+
+/** \brief Offset for Ifx_XBAR_ARBITER6_DBADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER6_DBADD_ADDRESS_OFF (28u)
+
+/** \brief Length for Ifx_XBAR_ARBITER6_DBMADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER6_DBMADD_ADDRESS_LEN (3u)
+
+/** \brief Mask for Ifx_XBAR_ARBITER6_DBMADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER6_DBMADD_ADDRESS_MSK (0x7u)
+
+/** \brief Offset for Ifx_XBAR_ARBITER6_DBMADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER6_DBMADD_ADDRESS_OFF (28u)
+
+/** \brief Length for Ifx_XBAR_ARBITER7_DBADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER7_DBADD_ADDRESS_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ARBITER7_DBADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER7_DBADD_ADDRESS_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ARBITER7_DBADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER7_DBADD_ADDRESS_OFF (29u)
+
+/** \brief Length for Ifx_XBAR_ARBITER7_DBMADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER7_DBMADD_ADDRESS_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ARBITER7_DBMADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER7_DBMADD_ADDRESS_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ARBITER7_DBMADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER7_DBMADD_ADDRESS_OFF (29u)
+
+/** \brief Length for Ifx_XBAR_ARBITER8_DBADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER8_DBADD_ADDRESS_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ARBITER8_DBADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER8_DBADD_ADDRESS_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ARBITER8_DBADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER8_DBADD_ADDRESS_OFF (29u)
+
+/** \brief Length for Ifx_XBAR_ARBITER8_DBMADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER8_DBMADD_ADDRESS_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ARBITER8_DBMADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER8_DBMADD_ADDRESS_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ARBITER8_DBMADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITER8_DBMADD_ADDRESS_OFF (29u)
+
+/** \brief Length for Ifx_XBAR_ARBITERD_DBADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITERD_DBADD_ADDRESS_LEN (30u)
+
+/** \brief Mask for Ifx_XBAR_ARBITERD_DBADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITERD_DBADD_ADDRESS_MSK (0x3fffffffu)
+
+/** \brief Offset for Ifx_XBAR_ARBITERD_DBADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITERD_DBADD_ADDRESS_OFF (2u)
+
+/** \brief Length for Ifx_XBAR_ARBITERD_DBMADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITERD_DBMADD_ADDRESS_LEN (32u)
+
+/** \brief Mask for Ifx_XBAR_ARBITERD_DBMADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITERD_DBMADD_ADDRESS_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_XBAR_ARBITERD_DBMADD_Bits.ADDRESS */
+#define IFX_XBAR_ARBITERD_DBMADD_ADDRESS_OFF (0u)
+
+/** \brief Length for Ifx_XBAR_DBCON_Bits.ADDEN */
+#define IFX_XBAR_DBCON_ADDEN_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_DBCON_Bits.ADDEN */
+#define IFX_XBAR_DBCON_ADDEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_DBCON_Bits.ADDEN */
+#define IFX_XBAR_DBCON_ADDEN_OFF (19u)
+
+/** \brief Length for Ifx_XBAR_DBCON_Bits.DBEN */
+#define IFX_XBAR_DBCON_DBEN_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_DBCON_Bits.DBEN */
+#define IFX_XBAR_DBCON_DBEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_DBCON_Bits.DBEN */
+#define IFX_XBAR_DBCON_DBEN_OFF (0u)
+
+/** \brief Length for Ifx_XBAR_DBCON_Bits.DBSAT */
+#define IFX_XBAR_DBCON_DBSAT_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_DBCON_Bits.DBSAT */
+#define IFX_XBAR_DBCON_DBSAT_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_DBCON_Bits.DBSAT */
+#define IFX_XBAR_DBCON_DBSAT_OFF (1u)
+
+/** \brief Length for Ifx_XBAR_DBCON_Bits.ERREN */
+#define IFX_XBAR_DBCON_ERREN_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_DBCON_Bits.ERREN */
+#define IFX_XBAR_DBCON_ERREN_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_DBCON_Bits.ERREN */
+#define IFX_XBAR_DBCON_ERREN_OFF (20u)
+
+/** \brief Length for Ifx_XBAR_DBCON_Bits.MASEN */
+#define IFX_XBAR_DBCON_MASEN_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_DBCON_Bits.MASEN */
+#define IFX_XBAR_DBCON_MASEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_DBCON_Bits.MASEN */
+#define IFX_XBAR_DBCON_MASEN_OFF (23u)
+
+/** \brief Length for Ifx_XBAR_DBCON_Bits.MASTER */
+#define IFX_XBAR_DBCON_MASTER_LEN (6u)
+
+/** \brief Mask for Ifx_XBAR_DBCON_Bits.MASTER */
+#define IFX_XBAR_DBCON_MASTER_MSK (0x3fu)
+
+/** \brief Offset for Ifx_XBAR_DBCON_Bits.MASTER */
+#define IFX_XBAR_DBCON_MASTER_OFF (24u)
+
+/** \brief Length for Ifx_XBAR_DBCON_Bits.RDEN */
+#define IFX_XBAR_DBCON_RDEN_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_DBCON_Bits.RDEN */
+#define IFX_XBAR_DBCON_RDEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_DBCON_Bits.RDEN */
+#define IFX_XBAR_DBCON_RDEN_OFF (16u)
+
+/** \brief Length for Ifx_XBAR_DBCON_Bits.REARM */
+#define IFX_XBAR_DBCON_REARM_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_DBCON_Bits.REARM */
+#define IFX_XBAR_DBCON_REARM_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_DBCON_Bits.REARM */
+#define IFX_XBAR_DBCON_REARM_OFF (2u)
+
+/** \brief Length for Ifx_XBAR_DBCON_Bits.SETDBEVT */
+#define IFX_XBAR_DBCON_SETDBEVT_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_DBCON_Bits.SETDBEVT */
+#define IFX_XBAR_DBCON_SETDBEVT_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_DBCON_Bits.SETDBEVT */
+#define IFX_XBAR_DBCON_SETDBEVT_OFF (3u)
+
+/** \brief Length for Ifx_XBAR_DBCON_Bits.SVMEN */
+#define IFX_XBAR_DBCON_SVMEN_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_DBCON_Bits.SVMEN */
+#define IFX_XBAR_DBCON_SVMEN_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_DBCON_Bits.SVMEN */
+#define IFX_XBAR_DBCON_SVMEN_OFF (18u)
+
+/** \brief Length for Ifx_XBAR_DBCON_Bits.WREN */
+#define IFX_XBAR_DBCON_WREN_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_DBCON_Bits.WREN */
+#define IFX_XBAR_DBCON_WREN_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_DBCON_Bits.WREN */
+#define IFX_XBAR_DBCON_WREN_OFF (17u)
+
+/** \brief Length for Ifx_XBAR_DBSAT_Bits.SCI0 */
+#define IFX_XBAR_DBSAT_SCI0_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_DBSAT_Bits.SCI0 */
+#define IFX_XBAR_DBSAT_SCI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_DBSAT_Bits.SCI0 */
+#define IFX_XBAR_DBSAT_SCI0_OFF (0u)
+
+/** \brief Length for Ifx_XBAR_DBSAT_Bits.SCI1 */
+#define IFX_XBAR_DBSAT_SCI1_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_DBSAT_Bits.SCI1 */
+#define IFX_XBAR_DBSAT_SCI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_DBSAT_Bits.SCI1 */
+#define IFX_XBAR_DBSAT_SCI1_OFF (1u)
+
+/** \brief Length for Ifx_XBAR_DBSAT_Bits.SCI4 */
+#define IFX_XBAR_DBSAT_SCI4_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_DBSAT_Bits.SCI4 */
+#define IFX_XBAR_DBSAT_SCI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_DBSAT_Bits.SCI4 */
+#define IFX_XBAR_DBSAT_SCI4_OFF (4u)
+
+/** \brief Length for Ifx_XBAR_DBSAT_Bits.SCI6 */
+#define IFX_XBAR_DBSAT_SCI6_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_DBSAT_Bits.SCI6 */
+#define IFX_XBAR_DBSAT_SCI6_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_DBSAT_Bits.SCI6 */
+#define IFX_XBAR_DBSAT_SCI6_OFF (6u)
+
+/** \brief Length for Ifx_XBAR_DBSAT_Bits.SCI7 */
+#define IFX_XBAR_DBSAT_SCI7_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_DBSAT_Bits.SCI7 */
+#define IFX_XBAR_DBSAT_SCI7_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_DBSAT_Bits.SCI7 */
+#define IFX_XBAR_DBSAT_SCI7_OFF (7u)
+
+/** \brief Length for Ifx_XBAR_DBSAT_Bits.SCI8 */
+#define IFX_XBAR_DBSAT_SCI8_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_DBSAT_Bits.SCI8 */
+#define IFX_XBAR_DBSAT_SCI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_DBSAT_Bits.SCI8 */
+#define IFX_XBAR_DBSAT_SCI8_OFF (8u)
+
+/** \brief Length for Ifx_XBAR_DBSAT_Bits.SCID */
+#define IFX_XBAR_DBSAT_SCID_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_DBSAT_Bits.SCID */
+#define IFX_XBAR_DBSAT_SCID_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_DBSAT_Bits.SCID */
+#define IFX_XBAR_DBSAT_SCID_OFF (15u)
+
+/** \brief Length for Ifx_XBAR_ERR_Bits.ADDR_ECC */
+#define IFX_XBAR_ERR_ADDR_ECC_LEN (8u)
+
+/** \brief Mask for Ifx_XBAR_ERR_Bits.ADDR_ECC */
+#define IFX_XBAR_ERR_ADDR_ECC_MSK (0xffu)
+
+/** \brief Offset for Ifx_XBAR_ERR_Bits.ADDR_ECC */
+#define IFX_XBAR_ERR_ADDR_ECC_OFF (16u)
+
+/** \brief Length for Ifx_XBAR_ERR_Bits.MCI_SBS */
+#define IFX_XBAR_ERR_MCI_SBS_LEN (8u)
+
+/** \brief Mask for Ifx_XBAR_ERR_Bits.MCI_SBS */
+#define IFX_XBAR_ERR_MCI_SBS_MSK (0xffu)
+
+/** \brief Offset for Ifx_XBAR_ERR_Bits.MCI_SBS */
+#define IFX_XBAR_ERR_MCI_SBS_OFF (24u)
+
+/** \brief Length for Ifx_XBAR_ERR_Bits.OPC */
+#define IFX_XBAR_ERR_OPC_LEN (4u)
+
+/** \brief Mask for Ifx_XBAR_ERR_Bits.OPC */
+#define IFX_XBAR_ERR_OPC_MSK (0xfu)
+
+/** \brief Offset for Ifx_XBAR_ERR_Bits.OPC */
+#define IFX_XBAR_ERR_OPC_OFF (4u)
+
+/** \brief Length for Ifx_XBAR_ERR_Bits.RD */
+#define IFX_XBAR_ERR_RD_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ERR_Bits.RD */
+#define IFX_XBAR_ERR_RD_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ERR_Bits.RD */
+#define IFX_XBAR_ERR_RD_OFF (0u)
+
+/** \brief Length for Ifx_XBAR_ERR_Bits.SVM */
+#define IFX_XBAR_ERR_SVM_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ERR_Bits.SVM */
+#define IFX_XBAR_ERR_SVM_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ERR_Bits.SVM */
+#define IFX_XBAR_ERR_SVM_OFF (2u)
+
+/** \brief Length for Ifx_XBAR_ERR_Bits.TR_ID */
+#define IFX_XBAR_ERR_TR_ID_LEN (8u)
+
+/** \brief Mask for Ifx_XBAR_ERR_Bits.TR_ID */
+#define IFX_XBAR_ERR_TR_ID_MSK (0xffu)
+
+/** \brief Offset for Ifx_XBAR_ERR_Bits.TR_ID */
+#define IFX_XBAR_ERR_TR_ID_OFF (8u)
+
+/** \brief Length for Ifx_XBAR_ERR_Bits.WR */
+#define IFX_XBAR_ERR_WR_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_ERR_Bits.WR */
+#define IFX_XBAR_ERR_WR_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_ERR_Bits.WR */
+#define IFX_XBAR_ERR_WR_OFF (1u)
+
+/** \brief Length for Ifx_XBAR_ERRADDR_Bits.ADDR */
+#define IFX_XBAR_ERRADDR_ADDR_LEN (32u)
+
+/** \brief Mask for Ifx_XBAR_ERRADDR_Bits.ADDR */
+#define IFX_XBAR_ERRADDR_ADDR_MSK (0xffffffffu)
+
+/** \brief Offset for Ifx_XBAR_ERRADDR_Bits.ADDR */
+#define IFX_XBAR_ERRADDR_ADDR_OFF (0u)
+
+/** \brief Length for Ifx_XBAR_EXTCOND_Bits.FREQDISF */
+#define IFX_XBAR_EXTCOND_FREQDISF_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_EXTCOND_Bits.FREQDISF */
+#define IFX_XBAR_EXTCOND_FREQDISF_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_EXTCOND_Bits.FREQDISF */
+#define IFX_XBAR_EXTCOND_FREQDISF_OFF (6u)
+
+/** \brief Length for Ifx_XBAR_EXTCOND_Bits.MAX_WS */
+#define IFX_XBAR_EXTCOND_MAX_WS_LEN (7u)
+
+/** \brief Mask for Ifx_XBAR_EXTCOND_Bits.MAX_WS */
+#define IFX_XBAR_EXTCOND_MAX_WS_MSK (0x7fu)
+
+/** \brief Offset for Ifx_XBAR_EXTCOND_Bits.MAX_WS */
+#define IFX_XBAR_EXTCOND_MAX_WS_OFF (13u)
+
+/** \brief Length for Ifx_XBAR_EXTCOND_Bits.NODELTR */
+#define IFX_XBAR_EXTCOND_NODELTR_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_EXTCOND_Bits.NODELTR */
+#define IFX_XBAR_EXTCOND_NODELTR_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_EXTCOND_Bits.NODELTR */
+#define IFX_XBAR_EXTCOND_NODELTR_OFF (9u)
+
+/** \brief Length for Ifx_XBAR_EXTCOND_Bits.NORMW */
+#define IFX_XBAR_EXTCOND_NORMW_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_EXTCOND_Bits.NORMW */
+#define IFX_XBAR_EXTCOND_NORMW_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_EXTCOND_Bits.NORMW */
+#define IFX_XBAR_EXTCOND_NORMW_OFF (10u)
+
+/** \brief Length for Ifx_XBAR_EXTCOND_Bits.WFWD */
+#define IFX_XBAR_EXTCOND_WFWD_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_EXTCOND_Bits.WFWD */
+#define IFX_XBAR_EXTCOND_WFWD_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_EXTCOND_Bits.WFWD */
+#define IFX_XBAR_EXTCOND_WFWD_OFF (3u)
+
+/** \brief Length for Ifx_XBAR_ID_Bits.MODNUMBER */
+#define IFX_XBAR_ID_MODNUMBER_LEN (16u)
+
+/** \brief Mask for Ifx_XBAR_ID_Bits.MODNUMBER */
+#define IFX_XBAR_ID_MODNUMBER_MSK (0xffffu)
+
+/** \brief Offset for Ifx_XBAR_ID_Bits.MODNUMBER */
+#define IFX_XBAR_ID_MODNUMBER_OFF (16u)
+
+/** \brief Length for Ifx_XBAR_ID_Bits.MODREV */
+#define IFX_XBAR_ID_MODREV_LEN (8u)
+
+/** \brief Mask for Ifx_XBAR_ID_Bits.MODREV */
+#define IFX_XBAR_ID_MODREV_MSK (0xffu)
+
+/** \brief Offset for Ifx_XBAR_ID_Bits.MODREV */
+#define IFX_XBAR_ID_MODREV_OFF (0u)
+
+/** \brief Length for Ifx_XBAR_ID_Bits.MODTYPE */
+#define IFX_XBAR_ID_MODTYPE_LEN (8u)
+
+/** \brief Mask for Ifx_XBAR_ID_Bits.MODTYPE */
+#define IFX_XBAR_ID_MODTYPE_MSK (0xffu)
+
+/** \brief Offset for Ifx_XBAR_ID_Bits.MODTYPE */
+#define IFX_XBAR_ID_MODTYPE_OFF (8u)
+
+/** \brief Length for Ifx_XBAR_IDINTEN_Bits.ENMCI0 */
+#define IFX_XBAR_IDINTEN_ENMCI0_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_IDINTEN_Bits.ENMCI0 */
+#define IFX_XBAR_IDINTEN_ENMCI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_IDINTEN_Bits.ENMCI0 */
+#define IFX_XBAR_IDINTEN_ENMCI0_OFF (16u)
+
+/** \brief Length for Ifx_XBAR_IDINTEN_Bits.ENMCI12 */
+#define IFX_XBAR_IDINTEN_ENMCI12_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_IDINTEN_Bits.ENMCI12 */
+#define IFX_XBAR_IDINTEN_ENMCI12_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_IDINTEN_Bits.ENMCI12 */
+#define IFX_XBAR_IDINTEN_ENMCI12_OFF (28u)
+
+/** \brief Length for Ifx_XBAR_IDINTEN_Bits.ENMCI13 */
+#define IFX_XBAR_IDINTEN_ENMCI13_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_IDINTEN_Bits.ENMCI13 */
+#define IFX_XBAR_IDINTEN_ENMCI13_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_IDINTEN_Bits.ENMCI13 */
+#define IFX_XBAR_IDINTEN_ENMCI13_OFF (29u)
+
+/** \brief Length for Ifx_XBAR_IDINTEN_Bits.ENMCI4 */
+#define IFX_XBAR_IDINTEN_ENMCI4_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_IDINTEN_Bits.ENMCI4 */
+#define IFX_XBAR_IDINTEN_ENMCI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_IDINTEN_Bits.ENMCI4 */
+#define IFX_XBAR_IDINTEN_ENMCI4_OFF (20u)
+
+/** \brief Length for Ifx_XBAR_IDINTEN_Bits.ENMCI5 */
+#define IFX_XBAR_IDINTEN_ENMCI5_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_IDINTEN_Bits.ENMCI5 */
+#define IFX_XBAR_IDINTEN_ENMCI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_IDINTEN_Bits.ENMCI5 */
+#define IFX_XBAR_IDINTEN_ENMCI5_OFF (21u)
+
+/** \brief Length for Ifx_XBAR_IDINTEN_Bits.ENMCI8 */
+#define IFX_XBAR_IDINTEN_ENMCI8_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_IDINTEN_Bits.ENMCI8 */
+#define IFX_XBAR_IDINTEN_ENMCI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_IDINTEN_Bits.ENMCI8 */
+#define IFX_XBAR_IDINTEN_ENMCI8_OFF (24u)
+
+/** \brief Length for Ifx_XBAR_IDINTEN_Bits.ENMCI9 */
+#define IFX_XBAR_IDINTEN_ENMCI9_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_IDINTEN_Bits.ENMCI9 */
+#define IFX_XBAR_IDINTEN_ENMCI9_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_IDINTEN_Bits.ENMCI9 */
+#define IFX_XBAR_IDINTEN_ENMCI9_OFF (25u)
+
+/** \brief Length for Ifx_XBAR_IDINTEN_Bits.ENSCI0 */
+#define IFX_XBAR_IDINTEN_ENSCI0_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_IDINTEN_Bits.ENSCI0 */
+#define IFX_XBAR_IDINTEN_ENSCI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_IDINTEN_Bits.ENSCI0 */
+#define IFX_XBAR_IDINTEN_ENSCI0_OFF (0u)
+
+/** \brief Length for Ifx_XBAR_IDINTEN_Bits.ENSCI1 */
+#define IFX_XBAR_IDINTEN_ENSCI1_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_IDINTEN_Bits.ENSCI1 */
+#define IFX_XBAR_IDINTEN_ENSCI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_IDINTEN_Bits.ENSCI1 */
+#define IFX_XBAR_IDINTEN_ENSCI1_OFF (1u)
+
+/** \brief Length for Ifx_XBAR_IDINTEN_Bits.ENSCI4 */
+#define IFX_XBAR_IDINTEN_ENSCI4_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_IDINTEN_Bits.ENSCI4 */
+#define IFX_XBAR_IDINTEN_ENSCI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_IDINTEN_Bits.ENSCI4 */
+#define IFX_XBAR_IDINTEN_ENSCI4_OFF (4u)
+
+/** \brief Length for Ifx_XBAR_IDINTEN_Bits.ENSCI6 */
+#define IFX_XBAR_IDINTEN_ENSCI6_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_IDINTEN_Bits.ENSCI6 */
+#define IFX_XBAR_IDINTEN_ENSCI6_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_IDINTEN_Bits.ENSCI6 */
+#define IFX_XBAR_IDINTEN_ENSCI6_OFF (6u)
+
+/** \brief Length for Ifx_XBAR_IDINTEN_Bits.ENSCI7 */
+#define IFX_XBAR_IDINTEN_ENSCI7_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_IDINTEN_Bits.ENSCI7 */
+#define IFX_XBAR_IDINTEN_ENSCI7_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_IDINTEN_Bits.ENSCI7 */
+#define IFX_XBAR_IDINTEN_ENSCI7_OFF (7u)
+
+/** \brief Length for Ifx_XBAR_IDINTEN_Bits.ENSCI8 */
+#define IFX_XBAR_IDINTEN_ENSCI8_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_IDINTEN_Bits.ENSCI8 */
+#define IFX_XBAR_IDINTEN_ENSCI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_IDINTEN_Bits.ENSCI8 */
+#define IFX_XBAR_IDINTEN_ENSCI8_OFF (8u)
+
+/** \brief Length for Ifx_XBAR_IDINTEN_Bits.ENSCID */
+#define IFX_XBAR_IDINTEN_ENSCID_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_IDINTEN_Bits.ENSCID */
+#define IFX_XBAR_IDINTEN_ENSCID_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_IDINTEN_Bits.ENSCID */
+#define IFX_XBAR_IDINTEN_ENSCID_OFF (15u)
+
+/** \brief Length for Ifx_XBAR_IDINTSAT_Bits.IDCSCI4 */
+#define IFX_XBAR_IDINTSAT_IDCSCI4_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_IDINTSAT_Bits.IDCSCI4 */
+#define IFX_XBAR_IDINTSAT_IDCSCI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_IDINTSAT_Bits.IDCSCI4 */
+#define IFX_XBAR_IDINTSAT_IDCSCI4_OFF (4u)
+
+/** \brief Length for Ifx_XBAR_IDINTSAT_Bits.IDMCI0 */
+#define IFX_XBAR_IDINTSAT_IDMCI0_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_IDINTSAT_Bits.IDMCI0 */
+#define IFX_XBAR_IDINTSAT_IDMCI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_IDINTSAT_Bits.IDMCI0 */
+#define IFX_XBAR_IDINTSAT_IDMCI0_OFF (16u)
+
+/** \brief Length for Ifx_XBAR_IDINTSAT_Bits.IDMCI12 */
+#define IFX_XBAR_IDINTSAT_IDMCI12_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_IDINTSAT_Bits.IDMCI12 */
+#define IFX_XBAR_IDINTSAT_IDMCI12_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_IDINTSAT_Bits.IDMCI12 */
+#define IFX_XBAR_IDINTSAT_IDMCI12_OFF (28u)
+
+/** \brief Length for Ifx_XBAR_IDINTSAT_Bits.IDMCI13 */
+#define IFX_XBAR_IDINTSAT_IDMCI13_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_IDINTSAT_Bits.IDMCI13 */
+#define IFX_XBAR_IDINTSAT_IDMCI13_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_IDINTSAT_Bits.IDMCI13 */
+#define IFX_XBAR_IDINTSAT_IDMCI13_OFF (29u)
+
+/** \brief Length for Ifx_XBAR_IDINTSAT_Bits.IDMCI4 */
+#define IFX_XBAR_IDINTSAT_IDMCI4_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_IDINTSAT_Bits.IDMCI4 */
+#define IFX_XBAR_IDINTSAT_IDMCI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_IDINTSAT_Bits.IDMCI4 */
+#define IFX_XBAR_IDINTSAT_IDMCI4_OFF (20u)
+
+/** \brief Length for Ifx_XBAR_IDINTSAT_Bits.IDMCI5 */
+#define IFX_XBAR_IDINTSAT_IDMCI5_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_IDINTSAT_Bits.IDMCI5 */
+#define IFX_XBAR_IDINTSAT_IDMCI5_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_IDINTSAT_Bits.IDMCI5 */
+#define IFX_XBAR_IDINTSAT_IDMCI5_OFF (21u)
+
+/** \brief Length for Ifx_XBAR_IDINTSAT_Bits.IDMCI8 */
+#define IFX_XBAR_IDINTSAT_IDMCI8_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_IDINTSAT_Bits.IDMCI8 */
+#define IFX_XBAR_IDINTSAT_IDMCI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_IDINTSAT_Bits.IDMCI8 */
+#define IFX_XBAR_IDINTSAT_IDMCI8_OFF (24u)
+
+/** \brief Length for Ifx_XBAR_IDINTSAT_Bits.IDMCI9 */
+#define IFX_XBAR_IDINTSAT_IDMCI9_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_IDINTSAT_Bits.IDMCI9 */
+#define IFX_XBAR_IDINTSAT_IDMCI9_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_IDINTSAT_Bits.IDMCI9 */
+#define IFX_XBAR_IDINTSAT_IDMCI9_OFF (25u)
+
+/** \brief Length for Ifx_XBAR_IDINTSAT_Bits.IDSCI0 */
+#define IFX_XBAR_IDINTSAT_IDSCI0_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_IDINTSAT_Bits.IDSCI0 */
+#define IFX_XBAR_IDINTSAT_IDSCI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_IDINTSAT_Bits.IDSCI0 */
+#define IFX_XBAR_IDINTSAT_IDSCI0_OFF (0u)
+
+/** \brief Length for Ifx_XBAR_IDINTSAT_Bits.IDSCI1 */
+#define IFX_XBAR_IDINTSAT_IDSCI1_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_IDINTSAT_Bits.IDSCI1 */
+#define IFX_XBAR_IDINTSAT_IDSCI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_IDINTSAT_Bits.IDSCI1 */
+#define IFX_XBAR_IDINTSAT_IDSCI1_OFF (1u)
+
+/** \brief Length for Ifx_XBAR_IDINTSAT_Bits.IDSCI6 */
+#define IFX_XBAR_IDINTSAT_IDSCI6_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_IDINTSAT_Bits.IDSCI6 */
+#define IFX_XBAR_IDINTSAT_IDSCI6_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_IDINTSAT_Bits.IDSCI6 */
+#define IFX_XBAR_IDINTSAT_IDSCI6_OFF (6u)
+
+/** \brief Length for Ifx_XBAR_IDINTSAT_Bits.IDSCI7 */
+#define IFX_XBAR_IDINTSAT_IDSCI7_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_IDINTSAT_Bits.IDSCI7 */
+#define IFX_XBAR_IDINTSAT_IDSCI7_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_IDINTSAT_Bits.IDSCI7 */
+#define IFX_XBAR_IDINTSAT_IDSCI7_OFF (7u)
+
+/** \brief Length for Ifx_XBAR_IDINTSAT_Bits.IDSCI8 */
+#define IFX_XBAR_IDINTSAT_IDSCI8_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_IDINTSAT_Bits.IDSCI8 */
+#define IFX_XBAR_IDINTSAT_IDSCI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_IDINTSAT_Bits.IDSCI8 */
+#define IFX_XBAR_IDINTSAT_IDSCI8_OFF (8u)
+
+/** \brief Length for Ifx_XBAR_IDINTSAT_Bits.IDSCID */
+#define IFX_XBAR_IDINTSAT_IDSCID_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_IDINTSAT_Bits.IDSCID */
+#define IFX_XBAR_IDINTSAT_IDSCID_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_IDINTSAT_Bits.IDSCID */
+#define IFX_XBAR_IDINTSAT_IDSCID_OFF (15u)
+
+/** \brief Length for Ifx_XBAR_INTSAT_Bits.PRSCI0 */
+#define IFX_XBAR_INTSAT_PRSCI0_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_INTSAT_Bits.PRSCI0 */
+#define IFX_XBAR_INTSAT_PRSCI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_INTSAT_Bits.PRSCI0 */
+#define IFX_XBAR_INTSAT_PRSCI0_OFF (16u)
+
+/** \brief Length for Ifx_XBAR_INTSAT_Bits.PRSCI1 */
+#define IFX_XBAR_INTSAT_PRSCI1_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_INTSAT_Bits.PRSCI1 */
+#define IFX_XBAR_INTSAT_PRSCI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_INTSAT_Bits.PRSCI1 */
+#define IFX_XBAR_INTSAT_PRSCI1_OFF (17u)
+
+/** \brief Length for Ifx_XBAR_INTSAT_Bits.PRSCI4 */
+#define IFX_XBAR_INTSAT_PRSCI4_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_INTSAT_Bits.PRSCI4 */
+#define IFX_XBAR_INTSAT_PRSCI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_INTSAT_Bits.PRSCI4 */
+#define IFX_XBAR_INTSAT_PRSCI4_OFF (20u)
+
+/** \brief Length for Ifx_XBAR_INTSAT_Bits.PRSCI6 */
+#define IFX_XBAR_INTSAT_PRSCI6_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_INTSAT_Bits.PRSCI6 */
+#define IFX_XBAR_INTSAT_PRSCI6_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_INTSAT_Bits.PRSCI6 */
+#define IFX_XBAR_INTSAT_PRSCI6_OFF (22u)
+
+/** \brief Length for Ifx_XBAR_INTSAT_Bits.PRSCI7 */
+#define IFX_XBAR_INTSAT_PRSCI7_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_INTSAT_Bits.PRSCI7 */
+#define IFX_XBAR_INTSAT_PRSCI7_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_INTSAT_Bits.PRSCI7 */
+#define IFX_XBAR_INTSAT_PRSCI7_OFF (23u)
+
+/** \brief Length for Ifx_XBAR_INTSAT_Bits.PRSCI8 */
+#define IFX_XBAR_INTSAT_PRSCI8_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_INTSAT_Bits.PRSCI8 */
+#define IFX_XBAR_INTSAT_PRSCI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_INTSAT_Bits.PRSCI8 */
+#define IFX_XBAR_INTSAT_PRSCI8_OFF (24u)
+
+/** \brief Length for Ifx_XBAR_INTSAT_Bits.PRSCID */
+#define IFX_XBAR_INTSAT_PRSCID_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_INTSAT_Bits.PRSCID */
+#define IFX_XBAR_INTSAT_PRSCID_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_INTSAT_Bits.PRSCID */
+#define IFX_XBAR_INTSAT_PRSCID_OFF (31u)
+
+/** \brief Length for Ifx_XBAR_INTSAT_Bits.SCSCI0 */
+#define IFX_XBAR_INTSAT_SCSCI0_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_INTSAT_Bits.SCSCI0 */
+#define IFX_XBAR_INTSAT_SCSCI0_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_INTSAT_Bits.SCSCI0 */
+#define IFX_XBAR_INTSAT_SCSCI0_OFF (0u)
+
+/** \brief Length for Ifx_XBAR_INTSAT_Bits.SCSCI1 */
+#define IFX_XBAR_INTSAT_SCSCI1_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_INTSAT_Bits.SCSCI1 */
+#define IFX_XBAR_INTSAT_SCSCI1_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_INTSAT_Bits.SCSCI1 */
+#define IFX_XBAR_INTSAT_SCSCI1_OFF (1u)
+
+/** \brief Length for Ifx_XBAR_INTSAT_Bits.SCSCI4 */
+#define IFX_XBAR_INTSAT_SCSCI4_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_INTSAT_Bits.SCSCI4 */
+#define IFX_XBAR_INTSAT_SCSCI4_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_INTSAT_Bits.SCSCI4 */
+#define IFX_XBAR_INTSAT_SCSCI4_OFF (4u)
+
+/** \brief Length for Ifx_XBAR_INTSAT_Bits.SCSCI6 */
+#define IFX_XBAR_INTSAT_SCSCI6_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_INTSAT_Bits.SCSCI6 */
+#define IFX_XBAR_INTSAT_SCSCI6_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_INTSAT_Bits.SCSCI6 */
+#define IFX_XBAR_INTSAT_SCSCI6_OFF (6u)
+
+/** \brief Length for Ifx_XBAR_INTSAT_Bits.SCSCI7 */
+#define IFX_XBAR_INTSAT_SCSCI7_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_INTSAT_Bits.SCSCI7 */
+#define IFX_XBAR_INTSAT_SCSCI7_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_INTSAT_Bits.SCSCI7 */
+#define IFX_XBAR_INTSAT_SCSCI7_OFF (7u)
+
+/** \brief Length for Ifx_XBAR_INTSAT_Bits.SCSCI8 */
+#define IFX_XBAR_INTSAT_SCSCI8_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_INTSAT_Bits.SCSCI8 */
+#define IFX_XBAR_INTSAT_SCSCI8_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_INTSAT_Bits.SCSCI8 */
+#define IFX_XBAR_INTSAT_SCSCI8_OFF (8u)
+
+/** \brief Length for Ifx_XBAR_INTSAT_Bits.SCSCID */
+#define IFX_XBAR_INTSAT_SCSCID_LEN (1u)
+
+/** \brief Mask for Ifx_XBAR_INTSAT_Bits.SCSCID */
+#define IFX_XBAR_INTSAT_SCSCID_MSK (0x1u)
+
+/** \brief Offset for Ifx_XBAR_INTSAT_Bits.SCSCID */
+#define IFX_XBAR_INTSAT_SCSCID_OFF (15u)
+
+/** \brief Length for Ifx_XBAR_PRIOH_Bits.MASTER12 */
+#define IFX_XBAR_PRIOH_MASTER12_LEN (3u)
+
+/** \brief Mask for Ifx_XBAR_PRIOH_Bits.MASTER12 */
+#define IFX_XBAR_PRIOH_MASTER12_MSK (0x7u)
+
+/** \brief Offset for Ifx_XBAR_PRIOH_Bits.MASTER12 */
+#define IFX_XBAR_PRIOH_MASTER12_OFF (16u)
+
+/** \brief Length for Ifx_XBAR_PRIOH_Bits.MASTER13 */
+#define IFX_XBAR_PRIOH_MASTER13_LEN (3u)
+
+/** \brief Mask for Ifx_XBAR_PRIOH_Bits.MASTER13 */
+#define IFX_XBAR_PRIOH_MASTER13_MSK (0x7u)
+
+/** \brief Offset for Ifx_XBAR_PRIOH_Bits.MASTER13 */
+#define IFX_XBAR_PRIOH_MASTER13_OFF (20u)
+
+/** \brief Length for Ifx_XBAR_PRIOH_Bits.MASTER8 */
+#define IFX_XBAR_PRIOH_MASTER8_LEN (3u)
+
+/** \brief Mask for Ifx_XBAR_PRIOH_Bits.MASTER8 */
+#define IFX_XBAR_PRIOH_MASTER8_MSK (0x7u)
+
+/** \brief Offset for Ifx_XBAR_PRIOH_Bits.MASTER8 */
+#define IFX_XBAR_PRIOH_MASTER8_OFF (0u)
+
+/** \brief Length for Ifx_XBAR_PRIOH_Bits.MASTER9 */
+#define IFX_XBAR_PRIOH_MASTER9_LEN (3u)
+
+/** \brief Mask for Ifx_XBAR_PRIOH_Bits.MASTER9 */
+#define IFX_XBAR_PRIOH_MASTER9_MSK (0x7u)
+
+/** \brief Offset for Ifx_XBAR_PRIOH_Bits.MASTER9 */
+#define IFX_XBAR_PRIOH_MASTER9_OFF (4u)
+
+/** \brief Length for Ifx_XBAR_PRIOL_Bits.MASTER0 */
+#define IFX_XBAR_PRIOL_MASTER0_LEN (3u)
+
+/** \brief Mask for Ifx_XBAR_PRIOL_Bits.MASTER0 */
+#define IFX_XBAR_PRIOL_MASTER0_MSK (0x7u)
+
+/** \brief Offset for Ifx_XBAR_PRIOL_Bits.MASTER0 */
+#define IFX_XBAR_PRIOL_MASTER0_OFF (0u)
+
+/** \brief Length for Ifx_XBAR_PRIOL_Bits.MASTER4 */
+#define IFX_XBAR_PRIOL_MASTER4_LEN (3u)
+
+/** \brief Mask for Ifx_XBAR_PRIOL_Bits.MASTER4 */
+#define IFX_XBAR_PRIOL_MASTER4_MSK (0x7u)
+
+/** \brief Offset for Ifx_XBAR_PRIOL_Bits.MASTER4 */
+#define IFX_XBAR_PRIOL_MASTER4_OFF (16u)
+
+/** \brief Length for Ifx_XBAR_PRIOL_Bits.MASTER5 */
+#define IFX_XBAR_PRIOL_MASTER5_LEN (3u)
+
+/** \brief Mask for Ifx_XBAR_PRIOL_Bits.MASTER5 */
+#define IFX_XBAR_PRIOL_MASTER5_MSK (0x7u)
+
+/** \brief Offset for Ifx_XBAR_PRIOL_Bits.MASTER5 */
+#define IFX_XBAR_PRIOL_MASTER5_OFF (20u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXXBAR_BF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxXbar_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxXbar_reg.h
new file mode 100644
index 0000000..67db1f5
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxXbar_reg.h
@@ -0,0 +1,523 @@
+/**
+ * \file IfxXbar_reg.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Xbar_Cfg Xbar address
+ * \ingroup IfxLld_Xbar
+ *
+ * \defgroup IfxLld_Xbar_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Xbar_Cfg
+ *
+ * \defgroup IfxLld_Xbar_Cfg_Xbar 2-XBAR
+ * \ingroup IfxLld_Xbar_Cfg
+ *
+ */
+#ifndef IFXXBAR_REG_H
+#define IFXXBAR_REG_H 1
+/******************************************************************************/
+#include "IfxXbar_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Xbar_Cfg_BaseAddress
+ * \{ */
+
+/** \brief XBAR object */
+#define MODULE_XBAR /*lint --e(923)*/ (*(Ifx_XBAR*)0xF8700000u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Xbar_Cfg_Xbar
+ * \{ */
+
+/** \brief 4FC, Access Enable Register 0 */
+#define XBAR_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_XBAR_ACCEN0*)0xF87004FCu)
+
+/** \brief 4F8, Access Enable Register 1 */
+#define XBAR_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_XBAR_ACCEN1*)0xF87004F8u)
+
+/** \brief 44, Arbiter Control Register */
+#define XBAR_ARBITER0_ARBCON /*lint --e(923)*/ (*(volatile Ifx_XBAR_ARBCON*)0xF8700044u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER0_ARBCON.
+* To use register names with standard convension, please use XBAR_ARBITER0_ARBCON.
+*/
+#define XBAR_ARBCON0 (XBAR_ARBITER0_ARBCON)
+
+/** \brief 5C, Debug Address Register */
+#define XBAR_ARBITER0_DBADD /*lint --e(923)*/ (*(volatile Ifx_XBAR_ARBITER0_DBADD*)0xF870005Cu)
+
+/** Alias (User Manual Name) for XBAR_ARBITER0_DBADD.
+* To use register names with standard convension, please use XBAR_ARBITER0_DBADD.
+*/
+#define XBAR_DBADD0 (XBAR_ARBITER0_DBADD)
+
+/** \brief 58, Debug Control Register */
+#define XBAR_ARBITER0_DBCON /*lint --e(923)*/ (*(volatile Ifx_XBAR_DBCON*)0xF8700058u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER0_DBCON.
+* To use register names with standard convension, please use XBAR_ARBITER0_DBCON.
+*/
+#define XBAR_DBCON0 (XBAR_ARBITER0_DBCON)
+
+/** \brief 60, Debug Mask Address Register */
+#define XBAR_ARBITER0_DBMADD /*lint --e(923)*/ (*(volatile Ifx_XBAR_ARBITER0_DBMADD*)0xF8700060u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER0_DBMADD.
+* To use register names with standard convension, please use XBAR_ARBITER0_DBMADD.
+*/
+#define XBAR_DBMADD0 (XBAR_ARBITER0_DBMADD)
+
+/** \brief 54, Error/Debug Capture Register */
+#define XBAR_ARBITER0_ERR /*lint --e(923)*/ (*(volatile Ifx_XBAR_ERR*)0xF8700054u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER0_ERR.
+* To use register names with standard convension, please use XBAR_ARBITER0_ERR.
+*/
+#define XBAR_ERR0 (XBAR_ARBITER0_ERR)
+
+/** \brief 50, Error/Debug Address Capture Register */
+#define XBAR_ARBITER0_ERRADDR /*lint --e(923)*/ (*(volatile Ifx_XBAR_ERRADDR*)0xF8700050u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER0_ERRADDR.
+* To use register names with standard convension, please use XBAR_ARBITER0_ERRADDR.
+*/
+#define XBAR_ERRADDR0 (XBAR_ARBITER0_ERRADDR)
+
+/** \brief 48, Arbiter Priority Register */
+#define XBAR_ARBITER0_PRIOH /*lint --e(923)*/ (*(volatile Ifx_XBAR_PRIOH*)0xF8700048u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER0_PRIOH.
+* To use register names with standard convension, please use XBAR_ARBITER0_PRIOH.
+*/
+#define XBAR_PRIOH0 (XBAR_ARBITER0_PRIOH)
+
+/** \brief 4C, Arbiter Priority Register */
+#define XBAR_ARBITER0_PRIOL /*lint --e(923)*/ (*(volatile Ifx_XBAR_PRIOL*)0xF870004Cu)
+
+/** Alias (User Manual Name) for XBAR_ARBITER0_PRIOL.
+* To use register names with standard convension, please use XBAR_ARBITER0_PRIOL.
+*/
+#define XBAR_PRIOL0 (XBAR_ARBITER0_PRIOL)
+
+/** \brief 84, Arbiter Control Register */
+#define XBAR_ARBITER1_ARBCON /*lint --e(923)*/ (*(volatile Ifx_XBAR_ARBCON*)0xF8700084u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER1_ARBCON.
+* To use register names with standard convension, please use XBAR_ARBITER1_ARBCON.
+*/
+#define XBAR_ARBCON1 (XBAR_ARBITER1_ARBCON)
+
+/** \brief 9C, Debug Address Register */
+#define XBAR_ARBITER1_DBADD /*lint --e(923)*/ (*(volatile Ifx_XBAR_ARBITER1_DBADD*)0xF870009Cu)
+
+/** Alias (User Manual Name) for XBAR_ARBITER1_DBADD.
+* To use register names with standard convension, please use XBAR_ARBITER1_DBADD.
+*/
+#define XBAR_DBADD1 (XBAR_ARBITER1_DBADD)
+
+/** \brief 98, Debug Control Register */
+#define XBAR_ARBITER1_DBCON /*lint --e(923)*/ (*(volatile Ifx_XBAR_DBCON*)0xF8700098u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER1_DBCON.
+* To use register names with standard convension, please use XBAR_ARBITER1_DBCON.
+*/
+#define XBAR_DBCON1 (XBAR_ARBITER1_DBCON)
+
+/** \brief A0, Debug Mask Address Register */
+#define XBAR_ARBITER1_DBMADD /*lint --e(923)*/ (*(volatile Ifx_XBAR_ARBITER1_DBMADD*)0xF87000A0u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER1_DBMADD.
+* To use register names with standard convension, please use XBAR_ARBITER1_DBMADD.
+*/
+#define XBAR_DBMADD1 (XBAR_ARBITER1_DBMADD)
+
+/** \brief 94, Error/Debug Capture Register */
+#define XBAR_ARBITER1_ERR /*lint --e(923)*/ (*(volatile Ifx_XBAR_ERR*)0xF8700094u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER1_ERR.
+* To use register names with standard convension, please use XBAR_ARBITER1_ERR.
+*/
+#define XBAR_ERR1 (XBAR_ARBITER1_ERR)
+
+/** \brief 90, Error/Debug Address Capture Register */
+#define XBAR_ARBITER1_ERRADDR /*lint --e(923)*/ (*(volatile Ifx_XBAR_ERRADDR*)0xF8700090u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER1_ERRADDR.
+* To use register names with standard convension, please use XBAR_ARBITER1_ERRADDR.
+*/
+#define XBAR_ERRADDR1 (XBAR_ARBITER1_ERRADDR)
+
+/** \brief 88, Arbiter Priority Register */
+#define XBAR_ARBITER1_PRIOH /*lint --e(923)*/ (*(volatile Ifx_XBAR_PRIOH*)0xF8700088u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER1_PRIOH.
+* To use register names with standard convension, please use XBAR_ARBITER1_PRIOH.
+*/
+#define XBAR_PRIOH1 (XBAR_ARBITER1_PRIOH)
+
+/** \brief 8C, Arbiter Priority Register */
+#define XBAR_ARBITER1_PRIOL /*lint --e(923)*/ (*(volatile Ifx_XBAR_PRIOL*)0xF870008Cu)
+
+/** Alias (User Manual Name) for XBAR_ARBITER1_PRIOL.
+* To use register names with standard convension, please use XBAR_ARBITER1_PRIOL.
+*/
+#define XBAR_PRIOL1 (XBAR_ARBITER1_PRIOL)
+
+/** \brief 144, Arbiter Control Register */
+#define XBAR_ARBITER4_ARBCON /*lint --e(923)*/ (*(volatile Ifx_XBAR_ARBCON*)0xF8700144u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER4_ARBCON.
+* To use register names with standard convension, please use XBAR_ARBITER4_ARBCON.
+*/
+#define XBAR_ARBCON4 (XBAR_ARBITER4_ARBCON)
+
+/** \brief 15C, Debug Address Register */
+#define XBAR_ARBITER4_DBADD /*lint --e(923)*/ (*(volatile Ifx_XBAR_ARBITER4_DBADD*)0xF870015Cu)
+
+/** Alias (User Manual Name) for XBAR_ARBITER4_DBADD.
+* To use register names with standard convension, please use XBAR_ARBITER4_DBADD.
+*/
+#define XBAR_DBADD4 (XBAR_ARBITER4_DBADD)
+
+/** \brief 158, Debug Control Register */
+#define XBAR_ARBITER4_DBCON /*lint --e(923)*/ (*(volatile Ifx_XBAR_DBCON*)0xF8700158u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER4_DBCON.
+* To use register names with standard convension, please use XBAR_ARBITER4_DBCON.
+*/
+#define XBAR_DBCON4 (XBAR_ARBITER4_DBCON)
+
+/** \brief 160, Debug Mask Address Register */
+#define XBAR_ARBITER4_DBMADD /*lint --e(923)*/ (*(volatile Ifx_XBAR_ARBITER4_DBMADD*)0xF8700160u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER4_DBMADD.
+* To use register names with standard convension, please use XBAR_ARBITER4_DBMADD.
+*/
+#define XBAR_DBMADD4 (XBAR_ARBITER4_DBMADD)
+
+/** \brief 154, Error/Debug Capture Register */
+#define XBAR_ARBITER4_ERR /*lint --e(923)*/ (*(volatile Ifx_XBAR_ERR*)0xF8700154u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER4_ERR.
+* To use register names with standard convension, please use XBAR_ARBITER4_ERR.
+*/
+#define XBAR_ERR4 (XBAR_ARBITER4_ERR)
+
+/** \brief 150, Error/Debug Address Capture Register */
+#define XBAR_ARBITER4_ERRADDR /*lint --e(923)*/ (*(volatile Ifx_XBAR_ERRADDR*)0xF8700150u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER4_ERRADDR.
+* To use register names with standard convension, please use XBAR_ARBITER4_ERRADDR.
+*/
+#define XBAR_ERRADDR4 (XBAR_ARBITER4_ERRADDR)
+
+/** \brief 148, Arbiter Priority Register */
+#define XBAR_ARBITER4_PRIOH /*lint --e(923)*/ (*(volatile Ifx_XBAR_PRIOH*)0xF8700148u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER4_PRIOH.
+* To use register names with standard convension, please use XBAR_ARBITER4_PRIOH.
+*/
+#define XBAR_PRIOH4 (XBAR_ARBITER4_PRIOH)
+
+/** \brief 14C, Arbiter Priority Register */
+#define XBAR_ARBITER4_PRIOL /*lint --e(923)*/ (*(volatile Ifx_XBAR_PRIOL*)0xF870014Cu)
+
+/** Alias (User Manual Name) for XBAR_ARBITER4_PRIOL.
+* To use register names with standard convension, please use XBAR_ARBITER4_PRIOL.
+*/
+#define XBAR_PRIOL4 (XBAR_ARBITER4_PRIOL)
+
+/** \brief 1C4, Arbiter Control Register */
+#define XBAR_ARBITER6_ARBCON /*lint --e(923)*/ (*(volatile Ifx_XBAR_ARBCON*)0xF87001C4u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER6_ARBCON.
+* To use register names with standard convension, please use XBAR_ARBITER6_ARBCON.
+*/
+#define XBAR_ARBCON6 (XBAR_ARBITER6_ARBCON)
+
+/** \brief 1DC, Debug Address Register */
+#define XBAR_ARBITER6_DBADD /*lint --e(923)*/ (*(volatile Ifx_XBAR_ARBITER6_DBADD*)0xF87001DCu)
+
+/** Alias (User Manual Name) for XBAR_ARBITER6_DBADD.
+* To use register names with standard convension, please use XBAR_ARBITER6_DBADD.
+*/
+#define XBAR_DBADD6 (XBAR_ARBITER6_DBADD)
+
+/** \brief 1D8, Debug Control Register */
+#define XBAR_ARBITER6_DBCON /*lint --e(923)*/ (*(volatile Ifx_XBAR_DBCON*)0xF87001D8u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER6_DBCON.
+* To use register names with standard convension, please use XBAR_ARBITER6_DBCON.
+*/
+#define XBAR_DBCON6 (XBAR_ARBITER6_DBCON)
+
+/** \brief 1E0, Debug Mask Address Register */
+#define XBAR_ARBITER6_DBMADD /*lint --e(923)*/ (*(volatile Ifx_XBAR_ARBITER6_DBMADD*)0xF87001E0u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER6_DBMADD.
+* To use register names with standard convension, please use XBAR_ARBITER6_DBMADD.
+*/
+#define XBAR_DBMADD6 (XBAR_ARBITER6_DBMADD)
+
+/** \brief 1D4, Error/Debug Capture Register */
+#define XBAR_ARBITER6_ERR /*lint --e(923)*/ (*(volatile Ifx_XBAR_ERR*)0xF87001D4u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER6_ERR.
+* To use register names with standard convension, please use XBAR_ARBITER6_ERR.
+*/
+#define XBAR_ERR6 (XBAR_ARBITER6_ERR)
+
+/** \brief 1D0, Error/Debug Address Capture Register */
+#define XBAR_ARBITER6_ERRADDR /*lint --e(923)*/ (*(volatile Ifx_XBAR_ERRADDR*)0xF87001D0u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER6_ERRADDR.
+* To use register names with standard convension, please use XBAR_ARBITER6_ERRADDR.
+*/
+#define XBAR_ERRADDR6 (XBAR_ARBITER6_ERRADDR)
+
+/** \brief 1C8, Arbiter Priority Register */
+#define XBAR_ARBITER6_PRIOH /*lint --e(923)*/ (*(volatile Ifx_XBAR_PRIOH*)0xF87001C8u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER6_PRIOH.
+* To use register names with standard convension, please use XBAR_ARBITER6_PRIOH.
+*/
+#define XBAR_PRIOH6 (XBAR_ARBITER6_PRIOH)
+
+/** \brief 1CC, Arbiter Priority Register */
+#define XBAR_ARBITER6_PRIOL /*lint --e(923)*/ (*(volatile Ifx_XBAR_PRIOL*)0xF87001CCu)
+
+/** Alias (User Manual Name) for XBAR_ARBITER6_PRIOL.
+* To use register names with standard convension, please use XBAR_ARBITER6_PRIOL.
+*/
+#define XBAR_PRIOL6 (XBAR_ARBITER6_PRIOL)
+
+/** \brief 204, Arbiter Control Register */
+#define XBAR_ARBITER7_ARBCON /*lint --e(923)*/ (*(volatile Ifx_XBAR_ARBCON*)0xF8700204u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER7_ARBCON.
+* To use register names with standard convension, please use XBAR_ARBITER7_ARBCON.
+*/
+#define XBAR_ARBCON7 (XBAR_ARBITER7_ARBCON)
+
+/** \brief 21C, Debug Address Register */
+#define XBAR_ARBITER7_DBADD /*lint --e(923)*/ (*(volatile Ifx_XBAR_ARBITER7_DBADD*)0xF870021Cu)
+
+/** Alias (User Manual Name) for XBAR_ARBITER7_DBADD.
+* To use register names with standard convension, please use XBAR_ARBITER7_DBADD.
+*/
+#define XBAR_DBADD7 (XBAR_ARBITER7_DBADD)
+
+/** \brief 218, Debug Control Register */
+#define XBAR_ARBITER7_DBCON /*lint --e(923)*/ (*(volatile Ifx_XBAR_DBCON*)0xF8700218u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER7_DBCON.
+* To use register names with standard convension, please use XBAR_ARBITER7_DBCON.
+*/
+#define XBAR_DBCON7 (XBAR_ARBITER7_DBCON)
+
+/** \brief 220, Debug Mask Address Register */
+#define XBAR_ARBITER7_DBMADD /*lint --e(923)*/ (*(volatile Ifx_XBAR_ARBITER7_DBMADD*)0xF8700220u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER7_DBMADD.
+* To use register names with standard convension, please use XBAR_ARBITER7_DBMADD.
+*/
+#define XBAR_DBMADD7 (XBAR_ARBITER7_DBMADD)
+
+/** \brief 214, Error/Debug Capture Register */
+#define XBAR_ARBITER7_ERR /*lint --e(923)*/ (*(volatile Ifx_XBAR_ERR*)0xF8700214u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER7_ERR.
+* To use register names with standard convension, please use XBAR_ARBITER7_ERR.
+*/
+#define XBAR_ERR7 (XBAR_ARBITER7_ERR)
+
+/** \brief 210, Error/Debug Address Capture Register */
+#define XBAR_ARBITER7_ERRADDR /*lint --e(923)*/ (*(volatile Ifx_XBAR_ERRADDR*)0xF8700210u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER7_ERRADDR.
+* To use register names with standard convension, please use XBAR_ARBITER7_ERRADDR.
+*/
+#define XBAR_ERRADDR7 (XBAR_ARBITER7_ERRADDR)
+
+/** \brief 208, Arbiter Priority Register */
+#define XBAR_ARBITER7_PRIOH /*lint --e(923)*/ (*(volatile Ifx_XBAR_PRIOH*)0xF8700208u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER7_PRIOH.
+* To use register names with standard convension, please use XBAR_ARBITER7_PRIOH.
+*/
+#define XBAR_PRIOH7 (XBAR_ARBITER7_PRIOH)
+
+/** \brief 20C, Arbiter Priority Register */
+#define XBAR_ARBITER7_PRIOL /*lint --e(923)*/ (*(volatile Ifx_XBAR_PRIOL*)0xF870020Cu)
+
+/** Alias (User Manual Name) for XBAR_ARBITER7_PRIOL.
+* To use register names with standard convension, please use XBAR_ARBITER7_PRIOL.
+*/
+#define XBAR_PRIOL7 (XBAR_ARBITER7_PRIOL)
+
+/** \brief 244, Arbiter Control Register */
+#define XBAR_ARBITER8_ARBCON /*lint --e(923)*/ (*(volatile Ifx_XBAR_ARBCON*)0xF8700244u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER8_ARBCON.
+* To use register names with standard convension, please use XBAR_ARBITER8_ARBCON.
+*/
+#define XBAR_ARBCON8 (XBAR_ARBITER8_ARBCON)
+
+/** \brief 25C, Debug Address Register */
+#define XBAR_ARBITER8_DBADD /*lint --e(923)*/ (*(volatile Ifx_XBAR_ARBITER8_DBADD*)0xF870025Cu)
+
+/** Alias (User Manual Name) for XBAR_ARBITER8_DBADD.
+* To use register names with standard convension, please use XBAR_ARBITER8_DBADD.
+*/
+#define XBAR_DBADD8 (XBAR_ARBITER8_DBADD)
+
+/** \brief 258, Debug Control Register */
+#define XBAR_ARBITER8_DBCON /*lint --e(923)*/ (*(volatile Ifx_XBAR_DBCON*)0xF8700258u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER8_DBCON.
+* To use register names with standard convension, please use XBAR_ARBITER8_DBCON.
+*/
+#define XBAR_DBCON8 (XBAR_ARBITER8_DBCON)
+
+/** \brief 260, Debug Mask Address Register */
+#define XBAR_ARBITER8_DBMADD /*lint --e(923)*/ (*(volatile Ifx_XBAR_ARBITER8_DBMADD*)0xF8700260u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER8_DBMADD.
+* To use register names with standard convension, please use XBAR_ARBITER8_DBMADD.
+*/
+#define XBAR_DBMADD8 (XBAR_ARBITER8_DBMADD)
+
+/** \brief 254, Error/Debug Capture Register */
+#define XBAR_ARBITER8_ERR /*lint --e(923)*/ (*(volatile Ifx_XBAR_ERR*)0xF8700254u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER8_ERR.
+* To use register names with standard convension, please use XBAR_ARBITER8_ERR.
+*/
+#define XBAR_ERR8 (XBAR_ARBITER8_ERR)
+
+/** \brief 250, Error/Debug Address Capture Register */
+#define XBAR_ARBITER8_ERRADDR /*lint --e(923)*/ (*(volatile Ifx_XBAR_ERRADDR*)0xF8700250u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER8_ERRADDR.
+* To use register names with standard convension, please use XBAR_ARBITER8_ERRADDR.
+*/
+#define XBAR_ERRADDR8 (XBAR_ARBITER8_ERRADDR)
+
+/** \brief 248, Arbiter Priority Register */
+#define XBAR_ARBITER8_PRIOH /*lint --e(923)*/ (*(volatile Ifx_XBAR_PRIOH*)0xF8700248u)
+
+/** Alias (User Manual Name) for XBAR_ARBITER8_PRIOH.
+* To use register names with standard convension, please use XBAR_ARBITER8_PRIOH.
+*/
+#define XBAR_PRIOH8 (XBAR_ARBITER8_PRIOH)
+
+/** \brief 24C, Arbiter Priority Register */
+#define XBAR_ARBITER8_PRIOL /*lint --e(923)*/ (*(volatile Ifx_XBAR_PRIOL*)0xF870024Cu)
+
+/** Alias (User Manual Name) for XBAR_ARBITER8_PRIOL.
+* To use register names with standard convension, please use XBAR_ARBITER8_PRIOL.
+*/
+#define XBAR_PRIOL8 (XBAR_ARBITER8_PRIOL)
+
+/** \brief 4, Arbiter Control Register */
+#define XBAR_ARBITERD_ARBCON /*lint --e(923)*/ (*(volatile Ifx_XBAR_ARBCON*)0xF8700004u)
+
+/** Alias (User Manual Name) for XBAR_ARBITERD_ARBCON.
+* To use register names with standard convension, please use XBAR_ARBITERD_ARBCON.
+*/
+#define XBAR_ARBCOND (XBAR_ARBITERD_ARBCON)
+
+/** \brief 1C, Debug Address Register */
+#define XBAR_ARBITERD_DBADD /*lint --e(923)*/ (*(volatile Ifx_XBAR_ARBITERD_DBADD*)0xF870001Cu)
+
+/** Alias (User Manual Name) for XBAR_ARBITERD_DBADD.
+* To use register names with standard convension, please use XBAR_ARBITERD_DBADD.
+*/
+#define XBAR_DBADDD (XBAR_ARBITERD_DBADD)
+
+/** \brief 18, Debug Control Register */
+#define XBAR_ARBITERD_DBCON /*lint --e(923)*/ (*(volatile Ifx_XBAR_DBCON*)0xF8700018u)
+
+/** Alias (User Manual Name) for XBAR_ARBITERD_DBCON.
+* To use register names with standard convension, please use XBAR_ARBITERD_DBCON.
+*/
+#define XBAR_DBCOND (XBAR_ARBITERD_DBCON)
+
+/** \brief 20, Debug Mask Address Register */
+#define XBAR_ARBITERD_DBMADD /*lint --e(923)*/ (*(volatile Ifx_XBAR_ARBITERD_DBMADD*)0xF8700020u)
+
+/** Alias (User Manual Name) for XBAR_ARBITERD_DBMADD.
+* To use register names with standard convension, please use XBAR_ARBITERD_DBMADD.
+*/
+#define XBAR_DBMADDD (XBAR_ARBITERD_DBMADD)
+
+/** \brief 14, Error/Debug Capture Register */
+#define XBAR_ARBITERD_ERR /*lint --e(923)*/ (*(volatile Ifx_XBAR_ERR*)0xF8700014u)
+
+/** Alias (User Manual Name) for XBAR_ARBITERD_ERR.
+* To use register names with standard convension, please use XBAR_ARBITERD_ERR.
+*/
+#define XBAR_ERRD (XBAR_ARBITERD_ERR)
+
+/** \brief 10, Error/Debug Address Capture Register */
+#define XBAR_ARBITERD_ERRADDR /*lint --e(923)*/ (*(volatile Ifx_XBAR_ERRADDR*)0xF8700010u)
+
+/** Alias (User Manual Name) for XBAR_ARBITERD_ERRADDR.
+* To use register names with standard convension, please use XBAR_ARBITERD_ERRADDR.
+*/
+#define XBAR_ERRADDRD (XBAR_ARBITERD_ERRADDR)
+
+/** \brief 8, Arbiter Priority Register */
+#define XBAR_ARBITERD_PRIOH /*lint --e(923)*/ (*(volatile Ifx_XBAR_PRIOH*)0xF8700008u)
+
+/** Alias (User Manual Name) for XBAR_ARBITERD_PRIOH.
+* To use register names with standard convension, please use XBAR_ARBITERD_PRIOH.
+*/
+#define XBAR_PRIOHD (XBAR_ARBITERD_PRIOH)
+
+/** \brief C, Arbiter Priority Register */
+#define XBAR_ARBITERD_PRIOL /*lint --e(923)*/ (*(volatile Ifx_XBAR_PRIOL*)0xF870000Cu)
+
+/** Alias (User Manual Name) for XBAR_ARBITERD_PRIOL.
+* To use register names with standard convension, please use XBAR_ARBITERD_PRIOL.
+*/
+#define XBAR_PRIOLD (XBAR_ARBITERD_PRIOL)
+
+/** \brief 40C, Debug Trigger Event Status Register */
+#define XBAR_DBSAT /*lint --e(923)*/ (*(volatile Ifx_XBAR_DBSAT*)0xF870040Cu)
+
+/** \brief 0, External Control Register D */
+#define XBAR_EXTCOND /*lint --e(923)*/ (*(volatile Ifx_XBAR_EXTCOND*)0xF8700000u)
+
+/** \brief 408, Module Identification Register */
+#define XBAR_ID /*lint --e(923)*/ (*(volatile Ifx_XBAR_ID*)0xF8700408u)
+
+/** \brief 418, Transaction ID Interrupt Enable Register */
+#define XBAR_IDINTEN /*lint --e(923)*/ (*(volatile Ifx_XBAR_IDINTEN*)0xF8700418u)
+
+/** \brief 414, Transaction ID Interrupt Status Register */
+#define XBAR_IDINTSAT /*lint --e(923)*/ (*(volatile Ifx_XBAR_IDINTSAT*)0xF8700414u)
+
+/** \brief 410, Arbiter Interrupt Status Register */
+#define XBAR_INTSAT /*lint --e(923)*/ (*(volatile Ifx_XBAR_INTSAT*)0xF8700410u)
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXXBAR_REG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxXbar_regdef.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxXbar_regdef.h
new file mode 100644
index 0000000..4e05bf0
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxXbar_regdef.h
@@ -0,0 +1,754 @@
+/**
+ * \file IfxXbar_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Xbar Xbar
+ * \ingroup IfxLld
+ *
+ * \defgroup IfxLld_Xbar_Bitfields Bitfields
+ * \ingroup IfxLld_Xbar
+ *
+ * \defgroup IfxLld_Xbar_union Union
+ * \ingroup IfxLld_Xbar
+ *
+ * \defgroup IfxLld_Xbar_struct Struct
+ * \ingroup IfxLld_Xbar
+ *
+ */
+#ifndef IFXXBAR_REGDEF_H
+#define IFXXBAR_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Xbar_Bitfields
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef struct _Ifx_XBAR_ACCEN0_Bits
+{
+ unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+ unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+ unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+ unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+ unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+ unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+ unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+ unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+ unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+ unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+ unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+ unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+ unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+ unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+ unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+ unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+ unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+ unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+ unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+ unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+ unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+ unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+ unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+ unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+ unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+ unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+ unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+ unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+ unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+ unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+ unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+ unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_XBAR_ACCEN0_Bits;
+
+/** \brief Access Enable Register 1 */
+typedef struct _Ifx_XBAR_ACCEN1_Bits
+{
+ unsigned int reserved_0:32; /**< \brief \internal Reserved */
+} Ifx_XBAR_ACCEN1_Bits;
+
+/** \brief Arbiter Control Register */
+typedef struct _Ifx_XBAR_ARBCON_Bits
+{
+ unsigned int PRERREN:1; /**< \brief [0:0] SRI Protocol Error Enable (rw) */
+ unsigned int SCERREN:1; /**< \brief [1:1] SRI Starvation Error Enable (rw) */
+ unsigned int SETPRINT:1; /**< \brief [2:2] Set SRI Protocol Interrupt (rwh) */
+ unsigned int SETSCINT:1; /**< \brief [3:3] Set SRI Starvation Interrupt (rwh) */
+ unsigned int INTACK:1; /**< \brief [4:4] Interrupt Acknowledge (rwh) */
+ unsigned int reserved_5:15; /**< \brief \internal Reserved */
+ unsigned int SPC:12; /**< \brief [31:20] Starvation Protection Counter Reload Value (rw) */
+} Ifx_XBAR_ARBCON_Bits;
+
+/** \brief Debug Address Register */
+typedef struct _Ifx_XBAR_ARBITER0_DBADD_Bits
+{
+ unsigned int reserved_0:27; /**< \brief \internal Reserved */
+ unsigned int ADDRESS:1; /**< \brief [27:27] Debug Address Boundary (rw) */
+ unsigned int reserved_28:4; /**< \brief \internal Reserved */
+} Ifx_XBAR_ARBITER0_DBADD_Bits;
+
+/** \brief Debug Mask Address Register */
+typedef struct _Ifx_XBAR_ARBITER0_DBMADD_Bits
+{
+ unsigned int reserved_0:2; /**< \brief \internal Reserved */
+ unsigned int ADDRESS:19; /**< \brief [20:2] Debug Address Boundary (rw) */
+ unsigned int reserved_21:11; /**< \brief \internal Reserved */
+} Ifx_XBAR_ARBITER0_DBMADD_Bits;
+
+/** \brief Debug Address Register */
+typedef struct _Ifx_XBAR_ARBITER1_DBADD_Bits
+{
+ unsigned int reserved_0:31; /**< \brief \internal Reserved */
+ unsigned int ADDRESS:1; /**< \brief [31:31] Debug Address Boundary (rw) */
+} Ifx_XBAR_ARBITER1_DBADD_Bits;
+
+/** \brief Debug Mask Address Register */
+typedef struct _Ifx_XBAR_ARBITER1_DBMADD_Bits
+{
+ unsigned int reserved_0:31; /**< \brief \internal Reserved */
+ unsigned int ADDRESS:1; /**< \brief [31:31] Debug Address Boundary (rw) */
+} Ifx_XBAR_ARBITER1_DBMADD_Bits;
+
+/** \brief Debug Address Register */
+typedef struct _Ifx_XBAR_ARBITER4_DBADD_Bits
+{
+ unsigned int reserved_0:2; /**< \brief \internal Reserved */
+ unsigned int ADDRESS:29; /**< \brief [30:2] Debug Address Boundary (rw) */
+ unsigned int reserved_31:1; /**< \brief \internal Reserved */
+} Ifx_XBAR_ARBITER4_DBADD_Bits;
+
+/** \brief Debug Mask Address Register */
+typedef struct _Ifx_XBAR_ARBITER4_DBMADD_Bits
+{
+ unsigned int reserved_0:2; /**< \brief \internal Reserved */
+ unsigned int ADDRESS:29; /**< \brief [30:2] Debug Address Boundary (rw) */
+ unsigned int reserved_31:1; /**< \brief \internal Reserved */
+} Ifx_XBAR_ARBITER4_DBMADD_Bits;
+
+/** \brief Debug Address Register */
+typedef struct _Ifx_XBAR_ARBITER6_DBADD_Bits
+{
+ unsigned int reserved_0:28; /**< \brief \internal Reserved */
+ unsigned int ADDRESS:3; /**< \brief [30:28] Debug Address Boundary (rw) */
+ unsigned int reserved_31:1; /**< \brief \internal Reserved */
+} Ifx_XBAR_ARBITER6_DBADD_Bits;
+
+/** \brief Debug Mask Address Register */
+typedef struct _Ifx_XBAR_ARBITER6_DBMADD_Bits
+{
+ unsigned int reserved_0:28; /**< \brief \internal Reserved */
+ unsigned int ADDRESS:3; /**< \brief [30:28] Debug Address Boundary (rw) */
+ unsigned int reserved_31:1; /**< \brief \internal Reserved */
+} Ifx_XBAR_ARBITER6_DBMADD_Bits;
+
+/** \brief Debug Address Register */
+typedef struct _Ifx_XBAR_ARBITER7_DBADD_Bits
+{
+ unsigned int reserved_0:29; /**< \brief \internal Reserved */
+ unsigned int ADDRESS:1; /**< \brief [29:29] Debug Address Boundary (rw) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_XBAR_ARBITER7_DBADD_Bits;
+
+/** \brief Debug Mask Address Register */
+typedef struct _Ifx_XBAR_ARBITER7_DBMADD_Bits
+{
+ unsigned int reserved_0:29; /**< \brief \internal Reserved */
+ unsigned int ADDRESS:1; /**< \brief [29:29] Debug Address Boundary (rw) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_XBAR_ARBITER7_DBMADD_Bits;
+
+/** \brief Debug Address Register */
+typedef struct _Ifx_XBAR_ARBITER8_DBADD_Bits
+{
+ unsigned int reserved_0:29; /**< \brief \internal Reserved */
+ unsigned int ADDRESS:1; /**< \brief [29:29] Debug Address Boundary (rw) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_XBAR_ARBITER8_DBADD_Bits;
+
+/** \brief Debug Mask Address Register */
+typedef struct _Ifx_XBAR_ARBITER8_DBMADD_Bits
+{
+ unsigned int reserved_0:29; /**< \brief \internal Reserved */
+ unsigned int ADDRESS:1; /**< \brief [29:29] Debug Address Boundary (rw) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_XBAR_ARBITER8_DBMADD_Bits;
+
+/** \brief Debug Address Register */
+typedef struct _Ifx_XBAR_ARBITERD_DBADD_Bits
+{
+ unsigned int reserved_0:2; /**< \brief \internal Reserved */
+ unsigned int ADDRESS:30; /**< \brief [31:2] Debug Address Boundary (rw) */
+} Ifx_XBAR_ARBITERD_DBADD_Bits;
+
+/** \brief Debug Mask Address Register */
+typedef struct _Ifx_XBAR_ARBITERD_DBMADD_Bits
+{
+ unsigned int ADDRESS:32; /**< \brief [31:0] Debug Address Boundary (rw) */
+} Ifx_XBAR_ARBITERD_DBMADD_Bits;
+
+/** \brief Debug Control Register */
+typedef struct _Ifx_XBAR_DBCON_Bits
+{
+ unsigned int DBEN:1; /**< \brief [0:0] Status of OCDS Enable Signal (r) */
+ unsigned int DBSAT:1; /**< \brief [1:1] Debug (OCDS) Trigger Status (rh) */
+ unsigned int REARM:1; /**< \brief [2:2] Rearm Debug (OCDS) Trigger (w) */
+ unsigned int SETDBEVT:1; /**< \brief [3:3] Set Debug Event (w) */
+ unsigned int reserved_4:12; /**< \brief \internal Reserved */
+ unsigned int RDEN:1; /**< \brief [16:16] Read Trigger Enable (rw) */
+ unsigned int WREN:1; /**< \brief [17:17] Write Trigger Enable (rw) */
+ unsigned int SVMEN:1; /**< \brief [18:18] SVM Trigger Enable (rw) */
+ unsigned int ADDEN:1; /**< \brief [19:19] Address Trigger Enable (rw) */
+ unsigned int ERREN:1; /**< \brief [20:20] Error Trigger Enable (rw) */
+ unsigned int reserved_21:2; /**< \brief \internal Reserved */
+ unsigned int MASEN:1; /**< \brief [23:23] Master Trigger Enable (rw) */
+ unsigned int MASTER:6; /**< \brief [29:24] Master TAG ID Trigger Selector (rw) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_XBAR_DBCON_Bits;
+
+/** \brief Debug Trigger Event Status Register */
+typedef struct _Ifx_XBAR_DBSAT_Bits
+{
+ unsigned int SCI0:1; /**< \brief [0:0] SCI Debug Trigger Event Status (rwh) */
+ unsigned int SCI1:1; /**< \brief [1:1] SCI Debug Trigger Event Status (rwh) */
+ unsigned int reserved_2:2; /**< \brief \internal Reserved */
+ unsigned int SCI4:1; /**< \brief [4:4] SCI Debug Trigger Event Status (rwh) */
+ unsigned int reserved_5:1; /**< \brief \internal Reserved */
+ unsigned int SCI6:1; /**< \brief [6:6] SCI Debug Trigger Event Status (rwh) */
+ unsigned int SCI7:1; /**< \brief [7:7] SCI Debug Trigger Event Status (rwh) */
+ unsigned int SCI8:1; /**< \brief [8:8] SCI Debug Trigger Event Status (rwh) */
+ unsigned int reserved_9:6; /**< \brief \internal Reserved */
+ unsigned int SCID:1; /**< \brief [15:15] Default Slave Debug Trigger Event Status (rwh) */
+ unsigned int reserved_16:16; /**< \brief \internal Reserved */
+} Ifx_XBAR_DBSAT_Bits;
+
+/** \brief Error/Debug Capture Register */
+typedef struct _Ifx_XBAR_ERR_Bits
+{
+ unsigned int RD:1; /**< \brief [0:0] Read Indication Status (rh) */
+ unsigned int WR:1; /**< \brief [1:1] Write Indication Status (rh) */
+ unsigned int SVM:1; /**< \brief [2:2] Supervisor Mode Indication Status (rh) */
+ unsigned int reserved_3:1; /**< \brief \internal Reserved */
+ unsigned int OPC:4; /**< \brief [7:4] Operation Code (rh) */
+ unsigned int TR_ID:8; /**< \brief [15:8] Transaction ID (rh) */
+ unsigned int ADDR_ECC:8; /**< \brief [23:16] SRI Address Phase ECC (rh) */
+ unsigned int MCI_SBS:8; /**< \brief [31:24] MCI Sideband Signals [7:0] (rh) */
+} Ifx_XBAR_ERR_Bits;
+
+/** \brief Error/Debug Address Capture Register */
+typedef struct _Ifx_XBAR_ERRADDR_Bits
+{
+ unsigned int ADDR:32; /**< \brief [31:0] Transaction Address (rh) */
+} Ifx_XBAR_ERRADDR_Bits;
+
+/** \brief External Control Register D */
+typedef struct _Ifx_XBAR_EXTCOND_Bits
+{
+ unsigned int reserved_0:3; /**< \brief \internal Reserved */
+ unsigned int WFWD:1; /**< \brief [3:3] Wait for FPI Write Data (rw) */
+ unsigned int reserved_4:2; /**< \brief \internal Reserved */
+ unsigned int FREQDISF:1; /**< \brief [6:6] Disable Fast Request Feature for FPI to SRI Transactions (rw) */
+ unsigned int reserved_7:2; /**< \brief \internal Reserved */
+ unsigned int NODELTR:1; /**< \brief [9:9] Control Signal for deferred transactions (rw) */
+ unsigned int NORMW:1; /**< \brief [10:10] Control Signal for deferred transactions (rw) */
+ unsigned int reserved_11:2; /**< \brief \internal Reserved */
+ unsigned int MAX_WS:7; /**< \brief [19:13] FPI-Bus Wait State Retry Ratio (rw) */
+ unsigned int reserved_20:12; /**< \brief \internal Reserved */
+} Ifx_XBAR_EXTCOND_Bits;
+
+/** \brief Module Identification Register */
+typedef struct _Ifx_XBAR_ID_Bits
+{
+ unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
+ unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
+ unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
+} Ifx_XBAR_ID_Bits;
+
+/** \brief Transaction ID Interrupt Enable Register */
+typedef struct _Ifx_XBAR_IDINTEN_Bits
+{
+ unsigned int ENSCI0:1; /**< \brief [0:0] Enable ID Error from SCI0 (rw) */
+ unsigned int ENSCI1:1; /**< \brief [1:1] Enable ID Error from SCI1 (rw) */
+ unsigned int reserved_2:2; /**< \brief \internal Reserved */
+ unsigned int ENSCI4:1; /**< \brief [4:4] Enable ID Error from SCI4 (rw) */
+ unsigned int reserved_5:1; /**< \brief \internal Reserved */
+ unsigned int ENSCI6:1; /**< \brief [6:6] Enable ID Error from SCI6 (rw) */
+ unsigned int ENSCI7:1; /**< \brief [7:7] Enable ID Error from SCI7 (rw) */
+ unsigned int ENSCI8:1; /**< \brief [8:8] Enable ID Error from SCI8 (rw) */
+ unsigned int reserved_9:6; /**< \brief \internal Reserved */
+ unsigned int ENSCID:1; /**< \brief [15:15] Enable ID Error from Default Slave (rw) */
+ unsigned int ENMCI0:1; /**< \brief [16:16] Enable ID Error from MCI0 (rw) */
+ unsigned int reserved_17:3; /**< \brief \internal Reserved */
+ unsigned int ENMCI4:1; /**< \brief [20:20] Enable ID Error from MCI4 (rw) */
+ unsigned int ENMCI5:1; /**< \brief [21:21] Enable ID Error from MCI5 (rw) */
+ unsigned int reserved_22:2; /**< \brief \internal Reserved */
+ unsigned int ENMCI8:1; /**< \brief [24:24] Enable ID Error from MCI8 (rw) */
+ unsigned int ENMCI9:1; /**< \brief [25:25] Enable ID Error from MCI9 (rw) */
+ unsigned int reserved_26:2; /**< \brief \internal Reserved */
+ unsigned int ENMCI12:1; /**< \brief [28:28] Enable ID Error from MCI12 (rw) */
+ unsigned int ENMCI13:1; /**< \brief [29:29] Enable ID Error from MCI13 (rw) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_XBAR_IDINTEN_Bits;
+
+/** \brief Transaction ID Interrupt Status Register */
+typedef struct _Ifx_XBAR_IDINTSAT_Bits
+{
+ unsigned int IDSCI0:1; /**< \brief [0:0] Transaction ID Error from SCI0 Status (rwh) */
+ unsigned int IDSCI1:1; /**< \brief [1:1] Transaction ID Error from SCI1 Status (rwh) */
+ unsigned int reserved_2:2; /**< \brief \internal Reserved */
+ unsigned int IDCSCI4:1; /**< \brief [4:4] Transaction ID Error from SCI4 Status (rwh) */
+ unsigned int reserved_5:1; /**< \brief \internal Reserved */
+ unsigned int IDSCI6:1; /**< \brief [6:6] Transaction ID Error from SCI6 Status (rwh) */
+ unsigned int IDSCI7:1; /**< \brief [7:7] Transaction ID Error from SCI7 Status (rwh) */
+ unsigned int IDSCI8:1; /**< \brief [8:8] Transaction ID Error from SCI8 Status (rwh) */
+ unsigned int reserved_9:6; /**< \brief \internal Reserved */
+ unsigned int IDSCID:1; /**< \brief [15:15] Transaction ID Error from Default Slave Status (rwh) */
+ unsigned int IDMCI0:1; /**< \brief [16:16] Transaction ID Error from MCI0 Status (rwh) */
+ unsigned int reserved_17:3; /**< \brief \internal Reserved */
+ unsigned int IDMCI4:1; /**< \brief [20:20] Transaction ID Error from MCI4 Status (rwh) */
+ unsigned int IDMCI5:1; /**< \brief [21:21] Transaction ID Error from MCI5 Status (rwh) */
+ unsigned int reserved_22:2; /**< \brief \internal Reserved */
+ unsigned int IDMCI8:1; /**< \brief [24:24] Transaction ID Error from MCI8 Status (rwh) */
+ unsigned int IDMCI9:1; /**< \brief [25:25] Transaction ID Error from MCI9 Status (rwh) */
+ unsigned int reserved_26:2; /**< \brief \internal Reserved */
+ unsigned int IDMCI12:1; /**< \brief [28:28] Transaction ID Error from MCI12 Status (rwh) */
+ unsigned int IDMCI13:1; /**< \brief [29:29] Transaction ID Error from MCI13 Status (rwh) */
+ unsigned int reserved_30:2; /**< \brief \internal Reserved */
+} Ifx_XBAR_IDINTSAT_Bits;
+
+/** \brief Arbiter Interrupt Status Register */
+typedef struct _Ifx_XBAR_INTSAT_Bits
+{
+ unsigned int SCSCI0:1; /**< \brief [0:0] Starvation Error from SCI0 Status (rwh) */
+ unsigned int SCSCI1:1; /**< \brief [1:1] Starvation Error from SCI1 Status (rwh) */
+ unsigned int reserved_2:2; /**< \brief \internal Reserved */
+ unsigned int SCSCI4:1; /**< \brief [4:4] Starvation Error from SCI4 Status (rwh) */
+ unsigned int reserved_5:1; /**< \brief \internal Reserved */
+ unsigned int SCSCI6:1; /**< \brief [6:6] Starvation Error from SCI6 Status (rwh) */
+ unsigned int SCSCI7:1; /**< \brief [7:7] Starvation Error from SCI7 Status (rwh) */
+ unsigned int SCSCI8:1; /**< \brief [8:8] Starvation Error from SCI8 Status (rwh) */
+ unsigned int reserved_9:6; /**< \brief \internal Reserved */
+ unsigned int SCSCID:1; /**< \brief [15:15] Starvation Error from Default Slave Status (rwh) */
+ unsigned int PRSCI0:1; /**< \brief [16:16] Protocol Error from SCI0 Status (rwh) */
+ unsigned int PRSCI1:1; /**< \brief [17:17] Protocol Error from SCI1 Status (rwh) */
+ unsigned int reserved_18:2; /**< \brief \internal Reserved */
+ unsigned int PRSCI4:1; /**< \brief [20:20] Protocol Error from SCI4 Status (rwh) */
+ unsigned int reserved_21:1; /**< \brief \internal Reserved */
+ unsigned int PRSCI6:1; /**< \brief [22:22] Protocol Error from SCI6 Status (rwh) */
+ unsigned int PRSCI7:1; /**< \brief [23:23] Protocol Error from SCI7 Status (rwh) */
+ unsigned int PRSCI8:1; /**< \brief [24:24] Protocol Error from SCI8 Status (rwh) */
+ unsigned int reserved_25:6; /**< \brief \internal Reserved */
+ unsigned int PRSCID:1; /**< \brief [31:31] Protocol Error from Default Slave Status (rwh) */
+} Ifx_XBAR_INTSAT_Bits;
+
+/** \brief Arbiter Priority Register */
+typedef struct _Ifx_XBAR_PRIOH_Bits
+{
+ unsigned int MASTER8:3; /**< \brief [2:0] Master 8 Priority (rw) */
+ unsigned int reserved_3:1; /**< \brief \internal Reserved */
+ unsigned int MASTER9:3; /**< \brief [6:4] Master 9 Priority (rw) */
+ unsigned int reserved_7:9; /**< \brief \internal Reserved */
+ unsigned int MASTER12:3; /**< \brief [18:16] Master 12 Priority (rw) */
+ unsigned int reserved_19:1; /**< \brief \internal Reserved */
+ unsigned int MASTER13:3; /**< \brief [22:20] Master 13 Priority (rw) */
+ unsigned int reserved_23:9; /**< \brief \internal Reserved */
+} Ifx_XBAR_PRIOH_Bits;
+
+/** \brief Arbiter Priority Register */
+typedef struct _Ifx_XBAR_PRIOL_Bits
+{
+ unsigned int MASTER0:3; /**< \brief [2:0] Master 0 Priority (rw) */
+ unsigned int reserved_3:13; /**< \brief \internal Reserved */
+ unsigned int MASTER4:3; /**< \brief [18:16] Master 4 Priority (rw) */
+ unsigned int reserved_19:1; /**< \brief \internal Reserved */
+ unsigned int MASTER5:3; /**< \brief [22:20] Master 5 Priority (rw) */
+ unsigned int reserved_23:9; /**< \brief \internal Reserved */
+} Ifx_XBAR_PRIOL_Bits;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Xbar_union
+ * \{ */
+
+/** \brief Access Enable Register 0 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_XBAR_ACCEN0_Bits B; /**< \brief Bitfield access */
+} Ifx_XBAR_ACCEN0;
+
+/** \brief Access Enable Register 1 */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_XBAR_ACCEN1_Bits B; /**< \brief Bitfield access */
+} Ifx_XBAR_ACCEN1;
+
+/** \brief Arbiter Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_XBAR_ARBCON_Bits B; /**< \brief Bitfield access */
+} Ifx_XBAR_ARBCON;
+
+/** \brief Debug Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_XBAR_ARBITER0_DBADD_Bits B; /**< \brief Bitfield access */
+} Ifx_XBAR_ARBITER0_DBADD;
+
+/** \brief Debug Mask Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_XBAR_ARBITER0_DBMADD_Bits B; /**< \brief Bitfield access */
+} Ifx_XBAR_ARBITER0_DBMADD;
+
+/** \brief Debug Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_XBAR_ARBITER1_DBADD_Bits B; /**< \brief Bitfield access */
+} Ifx_XBAR_ARBITER1_DBADD;
+
+/** \brief Debug Mask Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_XBAR_ARBITER1_DBMADD_Bits B; /**< \brief Bitfield access */
+} Ifx_XBAR_ARBITER1_DBMADD;
+
+/** \brief Debug Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_XBAR_ARBITER4_DBADD_Bits B; /**< \brief Bitfield access */
+} Ifx_XBAR_ARBITER4_DBADD;
+
+/** \brief Debug Mask Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_XBAR_ARBITER4_DBMADD_Bits B; /**< \brief Bitfield access */
+} Ifx_XBAR_ARBITER4_DBMADD;
+
+/** \brief Debug Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_XBAR_ARBITER6_DBADD_Bits B; /**< \brief Bitfield access */
+} Ifx_XBAR_ARBITER6_DBADD;
+
+/** \brief Debug Mask Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_XBAR_ARBITER6_DBMADD_Bits B; /**< \brief Bitfield access */
+} Ifx_XBAR_ARBITER6_DBMADD;
+
+/** \brief Debug Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_XBAR_ARBITER7_DBADD_Bits B; /**< \brief Bitfield access */
+} Ifx_XBAR_ARBITER7_DBADD;
+
+/** \brief Debug Mask Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_XBAR_ARBITER7_DBMADD_Bits B; /**< \brief Bitfield access */
+} Ifx_XBAR_ARBITER7_DBMADD;
+
+/** \brief Debug Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_XBAR_ARBITER8_DBADD_Bits B; /**< \brief Bitfield access */
+} Ifx_XBAR_ARBITER8_DBADD;
+
+/** \brief Debug Mask Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_XBAR_ARBITER8_DBMADD_Bits B; /**< \brief Bitfield access */
+} Ifx_XBAR_ARBITER8_DBMADD;
+
+/** \brief Debug Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_XBAR_ARBITERD_DBADD_Bits B; /**< \brief Bitfield access */
+} Ifx_XBAR_ARBITERD_DBADD;
+
+/** \brief Debug Mask Address Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_XBAR_ARBITERD_DBMADD_Bits B; /**< \brief Bitfield access */
+} Ifx_XBAR_ARBITERD_DBMADD;
+
+/** \brief Debug Control Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_XBAR_DBCON_Bits B; /**< \brief Bitfield access */
+} Ifx_XBAR_DBCON;
+
+/** \brief Debug Trigger Event Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_XBAR_DBSAT_Bits B; /**< \brief Bitfield access */
+} Ifx_XBAR_DBSAT;
+
+/** \brief Error/Debug Capture Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_XBAR_ERR_Bits B; /**< \brief Bitfield access */
+} Ifx_XBAR_ERR;
+
+/** \brief Error/Debug Address Capture Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_XBAR_ERRADDR_Bits B; /**< \brief Bitfield access */
+} Ifx_XBAR_ERRADDR;
+
+/** \brief External Control Register D */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_XBAR_EXTCOND_Bits B; /**< \brief Bitfield access */
+} Ifx_XBAR_EXTCOND;
+
+/** \brief Module Identification Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_XBAR_ID_Bits B; /**< \brief Bitfield access */
+} Ifx_XBAR_ID;
+
+/** \brief Transaction ID Interrupt Enable Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_XBAR_IDINTEN_Bits B; /**< \brief Bitfield access */
+} Ifx_XBAR_IDINTEN;
+
+/** \brief Transaction ID Interrupt Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_XBAR_IDINTSAT_Bits B; /**< \brief Bitfield access */
+} Ifx_XBAR_IDINTSAT;
+
+/** \brief Arbiter Interrupt Status Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_XBAR_INTSAT_Bits B; /**< \brief Bitfield access */
+} Ifx_XBAR_INTSAT;
+
+/** \brief Arbiter Priority Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_XBAR_PRIOH_Bits B; /**< \brief Bitfield access */
+} Ifx_XBAR_PRIOH;
+
+/** \brief Arbiter Priority Register */
+typedef union
+{
+ unsigned int U; /**< \brief Unsigned access */
+ signed int I; /**< \brief Signed access */
+ Ifx_XBAR_PRIOL_Bits B; /**< \brief Bitfield access */
+} Ifx_XBAR_PRIOL;
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Xbar_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L1
+ * \{ */
+
+/** \brief Arbiter objects */
+typedef volatile struct _Ifx_XBAR_ARBITER0
+{
+ Ifx_XBAR_ARBCON ARBCON; /**< \brief 0, Arbiter Control Register */
+ Ifx_XBAR_PRIOH PRIOH; /**< \brief 4, Arbiter Priority Register */
+ Ifx_XBAR_PRIOL PRIOL; /**< \brief 8, Arbiter Priority Register */
+ Ifx_XBAR_ERRADDR ERRADDR; /**< \brief C, Error/Debug Address Capture Register */
+ Ifx_XBAR_ERR ERR; /**< \brief 10, Error/Debug Capture Register */
+ Ifx_XBAR_DBCON DBCON; /**< \brief 14, Debug Control Register */
+ Ifx_XBAR_ARBITER0_DBADD DBADD; /**< \brief 18, Debug Address Register */
+ Ifx_XBAR_ARBITER0_DBMADD DBMADD; /**< \brief 1C, Debug Mask Address Register */
+} Ifx_XBAR_ARBITER0;
+
+/** \brief Arbiter objects */
+typedef volatile struct _Ifx_XBAR_ARBITER1
+{
+ Ifx_XBAR_ARBCON ARBCON; /**< \brief 0, Arbiter Control Register */
+ Ifx_XBAR_PRIOH PRIOH; /**< \brief 4, Arbiter Priority Register */
+ Ifx_XBAR_PRIOL PRIOL; /**< \brief 8, Arbiter Priority Register */
+ Ifx_XBAR_ERRADDR ERRADDR; /**< \brief C, Error/Debug Address Capture Register */
+ Ifx_XBAR_ERR ERR; /**< \brief 10, Error/Debug Capture Register */
+ Ifx_XBAR_DBCON DBCON; /**< \brief 14, Debug Control Register */
+ Ifx_XBAR_ARBITER1_DBADD DBADD; /**< \brief 18, Debug Address Register */
+ Ifx_XBAR_ARBITER1_DBMADD DBMADD; /**< \brief 1C, Debug Mask Address Register */
+} Ifx_XBAR_ARBITER1;
+
+/** \brief Arbiter objects */
+typedef volatile struct _Ifx_XBAR_ARBITER4
+{
+ Ifx_XBAR_ARBCON ARBCON; /**< \brief 0, Arbiter Control Register */
+ Ifx_XBAR_PRIOH PRIOH; /**< \brief 4, Arbiter Priority Register */
+ Ifx_XBAR_PRIOL PRIOL; /**< \brief 8, Arbiter Priority Register */
+ Ifx_XBAR_ERRADDR ERRADDR; /**< \brief C, Error/Debug Address Capture Register */
+ Ifx_XBAR_ERR ERR; /**< \brief 10, Error/Debug Capture Register */
+ Ifx_XBAR_DBCON DBCON; /**< \brief 14, Debug Control Register */
+ Ifx_XBAR_ARBITER4_DBADD DBADD; /**< \brief 18, Debug Address Register */
+ Ifx_XBAR_ARBITER4_DBMADD DBMADD; /**< \brief 1C, Debug Mask Address Register */
+} Ifx_XBAR_ARBITER4;
+
+/** \brief Arbiter objects */
+typedef volatile struct _Ifx_XBAR_ARBITER6
+{
+ Ifx_XBAR_ARBCON ARBCON; /**< \brief 0, Arbiter Control Register */
+ Ifx_XBAR_PRIOH PRIOH; /**< \brief 4, Arbiter Priority Register */
+ Ifx_XBAR_PRIOL PRIOL; /**< \brief 8, Arbiter Priority Register */
+ Ifx_XBAR_ERRADDR ERRADDR; /**< \brief C, Error/Debug Address Capture Register */
+ Ifx_XBAR_ERR ERR; /**< \brief 10, Error/Debug Capture Register */
+ Ifx_XBAR_DBCON DBCON; /**< \brief 14, Debug Control Register */
+ Ifx_XBAR_ARBITER6_DBADD DBADD; /**< \brief 18, Debug Address Register */
+ Ifx_XBAR_ARBITER6_DBMADD DBMADD; /**< \brief 1C, Debug Mask Address Register */
+} Ifx_XBAR_ARBITER6;
+
+/** \brief Arbiter objects */
+typedef volatile struct _Ifx_XBAR_ARBITER7
+{
+ Ifx_XBAR_ARBCON ARBCON; /**< \brief 0, Arbiter Control Register */
+ Ifx_XBAR_PRIOH PRIOH; /**< \brief 4, Arbiter Priority Register */
+ Ifx_XBAR_PRIOL PRIOL; /**< \brief 8, Arbiter Priority Register */
+ Ifx_XBAR_ERRADDR ERRADDR; /**< \brief C, Error/Debug Address Capture Register */
+ Ifx_XBAR_ERR ERR; /**< \brief 10, Error/Debug Capture Register */
+ Ifx_XBAR_DBCON DBCON; /**< \brief 14, Debug Control Register */
+ Ifx_XBAR_ARBITER7_DBADD DBADD; /**< \brief 18, Debug Address Register */
+ Ifx_XBAR_ARBITER7_DBMADD DBMADD; /**< \brief 1C, Debug Mask Address Register */
+} Ifx_XBAR_ARBITER7;
+
+/** \brief Arbiter objects */
+typedef volatile struct _Ifx_XBAR_ARBITER8
+{
+ Ifx_XBAR_ARBCON ARBCON; /**< \brief 0, Arbiter Control Register */
+ Ifx_XBAR_PRIOH PRIOH; /**< \brief 4, Arbiter Priority Register */
+ Ifx_XBAR_PRIOL PRIOL; /**< \brief 8, Arbiter Priority Register */
+ Ifx_XBAR_ERRADDR ERRADDR; /**< \brief C, Error/Debug Address Capture Register */
+ Ifx_XBAR_ERR ERR; /**< \brief 10, Error/Debug Capture Register */
+ Ifx_XBAR_DBCON DBCON; /**< \brief 14, Debug Control Register */
+ Ifx_XBAR_ARBITER8_DBADD DBADD; /**< \brief 18, Debug Address Register */
+ Ifx_XBAR_ARBITER8_DBMADD DBMADD; /**< \brief 1C, Debug Mask Address Register */
+} Ifx_XBAR_ARBITER8;
+
+/** \brief Arbiter objects */
+typedef volatile struct _Ifx_XBAR_ARBITERD
+{
+ Ifx_XBAR_ARBCON ARBCON; /**< \brief 0, Arbiter Control Register */
+ Ifx_XBAR_PRIOH PRIOH; /**< \brief 4, Arbiter Priority Register */
+ Ifx_XBAR_PRIOL PRIOL; /**< \brief 8, Arbiter Priority Register */
+ Ifx_XBAR_ERRADDR ERRADDR; /**< \brief C, Error/Debug Address Capture Register */
+ Ifx_XBAR_ERR ERR; /**< \brief 10, Error/Debug Capture Register */
+ Ifx_XBAR_DBCON DBCON; /**< \brief 14, Debug Control Register */
+ Ifx_XBAR_ARBITERD_DBADD DBADD; /**< \brief 18, Debug Address Register */
+ Ifx_XBAR_ARBITERD_DBMADD DBMADD; /**< \brief 1C, Debug Mask Address Register */
+} Ifx_XBAR_ARBITERD;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Xbar_struct
+ * \{ */
+/******************************************************************************/
+/** \name Object L0
+ * \{ */
+
+/** \brief XBAR object */
+typedef volatile struct _Ifx_XBAR
+{
+ Ifx_XBAR_EXTCOND EXTCOND; /**< \brief 0, External Control Register D */
+ Ifx_XBAR_ARBITERD ARBITERD; /**< \brief 4, Arbiter objects */
+ unsigned char reserved_24[32]; /**< \brief 24, \internal Reserved */
+ Ifx_XBAR_ARBITER0 ARBITER0; /**< \brief 44, Arbiter objects */
+ unsigned char reserved_64[32]; /**< \brief 64, \internal Reserved */
+ Ifx_XBAR_ARBITER1 ARBITER1; /**< \brief 84, Arbiter objects */
+ unsigned char reserved_A4[160]; /**< \brief A4, \internal Reserved */
+ Ifx_XBAR_ARBITER4 ARBITER4; /**< \brief 144, Arbiter objects */
+ unsigned char reserved_164[96]; /**< \brief 164, \internal Reserved */
+ Ifx_XBAR_ARBITER6 ARBITER6; /**< \brief 1C4, Arbiter objects */
+ unsigned char reserved_1E4[32]; /**< \brief 1E4, \internal Reserved */
+ Ifx_XBAR_ARBITER7 ARBITER7; /**< \brief 204, Arbiter objects */
+ unsigned char reserved_224[32]; /**< \brief 224, \internal Reserved */
+ Ifx_XBAR_ARBITER8 ARBITER8; /**< \brief 244, Arbiter objects */
+ unsigned char reserved_264[420]; /**< \brief 264, \internal Reserved */
+ Ifx_XBAR_ID ID; /**< \brief 408, Module Identification Register */
+ Ifx_XBAR_DBSAT DBSAT; /**< \brief 40C, Debug Trigger Event Status Register */
+ Ifx_XBAR_INTSAT INTSAT; /**< \brief 410, Arbiter Interrupt Status Register */
+ Ifx_XBAR_IDINTSAT IDINTSAT; /**< \brief 414, Transaction ID Interrupt Status Register */
+ Ifx_XBAR_IDINTEN IDINTEN; /**< \brief 418, Transaction ID Interrupt Enable Register */
+ unsigned char reserved_41C[220]; /**< \brief 41C, \internal Reserved */
+ Ifx_XBAR_ACCEN1 ACCEN1; /**< \brief 4F8, Access Enable Register 1 */
+ Ifx_XBAR_ACCEN0 ACCEN0; /**< \brief 4FC, Access Enable Register 0 */
+} Ifx_XBAR;
+/** \} */
+/******************************************************************************/
+/** \} */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXXBAR_REGDEF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/Ifx_TypesReg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/Ifx_TypesReg.h
new file mode 100644
index 0000000..0f52918
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/Ifx_TypesReg.h
@@ -0,0 +1,74 @@
+/**
+ * \file Ifx_TypesReg.h
+ * \brief
+ * \copyright Copyright (c) 2012 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: IFXREGTYPES_V1.0.R0
+ *
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ */
+
+#ifndef IFX_TYPESREG_H
+#define IFX_TYPESREG_H 1
+/******************************************************************************/
+
+#if defined(__TASKING__)
+#define Ifx_Strict_16Bit unsigned __sfrbit16
+#define Ifx_Strict_32Bit unsigned __sfrbit32
+#endif
+#if defined(__HIGHTEC__)
+#define Ifx_Strict_16Bit volatile unsigned short
+#define Ifx_Strict_32Bit volatile unsigned int
+#endif
+#if defined(__DCC__)
+#define Ifx_Strict_16Bit unsigned short
+#define Ifx_Strict_32Bit unsigned int
+#endif
+#if defined(__ghs__)
+#define Ifx_Strict_16Bit volatile unsigned short
+#define Ifx_Strict_32Bit volatile unsigned int
+#endif
+
+/*Backward Compatibility Macros for VADC registers*/
+#define Ifx_VADC_RES Ifx_VADC_G_RES
+#define Ifx_VADC_RESD Ifx_VADC_G_RESD
+#define Ifx_VADC_CHCTR Ifx_VADC_G_CHCTR
+#define Ifx_VADC_RCR Ifx_VADC_G_RCR
+
+/******************************************************************************/
+#endif /* IFX_TYPESREG_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/Ifx_reg.h b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/Ifx_reg.h
new file mode 100644
index 0000000..3a1c17d
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/Ifx_reg.h
@@ -0,0 +1,90 @@
+/**
+ * \file Ifx_reg.h
+ * \brief
+ * \copyright Copyright (c) 2012 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC26XB_UM_V1.2.R0
+ * Specification: Refer to module specific file heading
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ */
+#ifndef IFX_REG_H
+#define IFX_REG_H 1
+
+#include "IfxAsclin_reg.h"
+#include "IfxCan_reg.h"
+#include "IfxCbs_reg.h"
+#include "IfxCcu6_reg.h"
+#include "IfxCif_reg.h"
+#include "IfxCpu_reg.h"
+#include "IfxDma_reg.h"
+#include "IfxDsadc_reg.h"
+#include "IfxEbcu_reg.h"
+#include "IfxEmem_reg.h"
+#include "IfxEray_reg.h"
+#include "IfxEth_reg.h"
+#include "IfxFce_reg.h"
+#include "IfxFft_reg.h"
+#include "IfxFlash_reg.h"
+#include "IfxGpt12_reg.h"
+#include "IfxGtm_reg.h"
+#include "IfxHsct_reg.h"
+#include "IfxHssl_reg.h"
+#include "IfxI2c_reg.h"
+#include "IfxInt_reg.h"
+#include "IfxIom_reg.h"
+#include "IfxLmu_reg.h"
+#include "IfxMc_reg.h"
+#include "IfxMsc_reg.h"
+#include "IfxMtu_reg.h"
+#include "IfxOvc_reg.h"
+#include "IfxPmu_reg.h"
+#include "IfxPort_reg.h"
+#include "IfxPsi5_reg.h"
+#include "IfxPsi5s_reg.h"
+#include "IfxQspi_reg.h"
+#include "IfxSbcu_reg.h"
+#include "IfxScu_reg.h"
+#include "IfxSent_reg.h"
+#include "IfxSmu_reg.h"
+#include "IfxSrc_reg.h"
+#include "IfxStm_reg.h"
+#include "IfxVadc_reg.h"
+#include "IfxXbar_reg.h"
+
+#endif /*IFX_REG_H*/
+
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/_package.xml b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/_package.xml
new file mode 100644
index 0000000..44e406a
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/_package.xml
@@ -0,0 +1,630 @@
+
+
+ _REG_TC26XB
+ TC26XB_UM_V1.2.R0
+
+
+
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxAsclin_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxAsclin_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxAsclin_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxCan_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxCan_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxCan_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxCbs_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxCbs_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxCbs_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxCcu6_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxCcu6_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxCcu6_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxCif_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxCif_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxCif_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxCpu_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxCpu_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxCpu_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxDma_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxDma_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxDma_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxDsadc_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxDsadc_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxDsadc_regdef.h
+
+
+ TC2XXED_TS_V1.0.R2
+ ./
+ IfxEbcu_bf.h
+
+
+ TC2XXED_TS_V1.0.R2
+ ./
+ IfxEbcu_reg.h
+
+
+ TC2XXED_TS_V1.0.R2
+ ./
+ IfxEbcu_regdef.h
+
+
+ TC2XXED_TS_V1.0.R2
+ ./
+ IfxEmem_bf.h
+
+
+ TC2XXED_TS_V1.0.R2
+ ./
+ IfxEmem_reg.h
+
+
+ TC2XXED_TS_V1.0.R2
+ ./
+ IfxEmem_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxEray_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxEray_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxEray_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxEth_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxEth_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxEth_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxFce_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxFce_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxFce_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxFft_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxFft_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxFft_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxFlash_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxFlash_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxFlash_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxGpt12_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxGpt12_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxGpt12_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxGtm_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxGtm_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxGtm_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxHsct_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxHsct_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxHsct_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxHssl_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxHssl_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxHssl_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxI2c_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxI2c_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxI2c_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxInt_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxInt_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxInt_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxIom_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxIom_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxIom_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxLmu_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxLmu_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxLmu_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxMc_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxMc_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxMc_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxMsc_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxMsc_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxMsc_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxMtu_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxMtu_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxMtu_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxOvc_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxOvc_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxOvc_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxPmu_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxPmu_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxPmu_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxPort_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxPort_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxPort_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxPsi5s_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxPsi5s_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxPsi5s_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxPsi5_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxPsi5_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxPsi5_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxQspi_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxQspi_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxQspi_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxSbcu_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxSbcu_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxSbcu_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxScu_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxScu_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxScu_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxSent_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxSent_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxSent_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxSmu_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxSmu_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxSmu_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxSrc_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxSrc_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxSrc_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxStm_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxStm_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxStm_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxVadc_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxVadc_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxVadc_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxXbar_bf.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxXbar_reg.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ IfxXbar_regdef.h
+
+
+ TC26XB_UM_V1.2.R0
+ ./
+ Ifx_reg.h
+
+
+ IFXREGTYPES_V1.0.R0
+ ./
+ Ifx_TypesReg.h
+
+
+
+
+
+
+
+
+
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/If/Ccu6If/Icu.h b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/If/Ccu6If/Icu.h
new file mode 100644
index 0000000..216177e
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/If/Ccu6If/Icu.h
@@ -0,0 +1,87 @@
+/**
+ * \file Icu.h
+ * \brief ICU interface
+ *
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ * $Date: 2014-02-27 20:08:18 GMT$
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ * \defgroup library_srvsw_if_icu ICU interface
+ * \ingroup library_srvsw_if
+ *
+ */
+
+#ifndef ICU_H_
+#define ICU_H_ 1
+
+#include "Cpu/Std/Ifx_Types.h"
+
+typedef struct Icu_s Icu;
+typedef void (*Icu_StartCapture)(Icu *handle);
+typedef void (*Icu_StopCapture)(Icu *handle);
+typedef void (*Icu_GetTimeStamp)(Icu *handle);
+
+typedef struct
+{
+ Icu_StartCapture startCapture;
+ Icu_StopCapture stopCapture;
+ Icu_GetTimeStamp getTimeStamp;
+} Icu_Functions;
+
+/** \brief Structure of the Icu interface */
+struct Icu_s
+{
+ float32 frequency; /**< \brief dummy member to avoid error */
+#if IFX_CFG_USE_STANDARD_INTERFACE
+ Icu_Functions functions; /**< \brief Actual timer period */
+#endif
+};
+
+/** \brief Configuration structure of the Icu interface */
+typedef struct
+{
+ float32 frequency; /**< \brief dummy member to avoid error */
+// IfxCcu6_Timer *timer;
+} Icu_Config;
+
+#if IFX_CFG_USE_STANDARD_INTERFACE
+IFX_INLINE void Icu_startCapture(Icu *handle) {handle->functions.startCapture(handle); }
+IFX_INLINE void Icu_stopCapture(Icu *handle) {handle->functions.stopCapture(handle); }
+IFX_INLINE void Icu_getTimeStamp(Icu *handle) {handle->functions.getTimeStamp(handle); }
+#endif
+
+#endif /* ICU_H_ */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/If/Ccu6If/PwmHl.h b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/If/Ccu6If/PwmHl.h
new file mode 100644
index 0000000..3a41003
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/If/Ccu6If/PwmHl.h
@@ -0,0 +1,95 @@
+/**
+ * \file PwmHl.h
+ * \brief Multi-channels, dual-complementary PWM interface
+ *
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ * $Date: 2014-02-27 20:08:18 GMT$
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ * \defgroup library_srvsw_if_pwmhl PWM HL interface
+ * \ingroup library_srvsw_if
+ *
+ */
+
+#ifndef PWMHL_H_
+#define PWMHL_H_ 1
+
+#include "Cpu/Std/Ifx_Types.h"
+
+typedef struct PwmHl_s PwmHl;
+typedef void (*PwmHl_Start)(PwmHl *handle);
+typedef void (*PwmHl_Pause)(PwmHl *handle);
+typedef void (*PwmHl_Resume)(PwmHl *handle);
+typedef void (*PwmHl_Stop)(PwmHl *handle);
+
+typedef struct
+{
+ PwmHl_Start start;
+ PwmHl_Stop stop;
+} PwmHl_Functions;
+
+/** \brief Structure of the TPwm interface */
+struct PwmHl_s
+{
+ float32 t12Frequency; /**< \brief Actual timer12 frequency */
+ Ifx_TimerValue t12Period; /**< \brief Actual timer 12 period */
+ float32 t13Frequency; /**< \brief Actual timer13 frequency */
+ Ifx_TimerValue t13Period; /**< \brief Actual timer 13 period */
+#if IFX_CFG_USE_STANDARD_INTERFACE
+ PwmHl_Functions functions; /**< \brief Actual timer period */
+#endif
+};
+
+/** \brief Configuration structure of the TPwm interface */
+typedef struct
+{
+ float32 t12Frequency; /**< \brief Specify expected T12 PWM frequency in Hertz */
+ Ifx_TimerValue t12Period; /**< \brief Specify expected T12 PWM period in ticks. */
+ float32 t13Frequency; /**< \brief Specify expected T13 PWM frequency in Hertz */
+ Ifx_TimerValue t13Period; /**< \brief Specify expected T13 PWM period in ticks. */
+ Ifx_TimerValue phaseDelay; /**< \brief Specify the ticks before before updating each ouput hall pattern */
+ Ifx_TimerValue noiseFilter; /**< \brief Specify hall sensor noise filter */
+
+ Ifx_ActiveState activeState; /**< \brief Active state select for PWM output. Active high means that the PWM edge is rising at the elapsed of waitingTicks */
+} PwmHl_Config;
+
+#if IFX_CFG_USE_STANDARD_INTERFACE
+IFX_INLINE void PwmHl_start(PwmHl *handle) {handle->functions.start(handle); }
+IFX_INLINE void PwmHl_stop(PwmHl *handle) {handle->functions.stop(handle); }
+#endif
+
+#endif /* TPWM_H_ */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/If/Ccu6If/TPwm.h b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/If/Ccu6If/TPwm.h
new file mode 100644
index 0000000..4bc9c62
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/If/Ccu6If/TPwm.h
@@ -0,0 +1,94 @@
+/**
+ * \file TPwm.h
+ * \brief TPWM interface
+ *
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ * $Date: 2014-02-27 20:08:18 GMT$
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ * \defgroup library_srvsw_if_tpwm TPWM interface
+ * \ingroup library_srvsw_if
+ *
+ */
+
+#ifndef TPWM_H_
+#define TPWM_H_ 1
+
+#include "Cpu/Std/Ifx_Types.h"
+
+typedef struct TPwm_s TPwm;
+typedef void (*TPwm_Start)(TPwm *handle);
+typedef void (*TPwm_Pause)(TPwm *handle);
+typedef void (*TPwm_Resume)(TPwm *handle);
+typedef void (*TPwm_Stop)(TPwm *handle);
+
+typedef struct
+{
+ TPwm_Start start;
+ TPwm_Pause pause;
+ TPwm_Resume resume;
+ TPwm_Stop stop;
+} TPwm_Functions;
+
+/** \brief Structure of the TPwm interface */
+struct TPwm_s
+{
+ float32 frequency; /**< \brief Actual frequency */
+ Ifx_TimerValue period; /**< \brief Actual timer period */
+#if IFX_CFG_USE_STANDARD_INTERFACE
+ TPwm_Functions functions; /**< \brief Actual timer period */
+#endif
+};
+
+/** \brief Configuration structure of the TPwm interface */
+typedef struct
+{
+ float32 frequency; /**< \brief Specify expected PWM frequency in Hertz */
+ Ifx_TimerValue waitingTime; /**< \brief Specify the expected ticks before timer starts (TWAIT) */
+ Ifx_TimerValue activeCount; /**< \brief Specify active PWM period (TCOUNT) */
+ Ifx_TimerValue period; /**< \brief Specify expected PWM period in ticks. */
+ Ifx_ActiveState activeState; /**< \brief Active state select for PWM output. Active high means that the PWM edge is rising at the elapsed of waitingTicks */
+} TPwm_Config;
+
+#if IFX_CFG_USE_STANDARD_INTERFACE
+IFX_INLINE void TPwm_start(TPwm *handle) {handle->functions.start(handle); }
+IFX_INLINE void TPwm_pause(TPwm *handle) {handle->functions.pause(handle); }
+IFX_INLINE void TPwm_resume(TPwm *handle) {handle->functions.resume(handle); }
+IFX_INLINE void TPwm_stop(TPwm *handle) {handle->functions.stop(handle); }
+#endif
+
+#endif /* TPWM_H_ */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/If/Ccu6If/Timer.h b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/If/Ccu6If/Timer.h
new file mode 100644
index 0000000..1154af8
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/If/Ccu6If/Timer.h
@@ -0,0 +1,103 @@
+/**
+ * \file Timer.h
+ * \brief Timer interface
+ *
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ * $Date: 2014-02-27 20:08:19 GMT$
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ * \defgroup library_srvsw_if_timer Timer interface
+ * \ingroup library_srvsw_if
+ *
+ */
+
+#ifndef TIMER_H_
+#define TIMER_H_ 1
+
+#include "Cpu/Std/Ifx_Types.h"
+
+typedef struct Timer_s Timer;
+typedef void (*Timer_Start)(Timer *handle);
+typedef void (*Timer_Stop)(Timer *handle);
+typedef void (*Timer_SynchronousStart)(Timer *handle);
+typedef void (*Timer_SynchronousStop)(Timer *handle);
+typedef void (*Timer_CountOneStep)(Timer *handle);
+typedef void (*Timer_StartSingleShotMode)(Timer *handle);
+
+typedef struct
+{
+ Timer_Start start;
+ Timer_Stop stop;
+ Timer_SynchronousStart synchronousStart;
+ Timer_SynchronousStop synchronousStop;
+ Timer_CountOneStep countOneStep;
+ Timer_StartSingleShotMode startSingleShotMode;
+} Timer_Functions;
+
+/** \brief Structure of the Timer interface */
+struct Timer_s
+{
+ float32 t12Frequency; /**< \brief Actual timer12 frequency */
+ Ifx_TimerValue t12Period; /**< \brief Actual timer 12 period */
+ float32 t13Frequency; /**< \brief Actual timer13 frequency */
+ Ifx_TimerValue t13Period; /**< \brief Actual timer 13 period */
+#if IFX_CFG_USE_STANDARD_INTERFACE
+ Timer_Functions functions; /**< \brief timer functions */
+#endif
+};
+
+/** \brief Configuration structure of the Timer interface */
+typedef struct
+{
+ float32 t12Frequency; /**< \brief Specify expected T12 PWM frequency in Hertz */
+ Ifx_TimerValue t12Period; /**< \brief Specify expected T12 PWM period in ticks. */
+ float32 t13Frequency; /**< \brief Specify expected T13 PWM frequency in Hertz */
+ Ifx_TimerValue t13Period; /**< \brief Specify expected T13 PWM period in ticks. */
+ Ifx_TimerValue waitingTime; /**< \brief Specify the expected ticks before timer starts (TWAIT) */
+ Ifx_TimerValue activeCount; /**< \brief Specify active PWM period (TCOUNT) */
+} Timer_Config;
+
+#if IFX_CFG_USE_STANDARD_INTERFACE
+IFX_INLINE void Timer_start(Timer *handle) {handle->functions.start(handle); }
+IFX_INLINE void Timer_stop(Timer *handle) {handle->functions.stop(handle); }
+IFX_INLINE void Timer_synchronousStart(Timer *handle) {handle->functions.synchronousStart(handle); }
+IFX_INLINE void Timer_synchronousStop(Timer *handle) {handle->functions.synchronousStop(handle); }
+IFX_INLINE void Timer_countOneStep(Timer *handle) {handle->functions.countOneStep(handle); }
+IFX_INLINE void Timer_startSingleShotMode(Timer *handle) {handle->functions.startSingleShotMode(handle); }
+#endif
+
+#endif /* TIMER_H_ */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/If/SpiIf.c b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/If/SpiIf.c
new file mode 100644
index 0000000..7bf65c9
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/If/SpiIf.c
@@ -0,0 +1,81 @@
+/**
+ * \file SpiIf.c
+ * \brief SPI interface
+ *
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ * $Date: 2014-02-27 20:08:21 GMT$
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ */
+
+#include "SpiIf.h"
+
+void SpiIf_initConfig(SpiIf_Config *config)
+{
+ config->mode = SpiIf_Mode_master;
+ config->rxPriority = 0;
+ config->txPriority = 0;
+ config->erPriority = 0;
+ config->isrProvider = IfxSrc_Tos_cpu0;
+ config->bufferSize = 0;
+ config->buffer = NULL_PTR;
+ config->maximumBaudrate = 0;
+}
+
+
+void SpiIf_initChannelConfig(SpiIf_ChConfig *config, SpiIf *driver)
+{
+ config->driver = driver;
+ config->baudrate = 0;
+ config->mode.enabled = 1;
+ config->mode.autoCS = 1;
+ config->mode.loopback = 0;
+ config->mode.clockPolarity = SpiIf_ClockPolarity_idleLow;
+ config->mode.shiftClock = SpiIf_ShiftClock_shiftTransmitDataOnLeadingEdge;
+ config->mode.dataHeading = SpiIf_DataHeading_msbFirst;
+ config->mode.dataWidth = 8;
+ config->mode.csActiveLevel = Ifx_ActiveState_low;
+ config->mode.csLeadDelay = SpiIf_SlsoTiming_0;
+ config->mode.csTrailDelay = SpiIf_SlsoTiming_0;
+ config->mode.csInactiveDelay = SpiIf_SlsoTiming_0;
+ config->mode.parityCheck = 0;
+ config->mode.parityMode = Ifx_ParityMode_even;
+ config->errorChecks.baudrate = 0;
+ config->errorChecks.phase = 0;
+ config->errorChecks.receive = 0;
+ config->errorChecks.transmit = 0;
+}
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/If/SpiIf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/If/SpiIf.h
new file mode 100644
index 0000000..c0268f4
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/If/SpiIf.h
@@ -0,0 +1,291 @@
+/**
+ * \file SpiIf.h
+ * \brief SPI interface types
+ *
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ * $Date: 2014-02-27 20:08:22 GMT$
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ * \defgroup library_srvsw_if_spi SPI interface
+ * \ingroup library_srvsw_if
+ *
+ */
+
+#ifndef SPIIF_H
+#define SPIIF_H 1
+
+//________________________________________________________________________________________
+// INCLUDES
+
+#include "Src/Std/IfxSrc.h" /* FIXME interface should not have dependencies to the HAL, an If type needs to be defined */
+
+/** \addtogroup library_srvsw_if_spi
+ * \{ */
+
+//________________________________________________________________________________________
+// CONFIGURATION SWITCHES
+
+//________________________________________________________________________________________
+// HELPER MACROS
+
+//________________________________________________________________________________________
+// BASIC TYPES
+
+/** \brief SPI Interface Status */
+typedef enum
+{
+ SpiIf_Status_ok,
+ SpiIf_Status_busy,
+ SpiIf_Status_unknown
+} SpiIf_Status;
+
+/** \brief Slave select output timing */
+typedef enum
+{
+ SpiIf_SlsoTiming_0 = 0, /**< zero delay clock */
+ SpiIf_SlsoTiming_1, /**< 1 half-clock delay */
+ SpiIf_SlsoTiming_2, /**< 2 half-clock delay */
+ SpiIf_SlsoTiming_3, /**< 3 half-clock delay */
+ SpiIf_SlsoTiming_4, /**< 4 half-clock delay */
+ SpiIf_SlsoTiming_5, /**< 5 half-clock delay */
+ SpiIf_SlsoTiming_6, /**< 6 half-clock delay */
+ SpiIf_SlsoTiming_7 /**< 7 half-clock delay */
+} SpiIf_SlsoTiming;
+
+/** \brief Heading */
+typedef enum
+{
+ SpiIf_DataHeading_lsbFirst = 0, /**< LSB first */
+ SpiIf_DataHeading_msbFirst /**< MSB first */
+} SpiIf_DataHeading;
+
+/** \brief Clock phase */
+typedef enum
+{
+ SpiIf_ShiftClock_shiftTransmitDataOnLeadingEdge = 0, /**< Shift Tx data on leading edge */
+ SpiIf_ShiftClock_shiftTransmitDataOnTrailingEdge /**< Shift Tx data on training edge */
+} SpiIf_ShiftClock;
+
+/** \brief Clock polarity */
+typedef enum
+{
+ SpiIf_ClockPolarity_idleLow = 0, /**< Idle clock line is low */
+ SpiIf_ClockPolarity_idleHigh /**< Idle clock line is high */
+} SpiIf_ClockPolarity;
+
+//________________________________________________________________________________________
+// DATA STRUCTURES
+
+/** \brief Alias to the channel structure */
+typedef struct SpiIf_Ch_ SpiIf_Ch;
+typedef struct SpiIf_ChConfig_ SpiIf_ChConfig;
+typedef struct SpiIf_ SpiIf;
+
+typedef volatile struct
+{
+ uint32 onTransfer : 1; /**< \brief Channel status: On transfer */
+ uint32 byteAccess : 1; /**< \brief Channel status: 8bit / 16 bit access */
+} SpiIf_Flags;
+
+typedef struct
+{
+ void *data;
+ Ifx_SizeT remaining;
+} SpiIf_Job;
+
+/** SPI operation modes */
+typedef enum
+{ /* FIXME check conflicts with IfxQspi_Mode */
+ SpiIf_Mode_master, /**< \brief Master mode */
+ SpiIf_Mode_slave, /**< \brief Slave mode */
+ SpiIf_Mode_undefined /**< \brief Undefined mode */
+} SpiIf_Mode;
+
+typedef SpiIf_Status (*SpiIf_Exchange)(SpiIf_Ch *handle, const void *src, void *dest, Ifx_SizeT numOfData);
+typedef SpiIf_Status (*SpiIf_GetStatus)(SpiIf_Ch *handle);
+typedef void (*SpiIf_OnEvent)(SpiIf *handle);
+typedef uint32 SpiIf_SlsoTiming_HalfTsclk; /* SPI slave select output delay - in half-clock (1/(2*baudrate)) units. */
+ /* A value of 0 would set a delay of 1/Fqspi */
+
+typedef struct
+{
+ SpiIf_Exchange exchange;
+ SpiIf_GetStatus getStatus;
+ SpiIf_OnEvent onTx;
+ SpiIf_OnEvent onRx;
+ SpiIf_OnEvent onError;
+} SpiIf_funcs;
+
+struct SpiIf_
+{
+ pvoid driver; /**< \brief Spi specific driver */
+ uint32 sending; /**< \brief */
+ SpiIf_Ch *activeChannel; /**< \brief Channel actually transmitting / receiving */
+ uint32 txCount;
+ uint32 rxCount;
+ SpiIf_funcs functions;
+};
+
+typedef struct
+{
+ SpiIf_Mode mode; /**< \brief Specifies the interface operation mode */
+ Ifx_Priority rxPriority; /**< \brief Specifies the priority of the receive interrupt */
+ Ifx_Priority txPriority; /**< \brief Specifies the priority of the transmit interrupt */
+ Ifx_Priority erPriority; /**< \brief Specifies the priority of the error interrupt */
+ IfxSrc_Tos isrProvider; /**< \brief Specifies the handler of the interrupts */
+ Ifx_SizeT bufferSize; /**< \brief Specifies the number of channels that can be buffered. If 0, buffering is disabled */
+ void *buffer; /**< \brief Specifies the buffer location.The buffer parameter must point on a free memory location where the
+ * buffer object will be initialised. The Size of this area must be at least
+ * equals to "Size + sizeof(Ifx_Fifo) + 8",
+ * with "Size=config->bufferSize * Ifx_AlignOn32(sizeof(Spi_Ch*))". Not tacking
+ * this in account may result in unpredictable behaviour. */
+ float32 maximumBaudrate; /**< \brief Maximum baudrate used by the channels, this value is used to optimise the SPI internal clock */
+} SpiIf_Config;
+
+typedef struct
+{
+ uint32 baudrate : 1; /**< \brief TRUE = checked, FALSE = ignored */
+ uint32 phase : 1; /**< \brief TRUE = checked, FALSE = ignored */
+ uint32 receive : 1; /**< \brief TRUE = checked, FALSE = ignored */
+ uint32 transmit : 1; /**< \brief TRUE = checked, FALSE = ignored */
+ uint32 reserved : 28;
+} Spi_ErrorChecks;
+
+/** Channel operation mode */
+typedef struct
+{
+ uint32 enabled : 1; /**< \brief 1 = channel enabled, 0 = channel disabled */
+ uint32 autoCS : 1; /**< \brief 1 = chip select is controlled by the hardware module or, 0 = by software. */
+ uint32 loopback : 1; /**< \brief 0 = normal mode, 1 = loopback mode */
+ uint32 clockPolarity : 1; /**< \brief \ref SpiIf_ClockPolarity*/
+ uint32 shiftClock : 1; /**< \brief \ref SpiIf_ShiftClock */
+ uint32 dataHeading : 1; /**< \brief \ref SpiIf_DataHeading */
+ uint32 dataWidth : 6; /**< \brief range 2 .. 32 bits (note 2 = 2-bits, 3 = 3-bits ... */
+
+ uint32 csActiveLevel : 1; /**< \brief \ref Ifx_ActiveState */
+
+ uint32 parityCheck : 1; /**< \brief 0 = disabled, 1 = enabled */
+ uint32 parityMode : 1; /**< \brief \ref Ifx_ParityMode */
+
+ SpiIf_SlsoTiming_HalfTsclk csInactiveDelay; /**< \brief CS Inactive Delay in Tsclk/2 units */
+ SpiIf_SlsoTiming_HalfTsclk csLeadDelay; /**< \brief CS Lead Delay in Tsclk/2 units */
+ SpiIf_SlsoTiming_HalfTsclk csTrailDelay; /**< \brief CS Trail Delay in Tsclk/2 units */
+
+} SpiIf_ChMode;
+
+/** \brief SPI channel callback prototype */
+typedef void (*SpiIf_Cbk)(void *data);
+typedef void (*TxRxHandler)(SpiIf_Ch *handle);
+
+struct SpiIf_Ch_
+{
+ SpiIf *driver; /**< \brief Pointer to the SPI interface driver */
+ SpiIf_Flags flags;
+ Spi_ErrorChecks errorChecks; /**< \brief Error checks */
+ sint32 baudrate; /**< \brief Real baudrate */
+ SpiIf_Job tx;
+ SpiIf_Job rx;
+ SpiIf_Cbk onExchangeEnd; /**< \brief Specifies the callback function on end of exchange */
+ void *callbackData; /**< \brief Specifies pointer to the user specific data on transmit end */
+ TxRxHandler txHandler;
+ TxRxHandler rxHandler;
+};
+
+struct SpiIf_ChConfig_
+{
+ SpiIf *driver; /**< \brief Pointer to an implementation of SPI interface driver, e.g. \ref IfxQspi_SpiMaster_ChannelConfig */
+ float32 baudrate; /**< \brief Specifies the SPI baudrate */
+ SpiIf_ChMode mode; /**< \brief */
+ Spi_ErrorChecks errorChecks; /**< \brief */
+};
+
+//________________________________________________________________________________________
+// EXPORTED VARIABLES
+
+//________________________________________________________________________________________
+// FUNCTION PROTOTYPES
+
+IFX_INLINE void SpiIf_wait(SpiIf_Ch *handle);
+IFX_EXTERN void SpiIf_initConfig(SpiIf_Config *config);
+IFX_EXTERN void SpiIf_initChannelConfig(SpiIf_ChConfig *config, SpiIf *driver);
+
+/** \name Virtual functions
+ * These functions are implemented by a driver.
+ * \{ */
+IFX_INLINE SpiIf_Status SpiIf_exchange(SpiIf_Ch *handle, const void *src, void *dest, Ifx_SizeT numOfData);
+IFX_INLINE SpiIf_Status SpiIf_getStatus(SpiIf_Ch *handle);
+/** \} */
+
+/** \} */
+//________________________________________________________________________________________
+// INLINE FUNCTION IMPLEMENTATIONS
+
+/** Wait as long as the transmission is on-going
+ * \note This function blocks CPU for some-time */
+IFX_INLINE void SpiIf_wait(SpiIf_Ch *handle)
+{
+ while (handle->flags.onTransfer != FALSE)
+ {}
+}
+
+
+/** Perform the SPI exchange operation.
+ * \param handle Pointer to an implementation of SPI interface driver
+ * \param src Pointer to the start of data buffer for data to transmit
+ * \param dest Pointer to the start of data buffer for received data
+ * \param numOfData specifies number of byte/bit to transfer
+ * \return STATUS of SPI
+ * \note the src and dest may be the same data location.
+ */
+IFX_INLINE SpiIf_Status SpiIf_exchange(SpiIf_Ch *handle, const void *src, void *dest, Ifx_SizeT numOfData)
+{
+ return handle->driver->functions.exchange(handle, src, dest, numOfData);
+}
+
+
+/** get the SPI status
+ * * \param handle Pointer to an implementation of SPI interface driver
+ * \return STATUS of SPI
+ * */
+IFX_INLINE SpiIf_Status SpiIf_getStatus(SpiIf_Ch *handle)
+{
+ return handle->driver->functions.getStatus(handle);
+}
+
+
+//________________________________________________________________________________________
+#endif
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/If/info.dox b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/If/info.dox
new file mode 100644
index 0000000..bfc5547
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/If/info.dox
@@ -0,0 +1,6 @@
+/**
+ * \defgroup library_srvsw_if Standard interface (Obsolete)
+ * Use \ref library_srvsw_stdif instead
+ * \ingroup library_srvsw
+ *
+ */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/StdIf/IfxStdIf.h b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/StdIf/IfxStdIf.h
new file mode 100644
index 0000000..a7c3219
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/StdIf/IfxStdIf.h
@@ -0,0 +1,120 @@
+/**
+ * \file IfxStdIf.h
+ * \brief Standard interface types
+ * \ingroup IfxLld
+ *
+ * \copyright Copyright (c) 2018 Infineon Technologies AG. All rights reserved.
+ *
+ * $Date: 2014-02-27 20:08:23 GMT$
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ *
+ * \defgroup library_srvsw_stdif Standard interface
+ * \ingroup library_srvsw
+ *
+ *
+ *
+ * \par Terms
+ *
+ * Term | Description
+ * ------------------------- | -------
+ * Standard Interface | Interface defined in this document
+ * Interface Driver | Specific device driver as defined by the iLLD
+ * Standard Interface Driver | Specific interface driver which implements the Standard Interface
+ * API used at runtime | API that are used after initialization
+ * Module | Hardware functional block / IP
+ *
+ * \par Overview
+ * The Standard Interface provides generic runtime API written in C for common use case application. It abstracts the underlaying Interface Driver,
+ * i.e. the runtime API is completely device independent. It provides generic API for common use case application.
+ *
+ * Example of Standard Interface:
+ * - Serial communication interface
+ * - PWM interface
+ * - Position sensor interface
+ * - Timer interface
+ * - EEPROM interface
+ *
+ * The target is to be able to exchange the microcontroller or external connected devices on which the application is based with a minimal impact
+ * on the application code, to reduce the application software development and maintenance effort. This is archived by the Standard Interface,
+ * for which, changing the hardware only requires the update of the device configuration settings and the device initialization code. The API used
+ * at runtime, which represents the majority and the complexitity of the related code keep unchanged.
+ *
+ * Motivation: because the current software developed for the automotive applications mainly dont use C++, the Standard Interface provides a common
+ * definition for the device driver and an alternative layer for different hardware instead of using C++ interface wrapper class.
+ *
+ *
+ * The below figure shows the layers used and an example of APIs used by the application.
+ * \image html "StandardInterfaceLayers.png" "Standard interface layers"
+ * \image html "StandardInterfaceDataPipeExample.png" "Standard interface example: Serial interface as data pipe"
+ * \image html "StandardInterfaceTimerExample.png" "Standard interface example: Timer"
+ *
+ * The Standard Interface is implemented by Standard Interface wrapper by providing the function pointer to the custom functions. This gives
+ * the possibility to the programmer to use it or not. When used, it increases the code portability but slightly decreases the performance in
+ * term of run time execution and code size. When not used, the performance is not affected.
+ *
+ *
+ * \par Definition
+ * The standard interface requires the definition of at least two components: the standard interface component and the standard interface wrapper
+ * component. The standard interface component defines for each standard interface a standard interface object and a set of standard APIs used at
+ * runtime by the application. The standard interface wrapper component initializes the standard interface component by linking it to the interface
+ * driver.
+ *
+ * \attention: The application shall explicitly use the API provided by the standard interface component at runtime to access drivers parameters
+ * (setter/ getter) or action (methods). Trying to access members of the standard interface component directly though the object may not guaranty
+ * future code compatibility. The same applies to the interface driver (reminder).
+ *
+ *
+ * \par Convention
+ *
+ * The Standard interface defines the following files:
+ * Path/File | Description
+ * ----------------------------------------------- | -----------------
+ * 1_SrvSw/StdIf/IfxStdIf.h | Global standard interface definitions
+ * 1_SrvSw/StdIf/IfxStdIf_\.h | Specific standard interface definitions
+ * TCxxx/\/Ifx\_\.h/c | Specific standard interface wrapper initialization API are reconized by the name Ifx__StdIfInit()
+ * TCxxx/\/Ifx\_\.h/c | Specific standard interface wrapper function API are named according to the interface driver naming rules
+ *
+ */
+
+#ifndef IFXSTDIF_H_
+#define IFXSTDIF_H_ 1
+
+#include "Cpu/Std/Ifx_Types.h"
+
+typedef void *IfxStdIf_InterfaceDriver; /**< \brief Pointer to the specific interface driver */
+
+#endif /* IFXSTDIF_H_ */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/StdIf/IfxStdIf_DPipe.c b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/StdIf/IfxStdIf_DPipe.c
new file mode 100644
index 0000000..91f46ab
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/StdIf/IfxStdIf_DPipe.c
@@ -0,0 +1,72 @@
+/**
+ * \file IfxStdIf_DPipe.c
+ * \brief Standard interface: Data Pipe
+ * \ingroup IfxStdIf
+ *
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ * $Date: 2014-02-27 20:08:23 GMT$
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ */
+
+#include "IfxStdIf_DPipe.h"
+#include "_Utilities/Ifx_Assert.h"
+
+#include
+#include
+#include
+
+void IfxStdIf_DPipe_print(IfxStdIf_DPipe *stdIf, pchar format, ...)
+{
+ if (!stdIf->txDisabled)
+ {
+ char message[STDIF_DPIPE_MAX_PRINT_SIZE + 1];
+ Ifx_SizeT count;
+ va_list args;
+ va_start(args, format);
+ vsprintf((char *)message, format, args);
+ va_end(args);
+ count = (Ifx_SizeT)strlen(message);
+ IFX_ASSERT(IFX_VERBOSE_LEVEL_ERROR, count < STDIF_DPIPE_MAX_PRINT_SIZE);
+ //return
+ IfxStdIf_DPipe_write(stdIf, (void *)message, &count, TIME_INFINITE);
+ }
+ else
+ {
+ //return TRUE;
+ }
+}
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/StdIf/IfxStdIf_DPipe.h b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/StdIf/IfxStdIf_DPipe.h
new file mode 100644
index 0000000..222cb5f
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/StdIf/IfxStdIf_DPipe.h
@@ -0,0 +1,401 @@
+/**
+ * \file IfxStdIf_DPipe.h
+ * \brief Standard interface: Data Pipe
+ * \ingroup IfxStdIf
+ *
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ * $Date: 2014-02-27 20:08:24 GMT$
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ *
+ * \defgroup library_srvsw_stdif_dpipe Standard interface: Data Pipe
+ * \ingroup library_srvsw_stdif
+ *
+ * The standard interafce data pipe (DPipe) abstract the hardware used for data transfer. It provide, after proper initialization an hardware independant way to write
+ * and read data to/from as communciation channel.
+ *
+ * \par Porting StandardIo to DPipe
+ * replace all
+ * - StandardIo type with IfxStdIf_DPipe
+ * - StandardIo_print with IfxStdIf_DPipe_print
+ * delete StandardIo.c and StandardIo.h
+ * Include "StdIf/IfxStdIf_DPipe.h" instead of "SysSe/Bsp/StandardIo.h"
+ *
+ * The following files are already ported: Ifx_Console, Ifx_Shell
+ *
+ */
+#ifndef STDIF_DPIPE_H_
+#define STDIF_DPIPE_H_ 1
+
+#include "IfxStdIf.h"
+//----------------------------------------------------------------------------------------
+#ifndef ENDL
+# define ENDL "\r\n"
+#endif
+
+/** \brief Forward declaration */
+typedef struct IfxStdIf_DPipe_ IfxStdIf_DPipe;
+
+typedef volatile boolean *IfxStdIf_DPipe_WriteEvent;
+typedef volatile boolean *IfxStdIf_DPipe_ReadEvent;
+
+/** \brief Size of the buffer allocated on the stack for the print function */
+#define STDIF_DPIPE_MAX_PRINT_SIZE (255)
+
+/** \brief Write binary data into the \ref IfxStdIf_DPipe.
+ *
+ * Initially the parameter 'count' specifies count of data to write.
+ * After execution the data pointed by 'count' specifies the data actually written
+ *
+ * \param stdif Pointer to the interface driver object
+ * \param data Pointer to the start of data
+ * \param count Pointer to the count of data (in bytes).
+ * \param timeout in system timer ticks
+ *
+ * \retval TRUE Returns TRUE if all items could be written
+ * \retval FALSE Returns FALSE if not all the items could be written
+ */
+typedef boolean (*IfxStdIf_DPipe_Write)(IfxStdIf_InterfaceDriver stdIf, void *data, Ifx_SizeT *count, Ifx_TickTime timeout);
+
+/** \brief Read data from the \ref IfxStdIf_DPipe object
+ *
+ * Initially the parameter 'count' specifies count of data to read.
+ * After execution the data pointed by 'count' specifies the data actually read.
+ *
+ * \param stdif Pointer to the interface driver object
+ * \param data Pointer to the start of data
+ * \param count Pointer to the count of data (in bytes).
+ * \param timeout in system timer ticks
+ *
+ * \retval TRUE Returns TRUE if all items could be read
+ * \retval FALSE Returns FALSE if not all the items could be read
+ */
+typedef boolean (*IfxStdIf_DPipe_Read)(IfxStdIf_InterfaceDriver stdIf, void *data, Ifx_SizeT *count, Ifx_TickTime timeout);
+
+/** \brief Returns the number of bytes in the rx buffer
+ *
+ * \param stdif Pointer to the interface driver object
+ *
+ * \return Returns the number of bytes in the rx buffer
+ */
+typedef sint32 (*IfxStdIf_DPipe_GetReadCount)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Returns read event object
+ *
+ * \param stdif Pointer to the interface driver object
+ *
+ * \return Returns read event object
+ */
+typedef IfxStdIf_DPipe_ReadEvent (*IfxStdIf_DPipe_GetReadEvent)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Returns number of bytes send
+ *
+ * \param stdif Pointer to the interface driver object
+ *
+ * \return Returns number of bytes send
+ */
+typedef uint32 (*IfxStdIf_DPipe_GetSendCount)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Returns the time stamp of the last transmit data
+ *
+ * \param stdif Pointer to the interface driver object
+ *
+ * \return Returns the time stamp of the last transmit data
+ */
+typedef Ifx_TickTime (*IfxStdIf_DPipe_GetTxTimeStamp)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Returns the number of free bytes (free space) in the tx buffer
+ *
+ * \param stdif Pointer to the interface driver object
+ *
+ * \return Returns the number of free bytes in the tx buffer
+ */
+typedef sint32 (*IfxStdIf_DPipe_GetWriteCount)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Returns write event object
+ *
+ * \param stdif Pointer to the interface driver object
+ *
+ * \return Returns write event object
+ */
+typedef IfxStdIf_DPipe_WriteEvent (*IfxStdIf_DPipe_GetWriteEvent)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Indicates if the required number of bytes are available for read in the buffer
+ *
+ * \param stdif Pointer to the interface driver object
+ * \param count Pointer to the count of data (in bytes).
+ * \param timeout in system timer ticks
+ *
+ * \return Returns TRUE if at least count bytes are available for read in the rx buffer,
+ * if not the Event is armed to be set when the buffer count is bigger or equal to the requested count
+ */
+typedef boolean (*IfxStdIf_DPipe_CanReadCount)(IfxStdIf_InterfaceDriver stdIf, Ifx_SizeT count, Ifx_TickTime timeout);
+
+/** \brief Indicates if there is enough free space to write the data in the buffer
+ *
+ * \param stdif Pointer to the interface driver object
+ * \param count Pointer to the count of data (in bytes).
+ * \param timeout in system timer ticks
+ *
+ * \return Returns TRUE if at least count bytes can be written to the tx buffer,
+ * if not the Event is armed to be set when the buffer free count is bigger or equal to the requested count
+ */
+typedef boolean (*IfxStdIf_DPipe_CanWriteCount)(IfxStdIf_InterfaceDriver stdIf, Ifx_SizeT count, Ifx_TickTime timeout);
+
+/** \brief Flush the transmit buffer by transmitting all data
+ *
+ * \param stdif Pointer to the interface driver object
+ * \param timeout timeout for the flush operation
+ *
+ * \return Returns TRUE if the FIFO is empty
+ */
+typedef boolean (*IfxStdIf_DPipe_FlushTx)(IfxStdIf_InterfaceDriver stdIf, Ifx_TickTime timeout);
+
+/** \brief Clears the RX buffer by removing all data
+ *
+ * \param stdif Pointer to the interface driver object
+ * \return void
+ */
+typedef void (*IfxStdIf_DPipe_ClearRx)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Clears the TX buffer by removing all data
+ *
+ * \param stdif Pointer to the interface driver object
+ * \return void
+ */
+typedef void (*IfxStdIf_DPipe_ClearTx)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief handler called on reveive event
+ *
+ * \param stdif Pointer to the interface driver object
+ *
+ * \return none
+ */
+typedef void (*IfxStdIf_DPipe_OnReceive)(IfxStdIf_InterfaceDriver stdIf);
+/** \brief handler called on transmit event
+ *
+ * \param stdif Pointer to the interface driver object
+ *
+ * \return none
+ */
+typedef void (*IfxStdIf_DPipe_OnTransmit)(IfxStdIf_InterfaceDriver stdIf);
+/** \brief handler called on error event
+ *
+ * \param stdif Pointer to the interface driver object
+ *
+ * \return none
+ */
+typedef void (*IfxStdIf_DPipe_OnError)(IfxStdIf_InterfaceDriver stdIf);
+/** \brief Reset the sendCount counter
+ *
+ * \param stdif Pointer to the interface driver object
+ *
+ * \return none
+ */
+typedef void (*IfxStdIf_DPipe_ResetSendCount)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Standard interface object
+ */
+struct IfxStdIf_DPipe_
+{
+ IfxStdIf_InterfaceDriver driver; /**< \brief Pointer to the specific driver object */
+ boolean txDisabled; /**< \brief If disabled is set to TRUE, the output is disabled, else enabled */
+
+ /* Standard interface APIs */
+ IfxStdIf_DPipe_Write write; /**< \brief \see IfxStdIf_DPipe_Write */
+ IfxStdIf_DPipe_Read read; /**< \brief \see IfxStdIf_DPipe_Read */
+ IfxStdIf_DPipe_GetReadCount getReadCount; /**< \brief \see IfxStdIf_DPipe_GetReadCount */
+ IfxStdIf_DPipe_GetReadEvent getReadEvent; /**< \brief \see IfxStdIf_DPipe_GetReadEvent */
+ IfxStdIf_DPipe_GetWriteCount getWriteCount; /**< \brief \see IfxStdIf_DPipe_GetWriteCount */
+ IfxStdIf_DPipe_GetWriteEvent getWriteEvent; /**< \brief \see IfxStdIf_DPipe_GetWriteEvent */
+ IfxStdIf_DPipe_CanReadCount canReadCount; /**< \brief \see IfxStdIf_DPipe_CanReadCount */
+ IfxStdIf_DPipe_CanWriteCount canWriteCount; /**< \brief \see IfxStdIf_DPipe_CanWriteCount */
+ IfxStdIf_DPipe_FlushTx flushTx; /**< \brief \see IfxStdIf_DPipe_FlushTx */
+ IfxStdIf_DPipe_ClearTx clearTx; /**< \brief \see IfxStdIf_DPipe_ClearTx */
+ IfxStdIf_DPipe_ClearRx clearRx; /**< \brief \see IfxStdIf_DPipe_ClearRx */
+ IfxStdIf_DPipe_OnReceive onReceive; /**< \brief \see IfxStdIf_DPipe_OnReceive */
+ IfxStdIf_DPipe_OnTransmit onTransmit; /**< \brief \see IfxStdIf_DPipe_OnTransmit */
+ IfxStdIf_DPipe_OnError onError; /**< \brief \see IfxStdIf_DPipe_OnError */
+
+ IfxStdIf_DPipe_GetSendCount getSendCount; /**< \brief \see IfxStdIf_DPipe_GetSendCount */
+ IfxStdIf_DPipe_GetTxTimeStamp getTxTimeStamp; /**< \brief \see IfxStdIf_DPipe_GetTxTimeStamp */
+ IfxStdIf_DPipe_ResetSendCount resetSendCount; /**< \brief \see IfxStdIf_DPipe_ResetSendCount */
+};
+/** \addtogroup library_srvsw_stdif_dpipe
+ * \{ */
+/** \copydoc IfxStdIf_DPipe_Write
+ */
+IFX_INLINE boolean IfxStdIf_DPipe_write(IfxStdIf_DPipe *stdIf, void *data, Ifx_SizeT *count, Ifx_TickTime timeout)
+{
+ return stdIf->write(stdIf->driver, data, count, timeout);
+}
+
+
+/** \copydoc IfxStdIf_DPipe_Read
+ */
+IFX_INLINE boolean IfxStdIf_DPipe_read(IfxStdIf_DPipe *stdIf, void *data, Ifx_SizeT *count, Ifx_TickTime timeout)
+{
+ return stdIf->read(stdIf->driver, data, count, timeout);
+}
+
+
+/** \copydoc IfxStdIf_DPipe_GetReadCount
+ */
+IFX_INLINE sint32 IfxStdIf_DPipe_getReadCount(IfxStdIf_DPipe *stdIf)
+{
+ return stdIf->getReadCount(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_DPipe_GetWriteCount
+ */
+IFX_INLINE sint32 IfxStdIf_DPipe_getWriteCount(IfxStdIf_DPipe *stdIf)
+{
+ return stdIf->getWriteCount(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_DPipe_CanReadCount
+ */
+IFX_INLINE boolean IfxStdIf_DPipe_canReadCount(IfxStdIf_DPipe *stdIf, Ifx_SizeT count, Ifx_TickTime timeout)
+{
+ return stdIf->canReadCount(stdIf->driver, count, timeout);
+}
+
+
+/** \copydoc IfxStdIf_DPipe_CanWriteCount
+ */
+IFX_INLINE boolean IfxStdIf_DPipe_canWriteCount(IfxStdIf_DPipe *stdIf, Ifx_SizeT count, Ifx_TickTime timeout)
+{
+ return stdIf->canWriteCount(stdIf->driver, count, timeout);
+}
+
+
+/** \copydoc IfxStdIf_DPipe_GetReadEvent
+ */
+IFX_INLINE IfxStdIf_DPipe_ReadEvent IfxStdIf_DPipe_getReadEvent(IfxStdIf_DPipe *stdIf)
+{
+ return stdIf->getReadEvent(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_DPipe_GetWriteEvent
+ */
+IFX_INLINE IfxStdIf_DPipe_WriteEvent IfxStdIf_DPipe_getWriteEvent(IfxStdIf_DPipe *stdIf)
+{
+ return stdIf->getWriteEvent(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_DPipe_FlushTx
+ */
+IFX_INLINE boolean IfxStdIf_DPipe_flushTx(IfxStdIf_DPipe *stdIf, Ifx_TickTime timeout)
+{
+ return stdIf->flushTx(stdIf->driver, timeout);
+}
+
+
+/** \copydoc IfxStdIf_DPipe_ClearTx
+ */
+IFX_INLINE void IfxStdIf_DPipe_clearTx(IfxStdIf_DPipe *stdIf)
+{
+ stdIf->clearTx(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_DPipe_ClearRx
+ */
+IFX_INLINE void IfxStdIf_DPipe_clearRx(IfxStdIf_DPipe *stdIf)
+{
+ stdIf->clearRx(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_DPipe_OnReceive
+ */
+IFX_INLINE void IfxStdIf_DPipe_onReceive(IfxStdIf_DPipe *stdIf)
+{
+ stdIf->onReceive(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_DPipe_OnTransmit
+ */
+IFX_INLINE void IfxStdIf_DPipe_onTransmit(IfxStdIf_DPipe *stdIf)
+{
+ stdIf->onTransmit(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_DPipe_OnError
+ */
+IFX_INLINE void IfxStdIf_DPipe_onError(IfxStdIf_DPipe *stdIf)
+{
+ stdIf->onError(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_DPipe_GetSendCount
+ */
+IFX_INLINE uint32 IfxStdIf_DPipe_getSendCount(IfxStdIf_DPipe *stdIf)
+{
+ return stdIf->getSendCount(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_DPipe_GetTxTimeStamp
+ */
+IFX_INLINE Ifx_TickTime IfxStdIf_DPipe_getTxTimeStamp(IfxStdIf_DPipe *stdIf)
+{
+ return stdIf->getTxTimeStamp(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_DPipe_ResetSendCount
+ */
+IFX_INLINE void IfxStdIf_DPipe_resetSendCount(IfxStdIf_DPipe *stdIf)
+{
+ stdIf->resetSendCount(stdIf->driver);
+}
+
+
+IFX_EXTERN void IfxStdIf_DPipe_print(IfxStdIf_DPipe *stdIf, pchar format, ...);
+
+/** \} */
+//----------------------------------------------------------------------------------------
+
+#endif /* STDIF_DPIPE_H_ */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/StdIf/IfxStdIf_Pos.c b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/StdIf/IfxStdIf_Pos.c
new file mode 100644
index 0000000..b47d77c
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/StdIf/IfxStdIf_Pos.c
@@ -0,0 +1,97 @@
+/**
+ * \file IfxStdIf_Pos.c
+ * \brief Standard interface: Position interface
+ * \ingroup IfxStdIf
+ *
+ * \version disabled
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ */
+
+#include "IfxStdIf_Pos.h"
+
+void IfxStdIf_Pos_initConfig (IfxStdIf_Pos_Config * config)
+{
+ config->offset = 0;
+ config->reversed = FALSE;
+ config->resolution = 0;
+ config->periodPerRotation = 1;
+ config->resolutionFactor = IfxStdIf_Pos_ResolutionFactor_oneFold;
+ config->updatePeriod = 0.001;
+ config->speedModeThreshold = 0;
+ config->minSpeed = 0; // 0 rpm
+ config->maxSpeed = 20000.0 / 60.0 * (2 * IFX_PI); // 20000 rpm
+ config->speedFilterEnabled = FALSE;
+ config->speedFilerCutOffFrequency = 0;
+
+}
+
+void IfxStdIf_Pos_printStatus(IfxStdIf_Pos *driver, IfxStdIf_DPipe *io)
+{
+ IfxStdIf_Pos_Status status;
+ status = IfxStdIf_Pos_getFault(driver);
+
+ IfxStdIf_DPipe_print(io, "DSADC RDC status:"ENDL);
+ if (status.status != 0)
+ {
+ if (status.B.commError)
+ {
+ IfxStdIf_DPipe_print(io, "- Communication error"ENDL);
+ }
+ if (status.B.notSynchronised)
+ {
+ IfxStdIf_DPipe_print(io, "- Synchronization error"ENDL);
+ }
+ if (status.B.signalDegradation)
+ {
+ IfxStdIf_DPipe_print(io, "- Signal degradation error"ENDL);
+ }
+ if (status.B.signalLoss)
+ {
+ IfxStdIf_DPipe_print(io, "- Signal loss error"ENDL);
+ }
+ if (status.B.trackingLoss)
+ {
+ IfxStdIf_DPipe_print(io, "- Tracking error"ENDL);
+ }
+ }
+ else
+ {
+ IfxStdIf_DPipe_print(io, "- Ready"ENDL);
+ }
+}
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/StdIf/IfxStdIf_Pos.h b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/StdIf/IfxStdIf_Pos.h
new file mode 100644
index 0000000..ead46d3
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/StdIf/IfxStdIf_Pos.h
@@ -0,0 +1,583 @@
+/**
+ * \file IfxStdIf_Pos.h
+ * \brief Standard interface: Position interface
+ * \ingroup IfxStdIf
+ *
+ * \version disabled
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ *
+ * \defgroup library_srvsw_stdif_posif Standard interface: Position interface
+ * \ingroup library_srvsw_stdif
+ *
+ * The standard interface position interface (IfxStdIf_Pos) abstract the hardware used for position interface feature like encoder, hall, resolver, ... It provide, after proper initialization an hardware
+ * Independent way to interact with the position sensor like getting position, speed, direction, ...
+ *
+ * The figure below shows the standard position interface.
+ *
+ * \image html "stdif_PosIf.png" "Standard position interface"
+ *
+ * This interface defines the following features:
+ * -
+ *
+ *
+ */
+
+#ifndef IFXSTDIF_POSIF_H
+#define IFXSTDIF_POSIF_H 1
+
+#include "Cpu/Std/Ifx_Types.h"
+#include "IfxStdIf.h"
+#include "IfxStdIf_DPipe.h"
+
+/** \brief Output event enable / disable */
+typedef enum
+{
+ IfxStdIf_Pos_MotionType_rotating, /**< \brief Rotating sensor */
+ IfxStdIf_Pos_MotionType_linear /**< \brief Linear sensor */
+} IfxStdIf_Pos_MotionType;
+
+/** \brief Output event enable / disable */
+typedef enum
+{
+ IfxStdIf_Pos_ResolutionFactor_oneFold = 1, /**< \brief Default, no multipluication factor */
+ IfxStdIf_Pos_ResolutionFactor_twoFold = 2, /**< \brief 2-fold resolution. Valid for encoder */
+ IfxStdIf_Pos_ResolutionFactor_fourFold = 4 /**< \brief 4-fold resolution. Valid for encoder */
+} IfxStdIf_Pos_ResolutionFactor;
+
+/** \brief Position sensor Types */
+typedef enum
+{
+ IfxStdIf_Pos_SensorType_encoder,
+ IfxStdIf_Pos_SensorType_hall,
+ IfxStdIf_Pos_SensorType_resolver,
+ IfxStdIf_Pos_SensorType_angletrk,
+ IfxStdIf_Pos_SensorType_igmr,
+ IfxStdIf_Pos_SensorType_virtual
+} IfxStdIf_Pos_SensorType;
+
+/** \brief Position sensor direction definition */
+typedef enum
+{
+ IfxStdIf_Pos_Dir_forward, /**< \brief Forward direction. For rotating position sensor, forward is clockwise rotation */
+ IfxStdIf_Pos_Dir_backward, /**< \brief Backward direction. For rotating position sensor, fackward is counter-clockwise rotation */
+ IfxStdIf_Pos_Dir_unknown /**< \brief Unknown direction */
+} IfxStdIf_Pos_Dir;
+
+/** \brief Position sensor status definition */
+typedef union
+{
+ uint32 status; /**< \brief Global status access */
+ struct
+ {
+ uint32 notSynchronised : 1; /**< \brief Sensor is not synchronized */
+ uint32 signalLoss : 1; /**< \brief Loss of signal error */
+ uint32 signalDegradation : 1; /**< \brief Signal degradation warning */
+ uint32 trackingLoss : 1; /**< \brief Tracking loss error */
+ uint32 commError : 1; /**< \brief Communication error*/
+ } B; /**< \brief Bitfielf status access */
+} IfxStdIf_Pos_Status;
+
+typedef sint32 IfxStdIf_Pos_RawAngle;
+
+/** \brief Forward declaration */
+typedef struct IfxStdIf_Pos_ IfxStdIf_Pos;
+
+/** \brief Return the position, inclusive turns
+ *
+ * Return the sensor position in rad for rotating sensor inclusive turns, or in m for linear sensors.
+ * For linear sensor the effect is the same as IfxStdIf_Pos_GetPosition.
+ *
+ * \param stdIf Pointer to the interface driver object
+ * \return Return the position inclusive turns in rad
+ */
+typedef float32 (*IfxStdIf_Pos_GetAbsolutePosition)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Handles the zero interrupt
+ * \param stdIf Pointer to the interface driver object
+ * \return none
+ */
+typedef void (*IfxStdIf_Pos_OnZeroIrq)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Return the raw position sensor offset
+ *
+ * \param stdIf Pointer to the interface driver object
+ * \return Return the raw position sensor offset sensor in ticks
+ */
+typedef sint32 (*IfxStdIf_Pos_GetOffset)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Return the position
+ *
+ * Return the sensor position in rad for rotating sensor or in m for linear sensors.
+ * For rotating sensor, the position is always between 0 and 2*IFX_PI.
+ *
+ * \param stdIf Pointer to the interface driver object
+ * \return Return the position in rad or m
+ */
+typedef float32 (*IfxStdIf_Pos_GetPosition)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Return the direction
+ *
+ * Return the sensor direction.
+ *
+ * \param stdIf Pointer to the interface driver object
+ * \return Return the direction
+ */
+typedef IfxStdIf_Pos_Dir (*IfxStdIf_Pos_GetDirection)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Return the sensor status
+ *
+ * \param stdIf Pointer to the interface driver object
+ * \return Return the sensor status
+ */
+typedef IfxStdIf_Pos_Status (*IfxStdIf_Pos_GetFault)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Return the period per rotation setting
+ *
+ * \param stdIf Pointer to the interface driver object
+ * \return Return the period per rotation setting
+ */
+typedef uint16 (*IfxStdIf_Pos_GetPeriodPerRotation)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Return the raw position in ticks
+ *
+ * Return the sensor raw position in ticks.
+ *
+ * \param stdIf Pointer to the interface driver object
+ * \return Return the raw position in ticks
+ */
+typedef sint32 (*IfxStdIf_Pos_GetRawPosition)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Get the update period
+ * \param stdIf Pointer to the interface driver object
+ * \return Return the update period in s
+ */
+typedef float32 (*IfxStdIf_Pos_GetRefreshPeriod)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Get the resolution
+ * \param stdIf Pointer to the interface driver object
+ * \return Return the resolution
+ */
+typedef sint32 (*IfxStdIf_Pos_GetResolution)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Get the sensor type
+ * \param stdIf Pointer to the interface driver object
+ * \return Return the sensor type
+ */
+typedef IfxStdIf_Pos_SensorType (*IfxStdIf_Pos_GetSensorType)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Return the speed
+ * \param stdIf Pointer to the interface driver object
+ * \return Return the speed in rad/s or m/s
+ */
+typedef float32 (*IfxStdIf_Pos_GetSpeed)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Return position in turn
+ * \param stdIf Pointer to the interface driver object
+ * \return Return position in turn
+ */
+typedef sint32 (*IfxStdIf_Pos_GetTurn)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Handles the A sensor event
+ * Event A is a sensor defined event. it is optional.
+ * \param stdIf Pointer to the interface driver object
+ * \return none
+ */
+typedef void (*IfxStdIf_Pos_OnEventA)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Refresh the status
+ *
+ * Update the stdIf state like speed, position, status, taking into account the updatePeriod
+ *
+ * \param stdIf Pointer to the interface driver object
+ * \return None
+ */
+typedef void (*IfxStdIf_Pos_Update)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Reset the driver
+ *
+ * Clear faults, reset speed and position to 0
+ *
+ * \param stdIf Pointer to the interface driver object
+ * \return None
+ */
+typedef void (*IfxStdIf_Pos_Reset)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Reset the driver fault
+ *
+ * Clear faults
+ *
+ * \param stdIf Pointer to the interface driver object
+ * \return None
+ */
+typedef void (*IfxStdIf_Pos_ResetFaults)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Set the sensor offset
+ * \param stdIf Pointer to the interface driver object
+ * \param offset Offset in sensor ticks
+ * \return None
+ */
+typedef void (*IfxStdIf_Pos_SetOffset)(IfxStdIf_InterfaceDriver stdIf, sint32 offset);
+
+/** \brief Set the sensor position (virtual sensor)
+ * \param stdIf Pointer to the interface driver object
+ * \param position Position sensor rad
+ * \return None
+ */
+typedef void (*IfxStdIf_Pos_SetPosition)(IfxStdIf_InterfaceDriver stdIf, float32 position);
+/** \brief Set the sensor position (virtual sensor)
+ * \param stdIf Pointer to the interface driver object
+ * \param position Position sensor ticks
+ * \return None
+ */
+typedef void (*IfxStdIf_Pos_SetRawPosition)(IfxStdIf_InterfaceDriver stdIf, sint32 position);
+
+/** \brief Set the sensor speed (virtual sensor)
+ * \param stdIf Pointer to the interface driver object
+ * \param speed speed in rad/s
+ * \return None
+ */
+typedef void (*IfxStdIf_Pos_SetSpeed)(IfxStdIf_InterfaceDriver stdIf, float32 speed);
+
+/** \brief Set the update period
+ * \param stdIf Pointer to the interface driver object
+ * \param updatePeriod Refresh period in s
+ * \return None
+ */
+typedef void (*IfxStdIf_Pos_SetRefreshPeriod)(IfxStdIf_InterfaceDriver stdIf, float32 updatePeriod);
+
+/** \brief Standard interface object
+ */
+struct IfxStdIf_Pos_
+{
+ IfxStdIf_InterfaceDriver driver; /**< \brief Interface driver object */
+ IfxStdIf_Pos_OnZeroIrq onZeroIrq; /**< \brief \see IfxStdIf_Pos_OnZeroIrq */
+ IfxStdIf_Pos_GetAbsolutePosition getAbsolutePosition; /**< \brief Return the absolute position */
+ IfxStdIf_Pos_GetOffset getOffset; /**< \brief \see IfxStdIf_Pos_GetOffset */
+ IfxStdIf_Pos_GetPosition getPosition; /**< \brief \see IfxStdIf_Pos_GetPosition */
+ IfxStdIf_Pos_GetDirection getDirection; /**< \brief \see IfxStdIf_Pos_GetDirection */
+ IfxStdIf_Pos_GetFault getFault; /**< \brief \see IfxStdIf_Pos_GetFault */
+ IfxStdIf_Pos_GetRawPosition getRawPosition; /**< \brief \see IfxStdIf_Pos_GetRawPosition */
+ IfxStdIf_Pos_GetPeriodPerRotation getPeriodPerRotation; /**< \brief \see IfxStdIf_Pos_GetPeriodPerRotation */
+ IfxStdIf_Pos_GetRefreshPeriod getRefreshPeriod; /**< \brief \see IfxStdIf_Pos_GetRefreshPeriod */
+ IfxStdIf_Pos_GetResolution getResolution; /**< \brief \see IfxStdIf_Pos_GetResolution */
+ IfxStdIf_Pos_GetSensorType getSensorType; /**< \brief \see IfxStdIf_Pos_GetSensorType */
+ IfxStdIf_Pos_GetTurn getTurn; /**< \brief \see IfxStdIf_Pos_GetTurn */
+ IfxStdIf_Pos_OnEventA onEventA; /**< \brief \see IfxStdIf_Pos_OnEventA */
+ IfxStdIf_Pos_Reset reset; /**< \brief \see IfxStdIf_Pos_Reset */
+ IfxStdIf_Pos_ResetFaults resetFaults; /**< \brief \see IfxStdIf_Pos_ResetFaults */
+ IfxStdIf_Pos_GetSpeed getSpeed; /**< \brief \see IfxStdIf_Pos_GetSpeed */
+ IfxStdIf_Pos_Update update; /**< \brief \see IfxStdIf_Pos_Update */
+ IfxStdIf_Pos_SetOffset setOffset; /**< \brief \see IfxStdIf_Pos_SetOffset */
+ IfxStdIf_Pos_SetPosition setPosition; /**< \brief \see IfxStdIf_Pos_SetPosition */
+ IfxStdIf_Pos_SetRawPosition setRawPosition; /**< \brief \see IfxStdIf_Pos_SetRawPosition */
+ IfxStdIf_Pos_SetSpeed setSpeed; /**< \brief \see IfxStdIf_Pos_SetSpeed */
+ IfxStdIf_Pos_SetRefreshPeriod setRefreshPeriod; /**< \brief \see IfxStdIf_Pos_SetRefreshPeriod */
+};
+
+/** \brief Position interface configuration */
+typedef struct
+{
+ sint32 offset; /**< \brief Position sensor offset */
+ boolean reversed; /**< \brief If true, the sensor direction is reversed */
+ sint32 resolution; /**< \brief Sensor resolution. For encoder with 1024 pulse per revolution, the value should be 1024 */
+ uint16 periodPerRotation; /**< \brief Number of period per rotation. Is usually 1 for encoder */
+ IfxStdIf_Pos_ResolutionFactor resolutionFactor; /**< \brief Resolution multiplier for encoder interface, valid is 2, 4. */
+ float32 updatePeriod; /**< \brief period in seconds, at which the application calls IfxStdIf_Pos_update() */
+ float32 speedModeThreshold; /**< \brief Speed threshold used for the speed calculation mode. For encoder, above the threshold the pulse count mode is used, below the threshold, the time delta is used */
+ float32 minSpeed; /**< \brief Absolute minimal allowed speed. below speed is recognized as 0rad/s */
+ float32 maxSpeed; /**< \brief Absolute maximal allowed speed. Above speed is recognized as error */
+ boolean speedFilterEnabled; /**< \brief Enable / disable the speed low pass filter */
+ float32 speedFilerCutOffFrequency; /**< \brief Speed low pass filter cut off frequency */
+} IfxStdIf_Pos_Config;
+
+/** \addtogroup library_srvsw_stdif_posif
+ * \{
+ */
+
+/** \copydoc IfxStdIf_Pos_OnZeroIrq
+ */
+IFX_INLINE void IfxStdIf_Pos_onZeroIrq(IfxStdIf_Pos *stdIf)
+{
+ stdIf->onZeroIrq(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_Pos_GetAbsolutePosition
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE float32 IfxStdIf_Pos_getAbsolutePosition(IfxStdIf_Pos *stdIf)
+{
+ return stdIf->getAbsolutePosition(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_Pos_GetFault MCMETILLD-521
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE IfxStdIf_Pos_Status IfxStdIf_Pos_getFault(IfxStdIf_Pos *stdIf)
+{
+ return stdIf->getFault(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_Pos_GetOffset
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE sint32 IfxStdIf_Pos_getOffset(IfxStdIf_Pos *stdIf)
+{
+ return stdIf->getOffset(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_Pos_GetPosition
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE float32 IfxStdIf_Pos_getPosition(IfxStdIf_Pos *stdIf)
+{
+ return stdIf->getPosition(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_Pos_GetDirection
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE IfxStdIf_Pos_Dir IfxStdIf_Pos_getDirection(IfxStdIf_Pos *stdIf)
+{
+ return stdIf->getDirection(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_Pos_GetPeriodPerRotation
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE uint16 IfxStdIf_Pos_getPeriodPerRotation(IfxStdIf_Pos *stdIf)
+{
+ return stdIf->getPeriodPerRotation(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_Pos_GetRawPosition
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE sint32 IfxStdIf_Pos_getRawPosition(IfxStdIf_Pos *stdIf)
+{
+ return stdIf->getRawPosition(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_Pos_GetRefreshPeriod
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE float32 IfxStdIf_Pos_getRefreshPeriod(IfxStdIf_Pos *stdIf)
+{
+ return stdIf->getRefreshPeriod(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_Pos_GetResolution
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE sint32 IfxStdIf_Pos_getResolution(IfxStdIf_Pos *stdIf)
+{
+ return stdIf->getResolution(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_Pos_GetTurn
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE sint32 IfxStdIf_Pos_getTurn(IfxStdIf_Pos *stdIf)
+{
+ return stdIf->getTurn(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_Pos_GetSensorType
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE IfxStdIf_Pos_SensorType IfxStdIf_Pos_getSensorType(IfxStdIf_Pos *stdIf)
+{
+ return stdIf->getSensorType(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_Pos_GetSpeed
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE float32 IfxStdIf_Pos_getSpeed(IfxStdIf_Pos *stdIf)
+{
+ return stdIf->getSpeed(stdIf->driver);
+}
+
+
+/** Check whether the sensor is faulty
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE boolean IfxStdIf_Pos_isFault(IfxStdIf_Pos *stdIf)
+{
+ return IfxStdIf_Pos_getFault(stdIf).status != 0;
+}
+
+
+/** \copydoc IfxStdIf_Pos_OnEventA
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE void IfxStdIf_Pos_onEventA(IfxStdIf_Pos *stdIf)
+{
+ stdIf->onEventA(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_Pos_Update
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE void IfxStdIf_Pos_update(IfxStdIf_Pos *stdIf)
+{
+ stdIf->update(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_Pos_Reset
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE void IfxStdIf_Pos_reset(IfxStdIf_Pos *stdIf)
+{
+ stdIf->reset(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_Pos_ResetFaults
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE void IfxStdIf_Pos_resetFaults(IfxStdIf_Pos *stdIf)
+{
+ stdIf->resetFaults(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_Pos_SetOffset
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE void IfxStdIf_Pos_setOffset(IfxStdIf_Pos *stdIf, sint32 offset)
+{
+ stdIf->setOffset(stdIf->driver, offset);
+}
+
+
+/** \copydoc IfxStdIf_Pos_SetPosition
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE void IfxStdIf_Pos_setPosition(IfxStdIf_Pos *stdIf, float32 position)
+{
+ stdIf->setPosition(stdIf->driver, position);
+}
+
+
+/** \copydoc IfxStdIf_Pos_SetRawPosition
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE void IfxStdIf_Pos_setRawPosition(IfxStdIf_Pos *stdIf, sint32 position)
+{
+ stdIf->setRawPosition(stdIf->driver, position);
+}
+
+
+/** \copydoc IfxStdIf_Pos_SetSpeed
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE void IfxStdIf_Pos_setSpeed(IfxStdIf_Pos *stdIf, float32 speed)
+{
+ stdIf->setSpeed(stdIf->driver, speed);
+}
+
+
+/** \copydoc IfxStdIf_Pos_SetRefreshPeriod
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE void IfxStdIf_Pos_setRefreshPeriod(IfxStdIf_Pos *stdIf, float32 updatePeriod)
+{
+ stdIf->setRefreshPeriod(stdIf->driver, updatePeriod);
+}
+
+
+/** \} */
+
+/** \brief Converts from rad/s to rpm
+ *
+ * \param speed Specifies the speed in rad/s.
+ *
+ * \return returns the converted speed in rpm.
+ * \see IfxStdIf_Pos_rpmToRads()
+ */
+IFX_INLINE float32 IfxStdIf_Pos_radsToRpm(float32 speed)
+{
+ return (60.0 / (2.0 * IFX_PI)) * speed;
+}
+
+
+/** \brief Converts from rpm to rad/s
+ *
+ * \param speed Specifies the speed in rpm.
+ *
+ * \return returns the converted speed in rad/s.
+ * \see IfxStdIf_Pos_radsToRpm()
+ */
+IFX_INLINE float32 IfxStdIf_Pos_rpmToRads(float32 speed)
+{
+ return speed * ((2.0 * IFX_PI) / 60.0);
+}
+
+
+/** Initialize the configuration structure to default
+ *
+ * \param config Position interface configuration. This parameter is initialized by the function
+ *
+ */
+IFX_EXTERN void IfxStdIf_Pos_initConfig(IfxStdIf_Pos_Config *config);
+
+/** \brief Print the device status
+ *
+ * \param driver driver handle
+ * \param io Interface to which the status is output
+ * \return none
+ */
+IFX_EXTERN void IfxStdIf_Pos_printStatus(IfxStdIf_Pos *driver, IfxStdIf_DPipe *io);
+
+
+#endif /* IFXSTDIF_POSIF_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/StdIf/IfxStdIf_PwmHl.c b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/StdIf/IfxStdIf_PwmHl.c
new file mode 100644
index 0000000..d13f3ec
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/StdIf/IfxStdIf_PwmHl.c
@@ -0,0 +1,58 @@
+/**
+ * \file IfxStdIf_PwmHl.c
+ * \brief Standard interface: Multi-channels, dual-complementary PWM interface
+ * \ingroup IfxStdIf
+ *
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ * $Date: 2014-02-27 20:08:24 GMT$
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ */
+
+#include "IfxStdIf_PwmHl.h"
+
+void IfxStdIf_PwmHl_initConfig(IfxStdIf_PwmHl_Config *config)
+{
+ config->deadtime = 0;
+ config->minPulse = 0;
+ config->channelCount = 0;
+ config->emergencyEnabled = FALSE;
+ config->outputMode = IfxPort_OutputMode_pushPull;
+ config->outputDriver = IfxPort_PadDriver_cmosAutomotiveSpeed1;
+ config->ccxActiveState = Ifx_ActiveState_high;
+ config->coutxActiveState = Ifx_ActiveState_high;
+}
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/StdIf/IfxStdIf_PwmHl.h b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/StdIf/IfxStdIf_PwmHl.h
new file mode 100644
index 0000000..ecf814b
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/StdIf/IfxStdIf_PwmHl.h
@@ -0,0 +1,322 @@
+/**
+ * \file IfxStdIf_PwmHl.h
+ * \brief Standard interface: Multi-channels, dual-complementary PWM interface
+ * \ingroup IfxStdIf
+ *
+ * \version disabled
+ * \copyright Copyright (c) 2019 Infineon Technologies AG. All rights reserved.
+ *
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ *
+ * \defgroup library_srvsw_stdif_pwmhl Standard interface: Multi-channels, dual-complementary PWM interface
+ * \ingroup library_srvsw_stdif
+ *
+ * The standard interface pwm high/low (PwmHl) abstract the hardware used for pwm feature. It provide, after proper initialization an hardware
+ * independant way to interact with the PWM functionallity like setting duty cycles, dead time,timer functionalities, ...
+ *
+ * The figure below shows the standard Multi-channels, dual-complementary PWM interface.
+ *
+ * \image html "PwmHl-overview.png" "Standard Multi-channels, dual-complementary PWM interface"
+ *
+ * This PWM interface provides multiple dual-complementary PWM channels.
+ * Each dual-complementary PWM channel is made of two PWM channels, a top channel CCx and a bottom channel COUTx.
+ * The interface implements the \ref library_srvsw_stdif_timer.
+ *
+ * This interface defines the following features:
+ * - Configurable duty cycle from 0% to 100%
+ * - Adjustable dead-time between top and bottom channels
+ * - Center aligned, left aligned, right aligned PWM
+ * - Optional minimal pulse cancellation
+ * - Optional emergency stop
+ * - Configurable signal active state for top and bottom PWM
+ * - Configurable output ports
+ * - Inherit the features from library_srvsw_stdif_timer
+ *
+ * Example of signal generation in center aligned mode:
+ *
+ * \image html "PwmHl-centerAligned.png" "Standard Multi-channels, dual-complementary PWM interface - Center aligned mode"
+ */
+
+#ifndef IFXSTDIF_PWMHL_H
+#define IFXSTDIF_PWMHL_H 1
+
+#include "IfxStdIf.h"
+#include "IfxStdIf_Timer.h"
+
+/** \brief Forward declaration */
+typedef struct IfxStdIf_PwmHl_ IfxStdIf_PwmHl;
+
+/** \brief Set the dead time in s
+ * \param stdIf Pointer to the interface driver object
+ * \param deadtime deadtime in second
+ * \retval TRUE In case of success
+ * \retval FALSE In case of failure
+ */
+typedef boolean (*IfxStdIf_PwmHl_SetDeadtime)(IfxStdIf_InterfaceDriver stdIf, float32 deadtime);
+
+/** \brief Return the dead time in s
+ *
+ * It returns the last dead time values set by IfxStdIf_PwmHl_SetDeadtime() or during initialisation
+ * \param stdIf Pointer to the interface driver object
+ * \return Returns the deadtime in second
+ */
+typedef float32 (*IfxStdIf_PwmHl_GetDeadtime)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Set the minimum pulse time in s
+ * \param stdIf Pointer to the interface driver object
+ * \param minPulse minimal pulse in second
+ * \retval TRUE In case of success
+ * \retval FALSE In case of failure
+ */
+typedef boolean (*IfxStdIf_PwmHl_SetMinPulse)(IfxStdIf_InterfaceDriver stdIf, float32 minPulse);
+
+/** \brief Return the minimum pulse time in s
+ *
+ * It returns the last minimum pulse time values set by IfxStdIf_PwmHl_SetMinPulse() or during initialisation
+ * \param stdIf Pointer to the interface driver object
+ * \return Returns the minimum pulse time in second
+ */
+typedef float32 (*IfxStdIf_PwmHl_GetMinPulse)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Return the PWM mode
+ *
+ * It returns the last pwm mode set by IfxStdIf_PwmHl_SetMode() or during initialisation
+ * \param stdIf Pointer to the interface driver object
+ * \return Returns the pwm mode
+ */
+typedef Ifx_Pwm_Mode (*IfxStdIf_PwmHl_GetMode)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Set the pwm mode
+ * \param stdIf Pointer to the interface driver object
+ * \param mode PWM mode
+ * \retval TRUE In case of success
+ * \retval FALSE In case of failure (feature not supported)
+ */
+typedef boolean (*IfxStdIf_PwmHl_SetMode)(IfxStdIf_InterfaceDriver stdIf, Ifx_Pwm_Mode mode);
+
+/** \brief Set the pwm ON time
+ * \param stdIf Pointer to the interface driver object
+ * \param tOn Pointer to an array of ON times in ticks. The array size must be equal to the number of PWM channels
+ * \return none
+ */
+typedef void (*IfxStdIf_PwmHl_SetOnTime)(IfxStdIf_InterfaceDriver stdIf, Ifx_TimerValue *tOn);
+
+/** \brief Set the pwm ON time and shift value
+ * \param stdIf Pointer to the interface driver object
+ * \param tOn Pointer to an array of ON times in ticks. The array size must be equal to the number of PWM channels
+ * \param shift Pointer to an array of shift values in ticks. The array size must be equal to the number of PWM channels
+ * \return none
+ */
+typedef void (*IfxStdIf_PwmHl_SetOnTimeAndShift)(IfxStdIf_InterfaceDriver stdIf, Ifx_TimerValue *tOn, Ifx_TimerValue *shift);
+
+/** \brief Set the pwm pulse of all switched independently
+ * \param stdIf Pointer to the interface driver object
+ * \param tOn Pointer to an array of ON times in s. The array size must be equal to the number of PWM channels times 2. Parameters order is Phase 0 top, phase 1 top, ... phase 0 bottom, phase 1 botteom, ...
+ * \param offset Pointer to an array of offset values in s. The array size must be equal to the number of PWM channels times 2. Parameters order is Phase 0 top, phase 1 top, ... phase 0 bottom, phase 1 botteom, ...
+ * \return none
+ */
+typedef void (*IfxStdIf_PwmHl_SetPulse)(IfxStdIf_InterfaceDriver stdIf, float32 *tOn, float32 *offset);
+
+/** \brief Set channels which are generating PWM or in "stuck-at" state.
+ *
+ * \param stdIf Pointer to the interface driver object
+ * \param activeCh Pointer to boolean array containing values for PWM channels.
+ * If FALSE, the channel will be in stuck-at state, else the channel will generate PWM.
+ *
+ * \param stuckSt Pointer to boolean array containing values for active channels.
+ * If FALSE, the stuck-at state is passive level, else the stuck-at state is active level.
+ *
+ * \note The values for the parameters are arranged as follows:
+ * index = 0 --> phase 0 top
+ * index = 1 --> phase 0 bottom
+ * index = 2 --> phase 1 top
+ * index = 3 --> phase 1 bottom
+ * index = 4 --> phase 2 top
+ * index = 5 --> phase 2 bottom
+ */
+typedef void (*IfxStdIf_PwmHl_SetupChannels)(IfxStdIf_InterfaceDriver stdIf, boolean *activeCh, boolean *stuckSt);
+
+/** \brief Standard interface object
+ */
+struct IfxStdIf_PwmHl_
+{
+ IfxStdIf_InterfaceDriver driver; /**< \brief Interface driver object */
+
+ /* PWM related APIs*/
+ IfxStdIf_PwmHl_SetDeadtime setDeadtime; /**< \brief IfxStdIf_PwmHl_SetDeadtime */
+ IfxStdIf_PwmHl_GetDeadtime getDeadtime; /**< \brief IfxStdIf_PwmHl_GetDeadtime */
+ IfxStdIf_PwmHl_SetMinPulse setMinPulse; /**< \brief IfxStdIf_PwmHl_SetMinPulse */
+ IfxStdIf_PwmHl_GetMinPulse getMinPulse; /**< \brief IfxStdIf_PwmHl_GetMinPulse */
+ IfxStdIf_PwmHl_GetMode getMode; /**< \brief IfxStdIf_PwmHl_GetMode */
+ IfxStdIf_PwmHl_SetMode setMode; /**< \brief IfxStdIf_PwmHl_SetMode */
+ IfxStdIf_PwmHl_SetOnTime setOnTime; /**< \brief IfxStdIf_PwmHl_SetOnTime */
+ IfxStdIf_PwmHl_SetOnTimeAndShift setOnTimeAndShift; /**< \brief IfxStdIf_PwmHl_SetOnTime */
+ IfxStdIf_PwmHl_SetPulse setPulse; /**< \brief IfxStdIf_PwmHl_Pulse */
+ IfxStdIf_PwmHl_SetupChannels setupChannels; /**< \brief IfxStdIf_PwmHl_SetupChannels */
+
+ IfxStdIf_Timer timer; /**< \brief Timer related standard interface */
+};
+
+/** \brief Multi-channels PWM object configuration */
+typedef struct
+{
+ float32 deadtime; /**< \brief Dead time between the top and bottom channels in seconds */
+ float32 minPulse; /**< \brief Min pulse allowed as active state for the top and bottom PWM in seconds */
+ uint8 channelCount; /**< \brief Number of PWM channels, one channel is made of a top and bottom channel */
+ boolean emergencyEnabled; /**< \brief Specifies if the emergency stop should be enabled or not */
+
+ IfxPort_OutputMode outputMode; /**< \brief Output mode of ccx and coutx pins */
+ IfxPort_PadDriver outputDriver; /**< \brief Output pad driver of ccx and coutx pins */
+
+ Ifx_ActiveState ccxActiveState; /**< \brief Top PWM active state */
+ Ifx_ActiveState coutxActiveState; /**< \brief Bottom PWM active state */
+} IfxStdIf_PwmHl_Config;
+
+/** \addtogroup library_srvsw_stdif_pwmhl
+ * \{
+ */
+
+/** \copydoc IfxStdIf_PwmHl_SetDeadtime
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE boolean IfxStdIf_PwmHl_setDeadtime(IfxStdIf_PwmHl *stdIf, float32 deadtime)
+{
+ return stdIf->setDeadtime(stdIf->driver, deadtime);
+}
+
+
+/** \copydoc IfxStdIf_PwmHl_GetDeadtime
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE float32 IfxStdIf_PwmHl_getDeadtime(IfxStdIf_PwmHl *stdIf)
+{
+ return stdIf->getDeadtime(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_PwmHl_SetMinPulse
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE boolean IfxStdIf_PwmHl_setMinPulse(IfxStdIf_PwmHl *stdIf, float32 minPulse)
+{
+ return stdIf->setMinPulse(stdIf->driver, minPulse);
+}
+
+
+/** \copydoc IfxStdIf_PwmHl_GetMinPulse
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE float32 IfxStdIf_PwmHl_getMinPulse(IfxStdIf_PwmHl *stdIf)
+{
+ return stdIf->getMinPulse(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_PwmHl_GetMode
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE Ifx_Pwm_Mode IfxStdIf_PwmHl_getMode(IfxStdIf_PwmHl *stdIf)
+{
+ return stdIf->getMode(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_PwmHl_SetMode
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE boolean IfxStdIf_PwmHl_setMode(IfxStdIf_PwmHl *stdIf, Ifx_Pwm_Mode mode)
+{
+ return stdIf->setMode(stdIf->driver, mode);
+}
+
+
+/** \copydoc IfxStdIf_PwmHl_SetOnTime
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE void IfxStdIf_PwmHl_setOnTime(IfxStdIf_PwmHl *stdIf, Ifx_TimerValue *tOn)
+{
+ stdIf->setOnTime(stdIf->driver, tOn);
+}
+
+
+/** \copydoc IfxStdIf_PwmHl_SetOnTimeAndShift
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE void IfxStdIf_PwmHl_setOnTimeAndShift(IfxStdIf_PwmHl *stdIf, Ifx_TimerValue *tOn, Ifx_TimerValue *shift)
+{
+ stdIf->setOnTimeAndShift(stdIf->driver, tOn, shift);
+}
+
+
+/** \copydoc IfxStdIf_PwmHl_SetPulse
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE void IfxStdIf_PwmHl_setPulse(IfxStdIf_PwmHl *stdIf, float32 *tOn, float32 *offset)
+{
+ stdIf->setPulse(stdIf->driver, tOn, offset);
+}
+
+
+/** \copydoc IfxStdIf_PwmHl_SetupChannels
+ */
+IFX_INLINE void IfxStdIf_PwmHl_setupChannels(IfxStdIf_PwmHl *stdIf, boolean *activeCh, boolean *stuckSt)
+{
+ IFX_UNUSED_PARAMETER(stdIf);
+ IFX_UNUSED_PARAMETER(activeCh);
+ IFX_UNUSED_PARAMETER(stuckSt);
+}
+
+/** \brief Return the timer standard interface used by the IfxStdIf_PwmHl standard interface
+ * \param stdIf Standard interface pointer
+ * \return Returns the pointer to the IfxStdIf_Timer object
+ */
+IFX_INLINE IfxStdIf_Timer *IfxStdIf_PwmHl_getTimer(IfxStdIf_PwmHl *stdIf)
+{
+ return &stdIf->timer;
+}
+
+
+/** \} */
+
+/** Initialize the configuration structure to default
+ *
+ * \param config Timer configuration. This parameter is initialised by the function
+ *
+ */
+IFX_EXTERN void IfxStdIf_PwmHl_initConfig(IfxStdIf_PwmHl_Config *config);
+
+#endif /* IFXSTDIF_PWMHL_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/StdIf/IfxStdIf_Timer.c b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/StdIf/IfxStdIf_Timer.c
new file mode 100644
index 0000000..9d95ea8
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/StdIf/IfxStdIf_Timer.c
@@ -0,0 +1,165 @@
+/**
+ * \file IfxStdIf_Timer.c
+ * \brief Standard interface: Timer
+ * \ingroup IfxStdIf
+ *
+ * \version disabled
+ * \copyright Copyright (c) 2019 Infineon Technologies AG. All rights reserved.
+ *
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ */
+
+#include "IfxStdIf_Timer.h"
+
+void IfxStdIf_Timer_initConfig(IfxStdIf_Timer_Config *config)
+{
+ config->frequency = 1000;
+ config->isrPriority = 0;
+ config->isrProvider = IfxSrc_Tos_cpu0;
+ config->minResolution = 0;
+ config->trigger.outputMode = IfxPort_OutputMode_pushPull;
+ config->trigger.outputDriver = IfxPort_PadDriver_cmosAutomotiveSpeed1;
+ config->trigger.risingEdgeAtPeriod = FALSE;
+ config->trigger.outputEnabled = FALSE;
+ config->trigger.enabled = FALSE;
+ config->trigger.triggerPoint = 0;
+ config->trigger.isrPriority = 0;
+ config->trigger.isrProvider = IfxSrc_Tos_cpu0;
+ config->countDir = IfxStdIf_Timer_CountDir_up;
+ config->startOffset = 0.0;
+}
+
+
+static float32 IfxStdIf_Timer_nopGetFrequency(IfxStdIf_InterfaceDriver stdIf)
+{
+ IFX_UNUSED_PARAMETER(stdIf);
+ return 0.0;
+}
+static Ifx_TimerValue IfxStdIf_Timer_nopGetPeriod(IfxStdIf_InterfaceDriver stdIf)
+{
+ IFX_UNUSED_PARAMETER(stdIf);
+ return 0;
+}
+static float32 IfxStdIf_Timer_nopGetResolution(IfxStdIf_InterfaceDriver stdIf)
+{
+ IFX_UNUSED_PARAMETER(stdIf);
+ return 0.0;
+}
+static Ifx_TimerValue IfxStdIf_Timer_nopGetTrigger(IfxStdIf_InterfaceDriver stdIf)
+{
+ IFX_UNUSED_PARAMETER(stdIf);
+ return 0;
+}
+static boolean IfxStdIf_Timer_nopSetFrequency(IfxStdIf_InterfaceDriver stdIf, float32 frequency)
+{
+ IFX_UNUSED_PARAMETER(stdIf);
+ IFX_UNUSED_PARAMETER(frequency);
+ return FALSE;
+}
+static void IfxStdIf_Timer_nopUpdateInputFrequency(IfxStdIf_InterfaceDriver stdIf)
+{
+ IFX_UNUSED_PARAMETER(stdIf);
+}
+static void IfxStdIf_Timer_nopApplyUpdate(IfxStdIf_InterfaceDriver stdIf)
+{
+ IFX_UNUSED_PARAMETER(stdIf);
+}
+static void IfxStdIf_Timer_nopDisableUpdate(IfxStdIf_InterfaceDriver stdIf)
+{
+ IFX_UNUSED_PARAMETER(stdIf);
+}
+static float32 IfxStdIf_Timer_nopGetInputFrequency(IfxStdIf_InterfaceDriver stdIf)
+{
+ IFX_UNUSED_PARAMETER(stdIf);
+ return 0.0;
+}
+static void IfxStdIf_Timer_nopRun(IfxStdIf_InterfaceDriver stdIf)
+{
+ IFX_UNUSED_PARAMETER(stdIf);
+}
+static boolean IfxStdIf_Timer_nopSetPeriod(IfxStdIf_InterfaceDriver stdIf, Ifx_TimerValue period)
+{
+ IFX_UNUSED_PARAMETER(stdIf);
+ IFX_UNUSED_PARAMETER(period);
+ return FALSE;
+}
+static void IfxStdIf_Timer_nopSetSingleMode(IfxStdIf_InterfaceDriver stdIf, boolean enabled)
+{
+ IFX_UNUSED_PARAMETER(stdIf);
+ IFX_UNUSED_PARAMETER(enabled);
+}
+static void IfxStdIf_Timer_nopSetTrigger(IfxStdIf_InterfaceDriver stdIf, Ifx_TimerValue triggerPoint)
+{
+ IFX_UNUSED_PARAMETER(stdIf);
+ IFX_UNUSED_PARAMETER(triggerPoint);
+}
+static void IfxStdIf_Timer_nopStop(IfxStdIf_InterfaceDriver stdIf)
+{
+ IFX_UNUSED_PARAMETER(stdIf);
+}
+static boolean IfxStdIf_Timer_nopAckTimerIrq(IfxStdIf_InterfaceDriver stdIf)
+{
+ IFX_UNUSED_PARAMETER(stdIf);
+ return FALSE;
+}
+static boolean IfxStdIf_Timer_nopAckTriggerIrq(IfxStdIf_InterfaceDriver stdIf)
+{
+ IFX_UNUSED_PARAMETER(stdIf);
+ return FALSE;
+}
+
+
+void IfxStdIf_Timer_initStdIf(IfxStdIf_Timer *stdIf, IfxStdIf_InterfaceDriver driver)
+{
+ stdIf->driver = driver;
+ stdIf->getFrequency =&IfxStdIf_Timer_nopGetFrequency ;
+ stdIf->getPeriod =&IfxStdIf_Timer_nopGetPeriod ;
+ stdIf->getResolution =&IfxStdIf_Timer_nopGetResolution ;
+ stdIf->getTrigger =&IfxStdIf_Timer_nopGetTrigger ;
+ stdIf->setFrequency =&IfxStdIf_Timer_nopSetFrequency ;
+ stdIf->updateInputFrequency =&IfxStdIf_Timer_nopUpdateInputFrequency;
+ stdIf->applyUpdate =&IfxStdIf_Timer_nopApplyUpdate ;
+ stdIf->disableUpdate =&IfxStdIf_Timer_nopDisableUpdate ;
+ stdIf->getInputFrequency =&IfxStdIf_Timer_nopGetInputFrequency ;
+ stdIf->run =&IfxStdIf_Timer_nopRun ;
+ stdIf->setPeriod =&IfxStdIf_Timer_nopSetPeriod ;
+ stdIf->setSingleMode =&IfxStdIf_Timer_nopSetSingleMode ;
+ stdIf->setTrigger =&IfxStdIf_Timer_nopSetTrigger ;
+ stdIf->stop =&IfxStdIf_Timer_nopStop ;
+ stdIf->ackTimerIrq =&IfxStdIf_Timer_nopAckTimerIrq ;
+ stdIf->ackTriggerIrq =&IfxStdIf_Timer_nopAckTriggerIrq ;
+}
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/StdIf/IfxStdIf_Timer.h b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/StdIf/IfxStdIf_Timer.h
new file mode 100644
index 0000000..cef0af8
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/StdIf/IfxStdIf_Timer.h
@@ -0,0 +1,481 @@
+/**
+ * \file IfxStdIf_Timer.h
+ * \brief Standard interface: Timer
+ * \ingroup IfxStdIf
+ *
+ * \version disabled
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ *
+ * \defgroup library_srvsw_stdif_timer Standard interface: Timer
+ * \ingroup library_srvsw_stdif
+ *
+ * The standard interface timer (Timer) abstract the hardware used for timer feature. It provide, after proper initialization an hardware
+ * independant way to interact with the timer functionallity like setting period, trigger points, ...
+ *
+ * The figure below shows the standard timer interface.
+ *
+ * \image html "Timer.png" "Standard timer interface"
+ *
+ * This interface defines the following features:
+ * - Timer with configurable frequency
+ * - Configurable counting direction
+ * - Optional interrupt on timer event with configurable service request provider and priority
+ * - Optional trigger signal with:
+ * - Optional interrupt on trigger event with configurable service request provider and priority
+ * - Configurable trigger point
+ * - Configurable trigger edge
+ * - trigger signal can be internal only or forwarded to a port pin
+ */
+
+#ifndef IFXSTDIF_TIMER_H
+#define IFXSTDIF_TIMER_H 1
+
+#include "Cpu/Std/Ifx_Types.h"
+#include "Src/Std/IfxSrc.h"
+#include "Port/Std/IfxPort.h"
+#include "IfxStdIf.h"
+/** \brief Output event enable / disable */
+typedef enum
+{
+ IfxStdIf_Timer_Output_disabled, /**< \brief Timer output is set to the inactive, no change in the output */
+ IfxStdIf_Timer_Output_enabled /**< \brief In case the trigger is enabled,
+ * the output is set to active between time 0 to the trigger point,
+ * and is set to inactive between the trigger point and the period.
+ * In case the trigger is disabled and counting direction if IfxStdIf_Timer_CountDir_up, the output is toggled when the timer is reset
+ * In case the trigger is disabled and counting direction if IfxStdIf_Timer_CountDir_down, the output is toggled when the timer is reloaded
+ * In case the trigger is disabled and counting direction if IfxStdIf_Timer_CountDir_upAndDown, the output is toggled when the timer reach 0
+ * In case the trigger is enabled the trigger is active before the trigger point and inactive after the trigger point.
+ */
+} IfxStdIf_Timer_OutputEvent;
+
+/** \brief Timer increment direction */
+typedef enum
+{
+ IfxStdIf_Timer_CountDir_up, /**< \brief Timer is counting up */
+ IfxStdIf_Timer_CountDir_upAndDown, /**< \brief Timer is counting up and down */
+ IfxStdIf_Timer_CountDir_down /**< \brief Timer is counting down */
+} IfxStdIf_Timer_CountDir;
+
+/** \brief Forward declaration */
+typedef struct IfxStdIf_Timer_ IfxStdIf_Timer;
+
+/** \brief Return the timer frequency in Hz
+ * \param stdIf Pointer to the interface driver object
+ * \return Return the timer frequency in Hz
+ */
+typedef float32 (*IfxStdIf_Timer_GetFrequency)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Return the timer period in ticks
+ * \param stdIf Pointer to the interface driver object
+ * \return Return the timer period in ticks
+ */
+typedef Ifx_TimerValue (*IfxStdIf_Timer_GetPeriod)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Return the timer resolution in seconds
+ * \param stdIf Pointer to the interface driver object
+ * \return Return the timer resolution in seconds
+ */
+typedef float32 (*IfxStdIf_Timer_GetResolution)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Return the timer trigger point
+ * \param stdIf Pointer to the interface driver object
+ * \return Return the timer timer point
+ */
+typedef Ifx_TimerValue (*IfxStdIf_Timer_GetTrigger)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Set the timer frequency in Hz
+ * \param stdIf Pointer to the interface driver object
+ * \param frequency Requested timer frequency in Hz
+ * \retval TRUE The requested frequency could be set
+ * \retval FALSE The requested frequency is out of range
+ */
+typedef boolean (*IfxStdIf_Timer_SetFrequency)(IfxStdIf_InterfaceDriver stdIf, float32 frequency);
+
+/** \brief Indicates the stdIf that the imput frequency has changed and that it should be taken in account
+ * \param stdIf Pointer to the interface driver object
+ * \return None
+ */
+typedef void (*IfxStdIf_Timer_UpdateInputFrequency)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Apply requested updates.
+ *
+ * Such requested update are calls to:
+ * - IfxStdIf_Timer_setSingleMode()
+ * - IfxStdIf_Timer_setTrigger()
+ * - IfxStdIf_Timer_setPeriod() or IfxStdIf_Timer_setFrequency()
+ * as well as PWM generation related calls such as:
+ * - IfxStdIf_PwmHl_setDeadtime()
+ * - IfxStdIf_PwmHl_setMode()
+ * - IfxStdIf_PwmHl_setOnTime()
+ * - IfxStdIf_PwmHl_setupChannels()
+ *
+ * It is important to note, that only one call to Timer_applyUpdate() is allowed within
+ * one timer period!!!
+ * In order to ensure correct update synchronisation, disableUpdate() should have been called previously.
+ *
+ * \param stdIf Pointer to the interface driver object
+ * \return None
+ */
+typedef void (*IfxStdIf_Timer_ApplyUpdate)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Disable updates
+ *
+ * The following API action will not be taken in account before applyUpdate is called:
+ * - IfxStdIf_Timer_setSingleMode()
+ * - IfxStdIf_Timer_setTrigger()
+ * - IfxStdIf_Timer_setPeriod() or IfxStdIf_Timer_setFrequency()
+ * as well as PWM generation related calls such as:
+ * - IfxStdIf_PwmHl_setDeadtime()
+ * - IfxStdIf_PwmHl_setMode()
+ * - IfxStdIf_PwmHl_setOnTime()
+ * - IfxStdIf_PwmHl_setupChannels()
+ *
+ * \param stdIf Pointer to the interface driver object
+ * \return None
+ */
+typedef void (*IfxStdIf_Timer_DisableUpdate)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Return the timer input frequency in Hz
+ * \param stdIf Pointer to the interface driver object
+ * \return Return the timer input frequency in Hz
+ */
+typedef float32 (*IfxStdIf_Timer_GetInputFrequency)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Immediately start the timer.
+ *
+ * Please note that other mechanism may avoid the timer to tick, such as when the
+ * global (input) clock to the timer block is inactive.
+ * \param stdIf Pointer to the interface driver object
+ * \return none
+ */
+typedef void (*IfxStdIf_Timer_Run)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Set the timer period.
+ *
+ * Timer_applyUpdate() shall be invoked in order this to take effect.
+ * \param stdIf Pointer to the interface driver object
+ * \param period Period value in ticks
+ * \retval TRUE The requested period could be set
+ * \retval FALSE The requested period is out of range
+ */
+typedef boolean (*IfxStdIf_Timer_SetPeriod)(IfxStdIf_InterfaceDriver stdIf, Ifx_TimerValue period);
+
+/** \brief Stop timer at the end of the period
+ *
+ * Timer_applyUpdate() shall be invoked in order this to take effect.
+ * \param stdIf Pointer to the interface driver object
+ * \param enabled If TRUE, enable the single mode, else disable the single mode (continuous mode)
+ * \return none
+ */
+typedef void (*IfxStdIf_Timer_SetSingleMode)(IfxStdIf_InterfaceDriver stdIf, boolean enabled);
+
+/** \brief Set trigger point.
+ *
+ * \see Timer_OutputEvent for the definition of the output level.
+ * Active state is defined by Timer_Config::outputActiveState.
+ *
+ * Timer_applyUpdate() shall be invoked in order this to take effect.
+ * \param stdIf Pointer to the interface driver object
+ * \param triggerPoint Trigger point in ticks from the period start.
+ * \return none
+ */
+typedef void (*IfxStdIf_Timer_SetTrigger)(IfxStdIf_InterfaceDriver stdIf, Ifx_TimerValue triggerPoint);
+
+/** \brief Immediately stops the timer
+ * \param stdIf Pointer to the interface driver object
+ * \return none
+ */
+typedef void (*IfxStdIf_Timer_Stop)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Return the timer interrupt flag and reset it
+ * \param stdIf Pointer to the interface driver object
+ * \return Return the timer interrupt flag
+ */
+typedef boolean (*IfxStdIf_Timer_AckTimerIrq)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Return the trigger interrupt flag and reset it
+ * \param stdIf Pointer to the interface driver object
+ * \return Return the trigger interrupt flag
+ */
+typedef boolean (*IfxStdIf_Timer_AckTriggerIrq)(IfxStdIf_InterfaceDriver stdIf);
+
+/** \brief Standard interface object
+ */
+struct IfxStdIf_Timer_
+{
+ IfxStdIf_InterfaceDriver driver; /**< \brief Interface driver object */
+ IfxStdIf_Timer_GetFrequency getFrequency; /**< \brief \see IfxStdIf_Timer_GetFrequency */
+ IfxStdIf_Timer_GetPeriod getPeriod; /**< \brief \see IfxStdIf_Timer_GetPeriod */
+ IfxStdIf_Timer_GetResolution getResolution; /**< \brief \see IfxStdIf_Timer_GetResolution */
+ IfxStdIf_Timer_GetTrigger getTrigger; /**< \brief \see IfxStdIf_Timer_GetTrigger */
+ IfxStdIf_Timer_SetFrequency setFrequency; /**< \brief \see IfxStdIf_Timer_SetFrequency */
+ IfxStdIf_Timer_UpdateInputFrequency updateInputFrequency; /**< \brief \see IfxStdIf_Timer_UpdateInputFrequency */
+ IfxStdIf_Timer_ApplyUpdate applyUpdate; /**< \brief \see IfxStdIf_Timer_ApplyUpdate */
+ IfxStdIf_Timer_DisableUpdate disableUpdate; /**< \brief \see IfxStdIf_Timer_DisableUpdate */
+ IfxStdIf_Timer_GetInputFrequency getInputFrequency; /**< \brief \see IfxStdIf_Timer_GetInputFrequency */
+ IfxStdIf_Timer_Run run; /**< \brief \see IfxStdIf_Timer_Run */
+ IfxStdIf_Timer_SetPeriod setPeriod; /**< \brief \see IfxStdIf_Timer_SetPeriod */
+ IfxStdIf_Timer_SetSingleMode setSingleMode; /**< \brief \see IfxStdIf_Timer_SetSingleMode */
+ IfxStdIf_Timer_SetTrigger setTrigger; /**< \brief \see IfxStdIf_Timer_SetTrigger */
+ IfxStdIf_Timer_Stop stop; /**< \brief \see IfxStdIf_Timer_Stop */
+ IfxStdIf_Timer_AckTimerIrq ackTimerIrq; /**< \brief \see IfxStdIf_Timer_AckTimerIrq */
+ IfxStdIf_Timer_AckTriggerIrq ackTriggerIrq; /**< \brief \see IfxStdIf_Timer_AckTriggerIrq */
+};
+
+/** \brief Trigger configuration */
+typedef struct
+{
+ boolean enabled; /**< \brief If true, the trigger functionality is Initialised, else ignored */
+ Ifx_TimerValue triggerPoint; /**< \brief Trigger point in timer ticks */
+ Ifx_Priority isrPriority; /**< \brief Interrupt isrPriority of the trigger interrupt, if 0 the interrupt is disable */
+ IfxSrc_Tos isrProvider; /**< \brief Interrupt service provider for the trigger interrupt */
+ IfxPort_OutputMode outputMode; /**< \brief Output mode */
+ IfxPort_PadDriver outputDriver; /**< \brief Output pad driver */
+ boolean risingEdgeAtPeriod; /**< \brief Set the clock signal polarity, if TRUE, the rising edge is at the period, else at the trigger offset. When the timer is stopped, the output is set to high */
+ boolean outputEnabled; /**< \brief If TRUE, the output pin is enabled, else disabled. In case the output is disabled, the output pin is not initialized. */
+} IfxStdIf_Timer_TrigConfig;
+
+/** \brief Timer configuration */
+typedef struct
+{
+ float32 frequency; /**< \brief PWM frequency in Hz. This parameter is only used to initialise the timer structure. An additional cell is required to build the timer. */
+ Ifx_Priority isrPriority; /**< \brief Interrupt isrPriority of the timer interrupt, if 0 the interrupt is disable */
+ IfxSrc_Tos isrProvider; /**< \brief Interrupt service provider for the timer interrupt */
+ float32 minResolution; /**< \brief Minimum resolution of the timer in seconds. if 0, this parameter is ignored. If the configuration does not enable this setting a warning is given */
+ IfxStdIf_Timer_TrigConfig trigger; /**< \brief Trigger configuration */
+ IfxStdIf_Timer_CountDir countDir; /**< \brief Timer counting mode */
+ float32 startOffset; /**< \brief FIXME make startOffset as Ifx_TimerValue. Timer initial offset in % of the period */
+} IfxStdIf_Timer_Config;
+
+/** \addtogroup library_srvsw_stdif_timer
+ * \{
+ */
+/** \copydoc IfxStdIf_Timer_GetFrequency
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE float32 IfxStdIf_Timer_getFrequency(IfxStdIf_Timer *stdIf)
+{
+ return stdIf->getFrequency(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_Timer_GetPeriod
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE Ifx_TimerValue IfxStdIf_Timer_getPeriod(IfxStdIf_Timer *stdIf)
+{
+ return stdIf->getPeriod(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_Timer_GetTrigger
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE Ifx_TimerValue IfxStdIf_Timer_getTrigger(IfxStdIf_Timer *stdIf)
+{
+ return stdIf->getTrigger(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_Timer_GetResolution
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE float32 IfxStdIf_Timer_getResolution(IfxStdIf_Timer *stdIf)
+{
+ return stdIf->getResolution(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_Timer_SetFrequency
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE boolean IfxStdIf_Timer_setFrequency(IfxStdIf_Timer *stdIf, float32 frequency)
+{
+ return stdIf->setFrequency(stdIf->driver, frequency);
+}
+
+
+/** \copydoc IfxStdIf_Timer_UpdateInputFrequency
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE void IfxStdIf_Timer_updateInputFrequency(IfxStdIf_Timer *stdIf)
+{
+ stdIf->updateInputFrequency(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_Timer_ApplyUpdate
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE void IfxStdIf_Timer_applyUpdate(IfxStdIf_Timer *stdIf)
+{
+ stdIf->applyUpdate(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_Timer_DisableUpdate
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE void IfxStdIf_Timer_disableUpdate(IfxStdIf_Timer *stdIf)
+{
+ stdIf->disableUpdate(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_Timer_GetInputFrequency
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE float32 IfxStdIf_Timer_getInputFrequency(IfxStdIf_Timer *stdIf)
+{
+ return stdIf->getInputFrequency(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_Timer_Run
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE void IfxStdIf_Timer_run(IfxStdIf_Timer *stdIf)
+{
+ stdIf->run(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_Timer_SetPeriod
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE boolean IfxStdIf_Timer_setPeriod(IfxStdIf_Timer *stdIf, Ifx_TimerValue period)
+{
+ return stdIf->setPeriod(stdIf->driver, period);
+}
+
+
+/** \copydoc IfxStdIf_Timer_SetSingleMode
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE void IfxStdIf_Timer_setSingleMode(IfxStdIf_Timer *stdIf, boolean enabled)
+{
+ stdIf->setSingleMode(stdIf->driver, enabled);
+}
+
+
+/** \copydoc IfxStdIf_Timer_SetTrigger
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE void IfxStdIf_Timer_setTrigger(IfxStdIf_Timer *stdIf, Ifx_TimerValue triggerPoint)
+{
+ stdIf->setTrigger(stdIf->driver, triggerPoint);
+}
+
+
+/** \copydoc IfxStdIf_Timer_Stop
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE void IfxStdIf_Timer_stop(IfxStdIf_Timer *stdIf)
+{
+ stdIf->stop(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_Timer_AckTimerIrq
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE boolean IfxStdIf_Timer_ackTimerIrq(IfxStdIf_Timer *stdIf)
+{
+ return stdIf->ackTimerIrq(stdIf->driver);
+}
+
+
+/** \copydoc IfxStdIf_Timer_AckTriggerIrq
+ * \param stdIf Standard interface pointer
+ */
+IFX_INLINE boolean IfxStdIf_Timer_ackTriggerIrq(IfxStdIf_Timer *stdIf)
+{
+ return stdIf->ackTriggerIrq(stdIf->driver);
+}
+
+
+/** \brief Convert timer ticks to seconds
+ * \param clockFreq Timer clock frequency
+ * \param ticks time value in ticks to be converted
+ * \return Return the converted time in s
+ */
+IFX_INLINE float32 IfxStdIf_Timer_tickToS(float32 clockFreq, Ifx_TimerValue ticks)
+{
+ return ticks / clockFreq;
+}
+
+
+/** \brief Convert seconds to timer ticks
+ * \param clockFreq Timer clock frequency
+ * \param seconds time value in seconds to be converted
+ * \return Return the converted time in timer ticks
+ */
+IFX_INLINE Ifx_TimerValue IfxStdIf_Timer_sToTick(float32 clockFreq, float32 seconds)
+{
+ return seconds * clockFreq;
+}
+
+
+/** \brief Return the timer period in second
+ * \param stdIf Pointer to the interface driver object
+ */
+IFX_INLINE float32 IfxStdIf_Timer_getPeriodSecond(IfxStdIf_Timer *stdIf)
+{
+ return IfxStdIf_Timer_tickToS(IfxStdIf_Timer_getInputFrequency(stdIf), stdIf->getPeriod(stdIf->driver));
+}
+
+
+/** \} */
+
+/** Initialize the configuration structure to default
+ *
+ * \param config Timer configuration. This parameter is initialised by the function
+ *
+ */
+IFX_EXTERN void IfxStdIf_Timer_initConfig(IfxStdIf_Timer_Config *config);
+
+/** Initialize the stdIf so that all call back function default to no operation
+ *
+ * \param stdIf Pointer to the interface driver object
+ * \param driver Interface driver object
+ *
+ */
+IFX_EXTERN void IfxStdIf_Timer_initStdIf(IfxStdIf_Timer *stdIf, IfxStdIf_InterfaceDriver driver);
+
+#endif /* IFXSTDIF_TIMER_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/StdIf/StandardInterfaceDataPipeExample.png b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/StdIf/StandardInterfaceDataPipeExample.png
new file mode 100644
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diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Bsp/Assert.c b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Bsp/Assert.c
new file mode 100644
index 0000000..4e2c910
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Bsp/Assert.c
@@ -0,0 +1,127 @@
+/**
+ * \file Assert.c
+ * \brief Assert functions.
+ *
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ * $Date: 2014-02-27 20:08:29 GMT$
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ */
+
+#include "Assert.h"
+
+#if IFX_CFG_ASSERT_STDIO == 1
+/** Current standard IO used for the IFX_ASSERT and IFX_VALIDATE */
+IfxStdIf_DPipe *Assert_io = NULL_PTR;
+#endif
+
+#if IFX_CFG_ASSERT_VERBOSE_LEVEL_DEFAULT > IFX_VERBOSE_LEVEL_OFF
+uint32 Assert_verboseLevel = IFX_CFG_ASSERT_VERBOSE_LEVEL_DEFAULT;
+#endif
+
+#if IFX_CFG_ASSERT_STDIO == 1
+void Ifx_Assert_setStandardIo(IfxStdIf_DPipe *standardIo)
+{
+ Assert_io = standardIo;
+}
+
+
+#endif
+
+/** \internal
+ * Text used to display the king of assertion
+ */
+const pchar Assert_level[6] = {
+ "OFF",
+ "FAILURE",
+ "ERROR",
+ "WARNING",
+ "INFO",
+ "DEBUG"
+};
+
+void Ifx_Assert_doLevel(uint8 level, pchar __assertion, pchar __file, unsigned int __line, pchar __function)
+{
+#if IFX_CFG_ASSERT_USE_BREAKPOINT == 1
+
+ if (level <= IFX_VERBOSE_LEVEL_ERROR)
+ {
+ __debug();
+ }
+
+#endif
+
+#if IFX_CFG_ASSERT_STDIO == 1
+
+ if (Assert_io != NULL_PTR)
+ {
+ IfxStdIf_DPipe_print(Assert_io, "ASSERTION %s '%s' in %s:%u (function '%s()')" ENDL, Assert_level[level],
+ __assertion, __file, __line, __function);
+ }
+
+#endif
+}
+
+
+boolean Ifx_Assert_doValidate(boolean expr, uint8 level, pchar __assertion, pchar __file, unsigned int __line, pchar __function)
+{
+ if (!((expr) || (level > Assert_verboseLevel)))
+ {
+#if IFX_CFG_ASSERT_USE_BREAKPOINT == 1
+
+ if (level <= IFX_VERBOSE_LEVEL_ERROR)
+ {
+ __debug();
+ }
+
+#endif
+
+#if IFX_CFG_ASSERT_STDIO == 1
+
+ if (Assert_io != NULL_PTR)
+ {
+ IfxStdIf_DPipe_print(Assert_io, "VALIDATION %s '%s' in %s:%u (function '%s()')" ENDL, Assert_level[level],
+ __assertion, __file, __line, __function);
+ }
+
+#endif
+ }
+ else
+ {}
+
+ return expr;
+}
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Bsp/Assert.h b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Bsp/Assert.h
new file mode 100644
index 0000000..0a057ed
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Bsp/Assert.h
@@ -0,0 +1,209 @@
+/**
+ * \file Assert.h
+ * \brief Assert functions.
+ * \ingroup library_srvsw_sysse_bsp_assert
+ *
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ * $Date: 2014-02-28 14:15:34 GMT$
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ * \defgroup library_srvsw_sysse_bsp_assert Assertion
+ * This module implements assertion functions.
+ * \ingroup library_srvsw_sysse_bsp
+ */
+
+#ifndef ASSERT_H
+#define ASSERT_H 1
+
+#include "_Utilities/Ifx_Assert.h"
+
+/** \addtogroup library_srvsw_sysse_bsp_assert
+ * Global configuration settings (Ifx_Cfg.h) :
+ * - IFX_CFG_ASSERT_STDIO: if IFX_CFG_ASSERT_STDIO=1, the assertion is output to the io
+ * defined by \ref Ifx_Assert_setStandardIo (). if IFX_CFG_ASSERT_STDIO=0, no text
+ * output is done.
+ * Default is IFX_CFG_ASSERT_STDIO=0
+ * - IFX_CFG_ASSERT_USE_BREAKPOINT: if IFX_CFG_ASSERT_USE_BREAKPOINT=1, a debug instruction is
+ * inserted in case an assertion occurs with a level of
+ * \ref IFX_VERBOSE_LEVEL_FAILURE or \ref IFX_VERBOSE_LEVEL_ERROR. If IFX_CFG_ASSERT_USE_BREAKPOINT=0 then
+ * no debug instruction is inserted.
+ * Default is IFX_CFG_ASSERT_USE_BREAKPOINT=0.
+ * - IFX_CFG_ASSERT_VERBOSE_LEVEL_DEFAULT: Set the assertion limit,
+ * assertion with a level below or equal to the limit are taken in
+ * account, other are ignored. range=[\ref IFX_VERBOSE_LEVEL_OFF, \ref IFX_VERBOSE_LEVEL_FAILURE,
+ * \ref IFX_VERBOSE_LEVEL_ERROR, \ref IFX_VERBOSE_LEVEL_WARNING, \ref IFX_VERBOSE_LEVEL_INFO,
+ * \ref IFX_VERBOSE_LEVEL_DEBUG]
+ * Default is IFX_CFG_ASSERT_VERBOSE_LEVEL_DEFAULT=\ref IFX_VERBOSE_LEVEL_INFO.
+ *
+ * Do not include this file but use # include "_Utilities/Ifx_Assert.h" instead
+ * \{ */
+
+#ifndef IFX_CFG_ASSERT_STDIO
+# define IFX_CFG_ASSERT_STDIO (0) /**< \brief If set to 1, the assert message is send to the Assert_io interface */
+#endif
+
+#if IFX_CFG_ASSERT_STDIO == 1
+# include "StdIf/IfxStdIf_DPipe.h"
+#endif
+
+#ifndef IFX_CFG_ASSERT_USE_BREAKPOINT
+# define IFX_CFG_ASSERT_USE_BREAKPOINT (0) /**< \brief If set to 1, the assert function will break the execution (breakpoint) */
+#endif
+
+#ifndef IFX_CFG_ASSERT_VERBOSE_LEVEL_DEFAULT
+/** \brief defines the assertion default level
+ *
+ * If not defined, the default assert level is set to IFX_VERBOSE_LEVEL_INFO
+ * */
+#define IFX_CFG_ASSERT_VERBOSE_LEVEL_DEFAULT (IFX_VERBOSE_LEVEL_INFO)
+#endif
+
+/** \brief Set the standard output used for \ref IFX_ASSERT and \ref IFX_VALIDATE
+ *
+ * For example the standard IO could redirect the output to a serial interface, CAN interface, ...
+ *
+ * \param standardIo Specifies the standard output used
+ *
+ * Enable only if (IFX_CFG_ASSERT_STDIO!=0)
+ *
+ * \return None.
+ */
+#if IFX_CFG_ASSERT_STDIO == 1
+IFX_EXTERN void Ifx_Assert_setStandardIo(IfxStdIf_DPipe *standardIo);
+#else
+#define Ifx_Assert_setStandardIo(standardIo) ((void)0)
+#endif
+
+/** \internal
+ * \brief Execute the assertion and display the assertion message
+ *
+ * Do not call this function directly, use IFX_ASSERT() instead
+ *
+ * \param level assertion level
+ * \param __assertion test as string, is displayed with the assertion message
+ * \param __file file in which the assertion occurred
+ * \param __line line number where the assertion occurred
+ * \param __function name of the function in which the assertion occurred
+ * \return void
+ */
+IFX_EXTERN void Ifx_Assert_doLevel(uint8 level, pchar __assertion, pchar __file, unsigned int __line, pchar __function);
+
+/** \internal
+ * \brief Execute the assertion and display the assertion message.
+ *
+ * Do not call this function directly, use IFX_VALIDATE() instead
+ *
+ * \param expr expression value, assertion occurs if FALSE
+ * \param level assertion level
+ * \param __assertion test as string, is displayed with the assertion message
+ * \param __file file in which the assertion occurred
+ * \param __line line number where the assertion occurred
+ * \param __function name of the function in which the assertion occurred
+ * \return expr
+ */
+IFX_EXTERN boolean Ifx_Assert_doValidate(boolean expr, uint8 level, pchar __assertion, pchar __file, unsigned int __line, pchar __function);
+
+#if IFX_CFG_ASSERT_VERBOSE_LEVEL_DEFAULT > IFX_VERBOSE_LEVEL_OFF
+IFX_EXTERN uint32 Assert_verboseLevel; /**< \bri-ef Current verbose level, this value is initialised to IFX_CFG_ASSERT_VERBOSE_LEVEL_DEFAULT */
+
+#else
+
+# undef IFX_CFG_ASSERT_STDIO
+# define IFX_CFG_ASSERT_STDIO (0)
+
+#endif
+
+#undef IFX_ASSERT
+#undef IFX_VALIDATE
+
+/** \brief Assertion function (assert)
+ *
+ * If expr is FALSE, then an assertion message is displayed. The message
+ * indicates the assertion level, the file, line and function where the
+ * assertion occurred, and also display expr as text. In case the debug break
+ * point is enabled then a debug instruction will also be inserted so that the debugger stops
+ *
+ * If expr is true, nothing is additional done.
+ *
+ * The expr expression is ignored (code disabled) in case the assertion level set by IFX_CFG_ASSERT_VERBOSE_LEVEL_DEFAULT is \ref IFX_VERBOSE_LEVEL_OFF.
+ *
+ * The output needs to the be set with the function Ifx_Assert_setStandardIo() in order for the message to be displayed.
+ *
+ * \param level level of the assertion, range=[\ref IFX_VERBOSE_LEVEL_OFF, \ref IFX_VERBOSE_LEVEL_FAILURE,
+ * \ref IFX_VERBOSE_LEVEL_ERROR, \ref IFX_VERBOSE_LEVEL_WARNING, \ref IFX_VERBOSE_LEVEL_INFO,
+ * \ref IFX_VERBOSE_LEVEL_DEBUG]
+ * \param expr expression to be tested. If FALSE the assertion is executed else nothing is done
+ *
+ * \return void
+ */
+#if IFX_CFG_ASSERT_VERBOSE_LEVEL_DEFAULT > IFX_VERBOSE_LEVEL_OFF
+# define IFX_ASSERT(level, expr) (((expr) || (level > Assert_verboseLevel)) ? ((void)0) : Ifx_Assert_doLevel(level,#expr, __FILE__, __LINE__, __func__))
+#else
+# define IFX_ASSERT(level, expr) ((void)0)
+#endif
+
+/** \brief Assertion function (validate)
+ *
+ * If expr is FALSE, then an assertion message is displayed. The message
+ * indicates the assertion level, the file, line and function where the
+ * assertion occurred, and also display expr as text. In case the debug
+ * break point is enabled then a debug instruction will also be inserted so
+ * that the debugger stops.
+ *
+ * \ref IFX_VALIDATE differs from \ref IFX_ASSERT in the way that the expr expression is
+ * evaluated whatever the assertion level set by IFX_CFG_ASSERT_VERBOSE_LEVEL_DEFAULT.
+ *
+ * The output needs to the be set with the function Ifx_Assert_setStandardIo() in order for the message to be displayed.
+ *
+ * \param level level of the assertion, range=[\ref IFX_VERBOSE_LEVEL_OFF, \ref IFX_VERBOSE_LEVEL_FAILURE,
+ * \ref IFX_VERBOSE_LEVEL_ERROR, \ref IFX_VERBOSE_LEVEL_WARNING, \ref IFX_VERBOSE_LEVEL_INFO,
+ * \ref IFX_VERBOSE_LEVEL_DEBUG]
+ * \param expr expression to be tested. If FALSE the assertion is executed else nothing is done
+ *
+ * \return void
+ */
+#if IFX_CFG_ASSERT_VERBOSE_LEVEL_DEFAULT > IFX_VERBOSE_LEVEL_OFF
+# define IFX_VALIDATE(level, expr) (Ifx_Assert_doValidate(expr, level,#expr, __FILE__, __LINE__, __func__))
+#else
+# define IFX_VALIDATE(level, expr) (expr)
+#endif
+
+/** \} */
+
+//#include "_Utilities/Ifx_Assert.h" /* Needs to be at the end of the file */
+
+#endif
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Bsp/Bsp.c b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Bsp/Bsp.c
new file mode 100644
index 0000000..36d7121
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Bsp/Bsp.c
@@ -0,0 +1,96 @@
+/**
+ * \file Bsp.c
+ * \brief Board support package
+ * \ingroup library_srvsw_sysse_bsp_bsp
+ *
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ * $Date: 2014-02-28 14:15:34 GMT$
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ */
+
+#include "Bsp.h"
+
+Ifx_TickTime TimeConst[TIMER_COUNT];
+
+/** \brief Initialize the time constants.
+ *
+ * Initialize the time constants TimeConst_0s, TimeConst_100ns, TimeConst_1us,
+ * TimeConst_10us, TimeConst_100us, TimeConst_1ms, TimeConst_10ms, TimeConst_100ms,
+ * TimeConst_1s, TimeConst_10s
+ * \return None.
+ */
+void initTime(void)
+{
+ sint32 Fsys = IfxStm_getFrequency(BSP_DEFAULT_TIMER);
+
+ TimeConst[TIMER_INDEX_10NS] = Fsys / (1000000000 / 10);
+ TimeConst[TIMER_INDEX_100NS] = Fsys / (1000000000 / 100);
+ TimeConst[TIMER_INDEX_1US] = Fsys / (1000000 / 1);
+ TimeConst[TIMER_INDEX_10US] = Fsys / (1000000 / 10);
+ TimeConst[TIMER_INDEX_100US] = Fsys / (1000000 / 100);
+ TimeConst[TIMER_INDEX_1MS] = Fsys / (1000 / 1);
+ TimeConst[TIMER_INDEX_10MS] = Fsys / (1000 / 10);
+ TimeConst[TIMER_INDEX_100MS] = Fsys / (1000 / 100);
+ TimeConst[TIMER_INDEX_1S] = Fsys * (1);
+ TimeConst[TIMER_INDEX_10S] = Fsys * (10);
+ TimeConst[TIMER_INDEX_100S] = Fsys * (100);
+}
+
+
+/** \brief Wait function.
+ *
+ * This is an empty function that just spend some time waiting.
+ *
+ * \return None.
+ */
+void waitPoll(void)
+{}
+
+/** \brief Wait time function.
+ *
+ * This is an empty function that that returns after the timeout elapsed. The
+ * minimal time spend in the function is guaranteed, but not the max time.
+ *
+ * \param timeout Specifies the time the function waits for before returning
+ *
+ * \return None.
+ */
+void waitTime(Ifx_TickTime timeout)
+{
+ wait(timeout);
+}
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Bsp/Bsp.h b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Bsp/Bsp.h
new file mode 100644
index 0000000..cea0398
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Bsp/Bsp.h
@@ -0,0 +1,443 @@
+/**
+ * \file Bsp.h
+ * \brief Board support package
+ * \ingroup library_srvsw_sysse_bsp_bsp
+ *
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ * $Date: 2014-02-28 14:15:35 GMT$
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ * \defgroup library_srvsw_sysse_bsp_bsp Board support package
+ * This module implements the board support package
+ * \ingroup library_srvsw_sysse_bsp
+ *
+ */
+
+#ifndef BSP_H
+#define BSP_H 1
+
+#include "Ifx_Cfg.h" /* Do not remove this include */
+#include "Cpu/Std/IfxCpu_Intrinsics.h" /* Do not remove this include */
+#include "_Utilities/Ifx_Assert.h" /* Do not remove this include */
+
+#include "Cpu/Std/IfxCpu.h"
+#include "Port/Std/IfxPort.h"
+#include "Src/Std/IfxSrc.h"
+#include "Stm/Std/IfxStm.h"
+#include "Scu/Std/IfxScuCcu.h"
+
+#ifndef BSP_DEFAULT_TIMER
+/** Defined the default timer used */
+#define BSP_DEFAULT_TIMER (&MODULE_STM0)
+#endif
+
+/******************************************************************************/
+/* Function prototypes */
+/******************************************************************************/
+
+/** \addtogroup library_srvsw_sysse_bsp_bsp
+ * \{ */
+/** \name Interrupt APIs
+ * \{ */
+IFX_INLINE boolean areInterruptsEnabled(void);
+IFX_INLINE boolean disableInterrupts(void);
+IFX_INLINE void enableInterrupts(void);
+IFX_INLINE void restoreInterrupts(boolean enabled);
+IFX_INLINE void forceDisableInterrupts(void);
+/** \} */
+/** \} */
+
+/******************************************************************************/
+/* Functions */
+/******************************************************************************/
+
+/** \brief Return the status of the global interrupts
+ *
+ * \retval TRUE if the global interrupts are enabled.
+ * \retval FALSE if the global interrupts are disabled.
+ *
+ * \see restoreInterrupts(), disableInterrupts()
+ */
+IFX_INLINE boolean areInterruptsEnabled(void)
+{
+ return IfxCpu_areInterruptsEnabled();
+}
+
+
+/** \brief Disable the global interrupts
+ *
+ * \retval TRUE if the global interrupts were enabled before the call to the function.
+ * \retval FALSE if the global interrupts are disabled before the call to the function.
+ *
+ * \see areInterruptsEnabled(), restoreInterrupts()
+ */
+IFX_INLINE boolean disableInterrupts(void)
+{
+ return IfxCpu_disableInterrupts();
+}
+
+
+/** \brief Disable the global interrupts forcefully
+ *
+ *
+ * \see areInterruptsEnabled(), restoreInterrupts()
+ */
+IFX_INLINE void forceDisableInterrupts(void)
+{
+ IfxCpu_forceDisableInterrupts();
+}
+
+
+/** \brief enable the global interrupts
+ *
+ */
+IFX_INLINE void enableInterrupts(void)
+{
+ IfxCpu_enableInterrupts();
+}
+
+
+/** \brief Restore the state of the global interrupts.
+ *
+ * \param enabled if TRUE, re-enable the global interrupts, else do nothing.
+ *
+ * \return None.
+ *
+ * \see areInterruptsEnabled(), disableInterrupts()
+ */
+IFX_INLINE void restoreInterrupts(boolean enabled)
+{
+ IfxCpu_restoreInterrupts(enabled);
+}
+
+
+/******************************************************************************/
+/* Macros */
+/******************************************************************************/
+#define TIMER_COUNT (11) /**< \internal \brief number of timer values defined */
+#define TIMER_INDEX_10NS (0) /**< \internal \brief Index of the time value 10ns*/
+#define TIMER_INDEX_100NS (1) /**< \internal \brief Index of the time value 100ns*/
+#define TIMER_INDEX_1US (2) /**< \internal \brief Index of the time value 1us*/
+#define TIMER_INDEX_10US (3) /**< \internal \brief Index of the time value 10us*/
+#define TIMER_INDEX_100US (4) /**< \internal \brief Index of the time value 100us*/
+#define TIMER_INDEX_1MS (5) /**< \internal \brief Index of the time value 1ms*/
+#define TIMER_INDEX_10MS (6) /**< \internal \brief Index of the time value 10ms*/
+#define TIMER_INDEX_100MS (7) /**< \internal \brief Index of the time value 100ms*/
+#define TIMER_INDEX_1S (8) /**< \internal \brief Index of the time value 1s*/
+#define TIMER_INDEX_10S (9) /**< \internal \brief Index of the time value 10s*/
+#define TIMER_INDEX_100S (10) /**< \internal \brief Index of the time value 100s*/
+
+/** \internal
+ * Array containing the time constants. This variable should not be used in the application. TimeConst_0s, TimeConst_10ns, ... should be used instead
+ *
+ */
+IFX_EXTERN Ifx_TickTime TimeConst[TIMER_COUNT];
+
+/******************************************************************************/
+/* Function prototypes */
+/******************************************************************************/
+/** \addtogroup library_srvsw_sysse_bsp_bsp
+ * \{ */
+/** \name Time APIs
+ * \{ */
+IFX_INLINE Ifx_TickTime addTTime(Ifx_TickTime a, Ifx_TickTime b);
+IFX_INLINE Ifx_TickTime elapsed(Ifx_TickTime since);
+IFX_INLINE Ifx_TickTime getDeadLine(Ifx_TickTime timeout);
+IFX_INLINE Ifx_TickTime getTimeout(Ifx_TickTime deadline);
+IFX_EXTERN void initTime(void);
+IFX_INLINE boolean isDeadLine(Ifx_TickTime deadLine);
+IFX_INLINE Ifx_TickTime now(void);
+IFX_INLINE Ifx_TickTime nowWithoutCriticalSection(void);
+IFX_INLINE boolean poll(volatile boolean *test, Ifx_TickTime timeout);
+IFX_INLINE Ifx_TickTime timingNoInterruptEnd(Ifx_TickTime since, boolean interruptEnabled);
+IFX_INLINE Ifx_TickTime timingNoInterruptStart(boolean *interruptEnabled);
+IFX_INLINE void wait(Ifx_TickTime timeout);
+IFX_EXTERN void waitPoll(void);
+IFX_EXTERN void waitTime(Ifx_TickTime timeout);
+
+/** Prototype for wait() functions */
+typedef void (*WaitTimeFunction)(Ifx_TickTime timeout);
+
+#define TimeConst_0s ((Ifx_TickTime)0) /**< \brief time constant equal to 1s */
+#define TimeConst_10ns (TimeConst[TIMER_INDEX_10NS]) /**< \brief time constant equal to 10ns */
+#define TimeConst_100ns (TimeConst[TIMER_INDEX_100NS]) /**< \brief time constant equal to 100ns */
+#define TimeConst_1us (TimeConst[TIMER_INDEX_1US]) /**< \brief time constant equal to 1us */
+#define TimeConst_10us (TimeConst[TIMER_INDEX_10US]) /**< \brief time constant equal to 10us */
+#define TimeConst_100us (TimeConst[TIMER_INDEX_100US]) /**< \brief time constant equal to 100us */
+#define TimeConst_1ms (TimeConst[TIMER_INDEX_1MS]) /**< \brief time constant equal to 1ms */
+#define TimeConst_10ms (TimeConst[TIMER_INDEX_10MS]) /**< \brief time constant equal to 10ms */
+#define TimeConst_100ms (TimeConst[TIMER_INDEX_100MS]) /**< \brief time constant equal to 100ms */
+#define TimeConst_1s (TimeConst[TIMER_INDEX_1S]) /**< \brief time constant equal to 1s */
+#define TimeConst_10s (TimeConst[TIMER_INDEX_10S]) /**< \brief time constant equal to 10s */
+#define TimeConst_100s (TimeConst[TIMER_INDEX_100S]) /**< \brief time constant equal to 100s */
+
+/**\}*/
+/**\}*/
+/******************************************************************************/
+/* Functions */
+/******************************************************************************/
+
+/** \brief Return system timer value (critical section).
+ *
+ * The function IfxStm_get() is called in a critical section, disabling
+ * the interrupts. The system timer value is limited to TIME_INFINITE.
+ *
+ * \return Returns system timer value.
+ */
+IFX_INLINE Ifx_TickTime now(void)
+{
+ Ifx_TickTime stmNow;
+ boolean interruptState;
+
+ interruptState = disableInterrupts();
+ stmNow = (Ifx_TickTime)IfxStm_get(BSP_DEFAULT_TIMER) & TIME_INFINITE;
+ restoreInterrupts(interruptState);
+
+ return stmNow;
+}
+
+
+/** \brief Return system timer value (without critical section).
+ *
+ * The function IfxStm_get() is called. The system timer value is limited to TIME_INFINITE.
+ *
+ * \return Returns system timer value.
+ */
+IFX_INLINE Ifx_TickTime nowWithoutCriticalSection(void)
+{
+ Ifx_TickTime stmNow;
+
+ stmNow = (Ifx_TickTime)IfxStm_get(BSP_DEFAULT_TIMER) & TIME_INFINITE;
+
+ return stmNow;
+}
+
+
+/** \brief Add 2 Ifx_TickTime values and return the result
+ *
+ * \param a parameter a
+ * \param b parameter b
+ *
+ * \return a + b. If either a or b is TIME_INFINITE, the result is TIME_INFINITE
+ */
+IFX_INLINE Ifx_TickTime addTTime(Ifx_TickTime a, Ifx_TickTime b)
+{
+ Ifx_TickTime result;
+
+ if ((a == TIME_INFINITE) || (b == TIME_INFINITE))
+ {
+ result = TIME_INFINITE;
+ }
+ else
+ {
+ result = a + b; /* FIXME check for overflow */
+ }
+
+ return result;
+}
+
+
+/** \brief Return the elapsed time in ticks.
+ *
+ * Return the elapsed time between the current time and the time passed as parameter
+ *
+ * \return Returns the elapsed time.
+ */
+IFX_INLINE Ifx_TickTime elapsed(Ifx_TickTime since)
+{
+ return now() - since;
+}
+
+
+/** \brief Return the time dead line.
+ *
+ * \param timeout Specifies the dead line from now: Deadline = Now + Timeout
+ *
+ * \return Return the time dead line.
+ */
+IFX_INLINE Ifx_TickTime getDeadLine(Ifx_TickTime timeout)
+{
+ Ifx_TickTime deadLine;
+
+ if (timeout == TIME_INFINITE)
+ {
+ deadLine = TIME_INFINITE;
+ }
+ else
+ {
+ deadLine = now() + timeout;
+ }
+
+ return deadLine;
+}
+
+
+/** \brief Return the time until the dead line.
+ *
+ * \param deadline Specifies the dead line from now: Deadline = Now + Timeout
+ *
+ * \return Return the time until the dead line.
+ */
+IFX_INLINE Ifx_TickTime getTimeout(Ifx_TickTime deadline)
+{
+ Ifx_TickTime timeout;
+
+ if (deadline == TIME_INFINITE)
+ {
+ timeout = TIME_INFINITE;
+ }
+ else
+ {
+ timeout = deadline - now();
+ }
+
+ return timeout;
+}
+
+
+/** \brief Return TRUE if the dead line is over.
+ *
+ * \param deadLine Specifies the dead line.
+ *
+ * \retval TRUE Returns TRUE if the dead line is over
+ * \retval FALSE Returns FALSE if the dead line is not yet over
+ */
+IFX_INLINE boolean isDeadLine(Ifx_TickTime deadLine)
+{
+ boolean result;
+
+ if (deadLine == TIME_INFINITE)
+ {
+ result = FALSE;
+ }
+ else
+ {
+ result = now() >= deadLine;
+ }
+
+ return result;
+}
+
+
+/** \brief Poll a variable for a time.
+ *
+ * \param test Specifies the variable to test.
+ * \param timeout Specifies the maximal time the variable will be tested
+ *
+ * \retval TRUE Returns TRUE if the variable gets TRUE before the timeout elapse
+ * \retval FALSE Returns FALSE if the variable is FALSE as the timeout elapse
+ */
+IFX_INLINE boolean poll(volatile boolean *test, Ifx_TickTime timeout)
+{
+ Ifx_TickTime deadLine = getDeadLine(timeout);
+
+ while ((*test == FALSE) && (isDeadLine(deadLine) == FALSE))
+ {}
+
+ return *test;
+}
+
+
+/** \brief Return the elapsed time in system timer ticks, and enable the interrupts.
+ *
+ * The interrupts are enable by the function
+ *
+ * \param since time returned by timingNoInterruptStart()
+ * \param interruptEnabled If TRUE, the interrupts will be enabled before the function exit. This parameter should be set to the value returned by \ref timingNoInterruptStart()
+ *
+ * \return Returns the elapsed time.
+ *
+ * \see timingNoInterruptStart()
+ */
+IFX_INLINE Ifx_TickTime timingNoInterruptEnd(Ifx_TickTime since, boolean interruptEnabled)
+{
+ Ifx_TickTime stmNow;
+
+ stmNow = nowWithoutCriticalSection();
+ restoreInterrupts(interruptEnabled);
+
+ return stmNow - since;
+}
+
+
+/** \brief Disable the interrupt and return system timer value.
+ *
+ * The interrupt remains disabled after the function call
+ *
+ * \return Returns system timer value.
+ *
+ * \see timingNoInterruptEnd()
+ */
+IFX_INLINE Ifx_TickTime timingNoInterruptStart(boolean *interruptEnabled)
+{
+ *interruptEnabled = disableInterrupts();
+
+ return nowWithoutCriticalSection();
+}
+
+
+/** \brief Wait for a while.
+ *
+ * \param timeout Specifies the waiting time
+ *
+ * \return None.
+ */
+IFX_INLINE void wait(Ifx_TickTime timeout)
+{
+ Ifx_TickTime deadLine = getDeadLine(timeout);
+
+ while (isDeadLine(deadLine) == FALSE)
+ {}
+}
+
+
+#define PIN_DRIVER_STRONG_SHARP IfxPort_PadDriver_cmosAutomotiveSpeed1
+#define Pin_setState(pin, mode) IfxPort_setPinState((pin)->port, (pin)->pinIndex, (mode))
+#define Pin_setGroupState(pin, mask, data) IfxPort_setGroupState((pin)->port, (pin)->pinIndex, (mask), (data))
+#define Pin_setMode(pin, mode) IfxPort_setPinMode((pin)->port, (pin)->pinIndex, (mode))
+#define Pin_setDriver(pin, mode) IfxPort_setPinPadDriver((pin)->port, (pin)->pinIndex, (mode))
+#define Pin_setStateHigh(pin) IfxPort_setPinHigh((pin)->port, (pin)->pinIndex)
+#define Pin_setStateLow(pin) IfxPort_setPinLow((pin)->port, (pin)->pinIndex)
+#define Pin_getState(pin) IfxPort_getPinState((pin)->port, (pin)->pinIndex)
+#define Pin_setGroupModeOutput(pin, mask, mode, outputIdx) IfxPort_setGroupModeOutput((pin)->port, (pin)->pinIndex, (mask), (mode), (outputIdx))
+#define Pin_setGroupModeInput(pin, mask, mode) IfxPort_setGroupModeInput((pin)->port, (pin)->pinIndex, (mask), (mode))
+#define Pin_setGroupState(pin, mask, data) IfxPort_setGroupState((pin)->port, (pin)->pinIndex, (mask), (data))
+#define Pin_getGroupState(pin, mask) IfxPort_getGroupState((pin)->port, (pin)->pinIndex, (mask))
+#define Pin_enableEmgStop(pin) IfxPort_enableEmergencyStop((pin)->port, (pin)->pinIndex)
+//------------------------------------------------------------------------------
+
+#endif /* BSP_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Bsp/info.dox b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Bsp/info.dox
new file mode 100644
index 0000000..4be72f8
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Bsp/info.dox
@@ -0,0 +1,5 @@
+/**
+ * \defgroup library_srvsw_sysse_bsp Board support package
+ * \ingroup library_srvsw_sysse
+ *
+ */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Comm/Ifx_Console.c b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Comm/Ifx_Console.c
new file mode 100644
index 0000000..9f79478
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Comm/Ifx_Console.c
@@ -0,0 +1,130 @@
+/**
+ * \file Ifx_Console.c
+ * \brief Main Ifx_Console module implementation file
+ *
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ * $Date: 2014-03-13 15:49:47 GMT$
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ */
+
+#include
+#include
+#include
+
+#include "Ifx_Console.h"
+#include "_Utilities/Ifx_Assert.h"
+#include "Cpu/Std/IfxCpu_Intrinsics.h"
+
+Ifx_Console Ifx_g_console;
+
+/**
+ * \brief Initialize the \ref Ifx_g_console object.
+ * \param standardIo Pointer to the IfxStdIf_DPipe object used by the \ref Ifx_g_console.
+ */
+void Ifx_Console_init(IfxStdIf_DPipe *standardIo)
+{
+ Ifx_g_console.standardIo = standardIo;
+ Ifx_g_console.align = 0;
+}
+
+
+/**
+ * \brief Print formatted string into \ref Ifx_g_console.
+ * \param format printf-compatible formatted string.
+ * \retval TRUE if the string is printed successfully
+ * \retval FALSE if the function failed.
+ */
+boolean Ifx_Console_print(pchar format, ...)
+{
+ if (!Ifx_g_console.standardIo->txDisabled)
+ {
+ char message[STDIF_DPIPE_MAX_PRINT_SIZE + 1];
+ Ifx_SizeT count;
+ va_list args;
+ va_start(args, format);
+ vsprintf((char *)message, format, args);
+ va_end(args);
+ count = (Ifx_SizeT)strlen(message);
+ IFX_ASSERT(IFX_VERBOSE_LEVEL_ERROR, count < STDIF_DPIPE_MAX_PRINT_SIZE);
+
+ return IfxStdIf_DPipe_write(Ifx_g_console.standardIo, (void *)message, &count, TIME_INFINITE);
+ }
+ else
+ {
+ return TRUE;
+ }
+}
+
+
+/**
+ * \brief Print formatted string into \ref Ifx_g_console.
+ * Indented with a number of spaces.
+ * \param format printf-compatible formatted string.
+ * \retval TRUE if the string is printed successfully
+ * \retval FALSE if the function failed.
+ */
+boolean Ifx_Console_printAlign(pchar format, ...)
+{
+ if (!Ifx_g_console.standardIo->txDisabled)
+ {
+ char message[STDIF_DPIPE_MAX_PRINT_SIZE + 1];
+ Ifx_SizeT align, count;
+ char spaces[17] = " ";
+ va_list args;
+ va_start(args, format);
+ vsprintf((char *)message, format, args);
+ va_end(args);
+ count = (Ifx_SizeT)strlen(message);
+ IFX_ASSERT(IFX_VERBOSE_LEVEL_ERROR, count < STDIF_DPIPE_MAX_PRINT_SIZE);
+ align = Ifx_g_console.align;
+
+ while (align > 0)
+ {
+ Ifx_SizeT scount;
+ scount = __min(align, 10);
+ IfxStdIf_DPipe_write(Ifx_g_console.standardIo, (void *)spaces, &scount, TIME_INFINITE);
+ align = align - scount;
+ }
+
+ return IfxStdIf_DPipe_write(Ifx_g_console.standardIo, (void *)message, &count, TIME_INFINITE);
+ }
+ else
+ {
+ return TRUE;
+ }
+}
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Comm/Ifx_Console.h b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Comm/Ifx_Console.h
new file mode 100644
index 0000000..faa8f2b
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Comm/Ifx_Console.h
@@ -0,0 +1,115 @@
+/**
+ * \file Ifx_Console.h
+ * \brief Main Console module header file
+ *
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ * $Date: 2014-02-28 14:15:36 GMT$
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ * \defgroup library_srvsw_sysse_comm_console Console
+ * This module implements "Main Console" functions
+ * \ingroup library_srvsw_sysse_comm
+ *
+ */
+#ifndef IFX_CONSOLE_H
+#define IFX_CONSOLE_H 1
+
+#include "StdIf/IfxStdIf_DPipe.h"
+
+//----------------------------------------------------------------------------------------
+#if !defined(IFX_CFG_CONSOLE_INDENT_SIZE)
+#define IFX_CFG_CONSOLE_INDENT_SIZE (4) /**<\brief Default indentation/alignment size */
+#endif
+
+typedef struct
+{
+ IfxStdIf_DPipe *standardIo; /**<\brief Pointer to the \ref IfxStdIf_DPipe object used as general console */
+ sint16 align; /**<\brief Variable for storing the actual (left)indentation level of the \ref Ifx_g_console */
+} Ifx_Console;
+
+IFX_EXTERN Ifx_Console Ifx_g_console; /**< \brief Default main console global variable */
+
+//----------------------------------------------------------------------------------------
+/** \addtogroup library_srvsw_sysse_comm_console
+ * \{ */
+
+#ifndef CONSOLE
+
+/* FIXME (Alann to discuss with Dian) there is no requirement to define multiple console, CONSOLE should be removed, and APIs used instead */
+/** \brief Alias \ref Ifx_g_console object (by value) */
+#define CONSOLE Ifx_g_console
+
+/** \brief Return pointer to the default console object
+ *
+ * User can override this function by defining new \ref CONSOLE macro and this function
+ * externally, e.g. inside Ifx_Cfg.h file.*/
+IFX_INLINE IfxStdIf_DPipe *Ifx_Console_getIo(void)
+{
+ return Ifx_g_console.standardIo;
+}
+
+
+#endif
+
+IFX_EXTERN void Ifx_Console_init(IfxStdIf_DPipe *standardIo);
+IFX_EXTERN boolean Ifx_Console_print(pchar format, ...);
+IFX_EXTERN boolean Ifx_Console_printAlign(pchar format, ...);
+
+/**
+ * \brief Decrement the alignment/indentation using the given value
+ * \param value the increment. If value == 0, \ref IFX_CFG_CONSOLE_INDENT_SIZE will be used.
+ */
+IFX_INLINE void Ifx_Console_decrAlign(sint16 value)
+{
+ value = (sint16)(Ifx_g_console.align - ((value == 0U) ? IFX_CFG_CONSOLE_INDENT_SIZE : value));
+ Ifx_g_console.align = (value > 0) ? value : 0;
+}
+
+
+/**
+ * \brief Increment the alignment/indentation using the given value
+ * \param value the increment. If value == 0, \ref IFX_CFG_CONSOLE_INDENT_SIZE will be used.
+ */
+IFX_INLINE void Ifx_Console_incrAlign(sint16 value)
+{
+ Ifx_g_console.align += ((value == 0) ? (sint16)IFX_CFG_CONSOLE_INDENT_SIZE : value);
+}
+
+
+/** \} */
+//----------------------------------------------------------------------------------------
+#endif
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Comm/Ifx_Shell.c b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Comm/Ifx_Shell.c
new file mode 100644
index 0000000..ff4ce09
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Comm/Ifx_Shell.c
@@ -0,0 +1,1335 @@
+/**
+ * \file Ifx_Shell.c
+ * \brief shell functions.
+ *
+ * \version disabled
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ */
+
+//---------------------------------------------------------------------------
+#include "Ifx_Shell.h"
+#include "_Utilities/Ifx_Assert.h"
+#include "Cpu/Std/IfxCpu_Intrinsics.h"
+
+#include
+#include
+#include
+
+#define IFX_SHELL_LLD "%lld "
+#define IFX_SHELL_LLX "%llx "
+#define IFX_SHELL_LLU "%llu "
+
+//---------------------------------------------------------------------------
+#define IFX_SHELL_MAX_MESSAGE_SIZE 255
+//---------------------------------------------------------------------------
+
+/* Macro to detect space character */
+#define ISSPACE(c) (((c) == ' ') || ((c) == '\t'))
+
+/* Macro to only execute parameter if echo is enabled for this shell */
+#define IFX_SHELL_IF_ECHO(X) {if (shell->control.echo) {X; }}
+
+/* Macro to write lots of spaces */
+#define IFX_SHELL_WRITE_SPACES(X) \
+ {int ii; for (ii = 0; ii < (X); ii++) {IfxStdIf_DPipe_print(shell->io, " "); }}
+
+/* Macro to write lots of backspaces */
+#define IFX_SHELL_WRITE_BACKSPACES(X) \
+ {int ii; for (ii = 0; ii < (X); ii++) {IfxStdIf_DPipe_print(shell->io, "\b"); }}
+
+//---------------------------------------------------------------------------
+char Ifx_Shell_cmdBuffer[IFX_CFG_SHELL_CMD_LINE_SIZE * IFX_CFG_SHELL_CMD_HISTORY_SIZE];
+//---------------------------------------------------------------------------
+void Ifx_Shell_execute(Ifx_Shell *shell, pchar commandLine);
+void Ifx_Shell_cmdEscapeProcess(Ifx_Shell *shell, char EscapeChar1, char EscapeChar2);
+const Ifx_Shell_Command *Ifx_Shell_commandListFind(Ifx_Shell *shell, pchar commandLine, pchar *args, Ifx_Shell_CommandListConst *commandList);
+static boolean Ifx_Shell_matchCommand(pchar *argsPtr, pchar *match);
+
+//---------------------------------------------------------------------------
+/**
+ * \brief Check whether the args is already at the end.
+ * \param args The argument null-terminated string
+ */
+boolean Ifx_Shell_isEndOfLine(pchar args)
+{
+ return ((args == NULL_PTR) || (*args == IFX_SHELL_NULL_CHAR)) ? TRUE : FALSE;
+}
+
+
+static boolean Ifx_Shell_writeResult(Ifx_Shell *shell, Ifx_SizeT Code)
+{
+ Ifx_SizeT length = sizeof(Code);
+ boolean result = IfxStdIf_DPipe_write(shell->io, &Code, &length, TIME_INFINITE);
+
+ IFX_ASSERT(IFX_VERBOSE_LEVEL_ERROR, result != FALSE);
+
+ return result;
+}
+
+
+//---------------------------------------------------------------------------
+boolean Ifx_Shell_showHelpSingle(Ifx_Shell_CommandListConst commandList, IfxStdIf_DPipe *io, boolean briefOnly, boolean singleCommand)
+{
+ const Ifx_Shell_Command *command = commandList;
+ uint32 index = 0;
+ pchar space = "";
+ pchar spaceParam = "";
+
+ while (command->commandLine != NULL_PTR)
+ {
+ pchar help = command->help;
+ pchar chunk;
+ boolean isParam = FALSE;
+ boolean isSyntax = FALSE;
+ IfxStdIf_DPipe_print(io, "%s%s", space, command->commandLine);
+
+ while (*help != IFX_SHELL_NULL_CHAR)
+ {
+ Ifx_SizeT count;
+ pchar matchp = "/p";
+ pchar matchs = "/s";
+ spaceParam = "";
+
+ if (Ifx_Shell_matchCommand(&help, &matchp))
+ { /* Parameter description found */
+ isParam = TRUE;
+ isSyntax = FALSE,
+ spaceParam = " ";
+ }
+ else if (Ifx_Shell_matchCommand(&help, &matchs))
+ { /* Parameter description found */
+ isParam = FALSE;
+ isSyntax = TRUE,
+ spaceParam = " SYNTAX: ";
+ }
+ else
+ { /* Other text */
+ if (isParam)
+ { /* Show param details*/
+ spaceParam = " ";
+ }
+ else if (isSyntax)
+ { /* Show param details*/
+ spaceParam = " ";
+ }
+ }
+
+ /* Split print by ENDL */
+ chunk = strstr(help, ENDL);
+
+ if (chunk == NULL_PTR)
+ {
+ chunk = help + strlen(help);
+ }
+ else
+ {
+ if (!briefOnly)
+ {
+ chunk += strlen(ENDL);
+ }
+ }
+
+ count = chunk - help;
+ IfxStdIf_DPipe_print(io, "%s%s", space, spaceParam);
+ IfxStdIf_DPipe_write(io, (void *)help, &count, TIME_INFINITE);
+
+ help += count;
+
+ if (briefOnly)
+ { /* Print Brief only */
+ break;
+ }
+ }
+
+ IfxStdIf_DPipe_print(io, ENDL);
+
+ if ((command->call == NULL_PTR) && (index == 0))
+ {
+ index = 1;
+ space = " ";
+ }
+
+ command = &command[1];
+
+ if (singleCommand)
+ {
+ break;
+ }
+ }
+
+ return TRUE;
+}
+
+
+boolean Ifx_Shell_showHelpSingleCommand(pchar args, void *shellPtr, IfxStdIf_DPipe *io)
+{
+ Ifx_Shell_CommandListConst commandList;
+ const Ifx_Shell_Command *shellCommand = Ifx_Shell_commandListFind(shellPtr, args, &args, &commandList);
+
+ if (shellCommand != NULL_PTR)
+ {
+ if (shellCommand->call == NULL_PTR)
+ {
+ Ifx_Shell_showHelpSingle(commandList, io, FALSE, FALSE);
+ }
+ else
+ {
+ if (commandList->call == NULL_PTR)
+ {
+ IfxStdIf_DPipe_print(io, "%s ", commandList->commandLine);
+ }
+
+ Ifx_Shell_showHelpSingle(shellCommand, io, FALSE, TRUE);
+ }
+
+ return TRUE;
+ }
+ else
+ {
+ IfxStdIf_DPipe_print(io, "unknown command");
+ return FALSE;
+ }
+}
+
+
+boolean Ifx_Shell_showHelp(pchar args, void *shellPtr, IfxStdIf_DPipe *io)
+{
+ sint32 i;
+ Ifx_Shell *shell = shellPtr;
+ boolean result = TRUE;
+
+ if (*args == IFX_SHELL_NULL_CHAR)
+ {
+ for (i = 0; i < IFX_CFG_SHELL_COMMAND_LISTS; i++)
+ {
+ if (shell->commandList[i] != NULL_PTR)
+ {
+ Ifx_Shell_showHelpSingle(shell->commandList[i], io, TRUE, FALSE);
+ }
+ }
+ }
+ else
+ {
+ result = Ifx_Shell_showHelpSingleCommand(args, shellPtr, io);
+ }
+
+ return result;
+}
+
+
+boolean Ifx_Shell_protocolStart(pchar args, void *data, IfxStdIf_DPipe *io)
+{
+ Ifx_Shell *shell = data;
+ boolean Result = TRUE;
+
+ if (Ifx_Shell_matchToken(&args, "?") != FALSE)
+ {
+ IfxStdIf_DPipe_print(io, "Syntax : protocol start" ENDL);
+ IfxStdIf_DPipe_print(io, " > start a protocol" ENDL);
+ }
+ else if (Ifx_Shell_matchToken(&args, "start") != FALSE)
+ {
+ if ((shell->protocol.start != NULL_PTR) && (shell->protocol.object != NULL_PTR))
+ {
+ Result = shell->protocol.start(shell->protocol.object, io);
+ shell->protocol.started = (Result != FALSE);
+
+ if (shell->protocol.onStart != NULL_PTR)
+ {
+ shell->protocol.onStart(shell->protocol.object, shell->protocol.onStartData);
+ }
+ }
+ else
+ {
+ Result = FALSE;
+ }
+ }
+ else
+ {}
+
+ return Result;
+}
+
+
+boolean Ifx_Shell_bbProtocolStart(pchar args, void *data, IfxStdIf_DPipe *io)
+{
+ boolean result = TRUE;
+
+ if (Ifx_Shell_matchToken(&args, "?") != FALSE)
+ {
+ IfxStdIf_DPipe_print(io, "Syntax : protocol start" ENDL);
+ IfxStdIf_DPipe_print(io, " > start a protocol" ENDL);
+ }
+ else if (Ifx_Shell_matchToken(&args, "protocol") != FALSE)
+ {
+ result = Ifx_Shell_protocolStart(args, data, io);
+ }
+ else
+ {}
+
+ return result;
+}
+
+
+//---------------------------------------------------------------------------
+void Ifx_Shell_initConfig(Ifx_Shell_Config *config)
+{
+ uint32 i;
+
+ for (i = 0; i < IFX_CFG_SHELL_COMMAND_LISTS; i++)
+ {
+ config->commandList[i] = NULL_PTR;
+ }
+
+ config->standardIo = NULL_PTR;
+ config->echo = TRUE;
+ config->protocol.execute = NULL_PTR;
+ config->protocol.object = NULL_PTR;
+ config->protocol.onStart = NULL_PTR;
+ config->protocol.onStartData = NULL_PTR;
+ config->protocol.start = NULL_PTR;
+ config->protocol.started = FALSE;
+ config->sendResultCode = FALSE;
+ config->showPrompt = TRUE;
+ config->standardIo = NULL_PTR;
+}
+
+
+boolean Ifx_Shell_init(Ifx_Shell *shell, const Ifx_Shell_Config *config)
+{
+ sint32 i;
+ char **CmdHistory = NULL_PTR; /* Pointer to array of pointers for command history items */
+
+ /* Ensure state variable is cleared */
+ memset(shell, 0, sizeof(*shell));
+
+ shell->protocol = config->protocol;
+ shell->protocol.started = FALSE;
+
+ shell->io = config->standardIo;
+ shell->control.showPrompt = config->showPrompt;
+ shell->control.sendResultCode = config->sendResultCode;
+ shell->control.echo = config->echo;
+ shell->control.echoError = TRUE;
+ shell->control.enabled = TRUE;
+
+ shell->locals.escBracketNum = IFX_SHELL_NULL_CHAR; /* Used to cache number in sequence "ESC [ 1/2/3/4 ~" */
+ shell->locals.cmdState = IFX_SHELL_CMD_STATE_NORMAL;
+
+ /* Copy command line buffer pointer into state variable */
+ shell->cmd.cmdStr = shell->locals.cmdStr;
+
+ /* Initialize command history space and cache pointer */
+ memset(Ifx_Shell_cmdBuffer, 0, sizeof(Ifx_Shell_cmdBuffer));
+ shell->cmdHistory[0] = &Ifx_Shell_cmdBuffer[0];
+
+ for (i = 0; i < IFX_CFG_SHELL_COMMAND_LISTS; i++)
+ {
+ shell->commandList[i] = config->commandList[i];
+ }
+
+ /* Initialize command history pointers */
+ CmdHistory = shell->cmdHistory;
+
+ for (i = 1; i < IFX_CFG_SHELL_CMD_HISTORY_SIZE; i++)
+ {
+ CmdHistory[i] = &CmdHistory[i - 1][IFX_CFG_SHELL_CMD_LINE_SIZE]; /* Items are just offsets into a large allocated area */
+ }
+
+ shell->cmd.historyItem = IFX_SHELL_CMD_HISTORY_NO_ITEM;
+
+ /* Pre-load useful commands into history buffer */
+ strcpy(CmdHistory[0], "help");
+ //strcpy(CmdHistory[1], "protocol start");
+
+ if (shell->control.showPrompt != 0)
+ {
+ IfxStdIf_DPipe_print(shell->io, ENDL);
+ IfxStdIf_DPipe_print(shell->io, IFX_CFG_SHELL_PROMPT);
+ }
+
+ return TRUE;
+}
+
+
+void Ifx_Shell_process(Ifx_Shell *shell)
+{
+ Ifx_SizeT i, j; /* Loop variables */
+ Ifx_SizeT count;
+ Ifx_SizeT readCount;
+ boolean NormalKeyPress; /* Indicates if this is a normal keypress, i.e. not part of an escape code */
+
+ Ifx_Shell_CmdLine *Cmd = &shell->cmd;
+ char *inputbuffer = shell->locals.inputbuffer;
+ char *cmdStr = shell->locals.cmdStr;
+ char **CmdHistory = shell->cmdHistory;
+
+ if (shell->control.enabled == 0)
+ {
+ return;
+ }
+
+ if ((shell->protocol.object != NULL_PTR) && (shell->protocol.started != FALSE))
+ {
+ shell->protocol.execute(shell->protocol.object);
+ }
+ else
+ {
+ /**** NORMAL MODE ****/
+
+ /********************************************************************************/
+ /* Read all characters until enter inclusive. */
+ /* If the command is bigger than IFX_SHELL_CMD_SIZE, the command is ignored. */
+ /* */
+ /* Escape sequences are handled by a state machine. */
+ /* The following escape sequences (prefix "ESC [") are supported: */
+ /* */
+ /* A - up B - down C - right D - left */
+ /* 1~ - HOME 2~ - INSERT 3~ - DELETE 5~ - END */
+ /* */
+ /* Backspace ('\b') is also supported. */
+ /********************************************************************************/
+
+ count = 0;
+ readCount = IFX_CFG_SHELL_CMD_LINE_SIZE - count;
+ IfxStdIf_DPipe_read(shell->io, &inputbuffer[count], &readCount, TIME_NULL);
+ count += readCount;
+
+ for (i = 0; i < count; i++)
+ {
+ /* By default, we assume character is part of escape sequence */
+ NormalKeyPress = FALSE;
+
+ /* Process key pressed */
+ switch (inputbuffer[i])
+ {
+ /* New line (ENTER) */
+ case '\n':
+ case '\r':
+ /* Print new line to terminal if requested */
+ IFX_SHELL_IF_ECHO(IfxStdIf_DPipe_print(shell->io, ENDL))
+
+ /* Execute command if length is valid - i.e. not an over-full buffer
+ * (prevents attempted execution of junk) */
+ if (Cmd->length < IFX_CFG_SHELL_CMD_LINE_SIZE)
+ {
+ cmdStr[Cmd->length] = IFX_SHELL_NULL_CHAR; /* Terminate cmdStr */
+
+ if (Cmd->historyAdd != FALSE)
+ {
+ /* Shuffle history up */
+ for (j = IFX_CFG_SHELL_CMD_HISTORY_SIZE - 1; j > 0; j--)
+ {
+ /* Copy text */
+ strncpy(CmdHistory[j], CmdHistory[j - 1], IFX_CFG_SHELL_CMD_LINE_SIZE);
+ }
+
+ /* Copy in new entry */
+ strncpy(CmdHistory[0], cmdStr, IFX_CFG_SHELL_CMD_LINE_SIZE);
+ }
+
+ /* Execute command */
+ Ifx_Shell_execute(shell, cmdStr);
+ }
+
+ /* Show prompt if in main shell */
+ if (shell->control.showPrompt != 0)
+ {
+ IfxStdIf_DPipe_print(shell->io, IFX_CFG_SHELL_PROMPT);
+ }
+
+ /* Reset command line buffer length */
+ Cmd->length = 0;
+
+ /* Reset command line buffer cursor position */
+ Cmd->cursor = 0;
+
+ /* Clear flag */
+ Cmd->historyAdd = FALSE;
+
+ /* Ensure we're not in command history list */
+ Cmd->historyItem = IFX_SHELL_CMD_HISTORY_NO_ITEM;
+ break;
+
+ /* Backspace (may occur in middle of text if cursor location is not at end) */
+ case '\b':
+
+ if (Cmd->cursor > 0)
+ {
+ /* Update on screen */
+ if (shell->control.echo != 0)
+ {
+ /* Move left one character */
+ IfxStdIf_DPipe_print(shell->io, "\b");
+
+ /* Update line with new characters */
+ for (j = Cmd->cursor; j < Cmd->length; j++)
+ {
+ IfxStdIf_DPipe_print(shell->io, "%c", cmdStr[j]);
+ }
+
+ /* Write over duplicated character at end */
+ IfxStdIf_DPipe_print(shell->io, " ");
+ IFX_SHELL_WRITE_BACKSPACES((Cmd->length - Cmd->cursor) + 1)
+ }
+
+ /* Update in command line variable. Shuffle text left */
+ strncpy(&cmdStr[Cmd->cursor - 1], &cmdStr[Cmd->cursor], Cmd->length - Cmd->cursor);
+
+ /* Terminate string at end of shorter string */
+ cmdStr[Cmd->length - 1] = IFX_SHELL_NULL_CHAR;
+
+ Cmd->length--;
+ Cmd->cursor--;
+
+ /* Command line has been modified */
+ Cmd->historyAdd = TRUE;
+ }
+
+ break;
+
+ /* Escape character */
+ case '\x1B': /*'\x1B': */
+ shell->locals.cmdState = IFX_SHELL_CMD_STATE_ESCAPE;
+ break;
+
+ /* '[' - check to see if this is second part of an escape sequence */
+ case '[':
+
+ if (shell->locals.cmdState == IFX_SHELL_CMD_STATE_ESCAPE)
+ {
+ /* ESC [ pressed */
+ shell->locals.cmdState = IFX_SHELL_CMD_STATE_ESCAPE_BRACKET;
+ }
+ else
+ {
+ NormalKeyPress = TRUE;
+ }
+
+ break;
+
+ /* Check for supported characters in escape sequences ( ESC [ A/B/C/D ) */
+ case 'A':
+ case 'B':
+ case 'C':
+ case 'D':
+
+ if (shell->locals.cmdState == IFX_SHELL_CMD_STATE_ESCAPE_BRACKET)
+ {
+ /* Process arrow keys */
+ Ifx_Shell_cmdEscapeProcess(shell, inputbuffer[i], 0);
+
+ /* End of escape sequence */
+ shell->locals.cmdState = IFX_SHELL_CMD_STATE_NORMAL;
+ }
+ else
+ {
+ NormalKeyPress = TRUE;
+ }
+
+ break;
+
+ /* Check for supported characters in escape sequences (ESC [ 2/4/5 ~) */
+ case '1':
+ case '2':
+ case '3':
+ case '4':
+
+ if (shell->locals.cmdState == IFX_SHELL_CMD_STATE_ESCAPE_BRACKET)
+ {
+ /* Store number for use once complete escape sequence is confirmed (below) */
+ shell->locals.escBracketNum = inputbuffer[i];
+ shell->locals.cmdState = IFX_SHELL_CMD_STATE_ESCAPE_BRACKET_NUMBER;
+ }
+ else
+ {
+ NormalKeyPress = TRUE;
+ }
+
+ break;
+
+ /* Check for supported characters in escape sequences (ESC [ 2/4/5 ~) */
+ case '~':
+
+ if (shell->locals.cmdState == IFX_SHELL_CMD_STATE_ESCAPE_BRACKET_NUMBER)
+ {
+ /* Process home/delete/end */
+ Ifx_Shell_cmdEscapeProcess(shell, shell->locals.escBracketNum, '~');
+
+ /* End of escape sequence */
+ shell->locals.cmdState = IFX_SHELL_CMD_STATE_NORMAL;
+ }
+ else
+ {
+ NormalKeyPress = TRUE;
+ }
+
+ break;
+
+ /* Normal character - add to command string */
+ default:
+ NormalKeyPress = TRUE;
+ break;
+ }
+
+ IFX_ASSERT(IFX_VERBOSE_LEVEL_ERROR, Cmd->length >= Cmd->cursor); /* Sanity check */
+
+ /* If this was a normal key press (not part of an escape sequence),
+ * add it to the command string */
+ if (NormalKeyPress != FALSE)
+ {
+ /* Ensure state machine is reset */
+ shell->locals.cmdState = IFX_SHELL_CMD_STATE_NORMAL;
+
+ /* If not filled buffer, add in this character */
+ if (Cmd->length < (IFX_CFG_SHELL_CMD_LINE_SIZE - 1))
+ {
+ /* Command line has been modified */
+ Cmd->historyAdd = TRUE;
+
+ /* Copy into command line */
+ cmdStr[Cmd->cursor] = inputbuffer[i];
+ Cmd->cursor++;
+
+ /* Update length of buffer */
+ Cmd->length = __max(Cmd->length, Cmd->cursor);
+
+ if (shell->control.echo != 0)
+ {
+ /* echo character to shell output if requested */
+ shell->locals.echo[0] = inputbuffer[i];
+ IfxStdIf_DPipe_print(shell->io, shell->locals.echo);
+ }
+ }
+ else
+ {
+ /* Line too long - ignore further characters */
+ Cmd->historyAdd = FALSE; /* Invalid command line */
+ }
+ }
+ }
+ }
+}
+
+
+void Ifx_Shell_deinit(Ifx_Shell *shell)
+{
+ (void)shell; /* ignore compiler warning; */
+ // tbd free necessary memory
+}
+
+
+pchar Ifx_Shell_skipWhitespace(pchar args)
+{
+ if (args != NULL_PTR)
+ {
+ while ((*args != IFX_SHELL_NULL_CHAR) && (ISSPACE(*args)))
+ {
+ args = &args[1];
+ }
+ }
+
+ return args;
+}
+
+
+boolean Ifx_Shell_matchToken(pchar *argsPtr, pchar token)
+{
+ pchar savedArguments = *argsPtr;
+ char buffer[256];
+ boolean result = FALSE;
+
+ if (Ifx_Shell_parseToken(argsPtr, buffer, Ifx_COUNTOF(buffer)) != FALSE)
+ {
+ if (strcmp(token, buffer) == 0)
+ {
+ result = TRUE;
+ }
+ }
+
+ if (result == FALSE)
+ {
+ // No match: don't advance pointer
+ *argsPtr = savedArguments;
+ }
+
+ return result;
+}
+
+
+static boolean Ifx_Shell_matchCommand(pchar *argsPtr, pchar *match)
+{
+ boolean result = FALSE;
+ pchar savedArguments = *argsPtr;
+ pchar savedMatch = *match;
+ char buffer0[256];
+ char buffer1[256];
+
+ if ((Ifx_Shell_parseToken(argsPtr, buffer0, Ifx_COUNTOF(buffer0)) != FALSE)
+ && (Ifx_Shell_parseToken(match, buffer1, Ifx_COUNTOF(buffer1)) != FALSE))
+ {
+ if (strcmp(buffer1, buffer0) == 0)
+ {
+ result = TRUE;
+ }
+ }
+
+ if (result == FALSE)
+ {
+ // No match: don't advance pointer
+ *argsPtr = savedArguments;
+ *match = savedMatch;
+ }
+
+ return result;
+}
+
+
+boolean Ifx_Shell_parseToken(pchar *argsPtr, char *tokenBuffer, int bufferLength)
+{
+ int mindex = 0;
+ pchar args = Ifx_Shell_skipWhitespace(*argsPtr);
+
+ tokenBuffer[0] = IFX_SHELL_NULL_CHAR;
+
+ if (args == NULL_PTR)
+ {
+ return FALSE;
+ }
+
+ if (*args == '\"')
+ {
+ args = &args[1];
+
+ while ((*args != IFX_SHELL_NULL_CHAR) && (*args != '\"'))
+ {
+ if (mindex < bufferLength)
+ {
+ tokenBuffer[mindex] = *args;
+ mindex++;
+ }
+
+ args = &args[1];
+ }
+
+ // error if no closing quote
+ if (*args != '\"')
+ {
+ return FALSE;
+ }
+
+ args = &args[1];
+ }
+ else
+ {
+ // don't allow unquoted empty tokens
+ if (*args == IFX_SHELL_NULL_CHAR)
+ {
+ return FALSE;
+ }
+
+ while ((*args != IFX_SHELL_NULL_CHAR) && (!ISSPACE(*args)))
+ {
+ if (mindex < bufferLength)
+ {
+ tokenBuffer[mindex] = *args;
+ mindex++;
+ }
+
+ args = &args[1];
+ }
+ }
+
+ // make sure string is zero terminated
+ if (bufferLength > 0)
+ {
+ tokenBuffer[__min(mindex, bufferLength - 1)] = IFX_SHELL_NULL_CHAR;
+ }
+
+ *argsPtr = Ifx_Shell_skipWhitespace(args);
+
+ return TRUE;
+}
+
+
+boolean Ifx_Shell_parseAddress(pchar *argsPtr, void **address)
+{
+ char buffer[32];
+ boolean result;
+
+ *address = 0;
+
+ if (Ifx_Shell_parseToken(argsPtr, buffer, Ifx_COUNTOF(buffer)) == FALSE)
+ {
+ result = FALSE;
+ }
+ else
+ {
+ result = (buffer[0] != IFX_SHELL_NULL_CHAR) && (sscanf(buffer, "%x ", (unsigned int *)address) == 1);
+ }
+
+ return result;
+}
+
+
+boolean Ifx_Shell_parseSInt32(pchar *argsPtr, sint32 *value)
+{
+ sint64 value64;
+ boolean result;
+
+ *value = 0;
+
+ if (Ifx_Shell_parseSInt64(argsPtr, &value64) == FALSE)
+ {
+ result = FALSE;
+ }
+ else
+ {
+ *value = (sint32)value64;
+ result = TRUE;
+ }
+
+ return result;
+}
+
+
+boolean Ifx_Shell_parseUInt32(pchar *argsPtr, uint32 *value, boolean hex)
+{
+ uint64 value64;
+ boolean result;
+
+ *value = 0;
+
+ if (Ifx_Shell_parseUInt64(argsPtr, &value64, hex) == FALSE)
+ {
+ result = FALSE;
+ }
+ else
+ {
+ *value = (uint32)value64;
+ result = TRUE;
+ }
+
+ return result;
+}
+
+
+boolean Ifx_Shell_parseSInt64(pchar *argsPtr, sint64 *value)
+{
+ char buffer[64];
+ boolean result;
+
+ *value = 0;
+
+ if (Ifx_Shell_parseToken(argsPtr, buffer, Ifx_COUNTOF(buffer)) == FALSE)
+ {
+ result = FALSE;
+ }
+ else
+ {
+ result = (buffer[0] != IFX_SHELL_NULL_CHAR) && (sscanf(buffer, IFX_SHELL_LLD, value) == 1);
+ }
+
+ return result;
+}
+
+
+boolean Ifx_Shell_parseUInt64(pchar *argsPtr, uint64 *value, boolean hex)
+{
+ char buffer[64];
+ boolean result;
+
+ *value = 0;
+
+ if (Ifx_Shell_parseToken(argsPtr, buffer, Ifx_COUNTOF(buffer)) == FALSE)
+ {
+ result = FALSE;
+ }
+ else
+ {
+ char *bufferPointer = buffer;
+
+ if ((buffer[0] == '0') && (buffer[1] == 'x'))
+ {
+ bufferPointer = &bufferPointer[2];
+ hex = TRUE;
+ }
+
+ if (hex != FALSE)
+ {
+ result = (bufferPointer[0] != IFX_SHELL_NULL_CHAR) && (sscanf(bufferPointer, IFX_SHELL_LLX, value) == 1);
+ }
+ else
+ {
+ result = (bufferPointer[0] != IFX_SHELL_NULL_CHAR) && (sscanf(bufferPointer, IFX_SHELL_LLU, value) == 1);
+ }
+ }
+
+ return result;
+}
+
+
+boolean Ifx_Shell_parseFloat64(pchar *argsPtr, float64 *value)
+{
+ char buffer[64];
+ boolean result;
+
+ *value = 0;
+
+ if (Ifx_Shell_parseToken(argsPtr, buffer, Ifx_COUNTOF(buffer)) == FALSE)
+ {
+ result = FALSE;
+ }
+ else
+ {
+ result = (buffer[0] != IFX_SHELL_NULL_CHAR) && (sscanf(buffer, "%lf ", value) == 1);
+ }
+
+ return result;
+}
+
+
+boolean Ifx_Shell_parseFloat32(pchar *argsPtr, float32 *value)
+{
+ char buffer[64];
+ boolean result;
+
+ *value = 0;
+
+ if (Ifx_Shell_parseToken(argsPtr, buffer, Ifx_COUNTOF(buffer)) == FALSE)
+ {
+ result = FALSE;
+ }
+ else
+ {
+ result = (buffer[0] != IFX_SHELL_NULL_CHAR) && (sscanf(buffer, "%f ", value) == 1);
+ }
+
+ return result;
+}
+
+
+const Ifx_Shell_Command *Ifx_Shell_commandFind(Ifx_Shell_CommandListConst commandList, pchar commandLine, pchar *args, uint32 *match)
+{
+ const Ifx_Shell_Command *command = commandList;
+ const Ifx_Shell_Command *result = NULL_PTR;
+ pchar cmdLineTemp = commandLine;
+ uint32 matchInit = 0;
+ uint32 index = 0;
+
+ boolean hasPrefix;
+
+ hasPrefix = (command->commandLine != NULL_PTR) && (command->call == NULL_PTR);
+ *match = 0;
+
+ while (command->commandLine != NULL_PTR)
+ {
+ pchar commandTemp = command->commandLine;
+ pchar commandLineTemp = cmdLineTemp;
+ char buffer[256];
+ uint32 matchCount = matchInit;
+
+ while (Ifx_Shell_matchCommand(&commandLineTemp, &commandTemp) != FALSE)
+ {
+ matchCount++;
+ }
+
+ if ((matchCount > *match) && (Ifx_Shell_parseToken(&commandTemp, buffer, Ifx_COUNTOF(buffer)) == FALSE))
+ {
+ if ((index == 0) && (command->call == NULL_PTR))
+ { /* List has a prefix */
+ cmdLineTemp = commandLineTemp;
+ matchInit = matchCount;
+ }
+
+ *match = matchCount;
+ *args = commandLineTemp;
+ result = command;
+ }
+ else
+ {
+ if ((index == 0) && hasPrefix)
+ {
+ /* Prefix does not match */
+ break;
+ }
+ }
+
+ command = &command[1];
+
+ index++;
+ }
+
+ return result;
+}
+
+
+const Ifx_Shell_Command *Ifx_Shell_commandListFind(Ifx_Shell *shell, pchar commandLine, pchar *args, Ifx_Shell_CommandListConst *commandList)
+{
+ int i;
+ const Ifx_Shell_Command *shellCommand = NULL_PTR;
+ const Ifx_Shell_Command *Command = NULL_PTR;
+ uint32 matchMax = 0;
+ uint32 match;
+
+ for (i = 0; i < IFX_CFG_SHELL_COMMAND_LISTS; i++)
+ {
+ if (shell->commandList[i] != NULL_PTR)
+ {
+ shellCommand = Ifx_Shell_commandFind(shell->commandList[i], commandLine, args, &match);
+
+ if ((shellCommand != NULL_PTR) && (match > matchMax))
+ {
+ matchMax = match;
+ Command = shellCommand;
+ *commandList = shell->commandList[i];
+ }
+ }
+ }
+
+ return Command;
+}
+
+
+void Ifx_Shell_execute(Ifx_Shell *shell, pchar commandLine)
+{
+ pchar args = NULL_PTR;
+ Ifx_Shell_CommandListConst commandList;
+ const Ifx_Shell_Command *shellCommand = Ifx_Shell_commandListFind(shell, commandLine, &args, &commandList);
+
+ if (shellCommand != NULL_PTR)
+ {
+ if (shellCommand->call == NULL_PTR)
+ {
+ Ifx_Shell_showHelp(commandLine, shell, shell->io);
+ }
+ else if (shellCommand->call(args, shellCommand->data, shell->io) != FALSE)
+ {
+ if (shell->control.sendResultCode != 0)
+ {
+ Ifx_Shell_writeResult(shell, Ifx_Shell_ResultCode_ok);
+ }
+ }
+ else
+ {
+ if (shell->control.sendResultCode != 0)
+ {
+ Ifx_Shell_writeResult(shell, Ifx_Shell_ResultCode_nok);
+ }
+ else if (shell->control.echoError != 0)
+ {
+ IfxStdIf_DPipe_print(shell->io, "\r\nShell command error: %s" ENDL, commandLine);
+ }
+ else
+ {}
+ }
+ }
+ else
+ {
+ if (commandLine[0] != IFX_SHELL_NULL_CHAR)
+ {
+ if (shell->control.sendResultCode != 0)
+ {
+ Ifx_Shell_writeResult(shell, Ifx_Shell_ResultCode_unknown);
+ }
+ else if (shell->control.echoError != 0)
+ {
+ IfxStdIf_DPipe_print(shell->io, "\r\nUnknown command: %s" ENDL, commandLine);
+ }
+ else
+ {}
+ }
+ }
+}
+
+
+/****************************************************************************************/
+/* Processes escape sequences, including handling command history. */
+/* The following escape sequences (prefix "ESC [") are supported: */
+/* A - up B - down C - right D - left */
+/* 1~ - HOME 2~ - INSERT 3~ - DELETE 4~ - END */
+/* */
+/* Parameters: */
+/* EscapeChar1 - First character to follow ESC [ */
+/* EscapeChar2 - Second character following ESC [ , if applicable */
+/* */
+/****************************************************************************************/
+void Ifx_Shell_cmdEscapeProcess(Ifx_Shell *shell, char EscapeChar1, char EscapeChar2)
+{
+ Ifx_Shell_CmdLine *Cmd = NULL_PTR; /* Command line editing state */
+ char *cmdStr = NULL_PTR; /* Cached pointer to command line being edited */
+ sint32 i = 0; /* Loop variable */
+
+ /* Validate parameters */
+ boolean result = (shell != NULL_PTR);
+
+ IFX_ASSERT(IFX_VERBOSE_LEVEL_ERROR, result != FALSE);
+
+ if (result == FALSE)
+ {
+ return; /* ERROR CASE - no thread data available! */
+ }
+
+ /* Cache command state and command line pointer */
+ Cmd = &shell->cmd;
+ cmdStr = Cmd->cmdStr;
+
+ /* Validate command line state */
+ IFX_ASSERT(IFX_VERBOSE_LEVEL_ERROR, cmdStr != NULL_PTR);
+ IFX_ASSERT(IFX_VERBOSE_LEVEL_ERROR, Cmd->cursor < IFX_CFG_SHELL_CMD_LINE_SIZE);
+ IFX_ASSERT(IFX_VERBOSE_LEVEL_ERROR, Cmd->length < IFX_CFG_SHELL_CMD_LINE_SIZE);
+
+ /* Switch on first character after ESC [ */
+ switch (EscapeChar1)
+ {
+ case 'A': /* Up arrow */
+
+ if (Cmd->historyItem == IFX_SHELL_CMD_HISTORY_NO_ITEM)
+ {
+ /* Not using list at the moment - take most recent item [0] */
+ Cmd->historyItem = 0;
+ }
+ else
+ {
+ if (Cmd->historyItem < (IFX_CFG_SHELL_CMD_HISTORY_SIZE - 1))
+ {
+ /* If not already at oldest, go back one in list */
+ Cmd->historyItem++;
+ }
+ }
+
+ /* Copy text into buffer */
+ strncpy(cmdStr, shell->cmdHistory[Cmd->historyItem], IFX_CFG_SHELL_CMD_LINE_SIZE);
+
+ /* echo to screen if requested */
+ if (shell->control.echo != 0)
+ {
+ IFX_SHELL_WRITE_BACKSPACES(Cmd->cursor) /* Move cursor back to start */
+ IFX_SHELL_WRITE_SPACES(Cmd->length) /* Overwrite text with spaces */
+ IFX_SHELL_WRITE_BACKSPACES(Cmd->length) /* Move cursor back to start */
+ IfxStdIf_DPipe_print(shell->io, cmdStr); /* Copy buffer to screen */
+ }
+
+ Cmd->cursor = (Ifx_SizeT)strlen(cmdStr); /* Store cursor position */
+ Cmd->length = Cmd->cursor; /* Store command line length */
+ Cmd->historyAdd = FALSE; /* Don't add back to history unless modified */
+ break;
+
+ case 'B': /* Down arrow */
+
+ if ((Cmd->historyItem == IFX_SHELL_CMD_HISTORY_NO_ITEM) || (Cmd->historyItem == 0))
+ {
+ /* Not using list at the moment, or have dropped off the end - just clear command line */
+ if (shell->control.echo != 0)
+ {
+ IFX_SHELL_WRITE_BACKSPACES(Cmd->cursor) /* Move cursor back to start */
+ IFX_SHELL_WRITE_SPACES(Cmd->length) /* Overwrite text with spaces */
+ IFX_SHELL_WRITE_BACKSPACES(Cmd->length) /* Move cursor back to start */
+ }
+
+ Cmd->length = 0; /* Reset command line length */
+ Cmd->cursor = 0;
+ Cmd->historyItem = IFX_SHELL_CMD_HISTORY_NO_ITEM; /* Ensure we are not using list */
+ }
+ else
+ {
+ /* Within list - move to more recent entry */
+ Cmd->historyItem--;
+
+ /* Copy text into buffer */
+ strncpy(cmdStr, shell->cmdHistory[Cmd->historyItem], IFX_CFG_SHELL_CMD_LINE_SIZE);
+
+ if (shell->control.echo != 0)
+ {
+ IFX_SHELL_WRITE_BACKSPACES(Cmd->cursor) /* Move cursor back to start */
+ IFX_SHELL_WRITE_SPACES(Cmd->length) /* Overwrite text with spaces */
+ IFX_SHELL_WRITE_BACKSPACES(Cmd->length) /* Move cursor back to start */
+ IfxStdIf_DPipe_print(shell->io, cmdStr); /* Copy buffer to screen */
+ }
+
+ Cmd->cursor = (Ifx_SizeT)strlen(cmdStr); /* Store cursor position */
+ Cmd->length = Cmd->cursor; /* Store command line length */
+ }
+
+ Cmd->historyAdd = FALSE;
+ break;
+
+ case 'C': /* Right arrow */
+
+ if (Cmd->cursor < Cmd->length)
+ {
+ /* Move cursor one place to right */
+ IFX_SHELL_IF_ECHO(IfxStdIf_DPipe_print(shell->io, "%c", cmdStr[Cmd->cursor])) Cmd->cursor++;
+ }
+
+ break;
+
+ case 'D': /* Left arrow */
+
+ if (Cmd->cursor > 0)
+ {
+ /* Move cursor one place to left */
+ IFX_SHELL_IF_ECHO(IfxStdIf_DPipe_print(shell->io, "\b")) Cmd->cursor--;
+ }
+
+ break;
+
+ default:
+ break;
+ }
+
+ /* If second character after ESC [ is ~ then switch on number */
+ if (EscapeChar2 == '~')
+ {
+ switch (EscapeChar1)
+ {
+ case '1': /* HOME - move to start of buffer */
+
+ if (Cmd->cursor > 0)
+ {
+ IFX_SHELL_WRITE_BACKSPACES(Cmd->cursor) Cmd->cursor = 0;
+ }
+
+ break;
+
+ case '2': /* INSERT - insert blank character at cursor and move all remaining characters right one */
+
+ if ((Cmd->cursor < Cmd->length) && (Cmd->length < (IFX_CFG_SHELL_CMD_LINE_SIZE - 1)))
+ {
+ /* Update on screen */
+ if (shell->control.echo != FALSE)
+ {
+ /* write over duplicated character at cursor */
+ IfxStdIf_DPipe_print(shell->io, " ");
+
+ /* Update line with new characters */
+ for (i = Cmd->cursor; i < Cmd->length; i++)
+ {
+ IfxStdIf_DPipe_print(shell->io, "%c", cmdStr[i]);
+ }
+
+ /* Move cursor back to new place */
+ IFX_SHELL_WRITE_BACKSPACES((Cmd->length + 1) - Cmd->cursor)
+ }
+
+ /* Update in command line variable */
+ for (i = Cmd->length; i > Cmd->cursor; i--)
+ {
+ cmdStr[i] = cmdStr[i - 1]; /* Shuffle text right */
+ }
+
+ cmdStr[Cmd->length + 1] = IFX_SHELL_NULL_CHAR; /* Terminate string at end of longer string */
+ cmdStr[Cmd->cursor] = ' '; /* Blank character at cursor */
+
+ Cmd->length++; /* Now one character longer */
+ }
+
+ break;
+
+ case '3': /* DELETE - delete character to right and move all remaining characters left one */
+
+ if (Cmd->cursor < Cmd->length)
+ {
+ /* Update on screen */
+ if (shell->control.echo != 0)
+ {
+ for (i = Cmd->cursor; i < (Cmd->length - 1); i++)
+ {
+ /* Update line with new characters */
+ IfxStdIf_DPipe_print(shell->io, "%c", cmdStr[i + 1]);
+ }
+
+ /* write over duplicated character at end */
+ IfxStdIf_DPipe_print(shell->io, " ");
+
+ /* Move cursor back to right place */
+ IFX_SHELL_WRITE_BACKSPACES(Cmd->length - Cmd->cursor)
+ }
+
+ /* Update in command line variable. Shuffle text left */
+ strncpy(&cmdStr[Cmd->cursor], &cmdStr[Cmd->cursor + 1], Cmd->length - Cmd->cursor - 1);
+
+ cmdStr[Cmd->length - 1] = IFX_SHELL_NULL_CHAR; /* Terminate string at end of shorter string */
+ Cmd->length--; /* Now one character shorter */
+ }
+
+ break;
+
+ case '4': /* END - ensure cursor is at end */
+
+ while (Cmd->cursor < Cmd->length)
+ {
+ IFX_SHELL_IF_ECHO(IfxStdIf_DPipe_print(shell->io, "%c", cmdStr[Cmd->cursor])) Cmd->cursor++;
+ }
+
+ break;
+
+ default:
+ break;
+ }
+ }
+}
+
+
+void Ifx_Shell_enable(Ifx_Shell *shell)
+{
+ // Clear the Rx buffer!
+ IfxStdIf_DPipe_clearRx(shell->io);
+ // Enable the shell
+ shell->control.enabled = 1;
+}
+
+
+void Ifx_Shell_disable(Ifx_Shell *shell)
+{
+ shell->control.enabled = 0;
+}
+
+
+void Ifx_Shell_printSyntax(const Ifx_Shell_Syntax *syntaxList, IfxStdIf_DPipe *io)
+{
+ const Ifx_Shell_Syntax *syntax = syntaxList;
+
+ while (syntax->syntax != NULL_PTR)
+ {
+ IfxStdIf_DPipe_print(io, "Syntax : %s" ENDL, syntax->syntax);
+ IfxStdIf_DPipe_print(io, " > %s" ENDL, syntax->description);
+ syntax = &syntax[1];
+ }
+}
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Comm/Ifx_Shell.h b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Comm/Ifx_Shell.h
new file mode 100644
index 0000000..5d73d4c
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Comm/Ifx_Shell.h
@@ -0,0 +1,474 @@
+/**
+ * \file Ifx_Shell.h
+ * \brief Shell functions.
+ * \ingroup library_srvsw_sysse_comm_shell
+ *
+ * \version disabled
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ * \defgroup library_srvsw_sysse_comm_shell Shell
+ * This module implements the Shell functions.
+ * It parses a command line and call the corresponding command execution.
+ * Multiple command list can be used in parallel.
+ *
+ * Only full command match is accepted.
+ *
+ * New feature / change:
+ * - Prefix can be defined for each command list
+ * - Help for a single command is displayed with "help "
+ * - help for a command list is displayed with "help "
+ * - command short cut is not allowed
+ * - command with identical start option "opt1 opt2" and "opt1 opt3" are accepted, and root to different handlers
+ * - Enhanced help info print
+ *
+ * Help text xyntax:
+ * - /p indicates a parameter description, can be multi-line, lines must be separated with ENDL
+ * - /s Indicates a syntax help
+ *
+ * Example of help list:
+ * \code
+ * Ifx_Shell_Command Ifx_g_OsciShell_commands[] =
+ * {
+ * {IFX_OSCI_SHELL_PREFIX, " : Oscilloscope functions"
+ * , NULL_PTR, NULL_PTR },
+ * {"run", " : run the oscilloscope"ENDL
+ * "/s run [single|auto|normal]"
+ * , NULL_PTR, &Ifx_OsciShell_run },
+ * {"stop", " : stop oscilloscope"
+ * , NULL_PTR, &Ifx_OsciShell_stop },
+ * {"trigger", " : trigger settings"ENDL
+ * "/s trigger [force|single|level |raising|falling|source |interval ]"ENDL
+ * "/p force: Force the trigger"ENDL
+ * "/p single: Single the trigger"ENDL
+ * "/p level : Set trigger level to value"ENDL
+ * "/p [raising|falling]: Set trigger to raising or falling edges"ENDL
+ * "/p source : Set trigger channel number"ENDL
+ * " can be obtained with 'channel' command"ENDL
+ * "/p interval : Set sampling interval to value"
+ *
+ * , NULL_PTR, &Ifx_OsciShell_trigger },
+ * {"status", " : display status"
+ * , NULL_PTR, &Ifx_OsciShell_status },
+ * {"channel", " : channel information"ENDL
+ * "/s channel: Show the channels information"ENDL
+ * "/s channel : Assign a signal to a channel"
+ * , NULL_PTR, &Ifx_OsciShell_channel },
+ * {"analyze", " : signal analysis of a ch"ENDL
+ * "/s analyze : analyze the input channel "
+ * , NULL_PTR, &Ifx_OsciShell_analyze },
+ * {"simulate", " : simulate a signal"ENDL
+ * "/s simulate : Simulate a signal generation"ENDL
+ * "/p : {0 .. Channel count}"ENDL
+ * "/p : {add,sub,mul,clr}"ENDL
+ * "/p : {sine,square}"ENDL
+ * "/p : -INF .. INF"ENDL
+ * "/p : -INF .. INF"ENDL
+ * "/p : -INF .. INF"ENDL
+ * "/p : 0 .. 360 [degree]"ENDL
+ * "/s simulate atan : Compute atan(ych/xch) and store in channel "
+ * , NULL_PTR, &Ifx_OsciShell_simulate},
+ * {"dump", " : dump values (all channels)"ENDL
+ * "/s dump [hex]"ENDL
+ * "/p : Dump the values of the channel "ENDL
+ * "/p hex: If hex is specified, values will be in hexadecimal"
+ * , NULL_PTR, &Ifx_OsciShell_dump },
+ * IFX_SHELL_COMMAND_LIST_END,
+ * };
+ * \endcode
+ *
+ * To enable help command, include the below command in the main command list
+ * {"help", SHELL_HELP_DESCRIPTION_TEXT , &\, &Ifx_Shell_showHelp, },
+ *
+ * \ingroup library_srvsw_sysse_comm
+ *
+ */
+
+#ifndef IFX_SHELL_H
+#define IFX_SHELL_H 1
+//----------------------------------------------------------------------------------------
+#include "StdIf/IfxStdIf_DPipe.h"
+#include "Ifx_Cfg.h"
+//----------------------------------------------------------------------------------------
+#define IFX_SHELL_NULL_CHAR '\0'
+
+#ifndef IFX_CFG_SHELL_CMD_HISTORY_SIZE
+#define IFX_CFG_SHELL_CMD_HISTORY_SIZE (10) /**<\brief Number of commands to store in history */
+#endif
+
+#ifndef IFX_CFG_SHELL_CMD_LINE_SIZE
+#define IFX_CFG_SHELL_CMD_LINE_SIZE (128) /**<\brief max command line IFX_CFG_SHELL_CMD_LINE_SIZE - 1 */
+#endif
+
+#ifndef IFX_CFG_SHELL_COMMAND_LISTS
+#define IFX_CFG_SHELL_COMMAND_LISTS (1) /**<\brief Number of command lists */
+#endif
+
+#ifndef IFX_CFG_SHELL_PROMPT
+#define IFX_CFG_SHELL_PROMPT "Shell>" /**<\brief Shell prompt */
+#endif
+
+#define SHELL_HELP_DESCRIPTION_TEXT \
+ " : Display command list, and command help."ENDL \
+ "/s help: show all commands"ENDL \
+ "/s help : show the command details"
+
+/** \brief Marker for end of command list, the end of list is detected by commandLine=NULL */
+#define IFX_SHELL_COMMAND_LIST_END {0, 0, 0, 0}
+
+/** \brief Marker for end of syntax list */
+#define IFX_SHELL_SYNTAX_LIST_END {0, 0}
+
+/** \brief Signifies no item in use in command history list */
+#define IFX_SHELL_CMD_HISTORY_NO_ITEM (-1)
+//----------------------------------------------------------------------------------------
+/** \brief Result code definition used after each executed Shell command */
+typedef enum
+{
+ Ifx_Shell_ResultCode_unknown = (128),
+ Ifx_Shell_ResultCode_nok = (129),
+ Ifx_Shell_ResultCode_undefined = (130),
+ Ifx_Shell_ResultCode_ok = (255)
+} Ifx_Shell_ResultCode;
+
+/** \brief Definition of a callback function which handles a Shell command */
+typedef boolean (*Ifx_Shell_Call)(pchar args, void *data, IfxStdIf_DPipe *io);
+
+/** \brief Shell command object */
+typedef struct
+{
+ pchar commandLine;
+ pchar help;
+ void *data;
+ Ifx_Shell_Call call;
+} Ifx_Shell_Command;
+
+/** \brief Command line editing state */
+typedef struct
+{
+ char *cmdStr; /**< \brief Pointer to current string containing command line as so far processed */
+ Ifx_SizeT cursor; /**< \brief Pointer to variable containing position of cursor in so-far-processed command line */
+ Ifx_SizeT length; /**< \brief Pointer to variable containing total length of command line */
+ boolean historyAdd; /**< \brief If TRUE, when Enter is pressed, the current cmdLine should be added to the command history (in parent) */
+ Ifx_SizeT historyItem; /**< \brief Item ID in command history list, or IFX_SHELL_CMD_HISTORY_NO_ITEM if not using list (e.g. new command) */
+} Ifx_Shell_CmdLine;
+
+/** \brief Shell command processing state */
+typedef enum
+{
+ IFX_SHELL_CMD_STATE_NORMAL, /**< \brief Normal - no special sequences being processed */
+ IFX_SHELL_CMD_STATE_ESCAPE, /**< \brief Escape character has been pressed */
+ IFX_SHELL_CMD_STATE_ESCAPE_BRACKET, /**< \brief ESC [ pressed */
+ IFX_SHELL_CMD_STATE_ESCAPE_BRACKET_NUMBER /**< \brief ESC [ (number) pressed */
+} Ifx_Shell_CmdState;
+
+/** \brief Shell protocol configuration */
+typedef struct
+{
+ boolean (*start)(void *protocol, IfxStdIf_DPipe *io);
+ void (*execute)(void *protocol);
+ void (*onStart)(void *protocol, void *data);
+ void *onStartData;
+ void *object;
+ boolean started;
+} Ifx_Shell_Protocol;
+
+/** \brief Shell control flags */
+typedef struct
+{
+ uint16 showPrompt : 1;
+ uint16 enabled : 1;
+ uint16 sendResultCode : 1;
+ uint16 echo : 1;
+ uint16 echoError : 1;
+} Ifx_Shell_Flags;
+
+/** \brief internal Shell run-time data */
+typedef struct
+{
+ char echo[2];
+ char inputbuffer[IFX_CFG_SHELL_CMD_LINE_SIZE + 1];
+ char cmdStr[IFX_CFG_SHELL_CMD_LINE_SIZE];
+ Ifx_Shell_CmdState cmdState;
+ char escBracketNum;
+} Ifx_Shell_Runtime;
+
+typedef Ifx_Shell_Command *Ifx_Shell_CommandList;
+typedef const Ifx_Shell_Command *Ifx_Shell_CommandListConst;
+/**
+ * \brief Shell object definition
+ */
+typedef struct
+{
+ IfxStdIf_DPipe *io; /**< \brief Pointer to IfxStdIf_DPipe object used by the Shell */
+
+ Ifx_Shell_Flags control; /**< \brief control flags */
+
+ /** \brief Array of pointers to the history entries */
+ char *cmdHistory[IFX_CFG_SHELL_CMD_HISTORY_SIZE];
+
+ /** \brief Current status of command line editing (saves passing many parameters around) */
+ Ifx_Shell_CmdLine cmd;
+
+ Ifx_Shell_Runtime locals; /**< \brief Runtime data */
+
+ /** \brief Array of pointers to command list. The pointed location shall be constant
+ * during Shell lifetime, e.g. stored in non-volatile memory or as global variable
+ *
+ * The 1st item in the list is use as a group command prefix if its "call" parameter is NULL pointer, else it is use as other entries.
+ * In case "call" is NULL, the corresponding 'data' is ignored, and the 'help' is displayed.
+ *
+ **/
+ Ifx_Shell_CommandListConst commandList[IFX_CFG_SHELL_COMMAND_LISTS];
+
+ Ifx_Shell_Protocol protocol; /**< \brief Protocol handler data */
+} Ifx_Shell;
+
+/**
+ * \brief Shell configuration.
+ */
+typedef struct
+{
+ IfxStdIf_DPipe *standardIo; /**<\brief Pointer to a IfxStdIf_DPipe object used by the Shell */
+ boolean echo; /**<\brief Specifies whether each command shall be echoed back to user */
+ boolean showPrompt; /**<\brief Specifies whether the IFX_CFG_SHELL_PROMPT shall be displayed after each command */
+ boolean sendResultCode; /**<\brief Specifies whether the Ifx_Shell_ResultCode shall be sent to user */
+ Ifx_Shell_CommandListConst commandList[IFX_CFG_SHELL_COMMAND_LISTS]; /**< \brief Specifies pointer to the command list */
+ Ifx_Shell_Protocol protocol; /**<\brief Configuration for the Ifx_Shell_Protocol */
+} Ifx_Shell_Config;
+
+/**
+ * \brief Shell Syntax Description.
+ */
+typedef struct
+{
+ pchar syntax; /**<\brief syntax */
+ pchar description; /**<\brief description */
+} Ifx_Shell_Syntax;
+
+//----------------------------------------------------------------------------------------
+/** \addtogroup library_srvsw_sysse_comm_shell
+ * \{ */
+
+/** \name Basic functionality
+ * \{ */
+
+/** Set the config default parameter
+ *
+ * \param config Pointer to the configuration structure to be initialized
+ */
+void Ifx_Shell_initConfig(Ifx_Shell_Config *config);
+
+/**
+ * \brief Initialize the shell
+ * \param shell Pointer to the \ref Ifx_Shell object
+ * \param config Pointer to the configuration structure
+ */
+IFX_EXTERN boolean Ifx_Shell_init(Ifx_Shell *shell, const Ifx_Shell_Config *config);
+
+/**
+ * \brief Deinitialise the shell
+ * \param shell Pointer to the \ref Ifx_Shell object
+ */
+IFX_EXTERN void Ifx_Shell_deinit(Ifx_Shell *shell);
+
+/**
+ * \brief Clear the receive buffer and enable the shell
+ * \param shell Pointer to the \ref Ifx_Shell object
+ */
+IFX_EXTERN void Ifx_Shell_enable(Ifx_Shell *shell);
+
+/**
+ * \brief Disable the shell
+ * \param shell Pointer to the \ref Ifx_Shell object
+ */
+IFX_EXTERN void Ifx_Shell_disable(Ifx_Shell *shell);
+
+/**
+ * \brief Process the shell.
+ *
+ * This function shall be called within a loop or periodic timer to guarantee the correct
+ * processing of the incoming/received data.
+ *
+ * \param shell Pointer to the \ref Ifx_Shell object
+ */
+IFX_EXTERN void Ifx_Shell_process(Ifx_Shell *shell);
+
+/** \} */
+//----------------------------------------------------------------------------------------
+/** \name Parsing functions
+ * \{ */
+
+/**
+ * \brief Within the context of Shell.call, skip the whitespaces of the args string.
+ * \param args Pointer to the original string
+ * \return Pointer to the string after skipping the whitespaces
+ */
+IFX_EXTERN pchar Ifx_Shell_skipWhitespace(pchar args);
+
+/**
+ * \brief Match string pointed by the *argsPtr with a given token
+ * \param argsPtr Pointer to the argument null-terminated string
+ * \param token Pointer to the token string to match
+ * \retval TRUE if the given token match with the string pointed by argsPtr
+ */
+IFX_EXTERN boolean Ifx_Shell_matchToken(pchar *argsPtr, pchar token);
+
+/**
+ * \brief Parse a token
+ * Return the next token in tokenBuffer and move the argsPtr pointer after this token
+ * \param argsPtr Pointer to the argument null-terminated string
+ * \param tokenBuffer Pointer to the value storage
+ * \param bufferLength Maximum parsing length
+ */
+IFX_EXTERN boolean Ifx_Shell_parseToken(pchar *argsPtr, char *tokenBuffer, int bufferLength);
+
+/**
+ * \brief Parse an address
+ * \param argsPtr Pointer to the argument null-terminated string
+ * \param address Pointer to the value storage
+ */
+IFX_EXTERN boolean Ifx_Shell_parseAddress(pchar *argsPtr, void **address);
+
+/**
+ * \brief Parse a signed 32-bit integer value
+ * \param argsPtr Pointer to the argument null-terminated string
+ * \param value Pointer to the value storage
+ */
+IFX_EXTERN boolean Ifx_Shell_parseSInt32(pchar *argsPtr, sint32 *value);
+
+/**
+ * \brief Parse an unsigned 32-bit integer value
+ * \param argsPtr Pointer to the argument null-terminated string
+ * \param value Pointer to the value storage
+ * \param hex if TRUE, hex parsing will be done, else decimal parsing
+ */
+IFX_EXTERN boolean Ifx_Shell_parseUInt32(pchar *argsPtr, uint32 *value, boolean hex);
+
+/**
+ * \brief Parse a signed 64-bit integer value
+ * \param argsPtr Pointer to the argument null-terminated string
+ * \param value Pointer to the value storage
+ */
+IFX_EXTERN boolean Ifx_Shell_parseSInt64(pchar *argsPtr, sint64 *value);
+
+/**
+ * \brief Parse an unsigned 64-bit integer value
+ * \param argsPtr Pointer to the argument null-terminated string
+ * \param value Pointer to the value storage
+ * \param hex if TRUE, hex parsing will be done, else decimal parsing
+ */
+IFX_EXTERN boolean Ifx_Shell_parseUInt64(pchar *argsPtr, uint64 *value, boolean hex);
+
+/**
+ * \brief Parse a 64-bit (double precision) floating-point value
+ * \param argsPtr Pointer to the argument null-terminated string
+ * \param value Pointer to the value storage
+ */
+IFX_EXTERN boolean Ifx_Shell_parseFloat64(pchar *argsPtr, float64 *value);
+
+/**
+ * \brief Parse a 32-bit (single precision) floating-point value
+ * \param argsPtr Pointer to the argument null-terminated string
+ * \param value Pointer to the value storage
+ */
+IFX_EXTERN boolean Ifx_Shell_parseFloat32(pchar *argsPtr, float32 *value);
+
+/** \} */
+//----------------------------------------------------------------------------------------
+/** \name Command list functions
+ * \{ */
+
+/**
+ * \brief Find command in command List
+ * \param commandList Pointer to the first entry of an array of \ref Ifx_Shell_Command
+ * \param commandLine Pointer to null-terminated string containings the command to search.
+ * \param args Pointer to the argument null-terminated string
+ * \param match Return the number of arguments that matches
+ */
+IFX_EXTERN const Ifx_Shell_Command *Ifx_Shell_commandFind(Ifx_Shell_CommandListConst commandList, pchar commandLine, pchar *args, uint32 *match);
+
+/**
+ * \brief Implementation of \ref Ifx_Shell_Call. Show the help menu from single command list.
+ * \param commandList Pointer to an array of Ifx_Shell_Command
+ * \param io Pointer to the IfxStdIf_DPipe object
+ * \param briefOnly if TRUE, show only the brief description, else show the full description
+ * \param singleCommand If TRUE, only show the 1st command pointed by commandList, else show the full list
+ */
+IFX_EXTERN boolean Ifx_Shell_showHelpSingle(Ifx_Shell_CommandListConst commandList, IfxStdIf_DPipe *io, boolean briefOnly, boolean singleCommand);
+
+/**
+ * \brief Implementation of \ref Ifx_Shell_Call. Show the help menu and list of commands.
+ * \param args The argument null-terminated string
+ * \param shellPtr Pointer to a Shell object
+ * \param io Pointer to \ref IfxStdIf_DPipe object
+ */
+IFX_EXTERN boolean Ifx_Shell_showHelp(pchar args, void *shellPtr, IfxStdIf_DPipe *io);
+
+/**
+ * \brief Implementation of \ref Ifx_Shell_Call. print the syntax.
+ * \param syntaxList Pointer to syntax list
+ * \param io Pointer to \ref IfxStdIf_DPipe object
+ */
+IFX_EXTERN void Ifx_Shell_printSyntax(const Ifx_Shell_Syntax *syntaxList, IfxStdIf_DPipe *io);
+
+/** \} */
+//----------------------------------------------------------------------------------------
+/** \name Sub protocol functions
+ * \{ */
+
+/**
+ * \brief Implementation of \ref Ifx_Shell_Call. Start the Shell protocol.
+ * \param args The argument null-terminated string
+ * \param data Pointer to \ref Ifx_Shell object
+ * \param io Pointer to \ref IfxStdIf_DPipe object
+ */
+IFX_EXTERN boolean Ifx_Shell_protocolStart(pchar args, void *data, IfxStdIf_DPipe *io);
+
+/**
+ * \brief Implementation of \ref Ifx_Shell_Call. Start the ShellBb protocol.
+ * \param args The argument null-terminated string
+ * \param data Pointer to \ref Ifx_Shell object
+ * \param io Pointer to \ref IfxStdIf_DPipe object
+ */
+IFX_EXTERN boolean Ifx_Shell_bbProtocolStart(pchar args, void *data, IfxStdIf_DPipe *io);
+
+/** \} */
+//----------------------------------------------------------------------------------------
+/** \} */
+
+#endif
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Comm/info.dox b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Comm/info.dox
new file mode 100644
index 0000000..49d0723
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Comm/info.dox
@@ -0,0 +1,4 @@
+/**
+ * \defgroup library_srvsw_sysse_comm Communication
+ * \ingroup library_srvsw_sysse
+ */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/General/Ifx_GlobalResources.c b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/General/Ifx_GlobalResources.c
new file mode 100644
index 0000000..1dc58e3
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/General/Ifx_GlobalResources.c
@@ -0,0 +1,168 @@
+/**
+ * \file Ifx_GlobalResources.h
+ * \brief Handling of global resources
+ *
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ * $Date: 2014-02-27 20:08:36 GMT$
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ */
+
+#include "Ifx_GlobalResources.h"
+/** \brief Global resource object */
+typedef struct
+{
+ const Ifx_GlobalResources_Item *table; /**< \brief Pointer to the global resource table */
+ sint32 size; /**< \brief Size of the global resource table */
+} Ifx_GlobalResources;
+
+#if IFX_CFG_GLOBAL_RESOURCES_ENABLED
+
+Ifx_GlobalResources ifx_GlobalResource;
+#endif
+
+void *Ifx_GlobalResources_get(sint32 id)
+{
+ void *result;
+
+#if IFX_CFG_GLOBAL_RESOURCES_ENABLED
+
+ if (id < ifx_GlobalResource.size)
+ {
+ result = ifx_GlobalResource.table[id].resource;
+ }
+ else
+ {
+ result = NULL_PTR;
+ }
+
+#else
+ result = NULL_PTR;
+
+#endif
+
+ return result;
+}
+
+
+sint32 Ifx_GlobalResources_getIndex(void *resource)
+{
+ sint32 id = -1;
+
+#if IFX_CFG_GLOBAL_RESOURCES_ENABLED
+ int i;
+
+ for (i = 0; i < ifx_GlobalResource.size; i++)
+ {
+ if (resource == ifx_GlobalResource.table[i].resource)
+ {
+ id = i;
+ }
+ else
+ {}
+ }
+
+#else
+#endif
+
+ return id;
+}
+
+
+const Ifx_GlobalResources_Item *Ifx_GlobalResources_getItem(sint32 id)
+{
+ const Ifx_GlobalResources_Item *result;
+
+#if IFX_CFG_GLOBAL_RESOURCES_ENABLED
+
+ if (id < ifx_GlobalResource.size)
+ {
+ result = &ifx_GlobalResource.table[id];
+ }
+ else
+ {
+ result = NULL_PTR;
+ }
+
+#else
+ result = NULL_PTR;
+
+#endif
+
+ return result;
+}
+
+
+pchar Ifx_GlobalResources_getName(sint32 id)
+{
+ pchar name;
+
+#if IFX_CFG_GLOBAL_RESOURCES_ENABLED
+
+ if (id < ifx_GlobalResource.size)
+ {
+ name = ifx_GlobalResource.table[id].name;
+ }
+ else
+ {
+ name = "unknown";
+ }
+
+#else
+ name = "unknown";
+
+#endif
+
+ return name;
+}
+
+
+boolean Ifx_GlobalResources_init(const Ifx_GlobalResources_Item *table, uint32 size)
+{
+ boolean result;
+
+#if IFX_CFG_GLOBAL_RESOURCES_ENABLED
+ ifx_GlobalResource.table = table;
+ ifx_GlobalResource.size = size;
+ result = TRUE;
+#else
+ result = FALSE;
+
+#endif
+
+ return result;
+}
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/General/Ifx_GlobalResources.h b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/General/Ifx_GlobalResources.h
new file mode 100644
index 0000000..9c8790c
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/General/Ifx_GlobalResources.h
@@ -0,0 +1,107 @@
+/**
+ * \file Ifx_GlobalResources.h
+ * \brief Handling of global resources
+ *
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ * $Date: 2014-02-28 14:15:39 GMT$
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ * \defgroup library_srvsw_sysse_general_globalresources Global resources
+ * This module implements the global resources handling
+ * \ingroup library_srvsw_sysse_general
+ */
+
+#ifndef IFX_GLOBALRESOURCES_H
+#define IFX_GLOBALRESOURCES_H 1
+
+#include "Ifx_Cfg.h"
+#include "Cpu/Std/Ifx_Types.h"
+
+#ifndef IFX_CFG_GLOBAL_RESOURCES_ENABLED
+#define IFX_CFG_GLOBAL_RESOURCES_ENABLED (0)
+#endif
+
+typedef struct
+{
+ void *resource;
+ pchar name;
+} Ifx_GlobalResources_Item;
+
+/** \addtogroup library_srvsw_sysse_general_globalresources
+ * \{ */
+/** Return a pointer to the global resource
+ *
+ * \param id index of the Ifx_GlobalResources_Item in the table, the index starts with 0
+ *
+ * \return return Ifx_GlobalResources_Item.resource
+ */
+IFX_EXTERN void *Ifx_GlobalResources_get(sint32 id);
+
+/** \brief Returns the global resource index.
+ *
+ * \return Returns the global resource index, -1 if not found
+ */
+IFX_EXTERN sint32 Ifx_GlobalResources_getIndex(void *resource);
+
+/** Return a pointer to the global resource item
+ *
+ * \param id index of the Ifx_GlobalResources_Item in the table, the index starts with 0
+ *
+ * \return return the Ifx_GlobalResources_Item
+ */
+IFX_EXTERN const Ifx_GlobalResources_Item *Ifx_GlobalResources_getItem(sint32 id);
+
+/** Return a the resource name as an NULL terminated string
+ *
+ * \param id index of the Ifx_GlobalResources_Item in the table, the index starts with 0
+ *
+ * \return return Ifx_GlobalResources_Item.name
+ */
+IFX_EXTERN pchar Ifx_GlobalResources_getName(sint32 id);
+
+/** Initialize the global resource handler
+ *
+ * \param table pointer to an array of Ifx_GlobalResources_Item
+ * \param size number of item in the table corresponds to sizeof(table)
+ *
+ * return returns TRUE in case of success else FALSE
+ *
+ */
+IFX_EXTERN boolean Ifx_GlobalResources_init(const Ifx_GlobalResources_Item *table, uint32 size);
+/** \} */
+
+#endif /* IFX_GLOBALRESOURCES_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/General/info.dox b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/General/info.dox
new file mode 100644
index 0000000..7c0b750
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/General/info.dox
@@ -0,0 +1,4 @@
+/**
+ * \defgroup library_srvsw_sysse_general General
+ * \ingroup library_srvsw_sysse
+ */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Math/Ifx_AngleTrkF32.c b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Math/Ifx_AngleTrkF32.c
new file mode 100644
index 0000000..4274403
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Math/Ifx_AngleTrkF32.c
@@ -0,0 +1,464 @@
+/**
+ * \file Ifx_AngleTrkF32.c
+ * \brief Angle-tracking observer for sin/cos analog position sensor
+ *
+ *
+ * \version disabled
+ * \copyright Copyright (c) 2019 Infineon Technologies AG. All rights reserved.
+ *
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ */
+
+//________________________________________________________________________________________
+// INCLUDES
+
+#include "Ifx_AngleTrkF32.h"
+#include
+#include "string.h"
+#include "Ifx_LutAtan2F32.h"
+
+//________________________________________________________________________________________
+// LOCAL DEFINITIONS
+
+#define IFX_ANGLETRKF32_ATAN2F Ifx_LutAtan2F32_float32
+
+//________________________________________________________________________________________
+// LOCAL FUNCTION PROTOTYPES
+
+void Ifx_AngleTrkF32_setUserSampling(Ifx_AngleTrkF32 *aObsv, float32 Ts);
+
+//________________________________________________________________________________________
+// GLOBAL VARIABLES
+
+//________________________________________________________________________________________
+// LOCAL VARIABLES
+
+//________________________________________________________________________________________
+// LOCAL FUNCTION IMPLEMENTATIONS
+
+IFX_INLINE float32 Ifx_AngleTrkF32_bound(float32 angle, float32 periodPerRotation)
+{
+ IFX_UNUSED_PARAMETER(periodPerRotation);
+ float32 fullPeriod = 2 * IFX_PI;
+
+ if (angle >= (fullPeriod / 2))
+ {
+ angle = angle - fullPeriod;
+ }
+ else if (angle < (-fullPeriod / 2))
+ {
+ angle = angle + fullPeriod;
+ }
+ else
+ {}
+
+ return angle;
+}
+
+
+IFX_INLINE float32 Ifx_AngleTrkF32_boundInput(float32 input)
+{
+ return Ifx_AngleTrkF32_bound(input, 1);
+}
+
+
+float32 round_f(float32 val)
+{
+ /*lint -e632 -e633 -e524*/
+ sint32 val_i = (sint32)val;
+
+ /*lint +e632 +e633 +e524*/
+ if ((val - (float32)val_i) > 0.5)
+ {
+ val = (float32)(val_i + 1);
+ }
+ else
+ {
+ val = (float32)val_i;
+ }
+
+ return val;
+}
+
+
+//________________________________________________________________________________________
+// PUBLIC FUNCTION IMPLEMENTATIONS
+#define ATO_T (15e-3f)
+#define ATO_K (39.05f)
+#define ATO_PSI (1.5f * IFX_PI)
+
+void Ifx_AngleTrkF32_setControlGains(Ifx_AngleTrkF32_CfgData *cfgData, float32 K, float32 T, float32 psi)
+{
+ cfgData->kp = ((2 * K) + (psi * psi) + 1) / (T * T);
+ cfgData->ki = K * ((psi * psi) + 1) / (T * T * T);
+ cfgData->kd = (K + 2) / T;
+}
+
+
+/** \brief Fill config with default values */
+void Ifx_AngleTrkF32_initConfig(Ifx_AngleTrkF32_Config *config, sint16 *sinIn, sint16 *cosIn)
+{
+ Ifx_AngleTrkF32_CfgData cfgData;
+ Ifx_AngleTrkF32_setControlGains(&cfgData, ATO_K, ATO_T, ATO_PSI);
+ config->kp = cfgData.kp;
+ config->ki = cfgData.ki;
+ config->kd = cfgData.kd;
+ config->sinIn = sinIn;
+ config->cosIn = cosIn;
+ config->errorThreshold = 5.0f / 180 * IFX_PI;
+ config->sqrAmplMax = (sint32)((1.01f * 1.01f) * 2048);
+ config->sqrAmplMin = (sint32)((0.99f * 0.99f) * 2048);
+ config->speedLpfFc = 100;
+ config->periodPerRotation = 1;
+ config->reversed = FALSE;
+ config->offset = 0;
+ config->resolution = (1UL << 12);/** \brief 12-bit default resolution */
+}
+
+
+void Ifx_AngleTrkF32_setUserSampling(Ifx_AngleTrkF32 *aObsv, float32 Ts)
+{
+ aObsv->base.Ts = Ts;
+ aObsv->halfTs = aObsv->base.Ts / 2.0F;
+}
+
+
+/** \brief Initialize the Angle Tracking object
+ * \param aObsv Pointer to the Ifx_AngleTrkF32 object
+ * \param config Pointer to the configuration data
+ * \param Ts sampling period in seconds
+ */
+void Ifx_AngleTrkF32_init(Ifx_AngleTrkF32 *aObsv, const Ifx_AngleTrkF32_Config *config, float32 Ts)
+{
+ aObsv->base.offset = config->offset;
+ aObsv->base.resolution = config->resolution;
+ aObsv->base.reversed = config->reversed;
+ aObsv->base.Ts = Ts;
+ aObsv->base.rawPosition = 0;
+ aObsv->base.direction = IfxStdIf_Pos_Dir_unknown;
+ aObsv->base.turn = 0;
+ aObsv->base.status.status = 0;
+ aObsv->base.periodPerRotation = config->periodPerRotation;
+ aObsv->base.positionConst = 1.0 / (float32)aObsv->base.resolution * 2.0 * IFX_PI;
+
+ aObsv->cfgData.kd = config->kd;
+ aObsv->cfgData.ki = config->ki;
+ aObsv->cfgData.kp = config->kp;
+ aObsv->cfgData.errorThreshold = config->errorThreshold;
+ aObsv->cfgData.sqrAmplMax = config->sqrAmplMax;
+ aObsv->cfgData.sqrAmplMin = config->sqrAmplMin;
+ aObsv->sinIn = config->sinIn;
+ aObsv->cosIn = config->cosIn;
+
+ if (!__neqf(config->kp, 0) && !__neqf(config->ki, 0) && !__neqf(config->kp, 0))
+ { /* all gains are zero, use default */
+ /* FIXME might not be requied as set by Ifx_AngleTrkF32_initConfig() */
+ Ifx_AngleTrkF32_setControlGains(&aObsv->cfgData, ATO_K, ATO_T, ATO_PSI);
+ }
+
+ Ifx_AngleTrkF32_setUserSampling(aObsv, Ts);
+ aObsv->angleErr = 0.0F;
+ aObsv->angleEst = 0.0F;
+ aObsv->accelEst = 0.0F;
+ aObsv->speedEstA = 0.0F;
+ aObsv->speedEstB = 0.0F;
+ aObsv->angleRef = 0.0F;
+ {
+#if IFX_CFG_ANGLETRKF32_SPEED_FILTER
+ Ifx_LowPassPt1F32_Config lpfConfig;
+ lpfConfig.gain = 1.0F;
+ lpfConfig.cutOffFrequency = (2 * IFX_PI * config->speedLpfFc);
+ lpfConfig.samplingTime = Ts;
+ Ifx_LowPassPt1F32_init(&aObsv->speedLpf, &lpfConfig);
+#endif
+ }
+}
+
+
+/** \brief Step function of Ifx_AngleTrkF32 should be called at every sampling period provided
+ * during initialisation (call to Ifx_AngleTrkF32_init()).
+ *
+ * \note This function is automatically called by Ifx_AngleTrkF32_update()
+ * \param aObsv Pointer to the Ifx_AngleTrkF32 object
+ * \param sinIn sine input signal. The offset shall be zero.
+ * \param cosIn cosine input signal. The offset shall be zero.
+ * \param phase phase of input signal.
+ * \note This function returns the angular position in radians
+ * \note The amplitude of both sinIn and cosIn signal shall be the same.
+ */
+float32 Ifx_AngleTrkF32_step(Ifx_AngleTrkF32 *aObsv, sint16 sinIn, sint16 cosIn, float32 phase)
+{
+ float32 angleRef, angleEst, dAccel, dSpeed, dAngle;
+
+ if (aObsv->base.reversed != FALSE)
+ {
+ angleRef = IFX_ANGLETRKF32_ATAN2F((float32)cosIn, (float32)sinIn);
+ }
+ else
+ {
+ angleRef = IFX_ANGLETRKF32_ATAN2F((float32)sinIn, (float32)cosIn);
+ }
+
+ aObsv->angleAtan = angleRef;
+ angleRef = angleRef + phase;
+
+ aObsv->angleRef = angleRef;
+
+ // Acceleration, zero-order-hold integrator:
+ dAccel = aObsv->cfgData.ki * aObsv->angleErr;
+ aObsv->accelEst = aObsv->accelEst + (dAccel * aObsv->base.Ts);
+
+ // Speed, zero-order-hold integrator:
+ dSpeed = ((aObsv->cfgData.kp * aObsv->angleErr) + aObsv->accelEst);
+ aObsv->speedEstA = aObsv->speedEstA + (dSpeed * aObsv->base.Ts);
+
+ // Angle, first-order-hold integrator:
+ dAngle = ((aObsv->cfgData.kd * aObsv->angleErr) + aObsv->speedEstA);
+ angleEst = aObsv->angleEst + ((dAngle + aObsv->speedEstB) * aObsv->halfTs);
+ aObsv->speedEstB = dAngle;
+
+ aObsv->angleEst = Ifx_AngleTrkF32_boundInput(angleEst);
+
+ // Error, is calculated here to compensate one period delay
+ aObsv->angleErr = Ifx_AngleTrkF32_boundInput(aObsv->angleRef - aObsv->angleEst);
+
+ aObsv->base.direction = aObsv->speedEstB > 0 ? IfxStdIf_Pos_Dir_forward : IfxStdIf_Pos_Dir_backward;
+
+#if IFX_CFG_ANGLETRKF32_SPEED_FILTER
+ // Filter speed:
+ Ifx_LowPassPt1F32_do(&aObsv->speedLpf, aObsv->speedEstB);
+#endif
+
+ return aObsv->angleEst;
+}
+
+
+/** \brief Set the position offset (in ticks)
+ * \param aObsv Pointer to the Ifx_AngleTrkF32 object
+ * \param offset Position offset in ticks
+ */
+void Ifx_AngleTrkF32_setOffset(Ifx_AngleTrkF32 *aObsv, IfxStdIf_Pos_RawAngle offset)
+{
+ Ifx_AngleTrkF32_PosIf *base = &aObsv->base;
+ base->offset = offset;
+}
+
+
+/** \brief Update the status flags.
+ * \param aObsv Pointer to the Ifx_AngleTrkF32 object
+ * \param sinIn Sinus value
+ * \param cosIn Cosinus value
+ * \note This function is automatically called by Ifx_AngleTrkF32_update()
+ */
+void Ifx_AngleTrkF32_updateStatus(Ifx_AngleTrkF32 *aObsv, sint16 sinIn, sint16 cosIn)
+{
+ Ifx_AngleTrkF32_PosIf *base = &aObsv->base;
+ sint32 sqrAmpl = ((sint32)sinIn * (sint32)sinIn) + ((sint32)cosIn * (sint32)cosIn);
+ base->status.B.signalLoss = (sqrAmpl < aObsv->cfgData.sqrAmplMin);
+ base->status.B.signalDegradation = (sqrAmpl > aObsv->cfgData.sqrAmplMax);
+ base->status.B.trackingLoss = __absf(aObsv->angleErr) > aObsv->cfgData.errorThreshold;
+}
+
+
+/** \brief Update the object directly from its analog input
+ * \param aObsv Pointer to the Ifx_AngleTrkF32 object
+ */
+void Ifx_AngleTrkF32_update(Ifx_AngleTrkF32 *aObsv)
+{
+ Ifx_AngleTrkF32_PosIf *base = &aObsv->base;
+ float32 angleEst = Ifx_AngleTrkF32_step(aObsv, *aObsv->sinIn, *aObsv->cosIn, 0);
+
+ IfxStdIf_Pos_RawAngle newPosition = (IfxStdIf_Pos_RawAngle)(angleEst * (aObsv->base.resolution / 2) / IFX_PI);
+ newPosition = newPosition & (aObsv->base.resolution - 1);
+ base->rawPosition = newPosition;
+
+ Ifx_AngleTrkF32_updateStatus(aObsv, *aObsv->sinIn, *aObsv->cosIn);
+}
+
+
+/** \brief Returns the actual position
+ * \param aObsv Pointer to the Ifx_AngleTrkF32 object
+ * \note This function returns the angular position in ticks [0 .. Ifx_AngleTrkF32.base.resolution-1] (represents 0..360 degree)
+ */
+IfxStdIf_Pos_RawAngle Ifx_AngleTrkF32_getRawPosition(Ifx_AngleTrkF32 *aObsv)
+{
+ Ifx_AngleTrkF32_PosIf *base = &aObsv->base;
+ return base->rawPosition;
+}
+
+
+/** \brief Returns the Speed
+ * \param aObsv Pointer to the Ifx_AngleTrkF32 object
+ */
+float32 Ifx_AngleTrkF32_getSpeed(Ifx_AngleTrkF32 *aObsv)
+{
+#if !IFX_CFG_ANGLETRKF32_FILTERED_SPEED
+ return aObsv->speedEstB; /* note: using speedEstB has better dynamic */
+#else
+ return aObsv->speedLpf.out; /* note: using filtered speed has less ripples */
+#endif
+}
+
+
+/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/
+float32 Ifx_AngleTrkF32_getAbsolutePosition(Ifx_AngleTrkF32 *driver)
+{
+ return ((float32)driver->base.turn + (float32)driver->base.rawPosition / (float32)driver->base.resolution) * 2.0 * IFX_PI;
+}
+
+
+IfxStdIf_Pos_Dir Ifx_AngleTrkF32_getDirection(Ifx_AngleTrkF32 *driver)
+{
+ return driver->base.direction;
+}
+
+
+IfxStdIf_Pos_Status Ifx_AngleTrkF32_getFault(Ifx_AngleTrkF32 *driver)
+{
+ return driver->base.status;
+}
+
+
+sint32 Ifx_AngleTrkF32_getOffset(Ifx_AngleTrkF32 *driver)
+{
+ return driver->base.offset;
+}
+
+
+uint16 Ifx_AngleTrkF32_getPeriodPerRotation(Ifx_AngleTrkF32 *driver)
+{
+ return driver->base.periodPerRotation;
+}
+
+
+float32 Ifx_AngleTrkF32_getPosition(Ifx_AngleTrkF32 *driver)
+{
+ return (float32)driver->base.rawPosition * driver->base.positionConst;
+}
+
+
+float32 Ifx_AngleTrkF32_getRefreshPeriod(Ifx_AngleTrkF32 *driver)
+{
+ return driver->base.Ts;
+}
+
+
+sint32 Ifx_AngleTrkF32_getResolution(Ifx_AngleTrkF32 *driver)
+{
+ return driver->base.resolution;
+}
+
+
+IfxStdIf_Pos_SensorType Ifx_AngleTrkF32_getSensorType(Ifx_AngleTrkF32 *driver)
+{
+ IFX_UNUSED_PARAMETER(driver);
+ return IfxStdIf_Pos_SensorType_angletrk;
+}
+
+
+sint32 Ifx_AngleTrkF32_getTurn(Ifx_AngleTrkF32 *driver)
+{
+ return driver->base.turn;
+}
+
+
+void Ifx_AngleTrkF32_resetFaults(Ifx_AngleTrkF32 *driver)
+{
+ driver->base.status.status = 0;
+}
+
+
+void Ifx_AngleTrkF32_setRefreshPeriod(Ifx_AngleTrkF32 *driver, float32 updatePeriod)
+{
+ driver->base.Ts = updatePeriod;
+}
+
+
+void Ifx_AngleTrkF32_reset(Ifx_AngleTrkF32 *driver)
+{
+ driver->base.rawPosition = 0;
+ driver->base.direction = IfxStdIf_Pos_Dir_unknown;
+ driver->base.turn = 0;
+ driver->angleErr = 0.0F;
+ driver->angleEst = 0.0F;
+ driver->accelEst = 0.0F;
+ driver->speedEstA = 0.0F;
+ driver->speedEstB = 0.0F;
+ driver->angleRef = 0.0F;
+#if IFX_CFG_ANGLETRKF32_SPEED_FILTER
+ Ifx_LowPassPt1F32_reset(&driver->speedLpf);
+#endif
+
+ driver->base.status.status = 0;
+}
+
+
+boolean Ifx_AngleTrkF32_stdIfPosInit(IfxStdIf_Pos *stdif, Ifx_AngleTrkF32 *driver)
+{
+ /* Ensure the stdif is reset to zeros */
+ memset(stdif, 0, sizeof(IfxStdIf_Pos));
+
+ /* Set the driver */
+ stdif->driver = driver;
+
+ /* *INDENT-OFF* Note: this file was indented manually by the author. */
+ /* Set the API link */
+ stdif->onZeroIrq =(IfxStdIf_Pos_OnZeroIrq )NULL_PTR;
+ stdif->getAbsolutePosition=(IfxStdIf_Pos_GetAbsolutePosition )&Ifx_AngleTrkF32_getAbsolutePosition;
+ stdif->getDirection =(IfxStdIf_Pos_GetDirection )&Ifx_AngleTrkF32_getDirection;
+ stdif->getFault =(IfxStdIf_Pos_GetFault )&Ifx_AngleTrkF32_getFault;
+ stdif->getOffset =(IfxStdIf_Pos_GetOffset )&Ifx_AngleTrkF32_getOffset;
+ stdif->getPeriodPerRotation =(IfxStdIf_Pos_GetPeriodPerRotation )&Ifx_AngleTrkF32_getPeriodPerRotation;
+ stdif->getPosition =(IfxStdIf_Pos_GetPosition )&Ifx_AngleTrkF32_getPosition;
+ stdif->getRawPosition =(IfxStdIf_Pos_GetRawPosition )&Ifx_AngleTrkF32_getRawPosition;
+ stdif->getRefreshPeriod =(IfxStdIf_Pos_GetRefreshPeriod )&Ifx_AngleTrkF32_getRefreshPeriod;
+ stdif->getResolution =(IfxStdIf_Pos_GetResolution )&Ifx_AngleTrkF32_getResolution;
+ stdif->getSensorType =(IfxStdIf_Pos_GetSensorType )&Ifx_AngleTrkF32_getSensorType;
+ stdif->reset =(IfxStdIf_Pos_Reset )&Ifx_AngleTrkF32_reset;
+ stdif->resetFaults =(IfxStdIf_Pos_ResetFaults )&Ifx_AngleTrkF32_resetFaults;
+ stdif->getSpeed =(IfxStdIf_Pos_GetSpeed )&Ifx_AngleTrkF32_getSpeed;
+ stdif->update =(IfxStdIf_Pos_Update )&Ifx_AngleTrkF32_update;
+ stdif->setPosition =(IfxStdIf_Pos_SetPosition )NULL_PTR;
+ stdif->setRawPosition =(IfxStdIf_Pos_SetRawPosition )NULL_PTR;
+ stdif->setSpeed =(IfxStdIf_Pos_SetSpeed )NULL_PTR;
+ stdif->setOffset =(IfxStdIf_Pos_SetOffset )&Ifx_AngleTrkF32_setOffset;
+ stdif->setRefreshPeriod =(IfxStdIf_Pos_SetRefreshPeriod )&Ifx_AngleTrkF32_setRefreshPeriod;
+ stdif->getTurn =(IfxStdIf_Pos_GetTurn )&Ifx_AngleTrkF32_getTurn;
+ /* *INDENT-ON* */
+
+ return TRUE;
+}
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Math/Ifx_AngleTrkF32.h b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Math/Ifx_AngleTrkF32.h
new file mode 100644
index 0000000..6abc37e
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Math/Ifx_AngleTrkF32.h
@@ -0,0 +1,309 @@
+/**
+ * \file Ifx_AngleTrkF32.h
+ * \brief Angle-tracking observer for sin/cos analog position sensor
+ *
+ *
+ *
+ * \version disabled
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ * \defgroup library_srvsw_sysse_math_f32_angletrk Angle-Tracking Observer
+ * This driver implements \ref library_srvsw_stdif_posif using 3rd order Angle-Tracking Observer algorithm.
+ * \ingroup library_srvsw_sysse_math_f32
+ *
+ */
+
+#ifndef IFX_ANGLETRKF32_H
+#define IFX_ANGLETRKF32_H
+
+//________________________________________________________________________________________
+// INCLUDES
+
+#include "StdIf/IfxStdIf_Pos.h"
+#include "SysSe/Math/Ifx_LowPassPt1F32.h"
+
+//________________________________________________________________________________________
+// CONFIGURATION DEFINES
+
+#ifndef IFX_CFG_ANGLETRKF32_SPEED_FILTER
+#define IFX_CFG_ANGLETRKF32_SPEED_FILTER (1)
+#endif
+
+/** \brief Specify whether the speed reading is filtered by low-pass filter or not */
+#ifndef IFX_CFG_ANGLETRKF32_FILTERED_SPEED
+#define IFX_CFG_ANGLETRKF32_FILTERED_SPEED (1)
+#endif
+
+//________________________________________________________________________________________
+// DATA STRUCTURES
+
+/** \brief Angle Tracking Observer configuration */
+typedef struct
+{
+ float32 kp; /**< \brief Proportional gain */
+ float32 ki; /**< \brief Integrator gain */
+ float32 kd; /**< \brief Derivative gain */
+ float32 speedLpfFc; /**< \brief Cut-off frequency of speed low-pass filter. */
+ float32 errorThreshold; /**< \brief Threshold of error value in the tracking loop */
+ sint32 sqrAmplMax; /**< \brief Maximum value for square of signal amplitudes */
+ sint32 sqrAmplMin; /**< \brief Minimum value for square of signal amplitudes */
+ uint16 periodPerRotation; /**< \brief Number of electrical periods per mechanical rotation */
+ boolean reversed; /**< \brief TRUE: reversed direction, FALSE: straight direction */
+ sint32 resolution; /**< \brief Sensor resolution */
+ IfxStdIf_Pos_RawAngle offset; /**< \brief Offset in ticks. [0 .. (\ref Ifx_AngleTrkF32_Config.resolution - 1)] */
+ sint16 *sinIn; /**< \brief Pointer to SIN input variable */
+ sint16 *cosIn; /**< \brief Pointer to COS input variable */
+} Ifx_AngleTrkF32_Config;
+
+typedef struct
+{
+ float32 kp; /**< \brief Proportional gain */
+ float32 ki; /**< \brief Integrator gain */
+ float32 kd; /**< \brief Derivative gain */
+ float32 errorThreshold; /**< \brief Threshold of error value in the tracking loop */
+ sint32 sqrAmplMax; /**< \brief Maximum value for square of signal amplitudes */
+ sint32 sqrAmplMin; /**< \brief Minimum value for square of signal amplitudes */
+} Ifx_AngleTrkF32_CfgData;
+
+typedef struct
+{
+ IfxStdIf_Pos_RawAngle rawPosition; /**< \brief raw position in ticks. \note: the value already contains the offset */
+ sint32 turn; /**< \brief number of mechanical turns. FIXME to be implemented */
+ IfxStdIf_Pos_Dir direction; /**< \brief rotation direction */
+ IfxStdIf_Pos_Status status; /**< \brief error code (0 = no error) */
+ /* configuration */
+ IfxStdIf_Pos_RawAngle offset; /**< \brief raw position offset */
+ boolean reversed; /**< \brief reverse direction */
+ uint16 periodPerRotation; /**< \brief sensor 'electrical' periods per mechanical rotation */
+ IfxStdIf_Pos_RawAngle resolution; /**< \brief resolution of this position sensor interface */
+ float32 Ts; /**< \brief update period in seconds */
+ float32 positionConst; /**< \brief constant for calculating mechanical position (in rad) from raw position */
+} Ifx_AngleTrkF32_PosIf;
+
+/** \brief Angle Tracking Observer object */
+typedef struct
+{
+ Ifx_AngleTrkF32_PosIf base;
+ Ifx_AngleTrkF32_CfgData cfgData;
+ sint16 *sinIn; /**< \brief Pointer to SIN input variable */
+ sint16 *cosIn; /**< \brief Pointer to COS input variable */
+ float32 halfTs;
+ float32 angleAtan;
+ float32 angleRef;
+ float32 angleEst;
+ float32 speedEstA;
+ float32 speedEstB;
+ float32 accelEst;
+ float32 angleErr;
+ Ifx_LowPassPt1F32 speedLpf; /**< Only used if IFX_CFG_ANGLETRKF32_SPEED_FILTER is set */
+} Ifx_AngleTrkF32;
+
+/** \addtogroup library_srvsw_sysse_math_f32_angletrk
+ * \{ */
+
+//________________________________________________________________________________________
+// PUBLIC FUNCTION PROTOTYPES
+
+/** \name Initialisation functions
+ * Example use:
+ * \code
+ * extern sint16 g_SinInput, g_CosInput;
+ * Ifx_AngleTrkF32_Config driverConfig;
+ * Ifx_AngleTrkF32 driverData;
+ * Ifx_AngleTrkF32_initConfig(&driverConfig, &g_SinInput, g_CosInput);
+ * driverConfig.errorThreshold = 5.0 / 180 * IFX_PI; // 5 degree error
+ * driverConfig.sqrAmplMax = 1.01 * 1.01;
+ * driverConfig.sqrAmplMin = 0.99 * 0.99;
+ * driverConfig.speedLpfFc = 100;
+ * driverConfig.periodPerRotation = 1;
+ * driverConfig.reversed = FALSE;
+ * driverConfig.offset = 0;
+ * Ifx_AngleTrkF32_init(&driverData, &driverConfig);
+ * \endcode
+ * Prototypes:
+ * \{ */
+IFX_EXTERN void Ifx_AngleTrkF32_init(Ifx_AngleTrkF32 *aObsv, const Ifx_AngleTrkF32_Config *config, float32 Ts);
+IFX_EXTERN void Ifx_AngleTrkF32_initConfig(Ifx_AngleTrkF32_Config *config, sint16 *sinIn, sint16 *cosIn);
+/** \} */
+
+/** \name Protected functions
+ * These functions are not for end-user but may be used by another driver which extends
+ * the functionality of library_srvsw_sysse_math_f32_angletrk
+ * \{ */
+IFX_EXTERN float32 Ifx_AngleTrkF32_step(Ifx_AngleTrkF32 *aObsv, sint16 sinIn, sint16 cosIn, float32 phase);
+IFX_EXTERN void Ifx_AngleTrkF32_updateStatus(Ifx_AngleTrkF32 *aObsv, sint16 sinIn, sint16 cosIn);
+IFX_INLINE float32 Ifx_AngleTrkF32_getLoopSpeed(Ifx_AngleTrkF32 *aObsv);
+/** \} */
+
+/** \} */
+
+/** \brief get the speed.
+ * \param aObsv Pointer to the Ifx_AngleTrkF32 object
+ */
+IFX_INLINE float32 Ifx_AngleTrkF32_getLoopSpeed(Ifx_AngleTrkF32 *aObsv)
+{
+ return aObsv->speedEstB; /* note: using speedEstB has better dynamic */
+ /* return aObsv->speedLpf.out; */
+}
+
+
+/** \addtogroup library_srvsw_sysse_math_f32_angletrk
+ * \{ */
+
+/******************************************************************************/
+/*-------------------------Global Function Prototypes-------------------------*/
+/******************************************************************************/
+
+/** \brief \see IfxStdIf_Pos_GetAbsolutePosition
+ * \param driver driver handle
+ * \return absolute position
+ */
+IFX_EXTERN float32 Ifx_AngleTrkF32_getAbsolutePosition(Ifx_AngleTrkF32 *driver);
+
+/** \brief \see IfxStdIf_Pos_GetDirection
+ * \param driver driver handle
+ * \return direction
+ */
+IFX_EXTERN IfxStdIf_Pos_Dir Ifx_AngleTrkF32_getDirection(Ifx_AngleTrkF32 *driver);
+
+/** \brief \see IfxStdIf_Pos_GetFault
+ * \param driver driver handle
+ * \return Fault
+ */
+IFX_EXTERN IfxStdIf_Pos_Status Ifx_AngleTrkF32_getFault(Ifx_AngleTrkF32 *driver);
+
+/** \brief \see IfxStdIf_Pos_GetOffset
+ * \param driver driver handle
+ * \return offset address
+ */
+IFX_EXTERN sint32 Ifx_AngleTrkF32_getOffset(Ifx_AngleTrkF32 *driver);
+
+/** \brief \see IfxStdIf_Pos_GetPeriodPerRotation
+ * \param driver driver handle
+ * \return Period per rotation
+ */
+IFX_EXTERN uint16 Ifx_AngleTrkF32_getPeriodPerRotation(Ifx_AngleTrkF32 *driver);
+
+/** \brief \see IfxStdIf_Pos_GetPosition
+ * \param driver driver handle
+ * \return position
+ */
+IFX_EXTERN float32 Ifx_AngleTrkF32_getPosition(Ifx_AngleTrkF32 *driver);
+
+/** \brief \see IfxStdIf_Pos_GetRawPosition
+ * \param aObsv Pointer to the Ifx_AngleTrkF32 object
+ * \return position in ticks
+ */
+IFX_EXTERN IfxStdIf_Pos_RawAngle Ifx_AngleTrkF32_getRawPosition(Ifx_AngleTrkF32 *aObsv);
+
+/** \brief \see IfxStdIf_Pos_GetRefreshPeriod
+ * \param driver driver handle
+ * \return update period
+ */
+IFX_EXTERN float32 Ifx_AngleTrkF32_getRefreshPeriod(Ifx_AngleTrkF32 *driver);
+
+/** \brief \see IfxStdIf_Pos_GetResolution
+ * \param driver driver handle
+ * \return resolution
+ */
+IFX_EXTERN sint32 Ifx_AngleTrkF32_getResolution(Ifx_AngleTrkF32 *driver);
+
+/** \brief \see IfxStdIf_Pos_GetTurn
+ * \param driver driver handle
+ * \return Returns the number of turns
+ */
+IFX_EXTERN sint32 Ifx_AngleTrkF32_getTurn(Ifx_AngleTrkF32 *driver);
+
+/** \brief \see IfxStdIf_Pos_GetSensorType
+ * \param driver driver handle
+ * \return sensor type
+ */
+IFX_EXTERN IfxStdIf_Pos_SensorType Ifx_AngleTrkF32_getSensorType(Ifx_AngleTrkF32 *driver);
+
+/** \brief \see IfxStdIf_Pos_GetSpeed
+ * \param aObsv Pointer to the Ifx_AngleTrkF32 object
+ * \return speed
+ */
+IFX_EXTERN float32 Ifx_AngleTrkF32_getSpeed(Ifx_AngleTrkF32 *aObsv);
+
+/** \brief \see IfxStdIf_Pos_Reset
+ * \param driver driver handle
+ * \return None
+ */
+IFX_EXTERN void Ifx_AngleTrkF32_reset(Ifx_AngleTrkF32 *driver);
+
+/** \brief \see IfxStdIf_Pos_ResetFaults
+ * \param driver driver handle
+ * \return None
+ */
+IFX_EXTERN void Ifx_AngleTrkF32_resetFaults(Ifx_AngleTrkF32 *driver);
+
+/** \brief \see IfxStdIf_Pos_SetOffset
+ * \param aObsv driver handle
+ * \param offset offset
+ * \return None
+ */
+IFX_EXTERN void Ifx_AngleTrkF32_setOffset(Ifx_AngleTrkF32 *aObsv, IfxStdIf_Pos_RawAngle offset);
+
+/** \brief \see IfxStdIf_Pos_SetRefreshPeriod
+ * \param driver driver handle
+ * \param updatePeriod update period
+ * \return None
+ */
+IFX_EXTERN void Ifx_AngleTrkF32_setRefreshPeriod(Ifx_AngleTrkF32 *driver, float32 updatePeriod);
+
+/** \brief \see IfxStdIf_Pos_Update
+ * \param aObsv driver handle
+ * \return None
+ */
+IFX_EXTERN void Ifx_AngleTrkF32_update(Ifx_AngleTrkF32 *aObsv);
+
+/** \} */
+
+/******************************************************************************/
+/*-------------------------Global Function Prototypes-------------------------*/
+/******************************************************************************/
+
+/** \brief Initializes the standard interface "Pos"
+ * \param stdif Standard interface position object
+ * \param driver Virtual position sensor
+ * \return TRUE on success else FALSE
+ */
+IFX_EXTERN boolean Ifx_AngleTrkF32_stdIfPosInit(IfxStdIf_Pos *stdif, Ifx_AngleTrkF32 *driver);
+
+#endif /* IFX_ANGLETRKF32_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Math/Ifx_Cf32.c b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Math/Ifx_Cf32.c
new file mode 100644
index 0000000..25bfd3b
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Math/Ifx_Cf32.c
@@ -0,0 +1,390 @@
+/**
+ * \file Ifx_Cf32.c
+ * \brief Floating point signal, vector, and matrix library
+ *
+ *
+ * \version disabled
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ */
+
+#include "Ifx_Cf32.h"
+#include
+#include
+
+void CplxVecRst_f32(cfloat32 *X, short nX)
+{
+ for ( ; nX > 0; nX--)
+ {
+ X->real = X->imag = 0.0;
+ X++;
+ }
+}
+
+
+void CplxVecCpy_f32S(cfloat32 *X, short *S, short nS, short incrS)
+{
+ for ( ; nS > 0; nS--)
+ {
+ (*X).imag = 0.0;
+ (*X).real = *(S);
+ X++; S += incrS;
+ }
+}
+
+
+void CplxVecCpy_f32(cfloat32 *X, cfloat32 *S, short nS)
+{
+ for ( ; nS > 0; nS--)
+ {
+ *X = *S;
+ X++; S++;
+ }
+}
+
+
+float32 *CplxVecPwr_f32(cfloat32 *X, short nX)
+{
+ unsigned short i;
+ float32 *r = (float32 *)X;
+
+ for (i = 0; i < nX; i++)
+ {
+ *r = IFX_Cf32_dot(X);
+ r++; X++;
+ }
+
+ return &r[-nX];
+}
+
+
+float32 *CplxVecMag_f32(cfloat32 *X, short nX)
+{
+ unsigned short i;
+ float32 *r = (float32 *)X;
+
+ for (i = 0; i < nX; i++)
+ {
+ *r = IFX_Cf32_mag(X);
+ r++; X++;
+ }
+
+ return &r[-nX];
+}
+
+
+void CplxVecMul_f32(cfloat32 *X, const cfloat32 *mul, short nX)
+{
+ for ( ; nX > 0; nX--)
+ {
+ *X = IFX_Cf32_mul(X, mul);
+ X++;
+ }
+}
+
+
+void VecPwrdB_f32(float32 *X, short nX)
+{
+ unsigned short i;
+
+ for (i = 0; i < nX; i++)
+ {
+ *X = (float32)20.0 * log10f(*X);
+ X++;
+ }
+}
+
+
+void VecPwrdB_SF(sint16 *R, float32 *X, short nX)
+{
+ unsigned short i;
+
+ for (i = 0; i < nX; i++)
+ {
+ *R = (sint16)(20.0 * log10f(*X));
+ R++; X++;
+ }
+}
+
+
+float32 VecMaxIdx_f32(float32 *X, short nX, sint16 *minIdx, sint16 *maxIdx)
+{
+ float32 maxPeak = FLT_MIN;
+ unsigned short m;
+
+ for (m = 0; m < nX; m++)
+ {
+ if (*X > maxPeak)
+ {
+ maxPeak = *X;
+ *minIdx = m;
+ }
+
+ if (*X >= maxPeak)
+ {
+ *maxIdx = m;
+ }
+
+ X++;
+ }
+
+ return maxPeak;
+}
+
+
+float32 VecMinIdx_f32(float32 *X, short nX, sint16 *minIdx, sint16 *maxIdx)
+{
+ float32 minPeak = FLT_MAX;
+ short m;
+
+ for (m = 0; m < nX; m++)
+ {
+ if (*X < minPeak)
+ {
+ minPeak = *X;
+ *minIdx = m;
+ }
+
+ if (*X <= minPeak)
+ {
+ *maxIdx = m;
+ }
+
+ X++;
+ }
+
+ return minPeak;
+}
+
+
+void VecOfs_f32(float32 *X, float32 offset, short nX)
+{
+ unsigned short i;
+
+ for (i = 0; i < nX; i++)
+ {
+ *X -= offset;
+ X++;
+ }
+}
+
+
+void VecGain_f32(float32 *X, float32 gain, short nX)
+{
+ unsigned short i;
+
+ for (i = 0; i < nX; i++)
+ {
+ *X = *X * gain;
+ X++;
+ }
+}
+
+
+float32 VecSum_f32(float32 *X, short nX)
+{
+ float32 sumX = 0;
+ unsigned short i;
+
+ for (i = 0; i < nX; i++)
+ {
+ sumX += *X;
+ X++;
+ }
+
+ return sumX;
+}
+
+
+float32 VecAvg_f32(float32 *X, short nX)
+{
+ return VecSum_f32(X, nX) / nX;
+}
+
+
+float32 VecMax_f32(float32 *X, short nX)
+{
+ unsigned short i;
+ float32 r = FLT_MIN;
+
+ for (i = 0; i < nX; i++)
+ {
+ r = __maxf(r, *X);
+ X++;
+ }
+
+ return r;
+}
+
+
+float32 VecMin_f32(float32 *X, short nX)
+{
+ unsigned short i;
+ float32 r = FLT_MAX;
+
+ for (i = 0; i < nX; i++)
+ {
+ r = __minf(r, *X);
+ X++;
+ }
+
+ return r;
+}
+
+
+void VecHalfSwap_f32(float32 *X, short nX)
+{
+ unsigned short i;
+ unsigned short half = nX / 2;
+ float32 *F = &X[half];
+
+ for (i = 0; i < half; i++)
+ {
+ float32 tmp = *F;
+ *F = *X;
+ *X = tmp;
+ F++; X++;
+ }
+}
+
+
+/* NOTE:
+ * (nX <= nW) && ((nW % nX) == 0) && ((nX % 2) == 0)
+ * (symW != 0) when the window is symmetrical */
+void VecWin_f32(float32 *X, const float32 *W, short nX, short nW, short incrX, short symW)
+{
+ short step = nW / nX;
+ short i;
+
+ if (symW != 0)
+ { /* symmetrical window, using half of the length */
+ for (i = 0; i < nX / 2; i++)
+ {
+ *X = *X * *W;
+ X = &X[incrX];
+ W = &W[step];
+ }
+
+ W = &W[-step];
+
+ for ( ; i < nX; i++)
+ {
+ *X = *X * *W;
+ X = &X[incrX];
+ W = &W[-step];
+ }
+ }
+}
+
+
+#ifdef __WIN32__
+
+#define ENDL "\r\n"
+
+void DataF_printf(FILE *fp, pchar fileName, float32 *data, long nX, int enclosed)
+{
+ long i;
+
+ if (fileName != NULL)
+ {
+ fp = fopen(fileName, "w+");
+ }
+
+ if (fp != NULL)
+ {
+ if (enclosed)
+ {
+ for (i = 0; i < nX; i++)
+ {
+ fprintf(fp, "_DATAF(%10.20f),"ENDL, *data);
+ data = &data[1];
+ }
+ }
+ else
+ {
+ for (i = 0; i < nX; i++)
+ {
+ fprintf(fp, "%10.20f,"ENDL, *data);
+ data = &data[1];
+ }
+ }
+ }
+
+ if (fileName != NULL)
+ {
+ fclose(fp);
+ }
+}
+
+
+void Cplx_f32_printf(FILE *fp, pchar fileName, cfloat32 *data, long nX, int encloseData)
+{
+ long i;
+
+ if (fileName != NULL)
+ {
+ fp = fopen(fileName, "w+");
+ }
+
+ if (fp != NULL)
+ {
+ if (encloseData)
+ {
+ for (i = 0; i < nX; i++)
+ {
+ fprintf(fp, "{_DATAF(%10.20f), _DATAF(%10.20f)},"ENDL, data->real, data->imag);
+ data = &data[1];
+ }
+ }
+ else
+ {
+ for (i = 0; i < nX; i++)
+ {
+ fprintf(fp, "%10.20f, %10.20f"ENDL, data->real, data->imag);
+ data = &data[1];
+ }
+ }
+ }
+
+ if (fileName != NULL)
+ {
+ fclose(fp);
+ }
+}
+
+
+#endif
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Math/Ifx_Cf32.h b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Math/Ifx_Cf32.h
new file mode 100644
index 0000000..1d12a2b
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Math/Ifx_Cf32.h
@@ -0,0 +1,184 @@
+/**
+ * \file Ifx_Cf32.h
+ * \brief Floating point signal, vector, and matrix library
+ *
+ *
+ * \version disabled
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ * \defgroup library_srvsw_sysse_math_cf32 Floating point signal, vector, and matrix library
+ * \ingroup library_srvsw_sysse_math_f32
+ */
+
+#ifndef IFX_CF32_H
+#define IFX_CF32_H
+
+#include "Cpu/Std/IfxCpu_Intrinsics.h"
+#include
+
+#define _DATAF(val) ((float32)(val))
+
+/* Complex Arithmetic --------------------------------------------------------*/
+IFX_INLINE cfloat32 IFX_Cf32_exp(const cfloat32 *c)
+{
+ float32 f = (float32)expf(c->real);
+ cfloat32 R;
+ R.real = f * (float32)cosf(c->imag);
+ R.imag = f * (float32)sinf(c->imag);
+ return R;
+}
+
+
+IFX_INLINE cfloat32 IFX_Cf32_mul(const cfloat32 *a, const cfloat32 *b)
+{
+ cfloat32 R;
+ R.real = (a->real * b->real) - (a->imag * b->imag);
+ R.imag = (a->imag * b->real) + (a->real * b->imag);
+ return R;
+}
+
+
+IFX_INLINE cfloat32 IFX_Cf32_amp(const cfloat32 *a, float32 gain)
+{
+ cfloat32 R;
+ R.real = a->real * gain;
+ R.imag = a->imag * gain;
+ return R;
+}
+
+
+IFX_INLINE float32 IFX_Cf32_dot(const cfloat32 *b)
+{
+ return (b->real * b->real) + (b->imag * b->imag);
+}
+
+
+IFX_INLINE float32 IFX_Cf32_mag(const cfloat32 *c)
+{
+ return (float32)sqrtf(IFX_Cf32_dot(c));
+}
+
+
+IFX_INLINE cfloat32 IFX_Cf32_div(const cfloat32 *a, const cfloat32 *b)
+{
+ float32 denom = IFX_Cf32_dot(b);
+ cfloat32 R;
+ R.real = ((a->real * b->real) + (a->imag * b->imag)) / denom;
+ R.imag = ((a->imag * b->real) - (a->real * b->imag)) / denom;
+ return R;
+}
+
+
+IFX_INLINE cfloat32 IFX_Cf32_add(const cfloat32 *a, const cfloat32 *b)
+{
+ cfloat32 R;
+ R.real = (a->real + b->real);
+ R.imag = (a->imag + b->imag);
+ return R;
+}
+
+
+IFX_INLINE cfloat32 IFX_Cf32_sub(const cfloat32 *a, const cfloat32 *b)
+{
+ cfloat32 R;
+ R.real = (a->real - b->real);
+ R.imag = (a->imag - b->imag);
+ return R;
+}
+
+
+IFX_INLINE void IFX_Cf32_set(cfloat32 *a, float32 re, float32 im)
+{
+ a->real = re;
+ a->imag = im;
+}
+
+
+IFX_INLINE void IFX_Cf32_reset(cfloat32 *a)
+{
+ IFX_Cf32_set(a, 0.0, 0.0);
+}
+
+
+IFX_INLINE cfloat32 IFX_Cf32_saturate(cfloat32 *a, float32 *ampl, float32 limit)
+{
+ cfloat32 R = *a;
+ *ampl = IFX_Cf32_mag(a);
+
+ if (*ampl > limit)
+ {
+ float32 scale = limit / *ampl;
+ R.imag = R.imag * scale;
+ R.real = R.real * scale;
+ }
+
+ return R;
+}
+
+
+IFX_EXTERN void CplxVecCpy_f32S(cfloat32 *X, short *S, short nS, short incrS);
+IFX_EXTERN void CplxVecRst_f32(cfloat32 *X, short nX);
+IFX_EXTERN void CplxVecCpy_f32(cfloat32 *X, cfloat32 *S, short nS);
+IFX_EXTERN float32 *CplxVecPwr_f32(cfloat32 *X, short nX);
+IFX_EXTERN float32 *CplxVecMag_f32(cfloat32 *X, short nX);
+IFX_EXTERN void CplxVecMul_f32(cfloat32 *X, const cfloat32 *mul, short nX);
+
+/* Vector Operation ----------------------------------------------------------*/
+
+IFX_EXTERN void VecWin_f32(float32 *X, const float32 *W, short nX, short nW, short incrX, short symW);
+IFX_EXTERN void VecPwrdB_f32(float32 *X, short nX);
+IFX_EXTERN void VecPwrdB_SF(sint16 *R, float32 *X, short nX);
+IFX_EXTERN void VecGain_f32(float32 *X, float32 gain, short nX);
+IFX_EXTERN void VecOfs_f32(float32 *X, float32 offset, short nX);
+IFX_EXTERN float32 VecSum_f32(float32 *X, short nX);
+IFX_EXTERN float32 VecAvg_f32(float32 *X, short nX);
+IFX_EXTERN float32 VecMax_f32(float32 *X, short nX);
+IFX_EXTERN float32 VecMin_f32(float32 *X, short nX);
+IFX_EXTERN float32 VecMinIdx_f32(float32 *X, short nX, sint16 *minIdx, sint16 *maxIdx);
+IFX_EXTERN float32 VecMaxIdx_f32(float32 *X, short nX, sint16 *minIdx, sint16 *maxIdx);
+IFX_EXTERN void VecHalfSwap_f32(float32 *X, short nX);
+
+/* Helper functions ----------------------------------------------------------*/
+#ifdef __WIN32__
+#include
+void Cplx_f32_printf(FILE *fp, pchar fileName, cfloat32 *data, long nX, int encloseData);
+#else
+#define Cplx_f32_printf(...)
+#endif
+
+#endif /* IFX_CF32_H */
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Math/Ifx_Crc.c b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Math/Ifx_Crc.c
new file mode 100644
index 0000000..748021e
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Math/Ifx_Crc.c
@@ -0,0 +1,656 @@
+/**
+ * \file Ifx_Crc.c
+ * \brief CRC algorithm
+ *
+ * \version disabled
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ */
+#include "Ifx_Crc.h"
+
+uint32 Ifx_Crc_reflect(uint32 crc, sint32 bitnum);
+
+boolean Ifx_Crc_init(Ifc_Crc *driver, const Ifc_Crc_Table *table, sint32 direct, sint32 refout, uint32 crcinit, uint32 crcxor)
+{
+ sint32 i;
+ uint32 bit, crc;
+
+ if (crcinit != (crcinit & table->crcmask))
+ {
+ //IfxStdIf_DPipe_print(io,"ERROR, invalid crcinit."ENDL);
+ return FALSE;
+ }
+
+ if (crcxor != (crcxor & table->crcmask))
+ {
+ //IfxStdIf_DPipe_print(io,"ERROR, invalid crcxor."ENDL);
+ return FALSE;
+ }
+
+ driver->table = table;
+ driver->crcxor = crcxor;
+ driver->refout = refout;
+
+ // compute missing initial CRC value
+
+ if (!direct)
+ {
+ driver->crcinit_nondirect = crcinit;
+ crc = crcinit;
+
+ for (i = 0; i < table->order; i++)
+ {
+ bit = crc & table->crchighbit;
+ crc <<= 1;
+
+ if (bit)
+ {
+ crc ^= table->polynom;
+ }
+ }
+
+ crc &= table->crcmask;
+ driver->crcinit_direct = crc;
+ }
+
+ else
+ {
+ driver->crcinit_direct = crcinit;
+ crc = crcinit;
+
+ for (i = 0; i < table->order; i++)
+ {
+ bit = crc & 1;
+
+ if (bit)
+ {
+ crc ^= table->polynom;
+ }
+
+ crc >>= 1;
+
+ if (bit)
+ {
+ crc |= table->crchighbit;
+ }
+ }
+
+ driver->crcinit_nondirect = crc;
+ }
+
+ return TRUE;
+}
+
+
+boolean Ifx_Crc_createTable(Ifc_Crc_Table *table, sint32 order, uint32 polynom, sint32 refin)
+{
+ uint32 crcmask;
+ // at first, compute constant bit masks for whole CRC and CRC high bit
+
+ crcmask = ((((uint32)1 << (order - 1)) - 1) << 1) | 1;
+
+ // check parameters
+
+ if ((order < 1) || (order > 32))
+ {
+ //IfxStdIf_DPipe_print(io,"ERROR, invalid order, it must be between 1..32."ENDL);
+ return FALSE;
+ }
+
+ if (polynom != (polynom & crcmask))
+ {
+ //IfxStdIf_DPipe_print(io,"ERROR, invalid polynom."ENDL);
+ return FALSE;
+ }
+
+ table->order = order;
+ table->polynom = polynom;
+ table->refin = refin;
+ table->crchighbit = (uint32)1 << (order - 1);
+ table->crcmask = crcmask;
+ // generate lookup table
+ // make CRC lookup table used by table algorithms
+ {
+ sint32 i, j;
+ uint32 bit, crc;
+
+ for (i = 0; i < 256; i++)
+ {
+ crc = (uint32)i;
+
+ if (refin)
+ {
+ crc = Ifx_Crc_reflect(crc, 8);
+ }
+
+ crc <<= order - 8;
+
+ for (j = 0; j < 8; j++)
+ {
+ bit = crc & table->crchighbit;
+ crc <<= 1;
+
+ if (bit)
+ {
+ crc ^= polynom;
+ }
+ }
+
+ if (refin)
+ {
+ crc = Ifx_Crc_reflect(crc, order);
+ }
+
+ crc &= crcmask;
+
+ if (order <= 8)
+ {
+ uint8 *crctab = (uint8 *)((uint32)table + sizeof(Ifc_Crc_Table));
+ crctab[i] = (uint8)crc;
+ }
+ else if (order <= 16)
+ {
+ uint16 *crctab = (uint16 *)((uint32)table + sizeof(Ifc_Crc_Table));
+ crctab[i] = (uint16)crc;
+ }
+ else
+ {
+ uint32 *crctab = (uint32 *)((uint32)table + sizeof(Ifc_Crc_Table));
+ crctab[i] = crc;
+ }
+ }
+ }
+ return TRUE;
+}
+
+
+// subroutines
+
+uint32 Ifx_Crc_reflect(uint32 crc, sint32 bitnum)
+{
+ // reflects the lower 'bitnum' bits of 'crc'
+
+ uint32 i, j = 1, crcout = 0;
+
+ for (i = (uint32)1 << (bitnum - 1); i; i >>= 1)
+ {
+ if (crc & i)
+ {
+ crcout |= j;
+ }
+
+ j <<= 1;
+ }
+
+ return crcout;
+}
+
+
+uint32 Ifx_Crc_tableFast(Ifc_Crc *driver, uint8 *p, uint32 len)
+{
+ // fast lookup table algorithm without augmented zero bytes, e.g. used in pkzip.
+ // only usable with polynom orders of 8, 16, 24 or 32.
+
+ uint32 crc = driver->crcinit_direct;
+ sint32 orderMinusHeight = driver->table->order - 8;
+
+ if (driver->table->refin)
+ {
+ crc = Ifx_Crc_reflect(crc, driver->table->order);
+ }
+
+ if (driver->table->order <= 8)
+ {
+ uint8 *crctab = (uint8 *)((uint32)driver->table + sizeof(Ifc_Crc_Table));
+
+ if (!driver->table->refin)
+ {
+ while (len--)
+ {
+ crc = (crc << 8) ^ crctab[((crc >> (orderMinusHeight)) & 0xff) ^ *p++];
+ }
+ }
+ else
+ {
+ while (len--)
+ {
+ crc = (crc >> 8) ^ crctab[(crc & 0xff) ^ *p++];
+ }
+ }
+ }
+ else if (driver->table->order <= 16)
+ {
+ uint16 *crctab = (uint16 *)((uint32)driver->table + sizeof(Ifc_Crc_Table));
+
+ if (!driver->table->refin)
+ {
+ while (len--)
+ {
+ crc = (crc << 8) ^ crctab[((crc >> (orderMinusHeight)) & 0xff) ^ *p++];
+ }
+ }
+ else
+ {
+ while (len--)
+ {
+ crc = (crc >> 8) ^ crctab[(crc & 0xff) ^ *p++];
+ }
+ }
+ }
+ else
+ {
+ uint32 *crctab = (uint32 *)((uint32)driver->table + sizeof(Ifc_Crc_Table));
+
+ if (!driver->table->refin)
+ {
+ while (len--)
+ {
+ crc = (crc << 8) ^ crctab[((crc >> (orderMinusHeight)) & 0xff) ^ *p++];
+ }
+ }
+ else
+ {
+ while (len--)
+ {
+ crc = (crc >> 8) ^ crctab[(crc & 0xff) ^ *p++];
+ }
+ }
+ }
+
+ if (driver->refout ^ driver->table->refin)
+ {
+ crc = Ifx_Crc_reflect(crc, driver->table->order);
+ }
+
+ crc ^= driver->crcxor;
+ crc &= driver->table->crcmask;
+
+ return crc;
+}
+
+
+uint32 Ifx_Crc_table(Ifc_Crc *driver, uint8 *p, uint32 len)
+{
+ // normal lookup table algorithm with augmented zero bytes.
+ // only usable with polynom orders of 8, 16, 24 or 32.
+
+ uint32 crc = driver->crcinit_nondirect;
+ sint32 orderMinusHeight = driver->table->order - 8;
+
+ if (driver->table->refin)
+ {
+ crc = Ifx_Crc_reflect(crc, driver->table->order);
+ }
+
+ if (driver->table->order <= 8)
+ {
+ uint8 *crctab = (uint8 *)((uint32)driver->table + sizeof(Ifc_Crc_Table));
+
+ if (!driver->table->refin)
+ {
+ while (len--)
+ {
+ crc = ((crc << 8) | *p++) ^ crctab[(crc >> (orderMinusHeight)) & 0xff];
+ }
+ }
+ else
+ {
+ while (len--)
+ {
+ crc = ((crc >> 8) | (*p++ << (orderMinusHeight))) ^ crctab[crc & 0xff];
+ }
+ }
+
+ if (!driver->table->refin)
+ {
+ while (++len < (driver->table->order >> 3))
+ {
+ crc = (crc << 8) ^ crctab[(crc >> (orderMinusHeight)) & 0xff];
+ }
+ }
+ else
+ {
+ while (++len < (driver->table->order >> 3))
+ {
+ crc = (crc >> 8) ^ crctab[crc & 0xff];
+ }
+ }
+ }
+ else if (driver->table->order <= 16)
+ {
+ uint16 *crctab = (uint16 *)((uint32)driver->table + sizeof(Ifc_Crc_Table));
+
+ if (!driver->table->refin)
+ {
+ while (len--)
+ {
+ crc = ((crc << 8) | *p++) ^ crctab[(crc >> (orderMinusHeight)) & 0xff];
+ }
+ }
+ else
+ {
+ while (len--)
+ {
+ crc = ((crc >> 8) | (*p++ << (orderMinusHeight))) ^ crctab[crc & 0xff];
+ }
+ }
+
+ if (!driver->table->refin)
+ {
+ while (++len < (driver->table->order >> 3))
+ {
+ crc = (crc << 8) ^ crctab[(crc >> (orderMinusHeight)) & 0xff];
+ }
+ }
+ else
+ {
+ while (++len < (driver->table->order >> 3))
+ {
+ crc = (crc >> 8) ^ crctab[crc & 0xff];
+ }
+ }
+ }
+ else if (driver->table->order <= 32)
+ {
+ uint32 *crctab = (uint32 *)((uint32)driver->table + sizeof(Ifc_Crc_Table));
+
+ if (!driver->table->refin)
+ {
+ while (len--)
+ {
+ crc = ((crc << 8) | *p++) ^ crctab[(crc >> (orderMinusHeight)) & 0xff];
+ }
+ }
+ else
+ {
+ while (len--)
+ {
+ crc = ((crc >> 8) | (*p++ << (orderMinusHeight))) ^ crctab[crc & 0xff];
+ }
+ }
+
+ if (!driver->table->refin)
+ {
+ while (++len < (driver->table->order >> 3))
+ {
+ crc = (crc << 8) ^ crctab[(crc >> (orderMinusHeight)) & 0xff];
+ }
+ }
+ else
+ {
+ while (++len < (driver->table->order >> 3))
+ {
+ crc = (crc >> 8) ^ crctab[crc & 0xff];
+ }
+ }
+ }
+
+ if (driver->refout ^ driver->table->refin)
+ {
+ crc = Ifx_Crc_reflect(crc, driver->table->order);
+ }
+
+ crc ^= driver->crcxor;
+ crc &= driver->table->crcmask;
+
+ return crc;
+}
+
+
+uint32 Ifx_Crc_bitByBit(Ifc_Crc *driver, uint8 *p, uint32 len)
+{
+ // bit by bit algorithm with augmented zero bytes.
+ // does not use lookup table, suited for polynom driver->table->orders between 1...32.
+
+ uint32 i, j, c, bit;
+ uint32 crc = driver->crcinit_nondirect;
+
+ for (i = 0; i < len; i++)
+ {
+ c = (uint32)*p++;
+
+ if (driver->table->refin)
+ {
+ c = Ifx_Crc_reflect(c, 8);
+ }
+
+ for (j = 0x80; j; j >>= 1)
+ {
+ bit = crc & driver->table->crchighbit;
+ crc <<= 1;
+
+ if (c & j)
+ {
+ crc |= 1;
+ }
+
+ if (bit)
+ {
+ crc ^= driver->table->polynom;
+ }
+ }
+ }
+
+ for (i = 0; i < driver->table->order; i++)
+ {
+ bit = crc & driver->table->crchighbit;
+ crc <<= 1;
+
+ if (bit)
+ {
+ crc ^= driver->table->polynom;
+ }
+ }
+
+ if (driver->refout)
+ {
+ crc = Ifx_Crc_reflect(crc, driver->table->order);
+ }
+
+ crc ^= driver->crcxor;
+ crc &= driver->table->crcmask;
+
+ return crc;
+}
+
+
+uint32 Ifx_Crc_bitByBitFast(Ifc_Crc *driver, uint8 *p, uint32 len)
+{
+ // fast bit by bit algorithm without augmented zero bytes.
+ // does not use lookup table, suited for polynom driver->table->orders between 1...32.
+
+ uint32 i, j, c, bit;
+ uint32 crc = driver->crcinit_direct;
+
+ for (i = 0; i < len; i++)
+ {
+ c = (uint32)*p++;
+
+ if (driver->table->refin)
+ {
+ c = Ifx_Crc_reflect(c, 8);
+ }
+
+ for (j = 0x80; j; j >>= 1)
+ {
+ bit = crc & driver->table->crchighbit;
+ crc <<= 1;
+
+ if (c & j)
+ {
+ bit ^= driver->table->crchighbit;
+ }
+
+ if (bit)
+ {
+ crc ^= driver->table->polynom;
+ }
+ }
+ }
+
+ if (driver->refout)
+ {
+ crc = Ifx_Crc_reflect(crc, driver->table->order);
+ }
+
+ crc ^= driver->crcxor;
+ crc &= driver->table->crcmask;
+
+ return crc;
+}
+
+
+#if CRC_ENABLE_DPIPE
+void Ifx_Crc_printTable(Ifc_Crc_Table *table, IfxStdIf_DPipe *io)
+{
+ sint32 i = 0;
+
+ uint32 typeSize;
+
+ if (table->order <= 8)
+ {
+ typeSize = 8;
+ }
+ else if (table->order <= 16)
+ {
+ typeSize = 16;
+ }
+ else
+ {
+ typeSize = 32;
+ }
+
+ IfxStdIf_DPipe_print(io, ENDL "Ifc_Crc_Table%d = {"ENDL, typeSize);
+ IfxStdIf_DPipe_print(io, " .data.order=%d,"ENDL, table->order);
+ IfxStdIf_DPipe_print(io, " .data.polynom=0x%X,"ENDL, table->polynom);
+ IfxStdIf_DPipe_print(io, " .data.refin=%d,"ENDL, table->refin);
+ IfxStdIf_DPipe_print(io, " .data.crchighbit=%d,"ENDL, table->crchighbit);
+ IfxStdIf_DPipe_print(io, " .data.crcmask=0x%X,"ENDL, table->crcmask);
+ IfxStdIf_DPipe_print(io, " .crctab={"ENDL);
+ IfxStdIf_DPipe_print(io, " ");
+
+ while (i < 256)
+ {
+ if (table->order <= 4)
+ {
+ uint8 *crctab = (uint8 *)((uint32)table + sizeof(Ifc_Crc_Table));
+ IfxStdIf_DPipe_print(io, "0x%01X, ", crctab[i]);
+ }
+ else if (table->order <= 8)
+ {
+ uint8 *crctab = (uint8 *)((uint32)table + sizeof(Ifc_Crc_Table));
+ IfxStdIf_DPipe_print(io, "0x%02X, ", crctab[i]);
+ }
+ else if (table->order <= 16)
+ {
+ uint16 *crctab = (uint16 *)((uint32)table + sizeof(Ifc_Crc_Table));
+ IfxStdIf_DPipe_print(io, "0x%04X, ", crctab[i]);
+ }
+ else if (table->order <= 24)
+ {
+ uint32 *crctab = (uint32 *)((uint32)table + sizeof(Ifc_Crc_Table));
+ IfxStdIf_DPipe_print(io, "0x%06X, ", crctab[i]);
+ }
+ else
+ {
+ uint32 *crctab = (uint32 *)((uint32)table + sizeof(Ifc_Crc_Table));
+ IfxStdIf_DPipe_print(io, "0x%08X, ", crctab[i]);
+ }
+
+ i++;
+
+ if ((i % 16) == 0)
+ {
+ IfxStdIf_DPipe_print(io, ENDL " ");
+ }
+ }
+
+ IfxStdIf_DPipe_print(io, " }"ENDL);
+ IfxStdIf_DPipe_print(io, "};"ENDL);
+}
+
+
+boolean Ifx_Crc_Test(Ifc_Crc *driver, uint8 *string, uint32 length, IfxStdIf_DPipe *io)
+{
+ IfxStdIf_DPipe_print(io, ""ENDL);
+ IfxStdIf_DPipe_print(io, "CRC tester v1.1 written on 13/01/2003 by Sven Reifegerste (zorc/reflex)"ENDL);
+ IfxStdIf_DPipe_print(io, "-----------------------------------------------------------------------"ENDL);
+ IfxStdIf_DPipe_print(io, ""ENDL);
+ IfxStdIf_DPipe_print(io, "Parameters:"ENDL);
+ IfxStdIf_DPipe_print(io, ""ENDL);
+ IfxStdIf_DPipe_print(io, " polynom : 0x%x"ENDL, driver->table->polynom);
+ IfxStdIf_DPipe_print(io, " order : %d"ENDL, driver->table->order);
+ IfxStdIf_DPipe_print(io, " crcinit : 0x%x direct, 0x%x nondirect"ENDL, driver->crcinit_direct, driver->crcinit_nondirect);
+ IfxStdIf_DPipe_print(io, " crcxor : 0x%x"ENDL, driver->crcxor);
+ IfxStdIf_DPipe_print(io, " refin : %d"ENDL, driver->table->refin);
+ IfxStdIf_DPipe_print(io, " refout : %d"ENDL, driver->refout);
+ IfxStdIf_DPipe_print(io, ""ENDL);
+// IfxStdIf_DPipe_print(io," data string : '%s' (%d bytes)"ENDL, string, stringLength);
+ IfxStdIf_DPipe_print(io, ""ENDL);
+ IfxStdIf_DPipe_print(io, "Results:"ENDL);
+ IfxStdIf_DPipe_print(io, ""ENDL);
+#if 0
+ IfxCpu_Perf perf;
+ uint32 result;
+
+ IfxCpu_resetAndStartCounters(IfxCpu_CounterMode_normal);
+ result = Ifx_Crc_bitByBit(driver, (uint8 *)string, length);
+ perf = IfxCpu_stopCounters();
+ IfxStdIf_DPipe_print(io, " crc bit by bit : 0x%X, %d cycles"ENDL, result, perf.clock.counter);
+
+ IfxCpu_resetAndStartCounters(IfxCpu_CounterMode_normal);
+ result = Ifx_Crc_bitByBitFast(driver, (uint8 *)string, length);
+ perf = IfxCpu_stopCounters();
+ IfxStdIf_DPipe_print(io, " crc bit by bit fast : 0x%X, %d cycles"ENDL, result, perf.clock.counter);
+
+ IfxCpu_resetAndStartCounters(IfxCpu_CounterMode_normal);
+ result = Ifx_Crc_table(driver, (uint8 *)string, length);
+ perf = IfxCpu_stopCounters();
+ IfxStdIf_DPipe_print(io, " crc table : 0x%X, %d cycles"ENDL, result, perf.clock.counter);
+
+ IfxCpu_resetAndStartCounters(IfxCpu_CounterMode_normal);
+ result = Ifx_Crc_tableFast(driver, (uint8 *)string, length);
+ perf = IfxCpu_stopCounters();
+ IfxStdIf_DPipe_print(io, " crc table fast : 0x%X, %d cycles"ENDL, result, perf.clock.counter);
+
+#endif
+ return TRUE;
+}
+
+
+#endif
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Math/Ifx_Crc.h b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Math/Ifx_Crc.h
new file mode 100644
index 0000000..62a149a
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Math/Ifx_Crc.h
@@ -0,0 +1,130 @@
+/**
+ * \file Ifx_Crc.h
+ * \brief CRC algorithm
+ *
+ * \version disabled
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ * \defgroup library_srvsw_sysse_math_crc CRC
+ * This module implements CRC algorithm
+ * \ingroup library_srvsw_sysse_math
+ *
+ */
+
+#ifndef IFX_CRC_H
+#define IFX_CRC_H 1
+//---------------------------------------------------------------------------
+#include "Cpu/Std/Ifx_Types.h"
+
+#ifndef CRC_ENABLE_DPIPE
+#define CRC_ENABLE_DPIPE 0
+#endif
+
+#if CRC_ENABLE_DPIPE
+#include "IfxStdIf_DPipe.h"
+#endif
+//---------------------------------------------------------------------------
+typedef struct
+{
+ sint32 order;
+ uint32 polynom;
+ sint32 refin;
+ uint32 crchighbit;
+ uint32 crcmask;
+}Ifc_Crc_Table;
+typedef struct
+{
+ Ifc_Crc_Table data; /**< \brief CRC data, must be 1st member of the struct */
+ uint8 crctab[256]; /**< \brief CRC Table, must be 2st member of the struct */
+}Ifc_Crc_Table8;
+
+typedef struct
+{
+ Ifc_Crc_Table data; /**< \brief CRC data, must be 1st member of the struct */
+ uint16 crctab[256]; /**< \brief CRC Table, must be 2st member of the struct */
+}Ifc_Crc_Table16;
+
+typedef struct
+{
+ Ifc_Crc_Table data; /**< \brief CRC data, must be 1st member of the struct */
+ uint32 crctab[256]; /**< \brief CRC Table, must be 2st member of the struct */
+}Ifc_Crc_Table32;
+
+typedef struct
+{
+ uint32 crcxor;
+ sint32 refout;
+
+ uint32 crcinit_direct;
+ uint32 crcinit_nondirect;
+ const Ifc_Crc_Table *table;
+}Ifc_Crc;
+
+/** \addtogroup library_srvsw_sysse_math_crc
+ * \{ */
+/**
+ * \param direct [0,1] specifies the kind of algorithm: 1=direct, no augmented zero bits
+ * \param driver pointer to the crc driver
+ * \param table pointer to crc table
+ * \param direct direct
+ * \param crcinit is the initial CRC value belonging to that algorithm
+ * \param crcxor is the final XOR value
+ * \param refout [0,1] specifies if the CRC will be reflected before XOR
+ * \param table pointer to the table: Ifc_Crc_Table8, Ifc_Crc_Table16, Ifc_Crc_Table32
+ */
+boolean Ifx_Crc_init(Ifc_Crc *driver, const Ifc_Crc_Table *table, sint32 direct, sint32 refout, uint32 crcinit, uint32 crcxor);
+/**
+ * \param table pointer to the crc table
+ * \param order [1..32] is the CRC polynom order, counted without the leading '1' bit
+ * \param polynom is the CRC polynom without leading '1' bit
+ * \param refin [0,1] specifies if a data byte is reflected before processing (UART) or not
+ */
+boolean Ifx_Crc_createTable(Ifc_Crc_Table *table, sint32 order, uint32 polynom, sint32 refin);
+
+#if CRC_ENABLE_DPIPE
+boolean Ifx_Crc_Test(Ifc_Crc *driver, uint8 *string, uint32 length, IfxStdIf_DPipe *io);
+void Ifx_Crc_printTable(Ifc_Crc_Table *table, IfxStdIf_DPipe *io);
+#endif
+uint32 Ifx_Crc_tableFast(Ifc_Crc *driver, uint8 *p, uint32 len);
+uint32 Ifx_Crc_table(Ifc_Crc *driver, uint8 *p, uint32 len);
+uint32 Ifx_Crc_bitByBit(Ifc_Crc *driver, uint8 *p, uint32 len);
+uint32 Ifx_Crc_bitByBitFast(Ifc_Crc *driver, uint8 *p, uint32 len);
+/** \} */
+
+//---------------------------------------------------------------------------
+#endif // IFX_CRC_H
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Math/Ifx_FftF32.c b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Math/Ifx_FftF32.c
new file mode 100644
index 0000000..e057b78
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Math/Ifx_FftF32.c
@@ -0,0 +1,185 @@
+/**
+ * \file Ifx_FftF32.c
+ * \brief Floating-point Fast Fourier Transform
+ *
+ *
+ * \version disabled
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ */
+
+#include "Ifx_FftF32.h"
+#include
+
+//#include "Compiler.h"
+
+cfloat32 *Ifx_FftF32_generateTwiddleFactor(cfloat32 *TF, short nX)
+{
+ int i;
+ double Theta;
+
+ // prepare twiddle coefficients
+ for (i = 0; i < nX / 2; i++)
+ {
+ Theta = 2 * IFX_PI * i / nX;
+
+ TF[i].real = (float32)(cosf(Theta));
+ TF[i].imag = (float32)(-sinf(Theta));
+ }
+
+ return TF;
+}
+
+
+/******************************************************************************/
+unsigned short Ifx_FftF32_reverseBits(unsigned short n, unsigned bits)
+{
+ /* This code is from:
+ * http://graphics.stanford.edu/~seander/bithacks.html
+ * */
+ unsigned long v = n; // 32-bit word to reverse bit order
+
+ // swap odd and even bits
+ v = ((v >> 1) & 0x55555555UL) | ((v & 0x55555555UL) << 1);
+ // swap consecutive pairs
+ v = ((v >> 2) & 0x33333333UL) | ((v & 0x33333333UL) << 2);
+ // swap nibbles ...
+ v = ((v >> 4) & 0x0F0F0F0FUL) | ((v & 0x0F0F0F0FUL) << 4);
+ // swap bytes
+ v = ((v >> 8) & 0x00FF00FFUL) | ((v & 0x00FF00FFUL) << 8);
+ // swap 2-byte long pairs
+ v = (v >> 16) | (v << 16);
+
+ v = v >> (32 - bits);
+ return (unsigned short)v;
+}
+
+
+/******************************************************************************/
+void Ifx_FftF32_radix2DecimationInTime(cfloat32 *R, unsigned long p)
+{
+ /* http://www.engineeringproductivitytools.com/stuff/T0001/PT04.HTM#Head317
+ * */
+ /*Perform in place Ifx_FftF32_radix2DecimationInTime of 2^p points (=size of f)
+ * N.B. The input array f is in bit reversed order! So all the
+ * 'even' input samples are in the 'top' half, all the 'odd'
+ * input samples are in the 'bottom' halR..etc (recursively).
+ */
+ /*Ifx_FftF32_radix2DecimationInTime*/
+ unsigned long Bp, Np, Npx, P, b, k, BaseT, BaseB;
+ cfloat32 top, bot;
+ /*initialise pass parameters*/
+ Bp = 1 << (p - 1); /*No. of blocks*/
+ Np = 2; /*No. of points in each block*/
+
+ /*perform p passes*/
+ for (P = 0; P < p; P++)
+ {
+ /*pass loop*/
+ Npx = Np >> 1; /*No. of butterflies*/
+ BaseT = 0; /*Reset even base index*/
+
+ for (b = 0; b < Bp; b++)
+ {
+ /*block loop*/
+ BaseB = BaseT + Npx; /*calc odd base index*/
+
+ for (k = 0; k < Npx; k++)
+ {
+ //printf("P = %d; b = %d; Np = %d; k = %d\n", P, b, Np, k);
+ /*butterfly loop*/
+ top = Ifx_FftF32_lookUpTwiddleFactor(Np, k);
+ bot = IFX_Cf32_mul(&R[BaseB + k], &top); /*twiddle the odd n results*/
+ top = R[BaseT + k];
+ R[BaseT + k] = IFX_Cf32_add(&top, &bot); /*top subset*/
+ R[BaseB + k] = IFX_Cf32_sub(&top, &bot); /*bottom subset*/
+ } /*butterfly loop*/
+
+ BaseT = BaseT + Np; /*start of next block*/
+ } /*block loop*/
+
+ /*calc parameters for next pass*/
+ Bp = Bp >> 1; /*half as many blocks*/
+ Np = Np << 1; /*twice as many points in each block*/
+ } /*pass loop*/
+} /*Ifx_FftF32_radix2DecimationInTime*/
+
+
+cfloat32 *Ifx_FftF32_radix2(cfloat32 *R, const cfloat32 *X, unsigned short nX)
+{
+ unsigned int logN = 31 - __clz(nX);
+ unsigned short n, k;
+
+ /* Arrange in bit-reversed index */
+ for (n = 0; n < nX; n++)
+ {
+ //k = Ifx_FftF32_reverseBits(n, logN);
+ k = Ifx_FftF32_lookUpReversedBits(n, logN);
+ R[k] = X[n];
+ }
+
+ Ifx_FftF32_radix2DecimationInTime(R, logN);
+
+ return R;
+}
+
+
+cfloat32 *Ifx_FftF32_radix2I(cfloat32 *R, const cfloat32 *X, unsigned short nX)
+{
+ unsigned int logN = 31 - __clz(nX);
+ unsigned short n, k = 0;
+
+ /* Arrange in bit-reversed index, and conjugate the input */
+ for (n = 0; n < nX; n++)
+ {
+ //k = Ifx_FftF32_reverseBits(n, logN);
+ k = Ifx_FftF32_lookUpReversedBits(n, logN);
+ R[k].real = X[n].real;
+ R[k].imag = -X[n].imag;
+ }
+
+ Ifx_FftF32_radix2DecimationInTime(R, logN);
+
+ /* Conjugate the output */
+ for (n = 0; n < nX; n++)
+ {
+ R[n].imag = -R[n].imag;
+ }
+
+ return R;
+}
diff --git a/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Math/Ifx_FftF32.h b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Math/Ifx_FftF32.h
new file mode 100644
index 0000000..68cc65a
--- /dev/null
+++ b/Example/E15_fft_demo/libraries/infineon_libraries/Service/CpuGeneric/SysSe/Math/Ifx_FftF32.h
@@ -0,0 +1,115 @@
+/**
+ * \file Ifx_FftF32.h
+ * \brief Floating-point Fast Fourier Transform
+ * \ingroup library_srvsw_sysse_math_f32_fft
+ *
+ *
+ *
+ * \version disabled
+ * \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
+ *
+ *
+ * IMPORTANT NOTICE
+ *
+ *
+ * Use of this file is subject to the terms of use agreed between (i) you or
+ * the company in which ordinary course of business you are acting and (ii)
+ * Infineon Technologies AG or its licensees. If and as long as no such
+ * terms of use are agreed, use of this file is subject to following:
+
+
+ * Boost Software License - Version 1.0 - August 17th, 2003
+
+ * Permission is hereby granted, free of charge, to any person or
+ * organization obtaining a copy of the software and accompanying
+ * documentation covered by this license (the "Software") to use, reproduce,
+ * display, distribute, execute, and transmit the Software, and to prepare
+ * derivative works of the Software, and to permit third-parties to whom the
+ * Software is furnished to do so, all subject to the following:
+
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer, must
+ * be included in all copies of the Software, in whole or in part, and all
+ * derivative works of the Software, unless such copies or derivative works are
+ * solely in the form of machine-executable object code generated by a source
+ * language processor.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+ *
+ * \defgroup library_srvsw_sysse_math_f32_fft Floating-point FFT
+ * This module implements the Fast Fourier Transform in single precision floating-point
+ * \ingroup library_srvsw_sysse_math_f32
+ *
+ */
+
+#ifndef IFX_FFTF32_H
+#define IFX_FFTF32_H
+
+#include "Ifx_Cf32.h"
+
+/** \brief Maximum FFT resolution (bits).
+ * If redefined, then \ref Ifx_g_FftF32_bitReverseTable and \ref Ifx_g_FftF32_twiddleTable shall be regenerated. */
+#define IFX_FFTF32_MAX_RESOLUTION (14)
+
+/** \brief Maximum FFT length.
+ * If redefined, then \ref Ifx_g_FftF32_bitReverseTable and \ref Ifx_g_FftF32_twiddleTable shall be regenerated. */
+#define IFX_FFTF32_MAX_LENGTH (1U << IFX_FFTF32_MAX_RESOLUTION)
+
+/** \brief Bit reversal table */
+IFX_EXTERN IFX_CONST uint16 Ifx_g_FftF32_bitReverseTable[IFX_FFTF32_MAX_LENGTH];
+
+/** \brief Twiddle factor table */
+IFX_EXTERN IFX_CONST cfloat32 Ifx_g_FftF32_twiddleTable[IFX_FFTF32_MAX_LENGTH / 2];
+
+//----------------------------------------------------------------------------------------
+/** \addtogroup library_srvsw_sysse_math_f32_fft
+ * \{ */
+
+/** \name Transform functions
+ * \{ */
+
+/** \brief Twiddle factor generator */
+IFX_EXTERN cfloat32 *Ifx_FftF32_generateTwiddleFactor(cfloat32 *TF, sint16 nX);
+
+/** \brief Radix-2 Fast-Fourier Transform */
+IFX_EXTERN cfloat32 *Ifx_FftF32_radix2(cfloat32 *R, const cfloat32 *X, uint16 nX);
+
+/** \brief Radix-2 Inverse Fast-Fourier Transform */
+IFX_EXTERN cfloat32 *Ifx_FftF32_radix2I(cfloat32 *R, const cfloat32 *X, uint16 nX);
+
+/** \} */
+//----------------------------------------------------------------------------------------
+/** \name Utility functions
+ * \{ */
+
+/** \brief Lookup from \ref Ifx_g_FftF32_bitReverseTable the bit-reversed \