修复凌瞳高帧率版画质噪点问题
        修复延时函数在多中断时可能异常的问题
This commit is contained in:
SEEKFREE_BUDING
2024-03-09 17:58:13 +08:00
parent 9a30f1ec33
commit 146043d92e
115 changed files with 396 additions and 248 deletions

View File

@@ -54,7 +54,7 @@ IFX_INTERRUPT(stm0_isr, 0, IFX_INTPRIO_STM0_SR0)
stm0_isr_flag = 0;
}
IFX_INTERRUPT(stm1_isr, 0, IFX_INTPRIO_STM1_SR0)
IFX_INTERRUPT(stm1_isr, 1, IFX_INTPRIO_STM1_SR0)
{
interrupt_global_enable(0); // <20><><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>Ƕ<EFBFBD><C7B6>
IfxStm_clearCompareFlag(&MODULE_STM1, IfxStm_Comparator_0);
@@ -68,6 +68,8 @@ IFX_INTERRUPT(stm1_isr, 0, IFX_INTPRIO_STM1_SR0)
//-------------------------------------------------------------------------------------------------------------------
void system_delay_10ns (uint32 time)
{
uint32 interrupt_global_state;
IfxStm_Index stm_index;
stm_index = (IfxStm_Index)IfxCpu_getCoreId();
@@ -83,15 +85,19 @@ void system_delay_10ns (uint32 time)
case IfxStm_Index_0:
{
Ifx_STM *stm_sfr = &MODULE_STM0;
stm_sfr->CMP[0].U = stm_sfr->TIM0.U + time;
stm0_isr_flag = 1;
interrupt_global_state = interrupt_global_disable(); // <20>ر<EFBFBD>ȫ<EFBFBD><C8AB><EFBFBD>ж<EFBFBD>
stm_sfr->CMP[0].U = stm_sfr->TIM0.U + time;
interrupt_global_enable(interrupt_global_state); // <20><><EFBFBD><EFBFBD>ȫ<EFBFBD><C8AB><EFBFBD>ж<EFBFBD>
while(stm0_isr_flag);
}break;
case IfxStm_Index_1:
{
Ifx_STM *stm_sfr = &MODULE_STM1;
stm_sfr->CMP[0].U = stm_sfr->TIM0.U + time;
stm1_isr_flag = 1;
interrupt_global_state = interrupt_global_disable(); // <20>ر<EFBFBD>ȫ<EFBFBD><C8AB><EFBFBD>ж<EFBFBD>
stm_sfr->CMP[0].U = stm_sfr->TIM0.U + time;
interrupt_global_enable(interrupt_global_state); // <20><><EFBFBD><EFBFBD>ȫ<EFBFBD><C8AB><EFBFBD>ж<EFBFBD>
while(stm1_isr_flag);
}break;
case IfxStm_Index_none: break;

View File

@@ -41,7 +41,7 @@
typedef struct
{
Ifx_DMA_CH linked_list[8]; // DMA<4D><41><EFBFBD><EFBFBD>
Ifx_DMA_CH linked_list[10]; // DMA<4D><41><EFBFBD><EFBFBD>
IfxDma_Dma_Channel channel; // DMAͨ<41><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
}DMA_LINK;
@@ -67,7 +67,7 @@ IFX_ALIGN(256) DMA_LINK dma_link_list;
// ʹ<><CAB9>ʾ<EFBFBD><CABE> dma_init(MT9V03X_DMA_CH, MT9V03X_DATA_ADD, mt9v03x_image[0], MT9V03X_PCLK_PIN, EXTI_TRIGGER_RISING, MT9V03X_IMAGE_SIZE);
// <20><>ע<EFBFBD><D7A2>Ϣ
//-------------------------------------------------------------------------------------------------------------------
uint8 dma_init (IfxDma_ChannelId dma_ch, uint8 *source_addr, uint8 *destination_addr, exti_pin_enum exti_pin, exti_trigger_enum trigger, uint16 dma_count)
uint8 dma_init (IfxDma_ChannelId dma_ch, uint8 *source_addr, uint8 *destination_addr, exti_pin_enum exti_pin, exti_trigger_enum trigger, uint32 dma_count)
{
IfxDma_Dma_Channel dmaChn;
@@ -83,7 +83,7 @@ uint8 dma_init (IfxDma_ChannelId dma_ch, uint8 *source_addr, uint8 *destination_
IfxDma_Dma_initChannelConfig(&cfg, &dma);
uint8 list_num, i;
uint16 single_channel_dma_count;
uint32 single_channel_dma_count;
zf_assert(!(dma_count % 8)); // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ8<CEAA>ı<EFBFBD><C4B1><EFBFBD>
@@ -100,7 +100,7 @@ uint8 dma_init (IfxDma_ChannelId dma_ch, uint8 *source_addr, uint8 *destination_
break;
}
list_num++;
if(list_num > 8)
if(list_num > 10)
{
zf_assert(FALSE);
}
@@ -141,7 +141,7 @@ uint8 dma_init (IfxDma_ChannelId dma_ch, uint8 *source_addr, uint8 *destination_
cfg.destinationAddress = IFXCPU_GLB_ADDR_DSPR(IfxCpu_getCoreId(), destination_addr);
cfg.transferCount = single_channel_dma_count;
cfg.transferCount = (uint16)single_channel_dma_count;
IfxDma_Dma_initChannel(&dmaChn, &cfg);
@@ -153,13 +153,13 @@ uint8 dma_init (IfxDma_ChannelId dma_ch, uint8 *source_addr, uint8 *destination_
cfg.destinationAddress = IFXCPU_GLB_ADDR_DSPR(IfxCpu_getCoreId(), destination_addr + single_channel_dma_count * i);
if(i == (list_num - 1))
{
cfg.shadowAddress = IFXCPU_GLB_ADDR_DSPR(IfxCpu_getCoreId(), (unsigned)&dma_link_list.linked_list[0]);
cfg.shadowAddress = IFXCPU_GLB_ADDR_DSPR(IfxCpu_getCoreId(), (uint32)&dma_link_list.linked_list[0]);
}
else
{
cfg.shadowAddress = IFXCPU_GLB_ADDR_DSPR(IfxCpu_getCoreId(), (unsigned)&dma_link_list.linked_list[i+1]);
cfg.shadowAddress = IFXCPU_GLB_ADDR_DSPR(IfxCpu_getCoreId(), (uint32)&dma_link_list.linked_list[i+1]);
}
cfg.transferCount = single_channel_dma_count;
cfg.transferCount = (uint16)single_channel_dma_count;
IfxDma_Dma_initLinkedListEntry((void *)&dma_link_list.linked_list[i], &cfg);
i++;

View File

@@ -45,7 +45,7 @@
#define dma_set_destination(dma_ch, destination_addr) (IfxDma_setChannelDestinationAddress(&MODULE_DMA, (dma_ch), (void *)IFXCPU_GLB_ADDR_DSPR(IfxCpu_getCoreId(), (destination_addr))))
//====================================================DMA <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>====================================================
uint8 dma_init (IfxDma_ChannelId dma_ch, uint8 *source_addr, uint8 *destination_addr, exti_pin_enum eru_pin, exti_trigger_enum trigger, uint16 dma_count);
uint8 dma_init (IfxDma_ChannelId dma_ch, uint8 *source_addr, uint8 *destination_addr, exti_pin_enum eru_pin, exti_trigger_enum trigger, uint32 dma_count);
void dma_disable (IfxDma_ChannelId dma_ch);
void dma_enable (IfxDma_ChannelId dma_ch);
//====================================================DMA <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>====================================================