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https://gitee.com/seekfree/TC264_Library.git
synced 2026-06-04 03:32:56 +00:00
V3.2.11
修复凌瞳高帧率版画质噪点问题
修复延时函数在多中断时可能异常的问题
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@@ -54,7 +54,7 @@ IFX_INTERRUPT(stm0_isr, 0, IFX_INTPRIO_STM0_SR0)
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stm0_isr_flag = 0;
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}
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IFX_INTERRUPT(stm1_isr, 0, IFX_INTPRIO_STM1_SR0)
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IFX_INTERRUPT(stm1_isr, 1, IFX_INTPRIO_STM1_SR0)
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{
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interrupt_global_enable(0); // <20><><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>Ƕ<EFBFBD><C7B6>
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IfxStm_clearCompareFlag(&MODULE_STM1, IfxStm_Comparator_0);
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@@ -68,6 +68,8 @@ IFX_INTERRUPT(stm1_isr, 0, IFX_INTPRIO_STM1_SR0)
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//-------------------------------------------------------------------------------------------------------------------
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void system_delay_10ns (uint32 time)
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{
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uint32 interrupt_global_state;
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IfxStm_Index stm_index;
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stm_index = (IfxStm_Index)IfxCpu_getCoreId();
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@@ -83,15 +85,19 @@ void system_delay_10ns (uint32 time)
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case IfxStm_Index_0:
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{
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Ifx_STM *stm_sfr = &MODULE_STM0;
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stm_sfr->CMP[0].U = stm_sfr->TIM0.U + time;
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stm0_isr_flag = 1;
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interrupt_global_state = interrupt_global_disable(); // <20>ر<EFBFBD>ȫ<EFBFBD><C8AB><EFBFBD>ж<EFBFBD>
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stm_sfr->CMP[0].U = stm_sfr->TIM0.U + time;
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interrupt_global_enable(interrupt_global_state); // <20><><EFBFBD><EFBFBD>ȫ<EFBFBD><C8AB><EFBFBD>ж<EFBFBD>
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while(stm0_isr_flag);
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}break;
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case IfxStm_Index_1:
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{
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Ifx_STM *stm_sfr = &MODULE_STM1;
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stm_sfr->CMP[0].U = stm_sfr->TIM0.U + time;
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stm1_isr_flag = 1;
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interrupt_global_state = interrupt_global_disable(); // <20>ر<EFBFBD>ȫ<EFBFBD><C8AB><EFBFBD>ж<EFBFBD>
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stm_sfr->CMP[0].U = stm_sfr->TIM0.U + time;
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interrupt_global_enable(interrupt_global_state); // <20><><EFBFBD><EFBFBD>ȫ<EFBFBD><C8AB><EFBFBD>ж<EFBFBD>
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while(stm1_isr_flag);
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}break;
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case IfxStm_Index_none: break;
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@@ -41,7 +41,7 @@
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typedef struct
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{
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Ifx_DMA_CH linked_list[8]; // DMA<4D><41><EFBFBD><EFBFBD>
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Ifx_DMA_CH linked_list[10]; // DMA<4D><41><EFBFBD><EFBFBD>
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IfxDma_Dma_Channel channel; // DMAͨ<41><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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}DMA_LINK;
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@@ -67,7 +67,7 @@ IFX_ALIGN(256) DMA_LINK dma_link_list;
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// ʹ<><CAB9>ʾ<EFBFBD><CABE> dma_init(MT9V03X_DMA_CH, MT9V03X_DATA_ADD, mt9v03x_image[0], MT9V03X_PCLK_PIN, EXTI_TRIGGER_RISING, MT9V03X_IMAGE_SIZE);
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// <20><>ע<EFBFBD><D7A2>Ϣ
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//-------------------------------------------------------------------------------------------------------------------
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uint8 dma_init (IfxDma_ChannelId dma_ch, uint8 *source_addr, uint8 *destination_addr, exti_pin_enum exti_pin, exti_trigger_enum trigger, uint16 dma_count)
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uint8 dma_init (IfxDma_ChannelId dma_ch, uint8 *source_addr, uint8 *destination_addr, exti_pin_enum exti_pin, exti_trigger_enum trigger, uint32 dma_count)
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{
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IfxDma_Dma_Channel dmaChn;
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@@ -83,7 +83,7 @@ uint8 dma_init (IfxDma_ChannelId dma_ch, uint8 *source_addr, uint8 *destination_
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IfxDma_Dma_initChannelConfig(&cfg, &dma);
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uint8 list_num, i;
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uint16 single_channel_dma_count;
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uint32 single_channel_dma_count;
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zf_assert(!(dma_count % 8)); // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ8<CEAA>ı<EFBFBD><C4B1><EFBFBD>
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@@ -100,7 +100,7 @@ uint8 dma_init (IfxDma_ChannelId dma_ch, uint8 *source_addr, uint8 *destination_
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break;
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}
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list_num++;
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if(list_num > 8)
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if(list_num > 10)
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{
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zf_assert(FALSE);
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}
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@@ -141,7 +141,7 @@ uint8 dma_init (IfxDma_ChannelId dma_ch, uint8 *source_addr, uint8 *destination_
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cfg.destinationAddress = IFXCPU_GLB_ADDR_DSPR(IfxCpu_getCoreId(), destination_addr);
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cfg.transferCount = single_channel_dma_count;
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cfg.transferCount = (uint16)single_channel_dma_count;
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IfxDma_Dma_initChannel(&dmaChn, &cfg);
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@@ -153,13 +153,13 @@ uint8 dma_init (IfxDma_ChannelId dma_ch, uint8 *source_addr, uint8 *destination_
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cfg.destinationAddress = IFXCPU_GLB_ADDR_DSPR(IfxCpu_getCoreId(), destination_addr + single_channel_dma_count * i);
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if(i == (list_num - 1))
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{
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cfg.shadowAddress = IFXCPU_GLB_ADDR_DSPR(IfxCpu_getCoreId(), (unsigned)&dma_link_list.linked_list[0]);
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cfg.shadowAddress = IFXCPU_GLB_ADDR_DSPR(IfxCpu_getCoreId(), (uint32)&dma_link_list.linked_list[0]);
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}
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else
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{
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cfg.shadowAddress = IFXCPU_GLB_ADDR_DSPR(IfxCpu_getCoreId(), (unsigned)&dma_link_list.linked_list[i+1]);
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cfg.shadowAddress = IFXCPU_GLB_ADDR_DSPR(IfxCpu_getCoreId(), (uint32)&dma_link_list.linked_list[i+1]);
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}
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cfg.transferCount = single_channel_dma_count;
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cfg.transferCount = (uint16)single_channel_dma_count;
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IfxDma_Dma_initLinkedListEntry((void *)&dma_link_list.linked_list[i], &cfg);
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i++;
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@@ -45,7 +45,7 @@
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#define dma_set_destination(dma_ch, destination_addr) (IfxDma_setChannelDestinationAddress(&MODULE_DMA, (dma_ch), (void *)IFXCPU_GLB_ADDR_DSPR(IfxCpu_getCoreId(), (destination_addr))))
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//====================================================DMA <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>====================================================
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uint8 dma_init (IfxDma_ChannelId dma_ch, uint8 *source_addr, uint8 *destination_addr, exti_pin_enum eru_pin, exti_trigger_enum trigger, uint16 dma_count);
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uint8 dma_init (IfxDma_ChannelId dma_ch, uint8 *source_addr, uint8 *destination_addr, exti_pin_enum eru_pin, exti_trigger_enum trigger, uint32 dma_count);
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void dma_disable (IfxDma_ChannelId dma_ch);
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void dma_enable (IfxDma_ChannelId dma_ch);
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//====================================================DMA <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>====================================================
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